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authorJoachim Fenkes <fenkes@de.ibm.com>2017-06-17 17:16:32 -0500
committerDaniel M. Crowell <dcrowell@us.ibm.com>2017-06-23 10:47:26 -0400
commit3dfe06eda5ea7968fa43276292a443fd94cc4696 (patch)
treeaf82a8da5cf3517cd4aeaa6bc388d41307dbf0cf /src/import/chips/p9/common
parent6a207fa8c5da3075d6674bfe62682c032d546ec5 (diff)
downloadtalos-hostboot-3dfe06eda5ea7968fa43276292a443fd94cc4696.tar.gz
talos-hostboot-3dfe06eda5ea7968fa43276292a443fd94cc4696.zip
Move p9n2 SCOM headers into base chip include dir, mirror to PPE/HB
Change-Id: I5a4b929fad4aa954ad413eb73861ab1e53135360 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42026 Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Dev-Ready: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Benjamin Gass <bgass@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42024 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/common')
-rw-r--r--src/import/chips/p9/common/include/p9n2_mc_scom_addresses.H42059
-rw-r--r--src/import/chips/p9/common/include/p9n2_mc_scom_addresses_fld.H15145
-rw-r--r--src/import/chips/p9/common/include/p9n2_misc_scom_addresses.H14845
-rw-r--r--src/import/chips/p9/common/include/p9n2_misc_scom_addresses_fld.H50340
-rw-r--r--src/import/chips/p9/common/include/p9n2_obus_scom_addresses.H12245
-rw-r--r--src/import/chips/p9/common/include/p9n2_obus_scom_addresses_fld.H10693
-rw-r--r--src/import/chips/p9/common/include/p9n2_perv_scom_addresses.H18252
-rw-r--r--src/import/chips/p9/common/include/p9n2_perv_scom_addresses_fld.H5855
-rw-r--r--src/import/chips/p9/common/include/p9n2_quad_scom_addresses.H34970
-rw-r--r--src/import/chips/p9/common/include/p9n2_quad_scom_addresses_fld.H11158
-rw-r--r--src/import/chips/p9/common/include/p9n2_xbus_scom_addresses.H18542
-rw-r--r--src/import/chips/p9/common/include/p9n2_xbus_scom_addresses_fld.H18456
12 files changed, 252560 insertions, 0 deletions
diff --git a/src/import/chips/p9/common/include/p9n2_mc_scom_addresses.H b/src/import/chips/p9/common/include/p9n2_mc_scom_addresses.H
new file mode 100644
index 000000000..1f8430bc8
--- /dev/null
+++ b/src/import/chips/p9/common/include/p9n2_mc_scom_addresses.H
@@ -0,0 +1,42059 @@
+/* IBM_PROLOG_BEGIN_TAG */
+/* This is an automatically generated prolog. */
+/* */
+/* $Source: src/import/chips/p9/common/include/p9n2_mc_scom_addresses.H $ */
+/* */
+/* OpenPOWER HostBoot Project */
+/* */
+/* Contributors Listed Below - COPYRIGHT 2017 */
+/* [+] International Business Machines Corp. */
+/* */
+/* */
+/* Licensed under the Apache License, Version 2.0 (the "License"); */
+/* you may not use this file except in compliance with the License. */
+/* You may obtain a copy of the License at */
+/* */
+/* http://www.apache.org/licenses/LICENSE-2.0 */
+/* */
+/* Unless required by applicable law or agreed to in writing, software */
+/* distributed under the License is distributed on an "AS IS" BASIS, */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */
+/* implied. See the License for the specific language governing */
+/* permissions and limitations under the License. */
+/* */
+/* IBM_PROLOG_END_TAG */
+///
+/// @file p9_mc_scom_addresses.H
+/// @brief Defines constants for scom addresses
+///
+// *HWP HWP Owner: Ben Gass <bgass@us.ibm.com>
+// *HWP FW Owner: Thi Tran <thi@us.ibm.com>
+// *HWP Team: SOA
+// *HWP Level: 1
+// *HWP Consumed by: FSP:HB:HS:OCC:SBE:CME:SGPE:PGPE:FPPE:IPPE
+
+/*---------------------------------------------------------------
+ *
+ *---------------------------------------------------------------
+ *
+ *---------------------------------------------------------------
+ */
+
+
+#ifndef __P9N2_MC_SCOM_ADDRESSES_H
+#define __P9N2_MC_SCOM_ADDRESSES_H
+
+#include <stdint.h>
+
+static const uint64_t P9N2_MCA_0_WREITE_AACR = 0x07010A29ull;
+
+static const uint64_t P9N2_MCA_1_WREITE_AACR = 0x07010A69ull;
+
+static const uint64_t P9N2_MCA_2_WREITE_AACR = 0x07010AA9ull;
+
+static const uint64_t P9N2_MCA_3_WREITE_AACR = 0x07010AE9ull;
+
+static const uint64_t P9N2_MCA_4_WREITE_AACR = 0x08010A29ull;
+
+static const uint64_t P9N2_MCA_5_WREITE_AACR = 0x08010A69ull;
+
+static const uint64_t P9N2_MCA_6_WREITE_AACR = 0x08010AA9ull;
+
+static const uint64_t P9N2_MCA_7_WREITE_AACR = 0x08010AE9ull;
+
+static const uint64_t P9N2_MCA_WREITE_AACR = 0x07010A29ull;
+
+static const uint64_t P9N2_MCS_0_PORT02_AACR = 0x0501082Cull;
+
+static const uint64_t P9N2_MCS_1_PORT02_AACR = 0x050108ACull;
+
+static const uint64_t P9N2_MCS_2_PORT02_AACR = 0x0301082Cull;
+
+static const uint64_t P9N2_MCS_3_PORT02_AACR = 0x030108ACull;
+
+static const uint64_t P9N2_MCS_PORT02_AACR = 0x0501082Cull;
+
+
+static const uint64_t P9N2_MCA_AADR = 0x07010A2Aull;
+
+static const uint64_t P9N2_MCA_0_AADR = 0x07010A2Aull;
+
+static const uint64_t P9N2_MCA_1_AADR = 0x07010A6Aull;
+
+static const uint64_t P9N2_MCA_2_AADR = 0x07010AAAull;
+
+static const uint64_t P9N2_MCA_3_AADR = 0x07010AEAull;
+
+static const uint64_t P9N2_MCA_4_AADR = 0x08010A2Aull;
+
+static const uint64_t P9N2_MCA_5_AADR = 0x08010A6Aull;
+
+static const uint64_t P9N2_MCA_6_AADR = 0x08010AAAull;
+
+static const uint64_t P9N2_MCA_7_AADR = 0x08010AEAull;
+
+static const uint64_t P9N2_MCS_0_PORT02_AADR = 0x0501082Dull;
+
+static const uint64_t P9N2_MCS_1_PORT02_AADR = 0x050108ADull;
+
+static const uint64_t P9N2_MCS_2_PORT02_AADR = 0x0301082Dull;
+
+static const uint64_t P9N2_MCS_3_PORT02_AADR = 0x030108ADull;
+
+static const uint64_t P9N2_MCS_PORT02_AADR = 0x0501082Dull;
+
+
+static const uint64_t P9N2_MCA_AAER = 0x07010A2Bull;
+
+static const uint64_t P9N2_MCA_0_AAER = 0x07010A2Bull;
+
+static const uint64_t P9N2_MCA_1_AAER = 0x07010A6Bull;
+
+static const uint64_t P9N2_MCA_2_AAER = 0x07010AABull;
+
+static const uint64_t P9N2_MCA_3_AAER = 0x07010AEBull;
+
+static const uint64_t P9N2_MCA_4_AAER = 0x08010A2Bull;
+
+static const uint64_t P9N2_MCA_5_AAER = 0x08010A6Bull;
+
+static const uint64_t P9N2_MCA_6_AAER = 0x08010AABull;
+
+static const uint64_t P9N2_MCA_7_AAER = 0x08010AEBull;
+
+static const uint64_t P9N2_MCS_0_PORT02_AAER = 0x0501082Eull;
+
+static const uint64_t P9N2_MCS_1_PORT02_AAER = 0x050108AEull;
+
+static const uint64_t P9N2_MCS_2_PORT02_AAER = 0x0301082Eull;
+
+static const uint64_t P9N2_MCS_3_PORT02_AAER = 0x030108AEull;
+
+static const uint64_t P9N2_MCS_PORT02_AAER = 0x0501082Eull;
+
+
+static const uint64_t P9N2_MCA_ACTION0 = 0x07010A06ull;
+
+static const uint64_t P9N2_MCA_0_ACTION0 = 0x07010A06ull;
+
+static const uint64_t P9N2_MCA_1_ACTION0 = 0x07010A46ull;
+
+static const uint64_t P9N2_MCA_2_ACTION0 = 0x07010A86ull;
+
+static const uint64_t P9N2_MCA_3_ACTION0 = 0x07010AC6ull;
+
+static const uint64_t P9N2_MCA_4_ACTION0 = 0x08010A06ull;
+
+static const uint64_t P9N2_MCA_5_ACTION0 = 0x08010A46ull;
+
+static const uint64_t P9N2_MCA_6_ACTION0 = 0x08010A86ull;
+
+static const uint64_t P9N2_MCA_7_ACTION0 = 0x08010AC6ull;
+
+
+static const uint64_t P9N2_MCA_ACTION1 = 0x07010A07ull;
+
+static const uint64_t P9N2_MCA_0_ACTION1 = 0x07010A07ull;
+
+static const uint64_t P9N2_MCA_1_ACTION1 = 0x07010A47ull;
+
+static const uint64_t P9N2_MCA_2_ACTION1 = 0x07010A87ull;
+
+static const uint64_t P9N2_MCA_3_ACTION1 = 0x07010AC7ull;
+
+static const uint64_t P9N2_MCA_4_ACTION1 = 0x08010A07ull;
+
+static const uint64_t P9N2_MCA_5_ACTION1 = 0x08010A47ull;
+
+static const uint64_t P9N2_MCA_6_ACTION1 = 0x08010A87ull;
+
+static const uint64_t P9N2_MCA_7_ACTION1 = 0x08010AC7ull;
+
+
+static const uint64_t P9N2_MCA_ADDR_TRAP_REG = 0x07010003ull;
+
+static const uint64_t P9N2_MCA_0_ADDR_TRAP_REG = 0x07010003ull;
+
+static const uint64_t P9N2_MCA_4_ADDR_TRAP_REG = 0x08010003ull;
+
+
+static const uint64_t P9N2_MCA_ATOMIC_LOCK_MASK_LATCH_REG = 0x07010007ull;
+
+static const uint64_t P9N2_MCA_0_ATOMIC_LOCK_MASK_LATCH_REG = 0x07010007ull;
+
+static const uint64_t P9N2_MCA_4_ATOMIC_LOCK_MASK_LATCH_REG = 0x08010007ull;
+
+
+static const uint64_t P9N2_MCBIST_CCSARRERRINJQ = 0x070123DEull;
+
+static const uint64_t P9N2_MCBIST_0_CCSARRERRINJQ = 0x070123DEull;
+
+static const uint64_t P9N2_MCBIST_1_CCSARRERRINJQ = 0x080123DEull;
+
+
+static const uint64_t P9N2_MCBIST_CCS_CNTLQ = 0x070123A5ull;
+
+static const uint64_t P9N2_MCBIST_0_CCS_CNTLQ = 0x070123A5ull;
+
+static const uint64_t P9N2_MCBIST_1_CCS_CNTLQ = 0x080123A5ull;
+
+
+static const uint64_t P9N2_MCBIST_CCS_FIXED_DATA0Q = 0x070123E5ull;
+
+static const uint64_t P9N2_MCBIST_0_CCS_FIXED_DATA0Q = 0x070123E5ull;
+
+static const uint64_t P9N2_MCBIST_1_CCS_FIXED_DATA0Q = 0x080123E5ull;
+
+
+static const uint64_t P9N2_MCBIST_CCS_FIXED_DATA1Q = 0x070123E6ull;
+
+static const uint64_t P9N2_MCBIST_0_CCS_FIXED_DATA1Q = 0x070123E6ull;
+
+static const uint64_t P9N2_MCBIST_1_CCS_FIXED_DATA1Q = 0x080123E6ull;
+
+
+static const uint64_t P9N2_MCBIST_CCS_INST_ARR0_00 = 0x07012315ull;
+
+static const uint64_t P9N2_MCBIST_0_CCS_INST_ARR0_00 = 0x07012315ull;
+
+static const uint64_t P9N2_MCBIST_1_CCS_INST_ARR0_00 = 0x08012315ull;
+
+
+static const uint64_t P9N2_MCBIST_CCS_INST_ARR0_01 = 0x07012316ull;
+
+static const uint64_t P9N2_MCBIST_0_CCS_INST_ARR0_01 = 0x07012316ull;
+
+static const uint64_t P9N2_MCBIST_1_CCS_INST_ARR0_01 = 0x08012316ull;
+
+
+static const uint64_t P9N2_MCBIST_CCS_INST_ARR0_02 = 0x07012317ull;
+
+static const uint64_t P9N2_MCBIST_0_CCS_INST_ARR0_02 = 0x07012317ull;
+
+static const uint64_t P9N2_MCBIST_1_CCS_INST_ARR0_02 = 0x08012317ull;
+
+
+static const uint64_t P9N2_MCBIST_CCS_INST_ARR0_03 = 0x07012318ull;
+
+static const uint64_t P9N2_MCBIST_0_CCS_INST_ARR0_03 = 0x07012318ull;
+
+static const uint64_t P9N2_MCBIST_1_CCS_INST_ARR0_03 = 0x08012318ull;
+
+
+static const uint64_t P9N2_MCBIST_CCS_INST_ARR0_04 = 0x07012319ull;
+
+static const uint64_t P9N2_MCBIST_0_CCS_INST_ARR0_04 = 0x07012319ull;
+
+static const uint64_t P9N2_MCBIST_1_CCS_INST_ARR0_04 = 0x08012319ull;
+
+
+static const uint64_t P9N2_MCBIST_CCS_INST_ARR0_05 = 0x0701231Aull;
+
+static const uint64_t P9N2_MCBIST_0_CCS_INST_ARR0_05 = 0x0701231Aull;
+
+static const uint64_t P9N2_MCBIST_1_CCS_INST_ARR0_05 = 0x0801231Aull;
+
+
+static const uint64_t P9N2_MCBIST_CCS_INST_ARR0_06 = 0x0701231Bull;
+
+static const uint64_t P9N2_MCBIST_0_CCS_INST_ARR0_06 = 0x0701231Bull;
+
+static const uint64_t P9N2_MCBIST_1_CCS_INST_ARR0_06 = 0x0801231Bull;
+
+
+static const uint64_t P9N2_MCBIST_CCS_INST_ARR0_07 = 0x0701231Cull;
+
+static const uint64_t P9N2_MCBIST_0_CCS_INST_ARR0_07 = 0x0701231Cull;
+
+static const uint64_t P9N2_MCBIST_1_CCS_INST_ARR0_07 = 0x0801231Cull;
+
+
+static const uint64_t P9N2_MCBIST_CCS_INST_ARR0_08 = 0x0701231Dull;
+
+static const uint64_t P9N2_MCBIST_0_CCS_INST_ARR0_08 = 0x0701231Dull;
+
+static const uint64_t P9N2_MCBIST_1_CCS_INST_ARR0_08 = 0x0801231Dull;
+
+
+static const uint64_t P9N2_MCBIST_CCS_INST_ARR0_09 = 0x0701231Eull;
+
+static const uint64_t P9N2_MCBIST_0_CCS_INST_ARR0_09 = 0x0701231Eull;
+
+static const uint64_t P9N2_MCBIST_1_CCS_INST_ARR0_09 = 0x0801231Eull;
+
+
+static const uint64_t P9N2_MCBIST_CCS_INST_ARR0_10 = 0x0701231Full;
+
+static const uint64_t P9N2_MCBIST_0_CCS_INST_ARR0_10 = 0x0701231Full;
+
+static const uint64_t P9N2_MCBIST_1_CCS_INST_ARR0_10 = 0x0801231Full;
+
+
+static const uint64_t P9N2_MCBIST_CCS_INST_ARR0_11 = 0x07012320ull;
+
+static const uint64_t P9N2_MCBIST_0_CCS_INST_ARR0_11 = 0x07012320ull;
+
+static const uint64_t P9N2_MCBIST_1_CCS_INST_ARR0_11 = 0x08012320ull;
+
+
+static const uint64_t P9N2_MCBIST_CCS_INST_ARR0_12 = 0x07012321ull;
+
+static const uint64_t P9N2_MCBIST_0_CCS_INST_ARR0_12 = 0x07012321ull;
+
+static const uint64_t P9N2_MCBIST_1_CCS_INST_ARR0_12 = 0x08012321ull;
+
+
+static const uint64_t P9N2_MCBIST_CCS_INST_ARR0_13 = 0x07012322ull;
+
+static const uint64_t P9N2_MCBIST_0_CCS_INST_ARR0_13 = 0x07012322ull;
+
+static const uint64_t P9N2_MCBIST_1_CCS_INST_ARR0_13 = 0x08012322ull;
+
+
+static const uint64_t P9N2_MCBIST_CCS_INST_ARR0_14 = 0x07012323ull;
+
+static const uint64_t P9N2_MCBIST_0_CCS_INST_ARR0_14 = 0x07012323ull;
+
+static const uint64_t P9N2_MCBIST_1_CCS_INST_ARR0_14 = 0x08012323ull;
+
+
+static const uint64_t P9N2_MCBIST_CCS_INST_ARR0_15 = 0x07012324ull;
+
+static const uint64_t P9N2_MCBIST_0_CCS_INST_ARR0_15 = 0x07012324ull;
+
+static const uint64_t P9N2_MCBIST_1_CCS_INST_ARR0_15 = 0x08012324ull;
+
+
+static const uint64_t P9N2_MCBIST_CCS_INST_ARR0_16 = 0x07012325ull;
+
+static const uint64_t P9N2_MCBIST_0_CCS_INST_ARR0_16 = 0x07012325ull;
+
+static const uint64_t P9N2_MCBIST_1_CCS_INST_ARR0_16 = 0x08012325ull;
+
+
+static const uint64_t P9N2_MCBIST_CCS_INST_ARR0_17 = 0x07012326ull;
+
+static const uint64_t P9N2_MCBIST_0_CCS_INST_ARR0_17 = 0x07012326ull;
+
+static const uint64_t P9N2_MCBIST_1_CCS_INST_ARR0_17 = 0x08012326ull;
+
+
+static const uint64_t P9N2_MCBIST_CCS_INST_ARR0_18 = 0x07012327ull;
+
+static const uint64_t P9N2_MCBIST_0_CCS_INST_ARR0_18 = 0x07012327ull;
+
+static const uint64_t P9N2_MCBIST_1_CCS_INST_ARR0_18 = 0x08012327ull;
+
+
+static const uint64_t P9N2_MCBIST_CCS_INST_ARR0_19 = 0x07012328ull;
+
+static const uint64_t P9N2_MCBIST_0_CCS_INST_ARR0_19 = 0x07012328ull;
+
+static const uint64_t P9N2_MCBIST_1_CCS_INST_ARR0_19 = 0x08012328ull;
+
+
+static const uint64_t P9N2_MCBIST_CCS_INST_ARR0_20 = 0x07012329ull;
+
+static const uint64_t P9N2_MCBIST_0_CCS_INST_ARR0_20 = 0x07012329ull;
+
+static const uint64_t P9N2_MCBIST_1_CCS_INST_ARR0_20 = 0x08012329ull;
+
+
+static const uint64_t P9N2_MCBIST_CCS_INST_ARR0_21 = 0x0701232Aull;
+
+static const uint64_t P9N2_MCBIST_0_CCS_INST_ARR0_21 = 0x0701232Aull;
+
+static const uint64_t P9N2_MCBIST_1_CCS_INST_ARR0_21 = 0x0801232Aull;
+
+
+static const uint64_t P9N2_MCBIST_CCS_INST_ARR0_22 = 0x0701232Bull;
+
+static const uint64_t P9N2_MCBIST_0_CCS_INST_ARR0_22 = 0x0701232Bull;
+
+static const uint64_t P9N2_MCBIST_1_CCS_INST_ARR0_22 = 0x0801232Bull;
+
+
+static const uint64_t P9N2_MCBIST_CCS_INST_ARR0_23 = 0x0701232Cull;
+
+static const uint64_t P9N2_MCBIST_0_CCS_INST_ARR0_23 = 0x0701232Cull;
+
+static const uint64_t P9N2_MCBIST_1_CCS_INST_ARR0_23 = 0x0801232Cull;
+
+
+static const uint64_t P9N2_MCBIST_CCS_INST_ARR0_24 = 0x0701232Dull;
+
+static const uint64_t P9N2_MCBIST_0_CCS_INST_ARR0_24 = 0x0701232Dull;
+
+static const uint64_t P9N2_MCBIST_1_CCS_INST_ARR0_24 = 0x0801232Dull;
+
+
+static const uint64_t P9N2_MCBIST_CCS_INST_ARR0_25 = 0x0701232Eull;
+
+static const uint64_t P9N2_MCBIST_0_CCS_INST_ARR0_25 = 0x0701232Eull;
+
+static const uint64_t P9N2_MCBIST_1_CCS_INST_ARR0_25 = 0x0801232Eull;
+
+
+static const uint64_t P9N2_MCBIST_CCS_INST_ARR0_26 = 0x0701232Full;
+
+static const uint64_t P9N2_MCBIST_0_CCS_INST_ARR0_26 = 0x0701232Full;
+
+static const uint64_t P9N2_MCBIST_1_CCS_INST_ARR0_26 = 0x0801232Full;
+
+
+static const uint64_t P9N2_MCBIST_CCS_INST_ARR0_27 = 0x07012330ull;
+
+static const uint64_t P9N2_MCBIST_0_CCS_INST_ARR0_27 = 0x07012330ull;
+
+static const uint64_t P9N2_MCBIST_1_CCS_INST_ARR0_27 = 0x08012330ull;
+
+
+static const uint64_t P9N2_MCBIST_CCS_INST_ARR0_28 = 0x07012331ull;
+
+static const uint64_t P9N2_MCBIST_0_CCS_INST_ARR0_28 = 0x07012331ull;
+
+static const uint64_t P9N2_MCBIST_1_CCS_INST_ARR0_28 = 0x08012331ull;
+
+
+static const uint64_t P9N2_MCBIST_CCS_INST_ARR0_29 = 0x07012332ull;
+
+static const uint64_t P9N2_MCBIST_0_CCS_INST_ARR0_29 = 0x07012332ull;
+
+static const uint64_t P9N2_MCBIST_1_CCS_INST_ARR0_29 = 0x08012332ull;
+
+
+static const uint64_t P9N2_MCBIST_CCS_INST_ARR0_30 = 0x07012333ull;
+
+static const uint64_t P9N2_MCBIST_0_CCS_INST_ARR0_30 = 0x07012333ull;
+
+static const uint64_t P9N2_MCBIST_1_CCS_INST_ARR0_30 = 0x08012333ull;
+
+
+static const uint64_t P9N2_MCBIST_CCS_INST_ARR0_31 = 0x07012334ull;
+
+static const uint64_t P9N2_MCBIST_0_CCS_INST_ARR0_31 = 0x07012334ull;
+
+static const uint64_t P9N2_MCBIST_1_CCS_INST_ARR0_31 = 0x08012334ull;
+
+
+static const uint64_t P9N2_MCBIST_CCS_INST_ARR1_00 = 0x07012335ull;
+
+static const uint64_t P9N2_MCBIST_0_CCS_INST_ARR1_00 = 0x07012335ull;
+
+static const uint64_t P9N2_MCBIST_1_CCS_INST_ARR1_00 = 0x08012335ull;
+
+
+static const uint64_t P9N2_MCBIST_CCS_INST_ARR1_01 = 0x07012336ull;
+
+static const uint64_t P9N2_MCBIST_0_CCS_INST_ARR1_01 = 0x07012336ull;
+
+static const uint64_t P9N2_MCBIST_1_CCS_INST_ARR1_01 = 0x08012336ull;
+
+
+static const uint64_t P9N2_MCBIST_CCS_INST_ARR1_02 = 0x07012337ull;
+
+static const uint64_t P9N2_MCBIST_0_CCS_INST_ARR1_02 = 0x07012337ull;
+
+static const uint64_t P9N2_MCBIST_1_CCS_INST_ARR1_02 = 0x08012337ull;
+
+
+static const uint64_t P9N2_MCBIST_CCS_INST_ARR1_03 = 0x07012338ull;
+
+static const uint64_t P9N2_MCBIST_0_CCS_INST_ARR1_03 = 0x07012338ull;
+
+static const uint64_t P9N2_MCBIST_1_CCS_INST_ARR1_03 = 0x08012338ull;
+
+
+static const uint64_t P9N2_MCBIST_CCS_INST_ARR1_04 = 0x07012339ull;
+
+static const uint64_t P9N2_MCBIST_0_CCS_INST_ARR1_04 = 0x07012339ull;
+
+static const uint64_t P9N2_MCBIST_1_CCS_INST_ARR1_04 = 0x08012339ull;
+
+
+static const uint64_t P9N2_MCBIST_CCS_INST_ARR1_05 = 0x0701233Aull;
+
+static const uint64_t P9N2_MCBIST_0_CCS_INST_ARR1_05 = 0x0701233Aull;
+
+static const uint64_t P9N2_MCBIST_1_CCS_INST_ARR1_05 = 0x0801233Aull;
+
+
+static const uint64_t P9N2_MCBIST_CCS_INST_ARR1_06 = 0x0701233Bull;
+
+static const uint64_t P9N2_MCBIST_0_CCS_INST_ARR1_06 = 0x0701233Bull;
+
+static const uint64_t P9N2_MCBIST_1_CCS_INST_ARR1_06 = 0x0801233Bull;
+
+
+static const uint64_t P9N2_MCBIST_CCS_INST_ARR1_07 = 0x0701233Cull;
+
+static const uint64_t P9N2_MCBIST_0_CCS_INST_ARR1_07 = 0x0701233Cull;
+
+static const uint64_t P9N2_MCBIST_1_CCS_INST_ARR1_07 = 0x0801233Cull;
+
+
+static const uint64_t P9N2_MCBIST_CCS_INST_ARR1_08 = 0x0701233Dull;
+
+static const uint64_t P9N2_MCBIST_0_CCS_INST_ARR1_08 = 0x0701233Dull;
+
+static const uint64_t P9N2_MCBIST_1_CCS_INST_ARR1_08 = 0x0801233Dull;
+
+
+static const uint64_t P9N2_MCBIST_CCS_INST_ARR1_09 = 0x0701233Eull;
+
+static const uint64_t P9N2_MCBIST_0_CCS_INST_ARR1_09 = 0x0701233Eull;
+
+static const uint64_t P9N2_MCBIST_1_CCS_INST_ARR1_09 = 0x0801233Eull;
+
+
+static const uint64_t P9N2_MCBIST_CCS_INST_ARR1_10 = 0x0701233Full;
+
+static const uint64_t P9N2_MCBIST_0_CCS_INST_ARR1_10 = 0x0701233Full;
+
+static const uint64_t P9N2_MCBIST_1_CCS_INST_ARR1_10 = 0x0801233Full;
+
+
+static const uint64_t P9N2_MCBIST_CCS_INST_ARR1_11 = 0x07012340ull;
+
+static const uint64_t P9N2_MCBIST_0_CCS_INST_ARR1_11 = 0x07012340ull;
+
+static const uint64_t P9N2_MCBIST_1_CCS_INST_ARR1_11 = 0x08012340ull;
+
+
+static const uint64_t P9N2_MCBIST_CCS_INST_ARR1_12 = 0x07012341ull;
+
+static const uint64_t P9N2_MCBIST_0_CCS_INST_ARR1_12 = 0x07012341ull;
+
+static const uint64_t P9N2_MCBIST_1_CCS_INST_ARR1_12 = 0x08012341ull;
+
+
+static const uint64_t P9N2_MCBIST_CCS_INST_ARR1_13 = 0x07012342ull;
+
+static const uint64_t P9N2_MCBIST_0_CCS_INST_ARR1_13 = 0x07012342ull;
+
+static const uint64_t P9N2_MCBIST_1_CCS_INST_ARR1_13 = 0x08012342ull;
+
+
+static const uint64_t P9N2_MCBIST_CCS_INST_ARR1_14 = 0x07012343ull;
+
+static const uint64_t P9N2_MCBIST_0_CCS_INST_ARR1_14 = 0x07012343ull;
+
+static const uint64_t P9N2_MCBIST_1_CCS_INST_ARR1_14 = 0x08012343ull;
+
+
+static const uint64_t P9N2_MCBIST_CCS_INST_ARR1_15 = 0x07012344ull;
+
+static const uint64_t P9N2_MCBIST_0_CCS_INST_ARR1_15 = 0x07012344ull;
+
+static const uint64_t P9N2_MCBIST_1_CCS_INST_ARR1_15 = 0x08012344ull;
+
+
+static const uint64_t P9N2_MCBIST_CCS_INST_ARR1_16 = 0x07012345ull;
+
+static const uint64_t P9N2_MCBIST_0_CCS_INST_ARR1_16 = 0x07012345ull;
+
+static const uint64_t P9N2_MCBIST_1_CCS_INST_ARR1_16 = 0x08012345ull;
+
+
+static const uint64_t P9N2_MCBIST_CCS_INST_ARR1_17 = 0x07012346ull;
+
+static const uint64_t P9N2_MCBIST_0_CCS_INST_ARR1_17 = 0x07012346ull;
+
+static const uint64_t P9N2_MCBIST_1_CCS_INST_ARR1_17 = 0x08012346ull;
+
+
+static const uint64_t P9N2_MCBIST_CCS_INST_ARR1_18 = 0x07012347ull;
+
+static const uint64_t P9N2_MCBIST_0_CCS_INST_ARR1_18 = 0x07012347ull;
+
+static const uint64_t P9N2_MCBIST_1_CCS_INST_ARR1_18 = 0x08012347ull;
+
+
+static const uint64_t P9N2_MCBIST_CCS_INST_ARR1_19 = 0x07012348ull;
+
+static const uint64_t P9N2_MCBIST_0_CCS_INST_ARR1_19 = 0x07012348ull;
+
+static const uint64_t P9N2_MCBIST_1_CCS_INST_ARR1_19 = 0x08012348ull;
+
+
+static const uint64_t P9N2_MCBIST_CCS_INST_ARR1_20 = 0x07012349ull;
+
+static const uint64_t P9N2_MCBIST_0_CCS_INST_ARR1_20 = 0x07012349ull;
+
+static const uint64_t P9N2_MCBIST_1_CCS_INST_ARR1_20 = 0x08012349ull;
+
+
+static const uint64_t P9N2_MCBIST_CCS_INST_ARR1_21 = 0x0701234Aull;
+
+static const uint64_t P9N2_MCBIST_0_CCS_INST_ARR1_21 = 0x0701234Aull;
+
+static const uint64_t P9N2_MCBIST_1_CCS_INST_ARR1_21 = 0x0801234Aull;
+
+
+static const uint64_t P9N2_MCBIST_CCS_INST_ARR1_22 = 0x0701234Bull;
+
+static const uint64_t P9N2_MCBIST_0_CCS_INST_ARR1_22 = 0x0701234Bull;
+
+static const uint64_t P9N2_MCBIST_1_CCS_INST_ARR1_22 = 0x0801234Bull;
+
+
+static const uint64_t P9N2_MCBIST_CCS_INST_ARR1_23 = 0x0701234Cull;
+
+static const uint64_t P9N2_MCBIST_0_CCS_INST_ARR1_23 = 0x0701234Cull;
+
+static const uint64_t P9N2_MCBIST_1_CCS_INST_ARR1_23 = 0x0801234Cull;
+
+
+static const uint64_t P9N2_MCBIST_CCS_INST_ARR1_24 = 0x0701234Dull;
+
+static const uint64_t P9N2_MCBIST_0_CCS_INST_ARR1_24 = 0x0701234Dull;
+
+static const uint64_t P9N2_MCBIST_1_CCS_INST_ARR1_24 = 0x0801234Dull;
+
+
+static const uint64_t P9N2_MCBIST_CCS_INST_ARR1_25 = 0x0701234Eull;
+
+static const uint64_t P9N2_MCBIST_0_CCS_INST_ARR1_25 = 0x0701234Eull;
+
+static const uint64_t P9N2_MCBIST_1_CCS_INST_ARR1_25 = 0x0801234Eull;
+
+
+static const uint64_t P9N2_MCBIST_CCS_INST_ARR1_26 = 0x0701234Full;
+
+static const uint64_t P9N2_MCBIST_0_CCS_INST_ARR1_26 = 0x0701234Full;
+
+static const uint64_t P9N2_MCBIST_1_CCS_INST_ARR1_26 = 0x0801234Full;
+
+
+static const uint64_t P9N2_MCBIST_CCS_INST_ARR1_27 = 0x07012350ull;
+
+static const uint64_t P9N2_MCBIST_0_CCS_INST_ARR1_27 = 0x07012350ull;
+
+static const uint64_t P9N2_MCBIST_1_CCS_INST_ARR1_27 = 0x08012350ull;
+
+
+static const uint64_t P9N2_MCBIST_CCS_INST_ARR1_28 = 0x07012351ull;
+
+static const uint64_t P9N2_MCBIST_0_CCS_INST_ARR1_28 = 0x07012351ull;
+
+static const uint64_t P9N2_MCBIST_1_CCS_INST_ARR1_28 = 0x08012351ull;
+
+
+static const uint64_t P9N2_MCBIST_CCS_INST_ARR1_29 = 0x07012352ull;
+
+static const uint64_t P9N2_MCBIST_0_CCS_INST_ARR1_29 = 0x07012352ull;
+
+static const uint64_t P9N2_MCBIST_1_CCS_INST_ARR1_29 = 0x08012352ull;
+
+
+static const uint64_t P9N2_MCBIST_CCS_INST_ARR1_30 = 0x07012353ull;
+
+static const uint64_t P9N2_MCBIST_0_CCS_INST_ARR1_30 = 0x07012353ull;
+
+static const uint64_t P9N2_MCBIST_1_CCS_INST_ARR1_30 = 0x08012353ull;
+
+
+static const uint64_t P9N2_MCBIST_CCS_INST_ARR1_31 = 0x07012354ull;
+
+static const uint64_t P9N2_MCBIST_0_CCS_INST_ARR1_31 = 0x07012354ull;
+
+static const uint64_t P9N2_MCBIST_1_CCS_INST_ARR1_31 = 0x08012354ull;
+
+
+static const uint64_t P9N2_MCBIST_CCS_MODEQ = 0x070123A7ull;
+
+static const uint64_t P9N2_MCBIST_0_CCS_MODEQ = 0x070123A7ull;
+
+static const uint64_t P9N2_MCBIST_1_CCS_MODEQ = 0x080123A7ull;
+
+
+static const uint64_t P9N2_MCBIST_CCS_STATQ = 0x070123A6ull;
+
+static const uint64_t P9N2_MCBIST_0_CCS_STATQ = 0x070123A6ull;
+
+static const uint64_t P9N2_MCBIST_1_CCS_STATQ = 0x080123A6ull;
+
+
+static const uint64_t P9N2_MCA_CERR0 = 0x07010A0Eull;
+
+static const uint64_t P9N2_MCA_0_CERR0 = 0x07010A0Eull;
+
+static const uint64_t P9N2_MCA_1_CERR0 = 0x07010A4Eull;
+
+static const uint64_t P9N2_MCA_2_CERR0 = 0x07010A8Eull;
+
+static const uint64_t P9N2_MCA_3_CERR0 = 0x07010ACEull;
+
+static const uint64_t P9N2_MCA_4_CERR0 = 0x08010A0Eull;
+
+static const uint64_t P9N2_MCA_5_CERR0 = 0x08010A4Eull;
+
+static const uint64_t P9N2_MCA_6_CERR0 = 0x08010A8Eull;
+
+static const uint64_t P9N2_MCA_7_CERR0 = 0x08010ACEull;
+
+
+static const uint64_t P9N2_MCA_CERR1 = 0x07010A0Full;
+
+static const uint64_t P9N2_MCA_0_CERR1 = 0x07010A0Full;
+
+static const uint64_t P9N2_MCA_1_CERR1 = 0x07010A4Full;
+
+static const uint64_t P9N2_MCA_2_CERR1 = 0x07010A8Full;
+
+static const uint64_t P9N2_MCA_3_CERR1 = 0x07010ACFull;
+
+static const uint64_t P9N2_MCA_4_CERR1 = 0x08010A0Full;
+
+static const uint64_t P9N2_MCA_5_CERR1 = 0x08010A4Full;
+
+static const uint64_t P9N2_MCA_6_CERR1 = 0x08010A8Full;
+
+static const uint64_t P9N2_MCA_7_CERR1 = 0x08010ACFull;
+
+
+static const uint64_t P9N2_MCBIST_CLKRATIO = 0x070123F0ull;
+
+static const uint64_t P9N2_MCBIST_0_CLKRATIO = 0x070123F0ull;
+
+static const uint64_t P9N2_MCBIST_1_CLKRATIO = 0x080123F0ull;
+
+
+static const uint64_t P9N2_MCBIST_DBGCFG0Q = 0x070123E8ull;
+
+static const uint64_t P9N2_MCBIST_0_DBGCFG0Q = 0x070123E8ull;
+
+static const uint64_t P9N2_MCBIST_1_DBGCFG0Q = 0x080123E8ull;
+
+
+static const uint64_t P9N2_MCBIST_DBGCFG1Q = 0x070123E9ull;
+
+static const uint64_t P9N2_MCBIST_0_DBGCFG1Q = 0x070123E9ull;
+
+static const uint64_t P9N2_MCBIST_1_DBGCFG1Q = 0x080123E9ull;
+
+
+static const uint64_t P9N2_MCBIST_DBGCFG2Q = 0x070123EAull;
+
+static const uint64_t P9N2_MCBIST_0_DBGCFG2Q = 0x070123EAull;
+
+static const uint64_t P9N2_MCBIST_1_DBGCFG2Q = 0x080123EAull;
+
+
+static const uint64_t P9N2_MCBIST_DBGCFG3Q = 0x070123EBull;
+
+static const uint64_t P9N2_MCBIST_0_DBGCFG3Q = 0x070123EBull;
+
+static const uint64_t P9N2_MCBIST_1_DBGCFG3Q = 0x080123EBull;
+
+
+static const uint64_t P9N2_MCA_DBGR = 0x07010A0Bull;
+
+static const uint64_t P9N2_MCA_0_DBGR = 0x07010A0Bull;
+
+static const uint64_t P9N2_MCA_1_DBGR = 0x07010A4Bull;
+
+static const uint64_t P9N2_MCA_2_DBGR = 0x07010A8Bull;
+
+static const uint64_t P9N2_MCA_3_DBGR = 0x07010ACBull;
+
+static const uint64_t P9N2_MCA_4_DBGR = 0x08010A0Bull;
+
+static const uint64_t P9N2_MCA_5_DBGR = 0x08010A4Bull;
+
+static const uint64_t P9N2_MCA_6_DBGR = 0x08010A8Bull;
+
+static const uint64_t P9N2_MCA_7_DBGR = 0x08010ACBull;
+
+
+static const uint64_t P9N2_MCA_3_DBG_INST1_COND_REG_1 = 0x070107C1ull;
+
+static const uint64_t P9N2_MCA_7_DBG_INST1_COND_REG_1 = 0x080107C1ull;
+
+
+static const uint64_t P9N2_MCA_3_DBG_INST1_COND_REG_2 = 0x070107C2ull;
+
+static const uint64_t P9N2_MCA_7_DBG_INST1_COND_REG_2 = 0x080107C2ull;
+
+
+static const uint64_t P9N2_MCA_3_DBG_INST1_COND_REG_3 = 0x070107C3ull;
+
+static const uint64_t P9N2_MCA_7_DBG_INST1_COND_REG_3 = 0x080107C3ull;
+
+
+static const uint64_t P9N2_MCA_3_DBG_INST2_COND_REG_1 = 0x070107C4ull;
+
+static const uint64_t P9N2_MCA_7_DBG_INST2_COND_REG_1 = 0x080107C4ull;
+
+
+static const uint64_t P9N2_MCA_3_DBG_INST2_COND_REG_2 = 0x070107C5ull;
+
+static const uint64_t P9N2_MCA_7_DBG_INST2_COND_REG_2 = 0x080107C5ull;
+
+
+static const uint64_t P9N2_MCA_3_DBG_INST2_COND_REG_3 = 0x070107C6ull;
+
+static const uint64_t P9N2_MCA_7_DBG_INST2_COND_REG_3 = 0x080107C6ull;
+
+
+static const uint64_t P9N2_MCA_3_DBG_MODE_REG = 0x070107C0ull;
+
+static const uint64_t P9N2_MCA_7_DBG_MODE_REG = 0x080107C0ull;
+
+
+static const uint64_t P9N2_MCA_3_DBG_TRACE_MODE_REG_2 = 0x070107CFull;
+
+static const uint64_t P9N2_MCA_7_DBG_TRACE_MODE_REG_2 = 0x080107CFull;
+
+
+static const uint64_t P9N2_MCA_3_DBG_TRACE_REG_0 = 0x070107CDull;
+
+static const uint64_t P9N2_MCA_7_DBG_TRACE_REG_0 = 0x080107CDull;
+
+
+static const uint64_t P9N2_MCA_3_DBG_TRACE_REG_1 = 0x070107CEull;
+
+static const uint64_t P9N2_MCA_7_DBG_TRACE_REG_1 = 0x080107CEull;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_BIT_ENABLE_P0_ADR0 = 0x800040000701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_BIT_ENABLE_P0_ADR0 = 0x800040000701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_BIT_ENABLE_P0_ADR0 = 0x800040000801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_BIT_ENABLE_P0_ADR1 = 0x800044000701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_BIT_ENABLE_P0_ADR1 = 0x800044000701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_BIT_ENABLE_P0_ADR1 = 0x800044000801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_BIT_ENABLE_P0_ADR2 = 0x800048000701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_BIT_ENABLE_P0_ADR2 = 0x800048000701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_BIT_ENABLE_P0_ADR2 = 0x800048000801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_BIT_ENABLE_P0_ADR3 = 0x80004C000701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_BIT_ENABLE_P0_ADR3 = 0x80004C000701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_BIT_ENABLE_P0_ADR3 = 0x80004C000801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_BIT_ENABLE_P1_ADR0 = 0x800040000701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_BIT_ENABLE_P1_ADR0 = 0x800040000801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_BIT_ENABLE_P1_ADR1 = 0x800044000701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_BIT_ENABLE_P1_ADR1 = 0x800044000801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_BIT_ENABLE_P1_ADR2 = 0x800048000701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_BIT_ENABLE_P1_ADR2 = 0x800048000801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_BIT_ENABLE_P1_ADR3 = 0x80004C000701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_BIT_ENABLE_P1_ADR3 = 0x80004C000801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_BIT_ENABLE_P2_ADR0 = 0x800040000701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_BIT_ENABLE_P2_ADR0 = 0x800040000801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_BIT_ENABLE_P2_ADR1 = 0x800044000701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_BIT_ENABLE_P2_ADR1 = 0x800044000801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_BIT_ENABLE_P2_ADR2 = 0x800048000701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_BIT_ENABLE_P2_ADR2 = 0x800048000801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_BIT_ENABLE_P2_ADR3 = 0x80004C000701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_BIT_ENABLE_P2_ADR3 = 0x80004C000801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_BIT_ENABLE_P3_ADR0 = 0x8000400007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_BIT_ENABLE_P3_ADR0 = 0x8000400008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_BIT_ENABLE_P3_ADR1 = 0x8000440007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_BIT_ENABLE_P3_ADR1 = 0x8000440008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_BIT_ENABLE_P3_ADR2 = 0x8000480007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_BIT_ENABLE_P3_ADR2 = 0x8000480008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_BIT_ENABLE_P3_ADR3 = 0x80004C0007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_BIT_ENABLE_P3_ADR3 = 0x80004C0008011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S0 = 0x800080380701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S0 = 0x800080380701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S0 = 0x800080380801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S1 = 0x800084380701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S1 = 0x800084380701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S1 = 0x800084380801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_DCD_CONTROL_P1_ADR32S0 = 0x800080380701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_DCD_CONTROL_P1_ADR32S0 = 0x800080380801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_DCD_CONTROL_P1_ADR32S1 = 0x800084380701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_DCD_CONTROL_P1_ADR32S1 = 0x800084380801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_DCD_CONTROL_P2_ADR32S0 = 0x800080380701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_DCD_CONTROL_P2_ADR32S0 = 0x800080380801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_DCD_CONTROL_P2_ADR32S1 = 0x800084380701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_DCD_CONTROL_P2_ADR32S1 = 0x800084380801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_DCD_CONTROL_P3_ADR32S0 = 0x8000803807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_DCD_CONTROL_P3_ADR32S0 = 0x8000803808011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_DCD_CONTROL_P3_ADR32S1 = 0x8000843807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_DCD_CONTROL_P3_ADR32S1 = 0x8000843808011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_DELAY0_P0_ADR0 = 0x800040040701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_DELAY0_P0_ADR0 = 0x800040040701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_DELAY0_P0_ADR0 = 0x800040040801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_DELAY0_P0_ADR1 = 0x800044040701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_DELAY0_P0_ADR1 = 0x800044040701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_DELAY0_P0_ADR1 = 0x800044040801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_DELAY0_P0_ADR2 = 0x800048040701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_DELAY0_P0_ADR2 = 0x800048040701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_DELAY0_P0_ADR2 = 0x800048040801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_DELAY0_P0_ADR3 = 0x80004C040701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_DELAY0_P0_ADR3 = 0x80004C040701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_DELAY0_P0_ADR3 = 0x80004C040801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_DELAY0_P1_ADR0 = 0x800040040701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_DELAY0_P1_ADR0 = 0x800040040801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_DELAY0_P1_ADR1 = 0x800044040701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_DELAY0_P1_ADR1 = 0x800044040801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_DELAY0_P1_ADR2 = 0x800048040701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_DELAY0_P1_ADR2 = 0x800048040801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_DELAY0_P1_ADR3 = 0x80004C040701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_DELAY0_P1_ADR3 = 0x80004C040801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_DELAY0_P2_ADR0 = 0x800040040701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_DELAY0_P2_ADR0 = 0x800040040801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_DELAY0_P2_ADR1 = 0x800044040701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_DELAY0_P2_ADR1 = 0x800044040801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_DELAY0_P2_ADR2 = 0x800048040701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_DELAY0_P2_ADR2 = 0x800048040801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_DELAY0_P2_ADR3 = 0x80004C040701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_DELAY0_P2_ADR3 = 0x80004C040801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_DELAY0_P3_ADR0 = 0x8000400407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_DELAY0_P3_ADR0 = 0x8000400408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_DELAY0_P3_ADR1 = 0x8000440407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_DELAY0_P3_ADR1 = 0x8000440408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_DELAY0_P3_ADR2 = 0x8000480407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_DELAY0_P3_ADR2 = 0x8000480408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_DELAY0_P3_ADR3 = 0x80004C0407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_DELAY0_P3_ADR3 = 0x80004C0408011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_DELAY1_P0_ADR0 = 0x800040050701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_DELAY1_P0_ADR0 = 0x800040050701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_DELAY1_P0_ADR0 = 0x800040050801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_DELAY1_P0_ADR1 = 0x800044050701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_DELAY1_P0_ADR1 = 0x800044050701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_DELAY1_P0_ADR1 = 0x800044050801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_DELAY1_P0_ADR2 = 0x800048050701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_DELAY1_P0_ADR2 = 0x800048050701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_DELAY1_P0_ADR2 = 0x800048050801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_DELAY1_P0_ADR3 = 0x80004C050701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_DELAY1_P0_ADR3 = 0x80004C050701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_DELAY1_P0_ADR3 = 0x80004C050801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_DELAY1_P1_ADR0 = 0x800040050701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_DELAY1_P1_ADR0 = 0x800040050801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_DELAY1_P1_ADR1 = 0x800044050701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_DELAY1_P1_ADR1 = 0x800044050801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_DELAY1_P1_ADR2 = 0x800048050701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_DELAY1_P1_ADR2 = 0x800048050801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_DELAY1_P1_ADR3 = 0x80004C050701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_DELAY1_P1_ADR3 = 0x80004C050801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_DELAY1_P2_ADR0 = 0x800040050701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_DELAY1_P2_ADR0 = 0x800040050801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_DELAY1_P2_ADR1 = 0x800044050701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_DELAY1_P2_ADR1 = 0x800044050801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_DELAY1_P2_ADR2 = 0x800048050701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_DELAY1_P2_ADR2 = 0x800048050801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_DELAY1_P2_ADR3 = 0x80004C050701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_DELAY1_P2_ADR3 = 0x80004C050801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_DELAY1_P3_ADR0 = 0x8000400507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_DELAY1_P3_ADR0 = 0x8000400508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_DELAY1_P3_ADR1 = 0x8000440507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_DELAY1_P3_ADR1 = 0x8000440508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_DELAY1_P3_ADR2 = 0x8000480507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_DELAY1_P3_ADR2 = 0x8000480508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_DELAY1_P3_ADR3 = 0x80004C0507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_DELAY1_P3_ADR3 = 0x80004C0508011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_DELAY2_P0_ADR0 = 0x800040060701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_DELAY2_P0_ADR0 = 0x800040060701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_DELAY2_P0_ADR0 = 0x800040060801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_DELAY2_P0_ADR1 = 0x800044060701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_DELAY2_P0_ADR1 = 0x800044060701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_DELAY2_P0_ADR1 = 0x800044060801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_DELAY2_P0_ADR2 = 0x800048060701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_DELAY2_P0_ADR2 = 0x800048060701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_DELAY2_P0_ADR2 = 0x800048060801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_DELAY2_P0_ADR3 = 0x80004C060701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_DELAY2_P0_ADR3 = 0x80004C060701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_DELAY2_P0_ADR3 = 0x80004C060801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_DELAY2_P1_ADR0 = 0x800040060701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_DELAY2_P1_ADR0 = 0x800040060801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_DELAY2_P1_ADR1 = 0x800044060701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_DELAY2_P1_ADR1 = 0x800044060801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_DELAY2_P1_ADR2 = 0x800048060701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_DELAY2_P1_ADR2 = 0x800048060801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_DELAY2_P1_ADR3 = 0x80004C060701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_DELAY2_P1_ADR3 = 0x80004C060801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_DELAY2_P2_ADR0 = 0x800040060701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_DELAY2_P2_ADR0 = 0x800040060801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_DELAY2_P2_ADR1 = 0x800044060701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_DELAY2_P2_ADR1 = 0x800044060801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_DELAY2_P2_ADR2 = 0x800048060701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_DELAY2_P2_ADR2 = 0x800048060801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_DELAY2_P2_ADR3 = 0x80004C060701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_DELAY2_P2_ADR3 = 0x80004C060801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_DELAY2_P3_ADR0 = 0x8000400607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_DELAY2_P3_ADR0 = 0x8000400608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_DELAY2_P3_ADR1 = 0x8000440607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_DELAY2_P3_ADR1 = 0x8000440608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_DELAY2_P3_ADR2 = 0x8000480607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_DELAY2_P3_ADR2 = 0x8000480608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_DELAY2_P3_ADR3 = 0x80004C0607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_DELAY2_P3_ADR3 = 0x80004C0608011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_DELAY3_P0_ADR0 = 0x800040070701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_DELAY3_P0_ADR0 = 0x800040070701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_DELAY3_P0_ADR0 = 0x800040070801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_DELAY3_P0_ADR1 = 0x800044070701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_DELAY3_P0_ADR1 = 0x800044070701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_DELAY3_P0_ADR1 = 0x800044070801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_DELAY3_P0_ADR2 = 0x800048070701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_DELAY3_P0_ADR2 = 0x800048070701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_DELAY3_P0_ADR2 = 0x800048070801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_DELAY3_P0_ADR3 = 0x80004C070701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_DELAY3_P0_ADR3 = 0x80004C070701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_DELAY3_P0_ADR3 = 0x80004C070801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_DELAY3_P1_ADR0 = 0x800040070701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_DELAY3_P1_ADR0 = 0x800040070801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_DELAY3_P1_ADR1 = 0x800044070701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_DELAY3_P1_ADR1 = 0x800044070801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_DELAY3_P1_ADR2 = 0x800048070701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_DELAY3_P1_ADR2 = 0x800048070801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_DELAY3_P1_ADR3 = 0x80004C070701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_DELAY3_P1_ADR3 = 0x80004C070801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_DELAY3_P2_ADR0 = 0x800040070701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_DELAY3_P2_ADR0 = 0x800040070801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_DELAY3_P2_ADR1 = 0x800044070701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_DELAY3_P2_ADR1 = 0x800044070801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_DELAY3_P2_ADR2 = 0x800048070701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_DELAY3_P2_ADR2 = 0x800048070801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_DELAY3_P2_ADR3 = 0x80004C070701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_DELAY3_P2_ADR3 = 0x80004C070801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_DELAY3_P3_ADR0 = 0x8000400707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_DELAY3_P3_ADR0 = 0x8000400708011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_DELAY3_P3_ADR1 = 0x8000440707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_DELAY3_P3_ADR1 = 0x8000440708011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_DELAY3_P3_ADR2 = 0x8000480707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_DELAY3_P3_ADR2 = 0x8000480708011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_DELAY3_P3_ADR3 = 0x80004C0707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_DELAY3_P3_ADR3 = 0x80004C0708011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_DELAY4_P0_ADR0 = 0x800040080701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_DELAY4_P0_ADR0 = 0x800040080701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_DELAY4_P0_ADR0 = 0x800040080801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_DELAY4_P0_ADR1 = 0x800044080701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_DELAY4_P0_ADR1 = 0x800044080701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_DELAY4_P0_ADR1 = 0x800044080801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_DELAY4_P0_ADR2 = 0x800048080701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_DELAY4_P0_ADR2 = 0x800048080701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_DELAY4_P0_ADR2 = 0x800048080801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_DELAY4_P0_ADR3 = 0x80004C080701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_DELAY4_P0_ADR3 = 0x80004C080701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_DELAY4_P0_ADR3 = 0x80004C080801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_DELAY4_P1_ADR0 = 0x800040080701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_DELAY4_P1_ADR0 = 0x800040080801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_DELAY4_P1_ADR1 = 0x800044080701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_DELAY4_P1_ADR1 = 0x800044080801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_DELAY4_P1_ADR2 = 0x800048080701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_DELAY4_P1_ADR2 = 0x800048080801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_DELAY4_P1_ADR3 = 0x80004C080701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_DELAY4_P1_ADR3 = 0x80004C080801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_DELAY4_P2_ADR0 = 0x800040080701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_DELAY4_P2_ADR0 = 0x800040080801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_DELAY4_P2_ADR1 = 0x800044080701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_DELAY4_P2_ADR1 = 0x800044080801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_DELAY4_P2_ADR2 = 0x800048080701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_DELAY4_P2_ADR2 = 0x800048080801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_DELAY4_P2_ADR3 = 0x80004C080701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_DELAY4_P2_ADR3 = 0x80004C080801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_DELAY4_P3_ADR0 = 0x8000400807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_DELAY4_P3_ADR0 = 0x8000400808011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_DELAY4_P3_ADR1 = 0x8000440807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_DELAY4_P3_ADR1 = 0x8000440808011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_DELAY4_P3_ADR2 = 0x8000480807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_DELAY4_P3_ADR2 = 0x8000480808011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_DELAY4_P3_ADR3 = 0x80004C0807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_DELAY4_P3_ADR3 = 0x80004C0808011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_DELAY5_P0_ADR0 = 0x800040090701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_DELAY5_P0_ADR0 = 0x800040090701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_DELAY5_P0_ADR0 = 0x800040090801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_DELAY5_P0_ADR1 = 0x800044090701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_DELAY5_P0_ADR1 = 0x800044090701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_DELAY5_P0_ADR1 = 0x800044090801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_DELAY5_P0_ADR2 = 0x800048090701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_DELAY5_P0_ADR2 = 0x800048090701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_DELAY5_P0_ADR2 = 0x800048090801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_DELAY5_P0_ADR3 = 0x80004C090701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_DELAY5_P0_ADR3 = 0x80004C090701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_DELAY5_P0_ADR3 = 0x80004C090801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_DELAY5_P1_ADR0 = 0x800040090701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_DELAY5_P1_ADR0 = 0x800040090801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_DELAY5_P1_ADR1 = 0x800044090701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_DELAY5_P1_ADR1 = 0x800044090801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_DELAY5_P1_ADR2 = 0x800048090701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_DELAY5_P1_ADR2 = 0x800048090801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_DELAY5_P1_ADR3 = 0x80004C090701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_DELAY5_P1_ADR3 = 0x80004C090801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_DELAY5_P2_ADR0 = 0x800040090701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_DELAY5_P2_ADR0 = 0x800040090801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_DELAY5_P2_ADR1 = 0x800044090701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_DELAY5_P2_ADR1 = 0x800044090801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_DELAY5_P2_ADR2 = 0x800048090701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_DELAY5_P2_ADR2 = 0x800048090801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_DELAY5_P2_ADR3 = 0x80004C090701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_DELAY5_P2_ADR3 = 0x80004C090801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_DELAY5_P3_ADR0 = 0x8000400907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_DELAY5_P3_ADR0 = 0x8000400908011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_DELAY5_P3_ADR1 = 0x8000440907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_DELAY5_P3_ADR1 = 0x8000440908011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_DELAY5_P3_ADR2 = 0x8000480907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_DELAY5_P3_ADR2 = 0x8000480908011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_DELAY5_P3_ADR3 = 0x80004C0907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_DELAY5_P3_ADR3 = 0x80004C0908011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_DELAY6_P0_ADR0 = 0x8000400A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_DELAY6_P0_ADR0 = 0x8000400A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_DELAY6_P0_ADR0 = 0x8000400A0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_DELAY6_P0_ADR1 = 0x8000440A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_DELAY6_P0_ADR1 = 0x8000440A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_DELAY6_P0_ADR1 = 0x8000440A0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_DELAY6_P0_ADR2 = 0x8000480A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_DELAY6_P0_ADR2 = 0x8000480A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_DELAY6_P0_ADR2 = 0x8000480A0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_DELAY6_P0_ADR3 = 0x80004C0A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_DELAY6_P0_ADR3 = 0x80004C0A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_DELAY6_P0_ADR3 = 0x80004C0A0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_DELAY6_P1_ADR0 = 0x8000400A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_DELAY6_P1_ADR0 = 0x8000400A0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_DELAY6_P1_ADR1 = 0x8000440A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_DELAY6_P1_ADR1 = 0x8000440A0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_DELAY6_P1_ADR2 = 0x8000480A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_DELAY6_P1_ADR2 = 0x8000480A0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_DELAY6_P1_ADR3 = 0x80004C0A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_DELAY6_P1_ADR3 = 0x80004C0A0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_DELAY6_P2_ADR0 = 0x8000400A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_DELAY6_P2_ADR0 = 0x8000400A0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_DELAY6_P2_ADR1 = 0x8000440A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_DELAY6_P2_ADR1 = 0x8000440A0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_DELAY6_P2_ADR2 = 0x8000480A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_DELAY6_P2_ADR2 = 0x8000480A0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_DELAY6_P2_ADR3 = 0x80004C0A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_DELAY6_P2_ADR3 = 0x80004C0A0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_DELAY6_P3_ADR0 = 0x8000400A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_DELAY6_P3_ADR0 = 0x8000400A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_DELAY6_P3_ADR1 = 0x8000440A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_DELAY6_P3_ADR1 = 0x8000440A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_DELAY6_P3_ADR2 = 0x8000480A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_DELAY6_P3_ADR2 = 0x8000480A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_DELAY6_P3_ADR3 = 0x80004C0A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_DELAY6_P3_ADR3 = 0x80004C0A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_DELAY7_P0_ADR0 = 0x8000400B0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_DELAY7_P0_ADR0 = 0x8000400B0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_DELAY7_P0_ADR0 = 0x8000400B0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_DELAY7_P0_ADR1 = 0x8000440B0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_DELAY7_P0_ADR1 = 0x8000440B0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_DELAY7_P0_ADR1 = 0x8000440B0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_DELAY7_P0_ADR2 = 0x8000480B0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_DELAY7_P0_ADR2 = 0x8000480B0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_DELAY7_P0_ADR2 = 0x8000480B0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_DELAY7_P0_ADR3 = 0x80004C0B0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_DELAY7_P0_ADR3 = 0x80004C0B0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_DELAY7_P0_ADR3 = 0x80004C0B0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_DELAY7_P1_ADR0 = 0x8000400B0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_DELAY7_P1_ADR0 = 0x8000400B0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_DELAY7_P1_ADR1 = 0x8000440B0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_DELAY7_P1_ADR1 = 0x8000440B0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_DELAY7_P1_ADR2 = 0x8000480B0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_DELAY7_P1_ADR2 = 0x8000480B0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_DELAY7_P1_ADR3 = 0x80004C0B0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_DELAY7_P1_ADR3 = 0x80004C0B0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_DELAY7_P2_ADR0 = 0x8000400B0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_DELAY7_P2_ADR0 = 0x8000400B0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_DELAY7_P2_ADR1 = 0x8000440B0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_DELAY7_P2_ADR1 = 0x8000440B0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_DELAY7_P2_ADR2 = 0x8000480B0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_DELAY7_P2_ADR2 = 0x8000480B0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_DELAY7_P2_ADR3 = 0x80004C0B0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_DELAY7_P2_ADR3 = 0x80004C0B0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_DELAY7_P3_ADR0 = 0x8000400B07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_DELAY7_P3_ADR0 = 0x8000400B08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_DELAY7_P3_ADR1 = 0x8000440B07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_DELAY7_P3_ADR1 = 0x8000440B08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_DELAY7_P3_ADR2 = 0x8000480B07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_DELAY7_P3_ADR2 = 0x8000480B08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_DELAY7_P3_ADR3 = 0x80004C0B07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_DELAY7_P3_ADR3 = 0x80004C0B08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR0 = 0x8000400C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR0 = 0x8000400C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR0 = 0x8000400C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR1 = 0x8000440C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR1 = 0x8000440C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR1 = 0x8000440C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR2 = 0x8000480C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR2 = 0x8000480C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR2 = 0x8000480C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR3 = 0x80004C0C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR3 = 0x80004C0C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR3 = 0x80004C0C0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P1_ADR0 = 0x8000400C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P1_ADR0 = 0x8000400C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P1_ADR1 = 0x8000440C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P1_ADR1 = 0x8000440C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P1_ADR2 = 0x8000480C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P1_ADR2 = 0x8000480C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P1_ADR3 = 0x80004C0C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P1_ADR3 = 0x80004C0C0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P2_ADR0 = 0x8000400C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P2_ADR0 = 0x8000400C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P2_ADR1 = 0x8000440C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P2_ADR1 = 0x8000440C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P2_ADR2 = 0x8000480C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P2_ADR2 = 0x8000480C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P2_ADR3 = 0x80004C0C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P2_ADR3 = 0x80004C0C0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P3_ADR0 = 0x8000400C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P3_ADR0 = 0x8000400C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P3_ADR1 = 0x8000440C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P3_ADR1 = 0x8000440C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P3_ADR2 = 0x8000480C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P3_ADR2 = 0x8000480C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P3_ADR3 = 0x80004C0C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P3_ADR3 = 0x80004C0C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR0 = 0x800040010701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR0 = 0x800040010701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR0 = 0x800040010801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR1 = 0x800044010701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR1 = 0x800044010701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR1 = 0x800044010801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR2 = 0x800048010701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR2 = 0x800048010701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR2 = 0x800048010801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR3 = 0x80004C010701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR3 = 0x80004C010701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR3 = 0x80004C010801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_DIFFPAIR_ENABLE_P1_ADR0 = 0x800040010701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_DIFFPAIR_ENABLE_P1_ADR0 = 0x800040010801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_DIFFPAIR_ENABLE_P1_ADR1 = 0x800044010701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_DIFFPAIR_ENABLE_P1_ADR1 = 0x800044010801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_DIFFPAIR_ENABLE_P1_ADR2 = 0x800048010701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_DIFFPAIR_ENABLE_P1_ADR2 = 0x800048010801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_DIFFPAIR_ENABLE_P1_ADR3 = 0x80004C010701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_DIFFPAIR_ENABLE_P1_ADR3 = 0x80004C010801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_DIFFPAIR_ENABLE_P2_ADR0 = 0x800040010701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_DIFFPAIR_ENABLE_P2_ADR0 = 0x800040010801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_DIFFPAIR_ENABLE_P2_ADR1 = 0x800044010701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_DIFFPAIR_ENABLE_P2_ADR1 = 0x800044010801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_DIFFPAIR_ENABLE_P2_ADR2 = 0x800048010701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_DIFFPAIR_ENABLE_P2_ADR2 = 0x800048010801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_DIFFPAIR_ENABLE_P2_ADR3 = 0x80004C010701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_DIFFPAIR_ENABLE_P2_ADR3 = 0x80004C010801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_DIFFPAIR_ENABLE_P3_ADR0 = 0x8000400107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_DIFFPAIR_ENABLE_P3_ADR0 = 0x8000400108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_DIFFPAIR_ENABLE_P3_ADR1 = 0x8000440107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_DIFFPAIR_ENABLE_P3_ADR1 = 0x8000440108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_DIFFPAIR_ENABLE_P3_ADR2 = 0x8000480107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_DIFFPAIR_ENABLE_P3_ADR2 = 0x8000480108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_DIFFPAIR_ENABLE_P3_ADR3 = 0x80004C0107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_DIFFPAIR_ENABLE_P3_ADR3 = 0x80004C0108011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0 = 0x8000803A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0 = 0x8000803A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0 = 0x8000803A0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1 = 0x8000843A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1 = 0x8000843A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1 = 0x8000843A0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_DLL_CNTL_P1_ADR32S0 = 0x8000803A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_DLL_CNTL_P1_ADR32S0 = 0x8000803A0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_DLL_CNTL_P1_ADR32S1 = 0x8000843A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_DLL_CNTL_P1_ADR32S1 = 0x8000843A0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_DLL_CNTL_P2_ADR32S0 = 0x8000803A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_DLL_CNTL_P2_ADR32S0 = 0x8000803A0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_DLL_CNTL_P2_ADR32S1 = 0x8000843A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_DLL_CNTL_P2_ADR32S1 = 0x8000843A0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_DLL_CNTL_P3_ADR32S0 = 0x8000803A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_DLL_CNTL_P3_ADR32S0 = 0x8000803A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_DLL_CNTL_P3_ADR32S1 = 0x8000843A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_DLL_CNTL_P3_ADR32S1 = 0x8000843A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_DLL_DAC_LOWER_P0_ADR32S0 = 0x8000803B0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_DLL_DAC_LOWER_P0_ADR32S0 = 0x8000803B0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_DLL_DAC_LOWER_P0_ADR32S0 = 0x8000803B0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_DLL_DAC_LOWER_P0_ADR32S1 = 0x8000843B0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_DLL_DAC_LOWER_P0_ADR32S1 = 0x8000843B0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_DLL_DAC_LOWER_P0_ADR32S1 = 0x8000843B0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_DLL_DAC_LOWER_P1_ADR32S0 = 0x8000803B0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_DLL_DAC_LOWER_P1_ADR32S0 = 0x8000803B0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_DLL_DAC_LOWER_P1_ADR32S1 = 0x8000843B0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_DLL_DAC_LOWER_P1_ADR32S1 = 0x8000843B0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_DLL_DAC_LOWER_P2_ADR32S0 = 0x8000803B0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_DLL_DAC_LOWER_P2_ADR32S0 = 0x8000803B0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_DLL_DAC_LOWER_P2_ADR32S1 = 0x8000843B0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_DLL_DAC_LOWER_P2_ADR32S1 = 0x8000843B0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_DLL_DAC_LOWER_P3_ADR32S0 = 0x8000803B07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_DLL_DAC_LOWER_P3_ADR32S0 = 0x8000803B08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_DLL_DAC_LOWER_P3_ADR32S1 = 0x8000843B07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_DLL_DAC_LOWER_P3_ADR32S1 = 0x8000843B08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_DLL_DAC_UPPER_P0_ADR32S0 = 0x8000803C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_DLL_DAC_UPPER_P0_ADR32S0 = 0x8000803C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_DLL_DAC_UPPER_P0_ADR32S0 = 0x8000803C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_DLL_DAC_UPPER_P0_ADR32S1 = 0x8000843C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_DLL_DAC_UPPER_P0_ADR32S1 = 0x8000843C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_DLL_DAC_UPPER_P0_ADR32S1 = 0x8000843C0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_DLL_DAC_UPPER_P1_ADR32S0 = 0x8000803C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_DLL_DAC_UPPER_P1_ADR32S0 = 0x8000803C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_DLL_DAC_UPPER_P1_ADR32S1 = 0x8000843C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_DLL_DAC_UPPER_P1_ADR32S1 = 0x8000843C0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_DLL_DAC_UPPER_P2_ADR32S0 = 0x8000803C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_DLL_DAC_UPPER_P2_ADR32S0 = 0x8000803C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_DLL_DAC_UPPER_P2_ADR32S1 = 0x8000843C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_DLL_DAC_UPPER_P2_ADR32S1 = 0x8000843C0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_DLL_DAC_UPPER_P3_ADR32S0 = 0x8000803C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_DLL_DAC_UPPER_P3_ADR32S0 = 0x8000803C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_DLL_DAC_UPPER_P3_ADR32S1 = 0x8000843C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_DLL_DAC_UPPER_P3_ADR32S1 = 0x8000843C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_DLL_SLAVE_VREG_LOWER_P0_ADR32S0 = 0x8000802E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_DLL_SLAVE_VREG_LOWER_P0_ADR32S0 = 0x8000802E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_DLL_SLAVE_VREG_LOWER_P0_ADR32S0 = 0x8000802E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_DLL_SLAVE_VREG_LOWER_P0_ADR32S1 = 0x8000842E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_DLL_SLAVE_VREG_LOWER_P0_ADR32S1 = 0x8000842E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_DLL_SLAVE_VREG_LOWER_P0_ADR32S1 = 0x8000842E0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_DLL_SLAVE_VREG_LOWER_P1_ADR32S0 = 0x8000802E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_DLL_SLAVE_VREG_LOWER_P1_ADR32S0 = 0x8000802E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_DLL_SLAVE_VREG_LOWER_P1_ADR32S1 = 0x8000842E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_DLL_SLAVE_VREG_LOWER_P1_ADR32S1 = 0x8000842E0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_DLL_SLAVE_VREG_LOWER_P2_ADR32S0 = 0x8000802E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_DLL_SLAVE_VREG_LOWER_P2_ADR32S0 = 0x8000802E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_DLL_SLAVE_VREG_LOWER_P2_ADR32S1 = 0x8000842E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_DLL_SLAVE_VREG_LOWER_P2_ADR32S1 = 0x8000842E0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_DLL_SLAVE_VREG_LOWER_P3_ADR32S0 = 0x8000802E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_DLL_SLAVE_VREG_LOWER_P3_ADR32S0 = 0x8000802E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_DLL_SLAVE_VREG_LOWER_P3_ADR32S1 = 0x8000842E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_DLL_SLAVE_VREG_LOWER_P3_ADR32S1 = 0x8000842E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_DLL_SLAVE_VREG_UPPER_P0_ADR32S0 = 0x8000802F0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_DLL_SLAVE_VREG_UPPER_P0_ADR32S0 = 0x8000802F0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_DLL_SLAVE_VREG_UPPER_P0_ADR32S0 = 0x8000802F0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_DLL_SLAVE_VREG_UPPER_P0_ADR32S1 = 0x8000842F0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_DLL_SLAVE_VREG_UPPER_P0_ADR32S1 = 0x8000842F0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_DLL_SLAVE_VREG_UPPER_P0_ADR32S1 = 0x8000842F0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_DLL_SLAVE_VREG_UPPER_P1_ADR32S0 = 0x8000802F0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_DLL_SLAVE_VREG_UPPER_P1_ADR32S0 = 0x8000802F0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_DLL_SLAVE_VREG_UPPER_P1_ADR32S1 = 0x8000842F0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_DLL_SLAVE_VREG_UPPER_P1_ADR32S1 = 0x8000842F0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_DLL_SLAVE_VREG_UPPER_P2_ADR32S0 = 0x8000802F0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_DLL_SLAVE_VREG_UPPER_P2_ADR32S0 = 0x8000802F0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_DLL_SLAVE_VREG_UPPER_P2_ADR32S1 = 0x8000842F0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_DLL_SLAVE_VREG_UPPER_P2_ADR32S1 = 0x8000842F0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_DLL_SLAVE_VREG_UPPER_P3_ADR32S0 = 0x8000802F07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_DLL_SLAVE_VREG_UPPER_P3_ADR32S0 = 0x8000802F08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_DLL_SLAVE_VREG_UPPER_P3_ADR32S1 = 0x8000842F07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_DLL_SLAVE_VREG_UPPER_P3_ADR32S1 = 0x8000842F08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_DLL_SW_CONTROL_0_P0_ADR32S0 = 0x800080300701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_DLL_SW_CONTROL_0_P0_ADR32S0 = 0x800080300701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_DLL_SW_CONTROL_0_P0_ADR32S0 = 0x800080300801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_DLL_SW_CONTROL_0_P0_ADR32S1 = 0x800084300701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_DLL_SW_CONTROL_0_P0_ADR32S1 = 0x800084300701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_DLL_SW_CONTROL_0_P0_ADR32S1 = 0x800084300801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_DLL_SW_CONTROL_0_P1_ADR32S0 = 0x800080300701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_DLL_SW_CONTROL_0_P1_ADR32S0 = 0x800080300801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_DLL_SW_CONTROL_0_P1_ADR32S1 = 0x800084300701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_DLL_SW_CONTROL_0_P1_ADR32S1 = 0x800084300801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_DLL_SW_CONTROL_0_P2_ADR32S0 = 0x800080300701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_DLL_SW_CONTROL_0_P2_ADR32S0 = 0x800080300801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_DLL_SW_CONTROL_0_P2_ADR32S1 = 0x800084300701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_DLL_SW_CONTROL_0_P2_ADR32S1 = 0x800084300801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_DLL_SW_CONTROL_0_P3_ADR32S0 = 0x8000803007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_DLL_SW_CONTROL_0_P3_ADR32S0 = 0x8000803008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_DLL_SW_CONTROL_0_P3_ADR32S1 = 0x8000843007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_DLL_SW_CONTROL_0_P3_ADR32S1 = 0x8000843008011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_DLL_SW_CONTROL_1_P0_ADR32S0 = 0x8000802D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_DLL_SW_CONTROL_1_P0_ADR32S0 = 0x8000802D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_DLL_SW_CONTROL_1_P0_ADR32S0 = 0x8000802D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_DLL_SW_CONTROL_1_P0_ADR32S1 = 0x8000842D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_DLL_SW_CONTROL_1_P0_ADR32S1 = 0x8000842D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_DLL_SW_CONTROL_1_P0_ADR32S1 = 0x8000842D0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_DLL_SW_CONTROL_1_P1_ADR32S0 = 0x8000802D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_DLL_SW_CONTROL_1_P1_ADR32S0 = 0x8000802D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_DLL_SW_CONTROL_1_P1_ADR32S1 = 0x8000842D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_DLL_SW_CONTROL_1_P1_ADR32S1 = 0x8000842D0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_DLL_SW_CONTROL_1_P2_ADR32S0 = 0x8000802D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_DLL_SW_CONTROL_1_P2_ADR32S0 = 0x8000802D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_DLL_SW_CONTROL_1_P2_ADR32S1 = 0x8000842D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_DLL_SW_CONTROL_1_P2_ADR32S1 = 0x8000842D0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_DLL_SW_CONTROL_1_P3_ADR32S0 = 0x8000802D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_DLL_SW_CONTROL_1_P3_ADR32S0 = 0x8000802D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_DLL_SW_CONTROL_1_P3_ADR32S1 = 0x8000842D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_DLL_SW_CONTROL_1_P3_ADR32S1 = 0x8000842D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_COARSE_P0_ADR32S0 = 0x8000803E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_DLL_VREG_COARSE_P0_ADR32S0 = 0x8000803E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_DLL_VREG_COARSE_P0_ADR32S0 = 0x8000803E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_COARSE_P0_ADR32S1 = 0x8000843E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_DLL_VREG_COARSE_P0_ADR32S1 = 0x8000843E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_DLL_VREG_COARSE_P0_ADR32S1 = 0x8000843E0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_DLL_VREG_COARSE_P1_ADR32S0 = 0x8000803E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_DLL_VREG_COARSE_P1_ADR32S0 = 0x8000803E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_DLL_VREG_COARSE_P1_ADR32S1 = 0x8000843E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_DLL_VREG_COARSE_P1_ADR32S1 = 0x8000843E0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_DLL_VREG_COARSE_P2_ADR32S0 = 0x8000803E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_DLL_VREG_COARSE_P2_ADR32S0 = 0x8000803E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_DLL_VREG_COARSE_P2_ADR32S1 = 0x8000843E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_DLL_VREG_COARSE_P2_ADR32S1 = 0x8000843E0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_DLL_VREG_COARSE_P3_ADR32S0 = 0x8000803E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_DLL_VREG_COARSE_P3_ADR32S0 = 0x8000803E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_DLL_VREG_COARSE_P3_ADR32S1 = 0x8000843E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_DLL_VREG_COARSE_P3_ADR32S1 = 0x8000843E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S0 = 0x800080310701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S0 = 0x800080310701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S0 = 0x800080310801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S1 = 0x800084310701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S1 = 0x800084310701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S1 = 0x800084310801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_DLL_VREG_CONFIG_1_P1_ADR32S0 = 0x800080310701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_DLL_VREG_CONFIG_1_P1_ADR32S0 = 0x800080310801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_DLL_VREG_CONFIG_1_P1_ADR32S1 = 0x800084310701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_DLL_VREG_CONFIG_1_P1_ADR32S1 = 0x800084310801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_DLL_VREG_CONFIG_1_P2_ADR32S0 = 0x800080310701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_DLL_VREG_CONFIG_1_P2_ADR32S0 = 0x800080310801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_DLL_VREG_CONFIG_1_P2_ADR32S1 = 0x800084310701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_DLL_VREG_CONFIG_1_P2_ADR32S1 = 0x800084310801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_DLL_VREG_CONFIG_1_P3_ADR32S0 = 0x8000803107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_DLL_VREG_CONFIG_1_P3_ADR32S0 = 0x8000803108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_DLL_VREG_CONFIG_1_P3_ADR32S1 = 0x8000843107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_DLL_VREG_CONFIG_1_P3_ADR32S1 = 0x8000843108011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S0 = 0x8000803D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S0 = 0x8000803D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S0 = 0x8000803D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S1 = 0x8000843D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S1 = 0x8000843D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S1 = 0x8000843D0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_DLL_VREG_CONTROL_P1_ADR32S0 = 0x8000803D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_DLL_VREG_CONTROL_P1_ADR32S0 = 0x8000803D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_DLL_VREG_CONTROL_P1_ADR32S1 = 0x8000843D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_DLL_VREG_CONTROL_P1_ADR32S1 = 0x8000843D0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_DLL_VREG_CONTROL_P2_ADR32S0 = 0x8000803D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_DLL_VREG_CONTROL_P2_ADR32S0 = 0x8000803D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_DLL_VREG_CONTROL_P2_ADR32S1 = 0x8000843D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_DLL_VREG_CONTROL_P2_ADR32S1 = 0x8000843D0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_DLL_VREG_CONTROL_P3_ADR32S0 = 0x8000803D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_DLL_VREG_CONTROL_P3_ADR32S0 = 0x8000803D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_DLL_VREG_CONTROL_P3_ADR32S1 = 0x8000843D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_DLL_VREG_CONTROL_P3_ADR32S1 = 0x8000843D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0 = 0x800040200701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0 = 0x800040200701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0 = 0x800040200801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1 = 0x800044200701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1 = 0x800044200701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1 = 0x800044200801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2 = 0x800048200701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2 = 0x800048200701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2 = 0x800048200801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3 = 0x80004C200701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3 = 0x80004C200701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3 = 0x80004C200801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR0 = 0x800040200701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR0 = 0x800040200801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR1 = 0x800044200701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR1 = 0x800044200801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR2 = 0x800048200701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR2 = 0x800048200801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR3 = 0x80004C200701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR3 = 0x80004C200801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P2_ADR0 = 0x800040200701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P2_ADR0 = 0x800040200801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P2_ADR1 = 0x800044200701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P2_ADR1 = 0x800044200801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P2_ADR2 = 0x800048200701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P2_ADR2 = 0x800048200801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P2_ADR3 = 0x80004C200701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P2_ADR3 = 0x80004C200801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P3_ADR0 = 0x8000402007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P3_ADR0 = 0x8000402008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P3_ADR1 = 0x8000442007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P3_ADR1 = 0x8000442008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P3_ADR2 = 0x8000482007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P3_ADR2 = 0x8000482008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P3_ADR3 = 0x80004C2007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P3_ADR3 = 0x80004C2008011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0 = 0x800040210701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0 = 0x800040210701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0 = 0x800040210801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1 = 0x800044210701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1 = 0x800044210701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1 = 0x800044210801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2 = 0x800048210701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2 = 0x800048210701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2 = 0x800048210801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR3 = 0x80004C210701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR3 = 0x80004C210701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR3 = 0x80004C210801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR0 = 0x800040210701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR0 = 0x800040210801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR1 = 0x800044210701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR1 = 0x800044210801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR2 = 0x800048210701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR2 = 0x800048210801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR3 = 0x80004C210701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR3 = 0x80004C210801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P2_ADR0 = 0x800040210701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P2_ADR0 = 0x800040210801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P2_ADR1 = 0x800044210701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P2_ADR1 = 0x800044210801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P2_ADR2 = 0x800048210701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P2_ADR2 = 0x800048210801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P2_ADR3 = 0x80004C210701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P2_ADR3 = 0x80004C210801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P3_ADR0 = 0x8000402107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P3_ADR0 = 0x8000402108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P3_ADR1 = 0x8000442107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P3_ADR1 = 0x8000442108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P3_ADR2 = 0x8000482107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P3_ADR2 = 0x8000482108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P3_ADR3 = 0x80004C2107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P3_ADR3 = 0x80004C2108011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET_P0_ADR32S0 = 0x800080330701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET_P0_ADR32S0 = 0x800080330701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET_P0_ADR32S0 = 0x800080330801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET_P0_ADR32S1 = 0x800084330701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET_P0_ADR32S1 = 0x800084330701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET_P0_ADR32S1 = 0x800084330801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET_P1_ADR32S0 = 0x800080330701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET_P1_ADR32S0 = 0x800080330801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET_P1_ADR32S1 = 0x800084330701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET_P1_ADR32S1 = 0x800084330801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET_P2_ADR32S0 = 0x800080330701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET_P2_ADR32S0 = 0x800080330801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET_P2_ADR32S1 = 0x800084330701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET_P2_ADR32S1 = 0x800084330801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET_P3_ADR32S0 = 0x8000803307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET_P3_ADR32S0 = 0x8000803308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET_P3_ADR32S1 = 0x8000843307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET_P3_ADR32S1 = 0x8000843308011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE0_P0_ADR32S0 = 0x800080360701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE0_P0_ADR32S0 = 0x800080360701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE0_P0_ADR32S0 = 0x800080360801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE0_P0_ADR32S1 = 0x800084360701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE0_P0_ADR32S1 = 0x800084360701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE0_P0_ADR32S1 = 0x800084360801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE0_P1_ADR32S0 = 0x800080360701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE0_P1_ADR32S0 = 0x800080360801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE0_P1_ADR32S1 = 0x800084360701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE0_P1_ADR32S1 = 0x800084360801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE0_P2_ADR32S0 = 0x800080360701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE0_P2_ADR32S0 = 0x800080360801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE0_P2_ADR32S1 = 0x800084360701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE0_P2_ADR32S1 = 0x800084360801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE0_P3_ADR32S0 = 0x8000803607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE0_P3_ADR32S0 = 0x8000803608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE0_P3_ADR32S1 = 0x8000843607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE0_P3_ADR32S1 = 0x8000843608011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE1_P0_ADR32S0 = 0x800080370701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE1_P0_ADR32S0 = 0x800080370701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE1_P0_ADR32S0 = 0x800080370801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE1_P0_ADR32S1 = 0x800084370701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE1_P0_ADR32S1 = 0x800084370701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE1_P0_ADR32S1 = 0x800084370801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE1_P1_ADR32S0 = 0x800080370701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE1_P1_ADR32S0 = 0x800080370801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE1_P1_ADR32S1 = 0x800084370701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE1_P1_ADR32S1 = 0x800084370801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE1_P2_ADR32S0 = 0x800080370701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE1_P2_ADR32S0 = 0x800080370801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE1_P2_ADR32S1 = 0x800084370701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE1_P2_ADR32S1 = 0x800084370801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE1_P3_ADR32S0 = 0x8000803707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE1_P3_ADR32S0 = 0x8000803708011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE1_P3_ADR32S1 = 0x8000843707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE1_P3_ADR32S1 = 0x8000843708011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S0 = 0x800080350701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S0 = 0x800080350701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S0 = 0x800080350801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S1 = 0x800084350701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S1 = 0x800084350701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S1 = 0x800084350801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P1_ADR32S0 = 0x800080350701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P1_ADR32S0 = 0x800080350801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P1_ADR32S1 = 0x800084350701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P1_ADR32S1 = 0x800084350801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P2_ADR32S0 = 0x800080350701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P2_ADR32S0 = 0x800080350801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P2_ADR32S1 = 0x800084350701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P2_ADR32S1 = 0x800084350801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P3_ADR32S0 = 0x8000803507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P3_ADR32S0 = 0x8000803508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P3_ADR32S1 = 0x8000843507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P3_ADR32S1 = 0x8000843508011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR0 = 0x8000402C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_POWERDOWN_2_P0_ADR0 = 0x8000402C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_POWERDOWN_2_P0_ADR0 = 0x8000402C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR1 = 0x8000442C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_POWERDOWN_2_P0_ADR1 = 0x8000442C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_POWERDOWN_2_P0_ADR1 = 0x8000442C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR2 = 0x8000482C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_POWERDOWN_2_P0_ADR2 = 0x8000482C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_POWERDOWN_2_P0_ADR2 = 0x8000482C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR3 = 0x80004C2C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_POWERDOWN_2_P0_ADR3 = 0x80004C2C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_POWERDOWN_2_P0_ADR3 = 0x80004C2C0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_POWERDOWN_2_P1_ADR0 = 0x8000402C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_POWERDOWN_2_P1_ADR0 = 0x8000402C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_POWERDOWN_2_P1_ADR1 = 0x8000442C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_POWERDOWN_2_P1_ADR1 = 0x8000442C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_POWERDOWN_2_P1_ADR2 = 0x8000482C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_POWERDOWN_2_P1_ADR2 = 0x8000482C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_POWERDOWN_2_P1_ADR3 = 0x80004C2C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_POWERDOWN_2_P1_ADR3 = 0x80004C2C0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_POWERDOWN_2_P2_ADR0 = 0x8000402C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_POWERDOWN_2_P2_ADR0 = 0x8000402C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_POWERDOWN_2_P2_ADR1 = 0x8000442C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_POWERDOWN_2_P2_ADR1 = 0x8000442C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_POWERDOWN_2_P2_ADR2 = 0x8000482C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_POWERDOWN_2_P2_ADR2 = 0x8000482C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_POWERDOWN_2_P2_ADR3 = 0x80004C2C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_POWERDOWN_2_P2_ADR3 = 0x80004C2C0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_POWERDOWN_2_P3_ADR0 = 0x8000402C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_POWERDOWN_2_P3_ADR0 = 0x8000402C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_POWERDOWN_2_P3_ADR1 = 0x8000442C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_POWERDOWN_2_P3_ADR1 = 0x8000442C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_POWERDOWN_2_P3_ADR2 = 0x8000482C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_POWERDOWN_2_P3_ADR2 = 0x8000482C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_POWERDOWN_2_P3_ADR3 = 0x80004C2C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_POWERDOWN_2_P3_ADR3 = 0x80004C2C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0 = 0x800080320701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0 = 0x800080320701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0 = 0x800080320801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1 = 0x800084320701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1 = 0x800084320701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1 = 0x800084320801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S0 = 0x800080320701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S0 = 0x800080320801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S1 = 0x800084320701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S1 = 0x800084320801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_SYSCLK_CNTL_PR_P2_ADR32S0 = 0x800080320701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_SYSCLK_CNTL_PR_P2_ADR32S0 = 0x800080320801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_SYSCLK_CNTL_PR_P2_ADR32S1 = 0x800084320701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_SYSCLK_CNTL_PR_P2_ADR32S1 = 0x800084320801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_SYSCLK_CNTL_PR_P3_ADR32S0 = 0x8000803207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_SYSCLK_CNTL_PR_P3_ADR32S0 = 0x8000803208011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_SYSCLK_CNTL_PR_P3_ADR32S1 = 0x8000843207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_SYSCLK_CNTL_PR_P3_ADR32S1 = 0x8000843208011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S0 = 0x800080340701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S0 = 0x800080340701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S0 = 0x800080340801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S1 = 0x800084340701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S1 = 0x800084340701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S1 = 0x800084340801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P1_ADR32S0 = 0x800080340701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P1_ADR32S0 = 0x800080340801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P1_ADR32S1 = 0x800084340701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P1_ADR32S1 = 0x800084340801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P2_ADR32S0 = 0x800080340701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P2_ADR32S0 = 0x800080340801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P2_ADR32S1 = 0x800084340701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P2_ADR32S1 = 0x800084340801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P3_ADR32S0 = 0x8000803407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P3_ADR32S0 = 0x8000803408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P3_ADR32S1 = 0x8000843407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P3_ADR32S1 = 0x8000843408011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_APB_ATEST_MUX_SEL_P0 = 0x8000D0050701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_APB_ATEST_MUX_SEL_P0 = 0x8000D0050701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_APB_ATEST_MUX_SEL_P0 = 0x8000D0050801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_APB_ATEST_MUX_SEL_P1 = 0x8000D0050701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_APB_ATEST_MUX_SEL_P1 = 0x8000D0050801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_APB_ATEST_MUX_SEL_P2 = 0x8000D0050701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_APB_ATEST_MUX_SEL_P2 = 0x8000D0050801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_APB_ATEST_MUX_SEL_P3 = 0x8000D00507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_APB_ATEST_MUX_SEL_P3 = 0x8000D00508011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_APB_CONFIG0_P0 = 0x8000D0000701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_APB_CONFIG0_P0 = 0x8000D0000701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_APB_CONFIG0_P0 = 0x8000D0000801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_APB_CONFIG0_P1 = 0x8000D0000701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_APB_CONFIG0_P1 = 0x8000D0000801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_APB_CONFIG0_P2 = 0x8000D0000701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_APB_CONFIG0_P2 = 0x8000D0000801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_APB_CONFIG0_P3 = 0x8000D00007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_APB_CONFIG0_P3 = 0x8000D00008011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_APB_ERROR_MASK0_P0 = 0x8000D0020701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_APB_ERROR_MASK0_P0 = 0x8000D0020701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_APB_ERROR_MASK0_P0 = 0x8000D0020801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_APB_ERROR_MASK0_P1 = 0x8000D0020701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_APB_ERROR_MASK0_P1 = 0x8000D0020801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_APB_ERROR_MASK0_P2 = 0x8000D0020701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_APB_ERROR_MASK0_P2 = 0x8000D0020801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_APB_ERROR_MASK0_P3 = 0x8000D00207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_APB_ERROR_MASK0_P3 = 0x8000D00208011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_APB_ERROR_STATUS0_P0 = 0x8000D0010701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_APB_ERROR_STATUS0_P0 = 0x8000D0010701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_APB_ERROR_STATUS0_P0 = 0x8000D0010801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_APB_ERROR_STATUS0_P1 = 0x8000D0010701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_APB_ERROR_STATUS0_P1 = 0x8000D0010801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_APB_ERROR_STATUS0_P2 = 0x8000D0010701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_APB_ERROR_STATUS0_P2 = 0x8000D0010801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_APB_ERROR_STATUS0_P3 = 0x8000D00107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_APB_ERROR_STATUS0_P3 = 0x8000D00108011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_APB_FIR_ERR0_P0 = 0x8000D0060701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_APB_FIR_ERR0_P0 = 0x8000D0060701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_APB_FIR_ERR0_P0 = 0x8000D0060801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_APB_FIR_ERR0_P1 = 0x8000D0060701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_APB_FIR_ERR0_P1 = 0x8000D0060801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_APB_FIR_ERR0_P2 = 0x8000D0060701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_APB_FIR_ERR0_P2 = 0x8000D0060801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_APB_FIR_ERR0_P3 = 0x8000D00607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_APB_FIR_ERR0_P3 = 0x8000D00608011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_APB_FIR_ERR1_P0 = 0x8000D0070701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_APB_FIR_ERR1_P0 = 0x8000D0070701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_APB_FIR_ERR1_P0 = 0x8000D0070801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_APB_FIR_ERR1_P1 = 0x8000D0070701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_APB_FIR_ERR1_P1 = 0x8000D0070801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_APB_FIR_ERR1_P2 = 0x8000D0070701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_APB_FIR_ERR1_P2 = 0x8000D0070801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_APB_FIR_ERR1_P3 = 0x8000D00707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_APB_FIR_ERR1_P3 = 0x8000D00708011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_APB_FIR_ERR2_P0 = 0x8000D0030701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_APB_FIR_ERR2_P0 = 0x8000D0030701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_APB_FIR_ERR2_P0 = 0x8000D0030801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_APB_FIR_ERR2_P1 = 0x8000D0030701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_APB_FIR_ERR2_P1 = 0x8000D0030801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_APB_FIR_ERR2_P2 = 0x8000D0030701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_APB_FIR_ERR2_P2 = 0x8000D0030801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_APB_FIR_ERR2_P3 = 0x8000D00307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_APB_FIR_ERR2_P3 = 0x8000D00308011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_APB_FIR_ERR3_P0 = 0x8000D0040701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_APB_FIR_ERR3_P0 = 0x8000D0040701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_APB_FIR_ERR3_P0 = 0x8000D0040801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_APB_FIR_ERR3_P1 = 0x8000D0040701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_APB_FIR_ERR3_P1 = 0x8000D0040801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_APB_FIR_ERR3_P2 = 0x8000D0040701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_APB_FIR_ERR3_P2 = 0x8000D0040801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_APB_FIR_ERR3_P3 = 0x8000D00407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_APB_FIR_ERR3_P3 = 0x8000D00408011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_APB_LO_PROBE_SEL_P0 = 0x8000D0080701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_APB_LO_PROBE_SEL_P0 = 0x8000D0080701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_APB_LO_PROBE_SEL_P0 = 0x8000D0080801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_APB_LO_PROBE_SEL_P1 = 0x8000D0080701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_APB_LO_PROBE_SEL_P1 = 0x8000D0080801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_APB_LO_PROBE_SEL_P2 = 0x8000D0080701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_APB_LO_PROBE_SEL_P2 = 0x8000D0080801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_APB_LO_PROBE_SEL_P3 = 0x8000D00807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_APB_LO_PROBE_SEL_P3 = 0x8000D00808011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_0 = 0x800000220701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_0 = 0x800000220701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_0 = 0x800000220801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_1 = 0x800004220701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_1 = 0x800004220701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_1 = 0x800004220801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_2 = 0x800008220701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_2 = 0x800008220701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_2 = 0x800008220801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_3 = 0x80000C220701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_3 = 0x80000C220701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_3 = 0x80000C220801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_4 = 0x800010220701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_4 = 0x800010220701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_4 = 0x800010220801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P1_0 = 0x800000220701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P1_0 = 0x800000220801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P1_1 = 0x800004220701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P1_1 = 0x800004220801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P1_2 = 0x800008220701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P1_2 = 0x800008220801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P1_3 = 0x80000C220701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P1_3 = 0x80000C220801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P1_4 = 0x800010220701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P1_4 = 0x800010220801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P2_0 = 0x800000220701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P2_0 = 0x800000220801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P2_1 = 0x800004220701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P2_1 = 0x800004220801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P2_2 = 0x800008220701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P2_2 = 0x800008220801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P2_3 = 0x80000C220701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P2_3 = 0x80000C220801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P2_4 = 0x800010220701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P2_4 = 0x800010220801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P3_0 = 0x8000002207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P3_0 = 0x8000002208011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P3_1 = 0x8000042207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P3_1 = 0x8000042208011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P3_2 = 0x8000082207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P3_2 = 0x8000082208011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P3_3 = 0x80000C2207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P3_3 = 0x80000C2208011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P3_4 = 0x8000102207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P3_4 = 0x8000102208011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_0 = 0x800000230701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_0 = 0x800000230701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_0 = 0x800000230801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_1 = 0x800004230701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_1 = 0x800004230701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_1 = 0x800004230801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_2 = 0x800008230701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_2 = 0x800008230701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_2 = 0x800008230801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_3 = 0x80000C230701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_3 = 0x80000C230701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_3 = 0x80000C230801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_4 = 0x800010230701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_4 = 0x800010230701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_4 = 0x800010230801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P1_0 = 0x800000230701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P1_0 = 0x800000230801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P1_1 = 0x800004230701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P1_1 = 0x800004230801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P1_2 = 0x800008230701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P1_2 = 0x800008230801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P1_3 = 0x80000C230701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P1_3 = 0x80000C230801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P1_4 = 0x800010230701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P1_4 = 0x800010230801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P2_0 = 0x800000230701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P2_0 = 0x800000230801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P2_1 = 0x800004230701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P2_1 = 0x800004230801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P2_2 = 0x800008230701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P2_2 = 0x800008230801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P2_3 = 0x80000C230701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P2_3 = 0x80000C230801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P2_4 = 0x800010230701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P2_4 = 0x800010230801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P3_0 = 0x8000002307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P3_0 = 0x8000002308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P3_1 = 0x8000042307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P3_1 = 0x8000042308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P3_2 = 0x8000082307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P3_2 = 0x8000082308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P3_3 = 0x80000C2307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P3_3 = 0x80000C2308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P3_4 = 0x8000102307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P3_4 = 0x8000102308011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_0 = 0x800000030701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_CONFIG0_P0_0 = 0x800000030701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_CONFIG0_P0_0 = 0x800000030801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_1 = 0x800004030701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_CONFIG0_P0_1 = 0x800004030701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_CONFIG0_P0_1 = 0x800004030801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_2 = 0x800008030701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_CONFIG0_P0_2 = 0x800008030701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_CONFIG0_P0_2 = 0x800008030801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_3 = 0x80000C030701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_CONFIG0_P0_3 = 0x80000C030701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_CONFIG0_P0_3 = 0x80000C030801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_4 = 0x800010030701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_CONFIG0_P0_4 = 0x800010030701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_CONFIG0_P0_4 = 0x800010030801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_CONFIG0_P1_0 = 0x800000030701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_CONFIG0_P1_0 = 0x800000030801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_CONFIG0_P1_1 = 0x800004030701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_CONFIG0_P1_1 = 0x800004030801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_CONFIG0_P1_2 = 0x800008030701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_CONFIG0_P1_2 = 0x800008030801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_CONFIG0_P1_3 = 0x80000C030701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_CONFIG0_P1_3 = 0x80000C030801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_CONFIG0_P1_4 = 0x800010030701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_CONFIG0_P1_4 = 0x800010030801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_CONFIG0_P2_0 = 0x800000030701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_CONFIG0_P2_0 = 0x800000030801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_CONFIG0_P2_1 = 0x800004030701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_CONFIG0_P2_1 = 0x800004030801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_CONFIG0_P2_2 = 0x800008030701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_CONFIG0_P2_2 = 0x800008030801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_CONFIG0_P2_3 = 0x80000C030701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_CONFIG0_P2_3 = 0x80000C030801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_CONFIG0_P2_4 = 0x800010030701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_CONFIG0_P2_4 = 0x800010030801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_CONFIG0_P3_0 = 0x8000000307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_CONFIG0_P3_0 = 0x8000000308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_CONFIG0_P3_1 = 0x8000040307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_CONFIG0_P3_1 = 0x8000040308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_CONFIG0_P3_2 = 0x8000080307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_CONFIG0_P3_2 = 0x8000080308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_CONFIG0_P3_3 = 0x80000C0307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_CONFIG0_P3_3 = 0x80000C0308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_CONFIG0_P3_4 = 0x8000100307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_CONFIG0_P3_4 = 0x8000100308011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0 = 0x800000200701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0 = 0x800000200701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0 = 0x800000200801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1 = 0x800004200701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1 = 0x800004200701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1 = 0x800004200801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2 = 0x800008200701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2 = 0x800008200701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2 = 0x800008200801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3 = 0x80000C200701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3 = 0x80000C200701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3 = 0x80000C200801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4 = 0x800010200701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4 = 0x800010200701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4 = 0x800010200801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_CTLE_CTL_BYTE0_P1_0 = 0x800000200701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_CTLE_CTL_BYTE0_P1_0 = 0x800000200801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_CTLE_CTL_BYTE0_P1_1 = 0x800004200701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_CTLE_CTL_BYTE0_P1_1 = 0x800004200801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_CTLE_CTL_BYTE0_P1_2 = 0x800008200701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_CTLE_CTL_BYTE0_P1_2 = 0x800008200801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_CTLE_CTL_BYTE0_P1_3 = 0x80000C200701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_CTLE_CTL_BYTE0_P1_3 = 0x80000C200801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_CTLE_CTL_BYTE0_P1_4 = 0x800010200701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_CTLE_CTL_BYTE0_P1_4 = 0x800010200801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_CTLE_CTL_BYTE0_P2_0 = 0x800000200701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_CTLE_CTL_BYTE0_P2_0 = 0x800000200801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_CTLE_CTL_BYTE0_P2_1 = 0x800004200701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_CTLE_CTL_BYTE0_P2_1 = 0x800004200801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_CTLE_CTL_BYTE0_P2_2 = 0x800008200701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_CTLE_CTL_BYTE0_P2_2 = 0x800008200801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_CTLE_CTL_BYTE0_P2_3 = 0x80000C200701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_CTLE_CTL_BYTE0_P2_3 = 0x80000C200801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_CTLE_CTL_BYTE0_P2_4 = 0x800010200701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_CTLE_CTL_BYTE0_P2_4 = 0x800010200801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_CTLE_CTL_BYTE0_P3_0 = 0x8000002007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_CTLE_CTL_BYTE0_P3_0 = 0x8000002008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_CTLE_CTL_BYTE0_P3_1 = 0x8000042007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_CTLE_CTL_BYTE0_P3_1 = 0x8000042008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_CTLE_CTL_BYTE0_P3_2 = 0x8000082007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_CTLE_CTL_BYTE0_P3_2 = 0x8000082008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_CTLE_CTL_BYTE0_P3_3 = 0x80000C2007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_CTLE_CTL_BYTE0_P3_3 = 0x80000C2008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_CTLE_CTL_BYTE0_P3_4 = 0x8000102007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_CTLE_CTL_BYTE0_P3_4 = 0x8000102008011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0 = 0x800000210701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0 = 0x800000210701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0 = 0x800000210801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1 = 0x800004210701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1 = 0x800004210701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1 = 0x800004210801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2 = 0x800008210701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2 = 0x800008210701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2 = 0x800008210801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3 = 0x80000C210701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3 = 0x80000C210701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3 = 0x80000C210801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4 = 0x800010210701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4 = 0x800010210701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4 = 0x800010210801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_CTLE_CTL_BYTE1_P1_0 = 0x800000210701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_CTLE_CTL_BYTE1_P1_0 = 0x800000210801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_CTLE_CTL_BYTE1_P1_1 = 0x800004210701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_CTLE_CTL_BYTE1_P1_1 = 0x800004210801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_CTLE_CTL_BYTE1_P1_2 = 0x800008210701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_CTLE_CTL_BYTE1_P1_2 = 0x800008210801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_CTLE_CTL_BYTE1_P1_3 = 0x80000C210701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_CTLE_CTL_BYTE1_P1_3 = 0x80000C210801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_CTLE_CTL_BYTE1_P1_4 = 0x800010210701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_CTLE_CTL_BYTE1_P1_4 = 0x800010210801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_CTLE_CTL_BYTE1_P2_0 = 0x800000210701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_CTLE_CTL_BYTE1_P2_0 = 0x800000210801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_CTLE_CTL_BYTE1_P2_1 = 0x800004210701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_CTLE_CTL_BYTE1_P2_1 = 0x800004210801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_CTLE_CTL_BYTE1_P2_2 = 0x800008210701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_CTLE_CTL_BYTE1_P2_2 = 0x800008210801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_CTLE_CTL_BYTE1_P2_3 = 0x80000C210701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_CTLE_CTL_BYTE1_P2_3 = 0x80000C210801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_CTLE_CTL_BYTE1_P2_4 = 0x800010210701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_CTLE_CTL_BYTE1_P2_4 = 0x800010210801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_CTLE_CTL_BYTE1_P3_0 = 0x8000002107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_CTLE_CTL_BYTE1_P3_0 = 0x8000002108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_CTLE_CTL_BYTE1_P3_1 = 0x8000042107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_CTLE_CTL_BYTE1_P3_1 = 0x8000042108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_CTLE_CTL_BYTE1_P3_2 = 0x8000082107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_CTLE_CTL_BYTE1_P3_2 = 0x8000082108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_CTLE_CTL_BYTE1_P3_3 = 0x80000C2107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_CTLE_CTL_BYTE1_P3_3 = 0x80000C2108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_CTLE_CTL_BYTE1_P3_4 = 0x8000102107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_CTLE_CTL_BYTE1_P3_4 = 0x8000102108011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_0 = 0x800000A40701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DCD_CONTROL0_P0_0 = 0x800000A40701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DCD_CONTROL0_P0_0 = 0x800000A40801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_1 = 0x800004A40701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DCD_CONTROL0_P0_1 = 0x800004A40701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DCD_CONTROL0_P0_1 = 0x800004A40801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_2 = 0x800008A40701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DCD_CONTROL0_P0_2 = 0x800008A40701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DCD_CONTROL0_P0_2 = 0x800008A40801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_3 = 0x80000CA40701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DCD_CONTROL0_P0_3 = 0x80000CA40701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DCD_CONTROL0_P0_3 = 0x80000CA40801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_4 = 0x800010A40701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DCD_CONTROL0_P0_4 = 0x800010A40701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DCD_CONTROL0_P0_4 = 0x800010A40801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DCD_CONTROL0_P1_0 = 0x800000A40701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DCD_CONTROL0_P1_0 = 0x800000A40801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DCD_CONTROL0_P1_1 = 0x800004A40701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DCD_CONTROL0_P1_1 = 0x800004A40801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DCD_CONTROL0_P1_2 = 0x800008A40701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DCD_CONTROL0_P1_2 = 0x800008A40801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DCD_CONTROL0_P1_3 = 0x80000CA40701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DCD_CONTROL0_P1_3 = 0x80000CA40801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DCD_CONTROL0_P1_4 = 0x800010A40701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DCD_CONTROL0_P1_4 = 0x800010A40801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DCD_CONTROL0_P2_0 = 0x800000A40701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DCD_CONTROL0_P2_0 = 0x800000A40801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DCD_CONTROL0_P2_1 = 0x800004A40701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DCD_CONTROL0_P2_1 = 0x800004A40801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DCD_CONTROL0_P2_2 = 0x800008A40701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DCD_CONTROL0_P2_2 = 0x800008A40801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DCD_CONTROL0_P2_3 = 0x80000CA40701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DCD_CONTROL0_P2_3 = 0x80000CA40801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DCD_CONTROL0_P2_4 = 0x800010A40701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DCD_CONTROL0_P2_4 = 0x800010A40801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DCD_CONTROL0_P3_0 = 0x800000A407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DCD_CONTROL0_P3_0 = 0x800000A408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DCD_CONTROL0_P3_1 = 0x800004A407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DCD_CONTROL0_P3_1 = 0x800004A408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DCD_CONTROL0_P3_2 = 0x800008A407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DCD_CONTROL0_P3_2 = 0x800008A408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DCD_CONTROL0_P3_3 = 0x80000CA407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DCD_CONTROL0_P3_3 = 0x80000CA408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DCD_CONTROL0_P3_4 = 0x800010A407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DCD_CONTROL0_P3_4 = 0x800010A408011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_0 = 0x800000A50701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DCD_CONTROL1_P0_0 = 0x800000A50701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DCD_CONTROL1_P0_0 = 0x800000A50801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_1 = 0x800004A50701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DCD_CONTROL1_P0_1 = 0x800004A50701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DCD_CONTROL1_P0_1 = 0x800004A50801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_2 = 0x800008A50701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DCD_CONTROL1_P0_2 = 0x800008A50701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DCD_CONTROL1_P0_2 = 0x800008A50801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_3 = 0x80000CA50701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DCD_CONTROL1_P0_3 = 0x80000CA50701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DCD_CONTROL1_P0_3 = 0x80000CA50801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_4 = 0x800010A50701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DCD_CONTROL1_P0_4 = 0x800010A50701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DCD_CONTROL1_P0_4 = 0x800010A50801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DCD_CONTROL1_P1_0 = 0x800000A50701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DCD_CONTROL1_P1_0 = 0x800000A50801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DCD_CONTROL1_P1_1 = 0x800004A50701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DCD_CONTROL1_P1_1 = 0x800004A50801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DCD_CONTROL1_P1_2 = 0x800008A50701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DCD_CONTROL1_P1_2 = 0x800008A50801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DCD_CONTROL1_P1_3 = 0x80000CA50701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DCD_CONTROL1_P1_3 = 0x80000CA50801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DCD_CONTROL1_P1_4 = 0x800010A50701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DCD_CONTROL1_P1_4 = 0x800010A50801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DCD_CONTROL1_P2_0 = 0x800000A50701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DCD_CONTROL1_P2_0 = 0x800000A50801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DCD_CONTROL1_P2_1 = 0x800004A50701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DCD_CONTROL1_P2_1 = 0x800004A50801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DCD_CONTROL1_P2_2 = 0x800008A50701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DCD_CONTROL1_P2_2 = 0x800008A50801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DCD_CONTROL1_P2_3 = 0x80000CA50701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DCD_CONTROL1_P2_3 = 0x80000CA50801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DCD_CONTROL1_P2_4 = 0x800010A50701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DCD_CONTROL1_P2_4 = 0x800010A50801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DCD_CONTROL1_P3_0 = 0x800000A507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DCD_CONTROL1_P3_0 = 0x800000A508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DCD_CONTROL1_P3_1 = 0x800004A507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DCD_CONTROL1_P3_1 = 0x800004A508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DCD_CONTROL1_P3_2 = 0x800008A507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DCD_CONTROL1_P3_2 = 0x800008A508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DCD_CONTROL1_P3_3 = 0x80000CA507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DCD_CONTROL1_P3_3 = 0x80000CA508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DCD_CONTROL1_P3_4 = 0x800010A507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DCD_CONTROL1_P3_4 = 0x800010A508011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DEBUG_SEL_P0_0 = 0x8000000B0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DEBUG_SEL_P0_0 = 0x8000000B0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DEBUG_SEL_P0_0 = 0x8000000B0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DEBUG_SEL_P0_1 = 0x8000040B0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DEBUG_SEL_P0_1 = 0x8000040B0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DEBUG_SEL_P0_1 = 0x8000040B0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DEBUG_SEL_P0_2 = 0x8000080B0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DEBUG_SEL_P0_2 = 0x8000080B0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DEBUG_SEL_P0_2 = 0x8000080B0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DEBUG_SEL_P0_3 = 0x80000C0B0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DEBUG_SEL_P0_3 = 0x80000C0B0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DEBUG_SEL_P0_3 = 0x80000C0B0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DEBUG_SEL_P0_4 = 0x8000100B0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DEBUG_SEL_P0_4 = 0x8000100B0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DEBUG_SEL_P0_4 = 0x8000100B0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DEBUG_SEL_P1_0 = 0x8000000B0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DEBUG_SEL_P1_0 = 0x8000000B0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DEBUG_SEL_P1_1 = 0x8000040B0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DEBUG_SEL_P1_1 = 0x8000040B0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DEBUG_SEL_P1_2 = 0x8000080B0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DEBUG_SEL_P1_2 = 0x8000080B0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DEBUG_SEL_P1_3 = 0x80000C0B0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DEBUG_SEL_P1_3 = 0x80000C0B0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DEBUG_SEL_P1_4 = 0x8000100B0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DEBUG_SEL_P1_4 = 0x8000100B0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DEBUG_SEL_P2_0 = 0x8000000B0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DEBUG_SEL_P2_0 = 0x8000000B0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DEBUG_SEL_P2_1 = 0x8000040B0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DEBUG_SEL_P2_1 = 0x8000040B0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DEBUG_SEL_P2_2 = 0x8000080B0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DEBUG_SEL_P2_2 = 0x8000080B0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DEBUG_SEL_P2_3 = 0x80000C0B0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DEBUG_SEL_P2_3 = 0x80000C0B0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DEBUG_SEL_P2_4 = 0x8000100B0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DEBUG_SEL_P2_4 = 0x8000100B0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DEBUG_SEL_P3_0 = 0x8000000B07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DEBUG_SEL_P3_0 = 0x8000000B08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DEBUG_SEL_P3_1 = 0x8000040B07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DEBUG_SEL_P3_1 = 0x8000040B08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DEBUG_SEL_P3_2 = 0x8000080B07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DEBUG_SEL_P3_2 = 0x8000080B08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DEBUG_SEL_P3_3 = 0x80000C0B07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DEBUG_SEL_P3_3 = 0x80000C0B08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DEBUG_SEL_P3_4 = 0x8000100B07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DEBUG_SEL_P3_4 = 0x8000100B08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_0 = 0x8000006F0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_0 = 0x8000006F0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_0 = 0x8000006F0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_1 = 0x8000046F0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_1 = 0x8000046F0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_1 = 0x8000046F0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_2 = 0x8000086F0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_2 = 0x8000086F0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_2 = 0x8000086F0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_3 = 0x80000C6F0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_3 = 0x80000C6F0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_3 = 0x80000C6F0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_4 = 0x8000106F0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_4 = 0x8000106F0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_4 = 0x8000106F0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P1_0 = 0x8000006F0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P1_0 = 0x8000006F0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P1_1 = 0x8000046F0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P1_1 = 0x8000046F0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P1_2 = 0x8000086F0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P1_2 = 0x8000086F0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P1_3 = 0x80000C6F0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P1_3 = 0x80000C6F0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P1_4 = 0x8000106F0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P1_4 = 0x8000106F0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P2_0 = 0x8000006F0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P2_0 = 0x8000006F0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P2_1 = 0x8000046F0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P2_1 = 0x8000046F0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P2_2 = 0x8000086F0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P2_2 = 0x8000086F0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P2_3 = 0x80000C6F0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P2_3 = 0x80000C6F0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P2_4 = 0x8000106F0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P2_4 = 0x8000106F0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P3_0 = 0x8000006F07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P3_0 = 0x8000006F08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P3_1 = 0x8000046F07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P3_1 = 0x8000046F08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P3_2 = 0x8000086F07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P3_2 = 0x8000086F08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P3_3 = 0x80000C6F07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P3_3 = 0x80000C6F08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P3_4 = 0x8000106F07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P3_4 = 0x8000106F08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_0 = 0x800000080701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DFT_DIG_EYE_P0_0 = 0x800000080701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DFT_DIG_EYE_P0_0 = 0x800000080801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_1 = 0x800004080701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DFT_DIG_EYE_P0_1 = 0x800004080701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DFT_DIG_EYE_P0_1 = 0x800004080801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_2 = 0x800008080701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DFT_DIG_EYE_P0_2 = 0x800008080701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DFT_DIG_EYE_P0_2 = 0x800008080801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_3 = 0x80000C080701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DFT_DIG_EYE_P0_3 = 0x80000C080701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DFT_DIG_EYE_P0_3 = 0x80000C080801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_4 = 0x800010080701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DFT_DIG_EYE_P0_4 = 0x800010080701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DFT_DIG_EYE_P0_4 = 0x800010080801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DFT_DIG_EYE_P1_0 = 0x800000080701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DFT_DIG_EYE_P1_0 = 0x800000080801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DFT_DIG_EYE_P1_1 = 0x800004080701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DFT_DIG_EYE_P1_1 = 0x800004080801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DFT_DIG_EYE_P1_2 = 0x800008080701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DFT_DIG_EYE_P1_2 = 0x800008080801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DFT_DIG_EYE_P1_3 = 0x80000C080701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DFT_DIG_EYE_P1_3 = 0x80000C080801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DFT_DIG_EYE_P1_4 = 0x800010080701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DFT_DIG_EYE_P1_4 = 0x800010080801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DFT_DIG_EYE_P2_0 = 0x800000080701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DFT_DIG_EYE_P2_0 = 0x800000080801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DFT_DIG_EYE_P2_1 = 0x800004080701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DFT_DIG_EYE_P2_1 = 0x800004080801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DFT_DIG_EYE_P2_2 = 0x800008080701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DFT_DIG_EYE_P2_2 = 0x800008080801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DFT_DIG_EYE_P2_3 = 0x80000C080701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DFT_DIG_EYE_P2_3 = 0x80000C080801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DFT_DIG_EYE_P2_4 = 0x800010080701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DFT_DIG_EYE_P2_4 = 0x800010080801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DFT_DIG_EYE_P3_0 = 0x8000000807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DFT_DIG_EYE_P3_0 = 0x8000000808011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DFT_DIG_EYE_P3_1 = 0x8000040807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DFT_DIG_EYE_P3_1 = 0x8000040808011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DFT_DIG_EYE_P3_2 = 0x8000080807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DFT_DIG_EYE_P3_2 = 0x8000080808011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DFT_DIG_EYE_P3_3 = 0x80000C0807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DFT_DIG_EYE_P3_3 = 0x80000C0808011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DFT_DIG_EYE_P3_4 = 0x8000100807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DFT_DIG_EYE_P3_4 = 0x8000100808011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DFT_PDA_CONTROL_P0_0 = 0x800000010701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DFT_PDA_CONTROL_P0_0 = 0x800000010701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DFT_PDA_CONTROL_P0_0 = 0x800000010801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DFT_PDA_CONTROL_P0_1 = 0x800004010701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DFT_PDA_CONTROL_P0_1 = 0x800004010701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DFT_PDA_CONTROL_P0_1 = 0x800004010801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DFT_PDA_CONTROL_P0_2 = 0x800008010701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DFT_PDA_CONTROL_P0_2 = 0x800008010701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DFT_PDA_CONTROL_P0_2 = 0x800008010801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DFT_PDA_CONTROL_P0_3 = 0x80000C010701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DFT_PDA_CONTROL_P0_3 = 0x80000C010701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DFT_PDA_CONTROL_P0_3 = 0x80000C010801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DFT_PDA_CONTROL_P0_4 = 0x800010010701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DFT_PDA_CONTROL_P0_4 = 0x800010010701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DFT_PDA_CONTROL_P0_4 = 0x800010010801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DFT_PDA_CONTROL_P1_0 = 0x800000010701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DFT_PDA_CONTROL_P1_0 = 0x800000010801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DFT_PDA_CONTROL_P1_1 = 0x800004010701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DFT_PDA_CONTROL_P1_1 = 0x800004010801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DFT_PDA_CONTROL_P1_2 = 0x800008010701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DFT_PDA_CONTROL_P1_2 = 0x800008010801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DFT_PDA_CONTROL_P1_3 = 0x80000C010701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DFT_PDA_CONTROL_P1_3 = 0x80000C010801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DFT_PDA_CONTROL_P1_4 = 0x800010010701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DFT_PDA_CONTROL_P1_4 = 0x800010010801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DFT_PDA_CONTROL_P2_0 = 0x800000010701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DFT_PDA_CONTROL_P2_0 = 0x800000010801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DFT_PDA_CONTROL_P2_1 = 0x800004010701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DFT_PDA_CONTROL_P2_1 = 0x800004010801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DFT_PDA_CONTROL_P2_2 = 0x800008010701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DFT_PDA_CONTROL_P2_2 = 0x800008010801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DFT_PDA_CONTROL_P2_3 = 0x80000C010701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DFT_PDA_CONTROL_P2_3 = 0x80000C010801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DFT_PDA_CONTROL_P2_4 = 0x800010010701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DFT_PDA_CONTROL_P2_4 = 0x800010010801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DFT_PDA_CONTROL_P3_0 = 0x8000000107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DFT_PDA_CONTROL_P3_0 = 0x8000000108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DFT_PDA_CONTROL_P3_1 = 0x8000040107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DFT_PDA_CONTROL_P3_1 = 0x8000040108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DFT_PDA_CONTROL_P3_2 = 0x8000080107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DFT_PDA_CONTROL_P3_2 = 0x8000080108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DFT_PDA_CONTROL_P3_3 = 0x80000C0107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DFT_PDA_CONTROL_P3_3 = 0x80000C0108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DFT_PDA_CONTROL_P3_4 = 0x8000100107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DFT_PDA_CONTROL_P3_4 = 0x8000100108011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_0 = 0x8000001D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DFT_WRAP_STATUS_P0_0 = 0x8000001D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DFT_WRAP_STATUS_P0_0 = 0x8000001D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_1 = 0x8000041D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DFT_WRAP_STATUS_P0_1 = 0x8000041D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DFT_WRAP_STATUS_P0_1 = 0x8000041D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_2 = 0x8000081D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DFT_WRAP_STATUS_P0_2 = 0x8000081D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DFT_WRAP_STATUS_P0_2 = 0x8000081D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_3 = 0x80000C1D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DFT_WRAP_STATUS_P0_3 = 0x80000C1D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DFT_WRAP_STATUS_P0_3 = 0x80000C1D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_4 = 0x8000101D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DFT_WRAP_STATUS_P0_4 = 0x8000101D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DFT_WRAP_STATUS_P0_4 = 0x8000101D0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DFT_WRAP_STATUS_P1_0 = 0x8000001D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DFT_WRAP_STATUS_P1_0 = 0x8000001D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DFT_WRAP_STATUS_P1_1 = 0x8000041D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DFT_WRAP_STATUS_P1_1 = 0x8000041D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DFT_WRAP_STATUS_P1_2 = 0x8000081D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DFT_WRAP_STATUS_P1_2 = 0x8000081D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DFT_WRAP_STATUS_P1_3 = 0x80000C1D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DFT_WRAP_STATUS_P1_3 = 0x80000C1D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DFT_WRAP_STATUS_P1_4 = 0x8000101D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DFT_WRAP_STATUS_P1_4 = 0x8000101D0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DFT_WRAP_STATUS_P2_0 = 0x8000001D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DFT_WRAP_STATUS_P2_0 = 0x8000001D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DFT_WRAP_STATUS_P2_1 = 0x8000041D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DFT_WRAP_STATUS_P2_1 = 0x8000041D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DFT_WRAP_STATUS_P2_2 = 0x8000081D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DFT_WRAP_STATUS_P2_2 = 0x8000081D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DFT_WRAP_STATUS_P2_3 = 0x80000C1D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DFT_WRAP_STATUS_P2_3 = 0x80000C1D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DFT_WRAP_STATUS_P2_4 = 0x8000101D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DFT_WRAP_STATUS_P2_4 = 0x8000101D0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DFT_WRAP_STATUS_P3_0 = 0x8000001D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DFT_WRAP_STATUS_P3_0 = 0x8000001D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DFT_WRAP_STATUS_P3_1 = 0x8000041D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DFT_WRAP_STATUS_P3_1 = 0x8000041D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DFT_WRAP_STATUS_P3_2 = 0x8000081D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DFT_WRAP_STATUS_P3_2 = 0x8000081D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DFT_WRAP_STATUS_P3_3 = 0x80000C1D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DFT_WRAP_STATUS_P3_3 = 0x80000C1D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DFT_WRAP_STATUS_P3_4 = 0x8000101D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DFT_WRAP_STATUS_P3_4 = 0x8000101D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_0 = 0x800000240701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_CNTL0_P0_0 = 0x800000240701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_CNTL0_P0_0 = 0x800000240801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_1 = 0x800004240701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_CNTL0_P0_1 = 0x800004240701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_CNTL0_P0_1 = 0x800004240801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_2 = 0x800008240701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_CNTL0_P0_2 = 0x800008240701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_CNTL0_P0_2 = 0x800008240801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_3 = 0x80000C240701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_CNTL0_P0_3 = 0x80000C240701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_CNTL0_P0_3 = 0x80000C240801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_4 = 0x800010240701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_CNTL0_P0_4 = 0x800010240701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_CNTL0_P0_4 = 0x800010240801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_CNTL0_P1_0 = 0x800000240701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_CNTL0_P1_0 = 0x800000240801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_CNTL0_P1_1 = 0x800004240701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_CNTL0_P1_1 = 0x800004240801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_CNTL0_P1_2 = 0x800008240701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_CNTL0_P1_2 = 0x800008240801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_CNTL0_P1_3 = 0x80000C240701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_CNTL0_P1_3 = 0x80000C240801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_CNTL0_P1_4 = 0x800010240701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_CNTL0_P1_4 = 0x800010240801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_CNTL0_P2_0 = 0x800000240701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_CNTL0_P2_0 = 0x800000240801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_CNTL0_P2_1 = 0x800004240701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_CNTL0_P2_1 = 0x800004240801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_CNTL0_P2_2 = 0x800008240701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_CNTL0_P2_2 = 0x800008240801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_CNTL0_P2_3 = 0x80000C240701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_CNTL0_P2_3 = 0x80000C240801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_CNTL0_P2_4 = 0x800010240701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_CNTL0_P2_4 = 0x800010240801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_CNTL0_P3_0 = 0x8000002407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_CNTL0_P3_0 = 0x8000002408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_CNTL0_P3_1 = 0x8000042407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_CNTL0_P3_1 = 0x8000042408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_CNTL0_P3_2 = 0x8000082407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_CNTL0_P3_2 = 0x8000082408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_CNTL0_P3_3 = 0x80000C2407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_CNTL0_P3_3 = 0x80000C2408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_CNTL0_P3_4 = 0x8000102407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_CNTL0_P3_4 = 0x8000102408011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_0 = 0x800000250701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_CNTL1_P0_0 = 0x800000250701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_CNTL1_P0_0 = 0x800000250801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_1 = 0x800004250701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_CNTL1_P0_1 = 0x800004250701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_CNTL1_P0_1 = 0x800004250801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_2 = 0x800008250701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_CNTL1_P0_2 = 0x800008250701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_CNTL1_P0_2 = 0x800008250801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_3 = 0x80000C250701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_CNTL1_P0_3 = 0x80000C250701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_CNTL1_P0_3 = 0x80000C250801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_4 = 0x800010250701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_CNTL1_P0_4 = 0x800010250701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_CNTL1_P0_4 = 0x800010250801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_CNTL1_P1_0 = 0x800000250701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_CNTL1_P1_0 = 0x800000250801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_CNTL1_P1_1 = 0x800004250701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_CNTL1_P1_1 = 0x800004250801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_CNTL1_P1_2 = 0x800008250701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_CNTL1_P1_2 = 0x800008250801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_CNTL1_P1_3 = 0x80000C250701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_CNTL1_P1_3 = 0x80000C250801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_CNTL1_P1_4 = 0x800010250701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_CNTL1_P1_4 = 0x800010250801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_CNTL1_P2_0 = 0x800000250701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_CNTL1_P2_0 = 0x800000250801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_CNTL1_P2_1 = 0x800004250701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_CNTL1_P2_1 = 0x800004250801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_CNTL1_P2_2 = 0x800008250701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_CNTL1_P2_2 = 0x800008250801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_CNTL1_P2_3 = 0x80000C250701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_CNTL1_P2_3 = 0x80000C250801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_CNTL1_P2_4 = 0x800010250701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_CNTL1_P2_4 = 0x800010250801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_CNTL1_P3_0 = 0x8000002507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_CNTL1_P3_0 = 0x8000002508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_CNTL1_P3_1 = 0x8000042507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_CNTL1_P3_1 = 0x8000042508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_CNTL1_P3_2 = 0x8000082507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_CNTL1_P3_2 = 0x8000082508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_CNTL1_P3_3 = 0x80000C2507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_CNTL1_P3_3 = 0x80000C2508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_CNTL1_P3_4 = 0x8000102507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_CNTL1_P3_4 = 0x8000102508011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_CONFIG1_P0_0 = 0x800000770701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_CONFIG1_P0_0 = 0x800000770701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_CONFIG1_P0_0 = 0x800000770801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_CONFIG1_P0_1 = 0x800004770701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_CONFIG1_P0_1 = 0x800004770701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_CONFIG1_P0_1 = 0x800004770801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_CONFIG1_P0_2 = 0x800008770701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_CONFIG1_P0_2 = 0x800008770701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_CONFIG1_P0_2 = 0x800008770801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_CONFIG1_P0_3 = 0x80000C770701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_CONFIG1_P0_3 = 0x80000C770701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_CONFIG1_P0_3 = 0x80000C770801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_CONFIG1_P0_4 = 0x800010770701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_CONFIG1_P0_4 = 0x800010770701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_CONFIG1_P0_4 = 0x800010770801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_CONFIG1_P1_0 = 0x800000770701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_CONFIG1_P1_0 = 0x800000770801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_CONFIG1_P1_1 = 0x800004770701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_CONFIG1_P1_1 = 0x800004770801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_CONFIG1_P1_2 = 0x800008770701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_CONFIG1_P1_2 = 0x800008770801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_CONFIG1_P1_3 = 0x80000C770701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_CONFIG1_P1_3 = 0x80000C770801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_CONFIG1_P1_4 = 0x800010770701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_CONFIG1_P1_4 = 0x800010770801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_CONFIG1_P2_0 = 0x800000770701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_CONFIG1_P2_0 = 0x800000770801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_CONFIG1_P2_1 = 0x800004770701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_CONFIG1_P2_1 = 0x800004770801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_CONFIG1_P2_2 = 0x800008770701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_CONFIG1_P2_2 = 0x800008770801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_CONFIG1_P2_3 = 0x80000C770701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_CONFIG1_P2_3 = 0x80000C770801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_CONFIG1_P2_4 = 0x800010770701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_CONFIG1_P2_4 = 0x800010770801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_CONFIG1_P3_0 = 0x8000007707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_CONFIG1_P3_0 = 0x8000007708011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_CONFIG1_P3_1 = 0x8000047707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_CONFIG1_P3_1 = 0x8000047708011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_CONFIG1_P3_2 = 0x8000087707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_CONFIG1_P3_2 = 0x8000087708011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_CONFIG1_P3_3 = 0x80000C7707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_CONFIG1_P3_3 = 0x80000C7708011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_CONFIG1_P3_4 = 0x8000107707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_CONFIG1_P3_4 = 0x8000107708011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_0 = 0x800000260701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_DAC_LOWER0_P0_0 = 0x800000260701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_DAC_LOWER0_P0_0 = 0x800000260801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_1 = 0x800004260701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_DAC_LOWER0_P0_1 = 0x800004260701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_DAC_LOWER0_P0_1 = 0x800004260801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_2 = 0x800008260701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_DAC_LOWER0_P0_2 = 0x800008260701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_DAC_LOWER0_P0_2 = 0x800008260801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_3 = 0x80000C260701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_DAC_LOWER0_P0_3 = 0x80000C260701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_DAC_LOWER0_P0_3 = 0x80000C260801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_4 = 0x800010260701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_DAC_LOWER0_P0_4 = 0x800010260701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_DAC_LOWER0_P0_4 = 0x800010260801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_DAC_LOWER0_P1_0 = 0x800000260701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_DAC_LOWER0_P1_0 = 0x800000260801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_DAC_LOWER0_P1_1 = 0x800004260701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_DAC_LOWER0_P1_1 = 0x800004260801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_DAC_LOWER0_P1_2 = 0x800008260701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_DAC_LOWER0_P1_2 = 0x800008260801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_DAC_LOWER0_P1_3 = 0x80000C260701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_DAC_LOWER0_P1_3 = 0x80000C260801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_DAC_LOWER0_P1_4 = 0x800010260701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_DAC_LOWER0_P1_4 = 0x800010260801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_DAC_LOWER0_P2_0 = 0x800000260701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_DAC_LOWER0_P2_0 = 0x800000260801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_DAC_LOWER0_P2_1 = 0x800004260701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_DAC_LOWER0_P2_1 = 0x800004260801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_DAC_LOWER0_P2_2 = 0x800008260701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_DAC_LOWER0_P2_2 = 0x800008260801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_DAC_LOWER0_P2_3 = 0x80000C260701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_DAC_LOWER0_P2_3 = 0x80000C260801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_DAC_LOWER0_P2_4 = 0x800010260701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_DAC_LOWER0_P2_4 = 0x800010260801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_DAC_LOWER0_P3_0 = 0x8000002607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_DAC_LOWER0_P3_0 = 0x8000002608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_DAC_LOWER0_P3_1 = 0x8000042607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_DAC_LOWER0_P3_1 = 0x8000042608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_DAC_LOWER0_P3_2 = 0x8000082607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_DAC_LOWER0_P3_2 = 0x8000082608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_DAC_LOWER0_P3_3 = 0x80000C2607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_DAC_LOWER0_P3_3 = 0x80000C2608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_DAC_LOWER0_P3_4 = 0x8000102607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_DAC_LOWER0_P3_4 = 0x8000102608011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_0 = 0x800000270701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_DAC_LOWER1_P0_0 = 0x800000270701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_DAC_LOWER1_P0_0 = 0x800000270801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_1 = 0x800004270701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_DAC_LOWER1_P0_1 = 0x800004270701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_DAC_LOWER1_P0_1 = 0x800004270801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_2 = 0x800008270701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_DAC_LOWER1_P0_2 = 0x800008270701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_DAC_LOWER1_P0_2 = 0x800008270801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_3 = 0x80000C270701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_DAC_LOWER1_P0_3 = 0x80000C270701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_DAC_LOWER1_P0_3 = 0x80000C270801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_4 = 0x800010270701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_DAC_LOWER1_P0_4 = 0x800010270701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_DAC_LOWER1_P0_4 = 0x800010270801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_DAC_LOWER1_P1_0 = 0x800000270701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_DAC_LOWER1_P1_0 = 0x800000270801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_DAC_LOWER1_P1_1 = 0x800004270701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_DAC_LOWER1_P1_1 = 0x800004270801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_DAC_LOWER1_P1_2 = 0x800008270701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_DAC_LOWER1_P1_2 = 0x800008270801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_DAC_LOWER1_P1_3 = 0x80000C270701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_DAC_LOWER1_P1_3 = 0x80000C270801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_DAC_LOWER1_P1_4 = 0x800010270701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_DAC_LOWER1_P1_4 = 0x800010270801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_DAC_LOWER1_P2_0 = 0x800000270701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_DAC_LOWER1_P2_0 = 0x800000270801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_DAC_LOWER1_P2_1 = 0x800004270701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_DAC_LOWER1_P2_1 = 0x800004270801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_DAC_LOWER1_P2_2 = 0x800008270701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_DAC_LOWER1_P2_2 = 0x800008270801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_DAC_LOWER1_P2_3 = 0x80000C270701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_DAC_LOWER1_P2_3 = 0x80000C270801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_DAC_LOWER1_P2_4 = 0x800010270701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_DAC_LOWER1_P2_4 = 0x800010270801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_DAC_LOWER1_P3_0 = 0x8000002707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_DAC_LOWER1_P3_0 = 0x8000002708011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_DAC_LOWER1_P3_1 = 0x8000042707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_DAC_LOWER1_P3_1 = 0x8000042708011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_DAC_LOWER1_P3_2 = 0x8000082707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_DAC_LOWER1_P3_2 = 0x8000082708011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_DAC_LOWER1_P3_3 = 0x80000C2707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_DAC_LOWER1_P3_3 = 0x80000C2708011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_DAC_LOWER1_P3_4 = 0x8000102707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_DAC_LOWER1_P3_4 = 0x8000102708011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_0 = 0x800000280701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_DAC_UPPER0_P0_0 = 0x800000280701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_DAC_UPPER0_P0_0 = 0x800000280801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_1 = 0x800004280701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_DAC_UPPER0_P0_1 = 0x800004280701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_DAC_UPPER0_P0_1 = 0x800004280801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_2 = 0x800008280701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_DAC_UPPER0_P0_2 = 0x800008280701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_DAC_UPPER0_P0_2 = 0x800008280801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_3 = 0x80000C280701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_DAC_UPPER0_P0_3 = 0x80000C280701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_DAC_UPPER0_P0_3 = 0x80000C280801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_4 = 0x800010280701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_DAC_UPPER0_P0_4 = 0x800010280701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_DAC_UPPER0_P0_4 = 0x800010280801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_DAC_UPPER0_P1_0 = 0x800000280701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_DAC_UPPER0_P1_0 = 0x800000280801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_DAC_UPPER0_P1_1 = 0x800004280701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_DAC_UPPER0_P1_1 = 0x800004280801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_DAC_UPPER0_P1_2 = 0x800008280701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_DAC_UPPER0_P1_2 = 0x800008280801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_DAC_UPPER0_P1_3 = 0x80000C280701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_DAC_UPPER0_P1_3 = 0x80000C280801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_DAC_UPPER0_P1_4 = 0x800010280701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_DAC_UPPER0_P1_4 = 0x800010280801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_DAC_UPPER0_P2_0 = 0x800000280701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_DAC_UPPER0_P2_0 = 0x800000280801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_DAC_UPPER0_P2_1 = 0x800004280701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_DAC_UPPER0_P2_1 = 0x800004280801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_DAC_UPPER0_P2_2 = 0x800008280701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_DAC_UPPER0_P2_2 = 0x800008280801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_DAC_UPPER0_P2_3 = 0x80000C280701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_DAC_UPPER0_P2_3 = 0x80000C280801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_DAC_UPPER0_P2_4 = 0x800010280701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_DAC_UPPER0_P2_4 = 0x800010280801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_DAC_UPPER0_P3_0 = 0x8000002807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_DAC_UPPER0_P3_0 = 0x8000002808011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_DAC_UPPER0_P3_1 = 0x8000042807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_DAC_UPPER0_P3_1 = 0x8000042808011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_DAC_UPPER0_P3_2 = 0x8000082807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_DAC_UPPER0_P3_2 = 0x8000082808011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_DAC_UPPER0_P3_3 = 0x80000C2807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_DAC_UPPER0_P3_3 = 0x80000C2808011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_DAC_UPPER0_P3_4 = 0x8000102807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_DAC_UPPER0_P3_4 = 0x8000102808011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_0 = 0x800000290701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_DAC_UPPER1_P0_0 = 0x800000290701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_DAC_UPPER1_P0_0 = 0x800000290801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_1 = 0x800004290701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_DAC_UPPER1_P0_1 = 0x800004290701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_DAC_UPPER1_P0_1 = 0x800004290801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_2 = 0x800008290701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_DAC_UPPER1_P0_2 = 0x800008290701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_DAC_UPPER1_P0_2 = 0x800008290801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_3 = 0x80000C290701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_DAC_UPPER1_P0_3 = 0x80000C290701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_DAC_UPPER1_P0_3 = 0x80000C290801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_4 = 0x800010290701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_DAC_UPPER1_P0_4 = 0x800010290701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_DAC_UPPER1_P0_4 = 0x800010290801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_DAC_UPPER1_P1_0 = 0x800000290701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_DAC_UPPER1_P1_0 = 0x800000290801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_DAC_UPPER1_P1_1 = 0x800004290701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_DAC_UPPER1_P1_1 = 0x800004290801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_DAC_UPPER1_P1_2 = 0x800008290701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_DAC_UPPER1_P1_2 = 0x800008290801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_DAC_UPPER1_P1_3 = 0x80000C290701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_DAC_UPPER1_P1_3 = 0x80000C290801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_DAC_UPPER1_P1_4 = 0x800010290701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_DAC_UPPER1_P1_4 = 0x800010290801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_DAC_UPPER1_P2_0 = 0x800000290701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_DAC_UPPER1_P2_0 = 0x800000290801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_DAC_UPPER1_P2_1 = 0x800004290701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_DAC_UPPER1_P2_1 = 0x800004290801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_DAC_UPPER1_P2_2 = 0x800008290701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_DAC_UPPER1_P2_2 = 0x800008290801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_DAC_UPPER1_P2_3 = 0x80000C290701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_DAC_UPPER1_P2_3 = 0x80000C290801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_DAC_UPPER1_P2_4 = 0x800010290701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_DAC_UPPER1_P2_4 = 0x800010290801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_DAC_UPPER1_P3_0 = 0x8000002907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_DAC_UPPER1_P3_0 = 0x8000002908011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_DAC_UPPER1_P3_1 = 0x8000042907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_DAC_UPPER1_P3_1 = 0x8000042908011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_DAC_UPPER1_P3_2 = 0x8000082907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_DAC_UPPER1_P3_2 = 0x8000082908011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_DAC_UPPER1_P3_3 = 0x80000C2907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_DAC_UPPER1_P3_3 = 0x80000C2908011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_DAC_UPPER1_P3_4 = 0x8000102907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_DAC_UPPER1_P3_4 = 0x8000102908011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA0_P0_0 = 0x800000AC0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_EXTRA0_P0_0 = 0x800000AC0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_EXTRA0_P0_0 = 0x800000AC0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA0_P0_1 = 0x800004AC0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_EXTRA0_P0_1 = 0x800004AC0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_EXTRA0_P0_1 = 0x800004AC0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA0_P0_2 = 0x800008AC0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_EXTRA0_P0_2 = 0x800008AC0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_EXTRA0_P0_2 = 0x800008AC0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA0_P0_3 = 0x80000CAC0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_EXTRA0_P0_3 = 0x80000CAC0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_EXTRA0_P0_3 = 0x80000CAC0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA0_P0_4 = 0x800010AC0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_EXTRA0_P0_4 = 0x800010AC0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_EXTRA0_P0_4 = 0x800010AC0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_EXTRA0_P1_0 = 0x800000AC0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_EXTRA0_P1_0 = 0x800000AC0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_EXTRA0_P1_1 = 0x800004AC0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_EXTRA0_P1_1 = 0x800004AC0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_EXTRA0_P1_2 = 0x800008AC0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_EXTRA0_P1_2 = 0x800008AC0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_EXTRA0_P1_3 = 0x80000CAC0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_EXTRA0_P1_3 = 0x80000CAC0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_EXTRA0_P1_4 = 0x800010AC0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_EXTRA0_P1_4 = 0x800010AC0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_EXTRA0_P2_0 = 0x800000AC0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_EXTRA0_P2_0 = 0x800000AC0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_EXTRA0_P2_1 = 0x800004AC0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_EXTRA0_P2_1 = 0x800004AC0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_EXTRA0_P2_2 = 0x800008AC0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_EXTRA0_P2_2 = 0x800008AC0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_EXTRA0_P2_3 = 0x80000CAC0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_EXTRA0_P2_3 = 0x80000CAC0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_EXTRA0_P2_4 = 0x800010AC0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_EXTRA0_P2_4 = 0x800010AC0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_EXTRA0_P3_0 = 0x800000AC07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_EXTRA0_P3_0 = 0x800000AC08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_EXTRA0_P3_1 = 0x800004AC07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_EXTRA0_P3_1 = 0x800004AC08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_EXTRA0_P3_2 = 0x800008AC07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_EXTRA0_P3_2 = 0x800008AC08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_EXTRA0_P3_3 = 0x80000CAC07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_EXTRA0_P3_3 = 0x80000CAC08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_EXTRA0_P3_4 = 0x800010AC07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_EXTRA0_P3_4 = 0x800010AC08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA1_P0_0 = 0x800000AD0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_EXTRA1_P0_0 = 0x800000AD0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_EXTRA1_P0_0 = 0x800000AD0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA1_P0_1 = 0x800004AD0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_EXTRA1_P0_1 = 0x800004AD0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_EXTRA1_P0_1 = 0x800004AD0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA1_P0_2 = 0x800008AD0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_EXTRA1_P0_2 = 0x800008AD0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_EXTRA1_P0_2 = 0x800008AD0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA1_P0_3 = 0x80000CAD0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_EXTRA1_P0_3 = 0x80000CAD0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_EXTRA1_P0_3 = 0x80000CAD0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA1_P0_4 = 0x800010AD0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_EXTRA1_P0_4 = 0x800010AD0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_EXTRA1_P0_4 = 0x800010AD0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_EXTRA1_P1_0 = 0x800000AD0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_EXTRA1_P1_0 = 0x800000AD0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_EXTRA1_P1_1 = 0x800004AD0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_EXTRA1_P1_1 = 0x800004AD0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_EXTRA1_P1_2 = 0x800008AD0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_EXTRA1_P1_2 = 0x800008AD0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_EXTRA1_P1_3 = 0x80000CAD0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_EXTRA1_P1_3 = 0x80000CAD0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_EXTRA1_P1_4 = 0x800010AD0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_EXTRA1_P1_4 = 0x800010AD0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_EXTRA1_P2_0 = 0x800000AD0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_EXTRA1_P2_0 = 0x800000AD0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_EXTRA1_P2_1 = 0x800004AD0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_EXTRA1_P2_1 = 0x800004AD0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_EXTRA1_P2_2 = 0x800008AD0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_EXTRA1_P2_2 = 0x800008AD0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_EXTRA1_P2_3 = 0x80000CAD0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_EXTRA1_P2_3 = 0x80000CAD0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_EXTRA1_P2_4 = 0x800010AD0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_EXTRA1_P2_4 = 0x800010AD0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_EXTRA1_P3_0 = 0x800000AD07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_EXTRA1_P3_0 = 0x800000AD08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_EXTRA1_P3_1 = 0x800004AD07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_EXTRA1_P3_1 = 0x800004AD08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_EXTRA1_P3_2 = 0x800008AD07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_EXTRA1_P3_2 = 0x800008AD08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_EXTRA1_P3_3 = 0x80000CAD07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_EXTRA1_P3_3 = 0x80000CAD08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_EXTRA1_P3_4 = 0x800010AD07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_EXTRA1_P3_4 = 0x800010AD08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_0 = 0x800000A80701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_0 = 0x800000A80701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_0 = 0x800000A80801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_1 = 0x800004A80701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_1 = 0x800004A80701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_1 = 0x800004A80801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_2 = 0x800008A80701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_2 = 0x800008A80701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_2 = 0x800008A80801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_3 = 0x80000CA80701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_3 = 0x80000CA80701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_3 = 0x80000CA80801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_4 = 0x800010A80701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_4 = 0x800010A80701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_4 = 0x800010A80801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P1_0 = 0x800000A80701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P1_0 = 0x800000A80801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P1_1 = 0x800004A80701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P1_1 = 0x800004A80801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P1_2 = 0x800008A80701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P1_2 = 0x800008A80801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P1_3 = 0x80000CA80701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P1_3 = 0x80000CA80801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P1_4 = 0x800010A80701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P1_4 = 0x800010A80801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P2_0 = 0x800000A80701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P2_0 = 0x800000A80801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P2_1 = 0x800004A80701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P2_1 = 0x800004A80801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P2_2 = 0x800008A80701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P2_2 = 0x800008A80801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P2_3 = 0x80000CA80701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P2_3 = 0x80000CA80801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P2_4 = 0x800010A80701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P2_4 = 0x800010A80801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P3_0 = 0x800000A807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P3_0 = 0x800000A808011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P3_1 = 0x800004A807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P3_1 = 0x800004A808011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P3_2 = 0x800008A807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P3_2 = 0x800008A808011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P3_3 = 0x80000CA807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P3_3 = 0x80000CA808011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P3_4 = 0x800010A807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P3_4 = 0x800010A808011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_0 = 0x800000A90701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_0 = 0x800000A90701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_0 = 0x800000A90801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_1 = 0x800004A90701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_1 = 0x800004A90701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_1 = 0x800004A90801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_2 = 0x800008A90701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_2 = 0x800008A90701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_2 = 0x800008A90801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_3 = 0x80000CA90701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_3 = 0x80000CA90701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_3 = 0x80000CA90801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_4 = 0x800010A90701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_4 = 0x800010A90701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_4 = 0x800010A90801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P1_0 = 0x800000A90701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P1_0 = 0x800000A90801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P1_1 = 0x800004A90701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P1_1 = 0x800004A90801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P1_2 = 0x800008A90701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P1_2 = 0x800008A90801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P1_3 = 0x80000CA90701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P1_3 = 0x80000CA90801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P1_4 = 0x800010A90701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P1_4 = 0x800010A90801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P2_0 = 0x800000A90701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P2_0 = 0x800000A90801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P2_1 = 0x800004A90701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P2_1 = 0x800004A90801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P2_2 = 0x800008A90701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P2_2 = 0x800008A90801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P2_3 = 0x80000CA90701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P2_3 = 0x80000CA90801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P2_4 = 0x800010A90701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P2_4 = 0x800010A90801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P3_0 = 0x800000A907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P3_0 = 0x800000A908011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P3_1 = 0x800004A907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P3_1 = 0x800004A908011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P3_2 = 0x800008A907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P3_2 = 0x800008A908011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P3_3 = 0x80000CA907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P3_3 = 0x80000CA908011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P3_4 = 0x800010A907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P3_4 = 0x800010A908011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_0 = 0x800000AA0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_0 = 0x800000AA0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_0 = 0x800000AA0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_1 = 0x800004AA0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_1 = 0x800004AA0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_1 = 0x800004AA0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_2 = 0x800008AA0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_2 = 0x800008AA0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_2 = 0x800008AA0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_3 = 0x80000CAA0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_3 = 0x80000CAA0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_3 = 0x80000CAA0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_4 = 0x800010AA0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_4 = 0x800010AA0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_4 = 0x800010AA0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P1_0 = 0x800000AA0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P1_0 = 0x800000AA0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P1_1 = 0x800004AA0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P1_1 = 0x800004AA0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P1_2 = 0x800008AA0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P1_2 = 0x800008AA0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P1_3 = 0x80000CAA0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P1_3 = 0x80000CAA0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P1_4 = 0x800010AA0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P1_4 = 0x800010AA0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P2_0 = 0x800000AA0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P2_0 = 0x800000AA0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P2_1 = 0x800004AA0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P2_1 = 0x800004AA0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P2_2 = 0x800008AA0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P2_2 = 0x800008AA0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P2_3 = 0x80000CAA0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P2_3 = 0x80000CAA0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P2_4 = 0x800010AA0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P2_4 = 0x800010AA0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P3_0 = 0x800000AA07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P3_0 = 0x800000AA08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P3_1 = 0x800004AA07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P3_1 = 0x800004AA08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P3_2 = 0x800008AA07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P3_2 = 0x800008AA08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P3_3 = 0x80000CAA07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P3_3 = 0x80000CAA08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P3_4 = 0x800010AA07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P3_4 = 0x800010AA08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_0 = 0x800000AB0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_0 = 0x800000AB0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_0 = 0x800000AB0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_1 = 0x800004AB0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_1 = 0x800004AB0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_1 = 0x800004AB0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_2 = 0x800008AB0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_2 = 0x800008AB0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_2 = 0x800008AB0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_3 = 0x80000CAB0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_3 = 0x80000CAB0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_3 = 0x80000CAB0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_4 = 0x800010AB0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_4 = 0x800010AB0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_4 = 0x800010AB0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P1_0 = 0x800000AB0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P1_0 = 0x800000AB0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P1_1 = 0x800004AB0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P1_1 = 0x800004AB0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P1_2 = 0x800008AB0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P1_2 = 0x800008AB0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P1_3 = 0x80000CAB0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P1_3 = 0x80000CAB0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P1_4 = 0x800010AB0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P1_4 = 0x800010AB0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P2_0 = 0x800000AB0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P2_0 = 0x800000AB0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P2_1 = 0x800004AB0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P2_1 = 0x800004AB0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P2_2 = 0x800008AB0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P2_2 = 0x800008AB0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P2_3 = 0x80000CAB0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P2_3 = 0x80000CAB0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P2_4 = 0x800010AB0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P2_4 = 0x800010AB0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P3_0 = 0x800000AB07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P3_0 = 0x800000AB08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P3_1 = 0x800004AB07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P3_1 = 0x800004AB08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P3_2 = 0x800008AB07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P3_2 = 0x800008AB08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P3_3 = 0x80000CAB07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P3_3 = 0x80000CAB08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P3_4 = 0x800010AB07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P3_4 = 0x800010AB08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_0 = 0x800000A60701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_SW_CONTROL0_P0_0 = 0x800000A60701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_SW_CONTROL0_P0_0 = 0x800000A60801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_1 = 0x800004A60701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_SW_CONTROL0_P0_1 = 0x800004A60701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_SW_CONTROL0_P0_1 = 0x800004A60801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_2 = 0x800008A60701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_SW_CONTROL0_P0_2 = 0x800008A60701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_SW_CONTROL0_P0_2 = 0x800008A60801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_3 = 0x80000CA60701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_SW_CONTROL0_P0_3 = 0x80000CA60701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_SW_CONTROL0_P0_3 = 0x80000CA60801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_4 = 0x800010A60701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_SW_CONTROL0_P0_4 = 0x800010A60701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_SW_CONTROL0_P0_4 = 0x800010A60801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_SW_CONTROL0_P1_0 = 0x800000A60701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_SW_CONTROL0_P1_0 = 0x800000A60801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_SW_CONTROL0_P1_1 = 0x800004A60701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_SW_CONTROL0_P1_1 = 0x800004A60801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_SW_CONTROL0_P1_2 = 0x800008A60701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_SW_CONTROL0_P1_2 = 0x800008A60801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_SW_CONTROL0_P1_3 = 0x80000CA60701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_SW_CONTROL0_P1_3 = 0x80000CA60801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_SW_CONTROL0_P1_4 = 0x800010A60701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_SW_CONTROL0_P1_4 = 0x800010A60801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_SW_CONTROL0_P2_0 = 0x800000A60701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_SW_CONTROL0_P2_0 = 0x800000A60801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_SW_CONTROL0_P2_1 = 0x800004A60701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_SW_CONTROL0_P2_1 = 0x800004A60801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_SW_CONTROL0_P2_2 = 0x800008A60701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_SW_CONTROL0_P2_2 = 0x800008A60801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_SW_CONTROL0_P2_3 = 0x80000CA60701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_SW_CONTROL0_P2_3 = 0x80000CA60801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_SW_CONTROL0_P2_4 = 0x800010A60701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_SW_CONTROL0_P2_4 = 0x800010A60801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_SW_CONTROL0_P3_0 = 0x800000A607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_SW_CONTROL0_P3_0 = 0x800000A608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_SW_CONTROL0_P3_1 = 0x800004A607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_SW_CONTROL0_P3_1 = 0x800004A608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_SW_CONTROL0_P3_2 = 0x800008A607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_SW_CONTROL0_P3_2 = 0x800008A608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_SW_CONTROL0_P3_3 = 0x80000CA607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_SW_CONTROL0_P3_3 = 0x80000CA608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_SW_CONTROL0_P3_4 = 0x800010A607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_SW_CONTROL0_P3_4 = 0x800010A608011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_0 = 0x800000A70701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_SW_CONTROL1_P0_0 = 0x800000A70701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_SW_CONTROL1_P0_0 = 0x800000A70801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_1 = 0x800004A70701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_SW_CONTROL1_P0_1 = 0x800004A70701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_SW_CONTROL1_P0_1 = 0x800004A70801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_2 = 0x800008A70701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_SW_CONTROL1_P0_2 = 0x800008A70701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_SW_CONTROL1_P0_2 = 0x800008A70801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_3 = 0x80000CA70701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_SW_CONTROL1_P0_3 = 0x80000CA70701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_SW_CONTROL1_P0_3 = 0x80000CA70801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_4 = 0x800010A70701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_SW_CONTROL1_P0_4 = 0x800010A70701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_SW_CONTROL1_P0_4 = 0x800010A70801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_SW_CONTROL1_P1_0 = 0x800000A70701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_SW_CONTROL1_P1_0 = 0x800000A70801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_SW_CONTROL1_P1_1 = 0x800004A70701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_SW_CONTROL1_P1_1 = 0x800004A70801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_SW_CONTROL1_P1_2 = 0x800008A70701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_SW_CONTROL1_P1_2 = 0x800008A70801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_SW_CONTROL1_P1_3 = 0x80000CA70701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_SW_CONTROL1_P1_3 = 0x80000CA70801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_SW_CONTROL1_P1_4 = 0x800010A70701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_SW_CONTROL1_P1_4 = 0x800010A70801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_SW_CONTROL1_P2_0 = 0x800000A70701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_SW_CONTROL1_P2_0 = 0x800000A70801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_SW_CONTROL1_P2_1 = 0x800004A70701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_SW_CONTROL1_P2_1 = 0x800004A70801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_SW_CONTROL1_P2_2 = 0x800008A70701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_SW_CONTROL1_P2_2 = 0x800008A70801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_SW_CONTROL1_P2_3 = 0x80000CA70701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_SW_CONTROL1_P2_3 = 0x80000CA70801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_SW_CONTROL1_P2_4 = 0x800010A70701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_SW_CONTROL1_P2_4 = 0x800010A70801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_SW_CONTROL1_P3_0 = 0x800000A707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_SW_CONTROL1_P3_0 = 0x800000A708011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_SW_CONTROL1_P3_1 = 0x800004A707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_SW_CONTROL1_P3_1 = 0x800004A708011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_SW_CONTROL1_P3_2 = 0x800008A707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_SW_CONTROL1_P3_2 = 0x800008A708011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_SW_CONTROL1_P3_3 = 0x80000CA707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_SW_CONTROL1_P3_3 = 0x80000CA708011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_SW_CONTROL1_P3_4 = 0x800010A707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_SW_CONTROL1_P3_4 = 0x800010A708011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_0 = 0x8000002C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_VREG_COARSE0_P0_0 = 0x8000002C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_VREG_COARSE0_P0_0 = 0x8000002C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_1 = 0x8000042C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_VREG_COARSE0_P0_1 = 0x8000042C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_VREG_COARSE0_P0_1 = 0x8000042C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_2 = 0x8000082C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_VREG_COARSE0_P0_2 = 0x8000082C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_VREG_COARSE0_P0_2 = 0x8000082C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_3 = 0x80000C2C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_VREG_COARSE0_P0_3 = 0x80000C2C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_VREG_COARSE0_P0_3 = 0x80000C2C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_4 = 0x8000102C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_VREG_COARSE0_P0_4 = 0x8000102C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_VREG_COARSE0_P0_4 = 0x8000102C0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_VREG_COARSE0_P1_0 = 0x8000002C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_VREG_COARSE0_P1_0 = 0x8000002C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_VREG_COARSE0_P1_1 = 0x8000042C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_VREG_COARSE0_P1_1 = 0x8000042C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_VREG_COARSE0_P1_2 = 0x8000082C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_VREG_COARSE0_P1_2 = 0x8000082C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_VREG_COARSE0_P1_3 = 0x80000C2C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_VREG_COARSE0_P1_3 = 0x80000C2C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_VREG_COARSE0_P1_4 = 0x8000102C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_VREG_COARSE0_P1_4 = 0x8000102C0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_VREG_COARSE0_P2_0 = 0x8000002C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_VREG_COARSE0_P2_0 = 0x8000002C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_VREG_COARSE0_P2_1 = 0x8000042C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_VREG_COARSE0_P2_1 = 0x8000042C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_VREG_COARSE0_P2_2 = 0x8000082C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_VREG_COARSE0_P2_2 = 0x8000082C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_VREG_COARSE0_P2_3 = 0x80000C2C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_VREG_COARSE0_P2_3 = 0x80000C2C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_VREG_COARSE0_P2_4 = 0x8000102C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_VREG_COARSE0_P2_4 = 0x8000102C0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_VREG_COARSE0_P3_0 = 0x8000002C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_VREG_COARSE0_P3_0 = 0x8000002C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_VREG_COARSE0_P3_1 = 0x8000042C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_VREG_COARSE0_P3_1 = 0x8000042C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_VREG_COARSE0_P3_2 = 0x8000082C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_VREG_COARSE0_P3_2 = 0x8000082C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_VREG_COARSE0_P3_3 = 0x80000C2C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_VREG_COARSE0_P3_3 = 0x80000C2C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_VREG_COARSE0_P3_4 = 0x8000102C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_VREG_COARSE0_P3_4 = 0x8000102C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_0 = 0x8000002D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_VREG_COARSE1_P0_0 = 0x8000002D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_VREG_COARSE1_P0_0 = 0x8000002D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_1 = 0x8000042D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_VREG_COARSE1_P0_1 = 0x8000042D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_VREG_COARSE1_P0_1 = 0x8000042D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_2 = 0x8000082D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_VREG_COARSE1_P0_2 = 0x8000082D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_VREG_COARSE1_P0_2 = 0x8000082D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_3 = 0x80000C2D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_VREG_COARSE1_P0_3 = 0x80000C2D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_VREG_COARSE1_P0_3 = 0x80000C2D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_4 = 0x8000102D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_VREG_COARSE1_P0_4 = 0x8000102D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_VREG_COARSE1_P0_4 = 0x8000102D0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_VREG_COARSE1_P1_0 = 0x8000002D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_VREG_COARSE1_P1_0 = 0x8000002D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_VREG_COARSE1_P1_1 = 0x8000042D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_VREG_COARSE1_P1_1 = 0x8000042D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_VREG_COARSE1_P1_2 = 0x8000082D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_VREG_COARSE1_P1_2 = 0x8000082D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_VREG_COARSE1_P1_3 = 0x80000C2D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_VREG_COARSE1_P1_3 = 0x80000C2D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_VREG_COARSE1_P1_4 = 0x8000102D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_VREG_COARSE1_P1_4 = 0x8000102D0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_VREG_COARSE1_P2_0 = 0x8000002D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_VREG_COARSE1_P2_0 = 0x8000002D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_VREG_COARSE1_P2_1 = 0x8000042D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_VREG_COARSE1_P2_1 = 0x8000042D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_VREG_COARSE1_P2_2 = 0x8000082D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_VREG_COARSE1_P2_2 = 0x8000082D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_VREG_COARSE1_P2_3 = 0x80000C2D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_VREG_COARSE1_P2_3 = 0x80000C2D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_VREG_COARSE1_P2_4 = 0x8000102D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_VREG_COARSE1_P2_4 = 0x8000102D0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_VREG_COARSE1_P3_0 = 0x8000002D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_VREG_COARSE1_P3_0 = 0x8000002D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_VREG_COARSE1_P3_1 = 0x8000042D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_VREG_COARSE1_P3_1 = 0x8000042D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_VREG_COARSE1_P3_2 = 0x8000082D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_VREG_COARSE1_P3_2 = 0x8000082D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_VREG_COARSE1_P3_3 = 0x80000C2D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_VREG_COARSE1_P3_3 = 0x80000C2D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_VREG_COARSE1_P3_4 = 0x8000102D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_VREG_COARSE1_P3_4 = 0x8000102D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_0 = 0x8000002A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_0 = 0x8000002A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_0 = 0x8000002A0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_1 = 0x8000042A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_1 = 0x8000042A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_1 = 0x8000042A0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_2 = 0x8000082A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_2 = 0x8000082A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_2 = 0x8000082A0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_3 = 0x80000C2A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_3 = 0x80000C2A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_3 = 0x80000C2A0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_4 = 0x8000102A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_4 = 0x8000102A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_4 = 0x8000102A0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_VREG_CONTROL0_P1_0 = 0x8000002A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_VREG_CONTROL0_P1_0 = 0x8000002A0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_VREG_CONTROL0_P1_1 = 0x8000042A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_VREG_CONTROL0_P1_1 = 0x8000042A0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_VREG_CONTROL0_P1_2 = 0x8000082A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_VREG_CONTROL0_P1_2 = 0x8000082A0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_VREG_CONTROL0_P1_3 = 0x80000C2A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_VREG_CONTROL0_P1_3 = 0x80000C2A0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_VREG_CONTROL0_P1_4 = 0x8000102A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_VREG_CONTROL0_P1_4 = 0x8000102A0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_VREG_CONTROL0_P2_0 = 0x8000002A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_VREG_CONTROL0_P2_0 = 0x8000002A0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_VREG_CONTROL0_P2_1 = 0x8000042A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_VREG_CONTROL0_P2_1 = 0x8000042A0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_VREG_CONTROL0_P2_2 = 0x8000082A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_VREG_CONTROL0_P2_2 = 0x8000082A0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_VREG_CONTROL0_P2_3 = 0x80000C2A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_VREG_CONTROL0_P2_3 = 0x80000C2A0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_VREG_CONTROL0_P2_4 = 0x8000102A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_VREG_CONTROL0_P2_4 = 0x8000102A0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_VREG_CONTROL0_P3_0 = 0x8000002A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_VREG_CONTROL0_P3_0 = 0x8000002A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_VREG_CONTROL0_P3_1 = 0x8000042A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_VREG_CONTROL0_P3_1 = 0x8000042A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_VREG_CONTROL0_P3_2 = 0x8000082A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_VREG_CONTROL0_P3_2 = 0x8000082A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_VREG_CONTROL0_P3_3 = 0x80000C2A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_VREG_CONTROL0_P3_3 = 0x80000C2A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_VREG_CONTROL0_P3_4 = 0x8000102A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_VREG_CONTROL0_P3_4 = 0x8000102A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_0 = 0x8000002B0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_0 = 0x8000002B0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_0 = 0x8000002B0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_1 = 0x8000042B0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_1 = 0x8000042B0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_1 = 0x8000042B0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_2 = 0x8000082B0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_2 = 0x8000082B0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_2 = 0x8000082B0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_3 = 0x80000C2B0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_3 = 0x80000C2B0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_3 = 0x80000C2B0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_4 = 0x8000102B0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_4 = 0x8000102B0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_4 = 0x8000102B0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_VREG_CONTROL1_P1_0 = 0x8000002B0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_VREG_CONTROL1_P1_0 = 0x8000002B0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_VREG_CONTROL1_P1_1 = 0x8000042B0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_VREG_CONTROL1_P1_1 = 0x8000042B0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_VREG_CONTROL1_P1_2 = 0x8000082B0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_VREG_CONTROL1_P1_2 = 0x8000082B0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_VREG_CONTROL1_P1_3 = 0x80000C2B0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_VREG_CONTROL1_P1_3 = 0x80000C2B0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DLL_VREG_CONTROL1_P1_4 = 0x8000102B0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DLL_VREG_CONTROL1_P1_4 = 0x8000102B0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_VREG_CONTROL1_P2_0 = 0x8000002B0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_VREG_CONTROL1_P2_0 = 0x8000002B0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_VREG_CONTROL1_P2_1 = 0x8000042B0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_VREG_CONTROL1_P2_1 = 0x8000042B0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_VREG_CONTROL1_P2_2 = 0x8000082B0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_VREG_CONTROL1_P2_2 = 0x8000082B0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_VREG_CONTROL1_P2_3 = 0x80000C2B0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_VREG_CONTROL1_P2_3 = 0x80000C2B0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DLL_VREG_CONTROL1_P2_4 = 0x8000102B0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DLL_VREG_CONTROL1_P2_4 = 0x8000102B0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_VREG_CONTROL1_P3_0 = 0x8000002B07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_VREG_CONTROL1_P3_0 = 0x8000002B08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_VREG_CONTROL1_P3_1 = 0x8000042B07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_VREG_CONTROL1_P3_1 = 0x8000042B08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_VREG_CONTROL1_P3_2 = 0x8000082B07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_VREG_CONTROL1_P3_2 = 0x8000082B08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_VREG_CONTROL1_P3_3 = 0x80000C2B07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_VREG_CONTROL1_P3_3 = 0x80000C2B08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DLL_VREG_CONTROL1_P3_4 = 0x8000102B07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DLL_VREG_CONTROL1_P3_4 = 0x8000102B08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQSCLK_OFFSET_P0_0 = 0x800000370701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQSCLK_OFFSET_P0_0 = 0x800000370701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQSCLK_OFFSET_P0_0 = 0x800000370801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQSCLK_OFFSET_P0_1 = 0x800004370701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQSCLK_OFFSET_P0_1 = 0x800004370701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQSCLK_OFFSET_P0_1 = 0x800004370801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQSCLK_OFFSET_P0_2 = 0x800008370701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQSCLK_OFFSET_P0_2 = 0x800008370701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQSCLK_OFFSET_P0_2 = 0x800008370801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQSCLK_OFFSET_P0_3 = 0x80000C370701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQSCLK_OFFSET_P0_3 = 0x80000C370701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQSCLK_OFFSET_P0_3 = 0x80000C370801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQSCLK_OFFSET_P0_4 = 0x800010370701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQSCLK_OFFSET_P0_4 = 0x800010370701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQSCLK_OFFSET_P0_4 = 0x800010370801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQSCLK_OFFSET_P1_0 = 0x800000370701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQSCLK_OFFSET_P1_0 = 0x800000370801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQSCLK_OFFSET_P1_1 = 0x800004370701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQSCLK_OFFSET_P1_1 = 0x800004370801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQSCLK_OFFSET_P1_2 = 0x800008370701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQSCLK_OFFSET_P1_2 = 0x800008370801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQSCLK_OFFSET_P1_3 = 0x80000C370701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQSCLK_OFFSET_P1_3 = 0x80000C370801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQSCLK_OFFSET_P1_4 = 0x800010370701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQSCLK_OFFSET_P1_4 = 0x800010370801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQSCLK_OFFSET_P2_0 = 0x800000370701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQSCLK_OFFSET_P2_0 = 0x800000370801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQSCLK_OFFSET_P2_1 = 0x800004370701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQSCLK_OFFSET_P2_1 = 0x800004370801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQSCLK_OFFSET_P2_2 = 0x800008370701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQSCLK_OFFSET_P2_2 = 0x800008370801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQSCLK_OFFSET_P2_3 = 0x80000C370701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQSCLK_OFFSET_P2_3 = 0x80000C370801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQSCLK_OFFSET_P2_4 = 0x800010370701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQSCLK_OFFSET_P2_4 = 0x800010370801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQSCLK_OFFSET_P3_0 = 0x8000003707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQSCLK_OFFSET_P3_0 = 0x8000003708011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQSCLK_OFFSET_P3_1 = 0x8000043707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQSCLK_OFFSET_P3_1 = 0x8000043708011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQSCLK_OFFSET_P3_2 = 0x8000083707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQSCLK_OFFSET_P3_2 = 0x8000083708011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQSCLK_OFFSET_P3_3 = 0x80000C3707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQSCLK_OFFSET_P3_3 = 0x80000C3708011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQSCLK_OFFSET_P3_4 = 0x8000103707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQSCLK_OFFSET_P3_4 = 0x8000103708011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_0 = 0x800000300701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_0 = 0x800000300701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_0 = 0x800000300801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_1 = 0x800004300701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_1 = 0x800004300701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_1 = 0x800004300801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_2 = 0x800008300701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_2 = 0x800008300701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_2 = 0x800008300801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_3 = 0x80000C300701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_3 = 0x80000C300701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_3 = 0x80000C300801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_4 = 0x800010300701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_4 = 0x800010300701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_4 = 0x800010300801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P1_0 = 0x800000300701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P1_0 = 0x800000300801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P1_1 = 0x800004300701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P1_1 = 0x800004300801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P1_2 = 0x800008300701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P1_2 = 0x800008300801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P1_3 = 0x80000C300701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P1_3 = 0x80000C300801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P1_4 = 0x800010300701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P1_4 = 0x800010300801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P2_0 = 0x800000300701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P2_0 = 0x800000300801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P2_1 = 0x800004300701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P2_1 = 0x800004300801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P2_2 = 0x800008300701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P2_2 = 0x800008300801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P2_3 = 0x80000C300701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P2_3 = 0x80000C300801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P2_4 = 0x800010300701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P2_4 = 0x800010300801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P3_0 = 0x8000003007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P3_0 = 0x8000003008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P3_1 = 0x8000043007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P3_1 = 0x8000043008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P3_2 = 0x8000083007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P3_2 = 0x8000083008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P3_3 = 0x80000C3007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P3_3 = 0x80000C3008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P3_4 = 0x8000103007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P3_4 = 0x8000103008011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_0 = 0x800001300701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_0 = 0x800001300701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_0 = 0x800001300801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_1 = 0x800005300701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_1 = 0x800005300701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_1 = 0x800005300801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_2 = 0x800009300701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_2 = 0x800009300701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_2 = 0x800009300801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_3 = 0x80000D300701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_3 = 0x80000D300701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_3 = 0x80000D300801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_4 = 0x800011300701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_4 = 0x800011300701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_4 = 0x800011300801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P1_0 = 0x800001300701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P1_0 = 0x800001300801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P1_1 = 0x800005300701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P1_1 = 0x800005300801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P1_2 = 0x800009300701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P1_2 = 0x800009300801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P1_3 = 0x80000D300701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P1_3 = 0x80000D300801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P1_4 = 0x800011300701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P1_4 = 0x800011300801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P2_0 = 0x800001300701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P2_0 = 0x800001300801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P2_1 = 0x800005300701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P2_1 = 0x800005300801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P2_2 = 0x800009300701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P2_2 = 0x800009300801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P2_3 = 0x80000D300701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P2_3 = 0x80000D300801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P2_4 = 0x800011300701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P2_4 = 0x800011300801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P3_0 = 0x8000013007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P3_0 = 0x8000013008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P3_1 = 0x8000053007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P3_1 = 0x8000053008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P3_2 = 0x8000093007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P3_2 = 0x8000093008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P3_3 = 0x80000D3007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P3_3 = 0x80000D3008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P3_4 = 0x8000113007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P3_4 = 0x8000113008011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_0 = 0x800002300701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_0 = 0x800002300701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_0 = 0x800002300801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_1 = 0x800006300701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_1 = 0x800006300701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_1 = 0x800006300801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_2 = 0x80000A300701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_2 = 0x80000A300701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_2 = 0x80000A300801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_3 = 0x80000E300701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_3 = 0x80000E300701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_3 = 0x80000E300801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_4 = 0x800012300701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_4 = 0x800012300701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_4 = 0x800012300801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P1_0 = 0x800002300701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P1_0 = 0x800002300801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P1_1 = 0x800006300701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P1_1 = 0x800006300801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P1_2 = 0x80000A300701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P1_2 = 0x80000A300801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P1_3 = 0x80000E300701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P1_3 = 0x80000E300801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P1_4 = 0x800012300701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P1_4 = 0x800012300801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P2_0 = 0x800002300701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P2_0 = 0x800002300801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P2_1 = 0x800006300701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P2_1 = 0x800006300801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P2_2 = 0x80000A300701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P2_2 = 0x80000A300801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P2_3 = 0x80000E300701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P2_3 = 0x80000E300801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P2_4 = 0x800012300701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P2_4 = 0x800012300801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P3_0 = 0x8000023007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P3_0 = 0x8000023008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P3_1 = 0x8000063007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P3_1 = 0x8000063008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P3_2 = 0x80000A3007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P3_2 = 0x80000A3008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P3_3 = 0x80000E3007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P3_3 = 0x80000E3008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P3_4 = 0x8000123007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P3_4 = 0x8000123008011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_0 = 0x800003300701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_0 = 0x800003300701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_0 = 0x800003300801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_1 = 0x800007300701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_1 = 0x800007300701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_1 = 0x800007300801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_2 = 0x80000B300701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_2 = 0x80000B300701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_2 = 0x80000B300801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_3 = 0x80000F300701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_3 = 0x80000F300701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_3 = 0x80000F300801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_4 = 0x800013300701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_4 = 0x800013300701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_4 = 0x800013300801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P1_0 = 0x800003300701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P1_0 = 0x800003300801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P1_1 = 0x800007300701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P1_1 = 0x800007300801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P1_2 = 0x80000B300701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P1_2 = 0x80000B300801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P1_3 = 0x80000F300701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P1_3 = 0x80000F300801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P1_4 = 0x800013300701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P1_4 = 0x800013300801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P2_0 = 0x800003300701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P2_0 = 0x800003300801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P2_1 = 0x800007300701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P2_1 = 0x800007300801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P2_2 = 0x80000B300701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P2_2 = 0x80000B300801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P2_3 = 0x80000F300701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P2_3 = 0x80000F300801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P2_4 = 0x800013300701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P2_4 = 0x800013300801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P3_0 = 0x8000033007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P3_0 = 0x8000033008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P3_1 = 0x8000073007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P3_1 = 0x8000073008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P3_2 = 0x80000B3007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P3_2 = 0x80000B3008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P3_3 = 0x80000F3007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P3_3 = 0x80000F3008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P3_4 = 0x8000133007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P3_4 = 0x8000133008011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_0 = 0x800000310701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_0 = 0x800000310701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_0 = 0x800000310801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_1 = 0x800004310701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_1 = 0x800004310701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_1 = 0x800004310801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_2 = 0x800008310701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_2 = 0x800008310701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_2 = 0x800008310801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_3 = 0x80000C310701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_3 = 0x80000C310701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_3 = 0x80000C310801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_4 = 0x800010310701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_4 = 0x800010310701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_4 = 0x800010310801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P1_0 = 0x800000310701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P1_0 = 0x800000310801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P1_1 = 0x800004310701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P1_1 = 0x800004310801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P1_2 = 0x800008310701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P1_2 = 0x800008310801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P1_3 = 0x80000C310701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P1_3 = 0x80000C310801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P1_4 = 0x800010310701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P1_4 = 0x800010310801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P2_0 = 0x800000310701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P2_0 = 0x800000310801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P2_1 = 0x800004310701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P2_1 = 0x800004310801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P2_2 = 0x800008310701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P2_2 = 0x800008310801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P2_3 = 0x80000C310701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P2_3 = 0x80000C310801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P2_4 = 0x800010310701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P2_4 = 0x800010310801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P3_0 = 0x8000003107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P3_0 = 0x8000003108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P3_1 = 0x8000043107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P3_1 = 0x8000043108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P3_2 = 0x8000083107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P3_2 = 0x8000083108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P3_3 = 0x80000C3107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P3_3 = 0x80000C3108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P3_4 = 0x8000103107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P3_4 = 0x8000103108011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_0 = 0x800001310701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_0 = 0x800001310701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_0 = 0x800001310801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_1 = 0x800005310701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_1 = 0x800005310701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_1 = 0x800005310801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_2 = 0x800009310701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_2 = 0x800009310701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_2 = 0x800009310801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_3 = 0x80000D310701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_3 = 0x80000D310701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_3 = 0x80000D310801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_4 = 0x800011310701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_4 = 0x800011310701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_4 = 0x800011310801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P1_0 = 0x800001310701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P1_0 = 0x800001310801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P1_1 = 0x800005310701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P1_1 = 0x800005310801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P1_2 = 0x800009310701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P1_2 = 0x800009310801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P1_3 = 0x80000D310701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P1_3 = 0x80000D310801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P1_4 = 0x800011310701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P1_4 = 0x800011310801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P2_0 = 0x800001310701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P2_0 = 0x800001310801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P2_1 = 0x800005310701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P2_1 = 0x800005310801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P2_2 = 0x800009310701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P2_2 = 0x800009310801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P2_3 = 0x80000D310701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P2_3 = 0x80000D310801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P2_4 = 0x800011310701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P2_4 = 0x800011310801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P3_0 = 0x8000013107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P3_0 = 0x8000013108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P3_1 = 0x8000053107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P3_1 = 0x8000053108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P3_2 = 0x8000093107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P3_2 = 0x8000093108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P3_3 = 0x80000D3107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P3_3 = 0x80000D3108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P3_4 = 0x8000113107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P3_4 = 0x8000113108011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_0 = 0x800002310701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_0 = 0x800002310701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_0 = 0x800002310801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_1 = 0x800006310701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_1 = 0x800006310701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_1 = 0x800006310801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_2 = 0x80000A310701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_2 = 0x80000A310701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_2 = 0x80000A310801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_3 = 0x80000E310701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_3 = 0x80000E310701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_3 = 0x80000E310801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_4 = 0x800012310701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_4 = 0x800012310701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_4 = 0x800012310801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P1_0 = 0x800002310701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P1_0 = 0x800002310801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P1_1 = 0x800006310701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P1_1 = 0x800006310801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P1_2 = 0x80000A310701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P1_2 = 0x80000A310801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P1_3 = 0x80000E310701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P1_3 = 0x80000E310801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P1_4 = 0x800012310701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P1_4 = 0x800012310801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P2_0 = 0x800002310701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P2_0 = 0x800002310801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P2_1 = 0x800006310701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P2_1 = 0x800006310801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P2_2 = 0x80000A310701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P2_2 = 0x80000A310801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P2_3 = 0x80000E310701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P2_3 = 0x80000E310801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P2_4 = 0x800012310701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P2_4 = 0x800012310801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P3_0 = 0x8000023107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P3_0 = 0x8000023108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P3_1 = 0x8000063107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P3_1 = 0x8000063108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P3_2 = 0x80000A3107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P3_2 = 0x80000A3108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P3_3 = 0x80000E3107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P3_3 = 0x80000E3108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P3_4 = 0x8000123107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P3_4 = 0x8000123108011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_0 = 0x800003310701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_0 = 0x800003310701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_0 = 0x800003310801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_1 = 0x800007310701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_1 = 0x800007310701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_1 = 0x800007310801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_2 = 0x80000B310701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_2 = 0x80000B310701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_2 = 0x80000B310801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_3 = 0x80000F310701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_3 = 0x80000F310701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_3 = 0x80000F310801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_4 = 0x800013310701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_4 = 0x800013310701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_4 = 0x800013310801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P1_0 = 0x800003310701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P1_0 = 0x800003310801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P1_1 = 0x800007310701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P1_1 = 0x800007310801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P1_2 = 0x80000B310701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P1_2 = 0x80000B310801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P1_3 = 0x80000F310701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P1_3 = 0x80000F310801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P1_4 = 0x800013310701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P1_4 = 0x800013310801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P2_0 = 0x800003310701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P2_0 = 0x800003310801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P2_1 = 0x800007310701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P2_1 = 0x800007310801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P2_2 = 0x80000B310701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P2_2 = 0x80000B310801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P2_3 = 0x80000F310701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P2_3 = 0x80000F310801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P2_4 = 0x800013310701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P2_4 = 0x800013310801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P3_0 = 0x8000033107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P3_0 = 0x8000033108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P3_1 = 0x8000073107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P3_1 = 0x8000073108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P3_2 = 0x80000B3107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P3_2 = 0x80000B3108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P3_3 = 0x80000F3107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P3_3 = 0x80000F3108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P3_4 = 0x8000133107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P3_4 = 0x8000133108011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP0_P0_0 = 0x8000007D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQS_BIT_DISABLE_RP0_P0_0 = 0x8000007D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQS_BIT_DISABLE_RP0_P0_0 = 0x8000007D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP0_P0_1 = 0x8000047D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQS_BIT_DISABLE_RP0_P0_1 = 0x8000047D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQS_BIT_DISABLE_RP0_P0_1 = 0x8000047D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP0_P0_2 = 0x8000087D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQS_BIT_DISABLE_RP0_P0_2 = 0x8000087D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQS_BIT_DISABLE_RP0_P0_2 = 0x8000087D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP0_P0_3 = 0x80000C7D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQS_BIT_DISABLE_RP0_P0_3 = 0x80000C7D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQS_BIT_DISABLE_RP0_P0_3 = 0x80000C7D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP0_P0_4 = 0x8000107D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQS_BIT_DISABLE_RP0_P0_4 = 0x8000107D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQS_BIT_DISABLE_RP0_P0_4 = 0x8000107D0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQS_BIT_DISABLE_RP0_P1_0 = 0x8000007D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQS_BIT_DISABLE_RP0_P1_0 = 0x8000007D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQS_BIT_DISABLE_RP0_P1_1 = 0x8000047D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQS_BIT_DISABLE_RP0_P1_1 = 0x8000047D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQS_BIT_DISABLE_RP0_P1_2 = 0x8000087D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQS_BIT_DISABLE_RP0_P1_2 = 0x8000087D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQS_BIT_DISABLE_RP0_P1_3 = 0x80000C7D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQS_BIT_DISABLE_RP0_P1_3 = 0x80000C7D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQS_BIT_DISABLE_RP0_P1_4 = 0x8000107D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQS_BIT_DISABLE_RP0_P1_4 = 0x8000107D0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQS_BIT_DISABLE_RP0_P2_0 = 0x8000007D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQS_BIT_DISABLE_RP0_P2_0 = 0x8000007D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQS_BIT_DISABLE_RP0_P2_1 = 0x8000047D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQS_BIT_DISABLE_RP0_P2_1 = 0x8000047D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQS_BIT_DISABLE_RP0_P2_2 = 0x8000087D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQS_BIT_DISABLE_RP0_P2_2 = 0x8000087D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQS_BIT_DISABLE_RP0_P2_3 = 0x80000C7D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQS_BIT_DISABLE_RP0_P2_3 = 0x80000C7D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQS_BIT_DISABLE_RP0_P2_4 = 0x8000107D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQS_BIT_DISABLE_RP0_P2_4 = 0x8000107D0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQS_BIT_DISABLE_RP0_P3_0 = 0x8000007D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQS_BIT_DISABLE_RP0_P3_0 = 0x8000007D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQS_BIT_DISABLE_RP0_P3_1 = 0x8000047D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQS_BIT_DISABLE_RP0_P3_1 = 0x8000047D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQS_BIT_DISABLE_RP0_P3_2 = 0x8000087D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQS_BIT_DISABLE_RP0_P3_2 = 0x8000087D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQS_BIT_DISABLE_RP0_P3_3 = 0x80000C7D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQS_BIT_DISABLE_RP0_P3_3 = 0x80000C7D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQS_BIT_DISABLE_RP0_P3_4 = 0x8000107D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQS_BIT_DISABLE_RP0_P3_4 = 0x8000107D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP1_P0_0 = 0x8000017D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQS_BIT_DISABLE_RP1_P0_0 = 0x8000017D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQS_BIT_DISABLE_RP1_P0_0 = 0x8000017D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP1_P0_1 = 0x8000057D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQS_BIT_DISABLE_RP1_P0_1 = 0x8000057D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQS_BIT_DISABLE_RP1_P0_1 = 0x8000057D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP1_P0_2 = 0x8000097D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQS_BIT_DISABLE_RP1_P0_2 = 0x8000097D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQS_BIT_DISABLE_RP1_P0_2 = 0x8000097D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP1_P0_3 = 0x80000D7D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQS_BIT_DISABLE_RP1_P0_3 = 0x80000D7D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQS_BIT_DISABLE_RP1_P0_3 = 0x80000D7D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP1_P0_4 = 0x8000117D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQS_BIT_DISABLE_RP1_P0_4 = 0x8000117D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQS_BIT_DISABLE_RP1_P0_4 = 0x8000117D0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQS_BIT_DISABLE_RP1_P1_0 = 0x8000017D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQS_BIT_DISABLE_RP1_P1_0 = 0x8000017D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQS_BIT_DISABLE_RP1_P1_1 = 0x8000057D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQS_BIT_DISABLE_RP1_P1_1 = 0x8000057D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQS_BIT_DISABLE_RP1_P1_2 = 0x8000097D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQS_BIT_DISABLE_RP1_P1_2 = 0x8000097D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQS_BIT_DISABLE_RP1_P1_3 = 0x80000D7D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQS_BIT_DISABLE_RP1_P1_3 = 0x80000D7D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQS_BIT_DISABLE_RP1_P1_4 = 0x8000117D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQS_BIT_DISABLE_RP1_P1_4 = 0x8000117D0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQS_BIT_DISABLE_RP1_P2_0 = 0x8000017D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQS_BIT_DISABLE_RP1_P2_0 = 0x8000017D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQS_BIT_DISABLE_RP1_P2_1 = 0x8000057D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQS_BIT_DISABLE_RP1_P2_1 = 0x8000057D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQS_BIT_DISABLE_RP1_P2_2 = 0x8000097D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQS_BIT_DISABLE_RP1_P2_2 = 0x8000097D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQS_BIT_DISABLE_RP1_P2_3 = 0x80000D7D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQS_BIT_DISABLE_RP1_P2_3 = 0x80000D7D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQS_BIT_DISABLE_RP1_P2_4 = 0x8000117D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQS_BIT_DISABLE_RP1_P2_4 = 0x8000117D0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQS_BIT_DISABLE_RP1_P3_0 = 0x8000017D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQS_BIT_DISABLE_RP1_P3_0 = 0x8000017D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQS_BIT_DISABLE_RP1_P3_1 = 0x8000057D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQS_BIT_DISABLE_RP1_P3_1 = 0x8000057D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQS_BIT_DISABLE_RP1_P3_2 = 0x8000097D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQS_BIT_DISABLE_RP1_P3_2 = 0x8000097D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQS_BIT_DISABLE_RP1_P3_3 = 0x80000D7D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQS_BIT_DISABLE_RP1_P3_3 = 0x80000D7D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQS_BIT_DISABLE_RP1_P3_4 = 0x8000117D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQS_BIT_DISABLE_RP1_P3_4 = 0x8000117D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP2_P0_0 = 0x8000027D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQS_BIT_DISABLE_RP2_P0_0 = 0x8000027D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQS_BIT_DISABLE_RP2_P0_0 = 0x8000027D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP2_P0_1 = 0x8000067D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQS_BIT_DISABLE_RP2_P0_1 = 0x8000067D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQS_BIT_DISABLE_RP2_P0_1 = 0x8000067D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP2_P0_2 = 0x80000A7D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQS_BIT_DISABLE_RP2_P0_2 = 0x80000A7D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQS_BIT_DISABLE_RP2_P0_2 = 0x80000A7D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP2_P0_3 = 0x80000E7D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQS_BIT_DISABLE_RP2_P0_3 = 0x80000E7D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQS_BIT_DISABLE_RP2_P0_3 = 0x80000E7D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP2_P0_4 = 0x8000127D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQS_BIT_DISABLE_RP2_P0_4 = 0x8000127D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQS_BIT_DISABLE_RP2_P0_4 = 0x8000127D0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQS_BIT_DISABLE_RP2_P1_0 = 0x8000027D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQS_BIT_DISABLE_RP2_P1_0 = 0x8000027D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQS_BIT_DISABLE_RP2_P1_1 = 0x8000067D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQS_BIT_DISABLE_RP2_P1_1 = 0x8000067D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQS_BIT_DISABLE_RP2_P1_2 = 0x80000A7D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQS_BIT_DISABLE_RP2_P1_2 = 0x80000A7D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQS_BIT_DISABLE_RP2_P1_3 = 0x80000E7D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQS_BIT_DISABLE_RP2_P1_3 = 0x80000E7D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQS_BIT_DISABLE_RP2_P1_4 = 0x8000127D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQS_BIT_DISABLE_RP2_P1_4 = 0x8000127D0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQS_BIT_DISABLE_RP2_P2_0 = 0x8000027D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQS_BIT_DISABLE_RP2_P2_0 = 0x8000027D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQS_BIT_DISABLE_RP2_P2_1 = 0x8000067D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQS_BIT_DISABLE_RP2_P2_1 = 0x8000067D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQS_BIT_DISABLE_RP2_P2_2 = 0x80000A7D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQS_BIT_DISABLE_RP2_P2_2 = 0x80000A7D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQS_BIT_DISABLE_RP2_P2_3 = 0x80000E7D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQS_BIT_DISABLE_RP2_P2_3 = 0x80000E7D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQS_BIT_DISABLE_RP2_P2_4 = 0x8000127D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQS_BIT_DISABLE_RP2_P2_4 = 0x8000127D0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQS_BIT_DISABLE_RP2_P3_0 = 0x8000027D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQS_BIT_DISABLE_RP2_P3_0 = 0x8000027D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQS_BIT_DISABLE_RP2_P3_1 = 0x8000067D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQS_BIT_DISABLE_RP2_P3_1 = 0x8000067D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQS_BIT_DISABLE_RP2_P3_2 = 0x80000A7D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQS_BIT_DISABLE_RP2_P3_2 = 0x80000A7D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQS_BIT_DISABLE_RP2_P3_3 = 0x80000E7D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQS_BIT_DISABLE_RP2_P3_3 = 0x80000E7D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQS_BIT_DISABLE_RP2_P3_4 = 0x8000127D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQS_BIT_DISABLE_RP2_P3_4 = 0x8000127D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP3_P0_0 = 0x8000037D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQS_BIT_DISABLE_RP3_P0_0 = 0x8000037D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQS_BIT_DISABLE_RP3_P0_0 = 0x8000037D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP3_P0_1 = 0x8000077D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQS_BIT_DISABLE_RP3_P0_1 = 0x8000077D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQS_BIT_DISABLE_RP3_P0_1 = 0x8000077D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP3_P0_2 = 0x80000B7D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQS_BIT_DISABLE_RP3_P0_2 = 0x80000B7D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQS_BIT_DISABLE_RP3_P0_2 = 0x80000B7D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP3_P0_3 = 0x80000F7D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQS_BIT_DISABLE_RP3_P0_3 = 0x80000F7D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQS_BIT_DISABLE_RP3_P0_3 = 0x80000F7D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP3_P0_4 = 0x8000137D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQS_BIT_DISABLE_RP3_P0_4 = 0x8000137D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQS_BIT_DISABLE_RP3_P0_4 = 0x8000137D0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQS_BIT_DISABLE_RP3_P1_0 = 0x8000037D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQS_BIT_DISABLE_RP3_P1_0 = 0x8000037D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQS_BIT_DISABLE_RP3_P1_1 = 0x8000077D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQS_BIT_DISABLE_RP3_P1_1 = 0x8000077D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQS_BIT_DISABLE_RP3_P1_2 = 0x80000B7D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQS_BIT_DISABLE_RP3_P1_2 = 0x80000B7D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQS_BIT_DISABLE_RP3_P1_3 = 0x80000F7D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQS_BIT_DISABLE_RP3_P1_3 = 0x80000F7D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQS_BIT_DISABLE_RP3_P1_4 = 0x8000137D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQS_BIT_DISABLE_RP3_P1_4 = 0x8000137D0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQS_BIT_DISABLE_RP3_P2_0 = 0x8000037D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQS_BIT_DISABLE_RP3_P2_0 = 0x8000037D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQS_BIT_DISABLE_RP3_P2_1 = 0x8000077D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQS_BIT_DISABLE_RP3_P2_1 = 0x8000077D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQS_BIT_DISABLE_RP3_P2_2 = 0x80000B7D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQS_BIT_DISABLE_RP3_P2_2 = 0x80000B7D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQS_BIT_DISABLE_RP3_P2_3 = 0x80000F7D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQS_BIT_DISABLE_RP3_P2_3 = 0x80000F7D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQS_BIT_DISABLE_RP3_P2_4 = 0x8000137D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQS_BIT_DISABLE_RP3_P2_4 = 0x8000137D0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQS_BIT_DISABLE_RP3_P3_0 = 0x8000037D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQS_BIT_DISABLE_RP3_P3_0 = 0x8000037D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQS_BIT_DISABLE_RP3_P3_1 = 0x8000077D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQS_BIT_DISABLE_RP3_P3_1 = 0x8000077D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQS_BIT_DISABLE_RP3_P3_2 = 0x80000B7D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQS_BIT_DISABLE_RP3_P3_2 = 0x80000B7D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQS_BIT_DISABLE_RP3_P3_3 = 0x80000F7D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQS_BIT_DISABLE_RP3_P3_3 = 0x80000F7D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQS_BIT_DISABLE_RP3_P3_4 = 0x8000137D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQS_BIT_DISABLE_RP3_P3_4 = 0x8000137D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_0 = 0x800000130701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_0 = 0x800000130701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_0 = 0x800000130801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_1 = 0x800004130701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_1 = 0x800004130701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_1 = 0x800004130801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_2 = 0x800008130701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_2 = 0x800008130701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_2 = 0x800008130801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_3 = 0x80000C130701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_3 = 0x80000C130701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_3 = 0x80000C130801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_4 = 0x800010130701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_4 = 0x800010130701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_4 = 0x800010130801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P1_0 = 0x800000130701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P1_0 = 0x800000130801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P1_1 = 0x800004130701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P1_1 = 0x800004130801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P1_2 = 0x800008130701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P1_2 = 0x800008130801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P1_3 = 0x80000C130701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P1_3 = 0x80000C130801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P1_4 = 0x800010130701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P1_4 = 0x800010130801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P2_0 = 0x800000130701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P2_0 = 0x800000130801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P2_1 = 0x800004130701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P2_1 = 0x800004130801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P2_2 = 0x800008130701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P2_2 = 0x800008130801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P2_3 = 0x80000C130701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P2_3 = 0x80000C130801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P2_4 = 0x800010130701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P2_4 = 0x800010130801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P3_0 = 0x8000001307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P3_0 = 0x8000001308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P3_1 = 0x8000041307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P3_1 = 0x8000041308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P3_2 = 0x8000081307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P3_2 = 0x8000081308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P3_3 = 0x80000C1307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P3_3 = 0x80000C1308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P3_4 = 0x8000101307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P3_4 = 0x8000101308011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_0 = 0x800001130701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_0 = 0x800001130701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_0 = 0x800001130801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_1 = 0x800005130701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_1 = 0x800005130701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_1 = 0x800005130801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_2 = 0x800009130701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_2 = 0x800009130701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_2 = 0x800009130801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_3 = 0x80000D130701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_3 = 0x80000D130701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_3 = 0x80000D130801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_4 = 0x800011130701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_4 = 0x800011130701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_4 = 0x800011130801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P1_0 = 0x800001130701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P1_0 = 0x800001130801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P1_1 = 0x800005130701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P1_1 = 0x800005130801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P1_2 = 0x800009130701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P1_2 = 0x800009130801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P1_3 = 0x80000D130701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P1_3 = 0x80000D130801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P1_4 = 0x800011130701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P1_4 = 0x800011130801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P2_0 = 0x800001130701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P2_0 = 0x800001130801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P2_1 = 0x800005130701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P2_1 = 0x800005130801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P2_2 = 0x800009130701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P2_2 = 0x800009130801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P2_3 = 0x80000D130701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P2_3 = 0x80000D130801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P2_4 = 0x800011130701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P2_4 = 0x800011130801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P3_0 = 0x8000011307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P3_0 = 0x8000011308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P3_1 = 0x8000051307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P3_1 = 0x8000051308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P3_2 = 0x8000091307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P3_2 = 0x8000091308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P3_3 = 0x80000D1307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P3_3 = 0x80000D1308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P3_4 = 0x8000111307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P3_4 = 0x8000111308011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_0 = 0x800002130701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_0 = 0x800002130701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_0 = 0x800002130801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_1 = 0x800006130701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_1 = 0x800006130701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_1 = 0x800006130801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_2 = 0x80000A130701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_2 = 0x80000A130701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_2 = 0x80000A130801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_3 = 0x80000E130701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_3 = 0x80000E130701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_3 = 0x80000E130801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_4 = 0x800012130701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_4 = 0x800012130701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_4 = 0x800012130801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P1_0 = 0x800002130701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P1_0 = 0x800002130801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P1_1 = 0x800006130701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P1_1 = 0x800006130801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P1_2 = 0x80000A130701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P1_2 = 0x80000A130801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P1_3 = 0x80000E130701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P1_3 = 0x80000E130801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P1_4 = 0x800012130701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P1_4 = 0x800012130801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P2_0 = 0x800002130701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P2_0 = 0x800002130801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P2_1 = 0x800006130701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P2_1 = 0x800006130801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P2_2 = 0x80000A130701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P2_2 = 0x80000A130801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P2_3 = 0x80000E130701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P2_3 = 0x80000E130801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P2_4 = 0x800012130701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P2_4 = 0x800012130801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P3_0 = 0x8000021307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P3_0 = 0x8000021308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P3_1 = 0x8000061307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P3_1 = 0x8000061308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P3_2 = 0x80000A1307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P3_2 = 0x80000A1308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P3_3 = 0x80000E1307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P3_3 = 0x80000E1308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P3_4 = 0x8000121307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P3_4 = 0x8000121308011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_0 = 0x800003130701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_0 = 0x800003130701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_0 = 0x800003130801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_1 = 0x800007130701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_1 = 0x800007130701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_1 = 0x800007130801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_2 = 0x80000B130701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_2 = 0x80000B130701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_2 = 0x80000B130801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_3 = 0x80000F130701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_3 = 0x80000F130701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_3 = 0x80000F130801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_4 = 0x800013130701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_4 = 0x800013130701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_4 = 0x800013130801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P1_0 = 0x800003130701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P1_0 = 0x800003130801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P1_1 = 0x800007130701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P1_1 = 0x800007130801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P1_2 = 0x80000B130701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P1_2 = 0x80000B130801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P1_3 = 0x80000F130701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P1_3 = 0x80000F130801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P1_4 = 0x800013130701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P1_4 = 0x800013130801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P2_0 = 0x800003130701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P2_0 = 0x800003130801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P2_1 = 0x800007130701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P2_1 = 0x800007130801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P2_2 = 0x80000B130701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P2_2 = 0x80000B130801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P2_3 = 0x80000F130701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P2_3 = 0x80000F130801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P2_4 = 0x800013130701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P2_4 = 0x800013130801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P3_0 = 0x8000031307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P3_0 = 0x8000031308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P3_1 = 0x8000071307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P3_1 = 0x8000071308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P3_2 = 0x80000B1307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P3_2 = 0x80000B1308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P3_3 = 0x80000F1307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P3_3 = 0x80000F1308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P3_4 = 0x8000131307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P3_4 = 0x8000131308011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0 = 0x800000090701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0 = 0x800000090701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0 = 0x800000090801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1 = 0x800004090701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1 = 0x800004090701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1 = 0x800004090801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2 = 0x800008090701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2 = 0x800008090701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2 = 0x800008090801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3 = 0x80000C090701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3 = 0x80000C090701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3 = 0x80000C090801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4 = 0x800010090701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4 = 0x800010090701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4 = 0x800010090801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_0 = 0x800000090701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_0 = 0x800000090801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_1 = 0x800004090701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_1 = 0x800004090801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_2 = 0x800008090701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_2 = 0x800008090801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_3 = 0x80000C090701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_3 = 0x80000C090801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_4 = 0x800010090701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_4 = 0x800010090801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P2_0 = 0x800000090701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P2_0 = 0x800000090801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P2_1 = 0x800004090701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P2_1 = 0x800004090801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P2_2 = 0x800008090701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P2_2 = 0x800008090801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P2_3 = 0x80000C090701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P2_3 = 0x80000C090801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P2_4 = 0x800010090701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P2_4 = 0x800010090801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P3_0 = 0x8000000907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P3_0 = 0x8000000908011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P3_1 = 0x8000040907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P3_1 = 0x8000040908011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P3_2 = 0x8000080907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P3_2 = 0x8000080908011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P3_3 = 0x80000C0907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P3_3 = 0x80000C0908011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P3_4 = 0x8000100907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P3_4 = 0x8000100908011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0 = 0x800001090701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0 = 0x800001090701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0 = 0x800001090801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1 = 0x800005090701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1 = 0x800005090701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1 = 0x800005090801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2 = 0x800009090701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2 = 0x800009090701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2 = 0x800009090801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3 = 0x80000D090701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3 = 0x80000D090701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3 = 0x80000D090801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4 = 0x800011090701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4 = 0x800011090701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4 = 0x800011090801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_0 = 0x800001090701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_0 = 0x800001090801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_1 = 0x800005090701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_1 = 0x800005090801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_2 = 0x800009090701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_2 = 0x800009090801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_3 = 0x80000D090701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_3 = 0x80000D090801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_4 = 0x800011090701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_4 = 0x800011090801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P2_0 = 0x800001090701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P2_0 = 0x800001090801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P2_1 = 0x800005090701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P2_1 = 0x800005090801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P2_2 = 0x800009090701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P2_2 = 0x800009090801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P2_3 = 0x80000D090701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P2_3 = 0x80000D090801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P2_4 = 0x800011090701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P2_4 = 0x800011090801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P3_0 = 0x8000010907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P3_0 = 0x8000010908011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P3_1 = 0x8000050907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P3_1 = 0x8000050908011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P3_2 = 0x8000090907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P3_2 = 0x8000090908011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P3_3 = 0x80000D0907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P3_3 = 0x80000D0908011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P3_4 = 0x8000110907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P3_4 = 0x8000110908011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0 = 0x800002090701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0 = 0x800002090701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0 = 0x800002090801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1 = 0x800006090701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1 = 0x800006090701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1 = 0x800006090801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2 = 0x80000A090701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2 = 0x80000A090701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2 = 0x80000A090801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3 = 0x80000E090701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3 = 0x80000E090701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3 = 0x80000E090801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4 = 0x800012090701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4 = 0x800012090701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4 = 0x800012090801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_0 = 0x800002090701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_0 = 0x800002090801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_1 = 0x800006090701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_1 = 0x800006090801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_2 = 0x80000A090701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_2 = 0x80000A090801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_3 = 0x80000E090701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_3 = 0x80000E090801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_4 = 0x800012090701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_4 = 0x800012090801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P2_0 = 0x800002090701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P2_0 = 0x800002090801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P2_1 = 0x800006090701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P2_1 = 0x800006090801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P2_2 = 0x80000A090701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P2_2 = 0x80000A090801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P2_3 = 0x80000E090701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P2_3 = 0x80000E090801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P2_4 = 0x800012090701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P2_4 = 0x800012090801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P3_0 = 0x8000020907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P3_0 = 0x8000020908011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P3_1 = 0x8000060907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P3_1 = 0x8000060908011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P3_2 = 0x80000A0907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P3_2 = 0x80000A0908011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P3_3 = 0x80000E0907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P3_3 = 0x80000E0908011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P3_4 = 0x8000120907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P3_4 = 0x8000120908011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0 = 0x800003090701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0 = 0x800003090701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0 = 0x800003090801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1 = 0x800007090701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1 = 0x800007090701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1 = 0x800007090801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2 = 0x80000B090701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2 = 0x80000B090701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2 = 0x80000B090801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3 = 0x80000F090701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3 = 0x80000F090701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3 = 0x80000F090801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4 = 0x800013090701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4 = 0x800013090701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4 = 0x800013090801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_0 = 0x800003090701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_0 = 0x800003090801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_1 = 0x800007090701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_1 = 0x800007090801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_2 = 0x80000B090701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_2 = 0x80000B090801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_3 = 0x80000F090701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_3 = 0x80000F090801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_4 = 0x800013090701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_4 = 0x800013090801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P2_0 = 0x800003090701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P2_0 = 0x800003090801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P2_1 = 0x800007090701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P2_1 = 0x800007090801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P2_2 = 0x80000B090701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P2_2 = 0x80000B090801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P2_3 = 0x80000F090701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P2_3 = 0x80000F090801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P2_4 = 0x800013090701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P2_4 = 0x800013090801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P3_0 = 0x8000030907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P3_0 = 0x8000030908011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P3_1 = 0x8000070907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P3_1 = 0x8000070908011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P3_2 = 0x80000B0907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P3_2 = 0x80000B0908011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P3_3 = 0x80000F0907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P3_3 = 0x80000F0908011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P3_4 = 0x8000130907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P3_4 = 0x8000130908011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP0_P0_0 = 0x8000007C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQ_BIT_DISABLE_RP0_P0_0 = 0x8000007C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQ_BIT_DISABLE_RP0_P0_0 = 0x8000007C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP0_P0_1 = 0x8000047C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQ_BIT_DISABLE_RP0_P0_1 = 0x8000047C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQ_BIT_DISABLE_RP0_P0_1 = 0x8000047C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP0_P0_2 = 0x8000087C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQ_BIT_DISABLE_RP0_P0_2 = 0x8000087C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQ_BIT_DISABLE_RP0_P0_2 = 0x8000087C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP0_P0_3 = 0x80000C7C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQ_BIT_DISABLE_RP0_P0_3 = 0x80000C7C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQ_BIT_DISABLE_RP0_P0_3 = 0x80000C7C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP0_P0_4 = 0x8000107C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQ_BIT_DISABLE_RP0_P0_4 = 0x8000107C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQ_BIT_DISABLE_RP0_P0_4 = 0x8000107C0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQ_BIT_DISABLE_RP0_P1_0 = 0x8000007C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQ_BIT_DISABLE_RP0_P1_0 = 0x8000007C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQ_BIT_DISABLE_RP0_P1_1 = 0x8000047C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQ_BIT_DISABLE_RP0_P1_1 = 0x8000047C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQ_BIT_DISABLE_RP0_P1_2 = 0x8000087C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQ_BIT_DISABLE_RP0_P1_2 = 0x8000087C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQ_BIT_DISABLE_RP0_P1_3 = 0x80000C7C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQ_BIT_DISABLE_RP0_P1_3 = 0x80000C7C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQ_BIT_DISABLE_RP0_P1_4 = 0x8000107C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQ_BIT_DISABLE_RP0_P1_4 = 0x8000107C0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQ_BIT_DISABLE_RP0_P2_0 = 0x8000007C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQ_BIT_DISABLE_RP0_P2_0 = 0x8000007C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQ_BIT_DISABLE_RP0_P2_1 = 0x8000047C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQ_BIT_DISABLE_RP0_P2_1 = 0x8000047C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQ_BIT_DISABLE_RP0_P2_2 = 0x8000087C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQ_BIT_DISABLE_RP0_P2_2 = 0x8000087C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQ_BIT_DISABLE_RP0_P2_3 = 0x80000C7C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQ_BIT_DISABLE_RP0_P2_3 = 0x80000C7C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQ_BIT_DISABLE_RP0_P2_4 = 0x8000107C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQ_BIT_DISABLE_RP0_P2_4 = 0x8000107C0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQ_BIT_DISABLE_RP0_P3_0 = 0x8000007C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQ_BIT_DISABLE_RP0_P3_0 = 0x8000007C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQ_BIT_DISABLE_RP0_P3_1 = 0x8000047C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQ_BIT_DISABLE_RP0_P3_1 = 0x8000047C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQ_BIT_DISABLE_RP0_P3_2 = 0x8000087C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQ_BIT_DISABLE_RP0_P3_2 = 0x8000087C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQ_BIT_DISABLE_RP0_P3_3 = 0x80000C7C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQ_BIT_DISABLE_RP0_P3_3 = 0x80000C7C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQ_BIT_DISABLE_RP0_P3_4 = 0x8000107C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQ_BIT_DISABLE_RP0_P3_4 = 0x8000107C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP1_P0_0 = 0x8000017C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQ_BIT_DISABLE_RP1_P0_0 = 0x8000017C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQ_BIT_DISABLE_RP1_P0_0 = 0x8000017C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP1_P0_1 = 0x8000057C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQ_BIT_DISABLE_RP1_P0_1 = 0x8000057C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQ_BIT_DISABLE_RP1_P0_1 = 0x8000057C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP1_P0_2 = 0x8000097C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQ_BIT_DISABLE_RP1_P0_2 = 0x8000097C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQ_BIT_DISABLE_RP1_P0_2 = 0x8000097C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP1_P0_3 = 0x80000D7C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQ_BIT_DISABLE_RP1_P0_3 = 0x80000D7C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQ_BIT_DISABLE_RP1_P0_3 = 0x80000D7C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP1_P0_4 = 0x8000117C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQ_BIT_DISABLE_RP1_P0_4 = 0x8000117C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQ_BIT_DISABLE_RP1_P0_4 = 0x8000117C0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQ_BIT_DISABLE_RP1_P1_0 = 0x8000017C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQ_BIT_DISABLE_RP1_P1_0 = 0x8000017C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQ_BIT_DISABLE_RP1_P1_1 = 0x8000057C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQ_BIT_DISABLE_RP1_P1_1 = 0x8000057C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQ_BIT_DISABLE_RP1_P1_2 = 0x8000097C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQ_BIT_DISABLE_RP1_P1_2 = 0x8000097C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQ_BIT_DISABLE_RP1_P1_3 = 0x80000D7C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQ_BIT_DISABLE_RP1_P1_3 = 0x80000D7C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQ_BIT_DISABLE_RP1_P1_4 = 0x8000117C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQ_BIT_DISABLE_RP1_P1_4 = 0x8000117C0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQ_BIT_DISABLE_RP1_P2_0 = 0x8000017C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQ_BIT_DISABLE_RP1_P2_0 = 0x8000017C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQ_BIT_DISABLE_RP1_P2_1 = 0x8000057C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQ_BIT_DISABLE_RP1_P2_1 = 0x8000057C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQ_BIT_DISABLE_RP1_P2_2 = 0x8000097C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQ_BIT_DISABLE_RP1_P2_2 = 0x8000097C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQ_BIT_DISABLE_RP1_P2_3 = 0x80000D7C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQ_BIT_DISABLE_RP1_P2_3 = 0x80000D7C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQ_BIT_DISABLE_RP1_P2_4 = 0x8000117C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQ_BIT_DISABLE_RP1_P2_4 = 0x8000117C0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQ_BIT_DISABLE_RP1_P3_0 = 0x8000017C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQ_BIT_DISABLE_RP1_P3_0 = 0x8000017C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQ_BIT_DISABLE_RP1_P3_1 = 0x8000057C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQ_BIT_DISABLE_RP1_P3_1 = 0x8000057C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQ_BIT_DISABLE_RP1_P3_2 = 0x8000097C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQ_BIT_DISABLE_RP1_P3_2 = 0x8000097C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQ_BIT_DISABLE_RP1_P3_3 = 0x80000D7C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQ_BIT_DISABLE_RP1_P3_3 = 0x80000D7C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQ_BIT_DISABLE_RP1_P3_4 = 0x8000117C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQ_BIT_DISABLE_RP1_P3_4 = 0x8000117C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP2_P0_0 = 0x8000027C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQ_BIT_DISABLE_RP2_P0_0 = 0x8000027C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQ_BIT_DISABLE_RP2_P0_0 = 0x8000027C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP2_P0_1 = 0x8000067C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQ_BIT_DISABLE_RP2_P0_1 = 0x8000067C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQ_BIT_DISABLE_RP2_P0_1 = 0x8000067C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP2_P0_2 = 0x80000A7C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQ_BIT_DISABLE_RP2_P0_2 = 0x80000A7C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQ_BIT_DISABLE_RP2_P0_2 = 0x80000A7C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP2_P0_3 = 0x80000E7C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQ_BIT_DISABLE_RP2_P0_3 = 0x80000E7C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQ_BIT_DISABLE_RP2_P0_3 = 0x80000E7C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP2_P0_4 = 0x8000127C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQ_BIT_DISABLE_RP2_P0_4 = 0x8000127C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQ_BIT_DISABLE_RP2_P0_4 = 0x8000127C0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQ_BIT_DISABLE_RP2_P1_0 = 0x8000027C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQ_BIT_DISABLE_RP2_P1_0 = 0x8000027C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQ_BIT_DISABLE_RP2_P1_1 = 0x8000067C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQ_BIT_DISABLE_RP2_P1_1 = 0x8000067C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQ_BIT_DISABLE_RP2_P1_2 = 0x80000A7C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQ_BIT_DISABLE_RP2_P1_2 = 0x80000A7C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQ_BIT_DISABLE_RP2_P1_3 = 0x80000E7C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQ_BIT_DISABLE_RP2_P1_3 = 0x80000E7C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQ_BIT_DISABLE_RP2_P1_4 = 0x8000127C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQ_BIT_DISABLE_RP2_P1_4 = 0x8000127C0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQ_BIT_DISABLE_RP2_P2_0 = 0x8000027C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQ_BIT_DISABLE_RP2_P2_0 = 0x8000027C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQ_BIT_DISABLE_RP2_P2_1 = 0x8000067C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQ_BIT_DISABLE_RP2_P2_1 = 0x8000067C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQ_BIT_DISABLE_RP2_P2_2 = 0x80000A7C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQ_BIT_DISABLE_RP2_P2_2 = 0x80000A7C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQ_BIT_DISABLE_RP2_P2_3 = 0x80000E7C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQ_BIT_DISABLE_RP2_P2_3 = 0x80000E7C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQ_BIT_DISABLE_RP2_P2_4 = 0x8000127C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQ_BIT_DISABLE_RP2_P2_4 = 0x8000127C0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQ_BIT_DISABLE_RP2_P3_0 = 0x8000027C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQ_BIT_DISABLE_RP2_P3_0 = 0x8000027C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQ_BIT_DISABLE_RP2_P3_1 = 0x8000067C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQ_BIT_DISABLE_RP2_P3_1 = 0x8000067C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQ_BIT_DISABLE_RP2_P3_2 = 0x80000A7C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQ_BIT_DISABLE_RP2_P3_2 = 0x80000A7C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQ_BIT_DISABLE_RP2_P3_3 = 0x80000E7C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQ_BIT_DISABLE_RP2_P3_3 = 0x80000E7C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQ_BIT_DISABLE_RP2_P3_4 = 0x8000127C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQ_BIT_DISABLE_RP2_P3_4 = 0x8000127C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP3_P0_0 = 0x8000037C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQ_BIT_DISABLE_RP3_P0_0 = 0x8000037C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQ_BIT_DISABLE_RP3_P0_0 = 0x8000037C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP3_P0_1 = 0x8000077C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQ_BIT_DISABLE_RP3_P0_1 = 0x8000077C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQ_BIT_DISABLE_RP3_P0_1 = 0x8000077C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP3_P0_2 = 0x80000B7C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQ_BIT_DISABLE_RP3_P0_2 = 0x80000B7C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQ_BIT_DISABLE_RP3_P0_2 = 0x80000B7C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP3_P0_3 = 0x80000F7C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQ_BIT_DISABLE_RP3_P0_3 = 0x80000F7C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQ_BIT_DISABLE_RP3_P0_3 = 0x80000F7C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP3_P0_4 = 0x8000137C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQ_BIT_DISABLE_RP3_P0_4 = 0x8000137C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQ_BIT_DISABLE_RP3_P0_4 = 0x8000137C0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQ_BIT_DISABLE_RP3_P1_0 = 0x8000037C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQ_BIT_DISABLE_RP3_P1_0 = 0x8000037C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQ_BIT_DISABLE_RP3_P1_1 = 0x8000077C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQ_BIT_DISABLE_RP3_P1_1 = 0x8000077C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQ_BIT_DISABLE_RP3_P1_2 = 0x80000B7C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQ_BIT_DISABLE_RP3_P1_2 = 0x80000B7C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQ_BIT_DISABLE_RP3_P1_3 = 0x80000F7C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQ_BIT_DISABLE_RP3_P1_3 = 0x80000F7C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQ_BIT_DISABLE_RP3_P1_4 = 0x8000137C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQ_BIT_DISABLE_RP3_P1_4 = 0x8000137C0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQ_BIT_DISABLE_RP3_P2_0 = 0x8000037C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQ_BIT_DISABLE_RP3_P2_0 = 0x8000037C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQ_BIT_DISABLE_RP3_P2_1 = 0x8000077C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQ_BIT_DISABLE_RP3_P2_1 = 0x8000077C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQ_BIT_DISABLE_RP3_P2_2 = 0x80000B7C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQ_BIT_DISABLE_RP3_P2_2 = 0x80000B7C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQ_BIT_DISABLE_RP3_P2_3 = 0x80000F7C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQ_BIT_DISABLE_RP3_P2_3 = 0x80000F7C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQ_BIT_DISABLE_RP3_P2_4 = 0x8000137C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQ_BIT_DISABLE_RP3_P2_4 = 0x8000137C0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQ_BIT_DISABLE_RP3_P3_0 = 0x8000037C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQ_BIT_DISABLE_RP3_P3_0 = 0x8000037C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQ_BIT_DISABLE_RP3_P3_1 = 0x8000077C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQ_BIT_DISABLE_RP3_P3_1 = 0x8000077C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQ_BIT_DISABLE_RP3_P3_2 = 0x80000B7C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQ_BIT_DISABLE_RP3_P3_2 = 0x80000B7C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQ_BIT_DISABLE_RP3_P3_3 = 0x80000F7C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQ_BIT_DISABLE_RP3_P3_3 = 0x80000F7C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQ_BIT_DISABLE_RP3_P3_4 = 0x8000137C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQ_BIT_DISABLE_RP3_P3_4 = 0x8000137C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_ENABLE0_P0_0 = 0x800000000701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQ_BIT_ENABLE0_P0_0 = 0x800000000701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQ_BIT_ENABLE0_P0_0 = 0x800000000801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_ENABLE0_P0_1 = 0x800004000701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQ_BIT_ENABLE0_P0_1 = 0x800004000701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQ_BIT_ENABLE0_P0_1 = 0x800004000801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_ENABLE0_P0_2 = 0x800008000701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQ_BIT_ENABLE0_P0_2 = 0x800008000701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQ_BIT_ENABLE0_P0_2 = 0x800008000801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_ENABLE0_P0_3 = 0x80000C000701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQ_BIT_ENABLE0_P0_3 = 0x80000C000701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQ_BIT_ENABLE0_P0_3 = 0x80000C000801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_ENABLE0_P0_4 = 0x800010000701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQ_BIT_ENABLE0_P0_4 = 0x800010000701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQ_BIT_ENABLE0_P0_4 = 0x800010000801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQ_BIT_ENABLE0_P1_0 = 0x800000000701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQ_BIT_ENABLE0_P1_0 = 0x800000000801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQ_BIT_ENABLE0_P1_1 = 0x800004000701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQ_BIT_ENABLE0_P1_1 = 0x800004000801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQ_BIT_ENABLE0_P1_2 = 0x800008000701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQ_BIT_ENABLE0_P1_2 = 0x800008000801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQ_BIT_ENABLE0_P1_3 = 0x80000C000701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQ_BIT_ENABLE0_P1_3 = 0x80000C000801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQ_BIT_ENABLE0_P1_4 = 0x800010000701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQ_BIT_ENABLE0_P1_4 = 0x800010000801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQ_BIT_ENABLE0_P2_0 = 0x800000000701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQ_BIT_ENABLE0_P2_0 = 0x800000000801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQ_BIT_ENABLE0_P2_1 = 0x800004000701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQ_BIT_ENABLE0_P2_1 = 0x800004000801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQ_BIT_ENABLE0_P2_2 = 0x800008000701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQ_BIT_ENABLE0_P2_2 = 0x800008000801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQ_BIT_ENABLE0_P2_3 = 0x80000C000701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQ_BIT_ENABLE0_P2_3 = 0x80000C000801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQ_BIT_ENABLE0_P2_4 = 0x800010000701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQ_BIT_ENABLE0_P2_4 = 0x800010000801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQ_BIT_ENABLE0_P3_0 = 0x8000000007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQ_BIT_ENABLE0_P3_0 = 0x8000000008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQ_BIT_ENABLE0_P3_1 = 0x8000040007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQ_BIT_ENABLE0_P3_1 = 0x8000040008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQ_BIT_ENABLE0_P3_2 = 0x8000080007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQ_BIT_ENABLE0_P3_2 = 0x8000080008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQ_BIT_ENABLE0_P3_3 = 0x80000C0007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQ_BIT_ENABLE0_P3_3 = 0x80000C0008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQ_BIT_ENABLE0_P3_4 = 0x8000100007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQ_BIT_ENABLE0_P3_4 = 0x8000100008011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQ_FORCE_OUTPUTS_P0_0 = 0x800000020701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQ_FORCE_OUTPUTS_P0_0 = 0x800000020701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQ_FORCE_OUTPUTS_P0_0 = 0x800000020801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQ_FORCE_OUTPUTS_P0_1 = 0x800004020701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQ_FORCE_OUTPUTS_P0_1 = 0x800004020701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQ_FORCE_OUTPUTS_P0_1 = 0x800004020801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQ_FORCE_OUTPUTS_P0_2 = 0x800008020701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQ_FORCE_OUTPUTS_P0_2 = 0x800008020701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQ_FORCE_OUTPUTS_P0_2 = 0x800008020801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQ_FORCE_OUTPUTS_P0_3 = 0x80000C020701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQ_FORCE_OUTPUTS_P0_3 = 0x80000C020701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQ_FORCE_OUTPUTS_P0_3 = 0x80000C020801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQ_FORCE_OUTPUTS_P0_4 = 0x800010020701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQ_FORCE_OUTPUTS_P0_4 = 0x800010020701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQ_FORCE_OUTPUTS_P0_4 = 0x800010020801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQ_FORCE_OUTPUTS_P1_0 = 0x800000020701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQ_FORCE_OUTPUTS_P1_0 = 0x800000020801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQ_FORCE_OUTPUTS_P1_1 = 0x800004020701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQ_FORCE_OUTPUTS_P1_1 = 0x800004020801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQ_FORCE_OUTPUTS_P1_2 = 0x800008020701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQ_FORCE_OUTPUTS_P1_2 = 0x800008020801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQ_FORCE_OUTPUTS_P1_3 = 0x80000C020701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQ_FORCE_OUTPUTS_P1_3 = 0x80000C020801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQ_FORCE_OUTPUTS_P1_4 = 0x800010020701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQ_FORCE_OUTPUTS_P1_4 = 0x800010020801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQ_FORCE_OUTPUTS_P2_0 = 0x800000020701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQ_FORCE_OUTPUTS_P2_0 = 0x800000020801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQ_FORCE_OUTPUTS_P2_1 = 0x800004020701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQ_FORCE_OUTPUTS_P2_1 = 0x800004020801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQ_FORCE_OUTPUTS_P2_2 = 0x800008020701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQ_FORCE_OUTPUTS_P2_2 = 0x800008020801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQ_FORCE_OUTPUTS_P2_3 = 0x80000C020701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQ_FORCE_OUTPUTS_P2_3 = 0x80000C020801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQ_FORCE_OUTPUTS_P2_4 = 0x800010020701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQ_FORCE_OUTPUTS_P2_4 = 0x800010020801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQ_FORCE_OUTPUTS_P3_0 = 0x8000000207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQ_FORCE_OUTPUTS_P3_0 = 0x8000000208011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQ_FORCE_OUTPUTS_P3_1 = 0x8000040207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQ_FORCE_OUTPUTS_P3_1 = 0x8000040208011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQ_FORCE_OUTPUTS_P3_2 = 0x8000080207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQ_FORCE_OUTPUTS_P3_2 = 0x8000080208011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQ_FORCE_OUTPUTS_P3_3 = 0x80000C0207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQ_FORCE_OUTPUTS_P3_3 = 0x80000C0208011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQ_FORCE_OUTPUTS_P3_4 = 0x8000100207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQ_FORCE_OUTPUTS_P3_4 = 0x8000100208011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_0 = 0x8000007E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_0 = 0x8000007E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_0 = 0x8000007E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_1 = 0x8000047E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_1 = 0x8000047E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_1 = 0x8000047E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_2 = 0x8000087E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_2 = 0x8000087E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_2 = 0x8000087E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_3 = 0x80000C7E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_3 = 0x80000C7E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_3 = 0x80000C7E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_4 = 0x8000107E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_4 = 0x8000107E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_4 = 0x8000107E0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P1_0 = 0x8000007E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P1_0 = 0x8000007E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P1_1 = 0x8000047E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P1_1 = 0x8000047E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P1_2 = 0x8000087E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P1_2 = 0x8000087E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P1_3 = 0x80000C7E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P1_3 = 0x80000C7E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P1_4 = 0x8000107E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P1_4 = 0x8000107E0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P2_0 = 0x8000007E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P2_0 = 0x8000007E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P2_1 = 0x8000047E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P2_1 = 0x8000047E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P2_2 = 0x8000087E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P2_2 = 0x8000087E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P2_3 = 0x80000C7E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P2_3 = 0x80000C7E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P2_4 = 0x8000107E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P2_4 = 0x8000107E0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P3_0 = 0x8000007E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P3_0 = 0x8000007E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P3_1 = 0x8000047E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P3_1 = 0x8000047E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P3_2 = 0x8000087E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P3_2 = 0x8000087E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P3_3 = 0x80000C7E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P3_3 = 0x80000C7E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P3_4 = 0x8000107E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P3_4 = 0x8000107E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_0 = 0x8000017E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_0 = 0x8000017E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_0 = 0x8000017E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_1 = 0x8000057E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_1 = 0x8000057E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_1 = 0x8000057E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_2 = 0x8000097E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_2 = 0x8000097E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_2 = 0x8000097E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_3 = 0x80000D7E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_3 = 0x80000D7E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_3 = 0x80000D7E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_4 = 0x8000117E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_4 = 0x8000117E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_4 = 0x8000117E0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P1_0 = 0x8000017E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P1_0 = 0x8000017E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P1_1 = 0x8000057E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P1_1 = 0x8000057E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P1_2 = 0x8000097E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P1_2 = 0x8000097E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P1_3 = 0x80000D7E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P1_3 = 0x80000D7E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P1_4 = 0x8000117E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P1_4 = 0x8000117E0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P2_0 = 0x8000017E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P2_0 = 0x8000017E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P2_1 = 0x8000057E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P2_1 = 0x8000057E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P2_2 = 0x8000097E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P2_2 = 0x8000097E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P2_3 = 0x80000D7E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P2_3 = 0x80000D7E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P2_4 = 0x8000117E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P2_4 = 0x8000117E0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P3_0 = 0x8000017E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P3_0 = 0x8000017E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P3_1 = 0x8000057E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P3_1 = 0x8000057E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P3_2 = 0x8000097E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P3_2 = 0x8000097E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P3_3 = 0x80000D7E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P3_3 = 0x80000D7E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P3_4 = 0x8000117E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P3_4 = 0x8000117E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_0 = 0x8000027E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_0 = 0x8000027E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_0 = 0x8000027E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_1 = 0x8000067E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_1 = 0x8000067E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_1 = 0x8000067E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_2 = 0x80000A7E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_2 = 0x80000A7E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_2 = 0x80000A7E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_3 = 0x80000E7E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_3 = 0x80000E7E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_3 = 0x80000E7E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_4 = 0x8000127E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_4 = 0x8000127E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_4 = 0x8000127E0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P1_0 = 0x8000027E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P1_0 = 0x8000027E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P1_1 = 0x8000067E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P1_1 = 0x8000067E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P1_2 = 0x80000A7E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P1_2 = 0x80000A7E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P1_3 = 0x80000E7E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P1_3 = 0x80000E7E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P1_4 = 0x8000127E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P1_4 = 0x8000127E0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P2_0 = 0x8000027E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P2_0 = 0x8000027E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P2_1 = 0x8000067E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P2_1 = 0x8000067E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P2_2 = 0x80000A7E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P2_2 = 0x80000A7E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P2_3 = 0x80000E7E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P2_3 = 0x80000E7E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P2_4 = 0x8000127E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P2_4 = 0x8000127E0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P3_0 = 0x8000027E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P3_0 = 0x8000027E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P3_1 = 0x8000067E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P3_1 = 0x8000067E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P3_2 = 0x80000A7E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P3_2 = 0x80000A7E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P3_3 = 0x80000E7E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P3_3 = 0x80000E7E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P3_4 = 0x8000127E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P3_4 = 0x8000127E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_0 = 0x8000037E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_0 = 0x8000037E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_0 = 0x8000037E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_1 = 0x8000077E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_1 = 0x8000077E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_1 = 0x8000077E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_2 = 0x80000B7E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_2 = 0x80000B7E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_2 = 0x80000B7E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_3 = 0x80000F7E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_3 = 0x80000F7E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_3 = 0x80000F7E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_4 = 0x8000137E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_4 = 0x8000137E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_4 = 0x8000137E0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P1_0 = 0x8000037E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P1_0 = 0x8000037E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P1_1 = 0x8000077E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P1_1 = 0x8000077E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P1_2 = 0x80000B7E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P1_2 = 0x80000B7E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P1_3 = 0x80000F7E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P1_3 = 0x80000F7E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P1_4 = 0x8000137E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P1_4 = 0x8000137E0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P2_0 = 0x8000037E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P2_0 = 0x8000037E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P2_1 = 0x8000077E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P2_1 = 0x8000077E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P2_2 = 0x80000B7E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P2_2 = 0x80000B7E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P2_3 = 0x80000F7E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P2_3 = 0x80000F7E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P2_4 = 0x8000137E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P2_4 = 0x8000137E0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P3_0 = 0x8000037E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P3_0 = 0x8000037E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P3_1 = 0x8000077E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P3_1 = 0x8000077E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P3_2 = 0x80000B7E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P3_2 = 0x80000B7E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P3_3 = 0x80000F7E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P3_3 = 0x80000F7E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P3_4 = 0x8000137E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P3_4 = 0x8000137E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_0 = 0x8000000A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DRIFT_LIMITS_P0_0 = 0x8000000A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DRIFT_LIMITS_P0_0 = 0x8000000A0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_1 = 0x8000040A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DRIFT_LIMITS_P0_1 = 0x8000040A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DRIFT_LIMITS_P0_1 = 0x8000040A0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_2 = 0x8000080A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DRIFT_LIMITS_P0_2 = 0x8000080A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DRIFT_LIMITS_P0_2 = 0x8000080A0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_3 = 0x80000C0A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DRIFT_LIMITS_P0_3 = 0x80000C0A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DRIFT_LIMITS_P0_3 = 0x80000C0A0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_4 = 0x8000100A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_DRIFT_LIMITS_P0_4 = 0x8000100A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_DRIFT_LIMITS_P0_4 = 0x8000100A0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DRIFT_LIMITS_P1_0 = 0x8000000A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DRIFT_LIMITS_P1_0 = 0x8000000A0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DRIFT_LIMITS_P1_1 = 0x8000040A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DRIFT_LIMITS_P1_1 = 0x8000040A0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DRIFT_LIMITS_P1_2 = 0x8000080A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DRIFT_LIMITS_P1_2 = 0x8000080A0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DRIFT_LIMITS_P1_3 = 0x80000C0A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DRIFT_LIMITS_P1_3 = 0x80000C0A0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_DRIFT_LIMITS_P1_4 = 0x8000100A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_DRIFT_LIMITS_P1_4 = 0x8000100A0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DRIFT_LIMITS_P2_0 = 0x8000000A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DRIFT_LIMITS_P2_0 = 0x8000000A0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DRIFT_LIMITS_P2_1 = 0x8000040A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DRIFT_LIMITS_P2_1 = 0x8000040A0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DRIFT_LIMITS_P2_2 = 0x8000080A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DRIFT_LIMITS_P2_2 = 0x8000080A0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DRIFT_LIMITS_P2_3 = 0x80000C0A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DRIFT_LIMITS_P2_3 = 0x80000C0A0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_DRIFT_LIMITS_P2_4 = 0x8000100A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_DRIFT_LIMITS_P2_4 = 0x8000100A0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DRIFT_LIMITS_P3_0 = 0x8000000A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DRIFT_LIMITS_P3_0 = 0x8000000A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DRIFT_LIMITS_P3_1 = 0x8000040A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DRIFT_LIMITS_P3_1 = 0x8000040A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DRIFT_LIMITS_P3_2 = 0x8000080A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DRIFT_LIMITS_P3_2 = 0x8000080A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DRIFT_LIMITS_P3_3 = 0x80000C0A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DRIFT_LIMITS_P3_3 = 0x80000C0A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_DRIFT_LIMITS_P3_4 = 0x8000100A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_DRIFT_LIMITS_P3_4 = 0x8000100A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_0 = 0x8000005C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_0 = 0x8000005C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_0 = 0x8000005C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_1 = 0x8000045C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_1 = 0x8000045C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_1 = 0x8000045C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_2 = 0x8000085C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_2 = 0x8000085C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_2 = 0x8000085C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_3 = 0x80000C5C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_3 = 0x80000C5C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_3 = 0x80000C5C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_4 = 0x8000105C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_4 = 0x8000105C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_4 = 0x8000105C0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P1_0 = 0x8000005C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P1_0 = 0x8000005C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P1_1 = 0x8000045C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P1_1 = 0x8000045C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P1_2 = 0x8000085C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P1_2 = 0x8000085C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P1_3 = 0x80000C5C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P1_3 = 0x80000C5C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P1_4 = 0x8000105C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P1_4 = 0x8000105C0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P2_0 = 0x8000005C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P2_0 = 0x8000005C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P2_1 = 0x8000045C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P2_1 = 0x8000045C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P2_2 = 0x8000085C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P2_2 = 0x8000085C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P2_3 = 0x80000C5C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P2_3 = 0x80000C5C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P2_4 = 0x8000105C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P2_4 = 0x8000105C0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P3_0 = 0x8000005C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P3_0 = 0x8000005C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P3_1 = 0x8000045C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P3_1 = 0x8000045C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P3_2 = 0x8000085C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P3_2 = 0x8000085C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P3_3 = 0x80000C5C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P3_3 = 0x80000C5C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P3_4 = 0x8000105C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P3_4 = 0x8000105C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_0 = 0x8000015C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_0 = 0x8000015C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_0 = 0x8000015C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_1 = 0x8000055C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_1 = 0x8000055C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_1 = 0x8000055C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_2 = 0x8000095C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_2 = 0x8000095C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_2 = 0x8000095C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_3 = 0x80000D5C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_3 = 0x80000D5C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_3 = 0x80000D5C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_4 = 0x8000115C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_4 = 0x8000115C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_4 = 0x8000115C0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P1_0 = 0x8000015C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P1_0 = 0x8000015C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P1_1 = 0x8000055C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P1_1 = 0x8000055C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P1_2 = 0x8000095C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P1_2 = 0x8000095C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P1_3 = 0x80000D5C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P1_3 = 0x80000D5C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P1_4 = 0x8000115C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P1_4 = 0x8000115C0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P2_0 = 0x8000015C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P2_0 = 0x8000015C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P2_1 = 0x8000055C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P2_1 = 0x8000055C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P2_2 = 0x8000095C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P2_2 = 0x8000095C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P2_3 = 0x80000D5C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P2_3 = 0x80000D5C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P2_4 = 0x8000115C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P2_4 = 0x8000115C0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P3_0 = 0x8000015C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P3_0 = 0x8000015C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P3_1 = 0x8000055C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P3_1 = 0x8000055C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P3_2 = 0x8000095C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P3_2 = 0x8000095C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P3_3 = 0x80000D5C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P3_3 = 0x80000D5C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P3_4 = 0x8000115C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P3_4 = 0x8000115C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_0 = 0x8000025C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_0 = 0x8000025C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_0 = 0x8000025C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_1 = 0x8000065C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_1 = 0x8000065C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_1 = 0x8000065C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_2 = 0x80000A5C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_2 = 0x80000A5C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_2 = 0x80000A5C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_3 = 0x80000E5C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_3 = 0x80000E5C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_3 = 0x80000E5C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_4 = 0x8000125C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_4 = 0x8000125C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_4 = 0x8000125C0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P1_0 = 0x8000025C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P1_0 = 0x8000025C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P1_1 = 0x8000065C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P1_1 = 0x8000065C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P1_2 = 0x80000A5C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P1_2 = 0x80000A5C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P1_3 = 0x80000E5C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P1_3 = 0x80000E5C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P1_4 = 0x8000125C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P1_4 = 0x8000125C0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P2_0 = 0x8000025C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P2_0 = 0x8000025C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P2_1 = 0x8000065C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P2_1 = 0x8000065C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P2_2 = 0x80000A5C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P2_2 = 0x80000A5C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P2_3 = 0x80000E5C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P2_3 = 0x80000E5C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P2_4 = 0x8000125C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P2_4 = 0x8000125C0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P3_0 = 0x8000025C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P3_0 = 0x8000025C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P3_1 = 0x8000065C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P3_1 = 0x8000065C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P3_2 = 0x80000A5C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P3_2 = 0x80000A5C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P3_3 = 0x80000E5C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P3_3 = 0x80000E5C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P3_4 = 0x8000125C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P3_4 = 0x8000125C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_0 = 0x8000035C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_0 = 0x8000035C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_0 = 0x8000035C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_1 = 0x8000075C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_1 = 0x8000075C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_1 = 0x8000075C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_2 = 0x80000B5C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_2 = 0x80000B5C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_2 = 0x80000B5C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_3 = 0x80000F5C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_3 = 0x80000F5C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_3 = 0x80000F5C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_4 = 0x8000135C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_4 = 0x8000135C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_4 = 0x8000135C0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P1_0 = 0x8000035C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P1_0 = 0x8000035C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P1_1 = 0x8000075C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P1_1 = 0x8000075C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P1_2 = 0x80000B5C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P1_2 = 0x80000B5C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P1_3 = 0x80000F5C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P1_3 = 0x80000F5C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P1_4 = 0x8000135C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P1_4 = 0x8000135C0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P2_0 = 0x8000035C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P2_0 = 0x8000035C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P2_1 = 0x8000075C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P2_1 = 0x8000075C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P2_2 = 0x80000B5C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P2_2 = 0x80000B5C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P2_3 = 0x80000F5C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P2_3 = 0x80000F5C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P2_4 = 0x8000135C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P2_4 = 0x8000135C0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P3_0 = 0x8000035C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P3_0 = 0x8000035C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P3_1 = 0x8000075C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P3_1 = 0x8000075C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P3_2 = 0x80000B5C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P3_2 = 0x80000B5C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P3_3 = 0x80000F5C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P3_3 = 0x80000F5C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P3_4 = 0x8000135C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P3_4 = 0x8000135C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_0 = 0x8000005D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_0 = 0x8000005D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_0 = 0x8000005D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_1 = 0x8000045D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_1 = 0x8000045D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_1 = 0x8000045D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_2 = 0x8000085D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_2 = 0x8000085D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_2 = 0x8000085D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_3 = 0x80000C5D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_3 = 0x80000C5D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_3 = 0x80000C5D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_4 = 0x8000105D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_4 = 0x8000105D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_4 = 0x8000105D0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P1_0 = 0x8000005D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P1_0 = 0x8000005D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P1_1 = 0x8000045D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P1_1 = 0x8000045D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P1_2 = 0x8000085D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P1_2 = 0x8000085D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P1_3 = 0x80000C5D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P1_3 = 0x80000C5D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P1_4 = 0x8000105D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P1_4 = 0x8000105D0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P2_0 = 0x8000005D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P2_0 = 0x8000005D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P2_1 = 0x8000045D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P2_1 = 0x8000045D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P2_2 = 0x8000085D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P2_2 = 0x8000085D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P2_3 = 0x80000C5D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P2_3 = 0x80000C5D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P2_4 = 0x8000105D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P2_4 = 0x8000105D0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P3_0 = 0x8000005D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P3_0 = 0x8000005D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P3_1 = 0x8000045D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P3_1 = 0x8000045D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P3_2 = 0x8000085D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P3_2 = 0x8000085D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P3_3 = 0x80000C5D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P3_3 = 0x80000C5D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P3_4 = 0x8000105D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P3_4 = 0x8000105D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_0 = 0x8000015D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_0 = 0x8000015D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_0 = 0x8000015D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_1 = 0x8000055D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_1 = 0x8000055D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_1 = 0x8000055D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_2 = 0x8000095D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_2 = 0x8000095D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_2 = 0x8000095D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_3 = 0x80000D5D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_3 = 0x80000D5D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_3 = 0x80000D5D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_4 = 0x8000115D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_4 = 0x8000115D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_4 = 0x8000115D0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P1_0 = 0x8000015D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P1_0 = 0x8000015D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P1_1 = 0x8000055D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P1_1 = 0x8000055D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P1_2 = 0x8000095D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P1_2 = 0x8000095D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P1_3 = 0x80000D5D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P1_3 = 0x80000D5D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P1_4 = 0x8000115D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P1_4 = 0x8000115D0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P2_0 = 0x8000015D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P2_0 = 0x8000015D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P2_1 = 0x8000055D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P2_1 = 0x8000055D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P2_2 = 0x8000095D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P2_2 = 0x8000095D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P2_3 = 0x80000D5D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P2_3 = 0x80000D5D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P2_4 = 0x8000115D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P2_4 = 0x8000115D0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P3_0 = 0x8000015D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P3_0 = 0x8000015D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P3_1 = 0x8000055D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P3_1 = 0x8000055D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P3_2 = 0x8000095D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P3_2 = 0x8000095D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P3_3 = 0x80000D5D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P3_3 = 0x80000D5D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P3_4 = 0x8000115D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P3_4 = 0x8000115D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_0 = 0x8000025D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_0 = 0x8000025D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_0 = 0x8000025D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_1 = 0x8000065D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_1 = 0x8000065D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_1 = 0x8000065D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_2 = 0x80000A5D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_2 = 0x80000A5D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_2 = 0x80000A5D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_3 = 0x80000E5D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_3 = 0x80000E5D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_3 = 0x80000E5D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_4 = 0x8000125D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_4 = 0x8000125D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_4 = 0x8000125D0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P1_0 = 0x8000025D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P1_0 = 0x8000025D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P1_1 = 0x8000065D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P1_1 = 0x8000065D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P1_2 = 0x80000A5D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P1_2 = 0x80000A5D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P1_3 = 0x80000E5D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P1_3 = 0x80000E5D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P1_4 = 0x8000125D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P1_4 = 0x8000125D0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P2_0 = 0x8000025D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P2_0 = 0x8000025D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P2_1 = 0x8000065D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P2_1 = 0x8000065D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P2_2 = 0x80000A5D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P2_2 = 0x80000A5D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P2_3 = 0x80000E5D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P2_3 = 0x80000E5D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P2_4 = 0x8000125D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P2_4 = 0x8000125D0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P3_0 = 0x8000025D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P3_0 = 0x8000025D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P3_1 = 0x8000065D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P3_1 = 0x8000065D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P3_2 = 0x80000A5D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P3_2 = 0x80000A5D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P3_3 = 0x80000E5D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P3_3 = 0x80000E5D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P3_4 = 0x8000125D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P3_4 = 0x8000125D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_0 = 0x8000035D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_0 = 0x8000035D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_0 = 0x8000035D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_1 = 0x8000075D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_1 = 0x8000075D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_1 = 0x8000075D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_2 = 0x80000B5D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_2 = 0x80000B5D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_2 = 0x80000B5D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_3 = 0x80000F5D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_3 = 0x80000F5D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_3 = 0x80000F5D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_4 = 0x8000135D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_4 = 0x8000135D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_4 = 0x8000135D0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P1_0 = 0x8000035D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P1_0 = 0x8000035D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P1_1 = 0x8000075D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P1_1 = 0x8000075D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P1_2 = 0x80000B5D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P1_2 = 0x80000B5D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P1_3 = 0x80000F5D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P1_3 = 0x80000F5D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P1_4 = 0x8000135D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P1_4 = 0x8000135D0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P2_0 = 0x8000035D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P2_0 = 0x8000035D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P2_1 = 0x8000075D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P2_1 = 0x8000075D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P2_2 = 0x80000B5D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P2_2 = 0x80000B5D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P2_3 = 0x80000F5D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P2_3 = 0x80000F5D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P2_4 = 0x8000135D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P2_4 = 0x8000135D0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P3_0 = 0x8000035D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P3_0 = 0x8000035D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P3_1 = 0x8000075D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P3_1 = 0x8000075D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P3_2 = 0x80000B5D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P3_2 = 0x80000B5D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P3_3 = 0x80000F5D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P3_3 = 0x80000F5D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P3_4 = 0x8000135D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P3_4 = 0x8000135D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_0 = 0x800000750701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_IO_TX_CONFIG0_P0_0 = 0x800000750701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_IO_TX_CONFIG0_P0_0 = 0x800000750801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_1 = 0x800004750701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_IO_TX_CONFIG0_P0_1 = 0x800004750701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_IO_TX_CONFIG0_P0_1 = 0x800004750801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_2 = 0x800008750701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_IO_TX_CONFIG0_P0_2 = 0x800008750701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_IO_TX_CONFIG0_P0_2 = 0x800008750801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_3 = 0x80000C750701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_IO_TX_CONFIG0_P0_3 = 0x80000C750701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_IO_TX_CONFIG0_P0_3 = 0x80000C750801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_4 = 0x800010750701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_IO_TX_CONFIG0_P0_4 = 0x800010750701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_IO_TX_CONFIG0_P0_4 = 0x800010750801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_IO_TX_CONFIG0_P1_0 = 0x800000750701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_IO_TX_CONFIG0_P1_0 = 0x800000750801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_IO_TX_CONFIG0_P1_1 = 0x800004750701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_IO_TX_CONFIG0_P1_1 = 0x800004750801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_IO_TX_CONFIG0_P1_2 = 0x800008750701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_IO_TX_CONFIG0_P1_2 = 0x800008750801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_IO_TX_CONFIG0_P1_3 = 0x80000C750701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_IO_TX_CONFIG0_P1_3 = 0x80000C750801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_IO_TX_CONFIG0_P1_4 = 0x800010750701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_IO_TX_CONFIG0_P1_4 = 0x800010750801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_IO_TX_CONFIG0_P2_0 = 0x800000750701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_IO_TX_CONFIG0_P2_0 = 0x800000750801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_IO_TX_CONFIG0_P2_1 = 0x800004750701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_IO_TX_CONFIG0_P2_1 = 0x800004750801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_IO_TX_CONFIG0_P2_2 = 0x800008750701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_IO_TX_CONFIG0_P2_2 = 0x800008750801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_IO_TX_CONFIG0_P2_3 = 0x80000C750701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_IO_TX_CONFIG0_P2_3 = 0x80000C750801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_IO_TX_CONFIG0_P2_4 = 0x800010750701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_IO_TX_CONFIG0_P2_4 = 0x800010750801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_IO_TX_CONFIG0_P3_0 = 0x8000007507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_IO_TX_CONFIG0_P3_0 = 0x8000007508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_IO_TX_CONFIG0_P3_1 = 0x8000047507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_IO_TX_CONFIG0_P3_1 = 0x8000047508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_IO_TX_CONFIG0_P3_2 = 0x8000087507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_IO_TX_CONFIG0_P3_2 = 0x8000087508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_IO_TX_CONFIG0_P3_3 = 0x80000C7507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_IO_TX_CONFIG0_P3_3 = 0x80000C7508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_IO_TX_CONFIG0_P3_4 = 0x8000107507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_IO_TX_CONFIG0_P3_4 = 0x8000107508011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_0 = 0x800000780701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_IO_TX_FET_SLICE_P0_0 = 0x800000780701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_IO_TX_FET_SLICE_P0_0 = 0x800000780801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_1 = 0x800004780701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_IO_TX_FET_SLICE_P0_1 = 0x800004780701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_IO_TX_FET_SLICE_P0_1 = 0x800004780801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_2 = 0x800008780701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_IO_TX_FET_SLICE_P0_2 = 0x800008780701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_IO_TX_FET_SLICE_P0_2 = 0x800008780801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_3 = 0x80000C780701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_IO_TX_FET_SLICE_P0_3 = 0x80000C780701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_IO_TX_FET_SLICE_P0_3 = 0x80000C780801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_4 = 0x800010780701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_IO_TX_FET_SLICE_P0_4 = 0x800010780701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_IO_TX_FET_SLICE_P0_4 = 0x800010780801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_IO_TX_FET_SLICE_P1_0 = 0x800000780701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_IO_TX_FET_SLICE_P1_0 = 0x800000780801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_IO_TX_FET_SLICE_P1_1 = 0x800004780701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_IO_TX_FET_SLICE_P1_1 = 0x800004780801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_IO_TX_FET_SLICE_P1_2 = 0x800008780701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_IO_TX_FET_SLICE_P1_2 = 0x800008780801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_IO_TX_FET_SLICE_P1_3 = 0x80000C780701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_IO_TX_FET_SLICE_P1_3 = 0x80000C780801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_IO_TX_FET_SLICE_P1_4 = 0x800010780701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_IO_TX_FET_SLICE_P1_4 = 0x800010780801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_IO_TX_FET_SLICE_P2_0 = 0x800000780701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_IO_TX_FET_SLICE_P2_0 = 0x800000780801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_IO_TX_FET_SLICE_P2_1 = 0x800004780701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_IO_TX_FET_SLICE_P2_1 = 0x800004780801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_IO_TX_FET_SLICE_P2_2 = 0x800008780701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_IO_TX_FET_SLICE_P2_2 = 0x800008780801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_IO_TX_FET_SLICE_P2_3 = 0x80000C780701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_IO_TX_FET_SLICE_P2_3 = 0x80000C780801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_IO_TX_FET_SLICE_P2_4 = 0x800010780701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_IO_TX_FET_SLICE_P2_4 = 0x800010780801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_IO_TX_FET_SLICE_P3_0 = 0x8000007807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_IO_TX_FET_SLICE_P3_0 = 0x8000007808011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_IO_TX_FET_SLICE_P3_1 = 0x8000047807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_IO_TX_FET_SLICE_P3_1 = 0x8000047808011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_IO_TX_FET_SLICE_P3_2 = 0x8000087807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_IO_TX_FET_SLICE_P3_2 = 0x8000087808011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_IO_TX_FET_SLICE_P3_3 = 0x80000C7807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_IO_TX_FET_SLICE_P3_3 = 0x80000C7808011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_IO_TX_FET_SLICE_P3_4 = 0x8000107807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_IO_TX_FET_SLICE_P3_4 = 0x8000107808011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_0 = 0x8000007B0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_IO_TX_PFET_TERM_P0_0 = 0x8000007B0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_IO_TX_PFET_TERM_P0_0 = 0x8000007B0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_1 = 0x8000047B0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_IO_TX_PFET_TERM_P0_1 = 0x8000047B0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_IO_TX_PFET_TERM_P0_1 = 0x8000047B0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_2 = 0x8000087B0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_IO_TX_PFET_TERM_P0_2 = 0x8000087B0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_IO_TX_PFET_TERM_P0_2 = 0x8000087B0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_3 = 0x80000C7B0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_IO_TX_PFET_TERM_P0_3 = 0x80000C7B0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_IO_TX_PFET_TERM_P0_3 = 0x80000C7B0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_4 = 0x8000107B0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_IO_TX_PFET_TERM_P0_4 = 0x8000107B0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_IO_TX_PFET_TERM_P0_4 = 0x8000107B0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_IO_TX_PFET_TERM_P1_0 = 0x8000007B0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_IO_TX_PFET_TERM_P1_0 = 0x8000007B0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_IO_TX_PFET_TERM_P1_1 = 0x8000047B0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_IO_TX_PFET_TERM_P1_1 = 0x8000047B0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_IO_TX_PFET_TERM_P1_2 = 0x8000087B0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_IO_TX_PFET_TERM_P1_2 = 0x8000087B0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_IO_TX_PFET_TERM_P1_3 = 0x80000C7B0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_IO_TX_PFET_TERM_P1_3 = 0x80000C7B0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_IO_TX_PFET_TERM_P1_4 = 0x8000107B0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_IO_TX_PFET_TERM_P1_4 = 0x8000107B0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_IO_TX_PFET_TERM_P2_0 = 0x8000007B0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_IO_TX_PFET_TERM_P2_0 = 0x8000007B0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_IO_TX_PFET_TERM_P2_1 = 0x8000047B0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_IO_TX_PFET_TERM_P2_1 = 0x8000047B0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_IO_TX_PFET_TERM_P2_2 = 0x8000087B0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_IO_TX_PFET_TERM_P2_2 = 0x8000087B0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_IO_TX_PFET_TERM_P2_3 = 0x80000C7B0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_IO_TX_PFET_TERM_P2_3 = 0x80000C7B0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_IO_TX_PFET_TERM_P2_4 = 0x8000107B0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_IO_TX_PFET_TERM_P2_4 = 0x8000107B0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_IO_TX_PFET_TERM_P3_0 = 0x8000007B07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_IO_TX_PFET_TERM_P3_0 = 0x8000007B08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_IO_TX_PFET_TERM_P3_1 = 0x8000047B07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_IO_TX_PFET_TERM_P3_1 = 0x8000047B08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_IO_TX_PFET_TERM_P3_2 = 0x8000087B07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_IO_TX_PFET_TERM_P3_2 = 0x8000087B08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_IO_TX_PFET_TERM_P3_3 = 0x80000C7B07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_IO_TX_PFET_TERM_P3_3 = 0x80000C7B08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_IO_TX_PFET_TERM_P3_4 = 0x8000107B07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_IO_TX_PFET_TERM_P3_4 = 0x8000107B08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_0 = 0x800000790701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_LO_PROBE_SELECT_P0_0 = 0x800000790701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_LO_PROBE_SELECT_P0_0 = 0x800000790801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_1 = 0x800004790701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_LO_PROBE_SELECT_P0_1 = 0x800004790701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_LO_PROBE_SELECT_P0_1 = 0x800004790801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_2 = 0x800008790701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_LO_PROBE_SELECT_P0_2 = 0x800008790701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_LO_PROBE_SELECT_P0_2 = 0x800008790801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_3 = 0x80000C790701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_LO_PROBE_SELECT_P0_3 = 0x80000C790701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_LO_PROBE_SELECT_P0_3 = 0x80000C790801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_4 = 0x800010790701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_LO_PROBE_SELECT_P0_4 = 0x800010790701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_LO_PROBE_SELECT_P0_4 = 0x800010790801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_LO_PROBE_SELECT_P1_0 = 0x800000790701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_LO_PROBE_SELECT_P1_0 = 0x800000790801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_LO_PROBE_SELECT_P1_1 = 0x800004790701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_LO_PROBE_SELECT_P1_1 = 0x800004790801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_LO_PROBE_SELECT_P1_2 = 0x800008790701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_LO_PROBE_SELECT_P1_2 = 0x800008790801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_LO_PROBE_SELECT_P1_3 = 0x80000C790701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_LO_PROBE_SELECT_P1_3 = 0x80000C790801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_LO_PROBE_SELECT_P1_4 = 0x800010790701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_LO_PROBE_SELECT_P1_4 = 0x800010790801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_LO_PROBE_SELECT_P2_0 = 0x800000790701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_LO_PROBE_SELECT_P2_0 = 0x800000790801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_LO_PROBE_SELECT_P2_1 = 0x800004790701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_LO_PROBE_SELECT_P2_1 = 0x800004790801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_LO_PROBE_SELECT_P2_2 = 0x800008790701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_LO_PROBE_SELECT_P2_2 = 0x800008790801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_LO_PROBE_SELECT_P2_3 = 0x80000C790701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_LO_PROBE_SELECT_P2_3 = 0x80000C790801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_LO_PROBE_SELECT_P2_4 = 0x800010790701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_LO_PROBE_SELECT_P2_4 = 0x800010790801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_LO_PROBE_SELECT_P3_0 = 0x8000007907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_LO_PROBE_SELECT_P3_0 = 0x8000007908011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_LO_PROBE_SELECT_P3_1 = 0x8000047907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_LO_PROBE_SELECT_P3_1 = 0x8000047908011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_LO_PROBE_SELECT_P3_2 = 0x8000087907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_LO_PROBE_SELECT_P3_2 = 0x8000087908011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_LO_PROBE_SELECT_P3_3 = 0x80000C7907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_LO_PROBE_SELECT_P3_3 = 0x80000C7908011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_LO_PROBE_SELECT_P3_4 = 0x8000107907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_LO_PROBE_SELECT_P3_4 = 0x8000107908011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_0 = 0x800000320701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_PATTERN_POS_0_P0_0 = 0x800000320701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_PATTERN_POS_0_P0_0 = 0x800000320801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_1 = 0x800004320701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_PATTERN_POS_0_P0_1 = 0x800004320701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_PATTERN_POS_0_P0_1 = 0x800004320801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_2 = 0x800008320701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_PATTERN_POS_0_P0_2 = 0x800008320701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_PATTERN_POS_0_P0_2 = 0x800008320801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_3 = 0x80000C320701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_PATTERN_POS_0_P0_3 = 0x80000C320701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_PATTERN_POS_0_P0_3 = 0x80000C320801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_4 = 0x800010320701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_PATTERN_POS_0_P0_4 = 0x800010320701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_PATTERN_POS_0_P0_4 = 0x800010320801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_PATTERN_POS_0_P1_0 = 0x800000320701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_PATTERN_POS_0_P1_0 = 0x800000320801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_PATTERN_POS_0_P1_1 = 0x800004320701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_PATTERN_POS_0_P1_1 = 0x800004320801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_PATTERN_POS_0_P1_2 = 0x800008320701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_PATTERN_POS_0_P1_2 = 0x800008320801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_PATTERN_POS_0_P1_3 = 0x80000C320701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_PATTERN_POS_0_P1_3 = 0x80000C320801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_PATTERN_POS_0_P1_4 = 0x800010320701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_PATTERN_POS_0_P1_4 = 0x800010320801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_PATTERN_POS_0_P2_0 = 0x800000320701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_PATTERN_POS_0_P2_0 = 0x800000320801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_PATTERN_POS_0_P2_1 = 0x800004320701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_PATTERN_POS_0_P2_1 = 0x800004320801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_PATTERN_POS_0_P2_2 = 0x800008320701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_PATTERN_POS_0_P2_2 = 0x800008320801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_PATTERN_POS_0_P2_3 = 0x80000C320701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_PATTERN_POS_0_P2_3 = 0x80000C320801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_PATTERN_POS_0_P2_4 = 0x800010320701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_PATTERN_POS_0_P2_4 = 0x800010320801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_PATTERN_POS_0_P3_0 = 0x8000003207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_PATTERN_POS_0_P3_0 = 0x8000003208011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_PATTERN_POS_0_P3_1 = 0x8000043207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_PATTERN_POS_0_P3_1 = 0x8000043208011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_PATTERN_POS_0_P3_2 = 0x8000083207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_PATTERN_POS_0_P3_2 = 0x8000083208011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_PATTERN_POS_0_P3_3 = 0x80000C3207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_PATTERN_POS_0_P3_3 = 0x80000C3208011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_PATTERN_POS_0_P3_4 = 0x8000103207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_PATTERN_POS_0_P3_4 = 0x8000103208011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_0 = 0x800000330701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_PATTERN_POS_1_P0_0 = 0x800000330701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_PATTERN_POS_1_P0_0 = 0x800000330801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_1 = 0x800004330701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_PATTERN_POS_1_P0_1 = 0x800004330701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_PATTERN_POS_1_P0_1 = 0x800004330801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_2 = 0x800008330701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_PATTERN_POS_1_P0_2 = 0x800008330701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_PATTERN_POS_1_P0_2 = 0x800008330801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_3 = 0x80000C330701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_PATTERN_POS_1_P0_3 = 0x80000C330701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_PATTERN_POS_1_P0_3 = 0x80000C330801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_4 = 0x800010330701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_PATTERN_POS_1_P0_4 = 0x800010330701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_PATTERN_POS_1_P0_4 = 0x800010330801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_PATTERN_POS_1_P1_0 = 0x800000330701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_PATTERN_POS_1_P1_0 = 0x800000330801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_PATTERN_POS_1_P1_1 = 0x800004330701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_PATTERN_POS_1_P1_1 = 0x800004330801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_PATTERN_POS_1_P1_2 = 0x800008330701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_PATTERN_POS_1_P1_2 = 0x800008330801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_PATTERN_POS_1_P1_3 = 0x80000C330701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_PATTERN_POS_1_P1_3 = 0x80000C330801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_PATTERN_POS_1_P1_4 = 0x800010330701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_PATTERN_POS_1_P1_4 = 0x800010330801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_PATTERN_POS_1_P2_0 = 0x800000330701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_PATTERN_POS_1_P2_0 = 0x800000330801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_PATTERN_POS_1_P2_1 = 0x800004330701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_PATTERN_POS_1_P2_1 = 0x800004330801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_PATTERN_POS_1_P2_2 = 0x800008330701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_PATTERN_POS_1_P2_2 = 0x800008330801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_PATTERN_POS_1_P2_3 = 0x80000C330701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_PATTERN_POS_1_P2_3 = 0x80000C330801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_PATTERN_POS_1_P2_4 = 0x800010330701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_PATTERN_POS_1_P2_4 = 0x800010330801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_PATTERN_POS_1_P3_0 = 0x8000003307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_PATTERN_POS_1_P3_0 = 0x8000003308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_PATTERN_POS_1_P3_1 = 0x8000043307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_PATTERN_POS_1_P3_1 = 0x8000043308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_PATTERN_POS_1_P3_2 = 0x8000083307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_PATTERN_POS_1_P3_2 = 0x8000083308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_PATTERN_POS_1_P3_3 = 0x80000C3307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_PATTERN_POS_1_P3_3 = 0x80000C3308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_PATTERN_POS_1_P3_4 = 0x8000103307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_PATTERN_POS_1_P3_4 = 0x8000103308011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_0 = 0x8000001E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_DIA_CONFIG0_P0_0 = 0x8000001E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_DIA_CONFIG0_P0_0 = 0x8000001E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_1 = 0x8000041E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_DIA_CONFIG0_P0_1 = 0x8000041E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_DIA_CONFIG0_P0_1 = 0x8000041E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_2 = 0x8000081E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_DIA_CONFIG0_P0_2 = 0x8000081E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_DIA_CONFIG0_P0_2 = 0x8000081E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_3 = 0x80000C1E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_DIA_CONFIG0_P0_3 = 0x80000C1E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_DIA_CONFIG0_P0_3 = 0x80000C1E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_4 = 0x8000101E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_DIA_CONFIG0_P0_4 = 0x8000101E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_DIA_CONFIG0_P0_4 = 0x8000101E0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_DIA_CONFIG0_P1_0 = 0x8000001E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_DIA_CONFIG0_P1_0 = 0x8000001E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_DIA_CONFIG0_P1_1 = 0x8000041E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_DIA_CONFIG0_P1_1 = 0x8000041E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_DIA_CONFIG0_P1_2 = 0x8000081E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_DIA_CONFIG0_P1_2 = 0x8000081E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_DIA_CONFIG0_P1_3 = 0x80000C1E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_DIA_CONFIG0_P1_3 = 0x80000C1E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_DIA_CONFIG0_P1_4 = 0x8000101E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_DIA_CONFIG0_P1_4 = 0x8000101E0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_DIA_CONFIG0_P2_0 = 0x8000001E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_DIA_CONFIG0_P2_0 = 0x8000001E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_DIA_CONFIG0_P2_1 = 0x8000041E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_DIA_CONFIG0_P2_1 = 0x8000041E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_DIA_CONFIG0_P2_2 = 0x8000081E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_DIA_CONFIG0_P2_2 = 0x8000081E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_DIA_CONFIG0_P2_3 = 0x80000C1E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_DIA_CONFIG0_P2_3 = 0x80000C1E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_DIA_CONFIG0_P2_4 = 0x8000101E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_DIA_CONFIG0_P2_4 = 0x8000101E0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_DIA_CONFIG0_P3_0 = 0x8000001E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_DIA_CONFIG0_P3_0 = 0x8000001E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_DIA_CONFIG0_P3_1 = 0x8000041E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_DIA_CONFIG0_P3_1 = 0x8000041E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_DIA_CONFIG0_P3_2 = 0x8000081E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_DIA_CONFIG0_P3_2 = 0x8000081E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_DIA_CONFIG0_P3_3 = 0x80000C1E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_DIA_CONFIG0_P3_3 = 0x80000C1E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_DIA_CONFIG0_P3_4 = 0x8000101E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_DIA_CONFIG0_P3_4 = 0x8000101E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_0 = 0x800000350701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_DIA_CONFIG1_P0_0 = 0x800000350701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_DIA_CONFIG1_P0_0 = 0x800000350801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_1 = 0x800004350701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_DIA_CONFIG1_P0_1 = 0x800004350701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_DIA_CONFIG1_P0_1 = 0x800004350801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_2 = 0x800008350701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_DIA_CONFIG1_P0_2 = 0x800008350701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_DIA_CONFIG1_P0_2 = 0x800008350801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_3 = 0x80000C350701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_DIA_CONFIG1_P0_3 = 0x80000C350701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_DIA_CONFIG1_P0_3 = 0x80000C350801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_4 = 0x800010350701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_DIA_CONFIG1_P0_4 = 0x800010350701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_DIA_CONFIG1_P0_4 = 0x800010350801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_DIA_CONFIG1_P1_0 = 0x800000350701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_DIA_CONFIG1_P1_0 = 0x800000350801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_DIA_CONFIG1_P1_1 = 0x800004350701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_DIA_CONFIG1_P1_1 = 0x800004350801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_DIA_CONFIG1_P1_2 = 0x800008350701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_DIA_CONFIG1_P1_2 = 0x800008350801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_DIA_CONFIG1_P1_3 = 0x80000C350701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_DIA_CONFIG1_P1_3 = 0x80000C350801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_DIA_CONFIG1_P1_4 = 0x800010350701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_DIA_CONFIG1_P1_4 = 0x800010350801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_DIA_CONFIG1_P2_0 = 0x800000350701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_DIA_CONFIG1_P2_0 = 0x800000350801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_DIA_CONFIG1_P2_1 = 0x800004350701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_DIA_CONFIG1_P2_1 = 0x800004350801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_DIA_CONFIG1_P2_2 = 0x800008350701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_DIA_CONFIG1_P2_2 = 0x800008350801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_DIA_CONFIG1_P2_3 = 0x80000C350701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_DIA_CONFIG1_P2_3 = 0x80000C350801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_DIA_CONFIG1_P2_4 = 0x800010350701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_DIA_CONFIG1_P2_4 = 0x800010350801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_DIA_CONFIG1_P3_0 = 0x8000003507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_DIA_CONFIG1_P3_0 = 0x8000003508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_DIA_CONFIG1_P3_1 = 0x8000043507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_DIA_CONFIG1_P3_1 = 0x8000043508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_DIA_CONFIG1_P3_2 = 0x8000083507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_DIA_CONFIG1_P3_2 = 0x8000083508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_DIA_CONFIG1_P3_3 = 0x80000C3507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_DIA_CONFIG1_P3_3 = 0x80000C3508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_DIA_CONFIG1_P3_4 = 0x8000103507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_DIA_CONFIG1_P3_4 = 0x8000103508011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_0 = 0x800000360701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_DIA_CONFIG2_P0_0 = 0x800000360701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_DIA_CONFIG2_P0_0 = 0x800000360801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_1 = 0x800004360701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_DIA_CONFIG2_P0_1 = 0x800004360701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_DIA_CONFIG2_P0_1 = 0x800004360801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_2 = 0x800008360701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_DIA_CONFIG2_P0_2 = 0x800008360701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_DIA_CONFIG2_P0_2 = 0x800008360801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_3 = 0x80000C360701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_DIA_CONFIG2_P0_3 = 0x80000C360701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_DIA_CONFIG2_P0_3 = 0x80000C360801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_4 = 0x800010360701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_DIA_CONFIG2_P0_4 = 0x800010360701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_DIA_CONFIG2_P0_4 = 0x800010360801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_DIA_CONFIG2_P1_0 = 0x800000360701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_DIA_CONFIG2_P1_0 = 0x800000360801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_DIA_CONFIG2_P1_1 = 0x800004360701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_DIA_CONFIG2_P1_1 = 0x800004360801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_DIA_CONFIG2_P1_2 = 0x800008360701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_DIA_CONFIG2_P1_2 = 0x800008360801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_DIA_CONFIG2_P1_3 = 0x80000C360701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_DIA_CONFIG2_P1_3 = 0x80000C360801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_DIA_CONFIG2_P1_4 = 0x800010360701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_DIA_CONFIG2_P1_4 = 0x800010360801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_DIA_CONFIG2_P2_0 = 0x800000360701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_DIA_CONFIG2_P2_0 = 0x800000360801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_DIA_CONFIG2_P2_1 = 0x800004360701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_DIA_CONFIG2_P2_1 = 0x800004360801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_DIA_CONFIG2_P2_2 = 0x800008360701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_DIA_CONFIG2_P2_2 = 0x800008360801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_DIA_CONFIG2_P2_3 = 0x80000C360701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_DIA_CONFIG2_P2_3 = 0x80000C360801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_DIA_CONFIG2_P2_4 = 0x800010360701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_DIA_CONFIG2_P2_4 = 0x800010360801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_DIA_CONFIG2_P3_0 = 0x8000003607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_DIA_CONFIG2_P3_0 = 0x8000003608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_DIA_CONFIG2_P3_1 = 0x8000043607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_DIA_CONFIG2_P3_1 = 0x8000043608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_DIA_CONFIG2_P3_2 = 0x8000083607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_DIA_CONFIG2_P3_2 = 0x8000083608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_DIA_CONFIG2_P3_3 = 0x80000C3607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_DIA_CONFIG2_P3_3 = 0x80000C3608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_DIA_CONFIG2_P3_4 = 0x8000103607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_DIA_CONFIG2_P3_4 = 0x8000103608011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_0 = 0x8000006D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_DIA_CONFIG3_P0_0 = 0x8000006D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_DIA_CONFIG3_P0_0 = 0x8000006D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_1 = 0x8000046D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_DIA_CONFIG3_P0_1 = 0x8000046D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_DIA_CONFIG3_P0_1 = 0x8000046D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_2 = 0x8000086D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_DIA_CONFIG3_P0_2 = 0x8000086D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_DIA_CONFIG3_P0_2 = 0x8000086D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_3 = 0x80000C6D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_DIA_CONFIG3_P0_3 = 0x80000C6D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_DIA_CONFIG3_P0_3 = 0x80000C6D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_4 = 0x8000106D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_DIA_CONFIG3_P0_4 = 0x8000106D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_DIA_CONFIG3_P0_4 = 0x8000106D0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_DIA_CONFIG3_P1_0 = 0x8000006D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_DIA_CONFIG3_P1_0 = 0x8000006D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_DIA_CONFIG3_P1_1 = 0x8000046D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_DIA_CONFIG3_P1_1 = 0x8000046D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_DIA_CONFIG3_P1_2 = 0x8000086D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_DIA_CONFIG3_P1_2 = 0x8000086D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_DIA_CONFIG3_P1_3 = 0x80000C6D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_DIA_CONFIG3_P1_3 = 0x80000C6D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_DIA_CONFIG3_P1_4 = 0x8000106D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_DIA_CONFIG3_P1_4 = 0x8000106D0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_DIA_CONFIG3_P2_0 = 0x8000006D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_DIA_CONFIG3_P2_0 = 0x8000006D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_DIA_CONFIG3_P2_1 = 0x8000046D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_DIA_CONFIG3_P2_1 = 0x8000046D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_DIA_CONFIG3_P2_2 = 0x8000086D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_DIA_CONFIG3_P2_2 = 0x8000086D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_DIA_CONFIG3_P2_3 = 0x80000C6D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_DIA_CONFIG3_P2_3 = 0x80000C6D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_DIA_CONFIG3_P2_4 = 0x8000106D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_DIA_CONFIG3_P2_4 = 0x8000106D0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_DIA_CONFIG3_P3_0 = 0x8000006D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_DIA_CONFIG3_P3_0 = 0x8000006D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_DIA_CONFIG3_P3_1 = 0x8000046D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_DIA_CONFIG3_P3_1 = 0x8000046D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_DIA_CONFIG3_P3_2 = 0x8000086D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_DIA_CONFIG3_P3_2 = 0x8000086D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_DIA_CONFIG3_P3_3 = 0x80000C6D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_DIA_CONFIG3_P3_3 = 0x80000C6D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_DIA_CONFIG3_P3_4 = 0x8000106D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_DIA_CONFIG3_P3_4 = 0x8000106D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG4_P0_0 = 0x8000006E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_DIA_CONFIG4_P0_0 = 0x8000006E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_DIA_CONFIG4_P0_0 = 0x8000006E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG4_P0_1 = 0x8000046E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_DIA_CONFIG4_P0_1 = 0x8000046E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_DIA_CONFIG4_P0_1 = 0x8000046E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG4_P0_2 = 0x8000086E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_DIA_CONFIG4_P0_2 = 0x8000086E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_DIA_CONFIG4_P0_2 = 0x8000086E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG4_P0_3 = 0x80000C6E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_DIA_CONFIG4_P0_3 = 0x80000C6E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_DIA_CONFIG4_P0_3 = 0x80000C6E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG4_P0_4 = 0x8000106E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_DIA_CONFIG4_P0_4 = 0x8000106E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_DIA_CONFIG4_P0_4 = 0x8000106E0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_DIA_CONFIG4_P1_0 = 0x8000006E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_DIA_CONFIG4_P1_0 = 0x8000006E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_DIA_CONFIG4_P1_1 = 0x8000046E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_DIA_CONFIG4_P1_1 = 0x8000046E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_DIA_CONFIG4_P1_2 = 0x8000086E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_DIA_CONFIG4_P1_2 = 0x8000086E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_DIA_CONFIG4_P1_3 = 0x80000C6E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_DIA_CONFIG4_P1_3 = 0x80000C6E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_DIA_CONFIG4_P1_4 = 0x8000106E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_DIA_CONFIG4_P1_4 = 0x8000106E0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_DIA_CONFIG4_P2_0 = 0x8000006E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_DIA_CONFIG4_P2_0 = 0x8000006E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_DIA_CONFIG4_P2_1 = 0x8000046E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_DIA_CONFIG4_P2_1 = 0x8000046E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_DIA_CONFIG4_P2_2 = 0x8000086E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_DIA_CONFIG4_P2_2 = 0x8000086E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_DIA_CONFIG4_P2_3 = 0x80000C6E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_DIA_CONFIG4_P2_3 = 0x80000C6E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_DIA_CONFIG4_P2_4 = 0x8000106E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_DIA_CONFIG4_P2_4 = 0x8000106E0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_DIA_CONFIG4_P3_0 = 0x8000006E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_DIA_CONFIG4_P3_0 = 0x8000006E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_DIA_CONFIG4_P3_1 = 0x8000046E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_DIA_CONFIG4_P3_1 = 0x8000046E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_DIA_CONFIG4_P3_2 = 0x8000086E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_DIA_CONFIG4_P3_2 = 0x8000086E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_DIA_CONFIG4_P3_3 = 0x80000C6E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_DIA_CONFIG4_P3_3 = 0x80000C6E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_DIA_CONFIG4_P3_4 = 0x8000106E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_DIA_CONFIG4_P3_4 = 0x8000106E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_0 = 0x800000120701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_DIA_CONFIG5_P0_0 = 0x800000120701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_DIA_CONFIG5_P0_0 = 0x800000120801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_1 = 0x800004120701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_DIA_CONFIG5_P0_1 = 0x800004120701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_DIA_CONFIG5_P0_1 = 0x800004120801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_2 = 0x800008120701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_DIA_CONFIG5_P0_2 = 0x800008120701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_DIA_CONFIG5_P0_2 = 0x800008120801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_3 = 0x80000C120701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_DIA_CONFIG5_P0_3 = 0x80000C120701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_DIA_CONFIG5_P0_3 = 0x80000C120801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_4 = 0x800010120701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_DIA_CONFIG5_P0_4 = 0x800010120701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_DIA_CONFIG5_P0_4 = 0x800010120801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_DIA_CONFIG5_P1_0 = 0x800000120701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_DIA_CONFIG5_P1_0 = 0x800000120801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_DIA_CONFIG5_P1_1 = 0x800004120701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_DIA_CONFIG5_P1_1 = 0x800004120801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_DIA_CONFIG5_P1_2 = 0x800008120701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_DIA_CONFIG5_P1_2 = 0x800008120801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_DIA_CONFIG5_P1_3 = 0x80000C120701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_DIA_CONFIG5_P1_3 = 0x80000C120801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_DIA_CONFIG5_P1_4 = 0x800010120701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_DIA_CONFIG5_P1_4 = 0x800010120801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_DIA_CONFIG5_P2_0 = 0x800000120701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_DIA_CONFIG5_P2_0 = 0x800000120801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_DIA_CONFIG5_P2_1 = 0x800004120701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_DIA_CONFIG5_P2_1 = 0x800004120801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_DIA_CONFIG5_P2_2 = 0x800008120701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_DIA_CONFIG5_P2_2 = 0x800008120801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_DIA_CONFIG5_P2_3 = 0x80000C120701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_DIA_CONFIG5_P2_3 = 0x80000C120801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_DIA_CONFIG5_P2_4 = 0x800010120701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_DIA_CONFIG5_P2_4 = 0x800010120801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_DIA_CONFIG5_P3_0 = 0x8000001207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_DIA_CONFIG5_P3_0 = 0x8000001208011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_DIA_CONFIG5_P3_1 = 0x8000041207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_DIA_CONFIG5_P3_1 = 0x8000041208011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_DIA_CONFIG5_P3_2 = 0x8000081207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_DIA_CONFIG5_P3_2 = 0x8000081208011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_DIA_CONFIG5_P3_3 = 0x80000C1207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_DIA_CONFIG5_P3_3 = 0x80000C1208011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_DIA_CONFIG5_P3_4 = 0x8000101207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_DIA_CONFIG5_P3_4 = 0x8000101208011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_0 = 0x800000150701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_ERROR_MASK0_P0_0 = 0x800000150701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_ERROR_MASK0_P0_0 = 0x800000150801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_1 = 0x800004150701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_ERROR_MASK0_P0_1 = 0x800004150701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_ERROR_MASK0_P0_1 = 0x800004150801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_2 = 0x800008150701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_ERROR_MASK0_P0_2 = 0x800008150701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_ERROR_MASK0_P0_2 = 0x800008150801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_3 = 0x80000C150701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_ERROR_MASK0_P0_3 = 0x80000C150701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_ERROR_MASK0_P0_3 = 0x80000C150801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_4 = 0x800010150701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_ERROR_MASK0_P0_4 = 0x800010150701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_ERROR_MASK0_P0_4 = 0x800010150801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_ERROR_MASK0_P1_0 = 0x800000150701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_ERROR_MASK0_P1_0 = 0x800000150801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_ERROR_MASK0_P1_1 = 0x800004150701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_ERROR_MASK0_P1_1 = 0x800004150801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_ERROR_MASK0_P1_2 = 0x800008150701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_ERROR_MASK0_P1_2 = 0x800008150801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_ERROR_MASK0_P1_3 = 0x80000C150701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_ERROR_MASK0_P1_3 = 0x80000C150801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_ERROR_MASK0_P1_4 = 0x800010150701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_ERROR_MASK0_P1_4 = 0x800010150801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_ERROR_MASK0_P2_0 = 0x800000150701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_ERROR_MASK0_P2_0 = 0x800000150801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_ERROR_MASK0_P2_1 = 0x800004150701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_ERROR_MASK0_P2_1 = 0x800004150801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_ERROR_MASK0_P2_2 = 0x800008150701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_ERROR_MASK0_P2_2 = 0x800008150801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_ERROR_MASK0_P2_3 = 0x80000C150701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_ERROR_MASK0_P2_3 = 0x80000C150801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_ERROR_MASK0_P2_4 = 0x800010150701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_ERROR_MASK0_P2_4 = 0x800010150801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_ERROR_MASK0_P3_0 = 0x8000001507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_ERROR_MASK0_P3_0 = 0x8000001508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_ERROR_MASK0_P3_1 = 0x8000041507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_ERROR_MASK0_P3_1 = 0x8000041508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_ERROR_MASK0_P3_2 = 0x8000081507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_ERROR_MASK0_P3_2 = 0x8000081508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_ERROR_MASK0_P3_3 = 0x80000C1507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_ERROR_MASK0_P3_3 = 0x80000C1508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_ERROR_MASK0_P3_4 = 0x8000101507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_ERROR_MASK0_P3_4 = 0x8000101508011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_LVL_STATUS0_P0_0 = 0x8000000E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_LVL_STATUS0_P0_0 = 0x8000000E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_LVL_STATUS0_P0_0 = 0x8000000E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_LVL_STATUS0_P0_1 = 0x8000040E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_LVL_STATUS0_P0_1 = 0x8000040E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_LVL_STATUS0_P0_1 = 0x8000040E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_LVL_STATUS0_P0_2 = 0x8000080E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_LVL_STATUS0_P0_2 = 0x8000080E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_LVL_STATUS0_P0_2 = 0x8000080E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_LVL_STATUS0_P0_3 = 0x80000C0E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_LVL_STATUS0_P0_3 = 0x80000C0E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_LVL_STATUS0_P0_3 = 0x80000C0E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_LVL_STATUS0_P0_4 = 0x8000100E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_LVL_STATUS0_P0_4 = 0x8000100E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_LVL_STATUS0_P0_4 = 0x8000100E0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_LVL_STATUS0_P1_0 = 0x8000000E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_LVL_STATUS0_P1_0 = 0x8000000E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_LVL_STATUS0_P1_1 = 0x8000040E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_LVL_STATUS0_P1_1 = 0x8000040E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_LVL_STATUS0_P1_2 = 0x8000080E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_LVL_STATUS0_P1_2 = 0x8000080E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_LVL_STATUS0_P1_3 = 0x80000C0E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_LVL_STATUS0_P1_3 = 0x80000C0E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_LVL_STATUS0_P1_4 = 0x8000100E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_LVL_STATUS0_P1_4 = 0x8000100E0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_LVL_STATUS0_P2_0 = 0x8000000E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_LVL_STATUS0_P2_0 = 0x8000000E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_LVL_STATUS0_P2_1 = 0x8000040E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_LVL_STATUS0_P2_1 = 0x8000040E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_LVL_STATUS0_P2_2 = 0x8000080E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_LVL_STATUS0_P2_2 = 0x8000080E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_LVL_STATUS0_P2_3 = 0x80000C0E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_LVL_STATUS0_P2_3 = 0x80000C0E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_LVL_STATUS0_P2_4 = 0x8000100E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_LVL_STATUS0_P2_4 = 0x8000100E0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_LVL_STATUS0_P3_0 = 0x8000000E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_LVL_STATUS0_P3_0 = 0x8000000E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_LVL_STATUS0_P3_1 = 0x8000040E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_LVL_STATUS0_P3_1 = 0x8000040E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_LVL_STATUS0_P3_2 = 0x8000080E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_LVL_STATUS0_P3_2 = 0x8000080E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_LVL_STATUS0_P3_3 = 0x80000C0E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_LVL_STATUS0_P3_3 = 0x80000C0E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_LVL_STATUS0_P3_4 = 0x8000100E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_LVL_STATUS0_P3_4 = 0x8000100E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_LVL_STATUS2_P0_0 = 0x800000100701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_LVL_STATUS2_P0_0 = 0x800000100701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_LVL_STATUS2_P0_0 = 0x800000100801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_LVL_STATUS2_P0_1 = 0x800004100701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_LVL_STATUS2_P0_1 = 0x800004100701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_LVL_STATUS2_P0_1 = 0x800004100801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_LVL_STATUS2_P0_2 = 0x800008100701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_LVL_STATUS2_P0_2 = 0x800008100701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_LVL_STATUS2_P0_2 = 0x800008100801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_LVL_STATUS2_P0_3 = 0x80000C100701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_LVL_STATUS2_P0_3 = 0x80000C100701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_LVL_STATUS2_P0_3 = 0x80000C100801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_LVL_STATUS2_P0_4 = 0x800010100701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_LVL_STATUS2_P0_4 = 0x800010100701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_LVL_STATUS2_P0_4 = 0x800010100801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_LVL_STATUS2_P1_0 = 0x800000100701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_LVL_STATUS2_P1_0 = 0x800000100801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_LVL_STATUS2_P1_1 = 0x800004100701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_LVL_STATUS2_P1_1 = 0x800004100801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_LVL_STATUS2_P1_2 = 0x800008100701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_LVL_STATUS2_P1_2 = 0x800008100801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_LVL_STATUS2_P1_3 = 0x80000C100701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_LVL_STATUS2_P1_3 = 0x80000C100801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_LVL_STATUS2_P1_4 = 0x800010100701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_LVL_STATUS2_P1_4 = 0x800010100801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_LVL_STATUS2_P2_0 = 0x800000100701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_LVL_STATUS2_P2_0 = 0x800000100801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_LVL_STATUS2_P2_1 = 0x800004100701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_LVL_STATUS2_P2_1 = 0x800004100801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_LVL_STATUS2_P2_2 = 0x800008100701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_LVL_STATUS2_P2_2 = 0x800008100801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_LVL_STATUS2_P2_3 = 0x80000C100701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_LVL_STATUS2_P2_3 = 0x80000C100801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_LVL_STATUS2_P2_4 = 0x800010100701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_LVL_STATUS2_P2_4 = 0x800010100801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_LVL_STATUS2_P3_0 = 0x8000001007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_LVL_STATUS2_P3_0 = 0x8000001008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_LVL_STATUS2_P3_1 = 0x8000041007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_LVL_STATUS2_P3_1 = 0x8000041008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_LVL_STATUS2_P3_2 = 0x8000081007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_LVL_STATUS2_P3_2 = 0x8000081008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_LVL_STATUS2_P3_3 = 0x80000C1007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_LVL_STATUS2_P3_3 = 0x80000C1008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_LVL_STATUS2_P3_4 = 0x8000101007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_LVL_STATUS2_P3_4 = 0x8000101008011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_0 = 0x800000140701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_STATUS0_P0_0 = 0x800000140701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_STATUS0_P0_0 = 0x800000140801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_1 = 0x800004140701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_STATUS0_P0_1 = 0x800004140701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_STATUS0_P0_1 = 0x800004140801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_2 = 0x800008140701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_STATUS0_P0_2 = 0x800008140701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_STATUS0_P0_2 = 0x800008140801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_3 = 0x80000C140701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_STATUS0_P0_3 = 0x80000C140701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_STATUS0_P0_3 = 0x80000C140801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_4 = 0x800010140701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_STATUS0_P0_4 = 0x800010140701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_STATUS0_P0_4 = 0x800010140801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_STATUS0_P1_0 = 0x800000140701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_STATUS0_P1_0 = 0x800000140801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_STATUS0_P1_1 = 0x800004140701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_STATUS0_P1_1 = 0x800004140801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_STATUS0_P1_2 = 0x800008140701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_STATUS0_P1_2 = 0x800008140801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_STATUS0_P1_3 = 0x80000C140701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_STATUS0_P1_3 = 0x80000C140801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_STATUS0_P1_4 = 0x800010140701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_STATUS0_P1_4 = 0x800010140801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_STATUS0_P2_0 = 0x800000140701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_STATUS0_P2_0 = 0x800000140801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_STATUS0_P2_1 = 0x800004140701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_STATUS0_P2_1 = 0x800004140801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_STATUS0_P2_2 = 0x800008140701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_STATUS0_P2_2 = 0x800008140801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_STATUS0_P2_3 = 0x80000C140701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_STATUS0_P2_3 = 0x80000C140801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_STATUS0_P2_4 = 0x800010140701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_STATUS0_P2_4 = 0x800010140801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_STATUS0_P3_0 = 0x8000001407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_STATUS0_P3_0 = 0x8000001408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_STATUS0_P3_1 = 0x8000041407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_STATUS0_P3_1 = 0x8000041408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_STATUS0_P3_2 = 0x8000081407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_STATUS0_P3_2 = 0x8000081408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_STATUS0_P3_3 = 0x80000C1407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_STATUS0_P3_3 = 0x80000C1408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_STATUS0_P3_4 = 0x8000101407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_STATUS0_P3_4 = 0x8000101408011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_VREF_CAL_EN_P0_0 = 0x800000760701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_VREF_CAL_EN_P0_0 = 0x800000760701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_VREF_CAL_EN_P0_0 = 0x800000760801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_VREF_CAL_EN_P0_1 = 0x800004760701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_VREF_CAL_EN_P0_1 = 0x800004760701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_VREF_CAL_EN_P0_1 = 0x800004760801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_VREF_CAL_EN_P0_2 = 0x800008760701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_VREF_CAL_EN_P0_2 = 0x800008760701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_VREF_CAL_EN_P0_2 = 0x800008760801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_VREF_CAL_EN_P0_3 = 0x80000C760701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_VREF_CAL_EN_P0_3 = 0x80000C760701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_VREF_CAL_EN_P0_3 = 0x80000C760801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_VREF_CAL_EN_P0_4 = 0x800010760701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_VREF_CAL_EN_P0_4 = 0x800010760701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_VREF_CAL_EN_P0_4 = 0x800010760801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_VREF_CAL_EN_P1_0 = 0x800000760701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_VREF_CAL_EN_P1_0 = 0x800000760801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_VREF_CAL_EN_P1_1 = 0x800004760701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_VREF_CAL_EN_P1_1 = 0x800004760801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_VREF_CAL_EN_P1_2 = 0x800008760701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_VREF_CAL_EN_P1_2 = 0x800008760801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_VREF_CAL_EN_P1_3 = 0x80000C760701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_VREF_CAL_EN_P1_3 = 0x80000C760801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_VREF_CAL_EN_P1_4 = 0x800010760701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_VREF_CAL_EN_P1_4 = 0x800010760801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_VREF_CAL_EN_P2_0 = 0x800000760701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_VREF_CAL_EN_P2_0 = 0x800000760801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_VREF_CAL_EN_P2_1 = 0x800004760701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_VREF_CAL_EN_P2_1 = 0x800004760801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_VREF_CAL_EN_P2_2 = 0x800008760701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_VREF_CAL_EN_P2_2 = 0x800008760801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_VREF_CAL_EN_P2_3 = 0x80000C760701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_VREF_CAL_EN_P2_3 = 0x80000C760801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_VREF_CAL_EN_P2_4 = 0x800010760701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_VREF_CAL_EN_P2_4 = 0x800010760801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_VREF_CAL_EN_P3_0 = 0x8000007607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_VREF_CAL_EN_P3_0 = 0x8000007608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_VREF_CAL_EN_P3_1 = 0x8000047607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_VREF_CAL_EN_P3_1 = 0x8000047608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_VREF_CAL_EN_P3_2 = 0x8000087607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_VREF_CAL_EN_P3_2 = 0x8000087608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_VREF_CAL_EN_P3_3 = 0x80000C7607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_VREF_CAL_EN_P3_3 = 0x80000C7608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_VREF_CAL_EN_P3_4 = 0x8000107607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_VREF_CAL_EN_P3_4 = 0x8000107608011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_0 = 0x8000007A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_0 = 0x8000007A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_0 = 0x8000007A0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_1 = 0x8000047A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_1 = 0x8000047A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_1 = 0x8000047A0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_2 = 0x8000087A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_2 = 0x8000087A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_2 = 0x8000087A0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_3 = 0x80000C7A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_3 = 0x80000C7A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_3 = 0x80000C7A0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_4 = 0x8000107A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_4 = 0x8000107A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_4 = 0x8000107A0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_VREF_CAL_ERROR_P1_0 = 0x8000007A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_VREF_CAL_ERROR_P1_0 = 0x8000007A0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_VREF_CAL_ERROR_P1_1 = 0x8000047A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_VREF_CAL_ERROR_P1_1 = 0x8000047A0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_VREF_CAL_ERROR_P1_2 = 0x8000087A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_VREF_CAL_ERROR_P1_2 = 0x8000087A0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_VREF_CAL_ERROR_P1_3 = 0x80000C7A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_VREF_CAL_ERROR_P1_3 = 0x80000C7A0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_VREF_CAL_ERROR_P1_4 = 0x8000107A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_VREF_CAL_ERROR_P1_4 = 0x8000107A0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_VREF_CAL_ERROR_P2_0 = 0x8000007A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_VREF_CAL_ERROR_P2_0 = 0x8000007A0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_VREF_CAL_ERROR_P2_1 = 0x8000047A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_VREF_CAL_ERROR_P2_1 = 0x8000047A0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_VREF_CAL_ERROR_P2_2 = 0x8000087A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_VREF_CAL_ERROR_P2_2 = 0x8000087A0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_VREF_CAL_ERROR_P2_3 = 0x80000C7A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_VREF_CAL_ERROR_P2_3 = 0x80000C7A0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_VREF_CAL_ERROR_P2_4 = 0x8000107A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_VREF_CAL_ERROR_P2_4 = 0x8000107A0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_VREF_CAL_ERROR_P3_0 = 0x8000007A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_VREF_CAL_ERROR_P3_0 = 0x8000007A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_VREF_CAL_ERROR_P3_1 = 0x8000047A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_VREF_CAL_ERROR_P3_1 = 0x8000047A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_VREF_CAL_ERROR_P3_2 = 0x8000087A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_VREF_CAL_ERROR_P3_2 = 0x8000087A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_VREF_CAL_ERROR_P3_3 = 0x80000C7A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_VREF_CAL_ERROR_P3_3 = 0x80000C7A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_VREF_CAL_ERROR_P3_4 = 0x8000107A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_VREF_CAL_ERROR_P3_4 = 0x8000107A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_0_P0_0 = 0x800000160701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_VREF_DAC_0_P0_0 = 0x800000160701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_VREF_DAC_0_P0_0 = 0x800000160801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_0_P0_1 = 0x800004160701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_VREF_DAC_0_P0_1 = 0x800004160701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_VREF_DAC_0_P0_1 = 0x800004160801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_0_P0_2 = 0x800008160701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_VREF_DAC_0_P0_2 = 0x800008160701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_VREF_DAC_0_P0_2 = 0x800008160801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_0_P0_3 = 0x80000C160701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_VREF_DAC_0_P0_3 = 0x80000C160701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_VREF_DAC_0_P0_3 = 0x80000C160801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_0_P0_4 = 0x800010160701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_VREF_DAC_0_P0_4 = 0x800010160701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_VREF_DAC_0_P0_4 = 0x800010160801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_VREF_DAC_0_P1_0 = 0x800000160701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_VREF_DAC_0_P1_0 = 0x800000160801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_VREF_DAC_0_P1_1 = 0x800004160701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_VREF_DAC_0_P1_1 = 0x800004160801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_VREF_DAC_0_P1_2 = 0x800008160701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_VREF_DAC_0_P1_2 = 0x800008160801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_VREF_DAC_0_P1_3 = 0x80000C160701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_VREF_DAC_0_P1_3 = 0x80000C160801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_VREF_DAC_0_P1_4 = 0x800010160701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_VREF_DAC_0_P1_4 = 0x800010160801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_VREF_DAC_0_P2_0 = 0x800000160701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_VREF_DAC_0_P2_0 = 0x800000160801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_VREF_DAC_0_P2_1 = 0x800004160701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_VREF_DAC_0_P2_1 = 0x800004160801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_VREF_DAC_0_P2_2 = 0x800008160701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_VREF_DAC_0_P2_2 = 0x800008160801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_VREF_DAC_0_P2_3 = 0x80000C160701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_VREF_DAC_0_P2_3 = 0x80000C160801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_VREF_DAC_0_P2_4 = 0x800010160701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_VREF_DAC_0_P2_4 = 0x800010160801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_VREF_DAC_0_P3_0 = 0x8000001607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_VREF_DAC_0_P3_0 = 0x8000001608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_VREF_DAC_0_P3_1 = 0x8000041607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_VREF_DAC_0_P3_1 = 0x8000041608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_VREF_DAC_0_P3_2 = 0x8000081607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_VREF_DAC_0_P3_2 = 0x8000081608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_VREF_DAC_0_P3_3 = 0x80000C1607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_VREF_DAC_0_P3_3 = 0x80000C1608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_VREF_DAC_0_P3_4 = 0x8000101607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_VREF_DAC_0_P3_4 = 0x8000101608011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_1_P0_0 = 0x8000001F0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_VREF_DAC_1_P0_0 = 0x8000001F0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_VREF_DAC_1_P0_0 = 0x8000001F0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_1_P0_1 = 0x8000041F0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_VREF_DAC_1_P0_1 = 0x8000041F0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_VREF_DAC_1_P0_1 = 0x8000041F0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_1_P0_2 = 0x8000081F0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_VREF_DAC_1_P0_2 = 0x8000081F0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_VREF_DAC_1_P0_2 = 0x8000081F0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_1_P0_3 = 0x80000C1F0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_VREF_DAC_1_P0_3 = 0x80000C1F0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_VREF_DAC_1_P0_3 = 0x80000C1F0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_1_P0_4 = 0x8000101F0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_VREF_DAC_1_P0_4 = 0x8000101F0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_VREF_DAC_1_P0_4 = 0x8000101F0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_VREF_DAC_1_P1_0 = 0x8000001F0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_VREF_DAC_1_P1_0 = 0x8000001F0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_VREF_DAC_1_P1_1 = 0x8000041F0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_VREF_DAC_1_P1_1 = 0x8000041F0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_VREF_DAC_1_P1_2 = 0x8000081F0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_VREF_DAC_1_P1_2 = 0x8000081F0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_VREF_DAC_1_P1_3 = 0x80000C1F0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_VREF_DAC_1_P1_3 = 0x80000C1F0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_VREF_DAC_1_P1_4 = 0x8000101F0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_VREF_DAC_1_P1_4 = 0x8000101F0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_VREF_DAC_1_P2_0 = 0x8000001F0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_VREF_DAC_1_P2_0 = 0x8000001F0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_VREF_DAC_1_P2_1 = 0x8000041F0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_VREF_DAC_1_P2_1 = 0x8000041F0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_VREF_DAC_1_P2_2 = 0x8000081F0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_VREF_DAC_1_P2_2 = 0x8000081F0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_VREF_DAC_1_P2_3 = 0x80000C1F0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_VREF_DAC_1_P2_3 = 0x80000C1F0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_VREF_DAC_1_P2_4 = 0x8000101F0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_VREF_DAC_1_P2_4 = 0x8000101F0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_VREF_DAC_1_P3_0 = 0x8000001F07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_VREF_DAC_1_P3_0 = 0x8000001F08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_VREF_DAC_1_P3_1 = 0x8000041F07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_VREF_DAC_1_P3_1 = 0x8000041F08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_VREF_DAC_1_P3_2 = 0x8000081F07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_VREF_DAC_1_P3_2 = 0x8000081F08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_VREF_DAC_1_P3_3 = 0x80000C1F07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_VREF_DAC_1_P3_3 = 0x80000C1F08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_VREF_DAC_1_P3_4 = 0x8000101F07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_VREF_DAC_1_P3_4 = 0x8000101F08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_2_P0_0 = 0x800000C00701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_VREF_DAC_2_P0_0 = 0x800000C00701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_VREF_DAC_2_P0_0 = 0x800000C00801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_2_P0_1 = 0x800004C00701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_VREF_DAC_2_P0_1 = 0x800004C00701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_VREF_DAC_2_P0_1 = 0x800004C00801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_2_P0_2 = 0x800008C00701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_VREF_DAC_2_P0_2 = 0x800008C00701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_VREF_DAC_2_P0_2 = 0x800008C00801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_2_P0_3 = 0x80000CC00701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_VREF_DAC_2_P0_3 = 0x80000CC00701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_VREF_DAC_2_P0_3 = 0x80000CC00801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_2_P0_4 = 0x800010C00701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_VREF_DAC_2_P0_4 = 0x800010C00701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_VREF_DAC_2_P0_4 = 0x800010C00801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_VREF_DAC_2_P1_0 = 0x800000C00701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_VREF_DAC_2_P1_0 = 0x800000C00801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_VREF_DAC_2_P1_1 = 0x800004C00701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_VREF_DAC_2_P1_1 = 0x800004C00801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_VREF_DAC_2_P1_2 = 0x800008C00701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_VREF_DAC_2_P1_2 = 0x800008C00801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_VREF_DAC_2_P1_3 = 0x80000CC00701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_VREF_DAC_2_P1_3 = 0x80000CC00801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_VREF_DAC_2_P1_4 = 0x800010C00701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_VREF_DAC_2_P1_4 = 0x800010C00801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_VREF_DAC_2_P2_0 = 0x800000C00701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_VREF_DAC_2_P2_0 = 0x800000C00801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_VREF_DAC_2_P2_1 = 0x800004C00701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_VREF_DAC_2_P2_1 = 0x800004C00801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_VREF_DAC_2_P2_2 = 0x800008C00701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_VREF_DAC_2_P2_2 = 0x800008C00801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_VREF_DAC_2_P2_3 = 0x80000CC00701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_VREF_DAC_2_P2_3 = 0x80000CC00801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_VREF_DAC_2_P2_4 = 0x800010C00701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_VREF_DAC_2_P2_4 = 0x800010C00801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_VREF_DAC_2_P3_0 = 0x800000C007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_VREF_DAC_2_P3_0 = 0x800000C008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_VREF_DAC_2_P3_1 = 0x800004C007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_VREF_DAC_2_P3_1 = 0x800004C008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_VREF_DAC_2_P3_2 = 0x800008C007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_VREF_DAC_2_P3_2 = 0x800008C008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_VREF_DAC_2_P3_3 = 0x80000CC007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_VREF_DAC_2_P3_3 = 0x80000CC008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_VREF_DAC_2_P3_4 = 0x800010C007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_VREF_DAC_2_P3_4 = 0x800010C008011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_3_P0_0 = 0x800000C10701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_VREF_DAC_3_P0_0 = 0x800000C10701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_VREF_DAC_3_P0_0 = 0x800000C10801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_3_P0_1 = 0x800004C10701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_VREF_DAC_3_P0_1 = 0x800004C10701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_VREF_DAC_3_P0_1 = 0x800004C10801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_3_P0_2 = 0x800008C10701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_VREF_DAC_3_P0_2 = 0x800008C10701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_VREF_DAC_3_P0_2 = 0x800008C10801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_3_P0_3 = 0x80000CC10701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_VREF_DAC_3_P0_3 = 0x80000CC10701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_VREF_DAC_3_P0_3 = 0x80000CC10801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_3_P0_4 = 0x800010C10701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_VREF_DAC_3_P0_4 = 0x800010C10701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_VREF_DAC_3_P0_4 = 0x800010C10801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_VREF_DAC_3_P1_0 = 0x800000C10701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_VREF_DAC_3_P1_0 = 0x800000C10801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_VREF_DAC_3_P1_1 = 0x800004C10701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_VREF_DAC_3_P1_1 = 0x800004C10801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_VREF_DAC_3_P1_2 = 0x800008C10701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_VREF_DAC_3_P1_2 = 0x800008C10801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_VREF_DAC_3_P1_3 = 0x80000CC10701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_VREF_DAC_3_P1_3 = 0x80000CC10801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_VREF_DAC_3_P1_4 = 0x800010C10701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_VREF_DAC_3_P1_4 = 0x800010C10801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_VREF_DAC_3_P2_0 = 0x800000C10701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_VREF_DAC_3_P2_0 = 0x800000C10801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_VREF_DAC_3_P2_1 = 0x800004C10701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_VREF_DAC_3_P2_1 = 0x800004C10801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_VREF_DAC_3_P2_2 = 0x800008C10701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_VREF_DAC_3_P2_2 = 0x800008C10801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_VREF_DAC_3_P2_3 = 0x80000CC10701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_VREF_DAC_3_P2_3 = 0x80000CC10801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_VREF_DAC_3_P2_4 = 0x800010C10701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_VREF_DAC_3_P2_4 = 0x800010C10801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_VREF_DAC_3_P3_0 = 0x800000C107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_VREF_DAC_3_P3_0 = 0x800000C108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_VREF_DAC_3_P3_1 = 0x800004C107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_VREF_DAC_3_P3_1 = 0x800004C108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_VREF_DAC_3_P3_2 = 0x800008C107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_VREF_DAC_3_P3_2 = 0x800008C108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_VREF_DAC_3_P3_3 = 0x80000CC107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_VREF_DAC_3_P3_3 = 0x80000CC108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_VREF_DAC_3_P3_4 = 0x800010C107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_VREF_DAC_3_P3_4 = 0x800010C108011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_4_P0_0 = 0x800000C20701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_VREF_DAC_4_P0_0 = 0x800000C20701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_VREF_DAC_4_P0_0 = 0x800000C20801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_4_P0_1 = 0x800004C20701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_VREF_DAC_4_P0_1 = 0x800004C20701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_VREF_DAC_4_P0_1 = 0x800004C20801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_4_P0_2 = 0x800008C20701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_VREF_DAC_4_P0_2 = 0x800008C20701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_VREF_DAC_4_P0_2 = 0x800008C20801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_4_P0_3 = 0x80000CC20701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_VREF_DAC_4_P0_3 = 0x80000CC20701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_VREF_DAC_4_P0_3 = 0x80000CC20801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_4_P0_4 = 0x800010C20701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_VREF_DAC_4_P0_4 = 0x800010C20701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_VREF_DAC_4_P0_4 = 0x800010C20801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_VREF_DAC_4_P1_0 = 0x800000C20701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_VREF_DAC_4_P1_0 = 0x800000C20801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_VREF_DAC_4_P1_1 = 0x800004C20701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_VREF_DAC_4_P1_1 = 0x800004C20801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_VREF_DAC_4_P1_2 = 0x800008C20701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_VREF_DAC_4_P1_2 = 0x800008C20801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_VREF_DAC_4_P1_3 = 0x80000CC20701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_VREF_DAC_4_P1_3 = 0x80000CC20801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_VREF_DAC_4_P1_4 = 0x800010C20701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_VREF_DAC_4_P1_4 = 0x800010C20801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_VREF_DAC_4_P2_0 = 0x800000C20701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_VREF_DAC_4_P2_0 = 0x800000C20801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_VREF_DAC_4_P2_1 = 0x800004C20701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_VREF_DAC_4_P2_1 = 0x800004C20801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_VREF_DAC_4_P2_2 = 0x800008C20701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_VREF_DAC_4_P2_2 = 0x800008C20801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_VREF_DAC_4_P2_3 = 0x80000CC20701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_VREF_DAC_4_P2_3 = 0x80000CC20801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_VREF_DAC_4_P2_4 = 0x800010C20701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_VREF_DAC_4_P2_4 = 0x800010C20801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_VREF_DAC_4_P3_0 = 0x800000C207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_VREF_DAC_4_P3_0 = 0x800000C208011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_VREF_DAC_4_P3_1 = 0x800004C207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_VREF_DAC_4_P3_1 = 0x800004C208011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_VREF_DAC_4_P3_2 = 0x800008C207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_VREF_DAC_4_P3_2 = 0x800008C208011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_VREF_DAC_4_P3_3 = 0x80000CC207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_VREF_DAC_4_P3_3 = 0x80000CC208011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_VREF_DAC_4_P3_4 = 0x800010C207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_VREF_DAC_4_P3_4 = 0x800010C208011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_5_P0_0 = 0x800000C30701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_VREF_DAC_5_P0_0 = 0x800000C30701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_VREF_DAC_5_P0_0 = 0x800000C30801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_5_P0_1 = 0x800004C30701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_VREF_DAC_5_P0_1 = 0x800004C30701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_VREF_DAC_5_P0_1 = 0x800004C30801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_5_P0_2 = 0x800008C30701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_VREF_DAC_5_P0_2 = 0x800008C30701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_VREF_DAC_5_P0_2 = 0x800008C30801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_5_P0_3 = 0x80000CC30701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_VREF_DAC_5_P0_3 = 0x80000CC30701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_VREF_DAC_5_P0_3 = 0x80000CC30801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_5_P0_4 = 0x800010C30701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_VREF_DAC_5_P0_4 = 0x800010C30701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_VREF_DAC_5_P0_4 = 0x800010C30801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_VREF_DAC_5_P1_0 = 0x800000C30701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_VREF_DAC_5_P1_0 = 0x800000C30801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_VREF_DAC_5_P1_1 = 0x800004C30701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_VREF_DAC_5_P1_1 = 0x800004C30801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_VREF_DAC_5_P1_2 = 0x800008C30701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_VREF_DAC_5_P1_2 = 0x800008C30801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_VREF_DAC_5_P1_3 = 0x80000CC30701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_VREF_DAC_5_P1_3 = 0x80000CC30801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_VREF_DAC_5_P1_4 = 0x800010C30701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_VREF_DAC_5_P1_4 = 0x800010C30801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_VREF_DAC_5_P2_0 = 0x800000C30701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_VREF_DAC_5_P2_0 = 0x800000C30801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_VREF_DAC_5_P2_1 = 0x800004C30701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_VREF_DAC_5_P2_1 = 0x800004C30801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_VREF_DAC_5_P2_2 = 0x800008C30701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_VREF_DAC_5_P2_2 = 0x800008C30801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_VREF_DAC_5_P2_3 = 0x80000CC30701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_VREF_DAC_5_P2_3 = 0x80000CC30801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_VREF_DAC_5_P2_4 = 0x800010C30701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_VREF_DAC_5_P2_4 = 0x800010C30801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_VREF_DAC_5_P3_0 = 0x800000C307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_VREF_DAC_5_P3_0 = 0x800000C308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_VREF_DAC_5_P3_1 = 0x800004C307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_VREF_DAC_5_P3_1 = 0x800004C308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_VREF_DAC_5_P3_2 = 0x800008C307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_VREF_DAC_5_P3_2 = 0x800008C308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_VREF_DAC_5_P3_3 = 0x80000CC307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_VREF_DAC_5_P3_3 = 0x80000CC308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_VREF_DAC_5_P3_4 = 0x800010C307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_VREF_DAC_5_P3_4 = 0x800010C308011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_6_P0_0 = 0x800000C40701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_VREF_DAC_6_P0_0 = 0x800000C40701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_VREF_DAC_6_P0_0 = 0x800000C40801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_6_P0_1 = 0x800004C40701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_VREF_DAC_6_P0_1 = 0x800004C40701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_VREF_DAC_6_P0_1 = 0x800004C40801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_6_P0_2 = 0x800008C40701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_VREF_DAC_6_P0_2 = 0x800008C40701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_VREF_DAC_6_P0_2 = 0x800008C40801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_6_P0_3 = 0x80000CC40701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_VREF_DAC_6_P0_3 = 0x80000CC40701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_VREF_DAC_6_P0_3 = 0x80000CC40801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_6_P0_4 = 0x800010C40701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_VREF_DAC_6_P0_4 = 0x800010C40701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_VREF_DAC_6_P0_4 = 0x800010C40801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_VREF_DAC_6_P1_0 = 0x800000C40701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_VREF_DAC_6_P1_0 = 0x800000C40801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_VREF_DAC_6_P1_1 = 0x800004C40701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_VREF_DAC_6_P1_1 = 0x800004C40801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_VREF_DAC_6_P1_2 = 0x800008C40701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_VREF_DAC_6_P1_2 = 0x800008C40801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_VREF_DAC_6_P1_3 = 0x80000CC40701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_VREF_DAC_6_P1_3 = 0x80000CC40801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_VREF_DAC_6_P1_4 = 0x800010C40701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_VREF_DAC_6_P1_4 = 0x800010C40801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_VREF_DAC_6_P2_0 = 0x800000C40701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_VREF_DAC_6_P2_0 = 0x800000C40801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_VREF_DAC_6_P2_1 = 0x800004C40701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_VREF_DAC_6_P2_1 = 0x800004C40801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_VREF_DAC_6_P2_2 = 0x800008C40701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_VREF_DAC_6_P2_2 = 0x800008C40801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_VREF_DAC_6_P2_3 = 0x80000CC40701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_VREF_DAC_6_P2_3 = 0x80000CC40801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_VREF_DAC_6_P2_4 = 0x800010C40701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_VREF_DAC_6_P2_4 = 0x800010C40801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_VREF_DAC_6_P3_0 = 0x800000C407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_VREF_DAC_6_P3_0 = 0x800000C408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_VREF_DAC_6_P3_1 = 0x800004C407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_VREF_DAC_6_P3_1 = 0x800004C408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_VREF_DAC_6_P3_2 = 0x800008C407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_VREF_DAC_6_P3_2 = 0x800008C408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_VREF_DAC_6_P3_3 = 0x80000CC407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_VREF_DAC_6_P3_3 = 0x80000CC408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_VREF_DAC_6_P3_4 = 0x800010C407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_VREF_DAC_6_P3_4 = 0x800010C408011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_7_P0_0 = 0x800000C50701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_VREF_DAC_7_P0_0 = 0x800000C50701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_VREF_DAC_7_P0_0 = 0x800000C50801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_7_P0_1 = 0x800004C50701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_VREF_DAC_7_P0_1 = 0x800004C50701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_VREF_DAC_7_P0_1 = 0x800004C50801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_7_P0_2 = 0x800008C50701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_VREF_DAC_7_P0_2 = 0x800008C50701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_VREF_DAC_7_P0_2 = 0x800008C50801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_7_P0_3 = 0x80000CC50701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_VREF_DAC_7_P0_3 = 0x80000CC50701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_VREF_DAC_7_P0_3 = 0x80000CC50801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_7_P0_4 = 0x800010C50701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_VREF_DAC_7_P0_4 = 0x800010C50701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_VREF_DAC_7_P0_4 = 0x800010C50801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_VREF_DAC_7_P1_0 = 0x800000C50701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_VREF_DAC_7_P1_0 = 0x800000C50801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_VREF_DAC_7_P1_1 = 0x800004C50701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_VREF_DAC_7_P1_1 = 0x800004C50801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_VREF_DAC_7_P1_2 = 0x800008C50701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_VREF_DAC_7_P1_2 = 0x800008C50801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_VREF_DAC_7_P1_3 = 0x80000CC50701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_VREF_DAC_7_P1_3 = 0x80000CC50801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_VREF_DAC_7_P1_4 = 0x800010C50701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_VREF_DAC_7_P1_4 = 0x800010C50801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_VREF_DAC_7_P2_0 = 0x800000C50701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_VREF_DAC_7_P2_0 = 0x800000C50801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_VREF_DAC_7_P2_1 = 0x800004C50701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_VREF_DAC_7_P2_1 = 0x800004C50801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_VREF_DAC_7_P2_2 = 0x800008C50701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_VREF_DAC_7_P2_2 = 0x800008C50801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_VREF_DAC_7_P2_3 = 0x80000CC50701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_VREF_DAC_7_P2_3 = 0x80000CC50801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_VREF_DAC_7_P2_4 = 0x800010C50701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_VREF_DAC_7_P2_4 = 0x800010C50801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_VREF_DAC_7_P3_0 = 0x800000C507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_VREF_DAC_7_P3_0 = 0x800000C508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_VREF_DAC_7_P3_1 = 0x800004C507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_VREF_DAC_7_P3_1 = 0x800004C508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_VREF_DAC_7_P3_2 = 0x800008C507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_VREF_DAC_7_P3_2 = 0x800008C508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_VREF_DAC_7_P3_3 = 0x80000CC507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_VREF_DAC_7_P3_3 = 0x80000CC508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_VREF_DAC_7_P3_4 = 0x800010C507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_VREF_DAC_7_P3_4 = 0x800010C508011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P0_0 = 0x800000F60701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P0_0 = 0x800000F60701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P0_0 = 0x800000F60801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P0_1 = 0x800004F60701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P0_1 = 0x800004F60701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P0_1 = 0x800004F60801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P0_2 = 0x800008F60701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P0_2 = 0x800008F60701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P0_2 = 0x800008F60801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P0_3 = 0x80000CF60701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P0_3 = 0x80000CF60701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P0_3 = 0x80000CF60801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P0_4 = 0x800010F60701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P0_4 = 0x800010F60701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P0_4 = 0x800010F60801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P1_0 = 0x800000F60701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P1_0 = 0x800000F60801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P1_1 = 0x800004F60701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P1_1 = 0x800004F60801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P1_2 = 0x800008F60701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P1_2 = 0x800008F60801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P1_3 = 0x80000CF60701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P1_3 = 0x80000CF60801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P1_4 = 0x800010F60701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P1_4 = 0x800010F60801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P2_0 = 0x800000F60701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P2_0 = 0x800000F60801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P2_1 = 0x800004F60701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P2_1 = 0x800004F60801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P2_2 = 0x800008F60701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P2_2 = 0x800008F60801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P2_3 = 0x80000CF60701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P2_3 = 0x80000CF60801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P2_4 = 0x800010F60701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P2_4 = 0x800010F60801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P3_0 = 0x800000F607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P3_0 = 0x800000F608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P3_1 = 0x800004F607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P3_1 = 0x800004F608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P3_2 = 0x800008F607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P3_2 = 0x800008F608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P3_3 = 0x80000CF607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P3_3 = 0x80000CF608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P3_4 = 0x800010F607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P3_4 = 0x800010F608011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_0 = 0x800000040701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_0 = 0x800000040701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_0 = 0x800000040801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_1 = 0x800004040701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_1 = 0x800004040701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_1 = 0x800004040801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_2 = 0x800008040701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_2 = 0x800008040701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_2 = 0x800008040801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_3 = 0x80000C040701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_3 = 0x80000C040701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_3 = 0x80000C040801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_4 = 0x800010040701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_4 = 0x800010040701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_4 = 0x800010040801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P1_0 = 0x800000040701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P1_0 = 0x800000040801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P1_1 = 0x800004040701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P1_1 = 0x800004040801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P1_2 = 0x800008040701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P1_2 = 0x800008040801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P1_3 = 0x80000C040701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P1_3 = 0x80000C040801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P1_4 = 0x800010040701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P1_4 = 0x800010040801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P2_0 = 0x800000040701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P2_0 = 0x800000040801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P2_1 = 0x800004040701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P2_1 = 0x800004040801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P2_2 = 0x800008040701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P2_2 = 0x800008040801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P2_3 = 0x80000C040701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P2_3 = 0x80000C040801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P2_4 = 0x800010040701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P2_4 = 0x800010040801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P3_0 = 0x8000000407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P3_0 = 0x8000000408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P3_1 = 0x8000040407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P3_1 = 0x8000040408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P3_2 = 0x8000080407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P3_2 = 0x8000080408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P3_3 = 0x80000C0407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P3_3 = 0x80000C0408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P3_4 = 0x8000100407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P3_4 = 0x8000100408011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_0 = 0x800001040701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_0 = 0x800001040701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_0 = 0x800001040801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_1 = 0x800005040701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_1 = 0x800005040701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_1 = 0x800005040801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_2 = 0x800009040701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_2 = 0x800009040701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_2 = 0x800009040801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_3 = 0x80000D040701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_3 = 0x80000D040701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_3 = 0x80000D040801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_4 = 0x800011040701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_4 = 0x800011040701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_4 = 0x800011040801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P1_0 = 0x800001040701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P1_0 = 0x800001040801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P1_1 = 0x800005040701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P1_1 = 0x800005040801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P1_2 = 0x800009040701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P1_2 = 0x800009040801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P1_3 = 0x80000D040701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P1_3 = 0x80000D040801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P1_4 = 0x800011040701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P1_4 = 0x800011040801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P2_0 = 0x800001040701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P2_0 = 0x800001040801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P2_1 = 0x800005040701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P2_1 = 0x800005040801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P2_2 = 0x800009040701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P2_2 = 0x800009040801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P2_3 = 0x80000D040701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P2_3 = 0x80000D040801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P2_4 = 0x800011040701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P2_4 = 0x800011040801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P3_0 = 0x8000010407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P3_0 = 0x8000010408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P3_1 = 0x8000050407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P3_1 = 0x8000050408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P3_2 = 0x8000090407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P3_2 = 0x8000090408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P3_3 = 0x80000D0407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P3_3 = 0x80000D0408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P3_4 = 0x8000110407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P3_4 = 0x8000110408011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_0 = 0x800002040701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_0 = 0x800002040701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_0 = 0x800002040801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_1 = 0x800006040701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_1 = 0x800006040701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_1 = 0x800006040801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_2 = 0x80000A040701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_2 = 0x80000A040701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_2 = 0x80000A040801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_3 = 0x80000E040701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_3 = 0x80000E040701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_3 = 0x80000E040801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_4 = 0x800012040701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_4 = 0x800012040701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_4 = 0x800012040801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P1_0 = 0x800002040701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P1_0 = 0x800002040801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P1_1 = 0x800006040701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P1_1 = 0x800006040801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P1_2 = 0x80000A040701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P1_2 = 0x80000A040801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P1_3 = 0x80000E040701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P1_3 = 0x80000E040801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P1_4 = 0x800012040701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P1_4 = 0x800012040801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P2_0 = 0x800002040701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P2_0 = 0x800002040801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P2_1 = 0x800006040701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P2_1 = 0x800006040801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P2_2 = 0x80000A040701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P2_2 = 0x80000A040801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P2_3 = 0x80000E040701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P2_3 = 0x80000E040801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P2_4 = 0x800012040701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P2_4 = 0x800012040801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P3_0 = 0x8000020407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P3_0 = 0x8000020408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P3_1 = 0x8000060407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P3_1 = 0x8000060408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P3_2 = 0x80000A0407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P3_2 = 0x80000A0408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P3_3 = 0x80000E0407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P3_3 = 0x80000E0408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P3_4 = 0x8000120407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P3_4 = 0x8000120408011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_0 = 0x800003040701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_0 = 0x800003040701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_0 = 0x800003040801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_1 = 0x800007040701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_1 = 0x800007040701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_1 = 0x800007040801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_2 = 0x80000B040701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_2 = 0x80000B040701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_2 = 0x80000B040801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_3 = 0x80000F040701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_3 = 0x80000F040701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_3 = 0x80000F040801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_4 = 0x800013040701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_4 = 0x800013040701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_4 = 0x800013040801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P1_0 = 0x800003040701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P1_0 = 0x800003040801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P1_1 = 0x800007040701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P1_1 = 0x800007040801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P1_2 = 0x80000B040701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P1_2 = 0x80000B040801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P1_3 = 0x80000F040701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P1_3 = 0x80000F040801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P1_4 = 0x800013040701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P1_4 = 0x800013040801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P2_0 = 0x800003040701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P2_0 = 0x800003040801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P2_1 = 0x800007040701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P2_1 = 0x800007040801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P2_2 = 0x80000B040701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P2_2 = 0x80000B040801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P2_3 = 0x80000F040701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P2_3 = 0x80000F040801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P2_4 = 0x800013040701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P2_4 = 0x800013040801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P3_0 = 0x8000030407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P3_0 = 0x8000030408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P3_1 = 0x8000070407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P3_1 = 0x8000070408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P3_2 = 0x80000B0407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P3_2 = 0x80000B0408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P3_3 = 0x80000F0407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P3_3 = 0x80000F0408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P3_4 = 0x8000130407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P3_4 = 0x8000130408011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_0 = 0x800000500701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_0 = 0x800000500701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_0 = 0x800000500801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_1 = 0x800004500701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_1 = 0x800004500701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_1 = 0x800004500801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_2 = 0x800008500701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_2 = 0x800008500701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_2 = 0x800008500801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_3 = 0x80000C500701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_3 = 0x80000C500701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_3 = 0x80000C500801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_4 = 0x800010500701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_4 = 0x800010500701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_4 = 0x800010500801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P1_0 = 0x800000500701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P1_0 = 0x800000500801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P1_1 = 0x800004500701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P1_1 = 0x800004500801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P1_2 = 0x800008500701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P1_2 = 0x800008500801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P1_3 = 0x80000C500701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P1_3 = 0x80000C500801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P1_4 = 0x800010500701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P1_4 = 0x800010500801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P2_0 = 0x800000500701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P2_0 = 0x800000500801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P2_1 = 0x800004500701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P2_1 = 0x800004500801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P2_2 = 0x800008500701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P2_2 = 0x800008500801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P2_3 = 0x80000C500701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P2_3 = 0x80000C500801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P2_4 = 0x800010500701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P2_4 = 0x800010500801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P3_0 = 0x8000005007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P3_0 = 0x8000005008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P3_1 = 0x8000045007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P3_1 = 0x8000045008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P3_2 = 0x8000085007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P3_2 = 0x8000085008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P3_3 = 0x80000C5007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P3_3 = 0x80000C5008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P3_4 = 0x8000105007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P3_4 = 0x8000105008011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_0 = 0x800001500701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_0 = 0x800001500701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_0 = 0x800001500801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_1 = 0x800005500701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_1 = 0x800005500701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_1 = 0x800005500801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_2 = 0x800009500701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_2 = 0x800009500701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_2 = 0x800009500801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_3 = 0x80000D500701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_3 = 0x80000D500701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_3 = 0x80000D500801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_4 = 0x800011500701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_4 = 0x800011500701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_4 = 0x800011500801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P1_0 = 0x800001500701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P1_0 = 0x800001500801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P1_1 = 0x800005500701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P1_1 = 0x800005500801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P1_2 = 0x800009500701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P1_2 = 0x800009500801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P1_3 = 0x80000D500701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P1_3 = 0x80000D500801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P1_4 = 0x800011500701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P1_4 = 0x800011500801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P2_0 = 0x800001500701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P2_0 = 0x800001500801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P2_1 = 0x800005500701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P2_1 = 0x800005500801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P2_2 = 0x800009500701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P2_2 = 0x800009500801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P2_3 = 0x80000D500701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P2_3 = 0x80000D500801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P2_4 = 0x800011500701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P2_4 = 0x800011500801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P3_0 = 0x8000015007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P3_0 = 0x8000015008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P3_1 = 0x8000055007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P3_1 = 0x8000055008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P3_2 = 0x8000095007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P3_2 = 0x8000095008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P3_3 = 0x80000D5007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P3_3 = 0x80000D5008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P3_4 = 0x8000115007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P3_4 = 0x8000115008011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_0 = 0x800002500701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_0 = 0x800002500701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_0 = 0x800002500801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_1 = 0x800006500701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_1 = 0x800006500701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_1 = 0x800006500801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_2 = 0x80000A500701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_2 = 0x80000A500701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_2 = 0x80000A500801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_3 = 0x80000E500701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_3 = 0x80000E500701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_3 = 0x80000E500801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_4 = 0x800012500701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_4 = 0x800012500701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_4 = 0x800012500801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P1_0 = 0x800002500701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P1_0 = 0x800002500801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P1_1 = 0x800006500701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P1_1 = 0x800006500801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P1_2 = 0x80000A500701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P1_2 = 0x80000A500801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P1_3 = 0x80000E500701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P1_3 = 0x80000E500801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P1_4 = 0x800012500701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P1_4 = 0x800012500801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P2_0 = 0x800002500701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P2_0 = 0x800002500801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P2_1 = 0x800006500701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P2_1 = 0x800006500801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P2_2 = 0x80000A500701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P2_2 = 0x80000A500801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P2_3 = 0x80000E500701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P2_3 = 0x80000E500801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P2_4 = 0x800012500701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P2_4 = 0x800012500801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P3_0 = 0x8000025007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P3_0 = 0x8000025008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P3_1 = 0x8000065007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P3_1 = 0x8000065008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P3_2 = 0x80000A5007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P3_2 = 0x80000A5008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P3_3 = 0x80000E5007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P3_3 = 0x80000E5008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P3_4 = 0x8000125007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P3_4 = 0x8000125008011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_0 = 0x800003500701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_0 = 0x800003500701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_0 = 0x800003500801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_1 = 0x800007500701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_1 = 0x800007500701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_1 = 0x800007500801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_2 = 0x80000B500701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_2 = 0x80000B500701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_2 = 0x80000B500801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_3 = 0x80000F500701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_3 = 0x80000F500701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_3 = 0x80000F500801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_4 = 0x800013500701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_4 = 0x800013500701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_4 = 0x800013500801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P1_0 = 0x800003500701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P1_0 = 0x800003500801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P1_1 = 0x800007500701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P1_1 = 0x800007500801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P1_2 = 0x80000B500701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P1_2 = 0x80000B500801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P1_3 = 0x80000F500701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P1_3 = 0x80000F500801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P1_4 = 0x800013500701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P1_4 = 0x800013500801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P2_0 = 0x800003500701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P2_0 = 0x800003500801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P2_1 = 0x800007500701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P2_1 = 0x800007500801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P2_2 = 0x80000B500701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P2_2 = 0x80000B500801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P2_3 = 0x80000F500701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P2_3 = 0x80000F500801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P2_4 = 0x800013500701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P2_4 = 0x800013500801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P3_0 = 0x8000035007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P3_0 = 0x8000035008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P3_1 = 0x8000075007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P3_1 = 0x8000075008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P3_2 = 0x80000B5007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P3_2 = 0x80000B5008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P3_3 = 0x80000F5007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P3_3 = 0x80000F5008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P3_4 = 0x8000135007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P3_4 = 0x8000135008011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_0 = 0x800000510701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_0 = 0x800000510701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_0 = 0x800000510801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_1 = 0x800004510701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_1 = 0x800004510701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_1 = 0x800004510801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_2 = 0x800008510701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_2 = 0x800008510701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_2 = 0x800008510801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_3 = 0x80000C510701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_3 = 0x80000C510701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_3 = 0x80000C510801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_4 = 0x800010510701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_4 = 0x800010510701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_4 = 0x800010510801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P1_0 = 0x800000510701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P1_0 = 0x800000510801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P1_1 = 0x800004510701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P1_1 = 0x800004510801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P1_2 = 0x800008510701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P1_2 = 0x800008510801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P1_3 = 0x80000C510701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P1_3 = 0x80000C510801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P1_4 = 0x800010510701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P1_4 = 0x800010510801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P2_0 = 0x800000510701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P2_0 = 0x800000510801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P2_1 = 0x800004510701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P2_1 = 0x800004510801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P2_2 = 0x800008510701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P2_2 = 0x800008510801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P2_3 = 0x80000C510701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P2_3 = 0x80000C510801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P2_4 = 0x800010510701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P2_4 = 0x800010510801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P3_0 = 0x8000005107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P3_0 = 0x8000005108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P3_1 = 0x8000045107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P3_1 = 0x8000045108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P3_2 = 0x8000085107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P3_2 = 0x8000085108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P3_3 = 0x80000C5107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P3_3 = 0x80000C5108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P3_4 = 0x8000105107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P3_4 = 0x8000105108011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_0 = 0x800001510701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_0 = 0x800001510701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_0 = 0x800001510801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_1 = 0x800005510701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_1 = 0x800005510701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_1 = 0x800005510801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_2 = 0x800009510701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_2 = 0x800009510701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_2 = 0x800009510801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_3 = 0x80000D510701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_3 = 0x80000D510701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_3 = 0x80000D510801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_4 = 0x800011510701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_4 = 0x800011510701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_4 = 0x800011510801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P1_0 = 0x800001510701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P1_0 = 0x800001510801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P1_1 = 0x800005510701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P1_1 = 0x800005510801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P1_2 = 0x800009510701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P1_2 = 0x800009510801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P1_3 = 0x80000D510701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P1_3 = 0x80000D510801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P1_4 = 0x800011510701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P1_4 = 0x800011510801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P2_0 = 0x800001510701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P2_0 = 0x800001510801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P2_1 = 0x800005510701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P2_1 = 0x800005510801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P2_2 = 0x800009510701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P2_2 = 0x800009510801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P2_3 = 0x80000D510701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P2_3 = 0x80000D510801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P2_4 = 0x800011510701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P2_4 = 0x800011510801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P3_0 = 0x8000015107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P3_0 = 0x8000015108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P3_1 = 0x8000055107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P3_1 = 0x8000055108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P3_2 = 0x8000095107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P3_2 = 0x8000095108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P3_3 = 0x80000D5107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P3_3 = 0x80000D5108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P3_4 = 0x8000115107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P3_4 = 0x8000115108011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_0 = 0x800002510701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_0 = 0x800002510701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_0 = 0x800002510801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_1 = 0x800006510701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_1 = 0x800006510701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_1 = 0x800006510801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_2 = 0x80000A510701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_2 = 0x80000A510701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_2 = 0x80000A510801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_3 = 0x80000E510701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_3 = 0x80000E510701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_3 = 0x80000E510801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_4 = 0x800012510701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_4 = 0x800012510701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_4 = 0x800012510801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P1_0 = 0x800002510701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P1_0 = 0x800002510801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P1_1 = 0x800006510701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P1_1 = 0x800006510801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P1_2 = 0x80000A510701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P1_2 = 0x80000A510801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P1_3 = 0x80000E510701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P1_3 = 0x80000E510801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P1_4 = 0x800012510701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P1_4 = 0x800012510801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P2_0 = 0x800002510701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P2_0 = 0x800002510801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P2_1 = 0x800006510701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P2_1 = 0x800006510801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P2_2 = 0x80000A510701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P2_2 = 0x80000A510801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P2_3 = 0x80000E510701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P2_3 = 0x80000E510801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P2_4 = 0x800012510701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P2_4 = 0x800012510801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P3_0 = 0x8000025107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P3_0 = 0x8000025108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P3_1 = 0x8000065107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P3_1 = 0x8000065108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P3_2 = 0x80000A5107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P3_2 = 0x80000A5108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P3_3 = 0x80000E5107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P3_3 = 0x80000E5108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P3_4 = 0x8000125107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P3_4 = 0x8000125108011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_0 = 0x800003510701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_0 = 0x800003510701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_0 = 0x800003510801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_1 = 0x800007510701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_1 = 0x800007510701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_1 = 0x800007510801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_2 = 0x80000B510701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_2 = 0x80000B510701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_2 = 0x80000B510801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_3 = 0x80000F510701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_3 = 0x80000F510701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_3 = 0x80000F510801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_4 = 0x800013510701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_4 = 0x800013510701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_4 = 0x800013510801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P1_0 = 0x800003510701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P1_0 = 0x800003510801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P1_1 = 0x800007510701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P1_1 = 0x800007510801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P1_2 = 0x80000B510701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P1_2 = 0x80000B510801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P1_3 = 0x80000F510701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P1_3 = 0x80000F510801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P1_4 = 0x800013510701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P1_4 = 0x800013510801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P2_0 = 0x800003510701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P2_0 = 0x800003510801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P2_1 = 0x800007510701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P2_1 = 0x800007510801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P2_2 = 0x80000B510701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P2_2 = 0x80000B510801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P2_3 = 0x80000F510701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P2_3 = 0x80000F510801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P2_4 = 0x800013510701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P2_4 = 0x800013510801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P3_0 = 0x8000035107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P3_0 = 0x8000035108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P3_1 = 0x8000075107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P3_1 = 0x8000075108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P3_2 = 0x80000B5107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P3_2 = 0x80000B5108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P3_3 = 0x80000F5107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P3_3 = 0x80000F5108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P3_4 = 0x8000135107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P3_4 = 0x8000135108011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_0 = 0x800000520701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_0 = 0x800000520701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_0 = 0x800000520801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_1 = 0x800004520701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_1 = 0x800004520701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_1 = 0x800004520801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_2 = 0x800008520701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_2 = 0x800008520701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_2 = 0x800008520801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_3 = 0x80000C520701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_3 = 0x80000C520701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_3 = 0x80000C520801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_4 = 0x800010520701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_4 = 0x800010520701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_4 = 0x800010520801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P1_0 = 0x800000520701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P1_0 = 0x800000520801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P1_1 = 0x800004520701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P1_1 = 0x800004520801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P1_2 = 0x800008520701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P1_2 = 0x800008520801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P1_3 = 0x80000C520701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P1_3 = 0x80000C520801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P1_4 = 0x800010520701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P1_4 = 0x800010520801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P2_0 = 0x800000520701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P2_0 = 0x800000520801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P2_1 = 0x800004520701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P2_1 = 0x800004520801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P2_2 = 0x800008520701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P2_2 = 0x800008520801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P2_3 = 0x80000C520701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P2_3 = 0x80000C520801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P2_4 = 0x800010520701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P2_4 = 0x800010520801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P3_0 = 0x8000005207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P3_0 = 0x8000005208011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P3_1 = 0x8000045207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P3_1 = 0x8000045208011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P3_2 = 0x8000085207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P3_2 = 0x8000085208011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P3_3 = 0x80000C5207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P3_3 = 0x80000C5208011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P3_4 = 0x8000105207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P3_4 = 0x8000105208011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_0 = 0x800001520701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_0 = 0x800001520701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_0 = 0x800001520801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_1 = 0x800005520701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_1 = 0x800005520701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_1 = 0x800005520801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_2 = 0x800009520701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_2 = 0x800009520701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_2 = 0x800009520801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_3 = 0x80000D520701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_3 = 0x80000D520701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_3 = 0x80000D520801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_4 = 0x800011520701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_4 = 0x800011520701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_4 = 0x800011520801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P1_0 = 0x800001520701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P1_0 = 0x800001520801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P1_1 = 0x800005520701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P1_1 = 0x800005520801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P1_2 = 0x800009520701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P1_2 = 0x800009520801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P1_3 = 0x80000D520701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P1_3 = 0x80000D520801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P1_4 = 0x800011520701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P1_4 = 0x800011520801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P2_0 = 0x800001520701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P2_0 = 0x800001520801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P2_1 = 0x800005520701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P2_1 = 0x800005520801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P2_2 = 0x800009520701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P2_2 = 0x800009520801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P2_3 = 0x80000D520701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P2_3 = 0x80000D520801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P2_4 = 0x800011520701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P2_4 = 0x800011520801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P3_0 = 0x8000015207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P3_0 = 0x8000015208011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P3_1 = 0x8000055207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P3_1 = 0x8000055208011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P3_2 = 0x8000095207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P3_2 = 0x8000095208011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P3_3 = 0x80000D5207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P3_3 = 0x80000D5208011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P3_4 = 0x8000115207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P3_4 = 0x8000115208011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_0 = 0x800002520701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_0 = 0x800002520701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_0 = 0x800002520801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_1 = 0x800006520701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_1 = 0x800006520701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_1 = 0x800006520801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_2 = 0x80000A520701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_2 = 0x80000A520701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_2 = 0x80000A520801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_3 = 0x80000E520701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_3 = 0x80000E520701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_3 = 0x80000E520801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_4 = 0x800012520701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_4 = 0x800012520701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_4 = 0x800012520801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P1_0 = 0x800002520701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P1_0 = 0x800002520801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P1_1 = 0x800006520701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P1_1 = 0x800006520801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P1_2 = 0x80000A520701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P1_2 = 0x80000A520801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P1_3 = 0x80000E520701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P1_3 = 0x80000E520801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P1_4 = 0x800012520701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P1_4 = 0x800012520801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P2_0 = 0x800002520701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P2_0 = 0x800002520801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P2_1 = 0x800006520701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P2_1 = 0x800006520801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P2_2 = 0x80000A520701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P2_2 = 0x80000A520801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P2_3 = 0x80000E520701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P2_3 = 0x80000E520801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P2_4 = 0x800012520701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P2_4 = 0x800012520801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P3_0 = 0x8000025207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P3_0 = 0x8000025208011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P3_1 = 0x8000065207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P3_1 = 0x8000065208011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P3_2 = 0x80000A5207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P3_2 = 0x80000A5208011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P3_3 = 0x80000E5207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P3_3 = 0x80000E5208011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P3_4 = 0x8000125207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P3_4 = 0x8000125208011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_0 = 0x800003520701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_0 = 0x800003520701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_0 = 0x800003520801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_1 = 0x800007520701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_1 = 0x800007520701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_1 = 0x800007520801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_2 = 0x80000B520701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_2 = 0x80000B520701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_2 = 0x80000B520801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_3 = 0x80000F520701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_3 = 0x80000F520701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_3 = 0x80000F520801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_4 = 0x800013520701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_4 = 0x800013520701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_4 = 0x800013520801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P1_0 = 0x800003520701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P1_0 = 0x800003520801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P1_1 = 0x800007520701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P1_1 = 0x800007520801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P1_2 = 0x80000B520701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P1_2 = 0x80000B520801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P1_3 = 0x80000F520701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P1_3 = 0x80000F520801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P1_4 = 0x800013520701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P1_4 = 0x800013520801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P2_0 = 0x800003520701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P2_0 = 0x800003520801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P2_1 = 0x800007520701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P2_1 = 0x800007520801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P2_2 = 0x80000B520701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P2_2 = 0x80000B520801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P2_3 = 0x80000F520701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P2_3 = 0x80000F520801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P2_4 = 0x800013520701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P2_4 = 0x800013520801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P3_0 = 0x8000035207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P3_0 = 0x8000035208011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P3_1 = 0x8000075207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P3_1 = 0x8000075208011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P3_2 = 0x80000B5207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P3_2 = 0x80000B5208011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P3_3 = 0x80000F5207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P3_3 = 0x80000F5208011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P3_4 = 0x8000135207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P3_4 = 0x8000135208011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_0 = 0x800000530701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_0 = 0x800000530701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_0 = 0x800000530801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_1 = 0x800004530701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_1 = 0x800004530701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_1 = 0x800004530801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_2 = 0x800008530701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_2 = 0x800008530701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_2 = 0x800008530801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_3 = 0x80000C530701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_3 = 0x80000C530701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_3 = 0x80000C530801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_4 = 0x800010530701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_4 = 0x800010530701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_4 = 0x800010530801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P1_0 = 0x800000530701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P1_0 = 0x800000530801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P1_1 = 0x800004530701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P1_1 = 0x800004530801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P1_2 = 0x800008530701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P1_2 = 0x800008530801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P1_3 = 0x80000C530701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P1_3 = 0x80000C530801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P1_4 = 0x800010530701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P1_4 = 0x800010530801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P2_0 = 0x800000530701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P2_0 = 0x800000530801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P2_1 = 0x800004530701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P2_1 = 0x800004530801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P2_2 = 0x800008530701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P2_2 = 0x800008530801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P2_3 = 0x80000C530701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P2_3 = 0x80000C530801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P2_4 = 0x800010530701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P2_4 = 0x800010530801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P3_0 = 0x8000005307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P3_0 = 0x8000005308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P3_1 = 0x8000045307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P3_1 = 0x8000045308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P3_2 = 0x8000085307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P3_2 = 0x8000085308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P3_3 = 0x80000C5307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P3_3 = 0x80000C5308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P3_4 = 0x8000105307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P3_4 = 0x8000105308011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_0 = 0x800001530701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_0 = 0x800001530701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_0 = 0x800001530801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_1 = 0x800005530701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_1 = 0x800005530701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_1 = 0x800005530801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_2 = 0x800009530701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_2 = 0x800009530701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_2 = 0x800009530801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_3 = 0x80000D530701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_3 = 0x80000D530701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_3 = 0x80000D530801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_4 = 0x800011530701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_4 = 0x800011530701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_4 = 0x800011530801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P1_0 = 0x800001530701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P1_0 = 0x800001530801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P1_1 = 0x800005530701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P1_1 = 0x800005530801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P1_2 = 0x800009530701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P1_2 = 0x800009530801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P1_3 = 0x80000D530701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P1_3 = 0x80000D530801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P1_4 = 0x800011530701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P1_4 = 0x800011530801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P2_0 = 0x800001530701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P2_0 = 0x800001530801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P2_1 = 0x800005530701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P2_1 = 0x800005530801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P2_2 = 0x800009530701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P2_2 = 0x800009530801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P2_3 = 0x80000D530701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P2_3 = 0x80000D530801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P2_4 = 0x800011530701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P2_4 = 0x800011530801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P3_0 = 0x8000015307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P3_0 = 0x8000015308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P3_1 = 0x8000055307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P3_1 = 0x8000055308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P3_2 = 0x8000095307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P3_2 = 0x8000095308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P3_3 = 0x80000D5307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P3_3 = 0x80000D5308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P3_4 = 0x8000115307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P3_4 = 0x8000115308011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_0 = 0x800002530701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_0 = 0x800002530701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_0 = 0x800002530801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_1 = 0x800006530701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_1 = 0x800006530701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_1 = 0x800006530801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_2 = 0x80000A530701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_2 = 0x80000A530701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_2 = 0x80000A530801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_3 = 0x80000E530701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_3 = 0x80000E530701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_3 = 0x80000E530801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_4 = 0x800012530701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_4 = 0x800012530701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_4 = 0x800012530801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P1_0 = 0x800002530701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P1_0 = 0x800002530801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P1_1 = 0x800006530701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P1_1 = 0x800006530801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P1_2 = 0x80000A530701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P1_2 = 0x80000A530801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P1_3 = 0x80000E530701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P1_3 = 0x80000E530801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P1_4 = 0x800012530701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P1_4 = 0x800012530801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P2_0 = 0x800002530701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P2_0 = 0x800002530801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P2_1 = 0x800006530701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P2_1 = 0x800006530801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P2_2 = 0x80000A530701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P2_2 = 0x80000A530801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P2_3 = 0x80000E530701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P2_3 = 0x80000E530801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P2_4 = 0x800012530701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P2_4 = 0x800012530801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P3_0 = 0x8000025307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P3_0 = 0x8000025308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P3_1 = 0x8000065307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P3_1 = 0x8000065308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P3_2 = 0x80000A5307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P3_2 = 0x80000A5308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P3_3 = 0x80000E5307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P3_3 = 0x80000E5308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P3_4 = 0x8000125307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P3_4 = 0x8000125308011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_0 = 0x800003530701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_0 = 0x800003530701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_0 = 0x800003530801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_1 = 0x800007530701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_1 = 0x800007530701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_1 = 0x800007530801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_2 = 0x80000B530701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_2 = 0x80000B530701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_2 = 0x80000B530801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_3 = 0x80000F530701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_3 = 0x80000F530701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_3 = 0x80000F530801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_4 = 0x800013530701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_4 = 0x800013530701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_4 = 0x800013530801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P1_0 = 0x800003530701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P1_0 = 0x800003530801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P1_1 = 0x800007530701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P1_1 = 0x800007530801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P1_2 = 0x80000B530701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P1_2 = 0x80000B530801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P1_3 = 0x80000F530701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P1_3 = 0x80000F530801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P1_4 = 0x800013530701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P1_4 = 0x800013530801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P2_0 = 0x800003530701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P2_0 = 0x800003530801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P2_1 = 0x800007530701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P2_1 = 0x800007530801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P2_2 = 0x80000B530701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P2_2 = 0x80000B530801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P2_3 = 0x80000F530701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P2_3 = 0x80000F530801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P2_4 = 0x800013530701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P2_4 = 0x800013530801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P3_0 = 0x8000035307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P3_0 = 0x8000035308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P3_1 = 0x8000075307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P3_1 = 0x8000075308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P3_2 = 0x80000B5307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P3_2 = 0x80000B5308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P3_3 = 0x80000F5307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P3_3 = 0x80000F5308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P3_4 = 0x8000135307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P3_4 = 0x8000135308011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_0 = 0x800000540701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_0 = 0x800000540701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_0 = 0x800000540801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_1 = 0x800004540701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_1 = 0x800004540701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_1 = 0x800004540801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_2 = 0x800008540701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_2 = 0x800008540701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_2 = 0x800008540801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_3 = 0x80000C540701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_3 = 0x80000C540701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_3 = 0x80000C540801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_4 = 0x800010540701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_4 = 0x800010540701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_4 = 0x800010540801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P1_0 = 0x800000540701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P1_0 = 0x800000540801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P1_1 = 0x800004540701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P1_1 = 0x800004540801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P1_2 = 0x800008540701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P1_2 = 0x800008540801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P1_3 = 0x80000C540701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P1_3 = 0x80000C540801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P1_4 = 0x800010540701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P1_4 = 0x800010540801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P2_0 = 0x800000540701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P2_0 = 0x800000540801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P2_1 = 0x800004540701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P2_1 = 0x800004540801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P2_2 = 0x800008540701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P2_2 = 0x800008540801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P2_3 = 0x80000C540701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P2_3 = 0x80000C540801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P2_4 = 0x800010540701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P2_4 = 0x800010540801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P3_0 = 0x8000005407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P3_0 = 0x8000005408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P3_1 = 0x8000045407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P3_1 = 0x8000045408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P3_2 = 0x8000085407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P3_2 = 0x8000085408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P3_3 = 0x80000C5407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P3_3 = 0x80000C5408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P3_4 = 0x8000105407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P3_4 = 0x8000105408011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_0 = 0x800001540701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_0 = 0x800001540701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_0 = 0x800001540801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_1 = 0x800005540701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_1 = 0x800005540701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_1 = 0x800005540801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_2 = 0x800009540701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_2 = 0x800009540701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_2 = 0x800009540801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_3 = 0x80000D540701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_3 = 0x80000D540701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_3 = 0x80000D540801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_4 = 0x800011540701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_4 = 0x800011540701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_4 = 0x800011540801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P1_0 = 0x800001540701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P1_0 = 0x800001540801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P1_1 = 0x800005540701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P1_1 = 0x800005540801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P1_2 = 0x800009540701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P1_2 = 0x800009540801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P1_3 = 0x80000D540701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P1_3 = 0x80000D540801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P1_4 = 0x800011540701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P1_4 = 0x800011540801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P2_0 = 0x800001540701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P2_0 = 0x800001540801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P2_1 = 0x800005540701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P2_1 = 0x800005540801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P2_2 = 0x800009540701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P2_2 = 0x800009540801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P2_3 = 0x80000D540701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P2_3 = 0x80000D540801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P2_4 = 0x800011540701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P2_4 = 0x800011540801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P3_0 = 0x8000015407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P3_0 = 0x8000015408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P3_1 = 0x8000055407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P3_1 = 0x8000055408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P3_2 = 0x8000095407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P3_2 = 0x8000095408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P3_3 = 0x80000D5407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P3_3 = 0x80000D5408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P3_4 = 0x8000115407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P3_4 = 0x8000115408011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_0 = 0x800002540701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_0 = 0x800002540701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_0 = 0x800002540801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_1 = 0x800006540701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_1 = 0x800006540701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_1 = 0x800006540801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_2 = 0x80000A540701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_2 = 0x80000A540701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_2 = 0x80000A540801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_3 = 0x80000E540701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_3 = 0x80000E540701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_3 = 0x80000E540801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_4 = 0x800012540701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_4 = 0x800012540701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_4 = 0x800012540801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P1_0 = 0x800002540701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P1_0 = 0x800002540801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P1_1 = 0x800006540701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P1_1 = 0x800006540801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P1_2 = 0x80000A540701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P1_2 = 0x80000A540801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P1_3 = 0x80000E540701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P1_3 = 0x80000E540801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P1_4 = 0x800012540701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P1_4 = 0x800012540801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P2_0 = 0x800002540701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P2_0 = 0x800002540801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P2_1 = 0x800006540701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P2_1 = 0x800006540801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P2_2 = 0x80000A540701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P2_2 = 0x80000A540801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P2_3 = 0x80000E540701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P2_3 = 0x80000E540801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P2_4 = 0x800012540701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P2_4 = 0x800012540801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P3_0 = 0x8000025407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P3_0 = 0x8000025408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P3_1 = 0x8000065407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P3_1 = 0x8000065408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P3_2 = 0x80000A5407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P3_2 = 0x80000A5408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P3_3 = 0x80000E5407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P3_3 = 0x80000E5408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P3_4 = 0x8000125407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P3_4 = 0x8000125408011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_0 = 0x800003540701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_0 = 0x800003540701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_0 = 0x800003540801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_1 = 0x800007540701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_1 = 0x800007540701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_1 = 0x800007540801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_2 = 0x80000B540701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_2 = 0x80000B540701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_2 = 0x80000B540801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_3 = 0x80000F540701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_3 = 0x80000F540701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_3 = 0x80000F540801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_4 = 0x800013540701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_4 = 0x800013540701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_4 = 0x800013540801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P1_0 = 0x800003540701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P1_0 = 0x800003540801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P1_1 = 0x800007540701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P1_1 = 0x800007540801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P1_2 = 0x80000B540701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P1_2 = 0x80000B540801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P1_3 = 0x80000F540701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P1_3 = 0x80000F540801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P1_4 = 0x800013540701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P1_4 = 0x800013540801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P2_0 = 0x800003540701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P2_0 = 0x800003540801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P2_1 = 0x800007540701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P2_1 = 0x800007540801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P2_2 = 0x80000B540701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P2_2 = 0x80000B540801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P2_3 = 0x80000F540701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P2_3 = 0x80000F540801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P2_4 = 0x800013540701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P2_4 = 0x800013540801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P3_0 = 0x8000035407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P3_0 = 0x8000035408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P3_1 = 0x8000075407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P3_1 = 0x8000075408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P3_2 = 0x80000B5407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P3_2 = 0x80000B5408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P3_3 = 0x80000F5407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P3_3 = 0x80000F5408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P3_4 = 0x8000135407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P3_4 = 0x8000135408011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_0 = 0x800000550701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_0 = 0x800000550701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_0 = 0x800000550801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_1 = 0x800004550701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_1 = 0x800004550701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_1 = 0x800004550801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_2 = 0x800008550701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_2 = 0x800008550701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_2 = 0x800008550801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_3 = 0x80000C550701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_3 = 0x80000C550701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_3 = 0x80000C550801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_4 = 0x800010550701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_4 = 0x800010550701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_4 = 0x800010550801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P1_0 = 0x800000550701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P1_0 = 0x800000550801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P1_1 = 0x800004550701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P1_1 = 0x800004550801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P1_2 = 0x800008550701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P1_2 = 0x800008550801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P1_3 = 0x80000C550701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P1_3 = 0x80000C550801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P1_4 = 0x800010550701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P1_4 = 0x800010550801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P2_0 = 0x800000550701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P2_0 = 0x800000550801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P2_1 = 0x800004550701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P2_1 = 0x800004550801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P2_2 = 0x800008550701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P2_2 = 0x800008550801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P2_3 = 0x80000C550701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P2_3 = 0x80000C550801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P2_4 = 0x800010550701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P2_4 = 0x800010550801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P3_0 = 0x8000005507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P3_0 = 0x8000005508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P3_1 = 0x8000045507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P3_1 = 0x8000045508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P3_2 = 0x8000085507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P3_2 = 0x8000085508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P3_3 = 0x80000C5507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P3_3 = 0x80000C5508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P3_4 = 0x8000105507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P3_4 = 0x8000105508011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_0 = 0x800001550701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_0 = 0x800001550701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_0 = 0x800001550801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_1 = 0x800005550701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_1 = 0x800005550701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_1 = 0x800005550801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_2 = 0x800009550701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_2 = 0x800009550701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_2 = 0x800009550801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_3 = 0x80000D550701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_3 = 0x80000D550701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_3 = 0x80000D550801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_4 = 0x800011550701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_4 = 0x800011550701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_4 = 0x800011550801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P1_0 = 0x800001550701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P1_0 = 0x800001550801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P1_1 = 0x800005550701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P1_1 = 0x800005550801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P1_2 = 0x800009550701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P1_2 = 0x800009550801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P1_3 = 0x80000D550701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P1_3 = 0x80000D550801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P1_4 = 0x800011550701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P1_4 = 0x800011550801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P2_0 = 0x800001550701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P2_0 = 0x800001550801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P2_1 = 0x800005550701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P2_1 = 0x800005550801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P2_2 = 0x800009550701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P2_2 = 0x800009550801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P2_3 = 0x80000D550701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P2_3 = 0x80000D550801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P2_4 = 0x800011550701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P2_4 = 0x800011550801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P3_0 = 0x8000015507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P3_0 = 0x8000015508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P3_1 = 0x8000055507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P3_1 = 0x8000055508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P3_2 = 0x8000095507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P3_2 = 0x8000095508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P3_3 = 0x80000D5507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P3_3 = 0x80000D5508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P3_4 = 0x8000115507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P3_4 = 0x8000115508011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_0 = 0x800002550701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_0 = 0x800002550701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_0 = 0x800002550801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_1 = 0x800006550701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_1 = 0x800006550701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_1 = 0x800006550801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_2 = 0x80000A550701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_2 = 0x80000A550701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_2 = 0x80000A550801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_3 = 0x80000E550701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_3 = 0x80000E550701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_3 = 0x80000E550801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_4 = 0x800012550701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_4 = 0x800012550701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_4 = 0x800012550801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P1_0 = 0x800002550701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P1_0 = 0x800002550801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P1_1 = 0x800006550701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P1_1 = 0x800006550801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P1_2 = 0x80000A550701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P1_2 = 0x80000A550801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P1_3 = 0x80000E550701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P1_3 = 0x80000E550801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P1_4 = 0x800012550701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P1_4 = 0x800012550801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P2_0 = 0x800002550701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P2_0 = 0x800002550801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P2_1 = 0x800006550701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P2_1 = 0x800006550801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P2_2 = 0x80000A550701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P2_2 = 0x80000A550801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P2_3 = 0x80000E550701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P2_3 = 0x80000E550801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P2_4 = 0x800012550701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P2_4 = 0x800012550801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P3_0 = 0x8000025507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P3_0 = 0x8000025508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P3_1 = 0x8000065507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P3_1 = 0x8000065508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P3_2 = 0x80000A5507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P3_2 = 0x80000A5508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P3_3 = 0x80000E5507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P3_3 = 0x80000E5508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P3_4 = 0x8000125507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P3_4 = 0x8000125508011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_0 = 0x800003550701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_0 = 0x800003550701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_0 = 0x800003550801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_1 = 0x800007550701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_1 = 0x800007550701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_1 = 0x800007550801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_2 = 0x80000B550701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_2 = 0x80000B550701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_2 = 0x80000B550801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_3 = 0x80000F550701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_3 = 0x80000F550701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_3 = 0x80000F550801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_4 = 0x800013550701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_4 = 0x800013550701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_4 = 0x800013550801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P1_0 = 0x800003550701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P1_0 = 0x800003550801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P1_1 = 0x800007550701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P1_1 = 0x800007550801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P1_2 = 0x80000B550701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P1_2 = 0x80000B550801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P1_3 = 0x80000F550701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P1_3 = 0x80000F550801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P1_4 = 0x800013550701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P1_4 = 0x800013550801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P2_0 = 0x800003550701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P2_0 = 0x800003550801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P2_1 = 0x800007550701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P2_1 = 0x800007550801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P2_2 = 0x80000B550701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P2_2 = 0x80000B550801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P2_3 = 0x80000F550701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P2_3 = 0x80000F550801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P2_4 = 0x800013550701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P2_4 = 0x800013550801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P3_0 = 0x8000035507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P3_0 = 0x8000035508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P3_1 = 0x8000075507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P3_1 = 0x8000075508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P3_2 = 0x80000B5507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P3_2 = 0x80000B5508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P3_3 = 0x80000F5507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P3_3 = 0x80000F5508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P3_4 = 0x8000135507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P3_4 = 0x8000135508011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_0 = 0x800000560701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_0 = 0x800000560701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_0 = 0x800000560801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_1 = 0x800004560701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_1 = 0x800004560701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_1 = 0x800004560801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_2 = 0x800008560701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_2 = 0x800008560701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_2 = 0x800008560801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_3 = 0x80000C560701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_3 = 0x80000C560701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_3 = 0x80000C560801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_4 = 0x800010560701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_4 = 0x800010560701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_4 = 0x800010560801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P1_0 = 0x800000560701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P1_0 = 0x800000560801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P1_1 = 0x800004560701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P1_1 = 0x800004560801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P1_2 = 0x800008560701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P1_2 = 0x800008560801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P1_3 = 0x80000C560701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P1_3 = 0x80000C560801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P1_4 = 0x800010560701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P1_4 = 0x800010560801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P2_0 = 0x800000560701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P2_0 = 0x800000560801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P2_1 = 0x800004560701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P2_1 = 0x800004560801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P2_2 = 0x800008560701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P2_2 = 0x800008560801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P2_3 = 0x80000C560701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P2_3 = 0x80000C560801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P2_4 = 0x800010560701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P2_4 = 0x800010560801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P3_0 = 0x8000005607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P3_0 = 0x8000005608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P3_1 = 0x8000045607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P3_1 = 0x8000045608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P3_2 = 0x8000085607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P3_2 = 0x8000085608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P3_3 = 0x80000C5607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P3_3 = 0x80000C5608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P3_4 = 0x8000105607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P3_4 = 0x8000105608011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_0 = 0x800001560701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_0 = 0x800001560701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_0 = 0x800001560801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_1 = 0x800005560701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_1 = 0x800005560701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_1 = 0x800005560801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_2 = 0x800009560701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_2 = 0x800009560701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_2 = 0x800009560801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_3 = 0x80000D560701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_3 = 0x80000D560701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_3 = 0x80000D560801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_4 = 0x800011560701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_4 = 0x800011560701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_4 = 0x800011560801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P1_0 = 0x800001560701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P1_0 = 0x800001560801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P1_1 = 0x800005560701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P1_1 = 0x800005560801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P1_2 = 0x800009560701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P1_2 = 0x800009560801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P1_3 = 0x80000D560701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P1_3 = 0x80000D560801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P1_4 = 0x800011560701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P1_4 = 0x800011560801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P2_0 = 0x800001560701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P2_0 = 0x800001560801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P2_1 = 0x800005560701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P2_1 = 0x800005560801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P2_2 = 0x800009560701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P2_2 = 0x800009560801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P2_3 = 0x80000D560701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P2_3 = 0x80000D560801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P2_4 = 0x800011560701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P2_4 = 0x800011560801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P3_0 = 0x8000015607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P3_0 = 0x8000015608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P3_1 = 0x8000055607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P3_1 = 0x8000055608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P3_2 = 0x8000095607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P3_2 = 0x8000095608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P3_3 = 0x80000D5607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P3_3 = 0x80000D5608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P3_4 = 0x8000115607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P3_4 = 0x8000115608011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_0 = 0x800002560701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_0 = 0x800002560701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_0 = 0x800002560801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_1 = 0x800006560701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_1 = 0x800006560701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_1 = 0x800006560801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_2 = 0x80000A560701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_2 = 0x80000A560701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_2 = 0x80000A560801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_3 = 0x80000E560701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_3 = 0x80000E560701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_3 = 0x80000E560801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_4 = 0x800012560701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_4 = 0x800012560701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_4 = 0x800012560801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P1_0 = 0x800002560701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P1_0 = 0x800002560801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P1_1 = 0x800006560701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P1_1 = 0x800006560801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P1_2 = 0x80000A560701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P1_2 = 0x80000A560801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P1_3 = 0x80000E560701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P1_3 = 0x80000E560801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P1_4 = 0x800012560701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P1_4 = 0x800012560801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P2_0 = 0x800002560701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P2_0 = 0x800002560801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P2_1 = 0x800006560701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P2_1 = 0x800006560801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P2_2 = 0x80000A560701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P2_2 = 0x80000A560801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P2_3 = 0x80000E560701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P2_3 = 0x80000E560801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P2_4 = 0x800012560701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P2_4 = 0x800012560801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P3_0 = 0x8000025607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P3_0 = 0x8000025608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P3_1 = 0x8000065607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P3_1 = 0x8000065608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P3_2 = 0x80000A5607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P3_2 = 0x80000A5608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P3_3 = 0x80000E5607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P3_3 = 0x80000E5608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P3_4 = 0x8000125607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P3_4 = 0x8000125608011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_0 = 0x800003560701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_0 = 0x800003560701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_0 = 0x800003560801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_1 = 0x800007560701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_1 = 0x800007560701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_1 = 0x800007560801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_2 = 0x80000B560701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_2 = 0x80000B560701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_2 = 0x80000B560801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_3 = 0x80000F560701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_3 = 0x80000F560701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_3 = 0x80000F560801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_4 = 0x800013560701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_4 = 0x800013560701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_4 = 0x800013560801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P1_0 = 0x800003560701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P1_0 = 0x800003560801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P1_1 = 0x800007560701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P1_1 = 0x800007560801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P1_2 = 0x80000B560701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P1_2 = 0x80000B560801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P1_3 = 0x80000F560701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P1_3 = 0x80000F560801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P1_4 = 0x800013560701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P1_4 = 0x800013560801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P2_0 = 0x800003560701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P2_0 = 0x800003560801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P2_1 = 0x800007560701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P2_1 = 0x800007560801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P2_2 = 0x80000B560701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P2_2 = 0x80000B560801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P2_3 = 0x80000F560701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P2_3 = 0x80000F560801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P2_4 = 0x800013560701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P2_4 = 0x800013560801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P3_0 = 0x8000035607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P3_0 = 0x8000035608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P3_1 = 0x8000075607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P3_1 = 0x8000075608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P3_2 = 0x80000B5607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P3_2 = 0x80000B5608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P3_3 = 0x80000F5607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P3_3 = 0x80000F5608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P3_4 = 0x8000135607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P3_4 = 0x8000135608011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_0 = 0x800000570701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_0 = 0x800000570701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_0 = 0x800000570801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_1 = 0x800004570701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_1 = 0x800004570701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_1 = 0x800004570801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_2 = 0x800008570701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_2 = 0x800008570701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_2 = 0x800008570801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_3 = 0x80000C570701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_3 = 0x80000C570701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_3 = 0x80000C570801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_4 = 0x800010570701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_4 = 0x800010570701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_4 = 0x800010570801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P1_0 = 0x800000570701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P1_0 = 0x800000570801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P1_1 = 0x800004570701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P1_1 = 0x800004570801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P1_2 = 0x800008570701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P1_2 = 0x800008570801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P1_3 = 0x80000C570701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P1_3 = 0x80000C570801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P1_4 = 0x800010570701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P1_4 = 0x800010570801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P2_0 = 0x800000570701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P2_0 = 0x800000570801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P2_1 = 0x800004570701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P2_1 = 0x800004570801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P2_2 = 0x800008570701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P2_2 = 0x800008570801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P2_3 = 0x80000C570701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P2_3 = 0x80000C570801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P2_4 = 0x800010570701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P2_4 = 0x800010570801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P3_0 = 0x8000005707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P3_0 = 0x8000005708011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P3_1 = 0x8000045707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P3_1 = 0x8000045708011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P3_2 = 0x8000085707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P3_2 = 0x8000085708011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P3_3 = 0x80000C5707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P3_3 = 0x80000C5708011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P3_4 = 0x8000105707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P3_4 = 0x8000105708011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_0 = 0x800001570701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_0 = 0x800001570701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_0 = 0x800001570801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_1 = 0x800005570701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_1 = 0x800005570701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_1 = 0x800005570801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_2 = 0x800009570701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_2 = 0x800009570701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_2 = 0x800009570801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_3 = 0x80000D570701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_3 = 0x80000D570701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_3 = 0x80000D570801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_4 = 0x800011570701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_4 = 0x800011570701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_4 = 0x800011570801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P1_0 = 0x800001570701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P1_0 = 0x800001570801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P1_1 = 0x800005570701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P1_1 = 0x800005570801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P1_2 = 0x800009570701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P1_2 = 0x800009570801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P1_3 = 0x80000D570701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P1_3 = 0x80000D570801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P1_4 = 0x800011570701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P1_4 = 0x800011570801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P2_0 = 0x800001570701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P2_0 = 0x800001570801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P2_1 = 0x800005570701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P2_1 = 0x800005570801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P2_2 = 0x800009570701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P2_2 = 0x800009570801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P2_3 = 0x80000D570701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P2_3 = 0x80000D570801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P2_4 = 0x800011570701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P2_4 = 0x800011570801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P3_0 = 0x8000015707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P3_0 = 0x8000015708011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P3_1 = 0x8000055707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P3_1 = 0x8000055708011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P3_2 = 0x8000095707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P3_2 = 0x8000095708011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P3_3 = 0x80000D5707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P3_3 = 0x80000D5708011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P3_4 = 0x8000115707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P3_4 = 0x8000115708011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_0 = 0x800002570701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_0 = 0x800002570701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_0 = 0x800002570801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_1 = 0x800006570701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_1 = 0x800006570701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_1 = 0x800006570801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_2 = 0x80000A570701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_2 = 0x80000A570701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_2 = 0x80000A570801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_3 = 0x80000E570701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_3 = 0x80000E570701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_3 = 0x80000E570801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_4 = 0x800012570701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_4 = 0x800012570701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_4 = 0x800012570801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P1_0 = 0x800002570701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P1_0 = 0x800002570801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P1_1 = 0x800006570701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P1_1 = 0x800006570801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P1_2 = 0x80000A570701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P1_2 = 0x80000A570801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P1_3 = 0x80000E570701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P1_3 = 0x80000E570801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P1_4 = 0x800012570701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P1_4 = 0x800012570801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P2_0 = 0x800002570701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P2_0 = 0x800002570801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P2_1 = 0x800006570701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P2_1 = 0x800006570801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P2_2 = 0x80000A570701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P2_2 = 0x80000A570801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P2_3 = 0x80000E570701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P2_3 = 0x80000E570801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P2_4 = 0x800012570701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P2_4 = 0x800012570801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P3_0 = 0x8000025707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P3_0 = 0x8000025708011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P3_1 = 0x8000065707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P3_1 = 0x8000065708011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P3_2 = 0x80000A5707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P3_2 = 0x80000A5708011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P3_3 = 0x80000E5707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P3_3 = 0x80000E5708011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P3_4 = 0x8000125707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P3_4 = 0x8000125708011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_0 = 0x800003570701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_0 = 0x800003570701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_0 = 0x800003570801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_1 = 0x800007570701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_1 = 0x800007570701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_1 = 0x800007570801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_2 = 0x80000B570701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_2 = 0x80000B570701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_2 = 0x80000B570801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_3 = 0x80000F570701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_3 = 0x80000F570701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_3 = 0x80000F570801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_4 = 0x800013570701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_4 = 0x800013570701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_4 = 0x800013570801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P1_0 = 0x800003570701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P1_0 = 0x800003570801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P1_1 = 0x800007570701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P1_1 = 0x800007570801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P1_2 = 0x80000B570701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P1_2 = 0x80000B570801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P1_3 = 0x80000F570701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P1_3 = 0x80000F570801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P1_4 = 0x800013570701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P1_4 = 0x800013570801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P2_0 = 0x800003570701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P2_0 = 0x800003570801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P2_1 = 0x800007570701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P2_1 = 0x800007570801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P2_2 = 0x80000B570701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P2_2 = 0x80000B570801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P2_3 = 0x80000F570701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P2_3 = 0x80000F570801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P2_4 = 0x800013570701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P2_4 = 0x800013570801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P3_0 = 0x8000035707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P3_0 = 0x8000035708011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P3_1 = 0x8000075707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P3_1 = 0x8000075708011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P3_2 = 0x80000B5707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P3_2 = 0x80000B5708011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P3_3 = 0x80000F5707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P3_3 = 0x80000F5708011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P3_4 = 0x8000135707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P3_4 = 0x8000135708011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_0 = 0x8000000C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_0 = 0x8000000C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_0 = 0x8000000C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_1 = 0x8000040C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_1 = 0x8000040C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_1 = 0x8000040C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_2 = 0x8000080C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_2 = 0x8000080C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_2 = 0x8000080C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_3 = 0x80000C0C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_3 = 0x80000C0C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_3 = 0x80000C0C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_4 = 0x8000100C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_4 = 0x8000100C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_4 = 0x8000100C0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P1_0 = 0x8000000C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P1_0 = 0x8000000C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P1_1 = 0x8000040C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P1_1 = 0x8000040C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P1_2 = 0x8000080C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P1_2 = 0x8000080C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P1_3 = 0x80000C0C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P1_3 = 0x80000C0C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P1_4 = 0x8000100C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P1_4 = 0x8000100C0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P2_0 = 0x8000000C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P2_0 = 0x8000000C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P2_1 = 0x8000040C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P2_1 = 0x8000040C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P2_2 = 0x8000080C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P2_2 = 0x8000080C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P2_3 = 0x80000C0C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P2_3 = 0x80000C0C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P2_4 = 0x8000100C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P2_4 = 0x8000100C0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P3_0 = 0x8000000C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P3_0 = 0x8000000C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P3_1 = 0x8000040C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P3_1 = 0x8000040C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P3_2 = 0x8000080C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P3_2 = 0x8000080C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P3_3 = 0x80000C0C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P3_3 = 0x80000C0C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P3_4 = 0x8000100C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P3_4 = 0x8000100C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_0 = 0x8000010C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_0 = 0x8000010C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_0 = 0x8000010C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_1 = 0x8000050C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_1 = 0x8000050C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_1 = 0x8000050C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_2 = 0x8000090C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_2 = 0x8000090C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_2 = 0x8000090C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_3 = 0x80000D0C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_3 = 0x80000D0C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_3 = 0x80000D0C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_4 = 0x8000110C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_4 = 0x8000110C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_4 = 0x8000110C0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P1_0 = 0x8000010C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P1_0 = 0x8000010C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P1_1 = 0x8000050C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P1_1 = 0x8000050C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P1_2 = 0x8000090C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P1_2 = 0x8000090C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P1_3 = 0x80000D0C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P1_3 = 0x80000D0C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P1_4 = 0x8000110C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P1_4 = 0x8000110C0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P2_0 = 0x8000010C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P2_0 = 0x8000010C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P2_1 = 0x8000050C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P2_1 = 0x8000050C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P2_2 = 0x8000090C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P2_2 = 0x8000090C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P2_3 = 0x80000D0C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P2_3 = 0x80000D0C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P2_4 = 0x8000110C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P2_4 = 0x8000110C0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P3_0 = 0x8000010C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P3_0 = 0x8000010C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P3_1 = 0x8000050C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P3_1 = 0x8000050C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P3_2 = 0x8000090C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P3_2 = 0x8000090C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P3_3 = 0x80000D0C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P3_3 = 0x80000D0C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P3_4 = 0x8000110C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P3_4 = 0x8000110C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_0 = 0x8000020C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_0 = 0x8000020C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_0 = 0x8000020C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_1 = 0x8000060C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_1 = 0x8000060C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_1 = 0x8000060C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_2 = 0x80000A0C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_2 = 0x80000A0C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_2 = 0x80000A0C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_3 = 0x80000E0C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_3 = 0x80000E0C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_3 = 0x80000E0C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_4 = 0x8000120C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_4 = 0x8000120C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_4 = 0x8000120C0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P1_0 = 0x8000020C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P1_0 = 0x8000020C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P1_1 = 0x8000060C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P1_1 = 0x8000060C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P1_2 = 0x80000A0C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P1_2 = 0x80000A0C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P1_3 = 0x80000E0C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P1_3 = 0x80000E0C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P1_4 = 0x8000120C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P1_4 = 0x8000120C0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P2_0 = 0x8000020C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P2_0 = 0x8000020C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P2_1 = 0x8000060C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P2_1 = 0x8000060C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P2_2 = 0x80000A0C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P2_2 = 0x80000A0C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P2_3 = 0x80000E0C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P2_3 = 0x80000E0C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P2_4 = 0x8000120C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P2_4 = 0x8000120C0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P3_0 = 0x8000020C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P3_0 = 0x8000020C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P3_1 = 0x8000060C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P3_1 = 0x8000060C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P3_2 = 0x80000A0C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P3_2 = 0x80000A0C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P3_3 = 0x80000E0C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P3_3 = 0x80000E0C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P3_4 = 0x8000120C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P3_4 = 0x8000120C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_0 = 0x8000030C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_0 = 0x8000030C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_0 = 0x8000030C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_1 = 0x8000070C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_1 = 0x8000070C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_1 = 0x8000070C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_2 = 0x80000B0C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_2 = 0x80000B0C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_2 = 0x80000B0C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_3 = 0x80000F0C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_3 = 0x80000F0C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_3 = 0x80000F0C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_4 = 0x8000130C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_4 = 0x8000130C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_4 = 0x8000130C0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P1_0 = 0x8000030C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P1_0 = 0x8000030C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P1_1 = 0x8000070C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P1_1 = 0x8000070C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P1_2 = 0x80000B0C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P1_2 = 0x80000B0C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P1_3 = 0x80000F0C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P1_3 = 0x80000F0C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P1_4 = 0x8000130C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P1_4 = 0x8000130C0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P2_0 = 0x8000030C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P2_0 = 0x8000030C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P2_1 = 0x8000070C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P2_1 = 0x8000070C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P2_2 = 0x80000B0C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P2_2 = 0x80000B0C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P2_3 = 0x80000F0C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P2_3 = 0x80000F0C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P2_4 = 0x8000130C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P2_4 = 0x8000130C0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P3_0 = 0x8000030C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P3_0 = 0x8000030C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P3_1 = 0x8000070C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P3_1 = 0x8000070C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P3_2 = 0x80000B0C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P3_2 = 0x80000B0C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P3_3 = 0x80000F0C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P3_3 = 0x80000F0C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P3_4 = 0x8000130C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P3_4 = 0x8000130C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_0 = 0x8000000D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_0 = 0x8000000D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_0 = 0x8000000D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_1 = 0x8000040D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_1 = 0x8000040D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_1 = 0x8000040D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_2 = 0x8000080D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_2 = 0x8000080D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_2 = 0x8000080D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_3 = 0x80000C0D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_3 = 0x80000C0D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_3 = 0x80000C0D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_4 = 0x8000100D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_4 = 0x8000100D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_4 = 0x8000100D0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P1_0 = 0x8000000D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P1_0 = 0x8000000D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P1_1 = 0x8000040D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P1_1 = 0x8000040D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P1_2 = 0x8000080D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P1_2 = 0x8000080D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P1_3 = 0x80000C0D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P1_3 = 0x80000C0D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P1_4 = 0x8000100D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P1_4 = 0x8000100D0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P2_0 = 0x8000000D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P2_0 = 0x8000000D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P2_1 = 0x8000040D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P2_1 = 0x8000040D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P2_2 = 0x8000080D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P2_2 = 0x8000080D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P2_3 = 0x80000C0D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P2_3 = 0x80000C0D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P2_4 = 0x8000100D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P2_4 = 0x8000100D0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P3_0 = 0x8000000D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P3_0 = 0x8000000D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P3_1 = 0x8000040D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P3_1 = 0x8000040D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P3_2 = 0x8000080D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P3_2 = 0x8000080D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P3_3 = 0x80000C0D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P3_3 = 0x80000C0D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P3_4 = 0x8000100D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P3_4 = 0x8000100D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_0 = 0x8000010D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_0 = 0x8000010D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_0 = 0x8000010D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_1 = 0x8000050D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_1 = 0x8000050D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_1 = 0x8000050D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_2 = 0x8000090D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_2 = 0x8000090D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_2 = 0x8000090D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_3 = 0x80000D0D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_3 = 0x80000D0D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_3 = 0x80000D0D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_4 = 0x8000110D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_4 = 0x8000110D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_4 = 0x8000110D0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P1_0 = 0x8000010D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P1_0 = 0x8000010D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P1_1 = 0x8000050D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P1_1 = 0x8000050D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P1_2 = 0x8000090D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P1_2 = 0x8000090D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P1_3 = 0x80000D0D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P1_3 = 0x80000D0D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P1_4 = 0x8000110D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P1_4 = 0x8000110D0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P2_0 = 0x8000010D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P2_0 = 0x8000010D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P2_1 = 0x8000050D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P2_1 = 0x8000050D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P2_2 = 0x8000090D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P2_2 = 0x8000090D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P2_3 = 0x80000D0D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P2_3 = 0x80000D0D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P2_4 = 0x8000110D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P2_4 = 0x8000110D0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P3_0 = 0x8000010D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P3_0 = 0x8000010D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P3_1 = 0x8000050D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P3_1 = 0x8000050D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P3_2 = 0x8000090D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P3_2 = 0x8000090D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P3_3 = 0x80000D0D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P3_3 = 0x80000D0D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P3_4 = 0x8000110D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P3_4 = 0x8000110D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_0 = 0x8000020D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_0 = 0x8000020D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_0 = 0x8000020D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_1 = 0x8000060D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_1 = 0x8000060D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_1 = 0x8000060D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_2 = 0x80000A0D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_2 = 0x80000A0D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_2 = 0x80000A0D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_3 = 0x80000E0D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_3 = 0x80000E0D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_3 = 0x80000E0D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_4 = 0x8000120D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_4 = 0x8000120D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_4 = 0x8000120D0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P1_0 = 0x8000020D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P1_0 = 0x8000020D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P1_1 = 0x8000060D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P1_1 = 0x8000060D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P1_2 = 0x80000A0D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P1_2 = 0x80000A0D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P1_3 = 0x80000E0D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P1_3 = 0x80000E0D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P1_4 = 0x8000120D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P1_4 = 0x8000120D0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P2_0 = 0x8000020D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P2_0 = 0x8000020D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P2_1 = 0x8000060D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P2_1 = 0x8000060D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P2_2 = 0x80000A0D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P2_2 = 0x80000A0D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P2_3 = 0x80000E0D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P2_3 = 0x80000E0D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P2_4 = 0x8000120D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P2_4 = 0x8000120D0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P3_0 = 0x8000020D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P3_0 = 0x8000020D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P3_1 = 0x8000060D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P3_1 = 0x8000060D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P3_2 = 0x80000A0D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P3_2 = 0x80000A0D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P3_3 = 0x80000E0D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P3_3 = 0x80000E0D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P3_4 = 0x8000120D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P3_4 = 0x8000120D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_0 = 0x8000030D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_0 = 0x8000030D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_0 = 0x8000030D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_1 = 0x8000070D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_1 = 0x8000070D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_1 = 0x8000070D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_2 = 0x80000B0D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_2 = 0x80000B0D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_2 = 0x80000B0D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_3 = 0x80000F0D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_3 = 0x80000F0D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_3 = 0x80000F0D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_4 = 0x8000130D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_4 = 0x8000130D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_4 = 0x8000130D0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P1_0 = 0x8000030D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P1_0 = 0x8000030D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P1_1 = 0x8000070D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P1_1 = 0x8000070D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P1_2 = 0x80000B0D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P1_2 = 0x80000B0D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P1_3 = 0x80000F0D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P1_3 = 0x80000F0D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P1_4 = 0x8000130D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P1_4 = 0x8000130D0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P2_0 = 0x8000030D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P2_0 = 0x8000030D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P2_1 = 0x8000070D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P2_1 = 0x8000070D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P2_2 = 0x80000B0D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P2_2 = 0x80000B0D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P2_3 = 0x80000F0D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P2_3 = 0x80000F0D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P2_4 = 0x8000130D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P2_4 = 0x8000130D0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P3_0 = 0x8000030D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P3_0 = 0x8000030D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P3_1 = 0x8000070D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P3_1 = 0x8000070D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P3_2 = 0x80000B0D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P3_2 = 0x80000B0D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P3_3 = 0x80000F0D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P3_3 = 0x80000F0D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P3_4 = 0x8000130D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P3_4 = 0x8000130D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_0 = 0x800000720701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_0 = 0x800000720701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_0 = 0x800000720801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_1 = 0x800004720701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_1 = 0x800004720701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_1 = 0x800004720801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_2 = 0x800008720701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_2 = 0x800008720701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_2 = 0x800008720801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_3 = 0x80000C720701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_3 = 0x80000C720701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_3 = 0x80000C720801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_4 = 0x800010720701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_4 = 0x800010720701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_4 = 0x800010720801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P1_0 = 0x800000720701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P1_0 = 0x800000720801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P1_1 = 0x800004720701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P1_1 = 0x800004720801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P1_2 = 0x800008720701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P1_2 = 0x800008720801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P1_3 = 0x80000C720701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P1_3 = 0x80000C720801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P1_4 = 0x800010720701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P1_4 = 0x800010720801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P2_0 = 0x800000720701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P2_0 = 0x800000720801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P2_1 = 0x800004720701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P2_1 = 0x800004720801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P2_2 = 0x800008720701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P2_2 = 0x800008720801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P2_3 = 0x80000C720701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P2_3 = 0x80000C720801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P2_4 = 0x800010720701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P2_4 = 0x800010720801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P3_0 = 0x8000007207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P3_0 = 0x8000007208011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P3_1 = 0x8000047207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P3_1 = 0x8000047208011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P3_2 = 0x8000087207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P3_2 = 0x8000087208011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P3_3 = 0x80000C7207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P3_3 = 0x80000C7208011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P3_4 = 0x8000107207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P3_4 = 0x8000107208011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_0 = 0x800000600701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_0 = 0x800000600701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_0 = 0x800000600801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_1 = 0x800004600701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_1 = 0x800004600701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_1 = 0x800004600801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_2 = 0x800008600701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_2 = 0x800008600701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_2 = 0x800008600801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_3 = 0x80000C600701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_3 = 0x80000C600701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_3 = 0x80000C600801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_4 = 0x800010600701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_4 = 0x800010600701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_4 = 0x800010600801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P1_0 = 0x800000600701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P1_0 = 0x800000600801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P1_1 = 0x800004600701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P1_1 = 0x800004600801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P1_2 = 0x800008600701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P1_2 = 0x800008600801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P1_3 = 0x80000C600701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P1_3 = 0x80000C600801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P1_4 = 0x800010600701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P1_4 = 0x800010600801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P2_0 = 0x800000600701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P2_0 = 0x800000600801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P2_1 = 0x800004600701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P2_1 = 0x800004600801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P2_2 = 0x800008600701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P2_2 = 0x800008600801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P2_3 = 0x80000C600701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P2_3 = 0x80000C600801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P2_4 = 0x800010600701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P2_4 = 0x800010600801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P3_0 = 0x8000006007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P3_0 = 0x8000006008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P3_1 = 0x8000046007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P3_1 = 0x8000046008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P3_2 = 0x8000086007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P3_2 = 0x8000086008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P3_3 = 0x80000C6007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P3_3 = 0x80000C6008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P3_4 = 0x8000106007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P3_4 = 0x8000106008011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_0 = 0x800001600701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_0 = 0x800001600701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_0 = 0x800001600801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_1 = 0x800005600701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_1 = 0x800005600701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_1 = 0x800005600801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_2 = 0x800009600701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_2 = 0x800009600701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_2 = 0x800009600801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_3 = 0x80000D600701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_3 = 0x80000D600701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_3 = 0x80000D600801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_4 = 0x800011600701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_4 = 0x800011600701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_4 = 0x800011600801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P1_0 = 0x800001600701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P1_0 = 0x800001600801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P1_1 = 0x800005600701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P1_1 = 0x800005600801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P1_2 = 0x800009600701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P1_2 = 0x800009600801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P1_3 = 0x80000D600701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P1_3 = 0x80000D600801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P1_4 = 0x800011600701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P1_4 = 0x800011600801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P2_0 = 0x800001600701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P2_0 = 0x800001600801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P2_1 = 0x800005600701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P2_1 = 0x800005600801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P2_2 = 0x800009600701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P2_2 = 0x800009600801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P2_3 = 0x80000D600701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P2_3 = 0x80000D600801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P2_4 = 0x800011600701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P2_4 = 0x800011600801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P3_0 = 0x8000016007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P3_0 = 0x8000016008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P3_1 = 0x8000056007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P3_1 = 0x8000056008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P3_2 = 0x8000096007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P3_2 = 0x8000096008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P3_3 = 0x80000D6007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P3_3 = 0x80000D6008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P3_4 = 0x8000116007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P3_4 = 0x8000116008011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_0 = 0x800002600701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_0 = 0x800002600701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_0 = 0x800002600801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_1 = 0x800006600701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_1 = 0x800006600701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_1 = 0x800006600801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_2 = 0x80000A600701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_2 = 0x80000A600701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_2 = 0x80000A600801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_3 = 0x80000E600701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_3 = 0x80000E600701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_3 = 0x80000E600801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_4 = 0x800012600701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_4 = 0x800012600701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_4 = 0x800012600801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P1_0 = 0x800002600701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P1_0 = 0x800002600801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P1_1 = 0x800006600701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P1_1 = 0x800006600801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P1_2 = 0x80000A600701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P1_2 = 0x80000A600801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P1_3 = 0x80000E600701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P1_3 = 0x80000E600801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P1_4 = 0x800012600701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P1_4 = 0x800012600801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P2_0 = 0x800002600701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P2_0 = 0x800002600801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P2_1 = 0x800006600701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P2_1 = 0x800006600801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P2_2 = 0x80000A600701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P2_2 = 0x80000A600801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P2_3 = 0x80000E600701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P2_3 = 0x80000E600801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P2_4 = 0x800012600701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P2_4 = 0x800012600801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P3_0 = 0x8000026007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P3_0 = 0x8000026008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P3_1 = 0x8000066007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P3_1 = 0x8000066008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P3_2 = 0x80000A6007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P3_2 = 0x80000A6008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P3_3 = 0x80000E6007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P3_3 = 0x80000E6008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P3_4 = 0x8000126007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P3_4 = 0x8000126008011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_0 = 0x800003600701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_0 = 0x800003600701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_0 = 0x800003600801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_1 = 0x800007600701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_1 = 0x800007600701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_1 = 0x800007600801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_2 = 0x80000B600701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_2 = 0x80000B600701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_2 = 0x80000B600801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_3 = 0x80000F600701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_3 = 0x80000F600701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_3 = 0x80000F600801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_4 = 0x800013600701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_4 = 0x800013600701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_4 = 0x800013600801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P1_0 = 0x800003600701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P1_0 = 0x800003600801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P1_1 = 0x800007600701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P1_1 = 0x800007600801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P1_2 = 0x80000B600701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P1_2 = 0x80000B600801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P1_3 = 0x80000F600701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P1_3 = 0x80000F600801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P1_4 = 0x800013600701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P1_4 = 0x800013600801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P2_0 = 0x800003600701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P2_0 = 0x800003600801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P2_1 = 0x800007600701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P2_1 = 0x800007600801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P2_2 = 0x80000B600701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P2_2 = 0x80000B600801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P2_3 = 0x80000F600701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P2_3 = 0x80000F600801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P2_4 = 0x800013600701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P2_4 = 0x800013600801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P3_0 = 0x8000036007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P3_0 = 0x8000036008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P3_1 = 0x8000076007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P3_1 = 0x8000076008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P3_2 = 0x80000B6007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P3_2 = 0x80000B6008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P3_3 = 0x80000F6007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P3_3 = 0x80000F6008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P3_4 = 0x8000136007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P3_4 = 0x8000136008011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_0 = 0x8000006A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_0 = 0x8000006A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_0 = 0x8000006A0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_1 = 0x8000046A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_1 = 0x8000046A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_1 = 0x8000046A0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_2 = 0x8000086A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_2 = 0x8000086A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_2 = 0x8000086A0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_3 = 0x80000C6A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_3 = 0x80000C6A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_3 = 0x80000C6A0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_4 = 0x8000106A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_4 = 0x8000106A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_4 = 0x8000106A0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P1_0 = 0x8000006A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P1_0 = 0x8000006A0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P1_1 = 0x8000046A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P1_1 = 0x8000046A0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P1_2 = 0x8000086A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P1_2 = 0x8000086A0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P1_3 = 0x80000C6A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P1_3 = 0x80000C6A0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P1_4 = 0x8000106A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P1_4 = 0x8000106A0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P2_0 = 0x8000006A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P2_0 = 0x8000006A0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P2_1 = 0x8000046A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P2_1 = 0x8000046A0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P2_2 = 0x8000086A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P2_2 = 0x8000086A0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P2_3 = 0x80000C6A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P2_3 = 0x80000C6A0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P2_4 = 0x8000106A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P2_4 = 0x8000106A0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P3_0 = 0x8000006A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P3_0 = 0x8000006A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P3_1 = 0x8000046A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P3_1 = 0x8000046A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P3_2 = 0x8000086A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P3_2 = 0x8000086A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P3_3 = 0x80000C6A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P3_3 = 0x80000C6A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P3_4 = 0x8000106A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P3_4 = 0x8000106A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_0 = 0x8000016A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_0 = 0x8000016A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_0 = 0x8000016A0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_1 = 0x8000056A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_1 = 0x8000056A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_1 = 0x8000056A0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_2 = 0x8000096A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_2 = 0x8000096A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_2 = 0x8000096A0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_3 = 0x80000D6A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_3 = 0x80000D6A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_3 = 0x80000D6A0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_4 = 0x8000116A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_4 = 0x8000116A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_4 = 0x8000116A0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P1_0 = 0x8000016A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P1_0 = 0x8000016A0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P1_1 = 0x8000056A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P1_1 = 0x8000056A0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P1_2 = 0x8000096A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P1_2 = 0x8000096A0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P1_3 = 0x80000D6A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P1_3 = 0x80000D6A0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P1_4 = 0x8000116A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P1_4 = 0x8000116A0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P2_0 = 0x8000016A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P2_0 = 0x8000016A0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P2_1 = 0x8000056A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P2_1 = 0x8000056A0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P2_2 = 0x8000096A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P2_2 = 0x8000096A0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P2_3 = 0x80000D6A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P2_3 = 0x80000D6A0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P2_4 = 0x8000116A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P2_4 = 0x8000116A0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P3_0 = 0x8000016A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P3_0 = 0x8000016A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P3_1 = 0x8000056A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P3_1 = 0x8000056A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P3_2 = 0x8000096A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P3_2 = 0x8000096A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P3_3 = 0x80000D6A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P3_3 = 0x80000D6A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P3_4 = 0x8000116A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P3_4 = 0x8000116A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_0 = 0x8000026A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_0 = 0x8000026A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_0 = 0x8000026A0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_1 = 0x8000066A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_1 = 0x8000066A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_1 = 0x8000066A0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_2 = 0x80000A6A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_2 = 0x80000A6A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_2 = 0x80000A6A0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_3 = 0x80000E6A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_3 = 0x80000E6A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_3 = 0x80000E6A0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_4 = 0x8000126A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_4 = 0x8000126A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_4 = 0x8000126A0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P1_0 = 0x8000026A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P1_0 = 0x8000026A0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P1_1 = 0x8000066A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P1_1 = 0x8000066A0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P1_2 = 0x80000A6A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P1_2 = 0x80000A6A0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P1_3 = 0x80000E6A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P1_3 = 0x80000E6A0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P1_4 = 0x8000126A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P1_4 = 0x8000126A0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P2_0 = 0x8000026A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P2_0 = 0x8000026A0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P2_1 = 0x8000066A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P2_1 = 0x8000066A0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P2_2 = 0x80000A6A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P2_2 = 0x80000A6A0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P2_3 = 0x80000E6A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P2_3 = 0x80000E6A0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P2_4 = 0x8000126A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P2_4 = 0x8000126A0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P3_0 = 0x8000026A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P3_0 = 0x8000026A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P3_1 = 0x8000066A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P3_1 = 0x8000066A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P3_2 = 0x80000A6A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P3_2 = 0x80000A6A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P3_3 = 0x80000E6A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P3_3 = 0x80000E6A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P3_4 = 0x8000126A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P3_4 = 0x8000126A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_0 = 0x8000036A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_0 = 0x8000036A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_0 = 0x8000036A0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_1 = 0x8000076A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_1 = 0x8000076A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_1 = 0x8000076A0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_2 = 0x80000B6A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_2 = 0x80000B6A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_2 = 0x80000B6A0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_3 = 0x80000F6A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_3 = 0x80000F6A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_3 = 0x80000F6A0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_4 = 0x8000136A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_4 = 0x8000136A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_4 = 0x8000136A0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P1_0 = 0x8000036A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P1_0 = 0x8000036A0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P1_1 = 0x8000076A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P1_1 = 0x8000076A0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P1_2 = 0x80000B6A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P1_2 = 0x80000B6A0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P1_3 = 0x80000F6A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P1_3 = 0x80000F6A0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P1_4 = 0x8000136A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P1_4 = 0x8000136A0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P2_0 = 0x8000036A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P2_0 = 0x8000036A0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P2_1 = 0x8000076A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P2_1 = 0x8000076A0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P2_2 = 0x80000B6A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P2_2 = 0x80000B6A0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P2_3 = 0x80000F6A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P2_3 = 0x80000F6A0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P2_4 = 0x8000136A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P2_4 = 0x8000136A0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P3_0 = 0x8000036A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P3_0 = 0x8000036A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P3_1 = 0x8000076A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P3_1 = 0x8000076A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P3_2 = 0x80000B6A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P3_2 = 0x80000B6A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P3_3 = 0x80000F6A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P3_3 = 0x80000F6A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P3_4 = 0x8000136A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P3_4 = 0x8000136A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_0 = 0x8000006B0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_0 = 0x8000006B0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_0 = 0x8000006B0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_1 = 0x8000046B0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_1 = 0x8000046B0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_1 = 0x8000046B0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_2 = 0x8000086B0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_2 = 0x8000086B0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_2 = 0x8000086B0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_3 = 0x80000C6B0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_3 = 0x80000C6B0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_3 = 0x80000C6B0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_4 = 0x8000106B0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_4 = 0x8000106B0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_4 = 0x8000106B0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P1_0 = 0x8000006B0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P1_0 = 0x8000006B0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P1_1 = 0x8000046B0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P1_1 = 0x8000046B0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P1_2 = 0x8000086B0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P1_2 = 0x8000086B0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P1_3 = 0x80000C6B0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P1_3 = 0x80000C6B0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P1_4 = 0x8000106B0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P1_4 = 0x8000106B0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P2_0 = 0x8000006B0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P2_0 = 0x8000006B0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P2_1 = 0x8000046B0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P2_1 = 0x8000046B0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P2_2 = 0x8000086B0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P2_2 = 0x8000086B0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P2_3 = 0x80000C6B0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P2_3 = 0x80000C6B0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P2_4 = 0x8000106B0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P2_4 = 0x8000106B0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P3_0 = 0x8000006B07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P3_0 = 0x8000006B08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P3_1 = 0x8000046B07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P3_1 = 0x8000046B08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P3_2 = 0x8000086B07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P3_2 = 0x8000086B08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P3_3 = 0x80000C6B07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P3_3 = 0x80000C6B08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P3_4 = 0x8000106B07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P3_4 = 0x8000106B08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_0 = 0x8000016B0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_0 = 0x8000016B0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_0 = 0x8000016B0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_1 = 0x8000056B0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_1 = 0x8000056B0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_1 = 0x8000056B0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_2 = 0x8000096B0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_2 = 0x8000096B0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_2 = 0x8000096B0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_3 = 0x80000D6B0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_3 = 0x80000D6B0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_3 = 0x80000D6B0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_4 = 0x8000116B0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_4 = 0x8000116B0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_4 = 0x8000116B0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P1_0 = 0x8000016B0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P1_0 = 0x8000016B0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P1_1 = 0x8000056B0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P1_1 = 0x8000056B0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P1_2 = 0x8000096B0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P1_2 = 0x8000096B0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P1_3 = 0x80000D6B0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P1_3 = 0x80000D6B0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P1_4 = 0x8000116B0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P1_4 = 0x8000116B0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P2_0 = 0x8000016B0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P2_0 = 0x8000016B0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P2_1 = 0x8000056B0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P2_1 = 0x8000056B0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P2_2 = 0x8000096B0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P2_2 = 0x8000096B0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P2_3 = 0x80000D6B0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P2_3 = 0x80000D6B0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P2_4 = 0x8000116B0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P2_4 = 0x8000116B0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P3_0 = 0x8000016B07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P3_0 = 0x8000016B08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P3_1 = 0x8000056B07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P3_1 = 0x8000056B08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P3_2 = 0x8000096B07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P3_2 = 0x8000096B08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P3_3 = 0x80000D6B07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P3_3 = 0x80000D6B08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P3_4 = 0x8000116B07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P3_4 = 0x8000116B08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_0 = 0x8000026B0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_0 = 0x8000026B0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_0 = 0x8000026B0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_1 = 0x8000066B0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_1 = 0x8000066B0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_1 = 0x8000066B0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_2 = 0x80000A6B0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_2 = 0x80000A6B0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_2 = 0x80000A6B0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_3 = 0x80000E6B0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_3 = 0x80000E6B0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_3 = 0x80000E6B0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_4 = 0x8000126B0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_4 = 0x8000126B0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_4 = 0x8000126B0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P1_0 = 0x8000026B0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P1_0 = 0x8000026B0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P1_1 = 0x8000066B0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P1_1 = 0x8000066B0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P1_2 = 0x80000A6B0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P1_2 = 0x80000A6B0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P1_3 = 0x80000E6B0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P1_3 = 0x80000E6B0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P1_4 = 0x8000126B0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P1_4 = 0x8000126B0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P2_0 = 0x8000026B0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P2_0 = 0x8000026B0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P2_1 = 0x8000066B0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P2_1 = 0x8000066B0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P2_2 = 0x80000A6B0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P2_2 = 0x80000A6B0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P2_3 = 0x80000E6B0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P2_3 = 0x80000E6B0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P2_4 = 0x8000126B0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P2_4 = 0x8000126B0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P3_0 = 0x8000026B07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P3_0 = 0x8000026B08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P3_1 = 0x8000066B07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P3_1 = 0x8000066B08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P3_2 = 0x80000A6B07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P3_2 = 0x80000A6B08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P3_3 = 0x80000E6B07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P3_3 = 0x80000E6B08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P3_4 = 0x8000126B07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P3_4 = 0x8000126B08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_0 = 0x8000036B0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_0 = 0x8000036B0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_0 = 0x8000036B0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_1 = 0x8000076B0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_1 = 0x8000076B0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_1 = 0x8000076B0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_2 = 0x80000B6B0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_2 = 0x80000B6B0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_2 = 0x80000B6B0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_3 = 0x80000F6B0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_3 = 0x80000F6B0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_3 = 0x80000F6B0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_4 = 0x8000136B0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_4 = 0x8000136B0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_4 = 0x8000136B0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P1_0 = 0x8000036B0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P1_0 = 0x8000036B0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P1_1 = 0x8000076B0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P1_1 = 0x8000076B0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P1_2 = 0x80000B6B0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P1_2 = 0x80000B6B0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P1_3 = 0x80000F6B0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P1_3 = 0x80000F6B0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P1_4 = 0x8000136B0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P1_4 = 0x8000136B0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P2_0 = 0x8000036B0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P2_0 = 0x8000036B0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P2_1 = 0x8000076B0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P2_1 = 0x8000076B0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P2_2 = 0x80000B6B0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P2_2 = 0x80000B6B0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P2_3 = 0x80000F6B0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P2_3 = 0x80000F6B0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P2_4 = 0x8000136B0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P2_4 = 0x8000136B0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P3_0 = 0x8000036B07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P3_0 = 0x8000036B08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P3_1 = 0x8000076B07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P3_1 = 0x8000076B08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P3_2 = 0x80000B6B07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P3_2 = 0x80000B6B08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P3_3 = 0x80000F6B07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P3_3 = 0x80000F6B08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P3_4 = 0x8000136B07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P3_4 = 0x8000136B08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_0 = 0x800000610701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_0 = 0x800000610701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_0 = 0x800000610801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_1 = 0x800004610701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_1 = 0x800004610701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_1 = 0x800004610801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_2 = 0x800008610701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_2 = 0x800008610701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_2 = 0x800008610801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_3 = 0x80000C610701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_3 = 0x80000C610701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_3 = 0x80000C610801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_4 = 0x800010610701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_4 = 0x800010610701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_4 = 0x800010610801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P1_0 = 0x800000610701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P1_0 = 0x800000610801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P1_1 = 0x800004610701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P1_1 = 0x800004610801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P1_2 = 0x800008610701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P1_2 = 0x800008610801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P1_3 = 0x80000C610701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P1_3 = 0x80000C610801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P1_4 = 0x800010610701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P1_4 = 0x800010610801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P2_0 = 0x800000610701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P2_0 = 0x800000610801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P2_1 = 0x800004610701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P2_1 = 0x800004610801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P2_2 = 0x800008610701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P2_2 = 0x800008610801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P2_3 = 0x80000C610701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P2_3 = 0x80000C610801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P2_4 = 0x800010610701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P2_4 = 0x800010610801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P3_0 = 0x8000006107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P3_0 = 0x8000006108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P3_1 = 0x8000046107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P3_1 = 0x8000046108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P3_2 = 0x8000086107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P3_2 = 0x8000086108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P3_3 = 0x80000C6107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P3_3 = 0x80000C6108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P3_4 = 0x8000106107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P3_4 = 0x8000106108011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_0 = 0x800001610701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_0 = 0x800001610701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_0 = 0x800001610801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_1 = 0x800005610701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_1 = 0x800005610701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_1 = 0x800005610801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_2 = 0x800009610701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_2 = 0x800009610701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_2 = 0x800009610801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_3 = 0x80000D610701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_3 = 0x80000D610701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_3 = 0x80000D610801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_4 = 0x800011610701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_4 = 0x800011610701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_4 = 0x800011610801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P1_0 = 0x800001610701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P1_0 = 0x800001610801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P1_1 = 0x800005610701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P1_1 = 0x800005610801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P1_2 = 0x800009610701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P1_2 = 0x800009610801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P1_3 = 0x80000D610701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P1_3 = 0x80000D610801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P1_4 = 0x800011610701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P1_4 = 0x800011610801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P2_0 = 0x800001610701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P2_0 = 0x800001610801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P2_1 = 0x800005610701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P2_1 = 0x800005610801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P2_2 = 0x800009610701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P2_2 = 0x800009610801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P2_3 = 0x80000D610701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P2_3 = 0x80000D610801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P2_4 = 0x800011610701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P2_4 = 0x800011610801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P3_0 = 0x8000016107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P3_0 = 0x8000016108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P3_1 = 0x8000056107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P3_1 = 0x8000056108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P3_2 = 0x8000096107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P3_2 = 0x8000096108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P3_3 = 0x80000D6107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P3_3 = 0x80000D6108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P3_4 = 0x8000116107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P3_4 = 0x8000116108011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_0 = 0x800002610701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_0 = 0x800002610701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_0 = 0x800002610801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_1 = 0x800006610701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_1 = 0x800006610701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_1 = 0x800006610801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_2 = 0x80000A610701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_2 = 0x80000A610701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_2 = 0x80000A610801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_3 = 0x80000E610701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_3 = 0x80000E610701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_3 = 0x80000E610801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_4 = 0x800012610701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_4 = 0x800012610701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_4 = 0x800012610801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P1_0 = 0x800002610701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P1_0 = 0x800002610801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P1_1 = 0x800006610701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P1_1 = 0x800006610801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P1_2 = 0x80000A610701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P1_2 = 0x80000A610801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P1_3 = 0x80000E610701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P1_3 = 0x80000E610801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P1_4 = 0x800012610701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P1_4 = 0x800012610801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P2_0 = 0x800002610701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P2_0 = 0x800002610801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P2_1 = 0x800006610701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P2_1 = 0x800006610801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P2_2 = 0x80000A610701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P2_2 = 0x80000A610801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P2_3 = 0x80000E610701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P2_3 = 0x80000E610801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P2_4 = 0x800012610701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P2_4 = 0x800012610801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P3_0 = 0x8000026107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P3_0 = 0x8000026108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P3_1 = 0x8000066107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P3_1 = 0x8000066108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P3_2 = 0x80000A6107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P3_2 = 0x80000A6108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P3_3 = 0x80000E6107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P3_3 = 0x80000E6108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P3_4 = 0x8000126107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P3_4 = 0x8000126108011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_0 = 0x800003610701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_0 = 0x800003610701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_0 = 0x800003610801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_1 = 0x800007610701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_1 = 0x800007610701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_1 = 0x800007610801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_2 = 0x80000B610701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_2 = 0x80000B610701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_2 = 0x80000B610801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_3 = 0x80000F610701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_3 = 0x80000F610701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_3 = 0x80000F610801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_4 = 0x800013610701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_4 = 0x800013610701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_4 = 0x800013610801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P1_0 = 0x800003610701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P1_0 = 0x800003610801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P1_1 = 0x800007610701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P1_1 = 0x800007610801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P1_2 = 0x80000B610701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P1_2 = 0x80000B610801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P1_3 = 0x80000F610701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P1_3 = 0x80000F610801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P1_4 = 0x800013610701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P1_4 = 0x800013610801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P2_0 = 0x800003610701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P2_0 = 0x800003610801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P2_1 = 0x800007610701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P2_1 = 0x800007610801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P2_2 = 0x80000B610701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P2_2 = 0x80000B610801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P2_3 = 0x80000F610701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P2_3 = 0x80000F610801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P2_4 = 0x800013610701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P2_4 = 0x800013610801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P3_0 = 0x8000036107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P3_0 = 0x8000036108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P3_1 = 0x8000076107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P3_1 = 0x8000076108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P3_2 = 0x80000B6107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P3_2 = 0x80000B6108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P3_3 = 0x80000F6107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P3_3 = 0x80000F6108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P3_4 = 0x8000136107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P3_4 = 0x8000136108011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_0 = 0x800000620701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_0 = 0x800000620701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_0 = 0x800000620801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_1 = 0x800004620701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_1 = 0x800004620701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_1 = 0x800004620801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_2 = 0x800008620701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_2 = 0x800008620701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_2 = 0x800008620801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_3 = 0x80000C620701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_3 = 0x80000C620701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_3 = 0x80000C620801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_4 = 0x800010620701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_4 = 0x800010620701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_4 = 0x800010620801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P1_0 = 0x800000620701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P1_0 = 0x800000620801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P1_1 = 0x800004620701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P1_1 = 0x800004620801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P1_2 = 0x800008620701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P1_2 = 0x800008620801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P1_3 = 0x80000C620701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P1_3 = 0x80000C620801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P1_4 = 0x800010620701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P1_4 = 0x800010620801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P2_0 = 0x800000620701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P2_0 = 0x800000620801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P2_1 = 0x800004620701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P2_1 = 0x800004620801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P2_2 = 0x800008620701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P2_2 = 0x800008620801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P2_3 = 0x80000C620701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P2_3 = 0x80000C620801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P2_4 = 0x800010620701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P2_4 = 0x800010620801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P3_0 = 0x8000006207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P3_0 = 0x8000006208011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P3_1 = 0x8000046207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P3_1 = 0x8000046208011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P3_2 = 0x8000086207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P3_2 = 0x8000086208011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P3_3 = 0x80000C6207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P3_3 = 0x80000C6208011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P3_4 = 0x8000106207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P3_4 = 0x8000106208011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_0 = 0x800001620701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_0 = 0x800001620701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_0 = 0x800001620801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_1 = 0x800005620701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_1 = 0x800005620701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_1 = 0x800005620801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_2 = 0x800009620701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_2 = 0x800009620701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_2 = 0x800009620801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_3 = 0x80000D620701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_3 = 0x80000D620701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_3 = 0x80000D620801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_4 = 0x800011620701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_4 = 0x800011620701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_4 = 0x800011620801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P1_0 = 0x800001620701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P1_0 = 0x800001620801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P1_1 = 0x800005620701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P1_1 = 0x800005620801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P1_2 = 0x800009620701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P1_2 = 0x800009620801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P1_3 = 0x80000D620701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P1_3 = 0x80000D620801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P1_4 = 0x800011620701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P1_4 = 0x800011620801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P2_0 = 0x800001620701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P2_0 = 0x800001620801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P2_1 = 0x800005620701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P2_1 = 0x800005620801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P2_2 = 0x800009620701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P2_2 = 0x800009620801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P2_3 = 0x80000D620701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P2_3 = 0x80000D620801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P2_4 = 0x800011620701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P2_4 = 0x800011620801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P3_0 = 0x8000016207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P3_0 = 0x8000016208011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P3_1 = 0x8000056207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P3_1 = 0x8000056208011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P3_2 = 0x8000096207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P3_2 = 0x8000096208011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P3_3 = 0x80000D6207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P3_3 = 0x80000D6208011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P3_4 = 0x8000116207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P3_4 = 0x8000116208011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_0 = 0x800002620701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_0 = 0x800002620701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_0 = 0x800002620801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_1 = 0x800006620701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_1 = 0x800006620701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_1 = 0x800006620801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_2 = 0x80000A620701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_2 = 0x80000A620701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_2 = 0x80000A620801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_3 = 0x80000E620701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_3 = 0x80000E620701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_3 = 0x80000E620801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_4 = 0x800012620701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_4 = 0x800012620701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_4 = 0x800012620801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P1_0 = 0x800002620701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P1_0 = 0x800002620801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P1_1 = 0x800006620701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P1_1 = 0x800006620801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P1_2 = 0x80000A620701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P1_2 = 0x80000A620801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P1_3 = 0x80000E620701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P1_3 = 0x80000E620801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P1_4 = 0x800012620701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P1_4 = 0x800012620801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P2_0 = 0x800002620701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P2_0 = 0x800002620801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P2_1 = 0x800006620701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P2_1 = 0x800006620801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P2_2 = 0x80000A620701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P2_2 = 0x80000A620801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P2_3 = 0x80000E620701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P2_3 = 0x80000E620801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P2_4 = 0x800012620701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P2_4 = 0x800012620801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P3_0 = 0x8000026207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P3_0 = 0x8000026208011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P3_1 = 0x8000066207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P3_1 = 0x8000066208011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P3_2 = 0x80000A6207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P3_2 = 0x80000A6208011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P3_3 = 0x80000E6207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P3_3 = 0x80000E6208011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P3_4 = 0x8000126207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P3_4 = 0x8000126208011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_0 = 0x800003620701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_0 = 0x800003620701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_0 = 0x800003620801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_1 = 0x800007620701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_1 = 0x800007620701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_1 = 0x800007620801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_2 = 0x80000B620701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_2 = 0x80000B620701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_2 = 0x80000B620801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_3 = 0x80000F620701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_3 = 0x80000F620701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_3 = 0x80000F620801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_4 = 0x800013620701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_4 = 0x800013620701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_4 = 0x800013620801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P1_0 = 0x800003620701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P1_0 = 0x800003620801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P1_1 = 0x800007620701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P1_1 = 0x800007620801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P1_2 = 0x80000B620701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P1_2 = 0x80000B620801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P1_3 = 0x80000F620701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P1_3 = 0x80000F620801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P1_4 = 0x800013620701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P1_4 = 0x800013620801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P2_0 = 0x800003620701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P2_0 = 0x800003620801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P2_1 = 0x800007620701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P2_1 = 0x800007620801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P2_2 = 0x80000B620701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P2_2 = 0x80000B620801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P2_3 = 0x80000F620701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P2_3 = 0x80000F620801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P2_4 = 0x800013620701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P2_4 = 0x800013620801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P3_0 = 0x8000036207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P3_0 = 0x8000036208011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P3_1 = 0x8000076207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P3_1 = 0x8000076208011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P3_2 = 0x80000B6207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P3_2 = 0x80000B6208011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P3_3 = 0x80000F6207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P3_3 = 0x80000F6208011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P3_4 = 0x8000136207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P3_4 = 0x8000136208011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_0 = 0x800000630701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_0 = 0x800000630701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_0 = 0x800000630801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_1 = 0x800004630701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_1 = 0x800004630701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_1 = 0x800004630801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_2 = 0x800008630701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_2 = 0x800008630701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_2 = 0x800008630801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_3 = 0x80000C630701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_3 = 0x80000C630701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_3 = 0x80000C630801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_4 = 0x800010630701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_4 = 0x800010630701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_4 = 0x800010630801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P1_0 = 0x800000630701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P1_0 = 0x800000630801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P1_1 = 0x800004630701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P1_1 = 0x800004630801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P1_2 = 0x800008630701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P1_2 = 0x800008630801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P1_3 = 0x80000C630701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P1_3 = 0x80000C630801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P1_4 = 0x800010630701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P1_4 = 0x800010630801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P2_0 = 0x800000630701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P2_0 = 0x800000630801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P2_1 = 0x800004630701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P2_1 = 0x800004630801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P2_2 = 0x800008630701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P2_2 = 0x800008630801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P2_3 = 0x80000C630701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P2_3 = 0x80000C630801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P2_4 = 0x800010630701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P2_4 = 0x800010630801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P3_0 = 0x8000006307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P3_0 = 0x8000006308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P3_1 = 0x8000046307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P3_1 = 0x8000046308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P3_2 = 0x8000086307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P3_2 = 0x8000086308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P3_3 = 0x80000C6307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P3_3 = 0x80000C6308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P3_4 = 0x8000106307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P3_4 = 0x8000106308011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_0 = 0x800001630701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_0 = 0x800001630701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_0 = 0x800001630801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_1 = 0x800005630701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_1 = 0x800005630701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_1 = 0x800005630801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_2 = 0x800009630701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_2 = 0x800009630701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_2 = 0x800009630801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_3 = 0x80000D630701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_3 = 0x80000D630701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_3 = 0x80000D630801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_4 = 0x800011630701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_4 = 0x800011630701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_4 = 0x800011630801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P1_0 = 0x800001630701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P1_0 = 0x800001630801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P1_1 = 0x800005630701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P1_1 = 0x800005630801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P1_2 = 0x800009630701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P1_2 = 0x800009630801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P1_3 = 0x80000D630701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P1_3 = 0x80000D630801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P1_4 = 0x800011630701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P1_4 = 0x800011630801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P2_0 = 0x800001630701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P2_0 = 0x800001630801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P2_1 = 0x800005630701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P2_1 = 0x800005630801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P2_2 = 0x800009630701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P2_2 = 0x800009630801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P2_3 = 0x80000D630701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P2_3 = 0x80000D630801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P2_4 = 0x800011630701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P2_4 = 0x800011630801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P3_0 = 0x8000016307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P3_0 = 0x8000016308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P3_1 = 0x8000056307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P3_1 = 0x8000056308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P3_2 = 0x8000096307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P3_2 = 0x8000096308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P3_3 = 0x80000D6307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P3_3 = 0x80000D6308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P3_4 = 0x8000116307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P3_4 = 0x8000116308011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_0 = 0x800002630701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_0 = 0x800002630701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_0 = 0x800002630801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_1 = 0x800006630701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_1 = 0x800006630701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_1 = 0x800006630801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_2 = 0x80000A630701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_2 = 0x80000A630701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_2 = 0x80000A630801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_3 = 0x80000E630701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_3 = 0x80000E630701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_3 = 0x80000E630801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_4 = 0x800012630701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_4 = 0x800012630701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_4 = 0x800012630801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P1_0 = 0x800002630701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P1_0 = 0x800002630801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P1_1 = 0x800006630701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P1_1 = 0x800006630801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P1_2 = 0x80000A630701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P1_2 = 0x80000A630801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P1_3 = 0x80000E630701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P1_3 = 0x80000E630801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P1_4 = 0x800012630701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P1_4 = 0x800012630801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P2_0 = 0x800002630701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P2_0 = 0x800002630801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P2_1 = 0x800006630701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P2_1 = 0x800006630801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P2_2 = 0x80000A630701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P2_2 = 0x80000A630801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P2_3 = 0x80000E630701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P2_3 = 0x80000E630801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P2_4 = 0x800012630701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P2_4 = 0x800012630801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P3_0 = 0x8000026307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P3_0 = 0x8000026308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P3_1 = 0x8000066307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P3_1 = 0x8000066308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P3_2 = 0x80000A6307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P3_2 = 0x80000A6308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P3_3 = 0x80000E6307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P3_3 = 0x80000E6308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P3_4 = 0x8000126307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P3_4 = 0x8000126308011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_0 = 0x800003630701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_0 = 0x800003630701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_0 = 0x800003630801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_1 = 0x800007630701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_1 = 0x800007630701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_1 = 0x800007630801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_2 = 0x80000B630701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_2 = 0x80000B630701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_2 = 0x80000B630801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_3 = 0x80000F630701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_3 = 0x80000F630701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_3 = 0x80000F630801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_4 = 0x800013630701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_4 = 0x800013630701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_4 = 0x800013630801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P1_0 = 0x800003630701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P1_0 = 0x800003630801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P1_1 = 0x800007630701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P1_1 = 0x800007630801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P1_2 = 0x80000B630701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P1_2 = 0x80000B630801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P1_3 = 0x80000F630701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P1_3 = 0x80000F630801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P1_4 = 0x800013630701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P1_4 = 0x800013630801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P2_0 = 0x800003630701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P2_0 = 0x800003630801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P2_1 = 0x800007630701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P2_1 = 0x800007630801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P2_2 = 0x80000B630701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P2_2 = 0x80000B630801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P2_3 = 0x80000F630701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P2_3 = 0x80000F630801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P2_4 = 0x800013630701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P2_4 = 0x800013630801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P3_0 = 0x8000036307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P3_0 = 0x8000036308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P3_1 = 0x8000076307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P3_1 = 0x8000076308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P3_2 = 0x80000B6307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P3_2 = 0x80000B6308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P3_3 = 0x80000F6307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P3_3 = 0x80000F6308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P3_4 = 0x8000136307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P3_4 = 0x8000136308011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_0 = 0x800000640701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_0 = 0x800000640701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_0 = 0x800000640801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_1 = 0x800004640701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_1 = 0x800004640701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_1 = 0x800004640801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_2 = 0x800008640701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_2 = 0x800008640701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_2 = 0x800008640801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_3 = 0x80000C640701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_3 = 0x80000C640701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_3 = 0x80000C640801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_4 = 0x800010640701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_4 = 0x800010640701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_4 = 0x800010640801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P1_0 = 0x800000640701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P1_0 = 0x800000640801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P1_1 = 0x800004640701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P1_1 = 0x800004640801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P1_2 = 0x800008640701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P1_2 = 0x800008640801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P1_3 = 0x80000C640701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P1_3 = 0x80000C640801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P1_4 = 0x800010640701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P1_4 = 0x800010640801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P2_0 = 0x800000640701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P2_0 = 0x800000640801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P2_1 = 0x800004640701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P2_1 = 0x800004640801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P2_2 = 0x800008640701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P2_2 = 0x800008640801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P2_3 = 0x80000C640701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P2_3 = 0x80000C640801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P2_4 = 0x800010640701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P2_4 = 0x800010640801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P3_0 = 0x8000006407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P3_0 = 0x8000006408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P3_1 = 0x8000046407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P3_1 = 0x8000046408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P3_2 = 0x8000086407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P3_2 = 0x8000086408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P3_3 = 0x80000C6407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P3_3 = 0x80000C6408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P3_4 = 0x8000106407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P3_4 = 0x8000106408011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_0 = 0x800001640701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_0 = 0x800001640701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_0 = 0x800001640801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_1 = 0x800005640701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_1 = 0x800005640701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_1 = 0x800005640801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_2 = 0x800009640701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_2 = 0x800009640701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_2 = 0x800009640801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_3 = 0x80000D640701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_3 = 0x80000D640701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_3 = 0x80000D640801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_4 = 0x800011640701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_4 = 0x800011640701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_4 = 0x800011640801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P1_0 = 0x800001640701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P1_0 = 0x800001640801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P1_1 = 0x800005640701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P1_1 = 0x800005640801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P1_2 = 0x800009640701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P1_2 = 0x800009640801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P1_3 = 0x80000D640701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P1_3 = 0x80000D640801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P1_4 = 0x800011640701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P1_4 = 0x800011640801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P2_0 = 0x800001640701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P2_0 = 0x800001640801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P2_1 = 0x800005640701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P2_1 = 0x800005640801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P2_2 = 0x800009640701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P2_2 = 0x800009640801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P2_3 = 0x80000D640701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P2_3 = 0x80000D640801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P2_4 = 0x800011640701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P2_4 = 0x800011640801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P3_0 = 0x8000016407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P3_0 = 0x8000016408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P3_1 = 0x8000056407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P3_1 = 0x8000056408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P3_2 = 0x8000096407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P3_2 = 0x8000096408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P3_3 = 0x80000D6407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P3_3 = 0x80000D6408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P3_4 = 0x8000116407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P3_4 = 0x8000116408011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_0 = 0x800002640701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_0 = 0x800002640701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_0 = 0x800002640801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_1 = 0x800006640701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_1 = 0x800006640701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_1 = 0x800006640801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_2 = 0x80000A640701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_2 = 0x80000A640701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_2 = 0x80000A640801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_3 = 0x80000E640701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_3 = 0x80000E640701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_3 = 0x80000E640801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_4 = 0x800012640701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_4 = 0x800012640701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_4 = 0x800012640801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P1_0 = 0x800002640701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P1_0 = 0x800002640801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P1_1 = 0x800006640701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P1_1 = 0x800006640801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P1_2 = 0x80000A640701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P1_2 = 0x80000A640801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P1_3 = 0x80000E640701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P1_3 = 0x80000E640801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P1_4 = 0x800012640701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P1_4 = 0x800012640801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P2_0 = 0x800002640701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P2_0 = 0x800002640801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P2_1 = 0x800006640701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P2_1 = 0x800006640801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P2_2 = 0x80000A640701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P2_2 = 0x80000A640801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P2_3 = 0x80000E640701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P2_3 = 0x80000E640801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P2_4 = 0x800012640701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P2_4 = 0x800012640801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P3_0 = 0x8000026407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P3_0 = 0x8000026408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P3_1 = 0x8000066407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P3_1 = 0x8000066408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P3_2 = 0x80000A6407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P3_2 = 0x80000A6408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P3_3 = 0x80000E6407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P3_3 = 0x80000E6408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P3_4 = 0x8000126407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P3_4 = 0x8000126408011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_0 = 0x800003640701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_0 = 0x800003640701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_0 = 0x800003640801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_1 = 0x800007640701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_1 = 0x800007640701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_1 = 0x800007640801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_2 = 0x80000B640701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_2 = 0x80000B640701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_2 = 0x80000B640801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_3 = 0x80000F640701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_3 = 0x80000F640701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_3 = 0x80000F640801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_4 = 0x800013640701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_4 = 0x800013640701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_4 = 0x800013640801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P1_0 = 0x800003640701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P1_0 = 0x800003640801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P1_1 = 0x800007640701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P1_1 = 0x800007640801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P1_2 = 0x80000B640701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P1_2 = 0x80000B640801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P1_3 = 0x80000F640701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P1_3 = 0x80000F640801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P1_4 = 0x800013640701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P1_4 = 0x800013640801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P2_0 = 0x800003640701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P2_0 = 0x800003640801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P2_1 = 0x800007640701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P2_1 = 0x800007640801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P2_2 = 0x80000B640701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P2_2 = 0x80000B640801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P2_3 = 0x80000F640701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P2_3 = 0x80000F640801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P2_4 = 0x800013640701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P2_4 = 0x800013640801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P3_0 = 0x8000036407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P3_0 = 0x8000036408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P3_1 = 0x8000076407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P3_1 = 0x8000076408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P3_2 = 0x80000B6407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P3_2 = 0x80000B6408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P3_3 = 0x80000F6407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P3_3 = 0x80000F6408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P3_4 = 0x8000136407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P3_4 = 0x8000136408011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_0 = 0x800000650701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_0 = 0x800000650701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_0 = 0x800000650801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_1 = 0x800004650701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_1 = 0x800004650701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_1 = 0x800004650801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_2 = 0x800008650701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_2 = 0x800008650701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_2 = 0x800008650801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_3 = 0x80000C650701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_3 = 0x80000C650701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_3 = 0x80000C650801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_4 = 0x800010650701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_4 = 0x800010650701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_4 = 0x800010650801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P1_0 = 0x800000650701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P1_0 = 0x800000650801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P1_1 = 0x800004650701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P1_1 = 0x800004650801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P1_2 = 0x800008650701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P1_2 = 0x800008650801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P1_3 = 0x80000C650701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P1_3 = 0x80000C650801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P1_4 = 0x800010650701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P1_4 = 0x800010650801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P2_0 = 0x800000650701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P2_0 = 0x800000650801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P2_1 = 0x800004650701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P2_1 = 0x800004650801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P2_2 = 0x800008650701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P2_2 = 0x800008650801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P2_3 = 0x80000C650701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P2_3 = 0x80000C650801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P2_4 = 0x800010650701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P2_4 = 0x800010650801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P3_0 = 0x8000006507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P3_0 = 0x8000006508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P3_1 = 0x8000046507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P3_1 = 0x8000046508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P3_2 = 0x8000086507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P3_2 = 0x8000086508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P3_3 = 0x80000C6507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P3_3 = 0x80000C6508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P3_4 = 0x8000106507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P3_4 = 0x8000106508011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_0 = 0x800001650701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_0 = 0x800001650701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_0 = 0x800001650801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_1 = 0x800005650701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_1 = 0x800005650701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_1 = 0x800005650801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_2 = 0x800009650701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_2 = 0x800009650701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_2 = 0x800009650801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_3 = 0x80000D650701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_3 = 0x80000D650701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_3 = 0x80000D650801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_4 = 0x800011650701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_4 = 0x800011650701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_4 = 0x800011650801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P1_0 = 0x800001650701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P1_0 = 0x800001650801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P1_1 = 0x800005650701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P1_1 = 0x800005650801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P1_2 = 0x800009650701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P1_2 = 0x800009650801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P1_3 = 0x80000D650701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P1_3 = 0x80000D650801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P1_4 = 0x800011650701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P1_4 = 0x800011650801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P2_0 = 0x800001650701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P2_0 = 0x800001650801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P2_1 = 0x800005650701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P2_1 = 0x800005650801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P2_2 = 0x800009650701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P2_2 = 0x800009650801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P2_3 = 0x80000D650701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P2_3 = 0x80000D650801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P2_4 = 0x800011650701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P2_4 = 0x800011650801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P3_0 = 0x8000016507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P3_0 = 0x8000016508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P3_1 = 0x8000056507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P3_1 = 0x8000056508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P3_2 = 0x8000096507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P3_2 = 0x8000096508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P3_3 = 0x80000D6507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P3_3 = 0x80000D6508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P3_4 = 0x8000116507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P3_4 = 0x8000116508011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_0 = 0x800002650701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_0 = 0x800002650701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_0 = 0x800002650801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_1 = 0x800006650701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_1 = 0x800006650701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_1 = 0x800006650801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_2 = 0x80000A650701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_2 = 0x80000A650701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_2 = 0x80000A650801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_3 = 0x80000E650701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_3 = 0x80000E650701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_3 = 0x80000E650801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_4 = 0x800012650701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_4 = 0x800012650701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_4 = 0x800012650801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P1_0 = 0x800002650701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P1_0 = 0x800002650801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P1_1 = 0x800006650701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P1_1 = 0x800006650801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P1_2 = 0x80000A650701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P1_2 = 0x80000A650801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P1_3 = 0x80000E650701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P1_3 = 0x80000E650801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P1_4 = 0x800012650701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P1_4 = 0x800012650801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P2_0 = 0x800002650701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P2_0 = 0x800002650801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P2_1 = 0x800006650701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P2_1 = 0x800006650801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P2_2 = 0x80000A650701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P2_2 = 0x80000A650801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P2_3 = 0x80000E650701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P2_3 = 0x80000E650801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P2_4 = 0x800012650701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P2_4 = 0x800012650801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P3_0 = 0x8000026507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P3_0 = 0x8000026508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P3_1 = 0x8000066507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P3_1 = 0x8000066508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P3_2 = 0x80000A6507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P3_2 = 0x80000A6508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P3_3 = 0x80000E6507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P3_3 = 0x80000E6508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P3_4 = 0x8000126507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P3_4 = 0x8000126508011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_0 = 0x800003650701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_0 = 0x800003650701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_0 = 0x800003650801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_1 = 0x800007650701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_1 = 0x800007650701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_1 = 0x800007650801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_2 = 0x80000B650701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_2 = 0x80000B650701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_2 = 0x80000B650801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_3 = 0x80000F650701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_3 = 0x80000F650701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_3 = 0x80000F650801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_4 = 0x800013650701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_4 = 0x800013650701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_4 = 0x800013650801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P1_0 = 0x800003650701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P1_0 = 0x800003650801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P1_1 = 0x800007650701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P1_1 = 0x800007650801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P1_2 = 0x80000B650701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P1_2 = 0x80000B650801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P1_3 = 0x80000F650701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P1_3 = 0x80000F650801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P1_4 = 0x800013650701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P1_4 = 0x800013650801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P2_0 = 0x800003650701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P2_0 = 0x800003650801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P2_1 = 0x800007650701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P2_1 = 0x800007650801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P2_2 = 0x80000B650701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P2_2 = 0x80000B650801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P2_3 = 0x80000F650701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P2_3 = 0x80000F650801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P2_4 = 0x800013650701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P2_4 = 0x800013650801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P3_0 = 0x8000036507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P3_0 = 0x8000036508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P3_1 = 0x8000076507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P3_1 = 0x8000076508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P3_2 = 0x80000B6507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P3_2 = 0x80000B6508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P3_3 = 0x80000F6507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P3_3 = 0x80000F6508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P3_4 = 0x8000136507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P3_4 = 0x8000136508011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_0 = 0x800000660701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_0 = 0x800000660701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_0 = 0x800000660801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_1 = 0x800004660701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_1 = 0x800004660701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_1 = 0x800004660801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_2 = 0x800008660701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_2 = 0x800008660701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_2 = 0x800008660801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_3 = 0x80000C660701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_3 = 0x80000C660701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_3 = 0x80000C660801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_4 = 0x800010660701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_4 = 0x800010660701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_4 = 0x800010660801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P1_0 = 0x800000660701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P1_0 = 0x800000660801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P1_1 = 0x800004660701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P1_1 = 0x800004660801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P1_2 = 0x800008660701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P1_2 = 0x800008660801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P1_3 = 0x80000C660701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P1_3 = 0x80000C660801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P1_4 = 0x800010660701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P1_4 = 0x800010660801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P2_0 = 0x800000660701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P2_0 = 0x800000660801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P2_1 = 0x800004660701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P2_1 = 0x800004660801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P2_2 = 0x800008660701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P2_2 = 0x800008660801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P2_3 = 0x80000C660701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P2_3 = 0x80000C660801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P2_4 = 0x800010660701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P2_4 = 0x800010660801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P3_0 = 0x8000006607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P3_0 = 0x8000006608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P3_1 = 0x8000046607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P3_1 = 0x8000046608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P3_2 = 0x8000086607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P3_2 = 0x8000086608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P3_3 = 0x80000C6607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P3_3 = 0x80000C6608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P3_4 = 0x8000106607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P3_4 = 0x8000106608011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_0 = 0x800001660701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_0 = 0x800001660701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_0 = 0x800001660801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_1 = 0x800005660701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_1 = 0x800005660701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_1 = 0x800005660801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_2 = 0x800009660701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_2 = 0x800009660701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_2 = 0x800009660801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_3 = 0x80000D660701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_3 = 0x80000D660701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_3 = 0x80000D660801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_4 = 0x800011660701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_4 = 0x800011660701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_4 = 0x800011660801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P1_0 = 0x800001660701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P1_0 = 0x800001660801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P1_1 = 0x800005660701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P1_1 = 0x800005660801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P1_2 = 0x800009660701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P1_2 = 0x800009660801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P1_3 = 0x80000D660701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P1_3 = 0x80000D660801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P1_4 = 0x800011660701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P1_4 = 0x800011660801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P2_0 = 0x800001660701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P2_0 = 0x800001660801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P2_1 = 0x800005660701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P2_1 = 0x800005660801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P2_2 = 0x800009660701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P2_2 = 0x800009660801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P2_3 = 0x80000D660701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P2_3 = 0x80000D660801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P2_4 = 0x800011660701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P2_4 = 0x800011660801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P3_0 = 0x8000016607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P3_0 = 0x8000016608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P3_1 = 0x8000056607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P3_1 = 0x8000056608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P3_2 = 0x8000096607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P3_2 = 0x8000096608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P3_3 = 0x80000D6607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P3_3 = 0x80000D6608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P3_4 = 0x8000116607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P3_4 = 0x8000116608011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_0 = 0x800002660701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_0 = 0x800002660701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_0 = 0x800002660801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_1 = 0x800006660701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_1 = 0x800006660701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_1 = 0x800006660801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_2 = 0x80000A660701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_2 = 0x80000A660701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_2 = 0x80000A660801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_3 = 0x80000E660701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_3 = 0x80000E660701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_3 = 0x80000E660801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_4 = 0x800012660701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_4 = 0x800012660701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_4 = 0x800012660801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P1_0 = 0x800002660701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P1_0 = 0x800002660801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P1_1 = 0x800006660701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P1_1 = 0x800006660801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P1_2 = 0x80000A660701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P1_2 = 0x80000A660801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P1_3 = 0x80000E660701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P1_3 = 0x80000E660801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P1_4 = 0x800012660701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P1_4 = 0x800012660801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P2_0 = 0x800002660701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P2_0 = 0x800002660801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P2_1 = 0x800006660701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P2_1 = 0x800006660801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P2_2 = 0x80000A660701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P2_2 = 0x80000A660801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P2_3 = 0x80000E660701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P2_3 = 0x80000E660801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P2_4 = 0x800012660701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P2_4 = 0x800012660801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P3_0 = 0x8000026607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P3_0 = 0x8000026608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P3_1 = 0x8000066607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P3_1 = 0x8000066608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P3_2 = 0x80000A6607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P3_2 = 0x80000A6608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P3_3 = 0x80000E6607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P3_3 = 0x80000E6608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P3_4 = 0x8000126607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P3_4 = 0x8000126608011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_0 = 0x800003660701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_0 = 0x800003660701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_0 = 0x800003660801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_1 = 0x800007660701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_1 = 0x800007660701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_1 = 0x800007660801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_2 = 0x80000B660701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_2 = 0x80000B660701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_2 = 0x80000B660801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_3 = 0x80000F660701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_3 = 0x80000F660701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_3 = 0x80000F660801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_4 = 0x800013660701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_4 = 0x800013660701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_4 = 0x800013660801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P1_0 = 0x800003660701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P1_0 = 0x800003660801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P1_1 = 0x800007660701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P1_1 = 0x800007660801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P1_2 = 0x80000B660701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P1_2 = 0x80000B660801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P1_3 = 0x80000F660701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P1_3 = 0x80000F660801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P1_4 = 0x800013660701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P1_4 = 0x800013660801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P2_0 = 0x800003660701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P2_0 = 0x800003660801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P2_1 = 0x800007660701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P2_1 = 0x800007660801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P2_2 = 0x80000B660701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P2_2 = 0x80000B660801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P2_3 = 0x80000F660701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P2_3 = 0x80000F660801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P2_4 = 0x800013660701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P2_4 = 0x800013660801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P3_0 = 0x8000036607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P3_0 = 0x8000036608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P3_1 = 0x8000076607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P3_1 = 0x8000076608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P3_2 = 0x80000B6607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P3_2 = 0x80000B6608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P3_3 = 0x80000F6607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P3_3 = 0x80000F6608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P3_4 = 0x8000136607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P3_4 = 0x8000136608011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_0 = 0x800000670701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_0 = 0x800000670701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_0 = 0x800000670801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_1 = 0x800004670701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_1 = 0x800004670701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_1 = 0x800004670801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_2 = 0x800008670701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_2 = 0x800008670701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_2 = 0x800008670801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_3 = 0x80000C670701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_3 = 0x80000C670701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_3 = 0x80000C670801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_4 = 0x800010670701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_4 = 0x800010670701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_4 = 0x800010670801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P1_0 = 0x800000670701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P1_0 = 0x800000670801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P1_1 = 0x800004670701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P1_1 = 0x800004670801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P1_2 = 0x800008670701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P1_2 = 0x800008670801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P1_3 = 0x80000C670701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P1_3 = 0x80000C670801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P1_4 = 0x800010670701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P1_4 = 0x800010670801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P2_0 = 0x800000670701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P2_0 = 0x800000670801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P2_1 = 0x800004670701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P2_1 = 0x800004670801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P2_2 = 0x800008670701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P2_2 = 0x800008670801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P2_3 = 0x80000C670701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P2_3 = 0x80000C670801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P2_4 = 0x800010670701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P2_4 = 0x800010670801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P3_0 = 0x8000006707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P3_0 = 0x8000006708011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P3_1 = 0x8000046707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P3_1 = 0x8000046708011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P3_2 = 0x8000086707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P3_2 = 0x8000086708011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P3_3 = 0x80000C6707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P3_3 = 0x80000C6708011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P3_4 = 0x8000106707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P3_4 = 0x8000106708011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_0 = 0x800001670701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_0 = 0x800001670701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_0 = 0x800001670801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_1 = 0x800005670701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_1 = 0x800005670701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_1 = 0x800005670801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_2 = 0x800009670701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_2 = 0x800009670701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_2 = 0x800009670801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_3 = 0x80000D670701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_3 = 0x80000D670701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_3 = 0x80000D670801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_4 = 0x800011670701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_4 = 0x800011670701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_4 = 0x800011670801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P1_0 = 0x800001670701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P1_0 = 0x800001670801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P1_1 = 0x800005670701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P1_1 = 0x800005670801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P1_2 = 0x800009670701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P1_2 = 0x800009670801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P1_3 = 0x80000D670701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P1_3 = 0x80000D670801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P1_4 = 0x800011670701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P1_4 = 0x800011670801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P2_0 = 0x800001670701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P2_0 = 0x800001670801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P2_1 = 0x800005670701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P2_1 = 0x800005670801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P2_2 = 0x800009670701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P2_2 = 0x800009670801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P2_3 = 0x80000D670701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P2_3 = 0x80000D670801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P2_4 = 0x800011670701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P2_4 = 0x800011670801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P3_0 = 0x8000016707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P3_0 = 0x8000016708011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P3_1 = 0x8000056707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P3_1 = 0x8000056708011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P3_2 = 0x8000096707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P3_2 = 0x8000096708011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P3_3 = 0x80000D6707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P3_3 = 0x80000D6708011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P3_4 = 0x8000116707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P3_4 = 0x8000116708011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_0 = 0x800002670701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_0 = 0x800002670701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_0 = 0x800002670801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_1 = 0x800006670701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_1 = 0x800006670701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_1 = 0x800006670801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_2 = 0x80000A670701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_2 = 0x80000A670701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_2 = 0x80000A670801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_3 = 0x80000E670701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_3 = 0x80000E670701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_3 = 0x80000E670801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_4 = 0x800012670701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_4 = 0x800012670701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_4 = 0x800012670801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P1_0 = 0x800002670701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P1_0 = 0x800002670801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P1_1 = 0x800006670701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P1_1 = 0x800006670801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P1_2 = 0x80000A670701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P1_2 = 0x80000A670801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P1_3 = 0x80000E670701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P1_3 = 0x80000E670801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P1_4 = 0x800012670701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P1_4 = 0x800012670801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P2_0 = 0x800002670701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P2_0 = 0x800002670801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P2_1 = 0x800006670701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P2_1 = 0x800006670801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P2_2 = 0x80000A670701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P2_2 = 0x80000A670801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P2_3 = 0x80000E670701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P2_3 = 0x80000E670801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P2_4 = 0x800012670701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P2_4 = 0x800012670801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P3_0 = 0x8000026707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P3_0 = 0x8000026708011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P3_1 = 0x8000066707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P3_1 = 0x8000066708011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P3_2 = 0x80000A6707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P3_2 = 0x80000A6708011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P3_3 = 0x80000E6707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P3_3 = 0x80000E6708011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P3_4 = 0x8000126707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P3_4 = 0x8000126708011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_0 = 0x800003670701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_0 = 0x800003670701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_0 = 0x800003670801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_1 = 0x800007670701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_1 = 0x800007670701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_1 = 0x800007670801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_2 = 0x80000B670701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_2 = 0x80000B670701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_2 = 0x80000B670801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_3 = 0x80000F670701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_3 = 0x80000F670701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_3 = 0x80000F670801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_4 = 0x800013670701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_4 = 0x800013670701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_4 = 0x800013670801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P1_0 = 0x800003670701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P1_0 = 0x800003670801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P1_1 = 0x800007670701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P1_1 = 0x800007670801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P1_2 = 0x80000B670701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P1_2 = 0x80000B670801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P1_3 = 0x80000F670701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P1_3 = 0x80000F670801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P1_4 = 0x800013670701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P1_4 = 0x800013670801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P2_0 = 0x800003670701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P2_0 = 0x800003670801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P2_1 = 0x800007670701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P2_1 = 0x800007670801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P2_2 = 0x80000B670701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P2_2 = 0x80000B670801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P2_3 = 0x80000F670701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P2_3 = 0x80000F670801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P2_4 = 0x800013670701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P2_4 = 0x800013670801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P3_0 = 0x8000036707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P3_0 = 0x8000036708011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P3_1 = 0x8000076707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P3_1 = 0x8000076708011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P3_2 = 0x80000B6707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P3_2 = 0x80000B6708011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P3_3 = 0x80000F6707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P3_3 = 0x80000F6708011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P3_4 = 0x8000136707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P3_4 = 0x8000136708011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_0 = 0x800000680701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_0 = 0x800000680701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_0 = 0x800000680801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_1 = 0x800004680701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_1 = 0x800004680701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_1 = 0x800004680801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_2 = 0x800008680701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_2 = 0x800008680701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_2 = 0x800008680801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_3 = 0x80000C680701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_3 = 0x80000C680701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_3 = 0x80000C680801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_4 = 0x800010680701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_4 = 0x800010680701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_4 = 0x800010680801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P1_0 = 0x800000680701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P1_0 = 0x800000680801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P1_1 = 0x800004680701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P1_1 = 0x800004680801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P1_2 = 0x800008680701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P1_2 = 0x800008680801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P1_3 = 0x80000C680701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P1_3 = 0x80000C680801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P1_4 = 0x800010680701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P1_4 = 0x800010680801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P2_0 = 0x800000680701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P2_0 = 0x800000680801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P2_1 = 0x800004680701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P2_1 = 0x800004680801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P2_2 = 0x800008680701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P2_2 = 0x800008680801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P2_3 = 0x80000C680701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P2_3 = 0x80000C680801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P2_4 = 0x800010680701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P2_4 = 0x800010680801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P3_0 = 0x8000006807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P3_0 = 0x8000006808011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P3_1 = 0x8000046807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P3_1 = 0x8000046808011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P3_2 = 0x8000086807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P3_2 = 0x8000086808011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P3_3 = 0x80000C6807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P3_3 = 0x80000C6808011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P3_4 = 0x8000106807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P3_4 = 0x8000106808011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_0 = 0x800001680701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_0 = 0x800001680701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_0 = 0x800001680801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_1 = 0x800005680701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_1 = 0x800005680701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_1 = 0x800005680801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_2 = 0x800009680701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_2 = 0x800009680701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_2 = 0x800009680801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_3 = 0x80000D680701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_3 = 0x80000D680701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_3 = 0x80000D680801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_4 = 0x800011680701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_4 = 0x800011680701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_4 = 0x800011680801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P1_0 = 0x800001680701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P1_0 = 0x800001680801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P1_1 = 0x800005680701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P1_1 = 0x800005680801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P1_2 = 0x800009680701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P1_2 = 0x800009680801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P1_3 = 0x80000D680701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P1_3 = 0x80000D680801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P1_4 = 0x800011680701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P1_4 = 0x800011680801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P2_0 = 0x800001680701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P2_0 = 0x800001680801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P2_1 = 0x800005680701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P2_1 = 0x800005680801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P2_2 = 0x800009680701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P2_2 = 0x800009680801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P2_3 = 0x80000D680701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P2_3 = 0x80000D680801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P2_4 = 0x800011680701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P2_4 = 0x800011680801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P3_0 = 0x8000016807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P3_0 = 0x8000016808011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P3_1 = 0x8000056807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P3_1 = 0x8000056808011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P3_2 = 0x8000096807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P3_2 = 0x8000096808011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P3_3 = 0x80000D6807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P3_3 = 0x80000D6808011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P3_4 = 0x8000116807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P3_4 = 0x8000116808011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_0 = 0x800002680701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_0 = 0x800002680701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_0 = 0x800002680801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_1 = 0x800006680701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_1 = 0x800006680701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_1 = 0x800006680801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_2 = 0x80000A680701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_2 = 0x80000A680701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_2 = 0x80000A680801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_3 = 0x80000E680701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_3 = 0x80000E680701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_3 = 0x80000E680801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_4 = 0x800012680701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_4 = 0x800012680701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_4 = 0x800012680801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P1_0 = 0x800002680701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P1_0 = 0x800002680801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P1_1 = 0x800006680701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P1_1 = 0x800006680801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P1_2 = 0x80000A680701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P1_2 = 0x80000A680801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P1_3 = 0x80000E680701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P1_3 = 0x80000E680801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P1_4 = 0x800012680701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P1_4 = 0x800012680801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P2_0 = 0x800002680701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P2_0 = 0x800002680801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P2_1 = 0x800006680701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P2_1 = 0x800006680801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P2_2 = 0x80000A680701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P2_2 = 0x80000A680801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P2_3 = 0x80000E680701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P2_3 = 0x80000E680801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P2_4 = 0x800012680701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P2_4 = 0x800012680801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P3_0 = 0x8000026807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P3_0 = 0x8000026808011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P3_1 = 0x8000066807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P3_1 = 0x8000066808011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P3_2 = 0x80000A6807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P3_2 = 0x80000A6808011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P3_3 = 0x80000E6807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P3_3 = 0x80000E6808011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P3_4 = 0x8000126807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P3_4 = 0x8000126808011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_0 = 0x800003680701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_0 = 0x800003680701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_0 = 0x800003680801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_1 = 0x800007680701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_1 = 0x800007680701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_1 = 0x800007680801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_2 = 0x80000B680701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_2 = 0x80000B680701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_2 = 0x80000B680801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_3 = 0x80000F680701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_3 = 0x80000F680701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_3 = 0x80000F680801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_4 = 0x800013680701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_4 = 0x800013680701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_4 = 0x800013680801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P1_0 = 0x800003680701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P1_0 = 0x800003680801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P1_1 = 0x800007680701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P1_1 = 0x800007680801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P1_2 = 0x80000B680701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P1_2 = 0x80000B680801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P1_3 = 0x80000F680701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P1_3 = 0x80000F680801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P1_4 = 0x800013680701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P1_4 = 0x800013680801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P2_0 = 0x800003680701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P2_0 = 0x800003680801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P2_1 = 0x800007680701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P2_1 = 0x800007680801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P2_2 = 0x80000B680701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P2_2 = 0x80000B680801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P2_3 = 0x80000F680701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P2_3 = 0x80000F680801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P2_4 = 0x800013680701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P2_4 = 0x800013680801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P3_0 = 0x8000036807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P3_0 = 0x8000036808011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P3_1 = 0x8000076807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P3_1 = 0x8000076808011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P3_2 = 0x80000B6807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P3_2 = 0x80000B6808011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P3_3 = 0x80000F6807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P3_3 = 0x80000F6808011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P3_4 = 0x8000136807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P3_4 = 0x8000136808011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_0 = 0x800000690701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_0 = 0x800000690701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_0 = 0x800000690801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_1 = 0x800004690701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_1 = 0x800004690701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_1 = 0x800004690801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_2 = 0x800008690701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_2 = 0x800008690701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_2 = 0x800008690801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_3 = 0x80000C690701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_3 = 0x80000C690701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_3 = 0x80000C690801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_4 = 0x800010690701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_4 = 0x800010690701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_4 = 0x800010690801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P1_0 = 0x800000690701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P1_0 = 0x800000690801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P1_1 = 0x800004690701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P1_1 = 0x800004690801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P1_2 = 0x800008690701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P1_2 = 0x800008690801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P1_3 = 0x80000C690701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P1_3 = 0x80000C690801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P1_4 = 0x800010690701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P1_4 = 0x800010690801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P2_0 = 0x800000690701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P2_0 = 0x800000690801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P2_1 = 0x800004690701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P2_1 = 0x800004690801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P2_2 = 0x800008690701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P2_2 = 0x800008690801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P2_3 = 0x80000C690701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P2_3 = 0x80000C690801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P2_4 = 0x800010690701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P2_4 = 0x800010690801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P3_0 = 0x8000006907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P3_0 = 0x8000006908011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P3_1 = 0x8000046907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P3_1 = 0x8000046908011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P3_2 = 0x8000086907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P3_2 = 0x8000086908011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P3_3 = 0x80000C6907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P3_3 = 0x80000C6908011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P3_4 = 0x8000106907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P3_4 = 0x8000106908011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_0 = 0x800001690701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_0 = 0x800001690701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_0 = 0x800001690801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_1 = 0x800005690701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_1 = 0x800005690701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_1 = 0x800005690801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_2 = 0x800009690701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_2 = 0x800009690701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_2 = 0x800009690801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_3 = 0x80000D690701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_3 = 0x80000D690701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_3 = 0x80000D690801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_4 = 0x800011690701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_4 = 0x800011690701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_4 = 0x800011690801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P1_0 = 0x800001690701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P1_0 = 0x800001690801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P1_1 = 0x800005690701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P1_1 = 0x800005690801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P1_2 = 0x800009690701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P1_2 = 0x800009690801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P1_3 = 0x80000D690701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P1_3 = 0x80000D690801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P1_4 = 0x800011690701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P1_4 = 0x800011690801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P2_0 = 0x800001690701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P2_0 = 0x800001690801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P2_1 = 0x800005690701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P2_1 = 0x800005690801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P2_2 = 0x800009690701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P2_2 = 0x800009690801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P2_3 = 0x80000D690701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P2_3 = 0x80000D690801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P2_4 = 0x800011690701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P2_4 = 0x800011690801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P3_0 = 0x8000016907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P3_0 = 0x8000016908011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P3_1 = 0x8000056907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P3_1 = 0x8000056908011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P3_2 = 0x8000096907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P3_2 = 0x8000096908011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P3_3 = 0x80000D6907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P3_3 = 0x80000D6908011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P3_4 = 0x8000116907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P3_4 = 0x8000116908011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_0 = 0x800002690701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_0 = 0x800002690701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_0 = 0x800002690801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_1 = 0x800006690701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_1 = 0x800006690701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_1 = 0x800006690801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_2 = 0x80000A690701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_2 = 0x80000A690701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_2 = 0x80000A690801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_3 = 0x80000E690701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_3 = 0x80000E690701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_3 = 0x80000E690801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_4 = 0x800012690701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_4 = 0x800012690701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_4 = 0x800012690801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P1_0 = 0x800002690701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P1_0 = 0x800002690801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P1_1 = 0x800006690701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P1_1 = 0x800006690801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P1_2 = 0x80000A690701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P1_2 = 0x80000A690801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P1_3 = 0x80000E690701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P1_3 = 0x80000E690801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P1_4 = 0x800012690701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P1_4 = 0x800012690801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P2_0 = 0x800002690701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P2_0 = 0x800002690801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P2_1 = 0x800006690701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P2_1 = 0x800006690801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P2_2 = 0x80000A690701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P2_2 = 0x80000A690801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P2_3 = 0x80000E690701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P2_3 = 0x80000E690801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P2_4 = 0x800012690701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P2_4 = 0x800012690801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P3_0 = 0x8000026907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P3_0 = 0x8000026908011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P3_1 = 0x8000066907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P3_1 = 0x8000066908011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P3_2 = 0x80000A6907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P3_2 = 0x80000A6908011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P3_3 = 0x80000E6907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P3_3 = 0x80000E6908011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P3_4 = 0x8000126907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P3_4 = 0x8000126908011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_0 = 0x800003690701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_0 = 0x800003690701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_0 = 0x800003690801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_1 = 0x800007690701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_1 = 0x800007690701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_1 = 0x800007690801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_2 = 0x80000B690701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_2 = 0x80000B690701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_2 = 0x80000B690801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_3 = 0x80000F690701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_3 = 0x80000F690701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_3 = 0x80000F690801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_4 = 0x800013690701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_4 = 0x800013690701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_4 = 0x800013690801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P1_0 = 0x800003690701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P1_0 = 0x800003690801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P1_1 = 0x800007690701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P1_1 = 0x800007690801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P1_2 = 0x80000B690701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P1_2 = 0x80000B690801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P1_3 = 0x80000F690701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P1_3 = 0x80000F690801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P1_4 = 0x800013690701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P1_4 = 0x800013690801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P2_0 = 0x800003690701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P2_0 = 0x800003690801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P2_1 = 0x800007690701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P2_1 = 0x800007690801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P2_2 = 0x80000B690701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P2_2 = 0x80000B690801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P2_3 = 0x80000F690701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P2_3 = 0x80000F690801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P2_4 = 0x800013690701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P2_4 = 0x800013690801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P3_0 = 0x8000036907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P3_0 = 0x8000036908011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P3_1 = 0x8000076907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P3_1 = 0x8000076908011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P3_2 = 0x80000B6907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P3_2 = 0x80000B6908011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P3_3 = 0x80000F6907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P3_3 = 0x80000F6908011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P3_4 = 0x8000136907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P3_4 = 0x8000136908011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_0 = 0x800000700701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_0 = 0x800000700701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_0 = 0x800000700801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_1 = 0x800004700701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_1 = 0x800004700701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_1 = 0x800004700801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_2 = 0x800008700701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_2 = 0x800008700701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_2 = 0x800008700801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_3 = 0x80000C700701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_3 = 0x80000C700701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_3 = 0x80000C700801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_4 = 0x800010700701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_4 = 0x800010700701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_4 = 0x800010700801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_TIMING_REFERENCE0_P1_0 = 0x800000700701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_TIMING_REFERENCE0_P1_0 = 0x800000700801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_TIMING_REFERENCE0_P1_1 = 0x800004700701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_TIMING_REFERENCE0_P1_1 = 0x800004700801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_TIMING_REFERENCE0_P1_2 = 0x800008700701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_TIMING_REFERENCE0_P1_2 = 0x800008700801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_TIMING_REFERENCE0_P1_3 = 0x80000C700701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_TIMING_REFERENCE0_P1_3 = 0x80000C700801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_TIMING_REFERENCE0_P1_4 = 0x800010700701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_TIMING_REFERENCE0_P1_4 = 0x800010700801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_TIMING_REFERENCE0_P2_0 = 0x800000700701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_TIMING_REFERENCE0_P2_0 = 0x800000700801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_TIMING_REFERENCE0_P2_1 = 0x800004700701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_TIMING_REFERENCE0_P2_1 = 0x800004700801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_TIMING_REFERENCE0_P2_2 = 0x800008700701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_TIMING_REFERENCE0_P2_2 = 0x800008700801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_TIMING_REFERENCE0_P2_3 = 0x80000C700701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_TIMING_REFERENCE0_P2_3 = 0x80000C700801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_TIMING_REFERENCE0_P2_4 = 0x800010700701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_TIMING_REFERENCE0_P2_4 = 0x800010700801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_TIMING_REFERENCE0_P3_0 = 0x8000007007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_TIMING_REFERENCE0_P3_0 = 0x8000007008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_TIMING_REFERENCE0_P3_1 = 0x8000047007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_TIMING_REFERENCE0_P3_1 = 0x8000047008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_TIMING_REFERENCE0_P3_2 = 0x8000087007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_TIMING_REFERENCE0_P3_2 = 0x8000087008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_TIMING_REFERENCE0_P3_3 = 0x80000C7007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_TIMING_REFERENCE0_P3_3 = 0x80000C7008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_TIMING_REFERENCE0_P3_4 = 0x8000107007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_TIMING_REFERENCE0_P3_4 = 0x8000107008011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_0 = 0x800000710701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_0 = 0x800000710701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_0 = 0x800000710801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_1 = 0x800004710701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_1 = 0x800004710701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_1 = 0x800004710801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_2 = 0x800008710701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_2 = 0x800008710701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_2 = 0x800008710801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_3 = 0x80000C710701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_3 = 0x80000C710701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_3 = 0x80000C710801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_4 = 0x800010710701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_4 = 0x800010710701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_4 = 0x800010710801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_TIMING_REFERENCE1_P1_0 = 0x800000710701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_TIMING_REFERENCE1_P1_0 = 0x800000710801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_TIMING_REFERENCE1_P1_1 = 0x800004710701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_TIMING_REFERENCE1_P1_1 = 0x800004710801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_TIMING_REFERENCE1_P1_2 = 0x800008710701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_TIMING_REFERENCE1_P1_2 = 0x800008710801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_TIMING_REFERENCE1_P1_3 = 0x80000C710701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_TIMING_REFERENCE1_P1_3 = 0x80000C710801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_READ_TIMING_REFERENCE1_P1_4 = 0x800010710701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_READ_TIMING_REFERENCE1_P1_4 = 0x800010710801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_TIMING_REFERENCE1_P2_0 = 0x800000710701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_TIMING_REFERENCE1_P2_0 = 0x800000710801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_TIMING_REFERENCE1_P2_1 = 0x800004710701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_TIMING_REFERENCE1_P2_1 = 0x800004710801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_TIMING_REFERENCE1_P2_2 = 0x800008710701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_TIMING_REFERENCE1_P2_2 = 0x800008710801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_TIMING_REFERENCE1_P2_3 = 0x80000C710701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_TIMING_REFERENCE1_P2_3 = 0x80000C710801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_READ_TIMING_REFERENCE1_P2_4 = 0x800010710701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_READ_TIMING_REFERENCE1_P2_4 = 0x800010710801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_TIMING_REFERENCE1_P3_0 = 0x8000007107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_TIMING_REFERENCE1_P3_0 = 0x8000007108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_TIMING_REFERENCE1_P3_1 = 0x8000047107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_TIMING_REFERENCE1_P3_1 = 0x8000047108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_TIMING_REFERENCE1_P3_2 = 0x8000087107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_TIMING_REFERENCE1_P3_2 = 0x8000087108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_TIMING_REFERENCE1_P3_3 = 0x80000C7107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_TIMING_REFERENCE1_P3_3 = 0x80000C7108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_READ_TIMING_REFERENCE1_P3_4 = 0x8000107107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_READ_TIMING_REFERENCE1_P3_4 = 0x8000107108011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_0 = 0x800000060701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RX_CONFIG0_P0_0 = 0x800000060701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RX_CONFIG0_P0_0 = 0x800000060801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_1 = 0x800004060701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RX_CONFIG0_P0_1 = 0x800004060701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RX_CONFIG0_P0_1 = 0x800004060801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_2 = 0x800008060701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RX_CONFIG0_P0_2 = 0x800008060701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RX_CONFIG0_P0_2 = 0x800008060801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_3 = 0x80000C060701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RX_CONFIG0_P0_3 = 0x80000C060701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RX_CONFIG0_P0_3 = 0x80000C060801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_4 = 0x800010060701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_RX_CONFIG0_P0_4 = 0x800010060701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_RX_CONFIG0_P0_4 = 0x800010060801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RX_CONFIG0_P1_0 = 0x800000060701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RX_CONFIG0_P1_0 = 0x800000060801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RX_CONFIG0_P1_1 = 0x800004060701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RX_CONFIG0_P1_1 = 0x800004060801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RX_CONFIG0_P1_2 = 0x800008060701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RX_CONFIG0_P1_2 = 0x800008060801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RX_CONFIG0_P1_3 = 0x80000C060701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RX_CONFIG0_P1_3 = 0x80000C060801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_RX_CONFIG0_P1_4 = 0x800010060701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_RX_CONFIG0_P1_4 = 0x800010060801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RX_CONFIG0_P2_0 = 0x800000060701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RX_CONFIG0_P2_0 = 0x800000060801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RX_CONFIG0_P2_1 = 0x800004060701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RX_CONFIG0_P2_1 = 0x800004060801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RX_CONFIG0_P2_2 = 0x800008060701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RX_CONFIG0_P2_2 = 0x800008060801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RX_CONFIG0_P2_3 = 0x80000C060701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RX_CONFIG0_P2_3 = 0x80000C060801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_RX_CONFIG0_P2_4 = 0x800010060701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_RX_CONFIG0_P2_4 = 0x800010060801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RX_CONFIG0_P3_0 = 0x8000000607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RX_CONFIG0_P3_0 = 0x8000000608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RX_CONFIG0_P3_1 = 0x8000040607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RX_CONFIG0_P3_1 = 0x8000040608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RX_CONFIG0_P3_2 = 0x8000080607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RX_CONFIG0_P3_2 = 0x8000080608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RX_CONFIG0_P3_3 = 0x80000C0607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RX_CONFIG0_P3_3 = 0x80000C0608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_RX_CONFIG0_P3_4 = 0x8000100607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_RX_CONFIG0_P3_4 = 0x8000100608011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_0 = 0x800000070701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_SYSCLK_PR0_P0_0 = 0x800000070701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_SYSCLK_PR0_P0_0 = 0x800000070801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_1 = 0x800004070701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_SYSCLK_PR0_P0_1 = 0x800004070701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_SYSCLK_PR0_P0_1 = 0x800004070801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_2 = 0x800008070701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_SYSCLK_PR0_P0_2 = 0x800008070701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_SYSCLK_PR0_P0_2 = 0x800008070801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_3 = 0x80000C070701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_SYSCLK_PR0_P0_3 = 0x80000C070701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_SYSCLK_PR0_P0_3 = 0x80000C070801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_4 = 0x800010070701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_SYSCLK_PR0_P0_4 = 0x800010070701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_SYSCLK_PR0_P0_4 = 0x800010070801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_SYSCLK_PR0_P1_0 = 0x800000070701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_SYSCLK_PR0_P1_0 = 0x800000070801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_SYSCLK_PR0_P1_1 = 0x800004070701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_SYSCLK_PR0_P1_1 = 0x800004070801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_SYSCLK_PR0_P1_2 = 0x800008070701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_SYSCLK_PR0_P1_2 = 0x800008070801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_SYSCLK_PR0_P1_3 = 0x80000C070701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_SYSCLK_PR0_P1_3 = 0x80000C070801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_SYSCLK_PR0_P1_4 = 0x800010070701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_SYSCLK_PR0_P1_4 = 0x800010070801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_SYSCLK_PR0_P2_0 = 0x800000070701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_SYSCLK_PR0_P2_0 = 0x800000070801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_SYSCLK_PR0_P2_1 = 0x800004070701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_SYSCLK_PR0_P2_1 = 0x800004070801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_SYSCLK_PR0_P2_2 = 0x800008070701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_SYSCLK_PR0_P2_2 = 0x800008070801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_SYSCLK_PR0_P2_3 = 0x80000C070701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_SYSCLK_PR0_P2_3 = 0x80000C070801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_SYSCLK_PR0_P2_4 = 0x800010070701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_SYSCLK_PR0_P2_4 = 0x800010070801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_SYSCLK_PR0_P3_0 = 0x8000000707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_SYSCLK_PR0_P3_0 = 0x8000000708011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_SYSCLK_PR0_P3_1 = 0x8000040707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_SYSCLK_PR0_P3_1 = 0x8000040708011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_SYSCLK_PR0_P3_2 = 0x8000080707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_SYSCLK_PR0_P3_2 = 0x8000080708011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_SYSCLK_PR0_P3_3 = 0x80000C0707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_SYSCLK_PR0_P3_3 = 0x80000C0708011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_SYSCLK_PR0_P3_4 = 0x8000100707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_SYSCLK_PR0_P3_4 = 0x8000100708011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_0 = 0x8000007F0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_SYSCLK_PR1_P0_0 = 0x8000007F0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_SYSCLK_PR1_P0_0 = 0x8000007F0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_1 = 0x8000047F0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_SYSCLK_PR1_P0_1 = 0x8000047F0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_SYSCLK_PR1_P0_1 = 0x8000047F0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_2 = 0x8000087F0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_SYSCLK_PR1_P0_2 = 0x8000087F0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_SYSCLK_PR1_P0_2 = 0x8000087F0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_3 = 0x80000C7F0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_SYSCLK_PR1_P0_3 = 0x80000C7F0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_SYSCLK_PR1_P0_3 = 0x80000C7F0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_4 = 0x8000107F0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_SYSCLK_PR1_P0_4 = 0x8000107F0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_SYSCLK_PR1_P0_4 = 0x8000107F0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_SYSCLK_PR1_P1_0 = 0x8000007F0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_SYSCLK_PR1_P1_0 = 0x8000007F0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_SYSCLK_PR1_P1_1 = 0x8000047F0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_SYSCLK_PR1_P1_1 = 0x8000047F0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_SYSCLK_PR1_P1_2 = 0x8000087F0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_SYSCLK_PR1_P1_2 = 0x8000087F0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_SYSCLK_PR1_P1_3 = 0x80000C7F0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_SYSCLK_PR1_P1_3 = 0x80000C7F0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_SYSCLK_PR1_P1_4 = 0x8000107F0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_SYSCLK_PR1_P1_4 = 0x8000107F0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_SYSCLK_PR1_P2_0 = 0x8000007F0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_SYSCLK_PR1_P2_0 = 0x8000007F0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_SYSCLK_PR1_P2_1 = 0x8000047F0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_SYSCLK_PR1_P2_1 = 0x8000047F0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_SYSCLK_PR1_P2_2 = 0x8000087F0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_SYSCLK_PR1_P2_2 = 0x8000087F0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_SYSCLK_PR1_P2_3 = 0x80000C7F0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_SYSCLK_PR1_P2_3 = 0x80000C7F0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_SYSCLK_PR1_P2_4 = 0x8000107F0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_SYSCLK_PR1_P2_4 = 0x8000107F0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_SYSCLK_PR1_P3_0 = 0x8000007F07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_SYSCLK_PR1_P3_0 = 0x8000007F08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_SYSCLK_PR1_P3_1 = 0x8000047F07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_SYSCLK_PR1_P3_1 = 0x8000047F08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_SYSCLK_PR1_P3_2 = 0x8000087F07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_SYSCLK_PR1_P3_2 = 0x8000087F08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_SYSCLK_PR1_P3_3 = 0x80000C7F07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_SYSCLK_PR1_P3_3 = 0x80000C7F08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_SYSCLK_PR1_P3_4 = 0x8000107F07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_SYSCLK_PR1_P3_4 = 0x8000107F08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_0 = 0x800000730701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_0 = 0x800000730701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_0 = 0x800000730801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_1 = 0x800004730701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_1 = 0x800004730701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_1 = 0x800004730801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_2 = 0x800008730701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_2 = 0x800008730701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_2 = 0x800008730801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_3 = 0x80000C730701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_3 = 0x80000C730701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_3 = 0x80000C730801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_4 = 0x800010730701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_4 = 0x800010730701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_4 = 0x800010730801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_SYSCLK_PR_VALUE_P1_0 = 0x800000730701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_SYSCLK_PR_VALUE_P1_0 = 0x800000730801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_SYSCLK_PR_VALUE_P1_1 = 0x800004730701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_SYSCLK_PR_VALUE_P1_1 = 0x800004730801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_SYSCLK_PR_VALUE_P1_2 = 0x800008730701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_SYSCLK_PR_VALUE_P1_2 = 0x800008730801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_SYSCLK_PR_VALUE_P1_3 = 0x80000C730701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_SYSCLK_PR_VALUE_P1_3 = 0x80000C730801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_SYSCLK_PR_VALUE_P1_4 = 0x800010730701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_SYSCLK_PR_VALUE_P1_4 = 0x800010730801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_SYSCLK_PR_VALUE_P2_0 = 0x800000730701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_SYSCLK_PR_VALUE_P2_0 = 0x800000730801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_SYSCLK_PR_VALUE_P2_1 = 0x800004730701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_SYSCLK_PR_VALUE_P2_1 = 0x800004730801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_SYSCLK_PR_VALUE_P2_2 = 0x800008730701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_SYSCLK_PR_VALUE_P2_2 = 0x800008730801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_SYSCLK_PR_VALUE_P2_3 = 0x80000C730701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_SYSCLK_PR_VALUE_P2_3 = 0x80000C730801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_SYSCLK_PR_VALUE_P2_4 = 0x800010730701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_SYSCLK_PR_VALUE_P2_4 = 0x800010730801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_SYSCLK_PR_VALUE_P3_0 = 0x8000007307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_SYSCLK_PR_VALUE_P3_0 = 0x8000007308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_SYSCLK_PR_VALUE_P3_1 = 0x8000047307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_SYSCLK_PR_VALUE_P3_1 = 0x8000047308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_SYSCLK_PR_VALUE_P3_2 = 0x8000087307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_SYSCLK_PR_VALUE_P3_2 = 0x8000087308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_SYSCLK_PR_VALUE_P3_3 = 0x80000C7307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_SYSCLK_PR_VALUE_P3_3 = 0x80000C7308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_SYSCLK_PR_VALUE_P3_4 = 0x8000107307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_SYSCLK_PR_VALUE_P3_4 = 0x8000107308011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_0 = 0x800000050701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WRCLK_EN_RP0_P0_0 = 0x800000050701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WRCLK_EN_RP0_P0_0 = 0x800000050801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_1 = 0x800004050701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WRCLK_EN_RP0_P0_1 = 0x800004050701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WRCLK_EN_RP0_P0_1 = 0x800004050801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_2 = 0x800008050701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WRCLK_EN_RP0_P0_2 = 0x800008050701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WRCLK_EN_RP0_P0_2 = 0x800008050801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_3 = 0x80000C050701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WRCLK_EN_RP0_P0_3 = 0x80000C050701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WRCLK_EN_RP0_P0_3 = 0x80000C050801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_4 = 0x800010050701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WRCLK_EN_RP0_P0_4 = 0x800010050701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WRCLK_EN_RP0_P0_4 = 0x800010050801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WRCLK_EN_RP0_P1_0 = 0x800000050701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WRCLK_EN_RP0_P1_0 = 0x800000050801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WRCLK_EN_RP0_P1_1 = 0x800004050701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WRCLK_EN_RP0_P1_1 = 0x800004050801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WRCLK_EN_RP0_P1_2 = 0x800008050701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WRCLK_EN_RP0_P1_2 = 0x800008050801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WRCLK_EN_RP0_P1_3 = 0x80000C050701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WRCLK_EN_RP0_P1_3 = 0x80000C050801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WRCLK_EN_RP0_P1_4 = 0x800010050701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WRCLK_EN_RP0_P1_4 = 0x800010050801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WRCLK_EN_RP0_P2_0 = 0x800000050701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WRCLK_EN_RP0_P2_0 = 0x800000050801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WRCLK_EN_RP0_P2_1 = 0x800004050701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WRCLK_EN_RP0_P2_1 = 0x800004050801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WRCLK_EN_RP0_P2_2 = 0x800008050701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WRCLK_EN_RP0_P2_2 = 0x800008050801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WRCLK_EN_RP0_P2_3 = 0x80000C050701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WRCLK_EN_RP0_P2_3 = 0x80000C050801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WRCLK_EN_RP0_P2_4 = 0x800010050701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WRCLK_EN_RP0_P2_4 = 0x800010050801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WRCLK_EN_RP0_P3_0 = 0x8000000507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WRCLK_EN_RP0_P3_0 = 0x8000000508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WRCLK_EN_RP0_P3_1 = 0x8000040507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WRCLK_EN_RP0_P3_1 = 0x8000040508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WRCLK_EN_RP0_P3_2 = 0x8000080507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WRCLK_EN_RP0_P3_2 = 0x8000080508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WRCLK_EN_RP0_P3_3 = 0x80000C0507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WRCLK_EN_RP0_P3_3 = 0x80000C0508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WRCLK_EN_RP0_P3_4 = 0x8000100507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WRCLK_EN_RP0_P3_4 = 0x8000100508011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_0 = 0x800001050701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WRCLK_EN_RP1_P0_0 = 0x800001050701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WRCLK_EN_RP1_P0_0 = 0x800001050801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_1 = 0x800005050701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WRCLK_EN_RP1_P0_1 = 0x800005050701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WRCLK_EN_RP1_P0_1 = 0x800005050801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_2 = 0x800009050701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WRCLK_EN_RP1_P0_2 = 0x800009050701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WRCLK_EN_RP1_P0_2 = 0x800009050801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_3 = 0x80000D050701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WRCLK_EN_RP1_P0_3 = 0x80000D050701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WRCLK_EN_RP1_P0_3 = 0x80000D050801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_4 = 0x800011050701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WRCLK_EN_RP1_P0_4 = 0x800011050701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WRCLK_EN_RP1_P0_4 = 0x800011050801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WRCLK_EN_RP1_P1_0 = 0x800001050701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WRCLK_EN_RP1_P1_0 = 0x800001050801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WRCLK_EN_RP1_P1_1 = 0x800005050701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WRCLK_EN_RP1_P1_1 = 0x800005050801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WRCLK_EN_RP1_P1_2 = 0x800009050701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WRCLK_EN_RP1_P1_2 = 0x800009050801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WRCLK_EN_RP1_P1_3 = 0x80000D050701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WRCLK_EN_RP1_P1_3 = 0x80000D050801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WRCLK_EN_RP1_P1_4 = 0x800011050701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WRCLK_EN_RP1_P1_4 = 0x800011050801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WRCLK_EN_RP1_P2_0 = 0x800001050701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WRCLK_EN_RP1_P2_0 = 0x800001050801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WRCLK_EN_RP1_P2_1 = 0x800005050701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WRCLK_EN_RP1_P2_1 = 0x800005050801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WRCLK_EN_RP1_P2_2 = 0x800009050701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WRCLK_EN_RP1_P2_2 = 0x800009050801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WRCLK_EN_RP1_P2_3 = 0x80000D050701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WRCLK_EN_RP1_P2_3 = 0x80000D050801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WRCLK_EN_RP1_P2_4 = 0x800011050701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WRCLK_EN_RP1_P2_4 = 0x800011050801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WRCLK_EN_RP1_P3_0 = 0x8000010507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WRCLK_EN_RP1_P3_0 = 0x8000010508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WRCLK_EN_RP1_P3_1 = 0x8000050507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WRCLK_EN_RP1_P3_1 = 0x8000050508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WRCLK_EN_RP1_P3_2 = 0x8000090507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WRCLK_EN_RP1_P3_2 = 0x8000090508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WRCLK_EN_RP1_P3_3 = 0x80000D0507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WRCLK_EN_RP1_P3_3 = 0x80000D0508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WRCLK_EN_RP1_P3_4 = 0x8000110507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WRCLK_EN_RP1_P3_4 = 0x8000110508011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_0 = 0x800002050701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WRCLK_EN_RP2_P0_0 = 0x800002050701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WRCLK_EN_RP2_P0_0 = 0x800002050801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_1 = 0x800006050701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WRCLK_EN_RP2_P0_1 = 0x800006050701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WRCLK_EN_RP2_P0_1 = 0x800006050801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_2 = 0x80000A050701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WRCLK_EN_RP2_P0_2 = 0x80000A050701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WRCLK_EN_RP2_P0_2 = 0x80000A050801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_3 = 0x80000E050701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WRCLK_EN_RP2_P0_3 = 0x80000E050701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WRCLK_EN_RP2_P0_3 = 0x80000E050801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_4 = 0x800012050701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WRCLK_EN_RP2_P0_4 = 0x800012050701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WRCLK_EN_RP2_P0_4 = 0x800012050801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WRCLK_EN_RP2_P1_0 = 0x800002050701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WRCLK_EN_RP2_P1_0 = 0x800002050801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WRCLK_EN_RP2_P1_1 = 0x800006050701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WRCLK_EN_RP2_P1_1 = 0x800006050801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WRCLK_EN_RP2_P1_2 = 0x80000A050701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WRCLK_EN_RP2_P1_2 = 0x80000A050801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WRCLK_EN_RP2_P1_3 = 0x80000E050701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WRCLK_EN_RP2_P1_3 = 0x80000E050801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WRCLK_EN_RP2_P1_4 = 0x800012050701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WRCLK_EN_RP2_P1_4 = 0x800012050801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WRCLK_EN_RP2_P2_0 = 0x800002050701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WRCLK_EN_RP2_P2_0 = 0x800002050801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WRCLK_EN_RP2_P2_1 = 0x800006050701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WRCLK_EN_RP2_P2_1 = 0x800006050801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WRCLK_EN_RP2_P2_2 = 0x80000A050701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WRCLK_EN_RP2_P2_2 = 0x80000A050801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WRCLK_EN_RP2_P2_3 = 0x80000E050701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WRCLK_EN_RP2_P2_3 = 0x80000E050801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WRCLK_EN_RP2_P2_4 = 0x800012050701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WRCLK_EN_RP2_P2_4 = 0x800012050801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WRCLK_EN_RP2_P3_0 = 0x8000020507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WRCLK_EN_RP2_P3_0 = 0x8000020508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WRCLK_EN_RP2_P3_1 = 0x8000060507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WRCLK_EN_RP2_P3_1 = 0x8000060508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WRCLK_EN_RP2_P3_2 = 0x80000A0507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WRCLK_EN_RP2_P3_2 = 0x80000A0508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WRCLK_EN_RP2_P3_3 = 0x80000E0507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WRCLK_EN_RP2_P3_3 = 0x80000E0508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WRCLK_EN_RP2_P3_4 = 0x8000120507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WRCLK_EN_RP2_P3_4 = 0x8000120508011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_0 = 0x800003050701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WRCLK_EN_RP3_P0_0 = 0x800003050701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WRCLK_EN_RP3_P0_0 = 0x800003050801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_1 = 0x800007050701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WRCLK_EN_RP3_P0_1 = 0x800007050701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WRCLK_EN_RP3_P0_1 = 0x800007050801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_2 = 0x80000B050701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WRCLK_EN_RP3_P0_2 = 0x80000B050701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WRCLK_EN_RP3_P0_2 = 0x80000B050801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_3 = 0x80000F050701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WRCLK_EN_RP3_P0_3 = 0x80000F050701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WRCLK_EN_RP3_P0_3 = 0x80000F050801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_4 = 0x800013050701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WRCLK_EN_RP3_P0_4 = 0x800013050701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WRCLK_EN_RP3_P0_4 = 0x800013050801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WRCLK_EN_RP3_P1_0 = 0x800003050701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WRCLK_EN_RP3_P1_0 = 0x800003050801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WRCLK_EN_RP3_P1_1 = 0x800007050701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WRCLK_EN_RP3_P1_1 = 0x800007050801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WRCLK_EN_RP3_P1_2 = 0x80000B050701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WRCLK_EN_RP3_P1_2 = 0x80000B050801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WRCLK_EN_RP3_P1_3 = 0x80000F050701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WRCLK_EN_RP3_P1_3 = 0x80000F050801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WRCLK_EN_RP3_P1_4 = 0x800013050701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WRCLK_EN_RP3_P1_4 = 0x800013050801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WRCLK_EN_RP3_P2_0 = 0x800003050701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WRCLK_EN_RP3_P2_0 = 0x800003050801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WRCLK_EN_RP3_P2_1 = 0x800007050701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WRCLK_EN_RP3_P2_1 = 0x800007050801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WRCLK_EN_RP3_P2_2 = 0x80000B050701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WRCLK_EN_RP3_P2_2 = 0x80000B050801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WRCLK_EN_RP3_P2_3 = 0x80000F050701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WRCLK_EN_RP3_P2_3 = 0x80000F050801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WRCLK_EN_RP3_P2_4 = 0x800013050701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WRCLK_EN_RP3_P2_4 = 0x800013050801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WRCLK_EN_RP3_P3_0 = 0x8000030507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WRCLK_EN_RP3_P3_0 = 0x8000030508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WRCLK_EN_RP3_P3_1 = 0x8000070507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WRCLK_EN_RP3_P3_1 = 0x8000070508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WRCLK_EN_RP3_P3_2 = 0x80000B0507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WRCLK_EN_RP3_P3_2 = 0x80000B0508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WRCLK_EN_RP3_P3_3 = 0x80000F0507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WRCLK_EN_RP3_P3_3 = 0x80000F0508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WRCLK_EN_RP3_P3_4 = 0x8000130507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WRCLK_EN_RP3_P3_4 = 0x8000130508011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WRCLK_PR_P0_0 = 0x800000740701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WRCLK_PR_P0_0 = 0x800000740701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WRCLK_PR_P0_0 = 0x800000740801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WRCLK_PR_P0_1 = 0x800004740701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WRCLK_PR_P0_1 = 0x800004740701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WRCLK_PR_P0_1 = 0x800004740801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WRCLK_PR_P0_2 = 0x800008740701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WRCLK_PR_P0_2 = 0x800008740701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WRCLK_PR_P0_2 = 0x800008740801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WRCLK_PR_P0_3 = 0x80000C740701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WRCLK_PR_P0_3 = 0x80000C740701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WRCLK_PR_P0_3 = 0x80000C740801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WRCLK_PR_P0_4 = 0x800010740701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WRCLK_PR_P0_4 = 0x800010740701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WRCLK_PR_P0_4 = 0x800010740801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WRCLK_PR_P1_0 = 0x800000740701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WRCLK_PR_P1_0 = 0x800000740801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WRCLK_PR_P1_1 = 0x800004740701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WRCLK_PR_P1_1 = 0x800004740801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WRCLK_PR_P1_2 = 0x800008740701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WRCLK_PR_P1_2 = 0x800008740801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WRCLK_PR_P1_3 = 0x80000C740701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WRCLK_PR_P1_3 = 0x80000C740801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WRCLK_PR_P1_4 = 0x800010740701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WRCLK_PR_P1_4 = 0x800010740801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WRCLK_PR_P2_0 = 0x800000740701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WRCLK_PR_P2_0 = 0x800000740801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WRCLK_PR_P2_1 = 0x800004740701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WRCLK_PR_P2_1 = 0x800004740801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WRCLK_PR_P2_2 = 0x800008740701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WRCLK_PR_P2_2 = 0x800008740801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WRCLK_PR_P2_3 = 0x80000C740701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WRCLK_PR_P2_3 = 0x80000C740801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WRCLK_PR_P2_4 = 0x800010740701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WRCLK_PR_P2_4 = 0x800010740801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WRCLK_PR_P3_0 = 0x8000007407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WRCLK_PR_P3_0 = 0x8000007408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WRCLK_PR_P3_1 = 0x8000047407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WRCLK_PR_P3_1 = 0x8000047408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WRCLK_PR_P3_2 = 0x8000087407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WRCLK_PR_P3_2 = 0x8000087408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WRCLK_PR_P3_3 = 0x80000C7407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WRCLK_PR_P3_3 = 0x80000C7408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WRCLK_PR_P3_4 = 0x8000107407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WRCLK_PR_P3_4 = 0x8000107408011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_0 = 0x800000180701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_CNTR_STATUS0_P0_0 = 0x800000180701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_CNTR_STATUS0_P0_0 = 0x800000180801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_1 = 0x800004180701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_CNTR_STATUS0_P0_1 = 0x800004180701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_CNTR_STATUS0_P0_1 = 0x800004180801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_2 = 0x800008180701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_CNTR_STATUS0_P0_2 = 0x800008180701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_CNTR_STATUS0_P0_2 = 0x800008180801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_3 = 0x80000C180701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_CNTR_STATUS0_P0_3 = 0x80000C180701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_CNTR_STATUS0_P0_3 = 0x80000C180801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_4 = 0x800010180701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_CNTR_STATUS0_P0_4 = 0x800010180701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_CNTR_STATUS0_P0_4 = 0x800010180801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_CNTR_STATUS0_P1_0 = 0x800000180701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_CNTR_STATUS0_P1_0 = 0x800000180801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_CNTR_STATUS0_P1_1 = 0x800004180701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_CNTR_STATUS0_P1_1 = 0x800004180801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_CNTR_STATUS0_P1_2 = 0x800008180701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_CNTR_STATUS0_P1_2 = 0x800008180801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_CNTR_STATUS0_P1_3 = 0x80000C180701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_CNTR_STATUS0_P1_3 = 0x80000C180801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_CNTR_STATUS0_P1_4 = 0x800010180701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_CNTR_STATUS0_P1_4 = 0x800010180801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_CNTR_STATUS0_P2_0 = 0x800000180701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_CNTR_STATUS0_P2_0 = 0x800000180801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_CNTR_STATUS0_P2_1 = 0x800004180701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_CNTR_STATUS0_P2_1 = 0x800004180801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_CNTR_STATUS0_P2_2 = 0x800008180701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_CNTR_STATUS0_P2_2 = 0x800008180801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_CNTR_STATUS0_P2_3 = 0x80000C180701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_CNTR_STATUS0_P2_3 = 0x80000C180801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_CNTR_STATUS0_P2_4 = 0x800010180701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_CNTR_STATUS0_P2_4 = 0x800010180801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_CNTR_STATUS0_P3_0 = 0x8000001807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_CNTR_STATUS0_P3_0 = 0x8000001808011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_CNTR_STATUS0_P3_1 = 0x8000041807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_CNTR_STATUS0_P3_1 = 0x8000041808011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_CNTR_STATUS0_P3_2 = 0x8000081807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_CNTR_STATUS0_P3_2 = 0x8000081808011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_CNTR_STATUS0_P3_3 = 0x80000C1807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_CNTR_STATUS0_P3_3 = 0x80000C1808011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_CNTR_STATUS0_P3_4 = 0x8000101807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_CNTR_STATUS0_P3_4 = 0x8000101808011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS1_P0_0 = 0x800000190701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_CNTR_STATUS1_P0_0 = 0x800000190701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_CNTR_STATUS1_P0_0 = 0x800000190801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS1_P0_1 = 0x800004190701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_CNTR_STATUS1_P0_1 = 0x800004190701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_CNTR_STATUS1_P0_1 = 0x800004190801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS1_P0_2 = 0x800008190701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_CNTR_STATUS1_P0_2 = 0x800008190701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_CNTR_STATUS1_P0_2 = 0x800008190801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS1_P0_3 = 0x80000C190701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_CNTR_STATUS1_P0_3 = 0x80000C190701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_CNTR_STATUS1_P0_3 = 0x80000C190801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS1_P0_4 = 0x800010190701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_CNTR_STATUS1_P0_4 = 0x800010190701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_CNTR_STATUS1_P0_4 = 0x800010190801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_CNTR_STATUS1_P1_0 = 0x800000190701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_CNTR_STATUS1_P1_0 = 0x800000190801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_CNTR_STATUS1_P1_1 = 0x800004190701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_CNTR_STATUS1_P1_1 = 0x800004190801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_CNTR_STATUS1_P1_2 = 0x800008190701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_CNTR_STATUS1_P1_2 = 0x800008190801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_CNTR_STATUS1_P1_3 = 0x80000C190701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_CNTR_STATUS1_P1_3 = 0x80000C190801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_CNTR_STATUS1_P1_4 = 0x800010190701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_CNTR_STATUS1_P1_4 = 0x800010190801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_CNTR_STATUS1_P2_0 = 0x800000190701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_CNTR_STATUS1_P2_0 = 0x800000190801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_CNTR_STATUS1_P2_1 = 0x800004190701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_CNTR_STATUS1_P2_1 = 0x800004190801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_CNTR_STATUS1_P2_2 = 0x800008190701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_CNTR_STATUS1_P2_2 = 0x800008190801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_CNTR_STATUS1_P2_3 = 0x80000C190701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_CNTR_STATUS1_P2_3 = 0x80000C190801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_CNTR_STATUS1_P2_4 = 0x800010190701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_CNTR_STATUS1_P2_4 = 0x800010190801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_CNTR_STATUS1_P3_0 = 0x8000001907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_CNTR_STATUS1_P3_0 = 0x8000001908011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_CNTR_STATUS1_P3_1 = 0x8000041907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_CNTR_STATUS1_P3_1 = 0x8000041908011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_CNTR_STATUS1_P3_2 = 0x8000081907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_CNTR_STATUS1_P3_2 = 0x8000081908011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_CNTR_STATUS1_P3_3 = 0x80000C1907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_CNTR_STATUS1_P3_3 = 0x80000C1908011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_CNTR_STATUS1_P3_4 = 0x8000101907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_CNTR_STATUS1_P3_4 = 0x8000101908011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS2_P0_0 = 0x8000001A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_CNTR_STATUS2_P0_0 = 0x8000001A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_CNTR_STATUS2_P0_0 = 0x8000001A0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS2_P0_1 = 0x8000041A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_CNTR_STATUS2_P0_1 = 0x8000041A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_CNTR_STATUS2_P0_1 = 0x8000041A0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS2_P0_2 = 0x8000081A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_CNTR_STATUS2_P0_2 = 0x8000081A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_CNTR_STATUS2_P0_2 = 0x8000081A0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS2_P0_3 = 0x80000C1A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_CNTR_STATUS2_P0_3 = 0x80000C1A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_CNTR_STATUS2_P0_3 = 0x80000C1A0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS2_P0_4 = 0x8000101A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_CNTR_STATUS2_P0_4 = 0x8000101A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_CNTR_STATUS2_P0_4 = 0x8000101A0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_CNTR_STATUS2_P1_0 = 0x8000001A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_CNTR_STATUS2_P1_0 = 0x8000001A0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_CNTR_STATUS2_P1_1 = 0x8000041A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_CNTR_STATUS2_P1_1 = 0x8000041A0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_CNTR_STATUS2_P1_2 = 0x8000081A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_CNTR_STATUS2_P1_2 = 0x8000081A0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_CNTR_STATUS2_P1_3 = 0x80000C1A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_CNTR_STATUS2_P1_3 = 0x80000C1A0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_CNTR_STATUS2_P1_4 = 0x8000101A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_CNTR_STATUS2_P1_4 = 0x8000101A0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_CNTR_STATUS2_P2_0 = 0x8000001A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_CNTR_STATUS2_P2_0 = 0x8000001A0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_CNTR_STATUS2_P2_1 = 0x8000041A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_CNTR_STATUS2_P2_1 = 0x8000041A0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_CNTR_STATUS2_P2_2 = 0x8000081A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_CNTR_STATUS2_P2_2 = 0x8000081A0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_CNTR_STATUS2_P2_3 = 0x80000C1A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_CNTR_STATUS2_P2_3 = 0x80000C1A0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_CNTR_STATUS2_P2_4 = 0x8000101A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_CNTR_STATUS2_P2_4 = 0x8000101A0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_CNTR_STATUS2_P3_0 = 0x8000001A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_CNTR_STATUS2_P3_0 = 0x8000001A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_CNTR_STATUS2_P3_1 = 0x8000041A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_CNTR_STATUS2_P3_1 = 0x8000041A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_CNTR_STATUS2_P3_2 = 0x8000081A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_CNTR_STATUS2_P3_2 = 0x8000081A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_CNTR_STATUS2_P3_3 = 0x80000C1A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_CNTR_STATUS2_P3_3 = 0x80000C1A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_CNTR_STATUS2_P3_4 = 0x8000101A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_CNTR_STATUS2_P3_4 = 0x8000101A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP0_P0_0 = 0x800000380701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_0_RP0_P0_0 = 0x800000380701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_0_RP0_P0_0 = 0x800000380801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP0_P0_1 = 0x800004380701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_0_RP0_P0_1 = 0x800004380701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_0_RP0_P0_1 = 0x800004380801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP0_P0_2 = 0x800008380701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_0_RP0_P0_2 = 0x800008380701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_0_RP0_P0_2 = 0x800008380801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP0_P0_3 = 0x80000C380701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_0_RP0_P0_3 = 0x80000C380701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_0_RP0_P0_3 = 0x80000C380801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP0_P0_4 = 0x800010380701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_0_RP0_P0_4 = 0x800010380701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_0_RP0_P0_4 = 0x800010380801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_0_RP0_P1_0 = 0x800000380701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_0_RP0_P1_0 = 0x800000380801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_0_RP0_P1_1 = 0x800004380701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_0_RP0_P1_1 = 0x800004380801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_0_RP0_P1_2 = 0x800008380701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_0_RP0_P1_2 = 0x800008380801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_0_RP0_P1_3 = 0x80000C380701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_0_RP0_P1_3 = 0x80000C380801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_0_RP0_P1_4 = 0x800010380701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_0_RP0_P1_4 = 0x800010380801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_0_RP0_P2_0 = 0x800000380701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_0_RP0_P2_0 = 0x800000380801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_0_RP0_P2_1 = 0x800004380701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_0_RP0_P2_1 = 0x800004380801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_0_RP0_P2_2 = 0x800008380701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_0_RP0_P2_2 = 0x800008380801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_0_RP0_P2_3 = 0x80000C380701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_0_RP0_P2_3 = 0x80000C380801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_0_RP0_P2_4 = 0x800010380701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_0_RP0_P2_4 = 0x800010380801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_0_RP0_P3_0 = 0x8000003807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_0_RP0_P3_0 = 0x8000003808011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_0_RP0_P3_1 = 0x8000043807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_0_RP0_P3_1 = 0x8000043808011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_0_RP0_P3_2 = 0x8000083807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_0_RP0_P3_2 = 0x8000083808011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_0_RP0_P3_3 = 0x80000C3807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_0_RP0_P3_3 = 0x80000C3808011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_0_RP0_P3_4 = 0x8000103807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_0_RP0_P3_4 = 0x8000103808011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP1_P0_0 = 0x800001380701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_0_RP1_P0_0 = 0x800001380701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_0_RP1_P0_0 = 0x800001380801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP1_P0_1 = 0x800005380701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_0_RP1_P0_1 = 0x800005380701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_0_RP1_P0_1 = 0x800005380801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP1_P0_2 = 0x800009380701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_0_RP1_P0_2 = 0x800009380701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_0_RP1_P0_2 = 0x800009380801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP1_P0_3 = 0x80000D380701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_0_RP1_P0_3 = 0x80000D380701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_0_RP1_P0_3 = 0x80000D380801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP1_P0_4 = 0x800011380701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_0_RP1_P0_4 = 0x800011380701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_0_RP1_P0_4 = 0x800011380801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_0_RP1_P1_0 = 0x800001380701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_0_RP1_P1_0 = 0x800001380801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_0_RP1_P1_1 = 0x800005380701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_0_RP1_P1_1 = 0x800005380801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_0_RP1_P1_2 = 0x800009380701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_0_RP1_P1_2 = 0x800009380801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_0_RP1_P1_3 = 0x80000D380701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_0_RP1_P1_3 = 0x80000D380801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_0_RP1_P1_4 = 0x800011380701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_0_RP1_P1_4 = 0x800011380801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_0_RP1_P2_0 = 0x800001380701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_0_RP1_P2_0 = 0x800001380801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_0_RP1_P2_1 = 0x800005380701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_0_RP1_P2_1 = 0x800005380801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_0_RP1_P2_2 = 0x800009380701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_0_RP1_P2_2 = 0x800009380801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_0_RP1_P2_3 = 0x80000D380701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_0_RP1_P2_3 = 0x80000D380801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_0_RP1_P2_4 = 0x800011380701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_0_RP1_P2_4 = 0x800011380801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_0_RP1_P3_0 = 0x8000013807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_0_RP1_P3_0 = 0x8000013808011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_0_RP1_P3_1 = 0x8000053807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_0_RP1_P3_1 = 0x8000053808011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_0_RP1_P3_2 = 0x8000093807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_0_RP1_P3_2 = 0x8000093808011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_0_RP1_P3_3 = 0x80000D3807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_0_RP1_P3_3 = 0x80000D3808011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_0_RP1_P3_4 = 0x8000113807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_0_RP1_P3_4 = 0x8000113808011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP2_P0_0 = 0x800002380701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_0_RP2_P0_0 = 0x800002380701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_0_RP2_P0_0 = 0x800002380801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP2_P0_1 = 0x800006380701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_0_RP2_P0_1 = 0x800006380701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_0_RP2_P0_1 = 0x800006380801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP2_P0_2 = 0x80000A380701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_0_RP2_P0_2 = 0x80000A380701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_0_RP2_P0_2 = 0x80000A380801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP2_P0_3 = 0x80000E380701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_0_RP2_P0_3 = 0x80000E380701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_0_RP2_P0_3 = 0x80000E380801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP2_P0_4 = 0x800012380701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_0_RP2_P0_4 = 0x800012380701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_0_RP2_P0_4 = 0x800012380801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_0_RP2_P1_0 = 0x800002380701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_0_RP2_P1_0 = 0x800002380801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_0_RP2_P1_1 = 0x800006380701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_0_RP2_P1_1 = 0x800006380801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_0_RP2_P1_2 = 0x80000A380701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_0_RP2_P1_2 = 0x80000A380801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_0_RP2_P1_3 = 0x80000E380701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_0_RP2_P1_3 = 0x80000E380801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_0_RP2_P1_4 = 0x800012380701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_0_RP2_P1_4 = 0x800012380801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_0_RP2_P2_0 = 0x800002380701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_0_RP2_P2_0 = 0x800002380801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_0_RP2_P2_1 = 0x800006380701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_0_RP2_P2_1 = 0x800006380801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_0_RP2_P2_2 = 0x80000A380701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_0_RP2_P2_2 = 0x80000A380801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_0_RP2_P2_3 = 0x80000E380701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_0_RP2_P2_3 = 0x80000E380801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_0_RP2_P2_4 = 0x800012380701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_0_RP2_P2_4 = 0x800012380801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_0_RP2_P3_0 = 0x8000023807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_0_RP2_P3_0 = 0x8000023808011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_0_RP2_P3_1 = 0x8000063807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_0_RP2_P3_1 = 0x8000063808011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_0_RP2_P3_2 = 0x80000A3807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_0_RP2_P3_2 = 0x80000A3808011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_0_RP2_P3_3 = 0x80000E3807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_0_RP2_P3_3 = 0x80000E3808011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_0_RP2_P3_4 = 0x8000123807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_0_RP2_P3_4 = 0x8000123808011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP3_P0_0 = 0x800003380701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_0_RP3_P0_0 = 0x800003380701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_0_RP3_P0_0 = 0x800003380801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP3_P0_1 = 0x800007380701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_0_RP3_P0_1 = 0x800007380701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_0_RP3_P0_1 = 0x800007380801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP3_P0_2 = 0x80000B380701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_0_RP3_P0_2 = 0x80000B380701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_0_RP3_P0_2 = 0x80000B380801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP3_P0_3 = 0x80000F380701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_0_RP3_P0_3 = 0x80000F380701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_0_RP3_P0_3 = 0x80000F380801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP3_P0_4 = 0x800013380701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_0_RP3_P0_4 = 0x800013380701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_0_RP3_P0_4 = 0x800013380801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_0_RP3_P1_0 = 0x800003380701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_0_RP3_P1_0 = 0x800003380801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_0_RP3_P1_1 = 0x800007380701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_0_RP3_P1_1 = 0x800007380801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_0_RP3_P1_2 = 0x80000B380701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_0_RP3_P1_2 = 0x80000B380801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_0_RP3_P1_3 = 0x80000F380701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_0_RP3_P1_3 = 0x80000F380801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_0_RP3_P1_4 = 0x800013380701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_0_RP3_P1_4 = 0x800013380801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_0_RP3_P2_0 = 0x800003380701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_0_RP3_P2_0 = 0x800003380801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_0_RP3_P2_1 = 0x800007380701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_0_RP3_P2_1 = 0x800007380801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_0_RP3_P2_2 = 0x80000B380701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_0_RP3_P2_2 = 0x80000B380801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_0_RP3_P2_3 = 0x80000F380701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_0_RP3_P2_3 = 0x80000F380801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_0_RP3_P2_4 = 0x800013380701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_0_RP3_P2_4 = 0x800013380801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_0_RP3_P3_0 = 0x8000033807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_0_RP3_P3_0 = 0x8000033808011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_0_RP3_P3_1 = 0x8000073807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_0_RP3_P3_1 = 0x8000073808011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_0_RP3_P3_2 = 0x80000B3807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_0_RP3_P3_2 = 0x80000B3808011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_0_RP3_P3_3 = 0x80000F3807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_0_RP3_P3_3 = 0x80000F3808011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_0_RP3_P3_4 = 0x8000133807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_0_RP3_P3_4 = 0x8000133808011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP0_P0_0 = 0x800000420701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_10_RP0_P0_0 = 0x800000420701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_10_RP0_P0_0 = 0x800000420801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP0_P0_1 = 0x800004420701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_10_RP0_P0_1 = 0x800004420701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_10_RP0_P0_1 = 0x800004420801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP0_P0_2 = 0x800008420701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_10_RP0_P0_2 = 0x800008420701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_10_RP0_P0_2 = 0x800008420801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP0_P0_3 = 0x80000C420701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_10_RP0_P0_3 = 0x80000C420701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_10_RP0_P0_3 = 0x80000C420801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP0_P0_4 = 0x800010420701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_10_RP0_P0_4 = 0x800010420701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_10_RP0_P0_4 = 0x800010420801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_10_RP0_P1_0 = 0x800000420701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_10_RP0_P1_0 = 0x800000420801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_10_RP0_P1_1 = 0x800004420701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_10_RP0_P1_1 = 0x800004420801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_10_RP0_P1_2 = 0x800008420701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_10_RP0_P1_2 = 0x800008420801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_10_RP0_P1_3 = 0x80000C420701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_10_RP0_P1_3 = 0x80000C420801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_10_RP0_P1_4 = 0x800010420701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_10_RP0_P1_4 = 0x800010420801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_10_RP0_P2_0 = 0x800000420701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_10_RP0_P2_0 = 0x800000420801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_10_RP0_P2_1 = 0x800004420701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_10_RP0_P2_1 = 0x800004420801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_10_RP0_P2_2 = 0x800008420701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_10_RP0_P2_2 = 0x800008420801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_10_RP0_P2_3 = 0x80000C420701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_10_RP0_P2_3 = 0x80000C420801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_10_RP0_P2_4 = 0x800010420701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_10_RP0_P2_4 = 0x800010420801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_10_RP0_P3_0 = 0x8000004207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_10_RP0_P3_0 = 0x8000004208011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_10_RP0_P3_1 = 0x8000044207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_10_RP0_P3_1 = 0x8000044208011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_10_RP0_P3_2 = 0x8000084207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_10_RP0_P3_2 = 0x8000084208011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_10_RP0_P3_3 = 0x80000C4207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_10_RP0_P3_3 = 0x80000C4208011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_10_RP0_P3_4 = 0x8000104207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_10_RP0_P3_4 = 0x8000104208011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP1_P0_0 = 0x800001420701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_10_RP1_P0_0 = 0x800001420701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_10_RP1_P0_0 = 0x800001420801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP1_P0_1 = 0x800005420701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_10_RP1_P0_1 = 0x800005420701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_10_RP1_P0_1 = 0x800005420801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP1_P0_2 = 0x800009420701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_10_RP1_P0_2 = 0x800009420701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_10_RP1_P0_2 = 0x800009420801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP1_P0_3 = 0x80000D420701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_10_RP1_P0_3 = 0x80000D420701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_10_RP1_P0_3 = 0x80000D420801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP1_P0_4 = 0x800011420701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_10_RP1_P0_4 = 0x800011420701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_10_RP1_P0_4 = 0x800011420801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_10_RP1_P1_0 = 0x800001420701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_10_RP1_P1_0 = 0x800001420801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_10_RP1_P1_1 = 0x800005420701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_10_RP1_P1_1 = 0x800005420801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_10_RP1_P1_2 = 0x800009420701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_10_RP1_P1_2 = 0x800009420801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_10_RP1_P1_3 = 0x80000D420701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_10_RP1_P1_3 = 0x80000D420801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_10_RP1_P1_4 = 0x800011420701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_10_RP1_P1_4 = 0x800011420801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_10_RP1_P2_0 = 0x800001420701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_10_RP1_P2_0 = 0x800001420801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_10_RP1_P2_1 = 0x800005420701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_10_RP1_P2_1 = 0x800005420801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_10_RP1_P2_2 = 0x800009420701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_10_RP1_P2_2 = 0x800009420801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_10_RP1_P2_3 = 0x80000D420701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_10_RP1_P2_3 = 0x80000D420801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_10_RP1_P2_4 = 0x800011420701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_10_RP1_P2_4 = 0x800011420801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_10_RP1_P3_0 = 0x8000014207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_10_RP1_P3_0 = 0x8000014208011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_10_RP1_P3_1 = 0x8000054207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_10_RP1_P3_1 = 0x8000054208011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_10_RP1_P3_2 = 0x8000094207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_10_RP1_P3_2 = 0x8000094208011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_10_RP1_P3_3 = 0x80000D4207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_10_RP1_P3_3 = 0x80000D4208011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_10_RP1_P3_4 = 0x8000114207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_10_RP1_P3_4 = 0x8000114208011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP2_P0_0 = 0x800002420701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_10_RP2_P0_0 = 0x800002420701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_10_RP2_P0_0 = 0x800002420801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP2_P0_1 = 0x800006420701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_10_RP2_P0_1 = 0x800006420701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_10_RP2_P0_1 = 0x800006420801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP2_P0_2 = 0x80000A420701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_10_RP2_P0_2 = 0x80000A420701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_10_RP2_P0_2 = 0x80000A420801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP2_P0_3 = 0x80000E420701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_10_RP2_P0_3 = 0x80000E420701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_10_RP2_P0_3 = 0x80000E420801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP2_P0_4 = 0x800012420701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_10_RP2_P0_4 = 0x800012420701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_10_RP2_P0_4 = 0x800012420801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_10_RP2_P1_0 = 0x800002420701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_10_RP2_P1_0 = 0x800002420801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_10_RP2_P1_1 = 0x800006420701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_10_RP2_P1_1 = 0x800006420801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_10_RP2_P1_2 = 0x80000A420701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_10_RP2_P1_2 = 0x80000A420801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_10_RP2_P1_3 = 0x80000E420701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_10_RP2_P1_3 = 0x80000E420801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_10_RP2_P1_4 = 0x800012420701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_10_RP2_P1_4 = 0x800012420801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_10_RP2_P2_0 = 0x800002420701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_10_RP2_P2_0 = 0x800002420801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_10_RP2_P2_1 = 0x800006420701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_10_RP2_P2_1 = 0x800006420801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_10_RP2_P2_2 = 0x80000A420701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_10_RP2_P2_2 = 0x80000A420801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_10_RP2_P2_3 = 0x80000E420701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_10_RP2_P2_3 = 0x80000E420801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_10_RP2_P2_4 = 0x800012420701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_10_RP2_P2_4 = 0x800012420801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_10_RP2_P3_0 = 0x8000024207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_10_RP2_P3_0 = 0x8000024208011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_10_RP2_P3_1 = 0x8000064207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_10_RP2_P3_1 = 0x8000064208011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_10_RP2_P3_2 = 0x80000A4207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_10_RP2_P3_2 = 0x80000A4208011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_10_RP2_P3_3 = 0x80000E4207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_10_RP2_P3_3 = 0x80000E4208011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_10_RP2_P3_4 = 0x8000124207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_10_RP2_P3_4 = 0x8000124208011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP3_P0_0 = 0x800003420701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_10_RP3_P0_0 = 0x800003420701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_10_RP3_P0_0 = 0x800003420801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP3_P0_1 = 0x800007420701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_10_RP3_P0_1 = 0x800007420701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_10_RP3_P0_1 = 0x800007420801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP3_P0_2 = 0x80000B420701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_10_RP3_P0_2 = 0x80000B420701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_10_RP3_P0_2 = 0x80000B420801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP3_P0_3 = 0x80000F420701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_10_RP3_P0_3 = 0x80000F420701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_10_RP3_P0_3 = 0x80000F420801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP3_P0_4 = 0x800013420701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_10_RP3_P0_4 = 0x800013420701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_10_RP3_P0_4 = 0x800013420801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_10_RP3_P1_0 = 0x800003420701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_10_RP3_P1_0 = 0x800003420801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_10_RP3_P1_1 = 0x800007420701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_10_RP3_P1_1 = 0x800007420801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_10_RP3_P1_2 = 0x80000B420701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_10_RP3_P1_2 = 0x80000B420801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_10_RP3_P1_3 = 0x80000F420701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_10_RP3_P1_3 = 0x80000F420801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_10_RP3_P1_4 = 0x800013420701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_10_RP3_P1_4 = 0x800013420801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_10_RP3_P2_0 = 0x800003420701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_10_RP3_P2_0 = 0x800003420801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_10_RP3_P2_1 = 0x800007420701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_10_RP3_P2_1 = 0x800007420801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_10_RP3_P2_2 = 0x80000B420701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_10_RP3_P2_2 = 0x80000B420801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_10_RP3_P2_3 = 0x80000F420701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_10_RP3_P2_3 = 0x80000F420801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_10_RP3_P2_4 = 0x800013420701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_10_RP3_P2_4 = 0x800013420801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_10_RP3_P3_0 = 0x8000034207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_10_RP3_P3_0 = 0x8000034208011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_10_RP3_P3_1 = 0x8000074207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_10_RP3_P3_1 = 0x8000074208011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_10_RP3_P3_2 = 0x80000B4207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_10_RP3_P3_2 = 0x80000B4208011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_10_RP3_P3_3 = 0x80000F4207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_10_RP3_P3_3 = 0x80000F4208011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_10_RP3_P3_4 = 0x8000134207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_10_RP3_P3_4 = 0x8000134208011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP0_P0_0 = 0x800000430701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_11_RP0_P0_0 = 0x800000430701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_11_RP0_P0_0 = 0x800000430801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP0_P0_1 = 0x800004430701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_11_RP0_P0_1 = 0x800004430701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_11_RP0_P0_1 = 0x800004430801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP0_P0_2 = 0x800008430701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_11_RP0_P0_2 = 0x800008430701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_11_RP0_P0_2 = 0x800008430801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP0_P0_3 = 0x80000C430701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_11_RP0_P0_3 = 0x80000C430701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_11_RP0_P0_3 = 0x80000C430801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP0_P0_4 = 0x800010430701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_11_RP0_P0_4 = 0x800010430701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_11_RP0_P0_4 = 0x800010430801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_11_RP0_P1_0 = 0x800000430701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_11_RP0_P1_0 = 0x800000430801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_11_RP0_P1_1 = 0x800004430701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_11_RP0_P1_1 = 0x800004430801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_11_RP0_P1_2 = 0x800008430701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_11_RP0_P1_2 = 0x800008430801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_11_RP0_P1_3 = 0x80000C430701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_11_RP0_P1_3 = 0x80000C430801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_11_RP0_P1_4 = 0x800010430701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_11_RP0_P1_4 = 0x800010430801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_11_RP0_P2_0 = 0x800000430701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_11_RP0_P2_0 = 0x800000430801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_11_RP0_P2_1 = 0x800004430701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_11_RP0_P2_1 = 0x800004430801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_11_RP0_P2_2 = 0x800008430701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_11_RP0_P2_2 = 0x800008430801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_11_RP0_P2_3 = 0x80000C430701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_11_RP0_P2_3 = 0x80000C430801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_11_RP0_P2_4 = 0x800010430701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_11_RP0_P2_4 = 0x800010430801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_11_RP0_P3_0 = 0x8000004307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_11_RP0_P3_0 = 0x8000004308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_11_RP0_P3_1 = 0x8000044307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_11_RP0_P3_1 = 0x8000044308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_11_RP0_P3_2 = 0x8000084307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_11_RP0_P3_2 = 0x8000084308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_11_RP0_P3_3 = 0x80000C4307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_11_RP0_P3_3 = 0x80000C4308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_11_RP0_P3_4 = 0x8000104307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_11_RP0_P3_4 = 0x8000104308011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP1_P0_0 = 0x800001430701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_11_RP1_P0_0 = 0x800001430701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_11_RP1_P0_0 = 0x800001430801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP1_P0_1 = 0x800005430701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_11_RP1_P0_1 = 0x800005430701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_11_RP1_P0_1 = 0x800005430801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP1_P0_2 = 0x800009430701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_11_RP1_P0_2 = 0x800009430701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_11_RP1_P0_2 = 0x800009430801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP1_P0_3 = 0x80000D430701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_11_RP1_P0_3 = 0x80000D430701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_11_RP1_P0_3 = 0x80000D430801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP1_P0_4 = 0x800011430701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_11_RP1_P0_4 = 0x800011430701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_11_RP1_P0_4 = 0x800011430801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_11_RP1_P1_0 = 0x800001430701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_11_RP1_P1_0 = 0x800001430801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_11_RP1_P1_1 = 0x800005430701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_11_RP1_P1_1 = 0x800005430801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_11_RP1_P1_2 = 0x800009430701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_11_RP1_P1_2 = 0x800009430801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_11_RP1_P1_3 = 0x80000D430701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_11_RP1_P1_3 = 0x80000D430801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_11_RP1_P1_4 = 0x800011430701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_11_RP1_P1_4 = 0x800011430801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_11_RP1_P2_0 = 0x800001430701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_11_RP1_P2_0 = 0x800001430801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_11_RP1_P2_1 = 0x800005430701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_11_RP1_P2_1 = 0x800005430801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_11_RP1_P2_2 = 0x800009430701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_11_RP1_P2_2 = 0x800009430801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_11_RP1_P2_3 = 0x80000D430701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_11_RP1_P2_3 = 0x80000D430801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_11_RP1_P2_4 = 0x800011430701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_11_RP1_P2_4 = 0x800011430801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_11_RP1_P3_0 = 0x8000014307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_11_RP1_P3_0 = 0x8000014308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_11_RP1_P3_1 = 0x8000054307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_11_RP1_P3_1 = 0x8000054308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_11_RP1_P3_2 = 0x8000094307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_11_RP1_P3_2 = 0x8000094308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_11_RP1_P3_3 = 0x80000D4307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_11_RP1_P3_3 = 0x80000D4308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_11_RP1_P3_4 = 0x8000114307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_11_RP1_P3_4 = 0x8000114308011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP2_P0_0 = 0x800002430701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_11_RP2_P0_0 = 0x800002430701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_11_RP2_P0_0 = 0x800002430801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP2_P0_1 = 0x800006430701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_11_RP2_P0_1 = 0x800006430701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_11_RP2_P0_1 = 0x800006430801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP2_P0_2 = 0x80000A430701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_11_RP2_P0_2 = 0x80000A430701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_11_RP2_P0_2 = 0x80000A430801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP2_P0_3 = 0x80000E430701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_11_RP2_P0_3 = 0x80000E430701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_11_RP2_P0_3 = 0x80000E430801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP2_P0_4 = 0x800012430701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_11_RP2_P0_4 = 0x800012430701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_11_RP2_P0_4 = 0x800012430801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_11_RP2_P1_0 = 0x800002430701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_11_RP2_P1_0 = 0x800002430801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_11_RP2_P1_1 = 0x800006430701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_11_RP2_P1_1 = 0x800006430801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_11_RP2_P1_2 = 0x80000A430701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_11_RP2_P1_2 = 0x80000A430801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_11_RP2_P1_3 = 0x80000E430701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_11_RP2_P1_3 = 0x80000E430801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_11_RP2_P1_4 = 0x800012430701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_11_RP2_P1_4 = 0x800012430801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_11_RP2_P2_0 = 0x800002430701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_11_RP2_P2_0 = 0x800002430801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_11_RP2_P2_1 = 0x800006430701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_11_RP2_P2_1 = 0x800006430801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_11_RP2_P2_2 = 0x80000A430701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_11_RP2_P2_2 = 0x80000A430801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_11_RP2_P2_3 = 0x80000E430701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_11_RP2_P2_3 = 0x80000E430801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_11_RP2_P2_4 = 0x800012430701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_11_RP2_P2_4 = 0x800012430801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_11_RP2_P3_0 = 0x8000024307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_11_RP2_P3_0 = 0x8000024308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_11_RP2_P3_1 = 0x8000064307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_11_RP2_P3_1 = 0x8000064308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_11_RP2_P3_2 = 0x80000A4307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_11_RP2_P3_2 = 0x80000A4308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_11_RP2_P3_3 = 0x80000E4307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_11_RP2_P3_3 = 0x80000E4308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_11_RP2_P3_4 = 0x8000124307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_11_RP2_P3_4 = 0x8000124308011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP3_P0_0 = 0x800003430701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_11_RP3_P0_0 = 0x800003430701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_11_RP3_P0_0 = 0x800003430801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP3_P0_1 = 0x800007430701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_11_RP3_P0_1 = 0x800007430701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_11_RP3_P0_1 = 0x800007430801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP3_P0_2 = 0x80000B430701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_11_RP3_P0_2 = 0x80000B430701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_11_RP3_P0_2 = 0x80000B430801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP3_P0_3 = 0x80000F430701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_11_RP3_P0_3 = 0x80000F430701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_11_RP3_P0_3 = 0x80000F430801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP3_P0_4 = 0x800013430701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_11_RP3_P0_4 = 0x800013430701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_11_RP3_P0_4 = 0x800013430801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_11_RP3_P1_0 = 0x800003430701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_11_RP3_P1_0 = 0x800003430801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_11_RP3_P1_1 = 0x800007430701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_11_RP3_P1_1 = 0x800007430801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_11_RP3_P1_2 = 0x80000B430701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_11_RP3_P1_2 = 0x80000B430801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_11_RP3_P1_3 = 0x80000F430701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_11_RP3_P1_3 = 0x80000F430801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_11_RP3_P1_4 = 0x800013430701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_11_RP3_P1_4 = 0x800013430801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_11_RP3_P2_0 = 0x800003430701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_11_RP3_P2_0 = 0x800003430801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_11_RP3_P2_1 = 0x800007430701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_11_RP3_P2_1 = 0x800007430801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_11_RP3_P2_2 = 0x80000B430701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_11_RP3_P2_2 = 0x80000B430801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_11_RP3_P2_3 = 0x80000F430701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_11_RP3_P2_3 = 0x80000F430801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_11_RP3_P2_4 = 0x800013430701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_11_RP3_P2_4 = 0x800013430801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_11_RP3_P3_0 = 0x8000034307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_11_RP3_P3_0 = 0x8000034308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_11_RP3_P3_1 = 0x8000074307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_11_RP3_P3_1 = 0x8000074308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_11_RP3_P3_2 = 0x80000B4307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_11_RP3_P3_2 = 0x80000B4308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_11_RP3_P3_3 = 0x80000F4307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_11_RP3_P3_3 = 0x80000F4308011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_11_RP3_P3_4 = 0x8000134307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_11_RP3_P3_4 = 0x8000134308011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP0_P0_0 = 0x800000440701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_12_RP0_P0_0 = 0x800000440701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_12_RP0_P0_0 = 0x800000440801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP0_P0_1 = 0x800004440701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_12_RP0_P0_1 = 0x800004440701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_12_RP0_P0_1 = 0x800004440801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP0_P0_2 = 0x800008440701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_12_RP0_P0_2 = 0x800008440701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_12_RP0_P0_2 = 0x800008440801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP0_P0_3 = 0x80000C440701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_12_RP0_P0_3 = 0x80000C440701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_12_RP0_P0_3 = 0x80000C440801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP0_P0_4 = 0x800010440701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_12_RP0_P0_4 = 0x800010440701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_12_RP0_P0_4 = 0x800010440801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_12_RP0_P1_0 = 0x800000440701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_12_RP0_P1_0 = 0x800000440801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_12_RP0_P1_1 = 0x800004440701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_12_RP0_P1_1 = 0x800004440801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_12_RP0_P1_2 = 0x800008440701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_12_RP0_P1_2 = 0x800008440801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_12_RP0_P1_3 = 0x80000C440701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_12_RP0_P1_3 = 0x80000C440801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_12_RP0_P1_4 = 0x800010440701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_12_RP0_P1_4 = 0x800010440801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_12_RP0_P2_0 = 0x800000440701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_12_RP0_P2_0 = 0x800000440801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_12_RP0_P2_1 = 0x800004440701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_12_RP0_P2_1 = 0x800004440801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_12_RP0_P2_2 = 0x800008440701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_12_RP0_P2_2 = 0x800008440801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_12_RP0_P2_3 = 0x80000C440701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_12_RP0_P2_3 = 0x80000C440801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_12_RP0_P2_4 = 0x800010440701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_12_RP0_P2_4 = 0x800010440801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_12_RP0_P3_0 = 0x8000004407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_12_RP0_P3_0 = 0x8000004408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_12_RP0_P3_1 = 0x8000044407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_12_RP0_P3_1 = 0x8000044408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_12_RP0_P3_2 = 0x8000084407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_12_RP0_P3_2 = 0x8000084408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_12_RP0_P3_3 = 0x80000C4407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_12_RP0_P3_3 = 0x80000C4408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_12_RP0_P3_4 = 0x8000104407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_12_RP0_P3_4 = 0x8000104408011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP1_P0_0 = 0x800001440701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_12_RP1_P0_0 = 0x800001440701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_12_RP1_P0_0 = 0x800001440801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP1_P0_1 = 0x800005440701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_12_RP1_P0_1 = 0x800005440701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_12_RP1_P0_1 = 0x800005440801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP1_P0_2 = 0x800009440701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_12_RP1_P0_2 = 0x800009440701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_12_RP1_P0_2 = 0x800009440801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP1_P0_3 = 0x80000D440701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_12_RP1_P0_3 = 0x80000D440701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_12_RP1_P0_3 = 0x80000D440801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP1_P0_4 = 0x800011440701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_12_RP1_P0_4 = 0x800011440701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_12_RP1_P0_4 = 0x800011440801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_12_RP1_P1_0 = 0x800001440701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_12_RP1_P1_0 = 0x800001440801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_12_RP1_P1_1 = 0x800005440701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_12_RP1_P1_1 = 0x800005440801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_12_RP1_P1_2 = 0x800009440701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_12_RP1_P1_2 = 0x800009440801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_12_RP1_P1_3 = 0x80000D440701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_12_RP1_P1_3 = 0x80000D440801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_12_RP1_P1_4 = 0x800011440701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_12_RP1_P1_4 = 0x800011440801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_12_RP1_P2_0 = 0x800001440701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_12_RP1_P2_0 = 0x800001440801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_12_RP1_P2_1 = 0x800005440701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_12_RP1_P2_1 = 0x800005440801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_12_RP1_P2_2 = 0x800009440701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_12_RP1_P2_2 = 0x800009440801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_12_RP1_P2_3 = 0x80000D440701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_12_RP1_P2_3 = 0x80000D440801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_12_RP1_P2_4 = 0x800011440701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_12_RP1_P2_4 = 0x800011440801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_12_RP1_P3_0 = 0x8000014407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_12_RP1_P3_0 = 0x8000014408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_12_RP1_P3_1 = 0x8000054407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_12_RP1_P3_1 = 0x8000054408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_12_RP1_P3_2 = 0x8000094407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_12_RP1_P3_2 = 0x8000094408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_12_RP1_P3_3 = 0x80000D4407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_12_RP1_P3_3 = 0x80000D4408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_12_RP1_P3_4 = 0x8000114407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_12_RP1_P3_4 = 0x8000114408011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP2_P0_0 = 0x800002440701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_12_RP2_P0_0 = 0x800002440701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_12_RP2_P0_0 = 0x800002440801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP2_P0_1 = 0x800006440701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_12_RP2_P0_1 = 0x800006440701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_12_RP2_P0_1 = 0x800006440801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP2_P0_2 = 0x80000A440701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_12_RP2_P0_2 = 0x80000A440701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_12_RP2_P0_2 = 0x80000A440801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP2_P0_3 = 0x80000E440701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_12_RP2_P0_3 = 0x80000E440701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_12_RP2_P0_3 = 0x80000E440801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP2_P0_4 = 0x800012440701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_12_RP2_P0_4 = 0x800012440701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_12_RP2_P0_4 = 0x800012440801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_12_RP2_P1_0 = 0x800002440701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_12_RP2_P1_0 = 0x800002440801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_12_RP2_P1_1 = 0x800006440701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_12_RP2_P1_1 = 0x800006440801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_12_RP2_P1_2 = 0x80000A440701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_12_RP2_P1_2 = 0x80000A440801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_12_RP2_P1_3 = 0x80000E440701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_12_RP2_P1_3 = 0x80000E440801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_12_RP2_P1_4 = 0x800012440701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_12_RP2_P1_4 = 0x800012440801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_12_RP2_P2_0 = 0x800002440701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_12_RP2_P2_0 = 0x800002440801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_12_RP2_P2_1 = 0x800006440701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_12_RP2_P2_1 = 0x800006440801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_12_RP2_P2_2 = 0x80000A440701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_12_RP2_P2_2 = 0x80000A440801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_12_RP2_P2_3 = 0x80000E440701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_12_RP2_P2_3 = 0x80000E440801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_12_RP2_P2_4 = 0x800012440701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_12_RP2_P2_4 = 0x800012440801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_12_RP2_P3_0 = 0x8000024407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_12_RP2_P3_0 = 0x8000024408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_12_RP2_P3_1 = 0x8000064407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_12_RP2_P3_1 = 0x8000064408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_12_RP2_P3_2 = 0x80000A4407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_12_RP2_P3_2 = 0x80000A4408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_12_RP2_P3_3 = 0x80000E4407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_12_RP2_P3_3 = 0x80000E4408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_12_RP2_P3_4 = 0x8000124407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_12_RP2_P3_4 = 0x8000124408011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP3_P0_0 = 0x800003440701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_12_RP3_P0_0 = 0x800003440701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_12_RP3_P0_0 = 0x800003440801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP3_P0_1 = 0x800007440701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_12_RP3_P0_1 = 0x800007440701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_12_RP3_P0_1 = 0x800007440801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP3_P0_2 = 0x80000B440701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_12_RP3_P0_2 = 0x80000B440701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_12_RP3_P0_2 = 0x80000B440801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP3_P0_3 = 0x80000F440701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_12_RP3_P0_3 = 0x80000F440701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_12_RP3_P0_3 = 0x80000F440801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP3_P0_4 = 0x800013440701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_12_RP3_P0_4 = 0x800013440701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_12_RP3_P0_4 = 0x800013440801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_12_RP3_P1_0 = 0x800003440701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_12_RP3_P1_0 = 0x800003440801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_12_RP3_P1_1 = 0x800007440701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_12_RP3_P1_1 = 0x800007440801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_12_RP3_P1_2 = 0x80000B440701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_12_RP3_P1_2 = 0x80000B440801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_12_RP3_P1_3 = 0x80000F440701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_12_RP3_P1_3 = 0x80000F440801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_12_RP3_P1_4 = 0x800013440701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_12_RP3_P1_4 = 0x800013440801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_12_RP3_P2_0 = 0x800003440701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_12_RP3_P2_0 = 0x800003440801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_12_RP3_P2_1 = 0x800007440701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_12_RP3_P2_1 = 0x800007440801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_12_RP3_P2_2 = 0x80000B440701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_12_RP3_P2_2 = 0x80000B440801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_12_RP3_P2_3 = 0x80000F440701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_12_RP3_P2_3 = 0x80000F440801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_12_RP3_P2_4 = 0x800013440701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_12_RP3_P2_4 = 0x800013440801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_12_RP3_P3_0 = 0x8000034407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_12_RP3_P3_0 = 0x8000034408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_12_RP3_P3_1 = 0x8000074407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_12_RP3_P3_1 = 0x8000074408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_12_RP3_P3_2 = 0x80000B4407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_12_RP3_P3_2 = 0x80000B4408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_12_RP3_P3_3 = 0x80000F4407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_12_RP3_P3_3 = 0x80000F4408011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_12_RP3_P3_4 = 0x8000134407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_12_RP3_P3_4 = 0x8000134408011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP0_P0_0 = 0x800000450701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_13_RP0_P0_0 = 0x800000450701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_13_RP0_P0_0 = 0x800000450801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP0_P0_1 = 0x800004450701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_13_RP0_P0_1 = 0x800004450701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_13_RP0_P0_1 = 0x800004450801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP0_P0_2 = 0x800008450701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_13_RP0_P0_2 = 0x800008450701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_13_RP0_P0_2 = 0x800008450801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP0_P0_3 = 0x80000C450701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_13_RP0_P0_3 = 0x80000C450701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_13_RP0_P0_3 = 0x80000C450801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP0_P0_4 = 0x800010450701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_13_RP0_P0_4 = 0x800010450701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_13_RP0_P0_4 = 0x800010450801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_13_RP0_P1_0 = 0x800000450701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_13_RP0_P1_0 = 0x800000450801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_13_RP0_P1_1 = 0x800004450701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_13_RP0_P1_1 = 0x800004450801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_13_RP0_P1_2 = 0x800008450701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_13_RP0_P1_2 = 0x800008450801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_13_RP0_P1_3 = 0x80000C450701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_13_RP0_P1_3 = 0x80000C450801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_13_RP0_P1_4 = 0x800010450701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_13_RP0_P1_4 = 0x800010450801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_13_RP0_P2_0 = 0x800000450701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_13_RP0_P2_0 = 0x800000450801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_13_RP0_P2_1 = 0x800004450701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_13_RP0_P2_1 = 0x800004450801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_13_RP0_P2_2 = 0x800008450701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_13_RP0_P2_2 = 0x800008450801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_13_RP0_P2_3 = 0x80000C450701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_13_RP0_P2_3 = 0x80000C450801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_13_RP0_P2_4 = 0x800010450701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_13_RP0_P2_4 = 0x800010450801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_13_RP0_P3_0 = 0x8000004507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_13_RP0_P3_0 = 0x8000004508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_13_RP0_P3_1 = 0x8000044507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_13_RP0_P3_1 = 0x8000044508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_13_RP0_P3_2 = 0x8000084507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_13_RP0_P3_2 = 0x8000084508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_13_RP0_P3_3 = 0x80000C4507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_13_RP0_P3_3 = 0x80000C4508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_13_RP0_P3_4 = 0x8000104507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_13_RP0_P3_4 = 0x8000104508011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP1_P0_0 = 0x800001450701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_13_RP1_P0_0 = 0x800001450701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_13_RP1_P0_0 = 0x800001450801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP1_P0_1 = 0x800005450701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_13_RP1_P0_1 = 0x800005450701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_13_RP1_P0_1 = 0x800005450801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP1_P0_2 = 0x800009450701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_13_RP1_P0_2 = 0x800009450701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_13_RP1_P0_2 = 0x800009450801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP1_P0_3 = 0x80000D450701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_13_RP1_P0_3 = 0x80000D450701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_13_RP1_P0_3 = 0x80000D450801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP1_P0_4 = 0x800011450701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_13_RP1_P0_4 = 0x800011450701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_13_RP1_P0_4 = 0x800011450801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_13_RP1_P1_0 = 0x800001450701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_13_RP1_P1_0 = 0x800001450801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_13_RP1_P1_1 = 0x800005450701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_13_RP1_P1_1 = 0x800005450801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_13_RP1_P1_2 = 0x800009450701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_13_RP1_P1_2 = 0x800009450801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_13_RP1_P1_3 = 0x80000D450701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_13_RP1_P1_3 = 0x80000D450801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_13_RP1_P1_4 = 0x800011450701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_13_RP1_P1_4 = 0x800011450801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_13_RP1_P2_0 = 0x800001450701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_13_RP1_P2_0 = 0x800001450801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_13_RP1_P2_1 = 0x800005450701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_13_RP1_P2_1 = 0x800005450801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_13_RP1_P2_2 = 0x800009450701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_13_RP1_P2_2 = 0x800009450801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_13_RP1_P2_3 = 0x80000D450701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_13_RP1_P2_3 = 0x80000D450801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_13_RP1_P2_4 = 0x800011450701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_13_RP1_P2_4 = 0x800011450801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_13_RP1_P3_0 = 0x8000014507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_13_RP1_P3_0 = 0x8000014508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_13_RP1_P3_1 = 0x8000054507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_13_RP1_P3_1 = 0x8000054508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_13_RP1_P3_2 = 0x8000094507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_13_RP1_P3_2 = 0x8000094508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_13_RP1_P3_3 = 0x80000D4507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_13_RP1_P3_3 = 0x80000D4508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_13_RP1_P3_4 = 0x8000114507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_13_RP1_P3_4 = 0x8000114508011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP2_P0_0 = 0x800002450701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_13_RP2_P0_0 = 0x800002450701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_13_RP2_P0_0 = 0x800002450801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP2_P0_1 = 0x800006450701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_13_RP2_P0_1 = 0x800006450701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_13_RP2_P0_1 = 0x800006450801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP2_P0_2 = 0x80000A450701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_13_RP2_P0_2 = 0x80000A450701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_13_RP2_P0_2 = 0x80000A450801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP2_P0_3 = 0x80000E450701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_13_RP2_P0_3 = 0x80000E450701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_13_RP2_P0_3 = 0x80000E450801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP2_P0_4 = 0x800012450701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_13_RP2_P0_4 = 0x800012450701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_13_RP2_P0_4 = 0x800012450801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_13_RP2_P1_0 = 0x800002450701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_13_RP2_P1_0 = 0x800002450801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_13_RP2_P1_1 = 0x800006450701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_13_RP2_P1_1 = 0x800006450801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_13_RP2_P1_2 = 0x80000A450701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_13_RP2_P1_2 = 0x80000A450801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_13_RP2_P1_3 = 0x80000E450701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_13_RP2_P1_3 = 0x80000E450801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_13_RP2_P1_4 = 0x800012450701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_13_RP2_P1_4 = 0x800012450801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_13_RP2_P2_0 = 0x800002450701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_13_RP2_P2_0 = 0x800002450801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_13_RP2_P2_1 = 0x800006450701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_13_RP2_P2_1 = 0x800006450801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_13_RP2_P2_2 = 0x80000A450701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_13_RP2_P2_2 = 0x80000A450801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_13_RP2_P2_3 = 0x80000E450701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_13_RP2_P2_3 = 0x80000E450801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_13_RP2_P2_4 = 0x800012450701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_13_RP2_P2_4 = 0x800012450801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_13_RP2_P3_0 = 0x8000024507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_13_RP2_P3_0 = 0x8000024508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_13_RP2_P3_1 = 0x8000064507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_13_RP2_P3_1 = 0x8000064508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_13_RP2_P3_2 = 0x80000A4507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_13_RP2_P3_2 = 0x80000A4508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_13_RP2_P3_3 = 0x80000E4507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_13_RP2_P3_3 = 0x80000E4508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_13_RP2_P3_4 = 0x8000124507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_13_RP2_P3_4 = 0x8000124508011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP3_P0_0 = 0x800003450701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_13_RP3_P0_0 = 0x800003450701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_13_RP3_P0_0 = 0x800003450801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP3_P0_1 = 0x800007450701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_13_RP3_P0_1 = 0x800007450701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_13_RP3_P0_1 = 0x800007450801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP3_P0_2 = 0x80000B450701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_13_RP3_P0_2 = 0x80000B450701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_13_RP3_P0_2 = 0x80000B450801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP3_P0_3 = 0x80000F450701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_13_RP3_P0_3 = 0x80000F450701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_13_RP3_P0_3 = 0x80000F450801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP3_P0_4 = 0x800013450701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_13_RP3_P0_4 = 0x800013450701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_13_RP3_P0_4 = 0x800013450801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_13_RP3_P1_0 = 0x800003450701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_13_RP3_P1_0 = 0x800003450801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_13_RP3_P1_1 = 0x800007450701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_13_RP3_P1_1 = 0x800007450801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_13_RP3_P1_2 = 0x80000B450701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_13_RP3_P1_2 = 0x80000B450801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_13_RP3_P1_3 = 0x80000F450701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_13_RP3_P1_3 = 0x80000F450801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_13_RP3_P1_4 = 0x800013450701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_13_RP3_P1_4 = 0x800013450801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_13_RP3_P2_0 = 0x800003450701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_13_RP3_P2_0 = 0x800003450801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_13_RP3_P2_1 = 0x800007450701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_13_RP3_P2_1 = 0x800007450801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_13_RP3_P2_2 = 0x80000B450701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_13_RP3_P2_2 = 0x80000B450801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_13_RP3_P2_3 = 0x80000F450701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_13_RP3_P2_3 = 0x80000F450801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_13_RP3_P2_4 = 0x800013450701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_13_RP3_P2_4 = 0x800013450801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_13_RP3_P3_0 = 0x8000034507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_13_RP3_P3_0 = 0x8000034508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_13_RP3_P3_1 = 0x8000074507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_13_RP3_P3_1 = 0x8000074508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_13_RP3_P3_2 = 0x80000B4507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_13_RP3_P3_2 = 0x80000B4508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_13_RP3_P3_3 = 0x80000F4507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_13_RP3_P3_3 = 0x80000F4508011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_13_RP3_P3_4 = 0x8000134507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_13_RP3_P3_4 = 0x8000134508011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP0_P0_0 = 0x800000460701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_14_RP0_P0_0 = 0x800000460701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_14_RP0_P0_0 = 0x800000460801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP0_P0_1 = 0x800004460701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_14_RP0_P0_1 = 0x800004460701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_14_RP0_P0_1 = 0x800004460801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP0_P0_2 = 0x800008460701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_14_RP0_P0_2 = 0x800008460701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_14_RP0_P0_2 = 0x800008460801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP0_P0_3 = 0x80000C460701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_14_RP0_P0_3 = 0x80000C460701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_14_RP0_P0_3 = 0x80000C460801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP0_P0_4 = 0x800010460701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_14_RP0_P0_4 = 0x800010460701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_14_RP0_P0_4 = 0x800010460801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_14_RP0_P1_0 = 0x800000460701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_14_RP0_P1_0 = 0x800000460801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_14_RP0_P1_1 = 0x800004460701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_14_RP0_P1_1 = 0x800004460801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_14_RP0_P1_2 = 0x800008460701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_14_RP0_P1_2 = 0x800008460801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_14_RP0_P1_3 = 0x80000C460701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_14_RP0_P1_3 = 0x80000C460801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_14_RP0_P1_4 = 0x800010460701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_14_RP0_P1_4 = 0x800010460801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_14_RP0_P2_0 = 0x800000460701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_14_RP0_P2_0 = 0x800000460801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_14_RP0_P2_1 = 0x800004460701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_14_RP0_P2_1 = 0x800004460801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_14_RP0_P2_2 = 0x800008460701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_14_RP0_P2_2 = 0x800008460801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_14_RP0_P2_3 = 0x80000C460701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_14_RP0_P2_3 = 0x80000C460801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_14_RP0_P2_4 = 0x800010460701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_14_RP0_P2_4 = 0x800010460801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_14_RP0_P3_0 = 0x8000004607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_14_RP0_P3_0 = 0x8000004608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_14_RP0_P3_1 = 0x8000044607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_14_RP0_P3_1 = 0x8000044608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_14_RP0_P3_2 = 0x8000084607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_14_RP0_P3_2 = 0x8000084608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_14_RP0_P3_3 = 0x80000C4607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_14_RP0_P3_3 = 0x80000C4608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_14_RP0_P3_4 = 0x8000104607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_14_RP0_P3_4 = 0x8000104608011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP1_P0_0 = 0x800001460701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_14_RP1_P0_0 = 0x800001460701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_14_RP1_P0_0 = 0x800001460801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP1_P0_1 = 0x800005460701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_14_RP1_P0_1 = 0x800005460701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_14_RP1_P0_1 = 0x800005460801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP1_P0_2 = 0x800009460701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_14_RP1_P0_2 = 0x800009460701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_14_RP1_P0_2 = 0x800009460801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP1_P0_3 = 0x80000D460701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_14_RP1_P0_3 = 0x80000D460701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_14_RP1_P0_3 = 0x80000D460801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP1_P0_4 = 0x800011460701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_14_RP1_P0_4 = 0x800011460701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_14_RP1_P0_4 = 0x800011460801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_14_RP1_P1_0 = 0x800001460701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_14_RP1_P1_0 = 0x800001460801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_14_RP1_P1_1 = 0x800005460701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_14_RP1_P1_1 = 0x800005460801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_14_RP1_P1_2 = 0x800009460701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_14_RP1_P1_2 = 0x800009460801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_14_RP1_P1_3 = 0x80000D460701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_14_RP1_P1_3 = 0x80000D460801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_14_RP1_P1_4 = 0x800011460701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_14_RP1_P1_4 = 0x800011460801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_14_RP1_P2_0 = 0x800001460701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_14_RP1_P2_0 = 0x800001460801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_14_RP1_P2_1 = 0x800005460701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_14_RP1_P2_1 = 0x800005460801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_14_RP1_P2_2 = 0x800009460701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_14_RP1_P2_2 = 0x800009460801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_14_RP1_P2_3 = 0x80000D460701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_14_RP1_P2_3 = 0x80000D460801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_14_RP1_P2_4 = 0x800011460701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_14_RP1_P2_4 = 0x800011460801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_14_RP1_P3_0 = 0x8000014607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_14_RP1_P3_0 = 0x8000014608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_14_RP1_P3_1 = 0x8000054607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_14_RP1_P3_1 = 0x8000054608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_14_RP1_P3_2 = 0x8000094607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_14_RP1_P3_2 = 0x8000094608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_14_RP1_P3_3 = 0x80000D4607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_14_RP1_P3_3 = 0x80000D4608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_14_RP1_P3_4 = 0x8000114607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_14_RP1_P3_4 = 0x8000114608011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP2_P0_0 = 0x800002460701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_14_RP2_P0_0 = 0x800002460701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_14_RP2_P0_0 = 0x800002460801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP2_P0_1 = 0x800006460701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_14_RP2_P0_1 = 0x800006460701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_14_RP2_P0_1 = 0x800006460801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP2_P0_2 = 0x80000A460701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_14_RP2_P0_2 = 0x80000A460701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_14_RP2_P0_2 = 0x80000A460801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP2_P0_3 = 0x80000E460701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_14_RP2_P0_3 = 0x80000E460701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_14_RP2_P0_3 = 0x80000E460801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP2_P0_4 = 0x800012460701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_14_RP2_P0_4 = 0x800012460701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_14_RP2_P0_4 = 0x800012460801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_14_RP2_P1_0 = 0x800002460701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_14_RP2_P1_0 = 0x800002460801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_14_RP2_P1_1 = 0x800006460701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_14_RP2_P1_1 = 0x800006460801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_14_RP2_P1_2 = 0x80000A460701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_14_RP2_P1_2 = 0x80000A460801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_14_RP2_P1_3 = 0x80000E460701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_14_RP2_P1_3 = 0x80000E460801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_14_RP2_P1_4 = 0x800012460701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_14_RP2_P1_4 = 0x800012460801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_14_RP2_P2_0 = 0x800002460701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_14_RP2_P2_0 = 0x800002460801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_14_RP2_P2_1 = 0x800006460701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_14_RP2_P2_1 = 0x800006460801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_14_RP2_P2_2 = 0x80000A460701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_14_RP2_P2_2 = 0x80000A460801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_14_RP2_P2_3 = 0x80000E460701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_14_RP2_P2_3 = 0x80000E460801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_14_RP2_P2_4 = 0x800012460701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_14_RP2_P2_4 = 0x800012460801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_14_RP2_P3_0 = 0x8000024607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_14_RP2_P3_0 = 0x8000024608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_14_RP2_P3_1 = 0x8000064607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_14_RP2_P3_1 = 0x8000064608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_14_RP2_P3_2 = 0x80000A4607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_14_RP2_P3_2 = 0x80000A4608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_14_RP2_P3_3 = 0x80000E4607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_14_RP2_P3_3 = 0x80000E4608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_14_RP2_P3_4 = 0x8000124607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_14_RP2_P3_4 = 0x8000124608011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP3_P0_0 = 0x800003460701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_14_RP3_P0_0 = 0x800003460701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_14_RP3_P0_0 = 0x800003460801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP3_P0_1 = 0x800007460701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_14_RP3_P0_1 = 0x800007460701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_14_RP3_P0_1 = 0x800007460801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP3_P0_2 = 0x80000B460701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_14_RP3_P0_2 = 0x80000B460701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_14_RP3_P0_2 = 0x80000B460801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP3_P0_3 = 0x80000F460701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_14_RP3_P0_3 = 0x80000F460701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_14_RP3_P0_3 = 0x80000F460801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP3_P0_4 = 0x800013460701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_14_RP3_P0_4 = 0x800013460701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_14_RP3_P0_4 = 0x800013460801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_14_RP3_P1_0 = 0x800003460701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_14_RP3_P1_0 = 0x800003460801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_14_RP3_P1_1 = 0x800007460701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_14_RP3_P1_1 = 0x800007460801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_14_RP3_P1_2 = 0x80000B460701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_14_RP3_P1_2 = 0x80000B460801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_14_RP3_P1_3 = 0x80000F460701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_14_RP3_P1_3 = 0x80000F460801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_14_RP3_P1_4 = 0x800013460701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_14_RP3_P1_4 = 0x800013460801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_14_RP3_P2_0 = 0x800003460701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_14_RP3_P2_0 = 0x800003460801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_14_RP3_P2_1 = 0x800007460701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_14_RP3_P2_1 = 0x800007460801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_14_RP3_P2_2 = 0x80000B460701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_14_RP3_P2_2 = 0x80000B460801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_14_RP3_P2_3 = 0x80000F460701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_14_RP3_P2_3 = 0x80000F460801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_14_RP3_P2_4 = 0x800013460701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_14_RP3_P2_4 = 0x800013460801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_14_RP3_P3_0 = 0x8000034607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_14_RP3_P3_0 = 0x8000034608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_14_RP3_P3_1 = 0x8000074607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_14_RP3_P3_1 = 0x8000074608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_14_RP3_P3_2 = 0x80000B4607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_14_RP3_P3_2 = 0x80000B4608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_14_RP3_P3_3 = 0x80000F4607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_14_RP3_P3_3 = 0x80000F4608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_14_RP3_P3_4 = 0x8000134607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_14_RP3_P3_4 = 0x8000134608011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP0_P0_0 = 0x800000470701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_15_RP0_P0_0 = 0x800000470701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_15_RP0_P0_0 = 0x800000470801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP0_P0_1 = 0x800004470701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_15_RP0_P0_1 = 0x800004470701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_15_RP0_P0_1 = 0x800004470801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP0_P0_2 = 0x800008470701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_15_RP0_P0_2 = 0x800008470701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_15_RP0_P0_2 = 0x800008470801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP0_P0_3 = 0x80000C470701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_15_RP0_P0_3 = 0x80000C470701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_15_RP0_P0_3 = 0x80000C470801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP0_P0_4 = 0x800010470701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_15_RP0_P0_4 = 0x800010470701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_15_RP0_P0_4 = 0x800010470801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_15_RP0_P1_0 = 0x800000470701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_15_RP0_P1_0 = 0x800000470801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_15_RP0_P1_1 = 0x800004470701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_15_RP0_P1_1 = 0x800004470801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_15_RP0_P1_2 = 0x800008470701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_15_RP0_P1_2 = 0x800008470801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_15_RP0_P1_3 = 0x80000C470701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_15_RP0_P1_3 = 0x80000C470801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_15_RP0_P1_4 = 0x800010470701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_15_RP0_P1_4 = 0x800010470801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_15_RP0_P2_0 = 0x800000470701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_15_RP0_P2_0 = 0x800000470801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_15_RP0_P2_1 = 0x800004470701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_15_RP0_P2_1 = 0x800004470801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_15_RP0_P2_2 = 0x800008470701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_15_RP0_P2_2 = 0x800008470801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_15_RP0_P2_3 = 0x80000C470701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_15_RP0_P2_3 = 0x80000C470801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_15_RP0_P2_4 = 0x800010470701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_15_RP0_P2_4 = 0x800010470801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_15_RP0_P3_0 = 0x8000004707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_15_RP0_P3_0 = 0x8000004708011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_15_RP0_P3_1 = 0x8000044707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_15_RP0_P3_1 = 0x8000044708011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_15_RP0_P3_2 = 0x8000084707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_15_RP0_P3_2 = 0x8000084708011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_15_RP0_P3_3 = 0x80000C4707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_15_RP0_P3_3 = 0x80000C4708011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_15_RP0_P3_4 = 0x8000104707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_15_RP0_P3_4 = 0x8000104708011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP1_P0_0 = 0x800001470701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_15_RP1_P0_0 = 0x800001470701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_15_RP1_P0_0 = 0x800001470801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP1_P0_1 = 0x800005470701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_15_RP1_P0_1 = 0x800005470701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_15_RP1_P0_1 = 0x800005470801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP1_P0_2 = 0x800009470701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_15_RP1_P0_2 = 0x800009470701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_15_RP1_P0_2 = 0x800009470801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP1_P0_3 = 0x80000D470701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_15_RP1_P0_3 = 0x80000D470701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_15_RP1_P0_3 = 0x80000D470801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP1_P0_4 = 0x800011470701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_15_RP1_P0_4 = 0x800011470701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_15_RP1_P0_4 = 0x800011470801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_15_RP1_P1_0 = 0x800001470701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_15_RP1_P1_0 = 0x800001470801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_15_RP1_P1_1 = 0x800005470701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_15_RP1_P1_1 = 0x800005470801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_15_RP1_P1_2 = 0x800009470701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_15_RP1_P1_2 = 0x800009470801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_15_RP1_P1_3 = 0x80000D470701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_15_RP1_P1_3 = 0x80000D470801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_15_RP1_P1_4 = 0x800011470701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_15_RP1_P1_4 = 0x800011470801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_15_RP1_P2_0 = 0x800001470701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_15_RP1_P2_0 = 0x800001470801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_15_RP1_P2_1 = 0x800005470701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_15_RP1_P2_1 = 0x800005470801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_15_RP1_P2_2 = 0x800009470701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_15_RP1_P2_2 = 0x800009470801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_15_RP1_P2_3 = 0x80000D470701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_15_RP1_P2_3 = 0x80000D470801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_15_RP1_P2_4 = 0x800011470701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_15_RP1_P2_4 = 0x800011470801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_15_RP1_P3_0 = 0x8000014707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_15_RP1_P3_0 = 0x8000014708011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_15_RP1_P3_1 = 0x8000054707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_15_RP1_P3_1 = 0x8000054708011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_15_RP1_P3_2 = 0x8000094707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_15_RP1_P3_2 = 0x8000094708011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_15_RP1_P3_3 = 0x80000D4707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_15_RP1_P3_3 = 0x80000D4708011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_15_RP1_P3_4 = 0x8000114707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_15_RP1_P3_4 = 0x8000114708011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP2_P0_0 = 0x800002470701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_15_RP2_P0_0 = 0x800002470701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_15_RP2_P0_0 = 0x800002470801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP2_P0_1 = 0x800006470701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_15_RP2_P0_1 = 0x800006470701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_15_RP2_P0_1 = 0x800006470801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP2_P0_2 = 0x80000A470701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_15_RP2_P0_2 = 0x80000A470701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_15_RP2_P0_2 = 0x80000A470801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP2_P0_3 = 0x80000E470701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_15_RP2_P0_3 = 0x80000E470701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_15_RP2_P0_3 = 0x80000E470801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP2_P0_4 = 0x800012470701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_15_RP2_P0_4 = 0x800012470701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_15_RP2_P0_4 = 0x800012470801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_15_RP2_P1_0 = 0x800002470701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_15_RP2_P1_0 = 0x800002470801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_15_RP2_P1_1 = 0x800006470701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_15_RP2_P1_1 = 0x800006470801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_15_RP2_P1_2 = 0x80000A470701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_15_RP2_P1_2 = 0x80000A470801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_15_RP2_P1_3 = 0x80000E470701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_15_RP2_P1_3 = 0x80000E470801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_15_RP2_P1_4 = 0x800012470701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_15_RP2_P1_4 = 0x800012470801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_15_RP2_P2_0 = 0x800002470701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_15_RP2_P2_0 = 0x800002470801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_15_RP2_P2_1 = 0x800006470701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_15_RP2_P2_1 = 0x800006470801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_15_RP2_P2_2 = 0x80000A470701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_15_RP2_P2_2 = 0x80000A470801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_15_RP2_P2_3 = 0x80000E470701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_15_RP2_P2_3 = 0x80000E470801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_15_RP2_P2_4 = 0x800012470701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_15_RP2_P2_4 = 0x800012470801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_15_RP2_P3_0 = 0x8000024707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_15_RP2_P3_0 = 0x8000024708011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_15_RP2_P3_1 = 0x8000064707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_15_RP2_P3_1 = 0x8000064708011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_15_RP2_P3_2 = 0x80000A4707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_15_RP2_P3_2 = 0x80000A4708011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_15_RP2_P3_3 = 0x80000E4707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_15_RP2_P3_3 = 0x80000E4708011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_15_RP2_P3_4 = 0x8000124707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_15_RP2_P3_4 = 0x8000124708011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP3_P0_0 = 0x800003470701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_15_RP3_P0_0 = 0x800003470701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_15_RP3_P0_0 = 0x800003470801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP3_P0_1 = 0x800007470701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_15_RP3_P0_1 = 0x800007470701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_15_RP3_P0_1 = 0x800007470801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP3_P0_2 = 0x80000B470701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_15_RP3_P0_2 = 0x80000B470701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_15_RP3_P0_2 = 0x80000B470801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP3_P0_3 = 0x80000F470701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_15_RP3_P0_3 = 0x80000F470701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_15_RP3_P0_3 = 0x80000F470801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP3_P0_4 = 0x800013470701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_15_RP3_P0_4 = 0x800013470701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_15_RP3_P0_4 = 0x800013470801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_15_RP3_P1_0 = 0x800003470701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_15_RP3_P1_0 = 0x800003470801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_15_RP3_P1_1 = 0x800007470701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_15_RP3_P1_1 = 0x800007470801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_15_RP3_P1_2 = 0x80000B470701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_15_RP3_P1_2 = 0x80000B470801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_15_RP3_P1_3 = 0x80000F470701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_15_RP3_P1_3 = 0x80000F470801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_15_RP3_P1_4 = 0x800013470701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_15_RP3_P1_4 = 0x800013470801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_15_RP3_P2_0 = 0x800003470701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_15_RP3_P2_0 = 0x800003470801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_15_RP3_P2_1 = 0x800007470701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_15_RP3_P2_1 = 0x800007470801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_15_RP3_P2_2 = 0x80000B470701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_15_RP3_P2_2 = 0x80000B470801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_15_RP3_P2_3 = 0x80000F470701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_15_RP3_P2_3 = 0x80000F470801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_15_RP3_P2_4 = 0x800013470701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_15_RP3_P2_4 = 0x800013470801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_15_RP3_P3_0 = 0x8000034707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_15_RP3_P3_0 = 0x8000034708011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_15_RP3_P3_1 = 0x8000074707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_15_RP3_P3_1 = 0x8000074708011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_15_RP3_P3_2 = 0x80000B4707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_15_RP3_P3_2 = 0x80000B4708011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_15_RP3_P3_3 = 0x80000F4707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_15_RP3_P3_3 = 0x80000F4708011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_15_RP3_P3_4 = 0x8000134707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_15_RP3_P3_4 = 0x8000134708011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP0_P0_0 = 0x800000480701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_16_RP0_P0_0 = 0x800000480701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_16_RP0_P0_0 = 0x800000480801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP0_P0_1 = 0x800004480701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_16_RP0_P0_1 = 0x800004480701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_16_RP0_P0_1 = 0x800004480801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP0_P0_2 = 0x800008480701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_16_RP0_P0_2 = 0x800008480701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_16_RP0_P0_2 = 0x800008480801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP0_P0_3 = 0x80000C480701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_16_RP0_P0_3 = 0x80000C480701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_16_RP0_P0_3 = 0x80000C480801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP0_P0_4 = 0x800010480701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_16_RP0_P0_4 = 0x800010480701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_16_RP0_P0_4 = 0x800010480801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_16_RP0_P1_0 = 0x800000480701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_16_RP0_P1_0 = 0x800000480801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_16_RP0_P1_1 = 0x800004480701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_16_RP0_P1_1 = 0x800004480801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_16_RP0_P1_2 = 0x800008480701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_16_RP0_P1_2 = 0x800008480801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_16_RP0_P1_3 = 0x80000C480701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_16_RP0_P1_3 = 0x80000C480801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_16_RP0_P1_4 = 0x800010480701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_16_RP0_P1_4 = 0x800010480801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_16_RP0_P2_0 = 0x800000480701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_16_RP0_P2_0 = 0x800000480801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_16_RP0_P2_1 = 0x800004480701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_16_RP0_P2_1 = 0x800004480801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_16_RP0_P2_2 = 0x800008480701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_16_RP0_P2_2 = 0x800008480801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_16_RP0_P2_3 = 0x80000C480701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_16_RP0_P2_3 = 0x80000C480801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_16_RP0_P2_4 = 0x800010480701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_16_RP0_P2_4 = 0x800010480801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_16_RP0_P3_0 = 0x8000004807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_16_RP0_P3_0 = 0x8000004808011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_16_RP0_P3_1 = 0x8000044807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_16_RP0_P3_1 = 0x8000044808011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_16_RP0_P3_2 = 0x8000084807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_16_RP0_P3_2 = 0x8000084808011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_16_RP0_P3_3 = 0x80000C4807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_16_RP0_P3_3 = 0x80000C4808011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_16_RP0_P3_4 = 0x8000104807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_16_RP0_P3_4 = 0x8000104808011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP1_P0_0 = 0x800001480701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_16_RP1_P0_0 = 0x800001480701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_16_RP1_P0_0 = 0x800001480801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP1_P0_1 = 0x800005480701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_16_RP1_P0_1 = 0x800005480701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_16_RP1_P0_1 = 0x800005480801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP1_P0_2 = 0x800009480701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_16_RP1_P0_2 = 0x800009480701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_16_RP1_P0_2 = 0x800009480801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP1_P0_3 = 0x80000D480701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_16_RP1_P0_3 = 0x80000D480701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_16_RP1_P0_3 = 0x80000D480801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP1_P0_4 = 0x800011480701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_16_RP1_P0_4 = 0x800011480701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_16_RP1_P0_4 = 0x800011480801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_16_RP1_P1_0 = 0x800001480701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_16_RP1_P1_0 = 0x800001480801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_16_RP1_P1_1 = 0x800005480701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_16_RP1_P1_1 = 0x800005480801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_16_RP1_P1_2 = 0x800009480701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_16_RP1_P1_2 = 0x800009480801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_16_RP1_P1_3 = 0x80000D480701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_16_RP1_P1_3 = 0x80000D480801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_16_RP1_P1_4 = 0x800011480701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_16_RP1_P1_4 = 0x800011480801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_16_RP1_P2_0 = 0x800001480701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_16_RP1_P2_0 = 0x800001480801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_16_RP1_P2_1 = 0x800005480701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_16_RP1_P2_1 = 0x800005480801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_16_RP1_P2_2 = 0x800009480701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_16_RP1_P2_2 = 0x800009480801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_16_RP1_P2_3 = 0x80000D480701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_16_RP1_P2_3 = 0x80000D480801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_16_RP1_P2_4 = 0x800011480701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_16_RP1_P2_4 = 0x800011480801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_16_RP1_P3_0 = 0x8000014807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_16_RP1_P3_0 = 0x8000014808011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_16_RP1_P3_1 = 0x8000054807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_16_RP1_P3_1 = 0x8000054808011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_16_RP1_P3_2 = 0x8000094807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_16_RP1_P3_2 = 0x8000094808011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_16_RP1_P3_3 = 0x80000D4807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_16_RP1_P3_3 = 0x80000D4808011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_16_RP1_P3_4 = 0x8000114807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_16_RP1_P3_4 = 0x8000114808011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP2_P0_0 = 0x800002480701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_16_RP2_P0_0 = 0x800002480701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_16_RP2_P0_0 = 0x800002480801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP2_P0_1 = 0x800006480701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_16_RP2_P0_1 = 0x800006480701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_16_RP2_P0_1 = 0x800006480801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP2_P0_2 = 0x80000A480701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_16_RP2_P0_2 = 0x80000A480701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_16_RP2_P0_2 = 0x80000A480801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP2_P0_3 = 0x80000E480701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_16_RP2_P0_3 = 0x80000E480701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_16_RP2_P0_3 = 0x80000E480801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP2_P0_4 = 0x800012480701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_16_RP2_P0_4 = 0x800012480701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_16_RP2_P0_4 = 0x800012480801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_16_RP2_P1_0 = 0x800002480701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_16_RP2_P1_0 = 0x800002480801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_16_RP2_P1_1 = 0x800006480701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_16_RP2_P1_1 = 0x800006480801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_16_RP2_P1_2 = 0x80000A480701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_16_RP2_P1_2 = 0x80000A480801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_16_RP2_P1_3 = 0x80000E480701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_16_RP2_P1_3 = 0x80000E480801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_16_RP2_P1_4 = 0x800012480701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_16_RP2_P1_4 = 0x800012480801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_16_RP2_P2_0 = 0x800002480701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_16_RP2_P2_0 = 0x800002480801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_16_RP2_P2_1 = 0x800006480701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_16_RP2_P2_1 = 0x800006480801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_16_RP2_P2_2 = 0x80000A480701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_16_RP2_P2_2 = 0x80000A480801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_16_RP2_P2_3 = 0x80000E480701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_16_RP2_P2_3 = 0x80000E480801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_16_RP2_P2_4 = 0x800012480701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_16_RP2_P2_4 = 0x800012480801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_16_RP2_P3_0 = 0x8000024807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_16_RP2_P3_0 = 0x8000024808011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_16_RP2_P3_1 = 0x8000064807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_16_RP2_P3_1 = 0x8000064808011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_16_RP2_P3_2 = 0x80000A4807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_16_RP2_P3_2 = 0x80000A4808011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_16_RP2_P3_3 = 0x80000E4807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_16_RP2_P3_3 = 0x80000E4808011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_16_RP2_P3_4 = 0x8000124807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_16_RP2_P3_4 = 0x8000124808011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP3_P0_0 = 0x800003480701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_16_RP3_P0_0 = 0x800003480701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_16_RP3_P0_0 = 0x800003480801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP3_P0_1 = 0x800007480701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_16_RP3_P0_1 = 0x800007480701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_16_RP3_P0_1 = 0x800007480801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP3_P0_2 = 0x80000B480701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_16_RP3_P0_2 = 0x80000B480701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_16_RP3_P0_2 = 0x80000B480801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP3_P0_3 = 0x80000F480701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_16_RP3_P0_3 = 0x80000F480701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_16_RP3_P0_3 = 0x80000F480801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP3_P0_4 = 0x800013480701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_16_RP3_P0_4 = 0x800013480701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_16_RP3_P0_4 = 0x800013480801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_16_RP3_P1_0 = 0x800003480701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_16_RP3_P1_0 = 0x800003480801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_16_RP3_P1_1 = 0x800007480701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_16_RP3_P1_1 = 0x800007480801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_16_RP3_P1_2 = 0x80000B480701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_16_RP3_P1_2 = 0x80000B480801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_16_RP3_P1_3 = 0x80000F480701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_16_RP3_P1_3 = 0x80000F480801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_16_RP3_P1_4 = 0x800013480701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_16_RP3_P1_4 = 0x800013480801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_16_RP3_P2_0 = 0x800003480701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_16_RP3_P2_0 = 0x800003480801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_16_RP3_P2_1 = 0x800007480701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_16_RP3_P2_1 = 0x800007480801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_16_RP3_P2_2 = 0x80000B480701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_16_RP3_P2_2 = 0x80000B480801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_16_RP3_P2_3 = 0x80000F480701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_16_RP3_P2_3 = 0x80000F480801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_16_RP3_P2_4 = 0x800013480701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_16_RP3_P2_4 = 0x800013480801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_16_RP3_P3_0 = 0x8000034807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_16_RP3_P3_0 = 0x8000034808011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_16_RP3_P3_1 = 0x8000074807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_16_RP3_P3_1 = 0x8000074808011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_16_RP3_P3_2 = 0x80000B4807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_16_RP3_P3_2 = 0x80000B4808011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_16_RP3_P3_3 = 0x80000F4807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_16_RP3_P3_3 = 0x80000F4808011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_16_RP3_P3_4 = 0x8000134807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_16_RP3_P3_4 = 0x8000134808011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP0_P0_0 = 0x8000004A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_18_RP0_P0_0 = 0x8000004A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_18_RP0_P0_0 = 0x8000004A0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP0_P0_1 = 0x8000044A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_18_RP0_P0_1 = 0x8000044A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_18_RP0_P0_1 = 0x8000044A0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP0_P0_2 = 0x8000084A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_18_RP0_P0_2 = 0x8000084A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_18_RP0_P0_2 = 0x8000084A0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP0_P0_3 = 0x80000C4A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_18_RP0_P0_3 = 0x80000C4A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_18_RP0_P0_3 = 0x80000C4A0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP0_P0_4 = 0x8000104A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_18_RP0_P0_4 = 0x8000104A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_18_RP0_P0_4 = 0x8000104A0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_18_RP0_P1_0 = 0x8000004A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_18_RP0_P1_0 = 0x8000004A0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_18_RP0_P1_1 = 0x8000044A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_18_RP0_P1_1 = 0x8000044A0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_18_RP0_P1_2 = 0x8000084A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_18_RP0_P1_2 = 0x8000084A0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_18_RP0_P1_3 = 0x80000C4A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_18_RP0_P1_3 = 0x80000C4A0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_18_RP0_P1_4 = 0x8000104A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_18_RP0_P1_4 = 0x8000104A0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_18_RP0_P2_0 = 0x8000004A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_18_RP0_P2_0 = 0x8000004A0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_18_RP0_P2_1 = 0x8000044A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_18_RP0_P2_1 = 0x8000044A0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_18_RP0_P2_2 = 0x8000084A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_18_RP0_P2_2 = 0x8000084A0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_18_RP0_P2_3 = 0x80000C4A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_18_RP0_P2_3 = 0x80000C4A0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_18_RP0_P2_4 = 0x8000104A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_18_RP0_P2_4 = 0x8000104A0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_18_RP0_P3_0 = 0x8000004A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_18_RP0_P3_0 = 0x8000004A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_18_RP0_P3_1 = 0x8000044A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_18_RP0_P3_1 = 0x8000044A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_18_RP0_P3_2 = 0x8000084A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_18_RP0_P3_2 = 0x8000084A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_18_RP0_P3_3 = 0x80000C4A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_18_RP0_P3_3 = 0x80000C4A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_18_RP0_P3_4 = 0x8000104A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_18_RP0_P3_4 = 0x8000104A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP1_P0_0 = 0x8000014A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_18_RP1_P0_0 = 0x8000014A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_18_RP1_P0_0 = 0x8000014A0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP1_P0_1 = 0x8000054A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_18_RP1_P0_1 = 0x8000054A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_18_RP1_P0_1 = 0x8000054A0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP1_P0_2 = 0x8000094A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_18_RP1_P0_2 = 0x8000094A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_18_RP1_P0_2 = 0x8000094A0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP1_P0_3 = 0x80000D4A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_18_RP1_P0_3 = 0x80000D4A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_18_RP1_P0_3 = 0x80000D4A0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP1_P0_4 = 0x8000114A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_18_RP1_P0_4 = 0x8000114A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_18_RP1_P0_4 = 0x8000114A0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_18_RP1_P1_0 = 0x8000014A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_18_RP1_P1_0 = 0x8000014A0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_18_RP1_P1_1 = 0x8000054A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_18_RP1_P1_1 = 0x8000054A0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_18_RP1_P1_2 = 0x8000094A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_18_RP1_P1_2 = 0x8000094A0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_18_RP1_P1_3 = 0x80000D4A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_18_RP1_P1_3 = 0x80000D4A0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_18_RP1_P1_4 = 0x8000114A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_18_RP1_P1_4 = 0x8000114A0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_18_RP1_P2_0 = 0x8000014A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_18_RP1_P2_0 = 0x8000014A0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_18_RP1_P2_1 = 0x8000054A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_18_RP1_P2_1 = 0x8000054A0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_18_RP1_P2_2 = 0x8000094A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_18_RP1_P2_2 = 0x8000094A0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_18_RP1_P2_3 = 0x80000D4A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_18_RP1_P2_3 = 0x80000D4A0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_18_RP1_P2_4 = 0x8000114A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_18_RP1_P2_4 = 0x8000114A0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_18_RP1_P3_0 = 0x8000014A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_18_RP1_P3_0 = 0x8000014A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_18_RP1_P3_1 = 0x8000054A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_18_RP1_P3_1 = 0x8000054A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_18_RP1_P3_2 = 0x8000094A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_18_RP1_P3_2 = 0x8000094A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_18_RP1_P3_3 = 0x80000D4A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_18_RP1_P3_3 = 0x80000D4A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_18_RP1_P3_4 = 0x8000114A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_18_RP1_P3_4 = 0x8000114A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP2_P0_0 = 0x8000024A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_18_RP2_P0_0 = 0x8000024A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_18_RP2_P0_0 = 0x8000024A0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP2_P0_1 = 0x8000064A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_18_RP2_P0_1 = 0x8000064A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_18_RP2_P0_1 = 0x8000064A0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP2_P0_2 = 0x80000A4A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_18_RP2_P0_2 = 0x80000A4A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_18_RP2_P0_2 = 0x80000A4A0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP2_P0_3 = 0x80000E4A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_18_RP2_P0_3 = 0x80000E4A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_18_RP2_P0_3 = 0x80000E4A0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP2_P0_4 = 0x8000124A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_18_RP2_P0_4 = 0x8000124A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_18_RP2_P0_4 = 0x8000124A0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_18_RP2_P1_0 = 0x8000024A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_18_RP2_P1_0 = 0x8000024A0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_18_RP2_P1_1 = 0x8000064A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_18_RP2_P1_1 = 0x8000064A0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_18_RP2_P1_2 = 0x80000A4A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_18_RP2_P1_2 = 0x80000A4A0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_18_RP2_P1_3 = 0x80000E4A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_18_RP2_P1_3 = 0x80000E4A0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_18_RP2_P1_4 = 0x8000124A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_18_RP2_P1_4 = 0x8000124A0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_18_RP2_P2_0 = 0x8000024A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_18_RP2_P2_0 = 0x8000024A0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_18_RP2_P2_1 = 0x8000064A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_18_RP2_P2_1 = 0x8000064A0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_18_RP2_P2_2 = 0x80000A4A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_18_RP2_P2_2 = 0x80000A4A0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_18_RP2_P2_3 = 0x80000E4A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_18_RP2_P2_3 = 0x80000E4A0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_18_RP2_P2_4 = 0x8000124A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_18_RP2_P2_4 = 0x8000124A0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_18_RP2_P3_0 = 0x8000024A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_18_RP2_P3_0 = 0x8000024A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_18_RP2_P3_1 = 0x8000064A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_18_RP2_P3_1 = 0x8000064A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_18_RP2_P3_2 = 0x80000A4A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_18_RP2_P3_2 = 0x80000A4A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_18_RP2_P3_3 = 0x80000E4A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_18_RP2_P3_3 = 0x80000E4A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_18_RP2_P3_4 = 0x8000124A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_18_RP2_P3_4 = 0x8000124A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP3_P0_0 = 0x8000034A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_18_RP3_P0_0 = 0x8000034A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_18_RP3_P0_0 = 0x8000034A0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP3_P0_1 = 0x8000074A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_18_RP3_P0_1 = 0x8000074A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_18_RP3_P0_1 = 0x8000074A0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP3_P0_2 = 0x80000B4A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_18_RP3_P0_2 = 0x80000B4A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_18_RP3_P0_2 = 0x80000B4A0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP3_P0_3 = 0x80000F4A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_18_RP3_P0_3 = 0x80000F4A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_18_RP3_P0_3 = 0x80000F4A0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP3_P0_4 = 0x8000134A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_18_RP3_P0_4 = 0x8000134A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_18_RP3_P0_4 = 0x8000134A0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_18_RP3_P1_0 = 0x8000034A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_18_RP3_P1_0 = 0x8000034A0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_18_RP3_P1_1 = 0x8000074A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_18_RP3_P1_1 = 0x8000074A0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_18_RP3_P1_2 = 0x80000B4A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_18_RP3_P1_2 = 0x80000B4A0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_18_RP3_P1_3 = 0x80000F4A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_18_RP3_P1_3 = 0x80000F4A0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_18_RP3_P1_4 = 0x8000134A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_18_RP3_P1_4 = 0x8000134A0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_18_RP3_P2_0 = 0x8000034A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_18_RP3_P2_0 = 0x8000034A0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_18_RP3_P2_1 = 0x8000074A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_18_RP3_P2_1 = 0x8000074A0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_18_RP3_P2_2 = 0x80000B4A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_18_RP3_P2_2 = 0x80000B4A0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_18_RP3_P2_3 = 0x80000F4A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_18_RP3_P2_3 = 0x80000F4A0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_18_RP3_P2_4 = 0x8000134A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_18_RP3_P2_4 = 0x8000134A0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_18_RP3_P3_0 = 0x8000034A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_18_RP3_P3_0 = 0x8000034A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_18_RP3_P3_1 = 0x8000074A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_18_RP3_P3_1 = 0x8000074A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_18_RP3_P3_2 = 0x80000B4A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_18_RP3_P3_2 = 0x80000B4A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_18_RP3_P3_3 = 0x80000F4A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_18_RP3_P3_3 = 0x80000F4A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_18_RP3_P3_4 = 0x8000134A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_18_RP3_P3_4 = 0x8000134A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP0_P0_0 = 0x800000390701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_1_RP0_P0_0 = 0x800000390701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_1_RP0_P0_0 = 0x800000390801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP0_P0_1 = 0x800004390701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_1_RP0_P0_1 = 0x800004390701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_1_RP0_P0_1 = 0x800004390801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP0_P0_2 = 0x800008390701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_1_RP0_P0_2 = 0x800008390701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_1_RP0_P0_2 = 0x800008390801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP0_P0_3 = 0x80000C390701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_1_RP0_P0_3 = 0x80000C390701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_1_RP0_P0_3 = 0x80000C390801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP0_P0_4 = 0x800010390701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_1_RP0_P0_4 = 0x800010390701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_1_RP0_P0_4 = 0x800010390801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_1_RP0_P1_0 = 0x800000390701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_1_RP0_P1_0 = 0x800000390801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_1_RP0_P1_1 = 0x800004390701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_1_RP0_P1_1 = 0x800004390801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_1_RP0_P1_2 = 0x800008390701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_1_RP0_P1_2 = 0x800008390801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_1_RP0_P1_3 = 0x80000C390701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_1_RP0_P1_3 = 0x80000C390801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_1_RP0_P1_4 = 0x800010390701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_1_RP0_P1_4 = 0x800010390801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_1_RP0_P2_0 = 0x800000390701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_1_RP0_P2_0 = 0x800000390801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_1_RP0_P2_1 = 0x800004390701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_1_RP0_P2_1 = 0x800004390801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_1_RP0_P2_2 = 0x800008390701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_1_RP0_P2_2 = 0x800008390801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_1_RP0_P2_3 = 0x80000C390701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_1_RP0_P2_3 = 0x80000C390801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_1_RP0_P2_4 = 0x800010390701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_1_RP0_P2_4 = 0x800010390801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_1_RP0_P3_0 = 0x8000003907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_1_RP0_P3_0 = 0x8000003908011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_1_RP0_P3_1 = 0x8000043907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_1_RP0_P3_1 = 0x8000043908011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_1_RP0_P3_2 = 0x8000083907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_1_RP0_P3_2 = 0x8000083908011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_1_RP0_P3_3 = 0x80000C3907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_1_RP0_P3_3 = 0x80000C3908011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_1_RP0_P3_4 = 0x8000103907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_1_RP0_P3_4 = 0x8000103908011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP1_P0_0 = 0x800001390701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_1_RP1_P0_0 = 0x800001390701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_1_RP1_P0_0 = 0x800001390801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP1_P0_1 = 0x800005390701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_1_RP1_P0_1 = 0x800005390701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_1_RP1_P0_1 = 0x800005390801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP1_P0_2 = 0x800009390701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_1_RP1_P0_2 = 0x800009390701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_1_RP1_P0_2 = 0x800009390801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP1_P0_3 = 0x80000D390701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_1_RP1_P0_3 = 0x80000D390701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_1_RP1_P0_3 = 0x80000D390801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP1_P0_4 = 0x800011390701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_1_RP1_P0_4 = 0x800011390701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_1_RP1_P0_4 = 0x800011390801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_1_RP1_P1_0 = 0x800001390701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_1_RP1_P1_0 = 0x800001390801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_1_RP1_P1_1 = 0x800005390701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_1_RP1_P1_1 = 0x800005390801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_1_RP1_P1_2 = 0x800009390701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_1_RP1_P1_2 = 0x800009390801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_1_RP1_P1_3 = 0x80000D390701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_1_RP1_P1_3 = 0x80000D390801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_1_RP1_P1_4 = 0x800011390701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_1_RP1_P1_4 = 0x800011390801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_1_RP1_P2_0 = 0x800001390701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_1_RP1_P2_0 = 0x800001390801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_1_RP1_P2_1 = 0x800005390701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_1_RP1_P2_1 = 0x800005390801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_1_RP1_P2_2 = 0x800009390701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_1_RP1_P2_2 = 0x800009390801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_1_RP1_P2_3 = 0x80000D390701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_1_RP1_P2_3 = 0x80000D390801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_1_RP1_P2_4 = 0x800011390701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_1_RP1_P2_4 = 0x800011390801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_1_RP1_P3_0 = 0x8000013907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_1_RP1_P3_0 = 0x8000013908011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_1_RP1_P3_1 = 0x8000053907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_1_RP1_P3_1 = 0x8000053908011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_1_RP1_P3_2 = 0x8000093907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_1_RP1_P3_2 = 0x8000093908011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_1_RP1_P3_3 = 0x80000D3907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_1_RP1_P3_3 = 0x80000D3908011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_1_RP1_P3_4 = 0x8000113907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_1_RP1_P3_4 = 0x8000113908011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP2_P0_0 = 0x800002390701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_1_RP2_P0_0 = 0x800002390701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_1_RP2_P0_0 = 0x800002390801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP2_P0_1 = 0x800006390701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_1_RP2_P0_1 = 0x800006390701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_1_RP2_P0_1 = 0x800006390801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP2_P0_2 = 0x80000A390701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_1_RP2_P0_2 = 0x80000A390701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_1_RP2_P0_2 = 0x80000A390801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP2_P0_3 = 0x80000E390701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_1_RP2_P0_3 = 0x80000E390701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_1_RP2_P0_3 = 0x80000E390801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP2_P0_4 = 0x800012390701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_1_RP2_P0_4 = 0x800012390701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_1_RP2_P0_4 = 0x800012390801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_1_RP2_P1_0 = 0x800002390701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_1_RP2_P1_0 = 0x800002390801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_1_RP2_P1_1 = 0x800006390701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_1_RP2_P1_1 = 0x800006390801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_1_RP2_P1_2 = 0x80000A390701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_1_RP2_P1_2 = 0x80000A390801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_1_RP2_P1_3 = 0x80000E390701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_1_RP2_P1_3 = 0x80000E390801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_1_RP2_P1_4 = 0x800012390701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_1_RP2_P1_4 = 0x800012390801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_1_RP2_P2_0 = 0x800002390701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_1_RP2_P2_0 = 0x800002390801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_1_RP2_P2_1 = 0x800006390701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_1_RP2_P2_1 = 0x800006390801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_1_RP2_P2_2 = 0x80000A390701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_1_RP2_P2_2 = 0x80000A390801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_1_RP2_P2_3 = 0x80000E390701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_1_RP2_P2_3 = 0x80000E390801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_1_RP2_P2_4 = 0x800012390701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_1_RP2_P2_4 = 0x800012390801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_1_RP2_P3_0 = 0x8000023907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_1_RP2_P3_0 = 0x8000023908011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_1_RP2_P3_1 = 0x8000063907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_1_RP2_P3_1 = 0x8000063908011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_1_RP2_P3_2 = 0x80000A3907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_1_RP2_P3_2 = 0x80000A3908011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_1_RP2_P3_3 = 0x80000E3907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_1_RP2_P3_3 = 0x80000E3908011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_1_RP2_P3_4 = 0x8000123907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_1_RP2_P3_4 = 0x8000123908011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP3_P0_0 = 0x800003390701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_1_RP3_P0_0 = 0x800003390701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_1_RP3_P0_0 = 0x800003390801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP3_P0_1 = 0x800007390701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_1_RP3_P0_1 = 0x800007390701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_1_RP3_P0_1 = 0x800007390801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP3_P0_2 = 0x80000B390701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_1_RP3_P0_2 = 0x80000B390701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_1_RP3_P0_2 = 0x80000B390801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP3_P0_3 = 0x80000F390701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_1_RP3_P0_3 = 0x80000F390701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_1_RP3_P0_3 = 0x80000F390801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP3_P0_4 = 0x800013390701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_1_RP3_P0_4 = 0x800013390701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_1_RP3_P0_4 = 0x800013390801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_1_RP3_P1_0 = 0x800003390701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_1_RP3_P1_0 = 0x800003390801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_1_RP3_P1_1 = 0x800007390701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_1_RP3_P1_1 = 0x800007390801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_1_RP3_P1_2 = 0x80000B390701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_1_RP3_P1_2 = 0x80000B390801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_1_RP3_P1_3 = 0x80000F390701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_1_RP3_P1_3 = 0x80000F390801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_1_RP3_P1_4 = 0x800013390701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_1_RP3_P1_4 = 0x800013390801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_1_RP3_P2_0 = 0x800003390701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_1_RP3_P2_0 = 0x800003390801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_1_RP3_P2_1 = 0x800007390701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_1_RP3_P2_1 = 0x800007390801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_1_RP3_P2_2 = 0x80000B390701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_1_RP3_P2_2 = 0x80000B390801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_1_RP3_P2_3 = 0x80000F390701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_1_RP3_P2_3 = 0x80000F390801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_1_RP3_P2_4 = 0x800013390701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_1_RP3_P2_4 = 0x800013390801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_1_RP3_P3_0 = 0x8000033907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_1_RP3_P3_0 = 0x8000033908011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_1_RP3_P3_1 = 0x8000073907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_1_RP3_P3_1 = 0x8000073908011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_1_RP3_P3_2 = 0x80000B3907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_1_RP3_P3_2 = 0x80000B3908011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_1_RP3_P3_3 = 0x80000F3907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_1_RP3_P3_3 = 0x80000F3908011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_1_RP3_P3_4 = 0x8000133907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_1_RP3_P3_4 = 0x8000133908011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP0_P0_0 = 0x8000004C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_20_RP0_P0_0 = 0x8000004C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_20_RP0_P0_0 = 0x8000004C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP0_P0_1 = 0x8000044C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_20_RP0_P0_1 = 0x8000044C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_20_RP0_P0_1 = 0x8000044C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP0_P0_2 = 0x8000084C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_20_RP0_P0_2 = 0x8000084C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_20_RP0_P0_2 = 0x8000084C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP0_P0_3 = 0x80000C4C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_20_RP0_P0_3 = 0x80000C4C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_20_RP0_P0_3 = 0x80000C4C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP0_P0_4 = 0x8000104C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_20_RP0_P0_4 = 0x8000104C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_20_RP0_P0_4 = 0x8000104C0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_20_RP0_P1_0 = 0x8000004C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_20_RP0_P1_0 = 0x8000004C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_20_RP0_P1_1 = 0x8000044C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_20_RP0_P1_1 = 0x8000044C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_20_RP0_P1_2 = 0x8000084C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_20_RP0_P1_2 = 0x8000084C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_20_RP0_P1_3 = 0x80000C4C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_20_RP0_P1_3 = 0x80000C4C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_20_RP0_P1_4 = 0x8000104C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_20_RP0_P1_4 = 0x8000104C0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_20_RP0_P2_0 = 0x8000004C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_20_RP0_P2_0 = 0x8000004C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_20_RP0_P2_1 = 0x8000044C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_20_RP0_P2_1 = 0x8000044C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_20_RP0_P2_2 = 0x8000084C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_20_RP0_P2_2 = 0x8000084C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_20_RP0_P2_3 = 0x80000C4C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_20_RP0_P2_3 = 0x80000C4C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_20_RP0_P2_4 = 0x8000104C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_20_RP0_P2_4 = 0x8000104C0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_20_RP0_P3_0 = 0x8000004C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_20_RP0_P3_0 = 0x8000004C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_20_RP0_P3_1 = 0x8000044C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_20_RP0_P3_1 = 0x8000044C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_20_RP0_P3_2 = 0x8000084C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_20_RP0_P3_2 = 0x8000084C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_20_RP0_P3_3 = 0x80000C4C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_20_RP0_P3_3 = 0x80000C4C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_20_RP0_P3_4 = 0x8000104C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_20_RP0_P3_4 = 0x8000104C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP1_P0_0 = 0x8000014C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_20_RP1_P0_0 = 0x8000014C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_20_RP1_P0_0 = 0x8000014C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP1_P0_1 = 0x8000054C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_20_RP1_P0_1 = 0x8000054C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_20_RP1_P0_1 = 0x8000054C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP1_P0_2 = 0x8000094C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_20_RP1_P0_2 = 0x8000094C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_20_RP1_P0_2 = 0x8000094C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP1_P0_3 = 0x80000D4C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_20_RP1_P0_3 = 0x80000D4C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_20_RP1_P0_3 = 0x80000D4C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP1_P0_4 = 0x8000114C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_20_RP1_P0_4 = 0x8000114C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_20_RP1_P0_4 = 0x8000114C0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_20_RP1_P1_0 = 0x8000014C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_20_RP1_P1_0 = 0x8000014C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_20_RP1_P1_1 = 0x8000054C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_20_RP1_P1_1 = 0x8000054C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_20_RP1_P1_2 = 0x8000094C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_20_RP1_P1_2 = 0x8000094C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_20_RP1_P1_3 = 0x80000D4C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_20_RP1_P1_3 = 0x80000D4C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_20_RP1_P1_4 = 0x8000114C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_20_RP1_P1_4 = 0x8000114C0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_20_RP1_P2_0 = 0x8000014C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_20_RP1_P2_0 = 0x8000014C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_20_RP1_P2_1 = 0x8000054C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_20_RP1_P2_1 = 0x8000054C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_20_RP1_P2_2 = 0x8000094C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_20_RP1_P2_2 = 0x8000094C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_20_RP1_P2_3 = 0x80000D4C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_20_RP1_P2_3 = 0x80000D4C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_20_RP1_P2_4 = 0x8000114C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_20_RP1_P2_4 = 0x8000114C0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_20_RP1_P3_0 = 0x8000014C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_20_RP1_P3_0 = 0x8000014C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_20_RP1_P3_1 = 0x8000054C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_20_RP1_P3_1 = 0x8000054C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_20_RP1_P3_2 = 0x8000094C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_20_RP1_P3_2 = 0x8000094C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_20_RP1_P3_3 = 0x80000D4C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_20_RP1_P3_3 = 0x80000D4C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_20_RP1_P3_4 = 0x8000114C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_20_RP1_P3_4 = 0x8000114C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP2_P0_0 = 0x8000024C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_20_RP2_P0_0 = 0x8000024C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_20_RP2_P0_0 = 0x8000024C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP2_P0_1 = 0x8000064C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_20_RP2_P0_1 = 0x8000064C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_20_RP2_P0_1 = 0x8000064C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP2_P0_2 = 0x80000A4C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_20_RP2_P0_2 = 0x80000A4C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_20_RP2_P0_2 = 0x80000A4C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP2_P0_3 = 0x80000E4C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_20_RP2_P0_3 = 0x80000E4C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_20_RP2_P0_3 = 0x80000E4C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP2_P0_4 = 0x8000124C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_20_RP2_P0_4 = 0x8000124C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_20_RP2_P0_4 = 0x8000124C0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_20_RP2_P1_0 = 0x8000024C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_20_RP2_P1_0 = 0x8000024C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_20_RP2_P1_1 = 0x8000064C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_20_RP2_P1_1 = 0x8000064C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_20_RP2_P1_2 = 0x80000A4C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_20_RP2_P1_2 = 0x80000A4C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_20_RP2_P1_3 = 0x80000E4C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_20_RP2_P1_3 = 0x80000E4C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_20_RP2_P1_4 = 0x8000124C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_20_RP2_P1_4 = 0x8000124C0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_20_RP2_P2_0 = 0x8000024C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_20_RP2_P2_0 = 0x8000024C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_20_RP2_P2_1 = 0x8000064C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_20_RP2_P2_1 = 0x8000064C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_20_RP2_P2_2 = 0x80000A4C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_20_RP2_P2_2 = 0x80000A4C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_20_RP2_P2_3 = 0x80000E4C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_20_RP2_P2_3 = 0x80000E4C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_20_RP2_P2_4 = 0x8000124C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_20_RP2_P2_4 = 0x8000124C0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_20_RP2_P3_0 = 0x8000024C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_20_RP2_P3_0 = 0x8000024C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_20_RP2_P3_1 = 0x8000064C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_20_RP2_P3_1 = 0x8000064C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_20_RP2_P3_2 = 0x80000A4C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_20_RP2_P3_2 = 0x80000A4C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_20_RP2_P3_3 = 0x80000E4C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_20_RP2_P3_3 = 0x80000E4C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_20_RP2_P3_4 = 0x8000124C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_20_RP2_P3_4 = 0x8000124C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP3_P0_0 = 0x8000034C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_20_RP3_P0_0 = 0x8000034C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_20_RP3_P0_0 = 0x8000034C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP3_P0_1 = 0x8000074C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_20_RP3_P0_1 = 0x8000074C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_20_RP3_P0_1 = 0x8000074C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP3_P0_2 = 0x80000B4C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_20_RP3_P0_2 = 0x80000B4C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_20_RP3_P0_2 = 0x80000B4C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP3_P0_3 = 0x80000F4C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_20_RP3_P0_3 = 0x80000F4C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_20_RP3_P0_3 = 0x80000F4C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP3_P0_4 = 0x8000134C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_20_RP3_P0_4 = 0x8000134C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_20_RP3_P0_4 = 0x8000134C0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_20_RP3_P1_0 = 0x8000034C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_20_RP3_P1_0 = 0x8000034C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_20_RP3_P1_1 = 0x8000074C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_20_RP3_P1_1 = 0x8000074C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_20_RP3_P1_2 = 0x80000B4C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_20_RP3_P1_2 = 0x80000B4C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_20_RP3_P1_3 = 0x80000F4C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_20_RP3_P1_3 = 0x80000F4C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_20_RP3_P1_4 = 0x8000134C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_20_RP3_P1_4 = 0x8000134C0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_20_RP3_P2_0 = 0x8000034C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_20_RP3_P2_0 = 0x8000034C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_20_RP3_P2_1 = 0x8000074C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_20_RP3_P2_1 = 0x8000074C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_20_RP3_P2_2 = 0x80000B4C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_20_RP3_P2_2 = 0x80000B4C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_20_RP3_P2_3 = 0x80000F4C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_20_RP3_P2_3 = 0x80000F4C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_20_RP3_P2_4 = 0x8000134C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_20_RP3_P2_4 = 0x8000134C0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_20_RP3_P3_0 = 0x8000034C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_20_RP3_P3_0 = 0x8000034C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_20_RP3_P3_1 = 0x8000074C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_20_RP3_P3_1 = 0x8000074C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_20_RP3_P3_2 = 0x80000B4C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_20_RP3_P3_2 = 0x80000B4C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_20_RP3_P3_3 = 0x80000F4C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_20_RP3_P3_3 = 0x80000F4C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_20_RP3_P3_4 = 0x8000134C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_20_RP3_P3_4 = 0x8000134C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP0_P0_0 = 0x8000004E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_22_RP0_P0_0 = 0x8000004E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_22_RP0_P0_0 = 0x8000004E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP0_P0_1 = 0x8000044E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_22_RP0_P0_1 = 0x8000044E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_22_RP0_P0_1 = 0x8000044E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP0_P0_2 = 0x8000084E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_22_RP0_P0_2 = 0x8000084E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_22_RP0_P0_2 = 0x8000084E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP0_P0_3 = 0x80000C4E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_22_RP0_P0_3 = 0x80000C4E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_22_RP0_P0_3 = 0x80000C4E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP0_P0_4 = 0x8000104E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_22_RP0_P0_4 = 0x8000104E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_22_RP0_P0_4 = 0x8000104E0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_22_RP0_P1_0 = 0x8000004E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_22_RP0_P1_0 = 0x8000004E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_22_RP0_P1_1 = 0x8000044E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_22_RP0_P1_1 = 0x8000044E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_22_RP0_P1_2 = 0x8000084E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_22_RP0_P1_2 = 0x8000084E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_22_RP0_P1_3 = 0x80000C4E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_22_RP0_P1_3 = 0x80000C4E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_22_RP0_P1_4 = 0x8000104E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_22_RP0_P1_4 = 0x8000104E0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_22_RP0_P2_0 = 0x8000004E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_22_RP0_P2_0 = 0x8000004E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_22_RP0_P2_1 = 0x8000044E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_22_RP0_P2_1 = 0x8000044E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_22_RP0_P2_2 = 0x8000084E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_22_RP0_P2_2 = 0x8000084E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_22_RP0_P2_3 = 0x80000C4E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_22_RP0_P2_3 = 0x80000C4E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_22_RP0_P2_4 = 0x8000104E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_22_RP0_P2_4 = 0x8000104E0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_22_RP0_P3_0 = 0x8000004E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_22_RP0_P3_0 = 0x8000004E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_22_RP0_P3_1 = 0x8000044E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_22_RP0_P3_1 = 0x8000044E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_22_RP0_P3_2 = 0x8000084E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_22_RP0_P3_2 = 0x8000084E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_22_RP0_P3_3 = 0x80000C4E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_22_RP0_P3_3 = 0x80000C4E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_22_RP0_P3_4 = 0x8000104E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_22_RP0_P3_4 = 0x8000104E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP1_P0_0 = 0x8000014E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_22_RP1_P0_0 = 0x8000014E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_22_RP1_P0_0 = 0x8000014E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP1_P0_1 = 0x8000054E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_22_RP1_P0_1 = 0x8000054E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_22_RP1_P0_1 = 0x8000054E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP1_P0_2 = 0x8000094E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_22_RP1_P0_2 = 0x8000094E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_22_RP1_P0_2 = 0x8000094E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP1_P0_3 = 0x80000D4E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_22_RP1_P0_3 = 0x80000D4E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_22_RP1_P0_3 = 0x80000D4E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP1_P0_4 = 0x8000114E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_22_RP1_P0_4 = 0x8000114E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_22_RP1_P0_4 = 0x8000114E0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_22_RP1_P1_0 = 0x8000014E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_22_RP1_P1_0 = 0x8000014E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_22_RP1_P1_1 = 0x8000054E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_22_RP1_P1_1 = 0x8000054E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_22_RP1_P1_2 = 0x8000094E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_22_RP1_P1_2 = 0x8000094E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_22_RP1_P1_3 = 0x80000D4E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_22_RP1_P1_3 = 0x80000D4E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_22_RP1_P1_4 = 0x8000114E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_22_RP1_P1_4 = 0x8000114E0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_22_RP1_P2_0 = 0x8000014E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_22_RP1_P2_0 = 0x8000014E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_22_RP1_P2_1 = 0x8000054E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_22_RP1_P2_1 = 0x8000054E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_22_RP1_P2_2 = 0x8000094E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_22_RP1_P2_2 = 0x8000094E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_22_RP1_P2_3 = 0x80000D4E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_22_RP1_P2_3 = 0x80000D4E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_22_RP1_P2_4 = 0x8000114E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_22_RP1_P2_4 = 0x8000114E0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_22_RP1_P3_0 = 0x8000014E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_22_RP1_P3_0 = 0x8000014E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_22_RP1_P3_1 = 0x8000054E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_22_RP1_P3_1 = 0x8000054E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_22_RP1_P3_2 = 0x8000094E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_22_RP1_P3_2 = 0x8000094E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_22_RP1_P3_3 = 0x80000D4E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_22_RP1_P3_3 = 0x80000D4E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_22_RP1_P3_4 = 0x8000114E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_22_RP1_P3_4 = 0x8000114E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP2_P0_0 = 0x8000024E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_22_RP2_P0_0 = 0x8000024E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_22_RP2_P0_0 = 0x8000024E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP2_P0_1 = 0x8000064E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_22_RP2_P0_1 = 0x8000064E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_22_RP2_P0_1 = 0x8000064E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP2_P0_2 = 0x80000A4E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_22_RP2_P0_2 = 0x80000A4E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_22_RP2_P0_2 = 0x80000A4E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP2_P0_3 = 0x80000E4E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_22_RP2_P0_3 = 0x80000E4E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_22_RP2_P0_3 = 0x80000E4E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP2_P0_4 = 0x8000124E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_22_RP2_P0_4 = 0x8000124E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_22_RP2_P0_4 = 0x8000124E0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_22_RP2_P1_0 = 0x8000024E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_22_RP2_P1_0 = 0x8000024E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_22_RP2_P1_1 = 0x8000064E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_22_RP2_P1_1 = 0x8000064E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_22_RP2_P1_2 = 0x80000A4E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_22_RP2_P1_2 = 0x80000A4E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_22_RP2_P1_3 = 0x80000E4E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_22_RP2_P1_3 = 0x80000E4E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_22_RP2_P1_4 = 0x8000124E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_22_RP2_P1_4 = 0x8000124E0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_22_RP2_P2_0 = 0x8000024E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_22_RP2_P2_0 = 0x8000024E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_22_RP2_P2_1 = 0x8000064E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_22_RP2_P2_1 = 0x8000064E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_22_RP2_P2_2 = 0x80000A4E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_22_RP2_P2_2 = 0x80000A4E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_22_RP2_P2_3 = 0x80000E4E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_22_RP2_P2_3 = 0x80000E4E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_22_RP2_P2_4 = 0x8000124E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_22_RP2_P2_4 = 0x8000124E0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_22_RP2_P3_0 = 0x8000024E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_22_RP2_P3_0 = 0x8000024E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_22_RP2_P3_1 = 0x8000064E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_22_RP2_P3_1 = 0x8000064E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_22_RP2_P3_2 = 0x80000A4E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_22_RP2_P3_2 = 0x80000A4E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_22_RP2_P3_3 = 0x80000E4E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_22_RP2_P3_3 = 0x80000E4E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_22_RP2_P3_4 = 0x8000124E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_22_RP2_P3_4 = 0x8000124E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP3_P0_0 = 0x8000034E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_22_RP3_P0_0 = 0x8000034E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_22_RP3_P0_0 = 0x8000034E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP3_P0_1 = 0x8000074E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_22_RP3_P0_1 = 0x8000074E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_22_RP3_P0_1 = 0x8000074E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP3_P0_2 = 0x80000B4E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_22_RP3_P0_2 = 0x80000B4E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_22_RP3_P0_2 = 0x80000B4E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP3_P0_3 = 0x80000F4E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_22_RP3_P0_3 = 0x80000F4E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_22_RP3_P0_3 = 0x80000F4E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP3_P0_4 = 0x8000134E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_22_RP3_P0_4 = 0x8000134E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_22_RP3_P0_4 = 0x8000134E0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_22_RP3_P1_0 = 0x8000034E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_22_RP3_P1_0 = 0x8000034E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_22_RP3_P1_1 = 0x8000074E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_22_RP3_P1_1 = 0x8000074E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_22_RP3_P1_2 = 0x80000B4E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_22_RP3_P1_2 = 0x80000B4E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_22_RP3_P1_3 = 0x80000F4E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_22_RP3_P1_3 = 0x80000F4E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_22_RP3_P1_4 = 0x8000134E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_22_RP3_P1_4 = 0x8000134E0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_22_RP3_P2_0 = 0x8000034E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_22_RP3_P2_0 = 0x8000034E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_22_RP3_P2_1 = 0x8000074E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_22_RP3_P2_1 = 0x8000074E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_22_RP3_P2_2 = 0x80000B4E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_22_RP3_P2_2 = 0x80000B4E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_22_RP3_P2_3 = 0x80000F4E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_22_RP3_P2_3 = 0x80000F4E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_22_RP3_P2_4 = 0x8000134E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_22_RP3_P2_4 = 0x8000134E0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_22_RP3_P3_0 = 0x8000034E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_22_RP3_P3_0 = 0x8000034E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_22_RP3_P3_1 = 0x8000074E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_22_RP3_P3_1 = 0x8000074E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_22_RP3_P3_2 = 0x80000B4E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_22_RP3_P3_2 = 0x80000B4E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_22_RP3_P3_3 = 0x80000F4E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_22_RP3_P3_3 = 0x80000F4E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_22_RP3_P3_4 = 0x8000134E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_22_RP3_P3_4 = 0x8000134E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP0_P0_0 = 0x8000003A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_2_RP0_P0_0 = 0x8000003A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_2_RP0_P0_0 = 0x8000003A0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP0_P0_1 = 0x8000043A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_2_RP0_P0_1 = 0x8000043A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_2_RP0_P0_1 = 0x8000043A0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP0_P0_2 = 0x8000083A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_2_RP0_P0_2 = 0x8000083A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_2_RP0_P0_2 = 0x8000083A0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP0_P0_3 = 0x80000C3A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_2_RP0_P0_3 = 0x80000C3A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_2_RP0_P0_3 = 0x80000C3A0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP0_P0_4 = 0x8000103A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_2_RP0_P0_4 = 0x8000103A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_2_RP0_P0_4 = 0x8000103A0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_2_RP0_P1_0 = 0x8000003A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_2_RP0_P1_0 = 0x8000003A0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_2_RP0_P1_1 = 0x8000043A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_2_RP0_P1_1 = 0x8000043A0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_2_RP0_P1_2 = 0x8000083A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_2_RP0_P1_2 = 0x8000083A0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_2_RP0_P1_3 = 0x80000C3A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_2_RP0_P1_3 = 0x80000C3A0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_2_RP0_P1_4 = 0x8000103A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_2_RP0_P1_4 = 0x8000103A0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_2_RP0_P2_0 = 0x8000003A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_2_RP0_P2_0 = 0x8000003A0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_2_RP0_P2_1 = 0x8000043A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_2_RP0_P2_1 = 0x8000043A0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_2_RP0_P2_2 = 0x8000083A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_2_RP0_P2_2 = 0x8000083A0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_2_RP0_P2_3 = 0x80000C3A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_2_RP0_P2_3 = 0x80000C3A0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_2_RP0_P2_4 = 0x8000103A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_2_RP0_P2_4 = 0x8000103A0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_2_RP0_P3_0 = 0x8000003A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_2_RP0_P3_0 = 0x8000003A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_2_RP0_P3_1 = 0x8000043A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_2_RP0_P3_1 = 0x8000043A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_2_RP0_P3_2 = 0x8000083A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_2_RP0_P3_2 = 0x8000083A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_2_RP0_P3_3 = 0x80000C3A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_2_RP0_P3_3 = 0x80000C3A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_2_RP0_P3_4 = 0x8000103A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_2_RP0_P3_4 = 0x8000103A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP1_P0_0 = 0x8000013A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_2_RP1_P0_0 = 0x8000013A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_2_RP1_P0_0 = 0x8000013A0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP1_P0_1 = 0x8000053A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_2_RP1_P0_1 = 0x8000053A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_2_RP1_P0_1 = 0x8000053A0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP1_P0_2 = 0x8000093A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_2_RP1_P0_2 = 0x8000093A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_2_RP1_P0_2 = 0x8000093A0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP1_P0_3 = 0x80000D3A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_2_RP1_P0_3 = 0x80000D3A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_2_RP1_P0_3 = 0x80000D3A0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP1_P0_4 = 0x8000113A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_2_RP1_P0_4 = 0x8000113A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_2_RP1_P0_4 = 0x8000113A0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_2_RP1_P1_0 = 0x8000013A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_2_RP1_P1_0 = 0x8000013A0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_2_RP1_P1_1 = 0x8000053A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_2_RP1_P1_1 = 0x8000053A0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_2_RP1_P1_2 = 0x8000093A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_2_RP1_P1_2 = 0x8000093A0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_2_RP1_P1_3 = 0x80000D3A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_2_RP1_P1_3 = 0x80000D3A0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_2_RP1_P1_4 = 0x8000113A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_2_RP1_P1_4 = 0x8000113A0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_2_RP1_P2_0 = 0x8000013A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_2_RP1_P2_0 = 0x8000013A0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_2_RP1_P2_1 = 0x8000053A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_2_RP1_P2_1 = 0x8000053A0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_2_RP1_P2_2 = 0x8000093A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_2_RP1_P2_2 = 0x8000093A0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_2_RP1_P2_3 = 0x80000D3A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_2_RP1_P2_3 = 0x80000D3A0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_2_RP1_P2_4 = 0x8000113A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_2_RP1_P2_4 = 0x8000113A0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_2_RP1_P3_0 = 0x8000013A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_2_RP1_P3_0 = 0x8000013A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_2_RP1_P3_1 = 0x8000053A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_2_RP1_P3_1 = 0x8000053A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_2_RP1_P3_2 = 0x8000093A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_2_RP1_P3_2 = 0x8000093A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_2_RP1_P3_3 = 0x80000D3A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_2_RP1_P3_3 = 0x80000D3A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_2_RP1_P3_4 = 0x8000113A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_2_RP1_P3_4 = 0x8000113A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP2_P0_0 = 0x8000023A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_2_RP2_P0_0 = 0x8000023A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_2_RP2_P0_0 = 0x8000023A0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP2_P0_1 = 0x8000063A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_2_RP2_P0_1 = 0x8000063A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_2_RP2_P0_1 = 0x8000063A0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP2_P0_2 = 0x80000A3A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_2_RP2_P0_2 = 0x80000A3A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_2_RP2_P0_2 = 0x80000A3A0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP2_P0_3 = 0x80000E3A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_2_RP2_P0_3 = 0x80000E3A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_2_RP2_P0_3 = 0x80000E3A0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP2_P0_4 = 0x8000123A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_2_RP2_P0_4 = 0x8000123A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_2_RP2_P0_4 = 0x8000123A0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_2_RP2_P1_0 = 0x8000023A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_2_RP2_P1_0 = 0x8000023A0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_2_RP2_P1_1 = 0x8000063A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_2_RP2_P1_1 = 0x8000063A0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_2_RP2_P1_2 = 0x80000A3A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_2_RP2_P1_2 = 0x80000A3A0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_2_RP2_P1_3 = 0x80000E3A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_2_RP2_P1_3 = 0x80000E3A0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_2_RP2_P1_4 = 0x8000123A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_2_RP2_P1_4 = 0x8000123A0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_2_RP2_P2_0 = 0x8000023A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_2_RP2_P2_0 = 0x8000023A0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_2_RP2_P2_1 = 0x8000063A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_2_RP2_P2_1 = 0x8000063A0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_2_RP2_P2_2 = 0x80000A3A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_2_RP2_P2_2 = 0x80000A3A0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_2_RP2_P2_3 = 0x80000E3A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_2_RP2_P2_3 = 0x80000E3A0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_2_RP2_P2_4 = 0x8000123A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_2_RP2_P2_4 = 0x8000123A0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_2_RP2_P3_0 = 0x8000023A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_2_RP2_P3_0 = 0x8000023A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_2_RP2_P3_1 = 0x8000063A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_2_RP2_P3_1 = 0x8000063A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_2_RP2_P3_2 = 0x80000A3A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_2_RP2_P3_2 = 0x80000A3A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_2_RP2_P3_3 = 0x80000E3A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_2_RP2_P3_3 = 0x80000E3A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_2_RP2_P3_4 = 0x8000123A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_2_RP2_P3_4 = 0x8000123A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP3_P0_0 = 0x8000033A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_2_RP3_P0_0 = 0x8000033A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_2_RP3_P0_0 = 0x8000033A0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP3_P0_1 = 0x8000073A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_2_RP3_P0_1 = 0x8000073A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_2_RP3_P0_1 = 0x8000073A0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP3_P0_2 = 0x80000B3A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_2_RP3_P0_2 = 0x80000B3A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_2_RP3_P0_2 = 0x80000B3A0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP3_P0_3 = 0x80000F3A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_2_RP3_P0_3 = 0x80000F3A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_2_RP3_P0_3 = 0x80000F3A0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP3_P0_4 = 0x8000133A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_2_RP3_P0_4 = 0x8000133A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_2_RP3_P0_4 = 0x8000133A0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_2_RP3_P1_0 = 0x8000033A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_2_RP3_P1_0 = 0x8000033A0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_2_RP3_P1_1 = 0x8000073A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_2_RP3_P1_1 = 0x8000073A0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_2_RP3_P1_2 = 0x80000B3A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_2_RP3_P1_2 = 0x80000B3A0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_2_RP3_P1_3 = 0x80000F3A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_2_RP3_P1_3 = 0x80000F3A0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_2_RP3_P1_4 = 0x8000133A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_2_RP3_P1_4 = 0x8000133A0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_2_RP3_P2_0 = 0x8000033A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_2_RP3_P2_0 = 0x8000033A0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_2_RP3_P2_1 = 0x8000073A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_2_RP3_P2_1 = 0x8000073A0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_2_RP3_P2_2 = 0x80000B3A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_2_RP3_P2_2 = 0x80000B3A0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_2_RP3_P2_3 = 0x80000F3A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_2_RP3_P2_3 = 0x80000F3A0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_2_RP3_P2_4 = 0x8000133A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_2_RP3_P2_4 = 0x8000133A0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_2_RP3_P3_0 = 0x8000033A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_2_RP3_P3_0 = 0x8000033A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_2_RP3_P3_1 = 0x8000073A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_2_RP3_P3_1 = 0x8000073A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_2_RP3_P3_2 = 0x80000B3A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_2_RP3_P3_2 = 0x80000B3A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_2_RP3_P3_3 = 0x80000F3A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_2_RP3_P3_3 = 0x80000F3A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_2_RP3_P3_4 = 0x8000133A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_2_RP3_P3_4 = 0x8000133A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP0_P0_0 = 0x8000003B0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_3_RP0_P0_0 = 0x8000003B0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_3_RP0_P0_0 = 0x8000003B0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP0_P0_1 = 0x8000043B0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_3_RP0_P0_1 = 0x8000043B0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_3_RP0_P0_1 = 0x8000043B0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP0_P0_2 = 0x8000083B0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_3_RP0_P0_2 = 0x8000083B0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_3_RP0_P0_2 = 0x8000083B0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP0_P0_3 = 0x80000C3B0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_3_RP0_P0_3 = 0x80000C3B0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_3_RP0_P0_3 = 0x80000C3B0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP0_P0_4 = 0x8000103B0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_3_RP0_P0_4 = 0x8000103B0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_3_RP0_P0_4 = 0x8000103B0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_3_RP0_P1_0 = 0x8000003B0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_3_RP0_P1_0 = 0x8000003B0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_3_RP0_P1_1 = 0x8000043B0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_3_RP0_P1_1 = 0x8000043B0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_3_RP0_P1_2 = 0x8000083B0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_3_RP0_P1_2 = 0x8000083B0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_3_RP0_P1_3 = 0x80000C3B0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_3_RP0_P1_3 = 0x80000C3B0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_3_RP0_P1_4 = 0x8000103B0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_3_RP0_P1_4 = 0x8000103B0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_3_RP0_P2_0 = 0x8000003B0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_3_RP0_P2_0 = 0x8000003B0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_3_RP0_P2_1 = 0x8000043B0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_3_RP0_P2_1 = 0x8000043B0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_3_RP0_P2_2 = 0x8000083B0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_3_RP0_P2_2 = 0x8000083B0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_3_RP0_P2_3 = 0x80000C3B0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_3_RP0_P2_3 = 0x80000C3B0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_3_RP0_P2_4 = 0x8000103B0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_3_RP0_P2_4 = 0x8000103B0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_3_RP0_P3_0 = 0x8000003B07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_3_RP0_P3_0 = 0x8000003B08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_3_RP0_P3_1 = 0x8000043B07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_3_RP0_P3_1 = 0x8000043B08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_3_RP0_P3_2 = 0x8000083B07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_3_RP0_P3_2 = 0x8000083B08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_3_RP0_P3_3 = 0x80000C3B07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_3_RP0_P3_3 = 0x80000C3B08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_3_RP0_P3_4 = 0x8000103B07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_3_RP0_P3_4 = 0x8000103B08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP1_P0_0 = 0x8000013B0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_3_RP1_P0_0 = 0x8000013B0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_3_RP1_P0_0 = 0x8000013B0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP1_P0_1 = 0x8000053B0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_3_RP1_P0_1 = 0x8000053B0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_3_RP1_P0_1 = 0x8000053B0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP1_P0_2 = 0x8000093B0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_3_RP1_P0_2 = 0x8000093B0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_3_RP1_P0_2 = 0x8000093B0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP1_P0_3 = 0x80000D3B0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_3_RP1_P0_3 = 0x80000D3B0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_3_RP1_P0_3 = 0x80000D3B0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP1_P0_4 = 0x8000113B0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_3_RP1_P0_4 = 0x8000113B0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_3_RP1_P0_4 = 0x8000113B0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_3_RP1_P1_0 = 0x8000013B0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_3_RP1_P1_0 = 0x8000013B0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_3_RP1_P1_1 = 0x8000053B0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_3_RP1_P1_1 = 0x8000053B0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_3_RP1_P1_2 = 0x8000093B0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_3_RP1_P1_2 = 0x8000093B0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_3_RP1_P1_3 = 0x80000D3B0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_3_RP1_P1_3 = 0x80000D3B0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_3_RP1_P1_4 = 0x8000113B0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_3_RP1_P1_4 = 0x8000113B0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_3_RP1_P2_0 = 0x8000013B0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_3_RP1_P2_0 = 0x8000013B0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_3_RP1_P2_1 = 0x8000053B0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_3_RP1_P2_1 = 0x8000053B0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_3_RP1_P2_2 = 0x8000093B0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_3_RP1_P2_2 = 0x8000093B0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_3_RP1_P2_3 = 0x80000D3B0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_3_RP1_P2_3 = 0x80000D3B0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_3_RP1_P2_4 = 0x8000113B0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_3_RP1_P2_4 = 0x8000113B0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_3_RP1_P3_0 = 0x8000013B07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_3_RP1_P3_0 = 0x8000013B08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_3_RP1_P3_1 = 0x8000053B07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_3_RP1_P3_1 = 0x8000053B08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_3_RP1_P3_2 = 0x8000093B07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_3_RP1_P3_2 = 0x8000093B08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_3_RP1_P3_3 = 0x80000D3B07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_3_RP1_P3_3 = 0x80000D3B08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_3_RP1_P3_4 = 0x8000113B07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_3_RP1_P3_4 = 0x8000113B08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP2_P0_0 = 0x8000023B0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_3_RP2_P0_0 = 0x8000023B0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_3_RP2_P0_0 = 0x8000023B0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP2_P0_1 = 0x8000063B0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_3_RP2_P0_1 = 0x8000063B0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_3_RP2_P0_1 = 0x8000063B0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP2_P0_2 = 0x80000A3B0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_3_RP2_P0_2 = 0x80000A3B0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_3_RP2_P0_2 = 0x80000A3B0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP2_P0_3 = 0x80000E3B0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_3_RP2_P0_3 = 0x80000E3B0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_3_RP2_P0_3 = 0x80000E3B0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP2_P0_4 = 0x8000123B0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_3_RP2_P0_4 = 0x8000123B0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_3_RP2_P0_4 = 0x8000123B0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_3_RP2_P1_0 = 0x8000023B0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_3_RP2_P1_0 = 0x8000023B0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_3_RP2_P1_1 = 0x8000063B0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_3_RP2_P1_1 = 0x8000063B0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_3_RP2_P1_2 = 0x80000A3B0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_3_RP2_P1_2 = 0x80000A3B0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_3_RP2_P1_3 = 0x80000E3B0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_3_RP2_P1_3 = 0x80000E3B0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_3_RP2_P1_4 = 0x8000123B0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_3_RP2_P1_4 = 0x8000123B0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_3_RP2_P2_0 = 0x8000023B0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_3_RP2_P2_0 = 0x8000023B0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_3_RP2_P2_1 = 0x8000063B0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_3_RP2_P2_1 = 0x8000063B0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_3_RP2_P2_2 = 0x80000A3B0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_3_RP2_P2_2 = 0x80000A3B0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_3_RP2_P2_3 = 0x80000E3B0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_3_RP2_P2_3 = 0x80000E3B0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_3_RP2_P2_4 = 0x8000123B0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_3_RP2_P2_4 = 0x8000123B0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_3_RP2_P3_0 = 0x8000023B07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_3_RP2_P3_0 = 0x8000023B08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_3_RP2_P3_1 = 0x8000063B07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_3_RP2_P3_1 = 0x8000063B08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_3_RP2_P3_2 = 0x80000A3B07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_3_RP2_P3_2 = 0x80000A3B08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_3_RP2_P3_3 = 0x80000E3B07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_3_RP2_P3_3 = 0x80000E3B08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_3_RP2_P3_4 = 0x8000123B07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_3_RP2_P3_4 = 0x8000123B08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP3_P0_0 = 0x8000033B0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_3_RP3_P0_0 = 0x8000033B0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_3_RP3_P0_0 = 0x8000033B0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP3_P0_1 = 0x8000073B0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_3_RP3_P0_1 = 0x8000073B0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_3_RP3_P0_1 = 0x8000073B0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP3_P0_2 = 0x80000B3B0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_3_RP3_P0_2 = 0x80000B3B0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_3_RP3_P0_2 = 0x80000B3B0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP3_P0_3 = 0x80000F3B0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_3_RP3_P0_3 = 0x80000F3B0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_3_RP3_P0_3 = 0x80000F3B0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP3_P0_4 = 0x8000133B0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_3_RP3_P0_4 = 0x8000133B0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_3_RP3_P0_4 = 0x8000133B0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_3_RP3_P1_0 = 0x8000033B0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_3_RP3_P1_0 = 0x8000033B0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_3_RP3_P1_1 = 0x8000073B0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_3_RP3_P1_1 = 0x8000073B0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_3_RP3_P1_2 = 0x80000B3B0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_3_RP3_P1_2 = 0x80000B3B0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_3_RP3_P1_3 = 0x80000F3B0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_3_RP3_P1_3 = 0x80000F3B0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_3_RP3_P1_4 = 0x8000133B0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_3_RP3_P1_4 = 0x8000133B0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_3_RP3_P2_0 = 0x8000033B0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_3_RP3_P2_0 = 0x8000033B0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_3_RP3_P2_1 = 0x8000073B0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_3_RP3_P2_1 = 0x8000073B0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_3_RP3_P2_2 = 0x80000B3B0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_3_RP3_P2_2 = 0x80000B3B0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_3_RP3_P2_3 = 0x80000F3B0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_3_RP3_P2_3 = 0x80000F3B0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_3_RP3_P2_4 = 0x8000133B0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_3_RP3_P2_4 = 0x8000133B0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_3_RP3_P3_0 = 0x8000033B07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_3_RP3_P3_0 = 0x8000033B08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_3_RP3_P3_1 = 0x8000073B07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_3_RP3_P3_1 = 0x8000073B08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_3_RP3_P3_2 = 0x80000B3B07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_3_RP3_P3_2 = 0x80000B3B08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_3_RP3_P3_3 = 0x80000F3B07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_3_RP3_P3_3 = 0x80000F3B08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_3_RP3_P3_4 = 0x8000133B07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_3_RP3_P3_4 = 0x8000133B08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP0_P0_0 = 0x8000003C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_4_RP0_P0_0 = 0x8000003C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_4_RP0_P0_0 = 0x8000003C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP0_P0_1 = 0x8000043C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_4_RP0_P0_1 = 0x8000043C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_4_RP0_P0_1 = 0x8000043C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP0_P0_2 = 0x8000083C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_4_RP0_P0_2 = 0x8000083C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_4_RP0_P0_2 = 0x8000083C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP0_P0_3 = 0x80000C3C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_4_RP0_P0_3 = 0x80000C3C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_4_RP0_P0_3 = 0x80000C3C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP0_P0_4 = 0x8000103C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_4_RP0_P0_4 = 0x8000103C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_4_RP0_P0_4 = 0x8000103C0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_4_RP0_P1_0 = 0x8000003C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_4_RP0_P1_0 = 0x8000003C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_4_RP0_P1_1 = 0x8000043C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_4_RP0_P1_1 = 0x8000043C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_4_RP0_P1_2 = 0x8000083C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_4_RP0_P1_2 = 0x8000083C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_4_RP0_P1_3 = 0x80000C3C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_4_RP0_P1_3 = 0x80000C3C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_4_RP0_P1_4 = 0x8000103C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_4_RP0_P1_4 = 0x8000103C0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_4_RP0_P2_0 = 0x8000003C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_4_RP0_P2_0 = 0x8000003C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_4_RP0_P2_1 = 0x8000043C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_4_RP0_P2_1 = 0x8000043C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_4_RP0_P2_2 = 0x8000083C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_4_RP0_P2_2 = 0x8000083C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_4_RP0_P2_3 = 0x80000C3C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_4_RP0_P2_3 = 0x80000C3C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_4_RP0_P2_4 = 0x8000103C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_4_RP0_P2_4 = 0x8000103C0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_4_RP0_P3_0 = 0x8000003C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_4_RP0_P3_0 = 0x8000003C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_4_RP0_P3_1 = 0x8000043C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_4_RP0_P3_1 = 0x8000043C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_4_RP0_P3_2 = 0x8000083C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_4_RP0_P3_2 = 0x8000083C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_4_RP0_P3_3 = 0x80000C3C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_4_RP0_P3_3 = 0x80000C3C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_4_RP0_P3_4 = 0x8000103C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_4_RP0_P3_4 = 0x8000103C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP1_P0_0 = 0x8000013C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_4_RP1_P0_0 = 0x8000013C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_4_RP1_P0_0 = 0x8000013C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP1_P0_1 = 0x8000053C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_4_RP1_P0_1 = 0x8000053C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_4_RP1_P0_1 = 0x8000053C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP1_P0_2 = 0x8000093C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_4_RP1_P0_2 = 0x8000093C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_4_RP1_P0_2 = 0x8000093C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP1_P0_3 = 0x80000D3C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_4_RP1_P0_3 = 0x80000D3C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_4_RP1_P0_3 = 0x80000D3C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP1_P0_4 = 0x8000113C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_4_RP1_P0_4 = 0x8000113C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_4_RP1_P0_4 = 0x8000113C0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_4_RP1_P1_0 = 0x8000013C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_4_RP1_P1_0 = 0x8000013C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_4_RP1_P1_1 = 0x8000053C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_4_RP1_P1_1 = 0x8000053C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_4_RP1_P1_2 = 0x8000093C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_4_RP1_P1_2 = 0x8000093C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_4_RP1_P1_3 = 0x80000D3C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_4_RP1_P1_3 = 0x80000D3C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_4_RP1_P1_4 = 0x8000113C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_4_RP1_P1_4 = 0x8000113C0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_4_RP1_P2_0 = 0x8000013C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_4_RP1_P2_0 = 0x8000013C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_4_RP1_P2_1 = 0x8000053C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_4_RP1_P2_1 = 0x8000053C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_4_RP1_P2_2 = 0x8000093C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_4_RP1_P2_2 = 0x8000093C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_4_RP1_P2_3 = 0x80000D3C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_4_RP1_P2_3 = 0x80000D3C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_4_RP1_P2_4 = 0x8000113C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_4_RP1_P2_4 = 0x8000113C0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_4_RP1_P3_0 = 0x8000013C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_4_RP1_P3_0 = 0x8000013C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_4_RP1_P3_1 = 0x8000053C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_4_RP1_P3_1 = 0x8000053C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_4_RP1_P3_2 = 0x8000093C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_4_RP1_P3_2 = 0x8000093C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_4_RP1_P3_3 = 0x80000D3C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_4_RP1_P3_3 = 0x80000D3C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_4_RP1_P3_4 = 0x8000113C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_4_RP1_P3_4 = 0x8000113C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP2_P0_0 = 0x8000023C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_4_RP2_P0_0 = 0x8000023C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_4_RP2_P0_0 = 0x8000023C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP2_P0_1 = 0x8000063C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_4_RP2_P0_1 = 0x8000063C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_4_RP2_P0_1 = 0x8000063C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP2_P0_2 = 0x80000A3C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_4_RP2_P0_2 = 0x80000A3C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_4_RP2_P0_2 = 0x80000A3C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP2_P0_3 = 0x80000E3C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_4_RP2_P0_3 = 0x80000E3C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_4_RP2_P0_3 = 0x80000E3C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP2_P0_4 = 0x8000123C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_4_RP2_P0_4 = 0x8000123C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_4_RP2_P0_4 = 0x8000123C0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_4_RP2_P1_0 = 0x8000023C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_4_RP2_P1_0 = 0x8000023C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_4_RP2_P1_1 = 0x8000063C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_4_RP2_P1_1 = 0x8000063C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_4_RP2_P1_2 = 0x80000A3C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_4_RP2_P1_2 = 0x80000A3C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_4_RP2_P1_3 = 0x80000E3C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_4_RP2_P1_3 = 0x80000E3C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_4_RP2_P1_4 = 0x8000123C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_4_RP2_P1_4 = 0x8000123C0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_4_RP2_P2_0 = 0x8000023C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_4_RP2_P2_0 = 0x8000023C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_4_RP2_P2_1 = 0x8000063C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_4_RP2_P2_1 = 0x8000063C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_4_RP2_P2_2 = 0x80000A3C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_4_RP2_P2_2 = 0x80000A3C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_4_RP2_P2_3 = 0x80000E3C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_4_RP2_P2_3 = 0x80000E3C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_4_RP2_P2_4 = 0x8000123C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_4_RP2_P2_4 = 0x8000123C0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_4_RP2_P3_0 = 0x8000023C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_4_RP2_P3_0 = 0x8000023C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_4_RP2_P3_1 = 0x8000063C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_4_RP2_P3_1 = 0x8000063C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_4_RP2_P3_2 = 0x80000A3C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_4_RP2_P3_2 = 0x80000A3C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_4_RP2_P3_3 = 0x80000E3C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_4_RP2_P3_3 = 0x80000E3C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_4_RP2_P3_4 = 0x8000123C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_4_RP2_P3_4 = 0x8000123C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP3_P0_0 = 0x8000033C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_4_RP3_P0_0 = 0x8000033C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_4_RP3_P0_0 = 0x8000033C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP3_P0_1 = 0x8000073C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_4_RP3_P0_1 = 0x8000073C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_4_RP3_P0_1 = 0x8000073C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP3_P0_2 = 0x80000B3C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_4_RP3_P0_2 = 0x80000B3C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_4_RP3_P0_2 = 0x80000B3C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP3_P0_3 = 0x80000F3C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_4_RP3_P0_3 = 0x80000F3C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_4_RP3_P0_3 = 0x80000F3C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP3_P0_4 = 0x8000133C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_4_RP3_P0_4 = 0x8000133C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_4_RP3_P0_4 = 0x8000133C0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_4_RP3_P1_0 = 0x8000033C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_4_RP3_P1_0 = 0x8000033C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_4_RP3_P1_1 = 0x8000073C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_4_RP3_P1_1 = 0x8000073C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_4_RP3_P1_2 = 0x80000B3C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_4_RP3_P1_2 = 0x80000B3C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_4_RP3_P1_3 = 0x80000F3C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_4_RP3_P1_3 = 0x80000F3C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_4_RP3_P1_4 = 0x8000133C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_4_RP3_P1_4 = 0x8000133C0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_4_RP3_P2_0 = 0x8000033C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_4_RP3_P2_0 = 0x8000033C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_4_RP3_P2_1 = 0x8000073C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_4_RP3_P2_1 = 0x8000073C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_4_RP3_P2_2 = 0x80000B3C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_4_RP3_P2_2 = 0x80000B3C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_4_RP3_P2_3 = 0x80000F3C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_4_RP3_P2_3 = 0x80000F3C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_4_RP3_P2_4 = 0x8000133C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_4_RP3_P2_4 = 0x8000133C0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_4_RP3_P3_0 = 0x8000033C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_4_RP3_P3_0 = 0x8000033C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_4_RP3_P3_1 = 0x8000073C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_4_RP3_P3_1 = 0x8000073C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_4_RP3_P3_2 = 0x80000B3C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_4_RP3_P3_2 = 0x80000B3C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_4_RP3_P3_3 = 0x80000F3C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_4_RP3_P3_3 = 0x80000F3C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_4_RP3_P3_4 = 0x8000133C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_4_RP3_P3_4 = 0x8000133C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP0_P0_0 = 0x8000003D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_5_RP0_P0_0 = 0x8000003D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_5_RP0_P0_0 = 0x8000003D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP0_P0_1 = 0x8000043D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_5_RP0_P0_1 = 0x8000043D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_5_RP0_P0_1 = 0x8000043D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP0_P0_2 = 0x8000083D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_5_RP0_P0_2 = 0x8000083D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_5_RP0_P0_2 = 0x8000083D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP0_P0_3 = 0x80000C3D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_5_RP0_P0_3 = 0x80000C3D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_5_RP0_P0_3 = 0x80000C3D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP0_P0_4 = 0x8000103D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_5_RP0_P0_4 = 0x8000103D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_5_RP0_P0_4 = 0x8000103D0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_5_RP0_P1_0 = 0x8000003D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_5_RP0_P1_0 = 0x8000003D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_5_RP0_P1_1 = 0x8000043D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_5_RP0_P1_1 = 0x8000043D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_5_RP0_P1_2 = 0x8000083D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_5_RP0_P1_2 = 0x8000083D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_5_RP0_P1_3 = 0x80000C3D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_5_RP0_P1_3 = 0x80000C3D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_5_RP0_P1_4 = 0x8000103D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_5_RP0_P1_4 = 0x8000103D0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_5_RP0_P2_0 = 0x8000003D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_5_RP0_P2_0 = 0x8000003D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_5_RP0_P2_1 = 0x8000043D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_5_RP0_P2_1 = 0x8000043D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_5_RP0_P2_2 = 0x8000083D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_5_RP0_P2_2 = 0x8000083D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_5_RP0_P2_3 = 0x80000C3D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_5_RP0_P2_3 = 0x80000C3D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_5_RP0_P2_4 = 0x8000103D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_5_RP0_P2_4 = 0x8000103D0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_5_RP0_P3_0 = 0x8000003D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_5_RP0_P3_0 = 0x8000003D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_5_RP0_P3_1 = 0x8000043D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_5_RP0_P3_1 = 0x8000043D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_5_RP0_P3_2 = 0x8000083D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_5_RP0_P3_2 = 0x8000083D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_5_RP0_P3_3 = 0x80000C3D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_5_RP0_P3_3 = 0x80000C3D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_5_RP0_P3_4 = 0x8000103D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_5_RP0_P3_4 = 0x8000103D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP1_P0_0 = 0x8000013D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_5_RP1_P0_0 = 0x8000013D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_5_RP1_P0_0 = 0x8000013D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP1_P0_1 = 0x8000053D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_5_RP1_P0_1 = 0x8000053D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_5_RP1_P0_1 = 0x8000053D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP1_P0_2 = 0x8000093D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_5_RP1_P0_2 = 0x8000093D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_5_RP1_P0_2 = 0x8000093D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP1_P0_3 = 0x80000D3D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_5_RP1_P0_3 = 0x80000D3D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_5_RP1_P0_3 = 0x80000D3D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP1_P0_4 = 0x8000113D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_5_RP1_P0_4 = 0x8000113D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_5_RP1_P0_4 = 0x8000113D0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_5_RP1_P1_0 = 0x8000013D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_5_RP1_P1_0 = 0x8000013D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_5_RP1_P1_1 = 0x8000053D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_5_RP1_P1_1 = 0x8000053D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_5_RP1_P1_2 = 0x8000093D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_5_RP1_P1_2 = 0x8000093D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_5_RP1_P1_3 = 0x80000D3D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_5_RP1_P1_3 = 0x80000D3D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_5_RP1_P1_4 = 0x8000113D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_5_RP1_P1_4 = 0x8000113D0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_5_RP1_P2_0 = 0x8000013D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_5_RP1_P2_0 = 0x8000013D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_5_RP1_P2_1 = 0x8000053D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_5_RP1_P2_1 = 0x8000053D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_5_RP1_P2_2 = 0x8000093D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_5_RP1_P2_2 = 0x8000093D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_5_RP1_P2_3 = 0x80000D3D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_5_RP1_P2_3 = 0x80000D3D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_5_RP1_P2_4 = 0x8000113D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_5_RP1_P2_4 = 0x8000113D0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_5_RP1_P3_0 = 0x8000013D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_5_RP1_P3_0 = 0x8000013D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_5_RP1_P3_1 = 0x8000053D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_5_RP1_P3_1 = 0x8000053D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_5_RP1_P3_2 = 0x8000093D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_5_RP1_P3_2 = 0x8000093D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_5_RP1_P3_3 = 0x80000D3D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_5_RP1_P3_3 = 0x80000D3D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_5_RP1_P3_4 = 0x8000113D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_5_RP1_P3_4 = 0x8000113D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP2_P0_0 = 0x8000023D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_5_RP2_P0_0 = 0x8000023D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_5_RP2_P0_0 = 0x8000023D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP2_P0_1 = 0x8000063D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_5_RP2_P0_1 = 0x8000063D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_5_RP2_P0_1 = 0x8000063D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP2_P0_2 = 0x80000A3D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_5_RP2_P0_2 = 0x80000A3D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_5_RP2_P0_2 = 0x80000A3D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP2_P0_3 = 0x80000E3D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_5_RP2_P0_3 = 0x80000E3D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_5_RP2_P0_3 = 0x80000E3D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP2_P0_4 = 0x8000123D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_5_RP2_P0_4 = 0x8000123D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_5_RP2_P0_4 = 0x8000123D0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_5_RP2_P1_0 = 0x8000023D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_5_RP2_P1_0 = 0x8000023D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_5_RP2_P1_1 = 0x8000063D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_5_RP2_P1_1 = 0x8000063D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_5_RP2_P1_2 = 0x80000A3D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_5_RP2_P1_2 = 0x80000A3D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_5_RP2_P1_3 = 0x80000E3D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_5_RP2_P1_3 = 0x80000E3D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_5_RP2_P1_4 = 0x8000123D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_5_RP2_P1_4 = 0x8000123D0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_5_RP2_P2_0 = 0x8000023D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_5_RP2_P2_0 = 0x8000023D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_5_RP2_P2_1 = 0x8000063D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_5_RP2_P2_1 = 0x8000063D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_5_RP2_P2_2 = 0x80000A3D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_5_RP2_P2_2 = 0x80000A3D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_5_RP2_P2_3 = 0x80000E3D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_5_RP2_P2_3 = 0x80000E3D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_5_RP2_P2_4 = 0x8000123D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_5_RP2_P2_4 = 0x8000123D0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_5_RP2_P3_0 = 0x8000023D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_5_RP2_P3_0 = 0x8000023D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_5_RP2_P3_1 = 0x8000063D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_5_RP2_P3_1 = 0x8000063D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_5_RP2_P3_2 = 0x80000A3D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_5_RP2_P3_2 = 0x80000A3D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_5_RP2_P3_3 = 0x80000E3D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_5_RP2_P3_3 = 0x80000E3D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_5_RP2_P3_4 = 0x8000123D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_5_RP2_P3_4 = 0x8000123D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP3_P0_0 = 0x8000033D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_5_RP3_P0_0 = 0x8000033D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_5_RP3_P0_0 = 0x8000033D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP3_P0_1 = 0x8000073D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_5_RP3_P0_1 = 0x8000073D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_5_RP3_P0_1 = 0x8000073D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP3_P0_2 = 0x80000B3D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_5_RP3_P0_2 = 0x80000B3D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_5_RP3_P0_2 = 0x80000B3D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP3_P0_3 = 0x80000F3D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_5_RP3_P0_3 = 0x80000F3D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_5_RP3_P0_3 = 0x80000F3D0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP3_P0_4 = 0x8000133D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_5_RP3_P0_4 = 0x8000133D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_5_RP3_P0_4 = 0x8000133D0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_5_RP3_P1_0 = 0x8000033D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_5_RP3_P1_0 = 0x8000033D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_5_RP3_P1_1 = 0x8000073D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_5_RP3_P1_1 = 0x8000073D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_5_RP3_P1_2 = 0x80000B3D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_5_RP3_P1_2 = 0x80000B3D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_5_RP3_P1_3 = 0x80000F3D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_5_RP3_P1_3 = 0x80000F3D0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_5_RP3_P1_4 = 0x8000133D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_5_RP3_P1_4 = 0x8000133D0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_5_RP3_P2_0 = 0x8000033D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_5_RP3_P2_0 = 0x8000033D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_5_RP3_P2_1 = 0x8000073D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_5_RP3_P2_1 = 0x8000073D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_5_RP3_P2_2 = 0x80000B3D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_5_RP3_P2_2 = 0x80000B3D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_5_RP3_P2_3 = 0x80000F3D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_5_RP3_P2_3 = 0x80000F3D0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_5_RP3_P2_4 = 0x8000133D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_5_RP3_P2_4 = 0x8000133D0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_5_RP3_P3_0 = 0x8000033D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_5_RP3_P3_0 = 0x8000033D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_5_RP3_P3_1 = 0x8000073D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_5_RP3_P3_1 = 0x8000073D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_5_RP3_P3_2 = 0x80000B3D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_5_RP3_P3_2 = 0x80000B3D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_5_RP3_P3_3 = 0x80000F3D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_5_RP3_P3_3 = 0x80000F3D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_5_RP3_P3_4 = 0x8000133D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_5_RP3_P3_4 = 0x8000133D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP0_P0_0 = 0x8000003E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_6_RP0_P0_0 = 0x8000003E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_6_RP0_P0_0 = 0x8000003E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP0_P0_1 = 0x8000043E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_6_RP0_P0_1 = 0x8000043E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_6_RP0_P0_1 = 0x8000043E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP0_P0_2 = 0x8000083E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_6_RP0_P0_2 = 0x8000083E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_6_RP0_P0_2 = 0x8000083E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP0_P0_3 = 0x80000C3E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_6_RP0_P0_3 = 0x80000C3E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_6_RP0_P0_3 = 0x80000C3E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP0_P0_4 = 0x8000103E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_6_RP0_P0_4 = 0x8000103E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_6_RP0_P0_4 = 0x8000103E0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_6_RP0_P1_0 = 0x8000003E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_6_RP0_P1_0 = 0x8000003E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_6_RP0_P1_1 = 0x8000043E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_6_RP0_P1_1 = 0x8000043E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_6_RP0_P1_2 = 0x8000083E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_6_RP0_P1_2 = 0x8000083E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_6_RP0_P1_3 = 0x80000C3E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_6_RP0_P1_3 = 0x80000C3E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_6_RP0_P1_4 = 0x8000103E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_6_RP0_P1_4 = 0x8000103E0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_6_RP0_P2_0 = 0x8000003E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_6_RP0_P2_0 = 0x8000003E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_6_RP0_P2_1 = 0x8000043E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_6_RP0_P2_1 = 0x8000043E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_6_RP0_P2_2 = 0x8000083E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_6_RP0_P2_2 = 0x8000083E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_6_RP0_P2_3 = 0x80000C3E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_6_RP0_P2_3 = 0x80000C3E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_6_RP0_P2_4 = 0x8000103E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_6_RP0_P2_4 = 0x8000103E0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_6_RP0_P3_0 = 0x8000003E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_6_RP0_P3_0 = 0x8000003E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_6_RP0_P3_1 = 0x8000043E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_6_RP0_P3_1 = 0x8000043E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_6_RP0_P3_2 = 0x8000083E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_6_RP0_P3_2 = 0x8000083E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_6_RP0_P3_3 = 0x80000C3E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_6_RP0_P3_3 = 0x80000C3E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_6_RP0_P3_4 = 0x8000103E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_6_RP0_P3_4 = 0x8000103E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP1_P0_0 = 0x8000013E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_6_RP1_P0_0 = 0x8000013E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_6_RP1_P0_0 = 0x8000013E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP1_P0_1 = 0x8000053E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_6_RP1_P0_1 = 0x8000053E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_6_RP1_P0_1 = 0x8000053E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP1_P0_2 = 0x8000093E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_6_RP1_P0_2 = 0x8000093E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_6_RP1_P0_2 = 0x8000093E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP1_P0_3 = 0x80000D3E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_6_RP1_P0_3 = 0x80000D3E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_6_RP1_P0_3 = 0x80000D3E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP1_P0_4 = 0x8000113E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_6_RP1_P0_4 = 0x8000113E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_6_RP1_P0_4 = 0x8000113E0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_6_RP1_P1_0 = 0x8000013E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_6_RP1_P1_0 = 0x8000013E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_6_RP1_P1_1 = 0x8000053E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_6_RP1_P1_1 = 0x8000053E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_6_RP1_P1_2 = 0x8000093E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_6_RP1_P1_2 = 0x8000093E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_6_RP1_P1_3 = 0x80000D3E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_6_RP1_P1_3 = 0x80000D3E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_6_RP1_P1_4 = 0x8000113E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_6_RP1_P1_4 = 0x8000113E0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_6_RP1_P2_0 = 0x8000013E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_6_RP1_P2_0 = 0x8000013E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_6_RP1_P2_1 = 0x8000053E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_6_RP1_P2_1 = 0x8000053E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_6_RP1_P2_2 = 0x8000093E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_6_RP1_P2_2 = 0x8000093E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_6_RP1_P2_3 = 0x80000D3E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_6_RP1_P2_3 = 0x80000D3E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_6_RP1_P2_4 = 0x8000113E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_6_RP1_P2_4 = 0x8000113E0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_6_RP1_P3_0 = 0x8000013E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_6_RP1_P3_0 = 0x8000013E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_6_RP1_P3_1 = 0x8000053E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_6_RP1_P3_1 = 0x8000053E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_6_RP1_P3_2 = 0x8000093E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_6_RP1_P3_2 = 0x8000093E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_6_RP1_P3_3 = 0x80000D3E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_6_RP1_P3_3 = 0x80000D3E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_6_RP1_P3_4 = 0x8000113E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_6_RP1_P3_4 = 0x8000113E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP2_P0_0 = 0x8000023E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_6_RP2_P0_0 = 0x8000023E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_6_RP2_P0_0 = 0x8000023E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP2_P0_1 = 0x8000063E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_6_RP2_P0_1 = 0x8000063E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_6_RP2_P0_1 = 0x8000063E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP2_P0_2 = 0x80000A3E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_6_RP2_P0_2 = 0x80000A3E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_6_RP2_P0_2 = 0x80000A3E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP2_P0_3 = 0x80000E3E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_6_RP2_P0_3 = 0x80000E3E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_6_RP2_P0_3 = 0x80000E3E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP2_P0_4 = 0x8000123E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_6_RP2_P0_4 = 0x8000123E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_6_RP2_P0_4 = 0x8000123E0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_6_RP2_P1_0 = 0x8000023E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_6_RP2_P1_0 = 0x8000023E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_6_RP2_P1_1 = 0x8000063E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_6_RP2_P1_1 = 0x8000063E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_6_RP2_P1_2 = 0x80000A3E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_6_RP2_P1_2 = 0x80000A3E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_6_RP2_P1_3 = 0x80000E3E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_6_RP2_P1_3 = 0x80000E3E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_6_RP2_P1_4 = 0x8000123E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_6_RP2_P1_4 = 0x8000123E0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_6_RP2_P2_0 = 0x8000023E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_6_RP2_P2_0 = 0x8000023E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_6_RP2_P2_1 = 0x8000063E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_6_RP2_P2_1 = 0x8000063E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_6_RP2_P2_2 = 0x80000A3E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_6_RP2_P2_2 = 0x80000A3E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_6_RP2_P2_3 = 0x80000E3E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_6_RP2_P2_3 = 0x80000E3E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_6_RP2_P2_4 = 0x8000123E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_6_RP2_P2_4 = 0x8000123E0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_6_RP2_P3_0 = 0x8000023E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_6_RP2_P3_0 = 0x8000023E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_6_RP2_P3_1 = 0x8000063E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_6_RP2_P3_1 = 0x8000063E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_6_RP2_P3_2 = 0x80000A3E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_6_RP2_P3_2 = 0x80000A3E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_6_RP2_P3_3 = 0x80000E3E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_6_RP2_P3_3 = 0x80000E3E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_6_RP2_P3_4 = 0x8000123E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_6_RP2_P3_4 = 0x8000123E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP3_P0_0 = 0x8000033E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_6_RP3_P0_0 = 0x8000033E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_6_RP3_P0_0 = 0x8000033E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP3_P0_1 = 0x8000073E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_6_RP3_P0_1 = 0x8000073E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_6_RP3_P0_1 = 0x8000073E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP3_P0_2 = 0x80000B3E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_6_RP3_P0_2 = 0x80000B3E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_6_RP3_P0_2 = 0x80000B3E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP3_P0_3 = 0x80000F3E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_6_RP3_P0_3 = 0x80000F3E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_6_RP3_P0_3 = 0x80000F3E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP3_P0_4 = 0x8000133E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_6_RP3_P0_4 = 0x8000133E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_6_RP3_P0_4 = 0x8000133E0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_6_RP3_P1_0 = 0x8000033E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_6_RP3_P1_0 = 0x8000033E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_6_RP3_P1_1 = 0x8000073E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_6_RP3_P1_1 = 0x8000073E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_6_RP3_P1_2 = 0x80000B3E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_6_RP3_P1_2 = 0x80000B3E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_6_RP3_P1_3 = 0x80000F3E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_6_RP3_P1_3 = 0x80000F3E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_6_RP3_P1_4 = 0x8000133E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_6_RP3_P1_4 = 0x8000133E0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_6_RP3_P2_0 = 0x8000033E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_6_RP3_P2_0 = 0x8000033E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_6_RP3_P2_1 = 0x8000073E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_6_RP3_P2_1 = 0x8000073E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_6_RP3_P2_2 = 0x80000B3E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_6_RP3_P2_2 = 0x80000B3E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_6_RP3_P2_3 = 0x80000F3E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_6_RP3_P2_3 = 0x80000F3E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_6_RP3_P2_4 = 0x8000133E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_6_RP3_P2_4 = 0x8000133E0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_6_RP3_P3_0 = 0x8000033E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_6_RP3_P3_0 = 0x8000033E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_6_RP3_P3_1 = 0x8000073E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_6_RP3_P3_1 = 0x8000073E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_6_RP3_P3_2 = 0x80000B3E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_6_RP3_P3_2 = 0x80000B3E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_6_RP3_P3_3 = 0x80000F3E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_6_RP3_P3_3 = 0x80000F3E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_6_RP3_P3_4 = 0x8000133E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_6_RP3_P3_4 = 0x8000133E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP0_P0_0 = 0x8000003F0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_7_RP0_P0_0 = 0x8000003F0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_7_RP0_P0_0 = 0x8000003F0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP0_P0_1 = 0x8000043F0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_7_RP0_P0_1 = 0x8000043F0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_7_RP0_P0_1 = 0x8000043F0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP0_P0_2 = 0x8000083F0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_7_RP0_P0_2 = 0x8000083F0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_7_RP0_P0_2 = 0x8000083F0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP0_P0_3 = 0x80000C3F0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_7_RP0_P0_3 = 0x80000C3F0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_7_RP0_P0_3 = 0x80000C3F0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP0_P0_4 = 0x8000103F0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_7_RP0_P0_4 = 0x8000103F0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_7_RP0_P0_4 = 0x8000103F0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_7_RP0_P1_0 = 0x8000003F0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_7_RP0_P1_0 = 0x8000003F0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_7_RP0_P1_1 = 0x8000043F0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_7_RP0_P1_1 = 0x8000043F0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_7_RP0_P1_2 = 0x8000083F0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_7_RP0_P1_2 = 0x8000083F0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_7_RP0_P1_3 = 0x80000C3F0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_7_RP0_P1_3 = 0x80000C3F0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_7_RP0_P1_4 = 0x8000103F0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_7_RP0_P1_4 = 0x8000103F0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_7_RP0_P2_0 = 0x8000003F0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_7_RP0_P2_0 = 0x8000003F0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_7_RP0_P2_1 = 0x8000043F0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_7_RP0_P2_1 = 0x8000043F0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_7_RP0_P2_2 = 0x8000083F0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_7_RP0_P2_2 = 0x8000083F0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_7_RP0_P2_3 = 0x80000C3F0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_7_RP0_P2_3 = 0x80000C3F0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_7_RP0_P2_4 = 0x8000103F0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_7_RP0_P2_4 = 0x8000103F0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_7_RP0_P3_0 = 0x8000003F07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_7_RP0_P3_0 = 0x8000003F08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_7_RP0_P3_1 = 0x8000043F07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_7_RP0_P3_1 = 0x8000043F08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_7_RP0_P3_2 = 0x8000083F07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_7_RP0_P3_2 = 0x8000083F08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_7_RP0_P3_3 = 0x80000C3F07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_7_RP0_P3_3 = 0x80000C3F08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_7_RP0_P3_4 = 0x8000103F07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_7_RP0_P3_4 = 0x8000103F08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP1_P0_0 = 0x8000013F0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_7_RP1_P0_0 = 0x8000013F0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_7_RP1_P0_0 = 0x8000013F0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP1_P0_1 = 0x8000053F0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_7_RP1_P0_1 = 0x8000053F0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_7_RP1_P0_1 = 0x8000053F0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP1_P0_2 = 0x8000093F0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_7_RP1_P0_2 = 0x8000093F0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_7_RP1_P0_2 = 0x8000093F0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP1_P0_3 = 0x80000D3F0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_7_RP1_P0_3 = 0x80000D3F0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_7_RP1_P0_3 = 0x80000D3F0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP1_P0_4 = 0x8000113F0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_7_RP1_P0_4 = 0x8000113F0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_7_RP1_P0_4 = 0x8000113F0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_7_RP1_P1_0 = 0x8000013F0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_7_RP1_P1_0 = 0x8000013F0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_7_RP1_P1_1 = 0x8000053F0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_7_RP1_P1_1 = 0x8000053F0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_7_RP1_P1_2 = 0x8000093F0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_7_RP1_P1_2 = 0x8000093F0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_7_RP1_P1_3 = 0x80000D3F0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_7_RP1_P1_3 = 0x80000D3F0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_7_RP1_P1_4 = 0x8000113F0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_7_RP1_P1_4 = 0x8000113F0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_7_RP1_P2_0 = 0x8000013F0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_7_RP1_P2_0 = 0x8000013F0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_7_RP1_P2_1 = 0x8000053F0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_7_RP1_P2_1 = 0x8000053F0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_7_RP1_P2_2 = 0x8000093F0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_7_RP1_P2_2 = 0x8000093F0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_7_RP1_P2_3 = 0x80000D3F0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_7_RP1_P2_3 = 0x80000D3F0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_7_RP1_P2_4 = 0x8000113F0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_7_RP1_P2_4 = 0x8000113F0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_7_RP1_P3_0 = 0x8000013F07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_7_RP1_P3_0 = 0x8000013F08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_7_RP1_P3_1 = 0x8000053F07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_7_RP1_P3_1 = 0x8000053F08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_7_RP1_P3_2 = 0x8000093F07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_7_RP1_P3_2 = 0x8000093F08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_7_RP1_P3_3 = 0x80000D3F07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_7_RP1_P3_3 = 0x80000D3F08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_7_RP1_P3_4 = 0x8000113F07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_7_RP1_P3_4 = 0x8000113F08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP2_P0_0 = 0x8000023F0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_7_RP2_P0_0 = 0x8000023F0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_7_RP2_P0_0 = 0x8000023F0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP2_P0_1 = 0x8000063F0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_7_RP2_P0_1 = 0x8000063F0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_7_RP2_P0_1 = 0x8000063F0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP2_P0_2 = 0x80000A3F0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_7_RP2_P0_2 = 0x80000A3F0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_7_RP2_P0_2 = 0x80000A3F0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP2_P0_3 = 0x80000E3F0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_7_RP2_P0_3 = 0x80000E3F0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_7_RP2_P0_3 = 0x80000E3F0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP2_P0_4 = 0x8000123F0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_7_RP2_P0_4 = 0x8000123F0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_7_RP2_P0_4 = 0x8000123F0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_7_RP2_P1_0 = 0x8000023F0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_7_RP2_P1_0 = 0x8000023F0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_7_RP2_P1_1 = 0x8000063F0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_7_RP2_P1_1 = 0x8000063F0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_7_RP2_P1_2 = 0x80000A3F0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_7_RP2_P1_2 = 0x80000A3F0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_7_RP2_P1_3 = 0x80000E3F0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_7_RP2_P1_3 = 0x80000E3F0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_7_RP2_P1_4 = 0x8000123F0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_7_RP2_P1_4 = 0x8000123F0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_7_RP2_P2_0 = 0x8000023F0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_7_RP2_P2_0 = 0x8000023F0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_7_RP2_P2_1 = 0x8000063F0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_7_RP2_P2_1 = 0x8000063F0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_7_RP2_P2_2 = 0x80000A3F0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_7_RP2_P2_2 = 0x80000A3F0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_7_RP2_P2_3 = 0x80000E3F0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_7_RP2_P2_3 = 0x80000E3F0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_7_RP2_P2_4 = 0x8000123F0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_7_RP2_P2_4 = 0x8000123F0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_7_RP2_P3_0 = 0x8000023F07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_7_RP2_P3_0 = 0x8000023F08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_7_RP2_P3_1 = 0x8000063F07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_7_RP2_P3_1 = 0x8000063F08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_7_RP2_P3_2 = 0x80000A3F07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_7_RP2_P3_2 = 0x80000A3F08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_7_RP2_P3_3 = 0x80000E3F07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_7_RP2_P3_3 = 0x80000E3F08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_7_RP2_P3_4 = 0x8000123F07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_7_RP2_P3_4 = 0x8000123F08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP3_P0_0 = 0x8000033F0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_7_RP3_P0_0 = 0x8000033F0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_7_RP3_P0_0 = 0x8000033F0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP3_P0_1 = 0x8000073F0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_7_RP3_P0_1 = 0x8000073F0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_7_RP3_P0_1 = 0x8000073F0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP3_P0_2 = 0x80000B3F0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_7_RP3_P0_2 = 0x80000B3F0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_7_RP3_P0_2 = 0x80000B3F0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP3_P0_3 = 0x80000F3F0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_7_RP3_P0_3 = 0x80000F3F0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_7_RP3_P0_3 = 0x80000F3F0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP3_P0_4 = 0x8000133F0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_7_RP3_P0_4 = 0x8000133F0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_7_RP3_P0_4 = 0x8000133F0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_7_RP3_P1_0 = 0x8000033F0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_7_RP3_P1_0 = 0x8000033F0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_7_RP3_P1_1 = 0x8000073F0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_7_RP3_P1_1 = 0x8000073F0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_7_RP3_P1_2 = 0x80000B3F0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_7_RP3_P1_2 = 0x80000B3F0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_7_RP3_P1_3 = 0x80000F3F0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_7_RP3_P1_3 = 0x80000F3F0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_7_RP3_P1_4 = 0x8000133F0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_7_RP3_P1_4 = 0x8000133F0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_7_RP3_P2_0 = 0x8000033F0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_7_RP3_P2_0 = 0x8000033F0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_7_RP3_P2_1 = 0x8000073F0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_7_RP3_P2_1 = 0x8000073F0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_7_RP3_P2_2 = 0x80000B3F0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_7_RP3_P2_2 = 0x80000B3F0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_7_RP3_P2_3 = 0x80000F3F0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_7_RP3_P2_3 = 0x80000F3F0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_7_RP3_P2_4 = 0x8000133F0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_7_RP3_P2_4 = 0x8000133F0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_7_RP3_P3_0 = 0x8000033F07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_7_RP3_P3_0 = 0x8000033F08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_7_RP3_P3_1 = 0x8000073F07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_7_RP3_P3_1 = 0x8000073F08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_7_RP3_P3_2 = 0x80000B3F07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_7_RP3_P3_2 = 0x80000B3F08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_7_RP3_P3_3 = 0x80000F3F07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_7_RP3_P3_3 = 0x80000F3F08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_7_RP3_P3_4 = 0x8000133F07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_7_RP3_P3_4 = 0x8000133F08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP0_P0_0 = 0x800000400701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_8_RP0_P0_0 = 0x800000400701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_8_RP0_P0_0 = 0x800000400801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP0_P0_1 = 0x800004400701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_8_RP0_P0_1 = 0x800004400701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_8_RP0_P0_1 = 0x800004400801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP0_P0_2 = 0x800008400701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_8_RP0_P0_2 = 0x800008400701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_8_RP0_P0_2 = 0x800008400801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP0_P0_3 = 0x80000C400701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_8_RP0_P0_3 = 0x80000C400701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_8_RP0_P0_3 = 0x80000C400801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP0_P0_4 = 0x800010400701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_8_RP0_P0_4 = 0x800010400701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_8_RP0_P0_4 = 0x800010400801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_8_RP0_P1_0 = 0x800000400701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_8_RP0_P1_0 = 0x800000400801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_8_RP0_P1_1 = 0x800004400701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_8_RP0_P1_1 = 0x800004400801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_8_RP0_P1_2 = 0x800008400701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_8_RP0_P1_2 = 0x800008400801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_8_RP0_P1_3 = 0x80000C400701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_8_RP0_P1_3 = 0x80000C400801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_8_RP0_P1_4 = 0x800010400701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_8_RP0_P1_4 = 0x800010400801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_8_RP0_P2_0 = 0x800000400701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_8_RP0_P2_0 = 0x800000400801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_8_RP0_P2_1 = 0x800004400701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_8_RP0_P2_1 = 0x800004400801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_8_RP0_P2_2 = 0x800008400701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_8_RP0_P2_2 = 0x800008400801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_8_RP0_P2_3 = 0x80000C400701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_8_RP0_P2_3 = 0x80000C400801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_8_RP0_P2_4 = 0x800010400701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_8_RP0_P2_4 = 0x800010400801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_8_RP0_P3_0 = 0x8000004007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_8_RP0_P3_0 = 0x8000004008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_8_RP0_P3_1 = 0x8000044007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_8_RP0_P3_1 = 0x8000044008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_8_RP0_P3_2 = 0x8000084007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_8_RP0_P3_2 = 0x8000084008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_8_RP0_P3_3 = 0x80000C4007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_8_RP0_P3_3 = 0x80000C4008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_8_RP0_P3_4 = 0x8000104007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_8_RP0_P3_4 = 0x8000104008011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP1_P0_0 = 0x800001400701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_8_RP1_P0_0 = 0x800001400701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_8_RP1_P0_0 = 0x800001400801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP1_P0_1 = 0x800005400701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_8_RP1_P0_1 = 0x800005400701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_8_RP1_P0_1 = 0x800005400801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP1_P0_2 = 0x800009400701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_8_RP1_P0_2 = 0x800009400701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_8_RP1_P0_2 = 0x800009400801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP1_P0_3 = 0x80000D400701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_8_RP1_P0_3 = 0x80000D400701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_8_RP1_P0_3 = 0x80000D400801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP1_P0_4 = 0x800011400701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_8_RP1_P0_4 = 0x800011400701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_8_RP1_P0_4 = 0x800011400801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_8_RP1_P1_0 = 0x800001400701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_8_RP1_P1_0 = 0x800001400801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_8_RP1_P1_1 = 0x800005400701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_8_RP1_P1_1 = 0x800005400801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_8_RP1_P1_2 = 0x800009400701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_8_RP1_P1_2 = 0x800009400801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_8_RP1_P1_3 = 0x80000D400701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_8_RP1_P1_3 = 0x80000D400801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_8_RP1_P1_4 = 0x800011400701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_8_RP1_P1_4 = 0x800011400801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_8_RP1_P2_0 = 0x800001400701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_8_RP1_P2_0 = 0x800001400801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_8_RP1_P2_1 = 0x800005400701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_8_RP1_P2_1 = 0x800005400801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_8_RP1_P2_2 = 0x800009400701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_8_RP1_P2_2 = 0x800009400801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_8_RP1_P2_3 = 0x80000D400701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_8_RP1_P2_3 = 0x80000D400801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_8_RP1_P2_4 = 0x800011400701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_8_RP1_P2_4 = 0x800011400801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_8_RP1_P3_0 = 0x8000014007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_8_RP1_P3_0 = 0x8000014008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_8_RP1_P3_1 = 0x8000054007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_8_RP1_P3_1 = 0x8000054008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_8_RP1_P3_2 = 0x8000094007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_8_RP1_P3_2 = 0x8000094008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_8_RP1_P3_3 = 0x80000D4007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_8_RP1_P3_3 = 0x80000D4008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_8_RP1_P3_4 = 0x8000114007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_8_RP1_P3_4 = 0x8000114008011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP2_P0_0 = 0x800002400701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_8_RP2_P0_0 = 0x800002400701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_8_RP2_P0_0 = 0x800002400801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP2_P0_1 = 0x800006400701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_8_RP2_P0_1 = 0x800006400701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_8_RP2_P0_1 = 0x800006400801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP2_P0_2 = 0x80000A400701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_8_RP2_P0_2 = 0x80000A400701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_8_RP2_P0_2 = 0x80000A400801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP2_P0_3 = 0x80000E400701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_8_RP2_P0_3 = 0x80000E400701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_8_RP2_P0_3 = 0x80000E400801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP2_P0_4 = 0x800012400701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_8_RP2_P0_4 = 0x800012400701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_8_RP2_P0_4 = 0x800012400801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_8_RP2_P1_0 = 0x800002400701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_8_RP2_P1_0 = 0x800002400801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_8_RP2_P1_1 = 0x800006400701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_8_RP2_P1_1 = 0x800006400801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_8_RP2_P1_2 = 0x80000A400701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_8_RP2_P1_2 = 0x80000A400801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_8_RP2_P1_3 = 0x80000E400701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_8_RP2_P1_3 = 0x80000E400801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_8_RP2_P1_4 = 0x800012400701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_8_RP2_P1_4 = 0x800012400801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_8_RP2_P2_0 = 0x800002400701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_8_RP2_P2_0 = 0x800002400801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_8_RP2_P2_1 = 0x800006400701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_8_RP2_P2_1 = 0x800006400801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_8_RP2_P2_2 = 0x80000A400701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_8_RP2_P2_2 = 0x80000A400801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_8_RP2_P2_3 = 0x80000E400701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_8_RP2_P2_3 = 0x80000E400801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_8_RP2_P2_4 = 0x800012400701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_8_RP2_P2_4 = 0x800012400801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_8_RP2_P3_0 = 0x8000024007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_8_RP2_P3_0 = 0x8000024008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_8_RP2_P3_1 = 0x8000064007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_8_RP2_P3_1 = 0x8000064008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_8_RP2_P3_2 = 0x80000A4007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_8_RP2_P3_2 = 0x80000A4008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_8_RP2_P3_3 = 0x80000E4007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_8_RP2_P3_3 = 0x80000E4008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_8_RP2_P3_4 = 0x8000124007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_8_RP2_P3_4 = 0x8000124008011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP3_P0_0 = 0x800003400701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_8_RP3_P0_0 = 0x800003400701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_8_RP3_P0_0 = 0x800003400801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP3_P0_1 = 0x800007400701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_8_RP3_P0_1 = 0x800007400701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_8_RP3_P0_1 = 0x800007400801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP3_P0_2 = 0x80000B400701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_8_RP3_P0_2 = 0x80000B400701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_8_RP3_P0_2 = 0x80000B400801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP3_P0_3 = 0x80000F400701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_8_RP3_P0_3 = 0x80000F400701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_8_RP3_P0_3 = 0x80000F400801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP3_P0_4 = 0x800013400701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_8_RP3_P0_4 = 0x800013400701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_8_RP3_P0_4 = 0x800013400801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_8_RP3_P1_0 = 0x800003400701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_8_RP3_P1_0 = 0x800003400801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_8_RP3_P1_1 = 0x800007400701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_8_RP3_P1_1 = 0x800007400801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_8_RP3_P1_2 = 0x80000B400701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_8_RP3_P1_2 = 0x80000B400801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_8_RP3_P1_3 = 0x80000F400701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_8_RP3_P1_3 = 0x80000F400801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_8_RP3_P1_4 = 0x800013400701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_8_RP3_P1_4 = 0x800013400801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_8_RP3_P2_0 = 0x800003400701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_8_RP3_P2_0 = 0x800003400801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_8_RP3_P2_1 = 0x800007400701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_8_RP3_P2_1 = 0x800007400801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_8_RP3_P2_2 = 0x80000B400701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_8_RP3_P2_2 = 0x80000B400801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_8_RP3_P2_3 = 0x80000F400701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_8_RP3_P2_3 = 0x80000F400801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_8_RP3_P2_4 = 0x800013400701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_8_RP3_P2_4 = 0x800013400801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_8_RP3_P3_0 = 0x8000034007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_8_RP3_P3_0 = 0x8000034008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_8_RP3_P3_1 = 0x8000074007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_8_RP3_P3_1 = 0x8000074008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_8_RP3_P3_2 = 0x80000B4007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_8_RP3_P3_2 = 0x80000B4008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_8_RP3_P3_3 = 0x80000F4007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_8_RP3_P3_3 = 0x80000F4008011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_8_RP3_P3_4 = 0x8000134007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_8_RP3_P3_4 = 0x8000134008011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP0_P0_0 = 0x800000410701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_9_RP0_P0_0 = 0x800000410701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_9_RP0_P0_0 = 0x800000410801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP0_P0_1 = 0x800004410701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_9_RP0_P0_1 = 0x800004410701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_9_RP0_P0_1 = 0x800004410801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP0_P0_2 = 0x800008410701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_9_RP0_P0_2 = 0x800008410701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_9_RP0_P0_2 = 0x800008410801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP0_P0_3 = 0x80000C410701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_9_RP0_P0_3 = 0x80000C410701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_9_RP0_P0_3 = 0x80000C410801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP0_P0_4 = 0x800010410701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_9_RP0_P0_4 = 0x800010410701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_9_RP0_P0_4 = 0x800010410801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_9_RP0_P1_0 = 0x800000410701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_9_RP0_P1_0 = 0x800000410801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_9_RP0_P1_1 = 0x800004410701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_9_RP0_P1_1 = 0x800004410801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_9_RP0_P1_2 = 0x800008410701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_9_RP0_P1_2 = 0x800008410801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_9_RP0_P1_3 = 0x80000C410701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_9_RP0_P1_3 = 0x80000C410801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_9_RP0_P1_4 = 0x800010410701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_9_RP0_P1_4 = 0x800010410801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_9_RP0_P2_0 = 0x800000410701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_9_RP0_P2_0 = 0x800000410801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_9_RP0_P2_1 = 0x800004410701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_9_RP0_P2_1 = 0x800004410801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_9_RP0_P2_2 = 0x800008410701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_9_RP0_P2_2 = 0x800008410801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_9_RP0_P2_3 = 0x80000C410701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_9_RP0_P2_3 = 0x80000C410801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_9_RP0_P2_4 = 0x800010410701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_9_RP0_P2_4 = 0x800010410801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_9_RP0_P3_0 = 0x8000004107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_9_RP0_P3_0 = 0x8000004108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_9_RP0_P3_1 = 0x8000044107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_9_RP0_P3_1 = 0x8000044108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_9_RP0_P3_2 = 0x8000084107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_9_RP0_P3_2 = 0x8000084108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_9_RP0_P3_3 = 0x80000C4107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_9_RP0_P3_3 = 0x80000C4108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_9_RP0_P3_4 = 0x8000104107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_9_RP0_P3_4 = 0x8000104108011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP1_P0_0 = 0x800001410701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_9_RP1_P0_0 = 0x800001410701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_9_RP1_P0_0 = 0x800001410801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP1_P0_1 = 0x800005410701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_9_RP1_P0_1 = 0x800005410701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_9_RP1_P0_1 = 0x800005410801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP1_P0_2 = 0x800009410701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_9_RP1_P0_2 = 0x800009410701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_9_RP1_P0_2 = 0x800009410801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP1_P0_3 = 0x80000D410701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_9_RP1_P0_3 = 0x80000D410701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_9_RP1_P0_3 = 0x80000D410801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP1_P0_4 = 0x800011410701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_9_RP1_P0_4 = 0x800011410701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_9_RP1_P0_4 = 0x800011410801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_9_RP1_P1_0 = 0x800001410701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_9_RP1_P1_0 = 0x800001410801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_9_RP1_P1_1 = 0x800005410701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_9_RP1_P1_1 = 0x800005410801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_9_RP1_P1_2 = 0x800009410701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_9_RP1_P1_2 = 0x800009410801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_9_RP1_P1_3 = 0x80000D410701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_9_RP1_P1_3 = 0x80000D410801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_9_RP1_P1_4 = 0x800011410701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_9_RP1_P1_4 = 0x800011410801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_9_RP1_P2_0 = 0x800001410701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_9_RP1_P2_0 = 0x800001410801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_9_RP1_P2_1 = 0x800005410701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_9_RP1_P2_1 = 0x800005410801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_9_RP1_P2_2 = 0x800009410701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_9_RP1_P2_2 = 0x800009410801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_9_RP1_P2_3 = 0x80000D410701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_9_RP1_P2_3 = 0x80000D410801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_9_RP1_P2_4 = 0x800011410701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_9_RP1_P2_4 = 0x800011410801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_9_RP1_P3_0 = 0x8000014107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_9_RP1_P3_0 = 0x8000014108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_9_RP1_P3_1 = 0x8000054107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_9_RP1_P3_1 = 0x8000054108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_9_RP1_P3_2 = 0x8000094107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_9_RP1_P3_2 = 0x8000094108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_9_RP1_P3_3 = 0x80000D4107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_9_RP1_P3_3 = 0x80000D4108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_9_RP1_P3_4 = 0x8000114107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_9_RP1_P3_4 = 0x8000114108011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP2_P0_0 = 0x800002410701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_9_RP2_P0_0 = 0x800002410701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_9_RP2_P0_0 = 0x800002410801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP2_P0_1 = 0x800006410701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_9_RP2_P0_1 = 0x800006410701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_9_RP2_P0_1 = 0x800006410801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP2_P0_2 = 0x80000A410701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_9_RP2_P0_2 = 0x80000A410701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_9_RP2_P0_2 = 0x80000A410801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP2_P0_3 = 0x80000E410701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_9_RP2_P0_3 = 0x80000E410701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_9_RP2_P0_3 = 0x80000E410801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP2_P0_4 = 0x800012410701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_9_RP2_P0_4 = 0x800012410701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_9_RP2_P0_4 = 0x800012410801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_9_RP2_P1_0 = 0x800002410701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_9_RP2_P1_0 = 0x800002410801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_9_RP2_P1_1 = 0x800006410701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_9_RP2_P1_1 = 0x800006410801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_9_RP2_P1_2 = 0x80000A410701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_9_RP2_P1_2 = 0x80000A410801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_9_RP2_P1_3 = 0x80000E410701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_9_RP2_P1_3 = 0x80000E410801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_9_RP2_P1_4 = 0x800012410701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_9_RP2_P1_4 = 0x800012410801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_9_RP2_P2_0 = 0x800002410701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_9_RP2_P2_0 = 0x800002410801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_9_RP2_P2_1 = 0x800006410701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_9_RP2_P2_1 = 0x800006410801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_9_RP2_P2_2 = 0x80000A410701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_9_RP2_P2_2 = 0x80000A410801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_9_RP2_P2_3 = 0x80000E410701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_9_RP2_P2_3 = 0x80000E410801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_9_RP2_P2_4 = 0x800012410701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_9_RP2_P2_4 = 0x800012410801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_9_RP2_P3_0 = 0x8000024107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_9_RP2_P3_0 = 0x8000024108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_9_RP2_P3_1 = 0x8000064107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_9_RP2_P3_1 = 0x8000064108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_9_RP2_P3_2 = 0x80000A4107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_9_RP2_P3_2 = 0x80000A4108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_9_RP2_P3_3 = 0x80000E4107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_9_RP2_P3_3 = 0x80000E4108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_9_RP2_P3_4 = 0x8000124107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_9_RP2_P3_4 = 0x8000124108011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP3_P0_0 = 0x800003410701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_9_RP3_P0_0 = 0x800003410701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_9_RP3_P0_0 = 0x800003410801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP3_P0_1 = 0x800007410701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_9_RP3_P0_1 = 0x800007410701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_9_RP3_P0_1 = 0x800007410801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP3_P0_2 = 0x80000B410701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_9_RP3_P0_2 = 0x80000B410701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_9_RP3_P0_2 = 0x80000B410801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP3_P0_3 = 0x80000F410701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_9_RP3_P0_3 = 0x80000F410701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_9_RP3_P0_3 = 0x80000F410801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP3_P0_4 = 0x800013410701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_DELAY_VALUE_9_RP3_P0_4 = 0x800013410701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_DELAY_VALUE_9_RP3_P0_4 = 0x800013410801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_9_RP3_P1_0 = 0x800003410701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_9_RP3_P1_0 = 0x800003410801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_9_RP3_P1_1 = 0x800007410701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_9_RP3_P1_1 = 0x800007410801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_9_RP3_P1_2 = 0x80000B410701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_9_RP3_P1_2 = 0x80000B410801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_9_RP3_P1_3 = 0x80000F410701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_9_RP3_P1_3 = 0x80000F410801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_DELAY_VALUE_9_RP3_P1_4 = 0x800013410701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_DELAY_VALUE_9_RP3_P1_4 = 0x800013410801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_9_RP3_P2_0 = 0x800003410701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_9_RP3_P2_0 = 0x800003410801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_9_RP3_P2_1 = 0x800007410701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_9_RP3_P2_1 = 0x800007410801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_9_RP3_P2_2 = 0x80000B410701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_9_RP3_P2_2 = 0x80000B410801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_9_RP3_P2_3 = 0x80000F410701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_9_RP3_P2_3 = 0x80000F410801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_DELAY_VALUE_9_RP3_P2_4 = 0x800013410701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_DELAY_VALUE_9_RP3_P2_4 = 0x800013410801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_9_RP3_P3_0 = 0x8000034107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_9_RP3_P3_0 = 0x8000034108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_9_RP3_P3_1 = 0x8000074107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_9_RP3_P3_1 = 0x8000074108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_9_RP3_P3_2 = 0x80000B4107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_9_RP3_P3_2 = 0x80000B4108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_9_RP3_P3_3 = 0x80000F4107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_9_RP3_P3_3 = 0x80000F4108011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_DELAY_VALUE_9_RP3_P3_4 = 0x8000134107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_DELAY_VALUE_9_RP3_P3_4 = 0x8000134108011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_0 = 0x8000001B0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_ERROR0_P0_0 = 0x8000001B0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_ERROR0_P0_0 = 0x8000001B0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_1 = 0x8000041B0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_ERROR0_P0_1 = 0x8000041B0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_ERROR0_P0_1 = 0x8000041B0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_2 = 0x8000081B0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_ERROR0_P0_2 = 0x8000081B0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_ERROR0_P0_2 = 0x8000081B0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_3 = 0x80000C1B0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_ERROR0_P0_3 = 0x80000C1B0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_ERROR0_P0_3 = 0x80000C1B0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_4 = 0x8000101B0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_ERROR0_P0_4 = 0x8000101B0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_ERROR0_P0_4 = 0x8000101B0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_ERROR0_P1_0 = 0x8000001B0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_ERROR0_P1_0 = 0x8000001B0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_ERROR0_P1_1 = 0x8000041B0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_ERROR0_P1_1 = 0x8000041B0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_ERROR0_P1_2 = 0x8000081B0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_ERROR0_P1_2 = 0x8000081B0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_ERROR0_P1_3 = 0x80000C1B0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_ERROR0_P1_3 = 0x80000C1B0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_ERROR0_P1_4 = 0x8000101B0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_ERROR0_P1_4 = 0x8000101B0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_ERROR0_P2_0 = 0x8000001B0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_ERROR0_P2_0 = 0x8000001B0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_ERROR0_P2_1 = 0x8000041B0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_ERROR0_P2_1 = 0x8000041B0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_ERROR0_P2_2 = 0x8000081B0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_ERROR0_P2_2 = 0x8000081B0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_ERROR0_P2_3 = 0x80000C1B0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_ERROR0_P2_3 = 0x80000C1B0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_ERROR0_P2_4 = 0x8000101B0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_ERROR0_P2_4 = 0x8000101B0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_ERROR0_P3_0 = 0x8000001B07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_ERROR0_P3_0 = 0x8000001B08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_ERROR0_P3_1 = 0x8000041B07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_ERROR0_P3_1 = 0x8000041B08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_ERROR0_P3_2 = 0x8000081B07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_ERROR0_P3_2 = 0x8000081B08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_ERROR0_P3_3 = 0x80000C1B07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_ERROR0_P3_3 = 0x80000C1B08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_ERROR0_P3_4 = 0x8000101B07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_ERROR0_P3_4 = 0x8000101B08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_0 = 0x8000001C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_ERROR_MASK0_P0_0 = 0x8000001C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_ERROR_MASK0_P0_0 = 0x8000001C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_1 = 0x8000041C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_ERROR_MASK0_P0_1 = 0x8000041C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_ERROR_MASK0_P0_1 = 0x8000041C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_2 = 0x8000081C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_ERROR_MASK0_P0_2 = 0x8000081C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_ERROR_MASK0_P0_2 = 0x8000081C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_3 = 0x80000C1C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_ERROR_MASK0_P0_3 = 0x80000C1C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_ERROR_MASK0_P0_3 = 0x80000C1C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_4 = 0x8000101C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_ERROR_MASK0_P0_4 = 0x8000101C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_ERROR_MASK0_P0_4 = 0x8000101C0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_ERROR_MASK0_P1_0 = 0x8000001C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_ERROR_MASK0_P1_0 = 0x8000001C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_ERROR_MASK0_P1_1 = 0x8000041C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_ERROR_MASK0_P1_1 = 0x8000041C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_ERROR_MASK0_P1_2 = 0x8000081C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_ERROR_MASK0_P1_2 = 0x8000081C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_ERROR_MASK0_P1_3 = 0x80000C1C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_ERROR_MASK0_P1_3 = 0x80000C1C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_ERROR_MASK0_P1_4 = 0x8000101C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_ERROR_MASK0_P1_4 = 0x8000101C0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_ERROR_MASK0_P2_0 = 0x8000001C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_ERROR_MASK0_P2_0 = 0x8000001C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_ERROR_MASK0_P2_1 = 0x8000041C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_ERROR_MASK0_P2_1 = 0x8000041C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_ERROR_MASK0_P2_2 = 0x8000081C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_ERROR_MASK0_P2_2 = 0x8000081C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_ERROR_MASK0_P2_3 = 0x80000C1C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_ERROR_MASK0_P2_3 = 0x80000C1C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_ERROR_MASK0_P2_4 = 0x8000101C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_ERROR_MASK0_P2_4 = 0x8000101C0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_ERROR_MASK0_P3_0 = 0x8000001C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_ERROR_MASK0_P3_0 = 0x8000001C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_ERROR_MASK0_P3_1 = 0x8000041C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_ERROR_MASK0_P3_1 = 0x8000041C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_ERROR_MASK0_P3_2 = 0x8000081C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_ERROR_MASK0_P3_2 = 0x8000081C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_ERROR_MASK0_P3_3 = 0x80000C1C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_ERROR_MASK0_P3_3 = 0x80000C1C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_ERROR_MASK0_P3_4 = 0x8000101C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_ERROR_MASK0_P3_4 = 0x8000101C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_0 = 0x800000170701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_LVL_STATUS0_P0_0 = 0x800000170701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_LVL_STATUS0_P0_0 = 0x800000170801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_1 = 0x800004170701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_LVL_STATUS0_P0_1 = 0x800004170701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_LVL_STATUS0_P0_1 = 0x800004170801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_2 = 0x800008170701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_LVL_STATUS0_P0_2 = 0x800008170701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_LVL_STATUS0_P0_2 = 0x800008170801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_3 = 0x80000C170701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_LVL_STATUS0_P0_3 = 0x80000C170701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_LVL_STATUS0_P0_3 = 0x80000C170801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_4 = 0x800010170701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_LVL_STATUS0_P0_4 = 0x800010170701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_LVL_STATUS0_P0_4 = 0x800010170801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_LVL_STATUS0_P1_0 = 0x800000170701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_LVL_STATUS0_P1_0 = 0x800000170801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_LVL_STATUS0_P1_1 = 0x800004170701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_LVL_STATUS0_P1_1 = 0x800004170801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_LVL_STATUS0_P1_2 = 0x800008170701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_LVL_STATUS0_P1_2 = 0x800008170801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_LVL_STATUS0_P1_3 = 0x80000C170701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_LVL_STATUS0_P1_3 = 0x80000C170801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_LVL_STATUS0_P1_4 = 0x800010170701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_LVL_STATUS0_P1_4 = 0x800010170801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_LVL_STATUS0_P2_0 = 0x800000170701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_LVL_STATUS0_P2_0 = 0x800000170801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_LVL_STATUS0_P2_1 = 0x800004170701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_LVL_STATUS0_P2_1 = 0x800004170801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_LVL_STATUS0_P2_2 = 0x800008170701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_LVL_STATUS0_P2_2 = 0x800008170801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_LVL_STATUS0_P2_3 = 0x80000C170701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_LVL_STATUS0_P2_3 = 0x80000C170801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_LVL_STATUS0_P2_4 = 0x800010170701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_LVL_STATUS0_P2_4 = 0x800010170801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_LVL_STATUS0_P3_0 = 0x8000001707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_LVL_STATUS0_P3_0 = 0x8000001708011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_LVL_STATUS0_P3_1 = 0x8000041707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_LVL_STATUS0_P3_1 = 0x8000041708011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_LVL_STATUS0_P3_2 = 0x8000081707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_LVL_STATUS0_P3_2 = 0x8000081708011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_LVL_STATUS0_P3_3 = 0x80000C1707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_LVL_STATUS0_P3_3 = 0x80000C1708011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_LVL_STATUS0_P3_4 = 0x8000101707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_LVL_STATUS0_P3_4 = 0x8000101708011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_0 = 0x8000006C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_CONFIG0_P0_0 = 0x8000006C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_CONFIG0_P0_0 = 0x8000006C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_1 = 0x8000046C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_CONFIG0_P0_1 = 0x8000046C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_CONFIG0_P0_1 = 0x8000046C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_2 = 0x8000086C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_CONFIG0_P0_2 = 0x8000086C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_CONFIG0_P0_2 = 0x8000086C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_3 = 0x80000C6C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_CONFIG0_P0_3 = 0x80000C6C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_CONFIG0_P0_3 = 0x80000C6C0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_4 = 0x8000106C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_CONFIG0_P0_4 = 0x8000106C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_CONFIG0_P0_4 = 0x8000106C0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_CONFIG0_P1_0 = 0x8000006C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_CONFIG0_P1_0 = 0x8000006C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_CONFIG0_P1_1 = 0x8000046C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_CONFIG0_P1_1 = 0x8000046C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_CONFIG0_P1_2 = 0x8000086C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_CONFIG0_P1_2 = 0x8000086C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_CONFIG0_P1_3 = 0x80000C6C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_CONFIG0_P1_3 = 0x80000C6C0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_CONFIG0_P1_4 = 0x8000106C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_CONFIG0_P1_4 = 0x8000106C0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_CONFIG0_P2_0 = 0x8000006C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_CONFIG0_P2_0 = 0x8000006C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_CONFIG0_P2_1 = 0x8000046C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_CONFIG0_P2_1 = 0x8000046C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_CONFIG0_P2_2 = 0x8000086C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_CONFIG0_P2_2 = 0x8000086C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_CONFIG0_P2_3 = 0x80000C6C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_CONFIG0_P2_3 = 0x80000C6C0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_CONFIG0_P2_4 = 0x8000106C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_CONFIG0_P2_4 = 0x8000106C0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_CONFIG0_P3_0 = 0x8000006C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_CONFIG0_P3_0 = 0x8000006C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_CONFIG0_P3_1 = 0x8000046C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_CONFIG0_P3_1 = 0x8000046C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_CONFIG0_P3_2 = 0x8000086C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_CONFIG0_P3_2 = 0x8000086C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_CONFIG0_P3_3 = 0x80000C6C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_CONFIG0_P3_3 = 0x80000C6C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_CONFIG0_P3_4 = 0x8000106C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_CONFIG0_P3_4 = 0x8000106C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_0 = 0x800000EC0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_CONFIG1_P0_0 = 0x800000EC0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_CONFIG1_P0_0 = 0x800000EC0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_1 = 0x800004EC0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_CONFIG1_P0_1 = 0x800004EC0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_CONFIG1_P0_1 = 0x800004EC0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_2 = 0x800008EC0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_CONFIG1_P0_2 = 0x800008EC0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_CONFIG1_P0_2 = 0x800008EC0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_3 = 0x80000CEC0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_CONFIG1_P0_3 = 0x80000CEC0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_CONFIG1_P0_3 = 0x80000CEC0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_4 = 0x800010EC0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_CONFIG1_P0_4 = 0x800010EC0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_CONFIG1_P0_4 = 0x800010EC0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_CONFIG1_P1_0 = 0x800000EC0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_CONFIG1_P1_0 = 0x800000EC0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_CONFIG1_P1_1 = 0x800004EC0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_CONFIG1_P1_1 = 0x800004EC0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_CONFIG1_P1_2 = 0x800008EC0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_CONFIG1_P1_2 = 0x800008EC0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_CONFIG1_P1_3 = 0x80000CEC0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_CONFIG1_P1_3 = 0x80000CEC0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_CONFIG1_P1_4 = 0x800010EC0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_CONFIG1_P1_4 = 0x800010EC0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_CONFIG1_P2_0 = 0x800000EC0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_CONFIG1_P2_0 = 0x800000EC0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_CONFIG1_P2_1 = 0x800004EC0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_CONFIG1_P2_1 = 0x800004EC0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_CONFIG1_P2_2 = 0x800008EC0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_CONFIG1_P2_2 = 0x800008EC0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_CONFIG1_P2_3 = 0x80000CEC0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_CONFIG1_P2_3 = 0x80000CEC0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_CONFIG1_P2_4 = 0x800010EC0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_CONFIG1_P2_4 = 0x800010EC0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_CONFIG1_P3_0 = 0x800000EC07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_CONFIG1_P3_0 = 0x800000EC08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_CONFIG1_P3_1 = 0x800004EC07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_CONFIG1_P3_1 = 0x800004EC08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_CONFIG1_P3_2 = 0x800008EC07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_CONFIG1_P3_2 = 0x800008EC08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_CONFIG1_P3_3 = 0x80000CEC07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_CONFIG1_P3_3 = 0x80000CEC08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_CONFIG1_P3_4 = 0x800010EC07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_CONFIG1_P3_4 = 0x800010EC08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0 = 0x800000AE0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_ERROR0_P0_0 = 0x800000AE0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_ERROR0_P0_0 = 0x800000AE0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_1 = 0x800004AE0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_ERROR0_P0_1 = 0x800004AE0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_ERROR0_P0_1 = 0x800004AE0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_2 = 0x800008AE0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_ERROR0_P0_2 = 0x800008AE0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_ERROR0_P0_2 = 0x800008AE0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_3 = 0x80000CAE0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_ERROR0_P0_3 = 0x80000CAE0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_ERROR0_P0_3 = 0x80000CAE0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_4 = 0x800010AE0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_ERROR0_P0_4 = 0x800010AE0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_ERROR0_P0_4 = 0x800010AE0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_ERROR0_P1_0 = 0x800000AE0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_ERROR0_P1_0 = 0x800000AE0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_ERROR0_P1_1 = 0x800004AE0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_ERROR0_P1_1 = 0x800004AE0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_ERROR0_P1_2 = 0x800008AE0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_ERROR0_P1_2 = 0x800008AE0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_ERROR0_P1_3 = 0x80000CAE0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_ERROR0_P1_3 = 0x80000CAE0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_ERROR0_P1_4 = 0x800010AE0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_ERROR0_P1_4 = 0x800010AE0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_ERROR0_P2_0 = 0x800000AE0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_ERROR0_P2_0 = 0x800000AE0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_ERROR0_P2_1 = 0x800004AE0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_ERROR0_P2_1 = 0x800004AE0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_ERROR0_P2_2 = 0x800008AE0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_ERROR0_P2_2 = 0x800008AE0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_ERROR0_P2_3 = 0x80000CAE0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_ERROR0_P2_3 = 0x80000CAE0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_ERROR0_P2_4 = 0x800010AE0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_ERROR0_P2_4 = 0x800010AE0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_ERROR0_P3_0 = 0x800000AE07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_ERROR0_P3_0 = 0x800000AE08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_ERROR0_P3_1 = 0x800004AE07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_ERROR0_P3_1 = 0x800004AE08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_ERROR0_P3_2 = 0x800008AE07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_ERROR0_P3_2 = 0x800008AE08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_ERROR0_P3_3 = 0x80000CAE07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_ERROR0_P3_3 = 0x80000CAE08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_ERROR0_P3_4 = 0x800010AE07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_ERROR0_P3_4 = 0x800010AE08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_0 = 0x800000AF0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_ERROR1_P0_0 = 0x800000AF0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_ERROR1_P0_0 = 0x800000AF0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_1 = 0x800004AF0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_ERROR1_P0_1 = 0x800004AF0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_ERROR1_P0_1 = 0x800004AF0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_2 = 0x800008AF0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_ERROR1_P0_2 = 0x800008AF0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_ERROR1_P0_2 = 0x800008AF0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_3 = 0x80000CAF0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_ERROR1_P0_3 = 0x80000CAF0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_ERROR1_P0_3 = 0x80000CAF0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_4 = 0x800010AF0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_ERROR1_P0_4 = 0x800010AF0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_ERROR1_P0_4 = 0x800010AF0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_ERROR1_P1_0 = 0x800000AF0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_ERROR1_P1_0 = 0x800000AF0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_ERROR1_P1_1 = 0x800004AF0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_ERROR1_P1_1 = 0x800004AF0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_ERROR1_P1_2 = 0x800008AF0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_ERROR1_P1_2 = 0x800008AF0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_ERROR1_P1_3 = 0x80000CAF0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_ERROR1_P1_3 = 0x80000CAF0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_ERROR1_P1_4 = 0x800010AF0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_ERROR1_P1_4 = 0x800010AF0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_ERROR1_P2_0 = 0x800000AF0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_ERROR1_P2_0 = 0x800000AF0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_ERROR1_P2_1 = 0x800004AF0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_ERROR1_P2_1 = 0x800004AF0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_ERROR1_P2_2 = 0x800008AF0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_ERROR1_P2_2 = 0x800008AF0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_ERROR1_P2_3 = 0x80000CAF0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_ERROR1_P2_3 = 0x80000CAF0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_ERROR1_P2_4 = 0x800010AF0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_ERROR1_P2_4 = 0x800010AF0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_ERROR1_P3_0 = 0x800000AF07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_ERROR1_P3_0 = 0x800000AF08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_ERROR1_P3_1 = 0x800004AF07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_ERROR1_P3_1 = 0x800004AF08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_ERROR1_P3_2 = 0x800008AF07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_ERROR1_P3_2 = 0x800008AF08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_ERROR1_P3_3 = 0x80000CAF07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_ERROR1_P3_3 = 0x80000CAF08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_ERROR1_P3_4 = 0x800010AF07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_ERROR1_P3_4 = 0x800010AF08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0 = 0x800000FB0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0 = 0x800000FB0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0 = 0x800000FB0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1 = 0x800004FB0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1 = 0x800004FB0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1 = 0x800004FB0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2 = 0x800008FB0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2 = 0x800008FB0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2 = 0x800008FB0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3 = 0x80000CFB0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3 = 0x80000CFB0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3 = 0x80000CFB0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4 = 0x800010FB0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4 = 0x800010FB0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4 = 0x800010FB0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P1_0 = 0x800000FB0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P1_0 = 0x800000FB0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P1_1 = 0x800004FB0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P1_1 = 0x800004FB0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P1_2 = 0x800008FB0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P1_2 = 0x800008FB0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P1_3 = 0x80000CFB0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P1_3 = 0x80000CFB0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P1_4 = 0x800010FB0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P1_4 = 0x800010FB0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P2_0 = 0x800000FB0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P2_0 = 0x800000FB0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P2_1 = 0x800004FB0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P2_1 = 0x800004FB0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P2_2 = 0x800008FB0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P2_2 = 0x800008FB0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P2_3 = 0x80000CFB0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P2_3 = 0x80000CFB0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P2_4 = 0x800010FB0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P2_4 = 0x800010FB0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P3_0 = 0x800000FB07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P3_0 = 0x800000FB08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P3_1 = 0x800004FB07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P3_1 = 0x800004FB08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P3_2 = 0x800008FB07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P3_2 = 0x800008FB08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P3_3 = 0x80000CFB07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P3_3 = 0x80000CFB08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P3_4 = 0x800010FB07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P3_4 = 0x800010FB08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0 = 0x800000FA0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0 = 0x800000FA0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0 = 0x800000FA0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1 = 0x800004FA0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1 = 0x800004FA0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1 = 0x800004FA0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2 = 0x800008FA0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2 = 0x800008FA0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2 = 0x800008FA0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3 = 0x80000CFA0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3 = 0x80000CFA0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3 = 0x80000CFA0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4 = 0x800010FA0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4 = 0x800010FA0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4 = 0x800010FA0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P1_0 = 0x800000FA0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P1_0 = 0x800000FA0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P1_1 = 0x800004FA0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P1_1 = 0x800004FA0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P1_2 = 0x800008FA0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P1_2 = 0x800008FA0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P1_3 = 0x80000CFA0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P1_3 = 0x80000CFA0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P1_4 = 0x800010FA0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P1_4 = 0x800010FA0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P2_0 = 0x800000FA0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P2_0 = 0x800000FA0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P2_1 = 0x800004FA0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P2_1 = 0x800004FA0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P2_2 = 0x800008FA0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P2_2 = 0x800008FA0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P2_3 = 0x80000CFA0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P2_3 = 0x80000CFA0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P2_4 = 0x800010FA0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P2_4 = 0x800010FA0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P3_0 = 0x800000FA07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P3_0 = 0x800000FA08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P3_1 = 0x800004FA07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P3_1 = 0x800004FA08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P3_2 = 0x800008FA07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P3_2 = 0x800008FA08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P3_3 = 0x80000CFA07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P3_3 = 0x80000CFA08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P3_4 = 0x800010FA07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P3_4 = 0x800010FA08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_STATUS0_P0_0 = 0x8000002E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_STATUS0_P0_0 = 0x8000002E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_STATUS0_P0_0 = 0x8000002E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_STATUS0_P0_1 = 0x8000042E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_STATUS0_P0_1 = 0x8000042E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_STATUS0_P0_1 = 0x8000042E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_STATUS0_P0_2 = 0x8000082E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_STATUS0_P0_2 = 0x8000082E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_STATUS0_P0_2 = 0x8000082E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_STATUS0_P0_3 = 0x80000C2E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_STATUS0_P0_3 = 0x80000C2E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_STATUS0_P0_3 = 0x80000C2E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_STATUS0_P0_4 = 0x8000102E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_STATUS0_P0_4 = 0x8000102E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_STATUS0_P0_4 = 0x8000102E0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_STATUS0_P1_0 = 0x8000002E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_STATUS0_P1_0 = 0x8000002E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_STATUS0_P1_1 = 0x8000042E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_STATUS0_P1_1 = 0x8000042E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_STATUS0_P1_2 = 0x8000082E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_STATUS0_P1_2 = 0x8000082E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_STATUS0_P1_3 = 0x80000C2E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_STATUS0_P1_3 = 0x80000C2E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_STATUS0_P1_4 = 0x8000102E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_STATUS0_P1_4 = 0x8000102E0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_STATUS0_P2_0 = 0x8000002E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_STATUS0_P2_0 = 0x8000002E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_STATUS0_P2_1 = 0x8000042E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_STATUS0_P2_1 = 0x8000042E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_STATUS0_P2_2 = 0x8000082E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_STATUS0_P2_2 = 0x8000082E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_STATUS0_P2_3 = 0x80000C2E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_STATUS0_P2_3 = 0x80000C2E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_STATUS0_P2_4 = 0x8000102E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_STATUS0_P2_4 = 0x8000102E0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_STATUS0_P3_0 = 0x8000002E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_STATUS0_P3_0 = 0x8000002E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_STATUS0_P3_1 = 0x8000042E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_STATUS0_P3_1 = 0x8000042E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_STATUS0_P3_2 = 0x8000082E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_STATUS0_P3_2 = 0x8000082E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_STATUS0_P3_3 = 0x80000C2E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_STATUS0_P3_3 = 0x80000C2E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_STATUS0_P3_4 = 0x8000102E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_STATUS0_P3_4 = 0x8000102E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_0 = 0x8000002F0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_STATUS1_P0_0 = 0x8000002F0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_STATUS1_P0_0 = 0x8000002F0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_1 = 0x8000042F0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_STATUS1_P0_1 = 0x8000042F0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_STATUS1_P0_1 = 0x8000042F0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_2 = 0x8000082F0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_STATUS1_P0_2 = 0x8000082F0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_STATUS1_P0_2 = 0x8000082F0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_3 = 0x80000C2F0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_STATUS1_P0_3 = 0x80000C2F0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_STATUS1_P0_3 = 0x80000C2F0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_4 = 0x8000102F0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_STATUS1_P0_4 = 0x8000102F0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_STATUS1_P0_4 = 0x8000102F0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_STATUS1_P1_0 = 0x8000002F0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_STATUS1_P1_0 = 0x8000002F0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_STATUS1_P1_1 = 0x8000042F0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_STATUS1_P1_1 = 0x8000042F0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_STATUS1_P1_2 = 0x8000082F0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_STATUS1_P1_2 = 0x8000082F0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_STATUS1_P1_3 = 0x80000C2F0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_STATUS1_P1_3 = 0x80000C2F0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_STATUS1_P1_4 = 0x8000102F0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_STATUS1_P1_4 = 0x8000102F0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_STATUS1_P2_0 = 0x8000002F0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_STATUS1_P2_0 = 0x8000002F0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_STATUS1_P2_1 = 0x8000042F0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_STATUS1_P2_1 = 0x8000042F0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_STATUS1_P2_2 = 0x8000082F0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_STATUS1_P2_2 = 0x8000082F0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_STATUS1_P2_3 = 0x80000C2F0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_STATUS1_P2_3 = 0x80000C2F0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_STATUS1_P2_4 = 0x8000102F0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_STATUS1_P2_4 = 0x8000102F0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_STATUS1_P3_0 = 0x8000002F07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_STATUS1_P3_0 = 0x8000002F08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_STATUS1_P3_1 = 0x8000042F07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_STATUS1_P3_1 = 0x8000042F08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_STATUS1_P3_2 = 0x8000082F07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_STATUS1_P3_2 = 0x8000082F08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_STATUS1_P3_3 = 0x80000C2F07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_STATUS1_P3_3 = 0x80000C2F08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_STATUS1_P3_4 = 0x8000102F07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_STATUS1_P3_4 = 0x8000102F08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_0 = 0x8000005E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_0 = 0x8000005E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_0 = 0x8000005E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_1 = 0x8000045E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_1 = 0x8000045E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_1 = 0x8000045E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_2 = 0x8000085E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_2 = 0x8000085E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_2 = 0x8000085E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_3 = 0x80000C5E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_3 = 0x80000C5E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_3 = 0x80000C5E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_4 = 0x8000105E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_4 = 0x8000105E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_4 = 0x8000105E0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P1_0 = 0x8000005E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P1_0 = 0x8000005E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P1_1 = 0x8000045E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P1_1 = 0x8000045E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P1_2 = 0x8000085E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P1_2 = 0x8000085E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P1_3 = 0x80000C5E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P1_3 = 0x80000C5E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P1_4 = 0x8000105E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P1_4 = 0x8000105E0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P2_0 = 0x8000005E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P2_0 = 0x8000005E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P2_1 = 0x8000045E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P2_1 = 0x8000045E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P2_2 = 0x8000085E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P2_2 = 0x8000085E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P2_3 = 0x80000C5E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P2_3 = 0x80000C5E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P2_4 = 0x8000105E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P2_4 = 0x8000105E0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P3_0 = 0x8000005E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P3_0 = 0x8000005E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P3_1 = 0x8000045E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P3_1 = 0x8000045E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P3_2 = 0x8000085E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P3_2 = 0x8000085E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P3_3 = 0x80000C5E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P3_3 = 0x80000C5E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P3_4 = 0x8000105E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P3_4 = 0x8000105E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_0 = 0x8000015E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_0 = 0x8000015E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_0 = 0x8000015E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_1 = 0x8000055E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_1 = 0x8000055E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_1 = 0x8000055E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_2 = 0x8000095E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_2 = 0x8000095E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_2 = 0x8000095E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_3 = 0x80000D5E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_3 = 0x80000D5E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_3 = 0x80000D5E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_4 = 0x8000115E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_4 = 0x8000115E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_4 = 0x8000115E0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P1_0 = 0x8000015E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P1_0 = 0x8000015E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P1_1 = 0x8000055E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P1_1 = 0x8000055E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P1_2 = 0x8000095E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P1_2 = 0x8000095E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P1_3 = 0x80000D5E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P1_3 = 0x80000D5E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P1_4 = 0x8000115E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P1_4 = 0x8000115E0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P2_0 = 0x8000015E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P2_0 = 0x8000015E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P2_1 = 0x8000055E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P2_1 = 0x8000055E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P2_2 = 0x8000095E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P2_2 = 0x8000095E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P2_3 = 0x80000D5E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P2_3 = 0x80000D5E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P2_4 = 0x8000115E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P2_4 = 0x8000115E0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P3_0 = 0x8000015E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P3_0 = 0x8000015E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P3_1 = 0x8000055E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P3_1 = 0x8000055E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P3_2 = 0x8000095E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P3_2 = 0x8000095E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P3_3 = 0x80000D5E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P3_3 = 0x80000D5E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P3_4 = 0x8000115E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P3_4 = 0x8000115E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_0 = 0x8000025E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_0 = 0x8000025E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_0 = 0x8000025E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_1 = 0x8000065E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_1 = 0x8000065E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_1 = 0x8000065E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_2 = 0x80000A5E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_2 = 0x80000A5E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_2 = 0x80000A5E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_3 = 0x80000E5E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_3 = 0x80000E5E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_3 = 0x80000E5E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_4 = 0x8000125E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_4 = 0x8000125E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_4 = 0x8000125E0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P1_0 = 0x8000025E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P1_0 = 0x8000025E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P1_1 = 0x8000065E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P1_1 = 0x8000065E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P1_2 = 0x80000A5E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P1_2 = 0x80000A5E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P1_3 = 0x80000E5E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P1_3 = 0x80000E5E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P1_4 = 0x8000125E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P1_4 = 0x8000125E0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P2_0 = 0x8000025E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P2_0 = 0x8000025E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P2_1 = 0x8000065E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P2_1 = 0x8000065E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P2_2 = 0x80000A5E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P2_2 = 0x80000A5E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P2_3 = 0x80000E5E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P2_3 = 0x80000E5E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P2_4 = 0x8000125E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P2_4 = 0x8000125E0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P3_0 = 0x8000025E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P3_0 = 0x8000025E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P3_1 = 0x8000065E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P3_1 = 0x8000065E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P3_2 = 0x80000A5E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P3_2 = 0x80000A5E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P3_3 = 0x80000E5E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P3_3 = 0x80000E5E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P3_4 = 0x8000125E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P3_4 = 0x8000125E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_0 = 0x8000035E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_0 = 0x8000035E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_0 = 0x8000035E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_1 = 0x8000075E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_1 = 0x8000075E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_1 = 0x8000075E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_2 = 0x80000B5E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_2 = 0x80000B5E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_2 = 0x80000B5E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_3 = 0x80000F5E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_3 = 0x80000F5E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_3 = 0x80000F5E0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_4 = 0x8000135E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_4 = 0x8000135E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_4 = 0x8000135E0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P1_0 = 0x8000035E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P1_0 = 0x8000035E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P1_1 = 0x8000075E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P1_1 = 0x8000075E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P1_2 = 0x80000B5E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P1_2 = 0x80000B5E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P1_3 = 0x80000F5E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P1_3 = 0x80000F5E0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P1_4 = 0x8000135E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P1_4 = 0x8000135E0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P2_0 = 0x8000035E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P2_0 = 0x8000035E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P2_1 = 0x8000075E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P2_1 = 0x8000075E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P2_2 = 0x80000B5E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P2_2 = 0x80000B5E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P2_3 = 0x80000F5E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P2_3 = 0x80000F5E0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P2_4 = 0x8000135E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P2_4 = 0x8000135E0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P3_0 = 0x8000035E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P3_0 = 0x8000035E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P3_1 = 0x8000075E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P3_1 = 0x8000075E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P3_2 = 0x80000B5E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P3_2 = 0x80000B5E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P3_3 = 0x80000F5E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P3_3 = 0x80000F5E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P3_4 = 0x8000135E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P3_4 = 0x8000135E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_0 = 0x8000005F0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_0 = 0x8000005F0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_0 = 0x8000005F0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_1 = 0x8000045F0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_1 = 0x8000045F0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_1 = 0x8000045F0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_2 = 0x8000085F0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_2 = 0x8000085F0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_2 = 0x8000085F0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_3 = 0x80000C5F0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_3 = 0x80000C5F0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_3 = 0x80000C5F0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_4 = 0x8000105F0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_4 = 0x8000105F0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_4 = 0x8000105F0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P1_0 = 0x8000005F0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P1_0 = 0x8000005F0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P1_1 = 0x8000045F0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P1_1 = 0x8000045F0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P1_2 = 0x8000085F0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P1_2 = 0x8000085F0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P1_3 = 0x80000C5F0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P1_3 = 0x80000C5F0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P1_4 = 0x8000105F0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P1_4 = 0x8000105F0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P2_0 = 0x8000005F0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P2_0 = 0x8000005F0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P2_1 = 0x8000045F0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P2_1 = 0x8000045F0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P2_2 = 0x8000085F0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P2_2 = 0x8000085F0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P2_3 = 0x80000C5F0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P2_3 = 0x80000C5F0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P2_4 = 0x8000105F0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P2_4 = 0x8000105F0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P3_0 = 0x8000005F07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P3_0 = 0x8000005F08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P3_1 = 0x8000045F07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P3_1 = 0x8000045F08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P3_2 = 0x8000085F07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P3_2 = 0x8000085F08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P3_3 = 0x80000C5F07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P3_3 = 0x80000C5F08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P3_4 = 0x8000105F07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P3_4 = 0x8000105F08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_0 = 0x8000015F0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_0 = 0x8000015F0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_0 = 0x8000015F0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_1 = 0x8000055F0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_1 = 0x8000055F0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_1 = 0x8000055F0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_2 = 0x8000095F0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_2 = 0x8000095F0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_2 = 0x8000095F0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_3 = 0x80000D5F0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_3 = 0x80000D5F0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_3 = 0x80000D5F0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_4 = 0x8000115F0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_4 = 0x8000115F0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_4 = 0x8000115F0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P1_0 = 0x8000015F0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P1_0 = 0x8000015F0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P1_1 = 0x8000055F0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P1_1 = 0x8000055F0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P1_2 = 0x8000095F0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P1_2 = 0x8000095F0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P1_3 = 0x80000D5F0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P1_3 = 0x80000D5F0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P1_4 = 0x8000115F0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P1_4 = 0x8000115F0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P2_0 = 0x8000015F0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P2_0 = 0x8000015F0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P2_1 = 0x8000055F0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P2_1 = 0x8000055F0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P2_2 = 0x8000095F0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P2_2 = 0x8000095F0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P2_3 = 0x80000D5F0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P2_3 = 0x80000D5F0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P2_4 = 0x8000115F0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P2_4 = 0x8000115F0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P3_0 = 0x8000015F07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P3_0 = 0x8000015F08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P3_1 = 0x8000055F07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P3_1 = 0x8000055F08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P3_2 = 0x8000095F07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P3_2 = 0x8000095F08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P3_3 = 0x80000D5F07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P3_3 = 0x80000D5F08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P3_4 = 0x8000115F07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P3_4 = 0x8000115F08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_0 = 0x8000025F0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_0 = 0x8000025F0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_0 = 0x8000025F0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_1 = 0x8000065F0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_1 = 0x8000065F0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_1 = 0x8000065F0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_2 = 0x80000A5F0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_2 = 0x80000A5F0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_2 = 0x80000A5F0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_3 = 0x80000E5F0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_3 = 0x80000E5F0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_3 = 0x80000E5F0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_4 = 0x8000125F0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_4 = 0x8000125F0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_4 = 0x8000125F0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P1_0 = 0x8000025F0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P1_0 = 0x8000025F0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P1_1 = 0x8000065F0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P1_1 = 0x8000065F0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P1_2 = 0x80000A5F0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P1_2 = 0x80000A5F0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P1_3 = 0x80000E5F0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P1_3 = 0x80000E5F0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P1_4 = 0x8000125F0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P1_4 = 0x8000125F0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P2_0 = 0x8000025F0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P2_0 = 0x8000025F0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P2_1 = 0x8000065F0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P2_1 = 0x8000065F0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P2_2 = 0x80000A5F0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P2_2 = 0x80000A5F0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P2_3 = 0x80000E5F0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P2_3 = 0x80000E5F0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P2_4 = 0x8000125F0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P2_4 = 0x8000125F0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P3_0 = 0x8000025F07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P3_0 = 0x8000025F08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P3_1 = 0x8000065F07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P3_1 = 0x8000065F08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P3_2 = 0x80000A5F07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P3_2 = 0x80000A5F08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P3_3 = 0x80000E5F07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P3_3 = 0x80000E5F08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P3_4 = 0x8000125F07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P3_4 = 0x8000125F08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_0 = 0x8000035F0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_0 = 0x8000035F0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_0 = 0x8000035F0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_1 = 0x8000075F0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_1 = 0x8000075F0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_1 = 0x8000075F0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_2 = 0x80000B5F0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_2 = 0x80000B5F0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_2 = 0x80000B5F0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_3 = 0x80000F5F0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_3 = 0x80000F5F0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_3 = 0x80000F5F0801103Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_4 = 0x8000135F0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_4 = 0x8000135F0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_4 = 0x8000135F0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P1_0 = 0x8000035F0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P1_0 = 0x8000035F0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P1_1 = 0x8000075F0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P1_1 = 0x8000075F0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P1_2 = 0x80000B5F0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P1_2 = 0x80000B5F0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P1_3 = 0x80000F5F0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P1_3 = 0x80000F5F0801143Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P1_4 = 0x8000135F0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P1_4 = 0x8000135F0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P2_0 = 0x8000035F0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P2_0 = 0x8000035F0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P2_1 = 0x8000075F0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P2_1 = 0x8000075F0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P2_2 = 0x80000B5F0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P2_2 = 0x80000B5F0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P2_3 = 0x80000F5F0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P2_3 = 0x80000F5F0801183Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P2_4 = 0x8000135F0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P2_4 = 0x8000135F0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P3_0 = 0x8000035F07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P3_0 = 0x8000035F08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P3_1 = 0x8000075F07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P3_1 = 0x8000075F08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P3_2 = 0x80000B5F07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P3_2 = 0x80000B5F08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P3_3 = 0x80000F5F07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P3_3 = 0x80000F5F08011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P3_4 = 0x8000135F07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P3_4 = 0x8000135F08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_PC_BASE_CNTR0_P0 = 0x8000C0040701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_PC_BASE_CNTR0_P0 = 0x8000C0040701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_PC_BASE_CNTR0_P0 = 0x8000C0040801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_PC_BASE_CNTR0_P1 = 0x8000C0040701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_PC_BASE_CNTR0_P1 = 0x8000C0040801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_PC_BASE_CNTR0_P2 = 0x8000C0040701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_PC_BASE_CNTR0_P2 = 0x8000C0040801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_PC_BASE_CNTR0_P3 = 0x8000C00407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_PC_BASE_CNTR0_P3 = 0x8000C00408011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_PC_BASE_CNTR1_P0 = 0x8000C0060701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_PC_BASE_CNTR1_P0 = 0x8000C0060701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_PC_BASE_CNTR1_P0 = 0x8000C0060801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_PC_BASE_CNTR1_P1 = 0x8000C0060701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_PC_BASE_CNTR1_P1 = 0x8000C0060801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_PC_BASE_CNTR1_P2 = 0x8000C0060701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_PC_BASE_CNTR1_P2 = 0x8000C0060801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_PC_BASE_CNTR1_P3 = 0x8000C00607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_PC_BASE_CNTR1_P3 = 0x8000C00608011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_PC_CAL_TIMER_P0 = 0x8000C0070701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_PC_CAL_TIMER_P0 = 0x8000C0070701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_PC_CAL_TIMER_P0 = 0x8000C0070801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_PC_CAL_TIMER_P1 = 0x8000C0070701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_PC_CAL_TIMER_P1 = 0x8000C0070801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_PC_CAL_TIMER_P2 = 0x8000C0070701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_PC_CAL_TIMER_P2 = 0x8000C0070801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_PC_CAL_TIMER_P3 = 0x8000C00707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_PC_CAL_TIMER_P3 = 0x8000C00708011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_PC_CAL_TIMER_RELOAD_VALUE_P0 = 0x8000C0080701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_PC_CAL_TIMER_RELOAD_VALUE_P0 = 0x8000C0080701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_PC_CAL_TIMER_RELOAD_VALUE_P0 = 0x8000C0080801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_PC_CAL_TIMER_RELOAD_VALUE_P1 = 0x8000C0080701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_PC_CAL_TIMER_RELOAD_VALUE_P1 = 0x8000C0080801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_PC_CAL_TIMER_RELOAD_VALUE_P2 = 0x8000C0080701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_PC_CAL_TIMER_RELOAD_VALUE_P2 = 0x8000C0080801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_PC_CAL_TIMER_RELOAD_VALUE_P3 = 0x8000C00807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_PC_CAL_TIMER_RELOAD_VALUE_P3 = 0x8000C00808011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_PC_CONFIG0_P0 = 0x8000C00C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_PC_CONFIG0_P0 = 0x8000C00C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_PC_CONFIG0_P0 = 0x8000C00C0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_PC_CONFIG0_P1 = 0x8000C00C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_PC_CONFIG0_P1 = 0x8000C00C0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_PC_CONFIG0_P2 = 0x8000C00C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_PC_CONFIG0_P2 = 0x8000C00C0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_PC_CONFIG0_P3 = 0x8000C00C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_PC_CONFIG0_P3 = 0x8000C00C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_PC_CONFIG1_P0 = 0x8000C00D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_PC_CONFIG1_P0 = 0x8000C00D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_PC_CONFIG1_P0 = 0x8000C00D0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_PC_CONFIG1_P1 = 0x8000C00D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_PC_CONFIG1_P1 = 0x8000C00D0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_PC_CONFIG1_P2 = 0x8000C00D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_PC_CONFIG1_P2 = 0x8000C00D0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_PC_CONFIG1_P3 = 0x8000C00D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_PC_CONFIG1_P3 = 0x8000C00D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_PC_CSID_CFG_P0 = 0x8000C0330701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_PC_CSID_CFG_P0 = 0x8000C0330701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_PC_CSID_CFG_P0 = 0x8000C0330801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_PC_CSID_CFG_P1 = 0x8000C0330701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_PC_CSID_CFG_P1 = 0x8000C0330801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_PC_CSID_CFG_P2 = 0x8000C0330701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_PC_CSID_CFG_P2 = 0x8000C0330801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_PC_CSID_CFG_P3 = 0x8000C03307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_PC_CSID_CFG_P3 = 0x8000C03308011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_PC_DLL_ZCAL_CAL_STATUS_P0 = 0x8000C0000701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_PC_DLL_ZCAL_CAL_STATUS_P0 = 0x8000C0000701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_PC_DLL_ZCAL_CAL_STATUS_P0 = 0x8000C0000801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_PC_DLL_ZCAL_CAL_STATUS_P1 = 0x8000C0000701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_PC_DLL_ZCAL_CAL_STATUS_P1 = 0x8000C0000801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_PC_DLL_ZCAL_CAL_STATUS_P2 = 0x8000C0000701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_PC_DLL_ZCAL_CAL_STATUS_P2 = 0x8000C0000801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_PC_DLL_ZCAL_CAL_STATUS_P3 = 0x8000C00007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_PC_DLL_ZCAL_CAL_STATUS_P3 = 0x8000C00008011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_PC_ERROR_MASK0_P0 = 0x8000C0130701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_PC_ERROR_MASK0_P0 = 0x8000C0130701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_PC_ERROR_MASK0_P0 = 0x8000C0130801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_PC_ERROR_MASK0_P1 = 0x8000C0130701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_PC_ERROR_MASK0_P1 = 0x8000C0130801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_PC_ERROR_MASK0_P2 = 0x8000C0130701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_PC_ERROR_MASK0_P2 = 0x8000C0130801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_PC_ERROR_MASK0_P3 = 0x8000C01307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_PC_ERROR_MASK0_P3 = 0x8000C01308011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_PC_ERROR_STATUS0_P0 = 0x8000C0120701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_PC_ERROR_STATUS0_P0 = 0x8000C0120701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_PC_ERROR_STATUS0_P0 = 0x8000C0120801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_PC_ERROR_STATUS0_P1 = 0x8000C0120701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_PC_ERROR_STATUS0_P1 = 0x8000C0120801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_PC_ERROR_STATUS0_P2 = 0x8000C0120701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_PC_ERROR_STATUS0_P2 = 0x8000C0120801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_PC_ERROR_STATUS0_P3 = 0x8000C01207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_PC_ERROR_STATUS0_P3 = 0x8000C01208011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0 = 0x8000C0160701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_PC_INIT_CAL_CONFIG0_P0 = 0x8000C0160701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_PC_INIT_CAL_CONFIG0_P0 = 0x8000C0160801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_PC_INIT_CAL_CONFIG0_P1 = 0x8000C0160701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_PC_INIT_CAL_CONFIG0_P1 = 0x8000C0160801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_PC_INIT_CAL_CONFIG0_P2 = 0x8000C0160701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_PC_INIT_CAL_CONFIG0_P2 = 0x8000C0160801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_PC_INIT_CAL_CONFIG0_P3 = 0x8000C01607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_PC_INIT_CAL_CONFIG0_P3 = 0x8000C01608011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_PC_INIT_CAL_CONFIG1_P0 = 0x8000C0170701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_PC_INIT_CAL_CONFIG1_P0 = 0x8000C0170701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_PC_INIT_CAL_CONFIG1_P0 = 0x8000C0170801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_PC_INIT_CAL_CONFIG1_P1 = 0x8000C0170701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_PC_INIT_CAL_CONFIG1_P1 = 0x8000C0170801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_PC_INIT_CAL_CONFIG1_P2 = 0x8000C0170701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_PC_INIT_CAL_CONFIG1_P2 = 0x8000C0170801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_PC_INIT_CAL_CONFIG1_P3 = 0x8000C01707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_PC_INIT_CAL_CONFIG1_P3 = 0x8000C01708011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_PC_INIT_CAL_ERROR_P0 = 0x8000C0180701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_PC_INIT_CAL_ERROR_P0 = 0x8000C0180701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_PC_INIT_CAL_ERROR_P0 = 0x8000C0180801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_PC_INIT_CAL_ERROR_P1 = 0x8000C0180701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_PC_INIT_CAL_ERROR_P1 = 0x8000C0180801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_PC_INIT_CAL_ERROR_P2 = 0x8000C0180701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_PC_INIT_CAL_ERROR_P2 = 0x8000C0180801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_PC_INIT_CAL_ERROR_P3 = 0x8000C01807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_PC_INIT_CAL_ERROR_P3 = 0x8000C01808011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_PC_INIT_CAL_MASK_P0 = 0x8000C01A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_PC_INIT_CAL_MASK_P0 = 0x8000C01A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_PC_INIT_CAL_MASK_P0 = 0x8000C01A0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_PC_INIT_CAL_MASK_P1 = 0x8000C01A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_PC_INIT_CAL_MASK_P1 = 0x8000C01A0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_PC_INIT_CAL_MASK_P2 = 0x8000C01A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_PC_INIT_CAL_MASK_P2 = 0x8000C01A0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_PC_INIT_CAL_MASK_P3 = 0x8000C01A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_PC_INIT_CAL_MASK_P3 = 0x8000C01A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_PC_INIT_CAL_STATUS_P0 = 0x8000C0190701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_PC_INIT_CAL_STATUS_P0 = 0x8000C0190701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_PC_INIT_CAL_STATUS_P0 = 0x8000C0190801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_PC_INIT_CAL_STATUS_P1 = 0x8000C0190701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_PC_INIT_CAL_STATUS_P1 = 0x8000C0190801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_PC_INIT_CAL_STATUS_P2 = 0x8000C0190701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_PC_INIT_CAL_STATUS_P2 = 0x8000C0190801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_PC_INIT_CAL_STATUS_P3 = 0x8000C01907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_PC_INIT_CAL_STATUS_P3 = 0x8000C01908011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_PC_IO_PVT_FET_CONTROL_P0 = 0x8000C0140701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_PC_IO_PVT_FET_CONTROL_P0 = 0x8000C0140701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_PC_IO_PVT_FET_CONTROL_P0 = 0x8000C0140801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_PC_IO_PVT_FET_CONTROL_P1 = 0x8000C0140701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_PC_IO_PVT_FET_CONTROL_P1 = 0x8000C0140801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_PC_IO_PVT_FET_CONTROL_P2 = 0x8000C0140701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_PC_IO_PVT_FET_CONTROL_P2 = 0x8000C0140801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_PC_IO_PVT_FET_CONTROL_P3 = 0x8000C01407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_PC_IO_PVT_FET_CONTROL_P3 = 0x8000C01408011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_PC_IO_PVT_FET_STATUS_P0 = 0x8000C01B0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_PC_IO_PVT_FET_STATUS_P0 = 0x8000C01B0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_PC_IO_PVT_FET_STATUS_P0 = 0x8000C01B0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_PC_IO_PVT_FET_STATUS_P1 = 0x8000C01B0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_PC_IO_PVT_FET_STATUS_P1 = 0x8000C01B0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_PC_IO_PVT_FET_STATUS_P2 = 0x8000C01B0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_PC_IO_PVT_FET_STATUS_P2 = 0x8000C01B0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_PC_IO_PVT_FET_STATUS_P3 = 0x8000C01B07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_PC_IO_PVT_FET_STATUS_P3 = 0x8000C01B08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_PC_MIRROR_CONFIG_P0 = 0x8000C0110701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_PC_MIRROR_CONFIG_P0 = 0x8000C0110701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_PC_MIRROR_CONFIG_P0 = 0x8000C0110801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_PC_MIRROR_CONFIG_P1 = 0x8000C0110701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_PC_MIRROR_CONFIG_P1 = 0x8000C0110801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_PC_MIRROR_CONFIG_P2 = 0x8000C0110701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_PC_MIRROR_CONFIG_P2 = 0x8000C0110801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_PC_MIRROR_CONFIG_P3 = 0x8000C01107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_PC_MIRROR_CONFIG_P3 = 0x8000C01108011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_PC_MR0_RP0_P0 = 0x8000C01C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_PC_MR0_RP0_P0 = 0x8000C01C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_PC_MR0_RP0_P0 = 0x8000C01C0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_PC_MR0_RP0_P1 = 0x8000C01C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_PC_MR0_RP0_P1 = 0x8000C01C0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_PC_MR0_RP0_P2 = 0x8000C01C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_PC_MR0_RP0_P2 = 0x8000C01C0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_PC_MR0_RP0_P3 = 0x8000C01C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_PC_MR0_RP0_P3 = 0x8000C01C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_PC_MR0_RP1_P0 = 0x8000C11C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_PC_MR0_RP1_P0 = 0x8000C11C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_PC_MR0_RP1_P0 = 0x8000C11C0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_PC_MR0_RP1_P1 = 0x8000C11C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_PC_MR0_RP1_P1 = 0x8000C11C0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_PC_MR0_RP1_P2 = 0x8000C11C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_PC_MR0_RP1_P2 = 0x8000C11C0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_PC_MR0_RP1_P3 = 0x8000C11C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_PC_MR0_RP1_P3 = 0x8000C11C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_PC_MR0_RP2_P0 = 0x8000C21C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_PC_MR0_RP2_P0 = 0x8000C21C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_PC_MR0_RP2_P0 = 0x8000C21C0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_PC_MR0_RP2_P1 = 0x8000C21C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_PC_MR0_RP2_P1 = 0x8000C21C0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_PC_MR0_RP2_P2 = 0x8000C21C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_PC_MR0_RP2_P2 = 0x8000C21C0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_PC_MR0_RP2_P3 = 0x8000C21C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_PC_MR0_RP2_P3 = 0x8000C21C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_PC_MR0_RP3_P0 = 0x8000C31C0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_PC_MR0_RP3_P0 = 0x8000C31C0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_PC_MR0_RP3_P0 = 0x8000C31C0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_PC_MR0_RP3_P1 = 0x8000C31C0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_PC_MR0_RP3_P1 = 0x8000C31C0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_PC_MR0_RP3_P2 = 0x8000C31C0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_PC_MR0_RP3_P2 = 0x8000C31C0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_PC_MR0_RP3_P3 = 0x8000C31C07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_PC_MR0_RP3_P3 = 0x8000C31C08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_PC_MR1_RP0_P0 = 0x8000C01D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_PC_MR1_RP0_P0 = 0x8000C01D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_PC_MR1_RP0_P0 = 0x8000C01D0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_PC_MR1_RP0_P1 = 0x8000C01D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_PC_MR1_RP0_P1 = 0x8000C01D0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_PC_MR1_RP0_P2 = 0x8000C01D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_PC_MR1_RP0_P2 = 0x8000C01D0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_PC_MR1_RP0_P3 = 0x8000C01D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_PC_MR1_RP0_P3 = 0x8000C01D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_PC_MR1_RP1_P0 = 0x8000C11D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_PC_MR1_RP1_P0 = 0x8000C11D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_PC_MR1_RP1_P0 = 0x8000C11D0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_PC_MR1_RP1_P1 = 0x8000C11D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_PC_MR1_RP1_P1 = 0x8000C11D0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_PC_MR1_RP1_P2 = 0x8000C11D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_PC_MR1_RP1_P2 = 0x8000C11D0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_PC_MR1_RP1_P3 = 0x8000C11D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_PC_MR1_RP1_P3 = 0x8000C11D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_PC_MR1_RP2_P0 = 0x8000C21D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_PC_MR1_RP2_P0 = 0x8000C21D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_PC_MR1_RP2_P0 = 0x8000C21D0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_PC_MR1_RP2_P1 = 0x8000C21D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_PC_MR1_RP2_P1 = 0x8000C21D0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_PC_MR1_RP2_P2 = 0x8000C21D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_PC_MR1_RP2_P2 = 0x8000C21D0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_PC_MR1_RP2_P3 = 0x8000C21D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_PC_MR1_RP2_P3 = 0x8000C21D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_PC_MR1_RP3_P0 = 0x8000C31D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_PC_MR1_RP3_P0 = 0x8000C31D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_PC_MR1_RP3_P0 = 0x8000C31D0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_PC_MR1_RP3_P1 = 0x8000C31D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_PC_MR1_RP3_P1 = 0x8000C31D0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_PC_MR1_RP3_P2 = 0x8000C31D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_PC_MR1_RP3_P2 = 0x8000C31D0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_PC_MR1_RP3_P3 = 0x8000C31D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_PC_MR1_RP3_P3 = 0x8000C31D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_PC_MR2_RP0_P0 = 0x8000C01E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_PC_MR2_RP0_P0 = 0x8000C01E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_PC_MR2_RP0_P0 = 0x8000C01E0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_PC_MR2_RP0_P1 = 0x8000C01E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_PC_MR2_RP0_P1 = 0x8000C01E0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_PC_MR2_RP0_P2 = 0x8000C01E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_PC_MR2_RP0_P2 = 0x8000C01E0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_PC_MR2_RP0_P3 = 0x8000C01E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_PC_MR2_RP0_P3 = 0x8000C01E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_PC_MR2_RP1_P0 = 0x8000C11E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_PC_MR2_RP1_P0 = 0x8000C11E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_PC_MR2_RP1_P0 = 0x8000C11E0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_PC_MR2_RP1_P1 = 0x8000C11E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_PC_MR2_RP1_P1 = 0x8000C11E0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_PC_MR2_RP1_P2 = 0x8000C11E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_PC_MR2_RP1_P2 = 0x8000C11E0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_PC_MR2_RP1_P3 = 0x8000C11E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_PC_MR2_RP1_P3 = 0x8000C11E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_PC_MR2_RP2_P0 = 0x8000C21E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_PC_MR2_RP2_P0 = 0x8000C21E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_PC_MR2_RP2_P0 = 0x8000C21E0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_PC_MR2_RP2_P1 = 0x8000C21E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_PC_MR2_RP2_P1 = 0x8000C21E0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_PC_MR2_RP2_P2 = 0x8000C21E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_PC_MR2_RP2_P2 = 0x8000C21E0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_PC_MR2_RP2_P3 = 0x8000C21E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_PC_MR2_RP2_P3 = 0x8000C21E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_PC_MR2_RP3_P0 = 0x8000C31E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_PC_MR2_RP3_P0 = 0x8000C31E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_PC_MR2_RP3_P0 = 0x8000C31E0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_PC_MR2_RP3_P1 = 0x8000C31E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_PC_MR2_RP3_P1 = 0x8000C31E0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_PC_MR2_RP3_P2 = 0x8000C31E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_PC_MR2_RP3_P2 = 0x8000C31E0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_PC_MR2_RP3_P3 = 0x8000C31E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_PC_MR2_RP3_P3 = 0x8000C31E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_PC_MR3_RP0_P0 = 0x8000C01F0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_PC_MR3_RP0_P0 = 0x8000C01F0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_PC_MR3_RP0_P0 = 0x8000C01F0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_PC_MR3_RP0_P1 = 0x8000C01F0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_PC_MR3_RP0_P1 = 0x8000C01F0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_PC_MR3_RP0_P2 = 0x8000C01F0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_PC_MR3_RP0_P2 = 0x8000C01F0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_PC_MR3_RP0_P3 = 0x8000C01F07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_PC_MR3_RP0_P3 = 0x8000C01F08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_PC_MR3_RP1_P0 = 0x8000C11F0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_PC_MR3_RP1_P0 = 0x8000C11F0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_PC_MR3_RP1_P0 = 0x8000C11F0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_PC_MR3_RP1_P1 = 0x8000C11F0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_PC_MR3_RP1_P1 = 0x8000C11F0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_PC_MR3_RP1_P2 = 0x8000C11F0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_PC_MR3_RP1_P2 = 0x8000C11F0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_PC_MR3_RP1_P3 = 0x8000C11F07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_PC_MR3_RP1_P3 = 0x8000C11F08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_PC_MR3_RP2_P0 = 0x8000C21F0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_PC_MR3_RP2_P0 = 0x8000C21F0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_PC_MR3_RP2_P0 = 0x8000C21F0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_PC_MR3_RP2_P1 = 0x8000C21F0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_PC_MR3_RP2_P1 = 0x8000C21F0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_PC_MR3_RP2_P2 = 0x8000C21F0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_PC_MR3_RP2_P2 = 0x8000C21F0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_PC_MR3_RP2_P3 = 0x8000C21F07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_PC_MR3_RP2_P3 = 0x8000C21F08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_PC_MR3_RP3_P0 = 0x8000C31F0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_PC_MR3_RP3_P0 = 0x8000C31F0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_PC_MR3_RP3_P0 = 0x8000C31F0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_PC_MR3_RP3_P1 = 0x8000C31F0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_PC_MR3_RP3_P1 = 0x8000C31F0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_PC_MR3_RP3_P2 = 0x8000C31F0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_PC_MR3_RP3_P2 = 0x8000C31F0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_PC_MR3_RP3_P3 = 0x8000C31F07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_PC_MR3_RP3_P3 = 0x8000C31F08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_PC_MR4_RP0_P0 = 0x8000C0200701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_PC_MR4_RP0_P0 = 0x8000C0200701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_PC_MR4_RP0_P0 = 0x8000C0200801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_PC_MR4_RP0_P1 = 0x8000C0200701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_PC_MR4_RP0_P1 = 0x8000C0200801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_PC_MR4_RP0_P2 = 0x8000C0200701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_PC_MR4_RP0_P2 = 0x8000C0200801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_PC_MR4_RP0_P3 = 0x8000C02007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_PC_MR4_RP0_P3 = 0x8000C02008011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_PC_MR4_RP1_P0 = 0x8000C1200701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_PC_MR4_RP1_P0 = 0x8000C1200701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_PC_MR4_RP1_P0 = 0x8000C1200801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_PC_MR4_RP1_P1 = 0x8000C1200701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_PC_MR4_RP1_P1 = 0x8000C1200801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_PC_MR4_RP1_P2 = 0x8000C1200701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_PC_MR4_RP1_P2 = 0x8000C1200801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_PC_MR4_RP1_P3 = 0x8000C12007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_PC_MR4_RP1_P3 = 0x8000C12008011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_PC_MR4_RP2_P0 = 0x8000C2200701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_PC_MR4_RP2_P0 = 0x8000C2200701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_PC_MR4_RP2_P0 = 0x8000C2200801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_PC_MR4_RP2_P1 = 0x8000C2200701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_PC_MR4_RP2_P1 = 0x8000C2200801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_PC_MR4_RP2_P2 = 0x8000C2200701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_PC_MR4_RP2_P2 = 0x8000C2200801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_PC_MR4_RP2_P3 = 0x8000C22007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_PC_MR4_RP2_P3 = 0x8000C22008011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_PC_MR4_RP3_P0 = 0x8000C3200701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_PC_MR4_RP3_P0 = 0x8000C3200701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_PC_MR4_RP3_P0 = 0x8000C3200801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_PC_MR4_RP3_P1 = 0x8000C3200701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_PC_MR4_RP3_P1 = 0x8000C3200801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_PC_MR4_RP3_P2 = 0x8000C3200701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_PC_MR4_RP3_P2 = 0x8000C3200801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_PC_MR4_RP3_P3 = 0x8000C32007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_PC_MR4_RP3_P3 = 0x8000C32008011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_PC_MR5_RP0_P0 = 0x8000C0210701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_PC_MR5_RP0_P0 = 0x8000C0210701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_PC_MR5_RP0_P0 = 0x8000C0210801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_PC_MR5_RP0_P1 = 0x8000C0210701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_PC_MR5_RP0_P1 = 0x8000C0210801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_PC_MR5_RP0_P2 = 0x8000C0210701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_PC_MR5_RP0_P2 = 0x8000C0210801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_PC_MR5_RP0_P3 = 0x8000C02107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_PC_MR5_RP0_P3 = 0x8000C02108011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_PC_MR5_RP1_P0 = 0x8000C1210701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_PC_MR5_RP1_P0 = 0x8000C1210701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_PC_MR5_RP1_P0 = 0x8000C1210801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_PC_MR5_RP1_P1 = 0x8000C1210701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_PC_MR5_RP1_P1 = 0x8000C1210801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_PC_MR5_RP1_P2 = 0x8000C1210701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_PC_MR5_RP1_P2 = 0x8000C1210801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_PC_MR5_RP1_P3 = 0x8000C12107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_PC_MR5_RP1_P3 = 0x8000C12108011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_PC_MR5_RP2_P0 = 0x8000C2210701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_PC_MR5_RP2_P0 = 0x8000C2210701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_PC_MR5_RP2_P0 = 0x8000C2210801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_PC_MR5_RP2_P1 = 0x8000C2210701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_PC_MR5_RP2_P1 = 0x8000C2210801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_PC_MR5_RP2_P2 = 0x8000C2210701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_PC_MR5_RP2_P2 = 0x8000C2210801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_PC_MR5_RP2_P3 = 0x8000C22107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_PC_MR5_RP2_P3 = 0x8000C22108011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_PC_MR5_RP3_P0 = 0x8000C3210701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_PC_MR5_RP3_P0 = 0x8000C3210701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_PC_MR5_RP3_P0 = 0x8000C3210801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_PC_MR5_RP3_P1 = 0x8000C3210701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_PC_MR5_RP3_P1 = 0x8000C3210801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_PC_MR5_RP3_P2 = 0x8000C3210701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_PC_MR5_RP3_P2 = 0x8000C3210801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_PC_MR5_RP3_P3 = 0x8000C32107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_PC_MR5_RP3_P3 = 0x8000C32108011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_PC_MR6_RP0_P0 = 0x8000C0220701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_PC_MR6_RP0_P0 = 0x8000C0220701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_PC_MR6_RP0_P0 = 0x8000C0220801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_PC_MR6_RP0_P1 = 0x8000C0220701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_PC_MR6_RP0_P1 = 0x8000C0220801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_PC_MR6_RP0_P2 = 0x8000C0220701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_PC_MR6_RP0_P2 = 0x8000C0220801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_PC_MR6_RP0_P3 = 0x8000C02207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_PC_MR6_RP0_P3 = 0x8000C02208011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_PC_MR6_RP1_P0 = 0x8000C1220701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_PC_MR6_RP1_P0 = 0x8000C1220701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_PC_MR6_RP1_P0 = 0x8000C1220801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_PC_MR6_RP1_P1 = 0x8000C1220701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_PC_MR6_RP1_P1 = 0x8000C1220801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_PC_MR6_RP1_P2 = 0x8000C1220701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_PC_MR6_RP1_P2 = 0x8000C1220801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_PC_MR6_RP1_P3 = 0x8000C12207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_PC_MR6_RP1_P3 = 0x8000C12208011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_PC_MR6_RP2_P0 = 0x8000C2220701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_PC_MR6_RP2_P0 = 0x8000C2220701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_PC_MR6_RP2_P0 = 0x8000C2220801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_PC_MR6_RP2_P1 = 0x8000C2220701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_PC_MR6_RP2_P1 = 0x8000C2220801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_PC_MR6_RP2_P2 = 0x8000C2220701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_PC_MR6_RP2_P2 = 0x8000C2220801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_PC_MR6_RP2_P3 = 0x8000C22207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_PC_MR6_RP2_P3 = 0x8000C22208011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_PC_MR6_RP3_P0 = 0x8000C3220701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_PC_MR6_RP3_P0 = 0x8000C3220701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_PC_MR6_RP3_P0 = 0x8000C3220801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_PC_MR6_RP3_P1 = 0x8000C3220701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_PC_MR6_RP3_P1 = 0x8000C3220801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_PC_MR6_RP3_P2 = 0x8000C3220701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_PC_MR6_RP3_P2 = 0x8000C3220801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_PC_MR6_RP3_P3 = 0x8000C32207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_PC_MR6_RP3_P3 = 0x8000C32208011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_PC_MR7_RP0_P0 = 0x8000C0230701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_PC_MR7_RP0_P0 = 0x8000C0230701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_PC_MR7_RP0_P0 = 0x8000C0230801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_PC_MR7_RP0_P1 = 0x8000C0230701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_PC_MR7_RP0_P1 = 0x8000C0230801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_PC_MR7_RP0_P2 = 0x8000C0230701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_PC_MR7_RP0_P2 = 0x8000C0230801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_PC_MR7_RP0_P3 = 0x8000C02307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_PC_MR7_RP0_P3 = 0x8000C02308011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_PC_MR7_RP1_P0 = 0x8000C1230701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_PC_MR7_RP1_P0 = 0x8000C1230701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_PC_MR7_RP1_P0 = 0x8000C1230801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_PC_MR7_RP1_P1 = 0x8000C1230701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_PC_MR7_RP1_P1 = 0x8000C1230801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_PC_MR7_RP1_P2 = 0x8000C1230701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_PC_MR7_RP1_P2 = 0x8000C1230801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_PC_MR7_RP1_P3 = 0x8000C12307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_PC_MR7_RP1_P3 = 0x8000C12308011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_PC_MR7_RP2_P0 = 0x8000C2230701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_PC_MR7_RP2_P0 = 0x8000C2230701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_PC_MR7_RP2_P0 = 0x8000C2230801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_PC_MR7_RP2_P1 = 0x8000C2230701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_PC_MR7_RP2_P1 = 0x8000C2230801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_PC_MR7_RP2_P2 = 0x8000C2230701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_PC_MR7_RP2_P2 = 0x8000C2230801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_PC_MR7_RP2_P3 = 0x8000C22307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_PC_MR7_RP2_P3 = 0x8000C22308011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_PC_MR7_RP3_P0 = 0x8000C3230701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_PC_MR7_RP3_P0 = 0x8000C3230701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_PC_MR7_RP3_P0 = 0x8000C3230801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_PC_MR7_RP3_P1 = 0x8000C3230701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_PC_MR7_RP3_P1 = 0x8000C3230801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_PC_MR7_RP3_P2 = 0x8000C3230701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_PC_MR7_RP3_P2 = 0x8000C3230801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_PC_MR7_RP3_P3 = 0x8000C32307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_PC_MR7_RP3_P3 = 0x8000C32308011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_PC_PBA_CONTROL_P0 = 0x8000C0150701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_PC_PBA_CONTROL_P0 = 0x8000C0150701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_PC_PBA_CONTROL_P0 = 0x8000C0150801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_PC_PBA_CONTROL_P1 = 0x8000C0150701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_PC_PBA_CONTROL_P1 = 0x8000C0150801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_PC_PBA_CONTROL_P2 = 0x8000C0150701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_PC_PBA_CONTROL_P2 = 0x8000C0150801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_PC_PBA_CONTROL_P3 = 0x8000C01507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_PC_PBA_CONTROL_P3 = 0x8000C01508011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_PC_PER_CAL_CONFIG_P0 = 0x8000C00B0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_PC_PER_CAL_CONFIG_P0 = 0x8000C00B0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_PC_PER_CAL_CONFIG_P0 = 0x8000C00B0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_PC_PER_CAL_CONFIG_P1 = 0x8000C00B0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_PC_PER_CAL_CONFIG_P1 = 0x8000C00B0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_PC_PER_CAL_CONFIG_P2 = 0x8000C00B0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_PC_PER_CAL_CONFIG_P2 = 0x8000C00B0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_PC_PER_CAL_CONFIG_P3 = 0x8000C00B07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_PC_PER_CAL_CONFIG_P3 = 0x8000C00B08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_PC_PER_ERR_INJECT_P0 = 0x8000C0010701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_PC_PER_ERR_INJECT_P0 = 0x8000C0010701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_PC_PER_ERR_INJECT_P0 = 0x8000C0010801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_PC_PER_ERR_INJECT_P1 = 0x8000C0010701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_PC_PER_ERR_INJECT_P1 = 0x8000C0010801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_PC_PER_ERR_INJECT_P2 = 0x8000C0010701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_PC_PER_ERR_INJECT_P2 = 0x8000C0010801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_PC_PER_ERR_INJECT_P3 = 0x8000C00107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_PC_PER_ERR_INJECT_P3 = 0x8000C00108011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_PC_PER_ZCAL_CONFIG_P0 = 0x8000C00F0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_PC_PER_ZCAL_CONFIG_P0 = 0x8000C00F0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_PC_PER_ZCAL_CONFIG_P0 = 0x8000C00F0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_PC_PER_ZCAL_CONFIG_P1 = 0x8000C00F0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_PC_PER_ZCAL_CONFIG_P1 = 0x8000C00F0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_PC_PER_ZCAL_CONFIG_P2 = 0x8000C00F0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_PC_PER_ZCAL_CONFIG_P2 = 0x8000C00F0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_PC_PER_ZCAL_CONFIG_P3 = 0x8000C00F07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_PC_PER_ZCAL_CONFIG_P3 = 0x8000C00F08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_PC_POWERDOWN_1_P0 = 0x8000C0100701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_PC_POWERDOWN_1_P0 = 0x8000C0100701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_PC_POWERDOWN_1_P0 = 0x8000C0100801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_PC_POWERDOWN_1_P1 = 0x8000C0100701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_PC_POWERDOWN_1_P1 = 0x8000C0100801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_PC_POWERDOWN_1_P2 = 0x8000C0100701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_PC_POWERDOWN_1_P2 = 0x8000C0100801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_PC_POWERDOWN_1_P3 = 0x8000C01007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_PC_POWERDOWN_1_P3 = 0x8000C01008011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_PC_RANK_GROUP_EXT_P0 = 0x8000C0350701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_PC_RANK_GROUP_EXT_P0 = 0x8000C0350701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_PC_RANK_GROUP_EXT_P0 = 0x8000C0350801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_PC_RANK_GROUP_EXT_P1 = 0x8000C0350701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_PC_RANK_GROUP_EXT_P1 = 0x8000C0350801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_PC_RANK_GROUP_EXT_P2 = 0x8000C0350701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_PC_RANK_GROUP_EXT_P2 = 0x8000C0350801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_PC_RANK_GROUP_EXT_P3 = 0x8000C03507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_PC_RANK_GROUP_EXT_P3 = 0x8000C03508011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_PC_RANK_PAIR0_P0 = 0x8000C0020701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_PC_RANK_PAIR0_P0 = 0x8000C0020701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_PC_RANK_PAIR0_P0 = 0x8000C0020801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_PC_RANK_PAIR0_P1 = 0x8000C0020701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_PC_RANK_PAIR0_P1 = 0x8000C0020801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_PC_RANK_PAIR0_P2 = 0x8000C0020701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_PC_RANK_PAIR0_P2 = 0x8000C0020801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_PC_RANK_PAIR0_P3 = 0x8000C00207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_PC_RANK_PAIR0_P3 = 0x8000C00208011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_PC_RANK_PAIR1_P0 = 0x8000C0030701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_PC_RANK_PAIR1_P0 = 0x8000C0030701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_PC_RANK_PAIR1_P0 = 0x8000C0030801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_PC_RANK_PAIR1_P1 = 0x8000C0030701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_PC_RANK_PAIR1_P1 = 0x8000C0030801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_PC_RANK_PAIR1_P2 = 0x8000C0030701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_PC_RANK_PAIR1_P2 = 0x8000C0030801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_PC_RANK_PAIR1_P3 = 0x8000C00307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_PC_RANK_PAIR1_P3 = 0x8000C00308011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_PC_RANK_PAIR2_P0 = 0x8000C0300701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_PC_RANK_PAIR2_P0 = 0x8000C0300701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_PC_RANK_PAIR2_P0 = 0x8000C0300801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_PC_RANK_PAIR2_P1 = 0x8000C0300701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_PC_RANK_PAIR2_P1 = 0x8000C0300801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_PC_RANK_PAIR2_P2 = 0x8000C0300701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_PC_RANK_PAIR2_P2 = 0x8000C0300801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_PC_RANK_PAIR2_P3 = 0x8000C03007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_PC_RANK_PAIR2_P3 = 0x8000C03008011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_PC_RANK_PAIR3_P0 = 0x8000C0310701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_PC_RANK_PAIR3_P0 = 0x8000C0310701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_PC_RANK_PAIR3_P0 = 0x8000C0310801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_PC_RANK_PAIR3_P1 = 0x8000C0310701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_PC_RANK_PAIR3_P1 = 0x8000C0310801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_PC_RANK_PAIR3_P2 = 0x8000C0310701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_PC_RANK_PAIR3_P2 = 0x8000C0310801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_PC_RANK_PAIR3_P3 = 0x8000C03107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_PC_RANK_PAIR3_P3 = 0x8000C03108011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_PC_RELOAD_VALUE0_P0 = 0x8000C0050701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_PC_RELOAD_VALUE0_P0 = 0x8000C0050701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_PC_RELOAD_VALUE0_P0 = 0x8000C0050801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_PC_RELOAD_VALUE0_P1 = 0x8000C0050701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_PC_RELOAD_VALUE0_P1 = 0x8000C0050801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_PC_RELOAD_VALUE0_P2 = 0x8000C0050701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_PC_RELOAD_VALUE0_P2 = 0x8000C0050801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_PC_RELOAD_VALUE0_P3 = 0x8000C00507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_PC_RELOAD_VALUE0_P3 = 0x8000C00508011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_PC_RESETS_P0 = 0x8000C00E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_PC_RESETS_P0 = 0x8000C00E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_PC_RESETS_P0 = 0x8000C00E0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_PC_RESETS_P1 = 0x8000C00E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_PC_RESETS_P1 = 0x8000C00E0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_PC_RESETS_P2 = 0x8000C00E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_PC_RESETS_P2 = 0x8000C00E0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_PC_RESETS_P3 = 0x8000C00E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_PC_RESETS_P3 = 0x8000C00E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_PC_ZCAL_TIMER_P0 = 0x8000C0090701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_PC_ZCAL_TIMER_P0 = 0x8000C0090701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_PC_ZCAL_TIMER_P0 = 0x8000C0090801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_PC_ZCAL_TIMER_P1 = 0x8000C0090701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_PC_ZCAL_TIMER_P1 = 0x8000C0090801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_PC_ZCAL_TIMER_P2 = 0x8000C0090701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_PC_ZCAL_TIMER_P2 = 0x8000C0090801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_PC_ZCAL_TIMER_P3 = 0x8000C00907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_PC_ZCAL_TIMER_P3 = 0x8000C00908011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_PC_ZCAL_TIMER_RELOAD_VALUE_P0 = 0x8000C00A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_PC_ZCAL_TIMER_RELOAD_VALUE_P0 = 0x8000C00A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_PC_ZCAL_TIMER_RELOAD_VALUE_P0 = 0x8000C00A0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_PC_ZCAL_TIMER_RELOAD_VALUE_P1 = 0x8000C00A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_PC_ZCAL_TIMER_RELOAD_VALUE_P1 = 0x8000C00A0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_PC_ZCAL_TIMER_RELOAD_VALUE_P2 = 0x8000C00A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_PC_ZCAL_TIMER_RELOAD_VALUE_P2 = 0x8000C00A0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_PC_ZCAL_TIMER_RELOAD_VALUE_P3 = 0x8000C00A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_PC_ZCAL_TIMER_RELOAD_VALUE_P3 = 0x8000C00A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_RC_CONFIG0_P0 = 0x8000C8000701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_RC_CONFIG0_P0 = 0x8000C8000701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_RC_CONFIG0_P0 = 0x8000C8000801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_RC_CONFIG0_P1 = 0x8000C8000701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_RC_CONFIG0_P1 = 0x8000C8000801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_RC_CONFIG0_P2 = 0x8000C8000701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_RC_CONFIG0_P2 = 0x8000C8000801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_RC_CONFIG0_P3 = 0x8000C80007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_RC_CONFIG0_P3 = 0x8000C80008011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_RC_CONFIG1_P0 = 0x8000C8010701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_RC_CONFIG1_P0 = 0x8000C8010701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_RC_CONFIG1_P0 = 0x8000C8010801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_RC_CONFIG1_P1 = 0x8000C8010701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_RC_CONFIG1_P1 = 0x8000C8010801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_RC_CONFIG1_P2 = 0x8000C8010701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_RC_CONFIG1_P2 = 0x8000C8010801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_RC_CONFIG1_P3 = 0x8000C80107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_RC_CONFIG1_P3 = 0x8000C80108011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_RC_CONFIG2_P0 = 0x8000C8020701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_RC_CONFIG2_P0 = 0x8000C8020701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_RC_CONFIG2_P0 = 0x8000C8020801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_RC_CONFIG2_P1 = 0x8000C8020701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_RC_CONFIG2_P1 = 0x8000C8020801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_RC_CONFIG2_P2 = 0x8000C8020701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_RC_CONFIG2_P2 = 0x8000C8020801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_RC_CONFIG2_P3 = 0x8000C80207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_RC_CONFIG2_P3 = 0x8000C80208011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_RC_CONFIG3_P0 = 0x8000C8070701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_RC_CONFIG3_P0 = 0x8000C8070701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_RC_CONFIG3_P0 = 0x8000C8070801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_RC_CONFIG3_P1 = 0x8000C8070701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_RC_CONFIG3_P1 = 0x8000C8070801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_RC_CONFIG3_P2 = 0x8000C8070701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_RC_CONFIG3_P2 = 0x8000C8070801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_RC_CONFIG3_P3 = 0x8000C80707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_RC_CONFIG3_P3 = 0x8000C80708011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_RC_ERROR_MASK0_P0 = 0x8000C8060701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_RC_ERROR_MASK0_P0 = 0x8000C8060701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_RC_ERROR_MASK0_P0 = 0x8000C8060801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_RC_ERROR_MASK0_P1 = 0x8000C8060701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_RC_ERROR_MASK0_P1 = 0x8000C8060801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_RC_ERROR_MASK0_P2 = 0x8000C8060701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_RC_ERROR_MASK0_P2 = 0x8000C8060801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_RC_ERROR_MASK0_P3 = 0x8000C80607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_RC_ERROR_MASK0_P3 = 0x8000C80608011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_RC_ERROR_STATUS0_P0 = 0x8000C8050701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_RC_ERROR_STATUS0_P0 = 0x8000C8050701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_RC_ERROR_STATUS0_P0 = 0x8000C8050801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_RC_ERROR_STATUS0_P1 = 0x8000C8050701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_RC_ERROR_STATUS0_P1 = 0x8000C8050801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_RC_ERROR_STATUS0_P2 = 0x8000C8050701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_RC_ERROR_STATUS0_P2 = 0x8000C8050801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_RC_ERROR_STATUS0_P3 = 0x8000C80507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_RC_ERROR_STATUS0_P3 = 0x8000C80508011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_RC_RDVREF_CONFIG0_P0 = 0x8000C8090701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_RC_RDVREF_CONFIG0_P0 = 0x8000C8090701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_RC_RDVREF_CONFIG0_P0 = 0x8000C8090801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_RC_RDVREF_CONFIG0_P1 = 0x8000C8090701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_RC_RDVREF_CONFIG0_P1 = 0x8000C8090801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_RC_RDVREF_CONFIG0_P2 = 0x8000C8090701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_RC_RDVREF_CONFIG0_P2 = 0x8000C8090801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_RC_RDVREF_CONFIG0_P3 = 0x8000C80907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_RC_RDVREF_CONFIG0_P3 = 0x8000C80908011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_RC_RDVREF_CONFIG1_P0 = 0x8000C80A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_RC_RDVREF_CONFIG1_P0 = 0x8000C80A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_RC_RDVREF_CONFIG1_P0 = 0x8000C80A0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_RC_RDVREF_CONFIG1_P1 = 0x8000C80A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_RC_RDVREF_CONFIG1_P1 = 0x8000C80A0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_RC_RDVREF_CONFIG1_P2 = 0x8000C80A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_RC_RDVREF_CONFIG1_P2 = 0x8000C80A0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_RC_RDVREF_CONFIG1_P3 = 0x8000C80A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_RC_RDVREF_CONFIG1_P3 = 0x8000C80A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_SEQ_CONFIG0_P0 = 0x8000C4020701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_SEQ_CONFIG0_P0 = 0x8000C4020701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_SEQ_CONFIG0_P0 = 0x8000C4020801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_SEQ_CONFIG0_P1 = 0x8000C4020701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_SEQ_CONFIG0_P1 = 0x8000C4020801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_SEQ_CONFIG0_P2 = 0x8000C4020701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_SEQ_CONFIG0_P2 = 0x8000C4020801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_SEQ_CONFIG0_P3 = 0x8000C40207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_SEQ_CONFIG0_P3 = 0x8000C40208011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_SEQ_ERROR_MASK0_P0 = 0x8000C4090701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_SEQ_ERROR_MASK0_P0 = 0x8000C4090701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_SEQ_ERROR_MASK0_P0 = 0x8000C4090801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_SEQ_ERROR_MASK0_P1 = 0x8000C4090701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_SEQ_ERROR_MASK0_P1 = 0x8000C4090801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_SEQ_ERROR_MASK0_P2 = 0x8000C4090701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_SEQ_ERROR_MASK0_P2 = 0x8000C4090801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_SEQ_ERROR_MASK0_P3 = 0x8000C40907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_SEQ_ERROR_MASK0_P3 = 0x8000C40908011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_SEQ_ERROR_STATUS0_P0 = 0x8000C4080701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_SEQ_ERROR_STATUS0_P0 = 0x8000C4080701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_SEQ_ERROR_STATUS0_P0 = 0x8000C4080801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_SEQ_ERROR_STATUS0_P1 = 0x8000C4080701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_SEQ_ERROR_STATUS0_P1 = 0x8000C4080801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_SEQ_ERROR_STATUS0_P2 = 0x8000C4080701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_SEQ_ERROR_STATUS0_P2 = 0x8000C4080801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_SEQ_ERROR_STATUS0_P3 = 0x8000C40807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_SEQ_ERROR_STATUS0_P3 = 0x8000C40808011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_SEQ_LPT_ADDR2_P0 = 0x8000C4170701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_SEQ_LPT_ADDR2_P0 = 0x8000C4170701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_SEQ_LPT_ADDR2_P0 = 0x8000C4170801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_SEQ_LPT_ADDR2_P1 = 0x8000C4170701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_SEQ_LPT_ADDR2_P1 = 0x8000C4170801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_SEQ_LPT_ADDR2_P2 = 0x8000C4170701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_SEQ_LPT_ADDR2_P2 = 0x8000C4170801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_SEQ_LPT_ADDR2_P3 = 0x8000C41707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_SEQ_LPT_ADDR2_P3 = 0x8000C41708011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_SEQ_LPT_ADDR3_P0 = 0x8000C4180701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_SEQ_LPT_ADDR3_P0 = 0x8000C4180701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_SEQ_LPT_ADDR3_P0 = 0x8000C4180801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_SEQ_LPT_ADDR3_P1 = 0x8000C4180701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_SEQ_LPT_ADDR3_P1 = 0x8000C4180801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_SEQ_LPT_ADDR3_P2 = 0x8000C4180701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_SEQ_LPT_ADDR3_P2 = 0x8000C4180801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_SEQ_LPT_ADDR3_P3 = 0x8000C41807011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_SEQ_LPT_ADDR3_P3 = 0x8000C41808011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_SEQ_LPT_ADDR4_P0 = 0x8000C4190701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_SEQ_LPT_ADDR4_P0 = 0x8000C4190701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_SEQ_LPT_ADDR4_P0 = 0x8000C4190801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_SEQ_LPT_ADDR4_P1 = 0x8000C4190701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_SEQ_LPT_ADDR4_P1 = 0x8000C4190801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_SEQ_LPT_ADDR4_P2 = 0x8000C4190701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_SEQ_LPT_ADDR4_P2 = 0x8000C4190801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_SEQ_LPT_ADDR4_P3 = 0x8000C41907011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_SEQ_LPT_ADDR4_P3 = 0x8000C41908011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_SEQ_MEM_TIMING_PARAM0_P0 = 0x8000C4120701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_SEQ_MEM_TIMING_PARAM0_P0 = 0x8000C4120701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_SEQ_MEM_TIMING_PARAM0_P0 = 0x8000C4120801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_SEQ_MEM_TIMING_PARAM0_P1 = 0x8000C4120701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_SEQ_MEM_TIMING_PARAM0_P1 = 0x8000C4120801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_SEQ_MEM_TIMING_PARAM0_P2 = 0x8000C4120701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_SEQ_MEM_TIMING_PARAM0_P2 = 0x8000C4120801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_SEQ_MEM_TIMING_PARAM0_P3 = 0x8000C41207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_SEQ_MEM_TIMING_PARAM0_P3 = 0x8000C41208011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_SEQ_MEM_TIMING_PARAM1_P0 = 0x8000C4130701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_SEQ_MEM_TIMING_PARAM1_P0 = 0x8000C4130701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_SEQ_MEM_TIMING_PARAM1_P0 = 0x8000C4130801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_SEQ_MEM_TIMING_PARAM1_P1 = 0x8000C4130701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_SEQ_MEM_TIMING_PARAM1_P1 = 0x8000C4130801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_SEQ_MEM_TIMING_PARAM1_P2 = 0x8000C4130701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_SEQ_MEM_TIMING_PARAM1_P2 = 0x8000C4130801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_SEQ_MEM_TIMING_PARAM1_P3 = 0x8000C41307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_SEQ_MEM_TIMING_PARAM1_P3 = 0x8000C41308011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_SEQ_MEM_TIMING_PARAM2_P0 = 0x8000C4140701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_SEQ_MEM_TIMING_PARAM2_P0 = 0x8000C4140701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_SEQ_MEM_TIMING_PARAM2_P0 = 0x8000C4140801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_SEQ_MEM_TIMING_PARAM2_P1 = 0x8000C4140701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_SEQ_MEM_TIMING_PARAM2_P1 = 0x8000C4140801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_SEQ_MEM_TIMING_PARAM2_P2 = 0x8000C4140701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_SEQ_MEM_TIMING_PARAM2_P2 = 0x8000C4140801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_SEQ_MEM_TIMING_PARAM2_P3 = 0x8000C41407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_SEQ_MEM_TIMING_PARAM2_P3 = 0x8000C41408011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_SEQ_ODT_DEFAULT_CONFIG_P0 = 0x8000C4240701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_SEQ_ODT_DEFAULT_CONFIG_P0 = 0x8000C4240701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_SEQ_ODT_DEFAULT_CONFIG_P0 = 0x8000C4240801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_SEQ_ODT_DEFAULT_CONFIG_P1 = 0x8000C4240701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_SEQ_ODT_DEFAULT_CONFIG_P1 = 0x8000C4240801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_SEQ_ODT_DEFAULT_CONFIG_P2 = 0x8000C4240701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_SEQ_ODT_DEFAULT_CONFIG_P2 = 0x8000C4240801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_SEQ_ODT_DEFAULT_CONFIG_P3 = 0x8000C42407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_SEQ_ODT_DEFAULT_CONFIG_P3 = 0x8000C42408011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_SEQ_ODT_RD_CONFIG0_P0 = 0x8000C40E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_SEQ_ODT_RD_CONFIG0_P0 = 0x8000C40E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_SEQ_ODT_RD_CONFIG0_P0 = 0x8000C40E0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_SEQ_ODT_RD_CONFIG0_P1 = 0x8000C40E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_SEQ_ODT_RD_CONFIG0_P1 = 0x8000C40E0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_SEQ_ODT_RD_CONFIG0_P2 = 0x8000C40E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_SEQ_ODT_RD_CONFIG0_P2 = 0x8000C40E0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_SEQ_ODT_RD_CONFIG0_P3 = 0x8000C40E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_SEQ_ODT_RD_CONFIG0_P3 = 0x8000C40E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_SEQ_ODT_RD_CONFIG1_P0 = 0x8000C40F0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_SEQ_ODT_RD_CONFIG1_P0 = 0x8000C40F0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_SEQ_ODT_RD_CONFIG1_P0 = 0x8000C40F0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_SEQ_ODT_RD_CONFIG1_P1 = 0x8000C40F0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_SEQ_ODT_RD_CONFIG1_P1 = 0x8000C40F0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_SEQ_ODT_RD_CONFIG1_P2 = 0x8000C40F0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_SEQ_ODT_RD_CONFIG1_P2 = 0x8000C40F0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_SEQ_ODT_RD_CONFIG1_P3 = 0x8000C40F07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_SEQ_ODT_RD_CONFIG1_P3 = 0x8000C40F08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_SEQ_ODT_WR_CONFIG0_P0 = 0x8000C40A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_SEQ_ODT_WR_CONFIG0_P0 = 0x8000C40A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_SEQ_ODT_WR_CONFIG0_P0 = 0x8000C40A0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_SEQ_ODT_WR_CONFIG0_P1 = 0x8000C40A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_SEQ_ODT_WR_CONFIG0_P1 = 0x8000C40A0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_SEQ_ODT_WR_CONFIG0_P2 = 0x8000C40A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_SEQ_ODT_WR_CONFIG0_P2 = 0x8000C40A0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_SEQ_ODT_WR_CONFIG0_P3 = 0x8000C40A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_SEQ_ODT_WR_CONFIG0_P3 = 0x8000C40A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_SEQ_ODT_WR_CONFIG1_P0 = 0x8000C40B0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_SEQ_ODT_WR_CONFIG1_P0 = 0x8000C40B0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_SEQ_ODT_WR_CONFIG1_P0 = 0x8000C40B0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_SEQ_ODT_WR_CONFIG1_P1 = 0x8000C40B0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_SEQ_ODT_WR_CONFIG1_P1 = 0x8000C40B0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_SEQ_ODT_WR_CONFIG1_P2 = 0x8000C40B0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_SEQ_ODT_WR_CONFIG1_P2 = 0x8000C40B0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_SEQ_ODT_WR_CONFIG1_P3 = 0x8000C40B07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_SEQ_ODT_WR_CONFIG1_P3 = 0x8000C40B08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_SEQ_RD_WR_DATA0_P0 = 0x8000C4000701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_SEQ_RD_WR_DATA0_P0 = 0x8000C4000701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_SEQ_RD_WR_DATA0_P0 = 0x8000C4000801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_SEQ_RD_WR_DATA0_P1 = 0x8000C4000701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_SEQ_RD_WR_DATA0_P1 = 0x8000C4000801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_SEQ_RD_WR_DATA0_P2 = 0x8000C4000701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_SEQ_RD_WR_DATA0_P2 = 0x8000C4000801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_SEQ_RD_WR_DATA0_P3 = 0x8000C40007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_SEQ_RD_WR_DATA0_P3 = 0x8000C40008011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_SEQ_RD_WR_DATA1_P0 = 0x8000C4010701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_SEQ_RD_WR_DATA1_P0 = 0x8000C4010701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_SEQ_RD_WR_DATA1_P0 = 0x8000C4010801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_SEQ_RD_WR_DATA1_P1 = 0x8000C4010701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_SEQ_RD_WR_DATA1_P1 = 0x8000C4010801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_SEQ_RD_WR_DATA1_P2 = 0x8000C4010701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_SEQ_RD_WR_DATA1_P2 = 0x8000C4010801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_SEQ_RD_WR_DATA1_P3 = 0x8000C40107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_SEQ_RD_WR_DATA1_P3 = 0x8000C40108011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_SEQ_RESERVED_ADDR0_P0 = 0x8000C4030701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_SEQ_RESERVED_ADDR0_P0 = 0x8000C4030701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_SEQ_RESERVED_ADDR0_P0 = 0x8000C4030801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_SEQ_RESERVED_ADDR0_P1 = 0x8000C4030701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_SEQ_RESERVED_ADDR0_P1 = 0x8000C4030801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_SEQ_RESERVED_ADDR0_P2 = 0x8000C4030701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_SEQ_RESERVED_ADDR0_P2 = 0x8000C4030801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_SEQ_RESERVED_ADDR0_P3 = 0x8000C40307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_SEQ_RESERVED_ADDR0_P3 = 0x8000C40308011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_SEQ_RESERVED_ADDR1_P0 = 0x8000C4040701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_SEQ_RESERVED_ADDR1_P0 = 0x8000C4040701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_SEQ_RESERVED_ADDR1_P0 = 0x8000C4040801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_SEQ_RESERVED_ADDR1_P1 = 0x8000C4040701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_SEQ_RESERVED_ADDR1_P1 = 0x8000C4040801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_SEQ_RESERVED_ADDR1_P2 = 0x8000C4040701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_SEQ_RESERVED_ADDR1_P2 = 0x8000C4040801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_SEQ_RESERVED_ADDR1_P3 = 0x8000C40407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_SEQ_RESERVED_ADDR1_P3 = 0x8000C40408011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_SEQ_RESERVED_ADDR2_P0 = 0x8000C4050701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_SEQ_RESERVED_ADDR2_P0 = 0x8000C4050701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_SEQ_RESERVED_ADDR2_P0 = 0x8000C4050801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_SEQ_RESERVED_ADDR2_P1 = 0x8000C4050701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_SEQ_RESERVED_ADDR2_P1 = 0x8000C4050801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_SEQ_RESERVED_ADDR2_P2 = 0x8000C4050701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_SEQ_RESERVED_ADDR2_P2 = 0x8000C4050801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_SEQ_RESERVED_ADDR2_P3 = 0x8000C40507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_SEQ_RESERVED_ADDR2_P3 = 0x8000C40508011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_SEQ_RESERVED_ADDR3_P0 = 0x8000C4060701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_SEQ_RESERVED_ADDR3_P0 = 0x8000C4060701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_SEQ_RESERVED_ADDR3_P0 = 0x8000C4060801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_SEQ_RESERVED_ADDR3_P1 = 0x8000C4060701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_SEQ_RESERVED_ADDR3_P1 = 0x8000C4060801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_SEQ_RESERVED_ADDR3_P2 = 0x8000C4060701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_SEQ_RESERVED_ADDR3_P2 = 0x8000C4060801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_SEQ_RESERVED_ADDR3_P3 = 0x8000C40607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_SEQ_RESERVED_ADDR3_P3 = 0x8000C40608011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_SEQ_RESERVED_ADDR4_P0 = 0x8000C4070701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_SEQ_RESERVED_ADDR4_P0 = 0x8000C4070701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_SEQ_RESERVED_ADDR4_P0 = 0x8000C4070801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_SEQ_RESERVED_ADDR4_P1 = 0x8000C4070701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_SEQ_RESERVED_ADDR4_P1 = 0x8000C4070801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_SEQ_RESERVED_ADDR4_P2 = 0x8000C4070701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_SEQ_RESERVED_ADDR4_P2 = 0x8000C4070801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_SEQ_RESERVED_ADDR4_P3 = 0x8000C40707011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_SEQ_RESERVED_ADDR4_P3 = 0x8000C40708011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_SEQ_WR_TERM_SWAP0_P0 = 0x8000C41D0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_SEQ_WR_TERM_SWAP0_P0 = 0x8000C41D0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_SEQ_WR_TERM_SWAP0_P0 = 0x8000C41D0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_SEQ_WR_TERM_SWAP0_P1 = 0x8000C41D0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_SEQ_WR_TERM_SWAP0_P1 = 0x8000C41D0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_SEQ_WR_TERM_SWAP0_P2 = 0x8000C41D0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_SEQ_WR_TERM_SWAP0_P2 = 0x8000C41D0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_SEQ_WR_TERM_SWAP0_P3 = 0x8000C41D07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_SEQ_WR_TERM_SWAP0_P3 = 0x8000C41D08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_SEQ_WR_TERM_SWAP1_P0 = 0x8000C41E0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_SEQ_WR_TERM_SWAP1_P0 = 0x8000C41E0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_SEQ_WR_TERM_SWAP1_P0 = 0x8000C41E0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_SEQ_WR_TERM_SWAP1_P1 = 0x8000C41E0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_SEQ_WR_TERM_SWAP1_P1 = 0x8000C41E0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_SEQ_WR_TERM_SWAP1_P2 = 0x8000C41E0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_SEQ_WR_TERM_SWAP1_P2 = 0x8000C41E0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_SEQ_WR_TERM_SWAP1_P3 = 0x8000C41E07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_SEQ_WR_TERM_SWAP1_P3 = 0x8000C41E08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG0_P0 = 0x8000C41A0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG0_P0 = 0x8000C41A0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG0_P0 = 0x8000C41A0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG0_P1 = 0x8000C41A0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG0_P1 = 0x8000C41A0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG0_P2 = 0x8000C41A0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG0_P2 = 0x8000C41A0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG0_P3 = 0x8000C41A07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG0_P3 = 0x8000C41A08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG1_P0 = 0x8000C41B0701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG1_P0 = 0x8000C41B0701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG1_P0 = 0x8000C41B0801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG1_P1 = 0x8000C41B0701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG1_P1 = 0x8000C41B0801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG1_P2 = 0x8000C41B0701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG1_P2 = 0x8000C41B0801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG1_P3 = 0x8000C41B07011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG1_P3 = 0x8000C41B08011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_WC_CONFIG0_P0 = 0x8000CC000701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_WC_CONFIG0_P0 = 0x8000CC000701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_WC_CONFIG0_P0 = 0x8000CC000801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_WC_CONFIG0_P1 = 0x8000CC000701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_WC_CONFIG0_P1 = 0x8000CC000801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_WC_CONFIG0_P2 = 0x8000CC000701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_WC_CONFIG0_P2 = 0x8000CC000801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_WC_CONFIG0_P3 = 0x8000CC0007011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_WC_CONFIG0_P3 = 0x8000CC0008011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_WC_CONFIG1_P0 = 0x8000CC010701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_WC_CONFIG1_P0 = 0x8000CC010701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_WC_CONFIG1_P0 = 0x8000CC010801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_WC_CONFIG1_P1 = 0x8000CC010701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_WC_CONFIG1_P1 = 0x8000CC010801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_WC_CONFIG1_P2 = 0x8000CC010701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_WC_CONFIG1_P2 = 0x8000CC010801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_WC_CONFIG1_P3 = 0x8000CC0107011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_WC_CONFIG1_P3 = 0x8000CC0108011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_WC_CONFIG2_P0 = 0x8000CC020701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_WC_CONFIG2_P0 = 0x8000CC020701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_WC_CONFIG2_P0 = 0x8000CC020801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_WC_CONFIG2_P1 = 0x8000CC020701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_WC_CONFIG2_P1 = 0x8000CC020801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_WC_CONFIG2_P2 = 0x8000CC020701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_WC_CONFIG2_P2 = 0x8000CC020801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_WC_CONFIG2_P3 = 0x8000CC0207011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_WC_CONFIG2_P3 = 0x8000CC0208011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_WC_CONFIG3_P0 = 0x8000CC050701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_WC_CONFIG3_P0 = 0x8000CC050701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_WC_CONFIG3_P0 = 0x8000CC050801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_WC_CONFIG3_P1 = 0x8000CC050701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_WC_CONFIG3_P1 = 0x8000CC050801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_WC_CONFIG3_P2 = 0x8000CC050701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_WC_CONFIG3_P2 = 0x8000CC050801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_WC_CONFIG3_P3 = 0x8000CC0507011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_WC_CONFIG3_P3 = 0x8000CC0508011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_WC_ERROR_MASK0_P0 = 0x8000CC040701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_WC_ERROR_MASK0_P0 = 0x8000CC040701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_WC_ERROR_MASK0_P0 = 0x8000CC040801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_WC_ERROR_MASK0_P1 = 0x8000CC040701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_WC_ERROR_MASK0_P1 = 0x8000CC040801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_WC_ERROR_MASK0_P2 = 0x8000CC040701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_WC_ERROR_MASK0_P2 = 0x8000CC040801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_WC_ERROR_MASK0_P3 = 0x8000CC0407011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_WC_ERROR_MASK0_P3 = 0x8000CC0408011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_WC_ERROR_STATUS0_P0 = 0x8000CC030701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_WC_ERROR_STATUS0_P0 = 0x8000CC030701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_WC_ERROR_STATUS0_P0 = 0x8000CC030801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_WC_ERROR_STATUS0_P1 = 0x8000CC030701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_WC_ERROR_STATUS0_P1 = 0x8000CC030801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_WC_ERROR_STATUS0_P2 = 0x8000CC030701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_WC_ERROR_STATUS0_P2 = 0x8000CC030801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_WC_ERROR_STATUS0_P3 = 0x8000CC0307011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_WC_ERROR_STATUS0_P3 = 0x8000CC0308011C3Full;
+
+
+static const uint64_t P9N2_MCA_DDRPHY_WC_RTT_WR_SWAP_ENABLE_P0 = 0x8000CC060701103Full;
+
+static const uint64_t P9N2_MCA_0_DDRPHY_WC_RTT_WR_SWAP_ENABLE_P0 = 0x8000CC060701103Full;
+
+static const uint64_t P9N2_MCA_4_DDRPHY_WC_RTT_WR_SWAP_ENABLE_P0 = 0x8000CC060801103Full;
+
+
+static const uint64_t P9N2_MCA_1_DDRPHY_WC_RTT_WR_SWAP_ENABLE_P1 = 0x8000CC060701143Full;
+
+static const uint64_t P9N2_MCA_5_DDRPHY_WC_RTT_WR_SWAP_ENABLE_P1 = 0x8000CC060801143Full;
+
+
+static const uint64_t P9N2_MCA_2_DDRPHY_WC_RTT_WR_SWAP_ENABLE_P2 = 0x8000CC060701183Full;
+
+static const uint64_t P9N2_MCA_6_DDRPHY_WC_RTT_WR_SWAP_ENABLE_P2 = 0x8000CC060801183Full;
+
+
+static const uint64_t P9N2_MCA_3_DDRPHY_WC_RTT_WR_SWAP_ENABLE_P3 = 0x8000CC0607011C3Full;
+
+static const uint64_t P9N2_MCA_7_DDRPHY_WC_RTT_WR_SWAP_ENABLE_P3 = 0x8000CC0608011C3Full;
+
+
+static const uint64_t P9N2_MCA_3_DEBUG_TRACE_CONTROL = 0x070107D0ull;
+
+static const uint64_t P9N2_MCA_7_DEBUG_TRACE_CONTROL = 0x080107D0ull;
+
+
+static const uint64_t P9N2_MCA_DQS0R = 0x07010A3Cull;
+
+static const uint64_t P9N2_MCA_0_DQS0R = 0x07010A3Cull;
+
+static const uint64_t P9N2_MCA_1_DQS0R = 0x07010A7Cull;
+
+static const uint64_t P9N2_MCA_2_DQS0R = 0x07010ABCull;
+
+static const uint64_t P9N2_MCA_3_DQS0R = 0x07010AFCull;
+
+static const uint64_t P9N2_MCA_4_DQS0R = 0x08010A3Cull;
+
+static const uint64_t P9N2_MCA_5_DQS0R = 0x08010A7Cull;
+
+static const uint64_t P9N2_MCA_6_DQS0R = 0x08010ABCull;
+
+static const uint64_t P9N2_MCA_7_DQS0R = 0x08010AFCull;
+
+
+static const uint64_t P9N2_MCA_DQS1R = 0x07010A3Dull;
+
+static const uint64_t P9N2_MCA_0_DQS1R = 0x07010A3Dull;
+
+static const uint64_t P9N2_MCA_1_DQS1R = 0x07010A7Dull;
+
+static const uint64_t P9N2_MCA_2_DQS1R = 0x07010ABDull;
+
+static const uint64_t P9N2_MCA_3_DQS1R = 0x07010AFDull;
+
+static const uint64_t P9N2_MCA_4_DQS1R = 0x08010A3Dull;
+
+static const uint64_t P9N2_MCA_5_DQS1R = 0x08010A7Dull;
+
+static const uint64_t P9N2_MCA_6_DQS1R = 0x08010ABDull;
+
+static const uint64_t P9N2_MCA_7_DQS1R = 0x08010AFDull;
+
+
+static const uint64_t P9N2_MCA_EICR = 0x07010A0Dull;
+
+static const uint64_t P9N2_MCA_0_EICR = 0x07010A0Dull;
+
+static const uint64_t P9N2_MCA_1_EICR = 0x07010A4Dull;
+
+static const uint64_t P9N2_MCA_2_EICR = 0x07010A8Dull;
+
+static const uint64_t P9N2_MCA_3_EICR = 0x07010ACDull;
+
+static const uint64_t P9N2_MCA_4_EICR = 0x08010A0Dull;
+
+static const uint64_t P9N2_MCA_5_EICR = 0x08010A4Dull;
+
+static const uint64_t P9N2_MCA_6_EICR = 0x08010A8Dull;
+
+static const uint64_t P9N2_MCA_7_EICR = 0x08010ACDull;
+
+
+static const uint64_t P9N2_MCA_ELPR = 0x07010A2Full;
+
+static const uint64_t P9N2_MCA_0_ELPR = 0x07010A2Full;
+
+static const uint64_t P9N2_MCA_1_ELPR = 0x07010A6Full;
+
+static const uint64_t P9N2_MCA_2_ELPR = 0x07010AAFull;
+
+static const uint64_t P9N2_MCA_3_ELPR = 0x07010AEFull;
+
+static const uint64_t P9N2_MCA_4_ELPR = 0x08010A2Full;
+
+static const uint64_t P9N2_MCA_5_ELPR = 0x08010A6Full;
+
+static const uint64_t P9N2_MCA_6_ELPR = 0x08010AAFull;
+
+static const uint64_t P9N2_MCA_7_ELPR = 0x08010AEFull;
+
+
+static const uint64_t P9N2_MCA_FIR = 0x07010A00ull;
+
+static const uint64_t P9N2_MCA_FIR_OR = 0x07010A02ull;
+
+static const uint64_t P9N2_MCA_0_FIR = 0x07010A00ull;
+
+static const uint64_t P9N2_MCA_0_FIR_OR = 0x07010A02ull;
+
+static const uint64_t P9N2_MCA_0_WDF_FIR = 0x07010A01ull;
+
+static const uint64_t P9N2_MCA_1_FIR = 0x07010A40ull;
+
+static const uint64_t P9N2_MCA_1_FIR_OR = 0x07010A42ull;
+
+static const uint64_t P9N2_MCA_1_WDF_FIR = 0x07010A41ull;
+
+static const uint64_t P9N2_MCA_2_FIR = 0x07010A80ull;
+
+static const uint64_t P9N2_MCA_2_FIR_OR = 0x07010A82ull;
+
+static const uint64_t P9N2_MCA_2_WDF_FIR = 0x07010A81ull;
+
+static const uint64_t P9N2_MCA_3_FIR = 0x07010AC0ull;
+
+static const uint64_t P9N2_MCA_3_FIR_OR = 0x07010AC2ull;
+
+static const uint64_t P9N2_MCA_3_WDF_FIR = 0x07010AC1ull;
+
+static const uint64_t P9N2_MCA_4_WDF_FIR = 0x08010A01ull;
+
+static const uint64_t P9N2_MCA_4_FIR = 0x08010A00ull;
+
+static const uint64_t P9N2_MCA_4_FIR_OR = 0x08010A02ull;
+
+static const uint64_t P9N2_MCA_5_FIR = 0x08010A40ull;
+
+static const uint64_t P9N2_MCA_5_FIR_OR = 0x08010A42ull;
+
+static const uint64_t P9N2_MCA_5_WDF_FIR = 0x08010A41ull;
+
+static const uint64_t P9N2_MCA_6_WDF_FIR = 0x08010A81ull;
+
+static const uint64_t P9N2_MCA_6_FIR = 0x08010A80ull;
+
+static const uint64_t P9N2_MCA_6_FIR_OR = 0x08010A82ull;
+
+static const uint64_t P9N2_MCA_7_WDF_FIR = 0x08010AC1ull;
+
+static const uint64_t P9N2_MCA_7_FIR = 0x08010AC0ull;
+
+static const uint64_t P9N2_MCA_7_FIR_OR = 0x08010AC2ull;
+
+static const uint64_t P9N2_MCA_WDF_FIR = 0x07010A01ull;
+
+
+static const uint64_t P9N2_MCA_FWMS0 = 0x07010A18ull;
+
+static const uint64_t P9N2_MCA_0_FWMS0 = 0x07010A18ull;
+
+static const uint64_t P9N2_MCA_1_FWMS0 = 0x07010A58ull;
+
+static const uint64_t P9N2_MCA_2_FWMS0 = 0x07010A98ull;
+
+static const uint64_t P9N2_MCA_3_FWMS0 = 0x07010AD8ull;
+
+static const uint64_t P9N2_MCA_4_FWMS0 = 0x08010A18ull;
+
+static const uint64_t P9N2_MCA_5_FWMS0 = 0x08010A58ull;
+
+static const uint64_t P9N2_MCA_6_FWMS0 = 0x08010A98ull;
+
+static const uint64_t P9N2_MCA_7_FWMS0 = 0x08010AD8ull;
+
+
+static const uint64_t P9N2_MCA_0_WREITE_FWMS1 = 0x07010A19ull;
+
+static const uint64_t P9N2_MCA_1_WREITE_FWMS1 = 0x07010A59ull;
+
+static const uint64_t P9N2_MCA_2_WREITE_FWMS1 = 0x07010A99ull;
+
+static const uint64_t P9N2_MCA_3_WREITE_FWMS1 = 0x07010AD9ull;
+
+static const uint64_t P9N2_MCA_4_WREITE_FWMS1 = 0x08010A19ull;
+
+static const uint64_t P9N2_MCA_5_WREITE_FWMS1 = 0x08010A59ull;
+
+static const uint64_t P9N2_MCA_6_WREITE_FWMS1 = 0x08010A99ull;
+
+static const uint64_t P9N2_MCA_7_WREITE_FWMS1 = 0x08010AD9ull;
+
+static const uint64_t P9N2_MCA_WREITE_FWMS1 = 0x07010A19ull;
+
+
+static const uint64_t P9N2_MCA_FWMS2 = 0x07010A1Aull;
+
+static const uint64_t P9N2_MCA_0_FWMS2 = 0x07010A1Aull;
+
+static const uint64_t P9N2_MCA_1_FWMS2 = 0x07010A5Aull;
+
+static const uint64_t P9N2_MCA_2_FWMS2 = 0x07010A9Aull;
+
+static const uint64_t P9N2_MCA_3_FWMS2 = 0x07010ADAull;
+
+static const uint64_t P9N2_MCA_4_FWMS2 = 0x08010A1Aull;
+
+static const uint64_t P9N2_MCA_5_FWMS2 = 0x08010A5Aull;
+
+static const uint64_t P9N2_MCA_6_FWMS2 = 0x08010A9Aull;
+
+static const uint64_t P9N2_MCA_7_FWMS2 = 0x08010ADAull;
+
+
+static const uint64_t P9N2_MCA_FWMS3 = 0x07010A1Bull;
+
+static const uint64_t P9N2_MCA_0_FWMS3 = 0x07010A1Bull;
+
+static const uint64_t P9N2_MCA_1_FWMS3 = 0x07010A5Bull;
+
+static const uint64_t P9N2_MCA_2_FWMS3 = 0x07010A9Bull;
+
+static const uint64_t P9N2_MCA_3_FWMS3 = 0x07010ADBull;
+
+static const uint64_t P9N2_MCA_4_FWMS3 = 0x08010A1Bull;
+
+static const uint64_t P9N2_MCA_5_FWMS3 = 0x08010A5Bull;
+
+static const uint64_t P9N2_MCA_6_FWMS3 = 0x08010A9Bull;
+
+static const uint64_t P9N2_MCA_7_FWMS3 = 0x08010ADBull;
+
+
+static const uint64_t P9N2_MCA_FWMS4 = 0x07010A1Cull;
+
+static const uint64_t P9N2_MCA_0_FWMS4 = 0x07010A1Cull;
+
+static const uint64_t P9N2_MCA_1_FWMS4 = 0x07010A5Cull;
+
+static const uint64_t P9N2_MCA_2_FWMS4 = 0x07010A9Cull;
+
+static const uint64_t P9N2_MCA_3_FWMS4 = 0x07010ADCull;
+
+static const uint64_t P9N2_MCA_4_FWMS4 = 0x08010A1Cull;
+
+static const uint64_t P9N2_MCA_5_FWMS4 = 0x08010A5Cull;
+
+static const uint64_t P9N2_MCA_6_FWMS4 = 0x08010A9Cull;
+
+static const uint64_t P9N2_MCA_7_FWMS4 = 0x08010ADCull;
+
+
+static const uint64_t P9N2_MCA_FWMS5 = 0x07010A1Dull;
+
+static const uint64_t P9N2_MCA_0_FWMS5 = 0x07010A1Dull;
+
+static const uint64_t P9N2_MCA_1_FWMS5 = 0x07010A5Dull;
+
+static const uint64_t P9N2_MCA_2_FWMS5 = 0x07010A9Dull;
+
+static const uint64_t P9N2_MCA_3_FWMS5 = 0x07010ADDull;
+
+static const uint64_t P9N2_MCA_4_FWMS5 = 0x08010A1Dull;
+
+static const uint64_t P9N2_MCA_5_FWMS5 = 0x08010A5Dull;
+
+static const uint64_t P9N2_MCA_6_FWMS5 = 0x08010A9Dull;
+
+static const uint64_t P9N2_MCA_7_FWMS5 = 0x08010ADDull;
+
+
+static const uint64_t P9N2_MCA_FWMS6 = 0x07010A1Eull;
+
+static const uint64_t P9N2_MCA_0_FWMS6 = 0x07010A1Eull;
+
+static const uint64_t P9N2_MCA_1_FWMS6 = 0x07010A5Eull;
+
+static const uint64_t P9N2_MCA_2_FWMS6 = 0x07010A9Eull;
+
+static const uint64_t P9N2_MCA_3_FWMS6 = 0x07010ADEull;
+
+static const uint64_t P9N2_MCA_4_FWMS6 = 0x08010A1Eull;
+
+static const uint64_t P9N2_MCA_5_FWMS6 = 0x08010A5Eull;
+
+static const uint64_t P9N2_MCA_6_FWMS6 = 0x08010A9Eull;
+
+static const uint64_t P9N2_MCA_7_FWMS6 = 0x08010ADEull;
+
+
+static const uint64_t P9N2_MCA_FWMS7 = 0x07010A1Full;
+
+static const uint64_t P9N2_MCA_0_FWMS7 = 0x07010A1Full;
+
+static const uint64_t P9N2_MCA_1_FWMS7 = 0x07010A5Full;
+
+static const uint64_t P9N2_MCA_2_FWMS7 = 0x07010A9Full;
+
+static const uint64_t P9N2_MCA_3_FWMS7 = 0x07010ADFull;
+
+static const uint64_t P9N2_MCA_4_FWMS7 = 0x08010A1Full;
+
+static const uint64_t P9N2_MCA_5_FWMS7 = 0x08010A5Full;
+
+static const uint64_t P9N2_MCA_6_FWMS7 = 0x08010A9Full;
+
+static const uint64_t P9N2_MCA_7_FWMS7 = 0x08010ADFull;
+
+
+static const uint64_t P9N2_MCA_HWMS0 = 0x07010A10ull;
+
+static const uint64_t P9N2_MCA_0_HWMS0 = 0x07010A10ull;
+
+static const uint64_t P9N2_MCA_1_HWMS0 = 0x07010A50ull;
+
+static const uint64_t P9N2_MCA_2_HWMS0 = 0x07010A90ull;
+
+static const uint64_t P9N2_MCA_3_HWMS0 = 0x07010AD0ull;
+
+static const uint64_t P9N2_MCA_4_HWMS0 = 0x08010A10ull;
+
+static const uint64_t P9N2_MCA_5_HWMS0 = 0x08010A50ull;
+
+static const uint64_t P9N2_MCA_6_HWMS0 = 0x08010A90ull;
+
+static const uint64_t P9N2_MCA_7_HWMS0 = 0x08010AD0ull;
+
+
+static const uint64_t P9N2_MCA_0_WDF_HWMS1 = 0x07010A11ull;
+
+static const uint64_t P9N2_MCA_1_WDF_HWMS1 = 0x07010A51ull;
+
+static const uint64_t P9N2_MCA_2_WDF_HWMS1 = 0x07010A91ull;
+
+static const uint64_t P9N2_MCA_3_WDF_HWMS1 = 0x07010AD1ull;
+
+static const uint64_t P9N2_MCA_4_WDF_HWMS1 = 0x08010A11ull;
+
+static const uint64_t P9N2_MCA_5_WDF_HWMS1 = 0x08010A51ull;
+
+static const uint64_t P9N2_MCA_6_WDF_HWMS1 = 0x08010A91ull;
+
+static const uint64_t P9N2_MCA_7_WDF_HWMS1 = 0x08010AD1ull;
+
+static const uint64_t P9N2_MCA_WDF_HWMS1 = 0x07010A11ull;
+
+
+static const uint64_t P9N2_MCA_HWMS2 = 0x07010A12ull;
+
+static const uint64_t P9N2_MCA_0_HWMS2 = 0x07010A12ull;
+
+static const uint64_t P9N2_MCA_1_HWMS2 = 0x07010A52ull;
+
+static const uint64_t P9N2_MCA_2_HWMS2 = 0x07010A92ull;
+
+static const uint64_t P9N2_MCA_3_HWMS2 = 0x07010AD2ull;
+
+static const uint64_t P9N2_MCA_4_HWMS2 = 0x08010A12ull;
+
+static const uint64_t P9N2_MCA_5_HWMS2 = 0x08010A52ull;
+
+static const uint64_t P9N2_MCA_6_HWMS2 = 0x08010A92ull;
+
+static const uint64_t P9N2_MCA_7_HWMS2 = 0x08010AD2ull;
+
+
+static const uint64_t P9N2_MCA_HWMS3 = 0x07010A13ull;
+
+static const uint64_t P9N2_MCA_0_HWMS3 = 0x07010A13ull;
+
+static const uint64_t P9N2_MCA_1_HWMS3 = 0x07010A53ull;
+
+static const uint64_t P9N2_MCA_2_HWMS3 = 0x07010A93ull;
+
+static const uint64_t P9N2_MCA_3_HWMS3 = 0x07010AD3ull;
+
+static const uint64_t P9N2_MCA_4_HWMS3 = 0x08010A13ull;
+
+static const uint64_t P9N2_MCA_5_HWMS3 = 0x08010A53ull;
+
+static const uint64_t P9N2_MCA_6_HWMS3 = 0x08010A93ull;
+
+static const uint64_t P9N2_MCA_7_HWMS3 = 0x08010AD3ull;
+
+
+static const uint64_t P9N2_MCA_HWMS4 = 0x07010A14ull;
+
+static const uint64_t P9N2_MCA_0_HWMS4 = 0x07010A14ull;
+
+static const uint64_t P9N2_MCA_1_HWMS4 = 0x07010A54ull;
+
+static const uint64_t P9N2_MCA_2_HWMS4 = 0x07010A94ull;
+
+static const uint64_t P9N2_MCA_3_HWMS4 = 0x07010AD4ull;
+
+static const uint64_t P9N2_MCA_4_HWMS4 = 0x08010A14ull;
+
+static const uint64_t P9N2_MCA_5_HWMS4 = 0x08010A54ull;
+
+static const uint64_t P9N2_MCA_6_HWMS4 = 0x08010A94ull;
+
+static const uint64_t P9N2_MCA_7_HWMS4 = 0x08010AD4ull;
+
+
+static const uint64_t P9N2_MCA_HWMS5 = 0x07010A15ull;
+
+static const uint64_t P9N2_MCA_0_HWMS5 = 0x07010A15ull;
+
+static const uint64_t P9N2_MCA_1_HWMS5 = 0x07010A55ull;
+
+static const uint64_t P9N2_MCA_2_HWMS5 = 0x07010A95ull;
+
+static const uint64_t P9N2_MCA_3_HWMS5 = 0x07010AD5ull;
+
+static const uint64_t P9N2_MCA_4_HWMS5 = 0x08010A15ull;
+
+static const uint64_t P9N2_MCA_5_HWMS5 = 0x08010A55ull;
+
+static const uint64_t P9N2_MCA_6_HWMS5 = 0x08010A95ull;
+
+static const uint64_t P9N2_MCA_7_HWMS5 = 0x08010AD5ull;
+
+
+static const uint64_t P9N2_MCA_HWMS6 = 0x07010A16ull;
+
+static const uint64_t P9N2_MCA_0_HWMS6 = 0x07010A16ull;
+
+static const uint64_t P9N2_MCA_1_HWMS6 = 0x07010A56ull;
+
+static const uint64_t P9N2_MCA_2_HWMS6 = 0x07010A96ull;
+
+static const uint64_t P9N2_MCA_3_HWMS6 = 0x07010AD6ull;
+
+static const uint64_t P9N2_MCA_4_HWMS6 = 0x08010A16ull;
+
+static const uint64_t P9N2_MCA_5_HWMS6 = 0x08010A56ull;
+
+static const uint64_t P9N2_MCA_6_HWMS6 = 0x08010A96ull;
+
+static const uint64_t P9N2_MCA_7_HWMS6 = 0x08010AD6ull;
+
+
+static const uint64_t P9N2_MCA_HWMS7 = 0x07010A17ull;
+
+static const uint64_t P9N2_MCA_0_HWMS7 = 0x07010A17ull;
+
+static const uint64_t P9N2_MCA_1_HWMS7 = 0x07010A57ull;
+
+static const uint64_t P9N2_MCA_2_HWMS7 = 0x07010A97ull;
+
+static const uint64_t P9N2_MCA_3_HWMS7 = 0x07010AD7ull;
+
+static const uint64_t P9N2_MCA_4_HWMS7 = 0x08010A17ull;
+
+static const uint64_t P9N2_MCA_5_HWMS7 = 0x08010A57ull;
+
+static const uint64_t P9N2_MCA_6_HWMS7 = 0x08010A97ull;
+
+static const uint64_t P9N2_MCA_7_HWMS7 = 0x08010AD7ull;
+
+
+static const uint64_t P9N2_MCA_IOM_PHY0_DDRPHY_FIR_ACTION0_REG = 0x07011006ull;
+
+static const uint64_t P9N2_MCA_0_IOM_PHY0_DDRPHY_FIR_ACTION0_REG = 0x07011006ull;
+
+static const uint64_t P9N2_MCA_4_IOM_PHY0_DDRPHY_FIR_ACTION0_REG = 0x08011006ull;
+
+
+static const uint64_t P9N2_MCA_IOM_PHY0_DDRPHY_FIR_ACTION1_REG = 0x07011007ull;
+
+static const uint64_t P9N2_MCA_0_IOM_PHY0_DDRPHY_FIR_ACTION1_REG = 0x07011007ull;
+
+static const uint64_t P9N2_MCA_4_IOM_PHY0_DDRPHY_FIR_ACTION1_REG = 0x08011007ull;
+
+
+static const uint64_t P9N2_MCA_IOM_PHY0_DDRPHY_FIR_MASK_REG = 0x07011003ull;
+
+static const uint64_t P9N2_MCA_IOM_PHY0_DDRPHY_FIR_MASK_REG_AND = 0x07011004ull;
+
+static const uint64_t P9N2_MCA_IOM_PHY0_DDRPHY_FIR_MASK_REG_OR = 0x07011005ull;
+
+static const uint64_t P9N2_MCA_0_IOM_PHY0_DDRPHY_FIR_MASK_REG = 0x07011003ull;
+
+static const uint64_t P9N2_MCA_0_IOM_PHY0_DDRPHY_FIR_MASK_REG_AND = 0x07011004ull;
+
+static const uint64_t P9N2_MCA_0_IOM_PHY0_DDRPHY_FIR_MASK_REG_OR = 0x07011005ull;
+
+static const uint64_t P9N2_MCA_4_IOM_PHY0_DDRPHY_FIR_MASK_REG = 0x08011003ull;
+
+static const uint64_t P9N2_MCA_4_IOM_PHY0_DDRPHY_FIR_MASK_REG_AND = 0x08011004ull;
+
+static const uint64_t P9N2_MCA_4_IOM_PHY0_DDRPHY_FIR_MASK_REG_OR = 0x08011005ull;
+
+
+static const uint64_t P9N2_MCA_IOM_PHY0_DDRPHY_FIR_REG = 0x07011000ull;
+
+static const uint64_t P9N2_MCA_IOM_PHY0_DDRPHY_FIR_REG_AND = 0x07011001ull;
+
+static const uint64_t P9N2_MCA_IOM_PHY0_DDRPHY_FIR_REG_OR = 0x07011002ull;
+
+static const uint64_t P9N2_MCA_0_IOM_PHY0_DDRPHY_FIR_REG = 0x07011000ull;
+
+static const uint64_t P9N2_MCA_0_IOM_PHY0_DDRPHY_FIR_REG_AND = 0x07011001ull;
+
+static const uint64_t P9N2_MCA_0_IOM_PHY0_DDRPHY_FIR_REG_OR = 0x07011002ull;
+
+static const uint64_t P9N2_MCA_4_IOM_PHY0_DDRPHY_FIR_REG = 0x08011000ull;
+
+static const uint64_t P9N2_MCA_4_IOM_PHY0_DDRPHY_FIR_REG_AND = 0x08011001ull;
+
+static const uint64_t P9N2_MCA_4_IOM_PHY0_DDRPHY_FIR_REG_OR = 0x08011002ull;
+
+
+static const uint64_t P9N2_MCA_IOM_PHY0_DDRPHY_FIR_WOF_REG = 0x07011008ull;
+
+static const uint64_t P9N2_MCA_0_IOM_PHY0_DDRPHY_FIR_WOF_REG = 0x07011008ull;
+
+static const uint64_t P9N2_MCA_4_IOM_PHY0_DDRPHY_FIR_WOF_REG = 0x08011008ull;
+
+
+static const uint64_t P9N2_MCA_1_IOM_PHY1_DDRPHY_FIR_ACTION0_REG = 0x07011406ull;
+
+static const uint64_t P9N2_MCA_5_IOM_PHY1_DDRPHY_FIR_ACTION0_REG = 0x08011406ull;
+
+
+static const uint64_t P9N2_MCA_1_IOM_PHY1_DDRPHY_FIR_ACTION1_REG = 0x07011407ull;
+
+static const uint64_t P9N2_MCA_5_IOM_PHY1_DDRPHY_FIR_ACTION1_REG = 0x08011407ull;
+
+
+static const uint64_t P9N2_MCA_1_IOM_PHY1_DDRPHY_FIR_MASK_REG = 0x07011403ull;
+
+static const uint64_t P9N2_MCA_1_IOM_PHY1_DDRPHY_FIR_MASK_REG_AND = 0x07011404ull;
+
+static const uint64_t P9N2_MCA_1_IOM_PHY1_DDRPHY_FIR_MASK_REG_OR = 0x07011405ull;
+
+static const uint64_t P9N2_MCA_5_IOM_PHY1_DDRPHY_FIR_MASK_REG = 0x08011403ull;
+
+static const uint64_t P9N2_MCA_5_IOM_PHY1_DDRPHY_FIR_MASK_REG_AND = 0x08011404ull;
+
+static const uint64_t P9N2_MCA_5_IOM_PHY1_DDRPHY_FIR_MASK_REG_OR = 0x08011405ull;
+
+
+static const uint64_t P9N2_MCA_1_IOM_PHY1_DDRPHY_FIR_REG = 0x07011400ull;
+
+static const uint64_t P9N2_MCA_1_IOM_PHY1_DDRPHY_FIR_REG_AND = 0x07011401ull;
+
+static const uint64_t P9N2_MCA_1_IOM_PHY1_DDRPHY_FIR_REG_OR = 0x07011402ull;
+
+static const uint64_t P9N2_MCA_5_IOM_PHY1_DDRPHY_FIR_REG = 0x08011400ull;
+
+static const uint64_t P9N2_MCA_5_IOM_PHY1_DDRPHY_FIR_REG_AND = 0x08011401ull;
+
+static const uint64_t P9N2_MCA_5_IOM_PHY1_DDRPHY_FIR_REG_OR = 0x08011402ull;
+
+
+static const uint64_t P9N2_MCA_1_IOM_PHY1_DDRPHY_FIR_WOF_REG = 0x07011408ull;
+
+static const uint64_t P9N2_MCA_5_IOM_PHY1_DDRPHY_FIR_WOF_REG = 0x08011408ull;
+
+
+static const uint64_t P9N2_MCA_2_IOM_PHY2_DDRPHY_FIR_ACTION0_REG = 0x07011806ull;
+
+static const uint64_t P9N2_MCA_6_IOM_PHY2_DDRPHY_FIR_ACTION0_REG = 0x08011806ull;
+
+
+static const uint64_t P9N2_MCA_2_IOM_PHY2_DDRPHY_FIR_ACTION1_REG = 0x07011807ull;
+
+static const uint64_t P9N2_MCA_6_IOM_PHY2_DDRPHY_FIR_ACTION1_REG = 0x08011807ull;
+
+
+static const uint64_t P9N2_MCA_2_IOM_PHY2_DDRPHY_FIR_MASK_REG = 0x07011803ull;
+
+static const uint64_t P9N2_MCA_2_IOM_PHY2_DDRPHY_FIR_MASK_REG_AND = 0x07011804ull;
+
+static const uint64_t P9N2_MCA_2_IOM_PHY2_DDRPHY_FIR_MASK_REG_OR = 0x07011805ull;
+
+static const uint64_t P9N2_MCA_6_IOM_PHY2_DDRPHY_FIR_MASK_REG = 0x08011803ull;
+
+static const uint64_t P9N2_MCA_6_IOM_PHY2_DDRPHY_FIR_MASK_REG_AND = 0x08011804ull;
+
+static const uint64_t P9N2_MCA_6_IOM_PHY2_DDRPHY_FIR_MASK_REG_OR = 0x08011805ull;
+
+
+static const uint64_t P9N2_MCA_2_IOM_PHY2_DDRPHY_FIR_REG = 0x07011800ull;
+
+static const uint64_t P9N2_MCA_2_IOM_PHY2_DDRPHY_FIR_REG_AND = 0x07011801ull;
+
+static const uint64_t P9N2_MCA_2_IOM_PHY2_DDRPHY_FIR_REG_OR = 0x07011802ull;
+
+static const uint64_t P9N2_MCA_6_IOM_PHY2_DDRPHY_FIR_REG = 0x08011800ull;
+
+static const uint64_t P9N2_MCA_6_IOM_PHY2_DDRPHY_FIR_REG_AND = 0x08011801ull;
+
+static const uint64_t P9N2_MCA_6_IOM_PHY2_DDRPHY_FIR_REG_OR = 0x08011802ull;
+
+
+static const uint64_t P9N2_MCA_2_IOM_PHY2_DDRPHY_FIR_WOF_REG = 0x07011808ull;
+
+static const uint64_t P9N2_MCA_6_IOM_PHY2_DDRPHY_FIR_WOF_REG = 0x08011808ull;
+
+
+static const uint64_t P9N2_MCA_3_IOM_PHY3_DDRPHY_FIR_ACTION0_REG = 0x07011C06ull;
+
+static const uint64_t P9N2_MCA_7_IOM_PHY3_DDRPHY_FIR_ACTION0_REG = 0x08011C06ull;
+
+
+static const uint64_t P9N2_MCA_3_IOM_PHY3_DDRPHY_FIR_ACTION1_REG = 0x07011C07ull;
+
+static const uint64_t P9N2_MCA_7_IOM_PHY3_DDRPHY_FIR_ACTION1_REG = 0x08011C07ull;
+
+
+static const uint64_t P9N2_MCA_3_IOM_PHY3_DDRPHY_FIR_MASK_REG = 0x07011C03ull;
+
+static const uint64_t P9N2_MCA_3_IOM_PHY3_DDRPHY_FIR_MASK_REG_AND = 0x07011C04ull;
+
+static const uint64_t P9N2_MCA_3_IOM_PHY3_DDRPHY_FIR_MASK_REG_OR = 0x07011C05ull;
+
+static const uint64_t P9N2_MCA_7_IOM_PHY3_DDRPHY_FIR_MASK_REG = 0x08011C03ull;
+
+static const uint64_t P9N2_MCA_7_IOM_PHY3_DDRPHY_FIR_MASK_REG_AND = 0x08011C04ull;
+
+static const uint64_t P9N2_MCA_7_IOM_PHY3_DDRPHY_FIR_MASK_REG_OR = 0x08011C05ull;
+
+
+static const uint64_t P9N2_MCA_3_IOM_PHY3_DDRPHY_FIR_REG = 0x07011C00ull;
+
+static const uint64_t P9N2_MCA_3_IOM_PHY3_DDRPHY_FIR_REG_AND = 0x07011C01ull;
+
+static const uint64_t P9N2_MCA_3_IOM_PHY3_DDRPHY_FIR_REG_OR = 0x07011C02ull;
+
+static const uint64_t P9N2_MCA_7_IOM_PHY3_DDRPHY_FIR_REG = 0x08011C00ull;
+
+static const uint64_t P9N2_MCA_7_IOM_PHY3_DDRPHY_FIR_REG_AND = 0x08011C01ull;
+
+static const uint64_t P9N2_MCA_7_IOM_PHY3_DDRPHY_FIR_REG_OR = 0x08011C02ull;
+
+
+static const uint64_t P9N2_MCA_3_IOM_PHY3_DDRPHY_FIR_WOF_REG = 0x07011C08ull;
+
+static const uint64_t P9N2_MCA_7_IOM_PHY3_DDRPHY_FIR_WOF_REG = 0x08011C08ull;
+
+
+static const uint64_t P9N2_MCA_MASK = 0x07010A03ull;
+
+static const uint64_t P9N2_MCA_MASK_AND = 0x07010A04ull;
+
+static const uint64_t P9N2_MCA_MASK_OR = 0x07010A05ull;
+
+static const uint64_t P9N2_MCA_0_MASK = 0x07010A03ull;
+
+static const uint64_t P9N2_MCA_0_MASK_AND = 0x07010A04ull;
+
+static const uint64_t P9N2_MCA_0_MASK_OR = 0x07010A05ull;
+
+static const uint64_t P9N2_MCA_1_MASK = 0x07010A43ull;
+
+static const uint64_t P9N2_MCA_1_MASK_AND = 0x07010A44ull;
+
+static const uint64_t P9N2_MCA_1_MASK_OR = 0x07010A45ull;
+
+static const uint64_t P9N2_MCA_2_MASK = 0x07010A83ull;
+
+static const uint64_t P9N2_MCA_2_MASK_AND = 0x07010A84ull;
+
+static const uint64_t P9N2_MCA_2_MASK_OR = 0x07010A85ull;
+
+static const uint64_t P9N2_MCA_3_MASK = 0x07010AC3ull;
+
+static const uint64_t P9N2_MCA_3_MASK_AND = 0x07010AC4ull;
+
+static const uint64_t P9N2_MCA_3_MASK_OR = 0x07010AC5ull;
+
+static const uint64_t P9N2_MCA_4_MASK = 0x08010A03ull;
+
+static const uint64_t P9N2_MCA_4_MASK_AND = 0x08010A04ull;
+
+static const uint64_t P9N2_MCA_4_MASK_OR = 0x08010A05ull;
+
+static const uint64_t P9N2_MCA_5_MASK = 0x08010A43ull;
+
+static const uint64_t P9N2_MCA_5_MASK_AND = 0x08010A44ull;
+
+static const uint64_t P9N2_MCA_5_MASK_OR = 0x08010A45ull;
+
+static const uint64_t P9N2_MCA_6_MASK = 0x08010A83ull;
+
+static const uint64_t P9N2_MCA_6_MASK_AND = 0x08010A84ull;
+
+static const uint64_t P9N2_MCA_6_MASK_OR = 0x08010A85ull;
+
+static const uint64_t P9N2_MCA_7_MASK = 0x08010AC3ull;
+
+static const uint64_t P9N2_MCA_7_MASK_AND = 0x08010AC4ull;
+
+static const uint64_t P9N2_MCA_7_MASK_OR = 0x08010AC5ull;
+
+
+static const uint64_t P9N2_MCA_MBACALFIRQ = 0x07010900ull;
+
+static const uint64_t P9N2_MCA_MBACALFIRQ_AND = 0x07010901ull;
+
+static const uint64_t P9N2_MCA_MBACALFIRQ_OR = 0x07010902ull;
+
+static const uint64_t P9N2_MCA_0_MBACALFIRQ = 0x07010900ull;
+
+static const uint64_t P9N2_MCA_0_MBACALFIRQ_AND = 0x07010901ull;
+
+static const uint64_t P9N2_MCA_0_MBACALFIRQ_OR = 0x07010902ull;
+
+static const uint64_t P9N2_MCA_1_MBACALFIRQ = 0x07010940ull;
+
+static const uint64_t P9N2_MCA_1_MBACALFIRQ_AND = 0x07010941ull;
+
+static const uint64_t P9N2_MCA_1_MBACALFIRQ_OR = 0x07010942ull;
+
+static const uint64_t P9N2_MCA_2_MBACALFIRQ = 0x07010980ull;
+
+static const uint64_t P9N2_MCA_2_MBACALFIRQ_AND = 0x07010981ull;
+
+static const uint64_t P9N2_MCA_2_MBACALFIRQ_OR = 0x07010982ull;
+
+static const uint64_t P9N2_MCA_3_MBACALFIRQ = 0x070109C0ull;
+
+static const uint64_t P9N2_MCA_3_MBACALFIRQ_AND = 0x070109C1ull;
+
+static const uint64_t P9N2_MCA_3_MBACALFIRQ_OR = 0x070109C2ull;
+
+static const uint64_t P9N2_MCA_4_MBACALFIRQ = 0x08010900ull;
+
+static const uint64_t P9N2_MCA_4_MBACALFIRQ_AND = 0x08010901ull;
+
+static const uint64_t P9N2_MCA_4_MBACALFIRQ_OR = 0x08010902ull;
+
+static const uint64_t P9N2_MCA_5_MBACALFIRQ = 0x08010940ull;
+
+static const uint64_t P9N2_MCA_5_MBACALFIRQ_AND = 0x08010941ull;
+
+static const uint64_t P9N2_MCA_5_MBACALFIRQ_OR = 0x08010942ull;
+
+static const uint64_t P9N2_MCA_6_MBACALFIRQ = 0x08010980ull;
+
+static const uint64_t P9N2_MCA_6_MBACALFIRQ_AND = 0x08010981ull;
+
+static const uint64_t P9N2_MCA_6_MBACALFIRQ_OR = 0x08010982ull;
+
+static const uint64_t P9N2_MCA_7_MBACALFIRQ = 0x080109C0ull;
+
+static const uint64_t P9N2_MCA_7_MBACALFIRQ_AND = 0x080109C1ull;
+
+static const uint64_t P9N2_MCA_7_MBACALFIRQ_OR = 0x080109C2ull;
+
+
+static const uint64_t P9N2_MCA_MBACALFIR_ACTION0 = 0x07010906ull;
+
+static const uint64_t P9N2_MCA_0_MBACALFIR_ACTION0 = 0x07010906ull;
+
+static const uint64_t P9N2_MCA_1_MBACALFIR_ACTION0 = 0x07010946ull;
+
+static const uint64_t P9N2_MCA_2_MBACALFIR_ACTION0 = 0x07010986ull;
+
+static const uint64_t P9N2_MCA_3_MBACALFIR_ACTION0 = 0x070109C6ull;
+
+static const uint64_t P9N2_MCA_4_MBACALFIR_ACTION0 = 0x08010906ull;
+
+static const uint64_t P9N2_MCA_5_MBACALFIR_ACTION0 = 0x08010946ull;
+
+static const uint64_t P9N2_MCA_6_MBACALFIR_ACTION0 = 0x08010986ull;
+
+static const uint64_t P9N2_MCA_7_MBACALFIR_ACTION0 = 0x080109C6ull;
+
+
+static const uint64_t P9N2_MCA_MBACALFIR_ACTION1 = 0x07010907ull;
+
+static const uint64_t P9N2_MCA_0_MBACALFIR_ACTION1 = 0x07010907ull;
+
+static const uint64_t P9N2_MCA_1_MBACALFIR_ACTION1 = 0x07010947ull;
+
+static const uint64_t P9N2_MCA_2_MBACALFIR_ACTION1 = 0x07010987ull;
+
+static const uint64_t P9N2_MCA_3_MBACALFIR_ACTION1 = 0x070109C7ull;
+
+static const uint64_t P9N2_MCA_4_MBACALFIR_ACTION1 = 0x08010907ull;
+
+static const uint64_t P9N2_MCA_5_MBACALFIR_ACTION1 = 0x08010947ull;
+
+static const uint64_t P9N2_MCA_6_MBACALFIR_ACTION1 = 0x08010987ull;
+
+static const uint64_t P9N2_MCA_7_MBACALFIR_ACTION1 = 0x080109C7ull;
+
+
+static const uint64_t P9N2_MCA_MBACALFIR_MASK = 0x07010903ull;
+
+static const uint64_t P9N2_MCA_MBACALFIR_MASK_AND = 0x07010904ull;
+
+static const uint64_t P9N2_MCA_MBACALFIR_MASK_OR = 0x07010905ull;
+
+static const uint64_t P9N2_MCA_0_MBACALFIR_MASK = 0x07010903ull;
+
+static const uint64_t P9N2_MCA_0_MBACALFIR_MASK_AND = 0x07010904ull;
+
+static const uint64_t P9N2_MCA_0_MBACALFIR_MASK_OR = 0x07010905ull;
+
+static const uint64_t P9N2_MCA_1_MBACALFIR_MASK = 0x07010943ull;
+
+static const uint64_t P9N2_MCA_1_MBACALFIR_MASK_AND = 0x07010944ull;
+
+static const uint64_t P9N2_MCA_1_MBACALFIR_MASK_OR = 0x07010945ull;
+
+static const uint64_t P9N2_MCA_2_MBACALFIR_MASK = 0x07010983ull;
+
+static const uint64_t P9N2_MCA_2_MBACALFIR_MASK_AND = 0x07010984ull;
+
+static const uint64_t P9N2_MCA_2_MBACALFIR_MASK_OR = 0x07010985ull;
+
+static const uint64_t P9N2_MCA_3_MBACALFIR_MASK = 0x070109C3ull;
+
+static const uint64_t P9N2_MCA_3_MBACALFIR_MASK_AND = 0x070109C4ull;
+
+static const uint64_t P9N2_MCA_3_MBACALFIR_MASK_OR = 0x070109C5ull;
+
+static const uint64_t P9N2_MCA_4_MBACALFIR_MASK = 0x08010903ull;
+
+static const uint64_t P9N2_MCA_4_MBACALFIR_MASK_AND = 0x08010904ull;
+
+static const uint64_t P9N2_MCA_4_MBACALFIR_MASK_OR = 0x08010905ull;
+
+static const uint64_t P9N2_MCA_5_MBACALFIR_MASK = 0x08010943ull;
+
+static const uint64_t P9N2_MCA_5_MBACALFIR_MASK_AND = 0x08010944ull;
+
+static const uint64_t P9N2_MCA_5_MBACALFIR_MASK_OR = 0x08010945ull;
+
+static const uint64_t P9N2_MCA_6_MBACALFIR_MASK = 0x08010983ull;
+
+static const uint64_t P9N2_MCA_6_MBACALFIR_MASK_AND = 0x08010984ull;
+
+static const uint64_t P9N2_MCA_6_MBACALFIR_MASK_OR = 0x08010985ull;
+
+static const uint64_t P9N2_MCA_7_MBACALFIR_MASK = 0x080109C3ull;
+
+static const uint64_t P9N2_MCA_7_MBACALFIR_MASK_AND = 0x080109C4ull;
+
+static const uint64_t P9N2_MCA_7_MBACALFIR_MASK_OR = 0x080109C5ull;
+
+
+static const uint64_t P9N2_MCA_MBAREF0Q = 0x07010932ull;
+
+static const uint64_t P9N2_MCA_0_MBAREF0Q = 0x07010932ull;
+
+static const uint64_t P9N2_MCA_1_MBAREF0Q = 0x07010972ull;
+
+static const uint64_t P9N2_MCA_2_MBAREF0Q = 0x070109B2ull;
+
+static const uint64_t P9N2_MCA_3_MBAREF0Q = 0x070109F2ull;
+
+static const uint64_t P9N2_MCA_4_MBAREF0Q = 0x08010932ull;
+
+static const uint64_t P9N2_MCA_5_MBAREF0Q = 0x08010972ull;
+
+static const uint64_t P9N2_MCA_6_MBAREF0Q = 0x080109B2ull;
+
+static const uint64_t P9N2_MCA_7_MBAREF0Q = 0x080109F2ull;
+
+
+static const uint64_t P9N2_MCA_MBAREFAQ = 0x07010936ull;
+
+static const uint64_t P9N2_MCA_0_MBAREFAQ = 0x07010936ull;
+
+static const uint64_t P9N2_MCA_1_MBAREFAQ = 0x07010976ull;
+
+static const uint64_t P9N2_MCA_2_MBAREFAQ = 0x070109B6ull;
+
+static const uint64_t P9N2_MCA_3_MBAREFAQ = 0x070109F6ull;
+
+static const uint64_t P9N2_MCA_4_MBAREFAQ = 0x08010936ull;
+
+static const uint64_t P9N2_MCA_5_MBAREFAQ = 0x08010976ull;
+
+static const uint64_t P9N2_MCA_6_MBAREFAQ = 0x080109B6ull;
+
+static const uint64_t P9N2_MCA_7_MBAREFAQ = 0x080109F6ull;
+
+
+static const uint64_t P9N2_MCA_MBARPC0Q = 0x07010934ull;
+
+static const uint64_t P9N2_MCA_0_MBARPC0Q = 0x07010934ull;
+
+static const uint64_t P9N2_MCA_1_MBARPC0Q = 0x07010974ull;
+
+static const uint64_t P9N2_MCA_2_MBARPC0Q = 0x070109B4ull;
+
+static const uint64_t P9N2_MCA_3_MBARPC0Q = 0x070109F4ull;
+
+static const uint64_t P9N2_MCA_4_MBARPC0Q = 0x08010934ull;
+
+static const uint64_t P9N2_MCA_5_MBARPC0Q = 0x08010974ull;
+
+static const uint64_t P9N2_MCA_6_MBARPC0Q = 0x080109B4ull;
+
+static const uint64_t P9N2_MCA_7_MBARPC0Q = 0x080109F4ull;
+
+
+static const uint64_t P9N2_MCA_MBARSVD0 = 0x07010933ull;
+
+static const uint64_t P9N2_MCA_0_MBARSVD0 = 0x07010933ull;
+
+static const uint64_t P9N2_MCA_1_MBARSVD0 = 0x07010973ull;
+
+static const uint64_t P9N2_MCA_2_MBARSVD0 = 0x070109B3ull;
+
+static const uint64_t P9N2_MCA_3_MBARSVD0 = 0x070109F3ull;
+
+static const uint64_t P9N2_MCA_4_MBARSVD0 = 0x08010933ull;
+
+static const uint64_t P9N2_MCA_5_MBARSVD0 = 0x08010973ull;
+
+static const uint64_t P9N2_MCA_6_MBARSVD0 = 0x080109B3ull;
+
+static const uint64_t P9N2_MCA_7_MBARSVD0 = 0x080109F3ull;
+
+
+static const uint64_t P9N2_MCA_MBASTR0Q = 0x07010935ull;
+
+static const uint64_t P9N2_MCA_0_MBASTR0Q = 0x07010935ull;
+
+static const uint64_t P9N2_MCA_1_MBASTR0Q = 0x07010975ull;
+
+static const uint64_t P9N2_MCA_2_MBASTR0Q = 0x070109B5ull;
+
+static const uint64_t P9N2_MCA_3_MBASTR0Q = 0x070109F5ull;
+
+static const uint64_t P9N2_MCA_4_MBASTR0Q = 0x08010935ull;
+
+static const uint64_t P9N2_MCA_5_MBASTR0Q = 0x08010975ull;
+
+static const uint64_t P9N2_MCA_6_MBASTR0Q = 0x080109B5ull;
+
+static const uint64_t P9N2_MCA_7_MBASTR0Q = 0x080109F5ull;
+
+
+static const uint64_t P9N2_MCBIST_MBAUER0Q = 0x0701236Eull;
+
+static const uint64_t P9N2_MCBIST_0_MBAUER0Q = 0x0701236Eull;
+
+static const uint64_t P9N2_MCBIST_1_MBAUER0Q = 0x0801236Eull;
+
+
+static const uint64_t P9N2_MCBIST_MBAUER1Q = 0x07012373ull;
+
+static const uint64_t P9N2_MCBIST_0_MBAUER1Q = 0x07012373ull;
+
+static const uint64_t P9N2_MCBIST_1_MBAUER1Q = 0x08012373ull;
+
+
+static const uint64_t P9N2_MCBIST_MBAUER2Q = 0x07012378ull;
+
+static const uint64_t P9N2_MCBIST_0_MBAUER2Q = 0x07012378ull;
+
+static const uint64_t P9N2_MCBIST_1_MBAUER2Q = 0x08012378ull;
+
+
+static const uint64_t P9N2_MCBIST_MBAUER3Q = 0x0701237Dull;
+
+static const uint64_t P9N2_MCBIST_0_MBAUER3Q = 0x0701237Dull;
+
+static const uint64_t P9N2_MCBIST_1_MBAUER3Q = 0x0801237Dull;
+
+
+static const uint64_t P9N2_MCA_MBA_CAL0Q = 0x0701090Full;
+
+static const uint64_t P9N2_MCA_0_MBA_CAL0Q = 0x0701090Full;
+
+static const uint64_t P9N2_MCA_1_MBA_CAL0Q = 0x0701094Full;
+
+static const uint64_t P9N2_MCA_2_MBA_CAL0Q = 0x0701098Full;
+
+static const uint64_t P9N2_MCA_3_MBA_CAL0Q = 0x070109CFull;
+
+static const uint64_t P9N2_MCA_4_MBA_CAL0Q = 0x0801090Full;
+
+static const uint64_t P9N2_MCA_5_MBA_CAL0Q = 0x0801094Full;
+
+static const uint64_t P9N2_MCA_6_MBA_CAL0Q = 0x0801098Full;
+
+static const uint64_t P9N2_MCA_7_MBA_CAL0Q = 0x080109CFull;
+
+
+static const uint64_t P9N2_MCA_MBA_CAL1Q = 0x07010910ull;
+
+static const uint64_t P9N2_MCA_0_MBA_CAL1Q = 0x07010910ull;
+
+static const uint64_t P9N2_MCA_1_MBA_CAL1Q = 0x07010950ull;
+
+static const uint64_t P9N2_MCA_2_MBA_CAL1Q = 0x07010990ull;
+
+static const uint64_t P9N2_MCA_3_MBA_CAL1Q = 0x070109D0ull;
+
+static const uint64_t P9N2_MCA_4_MBA_CAL1Q = 0x08010910ull;
+
+static const uint64_t P9N2_MCA_5_MBA_CAL1Q = 0x08010950ull;
+
+static const uint64_t P9N2_MCA_6_MBA_CAL1Q = 0x08010990ull;
+
+static const uint64_t P9N2_MCA_7_MBA_CAL1Q = 0x080109D0ull;
+
+
+static const uint64_t P9N2_MCA_MBA_CAL2Q = 0x07010911ull;
+
+static const uint64_t P9N2_MCA_0_MBA_CAL2Q = 0x07010911ull;
+
+static const uint64_t P9N2_MCA_1_MBA_CAL2Q = 0x07010951ull;
+
+static const uint64_t P9N2_MCA_2_MBA_CAL2Q = 0x07010991ull;
+
+static const uint64_t P9N2_MCA_3_MBA_CAL2Q = 0x070109D1ull;
+
+static const uint64_t P9N2_MCA_4_MBA_CAL2Q = 0x08010911ull;
+
+static const uint64_t P9N2_MCA_5_MBA_CAL2Q = 0x08010951ull;
+
+static const uint64_t P9N2_MCA_6_MBA_CAL2Q = 0x08010991ull;
+
+static const uint64_t P9N2_MCA_7_MBA_CAL2Q = 0x080109D1ull;
+
+
+static const uint64_t P9N2_MCA_MBA_CAL3Q = 0x07010912ull;
+
+static const uint64_t P9N2_MCA_0_MBA_CAL3Q = 0x07010912ull;
+
+static const uint64_t P9N2_MCA_1_MBA_CAL3Q = 0x07010952ull;
+
+static const uint64_t P9N2_MCA_2_MBA_CAL3Q = 0x07010992ull;
+
+static const uint64_t P9N2_MCA_3_MBA_CAL3Q = 0x070109D2ull;
+
+static const uint64_t P9N2_MCA_4_MBA_CAL3Q = 0x08010912ull;
+
+static const uint64_t P9N2_MCA_5_MBA_CAL3Q = 0x08010952ull;
+
+static const uint64_t P9N2_MCA_6_MBA_CAL3Q = 0x08010992ull;
+
+static const uint64_t P9N2_MCA_7_MBA_CAL3Q = 0x080109D2ull;
+
+
+static const uint64_t P9N2_MCA_MBA_DBG0Q = 0x07010926ull;
+
+static const uint64_t P9N2_MCA_0_MBA_DBG0Q = 0x07010926ull;
+
+static const uint64_t P9N2_MCA_1_MBA_DBG0Q = 0x07010966ull;
+
+static const uint64_t P9N2_MCA_2_MBA_DBG0Q = 0x070109A6ull;
+
+static const uint64_t P9N2_MCA_3_MBA_DBG0Q = 0x070109E6ull;
+
+static const uint64_t P9N2_MCA_4_MBA_DBG0Q = 0x08010926ull;
+
+static const uint64_t P9N2_MCA_5_MBA_DBG0Q = 0x08010966ull;
+
+static const uint64_t P9N2_MCA_6_MBA_DBG0Q = 0x080109A6ull;
+
+static const uint64_t P9N2_MCA_7_MBA_DBG0Q = 0x080109E6ull;
+
+
+static const uint64_t P9N2_MCA_MBA_DBG1Q = 0x07010927ull;
+
+static const uint64_t P9N2_MCA_0_MBA_DBG1Q = 0x07010927ull;
+
+static const uint64_t P9N2_MCA_1_MBA_DBG1Q = 0x07010967ull;
+
+static const uint64_t P9N2_MCA_2_MBA_DBG1Q = 0x070109A7ull;
+
+static const uint64_t P9N2_MCA_3_MBA_DBG1Q = 0x070109E7ull;
+
+static const uint64_t P9N2_MCA_4_MBA_DBG1Q = 0x08010927ull;
+
+static const uint64_t P9N2_MCA_5_MBA_DBG1Q = 0x08010967ull;
+
+static const uint64_t P9N2_MCA_6_MBA_DBG1Q = 0x080109A7ull;
+
+static const uint64_t P9N2_MCA_7_MBA_DBG1Q = 0x080109E7ull;
+
+
+static const uint64_t P9N2_MCA_MBA_DSM0Q = 0x0701090Aull;
+
+static const uint64_t P9N2_MCA_0_MBA_DSM0Q = 0x0701090Aull;
+
+static const uint64_t P9N2_MCA_1_MBA_DSM0Q = 0x0701094Aull;
+
+static const uint64_t P9N2_MCA_2_MBA_DSM0Q = 0x0701098Aull;
+
+static const uint64_t P9N2_MCA_3_MBA_DSM0Q = 0x070109CAull;
+
+static const uint64_t P9N2_MCA_4_MBA_DSM0Q = 0x0801090Aull;
+
+static const uint64_t P9N2_MCA_5_MBA_DSM0Q = 0x0801094Aull;
+
+static const uint64_t P9N2_MCA_6_MBA_DSM0Q = 0x0801098Aull;
+
+static const uint64_t P9N2_MCA_7_MBA_DSM0Q = 0x080109CAull;
+
+
+static const uint64_t P9N2_MCA_MBA_ERR_REPORTQ = 0x0701091Aull;
+
+static const uint64_t P9N2_MCA_0_MBA_ERR_REPORTQ = 0x0701091Aull;
+
+static const uint64_t P9N2_MCA_1_MBA_ERR_REPORTQ = 0x0701095Aull;
+
+static const uint64_t P9N2_MCA_2_MBA_ERR_REPORTQ = 0x0701099Aull;
+
+static const uint64_t P9N2_MCA_3_MBA_ERR_REPORTQ = 0x070109DAull;
+
+static const uint64_t P9N2_MCA_4_MBA_ERR_REPORTQ = 0x0801091Aull;
+
+static const uint64_t P9N2_MCA_5_MBA_ERR_REPORTQ = 0x0801095Aull;
+
+static const uint64_t P9N2_MCA_6_MBA_ERR_REPORTQ = 0x0801099Aull;
+
+static const uint64_t P9N2_MCA_7_MBA_ERR_REPORTQ = 0x080109DAull;
+
+
+static const uint64_t P9N2_MCA_MBA_FARB0Q = 0x07010913ull;
+
+static const uint64_t P9N2_MCA_0_MBA_FARB0Q = 0x07010913ull;
+
+static const uint64_t P9N2_MCA_1_MBA_FARB0Q = 0x07010953ull;
+
+static const uint64_t P9N2_MCA_2_MBA_FARB0Q = 0x07010993ull;
+
+static const uint64_t P9N2_MCA_3_MBA_FARB0Q = 0x070109D3ull;
+
+static const uint64_t P9N2_MCA_4_MBA_FARB0Q = 0x08010913ull;
+
+static const uint64_t P9N2_MCA_5_MBA_FARB0Q = 0x08010953ull;
+
+static const uint64_t P9N2_MCA_6_MBA_FARB0Q = 0x08010993ull;
+
+static const uint64_t P9N2_MCA_7_MBA_FARB0Q = 0x080109D3ull;
+
+
+static const uint64_t P9N2_MCA_MBA_FARB1Q = 0x07010914ull;
+
+static const uint64_t P9N2_MCA_0_MBA_FARB1Q = 0x07010914ull;
+
+static const uint64_t P9N2_MCA_1_MBA_FARB1Q = 0x07010954ull;
+
+static const uint64_t P9N2_MCA_2_MBA_FARB1Q = 0x07010994ull;
+
+static const uint64_t P9N2_MCA_3_MBA_FARB1Q = 0x070109D4ull;
+
+static const uint64_t P9N2_MCA_4_MBA_FARB1Q = 0x08010914ull;
+
+static const uint64_t P9N2_MCA_5_MBA_FARB1Q = 0x08010954ull;
+
+static const uint64_t P9N2_MCA_6_MBA_FARB1Q = 0x08010994ull;
+
+static const uint64_t P9N2_MCA_7_MBA_FARB1Q = 0x080109D4ull;
+
+
+static const uint64_t P9N2_MCA_MBA_FARB2Q = 0x07010915ull;
+
+static const uint64_t P9N2_MCA_0_MBA_FARB2Q = 0x07010915ull;
+
+static const uint64_t P9N2_MCA_1_MBA_FARB2Q = 0x07010955ull;
+
+static const uint64_t P9N2_MCA_2_MBA_FARB2Q = 0x07010995ull;
+
+static const uint64_t P9N2_MCA_3_MBA_FARB2Q = 0x070109D5ull;
+
+static const uint64_t P9N2_MCA_4_MBA_FARB2Q = 0x08010915ull;
+
+static const uint64_t P9N2_MCA_5_MBA_FARB2Q = 0x08010955ull;
+
+static const uint64_t P9N2_MCA_6_MBA_FARB2Q = 0x08010995ull;
+
+static const uint64_t P9N2_MCA_7_MBA_FARB2Q = 0x080109D5ull;
+
+
+static const uint64_t P9N2_MCA_MBA_FARB3Q = 0x07010916ull;
+
+static const uint64_t P9N2_MCA_0_MBA_FARB3Q = 0x07010916ull;
+
+static const uint64_t P9N2_MCA_1_MBA_FARB3Q = 0x07010956ull;
+
+static const uint64_t P9N2_MCA_2_MBA_FARB3Q = 0x07010996ull;
+
+static const uint64_t P9N2_MCA_3_MBA_FARB3Q = 0x070109D6ull;
+
+static const uint64_t P9N2_MCA_4_MBA_FARB3Q = 0x08010916ull;
+
+static const uint64_t P9N2_MCA_5_MBA_FARB3Q = 0x08010956ull;
+
+static const uint64_t P9N2_MCA_6_MBA_FARB3Q = 0x08010996ull;
+
+static const uint64_t P9N2_MCA_7_MBA_FARB3Q = 0x080109D6ull;
+
+
+static const uint64_t P9N2_MCA_MBA_FARB4Q = 0x07010917ull;
+
+static const uint64_t P9N2_MCA_0_MBA_FARB4Q = 0x07010917ull;
+
+static const uint64_t P9N2_MCA_1_MBA_FARB4Q = 0x07010957ull;
+
+static const uint64_t P9N2_MCA_2_MBA_FARB4Q = 0x07010997ull;
+
+static const uint64_t P9N2_MCA_3_MBA_FARB4Q = 0x070109D7ull;
+
+static const uint64_t P9N2_MCA_4_MBA_FARB4Q = 0x08010917ull;
+
+static const uint64_t P9N2_MCA_5_MBA_FARB4Q = 0x08010957ull;
+
+static const uint64_t P9N2_MCA_6_MBA_FARB4Q = 0x08010997ull;
+
+static const uint64_t P9N2_MCA_7_MBA_FARB4Q = 0x080109D7ull;
+
+
+static const uint64_t P9N2_MCA_MBA_FARB5Q = 0x07010918ull;
+
+static const uint64_t P9N2_MCA_0_MBA_FARB5Q = 0x07010918ull;
+
+static const uint64_t P9N2_MCA_1_MBA_FARB5Q = 0x07010958ull;
+
+static const uint64_t P9N2_MCA_2_MBA_FARB5Q = 0x07010998ull;
+
+static const uint64_t P9N2_MCA_3_MBA_FARB5Q = 0x070109D8ull;
+
+static const uint64_t P9N2_MCA_4_MBA_FARB5Q = 0x08010918ull;
+
+static const uint64_t P9N2_MCA_5_MBA_FARB5Q = 0x08010958ull;
+
+static const uint64_t P9N2_MCA_6_MBA_FARB5Q = 0x08010998ull;
+
+static const uint64_t P9N2_MCA_7_MBA_FARB5Q = 0x080109D8ull;
+
+
+static const uint64_t P9N2_MCA_MBA_FARB6Q = 0x07010919ull;
+
+static const uint64_t P9N2_MCA_0_MBA_FARB6Q = 0x07010919ull;
+
+static const uint64_t P9N2_MCA_1_MBA_FARB6Q = 0x07010959ull;
+
+static const uint64_t P9N2_MCA_2_MBA_FARB6Q = 0x07010999ull;
+
+static const uint64_t P9N2_MCA_3_MBA_FARB6Q = 0x070109D9ull;
+
+static const uint64_t P9N2_MCA_4_MBA_FARB6Q = 0x08010919ull;
+
+static const uint64_t P9N2_MCA_5_MBA_FARB6Q = 0x08010959ull;
+
+static const uint64_t P9N2_MCA_6_MBA_FARB6Q = 0x08010999ull;
+
+static const uint64_t P9N2_MCA_7_MBA_FARB6Q = 0x080109D9ull;
+
+
+static const uint64_t P9N2_MCA_MBA_FARB7Q = 0x07010925ull;
+
+static const uint64_t P9N2_MCA_0_MBA_FARB7Q = 0x07010925ull;
+
+static const uint64_t P9N2_MCA_1_MBA_FARB7Q = 0x07010965ull;
+
+static const uint64_t P9N2_MCA_2_MBA_FARB7Q = 0x070109A5ull;
+
+static const uint64_t P9N2_MCA_3_MBA_FARB7Q = 0x070109E5ull;
+
+static const uint64_t P9N2_MCA_4_MBA_FARB7Q = 0x08010925ull;
+
+static const uint64_t P9N2_MCA_5_MBA_FARB7Q = 0x08010965ull;
+
+static const uint64_t P9N2_MCA_6_MBA_FARB7Q = 0x080109A5ull;
+
+static const uint64_t P9N2_MCA_7_MBA_FARB7Q = 0x080109E5ull;
+
+
+static const uint64_t P9N2_MCA_MBA_FARB8Q = 0x07010928ull;
+
+static const uint64_t P9N2_MCA_0_MBA_FARB8Q = 0x07010928ull;
+
+static const uint64_t P9N2_MCA_1_MBA_FARB8Q = 0x07010968ull;
+
+static const uint64_t P9N2_MCA_2_MBA_FARB8Q = 0x070109A8ull;
+
+static const uint64_t P9N2_MCA_3_MBA_FARB8Q = 0x070109E8ull;
+
+static const uint64_t P9N2_MCA_4_MBA_FARB8Q = 0x08010928ull;
+
+static const uint64_t P9N2_MCA_5_MBA_FARB8Q = 0x08010968ull;
+
+static const uint64_t P9N2_MCA_6_MBA_FARB8Q = 0x080109A8ull;
+
+static const uint64_t P9N2_MCA_7_MBA_FARB8Q = 0x080109E8ull;
+
+
+static const uint64_t P9N2_MCBIST_MBA_MCBERRPTQ = 0x070123E7ull;
+
+static const uint64_t P9N2_MCBIST_0_MBA_MCBERRPTQ = 0x070123E7ull;
+
+static const uint64_t P9N2_MCBIST_1_MBA_MCBERRPTQ = 0x080123E7ull;
+
+
+static const uint64_t P9N2_MCA_MBA_PMU0Q = 0x07010937ull;
+
+static const uint64_t P9N2_MCA_0_MBA_PMU0Q = 0x07010937ull;
+
+static const uint64_t P9N2_MCA_1_MBA_PMU0Q = 0x07010977ull;
+
+static const uint64_t P9N2_MCA_2_MBA_PMU0Q = 0x070109B7ull;
+
+static const uint64_t P9N2_MCA_3_MBA_PMU0Q = 0x070109F7ull;
+
+static const uint64_t P9N2_MCA_4_MBA_PMU0Q = 0x08010937ull;
+
+static const uint64_t P9N2_MCA_5_MBA_PMU0Q = 0x08010977ull;
+
+static const uint64_t P9N2_MCA_6_MBA_PMU0Q = 0x080109B7ull;
+
+static const uint64_t P9N2_MCA_7_MBA_PMU0Q = 0x080109F7ull;
+
+
+static const uint64_t P9N2_MCA_MBA_PMU1Q = 0x07010938ull;
+
+static const uint64_t P9N2_MCA_0_MBA_PMU1Q = 0x07010938ull;
+
+static const uint64_t P9N2_MCA_1_MBA_PMU1Q = 0x07010978ull;
+
+static const uint64_t P9N2_MCA_2_MBA_PMU1Q = 0x070109B8ull;
+
+static const uint64_t P9N2_MCA_3_MBA_PMU1Q = 0x070109F8ull;
+
+static const uint64_t P9N2_MCA_4_MBA_PMU1Q = 0x08010938ull;
+
+static const uint64_t P9N2_MCA_5_MBA_PMU1Q = 0x08010978ull;
+
+static const uint64_t P9N2_MCA_6_MBA_PMU1Q = 0x080109B8ull;
+
+static const uint64_t P9N2_MCA_7_MBA_PMU1Q = 0x080109F8ull;
+
+
+static const uint64_t P9N2_MCA_MBA_PMU2Q = 0x07010939ull;
+
+static const uint64_t P9N2_MCA_0_MBA_PMU2Q = 0x07010939ull;
+
+static const uint64_t P9N2_MCA_1_MBA_PMU2Q = 0x07010979ull;
+
+static const uint64_t P9N2_MCA_2_MBA_PMU2Q = 0x070109B9ull;
+
+static const uint64_t P9N2_MCA_3_MBA_PMU2Q = 0x070109F9ull;
+
+static const uint64_t P9N2_MCA_4_MBA_PMU2Q = 0x08010939ull;
+
+static const uint64_t P9N2_MCA_5_MBA_PMU2Q = 0x08010979ull;
+
+static const uint64_t P9N2_MCA_6_MBA_PMU2Q = 0x080109B9ull;
+
+static const uint64_t P9N2_MCA_7_MBA_PMU2Q = 0x080109F9ull;
+
+
+static const uint64_t P9N2_MCA_MBA_PMU3Q = 0x0701093Aull;
+
+static const uint64_t P9N2_MCA_0_MBA_PMU3Q = 0x0701093Aull;
+
+static const uint64_t P9N2_MCA_1_MBA_PMU3Q = 0x0701097Aull;
+
+static const uint64_t P9N2_MCA_2_MBA_PMU3Q = 0x070109BAull;
+
+static const uint64_t P9N2_MCA_3_MBA_PMU3Q = 0x070109FAull;
+
+static const uint64_t P9N2_MCA_4_MBA_PMU3Q = 0x0801093Aull;
+
+static const uint64_t P9N2_MCA_5_MBA_PMU3Q = 0x0801097Aull;
+
+static const uint64_t P9N2_MCA_6_MBA_PMU3Q = 0x080109BAull;
+
+static const uint64_t P9N2_MCA_7_MBA_PMU3Q = 0x080109FAull;
+
+
+static const uint64_t P9N2_MCA_MBA_PMU4Q = 0x0701093Bull;
+
+static const uint64_t P9N2_MCA_0_MBA_PMU4Q = 0x0701093Bull;
+
+static const uint64_t P9N2_MCA_1_MBA_PMU4Q = 0x0701097Bull;
+
+static const uint64_t P9N2_MCA_2_MBA_PMU4Q = 0x070109BBull;
+
+static const uint64_t P9N2_MCA_3_MBA_PMU4Q = 0x070109FBull;
+
+static const uint64_t P9N2_MCA_4_MBA_PMU4Q = 0x0801093Bull;
+
+static const uint64_t P9N2_MCA_5_MBA_PMU4Q = 0x0801097Bull;
+
+static const uint64_t P9N2_MCA_6_MBA_PMU4Q = 0x080109BBull;
+
+static const uint64_t P9N2_MCA_7_MBA_PMU4Q = 0x080109FBull;
+
+
+static const uint64_t P9N2_MCA_MBA_PMU5Q = 0x0701093Cull;
+
+static const uint64_t P9N2_MCA_0_MBA_PMU5Q = 0x0701093Cull;
+
+static const uint64_t P9N2_MCA_1_MBA_PMU5Q = 0x0701097Cull;
+
+static const uint64_t P9N2_MCA_2_MBA_PMU5Q = 0x070109BCull;
+
+static const uint64_t P9N2_MCA_3_MBA_PMU5Q = 0x070109FCull;
+
+static const uint64_t P9N2_MCA_4_MBA_PMU5Q = 0x0801093Cull;
+
+static const uint64_t P9N2_MCA_5_MBA_PMU5Q = 0x0801097Cull;
+
+static const uint64_t P9N2_MCA_6_MBA_PMU5Q = 0x080109BCull;
+
+static const uint64_t P9N2_MCA_7_MBA_PMU5Q = 0x080109FCull;
+
+
+static const uint64_t P9N2_MCA_MBA_PMU6Q = 0x0701093Dull;
+
+static const uint64_t P9N2_MCA_0_MBA_PMU6Q = 0x0701093Dull;
+
+static const uint64_t P9N2_MCA_1_MBA_PMU6Q = 0x0701097Dull;
+
+static const uint64_t P9N2_MCA_2_MBA_PMU6Q = 0x070109BDull;
+
+static const uint64_t P9N2_MCA_3_MBA_PMU6Q = 0x070109FDull;
+
+static const uint64_t P9N2_MCA_4_MBA_PMU6Q = 0x0801093Dull;
+
+static const uint64_t P9N2_MCA_5_MBA_PMU6Q = 0x0801097Dull;
+
+static const uint64_t P9N2_MCA_6_MBA_PMU6Q = 0x080109BDull;
+
+static const uint64_t P9N2_MCA_7_MBA_PMU6Q = 0x080109FDull;
+
+
+static const uint64_t P9N2_MCA_MBA_PMU7Q = 0x0701093Eull;
+
+static const uint64_t P9N2_MCA_0_MBA_PMU7Q = 0x0701093Eull;
+
+static const uint64_t P9N2_MCA_1_MBA_PMU7Q = 0x0701097Eull;
+
+static const uint64_t P9N2_MCA_2_MBA_PMU7Q = 0x070109BEull;
+
+static const uint64_t P9N2_MCA_3_MBA_PMU7Q = 0x070109FEull;
+
+static const uint64_t P9N2_MCA_4_MBA_PMU7Q = 0x0801093Eull;
+
+static const uint64_t P9N2_MCA_5_MBA_PMU7Q = 0x0801097Eull;
+
+static const uint64_t P9N2_MCA_6_MBA_PMU7Q = 0x080109BEull;
+
+static const uint64_t P9N2_MCA_7_MBA_PMU7Q = 0x080109FEull;
+
+
+static const uint64_t P9N2_MCA_MBA_PMU8Q = 0x0701093Full;
+
+static const uint64_t P9N2_MCA_0_MBA_PMU8Q = 0x0701093Full;
+
+static const uint64_t P9N2_MCA_1_MBA_PMU8Q = 0x0701097Full;
+
+static const uint64_t P9N2_MCA_2_MBA_PMU8Q = 0x070109BFull;
+
+static const uint64_t P9N2_MCA_3_MBA_PMU8Q = 0x070109FFull;
+
+static const uint64_t P9N2_MCA_4_MBA_PMU8Q = 0x0801093Full;
+
+static const uint64_t P9N2_MCA_5_MBA_PMU8Q = 0x0801097Full;
+
+static const uint64_t P9N2_MCA_6_MBA_PMU8Q = 0x080109BFull;
+
+static const uint64_t P9N2_MCA_7_MBA_PMU8Q = 0x080109FFull;
+
+
+static const uint64_t P9N2_MCA_MBA_RRQ0Q = 0x0701090Eull;
+
+static const uint64_t P9N2_MCA_0_MBA_RRQ0Q = 0x0701090Eull;
+
+static const uint64_t P9N2_MCA_1_MBA_RRQ0Q = 0x0701094Eull;
+
+static const uint64_t P9N2_MCA_2_MBA_RRQ0Q = 0x0701098Eull;
+
+static const uint64_t P9N2_MCA_3_MBA_RRQ0Q = 0x070109CEull;
+
+static const uint64_t P9N2_MCA_4_MBA_RRQ0Q = 0x0801090Eull;
+
+static const uint64_t P9N2_MCA_5_MBA_RRQ0Q = 0x0801094Eull;
+
+static const uint64_t P9N2_MCA_6_MBA_RRQ0Q = 0x0801098Eull;
+
+static const uint64_t P9N2_MCA_7_MBA_RRQ0Q = 0x080109CEull;
+
+
+static const uint64_t P9N2_MCA_MBA_TMR0Q = 0x0701090Bull;
+
+static const uint64_t P9N2_MCA_0_MBA_TMR0Q = 0x0701090Bull;
+
+static const uint64_t P9N2_MCA_1_MBA_TMR0Q = 0x0701094Bull;
+
+static const uint64_t P9N2_MCA_2_MBA_TMR0Q = 0x0701098Bull;
+
+static const uint64_t P9N2_MCA_3_MBA_TMR0Q = 0x070109CBull;
+
+static const uint64_t P9N2_MCA_4_MBA_TMR0Q = 0x0801090Bull;
+
+static const uint64_t P9N2_MCA_5_MBA_TMR0Q = 0x0801094Bull;
+
+static const uint64_t P9N2_MCA_6_MBA_TMR0Q = 0x0801098Bull;
+
+static const uint64_t P9N2_MCA_7_MBA_TMR0Q = 0x080109CBull;
+
+
+static const uint64_t P9N2_MCA_MBA_TMR1Q = 0x0701090Cull;
+
+static const uint64_t P9N2_MCA_0_MBA_TMR1Q = 0x0701090Cull;
+
+static const uint64_t P9N2_MCA_1_MBA_TMR1Q = 0x0701094Cull;
+
+static const uint64_t P9N2_MCA_2_MBA_TMR1Q = 0x0701098Cull;
+
+static const uint64_t P9N2_MCA_3_MBA_TMR1Q = 0x070109CCull;
+
+static const uint64_t P9N2_MCA_4_MBA_TMR1Q = 0x0801090Cull;
+
+static const uint64_t P9N2_MCA_5_MBA_TMR1Q = 0x0801094Cull;
+
+static const uint64_t P9N2_MCA_6_MBA_TMR1Q = 0x0801098Cull;
+
+static const uint64_t P9N2_MCA_7_MBA_TMR1Q = 0x080109CCull;
+
+
+static const uint64_t P9N2_MCA_MBA_TMR2Q = 0x0701092Full;
+
+static const uint64_t P9N2_MCA_0_MBA_TMR2Q = 0x0701092Full;
+
+static const uint64_t P9N2_MCA_1_MBA_TMR2Q = 0x0701096Full;
+
+static const uint64_t P9N2_MCA_2_MBA_TMR2Q = 0x070109AFull;
+
+static const uint64_t P9N2_MCA_3_MBA_TMR2Q = 0x070109EFull;
+
+static const uint64_t P9N2_MCA_4_MBA_TMR2Q = 0x0801092Full;
+
+static const uint64_t P9N2_MCA_5_MBA_TMR2Q = 0x0801096Full;
+
+static const uint64_t P9N2_MCA_6_MBA_TMR2Q = 0x080109AFull;
+
+static const uint64_t P9N2_MCA_7_MBA_TMR2Q = 0x080109EFull;
+
+
+static const uint64_t P9N2_MCA_MBA_WRQ0Q = 0x0701090Dull;
+
+static const uint64_t P9N2_MCA_0_MBA_WRQ0Q = 0x0701090Dull;
+
+static const uint64_t P9N2_MCA_1_MBA_WRQ0Q = 0x0701094Dull;
+
+static const uint64_t P9N2_MCA_2_MBA_WRQ0Q = 0x0701098Dull;
+
+static const uint64_t P9N2_MCA_3_MBA_WRQ0Q = 0x070109CDull;
+
+static const uint64_t P9N2_MCA_4_MBA_WRQ0Q = 0x0801090Dull;
+
+static const uint64_t P9N2_MCA_5_MBA_WRQ0Q = 0x0801094Dull;
+
+static const uint64_t P9N2_MCA_6_MBA_WRQ0Q = 0x0801098Dull;
+
+static const uint64_t P9N2_MCA_7_MBA_WRQ0Q = 0x080109CDull;
+
+
+static const uint64_t P9N2_MCBIST_MBECTLQ = 0x07012310ull;
+
+static const uint64_t P9N2_MCBIST_0_MBECTLQ = 0x07012310ull;
+
+static const uint64_t P9N2_MCBIST_1_MBECTLQ = 0x08012310ull;
+
+
+static const uint64_t P9N2_MCA_MBMDI = 0x07010A2Dull;
+
+static const uint64_t P9N2_MCA_0_MBMDI = 0x07010A2Dull;
+
+static const uint64_t P9N2_MCA_1_MBMDI = 0x07010A6Dull;
+
+static const uint64_t P9N2_MCA_2_MBMDI = 0x07010AADull;
+
+static const uint64_t P9N2_MCA_3_MBMDI = 0x07010AEDull;
+
+static const uint64_t P9N2_MCA_4_MBMDI = 0x08010A2Dull;
+
+static const uint64_t P9N2_MCA_5_MBMDI = 0x08010A6Dull;
+
+static const uint64_t P9N2_MCA_6_MBMDI = 0x08010AADull;
+
+static const uint64_t P9N2_MCA_7_MBMDI = 0x08010AEDull;
+
+
+static const uint64_t P9N2_MCBIST_MBMPER0Q = 0x0701236Cull;
+
+static const uint64_t P9N2_MCBIST_0_MBMPER0Q = 0x0701236Cull;
+
+static const uint64_t P9N2_MCBIST_1_MBMPER0Q = 0x0801236Cull;
+
+
+static const uint64_t P9N2_MCBIST_MBMPER1Q = 0x07012371ull;
+
+static const uint64_t P9N2_MCBIST_0_MBMPER1Q = 0x07012371ull;
+
+static const uint64_t P9N2_MCBIST_1_MBMPER1Q = 0x08012371ull;
+
+
+static const uint64_t P9N2_MCBIST_MBMPER2Q = 0x07012376ull;
+
+static const uint64_t P9N2_MCBIST_0_MBMPER2Q = 0x07012376ull;
+
+static const uint64_t P9N2_MCBIST_1_MBMPER2Q = 0x08012376ull;
+
+
+static const uint64_t P9N2_MCBIST_MBMPER3Q = 0x0701237Bull;
+
+static const uint64_t P9N2_MCBIST_0_MBMPER3Q = 0x0701237Bull;
+
+static const uint64_t P9N2_MCBIST_1_MBMPER3Q = 0x0801237Bull;
+
+
+static const uint64_t P9N2_MCBIST_MBNCER0Q = 0x0701236Aull;
+
+static const uint64_t P9N2_MCBIST_0_MBNCER0Q = 0x0701236Aull;
+
+static const uint64_t P9N2_MCBIST_1_MBNCER0Q = 0x0801236Aull;
+
+
+static const uint64_t P9N2_MCBIST_MBNCER1Q = 0x0701236Full;
+
+static const uint64_t P9N2_MCBIST_0_MBNCER1Q = 0x0701236Full;
+
+static const uint64_t P9N2_MCBIST_1_MBNCER1Q = 0x0801236Full;
+
+
+static const uint64_t P9N2_MCBIST_MBNCER2Q = 0x07012374ull;
+
+static const uint64_t P9N2_MCBIST_0_MBNCER2Q = 0x07012374ull;
+
+static const uint64_t P9N2_MCBIST_1_MBNCER2Q = 0x08012374ull;
+
+
+static const uint64_t P9N2_MCBIST_MBNCER3Q = 0x07012379ull;
+
+static const uint64_t P9N2_MCBIST_0_MBNCER3Q = 0x07012379ull;
+
+static const uint64_t P9N2_MCBIST_1_MBNCER3Q = 0x08012379ull;
+
+
+static const uint64_t P9N2_MCBIST_MBRCER0Q = 0x0701236Bull;
+
+static const uint64_t P9N2_MCBIST_0_MBRCER0Q = 0x0701236Bull;
+
+static const uint64_t P9N2_MCBIST_1_MBRCER0Q = 0x0801236Bull;
+
+
+static const uint64_t P9N2_MCBIST_MBRCER1Q = 0x07012370ull;
+
+static const uint64_t P9N2_MCBIST_0_MBRCER1Q = 0x07012370ull;
+
+static const uint64_t P9N2_MCBIST_1_MBRCER1Q = 0x08012370ull;
+
+
+static const uint64_t P9N2_MCBIST_MBRCER2Q = 0x07012375ull;
+
+static const uint64_t P9N2_MCBIST_0_MBRCER2Q = 0x07012375ull;
+
+static const uint64_t P9N2_MCBIST_1_MBRCER2Q = 0x08012375ull;
+
+
+static const uint64_t P9N2_MCBIST_MBRCER3Q = 0x0701237Aull;
+
+static const uint64_t P9N2_MCBIST_0_MBRCER3Q = 0x0701237Aull;
+
+static const uint64_t P9N2_MCBIST_1_MBRCER3Q = 0x0801237Aull;
+
+
+static const uint64_t P9N2_MCBIST_MBSEC0Q = 0x07012355ull;
+
+static const uint64_t P9N2_MCBIST_0_MBSEC0Q = 0x07012355ull;
+
+static const uint64_t P9N2_MCBIST_1_MBSEC0Q = 0x08012355ull;
+
+
+static const uint64_t P9N2_MCBIST_MBSEC1Q = 0x07012356ull;
+
+static const uint64_t P9N2_MCBIST_0_MBSEC1Q = 0x07012356ull;
+
+static const uint64_t P9N2_MCBIST_1_MBSEC1Q = 0x08012356ull;
+
+
+static const uint64_t P9N2_MCBIST_MBSEVR0Q = 0x0701237Eull;
+
+static const uint64_t P9N2_MCBIST_0_MBSEVR0Q = 0x0701237Eull;
+
+static const uint64_t P9N2_MCBIST_1_MBSEVR0Q = 0x0801237Eull;
+
+
+static const uint64_t P9N2_MCBIST_MBSEVR1Q = 0x0701237Full;
+
+static const uint64_t P9N2_MCBIST_0_MBSEVR1Q = 0x0701237Full;
+
+static const uint64_t P9N2_MCBIST_1_MBSEVR1Q = 0x0801237Full;
+
+
+static const uint64_t P9N2_MCBIST_MBSMODESQ = 0x07012362ull;
+
+static const uint64_t P9N2_MCBIST_0_MBSMODESQ = 0x07012362ull;
+
+static const uint64_t P9N2_MCBIST_1_MBSMODESQ = 0x08012362ull;
+
+
+static const uint64_t P9N2_MCBIST_MBSMSECQ = 0x07012369ull;
+
+static const uint64_t P9N2_MCBIST_0_MBSMSECQ = 0x07012369ull;
+
+static const uint64_t P9N2_MCBIST_1_MBSMSECQ = 0x08012369ull;
+
+
+static const uint64_t P9N2_MCBIST_MBSSYMEC0Q = 0x07012358ull;
+
+static const uint64_t P9N2_MCBIST_0_MBSSYMEC0Q = 0x07012358ull;
+
+static const uint64_t P9N2_MCBIST_1_MBSSYMEC0Q = 0x08012358ull;
+
+
+static const uint64_t P9N2_MCBIST_MBSSYMEC1Q = 0x07012359ull;
+
+static const uint64_t P9N2_MCBIST_0_MBSSYMEC1Q = 0x07012359ull;
+
+static const uint64_t P9N2_MCBIST_1_MBSSYMEC1Q = 0x08012359ull;
+
+
+static const uint64_t P9N2_MCBIST_MBSSYMEC2Q = 0x0701235Aull;
+
+static const uint64_t P9N2_MCBIST_0_MBSSYMEC2Q = 0x0701235Aull;
+
+static const uint64_t P9N2_MCBIST_1_MBSSYMEC2Q = 0x0801235Aull;
+
+
+static const uint64_t P9N2_MCBIST_MBSSYMEC3Q = 0x0701235Bull;
+
+static const uint64_t P9N2_MCBIST_0_MBSSYMEC3Q = 0x0701235Bull;
+
+static const uint64_t P9N2_MCBIST_1_MBSSYMEC3Q = 0x0801235Bull;
+
+
+static const uint64_t P9N2_MCBIST_MBSSYMEC4Q = 0x0701235Cull;
+
+static const uint64_t P9N2_MCBIST_0_MBSSYMEC4Q = 0x0701235Cull;
+
+static const uint64_t P9N2_MCBIST_1_MBSSYMEC4Q = 0x0801235Cull;
+
+
+static const uint64_t P9N2_MCBIST_MBSSYMEC5Q = 0x0701235Dull;
+
+static const uint64_t P9N2_MCBIST_0_MBSSYMEC5Q = 0x0701235Dull;
+
+static const uint64_t P9N2_MCBIST_1_MBSSYMEC5Q = 0x0801235Dull;
+
+
+static const uint64_t P9N2_MCBIST_MBSSYMEC6Q = 0x0701235Eull;
+
+static const uint64_t P9N2_MCBIST_0_MBSSYMEC6Q = 0x0701235Eull;
+
+static const uint64_t P9N2_MCBIST_1_MBSSYMEC6Q = 0x0801235Eull;
+
+
+static const uint64_t P9N2_MCBIST_MBSSYMEC7Q = 0x0701235Full;
+
+static const uint64_t P9N2_MCBIST_0_MBSSYMEC7Q = 0x0701235Full;
+
+static const uint64_t P9N2_MCBIST_1_MBSSYMEC7Q = 0x0801235Full;
+
+
+static const uint64_t P9N2_MCBIST_MBSSYMEC8Q = 0x07012360ull;
+
+static const uint64_t P9N2_MCBIST_0_MBSSYMEC8Q = 0x07012360ull;
+
+static const uint64_t P9N2_MCBIST_1_MBSSYMEC8Q = 0x08012360ull;
+
+
+static const uint64_t P9N2_MCBIST_MBSTRQ = 0x07012357ull;
+
+static const uint64_t P9N2_MCBIST_0_MBSTRQ = 0x07012357ull;
+
+static const uint64_t P9N2_MCBIST_1_MBSTRQ = 0x08012357ull;
+
+
+static const uint64_t P9N2_MCBIST_MBUER0Q = 0x0701236Dull;
+
+static const uint64_t P9N2_MCBIST_0_MBUER0Q = 0x0701236Dull;
+
+static const uint64_t P9N2_MCBIST_1_MBUER0Q = 0x0801236Dull;
+
+
+static const uint64_t P9N2_MCBIST_MBUER1Q = 0x07012372ull;
+
+static const uint64_t P9N2_MCBIST_0_MBUER1Q = 0x07012372ull;
+
+static const uint64_t P9N2_MCBIST_1_MBUER1Q = 0x08012372ull;
+
+
+static const uint64_t P9N2_MCBIST_MBUER2Q = 0x07012377ull;
+
+static const uint64_t P9N2_MCBIST_0_MBUER2Q = 0x07012377ull;
+
+static const uint64_t P9N2_MCBIST_1_MBUER2Q = 0x08012377ull;
+
+
+static const uint64_t P9N2_MCBIST_MBUER3Q = 0x0701237Cull;
+
+static const uint64_t P9N2_MCBIST_0_MBUER3Q = 0x0701237Cull;
+
+static const uint64_t P9N2_MCBIST_1_MBUER3Q = 0x0801237Cull;
+
+
+static const uint64_t P9N2_MCS_0_PORT02_MCAMOC = 0x05010825ull;
+
+static const uint64_t P9N2_MCS_0_PORT13_MCAMOC = 0x05010835ull;
+
+static const uint64_t P9N2_MCS_1_PORT02_MCAMOC = 0x050108A5ull;
+
+static const uint64_t P9N2_MCS_1_PORT13_MCAMOC = 0x050108B5ull;
+
+static const uint64_t P9N2_MCS_2_PORT02_MCAMOC = 0x03010825ull;
+
+static const uint64_t P9N2_MCS_2_PORT13_MCAMOC = 0x03010835ull;
+
+static const uint64_t P9N2_MCS_3_PORT02_MCAMOC = 0x030108A5ull;
+
+static const uint64_t P9N2_MCS_3_PORT13_MCAMOC = 0x030108B5ull;
+
+static const uint64_t P9N2_MCS_PORT02_MCAMOC = 0x05010825ull;
+
+static const uint64_t P9N2_MCS_PORT13_MCAMOC = 0x05010835ull;
+
+
+static const uint64_t P9N2_MCBIST_MCBACQ = 0x070123D5ull;
+
+static const uint64_t P9N2_MCBIST_0_MCBACQ = 0x070123D5ull;
+
+static const uint64_t P9N2_MCBIST_1_MCBACQ = 0x080123D5ull;
+
+
+static const uint64_t P9N2_MCBIST_MCBAGRAQ = 0x070123D6ull;
+
+static const uint64_t P9N2_MCBIST_0_MCBAGRAQ = 0x070123D6ull;
+
+static const uint64_t P9N2_MCBIST_1_MCBAGRAQ = 0x080123D6ull;
+
+
+static const uint64_t P9N2_MCBIST_MCBAMR0A0Q = 0x070123C8ull;
+
+static const uint64_t P9N2_MCBIST_0_MCBAMR0A0Q = 0x070123C8ull;
+
+static const uint64_t P9N2_MCBIST_1_MCBAMR0A0Q = 0x080123C8ull;
+
+
+static const uint64_t P9N2_MCBIST_MCBAMR1A0Q = 0x070123C9ull;
+
+static const uint64_t P9N2_MCBIST_0_MCBAMR1A0Q = 0x070123C9ull;
+
+static const uint64_t P9N2_MCBIST_1_MCBAMR1A0Q = 0x080123C9ull;
+
+
+static const uint64_t P9N2_MCBIST_MCBAMR2A0Q = 0x070123CAull;
+
+static const uint64_t P9N2_MCBIST_0_MCBAMR2A0Q = 0x070123CAull;
+
+static const uint64_t P9N2_MCBIST_1_MCBAMR2A0Q = 0x080123CAull;
+
+
+static const uint64_t P9N2_MCBIST_MCBAMR3A0Q = 0x070123CBull;
+
+static const uint64_t P9N2_MCBIST_0_MCBAMR3A0Q = 0x070123CBull;
+
+static const uint64_t P9N2_MCBIST_1_MCBAMR3A0Q = 0x080123CBull;
+
+
+static const uint64_t P9N2_MCBIST_MCBCFGQ = 0x070123E0ull;
+
+static const uint64_t P9N2_MCBIST_0_MCBCFGQ = 0x070123E0ull;
+
+static const uint64_t P9N2_MCBIST_1_MCBCFGQ = 0x080123E0ull;
+
+
+static const uint64_t P9N2_MCA_MCBCM = 0x07010A2Cull;
+
+static const uint64_t P9N2_MCA_0_MCBCM = 0x07010A2Cull;
+
+static const uint64_t P9N2_MCA_1_MCBCM = 0x07010A6Cull;
+
+static const uint64_t P9N2_MCA_2_MCBCM = 0x07010AACull;
+
+static const uint64_t P9N2_MCA_3_MCBCM = 0x07010AECull;
+
+static const uint64_t P9N2_MCA_4_MCBCM = 0x08010A2Cull;
+
+static const uint64_t P9N2_MCA_5_MCBCM = 0x08010A6Cull;
+
+static const uint64_t P9N2_MCA_6_MCBCM = 0x08010AACull;
+
+static const uint64_t P9N2_MCA_7_MCBCM = 0x08010AECull;
+
+
+static const uint64_t P9N2_MCBIST_MCBDRCRQ = 0x070123BDull;
+
+static const uint64_t P9N2_MCBIST_0_MCBDRCRQ = 0x070123BDull;
+
+static const uint64_t P9N2_MCBIST_1_MCBDRCRQ = 0x080123BDull;
+
+
+static const uint64_t P9N2_MCBIST_MCBDRSRQ = 0x070123BCull;
+
+static const uint64_t P9N2_MCBIST_0_MCBDRSRQ = 0x070123BCull;
+
+static const uint64_t P9N2_MCBIST_1_MCBDRSRQ = 0x080123BCull;
+
+
+static const uint64_t P9N2_MCBIST_MCBEA0Q = 0x070123CEull;
+
+static const uint64_t P9N2_MCBIST_0_MCBEA0Q = 0x070123CEull;
+
+static const uint64_t P9N2_MCBIST_1_MCBEA0Q = 0x080123CEull;
+
+
+static const uint64_t P9N2_MCBIST_MCBEA1Q = 0x070123CFull;
+
+static const uint64_t P9N2_MCBIST_0_MCBEA1Q = 0x070123CFull;
+
+static const uint64_t P9N2_MCBIST_1_MCBEA1Q = 0x080123CFull;
+
+
+static const uint64_t P9N2_MCBIST_MCBEA2Q = 0x070123D2ull;
+
+static const uint64_t P9N2_MCBIST_0_MCBEA2Q = 0x070123D2ull;
+
+static const uint64_t P9N2_MCBIST_1_MCBEA2Q = 0x080123D2ull;
+
+
+static const uint64_t P9N2_MCBIST_MCBEA3Q = 0x070123D3ull;
+
+static const uint64_t P9N2_MCBIST_0_MCBEA3Q = 0x070123D3ull;
+
+static const uint64_t P9N2_MCBIST_1_MCBEA3Q = 0x080123D3ull;
+
+
+static const uint64_t P9N2_MCBIST_MCBFD0Q = 0x070123BEull;
+
+static const uint64_t P9N2_MCBIST_0_MCBFD0Q = 0x070123BEull;
+
+static const uint64_t P9N2_MCBIST_1_MCBFD0Q = 0x080123BEull;
+
+
+static const uint64_t P9N2_MCBIST_MCBFD1Q = 0x070123BFull;
+
+static const uint64_t P9N2_MCBIST_0_MCBFD1Q = 0x070123BFull;
+
+static const uint64_t P9N2_MCBIST_1_MCBFD1Q = 0x080123BFull;
+
+
+static const uint64_t P9N2_MCBIST_MCBFD2Q = 0x070123C0ull;
+
+static const uint64_t P9N2_MCBIST_0_MCBFD2Q = 0x070123C0ull;
+
+static const uint64_t P9N2_MCBIST_1_MCBFD2Q = 0x080123C0ull;
+
+
+static const uint64_t P9N2_MCBIST_MCBFD3Q = 0x070123C1ull;
+
+static const uint64_t P9N2_MCBIST_0_MCBFD3Q = 0x070123C1ull;
+
+static const uint64_t P9N2_MCBIST_1_MCBFD3Q = 0x080123C1ull;
+
+
+static const uint64_t P9N2_MCBIST_MCBFD4Q = 0x070123C2ull;
+
+static const uint64_t P9N2_MCBIST_0_MCBFD4Q = 0x070123C2ull;
+
+static const uint64_t P9N2_MCBIST_1_MCBFD4Q = 0x080123C2ull;
+
+
+static const uint64_t P9N2_MCBIST_MCBFD5Q = 0x070123C3ull;
+
+static const uint64_t P9N2_MCBIST_0_MCBFD5Q = 0x070123C3ull;
+
+static const uint64_t P9N2_MCBIST_1_MCBFD5Q = 0x080123C3ull;
+
+
+static const uint64_t P9N2_MCBIST_MCBFD6Q = 0x070123C4ull;
+
+static const uint64_t P9N2_MCBIST_0_MCBFD6Q = 0x070123C4ull;
+
+static const uint64_t P9N2_MCBIST_1_MCBFD6Q = 0x080123C4ull;
+
+
+static const uint64_t P9N2_MCBIST_MCBFD7Q = 0x070123C5ull;
+
+static const uint64_t P9N2_MCBIST_0_MCBFD7Q = 0x070123C5ull;
+
+static const uint64_t P9N2_MCBIST_1_MCBFD7Q = 0x080123C5ull;
+
+
+static const uint64_t P9N2_MCBIST_MCBFDQ = 0x070123C6ull;
+
+static const uint64_t P9N2_MCBIST_0_MCBFDQ = 0x070123C6ull;
+
+static const uint64_t P9N2_MCBIST_1_MCBFDQ = 0x080123C6ull;
+
+
+static const uint64_t P9N2_MCBIST_MCBISTFIRACT0 = 0x07012306ull;
+
+static const uint64_t P9N2_MCBIST_0_MCBISTFIRACT0 = 0x07012306ull;
+
+static const uint64_t P9N2_MCBIST_1_MCBISTFIRACT0 = 0x08012306ull;
+
+
+static const uint64_t P9N2_MCBIST_MCBISTFIRACT1 = 0x07012307ull;
+
+static const uint64_t P9N2_MCBIST_0_MCBISTFIRACT1 = 0x07012307ull;
+
+static const uint64_t P9N2_MCBIST_1_MCBISTFIRACT1 = 0x08012307ull;
+
+
+static const uint64_t P9N2_MCBIST_MCBISTFIRMASK = 0x07012303ull;
+
+static const uint64_t P9N2_MCBIST_MCBISTFIRMASK_AND = 0x07012304ull;
+
+static const uint64_t P9N2_MCBIST_MCBISTFIRMASK_OR = 0x07012305ull;
+
+static const uint64_t P9N2_MCBIST_0_MCBISTFIRMASK = 0x07012303ull;
+
+static const uint64_t P9N2_MCBIST_0_MCBISTFIRMASK_AND = 0x07012304ull;
+
+static const uint64_t P9N2_MCBIST_0_MCBISTFIRMASK_OR = 0x07012305ull;
+
+static const uint64_t P9N2_MCBIST_1_MCBISTFIRMASK = 0x08012303ull;
+
+static const uint64_t P9N2_MCBIST_1_MCBISTFIRMASK_AND = 0x08012304ull;
+
+static const uint64_t P9N2_MCBIST_1_MCBISTFIRMASK_OR = 0x08012305ull;
+
+
+static const uint64_t P9N2_MCBIST_MCBISTFIRQ = 0x07012300ull;
+
+static const uint64_t P9N2_MCBIST_MCBISTFIRQ_AND = 0x07012301ull;
+
+static const uint64_t P9N2_MCBIST_MCBISTFIRQ_OR = 0x07012302ull;
+
+static const uint64_t P9N2_MCBIST_0_MCBISTFIRQ = 0x07012300ull;
+
+static const uint64_t P9N2_MCBIST_0_MCBISTFIRQ_AND = 0x07012301ull;
+
+static const uint64_t P9N2_MCBIST_0_MCBISTFIRQ_OR = 0x07012302ull;
+
+static const uint64_t P9N2_MCBIST_1_MCBISTFIRQ = 0x08012300ull;
+
+static const uint64_t P9N2_MCBIST_1_MCBISTFIRQ_AND = 0x08012301ull;
+
+static const uint64_t P9N2_MCBIST_1_MCBISTFIRQ_OR = 0x08012302ull;
+
+
+static const uint64_t P9N2_MCBIST_MCBISTFIRWOF = 0x07012308ull;
+
+static const uint64_t P9N2_MCBIST_0_MCBISTFIRWOF = 0x07012308ull;
+
+static const uint64_t P9N2_MCBIST_1_MCBISTFIRWOF = 0x08012308ull;
+
+
+static const uint64_t P9N2_MCBIST_MCBLFSRA0Q = 0x070123D4ull;
+
+static const uint64_t P9N2_MCBIST_0_MCBLFSRA0Q = 0x070123D4ull;
+
+static const uint64_t P9N2_MCBIST_1_MCBLFSRA0Q = 0x080123D4ull;
+
+
+static const uint64_t P9N2_MCBIST_MCBMCATQ = 0x070123D7ull;
+
+static const uint64_t P9N2_MCBIST_0_MCBMCATQ = 0x070123D7ull;
+
+static const uint64_t P9N2_MCBIST_1_MCBMCATQ = 0x080123D7ull;
+
+
+static const uint64_t P9N2_MCBIST_MCBMR0Q = 0x070123A8ull;
+
+static const uint64_t P9N2_MCBIST_0_MCBMR0Q = 0x070123A8ull;
+
+static const uint64_t P9N2_MCBIST_1_MCBMR0Q = 0x080123A8ull;
+
+
+static const uint64_t P9N2_MCBIST_MCBMR1Q = 0x070123A9ull;
+
+static const uint64_t P9N2_MCBIST_0_MCBMR1Q = 0x070123A9ull;
+
+static const uint64_t P9N2_MCBIST_1_MCBMR1Q = 0x080123A9ull;
+
+
+static const uint64_t P9N2_MCBIST_MCBMR2Q = 0x070123AAull;
+
+static const uint64_t P9N2_MCBIST_0_MCBMR2Q = 0x070123AAull;
+
+static const uint64_t P9N2_MCBIST_1_MCBMR2Q = 0x080123AAull;
+
+
+static const uint64_t P9N2_MCBIST_MCBMR3Q = 0x070123ABull;
+
+static const uint64_t P9N2_MCBIST_0_MCBMR3Q = 0x070123ABull;
+
+static const uint64_t P9N2_MCBIST_1_MCBMR3Q = 0x080123ABull;
+
+
+static const uint64_t P9N2_MCBIST_MCBMR4Q = 0x070123ACull;
+
+static const uint64_t P9N2_MCBIST_0_MCBMR4Q = 0x070123ACull;
+
+static const uint64_t P9N2_MCBIST_1_MCBMR4Q = 0x080123ACull;
+
+
+static const uint64_t P9N2_MCBIST_MCBMR5Q = 0x070123ADull;
+
+static const uint64_t P9N2_MCBIST_0_MCBMR5Q = 0x070123ADull;
+
+static const uint64_t P9N2_MCBIST_1_MCBMR5Q = 0x080123ADull;
+
+
+static const uint64_t P9N2_MCBIST_MCBMR6Q = 0x070123AEull;
+
+static const uint64_t P9N2_MCBIST_0_MCBMR6Q = 0x070123AEull;
+
+static const uint64_t P9N2_MCBIST_1_MCBMR6Q = 0x080123AEull;
+
+
+static const uint64_t P9N2_MCBIST_MCBMR7Q = 0x070123DFull;
+
+static const uint64_t P9N2_MCBIST_0_MCBMR7Q = 0x070123DFull;
+
+static const uint64_t P9N2_MCBIST_1_MCBMR7Q = 0x080123DFull;
+
+
+static const uint64_t P9N2_MCBIST_MCBPARMQ = 0x070123AFull;
+
+static const uint64_t P9N2_MCBIST_0_MCBPARMQ = 0x070123AFull;
+
+static const uint64_t P9N2_MCBIST_1_MCBPARMQ = 0x080123AFull;
+
+
+static const uint64_t P9N2_MCBIST_MCBRCRQ = 0x070123B1ull;
+
+static const uint64_t P9N2_MCBIST_0_MCBRCRQ = 0x070123B1ull;
+
+static const uint64_t P9N2_MCBIST_1_MCBRCRQ = 0x080123B1ull;
+
+
+static const uint64_t P9N2_MCBIST_MCBRDS0Q = 0x070123B2ull;
+
+static const uint64_t P9N2_MCBIST_0_MCBRDS0Q = 0x070123B2ull;
+
+static const uint64_t P9N2_MCBIST_1_MCBRDS0Q = 0x080123B2ull;
+
+
+static const uint64_t P9N2_MCBIST_MCBRDS1Q = 0x070123B3ull;
+
+static const uint64_t P9N2_MCBIST_0_MCBRDS1Q = 0x070123B3ull;
+
+static const uint64_t P9N2_MCBIST_1_MCBRDS1Q = 0x080123B3ull;
+
+
+static const uint64_t P9N2_MCBIST_MCBSA0Q = 0x070123CCull;
+
+static const uint64_t P9N2_MCBIST_0_MCBSA0Q = 0x070123CCull;
+
+static const uint64_t P9N2_MCBIST_1_MCBSA0Q = 0x080123CCull;
+
+
+static const uint64_t P9N2_MCBIST_MCBSA1Q = 0x070123CDull;
+
+static const uint64_t P9N2_MCBIST_0_MCBSA1Q = 0x070123CDull;
+
+static const uint64_t P9N2_MCBIST_1_MCBSA1Q = 0x080123CDull;
+
+
+static const uint64_t P9N2_MCBIST_MCBSA2Q = 0x070123D0ull;
+
+static const uint64_t P9N2_MCBIST_0_MCBSA2Q = 0x070123D0ull;
+
+static const uint64_t P9N2_MCBIST_1_MCBSA2Q = 0x080123D0ull;
+
+
+static const uint64_t P9N2_MCBIST_MCBSA3Q = 0x070123D1ull;
+
+static const uint64_t P9N2_MCBIST_0_MCBSA3Q = 0x070123D1ull;
+
+static const uint64_t P9N2_MCBIST_1_MCBSA3Q = 0x080123D1ull;
+
+
+static const uint64_t P9N2_MCBIST_MCBSTATQ = 0x07012366ull;
+
+static const uint64_t P9N2_MCBIST_0_MCBSTATQ = 0x07012366ull;
+
+static const uint64_t P9N2_MCBIST_1_MCBSTATQ = 0x08012366ull;
+
+
+static const uint64_t P9N2_MCS_0_PORT02_MCBUSYQ = 0x05010827ull;
+
+static const uint64_t P9N2_MCS_0_PORT13_MCBUSYQ = 0x05010837ull;
+
+static const uint64_t P9N2_MCS_1_PORT02_MCBUSYQ = 0x050108A7ull;
+
+static const uint64_t P9N2_MCS_1_PORT13_MCBUSYQ = 0x050108B7ull;
+
+static const uint64_t P9N2_MCS_2_PORT02_MCBUSYQ = 0x03010827ull;
+
+static const uint64_t P9N2_MCS_2_PORT13_MCBUSYQ = 0x03010837ull;
+
+static const uint64_t P9N2_MCS_3_PORT02_MCBUSYQ = 0x030108A7ull;
+
+static const uint64_t P9N2_MCS_3_PORT13_MCBUSYQ = 0x030108B7ull;
+
+static const uint64_t P9N2_MCS_PORT02_MCBUSYQ = 0x05010827ull;
+
+static const uint64_t P9N2_MCS_PORT13_MCBUSYQ = 0x05010837ull;
+
+
+static const uint64_t P9N2_MCBIST_MCB_CNTLQ = 0x070123DBull;
+
+static const uint64_t P9N2_MCBIST_0_MCB_CNTLQ = 0x070123DBull;
+
+static const uint64_t P9N2_MCBIST_1_MCB_CNTLQ = 0x080123DBull;
+
+
+static const uint64_t P9N2_MCBIST_MCB_CNTLSTATQ = 0x070123DCull;
+
+static const uint64_t P9N2_MCBIST_0_MCB_CNTLSTATQ = 0x070123DCull;
+
+static const uint64_t P9N2_MCBIST_1_MCB_CNTLSTATQ = 0x080123DCull;
+
+
+static const uint64_t P9N2_MCS_MCDBG0 = 0x05010816ull;
+
+static const uint64_t P9N2_MCS_0_MCDBG0 = 0x05010816ull;
+
+static const uint64_t P9N2_MCS_1_MCDBG0 = 0x05010896ull;
+
+static const uint64_t P9N2_MCS_2_MCDBG0 = 0x03010816ull;
+
+static const uint64_t P9N2_MCS_3_MCDBG0 = 0x03010896ull;
+
+
+static const uint64_t P9N2_MCS_MCDBG1 = 0x05010817ull;
+
+static const uint64_t P9N2_MCS_0_MCDBG1 = 0x05010817ull;
+
+static const uint64_t P9N2_MCS_1_MCDBG1 = 0x05010897ull;
+
+static const uint64_t P9N2_MCS_2_MCDBG1 = 0x03010817ull;
+
+static const uint64_t P9N2_MCS_3_MCDBG1 = 0x03010897ull;
+
+
+static const uint64_t P9N2_MCS_0_PORT02_MCEBUSCL = 0x05010829ull;
+
+static const uint64_t P9N2_MCS_0_PORT13_MCEBUSCL = 0x05010839ull;
+
+static const uint64_t P9N2_MCS_1_PORT02_MCEBUSCL = 0x050108A9ull;
+
+static const uint64_t P9N2_MCS_1_PORT13_MCEBUSCL = 0x050108B9ull;
+
+static const uint64_t P9N2_MCS_2_PORT02_MCEBUSCL = 0x03010829ull;
+
+static const uint64_t P9N2_MCS_2_PORT13_MCEBUSCL = 0x03010839ull;
+
+static const uint64_t P9N2_MCS_3_PORT02_MCEBUSCL = 0x030108A9ull;
+
+static const uint64_t P9N2_MCS_3_PORT13_MCEBUSCL = 0x030108B9ull;
+
+static const uint64_t P9N2_MCS_PORT02_MCEBUSCL = 0x05010829ull;
+
+static const uint64_t P9N2_MCS_PORT13_MCEBUSCL = 0x05010839ull;
+
+
+static const uint64_t P9N2_MCS_0_PORT13_MCEBUSEN0 = 0x0501083Cull;
+
+static const uint64_t P9N2_MCS_1_PORT13_MCEBUSEN0 = 0x050108BCull;
+
+static const uint64_t P9N2_MCS_2_PORT13_MCEBUSEN0 = 0x0301083Cull;
+
+static const uint64_t P9N2_MCS_3_PORT13_MCEBUSEN0 = 0x030108BCull;
+
+static const uint64_t P9N2_MCS_PORT13_MCEBUSEN0 = 0x0501083Cull;
+
+
+static const uint64_t P9N2_MCS_0_PORT13_MCEBUSEN1 = 0x0501083Dull;
+
+static const uint64_t P9N2_MCS_1_PORT13_MCEBUSEN1 = 0x050108BDull;
+
+static const uint64_t P9N2_MCS_2_PORT13_MCEBUSEN1 = 0x0301083Dull;
+
+static const uint64_t P9N2_MCS_3_PORT13_MCEBUSEN1 = 0x030108BDull;
+
+static const uint64_t P9N2_MCS_PORT13_MCEBUSEN1 = 0x0501083Dull;
+
+
+static const uint64_t P9N2_MCS_0_PORT13_MCEBUSEN2 = 0x0501083Eull;
+
+static const uint64_t P9N2_MCS_1_PORT13_MCEBUSEN2 = 0x050108BEull;
+
+static const uint64_t P9N2_MCS_2_PORT13_MCEBUSEN2 = 0x0301083Eull;
+
+static const uint64_t P9N2_MCS_3_PORT13_MCEBUSEN2 = 0x030108BEull;
+
+static const uint64_t P9N2_MCS_PORT13_MCEBUSEN2 = 0x0501083Eull;
+
+
+static const uint64_t P9N2_MCS_0_PORT13_MCEBUSEN3 = 0x0501083Full;
+
+static const uint64_t P9N2_MCS_1_PORT13_MCEBUSEN3 = 0x050108BFull;
+
+static const uint64_t P9N2_MCS_2_PORT13_MCEBUSEN3 = 0x0301083Full;
+
+static const uint64_t P9N2_MCS_3_PORT13_MCEBUSEN3 = 0x030108BFull;
+
+static const uint64_t P9N2_MCS_PORT13_MCEBUSEN3 = 0x0501083Full;
+
+
+static const uint64_t P9N2_MCS_0_PORT02_MCEPSQ = 0x05010826ull;
+
+static const uint64_t P9N2_MCS_0_PORT13_MCEPSQ = 0x05010836ull;
+
+static const uint64_t P9N2_MCS_1_PORT02_MCEPSQ = 0x050108A6ull;
+
+static const uint64_t P9N2_MCS_1_PORT13_MCEPSQ = 0x050108B6ull;
+
+static const uint64_t P9N2_MCS_2_PORT02_MCEPSQ = 0x03010826ull;
+
+static const uint64_t P9N2_MCS_2_PORT13_MCEPSQ = 0x03010836ull;
+
+static const uint64_t P9N2_MCS_3_PORT02_MCEPSQ = 0x030108A6ull;
+
+static const uint64_t P9N2_MCS_3_PORT13_MCEPSQ = 0x030108B6ull;
+
+static const uint64_t P9N2_MCS_PORT02_MCEPSQ = 0x05010826ull;
+
+static const uint64_t P9N2_MCS_PORT13_MCEPSQ = 0x05010836ull;
+
+
+static const uint64_t P9N2_MCS_MCERPT0 = 0x0501081Eull;
+
+static const uint64_t P9N2_MCS_0_MCERPT0 = 0x0501081Eull;
+
+static const uint64_t P9N2_MCS_1_MCERPT0 = 0x0501089Eull;
+
+static const uint64_t P9N2_MCS_2_MCERPT0 = 0x0301081Eull;
+
+static const uint64_t P9N2_MCS_3_MCERPT0 = 0x0301089Eull;
+
+
+static const uint64_t P9N2_MCS_MCERPT1 = 0x0501081Full;
+
+static const uint64_t P9N2_MCS_0_MCERPT1 = 0x0501081Full;
+
+static const uint64_t P9N2_MCS_1_MCERPT1 = 0x0501089Full;
+
+static const uint64_t P9N2_MCS_2_MCERPT1 = 0x0301081Full;
+
+static const uint64_t P9N2_MCS_3_MCERPT1 = 0x0301089Full;
+
+
+static const uint64_t P9N2_MCS_MCERPT2 = 0x0501081Aull;
+
+static const uint64_t P9N2_MCS_0_MCERPT2 = 0x0501081Aull;
+
+static const uint64_t P9N2_MCS_1_MCERPT2 = 0x0501089Aull;
+
+static const uint64_t P9N2_MCS_2_MCERPT2 = 0x0301081Aull;
+
+static const uint64_t P9N2_MCS_3_MCERPT2 = 0x0301089Aull;
+
+
+static const uint64_t P9N2_MCS_0_PORT02_MCERRINJ = 0x05010828ull;
+
+static const uint64_t P9N2_MCS_0_PORT13_MCERRINJ = 0x05010838ull;
+
+static const uint64_t P9N2_MCS_1_PORT02_MCERRINJ = 0x050108A8ull;
+
+static const uint64_t P9N2_MCS_1_PORT13_MCERRINJ = 0x050108B8ull;
+
+static const uint64_t P9N2_MCS_2_PORT02_MCERRINJ = 0x03010828ull;
+
+static const uint64_t P9N2_MCS_2_PORT13_MCERRINJ = 0x03010838ull;
+
+static const uint64_t P9N2_MCS_3_PORT02_MCERRINJ = 0x030108A8ull;
+
+static const uint64_t P9N2_MCS_3_PORT13_MCERRINJ = 0x030108B8ull;
+
+static const uint64_t P9N2_MCS_PORT02_MCERRINJ = 0x05010828ull;
+
+static const uint64_t P9N2_MCS_PORT13_MCERRINJ = 0x05010838ull;
+
+
+static const uint64_t P9N2_MCS_MCFGP = 0x0501080Aull;
+
+static const uint64_t P9N2_MCS_0_MCFGP = 0x0501080Aull;
+
+static const uint64_t P9N2_MCS_1_MCFGP = 0x0501088Aull;
+
+static const uint64_t P9N2_MCS_2_MCFGP = 0x0301080Aull;
+
+static const uint64_t P9N2_MCS_3_MCFGP = 0x0301088Aull;
+
+
+static const uint64_t P9N2_MCS_MCFGPA = 0x0501080Bull;
+
+static const uint64_t P9N2_MCS_0_MCFGPA = 0x0501080Bull;
+
+static const uint64_t P9N2_MCS_1_MCFGPA = 0x0501088Bull;
+
+static const uint64_t P9N2_MCS_2_MCFGPA = 0x0301080Bull;
+
+static const uint64_t P9N2_MCS_3_MCFGPA = 0x0301088Bull;
+
+
+static const uint64_t P9N2_MCS_MCFGPM = 0x0501080Cull;
+
+static const uint64_t P9N2_MCS_0_MCFGPM = 0x0501080Cull;
+
+static const uint64_t P9N2_MCS_1_MCFGPM = 0x0501088Cull;
+
+static const uint64_t P9N2_MCS_2_MCFGPM = 0x0301080Cull;
+
+static const uint64_t P9N2_MCS_3_MCFGPM = 0x0301088Cull;
+
+
+static const uint64_t P9N2_MCS_MCFGPMA = 0x0501080Dull;
+
+static const uint64_t P9N2_MCS_0_MCFGPMA = 0x0501080Dull;
+
+static const uint64_t P9N2_MCS_1_MCFGPMA = 0x0501088Dull;
+
+static const uint64_t P9N2_MCS_2_MCFGPMA = 0x0301080Dull;
+
+static const uint64_t P9N2_MCS_3_MCFGPMA = 0x0301088Dull;
+
+
+static const uint64_t P9N2_MCS_MCFIR = 0x05010800ull;
+
+static const uint64_t P9N2_MCS_MCFIR_AND = 0x05010801ull;
+
+static const uint64_t P9N2_MCS_MCFIR_OR = 0x05010802ull;
+
+static const uint64_t P9N2_MCS_0_MCFIR = 0x05010800ull;
+
+static const uint64_t P9N2_MCS_0_MCFIR_AND = 0x05010801ull;
+
+static const uint64_t P9N2_MCS_0_MCFIR_OR = 0x05010802ull;
+
+static const uint64_t P9N2_MCS_1_MCFIR = 0x05010880ull;
+
+static const uint64_t P9N2_MCS_1_MCFIR_AND = 0x05010881ull;
+
+static const uint64_t P9N2_MCS_1_MCFIR_OR = 0x05010882ull;
+
+static const uint64_t P9N2_MCS_2_MCFIR = 0x03010800ull;
+
+static const uint64_t P9N2_MCS_2_MCFIR_AND = 0x03010801ull;
+
+static const uint64_t P9N2_MCS_2_MCFIR_OR = 0x03010802ull;
+
+static const uint64_t P9N2_MCS_3_MCFIR = 0x03010880ull;
+
+static const uint64_t P9N2_MCS_3_MCFIR_AND = 0x03010881ull;
+
+static const uint64_t P9N2_MCS_3_MCFIR_OR = 0x03010882ull;
+
+
+static const uint64_t P9N2_MCS_MCFIRACT0 = 0x05010806ull;
+
+static const uint64_t P9N2_MCS_0_MCFIRACT0 = 0x05010806ull;
+
+static const uint64_t P9N2_MCS_1_MCFIRACT0 = 0x05010886ull;
+
+static const uint64_t P9N2_MCS_2_MCFIRACT0 = 0x03010806ull;
+
+static const uint64_t P9N2_MCS_3_MCFIRACT0 = 0x03010886ull;
+
+
+static const uint64_t P9N2_MCS_MCFIRACT1 = 0x05010807ull;
+
+static const uint64_t P9N2_MCS_0_MCFIRACT1 = 0x05010807ull;
+
+static const uint64_t P9N2_MCS_1_MCFIRACT1 = 0x05010887ull;
+
+static const uint64_t P9N2_MCS_2_MCFIRACT1 = 0x03010807ull;
+
+static const uint64_t P9N2_MCS_3_MCFIRACT1 = 0x03010887ull;
+
+
+static const uint64_t P9N2_MCS_MCFIRMASK = 0x05010803ull;
+
+static const uint64_t P9N2_MCS_MCFIRMASK_AND = 0x05010804ull;
+
+static const uint64_t P9N2_MCS_MCFIRMASK_OR = 0x05010805ull;
+
+static const uint64_t P9N2_MCS_0_MCFIRMASK = 0x05010803ull;
+
+static const uint64_t P9N2_MCS_0_MCFIRMASK_AND = 0x05010804ull;
+
+static const uint64_t P9N2_MCS_0_MCFIRMASK_OR = 0x05010805ull;
+
+static const uint64_t P9N2_MCS_1_MCFIRMASK = 0x05010883ull;
+
+static const uint64_t P9N2_MCS_1_MCFIRMASK_AND = 0x05010884ull;
+
+static const uint64_t P9N2_MCS_1_MCFIRMASK_OR = 0x05010885ull;
+
+static const uint64_t P9N2_MCS_2_MCFIRMASK = 0x03010803ull;
+
+static const uint64_t P9N2_MCS_2_MCFIRMASK_AND = 0x03010804ull;
+
+static const uint64_t P9N2_MCS_2_MCFIRMASK_OR = 0x03010805ull;
+
+static const uint64_t P9N2_MCS_3_MCFIRMASK = 0x03010883ull;
+
+static const uint64_t P9N2_MCS_3_MCFIRMASK_AND = 0x03010884ull;
+
+static const uint64_t P9N2_MCS_3_MCFIRMASK_OR = 0x03010885ull;
+
+
+static const uint64_t P9N2_MCS_MCFIRWOF = 0x05010808ull;
+
+static const uint64_t P9N2_MCS_0_MCFIRWOF = 0x05010808ull;
+
+static const uint64_t P9N2_MCS_1_MCFIRWOF = 0x05010888ull;
+
+static const uint64_t P9N2_MCS_2_MCFIRWOF = 0x03010808ull;
+
+static const uint64_t P9N2_MCS_3_MCFIRWOF = 0x03010888ull;
+
+
+static const uint64_t P9N2_MCS_MCLFSR = 0x05010814ull;
+
+static const uint64_t P9N2_MCS_0_MCLFSR = 0x05010814ull;
+
+static const uint64_t P9N2_MCS_1_MCLFSR = 0x05010894ull;
+
+static const uint64_t P9N2_MCS_2_MCLFSR = 0x03010814ull;
+
+static const uint64_t P9N2_MCS_3_MCLFSR = 0x03010894ull;
+
+
+static const uint64_t P9N2_MCS_MCMODE0 = 0x05010811ull;
+
+static const uint64_t P9N2_MCS_0_MCMODE0 = 0x05010811ull;
+
+static const uint64_t P9N2_MCS_1_MCMODE0 = 0x05010891ull;
+
+static const uint64_t P9N2_MCS_2_MCMODE0 = 0x03010811ull;
+
+static const uint64_t P9N2_MCS_3_MCMODE0 = 0x03010891ull;
+
+
+static const uint64_t P9N2_MCS_MCMODE1 = 0x05010812ull;
+
+static const uint64_t P9N2_MCS_0_MCMODE1 = 0x05010812ull;
+
+static const uint64_t P9N2_MCS_1_MCMODE1 = 0x05010892ull;
+
+static const uint64_t P9N2_MCS_2_MCMODE1 = 0x03010812ull;
+
+static const uint64_t P9N2_MCS_3_MCMODE1 = 0x03010892ull;
+
+
+static const uint64_t P9N2_MCS_MCMODE2 = 0x05010813ull;
+
+static const uint64_t P9N2_MCS_0_MCMODE2 = 0x05010813ull;
+
+static const uint64_t P9N2_MCS_1_MCMODE2 = 0x05010893ull;
+
+static const uint64_t P9N2_MCS_2_MCMODE2 = 0x03010813ull;
+
+static const uint64_t P9N2_MCS_3_MCMODE2 = 0x03010893ull;
+
+
+static const uint64_t P9N2_MCS_0_PORT02_MCP0XLT0 = 0x05010820ull;
+
+static const uint64_t P9N2_MCS_0_PORT13_MCP0XLT0 = 0x05010830ull;
+
+static const uint64_t P9N2_MCS_1_PORT02_MCP0XLT0 = 0x050108A0ull;
+
+static const uint64_t P9N2_MCS_1_PORT13_MCP0XLT0 = 0x050108B0ull;
+
+static const uint64_t P9N2_MCS_2_PORT02_MCP0XLT0 = 0x03010820ull;
+
+static const uint64_t P9N2_MCS_2_PORT13_MCP0XLT0 = 0x03010830ull;
+
+static const uint64_t P9N2_MCS_3_PORT02_MCP0XLT0 = 0x030108A0ull;
+
+static const uint64_t P9N2_MCS_3_PORT13_MCP0XLT0 = 0x030108B0ull;
+
+static const uint64_t P9N2_MCS_PORT02_MCP0XLT0 = 0x05010820ull;
+
+static const uint64_t P9N2_MCS_PORT13_MCP0XLT0 = 0x05010830ull;
+
+
+static const uint64_t P9N2_MCS_0_PORT02_MCP0XLT1 = 0x05010821ull;
+
+static const uint64_t P9N2_MCS_0_PORT13_MCP0XLT1 = 0x05010831ull;
+
+static const uint64_t P9N2_MCS_1_PORT02_MCP0XLT1 = 0x050108A1ull;
+
+static const uint64_t P9N2_MCS_1_PORT13_MCP0XLT1 = 0x050108B1ull;
+
+static const uint64_t P9N2_MCS_2_PORT02_MCP0XLT1 = 0x03010821ull;
+
+static const uint64_t P9N2_MCS_2_PORT13_MCP0XLT1 = 0x03010831ull;
+
+static const uint64_t P9N2_MCS_3_PORT02_MCP0XLT1 = 0x030108A1ull;
+
+static const uint64_t P9N2_MCS_3_PORT13_MCP0XLT1 = 0x030108B1ull;
+
+static const uint64_t P9N2_MCS_PORT02_MCP0XLT1 = 0x05010821ull;
+
+static const uint64_t P9N2_MCS_PORT13_MCP0XLT1 = 0x05010831ull;
+
+
+static const uint64_t P9N2_MCS_0_PORT02_MCP0XLT2 = 0x05010822ull;
+
+static const uint64_t P9N2_MCS_0_PORT13_MCP0XLT2 = 0x05010832ull;
+
+static const uint64_t P9N2_MCS_1_PORT02_MCP0XLT2 = 0x050108A2ull;
+
+static const uint64_t P9N2_MCS_1_PORT13_MCP0XLT2 = 0x050108B2ull;
+
+static const uint64_t P9N2_MCS_2_PORT02_MCP0XLT2 = 0x03010822ull;
+
+static const uint64_t P9N2_MCS_2_PORT13_MCP0XLT2 = 0x03010832ull;
+
+static const uint64_t P9N2_MCS_3_PORT02_MCP0XLT2 = 0x030108A2ull;
+
+static const uint64_t P9N2_MCS_3_PORT13_MCP0XLT2 = 0x030108B2ull;
+
+static const uint64_t P9N2_MCS_PORT02_MCP0XLT2 = 0x05010822ull;
+
+static const uint64_t P9N2_MCS_PORT13_MCP0XLT2 = 0x05010832ull;
+
+
+static const uint64_t P9N2_MCS_0_PORT02_MCPERF0 = 0x05010823ull;
+
+static const uint64_t P9N2_MCS_0_PORT13_MCPERF0 = 0x05010833ull;
+
+static const uint64_t P9N2_MCS_1_PORT02_MCPERF0 = 0x050108A3ull;
+
+static const uint64_t P9N2_MCS_1_PORT13_MCPERF0 = 0x050108B3ull;
+
+static const uint64_t P9N2_MCS_2_PORT02_MCPERF0 = 0x03010823ull;
+
+static const uint64_t P9N2_MCS_2_PORT13_MCPERF0 = 0x03010833ull;
+
+static const uint64_t P9N2_MCS_3_PORT02_MCPERF0 = 0x030108A3ull;
+
+static const uint64_t P9N2_MCS_3_PORT13_MCPERF0 = 0x030108B3ull;
+
+static const uint64_t P9N2_MCS_PORT02_MCPERF0 = 0x05010823ull;
+
+static const uint64_t P9N2_MCS_PORT13_MCPERF0 = 0x05010833ull;
+
+
+static const uint64_t P9N2_MCS_MCPERF1 = 0x05010810ull;
+
+static const uint64_t P9N2_MCS_0_MCPERF1 = 0x05010810ull;
+
+static const uint64_t P9N2_MCS_1_MCPERF1 = 0x05010890ull;
+
+static const uint64_t P9N2_MCS_2_MCPERF1 = 0x03010810ull;
+
+static const uint64_t P9N2_MCS_3_MCPERF1 = 0x03010890ull;
+
+
+static const uint64_t P9N2_MCS_0_PORT02_MCPERF2 = 0x05010824ull;
+
+static const uint64_t P9N2_MCS_0_PORT13_MCPERF2 = 0x05010834ull;
+
+static const uint64_t P9N2_MCS_1_PORT02_MCPERF2 = 0x050108A4ull;
+
+static const uint64_t P9N2_MCS_1_PORT13_MCPERF2 = 0x050108B4ull;
+
+static const uint64_t P9N2_MCS_2_PORT02_MCPERF2 = 0x03010824ull;
+
+static const uint64_t P9N2_MCS_2_PORT13_MCPERF2 = 0x03010834ull;
+
+static const uint64_t P9N2_MCS_3_PORT02_MCPERF2 = 0x030108A4ull;
+
+static const uint64_t P9N2_MCS_3_PORT13_MCPERF2 = 0x030108B4ull;
+
+static const uint64_t P9N2_MCS_PORT02_MCPERF2 = 0x05010824ull;
+
+static const uint64_t P9N2_MCS_PORT13_MCPERF2 = 0x05010834ull;
+
+
+static const uint64_t P9N2_MCS_0_PORT02_MCPERF3 = 0x0501082Bull;
+
+static const uint64_t P9N2_MCS_0_PORT13_MCPERF3 = 0x0501083Bull;
+
+static const uint64_t P9N2_MCS_1_PORT02_MCPERF3 = 0x050108ABull;
+
+static const uint64_t P9N2_MCS_1_PORT13_MCPERF3 = 0x050108BBull;
+
+static const uint64_t P9N2_MCS_2_PORT02_MCPERF3 = 0x0301082Bull;
+
+static const uint64_t P9N2_MCS_2_PORT13_MCPERF3 = 0x0301083Bull;
+
+static const uint64_t P9N2_MCS_3_PORT02_MCPERF3 = 0x030108ABull;
+
+static const uint64_t P9N2_MCS_3_PORT13_MCPERF3 = 0x030108BBull;
+
+static const uint64_t P9N2_MCS_PORT02_MCPERF3 = 0x0501082Bull;
+
+static const uint64_t P9N2_MCS_PORT13_MCPERF3 = 0x0501083Bull;
+
+
+static const uint64_t P9N2_MCS_MCRSVD19 = 0x05010819ull;
+
+static const uint64_t P9N2_MCS_0_MCRSVD19 = 0x05010819ull;
+
+static const uint64_t P9N2_MCS_1_MCRSVD19 = 0x05010899ull;
+
+static const uint64_t P9N2_MCS_2_MCRSVD19 = 0x03010819ull;
+
+static const uint64_t P9N2_MCS_3_MCRSVD19 = 0x03010899ull;
+
+
+static const uint64_t P9N2_MCS_0_PORT02_MCRSVD2F = 0x0501082Full;
+
+static const uint64_t P9N2_MCS_1_PORT02_MCRSVD2F = 0x050108AFull;
+
+static const uint64_t P9N2_MCS_2_PORT02_MCRSVD2F = 0x0301082Full;
+
+static const uint64_t P9N2_MCS_3_PORT02_MCRSVD2F = 0x030108AFull;
+
+static const uint64_t P9N2_MCS_PORT02_MCRSVD2F = 0x0501082Full;
+
+
+static const uint64_t P9N2_MCS_MCRSVDE = 0x0501080Eull;
+
+static const uint64_t P9N2_MCS_0_MCRSVDE = 0x0501080Eull;
+
+static const uint64_t P9N2_MCS_1_MCRSVDE = 0x0501088Eull;
+
+static const uint64_t P9N2_MCS_2_MCRSVDE = 0x0301080Eull;
+
+static const uint64_t P9N2_MCS_3_MCRSVDE = 0x0301088Eull;
+
+
+static const uint64_t P9N2_MCS_MCRSVDF = 0x0501080Full;
+
+static const uint64_t P9N2_MCS_0_MCRSVDF = 0x0501080Full;
+
+static const uint64_t P9N2_MCS_1_MCRSVDF = 0x0501088Full;
+
+static const uint64_t P9N2_MCS_2_MCRSVDF = 0x0301080Full;
+
+static const uint64_t P9N2_MCS_3_MCRSVDF = 0x0301088Full;
+
+
+static const uint64_t P9N2_MCS_MCSYNC = 0x05010815ull;
+
+static const uint64_t P9N2_MCS_0_MCSYNC = 0x05010815ull;
+
+static const uint64_t P9N2_MCS_1_MCSYNC = 0x05010895ull;
+
+static const uint64_t P9N2_MCS_2_MCSYNC = 0x03010815ull;
+
+static const uint64_t P9N2_MCS_3_MCSYNC = 0x03010895ull;
+
+
+static const uint64_t P9N2_MCS_MCTEST = 0x05010818ull;
+
+static const uint64_t P9N2_MCS_0_MCTEST = 0x05010818ull;
+
+static const uint64_t P9N2_MCS_1_MCTEST = 0x05010898ull;
+
+static const uint64_t P9N2_MCS_2_MCTEST = 0x03010818ull;
+
+static const uint64_t P9N2_MCS_3_MCTEST = 0x03010898ull;
+
+
+static const uint64_t P9N2_MCS_MCTO = 0x0501081Bull;
+
+static const uint64_t P9N2_MCS_0_MCTO = 0x0501081Bull;
+
+static const uint64_t P9N2_MCS_1_MCTO = 0x0501089Bull;
+
+static const uint64_t P9N2_MCS_2_MCTO = 0x0301081Bull;
+
+static const uint64_t P9N2_MCS_3_MCTO = 0x0301089Bull;
+
+
+static const uint64_t P9N2_MCS_0_PORT02_MCWAT = 0x0501082Aull;
+
+static const uint64_t P9N2_MCS_0_PORT13_MCWAT = 0x0501083Aull;
+
+static const uint64_t P9N2_MCS_1_PORT02_MCWAT = 0x050108AAull;
+
+static const uint64_t P9N2_MCS_1_PORT13_MCWAT = 0x050108BAull;
+
+static const uint64_t P9N2_MCS_2_PORT02_MCWAT = 0x0301082Aull;
+
+static const uint64_t P9N2_MCS_2_PORT13_MCWAT = 0x0301083Aull;
+
+static const uint64_t P9N2_MCS_3_PORT02_MCWAT = 0x030108AAull;
+
+static const uint64_t P9N2_MCS_3_PORT13_MCWAT = 0x030108BAull;
+
+static const uint64_t P9N2_MCS_PORT02_MCWAT = 0x0501082Aull;
+
+static const uint64_t P9N2_MCS_PORT13_MCWAT = 0x0501083Aull;
+
+
+static const uint64_t P9N2_MCS_MCWATCNTL = 0x0501081Cull;
+
+static const uint64_t P9N2_MCS_0_MCWATCNTL = 0x0501081Cull;
+
+static const uint64_t P9N2_MCS_1_MCWATCNTL = 0x0501089Cull;
+
+static const uint64_t P9N2_MCS_2_MCWATCNTL = 0x0301081Cull;
+
+static const uint64_t P9N2_MCS_3_MCWATCNTL = 0x0301089Cull;
+
+
+static const uint64_t P9N2_MCS_MCWATDATA = 0x0501081Dull;
+
+static const uint64_t P9N2_MCS_0_MCWATDATA = 0x0501081Dull;
+
+static const uint64_t P9N2_MCS_1_MCWATDATA = 0x0501089Dull;
+
+static const uint64_t P9N2_MCS_2_MCWATDATA = 0x0301081Dull;
+
+static const uint64_t P9N2_MCS_3_MCWATDATA = 0x0301089Dull;
+
+
+static const uint64_t P9N2_MCA_MSR = 0x07010A0Cull;
+
+static const uint64_t P9N2_MCA_0_MSR = 0x07010A0Cull;
+
+static const uint64_t P9N2_MCA_1_MSR = 0x07010A4Cull;
+
+static const uint64_t P9N2_MCA_2_MSR = 0x07010A8Cull;
+
+static const uint64_t P9N2_MCA_3_MSR = 0x07010ACCull;
+
+static const uint64_t P9N2_MCA_4_MSR = 0x08010A0Cull;
+
+static const uint64_t P9N2_MCA_5_MSR = 0x08010A4Cull;
+
+static const uint64_t P9N2_MCA_6_MSR = 0x08010A8Cull;
+
+static const uint64_t P9N2_MCA_7_MSR = 0x08010ACCull;
+
+
+static const uint64_t P9N2_MCA_PSCOM_ERROR_MASK = 0x07010002ull;
+
+static const uint64_t P9N2_MCA_0_PSCOM_ERROR_MASK = 0x07010002ull;
+
+static const uint64_t P9N2_MCA_4_PSCOM_ERROR_MASK = 0x08010002ull;
+
+
+static const uint64_t P9N2_MCA_PSCOM_MODE_REG = 0x07010000ull;
+
+static const uint64_t P9N2_MCA_0_PSCOM_MODE_REG = 0x07010000ull;
+
+static const uint64_t P9N2_MCA_4_PSCOM_MODE_REG = 0x08010000ull;
+
+
+static const uint64_t P9N2_MCA_PSCOM_STATUS_ERROR_REG = 0x07010001ull;
+
+static const uint64_t P9N2_MCA_0_PSCOM_STATUS_ERROR_REG = 0x07010001ull;
+
+static const uint64_t P9N2_MCA_4_PSCOM_STATUS_ERROR_REG = 0x08010001ull;
+
+
+static const uint64_t P9N2_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q = 0x070123DDull;
+
+static const uint64_t P9N2_MCBIST_0_RCD_LRDIM_CNTL_WORD0_15Q = 0x070123DDull;
+
+static const uint64_t P9N2_MCBIST_1_RCD_LRDIM_CNTL_WORD0_15Q = 0x080123DDull;
+
+
+static const uint64_t P9N2_MCA_RECR = 0x07010A0Aull;
+
+static const uint64_t P9N2_MCA_0_RECR = 0x07010A0Aull;
+
+static const uint64_t P9N2_MCA_1_RECR = 0x07010A4Aull;
+
+static const uint64_t P9N2_MCA_2_RECR = 0x07010A8Aull;
+
+static const uint64_t P9N2_MCA_3_RECR = 0x07010ACAull;
+
+static const uint64_t P9N2_MCA_4_RECR = 0x08010A0Aull;
+
+static const uint64_t P9N2_MCA_5_RECR = 0x08010A4Aull;
+
+static const uint64_t P9N2_MCA_6_RECR = 0x08010A8Aull;
+
+static const uint64_t P9N2_MCA_7_RECR = 0x08010ACAull;
+
+
+static const uint64_t P9N2_MCA_RING_FENCE_MASK_LATCH_REG = 0x07010008ull;
+
+static const uint64_t P9N2_MCA_0_RING_FENCE_MASK_LATCH_REG = 0x07010008ull;
+
+static const uint64_t P9N2_MCA_4_RING_FENCE_MASK_LATCH_REG = 0x08010008ull;
+
+
+static const uint64_t P9N2_MCBIST_RUNTIMECTRQ = 0x070123B0ull;
+
+static const uint64_t P9N2_MCBIST_0_RUNTIMECTRQ = 0x070123B0ull;
+
+static const uint64_t P9N2_MCBIST_1_RUNTIMECTRQ = 0x080123B0ull;
+
+
+static const uint64_t P9N2_MCA_TRACE_HI_DATA_REG = 0x07010400ull;
+
+static const uint64_t P9N2_MCA_0_TRACE_HI_DATA_REG = 0x07010400ull;
+
+static const uint64_t P9N2_MCA_4_TRACE_HI_DATA_REG = 0x08010400ull;
+
+
+static const uint64_t P9N2_MCA_TRACE_LO_DATA_REG = 0x07010401ull;
+
+static const uint64_t P9N2_MCA_0_TRACE_LO_DATA_REG = 0x07010401ull;
+
+static const uint64_t P9N2_MCA_4_TRACE_LO_DATA_REG = 0x08010401ull;
+
+
+static const uint64_t P9N2_MCA_TRACE_TRCTRL_CONFIG = 0x07010402ull;
+
+static const uint64_t P9N2_MCA_0_TRACE_TRCTRL_CONFIG = 0x07010402ull;
+
+static const uint64_t P9N2_MCA_4_TRACE_TRCTRL_CONFIG = 0x08010402ull;
+
+
+static const uint64_t P9N2_MCA_TRACE_TRDATA_CONFIG_0 = 0x07010403ull;
+
+static const uint64_t P9N2_MCA_0_TRACE_TRDATA_CONFIG_0 = 0x07010403ull;
+
+static const uint64_t P9N2_MCA_4_TRACE_TRDATA_CONFIG_0 = 0x08010403ull;
+
+
+static const uint64_t P9N2_MCA_TRACE_TRDATA_CONFIG_1 = 0x07010404ull;
+
+static const uint64_t P9N2_MCA_0_TRACE_TRDATA_CONFIG_1 = 0x07010404ull;
+
+static const uint64_t P9N2_MCA_4_TRACE_TRDATA_CONFIG_1 = 0x08010404ull;
+
+
+static const uint64_t P9N2_MCA_TRACE_TRDATA_CONFIG_2 = 0x07010405ull;
+
+static const uint64_t P9N2_MCA_0_TRACE_TRDATA_CONFIG_2 = 0x07010405ull;
+
+static const uint64_t P9N2_MCA_4_TRACE_TRDATA_CONFIG_2 = 0x08010405ull;
+
+
+static const uint64_t P9N2_MCA_TRACE_TRDATA_CONFIG_3 = 0x07010406ull;
+
+static const uint64_t P9N2_MCA_0_TRACE_TRDATA_CONFIG_3 = 0x07010406ull;
+
+static const uint64_t P9N2_MCA_4_TRACE_TRDATA_CONFIG_3 = 0x08010406ull;
+
+
+static const uint64_t P9N2_MCA_TRACE_TRDATA_CONFIG_4 = 0x07010407ull;
+
+static const uint64_t P9N2_MCA_0_TRACE_TRDATA_CONFIG_4 = 0x07010407ull;
+
+static const uint64_t P9N2_MCA_4_TRACE_TRDATA_CONFIG_4 = 0x08010407ull;
+
+
+static const uint64_t P9N2_MCA_TRACE_TRDATA_CONFIG_5 = 0x07010408ull;
+
+static const uint64_t P9N2_MCA_0_TRACE_TRDATA_CONFIG_5 = 0x07010408ull;
+
+static const uint64_t P9N2_MCA_4_TRACE_TRDATA_CONFIG_5 = 0x08010408ull;
+
+
+static const uint64_t P9N2_MCA_TRACE_TRDATA_CONFIG_9 = 0x07010409ull;
+
+static const uint64_t P9N2_MCA_0_TRACE_TRDATA_CONFIG_9 = 0x07010409ull;
+
+static const uint64_t P9N2_MCA_4_TRACE_TRDATA_CONFIG_9 = 0x08010409ull;
+
+
+static const uint64_t P9N2_MCBIST_WATCFG0AQ = 0x07012380ull;
+
+static const uint64_t P9N2_MCBIST_0_WATCFG0AQ = 0x07012380ull;
+
+static const uint64_t P9N2_MCBIST_1_WATCFG0AQ = 0x08012380ull;
+
+
+static const uint64_t P9N2_MCBIST_WATCFG0BQ = 0x07012381ull;
+
+static const uint64_t P9N2_MCBIST_0_WATCFG0BQ = 0x07012381ull;
+
+static const uint64_t P9N2_MCBIST_1_WATCFG0BQ = 0x08012381ull;
+
+
+static const uint64_t P9N2_MCBIST_WATCFG0CQ = 0x07012382ull;
+
+static const uint64_t P9N2_MCBIST_0_WATCFG0CQ = 0x07012382ull;
+
+static const uint64_t P9N2_MCBIST_1_WATCFG0CQ = 0x08012382ull;
+
+
+static const uint64_t P9N2_MCBIST_WATCFG0DQ = 0x07012383ull;
+
+static const uint64_t P9N2_MCBIST_0_WATCFG0DQ = 0x07012383ull;
+
+static const uint64_t P9N2_MCBIST_1_WATCFG0DQ = 0x08012383ull;
+
+
+static const uint64_t P9N2_MCBIST_WATCFG0EQ = 0x07012384ull;
+
+static const uint64_t P9N2_MCBIST_0_WATCFG0EQ = 0x07012384ull;
+
+static const uint64_t P9N2_MCBIST_1_WATCFG0EQ = 0x08012384ull;
+
+
+static const uint64_t P9N2_MCBIST_WATCFG1AQ = 0x07012385ull;
+
+static const uint64_t P9N2_MCBIST_0_WATCFG1AQ = 0x07012385ull;
+
+static const uint64_t P9N2_MCBIST_1_WATCFG1AQ = 0x08012385ull;
+
+
+static const uint64_t P9N2_MCBIST_WATCFG1BQ = 0x07012386ull;
+
+static const uint64_t P9N2_MCBIST_0_WATCFG1BQ = 0x07012386ull;
+
+static const uint64_t P9N2_MCBIST_1_WATCFG1BQ = 0x08012386ull;
+
+
+static const uint64_t P9N2_MCBIST_WATCFG1CQ = 0x07012387ull;
+
+static const uint64_t P9N2_MCBIST_0_WATCFG1CQ = 0x07012387ull;
+
+static const uint64_t P9N2_MCBIST_1_WATCFG1CQ = 0x08012387ull;
+
+
+static const uint64_t P9N2_MCBIST_WATCFG1DQ = 0x07012388ull;
+
+static const uint64_t P9N2_MCBIST_0_WATCFG1DQ = 0x07012388ull;
+
+static const uint64_t P9N2_MCBIST_1_WATCFG1DQ = 0x08012388ull;
+
+
+static const uint64_t P9N2_MCBIST_WATCFG1EQ = 0x07012389ull;
+
+static const uint64_t P9N2_MCBIST_0_WATCFG1EQ = 0x07012389ull;
+
+static const uint64_t P9N2_MCBIST_1_WATCFG1EQ = 0x08012389ull;
+
+
+static const uint64_t P9N2_MCBIST_WATCFG2AQ = 0x0701238Aull;
+
+static const uint64_t P9N2_MCBIST_0_WATCFG2AQ = 0x0701238Aull;
+
+static const uint64_t P9N2_MCBIST_1_WATCFG2AQ = 0x0801238Aull;
+
+
+static const uint64_t P9N2_MCBIST_WATCFG2BQ = 0x0701238Bull;
+
+static const uint64_t P9N2_MCBIST_0_WATCFG2BQ = 0x0701238Bull;
+
+static const uint64_t P9N2_MCBIST_1_WATCFG2BQ = 0x0801238Bull;
+
+
+static const uint64_t P9N2_MCBIST_WATCFG2CQ = 0x0701238Cull;
+
+static const uint64_t P9N2_MCBIST_0_WATCFG2CQ = 0x0701238Cull;
+
+static const uint64_t P9N2_MCBIST_1_WATCFG2CQ = 0x0801238Cull;
+
+
+static const uint64_t P9N2_MCBIST_WATCFG2DQ = 0x0701238Dull;
+
+static const uint64_t P9N2_MCBIST_0_WATCFG2DQ = 0x0701238Dull;
+
+static const uint64_t P9N2_MCBIST_1_WATCFG2DQ = 0x0801238Dull;
+
+
+static const uint64_t P9N2_MCBIST_WATCFG2EQ = 0x0701238Eull;
+
+static const uint64_t P9N2_MCBIST_0_WATCFG2EQ = 0x0701238Eull;
+
+static const uint64_t P9N2_MCBIST_1_WATCFG2EQ = 0x0801238Eull;
+
+
+static const uint64_t P9N2_MCBIST_WATCFG3AQ = 0x0701238Full;
+
+static const uint64_t P9N2_MCBIST_0_WATCFG3AQ = 0x0701238Full;
+
+static const uint64_t P9N2_MCBIST_1_WATCFG3AQ = 0x0801238Full;
+
+
+static const uint64_t P9N2_MCBIST_WATCFG3BQ = 0x07012390ull;
+
+static const uint64_t P9N2_MCBIST_0_WATCFG3BQ = 0x07012390ull;
+
+static const uint64_t P9N2_MCBIST_1_WATCFG3BQ = 0x08012390ull;
+
+
+static const uint64_t P9N2_MCBIST_WATCFG3CQ = 0x07012391ull;
+
+static const uint64_t P9N2_MCBIST_0_WATCFG3CQ = 0x07012391ull;
+
+static const uint64_t P9N2_MCBIST_1_WATCFG3CQ = 0x08012391ull;
+
+
+static const uint64_t P9N2_MCBIST_WATCFG3DQ = 0x07012392ull;
+
+static const uint64_t P9N2_MCBIST_0_WATCFG3DQ = 0x07012392ull;
+
+static const uint64_t P9N2_MCBIST_1_WATCFG3DQ = 0x08012392ull;
+
+
+static const uint64_t P9N2_MCBIST_WATCFG3EQ = 0x07012393ull;
+
+static const uint64_t P9N2_MCBIST_0_WATCFG3EQ = 0x07012393ull;
+
+static const uint64_t P9N2_MCBIST_1_WATCFG3EQ = 0x08012393ull;
+
+
+static const uint64_t P9N2_MCA_WBMGR_TAG_INFO = 0x07010A33ull;
+
+static const uint64_t P9N2_MCA_0_WBMGR_TAG_INFO = 0x07010A33ull;
+
+static const uint64_t P9N2_MCA_1_WBMGR_TAG_INFO = 0x07010A73ull;
+
+static const uint64_t P9N2_MCA_2_WBMGR_TAG_INFO = 0x07010AB3ull;
+
+static const uint64_t P9N2_MCA_3_WBMGR_TAG_INFO = 0x07010AF3ull;
+
+static const uint64_t P9N2_MCA_4_WBMGR_TAG_INFO = 0x08010A33ull;
+
+static const uint64_t P9N2_MCA_5_WBMGR_TAG_INFO = 0x08010A73ull;
+
+static const uint64_t P9N2_MCA_6_WBMGR_TAG_INFO = 0x08010AB3ull;
+
+static const uint64_t P9N2_MCA_7_WBMGR_TAG_INFO = 0x08010AF3ull;
+
+
+static const uint64_t P9N2_MCA_WDFCFG = 0x07010A30ull;
+
+static const uint64_t P9N2_MCA_0_WDFCFG = 0x07010A30ull;
+
+static const uint64_t P9N2_MCA_1_WDFCFG = 0x07010A70ull;
+
+static const uint64_t P9N2_MCA_2_WDFCFG = 0x07010AB0ull;
+
+static const uint64_t P9N2_MCA_3_WDFCFG = 0x07010AF0ull;
+
+static const uint64_t P9N2_MCA_4_WDFCFG = 0x08010A30ull;
+
+static const uint64_t P9N2_MCA_5_WDFCFG = 0x08010A70ull;
+
+static const uint64_t P9N2_MCA_6_WDFCFG = 0x08010AB0ull;
+
+static const uint64_t P9N2_MCA_7_WDFCFG = 0x08010AF0ull;
+
+
+static const uint64_t P9N2_MCA_WDFDBG = 0x07010A34ull;
+
+static const uint64_t P9N2_MCA_0_WDFDBG = 0x07010A34ull;
+
+static const uint64_t P9N2_MCA_1_WDFDBG = 0x07010A74ull;
+
+static const uint64_t P9N2_MCA_2_WDFDBG = 0x07010AB4ull;
+
+static const uint64_t P9N2_MCA_3_WDFDBG = 0x07010AF4ull;
+
+static const uint64_t P9N2_MCA_4_WDFDBG = 0x08010A34ull;
+
+static const uint64_t P9N2_MCA_5_WDFDBG = 0x08010A74ull;
+
+static const uint64_t P9N2_MCA_6_WDFDBG = 0x08010AB4ull;
+
+static const uint64_t P9N2_MCA_7_WDFDBG = 0x08010AF4ull;
+
+
+static const uint64_t P9N2_MCA_WECR = 0x07010A28ull;
+
+static const uint64_t P9N2_MCA_0_WECR = 0x07010A28ull;
+
+static const uint64_t P9N2_MCA_1_WECR = 0x07010A68ull;
+
+static const uint64_t P9N2_MCA_2_WECR = 0x07010AA8ull;
+
+static const uint64_t P9N2_MCA_3_WECR = 0x07010AE8ull;
+
+static const uint64_t P9N2_MCA_4_WECR = 0x08010A28ull;
+
+static const uint64_t P9N2_MCA_5_WECR = 0x08010A68ull;
+
+static const uint64_t P9N2_MCA_6_WECR = 0x08010AA8ull;
+
+static const uint64_t P9N2_MCA_7_WECR = 0x08010AE8ull;
+
+
+static const uint64_t P9N2_MCA_WESR = 0x07010A2Eull;
+
+static const uint64_t P9N2_MCA_0_WESR = 0x07010A2Eull;
+
+static const uint64_t P9N2_MCA_1_WESR = 0x07010A6Eull;
+
+static const uint64_t P9N2_MCA_2_WESR = 0x07010AAEull;
+
+static const uint64_t P9N2_MCA_3_WESR = 0x07010AEEull;
+
+static const uint64_t P9N2_MCA_4_WESR = 0x08010A2Eull;
+
+static const uint64_t P9N2_MCA_5_WESR = 0x08010A6Eull;
+
+static const uint64_t P9N2_MCA_6_WESR = 0x08010AAEull;
+
+static const uint64_t P9N2_MCA_7_WESR = 0x08010AEEull;
+
+
+static const uint64_t P9N2_MCA_WOF = 0x07010A08ull;
+
+static const uint64_t P9N2_MCA_0_WOF = 0x07010A08ull;
+
+static const uint64_t P9N2_MCA_1_WOF = 0x07010A48ull;
+
+static const uint64_t P9N2_MCA_2_WOF = 0x07010A88ull;
+
+static const uint64_t P9N2_MCA_3_WOF = 0x07010AC8ull;
+
+static const uint64_t P9N2_MCA_4_WOF = 0x08010A08ull;
+
+static const uint64_t P9N2_MCA_5_WOF = 0x08010A48ull;
+
+static const uint64_t P9N2_MCA_6_WOF = 0x08010A88ull;
+
+static const uint64_t P9N2_MCA_7_WOF = 0x08010AC8ull;
+
+
+static const uint64_t P9N2_MCA_WRITE_PROTECT_ENABLE_REG = 0x07010005ull;
+
+static const uint64_t P9N2_MCA_0_WRITE_PROTECT_ENABLE_REG = 0x07010005ull;
+
+static const uint64_t P9N2_MCA_4_WRITE_PROTECT_ENABLE_REG = 0x08010005ull;
+
+
+static const uint64_t P9N2_MCA_WRITE_PROTECT_RINGS_REG = 0x07010006ull;
+
+static const uint64_t P9N2_MCA_0_WRITE_PROTECT_RINGS_REG = 0x07010006ull;
+
+static const uint64_t P9N2_MCA_4_WRITE_PROTECT_RINGS_REG = 0x08010006ull;
+
+
+static const uint64_t P9N2_MCA_WRTCFG = 0x07010A38ull;
+
+static const uint64_t P9N2_MCA_0_WRTCFG = 0x07010A38ull;
+
+static const uint64_t P9N2_MCA_1_WRTCFG = 0x07010A78ull;
+
+static const uint64_t P9N2_MCA_2_WRTCFG = 0x07010AB8ull;
+
+static const uint64_t P9N2_MCA_3_WRTCFG = 0x07010AF8ull;
+
+static const uint64_t P9N2_MCA_4_WRTCFG = 0x08010A38ull;
+
+static const uint64_t P9N2_MCA_5_WRTCFG = 0x08010A78ull;
+
+static const uint64_t P9N2_MCA_6_WRTCFG = 0x08010AB8ull;
+
+static const uint64_t P9N2_MCA_7_WRTCFG = 0x08010AF8ull;
+
+
+static const uint64_t P9N2_MCA_WRTDBGMCA = 0x07010A3Aull;
+
+static const uint64_t P9N2_MCA_0_WRTDBGMCA = 0x07010A3Aull;
+
+static const uint64_t P9N2_MCA_1_WRTDBGMCA = 0x07010A7Aull;
+
+static const uint64_t P9N2_MCA_2_WRTDBGMCA = 0x07010ABAull;
+
+static const uint64_t P9N2_MCA_3_WRTDBGMCA = 0x07010AFAull;
+
+static const uint64_t P9N2_MCA_4_WRTDBGMCA = 0x08010A3Aull;
+
+static const uint64_t P9N2_MCA_5_WRTDBGMCA = 0x08010A7Aull;
+
+static const uint64_t P9N2_MCA_6_WRTDBGMCA = 0x08010ABAull;
+
+static const uint64_t P9N2_MCA_7_WRTDBGMCA = 0x08010AFAull;
+
+
+static const uint64_t P9N2_MCA_WRTDBGNEST = 0x07010A3Bull;
+
+static const uint64_t P9N2_MCA_0_WRTDBGNEST = 0x07010A3Bull;
+
+static const uint64_t P9N2_MCA_1_WRTDBGNEST = 0x07010A7Bull;
+
+static const uint64_t P9N2_MCA_2_WRTDBGNEST = 0x07010ABBull;
+
+static const uint64_t P9N2_MCA_3_WRTDBGNEST = 0x07010AFBull;
+
+static const uint64_t P9N2_MCA_4_WRTDBGNEST = 0x08010A3Bull;
+
+static const uint64_t P9N2_MCA_5_WRTDBGNEST = 0x08010A7Bull;
+
+static const uint64_t P9N2_MCA_6_WRTDBGNEST = 0x08010ABBull;
+
+static const uint64_t P9N2_MCA_7_WRTDBGNEST = 0x08010AFBull;
+
+
+static const uint64_t P9N2_MCA_0_WREITE_WRT_ECC = 0x07010A39ull;
+
+static const uint64_t P9N2_MCA_0_WDF_WRT_ECC = 0x07010A31ull;
+
+static const uint64_t P9N2_MCA_1_WREITE_WRT_ECC = 0x07010A79ull;
+
+static const uint64_t P9N2_MCA_1_WDF_WRT_ECC = 0x07010A71ull;
+
+static const uint64_t P9N2_MCA_2_WDF_WRT_ECC = 0x07010AB1ull;
+
+static const uint64_t P9N2_MCA_2_WREITE_WRT_ECC = 0x07010AB9ull;
+
+static const uint64_t P9N2_MCA_3_WREITE_WRT_ECC = 0x07010AF9ull;
+
+static const uint64_t P9N2_MCA_3_WDF_WRT_ECC = 0x07010AF1ull;
+
+static const uint64_t P9N2_MCA_4_WREITE_WRT_ECC = 0x08010A39ull;
+
+static const uint64_t P9N2_MCA_4_WDF_WRT_ECC = 0x08010A31ull;
+
+static const uint64_t P9N2_MCA_5_WREITE_WRT_ECC = 0x08010A79ull;
+
+static const uint64_t P9N2_MCA_5_WDF_WRT_ECC = 0x08010A71ull;
+
+static const uint64_t P9N2_MCA_6_WREITE_WRT_ECC = 0x08010AB9ull;
+
+static const uint64_t P9N2_MCA_6_WDF_WRT_ECC = 0x08010AB1ull;
+
+static const uint64_t P9N2_MCA_7_WDF_WRT_ECC = 0x08010AF1ull;
+
+static const uint64_t P9N2_MCA_7_WREITE_WRT_ECC = 0x08010AF9ull;
+
+static const uint64_t P9N2_MCA_WDF_WRT_ECC = 0x07010A31ull;
+
+static const uint64_t P9N2_MCA_WREITE_WRT_ECC = 0x07010A39ull;
+
+
+static const uint64_t P9N2_MCA_3_XTRA_TRACE_MODE = 0x070107D1ull;
+
+static const uint64_t P9N2_MCA_7_XTRA_TRACE_MODE = 0x080107D1ull;
+
+#endif
+
diff --git a/src/import/chips/p9/common/include/p9n2_mc_scom_addresses_fld.H b/src/import/chips/p9/common/include/p9n2_mc_scom_addresses_fld.H
new file mode 100644
index 000000000..5e4624540
--- /dev/null
+++ b/src/import/chips/p9/common/include/p9n2_mc_scom_addresses_fld.H
@@ -0,0 +1,15145 @@
+/* IBM_PROLOG_BEGIN_TAG */
+/* This is an automatically generated prolog. */
+/* */
+/* $Source: src/import/chips/p9/common/include/p9n2_mc_scom_addresses_fld.H $ */
+/* */
+/* OpenPOWER HostBoot Project */
+/* */
+/* Contributors Listed Below - COPYRIGHT 2017 */
+/* [+] International Business Machines Corp. */
+/* */
+/* */
+/* Licensed under the Apache License, Version 2.0 (the "License"); */
+/* you may not use this file except in compliance with the License. */
+/* You may obtain a copy of the License at */
+/* */
+/* http://www.apache.org/licenses/LICENSE-2.0 */
+/* */
+/* Unless required by applicable law or agreed to in writing, software */
+/* distributed under the License is distributed on an "AS IS" BASIS, */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */
+/* implied. See the License for the specific language governing */
+/* permissions and limitations under the License. */
+/* */
+/* IBM_PROLOG_END_TAG */
+///
+/// @file p9_mc_scom_addresses_fld.H
+/// @brief Defines constants for scom addresses
+///
+// *HWP HWP Owner: Ben Gass <bgass@us.ibm.com>
+// *HWP FW Owner: Thi Tran <thi@us.ibm.com>
+// *HWP Team: SOA
+// *HWP Level: 1
+// *HWP Consumed by: FSP:HB:HS:OCC:SBE:CME:SGPE:PGPE:FPPE:IPPE
+
+#ifndef __P9N2_MC_SCOM_ADDRESSES_FLD_H
+#define __P9N2_MC_SCOM_ADDRESSES_FLD_H
+
+#include <stdint.h>
+
+static const uint8_t P9N2_MCS_PORT02_AACR_BUFFER = 0 ;
+static const uint8_t P9N2_MCS_PORT02_AACR_ADDRESS = 1 ;
+static const uint8_t P9N2_MCS_PORT02_AACR_ADDRESS_LEN = 9 ;
+static const uint8_t P9N2_MCS_PORT02_AACR_AUTOINC = 10 ;
+
+static const uint8_t P9N2_MCA_WREITE_AACR_BUFFER = 0 ;
+static const uint8_t P9N2_MCA_WREITE_AACR_ADDRESS = 1 ;
+static const uint8_t P9N2_MCA_WREITE_AACR_ADDRESS_LEN = 9 ;
+static const uint8_t P9N2_MCA_WREITE_AACR_AUTOINC = 10 ;
+static const uint8_t P9N2_MCA_WREITE_AACR_ECCGEN = 11 ;
+
+static const uint8_t P9N2_MCS_PORT02_AADR_DATA = 0 ;
+static const uint8_t P9N2_MCS_PORT02_AADR_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_MCA_AADR_DATA = 0 ;
+static const uint8_t P9N2_MCA_AADR_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_MCS_PORT02_AAER_TAG_ECC = 0 ;
+static const uint8_t P9N2_MCS_PORT02_AAER_TAG_ECC_LEN = 9 ;
+
+static const uint8_t P9N2_MCA_AAER_TAG_ECC = 0 ;
+static const uint8_t P9N2_MCA_AAER_TAG_ECC_LEN = 9 ;
+
+static const uint8_t P9N2_MCA_ACTION0_FIR = 0 ;
+static const uint8_t P9N2_MCA_ACTION0_FIR_LEN = 64 ;
+
+static const uint8_t P9N2_MCA_ACTION1_FIR = 0 ;
+static const uint8_t P9N2_MCA_ACTION1_FIR_LEN = 64 ;
+
+static const uint8_t P9N2_MCA_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR = 0 ;
+static const uint8_t P9N2_MCA_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN = 16 ;
+static const uint8_t P9N2_MCA_ADDR_TRAP_REG_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR = 16 ;
+static const uint8_t P9N2_MCA_ADDR_TRAP_REG_RESERVED_LAST_LT = 17 ;
+static const uint8_t P9N2_MCA_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR = 18 ;
+static const uint8_t P9N2_MCA_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN = 13 ;
+static const uint8_t P9N2_MCA_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY = 31 ;
+static const uint8_t P9N2_MCA_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR = 32 ;
+static const uint8_t P9N2_MCA_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION = 33 ;
+static const uint8_t P9N2_MCA_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER = 34 ;
+
+static const uint8_t P9N2_MCA_ATOMIC_LOCK_MASK_LATCH_REG_MASK = 0 ;
+static const uint8_t P9N2_MCA_ATOMIC_LOCK_MASK_LATCH_REG_MASK_LEN = 16 ;
+
+static const uint8_t P9N2_MCBIST_CCSARRERRINJQ_CCS_ARRAY_CE_ERR_INJ_MODE = 0 ;
+static const uint8_t P9N2_MCBIST_CCSARRERRINJQ_CCS_ARRAY_CE_ERR_INJ = 1 ;
+static const uint8_t P9N2_MCBIST_CCSARRERRINJQ_CCS_ARRAY_UE_ERR_INJ_MODE = 2 ;
+static const uint8_t P9N2_MCBIST_CCSARRERRINJQ_CCS_ARRAY_UE_ERR_INJ = 3 ;
+static const uint8_t P9N2_MCBIST_CCSARRERRINJQ_RESERVED_4 = 4 ;
+static const uint8_t P9N2_MCBIST_CCSARRERRINJQ_DISABLE_2N_MODE = 5 ;
+static const uint8_t P9N2_MCBIST_CCSARRERRINJQ_RESERVED_6_14 = 6 ;
+static const uint8_t P9N2_MCBIST_CCSARRERRINJQ_RESERVED_6_14_LEN = 9 ;
+static const uint8_t P9N2_MCBIST_CCSARRERRINJQ_READ_RESPONSE_DELAY_ENABLE = 15 ;
+static const uint8_t P9N2_MCBIST_CCSARRERRINJQ_CCS_LOOP_COUNTER_COMPARE0 = 16 ;
+static const uint8_t P9N2_MCBIST_CCSARRERRINJQ_CCS_LOOP_COUNTER_COMPARE0_LEN = 16 ;
+static const uint8_t P9N2_MCBIST_CCSARRERRINJQ_CCS_LOOP_COUNTER_COMPARE1 = 32 ;
+static const uint8_t P9N2_MCBIST_CCSARRERRINJQ_CCS_LOOP_COUNTER_COMPARE1_LEN = 16 ;
+static const uint8_t P9N2_MCBIST_CCSARRERRINJQ_CCS_LOOP_COUNTER_COMPARE2 = 48 ;
+static const uint8_t P9N2_MCBIST_CCSARRERRINJQ_CCS_LOOP_COUNTER_COMPARE2_LEN = 16 ;
+
+static const uint8_t P9N2_MCBIST_CCS_CNTLQ_START = 0 ;
+static const uint8_t P9N2_MCBIST_CCS_CNTLQ_STOP = 1 ;
+
+static const uint8_t P9N2_MCBIST_CCS_FIXED_DATA0Q_DATA_0_63 = 0 ;
+static const uint8_t P9N2_MCBIST_CCS_FIXED_DATA0Q_DATA_0_63_LEN = 64 ;
+
+static const uint8_t P9N2_MCBIST_CCS_FIXED_DATA1Q_DATA_64_79 = 0 ;
+static const uint8_t P9N2_MCBIST_CCS_FIXED_DATA1Q_DATA_64_79_LEN = 16 ;
+
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_0_13 = 0 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_0_13_LEN = 14 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_17 = 14 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_00_DDR_BANK_GROUP_1 = 15 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_00_DDR_RESETN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_00_DDR_BANK_0_1 = 17 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_00_DDR_BANK_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_00_DDR_BANK_GROUP_0 = 19 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_00_DDR_ACTN = 20 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_16 = 21 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_15 = 22 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_14 = 23 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_00_DDR_CKE = 24 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_00_DDR_CKE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_00_RESERVED_28_31 = 28 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_00_RESERVED_28_31_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_00_DDR_CSN_0_1 = 32 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_00_DDR_CSN_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_00_DDR_CID_0_1 = 34 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_00_DDR_CID_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_00_DDR_CSN_2_3 = 36 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_00_DDR_CSN_2_3_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_00_DDR_CID_2 = 38 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_00_RESERVED_39_47 = 39 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_00_RESERVED_39_47_LEN = 9 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_00_DDR_ODT = 48 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_00_DDR_ODT_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_00_RESERVED_52_55 = 52 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_00_RESERVED_52_55_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_00_DDR_CAL_TYPE = 56 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_00_DDR_CAL_TYPE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_00_DDR_PARITY = 60 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_00_DDR_BANK_2 = 61 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_00_LOOP_BREAK_MODE = 62 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_00_LOOP_BREAK_MODE_LEN = 2 ;
+
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_01_DDR_ADDRESS_0_13 = 0 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_01_DDR_ADDRESS_0_13_LEN = 14 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_01_DDR_ADDRESS_17 = 14 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_01_DDR_BANK_GROUP_1 = 15 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_01_DDR_RESETN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_01_DDR_BANK_0_1 = 17 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_01_DDR_BANK_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_01_DDR_BANK_GROUP_0 = 19 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_01_DDR_ACTN = 20 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_01_DDR_ADDRESS_16 = 21 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_01_DDR_ADDRESS_15 = 22 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_01_DDR_ADDRESS_14 = 23 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_01_DDR_CKE = 24 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_01_DDR_CKE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_01_RESERVED_28_31 = 28 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_01_RESERVED_28_31_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_01_DDR_CSN_0_1 = 32 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_01_DDR_CSN_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_01_DDR_CID_0_1 = 34 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_01_DDR_CID_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_01_DDR_CSN_2_3 = 36 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_01_DDR_CSN_2_3_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_01_DDR_CID_2 = 38 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_01_RESERVED_39_47 = 39 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_01_RESERVED_39_47_LEN = 9 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_01_DDR_ODT = 48 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_01_DDR_ODT_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_01_RESERVED_52_55 = 52 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_01_RESERVED_52_55_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_01_DDR_CAL_TYPE = 56 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_01_DDR_CAL_TYPE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_01_DDR_PARITY = 60 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_01_DDR_BANK_2 = 61 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_01_LOOP_BREAK_MODE = 62 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_01_LOOP_BREAK_MODE_LEN = 2 ;
+
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_02_DDR_ADDRESS_0_13 = 0 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_02_DDR_ADDRESS_0_13_LEN = 14 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_02_DDR_ADDRESS_17 = 14 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_02_DDR_BANK_GROUP_1 = 15 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_02_DDR_RESETN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_02_DDR_BANK_0_1 = 17 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_02_DDR_BANK_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_02_DDR_BANK_GROUP_0 = 19 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_02_DDR_ACTN = 20 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_02_DDR_ADDRESS_16 = 21 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_02_DDR_ADDRESS_15 = 22 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_02_DDR_ADDRESS_14 = 23 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_02_DDR_CKE = 24 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_02_DDR_CKE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_02_RESERVED_28_31 = 28 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_02_RESERVED_28_31_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_02_DDR_CSN_0_1 = 32 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_02_DDR_CSN_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_02_DDR_CID_0_1 = 34 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_02_DDR_CID_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_02_DDR_CSN_2_3 = 36 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_02_DDR_CSN_2_3_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_02_DDR_CID_2 = 38 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_02_RESERVED_39_47 = 39 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_02_RESERVED_39_47_LEN = 9 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_02_DDR_ODT = 48 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_02_DDR_ODT_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_02_RESERVED_52_55 = 52 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_02_RESERVED_52_55_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_02_DDR_CAL_TYPE = 56 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_02_DDR_CAL_TYPE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_02_DDR_PARITY = 60 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_02_DDR_BANK_2 = 61 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_02_LOOP_BREAK_MODE = 62 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_02_LOOP_BREAK_MODE_LEN = 2 ;
+
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_03_DDR_ADDRESS_0_13 = 0 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_03_DDR_ADDRESS_0_13_LEN = 14 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_03_DDR_ADDRESS_17 = 14 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_03_DDR_BANK_GROUP_1 = 15 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_03_DDR_RESETN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_03_DDR_BANK_0_1 = 17 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_03_DDR_BANK_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_03_DDR_BANK_GROUP_0 = 19 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_03_DDR_ACTN = 20 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_03_DDR_ADDRESS_16 = 21 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_03_DDR_ADDRESS_15 = 22 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_03_DDR_ADDRESS_14 = 23 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_03_DDR_CKE = 24 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_03_DDR_CKE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_03_RESERVED_28_31 = 28 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_03_RESERVED_28_31_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_03_DDR_CSN_0_1 = 32 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_03_DDR_CSN_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_03_DDR_CID_0_1 = 34 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_03_DDR_CID_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_03_DDR_CSN_2_3 = 36 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_03_DDR_CSN_2_3_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_03_DDR_CID_2 = 38 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_03_RESERVED_39_47 = 39 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_03_RESERVED_39_47_LEN = 9 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_03_DDR_ODT = 48 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_03_DDR_ODT_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_03_RESERVED_52_55 = 52 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_03_RESERVED_52_55_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_03_DDR_CAL_TYPE = 56 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_03_DDR_CAL_TYPE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_03_DDR_PARITY = 60 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_03_DDR_BANK_2 = 61 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_03_LOOP_BREAK_MODE = 62 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_03_LOOP_BREAK_MODE_LEN = 2 ;
+
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_04_DDR_ADDRESS_0_13 = 0 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_04_DDR_ADDRESS_0_13_LEN = 14 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_04_DDR_ADDRESS_17 = 14 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_04_DDR_BANK_GROUP_1 = 15 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_04_DDR_RESETN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_04_DDR_BANK_0_1 = 17 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_04_DDR_BANK_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_04_DDR_BANK_GROUP_0 = 19 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_04_DDR_ACTN = 20 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_04_DDR_ADDRESS_16 = 21 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_04_DDR_ADDRESS_15 = 22 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_04_DDR_ADDRESS_14 = 23 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_04_DDR_CKE = 24 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_04_DDR_CKE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_04_RESERVED_28_31 = 28 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_04_RESERVED_28_31_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_04_DDR_CSN_0_1 = 32 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_04_DDR_CSN_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_04_DDR_CID_0_1 = 34 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_04_DDR_CID_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_04_DDR_CSN_2_3 = 36 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_04_DDR_CSN_2_3_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_04_DDR_CID_2 = 38 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_04_RESERVED_39_47 = 39 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_04_RESERVED_39_47_LEN = 9 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_04_DDR_ODT = 48 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_04_DDR_ODT_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_04_RESERVED_52_55 = 52 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_04_RESERVED_52_55_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_04_DDR_CAL_TYPE = 56 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_04_DDR_CAL_TYPE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_04_DDR_PARITY = 60 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_04_DDR_BANK_2 = 61 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_04_LOOP_BREAK_MODE = 62 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_04_LOOP_BREAK_MODE_LEN = 2 ;
+
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_05_DDR_ADDRESS_0_13 = 0 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_05_DDR_ADDRESS_0_13_LEN = 14 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_05_DDR_ADDRESS_17 = 14 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_05_DDR_BANK_GROUP_1 = 15 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_05_DDR_RESETN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_05_DDR_BANK_0_1 = 17 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_05_DDR_BANK_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_05_DDR_BANK_GROUP_0 = 19 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_05_DDR_ACTN = 20 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_05_DDR_ADDRESS_16 = 21 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_05_DDR_ADDRESS_15 = 22 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_05_DDR_ADDRESS_14 = 23 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_05_DDR_CKE = 24 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_05_DDR_CKE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_05_RESERVED_28_31 = 28 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_05_RESERVED_28_31_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_05_DDR_CSN_0_1 = 32 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_05_DDR_CSN_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_05_DDR_CID_0_1 = 34 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_05_DDR_CID_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_05_DDR_CSN_2_3 = 36 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_05_DDR_CSN_2_3_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_05_DDR_CID_2 = 38 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_05_RESERVED_39_47 = 39 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_05_RESERVED_39_47_LEN = 9 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_05_DDR_ODT = 48 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_05_DDR_ODT_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_05_RESERVED_52_55 = 52 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_05_RESERVED_52_55_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_05_DDR_CAL_TYPE = 56 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_05_DDR_CAL_TYPE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_05_DDR_PARITY = 60 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_05_DDR_BANK_2 = 61 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_05_LOOP_BREAK_MODE = 62 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_05_LOOP_BREAK_MODE_LEN = 2 ;
+
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_06_DDR_ADDRESS_0_13 = 0 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_06_DDR_ADDRESS_0_13_LEN = 14 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_06_DDR_ADDRESS_17 = 14 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_06_DDR_BANK_GROUP_1 = 15 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_06_DDR_RESETN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_06_DDR_BANK_0_1 = 17 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_06_DDR_BANK_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_06_DDR_BANK_GROUP_0 = 19 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_06_DDR_ACTN = 20 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_06_DDR_ADDRESS_16 = 21 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_06_DDR_ADDRESS_15 = 22 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_06_DDR_ADDRESS_14 = 23 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_06_DDR_CKE = 24 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_06_DDR_CKE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_06_RESERVED_28_31 = 28 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_06_RESERVED_28_31_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_06_DDR_CSN_0_1 = 32 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_06_DDR_CSN_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_06_DDR_CID_0_1 = 34 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_06_DDR_CID_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_06_DDR_CSN_2_3 = 36 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_06_DDR_CSN_2_3_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_06_DDR_CID_2 = 38 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_06_RESERVED_39_47 = 39 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_06_RESERVED_39_47_LEN = 9 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_06_DDR_ODT = 48 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_06_DDR_ODT_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_06_RESERVED_52_55 = 52 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_06_RESERVED_52_55_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_06_DDR_CAL_TYPE = 56 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_06_DDR_CAL_TYPE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_06_DDR_PARITY = 60 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_06_DDR_BANK_2 = 61 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_06_LOOP_BREAK_MODE = 62 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_06_LOOP_BREAK_MODE_LEN = 2 ;
+
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_07_DDR_ADDRESS_0_13 = 0 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_07_DDR_ADDRESS_0_13_LEN = 14 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_07_DDR_ADDRESS_17 = 14 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_07_DDR_BANK_GROUP_1 = 15 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_07_DDR_RESETN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_07_DDR_BANK_0_1 = 17 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_07_DDR_BANK_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_07_DDR_BANK_GROUP_0 = 19 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_07_DDR_ACTN = 20 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_07_DDR_ADDRESS_16 = 21 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_07_DDR_ADDRESS_15 = 22 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_07_DDR_ADDRESS_14 = 23 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_07_DDR_CKE = 24 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_07_DDR_CKE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_07_RESERVED_28_31 = 28 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_07_RESERVED_28_31_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_07_DDR_CSN_0_1 = 32 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_07_DDR_CSN_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_07_DDR_CID_0_1 = 34 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_07_DDR_CID_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_07_DDR_CSN_2_3 = 36 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_07_DDR_CSN_2_3_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_07_DDR_CID_2 = 38 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_07_RESERVED_39_47 = 39 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_07_RESERVED_39_47_LEN = 9 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_07_DDR_ODT = 48 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_07_DDR_ODT_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_07_RESERVED_52_55 = 52 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_07_RESERVED_52_55_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_07_DDR_CAL_TYPE = 56 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_07_DDR_CAL_TYPE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_07_DDR_PARITY = 60 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_07_DDR_BANK_2 = 61 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_07_LOOP_BREAK_MODE = 62 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_07_LOOP_BREAK_MODE_LEN = 2 ;
+
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_08_DDR_ADDRESS_0_13 = 0 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_08_DDR_ADDRESS_0_13_LEN = 14 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_08_DDR_ADDRESS_17 = 14 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_08_DDR_BANK_GROUP_1 = 15 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_08_DDR_RESETN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_08_DDR_BANK_0_1 = 17 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_08_DDR_BANK_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_08_DDR_BANK_GROUP_0 = 19 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_08_DDR_ACTN = 20 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_08_DDR_ADDRESS_16 = 21 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_08_DDR_ADDRESS_15 = 22 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_08_DDR_ADDRESS_14 = 23 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_08_DDR_CKE = 24 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_08_DDR_CKE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_08_RESERVED_28_31 = 28 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_08_RESERVED_28_31_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_08_DDR_CSN_0_1 = 32 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_08_DDR_CSN_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_08_DDR_CID_0_1 = 34 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_08_DDR_CID_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_08_DDR_CSN_2_3 = 36 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_08_DDR_CSN_2_3_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_08_DDR_CID_2 = 38 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_08_RESERVED_39_47 = 39 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_08_RESERVED_39_47_LEN = 9 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_08_DDR_ODT = 48 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_08_DDR_ODT_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_08_RESERVED_52_55 = 52 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_08_RESERVED_52_55_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_08_DDR_CAL_TYPE = 56 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_08_DDR_CAL_TYPE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_08_DDR_PARITY = 60 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_08_DDR_BANK_2 = 61 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_08_LOOP_BREAK_MODE = 62 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_08_LOOP_BREAK_MODE_LEN = 2 ;
+
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_09_DDR_ADDRESS_0_13 = 0 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_09_DDR_ADDRESS_0_13_LEN = 14 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_09_DDR_ADDRESS_17 = 14 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_09_DDR_BANK_GROUP_1 = 15 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_09_DDR_RESETN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_09_DDR_BANK_0_1 = 17 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_09_DDR_BANK_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_09_DDR_BANK_GROUP_0 = 19 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_09_DDR_ACTN = 20 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_09_DDR_ADDRESS_16 = 21 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_09_DDR_ADDRESS_15 = 22 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_09_DDR_ADDRESS_14 = 23 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_09_DDR_CKE = 24 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_09_DDR_CKE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_09_RESERVED_28_31 = 28 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_09_RESERVED_28_31_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_09_DDR_CSN_0_1 = 32 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_09_DDR_CSN_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_09_DDR_CID_0_1 = 34 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_09_DDR_CID_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_09_DDR_CSN_2_3 = 36 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_09_DDR_CSN_2_3_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_09_DDR_CID_2 = 38 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_09_RESERVED_39_47 = 39 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_09_RESERVED_39_47_LEN = 9 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_09_DDR_ODT = 48 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_09_DDR_ODT_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_09_RESERVED_52_55 = 52 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_09_RESERVED_52_55_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_09_DDR_CAL_TYPE = 56 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_09_DDR_CAL_TYPE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_09_DDR_PARITY = 60 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_09_DDR_BANK_2 = 61 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_09_LOOP_BREAK_MODE = 62 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_09_LOOP_BREAK_MODE_LEN = 2 ;
+
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_10_DDR_ADDRESS_0_13 = 0 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_10_DDR_ADDRESS_0_13_LEN = 14 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_10_DDR_ADDRESS_17 = 14 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_10_DDR_BANK_GROUP_1 = 15 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_10_DDR_RESETN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_10_DDR_BANK_0_1 = 17 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_10_DDR_BANK_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_10_DDR_BANK_GROUP_0 = 19 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_10_DDR_ACTN = 20 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_10_DDR_ADDRESS_16 = 21 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_10_DDR_ADDRESS_15 = 22 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_10_DDR_ADDRESS_14 = 23 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_10_DDR_CKE = 24 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_10_DDR_CKE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_10_RESERVED_28_31 = 28 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_10_RESERVED_28_31_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_10_DDR_CSN_0_1 = 32 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_10_DDR_CSN_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_10_DDR_CID_0_1 = 34 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_10_DDR_CID_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_10_DDR_CSN_2_3 = 36 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_10_DDR_CSN_2_3_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_10_DDR_CID_2 = 38 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_10_RESERVED_39_47 = 39 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_10_RESERVED_39_47_LEN = 9 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_10_DDR_ODT = 48 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_10_DDR_ODT_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_10_RESERVED_52_55 = 52 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_10_RESERVED_52_55_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_10_DDR_CAL_TYPE = 56 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_10_DDR_CAL_TYPE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_10_DDR_PARITY = 60 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_10_DDR_BANK_2 = 61 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_10_LOOP_BREAK_MODE = 62 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_10_LOOP_BREAK_MODE_LEN = 2 ;
+
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_11_DDR_ADDRESS_0_13 = 0 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_11_DDR_ADDRESS_0_13_LEN = 14 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_11_DDR_ADDRESS_17 = 14 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_11_DDR_BANK_GROUP_1 = 15 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_11_DDR_RESETN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_11_DDR_BANK_0_1 = 17 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_11_DDR_BANK_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_11_DDR_BANK_GROUP_0 = 19 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_11_DDR_ACTN = 20 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_11_DDR_ADDRESS_16 = 21 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_11_DDR_ADDRESS_15 = 22 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_11_DDR_ADDRESS_14 = 23 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_11_DDR_CKE = 24 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_11_DDR_CKE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_11_RESERVED_28_31 = 28 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_11_RESERVED_28_31_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_11_DDR_CSN_0_1 = 32 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_11_DDR_CSN_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_11_DDR_CID_0_1 = 34 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_11_DDR_CID_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_11_DDR_CSN_2_3 = 36 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_11_DDR_CSN_2_3_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_11_DDR_CID_2 = 38 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_11_RESERVED_39_47 = 39 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_11_RESERVED_39_47_LEN = 9 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_11_DDR_ODT = 48 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_11_DDR_ODT_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_11_RESERVED_52_55 = 52 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_11_RESERVED_52_55_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_11_DDR_CAL_TYPE = 56 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_11_DDR_CAL_TYPE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_11_DDR_PARITY = 60 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_11_DDR_BANK_2 = 61 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_11_LOOP_BREAK_MODE = 62 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_11_LOOP_BREAK_MODE_LEN = 2 ;
+
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_12_DDR_ADDRESS_0_13 = 0 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_12_DDR_ADDRESS_0_13_LEN = 14 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_12_DDR_ADDRESS_17 = 14 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_12_DDR_BANK_GROUP_1 = 15 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_12_DDR_RESETN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_12_DDR_BANK_0_1 = 17 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_12_DDR_BANK_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_12_DDR_BANK_GROUP_0 = 19 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_12_DDR_ACTN = 20 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_12_DDR_ADDRESS_16 = 21 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_12_DDR_ADDRESS_15 = 22 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_12_DDR_ADDRESS_14 = 23 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_12_DDR_CKE = 24 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_12_DDR_CKE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_12_RESERVED_28_31 = 28 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_12_RESERVED_28_31_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_12_DDR_CSN_0_1 = 32 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_12_DDR_CSN_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_12_DDR_CID_0_1 = 34 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_12_DDR_CID_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_12_DDR_CSN_2_3 = 36 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_12_DDR_CSN_2_3_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_12_DDR_CID_2 = 38 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_12_RESERVED_39_47 = 39 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_12_RESERVED_39_47_LEN = 9 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_12_DDR_ODT = 48 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_12_DDR_ODT_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_12_RESERVED_52_55 = 52 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_12_RESERVED_52_55_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_12_DDR_CAL_TYPE = 56 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_12_DDR_CAL_TYPE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_12_DDR_PARITY = 60 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_12_DDR_BANK_2 = 61 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_12_LOOP_BREAK_MODE = 62 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_12_LOOP_BREAK_MODE_LEN = 2 ;
+
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_13_DDR_ADDRESS_0 = 0 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_13_DDR_ADDRESS_0_LEN = 14 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_13_DDR_ADDRESS_17 = 14 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_13_DDR_BANK_GROUP_1 = 15 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_13_DDR_RESETN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_13_DDR_BANK_0_1 = 17 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_13_DDR_BANK_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_13_DDR_BANK_GROUP_0 = 19 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_13_DDR_ACTN = 20 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_13_DDR_ADDRESS_16 = 21 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_13_DDR_ADDRESS_15 = 22 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_13_DDR_ADDRESS_14 = 23 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_13_DDR_CKE = 24 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_13_DDR_CKE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_13_RESERVED_28_31 = 28 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_13_RESERVED_28_31_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_13_DDR_CSN_0_1 = 32 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_13_DDR_CSN_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_13_DDR_CID_0_1 = 34 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_13_DDR_CID_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_13_DDR_CSN_2_3 = 36 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_13_DDR_CSN_2_3_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_13_DDR_CID_2 = 38 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_13_RESERVED_39_47 = 39 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_13_RESERVED_39_47_LEN = 9 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_13_DDR_ODT = 48 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_13_DDR_ODT_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_13_RESERVED_52_55 = 52 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_13_RESERVED_52_55_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_13_DDR_CAL_TYPE = 56 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_13_DDR_CAL_TYPE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_13_DDR_PARITY = 60 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_13_DDR_BANK_2 = 61 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_13_LOOP_BREAK_MODE = 62 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_13_LOOP_BREAK_MODE_LEN = 2 ;
+
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_14_DDR_ADDRESS_0_13 = 0 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_14_DDR_ADDRESS_0_13_LEN = 14 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_14_DDR_ADDRESS_17 = 14 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_14_DDR_BANK_GROUP_1 = 15 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_14_DDR_RESETN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_14_DDR_BANK_0_1 = 17 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_14_DDR_BANK_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_14_DDR_BANK_GROUP_0 = 19 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_14_DDR_ACTN = 20 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_14_DDR_ADDRESS_16 = 21 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_14_DDR_ADDRESS_15 = 22 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_14_DDR_ADDRESS = 23 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_14_DDR_CKE = 24 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_14_DDR_CKE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_14_RESERVED_28_31 = 28 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_14_RESERVED_28_31_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_14_DDR_CSN_0_1 = 32 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_14_DDR_CSN_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_14_DDR_CID_0_1 = 34 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_14_DDR_CID_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_14_DDR_CSN_2_3 = 36 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_14_DDR_CSN_2_3_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_14_DDR_CID_2 = 38 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_14_RESERVED_39_47 = 39 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_14_RESERVED_39_47_LEN = 9 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_14_DDR_ODT = 48 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_14_DDR_ODT_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_14_RESERVED_52_55 = 52 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_14_RESERVED_52_55_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_14_DDR_CAL_TYPE = 56 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_14_DDR_CAL_TYPE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_14_DDR_PARITY = 60 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_14_DDR_BANK_2 = 61 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_14_LOOP_BREAK_MODE = 62 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_14_LOOP_BREAK_MODE_LEN = 2 ;
+
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_15_DDR_ADDRESS_0_13 = 0 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_15_DDR_ADDRESS_0_13_LEN = 14 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_15_DDR_ADDRESS_17 = 14 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_15_DDR_BANK_GROUP_1 = 15 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_15_DDR_RESETN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_15_DDR_BANK_0_1 = 17 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_15_DDR_BANK_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_15_DDR_BANK_GROUP_0 = 19 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_15_DDR_ACTN = 20 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_15_DDR_ADDRESS_16 = 21 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_15_DDR_ADDRESS = 22 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_15_DDR_ADDRESS_14 = 23 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_15_DDR_CKE = 24 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_15_DDR_CKE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_15_RESERVED_28_31 = 28 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_15_RESERVED_28_31_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_15_DDR_CSN_0_1 = 32 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_15_DDR_CSN_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_15_DDR_CID_0_1 = 34 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_15_DDR_CID_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_15_DDR_CSN_2_3 = 36 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_15_DDR_CSN_2_3_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_15_DDR_CID_2 = 38 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_15_RESERVED_39_47 = 39 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_15_RESERVED_39_47_LEN = 9 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_15_DDR_ODT = 48 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_15_DDR_ODT_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_15_RESERVED_52_55 = 52 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_15_RESERVED_52_55_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_15_DDR_CAL_TYPE = 56 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_15_DDR_CAL_TYPE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_15_DDR_PARITY = 60 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_15_DDR_BANK_2 = 61 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_15_LOOP_BREAK_MODE = 62 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_15_LOOP_BREAK_MODE_LEN = 2 ;
+
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_16_DDR_ADDRESS_0_13 = 0 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_16_DDR_ADDRESS_0_13_LEN = 14 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_16_DDR_ADDRESS_17 = 14 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_16_DDR_BANK_GROUP_1 = 15 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_16_DDR_RESETN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_16_DDR_BANK_0_1 = 17 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_16_DDR_BANK_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_16_DDR_BANK_GROUP_0 = 19 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_16_DDR_ACTN = 20 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_16_DDR_ADDRESS = 21 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_16_DDR_ADDRESS_15 = 22 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_16_DDR_ADDRESS_14 = 23 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_16_DDR_CKE = 24 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_16_DDR_CKE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_16_RESERVED_28_31 = 28 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_16_RESERVED_28_31_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_16_DDR_CSN_0_1 = 32 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_16_DDR_CSN_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_16_DDR_CID_0_1 = 34 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_16_DDR_CID_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_16_DDR_CSN_2_3 = 36 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_16_DDR_CSN_2_3_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_16_DDR_CID_2 = 38 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_16_RESERVED_39_47 = 39 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_16_RESERVED_39_47_LEN = 9 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_16_DDR_ODT = 48 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_16_DDR_ODT_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_16_RESERVED_52_55 = 52 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_16_RESERVED_52_55_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_16_DDR_CAL_TYPE = 56 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_16_DDR_CAL_TYPE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_16_DDR_PARITY = 60 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_16_DDR_BANK_2 = 61 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_16_LOOP_BREAK_MODE = 62 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_16_LOOP_BREAK_MODE_LEN = 2 ;
+
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_17_DDR_ADDRESS_0_13 = 0 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_17_DDR_ADDRESS_0_13_LEN = 14 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_17_DDR_ADDRESS = 14 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_17_DDR_BANK_GROUP_1 = 15 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_17_DDR_RESETN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_17_DDR_BANK_0_1 = 17 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_17_DDR_BANK_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_17_DDR_BANK_GROUP_0 = 19 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_17_DDR_ACTN = 20 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_17_DDR_ADDRESS_16 = 21 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_17_DDR_ADDRESS_15 = 22 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_17_DDR_ADDRESS_14 = 23 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_17_DDR_CKE = 24 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_17_DDR_CKE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_17_RESERVED_28_31 = 28 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_17_RESERVED_28_31_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_17_DDR_CSN_0_1 = 32 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_17_DDR_CSN_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_17_DDR_CID_0_1 = 34 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_17_DDR_CID_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_17_DDR_CSN_2_3 = 36 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_17_DDR_CSN_2_3_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_17_DDR_CID_2 = 38 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_17_RESERVED_39_47 = 39 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_17_RESERVED_39_47_LEN = 9 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_17_DDR_ODT = 48 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_17_DDR_ODT_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_17_RESERVED_52_55 = 52 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_17_RESERVED_52_55_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_17_DDR_CAL_TYPE = 56 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_17_DDR_CAL_TYPE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_17_DDR_PARITY = 60 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_17_DDR_BANK_2 = 61 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_17_LOOP_BREAK_MODE = 62 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_17_LOOP_BREAK_MODE_LEN = 2 ;
+
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_18_DDR_ADDRESS_0_13 = 0 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_18_DDR_ADDRESS_0_13_LEN = 14 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_18_DDR_ADDRESS_17 = 14 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_18_DDR_BANK_GROUP_1 = 15 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_18_DDR_RESETN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_18_DDR_BANK_0_1 = 17 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_18_DDR_BANK_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_18_DDR_BANK_GROUP_0 = 19 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_18_DDR_ACTN = 20 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_18_DDR_ADDRESS_16 = 21 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_18_DDR_ADDRESS_15 = 22 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_18_DDR_ADDRESS_14 = 23 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_18_DDR_CKE = 24 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_18_DDR_CKE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_18_RESERVED_28_31 = 28 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_18_RESERVED_28_31_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_18_DDR_CSN_0_1 = 32 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_18_DDR_CSN_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_18_DDR_CID_0_1 = 34 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_18_DDR_CID_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_18_DDR_CSN_2_3 = 36 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_18_DDR_CSN_2_3_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_18_DDR_CID_2 = 38 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_18_RESERVED_39_47 = 39 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_18_RESERVED_39_47_LEN = 9 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_18_DDR_ODT = 48 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_18_DDR_ODT_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_18_RESERVED_52_55 = 52 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_18_RESERVED_52_55_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_18_DDR_CAL_TYPE = 56 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_18_DDR_CAL_TYPE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_18_DDR_PARITY = 60 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_18_DDR_BANK_2 = 61 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_18_LOOP_BREAK_MODE = 62 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_18_LOOP_BREAK_MODE_LEN = 2 ;
+
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_19_DDR_ADDRESS_0_13 = 0 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_19_DDR_ADDRESS_0_13_LEN = 14 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_19_DDR_ADDRESS_17 = 14 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_19_DDR_BANK_GROUP_1 = 15 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_19_DDR_RESETN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_19_DDR_BANK_0_1 = 17 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_19_DDR_BANK_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_19_DDR_BANK_GROUP_0 = 19 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_19_DDR_ACTN = 20 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_19_DDR_ADDRESS_16 = 21 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_19_DDR_ADDRESS_15 = 22 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_19_DDR_ADDRESS_14 = 23 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_19_DDR_CKE = 24 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_19_DDR_CKE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_19_RESERVED_28_31 = 28 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_19_RESERVED_28_31_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_19_DDR_CSN_0_1 = 32 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_19_DDR_CSN_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_19_DDR_CID_0_1 = 34 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_19_DDR_CID_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_19_DDR_CSN_2_3 = 36 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_19_DDR_CSN_2_3_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_19_DDR_CID_2 = 38 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_19_RESERVED_39_47 = 39 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_19_RESERVED_39_47_LEN = 9 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_19_DDR_ODT = 48 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_19_DDR_ODT_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_19_RESERVED_52_55 = 52 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_19_RESERVED_52_55_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_19_DDR_CAL_TYPE = 56 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_19_DDR_CAL_TYPE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_19_DDR_PARITY = 60 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_19_DDR_BANK_2 = 61 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_19_LOOP_BREAK_MODE = 62 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_19_LOOP_BREAK_MODE_LEN = 2 ;
+
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_20_DDR_ADDRESS_0_13 = 0 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_20_DDR_ADDRESS_0_13_LEN = 14 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_20_DDR_ADDRESS_17 = 14 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_20_DDR_BANK_GROUP_1 = 15 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_20_DDR_RESETN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_20_DDR_BANK_0_1 = 17 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_20_DDR_BANK_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_20_DDR_BANK_GROUP_0 = 19 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_20_DDR_ACTN = 20 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_20_DDR_ADDRESS_16 = 21 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_20_DDR_ADDRESS_15 = 22 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_20_DDR_ADDRESS_14 = 23 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_20_DDR_CKE = 24 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_20_DDR_CKE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_20_RESERVED_28_31 = 28 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_20_RESERVED_28_31_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_20_DDR_CSN_0_1 = 32 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_20_DDR_CSN_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_20_DDR_CID_0_1 = 34 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_20_DDR_CID_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_20_DDR_CSN_2_3 = 36 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_20_DDR_CSN_2_3_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_20_DDR_CID_2 = 38 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_20_RESERVED_39_47 = 39 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_20_RESERVED_39_47_LEN = 9 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_20_DDR_ODT = 48 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_20_DDR_ODT_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_20_RESERVED_52_55 = 52 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_20_RESERVED_52_55_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_20_DDR_CAL_TYPE = 56 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_20_DDR_CAL_TYPE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_20_DDR_PARITY = 60 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_20_DDR_BANK_2 = 61 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_20_LOOP_BREAK_MODE = 62 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_20_LOOP_BREAK_MODE_LEN = 2 ;
+
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_21_DDR_ADDRESS_0_13 = 0 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_21_DDR_ADDRESS_0_13_LEN = 14 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_21_DDR_ADDRESS_17 = 14 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_21_DDR_BANK_GROUP_1 = 15 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_21_DDR_RESETN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_21_DDR_BANK_0_1 = 17 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_21_DDR_BANK_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_21_DDR_BANK_GROUP_0 = 19 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_21_DDR_ACTN = 20 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_21_DDR_ADDRESS_16 = 21 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_21_DDR_ADDRESS_15 = 22 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_21_DDR_ADDRESS_14 = 23 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_21_DDR_CKE = 24 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_21_DDR_CKE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_21_RESERVED_28_31 = 28 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_21_RESERVED_28_31_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_21_DDR_CSN_0_1 = 32 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_21_DDR_CSN_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_21_DDR_CID_0_1 = 34 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_21_DDR_CID_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_21_DDR_CSN_2_3 = 36 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_21_DDR_CSN_2_3_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_21_DDR_CID_2 = 38 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_21_RESERVED_39_47 = 39 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_21_RESERVED_39_47_LEN = 9 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_21_DDR_ODT = 48 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_21_DDR_ODT_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_21_RESERVED_52_55 = 52 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_21_RESERVED_52_55_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_21_DDR_CAL_TYPE = 56 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_21_DDR_CAL_TYPE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_21_DDR_PARITY = 60 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_21_DDR_BANK_2 = 61 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_21_LOOP_BREAK_MODE = 62 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_21_LOOP_BREAK_MODE_LEN = 2 ;
+
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_22_DDR_ADDRESS_0_13 = 0 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_22_DDR_ADDRESS_0_13_LEN = 14 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_22_DDR_ADDRESS_17 = 14 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_22_DDR_BANK_GROUP_1 = 15 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_22_DDR_RESETN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_22_DDR_BANK_0_1 = 17 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_22_DDR_BANK_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_22_DDR_BANK_GROUP_0 = 19 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_22_DDR_ACTN = 20 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_22_DDR_ADDRESS_16 = 21 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_22_DDR_ADDRESS_15 = 22 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_22_DDR_ADDRESS_14 = 23 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_22_DDR_CKE = 24 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_22_DDR_CKE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_22_RESERVED_28_31 = 28 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_22_RESERVED_28_31_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_22_DDR_CSN_0_1 = 32 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_22_DDR_CSN_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_22_DDR_CID_0_1 = 34 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_22_DDR_CID_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_22_DDR_CSN_2_3 = 36 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_22_DDR_CSN_2_3_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_22_DDR_CID_2 = 38 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_22_RESERVED_39_47 = 39 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_22_RESERVED_39_47_LEN = 9 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_22_DDR_ODT = 48 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_22_DDR_ODT_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_22_RESERVED_52_55 = 52 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_22_RESERVED_52_55_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_22_DDR_CAL_TYPE = 56 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_22_DDR_CAL_TYPE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_22_DDR_PARITY = 60 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_22_DDR_BANK_2 = 61 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_22_LOOP_BREAK_MODE = 62 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_22_LOOP_BREAK_MODE_LEN = 2 ;
+
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_23_DDR_ADDRESS_0_13 = 0 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_23_DDR_ADDRESS_0_13_LEN = 14 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_23_DDR_ADDRESS_17 = 14 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_23_DDR_BANK_GROUP_1 = 15 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_23_DDR_RESETN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_23_DDR_BANK_0_1 = 17 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_23_DDR_BANK_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_23_DDR_BANK_GROUP_0 = 19 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_23_DDR_ACTN = 20 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_23_DDR_ADDRESS_16 = 21 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_23_DDR_ADDRESS_15 = 22 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_23_DDR_ADDRESS_14 = 23 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_23_DDR_CKE = 24 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_23_DDR_CKE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_23_RESERVED_28_31 = 28 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_23_RESERVED_28_31_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_23_DDR_CSN_0_1 = 32 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_23_DDR_CSN_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_23_DDR_CID_0_1 = 34 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_23_DDR_CID_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_23_DDR_CSN_2_3 = 36 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_23_DDR_CSN_2_3_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_23_DDR_CID_2 = 38 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_23_RESERVED_39_47 = 39 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_23_RESERVED_39_47_LEN = 9 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_23_DDR_ODT = 48 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_23_DDR_ODT_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_23_RESERVED_52_55 = 52 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_23_RESERVED_52_55_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_23_DDR_CAL_TYPE = 56 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_23_DDR_CAL_TYPE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_23_DDR_PARITY = 60 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_23_DDR_BANK_2 = 61 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_23_LOOP_BREAK_MODE = 62 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_23_LOOP_BREAK_MODE_LEN = 2 ;
+
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_24_DDR_ADDRESS_0_13 = 0 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_24_DDR_ADDRESS_0_13_LEN = 14 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_24_DDR_ADDRESS_17 = 14 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_24_DDR_BANK_GROUP_1 = 15 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_24_DDR_RESETN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_24_DDR_BANK_0_1 = 17 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_24_DDR_BANK_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_24_DDR_BANK_GROUP_0 = 19 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_24_DDR_ACTN = 20 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_24_DDR_ADDRESS_16 = 21 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_24_DDR_ADDRESS_15 = 22 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_24_DDR_ADDRESS_14 = 23 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_24_DDR_CKE = 24 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_24_DDR_CKE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_24_RESERVED_28_31 = 28 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_24_RESERVED_28_31_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_24_DDR_CSN_0_1 = 32 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_24_DDR_CSN_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_24_DDR_CID_0_1 = 34 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_24_DDR_CID_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_24_DDR_CSN_2_3 = 36 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_24_DDR_CSN_2_3_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_24_DDR_CID_2 = 38 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_24_RESERVED_39_47 = 39 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_24_RESERVED_39_47_LEN = 9 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_24_DDR_ODT = 48 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_24_DDR_ODT_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_24_RESERVED_52_55 = 52 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_24_RESERVED_52_55_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_24_DDR_CAL_TYPE = 56 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_24_DDR_CAL_TYPE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_24_DDR_PARITY = 60 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_24_DDR_BANK_2 = 61 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_24_LOOP_BREAK_MODE = 62 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_24_LOOP_BREAK_MODE_LEN = 2 ;
+
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_25_DDR_ADDRESS_0_13 = 0 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_25_DDR_ADDRESS_0_13_LEN = 14 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_25_DDR_ADDRESS_17 = 14 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_25_DDR_BANK_GROUP_1 = 15 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_25_DDR_RESETN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_25_DDR_BANK_0_1 = 17 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_25_DDR_BANK_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_25_DDR_BANK_GROUP_0 = 19 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_25_DDR_ACTN = 20 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_25_DDR_ADDRESS_16 = 21 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_25_DDR_ADDRESS_15 = 22 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_25_DDR_ADDRESS_14 = 23 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_25_DDR_CKE = 24 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_25_DDR_CKE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_25_RESERVED_28_31 = 28 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_25_RESERVED_28_31_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_25_DDR_CSN_0_1 = 32 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_25_DDR_CSN_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_25_DDR_CID_0_1 = 34 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_25_DDR_CID_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_25_DDR_CSN_2_3 = 36 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_25_DDR_CSN_2_3_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_25_DDR_CID_2 = 38 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_25_RESERVED_39_47 = 39 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_25_RESERVED_39_47_LEN = 9 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_25_DDR_ODT = 48 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_25_DDR_ODT_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_25_RESERVED_52_55 = 52 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_25_RESERVED_52_55_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_25_DDR_CAL_TYPE = 56 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_25_DDR_CAL_TYPE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_25_DDR_PARITY = 60 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_25_DDR_BANK_2 = 61 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_25_LOOP_BREAK_MODE = 62 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_25_LOOP_BREAK_MODE_LEN = 2 ;
+
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_26_DDR_ADDRESS_0_13 = 0 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_26_DDR_ADDRESS_0_13_LEN = 14 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_26_DDR_ADDRESS_17 = 14 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_26_DDR_BANK_GROUP_1 = 15 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_26_DDR_RESETN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_26_DDR_BANK_0_1 = 17 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_26_DDR_BANK_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_26_DDR_BANK_GROUP_0 = 19 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_26_DDR_ACTN = 20 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_26_DDR_ADDRESS_16 = 21 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_26_DDR_ADDRESS_15 = 22 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_26_DDR_ADDRESS_14 = 23 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_26_DDR_CKE = 24 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_26_DDR_CKE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_26_RESERVED_28_31 = 28 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_26_RESERVED_28_31_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_26_DDR_CSN_0_1 = 32 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_26_DDR_CSN_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_26_DDR_CID_0_1 = 34 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_26_DDR_CID_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_26_DDR_CSN_2_3 = 36 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_26_DDR_CSN_2_3_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_26_DDR_CID_2 = 38 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_26_RESERVED_39_47 = 39 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_26_RESERVED_39_47_LEN = 9 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_26_DDR_ODT = 48 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_26_DDR_ODT_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_26_RESERVED_52_55 = 52 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_26_RESERVED_52_55_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_26_DDR_CAL_TYPE = 56 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_26_DDR_CAL_TYPE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_26_DDR_PARITY = 60 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_26_DDR_BANK_2 = 61 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_26_LOOP_BREAK_MODE = 62 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_26_LOOP_BREAK_MODE_LEN = 2 ;
+
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_27_DDR_ADDRESS_0_13 = 0 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_27_DDR_ADDRESS_0_13_LEN = 14 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_27_DDR_ADDRESS_17 = 14 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_27_DDR_BANK_GROUP_1 = 15 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_27_DDR_RESETN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_27_DDR_BANK_0_1 = 17 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_27_DDR_BANK_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_27_DDR_BANK_GROUP_0 = 19 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_27_DDR_ACTN = 20 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_27_DDR_ADDRESS_16 = 21 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_27_DDR_ADDRESS_15 = 22 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_27_DDR_ADDRESS_14 = 23 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_27_DDR_CKE = 24 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_27_DDR_CKE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_27_RESERVED_28_31 = 28 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_27_RESERVED_28_31_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_27_DDR_CSN_0_1 = 32 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_27_DDR_CSN_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_27_DDR_CID_0_1 = 34 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_27_DDR_CID_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_27_DDR_CSN_2_3 = 36 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_27_DDR_CSN_2_3_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_27_DDR_CID_2 = 38 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_27_RESERVED_39_47 = 39 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_27_RESERVED_39_47_LEN = 9 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_27_DDR_ODT = 48 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_27_DDR_ODT_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_27_RESERVED_52_55 = 52 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_27_RESERVED_52_55_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_27_DDR_CAL_TYPE = 56 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_27_DDR_CAL_TYPE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_27_DDR_PARITY = 60 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_27_DDR_BANK_2 = 61 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_27_LOOP_BREAK_MODE = 62 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_27_LOOP_BREAK_MODE_LEN = 2 ;
+
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_28_DDR_ADDRESS_0_13 = 0 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_28_DDR_ADDRESS_0_13_LEN = 14 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_28_DDR_ADDRESS_17 = 14 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_28_DDR_BANK_GROUP_1 = 15 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_28_DDR_RESETN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_28_DDR_BANK_0_1 = 17 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_28_DDR_BANK_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_28_DDR_BANK_GROUP_0 = 19 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_28_DDR_ACTN = 20 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_28_DDR_ADDRESS_16 = 21 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_28_DDR_ADDRESS_15 = 22 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_28_DDR_ADDRESS_14 = 23 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_28_DDR_CKE = 24 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_28_DDR_CKE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_28_RESERVED_31 = 28 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_28_RESERVED_31_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_28_DDR_CSN_0_1 = 32 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_28_DDR_CSN_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_28_DDR_CID_0_1 = 34 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_28_DDR_CID_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_28_DDR_CSN_2_3 = 36 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_28_DDR_CSN_2_3_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_28_DDR_CID_2 = 38 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_28_RESERVED_39_47 = 39 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_28_RESERVED_39_47_LEN = 9 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_28_DDR_ODT = 48 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_28_DDR_ODT_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_28_RESERVED_52_55 = 52 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_28_RESERVED_52_55_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_28_DDR_CAL_TYPE = 56 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_28_DDR_CAL_TYPE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_28_DDR_PARITY = 60 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_28_DDR_BANK_2 = 61 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_28_LOOP_BREAK_MODE = 62 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_28_LOOP_BREAK_MODE_LEN = 2 ;
+
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_29_DDR_ADDRESS_0_13 = 0 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_29_DDR_ADDRESS_0_13_LEN = 14 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_29_DDR_ADDRESS_17 = 14 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_29_DDR_BANK_GROUP_1 = 15 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_29_DDR_RESETN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_29_DDR_BANK_0_1 = 17 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_29_DDR_BANK_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_29_DDR_BANK_GROUP_0 = 19 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_29_DDR_ACTN = 20 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_29_DDR_ADDRESS_16 = 21 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_29_DDR_ADDRESS_15 = 22 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_29_DDR_ADDRESS_14 = 23 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_29_DDR_CKE = 24 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_29_DDR_CKE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_29_RESERVED_28_31 = 28 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_29_RESERVED_28_31_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_29_DDR_CSN_0_1 = 32 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_29_DDR_CSN_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_29_DDR_CID_0_1 = 34 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_29_DDR_CID_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_29_DDR_CSN_2_3 = 36 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_29_DDR_CSN_2_3_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_29_DDR_CID_2 = 38 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_29_RESERVED_39_47 = 39 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_29_RESERVED_39_47_LEN = 9 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_29_DDR_ODT = 48 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_29_DDR_ODT_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_29_RESERVED_52_55 = 52 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_29_RESERVED_52_55_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_29_DDR_CAL_TYPE = 56 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_29_DDR_CAL_TYPE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_29_DDR_PARITY = 60 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_29_DDR_BANK_2 = 61 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_29_LOOP_BREAK_MODE = 62 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_29_LOOP_BREAK_MODE_LEN = 2 ;
+
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_30_DDR_ADDRESS_0_13 = 0 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_30_DDR_ADDRESS_0_13_LEN = 14 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_30_DDR_ADDRESS_17 = 14 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_30_DDR_BANK_GROUP_1 = 15 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_30_DDR_RESETN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_30_DDR_BANK_0_1 = 17 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_30_DDR_BANK_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_30_DDR_BANK_GROUP_0 = 19 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_30_DDR_ACTN = 20 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_30_DDR_ADDRESS_16 = 21 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_30_DDR_ADDRESS_15 = 22 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_30_DDR_ADDRESS_14 = 23 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_30_DDR_CKE = 24 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_30_DDR_CKE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_30_RESERVED_28_31 = 28 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_30_RESERVED_28_31_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_30_DDR_CSN_0_1 = 32 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_30_DDR_CSN_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_30_DDR_CID_0_1 = 34 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_30_DDR_CID_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_30_DDR_CSN_2_3 = 36 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_30_DDR_CSN_2_3_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_30_DDR_CID_2 = 38 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_30_RESERVED_39_47 = 39 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_30_RESERVED_39_47_LEN = 9 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_30_DDR_ODT = 48 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_30_DDR_ODT_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_30_RESERVED_52_55 = 52 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_30_RESERVED_52_55_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_30_DDR_CAL_TYPE = 56 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_30_DDR_CAL_TYPE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_30_DDR_PARITY = 60 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_30_DDR_BANK_2 = 61 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_30_LOOP_BREAK_MODE = 62 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_30_LOOP_BREAK_MODE_LEN = 2 ;
+
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_31_DDR_ADDRESS_0_13 = 0 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_31_DDR_ADDRESS_0_13_LEN = 14 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_31_DDR_ADDRESS_17 = 14 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_31_DDR_BANK_GROUP_1 = 15 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_31_DDR_RESETN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_31_DDR_BANK_0_1 = 17 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_31_DDR_BANK_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_31_DDR_BANK_GROUP_0 = 19 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_31_DDR_ACTN = 20 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_31_DDR_ADDRESS_16 = 21 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_31_DDR_ADDRESS_15 = 22 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_31_DDR_ADDRESS_14 = 23 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_31_DDR_CKE = 24 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_31_DDR_CKE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_31_RESERVED_28 = 28 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_31_RESERVED_28_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_31_DDR_CSN_0_1 = 32 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_31_DDR_CSN_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_31_DDR_CID_0_1 = 34 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_31_DDR_CID_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_31_DDR_CSN_2_3 = 36 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_31_DDR_CSN_2_3_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_31_DDR_CID_2 = 38 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_31_RESERVED_39_47 = 39 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_31_RESERVED_39_47_LEN = 9 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_31_DDR_ODT = 48 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_31_DDR_ODT_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_31_RESERVED_52_55 = 52 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_31_RESERVED_52_55_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_31_DDR_CAL_TYPE = 56 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_31_DDR_CAL_TYPE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_31_DDR_PARITY = 60 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_31_DDR_BANK_2 = 61 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_31_LOOP_BREAK_MODE = 62 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_31_LOOP_BREAK_MODE_LEN = 2 ;
+
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_00_IDLES = 0 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_00_IDLES_LEN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_00_REPEAT_CMD_CNT = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_00_REPEAT_CMD_CNT_LEN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_00_READ_OR_WRITE_DATA = 32 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_00_READ_OR_WRITE_DATA_LEN = 20 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_00_READ_COMPARE_REQUIRED = 52 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_00_DDR_CAL_RANK = 53 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_00_DDR_CAL_RANK_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_00_DDR_CALIBRATION_ENABLE = 57 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_00_END = 58 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_00_GOTO_CMD = 59 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_00_GOTO_CMD_LEN = 5 ;
+
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_01_IDLES = 0 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_01_IDLES_LEN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_01_REPEAT_CMD_CNT = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_01_REPEAT_CMD_CNT_LEN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_01_READ_OR_WRITE_DATA = 32 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_01_READ_OR_WRITE_DATA_LEN = 20 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_01_READ_COMPARE_REQUIRED = 52 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_01_DDR_CAL_RANK = 53 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_01_DDR_CAL_RANK_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_01_DDR_CALIBRATION_ENABLE = 57 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_01_END = 58 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_01_GOTO_CMD = 59 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_01_GOTO_CMD_LEN = 5 ;
+
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_02_IDLES = 0 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_02_IDLES_LEN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_02_REPEAT_CMD_CNT = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_02_REPEAT_CMD_CNT_LEN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_02_READ_OR_WRITE_DATA = 32 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_02_READ_OR_WRITE_DATA_LEN = 20 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_02_READ_COMPARE_REQUIRED = 52 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_02_DDR_CAL_RANK = 53 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_02_DDR_CAL_RANK_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_02_DDR_CALIBRATION_ENABLE = 57 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_02_END = 58 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_02_GOTO_CMD = 59 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_02_GOTO_CMD_LEN = 5 ;
+
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_03_IDLES = 0 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_03_IDLES_LEN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_03_REPEAT_CMD_CNT = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_03_REPEAT_CMD_CNT_LEN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_03_READ_OR_WRITE_DATA = 32 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_03_READ_OR_WRITE_DATA_LEN = 20 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_03_READ_COMPARE_REQUIRED = 52 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_03_DDR_CAL_RANK = 53 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_03_DDR_CAL_RANK_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_03_DDR_CALIBRATION_ENABLE = 57 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_03_END = 58 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_03_GOTO_CMD = 59 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_03_GOTO_CMD_LEN = 5 ;
+
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_04_IDLES = 0 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_04_IDLES_LEN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_04_REPEAT_CMD_CNT = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_04_REPEAT_CMD_CNT_LEN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_04_READ_OR_WRITE_DATA = 32 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_04_READ_OR_WRITE_DATA_LEN = 20 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_04_READ_COMPARE_REQUIRED = 52 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_04_DDR_CAL_RANK = 53 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_04_DDR_CAL_RANK_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_04_DDR_CALIBRATION_ENABLE = 57 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_04_END = 58 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_04_GOTO_CMD = 59 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_04_GOTO_CMD_LEN = 5 ;
+
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_05_IDLES = 0 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_05_IDLES_LEN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_05_REPEAT_CMD_CNT = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_05_REPEAT_CMD_CNT_LEN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_05_READ_OR_WRITE_DATA = 32 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_05_READ_OR_WRITE_DATA_LEN = 20 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_05_READ_COMPARE_REQUIRED = 52 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_05_DDR_CAL_RANK = 53 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_05_DDR_CAL_RANK_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_05_DDR_CALIBRATION_ENABLE = 57 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_05_END = 58 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_05_GOTO_CMD = 59 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_05_GOTO_CMD_LEN = 5 ;
+
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_06_IDLES = 0 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_06_IDLES_LEN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_06_REPEAT_CMD_CNT = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_06_REPEAT_CMD_CNT_LEN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_06_READ_OR_WRITE_DATA = 32 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_06_READ_OR_WRITE_DATA_LEN = 20 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_06_READ_COMPARE_REQUIRED = 52 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_06_DDR_CAL_RANK = 53 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_06_DDR_CAL_RANK_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_06_DDR_CALIBRATION_ENABLE = 57 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_06_END = 58 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_06_GOTO_CMD = 59 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_06_GOTO_CMD_LEN = 5 ;
+
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_07_IDLES = 0 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_07_IDLES_LEN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_07_REPEAT_CMD_CNT = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_07_REPEAT_CMD_CNT_LEN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_07_READ_OR_WRITE_DATA = 32 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_07_READ_OR_WRITE_DATA_LEN = 20 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_07_READ_COMPARE_REQUIRED = 52 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_07_DDR_CAL_RANK = 53 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_07_DDR_CAL_RANK_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_07_DDR_CALIBRATION_ENABLE = 57 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_07_END = 58 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_07_GOTO_CMD = 59 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_07_GOTO_CMD_LEN = 5 ;
+
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_08_IDLES = 0 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_08_IDLES_LEN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_08_REPEAT_CMD_CNT = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_08_REPEAT_CMD_CNT_LEN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_08_READ_OR_WRITE_DATA = 32 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_08_READ_OR_WRITE_DATA_LEN = 20 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_08_READ_COMPARE_REQUIRED = 52 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_08_DDR_CAL_RANK = 53 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_08_DDR_CAL_RANK_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_08_DDR_CALIBRATION_ENABLE = 57 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_08_END = 58 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_08_GOTO_CMD = 59 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_08_GOTO_CMD_LEN = 5 ;
+
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_09_IDLES = 0 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_09_IDLES_LEN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_09_REPEAT_CMD_CNT = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_09_REPEAT_CMD_CNT_LEN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_09_READ_OR_WRITE_DATA = 32 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_09_READ_OR_WRITE_DATA_LEN = 20 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_09_READ_COMPARE_REQUIRED = 52 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_09_DDR_CAL_RANK = 53 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_09_DDR_CAL_RANK_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_09_DDR_CALIBRATION_ENABLE = 57 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_09_END = 58 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_09_GOTO_CMD = 59 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_09_GOTO_CMD_LEN = 5 ;
+
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_10_IDLES = 0 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_10_IDLES_LEN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_10_REPEAT_CMD_CNT = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_10_REPEAT_CMD_CNT_LEN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_10_READ_OR_WRITE_DATA = 32 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_10_READ_OR_WRITE_DATA_LEN = 20 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_10_READ_COMPARE_REQUIRED = 52 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_10_DDR_CAL_RANK = 53 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_10_DDR_CAL_RANK_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_10_DDR_CALIBRATION_ENABLE = 57 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_10_END = 58 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_10_GOTO_CMD = 59 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_10_GOTO_CMD_LEN = 5 ;
+
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_11_IDLES = 0 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_11_IDLES_LEN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_11_REPEAT_CMD_CNT = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_11_REPEAT_CMD_CNT_LEN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_11_READ_OR_WRITE_DATA = 32 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_11_READ_OR_WRITE_DATA_LEN = 20 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_11_READ_COMPARE_REQUIRED = 52 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_11_DDR_CAL_RANK = 53 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_11_DDR_CAL_RANK_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_11_DDR_CALIBRATION_ENABLE = 57 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_11_END = 58 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_11_GOTO_CMD = 59 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_11_GOTO_CMD_LEN = 5 ;
+
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_12_IDLES = 0 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_12_IDLES_LEN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_12_REPEAT_CMD_CNT = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_12_REPEAT_CMD_CNT_LEN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_12_READ_OR_WRITE_DATA = 32 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_12_READ_OR_WRITE_DATA_LEN = 20 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_12_READ_COMPARE_REQUIRED = 52 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_12_DDR_CAL_RANK = 53 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_12_DDR_CAL_RANK_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_12_DDR_CALIBRATION_ENABLE = 57 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_12_END = 58 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_12_GOTO_CMD = 59 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_12_GOTO_CMD_LEN = 5 ;
+
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_13_IDLES = 0 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_13_IDLES_LEN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_13_REPEAT_CMD_CNT = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_13_REPEAT_CMD_CNT_LEN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_13_READ_OR_WRITE_DATA = 32 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_13_READ_OR_WRITE_DATA_LEN = 20 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_13_READ_COMPARE_REQUIRED = 52 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_13_DDR_CAL_RANK = 53 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_13_DDR_CAL_RANK_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_13_DDR_CALIBRATION_ENABLE = 57 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_13_END = 58 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_13_GOTO_CMD = 59 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_13_GOTO_CMD_LEN = 5 ;
+
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_14_IDLES = 0 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_14_IDLES_LEN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_14_REPEAT_CMD_CNT = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_14_REPEAT_CMD_CNT_LEN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_14_READ_OR_WRITE_DATA = 32 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_14_READ_OR_WRITE_DATA_LEN = 20 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_14_READ_COMPARE_REQUIRED = 52 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_14_DDR_CAL_RANK = 53 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_14_DDR_CAL_RANK_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_14_DDR_CALIBRATION_ENABLE = 57 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_14_END = 58 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_14_GOTO_CMD = 59 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_14_GOTO_CMD_LEN = 5 ;
+
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_15_IDLES = 0 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_15_IDLES_LEN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_15_REPEAT_CMD_CNT = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_15_REPEAT_CMD_CNT_LEN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_15_READ_OR_WRITE_DATA = 32 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_15_READ_OR_WRITE_DATA_LEN = 20 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_15_READ_COMPARE_REQUIRED = 52 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_15_DDR_CAL_RANK = 53 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_15_DDR_CAL_RANK_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_15_DDR_CALIBRATION_ENABLE = 57 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_15_END = 58 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_15_GOTO_CMD = 59 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_15_GOTO_CMD_LEN = 5 ;
+
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_16_IDLES = 0 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_16_IDLES_LEN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_16_REPEAT_CMD_CNT = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_16_REPEAT_CMD_CNT_LEN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_16_READ_OR_WRITE_DATA = 32 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_16_READ_OR_WRITE_DATA_LEN = 20 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_16_READ_COMPARE_REQUIRED = 52 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_16_DDR_CAL_RANK = 53 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_16_DDR_CAL_RANK_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_16_DDR_CALIBRATION_ENABLE = 57 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_16_END = 58 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_16_GOTO_CMD = 59 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_16_GOTO_CMD_LEN = 5 ;
+
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_17_IDLES = 0 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_17_IDLES_LEN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_17_REPEAT_CMD_CNT = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_17_REPEAT_CMD_CNT_LEN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_17_READ_OR_WRITE_DATA = 32 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_17_READ_OR_WRITE_DATA_LEN = 20 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_17_READ_COMPARE_REQUIRED = 52 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_17_DDR_CAL_RANK = 53 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_17_DDR_CAL_RANK_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_17_DDR_CALIBRATION_ENABLE = 57 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_17_END = 58 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_17_GOTO_CMD = 59 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_17_GOTO_CMD_LEN = 5 ;
+
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_18_IDLES = 0 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_18_IDLES_LEN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_18_REPEAT_CMD_CNT = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_18_REPEAT_CMD_CNT_LEN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_18_READ_OR_WRITE_DATA = 32 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_18_READ_OR_WRITE_DATA_LEN = 20 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_18_READ_COMPARE_REQUIRED = 52 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_18_DDR_CAL_RANK = 53 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_18_DDR_CAL_RANK_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_18_DDR_CALIBRATION_ENABLE = 57 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_18_END = 58 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_18_GOTO_CMD = 59 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_18_GOTO_CMD_LEN = 5 ;
+
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_19_IDLES = 0 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_19_IDLES_LEN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_19_REPEAT_CMD_CNT = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_19_REPEAT_CMD_CNT_LEN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_19_READ_OR_WRITE_DATA = 32 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_19_READ_OR_WRITE_DATA_LEN = 20 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_19_READ_COMPARE_REQUIRED = 52 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_19_DDR_CAL_RANK = 53 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_19_DDR_CAL_RANK_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_19_DDR_CALIBRATION_ENABLE = 57 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_19_END = 58 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_19_GOTO_CMD = 59 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_19_GOTO_CMD_LEN = 5 ;
+
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_20_IDLES = 0 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_20_IDLES_LEN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_20_REPEAT_CMD_CNT = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_20_REPEAT_CMD_CNT_LEN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_20_READ_OR_WRITE_DATA = 32 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_20_READ_OR_WRITE_DATA_LEN = 20 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_20_READ_COMPARE_REQUIRED = 52 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_20_DDR_CAL_RANK = 53 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_20_DDR_CAL_RANK_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_20_DDR_CALIBRATION_ENABLE = 57 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_20_END = 58 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_20_GOTO_CMD = 59 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_20_GOTO_CMD_LEN = 5 ;
+
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_21_IDLES = 0 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_21_IDLES_LEN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_21_REPEAT_CMD_CNT = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_21_REPEAT_CMD_CNT_LEN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_21_READ_OR_WRITE_DATA = 32 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_21_READ_OR_WRITE_DATA_LEN = 20 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_21_READ_COMPARE_REQUIRED = 52 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_21_DDR_CAL_RANK = 53 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_21_DDR_CAL_RANK_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_21_DDR_CALIBRATION_ENABLE = 57 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_21_END = 58 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_21_GOTO_CMD = 59 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_21_GOTO_CMD_LEN = 5 ;
+
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_22_IDLES = 0 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_22_IDLES_LEN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_22_REPEAT_CMD_CNT = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_22_REPEAT_CMD_CNT_LEN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_22_READ_OR_WRITE_DATA = 32 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_22_READ_OR_WRITE_DATA_LEN = 20 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_22_READ_COMPARE_REQUIRED = 52 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_22_DDR_CAL_RANK = 53 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_22_DDR_CAL_RANK_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_22_DDR_CALIBRATION_ENABLE = 57 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_22_END = 58 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_22_GOTO_CMD = 59 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_22_GOTO_CMD_LEN = 5 ;
+
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_23_IDLES = 0 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_23_IDLES_LEN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_23_REPEAT_CMD_CNT = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_23_REPEAT_CMD_CNT_LEN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_23_READ_OR_WRITE_DATA = 32 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_23_READ_OR_WRITE_DATA_LEN = 20 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_23_READ_COMPARE_REQUIRED = 52 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_23_DDR_CAL_RANK = 53 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_23_DDR_CAL_RANK_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_23_DDR_CALIBRATION_ENABLE = 57 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_23_END = 58 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_23_GOTO_CMD = 59 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_23_GOTO_CMD_LEN = 5 ;
+
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_24_IDLES = 0 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_24_IDLES_LEN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_24_REPEAT_CMD_CNT = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_24_REPEAT_CMD_CNT_LEN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_24_READ_OR_WRITE_DATA = 32 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_24_READ_OR_WRITE_DATA_LEN = 20 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_24_READ_COMPARE_REQUIRED = 52 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_24_DDR_CAL_RANK = 53 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_24_DDR_CAL_RANK_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_24_DDR_CALIBRATION_ENABLE = 57 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_24_END = 58 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_24_GOTO_CMD = 59 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_24_GOTO_CMD_LEN = 5 ;
+
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_25_IDLES = 0 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_25_IDLES_LEN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_25_REPEAT_CMD_CNT = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_25_REPEAT_CMD_CNT_LEN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_25_READ_OR_WRITE_DATA = 32 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_25_READ_OR_WRITE_DATA_LEN = 20 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_25_READ_COMPARE_REQUIRED = 52 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_25_DDR_CAL_RANK = 53 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_25_DDR_CAL_RANK_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_25_DDR_CALIBRATION_ENABLE = 57 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_25_END = 58 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_25_GOTO_CMD = 59 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_25_GOTO_CMD_LEN = 5 ;
+
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_26_IDLES = 0 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_26_IDLES_LEN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_26_REPEAT_CMD_CNT = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_26_REPEAT_CMD_CNT_LEN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_26_READ_OR_WRITE_DATA = 32 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_26_READ_OR_WRITE_DATA_LEN = 20 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_26_READ_COMPARE_REQUIRED = 52 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_26_DDR_CAL_RANK = 53 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_26_DDR_CAL_RANK_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_26_DDR_CALIBRATION_ENABLE = 57 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_26_END = 58 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_26_GOTO_CMD = 59 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_26_GOTO_CMD_LEN = 5 ;
+
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_27_IDLES = 0 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_27_IDLES_LEN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_27_REPEAT_CMD_CNT = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_27_REPEAT_CMD_CNT_LEN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_27_READ_OR_WRITE_DATA = 32 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_27_READ_OR_WRITE_DATA_LEN = 20 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_27_READ_COMPARE_REQUIRED = 52 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_27_DDR_CAL_RANK = 53 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_27_DDR_CAL_RANK_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_27_DDR_CALIBRATION_ENABLE = 57 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_27_END = 58 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_27_GOTO_CMD = 59 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_27_GOTO_CMD_LEN = 5 ;
+
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_28_IDLES = 0 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_28_IDLES_LEN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_28_REPEAT_CMD_CNT = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_28_REPEAT_CMD_CNT_LEN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_28_READ_OR_WRITE_DATA = 32 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_28_READ_OR_WRITE_DATA_LEN = 20 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_28_READ_COMPARE_REQUIRED = 52 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_28_DDR_CAL_RANK = 53 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_28_DDR_CAL_RANK_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_28_DDR_CALIBRATION_ENABLE = 57 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_28_END = 58 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_28_GOTO_CMD = 59 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_28_GOTO_CMD_LEN = 5 ;
+
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_29_IDLES = 0 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_29_IDLES_LEN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_29_REPEAT_CMD_CNT = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_29_REPEAT_CMD_CNT_LEN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_29_READ_OR_WRITE_DATA = 32 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_29_READ_OR_WRITE_DATA_LEN = 20 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_29_READ_COMPARE_REQUIRED = 52 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_29_DDR_CAL_RANK = 53 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_29_DDR_CAL_RANK_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_29_DDR_CALIBRATION_ENABLE = 57 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_29_END = 58 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_29_GOTO_CMD = 59 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_29_GOTO_CMD_LEN = 5 ;
+
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_30_IDLES = 0 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_30_IDLES_LEN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_30_REPEAT_CMD_CNT = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_30_REPEAT_CMD_CNT_LEN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_30_READ_OR_WRITE_DATA = 32 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_30_READ_OR_WRITE_DATA_LEN = 20 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_30_READ_COMPARE_REQUIRED = 52 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_30_DDR_CAL_RANK = 53 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_30_DDR_CAL_RANK_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_30_DDR_CALIBRATION_ENABLE = 57 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_30_END = 58 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_30_GOTO_CMD = 59 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_30_GOTO_CMD_LEN = 5 ;
+
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_31_IDLES = 0 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_31_IDLES_LEN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_31_REPEAT_CMD_CNT = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_31_REPEAT_CMD_CNT_LEN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_31_READ_OR_WRITE_DATA = 32 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_31_READ_OR_WRITE_DATA_LEN = 20 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_31_READ_COMPARE_REQUIRED = 52 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_31_DDR_CAL_RANK = 53 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_31_DDR_CAL_RANK_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_31_DDR_CALIBRATION_ENABLE = 57 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_31_END = 58 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_31_GOTO_CMD = 59 ;
+static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_31_GOTO_CMD_LEN = 5 ;
+
+static const uint8_t P9N2_MCBIST_CCS_MODEQ_STOP_ON_ERR = 0 ;
+static const uint8_t P9N2_MCBIST_CCS_MODEQ_UE_DISABLE = 1 ;
+static const uint8_t P9N2_MCBIST_CCS_MODEQ_DATA_COMPARE_BURST_SEL = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_MODEQ_DATA_COMPARE_BURST_SEL_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_MODEQ_RESERVED_4_7 = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_MODEQ_RESERVED_4_7_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_MODEQ_DDR_CAL_TIMEOUT_CNT = 8 ;
+static const uint8_t P9N2_MCBIST_CCS_MODEQ_DDR_CAL_TIMEOUT_CNT_LEN = 16 ;
+static const uint8_t P9N2_MCBIST_CCS_MODEQ_CFG_PARITY_AFTER_CMD = 24 ;
+static const uint8_t P9N2_MCBIST_CCS_MODEQ_RESERVED_25 = 25 ;
+static const uint8_t P9N2_MCBIST_CCS_MODEQ_COPY_CKE_TO_SPARE_CKE = 26 ;
+static const uint8_t P9N2_MCBIST_CCS_MODEQ_DISABLE_ECC_ARRAY_CHK = 27 ;
+static const uint8_t P9N2_MCBIST_CCS_MODEQ_DISABLE_ECC_ARRAY_CORRECTION = 28 ;
+static const uint8_t P9N2_MCBIST_CCS_MODEQ_CFG_DGEN_FIXED_MODE = 29 ;
+static const uint8_t P9N2_MCBIST_CCS_MODEQ_DDR_CAL_TIMEOUT_CNT_MULT = 30 ;
+static const uint8_t P9N2_MCBIST_CCS_MODEQ_DDR_CAL_TIMEOUT_CNT_MULT_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_MODEQ_IDLE_PAT_ADDRESS_0_13 = 32 ;
+static const uint8_t P9N2_MCBIST_CCS_MODEQ_IDLE_PAT_ADDRESS_0_13_LEN = 14 ;
+static const uint8_t P9N2_MCBIST_CCS_MODEQ_IDLE_PAT_ADDRESS_17 = 46 ;
+static const uint8_t P9N2_MCBIST_CCS_MODEQ_IDLE_PAT_BANK_GROUP_1 = 47 ;
+static const uint8_t P9N2_MCBIST_CCS_MODEQ_IDLE_PAT_BANK_0_1 = 48 ;
+static const uint8_t P9N2_MCBIST_CCS_MODEQ_IDLE_PAT_BANK_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_MODEQ_IDLE_PAT_BANK_GROUP_0 = 50 ;
+static const uint8_t P9N2_MCBIST_CCS_MODEQ_IDLE_PAT_ACTN = 51 ;
+static const uint8_t P9N2_MCBIST_CCS_MODEQ_IDLE_PAT_ADDRESS_16 = 52 ;
+static const uint8_t P9N2_MCBIST_CCS_MODEQ_IDLE_PAT_ADDRESS_15 = 53 ;
+static const uint8_t P9N2_MCBIST_CCS_MODEQ_IDLE_PAT_ADDRESS_14 = 54 ;
+static const uint8_t P9N2_MCBIST_CCS_MODEQ_NTTM_MODE = 55 ;
+static const uint8_t P9N2_MCBIST_CCS_MODEQ_NTTM_RW_DATA_DLY = 56 ;
+static const uint8_t P9N2_MCBIST_CCS_MODEQ_NTTM_RW_DATA_DLY_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_CCS_MODEQ_IDLE_PAT_BANK_2 = 60 ;
+static const uint8_t P9N2_MCBIST_CCS_MODEQ_DDR_PARITY_ENABLE = 61 ;
+static const uint8_t P9N2_MCBIST_CCS_MODEQ_IDLE_PAT_PARITY = 62 ;
+static const uint8_t P9N2_MCBIST_CCS_MODEQ_RESERVED_63 = 63 ;
+
+static const uint8_t P9N2_MCBIST_CCS_STATQ_IP = 0 ;
+static const uint8_t P9N2_MCBIST_CCS_STATQ_DONE = 1 ;
+static const uint8_t P9N2_MCBIST_CCS_STATQ_FAIL = 2 ;
+static const uint8_t P9N2_MCBIST_CCS_STATQ_FAIL_TYPE = 3 ;
+static const uint8_t P9N2_MCBIST_CCS_STATQ_FAIL_TYPE_LEN = 3 ;
+static const uint8_t P9N2_MCBIST_CCS_STATQ_MCBIST_SUBTEST_IP = 6 ;
+static const uint8_t P9N2_MCBIST_CCS_STATQ_FAIL_RCD = 7 ;
+
+static const uint8_t P9N2_MCA_CERR0_RECR_PE = 10 ;
+static const uint8_t P9N2_MCA_CERR0_DBGR_PE = 11 ;
+static const uint8_t P9N2_MCA_CERR0_MSR_PE = 12 ;
+static const uint8_t P9N2_MCA_CERR0_EICR_PE = 13 ;
+static const uint8_t P9N2_MCA_CERR0_HWMSX_PE = 16 ;
+static const uint8_t P9N2_MCA_CERR0_HWMSX_PE_LEN = 8 ;
+static const uint8_t P9N2_MCA_CERR0_FWMSX_PE = 24 ;
+static const uint8_t P9N2_MCA_CERR0_FWMSX_PE_LEN = 8 ;
+static const uint8_t P9N2_MCA_CERR0_WECR_PE = 40 ;
+static const uint8_t P9N2_MCA_CERR0_AACR_PE = 41 ;
+static const uint8_t P9N2_MCA_CERR0_AADR_PE = 42 ;
+static const uint8_t P9N2_MCA_CERR0_AAER_PE = 43 ;
+static const uint8_t P9N2_MCA_CERR0_MCBCM_PE = 44 ;
+static const uint8_t P9N2_MCA_CERR0_MBMDI_PE = 45 ;
+static const uint8_t P9N2_MCA_CERR0_WDFCFG_PE = 48 ;
+static const uint8_t P9N2_MCA_CERR0_WRTCFG_PE = 56 ;
+static const uint8_t P9N2_MCA_CERR0_DQS0R_PE = 60 ;
+static const uint8_t P9N2_MCA_CERR0_DQS1R_PE = 61 ;
+
+static const uint8_t P9N2_MCA_CERR1_ECC_CTL_AF_PERR = 0 ;
+static const uint8_t P9N2_MCA_CERR1_ECC_CTL_RPTR_PERR = 1 ;
+static const uint8_t P9N2_MCA_CERR1_ECC_CTL_TCHN_PERR = 2 ;
+static const uint8_t P9N2_MCA_CERR1_ECC_CTL_CMPMODE_ERR = 3 ;
+static const uint8_t P9N2_MCA_CERR1_ECC_CTL_SCHCTL_PERR = 4 ;
+static const uint8_t P9N2_MCA_CERR1_ECC_CTL_PCTL_PERR = 5 ;
+static const uint8_t P9N2_MCA_CERR1_ECC_CTL_TGST_PERR = 6 ;
+static const uint8_t P9N2_MCA_CERR1_ECC_CTL_SCHTAB_PERR = 7 ;
+static const uint8_t P9N2_MCA_CERR1_ECC_PIPE_PCX_PERR = 8 ;
+static const uint8_t P9N2_MCA_CERR1_ECC_PIPE_SYND_PERR = 9 ;
+static const uint8_t P9N2_MCA_CERR1_ECC_PIPE_2SYM_PERR = 10 ;
+static const uint8_t P9N2_MCA_CERR1_ECC_PIPE_CPLX_PERR = 11 ;
+static const uint8_t P9N2_MCA_CERR1_ECC_PIPE_EP2_PERR = 12 ;
+static const uint8_t P9N2_MCA_CERR1_READ_ECC_DATAPATH_PARITY_ERROR = 13 ;
+static const uint8_t P9N2_MCA_CERR1_PHY_RPTR_PARITY_ERROR = 14 ;
+static const uint8_t P9N2_MCA_CERR1_ECC_CTL_RPD_PERR = 15 ;
+static const uint8_t P9N2_MCA_CERR1_WDF_ASYNC_ERROR = 16 ;
+static const uint8_t P9N2_MCA_CERR1_WDF_BUFFER_CE = 17 ;
+static const uint8_t P9N2_MCA_CERR1_WDF_BUFFER_UE = 18 ;
+static const uint8_t P9N2_MCA_CERR1_WDF_BUFFER_SUE = 19 ;
+static const uint8_t P9N2_MCA_CERR1_WRT_BUFFER_CE = 25 ;
+static const uint8_t P9N2_MCA_CERR1_WRT_BUFFER_UE = 26 ;
+static const uint8_t P9N2_MCA_CERR1_WRT_BUFFER_SUE = 27 ;
+static const uint8_t P9N2_MCA_CERR1_READ_CONTROL_OVERFLOW_ERROR = 32 ;
+static const uint8_t P9N2_MCA_CERR1_WRITE_ECC_DATAPATH_ERROR = 40 ;
+
+static const uint8_t P9N2_MCBIST_CLKRATIO_RATIO = 0 ;
+static const uint8_t P9N2_MCBIST_CLKRATIO_RATIO_LEN = 12 ;
+static const uint8_t P9N2_MCBIST_CLKRATIO_CFG0_SYNC_MODE = 12 ;
+static const uint8_t P9N2_MCBIST_CLKRATIO_CFG1_SYNC_MODE = 13 ;
+
+static const uint8_t P9N2_MCBIST_DBGCFG0Q_CFG_DBG_ENABLE = 0 ;
+static const uint8_t P9N2_MCBIST_DBGCFG0Q_CFG_DBG_PICK_ASYNC_PORT01 = 1 ;
+static const uint8_t P9N2_MCBIST_DBGCFG0Q_CFG_DBG_PICK_ASYNC_PORT01_LEN = 11 ;
+static const uint8_t P9N2_MCBIST_DBGCFG0Q_CFG_DBG_PICK_ASYNC_PORT23 = 12 ;
+static const uint8_t P9N2_MCBIST_DBGCFG0Q_CFG_DBG_PICK_ASYNC_PORT23_LEN = 11 ;
+static const uint8_t P9N2_MCBIST_DBGCFG0Q_CFG_DBG_PICK_MCBIST01 = 23 ;
+static const uint8_t P9N2_MCBIST_DBGCFG0Q_CFG_DBG_PICK_MCBIST01_LEN = 11 ;
+static const uint8_t P9N2_MCBIST_DBGCFG0Q_CFG_DBG_PICK_MCBIST23 = 34 ;
+static const uint8_t P9N2_MCBIST_DBGCFG0Q_CFG_DBG_PICK_MCBIST23_LEN = 11 ;
+static const uint8_t P9N2_MCBIST_DBGCFG0Q_SCOM_SET_WAT_EXT_TRIGGER = 45 ;
+static const uint8_t P9N2_MCBIST_DBGCFG0Q_SCOM_SET_WAT_EXT_RESET = 46 ;
+static const uint8_t P9N2_MCBIST_DBGCFG0Q_SCOM_SET_WAT_EXT_ARM = 47 ;
+
+static const uint8_t P9N2_MCBIST_DBGCFG1Q_CFG_WAT_ENABLE = 0 ;
+static const uint8_t P9N2_MCBIST_DBGCFG1Q_CFG_WAT_EXT_EVENT_TO_INT = 1 ;
+static const uint8_t P9N2_MCBIST_DBGCFG1Q_CFG_WAT_EXT_EVENT_TO_INT_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_DBGCFG1Q_CFG_WAT_EXT_TRIGGER_SEL = 3 ;
+static const uint8_t P9N2_MCBIST_DBGCFG1Q_CFG_WAT_EXT_TRIGGER_SEL_LEN = 20 ;
+static const uint8_t P9N2_MCBIST_DBGCFG1Q_CFG_WAT_EXT_RESET_SEL = 23 ;
+static const uint8_t P9N2_MCBIST_DBGCFG1Q_CFG_WAT_EXT_RESET_SEL_LEN = 20 ;
+static const uint8_t P9N2_MCBIST_DBGCFG1Q_CFG_WAT_EXT_ARM_SEL = 43 ;
+static const uint8_t P9N2_MCBIST_DBGCFG1Q_CFG_WAT_EXT_ARM_SEL_LEN = 20 ;
+static const uint8_t P9N2_MCBIST_DBGCFG1Q_RESERVED_63 = 63 ;
+
+static const uint8_t P9N2_MCBIST_DBGCFG2Q_CFG_WAT_LOC_EVENT0_SEL = 0 ;
+static const uint8_t P9N2_MCBIST_DBGCFG2Q_CFG_WAT_LOC_EVENT0_SEL_LEN = 20 ;
+static const uint8_t P9N2_MCBIST_DBGCFG2Q_CFG_WAT_LOC_EVENT1_SEL = 20 ;
+static const uint8_t P9N2_MCBIST_DBGCFG2Q_CFG_WAT_LOC_EVENT1_SEL_LEN = 20 ;
+static const uint8_t P9N2_MCBIST_DBGCFG2Q_CFG_WAT_LOC_EVENT2_SEL = 40 ;
+static const uint8_t P9N2_MCBIST_DBGCFG2Q_CFG_WAT_LOC_EVENT2_SEL_LEN = 20 ;
+static const uint8_t P9N2_MCBIST_DBGCFG2Q_RESERVED_60_63 = 60 ;
+static const uint8_t P9N2_MCBIST_DBGCFG2Q_RESERVED_60_63_LEN = 4 ;
+
+static const uint8_t P9N2_MCBIST_DBGCFG3Q_CFG_WAT_LOC_EVENT3_SEL = 0 ;
+static const uint8_t P9N2_MCBIST_DBGCFG3Q_CFG_WAT_LOC_EVENT3_SEL_LEN = 20 ;
+static const uint8_t P9N2_MCBIST_DBGCFG3Q_CFG_WAT_GLOB_EVENT0_SEL = 20 ;
+static const uint8_t P9N2_MCBIST_DBGCFG3Q_CFG_WAT_GLOB_EVENT0_SEL_LEN = 3 ;
+static const uint8_t P9N2_MCBIST_DBGCFG3Q_CFG_WAT_GLOB_EVENT1_SEL = 23 ;
+static const uint8_t P9N2_MCBIST_DBGCFG3Q_CFG_WAT_GLOB_EVENT1_SEL_LEN = 3 ;
+static const uint8_t P9N2_MCBIST_DBGCFG3Q_CFG_WAT_GLOB_EVENT2_SEL = 26 ;
+static const uint8_t P9N2_MCBIST_DBGCFG3Q_CFG_WAT_GLOB_EVENT2_SEL_LEN = 3 ;
+static const uint8_t P9N2_MCBIST_DBGCFG3Q_CFG_WAT_GLOB_EVENT3_SEL = 29 ;
+static const uint8_t P9N2_MCBIST_DBGCFG3Q_CFG_WAT_GLOB_EVENT3_SEL_LEN = 3 ;
+static const uint8_t P9N2_MCBIST_DBGCFG3Q_CFG_WAT_OUTPUT_PULSE = 32 ;
+static const uint8_t P9N2_MCBIST_DBGCFG3Q_CFG_WAT_ACT_MNT_GO_IDLE_PULSE = 33 ;
+static const uint8_t P9N2_MCBIST_DBGCFG3Q_CFG_WAT_ACT_MNT_GO_IDLE_PULSE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_DBGCFG3Q_CFG_WAT_ACT_SET_SPATTN_PULSE = 37 ;
+static const uint8_t P9N2_MCBIST_DBGCFG3Q_CFG_WAT_ACT_SET_SPATTN_PULSE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_DBGCFG3Q_CFG_WAT_ACT_FRC_TB_PULSE_PULSE = 41 ;
+static const uint8_t P9N2_MCBIST_DBGCFG3Q_CFG_WAT_ACT_FRC_TB_PULSE_PULSE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_DBGCFG3Q_CFG_WAT_CNT_VALUE = 45 ;
+static const uint8_t P9N2_MCBIST_DBGCFG3Q_CFG_WAT_CNT_VALUE_LEN = 6 ;
+static const uint8_t P9N2_MCBIST_DBGCFG3Q_CFG_WAT_TMR_VALUE = 51 ;
+static const uint8_t P9N2_MCBIST_DBGCFG3Q_CFG_WAT_TMR_VALUE_LEN = 8 ;
+
+static const uint8_t P9N2_MCA_DBGR_ECC_DEBUG_ENABLE = 0 ;
+static const uint8_t P9N2_MCA_DBGR_ECC_DEBUG_CHUNK_SELECT = 1 ;
+static const uint8_t P9N2_MCA_DBGR_ECC_DEBUG_CHUNK_SELECT_LEN = 2 ;
+static const uint8_t P9N2_MCA_DBGR_ECC_DEBUG_PRIMARY_SELECT = 3 ;
+static const uint8_t P9N2_MCA_DBGR_ECC_DEBUG_PRIMARY_SELECT_LEN = 3 ;
+static const uint8_t P9N2_MCA_DBGR_ECC_DEBUG_SECONDARY_SELECT = 6 ;
+static const uint8_t P9N2_MCA_DBGR_ECC_DEBUG_SECONDARY_SELECT_LEN = 2 ;
+static const uint8_t P9N2_MCA_DBGR_ECC_WAT_ENABLE = 8 ;
+static const uint8_t P9N2_MCA_DBGR_ECC_WAT_ACTION_SELECT = 9 ;
+static const uint8_t P9N2_MCA_DBGR_ECC_WAT_SOURCE = 10 ;
+static const uint8_t P9N2_MCA_DBGR_ECC_WAT_SOURCE_LEN = 2 ;
+static const uint8_t P9N2_MCA_DBGR_READ_DEBUG_SELECT = 12 ;
+static const uint8_t P9N2_MCA_DBGR_READ_DEBUG_SELECT_LEN = 3 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_BIT_ENABLE_P0_ADR0_01_0_11 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_BIT_ENABLE_P0_ADR0_01_0_11_LEN = 12 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_BIT_ENABLE_P0_ADR1_01_0_11 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_BIT_ENABLE_P0_ADR1_01_0_11_LEN = 12 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_BIT_ENABLE_P0_ADR2_23_0_11 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_BIT_ENABLE_P0_ADR2_23_0_11_LEN = 12 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_BIT_ENABLE_P0_ADR3_23_0_11 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_BIT_ENABLE_P0_ADR3_23_0_11_LEN = 12 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S0_ADR0_DLL_ADJUST = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S0_ADR0_DLL_ADJUST_LEN = 8 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S0_ADR0_DLL_CORRECT_EN = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S0_ADR0_DLL_ITER_A = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S0_ADR0_DLL_CAL_ENABLE = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S0_ADR0_DLL_POWERDOWN = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S0_ADR0_DLL_CAL_DONE = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S0_ADR0_DLL_CAL_ERROR = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S0_ADR0_DLL_COMPARE_OUT = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S1_ADR1_DLL_ADJUST = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S1_ADR1_DLL_ADJUST_LEN = 8 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S1_ADR1_DLL_CORRECT_EN = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S1_ADR1_DLL_ITER_A = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S1_ADR1_DLL_CAL_ENABLE = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S1_ADR1_DLL_POWERDOWN = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S1_ADR1_DLL_CAL_DONE = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S1_ADR1_DLL_CAL_ERROR = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S1_ADR1_DLL_COMPARE_OUT = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY0_P0_ADR0_01 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY0_P0_ADR0_01_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY0_P0_ADR0_01_DELAY1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY0_P0_ADR0_01_DELAY1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY0_P0_ADR1_01 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY0_P0_ADR1_01_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY0_P0_ADR1_01_DELAY1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY0_P0_ADR1_01_DELAY1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY0_P0_ADR2_23 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY0_P0_ADR2_23_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY0_P0_ADR2_23_DELAY1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY0_P0_ADR2_23_DELAY1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY0_P0_ADR3_23 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY0_P0_ADR3_23_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY0_P0_ADR3_23_DELAY1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY0_P0_ADR3_23_DELAY1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY1_P0_ADR0_01_DELAY2 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY1_P0_ADR0_01_DELAY2_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY1_P0_ADR0_01_DELAY3 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY1_P0_ADR0_01_DELAY3_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY1_P0_ADR1_01_DELAY2 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY1_P0_ADR1_01_DELAY2_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY1_P0_ADR1_01_DELAY3 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY1_P0_ADR1_01_DELAY3_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY1_P0_ADR2_23_DELAY2 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY1_P0_ADR2_23_DELAY2_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY1_P0_ADR2_23_DELAY3 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY1_P0_ADR2_23_DELAY3_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY1_P0_ADR3_23_DELAY2 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY1_P0_ADR3_23_DELAY2_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY1_P0_ADR3_23_DELAY3 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY1_P0_ADR3_23_DELAY3_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY2_P0_ADR0_01_DELAY4 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY2_P0_ADR0_01_DELAY4_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY2_P0_ADR0_01_DELAY5 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY2_P0_ADR0_01_DELAY5_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY2_P0_ADR1_01_DELAY4 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY2_P0_ADR1_01_DELAY4_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY2_P0_ADR1_01_DELAY5 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY2_P0_ADR1_01_DELAY5_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY2_P0_ADR2_23_DELAY4 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY2_P0_ADR2_23_DELAY4_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY2_P0_ADR2_23_DELAY5 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY2_P0_ADR2_23_DELAY5_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY2_P0_ADR3_23_DELAY4 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY2_P0_ADR3_23_DELAY4_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY2_P0_ADR3_23_DELAY5 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY2_P0_ADR3_23_DELAY5_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY3_P0_ADR0_01_DELAY6 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY3_P0_ADR0_01_DELAY6_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY3_P0_ADR0_01_DELAY7 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY3_P0_ADR0_01_DELAY7_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY3_P0_ADR1_01_DELAY6 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY3_P0_ADR1_01_DELAY6_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY3_P0_ADR1_01_DELAY7 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY3_P0_ADR1_01_DELAY7_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY3_P0_ADR2_23_DELAY6 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY3_P0_ADR2_23_DELAY6_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY3_P0_ADR2_23_DELAY7 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY3_P0_ADR2_23_DELAY7_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY3_P0_ADR3_23_DELAY6 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY3_P0_ADR3_23_DELAY6_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY3_P0_ADR3_23_DELAY7 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY3_P0_ADR3_23_DELAY7_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY4_P0_ADR0_01_DELAY8 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY4_P0_ADR0_01_DELAY8_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY4_P0_ADR0_01_DELAY9 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY4_P0_ADR0_01_DELAY9_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY4_P0_ADR1_01_DELAY8 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY4_P0_ADR1_01_DELAY8_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY4_P0_ADR1_01_DELAY9 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY4_P0_ADR1_01_DELAY9_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY4_P0_ADR2_23_DELAY8 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY4_P0_ADR2_23_DELAY8_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY4_P0_ADR2_23_DELAY9 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY4_P0_ADR2_23_DELAY9_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY4_P0_ADR3_23_DELAY8 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY4_P0_ADR3_23_DELAY8_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY4_P0_ADR3_23_DELAY9 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY4_P0_ADR3_23_DELAY9_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY5_P0_ADR0_01_DELAY10 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY5_P0_ADR0_01_DELAY10_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY5_P0_ADR0_01_DELAY11 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY5_P0_ADR0_01_DELAY11_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY5_P0_ADR1_01_DELAY10 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY5_P0_ADR1_01_DELAY10_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY5_P0_ADR1_01_DELAY11 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY5_P0_ADR1_01_DELAY11_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY5_P0_ADR2_23_DELAY10 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY5_P0_ADR2_23_DELAY10_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY5_P0_ADR2_23_DELAY11 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY5_P0_ADR2_23_DELAY11_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY5_P0_ADR3_23_DELAY10 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY5_P0_ADR3_23_DELAY10_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY5_P0_ADR3_23_DELAY11 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY5_P0_ADR3_23_DELAY11_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY6_P0_ADR0_01_DELAY12 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY6_P0_ADR0_01_DELAY12_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY6_P0_ADR0_01_DELAY13 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY6_P0_ADR0_01_DELAY13_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY6_P0_ADR1_01_DELAY12 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY6_P0_ADR1_01_DELAY12_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY6_P0_ADR1_01_DELAY13 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY6_P0_ADR1_01_DELAY13_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY6_P0_ADR2_23_DELAY12 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY6_P0_ADR2_23_DELAY12_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY6_P0_ADR2_23_DELAY13 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY6_P0_ADR2_23_DELAY13_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY6_P0_ADR3_23_DELAY12 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY6_P0_ADR3_23_DELAY12_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY6_P0_ADR3_23_DELAY13 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY6_P0_ADR3_23_DELAY13_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY7_P0_ADR0_01_DELAY14 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY7_P0_ADR0_01_DELAY14_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY7_P0_ADR0_01_DELAY15 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY7_P0_ADR0_01_DELAY15_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY7_P0_ADR1_01_DELAY14 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY7_P0_ADR1_01_DELAY14_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY7_P0_ADR1_01_DELAY15 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY7_P0_ADR1_01_DELAY15_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY7_P0_ADR2_23_DELAY14 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY7_P0_ADR2_23_DELAY14_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY7_P0_ADR2_23_DELAY15 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY7_P0_ADR2_23_DELAY15_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY7_P0_ADR3_23_DELAY14 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY7_P0_ADR3_23_DELAY14_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY7_P0_ADR3_23_DELAY15 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY7_P0_ADR3_23_DELAY15_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR0_01_TEST_LANE_PAIR_FAIL = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR0_01_TEST_LANE_PAIR_FAIL_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR0_01_RESERVED_54_55 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR0_01_RESERVED_54_55_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR0_01_TEST_DATA_EN = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR0_01_TEST_MODE = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR0_01_TEST_MODE_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR0_01_TEST_4TO1_MODE = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR0_01_TEST_RESET = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR0_01_TEST_GEN_EN = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR0_01_TEST_CLEAR_ERROR = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR0_01_TEST_CHECK_EN = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR1_01_TEST_LANE_PAIR_FAIL = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR1_01_TEST_LANE_PAIR_FAIL_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR1_01_RESERVED_54_55 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR1_01_RESERVED_54_55_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR1_01_TEST_DATA_EN = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR1_01_TEST_MODE = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR1_01_TEST_MODE_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR1_01_TEST_4TO1_MODE = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR1_01_TEST_RESET = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR1_01_TEST_GEN_EN = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR1_01_TEST_CLEAR_ERROR = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR1_01_TEST_CHECK_EN = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR2_23_TEST_LANE_PAIR_FAIL = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR2_23_TEST_LANE_PAIR_FAIL_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR2_23_RESERVED_54_55 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR2_23_RESERVED_54_55_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR2_23_TEST_DATA_EN = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR2_23_TEST_MODE = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR2_23_TEST_MODE_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR2_23_TEST_4TO1_MODE = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR2_23_TEST_RESET = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR2_23_TEST_GEN_EN = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR2_23_TEST_CLEAR_ERROR = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR2_23_TEST_CHECK_EN = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR3_23_TEST_LANE_PAIR_FAIL = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR3_23_TEST_LANE_PAIR_FAIL_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR3_23_RESERVED_54_55 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR3_23_RESERVED_54_55_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR3_23_TEST_DATA_EN = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR3_23_TEST_MODE = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR3_23_TEST_MODE_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR3_23_TEST_4TO1_MODE = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR3_23_TEST_RESET = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR3_23_TEST_GEN_EN = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR3_23_TEST_CLEAR_ERROR = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR3_23_TEST_CHECK_EN = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR0_01_DI_ADR1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR0_01_DI_ADR2_ADR3 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR0_01_DI_ADR4_ADR5 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR0_01_DI_ADR6_ADR7 = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR0_01_DI_ADR8_ADR9 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR0_01_DI_ADR10_ADR11 = 53 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR1_01_DI_ADR0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR1_01_DI_ADR2_ADR3 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR1_01_DI_ADR4_ADR5 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR1_01_DI_ADR6_ADR7 = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR1_01_DI_ADR8_ADR9 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR1_01_DI_ADR10_ADR11 = 53 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR2_23_DI_ADR0_ADR1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR2_23_DI_ADR3 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR2_23_DI_ADR4_ADR5 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR2_23_DI_ADR6_ADR7 = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR2_23_DI_ADR8_ADR9 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR2_23_DI_ADR10_ADR11 = 53 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR3_23_DI_ADR0_ADR1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR3_23_DI_ADR2 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR3_23_DI_ADR4_ADR5 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR3_23_DI_ADR6_ADR7 = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR3_23_DI_ADR8_ADR9 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR3_23_DI_ADR10_ADR11 = 53 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_INIT_RXDLL_CAL_RESET = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_INIT_RXDLL_CAL_UPDATE = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_REGS_RXDLL_CAL_SKIP = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_REGS_RXDLL_CAL_SKIP_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_REGS_RXDLL_COARSE_ADJ_BY2 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_RXREG_FILTER_LENGTH_DC = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_RXREG_FILTER_LENGTH_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_RXREG_LEAD_LAG_SEPARATION_DC = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_RXREG_LEAD_LAG_SEPARATION_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_EN_DRIVER_INVFB_DC = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_CAL_GOOD = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_CAL_ERROR = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_CAL_ERROR_FINE = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_INIT_RXDLL_CAL_RESET = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_INIT_RXDLL_CAL_UPDATE = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_REGS_RXDLL_CAL_SKIP = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_REGS_RXDLL_CAL_SKIP_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_REGS_RXDLL_COARSE_ADJ_BY2 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_RXREG_FILTER_LENGTH_DC = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_RXREG_FILTER_LENGTH_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_RXREG_LEAD_LAG_SEPARATION_DC = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_RXREG_LEAD_LAG_SEPARATION_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_EN_DRIVER_INVFB_DC = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_CAL_GOOD = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_CAL_ERROR = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_CAL_ERROR_FINE = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_DAC_LOWER_P0_ADR32S0_ADR0_REGS_RXDLL_VREG = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_DAC_LOWER_P0_ADR32S0_ADR0_REGS_RXDLL_VREG_LEN = 15 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_DAC_LOWER_P0_ADR32S1_ADR1_REGS_RXDLL_VREG = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_DAC_LOWER_P0_ADR32S1_ADR1_REGS_RXDLL_VREG_LEN = 15 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_DAC_UPPER_P0_ADR32S0_ADR0_REGS_RXDLL_VREG = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_DAC_UPPER_P0_ADR32S0_ADR0_REGS_RXDLL_VREG_LEN = 15 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_DAC_UPPER_P0_ADR32S1_ADR1_REGS_RXDLL_VREG = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_DAC_UPPER_P0_ADR32S1_ADR1_REGS_RXDLL_VREG_LEN = 15 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SLAVE_VREG_LOWER_P0_ADR32S0_ADR0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SLAVE_VREG_LOWER_P0_ADR32S0_ADR0_LEN = 15 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SLAVE_VREG_LOWER_P0_ADR32S1_ADR1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SLAVE_VREG_LOWER_P0_ADR32S1_ADR1_LEN = 15 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SLAVE_VREG_UPPER_P0_ADR32S0_ADR0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SLAVE_VREG_UPPER_P0_ADR32S0_ADR0_LEN = 15 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SLAVE_VREG_UPPER_P0_ADR32S1_ADR1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SLAVE_VREG_UPPER_P0_ADR32S1_ADR1_LEN = 15 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SW_CONTROL_0_P0_ADR32S0_ADR0_OVERRIDE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SW_CONTROL_0_P0_ADR32S0_ADR0_CAL_PD_ENABLE = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SW_CONTROL_0_P0_ADR32S0_ADR0_MAIN_PD_ENABLE = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SW_CONTROL_0_P0_ADR32S0_ADR0_DETECT_REQ = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SW_CONTROL_0_P0_ADR32S0_ADR0_SLAVE_CAL_CKT_POWERDOWN = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SW_CONTROL_0_P0_ADR32S0_ADR0_VREG_RXCAL_COMP_OUT_META = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SW_CONTROL_0_P0_ADR32S0_ADR0_RXCAL_DETECT_DONE_META = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SW_CONTROL_0_P0_ADR32S0_ADR0_RXCAL_PD_CAL_LAG_META = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SW_CONTROL_0_P0_ADR32S0_ADR0_RXCAL_PD_MAIN_LEAD_META = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SW_CONTROL_0_P0_ADR32S0_ADR0_RXCAL_PD_MAIN_LAG_META = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SW_CONTROL_0_P0_ADR32S0_ADR0_VREG_SLAVE1_COMP_OUT = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SW_CONTROL_0_P0_ADR32S0_ADR0_VREG_SLAVE2_COMP_OUT = 62 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SW_CONTROL_0_P0_ADR32S1_ADR1_OVERRIDE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SW_CONTROL_0_P0_ADR32S1_ADR1_CAL_PD_ENABLE = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SW_CONTROL_0_P0_ADR32S1_ADR1_MAIN_PD_ENABLE = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SW_CONTROL_0_P0_ADR32S1_ADR1_DETECT_REQ = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SW_CONTROL_0_P0_ADR32S1_ADR1_SLAVE_CAL_CKT_POWERDOWN = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SW_CONTROL_0_P0_ADR32S1_ADR1_VREG_RXCAL_COMP_OUT_META = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SW_CONTROL_0_P0_ADR32S1_ADR1_RXCAL_DETECT_DONE_META = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SW_CONTROL_0_P0_ADR32S1_ADR1_RXCAL_PD_CAL_LAG_META = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SW_CONTROL_0_P0_ADR32S1_ADR1_RXCAL_PD_MAIN_LEAD_META = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SW_CONTROL_0_P0_ADR32S1_ADR1_RXCAL_PD_MAIN_LAG_META = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SW_CONTROL_0_P0_ADR32S1_ADR1_VREG_SLAVE1_COMP_OUT = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SW_CONTROL_0_P0_ADR32S1_ADR1_VREG_SLAVE2_COMP_OUT = 62 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SW_CONTROL_1_P0_ADR32S0_ADR0_SLAVE_VREG_OVERRIDE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SW_CONTROL_1_P0_ADR32S0_ADR0_SLAVE_VREG_REF_SEL_DC = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SW_CONTROL_1_P0_ADR32S0_ADR0_SLAVE_VREG_REF_SEL_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SW_CONTROL_1_P0_ADR32S0_ADR0_SLAVE_VREG_DAC_COARSE = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SW_CONTROL_1_P0_ADR32S0_ADR0_SLAVE_VREG_DAC_COARSE_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SW_CONTROL_1_P0_ADR32S0_ADR0_DD2_IE_FIX_DISABLE = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SW_CONTROL_1_P0_ADR32S1_ADR1_SLAVE_VREG_OVERRIDE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SW_CONTROL_1_P0_ADR32S1_ADR1_SLAVE_VREG_REF_SEL_DC = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SW_CONTROL_1_P0_ADR32S1_ADR1_SLAVE_VREG_REF_SEL_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SW_CONTROL_1_P0_ADR32S1_ADR1_SLAVE_VREG_DAC_COARSE = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SW_CONTROL_1_P0_ADR32S1_ADR1_SLAVE_VREG_DAC_COARSE_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SW_CONTROL_1_P0_ADR32S1_ADR1_DD2_IE_FIX_DISABLE = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_COARSE_P0_ADR32S0_ADR0_REGS_RXDLL_EN = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_COARSE_P0_ADR32S0_ADR0_REGS_RXDLL_EN_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_COARSE_P0_ADR32S0_ADR0_REGS_RXDLL_DAC = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_COARSE_P0_ADR32S0_ADR0_REGS_RXDLL_DAC_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_COARSE_P0_ADR32S1_ADR1_REGS_RXDLL_EN = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_COARSE_P0_ADR32S1_ADR1_REGS_RXDLL_EN_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_COARSE_P0_ADR32S1_ADR1_REGS_RXDLL_DAC = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_COARSE_P0_ADR32S1_ADR1_REGS_RXDLL_DAC_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S0_ADR0_HS_DLLMUX_SEL_0_3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S0_ADR0_HS_DLLMUX_SEL_0_3_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S0_ADR0_STRENGTH = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S0_ADR0_STRENGTH_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S0_ADR0_ANALOG_WRAPON = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S1_ADR1_HS_DLLMUX_SEL_0_3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S1_ADR1_HS_DLLMUX_SEL_0_3_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S1_ADR1_STRENGTH = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S1_ADR1_STRENGTH_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S1_ADR1_ANALOG_WRAPON = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S0_ADR0_RXREG_COMPCON_DC = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S0_ADR0_RXREG_COMPCON_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S0_ADR0_RXREG_DAC_PULLUP_DC = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S0_ADR0_RXREG_DRVCON_DC = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S0_ADR0_RXREG_DRVCON_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S0_ADR0_RXREG_REF_SEL_DC = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S0_ADR0_RXREG_REF_SEL_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S0_ADR0_REGS_RXDLL_COARSE_ADJ_BY0 = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S0_ADR0_CAL_CKTS_ACTIVE = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S1_ADR1_RXREG_COMPCON_DC = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S1_ADR1_RXREG_COMPCON_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S1_ADR1_RXREG_DAC_PULLUP_DC = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S1_ADR1_RXREG_DRVCON_DC = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S1_ADR1_RXREG_DRVCON_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S1_ADR1_RXREG_REF_SEL_DC = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S1_ADR1_RXREG_REF_SEL_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S1_ADR1_REGS_RXDLL_COARSE_ADJ_BY0 = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S1_ADR1_CAL_CKTS_ACTIVE = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0_01_SEL0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0_01_SEL1 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0_01_SEL2 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0_01_SEL3 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0_01_SEL4 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0_01_SEL5 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0_01_SEL6 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0_01_SEL7 = 62 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1_01_SEL0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1_01_SEL1 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1_01_SEL2 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1_01_SEL3 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1_01_SEL4 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1_01_SEL5 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1_01_SEL6 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1_01_SEL7 = 62 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2_23_SEL0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2_23_SEL1 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2_23_SEL2 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2_23_SEL3 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2_23_SEL4 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2_23_SEL5 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2_23_SEL6 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2_23_SEL7 = 62 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3_23_SEL0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3_23_SEL1 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3_23_SEL2 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3_23_SEL3 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3_23_SEL4 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3_23_SEL5 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3_23_SEL6 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3_23_SEL7 = 62 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0_01_SEL8 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0_01_SEL9 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0_01_SEL10 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0_01_SEL11 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0_01_SEL12 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0_01_SEL13 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0_01_SEL14 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0_01_SEL15 = 62 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1_01_SEL8 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1_01_SEL9 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1_01_SEL10 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1_01_SEL11 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1_01_SEL12 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1_01_SEL13 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1_01_SEL14 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1_01_SEL15 = 62 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2_23_SEL8 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2_23_SEL9 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2_23_SEL10 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2_23_SEL11 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2_23_SEL12 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2_23_SEL13 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2_23_SEL14 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2_23_SEL15 = 62 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR3_23_SEL8 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR3_23_SEL9 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR3_23_SEL10 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR3_23_SEL11 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR3_23_SEL12 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR3_23_SEL13 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR3_23_SEL14 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR3_23_SEL15 = 62 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET_P0_ADR32S0_ADR0_TSYS = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET_P0_ADR32S0_ADR0_TSYS_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET_P0_ADR32S1_ADR1_TSYS = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET_P0_ADR32S1_ADR1_TSYS_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE0_P0_ADR32S0_ADR0_VALUE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE0_P0_ADR32S0_ADR0_VALUE_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE0_P0_ADR32S1_ADR1_VALUE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE0_P0_ADR32S1_ADR1_VALUE_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE1_P0_ADR32S0_ADR0_VALUE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE1_P0_ADR32S0_ADR0_VALUE_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE1_P0_ADR32S1_ADR1_VALUE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE1_P0_ADR32S1_ADR1_VALUE_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S0_ADR0_FLUSH = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S0_ADR0_EN = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S0_ADR0_INIT_IO = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S0_ADR0_HS_PROBE_A_SEL_0_3 = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S0_ADR0_HS_PROBE_A_SEL_0_3_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S0_ADR0_HS_PROBE_B_SEL_0_3 = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S0_ADR0_HS_PROBE_B_SEL_0_3_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S0_ADR0_ATESTSEL_0_2 = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S0_ADR0_ATESTSEL_0_2_LEN = 3 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S1_ADR1_FLUSH = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S1_ADR1_EN = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S1_ADR1_INIT_IO = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S1_ADR1_HS_PROBE_A_SEL_0_3 = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S1_ADR1_HS_PROBE_A_SEL_0_3_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S1_ADR1_HS_PROBE_B_SEL_0_3 = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S1_ADR1_HS_PROBE_B_SEL_0_3_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S1_ADR1_ATESTSEL_0_2 = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S1_ADR1_ATESTSEL_0_2_LEN = 3 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR0_01_LANE__0_7_PD = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR0_01_LANE__0_7_PD_LEN = 8 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR0_01_LANE__8_11_PD = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR0_01_LANE__8_11_PD_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR0_01_LANE__12_15_PD = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR0_01_LANE__12_15_PD_LEN = 4 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR1_01_LANE__0_7_PD = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR1_01_LANE__0_7_PD_LEN = 8 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR1_01_LANE__8_11_PD = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR1_01_LANE__8_11_PD_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR1_01_LANE__12_15_PD = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR1_01_LANE__12_15_PD_LEN = 4 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR2_23_LANE__0_7_PD = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR2_23_LANE__0_7_PD_LEN = 8 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR2_23_LANE__8_11_PD = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR2_23_LANE__8_11_PD_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR2_23_LANE__12_15_PD = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR2_23_LANE__12_15_PD_LEN = 4 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR3_23_LANE__0_7_PD = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR3_23_LANE__0_7_PD_LEN = 8 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR3_23_LANE__8_11_PD = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR3_23_LANE__8_11_PD_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR3_23_LANE__12_15_PD = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR3_23_LANE__12_15_PD_LEN = 4 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0_ADR0_ROT_OVERRIDE = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0_ADR0_ROT_OVERRIDE_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0_ADR0_ROT_OVERRIDE_EN = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0_ADR0_PHASE_ALIGN_RESET = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0_ADR0_PHASE_EN = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0_ADR0_PHASE_DEFAULT_EN = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0_ADR0_POS_EDGE_ALIGN = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0_ADR0_CONTINUOUS_UPDATE = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0_ADR0_DD2_CG_DISABLE = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1_ADR1_ROT_OVERRIDE = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1_ADR1_ROT_OVERRIDE_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1_ADR1_ROT_OVERRIDE_EN = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1_ADR1_PHASE_ALIGN_RESET = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1_ADR1_PHASE_EN = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1_ADR1_PHASE_DEFAULT_EN = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1_ADR1_POS_EDGE_ALIGN = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1_ADR1_CONTINUOUS_UPDATE = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1_ADR1_DD2_CG_DISABLE = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S0_ADR0_ROT = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S0_ADR0_ROT_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S0_ADR0_BB_LOCK = 56 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S1_ADR1_ROT = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S1_ADR1_ROT_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S1_ADR1_BB_LOCK = 56 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_APB_ATEST_MUX_SEL_P0_CNTL = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_APB_ATEST_MUX_SEL_P0_CNTL_LEN = 5 ;
+static const uint8_t P9N2_MCA_DDRPHY_APB_ATEST_MUX_SEL_P0_INJECT_FIR_ERR0_4 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_APB_ATEST_MUX_SEL_P0_INJECT_FIR_ERR1_5 = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_APB_ATEST_MUX_SEL_P0_INJECT_FIR_ERR2_6 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_APB_ATEST_MUX_SEL_P0_INJECT_FIR_ERR3_7 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_APB_ATEST_MUX_SEL_P0_INJECT_FIR_ERR = 58 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_APB_CONFIG0_P0_DISABLE_PARITY_CHECKER = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_APB_CONFIG0_P0_RESET_ERR_RPT = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_APB_CONFIG0_P0_FORCE_ON_CLK_GATE = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_APB_CONFIG0_P0_DEBUG_BUS_SEL = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_APB_CONFIG0_P0_DEBUG_BUS_SEL_LEN = 5 ;
+static const uint8_t P9N2_MCA_DDRPHY_APB_CONFIG0_P0_ADR_SLAVE_SEL = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_APB_CONFIG0_P0_DEBUG_BUS_SEL2 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_APB_CONFIG0_P0_DEBUG_BUS_SEL2_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_APB_CONFIG0_P0_LOW_PROBE_TRACE_GATE = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_APB_CONFIG0_P0_HS_PROBE_TOP_SEL = 62 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_APB_ERROR_MASK0_P0_INVALID_ADDRESS_MASK = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_APB_ERROR_MASK0_P0_WR_PAR_ERR_MASK = 49 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_APB_ERROR_STATUS0_P0_INVALID_ADDRESS = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_APB_ERROR_STATUS0_P0_WR_PAR_ERR = 49 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_APB_FIR_ERR0_P0_ERR_SET0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_APB_FIR_ERR0_P0_ERR_SET1 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_APB_FIR_ERR0_P0_ERR_SET2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_APB_FIR_ERR0_P0_ERR_SET3 = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_APB_FIR_ERR0_P0_ERR_SET4 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_APB_FIR_ERR0_P0_ERR_SET5 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_APB_FIR_ERR0_P0_ERR_FSM_DP16 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_APB_FIR_ERR0_P0_ERR_FSM_DP16_LEN = 5 ;
+static const uint8_t P9N2_MCA_DDRPHY_APB_FIR_ERR0_P0_PC_ERR_STATUS0 = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_APB_FIR_ERR0_P0_PC_ERR_STATUS0_LEN = 5 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_APB_FIR_ERR1_P0_PC_INIT_CAL_ERR = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_APB_FIR_ERR1_P0_PC_INIT_CAL_ERR_LEN = 12 ;
+static const uint8_t P9N2_MCA_DDRPHY_APB_FIR_ERR1_P0_DP_DLL_CAL_ERROR = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_APB_FIR_ERR1_P0_DP_DLL_CAL_ERROR_FINE = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_APB_FIR_ERR1_P0_ADR_DLL_CAL_ERROR = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_APB_FIR_ERR1_P0_ADR_DLL_CAL_ERROR_FINE = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_APB_FIR_ERR2_P0_ERR0_REG_DP16 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_APB_FIR_ERR2_P0_ERR0_REG_DP16_LEN = 5 ;
+static const uint8_t P9N2_MCA_DDRPHY_APB_FIR_ERR2_P0_ERR1_REG_DP16 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_APB_FIR_ERR2_P0_ERR1_REG_DP16_LEN = 5 ;
+static const uint8_t P9N2_MCA_DDRPHY_APB_FIR_ERR2_P0_REG_DP16 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_APB_FIR_ERR2_P0_REG_DP16_LEN = 5 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_APB_FIR_ERR3_P0_REG_DP16 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_APB_FIR_ERR3_P0_REG_DP16_LEN = 5 ;
+static const uint8_t P9N2_MCA_DDRPHY_APB_FIR_ERR3_P0_ERR4_REG_DP16 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_APB_FIR_ERR3_P0_ERR4_REG_DP16_LEN = 5 ;
+static const uint8_t P9N2_MCA_DDRPHY_APB_FIR_ERR3_P0_ERR5_REG_DP16 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_APB_FIR_ERR3_P0_ERR5_REG_DP16_LEN = 5 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_APB_LO_PROBE_SEL_P0_RESET_0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_APB_LO_PROBE_SEL_P0_HOLD_0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_APB_LO_PROBE_SEL_P0_0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_APB_LO_PROBE_SEL_P0_0_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_APB_LO_PROBE_SEL_P0_RESET_1 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_APB_LO_PROBE_SEL_P0_HOLD_1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_APB_LO_PROBE_SEL_P0_1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_APB_LO_PROBE_SEL_P0_1_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_0_01_S0ACENSLICENDRV_DC = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_0_01_S0ACENSLICENDRV_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_0_01_S0ACENSLICEPDRV_DC = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_0_01_S0ACENSLICEPDRV_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_0_01_S0ACENSLICEPTERM_DC = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_0_01_S0ACENSLICEPTERM_DC_LEN = 3 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_1_01_S0ACENSLICENDRV_DC = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_1_01_S0ACENSLICENDRV_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_1_01_S0ACENSLICEPDRV_DC = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_1_01_S0ACENSLICEPDRV_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_1_01_S0ACENSLICEPTERM_DC = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_1_01_S0ACENSLICEPTERM_DC_LEN = 3 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_2_23_S0ACENSLICENDRV_DC = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_2_23_S0ACENSLICENDRV_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_2_23_S0ACENSLICEPDRV_DC = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_2_23_S0ACENSLICEPDRV_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_2_23_S0ACENSLICEPTERM_DC = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_2_23_S0ACENSLICEPTERM_DC_LEN = 3 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_3_23_S0ACENSLICENDRV_DC = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_3_23_S0ACENSLICENDRV_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_3_23_S0ACENSLICEPDRV_DC = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_3_23_S0ACENSLICEPDRV_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_3_23_S0ACENSLICEPTERM_DC = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_3_23_S0ACENSLICEPTERM_DC_LEN = 3 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_4_4_S0ACENSLICENDRV_DC = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_4_4_S0ACENSLICENDRV_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_4_4_S0ACENSLICEPDRV_DC = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_4_4_S0ACENSLICEPDRV_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_4_4_S0ACENSLICEPTERM_DC = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_4_4_S0ACENSLICEPTERM_DC_LEN = 3 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_0_01_S1ACENSLICENDRV_DC = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_0_01_S1ACENSLICENDRV_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_0_01_S1ACENSLICEPDRV_DC = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_0_01_S1ACENSLICEPDRV_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_0_01_S1ACENSLICEPTERM_DC = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_0_01_S1ACENSLICEPTERM_DC_LEN = 3 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_1_01_S1ACENSLICENDRV_DC = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_1_01_S1ACENSLICENDRV_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_1_01_S1ACENSLICEPDRV_DC = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_1_01_S1ACENSLICEPDRV_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_1_01_S1ACENSLICEPTERM_DC = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_1_01_S1ACENSLICEPTERM_DC_LEN = 3 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_2_23_S1ACENSLICENDRV_DC = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_2_23_S1ACENSLICENDRV_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_2_23_S1ACENSLICEPDRV_DC = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_2_23_S1ACENSLICEPDRV_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_2_23_S1ACENSLICEPTERM_DC = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_2_23_S1ACENSLICEPTERM_DC_LEN = 3 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_3_23_S1ACENSLICENDRV_DC = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_3_23_S1ACENSLICENDRV_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_3_23_S1ACENSLICEPDRV_DC = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_3_23_S1ACENSLICEPDRV_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_3_23_S1ACENSLICEPTERM_DC = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_3_23_S1ACENSLICEPTERM_DC_LEN = 3 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_4_4_S1ACENSLICENDRV_DC = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_4_4_S1ACENSLICENDRV_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_4_4_S1ACENSLICEPDRV_DC = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_4_4_S1ACENSLICEPDRV_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_4_4_S1ACENSLICEPTERM_DC = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_4_4_S1ACENSLICEPTERM_DC_LEN = 3 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_0_01_DD2_COARSE_OF_DISABLE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_0_01_DD2_DBDIS_DQS_DISABLE = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_0_01_DD2_SPARE_L2SFF_CG_DISABLE = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_0_01_FLUSH = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_0_01_DQS_FORCE_VALUE = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_0_01_P8_DD2_FIX_DIS = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_0_01_INIT_IO = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_0_01_ADVANCE_PING_PONG = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_0_01_WL_ADVANCE_DISABLE = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_0_01_DISABLE_PING_PONG = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_0_01_DELAY_PING_PONG_HALF = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_0_01_ATESTSEL_4 = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_0_01_ATESTSEL_4_LEN = 5 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_1_01_DD2_COARSE_OF_DISABLE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_1_01_DD2_DBDIS_DQS_DISABLE = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_1_01_DD2_SPARE_L2SFF_CG_DISABLE = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_1_01_FLUSH = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_1_01_DQS_FORCE_VALUE = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_1_01_P8_DD2_FIX_DIS = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_1_01_INIT_IO = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_1_01_ADVANCE_PING_PONG = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_1_01_WL_ADVANCE_DISABLE = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_1_01_DISABLE_PING_PONG = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_1_01_DELAY_PING_PONG_HALF = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_1_01_ATESTSEL_0_4 = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_1_01_ATESTSEL_0_4_LEN = 5 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_2_23_DD2_COARSE_OF_DISABLE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_2_23_DD2_DBDIS_DQS_DISABLE = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_2_23_DD2_SPARE_L2SFF_CG_DISABLE = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_2_23_FLUSH = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_2_23_DQS_FORCE_VALUE = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_2_23_P8_DD2_FIX_DIS = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_2_23_INIT_IO = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_2_23_ADVANCE_PING_PONG = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_2_23_WL_ADVANCE_DISABLE = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_2_23_DISABLE_PING_PONG = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_2_23_DELAY_PING_PONG_HALF = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_2_23_ATESTSEL_0_4 = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_2_23_ATESTSEL_0_4_LEN = 5 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_3_23_DD2_COARSE_OF_DISABLE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_3_23_DD2_DBDIS_DQS_DISABLE = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_3_23_DD2_SPARE_L2SFF_CG_DISABLE = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_3_23_FLUSH = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_3_23_DQS_FORCE_VALUE = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_3_23_P8_DD2_FIX_DIS = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_3_23_INIT_IO = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_3_23_ADVANCE_PING_PONG = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_3_23_WL_ADVANCE_DISABLE = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_3_23_DISABLE_PING_PONG = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_3_23_DELAY_PING_PONG_HALF = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_3_23_ATESTSEL_0_4 = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_3_23_ATESTSEL_0_4_LEN = 5 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_4_4_DD2_COARSE_OF_DISABLE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_4_4_DD2_DBDIS_DQS_DISABLE = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_4_4_DD2_SPARE_L2SFF_CG_DISABLE = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_4_4_FLUSH = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_4_4_DQS_FORCE_VALUE = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_4_4_P8_DD2_FIX_DIS = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_4_4_INIT_IO = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_4_4_ADVANCE_PING_PONG = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_4_4_WL_ADVANCE_DISABLE = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_4_4_DISABLE_PING_PONG = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_4_4_DELAY_PING_PONG_HALF = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_4_4_ATESTSEL_0 = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_4_4_ATESTSEL_0_LEN = 5 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_2_DQSEL_CAP = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_2_DQSEL_CAP_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_2_BIAS_TRIM = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_2_BIAS_TRIM_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_2_DQSEL_RES = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_2_DQSEL_RES_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_1_3_DQSEL_CAP = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_1_3_DQSEL_CAP_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_1_3_BIAS_TRIM = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_1_3_BIAS_TRIM_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_1_3_DQSEL_RES = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_1_3_DQSEL_RES_LEN = 3 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_NIB_0_2_DQSEL_CAP = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_NIB_0_2_DQSEL_CAP_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_NIB_0_2_BIAS_TRIM = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_NIB_0_2_BIAS_TRIM_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_NIB_0_2_DQSEL_RES = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_NIB_0_2_DQSEL_RES_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_NIB_3_DQSEL_CAP = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_NIB_3_DQSEL_CAP_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_NIB_3_BIAS_TRIM = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_NIB_3_BIAS_TRIM_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_NIB_3_DQSEL_RES = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_NIB_3_DQSEL_RES_LEN = 3 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_NIB_0_DQSEL_CAP = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_NIB_0_DQSEL_CAP_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_NIB_0_BIAS_TRIM = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_NIB_0_BIAS_TRIM_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_NIB_0_DQSEL_RES = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_NIB_0_DQSEL_RES_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_NIB_1_3_DQSEL_CAP = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_NIB_1_3_DQSEL_CAP_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_NIB_1_3_BIAS_TRIM = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_NIB_1_3_BIAS_TRIM_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_NIB_1_3_DQSEL_RES = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_NIB_1_3_DQSEL_RES_LEN = 3 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_NIB_0_2_DQSEL_CAP = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_NIB_0_2_DQSEL_CAP_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_NIB_0_2_BIAS_TRIM = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_NIB_0_2_BIAS_TRIM_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_NIB_0_2_DQSEL_RES = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_NIB_0_2_DQSEL_RES_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_NIB_1_DQSEL_CAP = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_NIB_1_DQSEL_CAP_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_NIB_1_BIAS_TRIM = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_NIB_1_BIAS_TRIM_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_NIB_1_DQSEL_RES = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_NIB_1_DQSEL_RES_LEN = 3 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_NIB_0_2_DQSEL_CAP = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_NIB_0_2_DQSEL_CAP_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_NIB_0_2_BIAS_TRIM = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_NIB_0_2_BIAS_TRIM_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_NIB_0_2_DQSEL_RES = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_NIB_0_2_DQSEL_RES_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_NIB_1_3_DQSEL_CAP = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_NIB_1_3_DQSEL_CAP_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_NIB_1_3_BIAS_TRIM = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_NIB_1_3_BIAS_TRIM_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_NIB_1_3_DQSEL_RES = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_NIB_1_3_DQSEL_RES_LEN = 3 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_NIB_2_DQSEL_CAP = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_NIB_2_DQSEL_CAP_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_NIB_2_BIAS_TRIM = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_NIB_2_BIAS_TRIM_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_NIB_2_DQSEL_RES = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_NIB_2_DQSEL_RES_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_NIB_1_3_DQSEL_CAP = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_NIB_1_3_DQSEL_CAP_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_NIB_1_3_BIAS_TRIM = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_NIB_1_3_BIAS_TRIM_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_NIB_1_3_DQSEL_RES = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_NIB_1_3_DQSEL_RES_LEN = 3 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_NIB_0_2_DQSEL_CAP = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_NIB_0_2_DQSEL_CAP_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_NIB_0_2_BIAS_TRIM = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_NIB_0_2_BIAS_TRIM_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_NIB_0_2_DQSEL_RES = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_NIB_0_2_DQSEL_RES_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_NIB_3_DQSEL_CAP = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_NIB_3_DQSEL_CAP_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_NIB_3_BIAS_TRIM = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_NIB_3_BIAS_TRIM_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_NIB_3_DQSEL_RES = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_NIB_3_DQSEL_RES_LEN = 3 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_NIB_0_DQSEL_CAP = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_NIB_0_DQSEL_CAP_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_NIB_0_BIAS_TRIM = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_NIB_0_BIAS_TRIM_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_NIB_0_DQSEL_RES = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_NIB_0_DQSEL_RES_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_NIB_1_3_DQSEL_CAP = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_NIB_1_3_DQSEL_CAP_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_NIB_1_3_BIAS_TRIM = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_NIB_1_3_BIAS_TRIM_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_NIB_1_3_DQSEL_RES = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_NIB_1_3_DQSEL_RES_LEN = 3 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_NIB_0_2_DQSEL_CAP = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_NIB_0_2_DQSEL_CAP_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_NIB_0_2_BIAS_TRIM = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_NIB_0_2_BIAS_TRIM_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_NIB_0_2_DQSEL_RES = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_NIB_0_2_DQSEL_RES_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_NIB_1_DQSEL_CAP = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_NIB_1_DQSEL_CAP_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_NIB_1_BIAS_TRIM = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_NIB_1_BIAS_TRIM_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_NIB_1_DQSEL_RES = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_NIB_1_DQSEL_RES_LEN = 3 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_NIB_0_2_DQSEL_CAP = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_NIB_0_2_DQSEL_CAP_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_NIB_0_2_BIAS_TRIM = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_NIB_0_2_BIAS_TRIM_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_NIB_0_2_DQSEL_RES = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_NIB_0_2_DQSEL_RES_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_NIB_1_3_DQSEL_CAP = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_NIB_1_3_DQSEL_CAP_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_NIB_1_3_BIAS_TRIM = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_NIB_1_3_BIAS_TRIM_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_NIB_1_3_DQSEL_RES = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_NIB_1_3_DQSEL_RES_LEN = 3 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_0_01_DLL_ADJUST = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_0_01_DLL_ADJUST_LEN = 8 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_0_01_DLL_CORRECT_EN = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_0_01_DLL_ITER_A = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_0_01_DLL_CAL_ENABLE = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_0_01_DLL_POWERDOWN = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_0_01_DLL_CAL_DONE = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_0_01_DLL_CAL_ERROR = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_0_01_DLL_COMPARE_OUT = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_1_01_DLL_ADJUST = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_1_01_DLL_ADJUST_LEN = 8 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_1_01_DLL_CORRECT_EN = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_1_01_DLL_ITER_A = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_1_01_DLL_CAL_ENABLE = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_1_01_DLL_POWERDOWN = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_1_01_DLL_CAL_DONE = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_1_01_DLL_CAL_ERROR = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_1_01_DLL_COMPARE_OUT = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_2_23_DLL_ADJUST = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_2_23_DLL_ADJUST_LEN = 8 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_2_23_DLL_CORRECT_EN = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_2_23_DLL_ITER_A = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_2_23_DLL_CAL_ENABLE = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_2_23_DLL_POWERDOWN = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_2_23_DLL_CAL_DONE = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_2_23_DLL_CAL_ERROR = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_2_23_DLL_COMPARE_OUT = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_3_23_DLL_ADJUST = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_3_23_DLL_ADJUST_LEN = 8 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_3_23_DLL_CORRECT_EN = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_3_23_DLL_ITER_A = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_3_23_DLL_CAL_ENABLE = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_3_23_DLL_POWERDOWN = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_3_23_DLL_CAL_DONE = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_3_23_DLL_CAL_ERROR = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_3_23_DLL_COMPARE_OUT = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_4_4_DLL_ADJUST = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_4_4_DLL_ADJUST_LEN = 8 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_4_4_DLL_CORRECT_EN = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_4_4_DLL_ITER_A = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_4_4_DLL_CAL_ENABLE = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_4_4_DLL_POWERDOWN = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_4_4_DLL_CAL_DONE = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_4_4_DLL_CAL_ERROR = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_4_4_DLL_COMPARE_OUT = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_0_01_DLL_ADJUST = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_0_01_DLL_ADJUST_LEN = 8 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_0_01_DLL_CORRECT_EN = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_0_01_DLL_ITER_A = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_0_01_DLL_CAL_ENABLE = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_0_01_DLL_POWERDOWN = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_0_01_DLL_CAL_DONE = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_0_01_DLL_CAL_ERROR = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_0_01_DLL_COMPARE_OUT = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_1_01_DLL_ADJUST = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_1_01_DLL_ADJUST_LEN = 8 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_1_01_DLL_CORRECT_EN = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_1_01_DLL_ITER_A = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_1_01_DLL_CAL_ENABLE = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_1_01_DLL_POWERDOWN = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_1_01_DLL_CAL_DONE = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_1_01_DLL_CAL_ERROR = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_1_01_DLL_COMPARE_OUT = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_2_23_DLL_ADJUST = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_2_23_DLL_ADJUST_LEN = 8 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_2_23_DLL_CORRECT_EN = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_2_23_DLL_ITER_A = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_2_23_DLL_CAL_ENABLE = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_2_23_DLL_POWERDOWN = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_2_23_DLL_CAL_DONE = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_2_23_DLL_CAL_ERROR = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_2_23_DLL_COMPARE_OUT = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_3_23_DLL_ADJUST = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_3_23_DLL_ADJUST_LEN = 8 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_3_23_DLL_CORRECT_EN = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_3_23_DLL_ITER_A = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_3_23_DLL_CAL_ENABLE = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_3_23_DLL_POWERDOWN = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_3_23_DLL_CAL_DONE = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_3_23_DLL_CAL_ERROR = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_3_23_DLL_COMPARE_OUT = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_4_4_DLL_ADJUST = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_4_4_DLL_ADJUST_LEN = 8 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_4_4_DLL_CORRECT_EN = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_4_4_DLL_ITER_A = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_4_4_DLL_CAL_ENABLE = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_4_4_DLL_POWERDOWN = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_4_4_DLL_CAL_DONE = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_4_4_DLL_CAL_ERROR = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_4_4_DLL_COMPARE_OUT = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DEBUG_SEL_P0_0_01_HS_PROBE_A = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DEBUG_SEL_P0_0_01_HS_PROBE_A_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DEBUG_SEL_P0_0_01_HS_PROBE_B = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DEBUG_SEL_P0_0_01_HS_PROBE_B_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DEBUG_SEL_P0_0_01_RD = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DEBUG_SEL_P0_0_01_RD_LEN = 4 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DEBUG_SEL_P0_1_01_HS_PROBE_A = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DEBUG_SEL_P0_1_01_HS_PROBE_A_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DEBUG_SEL_P0_1_01_HS_PROBE_B = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DEBUG_SEL_P0_1_01_HS_PROBE_B_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DEBUG_SEL_P0_1_01_RD = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DEBUG_SEL_P0_1_01_RD_LEN = 4 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DEBUG_SEL_P0_2_23_HS_PROBE_A = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DEBUG_SEL_P0_2_23_HS_PROBE_A_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DEBUG_SEL_P0_2_23_HS_PROBE_B = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DEBUG_SEL_P0_2_23_HS_PROBE_B_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DEBUG_SEL_P0_2_23_RD = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DEBUG_SEL_P0_2_23_RD_LEN = 4 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DEBUG_SEL_P0_3_23_HS_PROBE_A = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DEBUG_SEL_P0_3_23_HS_PROBE_A_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DEBUG_SEL_P0_3_23_HS_PROBE_B = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DEBUG_SEL_P0_3_23_HS_PROBE_B_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DEBUG_SEL_P0_3_23_RD = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DEBUG_SEL_P0_3_23_RD_LEN = 4 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DEBUG_SEL_P0_4_4_HS_PROBE_A = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DEBUG_SEL_P0_4_4_HS_PROBE_A_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DEBUG_SEL_P0_4_4_HS_PROBE_B = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DEBUG_SEL_P0_4_4_HS_PROBE_B_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DEBUG_SEL_P0_4_4_RD = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DEBUG_SEL_P0_4_4_RD_LEN = 4 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_0_01_QUAD0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_0_01_QUAD0_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_0_01_QUAD1 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_0_01_QUAD1_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_0_01_QUAD2 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_0_01_QUAD2_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_0_01_QUAD3 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_0_01_QUAD3_LEN = 4 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_1_01_QUAD0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_1_01_QUAD0_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_1_01_QUAD1 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_1_01_QUAD1_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_1_01_QUAD2 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_1_01_QUAD2_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_1_01_QUAD3 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_1_01_QUAD3_LEN = 4 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_2_23_QUAD0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_2_23_QUAD0_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_2_23_QUAD1 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_2_23_QUAD1_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_2_23_QUAD2 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_2_23_QUAD2_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_2_23_QUAD3 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_2_23_QUAD3_LEN = 4 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_3_23_QUAD0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_3_23_QUAD0_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_3_23_QUAD1 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_3_23_QUAD1_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_3_23_QUAD2 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_3_23_QUAD2_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_3_23_QUAD3 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_3_23_QUAD3_LEN = 4 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_4_4_QUAD0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_4_4_QUAD0_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_4_4_QUAD1 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_4_4_QUAD1_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_4_4_QUAD2 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_4_4_QUAD2_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_4_4_QUAD3 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_4_4_QUAD3_LEN = 4 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_0_01_DIGITAL_EN = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_0_01_BUMP = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_0_01_TRIG_PERIOD = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_0_01_CNTL_POL = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_0_01_CNTL_SRC = 55 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_1_01_DIGITAL_EN = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_1_01_BUMP = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_1_01_TRIG_PERIOD = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_1_01_CNTL_POL = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_1_01_CNTL_SRC = 55 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_2_23_DIGITAL_EN = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_2_23_BUMP = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_2_23_TRIG_PERIOD = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_2_23_CNTL_POL = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_2_23_CNTL_SRC = 55 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_3_23_DIGITAL_EN = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_3_23_BUMP = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_3_23_TRIG_PERIOD = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_3_23_CNTL_POL = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_3_23_CNTL_SRC = 55 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_4_4_DIGITAL_EN = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_4_4_BUMP = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_4_4_TRIG_PERIOD = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_4_4_CNTL_POL = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_4_4_CNTL_SRC = 55 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_PDA_CONTROL_P0_0_01_FORCE_OUTPUTS = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_PDA_CONTROL_P0_0_01_PRBS7_GEN_EN = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_PDA_CONTROL_P0_0_01_WRAPSEL = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_PDA_CONTROL_P0_0_01_MRS_CMD_DATA_N0 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_PDA_CONTROL_P0_0_01_MRS_CMD_DATA_N1 = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_PDA_CONTROL_P0_0_01_MRS_CMD_DATA_N2 = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_PDA_CONTROL_P0_0_01_MRS_CMD_DATA_N3 = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_PDA_CONTROL_P0_1_01_FORCE_OUTPUTS = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_PDA_CONTROL_P0_1_01_PRBS7_GEN_EN = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_PDA_CONTROL_P0_1_01_WRAPSEL = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_PDA_CONTROL_P0_1_01_MRS_CMD_DATA_N0 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_PDA_CONTROL_P0_1_01_MRS_CMD_DATA_N1 = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_PDA_CONTROL_P0_1_01_MRS_CMD_DATA_N2 = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_PDA_CONTROL_P0_1_01_MRS_CMD_DATA_N3 = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_PDA_CONTROL_P0_2_23_FORCE_OUTPUTS = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_PDA_CONTROL_P0_2_23_PRBS7_GEN_EN = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_PDA_CONTROL_P0_2_23_WRAPSEL = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_PDA_CONTROL_P0_2_23_MRS_CMD_DATA_N0 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_PDA_CONTROL_P0_2_23_MRS_CMD_DATA_N1 = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_PDA_CONTROL_P0_2_23_MRS_CMD_DATA_N2 = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_PDA_CONTROL_P0_2_23_MRS_CMD_DATA_N3 = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_PDA_CONTROL_P0_3_23_FORCE_OUTPUTS = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_PDA_CONTROL_P0_3_23_PRBS7_GEN_EN = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_PDA_CONTROL_P0_3_23_WRAPSEL = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_PDA_CONTROL_P0_3_23_MRS_CMD_DATA_N0 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_PDA_CONTROL_P0_3_23_MRS_CMD_DATA_N1 = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_PDA_CONTROL_P0_3_23_MRS_CMD_DATA_N2 = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_PDA_CONTROL_P0_3_23_MRS_CMD_DATA_N3 = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_PDA_CONTROL_P0_4_4_FORCE_OUTPUTS = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_PDA_CONTROL_P0_4_4_PRBS7_GEN_EN = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_PDA_CONTROL_P0_4_4_WRAPSEL = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_PDA_CONTROL_P0_4_4_MRS_CMD_DATA_N0 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_PDA_CONTROL_P0_4_4_MRS_CMD_DATA_N1 = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_PDA_CONTROL_P0_4_4_MRS_CMD_DATA_N2 = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_PDA_CONTROL_P0_4_4_MRS_CMD_DATA_N3 = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_0_01_CHECKER_ENABLE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_0_01_CHECKER_RESET = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_0_01_SYNC = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_0_01_SYNC_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_0_01_ERROR = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_0_01_ERROR_LEN = 4 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_1_01_CHECKER_ENABLE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_1_01_CHECKER_RESET = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_1_01_SYNC = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_1_01_SYNC_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_1_01_ERROR = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_1_01_ERROR_LEN = 4 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_2_23_CHECKER_ENABLE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_2_23_CHECKER_RESET = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_2_23_SYNC = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_2_23_SYNC_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_2_23_ERROR = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_2_23_ERROR_LEN = 4 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_3_23_CHECKER_ENABLE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_3_23_CHECKER_RESET = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_3_23_SYNC = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_3_23_SYNC_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_3_23_ERROR = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_3_23_ERROR_LEN = 4 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_4_4_CHECKER_ENABLE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_4_4_CHECKER_RESET = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_4_4_SYNC = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_4_4_SYNC_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_4_4_ERROR = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_4_4_ERROR_LEN = 4 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_INIT_RXDLL_CAL_RESET = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_INIT_RXDLL_CAL_UPDATE = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_REGS_RXDLL_CAL_SKIP = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_REGS_RXDLL_CAL_SKIP_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_REGS_RXDLL_COARSE_ADJ_BY2 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_RXREG_FILTER_LENGTH_DC = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_RXREG_FILTER_LENGTH_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_RXREG_LEAD_LAG_SEPARATION_DC = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_RXREG_LEAD_LAG_SEPARATION_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_EN_DRIVER_INVFB_DC = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_CAL_GOOD = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_CAL_ERROR = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_CAL_ERROR_FINE = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_INIT_RXDLL_CAL_RESET = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_INIT_RXDLL_CAL_UPDATE = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_REGS_RXDLL_CAL_SKIP = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_REGS_RXDLL_CAL_SKIP_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_REGS_RXDLL_COARSE_ADJ_BY2 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_RXREG_FILTER_LENGTH_DC = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_RXREG_FILTER_LENGTH_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_RXREG_LEAD_LAG_SEPARATION_DC = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_RXREG_LEAD_LAG_SEPARATION_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_EN_DRIVER_INVFB_DC = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_CAL_GOOD = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_CAL_ERROR = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_CAL_ERROR_FINE = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_INIT_RXDLL_CAL_RESET = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_INIT_RXDLL_CAL_UPDATE = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_REGS_RXDLL_CAL_SKIP = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_REGS_RXDLL_CAL_SKIP_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_REGS_RXDLL_COARSE_ADJ_BY2 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_RXREG_FILTER_LENGTH_DC = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_RXREG_FILTER_LENGTH_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_RXREG_LEAD_LAG_SEPARATION_DC = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_RXREG_LEAD_LAG_SEPARATION_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_EN_DRIVER_INVFB_DC = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_CAL_GOOD = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_CAL_ERROR = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_CAL_ERROR_FINE = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_INIT_RXDLL_CAL_RESET = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_INIT_RXDLL_CAL_UPDATE = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_REGS_RXDLL_CAL_SKIP = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_REGS_RXDLL_CAL_SKIP_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_REGS_RXDLL_COARSE_ADJ_BY2 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_RXREG_FILTER_LENGTH_DC = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_RXREG_FILTER_LENGTH_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_RXREG_LEAD_LAG_SEPARATION_DC = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_RXREG_LEAD_LAG_SEPARATION_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_EN_DRIVER_INVFB_DC = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_CAL_GOOD = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_CAL_ERROR = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_CAL_ERROR_FINE = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_INIT_RXDLL_CAL_RESET = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_INIT_RXDLL_CAL_UPDATE = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_REGS_RXDLL_CAL_SKIP = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_REGS_RXDLL_CAL_SKIP_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_REGS_RXDLL_COARSE_ADJ_BY2 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_RXREG_FILTER_LENGTH_DC = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_RXREG_FILTER_LENGTH_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_RXREG_LEAD_LAG_SEPARATION_DC = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_RXREG_LEAD_LAG_SEPARATION_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_EN_DRIVER_INVFB_DC = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_CAL_GOOD = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_CAL_ERROR = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_CAL_ERROR_FINE = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_INIT_RXDLL_CAL_RESET = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_INIT_RXDLL_CAL_UPDATE = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_REGS_RXDLL_CAL_SKIP = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_REGS_RXDLL_CAL_SKIP_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_REGS_RXDLL_COARSE_ADJ_BY2 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_RXREG_FILTER_LENGTH_DC = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_RXREG_FILTER_LENGTH_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_RXREG_LEAD_LAG_SEPARATION_DC = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_RXREG_LEAD_LAG_SEPARATION_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_EN_DRIVER_INVFB_DC = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_CAL_GOOD = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_CAL_ERROR = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_CAL_ERROR_FINE = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_INIT_RXDLL_CAL_RESET = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_INIT_RXDLL_CAL_UPDATE = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_REGS_RXDLL_CAL_SKIP = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_REGS_RXDLL_CAL_SKIP_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_REGS_RXDLL_COARSE_ADJ_BY2 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_RXREG_FILTER_LENGTH_DC = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_RXREG_FILTER_LENGTH_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_RXREG_LEAD_LAG_SEPARATION_DC = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_RXREG_LEAD_LAG_SEPARATION_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_EN_DRIVER_INVFB_DC = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_CAL_GOOD = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_CAL_ERROR = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_CAL_ERROR_FINE = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_INIT_RXDLL_CAL_RESET = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_INIT_RXDLL_CAL_UPDATE = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_REGS_RXDLL_CAL_SKIP = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_REGS_RXDLL_CAL_SKIP_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_REGS_RXDLL_COARSE_ADJ_BY2 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_RXREG_FILTER_LENGTH_DC = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_RXREG_FILTER_LENGTH_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_RXREG_LEAD_LAG_SEPARATION_DC = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_RXREG_LEAD_LAG_SEPARATION_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_EN_DRIVER_INVFB_DC = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_CAL_GOOD = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_CAL_ERROR = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_CAL_ERROR_FINE = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_INIT_RXDLL_CAL_RESET = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_INIT_RXDLL_CAL_UPDATE = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_REGS_RXDLL_CAL_SKIP = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_REGS_RXDLL_CAL_SKIP_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_REGS_RXDLL_COARSE_ADJ_BY2 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_RXREG_FILTER_LENGTH_DC = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_RXREG_FILTER_LENGTH_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_RXREG_LEAD_LAG_SEPARATION_DC = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_RXREG_LEAD_LAG_SEPARATION_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_EN_DRIVER_INVFB_DC = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_CAL_GOOD = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_CAL_ERROR = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_CAL_ERROR_FINE = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_INIT_RXDLL_CAL_RESET = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_INIT_RXDLL_CAL_UPDATE = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_REGS_RXDLL_CAL_SKIP = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_REGS_RXDLL_CAL_SKIP_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_REGS_RXDLL_COARSE_ADJ_BY2 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_RXREG_FILTER_LENGTH_DC = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_RXREG_FILTER_LENGTH_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_RXREG_LEAD_LAG_SEPARATION_DC = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_RXREG_LEAD_LAG_SEPARATION_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_EN_DRIVER_INVFB_DC = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_CAL_GOOD = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_CAL_ERROR = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_CAL_ERROR_FINE = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CONFIG1_P0_0_01_HS_DLLMUX_SEL_0_3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CONFIG1_P0_0_01_HS_DLLMUX_SEL_0_3_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CONFIG1_P0_0_01_HS_DLLMUX_SEL_1_3 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CONFIG1_P0_0_01_HS_DLLMUX_SEL_1_3_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CONFIG1_P0_0_01_S0INSDLYTAP = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CONFIG1_P0_0_01_S1INSDLYTAP = 62 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CONFIG1_P0_1_01_HS_DLLMUX_SEL_0_0_3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CONFIG1_P0_1_01_HS_DLLMUX_SEL_0_0_3_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CONFIG1_P0_1_01_HS_DLLMUX_SEL_0_3 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CONFIG1_P0_1_01_HS_DLLMUX_SEL_0_3_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CONFIG1_P0_1_01_S0INSDLYTAP = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CONFIG1_P0_1_01_S1INSDLYTAP = 62 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CONFIG1_P0_2_23_HS_DLLMUX_SEL_0_0_3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CONFIG1_P0_2_23_HS_DLLMUX_SEL_0_0_3_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CONFIG1_P0_2_23_HS_DLLMUX_SEL_1_0_3 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CONFIG1_P0_2_23_HS_DLLMUX_SEL_1_0_3_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CONFIG1_P0_2_23_S0INSDLYTAP = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CONFIG1_P0_2_23_S1INSDLYTAP = 62 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CONFIG1_P0_3_23_HS_DLLMUX_SEL_0_0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CONFIG1_P0_3_23_HS_DLLMUX_SEL_0_0_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CONFIG1_P0_3_23_HS_DLLMUX_SEL_1_0 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CONFIG1_P0_3_23_HS_DLLMUX_SEL_1_0_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CONFIG1_P0_3_23_S0INSDLYTAP = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CONFIG1_P0_3_23_S1INSDLYTAP = 62 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CONFIG1_P0_4_4_HS_DLLMUX_SEL_0_0_3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CONFIG1_P0_4_4_HS_DLLMUX_SEL_0_0_3_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CONFIG1_P0_4_4_HS_DLLMUX_SEL_1_0_3 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CONFIG1_P0_4_4_HS_DLLMUX_SEL_1_0_3_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CONFIG1_P0_4_4_S0INSDLYTAP = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CONFIG1_P0_4_4_S1INSDLYTAP = 62 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_0_01_REGS_RXDLL_VREG_LOWER = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_0_01_REGS_RXDLL_VREG_LOWER_LEN = 15 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_0_01_RESERVED_63 = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_1_01_REGS_RXDLL_VREG_LOWER = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_1_01_REGS_RXDLL_VREG_LOWER_LEN = 15 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_1_01_RESERVED_63 = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_2_23_REGS_RXDLL_VREG_LOWER = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_2_23_REGS_RXDLL_VREG_LOWER_LEN = 15 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_2_23_RESERVED_63 = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_3_23_REGS_RXDLL_VREG_LOWER = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_3_23_REGS_RXDLL_VREG_LOWER_LEN = 15 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_3_23_RESERVED_63 = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_4_4_REGS_RXDLL_VREG_LOWER = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_4_4_REGS_RXDLL_VREG_LOWER_LEN = 15 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_4_4_RESERVED_63 = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_0_01_REGS_RXDLL_VREG_LOWER = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_0_01_REGS_RXDLL_VREG_LOWER_LEN = 15 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_0_01_RESERVED_63 = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_1_01_REGS_RXDLL_VREG_LOWER = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_1_01_REGS_RXDLL_VREG_LOWER_LEN = 15 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_1_01_RESERVED_63 = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_2_23_REGS_RXDLL_VREG_LOWER = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_2_23_REGS_RXDLL_VREG_LOWER_LEN = 15 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_2_23_RESERVED_63 = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_3_23_REGS_RXDLL_VREG_LOWER = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_3_23_REGS_RXDLL_VREG_LOWER_LEN = 15 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_3_23_RESERVED_63 = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_4_4_REGS_RXDLL_VREG_LOWER = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_4_4_REGS_RXDLL_VREG_LOWER_LEN = 15 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_4_4_RESERVED_63 = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_0_01_REGS_RXDLL_VREG_UPPER = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_0_01_REGS_RXDLL_VREG_UPPER_LEN = 15 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_0_01_RESERVED_63 = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_1_01_REGS_RXDLL_VREG_UPPER = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_1_01_REGS_RXDLL_VREG_UPPER_LEN = 15 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_1_01_RESERVED_63 = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_2_23_REGS_RXDLL_VREG_UPPER = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_2_23_REGS_RXDLL_VREG_UPPER_LEN = 15 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_2_23_RESERVED_63 = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_3_23_REGS_RXDLL_VREG_UPPER = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_3_23_REGS_RXDLL_VREG_UPPER_LEN = 15 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_3_23_RESERVED_63 = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_4_4_REGS_RXDLL_VREG_UPPER = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_4_4_REGS_RXDLL_VREG_UPPER_LEN = 15 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_4_4_RESERVED_63 = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_0_01_REGS_RXDLL_VREG_UPPER = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_0_01_REGS_RXDLL_VREG_UPPER_LEN = 15 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_0_01_RESERVED_63 = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_1_01_REGS_RXDLL_VREG_UPPER = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_1_01_REGS_RXDLL_VREG_UPPER_LEN = 15 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_1_01_RESERVED_63 = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_2_23_REGS_RXDLL_VREG_UPPER = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_2_23_REGS_RXDLL_VREG_UPPER_LEN = 15 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_2_23_RESERVED_63 = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_3_23_REGS_RXDLL_VREG_UPPER = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_3_23_REGS_RXDLL_VREG_UPPER_LEN = 15 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_3_23_RESERVED_63 = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_4_4_REGS_RXDLL_VREG_UPPER = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_4_4_REGS_RXDLL_VREG_UPPER_LEN = 15 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_4_4_RESERVED_63 = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA0_P0_0_01_SLAVE_VREG_OVERRIDE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA0_P0_0_01_SLAVE_VREG_REF_SEL_DC = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA0_P0_0_01_SLAVE_VREG_REF_SEL_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA0_P0_0_01_SLAVE_VREG_DAC_COARSE = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA0_P0_0_01_SLAVE_VREG_DAC_COARSE_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA0_P0_1_01_SLAVE_VREG_OVERRIDE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA0_P0_1_01_SLAVE_VREG_REF_SEL_DC = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA0_P0_1_01_SLAVE_VREG_REF_SEL_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA0_P0_1_01_SLAVE_VREG_DAC_COARSE = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA0_P0_1_01_SLAVE_VREG_DAC_COARSE_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA0_P0_2_23_SLAVE_VREG_OVERRIDE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA0_P0_2_23_SLAVE_VREG_REF_SEL_DC = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA0_P0_2_23_SLAVE_VREG_REF_SEL_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA0_P0_2_23_SLAVE_VREG_DAC_COARSE = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA0_P0_2_23_SLAVE_VREG_DAC_COARSE_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA0_P0_3_23_SLAVE_VREG_OVERRIDE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA0_P0_3_23_SLAVE_VREG_REF_SEL_DC = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA0_P0_3_23_SLAVE_VREG_REF_SEL_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA0_P0_3_23_SLAVE_VREG_DAC_COARSE = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA0_P0_3_23_SLAVE_VREG_DAC_COARSE_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA0_P0_4_4_SLAVE_VREG_OVERRIDE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA0_P0_4_4_SLAVE_VREG_REF_SEL_DC = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA0_P0_4_4_SLAVE_VREG_REF_SEL_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA0_P0_4_4_SLAVE_VREG_DAC_COARSE = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA0_P0_4_4_SLAVE_VREG_DAC_COARSE_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA1_P0_0_01_SLAVE_VREG_OVERRIDE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA1_P0_0_01_SLAVE_VREG_REF_SEL_DC = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA1_P0_0_01_SLAVE_VREG_REF_SEL_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA1_P0_0_01_SLAVE_VREG_DAC_COARSE = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA1_P0_0_01_SLAVE_VREG_DAC_COARSE_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA1_P0_1_01_SLAVE_VREG_OVERRIDE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA1_P0_1_01_SLAVE_VREG_REF_SEL_DC = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA1_P0_1_01_SLAVE_VREG_REF_SEL_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA1_P0_1_01_SLAVE_VREG_DAC_COARSE = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA1_P0_1_01_SLAVE_VREG_DAC_COARSE_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA1_P0_2_23_SLAVE_VREG_OVERRIDE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA1_P0_2_23_SLAVE_VREG_REF_SEL_DC = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA1_P0_2_23_SLAVE_VREG_REF_SEL_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA1_P0_2_23_SLAVE_VREG_DAC_COARSE = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA1_P0_2_23_SLAVE_VREG_DAC_COARSE_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA1_P0_3_23_SLAVE_VREG_OVERRIDE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA1_P0_3_23_SLAVE_VREG_REF_SEL_DC = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA1_P0_3_23_SLAVE_VREG_REF_SEL_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA1_P0_3_23_SLAVE_VREG_DAC_COARSE = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA1_P0_3_23_SLAVE_VREG_DAC_COARSE_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA1_P0_4_4_SLAVE_VREG_OVERRIDE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA1_P0_4_4_SLAVE_VREG_REF_SEL_DC = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA1_P0_4_4_SLAVE_VREG_REF_SEL_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA1_P0_4_4_SLAVE_VREG_DAC_COARSE = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA1_P0_4_4_SLAVE_VREG_DAC_COARSE_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_0_01_LOWER = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_0_01_LOWER_LEN = 15 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_1_01_LOWER = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_1_01_LOWER_LEN = 15 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_2_23_LOWER = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_2_23_LOWER_LEN = 15 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_3_23_LOWER = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_3_23_LOWER_LEN = 15 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_4_4_LOWER = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_4_4_LOWER_LEN = 15 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_0_01_LOWER = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_0_01_LOWER_LEN = 15 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_1_01_LOWER = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_1_01_LOWER_LEN = 15 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_2_23_LOWER = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_2_23_LOWER_LEN = 15 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_3_23_LOWER = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_3_23_LOWER_LEN = 15 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_4_4_LOWER = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_4_4_LOWER_LEN = 15 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_0_01_UPPER = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_0_01_UPPER_LEN = 15 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_1_01_UPPER = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_1_01_UPPER_LEN = 15 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_2_23_UPPER = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_2_23_UPPER_LEN = 15 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_3_23_UPPER = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_3_23_UPPER_LEN = 15 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_4_4_UPPER = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_4_4_UPPER_LEN = 15 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_0_01_UPPER = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_0_01_UPPER_LEN = 15 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_1_01_UPPER = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_1_01_UPPER_LEN = 15 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_2_23_UPPER = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_2_23_UPPER_LEN = 15 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_3_23_UPPER = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_3_23_UPPER_LEN = 15 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_4_4_UPPER = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_4_4_UPPER_LEN = 15 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_0_01_OVERRIDE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_0_01_CAL_PD_ENABLE = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_0_01_MAIN_PD_ENABLE = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_0_01_DETECT_REQ = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_0_01_SLAVE_CAL_CKT_POWERDOWN = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_0_01_VREG_RXCAL_COMP_OUT_META = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_0_01_RXCAL_DETECT_DONE_META = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_0_01_RXCAL_PD_CAL_LAG_META = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_0_01_RXCAL_PD_MAIN_LEAD_META = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_0_01_RXCAL_PD_MAIN_LAG_META = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_0_01_VREG_SLAVE_COMP_OUT = 61 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_1_01_OVERRIDE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_1_01_CAL_PD_ENABLE = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_1_01_MAIN_PD_ENABLE = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_1_01_DETECT_REQ = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_1_01_SLAVE_CAL_CKT_POWERDOWN = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_1_01_VREG_RXCAL_COMP_OUT_META = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_1_01_RXCAL_DETECT_DONE_META = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_1_01_RXCAL_PD_CAL_LAG_META = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_1_01_RXCAL_PD_MAIN_LEAD_META = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_1_01_RXCAL_PD_MAIN_LAG_META = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_1_01_VREG_SLAVE_COMP_OUT = 61 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_2_23_OVERRIDE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_2_23_CAL_PD_ENABLE = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_2_23_MAIN_PD_ENABLE = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_2_23_DETECT_REQ = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_2_23_SLAVE_CAL_CKT_POWERDOWN = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_2_23_VREG_RXCAL_COMP_OUT_META = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_2_23_RXCAL_DETECT_DONE_META = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_2_23_RXCAL_PD_CAL_LAG_META = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_2_23_RXCAL_PD_MAIN_LEAD_META = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_2_23_RXCAL_PD_MAIN_LAG_META = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_2_23_VREG_SLAVE_COMP_OUT = 61 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_3_23_OVERRIDE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_3_23_CAL_PD_ENABLE = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_3_23_MAIN_PD_ENABLE = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_3_23_DETECT_REQ = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_3_23_SLAVE_CAL_CKT_POWERDOWN = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_3_23_VREG_RXCAL_COMP_OUT_META = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_3_23_RXCAL_DETECT_DONE_META = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_3_23_RXCAL_PD_CAL_LAG_META = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_3_23_RXCAL_PD_MAIN_LEAD_META = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_3_23_RXCAL_PD_MAIN_LAG_META = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_3_23_VREG_SLAVE_COMP_OUT = 61 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_4_4_OVERRIDE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_4_4_CAL_PD_ENABLE = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_4_4_MAIN_PD_ENABLE = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_4_4_DETECT_REQ = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_4_4_SLAVE_CAL_CKT_POWERDOWN = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_4_4_VREG_RXCAL_COMP_OUT_META = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_4_4_RXCAL_DETECT_DONE_META = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_4_4_RXCAL_PD_CAL_LAG_META = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_4_4_RXCAL_PD_MAIN_LEAD_META = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_4_4_RXCAL_PD_MAIN_LAG_META = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_4_4_VREG_SLAVE_COMP_OUT = 61 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_0_01_OVERRIDE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_0_01_CAL_PD_ENABLE = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_0_01_MAIN_PD_ENABLE = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_0_01_DETECT_REQ = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_0_01_SLAVE_CAL_CKT_POWERDOWN = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_0_01_VREG_RXCAL_COMP_OUT_META = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_0_01_RXCAL_DETECT_DONE_META = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_0_01_RXCAL_PD_CAL_LAG_META = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_0_01_RXCAL_PD_MAIN_LEAD_META = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_0_01_RXCAL_PD_MAIN_LAG_META = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_0_01_VREG_SLAVE_COMP_OUT = 61 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_1_01_OVERRIDE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_1_01_CAL_PD_ENABLE = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_1_01_MAIN_PD_ENABLE = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_1_01_DETECT_REQ = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_1_01_SLAVE_CAL_CKT_POWERDOWN = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_1_01_VREG_RXCAL_COMP_OUT_META = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_1_01_RXCAL_DETECT_DONE_META = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_1_01_RXCAL_PD_CAL_LAG_META = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_1_01_RXCAL_PD_MAIN_LEAD_META = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_1_01_RXCAL_PD_MAIN_LAG_META = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_1_01_VREG_SLAVE_COMP_OUT = 61 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_2_23_OVERRIDE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_2_23_CAL_PD_ENABLE = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_2_23_MAIN_PD_ENABLE = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_2_23_DETECT_REQ = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_2_23_SLAVE_CAL_CKT_POWERDOWN = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_2_23_VREG_RXCAL_COMP_OUT_META = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_2_23_RXCAL_DETECT_DONE_META = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_2_23_RXCAL_PD_CAL_LAG_META = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_2_23_RXCAL_PD_MAIN_LEAD_META = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_2_23_RXCAL_PD_MAIN_LAG_META = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_2_23_VREG_SLAVE_COMP_OUT = 61 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_3_23_OVERRIDE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_3_23_CAL_PD_ENABLE = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_3_23_MAIN_PD_ENABLE = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_3_23_DETECT_REQ = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_3_23_SLAVE_CAL_CKT_POWERDOWN = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_3_23_VREG_RXCAL_COMP_OUT_META = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_3_23_RXCAL_DETECT_DONE_META = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_3_23_RXCAL_PD_CAL_LAG_META = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_3_23_RXCAL_PD_MAIN_LEAD_META = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_3_23_RXCAL_PD_MAIN_LAG_META = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_3_23_VREG_SLAVE_COMP_OUT = 61 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_4_4_OVERRIDE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_4_4_CAL_PD_ENABLE = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_4_4_MAIN_PD_ENABLE = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_4_4_DETECT_REQ = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_4_4_SLAVE_CAL_CKT_POWERDOWN = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_4_4_VREG_RXCAL_COMP_OUT_META = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_4_4_RXCAL_DETECT_DONE_META = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_4_4_RXCAL_PD_CAL_LAG_META = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_4_4_RXCAL_PD_MAIN_LEAD_META = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_4_4_RXCAL_PD_MAIN_LAG_META = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_4_4_VREG_SLAVE_COMP_OUT = 61 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_0_01_REGS_RXDLL_COARSE_EN = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_0_01_REGS_RXDLL_COARSE_EN_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_0_01_REGS_RXDLL_DAC_COARSE = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_0_01_REGS_RXDLL_DAC_COARSE_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_1_01_REGS_RXDLL_COARSE_EN = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_1_01_REGS_RXDLL_COARSE_EN_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_1_01_REGS_RXDLL_DAC_COARSE = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_1_01_REGS_RXDLL_DAC_COARSE_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_2_23_REGS_RXDLL_COARSE_EN = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_2_23_REGS_RXDLL_COARSE_EN_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_2_23_REGS_RXDLL_DAC_COARSE = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_2_23_REGS_RXDLL_DAC_COARSE_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_3_23_REGS_RXDLL_COARSE_EN = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_3_23_REGS_RXDLL_COARSE_EN_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_3_23_REGS_RXDLL_DAC_COARSE = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_3_23_REGS_RXDLL_DAC_COARSE_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_4_4_REGS_RXDLL_COARSE_EN = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_4_4_REGS_RXDLL_COARSE_EN_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_4_4_REGS_RXDLL_DAC_COARSE = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_4_4_REGS_RXDLL_DAC_COARSE_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_0_01_REGS_RXDLL_COARSE_EN = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_0_01_REGS_RXDLL_COARSE_EN_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_0_01_REGS_RXDLL_DAC_COARSE = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_0_01_REGS_RXDLL_DAC_COARSE_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_1_01_REGS_RXDLL_COARSE_EN = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_1_01_REGS_RXDLL_COARSE_EN_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_1_01_REGS_RXDLL_DAC_COARSE = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_1_01_REGS_RXDLL_DAC_COARSE_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_2_23_REGS_RXDLL_COARSE_EN = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_2_23_REGS_RXDLL_COARSE_EN_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_2_23_REGS_RXDLL_DAC_COARSE = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_2_23_REGS_RXDLL_DAC_COARSE_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_3_23_REGS_RXDLL_COARSE_EN = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_3_23_REGS_RXDLL_COARSE_EN_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_3_23_REGS_RXDLL_DAC_COARSE = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_3_23_REGS_RXDLL_DAC_COARSE_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_4_4_REGS_RXDLL_COARSE_EN = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_4_4_REGS_RXDLL_COARSE_EN_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_4_4_REGS_RXDLL_DAC_COARSE = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_4_4_REGS_RXDLL_DAC_COARSE_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_0_01_RXREG_COMPCON_DC = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_0_01_RXREG_COMPCON_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_0_01_RXREG_DAC_PULLUP_DC = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_0_01_RXREG_DRVCON_DC = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_0_01_RXREG_DRVCON_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_0_01_RXREG_REF_SEL_DC = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_0_01_RXREG_REF_SEL_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_0_01_REGS_RXDLL_COARSE_ADJ_BY0 = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_0_01_DRVREN_MODE = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_0_01_CAL_CKTS_ACTIVE = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_1_01_RXREG_COMPCON_DC = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_1_01_RXREG_COMPCON_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_1_01_RXREG_DAC_PULLUP_DC = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_1_01_RXREG_DRVCON_DC = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_1_01_RXREG_DRVCON_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_1_01_RXREG_REF_SEL_DC = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_1_01_RXREG_REF_SEL_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_1_01_REGS_RXDLL_COARSE_ADJ_BY0 = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_1_01_DRVREN_MODE = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_1_01_CAL_CKTS_ACTIVE = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_2_23_RXREG_COMPCON_DC = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_2_23_RXREG_COMPCON_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_2_23_RXREG_DAC_PULLUP_DC = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_2_23_RXREG_DRVCON_DC = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_2_23_RXREG_DRVCON_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_2_23_RXREG_REF_SEL_DC = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_2_23_RXREG_REF_SEL_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_2_23_REGS_RXDLL_COARSE_ADJ_BY0 = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_2_23_DRVREN_MODE = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_2_23_CAL_CKTS_ACTIVE = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_3_23_RXREG_COMPCON_DC = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_3_23_RXREG_COMPCON_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_3_23_RXREG_DAC_PULLUP_DC = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_3_23_RXREG_DRVCON_DC = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_3_23_RXREG_DRVCON_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_3_23_RXREG_REF_SEL_DC = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_3_23_RXREG_REF_SEL_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_3_23_REGS_RXDLL_COARSE_ADJ_BY0 = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_3_23_DRVREN_MODE = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_3_23_CAL_CKTS_ACTIVE = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_4_4_RXREG_COMPCON_DC = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_4_4_RXREG_COMPCON_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_4_4_RXREG_DAC_PULLUP_DC = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_4_4_RXREG_DRVCON_DC = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_4_4_RXREG_DRVCON_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_4_4_RXREG_REF_SEL_DC = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_4_4_RXREG_REF_SEL_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_4_4_REGS_RXDLL_COARSE_ADJ_BY0 = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_4_4_DRVREN_MODE = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_4_4_CAL_CKTS_ACTIVE = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_0_01_RXREG_COMPCON_DC = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_0_01_RXREG_COMPCON_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_0_01_RXREG_DAC_PULLUP_DC = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_0_01_RXREG_DRVCON_DC = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_0_01_RXREG_DRVCON_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_0_01_RXREG_REF_SEL_DC = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_0_01_RXREG_REF_SEL_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_0_01_REGS_RXDLL_COARSE_ADJ_BY0 = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_0_01_DRVREN_MODE = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_0_01_CAL_CKTS_ACTIVE = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_1_01_RXREG_COMPCON_DC = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_1_01_RXREG_COMPCON_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_1_01_RXREG_DAC_PULLUP_DC = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_1_01_RXREG_DRVCON_DC = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_1_01_RXREG_DRVCON_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_1_01_RXREG_REF_SEL_DC = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_1_01_RXREG_REF_SEL_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_1_01_REGS_RXDLL_COARSE_ADJ_BY0 = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_1_01_DRVREN_MODE = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_1_01_CAL_CKTS_ACTIVE = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_2_23_RXREG_COMPCON_DC = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_2_23_RXREG_COMPCON_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_2_23_RXREG_DAC_PULLUP_DC = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_2_23_RXREG_DRVCON_DC = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_2_23_RXREG_DRVCON_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_2_23_RXREG_REF_SEL_DC = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_2_23_RXREG_REF_SEL_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_2_23_REGS_RXDLL_COARSE_ADJ_BY0 = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_2_23_DRVREN_MODE = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_2_23_CAL_CKTS_ACTIVE = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_3_23_RXREG_COMPCON_DC = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_3_23_RXREG_COMPCON_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_3_23_RXREG_DAC_PULLUP_DC = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_3_23_RXREG_DRVCON_DC = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_3_23_RXREG_DRVCON_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_3_23_RXREG_REF_SEL_DC = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_3_23_RXREG_REF_SEL_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_3_23_REGS_RXDLL_COARSE_ADJ_BY0 = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_3_23_DRVREN_MODE = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_3_23_CAL_CKTS_ACTIVE = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_4_4_RXREG_COMPCON_DC = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_4_4_RXREG_COMPCON_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_4_4_RXREG_DAC_PULLUP_DC = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_4_4_RXREG_DRVCON_DC = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_4_4_RXREG_DRVCON_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_4_4_RXREG_REF_SEL_DC = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_4_4_RXREG_REF_SEL_DC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_4_4_REGS_RXDLL_COARSE_ADJ_BY0 = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_4_4_DRVREN_MODE = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_4_4_CAL_CKTS_ACTIVE = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_OFFSET_P0_0_01_DQS = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_OFFSET_P0_0_01_DQS_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_OFFSET_P0_1_01_DQS = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_OFFSET_P0_1_01_DQS_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_OFFSET_P0_2_23_DQS = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_OFFSET_P0_2_23_DQS_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_OFFSET_P0_3_23_DQS = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_OFFSET_P0_3_23_DQS_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_OFFSET_P0_4_4_DQS = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_OFFSET_P0_4_4_DQS_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_0_01_ROT_CLK_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_0_01_ROT_CLK_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_0_01_ROT_CLK_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_0_01_ROT_CLK_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_1_01_ROT_CLK_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_1_01_ROT_CLK_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_1_01_ROT_CLK_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_1_01_ROT_CLK_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_2_23_ROT_CLK_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_2_23_ROT_CLK_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_2_23_ROT_CLK_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_2_23_ROT_CLK_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_3_23_ROT_CLK_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_3_23_ROT_CLK_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_3_23_ROT_CLK_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_3_23_ROT_CLK_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_4_4_ROT_CLK_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_4_4_ROT_CLK_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_4_4_ROT_CLK_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_4_4_ROT_CLK_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_0_01_ROT_CLK_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_0_01_ROT_CLK_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_0_01_ROT_CLK_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_0_01_ROT_CLK_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_1_01_ROT_CLK_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_1_01_ROT_CLK_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_1_01_ROT_CLK_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_1_01_ROT_CLK_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_2_23_ROT_CLK_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_2_23_ROT_CLK_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_2_23_ROT_CLK_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_2_23_ROT_CLK_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_3_23_ROT_CLK_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_3_23_ROT_CLK_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_3_23_ROT_CLK_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_3_23_ROT_CLK_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_4_4_ROT_CLK_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_4_4_ROT_CLK_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_4_4_ROT_CLK_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_4_4_ROT_CLK_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_0_01_ROT_CLK_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_0_01_ROT_CLK_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_0_01_ROT_CLK_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_0_01_ROT_CLK_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_1_01_ROT_CLK_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_1_01_ROT_CLK_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_1_01_ROT_CLK_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_1_01_ROT_CLK_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_2_23_ROT_CLK_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_2_23_ROT_CLK_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_2_23_ROT_CLK_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_2_23_ROT_CLK_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_3_23_ROT_CLK_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_3_23_ROT_CLK_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_3_23_ROT_CLK_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_3_23_ROT_CLK_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_4_4_ROT_CLK_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_4_4_ROT_CLK_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_4_4_ROT_CLK_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_4_4_ROT_CLK_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_0_01_ROT_CLK_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_0_01_ROT_CLK_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_0_01_ROT_CLK_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_0_01_ROT_CLK_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_1_01_ROT_CLK_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_1_01_ROT_CLK_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_1_01_ROT_CLK_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_1_01_ROT_CLK_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_2_23_ROT_CLK_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_2_23_ROT_CLK_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_2_23_ROT_CLK_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_2_23_ROT_CLK_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_3_23_ROT_CLK_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_3_23_ROT_CLK_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_3_23_ROT_CLK_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_3_23_ROT_CLK_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_4_4_ROT_CLK_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_4_4_ROT_CLK_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_4_4_ROT_CLK_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_4_4_ROT_CLK_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_0_01_ROT_CLK_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_0_01_ROT_CLK_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_0_01_ROT_CLK_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_0_01_ROT_CLK_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_1_01_ROT_CLK_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_1_01_ROT_CLK_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_1_01_ROT_CLK_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_1_01_ROT_CLK_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_2_23_ROT_CLK_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_2_23_ROT_CLK_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_2_23_ROT_CLK_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_2_23_ROT_CLK_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_3_23_ROT_CLK_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_3_23_ROT_CLK_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_3_23_ROT_CLK_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_3_23_ROT_CLK_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_4_4_ROT_CLK_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_4_4_ROT_CLK_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_4_4_ROT_CLK_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_4_4_ROT_CLK_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_0_01_ROT_CLK_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_0_01_ROT_CLK_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_0_01_ROT_CLK_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_0_01_ROT_CLK_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_1_01_ROT_CLK_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_1_01_ROT_CLK_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_1_01_ROT_CLK_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_1_01_ROT_CLK_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_2_23_ROT_CLK_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_2_23_ROT_CLK_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_2_23_ROT_CLK_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_2_23_ROT_CLK_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_3_23_ROT_CLK_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_3_23_ROT_CLK_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_3_23_ROT_CLK_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_3_23_ROT_CLK_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_4_4_ROT_CLK_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_4_4_ROT_CLK_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_4_4_ROT_CLK_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_4_4_ROT_CLK_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_0_01_ROT_CLK_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_0_01_ROT_CLK_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_0_01_ROT_CLK_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_0_01_ROT_CLK_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_1_01_ROT_CLK_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_1_01_ROT_CLK_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_1_01_ROT_CLK_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_1_01_ROT_CLK_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_2_23_ROT_CLK_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_2_23_ROT_CLK_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_2_23_ROT_CLK_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_2_23_ROT_CLK_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_3_23_ROT_CLK_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_3_23_ROT_CLK_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_3_23_ROT_CLK_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_3_23_ROT_CLK_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_4_4_ROT_CLK_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_4_4_ROT_CLK_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_4_4_ROT_CLK_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_4_4_ROT_CLK_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_0_01_ROT_CLK_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_0_01_ROT_CLK_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_0_01_ROT_CLK_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_0_01_ROT_CLK_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_1_01_ROT_CLK_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_1_01_ROT_CLK_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_1_01_ROT_CLK_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_1_01_ROT_CLK_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_2_23_ROT_CLK_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_2_23_ROT_CLK_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_2_23_ROT_CLK_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_2_23_ROT_CLK_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_3_23_ROT_CLK_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_3_23_ROT_CLK_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_3_23_ROT_CLK_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_3_23_ROT_CLK_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_4_4_ROT_CLK_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_4_4_ROT_CLK_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_4_4_ROT_CLK_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_4_4_ROT_CLK_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP0_P0_0_01_16_23 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP0_P0_0_01_16_23_LEN = 8 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP0_P0_1_01_16_23 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP0_P0_1_01_16_23_LEN = 8 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP0_P0_2_23_16_23 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP0_P0_2_23_16_23_LEN = 8 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP0_P0_3_23_16_23 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP0_P0_3_23_16_23_LEN = 8 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP0_P0_4_4_16_23 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP0_P0_4_4_16_23_LEN = 8 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP1_P0_0_01_16_23 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP1_P0_0_01_16_23_LEN = 8 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP1_P0_1_01_16_23 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP1_P0_1_01_16_23_LEN = 8 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP1_P0_2_23_16_23 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP1_P0_2_23_16_23_LEN = 8 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP1_P0_3_23_16_23 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP1_P0_3_23_16_23_LEN = 8 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP1_P0_4_4_16_23 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP1_P0_4_4_16_23_LEN = 8 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP2_P0_0_01_16_23 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP2_P0_0_01_16_23_LEN = 8 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP2_P0_1_01_16_23 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP2_P0_1_01_16_23_LEN = 8 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP2_P0_2_23_16_23 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP2_P0_2_23_16_23_LEN = 8 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP2_P0_3_23_16_23 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP2_P0_3_23_16_23_LEN = 8 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP2_P0_4_4_16_23 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP2_P0_4_4_16_23_LEN = 8 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP3_P0_0_01_16_23 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP3_P0_0_01_16_23_LEN = 8 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP3_P0_1_01_16_23 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP3_P0_1_01_16_23_LEN = 8 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP3_P0_2_23_16_23 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP3_P0_2_23_16_23_LEN = 8 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP3_P0_3_23_16_23 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP3_P0_3_23_16_23_LEN = 8 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP3_P0_4_4_16_23 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP3_P0_4_4_16_23_LEN = 8 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_0_01_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_0_01_N0_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_0_01_N1 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_0_01_N1_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_0_01_N2 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_0_01_N2_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_0_01_N3 = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_0_01_N3_LEN = 3 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_1_01_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_1_01_N0_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_1_01_N1 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_1_01_N1_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_1_01_N2 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_1_01_N2_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_1_01_N3 = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_1_01_N3_LEN = 3 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_2_23_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_2_23_N0_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_2_23_N1 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_2_23_N1_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_2_23_N2 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_2_23_N2_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_2_23_N3 = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_2_23_N3_LEN = 3 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_3_23_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_3_23_N0_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_3_23_N1 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_3_23_N1_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_3_23_N2 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_3_23_N2_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_3_23_N3 = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_3_23_N3_LEN = 3 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_4_4_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_4_4_N0_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_4_4_N1 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_4_4_N1_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_4_4_N2 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_4_4_N2_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_4_4_N3 = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_4_4_N3_LEN = 3 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_0_01_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_0_01_N0_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_0_01_N1 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_0_01_N1_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_0_01_N2 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_0_01_N2_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_0_01_N3 = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_0_01_N3_LEN = 3 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_1_01_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_1_01_N0_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_1_01_N1 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_1_01_N1_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_1_01_N2 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_1_01_N2_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_1_01_N3 = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_1_01_N3_LEN = 3 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_2_23_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_2_23_N0_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_2_23_N1 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_2_23_N1_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_2_23_N2 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_2_23_N2_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_2_23_N3 = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_2_23_N3_LEN = 3 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_3_23_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_3_23_N0_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_3_23_N1 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_3_23_N1_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_3_23_N2 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_3_23_N2_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_3_23_N3 = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_3_23_N3_LEN = 3 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_4_4_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_4_4_N0_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_4_4_N1 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_4_4_N1_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_4_4_N2 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_4_4_N2_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_4_4_N3 = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_4_4_N3_LEN = 3 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_0_01_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_0_01_N0_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_0_01_N1 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_0_01_N1_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_0_01_N2 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_0_01_N2_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_0_01_N3 = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_0_01_N3_LEN = 3 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_1_01_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_1_01_N0_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_1_01_N1 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_1_01_N1_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_1_01_N2 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_1_01_N2_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_1_01_N3 = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_1_01_N3_LEN = 3 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_2_23_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_2_23_N0_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_2_23_N1 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_2_23_N1_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_2_23_N2 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_2_23_N2_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_2_23_N3 = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_2_23_N3_LEN = 3 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_3_23_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_3_23_N0_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_3_23_N1 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_3_23_N1_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_3_23_N2 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_3_23_N2_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_3_23_N3 = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_3_23_N3_LEN = 3 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_4_4_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_4_4_N0_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_4_4_N1 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_4_4_N1_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_4_4_N2 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_4_4_N2_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_4_4_N3 = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_4_4_N3_LEN = 3 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_0_01_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_0_01_N0_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_0_01_N1 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_0_01_N1_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_0_01_N2 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_0_01_N2_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_0_01_N3 = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_0_01_N3_LEN = 3 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_1_01_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_1_01_N0_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_1_01_N1 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_1_01_N1_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_1_01_N2 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_1_01_N2_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_1_01_N3 = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_1_01_N3_LEN = 3 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_2_23_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_2_23_N0_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_2_23_N1 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_2_23_N1_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_2_23_N2 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_2_23_N2_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_2_23_N3 = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_2_23_N3_LEN = 3 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_3_23_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_3_23_N0_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_3_23_N1 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_3_23_N1_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_3_23_N2 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_3_23_N2_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_3_23_N3 = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_3_23_N3_LEN = 3 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_4_4_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_4_4_N0_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_4_4_N1 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_4_4_N1_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_4_4_N2 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_4_4_N2_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_4_4_N3 = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_4_4_N3_LEN = 3 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_DQSCLK_SELECT0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_DQSCLK_SELECT0_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_RDCLK_SELECT0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_RDCLK_SELECT0_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_DQSCLK_SELECT1 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_DQSCLK_SELECT1_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_RDCLK_SELECT1 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_RDCLK_SELECT1_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_DQSCLK_SELECT2 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_DQSCLK_SELECT2_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_RDCLK_SELECT2 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_RDCLK_SELECT2_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_DQSCLK_SELECT3 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_DQSCLK_SELECT3_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_RDCLK_SELECT3 = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_RDCLK_SELECT3_LEN = 2 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_DQSCLK_SELECT0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_DQSCLK_SELECT0_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_RDCLK_SELECT0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_RDCLK_SELECT0_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_DQSCLK_SELECT1 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_DQSCLK_SELECT1_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_RDCLK_SELECT1 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_RDCLK_SELECT1_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_DQSCLK_SELECT2 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_DQSCLK_SELECT2_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_RDCLK_SELECT2 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_RDCLK_SELECT2_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_DQSCLK_SELECT3 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_DQSCLK_SELECT3_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_RDCLK_SELECT3 = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_RDCLK_SELECT3_LEN = 2 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_DQSCLK_SELECT0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_DQSCLK_SELECT0_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_RDCLK_SELECT0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_RDCLK_SELECT0_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_DQSCLK_SELECT1 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_DQSCLK_SELECT1_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_RDCLK_SELECT1 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_RDCLK_SELECT1_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_DQSCLK_SELECT2 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_DQSCLK_SELECT2_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_RDCLK_SELECT2 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_RDCLK_SELECT2_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_DQSCLK_SELECT3 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_DQSCLK_SELECT3_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_RDCLK_SELECT3 = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_RDCLK_SELECT3_LEN = 2 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_DQSCLK_SELECT0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_DQSCLK_SELECT0_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_RDCLK_SELECT0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_RDCLK_SELECT0_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_DQSCLK_SELECT1 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_DQSCLK_SELECT1_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_RDCLK_SELECT1 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_RDCLK_SELECT1_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_DQSCLK_SELECT2 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_DQSCLK_SELECT2_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_RDCLK_SELECT2 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_RDCLK_SELECT2_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_DQSCLK_SELECT3 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_DQSCLK_SELECT3_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_RDCLK_SELECT3 = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_RDCLK_SELECT3_LEN = 2 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_4_DQSCLK_SELECT0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_4_DQSCLK_SELECT0_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_4_RDCLK_SELECT0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_4_RDCLK_SELECT0_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_4_DQSCLK_SELECT1 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_4_DQSCLK_SELECT1_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_4_RDCLK_SELECT1 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_4_RDCLK_SELECT1_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_4_DQSCLK_SELECT2 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_4_DQSCLK_SELECT2_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_4_RDCLK_SELECT2 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_4_RDCLK_SELECT2_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_4_DQSCLK_SELECT3 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_4_DQSCLK_SELECT3_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_4_RDCLK_SELECT3 = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_4_RDCLK_SELECT3_LEN = 2 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_DQSCLK_SELECT0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_DQSCLK_SELECT0_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_RDCLK_SELECT0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_RDCLK_SELECT0_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_DQSCLK_SELECT1 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_DQSCLK_SELECT1_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_RDCLK_SELECT1 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_RDCLK_SELECT1_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_DQSCLK_SELECT2 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_DQSCLK_SELECT2_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_RDCLK_SELECT2 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_RDCLK_SELECT2_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_DQSCLK_SELECT3 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_DQSCLK_SELECT3_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_RDCLK_SELECT3 = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_RDCLK_SELECT3_LEN = 2 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_DQSCLK_SELECT0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_DQSCLK_SELECT0_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_RDCLK_SELECT0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_RDCLK_SELECT0_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_DQSCLK_SELECT1 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_DQSCLK_SELECT1_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_RDCLK_SELECT1 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_RDCLK_SELECT1_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_DQSCLK_SELECT2 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_DQSCLK_SELECT2_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_RDCLK_SELECT2 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_RDCLK_SELECT2_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_DQSCLK_SELECT3 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_DQSCLK_SELECT3_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_RDCLK_SELECT3 = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_RDCLK_SELECT3_LEN = 2 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_DQSCLK_SELECT0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_DQSCLK_SELECT0_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_RDCLK_SELECT0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_RDCLK_SELECT0_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_DQSCLK_SELECT1 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_DQSCLK_SELECT1_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_RDCLK_SELECT1 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_RDCLK_SELECT1_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_DQSCLK_SELECT2 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_DQSCLK_SELECT2_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_RDCLK_SELECT2 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_RDCLK_SELECT2_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_DQSCLK_SELECT3 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_DQSCLK_SELECT3_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_RDCLK_SELECT3 = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_RDCLK_SELECT3_LEN = 2 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_DQSCLK_SELECT0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_DQSCLK_SELECT0_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_RDCLK_SELECT0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_RDCLK_SELECT0_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_DQSCLK_SELECT1 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_DQSCLK_SELECT1_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_RDCLK_SELECT1 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_RDCLK_SELECT1_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_DQSCLK_SELECT2 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_DQSCLK_SELECT2_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_RDCLK_SELECT2 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_RDCLK_SELECT2_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_DQSCLK_SELECT3 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_DQSCLK_SELECT3_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_RDCLK_SELECT3 = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_RDCLK_SELECT3_LEN = 2 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_4_DQSCLK_SELECT0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_4_DQSCLK_SELECT0_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_4_RDCLK_SELECT0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_4_RDCLK_SELECT0_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_4_DQSCLK_SELECT1 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_4_DQSCLK_SELECT1_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_4_RDCLK_SELECT1 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_4_RDCLK_SELECT1_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_4_DQSCLK_SELECT2 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_4_DQSCLK_SELECT2_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_4_RDCLK_SELECT2 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_4_RDCLK_SELECT2_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_4_DQSCLK_SELECT3 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_4_DQSCLK_SELECT3_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_4_RDCLK_SELECT3 = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_4_RDCLK_SELECT3_LEN = 2 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_DQSCLK_SELECT0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_DQSCLK_SELECT0_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_RDCLK_SELECT0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_RDCLK_SELECT0_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_DQSCLK_SELECT1 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_DQSCLK_SELECT1_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_RDCLK_SELECT1 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_RDCLK_SELECT1_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_DQSCLK_SELECT2 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_DQSCLK_SELECT2_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_RDCLK_SELECT2 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_RDCLK_SELECT2_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_DQSCLK_SELECT3 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_DQSCLK_SELECT3_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_RDCLK_SELECT3 = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_RDCLK_SELECT3_LEN = 2 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_DQSCLK_SELECT0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_DQSCLK_SELECT0_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_RDCLK_SELECT0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_RDCLK_SELECT0_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_DQSCLK_SELECT1 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_DQSCLK_SELECT1_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_RDCLK_SELECT1 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_RDCLK_SELECT1_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_DQSCLK_SELECT2 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_DQSCLK_SELECT2_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_RDCLK_SELECT2 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_RDCLK_SELECT2_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_DQSCLK_SELECT3 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_DQSCLK_SELECT3_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_RDCLK_SELECT3 = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_RDCLK_SELECT3_LEN = 2 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_DQSCLK_SELECT0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_DQSCLK_SELECT0_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_RDCLK_SELECT0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_RDCLK_SELECT0_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_DQSCLK_SELECT1 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_DQSCLK_SELECT1_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_RDCLK_SELECT1 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_RDCLK_SELECT1_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_DQSCLK_SELECT2 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_DQSCLK_SELECT2_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_RDCLK_SELECT2 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_RDCLK_SELECT2_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_DQSCLK_SELECT3 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_DQSCLK_SELECT3_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_RDCLK_SELECT3 = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_RDCLK_SELECT3_LEN = 2 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_DQSCLK_SELECT0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_DQSCLK_SELECT0_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_RDCLK_SELECT0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_RDCLK_SELECT0_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_DQSCLK_SELECT1 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_DQSCLK_SELECT1_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_RDCLK_SELECT1 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_RDCLK_SELECT1_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_DQSCLK_SELECT2 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_DQSCLK_SELECT2_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_RDCLK_SELECT2 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_RDCLK_SELECT2_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_DQSCLK_SELECT3 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_DQSCLK_SELECT3_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_RDCLK_SELECT3 = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_RDCLK_SELECT3_LEN = 2 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_4_DQSCLK_SELECT0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_4_DQSCLK_SELECT0_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_4_RDCLK_SELECT0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_4_RDCLK_SELECT0_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_4_DQSCLK_SELECT1 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_4_DQSCLK_SELECT1_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_4_RDCLK_SELECT1 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_4_RDCLK_SELECT1_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_4_DQSCLK_SELECT2 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_4_DQSCLK_SELECT2_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_4_RDCLK_SELECT2 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_4_RDCLK_SELECT2_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_4_DQSCLK_SELECT3 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_4_DQSCLK_SELECT3_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_4_RDCLK_SELECT3 = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_4_RDCLK_SELECT3_LEN = 2 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_DQSCLK_SELECT0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_DQSCLK_SELECT0_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_RDCLK_SELECT0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_RDCLK_SELECT0_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_DQSCLK_SELECT1 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_DQSCLK_SELECT1_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_RDCLK_SELECT1 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_RDCLK_SELECT1_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_DQSCLK_SELECT2 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_DQSCLK_SELECT2_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_RDCLK_SELECT2 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_RDCLK_SELECT2_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_DQSCLK_SELECT3 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_DQSCLK_SELECT3_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_RDCLK_SELECT3 = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_RDCLK_SELECT3_LEN = 2 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_DQSCLK_SELECT0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_DQSCLK_SELECT0_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_RDCLK_SELECT0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_RDCLK_SELECT0_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_DQSCLK_SELECT1 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_DQSCLK_SELECT1_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_RDCLK_SELECT1 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_RDCLK_SELECT1_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_DQSCLK_SELECT2 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_DQSCLK_SELECT2_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_RDCLK_SELECT2 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_RDCLK_SELECT2_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_DQSCLK_SELECT3 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_DQSCLK_SELECT3_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_RDCLK_SELECT3 = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_RDCLK_SELECT3_LEN = 2 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_DQSCLK_SELECT0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_DQSCLK_SELECT0_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_RDCLK_SELECT0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_RDCLK_SELECT0_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_DQSCLK_SELECT1 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_DQSCLK_SELECT1_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_RDCLK_SELECT1 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_RDCLK_SELECT1_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_DQSCLK_SELECT2 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_DQSCLK_SELECT2_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_RDCLK_SELECT2 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_RDCLK_SELECT2_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_DQSCLK_SELECT3 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_DQSCLK_SELECT3_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_RDCLK_SELECT3 = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_RDCLK_SELECT3_LEN = 2 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_DQSCLK_SELECT0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_DQSCLK_SELECT0_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_RDCLK_SELECT0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_RDCLK_SELECT0_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_DQSCLK_SELECT1 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_DQSCLK_SELECT1_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_RDCLK_SELECT1 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_RDCLK_SELECT1_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_DQSCLK_SELECT2 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_DQSCLK_SELECT2_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_RDCLK_SELECT2 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_RDCLK_SELECT2_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_DQSCLK_SELECT3 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_DQSCLK_SELECT3_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_RDCLK_SELECT3 = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_RDCLK_SELECT3_LEN = 2 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_4_DQSCLK_SELECT0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_4_DQSCLK_SELECT0_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_4_RDCLK_SELECT0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_4_RDCLK_SELECT0_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_4_DQSCLK_SELECT1 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_4_DQSCLK_SELECT1_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_4_RDCLK_SELECT1 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_4_RDCLK_SELECT1_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_4_DQSCLK_SELECT2 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_4_DQSCLK_SELECT2_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_4_RDCLK_SELECT2 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_4_RDCLK_SELECT2_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_4_DQSCLK_SELECT3 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_4_DQSCLK_SELECT3_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_4_RDCLK_SELECT3 = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_4_RDCLK_SELECT3_LEN = 2 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP0_P0_0_01_0_15 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP0_P0_0_01_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP0_P0_1_01_0_15 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP0_P0_1_01_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP0_P0_2_23_0_15 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP0_P0_2_23_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP0_P0_3_23_0_15 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP0_P0_3_23_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP0_P0_4_4_0_15 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP0_P0_4_4_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP1_P0_0_01_0_15 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP1_P0_0_01_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP1_P0_1_01_0_15 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP1_P0_1_01_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP1_P0_2_23_0_15 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP1_P0_2_23_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP1_P0_3_23_0_15 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP1_P0_3_23_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP1_P0_4_4_0_15 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP1_P0_4_4_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP2_P0_0_01_0_15 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP2_P0_0_01_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP2_P0_1_01_0_15 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP2_P0_1_01_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP2_P0_2_23_0_15 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP2_P0_2_23_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP2_P0_3_23_0_15 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP2_P0_3_23_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP2_P0_4_4_0_15 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP2_P0_4_4_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP3_P0_0_01_0_15 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP3_P0_0_01_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP3_P0_1_01_0_15 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP3_P0_1_01_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP3_P0_2_23_0_15 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP3_P0_2_23_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP3_P0_3_23_0_15 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP3_P0_3_23_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP3_P0_4_4_0_15 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP3_P0_4_4_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_ENABLE0_P0_0_01_DATA_ENABLE_15 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_ENABLE0_P0_0_01_DATA_ENABLE_15_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_ENABLE0_P0_1_01_DATA_ENABLE_0_15 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_ENABLE0_P0_1_01_DATA_ENABLE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_ENABLE0_P0_2_23_DATA_ENABLE_0_15 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_ENABLE0_P0_2_23_DATA_ENABLE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_ENABLE0_P0_3_23_DATA_ENABLE_0_15 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_ENABLE0_P0_3_23_DATA_ENABLE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_ENABLE0_P0_4_4_DATA_ENABLE_0_15 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_ENABLE0_P0_4_4_DATA_ENABLE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_FORCE_OUTPUTS_P0_0_01_VALUE_15 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_FORCE_OUTPUTS_P0_0_01_VALUE_15_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_FORCE_OUTPUTS_P0_1_01_VALUE_0_15 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_FORCE_OUTPUTS_P0_1_01_VALUE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_FORCE_OUTPUTS_P0_2_23_VALUE_0_15 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_FORCE_OUTPUTS_P0_2_23_VALUE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_FORCE_OUTPUTS_P0_3_23_VALUE_0_15 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_FORCE_OUTPUTS_P0_3_23_VALUE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_FORCE_OUTPUTS_P0_4_4_VALUE_0_15 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_FORCE_OUTPUTS_P0_4_4_VALUE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_0_01_N0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_0_01_N0_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_0_01_N1 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_0_01_N1_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_0_01_N2 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_0_01_N2_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_0_01_N3 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_0_01_N3_LEN = 4 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_1_01_N0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_1_01_N0_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_1_01_N1 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_1_01_N1_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_1_01_N2 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_1_01_N2_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_1_01_N3 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_1_01_N3_LEN = 4 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_2_23_N0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_2_23_N0_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_2_23_N1 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_2_23_N1_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_2_23_N2 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_2_23_N2_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_2_23_N3 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_2_23_N3_LEN = 4 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_3_23_N0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_3_23_N0_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_3_23_N1 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_3_23_N1_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_3_23_N2 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_3_23_N2_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_3_23_N3 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_3_23_N3_LEN = 4 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_4_4_N0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_4_4_N0_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_4_4_N1 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_4_4_N1_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_4_4_N2 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_4_4_N2_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_4_4_N3 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_4_4_N3_LEN = 4 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_0_01_N0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_0_01_N0_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_0_01_N1 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_0_01_N1_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_0_01_N2 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_0_01_N2_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_0_01_N3 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_0_01_N3_LEN = 4 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_1_01_N0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_1_01_N0_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_1_01_N1 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_1_01_N1_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_1_01_N2 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_1_01_N2_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_1_01_N3 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_1_01_N3_LEN = 4 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_2_23_N0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_2_23_N0_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_2_23_N1 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_2_23_N1_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_2_23_N2 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_2_23_N2_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_2_23_N3 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_2_23_N3_LEN = 4 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_3_23_N0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_3_23_N0_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_3_23_N1 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_3_23_N1_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_3_23_N2 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_3_23_N2_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_3_23_N3 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_3_23_N3_LEN = 4 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_4_4_N0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_4_4_N0_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_4_4_N1 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_4_4_N1_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_4_4_N2 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_4_4_N2_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_4_4_N3 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_4_4_N3_LEN = 4 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_0_01_N0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_0_01_N0_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_0_01_N1 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_0_01_N1_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_0_01_N2 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_0_01_N2_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_0_01_N3 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_0_01_N3_LEN = 4 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_1_01_N0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_1_01_N0_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_1_01_N1 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_1_01_N1_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_1_01_N2 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_1_01_N2_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_1_01_N3 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_1_01_N3_LEN = 4 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_2_23_N0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_2_23_N0_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_2_23_N1 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_2_23_N1_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_2_23_N2 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_2_23_N2_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_2_23_N3 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_2_23_N3_LEN = 4 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_3_23_N0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_3_23_N0_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_3_23_N1 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_3_23_N1_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_3_23_N2 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_3_23_N2_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_3_23_N3 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_3_23_N3_LEN = 4 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_4_4_N0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_4_4_N0_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_4_4_N1 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_4_4_N1_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_4_4_N2 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_4_4_N2_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_4_4_N3 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_4_4_N3_LEN = 4 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_0_01_N0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_0_01_N0_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_0_01_N1 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_0_01_N1_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_0_01_N2 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_0_01_N2_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_0_01_N3 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_0_01_N3_LEN = 4 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_1_01_N0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_1_01_N0_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_1_01_N1 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_1_01_N1_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_1_01_N2 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_1_01_N2_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_1_01_N3 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_1_01_N3_LEN = 4 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_2_23_N0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_2_23_N0_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_2_23_N1 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_2_23_N1_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_2_23_N2 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_2_23_N2_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_2_23_N3 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_2_23_N3_LEN = 4 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_3_23_N0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_3_23_N0_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_3_23_N1 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_3_23_N1_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_3_23_N2 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_3_23_N2_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_3_23_N3 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_3_23_N3_LEN = 4 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_4_4_N0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_4_4_N0_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_4_4_N1 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_4_4_N1_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_4_4_N2 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_4_4_N2_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_4_4_N3 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_4_4_N3_LEN = 4 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_0_01_DD2_BLUE_EXTEND_RANGE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_0_01_DD2_BLUE_EXTEND_RANGE_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_0_01_MIN_RD_EYE_SIZE = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_0_01_MIN_RD_EYE_SIZE_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_0_01_DD2_SPARE_L2SFF_CG_DISABLE = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_0_01_DD2_PERRDCTR_FIX_DISABLE = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_0_01_MAX_DQS = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_0_01_MAX_DQS_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_1_01_DD2_BLUE_EXTEND_RANGE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_1_01_DD2_BLUE_EXTEND_RANGE_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_1_01_MIN_RD_EYE_SIZE = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_1_01_MIN_RD_EYE_SIZE_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_1_01_DD2_SPARE_L2SFF_CG_DISABLE = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_1_01_DD2_PERRDCTR_FIX_DISABLE = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_1_01_MAX_DQS = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_1_01_MAX_DQS_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_2_23_DD2_BLUE_EXTEND_RANGE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_2_23_DD2_BLUE_EXTEND_RANGE_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_2_23_MIN_RD_EYE_SIZE = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_2_23_MIN_RD_EYE_SIZE_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_2_23_DD2_SPARE_L2SFF_CG_DISABLE = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_2_23_DD2_PERRDCTR_FIX_DISABLE = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_2_23_MAX_DQS = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_2_23_MAX_DQS_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_3_23_DD2_BLUE_EXTEND_RANGE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_3_23_DD2_BLUE_EXTEND_RANGE_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_3_23_MIN_RD_EYE_SIZE = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_3_23_MIN_RD_EYE_SIZE_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_3_23_DD2_SPARE_L2SFF_CG_DISABLE = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_3_23_DD2_PERRDCTR_FIX_DISABLE = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_3_23_MAX_DQS = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_3_23_MAX_DQS_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_4_4_DD2_BLUE_EXTEND_RANGE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_4_4_DD2_BLUE_EXTEND_RANGE_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_4_4_MIN_RD_EYE_SIZE = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_4_4_MIN_RD_EYE_SIZE_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_4_4_DD2_SPARE_L2SFF_CG_DISABLE = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_4_4_DD2_PERRDCTR_FIX_DISABLE = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_4_4_MAX_DQS = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_4_4_MAX_DQS_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_0_01_ROT_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_0_01_ROT_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_0_01_ROT_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_0_01_ROT_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_1_01_ROT_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_1_01_ROT_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_1_01_ROT_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_1_01_ROT_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_2_23_ROT_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_2_23_ROT_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_2_23_ROT_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_2_23_ROT_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_3_23_ROT_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_3_23_ROT_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_3_23_ROT_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_3_23_ROT_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_4_4_ROT_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_4_4_ROT_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_4_4_ROT_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_4_4_ROT_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_0_01_ROT_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_0_01_ROT_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_0_01_ROT_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_0_01_ROT_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_1_01_ROT_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_1_01_ROT_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_1_01_ROT_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_1_01_ROT_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_2_23_ROT_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_2_23_ROT_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_2_23_ROT_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_2_23_ROT_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_3_23_ROT_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_3_23_ROT_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_3_23_ROT_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_3_23_ROT_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_4_4_ROT_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_4_4_ROT_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_4_4_ROT_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_4_4_ROT_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_0_01_ROT_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_0_01_ROT_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_0_01_ROT_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_0_01_ROT_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_1_01_ROT_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_1_01_ROT_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_1_01_ROT_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_1_01_ROT_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_2_23_ROT_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_2_23_ROT_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_2_23_ROT_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_2_23_ROT_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_3_23_ROT_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_3_23_ROT_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_3_23_ROT_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_3_23_ROT_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_4_4_ROT_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_4_4_ROT_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_4_4_ROT_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_4_4_ROT_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_0_01_ROT_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_0_01_ROT_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_0_01_ROT_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_0_01_ROT_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_1_01_ROT_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_1_01_ROT_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_1_01_ROT_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_1_01_ROT_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_2_23_ROT_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_2_23_ROT_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_2_23_ROT_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_2_23_ROT_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_3_23_ROT_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_3_23_ROT_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_3_23_ROT_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_3_23_ROT_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_4_4_ROT_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_4_4_ROT_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_4_4_ROT_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_4_4_ROT_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_0_01_ROT_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_0_01_ROT_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_0_01_ROT_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_0_01_ROT_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_1_01_ROT_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_1_01_ROT_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_1_01_ROT_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_1_01_ROT_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_2_23_ROT_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_2_23_ROT_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_2_23_ROT_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_2_23_ROT_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_3_23_ROT_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_3_23_ROT_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_3_23_ROT_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_3_23_ROT_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_4_4_ROT_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_4_4_ROT_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_4_4_ROT_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_4_4_ROT_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_0_01_ROT_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_0_01_ROT_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_0_01_ROT_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_0_01_ROT_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_1_01_ROT_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_1_01_ROT_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_1_01_ROT_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_1_01_ROT_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_2_23_ROT_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_2_23_ROT_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_2_23_ROT_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_2_23_ROT_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_3_23_ROT_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_3_23_ROT_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_3_23_ROT_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_3_23_ROT_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_4_4_ROT_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_4_4_ROT_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_4_4_ROT_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_4_4_ROT_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_0_01_ROT_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_0_01_ROT_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_0_01_ROT_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_0_01_ROT_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_1_01_ROT_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_1_01_ROT_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_1_01_ROT_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_1_01_ROT_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_2_23_ROT_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_2_23_ROT_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_2_23_ROT_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_2_23_ROT_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_3_23_ROT_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_3_23_ROT_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_3_23_ROT_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_3_23_ROT_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_4_4_ROT_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_4_4_ROT_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_4_4_ROT_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_4_4_ROT_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_0_01_ROT_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_0_01_ROT_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_0_01_ROT_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_0_01_ROT_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_1_01_ROT_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_1_01_ROT_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_1_01_ROT_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_1_01_ROT_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_2_23_ROT_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_2_23_ROT_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_2_23_ROT_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_2_23_ROT_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_3_23_ROT_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_3_23_ROT_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_3_23_ROT_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_3_23_ROT_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_4_4_ROT_N0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_4_4_ROT_N0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_4_4_ROT_N1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_4_4_ROT_N1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_0_01_STRENGTH = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_0_01_STRENGTH_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_0_01_DD2_RESET_READ_FIX_DISABLE = 52 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_1_01_STRENGTH = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_1_01_STRENGTH_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_1_01_DD2_RESET_READ_FIX_DISABLE = 52 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_2_23_STRENGTH = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_2_23_STRENGTH_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_2_23_DD2_RESET_READ_FIX_DISABLE = 52 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_3_23_STRENGTH = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_3_23_STRENGTH_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_3_23_DD2_RESET_READ_FIX_DISABLE = 52 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_4_4_STRENGTH = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_4_4_STRENGTH_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_4_4_DD2_RESET_READ_FIX_DISABLE = 52 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_0_01_EN_N_WR = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_0_01_EN_N_WR_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_0_01_EN_P_WR = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_0_01_EN_P_WR_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_1_01_EN_N_WR = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_1_01_EN_N_WR_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_1_01_EN_P_WR = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_1_01_EN_P_WR_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_2_23_EN_N_WR = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_2_23_EN_N_WR_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_2_23_EN_P_WR = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_2_23_EN_P_WR_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_3_23_EN_N_WR = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_3_23_EN_N_WR_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_3_23_EN_P_WR = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_3_23_EN_P_WR_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_4_4_EN_N_WR = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_4_4_EN_N_WR_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_4_4_EN_P_WR = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_4_4_EN_P_WR_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_0_01_EN_P_WR = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_0_01_EN_P_WR_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_1_01_EN_P_WR = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_1_01_EN_P_WR_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_2_23_EN_P_WR = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_2_23_EN_P_WR_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_3_23_EN_P_WR = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_3_23_EN_P_WR_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_4_4_EN_P_WR = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_4_4_EN_P_WR_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_0_01_SEL_A = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_0_01_SEL_A_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_0_01_SEL_B = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_0_01_SEL_B_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_1_01_SEL_A = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_1_01_SEL_A_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_1_01_SEL_B = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_1_01_SEL_B_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_2_23_SEL_A = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_2_23_SEL_A_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_2_23_SEL_B = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_2_23_SEL_B_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_3_23_SEL_A = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_3_23_SEL_A_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_3_23_SEL_B = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_3_23_SEL_B_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_4_4_SEL_A = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_4_4_SEL_A_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_4_4_SEL_B = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_4_4_SEL_B_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_0_01_MEMINTD00 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_0_01_MEMINTD00_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_0_01_MEMINTD01 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_0_01_MEMINTD01_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_0_01_MEMINTD02 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_0_01_MEMINTD02_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_0_01_MEMINTD03 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_0_01_MEMINTD03_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_0_01_MEMINTD04 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_0_01_MEMINTD04_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_0_01_MEMINTD05 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_0_01_MEMINTD05_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_0_01_MEMINTD06 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_0_01_MEMINTD06_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_0_01_MEMINTD07 = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_0_01_MEMINTD07_LEN = 2 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_1_01_MEMINTD00 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_1_01_MEMINTD00_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_1_01_MEMINTD01 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_1_01_MEMINTD01_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_1_01_MEMINTD02 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_1_01_MEMINTD02_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_1_01_MEMINTD03 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_1_01_MEMINTD03_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_1_01_MEMINTD04 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_1_01_MEMINTD04_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_1_01_MEMINTD05 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_1_01_MEMINTD05_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_1_01_MEMINTD06 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_1_01_MEMINTD06_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_1_01_MEMINTD07 = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_1_01_MEMINTD07_LEN = 2 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_2_23_MEMINTD00 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_2_23_MEMINTD00_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_2_23_MEMINTD01 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_2_23_MEMINTD01_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_2_23_MEMINTD02 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_2_23_MEMINTD02_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_2_23_MEMINTD03 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_2_23_MEMINTD03_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_2_23_MEMINTD04 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_2_23_MEMINTD04_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_2_23_MEMINTD05 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_2_23_MEMINTD05_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_2_23_MEMINTD06 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_2_23_MEMINTD06_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_2_23_MEMINTD07 = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_2_23_MEMINTD07_LEN = 2 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_3_23_MEMINTD00 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_3_23_MEMINTD00_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_3_23_MEMINTD01 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_3_23_MEMINTD01_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_3_23_MEMINTD02 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_3_23_MEMINTD02_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_3_23_MEMINTD03 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_3_23_MEMINTD03_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_3_23_MEMINTD04 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_3_23_MEMINTD04_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_3_23_MEMINTD05 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_3_23_MEMINTD05_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_3_23_MEMINTD06 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_3_23_MEMINTD06_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_3_23_MEMINTD07 = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_3_23_MEMINTD07_LEN = 2 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_4_4_MEMINTD00 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_4_4_MEMINTD00_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_4_4_MEMINTD01 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_4_4_MEMINTD01_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_4_4_MEMINTD02 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_4_4_MEMINTD02_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_4_4_MEMINTD03 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_4_4_MEMINTD03_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_4_4_MEMINTD04 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_4_4_MEMINTD04_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_4_4_MEMINTD05 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_4_4_MEMINTD05_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_4_4_MEMINTD06 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_4_4_MEMINTD06_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_4_4_MEMINTD07 = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_4_4_MEMINTD07_LEN = 2 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_0_01_MEMINTD08 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_0_01_MEMINTD08_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_0_01_MEMINTD09 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_0_01_MEMINTD09_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_0_01_MEMINTD10 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_0_01_MEMINTD10_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_0_01_MEMINTD11 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_0_01_MEMINTD11_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_0_01_MEMINTD12 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_0_01_MEMINTD12_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_0_01_MEMINTD13 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_0_01_MEMINTD13_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_0_01_MEMINTD14 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_0_01_MEMINTD14_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_0_01_MEMINTD15 = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_0_01_MEMINTD15_LEN = 2 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_1_01_MEMINTD08 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_1_01_MEMINTD08_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_1_01_MEMINTD09 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_1_01_MEMINTD09_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_1_01_MEMINTD10 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_1_01_MEMINTD10_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_1_01_MEMINTD11 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_1_01_MEMINTD11_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_1_01_MEMINTD12 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_1_01_MEMINTD12_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_1_01_MEMINTD13 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_1_01_MEMINTD13_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_1_01_MEMINTD14 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_1_01_MEMINTD14_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_1_01_MEMINTD15 = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_1_01_MEMINTD15_LEN = 2 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_2_23_MEMINTD08 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_2_23_MEMINTD08_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_2_23_MEMINTD09 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_2_23_MEMINTD09_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_2_23_MEMINTD10 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_2_23_MEMINTD10_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_2_23_MEMINTD11 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_2_23_MEMINTD11_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_2_23_MEMINTD12 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_2_23_MEMINTD12_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_2_23_MEMINTD13 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_2_23_MEMINTD13_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_2_23_MEMINTD14 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_2_23_MEMINTD14_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_2_23_MEMINTD15 = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_2_23_MEMINTD15_LEN = 2 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_3_23_MEMINTD08 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_3_23_MEMINTD08_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_3_23_MEMINTD09 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_3_23_MEMINTD09_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_3_23_MEMINTD10 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_3_23_MEMINTD10_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_3_23_MEMINTD11 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_3_23_MEMINTD11_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_3_23_MEMINTD12 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_3_23_MEMINTD12_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_3_23_MEMINTD13 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_3_23_MEMINTD13_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_3_23_MEMINTD14 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_3_23_MEMINTD14_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_3_23_MEMINTD15 = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_3_23_MEMINTD15_LEN = 2 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_4_4_MEMINTD08 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_4_4_MEMINTD08_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_4_4_MEMINTD09 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_4_4_MEMINTD09_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_4_4_MEMINTD10 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_4_4_MEMINTD10_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_4_4_MEMINTD11 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_4_4_MEMINTD11_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_4_4_MEMINTD12 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_4_4_MEMINTD12_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_4_4_MEMINTD13 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_4_4_MEMINTD13_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_4_4_MEMINTD14 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_4_4_MEMINTD14_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_4_4_MEMINTD15 = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_4_4_MEMINTD15_LEN = 2 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_0_01_SYSCLK_DQSCLK_OFFSET = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_0_01_SYSCLK_DQSCLK_OFFSET_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_0_01_SYSCLK_RDCLK_OFFSET = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_0_01_SYSCLK_RDCLK_OFFSET_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_1_01_SYSCLK_DQSCLK_OFFSET = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_1_01_SYSCLK_DQSCLK_OFFSET_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_1_01_SYSCLK_RDCLK_OFFSET = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_1_01_SYSCLK_RDCLK_OFFSET_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_2_23_SYSCLK_DQSCLK_OFFSET = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_2_23_SYSCLK_DQSCLK_OFFSET_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_2_23_SYSCLK_RDCLK_OFFSET = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_2_23_SYSCLK_RDCLK_OFFSET_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_3_23_SYSCLK_DQSCLK_OFFSET = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_3_23_SYSCLK_DQSCLK_OFFSET_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_3_23_SYSCLK_RDCLK_OFFSET = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_3_23_SYSCLK_RDCLK_OFFSET_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_4_4_SYSCLK_DQSCLK_OFFSET = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_4_4_SYSCLK_DQSCLK_OFFSET_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_4_4_SYSCLK_RDCLK_OFFSET = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_4_4_SYSCLK_RDCLK_OFFSET_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_0_01_DQS_ALIGN_SM = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_0_01_DQS_ALIGN_SM_LEN = 5 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_0_01_DQS_ALIGN_CNTR = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_0_01_DQS_ALIGN_CNTR_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_0_01_ITERATION_CNTR = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_0_01_ITERATION_CNTR_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_1_01_DQS_ALIGN_SM = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_1_01_DQS_ALIGN_SM_LEN = 5 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_1_01_DQS_ALIGN_CNTR = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_1_01_DQS_ALIGN_CNTR_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_1_01_ITERATION_CNTR = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_1_01_ITERATION_CNTR_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_2_23_DQS_ALIGN_SM = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_2_23_DQS_ALIGN_SM_LEN = 5 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_2_23_DQS_ALIGN_CNTR = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_2_23_DQS_ALIGN_CNTR_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_2_23_ITERATION_CNTR = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_2_23_ITERATION_CNTR_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_3_23_DQS_ALIGN_SM = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_3_23_DQS_ALIGN_SM_LEN = 5 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_3_23_DQS_ALIGN_CNTR = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_3_23_DQS_ALIGN_CNTR_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_3_23_ITERATION_CNTR = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_3_23_ITERATION_CNTR_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_4_4_DQS_ALIGN_SM = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_4_4_DQS_ALIGN_SM_LEN = 5 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_4_4_DQS_ALIGN_CNTR = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_4_4_DQS_ALIGN_CNTR_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_4_4_ITERATION_CNTR = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_4_4_ITERATION_CNTR_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_0_01_CALIBRATE_BIT = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_0_01_CALIBRATE_BIT_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_0_01_DQS_ALIGN_QUAD = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_0_01_DQS_ALIGN_QUAD_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_0_01_DQS_QUAD_CONFIG = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_0_01_DQS_QUAD_CONFIG_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_0_01_OPERATE_MODE = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_0_01_OPERATE_MODE_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_0_01_EN_DQS_OFFSET = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_0_01_DQS_ALIGN_JITTER = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_0_01_DIS_CLK_GATE = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_0_01_MAX_DQS_ITER = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_1_01_CALIBRATE_BIT = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_1_01_CALIBRATE_BIT_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_1_01_DQS_ALIGN_QUAD = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_1_01_DQS_ALIGN_QUAD_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_1_01_DQS_QUAD_CONFIG = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_1_01_DQS_QUAD_CONFIG_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_1_01_OPERATE_MODE = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_1_01_OPERATE_MODE_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_1_01_EN_DQS_OFFSET = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_1_01_DQS_ALIGN_JITTER = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_1_01_DIS_CLK_GATE = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_1_01_MAX_DQS_ITER = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_2_23_CALIBRATE_BIT = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_2_23_CALIBRATE_BIT_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_2_23_DQS_ALIGN_QUAD = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_2_23_DQS_ALIGN_QUAD_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_2_23_DQS_QUAD_CONFIG = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_2_23_DQS_QUAD_CONFIG_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_2_23_OPERATE_MODE = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_2_23_OPERATE_MODE_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_2_23_EN_DQS_OFFSET = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_2_23_DQS_ALIGN_JITTER = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_2_23_DIS_CLK_GATE = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_2_23_MAX_DQS_ITER = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_3_23_CALIBRATE_BIT = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_3_23_CALIBRATE_BIT_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_3_23_DQS_ALIGN_QUAD = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_3_23_DQS_ALIGN_QUAD_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_3_23_DQS_QUAD_CONFIG = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_3_23_DQS_QUAD_CONFIG_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_3_23_OPERATE_MODE = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_3_23_OPERATE_MODE_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_3_23_EN_DQS_OFFSET = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_3_23_DQS_ALIGN_JITTER = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_3_23_DIS_CLK_GATE = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_3_23_MAX_DQS_ITER = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_4_4_CALIBRATE_BIT = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_4_4_CALIBRATE_BIT_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_4_4_DQS_ALIGN_QUAD = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_4_4_DQS_ALIGN_QUAD_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_4_4_DQS_QUAD_CONFIG = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_4_4_DQS_QUAD_CONFIG_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_4_4_OPERATE_MODE = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_4_4_OPERATE_MODE_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_4_4_EN_DQS_OFFSET = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_4_4_DQS_ALIGN_JITTER = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_4_4_DIS_CLK_GATE = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_4_4_MAX_DQS_ITER = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_0_01_DESIRED_EDGE_CNTR_TARGET_HIGH = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_0_01_DESIRED_EDGE_CNTR_TARGET_HIGH_LEN = 8 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_0_01_DESIRED_EDGE_CNTR_TARGET_LOW = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_0_01_DESIRED_EDGE_CNTR_TARGET_LOW_LEN = 8 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_1_01_DESIRED_EDGE_CNTR_TARGET_HIGH = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_1_01_DESIRED_EDGE_CNTR_TARGET_HIGH_LEN = 8 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_1_01_DESIRED_EDGE_CNTR_TARGET_LOW = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_1_01_DESIRED_EDGE_CNTR_TARGET_LOW_LEN = 8 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_2_23_DESIRED_EDGE_CNTR_TARGET_HIGH = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_2_23_DESIRED_EDGE_CNTR_TARGET_HIGH_LEN = 8 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_2_23_DESIRED_EDGE_CNTR_TARGET_LOW = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_2_23_DESIRED_EDGE_CNTR_TARGET_LOW_LEN = 8 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_3_23_DESIRED_EDGE_CNTR_TARGET_HIGH = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_3_23_DESIRED_EDGE_CNTR_TARGET_HIGH_LEN = 8 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_3_23_DESIRED_EDGE_CNTR_TARGET_LOW = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_3_23_DESIRED_EDGE_CNTR_TARGET_LOW_LEN = 8 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_4_4_DESIRED_EDGE_CNTR_TARGET_HIGH = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_4_4_DESIRED_EDGE_CNTR_TARGET_HIGH_LEN = 8 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_4_4_DESIRED_EDGE_CNTR_TARGET_LOW = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_4_4_DESIRED_EDGE_CNTR_TARGET_LOW_LEN = 8 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG4_P0_0_01_DQS_ALIGN_FIX_DIS = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG4_P0_0_01_CDD2_FIFO_FIX_DIS = 49 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG4_P0_1_01_DQS_ALIGN_FIX_DIS = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG4_P0_1_01_CDD2_FIFO_FIX_DIS = 49 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG4_P0_2_23_DQS_ALIGN_FIX_DIS = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG4_P0_2_23_CDD2_FIFO_FIX_DIS = 49 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG4_P0_3_23_DQS_ALIGN_FIX_DIS = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG4_P0_3_23_CDD2_FIFO_FIX_DIS = 49 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG4_P0_4_4_DQS_ALIGN_FIX_DIS = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG4_P0_4_4_CDD2_FIFO_FIX_DIS = 49 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_0_01_DYN_POWER_CNTL_EN = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_0_01_DYN_MCTERM_CNTL_EN = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_0_01_DYN_RX_GATE_CNTL_EN = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_0_01_CALGATE_ON = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_0_01_PER_CAL_UPDATE_DISABLE = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_0_01_DQS_PIPE_FIX_DIS = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_0_01_DQS_PIPE_FIX_DIS_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_0_01_CDD2_DQS_FIX_DIS = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_0_01_DL_FORCE_ON = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_0_01_BLFIFO_DIS = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_0_01_WTRFL_AVE_DIS = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_0_01_PERCAL_PWR_DIS = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_0_01_LOOPBACK_FIX_EN = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_0_01_LOOPBACK_DLY12 = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_0_01_CDD2_WTRFL_SYNC_DIS = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_0_01_FORCE_FIFO_CAPTURE = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_1_01_DYN_POWER_CNTL_EN = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_1_01_DYN_MCTERM_CNTL_EN = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_1_01_DYN_RX_GATE_CNTL_EN = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_1_01_CALGATE_ON = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_1_01_PER_CAL_UPDATE_DISABLE = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_1_01_DQS_PIPE_FIX_DIS = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_1_01_DQS_PIPE_FIX_DIS_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_1_01_CDD2_DQS_FIX_DIS = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_1_01_DL_FORCE_ON = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_1_01_BLFIFO_DIS = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_1_01_WTRFL_AVE_DIS = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_1_01_PERCAL_PWR_DIS = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_1_01_LOOPBACK_FIX_EN = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_1_01_LOOPBACK_DLY12 = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_1_01_CDD2_WTRFL_SYNC_DIS = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_1_01_FORCE_FIFO_CAPTURE = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_2_23_DYN_POWER_CNTL_EN = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_2_23_DYN_MCTERM_CNTL_EN = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_2_23_DYN_RX_GATE_CNTL_EN = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_2_23_CALGATE_ON = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_2_23_PER_CAL_UPDATE_DISABLE = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_2_23_DQS_PIPE_FIX_DIS = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_2_23_DQS_PIPE_FIX_DIS_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_2_23_CDD2_DQS_FIX_DIS = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_2_23_DL_FORCE_ON = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_2_23_BLFIFO_DIS = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_2_23_WTRFL_AVE_DIS = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_2_23_PERCAL_PWR_DIS = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_2_23_LOOPBACK_FIX_EN = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_2_23_LOOPBACK_DLY12 = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_2_23_CDD2_WTRFL_SYNC_DIS = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_2_23_FORCE_FIFO_CAPTURE = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_3_23_DYN_POWER_CNTL_EN = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_3_23_DYN_MCTERM_CNTL_EN = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_3_23_DYN_RX_GATE_CNTL_EN = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_3_23_CALGATE_ON = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_3_23_PER_CAL_UPDATE_DISABLE = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_3_23_DQS_PIPE_FIX_DIS = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_3_23_DQS_PIPE_FIX_DIS_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_3_23_CDD2_DQS_FIX_DIS = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_3_23_DL_FORCE_ON = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_3_23_BLFIFO_DIS = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_3_23_WTRFL_AVE_DIS = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_3_23_PERCAL_PWR_DIS = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_3_23_LOOPBACK_FIX_EN = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_3_23_LOOPBACK_DLY12 = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_3_23_CDD2_WTRFL_SYNC_DIS = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_3_23_FORCE_FIFO_CAPTURE = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_4_4_DYN_POWER_CNTL_EN = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_4_4_DYN_MCTERM_CNTL_EN = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_4_4_DYN_RX_GATE_CNTL_EN = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_4_4_CALGATE_ON = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_4_4_PER_CAL_UPDATE_DISABLE = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_4_4_DQS_PIPE_FIX_DIS = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_4_4_DQS_PIPE_FIX_DIS_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_4_4_CDD2_DQS_FIX_DIS = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_4_4_DL_FORCE_ON = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_4_4_BLFIFO_DIS = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_4_4_WTRFL_AVE_DIS = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_4_4_PERCAL_PWR_DIS = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_4_4_LOOPBACK_FIX_EN = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_4_4_LOOPBACK_DLY12 = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_4_4_CDD2_WTRFL_SYNC_DIS = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_4_4_FORCE_FIFO_CAPTURE = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_0_01_NO_EYE_DETECTED_MASK = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_0_01_LEADING_EDGE_FOUND_MASK = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_0_01_TRAILING_EDGE_FOUND_MASK = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_0_01_INCOMPLETE_CAL_N0_MASK = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_0_01_INCOMPLETE_CAL_N1_MASK = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_0_01_INCOMPLETE_CAL_N2_MASK = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_0_01_INCOMPLETE_CAL_N3_MASK = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_0_01_COARSE_PATTERN_ERR_N0_MASK = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_0_01_COARSE_PATTERN_ERR_N1_MASK = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_0_01_COARSE_PATTERN_ERR_N2_MASK = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_0_01_COARSE_PATTERN_ERR_N3_MASK = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_0_01_EYE_CLIPPING_MASK = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_0_01_NO_DQS_MASK = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_0_01_NO_LOCK_MASK = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_0_01_DRIFT_MASK = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_0_01_MIN_EYE_MASK = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_1_01_NO_EYE_DETECTED_MASK = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_1_01_LEADING_EDGE_FOUND_MASK = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_1_01_TRAILING_EDGE_FOUND_MASK = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_1_01_INCOMPLETE_CAL_N0_MASK = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_1_01_INCOMPLETE_CAL_N1_MASK = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_1_01_INCOMPLETE_CAL_N2_MASK = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_1_01_INCOMPLETE_CAL_N3_MASK = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_1_01_COARSE_PATTERN_ERR_N0_MASK = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_1_01_COARSE_PATTERN_ERR_N1_MASK = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_1_01_COARSE_PATTERN_ERR_N2_MASK = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_1_01_COARSE_PATTERN_ERR_N3_MASK = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_1_01_EYE_CLIPPING_MASK = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_1_01_NO_DQS_MASK = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_1_01_NO_LOCK_MASK = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_1_01_DRIFT_MASK = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_1_01_MIN_EYE_MASK = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_2_23_NO_EYE_DETECTED_MASK = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_2_23_LEADING_EDGE_FOUND_MASK = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_2_23_TRAILING_EDGE_FOUND_MASK = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_2_23_INCOMPLETE_CAL_N0_MASK = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_2_23_INCOMPLETE_CAL_N1_MASK = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_2_23_INCOMPLETE_CAL_N2_MASK = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_2_23_INCOMPLETE_CAL_N3_MASK = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_2_23_COARSE_PATTERN_ERR_N0_MASK = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_2_23_COARSE_PATTERN_ERR_N1_MASK = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_2_23_COARSE_PATTERN_ERR_N2_MASK = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_2_23_COARSE_PATTERN_ERR_N3_MASK = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_2_23_EYE_CLIPPING_MASK = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_2_23_NO_DQS_MASK = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_2_23_NO_LOCK_MASK = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_2_23_DRIFT_MASK = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_2_23_MIN_EYE_MASK = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_3_23_NO_EYE_DETECTED_MASK = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_3_23_LEADING_EDGE_FOUND_MASK = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_3_23_TRAILING_EDGE_FOUND_MASK = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_3_23_INCOMPLETE_CAL_N0_MASK = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_3_23_INCOMPLETE_CAL_N1_MASK = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_3_23_INCOMPLETE_CAL_N2_MASK = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_3_23_INCOMPLETE_CAL_N3_MASK = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_3_23_COARSE_PATTERN_ERR_N0_MASK = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_3_23_COARSE_PATTERN_ERR_N1_MASK = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_3_23_COARSE_PATTERN_ERR_N2_MASK = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_3_23_COARSE_PATTERN_ERR_N3_MASK = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_3_23_EYE_CLIPPING_MASK = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_3_23_NO_DQS_MASK = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_3_23_NO_LOCK_MASK = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_3_23_DRIFT_MASK = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_3_23_MIN_EYE_MASK = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_4_4_NO_EYE_DETECTED_MASK = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_4_4_LEADING_EDGE_FOUND_MASK = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_4_4_TRAILING_EDGE_FOUND_MASK = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_4_4_INCOMPLETE_CAL_N0_MASK = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_4_4_INCOMPLETE_CAL_N1_MASK = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_4_4_INCOMPLETE_CAL_N2_MASK = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_4_4_INCOMPLETE_CAL_N3_MASK = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_4_4_COARSE_PATTERN_ERR_N0_MASK = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_4_4_COARSE_PATTERN_ERR_N1_MASK = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_4_4_COARSE_PATTERN_ERR_N2_MASK = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_4_4_COARSE_PATTERN_ERR_N3_MASK = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_4_4_EYE_CLIPPING_MASK = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_4_4_NO_DQS_MASK = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_4_4_NO_LOCK_MASK = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_4_4_DRIFT_MASK = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_4_4_MIN_EYE_MASK = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_LVL_STATUS0_P0_0_01_LEADING_EDGE_NOT_FOUND_15 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_LVL_STATUS0_P0_0_01_LEADING_EDGE_NOT_FOUND_15_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_LVL_STATUS0_P0_1_01_LEADING_EDGE_NOT_FOUND_0_15 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_LVL_STATUS0_P0_1_01_LEADING_EDGE_NOT_FOUND_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_LVL_STATUS0_P0_2_23_LEADING_EDGE_NOT_FOUND_0_15 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_LVL_STATUS0_P0_2_23_LEADING_EDGE_NOT_FOUND_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_LVL_STATUS0_P0_3_23_LEADING_EDGE_NOT_FOUND_0_15 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_LVL_STATUS0_P0_3_23_LEADING_EDGE_NOT_FOUND_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_LVL_STATUS0_P0_4_4_LEADING_EDGE_NOT_FOUND_0_15 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_LVL_STATUS0_P0_4_4_LEADING_EDGE_NOT_FOUND_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_LVL_STATUS2_P0_0_01_TRAILING_EDGE_NOT_FOUND_15 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_LVL_STATUS2_P0_0_01_TRAILING_EDGE_NOT_FOUND_15_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_LVL_STATUS2_P0_1_01_TRAILING_EDGE_NOT_FOUND_0_15 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_LVL_STATUS2_P0_1_01_TRAILING_EDGE_NOT_FOUND_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_LVL_STATUS2_P0_2_23_TRAILING_EDGE_NOT_FOUND_0_15 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_LVL_STATUS2_P0_2_23_TRAILING_EDGE_NOT_FOUND_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_LVL_STATUS2_P0_3_23_TRAILING_EDGE_NOT_FOUND_0_15 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_LVL_STATUS2_P0_3_23_TRAILING_EDGE_NOT_FOUND_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_LVL_STATUS2_P0_4_4_TRAILING_EDGE_NOT_FOUND_0_15 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_LVL_STATUS2_P0_4_4_TRAILING_EDGE_NOT_FOUND_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_0_01_NO_EYE_DETECTED = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_0_01_LEADING_EDGE_NOT_FOUND = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_0_01_TRAILING_EDGE_NOT_FOUND = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_0_01_INCOMPLETE_CAL_N0 = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_0_01_INCOMPLETE_CAL_N1 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_0_01_INCOMPLETE_CAL_N2 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_0_01_INCOMPLETE_CAL_N3 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_0_01_COARSE_PATTERN_ERR_N0 = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_0_01_COARSE_PATTERN_ERR_N1 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_0_01_COARSE_PATTERN_ERR_N2 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_0_01_COARSE_PATTERN_ERR_N3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_0_01_EYE_CLIPPING = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_0_01_NO_DQS = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_0_01_NO_LOCK = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_0_01_DRIFT_ERROR = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_0_01_MIN_EYE = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_1_01_NO_EYE_DETECTED = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_1_01_LEADING_EDGE_NOT_FOUND = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_1_01_TRAILING_EDGE_NOT_FOUND = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_1_01_INCOMPLETE_CAL_N0 = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_1_01_INCOMPLETE_CAL_N1 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_1_01_INCOMPLETE_CAL_N2 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_1_01_INCOMPLETE_CAL_N3 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_1_01_COARSE_PATTERN_ERR_N0 = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_1_01_COARSE_PATTERN_ERR_N1 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_1_01_COARSE_PATTERN_ERR_N2 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_1_01_COARSE_PATTERN_ERR_N3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_1_01_EYE_CLIPPING = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_1_01_NO_DQS = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_1_01_NO_LOCK = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_1_01_DRIFT_ERROR = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_1_01_MIN_EYE = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_2_23_NO_EYE_DETECTED = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_2_23_LEADING_EDGE_NOT_FOUND = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_2_23_TRAILING_EDGE_NOT_FOUND = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_2_23_INCOMPLETE_CAL_N0 = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_2_23_INCOMPLETE_CAL_N1 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_2_23_INCOMPLETE_CAL_N2 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_2_23_INCOMPLETE_CAL_N3 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_2_23_COARSE_PATTERN_ERR_N0 = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_2_23_COARSE_PATTERN_ERR_N1 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_2_23_COARSE_PATTERN_ERR_N2 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_2_23_COARSE_PATTERN_ERR_N3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_2_23_EYE_CLIPPING = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_2_23_NO_DQS = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_2_23_NO_LOCK = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_2_23_DRIFT_ERROR = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_2_23_MIN_EYE = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_3_23_NO_EYE_DETECTED = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_3_23_LEADING_EDGE_NOT_FOUND = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_3_23_TRAILING_EDGE_NOT_FOUND = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_3_23_INCOMPLETE_CAL_N0 = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_3_23_INCOMPLETE_CAL_N1 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_3_23_INCOMPLETE_CAL_N2 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_3_23_INCOMPLETE_CAL_N3 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_3_23_COARSE_PATTERN_ERR_N0 = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_3_23_COARSE_PATTERN_ERR_N1 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_3_23_COARSE_PATTERN_ERR_N2 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_3_23_COARSE_PATTERN_ERR_N3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_3_23_EYE_CLIPPING = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_3_23_NO_DQS = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_3_23_NO_LOCK = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_3_23_DRIFT_ERROR = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_3_23_MIN_EYE = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_4_4_NO_EYE_DETECTED = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_4_4_LEADING_EDGE_NOT_FOUND = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_4_4_TRAILING_EDGE_NOT_FOUND = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_4_4_INCOMPLETE_CAL_N0 = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_4_4_INCOMPLETE_CAL_N1 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_4_4_INCOMPLETE_CAL_N2 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_4_4_INCOMPLETE_CAL_N3 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_4_4_COARSE_PATTERN_ERR_N0 = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_4_4_COARSE_PATTERN_ERR_N1 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_4_4_COARSE_PATTERN_ERR_N2 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_4_4_COARSE_PATTERN_ERR_N3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_4_4_EYE_CLIPPING = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_4_4_NO_DQS = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_4_4_NO_LOCK = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_4_4_DRIFT_ERROR = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_4_4_MIN_EYE = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_CAL_EN_P0_0_01 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_CAL_EN_P0_0_01_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_CAL_EN_P0_1_01 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_CAL_EN_P0_1_01_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_CAL_EN_P0_2_23 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_CAL_EN_P0_2_23_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_CAL_EN_P0_3_23 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_CAL_EN_P0_3_23_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_CAL_EN_P0_4_4 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_CAL_EN_P0_4_4_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_0_01 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_0_01_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_1_01 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_1_01_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_2_23 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_2_23_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_3_23 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_3_23_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_4_4 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_4_4_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_0_P0_0_01_NIB0_EN_FORCE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_0_P0_0_01_BIT0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_0_P0_0_01_BIT0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_0_P0_0_01_NIB1_EN_FORCE = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_0_P0_0_01_BIT1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_0_P0_0_01_BIT1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_0_P0_1_01_NIB0_EN_FORCE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_0_P0_1_01_BIT0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_0_P0_1_01_BIT0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_0_P0_1_01_NIB1_EN_FORCE = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_0_P0_1_01_BIT1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_0_P0_1_01_BIT1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_0_P0_2_23_NIB0_EN_FORCE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_0_P0_2_23_BIT0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_0_P0_2_23_BIT0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_0_P0_2_23_NIB1_EN_FORCE = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_0_P0_2_23_BIT1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_0_P0_2_23_BIT1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_0_P0_3_23_NIB0_EN_FORCE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_0_P0_3_23_BIT0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_0_P0_3_23_BIT0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_0_P0_3_23_NIB1_EN_FORCE = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_0_P0_3_23_BIT1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_0_P0_3_23_BIT1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_0_P0_4_4_NIB0_EN_FORCE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_0_P0_4_4_BIT0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_0_P0_4_4_BIT0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_0_P0_4_4_NIB1_EN_FORCE = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_0_P0_4_4_BIT1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_0_P0_4_4_BIT1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_1_P0_0_01_NIB2_EN_FORCE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_1_P0_0_01_BIT2 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_1_P0_0_01_BIT2_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_1_P0_0_01_NIB3_EN_FORCE = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_1_P0_0_01_BIT3 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_1_P0_0_01_BIT3_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_1_P0_1_01_NIB2_EN_FORCE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_1_P0_1_01_BIT2 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_1_P0_1_01_BIT2_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_1_P0_1_01_NIB3_EN_FORCE = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_1_P0_1_01_BIT3 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_1_P0_1_01_BIT3_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_1_P0_2_23_NIB2_EN_FORCE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_1_P0_2_23_BIT2 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_1_P0_2_23_BIT2_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_1_P0_2_23_NIB3_EN_FORCE = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_1_P0_2_23_BIT3 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_1_P0_2_23_BIT3_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_1_P0_3_23_NIB2_EN_FORCE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_1_P0_3_23_BIT2 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_1_P0_3_23_BIT2_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_1_P0_3_23_NIB3_EN_FORCE = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_1_P0_3_23_BIT3 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_1_P0_3_23_BIT3_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_1_P0_4_4_NIB2_EN_FORCE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_1_P0_4_4_BIT2 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_1_P0_4_4_BIT2_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_1_P0_4_4_NIB3_EN_FORCE = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_1_P0_4_4_BIT3 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_1_P0_4_4_BIT3_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_2_P0_0_01_BIT4 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_2_P0_0_01_BIT4_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_2_P0_0_01_BIT5 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_2_P0_0_01_BIT5_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_2_P0_1_01_BIT4 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_2_P0_1_01_BIT4_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_2_P0_1_01_BIT5 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_2_P0_1_01_BIT5_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_2_P0_2_23_BIT4 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_2_P0_2_23_BIT4_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_2_P0_2_23_BIT5 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_2_P0_2_23_BIT5_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_2_P0_3_23_BIT4 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_2_P0_3_23_BIT4_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_2_P0_3_23_BIT5 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_2_P0_3_23_BIT5_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_2_P0_4_4_BIT4 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_2_P0_4_4_BIT4_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_2_P0_4_4_BIT5 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_2_P0_4_4_BIT5_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_3_P0_0_01_BIT6 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_3_P0_0_01_BIT6_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_3_P0_0_01_BIT7 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_3_P0_0_01_BIT7_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_3_P0_1_01_BIT6 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_3_P0_1_01_BIT6_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_3_P0_1_01_BIT7 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_3_P0_1_01_BIT7_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_3_P0_2_23_BIT6 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_3_P0_2_23_BIT6_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_3_P0_2_23_BIT7 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_3_P0_2_23_BIT7_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_3_P0_3_23_BIT6 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_3_P0_3_23_BIT6_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_3_P0_3_23_BIT7 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_3_P0_3_23_BIT7_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_3_P0_4_4_BIT6 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_3_P0_4_4_BIT6_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_3_P0_4_4_BIT7 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_3_P0_4_4_BIT7_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_4_P0_0_01_BIT8 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_4_P0_0_01_BIT8_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_4_P0_0_01_BIT9 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_4_P0_0_01_BIT9_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_4_P0_1_01_BIT8 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_4_P0_1_01_BIT8_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_4_P0_1_01_BIT9 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_4_P0_1_01_BIT9_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_4_P0_2_23_BIT8 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_4_P0_2_23_BIT8_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_4_P0_2_23_BIT9 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_4_P0_2_23_BIT9_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_4_P0_3_23_BIT8 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_4_P0_3_23_BIT8_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_4_P0_3_23_BIT9 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_4_P0_3_23_BIT9_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_4_P0_4_BIT8 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_4_P0_4_BIT8_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_4_P0_4_BIT9 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_4_P0_4_BIT9_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_5_P0_0_01_BIT10 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_5_P0_0_01_BIT10_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_5_P0_0_01_BIT11 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_5_P0_0_01_BIT11_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_5_P0_1_01_BIT10 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_5_P0_1_01_BIT10_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_5_P0_1_01_BIT11 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_5_P0_1_01_BIT11_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_5_P0_2_23_BIT10 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_5_P0_2_23_BIT10_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_5_P0_2_23_BIT11 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_5_P0_2_23_BIT11_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_5_P0_3_23_BIT10 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_5_P0_3_23_BIT10_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_5_P0_3_23_BIT11 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_5_P0_3_23_BIT11_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_5_P0_4_4_BIT10 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_5_P0_4_4_BIT10_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_5_P0_4_4_BIT11 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_5_P0_4_4_BIT11_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_6_P0_0_01_BIT12 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_6_P0_0_01_BIT12_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_6_P0_0_01_BIT13 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_6_P0_0_01_BIT13_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_6_P0_1_01_BIT12 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_6_P0_1_01_BIT12_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_6_P0_1_01_BIT13 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_6_P0_1_01_BIT13_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_6_P0_2_23_BIT12 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_6_P0_2_23_BIT12_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_6_P0_2_23_BIT13 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_6_P0_2_23_BIT13_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_6_P0_3_23_BIT12 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_6_P0_3_23_BIT12_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_6_P0_3_23_BIT13 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_6_P0_3_23_BIT13_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_6_P0_4_4_BIT12 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_6_P0_4_4_BIT12_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_6_P0_4_4_BIT13 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_6_P0_4_4_BIT13_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_7_P0_0_01_DD2_PERBIT_RDVREF_DISABLE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_7_P0_0_01_BIT14 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_7_P0_0_01_BIT14_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_7_P0_0_01_BIT15 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_7_P0_0_01_BIT15_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_7_P0_1_01_DD2_PERBIT_RDVREF_DISABLE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_7_P0_1_01_BIT14 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_7_P0_1_01_BIT14_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_7_P0_1_01_BIT15 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_7_P0_1_01_BIT15_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_7_P0_2_23_DD2_PERBIT_RDVREF_DISABLE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_7_P0_2_23_BIT14 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_7_P0_2_23_BIT14_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_7_P0_2_23_BIT15 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_7_P0_2_23_BIT15_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_7_P0_3_23_DD2_PERBIT_RDVREF_DISABLE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_7_P0_3_23_BIT14 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_7_P0_3_23_BIT14_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_7_P0_3_23_BIT15 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_7_P0_3_23_BIT15_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_7_P0_4_4_DD2_PERBIT_RDVREF_DISABLE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_7_P0_4_4_BIT14 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_7_P0_4_4_BIT14_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_7_P0_4_4_BIT15 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_7_P0_4_4_BIT15_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P0_0_01 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P0_0_01_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P0_1_01 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P0_1_01_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P0_2_23 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P0_2_23_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P0_3_23 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P0_3_23_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P0_4_4 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P0_4_4_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_0_01_QUAD0_CLK16 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_0_01_QUAD1_CLK16 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_0_01_QUAD0_CLK18 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_0_01_QUAD1_CLK18 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_0_01_QUAD2_CLK20 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_0_01_QUAD3_CLK20 = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_0_01_QUAD2_CLK22 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_0_01_QUAD3_CLK22 = 57 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_1_01_QUAD0_CLK16 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_1_01_QUAD1_CLK16 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_1_01_QUAD0_CLK18 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_1_01_QUAD1_CLK18 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_1_01_QUAD2_CLK20 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_1_01_QUAD3_CLK20 = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_1_01_QUAD2_CLK22 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_1_01_QUAD3_CLK22 = 57 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_2_23_QUAD0_CLK16 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_2_23_QUAD1_CLK16 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_2_23_QUAD0_CLK18 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_2_23_QUAD1_CLK18 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_2_23_QUAD2_CLK20 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_2_23_QUAD3_CLK20 = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_2_23_QUAD2_CLK22 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_2_23_QUAD3_CLK22 = 57 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_3_23_QUAD0_CLK16 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_3_23_QUAD1_CLK16 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_3_23_QUAD0_CLK18 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_3_23_QUAD1_CLK18 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_3_23_QUAD2_CLK20 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_3_23_QUAD3_CLK20 = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_3_23_QUAD2_CLK22 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_3_23_QUAD3_CLK22 = 57 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_4_4_QUAD0_CLK16 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_4_4_QUAD1_CLK16 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_4_4_QUAD0_CLK18 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_4_4_QUAD1_CLK18 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_4_4_QUAD2_CLK20 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_4_4_QUAD3_CLK20 = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_4_4_QUAD2_CLK22 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_4_4_QUAD3_CLK22 = 57 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_0_01_QUAD0_CLK16 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_0_01_QUAD1_CLK16 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_0_01_QUAD0_CLK18 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_0_01_QUAD1_CLK18 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_0_01_QUAD2_CLK20 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_0_01_QUAD3_CLK20 = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_0_01_QUAD2_CLK22 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_0_01_QUAD3_CLK22 = 57 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_1_01_QUAD0_CLK16 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_1_01_QUAD1_CLK16 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_1_01_QUAD0_CLK18 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_1_01_QUAD1_CLK18 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_1_01_QUAD2_CLK20 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_1_01_QUAD3_CLK20 = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_1_01_QUAD2_CLK22 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_1_01_QUAD3_CLK22 = 57 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_2_23_QUAD0_CLK16 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_2_23_QUAD1_CLK16 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_2_23_QUAD0_CLK18 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_2_23_QUAD1_CLK18 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_2_23_QUAD2_CLK20 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_2_23_QUAD3_CLK20 = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_2_23_QUAD2_CLK22 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_2_23_QUAD3_CLK22 = 57 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_3_23_QUAD0_CLK16 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_3_23_QUAD1_CLK16 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_3_23_QUAD0_CLK18 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_3_23_QUAD1_CLK18 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_3_23_QUAD2_CLK20 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_3_23_QUAD3_CLK20 = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_3_23_QUAD2_CLK22 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_3_23_QUAD3_CLK22 = 57 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_4_4_QUAD0_CLK16 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_4_4_QUAD1_CLK16 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_4_4_QUAD0_CLK18 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_4_4_QUAD1_CLK18 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_4_4_QUAD2_CLK20 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_4_4_QUAD3_CLK20 = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_4_4_QUAD2_CLK22 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_4_4_QUAD3_CLK22 = 57 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_0_01_QUAD0_CLK16 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_0_01_QUAD1_CLK16 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_0_01_QUAD0_CLK18 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_0_01_QUAD1_CLK18 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_0_01_QUAD2_CLK20 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_0_01_QUAD3_CLK20 = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_0_01_QUAD2_CLK22 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_0_01_QUAD3_CLK22 = 57 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_1_01_QUAD0_CLK16 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_1_01_QUAD1_CLK16 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_1_01_QUAD0_CLK18 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_1_01_QUAD1_CLK18 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_1_01_QUAD2_CLK20 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_1_01_QUAD3_CLK20 = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_1_01_QUAD2_CLK22 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_1_01_QUAD3_CLK22 = 57 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_2_23_QUAD0_CLK16 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_2_23_QUAD1_CLK16 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_2_23_QUAD0_CLK18 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_2_23_QUAD1_CLK18 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_2_23_QUAD2_CLK20 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_2_23_QUAD3_CLK20 = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_2_23_QUAD2_CLK22 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_2_23_QUAD3_CLK22 = 57 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_3_23_QUAD0_CLK16 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_3_23_QUAD1_CLK16 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_3_23_QUAD0_CLK18 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_3_23_QUAD1_CLK18 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_3_23_QUAD2_CLK20 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_3_23_QUAD3_CLK20 = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_3_23_QUAD2_CLK22 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_3_23_QUAD3_CLK22 = 57 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_4_4_QUAD0_CLK16 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_4_4_QUAD1_CLK16 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_4_4_QUAD0_CLK18 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_4_4_QUAD1_CLK18 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_4_4_QUAD2_CLK20 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_4_4_QUAD3_CLK20 = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_4_4_QUAD2_CLK22 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_4_4_QUAD3_CLK22 = 57 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_0_01_QUAD0_CLK16 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_0_01_QUAD1_CLK16 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_0_01_QUAD0_CLK18 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_0_01_QUAD1_CLK18 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_0_01_QUAD2_CLK20 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_0_01_QUAD3_CLK20 = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_0_01_QUAD2_CLK22 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_0_01_QUAD3_CLK22 = 57 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_1_01_QUAD0_CLK16 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_1_01_QUAD1_CLK16 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_1_01_QUAD0_CLK18 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_1_01_QUAD1_CLK18 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_1_01_QUAD2_CLK20 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_1_01_QUAD3_CLK20 = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_1_01_QUAD2_CLK22 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_1_01_QUAD3_CLK22 = 57 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_2_23_QUAD0_CLK16 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_2_23_QUAD1_CLK16 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_2_23_QUAD0_CLK18 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_2_23_QUAD1_CLK18 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_2_23_QUAD2_CLK20 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_2_23_QUAD3_CLK20 = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_2_23_QUAD2_CLK22 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_2_23_QUAD3_CLK22 = 57 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_3_23_QUAD0_CLK16 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_3_23_QUAD1_CLK16 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_3_23_QUAD0_CLK18 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_3_23_QUAD1_CLK18 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_3_23_QUAD2_CLK20 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_3_23_QUAD3_CLK20 = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_3_23_QUAD2_CLK22 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_3_23_QUAD3_CLK22 = 57 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_4_4_QUAD0_CLK16 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_4_4_QUAD1_CLK16 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_4_4_QUAD0_CLK18 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_4_4_QUAD1_CLK18 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_4_4_QUAD2_CLK20 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_4_4_QUAD3_CLK20 = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_4_4_QUAD2_CLK22 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_4_4_QUAD3_CLK22 = 57 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_0_01_RD = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_0_01_RD_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_0_01_RD_DELAY1 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_0_01_RD_DELAY1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_1_01_RD = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_1_01_RD_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_1_01_RD_DELAY1 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_1_01_RD_DELAY1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_2_23_RD = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_2_23_RD_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_2_23_RD_DELAY1 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_2_23_RD_DELAY1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_3_23_RD = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_3_23_RD_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_3_23_RD_DELAY1 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_3_23_RD_DELAY1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_4_4_RD = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_4_4_RD_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_4_4_RD_DELAY1 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_4_4_RD_DELAY1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_0_01_RD_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_0_01_RD_DELAY2_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_0_01_RD_DELAY3 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_0_01_RD_DELAY3_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_1_01_RD_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_1_01_RD_DELAY2_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_1_01_RD_DELAY3 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_1_01_RD_DELAY3_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_2_23_RD_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_2_23_RD_DELAY2_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_2_23_RD_DELAY3 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_2_23_RD_DELAY3_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_3_23_RD_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_3_23_RD_DELAY2_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_3_23_RD_DELAY3 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_3_23_RD_DELAY3_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_4_4_RD_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_4_4_RD_DELAY2_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_4_4_RD_DELAY3 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_4_4_RD_DELAY3_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_0_01_RD_DELAY4 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_0_01_RD_DELAY4_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_0_01_RD_DELAY5 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_0_01_RD_DELAY5_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_1_01_RD_DELAY4 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_1_01_RD_DELAY4_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_1_01_RD_DELAY5 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_1_01_RD_DELAY5_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_2_23_RD_DELAY4 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_2_23_RD_DELAY4_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_2_23_RD_DELAY5 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_2_23_RD_DELAY5_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_3_23_RD_DELAY4 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_3_23_RD_DELAY4_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_3_23_RD_DELAY5 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_3_23_RD_DELAY5_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_4_4_RD_DELAY4 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_4_4_RD_DELAY4_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_4_4_RD_DELAY5 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_4_4_RD_DELAY5_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_0_01_RD_DELAY6 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_0_01_RD_DELAY6_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_0_01_RD_DELAY7 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_0_01_RD_DELAY7_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_1_01_RD_DELAY6 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_1_01_RD_DELAY6_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_1_01_RD_DELAY7 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_1_01_RD_DELAY7_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_2_23_RD_DELAY6 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_2_23_RD_DELAY6_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_2_23_RD_DELAY7 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_2_23_RD_DELAY7_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_3_23_RD_DELAY6 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_3_23_RD_DELAY6_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_3_23_RD_DELAY7 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_3_23_RD_DELAY7_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_4_4_RD_DELAY6 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_4_4_RD_DELAY6_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_4_4_RD_DELAY7 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_4_4_RD_DELAY7_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_0_01_RD_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_0_01_RD_DELAY0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_0_01_RD = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_0_01_RD_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_1_01_RD_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_1_01_RD_DELAY0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_1_01_RD = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_1_01_RD_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_2_23_RD_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_2_23_RD_DELAY0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_2_23_RD = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_2_23_RD_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_3_23_RD_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_3_23_RD_DELAY0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_3_23_RD = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_3_23_RD_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_4_4_RD_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_4_4_RD_DELAY0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_4_4_RD = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_4_4_RD_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_0_01_RD_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_0_01_RD_DELAY2_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_0_01_RD_DELAY3 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_0_01_RD_DELAY3_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_1_01_RD_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_1_01_RD_DELAY2_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_1_01_RD_DELAY3 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_1_01_RD_DELAY3_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_2_23_RD_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_2_23_RD_DELAY2_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_2_23_RD_DELAY3 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_2_23_RD_DELAY3_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_3_23_RD_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_3_23_RD_DELAY2_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_3_23_RD_DELAY3 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_3_23_RD_DELAY3_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_4_4_RD_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_4_4_RD_DELAY2_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_4_4_RD_DELAY3 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_4_4_RD_DELAY3_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_0_01_RD_DELAY4 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_0_01_RD_DELAY4_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_0_01_RD_DELAY5 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_0_01_RD_DELAY5_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_1_01_RD_DELAY4 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_1_01_RD_DELAY4_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_1_01_RD_DELAY5 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_1_01_RD_DELAY5_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_2_23_RD_DELAY4 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_2_23_RD_DELAY4_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_2_23_RD_DELAY5 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_2_23_RD_DELAY5_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_3_23_RD_DELAY4 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_3_23_RD_DELAY4_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_3_23_RD_DELAY5 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_3_23_RD_DELAY5_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_4_4_RD_DELAY4 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_4_4_RD_DELAY4_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_4_4_RD_DELAY5 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_4_4_RD_DELAY5_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_0_01_RD_DELAY6 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_0_01_RD_DELAY6_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_0_01_RD_DELAY7 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_0_01_RD_DELAY7_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_1_01_RD_DELAY6 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_1_01_RD_DELAY6_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_1_01_RD_DELAY7 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_1_01_RD_DELAY7_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_2_23_RD_DELAY6 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_2_23_RD_DELAY6_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_2_23_RD_DELAY7 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_2_23_RD_DELAY7_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_3_23_RD_DELAY6 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_3_23_RD_DELAY6_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_3_23_RD_DELAY7 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_3_23_RD_DELAY7_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_4_4_RD_DELAY6 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_4_4_RD_DELAY6_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_4_4_RD_DELAY7 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_4_4_RD_DELAY7_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_0_01_RD_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_0_01_RD_DELAY0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_0_01_RD_DELAY1 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_0_01_RD_DELAY1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_1_01_RD_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_1_01_RD_DELAY0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_1_01_RD_DELAY1 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_1_01_RD_DELAY1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_2_23_RD_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_2_23_RD_DELAY0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_2_23_RD_DELAY1 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_2_23_RD_DELAY1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_3_23_RD_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_3_23_RD_DELAY0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_3_23_RD_DELAY1 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_3_23_RD_DELAY1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_4_4_RD_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_4_4_RD_DELAY0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_4_4_RD_DELAY1 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_4_4_RD_DELAY1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_0_01_RD = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_0_01_RD_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_0_01_RD_DELAY3 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_0_01_RD_DELAY3_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_1_01_RD = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_1_01_RD_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_1_01_RD_DELAY3 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_1_01_RD_DELAY3_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_2_23_RD = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_2_23_RD_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_2_23_RD_DELAY3 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_2_23_RD_DELAY3_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_3_23_RD = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_3_23_RD_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_3_23_RD_DELAY3 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_3_23_RD_DELAY3_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_4_4_RD = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_4_4_RD_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_4_4_RD_DELAY3 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_4_4_RD_DELAY3_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_0_01_RD_DELAY4 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_0_01_RD_DELAY4_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_0_01_RD_DELAY5 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_0_01_RD_DELAY5_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_1_01_RD_DELAY4 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_1_01_RD_DELAY4_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_1_01_RD_DELAY5 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_1_01_RD_DELAY5_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_2_23_RD_DELAY4 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_2_23_RD_DELAY4_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_2_23_RD_DELAY5 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_2_23_RD_DELAY5_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_3_23_RD_DELAY4 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_3_23_RD_DELAY4_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_3_23_RD_DELAY5 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_3_23_RD_DELAY5_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_4_4_RD_DELAY4 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_4_4_RD_DELAY4_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_4_4_RD_DELAY5 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_4_4_RD_DELAY5_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_0_01_RD_DELAY6 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_0_01_RD_DELAY6_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_0_01_RD_DELAY7 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_0_01_RD_DELAY7_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_1_01_RD_DELAY6 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_1_01_RD_DELAY6_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_1_01_RD_DELAY7 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_1_01_RD_DELAY7_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_2_23_RD_DELAY6 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_2_23_RD_DELAY6_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_2_23_RD_DELAY7 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_2_23_RD_DELAY7_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_3_23_RD_DELAY6 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_3_23_RD_DELAY6_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_3_23_RD_DELAY7 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_3_23_RD_DELAY7_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_4_4_RD_DELAY6 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_4_4_RD_DELAY6_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_4_4_RD_DELAY7 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_4_4_RD_DELAY7_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_0_01_RD_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_0_01_RD_DELAY0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_0_01_RD_DELAY1 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_0_01_RD_DELAY1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_1_01_RD_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_1_01_RD_DELAY0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_1_01_RD_DELAY1 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_1_01_RD_DELAY1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_2_23_RD_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_2_23_RD_DELAY0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_2_23_RD_DELAY1 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_2_23_RD_DELAY1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_3_23_RD_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_3_23_RD_DELAY0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_3_23_RD_DELAY1 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_3_23_RD_DELAY1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_4_4_RD_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_4_4_RD_DELAY0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_4_4_RD_DELAY1 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_4_4_RD_DELAY1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_0_01_RD_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_0_01_RD_DELAY2_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_0_01_RD = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_0_01_RD_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_1_01_RD_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_1_01_RD_DELAY2_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_1_01_RD = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_1_01_RD_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_2_23_RD_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_2_23_RD_DELAY2_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_2_23_RD = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_2_23_RD_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_3_23_RD_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_3_23_RD_DELAY2_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_3_23_RD = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_3_23_RD_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_4_4_RD_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_4_4_RD_DELAY2_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_4_4_RD = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_4_4_RD_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_0_01_RD_DELAY4 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_0_01_RD_DELAY4_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_0_01_RD_DELAY5 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_0_01_RD_DELAY5_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_1_01_RD_DELAY4 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_1_01_RD_DELAY4_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_1_01_RD_DELAY5 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_1_01_RD_DELAY5_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_2_23_RD_DELAY4 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_2_23_RD_DELAY4_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_2_23_RD_DELAY5 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_2_23_RD_DELAY5_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_3_23_RD_DELAY4 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_3_23_RD_DELAY4_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_3_23_RD_DELAY5 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_3_23_RD_DELAY5_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_4_4_RD_DELAY4 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_4_4_RD_DELAY4_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_4_4_RD_DELAY5 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_4_4_RD_DELAY5_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_0_01_RD_DELAY6 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_0_01_RD_DELAY6_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_0_01_RD_DELAY7 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_0_01_RD_DELAY7_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_1_01_RD_DELAY6 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_1_01_RD_DELAY6_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_1_01_RD_DELAY7 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_1_01_RD_DELAY7_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_2_23_RD_DELAY6 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_2_23_RD_DELAY6_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_2_23_RD_DELAY7 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_2_23_RD_DELAY7_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_3_23_RD_DELAY6 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_3_23_RD_DELAY6_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_3_23_RD_DELAY7 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_3_23_RD_DELAY7_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_4_4_RD_DELAY6 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_4_4_RD_DELAY6_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_4_4_RD_DELAY7 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_4_4_RD_DELAY7_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_0_01_RD_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_0_01_RD_DELAY0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_0_01_RD_DELAY1 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_0_01_RD_DELAY1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_1_01_RD_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_1_01_RD_DELAY0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_1_01_RD_DELAY1 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_1_01_RD_DELAY1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_2_23_RD_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_2_23_RD_DELAY0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_2_23_RD_DELAY1 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_2_23_RD_DELAY1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_3_23_RD_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_3_23_RD_DELAY0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_3_23_RD_DELAY1 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_3_23_RD_DELAY1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_4_4_RD_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_4_4_RD_DELAY0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_4_4_RD_DELAY1 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_4_4_RD_DELAY1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_0_01_RD_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_0_01_RD_DELAY2_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_0_01_RD_DELAY3 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_0_01_RD_DELAY3_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_1_01_RD_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_1_01_RD_DELAY2_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_1_01_RD_DELAY3 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_1_01_RD_DELAY3_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_2_23_RD_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_2_23_RD_DELAY2_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_2_23_RD_DELAY3 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_2_23_RD_DELAY3_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_3_23_RD_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_3_23_RD_DELAY2_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_3_23_RD_DELAY3 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_3_23_RD_DELAY3_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_4_4_RD_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_4_4_RD_DELAY2_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_4_4_RD_DELAY3 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_4_4_RD_DELAY3_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_0_01_RD = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_0_01_RD_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_0_01_RD_DELAY5 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_0_01_RD_DELAY5_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_1_01_RD = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_1_01_RD_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_1_01_RD_DELAY5 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_1_01_RD_DELAY5_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_2_23_RD = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_2_23_RD_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_2_23_RD_DELAY5 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_2_23_RD_DELAY5_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_3_23_RD = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_3_23_RD_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_3_23_RD_DELAY5 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_3_23_RD_DELAY5_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_4_4_RD = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_4_4_RD_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_4_4_RD_DELAY5 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_4_4_RD_DELAY5_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_0_01_RD_DELAY6 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_0_01_RD_DELAY6_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_0_01_RD_DELAY7 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_0_01_RD_DELAY7_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_1_01_RD_DELAY6 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_1_01_RD_DELAY6_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_1_01_RD_DELAY7 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_1_01_RD_DELAY7_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_2_23_RD_DELAY6 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_2_23_RD_DELAY6_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_2_23_RD_DELAY7 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_2_23_RD_DELAY7_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_3_23_RD_DELAY6 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_3_23_RD_DELAY6_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_3_23_RD_DELAY7 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_3_23_RD_DELAY7_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_4_4_RD_DELAY6 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_4_4_RD_DELAY6_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_4_4_RD_DELAY7 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_4_4_RD_DELAY7_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_0_01_RD_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_0_01_RD_DELAY0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_0_01_RD_DELAY1 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_0_01_RD_DELAY1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_1_01_RD_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_1_01_RD_DELAY0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_1_01_RD_DELAY1 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_1_01_RD_DELAY1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_2_23_RD_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_2_23_RD_DELAY0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_2_23_RD_DELAY1 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_2_23_RD_DELAY1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_3_23_RD_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_3_23_RD_DELAY0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_3_23_RD_DELAY1 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_3_23_RD_DELAY1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_4_4_RD_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_4_4_RD_DELAY0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_4_4_RD_DELAY1 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_4_4_RD_DELAY1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_0_01_RD_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_0_01_RD_DELAY2_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_0_01_RD_DELAY3 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_0_01_RD_DELAY3_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_1_01_RD_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_1_01_RD_DELAY2_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_1_01_RD_DELAY3 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_1_01_RD_DELAY3_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_2_23_RD_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_2_23_RD_DELAY2_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_2_23_RD_DELAY3 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_2_23_RD_DELAY3_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_3_23_RD_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_3_23_RD_DELAY2_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_3_23_RD_DELAY3 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_3_23_RD_DELAY3_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_4_4_RD_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_4_4_RD_DELAY2_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_4_4_RD_DELAY3 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_4_4_RD_DELAY3_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_0_01_RD_DELAY4 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_0_01_RD_DELAY4_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_0_01_RD = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_0_01_RD_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_1_01_RD_DELAY4 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_1_01_RD_DELAY4_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_1_01_RD = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_1_01_RD_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_2_23_RD_DELAY4 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_2_23_RD_DELAY4_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_2_23_RD = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_2_23_RD_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_3_23_RD_DELAY4 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_3_23_RD_DELAY4_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_3_23_RD = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_3_23_RD_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_4_4_RD_DELAY4 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_4_4_RD_DELAY4_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_4_4_RD = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_4_4_RD_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_0_01_RD_DELAY6 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_0_01_RD_DELAY6_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_0_01_RD_DELAY7 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_0_01_RD_DELAY7_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_1_01_RD_DELAY6 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_1_01_RD_DELAY6_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_1_01_RD_DELAY7 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_1_01_RD_DELAY7_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_2_23_RD_DELAY6 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_2_23_RD_DELAY6_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_2_23_RD_DELAY7 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_2_23_RD_DELAY7_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_3_23_RD_DELAY6 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_3_23_RD_DELAY6_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_3_23_RD_DELAY7 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_3_23_RD_DELAY7_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_4_4_RD_DELAY6 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_4_4_RD_DELAY6_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_4_4_RD_DELAY7 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_4_4_RD_DELAY7_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_0_01_RD_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_0_01_RD_DELAY0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_0_01_RD_DELAY1 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_0_01_RD_DELAY1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_1_01_RD_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_1_01_RD_DELAY0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_1_01_RD_DELAY1 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_1_01_RD_DELAY1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_2_23_RD_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_2_23_RD_DELAY0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_2_23_RD_DELAY1 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_2_23_RD_DELAY1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_3_23_RD_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_3_23_RD_DELAY0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_3_23_RD_DELAY1 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_3_23_RD_DELAY1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_4_4_RD_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_4_4_RD_DELAY0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_4_4_RD_DELAY1 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_4_4_RD_DELAY1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_0_01_RD_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_0_01_RD_DELAY2_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_0_01_RD_DELAY3 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_0_01_RD_DELAY3_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_1_01_RD_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_1_01_RD_DELAY2_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_1_01_RD_DELAY3 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_1_01_RD_DELAY3_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_2_23_RD_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_2_23_RD_DELAY2_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_2_23_RD_DELAY3 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_2_23_RD_DELAY3_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_3_23_RD_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_3_23_RD_DELAY2_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_3_23_RD_DELAY3 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_3_23_RD_DELAY3_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_4_4_RD_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_4_4_RD_DELAY2_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_4_4_RD_DELAY3 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_4_4_RD_DELAY3_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_0_01_RD_DELAY4 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_0_01_RD_DELAY4_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_0_01_RD_DELAY5 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_0_01_RD_DELAY5_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_1_01_RD_DELAY4 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_1_01_RD_DELAY4_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_1_01_RD_DELAY5 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_1_01_RD_DELAY5_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_2_23_RD_DELAY4 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_2_23_RD_DELAY4_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_2_23_RD_DELAY5 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_2_23_RD_DELAY5_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_3_23_RD_DELAY4 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_3_23_RD_DELAY4_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_3_23_RD_DELAY5 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_3_23_RD_DELAY5_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_4_4_RD_DELAY4 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_4_4_RD_DELAY4_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_4_4_RD_DELAY5 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_4_4_RD_DELAY5_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_0_01_RD = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_0_01_RD_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_0_01_RD_DELAY7 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_0_01_RD_DELAY7_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_1_01_RD = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_1_01_RD_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_1_01_RD_DELAY7 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_1_01_RD_DELAY7_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_2_23_RD = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_2_23_RD_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_2_23_RD_DELAY7 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_2_23_RD_DELAY7_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_3_23_RD = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_3_23_RD_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_3_23_RD_DELAY7 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_3_23_RD_DELAY7_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_4_4_RD = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_4_4_RD_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_4_4_RD_DELAY7 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_4_4_RD_DELAY7_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_0_01_RD_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_0_01_RD_DELAY0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_0_01_RD_DELAY1 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_0_01_RD_DELAY1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_1_01_RD_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_1_01_RD_DELAY0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_1_01_RD_DELAY1 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_1_01_RD_DELAY1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_2_23_RD_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_2_23_RD_DELAY0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_2_23_RD_DELAY1 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_2_23_RD_DELAY1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_3_23_RD_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_3_23_RD_DELAY0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_3_23_RD_DELAY1 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_3_23_RD_DELAY1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_4_4_RD_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_4_4_RD_DELAY0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_4_4_RD_DELAY1 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_4_4_RD_DELAY1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_0_01_RD_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_0_01_RD_DELAY2_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_0_01_RD_DELAY3 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_0_01_RD_DELAY3_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_1_01_RD_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_1_01_RD_DELAY2_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_1_01_RD_DELAY3 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_1_01_RD_DELAY3_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_2_23_RD_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_2_23_RD_DELAY2_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_2_23_RD_DELAY3 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_2_23_RD_DELAY3_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_3_23_RD_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_3_23_RD_DELAY2_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_3_23_RD_DELAY3 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_3_23_RD_DELAY3_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_4_4_RD_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_4_4_RD_DELAY2_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_4_4_RD_DELAY3 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_4_4_RD_DELAY3_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_0_01_RD_DELAY4 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_0_01_RD_DELAY4_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_0_01_RD_DELAY5 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_0_01_RD_DELAY5_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_1_01_RD_DELAY4 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_1_01_RD_DELAY4_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_1_01_RD_DELAY5 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_1_01_RD_DELAY5_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_2_23_RD_DELAY4 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_2_23_RD_DELAY4_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_2_23_RD_DELAY5 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_2_23_RD_DELAY5_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_3_23_RD_DELAY4 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_3_23_RD_DELAY4_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_3_23_RD_DELAY5 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_3_23_RD_DELAY5_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_4_4_RD_DELAY4 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_4_4_RD_DELAY4_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_4_4_RD_DELAY5 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_4_4_RD_DELAY5_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_0_01_RD_DELAY6 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_0_01_RD_DELAY6_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_0_01_RD = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_0_01_RD_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_1_01_RD_DELAY6 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_1_01_RD_DELAY6_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_1_01_RD = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_1_01_RD_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_2_23_RD_DELAY6 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_2_23_RD_DELAY6_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_2_23_RD = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_2_23_RD_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_3_23_RD_DELAY6 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_3_23_RD_DELAY6_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_3_23_RD = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_3_23_RD_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_4_4_RD_DELAY6 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_4_4_RD_DELAY6_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_4_4_RD = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_4_4_RD_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_0_01 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_0_01_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_0_01_OFFSET1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_0_01_OFFSET1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_1_01 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_1_01_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_1_01_OFFSET1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_1_01_OFFSET1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_2_23 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_2_23_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_2_23_OFFSET1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_2_23_OFFSET1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_3_23 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_3_23_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_3_23_OFFSET1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_3_23_OFFSET1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_4_4 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_4_4_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_4_4_OFFSET1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_4_4_OFFSET1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_0_01_OFFSET2 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_0_01_OFFSET2_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_0_01_OFFSET3 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_0_01_OFFSET3_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_1_01_OFFSET2 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_1_01_OFFSET2_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_1_01_OFFSET3 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_1_01_OFFSET3_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_2_23_OFFSET2 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_2_23_OFFSET2_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_2_23_OFFSET3 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_2_23_OFFSET3_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_3_23_OFFSET2 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_3_23_OFFSET2_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_3_23_OFFSET3 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_3_23_OFFSET3_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_4_4_OFFSET2 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_4_4_OFFSET2_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_4_4_OFFSET3 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_4_4_OFFSET3_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_0_01_OFFSET4 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_0_01_OFFSET4_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_0_01_OFFSET5 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_0_01_OFFSET5_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_1_01_OFFSET4 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_1_01_OFFSET4_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_1_01_OFFSET5 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_1_01_OFFSET5_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_2_23_OFFSET4 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_2_23_OFFSET4_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_2_23_OFFSET5 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_2_23_OFFSET5_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_3_23_OFFSET4 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_3_23_OFFSET4_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_3_23_OFFSET5 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_3_23_OFFSET5_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_4_4_OFFSET4 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_4_4_OFFSET4_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_4_4_OFFSET5 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_4_4_OFFSET5_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_0_01_OFFSET6 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_0_01_OFFSET6_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_0_01_OFFSET7 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_0_01_OFFSET7_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_1_01_OFFSET6 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_1_01_OFFSET6_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_1_01_OFFSET7 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_1_01_OFFSET7_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_2_23_OFFSET6 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_2_23_OFFSET6_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_2_23_OFFSET7 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_2_23_OFFSET7_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_3_23_OFFSET6 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_3_23_OFFSET6_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_3_23_OFFSET7 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_3_23_OFFSET7_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_4_4_OFFSET6 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_4_4_OFFSET6_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_4_4_OFFSET7 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_4_4_OFFSET7_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_0_01_OFFSET0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_0_01_OFFSET0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_0_01 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_0_01_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_1_01_OFFSET0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_1_01_OFFSET0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_1_01 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_1_01_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_2_23_OFFSET0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_2_23_OFFSET0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_2_23 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_2_23_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_3_23_OFFSET0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_3_23_OFFSET0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_3_23 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_3_23_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_4_4_OFFSET0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_4_4_OFFSET0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_4_4 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_4_4_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_0_01_OFFSET2 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_0_01_OFFSET2_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_0_01_OFFSET3 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_0_01_OFFSET3_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_1_01_OFFSET2 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_1_01_OFFSET2_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_1_01_OFFSET3 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_1_01_OFFSET3_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_2_23_OFFSET2 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_2_23_OFFSET2_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_2_23_OFFSET3 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_2_23_OFFSET3_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_3_23_OFFSET2 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_3_23_OFFSET2_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_3_23_OFFSET3 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_3_23_OFFSET3_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_4_4_OFFSET2 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_4_4_OFFSET2_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_4_4_OFFSET3 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_4_4_OFFSET3_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_0_01_OFFSET4 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_0_01_OFFSET4_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_0_01_OFFSET5 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_0_01_OFFSET5_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_1_01_OFFSET4 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_1_01_OFFSET4_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_1_01_OFFSET5 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_1_01_OFFSET5_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_2_23_OFFSET4 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_2_23_OFFSET4_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_2_23_OFFSET5 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_2_23_OFFSET5_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_3_23_OFFSET4 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_3_23_OFFSET4_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_3_23_OFFSET5 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_3_23_OFFSET5_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_4_4_OFFSET4 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_4_4_OFFSET4_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_4_4_OFFSET5 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_4_4_OFFSET5_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_0_01_OFFSET6 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_0_01_OFFSET6_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_0_01_OFFSET7 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_0_01_OFFSET7_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_1_01_OFFSET6 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_1_01_OFFSET6_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_1_01_OFFSET7 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_1_01_OFFSET7_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_2_23_OFFSET6 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_2_23_OFFSET6_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_2_23_OFFSET7 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_2_23_OFFSET7_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_3_23_OFFSET6 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_3_23_OFFSET6_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_3_23_OFFSET7 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_3_23_OFFSET7_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_4_4_OFFSET6 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_4_4_OFFSET6_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_4_4_OFFSET7 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_4_4_OFFSET7_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_0_01 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_0_01_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_1_01 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_1_01_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_2_23 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_2_23_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_3_23 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_3_23_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_4_4 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_4_4_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_0_01_RD = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_0_01_RD_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_0_01_RD_SIZE1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_0_01_RD_SIZE1_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_1_01_RD = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_1_01_RD_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_1_01_RD_SIZE1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_1_01_RD_SIZE1_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_2_23_RD = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_2_23_RD_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_2_23_RD_SIZE1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_2_23_RD_SIZE1_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_3_23_RD = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_3_23_RD_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_3_23_RD_SIZE1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_3_23_RD_SIZE1_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_4_4_RD = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_4_4_RD_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_4_4_RD_SIZE1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_4_4_RD_SIZE1_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_0_01_RD_SIZE2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_0_01_RD_SIZE2_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_0_01_RD_SIZE3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_0_01_RD_SIZE3_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_1_01_RD_SIZE2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_1_01_RD_SIZE2_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_1_01_RD_SIZE3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_1_01_RD_SIZE3_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_2_23_RD_SIZE2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_2_23_RD_SIZE2_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_2_23_RD_SIZE3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_2_23_RD_SIZE3_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_3_23_RD_SIZE2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_3_23_RD_SIZE2_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_3_23_RD_SIZE3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_3_23_RD_SIZE3_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_4_4_RD_SIZE2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_4_4_RD_SIZE2_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_4_4_RD_SIZE3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_4_4_RD_SIZE3_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_0_01_RD_SIZE4 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_0_01_RD_SIZE4_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_0_01_RD_SIZE5 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_0_01_RD_SIZE5_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_1_01_RD_SIZE4 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_1_01_RD_SIZE4_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_1_01_RD_SIZE5 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_1_01_RD_SIZE5_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_2_23_RD_SIZE4 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_2_23_RD_SIZE4_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_2_23_RD_SIZE5 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_2_23_RD_SIZE5_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_3_23_RD_SIZE4 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_3_23_RD_SIZE4_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_3_23_RD_SIZE5 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_3_23_RD_SIZE5_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_4_4_RD_SIZE4 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_4_4_RD_SIZE4_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_4_4_RD_SIZE5 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_4_4_RD_SIZE5_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_0_01_RD_SIZE6 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_0_01_RD_SIZE6_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_0_01_RD_SIZE7 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_0_01_RD_SIZE7_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_1_01_RD_SIZE6 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_1_01_RD_SIZE6_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_1_01_RD_SIZE7 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_1_01_RD_SIZE7_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_2_23_RD_SIZE6 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_2_23_RD_SIZE6_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_2_23_RD_SIZE7 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_2_23_RD_SIZE7_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_3_23_RD_SIZE6 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_3_23_RD_SIZE6_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_3_23_RD_SIZE7 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_3_23_RD_SIZE7_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_4_4_RD_SIZE6 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_4_4_RD_SIZE6_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_4_4_RD_SIZE7 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_4_4_RD_SIZE7_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_0_01_RD_SIZE0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_0_01_RD_SIZE0_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_0_01_RD_SIZE1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_0_01_RD_SIZE1_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_1_01_RD_SIZE0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_1_01_RD_SIZE0_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_1_01_RD_SIZE1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_1_01_RD_SIZE1_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_2_23_RD_SIZE0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_2_23_RD_SIZE0_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_2_23_RD_SIZE1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_2_23_RD_SIZE1_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_3_23_RD_SIZE0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_3_23_RD_SIZE0_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_3_23_RD_SIZE1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_3_23_RD_SIZE1_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_4_4_RD_SIZE0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_4_4_RD_SIZE0_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_4_4_RD_SIZE1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_4_4_RD_SIZE1_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_0_01_RD_SIZE2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_0_01_RD_SIZE2_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_0_01_RD_SIZE3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_0_01_RD_SIZE3_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_1_01_RD_SIZE2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_1_01_RD_SIZE2_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_1_01_RD_SIZE3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_1_01_RD_SIZE3_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_2_23_RD_SIZE2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_2_23_RD_SIZE2_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_2_23_RD_SIZE3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_2_23_RD_SIZE3_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_3_23_RD_SIZE2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_3_23_RD_SIZE2_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_3_23_RD_SIZE3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_3_23_RD_SIZE3_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_4_4_RD_SIZE2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_4_4_RD_SIZE2_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_4_4_RD_SIZE3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_4_4_RD_SIZE3_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_0_01_RD_SIZE4 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_0_01_RD_SIZE4_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_0_01_RD_SIZE5 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_0_01_RD_SIZE5_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_1_01_RD_SIZE4 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_1_01_RD_SIZE4_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_1_01_RD_SIZE5 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_1_01_RD_SIZE5_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_2_23_RD_SIZE4 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_2_23_RD_SIZE4_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_2_23_RD_SIZE5 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_2_23_RD_SIZE5_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_3_23_RD_SIZE4 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_3_23_RD_SIZE4_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_3_23_RD_SIZE5 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_3_23_RD_SIZE5_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_4_4_RD_SIZE4 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_4_4_RD_SIZE4_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_4_4_RD_SIZE5 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_4_4_RD_SIZE5_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_0_01_RD_SIZE6 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_0_01_RD_SIZE6_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_0_01_RD_SIZE7 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_0_01_RD_SIZE7_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_1_01_RD_SIZE6 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_1_01_RD_SIZE6_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_1_01_RD_SIZE7 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_1_01_RD_SIZE7_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_2_23_RD_SIZE6 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_2_23_RD_SIZE6_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_2_23_RD_SIZE7 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_2_23_RD_SIZE7_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_3_23_RD_SIZE6 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_3_23_RD_SIZE6_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_3_23_RD_SIZE7 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_3_23_RD_SIZE7_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_4_4_RD_SIZE6 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_4_4_RD_SIZE6_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_4_4_RD_SIZE7 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_4_4_RD_SIZE7_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_0_01_RD_SIZE0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_0_01_RD_SIZE0_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_0_01_RD_SIZE1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_0_01_RD_SIZE1_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_1_01_RD_SIZE0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_1_01_RD_SIZE0_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_1_01_RD_SIZE1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_1_01_RD_SIZE1_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_2_23_RD_SIZE0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_2_23_RD_SIZE0_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_2_23_RD_SIZE1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_2_23_RD_SIZE1_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_3_23_RD_SIZE0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_3_23_RD_SIZE0_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_3_23_RD_SIZE1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_3_23_RD_SIZE1_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_4_4_RD_SIZE0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_4_4_RD_SIZE0_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_4_4_RD_SIZE1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_4_4_RD_SIZE1_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_0_01_RD_SIZE2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_0_01_RD_SIZE2_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_0_01_RD_SIZE3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_0_01_RD_SIZE3_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_1_01_RD_SIZE2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_1_01_RD_SIZE2_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_1_01_RD_SIZE3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_1_01_RD_SIZE3_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_2_23_RD_SIZE2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_2_23_RD_SIZE2_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_2_23_RD_SIZE3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_2_23_RD_SIZE3_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_3_23_RD_SIZE2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_3_23_RD_SIZE2_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_3_23_RD_SIZE3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_3_23_RD_SIZE3_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_4_4_RD_SIZE2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_4_4_RD_SIZE2_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_4_4_RD_SIZE3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_4_4_RD_SIZE3_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_0_01_RD_SIZE4 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_0_01_RD_SIZE4_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_0_01_RD_SIZE5 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_0_01_RD_SIZE5_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_1_01_RD_SIZE4 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_1_01_RD_SIZE4_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_1_01_RD_SIZE5 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_1_01_RD_SIZE5_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_2_23_RD_SIZE4 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_2_23_RD_SIZE4_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_2_23_RD_SIZE5 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_2_23_RD_SIZE5_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_3_23_RD_SIZE4 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_3_23_RD_SIZE4_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_3_23_RD_SIZE5 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_3_23_RD_SIZE5_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_4_4_RD_SIZE4 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_4_4_RD_SIZE4_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_4_4_RD_SIZE5 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_4_4_RD_SIZE5_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_0_01_RD_SIZE6 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_0_01_RD_SIZE6_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_0_01_RD_SIZE7 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_0_01_RD_SIZE7_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_1_01_RD_SIZE6 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_1_01_RD_SIZE6_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_1_01_RD_SIZE7 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_1_01_RD_SIZE7_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_2_23_RD_SIZE6 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_2_23_RD_SIZE6_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_2_23_RD_SIZE7 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_2_23_RD_SIZE7_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_3_23_RD_SIZE6 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_3_23_RD_SIZE6_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_3_23_RD_SIZE7 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_3_23_RD_SIZE7_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_4_4_RD_SIZE6 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_4_4_RD_SIZE6_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_4_4_RD_SIZE7 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_4_4_RD_SIZE7_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_0_01_RD_SIZE0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_0_01_RD_SIZE0_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_0_01_RD = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_0_01_RD_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_1_01_RD_SIZE0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_1_01_RD_SIZE0_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_1_01_RD = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_1_01_RD_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_2_23_RD_SIZE0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_2_23_RD_SIZE0_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_2_23_RD = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_2_23_RD_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_3_23_RD_SIZE0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_3_23_RD_SIZE0_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_3_23_RD = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_3_23_RD_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_4_4_RD_SIZE0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_4_4_RD_SIZE0_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_4_4_RD = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_4_4_RD_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_0_01_RD_SIZE2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_0_01_RD_SIZE2_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_0_01_RD_SIZE3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_0_01_RD_SIZE3_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_1_01_RD_SIZE2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_1_01_RD_SIZE2_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_1_01_RD_SIZE3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_1_01_RD_SIZE3_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_2_23_RD_SIZE2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_2_23_RD_SIZE2_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_2_23_RD_SIZE3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_2_23_RD_SIZE3_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_3_23_RD_SIZE2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_3_23_RD_SIZE2_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_3_23_RD_SIZE3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_3_23_RD_SIZE3_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_4_4_RD_SIZE2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_4_4_RD_SIZE2_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_4_4_RD_SIZE3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_4_4_RD_SIZE3_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_0_01_RD_SIZE4 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_0_01_RD_SIZE4_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_0_01_RD_SIZE5 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_0_01_RD_SIZE5_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_1_01_RD_SIZE4 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_1_01_RD_SIZE4_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_1_01_RD_SIZE5 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_1_01_RD_SIZE5_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_2_23_RD_SIZE4 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_2_23_RD_SIZE4_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_2_23_RD_SIZE5 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_2_23_RD_SIZE5_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_3_23_RD_SIZE4 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_3_23_RD_SIZE4_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_3_23_RD_SIZE5 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_3_23_RD_SIZE5_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_4_4_RD_SIZE4 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_4_4_RD_SIZE4_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_4_4_RD_SIZE5 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_4_4_RD_SIZE5_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_0_01_RD_SIZE6 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_0_01_RD_SIZE6_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_0_01_RD_SIZE7 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_0_01_RD_SIZE7_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_1_01_RD_SIZE6 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_1_01_RD_SIZE6_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_1_01_RD_SIZE7 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_1_01_RD_SIZE7_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_2_23_RD_SIZE6 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_2_23_RD_SIZE6_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_2_23_RD_SIZE7 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_2_23_RD_SIZE7_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_3_23_RD_SIZE6 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_3_23_RD_SIZE6_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_3_23_RD_SIZE7 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_3_23_RD_SIZE7_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_4_4_RD_SIZE6 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_4_4_RD_SIZE6_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_4_4_RD_SIZE7 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_4_4_RD_SIZE7_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_0_01_RD_SIZE0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_0_01_RD_SIZE0_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_0_01_RD_SIZE1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_0_01_RD_SIZE1_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_1_01_RD_SIZE0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_1_01_RD_SIZE0_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_1_01_RD_SIZE1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_1_01_RD_SIZE1_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_2_23_RD_SIZE0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_2_23_RD_SIZE0_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_2_23_RD_SIZE1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_2_23_RD_SIZE1_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_3_23_RD_SIZE0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_3_23_RD_SIZE0_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_3_23_RD_SIZE1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_3_23_RD_SIZE1_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_4_4_RD_SIZE0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_4_4_RD_SIZE0_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_4_4_RD_SIZE1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_4_4_RD_SIZE1_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_0_01_RD = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_0_01_RD_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_0_01_RD_SIZE3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_0_01_RD_SIZE3_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_1_01_RD = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_1_01_RD_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_1_01_RD_SIZE3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_1_01_RD_SIZE3_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_2_23_RD = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_2_23_RD_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_2_23_RD_SIZE3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_2_23_RD_SIZE3_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_3_23_RD = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_3_23_RD_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_3_23_RD_SIZE3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_3_23_RD_SIZE3_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_4_4_RD = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_4_4_RD_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_4_4_RD_SIZE3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_4_4_RD_SIZE3_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_0_01_RD_SIZE4 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_0_01_RD_SIZE4_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_0_01_RD_SIZE5 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_0_01_RD_SIZE5_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_1_01_RD_SIZE4 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_1_01_RD_SIZE4_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_1_01_RD_SIZE5 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_1_01_RD_SIZE5_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_2_23_RD_SIZE4 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_2_23_RD_SIZE4_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_2_23_RD_SIZE5 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_2_23_RD_SIZE5_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_3_23_RD_SIZE4 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_3_23_RD_SIZE4_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_3_23_RD_SIZE5 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_3_23_RD_SIZE5_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_4_4_RD_SIZE4 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_4_4_RD_SIZE4_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_4_4_RD_SIZE5 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_4_4_RD_SIZE5_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_0_01_RD_SIZE6 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_0_01_RD_SIZE6_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_0_01_RD_SIZE7 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_0_01_RD_SIZE7_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_1_01_RD_SIZE6 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_1_01_RD_SIZE6_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_1_01_RD_SIZE7 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_1_01_RD_SIZE7_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_2_23_RD_SIZE6 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_2_23_RD_SIZE6_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_2_23_RD_SIZE7 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_2_23_RD_SIZE7_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_3_23_RD_SIZE6 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_3_23_RD_SIZE6_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_3_23_RD_SIZE7 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_3_23_RD_SIZE7_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_4_4_RD_SIZE6 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_4_4_RD_SIZE6_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_4_4_RD_SIZE7 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_4_4_RD_SIZE7_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_0_01_RD_SIZE0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_0_01_RD_SIZE0_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_0_01_RD_SIZE1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_0_01_RD_SIZE1_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_1_01_RD_SIZE0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_1_01_RD_SIZE0_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_1_01_RD_SIZE1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_1_01_RD_SIZE1_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_2_23_RD_SIZE0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_2_23_RD_SIZE0_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_2_23_RD_SIZE1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_2_23_RD_SIZE1_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_3_23_RD_SIZE0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_3_23_RD_SIZE0_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_3_23_RD_SIZE1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_3_23_RD_SIZE1_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_4_4_RD_SIZE0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_4_4_RD_SIZE0_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_4_4_RD_SIZE1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_4_4_RD_SIZE1_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_0_01_RD_SIZE2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_0_01_RD_SIZE2_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_0_01_RD = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_0_01_RD_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_1_01_RD_SIZE2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_1_01_RD_SIZE2_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_1_01_RD = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_1_01_RD_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_2_23_RD_SIZE2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_2_23_RD_SIZE2_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_2_23_RD = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_2_23_RD_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_3_23_RD_SIZE2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_3_23_RD_SIZE2_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_3_23_RD = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_3_23_RD_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_4_4_RD_SIZE2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_4_4_RD_SIZE2_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_4_4_RD = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_4_4_RD_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_0_01_RD_SIZE4 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_0_01_RD_SIZE4_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_0_01_RD_SIZE5 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_0_01_RD_SIZE5_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_1_01_RD_SIZE4 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_1_01_RD_SIZE4_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_1_01_RD_SIZE5 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_1_01_RD_SIZE5_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_2_23_RD_SIZE4 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_2_23_RD_SIZE4_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_2_23_RD_SIZE5 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_2_23_RD_SIZE5_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_3_23_RD_SIZE4 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_3_23_RD_SIZE4_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_3_23_RD_SIZE5 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_3_23_RD_SIZE5_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_4_4_RD_SIZE4 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_4_4_RD_SIZE4_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_4_4_RD_SIZE5 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_4_4_RD_SIZE5_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_0_01_RD_SIZE6 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_0_01_RD_SIZE6_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_0_01_RD_SIZE7 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_0_01_RD_SIZE7_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_1_01_RD_SIZE6 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_1_01_RD_SIZE6_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_1_01_RD_SIZE7 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_1_01_RD_SIZE7_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_2_23_RD_SIZE6 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_2_23_RD_SIZE6_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_2_23_RD_SIZE7 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_2_23_RD_SIZE7_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_3_23_RD_SIZE6 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_3_23_RD_SIZE6_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_3_23_RD_SIZE7 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_3_23_RD_SIZE7_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_4_4_RD_SIZE6 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_4_4_RD_SIZE6_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_4_4_RD_SIZE7 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_4_4_RD_SIZE7_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_0_01_RD_SIZE0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_0_01_RD_SIZE0_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_0_01_RD_SIZE1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_0_01_RD_SIZE1_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_1_01_RD_SIZE0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_1_01_RD_SIZE0_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_1_01_RD_SIZE1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_1_01_RD_SIZE1_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_2_23_RD_SIZE0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_2_23_RD_SIZE0_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_2_23_RD_SIZE1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_2_23_RD_SIZE1_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_3_23_RD_SIZE0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_3_23_RD_SIZE0_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_3_23_RD_SIZE1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_3_23_RD_SIZE1_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_4_4_RD_SIZE0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_4_4_RD_SIZE0_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_4_4_RD_SIZE1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_4_4_RD_SIZE1_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_0_01_RD_SIZE2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_0_01_RD_SIZE2_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_0_01_RD_SIZE3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_0_01_RD_SIZE3_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_1_01_RD_SIZE2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_1_01_RD_SIZE2_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_1_01_RD_SIZE3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_1_01_RD_SIZE3_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_2_23_RD_SIZE2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_2_23_RD_SIZE2_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_2_23_RD_SIZE3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_2_23_RD_SIZE3_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_3_23_RD_SIZE2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_3_23_RD_SIZE2_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_3_23_RD_SIZE3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_3_23_RD_SIZE3_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_4_4_RD_SIZE2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_4_4_RD_SIZE2_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_4_4_RD_SIZE3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_4_4_RD_SIZE3_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_0_01_RD = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_0_01_RD_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_0_01_RD_SIZE5 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_0_01_RD_SIZE5_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_1_01_RD = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_1_01_RD_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_1_01_RD_SIZE5 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_1_01_RD_SIZE5_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_2_23_RD = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_2_23_RD_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_2_23_RD_SIZE5 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_2_23_RD_SIZE5_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_3_23_RD = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_3_23_RD_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_3_23_RD_SIZE5 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_3_23_RD_SIZE5_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_4_4_RD = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_4_4_RD_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_4_4_RD_SIZE5 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_4_4_RD_SIZE5_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_0_01_RD_SIZE6 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_0_01_RD_SIZE6_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_0_01_RD_SIZE7 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_0_01_RD_SIZE7_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_1_01_RD_SIZE6 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_1_01_RD_SIZE6_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_1_01_RD_SIZE7 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_1_01_RD_SIZE7_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_2_23_RD_SIZE6 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_2_23_RD_SIZE6_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_2_23_RD_SIZE7 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_2_23_RD_SIZE7_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_3_23_RD_SIZE6 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_3_23_RD_SIZE6_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_3_23_RD_SIZE7 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_3_23_RD_SIZE7_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_4_4_RD_SIZE6 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_4_4_RD_SIZE6_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_4_4_RD_SIZE7 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_4_4_RD_SIZE7_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_0_01_RD_SIZE0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_0_01_RD_SIZE0_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_0_01_RD_SIZE1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_0_01_RD_SIZE1_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_1_01_RD_SIZE0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_1_01_RD_SIZE0_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_1_01_RD_SIZE1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_1_01_RD_SIZE1_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_2_23_RD_SIZE0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_2_23_RD_SIZE0_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_2_23_RD_SIZE1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_2_23_RD_SIZE1_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_3_23_RD_SIZE0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_3_23_RD_SIZE0_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_3_23_RD_SIZE1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_3_23_RD_SIZE1_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_4_4_RD_SIZE0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_4_4_RD_SIZE0_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_4_4_RD_SIZE1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_4_4_RD_SIZE1_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_0_01_RD_SIZE2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_0_01_RD_SIZE2_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_0_01_RD_SIZE3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_0_01_RD_SIZE3_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_1_01_RD_SIZE2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_1_01_RD_SIZE2_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_1_01_RD_SIZE3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_1_01_RD_SIZE3_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_2_23_RD_SIZE2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_2_23_RD_SIZE2_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_2_23_RD_SIZE3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_2_23_RD_SIZE3_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_3_23_RD_SIZE2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_3_23_RD_SIZE2_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_3_23_RD_SIZE3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_3_23_RD_SIZE3_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_4_4_RD_SIZE2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_4_4_RD_SIZE2_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_4_4_RD_SIZE3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_4_4_RD_SIZE3_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_0_01_RD_SIZE4 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_0_01_RD_SIZE4_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_0_01_RD = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_0_01_RD_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_1_01_RD_SIZE4 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_1_01_RD_SIZE4_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_1_01_RD = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_1_01_RD_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_2_23_RD_SIZE4 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_2_23_RD_SIZE4_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_2_23_RD = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_2_23_RD_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_3_23_RD_SIZE4 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_3_23_RD_SIZE4_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_3_23_RD = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_3_23_RD_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_4_4_RD_SIZE4 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_4_4_RD_SIZE4_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_4_4_RD = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_4_4_RD_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_0_01_RD_SIZE6 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_0_01_RD_SIZE6_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_0_01_RD_SIZE7 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_0_01_RD_SIZE7_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_1_01_RD_SIZE6 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_1_01_RD_SIZE6_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_1_01_RD_SIZE7 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_1_01_RD_SIZE7_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_2_23_RD_SIZE6 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_2_23_RD_SIZE6_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_2_23_RD_SIZE7 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_2_23_RD_SIZE7_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_3_23_RD_SIZE6 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_3_23_RD_SIZE6_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_3_23_RD_SIZE7 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_3_23_RD_SIZE7_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_4_4_RD_SIZE6 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_4_4_RD_SIZE6_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_4_4_RD_SIZE7 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_4_4_RD_SIZE7_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_0_01_RD_SIZE0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_0_01_RD_SIZE0_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_0_01_RD_SIZE1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_0_01_RD_SIZE1_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_1_01_RD_SIZE0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_1_01_RD_SIZE0_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_1_01_RD_SIZE1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_1_01_RD_SIZE1_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_2_23_RD_SIZE0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_2_23_RD_SIZE0_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_2_23_RD_SIZE1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_2_23_RD_SIZE1_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_3_23_RD_SIZE0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_3_23_RD_SIZE0_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_3_23_RD_SIZE1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_3_23_RD_SIZE1_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_4_4_RD_SIZE0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_4_4_RD_SIZE0_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_4_4_RD_SIZE1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_4_4_RD_SIZE1_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_0_01_RD_SIZE2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_0_01_RD_SIZE2_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_0_01_RD_SIZE3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_0_01_RD_SIZE3_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_1_01_RD_SIZE2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_1_01_RD_SIZE2_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_1_01_RD_SIZE3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_1_01_RD_SIZE3_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_2_23_RD_SIZE2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_2_23_RD_SIZE2_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_2_23_RD_SIZE3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_2_23_RD_SIZE3_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_3_23_RD_SIZE2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_3_23_RD_SIZE2_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_3_23_RD_SIZE3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_3_23_RD_SIZE3_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_4_4_RD_SIZE2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_4_4_RD_SIZE2_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_4_4_RD_SIZE3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_4_4_RD_SIZE3_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_0_01_RD_SIZE4 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_0_01_RD_SIZE4_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_0_01_RD_SIZE5 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_0_01_RD_SIZE5_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_1_01_RD_SIZE4 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_1_01_RD_SIZE4_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_1_01_RD_SIZE5 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_1_01_RD_SIZE5_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_2_23_RD_SIZE4 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_2_23_RD_SIZE4_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_2_23_RD_SIZE5 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_2_23_RD_SIZE5_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_3_23_RD_SIZE4 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_3_23_RD_SIZE4_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_3_23_RD_SIZE5 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_3_23_RD_SIZE5_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_4_4_RD_SIZE4 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_4_4_RD_SIZE4_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_4_4_RD_SIZE5 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_4_4_RD_SIZE5_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_0_01_RD = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_0_01_RD_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_0_01_RD_SIZE7 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_0_01_RD_SIZE7_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_1_01_RD = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_1_01_RD_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_1_01_RD_SIZE7 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_1_01_RD_SIZE7_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_2_23_RD = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_2_23_RD_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_2_23_RD_SIZE7 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_2_23_RD_SIZE7_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_3_23_RD = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_3_23_RD_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_3_23_RD_SIZE7 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_3_23_RD_SIZE7_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_4_4_RD = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_4_4_RD_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_4_4_RD_SIZE7 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_4_4_RD_SIZE7_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_0_01_RD_SIZE0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_0_01_RD_SIZE0_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_0_01_RD_SIZE1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_0_01_RD_SIZE1_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_1_01_RD_SIZE0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_1_01_RD_SIZE0_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_1_01_RD_SIZE1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_1_01_RD_SIZE1_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_2_23_RD_SIZE0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_2_23_RD_SIZE0_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_2_23_RD_SIZE1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_2_23_RD_SIZE1_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_3_23_RD_SIZE0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_3_23_RD_SIZE0_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_3_23_RD_SIZE1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_3_23_RD_SIZE1_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_4_4_RD_SIZE0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_4_4_RD_SIZE0_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_4_4_RD_SIZE1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_4_4_RD_SIZE1_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_0_01_RD_SIZE2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_0_01_RD_SIZE2_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_0_01_RD_SIZE3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_0_01_RD_SIZE3_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_1_01_RD_SIZE2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_1_01_RD_SIZE2_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_1_01_RD_SIZE3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_1_01_RD_SIZE3_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_2_23_RD_SIZE2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_2_23_RD_SIZE2_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_2_23_RD_SIZE3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_2_23_RD_SIZE3_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_3_23_RD_SIZE2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_3_23_RD_SIZE2_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_3_23_RD_SIZE3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_3_23_RD_SIZE3_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_4_4_RD_SIZE2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_4_4_RD_SIZE2_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_4_4_RD_SIZE3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_4_4_RD_SIZE3_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_0_01_RD_SIZE4 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_0_01_RD_SIZE4_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_0_01_RD_SIZE5 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_0_01_RD_SIZE5_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_1_01_RD_SIZE4 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_1_01_RD_SIZE4_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_1_01_RD_SIZE5 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_1_01_RD_SIZE5_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_2_23_RD_SIZE4 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_2_23_RD_SIZE4_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_2_23_RD_SIZE5 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_2_23_RD_SIZE5_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_3_23_RD_SIZE4 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_3_23_RD_SIZE4_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_3_23_RD_SIZE5 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_3_23_RD_SIZE5_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_4_4_RD_SIZE4 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_4_4_RD_SIZE4_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_4_4_RD_SIZE5 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_4_4_RD_SIZE5_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_0_01_RD_SIZE6 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_0_01_RD_SIZE6_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_0_01_RD = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_0_01_RD_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_1_01_RD_SIZE6 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_1_01_RD_SIZE6_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_1_01_RD = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_1_01_RD_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_2_23_RD_SIZE6 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_2_23_RD_SIZE6_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_2_23_RD = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_2_23_RD_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_3_23_RD_SIZE6 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_3_23_RD_SIZE6_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_3_23_RD = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_3_23_RD_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_4_4_RD_SIZE6 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_4_4_RD_SIZE6_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_4_4_RD = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_4_4_RD_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_0_01_RD_SIZE0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_0_01_RD_SIZE0_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_0_01_RD_SIZE1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_0_01_RD_SIZE1_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_1_01_RD_SIZE0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_1_01_RD_SIZE0_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_1_01_RD_SIZE1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_1_01_RD_SIZE1_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_2_23_RD_SIZE0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_2_23_RD_SIZE0_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_2_23_RD_SIZE1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_2_23_RD_SIZE1_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_3_23_RD_SIZE0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_3_23_RD_SIZE0_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_3_23_RD_SIZE1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_3_23_RD_SIZE1_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_4_4_RD_SIZE0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_4_4_RD_SIZE0_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_4_4_RD_SIZE1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_4_4_RD_SIZE1_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_0_01_RD_SIZE2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_0_01_RD_SIZE2_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_0_01_RD_SIZE3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_0_01_RD_SIZE3_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_1_01_RD_SIZE2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_1_01_RD_SIZE2_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_1_01_RD_SIZE3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_1_01_RD_SIZE3_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_2_23_RD_SIZE2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_2_23_RD_SIZE2_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_2_23_RD_SIZE3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_2_23_RD_SIZE3_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_3_23_RD_SIZE2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_3_23_RD_SIZE2_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_3_23_RD_SIZE3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_3_23_RD_SIZE3_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_4_4_RD_SIZE2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_4_4_RD_SIZE2_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_4_4_RD_SIZE3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_4_4_RD_SIZE3_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_0_01_RD_SIZE4 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_0_01_RD_SIZE4_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_0_01_RD_SIZE5 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_0_01_RD_SIZE5_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_1_01_RD_SIZE4 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_1_01_RD_SIZE4_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_1_01_RD_SIZE5 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_1_01_RD_SIZE5_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_2_23_RD_SIZE4 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_2_23_RD_SIZE4_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_2_23_RD_SIZE5 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_2_23_RD_SIZE5_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_3_23_RD_SIZE4 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_3_23_RD_SIZE4_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_3_23_RD_SIZE5 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_3_23_RD_SIZE5_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_4_4_RD_SIZE4 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_4_4_RD_SIZE4_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_4_4_RD_SIZE5 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_4_4_RD_SIZE5_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_0_01_RD_SIZE6 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_0_01_RD_SIZE6_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_0_01_RD_SIZE7 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_0_01_RD_SIZE7_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_1_01_RD_SIZE6 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_1_01_RD_SIZE6_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_1_01_RD_SIZE7 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_1_01_RD_SIZE7_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_2_23_RD_SIZE6 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_2_23_RD_SIZE6_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_2_23_RD_SIZE7 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_2_23_RD_SIZE7_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_3_23_RD_SIZE6 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_3_23_RD_SIZE6_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_3_23_RD_SIZE7 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_3_23_RD_SIZE7_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_4_4_RD_SIZE6 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_4_4_RD_SIZE6_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_4_4_RD_SIZE7 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_4_4_RD_SIZE7_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_0_01_RD_SIZE0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_0_01_RD_SIZE0_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_0_01_RD_SIZE1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_0_01_RD_SIZE1_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_1_01_RD_SIZE0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_1_01_RD_SIZE0_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_1_01_RD_SIZE1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_1_01_RD_SIZE1_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_2_23_RD_SIZE0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_2_23_RD_SIZE0_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_2_23_RD_SIZE1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_2_23_RD_SIZE1_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_3_23_RD_SIZE0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_3_23_RD_SIZE0_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_3_23_RD_SIZE1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_3_23_RD_SIZE1_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_4_4_RD_SIZE0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_4_4_RD_SIZE0_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_4_4_RD_SIZE1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_4_4_RD_SIZE1_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_0_01_RD_SIZE2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_0_01_RD_SIZE2_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_0_01_RD_SIZE3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_0_01_RD_SIZE3_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_1_01_RD_SIZE2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_1_01_RD_SIZE2_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_1_01_RD_SIZE3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_1_01_RD_SIZE3_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_2_23_RD_SIZE2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_2_23_RD_SIZE2_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_2_23_RD_SIZE3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_2_23_RD_SIZE3_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_3_23_RD_SIZE2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_3_23_RD_SIZE2_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_3_23_RD_SIZE3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_3_23_RD_SIZE3_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_4_4_RD_SIZE2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_4_4_RD_SIZE2_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_4_4_RD_SIZE3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_4_4_RD_SIZE3_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_0_01_RD_SIZE4 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_0_01_RD_SIZE4_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_0_01_RD_SIZE5 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_0_01_RD_SIZE5_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_1_01_RD_SIZE4 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_1_01_RD_SIZE4_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_1_01_RD_SIZE5 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_1_01_RD_SIZE5_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_2_23_RD_SIZE4 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_2_23_RD_SIZE4_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_2_23_RD_SIZE5 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_2_23_RD_SIZE5_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_3_23_RD_SIZE4 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_3_23_RD_SIZE4_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_3_23_RD_SIZE5 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_3_23_RD_SIZE5_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_4_4_RD_SIZE4 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_4_4_RD_SIZE4_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_4_4_RD_SIZE5 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_4_4_RD_SIZE5_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_0_01_RD_SIZE6 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_0_01_RD_SIZE6_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_0_01_RD_SIZE7 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_0_01_RD_SIZE7_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_1_01_RD_SIZE6 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_1_01_RD_SIZE6_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_1_01_RD_SIZE7 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_1_01_RD_SIZE7_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_2_23_RD_SIZE6 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_2_23_RD_SIZE6_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_2_23_RD_SIZE7 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_2_23_RD_SIZE7_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_3_23_RD_SIZE6 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_3_23_RD_SIZE6_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_3_23_RD_SIZE7 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_3_23_RD_SIZE7_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_4_4_RD_SIZE6 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_4_4_RD_SIZE6_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_4_4_RD_SIZE7 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_4_4_RD_SIZE7_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_0_01 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_0_01_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_0_01_REFERENCE1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_0_01_REFERENCE1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_1_01 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_1_01_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_1_01_REFERENCE1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_1_01_REFERENCE1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_2_23 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_2_23_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_2_23_REFERENCE1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_2_23_REFERENCE1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_3_23 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_3_23_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_3_23_REFERENCE1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_3_23_REFERENCE1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_4_4 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_4_4_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_4_4_REFERENCE1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_4_4_REFERENCE1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_0_01_REFERENCE2 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_0_01_REFERENCE2_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_0_01_REFERENCE3 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_0_01_REFERENCE3_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_1_01_REFERENCE2 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_1_01_REFERENCE2_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_1_01_REFERENCE3 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_1_01_REFERENCE3_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_2_23_REFERENCE2 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_2_23_REFERENCE2_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_2_23_REFERENCE3 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_2_23_REFERENCE3_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_3_23_REFERENCE2 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_3_23_REFERENCE2_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_3_23_REFERENCE3 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_3_23_REFERENCE3_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_4_4_REFERENCE2 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_4_4_REFERENCE2_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_4_4_REFERENCE3 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_4_4_REFERENCE3_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_0_01_NIB0TCFLIP_DC = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_0_01_NIB1TCFLIP_DC = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_0_01_NIB2TCFLIP_DC = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_0_01_NIB3TCFLIP_DC = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_0_01_DD2_MCTERM_FIX_DISABLE = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_0_01_DD2_COARSE_ALN_FIX_DISABLE = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_0_01_DD2_RESET_READ_FIX_DISABLE = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_0_01_DD2_RDFIFO_CG_DISABLE = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_0_01_DD2_RDCNTL_CG_DISABLE = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_0_01_DD2_WRCNTL_CG_DISABLE = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_0_01_DD2_PARERROR_FIX_DISABLE = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_0_01_DISABLE_TERMINATION = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_0_01_READ_CENTERING_MODE = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_0_01_READ_CENTERING_MODE_LEN = 2 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_1_01_NIB0TCFLIP_DC = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_1_01_NIB1TCFLIP_DC = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_1_01_NIB2TCFLIP_DC = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_1_01_NIB3TCFLIP_DC = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_1_01_DD2_MCTERM_FIX_DISABLE = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_1_01_DD2_COARSE_ALN_FIX_DISABLE = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_1_01_DD2_RESET_READ_FIX_DISABLE = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_1_01_DD2_RDFIFO_CG_DISABLE = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_1_01_DD2_RDCNTL_CG_DISABLE = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_1_01_DD2_WRCNTL_CG_DISABLE = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_1_01_DD2_PARERROR_FIX_DISABLE = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_1_01_DISABLE_TERMINATION = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_1_01_READ_CENTERING_MODE = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_1_01_READ_CENTERING_MODE_LEN = 2 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_2_23_NIB0TCFLIP_DC = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_2_23_NIB1TCFLIP_DC = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_2_23_NIB2TCFLIP_DC = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_2_23_NIB3TCFLIP_DC = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_2_23_DD2_MCTERM_FIX_DISABLE = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_2_23_DD2_COARSE_ALN_FIX_DISABLE = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_2_23_DD2_RESET_READ_FIX_DISABLE = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_2_23_DD2_RDFIFO_CG_DISABLE = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_2_23_DD2_RDCNTL_CG_DISABLE = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_2_23_DD2_WRCNTL_CG_DISABLE = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_2_23_DD2_PARERROR_FIX_DISABLE = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_2_23_DISABLE_TERMINATION = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_2_23_READ_CENTERING_MODE = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_2_23_READ_CENTERING_MODE_LEN = 2 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_3_23_NIB0TCFLIP_DC = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_3_23_NIB1TCFLIP_DC = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_3_23_NIB2TCFLIP_DC = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_3_23_NIB3TCFLIP_DC = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_3_23_DD2_MCTERM_FIX_DISABLE = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_3_23_DD2_COARSE_ALN_FIX_DISABLE = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_3_23_DD2_RESET_READ_FIX_DISABLE = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_3_23_DD2_RDFIFO_CG_DISABLE = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_3_23_DD2_RDCNTL_CG_DISABLE = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_3_23_DD2_WRCNTL_CG_DISABLE = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_3_23_DD2_PARERROR_FIX_DISABLE = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_3_23_DISABLE_TERMINATION = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_3_23_READ_CENTERING_MODE = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_3_23_READ_CENTERING_MODE_LEN = 2 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_4_4_NIB0TCFLIP_DC = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_4_4_NIB1TCFLIP_DC = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_4_4_NIB2TCFLIP_DC = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_4_4_NIB3TCFLIP_DC = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_4_4_DD2_MCTERM_FIX_DISABLE = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_4_4_DD2_COARSE_ALN_FIX_DISABLE = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_4_4_DD2_RESET_READ_FIX_DISABLE = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_4_4_DD2_RDFIFO_CG_DISABLE = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_4_4_DD2_RDCNTL_CG_DISABLE = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_4_4_DD2_WRCNTL_CG_DISABLE = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_4_4_DD2_PARERROR_FIX_DISABLE = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_4_4_DISABLE_TERMINATION = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_4_4_READ_CENTERING_MODE = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_4_4_READ_CENTERING_MODE_LEN = 2 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_0_01_ROT_OVERRIDE = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_0_01_ROT_OVERRIDE_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_0_01_ROT_OVERRIDE_EN = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_0_01_PHASE_ALIGN_RESET = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_0_01_PHASE_CNTL_EN = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_0_01_PHASE_DEFAULT_EN = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_0_01_POS_EDGE_ALIGN = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_0_01_CONTINUOUS_UPDATE = 61 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_1_01_ROT_OVERRIDE = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_1_01_ROT_OVERRIDE_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_1_01_ROT_OVERRIDE_EN = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_1_01_PHASE_ALIGN_RESET = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_1_01_PHASE_CNTL_EN = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_1_01_PHASE_DEFAULT_EN = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_1_01_POS_EDGE_ALIGN = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_1_01_CONTINUOUS_UPDATE = 61 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_2_23_ROT_OVERRIDE = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_2_23_ROT_OVERRIDE_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_2_23_ROT_OVERRIDE_EN = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_2_23_PHASE_ALIGN_RESET = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_2_23_PHASE_CNTL_EN = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_2_23_PHASE_DEFAULT_EN = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_2_23_POS_EDGE_ALIGN = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_2_23_CONTINUOUS_UPDATE = 61 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_3_23_ROT_OVERRIDE = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_3_23_ROT_OVERRIDE_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_3_23_ROT_OVERRIDE_EN = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_3_23_PHASE_ALIGN_RESET = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_3_23_PHASE_CNTL_EN = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_3_23_PHASE_DEFAULT_EN = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_3_23_POS_EDGE_ALIGN = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_3_23_CONTINUOUS_UPDATE = 61 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_4_4_ROT_OVERRIDE = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_4_4_ROT_OVERRIDE_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_4_4_ROT_OVERRIDE_EN = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_4_4_PHASE_ALIGN_RESET = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_4_4_PHASE_CNTL_EN = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_4_4_PHASE_DEFAULT_EN = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_4_4_POS_EDGE_ALIGN = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_4_4_CONTINUOUS_UPDATE = 61 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_0_01_ROT_OVERRIDE = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_0_01_ROT_OVERRIDE_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_0_01_ROT_OVERRIDE_EN = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_0_01_PHASE_ALIGN_RESET = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_0_01_PHASE_CNTL_EN = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_0_01_PHASE_DEFAULT_EN = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_0_01_POS_EDGE_ALIGN = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_0_01_CONTINUOUS_UPDATE = 61 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_1_01_ROT_OVERRIDE = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_1_01_ROT_OVERRIDE_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_1_01_ROT_OVERRIDE_EN = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_1_01_PHASE_ALIGN_RESET = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_1_01_PHASE_CNTL_EN = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_1_01_PHASE_DEFAULT_EN = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_1_01_POS_EDGE_ALIGN = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_1_01_CONTINUOUS_UPDATE = 61 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_2_23_ROT_OVERRIDE = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_2_23_ROT_OVERRIDE_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_2_23_ROT_OVERRIDE_EN = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_2_23_PHASE_ALIGN_RESET = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_2_23_PHASE_CNTL_EN = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_2_23_PHASE_DEFAULT_EN = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_2_23_POS_EDGE_ALIGN = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_2_23_CONTINUOUS_UPDATE = 61 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_3_23_ROT_OVERRIDE = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_3_23_ROT_OVERRIDE_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_3_23_ROT_OVERRIDE_EN = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_3_23_PHASE_ALIGN_RESET = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_3_23_PHASE_CNTL_EN = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_3_23_PHASE_DEFAULT_EN = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_3_23_POS_EDGE_ALIGN = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_3_23_CONTINUOUS_UPDATE = 61 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_4_4_ROT_OVERRIDE = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_4_4_ROT_OVERRIDE_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_4_4_ROT_OVERRIDE_EN = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_4_4_PHASE_ALIGN_RESET = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_4_4_PHASE_CNTL_EN = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_4_4_PHASE_DEFAULT_EN = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_4_4_POS_EDGE_ALIGN = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_4_4_CONTINUOUS_UPDATE = 61 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_0_01_BB_LOCK0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_0_01_ROT0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_0_01_ROT0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_0_01_BB_LOCK1 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_0_01_ROT1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_0_01_ROT1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_1_01_BB_LOCK0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_1_01_ROT0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_1_01_ROT0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_1_01_BB_LOCK1 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_1_01_ROT1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_1_01_ROT1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_2_23_BB_LOCK0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_2_23_ROT0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_2_23_ROT0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_2_23_BB_LOCK1 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_2_23_ROT1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_2_23_ROT1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_3_23_BB_LOCK0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_3_23_ROT0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_3_23_ROT0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_3_23_BB_LOCK1 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_3_23_ROT1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_3_23_ROT1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_4_4_BB_LOCK0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_4_4_ROT0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_4_4_ROT0_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_4_4_BB_LOCK1 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_4_4_ROT1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_4_4_ROT1_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_0_01_QUAD0_CLK16 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_0_01_QUAD1_CLK16 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_0_01_QUAD0_CLK18 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_0_01_QUAD1_CLK18 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_0_01_QUAD2_CLK20 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_0_01_QUAD3_CLK20 = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_0_01_QUAD2_CLK22 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_0_01_QUAD3_CLK22 = 57 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_1_01_QUAD0_CLK16 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_1_01_QUAD1_CLK16 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_1_01_QUAD0_CLK18 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_1_01_QUAD1_CLK18 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_1_01_QUAD2_CLK20 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_1_01_QUAD3_CLK20 = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_1_01_QUAD2_CLK22 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_1_01_QUAD3_CLK22 = 57 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_2_23_QUAD0_CLK16 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_2_23_QUAD1_CLK16 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_2_23_QUAD0_CLK18 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_2_23_QUAD1_CLK18 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_2_23_QUAD2_CLK20 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_2_23_QUAD3_CLK20 = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_2_23_QUAD2_CLK22 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_2_23_QUAD3_CLK22 = 57 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_3_23_QUAD0_CLK16 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_3_23_QUAD1_CLK16 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_3_23_QUAD0_CLK18 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_3_23_QUAD1_CLK18 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_3_23_QUAD2_CLK20 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_3_23_QUAD3_CLK20 = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_3_23_QUAD2_CLK22 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_3_23_QUAD3_CLK22 = 57 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_4_4_QUAD0_CLK16 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_4_4_QUAD1_CLK16 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_4_4_QUAD0_CLK18 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_4_4_QUAD1_CLK18 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_4_4_QUAD2_CLK20 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_4_4_QUAD3_CLK20 = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_4_4_QUAD2_CLK22 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_4_4_QUAD3_CLK22 = 57 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_0_01_QUAD0_CLK16 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_0_01_QUAD1_CLK16 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_0_01_QUAD0_CLK18 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_0_01_QUAD1_CLK18 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_0_01_QUAD2_CLK20 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_0_01_QUAD3_CLK20 = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_0_01_QUAD2_CLK22 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_0_01_QUAD3_CLK22 = 57 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_1_01_QUAD0_CLK16 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_1_01_QUAD1_CLK16 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_1_01_QUAD0_CLK18 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_1_01_QUAD1_CLK18 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_1_01_QUAD2_CLK20 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_1_01_QUAD3_CLK20 = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_1_01_QUAD2_CLK22 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_1_01_QUAD3_CLK22 = 57 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_2_23_QUAD0_CLK16 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_2_23_QUAD1_CLK16 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_2_23_QUAD0_CLK18 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_2_23_QUAD1_CLK18 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_2_23_QUAD2_CLK20 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_2_23_QUAD3_CLK20 = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_2_23_QUAD2_CLK22 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_2_23_QUAD3_CLK22 = 57 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_3_23_QUAD0_CLK16 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_3_23_QUAD1_CLK16 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_3_23_QUAD0_CLK18 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_3_23_QUAD1_CLK18 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_3_23_QUAD2_CLK20 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_3_23_QUAD3_CLK20 = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_3_23_QUAD2_CLK22 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_3_23_QUAD3_CLK22 = 57 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_4_4_QUAD0_CLK16 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_4_4_QUAD1_CLK16 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_4_4_QUAD0_CLK18 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_4_4_QUAD1_CLK18 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_4_4_QUAD2_CLK20 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_4_4_QUAD3_CLK20 = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_4_4_QUAD2_CLK22 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_4_4_QUAD3_CLK22 = 57 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_0_01_QUAD0_CLK16 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_0_01_QUAD1_CLK16 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_0_01_QUAD0_CLK18 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_0_01_QUAD1_CLK18 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_0_01_QUAD2_CLK20 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_0_01_QUAD3_CLK20 = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_0_01_QUAD2_CLK22 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_0_01_QUAD3_CLK22 = 57 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_1_01_QUAD0_CLK16 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_1_01_QUAD1_CLK16 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_1_01_QUAD0_CLK18 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_1_01_QUAD1_CLK18 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_1_01_QUAD2_CLK20 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_1_01_QUAD3_CLK20 = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_1_01_QUAD2_CLK22 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_1_01_QUAD3_CLK22 = 57 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_2_23_QUAD0_CLK16 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_2_23_QUAD1_CLK16 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_2_23_QUAD0_CLK18 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_2_23_QUAD1_CLK18 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_2_23_QUAD2_CLK20 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_2_23_QUAD3_CLK20 = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_2_23_QUAD2_CLK22 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_2_23_QUAD3_CLK22 = 57 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_3_23_QUAD0_CLK16 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_3_23_QUAD1_CLK16 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_3_23_QUAD0_CLK18 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_3_23_QUAD1_CLK18 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_3_23_QUAD2_CLK20 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_3_23_QUAD3_CLK20 = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_3_23_QUAD2_CLK22 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_3_23_QUAD3_CLK22 = 57 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_4_4_QUAD0_CLK16 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_4_4_QUAD1_CLK16 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_4_4_QUAD0_CLK18 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_4_4_QUAD1_CLK18 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_4_4_QUAD2_CLK20 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_4_4_QUAD3_CLK20 = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_4_4_QUAD2_CLK22 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_4_4_QUAD3_CLK22 = 57 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_0_01_QUAD0_CLK16 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_0_01_QUAD1_CLK16 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_0_01_QUAD0_CLK18 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_0_01_QUAD1_CLK18 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_0_01_QUAD2_CLK20 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_0_01_QUAD3_CLK20 = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_0_01_QUAD2_CLK22 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_0_01_QUAD3_CLK22 = 57 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_1_01_QUAD0_CLK16 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_1_01_QUAD1_CLK16 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_1_01_QUAD0_CLK18 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_1_01_QUAD1_CLK18 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_1_01_QUAD2_CLK20 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_1_01_QUAD3_CLK20 = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_1_01_QUAD2_CLK22 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_1_01_QUAD3_CLK22 = 57 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_2_23_QUAD0_CLK16 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_2_23_QUAD1_CLK16 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_2_23_QUAD0_CLK18 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_2_23_QUAD1_CLK18 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_2_23_QUAD2_CLK20 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_2_23_QUAD3_CLK20 = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_2_23_QUAD2_CLK22 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_2_23_QUAD3_CLK22 = 57 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_3_23_QUAD0_CLK16 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_3_23_QUAD1_CLK16 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_3_23_QUAD0_CLK18 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_3_23_QUAD1_CLK18 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_3_23_QUAD2_CLK20 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_3_23_QUAD3_CLK20 = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_3_23_QUAD2_CLK22 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_3_23_QUAD3_CLK22 = 57 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_4_4_QUAD0_CLK16 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_4_4_QUAD1_CLK16 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_4_4_QUAD0_CLK18 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_4_4_QUAD1_CLK18 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_4_4_QUAD2_CLK20 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_4_4_QUAD3_CLK20 = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_4_4_QUAD2_CLK22 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_4_4_QUAD3_CLK22 = 57 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_PR_P0_0_01_TSYS = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_PR_P0_0_01_TSYS_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_PR_P0_1_01_TSYS = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_PR_P0_1_01_TSYS_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_PR_P0_2_23_TSYS = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_PR_P0_2_23_TSYS_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_PR_P0_3_23_TSYS = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_PR_P0_3_23_TSYS_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_PR_P0_4_4_TSYS = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_PR_P0_4_4_TSYS_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_0_01_BIT_CENTERED = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_0_01_BIT_CENTERED_LEN = 5 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_0_01_SMALL_STEP_LEFT = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_0_01_BIG_STEP_RIGHT = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_0_01_MATCH_STEP_RIGHT = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_0_01_JUMP_BACK_RIGHT = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_0_01_SMALL_STEP_RIGHT = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_0_01_DONE = 58 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_1_01_BIT_CENTERED = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_1_01_BIT_CENTERED_LEN = 5 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_1_01_SMALL_STEP_LEFT = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_1_01_BIG_STEP_RIGHT = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_1_01_MATCH_STEP_RIGHT = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_1_01_JUMP_BACK_RIGHT = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_1_01_SMALL_STEP_RIGHT = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_1_01_DONE = 58 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_2_23_BIT_CENTERED = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_2_23_BIT_CENTERED_LEN = 5 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_2_23_SMALL_STEP_LEFT = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_2_23_BIG_STEP_RIGHT = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_2_23_MATCH_STEP_RIGHT = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_2_23_JUMP_BACK_RIGHT = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_2_23_SMALL_STEP_RIGHT = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_2_23_DONE = 58 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_3_23_BIT_CENTERED = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_3_23_BIT_CENTERED_LEN = 5 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_3_23_SMALL_STEP_LEFT = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_3_23_BIG_STEP_RIGHT = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_3_23_MATCH_STEP_RIGHT = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_3_23_JUMP_BACK_RIGHT = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_3_23_SMALL_STEP_RIGHT = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_3_23_DONE = 58 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_4_4_BIT_CENTERED = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_4_4_BIT_CENTERED_LEN = 5 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_4_4_SMALL_STEP_LEFT = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_4_4_BIG_STEP_RIGHT = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_4_4_MATCH_STEP_RIGHT = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_4_4_JUMP_BACK_RIGHT = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_4_4_SMALL_STEP_RIGHT = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_4_4_DONE = 58 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS1_P0_0_01_FW_LEFT_SIDE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS1_P0_0_01_FW_LEFT_SIDE_LEN = 11 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS1_P0_1_01_FW_LEFT_SIDE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS1_P0_1_01_FW_LEFT_SIDE_LEN = 11 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS1_P0_2_23_FW_LEFT_SIDE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS1_P0_2_23_FW_LEFT_SIDE_LEN = 11 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS1_P0_3_23_FW_LEFT_SIDE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS1_P0_3_23_FW_LEFT_SIDE_LEN = 11 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS1_P0_4_4_FW_LEFT_SIDE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS1_P0_4_4_FW_LEFT_SIDE_LEN = 11 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS2_P0_0_01_FW_RIGHT_SIDE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS2_P0_0_01_FW_RIGHT_SIDE_LEN = 11 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS2_P0_1_01_FW_RIGHT_SIDE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS2_P0_1_01_FW_RIGHT_SIDE_LEN = 11 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS2_P0_2_23_FW_RIGHT_SIDE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS2_P0_2_23_FW_RIGHT_SIDE_LEN = 11 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS2_P0_3_23_FW_RIGHT_SIDE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS2_P0_3_23_FW_RIGHT_SIDE_LEN = 11 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS2_P0_4_4_FW_RIGHT_SIDE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS2_P0_4_4_FW_RIGHT_SIDE_LEN = 11 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP0_P0_0_01_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP0_P0_0_01_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP0_P0_1_01_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP0_P0_1_01_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP0_P0_2_23_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP0_P0_2_23_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP0_P0_3_23_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP0_P0_3_23_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP0_P0_4_4_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP0_P0_4_4_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP1_P0_0_01_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP1_P0_0_01_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP1_P0_1_01_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP1_P0_1_01_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP1_P0_2_23_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP1_P0_2_23_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP1_P0_3_23_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP1_P0_3_23_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP1_P0_4_4_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP1_P0_4_4_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP2_P0_0_01_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP2_P0_0_01_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP2_P0_1_01_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP2_P0_1_01_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP2_P0_2_23_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP2_P0_2_23_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP2_P0_3_23_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP2_P0_3_23_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP2_P0_4_4_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP2_P0_4_4_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP3_P0_0_01_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP3_P0_0_01_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP3_P0_1_01_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP3_P0_1_01_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP3_P0_2_23_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP3_P0_2_23_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP3_P0_3_23_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP3_P0_3_23_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP3_P0_4_4_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP3_P0_4_4_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP0_P0_0_01_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP0_P0_0_01_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP0_P0_1_01_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP0_P0_1_01_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP0_P0_2_23_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP0_P0_2_23_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP0_P0_3_23_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP0_P0_3_23_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP0_P0_4_4_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP0_P0_4_4_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP1_P0_0_01_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP1_P0_0_01_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP1_P0_1_01_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP1_P0_1_01_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP1_P0_2_23_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP1_P0_2_23_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP1_P0_3_23_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP1_P0_3_23_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP1_P0_4_4_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP1_P0_4_4_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP2_P0_0_01_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP2_P0_0_01_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP2_P0_1_01_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP2_P0_1_01_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP2_P0_2_23_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP2_P0_2_23_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP2_P0_3_23_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP2_P0_3_23_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP2_P0_4_4_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP2_P0_4_4_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP3_P0_0_01_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP3_P0_0_01_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP3_P0_1_01_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP3_P0_1_01_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP3_P0_2_23_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP3_P0_2_23_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP3_P0_3_23_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP3_P0_3_23_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP3_P0_4_4_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP3_P0_4_4_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP0_P0_0_01_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP0_P0_0_01_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP0_P0_1_01_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP0_P0_1_01_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP0_P0_2_23_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP0_P0_2_23_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP0_P0_3_23_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP0_P0_3_23_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP0_P0_4_4_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP0_P0_4_4_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP1_P0_0_01_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP1_P0_0_01_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP1_P0_1_01_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP1_P0_1_01_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP1_P0_2_23_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP1_P0_2_23_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP1_P0_3_23_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP1_P0_3_23_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP1_P0_4_4_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP1_P0_4_4_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP2_P0_0_01_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP2_P0_0_01_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP2_P0_1_01_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP2_P0_1_01_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP2_P0_2_23_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP2_P0_2_23_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP2_P0_3_23_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP2_P0_3_23_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP2_P0_4_4_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP2_P0_4_4_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP3_P0_0_01_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP3_P0_0_01_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP3_P0_1_01_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP3_P0_1_01_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP3_P0_2_23_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP3_P0_2_23_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP3_P0_3_23_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP3_P0_3_23_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP3_P0_4_4_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP3_P0_4_4_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP0_P0_0_01_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP0_P0_0_01_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP0_P0_1_01_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP0_P0_1_01_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP0_P0_2_23_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP0_P0_2_23_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP0_P0_3_23_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP0_P0_3_23_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP0_P0_4_4_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP0_P0_4_4_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP1_P0_0_01_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP1_P0_0_01_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP1_P0_1_01_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP1_P0_1_01_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP1_P0_2_23_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP1_P0_2_23_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP1_P0_3_23_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP1_P0_3_23_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP1_P0_4_4_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP1_P0_4_4_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP2_P0_0_01_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP2_P0_0_01_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP2_P0_1_01_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP2_P0_1_01_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP2_P0_2_23_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP2_P0_2_23_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP2_P0_3_23_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP2_P0_3_23_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP2_P0_4_4_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP2_P0_4_4_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP3_P0_0_01_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP3_P0_0_01_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP3_P0_1_01_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP3_P0_1_01_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP3_P0_2_23_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP3_P0_2_23_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP3_P0_3_23_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP3_P0_3_23_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP3_P0_4_4_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP3_P0_4_4_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP0_P0_0_01_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP0_P0_0_01_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP0_P0_1_01_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP0_P0_1_01_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP0_P0_2_23_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP0_P0_2_23_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP0_P0_3_23_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP0_P0_3_23_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP0_P0_4_4_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP0_P0_4_4_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP1_P0_0_01_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP1_P0_0_01_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP1_P0_1_01_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP1_P0_1_01_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP1_P0_2_23_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP1_P0_2_23_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP1_P0_3_23_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP1_P0_3_23_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP1_P0_4_4_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP1_P0_4_4_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP2_P0_0_01_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP2_P0_0_01_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP2_P0_1_01_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP2_P0_1_01_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP2_P0_2_23_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP2_P0_2_23_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP2_P0_3_23_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP2_P0_3_23_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP2_P0_4_4_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP2_P0_4_4_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP3_P0_0_01_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP3_P0_0_01_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP3_P0_1_01_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP3_P0_1_01_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP3_P0_2_23_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP3_P0_2_23_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP3_P0_3_23_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP3_P0_3_23_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP3_P0_4_4_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP3_P0_4_4_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP0_P0_0_01_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP0_P0_0_01_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP0_P0_1_01_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP0_P0_1_01_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP0_P0_2_23_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP0_P0_2_23_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP0_P0_3_23_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP0_P0_3_23_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP0_P0_4_4_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP0_P0_4_4_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP1_P0_0_01_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP1_P0_0_01_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP1_P0_1_01_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP1_P0_1_01_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP1_P0_2_23_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP1_P0_2_23_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP1_P0_3_23_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP1_P0_3_23_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP1_P0_4_4_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP1_P0_4_4_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP2_P0_0_01_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP2_P0_0_01_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP2_P0_1_01_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP2_P0_1_01_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP2_P0_2_23_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP2_P0_2_23_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP2_P0_3_23_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP2_P0_3_23_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP2_P0_4_4_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP2_P0_4_4_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP3_P0_0_01_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP3_P0_0_01_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP3_P0_1_01_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP3_P0_1_01_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP3_P0_2_23_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP3_P0_2_23_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP3_P0_3_23_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP3_P0_3_23_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP3_P0_4_4_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP3_P0_4_4_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP0_P0_0_01_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP0_P0_0_01_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP0_P0_1_01_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP0_P0_1_01_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP0_P0_2_23_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP0_P0_2_23_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP0_P0_3_23_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP0_P0_3_23_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP0_P0_4_4_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP0_P0_4_4_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP1_P0_0_01_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP1_P0_0_01_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP1_P0_1_01_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP1_P0_1_01_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP1_P0_2_23_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP1_P0_2_23_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP1_P0_3_23_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP1_P0_3_23_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP1_P0_4_4_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP1_P0_4_4_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP2_P0_0_01_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP2_P0_0_01_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP2_P0_1_01_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP2_P0_1_01_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP2_P0_2_23_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP2_P0_2_23_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP2_P0_3_23_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP2_P0_3_23_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP2_P0_4_4_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP2_P0_4_4_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP3_P0_0_01_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP3_P0_0_01_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP3_P0_1_01_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP3_P0_1_01_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP3_P0_2_23_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP3_P0_2_23_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP3_P0_3_23_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP3_P0_3_23_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP3_P0_4_4_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP3_P0_4_4_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP0_P0_0_01_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP0_P0_0_01_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP0_P0_1_01_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP0_P0_1_01_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP0_P0_2_23_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP0_P0_2_23_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP0_P0_3_23_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP0_P0_3_23_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP0_P0_4_4_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP0_P0_4_4_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP1_P0_0_01_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP1_P0_0_01_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP1_P0_1_01_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP1_P0_1_01_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP1_P0_2_23_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP1_P0_2_23_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP1_P0_3_23_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP1_P0_3_23_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP1_P0_4_4_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP1_P0_4_4_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP2_P0_0_01_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP2_P0_0_01_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP2_P0_1_01_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP2_P0_1_01_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP2_P0_2_23_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP2_P0_2_23_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP2_P0_3_23_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP2_P0_3_23_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP2_P0_4_4_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP2_P0_4_4_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP3_P0_0_01_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP3_P0_0_01_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP3_P0_1_01_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP3_P0_1_01_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP3_P0_2_23_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP3_P0_2_23_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP3_P0_3_23_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP3_P0_3_23_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP3_P0_4_4_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP3_P0_4_4_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP0_P0_0_01_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP0_P0_0_01_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP0_P0_1_01_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP0_P0_1_01_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP0_P0_2_23_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP0_P0_2_23_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP0_P0_3_23_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP0_P0_3_23_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP0_P0_4_4_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP0_P0_4_4_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP1_P0_0_01_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP1_P0_0_01_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP1_P0_1_01_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP1_P0_1_01_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP1_P0_2_23_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP1_P0_2_23_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP1_P0_3_23_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP1_P0_3_23_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP1_P0_4_4_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP1_P0_4_4_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP2_P0_0_01_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP2_P0_0_01_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP2_P0_1_01_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP2_P0_1_01_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP2_P0_2_23_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP2_P0_2_23_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP2_P0_3_23_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP2_P0_3_23_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP2_P0_4_4_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP2_P0_4_4_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP3_P0_0_01_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP3_P0_0_01_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP3_P0_1_01_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP3_P0_1_01_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP3_P0_2_23_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP3_P0_2_23_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP3_P0_3_23_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP3_P0_3_23_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP3_P0_4_4_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP3_P0_4_4_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP0_P0_0_01_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP0_P0_0_01_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP0_P0_1_01_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP0_P0_1_01_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP0_P0_2_23_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP0_P0_2_23_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP0_P0_3_23_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP0_P0_3_23_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP0_P0_4_4_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP0_P0_4_4_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP1_P0_0_01_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP1_P0_0_01_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP1_P0_1_01_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP1_P0_1_01_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP1_P0_2_23_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP1_P0_2_23_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP1_P0_3_23_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP1_P0_3_23_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP1_P0_4_4_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP1_P0_4_4_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP2_P0_0_01_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP2_P0_0_01_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP2_P0_1_01_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP2_P0_1_01_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP2_P0_2_23_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP2_P0_2_23_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP2_P0_3_23_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP2_P0_3_23_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP2_P0_4_4_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP2_P0_4_4_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP3_P0_0_01_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP3_P0_0_01_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP3_P0_1_01_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP3_P0_1_01_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP3_P0_2_23_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP3_P0_2_23_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP3_P0_3_23_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP3_P0_3_23_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP3_P0_4_4_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP3_P0_4_4_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP0_P0_0_01_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP0_P0_0_01_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP0_P0_1_01_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP0_P0_1_01_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP0_P0_2_23_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP0_P0_2_23_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP0_P0_3_23_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP0_P0_3_23_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP0_P0_4_4_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP0_P0_4_4_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP1_P0_0_01_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP1_P0_0_01_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP1_P0_1_01_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP1_P0_1_01_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP1_P0_2_23_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP1_P0_2_23_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP1_P0_3_23_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP1_P0_3_23_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP1_P0_4_4_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP1_P0_4_4_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP2_P0_0_01_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP2_P0_0_01_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP2_P0_1_01_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP2_P0_1_01_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP2_P0_2_23_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP2_P0_2_23_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP2_P0_3_23_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP2_P0_3_23_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP2_P0_4_4_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP2_P0_4_4_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP3_P0_0_01_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP3_P0_0_01_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP3_P0_1_01_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP3_P0_1_01_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP3_P0_2_23_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP3_P0_2_23_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP3_P0_3_23_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP3_P0_3_23_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP3_P0_4_4_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP3_P0_4_4_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP0_P0_0_01_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP0_P0_0_01_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP0_P0_1_01_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP0_P0_1_01_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP0_P0_2_23_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP0_P0_2_23_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP0_P0_3_23_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP0_P0_3_23_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP0_P0_4_4_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP0_P0_4_4_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP1_P0_0_01_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP1_P0_0_01_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP1_P0_1_01_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP1_P0_1_01_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP1_P0_2_23_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP1_P0_2_23_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP1_P0_3_23_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP1_P0_3_23_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP1_P0_4_4_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP1_P0_4_4_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP2_P0_0_01_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP2_P0_0_01_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP2_P0_1_01_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP2_P0_1_01_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP2_P0_2_23_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP2_P0_2_23_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP2_P0_3_23_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP2_P0_3_23_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP2_P0_4_4_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP2_P0_4_4_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP3_P0_0_01_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP3_P0_0_01_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP3_P0_1_01_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP3_P0_1_01_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP3_P0_2_23_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP3_P0_2_23_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP3_P0_3_23_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP3_P0_3_23_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP3_P0_4_4_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP3_P0_4_4_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP0_P0_0_01_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP0_P0_0_01_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP0_P0_1_01_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP0_P0_1_01_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP0_P0_2_23_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP0_P0_2_23_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP0_P0_3_23_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP0_P0_3_23_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP0_P0_4_4_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP0_P0_4_4_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP1_P0_0_01_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP1_P0_0_01_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP1_P0_1_01_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP1_P0_1_01_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP1_P0_2_23_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP1_P0_2_23_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP1_P0_3_23_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP1_P0_3_23_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP1_P0_4_4_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP1_P0_4_4_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP2_P0_0_01_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP2_P0_0_01_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP2_P0_1_01_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP2_P0_1_01_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP2_P0_2_23_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP2_P0_2_23_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP2_P0_3_23_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP2_P0_3_23_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP2_P0_4_4_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP2_P0_4_4_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP3_P0_0_01_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP3_P0_0_01_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP3_P0_1_01_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP3_P0_1_01_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP3_P0_2_23_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP3_P0_2_23_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP3_P0_3_23_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP3_P0_3_23_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP3_P0_4_4_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP3_P0_4_4_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP0_P0_0_01_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP0_P0_0_01_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP0_P0_1_01_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP0_P0_1_01_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP0_P0_2_23_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP0_P0_2_23_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP0_P0_3_23_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP0_P0_3_23_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP0_P0_4_4_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP0_P0_4_4_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP1_P0_0_01_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP1_P0_0_01_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP1_P0_1_01_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP1_P0_1_01_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP1_P0_2_23_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP1_P0_2_23_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP1_P0_3_23_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP1_P0_3_23_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP1_P0_4_4_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP1_P0_4_4_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP2_P0_0_01_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP2_P0_0_01_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP2_P0_1_01_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP2_P0_1_01_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP2_P0_2_23_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP2_P0_2_23_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP2_P0_3_23_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP2_P0_3_23_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP2_P0_4_4_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP2_P0_4_4_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP3_P0_0_01_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP3_P0_0_01_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP3_P0_1_01_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP3_P0_1_01_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP3_P0_2_23_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP3_P0_2_23_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP3_P0_3_23_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP3_P0_3_23_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP3_P0_4_4_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP3_P0_4_4_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP0_P0_0_01_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP0_P0_0_01_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP0_P0_1_01_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP0_P0_1_01_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP0_P0_2_23_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP0_P0_2_23_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP0_P0_3_23_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP0_P0_3_23_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP0_P0_4_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP0_P0_4_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP1_P0_0_01_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP1_P0_0_01_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP1_P0_1_01_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP1_P0_1_01_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP1_P0_2_23_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP1_P0_2_23_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP1_P0_3_23_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP1_P0_3_23_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP1_P0_4_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP1_P0_4_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP2_P0_0_01_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP2_P0_0_01_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP2_P0_1_01_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP2_P0_1_01_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP2_P0_2_23_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP2_P0_2_23_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP2_P0_3_23_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP2_P0_3_23_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP2_P0_4_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP2_P0_4_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP3_P0_0_01_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP3_P0_0_01_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP3_P0_1_01_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP3_P0_1_01_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP3_P0_2_23_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP3_P0_2_23_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP3_P0_3_23_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP3_P0_3_23_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP3_P0_4_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP3_P0_4_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP0_P0_0_01_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP0_P0_0_01_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP0_P0_1_01_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP0_P0_1_01_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP0_P0_2_23_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP0_P0_2_23_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP0_P0_3_23_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP0_P0_3_23_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP0_P0_4_4_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP0_P0_4_4_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP1_P0_0_01_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP1_P0_0_01_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP1_P0_1_01_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP1_P0_1_01_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP1_P0_2_23_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP1_P0_2_23_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP1_P0_3_23_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP1_P0_3_23_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP1_P0_4_4_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP1_P0_4_4_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP2_P0_0_01_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP2_P0_0_01_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP2_P0_1_01_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP2_P0_1_01_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP2_P0_2_23_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP2_P0_2_23_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP2_P0_3_23_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP2_P0_3_23_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP2_P0_4_4_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP2_P0_4_4_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP3_P0_0_01_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP3_P0_0_01_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP3_P0_1_01_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP3_P0_1_01_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP3_P0_2_23_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP3_P0_2_23_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP3_P0_3_23_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP3_P0_3_23_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP3_P0_4_4_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP3_P0_4_4_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP0_P0_0_01_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP0_P0_0_01_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP0_P0_1_01_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP0_P0_1_01_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP0_P0_2_23_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP0_P0_2_23_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP0_P0_3_23_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP0_P0_3_23_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP0_P0_4_4_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP0_P0_4_4_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP1_P0_0_01_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP1_P0_0_01_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP1_P0_1_01_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP1_P0_1_01_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP1_P0_2_23_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP1_P0_2_23_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP1_P0_3_23_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP1_P0_3_23_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP1_P0_4_4_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP1_P0_4_4_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP2_P0_0_01_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP2_P0_0_01_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP2_P0_1_01_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP2_P0_1_01_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP2_P0_2_23_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP2_P0_2_23_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP2_P0_3_23_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP2_P0_3_23_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP2_P0_4_4_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP2_P0_4_4_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP3_P0_0_01_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP3_P0_0_01_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP3_P0_1_01_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP3_P0_1_01_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP3_P0_2_23_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP3_P0_2_23_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP3_P0_3_23_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP3_P0_3_23_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP3_P0_4_4_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP3_P0_4_4_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP0_P0_0_01_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP0_P0_0_01_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP0_P0_1_01_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP0_P0_1_01_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP0_P0_2_23_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP0_P0_2_23_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP0_P0_3_23_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP0_P0_3_23_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP0_P0_4_4_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP0_P0_4_4_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP1_P0_0_01_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP1_P0_0_01_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP1_P0_1_01_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP1_P0_1_01_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP1_P0_2_23_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP1_P0_2_23_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP1_P0_3_23_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP1_P0_3_23_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP1_P0_4_4_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP1_P0_4_4_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP2_P0_0_01_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP2_P0_0_01_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP2_P0_1_01_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP2_P0_1_01_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP2_P0_2_23_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP2_P0_2_23_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP2_P0_3_23_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP2_P0_3_23_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP2_P0_4_4_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP2_P0_4_4_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP3_P0_0_01_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP3_P0_0_01_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP3_P0_1_01_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP3_P0_1_01_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP3_P0_2_23_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP3_P0_2_23_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP3_P0_3_23_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP3_P0_3_23_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP3_P0_4_4_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP3_P0_4_4_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP0_P0_0_01_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP0_P0_0_01_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP0_P0_1_01_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP0_P0_1_01_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP0_P0_2_23_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP0_P0_2_23_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP0_P0_3_23_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP0_P0_3_23_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP0_P0_4_4_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP0_P0_4_4_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP1_P0_0_01_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP1_P0_0_01_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP1_P0_1_01_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP1_P0_1_01_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP1_P0_2_23_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP1_P0_2_23_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP1_P0_3_23_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP1_P0_3_23_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP1_P0_4_4_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP1_P0_4_4_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP2_P0_0_01_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP2_P0_0_01_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP2_P0_1_01_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP2_P0_1_01_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP2_P0_2_23_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP2_P0_2_23_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP2_P0_3_23_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP2_P0_3_23_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP2_P0_4_4_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP2_P0_4_4_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP3_P0_0_01_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP3_P0_0_01_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP3_P0_1_01_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP3_P0_1_01_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP3_P0_2_23_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP3_P0_2_23_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP3_P0_3_23_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP3_P0_3_23_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP3_P0_4_4_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP3_P0_4_4_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP0_P0_0_01_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP0_P0_0_01_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP0_P0_1_01_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP0_P0_1_01_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP0_P0_2_23_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP0_P0_2_23_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP0_P0_3_23_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP0_P0_3_23_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP0_P0_4_4_DELAY0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP0_P0_4_4_DELAY0_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP1_P0_0_01_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP1_P0_0_01_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP1_P0_1_01_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP1_P0_1_01_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP1_P0_2_23_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP1_P0_2_23_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP1_P0_3_23_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP1_P0_3_23_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP1_P0_4_4_DELAY1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP1_P0_4_4_DELAY1_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP2_P0_0_01_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP2_P0_0_01_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP2_P0_1_01_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP2_P0_1_01_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP2_P0_2_23_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP2_P0_2_23_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP2_P0_3_23_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP2_P0_3_23_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP2_P0_4_4_DELAY2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP2_P0_4_4_DELAY2_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP3_P0_0_01_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP3_P0_0_01_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP3_P0_1_01_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP3_P0_1_01_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP3_P0_2_23_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP3_P0_2_23_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP3_P0_3_23_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP3_P0_3_23_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP3_P0_4_4_DELAY3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP3_P0_4_4_DELAY3_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_0_01_WL_ERR_CLK16 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_0_01_WL_ERR_CLK18 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_0_01_WL_ERR_CLK20 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_0_01_WL_ERR_CLK22 = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_0_01_COARSE_ERR_CLK16 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_0_01_COARSE_ERR_CLK18 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_0_01_COARSE_ERR_CLK20 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_0_01_COARSE_ERR_CLK22 = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_0_01_VALID_NS_BIG_L = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_0_01_INVALID_NS_SMALL_L = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_0_01_VALID_NS_BIG_R = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_0_01_INVALID_NS_BIG_R = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_0_01_VALID_NS_JUMP_BACK = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_0_01_INVALID_NS_SMALL_R = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_0_01_OFFSET_ERR = 62 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_1_01_WL_ERR_CLK16 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_1_01_WL_ERR_CLK18 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_1_01_WL_ERR_CLK20 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_1_01_WL_ERR_CLK22 = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_1_01_COARSE_ERR_CLK16 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_1_01_COARSE_ERR_CLK18 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_1_01_COARSE_ERR_CLK20 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_1_01_COARSE_ERR_CLK22 = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_1_01_VALID_NS_BIG_L = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_1_01_INVALID_NS_SMALL_L = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_1_01_VALID_NS_BIG_R = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_1_01_INVALID_NS_BIG_R = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_1_01_VALID_NS_JUMP_BACK = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_1_01_INVALID_NS_SMALL_R = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_1_01_OFFSET_ERR = 62 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_2_23_WL_ERR_CLK16 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_2_23_WL_ERR_CLK18 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_2_23_WL_ERR_CLK20 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_2_23_WL_ERR_CLK22 = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_2_23_COARSE_ERR_CLK16 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_2_23_COARSE_ERR_CLK18 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_2_23_COARSE_ERR_CLK20 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_2_23_COARSE_ERR_CLK22 = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_2_23_VALID_NS_BIG_L = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_2_23_INVALID_NS_SMALL_L = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_2_23_VALID_NS_BIG_R = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_2_23_INVALID_NS_BIG_R = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_2_23_VALID_NS_JUMP_BACK = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_2_23_INVALID_NS_SMALL_R = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_2_23_OFFSET_ERR = 62 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_3_23_WL_ERR_CLK16 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_3_23_WL_ERR_CLK18 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_3_23_WL_ERR_CLK20 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_3_23_WL_ERR_CLK22 = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_3_23_COARSE_ERR_CLK16 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_3_23_COARSE_ERR_CLK18 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_3_23_COARSE_ERR_CLK20 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_3_23_COARSE_ERR_CLK22 = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_3_23_VALID_NS_BIG_L = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_3_23_INVALID_NS_SMALL_L = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_3_23_VALID_NS_BIG_R = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_3_23_INVALID_NS_BIG_R = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_3_23_VALID_NS_JUMP_BACK = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_3_23_INVALID_NS_SMALL_R = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_3_23_OFFSET_ERR = 62 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_4_4_WL_ERR_CLK16 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_4_4_WL_ERR_CLK18 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_4_4_WL_ERR_CLK20 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_4_4_WL_ERR_CLK22 = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_4_4_COARSE_ERR_CLK16 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_4_4_COARSE_ERR_CLK18 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_4_4_COARSE_ERR_CLK20 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_4_4_COARSE_ERR_CLK22 = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_4_4_VALID_NS_BIG_L = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_4_4_INVALID_NS_SMALL_L = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_4_4_VALID_NS_BIG_R = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_4_4_INVALID_NS_BIG_R = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_4_4_VALID_NS_JUMP_BACK = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_4_4_INVALID_NS_SMALL_R = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_4_4_OFFSET_ERR = 62 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_0_01_WL_ERR_CLK16_MASK = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_0_01_WL_ERR_CLK18_MASK = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_0_01_WL_ERR_CLK20_MASK = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_0_01_ERR_CLK22_MASK = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_0_01_VALID_NS_BIG_L_MASK = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_0_01_INVALID_NS_SMALL_L_MASK = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_0_01_VALID_NS_BIG_R_MASK = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_0_01_INVALID_NS_BIG_R_MASK = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_0_01_VALID_NS_JUMP_BACK_MASK = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_0_01_INVALID_NS_SMALL_R_MASK = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_0_01_OFFSET_ERR_MASK = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_0_01_ADVANCE_PR_VALUE = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_1_01_WL_ERR_CLK16_MASK = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_1_01_WL_ERR_CLK18_MASK = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_1_01_WL_ERR_CLK20_MASK = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_1_01_ERR_CLK22_MASK = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_1_01_VALID_NS_BIG_L_MASK = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_1_01_INVALID_NS_SMALL_L_MASK = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_1_01_VALID_NS_BIG_R_MASK = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_1_01_INVALID_NS_BIG_R_MASK = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_1_01_VALID_NS_JUMP_BACK_MASK = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_1_01_INVALID_NS_SMALL_R_MASK = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_1_01_OFFSET_ERR_MASK = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_1_01_ADVANCE_PR_VALUE = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_2_23_WL_ERR_CLK16_MASK = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_2_23_WL_ERR_CLK18_MASK = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_2_23_WL_ERR_CLK20_MASK = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_2_23_ERR_CLK22_MASK = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_2_23_VALID_NS_BIG_L_MASK = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_2_23_INVALID_NS_SMALL_L_MASK = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_2_23_VALID_NS_BIG_R_MASK = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_2_23_INVALID_NS_BIG_R_MASK = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_2_23_VALID_NS_JUMP_BACK_MASK = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_2_23_INVALID_NS_SMALL_R_MASK = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_2_23_OFFSET_ERR_MASK = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_2_23_ADVANCE_PR_VALUE = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_3_23_WL_ERR_CLK16_MASK = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_3_23_WL_ERR_CLK18_MASK = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_3_23_WL_ERR_CLK20_MASK = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_3_23_ERR_CLK22_MASK = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_3_23_VALID_NS_BIG_L_MASK = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_3_23_INVALID_NS_SMALL_L_MASK = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_3_23_VALID_NS_BIG_R_MASK = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_3_23_INVALID_NS_BIG_R_MASK = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_3_23_VALID_NS_JUMP_BACK_MASK = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_3_23_INVALID_NS_SMALL_R_MASK = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_3_23_OFFSET_ERR_MASK = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_3_23_ADVANCE_PR_VALUE = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_4_4_WL_ERR_CLK16_MASK = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_4_4_WL_ERR_CLK18_MASK = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_4_4_WL_ERR_CLK20_MASK = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_4_4_ERR_CLK22_MASK = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_4_4_VALID_NS_BIG_L_MASK = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_4_4_INVALID_NS_SMALL_L_MASK = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_4_4_VALID_NS_BIG_R_MASK = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_4_4_INVALID_NS_BIG_R_MASK = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_4_4_VALID_NS_JUMP_BACK_MASK = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_4_4_INVALID_NS_SMALL_R_MASK = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_4_4_OFFSET_ERR_MASK = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_4_4_ADVANCE_PR_VALUE = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_0_01_CLK_LEVEL = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_0_01_CLK_LEVEL_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_0_01_FINE_STEPPING = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_0_01_DONE = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_0_01_WL_ERR_CLK16 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_0_01_WL_ERR_CLK18 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_0_01_WL_ERR_CLK20 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_0_01_WL_ERR_CLK22 = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_0_01_ZERO_DETECTED = 56 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_1_01_CLK_LEVEL = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_1_01_CLK_LEVEL_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_1_01_FINE_STEPPING = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_1_01_DONE = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_1_01_WL_ERR_CLK16 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_1_01_WL_ERR_CLK18 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_1_01_WL_ERR_CLK20 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_1_01_WL_ERR_CLK22 = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_1_01_ZERO_DETECTED = 56 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_2_23_CLK_LEVEL = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_2_23_CLK_LEVEL_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_2_23_FINE_STEPPING = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_2_23_DONE = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_2_23_WL_ERR_CLK16 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_2_23_WL_ERR_CLK18 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_2_23_WL_ERR_CLK20 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_2_23_WL_ERR_CLK22 = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_2_23_ZERO_DETECTED = 56 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_3_23_CLK_LEVEL = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_3_23_CLK_LEVEL_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_3_23_FINE_STEPPING = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_3_23_DONE = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_3_23_WL_ERR_CLK16 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_3_23_WL_ERR_CLK18 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_3_23_WL_ERR_CLK20 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_3_23_WL_ERR_CLK22 = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_3_23_ZERO_DETECTED = 56 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_4_4_CLK_LEVEL = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_4_4_CLK_LEVEL_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_4_4_FINE_STEPPING = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_4_4_DONE = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_4_4_WL_ERR_CLK16 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_4_4_WL_ERR_CLK18 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_4_4_WL_ERR_CLK20 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_4_4_WL_ERR_CLK22 = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_4_4_ZERO_DETECTED = 56 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_0_01_CTR_1D_MODE_SWITCH = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_0_01_CTR_RUN_FULL_1D = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_0_01_CTR_2D_SMALL_STEP_VAL = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_0_01_CTR_2D_SMALL_STEP_VAL_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_0_01_CTR_2D_BIG_STEP_VAL = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_0_01_CTR_2D_BIG_STEP_VAL_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_0_01_CTR_NUM_BITS_TO_SKIP = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_0_01_CTR_NUM_BITS_TO_SKIP_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_0_01_CTR_NUM_NO_INC_COMP = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_0_01_CTR_NUM_NO_INC_COMP_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_0_01_DD2_FIX_DISABLE = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_1_01_CTR_1D_MODE_SWITCH = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_1_01_CTR_RUN_FULL_1D = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_1_01_CTR_2D_SMALL_STEP_VAL = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_1_01_CTR_2D_SMALL_STEP_VAL_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_1_01_CTR_2D_BIG_STEP_VAL = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_1_01_CTR_2D_BIG_STEP_VAL_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_1_01_CTR_NUM_BITS_TO_SKIP = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_1_01_CTR_NUM_BITS_TO_SKIP_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_1_01_CTR_NUM_NO_INC_COMP = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_1_01_CTR_NUM_NO_INC_COMP_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_1_01_DD2_FIX_DISABLE = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_2_23_CTR_1D_MODE_SWITCH = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_2_23_CTR_RUN_FULL_1D = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_2_23_CTR_2D_SMALL_STEP_VAL = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_2_23_CTR_2D_SMALL_STEP_VAL_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_2_23_CTR_2D_BIG_STEP_VAL = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_2_23_CTR_2D_BIG_STEP_VAL_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_2_23_CTR_NUM_BITS_TO_SKIP = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_2_23_CTR_NUM_BITS_TO_SKIP_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_2_23_CTR_NUM_NO_INC_COMP = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_2_23_CTR_NUM_NO_INC_COMP_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_2_23_DD2_FIX_DISABLE = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_3_23_CTR_1D_MODE_SWITCH = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_3_23_CTR_RUN_FULL_1D = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_3_23_CTR_2D_SMALL_STEP_VAL = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_3_23_CTR_2D_SMALL_STEP_VAL_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_3_23_CTR_2D_BIG_STEP_VAL = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_3_23_CTR_2D_BIG_STEP_VAL_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_3_23_CTR_NUM_BITS_TO_SKIP = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_3_23_CTR_NUM_BITS_TO_SKIP_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_3_23_CTR_NUM_NO_INC_COMP = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_3_23_CTR_NUM_NO_INC_COMP_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_3_23_DD2_FIX_DISABLE = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_4_4_CTR_1D_MODE_SWITCH = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_4_4_CTR_RUN_FULL_1D = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_4_4_CTR_2D_SMALL_STEP_VAL = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_4_4_CTR_2D_SMALL_STEP_VAL_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_4_4_CTR_2D_BIG_STEP_VAL = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_4_4_CTR_2D_BIG_STEP_VAL_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_4_4_CTR_NUM_BITS_TO_SKIP = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_4_4_CTR_NUM_BITS_TO_SKIP_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_4_4_CTR_NUM_NO_INC_COMP = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_4_4_CTR_NUM_NO_INC_COMP_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_4_4_DD2_FIX_DISABLE = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_0_01_CTR_RANGE_SELECT = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_0_01_CTR_RANGE_CROSSOVER = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_0_01_CTR_RANGE_CROSSOVER_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_0_01_CTR_SINGLE_RANGE_MAX = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_0_01_CTR_SINGLE_RANGE_MAX_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_1_01_CTR_RANGE_SELECT = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_1_01_CTR_RANGE_CROSSOVER = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_1_01_CTR_RANGE_CROSSOVER_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_1_01_CTR_SINGLE_RANGE_MAX = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_1_01_CTR_SINGLE_RANGE_MAX_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_2_23_CTR_RANGE_SELECT = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_2_23_CTR_RANGE_CROSSOVER = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_2_23_CTR_RANGE_CROSSOVER_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_2_23_CTR_SINGLE_RANGE_MAX = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_2_23_CTR_SINGLE_RANGE_MAX_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_3_23_CTR_RANGE_SELECT = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_3_23_CTR_RANGE_CROSSOVER = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_3_23_CTR_RANGE_CROSSOVER_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_3_23_CTR_SINGLE_RANGE_MAX = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_3_23_CTR_SINGLE_RANGE_MAX_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_4_4_CTR_RANGE_SELECT = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_4_4_CTR_RANGE_CROSSOVER = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_4_4_CTR_RANGE_CROSSOVER_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_4_4_CTR_SINGLE_RANGE_MAX = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_4_4_CTR_SINGLE_RANGE_MAX_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_MAX_RANGE_ERR0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_MIN_RANGE_ERR0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_TWO_RANGE_BEST_CASE_ERR0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_BIT_STEP_DELTA_ERR0 = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_STEP_RANGE_EDGE_ERR0 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_NO_INCREASE_ERR0 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_1D_EYE_NOISE_ERR0 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_BAD_BIT_ERR0 = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_MAX_RANGE_ERR1 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_MIN_RANGE_ERR1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_TWO_RANGE_BEST_CASE_ERR1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_BIT_STEP_DELTA_ERR1 = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_STEP_RANGE_EDGE_ERR1 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_NO_INCREASE_ERR1 = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_1D_EYE_NOISE_ERR1 = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_BAD_BIT_ERR1 = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_1_01_MAX_RANGE_ERR0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_1_01_MIN_RANGE_ERR0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_1_01_TWO_RANGE_BEST_CASE_ERR0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_1_01_BIT_STEP_DELTA_ERR0 = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_1_01_STEP_RANGE_EDGE_ERR0 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_1_01_NO_INCREASE_ERR0 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_1_01_1D_EYE_NOISE_ERR0 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_1_01_BAD_BIT_ERR0 = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_1_01_MAX_RANGE_ERR1 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_1_01_MIN_RANGE_ERR1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_1_01_TWO_RANGE_BEST_CASE_ERR1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_1_01_BIT_STEP_DELTA_ERR1 = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_1_01_STEP_RANGE_EDGE_ERR1 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_1_01_NO_INCREASE_ERR1 = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_1_01_1D_EYE_NOISE_ERR1 = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_1_01_BAD_BIT_ERR1 = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_2_23_MAX_RANGE_ERR0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_2_23_MIN_RANGE_ERR0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_2_23_TWO_RANGE_BEST_CASE_ERR0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_2_23_BIT_STEP_DELTA_ERR0 = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_2_23_STEP_RANGE_EDGE_ERR0 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_2_23_NO_INCREASE_ERR0 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_2_23_1D_EYE_NOISE_ERR0 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_2_23_BAD_BIT_ERR0 = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_2_23_MAX_RANGE_ERR1 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_2_23_MIN_RANGE_ERR1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_2_23_TWO_RANGE_BEST_CASE_ERR1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_2_23_BIT_STEP_DELTA_ERR1 = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_2_23_STEP_RANGE_EDGE_ERR1 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_2_23_NO_INCREASE_ERR1 = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_2_23_1D_EYE_NOISE_ERR1 = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_2_23_BAD_BIT_ERR1 = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_3_23_MAX_RANGE_ERR0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_3_23_MIN_RANGE_ERR0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_3_23_TWO_RANGE_BEST_CASE_ERR0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_3_23_BIT_STEP_DELTA_ERR0 = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_3_23_STEP_RANGE_EDGE_ERR0 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_3_23_NO_INCREASE_ERR0 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_3_23_1D_EYE_NOISE_ERR0 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_3_23_BAD_BIT_ERR0 = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_3_23_MAX_RANGE_ERR1 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_3_23_MIN_RANGE_ERR1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_3_23_TWO_RANGE_BEST_CASE_ERR1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_3_23_BIT_STEP_DELTA_ERR1 = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_3_23_STEP_RANGE_EDGE_ERR1 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_3_23_NO_INCREASE_ERR1 = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_3_23_1D_EYE_NOISE_ERR1 = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_3_23_BAD_BIT_ERR1 = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_4_4_MAX_RANGE_ERR0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_4_4_MIN_RANGE_ERR0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_4_4_TWO_RANGE_BEST_CASE_ERR0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_4_4_BIT_STEP_DELTA_ERR0 = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_4_4_STEP_RANGE_EDGE_ERR0 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_4_4_NO_INCREASE_ERR0 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_4_4_1D_EYE_NOISE_ERR0 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_4_4_BAD_BIT_ERR0 = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_4_4_MAX_RANGE_ERR1 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_4_4_MIN_RANGE_ERR1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_4_4_TWO_RANGE_BEST_CASE_ERR1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_4_4_BIT_STEP_DELTA_ERR1 = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_4_4_STEP_RANGE_EDGE_ERR1 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_4_4_NO_INCREASE_ERR1 = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_4_4_1D_EYE_NOISE_ERR1 = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_4_4_BAD_BIT_ERR1 = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_0_01_MAX_RANGE_ERR2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_0_01_MIN_RANGE_ERR2 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_0_01_TWO_RANGE_BEST_CASE_ERR2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_0_01_BIT_STEP_DELTA_ERR2 = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_0_01_STEP_RANGE_EDGE_ERR2 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_0_01_NO_INCREASE_ERR2 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_0_01_1D_EYE_NOISE_ERR2 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_0_01_BAD_BIT_ERR2 = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_0_01_MAX_RANGE_ERR3 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_0_01_MIN_RANGE_ERR3 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_0_01_TWO_RANGE_BEST_CASE_ERR3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_0_01_BIT_STEP_DELTA_ERR3 = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_0_01_STEP_RANGE_EDGE_ERR3 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_0_01_NO_INCREASE_ERR3 = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_0_01_1D_EYE_NOISE_ERR3 = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_0_01_BAD_BIT_ERR3 = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_1_01_MAX_RANGE_ERR2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_1_01_MIN_RANGE_ERR2 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_1_01_TWO_RANGE_BEST_CASE_ERR2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_1_01_BIT_STEP_DELTA_ERR2 = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_1_01_STEP_RANGE_EDGE_ERR2 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_1_01_NO_INCREASE_ERR2 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_1_01_1D_EYE_NOISE_ERR2 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_1_01_BAD_BIT_ERR2 = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_1_01_MAX_RANGE_ERR3 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_1_01_MIN_RANGE_ERR3 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_1_01_TWO_RANGE_BEST_CASE_ERR3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_1_01_BIT_STEP_DELTA_ERR3 = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_1_01_STEP_RANGE_EDGE_ERR3 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_1_01_NO_INCREASE_ERR3 = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_1_01_1D_EYE_NOISE_ERR3 = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_1_01_BAD_BIT_ERR3 = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_2_23_MAX_RANGE_ERR2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_2_23_MIN_RANGE_ERR2 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_2_23_TWO_RANGE_BEST_CASE_ERR2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_2_23_BIT_STEP_DELTA_ERR2 = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_2_23_STEP_RANGE_EDGE_ERR2 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_2_23_NO_INCREASE_ERR2 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_2_23_1D_EYE_NOISE_ERR2 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_2_23_BAD_BIT_ERR2 = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_2_23_MAX_RANGE_ERR3 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_2_23_MIN_RANGE_ERR3 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_2_23_TWO_RANGE_BEST_CASE_ERR3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_2_23_BIT_STEP_DELTA_ERR3 = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_2_23_STEP_RANGE_EDGE_ERR3 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_2_23_NO_INCREASE_ERR3 = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_2_23_1D_EYE_NOISE_ERR3 = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_2_23_BAD_BIT_ERR3 = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_3_23_MAX_RANGE_ERR2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_3_23_MIN_RANGE_ERR2 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_3_23_TWO_RANGE_BEST_CASE_ERR2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_3_23_BIT_STEP_DELTA_ERR2 = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_3_23_STEP_RANGE_EDGE_ERR2 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_3_23_NO_INCREASE_ERR2 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_3_23_1D_EYE_NOISE_ERR2 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_3_23_BAD_BIT_ERR2 = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_3_23_MAX_RANGE_ERR3 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_3_23_MIN_RANGE_ERR3 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_3_23_TWO_RANGE_BEST_CASE_ERR3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_3_23_BIT_STEP_DELTA_ERR3 = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_3_23_STEP_RANGE_EDGE_ERR3 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_3_23_NO_INCREASE_ERR3 = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_3_23_1D_EYE_NOISE_ERR3 = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_3_23_BAD_BIT_ERR3 = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_4_4_MAX_RANGE_ERR2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_4_4_MIN_RANGE_ERR2 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_4_4_TWO_RANGE_BEST_CASE_ERR2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_4_4_BIT_STEP_DELTA_ERR2 = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_4_4_STEP_RANGE_EDGE_ERR2 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_4_4_NO_INCREASE_ERR2 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_4_4_1D_EYE_NOISE_ERR2 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_4_4_BAD_BIT_ERR2 = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_4_4_MAX_RANGE_ERR3 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_4_4_MIN_RANGE_ERR3 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_4_4_TWO_RANGE_BEST_CASE_ERR3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_4_4_BIT_STEP_DELTA_ERR3 = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_4_4_STEP_RANGE_EDGE_ERR3 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_4_4_NO_INCREASE_ERR3 = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_4_4_1D_EYE_NOISE_ERR3 = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_4_4_BAD_BIT_ERR3 = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_MAX_RANGE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_MIN_RANGE = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_TWO_RANGE_BEST_CASE = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_BIT_STEP_DELTA = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_STEP_RANGE_EDGE = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_NO_INCREASE = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_1D_EYE_NOISE = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_BAD_BIT = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_MAX_RANGE_MASK1 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_MIN_RANGE_MASK1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_TWO_RANGE_BEST_CASE_MASK1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_BIT_STEP_DELTA_MASK1 = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_STEP_RANGE_EDGE_MASK1 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_NO_INCREASE_MASK1 = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_1D_EYE_NOISE_MASK1 = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_BAD_BIT_MASK1 = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1_01_MAX_RANGE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1_01_MIN_RANGE = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1_01_TWO_RANGE_BEST_CASE = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1_01_BIT_STEP_DELTA = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1_01_STEP_RANGE_EDGE = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1_01_NO_INCREASE = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1_01_1D_EYE_NOISE = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1_01_BAD_BIT = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1_01_MAX_RANGE_MASK1 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1_01_MIN_RANGE_MASK1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1_01_TWO_RANGE_BEST_CASE_MASK1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1_01_BIT_STEP_DELTA_MASK1 = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1_01_STEP_RANGE_EDGE_MASK1 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1_01_NO_INCREASE_MASK1 = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1_01_1D_EYE_NOISE_MASK1 = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1_01_BAD_BIT_MASK1 = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2_23_MAX_RANGE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2_23_MIN_RANGE = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2_23_TWO_RANGE_BEST_CASE = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2_23_BIT_STEP_DELTA = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2_23_STEP_RANGE_EDGE = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2_23_NO_INCREASE = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2_23_1D_EYE_NOISE = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2_23_BAD_BIT = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2_23_MAX_RANGE_MASK1 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2_23_MIN_RANGE_MASK1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2_23_TWO_RANGE_BEST_CASE_MASK1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2_23_BIT_STEP_DELTA_MASK1 = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2_23_STEP_RANGE_EDGE_MASK1 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2_23_NO_INCREASE_MASK1 = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2_23_1D_EYE_NOISE_MASK1 = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2_23_BAD_BIT_MASK1 = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3_23_MAX_RANGE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3_23_MIN_RANGE = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3_23_TWO_RANGE_BEST_CASE = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3_23_BIT_STEP_DELTA = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3_23_STEP_RANGE_EDGE = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3_23_NO_INCREASE = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3_23_1D_EYE_NOISE = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3_23_BAD_BIT = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3_23_MAX_RANGE_MASK1 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3_23_MIN_RANGE_MASK1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3_23_TWO_RANGE_BEST_CASE_MASK1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3_23_BIT_STEP_DELTA_MASK1 = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3_23_STEP_RANGE_EDGE_MASK1 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3_23_NO_INCREASE_MASK1 = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3_23_1D_EYE_NOISE_MASK1 = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3_23_BAD_BIT_MASK1 = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4_4_MAX_RANGE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4_4_MIN_RANGE = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4_4_TWO_RANGE_BEST_CASE = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4_4_BIT_STEP_DELTA = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4_4_STEP_RANGE_EDGE = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4_4_NO_INCREASE = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4_4_1D_EYE_NOISE = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4_4_BAD_BIT = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4_4_MAX_RANGE_MASK1 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4_4_MIN_RANGE_MASK1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4_4_TWO_RANGE_BEST_CASE_MASK1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4_4_BIT_STEP_DELTA_MASK1 = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4_4_STEP_RANGE_EDGE_MASK1 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4_4_NO_INCREASE_MASK1 = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4_4_1D_EYE_NOISE_MASK1 = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4_4_BAD_BIT_MASK1 = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0_01_MAX_RANGE_MASK2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0_01_MIN_RANGE_MASK2 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0_01_TWO_RANGE_BEST_CASE_MASK2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0_01_BIT_STEP_DELTA_MASK2 = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0_01_STEP_RANGE_EDGE_MASK2 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0_01_NO_INCREASE_MASK2 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0_01_1D_EYE_NOISE_MASK2 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0_01_BAD_BIT_MASK2 = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0_01_MAX_RANGE_MASK3 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0_01_MIN_RANGE_MASK3 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0_01_TWO_RANGE_BEST_CASE_MASK3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0_01_BIT_STEP_DELTA_MASK3 = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0_01_STEP_RANGE_EDGE_MASK3 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0_01_NO_INCREASE_MASK3 = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0_01_1D_EYE_NOISE_MASK3 = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0_01_BAD_BIT_MASK3 = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1_01_MAX_RANGE_MASK2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1_01_MIN_RANGE_MASK2 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1_01_TWO_RANGE_BEST_CASE_MASK2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1_01_BIT_STEP_DELTA_MASK2 = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1_01_STEP_RANGE_EDGE_MASK2 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1_01_NO_INCREASE_MASK2 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1_01_1D_EYE_NOISE_MASK2 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1_01_BAD_BIT_MASK2 = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1_01_MAX_RANGE_MASK3 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1_01_MIN_RANGE_MASK3 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1_01_TWO_RANGE_BEST_CASE_MASK3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1_01_BIT_STEP_DELTA_MASK3 = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1_01_STEP_RANGE_EDGE_MASK3 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1_01_NO_INCREASE_MASK3 = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1_01_1D_EYE_NOISE_MASK3 = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1_01_BAD_BIT_MASK3 = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2_23_MAX_RANGE_MASK2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2_23_MIN_RANGE_MASK2 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2_23_TWO_RANGE_BEST_CASE_MASK2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2_23_BIT_STEP_DELTA_MASK2 = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2_23_STEP_RANGE_EDGE_MASK2 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2_23_NO_INCREASE_MASK2 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2_23_1D_EYE_NOISE_MASK2 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2_23_BAD_BIT_MASK2 = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2_23_MAX_RANGE_MASK3 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2_23_MIN_RANGE_MASK3 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2_23_TWO_RANGE_BEST_CASE_MASK3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2_23_BIT_STEP_DELTA_MASK3 = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2_23_STEP_RANGE_EDGE_MASK3 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2_23_NO_INCREASE_MASK3 = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2_23_1D_EYE_NOISE_MASK3 = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2_23_BAD_BIT_MASK3 = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3_23_MAX_RANGE_MASK2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3_23_MIN_RANGE_MASK2 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3_23_TWO_RANGE_BEST_CASE_MASK2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3_23_BIT_STEP_DELTA_MASK2 = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3_23_STEP_RANGE_EDGE_MASK2 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3_23_NO_INCREASE_MASK2 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3_23_1D_EYE_NOISE_MASK2 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3_23_BAD_BIT_MASK2 = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3_23_MAX_RANGE_MASK3 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3_23_MIN_RANGE_MASK3 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3_23_TWO_RANGE_BEST_CASE_MASK3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3_23_BIT_STEP_DELTA_MASK3 = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3_23_STEP_RANGE_EDGE_MASK3 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3_23_NO_INCREASE_MASK3 = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3_23_1D_EYE_NOISE_MASK3 = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3_23_BAD_BIT_MASK3 = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4_4_MAX_RANGE_MASK2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4_4_MIN_RANGE_MASK2 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4_4_TWO_RANGE_BEST_CASE_MASK2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4_4_BIT_STEP_DELTA_MASK2 = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4_4_STEP_RANGE_EDGE_MASK2 = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4_4_NO_INCREASE_MASK2 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4_4_1D_EYE_NOISE_MASK2 = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4_4_BAD_BIT_MASK2 = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4_4_MAX_RANGE_MASK3 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4_4_MIN_RANGE_MASK3 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4_4_TWO_RANGE_BEST_CASE_MASK3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4_4_BIT_STEP_DELTA_MASK3 = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4_4_STEP_RANGE_EDGE_MASK3 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4_4_NO_INCREASE_MASK3 = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4_4_1D_EYE_NOISE_MASK3 = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4_4_BAD_BIT_MASK3 = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_STATUS0_P0_0_01_CTR_NUM_WRRDREQ_CNT = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_STATUS0_P0_0_01_CTR_NUM_WRRDREQ_CNT_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_STATUS0_P0_1_01_CTR_NUM_WRRDREQ_CNT = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_STATUS0_P0_1_01_CTR_NUM_WRRDREQ_CNT_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_STATUS0_P0_2_23_CTR_NUM_WRRDREQ_CNT = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_STATUS0_P0_2_23_CTR_NUM_WRRDREQ_CNT_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_STATUS0_P0_3_23_CTR_NUM_WRRDREQ_CNT = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_STATUS0_P0_3_23_CTR_NUM_WRRDREQ_CNT_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_STATUS0_P0_4_4_CTR_NUM_WRRDREQ_CNT = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_STATUS0_P0_4_4_CTR_NUM_WRRDREQ_CNT_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_0_01_CTR_NUM_VREFREQ_CNT = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_0_01_CTR_NUM_VREFREQ_CNT_LEN = 9 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_0_01_CTR_CUR = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_0_01_CTR_CUR_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_1_01_CTR_NUM_VREFREQ_CNT = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_1_01_CTR_NUM_VREFREQ_CNT_LEN = 9 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_1_01_CTR_CUR = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_1_01_CTR_CUR_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_2_23_CTR_NUM_VREFREQ_CNT = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_2_23_CTR_NUM_VREFREQ_CNT_LEN = 9 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_2_23_CTR_CUR = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_2_23_CTR_CUR_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_3_23_CTR_NUM_VREFREQ_CNT = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_3_23_CTR_NUM_VREFREQ_CNT_LEN = 9 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_3_23_CTR_CUR = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_3_23_CTR_CUR_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_4_4_CTR_NUM_VREFREQ_CNT = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_4_4_CTR_NUM_VREFREQ_CNT_LEN = 9 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_4_4_CTR_CUR = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_4_4_CTR_CUR_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_0_01_RANGE_DRAM0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_0_01_VALUE_DRAM0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_0_01_VALUE_DRAM0_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_0_01_RANGE_DRAM1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_0_01_VALUE_DRAM1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_0_01_VALUE_DRAM1_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_1_01_RANGE_DRAM0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_1_01_VALUE_DRAM0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_1_01_VALUE_DRAM0_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_1_01_RANGE_DRAM1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_1_01_VALUE_DRAM1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_1_01_VALUE_DRAM1_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_2_23_RANGE_DRAM0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_2_23_VALUE_DRAM0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_2_23_VALUE_DRAM0_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_2_23_RANGE_DRAM1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_2_23_VALUE_DRAM1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_2_23_VALUE_DRAM1_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_3_23_RANGE_DRAM0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_3_23_VALUE_DRAM0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_3_23_VALUE_DRAM0_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_3_23_RANGE_DRAM1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_3_23_VALUE_DRAM1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_3_23_VALUE_DRAM1_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_4_4_RANGE_DRAM0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_4_4_VALUE_DRAM0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_4_4_VALUE_DRAM0_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_4_4_RANGE_DRAM1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_4_4_VALUE_DRAM1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_4_4_VALUE_DRAM1_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_0_01_RANGE_DRAM0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_0_01_VALUE_DRAM0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_0_01_VALUE_DRAM0_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_0_01_RANGE_DRAM1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_0_01_VALUE_DRAM1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_0_01_VALUE_DRAM1_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_1_01_RANGE_DRAM0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_1_01_VALUE_DRAM0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_1_01_VALUE_DRAM0_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_1_01_RANGE_DRAM1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_1_01_VALUE_DRAM1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_1_01_VALUE_DRAM1_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_2_23_RANGE_DRAM0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_2_23_VALUE_DRAM0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_2_23_VALUE_DRAM0_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_2_23_RANGE_DRAM1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_2_23_VALUE_DRAM1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_2_23_VALUE_DRAM1_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_3_23_RANGE_DRAM0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_3_23_VALUE_DRAM0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_3_23_VALUE_DRAM0_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_3_23_RANGE_DRAM1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_3_23_VALUE_DRAM1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_3_23_VALUE_DRAM1_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_4_4_RANGE_DRAM0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_4_4_VALUE_DRAM0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_4_4_VALUE_DRAM0_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_4_4_RANGE_DRAM1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_4_4_VALUE_DRAM1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_4_4_VALUE_DRAM1_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_0_01_RANGE_DRAM0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_0_01_VALUE_DRAM0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_0_01_VALUE_DRAM0_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_0_01_RANGE_DRAM1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_0_01_VALUE_DRAM1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_0_01_VALUE_DRAM1_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_1_01_RANGE_DRAM0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_1_01_VALUE_DRAM0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_1_01_VALUE_DRAM0_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_1_01_RANGE_DRAM1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_1_01_VALUE_DRAM1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_1_01_VALUE_DRAM1_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_2_23_RANGE_DRAM0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_2_23_VALUE_DRAM0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_2_23_VALUE_DRAM0_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_2_23_RANGE_DRAM1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_2_23_VALUE_DRAM1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_2_23_VALUE_DRAM1_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_3_23_RANGE_DRAM0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_3_23_VALUE_DRAM0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_3_23_VALUE_DRAM0_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_3_23_RANGE_DRAM1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_3_23_VALUE_DRAM1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_3_23_VALUE_DRAM1_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_4_4_RANGE_DRAM0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_4_4_VALUE_DRAM0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_4_4_VALUE_DRAM0_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_4_4_RANGE_DRAM1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_4_4_VALUE_DRAM1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_4_4_VALUE_DRAM1_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_0_01_RANGE_DRAM0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_0_01_VALUE_DRAM0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_0_01_VALUE_DRAM0_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_0_01_RANGE_DRAM1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_0_01_VALUE_DRAM1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_0_01_VALUE_DRAM1_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_1_01_RANGE_DRAM0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_1_01_VALUE_DRAM0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_1_01_VALUE_DRAM0_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_1_01_RANGE_DRAM1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_1_01_VALUE_DRAM1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_1_01_VALUE_DRAM1_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_2_23_RANGE_DRAM0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_2_23_VALUE_DRAM0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_2_23_VALUE_DRAM0_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_2_23_RANGE_DRAM1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_2_23_VALUE_DRAM1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_2_23_VALUE_DRAM1_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_3_23_RANGE_DRAM0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_3_23_VALUE_DRAM0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_3_23_VALUE_DRAM0_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_3_23_RANGE_DRAM1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_3_23_VALUE_DRAM1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_3_23_VALUE_DRAM1_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_4_4_RANGE_DRAM0 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_4_4_VALUE_DRAM0 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_4_4_VALUE_DRAM0_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_4_4_RANGE_DRAM1 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_4_4_VALUE_DRAM1 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_4_4_VALUE_DRAM1_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_0_01_RANGE_DRAM2 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_0_01_VALUE_DRAM2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_0_01_VALUE_DRAM2_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_0_01_RANGE_DRAM3 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_0_01_VALUE_DRAM3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_0_01_VALUE_DRAM3_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_1_01_RANGE_DRAM2 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_1_01_VALUE_DRAM2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_1_01_VALUE_DRAM2_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_1_01_RANGE_DRAM3 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_1_01_VALUE_DRAM3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_1_01_VALUE_DRAM3_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_2_23_RANGE_DRAM2 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_2_23_VALUE_DRAM2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_2_23_VALUE_DRAM2_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_2_23_RANGE_DRAM3 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_2_23_VALUE_DRAM3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_2_23_VALUE_DRAM3_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_3_23_RANGE_DRAM2 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_3_23_VALUE_DRAM2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_3_23_VALUE_DRAM2_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_3_23_RANGE_DRAM3 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_3_23_VALUE_DRAM3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_3_23_VALUE_DRAM3_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_4_4_RANGE_DRAM2 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_4_4_VALUE_DRAM2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_4_4_VALUE_DRAM2_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_4_4_RANGE_DRAM3 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_4_4_VALUE_DRAM3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_4_4_VALUE_DRAM3_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_0_01_RANGE_DRAM2 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_0_01_VALUE_DRAM2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_0_01_VALUE_DRAM2_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_0_01_RANGE_DRAM3 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_0_01_VALUE_DRAM3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_0_01_VALUE_DRAM3_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_1_01_RANGE_DRAM2 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_1_01_VALUE_DRAM2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_1_01_VALUE_DRAM2_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_1_01_RANGE_DRAM3 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_1_01_VALUE_DRAM3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_1_01_VALUE_DRAM3_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_2_23_RANGE_DRAM2 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_2_23_VALUE_DRAM2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_2_23_VALUE_DRAM2_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_2_23_RANGE_DRAM3 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_2_23_VALUE_DRAM3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_2_23_VALUE_DRAM3_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_3_23_RANGE_DRAM2 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_3_23_VALUE_DRAM2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_3_23_VALUE_DRAM2_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_3_23_RANGE_DRAM3 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_3_23_VALUE_DRAM3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_3_23_VALUE_DRAM3_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_4_4_RANGE_DRAM2 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_4_4_VALUE_DRAM2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_4_4_VALUE_DRAM2_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_4_4_RANGE_DRAM3 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_4_4_VALUE_DRAM3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_4_4_VALUE_DRAM3_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_0_01_RANGE_DRAM2 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_0_01_VALUE_DRAM2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_0_01_VALUE_DRAM2_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_0_01_RANGE_DRAM3 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_0_01_VALUE_DRAM3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_0_01_VALUE_DRAM3_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_1_01_RANGE_DRAM2 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_1_01_VALUE_DRAM2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_1_01_VALUE_DRAM2_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_1_01_RANGE_DRAM3 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_1_01_VALUE_DRAM3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_1_01_VALUE_DRAM3_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_2_23_RANGE_DRAM2 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_2_23_VALUE_DRAM2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_2_23_VALUE_DRAM2_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_2_23_RANGE_DRAM3 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_2_23_VALUE_DRAM3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_2_23_VALUE_DRAM3_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_3_23_RANGE_DRAM2 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_3_23_VALUE_DRAM2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_3_23_VALUE_DRAM2_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_3_23_RANGE_DRAM3 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_3_23_VALUE_DRAM3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_3_23_VALUE_DRAM3_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_4_4_RANGE_DRAM2 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_4_4_VALUE_DRAM2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_4_4_VALUE_DRAM2_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_4_4_RANGE_DRAM3 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_4_4_VALUE_DRAM3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_4_4_VALUE_DRAM3_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_0_01_RANGE_DRAM2 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_0_01_VALUE_DRAM2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_0_01_VALUE_DRAM2_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_0_01_RANGE_DRAM3 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_0_01_VALUE_DRAM3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_0_01_VALUE_DRAM3_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_1_01_RANGE_DRAM2 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_1_01_VALUE_DRAM2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_1_01_VALUE_DRAM2_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_1_01_RANGE_DRAM3 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_1_01_VALUE_DRAM3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_1_01_VALUE_DRAM3_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_2_23_RANGE_DRAM2 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_2_23_VALUE_DRAM2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_2_23_VALUE_DRAM2_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_2_23_RANGE_DRAM3 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_2_23_VALUE_DRAM3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_2_23_VALUE_DRAM3_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_3_23_RANGE_DRAM2 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_3_23_VALUE_DRAM2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_3_23_VALUE_DRAM2_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_3_23_RANGE_DRAM3 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_3_23_VALUE_DRAM3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_3_23_VALUE_DRAM3_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_4_4_RANGE_DRAM2 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_4_4_VALUE_DRAM2 = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_4_4_VALUE_DRAM2_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_4_4_RANGE_DRAM3 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_4_4_VALUE_DRAM3 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_4_4_VALUE_DRAM3_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_PC_BASE_CNTR0_P0_PERIODIC = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_BASE_CNTR0_P0_PERIODIC_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_PC_BASE_CNTR1_P0_PERIODIC = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_BASE_CNTR1_P0_PERIODIC_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_PC_CAL_TIMER_P0_PERIODIC = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_CAL_TIMER_P0_PERIODIC_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_PC_CAL_TIMER_RELOAD_VALUE_P0_PERIODIC = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_CAL_TIMER_RELOAD_VALUE_P0_PERIODIC_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_PC_CONFIG0_P0_PDA_ENABLE_OVERRIDE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_CONFIG0_P0_PDA_ENABLE_OVERRIDE_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_CONFIG0_P0_TCK_PREAMBLE_ENABLE = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_CONFIG0_P0_PBA_ENABLE = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_CONFIG0_P0_DDR4_CMD_SIG_REDUCTION = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_CONFIG0_P0_SYSCLK_2X_MEMINTCLKO = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_CONFIG0_P0_RANK_OVERRIDE = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_CONFIG0_P0_RANK_OVERRIDE_VALUE = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_CONFIG0_P0_RANK_OVERRIDE_VALUE_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_CONFIG0_P0_LOW_LATENCY = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_CONFIG0_P0_DDR4_IPW_LOOP_DIS = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_CONFIG0_P0_DDR4_VLEVEL_BANK_GROUP = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_CONFIG0_P0_VPROTH_PSEL_MODE = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_PC_CONFIG1_P0_WRITE_LATENCY_OFFSET = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_CONFIG1_P0_WRITE_LATENCY_OFFSET_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_CONFIG1_P0_READ_LATENCY_OFFSET = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_CONFIG1_P0_READ_LATENCY_OFFSET_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_CONFIG1_P0_MEMCTL_CIC_FAST = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_CONFIG1_P0_MEMCTL_CTRN_IGNORE = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_CONFIG1_P0_DISABLE_MEMCTL_CAL = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_CONFIG1_P0_MEMORY_TYPE = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_CONFIG1_P0_MEMORY_TYPE_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_CONFIG1_P0_DDR4_LATENCY_SW = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_CONFIG1_P0_RETRAIN_PERCAL_SW = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_PC_CSID_CFG_P0_CS0_INIT_CAL_VALUE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_CSID_CFG_P0_CS1_INIT_CAL_VALUE = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_CSID_CFG_P0_CS2_INIT_CAL_VALUE = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_CSID_CFG_P0_CS3_INIT_CAL_VALUE = 51 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_PC_DLL_ZCAL_CAL_STATUS_P0_DP_GOOD = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_DLL_ZCAL_CAL_STATUS_P0_DP_ERROR = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_DLL_ZCAL_CAL_STATUS_P0_DP_ERROR_FINE = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_DLL_ZCAL_CAL_STATUS_P0_ADR_GOOD = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_DLL_ZCAL_CAL_STATUS_P0_ADR_ERROR = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_DLL_ZCAL_CAL_STATUS_P0_ADR_ERROR_FINE = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_DLL_ZCAL_CAL_STATUS_P0_DONE = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_PC_ERROR_MASK0_P0_RC_MASK = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_ERROR_MASK0_P0_WC_MASK = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_ERROR_MASK0_P0_SEQ_MASK = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_ERROR_MASK0_P0_APB_MASK = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_ERROR_MASK0_P0_MASK = 53 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_PC_ERROR_STATUS0_P0_RC = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_ERROR_STATUS0_P0_WC = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_ERROR_STATUS0_P0_SEQ = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_ERROR_STATUS0_P0_RESERVED_51 = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_ERROR_STATUS0_P0_APB = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_ERROR_STATUS0_P0_ERROR = 53 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ENA_WR_LEVEL = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ENA_INITIAL_PAT_WR = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ENA_DQS_ALIGN = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ENA_RDCLK_ALIGN = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ENA_READ_CTR = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ENA_WRITE_CTR = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ENA_INITIAL_COARSE_WR = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ENA_COARSE_RD = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ENA_CUSTOM_RD = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ENA_CUSTOM_WR = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ABORT_ON_ERROR = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ENA_DIGITAL_EYE = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ENA_RANK_PAIR = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ENA_RANK_PAIR_LEN = 4 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_CONFIG1_P0_REFRESH_COUNT = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_CONFIG1_P0_REFRESH_COUNT_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_CONFIG1_P0_REFRESH_CONTROL = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_CONFIG1_P0_REFRESH_CONTROL_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_CONFIG1_P0_REFRESH_ALL_RANKS = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_CONFIG1_P0_CMD_SNOOP_DIS = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_CONFIG1_P0_MRS_SNOOP_DIS = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_CONFIG1_P0_REFRESH_INTERVAL = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_CONFIG1_P0_REFRESH_INTERVAL_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_ERROR_P0_WR_LEVEL = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_ERROR_P0_INITIAL_PAT_WRITE = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_ERROR_P0_DQS_ALIGN = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_ERROR_P0_RDCLK_ALIGN = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_ERROR_P0_READ_CTR = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_ERROR_P0_WRITE_CTR = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_ERROR_P0_INITIAL_COARSE_WR = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_ERROR_P0_COARSE_RD = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_ERROR_P0_CUSTOM_RD = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_ERROR_P0_CUSTOM_WR = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_ERROR_P0_DIGITAL_EYE = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_ERROR_P0_VREF = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_ERROR_P0_RANK_PAIR = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_ERROR_P0_RANK_PAIR_LEN = 4 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_MASK_P0_ERROR_WR_LEVEL = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_MASK_P0_ERROR_INITIAL_PAT_WRITE = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_MASK_P0_ERROR_DQS_ALIGN = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_MASK_P0_ERROR_RDCLK_ALIGN = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_MASK_P0_ERROR_READ_CTR = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_MASK_P0_ERROR_WRITE_CTR = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_MASK_P0_ERROR_INITIAL_COARSE_WR = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_MASK_P0_ERROR_COARSE_RD = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_MASK_P0_ERROR_CUSTOM_RD = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_MASK_P0_ERROR_CUSTOM_WR = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_MASK_P0_ERROR_DIGITAL_EYE = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_MASK_P0_ERROR_VREF = 59 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_STATUS_P0_COMPLETE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_STATUS_P0_COMPLETE_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_STATUS_P0_DFI_REQ_STATE = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_STATUS_P0_DFI_REQ_STATE_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_STATUS_P0_PER_PEND_OVRFLW = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_STATUS_P0_PER_ABORT = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_STATUS_P0_RESERVED_58 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_STATUS_P0_ICAL_STATE = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_STATUS_P0_ICAL_STATE_LEN = 5 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_PC_IO_PVT_FET_CONTROL_P0_PVTPB = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_IO_PVT_FET_CONTROL_P0_PVTPL = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_IO_PVT_FET_CONTROL_P0_PVTPL_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_IO_PVT_FET_CONTROL_P0_PVTNB = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_IO_PVT_FET_CONTROL_P0_PVTNL = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_IO_PVT_FET_CONTROL_P0_PVTNL_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_PC_IO_PVT_FET_STATUS_P0_PVTPB = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_IO_PVT_FET_STATUS_P0_PVTPL = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_IO_PVT_FET_STATUS_P0_PVTPL_LEN = 7 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_IO_PVT_FET_STATUS_P0_PVTNB = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_IO_PVT_FET_STATUS_P0_PVTNL = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_IO_PVT_FET_STATUS_P0_PVTNL_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_PC_MIRROR_CONFIG_P0_ADDR_RP0_PRI = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_MIRROR_CONFIG_P0_ADDR_RP0_SEC = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_MIRROR_CONFIG_P0_ADDR_RP1_PRI = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_MIRROR_CONFIG_P0_ADDR_RP1_SEC = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_MIRROR_CONFIG_P0_ADDR_RP2_PRI = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_MIRROR_CONFIG_P0_ADDR_RP2_SEC = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_MIRROR_CONFIG_P0_ADDR_RP3_PRI = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_MIRROR_CONFIG_P0_ADDR_RP3_SEC = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_MIRROR_CONFIG_P0_ADDR_A3_A4 = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_MIRROR_CONFIG_P0_ADDR_A5_A6 = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_MIRROR_CONFIG_P0_ADDR_A7_A8 = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_MIRROR_CONFIG_P0_ADDR_A11_A13 = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_MIRROR_CONFIG_P0_ADDR_BA0_BA1 = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_MIRROR_CONFIG_P0_ADDR_BG0_BG1 = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_PC_MR0_RP0_P0_MODE_REGISTER_0_VALUE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_MR0_RP0_P0_MODE_REGISTER_0_VALUE_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_PC_MR0_RP1_P0_MODE_REGISTER_0_VALUE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_MR0_RP1_P0_MODE_REGISTER_0_VALUE_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_PC_MR0_RP2_P0_MODE_REGISTER_0_VALUE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_MR0_RP2_P0_MODE_REGISTER_0_VALUE_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_PC_MR0_RP3_P0_MODE_REGISTER_0_VALUE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_MR0_RP3_P0_MODE_REGISTER_0_VALUE_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_PC_MR1_RP0_P0_MODE_REGISTER_1_VALUE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_MR1_RP0_P0_MODE_REGISTER_1_VALUE_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_PC_MR1_RP1_P0_MODE_REGISTER_1_VALUE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_MR1_RP1_P0_MODE_REGISTER_1_VALUE_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_PC_MR1_RP2_P0_MODE_REGISTER_1_VALUE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_MR1_RP2_P0_MODE_REGISTER_1_VALUE_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_PC_MR1_RP3_P0_MODE_REGISTER_1_VALUE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_MR1_RP3_P0_MODE_REGISTER_1_VALUE_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_PC_MR2_RP0_P0_MODE_REGISTER_2_VALUE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_MR2_RP0_P0_MODE_REGISTER_2_VALUE_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_PC_MR2_RP1_P0_MODE_REGISTER_2_VALUE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_MR2_RP1_P0_MODE_REGISTER_2_VALUE_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_PC_MR2_RP2_P0_MODE_REGISTER_2_VALUE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_MR2_RP2_P0_MODE_REGISTER_2_VALUE_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_PC_MR2_RP3_P0_MODE_REGISTER_2_VALUE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_MR2_RP3_P0_MODE_REGISTER_2_VALUE_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_PC_MR3_RP0_P0_MODE_REGISTER_3_VALUE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_MR3_RP0_P0_MODE_REGISTER_3_VALUE_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_PC_MR3_RP1_P0_MODE_REGISTER_3_VALUE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_MR3_RP1_P0_MODE_REGISTER_3_VALUE_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_PC_MR3_RP2_P0_MODE_REGISTER_3_VALUE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_MR3_RP2_P0_MODE_REGISTER_3_VALUE_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_PC_MR3_RP3_P0_MODE_REGISTER_3_VALUE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_MR3_RP3_P0_MODE_REGISTER_3_VALUE_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_PC_MR4_RP0_P0_MODE_REGISTER_4_VALUE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_MR4_RP0_P0_MODE_REGISTER_4_VALUE_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_PC_MR4_RP1_P0_MODE_REGISTER_4_VALUE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_MR4_RP1_P0_MODE_REGISTER_4_VALUE_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_PC_MR4_RP2_P0_MODE_REGISTER_4_VALUE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_MR4_RP2_P0_MODE_REGISTER_4_VALUE_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_PC_MR4_RP3_P0_MODE_REGISTER_4_VALUE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_MR4_RP3_P0_MODE_REGISTER_4_VALUE_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_PC_MR5_RP0_P0_MODE_REGISTER_5_VALUE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_MR5_RP0_P0_MODE_REGISTER_5_VALUE_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_PC_MR5_RP1_P0_MODE_REGISTER_5_VALUE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_MR5_RP1_P0_MODE_REGISTER_5_VALUE_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_PC_MR5_RP2_P0_MODE_REGISTER_5_VALUE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_MR5_RP2_P0_MODE_REGISTER_5_VALUE_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_PC_MR5_RP3_P0_MODE_REGISTER_5_VALUE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_MR5_RP3_P0_MODE_REGISTER_5_VALUE_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_PC_MR6_RP0_P0_MODE_REGISTER_6_VALUE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_MR6_RP0_P0_MODE_REGISTER_6_VALUE_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_PC_MR6_RP1_P0_MODE_REGISTER_6_VALUE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_MR6_RP1_P0_MODE_REGISTER_6_VALUE_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_PC_MR6_RP2_P0_MODE_REGISTER_6_VALUE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_MR6_RP2_P0_MODE_REGISTER_6_VALUE_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_PC_MR6_RP3_P0_MODE_REGISTER_6_VALUE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_MR6_RP3_P0_MODE_REGISTER_6_VALUE_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_PC_MR7_RP0_P0_MODE_REGISTER_7_VALUE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_MR7_RP0_P0_MODE_REGISTER_7_VALUE_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_PC_MR7_RP1_P0_MODE_REGISTER_7_VALUE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_MR7_RP1_P0_MODE_REGISTER_7_VALUE_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_PC_MR7_RP2_P0_MODE_REGISTER_7_VALUE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_MR7_RP2_P0_MODE_REGISTER_7_VALUE_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_PC_MR7_RP3_P0_MODE_REGISTER_7_VALUE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_MR7_RP3_P0_MODE_REGISTER_7_VALUE_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_PC_PBA_CONTROL_P0_SNOOPED_F0RC4X_BIT4 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_PBA_CONTROL_P0_PHY_CSN_MAP = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_PBA_CONTROL_P0_PHY_CSN_MAP_LEN = 2 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_PC_PER_CAL_CONFIG_P0_ENA_RANK_PAIR = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_PER_CAL_CONFIG_P0_ENA_RANK_PAIR_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_PER_CAL_CONFIG_P0_ENA_ZCAL = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_PER_CAL_CONFIG_P0_ENA_SYSCLK_ALIGN = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_PER_CAL_CONFIG_P0_ENA_READ_CTR = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_PER_CAL_CONFIG_P0_ENA_RDCLK_ALIGN = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_PER_CAL_CONFIG_P0_ENA_DQS_ALIGN = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_PER_CAL_CONFIG_P0_NEXT_RANK_PAIR = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_PER_CAL_CONFIG_P0_NEXT_RANK_PAIR_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_PER_CAL_CONFIG_P0_FAST_SIM_CNTR = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_PER_CAL_CONFIG_P0_START_INIT = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_PER_CAL_CONFIG_P0_START = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_PER_CAL_CONFIG_P0_ABORT_ON_ERR_EN = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_PER_CAL_CONFIG_P0_DD2_FIX_DIS = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_PC_PER_ERR_INJECT_P0_CA_PARITY = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_PER_ERR_INJECT_P0_HARD_ERROR = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_PER_ERR_INJECT_P0_HAS_FIRED = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_PER_ERR_INJECT_P0_RECUR_ERROR = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_PER_ERR_INJECT_P0_CONFIG_CNT = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_PER_ERR_INJECT_P0_CONFIG_CNT_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_PER_ERR_INJECT_P0_EN_PARITY_ERROR = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_PER_ERR_INJECT_P0_ERROR_THROWN_COUNT = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_PER_ERR_INJECT_P0_ERROR_THROWN_COUNT_LEN = 5 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_PC_PER_ZCAL_CONFIG_P0_ENA_RANK = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_PER_ZCAL_CONFIG_P0_ENA_RANK_LEN = 8 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_PER_ZCAL_CONFIG_P0_NEXT_RANK = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_PER_ZCAL_CONFIG_P0_NEXT_RANK_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_PER_ZCAL_CONFIG_P0_START = 59 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_PC_POWERDOWN_1_P0_MASTER = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_POWERDOWN_1_P0_DLL = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_POWERDOWN_1_P0_DLL_CLOCK_GATE = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_POWERDOWN_1_P0_DQS = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_POWERDOWN_1_P0_VPROTH = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_POWERDOWN_1_P0_KPRIME = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_POWERDOWN_1_P0_PORTPOWERDOWN = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_POWERDOWN_1_P0_ANALOG_INPUT_STAB = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_POWERDOWN_1_P0_ZCAL = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_POWERDOWN_1_P0_DELAY_LINE_CTL_OVERRIDE = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_POWERDOWN_1_P0_WR_FIFO_STAB = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_POWERDOWN_1_P0_RX = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_POWERDOWN_1_P0_DP_TX_TRISTATE = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_POWERDOWN_1_P0_ADR_TX_TRISTATE = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_POWERDOWN_1_P0_VREG_S = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_GROUP_EXT_P0_ADDR_MIRROR_RP0_TER = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_GROUP_EXT_P0_ADDR_MIRROR_RP0_QUA = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_GROUP_EXT_P0_ADDR_MIRROR_RP1_TER = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_GROUP_EXT_P0_ADDR_MIRROR_RP1_QUA = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_GROUP_EXT_P0_ADDR_MIRROR_RP2_TER = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_GROUP_EXT_P0_ADDR_MIRROR_RP2_QUA = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_GROUP_EXT_P0_ADDR_MIRROR_RP3_TER = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_GROUP_EXT_P0_ADDR_MIRROR_RP3_QUA = 55 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR0_P0_PRI = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR0_P0_PRI_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR0_P0_PRI_V = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR0_P0_SEC = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR0_P0_SEC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR0_P0_SEC_V = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR0_P0_PAIR1_PRI = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR0_P0_PAIR1_PRI_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR0_P0_PAIR1_PRI_V = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR0_P0_PAIR1_SEC = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR0_P0_PAIR1_SEC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR0_P0_PAIR1_SEC_V = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR1_P0_PAIR2_PRI = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR1_P0_PAIR2_PRI_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR1_P0_PAIR2_PRI_V = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR1_P0_PAIR2_SEC = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR1_P0_PAIR2_SEC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR1_P0_PAIR2_SEC_V = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR1_P0_PAIR3_PRI = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR1_P0_PAIR3_PRI_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR1_P0_PAIR3_PRI_V = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR1_P0_PAIR3_SEC = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR1_P0_PAIR3_SEC_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR1_P0_PAIR3_SEC_V = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR2_P0_PAIR0_TER = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR2_P0_PAIR0_TER_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR2_P0_PAIR0_TER_V = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR2_P0_PAIR0_QUA = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR2_P0_PAIR0_QUA_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR2_P0_PAIR0_QUA_V = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR2_P0_PAIR1_TER = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR2_P0_PAIR1_TER_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR2_P0_PAIR1_TER_V = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR2_P0_PAIR1_QUA = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR2_P0_PAIR1_QUA_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR2_P0_PAIR1_QUA_V = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR3_P0_PAIR2_TER = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR3_P0_PAIR2_TER_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR3_P0_PAIR2_TER_V = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR3_P0_PAIR2_QUA = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR3_P0_PAIR2_QUA_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR3_P0_PAIR2_QUA_V = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR3_P0_TER = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR3_P0_TER_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR3_P0_TER_V = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR3_P0_QUA = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR3_P0_QUA_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR3_P0_QUA_V = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_PC_RELOAD_VALUE0_P0_PERIODIC_CAL_REQ_EN = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_RELOAD_VALUE0_P0_PERIODIC = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_RELOAD_VALUE0_P0_PERIODIC_LEN = 15 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_PC_RESETS_P0_SYSCLK_RESET = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_RESETS_P0_PVT_OVERRIDE = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_RESETS_P0_ENABLE_ZCAL = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_RESETS_P0_VREF_85PER = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_RESETS_P0_DD2_WR_PRE_DLY_EXT = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_RESETS_P0_DD2_ADR_CG_DISABLE = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_RESETS_P0_DD2_WC_CA_ERROR_DISABLE = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_RESETS_P0_DD2_CAL_REG_CG_DISABLE = 59 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_RESETS_P0_DD2_CMDS_REG_CG_DISABLE = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_RESETS_P0_PBA_CW_F0RC06_DISABLE = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_RESETS_P0_DD2_RESET_READ_FIX_DISABLE = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_RESETS_P0_DD2_BABG_INV_FIX_DISABLE = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_PC_ZCAL_TIMER_P0_PERIODIC = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_ZCAL_TIMER_P0_PERIODIC_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_PC_ZCAL_TIMER_RELOAD_VALUE_P0_PERIODIC = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_PC_ZCAL_TIMER_RELOAD_VALUE_P0_PERIODIC_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_RC_CONFIG0_P0_GLOBAL_PHY_OFFSET = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_RC_CONFIG0_P0_GLOBAL_PHY_OFFSET_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_RC_CONFIG0_P0_PER_DUTY_CYCLE_SW = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_RC_CONFIG0_P0_PER_REPEAT_COUNT = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_RC_CONFIG0_P0_PER_REPEAT_COUNT_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_RC_CONFIG0_P0_PERFORM_RDCLK_ALIGN = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_RC_CONFIG0_P0_STAGGERED_PATTERN = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_RC_CONFIG1_P0_OUTER_LOOP_CNT = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_RC_CONFIG1_P0_OUTER_LOOP_CNT_LEN = 14 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_RC_CONFIG2_P0_CONSEC_PASS = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_RC_CONFIG2_P0_CONSEC_PASS_LEN = 5 ;
+static const uint8_t P9N2_MCA_DDRPHY_RC_CONFIG2_P0_ALLOW_RD_FIFO_AUTO_RESET = 59 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_RC_CONFIG3_P0_FINE_CAL_STEP_SIZE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_RC_CONFIG3_P0_FINE_CAL_STEP_SIZE_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_RC_CONFIG3_P0_COARSE_CAL_STEP_SIZE = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_RC_CONFIG3_P0_COARSE_CAL_STEP_SIZE_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_RC_CONFIG3_P0_DQ_SEL_QUAD = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_RC_CONFIG3_P0_DQ_SEL_QUAD_LEN = 2 ;
+static const uint8_t P9N2_MCA_DDRPHY_RC_CONFIG3_P0_DQ_SEL_LANE = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_RC_CONFIG3_P0_DQ_SEL_LANE_LEN = 3 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_RC_ERROR_MASK0_P0_RD_CNTL_MASK = 48 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_RC_ERROR_STATUS0_P0_ERROR = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_RC_ERROR_STATUS0_P0_DP16 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_RC_ERROR_STATUS0_P0_CNTR_UNDERFLOW = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_RC_ERROR_STATUS0_P0_CNTR_OVERFLOW = 51 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_RC_RDVREF_CONFIG0_P0_WAIT_TIME = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_RC_RDVREF_CONFIG0_P0_WAIT_TIME_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_RC_RDVREF_CONFIG1_P0_CMD_PRECEDE_TIME = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_RC_RDVREF_CONFIG1_P0_CMD_PRECEDE_TIME_LEN = 8 ;
+static const uint8_t P9N2_MCA_DDRPHY_RC_RDVREF_CONFIG1_P0_MPR_LOCATION = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_RC_RDVREF_CONFIG1_P0_MPR_LOCATION_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_RC_RDVREF_CONFIG1_P0_CALIBRATION_ENABLE = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_RC_RDVREF_CONFIG1_P0_SKIP_RDCENTERING = 61 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_CONFIG0_P0_MPR_PATTERN_BIT = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_CONFIG0_P0_TWO_CYCLE_ADDR_EN = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_CONFIG0_P0_MR_MASK_EN = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_CONFIG0_P0_MR_MASK_EN_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_CONFIG0_P0_DELAYED_PAR = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_CONFIG0_P0_LRDIMM_CONTEXT = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_CONFIG0_P0_FORCE_RESERVED = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_CONFIG0_P0_HALT_ROTATION = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_CONFIG0_P0_PAR_INVERT = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_CONFIG0_P0_IPW_SIDEAB_SEL = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_CONFIG0_P0_PAR_17_MASK = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_CONFIG0_P0_CW_MIRROR = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_ERROR_MASK0_P0_MULT_REQ_ERR_MASK = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_ERROR_MASK0_P0_INVALID_REQTYPE_ERR_MASK = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_ERROR_MASK0_P0_EARLY_REQ_ERR_MASK = 50 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_ERROR_STATUS0_P0_MULTIPLE_REQ = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_ERROR_STATUS0_P0_EARLY_REQ = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_ERROR_STATUS0_P0_MULTIPLE_REQ_SOURCE = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_ERROR_STATUS0_P0_MULTIPLE_REQ_SOURCE_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_ERROR_STATUS0_P0_INVALID_REQTYPE = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_ERROR_STATUS0_P0_INVALID_REQTYPE_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_ERROR_STATUS0_P0_INVALID_REQ_SOURCE = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_ERROR_STATUS0_P0_INVALID_REQ_SOURCE_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_ERROR_STATUS0_P0_EARLY_REQ_SOURCE = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_ERROR_STATUS0_P0_EARLY_REQ_SOURCE_LEN = 3 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_LPT_ADDR2_P0_ADDR2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_LPT_ADDR2_P0_ADDR2_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_LPT_ADDR3_P0_ADDR3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_LPT_ADDR3_P0_ADDR3_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_LPT_ADDR4_P0_ADDR4 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_LPT_ADDR4_P0_ADDR4_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_MEM_TIMING_PARAM0_P0_TMOD_CYCLES = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_MEM_TIMING_PARAM0_P0_TMOD_CYCLES_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_MEM_TIMING_PARAM0_P0_TRCD_CYCLES = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_MEM_TIMING_PARAM0_P0_TRCD_CYCLES_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_MEM_TIMING_PARAM0_P0_TRP_CYCLES = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_MEM_TIMING_PARAM0_P0_TRP_CYCLES_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_MEM_TIMING_PARAM0_P0_TRFC_CYCLES = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_MEM_TIMING_PARAM0_P0_TRFC_CYCLES_LEN = 4 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_MEM_TIMING_PARAM1_P0_TZQINIT_CYCLES = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_MEM_TIMING_PARAM1_P0_TZQINIT_CYCLES_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_MEM_TIMING_PARAM1_P0_TZQCS_CYCLES = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_MEM_TIMING_PARAM1_P0_TZQCS_CYCLES_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_MEM_TIMING_PARAM1_P0_TWLDQSEN_CYCLES = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_MEM_TIMING_PARAM1_P0_TWLDQSEN_CYCLES_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_MEM_TIMING_PARAM1_P0_TWRMRD_CYCLES = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_MEM_TIMING_PARAM1_P0_TWRMRD_CYCLES_LEN = 4 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_MEM_TIMING_PARAM2_P0_TODTLON_OFF_CYCLES = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_MEM_TIMING_PARAM2_P0_TODTLON_OFF_CYCLES_LEN = 4 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_ODT_DEFAULT_CONFIG_P0_DEF_VALUES = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_ODT_DEFAULT_CONFIG_P0_DEF_VALUES_LEN = 4 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_ODT_RD_CONFIG0_P0_VALUES0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_ODT_RD_CONFIG0_P0_VALUES0_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_ODT_RD_CONFIG0_P0_VALUES1 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_ODT_RD_CONFIG0_P0_VALUES1_LEN = 4 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_ODT_RD_CONFIG1_P0_VALUES2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_ODT_RD_CONFIG1_P0_VALUES2_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_ODT_RD_CONFIG1_P0_VALUES3 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_ODT_RD_CONFIG1_P0_VALUES3_LEN = 4 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_ODT_WR_CONFIG0_P0_VALUES0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_ODT_WR_CONFIG0_P0_VALUES0_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_ODT_WR_CONFIG0_P0_VALUES1 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_ODT_WR_CONFIG0_P0_VALUES1_LEN = 4 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_ODT_WR_CONFIG1_P0_VALUES2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_ODT_WR_CONFIG1_P0_VALUES2_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_ODT_WR_CONFIG1_P0_VALUES3 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_ODT_WR_CONFIG1_P0_VALUES3_LEN = 4 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_RD_WR_DATA0_P0_DATA_REG0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_RD_WR_DATA0_P0_DATA_REG0_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_RD_WR_DATA1_P0_DATA_REG1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_RD_WR_DATA1_P0_DATA_REG1_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_RESERVED_ADDR0_P0_ADDR0 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_RESERVED_ADDR0_P0_ADDR0_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_RESERVED_ADDR1_P0_ADDR1 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_RESERVED_ADDR1_P0_ADDR1_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_RESERVED_ADDR2_P0_ADDR2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_RESERVED_ADDR2_P0_ADDR2_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_RESERVED_ADDR3_P0_ADDR3 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_RESERVED_ADDR3_P0_ADDR3_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_RESERVED_ADDR4_P0_ADDR4 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_RESERVED_ADDR4_P0_ADDR4_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_WR_TERM_SWAP0_P0_RTT_WR0_NOM_VALUE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_WR_TERM_SWAP0_P0_RTT_WR0_NOM_VALUE_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_WR_TERM_SWAP0_P0_RTT_WR1_NOM_VALUE = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_WR_TERM_SWAP0_P0_RTT_WR1_NOM_VALUE_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_WR_TERM_SWAP0_P0_RTT_WR2_NOM_VALUE = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_WR_TERM_SWAP0_P0_RTT_WR2_NOM_VALUE_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_WR_TERM_SWAP0_P0_RTT_WR3_NOM_VALUE = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_WR_TERM_SWAP0_P0_RTT_WR3_NOM_VALUE_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_WR_TERM_SWAP0_P0_RTT_WR4_NOM_VALUE = 60 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_WR_TERM_SWAP0_P0_RTT_WR4_NOM_VALUE_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_WR_TERM_SWAP0_P0_DD2_VREF_FIX_DISABLE = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_WR_TERM_SWAP1_P0_RTT_WR5_NOM_VALUE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_WR_TERM_SWAP1_P0_RTT_WR5_NOM_VALUE_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_WR_TERM_SWAP1_P0_RTT_WR6_NOM_VALUE = 51 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_WR_TERM_SWAP1_P0_RTT_WR6_NOM_VALUE_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_WR_TERM_SWAP1_P0_RTT_WR7_NOM_VALUE = 54 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_WR_TERM_SWAP1_P0_RTT_WR7_NOM_VALUE_LEN = 3 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG0_P0_0_2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG0_P0_SEL_TYPE_0_2 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG0_P0_SEL_0_2 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG0_P0_SEL_0_2_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG0_P0_1_3 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG0_P0_SEL_TYPE_1_3 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG0_P0_SEL_1_3 = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG0_P0_SEL_1_3_LEN = 3 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG1_P0_0_2 = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG1_P0_SEL_TYPE_0_2 = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG1_P0_SEL_0_2 = 53 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG1_P0_SEL_0_2_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG1_P0_1_3 = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG1_P0_SEL_TYPE_1_3 = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG1_P0_SEL_1_3 = 61 ;
+static const uint8_t P9N2_MCA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG1_P0_SEL_1_3_LEN = 3 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_WC_CONFIG0_P0_TWLO_TWLOE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_WC_CONFIG0_P0_TWLO_TWLOE_LEN = 8 ;
+static const uint8_t P9N2_MCA_DDRPHY_WC_CONFIG0_P0_WL_ONE_DQS_PULSE = 56 ;
+static const uint8_t P9N2_MCA_DDRPHY_WC_CONFIG0_P0_FW_WR_RD = 57 ;
+static const uint8_t P9N2_MCA_DDRPHY_WC_CONFIG0_P0_FW_WR_RD_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_WC_CONFIG0_P0_CUSTOM_INIT_WRITE = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_WC_CONFIG1_P0_BIG_STEP = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_WC_CONFIG1_P0_BIG_STEP_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_WC_CONFIG1_P0_SMALL_STEP = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_WC_CONFIG1_P0_SMALL_STEP_LEN = 3 ;
+static const uint8_t P9N2_MCA_DDRPHY_WC_CONFIG1_P0_WR_PRE_DLY = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_WC_CONFIG1_P0_WR_PRE_DLY_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_WC_CONFIG2_P0_NUM_VALID_SAMPLES = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_WC_CONFIG2_P0_NUM_VALID_SAMPLES_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_WC_CONFIG2_P0_FW_RD_WR = 52 ;
+static const uint8_t P9N2_MCA_DDRPHY_WC_CONFIG2_P0_FW_RD_WR_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_WC_CONFIG2_P0_IPW_WR_WR = 58 ;
+static const uint8_t P9N2_MCA_DDRPHY_WC_CONFIG2_P0_IPW_WR_WR_LEN = 4 ;
+static const uint8_t P9N2_MCA_DDRPHY_WC_CONFIG2_P0_EN_RESET_DD2_FIX_DIS = 62 ;
+static const uint8_t P9N2_MCA_DDRPHY_WC_CONFIG2_P0_EN_RESET_WR_DELAY_WL = 63 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_WC_CONFIG3_P0_PDA_RANKDELAY_ENABLE = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_WC_CONFIG3_P0_MRS_CMD_DQ_ON = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_WC_CONFIG3_P0_MRS_CMD_DQ_ON_LEN = 6 ;
+static const uint8_t P9N2_MCA_DDRPHY_WC_CONFIG3_P0_MRS_CMD_DQ_OFF = 55 ;
+static const uint8_t P9N2_MCA_DDRPHY_WC_CONFIG3_P0_MRS_CMD_DQ_OFF_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_WC_ERROR_MASK0_P0_WR_CNTL_MASK = 48 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_WC_ERROR_STATUS0_P0_WR_CNTL = 48 ;
+
+static const uint8_t P9N2_MCA_DDRPHY_WC_RTT_WR_SWAP_ENABLE_P0_WL = 48 ;
+static const uint8_t P9N2_MCA_DDRPHY_WC_RTT_WR_SWAP_ENABLE_P0_CTR = 49 ;
+static const uint8_t P9N2_MCA_DDRPHY_WC_RTT_WR_SWAP_ENABLE_P0_CTR_VREF_COUNTER_RESET_VAL = 50 ;
+static const uint8_t P9N2_MCA_DDRPHY_WC_RTT_WR_SWAP_ENABLE_P0_CTR_VREF_COUNTER_RESET_VAL_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_DQS0R_CFG_BYTE0_SWIZZLE = 0 ;
+static const uint8_t P9N2_MCA_DQS0R_CFG_BYTE0_SWIZZLE_LEN = 11 ;
+static const uint8_t P9N2_MCA_DQS0R_CFG_BYTE1_SWIZZLE = 11 ;
+static const uint8_t P9N2_MCA_DQS0R_CFG_BYTE1_SWIZZLE_LEN = 11 ;
+static const uint8_t P9N2_MCA_DQS0R_CFG_BYTE2_SWIZZLE = 22 ;
+static const uint8_t P9N2_MCA_DQS0R_CFG_BYTE2_SWIZZLE_LEN = 11 ;
+static const uint8_t P9N2_MCA_DQS0R_CFG_BYTE3_SWIZZLE = 33 ;
+static const uint8_t P9N2_MCA_DQS0R_CFG_BYTE3_SWIZZLE_LEN = 11 ;
+static const uint8_t P9N2_MCA_DQS0R_CFG_BYTE4_SWIZZLE = 44 ;
+static const uint8_t P9N2_MCA_DQS0R_CFG_BYTE4_SWIZZLE_LEN = 11 ;
+
+static const uint8_t P9N2_MCA_DQS1R_CFG_BYTE5_SWIZZLE = 0 ;
+static const uint8_t P9N2_MCA_DQS1R_CFG_BYTE5_SWIZZLE_LEN = 11 ;
+static const uint8_t P9N2_MCA_DQS1R_CFG_BYTE6_SWIZZLE = 11 ;
+static const uint8_t P9N2_MCA_DQS1R_CFG_BYTE6_SWIZZLE_LEN = 11 ;
+static const uint8_t P9N2_MCA_DQS1R_CFG_BYTE7_SWIZZLE = 22 ;
+static const uint8_t P9N2_MCA_DQS1R_CFG_BYTE7_SWIZZLE_LEN = 11 ;
+static const uint8_t P9N2_MCA_DQS1R_CFG_BYTE8_SWIZZLE = 33 ;
+static const uint8_t P9N2_MCA_DQS1R_CFG_BYTE8_SWIZZLE_LEN = 11 ;
+static const uint8_t P9N2_MCA_DQS1R_CFG_ODD_RANK_SWIZZLE_EN = 44 ;
+
+static const uint8_t P9N2_MCA_EICR_ADDRESS = 0 ;
+static const uint8_t P9N2_MCA_EICR_ADDRESS_LEN = 37 ;
+static const uint8_t P9N2_MCA_EICR_RESERVED = 37 ;
+static const uint8_t P9N2_MCA_EICR_PERSIST = 38 ;
+static const uint8_t P9N2_MCA_EICR_PERSIST_LEN = 2 ;
+static const uint8_t P9N2_MCA_EICR_REGION = 40 ;
+static const uint8_t P9N2_MCA_EICR_REGION_LEN = 3 ;
+static const uint8_t P9N2_MCA_EICR_TYPE = 43 ;
+static const uint8_t P9N2_MCA_EICR_TYPE_LEN = 5 ;
+static const uint8_t P9N2_MCA_EICR_MISC = 48 ;
+static const uint8_t P9N2_MCA_EICR_MISC_LEN = 4 ;
+
+static const uint8_t P9N2_MCA_ELPR_LOG_FULL = 0 ;
+static const uint8_t P9N2_MCA_ELPR_LOG_POINTER = 2 ;
+static const uint8_t P9N2_MCA_ELPR_LOG_POINTER_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_WDF_FIR_MAINLINE_MPE_RANK_0_TO_7 = 0 ;
+static const uint8_t P9N2_MCA_WDF_FIR_MAINLINE_MPE_RANK_0_TO_7_LEN = 8 ;
+static const uint8_t P9N2_MCA_WDF_FIR_MAINLINE_NCE = 8 ;
+static const uint8_t P9N2_MCA_WDF_FIR_MAINLINE_TCE = 9 ;
+static const uint8_t P9N2_MCA_WDF_FIR_MAINLINE_SCE = 10 ;
+static const uint8_t P9N2_MCA_WDF_FIR_MAINLINE_MCE = 11 ;
+static const uint8_t P9N2_MCA_WDF_FIR_MAINLINE_SUE = 12 ;
+static const uint8_t P9N2_MCA_WDF_FIR_MAINLINE_AUE = 13 ;
+static const uint8_t P9N2_MCA_WDF_FIR_MAINLINE_UE = 14 ;
+static const uint8_t P9N2_MCA_WDF_FIR_MAINLINE_RCD = 15 ;
+static const uint8_t P9N2_MCA_WDF_FIR_MAINLINE_IAUE = 16 ;
+static const uint8_t P9N2_MCA_WDF_FIR_MAINLINE_IUE = 17 ;
+static const uint8_t P9N2_MCA_WDF_FIR_MAINLINE_IRCD = 18 ;
+static const uint8_t P9N2_MCA_WDF_FIR_MAINLINE_IMPE = 19 ;
+static const uint8_t P9N2_MCA_WDF_FIR_MAINTENANCE_MPE_RANK_0_TO_7 = 20 ;
+static const uint8_t P9N2_MCA_WDF_FIR_MAINTENANCE_MPE_RANK_0_TO_7_LEN = 8 ;
+static const uint8_t P9N2_MCA_WDF_FIR_MAINTENANCE_NCE = 28 ;
+static const uint8_t P9N2_MCA_WDF_FIR_MAINTENANCE_TCE = 29 ;
+static const uint8_t P9N2_MCA_WDF_FIR_MAINTENANCE_SCE = 30 ;
+static const uint8_t P9N2_MCA_WDF_FIR_MAINTENANCE_MCE = 31 ;
+static const uint8_t P9N2_MCA_WDF_FIR_MAINTENANCE_SUE = 32 ;
+static const uint8_t P9N2_MCA_WDF_FIR_MAINTENANCE_AUE = 33 ;
+static const uint8_t P9N2_MCA_WDF_FIR_MAINTENANCE_UE = 34 ;
+static const uint8_t P9N2_MCA_WDF_FIR_MAINTENANCE_RCD = 35 ;
+static const uint8_t P9N2_MCA_WDF_FIR_MAINTENANCE_IAUE = 36 ;
+static const uint8_t P9N2_MCA_WDF_FIR_MAINTENANCE_IUE = 37 ;
+static const uint8_t P9N2_MCA_WDF_FIR_MAINTENANCE_IRCD = 38 ;
+static const uint8_t P9N2_MCA_WDF_FIR_MAINTENANCE_IMPE = 39 ;
+static const uint8_t P9N2_MCA_WDF_FIR_SCOM_PARITY_CRC_SWIZZLE = 40 ;
+static const uint8_t P9N2_MCA_WDF_FIR_SCOM_PARITY_CLASS_STATUS = 41 ;
+static const uint8_t P9N2_MCA_WDF_FIR_SCOM_PARITY_CLASS_RECOVERABLE = 42 ;
+static const uint8_t P9N2_MCA_WDF_FIR_SCOM_PARITY_CLASS_UNRECOVERABLE = 43 ;
+static const uint8_t P9N2_MCA_WDF_FIR_ECC_CORRECTOR_INTERNAL_PARITY_ERROR = 44 ;
+static const uint8_t P9N2_MCA_WDF_FIR_WRITE_RMW_CE = 45 ;
+static const uint8_t P9N2_MCA_WDF_FIR_WRITE_RMW_UE = 46 ;
+static const uint8_t P9N2_MCA_WDF_FIR_WRITE_RMW_SUE = 47 ;
+static const uint8_t P9N2_MCA_WDF_FIR_WDF_OVERRUN_ERROR_0 = 48 ;
+static const uint8_t P9N2_MCA_WDF_FIR_WDF_OVERRUN_ERROR_1 = 49 ;
+static const uint8_t P9N2_MCA_WDF_FIR_WDF_SCOM_SEQUENCE_ERROR = 50 ;
+static const uint8_t P9N2_MCA_WDF_FIR_WDF_STATE_MACHINE_ERROR = 51 ;
+static const uint8_t P9N2_MCA_WDF_FIR_WDF_MISC_REGISTER_PARITY_ERROR = 52 ;
+static const uint8_t P9N2_MCA_WDF_FIR_WRT_SCOM_SEQUENCE_ERROR = 53 ;
+static const uint8_t P9N2_MCA_WDF_FIR_WRT_MISC_REGISTER_PARITY_ERROR = 54 ;
+static const uint8_t P9N2_MCA_WDF_FIR_ECC_GENERATOR_INTERNAL_PARITY_ERROR = 55 ;
+static const uint8_t P9N2_MCA_WDF_FIR_READ_BUFFER_OVERFLOW_ERROR = 56 ;
+static const uint8_t P9N2_MCA_WDF_FIR_WDF_ASYNC_INTERFACE_ERROR = 57 ;
+static const uint8_t P9N2_MCA_WDF_FIR_RESERVED_58 = 58 ;
+static const uint8_t P9N2_MCA_WDF_FIR_RESERVED_59 = 59 ;
+static const uint8_t P9N2_MCA_WDF_FIR_SCOM_PARITY_DEBUG_WAT = 60 ;
+static const uint8_t P9N2_MCA_WDF_FIR_RESERVED = 61 ;
+static const uint8_t P9N2_MCA_WDF_FIR_INTERNAL_SCOM_ERROR = 62 ;
+static const uint8_t P9N2_MCA_WDF_FIR_INTERNAL_SCOM_ERROR_COPY = 63 ;
+
+static const uint8_t P9N2_MCA_FIR_MAINLINE_MPE_RANK_0_TO_7 = 0 ;
+static const uint8_t P9N2_MCA_FIR_MAINLINE_MPE_RANK_0_TO_7_LEN = 8 ;
+static const uint8_t P9N2_MCA_FIR_MAINLINE_NCE = 8 ;
+static const uint8_t P9N2_MCA_FIR_MAINLINE_TCE = 9 ;
+static const uint8_t P9N2_MCA_FIR_MAINLINE_SCE = 10 ;
+static const uint8_t P9N2_MCA_FIR_MAINLINE_MCE = 11 ;
+static const uint8_t P9N2_MCA_FIR_MAINLINE_SUE = 12 ;
+static const uint8_t P9N2_MCA_FIR_MAINLINE_AUE = 13 ;
+static const uint8_t P9N2_MCA_FIR_MAINLINE_UE = 14 ;
+static const uint8_t P9N2_MCA_FIR_MAINLINE_RCD = 15 ;
+static const uint8_t P9N2_MCA_FIR_MAINLINE_IAUE = 16 ;
+static const uint8_t P9N2_MCA_FIR_MAINLINE_IUE = 17 ;
+static const uint8_t P9N2_MCA_FIR_MAINLINE_IRCD = 18 ;
+static const uint8_t P9N2_MCA_FIR_MAINLINE_IMPE = 19 ;
+static const uint8_t P9N2_MCA_FIR_MAINTENANCE_MPE_RANK_0_TO_7 = 20 ;
+static const uint8_t P9N2_MCA_FIR_MAINTENANCE_MPE_RANK_0_TO_7_LEN = 8 ;
+static const uint8_t P9N2_MCA_FIR_MAINTENANCE_NCE = 28 ;
+static const uint8_t P9N2_MCA_FIR_MAINTENANCE_TCE = 29 ;
+static const uint8_t P9N2_MCA_FIR_MAINTENANCE_SCE = 30 ;
+static const uint8_t P9N2_MCA_FIR_MAINTENANCE_MCE = 31 ;
+static const uint8_t P9N2_MCA_FIR_MAINTENANCE_SUE = 32 ;
+static const uint8_t P9N2_MCA_FIR_MAINTENANCE_AUE = 33 ;
+static const uint8_t P9N2_MCA_FIR_MAINTENANCE_UE = 34 ;
+static const uint8_t P9N2_MCA_FIR_MAINTENANCE_RCD = 35 ;
+static const uint8_t P9N2_MCA_FIR_MAINTENANCE_IAUE = 36 ;
+static const uint8_t P9N2_MCA_FIR_MAINTENANCE_IUE = 37 ;
+static const uint8_t P9N2_MCA_FIR_MAINTENANCE_IRCD = 38 ;
+static const uint8_t P9N2_MCA_FIR_MAINTENANCE_IMPE = 39 ;
+static const uint8_t P9N2_MCA_FIR_SCOM_PARITY_CRC_SWIZZLE = 40 ;
+static const uint8_t P9N2_MCA_FIR_SCOM_PARITY_CLASS_STATUS = 41 ;
+static const uint8_t P9N2_MCA_FIR_SCOM_PARITY_CLASS_RECOVERABLE = 42 ;
+static const uint8_t P9N2_MCA_FIR_SCOM_PARITY_CLASS_UNRECOVERABLE = 43 ;
+static const uint8_t P9N2_MCA_FIR_ECC_CORRECTOR_INTERNAL_PARITY_ERROR = 44 ;
+static const uint8_t P9N2_MCA_FIR_WRITE_RMW_CE = 45 ;
+static const uint8_t P9N2_MCA_FIR_WRITE_RMW_UE = 46 ;
+static const uint8_t P9N2_MCA_FIR_WRITE_RMW_SUE = 47 ;
+static const uint8_t P9N2_MCA_FIR_WDF_OVERRUN_ERROR_0 = 48 ;
+static const uint8_t P9N2_MCA_FIR_WDF_OVERRUN_ERROR_1 = 49 ;
+static const uint8_t P9N2_MCA_FIR_WDF_SCOM_SEQUENCE_ERROR = 50 ;
+static const uint8_t P9N2_MCA_FIR_WDF_STATE_MACHINE_ERROR = 51 ;
+static const uint8_t P9N2_MCA_FIR_WDF_MISC_REGISTER_PARITY_ERROR = 52 ;
+static const uint8_t P9N2_MCA_FIR_WRT_SCOM_SEQUENCE_ERROR = 53 ;
+static const uint8_t P9N2_MCA_FIR_WRT_MISC_REGISTER_PARITY_ERROR = 54 ;
+static const uint8_t P9N2_MCA_FIR_ECC_GENERATOR_INTERNAL_PARITY_ERROR = 55 ;
+static const uint8_t P9N2_MCA_FIR_READ_BUFFER_OVERFLOW_ERROR = 56 ;
+static const uint8_t P9N2_MCA_FIR_WDF_ASYNC_INTERFACE_ERROR = 57 ;
+static const uint8_t P9N2_MCA_FIR_RESERVED_58 = 58 ;
+static const uint8_t P9N2_MCA_FIR_RESERVED_59 = 59 ;
+static const uint8_t P9N2_MCA_FIR_SCOM_PARITY_DEBUG_WAT = 60 ;
+static const uint8_t P9N2_MCA_FIR_RESERVED = 61 ;
+static const uint8_t P9N2_MCA_FIR_INTERNAL_SCOM_ERROR = 62 ;
+static const uint8_t P9N2_MCA_FIR_INTERNAL_SCOM_ERROR_COPY = 63 ;
+
+static const uint8_t P9N2_MCA_FWMS0_MARK = 0 ;
+static const uint8_t P9N2_MCA_FWMS0_MARK_LEN = 8 ;
+static const uint8_t P9N2_MCA_FWMS0_TYPE = 8 ;
+static const uint8_t P9N2_MCA_FWMS0_REGION = 9 ;
+static const uint8_t P9N2_MCA_FWMS0_REGION_LEN = 3 ;
+static const uint8_t P9N2_MCA_FWMS0_ADDRESS = 12 ;
+static const uint8_t P9N2_MCA_FWMS0_ADDRESS_LEN = 11 ;
+static const uint8_t P9N2_MCA_FWMS0_EXIT_1 = 23 ;
+
+static const uint8_t P9N2_MCA_WREITE_FWMS1_MARK = 0 ;
+static const uint8_t P9N2_MCA_WREITE_FWMS1_MARK_LEN = 8 ;
+static const uint8_t P9N2_MCA_WREITE_FWMS1_TYPE = 8 ;
+static const uint8_t P9N2_MCA_WREITE_FWMS1_REGION = 9 ;
+static const uint8_t P9N2_MCA_WREITE_FWMS1_REGION_LEN = 3 ;
+static const uint8_t P9N2_MCA_WREITE_FWMS1_ADDRESS = 12 ;
+static const uint8_t P9N2_MCA_WREITE_FWMS1_ADDRESS_LEN = 11 ;
+static const uint8_t P9N2_MCA_WREITE_FWMS1_EXIT_1 = 23 ;
+
+static const uint8_t P9N2_MCA_FWMS2_MARK = 0 ;
+static const uint8_t P9N2_MCA_FWMS2_MARK_LEN = 8 ;
+static const uint8_t P9N2_MCA_FWMS2_TYPE = 8 ;
+static const uint8_t P9N2_MCA_FWMS2_REGION = 9 ;
+static const uint8_t P9N2_MCA_FWMS2_REGION_LEN = 3 ;
+static const uint8_t P9N2_MCA_FWMS2_ADDRESS = 12 ;
+static const uint8_t P9N2_MCA_FWMS2_ADDRESS_LEN = 11 ;
+static const uint8_t P9N2_MCA_FWMS2_EXIT_1 = 23 ;
+
+static const uint8_t P9N2_MCA_FWMS3_MARK = 0 ;
+static const uint8_t P9N2_MCA_FWMS3_MARK_LEN = 8 ;
+static const uint8_t P9N2_MCA_FWMS3_TYPE = 8 ;
+static const uint8_t P9N2_MCA_FWMS3_REGION = 9 ;
+static const uint8_t P9N2_MCA_FWMS3_REGION_LEN = 3 ;
+static const uint8_t P9N2_MCA_FWMS3_ADDRESS = 12 ;
+static const uint8_t P9N2_MCA_FWMS3_ADDRESS_LEN = 11 ;
+static const uint8_t P9N2_MCA_FWMS3_EXIT_1 = 23 ;
+
+static const uint8_t P9N2_MCA_FWMS4_MARK = 0 ;
+static const uint8_t P9N2_MCA_FWMS4_MARK_LEN = 8 ;
+static const uint8_t P9N2_MCA_FWMS4_TYPE = 8 ;
+static const uint8_t P9N2_MCA_FWMS4_REGION = 9 ;
+static const uint8_t P9N2_MCA_FWMS4_REGION_LEN = 3 ;
+static const uint8_t P9N2_MCA_FWMS4_ADDRESS = 12 ;
+static const uint8_t P9N2_MCA_FWMS4_ADDRESS_LEN = 11 ;
+static const uint8_t P9N2_MCA_FWMS4_EXIT_1 = 23 ;
+
+static const uint8_t P9N2_MCA_FWMS5_MARK = 0 ;
+static const uint8_t P9N2_MCA_FWMS5_MARK_LEN = 8 ;
+static const uint8_t P9N2_MCA_FWMS5_TYPE = 8 ;
+static const uint8_t P9N2_MCA_FWMS5_REGION = 9 ;
+static const uint8_t P9N2_MCA_FWMS5_REGION_LEN = 3 ;
+static const uint8_t P9N2_MCA_FWMS5_ADDRESS = 12 ;
+static const uint8_t P9N2_MCA_FWMS5_ADDRESS_LEN = 11 ;
+static const uint8_t P9N2_MCA_FWMS5_EXIT_1 = 23 ;
+
+static const uint8_t P9N2_MCA_FWMS6_MARK = 0 ;
+static const uint8_t P9N2_MCA_FWMS6_MARK_LEN = 8 ;
+static const uint8_t P9N2_MCA_FWMS6_TYPE = 8 ;
+static const uint8_t P9N2_MCA_FWMS6_REGION = 9 ;
+static const uint8_t P9N2_MCA_FWMS6_REGION_LEN = 3 ;
+static const uint8_t P9N2_MCA_FWMS6_ADDRESS = 12 ;
+static const uint8_t P9N2_MCA_FWMS6_ADDRESS_LEN = 11 ;
+static const uint8_t P9N2_MCA_FWMS6_EXIT_1 = 23 ;
+
+static const uint8_t P9N2_MCA_FWMS7_MARK = 0 ;
+static const uint8_t P9N2_MCA_FWMS7_MARK_LEN = 8 ;
+static const uint8_t P9N2_MCA_FWMS7_TYPE = 8 ;
+static const uint8_t P9N2_MCA_FWMS7_REGION = 9 ;
+static const uint8_t P9N2_MCA_FWMS7_REGION_LEN = 3 ;
+static const uint8_t P9N2_MCA_FWMS7_ADDRESS = 12 ;
+static const uint8_t P9N2_MCA_FWMS7_ADDRESS_LEN = 11 ;
+static const uint8_t P9N2_MCA_FWMS7_EXIT_1 = 23 ;
+
+static const uint8_t P9N2_MCA_HWMS0_CHIPMARK = 0 ;
+static const uint8_t P9N2_MCA_HWMS0_CHIPMARK_LEN = 8 ;
+static const uint8_t P9N2_MCA_HWMS0_CONFIRMED = 8 ;
+static const uint8_t P9N2_MCA_HWMS0_EXIT_1 = 9 ;
+
+static const uint8_t P9N2_MCA_WDF_HWMS1_CHIPMARK = 0 ;
+static const uint8_t P9N2_MCA_WDF_HWMS1_CHIPMARK_LEN = 8 ;
+static const uint8_t P9N2_MCA_WDF_HWMS1_CONFIRMED = 8 ;
+static const uint8_t P9N2_MCA_WDF_HWMS1_EXIT_1 = 9 ;
+
+static const uint8_t P9N2_MCA_HWMS2_CHIPMARK = 0 ;
+static const uint8_t P9N2_MCA_HWMS2_CHIPMARK_LEN = 8 ;
+static const uint8_t P9N2_MCA_HWMS2_CONFIRMED = 8 ;
+static const uint8_t P9N2_MCA_HWMS2_EXIT_1 = 9 ;
+
+static const uint8_t P9N2_MCA_HWMS3_CHIPMARK = 0 ;
+static const uint8_t P9N2_MCA_HWMS3_CHIPMARK_LEN = 8 ;
+static const uint8_t P9N2_MCA_HWMS3_CONFIRMED = 8 ;
+static const uint8_t P9N2_MCA_HWMS3_EXIT_1 = 9 ;
+
+static const uint8_t P9N2_MCA_HWMS4_CHIPMARK = 0 ;
+static const uint8_t P9N2_MCA_HWMS4_CHIPMARK_LEN = 8 ;
+static const uint8_t P9N2_MCA_HWMS4_CONFIRMED = 8 ;
+static const uint8_t P9N2_MCA_HWMS4_EXIT_1 = 9 ;
+
+static const uint8_t P9N2_MCA_HWMS5_CHIPMARK = 0 ;
+static const uint8_t P9N2_MCA_HWMS5_CHIPMARK_LEN = 8 ;
+static const uint8_t P9N2_MCA_HWMS5_CONFIRMED = 8 ;
+static const uint8_t P9N2_MCA_HWMS5_EXIT_1 = 9 ;
+
+static const uint8_t P9N2_MCA_HWMS6_CHIPMARK = 0 ;
+static const uint8_t P9N2_MCA_HWMS6_CHIPMARK_LEN = 8 ;
+static const uint8_t P9N2_MCA_HWMS6_CONFIRMED = 8 ;
+static const uint8_t P9N2_MCA_HWMS6_EXIT_1 = 9 ;
+
+static const uint8_t P9N2_MCA_HWMS7_CHIPMARK = 0 ;
+static const uint8_t P9N2_MCA_HWMS7_CHIPMARK_LEN = 8 ;
+static const uint8_t P9N2_MCA_HWMS7_CONFIRMED = 8 ;
+static const uint8_t P9N2_MCA_HWMS7_EXIT_1 = 9 ;
+
+static const uint8_t P9N2_MCA_IOM_PHY0_DDRPHY_FIR_ACTION0_REG_DDR = 54 ;
+static const uint8_t P9N2_MCA_IOM_PHY0_DDRPHY_FIR_ACTION0_REG_DDR_LEN = 8 ;
+
+static const uint8_t P9N2_MCA_IOM_PHY0_DDRPHY_FIR_ACTION1_REG_DDR = 54 ;
+static const uint8_t P9N2_MCA_IOM_PHY0_DDRPHY_FIR_ACTION1_REG_DDR_LEN = 8 ;
+
+static const uint8_t P9N2_MCA_IOM_PHY0_DDRPHY_FIR_MASK_REG_DDR_ERROR_0 = 54 ;
+static const uint8_t P9N2_MCA_IOM_PHY0_DDRPHY_FIR_MASK_REG_DDR_ERROR_1 = 55 ;
+static const uint8_t P9N2_MCA_IOM_PHY0_DDRPHY_FIR_MASK_REG_DDR_ERROR_2 = 56 ;
+static const uint8_t P9N2_MCA_IOM_PHY0_DDRPHY_FIR_MASK_REG_DDR_ERROR_3 = 57 ;
+static const uint8_t P9N2_MCA_IOM_PHY0_DDRPHY_FIR_MASK_REG_DDR_ERROR_4 = 58 ;
+static const uint8_t P9N2_MCA_IOM_PHY0_DDRPHY_FIR_MASK_REG_DDR_ERROR_5 = 59 ;
+static const uint8_t P9N2_MCA_IOM_PHY0_DDRPHY_FIR_MASK_REG_DDR_ERROR_6 = 60 ;
+static const uint8_t P9N2_MCA_IOM_PHY0_DDRPHY_FIR_MASK_REG_DDR_ERROR_7 = 61 ;
+
+static const uint8_t P9N2_MCA_IOM_PHY0_DDRPHY_FIR_REG_DDR_ERROR_0 = 54 ;
+static const uint8_t P9N2_MCA_IOM_PHY0_DDRPHY_FIR_REG_DDR_ERROR_1 = 55 ;
+static const uint8_t P9N2_MCA_IOM_PHY0_DDRPHY_FIR_REG_DDR_ERROR_2 = 56 ;
+static const uint8_t P9N2_MCA_IOM_PHY0_DDRPHY_FIR_REG_DDR_ERROR_3 = 57 ;
+static const uint8_t P9N2_MCA_IOM_PHY0_DDRPHY_FIR_REG_DDR_ERROR_4 = 58 ;
+static const uint8_t P9N2_MCA_IOM_PHY0_DDRPHY_FIR_REG_DDR_ERROR_5 = 59 ;
+static const uint8_t P9N2_MCA_IOM_PHY0_DDRPHY_FIR_REG_DDR_ERROR_6 = 60 ;
+static const uint8_t P9N2_MCA_IOM_PHY0_DDRPHY_FIR_REG_DDR_ERROR_7 = 61 ;
+
+static const uint8_t P9N2_MCA_IOM_PHY0_DDRPHY_FIR_WOF_REG_DDR = 54 ;
+static const uint8_t P9N2_MCA_IOM_PHY0_DDRPHY_FIR_WOF_REG_DDR_LEN = 8 ;
+
+static const uint8_t P9N2_MCA_MASK_FIR = 0 ;
+static const uint8_t P9N2_MCA_MASK_FIR_LEN = 64 ;
+
+static const uint8_t P9N2_MCA_MBACALFIRQ_MBA_RECOVERABLE_ERROR = 0 ;
+static const uint8_t P9N2_MCA_MBACALFIRQ_MBA_NONRECOVERABLE_ERROR = 1 ;
+static const uint8_t P9N2_MCA_MBACALFIRQ_REFRESH_OVERRUN = 2 ;
+static const uint8_t P9N2_MCA_MBACALFIRQ_WAT_ERROR = 3 ;
+static const uint8_t P9N2_MCA_MBACALFIRQ_RCD_PARITY_ERROR = 4 ;
+static const uint8_t P9N2_MCA_MBACALFIRQ_DDR_CAL_TIMEOUT_ERR = 5 ;
+static const uint8_t P9N2_MCA_MBACALFIRQ_EMERGENCY_THROTTLE = 6 ;
+static const uint8_t P9N2_MCA_MBACALFIRQ_DDR_CAL_RESET_TIMEOUT = 7 ;
+static const uint8_t P9N2_MCA_MBACALFIRQ_DDR_MBA_EVENT_N = 8 ;
+static const uint8_t P9N2_MCA_MBACALFIRQ_WRQ_RRQ_HANG_ERR = 9 ;
+static const uint8_t P9N2_MCA_MBACALFIRQ_SM_1HOT_ERR = 10 ;
+static const uint8_t P9N2_MCA_MBACALFIRQ_ASYNC_IF_ERROR = 11 ;
+static const uint8_t P9N2_MCA_MBACALFIRQ_CMD_PARITY_ERROR = 12 ;
+static const uint8_t P9N2_MCA_MBACALFIRQ_PORT_FAIL = 13 ;
+static const uint8_t P9N2_MCA_MBACALFIRQ_RCD_CAL_PARITY_ERROR = 14 ;
+static const uint8_t P9N2_MCA_MBACALFIRQ_DEBUG_PARITY_ERROR = 15 ;
+static const uint8_t P9N2_MCA_MBACALFIRQ_INTERNAL_SCOM_ERROR = 16 ;
+static const uint8_t P9N2_MCA_MBACALFIRQ_INTERNAL_SCOM_ERROR_COPY = 17 ;
+
+static const uint8_t P9N2_MCA_MBACALFIR_ACTION0_FIR = 0 ;
+static const uint8_t P9N2_MCA_MBACALFIR_ACTION0_FIR_LEN = 18 ;
+
+static const uint8_t P9N2_MCA_MBACALFIR_ACTION1_FIR = 0 ;
+static const uint8_t P9N2_MCA_MBACALFIR_ACTION1_FIR_LEN = 18 ;
+
+static const uint8_t P9N2_MCA_MBACALFIR_MASK_MBA_RECOVERABLE_ERROR = 0 ;
+static const uint8_t P9N2_MCA_MBACALFIR_MASK_MBA_NONRECOVERABLE_ERROR = 1 ;
+static const uint8_t P9N2_MCA_MBACALFIR_MASK_REFRESH_OVERRUN = 2 ;
+static const uint8_t P9N2_MCA_MBACALFIR_MASK_WAT_ERROR = 3 ;
+static const uint8_t P9N2_MCA_MBACALFIR_MASK_RCD_PARITY_ERROR = 4 ;
+static const uint8_t P9N2_MCA_MBACALFIR_MASK_DDR_CAL_TIMEOUT_ERR = 5 ;
+static const uint8_t P9N2_MCA_MBACALFIR_MASK_EMERGENCY_THROTTLE = 6 ;
+static const uint8_t P9N2_MCA_MBACALFIR_MASK_DDR_CAL_RESET_TIMEOUT = 7 ;
+static const uint8_t P9N2_MCA_MBACALFIR_MASK_DDR_MBA_EVENT_N = 8 ;
+static const uint8_t P9N2_MCA_MBACALFIR_MASK_WRQ_RRQ_HANG_ERR = 9 ;
+static const uint8_t P9N2_MCA_MBACALFIR_MASK_SM_1HOT_ERR = 10 ;
+static const uint8_t P9N2_MCA_MBACALFIR_MASK_ASYNC_IF_ERROR = 11 ;
+static const uint8_t P9N2_MCA_MBACALFIR_MASK_CMD_PARITY_ERROR = 12 ;
+static const uint8_t P9N2_MCA_MBACALFIR_MASK_MBACALFIRQ_PORT_FAIL = 13 ;
+static const uint8_t P9N2_MCA_MBACALFIR_MASK_MBACALFIRQ_RCD_CAL_PARITY_ERROR = 14 ;
+static const uint8_t P9N2_MCA_MBACALFIR_MASK_MBACALFIRQ_DEBUG_PARITY_ERROR = 15 ;
+static const uint8_t P9N2_MCA_MBACALFIR_MASK_INTERNAL_SCOM_ERROR = 16 ;
+static const uint8_t P9N2_MCA_MBACALFIR_MASK_INTERNAL_SCOM_ERROR_COPY = 17 ;
+
+static const uint8_t P9N2_MCA_MBAREF0Q_CFG_REFRESH_ENABLE = 0 ;
+static const uint8_t P9N2_MCA_MBAREF0Q_CFG_REFRESH_INTERVAL_TIMEBASE_SELECT = 1 ;
+static const uint8_t P9N2_MCA_MBAREF0Q_CFG_REFRESH_INTERVAL_TIMEBASE_SELECT_LEN = 2 ;
+static const uint8_t P9N2_MCA_MBAREF0Q_CFG_PER_BANK_REFRESH = 3 ;
+static const uint8_t P9N2_MCA_MBAREF0Q_CFG_REFRESH_DEBUG_SELECT = 4 ;
+static const uint8_t P9N2_MCA_MBAREF0Q_CFG_REFRESH_PRIORITY_THRESHOLD = 5 ;
+static const uint8_t P9N2_MCA_MBAREF0Q_CFG_REFRESH_PRIORITY_THRESHOLD_LEN = 3 ;
+static const uint8_t P9N2_MCA_MBAREF0Q_CFG_REFRESH_INTERVAL = 8 ;
+static const uint8_t P9N2_MCA_MBAREF0Q_CFG_REFRESH_INTERVAL_LEN = 11 ;
+static const uint8_t P9N2_MCA_MBAREF0Q_CFG_REFRESH_RESET_INTERVAL = 19 ;
+static const uint8_t P9N2_MCA_MBAREF0Q_CFG_REFRESH_RESET_INTERVAL_LEN = 11 ;
+static const uint8_t P9N2_MCA_MBAREF0Q_CFG_TRFC = 30 ;
+static const uint8_t P9N2_MCA_MBAREF0Q_CFG_TRFC_LEN = 10 ;
+static const uint8_t P9N2_MCA_MBAREF0Q_CFG_REFR_TSV_STACK = 40 ;
+static const uint8_t P9N2_MCA_MBAREF0Q_CFG_REFR_TSV_STACK_LEN = 10 ;
+static const uint8_t P9N2_MCA_MBAREF0Q_CFG_REFR_CHECK_INTERVAL = 50 ;
+static const uint8_t P9N2_MCA_MBAREF0Q_CFG_REFR_CHECK_INTERVAL_LEN = 11 ;
+static const uint8_t P9N2_MCA_MBAREF0Q_CFG_TRFC_STACK_GATE_ALL_REF = 61 ;
+static const uint8_t P9N2_MCA_MBAREF0Q_RESERVED_62_63 = 62 ;
+static const uint8_t P9N2_MCA_MBAREF0Q_RESERVED_62_63_LEN = 2 ;
+
+static const uint8_t P9N2_MCA_MBAREFAQ_CFG_STATIC_IDLE_DLY = 0 ;
+static const uint8_t P9N2_MCA_MBAREFAQ_CFG_STATIC_IDLE_DLY_LEN = 4 ;
+static const uint8_t P9N2_MCA_MBAREFAQ_CFG_LP_SUB_CNT = 4 ;
+static const uint8_t P9N2_MCA_MBAREFAQ_CFG_LP_SUB_CNT_LEN = 2 ;
+static const uint8_t P9N2_MCA_MBAREFAQ_CFG_REFRESH_HP_RANK_BLOCK_ENABLE = 6 ;
+static const uint8_t P9N2_MCA_MBAREFAQ_CFG_HP_WR_GATE_LP_REF_DIS = 7 ;
+static const uint8_t P9N2_MCA_MBAREFAQ_RESERVED_8_9 = 8 ;
+static const uint8_t P9N2_MCA_MBAREFAQ_RESERVED_8_9_LEN = 2 ;
+static const uint8_t P9N2_MCA_MBAREFAQ_CFG_REF_BLOCK_STOP_DLY = 10 ;
+static const uint8_t P9N2_MCA_MBAREFAQ_CFG_REF_BLOCK_STOP_DLY_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_MBARPC0Q_RESERVED_0_1 = 0 ;
+static const uint8_t P9N2_MCA_MBARPC0Q_RESERVED_0_1_LEN = 2 ;
+static const uint8_t P9N2_MCA_MBARPC0Q_CFG_MIN_MAX_DOMAINS_ENABLE = 2 ;
+static const uint8_t P9N2_MCA_MBARPC0Q_CFG_MIN_MAX_DOMAINS = 3 ;
+static const uint8_t P9N2_MCA_MBARPC0Q_CFG_MIN_MAX_DOMAINS_LEN = 3 ;
+static const uint8_t P9N2_MCA_MBARPC0Q_CFG_PUP_AVAIL = 6 ;
+static const uint8_t P9N2_MCA_MBARPC0Q_CFG_PUP_AVAIL_LEN = 5 ;
+static const uint8_t P9N2_MCA_MBARPC0Q_CFG_PDN_PUP = 11 ;
+static const uint8_t P9N2_MCA_MBARPC0Q_CFG_PDN_PUP_LEN = 5 ;
+static const uint8_t P9N2_MCA_MBARPC0Q_CFG_PUP_PDN = 16 ;
+static const uint8_t P9N2_MCA_MBARPC0Q_CFG_PUP_PDN_LEN = 5 ;
+static const uint8_t P9N2_MCA_MBARPC0Q_CFG_QUAD_RANK_ENC = 21 ;
+static const uint8_t P9N2_MCA_MBARPC0Q_CFG_MIN_DOMAIN_REDUCTION_ENABLE = 22 ;
+static const uint8_t P9N2_MCA_MBARPC0Q_CFG_MIN_DOMAIN_REDUCTION_TIME = 23 ;
+static const uint8_t P9N2_MCA_MBARPC0Q_CFG_MIN_DOMAIN_REDUCTION_TIME_LEN = 10 ;
+static const uint8_t P9N2_MCA_MBARPC0Q_CFG_PUP_AFTER_ACTIVATE_WAIT_ENABLE = 33 ;
+static const uint8_t P9N2_MCA_MBARPC0Q_CFG_PUP_AFTER_ACTIVATE_WAIT_TIME = 34 ;
+static const uint8_t P9N2_MCA_MBARPC0Q_CFG_PUP_AFTER_ACTIVATE_WAIT_TIME_LEN = 8 ;
+static const uint8_t P9N2_MCA_MBARPC0Q_CFG_FORCE_SPARE_PUP = 42 ;
+static const uint8_t P9N2_MCA_MBARPC0Q_CFG_MIN_DOMAIN_REDUCTION_CNT_REFR_INT = 43 ;
+static const uint8_t P9N2_MCA_MBARPC0Q_CFG_EMER_MIN_MAX_DOMAIN = 44 ;
+static const uint8_t P9N2_MCA_MBARPC0Q_CFG_EMER_MIN_MAX_DOMAIN_LEN = 3 ;
+static const uint8_t P9N2_MCA_MBARPC0Q_CFG_PUP_ALL_WRITES_PENDING = 47 ;
+static const uint8_t P9N2_MCA_MBARPC0Q_CFG_ALWAYS_WAIT_ACT_TIME = 48 ;
+static const uint8_t P9N2_MCA_MBARPC0Q_RESERVED_49_63 = 49 ;
+static const uint8_t P9N2_MCA_MBARPC0Q_RESERVED_49_63_LEN = 15 ;
+
+static const uint8_t P9N2_MCA_MBASTR0Q_CFG_STR_ENABLE = 0 ;
+static const uint8_t P9N2_MCA_MBASTR0Q_CFG_DIS_CLK_IN_STR = 1 ;
+static const uint8_t P9N2_MCA_MBASTR0Q_CFG_ENTER_STR_TIME = 2 ;
+static const uint8_t P9N2_MCA_MBASTR0Q_CFG_ENTER_STR_TIME_LEN = 10 ;
+static const uint8_t P9N2_MCA_MBASTR0Q_CFG_TCKESR = 12 ;
+static const uint8_t P9N2_MCA_MBASTR0Q_CFG_TCKESR_LEN = 5 ;
+static const uint8_t P9N2_MCA_MBASTR0Q_CFG_TCKSRE = 17 ;
+static const uint8_t P9N2_MCA_MBASTR0Q_CFG_TCKSRE_LEN = 5 ;
+static const uint8_t P9N2_MCA_MBASTR0Q_CFG_TCKSRX = 22 ;
+static const uint8_t P9N2_MCA_MBASTR0Q_CFG_TCKSRX_LEN = 5 ;
+static const uint8_t P9N2_MCA_MBASTR0Q_CFG_TXSDLL = 27 ;
+static const uint8_t P9N2_MCA_MBASTR0Q_CFG_TXSDLL_LEN = 11 ;
+static const uint8_t P9N2_MCA_MBASTR0Q_CFG_TRFC_COUNTER_DIS = 38 ;
+static const uint8_t P9N2_MCA_MBASTR0Q_CFG_TRFC_COUNTER_DIS_LEN = 8 ;
+static const uint8_t P9N2_MCA_MBASTR0Q_CFG_SAFE_REFRESH_INTERVAL = 46 ;
+static const uint8_t P9N2_MCA_MBASTR0Q_CFG_SAFE_REFRESH_INTERVAL_LEN = 11 ;
+static const uint8_t P9N2_MCA_MBASTR0Q_CFG_OCC_DEADMAN_TIMER_SEL = 57 ;
+static const uint8_t P9N2_MCA_MBASTR0Q_CFG_OCC_DEADMAN_TIMER_SEL_LEN = 4 ;
+static const uint8_t P9N2_MCA_MBASTR0Q_CFG_OCC_DEADMAN_TB_SEL = 61 ;
+static const uint8_t P9N2_MCA_MBASTR0Q_RESERVED_62_63 = 62 ;
+static const uint8_t P9N2_MCA_MBASTR0Q_RESERVED_62_63_LEN = 2 ;
+
+static const uint8_t P9N2_MCBIST_MBAUER0Q_PORT_0_MAINLINE_AUE_ADDR_TRAP = 0 ;
+static const uint8_t P9N2_MCBIST_MBAUER0Q_PORT_0_MAINLINE_AUE_ADDR_TRAP_LEN = 38 ;
+static const uint8_t P9N2_MCBIST_MBAUER0Q_RESERVED_38_39 = 38 ;
+static const uint8_t P9N2_MCBIST_MBAUER0Q_RESERVED_38_39_LEN = 2 ;
+
+static const uint8_t P9N2_MCBIST_MBAUER1Q_PORT_1_MAINLINE_AUE_ADDR_TRAP = 0 ;
+static const uint8_t P9N2_MCBIST_MBAUER1Q_PORT_1_MAINLINE_AUE_ADDR_TRAP_LEN = 38 ;
+static const uint8_t P9N2_MCBIST_MBAUER1Q_RESERVED_38_39 = 38 ;
+static const uint8_t P9N2_MCBIST_MBAUER1Q_RESERVED_38_39_LEN = 2 ;
+
+static const uint8_t P9N2_MCBIST_MBAUER2Q_PORT_2_MAINLINE_AUE_ADDR_TRAP = 0 ;
+static const uint8_t P9N2_MCBIST_MBAUER2Q_PORT_2_MAINLINE_AUE_ADDR_TRAP_LEN = 38 ;
+static const uint8_t P9N2_MCBIST_MBAUER2Q_RESERVED_38_39 = 38 ;
+static const uint8_t P9N2_MCBIST_MBAUER2Q_RESERVED_38_39_LEN = 2 ;
+
+static const uint8_t P9N2_MCBIST_MBAUER3Q_PORT_3_MAINLINE_AUE_ADDR_TRAP = 0 ;
+static const uint8_t P9N2_MCBIST_MBAUER3Q_PORT_3_MAINLINE_AUE_ADDR_TRAP_LEN = 38 ;
+static const uint8_t P9N2_MCBIST_MBAUER3Q_RESERVED_38_39 = 38 ;
+static const uint8_t P9N2_MCBIST_MBAUER3Q_RESERVED_38_39_LEN = 2 ;
+
+static const uint8_t P9N2_MCA_MBA_CAL0Q_CFG_CAL_INTERVAL_TMR0_ENABLE = 0 ;
+static const uint8_t P9N2_MCA_MBA_CAL0Q_CFG_TIME_BASE_TMR0 = 1 ;
+static const uint8_t P9N2_MCA_MBA_CAL0Q_CFG_TIME_BASE_TMR0_LEN = 2 ;
+static const uint8_t P9N2_MCA_MBA_CAL0Q_CFG_INTERVAL_COUNTER_TMR0 = 3 ;
+static const uint8_t P9N2_MCA_MBA_CAL0Q_CFG_INTERVAL_COUNTER_TMR0_LEN = 9 ;
+static const uint8_t P9N2_MCA_MBA_CAL0Q_CFG_CAL_TMR0_CAL1_ENABLE = 12 ;
+static const uint8_t P9N2_MCA_MBA_CAL0Q_CFG_CAL_TMR0_CAL1_TYPE = 13 ;
+static const uint8_t P9N2_MCA_MBA_CAL0Q_CFG_CAL_TMR0_CAL1_TYPE_LEN = 4 ;
+static const uint8_t P9N2_MCA_MBA_CAL0Q_CFG_CAL_TMR0_CAL1_DDR_DONE = 17 ;
+static const uint8_t P9N2_MCA_MBA_CAL0Q_CFG_CAL_TMR0_CAL2_ENABLE = 18 ;
+static const uint8_t P9N2_MCA_MBA_CAL0Q_CFG_CAL_TMR0_CAL2_TYPE = 19 ;
+static const uint8_t P9N2_MCA_MBA_CAL0Q_CFG_CAL_TMR0_CAL2_TYPE_LEN = 4 ;
+static const uint8_t P9N2_MCA_MBA_CAL0Q_CFG_CAL_TMR0_CAL2_DDR_DONE = 23 ;
+static const uint8_t P9N2_MCA_MBA_CAL0Q_CFG_CAL_TMR0_CAL3_ENABLE = 24 ;
+static const uint8_t P9N2_MCA_MBA_CAL0Q_CFG_CAL_TMR0_CAL3_TYPE = 25 ;
+static const uint8_t P9N2_MCA_MBA_CAL0Q_CFG_CAL_TMR0_CAL3_TYPE_LEN = 4 ;
+static const uint8_t P9N2_MCA_MBA_CAL0Q_CFG_CAL_TMR0_CAL3_DDR_DONE = 29 ;
+static const uint8_t P9N2_MCA_MBA_CAL0Q_CFG_CAL_TMR0_Z_SYNC = 30 ;
+static const uint8_t P9N2_MCA_MBA_CAL0Q_CFG_CAL_TMR0_Z_SYNC_LEN = 9 ;
+static const uint8_t P9N2_MCA_MBA_CAL0Q_CFG_CAL_TMR0_DDR_RESET_TMR = 39 ;
+static const uint8_t P9N2_MCA_MBA_CAL0Q_CFG_CAL_TMR0_DDR_RESET_TMR_LEN = 8 ;
+static const uint8_t P9N2_MCA_MBA_CAL0Q_CFG_CAL_TMR0_DDR_RESET_TMR_TB = 47 ;
+static const uint8_t P9N2_MCA_MBA_CAL0Q_CFG_CAL_TMR0_DDR_RESET_TMR_TB_LEN = 2 ;
+static const uint8_t P9N2_MCA_MBA_CAL0Q_CFG_CAL_TMR0_DDR_RESET_ENABLE = 49 ;
+static const uint8_t P9N2_MCA_MBA_CAL0Q_CFG_CAL_TMR0_SINGLE_RANK = 50 ;
+static const uint8_t P9N2_MCA_MBA_CAL0Q_RESERVED_51 = 51 ;
+static const uint8_t P9N2_MCA_MBA_CAL0Q_INJECT_1HOT_SM_ERROR = 52 ;
+static const uint8_t P9N2_MCA_MBA_CAL0Q_CFG_CAL_SINGLE_PORT_MODE = 53 ;
+static const uint8_t P9N2_MCA_MBA_CAL0Q_CFG_CAL_SINGLE_PORT_MODE_LEN = 3 ;
+static const uint8_t P9N2_MCA_MBA_CAL0Q_DBG_BUS_BIT = 56 ;
+static const uint8_t P9N2_MCA_MBA_CAL0Q_RESET_RECOVER = 57 ;
+static const uint8_t P9N2_MCA_MBA_CAL0Q_CFG_RANK_SM_STALL_DISABLE = 58 ;
+static const uint8_t P9N2_MCA_MBA_CAL0Q_CFG_ENABLE_SPEC_ATTN = 59 ;
+static const uint8_t P9N2_MCA_MBA_CAL0Q_CFG_ENABLE_HOST_ATTN = 60 ;
+static const uint8_t P9N2_MCA_MBA_CAL0Q_RESERVED_61_63 = 61 ;
+static const uint8_t P9N2_MCA_MBA_CAL0Q_RESERVED_61_63_LEN = 3 ;
+
+static const uint8_t P9N2_MCA_MBA_CAL1Q_CFG_CAL_INTERVAL_TMR1_ENABLE = 0 ;
+static const uint8_t P9N2_MCA_MBA_CAL1Q_CFG_TIME_BASE_TMR1 = 1 ;
+static const uint8_t P9N2_MCA_MBA_CAL1Q_CFG_TIME_BASE_TMR1_LEN = 2 ;
+static const uint8_t P9N2_MCA_MBA_CAL1Q_CFG_INTERVAL_COUNTER_TMR1 = 3 ;
+static const uint8_t P9N2_MCA_MBA_CAL1Q_CFG_INTERVAL_COUNTER_TMR1_LEN = 9 ;
+static const uint8_t P9N2_MCA_MBA_CAL1Q_CFG_CAL_TMR1_CAL1_ENABLE = 12 ;
+static const uint8_t P9N2_MCA_MBA_CAL1Q_CFG_CAL_TMR1_CAL1_TYPE = 13 ;
+static const uint8_t P9N2_MCA_MBA_CAL1Q_CFG_CAL_TMR1_CAL1_TYPE_LEN = 4 ;
+static const uint8_t P9N2_MCA_MBA_CAL1Q_CFG_CAL_TMR1_CAL1_DDR_DONE = 17 ;
+static const uint8_t P9N2_MCA_MBA_CAL1Q_CFG_CAL_TMR1_CAL2_ENABLE = 18 ;
+static const uint8_t P9N2_MCA_MBA_CAL1Q_CFG_CAL_TMR1_CAL2_TYPE = 19 ;
+static const uint8_t P9N2_MCA_MBA_CAL1Q_CFG_CAL_TMR1_CAL2_TYPE_LEN = 4 ;
+static const uint8_t P9N2_MCA_MBA_CAL1Q_CFG_CAL_TMR1_CAL2_DDR_DONE = 23 ;
+static const uint8_t P9N2_MCA_MBA_CAL1Q_CFG_CAL_TMR1_CAL3_ENABLE = 24 ;
+static const uint8_t P9N2_MCA_MBA_CAL1Q_CFG_CAL_TMR1_CAL3_TYPE = 25 ;
+static const uint8_t P9N2_MCA_MBA_CAL1Q_CFG_CAL_TMR1_CAL3_TYPE_LEN = 4 ;
+static const uint8_t P9N2_MCA_MBA_CAL1Q_CFG_CAL_TMR1_CAL3_DDR_DONE = 29 ;
+static const uint8_t P9N2_MCA_MBA_CAL1Q_CFG_CAL_TMR1_Z_SYNC = 30 ;
+static const uint8_t P9N2_MCA_MBA_CAL1Q_CFG_CAL_TMR1_Z_SYNC_LEN = 9 ;
+static const uint8_t P9N2_MCA_MBA_CAL1Q_CFG_CAL_TMR1_SINGLE_RANK = 39 ;
+static const uint8_t P9N2_MCA_MBA_CAL1Q_CFG_CAL_RANK_ENABLE = 40 ;
+static const uint8_t P9N2_MCA_MBA_CAL1Q_CFG_CAL_RANK_ENABLE_LEN = 8 ;
+static const uint8_t P9N2_MCA_MBA_CAL1Q_CFG_CAL_TMR0_WAT_SYNC_ENABLE = 48 ;
+static const uint8_t P9N2_MCA_MBA_CAL1Q_CFG_CAL_TMR1_WAT_SYNC_ENABLE = 49 ;
+static const uint8_t P9N2_MCA_MBA_CAL1Q_CFG_CAL_TMR2_WAT_SYNC_ENABLE = 50 ;
+static const uint8_t P9N2_MCA_MBA_CAL1Q_CFG_CAL_DBG_TMR_SEL0 = 51 ;
+static const uint8_t P9N2_MCA_MBA_CAL1Q_CFG_CAL_DBG_TMR_SEL0_LEN = 2 ;
+static const uint8_t P9N2_MCA_MBA_CAL1Q_CFG_CAL_DBG_TMR_SEL1 = 53 ;
+static const uint8_t P9N2_MCA_MBA_CAL1Q_CFG_CAL_DBG_TMR_INT_SEL = 54 ;
+static const uint8_t P9N2_MCA_MBA_CAL1Q_CFG_CAL_DBG_TMR_INT_SEL_LEN = 3 ;
+static const uint8_t P9N2_MCA_MBA_CAL1Q_RESERVED_48_63 = 57 ;
+static const uint8_t P9N2_MCA_MBA_CAL1Q_RESERVED_48_63_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_MBA_CAL2Q_CFG_CAL_INTERVAL_TMR2_ENABLE = 0 ;
+static const uint8_t P9N2_MCA_MBA_CAL2Q_CFG_TIME_BASE_TMR2 = 1 ;
+static const uint8_t P9N2_MCA_MBA_CAL2Q_CFG_TIME_BASE_TMR2_LEN = 2 ;
+static const uint8_t P9N2_MCA_MBA_CAL2Q_CFG_INTERVAL_COUNTER_TMR2 = 3 ;
+static const uint8_t P9N2_MCA_MBA_CAL2Q_CFG_INTERVAL_COUNTER_TMR2_LEN = 9 ;
+static const uint8_t P9N2_MCA_MBA_CAL2Q_CFG_CAL_TMR2_CAL1_ENABLE = 12 ;
+static const uint8_t P9N2_MCA_MBA_CAL2Q_CFG_CAL_TMR2_CAL1_TYPE = 13 ;
+static const uint8_t P9N2_MCA_MBA_CAL2Q_CFG_CAL_TMR2_CAL1_TYPE_LEN = 4 ;
+static const uint8_t P9N2_MCA_MBA_CAL2Q_CFG_CAL_TMR2_CAL1_DDR_DONE = 17 ;
+static const uint8_t P9N2_MCA_MBA_CAL2Q_CFG_CAL_TMR2_CAL2_ENABLE = 18 ;
+static const uint8_t P9N2_MCA_MBA_CAL2Q_CFG_CAL_TMR2_CAL2_TYPE = 19 ;
+static const uint8_t P9N2_MCA_MBA_CAL2Q_CFG_CAL_TMR2_CAL2_TYPE_LEN = 4 ;
+static const uint8_t P9N2_MCA_MBA_CAL2Q_CFG_CAL_TMR2_CAL2_DDR_DONE = 23 ;
+static const uint8_t P9N2_MCA_MBA_CAL2Q_CFG_CAL_TMR2_CAL3_ENABLE = 24 ;
+static const uint8_t P9N2_MCA_MBA_CAL2Q_CFG_CAL_TMR2_CAL3_TYPE = 25 ;
+static const uint8_t P9N2_MCA_MBA_CAL2Q_CFG_CAL_TMR2_CAL3_TYPE_LEN = 4 ;
+static const uint8_t P9N2_MCA_MBA_CAL2Q_CFG_CAL_TMR2_CAL3_DDR_DONE = 29 ;
+static const uint8_t P9N2_MCA_MBA_CAL2Q_CFG_CAL_TMR2_Z_SYNC = 30 ;
+static const uint8_t P9N2_MCA_MBA_CAL2Q_CFG_CAL_TMR2_Z_SYNC_LEN = 9 ;
+static const uint8_t P9N2_MCA_MBA_CAL2Q_CFG_CAL_TMR2_SINGLE_RANK = 39 ;
+static const uint8_t P9N2_MCA_MBA_CAL2Q_CFG_CAL_TMR2_WAT_EVENT_ENABLE = 40 ;
+static const uint8_t P9N2_MCA_MBA_CAL2Q_RESERVED_41_63 = 41 ;
+static const uint8_t P9N2_MCA_MBA_CAL2Q_RESERVED_41_63_LEN = 23 ;
+
+static const uint8_t P9N2_MCA_MBA_CAL3Q_CFG_INTERNAL_ZQ_TB = 0 ;
+static const uint8_t P9N2_MCA_MBA_CAL3Q_CFG_INTERNAL_ZQ_TB_LEN = 2 ;
+static const uint8_t P9N2_MCA_MBA_CAL3Q_CFG_INTERNAL_ZQ_LENGTH = 2 ;
+static const uint8_t P9N2_MCA_MBA_CAL3Q_CFG_INTERNAL_ZQ_LENGTH_LEN = 8 ;
+static const uint8_t P9N2_MCA_MBA_CAL3Q_CFG_EXTERNAL_ZQ_TB = 10 ;
+static const uint8_t P9N2_MCA_MBA_CAL3Q_CFG_EXTERNAL_ZQ_TB_LEN = 2 ;
+static const uint8_t P9N2_MCA_MBA_CAL3Q_CFG_EXTERNAL_ZQ_LENGTH = 12 ;
+static const uint8_t P9N2_MCA_MBA_CAL3Q_CFG_EXTERNAL_ZQ_LENGTH_LEN = 8 ;
+static const uint8_t P9N2_MCA_MBA_CAL3Q_CFG_RDCLK_SYSCLK_TB = 20 ;
+static const uint8_t P9N2_MCA_MBA_CAL3Q_CFG_RDCLK_SYSCLK_TB_LEN = 2 ;
+static const uint8_t P9N2_MCA_MBA_CAL3Q_CFG_RDCLK_SYSCLK_LENGTH = 22 ;
+static const uint8_t P9N2_MCA_MBA_CAL3Q_CFG_RDCLK_SYSCLK_LENGTH_LEN = 8 ;
+static const uint8_t P9N2_MCA_MBA_CAL3Q_CFG_DQS_ALIGNMENT_TB = 30 ;
+static const uint8_t P9N2_MCA_MBA_CAL3Q_CFG_DQS_ALIGNMENT_TB_LEN = 2 ;
+static const uint8_t P9N2_MCA_MBA_CAL3Q_CFG_DQS_ALIGNMENT_LENGTH = 32 ;
+static const uint8_t P9N2_MCA_MBA_CAL3Q_CFG_DQS_ALIGNMENT_LENGTH_LEN = 8 ;
+static const uint8_t P9N2_MCA_MBA_CAL3Q_CFG_MPR_READEYE_TB = 40 ;
+static const uint8_t P9N2_MCA_MBA_CAL3Q_CFG_MPR_READEYE_TB_LEN = 2 ;
+static const uint8_t P9N2_MCA_MBA_CAL3Q_CFG_MPR_READEYE_LENGTH = 42 ;
+static const uint8_t P9N2_MCA_MBA_CAL3Q_CFG_MPR_READEYE_LENGTH_LEN = 8 ;
+static const uint8_t P9N2_MCA_MBA_CAL3Q_CFG_ALL_PERIODIC_TB = 50 ;
+static const uint8_t P9N2_MCA_MBA_CAL3Q_CFG_ALL_PERIODIC_TB_LEN = 2 ;
+static const uint8_t P9N2_MCA_MBA_CAL3Q_CFG_ALL_PERIODIC_LENGTH = 52 ;
+static const uint8_t P9N2_MCA_MBA_CAL3Q_CFG_ALL_PERIODIC_LENGTH_LEN = 8 ;
+static const uint8_t P9N2_MCA_MBA_CAL3Q_CFG_FREEZE_ON_PARITY_ERROR_DIS = 60 ;
+static const uint8_t P9N2_MCA_MBA_CAL3Q_RESERVED_61_63 = 61 ;
+static const uint8_t P9N2_MCA_MBA_CAL3Q_RESERVED_61_63_LEN = 3 ;
+
+static const uint8_t P9N2_MCA_MBA_DBG0Q_CFG_DBG_SRQ_ENABLE = 0 ;
+static const uint8_t P9N2_MCA_MBA_DBG0Q_CFG_DBG_SRQ_SEL0 = 1 ;
+static const uint8_t P9N2_MCA_MBA_DBG0Q_CFG_DBG_SRQ_SEL0_LEN = 3 ;
+static const uint8_t P9N2_MCA_MBA_DBG0Q_CFG_DBG_SRQ_SEL1 = 4 ;
+static const uint8_t P9N2_MCA_MBA_DBG0Q_CFG_DBG_SRQ_SEL1_LEN = 3 ;
+static const uint8_t P9N2_MCA_MBA_DBG0Q_CFG_DBG_SRQ_SEL2 = 7 ;
+static const uint8_t P9N2_MCA_MBA_DBG0Q_CFG_DBG_SRQ_SEL2_LEN = 3 ;
+static const uint8_t P9N2_MCA_MBA_DBG0Q_CFG_DBG_SRQ_SEL3 = 10 ;
+static const uint8_t P9N2_MCA_MBA_DBG0Q_CFG_DBG_SRQ_SEL3_LEN = 3 ;
+static const uint8_t P9N2_MCA_MBA_DBG0Q_CFG_DBG_SRQ_SEL4 = 13 ;
+static const uint8_t P9N2_MCA_MBA_DBG0Q_CFG_DBG_SRQ_SEL4_LEN = 3 ;
+static const uint8_t P9N2_MCA_MBA_DBG0Q_CFG_DBG_SRQ_SEL5 = 16 ;
+static const uint8_t P9N2_MCA_MBA_DBG0Q_CFG_DBG_SRQ_SEL5_LEN = 3 ;
+static const uint8_t P9N2_MCA_MBA_DBG0Q_CFG_DBG_SRQ_SEL6 = 19 ;
+static const uint8_t P9N2_MCA_MBA_DBG0Q_CFG_DBG_SRQ_SEL6_LEN = 3 ;
+static const uint8_t P9N2_MCA_MBA_DBG0Q_CFG_DBG_SRQ_SEL7 = 22 ;
+static const uint8_t P9N2_MCA_MBA_DBG0Q_CFG_DBG_SRQ_SEL7_LEN = 3 ;
+static const uint8_t P9N2_MCA_MBA_DBG0Q_RESERVED_25_33 = 25 ;
+static const uint8_t P9N2_MCA_MBA_DBG0Q_RESERVED_25_33_LEN = 9 ;
+static const uint8_t P9N2_MCA_MBA_DBG0Q_CFG_DBG_SRQ_SEL_OTHER_SRQ = 34 ;
+static const uint8_t P9N2_MCA_MBA_DBG0Q_CFG_DBG_SRQ_SEL_OTHER_SRQ_LEN = 8 ;
+static const uint8_t P9N2_MCA_MBA_DBG0Q_RESERVED_42_47 = 42 ;
+static const uint8_t P9N2_MCA_MBA_DBG0Q_RESERVED_42_47_LEN = 6 ;
+static const uint8_t P9N2_MCA_MBA_DBG0Q_CFG_WAT_FARB_RRQ_GT = 48 ;
+static const uint8_t P9N2_MCA_MBA_DBG0Q_CFG_WAT_FARB_RRQ_GT_LEN = 4 ;
+static const uint8_t P9N2_MCA_MBA_DBG0Q_CFG_WAT_FARB_WRQ_GT = 52 ;
+static const uint8_t P9N2_MCA_MBA_DBG0Q_CFG_WAT_FARB_WRQ_GT_LEN = 4 ;
+static const uint8_t P9N2_MCA_MBA_DBG0Q_CFG_WAT_FARB_REF_GT = 56 ;
+static const uint8_t P9N2_MCA_MBA_DBG0Q_CFG_WAT_FARB_REF_GT_LEN = 4 ;
+static const uint8_t P9N2_MCA_MBA_DBG0Q_CFG_WAT_FARB_CAL_GT = 60 ;
+static const uint8_t P9N2_MCA_MBA_DBG0Q_CFG_WAT_FARB_CAL_GT_LEN = 4 ;
+
+static const uint8_t P9N2_MCA_MBA_DBG1Q_CFG_WAT_FORCE_WR_ENTRY0_HP = 0 ;
+static const uint8_t P9N2_MCA_MBA_DBG1Q_CFG_WAT_FORCE_WR_ENTRY0_HP_LEN = 4 ;
+static const uint8_t P9N2_MCA_MBA_DBG1Q_CFG_WAT_FORCE_RD_ENTRY0_HP = 4 ;
+static const uint8_t P9N2_MCA_MBA_DBG1Q_CFG_WAT_FORCE_RD_ENTRY0_HP_LEN = 4 ;
+static const uint8_t P9N2_MCA_MBA_DBG1Q_CFG_WAT_FP_DIS = 8 ;
+static const uint8_t P9N2_MCA_MBA_DBG1Q_CFG_WAT_FP_DIS_LEN = 4 ;
+static const uint8_t P9N2_MCA_MBA_DBG1Q_CFG_WAT_DIS_RD_PG = 12 ;
+static const uint8_t P9N2_MCA_MBA_DBG1Q_CFG_WAT_DIS_RD_PG_LEN = 4 ;
+static const uint8_t P9N2_MCA_MBA_DBG1Q_CFG_WAT_DIS_WR_PG = 16 ;
+static const uint8_t P9N2_MCA_MBA_DBG1Q_CFG_WAT_DIS_WR_PG_LEN = 4 ;
+static const uint8_t P9N2_MCA_MBA_DBG1Q_CFG_WAT_PUP_ALL = 20 ;
+static const uint8_t P9N2_MCA_MBA_DBG1Q_CFG_WAT_PUP_ALL_LEN = 4 ;
+static const uint8_t P9N2_MCA_MBA_DBG1Q_CFG_WAT_EXIT_STR = 24 ;
+static const uint8_t P9N2_MCA_MBA_DBG1Q_CFG_WAT_EXIT_STR_LEN = 4 ;
+static const uint8_t P9N2_MCA_MBA_DBG1Q_CFG_WAT_REF_HP = 28 ;
+static const uint8_t P9N2_MCA_MBA_DBG1Q_CFG_WAT_REF_HP_LEN = 4 ;
+static const uint8_t P9N2_MCA_MBA_DBG1Q_CFG_WAT_REF_SYNC = 32 ;
+static const uint8_t P9N2_MCA_MBA_DBG1Q_CFG_WAT_REF_SYNC_LEN = 4 ;
+static const uint8_t P9N2_MCA_MBA_DBG1Q_CFG_WAT_REF_SAFE = 36 ;
+static const uint8_t P9N2_MCA_MBA_DBG1Q_CFG_WAT_REF_SAFE_LEN = 4 ;
+static const uint8_t P9N2_MCA_MBA_DBG1Q_CFG_WAT_CAL_SYNC = 40 ;
+static const uint8_t P9N2_MCA_MBA_DBG1Q_CFG_WAT_CAL_SYNC_LEN = 4 ;
+static const uint8_t P9N2_MCA_MBA_DBG1Q_CFG_WAT_RRQ_MNT_GT = 44 ;
+static const uint8_t P9N2_MCA_MBA_DBG1Q_CFG_WAT_RRQ_MNT_GT_LEN = 4 ;
+static const uint8_t P9N2_MCA_MBA_DBG1Q_CFG_WAT_WRQ_MNT_GT = 48 ;
+static const uint8_t P9N2_MCA_MBA_DBG1Q_CFG_WAT_WRQ_MNT_GT_LEN = 4 ;
+static const uint8_t P9N2_MCA_MBA_DBG1Q_CFG_WAT_SET_FIR = 52 ;
+static const uint8_t P9N2_MCA_MBA_DBG1Q_CFG_WAT_SET_FIR_LEN = 4 ;
+static const uint8_t P9N2_MCA_MBA_DBG1Q_CFG_WAT_EMER_TH = 56 ;
+static const uint8_t P9N2_MCA_MBA_DBG1Q_CFG_WAT_EMER_TH_LEN = 4 ;
+static const uint8_t P9N2_MCA_MBA_DBG1Q_CFG_WAT_START_RECOVERY = 60 ;
+static const uint8_t P9N2_MCA_MBA_DBG1Q_CFG_WAT_START_RECOVERY_LEN = 4 ;
+
+static const uint8_t P9N2_MCA_MBA_DSM0Q_CFG_RODT_START_DLY = 0 ;
+static const uint8_t P9N2_MCA_MBA_DSM0Q_CFG_RODT_START_DLY_LEN = 6 ;
+static const uint8_t P9N2_MCA_MBA_DSM0Q_CFG_RODT_END_DLY = 6 ;
+static const uint8_t P9N2_MCA_MBA_DSM0Q_CFG_RODT_END_DLY_LEN = 6 ;
+static const uint8_t P9N2_MCA_MBA_DSM0Q_CFG_WODT_START_DLY = 12 ;
+static const uint8_t P9N2_MCA_MBA_DSM0Q_CFG_WODT_START_DLY_LEN = 6 ;
+static const uint8_t P9N2_MCA_MBA_DSM0Q_CFG_WODT_END_DLY = 18 ;
+static const uint8_t P9N2_MCA_MBA_DSM0Q_CFG_WODT_END_DLY_LEN = 6 ;
+static const uint8_t P9N2_MCA_MBA_DSM0Q_CFG_WRDONE_DLY = 24 ;
+static const uint8_t P9N2_MCA_MBA_DSM0Q_CFG_WRDONE_DLY_LEN = 6 ;
+static const uint8_t P9N2_MCA_MBA_DSM0Q_CFG_WRDATA_DLY = 30 ;
+static const uint8_t P9N2_MCA_MBA_DSM0Q_CFG_WRDATA_DLY_LEN = 6 ;
+static const uint8_t P9N2_MCA_MBA_DSM0Q_CFG_RDTAG_DLY = 36 ;
+static const uint8_t P9N2_MCA_MBA_DSM0Q_CFG_RDTAG_DLY_LEN = 6 ;
+static const uint8_t P9N2_MCA_MBA_DSM0Q_CFG_RDTAG_MBX_CYCLE = 42 ;
+static const uint8_t P9N2_MCA_MBA_DSM0Q_CFG_RODT_BC4_END_DLY = 43 ;
+static const uint8_t P9N2_MCA_MBA_DSM0Q_CFG_RODT_BC4_END_DLY_LEN = 6 ;
+static const uint8_t P9N2_MCA_MBA_DSM0Q_CFG_WODT_BC4_END_DLY = 49 ;
+static const uint8_t P9N2_MCA_MBA_DSM0Q_CFG_WODT_BC4_END_DLY_LEN = 6 ;
+static const uint8_t P9N2_MCA_MBA_DSM0Q_RESERVED_55_63 = 55 ;
+static const uint8_t P9N2_MCA_MBA_DSM0Q_RESERVED_55_63_LEN = 9 ;
+
+static const uint8_t P9N2_MCA_MBA_ERR_REPORTQ_WRQ_HANG = 0 ;
+static const uint8_t P9N2_MCA_MBA_ERR_REPORTQ_RRQ_HANG = 1 ;
+static const uint8_t P9N2_MCA_MBA_ERR_REPORTQ_DSM_PE = 2 ;
+static const uint8_t P9N2_MCA_MBA_ERR_REPORTQ_TMR_PE = 3 ;
+static const uint8_t P9N2_MCA_MBA_ERR_REPORTQ_RRQ_PE = 4 ;
+static const uint8_t P9N2_MCA_MBA_ERR_REPORTQ_WRQ_PE = 5 ;
+static const uint8_t P9N2_MCA_MBA_ERR_REPORTQ_FARB_PE = 6 ;
+static const uint8_t P9N2_MCA_MBA_ERR_REPORTQ_PC_PE = 7 ;
+static const uint8_t P9N2_MCA_MBA_ERR_REPORTQ_CAL0_PE = 8 ;
+static const uint8_t P9N2_MCA_MBA_ERR_REPORTQ_CAL1_PE = 9 ;
+static const uint8_t P9N2_MCA_MBA_ERR_REPORTQ_CAL2_PE = 10 ;
+static const uint8_t P9N2_MCA_MBA_ERR_REPORTQ_CAL3_PE = 11 ;
+static const uint8_t P9N2_MCA_MBA_ERR_REPORTQ_DDR_IF_SM_1HOT = 12 ;
+static const uint8_t P9N2_MCA_MBA_ERR_REPORTQ_CAL_SM_1HOT = 13 ;
+static const uint8_t P9N2_MCA_MBA_ERR_REPORTQ_RANK_SM_1HOT = 14 ;
+static const uint8_t P9N2_MCA_MBA_ERR_REPORTQ_RESERVED_15 = 15 ;
+static const uint8_t P9N2_MCA_MBA_ERR_REPORTQ_PC_CAL_PCFSM_1HOT = 16 ;
+static const uint8_t P9N2_MCA_MBA_ERR_REPORTQ_FARB_CAL_RECVFSM_1HOT = 17 ;
+static const uint8_t P9N2_MCA_MBA_ERR_REPORTQ_RESERVED_18_23 = 18 ;
+static const uint8_t P9N2_MCA_MBA_ERR_REPORTQ_RESERVED_18_23_LEN = 6 ;
+static const uint8_t P9N2_MCA_MBA_ERR_REPORTQ_RCMD_ASYNC_IF = 24 ;
+static const uint8_t P9N2_MCA_MBA_ERR_REPORTQ_PF_PROMOTE_ASYNC_IF = 25 ;
+static const uint8_t P9N2_MCA_MBA_ERR_REPORTQ_CANCEL_ACK_ASYNC_IF = 26 ;
+static const uint8_t P9N2_MCA_MBA_ERR_REPORTQ_FARB_CMD_PE_HOLD_OUT = 27 ;
+static const uint8_t P9N2_MCA_MBA_ERR_REPORTQ_DSM_CMD_PE_HOLD_OUT = 28 ;
+static const uint8_t P9N2_MCA_MBA_ERR_REPORTQ_RESERVED_29_30 = 29 ;
+static const uint8_t P9N2_MCA_MBA_ERR_REPORTQ_RESERVED_29_30_LEN = 2 ;
+
+static const uint8_t P9N2_MCA_MBA_FARB0Q_CFG_MISR_BLOCK = 0 ;
+static const uint8_t P9N2_MCA_MBA_FARB0Q_CFG_MISR_BLOCK_LEN = 16 ;
+static const uint8_t P9N2_MCA_MBA_FARB0Q_CFG_MISR_FEEDBACK_ENABLE = 16 ;
+static const uint8_t P9N2_MCA_MBA_FARB0Q_CFG_2N_ADDR = 17 ;
+static const uint8_t P9N2_MCA_MBA_FARB0Q_CFG_ADDR_CLK_EN_ALWAYS_ON = 18 ;
+static const uint8_t P9N2_MCA_MBA_FARB0Q_CFG_ADDR_CLK_EN_SAME_AS_OE = 19 ;
+static const uint8_t P9N2_MCA_MBA_FARB0Q_CFG_ACT_SAME_RANK_HOLD_TIME = 20 ;
+static const uint8_t P9N2_MCA_MBA_FARB0Q_CFG_ACT_SAME_RANK_HOLD_TIME_LEN = 4 ;
+static const uint8_t P9N2_MCA_MBA_FARB0Q_CFG_MAX_READS_IN_A_ROW = 24 ;
+static const uint8_t P9N2_MCA_MBA_FARB0Q_CFG_MAX_READS_IN_A_ROW_LEN = 7 ;
+static const uint8_t P9N2_MCA_MBA_FARB0Q_CFG_MAX_WRITES_IN_A_ROW = 31 ;
+static const uint8_t P9N2_MCA_MBA_FARB0Q_CFG_MAX_WRITES_IN_A_ROW_LEN = 7 ;
+static const uint8_t P9N2_MCA_MBA_FARB0Q_CFG_PARITY_AFTER_CMD = 38 ;
+static const uint8_t P9N2_MCA_MBA_FARB0Q_RESERVED_39 = 39 ;
+static const uint8_t P9N2_MCA_MBA_FARB0Q_CFG_INJECT_PARITY_ERR_ADDR5 = 40 ;
+static const uint8_t P9N2_MCA_MBA_FARB0Q_CFG_BW_WINDOW_SIZE = 41 ;
+static const uint8_t P9N2_MCA_MBA_FARB0Q_CFG_BW_WINDOW_SIZE_LEN = 2 ;
+static const uint8_t P9N2_MCA_MBA_FARB0Q_CFG_PARITY_DETECT_TIME = 43 ;
+static const uint8_t P9N2_MCA_MBA_FARB0Q_CFG_PARITY_DETECT_TIME_LEN = 5 ;
+static const uint8_t P9N2_MCA_MBA_FARB0Q_CFG_RCD_PROTECTION_TIME = 48 ;
+static const uint8_t P9N2_MCA_MBA_FARB0Q_CFG_RCD_PROTECTION_TIME_LEN = 6 ;
+static const uint8_t P9N2_MCA_MBA_FARB0Q_CFG_DISABLE_RCD_RECOVERY = 54 ;
+static const uint8_t P9N2_MCA_MBA_FARB0Q_CFG_OE_ALWAYS_ON = 55 ;
+static const uint8_t P9N2_MCA_MBA_FARB0Q_CFG_FARB_CLOSE_ALL_PAGES = 56 ;
+static const uint8_t P9N2_MCA_MBA_FARB0Q_CFG_PORT_FAIL_DISABLE = 57 ;
+static const uint8_t P9N2_MCA_MBA_FARB0Q_CFG_OE_ALL_CKE_POWERED_DOWN = 58 ;
+static const uint8_t P9N2_MCA_MBA_FARB0Q_CFG_INJECT_PARITY_ERR_CONSTANT = 59 ;
+static const uint8_t P9N2_MCA_MBA_FARB0Q_CFG_FINISH_WR_BEFORE_RD = 60 ;
+static const uint8_t P9N2_MCA_MBA_FARB0Q_CFG_OPT_RD_SIZE = 61 ;
+static const uint8_t P9N2_MCA_MBA_FARB0Q_CFG_OPT_RD_SIZE_LEN = 3 ;
+
+static const uint8_t P9N2_MCA_MBA_FARB1Q_CFG_SLOT0_S0_CID = 0 ;
+static const uint8_t P9N2_MCA_MBA_FARB1Q_CFG_SLOT0_S0_CID_LEN = 3 ;
+static const uint8_t P9N2_MCA_MBA_FARB1Q_CFG_SLOT0_S1_CID = 3 ;
+static const uint8_t P9N2_MCA_MBA_FARB1Q_CFG_SLOT0_S1_CID_LEN = 3 ;
+static const uint8_t P9N2_MCA_MBA_FARB1Q_CFG_SLOT0_S2_CID = 6 ;
+static const uint8_t P9N2_MCA_MBA_FARB1Q_CFG_SLOT0_S2_CID_LEN = 3 ;
+static const uint8_t P9N2_MCA_MBA_FARB1Q_CFG_SLOT0_S3_CID = 9 ;
+static const uint8_t P9N2_MCA_MBA_FARB1Q_CFG_SLOT0_S3_CID_LEN = 3 ;
+static const uint8_t P9N2_MCA_MBA_FARB1Q_CFG_SLOT0_S4_CID = 12 ;
+static const uint8_t P9N2_MCA_MBA_FARB1Q_CFG_SLOT0_S4_CID_LEN = 3 ;
+static const uint8_t P9N2_MCA_MBA_FARB1Q_CFG_SLOT0_S5_CID = 15 ;
+static const uint8_t P9N2_MCA_MBA_FARB1Q_CFG_SLOT0_S5_CID_LEN = 3 ;
+static const uint8_t P9N2_MCA_MBA_FARB1Q_CFG_SLOT0_S6_CID = 18 ;
+static const uint8_t P9N2_MCA_MBA_FARB1Q_CFG_SLOT0_S6_CID_LEN = 3 ;
+static const uint8_t P9N2_MCA_MBA_FARB1Q_CFG_SLOT0_S7_CID = 21 ;
+static const uint8_t P9N2_MCA_MBA_FARB1Q_CFG_SLOT0_S7_CID_LEN = 3 ;
+static const uint8_t P9N2_MCA_MBA_FARB1Q_CFG_SLOT1_S0_CID = 24 ;
+static const uint8_t P9N2_MCA_MBA_FARB1Q_CFG_SLOT1_S0_CID_LEN = 3 ;
+static const uint8_t P9N2_MCA_MBA_FARB1Q_CFG_SLOT1_S1_CID = 27 ;
+static const uint8_t P9N2_MCA_MBA_FARB1Q_CFG_SLOT1_S1_CID_LEN = 3 ;
+static const uint8_t P9N2_MCA_MBA_FARB1Q_CFG_SLOT1_S2_CID = 30 ;
+static const uint8_t P9N2_MCA_MBA_FARB1Q_CFG_SLOT1_S2_CID_LEN = 3 ;
+static const uint8_t P9N2_MCA_MBA_FARB1Q_CFG_SLOT1_S3_CID = 33 ;
+static const uint8_t P9N2_MCA_MBA_FARB1Q_CFG_SLOT1_S3_CID_LEN = 3 ;
+static const uint8_t P9N2_MCA_MBA_FARB1Q_CFG_SLOT1_S4_CID = 36 ;
+static const uint8_t P9N2_MCA_MBA_FARB1Q_CFG_SLOT1_S4_CID_LEN = 3 ;
+static const uint8_t P9N2_MCA_MBA_FARB1Q_CFG_SLOT1_S5_CID = 39 ;
+static const uint8_t P9N2_MCA_MBA_FARB1Q_CFG_SLOT1_S5_CID_LEN = 3 ;
+static const uint8_t P9N2_MCA_MBA_FARB1Q_CFG_SLOT1_S6_CID = 42 ;
+static const uint8_t P9N2_MCA_MBA_FARB1Q_CFG_SLOT1_S6_CID_LEN = 3 ;
+static const uint8_t P9N2_MCA_MBA_FARB1Q_CFG_SLOT1_S7_CID = 45 ;
+static const uint8_t P9N2_MCA_MBA_FARB1Q_CFG_SLOT1_S7_CID_LEN = 3 ;
+static const uint8_t P9N2_MCA_MBA_FARB1Q_CFG_DIS_SMDR = 48 ;
+static const uint8_t P9N2_MCA_MBA_FARB1Q_CFG_DDR4_PARITY_ON_CID_DIS = 49 ;
+static const uint8_t P9N2_MCA_MBA_FARB1Q_CFG_RSV0 = 50 ;
+static const uint8_t P9N2_MCA_MBA_FARB1Q_CFG_RSV0_LEN = 14 ;
+
+static const uint8_t P9N2_MCA_MBA_FARB2Q_CFG_RANK0_RD_ODT = 0 ;
+static const uint8_t P9N2_MCA_MBA_FARB2Q_CFG_RANK0_RD_ODT_LEN = 4 ;
+static const uint8_t P9N2_MCA_MBA_FARB2Q_CFG_RANK1_RD_ODT = 4 ;
+static const uint8_t P9N2_MCA_MBA_FARB2Q_CFG_RANK1_RD_ODT_LEN = 4 ;
+static const uint8_t P9N2_MCA_MBA_FARB2Q_CFG_RANK2_RD_ODT = 8 ;
+static const uint8_t P9N2_MCA_MBA_FARB2Q_CFG_RANK2_RD_ODT_LEN = 4 ;
+static const uint8_t P9N2_MCA_MBA_FARB2Q_CFG_RANK3_RD_ODT = 12 ;
+static const uint8_t P9N2_MCA_MBA_FARB2Q_CFG_RANK3_RD_ODT_LEN = 4 ;
+static const uint8_t P9N2_MCA_MBA_FARB2Q_CFG_RANK4_RD_ODT = 16 ;
+static const uint8_t P9N2_MCA_MBA_FARB2Q_CFG_RANK4_RD_ODT_LEN = 4 ;
+static const uint8_t P9N2_MCA_MBA_FARB2Q_CFG_RANK5_RD_ODT = 20 ;
+static const uint8_t P9N2_MCA_MBA_FARB2Q_CFG_RANK5_RD_ODT_LEN = 4 ;
+static const uint8_t P9N2_MCA_MBA_FARB2Q_CFG_RANK6_RD_ODT = 24 ;
+static const uint8_t P9N2_MCA_MBA_FARB2Q_CFG_RANK6_RD_ODT_LEN = 4 ;
+static const uint8_t P9N2_MCA_MBA_FARB2Q_CFG_RANK7_RD_ODT = 28 ;
+static const uint8_t P9N2_MCA_MBA_FARB2Q_CFG_RANK7_RD_ODT_LEN = 4 ;
+static const uint8_t P9N2_MCA_MBA_FARB2Q_CFG_RANK0_WR_ODT = 32 ;
+static const uint8_t P9N2_MCA_MBA_FARB2Q_CFG_RANK0_WR_ODT_LEN = 4 ;
+static const uint8_t P9N2_MCA_MBA_FARB2Q_CFG_RANK1_WR_ODT = 36 ;
+static const uint8_t P9N2_MCA_MBA_FARB2Q_CFG_RANK1_WR_ODT_LEN = 4 ;
+static const uint8_t P9N2_MCA_MBA_FARB2Q_CFG_RANK2_WR_ODT = 40 ;
+static const uint8_t P9N2_MCA_MBA_FARB2Q_CFG_RANK2_WR_ODT_LEN = 4 ;
+static const uint8_t P9N2_MCA_MBA_FARB2Q_CFG_RANK3_WR_ODT = 44 ;
+static const uint8_t P9N2_MCA_MBA_FARB2Q_CFG_RANK3_WR_ODT_LEN = 4 ;
+static const uint8_t P9N2_MCA_MBA_FARB2Q_CFG_RANK4_WR_ODT = 48 ;
+static const uint8_t P9N2_MCA_MBA_FARB2Q_CFG_RANK4_WR_ODT_LEN = 4 ;
+static const uint8_t P9N2_MCA_MBA_FARB2Q_CFG_RANK5_WR_ODT = 52 ;
+static const uint8_t P9N2_MCA_MBA_FARB2Q_CFG_RANK5_WR_ODT_LEN = 4 ;
+static const uint8_t P9N2_MCA_MBA_FARB2Q_CFG_RANK6_WR_ODT = 56 ;
+static const uint8_t P9N2_MCA_MBA_FARB2Q_CFG_RANK6_WR_ODT_LEN = 4 ;
+static const uint8_t P9N2_MCA_MBA_FARB2Q_CFG_RANK7_WR_ODT = 60 ;
+static const uint8_t P9N2_MCA_MBA_FARB2Q_CFG_RANK7_WR_ODT_LEN = 4 ;
+
+static const uint8_t P9N2_MCA_MBA_FARB3Q_CFG_NM_N_PER_SLOT = 0 ;
+static const uint8_t P9N2_MCA_MBA_FARB3Q_CFG_NM_N_PER_SLOT_LEN = 15 ;
+static const uint8_t P9N2_MCA_MBA_FARB3Q_CFG_NM_N_PER_PORT = 15 ;
+static const uint8_t P9N2_MCA_MBA_FARB3Q_CFG_NM_N_PER_PORT_LEN = 16 ;
+static const uint8_t P9N2_MCA_MBA_FARB3Q_CFG_NM_M = 31 ;
+static const uint8_t P9N2_MCA_MBA_FARB3Q_CFG_NM_M_LEN = 14 ;
+static const uint8_t P9N2_MCA_MBA_FARB3Q_CFG_NM_RAS_WEIGHT = 45 ;
+static const uint8_t P9N2_MCA_MBA_FARB3Q_CFG_NM_RAS_WEIGHT_LEN = 3 ;
+static const uint8_t P9N2_MCA_MBA_FARB3Q_CFG_NM_CAS_WEIGHT = 48 ;
+static const uint8_t P9N2_MCA_MBA_FARB3Q_CFG_NM_CAS_WEIGHT_LEN = 3 ;
+static const uint8_t P9N2_MCA_MBA_FARB3Q_RESERVED_51 = 51 ;
+static const uint8_t P9N2_MCA_MBA_FARB3Q_RESERVED_52 = 52 ;
+static const uint8_t P9N2_MCA_MBA_FARB3Q_CFG_NM_CHANGE_AFTER_SYNC = 53 ;
+static const uint8_t P9N2_MCA_MBA_FARB3Q_RESERVED_54_63 = 54 ;
+static const uint8_t P9N2_MCA_MBA_FARB3Q_RESERVED_54_63_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_MBA_FARB4Q_CFG_NOISE_WAIT_TIME = 0 ;
+static const uint8_t P9N2_MCA_MBA_FARB4Q_CFG_NOISE_WAIT_TIME_LEN = 16 ;
+static const uint8_t P9N2_MCA_MBA_FARB4Q_CFG_PRECHARGE_WAIT_TIME = 16 ;
+static const uint8_t P9N2_MCA_MBA_FARB4Q_CFG_PRECHARGE_WAIT_TIME_LEN = 6 ;
+static const uint8_t P9N2_MCA_MBA_FARB4Q_CFG_SIM_FAST_NOISE_WINDOW = 22 ;
+static const uint8_t P9N2_MCA_MBA_FARB4Q_RESERVED_23_26 = 23 ;
+static const uint8_t P9N2_MCA_MBA_FARB4Q_RESERVED_23_26_LEN = 4 ;
+static const uint8_t P9N2_MCA_MBA_FARB4Q_EMERGENCY_N = 27 ;
+static const uint8_t P9N2_MCA_MBA_FARB4Q_EMERGENCY_N_LEN = 15 ;
+static const uint8_t P9N2_MCA_MBA_FARB4Q_EMERGENCY_M = 42 ;
+static const uint8_t P9N2_MCA_MBA_FARB4Q_EMERGENCY_M_LEN = 14 ;
+static const uint8_t P9N2_MCA_MBA_FARB4Q_RESERVED_56_63 = 56 ;
+static const uint8_t P9N2_MCA_MBA_FARB4Q_RESERVED_56_63_LEN = 8 ;
+
+static const uint8_t P9N2_MCA_MBA_FARB5Q_CFG_DDR_DPHY_NCLK = 0 ;
+static const uint8_t P9N2_MCA_MBA_FARB5Q_CFG_DDR_DPHY_NCLK_LEN = 2 ;
+static const uint8_t P9N2_MCA_MBA_FARB5Q_CFG_DDR_DPHY_PCLK = 2 ;
+static const uint8_t P9N2_MCA_MBA_FARB5Q_CFG_DDR_DPHY_PCLK_LEN = 2 ;
+static const uint8_t P9N2_MCA_MBA_FARB5Q_CFG_DDR_RESETN = 4 ;
+static const uint8_t P9N2_MCA_MBA_FARB5Q_CFG_CCS_ADDR_MUX_SEL = 5 ;
+static const uint8_t P9N2_MCA_MBA_FARB5Q_CFG_CCS_INST_RESET_ENABLE = 6 ;
+static const uint8_t P9N2_MCA_MBA_FARB5Q_CFG_GP_BIT_3_ENABLE = 7 ;
+static const uint8_t P9N2_MCA_MBA_FARB5Q_CFG_FORCE_MCLK_LOW_N = 8 ;
+static const uint8_t P9N2_MCA_MBA_FARB5Q_RESERVED_56_63 = 9 ;
+static const uint8_t P9N2_MCA_MBA_FARB5Q_RESERVED_56_63_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_MBA_FARB6Q_CFG_BW_SNAPSHOT = 0 ;
+static const uint8_t P9N2_MCA_MBA_FARB6Q_CFG_BW_SNAPSHOT_LEN = 11 ;
+static const uint8_t P9N2_MCA_MBA_FARB6Q_CFG_CKE_PUP_STATE = 11 ;
+static const uint8_t P9N2_MCA_MBA_FARB6Q_CFG_CKE_PUP_STATE_LEN = 4 ;
+static const uint8_t P9N2_MCA_MBA_FARB6Q_CFG_STR_STATE = 15 ;
+static const uint8_t P9N2_MCA_MBA_FARB6Q_CFG_RRQ_DEPTH = 16 ;
+static const uint8_t P9N2_MCA_MBA_FARB6Q_CFG_RRQ_DEPTH_LEN = 5 ;
+static const uint8_t P9N2_MCA_MBA_FARB6Q_CFG_WRQ_DEPTH = 21 ;
+static const uint8_t P9N2_MCA_MBA_FARB6Q_CFG_WRQ_DEPTH_LEN = 5 ;
+static const uint8_t P9N2_MCA_MBA_FARB6Q_CFG_RCD_PARITY_DLY = 26 ;
+static const uint8_t P9N2_MCA_MBA_FARB6Q_CFG_RCD_PARITY_DLY_LEN = 5 ;
+static const uint8_t P9N2_MCA_MBA_FARB6Q_CFG_EVENTN = 31 ;
+
+static const uint8_t P9N2_MCA_MBA_FARB7Q_EMER_THROTTLE_IP = 0 ;
+
+static const uint8_t P9N2_MCA_MBA_FARB8Q_SAFE_REFRESH_MODE = 0 ;
+
+static const uint8_t P9N2_MCBIST_MBA_MCBERRPTQ_MCB_FIR_CCS_ERR_HOLD_OUT = 0 ;
+static const uint8_t P9N2_MCBIST_MBA_MCBERRPTQ_MCB_FIR_MCBFSM_ERR_HOLD_OUT = 1 ;
+static const uint8_t P9N2_MCBIST_MBA_MCBERRPTQ_MCB_CNTLQ_PE_HOLD_OUT = 2 ;
+static const uint8_t P9N2_MCBIST_MBA_MCBERRPTQ_CCS_CNTLQ_PE_HOLD_OUT = 3 ;
+static const uint8_t P9N2_MCBIST_MBA_MCBERRPTQ_MCBCNTL_PE_HOLD_OUT = 4 ;
+static const uint8_t P9N2_MCBIST_MBA_MCBERRPTQ_MCBAGEN_PE_HOLD_OUT = 5 ;
+static const uint8_t P9N2_MCBIST_MBA_MCBERRPTQ_MAINT_CCS_PE_HOLD_OUT = 6 ;
+static const uint8_t P9N2_MCBIST_MBA_MCBERRPTQ_MCBDGEN_PE_HOLD_OUT = 7 ;
+static const uint8_t P9N2_MCBIST_MBA_MCBERRPTQ_MCBERR_SCOM_PE_HOLD_OUT = 8 ;
+static const uint8_t P9N2_MCBIST_MBA_MCBERRPTQ_ECC_MCBIST_OUT_OF_SYNC_HOLD_OUT = 9 ;
+static const uint8_t P9N2_MCBIST_MBA_MCBERRPTQ_SRQ_MCBIST_OUT_OF_SYNC_HOLD_OUT = 10 ;
+static const uint8_t P9N2_MCBIST_MBA_MCBERRPTQ_WRD_MCBIST_OUT_OF_SYNC_HOLD_OUT = 11 ;
+static const uint8_t P9N2_MCBIST_MBA_MCBERRPTQ_SRQ_CCS_UNEXPECTED_PORT_ACTIVE_HOLD_OUT = 12 ;
+static const uint8_t P9N2_MCBIST_MBA_MCBERRPTQ_FATAL_CNFG_HOLD_OUT = 13 ;
+
+static const uint8_t P9N2_MCA_MBA_PMU0Q_READ_COUNT = 0 ;
+static const uint8_t P9N2_MCA_MBA_PMU0Q_READ_COUNT_LEN = 32 ;
+static const uint8_t P9N2_MCA_MBA_PMU0Q_WRITE_COUNT = 32 ;
+static const uint8_t P9N2_MCA_MBA_PMU0Q_WRITE_COUNT_LEN = 32 ;
+
+static const uint8_t P9N2_MCA_MBA_PMU1Q_ACTIVATE_COUNT = 0 ;
+static const uint8_t P9N2_MCA_MBA_PMU1Q_ACTIVATE_COUNT_LEN = 32 ;
+static const uint8_t P9N2_MCA_MBA_PMU1Q_PU_COUNTS = 32 ;
+static const uint8_t P9N2_MCA_MBA_PMU1Q_PU_COUNTS_LEN = 32 ;
+
+static const uint8_t P9N2_MCA_MBA_PMU2Q_FRAME_COUNT = 0 ;
+static const uint8_t P9N2_MCA_MBA_PMU2Q_FRAME_COUNT_LEN = 32 ;
+
+static const uint8_t P9N2_MCA_MBA_PMU3Q_LOW_IDLE_THRESHOLD = 0 ;
+static const uint8_t P9N2_MCA_MBA_PMU3Q_LOW_IDLE_THRESHOLD_LEN = 16 ;
+static const uint8_t P9N2_MCA_MBA_PMU3Q_MED_IDLE_THRESHOLD = 16 ;
+static const uint8_t P9N2_MCA_MBA_PMU3Q_MED_IDLE_THRESHOLD_LEN = 16 ;
+static const uint8_t P9N2_MCA_MBA_PMU3Q_HIGH_IDLE_THRESHOLD = 32 ;
+static const uint8_t P9N2_MCA_MBA_PMU3Q_HIGH_IDLE_THRESHOLD_LEN = 32 ;
+
+static const uint8_t P9N2_MCA_MBA_PMU4Q_BASE_IDLE_COUNT = 0 ;
+static const uint8_t P9N2_MCA_MBA_PMU4Q_BASE_IDLE_COUNT_LEN = 32 ;
+static const uint8_t P9N2_MCA_MBA_PMU4Q_LOW_IDLE_COUNT = 32 ;
+static const uint8_t P9N2_MCA_MBA_PMU4Q_LOW_IDLE_COUNT_LEN = 32 ;
+
+static const uint8_t P9N2_MCA_MBA_PMU5Q_MED_IDLE_COUNT = 0 ;
+static const uint8_t P9N2_MCA_MBA_PMU5Q_MED_IDLE_COUNT_LEN = 32 ;
+static const uint8_t P9N2_MCA_MBA_PMU5Q_HIGH_IDLE_COUNT = 32 ;
+static const uint8_t P9N2_MCA_MBA_PMU5Q_HIGH_IDLE_COUNT_LEN = 32 ;
+
+static const uint8_t P9N2_MCA_MBA_PMU6Q_EVENT0_COUNTER = 0 ;
+static const uint8_t P9N2_MCA_MBA_PMU6Q_EVENT0_COUNTER_LEN = 16 ;
+static const uint8_t P9N2_MCA_MBA_PMU6Q_EVENT1_COUNTER = 16 ;
+static const uint8_t P9N2_MCA_MBA_PMU6Q_EVENT1_COUNTER_LEN = 16 ;
+static const uint8_t P9N2_MCA_MBA_PMU6Q_EVENT2_COUNTER = 32 ;
+static const uint8_t P9N2_MCA_MBA_PMU6Q_EVENT2_COUNTER_LEN = 16 ;
+static const uint8_t P9N2_MCA_MBA_PMU6Q_EVENT3_COUNTER = 48 ;
+static const uint8_t P9N2_MCA_MBA_PMU6Q_EVENT3_COUNTER_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_MBA_PMU7Q_CFG_EVENT0_SELECT = 0 ;
+static const uint8_t P9N2_MCA_MBA_PMU7Q_CFG_EVENT0_SELECT_LEN = 6 ;
+static const uint8_t P9N2_MCA_MBA_PMU7Q_CFG_EVENT1_SELECT = 6 ;
+static const uint8_t P9N2_MCA_MBA_PMU7Q_CFG_EVENT1_SELECT_LEN = 6 ;
+static const uint8_t P9N2_MCA_MBA_PMU7Q_CFG_EVENT2_SELECT = 12 ;
+static const uint8_t P9N2_MCA_MBA_PMU7Q_CFG_EVENT2_SELECT_LEN = 6 ;
+static const uint8_t P9N2_MCA_MBA_PMU7Q_CFG_EVENT3_SELECT = 18 ;
+static const uint8_t P9N2_MCA_MBA_PMU7Q_CFG_EVENT3_SELECT_LEN = 6 ;
+static const uint8_t P9N2_MCA_MBA_PMU7Q_CFG_PRESCALER_C0 = 24 ;
+static const uint8_t P9N2_MCA_MBA_PMU7Q_CFG_PRESCALER_C0_LEN = 2 ;
+static const uint8_t P9N2_MCA_MBA_PMU7Q_CFG_PRESCALER_C1 = 26 ;
+static const uint8_t P9N2_MCA_MBA_PMU7Q_CFG_PRESCALER_C1_LEN = 2 ;
+static const uint8_t P9N2_MCA_MBA_PMU7Q_CFG_PRESCALER_C2 = 28 ;
+static const uint8_t P9N2_MCA_MBA_PMU7Q_CFG_PRESCALER_C2_LEN = 2 ;
+static const uint8_t P9N2_MCA_MBA_PMU7Q_CFG_PRESCALER_C3 = 30 ;
+static const uint8_t P9N2_MCA_MBA_PMU7Q_CFG_PRESCALER_C3_LEN = 2 ;
+static const uint8_t P9N2_MCA_MBA_PMU7Q_CASCADE = 32 ;
+static const uint8_t P9N2_MCA_MBA_PMU7Q_CASCADE_LEN = 3 ;
+static const uint8_t P9N2_MCA_MBA_PMU7Q_FREEZE = 35 ;
+
+static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD0_TYPE = 0 ;
+static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD0_TYPE_LEN = 2 ;
+static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD0_MRANK_MATCH_EN = 2 ;
+static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD0_SRANK_MATCH_EN = 3 ;
+static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD0_BG_MATCH_EN = 4 ;
+static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD0_BANK_MATCH_EN = 5 ;
+static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD0_MRANK = 6 ;
+static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD0_MRANK_LEN = 3 ;
+static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD0_SRANK = 9 ;
+static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD0_SRANK_LEN = 3 ;
+static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD0_BG = 12 ;
+static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD0_BG_LEN = 2 ;
+static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD0_BANK = 14 ;
+static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD0_BANK_LEN = 3 ;
+static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD1_TYPE = 17 ;
+static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD1_TYPE_LEN = 2 ;
+static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD1_MRANK_MATCH_EN = 19 ;
+static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD1_SRANK_MATCH_EN = 20 ;
+static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD1_BG_MATCH_EN = 21 ;
+static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD1_BANK_MATCH_EN = 22 ;
+static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD1_MRANK = 23 ;
+static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD1_MRANK_LEN = 3 ;
+static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD1_SRANK = 26 ;
+static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD1_SRANK_LEN = 3 ;
+static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD1_BG = 29 ;
+static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD1_BG_LEN = 2 ;
+static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD1_BANK = 31 ;
+static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD1_BANK_LEN = 3 ;
+static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD2_TYPE = 34 ;
+static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD2_TYPE_LEN = 2 ;
+static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD2_MRANK_MATCH_EN = 36 ;
+static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD2_SRANK_MATCH_EN = 37 ;
+static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD2_BG_MATCH_EN = 38 ;
+static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD2_BANK_MATCH_EN = 39 ;
+static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD2_MRANK = 40 ;
+static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD2_MRANK_LEN = 3 ;
+static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD2_SRANK = 43 ;
+static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD2_SRANK_LEN = 3 ;
+static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD2_BG = 46 ;
+static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD2_BG_LEN = 2 ;
+static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD2_BANK = 48 ;
+static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD2_BANK_LEN = 3 ;
+static const uint8_t P9N2_MCA_MBA_PMU8Q_RESERVED_51_63 = 51 ;
+static const uint8_t P9N2_MCA_MBA_PMU8Q_RESERVED_51_63_LEN = 13 ;
+
+static const uint8_t P9N2_MCA_MBA_RRQ0Q_CFG_RRQ_SKIP_LIMIT = 0 ;
+static const uint8_t P9N2_MCA_MBA_RRQ0Q_CFG_RRQ_SKIP_LIMIT_LEN = 6 ;
+static const uint8_t P9N2_MCA_MBA_RRQ0Q_CFG_RRQ_FIFO_MODE = 6 ;
+static const uint8_t P9N2_MCA_MBA_RRQ0Q_CFG_RRQ_SINGLE_THREAD_MODE = 7 ;
+static const uint8_t P9N2_MCA_MBA_RRQ0Q_RESERVED_8_10 = 8 ;
+static const uint8_t P9N2_MCA_MBA_RRQ0Q_RESERVED_8_10_LEN = 3 ;
+static const uint8_t P9N2_MCA_MBA_RRQ0Q_CFG_DISABLE_RD_PG_MODE = 11 ;
+static const uint8_t P9N2_MCA_MBA_RRQ0Q_CFG_DISABLE_FAST_PATH = 12 ;
+static const uint8_t P9N2_MCA_MBA_RRQ0Q_CFG_RD_IDLE_ALLOW_WR = 13 ;
+static const uint8_t P9N2_MCA_MBA_RRQ0Q_CFG_RD_IDLE_ALLOW_WR_LEN = 11 ;
+static const uint8_t P9N2_MCA_MBA_RRQ0Q_CFG_RDBUFF_CAPACITY_LIMIT = 24 ;
+static const uint8_t P9N2_MCA_MBA_RRQ0Q_CFG_RDBUFF_CAPACITY_LIMIT_LEN = 6 ;
+static const uint8_t P9N2_MCA_MBA_RRQ0Q_CFG_RMWBUFF_CAPACITY_LIMIT = 30 ;
+static const uint8_t P9N2_MCA_MBA_RRQ0Q_CFG_RMWBUFF_CAPACITY_LIMIT_LEN = 7 ;
+static const uint8_t P9N2_MCA_MBA_RRQ0Q_RESERVED_37_56 = 37 ;
+static const uint8_t P9N2_MCA_MBA_RRQ0Q_RESERVED_37_56_LEN = 20 ;
+static const uint8_t P9N2_MCA_MBA_RRQ0Q_CFG_RRQ_ACT_NUM_READS_PENDING = 57 ;
+static const uint8_t P9N2_MCA_MBA_RRQ0Q_CFG_RRQ_ACT_NUM_READS_PENDING_LEN = 4 ;
+static const uint8_t P9N2_MCA_MBA_RRQ0Q_CFG_INJ_CANCEL_ACK_ERR = 61 ;
+static const uint8_t P9N2_MCA_MBA_RRQ0Q_CFG_RRQ_ENTRY0_ENABLE = 62 ;
+static const uint8_t P9N2_MCA_MBA_RRQ0Q_RESERVED_63 = 63 ;
+
+static const uint8_t P9N2_MCA_MBA_TMR0Q_RRDM_DLY = 0 ;
+static const uint8_t P9N2_MCA_MBA_TMR0Q_RRDM_DLY_LEN = 4 ;
+static const uint8_t P9N2_MCA_MBA_TMR0Q_RRSMSR_DLY = 4 ;
+static const uint8_t P9N2_MCA_MBA_TMR0Q_RRSMSR_DLY_LEN = 4 ;
+static const uint8_t P9N2_MCA_MBA_TMR0Q_RRSMDR_DLY = 8 ;
+static const uint8_t P9N2_MCA_MBA_TMR0Q_RRSMDR_DLY_LEN = 4 ;
+static const uint8_t P9N2_MCA_MBA_TMR0Q_RROP_DLY = 12 ;
+static const uint8_t P9N2_MCA_MBA_TMR0Q_RROP_DLY_LEN = 4 ;
+static const uint8_t P9N2_MCA_MBA_TMR0Q_WWDM_DLY = 16 ;
+static const uint8_t P9N2_MCA_MBA_TMR0Q_WWDM_DLY_LEN = 4 ;
+static const uint8_t P9N2_MCA_MBA_TMR0Q_WWSMSR_DLY = 20 ;
+static const uint8_t P9N2_MCA_MBA_TMR0Q_WWSMSR_DLY_LEN = 4 ;
+static const uint8_t P9N2_MCA_MBA_TMR0Q_WWSMDR_DLY = 24 ;
+static const uint8_t P9N2_MCA_MBA_TMR0Q_WWSMDR_DLY_LEN = 4 ;
+static const uint8_t P9N2_MCA_MBA_TMR0Q_WWOP_DLY = 28 ;
+static const uint8_t P9N2_MCA_MBA_TMR0Q_WWOP_DLY_LEN = 4 ;
+static const uint8_t P9N2_MCA_MBA_TMR0Q_RWDM_DLY = 32 ;
+static const uint8_t P9N2_MCA_MBA_TMR0Q_RWDM_DLY_LEN = 5 ;
+static const uint8_t P9N2_MCA_MBA_TMR0Q_RWSMSR_DLY = 37 ;
+static const uint8_t P9N2_MCA_MBA_TMR0Q_RWSMSR_DLY_LEN = 5 ;
+static const uint8_t P9N2_MCA_MBA_TMR0Q_RWSMDR_DLY = 42 ;
+static const uint8_t P9N2_MCA_MBA_TMR0Q_RWSMDR_DLY_LEN = 5 ;
+static const uint8_t P9N2_MCA_MBA_TMR0Q_WRDM_DLY = 47 ;
+static const uint8_t P9N2_MCA_MBA_TMR0Q_WRDM_DLY_LEN = 4 ;
+static const uint8_t P9N2_MCA_MBA_TMR0Q_WRSMSR_DLY = 51 ;
+static const uint8_t P9N2_MCA_MBA_TMR0Q_WRSMSR_DLY_LEN = 6 ;
+static const uint8_t P9N2_MCA_MBA_TMR0Q_WRSMDR_DLY = 57 ;
+static const uint8_t P9N2_MCA_MBA_TMR0Q_WRSMDR_DLY_LEN = 6 ;
+static const uint8_t P9N2_MCA_MBA_TMR0Q_RESERVED_63 = 63 ;
+
+static const uint8_t P9N2_MCA_MBA_TMR1Q_RRSBG_DLY = 0 ;
+static const uint8_t P9N2_MCA_MBA_TMR1Q_RRSBG_DLY_LEN = 4 ;
+static const uint8_t P9N2_MCA_MBA_TMR1Q_WRSBG_DLY = 4 ;
+static const uint8_t P9N2_MCA_MBA_TMR1Q_WRSBG_DLY_LEN = 6 ;
+static const uint8_t P9N2_MCA_MBA_TMR1Q_CFG_TFAW = 10 ;
+static const uint8_t P9N2_MCA_MBA_TMR1Q_CFG_TFAW_LEN = 6 ;
+static const uint8_t P9N2_MCA_MBA_TMR1Q_CFG_TRCD = 16 ;
+static const uint8_t P9N2_MCA_MBA_TMR1Q_CFG_TRCD_LEN = 5 ;
+static const uint8_t P9N2_MCA_MBA_TMR1Q_CFG_TRP = 21 ;
+static const uint8_t P9N2_MCA_MBA_TMR1Q_CFG_TRP_LEN = 5 ;
+static const uint8_t P9N2_MCA_MBA_TMR1Q_CFG_TRAS = 26 ;
+static const uint8_t P9N2_MCA_MBA_TMR1Q_CFG_TRAS_LEN = 6 ;
+static const uint8_t P9N2_MCA_MBA_TMR1Q_RESERVED_32_40 = 32 ;
+static const uint8_t P9N2_MCA_MBA_TMR1Q_RESERVED_32_40_LEN = 9 ;
+static const uint8_t P9N2_MCA_MBA_TMR1Q_CFG_WR2PRE = 41 ;
+static const uint8_t P9N2_MCA_MBA_TMR1Q_CFG_WR2PRE_LEN = 7 ;
+static const uint8_t P9N2_MCA_MBA_TMR1Q_CFG_RD2PRE = 48 ;
+static const uint8_t P9N2_MCA_MBA_TMR1Q_CFG_RD2PRE_LEN = 4 ;
+static const uint8_t P9N2_MCA_MBA_TMR1Q_TRRD = 52 ;
+static const uint8_t P9N2_MCA_MBA_TMR1Q_TRRD_LEN = 4 ;
+static const uint8_t P9N2_MCA_MBA_TMR1Q_TRRD_SBG = 56 ;
+static const uint8_t P9N2_MCA_MBA_TMR1Q_TRRD_SBG_LEN = 4 ;
+static const uint8_t P9N2_MCA_MBA_TMR1Q_CFG_ACT_TO_DIFF_RANK_DLY = 60 ;
+static const uint8_t P9N2_MCA_MBA_TMR1Q_CFG_ACT_TO_DIFF_RANK_DLY_LEN = 4 ;
+
+static const uint8_t P9N2_MCA_MBA_TMR2Q_CFG_BANK_BUSY_FSM_DIS = 0 ;
+static const uint8_t P9N2_MCA_MBA_TMR2Q_CFG_BANK_BUSY_FSM_DIS_LEN = 20 ;
+static const uint8_t P9N2_MCA_MBA_TMR2Q_CFG_BANK_BUSY_OPEN_PAGE_DIS = 20 ;
+static const uint8_t P9N2_MCA_MBA_TMR2Q_CFG_BANK_BUSY_OPEN_PAGE_DIS_LEN = 12 ;
+static const uint8_t P9N2_MCA_MBA_TMR2Q_RESERVED_32_63 = 32 ;
+static const uint8_t P9N2_MCA_MBA_TMR2Q_RESERVED_32_63_LEN = 32 ;
+
+static const uint8_t P9N2_MCA_MBA_WRQ0Q_CFG_WRITE_HW_MARK = 0 ;
+static const uint8_t P9N2_MCA_MBA_WRQ0Q_CFG_WRITE_HW_MARK_LEN = 5 ;
+static const uint8_t P9N2_MCA_MBA_WRQ0Q_CFG_WRQ_FIFO_MODE = 5 ;
+static const uint8_t P9N2_MCA_MBA_WRQ0Q_CFG_DISABLE_WR_PG_MODE = 6 ;
+static const uint8_t P9N2_MCA_MBA_WRQ0Q_CFG_WRQ_ENTRY0_HP_DLY = 7 ;
+static const uint8_t P9N2_MCA_MBA_WRQ0Q_CFG_WRQ_ENTRY0_HP_DLY_LEN = 12 ;
+static const uint8_t P9N2_MCA_MBA_WRQ0Q_CFG_WRQ_FLUSH_WR_RANK = 19 ;
+static const uint8_t P9N2_MCA_MBA_WRQ0Q_CFG_WRQ_ENABLE_NON_HP_WR = 20 ;
+static const uint8_t P9N2_MCA_MBA_WRQ0Q_CFG_ENTRY0_MIN_FOR_RRQ_IDLE_WR = 21 ;
+static const uint8_t P9N2_MCA_MBA_WRQ0Q_CFG_ENTRY0_MIN_FOR_RRQ_IDLE_WR_LEN = 12 ;
+static const uint8_t P9N2_MCA_MBA_WRQ0Q_CFG_WRITE_LW_MARK = 33 ;
+static const uint8_t P9N2_MCA_MBA_WRQ0Q_CFG_WRITE_LW_MARK_LEN = 5 ;
+static const uint8_t P9N2_MCA_MBA_WRQ0Q_CFG_WRQ_SKIP_LIMIT = 38 ;
+static const uint8_t P9N2_MCA_MBA_WRQ0Q_CFG_WRQ_SKIP_LIMIT_LEN = 6 ;
+static const uint8_t P9N2_MCA_MBA_WRQ0Q_CFG_WRQ_SINGLE_THREAD_MODE = 44 ;
+static const uint8_t P9N2_MCA_MBA_WRQ0Q_CFG_RQ_HANG_THRESHOLD = 45 ;
+static const uint8_t P9N2_MCA_MBA_WRQ0Q_CFG_RQ_HANG_THRESHOLD_LEN = 8 ;
+static const uint8_t P9N2_MCA_MBA_WRQ0Q_CFG_WRQ_SKIP_RRQ_ENTRIES_DIS = 53 ;
+static const uint8_t P9N2_MCA_MBA_WRQ0Q_RESERVED_54 = 54 ;
+static const uint8_t P9N2_MCA_MBA_WRQ0Q_CFG_WRQ_ACT_NUM_WRITES_PENDING = 55 ;
+static const uint8_t P9N2_MCA_MBA_WRQ0Q_CFG_WRQ_ACT_NUM_WRITES_PENDING_LEN = 4 ;
+static const uint8_t P9N2_MCA_MBA_WRQ0Q_CFG_WRQ_ALLOW_NEW_PAGE_COMMIT = 59 ;
+static const uint8_t P9N2_MCA_MBA_WRQ0Q_RESERVED_60_63 = 60 ;
+static const uint8_t P9N2_MCA_MBA_WRQ0Q_RESERVED_60_63_LEN = 4 ;
+
+static const uint8_t P9N2_MCBIST_MBECTLQ_ATOMIC_ALT_CE_INJ = 0 ;
+static const uint8_t P9N2_MCBIST_MBECTLQ_ATOMIC_ALT_CHIP_KILL_INJ = 1 ;
+static const uint8_t P9N2_MCBIST_MBECTLQ_ATOMIC_ALT_UE_INJ = 2 ;
+static const uint8_t P9N2_MCBIST_MBECTLQ_ATOMIC_ALT_SUE_INJ = 3 ;
+static const uint8_t P9N2_MCBIST_MBECTLQ_ATOMIC_ALT_INJ_SYM_SEL = 4 ;
+static const uint8_t P9N2_MCBIST_MBECTLQ_ATOMIC_ALT_INJ_SYM_SEL_LEN = 7 ;
+static const uint8_t P9N2_MCBIST_MBECTLQ_RESERVE_11 = 11 ;
+static const uint8_t P9N2_MCBIST_MBECTLQ_SCOM_CMD_REG_INJ_MODE = 12 ;
+static const uint8_t P9N2_MCBIST_MBECTLQ_SCOM_CMD_REG_INJ = 13 ;
+static const uint8_t P9N2_MCBIST_MBECTLQ_MCBIST_FSM_INJ_MODE = 14 ;
+static const uint8_t P9N2_MCBIST_MBECTLQ_MCBIST_FSM_INJ_REG = 15 ;
+static const uint8_t P9N2_MCBIST_MBECTLQ_CCS_FSM_INJ_MODE = 16 ;
+static const uint8_t P9N2_MCBIST_MBECTLQ_CCS_FSM_INJ_REG = 17 ;
+static const uint8_t P9N2_MCBIST_MBECTLQ_RESERVED_18_31 = 18 ;
+static const uint8_t P9N2_MCBIST_MBECTLQ_RESERVED_18_31_LEN = 14 ;
+
+static const uint8_t P9N2_MCA_MBMDI_MDI_0 = 0 ;
+static const uint8_t P9N2_MCA_MBMDI_SUE_0 = 1 ;
+static const uint8_t P9N2_MCA_MBMDI_MDI_1 = 2 ;
+static const uint8_t P9N2_MCA_MBMDI_SUE_1 = 3 ;
+
+static const uint8_t P9N2_MCBIST_MBMPER0Q_PORT_0_MAINLINE_MPE_ADDR_TRAP = 0 ;
+static const uint8_t P9N2_MCBIST_MBMPER0Q_PORT_0_MAINLINE_MPE_ADDR_TRAP_LEN = 38 ;
+static const uint8_t P9N2_MCBIST_MBMPER0Q_PORT_0_MAINLINE_MPE_ON_RCE = 38 ;
+static const uint8_t P9N2_MCBIST_MBMPER0Q_RESERVED_39 = 39 ;
+
+static const uint8_t P9N2_MCBIST_MBMPER1Q_PORT_1_MAINLINE_MPE_ADDR_TRAP = 0 ;
+static const uint8_t P9N2_MCBIST_MBMPER1Q_PORT_1_MAINLINE_MPE_ADDR_TRAP_LEN = 38 ;
+static const uint8_t P9N2_MCBIST_MBMPER1Q_PORT_1_MAINLINE_MPE_ON_RCE = 38 ;
+static const uint8_t P9N2_MCBIST_MBMPER1Q_RESERVED_39 = 39 ;
+
+static const uint8_t P9N2_MCBIST_MBMPER2Q_PORT_2_MAINLINE_MPE_ADDR_TRAP = 0 ;
+static const uint8_t P9N2_MCBIST_MBMPER2Q_PORT_2_MAINLINE_MPE_ADDR_TRAP_LEN = 38 ;
+static const uint8_t P9N2_MCBIST_MBMPER2Q_PORT_2_MAINLINE_MPE_ON_RCE = 38 ;
+static const uint8_t P9N2_MCBIST_MBMPER2Q_RESERVED_39 = 39 ;
+
+static const uint8_t P9N2_MCBIST_MBMPER3Q_PORT_3_MAINLINE_MPE_ADDR_TRAP = 0 ;
+static const uint8_t P9N2_MCBIST_MBMPER3Q_PORT_3_MAINLINE_MPE_ADDR_TRAP_LEN = 38 ;
+static const uint8_t P9N2_MCBIST_MBMPER3Q_PORT_3_MAINLINE_MPE_ON_RCE = 38 ;
+static const uint8_t P9N2_MCBIST_MBMPER3Q_RESERVED_39 = 39 ;
+
+static const uint8_t P9N2_MCBIST_MBNCER0Q_PORT_0_MAINLINE_NCE_ADDR_TRAP = 0 ;
+static const uint8_t P9N2_MCBIST_MBNCER0Q_PORT_0_MAINLINE_NCE_ADDR_TRAP_LEN = 38 ;
+static const uint8_t P9N2_MCBIST_MBNCER0Q_PORT_0_MAINLINE_NCE_ON_RCE = 38 ;
+static const uint8_t P9N2_MCBIST_MBNCER0Q_PORT_0_MAINLINE_NCE_IS_TCE = 39 ;
+
+static const uint8_t P9N2_MCBIST_MBNCER1Q_PORT_1_MAINLINE_NCE_ADDR_TRAP = 0 ;
+static const uint8_t P9N2_MCBIST_MBNCER1Q_PORT_1_MAINLINE_NCE_ADDR_TRAP_LEN = 38 ;
+static const uint8_t P9N2_MCBIST_MBNCER1Q_PORT_1_MAINLINE_NCE_ON_RCE = 38 ;
+static const uint8_t P9N2_MCBIST_MBNCER1Q_PORT_1_MAINLINE_NCE_IS_TCE = 39 ;
+
+static const uint8_t P9N2_MCBIST_MBNCER2Q_PORT_2_MAINLINE_NCE_ADDR_TRAP = 0 ;
+static const uint8_t P9N2_MCBIST_MBNCER2Q_PORT_2_MAINLINE_NCE_ADDR_TRAP_LEN = 38 ;
+static const uint8_t P9N2_MCBIST_MBNCER2Q_PORT_2_MAINLINE_NCE_ON_RCE = 38 ;
+static const uint8_t P9N2_MCBIST_MBNCER2Q_PORT_2_MAINLINE_NCE_IS_TCE = 39 ;
+
+static const uint8_t P9N2_MCBIST_MBNCER3Q_PORT_3_MAINLINE_NCE_ADDR_TRAP = 0 ;
+static const uint8_t P9N2_MCBIST_MBNCER3Q_PORT_3_MAINLINE_NCE_ADDR_TRAP_LEN = 38 ;
+static const uint8_t P9N2_MCBIST_MBNCER3Q_PORT_3_MAINLINE_NCE_ON_RCE = 38 ;
+static const uint8_t P9N2_MCBIST_MBNCER3Q_PORT_3_MAINLINE_NCE_IS_TCE = 39 ;
+
+static const uint8_t P9N2_MCBIST_MBRCER0Q_PORT_0_MAINLINE_RCE_ADDR_TRAP = 0 ;
+static const uint8_t P9N2_MCBIST_MBRCER0Q_PORT_0_MAINLINE_RCE_ADDR_TRAP_LEN = 38 ;
+static const uint8_t P9N2_MCBIST_MBRCER0Q_RESERVED_38_39 = 38 ;
+static const uint8_t P9N2_MCBIST_MBRCER0Q_RESERVED_38_39_LEN = 2 ;
+
+static const uint8_t P9N2_MCBIST_MBRCER1Q_PORT_1_MAINLINE_RCE_ADDR_TRAP = 0 ;
+static const uint8_t P9N2_MCBIST_MBRCER1Q_PORT_1_MAINLINE_RCE_ADDR_TRAP_LEN = 38 ;
+static const uint8_t P9N2_MCBIST_MBRCER1Q_RESERVED_38_39 = 38 ;
+static const uint8_t P9N2_MCBIST_MBRCER1Q_RESERVED_38_39_LEN = 2 ;
+
+static const uint8_t P9N2_MCBIST_MBRCER2Q_PORT_2_MAINLINE_RCE_ADDR_TRAP = 0 ;
+static const uint8_t P9N2_MCBIST_MBRCER2Q_PORT_2_MAINLINE_RCE_ADDR_TRAP_LEN = 38 ;
+static const uint8_t P9N2_MCBIST_MBRCER2Q_RESERVED_38_39 = 38 ;
+static const uint8_t P9N2_MCBIST_MBRCER2Q_RESERVED_38_39_LEN = 2 ;
+
+static const uint8_t P9N2_MCBIST_MBRCER3Q_PORT_3_MAINLINE_RCE_ADDR_TRAP = 0 ;
+static const uint8_t P9N2_MCBIST_MBRCER3Q_PORT_3_MAINLINE_RCE_ADDR_TRAP_LEN = 38 ;
+static const uint8_t P9N2_MCBIST_MBRCER3Q_RESERVED_38_39 = 38 ;
+static const uint8_t P9N2_MCBIST_MBRCER3Q_RESERVED_38_39_LEN = 2 ;
+
+static const uint8_t P9N2_MCBIST_MBSEC0Q_INTERMITTENT_CE_COUNT = 0 ;
+static const uint8_t P9N2_MCBIST_MBSEC0Q_INTERMITTENT_CE_COUNT_LEN = 12 ;
+static const uint8_t P9N2_MCBIST_MBSEC0Q_SOFT_CE_COUNT = 12 ;
+static const uint8_t P9N2_MCBIST_MBSEC0Q_SOFT_CE_COUNT_LEN = 12 ;
+static const uint8_t P9N2_MCBIST_MBSEC0Q_HARD_CE_COUNT = 24 ;
+static const uint8_t P9N2_MCBIST_MBSEC0Q_HARD_CE_COUNT_LEN = 12 ;
+static const uint8_t P9N2_MCBIST_MBSEC0Q_INTERMITTENT_MCE_COUNT = 36 ;
+static const uint8_t P9N2_MCBIST_MBSEC0Q_INTERMITTENT_MCE_COUNT_LEN = 12 ;
+static const uint8_t P9N2_MCBIST_MBSEC0Q_SOFT_MCE_COUNT = 48 ;
+static const uint8_t P9N2_MCBIST_MBSEC0Q_SOFT_MCE_COUNT_LEN = 12 ;
+
+static const uint8_t P9N2_MCBIST_MBSEC1Q_HARD_MCE_COUNT = 0 ;
+static const uint8_t P9N2_MCBIST_MBSEC1Q_HARD_MCE_COUNT_LEN = 12 ;
+static const uint8_t P9N2_MCBIST_MBSEC1Q_ICE_COUNT = 12 ;
+static const uint8_t P9N2_MCBIST_MBSEC1Q_ICE_COUNT_LEN = 12 ;
+static const uint8_t P9N2_MCBIST_MBSEC1Q_UE_COUNT = 24 ;
+static const uint8_t P9N2_MCBIST_MBSEC1Q_UE_COUNT_LEN = 12 ;
+static const uint8_t P9N2_MCBIST_MBSEC1Q_AUE = 36 ;
+static const uint8_t P9N2_MCBIST_MBSEC1Q_AUE_LEN = 12 ;
+static const uint8_t P9N2_MCBIST_MBSEC1Q_RCE_COUNT = 48 ;
+static const uint8_t P9N2_MCBIST_MBSEC1Q_RCE_COUNT_LEN = 12 ;
+
+static const uint8_t P9N2_MCBIST_MBSEVR0Q_PORT_0_MAINLINE_NCE_GALOIS_FIELD = 0 ;
+static const uint8_t P9N2_MCBIST_MBSEVR0Q_PORT_0_MAINLINE_NCE_GALOIS_FIELD_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSEVR0Q_PORT_0_MAINLINE_NCE_MAGNITUDE_FIELD = 8 ;
+static const uint8_t P9N2_MCBIST_MBSEVR0Q_PORT_0_MAINLINE_NCE_MAGNITUDE_FIELD_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSEVR0Q_PORT_0_MAINLINE_TCE_GALOIS_FIELD = 16 ;
+static const uint8_t P9N2_MCBIST_MBSEVR0Q_PORT_0_MAINLINE_TCE_GALOIS_FIELD_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSEVR0Q_PORT_0_MAINLINE_TCE_MAGNITUDE_FIELD = 24 ;
+static const uint8_t P9N2_MCBIST_MBSEVR0Q_PORT_0_MAINLINE_TCE_MAGNITUDE_FIELD_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSEVR0Q_PORT_1_MAINLINE_NCE_GALOIS_FIELD = 32 ;
+static const uint8_t P9N2_MCBIST_MBSEVR0Q_PORT_1_MAINLINE_NCE_GALOIS_FIELD_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSEVR0Q_PORT_1_MAINLINE_NCE_MAGNITUDE_FIELD = 40 ;
+static const uint8_t P9N2_MCBIST_MBSEVR0Q_PORT_1_MAINLINE_NCE_MAGNITUDE_FIELD_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSEVR0Q_PORT_1_MAINLINE_TCE_GALOIS_FIELD = 48 ;
+static const uint8_t P9N2_MCBIST_MBSEVR0Q_PORT_1_MAINLINE_TCE_GALOIS_FIELD_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSEVR0Q_PORT_1_MAINLINE_TCE_MAGNITUDE_FIELD = 56 ;
+static const uint8_t P9N2_MCBIST_MBSEVR0Q_PORT_1_MAINLINE_TCE_MAGNITUDE_FIELD_LEN = 8 ;
+
+static const uint8_t P9N2_MCBIST_MBSEVR1Q_PORT_2_MAINLINE_NCE_GALOIS_FIELD = 0 ;
+static const uint8_t P9N2_MCBIST_MBSEVR1Q_PORT_2_MAINLINE_NCE_GALOIS_FIELD_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSEVR1Q_PORT_2_MAINLINE_NCE_MAGNITUDE_FIELD = 8 ;
+static const uint8_t P9N2_MCBIST_MBSEVR1Q_PORT_2_MAINLINE_NCE_MAGNITUDE_FIELD_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSEVR1Q_PORT_2_MAINLINE_TCE_GALOIS_FIELD = 16 ;
+static const uint8_t P9N2_MCBIST_MBSEVR1Q_PORT_2_MAINLINE_TCE_GALOIS_FIELD_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSEVR1Q_PORT_2_MAINLINE_TCE_MAGNITUDE_FIELD = 24 ;
+static const uint8_t P9N2_MCBIST_MBSEVR1Q_PORT_2_MAINLINE_TCE_MAGNITUDE_FIELD_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSEVR1Q_PORT_3_MAINLINE_NCE_GALOIS_FIELD = 32 ;
+static const uint8_t P9N2_MCBIST_MBSEVR1Q_PORT_3_MAINLINE_NCE_GALOIS_FIELD_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSEVR1Q_PORT_3_MAINLINE_NCE_MAGNITUDE_FIELD = 40 ;
+static const uint8_t P9N2_MCBIST_MBSEVR1Q_PORT_3_MAINLINE_NCE_MAGNITUDE_FIELD_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSEVR1Q_PORT_3_MAINLINE_TCE_GALOIS_FIELD = 48 ;
+static const uint8_t P9N2_MCBIST_MBSEVR1Q_PORT_3_MAINLINE_TCE_GALOIS_FIELD_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSEVR1Q_PORT_3_MAINLINE_TCE_MAGNITUDE_FIELD = 56 ;
+static const uint8_t P9N2_MCBIST_MBSEVR1Q_PORT_3_MAINLINE_TCE_MAGNITUDE_FIELD_LEN = 8 ;
+
+static const uint8_t P9N2_MCBIST_MBSMODESQ_CFG_DDR4E_BLIND_STEER_MODE = 0 ;
+static const uint8_t P9N2_MCBIST_MBSMODESQ_CFG_MCB_NIB_CNT_PORT_AGNOSTIC_MASK_DIS = 1 ;
+static const uint8_t P9N2_MCBIST_MBSMODESQ_CFG_MCB_NIB_CNT_PORT_AGNOSTIC_MASK_DIS_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_MBSMODESQ_RESERVE_5_15 = 5 ;
+static const uint8_t P9N2_MCBIST_MBSMODESQ_RESERVE_5_15_LEN = 11 ;
+
+static const uint8_t P9N2_MCBIST_MBSMSECQ_MCE_SYMBOL0_COUNT = 0 ;
+static const uint8_t P9N2_MCBIST_MBSMSECQ_MCE_SYMBOL0_COUNT_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSMSECQ_MCE_SYMBOL1_COUNT = 8 ;
+static const uint8_t P9N2_MCBIST_MBSMSECQ_MCE_SYMBOL1_COUNT_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSMSECQ_MCE_SYMBOL2_COUNT = 16 ;
+static const uint8_t P9N2_MCBIST_MBSMSECQ_MCE_SYMBOL2_COUNT_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSMSECQ_MCE_SYMBOL3_COUNT = 24 ;
+static const uint8_t P9N2_MCBIST_MBSMSECQ_MCE_SYMBOL3_COUNT_LEN = 8 ;
+
+static const uint8_t P9N2_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_00 = 0 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_00_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_01 = 8 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_01_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_02 = 16 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_02_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_03 = 24 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_03_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_04 = 32 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_04_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_05 = 40 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_05_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_06 = 48 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_06_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_07 = 56 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_07_LEN = 8 ;
+
+static const uint8_t P9N2_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_08 = 0 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_08_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_09 = 8 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_09_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_10 = 16 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_10_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_11 = 24 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_11_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_12 = 32 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_12_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_13 = 40 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_13_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_14 = 48 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_14_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_15 = 56 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_15_LEN = 8 ;
+
+static const uint8_t P9N2_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_16 = 0 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_16_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_17 = 8 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_17_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_18 = 16 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_18_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_19 = 24 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_19_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_20 = 32 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_20_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_21 = 40 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_21_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_22 = 48 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_22_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_23 = 56 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_23_LEN = 8 ;
+
+static const uint8_t P9N2_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_24 = 0 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_24_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_25 = 8 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_25_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_26 = 16 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_26_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_27 = 24 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_27_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_28 = 32 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_28_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_29 = 40 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_29_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_30 = 48 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_30_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_31 = 56 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_31_LEN = 8 ;
+
+static const uint8_t P9N2_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_32 = 0 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_32_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_33 = 8 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_33_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_34 = 16 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_34_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_35 = 24 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_35_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_36 = 32 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_36_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_37 = 40 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_37_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_38 = 48 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_38_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_39 = 56 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_39_LEN = 8 ;
+
+static const uint8_t P9N2_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_40 = 0 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_40_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_41 = 8 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_41_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_42 = 16 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_42_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_43 = 24 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_43_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_44 = 32 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_44_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_45 = 40 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_45_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_46 = 48 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_46_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_47 = 56 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_47_LEN = 8 ;
+
+static const uint8_t P9N2_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_48 = 0 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_48_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_49 = 8 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_49_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_50 = 16 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_50_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_51 = 24 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_51_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_52 = 32 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_52_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_53 = 40 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_53_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_54 = 48 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_54_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_55 = 56 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_55_LEN = 8 ;
+
+static const uint8_t P9N2_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_56 = 0 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_56_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_57 = 8 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_57_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_58 = 16 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_58_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_59 = 24 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_59_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_60 = 32 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_60_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_61 = 40 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_61_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_62 = 48 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_62_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_63 = 56 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_63_LEN = 8 ;
+
+static const uint8_t P9N2_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_64 = 0 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_64_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_65 = 8 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_65_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_66 = 16 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_66_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_67 = 24 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_67_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_68 = 32 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_68_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_69 = 40 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_69_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_70 = 48 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_70_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_71 = 56 ;
+static const uint8_t P9N2_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_71_LEN = 8 ;
+
+static const uint8_t P9N2_MCBIST_MBSTRQ_CFG_THRESH_MAG_NCE_INT = 0 ;
+static const uint8_t P9N2_MCBIST_MBSTRQ_CFG_THRESH_MAG_NCE_INT_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_MBSTRQ_CFG_THRESH_MAG_NCE_SOFT = 4 ;
+static const uint8_t P9N2_MCBIST_MBSTRQ_CFG_THRESH_MAG_NCE_SOFT_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_MBSTRQ_CFG_THRESH_MAG_NCE_HARD = 8 ;
+static const uint8_t P9N2_MCBIST_MBSTRQ_CFG_THRESH_MAG_NCE_HARD_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_MBSTRQ_CFG_THRESH_MAG_RCE = 12 ;
+static const uint8_t P9N2_MCBIST_MBSTRQ_CFG_THRESH_MAG_RCE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_MBSTRQ_CFG_THRESH_MAG_ICE = 16 ;
+static const uint8_t P9N2_MCBIST_MBSTRQ_CFG_THRESH_MAG_ICE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_MBSTRQ_CFG_THRESH_MAG_MCE_INT = 20 ;
+static const uint8_t P9N2_MCBIST_MBSTRQ_CFG_THRESH_MAG_MCE_INT_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_MBSTRQ_CFG_THRESH_MAG_MCE_SOFT = 24 ;
+static const uint8_t P9N2_MCBIST_MBSTRQ_CFG_THRESH_MAG_MCE_SOFT_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_MBSTRQ_CFG_THRESH_MAG_MCE_HARD = 28 ;
+static const uint8_t P9N2_MCBIST_MBSTRQ_CFG_THRESH_MAG_MCE_HARD_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_MBSTRQ_CFG_PAUSE_ON_SCE = 32 ;
+static const uint8_t P9N2_MCBIST_MBSTRQ_RESERVED_33 = 33 ;
+static const uint8_t P9N2_MCBIST_MBSTRQ_CFG_PAUSE_ON_MPE = 34 ;
+static const uint8_t P9N2_MCBIST_MBSTRQ_CFG_PAUSE_ON_UE = 35 ;
+static const uint8_t P9N2_MCBIST_MBSTRQ_CFG_PAUSE_ON_SUE = 36 ;
+static const uint8_t P9N2_MCBIST_MBSTRQ_CFG_PAUSE_ON_AUE = 37 ;
+static const uint8_t P9N2_MCBIST_MBSTRQ_CFG_PAUSE_ON_RCD = 38 ;
+static const uint8_t P9N2_MCBIST_MBSTRQ_RESERVE_39_52 = 39 ;
+static const uint8_t P9N2_MCBIST_MBSTRQ_RESERVE_39_52_LEN = 14 ;
+static const uint8_t P9N2_MCBIST_MBSTRQ_CFG_SYMBOL_COUNTER_MODE = 53 ;
+static const uint8_t P9N2_MCBIST_MBSTRQ_CFG_SYMBOL_COUNTER_MODE_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_MBSTRQ_CFG_NCE_SOFT_SYMBOL_COUNT_ENABLE = 55 ;
+static const uint8_t P9N2_MCBIST_MBSTRQ_CFG_NCE_INTER_SYMBOL_COUNT_ENABLE = 56 ;
+static const uint8_t P9N2_MCBIST_MBSTRQ_CFG_NCE_HARD_SYMBOL_COUNT_ENABLE = 57 ;
+static const uint8_t P9N2_MCBIST_MBSTRQ_CFG_PAUSE_MCB_ERROR = 58 ;
+static const uint8_t P9N2_MCBIST_MBSTRQ_CFG_PAUSE_MCB_LOG_FULL = 59 ;
+static const uint8_t P9N2_MCBIST_MBSTRQ_CFG_MAINT_RCE_WITH_CE = 60 ;
+static const uint8_t P9N2_MCBIST_MBSTRQ_CFG_MCE_SOFT_SYMBOL_COUNT_ENABLE = 61 ;
+static const uint8_t P9N2_MCBIST_MBSTRQ_CFG_MCE_INTER_SYMBOL_COUNT_ENABLE = 62 ;
+static const uint8_t P9N2_MCBIST_MBSTRQ_CFG_MCE_HARD_SYMBOL_COUNT_ENABLE = 63 ;
+
+static const uint8_t P9N2_MCBIST_MBUER0Q_PORT_0_MAINLINE_UE_ADDR_TRAP = 0 ;
+static const uint8_t P9N2_MCBIST_MBUER0Q_PORT_0_MAINLINE_UE_ADDR_TRAP_LEN = 38 ;
+static const uint8_t P9N2_MCBIST_MBUER0Q_RESERVED_38_39 = 38 ;
+static const uint8_t P9N2_MCBIST_MBUER0Q_RESERVED_38_39_LEN = 2 ;
+
+static const uint8_t P9N2_MCBIST_MBUER1Q_PORT_1_MAINLINE_UE_ADDR_TRAP = 0 ;
+static const uint8_t P9N2_MCBIST_MBUER1Q_PORT_1_MAINLINE_UE_ADDR_TRAP_LEN = 38 ;
+static const uint8_t P9N2_MCBIST_MBUER1Q_RESERVED_38_39 = 38 ;
+static const uint8_t P9N2_MCBIST_MBUER1Q_RESERVED_38_39_LEN = 2 ;
+
+static const uint8_t P9N2_MCBIST_MBUER2Q_PORT_2_MAINLINE_UE_ADDR_TRAP = 0 ;
+static const uint8_t P9N2_MCBIST_MBUER2Q_PORT_2_MAINLINE_UE_ADDR_TRAP_LEN = 38 ;
+static const uint8_t P9N2_MCBIST_MBUER2Q_RESERVED_38_39 = 38 ;
+static const uint8_t P9N2_MCBIST_MBUER2Q_RESERVED_38_39_LEN = 2 ;
+
+static const uint8_t P9N2_MCBIST_MBUER3Q_PORT_3_MAINLINE_UE_ADDR_TRAP = 0 ;
+static const uint8_t P9N2_MCBIST_MBUER3Q_PORT_3_MAINLINE_UE_ADDR_TRAP_LEN = 38 ;
+static const uint8_t P9N2_MCBIST_MBUER3Q_RESERVED_38_39 = 38 ;
+static const uint8_t P9N2_MCBIST_MBUER3Q_RESERVED_38_39_LEN = 2 ;
+
+static const uint8_t P9N2_MCS_PORT02_MCAMOC_ENABLE_CLEAN = 0 ;
+static const uint8_t P9N2_MCS_PORT02_MCAMOC_FORCE_PF_DROP0 = 1 ;
+static const uint8_t P9N2_MCS_PORT02_MCAMOC_FORCE_PF_DROP1 = 2 ;
+static const uint8_t P9N2_MCS_PORT02_MCAMOC_EN_RD_FROM_AMOC = 3 ;
+static const uint8_t P9N2_MCS_PORT02_MCAMOC_WRTO_AMO_COLLISION_RULES = 4 ;
+static const uint8_t P9N2_MCS_PORT02_MCAMOC_WRTO_AMO_COLLISION_RULES_LEN = 25 ;
+static const uint8_t P9N2_MCS_PORT02_MCAMOC_AMO_SIZE_SELECT = 29 ;
+static const uint8_t P9N2_MCS_PORT02_MCAMOC_AMO_SIZE_SELECT_LEN = 3 ;
+
+static const uint8_t P9N2_MCS_PORT13_MCAMOC_ENABLE_CLEAN = 0 ;
+static const uint8_t P9N2_MCS_PORT13_MCAMOC_FORCE_PF_DROP0 = 1 ;
+static const uint8_t P9N2_MCS_PORT13_MCAMOC_FORCE_PF_DROP1 = 2 ;
+static const uint8_t P9N2_MCS_PORT13_MCAMOC_EN_RD_FROM_AMOC = 3 ;
+static const uint8_t P9N2_MCS_PORT13_MCAMOC_WRTO_AMO_COLLISION_RULES = 4 ;
+static const uint8_t P9N2_MCS_PORT13_MCAMOC_WRTO_AMO_COLLISION_RULES_LEN = 25 ;
+static const uint8_t P9N2_MCS_PORT13_MCAMOC_AMO_SIZE_SELECT = 29 ;
+static const uint8_t P9N2_MCS_PORT13_MCAMOC_AMO_SIZE_SELECT_LEN = 3 ;
+
+static const uint8_t P9N2_MCBIST_MCBACQ_CFG_ADDRESS_COUNTER = 0 ;
+static const uint8_t P9N2_MCBIST_MCBACQ_CFG_ADDRESS_COUNTER_LEN = 38 ;
+
+static const uint8_t P9N2_MCBIST_MCBAGRAQ_CFG_FIXED_WIDTH = 0 ;
+static const uint8_t P9N2_MCBIST_MCBAGRAQ_CFG_FIXED_WIDTH_LEN = 6 ;
+static const uint8_t P9N2_MCBIST_MCBAGRAQ_CFG_ADDR_COUNTER_MODE = 6 ;
+static const uint8_t P9N2_MCBIST_MCBAGRAQ_CFG_ADDR_COUNTER_MODE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_MCBAGRAQ_CFG_MAINT_ADDR_MODE_EN = 10 ;
+static const uint8_t P9N2_MCBIST_MCBAGRAQ_CFG_MAINT_BROADCAST_MODE_EN = 11 ;
+static const uint8_t P9N2_MCBIST_MCBAGRAQ_CFG_MAINT_DETECT_SRANK_BOUNDARIES = 12 ;
+static const uint8_t P9N2_MCBIST_MCBAGRAQ_RESERVED_13_31 = 13 ;
+static const uint8_t P9N2_MCBIST_MCBAGRAQ_RESERVED_13_31_LEN = 19 ;
+
+static const uint8_t P9N2_MCBIST_MCBAMR0A0Q_CFG_AMAP_DIMM_SELECT = 0 ;
+static const uint8_t P9N2_MCBIST_MCBAMR0A0Q_CFG_AMAP_DIMM_SELECT_LEN = 6 ;
+static const uint8_t P9N2_MCBIST_MCBAMR0A0Q_CFG_AMAP_MRANK0 = 6 ;
+static const uint8_t P9N2_MCBIST_MCBAMR0A0Q_CFG_AMAP_MRANK0_LEN = 6 ;
+static const uint8_t P9N2_MCBIST_MCBAMR0A0Q_CFG_AMAP_MRANK1 = 12 ;
+static const uint8_t P9N2_MCBIST_MCBAMR0A0Q_CFG_AMAP_MRANK1_LEN = 6 ;
+static const uint8_t P9N2_MCBIST_MCBAMR0A0Q_RESERVED_18_23 = 18 ;
+static const uint8_t P9N2_MCBIST_MCBAMR0A0Q_RESERVED_18_23_LEN = 6 ;
+static const uint8_t P9N2_MCBIST_MCBAMR0A0Q_CFG_AMAP_SRANK0 = 24 ;
+static const uint8_t P9N2_MCBIST_MCBAMR0A0Q_CFG_AMAP_SRANK0_LEN = 6 ;
+static const uint8_t P9N2_MCBIST_MCBAMR0A0Q_CFG_AMAP_SRANK1 = 30 ;
+static const uint8_t P9N2_MCBIST_MCBAMR0A0Q_CFG_AMAP_SRANK1_LEN = 6 ;
+static const uint8_t P9N2_MCBIST_MCBAMR0A0Q_CFG_AMAP_SRANK2 = 36 ;
+static const uint8_t P9N2_MCBIST_MCBAMR0A0Q_CFG_AMAP_SRANK2_LEN = 6 ;
+static const uint8_t P9N2_MCBIST_MCBAMR0A0Q_CFG_AMAP_BANK2 = 42 ;
+static const uint8_t P9N2_MCBIST_MCBAMR0A0Q_CFG_AMAP_BANK2_LEN = 6 ;
+static const uint8_t P9N2_MCBIST_MCBAMR0A0Q_CFG_AMAP_BANK1 = 48 ;
+static const uint8_t P9N2_MCBIST_MCBAMR0A0Q_CFG_AMAP_BANK1_LEN = 6 ;
+static const uint8_t P9N2_MCBIST_MCBAMR0A0Q_CFG_AMAP_BANK0 = 54 ;
+static const uint8_t P9N2_MCBIST_MCBAMR0A0Q_CFG_AMAP_BANK0_LEN = 6 ;
+static const uint8_t P9N2_MCBIST_MCBAMR0A0Q_RESERVED_60_63 = 60 ;
+static const uint8_t P9N2_MCBIST_MCBAMR0A0Q_RESERVED_60_63_LEN = 4 ;
+
+static const uint8_t P9N2_MCBIST_MCBAMR1A0Q_CFG_AMAP_BANK_GROUP1 = 0 ;
+static const uint8_t P9N2_MCBIST_MCBAMR1A0Q_CFG_AMAP_BANK_GROUP1_LEN = 6 ;
+static const uint8_t P9N2_MCBIST_MCBAMR1A0Q_CFG_AMAP_BANK_GROUP0 = 6 ;
+static const uint8_t P9N2_MCBIST_MCBAMR1A0Q_CFG_AMAP_BANK_GROUP0_LEN = 6 ;
+static const uint8_t P9N2_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW17 = 12 ;
+static const uint8_t P9N2_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW17_LEN = 6 ;
+static const uint8_t P9N2_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW16 = 18 ;
+static const uint8_t P9N2_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW16_LEN = 6 ;
+static const uint8_t P9N2_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW15 = 24 ;
+static const uint8_t P9N2_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW15_LEN = 6 ;
+static const uint8_t P9N2_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW14 = 30 ;
+static const uint8_t P9N2_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW14_LEN = 6 ;
+static const uint8_t P9N2_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW13 = 36 ;
+static const uint8_t P9N2_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW13_LEN = 6 ;
+static const uint8_t P9N2_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW12 = 42 ;
+static const uint8_t P9N2_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW12_LEN = 6 ;
+static const uint8_t P9N2_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW11 = 48 ;
+static const uint8_t P9N2_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW11_LEN = 6 ;
+static const uint8_t P9N2_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW10 = 54 ;
+static const uint8_t P9N2_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW10_LEN = 6 ;
+static const uint8_t P9N2_MCBIST_MCBAMR1A0Q_RESERVED_60_63 = 60 ;
+static const uint8_t P9N2_MCBIST_MCBAMR1A0Q_RESERVED_60_63_LEN = 4 ;
+
+static const uint8_t P9N2_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW9 = 0 ;
+static const uint8_t P9N2_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW9_LEN = 6 ;
+static const uint8_t P9N2_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW8 = 6 ;
+static const uint8_t P9N2_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW8_LEN = 6 ;
+static const uint8_t P9N2_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW7 = 12 ;
+static const uint8_t P9N2_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW7_LEN = 6 ;
+static const uint8_t P9N2_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW6 = 18 ;
+static const uint8_t P9N2_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW6_LEN = 6 ;
+static const uint8_t P9N2_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW5 = 24 ;
+static const uint8_t P9N2_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW5_LEN = 6 ;
+static const uint8_t P9N2_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW4 = 30 ;
+static const uint8_t P9N2_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW4_LEN = 6 ;
+static const uint8_t P9N2_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW3 = 36 ;
+static const uint8_t P9N2_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW3_LEN = 6 ;
+static const uint8_t P9N2_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW2 = 42 ;
+static const uint8_t P9N2_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW2_LEN = 6 ;
+static const uint8_t P9N2_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW1 = 48 ;
+static const uint8_t P9N2_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW1_LEN = 6 ;
+static const uint8_t P9N2_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW0 = 54 ;
+static const uint8_t P9N2_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW0_LEN = 6 ;
+static const uint8_t P9N2_MCBIST_MCBAMR2A0Q_RESERVED_60_63 = 60 ;
+static const uint8_t P9N2_MCBIST_MCBAMR2A0Q_RESERVED_60_63_LEN = 4 ;
+
+static const uint8_t P9N2_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL9 = 0 ;
+static const uint8_t P9N2_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL9_LEN = 6 ;
+static const uint8_t P9N2_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL8 = 6 ;
+static const uint8_t P9N2_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL8_LEN = 6 ;
+static const uint8_t P9N2_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL7 = 12 ;
+static const uint8_t P9N2_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL7_LEN = 6 ;
+static const uint8_t P9N2_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL6 = 18 ;
+static const uint8_t P9N2_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL6_LEN = 6 ;
+static const uint8_t P9N2_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL5 = 24 ;
+static const uint8_t P9N2_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL5_LEN = 6 ;
+static const uint8_t P9N2_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL4 = 30 ;
+static const uint8_t P9N2_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL4_LEN = 6 ;
+static const uint8_t P9N2_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL3 = 36 ;
+static const uint8_t P9N2_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL3_LEN = 6 ;
+static const uint8_t P9N2_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL2 = 42 ;
+static const uint8_t P9N2_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL2_LEN = 6 ;
+static const uint8_t P9N2_MCBIST_MCBAMR3A0Q_RESERVED_48_63 = 48 ;
+static const uint8_t P9N2_MCBIST_MCBAMR3A0Q_RESERVED_48_63_LEN = 16 ;
+
+static const uint8_t P9N2_MCBIST_MCBCFGQ_BROADCAST_SYNC_EN = 0 ;
+static const uint8_t P9N2_MCBIST_MCBCFGQ_BROADCAST_SYNC_WAIT = 1 ;
+static const uint8_t P9N2_MCBIST_MCBCFGQ_BROADCAST_SYNC_WAIT_LEN = 7 ;
+static const uint8_t P9N2_MCBIST_MCBCFGQ_CFG_CMD_TIMEOUT_MODE = 8 ;
+static const uint8_t P9N2_MCBIST_MCBCFGQ_CFG_CMD_TIMEOUT_MODE_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_MCBCFGQ_RESET_KEEPER = 10 ;
+static const uint8_t P9N2_MCBIST_MCBCFGQ_CFG_CURRENT_ADDR_TRAP_UPDATE_DIS = 11 ;
+static const uint8_t P9N2_MCBIST_MCBCFGQ_CFG_CCS_RETRY_DIS = 12 ;
+static const uint8_t P9N2_MCBIST_MCBCFGQ_RESERVED_13_33 = 13 ;
+static const uint8_t P9N2_MCBIST_MCBCFGQ_RESERVED_13_33_LEN = 21 ;
+static const uint8_t P9N2_MCBIST_MCBCFGQ_MCBIST_CFG_FORCE_PAUSE_AFTER_RANK = 34 ;
+static const uint8_t P9N2_MCBIST_MCBCFGQ_CFG_RESET_CNTS_START_OF_RANK = 35 ;
+static const uint8_t P9N2_MCBIST_MCBCFGQ_CFG_LOG_COUNTS_IN_TRACE = 36 ;
+static const uint8_t P9N2_MCBIST_MCBCFGQ_SKIP_INVALID_ADDR_DIMM_DIS = 37 ;
+static const uint8_t P9N2_MCBIST_MCBCFGQ_REFRESH_ONLY_SUBTEST_EN = 38 ;
+static const uint8_t P9N2_MCBIST_MCBCFGQ_REFRESH_ONLY_SUBTEST_TIMEBASE_SEL = 39 ;
+static const uint8_t P9N2_MCBIST_MCBCFGQ_REFRESH_ONLY_SUBTEST_TIMEBASE_SEL_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_MCBCFGQ_RAND_ADDR_ALL_ADDR_MODE_EN = 41 ;
+static const uint8_t P9N2_MCBIST_MCBCFGQ_MCBIST_CFG_REF_WAIT_TIME = 42 ;
+static const uint8_t P9N2_MCBIST_MCBCFGQ_MCBIST_CFG_REF_WAIT_TIME_LEN = 14 ;
+static const uint8_t P9N2_MCBIST_MCBCFGQ_CFG_MCB_LEN64 = 56 ;
+static const uint8_t P9N2_MCBIST_MCBCFGQ_CFG_PAUSE_ON_ERROR_MODE = 57 ;
+static const uint8_t P9N2_MCBIST_MCBCFGQ_CFG_PAUSE_ON_ERROR_MODE_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_MCBCFGQ_MCBIST_CFG_PAUSE_AFTER_CCS_SUBTEST = 59 ;
+static const uint8_t P9N2_MCBIST_MCBCFGQ_MCBIST_CFG_FORCE_PAUSE_AFTER_ADDR = 60 ;
+static const uint8_t P9N2_MCBIST_MCBCFGQ_MCBIST_CFG_FORCE_PAUSE_AFTER_SUBTEST = 61 ;
+static const uint8_t P9N2_MCBIST_MCBCFGQ_CFG_ENABLE_SPEC_ATTN = 62 ;
+static const uint8_t P9N2_MCBIST_MCBCFGQ_CFG_ENABLE_HOST_ATTN = 63 ;
+
+static const uint8_t P9N2_MCA_MCBCM_MCBIST_HALF_COMPARE_MASK = 0 ;
+static const uint8_t P9N2_MCA_MCBCM_MCBIST_HALF_COMPARE_MASK_LEN = 40 ;
+static const uint8_t P9N2_MCA_MCBCM_MCBIST_MASK_COVERAGE_SELECTOR = 40 ;
+static const uint8_t P9N2_MCA_MCBCM_MCBIST_TRAP_NONSTOP = 41 ;
+static const uint8_t P9N2_MCA_MCBCM_MCBIST_TRAP_CE_ENABLE = 42 ;
+static const uint8_t P9N2_MCA_MCBCM_MCBIST_TRAP_MPE_ENABLE = 43 ;
+static const uint8_t P9N2_MCA_MCBCM_MCBIST_TRAP_UE_ENABLE = 44 ;
+
+static const uint8_t P9N2_MCBIST_MCBDRCRQ_CFG_DATA_ROT = 0 ;
+static const uint8_t P9N2_MCBIST_MCBDRCRQ_CFG_DATA_ROT_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_MCBDRCRQ_CFG_DATA_ROT_SEED = 4 ;
+static const uint8_t P9N2_MCBIST_MCBDRCRQ_CFG_DATA_ROT_SEED_LEN = 16 ;
+static const uint8_t P9N2_MCBIST_MCBDRCRQ_RESERVED_20 = 20 ;
+static const uint8_t P9N2_MCBIST_MCBDRCRQ_CFG_DATA_SEED_MODE = 21 ;
+static const uint8_t P9N2_MCBIST_MCBDRCRQ_CFG_DATA_SEED_MODE_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_MCBDRCRQ_RESERVED_23_63 = 23 ;
+static const uint8_t P9N2_MCBIST_MCBDRCRQ_RESERVED_23_63_LEN = 41 ;
+
+static const uint8_t P9N2_MCBIST_MCBDRSRQ_CFG_DATA_ROT_SEED = 0 ;
+static const uint8_t P9N2_MCBIST_MCBDRSRQ_CFG_DATA_ROT_SEED_LEN = 64 ;
+
+static const uint8_t P9N2_MCBIST_MCBEA0Q_CFG_END_ADDR_0 = 0 ;
+static const uint8_t P9N2_MCBIST_MCBEA0Q_CFG_END_ADDR_0_LEN = 38 ;
+
+static const uint8_t P9N2_MCBIST_MCBEA1Q_CFG_END_ADDR_1 = 0 ;
+static const uint8_t P9N2_MCBIST_MCBEA1Q_CFG_END_ADDR_1_LEN = 38 ;
+
+static const uint8_t P9N2_MCBIST_MCBEA2Q_CFG_END_ADDR_2 = 0 ;
+static const uint8_t P9N2_MCBIST_MCBEA2Q_CFG_END_ADDR_2_LEN = 38 ;
+
+static const uint8_t P9N2_MCBIST_MCBEA3Q_CFG_END_ADDR_3 = 0 ;
+static const uint8_t P9N2_MCBIST_MCBEA3Q_CFG_END_ADDR_3_LEN = 38 ;
+
+static const uint8_t P9N2_MCBIST_MCBFD0Q_CFG_FIXED_SEED = 0 ;
+static const uint8_t P9N2_MCBIST_MCBFD0Q_CFG_FIXED_SEED_LEN = 64 ;
+
+static const uint8_t P9N2_MCBIST_MCBFD1Q_CFG_FIXED_SEED = 0 ;
+static const uint8_t P9N2_MCBIST_MCBFD1Q_CFG_FIXED_SEED_LEN = 64 ;
+
+static const uint8_t P9N2_MCBIST_MCBFD2Q_CFG_FIXED_SEED = 0 ;
+static const uint8_t P9N2_MCBIST_MCBFD2Q_CFG_FIXED_SEED_LEN = 64 ;
+
+static const uint8_t P9N2_MCBIST_MCBFD3Q_CFG_FIXED_SEED = 0 ;
+static const uint8_t P9N2_MCBIST_MCBFD3Q_CFG_FIXED_SEED_LEN = 64 ;
+
+static const uint8_t P9N2_MCBIST_MCBFD4Q_CFG_FIXED_SEED = 0 ;
+static const uint8_t P9N2_MCBIST_MCBFD4Q_CFG_FIXED_SEED_LEN = 64 ;
+
+static const uint8_t P9N2_MCBIST_MCBFD5Q_CFG_FIXED_SEED = 0 ;
+static const uint8_t P9N2_MCBIST_MCBFD5Q_CFG_FIXED_SEED_LEN = 64 ;
+
+static const uint8_t P9N2_MCBIST_MCBFD6Q_CFG_FIXED_SEED = 0 ;
+static const uint8_t P9N2_MCBIST_MCBFD6Q_CFG_FIXED_SEED_LEN = 64 ;
+
+static const uint8_t P9N2_MCBIST_MCBFD7Q_CFG_FIXED_SEED = 0 ;
+static const uint8_t P9N2_MCBIST_MCBFD7Q_CFG_FIXED_SEED_LEN = 64 ;
+
+static const uint8_t P9N2_MCBIST_MCBFDQ_CFG_FIXED_SEED1 = 0 ;
+static const uint8_t P9N2_MCBIST_MCBFDQ_CFG_FIXED_SEED1_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MCBFDQ_CFG_FIXED_SEED2 = 8 ;
+static const uint8_t P9N2_MCBIST_MCBFDQ_CFG_FIXED_SEED2_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MCBFDQ_CFG_FIXED_SEED3 = 16 ;
+static const uint8_t P9N2_MCBIST_MCBFDQ_CFG_FIXED_SEED3_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MCBFDQ_CFG_FIXED_SEED4 = 24 ;
+static const uint8_t P9N2_MCBIST_MCBFDQ_CFG_FIXED_SEED4_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MCBFDQ_CFG_FIXED_SEED5 = 32 ;
+static const uint8_t P9N2_MCBIST_MCBFDQ_CFG_FIXED_SEED5_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MCBFDQ_CFG_FIXED_SEED6 = 40 ;
+static const uint8_t P9N2_MCBIST_MCBFDQ_CFG_FIXED_SEED6_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MCBFDQ_CFG_FIXED_SEED7 = 48 ;
+static const uint8_t P9N2_MCBIST_MCBFDQ_CFG_FIXED_SEED7_LEN = 8 ;
+static const uint8_t P9N2_MCBIST_MCBFDQ_CFG_FIXED_SEED8 = 56 ;
+static const uint8_t P9N2_MCBIST_MCBFDQ_CFG_FIXED_SEED8_LEN = 8 ;
+
+static const uint8_t P9N2_MCBIST_MCBISTFIRACT0_FIR_ACTION0 = 0 ;
+static const uint8_t P9N2_MCBIST_MCBISTFIRACT0_FIR_ACTION0_LEN = 20 ;
+
+static const uint8_t P9N2_MCBIST_MCBISTFIRACT1_FIR_ACTION1 = 0 ;
+static const uint8_t P9N2_MCBIST_MCBISTFIRACT1_FIR_ACTION1_LEN = 20 ;
+
+static const uint8_t P9N2_MCBIST_MCBISTFIRMASK_FIR_MASK = 0 ;
+static const uint8_t P9N2_MCBIST_MCBISTFIRMASK_FIR_MASK_LEN = 20 ;
+
+static const uint8_t P9N2_MCBIST_MCBISTFIRQ_INVALID_MAINT_ADDRESS = 0 ;
+static const uint8_t P9N2_MCBIST_MCBISTFIRQ_COMMAND_ADDRESS_TIMEOUT = 1 ;
+static const uint8_t P9N2_MCBIST_MCBISTFIRQ_INTERNAL_FSM_ERROR = 2 ;
+static const uint8_t P9N2_MCBIST_MCBISTFIRQ_MCBIST_BRODCAST_OUT_OF_SYNC = 3 ;
+static const uint8_t P9N2_MCBIST_MCBISTFIRQ_MCBIST_DATA_ERROR = 4 ;
+static const uint8_t P9N2_MCBIST_MCBISTFIRQ_HARD_NCE_ETE_ATTN = 5 ;
+static const uint8_t P9N2_MCBIST_MCBISTFIRQ_SOFT_NCE_ETE_ATTN = 6 ;
+static const uint8_t P9N2_MCBIST_MCBISTFIRQ_INT_NCE_ETE_ATTN = 7 ;
+static const uint8_t P9N2_MCBIST_MCBISTFIRQ_RCE_ETE_ATTN = 8 ;
+static const uint8_t P9N2_MCBIST_MCBISTFIRQ_ICE_ETE_ATTN = 9 ;
+static const uint8_t P9N2_MCBIST_MCBISTFIRQ_MCBIST_PROGRAM_COMPLETE = 10 ;
+static const uint8_t P9N2_MCBIST_MCBISTFIRQ_MCBIST_CCS_SUBTEST_DONE = 11 ;
+static const uint8_t P9N2_MCBIST_MCBISTFIRQ_WAT_DEBUG_ATTN = 12 ;
+static const uint8_t P9N2_MCBIST_MCBISTFIRQ_SCOM_RECOVERABLE_REG_PE = 13 ;
+static const uint8_t P9N2_MCBIST_MCBISTFIRQ_SCOM_FATAL_REG_PE = 14 ;
+static const uint8_t P9N2_MCBIST_MCBISTFIRQ_WAT_DEBUG_REG_PE = 15 ;
+static const uint8_t P9N2_MCBIST_MCBISTFIRQ_RESERVED_16 = 16 ;
+static const uint8_t P9N2_MCBIST_MCBISTFIRQ_RESERVED_17 = 17 ;
+static const uint8_t P9N2_MCBIST_MCBISTFIRQ_INTERNAL_SCOM_ERROR = 18 ;
+static const uint8_t P9N2_MCBIST_MCBISTFIRQ_INTERNAL_SCOM_ERROR_CLONE = 19 ;
+
+static const uint8_t P9N2_MCBIST_MCBISTFIRWOF_INVALID_MAINT_ADDRESS = 0 ;
+static const uint8_t P9N2_MCBIST_MCBISTFIRWOF_INVALID_MAINT_ADDRESS_LEN = 20 ;
+
+static const uint8_t P9N2_MCBIST_MCBLFSRA0Q_CFG_LFSR_MASK_A0 = 0 ;
+static const uint8_t P9N2_MCBIST_MCBLFSRA0Q_CFG_LFSR_MASK_A0_LEN = 38 ;
+static const uint8_t P9N2_MCBIST_MCBLFSRA0Q_RESERVED_38_63 = 38 ;
+static const uint8_t P9N2_MCBIST_MCBLFSRA0Q_RESERVED_38_63_LEN = 26 ;
+
+static const uint8_t P9N2_MCBIST_MCBMCATQ_CFG_CURRENT_ADDR_TRAP = 0 ;
+static const uint8_t P9N2_MCBIST_MCBMCATQ_CFG_CURRENT_ADDR_TRAP_LEN = 38 ;
+static const uint8_t P9N2_MCBIST_MCBMCATQ_CFG_CURRENT_PORT_TRAP = 38 ;
+static const uint8_t P9N2_MCBIST_MCBMCATQ_CFG_CURRENT_PORT_TRAP_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_MCBMCATQ_CFG_CURRENT_DIMM_TRAP = 40 ;
+
+static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_OP_TYPE = 0 ;
+static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_OP_TYPE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_COMPL_1ST_CMD = 4 ;
+static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_COMPL_2ND_CMD = 5 ;
+static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_COMPL_3RD_CMD = 6 ;
+static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_ADDR_REV_MODE = 7 ;
+static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_ADDR_RAND_MODE = 8 ;
+static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_DATA_MODE = 9 ;
+static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_DATA_MODE_LEN = 3 ;
+static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_ECC_MODE = 12 ;
+static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_DONE = 13 ;
+static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_ADDR_SEL = 14 ;
+static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_ADDR_SEL_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_OP_TYPE = 16 ;
+static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_OP_TYPE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_COMPL_1ST_CMD = 20 ;
+static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_COMPL_2ND_CMD = 21 ;
+static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_COMPL_3RD_CMD = 22 ;
+static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_ADDR_REV_MODE = 23 ;
+static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_ADDR_RAND_MODE = 24 ;
+static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_DATA_MODE = 25 ;
+static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_DATA_MODE_LEN = 3 ;
+static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_ECC_MODE = 28 ;
+static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_DONE = 29 ;
+static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_ADDR_SEL = 30 ;
+static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_ADDR_SEL_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_OP_TYPE = 32 ;
+static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_OP_TYPE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_COMPL_1ST_CMD = 36 ;
+static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_COMPL_2ND_CMD = 37 ;
+static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_COMPL_3RD_CMD = 38 ;
+static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_ADDR_REV_MODE = 39 ;
+static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_ADDR_RAND_MODE = 40 ;
+static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_DATA_MODE = 41 ;
+static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_DATA_MODE_LEN = 3 ;
+static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_ECC_MODE = 44 ;
+static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_DONE = 45 ;
+static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_ADDR_SEL = 46 ;
+static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_ADDR_SEL_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_OP_TYPE = 48 ;
+static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_OP_TYPE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_COMPL_1ST_CMD = 52 ;
+static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_COMPL_2ND_CMD = 53 ;
+static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_COMPL_3RD_CMD = 54 ;
+static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_ADDR_REV_MODE = 55 ;
+static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_ADDR_RAND_MODE = 56 ;
+static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_DATA_MODE = 57 ;
+static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_DATA_MODE_LEN = 3 ;
+static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_ECC_MODE = 60 ;
+static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_DONE = 61 ;
+static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_ADDR_SEL = 62 ;
+static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_ADDR_SEL_LEN = 2 ;
+
+static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_OP_TYPE = 0 ;
+static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_OP_TYPE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_COMPL_1ST_CMD = 4 ;
+static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_COMPL_2ND_CMD = 5 ;
+static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_COMPL_3RD_CMD = 6 ;
+static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_ADDR_REV_MODE = 7 ;
+static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_ADDR_RAND_MODE = 8 ;
+static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_DATA_MODE = 9 ;
+static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_DATA_MODE_LEN = 3 ;
+static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_ECC_MODE = 12 ;
+static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_DONE = 13 ;
+static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_ADDR_SEL = 14 ;
+static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_ADDR_SEL_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_OP_TYPE = 16 ;
+static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_OP_TYPE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_COMPL_1ST_CMD = 20 ;
+static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_COMPL_2ND_CMD = 21 ;
+static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_COMPL_3RD_CMD = 22 ;
+static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_ADDR_REV_MODE = 23 ;
+static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_ADDR_RAND_MODE = 24 ;
+static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_DATA_MODE = 25 ;
+static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_DATA_MODE_LEN = 3 ;
+static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_ECC_MODE = 28 ;
+static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_DONE = 29 ;
+static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_ADDR_SEL = 30 ;
+static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_ADDR_SEL_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_OP_TYPE = 32 ;
+static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_OP_TYPE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_COMPL_1ST_CMD = 36 ;
+static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_COMPL_2ND_CMD = 37 ;
+static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_COMPL_3RD_CMD = 38 ;
+static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_ADDR_REV_MODE = 39 ;
+static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_ADDR_RAND_MODE = 40 ;
+static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_DATA_MODE = 41 ;
+static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_DATA_MODE_LEN = 3 ;
+static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_ECC_MODE = 44 ;
+static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_DONE = 45 ;
+static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_ADDR_SEL = 46 ;
+static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_ADDR_SEL_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_OP_TYPE = 48 ;
+static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_OP_TYPE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_COMPL_1ST_CMD = 52 ;
+static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_COMPL_2ND_CMD = 53 ;
+static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_COMPL_3RD_CMD = 54 ;
+static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_ADDR_REV_MODE = 55 ;
+static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_ADDR_RAND_MODE = 56 ;
+static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_DATA_MODE = 57 ;
+static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_DATA_MODE_LEN = 3 ;
+static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_ECC_MODE = 60 ;
+static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_DONE = 61 ;
+static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_ADDR_SEL = 62 ;
+static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_ADDR_SEL_LEN = 2 ;
+
+static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_OP_TYPE = 0 ;
+static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_OP_TYPE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_COMPL_1ST_CMD = 4 ;
+static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_COMPL_2ND_CMD = 5 ;
+static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_COMPL_3RD_CMD = 6 ;
+static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_ADDR_REV_MODE = 7 ;
+static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_ADDR_RAND_MODE = 8 ;
+static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_DATA_MODE = 9 ;
+static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_DATA_MODE_LEN = 3 ;
+static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_ECC_MODE = 12 ;
+static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_DONE = 13 ;
+static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_ADDR_SEL = 14 ;
+static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_ADDR_SEL_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_OP_TYPE = 16 ;
+static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_OP_TYPE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_COMPL_1ST_CMD = 20 ;
+static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_COMPL_2ND_CMD = 21 ;
+static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_COMPL_3RD_CMD = 22 ;
+static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_ADDR_REV_MODE = 23 ;
+static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_ADDR_RAND_MODE = 24 ;
+static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_DATA_MODE = 25 ;
+static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_DATA_MODE_LEN = 3 ;
+static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_ECC_MODE = 28 ;
+static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_DONE = 29 ;
+static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_ADDR_SEL = 30 ;
+static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_ADDR_SEL_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_OP_TYPE = 32 ;
+static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_OP_TYPE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_COMPL_1ST_CMD = 36 ;
+static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_COMPL_2ND_CMD = 37 ;
+static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_COMPL_3RD_CMD = 38 ;
+static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_ADDR_REV_MODE = 39 ;
+static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_ADDR_RAND_MODE = 40 ;
+static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_DATA_MODE = 41 ;
+static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_DATA_MODE_LEN = 3 ;
+static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_ECC_MODE = 44 ;
+static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_DONE = 45 ;
+static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_ADDR_SEL = 46 ;
+static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_ADDR_SEL_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_OP_TYPE = 48 ;
+static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_OP_TYPE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_COMPL_1ST_CMD = 52 ;
+static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_COMPL_2ND_CMD = 53 ;
+static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_COMPL_3RD_CMD = 54 ;
+static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_ADDR_REV_MODE = 55 ;
+static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_ADDR_RAND_MODE = 56 ;
+static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_DATA_MODE = 57 ;
+static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_DATA_MODE_LEN = 3 ;
+static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_ECC_MODE = 60 ;
+static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_DONE = 61 ;
+static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_ADDR_SEL = 62 ;
+static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_ADDR_SEL_LEN = 2 ;
+
+static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_OP_TYPE = 0 ;
+static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_OP_TYPE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_COMPL_1ST_CMD = 4 ;
+static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_COMPL_2ND_CMD = 5 ;
+static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_COMPL_3RD_CMD = 6 ;
+static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_ADDR_REV_MODE = 7 ;
+static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_ADDR_RAND_MODE = 8 ;
+static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_DATA_MODE = 9 ;
+static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_DATA_MODE_LEN = 3 ;
+static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_ECC_MODE = 12 ;
+static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_DONE = 13 ;
+static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_ADDR_SEL = 14 ;
+static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_ADDR_SEL_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_OP_TYPE = 16 ;
+static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_OP_TYPE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_COMPL_1ST_CMD = 20 ;
+static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_COMPL_2ND_CMD = 21 ;
+static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_COMPL_3RD_CMD = 22 ;
+static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_ADDR_REV_MODE = 23 ;
+static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_ADDR_RAND_MODE = 24 ;
+static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_DATA_MODE = 25 ;
+static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_DATA_MODE_LEN = 3 ;
+static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_ECC_MODE = 28 ;
+static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_DONE = 29 ;
+static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_ADDR_SEL = 30 ;
+static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_ADDR_SEL_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_OP_TYPE = 32 ;
+static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_OP_TYPE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_COMPL_1ST_CMD = 36 ;
+static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_COMPL_2ND_CMD = 37 ;
+static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_COMPL_3RD_CMD = 38 ;
+static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_ADDR_REV_MODE = 39 ;
+static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_ADDR_RAND_MODE = 40 ;
+static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_DATA_MODE = 41 ;
+static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_DATA_MODE_LEN = 3 ;
+static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_ECC_MODE = 44 ;
+static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_DONE = 45 ;
+static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_ADDR_SEL = 46 ;
+static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_ADDR_SEL_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_OP_TYPE = 48 ;
+static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_OP_TYPE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_COMPL_1ST_CMD = 52 ;
+static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_COMPL_2ND_CMD = 53 ;
+static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_COMPL_3RD_CMD = 54 ;
+static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_ADDR_REV_MODE = 55 ;
+static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_ADDR_RAND_MODE = 56 ;
+static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_DATA_MODE = 57 ;
+static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_DATA_MODE_LEN = 3 ;
+static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_ECC_MODE = 60 ;
+static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_DONE = 61 ;
+static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_ADDR_SEL = 62 ;
+static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_ADDR_SEL_LEN = 2 ;
+
+static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_OP_TYPE = 0 ;
+static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_OP_TYPE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_COMPL_1ST_CMD = 4 ;
+static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_COMPL_2ND_CMD = 5 ;
+static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_COMPL_3RD_CMD = 6 ;
+static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_ADDR_REV_MODE = 7 ;
+static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_ADDR_RAND_MODE = 8 ;
+static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_DATA_MODE = 9 ;
+static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_DATA_MODE_LEN = 3 ;
+static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_ECC_MODE = 12 ;
+static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_DONE = 13 ;
+static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_ADDR_SEL = 14 ;
+static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_ADDR_SEL_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_OP_TYPE = 16 ;
+static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_OP_TYPE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_COMPL_1ST_CMD = 20 ;
+static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_COMPL_2ND_CMD = 21 ;
+static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_COMPL_3RD_CMD = 22 ;
+static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_ADDR_REV_MODE = 23 ;
+static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_ADDR_RAND_MODE = 24 ;
+static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_DATA_MODE = 25 ;
+static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_DATA_MODE_LEN = 3 ;
+static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_ECC_MODE = 28 ;
+static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_DONE = 29 ;
+static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_ADDR_SEL = 30 ;
+static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_ADDR_SEL_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_OP_TYPE = 32 ;
+static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_OP_TYPE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_COMPL_1ST_CMD = 36 ;
+static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_COMPL_2ND_CMD = 37 ;
+static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_COMPL_3RD_CMD = 38 ;
+static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_ADDR_REV_MODE = 39 ;
+static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_ADDR_RAND_MODE = 40 ;
+static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_DATA_MODE = 41 ;
+static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_DATA_MODE_LEN = 3 ;
+static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_ECC_MODE = 44 ;
+static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_DONE = 45 ;
+static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_ADDR_SEL = 46 ;
+static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_ADDR_SEL_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_OP_TYPE = 48 ;
+static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_OP_TYPE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_COMPL_1ST_CMD = 52 ;
+static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_COMPL_2ND_CMD = 53 ;
+static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_COMPL_3RD_CMD = 54 ;
+static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_ADDR_REV_MODE = 55 ;
+static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_ADDR_RAND_MODE = 56 ;
+static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_DATA_MODE = 57 ;
+static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_DATA_MODE_LEN = 3 ;
+static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_ECC_MODE = 60 ;
+static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_DONE = 61 ;
+static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_ADDR_SEL = 62 ;
+static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_ADDR_SEL_LEN = 2 ;
+
+static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_OP_TYPE = 0 ;
+static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_OP_TYPE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_COMPL_1ST_CMD = 4 ;
+static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_COMPL_2ND_CMD = 5 ;
+static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_COMPL_3RD_CMD = 6 ;
+static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_ADDR_REV_MODE = 7 ;
+static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_ADDR_RAND_MODE = 8 ;
+static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_DATA_MODE = 9 ;
+static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_DATA_MODE_LEN = 3 ;
+static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_ECC_MODE = 12 ;
+static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_DONE = 13 ;
+static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_ADDR_SEL = 14 ;
+static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_ADDR_SEL_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_OP_TYPE = 16 ;
+static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_OP_TYPE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_COMPL_1ST_CMD = 20 ;
+static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_COMPL_2ND_CMD = 21 ;
+static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_COMPL_3RD_CMD = 22 ;
+static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_ADDR_REV_MODE = 23 ;
+static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_ADDR_RAND_MODE = 24 ;
+static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_DATA_MODE = 25 ;
+static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_DATA_MODE_LEN = 3 ;
+static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_ECC_MODE = 28 ;
+static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_DONE = 29 ;
+static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_ADDR_SEL = 30 ;
+static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_ADDR_SEL_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_OP_TYPE = 32 ;
+static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_OP_TYPE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_COMPL_1ST_CMD = 36 ;
+static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_COMPL_2ND_CMD = 37 ;
+static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_COMPL_3RD_CMD = 38 ;
+static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_ADDR_REV_MODE = 39 ;
+static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_ADDR_RAND_MODE = 40 ;
+static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_DATA_MODE = 41 ;
+static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_DATA_MODE_LEN = 3 ;
+static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_ECC_MODE = 44 ;
+static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_DONE = 45 ;
+static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_ADDR_SEL = 46 ;
+static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_ADDR_SEL_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_OP_TYPE = 48 ;
+static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_OP_TYPE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_COMPL_1ST_CMD = 52 ;
+static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_COMPL_2ND_CMD = 53 ;
+static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_COMPL_3RD_CMD = 54 ;
+static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_ADDR_REV_MODE = 55 ;
+static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_ADDR_RAND_MODE = 56 ;
+static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_DATA_MODE = 57 ;
+static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_DATA_MODE_LEN = 3 ;
+static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_ECC_MODE = 60 ;
+static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_DONE = 61 ;
+static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_ADDR_SEL = 62 ;
+static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_ADDR_SEL_LEN = 2 ;
+
+static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_OP_TYPE = 0 ;
+static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_OP_TYPE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_COMPL_1ST_CMD = 4 ;
+static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_COMPL_2ND_CMD = 5 ;
+static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_COMPL_3RD_CMD = 6 ;
+static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_ADDR_REV_MODE = 7 ;
+static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_ADDR_RAND_MODE = 8 ;
+static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_DATA_MODE = 9 ;
+static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_DATA_MODE_LEN = 3 ;
+static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_ECC_MODE = 12 ;
+static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_DONE = 13 ;
+static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_ADDR_SEL = 14 ;
+static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_ADDR_SEL_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_OP_TYPE = 16 ;
+static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_OP_TYPE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_COMPL_1ST_CMD = 20 ;
+static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_COMPL_2ND_CMD = 21 ;
+static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_COMPL_3RD_CMD = 22 ;
+static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_ADDR_REV_MODE = 23 ;
+static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_ADDR_RAND_MODE = 24 ;
+static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_DATA_MODE = 25 ;
+static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_DATA_MODE_LEN = 3 ;
+static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_ECC_MODE = 28 ;
+static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_DONE = 29 ;
+static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_ADDR_SEL = 30 ;
+static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_ADDR_SEL_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_OP_TYPE = 32 ;
+static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_OP_TYPE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_COMPL_1ST_CMD = 36 ;
+static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_COMPL_2ND_CMD = 37 ;
+static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_COMPL_3RD_CMD = 38 ;
+static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_ADDR_REV_MODE = 39 ;
+static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_ADDR_RAND_MODE = 40 ;
+static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_DATA_MODE = 41 ;
+static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_DATA_MODE_LEN = 3 ;
+static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_ECC_MODE = 44 ;
+static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_DONE = 45 ;
+static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_ADDR_SEL = 46 ;
+static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_ADDR_SEL_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_OP_TYPE = 48 ;
+static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_OP_TYPE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_COMPL_1ST_CMD = 52 ;
+static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_COMPL_2ND_CMD = 53 ;
+static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_COMPL_3RD_CMD = 54 ;
+static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_ADDR_REV_MODE = 55 ;
+static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_ADDR_RAND_MODE = 56 ;
+static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_DATA_MODE = 57 ;
+static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_DATA_MODE_LEN = 3 ;
+static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_ECC_MODE = 60 ;
+static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_DONE = 61 ;
+static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_ADDR_SEL = 62 ;
+static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_ADDR_SEL_LEN = 2 ;
+
+static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_OP_TYPE = 0 ;
+static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_OP_TYPE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_COMPL_1ST_CMD = 4 ;
+static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_COMPL_2ND_CMD = 5 ;
+static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_COMPL_3RD_CMD = 6 ;
+static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_ADDR_REV_MODE = 7 ;
+static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_ADDR_RAND_MODE = 8 ;
+static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_DATA_MODE = 9 ;
+static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_DATA_MODE_LEN = 3 ;
+static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_ECC_MODE = 12 ;
+static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_DONE = 13 ;
+static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_ADDR_SEL = 14 ;
+static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_ADDR_SEL_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_OP_TYPE = 16 ;
+static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_OP_TYPE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_COMPL_1ST_CMD = 20 ;
+static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_COMPL_2ND_CMD = 21 ;
+static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_COMPL_3RD_CMD = 22 ;
+static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_ADDR_REV_MODE = 23 ;
+static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_ADDR_RAND_MODE = 24 ;
+static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_DATA_MODE = 25 ;
+static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_DATA_MODE_LEN = 3 ;
+static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_ECC_MODE = 28 ;
+static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_DONE = 29 ;
+static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_ADDR_SEL = 30 ;
+static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_ADDR_SEL_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_OP_TYPE = 32 ;
+static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_OP_TYPE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_COMPL_1ST_CMD = 36 ;
+static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_COMPL_2ND_CMD = 37 ;
+static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_COMPL_3RD_CMD = 38 ;
+static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_ADDR_REV_MODE = 39 ;
+static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_ADDR_RAND_MODE = 40 ;
+static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_DATA_MODE = 41 ;
+static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_DATA_MODE_LEN = 3 ;
+static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_ECC_MODE = 44 ;
+static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_DONE = 45 ;
+static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_ADDR_SEL = 46 ;
+static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_ADDR_SEL_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_OP_TYPE = 48 ;
+static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_OP_TYPE_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_COMPL_1ST_CMD = 52 ;
+static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_COMPL_2ND_CMD = 53 ;
+static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_COMPL_3RD_CMD = 54 ;
+static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_ADDR_REV_MODE = 55 ;
+static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_ADDR_RAND_MODE = 56 ;
+static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_DATA_MODE = 57 ;
+static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_DATA_MODE_LEN = 3 ;
+static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_ECC_MODE = 60 ;
+static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_DONE = 61 ;
+static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_ADDR_SEL = 62 ;
+static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_ADDR_SEL_LEN = 2 ;
+
+static const uint8_t P9N2_MCBIST_MCBPARMQ_CFG_MIN_CMD_GAP = 0 ;
+static const uint8_t P9N2_MCBIST_MCBPARMQ_CFG_MIN_CMD_GAP_LEN = 12 ;
+static const uint8_t P9N2_MCBIST_MCBPARMQ_CFG_MIN_GAP_TIMEBASE = 12 ;
+static const uint8_t P9N2_MCBIST_MCBPARMQ_CFG_MIN_CMD_GAP_BLIND_STEER = 13 ;
+static const uint8_t P9N2_MCBIST_MCBPARMQ_CFG_MIN_CMD_GAP_BLIND_STEER_LEN = 12 ;
+static const uint8_t P9N2_MCBIST_MCBPARMQ_CFG_MIN_GAP_TIMEBASE_BLIND_STEER = 25 ;
+static const uint8_t P9N2_MCBIST_MCBPARMQ_RESERVED_26_49 = 26 ;
+static const uint8_t P9N2_MCBIST_MCBPARMQ_RESERVED_26_49_LEN = 24 ;
+static const uint8_t P9N2_MCBIST_MCBPARMQ_CFG_RANDCMD_WGT = 50 ;
+static const uint8_t P9N2_MCBIST_MCBPARMQ_CFG_RANDCMD_WGT_LEN = 3 ;
+static const uint8_t P9N2_MCBIST_MCBPARMQ_RESERVED_53_58 = 53 ;
+static const uint8_t P9N2_MCBIST_MCBPARMQ_RESERVED_53_58_LEN = 6 ;
+static const uint8_t P9N2_MCBIST_MCBPARMQ_CFG_CLOCK_MONITOR_EN = 59 ;
+static const uint8_t P9N2_MCBIST_MCBPARMQ_CFG_EN_RANDCMD_GAP = 60 ;
+static const uint8_t P9N2_MCBIST_MCBPARMQ_CFG_RANDGAP_WGT = 61 ;
+static const uint8_t P9N2_MCBIST_MCBPARMQ_CFG_RANDGAP_WGT_LEN = 2 ;
+static const uint8_t P9N2_MCBIST_MCBPARMQ_CFG_BC4_EN = 63 ;
+
+static const uint8_t P9N2_MCBIST_MCBRCRQ_RESERVED_0_31 = 0 ;
+static const uint8_t P9N2_MCBIST_MCBRCRQ_RESERVED_0_31_LEN = 32 ;
+static const uint8_t P9N2_MCBIST_MCBRCRQ_CFG_RUNTIME_MCBALL = 32 ;
+static const uint8_t P9N2_MCBIST_MCBRCRQ_CFG_RUNTIME_SUBTEST = 33 ;
+static const uint8_t P9N2_MCBIST_MCBRCRQ_CFG_RUNTIME_SUBTEST_LEN = 5 ;
+static const uint8_t P9N2_MCBIST_MCBRCRQ_CFG_RUNTIME_OVERHEAD = 38 ;
+static const uint8_t P9N2_MCBIST_MCBRCRQ_RESERVED_39 = 39 ;
+
+static const uint8_t P9N2_MCBIST_MCBRDS0Q_DGEN_RNDD_SEED0 = 0 ;
+static const uint8_t P9N2_MCBIST_MCBRDS0Q_DGEN_RNDD_SEED0_LEN = 24 ;
+static const uint8_t P9N2_MCBIST_MCBRDS0Q_DGEN_RNDD_SEED1 = 24 ;
+static const uint8_t P9N2_MCBIST_MCBRDS0Q_DGEN_RNDD_SEED1_LEN = 24 ;
+
+static const uint8_t P9N2_MCBIST_MCBRDS1Q_DGEN_RNDD_SEED2 = 0 ;
+static const uint8_t P9N2_MCBIST_MCBRDS1Q_DGEN_RNDD_SEED2_LEN = 24 ;
+static const uint8_t P9N2_MCBIST_MCBRDS1Q_DGEN_RNDD_DATA_MAPPING = 24 ;
+static const uint8_t P9N2_MCBIST_MCBRDS1Q_DGEN_RNDD_DATA_MAPPING_LEN = 40 ;
+
+static const uint8_t P9N2_MCBIST_MCBSA0Q_CFG_START_ADDR_0 = 0 ;
+static const uint8_t P9N2_MCBIST_MCBSA0Q_CFG_START_ADDR_0_LEN = 38 ;
+
+static const uint8_t P9N2_MCBIST_MCBSA1Q_CFG_START_ADDR_1 = 0 ;
+static const uint8_t P9N2_MCBIST_MCBSA1Q_CFG_START_ADDR_1_LEN = 38 ;
+
+static const uint8_t P9N2_MCBIST_MCBSA2Q_CFG_START_ADDR_2 = 0 ;
+static const uint8_t P9N2_MCBIST_MCBSA2Q_CFG_START_ADDR_2_LEN = 38 ;
+
+static const uint8_t P9N2_MCBIST_MCBSA3Q_CFG_START_ADDR_3 = 0 ;
+static const uint8_t P9N2_MCBIST_MCBSA3Q_CFG_START_ADDR_3_LEN = 38 ;
+
+static const uint8_t P9N2_MCBIST_MCBSTATQ_MCBIST_LOGGED_ERROR_ON_PORT_INDICATOR = 0 ;
+static const uint8_t P9N2_MCBIST_MCBSTATQ_MCBIST_LOGGED_ERROR_ON_PORT_INDICATOR_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_MCBSTATQ_MCBIST_SUBTEST_NUM_INDICATOR = 4 ;
+static const uint8_t P9N2_MCBIST_MCBSTATQ_MCBIST_SUBTEST_NUM_INDICATOR_LEN = 5 ;
+static const uint8_t P9N2_MCBIST_MCBSTATQ_RESERVED_9_15 = 9 ;
+static const uint8_t P9N2_MCBIST_MCBSTATQ_RESERVED_9_15_LEN = 7 ;
+
+static const uint8_t P9N2_MCS_PORT02_MCBUSYQ_ENABLE_BUSY_COUNTERS = 0 ;
+static const uint8_t P9N2_MCS_PORT02_MCBUSYQ_BUSY_COUNTER_WINDOW_SELECT = 1 ;
+static const uint8_t P9N2_MCS_PORT02_MCBUSYQ_BUSY_COUNTER_WINDOW_SELECT_LEN = 3 ;
+static const uint8_t P9N2_MCS_PORT02_MCBUSYQ_BUSY_COUNTER_THRESHOLD0 = 4 ;
+static const uint8_t P9N2_MCS_PORT02_MCBUSYQ_BUSY_COUNTER_THRESHOLD0_LEN = 10 ;
+static const uint8_t P9N2_MCS_PORT02_MCBUSYQ_BUSY_COUNTER_THRESHOLD1 = 14 ;
+static const uint8_t P9N2_MCS_PORT02_MCBUSYQ_BUSY_COUNTER_THRESHOLD1_LEN = 10 ;
+static const uint8_t P9N2_MCS_PORT02_MCBUSYQ_BUSY_COUNTER_THRESHOLD2 = 24 ;
+static const uint8_t P9N2_MCS_PORT02_MCBUSYQ_BUSY_COUNTER_THRESHOLD2_LEN = 10 ;
+static const uint8_t P9N2_MCS_PORT02_MCBUSYQ_ENABLE_AGGRESSIVE_BUSY = 34 ;
+static const uint8_t P9N2_MCS_PORT02_MCBUSYQ_RSVD_35_43 = 35 ;
+static const uint8_t P9N2_MCS_PORT02_MCBUSYQ_RSVD_35_43_LEN = 9 ;
+
+static const uint8_t P9N2_MCS_PORT13_MCBUSYQ_ENABLE_BUSY_COUNTERS = 0 ;
+static const uint8_t P9N2_MCS_PORT13_MCBUSYQ_BUSY_COUNTER_WINDOW_SELECT = 1 ;
+static const uint8_t P9N2_MCS_PORT13_MCBUSYQ_BUSY_COUNTER_WINDOW_SELECT_LEN = 3 ;
+static const uint8_t P9N2_MCS_PORT13_MCBUSYQ_BUSY_COUNTER_THRESHOLD0 = 4 ;
+static const uint8_t P9N2_MCS_PORT13_MCBUSYQ_BUSY_COUNTER_THRESHOLD0_LEN = 10 ;
+static const uint8_t P9N2_MCS_PORT13_MCBUSYQ_BUSY_COUNTER_THRESHOLD1 = 14 ;
+static const uint8_t P9N2_MCS_PORT13_MCBUSYQ_BUSY_COUNTER_THRESHOLD1_LEN = 10 ;
+static const uint8_t P9N2_MCS_PORT13_MCBUSYQ_BUSY_COUNTER_THRESHOLD2 = 24 ;
+static const uint8_t P9N2_MCS_PORT13_MCBUSYQ_BUSY_COUNTER_THRESHOLD2_LEN = 10 ;
+static const uint8_t P9N2_MCS_PORT13_MCBUSYQ_ENABLE_AGGRESSIVE_BUSY = 34 ;
+static const uint8_t P9N2_MCS_PORT13_MCBUSYQ_RSVD_35_43 = 35 ;
+static const uint8_t P9N2_MCS_PORT13_MCBUSYQ_RSVD_35_43_LEN = 9 ;
+
+static const uint8_t P9N2_MCBIST_MCB_CNTLQ_START = 0 ;
+static const uint8_t P9N2_MCBIST_MCB_CNTLQ_STOP = 1 ;
+static const uint8_t P9N2_MCBIST_MCB_CNTLQ_MCBCNTL_PORT_SEL = 2 ;
+static const uint8_t P9N2_MCBIST_MCB_CNTLQ_MCBCNTL_PORT_SEL_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_MCB_CNTLQ_RESET_TRAP_CNFG = 6 ;
+static const uint8_t P9N2_MCBIST_MCB_CNTLQ_RESET_ERROR_LOGS = 7 ;
+static const uint8_t P9N2_MCBIST_MCB_CNTLQ_RESUME_FROM_PAUSE = 8 ;
+
+static const uint8_t P9N2_MCBIST_MCB_CNTLSTATQ_IP = 0 ;
+static const uint8_t P9N2_MCBIST_MCB_CNTLSTATQ_DONE = 1 ;
+static const uint8_t P9N2_MCBIST_MCB_CNTLSTATQ_FAIL = 2 ;
+
+static const uint8_t P9N2_MCS_MCDBG0_DEBUG_BUS_0_63 = 0 ;
+static const uint8_t P9N2_MCS_MCDBG0_DEBUG_BUS_0_63_LEN = 64 ;
+
+static const uint8_t P9N2_MCS_MCDBG1_DEBUG_BUS_64_87 = 0 ;
+static const uint8_t P9N2_MCS_MCDBG1_DEBUG_BUS_64_87_LEN = 24 ;
+static const uint8_t P9N2_MCS_MCDBG1_WRQ0_EMPTY = 24 ;
+static const uint8_t P9N2_MCS_MCDBG1_WRQ1_EMPTY = 25 ;
+
+static const uint8_t P9N2_MCS_PORT02_MCEBUSCL_BYTE0_SEL = 0 ;
+static const uint8_t P9N2_MCS_PORT02_MCEBUSCL_BYTE0_SEL_LEN = 2 ;
+static const uint8_t P9N2_MCS_PORT02_MCEBUSCL_BYTE1_SEL = 2 ;
+static const uint8_t P9N2_MCS_PORT02_MCEBUSCL_BYTE1_SEL_LEN = 2 ;
+static const uint8_t P9N2_MCS_PORT02_MCEBUSCL_BYTE2_SEL = 4 ;
+static const uint8_t P9N2_MCS_PORT02_MCEBUSCL_BYTE2_SEL_LEN = 2 ;
+static const uint8_t P9N2_MCS_PORT02_MCEBUSCL_BYTE3_SEL = 6 ;
+static const uint8_t P9N2_MCS_PORT02_MCEBUSCL_BYTE3_SEL_LEN = 2 ;
+static const uint8_t P9N2_MCS_PORT02_MCEBUSCL_LAT_THRESHA = 8 ;
+static const uint8_t P9N2_MCS_PORT02_MCEBUSCL_LAT_THRESHA_LEN = 8 ;
+static const uint8_t P9N2_MCS_PORT02_MCEBUSCL_LAT_THRESHB = 16 ;
+static const uint8_t P9N2_MCS_PORT02_MCEBUSCL_LAT_THRESHB_LEN = 8 ;
+static const uint8_t P9N2_MCS_PORT02_MCEBUSCL_LAT_THRESHC = 24 ;
+static const uint8_t P9N2_MCS_PORT02_MCEBUSCL_LAT_THRESHC_LEN = 8 ;
+static const uint8_t P9N2_MCS_PORT02_MCEBUSCL_SCOM20A_SEL = 32 ;
+static const uint8_t P9N2_MCS_PORT02_MCEBUSCL_SCOM28A_30A_SEL = 33 ;
+
+static const uint8_t P9N2_MCS_PORT13_MCEBUSCL_BYTE0_SEL = 0 ;
+static const uint8_t P9N2_MCS_PORT13_MCEBUSCL_BYTE0_SEL_LEN = 2 ;
+static const uint8_t P9N2_MCS_PORT13_MCEBUSCL_BYTE1_SEL = 2 ;
+static const uint8_t P9N2_MCS_PORT13_MCEBUSCL_BYTE1_SEL_LEN = 2 ;
+static const uint8_t P9N2_MCS_PORT13_MCEBUSCL_BYTE2_SEL = 4 ;
+static const uint8_t P9N2_MCS_PORT13_MCEBUSCL_BYTE2_SEL_LEN = 2 ;
+static const uint8_t P9N2_MCS_PORT13_MCEBUSCL_BYTE3_SEL = 6 ;
+static const uint8_t P9N2_MCS_PORT13_MCEBUSCL_BYTE3_SEL_LEN = 2 ;
+static const uint8_t P9N2_MCS_PORT13_MCEBUSCL_LAT_THRESHA = 8 ;
+static const uint8_t P9N2_MCS_PORT13_MCEBUSCL_LAT_THRESHA_LEN = 8 ;
+static const uint8_t P9N2_MCS_PORT13_MCEBUSCL_LAT_THRESHB = 16 ;
+static const uint8_t P9N2_MCS_PORT13_MCEBUSCL_LAT_THRESHB_LEN = 8 ;
+static const uint8_t P9N2_MCS_PORT13_MCEBUSCL_LAT_THRESHC = 24 ;
+static const uint8_t P9N2_MCS_PORT13_MCEBUSCL_LAT_THRESHC_LEN = 8 ;
+static const uint8_t P9N2_MCS_PORT13_MCEBUSCL_SCOM20A_SEL = 32 ;
+static const uint8_t P9N2_MCS_PORT13_MCEBUSCL_SCOM28A_30A_SEL = 33 ;
+
+static const uint8_t P9N2_MCS_PORT13_MCEBUSEN0_EVENT_BUS_SELECTS = 0 ;
+static const uint8_t P9N2_MCS_PORT13_MCEBUSEN0_EVENT_BUS_SELECTS_LEN = 64 ;
+
+static const uint8_t P9N2_MCS_PORT13_MCEBUSEN1_EVENT_BUS_SELECTS = 0 ;
+static const uint8_t P9N2_MCS_PORT13_MCEBUSEN1_EVENT_BUS_SELECTS_LEN = 64 ;
+
+static const uint8_t P9N2_MCS_PORT13_MCEBUSEN2_EVENT_BUS_SELECTS = 0 ;
+static const uint8_t P9N2_MCS_PORT13_MCEBUSEN2_EVENT_BUS_SELECTS_LEN = 64 ;
+
+static const uint8_t P9N2_MCS_PORT13_MCEBUSEN3_EVENT_BUS_EN = 0 ;
+static const uint8_t P9N2_MCS_PORT13_MCEBUSEN3_EVENT_BUS_EN_LEN = 16 ;
+static const uint8_t P9N2_MCS_PORT13_MCEBUSEN3_EVENT_BUS_ENABLE = 16 ;
+static const uint8_t P9N2_MCS_PORT13_MCEBUSEN3_EBUS_16A_SELECT = 17 ;
+
+static const uint8_t P9N2_MCS_PORT02_MCEPSQ_JITTER_EPSILON = 0 ;
+static const uint8_t P9N2_MCS_PORT02_MCEPSQ_JITTER_EPSILON_LEN = 8 ;
+static const uint8_t P9N2_MCS_PORT02_MCEPSQ_LOCAL_NODE_EPSILON = 8 ;
+static const uint8_t P9N2_MCS_PORT02_MCEPSQ_LOCAL_NODE_EPSILON_LEN = 8 ;
+static const uint8_t P9N2_MCS_PORT02_MCEPSQ_NEAR_NODAL_EPSILON = 16 ;
+static const uint8_t P9N2_MCS_PORT02_MCEPSQ_NEAR_NODAL_EPSILON_LEN = 8 ;
+static const uint8_t P9N2_MCS_PORT02_MCEPSQ_GROUP_EPSILON = 24 ;
+static const uint8_t P9N2_MCS_PORT02_MCEPSQ_GROUP_EPSILON_LEN = 8 ;
+static const uint8_t P9N2_MCS_PORT02_MCEPSQ_REMOTE_NODAL_EPSILON = 32 ;
+static const uint8_t P9N2_MCS_PORT02_MCEPSQ_REMOTE_NODAL_EPSILON_LEN = 8 ;
+static const uint8_t P9N2_MCS_PORT02_MCEPSQ_VECTOR_GROUP_EPSILON = 40 ;
+static const uint8_t P9N2_MCS_PORT02_MCEPSQ_VECTOR_GROUP_EPSILON_LEN = 8 ;
+
+static const uint8_t P9N2_MCS_PORT13_MCEPSQ_JITTER_EPSILON = 0 ;
+static const uint8_t P9N2_MCS_PORT13_MCEPSQ_JITTER_EPSILON_LEN = 8 ;
+static const uint8_t P9N2_MCS_PORT13_MCEPSQ_LOCAL_NODE_EPSILON = 8 ;
+static const uint8_t P9N2_MCS_PORT13_MCEPSQ_LOCAL_NODE_EPSILON_LEN = 8 ;
+static const uint8_t P9N2_MCS_PORT13_MCEPSQ_NEAR_NODAL_EPSILON = 16 ;
+static const uint8_t P9N2_MCS_PORT13_MCEPSQ_NEAR_NODAL_EPSILON_LEN = 8 ;
+static const uint8_t P9N2_MCS_PORT13_MCEPSQ_GROUP_EPSILON = 24 ;
+static const uint8_t P9N2_MCS_PORT13_MCEPSQ_GROUP_EPSILON_LEN = 8 ;
+static const uint8_t P9N2_MCS_PORT13_MCEPSQ_REMOTE_NODAL_EPSILON = 32 ;
+static const uint8_t P9N2_MCS_PORT13_MCEPSQ_REMOTE_NODAL_EPSILON_LEN = 8 ;
+static const uint8_t P9N2_MCS_PORT13_MCEPSQ_VECTOR_GROUP_EPSILON = 40 ;
+static const uint8_t P9N2_MCS_PORT13_MCEPSQ_VECTOR_GROUP_EPSILON_LEN = 8 ;
+
+static const uint8_t P9N2_MCS_MCERPT0_DATA = 0 ;
+static const uint8_t P9N2_MCS_MCERPT0_DATA_LEN = 63 ;
+
+static const uint8_t P9N2_MCS_MCERPT1_DATA = 0 ;
+static const uint8_t P9N2_MCS_MCERPT1_DATA_LEN = 63 ;
+
+static const uint8_t P9N2_MCS_MCERPT2_DATA = 0 ;
+static const uint8_t P9N2_MCS_MCERPT2_DATA_LEN = 7 ;
+
+static const uint8_t P9N2_MCS_PORT02_MCERRINJ_WDF_ERR_INJECT0 = 0 ;
+static const uint8_t P9N2_MCS_PORT02_MCERRINJ_WDF_ERR_INJECT0_LEN = 4 ;
+static const uint8_t P9N2_MCS_PORT02_MCERRINJ_READ_ERR_INJECT0 = 4 ;
+static const uint8_t P9N2_MCS_PORT02_MCERRINJ_READ_ERR_INJECT0_LEN = 4 ;
+static const uint8_t P9N2_MCS_PORT02_MCERRINJ_WRITE_ERR_INJECT0 = 8 ;
+static const uint8_t P9N2_MCS_PORT02_MCERRINJ_WRITE_ERR_INJECT0_LEN = 4 ;
+static const uint8_t P9N2_MCS_PORT02_MCERRINJ_READ_PAR_NOT_SEQ = 12 ;
+static const uint8_t P9N2_MCS_PORT02_MCERRINJ_RCMD_ERR_INJ = 13 ;
+static const uint8_t P9N2_MCS_PORT02_MCERRINJ_PF_PROMOTE_ERR_INJ = 14 ;
+static const uint8_t P9N2_MCS_PORT02_MCERRINJ_RESET_KEEPER = 15 ;
+
+static const uint8_t P9N2_MCS_PORT13_MCERRINJ_WDF_ERR_INJECT0 = 0 ;
+static const uint8_t P9N2_MCS_PORT13_MCERRINJ_WDF_ERR_INJECT0_LEN = 4 ;
+static const uint8_t P9N2_MCS_PORT13_MCERRINJ_READ_ERR_INJECT0 = 4 ;
+static const uint8_t P9N2_MCS_PORT13_MCERRINJ_READ_ERR_INJECT0_LEN = 4 ;
+static const uint8_t P9N2_MCS_PORT13_MCERRINJ_WRITE_ERR_INJECT0 = 8 ;
+static const uint8_t P9N2_MCS_PORT13_MCERRINJ_WRITE_ERR_INJECT0_LEN = 4 ;
+static const uint8_t P9N2_MCS_PORT13_MCERRINJ_READ_PAR_NOT_SEQ = 12 ;
+static const uint8_t P9N2_MCS_PORT13_MCERRINJ_RCMD_ERR_INJ = 13 ;
+static const uint8_t P9N2_MCS_PORT13_MCERRINJ_PF_PROMOTE_ERR_INJ = 14 ;
+static const uint8_t P9N2_MCS_PORT13_MCERRINJ_RESET_KEEPER = 15 ;
+
+static const uint8_t P9N2_MCS_MCFGP_VALID = 0 ;
+static const uint8_t P9N2_MCS_MCFGP_MC_CHANNELS_PER_GROUP = 1 ;
+static const uint8_t P9N2_MCS_MCFGP_MC_CHANNELS_PER_GROUP_LEN = 4 ;
+static const uint8_t P9N2_MCS_MCFGP_CHANNEL_0_GROUP_MEMBER_IDENTIFICATION = 5 ;
+static const uint8_t P9N2_MCS_MCFGP_CHANNEL_0_GROUP_MEMBER_IDENTIFICATION_LEN = 3 ;
+static const uint8_t P9N2_MCS_MCFGP_CHANNEL_1_GROUP_MEMBER_IDENTIFICATION = 8 ;
+static const uint8_t P9N2_MCS_MCFGP_CHANNEL_1_GROUP_MEMBER_IDENTIFICATION_LEN = 3 ;
+static const uint8_t P9N2_MCS_MCFGP_RESERVED_11_12 = 11 ;
+static const uint8_t P9N2_MCS_MCFGP_RESERVED_11_12_LEN = 2 ;
+static const uint8_t P9N2_MCS_MCFGP_GROUP_SIZE = 13 ;
+static const uint8_t P9N2_MCS_MCFGP_GROUP_SIZE_LEN = 11 ;
+static const uint8_t P9N2_MCS_MCFGP_GROUP_BASE_ADDRESS = 24 ;
+static const uint8_t P9N2_MCS_MCFGP_GROUP_BASE_ADDRESS_LEN = 24 ;
+
+static const uint8_t P9N2_MCS_MCFGPA_HOLE0_VALID = 0 ;
+static const uint8_t P9N2_MCS_MCFGPA_HOLE0_UPPER_ADDRESS_AT_END_OF_RANGE = 1 ;
+static const uint8_t P9N2_MCS_MCFGPA_HOLE0_LOWER_ADDRESS = 2 ;
+static const uint8_t P9N2_MCS_MCFGPA_HOLE0_LOWER_ADDRESS_LEN = 10 ;
+static const uint8_t P9N2_MCS_MCFGPA_HOLE0_UPPER_ADDRESS = 12 ;
+static const uint8_t P9N2_MCS_MCFGPA_HOLE0_UPPER_ADDRESS_LEN = 10 ;
+static const uint8_t P9N2_MCS_MCFGPA_RESERVED_22_27 = 22 ;
+static const uint8_t P9N2_MCS_MCFGPA_RESERVED_22_27_LEN = 6 ;
+static const uint8_t P9N2_MCS_MCFGPA_SMF_VALID = 28 ;
+static const uint8_t P9N2_MCS_MCFGPA_SMF_UPPER_ADDRESS_AT_END_OF_RANGE = 29 ;
+static const uint8_t P9N2_MCS_MCFGPA_SMF_LOWER_ADDRESS = 30 ;
+static const uint8_t P9N2_MCS_MCFGPA_SMF_LOWER_ADDRESS_LEN = 14 ;
+static const uint8_t P9N2_MCS_MCFGPA_SMF_UPPER_ADDRESS = 44 ;
+static const uint8_t P9N2_MCS_MCFGPA_SMF_UPPER_ADDRESS_LEN = 14 ;
+
+static const uint8_t P9N2_MCS_MCFGPM_VALID = 0 ;
+static const uint8_t P9N2_MCS_MCFGPM_RESERVED_1_12 = 1 ;
+static const uint8_t P9N2_MCS_MCFGPM_RESERVED_1_12_LEN = 12 ;
+static const uint8_t P9N2_MCS_MCFGPM_GROUP_SIZE = 13 ;
+static const uint8_t P9N2_MCS_MCFGPM_GROUP_SIZE_LEN = 11 ;
+static const uint8_t P9N2_MCS_MCFGPM_GROUP_BASE_ADDRESS = 24 ;
+static const uint8_t P9N2_MCS_MCFGPM_GROUP_BASE_ADDRESS_LEN = 24 ;
+
+static const uint8_t P9N2_MCS_MCFGPMA_HOLE0_VALID = 0 ;
+static const uint8_t P9N2_MCS_MCFGPMA_HOLE0_UPPER_ADDRESS_AT_END_OF_RANGE = 1 ;
+static const uint8_t P9N2_MCS_MCFGPMA_HOLE0_LOWER_ADDRESS = 2 ;
+static const uint8_t P9N2_MCS_MCFGPMA_HOLE0_LOWER_ADDRESS_LEN = 10 ;
+static const uint8_t P9N2_MCS_MCFGPMA_HOLE0_UPPER_ADDRESS = 12 ;
+static const uint8_t P9N2_MCS_MCFGPMA_HOLE0_UPPER_ADDRESS_LEN = 10 ;
+static const uint8_t P9N2_MCS_MCFGPMA_RESERVED_22_27 = 22 ;
+static const uint8_t P9N2_MCS_MCFGPMA_RESERVED_22_27_LEN = 6 ;
+static const uint8_t P9N2_MCS_MCFGPMA_SMF_VALID = 28 ;
+static const uint8_t P9N2_MCS_MCFGPMA_SMF_UPPER_ADDRESS_AT_END_OF_RANGE = 29 ;
+static const uint8_t P9N2_MCS_MCFGPMA_SMF_LOWER_ADDRESS = 30 ;
+static const uint8_t P9N2_MCS_MCFGPMA_SMF_LOWER_ADDRESS_LEN = 14 ;
+static const uint8_t P9N2_MCS_MCFGPMA_SMF_UPPER_ADDRESS = 44 ;
+static const uint8_t P9N2_MCS_MCFGPMA_SMF_UPPER_ADDRESS_LEN = 14 ;
+
+static const uint8_t P9N2_MCS_MCFIR_MC_INTERNAL_RECOVERABLE_ERROR = 0 ;
+static const uint8_t P9N2_MCS_MCFIR_MC_INTERNAL_NONRECOVERABLE_ERROR = 1 ;
+static const uint8_t P9N2_MCS_MCFIR_POWERBUS_PROTOCOL_ERROR = 2 ;
+static const uint8_t P9N2_MCS_MCFIR_RESERVED_3 = 3 ;
+static const uint8_t P9N2_MCS_MCFIR_MULTIPLE_BAR = 4 ;
+static const uint8_t P9N2_MCS_MCFIR_INVALID_ADDRESS = 5 ;
+static const uint8_t P9N2_MCS_MCFIR_HA_ILLEGAL_CONSUMER_ACCESS = 6 ;
+static const uint8_t P9N2_MCS_MCFIR_HA_ILLEGAL_PRODUCER_ACCESS = 7 ;
+static const uint8_t P9N2_MCS_MCFIR_COMMAND_LIST_TIMEOUT = 8 ;
+static const uint8_t P9N2_MCS_MCFIR_CHANNEL_0_TIMEOUT_ERROR = 9 ;
+static const uint8_t P9N2_MCS_MCFIR_CHANNEL_1_TIMEOUT_ERROR = 10 ;
+static const uint8_t P9N2_MCS_MCFIR_MCS_WAT0 = 11 ;
+static const uint8_t P9N2_MCS_MCFIR_MCS_WAT1 = 12 ;
+static const uint8_t P9N2_MCS_MCFIR_MCS_WAT2 = 13 ;
+static const uint8_t P9N2_MCS_MCFIR_MCS_WAT3 = 14 ;
+static const uint8_t P9N2_MCS_MCFIR_MIRROR_ACTION_OCCURRED = 15 ;
+static const uint8_t P9N2_MCS_MCFIR_CENTAUR_SYNC_COMMAND_OCCURRED = 16 ;
+static const uint8_t P9N2_MCS_MCFIR_MS_WAT_DEBUG_CONFIG_REG_ERROR = 17 ;
+static const uint8_t P9N2_MCS_MCFIR_RESERVED_18 = 18 ;
+static const uint8_t P9N2_MCS_MCFIR_RESERVED_19 = 19 ;
+static const uint8_t P9N2_MCS_MCFIR_RESERVED_20 = 20 ;
+static const uint8_t P9N2_MCS_MCFIR_RESERVED_21 = 21 ;
+static const uint8_t P9N2_MCS_MCFIR_INVALID_SMF_ACCESS = 22 ;
+static const uint8_t P9N2_MCS_MCFIR_RESERVED_23 = 23 ;
+static const uint8_t P9N2_MCS_MCFIR_INTERNAL_SCOM_ERROR = 24 ;
+static const uint8_t P9N2_MCS_MCFIR_INTERNAL_SCOM_ERROR_CLONE = 25 ;
+
+static const uint8_t P9N2_MCS_MCFIRACT0_ACTION_0 = 0 ;
+static const uint8_t P9N2_MCS_MCFIRACT0_ACTION_0_LEN = 26 ;
+
+static const uint8_t P9N2_MCS_MCFIRACT1_ACTION_1 = 0 ;
+static const uint8_t P9N2_MCS_MCFIRACT1_ACTION_1_LEN = 26 ;
+
+static const uint8_t P9N2_MCS_MCFIRMASK_FIR_MASK = 0 ;
+static const uint8_t P9N2_MCS_MCFIRMASK_FIR_MASK_LEN = 26 ;
+
+static const uint8_t P9N2_MCS_MCFIRWOF_WOF = 0 ;
+static const uint8_t P9N2_MCS_MCFIRWOF_WOF_LEN = 26 ;
+
+static const uint8_t P9N2_MCS_MCLFSR_RETRY_LPC_LFSR_SELECT = 0 ;
+static const uint8_t P9N2_MCS_MCLFSR_RETRY_LPC_LFSR_SELECT_LEN = 2 ;
+static const uint8_t P9N2_MCS_MCLFSR_ENABLE_READ_LFSR_DATA = 2 ;
+static const uint8_t P9N2_MCS_MCLFSR_ENABLE_CHANNEL_ARB_DISABLE_HP_OP_LFSR = 3 ;
+static const uint8_t P9N2_MCS_MCLFSR_ENABLE_CHANNEL_ARB_FORCE_WR_HP_LFSR = 4 ;
+static const uint8_t P9N2_MCS_MCLFSR_RESERVED_5_15 = 5 ;
+static const uint8_t P9N2_MCS_MCLFSR_RESERVED_5_15_LEN = 11 ;
+
+static const uint8_t P9N2_MCS_MCMODE0_CENTAUR_MODE = 0 ;
+static const uint8_t P9N2_MCS_MCMODE0_RESERVED_1 = 1 ;
+static const uint8_t P9N2_MCS_MCMODE0_CENTAURP_ENABLE_CP_ME = 2 ;
+static const uint8_t P9N2_MCS_MCMODE0_CENTAURP_ENABLE_NEW_AMO = 3 ;
+static const uint8_t P9N2_MCS_MCMODE0_CENTAURP_INBAND_IS_63 = 4 ;
+static const uint8_t P9N2_MCS_MCMODE0_SYNC_MODE = 5 ;
+static const uint8_t P9N2_MCS_MCMODE0_ASYNC_MODE = 6 ;
+static const uint8_t P9N2_MCS_MCMODE0_CENTAURP_ENABLE_ECRESP = 7 ;
+static const uint8_t P9N2_MCS_MCMODE0_ENABLE_DROP_FP_DYN64_ACTIVE = 8 ;
+static const uint8_t P9N2_MCS_MCMODE0_ENABLE_64_128B_READ = 9 ;
+static const uint8_t P9N2_MCS_MCMODE0_CENTAURP_ENABLE_CENTAURP_CMD = 10 ;
+static const uint8_t P9N2_MCS_MCMODE0_CENTAURP_ENABLE_BYPASS_CMD = 11 ;
+static const uint8_t P9N2_MCS_MCMODE0_CENTAURP_ENABLE_CR_SIDEBAND = 12 ;
+static const uint8_t P9N2_MCS_MCMODE0_CENTAURP_ENABLE_DTAG_CR = 13 ;
+static const uint8_t P9N2_MCS_MCMODE0_EN_CHARB_STALL = 14 ;
+static const uint8_t P9N2_MCS_MCMODE0_SYNC_FENCE = 15 ;
+static const uint8_t P9N2_MCS_MCMODE0_ECRESP_HASH_MODE = 16 ;
+static const uint8_t P9N2_MCS_MCMODE0_FORCE_COMMANDLIST_VALID = 17 ;
+static const uint8_t P9N2_MCS_MCMODE0_FORCE_ANY_BAR_ACTIVE = 18 ;
+static const uint8_t P9N2_MCS_MCMODE0_MCS_RESET_KEEPER = 19 ;
+static const uint8_t P9N2_MCS_MCMODE0_ENABLE_CENTAUR_SYNC = 20 ;
+static const uint8_t P9N2_MCS_MCMODE0_ENABLE_EMERGENCY_THROTTLE = 21 ;
+static const uint8_t P9N2_MCS_MCMODE0_ENABLE_CENTAUR_CHECKSTOP_COMMAND = 22 ;
+static const uint8_t P9N2_MCS_MCMODE0_ENABLE_CENTAUR_TRACESTOP_COMMAND = 23 ;
+static const uint8_t P9N2_MCS_MCMODE0_ENABLE_COMBINED_RESPONSE_PARITY_ERROR = 24 ;
+static const uint8_t P9N2_MCS_MCMODE0_RESERVED_25_26 = 25 ;
+static const uint8_t P9N2_MCS_MCMODE0_RESERVED_25_26_LEN = 2 ;
+static const uint8_t P9N2_MCS_MCMODE0_DISABLE_MC_SYNC = 27 ;
+static const uint8_t P9N2_MCS_MCMODE0_DISABLE_MC_PAIR_SYNC = 28 ;
+static const uint8_t P9N2_MCS_MCMODE0_64B_WR_IS_PWRT = 29 ;
+static const uint8_t P9N2_MCS_MCMODE0_CL_GLOBAL_DISABLE = 30 ;
+static const uint8_t P9N2_MCS_MCMODE0_CL_GLOBAL_DISABLE_LEN = 10 ;
+static const uint8_t P9N2_MCS_MCMODE0_CL_FINE_DISABLE = 40 ;
+static const uint8_t P9N2_MCS_MCMODE0_CL_FINE_DISABLE_LEN = 7 ;
+static const uint8_t P9N2_MCS_MCMODE0_RESERVED_47 = 47 ;
+static const uint8_t P9N2_MCS_MCMODE0_ENABLE_CENTAUR_PERFMON_COMMAND = 48 ;
+static const uint8_t P9N2_MCS_MCMODE0_SCOM_PERFMON_START_COMMAND = 49 ;
+static const uint8_t P9N2_MCS_MCMODE0_SCOM_PERFMON_STOP_COMMAND = 50 ;
+static const uint8_t P9N2_MCS_MCMODE0_DISABLE_PERFMON_RESET_ON_START = 51 ;
+static const uint8_t P9N2_MCS_MCMODE0_GROUP_ADDRESS_INTERLEAVE_GRANULARITY = 52 ;
+static const uint8_t P9N2_MCS_MCMODE0_GROUP_ADDRESS_INTERLEAVE_GRANULARITY_LEN = 4 ;
+static const uint8_t P9N2_MCS_MCMODE0_MPIPL_CANCEL = 56 ;
+static const uint8_t P9N2_MCS_MCMODE0_RESERVED_57_63 = 57 ;
+static const uint8_t P9N2_MCS_MCMODE0_RESERVED_57_63_LEN = 7 ;
+
+static const uint8_t P9N2_MCS_MCMODE1_DISABLE_HIGH_PRIORITY = 0 ;
+static const uint8_t P9N2_MCS_MCMODE1_DISABLE_HIGH_PRIORITY_LEN = 10 ;
+static const uint8_t P9N2_MCS_MCMODE1_DISABLE_FP_M_BIT = 10 ;
+static const uint8_t P9N2_MCS_MCMODE1_DISABLE_CRC_ECC_BYPASS = 11 ;
+static const uint8_t P9N2_MCS_MCMODE1_DISABLE_CRC_ECC_BYPASS_LEN = 6 ;
+static const uint8_t P9N2_MCS_MCMODE1_DISABLE_FP_CRC_ECC_BYPASS = 17 ;
+static const uint8_t P9N2_MCS_MCMODE1_ENABLE_CRC_ECC_BYPASS_NODAL_ONLY = 18 ;
+static const uint8_t P9N2_MCS_MCMODE1_DISABLE_SPEC_SOURCE_SCOPE = 19 ;
+static const uint8_t P9N2_MCS_MCMODE1_DISABLE_SPEC_SOURCE_SCOPE_LEN = 9 ;
+static const uint8_t P9N2_MCS_MCMODE1_DISABLE_CENTAUR_CMD_PREFETCH = 28 ;
+static const uint8_t P9N2_MCS_MCMODE1_DISABLE_CENTAUR_CMD_PREFETCH_LEN = 4 ;
+static const uint8_t P9N2_MCS_MCMODE1_DISABLE_ALL_SPEC_OPS = 32 ;
+static const uint8_t P9N2_MCS_MCMODE1_DISABLE_SPEC_OP = 33 ;
+static const uint8_t P9N2_MCS_MCMODE1_DISABLE_SPEC_OP_LEN = 19 ;
+static const uint8_t P9N2_MCS_MCMODE1_DISABLE_CI = 52 ;
+static const uint8_t P9N2_MCS_MCMODE1_DISABLE_CI_LEN = 2 ;
+static const uint8_t P9N2_MCS_MCMODE1_DISABLE_COMMAND_BYPASS = 54 ;
+static const uint8_t P9N2_MCS_MCMODE1_DISABLE_COMMAND_BYPASS_LEN = 7 ;
+static const uint8_t P9N2_MCS_MCMODE1_DISABLE_FP_COMMAND_BYPASS = 61 ;
+static const uint8_t P9N2_MCS_MCMODE1_DISABLE_BYPASS_IN_READ_DATAFLOW = 62 ;
+static const uint8_t P9N2_MCS_MCMODE1_RESERVED_63 = 63 ;
+
+static const uint8_t P9N2_MCS_MCMODE2_FORCE_SFSTAT_ACTIVE = 0 ;
+static const uint8_t P9N2_MCS_MCMODE2_DISABLE_MDI0 = 1 ;
+static const uint8_t P9N2_MCS_MCMODE2_DISABLE_MDI0_LEN = 13 ;
+static const uint8_t P9N2_MCS_MCMODE2_RESERVED_14 = 14 ;
+static const uint8_t P9N2_MCS_MCMODE2_RESERVED_15 = 15 ;
+static const uint8_t P9N2_MCS_MCMODE2_DISABLE_SHARED_PRESP_ABORT = 16 ;
+static const uint8_t P9N2_MCS_MCMODE2_DISABLE_RETRY_LOST_CLAIM = 17 ;
+static const uint8_t P9N2_MCS_MCMODE2_RESERVED_18 = 18 ;
+static const uint8_t P9N2_MCS_MCMODE2_SMF_MODE_SELECT = 19 ;
+static const uint8_t P9N2_MCS_MCMODE2_SMF_MODE_SELECT_LEN = 2 ;
+static const uint8_t P9N2_MCS_MCMODE2_RESERVED_21_22 = 21 ;
+static const uint8_t P9N2_MCS_MCMODE2_RESERVED_21_22_LEN = 2 ;
+static const uint8_t P9N2_MCS_MCMODE2_ENABLE_OP_HIT_ERROR = 23 ;
+static const uint8_t P9N2_MCS_MCMODE2_COLLISION_MODES = 24 ;
+static const uint8_t P9N2_MCS_MCMODE2_COLLISION_MODES_LEN = 16 ;
+static const uint8_t P9N2_MCS_MCMODE2_EPSILON_LENGTH = 40 ;
+static const uint8_t P9N2_MCS_MCMODE2_EPSILON_LENGTH_LEN = 4 ;
+static const uint8_t P9N2_MCS_MCMODE2_ENABLE_FIR_SPEC_ATTN = 44 ;
+static const uint8_t P9N2_MCS_MCMODE2_ENABLE_FIR_HOST_ATTN = 45 ;
+
+static const uint8_t P9N2_MCS_PORT02_MCP0XLT0_SLOT0_VALID = 0 ;
+static const uint8_t P9N2_MCS_PORT02_MCP0XLT0_SLOT0_D_VALUE = 1 ;
+static const uint8_t P9N2_MCS_PORT02_MCP0XLT0_12GB_ENABLE = 2 ;
+static const uint8_t P9N2_MCS_PORT02_MCP0XLT0_SLOT0_M0_VALID = 5 ;
+static const uint8_t P9N2_MCS_PORT02_MCP0XLT0_SLOT0_M1_VALID = 6 ;
+static const uint8_t P9N2_MCS_PORT02_MCP0XLT0_SLOT0_S0_VALID = 9 ;
+static const uint8_t P9N2_MCS_PORT02_MCP0XLT0_SLOT0_S1_VALID = 10 ;
+static const uint8_t P9N2_MCS_PORT02_MCP0XLT0_SLOT0_S2_VALID = 11 ;
+static const uint8_t P9N2_MCS_PORT02_MCP0XLT0_SLOT0_B2_VALID = 12 ;
+static const uint8_t P9N2_MCS_PORT02_MCP0XLT0_SLOT0_ROW15_VALID = 13 ;
+static const uint8_t P9N2_MCS_PORT02_MCP0XLT0_SLOT0_ROW16_VALID = 14 ;
+static const uint8_t P9N2_MCS_PORT02_MCP0XLT0_SLOT0_ROW17_VALID = 15 ;
+static const uint8_t P9N2_MCS_PORT02_MCP0XLT0_SLOT1_VALID = 16 ;
+static const uint8_t P9N2_MCS_PORT02_MCP0XLT0_SLOT1_D_VALUE = 17 ;
+static const uint8_t P9N2_MCS_PORT02_MCP0XLT0_SLOT1_M0_VALID = 21 ;
+static const uint8_t P9N2_MCS_PORT02_MCP0XLT0_SLOT1_M1_VALID = 22 ;
+static const uint8_t P9N2_MCS_PORT02_MCP0XLT0_SLOT1_S0_VALID = 25 ;
+static const uint8_t P9N2_MCS_PORT02_MCP0XLT0_SLOT1_S1_VALID = 26 ;
+static const uint8_t P9N2_MCS_PORT02_MCP0XLT0_SLOT1_S2_VALID = 27 ;
+static const uint8_t P9N2_MCS_PORT02_MCP0XLT0_SLOT1_B2_VALID = 28 ;
+static const uint8_t P9N2_MCS_PORT02_MCP0XLT0_SLOT1_ROW15_VALID = 29 ;
+static const uint8_t P9N2_MCS_PORT02_MCP0XLT0_SLOT1_ROW16_VALID = 30 ;
+static const uint8_t P9N2_MCS_PORT02_MCP0XLT0_SLOT1_ROW17_VALID = 31 ;
+static const uint8_t P9N2_MCS_PORT02_MCP0XLT0_D_BIT_MAP = 35 ;
+static const uint8_t P9N2_MCS_PORT02_MCP0XLT0_D_BIT_MAP_LEN = 5 ;
+static const uint8_t P9N2_MCS_PORT02_MCP0XLT0_M0_BIT_MAP = 41 ;
+static const uint8_t P9N2_MCS_PORT02_MCP0XLT0_M0_BIT_MAP_LEN = 3 ;
+static const uint8_t P9N2_MCS_PORT02_MCP0XLT0_M1_BIT_MAP = 47 ;
+static const uint8_t P9N2_MCS_PORT02_MCP0XLT0_M1_BIT_MAP_LEN = 5 ;
+static const uint8_t P9N2_MCS_PORT02_MCP0XLT0_R17_BIT_MAP = 53 ;
+static const uint8_t P9N2_MCS_PORT02_MCP0XLT0_R17_BIT_MAP_LEN = 3 ;
+static const uint8_t P9N2_MCS_PORT02_MCP0XLT0_R16_BIT_MAP = 57 ;
+static const uint8_t P9N2_MCS_PORT02_MCP0XLT0_R16_BIT_MAP_LEN = 3 ;
+static const uint8_t P9N2_MCS_PORT02_MCP0XLT0_R15_BIT_MAP = 61 ;
+static const uint8_t P9N2_MCS_PORT02_MCP0XLT0_R15_BIT_MAP_LEN = 3 ;
+
+static const uint8_t P9N2_MCS_PORT13_MCP0XLT0_SLOT0_VALID = 0 ;
+static const uint8_t P9N2_MCS_PORT13_MCP0XLT0_SLOT0_D_VALUE = 1 ;
+static const uint8_t P9N2_MCS_PORT13_MCP0XLT0_12GB_ENABLE = 2 ;
+static const uint8_t P9N2_MCS_PORT13_MCP0XLT0_SLOT0_M0_VALID = 5 ;
+static const uint8_t P9N2_MCS_PORT13_MCP0XLT0_SLOT0_M1_VALID = 6 ;
+static const uint8_t P9N2_MCS_PORT13_MCP0XLT0_SLOT0_S0_VALID = 9 ;
+static const uint8_t P9N2_MCS_PORT13_MCP0XLT0_SLOT0_S1_VALID = 10 ;
+static const uint8_t P9N2_MCS_PORT13_MCP0XLT0_SLOT0_S2_VALID = 11 ;
+static const uint8_t P9N2_MCS_PORT13_MCP0XLT0_SLOT0_B2_VALID = 12 ;
+static const uint8_t P9N2_MCS_PORT13_MCP0XLT0_SLOT0_ROW15_VALID = 13 ;
+static const uint8_t P9N2_MCS_PORT13_MCP0XLT0_SLOT0_ROW16_VALID = 14 ;
+static const uint8_t P9N2_MCS_PORT13_MCP0XLT0_SLOT0_ROW17_VALID = 15 ;
+static const uint8_t P9N2_MCS_PORT13_MCP0XLT0_SLOT1_VALID = 16 ;
+static const uint8_t P9N2_MCS_PORT13_MCP0XLT0_SLOT1_D_VALUE = 17 ;
+static const uint8_t P9N2_MCS_PORT13_MCP0XLT0_SLOT1_M0_VALID = 21 ;
+static const uint8_t P9N2_MCS_PORT13_MCP0XLT0_SLOT1_M1_VALID = 22 ;
+static const uint8_t P9N2_MCS_PORT13_MCP0XLT0_SLOT1_S0_VALID = 25 ;
+static const uint8_t P9N2_MCS_PORT13_MCP0XLT0_SLOT1_S1_VALID = 26 ;
+static const uint8_t P9N2_MCS_PORT13_MCP0XLT0_SLOT1_S2_VALID = 27 ;
+static const uint8_t P9N2_MCS_PORT13_MCP0XLT0_SLOT1_B2_VALID = 28 ;
+static const uint8_t P9N2_MCS_PORT13_MCP0XLT0_SLOT1_ROW15_VALID = 29 ;
+static const uint8_t P9N2_MCS_PORT13_MCP0XLT0_SLOT1_ROW16_VALID = 30 ;
+static const uint8_t P9N2_MCS_PORT13_MCP0XLT0_SLOT1_ROW17_VALID = 31 ;
+static const uint8_t P9N2_MCS_PORT13_MCP0XLT0_D_BIT_MAP = 35 ;
+static const uint8_t P9N2_MCS_PORT13_MCP0XLT0_D_BIT_MAP_LEN = 5 ;
+static const uint8_t P9N2_MCS_PORT13_MCP0XLT0_M0_BIT_MAP = 41 ;
+static const uint8_t P9N2_MCS_PORT13_MCP0XLT0_M0_BIT_MAP_LEN = 3 ;
+static const uint8_t P9N2_MCS_PORT13_MCP0XLT0_M1_BIT_MAP = 47 ;
+static const uint8_t P9N2_MCS_PORT13_MCP0XLT0_M1_BIT_MAP_LEN = 5 ;
+static const uint8_t P9N2_MCS_PORT13_MCP0XLT0_R17_BIT_MAP = 53 ;
+static const uint8_t P9N2_MCS_PORT13_MCP0XLT0_R17_BIT_MAP_LEN = 3 ;
+static const uint8_t P9N2_MCS_PORT13_MCP0XLT0_R16_BIT_MAP = 57 ;
+static const uint8_t P9N2_MCS_PORT13_MCP0XLT0_R16_BIT_MAP_LEN = 3 ;
+static const uint8_t P9N2_MCS_PORT13_MCP0XLT0_R15_BIT_MAP = 61 ;
+static const uint8_t P9N2_MCS_PORT13_MCP0XLT0_R15_BIT_MAP_LEN = 3 ;
+
+static const uint8_t P9N2_MCS_PORT02_MCP0XLT1_S0_BIT_MAP = 3 ;
+static const uint8_t P9N2_MCS_PORT02_MCP0XLT1_S0_BIT_MAP_LEN = 5 ;
+static const uint8_t P9N2_MCS_PORT02_MCP0XLT1_S1_BIT_MAP = 11 ;
+static const uint8_t P9N2_MCS_PORT02_MCP0XLT1_S1_BIT_MAP_LEN = 5 ;
+static const uint8_t P9N2_MCS_PORT02_MCP0XLT1_S2_BIT_MAP = 19 ;
+static const uint8_t P9N2_MCS_PORT02_MCP0XLT1_S2_BIT_MAP_LEN = 5 ;
+static const uint8_t P9N2_MCS_PORT02_MCP0XLT1_COL4_BIT_MAP = 35 ;
+static const uint8_t P9N2_MCS_PORT02_MCP0XLT1_COL4_BIT_MAP_LEN = 5 ;
+static const uint8_t P9N2_MCS_PORT02_MCP0XLT1_COL5_BIT_MAP = 43 ;
+static const uint8_t P9N2_MCS_PORT02_MCP0XLT1_COL5_BIT_MAP_LEN = 5 ;
+static const uint8_t P9N2_MCS_PORT02_MCP0XLT1_COL6_BIT_MAP = 51 ;
+static const uint8_t P9N2_MCS_PORT02_MCP0XLT1_COL6_BIT_MAP_LEN = 5 ;
+static const uint8_t P9N2_MCS_PORT02_MCP0XLT1_COL7_BIT_MAP = 59 ;
+static const uint8_t P9N2_MCS_PORT02_MCP0XLT1_COL7_BIT_MAP_LEN = 5 ;
+
+static const uint8_t P9N2_MCS_PORT13_MCP0XLT1_S0_BIT_MAP = 3 ;
+static const uint8_t P9N2_MCS_PORT13_MCP0XLT1_S0_BIT_MAP_LEN = 5 ;
+static const uint8_t P9N2_MCS_PORT13_MCP0XLT1_S1_BIT_MAP = 11 ;
+static const uint8_t P9N2_MCS_PORT13_MCP0XLT1_S1_BIT_MAP_LEN = 5 ;
+static const uint8_t P9N2_MCS_PORT13_MCP0XLT1_S2_BIT_MAP = 19 ;
+static const uint8_t P9N2_MCS_PORT13_MCP0XLT1_S2_BIT_MAP_LEN = 5 ;
+static const uint8_t P9N2_MCS_PORT13_MCP0XLT1_COL4_BIT_MAP = 35 ;
+static const uint8_t P9N2_MCS_PORT13_MCP0XLT1_COL4_BIT_MAP_LEN = 5 ;
+static const uint8_t P9N2_MCS_PORT13_MCP0XLT1_COL5_BIT_MAP = 43 ;
+static const uint8_t P9N2_MCS_PORT13_MCP0XLT1_COL5_BIT_MAP_LEN = 5 ;
+static const uint8_t P9N2_MCS_PORT13_MCP0XLT1_COL6_BIT_MAP = 51 ;
+static const uint8_t P9N2_MCS_PORT13_MCP0XLT1_COL6_BIT_MAP_LEN = 5 ;
+static const uint8_t P9N2_MCS_PORT13_MCP0XLT1_COL7_BIT_MAP = 59 ;
+static const uint8_t P9N2_MCS_PORT13_MCP0XLT1_COL7_BIT_MAP_LEN = 5 ;
+
+static const uint8_t P9N2_MCS_PORT02_MCP0XLT2_COL8_BIT_MAP = 3 ;
+static const uint8_t P9N2_MCS_PORT02_MCP0XLT2_COL8_BIT_MAP_LEN = 5 ;
+static const uint8_t P9N2_MCS_PORT02_MCP0XLT2_COL9_BIT_MAP = 11 ;
+static const uint8_t P9N2_MCS_PORT02_MCP0XLT2_COL9_BIT_MAP_LEN = 5 ;
+static const uint8_t P9N2_MCS_PORT02_MCP0XLT2_BANK0_BIT_MAP = 19 ;
+static const uint8_t P9N2_MCS_PORT02_MCP0XLT2_BANK0_BIT_MAP_LEN = 5 ;
+static const uint8_t P9N2_MCS_PORT02_MCP0XLT2_BANK1_BIT_MAP = 27 ;
+static const uint8_t P9N2_MCS_PORT02_MCP0XLT2_BANK1_BIT_MAP_LEN = 5 ;
+static const uint8_t P9N2_MCS_PORT02_MCP0XLT2_BANK2_BIT_MAP = 35 ;
+static const uint8_t P9N2_MCS_PORT02_MCP0XLT2_BANK2_BIT_MAP_LEN = 5 ;
+static const uint8_t P9N2_MCS_PORT02_MCP0XLT2_BANK_GROUP0_BIT_MAP = 43 ;
+static const uint8_t P9N2_MCS_PORT02_MCP0XLT2_BANK_GROUP0_BIT_MAP_LEN = 5 ;
+static const uint8_t P9N2_MCS_PORT02_MCP0XLT2_BANK_GROUP1_BIT_MAP = 51 ;
+static const uint8_t P9N2_MCS_PORT02_MCP0XLT2_BANK_GROUP1_BIT_MAP_LEN = 5 ;
+
+static const uint8_t P9N2_MCS_PORT13_MCP0XLT2_COL8_BIT_MAP = 3 ;
+static const uint8_t P9N2_MCS_PORT13_MCP0XLT2_COL8_BIT_MAP_LEN = 5 ;
+static const uint8_t P9N2_MCS_PORT13_MCP0XLT2_COL9_BIT_MAP = 11 ;
+static const uint8_t P9N2_MCS_PORT13_MCP0XLT2_COL9_BIT_MAP_LEN = 5 ;
+static const uint8_t P9N2_MCS_PORT13_MCP0XLT2_BANK0_BIT_MAP = 19 ;
+static const uint8_t P9N2_MCS_PORT13_MCP0XLT2_BANK0_BIT_MAP_LEN = 5 ;
+static const uint8_t P9N2_MCS_PORT13_MCP0XLT2_BANK1_BIT_MAP = 27 ;
+static const uint8_t P9N2_MCS_PORT13_MCP0XLT2_BANK1_BIT_MAP_LEN = 5 ;
+static const uint8_t P9N2_MCS_PORT13_MCP0XLT2_BANK2_BIT_MAP = 35 ;
+static const uint8_t P9N2_MCS_PORT13_MCP0XLT2_BANK2_BIT_MAP_LEN = 5 ;
+static const uint8_t P9N2_MCS_PORT13_MCP0XLT2_BANK_GROUP0_BIT_MAP = 43 ;
+static const uint8_t P9N2_MCS_PORT13_MCP0XLT2_BANK_GROUP0_BIT_MAP_LEN = 5 ;
+static const uint8_t P9N2_MCS_PORT13_MCP0XLT2_BANK_GROUP1_BIT_MAP = 51 ;
+static const uint8_t P9N2_MCS_PORT13_MCP0XLT2_BANK_GROUP1_BIT_MAP_LEN = 5 ;
+
+static const uint8_t P9N2_MCS_PORT02_MCPERF0_ENABLE_DYNAMIC_WR_USAGE = 0 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF0_ENABLE_DYNAMIC_PF_USAGE = 1 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF0_DYNAMIC_WINDOW_SELECT = 2 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF0_DYNAMIC_WINDOW_SELECT_LEN = 2 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF0_NUM_SEC_MIRROR_RSVD = 4 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF0_NUM_SEC_MIRROR_RSVD_LEN = 4 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF0_NUM_HPC_RD_RSVD = 8 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF0_NUM_HPC_RD_RSVD_LEN = 4 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF0_NUM_HA_RSVD = 12 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF0_NUM_HA_RSVD_LEN = 4 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF0_NUM_HTM_RSVD = 16 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF0_NUM_HTM_RSVD_LEN = 6 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF0_AMO_LIMIT = 22 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF0_AMO_LIMIT_LEN = 6 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF0_PREFETCH_LIMIT = 28 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF0_PREFETCH_LIMIT_LEN = 6 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF0_FASTPATH_LIMIT = 34 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF0_FASTPATH_LIMIT_LEN = 6 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF0_WR_RSVD_LOWER_OR_STATIC_LIMIT = 40 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF0_WR_RSVD_LOWER_OR_STATIC_LIMIT_LEN = 6 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF0_WR_RSVD_UPPER_LIMIT = 46 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF0_WR_RSVD_UPPER_LIMIT_LEN = 6 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF0_NUM_CL_ACTIVE = 52 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF0_NUM_CL_ACTIVE_LEN = 6 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF0_NUM_HA_RSVD_SEL = 58 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF0_NUM_HA_RSVD_SEL_LEN = 2 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF0_NUM_HTM_RSVD_SEL = 60 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF0_NUM_HTM_RSVD_SEL_LEN = 2 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF0_NUM_SEC_MIRROR_RSVD_SEL = 62 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF0_NUM_SEC_MIRROR_RSVD_SEL_LEN = 2 ;
+
+static const uint8_t P9N2_MCS_PORT13_MCPERF0_ENABLE_DYNAMIC_WR_USAGE = 0 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF0_ENABLE_DYNAMIC_PF_USAGE = 1 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF0_DYNAMIC_WINDOW_SELECT = 2 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF0_DYNAMIC_WINDOW_SELECT_LEN = 2 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF0_NUM_SEC_MIRROR_RSVD = 4 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF0_NUM_SEC_MIRROR_RSVD_LEN = 4 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF0_NUM_HPC_RD_RSVD = 8 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF0_NUM_HPC_RD_RSVD_LEN = 4 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF0_NUM_HA_RSVD = 12 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF0_NUM_HA_RSVD_LEN = 4 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF0_NUM_HTM_RSVD = 16 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF0_NUM_HTM_RSVD_LEN = 6 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF0_AMO_LIMIT = 22 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF0_AMO_LIMIT_LEN = 6 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF0_PREFETCH_LIMIT = 28 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF0_PREFETCH_LIMIT_LEN = 6 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF0_FASTPATH_LIMIT = 34 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF0_FASTPATH_LIMIT_LEN = 6 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF0_WR_RSVD_LOWER_OR_STATIC_LIMIT = 40 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF0_WR_RSVD_LOWER_OR_STATIC_LIMIT_LEN = 6 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF0_WR_RSVD_UPPER_LIMIT = 46 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF0_WR_RSVD_UPPER_LIMIT_LEN = 6 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF0_NUM_CL_ACTIVE = 52 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF0_NUM_CL_ACTIVE_LEN = 6 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF0_NUM_HA_RSVD_SEL = 58 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF0_NUM_HA_RSVD_SEL_LEN = 2 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF0_NUM_HTM_RSVD_SEL = 60 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF0_NUM_HTM_RSVD_SEL_LEN = 2 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF0_NUM_SEC_MIRROR_RSVD_SEL = 62 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF0_NUM_SEC_MIRROR_RSVD_SEL_LEN = 2 ;
+
+static const uint8_t P9N2_MCS_MCPERF1_DISABLE_FASTPATH = 0 ;
+static const uint8_t P9N2_MCS_MCPERF1_RESERVED_1_2 = 1 ;
+static const uint8_t P9N2_MCS_MCPERF1_RESERVED_1_2_LEN = 2 ;
+static const uint8_t P9N2_MCS_MCPERF1_ENABLE_DISABLE_SPEC_READ_FOR_NONDMA_GROUP_PUMP_LOCAL_READ = 3 ;
+static const uint8_t P9N2_MCS_MCPERF1_ENABLE_DISABLE_SPEC_READ_FOR_NONDMA_SYSTEM_PUMP_LOCAL_READ = 4 ;
+static const uint8_t P9N2_MCS_MCPERF1_DISABLE_FASTPATH_QOS = 5 ;
+static const uint8_t P9N2_MCS_MCPERF1_DISABLE_CHARB_BYPASS = 6 ;
+static const uint8_t P9N2_MCS_MCPERF1_DISABLE_SPEC_DISABLE_HINT_BIT = 7 ;
+static const uint8_t P9N2_MCS_MCPERF1_DISABLE_2K_SPEC_FILTER = 8 ;
+static const uint8_t P9N2_MCS_MCPERF1_DISABLE_RESET_2K_COUNT_IF_HINT_BIT_SET = 9 ;
+static const uint8_t P9N2_MCS_MCPERF1_D2K_SPEC_FILTER_COUNTER_LFSR_INC_SELECT = 10 ;
+static const uint8_t P9N2_MCS_MCPERF1_D2K_SPEC_FILTER_COUNTER_LFSR_INC_SELECT_LEN = 4 ;
+static const uint8_t P9N2_MCS_MCPERF1_D2K_SPEC_FILTER_COUNTER_LFSR_DEC_SELECT = 14 ;
+static const uint8_t P9N2_MCS_MCPERF1_D2K_SPEC_FILTER_COUNTER_LFSR_DEC_SELECT_LEN = 4 ;
+static const uint8_t P9N2_MCS_MCPERF1_SPEC_READ_FILTER_NO_HASH_MODE = 18 ;
+static const uint8_t P9N2_MCS_MCPERF1_RESERVED_19_31 = 19 ;
+static const uint8_t P9N2_MCS_MCPERF1_RESERVED_19_31_LEN = 13 ;
+static const uint8_t P9N2_MCS_MCPERF1_PF_DROP_CNT_THRESH = 32 ;
+static const uint8_t P9N2_MCS_MCPERF1_PF_DROP_CNT_THRESH_LEN = 7 ;
+static const uint8_t P9N2_MCS_MCPERF1_CP_RETRY_THRESH = 39 ;
+static const uint8_t P9N2_MCS_MCPERF1_CP_RETRY_THRESH_LEN = 7 ;
+static const uint8_t P9N2_MCS_MCPERF1_MERGE_CAPACITY_LIMIT = 46 ;
+static const uint8_t P9N2_MCS_MCPERF1_MERGE_CAPACITY_LIMIT_LEN = 4 ;
+static const uint8_t P9N2_MCS_MCPERF1_RRQ_CAPACITY_LIMIT = 50 ;
+static const uint8_t P9N2_MCS_MCPERF1_RRQ_CAPACITY_LIMIT_LEN = 5 ;
+static const uint8_t P9N2_MCS_MCPERF1_WRQ_CAPACITY_LIMIT = 55 ;
+static const uint8_t P9N2_MCS_MCPERF1_WRQ_CAPACITY_LIMIT_LEN = 6 ;
+static const uint8_t P9N2_MCS_MCPERF1_ENABLE_PF_DROP_CMDLIST = 61 ;
+static const uint8_t P9N2_MCS_MCPERF1_ENABLE_PF_DROP_SRQ = 62 ;
+static const uint8_t P9N2_MCS_MCPERF1_ENABLE_PREFETCH_PROMOTE = 63 ;
+
+static const uint8_t P9N2_MCS_PORT02_MCPERF2_PF_DROP_VALUE0 = 0 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF2_PF_DROP_VALUE0_LEN = 3 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF2_PF_DROP_VALUE1 = 3 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF2_PF_DROP_VALUE1_LEN = 3 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF2_PF_DROP_VALUE2 = 6 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF2_PF_DROP_VALUE2_LEN = 3 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF2_PF_DROP_VALUE3 = 9 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF2_PF_DROP_VALUE3_LEN = 3 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF2_DISABLE_DROPABLE = 12 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF2_REFRESH_BLOCK_CONFIG = 13 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF2_REFRESH_BLOCK_CONFIG_LEN = 3 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF2_ENABLE_REFRESH_BLOCK_SQ = 16 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF2_ENABLE_REFRESH_BLOCK_NSQ = 17 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF2_ENABLE_REFRESH_BLOCK_DISP = 18 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF2_PERF_THRESH = 19 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF2_PERF_THRESH_LEN = 5 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF2_NSQ_LFSR_CNTL = 24 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF2_NSQ_LFSR_CNTL_LEN = 4 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF2_SQ_LFSR_CNTL = 28 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF2_SQ_LFSR_CNTL_LEN = 4 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF2_EN_CHARB_CMD_STALL = 32 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF2_EN_CHARB_RRQ_STALL = 33 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF2_EN_CHARB_WRQ_STALL = 34 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF2_EN_CHARB_MERGE_STALL = 35 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF2_EN_64_128_PB_READ = 36 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF2_RCTRL_CONFIG = 37 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF2_RCTRL_CONFIG_LEN = 3 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF2_ALT_M = 40 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF2_ALT_M_LEN = 4 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF2_NUM_CLEAN = 44 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF2_NUM_CLEAN_LEN = 6 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF2_NUM_RMW_BUF = 50 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF2_NUM_RMW_BUF_LEN = 5 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF2_RMW_BUF_THRESH = 55 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF2_RMW_BUF_THRESH_LEN = 5 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF2_EN_ALT_ECR_NO_ERR = 60 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF2_EN_ALT_ECR_ERR = 61 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF2_EN_ALT_CR = 62 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF2_LOAD_RSVD_VALUES = 63 ;
+
+static const uint8_t P9N2_MCS_PORT13_MCPERF2_PF_DROP_VALUE0 = 0 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF2_PF_DROP_VALUE0_LEN = 3 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF2_PF_DROP_VALUE1 = 3 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF2_PF_DROP_VALUE1_LEN = 3 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF2_PF_DROP_VALUE2 = 6 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF2_PF_DROP_VALUE2_LEN = 3 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF2_PF_DROP_VALUE3 = 9 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF2_PF_DROP_VALUE3_LEN = 3 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF2_DISABLE_DROPABLE = 12 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF2_REFRESH_BLOCK_CONFIG = 13 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF2_REFRESH_BLOCK_CONFIG_LEN = 3 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF2_ENABLE_REFRESH_BLOCK_SQ = 16 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF2_ENABLE_REFRESH_BLOCK_NSQ = 17 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF2_ENABLE_REFRESH_BLOCK_DISP = 18 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF2_PERF_THRESH = 19 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF2_PERF_THRESH_LEN = 5 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF2_NSQ_LFSR_CNTL = 24 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF2_NSQ_LFSR_CNTL_LEN = 4 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF2_SQ_LFSR_CNTL = 28 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF2_SQ_LFSR_CNTL_LEN = 4 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF2_EN_CHARB_CMD_STALL = 32 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF2_EN_CHARB_RRQ_STALL = 33 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF2_EN_CHARB_WRQ_STALL = 34 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF2_EN_CHARB_MERGE_STALL = 35 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF2_EN_64_128_PB_READ = 36 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF2_RCTRL_CONFIG = 37 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF2_RCTRL_CONFIG_LEN = 3 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF2_ALT_M = 40 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF2_ALT_M_LEN = 4 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF2_NUM_CLEAN = 44 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF2_NUM_CLEAN_LEN = 6 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF2_NUM_RMW_BUF = 50 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF2_NUM_RMW_BUF_LEN = 5 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF2_RMW_BUF_THRESH = 55 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF2_RMW_BUF_THRESH_LEN = 5 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF2_EN_ALT_ECR_NO_ERR = 60 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF2_EN_ALT_ECR_ERR = 61 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF2_EN_ALT_CR = 62 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF2_LOAD_RSVD_VALUES = 63 ;
+
+static const uint8_t P9N2_MCS_PORT02_MCPERF3_EN_DROP_PLS_F_FULL = 0 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF3_DIS_DROPABLE_HP = 1 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF3_EN_PF_CONF_RETRY = 2 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF3_DROP_PLS_DIV00 = 3 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF3_DROP_PLS_DIV00_LEN = 3 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF3_DROP_PLS_DIV01 = 6 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF3_DROP_PLS_DIV01_LEN = 3 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF3_DROP_PLS_DIV10 = 9 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF3_DROP_PLS_DIV10_LEN = 3 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF3_DROP_PLS_DIV11 = 12 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF3_DROP_PLS_DIV11_LEN = 3 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF3_PF_CONF_RETRY_THRESH0 = 15 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF3_PF_CONF_RETRY_THRESH0_LEN = 4 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF3_PF_CONF_RETRY_THRESH1 = 19 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF3_PF_CONF_RETRY_THRESH1_LEN = 4 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF3_PF_CONF_RETRY_THRESH2 = 23 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF3_PF_CONF_RETRY_THRESH2_LEN = 4 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF3_PF_CONF_RETRY_THRESH3 = 27 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF3_PF_CONF_RETRY_THRESH3_LEN = 4 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF3_ENABLE_CL0 = 31 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF3_EN_NS_RD_DYN_64B = 32 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF3_EN_NS_RD_DYN_INV = 33 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF3_PF_DROP_IF_CNT = 34 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF3_PF_DROP_IF_CNT_LEN = 3 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF3_HP_PF_EQ_LP_RD = 37 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF3_LP_PF_EQ_LP_RD = 38 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF3_ENABLE_CRESP_STALL = 39 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF3_ENABLE_RMW_BUF_DEALLOC_STALL = 40 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF3_ENABLE_AMO_MSI_RMW_ONLY = 41 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF3_DISABLE_READ_HIT_AMO_WINDOW = 42 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF3_ENABLE_CP_M_MDI0_LOCAL_ONLY = 43 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF3_DISABLE_WRTO_IG = 44 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF3_AMO_LIMIT_SEL = 45 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF3_RESERVED_46_47 = 46 ;
+static const uint8_t P9N2_MCS_PORT02_MCPERF3_RESERVED_46_47_LEN = 2 ;
+
+static const uint8_t P9N2_MCS_PORT13_MCPERF3_EN_DROP_PLS_F_FULL = 0 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF3_DIS_DROPABLE_HP = 1 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF3_EN_PF_CONF_RETRY = 2 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF3_DROP_PLS_DIV00 = 3 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF3_DROP_PLS_DIV00_LEN = 3 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF3_DROP_PLS_DIV01 = 6 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF3_DROP_PLS_DIV01_LEN = 3 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF3_DROP_PLS_DIV10 = 9 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF3_DROP_PLS_DIV10_LEN = 3 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF3_DROP_PLS_DIV11 = 12 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF3_DROP_PLS_DIV11_LEN = 3 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF3_PF_CONF_RETRY_THRESH0 = 15 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF3_PF_CONF_RETRY_THRESH0_LEN = 4 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF3_PF_CONF_RETRY_THRESH1 = 19 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF3_PF_CONF_RETRY_THRESH1_LEN = 4 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF3_PF_CONF_RETRY_THRESH2 = 23 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF3_PF_CONF_RETRY_THRESH2_LEN = 4 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF3_PF_CONF_RETRY_THRESH3 = 27 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF3_PF_CONF_RETRY_THRESH3_LEN = 4 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF3_ENABLE_CL0 = 31 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF3_EN_NS_RD_DYN_64B = 32 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF3_EN_NS_RD_DYN_INV = 33 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF3_PF_DROP_IF_CNT = 34 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF3_PF_DROP_IF_CNT_LEN = 3 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF3_HP_PF_EQ_LP_RD = 37 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF3_LP_PF_EQ_LP_RD = 38 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF3_ENABLE_CRESP_STALL = 39 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF3_ENABLE_RMW_BUF_DEALLOC_STALL = 40 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF3_ENABLE_AMO_MSI_RMW_ONLY = 41 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF3_DISABLE_READ_HIT_AMO_WINDOW = 42 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF3_ENABLE_CP_M_MDI0_LOCAL_ONLY = 43 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF3_DISABLE_WRTO_IG = 44 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF3_AMO_LIMIT_SEL = 45 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF3_RESERVED_46_47 = 46 ;
+static const uint8_t P9N2_MCS_PORT13_MCPERF3_RESERVED_46_47_LEN = 2 ;
+
+static const uint8_t P9N2_MCS_MCSYNC_CHANNEL_SELECT = 0 ;
+static const uint8_t P9N2_MCS_MCSYNC_CHANNEL_SELECT_LEN = 8 ;
+static const uint8_t P9N2_MCS_MCSYNC_SYNC_TYPE = 8 ;
+static const uint8_t P9N2_MCS_MCSYNC_SYNC_TYPE_LEN = 8 ;
+static const uint8_t P9N2_MCS_MCSYNC_SYNC_GO = 16 ;
+static const uint8_t P9N2_MCS_MCSYNC_SYNC_RESERVED = 17 ;
+static const uint8_t P9N2_MCS_MCSYNC_SYNC_RESERVED_LEN = 11 ;
+
+static const uint8_t P9N2_MCS_MCTEST_INJECT_MODE_SELECT = 0 ;
+static const uint8_t P9N2_MCS_MCTEST_RESERVED_1 = 1 ;
+static const uint8_t P9N2_MCS_MCTEST_CONTINUOUS_LEVEL_INJECT_ENABLE = 2 ;
+static const uint8_t P9N2_MCS_MCTEST_RESERVED_3 = 3 ;
+static const uint8_t P9N2_MCS_MCTEST_EVENT_0_WAT_DISABLE_ALL_SPECULATION = 4 ;
+static const uint8_t P9N2_MCS_MCTEST_EVENT_1_WAT_DISABLE_ALL_SPECULATION = 5 ;
+static const uint8_t P9N2_MCS_MCTEST_EVENT_2_WAT_DISABLE_ALL_SPECULATION = 6 ;
+static const uint8_t P9N2_MCS_MCTEST_EVENT_3_WAT_DISABLE_ALL_SPECULATION = 7 ;
+static const uint8_t P9N2_MCS_MCTEST_EVENT_0_WAT_DISABLE_READ_BYPASS = 8 ;
+static const uint8_t P9N2_MCS_MCTEST_EVENT_1_WAT_DISABLE_READ_BYPASS = 9 ;
+static const uint8_t P9N2_MCS_MCTEST_EVENT_2_WAT_DISABLE_READ_BYPASS = 10 ;
+static const uint8_t P9N2_MCS_MCTEST_EVENT_3_WAT_DISABLE_READ_BYPASS = 11 ;
+static const uint8_t P9N2_MCS_MCTEST_EVENT_0_WAT_DISABLE_PREFETCH = 12 ;
+static const uint8_t P9N2_MCS_MCTEST_EVENT_1_WAT_DISABLE_PREFETCH = 13 ;
+static const uint8_t P9N2_MCS_MCTEST_EVENT_2_WAT_DISABLE_PREFETCH = 14 ;
+static const uint8_t P9N2_MCS_MCTEST_EVENT_3_WAT_DISABLE_PREFETCH = 15 ;
+static const uint8_t P9N2_MCS_MCTEST_EVENT_0_WAT_DISABLE_FASTPATH = 16 ;
+static const uint8_t P9N2_MCS_MCTEST_EVENT_1_WAT_DISABLE_FASTPATH = 17 ;
+static const uint8_t P9N2_MCS_MCTEST_EVENT_2_WAT_DISABLE_FASTPATH = 18 ;
+static const uint8_t P9N2_MCS_MCTEST_EVENT_3_WAT_DISABLE_FASTPATH = 19 ;
+static const uint8_t P9N2_MCS_MCTEST_EVENT_0_WAT_FORCE_SFSTAT = 20 ;
+static const uint8_t P9N2_MCS_MCTEST_EVENT_1_WAT_FORCE_SFSTAT = 21 ;
+static const uint8_t P9N2_MCS_MCTEST_EVENT_2_WAT_FORCE_SFSTAT = 22 ;
+static const uint8_t P9N2_MCS_MCTEST_EVENT_3_WAT_FORCE_SFSTAT = 23 ;
+static const uint8_t P9N2_MCS_MCTEST_EVENT_0_WAT_FORCE_MDI1 = 24 ;
+static const uint8_t P9N2_MCS_MCTEST_EVENT_1_WAT_FORCE_MDI1 = 25 ;
+static const uint8_t P9N2_MCS_MCTEST_EVENT_2_WAT_FORCE_MDI1 = 26 ;
+static const uint8_t P9N2_MCS_MCTEST_EVENT_3_WAT_FORCE_MDI1 = 27 ;
+static const uint8_t P9N2_MCS_MCTEST_RESERVED_28_31 = 28 ;
+static const uint8_t P9N2_MCS_MCTEST_RESERVED_28_31_LEN = 4 ;
+static const uint8_t P9N2_MCS_MCTEST_CONFIGURE_RCTRL_WAT_SELECT = 32 ;
+static const uint8_t P9N2_MCS_MCTEST_CONFIGURE_RCTRL_WAT_SELECT_LEN = 4 ;
+static const uint8_t P9N2_MCS_MCTEST_RESERVED_36_47 = 36 ;
+static const uint8_t P9N2_MCS_MCTEST_RESERVED_36_47_LEN = 12 ;
+
+static const uint8_t P9N2_MCS_MCTO_SELECT_PB_HANG_PULSE = 0 ;
+static const uint8_t P9N2_MCS_MCTO_SELECT_LOCAL_HANG_PULSE = 1 ;
+static const uint8_t P9N2_MCS_MCTO_RPT_HANG_SELECT = 2 ;
+static const uint8_t P9N2_MCS_MCTO_RPT_HANG_SELECT_LEN = 2 ;
+static const uint8_t P9N2_MCS_MCTO_RESERVED_4 = 4 ;
+static const uint8_t P9N2_MCS_MCTO_CL_TIMEOUT_VALUE = 5 ;
+static const uint8_t P9N2_MCS_MCTO_CL_TIMEOUT_VALUE_LEN = 3 ;
+static const uint8_t P9N2_MCS_MCTO_LOCAL_HANG_COMP = 8 ;
+static const uint8_t P9N2_MCS_MCTO_LOCAL_HANG_COMP_LEN = 16 ;
+static const uint8_t P9N2_MCS_MCTO_HANG_COMP = 24 ;
+static const uint8_t P9N2_MCS_MCTO_HANG_COMP_LEN = 8 ;
+static const uint8_t P9N2_MCS_MCTO_ENABLE_NONMIRROR_HANG = 32 ;
+static const uint8_t P9N2_MCS_MCTO_ENABLE_MIRROR_HANG = 33 ;
+static const uint8_t P9N2_MCS_MCTO_ENABLE_APO_HANG = 34 ;
+static const uint8_t P9N2_MCS_MCTO_ENABLE_CLIB_HANG = 35 ;
+
+static const uint8_t P9N2_MCS_PORT02_MCWAT_WAT_STALL_ACTION = 0 ;
+static const uint8_t P9N2_MCS_PORT02_MCWAT_WAT_STALL_ACTION_LEN = 4 ;
+static const uint8_t P9N2_MCS_PORT02_MCWAT_CL_WRAP_DEBUG_OR = 4 ;
+static const uint8_t P9N2_MCS_PORT02_MCWAT_CLSTATE_DEBUG_SEL = 5 ;
+static const uint8_t P9N2_MCS_PORT02_MCWAT_CLSTATE_DEBUG_SEL_LEN = 3 ;
+static const uint8_t P9N2_MCS_PORT02_MCWAT_RESERVED8_9 = 8 ;
+static const uint8_t P9N2_MCS_PORT02_MCWAT_RESERVED8_9_LEN = 2 ;
+static const uint8_t P9N2_MCS_PORT02_MCWAT_DISP_DEBUG_SEL = 10 ;
+static const uint8_t P9N2_MCS_PORT02_MCWAT_DISP_DEBUG_SEL_LEN = 2 ;
+static const uint8_t P9N2_MCS_PORT02_MCWAT_CL_WRAP_DEBUG_SEL = 12 ;
+static const uint8_t P9N2_MCS_PORT02_MCWAT_CL_WRAP_DEBUG_SEL_LEN = 5 ;
+static const uint8_t P9N2_MCS_PORT02_MCWAT_WAT_ACTION_SEL = 17 ;
+static const uint8_t P9N2_MCS_PORT02_MCWAT_WAT_ACTION_SEL_LEN = 5 ;
+static const uint8_t P9N2_MCS_PORT02_MCWAT_RESERVED22_31 = 22 ;
+static const uint8_t P9N2_MCS_PORT02_MCWAT_RESERVED22_31_LEN = 10 ;
+
+static const uint8_t P9N2_MCS_PORT13_MCWAT_WAT_STALL_ACTION = 0 ;
+static const uint8_t P9N2_MCS_PORT13_MCWAT_WAT_STALL_ACTION_LEN = 4 ;
+static const uint8_t P9N2_MCS_PORT13_MCWAT_CL_WRAP_DEBUG_OR = 4 ;
+static const uint8_t P9N2_MCS_PORT13_MCWAT_CLSTATE_DEBUG_SEL = 5 ;
+static const uint8_t P9N2_MCS_PORT13_MCWAT_CLSTATE_DEBUG_SEL_LEN = 3 ;
+static const uint8_t P9N2_MCS_PORT13_MCWAT_RESERVED8_9 = 8 ;
+static const uint8_t P9N2_MCS_PORT13_MCWAT_RESERVED8_9_LEN = 2 ;
+static const uint8_t P9N2_MCS_PORT13_MCWAT_DISP_DEBUG_SEL = 10 ;
+static const uint8_t P9N2_MCS_PORT13_MCWAT_DISP_DEBUG_SEL_LEN = 2 ;
+static const uint8_t P9N2_MCS_PORT13_MCWAT_CL_WRAP_DEBUG_SEL = 12 ;
+static const uint8_t P9N2_MCS_PORT13_MCWAT_CL_WRAP_DEBUG_SEL_LEN = 5 ;
+static const uint8_t P9N2_MCS_PORT13_MCWAT_WAT_ACTION_SEL = 17 ;
+static const uint8_t P9N2_MCS_PORT13_MCWAT_WAT_ACTION_SEL_LEN = 5 ;
+static const uint8_t P9N2_MCS_PORT13_MCWAT_RESERVED22_31 = 22 ;
+static const uint8_t P9N2_MCS_PORT13_MCWAT_RESERVED22_31_LEN = 10 ;
+
+static const uint8_t P9N2_MCS_MCWATCNTL_ENABLE_WAT = 0 ;
+static const uint8_t P9N2_MCS_MCWATCNTL_SET_WAT_EXTERNAL_ARM = 1 ;
+static const uint8_t P9N2_MCS_MCWATCNTL_SET_WAT_EXTERNAL_RESET = 2 ;
+static const uint8_t P9N2_MCS_MCWATCNTL_SET_WAT_EXTERNAL_TRIGGER = 3 ;
+static const uint8_t P9N2_MCS_MCWATCNTL_MCWATDATAX_SELECT = 4 ;
+static const uint8_t P9N2_MCS_MCWATCNTL_MCWATDATAX_SELECT_LEN = 4 ;
+static const uint8_t P9N2_MCS_MCWATCNTL_WAT_EVENT_SELECT = 8 ;
+static const uint8_t P9N2_MCS_MCWATCNTL_WAT_EVENT_SELECT_LEN = 2 ;
+static const uint8_t P9N2_MCS_MCWATCNTL_WAT_EXTERNAL_SELECT = 10 ;
+static const uint8_t P9N2_MCS_MCWATCNTL_WAT_EXTERNAL_SELECT_LEN = 2 ;
+static const uint8_t P9N2_MCS_MCWATCNTL_WAT_LOCAL_EVENT_SELECT = 12 ;
+static const uint8_t P9N2_MCS_MCWATCNTL_WAT_LOCAL_EVENT_SELECT_LEN = 2 ;
+static const uint8_t P9N2_MCS_MCWATCNTL_WAT_EXTERNAL_EVENT_TO_INTERNAL = 14 ;
+static const uint8_t P9N2_MCS_MCWATCNTL_WAT_EXTERNAL_EVENT_TO_INTERNAL_LEN = 2 ;
+static const uint8_t P9N2_MCS_MCWATCNTL_WAT_GLOBAL_EVENT_0_SELECT = 16 ;
+static const uint8_t P9N2_MCS_MCWATCNTL_WAT_GLOBAL_EVENT_0_SELECT_LEN = 3 ;
+static const uint8_t P9N2_MCS_MCWATCNTL_WAT_GLOBAL_EVENT_1_SELECT = 19 ;
+static const uint8_t P9N2_MCS_MCWATCNTL_WAT_GLOBAL_EVENT_1_SELECT_LEN = 3 ;
+static const uint8_t P9N2_MCS_MCWATCNTL_WAT_GLOBAL_EVENT_2_SELECT = 22 ;
+static const uint8_t P9N2_MCS_MCWATCNTL_WAT_GLOBAL_EVENT_2_SELECT_LEN = 3 ;
+static const uint8_t P9N2_MCS_MCWATCNTL_WAT_GLOBAL_EVENT_3_SELECT = 25 ;
+static const uint8_t P9N2_MCS_MCWATCNTL_WAT_GLOBAL_EVENT_3_SELECT_LEN = 3 ;
+static const uint8_t P9N2_MCS_MCWATCNTL_RESERVED_28_31 = 28 ;
+static const uint8_t P9N2_MCS_MCWATCNTL_RESERVED_28_31_LEN = 4 ;
+static const uint8_t P9N2_MCS_MCWATCNTL_PBI_DEBUG_SELECT = 32 ;
+static const uint8_t P9N2_MCS_MCWATCNTL_PBI_DEBUG_SELECT_LEN = 4 ;
+static const uint8_t P9N2_MCS_MCWATCNTL_RCTRL_DEBUG_SELECT = 36 ;
+static const uint8_t P9N2_MCS_MCWATCNTL_RCTRL_DEBUG_SELECT_LEN = 4 ;
+static const uint8_t P9N2_MCS_MCWATCNTL_DBG_COUNT_DEBUG_SELECT = 40 ;
+static const uint8_t P9N2_MCS_MCWATCNTL_DBG_COUNT_DEBUG_SELECT_LEN = 7 ;
+static const uint8_t P9N2_MCS_MCWATCNTL_DBG_COUNT_EVENT_BUS_SELECT = 47 ;
+static const uint8_t P9N2_MCS_MCWATCNTL_DBG_COUNT_EVENT_BUS_SELECT_LEN = 5 ;
+static const uint8_t P9N2_MCS_MCWATCNTL_DBG_COUNT_SELECT = 52 ;
+static const uint8_t P9N2_MCS_MCWATCNTL_DBG_COUNT_SELECT_LEN = 4 ;
+static const uint8_t P9N2_MCS_MCWATCNTL_RESERVED_56_59 = 56 ;
+static const uint8_t P9N2_MCS_MCWATCNTL_RESERVED_56_59_LEN = 4 ;
+static const uint8_t P9N2_MCS_MCWATCNTL_DBG_COUNT_ENABLE = 60 ;
+static const uint8_t P9N2_MCS_MCWATCNTL_DBG_COUNT_RESET = 61 ;
+static const uint8_t P9N2_MCS_MCWATCNTL_AND_22BIT_WAT_OUTPUTS = 62 ;
+static const uint8_t P9N2_MCS_MCWATCNTL_RESERVED_63 = 63 ;
+
+static const uint8_t P9N2_MCS_MCWATDATA_MCWATDATA0 = 0 ;
+static const uint8_t P9N2_MCS_MCWATDATA_MCWATDATA0_LEN = 40 ;
+
+static const uint8_t P9N2_MCA_MSR_CHIPMARK = 8 ;
+static const uint8_t P9N2_MCA_MSR_CHIPMARK_LEN = 8 ;
+static const uint8_t P9N2_MCA_MSR_RANK = 16 ;
+static const uint8_t P9N2_MCA_MSR_RANK_LEN = 3 ;
+
+static const uint8_t P9N2_MCA_PSCOM_ERROR_MASK_PCB_WDATA_PARITY = 0 ;
+static const uint8_t P9N2_MCA_PSCOM_ERROR_MASK_PCB_ADDRESS_PARITY = 1 ;
+static const uint8_t P9N2_MCA_PSCOM_ERROR_MASK_DL_RETURN_WDATA_PARITY = 2 ;
+static const uint8_t P9N2_MCA_PSCOM_ERROR_MASK_DL_RETURN_P0 = 3 ;
+static const uint8_t P9N2_MCA_PSCOM_ERROR_MASK_UL_RDATA_PARITY = 4 ;
+static const uint8_t P9N2_MCA_PSCOM_ERROR_MASK_UL_P0 = 5 ;
+static const uint8_t P9N2_MCA_PSCOM_ERROR_MASK_PARITY_ON_INTERFACE_MACHINE = 6 ;
+static const uint8_t P9N2_MCA_PSCOM_ERROR_MASK_PARITY_ON_P2S_MACHINE = 7 ;
+static const uint8_t P9N2_MCA_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 8 ;
+static const uint8_t P9N2_MCA_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 9 ;
+static const uint8_t P9N2_MCA_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 10 ;
+static const uint8_t P9N2_MCA_PSCOM_ERROR_MASK_PARALLEL_WRITE_NVLD = 11 ;
+static const uint8_t P9N2_MCA_PSCOM_ERROR_MASK_PARALLEL_READ_NVLD = 12 ;
+static const uint8_t P9N2_MCA_PSCOM_ERROR_MASK_PARALLEL_ADDR_INVALID = 13 ;
+static const uint8_t P9N2_MCA_PSCOM_ERROR_MASK_PCB_COMMAND_PARITY = 14 ;
+static const uint8_t P9N2_MCA_PSCOM_ERROR_MASK_GENERAL_TIMEOUT = 15 ;
+static const uint8_t P9N2_MCA_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 16 ;
+static const uint8_t P9N2_MCA_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 17 ;
+
+static const uint8_t P9N2_MCA_PSCOM_MODE_REG_ABORT_ON_PCB_ADDR_PARITY_ERROR = 0 ;
+static const uint8_t P9N2_MCA_PSCOM_MODE_REG_ABORT_ON_PCB_WDATA_PARITY_ERROR = 1 ;
+static const uint8_t P9N2_MCA_PSCOM_MODE_REG_UNUSED_BIT_2 = 2 ;
+static const uint8_t P9N2_MCA_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR = 3 ;
+static const uint8_t P9N2_MCA_PSCOM_MODE_REG_WATCHDOG_ENABLE = 4 ;
+static const uint8_t P9N2_MCA_PSCOM_MODE_REG_SCOM_HANG_LIMIT = 5 ;
+static const uint8_t P9N2_MCA_PSCOM_MODE_REG_SCOM_HANG_LIMIT_LEN = 2 ;
+static const uint8_t P9N2_MCA_PSCOM_MODE_REG_FORCE_ALL_RINGS = 7 ;
+static const uint8_t P9N2_MCA_PSCOM_MODE_REG_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE = 8 ;
+static const uint8_t P9N2_MCA_PSCOM_MODE_REG_RESERVED_LT = 9 ;
+static const uint8_t P9N2_MCA_PSCOM_MODE_REG_RESERVED_LT_LEN = 3 ;
+
+static const uint8_t P9N2_MCA_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_WDATA_PARITY = 0 ;
+static const uint8_t P9N2_MCA_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_ADDRESS_PARITY = 1 ;
+static const uint8_t P9N2_MCA_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_WDATA_PARITY = 2 ;
+static const uint8_t P9N2_MCA_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_P0 = 3 ;
+static const uint8_t P9N2_MCA_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_RDATA_PARITY = 4 ;
+static const uint8_t P9N2_MCA_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_P0 = 5 ;
+static const uint8_t P9N2_MCA_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE = 6 ;
+static const uint8_t P9N2_MCA_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_P2S_MACHINE = 7 ;
+static const uint8_t P9N2_MCA_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 8 ;
+static const uint8_t P9N2_MCA_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 9 ;
+static const uint8_t P9N2_MCA_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 10 ;
+static const uint8_t P9N2_MCA_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_WRITE_NVLD = 11 ;
+static const uint8_t P9N2_MCA_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_READ_NVLD = 12 ;
+static const uint8_t P9N2_MCA_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_ADDR_INVALID = 13 ;
+static const uint8_t P9N2_MCA_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_COMMAND_PARITY = 14 ;
+static const uint8_t P9N2_MCA_PSCOM_STATUS_ERROR_REG_ACCUMULATED_GENERAL_TIMEOUT = 15 ;
+static const uint8_t P9N2_MCA_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 16 ;
+static const uint8_t P9N2_MCA_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 17 ;
+static const uint8_t P9N2_MCA_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_WDATA_PARITY = 18 ;
+static const uint8_t P9N2_MCA_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_ADDRESS_PARITY = 19 ;
+static const uint8_t P9N2_MCA_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_WDATA_PARITY = 20 ;
+static const uint8_t P9N2_MCA_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_P0 = 21 ;
+static const uint8_t P9N2_MCA_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_RDATA_PARITY = 22 ;
+static const uint8_t P9N2_MCA_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_P0 = 23 ;
+static const uint8_t P9N2_MCA_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_INTERFACE_MACHINE = 24 ;
+static const uint8_t P9N2_MCA_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_P2S_MACHINE = 25 ;
+static const uint8_t P9N2_MCA_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 26 ;
+static const uint8_t P9N2_MCA_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 27 ;
+static const uint8_t P9N2_MCA_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 28 ;
+static const uint8_t P9N2_MCA_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_WRITE_NVLD = 29 ;
+static const uint8_t P9N2_MCA_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_READ_NVLD = 30 ;
+static const uint8_t P9N2_MCA_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_ADDR_INVALID = 31 ;
+static const uint8_t P9N2_MCA_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_COMMAND_PARITY = 32 ;
+static const uint8_t P9N2_MCA_PSCOM_STATUS_ERROR_REG_TRAPPED_GENERAL_TIMEOUT = 33 ;
+static const uint8_t P9N2_MCA_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 34 ;
+static const uint8_t P9N2_MCA_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 35 ;
+
+static const uint8_t P9N2_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM = 0 ;
+static const uint8_t P9N2_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD1 = 4 ;
+static const uint8_t P9N2_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD1_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD2 = 8 ;
+static const uint8_t P9N2_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD2_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD3 = 12 ;
+static const uint8_t P9N2_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD3_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD4 = 16 ;
+static const uint8_t P9N2_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD4_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD5 = 20 ;
+static const uint8_t P9N2_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD5_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD6 = 24 ;
+static const uint8_t P9N2_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD6_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD7 = 28 ;
+static const uint8_t P9N2_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD7_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD8 = 32 ;
+static const uint8_t P9N2_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD8_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD9 = 36 ;
+static const uint8_t P9N2_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD9_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD10 = 40 ;
+static const uint8_t P9N2_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD10_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD11 = 44 ;
+static const uint8_t P9N2_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD11_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD12 = 48 ;
+static const uint8_t P9N2_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD12_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD13 = 52 ;
+static const uint8_t P9N2_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD13_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD14 = 56 ;
+static const uint8_t P9N2_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD14_LEN = 4 ;
+static const uint8_t P9N2_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD15 = 60 ;
+static const uint8_t P9N2_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD15_LEN = 4 ;
+
+static const uint8_t P9N2_MCA_RECR_MBSECCQ_DISABLE_MEMORY_ECC_CHECK_CORRECT = 0 ;
+static const uint8_t P9N2_MCA_RECR_MBSECCQ_DISABLE_MEMORY_ECC_CORRECT = 1 ;
+static const uint8_t P9N2_MCA_RECR_MBSECCQ_DISABLE_MARK_STORE_WRITE = 2 ;
+static const uint8_t P9N2_MCA_RECR_MBSECCQ_DISABLE_UE_RETRY = 3 ;
+static const uint8_t P9N2_MCA_RECR_MBSECCQ_ITAG_METADATA_ENABLE = 4 ;
+static const uint8_t P9N2_MCA_RECR_MBSECCQ_SLOW_EXIT_REDUCTION = 5 ;
+static const uint8_t P9N2_MCA_RECR_MBSECCQ_READ_POINTER_DELAY = 6 ;
+static const uint8_t P9N2_MCA_RECR_MBSECCQ_READ_POINTER_DELAY_LEN = 3 ;
+static const uint8_t P9N2_MCA_RECR_MBSECCQ_EXIT_OVERRIDE = 9 ;
+static const uint8_t P9N2_MCA_RECR_MBSECCQ_EXIT_OVERRIDE_LEN = 2 ;
+static const uint8_t P9N2_MCA_RECR_MBSECCQ_HWMARK_EXIT1 = 11 ;
+static const uint8_t P9N2_MCA_RECR_MBSECCQ_DATA_GENERATOR_OVERRIDE = 12 ;
+static const uint8_t P9N2_MCA_RECR_MBSECCQ_ECC_SCHEDULER_DELAY = 13 ;
+static const uint8_t P9N2_MCA_RECR_MBSECCQ_ECC_SCHEDULER_DELAY_LEN = 3 ;
+static const uint8_t P9N2_MCA_RECR_MBSECCQ_VAL_TO_DATA_DELAY = 16 ;
+static const uint8_t P9N2_MCA_RECR_MBSECCQ_VAL_TO_DATA_DELAY_LEN = 3 ;
+static const uint8_t P9N2_MCA_RECR_MBSECCQ_DELAY_VALID_1X = 19 ;
+static const uint8_t P9N2_MCA_RECR_MBSECCQ_NEST_VAL_TO_DATA_DELAY = 20 ;
+static const uint8_t P9N2_MCA_RECR_MBSECCQ_NEST_VAL_TO_DATA_DELAY_LEN = 2 ;
+static const uint8_t P9N2_MCA_RECR_MBSECCQ_DELAY_NONBYPASS = 22 ;
+static const uint8_t P9N2_MCA_RECR_MBSECCQ_ENABLE_SPECIAL_ATTENTION = 23 ;
+static const uint8_t P9N2_MCA_RECR_MBSECCQ_ENABLE_HOST_ATTENTION = 24 ;
+static const uint8_t P9N2_MCA_RECR_MBSECCQ_DISABLE_MPE_CONFIRM = 25 ;
+static const uint8_t P9N2_MCA_RECR_MBSECCQ_ENABLE_UE_NOISE_WINDOW = 26 ;
+static const uint8_t P9N2_MCA_RECR_MBSECCQ_ENABLE_TCE_CORRECTION = 27 ;
+static const uint8_t P9N2_MCA_RECR_MBSECCQ_ENABLE_CHIPMARKED_SCE_NCE = 28 ;
+static const uint8_t P9N2_MCA_RECR_MBSECCQ_USE_ADDRESS_HASH = 29 ;
+static const uint8_t P9N2_MCA_RECR_MBSECCQ_DATA_INVERSION = 30 ;
+static const uint8_t P9N2_MCA_RECR_MBSECCQ_DATA_INVERSION_LEN = 2 ;
+static const uint8_t P9N2_MCA_RECR_MBSECCQ_DISABLE_PIPE_NOERR_CLOCK_GATING = 32 ;
+static const uint8_t P9N2_MCA_RECR_MBSECCQ_MAINT_NO_RETRY_UE = 33 ;
+static const uint8_t P9N2_MCA_RECR_MBSECCQ_MAINT_NO_RETRY_MPE = 34 ;
+static const uint8_t P9N2_MCA_RECR_MBSECCQ_DISABLE_BYPASS_TEMPLATE_A = 35 ;
+static const uint8_t P9N2_MCA_RECR_HW372042_MARKS_ACT_EMPTY_IF_PERR_FIX_DISABLE = 36 ;
+static const uint8_t P9N2_MCA_RECR_HW365909_NOCONFIRM_REDUNDANT_FIR_FIX_DISABLE = 37 ;
+static const uint8_t P9N2_MCA_RECR_HW365926_FORCE_EXIT2_FIX_DISABLE = 38 ;
+static const uint8_t P9N2_MCA_RECR_MBSECCQ_ENABLE_BYPASS_MARK_PLACE = 39 ;
+static const uint8_t P9N2_MCA_RECR_MBSECCQ_BYPASS_TENURE_3 = 40 ;
+static const uint8_t P9N2_MCA_RECR_MBSECCQ_RESERVED_41_47 = 41 ;
+static const uint8_t P9N2_MCA_RECR_MBSECCQ_RESERVED_41_47_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_RING_FENCE_MASK_LATCH_REG_ENABLE = 1 ;
+static const uint8_t P9N2_MCA_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN = 15 ;
+
+static const uint8_t P9N2_MCBIST_RUNTIMECTRQ_CFG_RUNTIME_CTR = 0 ;
+static const uint8_t P9N2_MCBIST_RUNTIMECTRQ_CFG_RUNTIME_CTR_LEN = 37 ;
+
+static const uint8_t P9N2_MCA_TRACE_HI_DATA_REG_DATA = 0 ;
+static const uint8_t P9N2_MCA_TRACE_HI_DATA_REG_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_MCA_TRACE_LO_DATA_REG_DATA = 0 ;
+static const uint8_t P9N2_MCA_TRACE_LO_DATA_REG_DATA_LEN = 32 ;
+static const uint8_t P9N2_MCA_TRACE_LO_DATA_REG_ADDRESS = 32 ;
+static const uint8_t P9N2_MCA_TRACE_LO_DATA_REG_ADDRESS_LEN = 10 ;
+static const uint8_t P9N2_MCA_TRACE_LO_DATA_REG_LAST_BANK = 42 ;
+static const uint8_t P9N2_MCA_TRACE_LO_DATA_REG_LAST_BANK_LEN = 9 ;
+static const uint8_t P9N2_MCA_TRACE_LO_DATA_REG_LAST_BANK_VALID = 51 ;
+static const uint8_t P9N2_MCA_TRACE_LO_DATA_REG_WRITE_ON_RUN = 52 ;
+static const uint8_t P9N2_MCA_TRACE_LO_DATA_REG_RUNNING = 53 ;
+static const uint8_t P9N2_MCA_TRACE_LO_DATA_REG_HOLD_ADDRESS = 54 ;
+static const uint8_t P9N2_MCA_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN = 10 ;
+
+static const uint8_t P9N2_MCA_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE = 0 ;
+static const uint8_t P9N2_MCA_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE = 1 ;
+static const uint8_t P9N2_MCA_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE = 2 ;
+static const uint8_t P9N2_MCA_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN = 8 ;
+static const uint8_t P9N2_MCA_TRACE_TRCTRL_CONFIG_BANK_MODE = 10 ;
+static const uint8_t P9N2_MCA_TRACE_TRCTRL_CONFIG_ENH_MODE = 11 ;
+static const uint8_t P9N2_MCA_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL = 12 ;
+static const uint8_t P9N2_MCA_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN = 2 ;
+static const uint8_t P9N2_MCA_TRACE_TRCTRL_CONFIG_SELECT_CONTROL = 14 ;
+static const uint8_t P9N2_MCA_TRACE_TRCTRL_CONFIG_SELECT_CONTROL_LEN = 4 ;
+static const uint8_t P9N2_MCA_TRACE_TRCTRL_CONFIG_RUN_HOLD_OFF = 18 ;
+static const uint8_t P9N2_MCA_TRACE_TRCTRL_CONFIG_RUN_STATUS = 19 ;
+static const uint8_t P9N2_MCA_TRACE_TRCTRL_CONFIG_RUN_STICKY = 20 ;
+static const uint8_t P9N2_MCA_TRACE_TRCTRL_CONFIG_DISABLE_BANK_EDGE_DETECT = 21 ;
+static const uint8_t P9N2_MCA_TRACE_TRCTRL_CONFIG_CONTROL_UNUSED = 22 ;
+static const uint8_t P9N2_MCA_TRACE_TRCTRL_CONFIG_CONTROL_UNUSED_LEN = 6 ;
+
+static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 = 0 ;
+static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN = 64 ;
+
+static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 = 0 ;
+static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN = 24 ;
+
+static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_2_PATTERNA = 0 ;
+static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN = 24 ;
+static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_2_PATTERNB = 24 ;
+static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN = 24 ;
+
+static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_3_PATTERNC = 0 ;
+static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN = 24 ;
+static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_3_PATTERND = 24 ;
+static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_3_PATTERND_LEN = 24 ;
+
+static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_4_MASKA = 0 ;
+static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_4_MASKA_LEN = 24 ;
+static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_4_MASKB = 24 ;
+static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_4_MASKB_LEN = 24 ;
+
+static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_5_MASKC = 0 ;
+static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_5_MASKC_LEN = 24 ;
+static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_5_MASKD = 24 ;
+static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_5_MASKD_LEN = 24 ;
+
+static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION = 0 ;
+static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK = 1 ;
+static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL = 2 ;
+static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN = 2 ;
+static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL = 4 ;
+static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN = 2 ;
+static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL = 6 ;
+static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN = 2 ;
+static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL = 8 ;
+static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN = 2 ;
+static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK = 10 ;
+static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN = 4 ;
+static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK = 14 ;
+static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN = 4 ;
+static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK = 18 ;
+static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN = 4 ;
+static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK = 22 ;
+static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN = 4 ;
+static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE = 26 ;
+static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE = 27 ;
+static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE = 28 ;
+static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN = 4 ;
+static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_9_ERROR_CMP_MASK = 32 ;
+static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_9_ERROR_CMP_PATTERN = 33 ;
+static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_9_TRIG0_ERR_CMP = 34 ;
+static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_9_TRIG1_ERR_CMP = 35 ;
+static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES = 36 ;
+static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_9_SPARE_LT = 37 ;
+
+static const uint8_t P9N2_MCBIST_WATCFG0AQ_CFG_WAT_EVENT_SEL = 0 ;
+static const uint8_t P9N2_MCBIST_WATCFG0AQ_CFG_WAT_EVENT_SEL_LEN = 48 ;
+
+static const uint8_t P9N2_MCBIST_WATCFG0BQ_CFG_WAT_MSKA = 0 ;
+static const uint8_t P9N2_MCBIST_WATCFG0BQ_CFG_WAT_MSKA_LEN = 44 ;
+static const uint8_t P9N2_MCBIST_WATCFG0BQ_CFG_WAT_CNTL = 44 ;
+static const uint8_t P9N2_MCBIST_WATCFG0BQ_CFG_WAT_CNTL_LEN = 17 ;
+
+static const uint8_t P9N2_MCBIST_WATCFG0CQ_CFG_WAT_MSKB = 0 ;
+static const uint8_t P9N2_MCBIST_WATCFG0CQ_CFG_WAT_MSKB_LEN = 44 ;
+
+static const uint8_t P9N2_MCBIST_WATCFG0DQ_CFG_WAT_PATA = 0 ;
+static const uint8_t P9N2_MCBIST_WATCFG0DQ_CFG_WAT_PATA_LEN = 44 ;
+
+static const uint8_t P9N2_MCBIST_WATCFG0EQ_CFG_WAT_PATB = 0 ;
+static const uint8_t P9N2_MCBIST_WATCFG0EQ_CFG_WAT_PATB_LEN = 44 ;
+
+static const uint8_t P9N2_MCBIST_WATCFG1AQ_CFG_WAT_EVENT_SEL = 0 ;
+static const uint8_t P9N2_MCBIST_WATCFG1AQ_CFG_WAT_EVENT_SEL_LEN = 48 ;
+
+static const uint8_t P9N2_MCBIST_WATCFG1BQ_CFG_WAT_MSKA = 0 ;
+static const uint8_t P9N2_MCBIST_WATCFG1BQ_CFG_WAT_MSKA_LEN = 44 ;
+static const uint8_t P9N2_MCBIST_WATCFG1BQ_CFG_WAT_CNTL = 44 ;
+static const uint8_t P9N2_MCBIST_WATCFG1BQ_CFG_WAT_CNTL_LEN = 17 ;
+
+static const uint8_t P9N2_MCBIST_WATCFG1CQ_CFG_WAT_MSKB = 0 ;
+static const uint8_t P9N2_MCBIST_WATCFG1CQ_CFG_WAT_MSKB_LEN = 44 ;
+
+static const uint8_t P9N2_MCBIST_WATCFG1DQ_CFG_WAT_PATA = 0 ;
+static const uint8_t P9N2_MCBIST_WATCFG1DQ_CFG_WAT_PATA_LEN = 44 ;
+
+static const uint8_t P9N2_MCBIST_WATCFG1EQ_CFG_WAT_PATB = 0 ;
+static const uint8_t P9N2_MCBIST_WATCFG1EQ_CFG_WAT_PATB_LEN = 44 ;
+
+static const uint8_t P9N2_MCBIST_WATCFG2AQ_CFG_WAT_EVENT_SEL = 0 ;
+static const uint8_t P9N2_MCBIST_WATCFG2AQ_CFG_WAT_EVENT_SEL_LEN = 48 ;
+
+static const uint8_t P9N2_MCBIST_WATCFG2BQ_CFG_WAT_MSKA = 0 ;
+static const uint8_t P9N2_MCBIST_WATCFG2BQ_CFG_WAT_MSKA_LEN = 44 ;
+static const uint8_t P9N2_MCBIST_WATCFG2BQ_CFG_WAT_CNTL = 44 ;
+static const uint8_t P9N2_MCBIST_WATCFG2BQ_CFG_WAT_CNTL_LEN = 17 ;
+
+static const uint8_t P9N2_MCBIST_WATCFG2CQ_CFG_WAT_MSKB = 0 ;
+static const uint8_t P9N2_MCBIST_WATCFG2CQ_CFG_WAT_MSKB_LEN = 44 ;
+
+static const uint8_t P9N2_MCBIST_WATCFG2DQ_CFG_WAT_PATA = 0 ;
+static const uint8_t P9N2_MCBIST_WATCFG2DQ_CFG_WAT_PATA_LEN = 44 ;
+
+static const uint8_t P9N2_MCBIST_WATCFG2EQ_CFG_WAT_PATB = 0 ;
+static const uint8_t P9N2_MCBIST_WATCFG2EQ_CFG_WAT_PATB_LEN = 44 ;
+
+static const uint8_t P9N2_MCBIST_WATCFG3AQ_CFG_WAT_EVENT_SEL = 0 ;
+static const uint8_t P9N2_MCBIST_WATCFG3AQ_CFG_WAT_EVENT_SEL_LEN = 48 ;
+
+static const uint8_t P9N2_MCBIST_WATCFG3BQ_CFG_WAT_MSKA = 0 ;
+static const uint8_t P9N2_MCBIST_WATCFG3BQ_CFG_WAT_MSKA_LEN = 44 ;
+static const uint8_t P9N2_MCBIST_WATCFG3BQ_CFG_WAT_CNTL = 44 ;
+static const uint8_t P9N2_MCBIST_WATCFG3BQ_CFG_WAT_CNTL_LEN = 17 ;
+
+static const uint8_t P9N2_MCBIST_WATCFG3CQ_CFG_WAT_MSKB = 0 ;
+static const uint8_t P9N2_MCBIST_WATCFG3CQ_CFG_WAT_MSKB_LEN = 44 ;
+
+static const uint8_t P9N2_MCBIST_WATCFG3DQ_CFG_WAT_PATA = 0 ;
+static const uint8_t P9N2_MCBIST_WATCFG3DQ_CFG_WAT_PATA_LEN = 44 ;
+
+static const uint8_t P9N2_MCBIST_WATCFG3EQ_CFG_WAT_PATB = 0 ;
+static const uint8_t P9N2_MCBIST_WATCFG3EQ_CFG_WAT_PATB_LEN = 44 ;
+
+static const uint8_t P9N2_MCA_WBMGR_TAG_INFO_BUFFER_OVERRUN = 0 ;
+static const uint8_t P9N2_MCA_WBMGR_TAG_INFO_OVERRUN = 1 ;
+static const uint8_t P9N2_MCA_WBMGR_TAG_INFO_REL_ASYNC_PARITY_ERROR = 2 ;
+static const uint8_t P9N2_MCA_WBMGR_TAG_INFO_REL_ASYNC_SEQUENCE_ERROR = 3 ;
+static const uint8_t P9N2_MCA_WBMGR_TAG_INFO_REL_MERGE_ASYNC_PARITY_ERROR = 4 ;
+static const uint8_t P9N2_MCA_WBMGR_TAG_INFO_REL_MERGE_ASYNC_SEQUENCE_ERROR = 5 ;
+static const uint8_t P9N2_MCA_WBMGR_TAG_INFO_INFORMATION = 6 ;
+static const uint8_t P9N2_MCA_WBMGR_TAG_INFO_INFORMATION_LEN = 7 ;
+
+static const uint8_t P9N2_MCA_WDFCFG_CFG_WRITE_MODE_ECC_CHK_DIS = 0 ;
+static const uint8_t P9N2_MCA_WDFCFG_CFG_WRITE_MODE_ECC_COR_DIS = 1 ;
+static const uint8_t P9N2_MCA_WDFCFG_CFG_WDF_SERIAL_SEQ_MODE = 2 ;
+static const uint8_t P9N2_MCA_WDFCFG_RESET_KEEPER = 3 ;
+static const uint8_t P9N2_MCA_WDFCFG_MERGE_CAPACITY_LIMIT = 4 ;
+static const uint8_t P9N2_MCA_WDFCFG_MERGE_CAPACITY_LIMIT_LEN = 4 ;
+static const uint8_t P9N2_MCA_WDFCFG_EN_HW365559 = 8 ;
+static const uint8_t P9N2_MCA_WDFCFG_CFG_OVERRUN_FORCE_SUE_ENABLE = 9 ;
+static const uint8_t P9N2_MCA_WDFCFG_10_11_SPARE = 10 ;
+static const uint8_t P9N2_MCA_WDFCFG_10_11_SPARE_LEN = 2 ;
+static const uint8_t P9N2_MCA_WDFCFG_ASYNC_INJ = 12 ;
+static const uint8_t P9N2_MCA_WDFCFG_ASYNC_INJ_LEN = 6 ;
+static const uint8_t P9N2_MCA_WDFCFG_18_31_SPARE = 18 ;
+static const uint8_t P9N2_MCA_WDFCFG_18_31_SPARE_LEN = 14 ;
+static const uint8_t P9N2_MCA_WDFCFG_ECC_WDF_HCA_TIMEBASE_SELECT = 32 ;
+static const uint8_t P9N2_MCA_WDFCFG_ECC_WDF_HCA_TIMEBASE_SELECT_LEN = 4 ;
+static const uint8_t P9N2_MCA_WDFCFG_ECC_WDF_HCA_TIMEBASE = 36 ;
+static const uint8_t P9N2_MCA_WDFCFG_ECC_WDF_HCA_TIMEBASE_LEN = 28 ;
+
+static const uint8_t P9N2_MCA_WDFDBG_DBG_SEL_IN = 0 ;
+static const uint8_t P9N2_MCA_WDFDBG_DBG_SEL_WDF = 1 ;
+static const uint8_t P9N2_MCA_WDFDBG_DBG_SEL_PWSEQ0_DEBUG_0 = 2 ;
+static const uint8_t P9N2_MCA_WDFDBG_DBG_SEL_PWSEQ0_DEBUG_1 = 3 ;
+static const uint8_t P9N2_MCA_WDFDBG_DBG_SEL_PWSEQ1_DEBUG_0 = 4 ;
+static const uint8_t P9N2_MCA_WDFDBG_DBG_SEL_PWSEQ1_DEBUG_1 = 5 ;
+static const uint8_t P9N2_MCA_WDFDBG_DBG_SEL_PWSEQ2_DEBUG_0 = 6 ;
+static const uint8_t P9N2_MCA_WDFDBG_DBG_SEL_PWSEQ2_DEBUG_1 = 7 ;
+static const uint8_t P9N2_MCA_WDFDBG_DBG_SEL_PWSEQ3_DEBUG_0 = 8 ;
+static const uint8_t P9N2_MCA_WDFDBG_DBG_SEL_PWSEQ3_DEBUG_1 = 9 ;
+static const uint8_t P9N2_MCA_WDFDBG_DBG_SEL_PWSEQ4_DEBUG_0 = 10 ;
+static const uint8_t P9N2_MCA_WDFDBG_DBG_SEL_PWSEQ4_DEBUG_1 = 11 ;
+static const uint8_t P9N2_MCA_WDFDBG_DBG_SEL_PWSEQ5_DEBUG_0 = 12 ;
+static const uint8_t P9N2_MCA_WDFDBG_DBG_SEL_PWSEQ5_DEBUG_1 = 13 ;
+static const uint8_t P9N2_MCA_WDFDBG_DBG_SEL_PWCTL_DEBUG = 14 ;
+static const uint8_t P9N2_MCA_WDFDBG_DBG_SEL_WDFMGR_DEBUG = 15 ;
+static const uint8_t P9N2_MCA_WDFDBG_DBG_SEL_WDFRD_DEBUG_0 = 16 ;
+static const uint8_t P9N2_MCA_WDFDBG_DBG_SEL_WDFRD_DEBUG_1 = 17 ;
+static const uint8_t P9N2_MCA_WDFDBG_DBG_SEL_WDFWR_DEBUG_0 = 18 ;
+static const uint8_t P9N2_MCA_WDFDBG_DBG_SEL_WDFWR_DEBUG_1 = 19 ;
+static const uint8_t P9N2_MCA_WDFDBG_DBG_SEL_SEC_WDFRD_DEBUG_0 = 20 ;
+static const uint8_t P9N2_MCA_WDFDBG_DBG_SEL_SEC_WDFRD_DEBUG_1 = 21 ;
+static const uint8_t P9N2_MCA_WDFDBG_DBG_SPARE = 22 ;
+static const uint8_t P9N2_MCA_WDFDBG_DBG_SPARE_LEN = 10 ;
+static const uint8_t P9N2_MCA_WDFDBG_WAT_EVENT_ENABLE = 32 ;
+static const uint8_t P9N2_MCA_WDFDBG_WAT_SPARE1 = 33 ;
+static const uint8_t P9N2_MCA_WDFDBG_WAT_SPARE1_LEN = 3 ;
+static const uint8_t P9N2_MCA_WDFDBG_WAT0_EVENT_SELECT = 36 ;
+static const uint8_t P9N2_MCA_WDFDBG_WAT0_EVENT_SELECT_LEN = 4 ;
+static const uint8_t P9N2_MCA_WDFDBG_WAT1_EVENT_SELECT = 40 ;
+static const uint8_t P9N2_MCA_WDFDBG_WAT1_EVENT_SELECT_LEN = 4 ;
+
+static const uint8_t P9N2_MCA_WECR_MBA_WRD_MODE_CFG_WRD_ECC_CHK_DISABLE = 0 ;
+static const uint8_t P9N2_MCA_WECR_MBA_WRD_MODE_CFG_WRD_ECC_COR_DISABLE = 1 ;
+static const uint8_t P9N2_MCA_WECR_MBA_WRD_MODE_CFG_CRC_MODE_EN = 2 ;
+static const uint8_t P9N2_MCA_WECR_MBA_WRD_MODE_CFG_CRC_MODE_X8 = 3 ;
+static const uint8_t P9N2_MCA_WECR_MBA_WRD_MODE_CFG_FORCE_DFI_CG_ALWAYS_ON = 4 ;
+static const uint8_t P9N2_MCA_WECR_MBA_WRD_MODE_CFG_CAW2_CE_UE_ERR_DETECT_EN = 5 ;
+
+static const uint8_t P9N2_MCA_WESR_SYNDROME = 0 ;
+static const uint8_t P9N2_MCA_WESR_SYNDROME_LEN = 8 ;
+static const uint8_t P9N2_MCA_WESR_WHICH_8BECK = 8 ;
+static const uint8_t P9N2_MCA_WESR_WHICH_8BECK_LEN = 2 ;
+static const uint8_t P9N2_MCA_WESR_PAR_ERR_ONLY = 10 ;
+
+static const uint8_t P9N2_MCA_WOF_FIR = 0 ;
+static const uint8_t P9N2_MCA_WOF_FIR_LEN = 64 ;
+
+static const uint8_t P9N2_MCA_WRITE_PROTECT_ENABLE_REG_RING_LOCKING = 0 ;
+static const uint8_t P9N2_MCA_WRITE_PROTECT_ENABLE_REG_RESERVED_RING_LOCKING = 1 ;
+
+static const uint8_t P9N2_MCA_WRITE_PROTECT_RINGS_REG_RINGS = 0 ;
+static const uint8_t P9N2_MCA_WRITE_PROTECT_RINGS_REG_RINGS_LEN = 16 ;
+
+static const uint8_t P9N2_MCA_WRTCFG_CFG_WRITE_MODE_ECC_CHK_DIS = 0 ;
+static const uint8_t P9N2_MCA_WRTCFG_CFG_WRITE_MODE_ECC_COR_DIS = 1 ;
+static const uint8_t P9N2_MCA_WRTCFG_RESET_KEEPER = 2 ;
+static const uint8_t P9N2_MCA_WRTCFG_MPIPL = 3 ;
+static const uint8_t P9N2_MCA_WRTCFG_ASYNC_INJ = 4 ;
+static const uint8_t P9N2_MCA_WRTCFG_ASYNC_INJ_LEN = 4 ;
+static const uint8_t P9N2_MCA_WRTCFG_EN_HW365559 = 8 ;
+static const uint8_t P9N2_MCA_WRTCFG_NEW_WRITE_64B_MODE = 9 ;
+static const uint8_t P9N2_MCA_WRTCFG_CFG_OVERRUN_FORCE_SUE_ENABLE = 10 ;
+
+static const uint8_t P9N2_MCA_WRTDBGMCA_MCA_DBG_SEL_IN = 0 ;
+static const uint8_t P9N2_MCA_WRTDBGMCA_MCA_DBG_SEL_WRT = 1 ;
+static const uint8_t P9N2_MCA_WRTDBGMCA_WBRD_DEBUG_0_SELECT = 2 ;
+static const uint8_t P9N2_MCA_WRTDBGMCA_WBRD_DEBUG_1_SELECT = 3 ;
+static const uint8_t P9N2_MCA_WRTDBGMCA_SEC_WBRD_DEBUG_0_SELECT = 4 ;
+static const uint8_t P9N2_MCA_WRTDBGMCA_SEC_WBRD_DEBUG_1_SELECT = 5 ;
+static const uint8_t P9N2_MCA_WRTDBGMCA_DBG_SPARE_MCA = 6 ;
+static const uint8_t P9N2_MCA_WRTDBGMCA_DBG_SPARE_MCA_LEN = 10 ;
+static const uint8_t P9N2_MCA_WRTDBGMCA_WAT_EVENT_ENABLE_MCA = 16 ;
+static const uint8_t P9N2_MCA_WRTDBGMCA_WAT_SPARE1_MCA = 17 ;
+static const uint8_t P9N2_MCA_WRTDBGMCA_WAT_SPARE1_MCA_LEN = 3 ;
+static const uint8_t P9N2_MCA_WRTDBGMCA_WAT0_EVENT_SELECT_MCA = 20 ;
+static const uint8_t P9N2_MCA_WRTDBGMCA_WAT0_EVENT_SELECT_MCA_LEN = 4 ;
+static const uint8_t P9N2_MCA_WRTDBGMCA_WAT1_EVENT_SELECT_MCA = 24 ;
+static const uint8_t P9N2_MCA_WRTDBGMCA_WAT1_EVENT_SELECT_MCA_LEN = 4 ;
+
+static const uint8_t P9N2_MCA_WRTDBGNEST_NEST_DBG_SEL_IN = 0 ;
+static const uint8_t P9N2_MCA_WRTDBGNEST_NEST_DBG_SEL_WRT = 1 ;
+static const uint8_t P9N2_MCA_WRTDBGNEST_WBMGR_DBG_0_SELECT = 2 ;
+static const uint8_t P9N2_MCA_WRTDBGNEST_WBMGR_DBG_1_SELECT = 3 ;
+static const uint8_t P9N2_MCA_WRTDBGNEST_WRCNTL_DBG_SELECT = 4 ;
+static const uint8_t P9N2_MCA_WRTDBGNEST_DBG_SPARE_NEST = 5 ;
+static const uint8_t P9N2_MCA_WRTDBGNEST_DBG_SPARE_NEST_LEN = 11 ;
+static const uint8_t P9N2_MCA_WRTDBGNEST_WAT_EVENT_ENABLE_NEST = 16 ;
+static const uint8_t P9N2_MCA_WRTDBGNEST_WAT_SPARE1_NEST = 17 ;
+static const uint8_t P9N2_MCA_WRTDBGNEST_WAT_SPARE1_NEST_LEN = 3 ;
+static const uint8_t P9N2_MCA_WRTDBGNEST_WAT0_EVENT_SELECT_NEST = 20 ;
+static const uint8_t P9N2_MCA_WRTDBGNEST_WAT0_EVENT_SELECT_NEST_LEN = 4 ;
+static const uint8_t P9N2_MCA_WRTDBGNEST_WAT1_EVENT_SELECT_NEST = 24 ;
+static const uint8_t P9N2_MCA_WRTDBGNEST_WAT1_EVENT_SELECT_NEST_LEN = 4 ;
+
+static const uint8_t P9N2_MCA_WDF_WRT_ECC_DW0_ERR_TYPE = 0 ;
+static const uint8_t P9N2_MCA_WDF_WRT_ECC_DW0_ERR_TYPE_LEN = 3 ;
+static const uint8_t P9N2_MCA_WDF_WRT_ECC_DW0_SYNDROME = 8 ;
+static const uint8_t P9N2_MCA_WDF_WRT_ECC_DW0_SYNDROME_LEN = 8 ;
+static const uint8_t P9N2_MCA_WDF_WRT_ECC_DW1_ERR_TYPE = 16 ;
+static const uint8_t P9N2_MCA_WDF_WRT_ECC_DW1_ERR_TYPE_LEN = 3 ;
+static const uint8_t P9N2_MCA_WDF_WRT_ECC_DW1_SYNDROME = 24 ;
+static const uint8_t P9N2_MCA_WDF_WRT_ECC_DW1_SYNDROME_LEN = 8 ;
+static const uint8_t P9N2_MCA_WDF_WRT_ECC_DW2_ERR_TYPE = 32 ;
+static const uint8_t P9N2_MCA_WDF_WRT_ECC_DW2_ERR_TYPE_LEN = 3 ;
+static const uint8_t P9N2_MCA_WDF_WRT_ECC_DW2_SYNDROME = 40 ;
+static const uint8_t P9N2_MCA_WDF_WRT_ECC_DW2_SYNDROME_LEN = 8 ;
+static const uint8_t P9N2_MCA_WDF_WRT_ECC_DW3_ERR_TYPE = 48 ;
+static const uint8_t P9N2_MCA_WDF_WRT_ECC_DW3_ERR_TYPE_LEN = 3 ;
+static const uint8_t P9N2_MCA_WDF_WRT_ECC_DW3_SYNDROME = 56 ;
+static const uint8_t P9N2_MCA_WDF_WRT_ECC_DW3_SYNDROME_LEN = 8 ;
+
+static const uint8_t P9N2_MCA_WREITE_WRT_ECC_DW0_ERR_TYPE = 0 ;
+static const uint8_t P9N2_MCA_WREITE_WRT_ECC_DW0_ERR_TYPE_LEN = 3 ;
+static const uint8_t P9N2_MCA_WREITE_WRT_ECC_DW0_SYNDROME = 8 ;
+static const uint8_t P9N2_MCA_WREITE_WRT_ECC_DW0_SYNDROME_LEN = 8 ;
+static const uint8_t P9N2_MCA_WREITE_WRT_ECC_DW1_ERR_TYPE = 16 ;
+static const uint8_t P9N2_MCA_WREITE_WRT_ECC_DW1_ERR_TYPE_LEN = 3 ;
+static const uint8_t P9N2_MCA_WREITE_WRT_ECC_DW1_SYNDROME = 24 ;
+static const uint8_t P9N2_MCA_WREITE_WRT_ECC_DW1_SYNDROME_LEN = 8 ;
+static const uint8_t P9N2_MCA_WREITE_WRT_ECC_DW2_ERR_TYPE = 32 ;
+static const uint8_t P9N2_MCA_WREITE_WRT_ECC_DW2_ERR_TYPE_LEN = 3 ;
+static const uint8_t P9N2_MCA_WREITE_WRT_ECC_DW2_SYNDROME = 40 ;
+static const uint8_t P9N2_MCA_WREITE_WRT_ECC_DW2_SYNDROME_LEN = 8 ;
+static const uint8_t P9N2_MCA_WREITE_WRT_ECC_DW3_ERR_TYPE = 48 ;
+static const uint8_t P9N2_MCA_WREITE_WRT_ECC_DW3_ERR_TYPE_LEN = 3 ;
+static const uint8_t P9N2_MCA_WREITE_WRT_ECC_DW3_SYNDROME = 56 ;
+static const uint8_t P9N2_MCA_WREITE_WRT_ECC_DW3_SYNDROME_LEN = 8 ;
+
+#endif
+
diff --git a/src/import/chips/p9/common/include/p9n2_misc_scom_addresses.H b/src/import/chips/p9/common/include/p9n2_misc_scom_addresses.H
new file mode 100644
index 000000000..32a21ddac
--- /dev/null
+++ b/src/import/chips/p9/common/include/p9n2_misc_scom_addresses.H
@@ -0,0 +1,14845 @@
+/* IBM_PROLOG_BEGIN_TAG */
+/* This is an automatically generated prolog. */
+/* */
+/* $Source: src/import/chips/p9/common/include/p9n2_misc_scom_addresses.H $ */
+/* */
+/* OpenPOWER HostBoot Project */
+/* */
+/* Contributors Listed Below - COPYRIGHT 2017 */
+/* [+] International Business Machines Corp. */
+/* */
+/* */
+/* Licensed under the Apache License, Version 2.0 (the "License"); */
+/* you may not use this file except in compliance with the License. */
+/* You may obtain a copy of the License at */
+/* */
+/* http://www.apache.org/licenses/LICENSE-2.0 */
+/* */
+/* Unless required by applicable law or agreed to in writing, software */
+/* distributed under the License is distributed on an "AS IS" BASIS, */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */
+/* implied. See the License for the specific language governing */
+/* permissions and limitations under the License. */
+/* */
+/* IBM_PROLOG_END_TAG */
+///
+/// @file p9_misc_scom_addresses.H
+/// @brief Defines constants for scom addresses
+///
+// *HWP HWP Owner: Ben Gass <bgass@us.ibm.com>
+// *HWP FW Owner: Thi Tran <thi@us.ibm.com>
+// *HWP Team: SOA
+// *HWP Level: 1
+// *HWP Consumed by: FSP:HB:HS:OCC:SBE:CME:SGPE:PGPE:FPPE:IPPE
+
+/*---------------------------------------------------------------
+ *
+ *---------------------------------------------------------------
+ *
+ *---------------------------------------------------------------
+ */
+
+#ifndef __P9N2_MISC_SCOM_ADDRESSES_H
+#define __P9N2_MISC_SCOM_ADDRESSES_H
+
+#include <stdint.h>
+
+
+static const uint64_t P9N2_PHB_ACT0_REG = 0x0D01090Eull;
+
+static const uint64_t P9N2_PHB_0_ACT0_REG = 0x0D01090Eull;
+
+static const uint64_t P9N2_PHB_1_ACT0_REG = 0x0E01090Eull;
+
+static const uint64_t P9N2_PHB_2_ACT0_REG = 0x0E01094Eull;
+
+static const uint64_t P9N2_PHB_3_ACT0_REG = 0x0F01090Eull;
+
+static const uint64_t P9N2_PHB_4_ACT0_REG = 0x0F01094Eull;
+
+static const uint64_t P9N2_PHB_5_ACT0_REG = 0x0F01098Eull;
+
+
+static const uint64_t P9N2_PHB_ACTION1_REG = 0x0D01090Full;
+
+static const uint64_t P9N2_PHB_0_ACTION1_REG = 0x0D01090Full;
+
+static const uint64_t P9N2_PHB_1_ACTION1_REG = 0x0E01090Full;
+
+static const uint64_t P9N2_PHB_2_ACTION1_REG = 0x0E01094Full;
+
+static const uint64_t P9N2_PHB_3_ACTION1_REG = 0x0F01090Full;
+
+static const uint64_t P9N2_PHB_4_ACTION1_REG = 0x0F01094Full;
+
+static const uint64_t P9N2_PHB_5_ACTION1_REG = 0x0F01098Full;
+
+
+static const uint64_t P9N2_PEC_ADDREXTMASK_REG = 0x04010C05ull;
+
+static const uint64_t P9N2_PEC_0_ADDREXTMASK_REG = 0x04010C05ull;
+
+static const uint64_t P9N2_PEC_1_ADDREXTMASK_REG = 0x04011005ull;
+
+static const uint64_t P9N2_PEC_2_ADDREXTMASK_REG = 0x04011405ull;
+
+
+static const uint64_t P9N2_PU_ADDR_0_HASH_FUNCTION_REG = 0x02011141ull;
+
+
+static const uint64_t P9N2_PU_ADDR_10_HASH_FUNCTION_REG = 0x0201114Bull;
+
+
+static const uint64_t P9N2_PU_ADDR_1_HASH_FUNCTION_REG = 0x02011142ull;
+
+
+static const uint64_t P9N2_PU_ADDR_2_HASH_FUNCTION_REG = 0x02011143ull;
+
+
+static const uint64_t P9N2_PU_ADDR_3_HASH_FUNCTION_REG = 0x02011144ull;
+
+
+static const uint64_t P9N2_PU_ADDR_4_HASH_FUNCTION_REG = 0x02011145ull;
+
+
+static const uint64_t P9N2_PU_ADDR_5_HASH_FUNCTION_REG = 0x02011146ull;
+
+
+static const uint64_t P9N2_PU_ADDR_6_HASH_FUNCTION_REG = 0x02011147ull;
+
+
+static const uint64_t P9N2_PU_ADDR_7_HASH_FUNCTION_REG = 0x02011148ull;
+
+
+static const uint64_t P9N2_PU_ADDR_8_HASH_FUNCTION_REG = 0x02011149ull;
+
+
+static const uint64_t P9N2_PU_ADDR_9_HASH_FUNCTION_REG = 0x0201114Aull;
+
+
+static const uint64_t P9N2_PU_ADDR_TRAP_REG = 0x06010003ull;
+
+
+static const uint64_t P9N2_PEC_ADDR_TRAP_REG = 0x0D010003ull;
+
+static const uint64_t P9N2_PEC_0_ADDR_TRAP_REG = 0x0D010003ull;
+
+static const uint64_t P9N2_PEC_1_ADDR_TRAP_REG = 0x0E010003ull;
+
+static const uint64_t P9N2_PEC_2_ADDR_TRAP_REG = 0x0F010003ull;
+
+
+static const uint64_t P9N2_PU_N0_ADDR_TRAP_REG = 0x02010003ull;
+
+static const uint64_t P9N2_PU_N1_ADDR_TRAP_REG = 0x03010003ull;
+
+static const uint64_t P9N2_PU_N2_ADDR_TRAP_REG = 0x04010003ull;
+
+static const uint64_t P9N2_PU_N3_ADDR_TRAP_REG = 0x05010003ull;
+
+
+static const uint64_t P9N2_PU_ADS_XSCOM_CMD_REG = 0x0009001Cull;
+
+
+static const uint64_t P9N2_PU_ADU_HANG_DIV_REG = 0x00090050ull;
+
+
+static const uint64_t P9N2_PU_ALTD_ADDR_REG = 0x00090000ull;
+
+
+static const uint64_t P9N2_PU_ALTD_CMD_REG = 0x00090001ull;
+
+
+static const uint64_t P9N2_PU_ALTD_DATA_REG = 0x00090004ull;
+
+
+static const uint64_t P9N2_PU_ALTD_OPTION_REG = 0x00090002ull;
+
+
+static const uint64_t P9N2_PU_ALTD_STATUS_REG = 0x00090003ull;
+
+
+static const uint64_t P9N2_PU_NPU_CTL_ALTER_CREDIT_COUNTERS = 0x05011390ull;
+
+static const uint64_t P9N2_PU_NPU_SM3_ALTER_CREDIT_COUNTERS = 0x05011360ull;
+
+static const uint64_t P9N2__CTL_ALTER_CREDIT_COUNTERS = 0x05011590ull;
+
+static const uint64_t P9N2__SM3_ALTER_CREDIT_COUNTERS = 0x05011560ull;
+
+
+static const uint64_t P9N2_CAPP_APCFG = 0x02010819ull;
+
+static const uint64_t P9N2_CAPP_0_APCFG = 0x02010819ull;
+
+static const uint64_t P9N2_CAPP_1_APCFG = 0x04010819ull;
+
+
+static const uint64_t P9N2_CAPP_APCLCO = 0x02010821ull;
+
+static const uint64_t P9N2_CAPP_0_APCLCO = 0x02010821ull;
+
+static const uint64_t P9N2_CAPP_1_APCLCO = 0x04010821ull;
+
+
+static const uint64_t P9N2_CAPP_APCRDFSMMASK = 0x02010823ull;
+
+static const uint64_t P9N2_CAPP_0_APCRDFSMMASK = 0x02010823ull;
+
+static const uint64_t P9N2_CAPP_1_APCRDFSMMASK = 0x04010823ull;
+
+
+static const uint64_t P9N2_CAPP_APCTL = 0x02010818ull;
+
+static const uint64_t P9N2_CAPP_0_APCTL = 0x02010818ull;
+
+static const uint64_t P9N2_CAPP_1_APCTL = 0x04010818ull;
+
+
+static const uint64_t P9N2_CAPP_APC_ARRY_ADDR = 0x0201082Aull;
+
+static const uint64_t P9N2_CAPP_0_APC_ARRY_ADDR = 0x0201082Aull;
+
+static const uint64_t P9N2_CAPP_1_APC_ARRY_ADDR = 0x0401082Aull;
+
+
+static const uint64_t P9N2_CAPP_APC_ARRY_RDDATA = 0x0201082Bull;
+
+static const uint64_t P9N2_CAPP_0_APC_ARRY_RDDATA = 0x0201082Bull;
+
+static const uint64_t P9N2_CAPP_1_APC_ARRY_RDDATA = 0x0401082Bull;
+
+
+static const uint64_t P9N2_CAPP_APC_ARRY_WRDATA = 0x02010842ull;
+
+static const uint64_t P9N2_CAPP_0_APC_ARRY_WRDATA = 0x02010842ull;
+
+static const uint64_t P9N2_CAPP_1_APC_ARRY_WRDATA = 0x04010842ull;
+
+
+static const uint64_t P9N2_CAPP_APC_ERRINJ = 0x02010810ull;
+
+static const uint64_t P9N2_CAPP_0_APC_ERRINJ = 0x02010810ull;
+
+static const uint64_t P9N2_CAPP_1_APC_ERRINJ = 0x04010810ull;
+
+
+static const uint64_t P9N2_CAPP_APC_PMUSEL = 0x02010816ull;
+
+static const uint64_t P9N2_CAPP_0_APC_PMUSEL = 0x02010816ull;
+
+static const uint64_t P9N2_CAPP_1_APC_PMUSEL = 0x04010816ull;
+
+
+static const uint64_t P9N2_CAPP_ASE_TUPLE0 = 0x02010846ull;
+
+static const uint64_t P9N2_CAPP_0_ASE_TUPLE0 = 0x02010846ull;
+
+static const uint64_t P9N2_CAPP_1_ASE_TUPLE0 = 0x04010846ull;
+
+
+static const uint64_t P9N2_CAPP_ASE_TUPLE1 = 0x02010847ull;
+
+static const uint64_t P9N2_CAPP_0_ASE_TUPLE1 = 0x02010847ull;
+
+static const uint64_t P9N2_CAPP_1_ASE_TUPLE1 = 0x04010847ull;
+
+
+static const uint64_t P9N2_CAPP_ASE_TUPLE2 = 0x02010848ull;
+
+static const uint64_t P9N2_CAPP_0_ASE_TUPLE2 = 0x02010848ull;
+
+static const uint64_t P9N2_CAPP_1_ASE_TUPLE2 = 0x04010848ull;
+
+
+static const uint64_t P9N2_CAPP_ASE_TUPLE3 = 0x02010849ull;
+
+static const uint64_t P9N2_CAPP_0_ASE_TUPLE3 = 0x02010849ull;
+
+static const uint64_t P9N2_CAPP_1_ASE_TUPLE3 = 0x04010849ull;
+
+
+static const uint64_t P9N2_PEC_ASSIST_INTERRUPT_REG = 0x0D0F0011ull;
+
+static const uint64_t P9N2_PEC_0_ASSIST_INTERRUPT_REG = 0x0D0F0011ull;
+
+static const uint64_t P9N2_PEC_1_ASSIST_INTERRUPT_REG = 0x0E0F0011ull;
+
+static const uint64_t P9N2_PEC_2_ASSIST_INTERRUPT_REG = 0x0F0F0011ull;
+
+
+static const uint64_t P9N2_PU_ATOMIC_LOCK_MASK_LATCH_REG = 0x06010007ull;
+
+
+static const uint64_t P9N2_PEC_ATOMIC_LOCK_MASK_LATCH_REG = 0x0D010007ull;
+
+static const uint64_t P9N2_PEC_0_ATOMIC_LOCK_MASK_LATCH_REG = 0x0D010007ull;
+
+static const uint64_t P9N2_PEC_1_ATOMIC_LOCK_MASK_LATCH_REG = 0x0E010007ull;
+
+static const uint64_t P9N2_PEC_2_ATOMIC_LOCK_MASK_LATCH_REG = 0x0F010007ull;
+
+
+static const uint64_t P9N2_PU_N0_ATOMIC_LOCK_MASK_LATCH_REG = 0x02010007ull;
+
+static const uint64_t P9N2_PU_N1_ATOMIC_LOCK_MASK_LATCH_REG = 0x03010007ull;
+
+static const uint64_t P9N2_PU_N2_ATOMIC_LOCK_MASK_LATCH_REG = 0x04010007ull;
+
+static const uint64_t P9N2_PU_N3_ATOMIC_LOCK_MASK_LATCH_REG = 0x05010007ull;
+
+
+static const uint64_t P9N2_PEC_ATOMIC_LOCK_REG = 0x0D0F03FFull;
+
+static const uint64_t P9N2_PEC_0_ATOMIC_LOCK_REG = 0x0D0F03FFull;
+
+static const uint64_t P9N2_PEC_1_ATOMIC_LOCK_REG = 0x0E0F03FFull;
+
+static const uint64_t P9N2_PEC_2_ATOMIC_LOCK_REG = 0x0F0F03FFull;
+
+
+static const uint64_t P9N2_PU_NPU1_SM1_ATR_HA_PTR = 0x05011122ull;
+
+static const uint64_t P9N2_PU_NPU1_SM2_ATR_HA_PTR = 0x05011142ull;
+
+static const uint64_t P9N2_PU_NPU_SM1_ATR_HA_PTR = 0x05011322ull;
+
+static const uint64_t P9N2_PU_NPU_SM2_ATR_HA_PTR = 0x05011342ull;
+
+static const uint64_t P9N2__SM1_ATR_HA_PTR = 0x05011522ull;
+
+static const uint64_t P9N2__SM2_ATR_HA_PTR = 0x05011542ull;
+
+
+static const uint64_t P9N2__SM0_ATS_CKSW = 0x05011604ull;
+
+
+static const uint64_t P9N2__SM1_ATS_CTRL = 0x05011620ull;
+
+
+static const uint64_t P9N2__SM0_ATS_HOLD = 0x05011605ull;
+
+
+static const uint64_t P9N2__SM0_ATS_MASK = 0x05011606ull;
+
+
+static const uint64_t P9N2__SM1_ATS_TCR = 0x05011626ull;
+
+
+static const uint64_t P9N2_PEC_ATTN_INTERRUPT_REG = 0x0D0F001Aull;
+
+static const uint64_t P9N2_PEC_0_ATTN_INTERRUPT_REG = 0x0D0F001Aull;
+
+static const uint64_t P9N2_PEC_1_ATTN_INTERRUPT_REG = 0x0E0F001Aull;
+
+static const uint64_t P9N2_PEC_2_ATTN_INTERRUPT_REG = 0x0F0F001Aull;
+
+
+static const uint64_t P9N2_PU_BANK0_MCD_BOT = 0x0301140Cull;
+
+static const uint64_t P9N2_PU_MCD1_BANK0_MCD_BOT = 0x0301100Cull;
+
+
+static const uint64_t P9N2_PU_BANK0_MCD_CHA = 0x0301140Dull;
+
+static const uint64_t P9N2_PU_MCD1_BANK0_MCD_CHA = 0x0301100Dull;
+
+
+static const uint64_t P9N2_PU_BANK0_MCD_CMD = 0x0301140Eull;
+
+static const uint64_t P9N2_PU_MCD1_BANK0_MCD_CMD = 0x0301100Eull;
+
+
+static const uint64_t P9N2_PU_BANK0_MCD_REC = 0x03011410ull;
+
+static const uint64_t P9N2_PU_MCD1_BANK0_MCD_REC = 0x03011010ull;
+
+
+static const uint64_t P9N2_PU_BANK0_MCD_RW = 0x0301140Full;
+
+static const uint64_t P9N2_PU_MCD1_BANK0_MCD_RW = 0x0301100Full;
+
+
+static const uint64_t P9N2_PU_BANK0_MCD_STR = 0x0301140Bull;
+
+static const uint64_t P9N2_PU_MCD1_BANK0_MCD_STR = 0x0301100Bull;
+
+
+static const uint64_t P9N2_PU_BANK0_MCD_TOP = 0x0301140Aull;
+
+static const uint64_t P9N2_PU_MCD1_BANK0_MCD_TOP = 0x0301100Aull;
+
+
+static const uint64_t P9N2_PU_BANK0_MCD_VGC = 0x03011411ull;
+
+static const uint64_t P9N2_PU_MCD1_BANK0_MCD_VGC = 0x03011011ull;
+
+
+static const uint64_t P9N2_PEC_0_STACK0_BARE_REG = 0x04010C54ull;
+
+static const uint64_t P9N2_PEC_1_STACK0_BARE_REG = 0x04011054ull;
+
+static const uint64_t P9N2_PEC_1_STACK1_BARE_REG = 0x04011094ull;
+
+static const uint64_t P9N2_PEC_1_STACK2_BARE_REG = 0x040110D4ull;
+
+static const uint64_t P9N2_PEC_2_STACK0_BARE_REG = 0x04011454ull;
+
+static const uint64_t P9N2_PEC_2_STACK1_BARE_REG = 0x04011494ull;
+
+static const uint64_t P9N2_PEC_2_STACK2_BARE_REG = 0x040114D4ull;
+
+static const uint64_t P9N2_PEC_STACK0_BARE_REG = 0x04010C54ull;
+
+static const uint64_t P9N2_PHB_BARE_REG = 0x04010C54ull;
+
+static const uint64_t P9N2_PHB_0_BARE_REG = 0x04010C54ull;
+
+static const uint64_t P9N2_PHB_1_BARE_REG = 0x04011054ull;
+
+static const uint64_t P9N2_PHB_2_BARE_REG = 0x04011094ull;
+
+static const uint64_t P9N2_PHB_3_BARE_REG = 0x04011454ull;
+
+static const uint64_t P9N2_PHB_4_BARE_REG = 0x04011494ull;
+
+static const uint64_t P9N2_PHB_5_BARE_REG = 0x040114D4ull;
+
+
+static const uint64_t P9N2_PU_BCDE_CTL_OCI = 0xC0040080ull;
+
+static const uint64_t P9N2_PU_BCDE_CTL_PIB = 0x00068010ull;
+
+
+static const uint64_t P9N2_PU_BCDE_OCIBAR_OCI = 0xC00400A0ull;
+
+static const uint64_t P9N2_PU_BCDE_OCIBAR_PIB = 0x00068014ull;
+
+
+static const uint64_t P9N2_PU_BCDE_PBADR_OCI = 0xC0040098ull;
+
+static const uint64_t P9N2_PU_BCDE_PBADR_PIB = 0x00068013ull;
+
+
+static const uint64_t P9N2_PU_BCDE_SET_OCI = 0xC0040088ull;
+
+static const uint64_t P9N2_PU_BCDE_SET_PIB = 0x00068011ull;
+
+
+static const uint64_t P9N2_PU_BCDE_STAT_OCI = 0xC0040090ull;
+
+static const uint64_t P9N2_PU_BCDE_STAT_PIB = 0x00068012ull;
+
+
+static const uint64_t P9N2_PU_BCUE_CTL_OCI = 0xC00400A8ull;
+
+static const uint64_t P9N2_PU_BCUE_CTL_PIB = 0x00068015ull;
+
+
+static const uint64_t P9N2_PU_BCUE_OCIBAR_OCI = 0xC00400C8ull;
+
+static const uint64_t P9N2_PU_BCUE_OCIBAR_PIB = 0x00068019ull;
+
+
+static const uint64_t P9N2_PU_BCUE_PBADR_OCI = 0xC00400C0ull;
+
+static const uint64_t P9N2_PU_BCUE_PBADR_PIB = 0x00068018ull;
+
+
+static const uint64_t P9N2_PU_BCUE_SET_OCI = 0xC00400B0ull;
+
+static const uint64_t P9N2_PU_BCUE_SET_PIB = 0x00068016ull;
+
+
+static const uint64_t P9N2_PU_BCUE_STAT_OCI = 0xC00400B8ull;
+
+static const uint64_t P9N2_PU_BCUE_STAT_PIB = 0x00068017ull;
+
+
+static const uint64_t P9N2_PU_BDF2PE_00_CONFIG = 0x050116A0ull;
+
+static const uint64_t P9N2_NV_BDF2PE_00_CONFIG = 0x050110CAull;
+
+static const uint64_t P9N2_NV_0_BDF2PE_00_CONFIG = 0x050110CAull;
+
+static const uint64_t P9N2_NV_4_BDF2PE_00_CONFIG = 0x050114CAull;
+
+static const uint64_t P9N2_PU_NPU2_NTL0_BDF2PE_00_CONFIG = 0x050112CAull;
+
+
+static const uint64_t P9N2_PU_BDF2PE_01_CONFIG = 0x050116A1ull;
+
+static const uint64_t P9N2_NV_BDF2PE_01_CONFIG = 0x050110CBull;
+
+static const uint64_t P9N2_NV_0_BDF2PE_01_CONFIG = 0x050110CBull;
+
+static const uint64_t P9N2_NV_4_BDF2PE_01_CONFIG = 0x050114CBull;
+
+static const uint64_t P9N2_PU_NPU2_NTL0_BDF2PE_01_CONFIG = 0x050112CBull;
+
+
+static const uint64_t P9N2_PU_BDF2PE_02_CONFIG = 0x050116A2ull;
+
+static const uint64_t P9N2_NV_BDF2PE_02_CONFIG = 0x050110CCull;
+
+static const uint64_t P9N2_NV_0_BDF2PE_02_CONFIG = 0x050110CCull;
+
+static const uint64_t P9N2_NV_4_BDF2PE_02_CONFIG = 0x050114CCull;
+
+static const uint64_t P9N2_PU_NPU2_NTL0_BDF2PE_02_CONFIG = 0x050112CCull;
+
+
+static const uint64_t P9N2_PU_BDF2PE_10_CONFIG = 0x050116A3ull;
+
+static const uint64_t P9N2_NV_BDF2PE_10_CONFIG = 0x050110CDull;
+
+static const uint64_t P9N2_NV_0_BDF2PE_10_CONFIG = 0x050110CDull;
+
+static const uint64_t P9N2_NV_4_BDF2PE_10_CONFIG = 0x050114CDull;
+
+static const uint64_t P9N2_PU_NPU2_NTL0_BDF2PE_10_CONFIG = 0x050112CDull;
+
+
+static const uint64_t P9N2_PU_BDF2PE_11_CONFIG = 0x050116A4ull;
+
+static const uint64_t P9N2_NV_BDF2PE_11_CONFIG = 0x050110CEull;
+
+static const uint64_t P9N2_NV_0_BDF2PE_11_CONFIG = 0x050110CEull;
+
+static const uint64_t P9N2_NV_4_BDF2PE_11_CONFIG = 0x050114CEull;
+
+static const uint64_t P9N2_PU_NPU2_NTL0_BDF2PE_11_CONFIG = 0x050112CEull;
+
+
+static const uint64_t P9N2_PU_BDF2PE_12_CONFIG = 0x050116A5ull;
+
+static const uint64_t P9N2_NV_BDF2PE_12_CONFIG = 0x050110CFull;
+
+static const uint64_t P9N2_NV_0_BDF2PE_12_CONFIG = 0x050110CFull;
+
+static const uint64_t P9N2_NV_4_BDF2PE_12_CONFIG = 0x050114CFull;
+
+static const uint64_t P9N2_PU_NPU2_NTL0_BDF2PE_12_CONFIG = 0x050112CFull;
+
+
+static const uint64_t P9N2_PU_BDF2PE_20_CONFIG = 0x050116A6ull;
+
+
+static const uint64_t P9N2_PU_BDF2PE_21_CONFIG = 0x050116A7ull;
+
+
+static const uint64_t P9N2_PU_BDF2PE_22_CONFIG = 0x050116A8ull;
+
+
+static const uint64_t P9N2_PU_BDF2PE_30_CONFIG = 0x050116A9ull;
+
+
+static const uint64_t P9N2_PU_BDF2PE_31_CONFIG = 0x050116AAull;
+
+
+static const uint64_t P9N2_PU_BDF2PE_32_CONFIG = 0x050116ABull;
+
+
+static const uint64_t P9N2_PU_BDF2PE_40_CONFIG = 0x050116ACull;
+
+
+static const uint64_t P9N2_PU_BDF2PE_41_CONFIG = 0x050116ADull;
+
+
+static const uint64_t P9N2_PU_BDF2PE_42_CONFIG = 0x050116AEull;
+
+
+static const uint64_t P9N2_PU_BDF2PE_50_CONFIG = 0x050116AFull;
+
+
+static const uint64_t P9N2__DAT_BDF2PE_51_CONFIG = 0x050116B0ull;
+
+
+static const uint64_t P9N2__DAT_BDF2PE_52_CONFIG = 0x050116B1ull;
+
+
+static const uint64_t P9N2_PEC_BIST = 0x0D03000Bull;
+
+static const uint64_t P9N2_PEC_0_BIST = 0x0D03000Bull;
+
+static const uint64_t P9N2_PEC_1_BIST = 0x0E03000Bull;
+
+static const uint64_t P9N2_PEC_2_BIST = 0x0F03000Bull;
+
+
+static const uint64_t P9N2_CAPP_CAPP_EPOCH_AND_RECOVERY_TMR_CONTROL = 0x0201082Cull;
+
+static const uint64_t P9N2_CAPP_0_CAPP_EPOCH_AND_RECOVERY_TMR_CONTROL = 0x0201082Cull;
+
+static const uint64_t P9N2_CAPP_1_CAPP_EPOCH_AND_RECOVERY_TMR_CONTROL = 0x0401082Cull;
+
+
+static const uint64_t P9N2_CAPP_CAPP_ERR_STATUS_CONTROL = 0x0201080Eull;
+
+static const uint64_t P9N2_CAPP_0_CAPP_ERR_STATUS_CONTROL = 0x0201080Eull;
+
+static const uint64_t P9N2_CAPP_1_CAPP_ERR_STATUS_CONTROL = 0x0401080Eull;
+
+
+static const uint64_t P9N2_PEC_CC_ATOMIC_LOCK_REG = 0x0D0303FFull;
+
+static const uint64_t P9N2_PEC_0_CC_ATOMIC_LOCK_REG = 0x0D0303FFull;
+
+static const uint64_t P9N2_PEC_1_CC_ATOMIC_LOCK_REG = 0x0E0303FFull;
+
+static const uint64_t P9N2_PEC_2_CC_ATOMIC_LOCK_REG = 0x0F0303FFull;
+
+
+static const uint64_t P9N2_PEC_CC_PROTECT_MODE_REG = 0x0D0303FEull;
+
+static const uint64_t P9N2_PEC_0_CC_PROTECT_MODE_REG = 0x0D0303FEull;
+
+static const uint64_t P9N2_PEC_1_CC_PROTECT_MODE_REG = 0x0E0303FEull;
+
+static const uint64_t P9N2_PEC_2_CC_PROTECT_MODE_REG = 0x0F0303FEull;
+
+
+static const uint64_t P9N2_NV_1_CERR_ECC_FIRST = 0x050110F6ull;
+
+static const uint64_t P9N2_NV_5_CERR_ECC_FIRST = 0x050114F6ull;
+
+static const uint64_t P9N2_PU_NPU2_NTL1_CERR_ECC_FIRST = 0x050112F6ull;
+
+
+static const uint64_t P9N2_NV_1_CERR_ECC_HOLD = 0x050110F4ull;
+
+static const uint64_t P9N2_NV_5_CERR_ECC_HOLD = 0x050114F4ull;
+
+static const uint64_t P9N2_PU_NPU2_NTL1_CERR_ECC_HOLD = 0x050112F4ull;
+
+
+static const uint64_t P9N2_NV_1_CERR_ECC_MASK = 0x050110F5ull;
+
+static const uint64_t P9N2_NV_5_CERR_ECC_MASK = 0x050114F5ull;
+
+static const uint64_t P9N2_PU_NPU2_NTL1_CERR_ECC_MASK = 0x050112F5ull;
+
+
+static const uint64_t P9N2_NV_CERR_FIRST0 = 0x050110DAull;
+
+static const uint64_t P9N2_NV_0_CERR_FIRST0 = 0x050110DAull;
+
+static const uint64_t P9N2_NV_4_CERR_FIRST0 = 0x050114DAull;
+
+static const uint64_t P9N2_PU_NPU0_CERR_FIRST0 = 0x050110A7ull;
+
+static const uint64_t P9N2_PU_NPU2_CERR_FIRST0 = 0x050112A7ull;
+
+static const uint64_t P9N2_PU_NPU0_SM0_CERR_FIRST0 = 0x05011017ull;
+
+static const uint64_t P9N2_PU_NPU0_SM2_CERR_FIRST0 = 0x05011047ull;
+
+static const uint64_t P9N2_PU_NPU0_SM3_CERR_FIRST0 = 0x05011077ull;
+
+static const uint64_t P9N2_PU_NPU2_NTL0_CERR_FIRST0 = 0x050112DAull;
+
+static const uint64_t P9N2_PU_NPU2_SM0_CERR_FIRST0 = 0x05011217ull;
+
+static const uint64_t P9N2_PU_NPU2_SM2_CERR_FIRST0 = 0x05011247ull;
+
+static const uint64_t P9N2_PU_NPU2_SM3_CERR_FIRST0 = 0x05011277ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_CERR_FIRST0 = 0x050114A7ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0 = 0x05011417ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0 = 0x05011447ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0 = 0x05011477ull;
+
+
+static const uint64_t P9N2_NV_CERR_FIRST1 = 0x050110DBull;
+
+static const uint64_t P9N2_NV_0_CERR_FIRST1 = 0x050110DBull;
+
+static const uint64_t P9N2_NV_4_CERR_FIRST1 = 0x050114DBull;
+
+static const uint64_t P9N2_PU_NPU0_CERR_FIRST1 = 0x050110A8ull;
+
+static const uint64_t P9N2_PU_NPU2_CERR_FIRST1 = 0x050112A8ull;
+
+static const uint64_t P9N2_PU_NPU0_SM0_CERR_FIRST1 = 0x05011018ull;
+
+static const uint64_t P9N2_PU_NPU0_SM2_CERR_FIRST1 = 0x05011048ull;
+
+static const uint64_t P9N2_PU_NPU0_SM3_CERR_FIRST1 = 0x05011078ull;
+
+static const uint64_t P9N2_PU_NPU1_SM0_CERR_FIRST1 = 0x05011114ull;
+
+static const uint64_t P9N2_PU_NPU1_SM1_CERR_FIRST1 = 0x05011134ull;
+
+static const uint64_t P9N2_PU_NPU2_NTL0_CERR_FIRST1 = 0x050112DBull;
+
+static const uint64_t P9N2_PU_NPU2_SM0_CERR_FIRST1 = 0x05011218ull;
+
+static const uint64_t P9N2_PU_NPU2_SM2_CERR_FIRST1 = 0x05011248ull;
+
+static const uint64_t P9N2_PU_NPU2_SM3_CERR_FIRST1 = 0x05011278ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_CERR_FIRST1 = 0x050114A8ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1 = 0x05011418ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1 = 0x05011448ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1 = 0x05011478ull;
+
+static const uint64_t P9N2_PU_NPU_SM0_CERR_FIRST1 = 0x05011314ull;
+
+static const uint64_t P9N2_PU_NPU_SM1_CERR_FIRST1 = 0x05011334ull;
+
+static const uint64_t P9N2__SM0_CERR_FIRST1 = 0x05011514ull;
+
+static const uint64_t P9N2__SM1_CERR_FIRST1 = 0x05011534ull;
+
+
+static const uint64_t P9N2_PU_NPU0_CERR_FIRST2 = 0x050110A9ull;
+
+static const uint64_t P9N2_PU_NPU2_CERR_FIRST2 = 0x050112A9ull;
+
+static const uint64_t P9N2_PU_NPU0_SM0_CERR_FIRST2 = 0x05011019ull;
+
+static const uint64_t P9N2_PU_NPU0_SM2_CERR_FIRST2 = 0x05011049ull;
+
+static const uint64_t P9N2_PU_NPU0_SM3_CERR_FIRST2 = 0x05011079ull;
+
+static const uint64_t P9N2_PU_NPU1_SM0_CERR_FIRST2 = 0x05011118ull;
+
+static const uint64_t P9N2_PU_NPU1_SM1_CERR_FIRST2 = 0x05011138ull;
+
+static const uint64_t P9N2_PU_NPU2_SM0_CERR_FIRST2 = 0x05011219ull;
+
+static const uint64_t P9N2_PU_NPU2_SM2_CERR_FIRST2 = 0x05011249ull;
+
+static const uint64_t P9N2_PU_NPU2_SM3_CERR_FIRST2 = 0x05011279ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_CERR_FIRST2 = 0x050114A9ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2 = 0x05011419ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2 = 0x05011449ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2 = 0x05011479ull;
+
+static const uint64_t P9N2_PU_NPU_SM0_CERR_FIRST2 = 0x05011318ull;
+
+static const uint64_t P9N2_PU_NPU_SM1_CERR_FIRST2 = 0x05011338ull;
+
+static const uint64_t P9N2__SM0_CERR_FIRST2 = 0x05011518ull;
+
+static const uint64_t P9N2__SM1_CERR_FIRST2 = 0x05011538ull;
+
+
+static const uint64_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1 = 0x05011115ull;
+
+static const uint64_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1 = 0x05011135ull;
+
+static const uint64_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1 = 0x05011315ull;
+
+static const uint64_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1 = 0x05011335ull;
+
+static const uint64_t P9N2__SM0_CERR_FIRST_MASK1 = 0x05011515ull;
+
+static const uint64_t P9N2__SM1_CERR_FIRST_MASK1 = 0x05011535ull;
+
+
+static const uint64_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2 = 0x05011119ull;
+
+static const uint64_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2 = 0x05011139ull;
+
+static const uint64_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2 = 0x05011319ull;
+
+static const uint64_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2 = 0x05011339ull;
+
+static const uint64_t P9N2__SM0_CERR_FIRST_MASK2 = 0x05011519ull;
+
+static const uint64_t P9N2__SM1_CERR_FIRST_MASK2 = 0x05011539ull;
+
+
+static const uint64_t P9N2_NV_CERR_HOLD0 = 0x050110DEull;
+
+static const uint64_t P9N2_NV_0_CERR_HOLD0 = 0x050110DEull;
+
+static const uint64_t P9N2_NV_4_CERR_HOLD0 = 0x050114DEull;
+
+static const uint64_t P9N2_PU_NPU0_CERR_HOLD0 = 0x050110ADull;
+
+static const uint64_t P9N2_PU_NPU2_CERR_HOLD0 = 0x050112ADull;
+
+static const uint64_t P9N2_PU_NPU0_SM0_CERR_HOLD0 = 0x0501101Dull;
+
+static const uint64_t P9N2_PU_NPU0_SM2_CERR_HOLD0 = 0x0501104Dull;
+
+static const uint64_t P9N2_PU_NPU0_SM3_CERR_HOLD0 = 0x0501107Dull;
+
+static const uint64_t P9N2_PU_NPU2_NTL0_CERR_HOLD0 = 0x050112DEull;
+
+static const uint64_t P9N2_PU_NPU2_SM0_CERR_HOLD0 = 0x0501121Dull;
+
+static const uint64_t P9N2_PU_NPU2_SM2_CERR_HOLD0 = 0x0501124Dull;
+
+static const uint64_t P9N2_PU_NPU2_SM3_CERR_HOLD0 = 0x0501127Dull;
+
+static const uint64_t P9N2_PU_NPU_MSC_CERR_HOLD0 = 0x050114ADull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0 = 0x0501141Dull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0 = 0x0501144Dull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0 = 0x0501147Dull;
+
+
+static const uint64_t P9N2_NV_CERR_HOLD1 = 0x050110DFull;
+
+static const uint64_t P9N2_NV_0_CERR_HOLD1 = 0x050110DFull;
+
+static const uint64_t P9N2_NV_4_CERR_HOLD1 = 0x050114DFull;
+
+static const uint64_t P9N2_PU_NPU0_CERR_HOLD1 = 0x050110AEull;
+
+static const uint64_t P9N2_PU_NPU2_CERR_HOLD1 = 0x050112AEull;
+
+static const uint64_t P9N2_PU_NPU0_SM0_CERR_HOLD1 = 0x0501101Eull;
+
+static const uint64_t P9N2_PU_NPU0_SM2_CERR_HOLD1 = 0x0501104Eull;
+
+static const uint64_t P9N2_PU_NPU0_SM3_CERR_HOLD1 = 0x0501107Eull;
+
+static const uint64_t P9N2_PU_NPU1_SM0_CERR_HOLD1 = 0x05011112ull;
+
+static const uint64_t P9N2_PU_NPU1_SM1_CERR_HOLD1 = 0x05011132ull;
+
+static const uint64_t P9N2_PU_NPU2_NTL0_CERR_HOLD1 = 0x050112DFull;
+
+static const uint64_t P9N2_PU_NPU2_SM0_CERR_HOLD1 = 0x0501121Eull;
+
+static const uint64_t P9N2_PU_NPU2_SM2_CERR_HOLD1 = 0x0501124Eull;
+
+static const uint64_t P9N2_PU_NPU2_SM3_CERR_HOLD1 = 0x0501127Eull;
+
+static const uint64_t P9N2_PU_NPU_MSC_CERR_HOLD1 = 0x050114AEull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1 = 0x0501141Eull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1 = 0x0501144Eull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1 = 0x0501147Eull;
+
+static const uint64_t P9N2_PU_NPU_SM0_CERR_HOLD1 = 0x05011312ull;
+
+static const uint64_t P9N2_PU_NPU_SM1_CERR_HOLD1 = 0x05011332ull;
+
+static const uint64_t P9N2__SM0_CERR_HOLD1 = 0x05011512ull;
+
+static const uint64_t P9N2__SM1_CERR_HOLD1 = 0x05011532ull;
+
+
+static const uint64_t P9N2_PU_NPU0_CERR_HOLD2 = 0x050110AFull;
+
+static const uint64_t P9N2_PU_NPU2_CERR_HOLD2 = 0x050112AFull;
+
+static const uint64_t P9N2_PU_NPU0_SM0_CERR_HOLD2 = 0x0501101Full;
+
+static const uint64_t P9N2_PU_NPU0_SM2_CERR_HOLD2 = 0x0501104Full;
+
+static const uint64_t P9N2_PU_NPU0_SM3_CERR_HOLD2 = 0x0501107Full;
+
+static const uint64_t P9N2_PU_NPU1_SM0_CERR_HOLD2 = 0x05011116ull;
+
+static const uint64_t P9N2_PU_NPU1_SM1_CERR_HOLD2 = 0x05011136ull;
+
+static const uint64_t P9N2_PU_NPU2_SM0_CERR_HOLD2 = 0x0501121Full;
+
+static const uint64_t P9N2_PU_NPU2_SM2_CERR_HOLD2 = 0x0501124Full;
+
+static const uint64_t P9N2_PU_NPU2_SM3_CERR_HOLD2 = 0x0501127Full;
+
+static const uint64_t P9N2_PU_NPU_MSC_CERR_HOLD2 = 0x050114AFull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2 = 0x0501141Full;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2 = 0x0501144Full;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2 = 0x0501147Full;
+
+static const uint64_t P9N2_PU_NPU_SM0_CERR_HOLD2 = 0x05011316ull;
+
+static const uint64_t P9N2_PU_NPU_SM1_CERR_HOLD2 = 0x05011336ull;
+
+static const uint64_t P9N2__SM0_CERR_HOLD2 = 0x05011516ull;
+
+static const uint64_t P9N2__SM1_CERR_HOLD2 = 0x05011536ull;
+
+
+static const uint64_t P9N2_NV_1_CERR_LOG_FIRST = 0x050110FCull;
+
+static const uint64_t P9N2_NV_5_CERR_LOG_FIRST = 0x050114FCull;
+
+static const uint64_t P9N2_PU_NPU2_NTL1_CERR_LOG_FIRST = 0x050112FCull;
+
+
+static const uint64_t P9N2_NV_1_CERR_LOG_HOLD = 0x050110FAull;
+
+static const uint64_t P9N2_NV_5_CERR_LOG_HOLD = 0x050114FAull;
+
+static const uint64_t P9N2_PU_NPU2_NTL1_CERR_LOG_HOLD = 0x050112FAull;
+
+
+static const uint64_t P9N2_NV_1_CERR_LOG_MASK = 0x050110FBull;
+
+static const uint64_t P9N2_NV_5_CERR_LOG_MASK = 0x050114FBull;
+
+static const uint64_t P9N2_PU_NPU2_NTL1_CERR_LOG_MASK = 0x050112FBull;
+
+
+static const uint64_t P9N2_NV_CERR_MASK0 = 0x050110DCull;
+
+static const uint64_t P9N2_NV_0_CERR_MASK0 = 0x050110DCull;
+
+static const uint64_t P9N2_NV_4_CERR_MASK0 = 0x050114DCull;
+
+static const uint64_t P9N2_PU_NPU0_CERR_MASK0 = 0x050110AAull;
+
+static const uint64_t P9N2_PU_NPU2_CERR_MASK0 = 0x050112AAull;
+
+static const uint64_t P9N2_PU_NPU0_SM0_CERR_MASK0 = 0x0501101Aull;
+
+static const uint64_t P9N2_PU_NPU0_SM2_CERR_MASK0 = 0x0501104Aull;
+
+static const uint64_t P9N2_PU_NPU0_SM3_CERR_MASK0 = 0x0501107Aull;
+
+static const uint64_t P9N2_PU_NPU2_NTL0_CERR_MASK0 = 0x050112DCull;
+
+static const uint64_t P9N2_PU_NPU2_SM0_CERR_MASK0 = 0x0501121Aull;
+
+static const uint64_t P9N2_PU_NPU2_SM2_CERR_MASK0 = 0x0501124Aull;
+
+static const uint64_t P9N2_PU_NPU2_SM3_CERR_MASK0 = 0x0501127Aull;
+
+static const uint64_t P9N2_PU_NPU_MSC_CERR_MASK0 = 0x050114AAull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0 = 0x0501141Aull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0 = 0x0501144Aull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0 = 0x0501147Aull;
+
+
+static const uint64_t P9N2_NV_CERR_MASK1 = 0x050110DDull;
+
+static const uint64_t P9N2_NV_0_CERR_MASK1 = 0x050110DDull;
+
+static const uint64_t P9N2_NV_4_CERR_MASK1 = 0x050114DDull;
+
+static const uint64_t P9N2_PU_NPU0_CERR_MASK1 = 0x050110ABull;
+
+static const uint64_t P9N2_PU_NPU2_CERR_MASK1 = 0x050112ABull;
+
+static const uint64_t P9N2_PU_NPU0_SM0_CERR_MASK1 = 0x0501101Bull;
+
+static const uint64_t P9N2_PU_NPU0_SM2_CERR_MASK1 = 0x0501104Bull;
+
+static const uint64_t P9N2_PU_NPU0_SM3_CERR_MASK1 = 0x0501107Bull;
+
+static const uint64_t P9N2_PU_NPU1_SM0_CERR_MASK1 = 0x05011113ull;
+
+static const uint64_t P9N2_PU_NPU1_SM1_CERR_MASK1 = 0x05011133ull;
+
+static const uint64_t P9N2_PU_NPU2_NTL0_CERR_MASK1 = 0x050112DDull;
+
+static const uint64_t P9N2_PU_NPU2_SM0_CERR_MASK1 = 0x0501121Bull;
+
+static const uint64_t P9N2_PU_NPU2_SM2_CERR_MASK1 = 0x0501124Bull;
+
+static const uint64_t P9N2_PU_NPU2_SM3_CERR_MASK1 = 0x0501127Bull;
+
+static const uint64_t P9N2_PU_NPU_MSC_CERR_MASK1 = 0x050114ABull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1 = 0x0501141Bull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1 = 0x0501144Bull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1 = 0x0501147Bull;
+
+static const uint64_t P9N2_PU_NPU_SM0_CERR_MASK1 = 0x05011313ull;
+
+static const uint64_t P9N2_PU_NPU_SM1_CERR_MASK1 = 0x05011333ull;
+
+static const uint64_t P9N2__SM0_CERR_MASK1 = 0x05011513ull;
+
+static const uint64_t P9N2__SM1_CERR_MASK1 = 0x05011533ull;
+
+
+static const uint64_t P9N2_PU_NPU0_CERR_MASK2 = 0x050110ACull;
+
+static const uint64_t P9N2_PU_NPU2_CERR_MASK2 = 0x050112ACull;
+
+static const uint64_t P9N2_PU_NPU0_SM0_CERR_MASK2 = 0x0501101Cull;
+
+static const uint64_t P9N2_PU_NPU0_SM2_CERR_MASK2 = 0x0501104Cull;
+
+static const uint64_t P9N2_PU_NPU0_SM3_CERR_MASK2 = 0x0501107Cull;
+
+static const uint64_t P9N2_PU_NPU1_SM0_CERR_MASK2 = 0x05011117ull;
+
+static const uint64_t P9N2_PU_NPU1_SM1_CERR_MASK2 = 0x05011137ull;
+
+static const uint64_t P9N2_PU_NPU2_SM0_CERR_MASK2 = 0x0501121Cull;
+
+static const uint64_t P9N2_PU_NPU2_SM2_CERR_MASK2 = 0x0501124Cull;
+
+static const uint64_t P9N2_PU_NPU2_SM3_CERR_MASK2 = 0x0501127Cull;
+
+static const uint64_t P9N2_PU_NPU_MSC_CERR_MASK2 = 0x050114ACull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2 = 0x0501141Cull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2 = 0x0501144Cull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2 = 0x0501147Cull;
+
+static const uint64_t P9N2_PU_NPU_SM0_CERR_MASK2 = 0x05011317ull;
+
+static const uint64_t P9N2_PU_NPU_SM1_CERR_MASK2 = 0x05011337ull;
+
+static const uint64_t P9N2__SM0_CERR_MASK2 = 0x05011517ull;
+
+static const uint64_t P9N2__SM1_CERR_MASK2 = 0x05011537ull;
+
+
+static const uint64_t P9N2_NV_CERR_MESSAGE0 = 0x050110D8ull;
+
+static const uint64_t P9N2_NV_0_CERR_MESSAGE0 = 0x050110D8ull;
+
+static const uint64_t P9N2_NV_4_CERR_MESSAGE0 = 0x050114D8ull;
+
+static const uint64_t P9N2_PU_NPU0_CERR_MESSAGE0 = 0x050110A1ull;
+
+static const uint64_t P9N2_PU_NPU2_CERR_MESSAGE0 = 0x050112A1ull;
+
+static const uint64_t P9N2_PU_NPU0_SM0_CERR_MESSAGE0 = 0x05011011ull;
+
+static const uint64_t P9N2_PU_NPU0_SM2_CERR_MESSAGE0 = 0x05011041ull;
+
+static const uint64_t P9N2_PU_NPU0_SM3_CERR_MESSAGE0 = 0x05011071ull;
+
+static const uint64_t P9N2_PU_NPU2_NTL0_CERR_MESSAGE0 = 0x050112D8ull;
+
+static const uint64_t P9N2_PU_NPU2_SM0_CERR_MESSAGE0 = 0x05011211ull;
+
+static const uint64_t P9N2_PU_NPU2_SM2_CERR_MESSAGE0 = 0x05011241ull;
+
+static const uint64_t P9N2_PU_NPU2_SM3_CERR_MESSAGE0 = 0x05011271ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_CERR_MESSAGE0 = 0x050114A1ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM0_CERR_MESSAGE0 = 0x05011411ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM2_CERR_MESSAGE0 = 0x05011441ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM3_CERR_MESSAGE0 = 0x05011471ull;
+
+
+static const uint64_t P9N2_NV_CERR_MESSAGE1 = 0x050110D9ull;
+
+static const uint64_t P9N2_NV_0_CERR_MESSAGE1 = 0x050110D9ull;
+
+static const uint64_t P9N2_NV_4_CERR_MESSAGE1 = 0x050114D9ull;
+
+static const uint64_t P9N2_PU_NPU0_CERR_MESSAGE1 = 0x050110A2ull;
+
+static const uint64_t P9N2_PU_NPU2_CERR_MESSAGE1 = 0x050112A2ull;
+
+static const uint64_t P9N2_PU_NPU0_SM0_CERR_MESSAGE1 = 0x05011012ull;
+
+static const uint64_t P9N2_PU_NPU0_SM2_CERR_MESSAGE1 = 0x05011042ull;
+
+static const uint64_t P9N2_PU_NPU0_SM3_CERR_MESSAGE1 = 0x05011072ull;
+
+static const uint64_t P9N2_PU_NPU2_NTL0_CERR_MESSAGE1 = 0x050112D9ull;
+
+static const uint64_t P9N2_PU_NPU2_SM0_CERR_MESSAGE1 = 0x05011212ull;
+
+static const uint64_t P9N2_PU_NPU2_SM2_CERR_MESSAGE1 = 0x05011242ull;
+
+static const uint64_t P9N2_PU_NPU2_SM3_CERR_MESSAGE1 = 0x05011272ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_CERR_MESSAGE1 = 0x050114A2ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM0_CERR_MESSAGE1 = 0x05011412ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM2_CERR_MESSAGE1 = 0x05011442ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM3_CERR_MESSAGE1 = 0x05011472ull;
+
+
+static const uint64_t P9N2_PU_NPU0_CERR_MESSAGE2 = 0x050110A3ull;
+
+static const uint64_t P9N2_PU_NPU2_CERR_MESSAGE2 = 0x050112A3ull;
+
+static const uint64_t P9N2_PU_NPU0_SM0_CERR_MESSAGE2 = 0x05011013ull;
+
+static const uint64_t P9N2_PU_NPU0_SM2_CERR_MESSAGE2 = 0x05011043ull;
+
+static const uint64_t P9N2_PU_NPU0_SM3_CERR_MESSAGE2 = 0x05011073ull;
+
+static const uint64_t P9N2_PU_NPU2_SM0_CERR_MESSAGE2 = 0x05011213ull;
+
+static const uint64_t P9N2_PU_NPU2_SM2_CERR_MESSAGE2 = 0x05011243ull;
+
+static const uint64_t P9N2_PU_NPU2_SM3_CERR_MESSAGE2 = 0x05011273ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_CERR_MESSAGE2 = 0x050114A3ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM0_CERR_MESSAGE2 = 0x05011413ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM2_CERR_MESSAGE2 = 0x05011443ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM3_CERR_MESSAGE2 = 0x05011473ull;
+
+
+static const uint64_t P9N2_PU_NPU0_CERR_MESSAGE3 = 0x050110A4ull;
+
+static const uint64_t P9N2_PU_NPU2_CERR_MESSAGE3 = 0x050112A4ull;
+
+static const uint64_t P9N2_PU_NPU0_SM0_CERR_MESSAGE3 = 0x05011014ull;
+
+static const uint64_t P9N2_PU_NPU0_SM2_CERR_MESSAGE3 = 0x05011044ull;
+
+static const uint64_t P9N2_PU_NPU0_SM3_CERR_MESSAGE3 = 0x05011074ull;
+
+static const uint64_t P9N2_PU_NPU2_SM0_CERR_MESSAGE3 = 0x05011214ull;
+
+static const uint64_t P9N2_PU_NPU2_SM2_CERR_MESSAGE3 = 0x05011244ull;
+
+static const uint64_t P9N2_PU_NPU2_SM3_CERR_MESSAGE3 = 0x05011274ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_CERR_MESSAGE3 = 0x050114A4ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM0_CERR_MESSAGE3 = 0x05011414ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM2_CERR_MESSAGE3 = 0x05011444ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM3_CERR_MESSAGE3 = 0x05011474ull;
+
+
+static const uint64_t P9N2_PU_NPU0_CERR_MESSAGE4 = 0x050110A5ull;
+
+static const uint64_t P9N2_PU_NPU2_CERR_MESSAGE4 = 0x050112A5ull;
+
+static const uint64_t P9N2_PU_NPU0_SM0_CERR_MESSAGE4 = 0x05011015ull;
+
+static const uint64_t P9N2_PU_NPU0_SM2_CERR_MESSAGE4 = 0x05011045ull;
+
+static const uint64_t P9N2_PU_NPU0_SM3_CERR_MESSAGE4 = 0x05011075ull;
+
+static const uint64_t P9N2_PU_NPU2_SM0_CERR_MESSAGE4 = 0x05011215ull;
+
+static const uint64_t P9N2_PU_NPU2_SM2_CERR_MESSAGE4 = 0x05011245ull;
+
+static const uint64_t P9N2_PU_NPU2_SM3_CERR_MESSAGE4 = 0x05011275ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_CERR_MESSAGE4 = 0x050114A5ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM0_CERR_MESSAGE4 = 0x05011415ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM2_CERR_MESSAGE4 = 0x05011445ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM3_CERR_MESSAGE4 = 0x05011475ull;
+
+
+static const uint64_t P9N2_PU_NPU0_CTL_CERR_MESSAGE5 = 0x05011085ull;
+
+static const uint64_t P9N2_PU_NPU0_DAT_CERR_MESSAGE5 = 0x050110B5ull;
+
+static const uint64_t P9N2_PU_NPU2_CTL_CERR_MESSAGE5 = 0x05011285ull;
+
+static const uint64_t P9N2_PU_NPU2_DAT_CERR_MESSAGE5 = 0x050112B5ull;
+
+static const uint64_t P9N2_PU_NPU0_SM1_CERR_MESSAGE5 = 0x05011025ull;
+
+static const uint64_t P9N2_PU_NPU0_SM2_CERR_MESSAGE5 = 0x05011055ull;
+
+static const uint64_t P9N2_PU_NPU2_SM1_CERR_MESSAGE5 = 0x05011225ull;
+
+static const uint64_t P9N2_PU_NPU2_SM2_CERR_MESSAGE5 = 0x05011255ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_CTL_CERR_MESSAGE5 = 0x05011485ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_DAT_CERR_MESSAGE5 = 0x050114B5ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM1_CERR_MESSAGE5 = 0x05011425ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM2_CERR_MESSAGE5 = 0x05011455ull;
+
+
+static const uint64_t P9N2_PU_NPU0_CTL_CERR_MESSAGE6 = 0x05011086ull;
+
+static const uint64_t P9N2_PU_NPU0_DAT_CERR_MESSAGE6 = 0x050110B6ull;
+
+static const uint64_t P9N2_PU_NPU2_CTL_CERR_MESSAGE6 = 0x05011286ull;
+
+static const uint64_t P9N2_PU_NPU2_DAT_CERR_MESSAGE6 = 0x050112B6ull;
+
+static const uint64_t P9N2_PU_NPU0_SM1_CERR_MESSAGE6 = 0x05011026ull;
+
+static const uint64_t P9N2_PU_NPU0_SM2_CERR_MESSAGE6 = 0x05011056ull;
+
+static const uint64_t P9N2_PU_NPU2_SM1_CERR_MESSAGE6 = 0x05011226ull;
+
+static const uint64_t P9N2_PU_NPU2_SM2_CERR_MESSAGE6 = 0x05011256ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_CTL_CERR_MESSAGE6 = 0x05011486ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_DAT_CERR_MESSAGE6 = 0x050114B6ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM1_CERR_MESSAGE6 = 0x05011426ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM2_CERR_MESSAGE6 = 0x05011456ull;
+
+
+static const uint64_t P9N2_NV_1_CERR_PTY_FIRST = 0x050110F9ull;
+
+static const uint64_t P9N2_NV_5_CERR_PTY_FIRST = 0x050114F9ull;
+
+static const uint64_t P9N2_PU_NPU2_NTL1_CERR_PTY_FIRST = 0x050112F9ull;
+
+
+static const uint64_t P9N2_NV_1_CERR_PTY_HOLD = 0x050110F7ull;
+
+static const uint64_t P9N2_NV_5_CERR_PTY_HOLD = 0x050114F7ull;
+
+static const uint64_t P9N2_PU_NPU2_NTL1_CERR_PTY_HOLD = 0x050112F7ull;
+
+
+static const uint64_t P9N2_NV_1_CERR_PTY_MASK = 0x050110F8ull;
+
+static const uint64_t P9N2_NV_5_CERR_PTY_MASK = 0x050114F8ull;
+
+static const uint64_t P9N2_PU_NPU2_NTL1_CERR_PTY_MASK = 0x050112F8ull;
+
+
+static const uint64_t P9N2_PEC_0_STACK0_CERR_RPT0_REG = 0x04010C4Aull;
+
+static const uint64_t P9N2_PEC_1_STACK0_CERR_RPT0_REG = 0x0401104Aull;
+
+static const uint64_t P9N2_PEC_1_STACK1_CERR_RPT0_REG = 0x0401108Aull;
+
+static const uint64_t P9N2_PEC_1_STACK2_CERR_RPT0_REG = 0x040110CAull;
+
+static const uint64_t P9N2_PEC_2_STACK0_CERR_RPT0_REG = 0x0401144Aull;
+
+static const uint64_t P9N2_PEC_2_STACK1_CERR_RPT0_REG = 0x0401148Aull;
+
+static const uint64_t P9N2_PEC_2_STACK2_CERR_RPT0_REG = 0x040114CAull;
+
+static const uint64_t P9N2_PEC_STACK0_CERR_RPT0_REG = 0x04010C4Aull;
+
+static const uint64_t P9N2_PHB_CERR_RPT0_REG = 0x04010C4Aull;
+
+static const uint64_t P9N2_PHB_0_CERR_RPT0_REG = 0x04010C4Aull;
+
+static const uint64_t P9N2_PHB_1_CERR_RPT0_REG = 0x0401104Aull;
+
+static const uint64_t P9N2_PHB_2_CERR_RPT0_REG = 0x0401108Aull;
+
+static const uint64_t P9N2_PHB_3_CERR_RPT0_REG = 0x0401144Aull;
+
+static const uint64_t P9N2_PHB_4_CERR_RPT0_REG = 0x0401148Aull;
+
+static const uint64_t P9N2_PHB_5_CERR_RPT0_REG = 0x040114CAull;
+
+
+static const uint64_t P9N2_PEC_0_STACK0_CERR_RPT1_REG = 0x04010C4Bull;
+
+static const uint64_t P9N2_PEC_1_STACK0_CERR_RPT1_REG = 0x0401104Bull;
+
+static const uint64_t P9N2_PEC_1_STACK1_CERR_RPT1_REG = 0x0401108Bull;
+
+static const uint64_t P9N2_PEC_1_STACK2_CERR_RPT1_REG = 0x040110CBull;
+
+static const uint64_t P9N2_PEC_2_STACK0_CERR_RPT1_REG = 0x0401144Bull;
+
+static const uint64_t P9N2_PEC_2_STACK1_CERR_RPT1_REG = 0x0401148Bull;
+
+static const uint64_t P9N2_PEC_2_STACK2_CERR_RPT1_REG = 0x040114CBull;
+
+static const uint64_t P9N2_PEC_STACK0_CERR_RPT1_REG = 0x04010C4Bull;
+
+static const uint64_t P9N2_PHB_CERR_RPT1_REG = 0x04010C4Bull;
+
+static const uint64_t P9N2_PHB_0_CERR_RPT1_REG = 0x04010C4Bull;
+
+static const uint64_t P9N2_PHB_1_CERR_RPT1_REG = 0x0401104Bull;
+
+static const uint64_t P9N2_PHB_2_CERR_RPT1_REG = 0x0401108Bull;
+
+static const uint64_t P9N2_PHB_3_CERR_RPT1_REG = 0x0401144Bull;
+
+static const uint64_t P9N2_PHB_4_CERR_RPT1_REG = 0x0401148Bull;
+
+static const uint64_t P9N2_PHB_5_CERR_RPT1_REG = 0x040114CBull;
+
+
+static const uint64_t P9N2_PU_NPU_CTL_CHKSW0 = 0x05011381ull;
+
+static const uint64_t P9N2_PU_NPU_SM2_CHKSW0 = 0x05011351ull;
+
+static const uint64_t P9N2__CTL_CHKSW0 = 0x05011581ull;
+
+static const uint64_t P9N2__SM2_CHKSW0 = 0x05011551ull;
+
+
+static const uint64_t P9N2_PEC_CLK_REGION = 0x0D030006ull;
+
+static const uint64_t P9N2_PEC_0_CLK_REGION = 0x0D030006ull;
+
+static const uint64_t P9N2_PEC_1_CLK_REGION = 0x0E030006ull;
+
+static const uint64_t P9N2_PEC_2_CLK_REGION = 0x0F030006ull;
+
+
+static const uint64_t P9N2_PEC_CLOCK_STAT_ARY = 0x0D03000Aull;
+
+static const uint64_t P9N2_PEC_0_CLOCK_STAT_ARY = 0x0D03000Aull;
+
+static const uint64_t P9N2_PEC_1_CLOCK_STAT_ARY = 0x0E03000Aull;
+
+static const uint64_t P9N2_PEC_2_CLOCK_STAT_ARY = 0x0F03000Aull;
+
+
+static const uint64_t P9N2_PEC_CLOCK_STAT_NSL = 0x0D030009ull;
+
+static const uint64_t P9N2_PEC_0_CLOCK_STAT_NSL = 0x0D030009ull;
+
+static const uint64_t P9N2_PEC_1_CLOCK_STAT_NSL = 0x0E030009ull;
+
+static const uint64_t P9N2_PEC_2_CLOCK_STAT_NSL = 0x0F030009ull;
+
+
+static const uint64_t P9N2_PEC_CLOCK_STAT_SL = 0x0D030008ull;
+
+static const uint64_t P9N2_PEC_0_CLOCK_STAT_SL = 0x0D030008ull;
+
+static const uint64_t P9N2_PEC_1_CLOCK_STAT_SL = 0x0E030008ull;
+
+static const uint64_t P9N2_PEC_2_CLOCK_STAT_SL = 0x0F030008ull;
+
+
+static const uint64_t P9N2_PU_CME0_CME_LCL_DBG_PPE = 0x109010120ull;
+
+static const uint64_t P9N2_PU_CME0_CME_LCL_DBG_PPE1 = 0x109010138ull;
+
+static const uint64_t P9N2_PU_CME0_CME_LCL_DBG_PPE2 = 0x109010130ull;
+
+static const uint64_t P9N2_PU_CME1_CME_LCL_DBG_PPE = 0x109020120ull;
+
+static const uint64_t P9N2_PU_CME1_CME_LCL_DBG_PPE1 = 0x109020138ull;
+
+static const uint64_t P9N2_PU_CME1_CME_LCL_DBG_PPE2 = 0x109020130ull;
+
+static const uint64_t P9N2_PU_CME2_CME_LCL_DBG_PPE = 0x10A010120ull;
+
+static const uint64_t P9N2_PU_CME2_CME_LCL_DBG_PPE1 = 0x10A010138ull;
+
+static const uint64_t P9N2_PU_CME2_CME_LCL_DBG_PPE2 = 0x10A010130ull;
+
+static const uint64_t P9N2_PU_CME3_CME_LCL_DBG_PPE = 0x10A020120ull;
+
+static const uint64_t P9N2_PU_CME3_CME_LCL_DBG_PPE1 = 0x10A020138ull;
+
+static const uint64_t P9N2_PU_CME3_CME_LCL_DBG_PPE2 = 0x10A020130ull;
+
+static const uint64_t P9N2_PU_CME4_CME_LCL_DBG_PPE = 0x10B010120ull;
+
+static const uint64_t P9N2_PU_CME4_CME_LCL_DBG_PPE1 = 0x10B010138ull;
+
+static const uint64_t P9N2_PU_CME4_CME_LCL_DBG_PPE2 = 0x10B010130ull;
+
+static const uint64_t P9N2_PU_CME5_CME_LCL_DBG_PPE = 0x10B020120ull;
+
+static const uint64_t P9N2_PU_CME5_CME_LCL_DBG_PPE1 = 0x10B020138ull;
+
+static const uint64_t P9N2_PU_CME5_CME_LCL_DBG_PPE2 = 0x10B020130ull;
+
+static const uint64_t P9N2_PU_CME6_CME_LCL_DBG_PPE = 0x10C010120ull;
+
+static const uint64_t P9N2_PU_CME6_CME_LCL_DBG_PPE1 = 0x10C010138ull;
+
+static const uint64_t P9N2_PU_CME6_CME_LCL_DBG_PPE2 = 0x10C010130ull;
+
+static const uint64_t P9N2_PU_CME7_CME_LCL_DBG_PPE = 0x10C020120ull;
+
+static const uint64_t P9N2_PU_CME7_CME_LCL_DBG_PPE1 = 0x10C020138ull;
+
+static const uint64_t P9N2_PU_CME7_CME_LCL_DBG_PPE2 = 0x10C020130ull;
+
+static const uint64_t P9N2_PU_CME8_CME_LCL_DBG_PPE = 0x10D010120ull;
+
+static const uint64_t P9N2_PU_CME8_CME_LCL_DBG_PPE1 = 0x10D010138ull;
+
+static const uint64_t P9N2_PU_CME8_CME_LCL_DBG_PPE2 = 0x10D010130ull;
+
+static const uint64_t P9N2_PU_CME9_CME_LCL_DBG_PPE = 0x10D020120ull;
+
+static const uint64_t P9N2_PU_CME9_CME_LCL_DBG_PPE1 = 0x10D020138ull;
+
+static const uint64_t P9N2_PU_CME9_CME_LCL_DBG_PPE2 = 0x10D020130ull;
+
+static const uint64_t P9N2_PU_CME10_CME_LCL_DBG_PPE = 0x10E010120ull;
+
+static const uint64_t P9N2_PU_CME10_CME_LCL_DBG_PPE1 = 0x10E010138ull;
+
+static const uint64_t P9N2_PU_CME10_CME_LCL_DBG_PPE2 = 0x10E010130ull;
+
+static const uint64_t P9N2_PU_CME11_CME_LCL_DBG_PPE = 0x10E020120ull;
+
+static const uint64_t P9N2_PU_CME11_CME_LCL_DBG_PPE1 = 0x10E020138ull;
+
+static const uint64_t P9N2_PU_CME11_CME_LCL_DBG_PPE2 = 0x10E020130ull;
+
+
+static const uint64_t P9N2_PU_CME0_CME_LCL_EIMR_PPE = 0x109010020ull;
+
+static const uint64_t P9N2_PU_CME0_CME_LCL_EIMR_PPE1 = 0x109010038ull;
+
+static const uint64_t P9N2_PU_CME0_CME_LCL_EIMR_PPE2 = 0x109010030ull;
+
+static const uint64_t P9N2_PU_CME1_CME_LCL_EIMR_PPE = 0x109020020ull;
+
+static const uint64_t P9N2_PU_CME1_CME_LCL_EIMR_PPE1 = 0x109020038ull;
+
+static const uint64_t P9N2_PU_CME1_CME_LCL_EIMR_PPE2 = 0x109020030ull;
+
+static const uint64_t P9N2_PU_CME2_CME_LCL_EIMR_PPE = 0x10A010020ull;
+
+static const uint64_t P9N2_PU_CME2_CME_LCL_EIMR_PPE1 = 0x10A010038ull;
+
+static const uint64_t P9N2_PU_CME2_CME_LCL_EIMR_PPE2 = 0x10A010030ull;
+
+static const uint64_t P9N2_PU_CME3_CME_LCL_EIMR_PPE = 0x10A020020ull;
+
+static const uint64_t P9N2_PU_CME3_CME_LCL_EIMR_PPE1 = 0x10A020038ull;
+
+static const uint64_t P9N2_PU_CME3_CME_LCL_EIMR_PPE2 = 0x10A020030ull;
+
+static const uint64_t P9N2_PU_CME4_CME_LCL_EIMR_PPE = 0x10B010020ull;
+
+static const uint64_t P9N2_PU_CME4_CME_LCL_EIMR_PPE1 = 0x10B010038ull;
+
+static const uint64_t P9N2_PU_CME4_CME_LCL_EIMR_PPE2 = 0x10B010030ull;
+
+static const uint64_t P9N2_PU_CME5_CME_LCL_EIMR_PPE = 0x10B020020ull;
+
+static const uint64_t P9N2_PU_CME5_CME_LCL_EIMR_PPE1 = 0x10B020038ull;
+
+static const uint64_t P9N2_PU_CME5_CME_LCL_EIMR_PPE2 = 0x10B020030ull;
+
+static const uint64_t P9N2_PU_CME6_CME_LCL_EIMR_PPE = 0x10C010020ull;
+
+static const uint64_t P9N2_PU_CME6_CME_LCL_EIMR_PPE1 = 0x10C010038ull;
+
+static const uint64_t P9N2_PU_CME6_CME_LCL_EIMR_PPE2 = 0x10C010030ull;
+
+static const uint64_t P9N2_PU_CME7_CME_LCL_EIMR_PPE = 0x10C020020ull;
+
+static const uint64_t P9N2_PU_CME7_CME_LCL_EIMR_PPE1 = 0x10C020038ull;
+
+static const uint64_t P9N2_PU_CME7_CME_LCL_EIMR_PPE2 = 0x10C020030ull;
+
+static const uint64_t P9N2_PU_CME8_CME_LCL_EIMR_PPE = 0x10D010020ull;
+
+static const uint64_t P9N2_PU_CME8_CME_LCL_EIMR_PPE1 = 0x10D010038ull;
+
+static const uint64_t P9N2_PU_CME8_CME_LCL_EIMR_PPE2 = 0x10D010030ull;
+
+static const uint64_t P9N2_PU_CME9_CME_LCL_EIMR_PPE = 0x10D020020ull;
+
+static const uint64_t P9N2_PU_CME9_CME_LCL_EIMR_PPE1 = 0x10D020038ull;
+
+static const uint64_t P9N2_PU_CME9_CME_LCL_EIMR_PPE2 = 0x10D020030ull;
+
+static const uint64_t P9N2_PU_CME10_CME_LCL_EIMR_PPE = 0x10E010020ull;
+
+static const uint64_t P9N2_PU_CME10_CME_LCL_EIMR_PPE1 = 0x10E010038ull;
+
+static const uint64_t P9N2_PU_CME10_CME_LCL_EIMR_PPE2 = 0x10E010030ull;
+
+static const uint64_t P9N2_PU_CME11_CME_LCL_EIMR_PPE = 0x10E020020ull;
+
+static const uint64_t P9N2_PU_CME11_CME_LCL_EIMR_PPE1 = 0x10E020038ull;
+
+static const uint64_t P9N2_PU_CME11_CME_LCL_EIMR_PPE2 = 0x10E020030ull;
+
+
+static const uint64_t P9N2_PU_CME0_CME_LCL_EINR_PPE = 0x1090100A0ull;
+
+static const uint64_t P9N2_PU_CME1_CME_LCL_EINR_PPE = 0x1090200A0ull;
+
+static const uint64_t P9N2_PU_CME2_CME_LCL_EINR_PPE = 0x10A0100A0ull;
+
+static const uint64_t P9N2_PU_CME3_CME_LCL_EINR_PPE = 0x10A0200A0ull;
+
+static const uint64_t P9N2_PU_CME4_CME_LCL_EINR_PPE = 0x10B0100A0ull;
+
+static const uint64_t P9N2_PU_CME5_CME_LCL_EINR_PPE = 0x10B0200A0ull;
+
+static const uint64_t P9N2_PU_CME6_CME_LCL_EINR_PPE = 0x10C0100A0ull;
+
+static const uint64_t P9N2_PU_CME7_CME_LCL_EINR_PPE = 0x10C0200A0ull;
+
+static const uint64_t P9N2_PU_CME8_CME_LCL_EINR_PPE = 0x10D0100A0ull;
+
+static const uint64_t P9N2_PU_CME9_CME_LCL_EINR_PPE = 0x10D0200A0ull;
+
+static const uint64_t P9N2_PU_CME10_CME_LCL_EINR_PPE = 0x10E0100A0ull;
+
+static const uint64_t P9N2_PU_CME11_CME_LCL_EINR_PPE = 0x10E0200A0ull;
+
+
+static const uint64_t P9N2_PU_CME0_CME_LCL_EIPR_PPE = 0x109010040ull;
+
+static const uint64_t P9N2_PU_CME0_CME_LCL_EIPR_PPE1 = 0x109010058ull;
+
+static const uint64_t P9N2_PU_CME0_CME_LCL_EIPR_PPE2 = 0x109010050ull;
+
+static const uint64_t P9N2_PU_CME1_CME_LCL_EIPR_PPE = 0x109020040ull;
+
+static const uint64_t P9N2_PU_CME1_CME_LCL_EIPR_PPE1 = 0x109020058ull;
+
+static const uint64_t P9N2_PU_CME1_CME_LCL_EIPR_PPE2 = 0x109020050ull;
+
+static const uint64_t P9N2_PU_CME2_CME_LCL_EIPR_PPE = 0x10A010040ull;
+
+static const uint64_t P9N2_PU_CME2_CME_LCL_EIPR_PPE1 = 0x10A010058ull;
+
+static const uint64_t P9N2_PU_CME2_CME_LCL_EIPR_PPE2 = 0x10A010050ull;
+
+static const uint64_t P9N2_PU_CME3_CME_LCL_EIPR_PPE = 0x10A020040ull;
+
+static const uint64_t P9N2_PU_CME3_CME_LCL_EIPR_PPE1 = 0x10A020058ull;
+
+static const uint64_t P9N2_PU_CME3_CME_LCL_EIPR_PPE2 = 0x10A020050ull;
+
+static const uint64_t P9N2_PU_CME4_CME_LCL_EIPR_PPE = 0x10B010040ull;
+
+static const uint64_t P9N2_PU_CME4_CME_LCL_EIPR_PPE1 = 0x10B010058ull;
+
+static const uint64_t P9N2_PU_CME4_CME_LCL_EIPR_PPE2 = 0x10B010050ull;
+
+static const uint64_t P9N2_PU_CME5_CME_LCL_EIPR_PPE = 0x10B020040ull;
+
+static const uint64_t P9N2_PU_CME5_CME_LCL_EIPR_PPE1 = 0x10B020058ull;
+
+static const uint64_t P9N2_PU_CME5_CME_LCL_EIPR_PPE2 = 0x10B020050ull;
+
+static const uint64_t P9N2_PU_CME6_CME_LCL_EIPR_PPE = 0x10C010040ull;
+
+static const uint64_t P9N2_PU_CME6_CME_LCL_EIPR_PPE1 = 0x10C010058ull;
+
+static const uint64_t P9N2_PU_CME6_CME_LCL_EIPR_PPE2 = 0x10C010050ull;
+
+static const uint64_t P9N2_PU_CME7_CME_LCL_EIPR_PPE = 0x10C020040ull;
+
+static const uint64_t P9N2_PU_CME7_CME_LCL_EIPR_PPE1 = 0x10C020058ull;
+
+static const uint64_t P9N2_PU_CME7_CME_LCL_EIPR_PPE2 = 0x10C020050ull;
+
+static const uint64_t P9N2_PU_CME8_CME_LCL_EIPR_PPE = 0x10D010040ull;
+
+static const uint64_t P9N2_PU_CME8_CME_LCL_EIPR_PPE1 = 0x10D010058ull;
+
+static const uint64_t P9N2_PU_CME8_CME_LCL_EIPR_PPE2 = 0x10D010050ull;
+
+static const uint64_t P9N2_PU_CME9_CME_LCL_EIPR_PPE = 0x10D020040ull;
+
+static const uint64_t P9N2_PU_CME9_CME_LCL_EIPR_PPE1 = 0x10D020058ull;
+
+static const uint64_t P9N2_PU_CME9_CME_LCL_EIPR_PPE2 = 0x10D020050ull;
+
+static const uint64_t P9N2_PU_CME10_CME_LCL_EIPR_PPE = 0x10E010040ull;
+
+static const uint64_t P9N2_PU_CME10_CME_LCL_EIPR_PPE1 = 0x10E010058ull;
+
+static const uint64_t P9N2_PU_CME10_CME_LCL_EIPR_PPE2 = 0x10E010050ull;
+
+static const uint64_t P9N2_PU_CME11_CME_LCL_EIPR_PPE = 0x10E020040ull;
+
+static const uint64_t P9N2_PU_CME11_CME_LCL_EIPR_PPE1 = 0x10E020058ull;
+
+static const uint64_t P9N2_PU_CME11_CME_LCL_EIPR_PPE2 = 0x10E020050ull;
+
+
+static const uint64_t P9N2_PU_CME0_CME_LCL_EISR_PPE = 0x109010000ull;
+
+static const uint64_t P9N2_PU_CME0_CME_LCL_EISR_PPE1 = 0x109010018ull;
+
+static const uint64_t P9N2_PU_CME0_CME_LCL_EISR_PPE2 = 0x109010010ull;
+
+static const uint64_t P9N2_PU_CME1_CME_LCL_EISR_PPE = 0x109020000ull;
+
+static const uint64_t P9N2_PU_CME1_CME_LCL_EISR_PPE1 = 0x109020018ull;
+
+static const uint64_t P9N2_PU_CME1_CME_LCL_EISR_PPE2 = 0x109020010ull;
+
+static const uint64_t P9N2_PU_CME2_CME_LCL_EISR_PPE = 0x10A010000ull;
+
+static const uint64_t P9N2_PU_CME2_CME_LCL_EISR_PPE1 = 0x10A010018ull;
+
+static const uint64_t P9N2_PU_CME2_CME_LCL_EISR_PPE2 = 0x10A010010ull;
+
+static const uint64_t P9N2_PU_CME3_CME_LCL_EISR_PPE = 0x10A020000ull;
+
+static const uint64_t P9N2_PU_CME3_CME_LCL_EISR_PPE1 = 0x10A020018ull;
+
+static const uint64_t P9N2_PU_CME3_CME_LCL_EISR_PPE2 = 0x10A020010ull;
+
+static const uint64_t P9N2_PU_CME4_CME_LCL_EISR_PPE = 0x10B010000ull;
+
+static const uint64_t P9N2_PU_CME4_CME_LCL_EISR_PPE1 = 0x10B010018ull;
+
+static const uint64_t P9N2_PU_CME4_CME_LCL_EISR_PPE2 = 0x10B010010ull;
+
+static const uint64_t P9N2_PU_CME5_CME_LCL_EISR_PPE = 0x10B020000ull;
+
+static const uint64_t P9N2_PU_CME5_CME_LCL_EISR_PPE1 = 0x10B020018ull;
+
+static const uint64_t P9N2_PU_CME5_CME_LCL_EISR_PPE2 = 0x10B020010ull;
+
+static const uint64_t P9N2_PU_CME6_CME_LCL_EISR_PPE = 0x10C010000ull;
+
+static const uint64_t P9N2_PU_CME6_CME_LCL_EISR_PPE1 = 0x10C010018ull;
+
+static const uint64_t P9N2_PU_CME6_CME_LCL_EISR_PPE2 = 0x10C010010ull;
+
+static const uint64_t P9N2_PU_CME7_CME_LCL_EISR_PPE = 0x10C020000ull;
+
+static const uint64_t P9N2_PU_CME7_CME_LCL_EISR_PPE1 = 0x10C020018ull;
+
+static const uint64_t P9N2_PU_CME7_CME_LCL_EISR_PPE2 = 0x10C020010ull;
+
+static const uint64_t P9N2_PU_CME8_CME_LCL_EISR_PPE = 0x10D010000ull;
+
+static const uint64_t P9N2_PU_CME8_CME_LCL_EISR_PPE1 = 0x10D010018ull;
+
+static const uint64_t P9N2_PU_CME8_CME_LCL_EISR_PPE2 = 0x10D010010ull;
+
+static const uint64_t P9N2_PU_CME9_CME_LCL_EISR_PPE = 0x10D020000ull;
+
+static const uint64_t P9N2_PU_CME9_CME_LCL_EISR_PPE1 = 0x10D020018ull;
+
+static const uint64_t P9N2_PU_CME9_CME_LCL_EISR_PPE2 = 0x10D020010ull;
+
+static const uint64_t P9N2_PU_CME10_CME_LCL_EISR_PPE = 0x10E010000ull;
+
+static const uint64_t P9N2_PU_CME10_CME_LCL_EISR_PPE1 = 0x10E010018ull;
+
+static const uint64_t P9N2_PU_CME10_CME_LCL_EISR_PPE2 = 0x10E010010ull;
+
+static const uint64_t P9N2_PU_CME11_CME_LCL_EISR_PPE = 0x10E020000ull;
+
+static const uint64_t P9N2_PU_CME11_CME_LCL_EISR_PPE1 = 0x10E020018ull;
+
+static const uint64_t P9N2_PU_CME11_CME_LCL_EISR_PPE2 = 0x10E020010ull;
+
+
+static const uint64_t P9N2_PU_CME0_CME_LCL_EISTR_PPE = 0x109010080ull;
+
+static const uint64_t P9N2_PU_CME1_CME_LCL_EISTR_PPE = 0x109020080ull;
+
+static const uint64_t P9N2_PU_CME2_CME_LCL_EISTR_PPE = 0x10A010080ull;
+
+static const uint64_t P9N2_PU_CME3_CME_LCL_EISTR_PPE = 0x10A020080ull;
+
+static const uint64_t P9N2_PU_CME4_CME_LCL_EISTR_PPE = 0x10B010080ull;
+
+static const uint64_t P9N2_PU_CME5_CME_LCL_EISTR_PPE = 0x10B020080ull;
+
+static const uint64_t P9N2_PU_CME6_CME_LCL_EISTR_PPE = 0x10C010080ull;
+
+static const uint64_t P9N2_PU_CME7_CME_LCL_EISTR_PPE = 0x10C020080ull;
+
+static const uint64_t P9N2_PU_CME8_CME_LCL_EISTR_PPE = 0x10D010080ull;
+
+static const uint64_t P9N2_PU_CME9_CME_LCL_EISTR_PPE = 0x10D020080ull;
+
+static const uint64_t P9N2_PU_CME10_CME_LCL_EISTR_PPE = 0x10E010080ull;
+
+static const uint64_t P9N2_PU_CME11_CME_LCL_EISTR_PPE = 0x10E020080ull;
+
+
+static const uint64_t P9N2_PU_CME0_CME_LCL_EITR_PPE = 0x109010060ull;
+
+static const uint64_t P9N2_PU_CME0_CME_LCL_EITR_PPE1 = 0x109010078ull;
+
+static const uint64_t P9N2_PU_CME0_CME_LCL_EITR_PPE2 = 0x109010070ull;
+
+static const uint64_t P9N2_PU_CME1_CME_LCL_EITR_PPE = 0x109020060ull;
+
+static const uint64_t P9N2_PU_CME1_CME_LCL_EITR_PPE1 = 0x109020078ull;
+
+static const uint64_t P9N2_PU_CME1_CME_LCL_EITR_PPE2 = 0x109020070ull;
+
+static const uint64_t P9N2_PU_CME2_CME_LCL_EITR_PPE = 0x10A010060ull;
+
+static const uint64_t P9N2_PU_CME2_CME_LCL_EITR_PPE1 = 0x10A010078ull;
+
+static const uint64_t P9N2_PU_CME2_CME_LCL_EITR_PPE2 = 0x10A010070ull;
+
+static const uint64_t P9N2_PU_CME3_CME_LCL_EITR_PPE = 0x10A020060ull;
+
+static const uint64_t P9N2_PU_CME3_CME_LCL_EITR_PPE1 = 0x10A020078ull;
+
+static const uint64_t P9N2_PU_CME3_CME_LCL_EITR_PPE2 = 0x10A020070ull;
+
+static const uint64_t P9N2_PU_CME4_CME_LCL_EITR_PPE = 0x10B010060ull;
+
+static const uint64_t P9N2_PU_CME4_CME_LCL_EITR_PPE1 = 0x10B010078ull;
+
+static const uint64_t P9N2_PU_CME4_CME_LCL_EITR_PPE2 = 0x10B010070ull;
+
+static const uint64_t P9N2_PU_CME5_CME_LCL_EITR_PPE = 0x10B020060ull;
+
+static const uint64_t P9N2_PU_CME5_CME_LCL_EITR_PPE1 = 0x10B020078ull;
+
+static const uint64_t P9N2_PU_CME5_CME_LCL_EITR_PPE2 = 0x10B020070ull;
+
+static const uint64_t P9N2_PU_CME6_CME_LCL_EITR_PPE = 0x10C010060ull;
+
+static const uint64_t P9N2_PU_CME6_CME_LCL_EITR_PPE1 = 0x10C010078ull;
+
+static const uint64_t P9N2_PU_CME6_CME_LCL_EITR_PPE2 = 0x10C010070ull;
+
+static const uint64_t P9N2_PU_CME7_CME_LCL_EITR_PPE = 0x10C020060ull;
+
+static const uint64_t P9N2_PU_CME7_CME_LCL_EITR_PPE1 = 0x10C020078ull;
+
+static const uint64_t P9N2_PU_CME7_CME_LCL_EITR_PPE2 = 0x10C020070ull;
+
+static const uint64_t P9N2_PU_CME8_CME_LCL_EITR_PPE = 0x10D010060ull;
+
+static const uint64_t P9N2_PU_CME8_CME_LCL_EITR_PPE1 = 0x10D010078ull;
+
+static const uint64_t P9N2_PU_CME8_CME_LCL_EITR_PPE2 = 0x10D010070ull;
+
+static const uint64_t P9N2_PU_CME9_CME_LCL_EITR_PPE = 0x10D020060ull;
+
+static const uint64_t P9N2_PU_CME9_CME_LCL_EITR_PPE1 = 0x10D020078ull;
+
+static const uint64_t P9N2_PU_CME9_CME_LCL_EITR_PPE2 = 0x10D020070ull;
+
+static const uint64_t P9N2_PU_CME10_CME_LCL_EITR_PPE = 0x10E010060ull;
+
+static const uint64_t P9N2_PU_CME10_CME_LCL_EITR_PPE1 = 0x10E010078ull;
+
+static const uint64_t P9N2_PU_CME10_CME_LCL_EITR_PPE2 = 0x10E010070ull;
+
+static const uint64_t P9N2_PU_CME11_CME_LCL_EITR_PPE = 0x10E020060ull;
+
+static const uint64_t P9N2_PU_CME11_CME_LCL_EITR_PPE1 = 0x10E020078ull;
+
+static const uint64_t P9N2_PU_CME11_CME_LCL_EITR_PPE2 = 0x10E020070ull;
+
+
+static const uint64_t P9N2_PU_CME0_CME_LCL_ICCR_PPE = 0x109010700ull;
+
+static const uint64_t P9N2_PU_CME0_CME_LCL_ICCR_PPE1 = 0x109010718ull;
+
+static const uint64_t P9N2_PU_CME0_CME_LCL_ICCR_PPE2 = 0x109010710ull;
+
+static const uint64_t P9N2_PU_CME1_CME_LCL_ICCR_PPE = 0x109020700ull;
+
+static const uint64_t P9N2_PU_CME1_CME_LCL_ICCR_PPE1 = 0x109020718ull;
+
+static const uint64_t P9N2_PU_CME1_CME_LCL_ICCR_PPE2 = 0x109020710ull;
+
+static const uint64_t P9N2_PU_CME2_CME_LCL_ICCR_PPE = 0x10A010700ull;
+
+static const uint64_t P9N2_PU_CME2_CME_LCL_ICCR_PPE1 = 0x10A010718ull;
+
+static const uint64_t P9N2_PU_CME2_CME_LCL_ICCR_PPE2 = 0x10A010710ull;
+
+static const uint64_t P9N2_PU_CME3_CME_LCL_ICCR_PPE = 0x10A020700ull;
+
+static const uint64_t P9N2_PU_CME3_CME_LCL_ICCR_PPE1 = 0x10A020718ull;
+
+static const uint64_t P9N2_PU_CME3_CME_LCL_ICCR_PPE2 = 0x10A020710ull;
+
+static const uint64_t P9N2_PU_CME4_CME_LCL_ICCR_PPE = 0x10B010700ull;
+
+static const uint64_t P9N2_PU_CME4_CME_LCL_ICCR_PPE1 = 0x10B010718ull;
+
+static const uint64_t P9N2_PU_CME4_CME_LCL_ICCR_PPE2 = 0x10B010710ull;
+
+static const uint64_t P9N2_PU_CME5_CME_LCL_ICCR_PPE = 0x10B020700ull;
+
+static const uint64_t P9N2_PU_CME5_CME_LCL_ICCR_PPE1 = 0x10B020718ull;
+
+static const uint64_t P9N2_PU_CME5_CME_LCL_ICCR_PPE2 = 0x10B020710ull;
+
+static const uint64_t P9N2_PU_CME6_CME_LCL_ICCR_PPE = 0x10C010700ull;
+
+static const uint64_t P9N2_PU_CME6_CME_LCL_ICCR_PPE1 = 0x10C010718ull;
+
+static const uint64_t P9N2_PU_CME6_CME_LCL_ICCR_PPE2 = 0x10C010710ull;
+
+static const uint64_t P9N2_PU_CME7_CME_LCL_ICCR_PPE = 0x10C020700ull;
+
+static const uint64_t P9N2_PU_CME7_CME_LCL_ICCR_PPE1 = 0x10C020718ull;
+
+static const uint64_t P9N2_PU_CME7_CME_LCL_ICCR_PPE2 = 0x10C020710ull;
+
+static const uint64_t P9N2_PU_CME8_CME_LCL_ICCR_PPE = 0x10D010700ull;
+
+static const uint64_t P9N2_PU_CME8_CME_LCL_ICCR_PPE1 = 0x10D010718ull;
+
+static const uint64_t P9N2_PU_CME8_CME_LCL_ICCR_PPE2 = 0x10D010710ull;
+
+static const uint64_t P9N2_PU_CME9_CME_LCL_ICCR_PPE = 0x10D020700ull;
+
+static const uint64_t P9N2_PU_CME9_CME_LCL_ICCR_PPE1 = 0x10D020718ull;
+
+static const uint64_t P9N2_PU_CME9_CME_LCL_ICCR_PPE2 = 0x10D020710ull;
+
+static const uint64_t P9N2_PU_CME10_CME_LCL_ICCR_PPE = 0x10E010700ull;
+
+static const uint64_t P9N2_PU_CME10_CME_LCL_ICCR_PPE1 = 0x10E010718ull;
+
+static const uint64_t P9N2_PU_CME10_CME_LCL_ICCR_PPE2 = 0x10E010710ull;
+
+static const uint64_t P9N2_PU_CME11_CME_LCL_ICCR_PPE = 0x10E020700ull;
+
+static const uint64_t P9N2_PU_CME11_CME_LCL_ICCR_PPE1 = 0x10E020718ull;
+
+static const uint64_t P9N2_PU_CME11_CME_LCL_ICCR_PPE2 = 0x10E020710ull;
+
+
+static const uint64_t P9N2_PU_CME0_CME_LCL_ICRR_PPE = 0x109010740ull;
+
+static const uint64_t P9N2_PU_CME1_CME_LCL_ICRR_PPE = 0x109020740ull;
+
+static const uint64_t P9N2_PU_CME2_CME_LCL_ICRR_PPE = 0x10A010740ull;
+
+static const uint64_t P9N2_PU_CME3_CME_LCL_ICRR_PPE = 0x10A020740ull;
+
+static const uint64_t P9N2_PU_CME4_CME_LCL_ICRR_PPE = 0x10B010740ull;
+
+static const uint64_t P9N2_PU_CME5_CME_LCL_ICRR_PPE = 0x10B020740ull;
+
+static const uint64_t P9N2_PU_CME6_CME_LCL_ICRR_PPE = 0x10C010740ull;
+
+static const uint64_t P9N2_PU_CME7_CME_LCL_ICRR_PPE = 0x10C020740ull;
+
+static const uint64_t P9N2_PU_CME8_CME_LCL_ICRR_PPE = 0x10D010740ull;
+
+static const uint64_t P9N2_PU_CME9_CME_LCL_ICRR_PPE = 0x10D020740ull;
+
+static const uint64_t P9N2_PU_CME10_CME_LCL_ICRR_PPE = 0x10E010740ull;
+
+static const uint64_t P9N2_PU_CME11_CME_LCL_ICRR_PPE = 0x10E020740ull;
+
+
+static const uint64_t P9N2_PU_CME0_CME_LCL_ICSR_PPE = 0x109010720ull;
+
+static const uint64_t P9N2_PU_CME1_CME_LCL_ICSR_PPE = 0x109020720ull;
+
+static const uint64_t P9N2_PU_CME2_CME_LCL_ICSR_PPE = 0x10A010720ull;
+
+static const uint64_t P9N2_PU_CME3_CME_LCL_ICSR_PPE = 0x10A020720ull;
+
+static const uint64_t P9N2_PU_CME4_CME_LCL_ICSR_PPE = 0x10B010720ull;
+
+static const uint64_t P9N2_PU_CME5_CME_LCL_ICSR_PPE = 0x10B020720ull;
+
+static const uint64_t P9N2_PU_CME6_CME_LCL_ICSR_PPE = 0x10C010720ull;
+
+static const uint64_t P9N2_PU_CME7_CME_LCL_ICSR_PPE = 0x10C020720ull;
+
+static const uint64_t P9N2_PU_CME8_CME_LCL_ICSR_PPE = 0x10D010720ull;
+
+static const uint64_t P9N2_PU_CME9_CME_LCL_ICSR_PPE = 0x10D020720ull;
+
+static const uint64_t P9N2_PU_CME10_CME_LCL_ICSR_PPE = 0x10E010720ull;
+
+static const uint64_t P9N2_PU_CME11_CME_LCL_ICSR_PPE = 0x10E020720ull;
+
+
+static const uint64_t P9N2_PU_CME0_CME_LCL_PECESR0_PPE = 0x109010280ull;
+
+static const uint64_t P9N2_PU_CME1_CME_LCL_PECESR0_PPE = 0x109020280ull;
+
+static const uint64_t P9N2_PU_CME2_CME_LCL_PECESR0_PPE = 0x10A010280ull;
+
+static const uint64_t P9N2_PU_CME3_CME_LCL_PECESR0_PPE = 0x10A020280ull;
+
+static const uint64_t P9N2_PU_CME4_CME_LCL_PECESR0_PPE = 0x10B010280ull;
+
+static const uint64_t P9N2_PU_CME5_CME_LCL_PECESR0_PPE = 0x10B020280ull;
+
+static const uint64_t P9N2_PU_CME6_CME_LCL_PECESR0_PPE = 0x10C010280ull;
+
+static const uint64_t P9N2_PU_CME7_CME_LCL_PECESR0_PPE = 0x10C020280ull;
+
+static const uint64_t P9N2_PU_CME8_CME_LCL_PECESR0_PPE = 0x10D010280ull;
+
+static const uint64_t P9N2_PU_CME9_CME_LCL_PECESR0_PPE = 0x10D020280ull;
+
+static const uint64_t P9N2_PU_CME10_CME_LCL_PECESR0_PPE = 0x10E010280ull;
+
+static const uint64_t P9N2_PU_CME11_CME_LCL_PECESR0_PPE = 0x10E020280ull;
+
+
+static const uint64_t P9N2_PU_CME0_CME_LCL_PECESR1_PPE = 0x1090102A0ull;
+
+static const uint64_t P9N2_PU_CME1_CME_LCL_PECESR1_PPE = 0x1090202A0ull;
+
+static const uint64_t P9N2_PU_CME2_CME_LCL_PECESR1_PPE = 0x10A0102A0ull;
+
+static const uint64_t P9N2_PU_CME3_CME_LCL_PECESR1_PPE = 0x10A0202A0ull;
+
+static const uint64_t P9N2_PU_CME4_CME_LCL_PECESR1_PPE = 0x10B0102A0ull;
+
+static const uint64_t P9N2_PU_CME5_CME_LCL_PECESR1_PPE = 0x10B0202A0ull;
+
+static const uint64_t P9N2_PU_CME6_CME_LCL_PECESR1_PPE = 0x10C0102A0ull;
+
+static const uint64_t P9N2_PU_CME7_CME_LCL_PECESR1_PPE = 0x10C0202A0ull;
+
+static const uint64_t P9N2_PU_CME8_CME_LCL_PECESR1_PPE = 0x10D0102A0ull;
+
+static const uint64_t P9N2_PU_CME9_CME_LCL_PECESR1_PPE = 0x10D0202A0ull;
+
+static const uint64_t P9N2_PU_CME10_CME_LCL_PECESR1_PPE = 0x10E0102A0ull;
+
+static const uint64_t P9N2_PU_CME11_CME_LCL_PECESR1_PPE = 0x10E0202A0ull;
+
+
+static const uint64_t P9N2_PU_CME0_CME_LCL_SISR_PPE = 0x109010520ull;
+
+static const uint64_t P9N2_PU_CME1_CME_LCL_SISR_PPE = 0x109020520ull;
+
+static const uint64_t P9N2_PU_CME2_CME_LCL_SISR_PPE = 0x10A010520ull;
+
+static const uint64_t P9N2_PU_CME3_CME_LCL_SISR_PPE = 0x10A020520ull;
+
+static const uint64_t P9N2_PU_CME4_CME_LCL_SISR_PPE = 0x10B010520ull;
+
+static const uint64_t P9N2_PU_CME5_CME_LCL_SISR_PPE = 0x10B020520ull;
+
+static const uint64_t P9N2_PU_CME6_CME_LCL_SISR_PPE = 0x10C010520ull;
+
+static const uint64_t P9N2_PU_CME7_CME_LCL_SISR_PPE = 0x10C020520ull;
+
+static const uint64_t P9N2_PU_CME8_CME_LCL_SISR_PPE = 0x10D010520ull;
+
+static const uint64_t P9N2_PU_CME9_CME_LCL_SISR_PPE = 0x10D020520ull;
+
+static const uint64_t P9N2_PU_CME10_CME_LCL_SISR_PPE = 0x10E010520ull;
+
+static const uint64_t P9N2_PU_CME11_CME_LCL_SISR_PPE = 0x10E020520ull;
+
+
+static const uint64_t P9N2_PU_CME0_CME_LCL_TSEL_PPE = 0x109010100ull;
+
+static const uint64_t P9N2_PU_CME1_CME_LCL_TSEL_PPE = 0x109020100ull;
+
+static const uint64_t P9N2_PU_CME2_CME_LCL_TSEL_PPE = 0x10A010100ull;
+
+static const uint64_t P9N2_PU_CME3_CME_LCL_TSEL_PPE = 0x10A020100ull;
+
+static const uint64_t P9N2_PU_CME4_CME_LCL_TSEL_PPE = 0x10B010100ull;
+
+static const uint64_t P9N2_PU_CME5_CME_LCL_TSEL_PPE = 0x10B020100ull;
+
+static const uint64_t P9N2_PU_CME6_CME_LCL_TSEL_PPE = 0x10C010100ull;
+
+static const uint64_t P9N2_PU_CME7_CME_LCL_TSEL_PPE = 0x10C020100ull;
+
+static const uint64_t P9N2_PU_CME8_CME_LCL_TSEL_PPE = 0x10D010100ull;
+
+static const uint64_t P9N2_PU_CME9_CME_LCL_TSEL_PPE = 0x10D020100ull;
+
+static const uint64_t P9N2_PU_CME10_CME_LCL_TSEL_PPE = 0x10E010100ull;
+
+static const uint64_t P9N2_PU_CME11_CME_LCL_TSEL_PPE = 0x10E020100ull;
+
+
+static const uint64_t P9N2_PU_CME0_CME_SCOM_AFSR_PPE = 0x109010160ull;
+
+static const uint64_t P9N2_PU_CME1_CME_SCOM_AFSR_PPE = 0x109020160ull;
+
+static const uint64_t P9N2_PU_CME2_CME_SCOM_AFSR_PPE = 0x10A010160ull;
+
+static const uint64_t P9N2_PU_CME3_CME_SCOM_AFSR_PPE = 0x10A020160ull;
+
+static const uint64_t P9N2_PU_CME4_CME_SCOM_AFSR_PPE = 0x10B010160ull;
+
+static const uint64_t P9N2_PU_CME5_CME_SCOM_AFSR_PPE = 0x10B020160ull;
+
+static const uint64_t P9N2_PU_CME6_CME_SCOM_AFSR_PPE = 0x10C010160ull;
+
+static const uint64_t P9N2_PU_CME7_CME_SCOM_AFSR_PPE = 0x10C020160ull;
+
+static const uint64_t P9N2_PU_CME8_CME_SCOM_AFSR_PPE = 0x10D010160ull;
+
+static const uint64_t P9N2_PU_CME9_CME_SCOM_AFSR_PPE = 0x10D020160ull;
+
+static const uint64_t P9N2_PU_CME10_CME_SCOM_AFSR_PPE = 0x10E010160ull;
+
+static const uint64_t P9N2_PU_CME11_CME_SCOM_AFSR_PPE = 0x10E020160ull;
+
+
+static const uint64_t P9N2_PU_CME0_CME_SCOM_AFTR_PPE = 0x109010180ull;
+
+static const uint64_t P9N2_PU_CME1_CME_SCOM_AFTR_PPE = 0x109020180ull;
+
+static const uint64_t P9N2_PU_CME2_CME_SCOM_AFTR_PPE = 0x10A010180ull;
+
+static const uint64_t P9N2_PU_CME3_CME_SCOM_AFTR_PPE = 0x10A020180ull;
+
+static const uint64_t P9N2_PU_CME4_CME_SCOM_AFTR_PPE = 0x10B010180ull;
+
+static const uint64_t P9N2_PU_CME5_CME_SCOM_AFTR_PPE = 0x10B020180ull;
+
+static const uint64_t P9N2_PU_CME6_CME_SCOM_AFTR_PPE = 0x10C010180ull;
+
+static const uint64_t P9N2_PU_CME7_CME_SCOM_AFTR_PPE = 0x10C020180ull;
+
+static const uint64_t P9N2_PU_CME8_CME_SCOM_AFTR_PPE = 0x10D010180ull;
+
+static const uint64_t P9N2_PU_CME9_CME_SCOM_AFTR_PPE = 0x10D020180ull;
+
+static const uint64_t P9N2_PU_CME10_CME_SCOM_AFTR_PPE = 0x10E010180ull;
+
+static const uint64_t P9N2_PU_CME11_CME_SCOM_AFTR_PPE = 0x10E020180ull;
+
+
+static const uint64_t P9N2_PU_CME0_CME_SCOM_BCECSR_PPE = 0x1090101E0ull;
+
+static const uint64_t P9N2_PU_CME1_CME_SCOM_BCECSR_PPE = 0x1090201E0ull;
+
+static const uint64_t P9N2_PU_CME2_CME_SCOM_BCECSR_PPE = 0x10A0101E0ull;
+
+static const uint64_t P9N2_PU_CME3_CME_SCOM_BCECSR_PPE = 0x10A0201E0ull;
+
+static const uint64_t P9N2_PU_CME4_CME_SCOM_BCECSR_PPE = 0x10B0101E0ull;
+
+static const uint64_t P9N2_PU_CME5_CME_SCOM_BCECSR_PPE = 0x10B0201E0ull;
+
+static const uint64_t P9N2_PU_CME6_CME_SCOM_BCECSR_PPE = 0x10C0101E0ull;
+
+static const uint64_t P9N2_PU_CME7_CME_SCOM_BCECSR_PPE = 0x10C0201E0ull;
+
+static const uint64_t P9N2_PU_CME8_CME_SCOM_BCECSR_PPE = 0x10D0101E0ull;
+
+static const uint64_t P9N2_PU_CME9_CME_SCOM_BCECSR_PPE = 0x10D0201E0ull;
+
+static const uint64_t P9N2_PU_CME10_CME_SCOM_BCECSR_PPE = 0x10E0101E0ull;
+
+static const uint64_t P9N2_PU_CME11_CME_SCOM_BCECSR_PPE = 0x10E0201E0ull;
+
+
+static const uint64_t P9N2_PU_CME0_CME_SCOM_CIDSR_PPE = 0x1090106C0ull;
+
+static const uint64_t P9N2_PU_CME1_CME_SCOM_CIDSR_PPE = 0x1090206C0ull;
+
+static const uint64_t P9N2_PU_CME2_CME_SCOM_CIDSR_PPE = 0x10A0106C0ull;
+
+static const uint64_t P9N2_PU_CME3_CME_SCOM_CIDSR_PPE = 0x10A0206C0ull;
+
+static const uint64_t P9N2_PU_CME4_CME_SCOM_CIDSR_PPE = 0x10B0106C0ull;
+
+static const uint64_t P9N2_PU_CME5_CME_SCOM_CIDSR_PPE = 0x10B0206C0ull;
+
+static const uint64_t P9N2_PU_CME6_CME_SCOM_CIDSR_PPE = 0x10C0106C0ull;
+
+static const uint64_t P9N2_PU_CME7_CME_SCOM_CIDSR_PPE = 0x10C0206C0ull;
+
+static const uint64_t P9N2_PU_CME8_CME_SCOM_CIDSR_PPE = 0x10D0106C0ull;
+
+static const uint64_t P9N2_PU_CME9_CME_SCOM_CIDSR_PPE = 0x10D0206C0ull;
+
+static const uint64_t P9N2_PU_CME10_CME_SCOM_CIDSR_PPE = 0x10E0106C0ull;
+
+static const uint64_t P9N2_PU_CME11_CME_SCOM_CIDSR_PPE = 0x10E0206C0ull;
+
+
+static const uint64_t P9N2_PU_CME0_CME_SCOM_FLAGS_PPE = 0x109010400ull;
+
+static const uint64_t P9N2_PU_CME0_CME_SCOM_FLAGS_PPE1 = 0x109010418ull;
+
+static const uint64_t P9N2_PU_CME0_CME_SCOM_FLAGS_PPE2 = 0x109010410ull;
+
+static const uint64_t P9N2_PU_CME1_CME_SCOM_FLAGS_PPE = 0x109020400ull;
+
+static const uint64_t P9N2_PU_CME1_CME_SCOM_FLAGS_PPE1 = 0x109020418ull;
+
+static const uint64_t P9N2_PU_CME1_CME_SCOM_FLAGS_PPE2 = 0x109020410ull;
+
+static const uint64_t P9N2_PU_CME2_CME_SCOM_FLAGS_PPE = 0x10A010400ull;
+
+static const uint64_t P9N2_PU_CME2_CME_SCOM_FLAGS_PPE1 = 0x10A010418ull;
+
+static const uint64_t P9N2_PU_CME2_CME_SCOM_FLAGS_PPE2 = 0x10A010410ull;
+
+static const uint64_t P9N2_PU_CME3_CME_SCOM_FLAGS_PPE = 0x10A020400ull;
+
+static const uint64_t P9N2_PU_CME3_CME_SCOM_FLAGS_PPE1 = 0x10A020418ull;
+
+static const uint64_t P9N2_PU_CME3_CME_SCOM_FLAGS_PPE2 = 0x10A020410ull;
+
+static const uint64_t P9N2_PU_CME4_CME_SCOM_FLAGS_PPE = 0x10B010400ull;
+
+static const uint64_t P9N2_PU_CME4_CME_SCOM_FLAGS_PPE1 = 0x10B010418ull;
+
+static const uint64_t P9N2_PU_CME4_CME_SCOM_FLAGS_PPE2 = 0x10B010410ull;
+
+static const uint64_t P9N2_PU_CME5_CME_SCOM_FLAGS_PPE = 0x10B020400ull;
+
+static const uint64_t P9N2_PU_CME5_CME_SCOM_FLAGS_PPE1 = 0x10B020418ull;
+
+static const uint64_t P9N2_PU_CME5_CME_SCOM_FLAGS_PPE2 = 0x10B020410ull;
+
+static const uint64_t P9N2_PU_CME6_CME_SCOM_FLAGS_PPE = 0x10C010400ull;
+
+static const uint64_t P9N2_PU_CME6_CME_SCOM_FLAGS_PPE1 = 0x10C010418ull;
+
+static const uint64_t P9N2_PU_CME6_CME_SCOM_FLAGS_PPE2 = 0x10C010410ull;
+
+static const uint64_t P9N2_PU_CME7_CME_SCOM_FLAGS_PPE = 0x10C020400ull;
+
+static const uint64_t P9N2_PU_CME7_CME_SCOM_FLAGS_PPE1 = 0x10C020418ull;
+
+static const uint64_t P9N2_PU_CME7_CME_SCOM_FLAGS_PPE2 = 0x10C020410ull;
+
+static const uint64_t P9N2_PU_CME8_CME_SCOM_FLAGS_PPE = 0x10D010400ull;
+
+static const uint64_t P9N2_PU_CME8_CME_SCOM_FLAGS_PPE1 = 0x10D010418ull;
+
+static const uint64_t P9N2_PU_CME8_CME_SCOM_FLAGS_PPE2 = 0x10D010410ull;
+
+static const uint64_t P9N2_PU_CME9_CME_SCOM_FLAGS_PPE = 0x10D020400ull;
+
+static const uint64_t P9N2_PU_CME9_CME_SCOM_FLAGS_PPE1 = 0x10D020418ull;
+
+static const uint64_t P9N2_PU_CME9_CME_SCOM_FLAGS_PPE2 = 0x10D020410ull;
+
+static const uint64_t P9N2_PU_CME10_CME_SCOM_FLAGS_PPE = 0x10E010400ull;
+
+static const uint64_t P9N2_PU_CME10_CME_SCOM_FLAGS_PPE1 = 0x10E010418ull;
+
+static const uint64_t P9N2_PU_CME10_CME_SCOM_FLAGS_PPE2 = 0x10E010410ull;
+
+static const uint64_t P9N2_PU_CME11_CME_SCOM_FLAGS_PPE = 0x10E020400ull;
+
+static const uint64_t P9N2_PU_CME11_CME_SCOM_FLAGS_PPE1 = 0x10E020418ull;
+
+static const uint64_t P9N2_PU_CME11_CME_SCOM_FLAGS_PPE2 = 0x10E020410ull;
+
+
+static const uint64_t P9N2_PU_CME0_CME_SCOM_IDCR_PPE = 0x1090106A0ull;
+
+static const uint64_t P9N2_PU_CME1_CME_SCOM_IDCR_PPE = 0x1090206A0ull;
+
+static const uint64_t P9N2_PU_CME2_CME_SCOM_IDCR_PPE = 0x10A0106A0ull;
+
+static const uint64_t P9N2_PU_CME3_CME_SCOM_IDCR_PPE = 0x10A0206A0ull;
+
+static const uint64_t P9N2_PU_CME4_CME_SCOM_IDCR_PPE = 0x10B0106A0ull;
+
+static const uint64_t P9N2_PU_CME5_CME_SCOM_IDCR_PPE = 0x10B0206A0ull;
+
+static const uint64_t P9N2_PU_CME6_CME_SCOM_IDCR_PPE = 0x10C0106A0ull;
+
+static const uint64_t P9N2_PU_CME7_CME_SCOM_IDCR_PPE = 0x10C0206A0ull;
+
+static const uint64_t P9N2_PU_CME8_CME_SCOM_IDCR_PPE = 0x10D0106A0ull;
+
+static const uint64_t P9N2_PU_CME9_CME_SCOM_IDCR_PPE = 0x10D0206A0ull;
+
+static const uint64_t P9N2_PU_CME10_CME_SCOM_IDCR_PPE = 0x10E0106A0ull;
+
+static const uint64_t P9N2_PU_CME11_CME_SCOM_IDCR_PPE = 0x10E0206A0ull;
+
+
+static const uint64_t P9N2_PU_CME0_CME_SCOM_LMCR_PPE = 0x1090101A0ull;
+
+static const uint64_t P9N2_PU_CME0_CME_SCOM_LMCR_PPE1 = 0x1090101B8ull;
+
+static const uint64_t P9N2_PU_CME0_CME_SCOM_LMCR_PPE2 = 0x1090101B0ull;
+
+static const uint64_t P9N2_PU_CME1_CME_SCOM_LMCR_PPE = 0x1090201A0ull;
+
+static const uint64_t P9N2_PU_CME1_CME_SCOM_LMCR_PPE1 = 0x1090201B8ull;
+
+static const uint64_t P9N2_PU_CME1_CME_SCOM_LMCR_PPE2 = 0x1090201B0ull;
+
+static const uint64_t P9N2_PU_CME2_CME_SCOM_LMCR_PPE = 0x10A0101A0ull;
+
+static const uint64_t P9N2_PU_CME2_CME_SCOM_LMCR_PPE1 = 0x10A0101B8ull;
+
+static const uint64_t P9N2_PU_CME2_CME_SCOM_LMCR_PPE2 = 0x10A0101B0ull;
+
+static const uint64_t P9N2_PU_CME3_CME_SCOM_LMCR_PPE = 0x10A0201A0ull;
+
+static const uint64_t P9N2_PU_CME3_CME_SCOM_LMCR_PPE1 = 0x10A0201B8ull;
+
+static const uint64_t P9N2_PU_CME3_CME_SCOM_LMCR_PPE2 = 0x10A0201B0ull;
+
+static const uint64_t P9N2_PU_CME4_CME_SCOM_LMCR_PPE = 0x10B0101A0ull;
+
+static const uint64_t P9N2_PU_CME4_CME_SCOM_LMCR_PPE1 = 0x10B0101B8ull;
+
+static const uint64_t P9N2_PU_CME4_CME_SCOM_LMCR_PPE2 = 0x10B0101B0ull;
+
+static const uint64_t P9N2_PU_CME5_CME_SCOM_LMCR_PPE = 0x10B0201A0ull;
+
+static const uint64_t P9N2_PU_CME5_CME_SCOM_LMCR_PPE1 = 0x10B0201B8ull;
+
+static const uint64_t P9N2_PU_CME5_CME_SCOM_LMCR_PPE2 = 0x10B0201B0ull;
+
+static const uint64_t P9N2_PU_CME6_CME_SCOM_LMCR_PPE = 0x10C0101A0ull;
+
+static const uint64_t P9N2_PU_CME6_CME_SCOM_LMCR_PPE1 = 0x10C0101B8ull;
+
+static const uint64_t P9N2_PU_CME6_CME_SCOM_LMCR_PPE2 = 0x10C0101B0ull;
+
+static const uint64_t P9N2_PU_CME7_CME_SCOM_LMCR_PPE = 0x10C0201A0ull;
+
+static const uint64_t P9N2_PU_CME7_CME_SCOM_LMCR_PPE1 = 0x10C0201B8ull;
+
+static const uint64_t P9N2_PU_CME7_CME_SCOM_LMCR_PPE2 = 0x10C0201B0ull;
+
+static const uint64_t P9N2_PU_CME8_CME_SCOM_LMCR_PPE = 0x10D0101A0ull;
+
+static const uint64_t P9N2_PU_CME8_CME_SCOM_LMCR_PPE1 = 0x10D0101B8ull;
+
+static const uint64_t P9N2_PU_CME8_CME_SCOM_LMCR_PPE2 = 0x10D0101B0ull;
+
+static const uint64_t P9N2_PU_CME9_CME_SCOM_LMCR_PPE = 0x10D0201A0ull;
+
+static const uint64_t P9N2_PU_CME9_CME_SCOM_LMCR_PPE1 = 0x10D0201B8ull;
+
+static const uint64_t P9N2_PU_CME9_CME_SCOM_LMCR_PPE2 = 0x10D0201B0ull;
+
+static const uint64_t P9N2_PU_CME10_CME_SCOM_LMCR_PPE = 0x10E0101A0ull;
+
+static const uint64_t P9N2_PU_CME10_CME_SCOM_LMCR_PPE1 = 0x10E0101B8ull;
+
+static const uint64_t P9N2_PU_CME10_CME_SCOM_LMCR_PPE2 = 0x10E0101B0ull;
+
+static const uint64_t P9N2_PU_CME11_CME_SCOM_LMCR_PPE = 0x10E0201A0ull;
+
+static const uint64_t P9N2_PU_CME11_CME_SCOM_LMCR_PPE1 = 0x10E0201B8ull;
+
+static const uint64_t P9N2_PU_CME11_CME_SCOM_LMCR_PPE2 = 0x10E0201B0ull;
+
+
+static const uint64_t P9N2_PU_CME0_CME_SCOM_PMCRS0_PPE = 0x109010240ull;
+
+static const uint64_t P9N2_PU_CME1_CME_SCOM_PMCRS0_PPE = 0x109020240ull;
+
+static const uint64_t P9N2_PU_CME2_CME_SCOM_PMCRS0_PPE = 0x10A010240ull;
+
+static const uint64_t P9N2_PU_CME3_CME_SCOM_PMCRS0_PPE = 0x10A020240ull;
+
+static const uint64_t P9N2_PU_CME4_CME_SCOM_PMCRS0_PPE = 0x10B010240ull;
+
+static const uint64_t P9N2_PU_CME5_CME_SCOM_PMCRS0_PPE = 0x10B020240ull;
+
+static const uint64_t P9N2_PU_CME6_CME_SCOM_PMCRS0_PPE = 0x10C010240ull;
+
+static const uint64_t P9N2_PU_CME7_CME_SCOM_PMCRS0_PPE = 0x10C020240ull;
+
+static const uint64_t P9N2_PU_CME8_CME_SCOM_PMCRS0_PPE = 0x10D010240ull;
+
+static const uint64_t P9N2_PU_CME9_CME_SCOM_PMCRS0_PPE = 0x10D020240ull;
+
+static const uint64_t P9N2_PU_CME10_CME_SCOM_PMCRS0_PPE = 0x10E010240ull;
+
+static const uint64_t P9N2_PU_CME11_CME_SCOM_PMCRS0_PPE = 0x10E020240ull;
+
+
+static const uint64_t P9N2_PU_CME0_CME_SCOM_PMCRS1_PPE = 0x109010260ull;
+
+static const uint64_t P9N2_PU_CME1_CME_SCOM_PMCRS1_PPE = 0x109020260ull;
+
+static const uint64_t P9N2_PU_CME2_CME_SCOM_PMCRS1_PPE = 0x10A010260ull;
+
+static const uint64_t P9N2_PU_CME3_CME_SCOM_PMCRS1_PPE = 0x10A020260ull;
+
+static const uint64_t P9N2_PU_CME4_CME_SCOM_PMCRS1_PPE = 0x10B010260ull;
+
+static const uint64_t P9N2_PU_CME5_CME_SCOM_PMCRS1_PPE = 0x10B020260ull;
+
+static const uint64_t P9N2_PU_CME6_CME_SCOM_PMCRS1_PPE = 0x10C010260ull;
+
+static const uint64_t P9N2_PU_CME7_CME_SCOM_PMCRS1_PPE = 0x10C020260ull;
+
+static const uint64_t P9N2_PU_CME8_CME_SCOM_PMCRS1_PPE = 0x10D010260ull;
+
+static const uint64_t P9N2_PU_CME9_CME_SCOM_PMCRS1_PPE = 0x10D020260ull;
+
+static const uint64_t P9N2_PU_CME10_CME_SCOM_PMCRS1_PPE = 0x10E010260ull;
+
+static const uint64_t P9N2_PU_CME11_CME_SCOM_PMCRS1_PPE = 0x10E020260ull;
+
+
+static const uint64_t P9N2_PU_CME0_CME_SCOM_PMSRS0_PPE = 0x109010200ull;
+
+static const uint64_t P9N2_PU_CME1_CME_SCOM_PMSRS0_PPE = 0x109020200ull;
+
+static const uint64_t P9N2_PU_CME2_CME_SCOM_PMSRS0_PPE = 0x10A010200ull;
+
+static const uint64_t P9N2_PU_CME3_CME_SCOM_PMSRS0_PPE = 0x10A020200ull;
+
+static const uint64_t P9N2_PU_CME4_CME_SCOM_PMSRS0_PPE = 0x10B010200ull;
+
+static const uint64_t P9N2_PU_CME5_CME_SCOM_PMSRS0_PPE = 0x10B020200ull;
+
+static const uint64_t P9N2_PU_CME6_CME_SCOM_PMSRS0_PPE = 0x10C010200ull;
+
+static const uint64_t P9N2_PU_CME7_CME_SCOM_PMSRS0_PPE = 0x10C020200ull;
+
+static const uint64_t P9N2_PU_CME8_CME_SCOM_PMSRS0_PPE = 0x10D010200ull;
+
+static const uint64_t P9N2_PU_CME9_CME_SCOM_PMSRS0_PPE = 0x10D020200ull;
+
+static const uint64_t P9N2_PU_CME10_CME_SCOM_PMSRS0_PPE = 0x10E010200ull;
+
+static const uint64_t P9N2_PU_CME11_CME_SCOM_PMSRS0_PPE = 0x10E020200ull;
+
+
+static const uint64_t P9N2_PU_CME0_CME_SCOM_PMSRS1_PPE = 0x109010220ull;
+
+static const uint64_t P9N2_PU_CME1_CME_SCOM_PMSRS1_PPE = 0x109020220ull;
+
+static const uint64_t P9N2_PU_CME2_CME_SCOM_PMSRS1_PPE = 0x10A010220ull;
+
+static const uint64_t P9N2_PU_CME3_CME_SCOM_PMSRS1_PPE = 0x10A020220ull;
+
+static const uint64_t P9N2_PU_CME4_CME_SCOM_PMSRS1_PPE = 0x10B010220ull;
+
+static const uint64_t P9N2_PU_CME5_CME_SCOM_PMSRS1_PPE = 0x10B020220ull;
+
+static const uint64_t P9N2_PU_CME6_CME_SCOM_PMSRS1_PPE = 0x10C010220ull;
+
+static const uint64_t P9N2_PU_CME7_CME_SCOM_PMSRS1_PPE = 0x10C020220ull;
+
+static const uint64_t P9N2_PU_CME8_CME_SCOM_PMSRS1_PPE = 0x10D010220ull;
+
+static const uint64_t P9N2_PU_CME9_CME_SCOM_PMSRS1_PPE = 0x10D020220ull;
+
+static const uint64_t P9N2_PU_CME10_CME_SCOM_PMSRS1_PPE = 0x10E010220ull;
+
+static const uint64_t P9N2_PU_CME11_CME_SCOM_PMSRS1_PPE = 0x10E020220ull;
+
+
+static const uint64_t P9N2_PU_CME0_CME_SCOM_PSCRS00_PPE = 0x109010300ull;
+
+static const uint64_t P9N2_PU_CME1_CME_SCOM_PSCRS00_PPE = 0x109020300ull;
+
+static const uint64_t P9N2_PU_CME2_CME_SCOM_PSCRS00_PPE = 0x10A010300ull;
+
+static const uint64_t P9N2_PU_CME3_CME_SCOM_PSCRS00_PPE = 0x10A020300ull;
+
+static const uint64_t P9N2_PU_CME4_CME_SCOM_PSCRS00_PPE = 0x10B010300ull;
+
+static const uint64_t P9N2_PU_CME5_CME_SCOM_PSCRS00_PPE = 0x10B020300ull;
+
+static const uint64_t P9N2_PU_CME6_CME_SCOM_PSCRS00_PPE = 0x10C010300ull;
+
+static const uint64_t P9N2_PU_CME7_CME_SCOM_PSCRS00_PPE = 0x10C020300ull;
+
+static const uint64_t P9N2_PU_CME8_CME_SCOM_PSCRS00_PPE = 0x10D010300ull;
+
+static const uint64_t P9N2_PU_CME9_CME_SCOM_PSCRS00_PPE = 0x10D020300ull;
+
+static const uint64_t P9N2_PU_CME10_CME_SCOM_PSCRS00_PPE = 0x10E010300ull;
+
+static const uint64_t P9N2_PU_CME11_CME_SCOM_PSCRS00_PPE = 0x10E020300ull;
+
+
+static const uint64_t P9N2_PU_CME0_CME_SCOM_PSCRS01_PPE = 0x109010320ull;
+
+static const uint64_t P9N2_PU_CME1_CME_SCOM_PSCRS01_PPE = 0x109020320ull;
+
+static const uint64_t P9N2_PU_CME2_CME_SCOM_PSCRS01_PPE = 0x10A010320ull;
+
+static const uint64_t P9N2_PU_CME3_CME_SCOM_PSCRS01_PPE = 0x10A020320ull;
+
+static const uint64_t P9N2_PU_CME4_CME_SCOM_PSCRS01_PPE = 0x10B010320ull;
+
+static const uint64_t P9N2_PU_CME5_CME_SCOM_PSCRS01_PPE = 0x10B020320ull;
+
+static const uint64_t P9N2_PU_CME6_CME_SCOM_PSCRS01_PPE = 0x10C010320ull;
+
+static const uint64_t P9N2_PU_CME7_CME_SCOM_PSCRS01_PPE = 0x10C020320ull;
+
+static const uint64_t P9N2_PU_CME8_CME_SCOM_PSCRS01_PPE = 0x10D010320ull;
+
+static const uint64_t P9N2_PU_CME9_CME_SCOM_PSCRS01_PPE = 0x10D020320ull;
+
+static const uint64_t P9N2_PU_CME10_CME_SCOM_PSCRS01_PPE = 0x10E010320ull;
+
+static const uint64_t P9N2_PU_CME11_CME_SCOM_PSCRS01_PPE = 0x10E020320ull;
+
+
+static const uint64_t P9N2_PU_CME0_CME_SCOM_PSCRS02_PPE = 0x109010340ull;
+
+static const uint64_t P9N2_PU_CME1_CME_SCOM_PSCRS02_PPE = 0x109020340ull;
+
+static const uint64_t P9N2_PU_CME2_CME_SCOM_PSCRS02_PPE = 0x10A010340ull;
+
+static const uint64_t P9N2_PU_CME3_CME_SCOM_PSCRS02_PPE = 0x10A020340ull;
+
+static const uint64_t P9N2_PU_CME4_CME_SCOM_PSCRS02_PPE = 0x10B010340ull;
+
+static const uint64_t P9N2_PU_CME5_CME_SCOM_PSCRS02_PPE = 0x10B020340ull;
+
+static const uint64_t P9N2_PU_CME6_CME_SCOM_PSCRS02_PPE = 0x10C010340ull;
+
+static const uint64_t P9N2_PU_CME7_CME_SCOM_PSCRS02_PPE = 0x10C020340ull;
+
+static const uint64_t P9N2_PU_CME8_CME_SCOM_PSCRS02_PPE = 0x10D010340ull;
+
+static const uint64_t P9N2_PU_CME9_CME_SCOM_PSCRS02_PPE = 0x10D020340ull;
+
+static const uint64_t P9N2_PU_CME10_CME_SCOM_PSCRS02_PPE = 0x10E010340ull;
+
+static const uint64_t P9N2_PU_CME11_CME_SCOM_PSCRS02_PPE = 0x10E020340ull;
+
+
+static const uint64_t P9N2_PU_CME0_CME_SCOM_PSCRS03_PPE = 0x109010360ull;
+
+static const uint64_t P9N2_PU_CME1_CME_SCOM_PSCRS03_PPE = 0x109020360ull;
+
+static const uint64_t P9N2_PU_CME2_CME_SCOM_PSCRS03_PPE = 0x10A010360ull;
+
+static const uint64_t P9N2_PU_CME3_CME_SCOM_PSCRS03_PPE = 0x10A020360ull;
+
+static const uint64_t P9N2_PU_CME4_CME_SCOM_PSCRS03_PPE = 0x10B010360ull;
+
+static const uint64_t P9N2_PU_CME5_CME_SCOM_PSCRS03_PPE = 0x10B020360ull;
+
+static const uint64_t P9N2_PU_CME6_CME_SCOM_PSCRS03_PPE = 0x10C010360ull;
+
+static const uint64_t P9N2_PU_CME7_CME_SCOM_PSCRS03_PPE = 0x10C020360ull;
+
+static const uint64_t P9N2_PU_CME8_CME_SCOM_PSCRS03_PPE = 0x10D010360ull;
+
+static const uint64_t P9N2_PU_CME9_CME_SCOM_PSCRS03_PPE = 0x10D020360ull;
+
+static const uint64_t P9N2_PU_CME10_CME_SCOM_PSCRS03_PPE = 0x10E010360ull;
+
+static const uint64_t P9N2_PU_CME11_CME_SCOM_PSCRS03_PPE = 0x10E020360ull;
+
+
+static const uint64_t P9N2_PU_CME0_CME_SCOM_PSCRS10_PPE = 0x109010380ull;
+
+static const uint64_t P9N2_PU_CME1_CME_SCOM_PSCRS10_PPE = 0x109020380ull;
+
+static const uint64_t P9N2_PU_CME2_CME_SCOM_PSCRS10_PPE = 0x10A010380ull;
+
+static const uint64_t P9N2_PU_CME3_CME_SCOM_PSCRS10_PPE = 0x10A020380ull;
+
+static const uint64_t P9N2_PU_CME4_CME_SCOM_PSCRS10_PPE = 0x10B010380ull;
+
+static const uint64_t P9N2_PU_CME5_CME_SCOM_PSCRS10_PPE = 0x10B020380ull;
+
+static const uint64_t P9N2_PU_CME6_CME_SCOM_PSCRS10_PPE = 0x10C010380ull;
+
+static const uint64_t P9N2_PU_CME7_CME_SCOM_PSCRS10_PPE = 0x10C020380ull;
+
+static const uint64_t P9N2_PU_CME8_CME_SCOM_PSCRS10_PPE = 0x10D010380ull;
+
+static const uint64_t P9N2_PU_CME9_CME_SCOM_PSCRS10_PPE = 0x10D020380ull;
+
+static const uint64_t P9N2_PU_CME10_CME_SCOM_PSCRS10_PPE = 0x10E010380ull;
+
+static const uint64_t P9N2_PU_CME11_CME_SCOM_PSCRS10_PPE = 0x10E020380ull;
+
+
+static const uint64_t P9N2_PU_CME0_CME_SCOM_PSCRS11_PPE = 0x1090103A0ull;
+
+static const uint64_t P9N2_PU_CME1_CME_SCOM_PSCRS11_PPE = 0x1090203A0ull;
+
+static const uint64_t P9N2_PU_CME2_CME_SCOM_PSCRS11_PPE = 0x10A0103A0ull;
+
+static const uint64_t P9N2_PU_CME3_CME_SCOM_PSCRS11_PPE = 0x10A0203A0ull;
+
+static const uint64_t P9N2_PU_CME4_CME_SCOM_PSCRS11_PPE = 0x10B0103A0ull;
+
+static const uint64_t P9N2_PU_CME5_CME_SCOM_PSCRS11_PPE = 0x10B0203A0ull;
+
+static const uint64_t P9N2_PU_CME6_CME_SCOM_PSCRS11_PPE = 0x10C0103A0ull;
+
+static const uint64_t P9N2_PU_CME7_CME_SCOM_PSCRS11_PPE = 0x10C0203A0ull;
+
+static const uint64_t P9N2_PU_CME8_CME_SCOM_PSCRS11_PPE = 0x10D0103A0ull;
+
+static const uint64_t P9N2_PU_CME9_CME_SCOM_PSCRS11_PPE = 0x10D0203A0ull;
+
+static const uint64_t P9N2_PU_CME10_CME_SCOM_PSCRS11_PPE = 0x10E0103A0ull;
+
+static const uint64_t P9N2_PU_CME11_CME_SCOM_PSCRS11_PPE = 0x10E0203A0ull;
+
+
+static const uint64_t P9N2_PU_CME0_CME_SCOM_PSCRS12_PPE = 0x1090103C0ull;
+
+static const uint64_t P9N2_PU_CME1_CME_SCOM_PSCRS12_PPE = 0x1090203C0ull;
+
+static const uint64_t P9N2_PU_CME2_CME_SCOM_PSCRS12_PPE = 0x10A0103C0ull;
+
+static const uint64_t P9N2_PU_CME3_CME_SCOM_PSCRS12_PPE = 0x10A0203C0ull;
+
+static const uint64_t P9N2_PU_CME4_CME_SCOM_PSCRS12_PPE = 0x10B0103C0ull;
+
+static const uint64_t P9N2_PU_CME5_CME_SCOM_PSCRS12_PPE = 0x10B0203C0ull;
+
+static const uint64_t P9N2_PU_CME6_CME_SCOM_PSCRS12_PPE = 0x10C0103C0ull;
+
+static const uint64_t P9N2_PU_CME7_CME_SCOM_PSCRS12_PPE = 0x10C0203C0ull;
+
+static const uint64_t P9N2_PU_CME8_CME_SCOM_PSCRS12_PPE = 0x10D0103C0ull;
+
+static const uint64_t P9N2_PU_CME9_CME_SCOM_PSCRS12_PPE = 0x10D0203C0ull;
+
+static const uint64_t P9N2_PU_CME10_CME_SCOM_PSCRS12_PPE = 0x10E0103C0ull;
+
+static const uint64_t P9N2_PU_CME11_CME_SCOM_PSCRS12_PPE = 0x10E0203C0ull;
+
+
+static const uint64_t P9N2_PU_CME0_CME_SCOM_PSCRS13_PPE = 0x1090103E0ull;
+
+static const uint64_t P9N2_PU_CME1_CME_SCOM_PSCRS13_PPE = 0x1090203E0ull;
+
+static const uint64_t P9N2_PU_CME2_CME_SCOM_PSCRS13_PPE = 0x10A0103E0ull;
+
+static const uint64_t P9N2_PU_CME3_CME_SCOM_PSCRS13_PPE = 0x10A0203E0ull;
+
+static const uint64_t P9N2_PU_CME4_CME_SCOM_PSCRS13_PPE = 0x10B0103E0ull;
+
+static const uint64_t P9N2_PU_CME5_CME_SCOM_PSCRS13_PPE = 0x10B0203E0ull;
+
+static const uint64_t P9N2_PU_CME6_CME_SCOM_PSCRS13_PPE = 0x10C0103E0ull;
+
+static const uint64_t P9N2_PU_CME7_CME_SCOM_PSCRS13_PPE = 0x10C0203E0ull;
+
+static const uint64_t P9N2_PU_CME8_CME_SCOM_PSCRS13_PPE = 0x10D0103E0ull;
+
+static const uint64_t P9N2_PU_CME9_CME_SCOM_PSCRS13_PPE = 0x10D0203E0ull;
+
+static const uint64_t P9N2_PU_CME10_CME_SCOM_PSCRS13_PPE = 0x10E0103E0ull;
+
+static const uint64_t P9N2_PU_CME11_CME_SCOM_PSCRS13_PPE = 0x10E0203E0ull;
+
+
+static const uint64_t P9N2_PU_CME0_CME_SCOM_QFMR_PPE = 0x109010140ull;
+
+static const uint64_t P9N2_PU_CME1_CME_SCOM_QFMR_PPE = 0x109020140ull;
+
+static const uint64_t P9N2_PU_CME2_CME_SCOM_QFMR_PPE = 0x10A010140ull;
+
+static const uint64_t P9N2_PU_CME3_CME_SCOM_QFMR_PPE = 0x10A020140ull;
+
+static const uint64_t P9N2_PU_CME4_CME_SCOM_QFMR_PPE = 0x10B010140ull;
+
+static const uint64_t P9N2_PU_CME5_CME_SCOM_QFMR_PPE = 0x10B020140ull;
+
+static const uint64_t P9N2_PU_CME6_CME_SCOM_QFMR_PPE = 0x10C010140ull;
+
+static const uint64_t P9N2_PU_CME7_CME_SCOM_QFMR_PPE = 0x10C020140ull;
+
+static const uint64_t P9N2_PU_CME8_CME_SCOM_QFMR_PPE = 0x10D010140ull;
+
+static const uint64_t P9N2_PU_CME9_CME_SCOM_QFMR_PPE = 0x10D020140ull;
+
+static const uint64_t P9N2_PU_CME10_CME_SCOM_QFMR_PPE = 0x10E010140ull;
+
+static const uint64_t P9N2_PU_CME11_CME_SCOM_QFMR_PPE = 0x10E020140ull;
+
+
+static const uint64_t P9N2_PU_CME0_CME_SCOM_QIDSR_PPE = 0x1090106E0ull;
+
+static const uint64_t P9N2_PU_CME1_CME_SCOM_QIDSR_PPE = 0x1090206E0ull;
+
+static const uint64_t P9N2_PU_CME2_CME_SCOM_QIDSR_PPE = 0x10A0106E0ull;
+
+static const uint64_t P9N2_PU_CME3_CME_SCOM_QIDSR_PPE = 0x10A0206E0ull;
+
+static const uint64_t P9N2_PU_CME4_CME_SCOM_QIDSR_PPE = 0x10B0106E0ull;
+
+static const uint64_t P9N2_PU_CME5_CME_SCOM_QIDSR_PPE = 0x10B0206E0ull;
+
+static const uint64_t P9N2_PU_CME6_CME_SCOM_QIDSR_PPE = 0x10C0106E0ull;
+
+static const uint64_t P9N2_PU_CME7_CME_SCOM_QIDSR_PPE = 0x10C0206E0ull;
+
+static const uint64_t P9N2_PU_CME8_CME_SCOM_QIDSR_PPE = 0x10D0106E0ull;
+
+static const uint64_t P9N2_PU_CME9_CME_SCOM_QIDSR_PPE = 0x10D0206E0ull;
+
+static const uint64_t P9N2_PU_CME10_CME_SCOM_QIDSR_PPE = 0x10E0106E0ull;
+
+static const uint64_t P9N2_PU_CME11_CME_SCOM_QIDSR_PPE = 0x10E0206E0ull;
+
+
+static const uint64_t P9N2_PU_CME0_CME_SCOM_SICR_PPE = 0x109010500ull;
+
+static const uint64_t P9N2_PU_CME0_CME_SCOM_SICR_PPE1 = 0x109010518ull;
+
+static const uint64_t P9N2_PU_CME0_CME_SCOM_SICR_PPE2 = 0x109010510ull;
+
+static const uint64_t P9N2_PU_CME1_CME_SCOM_SICR_PPE = 0x109020500ull;
+
+static const uint64_t P9N2_PU_CME1_CME_SCOM_SICR_PPE1 = 0x109020518ull;
+
+static const uint64_t P9N2_PU_CME1_CME_SCOM_SICR_PPE2 = 0x109020510ull;
+
+static const uint64_t P9N2_PU_CME2_CME_SCOM_SICR_PPE = 0x10A010500ull;
+
+static const uint64_t P9N2_PU_CME2_CME_SCOM_SICR_PPE1 = 0x10A010518ull;
+
+static const uint64_t P9N2_PU_CME2_CME_SCOM_SICR_PPE2 = 0x10A010510ull;
+
+static const uint64_t P9N2_PU_CME3_CME_SCOM_SICR_PPE = 0x10A020500ull;
+
+static const uint64_t P9N2_PU_CME3_CME_SCOM_SICR_PPE1 = 0x10A020518ull;
+
+static const uint64_t P9N2_PU_CME3_CME_SCOM_SICR_PPE2 = 0x10A020510ull;
+
+static const uint64_t P9N2_PU_CME4_CME_SCOM_SICR_PPE = 0x10B010500ull;
+
+static const uint64_t P9N2_PU_CME4_CME_SCOM_SICR_PPE1 = 0x10B010518ull;
+
+static const uint64_t P9N2_PU_CME4_CME_SCOM_SICR_PPE2 = 0x10B010510ull;
+
+static const uint64_t P9N2_PU_CME5_CME_SCOM_SICR_PPE = 0x10B020500ull;
+
+static const uint64_t P9N2_PU_CME5_CME_SCOM_SICR_PPE1 = 0x10B020518ull;
+
+static const uint64_t P9N2_PU_CME5_CME_SCOM_SICR_PPE2 = 0x10B020510ull;
+
+static const uint64_t P9N2_PU_CME6_CME_SCOM_SICR_PPE = 0x10C010500ull;
+
+static const uint64_t P9N2_PU_CME6_CME_SCOM_SICR_PPE1 = 0x10C010518ull;
+
+static const uint64_t P9N2_PU_CME6_CME_SCOM_SICR_PPE2 = 0x10C010510ull;
+
+static const uint64_t P9N2_PU_CME7_CME_SCOM_SICR_PPE = 0x10C020500ull;
+
+static const uint64_t P9N2_PU_CME7_CME_SCOM_SICR_PPE1 = 0x10C020518ull;
+
+static const uint64_t P9N2_PU_CME7_CME_SCOM_SICR_PPE2 = 0x10C020510ull;
+
+static const uint64_t P9N2_PU_CME8_CME_SCOM_SICR_PPE = 0x10D010500ull;
+
+static const uint64_t P9N2_PU_CME8_CME_SCOM_SICR_PPE1 = 0x10D010518ull;
+
+static const uint64_t P9N2_PU_CME8_CME_SCOM_SICR_PPE2 = 0x10D010510ull;
+
+static const uint64_t P9N2_PU_CME9_CME_SCOM_SICR_PPE = 0x10D020500ull;
+
+static const uint64_t P9N2_PU_CME9_CME_SCOM_SICR_PPE1 = 0x10D020518ull;
+
+static const uint64_t P9N2_PU_CME9_CME_SCOM_SICR_PPE2 = 0x10D020510ull;
+
+static const uint64_t P9N2_PU_CME10_CME_SCOM_SICR_PPE = 0x10E010500ull;
+
+static const uint64_t P9N2_PU_CME10_CME_SCOM_SICR_PPE1 = 0x10E010518ull;
+
+static const uint64_t P9N2_PU_CME10_CME_SCOM_SICR_PPE2 = 0x10E010510ull;
+
+static const uint64_t P9N2_PU_CME11_CME_SCOM_SICR_PPE = 0x10E020500ull;
+
+static const uint64_t P9N2_PU_CME11_CME_SCOM_SICR_PPE1 = 0x10E020518ull;
+
+static const uint64_t P9N2_PU_CME11_CME_SCOM_SICR_PPE2 = 0x10E020510ull;
+
+
+static const uint64_t P9N2_PU_CME0_CME_SCOM_SRTCH0_PPE = 0x109010420ull;
+
+static const uint64_t P9N2_PU_CME1_CME_SCOM_SRTCH0_PPE = 0x109020420ull;
+
+static const uint64_t P9N2_PU_CME2_CME_SCOM_SRTCH0_PPE = 0x10A010420ull;
+
+static const uint64_t P9N2_PU_CME3_CME_SCOM_SRTCH0_PPE = 0x10A020420ull;
+
+static const uint64_t P9N2_PU_CME4_CME_SCOM_SRTCH0_PPE = 0x10B010420ull;
+
+static const uint64_t P9N2_PU_CME5_CME_SCOM_SRTCH0_PPE = 0x10B020420ull;
+
+static const uint64_t P9N2_PU_CME6_CME_SCOM_SRTCH0_PPE = 0x10C010420ull;
+
+static const uint64_t P9N2_PU_CME7_CME_SCOM_SRTCH0_PPE = 0x10C020420ull;
+
+static const uint64_t P9N2_PU_CME8_CME_SCOM_SRTCH0_PPE = 0x10D010420ull;
+
+static const uint64_t P9N2_PU_CME9_CME_SCOM_SRTCH0_PPE = 0x10D020420ull;
+
+static const uint64_t P9N2_PU_CME10_CME_SCOM_SRTCH0_PPE = 0x10E010420ull;
+
+static const uint64_t P9N2_PU_CME11_CME_SCOM_SRTCH0_PPE = 0x10E020420ull;
+
+
+static const uint64_t P9N2_PU_CME0_CME_SCOM_SRTCH1_PPE = 0x109010440ull;
+
+static const uint64_t P9N2_PU_CME1_CME_SCOM_SRTCH1_PPE = 0x109020440ull;
+
+static const uint64_t P9N2_PU_CME2_CME_SCOM_SRTCH1_PPE = 0x10A010440ull;
+
+static const uint64_t P9N2_PU_CME3_CME_SCOM_SRTCH1_PPE = 0x10A020440ull;
+
+static const uint64_t P9N2_PU_CME4_CME_SCOM_SRTCH1_PPE = 0x10B010440ull;
+
+static const uint64_t P9N2_PU_CME5_CME_SCOM_SRTCH1_PPE = 0x10B020440ull;
+
+static const uint64_t P9N2_PU_CME6_CME_SCOM_SRTCH1_PPE = 0x10C010440ull;
+
+static const uint64_t P9N2_PU_CME7_CME_SCOM_SRTCH1_PPE = 0x10C020440ull;
+
+static const uint64_t P9N2_PU_CME8_CME_SCOM_SRTCH1_PPE = 0x10D010440ull;
+
+static const uint64_t P9N2_PU_CME9_CME_SCOM_SRTCH1_PPE = 0x10D020440ull;
+
+static const uint64_t P9N2_PU_CME10_CME_SCOM_SRTCH1_PPE = 0x10E010440ull;
+
+static const uint64_t P9N2_PU_CME11_CME_SCOM_SRTCH1_PPE = 0x10E020440ull;
+
+
+static const uint64_t P9N2_PU_CME0_CME_SCOM_VCCR_PPE = 0x109010680ull;
+
+static const uint64_t P9N2_PU_CME1_CME_SCOM_VCCR_PPE = 0x109020680ull;
+
+static const uint64_t P9N2_PU_CME2_CME_SCOM_VCCR_PPE = 0x10A010680ull;
+
+static const uint64_t P9N2_PU_CME3_CME_SCOM_VCCR_PPE = 0x10A020680ull;
+
+static const uint64_t P9N2_PU_CME4_CME_SCOM_VCCR_PPE = 0x10B010680ull;
+
+static const uint64_t P9N2_PU_CME5_CME_SCOM_VCCR_PPE = 0x10B020680ull;
+
+static const uint64_t P9N2_PU_CME6_CME_SCOM_VCCR_PPE = 0x10C010680ull;
+
+static const uint64_t P9N2_PU_CME7_CME_SCOM_VCCR_PPE = 0x10C020680ull;
+
+static const uint64_t P9N2_PU_CME8_CME_SCOM_VCCR_PPE = 0x10D010680ull;
+
+static const uint64_t P9N2_PU_CME9_CME_SCOM_VCCR_PPE = 0x10D020680ull;
+
+static const uint64_t P9N2_PU_CME10_CME_SCOM_VCCR_PPE = 0x10E010680ull;
+
+static const uint64_t P9N2_PU_CME11_CME_SCOM_VCCR_PPE = 0x10E020680ull;
+
+
+static const uint64_t P9N2_PU_CME0_CME_SCOM_VDCR_PPE = 0x109010600ull;
+
+static const uint64_t P9N2_PU_CME1_CME_SCOM_VDCR_PPE = 0x109020600ull;
+
+static const uint64_t P9N2_PU_CME2_CME_SCOM_VDCR_PPE = 0x10A010600ull;
+
+static const uint64_t P9N2_PU_CME3_CME_SCOM_VDCR_PPE = 0x10A020600ull;
+
+static const uint64_t P9N2_PU_CME4_CME_SCOM_VDCR_PPE = 0x10B010600ull;
+
+static const uint64_t P9N2_PU_CME5_CME_SCOM_VDCR_PPE = 0x10B020600ull;
+
+static const uint64_t P9N2_PU_CME6_CME_SCOM_VDCR_PPE = 0x10C010600ull;
+
+static const uint64_t P9N2_PU_CME7_CME_SCOM_VDCR_PPE = 0x10C020600ull;
+
+static const uint64_t P9N2_PU_CME8_CME_SCOM_VDCR_PPE = 0x10D010600ull;
+
+static const uint64_t P9N2_PU_CME9_CME_SCOM_VDCR_PPE = 0x10D020600ull;
+
+static const uint64_t P9N2_PU_CME10_CME_SCOM_VDCR_PPE = 0x10E010600ull;
+
+static const uint64_t P9N2_PU_CME11_CME_SCOM_VDCR_PPE = 0x10E020600ull;
+
+
+static const uint64_t P9N2_PU_CME0_CME_SCOM_VDSR_PPE = 0x109010640ull;
+
+static const uint64_t P9N2_PU_CME1_CME_SCOM_VDSR_PPE = 0x109020640ull;
+
+static const uint64_t P9N2_PU_CME2_CME_SCOM_VDSR_PPE = 0x10A010640ull;
+
+static const uint64_t P9N2_PU_CME3_CME_SCOM_VDSR_PPE = 0x10A020640ull;
+
+static const uint64_t P9N2_PU_CME4_CME_SCOM_VDSR_PPE = 0x10B010640ull;
+
+static const uint64_t P9N2_PU_CME5_CME_SCOM_VDSR_PPE = 0x10B020640ull;
+
+static const uint64_t P9N2_PU_CME6_CME_SCOM_VDSR_PPE = 0x10C010640ull;
+
+static const uint64_t P9N2_PU_CME7_CME_SCOM_VDSR_PPE = 0x10C020640ull;
+
+static const uint64_t P9N2_PU_CME8_CME_SCOM_VDSR_PPE = 0x10D010640ull;
+
+static const uint64_t P9N2_PU_CME9_CME_SCOM_VDSR_PPE = 0x10D020640ull;
+
+static const uint64_t P9N2_PU_CME10_CME_SCOM_VDSR_PPE = 0x10E010640ull;
+
+static const uint64_t P9N2_PU_CME11_CME_SCOM_VDSR_PPE = 0x10E020640ull;
+
+
+static const uint64_t P9N2_PU_CME0_CME_SCOM_VECR_PPE = 0x109010660ull;
+
+static const uint64_t P9N2_PU_CME1_CME_SCOM_VECR_PPE = 0x109020660ull;
+
+static const uint64_t P9N2_PU_CME2_CME_SCOM_VECR_PPE = 0x10A010660ull;
+
+static const uint64_t P9N2_PU_CME3_CME_SCOM_VECR_PPE = 0x10A020660ull;
+
+static const uint64_t P9N2_PU_CME4_CME_SCOM_VECR_PPE = 0x10B010660ull;
+
+static const uint64_t P9N2_PU_CME5_CME_SCOM_VECR_PPE = 0x10B020660ull;
+
+static const uint64_t P9N2_PU_CME6_CME_SCOM_VECR_PPE = 0x10C010660ull;
+
+static const uint64_t P9N2_PU_CME7_CME_SCOM_VECR_PPE = 0x10C020660ull;
+
+static const uint64_t P9N2_PU_CME8_CME_SCOM_VECR_PPE = 0x10D010660ull;
+
+static const uint64_t P9N2_PU_CME9_CME_SCOM_VECR_PPE = 0x10D020660ull;
+
+static const uint64_t P9N2_PU_CME10_CME_SCOM_VECR_PPE = 0x10E010660ull;
+
+static const uint64_t P9N2_PU_CME11_CME_SCOM_VECR_PPE = 0x10E020660ull;
+
+
+static const uint64_t P9N2_PU_CME0_CME_SCOM_VNCR_PPE = 0x109010620ull;
+
+static const uint64_t P9N2_PU_CME1_CME_SCOM_VNCR_PPE = 0x109020620ull;
+
+static const uint64_t P9N2_PU_CME2_CME_SCOM_VNCR_PPE = 0x10A010620ull;
+
+static const uint64_t P9N2_PU_CME3_CME_SCOM_VNCR_PPE = 0x10A020620ull;
+
+static const uint64_t P9N2_PU_CME4_CME_SCOM_VNCR_PPE = 0x10B010620ull;
+
+static const uint64_t P9N2_PU_CME5_CME_SCOM_VNCR_PPE = 0x10B020620ull;
+
+static const uint64_t P9N2_PU_CME6_CME_SCOM_VNCR_PPE = 0x10C010620ull;
+
+static const uint64_t P9N2_PU_CME7_CME_SCOM_VNCR_PPE = 0x10C020620ull;
+
+static const uint64_t P9N2_PU_CME8_CME_SCOM_VNCR_PPE = 0x10D010620ull;
+
+static const uint64_t P9N2_PU_CME9_CME_SCOM_VNCR_PPE = 0x10D020620ull;
+
+static const uint64_t P9N2_PU_CME10_CME_SCOM_VNCR_PPE = 0x10E010620ull;
+
+static const uint64_t P9N2_PU_CME11_CME_SCOM_VNCR_PPE = 0x10E020620ull;
+
+
+static const uint64_t P9N2_PU_CME0_CME_SCOM_XIPCBMD0_PPE = 0x109010580ull;
+
+static const uint64_t P9N2_PU_CME1_CME_SCOM_XIPCBMD0_PPE = 0x109020580ull;
+
+static const uint64_t P9N2_PU_CME2_CME_SCOM_XIPCBMD0_PPE = 0x10A010580ull;
+
+static const uint64_t P9N2_PU_CME3_CME_SCOM_XIPCBMD0_PPE = 0x10A020580ull;
+
+static const uint64_t P9N2_PU_CME4_CME_SCOM_XIPCBMD0_PPE = 0x10B010580ull;
+
+static const uint64_t P9N2_PU_CME5_CME_SCOM_XIPCBMD0_PPE = 0x10B020580ull;
+
+static const uint64_t P9N2_PU_CME6_CME_SCOM_XIPCBMD0_PPE = 0x10C010580ull;
+
+static const uint64_t P9N2_PU_CME7_CME_SCOM_XIPCBMD0_PPE = 0x10C020580ull;
+
+static const uint64_t P9N2_PU_CME8_CME_SCOM_XIPCBMD0_PPE = 0x10D010580ull;
+
+static const uint64_t P9N2_PU_CME9_CME_SCOM_XIPCBMD0_PPE = 0x10D020580ull;
+
+static const uint64_t P9N2_PU_CME10_CME_SCOM_XIPCBMD0_PPE = 0x10E010580ull;
+
+static const uint64_t P9N2_PU_CME11_CME_SCOM_XIPCBMD0_PPE = 0x10E020580ull;
+
+
+static const uint64_t P9N2_PU_CME0_CME_SCOM_XIPCBMD1_PPE = 0x1090105A0ull;
+
+static const uint64_t P9N2_PU_CME1_CME_SCOM_XIPCBMD1_PPE = 0x1090205A0ull;
+
+static const uint64_t P9N2_PU_CME2_CME_SCOM_XIPCBMD1_PPE = 0x10A0105A0ull;
+
+static const uint64_t P9N2_PU_CME3_CME_SCOM_XIPCBMD1_PPE = 0x10A0205A0ull;
+
+static const uint64_t P9N2_PU_CME4_CME_SCOM_XIPCBMD1_PPE = 0x10B0105A0ull;
+
+static const uint64_t P9N2_PU_CME5_CME_SCOM_XIPCBMD1_PPE = 0x10B0205A0ull;
+
+static const uint64_t P9N2_PU_CME6_CME_SCOM_XIPCBMD1_PPE = 0x10C0105A0ull;
+
+static const uint64_t P9N2_PU_CME7_CME_SCOM_XIPCBMD1_PPE = 0x10C0205A0ull;
+
+static const uint64_t P9N2_PU_CME8_CME_SCOM_XIPCBMD1_PPE = 0x10D0105A0ull;
+
+static const uint64_t P9N2_PU_CME9_CME_SCOM_XIPCBMD1_PPE = 0x10D0205A0ull;
+
+static const uint64_t P9N2_PU_CME10_CME_SCOM_XIPCBMD1_PPE = 0x10E0105A0ull;
+
+static const uint64_t P9N2_PU_CME11_CME_SCOM_XIPCBMD1_PPE = 0x10E0205A0ull;
+
+
+static const uint64_t P9N2_PU_CME0_CME_SCOM_XIPCBMI0_PPE = 0x1090105C0ull;
+
+static const uint64_t P9N2_PU_CME1_CME_SCOM_XIPCBMI0_PPE = 0x1090205C0ull;
+
+static const uint64_t P9N2_PU_CME2_CME_SCOM_XIPCBMI0_PPE = 0x10A0105C0ull;
+
+static const uint64_t P9N2_PU_CME3_CME_SCOM_XIPCBMI0_PPE = 0x10A0205C0ull;
+
+static const uint64_t P9N2_PU_CME4_CME_SCOM_XIPCBMI0_PPE = 0x10B0105C0ull;
+
+static const uint64_t P9N2_PU_CME5_CME_SCOM_XIPCBMI0_PPE = 0x10B0205C0ull;
+
+static const uint64_t P9N2_PU_CME6_CME_SCOM_XIPCBMI0_PPE = 0x10C0105C0ull;
+
+static const uint64_t P9N2_PU_CME7_CME_SCOM_XIPCBMI0_PPE = 0x10C0205C0ull;
+
+static const uint64_t P9N2_PU_CME8_CME_SCOM_XIPCBMI0_PPE = 0x10D0105C0ull;
+
+static const uint64_t P9N2_PU_CME9_CME_SCOM_XIPCBMI0_PPE = 0x10D0205C0ull;
+
+static const uint64_t P9N2_PU_CME10_CME_SCOM_XIPCBMI0_PPE = 0x10E0105C0ull;
+
+static const uint64_t P9N2_PU_CME11_CME_SCOM_XIPCBMI0_PPE = 0x10E0205C0ull;
+
+
+static const uint64_t P9N2_PU_CME0_CME_SCOM_XIPCBMI1_PPE = 0x1090105E0ull;
+
+static const uint64_t P9N2_PU_CME1_CME_SCOM_XIPCBMI1_PPE = 0x1090205E0ull;
+
+static const uint64_t P9N2_PU_CME2_CME_SCOM_XIPCBMI1_PPE = 0x10A0105E0ull;
+
+static const uint64_t P9N2_PU_CME3_CME_SCOM_XIPCBMI1_PPE = 0x10A0205E0ull;
+
+static const uint64_t P9N2_PU_CME4_CME_SCOM_XIPCBMI1_PPE = 0x10B0105E0ull;
+
+static const uint64_t P9N2_PU_CME5_CME_SCOM_XIPCBMI1_PPE = 0x10B0205E0ull;
+
+static const uint64_t P9N2_PU_CME6_CME_SCOM_XIPCBMI1_PPE = 0x10C0105E0ull;
+
+static const uint64_t P9N2_PU_CME7_CME_SCOM_XIPCBMI1_PPE = 0x10C0205E0ull;
+
+static const uint64_t P9N2_PU_CME8_CME_SCOM_XIPCBMI1_PPE = 0x10D0105E0ull;
+
+static const uint64_t P9N2_PU_CME9_CME_SCOM_XIPCBMI1_PPE = 0x10D0205E0ull;
+
+static const uint64_t P9N2_PU_CME10_CME_SCOM_XIPCBMI1_PPE = 0x10E0105E0ull;
+
+static const uint64_t P9N2_PU_CME11_CME_SCOM_XIPCBMI1_PPE = 0x10E0205E0ull;
+
+
+static const uint64_t P9N2_PU_COMMAND_REGISTER = 0x00010000ull;
+
+
+static const uint64_t P9N2_PU_COMMAND_REGISTER_B = 0x000A0005ull;
+
+
+static const uint64_t P9N2_PU_COMMAND_REGISTER_C = 0x000A1005ull;
+
+
+static const uint64_t P9N2_PU_COMMAND_REGISTER_D = 0x000A2005ull;
+
+
+static const uint64_t P9N2_PU_COMMAND_REGISTER_E = 0x000A3005ull;
+
+
+static const uint64_t P9N2_NV_CONFIG0 = 0x050110C0ull;
+
+static const uint64_t P9N2_NV_0_CONFIG0 = 0x050110C0ull;
+
+static const uint64_t P9N2_NV_4_CONFIG0 = 0x050114C0ull;
+
+static const uint64_t P9N2_PU_NPU0_CTL_CONFIG0 = 0x05011090ull;
+
+static const uint64_t P9N2_PU_NPU2_CTL_CONFIG0 = 0x05011290ull;
+
+static const uint64_t P9N2_PU_NPU0_SM0_CONFIG0 = 0x05011000ull;
+
+static const uint64_t P9N2_PU_NPU0_SM1_CONFIG0 = 0x05011030ull;
+
+static const uint64_t P9N2_PU_NPU0_SM3_CONFIG0 = 0x05011060ull;
+
+static const uint64_t P9N2_PU_NPU2_NTL0_CONFIG0 = 0x050112C0ull;
+
+static const uint64_t P9N2_PU_NPU2_SM0_CONFIG0 = 0x05011200ull;
+
+static const uint64_t P9N2_PU_NPU2_SM1_CONFIG0 = 0x05011230ull;
+
+static const uint64_t P9N2_PU_NPU2_SM3_CONFIG0 = 0x05011260ull;
+
+static const uint64_t P9N2_PU_NPU_CTL_CONFIG0 = 0x05011380ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_CTL_CONFIG0 = 0x05011490ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM0_CONFIG0 = 0x05011400ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM1_CONFIG0 = 0x05011430ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM3_CONFIG0 = 0x05011460ull;
+
+static const uint64_t P9N2_PU_NPU_SM2_CONFIG0 = 0x05011350ull;
+
+static const uint64_t P9N2__CTL_CONFIG0 = 0x05011580ull;
+
+static const uint64_t P9N2__SM2_CONFIG0 = 0x05011550ull;
+
+
+static const uint64_t P9N2_NV_CONFIG1 = 0x050110C1ull;
+
+static const uint64_t P9N2_NV_0_CONFIG1 = 0x050110C1ull;
+
+static const uint64_t P9N2_NV_1_CONFIG1 = 0x050110F1ull;
+
+static const uint64_t P9N2_NV_4_CONFIG1 = 0x050114C1ull;
+
+static const uint64_t P9N2_NV_5_CONFIG1 = 0x050114F1ull;
+
+static const uint64_t P9N2_PU_NPU0_CTL_CONFIG1 = 0x05011091ull;
+
+static const uint64_t P9N2_PU_NPU2_CTL_CONFIG1 = 0x05011291ull;
+
+static const uint64_t P9N2_PU_NPU0_SM0_CONFIG1 = 0x05011001ull;
+
+static const uint64_t P9N2_PU_NPU0_SM1_CONFIG1 = 0x05011031ull;
+
+static const uint64_t P9N2_PU_NPU0_SM3_CONFIG1 = 0x05011061ull;
+
+static const uint64_t P9N2_PU_NPU1_SM1_CONFIG1 = 0x05011128ull;
+
+static const uint64_t P9N2_PU_NPU1_SM2_CONFIG1 = 0x05011148ull;
+
+static const uint64_t P9N2_PU_NPU2_NTL0_CONFIG1 = 0x050112C1ull;
+
+static const uint64_t P9N2_PU_NPU2_NTL1_CONFIG1 = 0x050112F1ull;
+
+static const uint64_t P9N2_PU_NPU2_SM0_CONFIG1 = 0x05011201ull;
+
+static const uint64_t P9N2_PU_NPU2_SM1_CONFIG1 = 0x05011231ull;
+
+static const uint64_t P9N2_PU_NPU2_SM3_CONFIG1 = 0x05011261ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_CTL_CONFIG1 = 0x05011491ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM0_CONFIG1 = 0x05011401ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM1_CONFIG1 = 0x05011431ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM3_CONFIG1 = 0x05011461ull;
+
+static const uint64_t P9N2_PU_NPU_SM1_CONFIG1 = 0x05011328ull;
+
+static const uint64_t P9N2_PU_NPU_SM2_CONFIG1 = 0x05011348ull;
+
+static const uint64_t P9N2__SM1_CONFIG1 = 0x05011528ull;
+
+static const uint64_t P9N2__SM2_CONFIG1 = 0x05011548ull;
+
+
+static const uint64_t P9N2_NV_CONFIG2 = 0x050110C2ull;
+
+static const uint64_t P9N2_NV_0_CONFIG2 = 0x050110C2ull;
+
+static const uint64_t P9N2_NV_4_CONFIG2 = 0x050114C2ull;
+
+static const uint64_t P9N2_PU_NPU0_CTL_CONFIG2 = 0x05011089ull;
+
+static const uint64_t P9N2_PU_NPU0_DAT_CONFIG2 = 0x050110B9ull;
+
+static const uint64_t P9N2_PU_NPU2_DAT_CONFIG2 = 0x050112B9ull;
+
+static const uint64_t P9N2_PU_NPU2_CTL_CONFIG2 = 0x05011289ull;
+
+static const uint64_t P9N2_PU_NPU0_SM1_CONFIG2 = 0x05011029ull;
+
+static const uint64_t P9N2_PU_NPU0_SM2_CONFIG2 = 0x05011059ull;
+
+static const uint64_t P9N2_PU_NPU1_SM0_CONFIG2 = 0x05011110ull;
+
+static const uint64_t P9N2_PU_NPU1_SM1_CONFIG2 = 0x05011130ull;
+
+static const uint64_t P9N2_PU_NPU2_NTL0_CONFIG2 = 0x050112C2ull;
+
+static const uint64_t P9N2_PU_NPU2_SM1_CONFIG2 = 0x05011229ull;
+
+static const uint64_t P9N2_PU_NPU2_SM2_CONFIG2 = 0x05011259ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_CTL_CONFIG2 = 0x05011489ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_DAT_CONFIG2 = 0x050114B9ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM1_CONFIG2 = 0x05011429ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM2_CONFIG2 = 0x05011459ull;
+
+static const uint64_t P9N2_PU_NPU_SM0_CONFIG2 = 0x05011310ull;
+
+static const uint64_t P9N2_PU_NPU_SM1_CONFIG2 = 0x05011330ull;
+
+static const uint64_t P9N2__SM0_CONFIG2 = 0x05011510ull;
+
+static const uint64_t P9N2__SM1_CONFIG2 = 0x05011530ull;
+
+
+static const uint64_t P9N2_NV_CONFIG3 = 0x050110C3ull;
+
+static const uint64_t P9N2_NV_0_CONFIG3 = 0x050110C3ull;
+
+static const uint64_t P9N2_NV_4_CONFIG3 = 0x050114C3ull;
+
+static const uint64_t P9N2_PU_NPU1_SM0_CONFIG3 = 0x05011111ull;
+
+static const uint64_t P9N2_PU_NPU1_SM1_CONFIG3 = 0x05011131ull;
+
+static const uint64_t P9N2_PU_NPU2_NTL0_CONFIG3 = 0x050112C3ull;
+
+static const uint64_t P9N2_PU_NPU_SM0_CONFIG3 = 0x05011311ull;
+
+static const uint64_t P9N2_PU_NPU_SM1_CONFIG3 = 0x05011331ull;
+
+static const uint64_t P9N2__SM0_CONFIG3 = 0x05011511ull;
+
+static const uint64_t P9N2__SM1_CONFIG3 = 0x05011531ull;
+
+
+static const uint64_t P9N2_NV_1_CONFIG_ADDR0 = 0x050110E4ull;
+
+static const uint64_t P9N2_NV_5_CONFIG_ADDR0 = 0x050114E4ull;
+
+static const uint64_t P9N2_PU_NPU2_NTL1_CONFIG_ADDR0 = 0x050112E4ull;
+
+
+static const uint64_t P9N2_NV_1_CONFIG_ADDR1 = 0x050110E5ull;
+
+static const uint64_t P9N2_NV_5_CONFIG_ADDR1 = 0x050114E5ull;
+
+static const uint64_t P9N2_PU_NPU2_NTL1_CONFIG_ADDR1 = 0x050112E5ull;
+
+
+static const uint64_t P9N2_NV_1_CONFIG_DATA0 = 0x050110E6ull;
+
+static const uint64_t P9N2_NV_5_CONFIG_DATA0 = 0x050114E6ull;
+
+static const uint64_t P9N2_PU_NPU2_NTL1_CONFIG_DATA0 = 0x050112E6ull;
+
+
+static const uint64_t P9N2_NV_1_CONFIG_DATA1 = 0x050110E7ull;
+
+static const uint64_t P9N2_NV_5_CONFIG_DATA1 = 0x050114E7ull;
+
+static const uint64_t P9N2_PU_NPU2_NTL1_CONFIG_DATA1 = 0x050112E7ull;
+
+
+static const uint64_t P9N2_PU_NPU_CTL_CONFIG_DEBUG0 = 0x05011388ull;
+
+static const uint64_t P9N2_PU_NPU_SM2_CONFIG_DEBUG0 = 0x05011358ull;
+
+static const uint64_t P9N2__CTL_CONFIG_DEBUG0 = 0x05011588ull;
+
+static const uint64_t P9N2__SM2_CONFIG_DEBUG0 = 0x05011558ull;
+
+
+static const uint64_t P9N2_PU_NPU_CTL_CONFIG_DEBUG1 = 0x05011389ull;
+
+static const uint64_t P9N2_PU_NPU_SM2_CONFIG_DEBUG1 = 0x05011359ull;
+
+static const uint64_t P9N2__CTL_CONFIG_DEBUG1 = 0x05011589ull;
+
+static const uint64_t P9N2__SM2_CONFIG_DEBUG1 = 0x05011559ull;
+
+
+static const uint64_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED0 = 0x0501109Aull;
+
+static const uint64_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED0 = 0x0501129Aull;
+
+static const uint64_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED0 = 0x0501100Aull;
+
+static const uint64_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED0 = 0x0501103Aull;
+
+static const uint64_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED0 = 0x0501106Aull;
+
+static const uint64_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED0 = 0x0501120Aull;
+
+static const uint64_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED0 = 0x0501123Aull;
+
+static const uint64_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED0 = 0x0501126Aull;
+
+static const uint64_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED0 = 0x0501149Aull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED0 = 0x0501140Aull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED0 = 0x0501143Aull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED0 = 0x0501146Aull;
+
+
+static const uint64_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED1 = 0x0501109Bull;
+
+static const uint64_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED1 = 0x0501129Bull;
+
+static const uint64_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED1 = 0x0501100Bull;
+
+static const uint64_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED1 = 0x0501103Bull;
+
+static const uint64_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED1 = 0x0501106Bull;
+
+static const uint64_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED1 = 0x0501120Bull;
+
+static const uint64_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED1 = 0x0501123Bull;
+
+static const uint64_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED1 = 0x0501126Bull;
+
+static const uint64_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED1 = 0x0501149Bull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED1 = 0x0501140Bull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED1 = 0x0501143Bull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED1 = 0x0501146Bull;
+
+
+static const uint64_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2 = 0x0501109Cull;
+
+static const uint64_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2 = 0x0501129Cull;
+
+static const uint64_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2 = 0x0501100Cull;
+
+static const uint64_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2 = 0x0501103Cull;
+
+static const uint64_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2 = 0x0501106Cull;
+
+static const uint64_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2 = 0x0501120Cull;
+
+static const uint64_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2 = 0x0501123Cull;
+
+static const uint64_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2 = 0x0501126Cull;
+
+static const uint64_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2 = 0x0501149Cull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2 = 0x0501140Cull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2 = 0x0501143Cull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2 = 0x0501146Cull;
+
+
+static const uint64_t P9N2_PU_NPU_CTL_CONFIG_TLX_CREDITS = 0x0501138Aull;
+
+static const uint64_t P9N2_PU_NPU_SM2_CONFIG_TLX_CREDITS = 0x0501135Aull;
+
+static const uint64_t P9N2__CTL_CONFIG_TLX_CREDITS = 0x0501158Aull;
+
+static const uint64_t P9N2__SM2_CONFIG_TLX_CREDITS = 0x0501155Aull;
+
+
+static const uint64_t P9N2_PU_NPU_CTL_CONFIG_TX = 0x0501138Bull;
+
+static const uint64_t P9N2_PU_NPU_SM2_CONFIG_TX = 0x0501135Bull;
+
+static const uint64_t P9N2__CTL_CONFIG_TX = 0x0501158Bull;
+
+static const uint64_t P9N2__SM2_CONFIG_TX = 0x0501155Bull;
+
+
+static const uint64_t P9N2_PU_NPU_CTL_CONFIG_TX2 = 0x05011398ull;
+
+static const uint64_t P9N2_PU_NPU_SM3_CONFIG_TX2 = 0x05011368ull;
+
+static const uint64_t P9N2__CTL_CONFIG_TX2 = 0x05011598ull;
+
+static const uint64_t P9N2__SM3_CONFIG_TX2 = 0x05011568ull;
+
+
+static const uint64_t P9N2_PU_NPU_CTL_CONFIG_TX_DLC = 0x0501138Cull;
+
+static const uint64_t P9N2_PU_NPU_SM2_CONFIG_TX_DLC = 0x0501135Cull;
+
+static const uint64_t P9N2__CTL_CONFIG_TX_DLC = 0x0501158Cull;
+
+static const uint64_t P9N2__SM2_CONFIG_TX_DLC = 0x0501155Cull;
+
+
+static const uint64_t P9N2_PEC_CONTROL_REG = 0x0D050012ull;
+
+static const uint64_t P9N2_PEC_0_CONTROL_REG = 0x0D050012ull;
+
+static const uint64_t P9N2_PEC_1_CONTROL_REG = 0x0E050012ull;
+
+static const uint64_t P9N2_PEC_2_CONTROL_REG = 0x0F050012ull;
+
+
+static const uint64_t P9N2_PU_CONTROL_REGISTER_B = 0x000A0000ull;
+
+
+static const uint64_t P9N2_PU_CONTROL_REGISTER_C = 0x000A1000ull;
+
+
+static const uint64_t P9N2_PU_CONTROL_REGISTER_D = 0x000A2000ull;
+
+
+static const uint64_t P9N2_PU_CONTROL_REGISTER_E = 0x000A3000ull;
+
+
+static const uint64_t P9N2_PEC_CPLT_CONF0 = 0x0D000008ull;
+
+static const uint64_t P9N2_PEC_CPLT_CONF0_OR = 0x0D000018ull;
+
+static const uint64_t P9N2_PEC_CPLT_CONF0_CLEAR = 0x0D000028ull;
+
+static const uint64_t P9N2_PEC_0_CPLT_CONF0 = 0x0D000008ull;
+
+static const uint64_t P9N2_PEC_0_CPLT_CONF0_OR = 0x0D000018ull;
+
+static const uint64_t P9N2_PEC_0_CPLT_CONF0_CLEAR = 0x0D000028ull;
+
+static const uint64_t P9N2_PEC_1_CPLT_CONF0 = 0x0E000008ull;
+
+static const uint64_t P9N2_PEC_1_CPLT_CONF0_OR = 0x0E000018ull;
+
+static const uint64_t P9N2_PEC_1_CPLT_CONF0_CLEAR = 0x0E000028ull;
+
+static const uint64_t P9N2_PEC_2_CPLT_CONF0 = 0x0F000008ull;
+
+static const uint64_t P9N2_PEC_2_CPLT_CONF0_OR = 0x0F000018ull;
+
+static const uint64_t P9N2_PEC_2_CPLT_CONF0_CLEAR = 0x0F000028ull;
+
+
+static const uint64_t P9N2_PEC_CPLT_CONF1 = 0x0D000009ull;
+
+static const uint64_t P9N2_PEC_CPLT_CONF1_OR = 0x0D000019ull;
+
+static const uint64_t P9N2_PEC_CPLT_CONF1_CLEAR = 0x0D000029ull;
+
+static const uint64_t P9N2_PEC_0_CPLT_CONF1 = 0x0D000009ull;
+
+static const uint64_t P9N2_PEC_0_CPLT_CONF1_OR = 0x0D000019ull;
+
+static const uint64_t P9N2_PEC_0_CPLT_CONF1_CLEAR = 0x0D000029ull;
+
+static const uint64_t P9N2_PEC_1_CPLT_CONF1 = 0x0E000009ull;
+
+static const uint64_t P9N2_PEC_1_CPLT_CONF1_OR = 0x0E000019ull;
+
+static const uint64_t P9N2_PEC_1_CPLT_CONF1_CLEAR = 0x0E000029ull;
+
+static const uint64_t P9N2_PEC_2_CPLT_CONF1 = 0x0F000009ull;
+
+static const uint64_t P9N2_PEC_2_CPLT_CONF1_OR = 0x0F000019ull;
+
+static const uint64_t P9N2_PEC_2_CPLT_CONF1_CLEAR = 0x0F000029ull;
+
+
+static const uint64_t P9N2_PEC_CPLT_CTRL0 = 0x0D000000ull;
+
+static const uint64_t P9N2_PEC_CPLT_CTRL0_OR = 0x0D000010ull;
+
+static const uint64_t P9N2_PEC_CPLT_CTRL0_CLEAR = 0x0D000020ull;
+
+static const uint64_t P9N2_PEC_0_CPLT_CTRL0 = 0x0D000000ull;
+
+static const uint64_t P9N2_PEC_0_CPLT_CTRL0_OR = 0x0D000010ull;
+
+static const uint64_t P9N2_PEC_0_CPLT_CTRL0_CLEAR = 0x0D000020ull;
+
+static const uint64_t P9N2_PEC_1_CPLT_CTRL0 = 0x0E000000ull;
+
+static const uint64_t P9N2_PEC_1_CPLT_CTRL0_OR = 0x0E000010ull;
+
+static const uint64_t P9N2_PEC_1_CPLT_CTRL0_CLEAR = 0x0E000020ull;
+
+static const uint64_t P9N2_PEC_2_CPLT_CTRL0 = 0x0F000000ull;
+
+static const uint64_t P9N2_PEC_2_CPLT_CTRL0_OR = 0x0F000010ull;
+
+static const uint64_t P9N2_PEC_2_CPLT_CTRL0_CLEAR = 0x0F000020ull;
+
+
+static const uint64_t P9N2_PEC_CPLT_CTRL1 = 0x0D000001ull;
+
+static const uint64_t P9N2_PEC_CPLT_CTRL1_OR = 0x0D000011ull;
+
+static const uint64_t P9N2_PEC_CPLT_CTRL1_CLEAR = 0x0D000021ull;
+
+static const uint64_t P9N2_PEC_0_CPLT_CTRL1 = 0x0D000001ull;
+
+static const uint64_t P9N2_PEC_0_CPLT_CTRL1_OR = 0x0D000011ull;
+
+static const uint64_t P9N2_PEC_0_CPLT_CTRL1_CLEAR = 0x0D000021ull;
+
+static const uint64_t P9N2_PEC_1_CPLT_CTRL1 = 0x0E000001ull;
+
+static const uint64_t P9N2_PEC_1_CPLT_CTRL1_OR = 0x0E000011ull;
+
+static const uint64_t P9N2_PEC_1_CPLT_CTRL1_CLEAR = 0x0E000021ull;
+
+static const uint64_t P9N2_PEC_2_CPLT_CTRL1 = 0x0F000001ull;
+
+static const uint64_t P9N2_PEC_2_CPLT_CTRL1_OR = 0x0F000011ull;
+
+static const uint64_t P9N2_PEC_2_CPLT_CTRL1_CLEAR = 0x0F000021ull;
+
+
+static const uint64_t P9N2_PEC_CPLT_MASK0 = 0x0D000101ull;
+
+static const uint64_t P9N2_PEC_0_CPLT_MASK0 = 0x0D000101ull;
+
+static const uint64_t P9N2_PEC_1_CPLT_MASK0 = 0x0E000101ull;
+
+static const uint64_t P9N2_PEC_2_CPLT_MASK0 = 0x0F000101ull;
+
+
+static const uint64_t P9N2_PEC_CPLT_STAT0 = 0x0D000100ull;
+
+static const uint64_t P9N2_PEC_0_CPLT_STAT0 = 0x0D000100ull;
+
+static const uint64_t P9N2_PEC_1_CPLT_STAT0 = 0x0E000100ull;
+
+static const uint64_t P9N2_PEC_2_CPLT_STAT0 = 0x0F000100ull;
+
+
+static const uint64_t P9N2_PEC_0_STACK0_CQSTAT_REG = 0x04010C4Cull;
+
+static const uint64_t P9N2_PEC_1_STACK0_CQSTAT_REG = 0x0401104Cull;
+
+static const uint64_t P9N2_PEC_1_STACK1_CQSTAT_REG = 0x0401108Cull;
+
+static const uint64_t P9N2_PEC_1_STACK2_CQSTAT_REG = 0x040110CCull;
+
+static const uint64_t P9N2_PEC_2_STACK0_CQSTAT_REG = 0x0401144Cull;
+
+static const uint64_t P9N2_PEC_2_STACK1_CQSTAT_REG = 0x0401148Cull;
+
+static const uint64_t P9N2_PEC_2_STACK2_CQSTAT_REG = 0x040114CCull;
+
+static const uint64_t P9N2_PEC_STACK0_CQSTAT_REG = 0x04010C4Cull;
+
+static const uint64_t P9N2_PHB_CQSTAT_REG = 0x04010C4Cull;
+
+static const uint64_t P9N2_PHB_0_CQSTAT_REG = 0x04010C4Cull;
+
+static const uint64_t P9N2_PHB_1_CQSTAT_REG = 0x0401104Cull;
+
+static const uint64_t P9N2_PHB_2_CQSTAT_REG = 0x0401108Cull;
+
+static const uint64_t P9N2_PHB_3_CQSTAT_REG = 0x0401144Cull;
+
+static const uint64_t P9N2_PHB_4_CQSTAT_REG = 0x0401148Cull;
+
+static const uint64_t P9N2_PHB_5_CQSTAT_REG = 0x040114CCull;
+
+
+static const uint64_t P9N2_PU_NPU1_SM1_CREQ_DA_PTR = 0x05011124ull;
+
+static const uint64_t P9N2_PU_NPU1_SM2_CREQ_DA_PTR = 0x05011144ull;
+
+static const uint64_t P9N2_PU_NPU_SM1_CREQ_DA_PTR = 0x05011324ull;
+
+static const uint64_t P9N2_PU_NPU_SM2_CREQ_DA_PTR = 0x05011344ull;
+
+static const uint64_t P9N2__SM1_CREQ_DA_PTR = 0x05011524ull;
+
+static const uint64_t P9N2__SM2_CREQ_DA_PTR = 0x05011544ull;
+
+
+static const uint64_t P9N2_PU_NPU1_SM1_CREQ_HA_PTR = 0x05011120ull;
+
+static const uint64_t P9N2_PU_NPU1_SM2_CREQ_HA_PTR = 0x05011140ull;
+
+static const uint64_t P9N2_PU_NPU_SM1_CREQ_HA_PTR = 0x05011320ull;
+
+static const uint64_t P9N2_PU_NPU_SM2_CREQ_HA_PTR = 0x05011340ull;
+
+static const uint64_t P9N2__SM1_CREQ_HA_PTR = 0x05011520ull;
+
+static const uint64_t P9N2__SM2_CREQ_HA_PTR = 0x05011540ull;
+
+
+static const uint64_t P9N2_PU_CSAR = 0x0C01104Dull;
+//DUPS: 0901104D, 0C01104D,
+
+static const uint64_t P9N2_PU_CSCR = 0x0C01104Aull;
+//DUPS: 0901104A, 0C01104A,
+static const uint64_t P9N2_PU_CSCR_CLEAR = 0x0C01104Bull;
+//DUPS: 0901104B, 0C01104B,
+static const uint64_t P9N2_PU_CSCR_OR = 0x0C01104Cull;
+//DUPS: 0901104C, 0C01104C,
+
+static const uint64_t P9N2_PU_CSDR = 0x0C01104Eull;
+//DUPS: 0901104E, 0C01104E,
+
+static const uint64_t P9N2_NV_CTL_STATUS = 0x050110D2ull;
+
+static const uint64_t P9N2_NV_0_CTL_STATUS = 0x050110D2ull;
+
+static const uint64_t P9N2_NV_4_CTL_STATUS = 0x050114D2ull;
+
+static const uint64_t P9N2_PU_NPU2_NTL0_CTL_STATUS = 0x050112D2ull;
+
+
+static const uint64_t P9N2_PEC_CTRL_ATOMIC_LOCK_REG = 0x0D0003FFull;
+
+static const uint64_t P9N2_PEC_0_CTRL_ATOMIC_LOCK_REG = 0x0D0003FFull;
+
+static const uint64_t P9N2_PEC_1_CTRL_ATOMIC_LOCK_REG = 0x0E0003FFull;
+
+static const uint64_t P9N2_PEC_2_CTRL_ATOMIC_LOCK_REG = 0x0F0003FFull;
+
+
+static const uint64_t P9N2_PEC_CTRL_PROTECT_MODE_REG = 0x0D0003FEull;
+
+static const uint64_t P9N2_PEC_0_CTRL_PROTECT_MODE_REG = 0x0D0003FEull;
+
+static const uint64_t P9N2_PEC_1_CTRL_PROTECT_MODE_REG = 0x0E0003FEull;
+
+static const uint64_t P9N2_PEC_2_CTRL_PROTECT_MODE_REG = 0x0F0003FEull;
+
+
+static const uint64_t P9N2_CAPP_CXA_SNP_ARRAY_ADDR_REG = 0x02010828ull;
+
+static const uint64_t P9N2_CAPP_0_CXA_SNP_ARRAY_ADDR_REG = 0x02010828ull;
+
+static const uint64_t P9N2_CAPP_1_CXA_SNP_ARRAY_ADDR_REG = 0x04010828ull;
+
+
+static const uint64_t P9N2_CAPP_CXA_SNP_ARRAY_READ_REG = 0x02010829ull;
+
+static const uint64_t P9N2_CAPP_0_CXA_SNP_ARRAY_READ_REG = 0x02010829ull;
+
+static const uint64_t P9N2_CAPP_1_CXA_SNP_ARRAY_READ_REG = 0x04010829ull;
+
+
+static const uint64_t P9N2_CAPP_CXA_SNP_ARRAY_WRITE_REG = 0x02010841ull;
+
+static const uint64_t P9N2_CAPP_0_CXA_SNP_ARRAY_WRITE_REG = 0x02010841ull;
+
+static const uint64_t P9N2_CAPP_1_CXA_SNP_ARRAY_WRITE_REG = 0x04010841ull;
+
+
+static const uint64_t P9N2_CAPP_CXA_SNP_CAPI_CFG_REG = 0x0201081Aull;
+
+static const uint64_t P9N2_CAPP_0_CXA_SNP_CAPI_CFG_REG = 0x0201081Aull;
+
+static const uint64_t P9N2_CAPP_1_CXA_SNP_CAPI_CFG_REG = 0x0401081Aull;
+
+
+static const uint64_t P9N2_CAPP_CXA_SNP_CNTL_REG = 0x0201081Bull;
+
+static const uint64_t P9N2_CAPP_0_CXA_SNP_CNTL_REG = 0x0201081Bull;
+
+static const uint64_t P9N2_CAPP_1_CXA_SNP_CNTL_REG = 0x0401081Bull;
+
+
+static const uint64_t P9N2_CAPP_CXA_SNP_ERROR_REPORT_REG = 0x0201080Aull;
+
+static const uint64_t P9N2_CAPP_0_CXA_SNP_ERROR_REPORT_REG = 0x0201080Aull;
+
+static const uint64_t P9N2_CAPP_1_CXA_SNP_ERROR_REPORT_REG = 0x0401080Aull;
+
+
+static const uint64_t P9N2_CAPP_CXA_SNP_PHB_TTAG_FILTER_REG = 0x02010831ull;
+
+static const uint64_t P9N2_CAPP_0_CXA_SNP_PHB_TTAG_FILTER_REG = 0x02010831ull;
+
+static const uint64_t P9N2_CAPP_1_CXA_SNP_PHB_TTAG_FILTER_REG = 0x04010831ull;
+
+
+static const uint64_t P9N2_CAPP_CXA_SNP_PMU_EVENTS_SELECT_REG = 0x02010817ull;
+
+static const uint64_t P9N2_CAPP_0_CXA_SNP_PMU_EVENTS_SELECT_REG = 0x02010817ull;
+
+static const uint64_t P9N2_CAPP_1_CXA_SNP_PMU_EVENTS_SELECT_REG = 0x04010817ull;
+
+
+static const uint64_t P9N2_CAPP_CXA_TRIGCTL = 0x02010812ull;
+
+static const uint64_t P9N2_CAPP_0_CXA_TRIGCTL = 0x02010812ull;
+
+static const uint64_t P9N2_CAPP_1_CXA_TRIGCTL = 0x04010812ull;
+
+
+static const uint64_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0 = 0x05011386ull;
+
+static const uint64_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0 = 0x05011356ull;
+
+static const uint64_t P9N2__CTL_C_ERR_RPT_HOLD0 = 0x05011586ull;
+
+static const uint64_t P9N2__SM2_C_ERR_RPT_HOLD0 = 0x05011556ull;
+
+
+static const uint64_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD1 = 0x05011396ull;
+
+static const uint64_t P9N2_PU_NPU_SM3_C_ERR_RPT_HOLD1 = 0x05011366ull;
+
+static const uint64_t P9N2__CTL_C_ERR_RPT_HOLD1 = 0x05011596ull;
+
+static const uint64_t P9N2__SM3_C_ERR_RPT_HOLD1 = 0x05011566ull;
+
+
+static const uint64_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0 = 0x05011387ull;
+
+static const uint64_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0 = 0x05011357ull;
+
+static const uint64_t P9N2__CTL_C_ERR_RPT_MASK0 = 0x05011587ull;
+
+static const uint64_t P9N2__SM2_C_ERR_RPT_MASK0 = 0x05011557ull;
+
+
+static const uint64_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK1 = 0x05011397ull;
+
+static const uint64_t P9N2_PU_NPU_SM3_C_ERR_RPT_MASK1 = 0x05011367ull;
+
+static const uint64_t P9N2__CTL_C_ERR_RPT_MASK1 = 0x05011597ull;
+
+static const uint64_t P9N2__SM3_C_ERR_RPT_MASK1 = 0x05011567ull;
+
+
+static const uint64_t P9N2_PU_DATA0TO7_REGISTER_B = 0x000A0003ull;
+
+
+static const uint64_t P9N2_PU_DATA0TO7_REGISTER_C = 0x000A1003ull;
+
+
+static const uint64_t P9N2_PU_DATA0TO7_REGISTER_D = 0x000A2003ull;
+
+
+static const uint64_t P9N2_PU_DATA0TO7_REGISTER_E = 0x000A3003ull;
+
+
+static const uint64_t P9N2_PU_DATA8TO15_REGISTER_B = 0x000A0001ull;
+
+
+static const uint64_t P9N2_PU_DATA8TO15_REGISTER_C = 0x000A1001ull;
+
+
+static const uint64_t P9N2_PU_DATA8TO15_REGISTER_D = 0x000A2001ull;
+
+
+static const uint64_t P9N2_PU_DATA8TO15_REGISTER_E = 0x000A3001ull;
+
+
+static const uint64_t P9N2_PU_DATATAG_0_HASH_FUNCTION_REG = 0x0201114Cull;
+
+
+static const uint64_t P9N2_PU_DATATAG_1_HASH_FUNCTION_REG = 0x0201114Dull;
+
+
+static const uint64_t P9N2_PU_DATATAG_2_HASH_FUNCTION_REG = 0x0201114Eull;
+
+
+static const uint64_t P9N2_PU_DATATAG_3_HASH_FUNCTION_REG = 0x0201114Full;
+
+
+static const uint64_t P9N2_PU_DATATAG_4_HASH_FUNCTION_REG = 0x02011150ull;
+
+
+static const uint64_t P9N2_PU_DATATAG_5_HASH_FUNCTION_REG = 0x02011151ull;
+
+
+static const uint64_t P9N2_PU_DATA_REGISTER = 0x00010003ull;
+
+
+static const uint64_t P9N2__CTL_DA_ADDR = 0x0501168Eull;
+
+
+static const uint64_t P9N2__CTL_DA_DATA = 0x0501168Full;
+
+
+static const uint64_t P9N2_PEC_DBG_CBS_CC = 0x0D030013ull;
+
+static const uint64_t P9N2_PEC_0_DBG_CBS_CC = 0x0D030013ull;
+
+static const uint64_t P9N2_PEC_1_DBG_CBS_CC = 0x0E030013ull;
+
+static const uint64_t P9N2_PEC_2_DBG_CBS_CC = 0x0F030013ull;
+
+
+static const uint64_t P9N2_PEC_DBG_INST1_COND_REG_1 = 0x0D0107C1ull;
+
+static const uint64_t P9N2_PEC_0_DBG_INST1_COND_REG_1 = 0x0D0107C1ull;
+
+static const uint64_t P9N2_PEC_1_DBG_INST1_COND_REG_1 = 0x0E0107C1ull;
+
+static const uint64_t P9N2_PEC_2_DBG_INST1_COND_REG_1 = 0x0F0107C1ull;
+
+
+static const uint64_t P9N2_PU_N0_DBG_INST1_COND_REG_1 = 0x020107C1ull;
+
+static const uint64_t P9N2_PU_N1_DBG_INST1_COND_REG_1 = 0x030107C1ull;
+
+static const uint64_t P9N2_PU_N2_DBG_INST1_COND_REG_1 = 0x040107C1ull;
+
+static const uint64_t P9N2_PU_N3_DBG_INST1_COND_REG_1 = 0x050107C1ull;
+
+
+static const uint64_t P9N2_PEC_DBG_INST1_COND_REG_2 = 0x0D0107C2ull;
+
+static const uint64_t P9N2_PEC_0_DBG_INST1_COND_REG_2 = 0x0D0107C2ull;
+
+static const uint64_t P9N2_PEC_1_DBG_INST1_COND_REG_2 = 0x0E0107C2ull;
+
+static const uint64_t P9N2_PEC_2_DBG_INST1_COND_REG_2 = 0x0F0107C2ull;
+
+
+static const uint64_t P9N2_PU_N0_DBG_INST1_COND_REG_2 = 0x020107C2ull;
+
+static const uint64_t P9N2_PU_N1_DBG_INST1_COND_REG_2 = 0x030107C2ull;
+
+static const uint64_t P9N2_PU_N2_DBG_INST1_COND_REG_2 = 0x040107C2ull;
+
+static const uint64_t P9N2_PU_N3_DBG_INST1_COND_REG_2 = 0x050107C2ull;
+
+
+static const uint64_t P9N2_PEC_DBG_INST1_COND_REG_3 = 0x0D0107C3ull;
+
+static const uint64_t P9N2_PEC_0_DBG_INST1_COND_REG_3 = 0x0D0107C3ull;
+
+static const uint64_t P9N2_PEC_1_DBG_INST1_COND_REG_3 = 0x0E0107C3ull;
+
+static const uint64_t P9N2_PEC_2_DBG_INST1_COND_REG_3 = 0x0F0107C3ull;
+
+
+static const uint64_t P9N2_PU_N0_DBG_INST1_COND_REG_3 = 0x020107C3ull;
+
+static const uint64_t P9N2_PU_N1_DBG_INST1_COND_REG_3 = 0x030107C3ull;
+
+static const uint64_t P9N2_PU_N2_DBG_INST1_COND_REG_3 = 0x040107C3ull;
+
+static const uint64_t P9N2_PU_N3_DBG_INST1_COND_REG_3 = 0x050107C3ull;
+
+
+static const uint64_t P9N2_PEC_DBG_INST2_COND_REG_1 = 0x0D0107C4ull;
+
+static const uint64_t P9N2_PEC_0_DBG_INST2_COND_REG_1 = 0x0D0107C4ull;
+
+static const uint64_t P9N2_PEC_1_DBG_INST2_COND_REG_1 = 0x0E0107C4ull;
+
+static const uint64_t P9N2_PEC_2_DBG_INST2_COND_REG_1 = 0x0F0107C4ull;
+
+
+static const uint64_t P9N2_PU_N0_DBG_INST2_COND_REG_1 = 0x020107C4ull;
+
+static const uint64_t P9N2_PU_N1_DBG_INST2_COND_REG_1 = 0x030107C4ull;
+
+static const uint64_t P9N2_PU_N2_DBG_INST2_COND_REG_1 = 0x040107C4ull;
+
+static const uint64_t P9N2_PU_N3_DBG_INST2_COND_REG_1 = 0x050107C4ull;
+
+
+static const uint64_t P9N2_PEC_DBG_INST2_COND_REG_2 = 0x0D0107C5ull;
+
+static const uint64_t P9N2_PEC_0_DBG_INST2_COND_REG_2 = 0x0D0107C5ull;
+
+static const uint64_t P9N2_PEC_1_DBG_INST2_COND_REG_2 = 0x0E0107C5ull;
+
+static const uint64_t P9N2_PEC_2_DBG_INST2_COND_REG_2 = 0x0F0107C5ull;
+
+
+static const uint64_t P9N2_PU_N0_DBG_INST2_COND_REG_2 = 0x020107C5ull;
+
+static const uint64_t P9N2_PU_N1_DBG_INST2_COND_REG_2 = 0x030107C5ull;
+
+static const uint64_t P9N2_PU_N2_DBG_INST2_COND_REG_2 = 0x040107C5ull;
+
+static const uint64_t P9N2_PU_N3_DBG_INST2_COND_REG_2 = 0x050107C5ull;
+
+
+static const uint64_t P9N2_PEC_DBG_INST2_COND_REG_3 = 0x0D0107C6ull;
+
+static const uint64_t P9N2_PEC_0_DBG_INST2_COND_REG_3 = 0x0D0107C6ull;
+
+static const uint64_t P9N2_PEC_1_DBG_INST2_COND_REG_3 = 0x0E0107C6ull;
+
+static const uint64_t P9N2_PEC_2_DBG_INST2_COND_REG_3 = 0x0F0107C6ull;
+
+
+static const uint64_t P9N2_PU_N0_DBG_INST2_COND_REG_3 = 0x020107C6ull;
+
+static const uint64_t P9N2_PU_N1_DBG_INST2_COND_REG_3 = 0x030107C6ull;
+
+static const uint64_t P9N2_PU_N2_DBG_INST2_COND_REG_3 = 0x040107C6ull;
+
+static const uint64_t P9N2_PU_N3_DBG_INST2_COND_REG_3 = 0x050107C6ull;
+
+
+static const uint64_t P9N2_PEC_DBG_MODE_REG = 0x0D0107C0ull;
+
+static const uint64_t P9N2_PEC_0_DBG_MODE_REG = 0x0D0107C0ull;
+
+static const uint64_t P9N2_PEC_1_DBG_MODE_REG = 0x0E0107C0ull;
+
+static const uint64_t P9N2_PEC_2_DBG_MODE_REG = 0x0F0107C0ull;
+
+
+static const uint64_t P9N2_PU_N0_DBG_MODE_REG = 0x020107C0ull;
+
+static const uint64_t P9N2_PU_N1_DBG_MODE_REG = 0x030107C0ull;
+
+static const uint64_t P9N2_PU_N2_DBG_MODE_REG = 0x040107C0ull;
+
+static const uint64_t P9N2_PU_N3_DBG_MODE_REG = 0x050107C0ull;
+
+
+static const uint64_t P9N2_PEC_DBG_TRACE_MODE_REG_2 = 0x0D0107CFull;
+
+static const uint64_t P9N2_PEC_0_DBG_TRACE_MODE_REG_2 = 0x0D0107CFull;
+
+static const uint64_t P9N2_PEC_1_DBG_TRACE_MODE_REG_2 = 0x0E0107CFull;
+
+static const uint64_t P9N2_PEC_2_DBG_TRACE_MODE_REG_2 = 0x0F0107CFull;
+
+
+static const uint64_t P9N2_PU_N0_DBG_TRACE_MODE_REG_2 = 0x020107CFull;
+
+static const uint64_t P9N2_PU_N1_DBG_TRACE_MODE_REG_2 = 0x030107CFull;
+
+static const uint64_t P9N2_PU_N2_DBG_TRACE_MODE_REG_2 = 0x040107CFull;
+
+static const uint64_t P9N2_PU_N3_DBG_TRACE_MODE_REG_2 = 0x050107CFull;
+
+
+static const uint64_t P9N2_PEC_DBG_TRACE_REG_0 = 0x0D0107CDull;
+
+static const uint64_t P9N2_PEC_0_DBG_TRACE_REG_0 = 0x0D0107CDull;
+
+static const uint64_t P9N2_PEC_1_DBG_TRACE_REG_0 = 0x0E0107CDull;
+
+static const uint64_t P9N2_PEC_2_DBG_TRACE_REG_0 = 0x0F0107CDull;
+
+
+static const uint64_t P9N2_PU_N0_DBG_TRACE_REG_0 = 0x020107CDull;
+
+static const uint64_t P9N2_PU_N1_DBG_TRACE_REG_0 = 0x030107CDull;
+
+static const uint64_t P9N2_PU_N2_DBG_TRACE_REG_0 = 0x040107CDull;
+
+static const uint64_t P9N2_PU_N3_DBG_TRACE_REG_0 = 0x050107CDull;
+
+
+static const uint64_t P9N2_PEC_DBG_TRACE_REG_1 = 0x0D0107CEull;
+
+static const uint64_t P9N2_PEC_0_DBG_TRACE_REG_1 = 0x0D0107CEull;
+
+static const uint64_t P9N2_PEC_1_DBG_TRACE_REG_1 = 0x0E0107CEull;
+
+static const uint64_t P9N2_PEC_2_DBG_TRACE_REG_1 = 0x0F0107CEull;
+
+
+static const uint64_t P9N2_PU_N0_DBG_TRACE_REG_1 = 0x020107CEull;
+
+static const uint64_t P9N2_PU_N1_DBG_TRACE_REG_1 = 0x030107CEull;
+
+static const uint64_t P9N2_PU_N2_DBG_TRACE_REG_1 = 0x040107CEull;
+
+static const uint64_t P9N2_PU_N3_DBG_TRACE_REG_1 = 0x050107CEull;
+
+
+static const uint64_t P9N2_NV_DEBUG0_CONFIG = 0x050110C8ull;
+
+static const uint64_t P9N2_NV_0_DEBUG0_CONFIG = 0x050110C8ull;
+
+static const uint64_t P9N2_NV_4_DEBUG0_CONFIG = 0x050114C8ull;
+
+static const uint64_t P9N2_PU_NPU0_CTL_DEBUG0_CONFIG = 0x05011083ull;
+
+static const uint64_t P9N2_PU_NPU0_DAT_DEBUG0_CONFIG = 0x050110B3ull;
+
+static const uint64_t P9N2_PU_NPU2_DAT_DEBUG0_CONFIG = 0x050112B3ull;
+
+static const uint64_t P9N2_PU_NPU2_CTL_DEBUG0_CONFIG = 0x05011283ull;
+
+static const uint64_t P9N2_PU_NPU0_SM1_DEBUG0_CONFIG = 0x05011023ull;
+
+static const uint64_t P9N2_PU_NPU0_SM2_DEBUG0_CONFIG = 0x05011053ull;
+
+static const uint64_t P9N2_PU_NPU1_SM0_DEBUG0_CONFIG = 0x0501111Cull;
+//DUPS: 0501111C,
+static const uint64_t P9N2_PU_NPU1_SM1_DEBUG0_CONFIG = 0x0501113Cull;
+
+static const uint64_t P9N2_PU_NPU2_NTL0_DEBUG0_CONFIG = 0x050112C8ull;
+
+static const uint64_t P9N2_PU_NPU2_SM1_DEBUG0_CONFIG = 0x05011223ull;
+
+static const uint64_t P9N2_PU_NPU2_SM2_DEBUG0_CONFIG = 0x05011253ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_CTL_DEBUG0_CONFIG = 0x05011483ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_DAT_DEBUG0_CONFIG = 0x050114B3ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM1_DEBUG0_CONFIG = 0x05011423ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM2_DEBUG0_CONFIG = 0x05011453ull;
+
+static const uint64_t P9N2_PU_NPU_SM0_DEBUG0_CONFIG = 0x0501131Cull;
+//DUPS: 0501131C,
+static const uint64_t P9N2_PU_NPU_SM1_DEBUG0_CONFIG = 0x0501133Cull;
+
+static const uint64_t P9N2__SM0_DEBUG0_CONFIG = 0x0501151Cull;
+//DUPS: 0501151C,
+static const uint64_t P9N2__SM1_DEBUG0_CONFIG = 0x0501153Cull;
+
+static const uint64_t P9N2__SM2_DEBUG0_CONFIG = 0x05011646ull;
+
+
+static const uint64_t P9N2_NV_DEBUG1_CONFIG = 0x050110C9ull;
+
+static const uint64_t P9N2_NV_0_DEBUG1_CONFIG = 0x050110C9ull;
+
+static const uint64_t P9N2_NV_4_DEBUG1_CONFIG = 0x050114C9ull;
+
+static const uint64_t P9N2_PU_NPU0_CTL_DEBUG1_CONFIG = 0x05011084ull;
+
+static const uint64_t P9N2_PU_NPU0_DAT_DEBUG1_CONFIG = 0x050110B4ull;
+
+static const uint64_t P9N2_PU_NPU2_DAT_DEBUG1_CONFIG = 0x050112B4ull;
+
+static const uint64_t P9N2_PU_NPU2_CTL_DEBUG1_CONFIG = 0x05011284ull;
+
+static const uint64_t P9N2_PU_NPU0_SM1_DEBUG1_CONFIG = 0x05011024ull;
+
+static const uint64_t P9N2_PU_NPU0_SM2_DEBUG1_CONFIG = 0x05011054ull;
+
+static const uint64_t P9N2_PU_NPU1_SM0_DEBUG1_CONFIG = 0x0501111Dull;
+//DUPS: 0501111D,
+static const uint64_t P9N2_PU_NPU1_SM1_DEBUG1_CONFIG = 0x0501113Dull;
+
+static const uint64_t P9N2_PU_NPU2_NTL0_DEBUG1_CONFIG = 0x050112C9ull;
+
+static const uint64_t P9N2_PU_NPU2_SM1_DEBUG1_CONFIG = 0x05011224ull;
+
+static const uint64_t P9N2_PU_NPU2_SM2_DEBUG1_CONFIG = 0x05011254ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_CTL_DEBUG1_CONFIG = 0x05011484ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_DAT_DEBUG1_CONFIG = 0x050114B4ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM1_DEBUG1_CONFIG = 0x05011424ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM2_DEBUG1_CONFIG = 0x05011454ull;
+
+static const uint64_t P9N2_PU_NPU_SM0_DEBUG1_CONFIG = 0x0501131Dull;
+//DUPS: 0501131D,
+static const uint64_t P9N2_PU_NPU_SM1_DEBUG1_CONFIG = 0x0501133Dull;
+
+static const uint64_t P9N2__SM0_DEBUG1_CONFIG = 0x0501151Dull;
+//DUPS: 0501151D,
+static const uint64_t P9N2__SM1_DEBUG1_CONFIG = 0x0501153Dull;
+
+static const uint64_t P9N2__SM2_DEBUG1_CONFIG = 0x05011647ull;
+
+
+static const uint64_t P9N2_PU_NPU0_CTL_DEBUG3_CONFIG = 0x05011087ull;
+
+static const uint64_t P9N2_PU_NPU0_DAT_DEBUG3_CONFIG = 0x050110B7ull;
+
+static const uint64_t P9N2_PU_NPU2_CTL_DEBUG3_CONFIG = 0x05011287ull;
+
+static const uint64_t P9N2_PU_NPU2_DAT_DEBUG3_CONFIG = 0x050112B7ull;
+
+static const uint64_t P9N2_PU_NPU0_SM1_DEBUG3_CONFIG = 0x05011027ull;
+
+static const uint64_t P9N2_PU_NPU0_SM2_DEBUG3_CONFIG = 0x05011057ull;
+
+static const uint64_t P9N2_PU_NPU2_SM1_DEBUG3_CONFIG = 0x05011227ull;
+
+static const uint64_t P9N2_PU_NPU2_SM2_DEBUG3_CONFIG = 0x05011257ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_CTL_DEBUG3_CONFIG = 0x05011487ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_DAT_DEBUG3_CONFIG = 0x050114B7ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM1_DEBUG3_CONFIG = 0x05011427ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM2_DEBUG3_CONFIG = 0x05011457ull;
+
+
+static const uint64_t P9N2_PU_NPU0_CTL_DEBUG4_CONFIG = 0x05011088ull;
+
+static const uint64_t P9N2_PU_NPU0_DAT_DEBUG4_CONFIG = 0x050110B8ull;
+
+static const uint64_t P9N2_PU_NPU2_CTL_DEBUG4_CONFIG = 0x05011288ull;
+
+static const uint64_t P9N2_PU_NPU2_DAT_DEBUG4_CONFIG = 0x050112B8ull;
+
+static const uint64_t P9N2_PU_NPU0_SM1_DEBUG4_CONFIG = 0x05011028ull;
+
+static const uint64_t P9N2_PU_NPU0_SM2_DEBUG4_CONFIG = 0x05011058ull;
+
+static const uint64_t P9N2_PU_NPU2_SM1_DEBUG4_CONFIG = 0x05011228ull;
+
+static const uint64_t P9N2_PU_NPU2_SM2_DEBUG4_CONFIG = 0x05011258ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_CTL_DEBUG4_CONFIG = 0x05011488ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_DAT_DEBUG4_CONFIG = 0x050114B8ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM1_DEBUG4_CONFIG = 0x05011428ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM2_DEBUG4_CONFIG = 0x05011458ull;
+
+
+static const uint64_t P9N2__CTL_DEBUG_CONFIG = 0x05011680ull;
+
+
+static const uint64_t P9N2_CAPP_DEBUG_CONTROL = 0x02010811ull;
+
+static const uint64_t P9N2_CAPP_0_DEBUG_CONTROL = 0x02010811ull;
+
+static const uint64_t P9N2_CAPP_1_DEBUG_CONTROL = 0x04010811ull;
+
+
+static const uint64_t P9N2_PU_DEBUG_TRACE_CONTROL = 0x020107D0ull;
+//DUPS: 050107D0, 030107D0, 040107D0,
+
+static const uint64_t P9N2_PEC_DEBUG_TRACE_CONTROL = 0x0D0107D0ull;
+
+static const uint64_t P9N2_PEC_0_DEBUG_TRACE_CONTROL = 0x0D0107D0ull;
+
+static const uint64_t P9N2_PEC_1_DEBUG_TRACE_CONTROL = 0x0E0107D0ull;
+
+static const uint64_t P9N2_PEC_2_DEBUG_TRACE_CONTROL = 0x0F0107D0ull;
+
+
+static const uint64_t P9N2_CAPP_DFSUOP1 = 0x02010843ull;
+
+static const uint64_t P9N2_CAPP_0_DFSUOP1 = 0x02010843ull;
+
+static const uint64_t P9N2_CAPP_1_DFSUOP1 = 0x04010843ull;
+
+
+static const uint64_t P9N2_PU_DISABLE_FORCE_PFET_OFF = 0x0001000Dull;
+
+
+static const uint64_t P9N2__SM1_DMA_SYNC = 0x05011623ull;
+
+
+static const uint64_t P9N2_PU_DMA_UP_ADDR = 0x05012914ull;
+
+
+static const uint64_t P9N2_PU_DMA_VAS_MMIO_BAR = 0x0201105Eull;
+
+
+static const uint64_t P9N2_PEC_DRPPRICTL_REG = 0x04010C01ull;
+
+static const uint64_t P9N2_PEC_0_DRPPRICTL_REG = 0x04010C01ull;
+
+static const uint64_t P9N2_PEC_1_DRPPRICTL_REG = 0x04011001ull;
+
+static const uint64_t P9N2_PEC_2_DRPPRICTL_REG = 0x04011401ull;
+
+
+static const uint64_t P9N2_PEC_DTS_RESULT0 = 0x0D050000ull;
+
+static const uint64_t P9N2_PEC_0_DTS_RESULT0 = 0x0D050000ull;
+
+static const uint64_t P9N2_PEC_1_DTS_RESULT0 = 0x0E050000ull;
+
+static const uint64_t P9N2_PEC_2_DTS_RESULT0 = 0x0F050000ull;
+
+
+static const uint64_t P9N2_PEC_DTS_TRC_RESULT = 0x0D050003ull;
+
+static const uint64_t P9N2_PEC_0_DTS_TRC_RESULT = 0x0D050003ull;
+
+static const uint64_t P9N2_PEC_1_DTS_TRC_RESULT = 0x0E050003ull;
+
+static const uint64_t P9N2_PEC_2_DTS_TRC_RESULT = 0x0F050003ull;
+
+
+static const uint64_t P9N2_NV_1_ECC_CONFIG = 0x050110F2ull;
+
+static const uint64_t P9N2_NV_5_ECC_CONFIG = 0x050114F2ull;
+
+static const uint64_t P9N2_PU_NPU2_NTL1_ECC_CONFIG = 0x050112F2ull;
+
+
+static const uint64_t P9N2_PU_OTPROM0_ECID_PART0_REGISTER = 0x00018000ull;
+
+static const uint64_t P9N2_PU_OTPROM1_ECID_PART0_REGISTER = 0x00018040ull;
+
+
+static const uint64_t P9N2_PU_OTPROM0_ECID_PART10_REGISTER = 0x0001800Aull;
+
+static const uint64_t P9N2_PU_OTPROM1_ECID_PART10_REGISTER = 0x0001804Aull;
+
+
+static const uint64_t P9N2_PU_OTPROM0_ECID_PART11_REGISTER = 0x0001800Bull;
+
+static const uint64_t P9N2_PU_OTPROM1_ECID_PART11_REGISTER = 0x0001804Bull;
+
+
+static const uint64_t P9N2_PU_OTPROM0_ECID_PART12_REGISTER = 0x0001800Cull;
+
+static const uint64_t P9N2_PU_OTPROM1_ECID_PART12_REGISTER = 0x0001804Cull;
+
+
+static const uint64_t P9N2_PU_OTPROM0_ECID_PART13_REGISTER = 0x0001800Dull;
+
+static const uint64_t P9N2_PU_OTPROM1_ECID_PART13_REGISTER = 0x0001804Dull;
+
+
+static const uint64_t P9N2_PU_OTPROM0_ECID_PART14_REGISTER = 0x0001800Eull;
+
+static const uint64_t P9N2_PU_OTPROM1_ECID_PART14_REGISTER = 0x0001804Eull;
+
+
+static const uint64_t P9N2_PU_OTPROM0_ECID_PART15_REGISTER = 0x0001800Full;
+
+static const uint64_t P9N2_PU_OTPROM1_ECID_PART15_REGISTER = 0x0001804Full;
+
+
+static const uint64_t P9N2_PU_OTPROM0_ECID_PART16_REGISTER = 0x00018010ull;
+
+static const uint64_t P9N2_PU_OTPROM1_ECID_PART16_REGISTER = 0x00018050ull;
+
+
+static const uint64_t P9N2_PU_OTPROM0_ECID_PART17_REGISTER = 0x00018011ull;
+
+static const uint64_t P9N2_PU_OTPROM1_ECID_PART17_REGISTER = 0x00018051ull;
+
+
+static const uint64_t P9N2_PU_OTPROM0_ECID_PART18_REGISTER = 0x00018012ull;
+
+static const uint64_t P9N2_PU_OTPROM1_ECID_PART18_REGISTER = 0x00018052ull;
+
+
+static const uint64_t P9N2_PU_OTPROM0_ECID_PART19_REGISTER = 0x00018013ull;
+
+static const uint64_t P9N2_PU_OTPROM1_ECID_PART19_REGISTER = 0x00018053ull;
+
+
+static const uint64_t P9N2_PU_OTPROM0_ECID_PART1_REGISTER = 0x00018001ull;
+
+static const uint64_t P9N2_PU_OTPROM1_ECID_PART1_REGISTER = 0x00018041ull;
+
+
+static const uint64_t P9N2_PU_OTPROM0_ECID_PART20_REGISTER = 0x00018014ull;
+
+static const uint64_t P9N2_PU_OTPROM1_ECID_PART20_REGISTER = 0x00018054ull;
+
+
+static const uint64_t P9N2_PU_OTPROM0_ECID_PART21_REGISTER = 0x00018015ull;
+
+static const uint64_t P9N2_PU_OTPROM1_ECID_PART21_REGISTER = 0x00018055ull;
+
+
+static const uint64_t P9N2_PU_OTPROM0_ECID_PART22_REGISTER = 0x00018016ull;
+
+static const uint64_t P9N2_PU_OTPROM1_ECID_PART22_REGISTER = 0x00018056ull;
+
+
+static const uint64_t P9N2_PU_OTPROM0_ECID_PART23_REGISTER = 0x00018017ull;
+
+static const uint64_t P9N2_PU_OTPROM1_ECID_PART23_REGISTER = 0x00018057ull;
+
+
+static const uint64_t P9N2_PU_OTPROM0_ECID_PART24_REGISTER = 0x00018018ull;
+
+static const uint64_t P9N2_PU_OTPROM1_ECID_PART24_REGISTER = 0x00018058ull;
+
+
+static const uint64_t P9N2_PU_OTPROM0_ECID_PART25_REGISTER = 0x00018019ull;
+
+static const uint64_t P9N2_PU_OTPROM1_ECID_PART25_REGISTER = 0x00018059ull;
+
+
+static const uint64_t P9N2_PU_OTPROM0_ECID_PART26_REGISTER = 0x0001801Aull;
+
+static const uint64_t P9N2_PU_OTPROM1_ECID_PART26_REGISTER = 0x0001805Aull;
+
+
+static const uint64_t P9N2_PU_OTPROM0_ECID_PART27_REGISTER = 0x0001801Bull;
+
+static const uint64_t P9N2_PU_OTPROM1_ECID_PART27_REGISTER = 0x0001805Bull;
+
+
+static const uint64_t P9N2_PU_OTPROM0_ECID_PART28_REGISTER = 0x0001801Cull;
+
+static const uint64_t P9N2_PU_OTPROM1_ECID_PART28_REGISTER = 0x0001805Cull;
+
+
+static const uint64_t P9N2_PU_OTPROM0_ECID_PART29_REGISTER = 0x0001801Dull;
+
+static const uint64_t P9N2_PU_OTPROM1_ECID_PART29_REGISTER = 0x0001805Dull;
+
+
+static const uint64_t P9N2_PU_OTPROM0_ECID_PART2_REGISTER = 0x00018002ull;
+
+static const uint64_t P9N2_PU_OTPROM1_ECID_PART2_REGISTER = 0x00018042ull;
+
+
+static const uint64_t P9N2_PU_OTPROM0_ECID_PART30_REGISTER = 0x0001801Eull;
+
+static const uint64_t P9N2_PU_OTPROM1_ECID_PART30_REGISTER = 0x0001805Eull;
+
+
+static const uint64_t P9N2_PU_OTPROM0_ECID_PART31_REGISTER = 0x0001801Full;
+
+static const uint64_t P9N2_PU_OTPROM1_ECID_PART31_REGISTER = 0x0001805Full;
+
+
+static const uint64_t P9N2_PU_OTPROM0_ECID_PART32_REGISTER = 0x00018020ull;
+
+static const uint64_t P9N2_PU_OTPROM1_ECID_PART32_REGISTER = 0x00018060ull;
+
+
+static const uint64_t P9N2_PU_OTPROM0_ECID_PART33_REGISTER = 0x00018021ull;
+
+static const uint64_t P9N2_PU_OTPROM1_ECID_PART33_REGISTER = 0x00018061ull;
+
+
+static const uint64_t P9N2_PU_OTPROM0_ECID_PART34_REGISTER = 0x00018022ull;
+
+static const uint64_t P9N2_PU_OTPROM1_ECID_PART34_REGISTER = 0x00018062ull;
+
+
+static const uint64_t P9N2_PU_OTPROM0_ECID_PART35_REGISTER = 0x00018023ull;
+
+static const uint64_t P9N2_PU_OTPROM1_ECID_PART35_REGISTER = 0x00018063ull;
+
+
+static const uint64_t P9N2_PU_OTPROM0_ECID_PART36_REGISTER = 0x00018024ull;
+
+static const uint64_t P9N2_PU_OTPROM1_ECID_PART36_REGISTER = 0x00018064ull;
+
+
+static const uint64_t P9N2_PU_OTPROM0_ECID_PART37_REGISTER = 0x00018025ull;
+
+static const uint64_t P9N2_PU_OTPROM1_ECID_PART37_REGISTER = 0x00018065ull;
+
+
+static const uint64_t P9N2_PU_OTPROM0_ECID_PART38_REGISTER = 0x00018026ull;
+
+static const uint64_t P9N2_PU_OTPROM1_ECID_PART38_REGISTER = 0x00018066ull;
+
+
+static const uint64_t P9N2_PU_OTPROM0_ECID_PART39_REGISTER = 0x00018027ull;
+
+static const uint64_t P9N2_PU_OTPROM1_ECID_PART39_REGISTER = 0x00018067ull;
+
+
+static const uint64_t P9N2_PU_OTPROM0_ECID_PART3_REGISTER = 0x00018003ull;
+
+static const uint64_t P9N2_PU_OTPROM1_ECID_PART3_REGISTER = 0x00018043ull;
+
+
+static const uint64_t P9N2_PU_OTPROM0_ECID_PART40_REGISTER = 0x00018028ull;
+
+static const uint64_t P9N2_PU_OTPROM1_ECID_PART40_REGISTER = 0x00018068ull;
+
+
+static const uint64_t P9N2_PU_OTPROM0_ECID_PART41_REGISTER = 0x00018029ull;
+
+static const uint64_t P9N2_PU_OTPROM1_ECID_PART41_REGISTER = 0x00018069ull;
+
+
+static const uint64_t P9N2_PU_OTPROM0_ECID_PART42_REGISTER = 0x0001802Aull;
+
+static const uint64_t P9N2_PU_OTPROM1_ECID_PART42_REGISTER = 0x0001806Aull;
+
+
+static const uint64_t P9N2_PU_OTPROM0_ECID_PART43_REGISTER = 0x0001802Bull;
+
+static const uint64_t P9N2_PU_OTPROM1_ECID_PART43_REGISTER = 0x0001806Bull;
+
+
+static const uint64_t P9N2_PU_OTPROM0_ECID_PART44_REGISTER = 0x0001802Cull;
+
+static const uint64_t P9N2_PU_OTPROM1_ECID_PART44_REGISTER = 0x0001806Cull;
+
+
+static const uint64_t P9N2_PU_OTPROM0_ECID_PART45_REGISTER = 0x0001802Dull;
+
+static const uint64_t P9N2_PU_OTPROM1_ECID_PART45_REGISTER = 0x0001806Dull;
+
+
+static const uint64_t P9N2_PU_OTPROM0_ECID_PART46_REGISTER = 0x0001802Eull;
+
+static const uint64_t P9N2_PU_OTPROM1_ECID_PART46_REGISTER = 0x0001806Eull;
+
+
+static const uint64_t P9N2_PU_OTPROM0_ECID_PART47_REGISTER = 0x0001802Full;
+
+static const uint64_t P9N2_PU_OTPROM1_ECID_PART47_REGISTER = 0x0001806Full;
+
+
+static const uint64_t P9N2_PU_OTPROM0_ECID_PART48_REGISTER = 0x00018030ull;
+
+static const uint64_t P9N2_PU_OTPROM1_ECID_PART48_REGISTER = 0x00018070ull;
+
+
+static const uint64_t P9N2_PU_OTPROM0_ECID_PART49_REGISTER = 0x00018031ull;
+
+static const uint64_t P9N2_PU_OTPROM1_ECID_PART49_REGISTER = 0x00018071ull;
+
+
+static const uint64_t P9N2_PU_OTPROM0_ECID_PART4_REGISTER = 0x00018004ull;
+
+static const uint64_t P9N2_PU_OTPROM1_ECID_PART4_REGISTER = 0x00018044ull;
+
+
+static const uint64_t P9N2_PU_OTPROM0_ECID_PART50_REGISTER = 0x00018032ull;
+
+static const uint64_t P9N2_PU_OTPROM1_ECID_PART50_REGISTER = 0x00018072ull;
+
+
+static const uint64_t P9N2_PU_OTPROM0_ECID_PART51_REGISTER = 0x00018033ull;
+
+static const uint64_t P9N2_PU_OTPROM1_ECID_PART51_REGISTER = 0x00018073ull;
+
+
+static const uint64_t P9N2_PU_OTPROM0_ECID_PART52_REGISTER = 0x00018034ull;
+
+static const uint64_t P9N2_PU_OTPROM1_ECID_PART52_REGISTER = 0x00018074ull;
+
+
+static const uint64_t P9N2_PU_OTPROM0_ECID_PART53_REGISTER = 0x00018035ull;
+
+static const uint64_t P9N2_PU_OTPROM1_ECID_PART53_REGISTER = 0x00018075ull;
+
+
+static const uint64_t P9N2_PU_OTPROM0_ECID_PART54_REGISTER = 0x00018036ull;
+
+static const uint64_t P9N2_PU_OTPROM1_ECID_PART54_REGISTER = 0x00018076ull;
+
+
+static const uint64_t P9N2_PU_OTPROM0_ECID_PART55_REGISTER = 0x00018037ull;
+
+static const uint64_t P9N2_PU_OTPROM1_ECID_PART55_REGISTER = 0x00018077ull;
+
+
+static const uint64_t P9N2_PU_OTPROM0_ECID_PART56_REGISTER = 0x00018038ull;
+
+static const uint64_t P9N2_PU_OTPROM1_ECID_PART56_REGISTER = 0x00018078ull;
+
+
+static const uint64_t P9N2_PU_OTPROM0_ECID_PART57_REGISTER = 0x00018039ull;
+
+static const uint64_t P9N2_PU_OTPROM1_ECID_PART57_REGISTER = 0x00018079ull;
+
+
+static const uint64_t P9N2_PU_OTPROM0_ECID_PART58_REGISTER = 0x0001803Aull;
+
+static const uint64_t P9N2_PU_OTPROM1_ECID_PART58_REGISTER = 0x0001807Aull;
+
+
+static const uint64_t P9N2_PU_OTPROM0_ECID_PART59_REGISTER = 0x0001803Bull;
+
+static const uint64_t P9N2_PU_OTPROM1_ECID_PART59_REGISTER = 0x0001807Bull;
+
+
+static const uint64_t P9N2_PU_OTPROM0_ECID_PART5_REGISTER = 0x00018005ull;
+
+static const uint64_t P9N2_PU_OTPROM1_ECID_PART5_REGISTER = 0x00018045ull;
+
+
+static const uint64_t P9N2_PU_OTPROM0_ECID_PART60_REGISTER = 0x0001803Cull;
+
+static const uint64_t P9N2_PU_OTPROM1_ECID_PART60_REGISTER = 0x0001807Cull;
+
+
+static const uint64_t P9N2_PU_OTPROM0_ECID_PART61_REGISTER = 0x0001803Dull;
+
+static const uint64_t P9N2_PU_OTPROM1_ECID_PART61_REGISTER = 0x0001807Dull;
+
+
+static const uint64_t P9N2_PU_OTPROM0_ECID_PART62_REGISTER = 0x0001803Eull;
+
+static const uint64_t P9N2_PU_OTPROM1_ECID_PART62_REGISTER = 0x0001807Eull;
+
+
+static const uint64_t P9N2_PU_OTPROM0_ECID_PART63_REGISTER = 0x0001803Full;
+
+static const uint64_t P9N2_PU_OTPROM1_ECID_PART63_REGISTER = 0x0001807Full;
+
+
+static const uint64_t P9N2_PU_OTPROM0_ECID_PART6_REGISTER = 0x00018006ull;
+
+static const uint64_t P9N2_PU_OTPROM1_ECID_PART6_REGISTER = 0x00018046ull;
+
+
+static const uint64_t P9N2_PU_OTPROM0_ECID_PART7_REGISTER = 0x00018007ull;
+
+static const uint64_t P9N2_PU_OTPROM1_ECID_PART7_REGISTER = 0x00018047ull;
+
+
+static const uint64_t P9N2_PU_OTPROM0_ECID_PART8_REGISTER = 0x00018008ull;
+
+static const uint64_t P9N2_PU_OTPROM1_ECID_PART8_REGISTER = 0x00018048ull;
+
+
+static const uint64_t P9N2_PU_OTPROM0_ECID_PART9_REGISTER = 0x00018009ull;
+
+static const uint64_t P9N2_PU_OTPROM1_ECID_PART9_REGISTER = 0x00018049ull;
+
+
+static const uint64_t P9N2_PEC_EDRAM_STATUS = 0x0D0F0029ull;
+
+static const uint64_t P9N2_PEC_0_EDRAM_STATUS = 0x0D0F0029ull;
+
+static const uint64_t P9N2_PEC_1_EDRAM_STATUS = 0x0E0F0029ull;
+
+static const uint64_t P9N2_PEC_2_EDRAM_STATUS = 0x0F0F0029ull;
+
+
+static const uint64_t P9N2_PU_EECNT_REG = 0x05012809ull;
+
+
+static const uint64_t P9N2_PU_EFT_HI_PRIOR_RCV_FIFO_ASB = 0x020110C6ull;
+
+
+static const uint64_t P9N2_PU_EFT_HI_PRIOR_RCV_FIFO_BAR = 0x020110C0ull;
+
+
+static const uint64_t P9N2_PU_EFT_HI_PRIOR_RCV_FIFO_CNTL = 0x020110C3ull;
+
+
+static const uint64_t P9N2_PU_EFT_LO_PRIOR_RCV_FIFO_ASB = 0x020110CFull;
+
+
+static const uint64_t P9N2_PU_EFT_LO_PRIOR_RCV_FIFO_BAR = 0x020110C9ull;
+
+
+static const uint64_t P9N2_PU_EFT_LO_PRIOR_RCV_FIFO_CNTL = 0x020110CCull;
+
+
+static const uint64_t P9N2_PU_EFT_MAX_BYTE_CNT = 0x02011059ull;
+
+
+static const uint64_t P9N2_PU_EMPTY_10 = 0x05012910ull;
+
+
+static const uint64_t P9N2_PU_EMPTY_1B = 0x0501291Bull;
+
+
+static const uint64_t P9N2_PU_ENHCA_FIR_ACTION0_REG = 0x05012946ull;
+
+
+static const uint64_t P9N2_PU_ENHCA_FIR_ACTION1_REG = 0x05012947ull;
+
+
+static const uint64_t P9N2_PU_ENHCA_FIR_MASK_REG = 0x05012943ull;
+
+static const uint64_t P9N2_PU_ENHCA_FIR_MASK_REG_AND = 0x05012944ull;
+
+static const uint64_t P9N2_PU_ENHCA_FIR_MASK_REG_OR = 0x05012945ull;
+
+
+static const uint64_t P9N2_PU_ENHCA_FIR_REG = 0x05012940ull;
+
+static const uint64_t P9N2_PU_ENHCA_FIR_REG_AND = 0x05012941ull;
+
+static const uint64_t P9N2_PU_ENHCA_FIR_REG_OR = 0x05012942ull;
+
+
+static const uint64_t P9N2_PU_NPU0_CTL_EPSILON_CONFIG = 0x05011092ull;
+
+static const uint64_t P9N2_PU_NPU2_CTL_EPSILON_CONFIG = 0x05011292ull;
+
+static const uint64_t P9N2_PU_NPU0_SM0_EPSILON_CONFIG = 0x05011002ull;
+
+static const uint64_t P9N2_PU_NPU0_SM1_EPSILON_CONFIG = 0x05011032ull;
+
+static const uint64_t P9N2_PU_NPU0_SM3_EPSILON_CONFIG = 0x05011062ull;
+
+static const uint64_t P9N2_PU_NPU2_SM0_EPSILON_CONFIG = 0x05011202ull;
+
+static const uint64_t P9N2_PU_NPU2_SM1_EPSILON_CONFIG = 0x05011232ull;
+
+static const uint64_t P9N2_PU_NPU2_SM3_EPSILON_CONFIG = 0x05011262ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_CTL_EPSILON_CONFIG = 0x05011492ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM0_EPSILON_CONFIG = 0x05011402ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM1_EPSILON_CONFIG = 0x05011432ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM3_EPSILON_CONFIG = 0x05011462ull;
+
+
+static const uint64_t P9N2_PU_ERAT_STATUS_CONTROL = 0x020110D6ull;
+
+
+static const uint64_t P9N2__CTL_ERROR_BRICK_GROUP_CONFIG = 0x05011694ull;
+
+
+static const uint64_t P9N2_PEC_ERROR_REG = 0x0D0F001Full;
+
+static const uint64_t P9N2_PEC_0_ERROR_REG = 0x0D0F001Full;
+
+static const uint64_t P9N2_PEC_1_ERROR_REG = 0x0E0F001Full;
+
+static const uint64_t P9N2_PEC_2_ERROR_REG = 0x0F0F001Full;
+
+
+static const uint64_t P9N2_PU_NPU_CTL_ERROR_SIG_RXI = 0x0501138Eull;
+
+static const uint64_t P9N2_PU_NPU_SM2_ERROR_SIG_RXI = 0x0501135Eull;
+
+static const uint64_t P9N2__CTL_ERROR_SIG_RXI = 0x0501158Eull;
+
+static const uint64_t P9N2__SM2_ERROR_SIG_RXI = 0x0501155Eull;
+
+
+static const uint64_t P9N2_PU_NPU_CTL_ERROR_SIG_RXO = 0x0501138Full;
+
+static const uint64_t P9N2_PU_NPU_SM2_ERROR_SIG_RXO = 0x0501135Full;
+
+static const uint64_t P9N2__CTL_ERROR_SIG_RXO = 0x0501158Full;
+
+static const uint64_t P9N2__SM2_ERROR_SIG_RXO = 0x0501155Full;
+
+
+static const uint64_t P9N2_PEC_ERROR_STATUS = 0x0D03000Full;
+
+static const uint64_t P9N2_PEC_0_ERROR_STATUS = 0x0D03000Full;
+
+static const uint64_t P9N2_PEC_1_ERROR_STATUS = 0x0E03000Full;
+
+static const uint64_t P9N2_PEC_2_ERROR_STATUS = 0x0F03000Full;
+
+
+static const uint64_t P9N2_CAPP_ERRRPT = 0x0201080Bull;
+
+static const uint64_t P9N2_CAPP_0_ERRRPT = 0x0201080Bull;
+
+static const uint64_t P9N2_CAPP_1_ERRRPT = 0x0401080Bull;
+
+
+static const uint64_t P9N2__SM2_ERR_FIRST = 0x05011643ull;
+
+
+static const uint64_t P9N2__SM2_ERR_HOLD = 0x05011640ull;
+
+
+static const uint64_t P9N2__CTL_ERR_INFO_NPU_RING_ADDR = 0x05011692ull;
+
+
+static const uint64_t P9N2__SM2_ERR_MASK = 0x05011642ull;
+
+
+static const uint64_t P9N2_CAPP_ERR_RPT_CLR = 0x02010813ull;
+
+static const uint64_t P9N2_CAPP_0_ERR_RPT_CLR = 0x02010813ull;
+
+static const uint64_t P9N2_CAPP_1_ERR_RPT_CLR = 0x04010813ull;
+
+
+static const uint64_t P9N2__CTL_ERR_SCOPE_CTL_CONFIG = 0x05011691ull;
+
+
+static const uint64_t P9N2_PEC_ERR_STATUS_REG = 0x0D050013ull;
+
+static const uint64_t P9N2_PEC_0_ERR_STATUS_REG = 0x0D050013ull;
+
+static const uint64_t P9N2_PEC_1_ERR_STATUS_REG = 0x0E050013ull;
+
+static const uint64_t P9N2_PEC_2_ERR_STATUS_REG = 0x0F050013ull;
+
+
+static const uint64_t P9N2_PU_ESB_CI_BASE = 0x05012916ull;
+
+
+static const uint64_t P9N2_PU_ESB_NOTIFY = 0x05012917ull;
+
+
+static const uint64_t P9N2_PU_EXPORT_REGL_CTRL = 0x0001000Eull;
+
+
+static const uint64_t P9N2_PU_EXTENDED_STATUS_B = 0x000A000Cull;
+
+
+static const uint64_t P9N2_PU_EXTENDED_STATUS_C = 0x000A100Cull;
+
+
+static const uint64_t P9N2_PU_EXTENDED_STATUS_D = 0x000A200Cull;
+
+
+static const uint64_t P9N2_PU_EXTENDED_STATUS_E = 0x000A300Cull;
+
+
+static const uint64_t P9N2_PU_PB_CENT_SM1_EXTFIR_ACTION0_REG = 0x05011C34ull;
+
+
+static const uint64_t P9N2_PU_PB_CENT_SM1_EXTFIR_ACTION1_REG = 0x05011C35ull;
+
+
+static const uint64_t P9N2_PU_PB_CENT_SM1_EXTFIR_MASK_REG = 0x05011C31ull;
+
+static const uint64_t P9N2_PU_PB_CENT_SM1_EXTFIR_MASK_REG_AND = 0x05011C32ull;
+
+static const uint64_t P9N2_PU_PB_CENT_SM1_EXTFIR_MASK_REG_OR = 0x05011C33ull;
+
+
+static const uint64_t P9N2_PU_PB_CENT_SM1_EXTFIR_REG = 0x05011C2Eull;
+
+static const uint64_t P9N2_PU_PB_CENT_SM1_EXTFIR_REG_AND = 0x05011C2Full;
+
+static const uint64_t P9N2_PU_PB_CENT_SM1_EXTFIR_REG_OR = 0x05011C30ull;
+
+
+static const uint64_t P9N2__CTL_FENCE_0_CONFIG = 0x0501168Aull;
+
+
+static const uint64_t P9N2__CTL_FENCE_1_CONFIG = 0x0501168Bull;
+
+
+static const uint64_t P9N2_PU_NPU_SM0_FENCE_2_CONFIG = 0x05011700ull;
+
+
+static const uint64_t P9N2_NV_1_FENCE_CONTROL0 = 0x050110E8ull;
+
+static const uint64_t P9N2_NV_5_FENCE_CONTROL0 = 0x050114E8ull;
+
+static const uint64_t P9N2_PU_NPU2_NTL1_FENCE_CONTROL0 = 0x050112E8ull;
+
+
+static const uint64_t P9N2_NV_1_FENCE_CONTROL1 = 0x050110E9ull;
+
+static const uint64_t P9N2_NV_5_FENCE_CONTROL1 = 0x050114E9ull;
+
+static const uint64_t P9N2_PU_NPU2_NTL1_FENCE_CONTROL1 = 0x050112E9ull;
+
+
+static const uint64_t P9N2__CTL_FENCE_STATE = 0x05011696ull;
+
+
+static const uint64_t P9N2_PU_FI2C_CFG_PPE = 0xC0000800ull;
+
+static const uint64_t P9N2_PU_FI2C_CFG_PPE1 = 0xC0000810ull;
+
+static const uint64_t P9N2_PU_FI2C_CFG_PPE2 = 0xC0000818ull;
+
+
+static const uint64_t P9N2_PU_FI2C_SCFG0_PPE = 0xC0000860ull;
+
+static const uint64_t P9N2_PU_FI2C_SCFG0_PPE1 = 0xC0000870ull;
+
+static const uint64_t P9N2_PU_FI2C_SCFG0_PPE2 = 0xC0000878ull;
+
+
+static const uint64_t P9N2_PU_FI2C_SCFG1_PPE = 0xC0000880ull;
+
+static const uint64_t P9N2_PU_FI2C_SCFG1_PPE1 = 0xC0000890ull;
+
+static const uint64_t P9N2_PU_FI2C_SCFG1_PPE2 = 0xC0000898ull;
+
+
+static const uint64_t P9N2_PU_FI2C_SCFG2_PPE = 0xC00008A0ull;
+
+static const uint64_t P9N2_PU_FI2C_SCFG2_PPE1 = 0xC00008B0ull;
+
+static const uint64_t P9N2_PU_FI2C_SCFG2_PPE2 = 0xC00008B8ull;
+
+
+static const uint64_t P9N2_PU_FI2C_SCFG3_PPE = 0xC00008C0ull;
+
+static const uint64_t P9N2_PU_FI2C_SCFG3_PPE1 = 0xC00008D0ull;
+
+static const uint64_t P9N2_PU_FI2C_SCFG3_PPE2 = 0xC00008D8ull;
+
+
+static const uint64_t P9N2_PU_FI2C_STAT_PPE = 0xC0000820ull;
+
+
+static const uint64_t P9N2_PU_FIFO1_REGISTER_READ_B = 0x000A0004ull;
+
+
+static const uint64_t P9N2_PU_FIFO1_REGISTER_READ_C = 0x000A1004ull;
+
+
+static const uint64_t P9N2_PU_FIFO1_REGISTER_READ_D = 0x000A2004ull;
+
+
+static const uint64_t P9N2_PU_FIFO1_REGISTER_READ_E = 0x000A3004ull;
+
+
+static const uint64_t P9N2_PU_FIFO4_REGISTER_READ_B = 0x000A0012ull;
+
+
+static const uint64_t P9N2_PU_FIFO4_REGISTER_READ_C = 0x000A1012ull;
+
+
+static const uint64_t P9N2_PU_FIFO4_REGISTER_READ_D = 0x000A2012ull;
+
+
+static const uint64_t P9N2_PU_FIFO4_REGISTER_READ_E = 0x000A3012ull;
+
+
+static const uint64_t P9N2_PU_FIR_ACTION0_REG = 0x04011806ull;
+
+static const uint64_t P9N2_CAPP_FIR_ACTION0_REG = 0x02010806ull;
+
+static const uint64_t P9N2_CAPP_0_FIR_ACTION0_REG = 0x02010806ull;
+
+static const uint64_t P9N2_CAPP_1_FIR_ACTION0_REG = 0x04010806ull;
+
+
+static const uint64_t P9N2_PEC_FIR_ACTION0_REG = 0x0D010C06ull;
+
+static const uint64_t P9N2_PEC_0_FIR_ACTION0_REG = 0x0D010C06ull;
+
+static const uint64_t P9N2_PEC_1_FIR_ACTION0_REG = 0x0E010C06ull;
+
+static const uint64_t P9N2_PEC_2_FIR_ACTION0_REG = 0x0F010C06ull;
+
+
+static const uint64_t P9N2_PU_FIR_ACTION0_REG_0 = 0x05013C06ull;
+
+
+static const uint64_t P9N2_PU_FIR_ACTION0_REG_1 = 0x05013C46ull;
+
+
+static const uint64_t P9N2_PU_FIR_ACTION0_REG_2 = 0x05013C86ull;
+
+
+static const uint64_t P9N2_PU_FIR_ACTION1_REG = 0x04011807ull;
+
+static const uint64_t P9N2_CAPP_FIR_ACTION1_REG = 0x02010807ull;
+
+static const uint64_t P9N2_CAPP_0_FIR_ACTION1_REG = 0x02010807ull;
+
+static const uint64_t P9N2_CAPP_1_FIR_ACTION1_REG = 0x04010807ull;
+
+
+static const uint64_t P9N2_PEC_FIR_ACTION1_REG = 0x0D010C07ull;
+
+static const uint64_t P9N2_PEC_0_FIR_ACTION1_REG = 0x0D010C07ull;
+
+static const uint64_t P9N2_PEC_1_FIR_ACTION1_REG = 0x0E010C07ull;
+
+static const uint64_t P9N2_PEC_2_FIR_ACTION1_REG = 0x0F010C07ull;
+
+
+static const uint64_t P9N2_PU_FIR_ACTION1_REG_0 = 0x05013C07ull;
+
+
+static const uint64_t P9N2_PU_FIR_ACTION1_REG_1 = 0x05013C47ull;
+
+
+static const uint64_t P9N2_PU_FIR_ACTION1_REG_2 = 0x05013C87ull;
+
+
+static const uint64_t P9N2_PEC_FIR_MASK = 0x0D040002ull;
+
+static const uint64_t P9N2_PEC_0_FIR_MASK = 0x0D040002ull;
+
+static const uint64_t P9N2_PEC_1_FIR_MASK = 0x0E040002ull;
+
+static const uint64_t P9N2_PEC_2_FIR_MASK = 0x0F040002ull;
+
+
+static const uint64_t P9N2_PU_FIR_MASK_REG = 0x04011803ull;
+
+static const uint64_t P9N2_PU_FIR_MASK_REG_AND = 0x04011804ull;
+
+static const uint64_t P9N2_PU_FIR_MASK_REG_OR = 0x04011805ull;
+
+static const uint64_t P9N2_CAPP_FIR_MASK_REG = 0x02010803ull;
+
+static const uint64_t P9N2_CAPP_FIR_MASK_REG_AND = 0x02010804ull;
+
+static const uint64_t P9N2_CAPP_FIR_MASK_REG_OR = 0x02010805ull;
+
+static const uint64_t P9N2_CAPP_0_FIR_MASK_REG = 0x02010803ull;
+
+static const uint64_t P9N2_CAPP_0_FIR_MASK_REG_AND = 0x02010804ull;
+
+static const uint64_t P9N2_CAPP_0_FIR_MASK_REG_OR = 0x02010805ull;
+
+static const uint64_t P9N2_CAPP_1_FIR_MASK_REG = 0x04010803ull;
+
+static const uint64_t P9N2_CAPP_1_FIR_MASK_REG_AND = 0x04010804ull;
+
+static const uint64_t P9N2_CAPP_1_FIR_MASK_REG_OR = 0x04010805ull;
+
+
+static const uint64_t P9N2_PEC_FIR_MASK_REG = 0x0D010C03ull;
+
+static const uint64_t P9N2_PEC_FIR_MASK_REG_AND = 0x0D010C04ull;
+
+static const uint64_t P9N2_PEC_FIR_MASK_REG_OR = 0x0D010C05ull;
+
+static const uint64_t P9N2_PEC_0_FIR_MASK_REG = 0x0D010C03ull;
+
+static const uint64_t P9N2_PEC_0_FIR_MASK_REG_AND = 0x0D010C04ull;
+
+static const uint64_t P9N2_PEC_0_FIR_MASK_REG_OR = 0x0D010C05ull;
+
+static const uint64_t P9N2_PEC_1_FIR_MASK_REG = 0x0E010C03ull;
+
+static const uint64_t P9N2_PEC_1_FIR_MASK_REG_AND = 0x0E010C04ull;
+
+static const uint64_t P9N2_PEC_1_FIR_MASK_REG_OR = 0x0E010C05ull;
+
+static const uint64_t P9N2_PEC_2_FIR_MASK_REG = 0x0F010C03ull;
+
+static const uint64_t P9N2_PEC_2_FIR_MASK_REG_AND = 0x0F010C04ull;
+
+static const uint64_t P9N2_PEC_2_FIR_MASK_REG_OR = 0x0F010C05ull;
+
+
+static const uint64_t P9N2_PU_FIR_MASK_REGISTER = 0x00088008ull;
+
+
+static const uint64_t P9N2_PU_FIR_MASK_REG_0 = 0x05013C03ull;
+
+static const uint64_t P9N2_PU_FIR_MASK_REG_0_AND = 0x05013C04ull;
+
+static const uint64_t P9N2_PU_FIR_MASK_REG_0_OR = 0x05013C05ull;
+
+
+static const uint64_t P9N2_PU_FIR_MASK_REG_1 = 0x05013C43ull;
+
+static const uint64_t P9N2_PU_FIR_MASK_REG_1_AND = 0x05013C44ull;
+
+static const uint64_t P9N2_PU_FIR_MASK_REG_1_OR = 0x05013C45ull;
+
+
+static const uint64_t P9N2_PU_FIR_MASK_REG_2 = 0x05013C83ull;
+
+static const uint64_t P9N2_PU_FIR_MASK_REG_2_AND = 0x05013C84ull;
+
+static const uint64_t P9N2_PU_FIR_MASK_REG_2_OR = 0x05013C85ull;
+
+
+static const uint64_t P9N2_PU_FIR_REG = 0x04011800ull;
+
+static const uint64_t P9N2_PU_FIR_REG_AND = 0x04011801ull;
+
+static const uint64_t P9N2_PU_FIR_REG_OR = 0x04011802ull;
+
+static const uint64_t P9N2_CAPP_FIR_REG = 0x02010800ull;
+
+static const uint64_t P9N2_CAPP_FIR_REG_AND = 0x02010801ull;
+
+static const uint64_t P9N2_CAPP_FIR_REG_OR = 0x02010802ull;
+
+static const uint64_t P9N2_CAPP_0_FIR_REG = 0x02010800ull;
+
+static const uint64_t P9N2_CAPP_0_FIR_REG_AND = 0x02010801ull;
+
+static const uint64_t P9N2_CAPP_0_FIR_REG_OR = 0x02010802ull;
+
+static const uint64_t P9N2_CAPP_1_FIR_REG = 0x04010800ull;
+
+static const uint64_t P9N2_CAPP_1_FIR_REG_AND = 0x04010801ull;
+
+static const uint64_t P9N2_CAPP_1_FIR_REG_OR = 0x04010802ull;
+
+
+static const uint64_t P9N2_PHB_FIR_REG = 0x0D010908ull;
+
+static const uint64_t P9N2_PHB_FIR_REG_AND = 0x0D010909ull;
+
+static const uint64_t P9N2_PHB_FIR_REG_OR = 0x0D01090Aull;
+
+static const uint64_t P9N2_PHB_0_FIR_REG = 0x0D010908ull;
+
+static const uint64_t P9N2_PHB_0_FIR_REG_AND = 0x0D010909ull;
+
+static const uint64_t P9N2_PHB_0_FIR_REG_OR = 0x0D01090Aull;
+
+static const uint64_t P9N2_PHB_1_FIR_REG = 0x0E010908ull;
+
+static const uint64_t P9N2_PHB_1_FIR_REG_AND = 0x0E010909ull;
+
+static const uint64_t P9N2_PHB_1_FIR_REG_OR = 0x0E01090Aull;
+
+static const uint64_t P9N2_PHB_2_FIR_REG = 0x0E010948ull;
+
+static const uint64_t P9N2_PHB_2_FIR_REG_AND = 0x0E010949ull;
+
+static const uint64_t P9N2_PHB_2_FIR_REG_OR = 0x0E01094Aull;
+
+static const uint64_t P9N2_PHB_3_FIR_REG = 0x0F010908ull;
+
+static const uint64_t P9N2_PHB_3_FIR_REG_AND = 0x0F010909ull;
+
+static const uint64_t P9N2_PHB_3_FIR_REG_OR = 0x0F01090Aull;
+
+static const uint64_t P9N2_PHB_4_FIR_REG = 0x0F010948ull;
+
+static const uint64_t P9N2_PHB_4_FIR_REG_AND = 0x0F010949ull;
+
+static const uint64_t P9N2_PHB_4_FIR_REG_OR = 0x0F01094Aull;
+
+static const uint64_t P9N2_PHB_5_FIR_REG = 0x0F010988ull;
+
+static const uint64_t P9N2_PHB_5_FIR_REG_AND = 0x0F010989ull;
+
+static const uint64_t P9N2_PHB_5_FIR_REG_OR = 0x0F01098Aull;
+
+
+static const uint64_t P9N2_PU_FIR_REG_0 = 0x05013C00ull;
+
+static const uint64_t P9N2_PU_FIR_REG_0_AND = 0x05013C01ull;
+
+static const uint64_t P9N2_PU_FIR_REG_0_OR = 0x05013C02ull;
+
+
+static const uint64_t P9N2_PU_FIR_REG_1 = 0x05013C40ull;
+
+static const uint64_t P9N2_PU_FIR_REG_1_AND = 0x05013C41ull;
+
+static const uint64_t P9N2_PU_FIR_REG_1_OR = 0x05013C42ull;
+
+
+static const uint64_t P9N2_PU_FIR_REG_2 = 0x05013C80ull;
+
+static const uint64_t P9N2_PU_FIR_REG_2_AND = 0x05013C81ull;
+
+static const uint64_t P9N2_PU_FIR_REG_2_OR = 0x05013C82ull;
+
+
+static const uint64_t P9N2_PEC_FIR_STATUS_REG = 0x0D010C00ull;
+
+static const uint64_t P9N2_PEC_FIR_STATUS_REG_AND = 0x0D010C01ull;
+
+static const uint64_t P9N2_PEC_FIR_STATUS_REG_OR = 0x0D010C02ull;
+
+static const uint64_t P9N2_PEC_0_FIR_STATUS_REG = 0x0D010C00ull;
+
+static const uint64_t P9N2_PEC_0_FIR_STATUS_REG_AND = 0x0D010C01ull;
+
+static const uint64_t P9N2_PEC_0_FIR_STATUS_REG_OR = 0x0D010C02ull;
+
+static const uint64_t P9N2_PEC_1_FIR_STATUS_REG = 0x0E010C00ull;
+
+static const uint64_t P9N2_PEC_1_FIR_STATUS_REG_AND = 0x0E010C01ull;
+
+static const uint64_t P9N2_PEC_1_FIR_STATUS_REG_OR = 0x0E010C02ull;
+
+static const uint64_t P9N2_PEC_2_FIR_STATUS_REG = 0x0F010C00ull;
+
+static const uint64_t P9N2_PEC_2_FIR_STATUS_REG_AND = 0x0F010C01ull;
+
+static const uint64_t P9N2_PEC_2_FIR_STATUS_REG_OR = 0x0F010C02ull;
+
+
+static const uint64_t P9N2_PU_FIR_WOF_REG = 0x04011808ull;
+
+static const uint64_t P9N2_PEC_FIR_WOF_REG = 0x0D010C08ull;
+
+static const uint64_t P9N2_PEC_0_FIR_WOF_REG = 0x0D010C08ull;
+
+static const uint64_t P9N2_PEC_1_FIR_WOF_REG = 0x0E010C08ull;
+
+static const uint64_t P9N2_PEC_2_FIR_WOF_REG = 0x0F010C08ull;
+
+
+static const uint64_t P9N2_CAPP_FLUSHCPIG = 0x02010820ull;
+
+static const uint64_t P9N2_CAPP_0_FLUSHCPIG = 0x02010820ull;
+
+static const uint64_t P9N2_CAPP_1_FLUSHCPIG = 0x04010820ull;
+
+
+static const uint64_t P9N2_CAPP_FLUSHSHUE = 0x0201080Full;
+
+static const uint64_t P9N2_CAPP_0_FLUSHSHUE = 0x0201080Full;
+
+static const uint64_t P9N2_CAPP_1_FLUSHSHUE = 0x0401080Full;
+
+
+static const uint64_t P9N2_PU_FORCE_ECC_REG = 0x0009000Dull;
+
+
+static const uint64_t P9N2__CTL_FREEZE_0_CONFIG = 0x05011688ull;
+
+
+static const uint64_t P9N2__CTL_FREEZE_1_CONFIG = 0x05011689ull;
+
+
+static const uint64_t P9N2__CTL_FREEZE_STATE = 0x05011695ull;
+
+
+static const uint64_t P9N2_PU_FSB_DOWNFIFO_DATA_IN = 0x000B0010ull;
+
+
+static const uint64_t P9N2_PU_FSB_DOWNFIFO_MTC = 0x000B0016ull;
+
+
+static const uint64_t P9N2_PU_FSB_DOWNFIFO_REQ_RESET = 0x000B0013ull;
+
+
+static const uint64_t P9N2_PU_FSB_DOWNFIFO_SIG_EOT = 0x000B0012ull;
+
+
+static const uint64_t P9N2_PU_FSB_DOWNFIFO_STATUS = 0x000B0011ull;
+
+
+static const uint64_t P9N2_PU_FSB_UPFIFO_ACK_EOT = 0x000B0005ull;
+
+
+static const uint64_t P9N2_PU_FSB_UPFIFO_DATA_OUT = 0x000B0000ull;
+
+
+static const uint64_t P9N2_PU_FSB_UPFIFO_RESET = 0x000B0004ull;
+
+
+static const uint64_t P9N2_PU_FSB_UPFIFO_STATUS = 0x000B0001ull;
+
+
+static const uint64_t P9N2_PU_NPU0_CTL_GENID_BAR = 0x05011097ull;
+
+static const uint64_t P9N2_PU_NPU2_CTL_GENID_BAR = 0x05011297ull;
+
+static const uint64_t P9N2_PU_NPU0_SM0_GENID_BAR = 0x05011007ull;
+
+static const uint64_t P9N2_PU_NPU0_SM1_GENID_BAR = 0x05011037ull;
+
+static const uint64_t P9N2_PU_NPU0_SM3_GENID_BAR = 0x05011067ull;
+
+static const uint64_t P9N2_PU_NPU2_SM0_GENID_BAR = 0x05011207ull;
+
+static const uint64_t P9N2_PU_NPU2_SM1_GENID_BAR = 0x05011237ull;
+
+static const uint64_t P9N2_PU_NPU2_SM3_GENID_BAR = 0x05011267ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_CTL_GENID_BAR = 0x05011497ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM0_GENID_BAR = 0x05011407ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM1_GENID_BAR = 0x05011437ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM3_GENID_BAR = 0x05011467ull;
+
+
+static const uint64_t P9N2_NV_1_GENID_HEAD0 = 0x050110E0ull;
+
+static const uint64_t P9N2_NV_5_GENID_HEAD0 = 0x050114E0ull;
+
+static const uint64_t P9N2_PU_NPU2_NTL1_GENID_HEAD0 = 0x050112E0ull;
+
+
+static const uint64_t P9N2_NV_1_GENID_HEAD1 = 0x050110E1ull;
+
+static const uint64_t P9N2_NV_5_GENID_HEAD1 = 0x050114E1ull;
+
+static const uint64_t P9N2_PU_NPU2_NTL1_GENID_HEAD1 = 0x050112E1ull;
+
+
+static const uint64_t P9N2_NV_1_GENID_TAIL0 = 0x050110E2ull;
+
+static const uint64_t P9N2_NV_5_GENID_TAIL0 = 0x050114E2ull;
+
+static const uint64_t P9N2_PU_NPU2_NTL1_GENID_TAIL0 = 0x050112E2ull;
+
+
+static const uint64_t P9N2_NV_1_GENID_TAIL1 = 0x050110E3ull;
+
+static const uint64_t P9N2_NV_5_GENID_TAIL1 = 0x050114E3ull;
+
+static const uint64_t P9N2_PU_NPU2_NTL1_GENID_TAIL1 = 0x050112E3ull;
+
+
+static const uint64_t P9N2_PU_GPE0_GPEDBG_OCI = 0xC0000010ull;
+
+static const uint64_t P9N2_PU_GPE0_GPEDBG_SCOM = 0x00060002ull;
+
+
+static const uint64_t P9N2_PU_GPE0_GPEIVPR_OCI = 0xC0000008ull;
+
+static const uint64_t P9N2_PU_GPE0_GPEIVPR_SCOM = 0x00060001ull;
+
+
+static const uint64_t P9N2_PU_GPE0_GPEMACR_OCI = 0xC0000020ull;
+
+static const uint64_t P9N2_PU_GPE0_GPEMACR_SCOM = 0x00060004ull;
+
+
+static const uint64_t P9N2_PU_GPE0_GPENXIXCR_OCI = 0xC0000080ull;
+
+static const uint64_t P9N2_PU_GPE0_GPENXIXCR_SCOM = 0x00060010ull;
+
+
+static const uint64_t P9N2_PU_GPE0_GPESTR_OCI = 0xC0000018ull;
+
+static const uint64_t P9N2_PU_GPE0_GPESTR_SCOM = 0x00060003ull;
+
+
+static const uint64_t P9N2_PU_GPE0_GPETSEL_OCI = 0xC0000000ull;
+
+static const uint64_t P9N2_PU_GPE0_GPETSEL_SCOM = 0x00060000ull;
+
+
+static const uint64_t P9N2_PU_GPE0_GPEXIEDR_OCI = 0xC0000118ull;
+
+static const uint64_t P9N2_PU_GPE0_GPEXIEDR_SCOM = 0x00060023ull;
+
+
+static const uint64_t P9N2_PU_GPE0_GPEXIIAR_OCI = 0xC0000128ull;
+
+static const uint64_t P9N2_PU_GPE0_GPEXIIAR_SCOM = 0x00060025ull;
+
+
+static const uint64_t P9N2_PU_GPE0_GPEXIIR_OCI = 0xC0000120ull;
+
+static const uint64_t P9N2_PU_GPE0_GPEXIIR_SCOM = 0x00060024ull;
+
+
+static const uint64_t P9N2_PU_GPE0_GPEXISPRG0_OCI = 0xC0000110ull;
+
+static const uint64_t P9N2_PU_GPE0_GPEXISPRG0_SCOM = 0x00060022ull;
+
+
+static const uint64_t P9N2_PU_GPE0_GPEXIXCR_OCI = 0xC0000100ull;
+
+static const uint64_t P9N2_PU_GPE0_GPEXIXCR_SCOM = 0x00060020ull;
+
+
+static const uint64_t P9N2_PU_GPE0_GPEXIXSR_OCI = 0xC0000108ull;
+
+static const uint64_t P9N2_PU_GPE0_GPEXIXSR_SCOM = 0x00060021ull;
+
+
+static const uint64_t P9N2_PU_GPE0_MIB_XIDCAC_OCI = 0xC00000D0ull;
+
+static const uint64_t P9N2_PU_GPE0_MIB_XIDCAC_SCOM = 0x0006001Aull;
+
+
+static const uint64_t P9N2_PU_GPE0_MIB_XIICAC = 0x00060019ull;
+
+
+static const uint64_t P9N2_PU_GPE0_MIB_XIMEM = 0x00060017ull;
+
+
+static const uint64_t P9N2_PU_GPE0_MIB_XISGB = 0x00060018ull;
+
+
+static const uint64_t P9N2_PU_GPE0_MIB_XISIB_OCI = 0xC00000B0ull;
+
+static const uint64_t P9N2_PU_GPE0_MIB_XISIB_SCOM = 0x00060016ull;
+
+
+static const uint64_t P9N2_PU_GPE0_PPE_XIDBGPRO = 0x00060015ull;
+
+
+static const uint64_t P9N2_PU_GPE0_PPE_XIRAMDBG = 0x00060013ull;
+
+
+static const uint64_t P9N2_PU_GPE0_PPE_XIRAMEDR = 0x00060014ull;
+
+
+static const uint64_t P9N2_PU_GPE0_PPE_XIRAMGA = 0x00060012ull;
+
+
+static const uint64_t P9N2_PU_GPE0_PPE_XIRAMRA = 0x00060011ull;
+
+
+static const uint64_t P9N2_PU_GPE0_PPE_XIXCR = 0x00060010ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+
+static const uint64_t P9N2_PU_GPE1_GPEDBG_OCI = 0xC0010010ull;
+
+static const uint64_t P9N2_PU_GPE1_GPEDBG_SCOM = 0x00062002ull;
+
+
+static const uint64_t P9N2_PU_GPE1_GPEIVPR_OCI = 0xC0010008ull;
+
+static const uint64_t P9N2_PU_GPE1_GPEIVPR_SCOM = 0x00062001ull;
+
+
+static const uint64_t P9N2_PU_GPE1_GPEMACR_OCI = 0xC0010020ull;
+
+static const uint64_t P9N2_PU_GPE1_GPEMACR_SCOM = 0x00062004ull;
+
+
+static const uint64_t P9N2_PU_GPE1_GPENXIXCR_OCI = 0xC0010080ull;
+
+static const uint64_t P9N2_PU_GPE1_GPENXIXCR_SCOM = 0x00062010ull;
+
+
+static const uint64_t P9N2_PU_GPE1_GPESTR_OCI = 0xC0010018ull;
+
+static const uint64_t P9N2_PU_GPE1_GPESTR_SCOM = 0x00062003ull;
+
+
+static const uint64_t P9N2_PU_GPE1_GPETSEL_OCI = 0xC0010000ull;
+
+static const uint64_t P9N2_PU_GPE1_GPETSEL_SCOM = 0x00062000ull;
+
+
+static const uint64_t P9N2_PU_GPE1_GPEXIEDR_OCI = 0xC0010118ull;
+
+static const uint64_t P9N2_PU_GPE1_GPEXIEDR_SCOM = 0x00062023ull;
+
+
+static const uint64_t P9N2_PU_GPE1_GPEXIIAR_OCI = 0xC0010128ull;
+
+static const uint64_t P9N2_PU_GPE1_GPEXIIAR_SCOM = 0x00062025ull;
+
+
+static const uint64_t P9N2_PU_GPE1_GPEXIIR_OCI = 0xC0010120ull;
+
+static const uint64_t P9N2_PU_GPE1_GPEXIIR_SCOM = 0x00062024ull;
+
+
+static const uint64_t P9N2_PU_GPE1_GPEXISPRG0_OCI = 0xC0010110ull;
+
+static const uint64_t P9N2_PU_GPE1_GPEXISPRG0_SCOM = 0x00062022ull;
+
+
+static const uint64_t P9N2_PU_GPE1_GPEXIXCR_OCI = 0xC0010100ull;
+
+static const uint64_t P9N2_PU_GPE1_GPEXIXCR_SCOM = 0x00062020ull;
+
+
+static const uint64_t P9N2_PU_GPE1_GPEXIXSR_OCI = 0xC0010108ull;
+
+static const uint64_t P9N2_PU_GPE1_GPEXIXSR_SCOM = 0x00062021ull;
+
+
+static const uint64_t P9N2_PU_GPE1_MIB_XIDCAC_OCI = 0xC00100D0ull;
+
+static const uint64_t P9N2_PU_GPE1_MIB_XIDCAC_SCOM = 0x0006201Aull;
+
+
+static const uint64_t P9N2_PU_GPE1_MIB_XIICAC = 0x00062019ull;
+
+
+static const uint64_t P9N2_PU_GPE1_MIB_XIMEM = 0x00062017ull;
+
+
+static const uint64_t P9N2_PU_GPE1_MIB_XISGB = 0x00062018ull;
+
+
+static const uint64_t P9N2_PU_GPE1_MIB_XISIB_OCI = 0xC00100B0ull;
+
+static const uint64_t P9N2_PU_GPE1_MIB_XISIB_SCOM = 0x00062016ull;
+
+
+static const uint64_t P9N2_PU_GPE1_PPE_XIDBGPRO = 0x00062015ull;
+
+
+static const uint64_t P9N2_PU_GPE1_PPE_XIRAMDBG = 0x00062013ull;
+
+
+static const uint64_t P9N2_PU_GPE1_PPE_XIRAMEDR = 0x00062014ull;
+
+
+static const uint64_t P9N2_PU_GPE1_PPE_XIRAMGA = 0x00062012ull;
+
+
+static const uint64_t P9N2_PU_GPE1_PPE_XIRAMRA = 0x00062011ull;
+
+
+static const uint64_t P9N2_PU_GPE1_PPE_XIXCR = 0x00062010ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+
+static const uint64_t P9N2_PU_GPE2_GPEDBG_OCI = 0xC0020010ull;
+
+static const uint64_t P9N2_PU_GPE2_GPEDBG_SCOM = 0x00064002ull;
+
+
+static const uint64_t P9N2_PU_GPE2_GPEIVPR_OCI = 0xC0020008ull;
+
+static const uint64_t P9N2_PU_GPE2_GPEIVPR_SCOM = 0x00064001ull;
+
+
+static const uint64_t P9N2_PU_GPE2_GPEMACR_OCI = 0xC0020020ull;
+
+static const uint64_t P9N2_PU_GPE2_GPEMACR_SCOM = 0x00064004ull;
+
+
+static const uint64_t P9N2_PU_GPE2_GPENXIXCR_OCI = 0xC0020080ull;
+
+static const uint64_t P9N2_PU_GPE2_GPENXIXCR_SCOM = 0x00064010ull;
+
+
+static const uint64_t P9N2_PU_GPE2_GPESTR_OCI = 0xC0020018ull;
+
+static const uint64_t P9N2_PU_GPE2_GPESTR_SCOM = 0x00064003ull;
+
+
+static const uint64_t P9N2_PU_GPE2_GPETSEL_OCI = 0xC0020000ull;
+
+static const uint64_t P9N2_PU_GPE2_GPETSEL_SCOM = 0x00064000ull;
+
+
+static const uint64_t P9N2_PU_GPE2_GPEXIEDR_OCI = 0xC0020118ull;
+
+static const uint64_t P9N2_PU_GPE2_GPEXIEDR_SCOM = 0x00064023ull;
+
+
+static const uint64_t P9N2_PU_GPE2_GPEXIIAR_OCI = 0xC0020128ull;
+
+static const uint64_t P9N2_PU_GPE2_GPEXIIAR_SCOM = 0x00064025ull;
+
+
+static const uint64_t P9N2_PU_GPE2_GPEXIIR_OCI = 0xC0020120ull;
+
+static const uint64_t P9N2_PU_GPE2_GPEXIIR_SCOM = 0x00064024ull;
+
+
+static const uint64_t P9N2_PU_GPE2_GPEXISPRG0_OCI = 0xC0020110ull;
+
+static const uint64_t P9N2_PU_GPE2_GPEXISPRG0_SCOM = 0x00064022ull;
+
+
+static const uint64_t P9N2_PU_GPE2_GPEXIXCR_OCI = 0xC0020100ull;
+
+static const uint64_t P9N2_PU_GPE2_GPEXIXCR_SCOM = 0x00064020ull;
+
+
+static const uint64_t P9N2_PU_GPE2_GPEXIXSR_OCI = 0xC0020108ull;
+
+static const uint64_t P9N2_PU_GPE2_GPEXIXSR_SCOM = 0x00064021ull;
+
+
+static const uint64_t P9N2_PU_GPE2_MIB_XIDCAC_OCI = 0xC00200D0ull;
+
+static const uint64_t P9N2_PU_GPE2_MIB_XIDCAC_SCOM = 0x0006401Aull;
+
+
+static const uint64_t P9N2_PU_GPE2_MIB_XIICAC = 0x00064019ull;
+
+
+static const uint64_t P9N2_PU_GPE2_MIB_XIMEM = 0x00064017ull;
+
+
+static const uint64_t P9N2_PU_GPE2_MIB_XISGB = 0x00064018ull;
+
+
+static const uint64_t P9N2_PU_GPE2_MIB_XISIB_OCI = 0xC00200B0ull;
+
+static const uint64_t P9N2_PU_GPE2_MIB_XISIB_SCOM = 0x00064016ull;
+
+
+static const uint64_t P9N2_PU_GPE2_PPE_XIDBGPRO = 0x00064015ull;
+
+
+static const uint64_t P9N2_PU_GPE2_PPE_XIRAMDBG = 0x00064013ull;
+
+
+static const uint64_t P9N2_PU_GPE2_PPE_XIRAMEDR = 0x00064014ull;
+
+
+static const uint64_t P9N2_PU_GPE2_PPE_XIRAMGA = 0x00064012ull;
+
+
+static const uint64_t P9N2_PU_GPE2_PPE_XIRAMRA = 0x00064011ull;
+
+
+static const uint64_t P9N2_PU_GPE2_PPE_XIXCR = 0x00064010ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+
+static const uint64_t P9N2_PU_GPE3_GPEDBG_OCI = 0xC0030010ull;
+
+static const uint64_t P9N2_PU_GPE3_GPEDBG_SCOM = 0x00066002ull;
+
+
+static const uint64_t P9N2_PU_GPE3_GPEIVPR_OCI = 0xC0030008ull;
+
+static const uint64_t P9N2_PU_GPE3_GPEIVPR_SCOM = 0x00066001ull;
+
+
+static const uint64_t P9N2_PU_GPE3_GPEMACR_OCI = 0xC0030020ull;
+
+static const uint64_t P9N2_PU_GPE3_GPEMACR_SCOM = 0x00066004ull;
+
+
+static const uint64_t P9N2_PU_GPE3_GPENXIXCR_OCI = 0xC0030080ull;
+
+static const uint64_t P9N2_PU_GPE3_GPENXIXCR_SCOM = 0x00066010ull;
+
+
+static const uint64_t P9N2_PU_GPE3_GPESTR_OCI = 0xC0030018ull;
+
+static const uint64_t P9N2_PU_GPE3_GPESTR_SCOM = 0x00066003ull;
+
+
+static const uint64_t P9N2_PU_GPE3_GPETSEL_OCI = 0xC0030000ull;
+
+static const uint64_t P9N2_PU_GPE3_GPETSEL_SCOM = 0x00066000ull;
+
+
+static const uint64_t P9N2_PU_GPE3_GPEXIEDR_OCI = 0xC0030118ull;
+
+static const uint64_t P9N2_PU_GPE3_GPEXIEDR_SCOM = 0x00066023ull;
+
+
+static const uint64_t P9N2_PU_GPE3_GPEXIIAR_OCI = 0xC0030128ull;
+
+static const uint64_t P9N2_PU_GPE3_GPEXIIAR_SCOM = 0x00066025ull;
+
+
+static const uint64_t P9N2_PU_GPE3_GPEXIIR_OCI = 0xC0030120ull;
+
+static const uint64_t P9N2_PU_GPE3_GPEXIIR_SCOM = 0x00066024ull;
+
+
+static const uint64_t P9N2_PU_GPE3_GPEXISPRG0_OCI = 0xC0030110ull;
+
+static const uint64_t P9N2_PU_GPE3_GPEXISPRG0_SCOM = 0x00066022ull;
+
+
+static const uint64_t P9N2_PU_GPE3_GPEXIXCR_OCI = 0xC0030100ull;
+
+static const uint64_t P9N2_PU_GPE3_GPEXIXCR_SCOM = 0x00066020ull;
+
+
+static const uint64_t P9N2_PU_GPE3_GPEXIXSR_OCI = 0xC0030108ull;
+
+static const uint64_t P9N2_PU_GPE3_GPEXIXSR_SCOM = 0x00066021ull;
+
+
+static const uint64_t P9N2_PU_GPE3_MIB_XIDCAC_OCI = 0xC00300D0ull;
+
+static const uint64_t P9N2_PU_GPE3_MIB_XIDCAC_SCOM = 0x0006601Aull;
+
+
+static const uint64_t P9N2_PU_GPE3_MIB_XIICAC = 0x00066019ull;
+
+
+static const uint64_t P9N2_PU_GPE3_MIB_XIMEM = 0x00066017ull;
+
+
+static const uint64_t P9N2_PU_GPE3_MIB_XISGB = 0x00066018ull;
+
+
+static const uint64_t P9N2_PU_GPE3_MIB_XISIB_OCI = 0xC00300B0ull;
+
+static const uint64_t P9N2_PU_GPE3_MIB_XISIB_SCOM = 0x00066016ull;
+
+
+static const uint64_t P9N2_PU_GPE3_PPE_XIDBGPRO = 0x00066015ull;
+
+
+static const uint64_t P9N2_PU_GPE3_PPE_XIRAMDBG = 0x00066013ull;
+
+
+static const uint64_t P9N2_PU_GPE3_PPE_XIRAMEDR = 0x00066014ull;
+
+
+static const uint64_t P9N2_PU_GPE3_PPE_XIRAMGA = 0x00066012ull;
+
+
+static const uint64_t P9N2_PU_GPE3_PPE_XIRAMRA = 0x00066011ull;
+
+
+static const uint64_t P9N2_PU_GPE3_PPE_XIXCR = 0x00066010ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+
+static const uint64_t P9N2_PU_GPIO_INPUT = 0x000B0050ull;
+
+
+static const uint64_t P9N2_PU_GPIO_INT_COND = 0x000B005Eull;
+
+
+static const uint64_t P9N2_PU_GPIO_INT_ENABLE = 0x000B005Dull;
+
+
+static const uint64_t P9N2_PU_GPIO_INT_POLARITY = 0x000B005Cull;
+
+
+static const uint64_t P9N2_PU_GPIO_INT_STATUS = 0x000B0057ull;
+
+
+static const uint64_t P9N2_PU_GPIO_MODE = 0x000B0059ull;
+
+
+static const uint64_t P9N2_PU_GPIO_OUTPUT = 0x000B0051ull;
+
+static const uint64_t P9N2_PU_GPIO_OUTPUT_OR = 0x000B0052ull;
+
+static const uint64_t P9N2_PU_GPIO_OUTPUT_CLEAR = 0x000B0053ull;
+
+
+static const uint64_t P9N2_PU_GPIO_OUTPUT_EN = 0x000B0054ull;
+
+
+static const uint64_t P9N2_PU_NPU0_CTL_GPU0_BAR = 0x05011094ull;
+
+static const uint64_t P9N2_PU_NPU2_CTL_GPU0_BAR = 0x05011294ull;
+
+static const uint64_t P9N2_PU_NPU0_SM0_GPU0_BAR = 0x05011004ull;
+
+static const uint64_t P9N2_PU_NPU0_SM1_GPU0_BAR = 0x05011034ull;
+
+static const uint64_t P9N2_PU_NPU0_SM3_GPU0_BAR = 0x05011064ull;
+
+static const uint64_t P9N2_PU_NPU2_SM0_GPU0_BAR = 0x05011204ull;
+
+static const uint64_t P9N2_PU_NPU2_SM1_GPU0_BAR = 0x05011234ull;
+
+static const uint64_t P9N2_PU_NPU2_SM3_GPU0_BAR = 0x05011264ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_CTL_GPU0_BAR = 0x05011494ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM0_GPU0_BAR = 0x05011404ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM1_GPU0_BAR = 0x05011434ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM3_GPU0_BAR = 0x05011464ull;
+
+
+static const uint64_t P9N2_PU_NPU0_CTL_GPU1_BAR = 0x05011095ull;
+
+static const uint64_t P9N2_PU_NPU2_CTL_GPU1_BAR = 0x05011295ull;
+
+static const uint64_t P9N2_PU_NPU0_SM0_GPU1_BAR = 0x05011005ull;
+
+static const uint64_t P9N2_PU_NPU0_SM1_GPU1_BAR = 0x05011035ull;
+
+static const uint64_t P9N2_PU_NPU0_SM3_GPU1_BAR = 0x05011065ull;
+
+static const uint64_t P9N2_PU_NPU2_SM0_GPU1_BAR = 0x05011205ull;
+
+static const uint64_t P9N2_PU_NPU2_SM1_GPU1_BAR = 0x05011235ull;
+
+static const uint64_t P9N2_PU_NPU2_SM3_GPU1_BAR = 0x05011265ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_CTL_GPU1_BAR = 0x05011495ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM0_GPU1_BAR = 0x05011405ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM1_GPU1_BAR = 0x05011435ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM3_GPU1_BAR = 0x05011465ull;
+
+
+static const uint64_t P9N2_PEC_GXSTOP0_MASK_REG = 0x0D040014ull;
+
+static const uint64_t P9N2_PEC_0_GXSTOP0_MASK_REG = 0x0D040014ull;
+
+static const uint64_t P9N2_PEC_1_GXSTOP0_MASK_REG = 0x0E040014ull;
+
+static const uint64_t P9N2_PEC_2_GXSTOP0_MASK_REG = 0x0F040014ull;
+
+
+static const uint64_t P9N2_PEC_GXSTOP1_MASK_REG = 0x0D040015ull;
+
+static const uint64_t P9N2_PEC_0_GXSTOP1_MASK_REG = 0x0D040015ull;
+
+static const uint64_t P9N2_PEC_1_GXSTOP1_MASK_REG = 0x0E040015ull;
+
+static const uint64_t P9N2_PEC_2_GXSTOP1_MASK_REG = 0x0F040015ull;
+
+
+static const uint64_t P9N2_PEC_GXSTOP2_MASK_REG = 0x0D040016ull;
+
+static const uint64_t P9N2_PEC_0_GXSTOP2_MASK_REG = 0x0D040016ull;
+
+static const uint64_t P9N2_PEC_1_GXSTOP2_MASK_REG = 0x0E040016ull;
+
+static const uint64_t P9N2_PEC_2_GXSTOP2_MASK_REG = 0x0F040016ull;
+
+
+static const uint64_t P9N2_PEC_GXSTOP_TRIG_REG = 0x0D040013ull;
+
+static const uint64_t P9N2_PEC_0_GXSTOP_TRIG_REG = 0x0D040013ull;
+
+static const uint64_t P9N2_PEC_1_GXSTOP_TRIG_REG = 0x0E040013ull;
+
+static const uint64_t P9N2_PEC_2_GXSTOP_TRIG_REG = 0x0F040013ull;
+
+
+static const uint64_t P9N2_PU_GZIP_CONTROL_REG = 0x02011140ull;
+
+
+static const uint64_t P9N2_PU_GZIP_ERRRPT_HOLD_REG = 0x02011152ull;
+
+
+static const uint64_t P9N2_PU_GZIP_HI_PRIOR_RCV_FIFO_ASB = 0x020110C8ull;
+
+
+static const uint64_t P9N2_PU_GZIP_HI_PRIOR_RCV_FIFO_BAR = 0x020110C2ull;
+
+
+static const uint64_t P9N2_PU_GZIP_HI_PRIOR_RCV_FIFO_CNTL = 0x020110C5ull;
+
+
+static const uint64_t P9N2_PU_GZIP_LO_PRIOR_RCV_FIFO_ASB = 0x020110D1ull;
+
+
+static const uint64_t P9N2_PU_GZIP_LO_PRIOR_RCV_FIFO_BAR = 0x020110CBull;
+
+
+static const uint64_t P9N2_PU_GZIP_LO_PRIOR_RCV_FIFO_CNTL = 0x020110CEull;
+
+
+static const uint64_t P9N2_PU_GZIP_MAX_BYTE_CNT = 0x0201105Bull;
+
+
+static const uint64_t P9N2_PEC_HANG_PULSE_0_REG = 0x0D0F0020ull;
+
+static const uint64_t P9N2_PEC_0_HANG_PULSE_0_REG = 0x0D0F0020ull;
+
+static const uint64_t P9N2_PEC_1_HANG_PULSE_0_REG = 0x0E0F0020ull;
+
+static const uint64_t P9N2_PEC_2_HANG_PULSE_0_REG = 0x0F0F0020ull;
+
+
+static const uint64_t P9N2_PEC_HANG_PULSE_1_REG = 0x0D0F0021ull;
+
+static const uint64_t P9N2_PEC_0_HANG_PULSE_1_REG = 0x0D0F0021ull;
+
+static const uint64_t P9N2_PEC_1_HANG_PULSE_1_REG = 0x0E0F0021ull;
+
+static const uint64_t P9N2_PEC_2_HANG_PULSE_1_REG = 0x0F0F0021ull;
+
+
+static const uint64_t P9N2_PEC_HANG_PULSE_2_REG = 0x0D0F0022ull;
+
+static const uint64_t P9N2_PEC_0_HANG_PULSE_2_REG = 0x0D0F0022ull;
+
+static const uint64_t P9N2_PEC_1_HANG_PULSE_2_REG = 0x0E0F0022ull;
+
+static const uint64_t P9N2_PEC_2_HANG_PULSE_2_REG = 0x0F0F0022ull;
+
+
+static const uint64_t P9N2_PEC_HANG_PULSE_3_REG = 0x0D0F0023ull;
+
+static const uint64_t P9N2_PEC_0_HANG_PULSE_3_REG = 0x0D0F0023ull;
+
+static const uint64_t P9N2_PEC_1_HANG_PULSE_3_REG = 0x0E0F0023ull;
+
+static const uint64_t P9N2_PEC_2_HANG_PULSE_3_REG = 0x0F0F0023ull;
+
+
+static const uint64_t P9N2_PEC_HANG_PULSE_4_REG = 0x0D0F0024ull;
+
+static const uint64_t P9N2_PEC_0_HANG_PULSE_4_REG = 0x0D0F0024ull;
+
+static const uint64_t P9N2_PEC_1_HANG_PULSE_4_REG = 0x0E0F0024ull;
+
+static const uint64_t P9N2_PEC_2_HANG_PULSE_4_REG = 0x0F0F0024ull;
+
+
+static const uint64_t P9N2_PEC_HANG_PULSE_5_REG = 0x0D0F0025ull;
+
+static const uint64_t P9N2_PEC_0_HANG_PULSE_5_REG = 0x0D0F0025ull;
+
+static const uint64_t P9N2_PEC_1_HANG_PULSE_5_REG = 0x0E0F0025ull;
+
+static const uint64_t P9N2_PEC_2_HANG_PULSE_5_REG = 0x0F0F0025ull;
+
+
+static const uint64_t P9N2_PEC_HANG_PULSE_6_REG = 0x0D0F0026ull;
+
+static const uint64_t P9N2_PEC_0_HANG_PULSE_6_REG = 0x0D0F0026ull;
+
+static const uint64_t P9N2_PEC_1_HANG_PULSE_6_REG = 0x0E0F0026ull;
+
+static const uint64_t P9N2_PEC_2_HANG_PULSE_6_REG = 0x0F0F0026ull;
+
+
+static const uint64_t P9N2_PU_HCA_BAR = 0x0501294Aull;
+
+
+static const uint64_t P9N2_PU_HCA_COUNT_BAR = 0x0501294Bull;
+
+
+static const uint64_t P9N2_PU_HCA_DECAY1 = 0x0501294Cull;
+
+
+static const uint64_t P9N2_PU_HCA_DECAY2 = 0x0501294Dull;
+
+
+static const uint64_t P9N2_PU_HCA_DROP = 0x05012951ull;
+
+
+static const uint64_t P9N2_PU_HCA_MIRROR_BAR = 0x05012953ull;
+
+
+static const uint64_t P9N2_PU_HCA_MODES = 0x0501294Full;
+
+
+static const uint64_t P9N2_PU_HCA_REF_BAR = 0x0501294Eull;
+
+
+static const uint64_t P9N2_PU_HCA_RESET = 0x05012952ull;
+
+
+static const uint64_t P9N2_PEC_HEARTBEAT_REG = 0x0D0F0018ull;
+
+static const uint64_t P9N2_PEC_0_HEARTBEAT_REG = 0x0D0F0018ull;
+
+static const uint64_t P9N2_PEC_1_HEARTBEAT_REG = 0x0E0F0018ull;
+
+static const uint64_t P9N2_PEC_2_HEARTBEAT_REG = 0x0F0F0018ull;
+
+
+static const uint64_t P9N2_PU_NPU0_CTL_HIGH_WATER = 0x05011099ull;
+
+static const uint64_t P9N2_PU_NPU2_CTL_HIGH_WATER = 0x05011299ull;
+
+static const uint64_t P9N2_PU_NPU0_SM0_HIGH_WATER = 0x05011009ull;
+
+static const uint64_t P9N2_PU_NPU0_SM1_HIGH_WATER = 0x05011039ull;
+
+static const uint64_t P9N2_PU_NPU0_SM3_HIGH_WATER = 0x05011069ull;
+
+static const uint64_t P9N2_PU_NPU2_SM0_HIGH_WATER = 0x05011209ull;
+
+static const uint64_t P9N2_PU_NPU2_SM1_HIGH_WATER = 0x05011239ull;
+
+static const uint64_t P9N2_PU_NPU2_SM3_HIGH_WATER = 0x05011269ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_CTL_HIGH_WATER = 0x05011499ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM0_HIGH_WATER = 0x05011409ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM1_HIGH_WATER = 0x05011439ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM3_HIGH_WATER = 0x05011469ull;
+
+
+static const uint64_t P9N2_PEC_HOSTATTN = 0x0D040009ull;
+
+static const uint64_t P9N2_PEC_0_HOSTATTN = 0x0D040009ull;
+
+static const uint64_t P9N2_PEC_1_HOSTATTN = 0x0E040009ull;
+
+static const uint64_t P9N2_PEC_2_HOSTATTN = 0x0F040009ull;
+
+
+static const uint64_t P9N2_PEC_HOSTATTN_MASK = 0x0D04001Aull;
+
+static const uint64_t P9N2_PEC_0_HOSTATTN_MASK = 0x0D04001Aull;
+
+static const uint64_t P9N2_PEC_1_HOSTATTN_MASK = 0x0E04001Aull;
+
+static const uint64_t P9N2_PEC_2_HOSTATTN_MASK = 0x0F04001Aull;
+
+
+static const uint64_t P9N2_PU_HTM0_HTM_CFG = 0x05012888ull;
+
+static const uint64_t P9N2_PU_HTM1_HTM_CFG = 0x050128C8ull;
+
+
+static const uint64_t P9N2_PU_HTM0_HTM_CTRL = 0x05012885ull;
+
+static const uint64_t P9N2_PU_HTM1_HTM_CTRL = 0x050128C5ull;
+
+
+static const uint64_t P9N2_PU_HTM0_HTM_FILT = 0x05012886ull;
+
+static const uint64_t P9N2_PU_HTM1_HTM_FILT = 0x050128C6ull;
+
+
+static const uint64_t P9N2_PU_HTM0_HTM_FLEX = 0x05012889ull;
+
+static const uint64_t P9N2_PU_HTM1_HTM_FLEX = 0x050128C9ull;
+
+
+static const uint64_t P9N2_PU_HTM0_HTM_LAST = 0x05012883ull;
+
+static const uint64_t P9N2_PU_HTM1_HTM_LAST = 0x050128C3ull;
+
+
+static const uint64_t P9N2_PU_HTM0_HTM_MEM = 0x05012881ull;
+
+static const uint64_t P9N2_PU_HTM1_HTM_MEM = 0x050128C1ull;
+
+
+static const uint64_t P9N2_PU_HTM0_HTM_MODE = 0x05012880ull;
+
+static const uint64_t P9N2_PU_HTM1_HTM_MODE = 0x050128C0ull;
+
+
+static const uint64_t P9N2_PU_HTM0_HTM_STAT = 0x05012882ull;
+
+static const uint64_t P9N2_PU_HTM1_HTM_STAT = 0x050128C2ull;
+
+
+static const uint64_t P9N2_PU_HTM0_HTM_TRIG = 0x05012884ull;
+
+static const uint64_t P9N2_PU_HTM1_HTM_TRIG = 0x050128C4ull;
+
+
+static const uint64_t P9N2_PU_HTM0_HTM_TTYPEFILT = 0x05012887ull;
+
+static const uint64_t P9N2_PU_HTM1_HTM_TTYPEFILT = 0x050128C7ull;
+
+
+static const uint64_t P9N2_PU_I2C_BUSY_REGISTER_B = 0x000A000Eull;
+
+
+static const uint64_t P9N2_PU_I2C_BUSY_REGISTER_C = 0x000A100Eull;
+
+
+static const uint64_t P9N2_PU_I2C_BUSY_REGISTER_D = 0x000A200Eull;
+
+
+static const uint64_t P9N2_PU_I2C_BUSY_REGISTER_E = 0x000A300Eull;
+
+
+static const uint64_t P9N2_PU_IMM_RESET_ERR_B = 0x000A000Cull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+
+static const uint64_t P9N2_PU_IMM_RESET_ERR_C = 0x000A100Cull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+
+static const uint64_t P9N2_PU_IMM_RESET_ERR_D = 0x000A200Cull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+
+static const uint64_t P9N2_PU_IMM_RESET_ERR_E = 0x000A300Cull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+
+static const uint64_t P9N2_PU_IMM_RESET_I2C_B = 0x000A000Bull;
+
+
+static const uint64_t P9N2_PU_IMM_RESET_I2C_C = 0x000A100Bull;
+
+
+static const uint64_t P9N2_PU_IMM_RESET_I2C_D = 0x000A200Bull;
+
+
+static const uint64_t P9N2_PU_IMM_RESET_I2C_E = 0x000A300Bull;
+
+
+static const uint64_t P9N2_PU_IMM_RESET_S_SCL_B = 0x000A000Full;
+
+
+static const uint64_t P9N2_PU_IMM_RESET_S_SCL_C = 0x000A100Full;
+
+
+static const uint64_t P9N2_PU_IMM_RESET_S_SCL_D = 0x000A200Full;
+
+
+static const uint64_t P9N2_PU_IMM_RESET_S_SCL_E = 0x000A300Full;
+
+
+static const uint64_t P9N2_PU_IMM_RESET_S_SDA_B = 0x000A0011ull;
+
+
+static const uint64_t P9N2_PU_IMM_RESET_S_SDA_C = 0x000A1011ull;
+
+
+static const uint64_t P9N2_PU_IMM_RESET_S_SDA_D = 0x000A2011ull;
+
+
+static const uint64_t P9N2_PU_IMM_RESET_S_SDA_E = 0x000A3011ull;
+
+
+static const uint64_t P9N2_PU_IMM_SET_S_SCL_B = 0x000A000Dull;
+
+
+static const uint64_t P9N2_PU_IMM_SET_S_SCL_C = 0x000A100Dull;
+
+
+static const uint64_t P9N2_PU_IMM_SET_S_SCL_D = 0x000A200Dull;
+
+
+static const uint64_t P9N2_PU_IMM_SET_S_SCL_E = 0x000A300Dull;
+
+
+static const uint64_t P9N2_PU_IMM_SET_S_SDA_B = 0x000A0010ull;
+
+
+static const uint64_t P9N2_PU_IMM_SET_S_SDA_C = 0x000A1010ull;
+
+
+static const uint64_t P9N2_PU_IMM_SET_S_SDA_D = 0x000A2010ull;
+
+
+static const uint64_t P9N2_PU_IMM_SET_S_SDA_E = 0x000A3010ull;
+
+
+static const uint64_t P9N2_NV_INHIBIT_CONFIG = 0x050110D1ull;
+
+static const uint64_t P9N2_NV_0_INHIBIT_CONFIG = 0x050110D1ull;
+
+static const uint64_t P9N2_NV_4_INHIBIT_CONFIG = 0x050114D1ull;
+
+static const uint64_t P9N2_PU_NPU0_INHIBIT_CONFIG = 0x050110A0ull;
+
+static const uint64_t P9N2_PU_NPU2_INHIBIT_CONFIG = 0x050112A0ull;
+
+static const uint64_t P9N2_PU_NPU0_SM0_INHIBIT_CONFIG = 0x05011010ull;
+
+static const uint64_t P9N2_PU_NPU0_SM2_INHIBIT_CONFIG = 0x05011040ull;
+
+static const uint64_t P9N2_PU_NPU0_SM3_INHIBIT_CONFIG = 0x05011070ull;
+
+static const uint64_t P9N2_PU_NPU2_NTL0_INHIBIT_CONFIG = 0x050112D1ull;
+
+static const uint64_t P9N2_PU_NPU2_SM0_INHIBIT_CONFIG = 0x05011210ull;
+
+static const uint64_t P9N2_PU_NPU2_SM2_INHIBIT_CONFIG = 0x05011240ull;
+
+static const uint64_t P9N2_PU_NPU2_SM3_INHIBIT_CONFIG = 0x05011270ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_INHIBIT_CONFIG = 0x050114A0ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM0_INHIBIT_CONFIG = 0x05011410ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM2_INHIBIT_CONFIG = 0x05011440ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM3_INHIBIT_CONFIG = 0x05011470ull;
+
+static const uint64_t P9N2__CTL_INHIBIT_CONFIG = 0x05011687ull;
+
+
+static const uint64_t P9N2_PEC_INJECT_REG = 0x0D050011ull;
+
+static const uint64_t P9N2_PEC_0_INJECT_REG = 0x0D050011ull;
+
+static const uint64_t P9N2_PEC_1_INJECT_REG = 0x0E050011ull;
+
+static const uint64_t P9N2_PEC_2_INJECT_REG = 0x0F050011ull;
+
+
+static const uint64_t P9N2_PEC_0_STACK0_INTBAR_REG = 0x04010C53ull;
+
+static const uint64_t P9N2_PEC_1_STACK0_INTBAR_REG = 0x04011053ull;
+
+static const uint64_t P9N2_PEC_1_STACK1_INTBAR_REG = 0x04011093ull;
+
+static const uint64_t P9N2_PEC_1_STACK2_INTBAR_REG = 0x040110D3ull;
+
+static const uint64_t P9N2_PEC_2_STACK0_INTBAR_REG = 0x04011453ull;
+
+static const uint64_t P9N2_PEC_2_STACK1_INTBAR_REG = 0x04011493ull;
+
+static const uint64_t P9N2_PEC_2_STACK2_INTBAR_REG = 0x040114D3ull;
+
+static const uint64_t P9N2_PEC_STACK0_INTBAR_REG = 0x04010C53ull;
+
+static const uint64_t P9N2_PHB_INTBAR_REG = 0x04010C53ull;
+
+static const uint64_t P9N2_PHB_0_INTBAR_REG = 0x04010C53ull;
+
+static const uint64_t P9N2_PHB_1_INTBAR_REG = 0x04011053ull;
+
+static const uint64_t P9N2_PHB_2_INTBAR_REG = 0x04011093ull;
+
+static const uint64_t P9N2_PHB_3_INTBAR_REG = 0x04011453ull;
+
+static const uint64_t P9N2_PHB_4_INTBAR_REG = 0x04011493ull;
+
+static const uint64_t P9N2_PHB_5_INTBAR_REG = 0x040114D3ull;
+
+
+static const uint64_t P9N2_PU_INTERRUPTS_B = 0x000A000Aull;
+
+
+static const uint64_t P9N2_PU_INTERRUPTS_C = 0x000A100Aull;
+
+
+static const uint64_t P9N2_PU_INTERRUPTS_D = 0x000A200Aull;
+
+
+static const uint64_t P9N2_PU_INTERRUPTS_E = 0x000A300Aull;
+
+
+static const uint64_t P9N2_PU_INTERRUPT_COND_B = 0x000A0009ull;
+
+
+static const uint64_t P9N2_PU_INTERRUPT_COND_C = 0x000A1009ull;
+
+
+static const uint64_t P9N2_PU_INTERRUPT_COND_D = 0x000A2009ull;
+
+
+static const uint64_t P9N2_PU_INTERRUPT_COND_E = 0x000A3009ull;
+
+
+static const uint64_t P9N2_PU_INTERRUPT_MASK_REGISTER_B_WO = 0x000A0008ull;
+
+static const uint64_t P9N2_PU_INTERRUPT_MASK_REGISTER_B_OR = 0x000A0009ull;
+
+static const uint64_t P9N2_PU_INTERRUPT_MASK_REGISTER_B_AND = 0x000A000Aull;
+
+
+static const uint64_t P9N2_PU_INTERRUPT_MASK_REGISTER_C_WO = 0x000A1008ull;
+
+static const uint64_t P9N2_PU_INTERRUPT_MASK_REGISTER_C_OR = 0x000A1009ull;
+
+static const uint64_t P9N2_PU_INTERRUPT_MASK_REGISTER_C_AND = 0x000A100Aull;
+
+
+static const uint64_t P9N2_PU_INTERRUPT_MASK_REGISTER_D_WO = 0x000A2008ull;
+
+static const uint64_t P9N2_PU_INTERRUPT_MASK_REGISTER_D_OR = 0x000A2009ull;
+
+static const uint64_t P9N2_PU_INTERRUPT_MASK_REGISTER_D_AND = 0x000A200Aull;
+
+
+static const uint64_t P9N2_PU_INTERRUPT_MASK_REGISTER_E_WO = 0x000A3008ull;
+
+static const uint64_t P9N2_PU_INTERRUPT_MASK_REGISTER_E_OR = 0x000A3009ull;
+
+static const uint64_t P9N2_PU_INTERRUPT_MASK_REGISTER_E_AND = 0x000A300Aull;
+
+
+static const uint64_t P9N2_PU_INTERRUPT_MASK_REGISTER_READ_B = 0x000A0008ull;
+
+
+static const uint64_t P9N2_PU_INTERRUPT_MASK_REGISTER_READ_C = 0x000A1008ull;
+
+
+static const uint64_t P9N2_PU_INTERRUPT_MASK_REGISTER_READ_D = 0x000A2008ull;
+
+
+static const uint64_t P9N2_PU_INTERRUPT_MASK_REGISTER_READ_E = 0x000A3008ull;
+
+
+static const uint64_t P9N2__CTL_INT_0_CONFIG = 0x0501168Cull;
+
+
+static const uint64_t P9N2__CTL_INT_1_CONFIG = 0x0501168Dull;
+
+
+static const uint64_t P9N2_PU_NPU_SM0_INT_2_CONFIG = 0x05011701ull;
+
+
+static const uint64_t P9N2__CTL_INT_BAR = 0x05011693ull;
+
+
+static const uint64_t P9N2_PU_INT_CQ_ACTION0 = 0x05013036ull;
+
+
+static const uint64_t P9N2_PU_INT_CQ_ACTION1 = 0x05013037ull;
+
+
+static const uint64_t P9N2_PU_INT_CQ_AIB_CTL = 0x05013022ull;
+
+
+static const uint64_t P9N2_PU_INT_CQ_CFG_LDQ = 0x05013026ull;
+
+
+static const uint64_t P9N2_PU_INT_CQ_CFG_PB_GEN = 0x0501300Aull;
+
+
+static const uint64_t P9N2_PU_INT_CQ_CFG_STQ1 = 0x05013024ull;
+
+
+static const uint64_t P9N2_PU_INT_CQ_CFG_STQ2 = 0x05013025ull;
+
+
+static const uint64_t P9N2_PU_INT_CQ_CNPM_SEL = 0x0501300Full;
+
+
+static const uint64_t P9N2_PU_INT_CQ_ERR_INFO0 = 0x0501303Aull;
+
+
+static const uint64_t P9N2_PU_INT_CQ_ERR_INFO1 = 0x0501303Bull;
+
+
+static const uint64_t P9N2_PU_INT_CQ_ERR_INFO2 = 0x0501303Cull;
+
+
+static const uint64_t P9N2_PU_INT_CQ_ERR_INFO3 = 0x0501303Dull;
+
+
+static const uint64_t P9N2_PU_INT_CQ_ERR_RPT_HOLD = 0x05013039ull;
+
+
+static const uint64_t P9N2_PU_INT_CQ_FIR = 0x05013030ull;
+
+static const uint64_t P9N2_PU_INT_CQ_FIR_AND = 0x05013031ull;
+
+static const uint64_t P9N2_PU_INT_CQ_FIR_OR = 0x05013032ull;
+
+
+static const uint64_t P9N2_PU_INT_CQ_FIRMASK = 0x05013033ull;
+
+static const uint64_t P9N2_PU_INT_CQ_FIRMASK_AND = 0x05013034ull;
+
+static const uint64_t P9N2_PU_INT_CQ_FIRMASK_OR = 0x05013035ull;
+
+
+static const uint64_t P9N2_PU_INT_CQ_IC_BAR = 0x05013010ull;
+
+
+static const uint64_t P9N2_PU_INT_CQ_MSGSND = 0x0501300Bull;
+
+
+static const uint64_t P9N2_PU_INT_CQ_PBC_LIMIT = 0x0501300Cull;
+
+
+static const uint64_t P9N2_PU_INT_CQ_PBI_CTL = 0x05013020ull;
+
+
+static const uint64_t P9N2_PU_INT_CQ_PBO_CTL = 0x05013021ull;
+
+
+static const uint64_t P9N2_PU_INT_CQ_PC_BAR = 0x05013016ull;
+
+
+static const uint64_t P9N2_PU_INT_CQ_PC_BARM = 0x05013017ull;
+
+
+static const uint64_t P9N2_PU_INT_CQ_PGM_DBG0 = 0x05013000ull;
+
+
+static const uint64_t P9N2_PU_INT_CQ_PGM_DBG1 = 0x05013001ull;
+
+
+static const uint64_t P9N2_PU_INT_CQ_PMC_0 = 0x05013028ull;
+
+
+static const uint64_t P9N2_PU_INT_CQ_PMC_1 = 0x05013029ull;
+
+
+static const uint64_t P9N2_PU_INT_CQ_PMC_2 = 0x0501302Aull;
+
+
+static const uint64_t P9N2_PU_INT_CQ_PMC_3 = 0x0501302Bull;
+
+
+static const uint64_t P9N2_PU_INT_CQ_PMC_4 = 0x0501302Cull;
+
+
+static const uint64_t P9N2_PU_INT_CQ_PMC_5 = 0x0501302Dull;
+
+
+static const uint64_t P9N2_PU_INT_CQ_PMC_6 = 0x0501302Eull;
+
+
+static const uint64_t P9N2_PU_INT_CQ_PMC_7 = 0x0501302Full;
+
+
+static const uint64_t P9N2_PU_INT_CQ_PM_CTL = 0x05013027ull;
+
+
+static const uint64_t P9N2_PU_INT_CQ_RST_CTL = 0x05013023ull;
+
+
+static const uint64_t P9N2_PU_INT_CQ_SWI_CMD1 = 0x05013004ull;
+
+
+static const uint64_t P9N2_PU_INT_CQ_SWI_CMD2 = 0x05013005ull;
+
+
+static const uint64_t P9N2_PU_INT_CQ_SWI_CMD3 = 0x05013006ull;
+
+
+static const uint64_t P9N2_PU_INT_CQ_SWI_CMD4 = 0x05013007ull;
+
+
+static const uint64_t P9N2_PU_INT_CQ_SWI_CMD5 = 0x05013008ull;
+
+
+static const uint64_t P9N2_PU_INT_CQ_SWI_RSP = 0x05013009ull;
+
+
+static const uint64_t P9N2_PU_INT_CQ_TAR = 0x0501301Eull;
+
+
+static const uint64_t P9N2_PU_INT_CQ_TDR = 0x0501301Full;
+
+
+static const uint64_t P9N2_PU_INT_CQ_TM1_BAR = 0x05013012ull;
+
+
+static const uint64_t P9N2_PU_INT_CQ_TM2_BAR = 0x05013014ull;
+
+
+static const uint64_t P9N2_PU_INT_CQ_VC_BAR = 0x05013018ull;
+
+
+static const uint64_t P9N2_PU_INT_CQ_VC_BARM = 0x05013019ull;
+
+
+static const uint64_t P9N2_PU_INT_CQ_WOF = 0x05013038ull;
+
+
+static const uint64_t P9N2__NTL1_INT_LOG_0_PE0 = 0x050116E0ull;
+
+
+static const uint64_t P9N2__NTL1_INT_LOG_0_PE1 = 0x050116E1ull;
+
+
+static const uint64_t P9N2__NTL1_INT_LOG_0_PE10 = 0x050116EAull;
+
+
+static const uint64_t P9N2__NTL1_INT_LOG_0_PE11 = 0x050116EBull;
+
+
+static const uint64_t P9N2__NTL1_INT_LOG_0_PE12 = 0x050116ECull;
+
+
+static const uint64_t P9N2__NTL1_INT_LOG_0_PE13 = 0x050116EDull;
+
+
+static const uint64_t P9N2__NTL1_INT_LOG_0_PE14 = 0x050116EEull;
+
+
+static const uint64_t P9N2__NTL1_INT_LOG_0_PE15 = 0x050116EFull;
+
+
+static const uint64_t P9N2__NTL1_INT_LOG_0_PE2 = 0x050116E2ull;
+
+
+static const uint64_t P9N2__NTL1_INT_LOG_0_PE3 = 0x050116E3ull;
+
+
+static const uint64_t P9N2__NTL1_INT_LOG_0_PE4 = 0x050116E4ull;
+
+
+static const uint64_t P9N2__NTL1_INT_LOG_0_PE5 = 0x050116E5ull;
+
+
+static const uint64_t P9N2__NTL1_INT_LOG_0_PE6 = 0x050116E6ull;
+
+
+static const uint64_t P9N2__NTL1_INT_LOG_0_PE7 = 0x050116E7ull;
+
+
+static const uint64_t P9N2__NTL1_INT_LOG_0_PE8 = 0x050116E8ull;
+
+
+static const uint64_t P9N2__NTL1_INT_LOG_0_PE9 = 0x050116E9ull;
+
+
+static const uint64_t P9N2__NTL1_INT_LOG_1_PE0 = 0x050116F0ull;
+
+
+static const uint64_t P9N2__NTL1_INT_LOG_1_PE1 = 0x050116F1ull;
+
+
+static const uint64_t P9N2__NTL1_INT_LOG_1_PE10 = 0x050116FAull;
+
+
+static const uint64_t P9N2__NTL1_INT_LOG_1_PE11 = 0x050116FBull;
+
+
+static const uint64_t P9N2__NTL1_INT_LOG_1_PE12 = 0x050116FCull;
+
+
+static const uint64_t P9N2__NTL1_INT_LOG_1_PE13 = 0x050116FDull;
+
+
+static const uint64_t P9N2__NTL1_INT_LOG_1_PE14 = 0x050116FEull;
+
+
+static const uint64_t P9N2__NTL1_INT_LOG_1_PE15 = 0x050116FFull;
+
+
+static const uint64_t P9N2__NTL1_INT_LOG_1_PE2 = 0x050116F2ull;
+
+
+static const uint64_t P9N2__NTL1_INT_LOG_1_PE3 = 0x050116F3ull;
+
+
+static const uint64_t P9N2__NTL1_INT_LOG_1_PE4 = 0x050116F4ull;
+
+
+static const uint64_t P9N2__NTL1_INT_LOG_1_PE5 = 0x050116F5ull;
+
+
+static const uint64_t P9N2__NTL1_INT_LOG_1_PE6 = 0x050116F6ull;
+
+
+static const uint64_t P9N2__NTL1_INT_LOG_1_PE7 = 0x050116F7ull;
+
+
+static const uint64_t P9N2__NTL1_INT_LOG_1_PE8 = 0x050116F8ull;
+
+
+static const uint64_t P9N2__NTL1_INT_LOG_1_PE9 = 0x050116F9ull;
+
+
+static const uint64_t P9N2_PU_INT_PC_AIB_RX_CRD_CMD = 0x05013121ull;
+
+
+static const uint64_t P9N2_PU_INT_PC_AIB_RX_CRD_DAT = 0x05013122ull;
+
+
+static const uint64_t P9N2_PU_INT_PC_AIB_RX_CRD_INIT = 0x05013120ull;
+
+
+static const uint64_t P9N2_PU_INT_PC_AIB_TX_CRD = 0x05013124ull;
+
+
+static const uint64_t P9N2_PU_INT_PC_AIB_TX_ORDER = 0x05013126ull;
+
+
+static const uint64_t P9N2_PU_INT_PC_AIB_TX_PRIO = 0x05013125ull;
+
+
+static const uint64_t P9N2_PU_INT_PC_AT_KILL = 0x05013116ull;
+
+
+static const uint64_t P9N2_PU_INT_PC_AT_KILL_MASK = 0x05013117ull;
+
+
+static const uint64_t P9N2_PU_INT_PC_DBG_ECC = 0x05013131ull;
+
+
+static const uint64_t P9N2_PU_INT_PC_DBG_INT = 0x05013132ull;
+
+
+static const uint64_t P9N2_PU_INT_PC_DBG_PMC = 0x05013134ull;
+
+
+static const uint64_t P9N2_PU_INT_PC_DBG_PMC_ATX0 = 0x05013135ull;
+
+
+static const uint64_t P9N2_PU_INT_PC_DBG_PMC_ATX1 = 0x05013136ull;
+
+
+static const uint64_t P9N2_PU_INT_PC_DBG_PMC_ATX2 = 0x05013137ull;
+
+
+static const uint64_t P9N2_PU_INT_PC_DBG_TMOT = 0x05013130ull;
+
+
+static const uint64_t P9N2_PU_INT_PC_DBG_TRACE = 0x05013133ull;
+
+
+static const uint64_t P9N2_PU_INT_PC_EQD_BLOCK_MODE = 0x05013114ull;
+
+
+static const uint64_t P9N2_PU_INT_PC_ERR0_CFG0 = 0x05013140ull;
+
+
+static const uint64_t P9N2_PU_INT_PC_ERR0_CFG1 = 0x05013141ull;
+
+
+static const uint64_t P9N2_PU_INT_PC_ERR0_FATAL = 0x05013144ull;
+
+
+static const uint64_t P9N2_PU_INT_PC_ERR0_INFO = 0x05013146ull;
+
+
+static const uint64_t P9N2_PU_INT_PC_ERR0_RECOV = 0x05013145ull;
+
+
+static const uint64_t P9N2_PU_INT_PC_ERR0_WOF = 0x05013142ull;
+
+
+static const uint64_t P9N2_PU_INT_PC_ERR0_WOF_DETAIL = 0x05013143ull;
+
+
+static const uint64_t P9N2_PU_INT_PC_ERR1_CFG0 = 0x05013148ull;
+
+
+static const uint64_t P9N2_PU_INT_PC_ERR1_CFG1 = 0x05013149ull;
+
+
+static const uint64_t P9N2_PU_INT_PC_ERR1_FATAL = 0x0501314Cull;
+
+
+static const uint64_t P9N2_PU_INT_PC_ERR1_INFO = 0x0501314Eull;
+
+
+static const uint64_t P9N2_PU_INT_PC_ERR1_RECOV = 0x0501314Dull;
+
+
+static const uint64_t P9N2_PU_INT_PC_ERR1_WOF = 0x0501314Aull;
+
+
+static const uint64_t P9N2_PU_INT_PC_ERR1_WOF_DETAIL = 0x0501314Bull;
+
+
+static const uint64_t P9N2_PU_INT_PC_GLOBAL_CFG = 0x05013110ull;
+
+
+static const uint64_t P9N2_PU_INT_PC_IVE_BLOCK_MODE = 0x05013113ull;
+
+
+static const uint64_t P9N2_PU_INT_PC_LSI_TRIG_EOI = 0x05013128ull;
+
+
+static const uint64_t P9N2_PU_INT_PC_LSI_TRIG_LD = 0x05013129ull;
+
+
+static const uint64_t P9N2_PU_INT_PC_MMIO_ARB = 0x0501311Aull;
+
+
+static const uint64_t P9N2_PU_INT_PC_PCMD_ARB = 0x05013118ull;
+
+
+static const uint64_t P9N2_PU_INT_PC_VPC_ADDITIONAL_PERF_1 = 0x05013174ull;
+
+
+static const uint64_t P9N2_PU_INT_PC_VPC_ADDITIONAL_PERF_2 = 0x05013175ull;
+
+
+static const uint64_t P9N2_PU_INT_PC_VPC_CACHE_EN = 0x05013161ull;
+
+
+static const uint64_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA0 = 0x05013168ull;
+
+
+static const uint64_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA1 = 0x05013169ull;
+
+
+static const uint64_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA2 = 0x0501316Aull;
+
+
+static const uint64_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA3 = 0x0501316Bull;
+
+
+static const uint64_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA4 = 0x0501316Cull;
+
+
+static const uint64_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA5 = 0x0501316Dull;
+
+
+static const uint64_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA6 = 0x0501316Eull;
+
+
+static const uint64_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA7 = 0x0501316Full;
+
+
+static const uint64_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_SPEC = 0x05013167ull;
+
+
+static const uint64_t P9N2_PU_INT_PC_VPC_CONFIG = 0x05013164ull;
+
+
+static const uint64_t P9N2_PU_INT_PC_VPC_DEBUG = 0x05013170ull;
+
+
+static const uint64_t P9N2_PU_INT_PC_VPC_ERR_CFG0 = 0x05013178ull;
+
+
+static const uint64_t P9N2_PU_INT_PC_VPC_ERR_CFG1 = 0x05013179ull;
+
+
+static const uint64_t P9N2_PU_INT_PC_VPC_FATAL_ERR = 0x0501317Cull;
+
+
+static const uint64_t P9N2_PU_INT_PC_VPC_INFO_ERR = 0x0501317Eull;
+
+
+static const uint64_t P9N2_PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD = 0x05013160ull;
+
+
+static const uint64_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_1 = 0x05013171ull;
+
+
+static const uint64_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_2 = 0x05013172ull;
+
+
+static const uint64_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_3 = 0x05013173ull;
+
+
+static const uint64_t P9N2_PU_INT_PC_VPC_RECOV_ERR = 0x0501317Dull;
+
+
+static const uint64_t P9N2_PU_INT_PC_VPC_SCRUB_MASK = 0x05013163ull;
+
+
+static const uint64_t P9N2_PU_INT_PC_VPC_SCRUB_TRIG = 0x05013162ull;
+
+
+static const uint64_t P9N2_PU_INT_PC_VPC_WOF_ERR = 0x0501317Aull;
+
+
+static const uint64_t P9N2_PU_INT_PC_VPC_WOF_ERR_DETAIL = 0x0501317Bull;
+
+
+static const uint64_t P9N2_PU_INT_PC_VPD_BLOCK_MODE = 0x05013115ull;
+
+
+static const uint64_t P9N2_PU_INT_PC_VRQ_CFG = 0x0501311Cull;
+
+
+static const uint64_t P9N2_PU_INT_PC_VRQ_PEND_ARB = 0x0501311Dull;
+
+
+static const uint64_t P9N2_PU_INT_PC_VRQ_VPC_ARB = 0x0501311Full;
+
+
+static const uint64_t P9N2_PU_INT_PC_VRQ_VPC_CRD = 0x0501311Eull;
+
+
+static const uint64_t P9N2_PU_INT_PC_VSD_TABLE_ADDR = 0x05013111ull;
+
+
+static const uint64_t P9N2_PU_INT_PC_VSD_TABLE_DATA = 0x05013112ull;
+
+
+static const uint64_t P9N2__CTL_INT_REQ = 0x05011697ull;
+
+
+static const uint64_t P9N2_PU_INT_TCTXT_CFG = 0x05013100ull;
+
+
+static const uint64_t P9N2_PU_INT_TCTXT_EN0 = 0x05013108ull;
+
+
+static const uint64_t P9N2_PU_INT_TCTXT_EN0_RESET = 0x0501310Aull;
+
+
+static const uint64_t P9N2_PU_INT_TCTXT_EN0_SET = 0x05013109ull;
+
+
+static const uint64_t P9N2_PU_INT_TCTXT_EN1 = 0x0501310Cull;
+
+
+static const uint64_t P9N2_PU_INT_TCTXT_EN1_RESET = 0x0501310Eull;
+
+
+static const uint64_t P9N2_PU_INT_TCTXT_EN1_SET = 0x0501310Dull;
+
+
+static const uint64_t P9N2_PU_INT_TCTXT_INDIR0 = 0x05013104ull;
+
+
+static const uint64_t P9N2_PU_INT_TCTXT_INDIR1 = 0x05013105ull;
+
+
+static const uint64_t P9N2_PU_INT_TCTXT_INDIR2 = 0x05013106ull;
+
+
+static const uint64_t P9N2_PU_INT_TCTXT_INDIR3 = 0x05013107ull;
+
+
+static const uint64_t P9N2_PU_INT_TCTXT_TRACK = 0x05013101ull;
+
+
+static const uint64_t P9N2_PU_INT_VC_AIB_TIMEOUT = 0x0501322Bull;
+
+
+static const uint64_t P9N2_PU_INT_VC_AIB_TX_CMD_PRIORITY = 0x0501323Dull;
+
+
+static const uint64_t P9N2_PU_INT_VC_AIB_TX_ORDERING_TAG_1 = 0x0501322Cull;
+
+
+static const uint64_t P9N2_PU_INT_VC_AIB_TX_ORDERING_TAG_2 = 0x0501322Dull;
+
+
+static const uint64_t P9N2_PU_INT_VC_ATX_INIT_CREDIT_COUNT = 0x0501323Cull;
+
+
+static const uint64_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_1 = 0x05013240ull;
+
+
+static const uint64_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_2 = 0x05013241ull;
+
+
+static const uint64_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_3 = 0x05013242ull;
+
+
+static const uint64_t P9N2_PU_INT_VC_AT_MACRO_KILL = 0x0501323Eull;
+
+
+static const uint64_t P9N2_PU_INT_VC_AT_MACRO_KILL_MASK = 0x0501323Full;
+
+
+static const uint64_t P9N2_PU_INT_VC_EQC_ADDITIONAL_PERF_1 = 0x05013253ull;
+
+
+static const uint64_t P9N2_PU_INT_VC_EQC_ADDITIONAL_PERF_2 = 0x05013254ull;
+
+
+static const uint64_t P9N2_PU_INT_VC_EQC_CACHE_EN = 0x05013211ull;
+
+
+static const uint64_t P9N2_PU_INT_VC_EQC_CACHE_WATCH_DATA0 = 0x05013216ull;
+
+
+static const uint64_t P9N2_PU_INT_VC_EQC_CACHE_WATCH_DATA1 = 0x05013217ull;
+
+
+static const uint64_t P9N2_PU_INT_VC_EQC_CACHE_WATCH_DATA2 = 0x05013218ull;
+
+
+static const uint64_t P9N2_PU_INT_VC_EQC_CACHE_WATCH_DATA3 = 0x05013219ull;
+
+
+static const uint64_t P9N2_PU_INT_VC_EQC_CACHE_WATCH_SPEC = 0x05013215ull;
+
+
+static const uint64_t P9N2_PU_INT_VC_EQC_CONFIG = 0x05013214ull;
+
+
+static const uint64_t P9N2_PU_INT_VC_EQC_DEBUG = 0x0501321Aull;
+
+
+static const uint64_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_1 = 0x05013250ull;
+
+
+static const uint64_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_2 = 0x05013251ull;
+
+
+static const uint64_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_3 = 0x05013252ull;
+
+
+static const uint64_t P9N2_PU_INT_VC_EQC_SCRUB_MASK = 0x05013213ull;
+
+
+static const uint64_t P9N2_PU_INT_VC_EQC_SCRUB_TRIG = 0x05013212ull;
+
+
+static const uint64_t P9N2_PU_INT_VC_EQD_BLOCK_MODE = 0x05013204ull;
+
+
+static const uint64_t P9N2_PU_INT_VC_ERR_CFG_G0R0 = 0x05013270ull;
+
+
+static const uint64_t P9N2_PU_INT_VC_ERR_CFG_G0R1 = 0x05013271ull;
+
+
+static const uint64_t P9N2_PU_INT_VC_ERR_CFG_G1R0 = 0x05013272ull;
+
+
+static const uint64_t P9N2_PU_INT_VC_ERR_CFG_G1R1 = 0x05013273ull;
+
+
+static const uint64_t P9N2_PU_INT_VC_FATAL_ERR_G0 = 0x05013278ull;
+
+
+static const uint64_t P9N2_PU_INT_VC_FATAL_ERR_G1 = 0x0501327Bull;
+
+
+static const uint64_t P9N2_PU_INT_VC_GLOBAL_CONFIG = 0x05013200ull;
+
+
+static const uint64_t P9N2_PU_INT_VC_INFO_ERR_G0 = 0x0501327Aull;
+
+
+static const uint64_t P9N2_PU_INT_VC_INFO_ERR_G1 = 0x0501327Dull;
+
+
+static const uint64_t P9N2_PU_INT_VC_IRQ_CONFIG_0 = 0x05013208ull;
+
+
+static const uint64_t P9N2_PU_INT_VC_IRQ_CONFIG_1 = 0x05013209ull;
+
+
+static const uint64_t P9N2_PU_INT_VC_IRQ_CONFIG_2 = 0x0501320Aull;
+
+
+static const uint64_t P9N2_PU_INT_VC_IRQ_CONFIG_3 = 0x0501320Bull;
+
+
+static const uint64_t P9N2_PU_INT_VC_IRQ_CONFIG_4 = 0x0501320Cull;
+
+
+static const uint64_t P9N2_PU_INT_VC_IRQ_CONFIG_5 = 0x0501320Dull;
+
+
+static const uint64_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_0 = 0x05013268ull;
+
+
+static const uint64_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_1 = 0x05013269ull;
+
+
+static const uint64_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_2 = 0x0501326Aull;
+
+
+static const uint64_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_3 = 0x0501326Bull;
+
+
+static const uint64_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_4 = 0x0501326Cull;
+
+
+static const uint64_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_5 = 0x0501326Dull;
+
+
+static const uint64_t P9N2_PU_INT_VC_IRQ_TO_EQC_CREDITS = 0x0501320Eull;
+
+
+static const uint64_t P9N2_PU_INT_VC_IVC_ADDITIONAL_PERF = 0x0501325Bull;
+
+
+static const uint64_t P9N2_PU_INT_VC_IVC_CACHE_EN = 0x05013221ull;
+
+
+static const uint64_t P9N2_PU_INT_VC_IVC_CACHE_WATCH_ADDR = 0x05013225ull;
+
+
+static const uint64_t P9N2_PU_INT_VC_IVC_CACHE_WATCH_DATA = 0x05013226ull;
+
+
+static const uint64_t P9N2_PU_INT_VC_IVC_DEBUG = 0x0501322Aull;
+
+
+static const uint64_t P9N2_PU_INT_VC_IVC_HASH_1 = 0x05013227ull;
+
+
+static const uint64_t P9N2_PU_INT_VC_IVC_HASH_2 = 0x05013228ull;
+
+
+static const uint64_t P9N2_PU_INT_VC_IVC_HASH_3 = 0x05013229ull;
+
+
+static const uint64_t P9N2_PU_INT_VC_IVC_PERF_EVENT_SEL_1 = 0x05013258ull;
+
+
+static const uint64_t P9N2_PU_INT_VC_IVC_PERF_EVENT_SEL_2 = 0x05013259ull;
+
+
+static const uint64_t P9N2_PU_INT_VC_IVC_PERF_EVENT_SEL_3 = 0x0501325Aull;
+
+
+static const uint64_t P9N2_PU_INT_VC_IVC_SCRUB_MASK = 0x05013223ull;
+
+
+static const uint64_t P9N2_PU_INT_VC_IVC_SCRUB_TRIG = 0x05013222ull;
+
+
+static const uint64_t P9N2_PU_INT_VC_IVE_ISB_BLOCK_MODE = 0x05013203ull;
+
+
+static const uint64_t P9N2_PU_INT_VC_LBS6_DEBUG = 0x05013206ull;
+
+
+static const uint64_t P9N2_PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD = 0x05013210ull;
+
+
+static const uint64_t P9N2_PU_INT_VC_MAX_OUTSTANDING_IRQ_DMA = 0x0501323Bull;
+
+
+static const uint64_t P9N2_PU_INT_VC_MAX_OUTSTANDING_IVC_CMD = 0x05013220ull;
+
+
+static const uint64_t P9N2_PU_INT_VC_MAX_OUTSTANDING_SBC_CMD = 0x05013230ull;
+
+
+static const uint64_t P9N2_PU_INT_VC_RECOV_ERR_G0 = 0x05013279ull;
+
+
+static const uint64_t P9N2_PU_INT_VC_RECOV_ERR_G1 = 0x0501327Cull;
+
+
+static const uint64_t P9N2_PU_INT_VC_SBC_ADDITIONAL_PERF = 0x05013263ull;
+
+
+static const uint64_t P9N2_PU_INT_VC_SBC_CACHE_EN = 0x05013231ull;
+
+
+static const uint64_t P9N2_PU_INT_VC_SBC_CACHE_WATCH_ADDR = 0x05013235ull;
+
+
+static const uint64_t P9N2_PU_INT_VC_SBC_CACHE_WATCH_DATA = 0x05013236ull;
+
+
+static const uint64_t P9N2_PU_INT_VC_SBC_CONFIG = 0x05013234ull;
+
+
+static const uint64_t P9N2_PU_INT_VC_SBC_DEBUG = 0x0501323Aull;
+
+
+static const uint64_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_1 = 0x05013260ull;
+
+
+static const uint64_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_2 = 0x05013261ull;
+
+
+static const uint64_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_3 = 0x05013262ull;
+
+
+static const uint64_t P9N2_PU_INT_VC_SBC_SCRUB_MASK = 0x05013233ull;
+
+
+static const uint64_t P9N2_PU_INT_VC_SBC_SCRUB_TRIG = 0x05013232ull;
+
+
+static const uint64_t P9N2_PU_INT_VC_SBC_SOFTWR_ADDR = 0x05013237ull;
+
+
+static const uint64_t P9N2_PU_INT_VC_SBC_SOFTWR_DATA = 0x05013239ull;
+
+
+static const uint64_t P9N2_PU_INT_VC_SBC_SOFTWR_MASK = 0x05013238ull;
+
+
+static const uint64_t P9N2_PU_INT_VC_VPS_BLOCK_MODE = 0x05013205ull;
+
+
+static const uint64_t P9N2_PU_INT_VC_VSD_TABLE_ADDR = 0x05013201ull;
+
+
+static const uint64_t P9N2_PU_INT_VC_VSD_TABLE_DATA = 0x05013202ull;
+
+
+static const uint64_t P9N2_PU_INT_VC_WOF_ERR_G0 = 0x05013274ull;
+
+
+static const uint64_t P9N2_PU_INT_VC_WOF_ERR_G0_DETAIL = 0x05013275ull;
+
+
+static const uint64_t P9N2_PU_INT_VC_WOF_ERR_G1 = 0x05013276ull;
+
+
+static const uint64_t P9N2_PU_INT_VC_WOF_ERR_G1_DETAIL = 0x05013277ull;
+
+
+static const uint64_t P9N2__SM1_IODA_ADDR = 0x05011621ull;
+
+
+static const uint64_t P9N2__SM1_IODA_DAT0 = 0x05011622ull;
+
+
+static const uint64_t P9N2_PU_IO_DATA_REG = 0x00090030ull;
+
+
+static const uint64_t P9N2_PU_IVT_OFFSET = 0x05012918ull;
+
+
+static const uint64_t P9N2_PU_JTG_PIB_OJCFG = 0x0006D004ull;
+
+static const uint64_t P9N2_PU_JTG_PIB_OJCFG_AND = 0x0006D005ull;
+
+static const uint64_t P9N2_PU_JTG_PIB_OJCFG_OR = 0x0006D006ull;
+
+
+static const uint64_t P9N2_PU_JTG_PIB_OJFRST = 0x0006D007ull;
+
+
+static const uint64_t P9N2_PU_JTG_PIB_OJIC_SCOM = 0x0006D008ull;
+
+static const uint64_t P9N2_PU_JTG_PIB_OJIC_SCOM1 = 0x0006D009ull;
+
+static const uint64_t P9N2_PU_JTG_PIB_OJIC_SCOM2 = 0x0006D00Aull;
+
+
+static const uint64_t P9N2_PU_JTG_PIB_OJSTAT = 0x0006D00Bull;
+
+
+static const uint64_t P9N2_PU_JTG_PIB_OJTDI = 0x0006D00Cull;
+
+
+static const uint64_t P9N2_PU_JTG_PIB_OJTDO = 0x0006D00Dull;
+
+
+static const uint64_t P9N2__CTL_LCO_CONFIG = 0x05011682ull;
+
+
+static const uint64_t P9N2_CAPP_LINK_DELAY_TIMER = 0x02010845ull;
+
+static const uint64_t P9N2_CAPP_0_LINK_DELAY_TIMER = 0x02010845ull;
+
+static const uint64_t P9N2_CAPP_1_LINK_DELAY_TIMER = 0x04010845ull;
+
+
+static const uint64_t P9N2_PEC_LOCAL_FIR = 0x0D04000Aull;
+
+static const uint64_t P9N2_PEC_LOCAL_FIR_AND = 0x0D04000Bull;
+
+static const uint64_t P9N2_PEC_LOCAL_FIR_OR = 0x0D04000Cull;
+
+static const uint64_t P9N2_PEC_0_LOCAL_FIR = 0x0D04000Aull;
+
+static const uint64_t P9N2_PEC_0_LOCAL_FIR_AND = 0x0D04000Bull;
+
+static const uint64_t P9N2_PEC_0_LOCAL_FIR_OR = 0x0D04000Cull;
+
+static const uint64_t P9N2_PEC_1_LOCAL_FIR = 0x0E04000Aull;
+
+static const uint64_t P9N2_PEC_1_LOCAL_FIR_AND = 0x0E04000Bull;
+
+static const uint64_t P9N2_PEC_1_LOCAL_FIR_OR = 0x0E04000Cull;
+
+static const uint64_t P9N2_PEC_2_LOCAL_FIR = 0x0F04000Aull;
+
+static const uint64_t P9N2_PEC_2_LOCAL_FIR_AND = 0x0F04000Bull;
+
+static const uint64_t P9N2_PEC_2_LOCAL_FIR_OR = 0x0F04000Cull;
+
+
+static const uint64_t P9N2_PEC_LOCAL_FIR_ACTION0 = 0x0D040010ull;
+
+static const uint64_t P9N2_PEC_0_LOCAL_FIR_ACTION0 = 0x0D040010ull;
+
+static const uint64_t P9N2_PEC_1_LOCAL_FIR_ACTION0 = 0x0E040010ull;
+
+static const uint64_t P9N2_PEC_2_LOCAL_FIR_ACTION0 = 0x0F040010ull;
+
+
+static const uint64_t P9N2_PEC_LOCAL_FIR_ACTION1 = 0x0D040011ull;
+
+static const uint64_t P9N2_PEC_0_LOCAL_FIR_ACTION1 = 0x0D040011ull;
+
+static const uint64_t P9N2_PEC_1_LOCAL_FIR_ACTION1 = 0x0E040011ull;
+
+static const uint64_t P9N2_PEC_2_LOCAL_FIR_ACTION1 = 0x0F040011ull;
+
+
+static const uint64_t P9N2_PEC_LOCAL_FIR_MASK = 0x0D04000Dull;
+
+static const uint64_t P9N2_PEC_LOCAL_FIR_MASK_AND = 0x0D04000Eull;
+
+static const uint64_t P9N2_PEC_LOCAL_FIR_MASK_OR = 0x0D04000Full;
+
+static const uint64_t P9N2_PEC_0_LOCAL_FIR_MASK = 0x0D04000Dull;
+
+static const uint64_t P9N2_PEC_0_LOCAL_FIR_MASK_AND = 0x0D04000Eull;
+
+static const uint64_t P9N2_PEC_0_LOCAL_FIR_MASK_OR = 0x0D04000Full;
+
+static const uint64_t P9N2_PEC_1_LOCAL_FIR_MASK = 0x0E04000Dull;
+
+static const uint64_t P9N2_PEC_1_LOCAL_FIR_MASK_AND = 0x0E04000Eull;
+
+static const uint64_t P9N2_PEC_1_LOCAL_FIR_MASK_OR = 0x0E04000Full;
+
+static const uint64_t P9N2_PEC_2_LOCAL_FIR_MASK = 0x0F04000Dull;
+
+static const uint64_t P9N2_PEC_2_LOCAL_FIR_MASK_AND = 0x0F04000Eull;
+
+static const uint64_t P9N2_PEC_2_LOCAL_FIR_MASK_OR = 0x0F04000Full;
+
+
+static const uint64_t P9N2_PEC_LOCAL_XSTOP_ERR = 0x0D040018ull;
+
+static const uint64_t P9N2_PEC_0_LOCAL_XSTOP_ERR = 0x0D040018ull;
+
+static const uint64_t P9N2_PEC_1_LOCAL_XSTOP_ERR = 0x0E040018ull;
+
+static const uint64_t P9N2_PEC_2_LOCAL_XSTOP_ERR = 0x0F040018ull;
+
+
+static const uint64_t P9N2_PEC_LOCAL_XSTOP_MASK = 0x0D040019ull;
+
+static const uint64_t P9N2_PEC_0_LOCAL_XSTOP_MASK = 0x0D040019ull;
+
+static const uint64_t P9N2_PEC_1_LOCAL_XSTOP_MASK = 0x0E040019ull;
+
+static const uint64_t P9N2_PEC_2_LOCAL_XSTOP_MASK = 0x0F040019ull;
+
+
+static const uint64_t P9N2_PU_NPU1_SM1_LOW_PWR = 0x0501112Cull;
+
+static const uint64_t P9N2_PU_NPU1_SM2_LOW_PWR = 0x0501114Cull;
+
+static const uint64_t P9N2_PU_NPU_SM1_LOW_PWR = 0x0501132Cull;
+
+static const uint64_t P9N2_PU_NPU_SM2_LOW_PWR = 0x0501134Cull;
+
+static const uint64_t P9N2__SM1_LOW_PWR = 0x0501152Cull;
+
+static const uint64_t P9N2__SM2_LOW_PWR = 0x0501154Cull;
+
+
+static const uint64_t P9N2_PU_NPU0_CTL_LOW_WATER = 0x05011098ull;
+
+static const uint64_t P9N2_PU_NPU2_CTL_LOW_WATER = 0x05011298ull;
+
+static const uint64_t P9N2_PU_NPU0_SM0_LOW_WATER = 0x05011008ull;
+
+static const uint64_t P9N2_PU_NPU0_SM1_LOW_WATER = 0x05011038ull;
+
+static const uint64_t P9N2_PU_NPU0_SM3_LOW_WATER = 0x05011068ull;
+
+static const uint64_t P9N2_PU_NPU2_SM0_LOW_WATER = 0x05011208ull;
+
+static const uint64_t P9N2_PU_NPU2_SM1_LOW_WATER = 0x05011238ull;
+
+static const uint64_t P9N2_PU_NPU2_SM3_LOW_WATER = 0x05011268ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_CTL_LOW_WATER = 0x05011498ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM0_LOW_WATER = 0x05011408ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM1_LOW_WATER = 0x05011438ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM3_LOW_WATER = 0x05011468ull;
+
+
+static const uint64_t P9N2_NV_LPCTH_CONFIG = 0x050110D0ull;
+
+static const uint64_t P9N2_NV_0_LPCTH_CONFIG = 0x050110D0ull;
+
+static const uint64_t P9N2_NV_4_LPCTH_CONFIG = 0x050114D0ull;
+
+static const uint64_t P9N2_PU_NPU2_NTL0_LPCTH_CONFIG = 0x050112D0ull;
+
+
+static const uint64_t P9N2_PU_LPC_BASE_REG = 0x00090040ull;
+
+
+static const uint64_t P9N2_PU_LPC_CMD_REG = 0x00090041ull;
+
+
+static const uint64_t P9N2_PU_LPC_DATA_REG = 0x00090042ull;
+
+
+static const uint64_t P9N2_PU_LPC_STATUS_REG = 0x00090043ull;
+
+
+static const uint64_t P9N2_PHB_MASK_REG = 0x0D01090Bull;
+
+static const uint64_t P9N2_PHB_MASK_REG_AND = 0x0D01090Cull;
+
+static const uint64_t P9N2_PHB_MASK_REG_OR = 0x0D01090Dull;
+
+static const uint64_t P9N2_PHB_0_MASK_REG = 0x0D01090Bull;
+
+static const uint64_t P9N2_PHB_0_MASK_REG_AND = 0x0D01090Cull;
+
+static const uint64_t P9N2_PHB_0_MASK_REG_OR = 0x0D01090Dull;
+
+static const uint64_t P9N2_PHB_1_MASK_REG = 0x0E01090Bull;
+
+static const uint64_t P9N2_PHB_1_MASK_REG_AND = 0x0E01090Cull;
+
+static const uint64_t P9N2_PHB_1_MASK_REG_OR = 0x0E01090Dull;
+
+static const uint64_t P9N2_PHB_2_MASK_REG = 0x0E01094Bull;
+
+static const uint64_t P9N2_PHB_2_MASK_REG_AND = 0x0E01094Cull;
+
+static const uint64_t P9N2_PHB_2_MASK_REG_OR = 0x0E01094Dull;
+
+static const uint64_t P9N2_PHB_3_MASK_REG = 0x0F01090Bull;
+
+static const uint64_t P9N2_PHB_3_MASK_REG_AND = 0x0F01090Cull;
+
+static const uint64_t P9N2_PHB_3_MASK_REG_OR = 0x0F01090Dull;
+
+static const uint64_t P9N2_PHB_4_MASK_REG = 0x0F01094Bull;
+
+static const uint64_t P9N2_PHB_4_MASK_REG_AND = 0x0F01094Cull;
+
+static const uint64_t P9N2_PHB_4_MASK_REG_OR = 0x0F01094Dull;
+
+static const uint64_t P9N2_PHB_5_MASK_REG = 0x0F01098Bull;
+
+static const uint64_t P9N2_PHB_5_MASK_REG_AND = 0x0F01098Cull;
+
+static const uint64_t P9N2_PHB_5_MASK_REG_OR = 0x0F01098Dull;
+
+
+static const uint64_t P9N2_PU_MCC_FIR_REG = 0x03011400ull;
+
+static const uint64_t P9N2_PU_MCC_FIR_REG_AND = 0x03011401ull;
+
+static const uint64_t P9N2_PU_MCC_FIR_REG_OR = 0x03011402ull;
+
+static const uint64_t P9N2_PU_MCD1_MCC_FIR_REG = 0x03011000ull;
+
+static const uint64_t P9N2_PU_MCD1_MCC_FIR_REG_AND = 0x03011001ull;
+
+static const uint64_t P9N2_PU_MCD1_MCC_FIR_REG_OR = 0x03011002ull;
+
+
+static const uint64_t P9N2_PU_MCD_DBG = 0x03011413ull;
+
+static const uint64_t P9N2_PU_MCD1_MCD_DBG = 0x03011013ull;
+
+
+static const uint64_t P9N2_PU_MCD_ECAP = 0x03011412ull;
+
+static const uint64_t P9N2_PU_MCD1_MCD_ECAP = 0x03011012ull;
+
+
+static const uint64_t P9N2_PU_MCD_FIR_ACTION0_REG = 0x03011406ull;
+
+static const uint64_t P9N2_PU_MCD1_MCD_FIR_ACTION0_REG = 0x03011006ull;
+
+
+static const uint64_t P9N2_PU_MCD_FIR_ACTION1_REG = 0x03011407ull;
+
+static const uint64_t P9N2_PU_MCD1_MCD_FIR_ACTION1_REG = 0x03011007ull;
+
+
+static const uint64_t P9N2_PU_MCD_FIR_MASK_REG = 0x03011403ull;
+
+static const uint64_t P9N2_PU_MCD_FIR_MASK_REG_AND = 0x03011404ull;
+
+static const uint64_t P9N2_PU_MCD_FIR_MASK_REG_OR = 0x03011405ull;
+
+static const uint64_t P9N2_PU_MCD1_MCD_FIR_MASK_REG = 0x03011003ull;
+
+static const uint64_t P9N2_PU_MCD1_MCD_FIR_MASK_REG_AND = 0x03011004ull;
+
+static const uint64_t P9N2_PU_MCD1_MCD_FIR_MASK_REG_OR = 0x03011005ull;
+
+
+static const uint64_t P9N2_PU_MCD_FIR_WOF_REG = 0x03011408ull;
+
+static const uint64_t P9N2_PU_MCD1_MCD_FIR_WOF_REG = 0x03011008ull;
+
+
+static const uint64_t P9N2_PU_MIB_XIICAC = 0x000E0009ull;
+//DUPS: 05012419, 09011059, 0C011059,
+
+static const uint64_t P9N2_PU_MIB_XIMEM = 0x000E0007ull;
+//DUPS: 05012417, 09011057, 0C011057,
+
+static const uint64_t P9N2_PU_MIB_XISGB = 0x000E0008ull;
+//DUPS: 05012418, 09011058, 0C011058,
+
+static const uint64_t P9N2_PU_MIB_XISIB = 0x000E0006ull;
+
+
+static const uint64_t P9N2__CTL_MISC_CONFIG = 0x05011686ull;
+
+
+static const uint64_t P9N2__CTL_MISC_HOLD = 0x05011684ull;
+
+
+static const uint64_t P9N2__CTL_MISC_MASK = 0x05011685ull;
+
+
+static const uint64_t P9N2_PU_NMMU_MMCQ_PB_MODE_REG = 0x05012C15ull;
+
+
+static const uint64_t P9N2_PEC_0_STACK0_MMIOBAR0_MASK_REG = 0x04010C4Full;
+
+static const uint64_t P9N2_PEC_1_STACK0_MMIOBAR0_MASK_REG = 0x0401104Full;
+
+static const uint64_t P9N2_PEC_1_STACK1_MMIOBAR0_MASK_REG = 0x0401108Full;
+
+static const uint64_t P9N2_PEC_1_STACK2_MMIOBAR0_MASK_REG = 0x040110CFull;
+
+static const uint64_t P9N2_PEC_2_STACK0_MMIOBAR0_MASK_REG = 0x0401144Full;
+
+static const uint64_t P9N2_PEC_2_STACK1_MMIOBAR0_MASK_REG = 0x0401148Full;
+
+static const uint64_t P9N2_PEC_2_STACK2_MMIOBAR0_MASK_REG = 0x040114CFull;
+
+static const uint64_t P9N2_PEC_STACK0_MMIOBAR0_MASK_REG = 0x04010C4Full;
+
+static const uint64_t P9N2_PHB_MMIOBAR0_MASK_REG = 0x04010C4Full;
+
+static const uint64_t P9N2_PHB_0_MMIOBAR0_MASK_REG = 0x04010C4Full;
+
+static const uint64_t P9N2_PHB_1_MMIOBAR0_MASK_REG = 0x0401104Full;
+
+static const uint64_t P9N2_PHB_2_MMIOBAR0_MASK_REG = 0x0401108Full;
+
+static const uint64_t P9N2_PHB_3_MMIOBAR0_MASK_REG = 0x0401144Full;
+
+static const uint64_t P9N2_PHB_4_MMIOBAR0_MASK_REG = 0x0401148Full;
+
+static const uint64_t P9N2_PHB_5_MMIOBAR0_MASK_REG = 0x040114CFull;
+
+
+static const uint64_t P9N2_PEC_0_STACK0_MMIOBAR0_REG = 0x04010C4Eull;
+
+static const uint64_t P9N2_PEC_1_STACK0_MMIOBAR0_REG = 0x0401104Eull;
+
+static const uint64_t P9N2_PEC_1_STACK1_MMIOBAR0_REG = 0x0401108Eull;
+
+static const uint64_t P9N2_PEC_1_STACK2_MMIOBAR0_REG = 0x040110CEull;
+
+static const uint64_t P9N2_PEC_2_STACK0_MMIOBAR0_REG = 0x0401144Eull;
+
+static const uint64_t P9N2_PEC_2_STACK1_MMIOBAR0_REG = 0x0401148Eull;
+
+static const uint64_t P9N2_PEC_2_STACK2_MMIOBAR0_REG = 0x040114CEull;
+
+static const uint64_t P9N2_PEC_STACK0_MMIOBAR0_REG = 0x04010C4Eull;
+
+static const uint64_t P9N2_PHB_MMIOBAR0_REG = 0x04010C4Eull;
+
+static const uint64_t P9N2_PHB_0_MMIOBAR0_REG = 0x04010C4Eull;
+
+static const uint64_t P9N2_PHB_1_MMIOBAR0_REG = 0x0401104Eull;
+
+static const uint64_t P9N2_PHB_2_MMIOBAR0_REG = 0x0401108Eull;
+
+static const uint64_t P9N2_PHB_3_MMIOBAR0_REG = 0x0401144Eull;
+
+static const uint64_t P9N2_PHB_4_MMIOBAR0_REG = 0x0401148Eull;
+
+static const uint64_t P9N2_PHB_5_MMIOBAR0_REG = 0x040114CEull;
+
+
+static const uint64_t P9N2_PEC_0_STACK0_MMIOBAR1_MASK_REG = 0x04010C51ull;
+
+static const uint64_t P9N2_PEC_1_STACK0_MMIOBAR1_MASK_REG = 0x04011051ull;
+
+static const uint64_t P9N2_PEC_1_STACK1_MMIOBAR1_MASK_REG = 0x04011091ull;
+
+static const uint64_t P9N2_PEC_1_STACK2_MMIOBAR1_MASK_REG = 0x040110D1ull;
+
+static const uint64_t P9N2_PEC_2_STACK0_MMIOBAR1_MASK_REG = 0x04011451ull;
+
+static const uint64_t P9N2_PEC_2_STACK1_MMIOBAR1_MASK_REG = 0x04011491ull;
+
+static const uint64_t P9N2_PEC_2_STACK2_MMIOBAR1_MASK_REG = 0x040114D1ull;
+
+static const uint64_t P9N2_PEC_STACK0_MMIOBAR1_MASK_REG = 0x04010C51ull;
+
+static const uint64_t P9N2_PHB_MMIOBAR1_MASK_REG = 0x04010C51ull;
+
+static const uint64_t P9N2_PHB_0_MMIOBAR1_MASK_REG = 0x04010C51ull;
+
+static const uint64_t P9N2_PHB_1_MMIOBAR1_MASK_REG = 0x04011051ull;
+
+static const uint64_t P9N2_PHB_2_MMIOBAR1_MASK_REG = 0x04011091ull;
+
+static const uint64_t P9N2_PHB_3_MMIOBAR1_MASK_REG = 0x04011451ull;
+
+static const uint64_t P9N2_PHB_4_MMIOBAR1_MASK_REG = 0x04011491ull;
+
+static const uint64_t P9N2_PHB_5_MMIOBAR1_MASK_REG = 0x040114D1ull;
+
+
+static const uint64_t P9N2_PEC_0_STACK0_MMIOBAR1_REG = 0x04010C50ull;
+
+static const uint64_t P9N2_PEC_1_STACK0_MMIOBAR1_REG = 0x04011050ull;
+
+static const uint64_t P9N2_PEC_1_STACK1_MMIOBAR1_REG = 0x04011090ull;
+
+static const uint64_t P9N2_PEC_1_STACK2_MMIOBAR1_REG = 0x040110D0ull;
+
+static const uint64_t P9N2_PEC_2_STACK0_MMIOBAR1_REG = 0x04011450ull;
+
+static const uint64_t P9N2_PEC_2_STACK1_MMIOBAR1_REG = 0x04011490ull;
+
+static const uint64_t P9N2_PEC_2_STACK2_MMIOBAR1_REG = 0x040114D0ull;
+
+static const uint64_t P9N2_PEC_STACK0_MMIOBAR1_REG = 0x04010C50ull;
+
+static const uint64_t P9N2_PHB_MMIOBAR1_REG = 0x04010C50ull;
+
+static const uint64_t P9N2_PHB_0_MMIOBAR1_REG = 0x04010C50ull;
+
+static const uint64_t P9N2_PHB_1_MMIOBAR1_REG = 0x04011050ull;
+
+static const uint64_t P9N2_PHB_2_MMIOBAR1_REG = 0x04011090ull;
+
+static const uint64_t P9N2_PHB_3_MMIOBAR1_REG = 0x04011450ull;
+
+static const uint64_t P9N2_PHB_4_MMIOBAR1_REG = 0x04011490ull;
+
+static const uint64_t P9N2_PHB_5_MMIOBAR1_REG = 0x040114D0ull;
+
+
+static const uint64_t P9N2_NV_MMIOPA0_CONFIG = 0x050110D6ull;
+
+static const uint64_t P9N2_NV_0_MMIOPA0_CONFIG = 0x050110D6ull;
+
+static const uint64_t P9N2_NV_4_MMIOPA0_CONFIG = 0x050114D6ull;
+
+static const uint64_t P9N2_PU_NPU2_NTL0_MMIOPA0_CONFIG = 0x050112D6ull;
+
+
+static const uint64_t P9N2_NV_MMIOPA1_CONFIG = 0x050110D7ull;
+
+static const uint64_t P9N2_NV_0_MMIOPA1_CONFIG = 0x050110D7ull;
+
+static const uint64_t P9N2_NV_4_MMIOPA1_CONFIG = 0x050114D7ull;
+
+static const uint64_t P9N2_PU_NPU2_NTL0_MMIOPA1_CONFIG = 0x050112D7ull;
+
+
+static const uint64_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_MISC = 0x05012C53ull;
+
+
+static const uint64_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SLB = 0x05012C54ull;
+
+
+static const uint64_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM = 0x05012C52ull;
+
+
+static const uint64_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB = 0x05012C55ull;
+
+
+static const uint64_t P9N2_PU_NMMU_MM_CFG_NMMU_XLAT_CTL_REG0 = 0x05012C4Aull;
+
+
+static const uint64_t P9N2_PU_NMMU_MM_CFG_NMMU_XLAT_CTL_REG1 = 0x05012C4Bull;
+
+
+static const uint64_t P9N2_PU_NMMU_MM_CFG_NMMU_XLAT_CTL_REG2 = 0x05012C4Cull;
+
+
+static const uint64_t P9N2_PU_NMMU_MM_EPSILON_COUNTER_VALUE = 0x05012C1Dull;
+
+
+static const uint64_t P9N2_PU_NMMU_MM_FIR1_ACTION0_REG = 0x05012C46ull;
+
+
+static const uint64_t P9N2_PU_NMMU_MM_FIR1_ACTION1_REG = 0x05012C47ull;
+
+
+static const uint64_t P9N2_PU_NMMU_MM_FIR1_MASK_REG = 0x05012C43ull;
+
+static const uint64_t P9N2_PU_NMMU_MM_FIR1_MASK_REG_AND = 0x05012C44ull;
+
+static const uint64_t P9N2_PU_NMMU_MM_FIR1_MASK_REG_OR = 0x05012C45ull;
+
+
+static const uint64_t P9N2_PU_NMMU_MM_FIR1_REG = 0x05012C40ull;
+
+static const uint64_t P9N2_PU_NMMU_MM_FIR1_REG_AND = 0x05012C41ull;
+
+static const uint64_t P9N2_PU_NMMU_MM_FIR1_REG_OR = 0x05012C42ull;
+
+
+static const uint64_t P9N2_PU_NMMU_MM_FIR1_WOF_REG = 0x05012C48ull;
+
+
+static const uint64_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE = 0x05012C59ull;
+
+
+static const uint64_t P9N2_PU_NMMU_MM_NMMU_ERR_INJ = 0x05012C58ull;
+
+
+static const uint64_t P9N2_PU_NMMU_MM_NMMU_ERR_LOG = 0x05012C57ull;
+
+
+static const uint64_t P9N2_PU_NMMU_MM_NMMU_FLT_STAT_REG = 0x05012C51ull;
+
+
+static const uint64_t P9N2_PU_NMMU_MM_NMMU_PMU0_CNT_REG = 0x05012C4Full;
+
+
+static const uint64_t P9N2_PU_NMMU_MM_NMMU_PMU0_CTL_REG = 0x05012C4Dull;
+
+
+static const uint64_t P9N2_PU_NMMU_MM_NMMU_PMU1_CNT_REG = 0x05012C50ull;
+
+
+static const uint64_t P9N2_PU_NMMU_MM_NMMU_PMU1_CTL_REG = 0x05012C4Eull;
+
+
+static const uint64_t P9N2_PEC_MODE_REG = 0x0D040008ull;
+
+static const uint64_t P9N2_PEC_0_MODE_REG = 0x0D040008ull;
+
+static const uint64_t P9N2_PEC_1_MODE_REG = 0x0E040008ull;
+
+static const uint64_t P9N2_PEC_2_MODE_REG = 0x0F040008ull;
+
+
+static const uint64_t P9N2_PU_MODE_REGISTER = 0x00010008ull;
+
+
+static const uint64_t P9N2_PU_MODE_REGISTER_B = 0x000A0006ull;
+
+
+static const uint64_t P9N2_PU_MODE_REGISTER_C = 0x000A1006ull;
+
+
+static const uint64_t P9N2_PU_MODE_REGISTER_D = 0x000A2006ull;
+
+
+static const uint64_t P9N2_PU_MODE_REGISTER_E = 0x000A3006ull;
+
+
+static const uint64_t P9N2_PEC_MULTICAST_GROUP_1 = 0x0D0F0001ull;
+
+static const uint64_t P9N2_PEC_0_MULTICAST_GROUP_1 = 0x0D0F0001ull;
+
+static const uint64_t P9N2_PEC_1_MULTICAST_GROUP_1 = 0x0E0F0001ull;
+
+static const uint64_t P9N2_PEC_2_MULTICAST_GROUP_1 = 0x0F0F0001ull;
+
+
+static const uint64_t P9N2_PEC_MULTICAST_GROUP_2 = 0x0D0F0002ull;
+
+static const uint64_t P9N2_PEC_0_MULTICAST_GROUP_2 = 0x0D0F0002ull;
+
+static const uint64_t P9N2_PEC_1_MULTICAST_GROUP_2 = 0x0E0F0002ull;
+
+static const uint64_t P9N2_PEC_2_MULTICAST_GROUP_2 = 0x0F0F0002ull;
+
+
+static const uint64_t P9N2_PEC_MULTICAST_GROUP_3 = 0x0D0F0003ull;
+
+static const uint64_t P9N2_PEC_0_MULTICAST_GROUP_3 = 0x0D0F0003ull;
+
+static const uint64_t P9N2_PEC_1_MULTICAST_GROUP_3 = 0x0E0F0003ull;
+
+static const uint64_t P9N2_PEC_2_MULTICAST_GROUP_3 = 0x0F0F0003ull;
+
+
+static const uint64_t P9N2_PEC_MULTICAST_GROUP_4 = 0x0D0F0004ull;
+
+static const uint64_t P9N2_PEC_0_MULTICAST_GROUP_4 = 0x0D0F0004ull;
+
+static const uint64_t P9N2_PEC_1_MULTICAST_GROUP_4 = 0x0E0F0004ull;
+
+static const uint64_t P9N2_PEC_2_MULTICAST_GROUP_4 = 0x0F0F0004ull;
+
+
+static const uint64_t P9N2_PU_NPU0_CTL_NDT0_BAR = 0x0501109Dull;
+
+static const uint64_t P9N2_PU_NPU2_CTL_NDT0_BAR = 0x0501129Dull;
+
+static const uint64_t P9N2_PU_NPU0_SM0_NDT0_BAR = 0x0501100Dull;
+
+static const uint64_t P9N2_PU_NPU0_SM1_NDT0_BAR = 0x0501103Dull;
+
+static const uint64_t P9N2_PU_NPU0_SM3_NDT0_BAR = 0x0501106Dull;
+
+static const uint64_t P9N2_PU_NPU2_SM0_NDT0_BAR = 0x0501120Dull;
+
+static const uint64_t P9N2_PU_NPU2_SM1_NDT0_BAR = 0x0501123Dull;
+
+static const uint64_t P9N2_PU_NPU2_SM3_NDT0_BAR = 0x0501126Dull;
+
+static const uint64_t P9N2_PU_NPU_MSC_CTL_NDT0_BAR = 0x0501149Dull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM0_NDT0_BAR = 0x0501140Dull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM1_NDT0_BAR = 0x0501143Dull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM3_NDT0_BAR = 0x0501146Dull;
+
+
+static const uint64_t P9N2_PU_NPU0_CTL_NDT1_BAR = 0x0501109Eull;
+
+static const uint64_t P9N2_PU_NPU2_CTL_NDT1_BAR = 0x0501129Eull;
+
+static const uint64_t P9N2_PU_NPU0_SM0_NDT1_BAR = 0x0501100Eull;
+
+static const uint64_t P9N2_PU_NPU0_SM1_NDT1_BAR = 0x0501103Eull;
+
+static const uint64_t P9N2_PU_NPU0_SM3_NDT1_BAR = 0x0501106Eull;
+
+static const uint64_t P9N2_PU_NPU2_SM0_NDT1_BAR = 0x0501120Eull;
+
+static const uint64_t P9N2_PU_NPU2_SM1_NDT1_BAR = 0x0501123Eull;
+
+static const uint64_t P9N2_PU_NPU2_SM3_NDT1_BAR = 0x0501126Eull;
+
+static const uint64_t P9N2_PU_NPU_MSC_CTL_NDT1_BAR = 0x0501149Eull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM0_NDT1_BAR = 0x0501140Eull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM1_NDT1_BAR = 0x0501143Eull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM3_NDT1_BAR = 0x0501146Eull;
+
+
+static const uint64_t P9N2_PEC_NESTTRC_REG = 0x04010C03ull;
+
+static const uint64_t P9N2_PEC_0_NESTTRC_REG = 0x04010C03ull;
+
+static const uint64_t P9N2_PEC_1_NESTTRC_REG = 0x04011003ull;
+
+static const uint64_t P9N2_PEC_2_NESTTRC_REG = 0x04011403ull;
+
+
+static const uint64_t P9N2_PEC_0_STACK0_NET_CTRL0 = 0x0D0F0040ull;
+
+static const uint64_t P9N2_PEC_0_STACK0_NET_CTRL0_WAND = 0x0D0F0041ull;
+
+static const uint64_t P9N2_PEC_0_STACK0_NET_CTRL0_WOR = 0x0D0F0042ull;
+
+static const uint64_t P9N2_PEC_1_STACK0_NET_CTRL0 = 0x0E0F0040ull;
+
+static const uint64_t P9N2_PEC_1_STACK0_NET_CTRL0_WAND = 0x0E0F0041ull;
+
+static const uint64_t P9N2_PEC_1_STACK0_NET_CTRL0_WOR = 0x0E0F0042ull;
+
+static const uint64_t P9N2_PEC_2_STACK0_NET_CTRL0 = 0x0F0F0040ull;
+
+static const uint64_t P9N2_PEC_2_STACK0_NET_CTRL0_WAND = 0x0F0F0041ull;
+
+static const uint64_t P9N2_PEC_2_STACK0_NET_CTRL0_WOR = 0x0F0F0042ull;
+
+static const uint64_t P9N2_PEC_STACK0_NET_CTRL0 = 0x0D0F0040ull;
+
+static const uint64_t P9N2_PEC_STACK0_NET_CTRL0_WAND = 0x0D0F0041ull;
+
+static const uint64_t P9N2_PEC_STACK0_NET_CTRL0_WOR = 0x0D0F0042ull;
+
+
+static const uint64_t P9N2_PEC_0_STACK0_NET_CTRL1 = 0x0D0F0044ull;
+
+static const uint64_t P9N2_PEC_0_STACK0_NET_CTRL1_WAND = 0x0D0F0045ull;
+
+static const uint64_t P9N2_PEC_0_STACK0_NET_CTRL1_WOR = 0x0D0F0046ull;
+
+static const uint64_t P9N2_PEC_1_STACK0_NET_CTRL1 = 0x0E0F0044ull;
+
+static const uint64_t P9N2_PEC_1_STACK0_NET_CTRL1_WAND = 0x0E0F0045ull;
+
+static const uint64_t P9N2_PEC_1_STACK0_NET_CTRL1_WOR = 0x0E0F0046ull;
+
+static const uint64_t P9N2_PEC_2_STACK0_NET_CTRL1 = 0x0F0F0044ull;
+
+static const uint64_t P9N2_PEC_2_STACK0_NET_CTRL1_WAND = 0x0F0F0045ull;
+
+static const uint64_t P9N2_PEC_2_STACK0_NET_CTRL1_WOR = 0x0F0F0046ull;
+
+static const uint64_t P9N2_PEC_STACK0_NET_CTRL1 = 0x0D0F0044ull;
+
+static const uint64_t P9N2_PEC_STACK0_NET_CTRL1_WAND = 0x0D0F0045ull;
+
+static const uint64_t P9N2_PEC_STACK0_NET_CTRL1_WOR = 0x0D0F0046ull;
+
+
+static const uint64_t P9N2_PEC_0_STACK0_NFIRACTION0_REG = 0x04010C46ull;
+
+static const uint64_t P9N2_PEC_1_STACK0_NFIRACTION0_REG = 0x04011046ull;
+
+static const uint64_t P9N2_PEC_1_STACK1_NFIRACTION0_REG = 0x04011086ull;
+
+static const uint64_t P9N2_PEC_1_STACK2_NFIRACTION0_REG = 0x040110C6ull;
+
+static const uint64_t P9N2_PEC_2_STACK0_NFIRACTION0_REG = 0x04011446ull;
+
+static const uint64_t P9N2_PEC_2_STACK1_NFIRACTION0_REG = 0x04011486ull;
+
+static const uint64_t P9N2_PEC_2_STACK2_NFIRACTION0_REG = 0x040114C6ull;
+
+static const uint64_t P9N2_PEC_STACK0_NFIRACTION0_REG = 0x04010C46ull;
+
+static const uint64_t P9N2_PHB_NFIRACTION0_REG = 0x04010C46ull;
+
+static const uint64_t P9N2_PHB_0_NFIRACTION0_REG = 0x04010C46ull;
+
+static const uint64_t P9N2_PHB_1_NFIRACTION0_REG = 0x04011046ull;
+
+static const uint64_t P9N2_PHB_2_NFIRACTION0_REG = 0x04011086ull;
+
+static const uint64_t P9N2_PHB_3_NFIRACTION0_REG = 0x04011446ull;
+
+static const uint64_t P9N2_PHB_4_NFIRACTION0_REG = 0x04011486ull;
+
+static const uint64_t P9N2_PHB_5_NFIRACTION0_REG = 0x040114C6ull;
+
+
+static const uint64_t P9N2_PEC_0_STACK0_NFIRACTION1_REG = 0x04010C47ull;
+
+static const uint64_t P9N2_PEC_1_STACK0_NFIRACTION1_REG = 0x04011047ull;
+
+static const uint64_t P9N2_PEC_1_STACK1_NFIRACTION1_REG = 0x04011087ull;
+
+static const uint64_t P9N2_PEC_1_STACK2_NFIRACTION1_REG = 0x040110C7ull;
+
+static const uint64_t P9N2_PEC_2_STACK0_NFIRACTION1_REG = 0x04011447ull;
+
+static const uint64_t P9N2_PEC_2_STACK1_NFIRACTION1_REG = 0x04011487ull;
+
+static const uint64_t P9N2_PEC_2_STACK2_NFIRACTION1_REG = 0x040114C7ull;
+
+static const uint64_t P9N2_PEC_STACK0_NFIRACTION1_REG = 0x04010C47ull;
+
+static const uint64_t P9N2_PHB_NFIRACTION1_REG = 0x04010C47ull;
+
+static const uint64_t P9N2_PHB_0_NFIRACTION1_REG = 0x04010C47ull;
+
+static const uint64_t P9N2_PHB_1_NFIRACTION1_REG = 0x04011047ull;
+
+static const uint64_t P9N2_PHB_2_NFIRACTION1_REG = 0x04011087ull;
+
+static const uint64_t P9N2_PHB_3_NFIRACTION1_REG = 0x04011447ull;
+
+static const uint64_t P9N2_PHB_4_NFIRACTION1_REG = 0x04011487ull;
+
+static const uint64_t P9N2_PHB_5_NFIRACTION1_REG = 0x040114C7ull;
+
+
+static const uint64_t P9N2_PEC_0_STACK0_NFIRMASK_REG = 0x04010C43ull;
+
+static const uint64_t P9N2_PEC_0_STACK0_NFIRMASK_REG_AND = 0x04010C44ull;
+
+static const uint64_t P9N2_PEC_0_STACK0_NFIRMASK_REG_OR = 0x04010C45ull;
+
+static const uint64_t P9N2_PEC_1_STACK0_NFIRMASK_REG = 0x04011043ull;
+
+static const uint64_t P9N2_PEC_1_STACK0_NFIRMASK_REG_AND = 0x04011044ull;
+
+static const uint64_t P9N2_PEC_1_STACK0_NFIRMASK_REG_OR = 0x04011045ull;
+
+static const uint64_t P9N2_PEC_1_STACK1_NFIRMASK_REG = 0x04011083ull;
+
+static const uint64_t P9N2_PEC_1_STACK1_NFIRMASK_REG_AND = 0x04011084ull;
+
+static const uint64_t P9N2_PEC_1_STACK1_NFIRMASK_REG_OR = 0x04011085ull;
+
+static const uint64_t P9N2_PEC_1_STACK2_NFIRMASK_REG = 0x040110C3ull;
+
+static const uint64_t P9N2_PEC_1_STACK2_NFIRMASK_REG_AND = 0x040110C4ull;
+
+static const uint64_t P9N2_PEC_1_STACK2_NFIRMASK_REG_OR = 0x040110C5ull;
+
+static const uint64_t P9N2_PEC_2_STACK0_NFIRMASK_REG = 0x04011443ull;
+
+static const uint64_t P9N2_PEC_2_STACK0_NFIRMASK_REG_AND = 0x04011444ull;
+
+static const uint64_t P9N2_PEC_2_STACK0_NFIRMASK_REG_OR = 0x04011445ull;
+
+static const uint64_t P9N2_PEC_2_STACK1_NFIRMASK_REG = 0x04011483ull;
+
+static const uint64_t P9N2_PEC_2_STACK1_NFIRMASK_REG_AND = 0x04011484ull;
+
+static const uint64_t P9N2_PEC_2_STACK1_NFIRMASK_REG_OR = 0x04011485ull;
+
+static const uint64_t P9N2_PEC_2_STACK2_NFIRMASK_REG = 0x040114C3ull;
+
+static const uint64_t P9N2_PEC_2_STACK2_NFIRMASK_REG_AND = 0x040114C4ull;
+
+static const uint64_t P9N2_PEC_2_STACK2_NFIRMASK_REG_OR = 0x040114C5ull;
+
+static const uint64_t P9N2_PEC_STACK0_NFIRMASK_REG = 0x04010C43ull;
+
+static const uint64_t P9N2_PEC_STACK0_NFIRMASK_REG_AND = 0x04010C44ull;
+
+static const uint64_t P9N2_PEC_STACK0_NFIRMASK_REG_OR = 0x04010C45ull;
+
+static const uint64_t P9N2_PHB_NFIRMASK_REG = 0x04010C43ull;
+
+static const uint64_t P9N2_PHB_NFIRMASK_REG_AND = 0x04010C44ull;
+
+static const uint64_t P9N2_PHB_NFIRMASK_REG_OR = 0x04010C45ull;
+
+static const uint64_t P9N2_PHB_0_NFIRMASK_REG = 0x04010C43ull;
+
+static const uint64_t P9N2_PHB_0_NFIRMASK_REG_AND = 0x04010C44ull;
+
+static const uint64_t P9N2_PHB_0_NFIRMASK_REG_OR = 0x04010C45ull;
+
+static const uint64_t P9N2_PHB_1_NFIRMASK_REG = 0x04011043ull;
+
+static const uint64_t P9N2_PHB_1_NFIRMASK_REG_AND = 0x04011044ull;
+
+static const uint64_t P9N2_PHB_1_NFIRMASK_REG_OR = 0x04011045ull;
+
+static const uint64_t P9N2_PHB_2_NFIRMASK_REG = 0x04011083ull;
+
+static const uint64_t P9N2_PHB_2_NFIRMASK_REG_AND = 0x04011084ull;
+
+static const uint64_t P9N2_PHB_2_NFIRMASK_REG_OR = 0x04011085ull;
+
+static const uint64_t P9N2_PHB_3_NFIRMASK_REG = 0x04011443ull;
+
+static const uint64_t P9N2_PHB_3_NFIRMASK_REG_AND = 0x04011444ull;
+
+static const uint64_t P9N2_PHB_3_NFIRMASK_REG_OR = 0x04011445ull;
+
+static const uint64_t P9N2_PHB_4_NFIRMASK_REG = 0x04011483ull;
+
+static const uint64_t P9N2_PHB_4_NFIRMASK_REG_AND = 0x04011484ull;
+
+static const uint64_t P9N2_PHB_4_NFIRMASK_REG_OR = 0x04011485ull;
+
+static const uint64_t P9N2_PHB_5_NFIRMASK_REG = 0x040114C3ull;
+
+static const uint64_t P9N2_PHB_5_NFIRMASK_REG_AND = 0x040114C4ull;
+
+static const uint64_t P9N2_PHB_5_NFIRMASK_REG_OR = 0x040114C5ull;
+
+
+static const uint64_t P9N2_PEC_0_STACK0_NFIRWOF_REG = 0x04010C48ull;
+
+static const uint64_t P9N2_PEC_1_STACK0_NFIRWOF_REG = 0x04011048ull;
+
+static const uint64_t P9N2_PEC_1_STACK1_NFIRWOF_REG = 0x04011088ull;
+
+static const uint64_t P9N2_PEC_1_STACK2_NFIRWOF_REG = 0x040110C8ull;
+
+static const uint64_t P9N2_PEC_2_STACK0_NFIRWOF_REG = 0x04011448ull;
+
+static const uint64_t P9N2_PEC_2_STACK1_NFIRWOF_REG = 0x04011488ull;
+
+static const uint64_t P9N2_PEC_2_STACK2_NFIRWOF_REG = 0x040114C8ull;
+
+static const uint64_t P9N2_PEC_STACK0_NFIRWOF_REG = 0x04010C48ull;
+
+static const uint64_t P9N2_PHB_NFIRWOF_REG = 0x04010C48ull;
+
+static const uint64_t P9N2_PHB_0_NFIRWOF_REG = 0x04010C48ull;
+
+static const uint64_t P9N2_PHB_1_NFIRWOF_REG = 0x04011048ull;
+
+static const uint64_t P9N2_PHB_2_NFIRWOF_REG = 0x04011088ull;
+
+static const uint64_t P9N2_PHB_3_NFIRWOF_REG = 0x04011448ull;
+
+static const uint64_t P9N2_PHB_4_NFIRWOF_REG = 0x04011488ull;
+
+static const uint64_t P9N2_PHB_5_NFIRWOF_REG = 0x040114C8ull;
+
+
+static const uint64_t P9N2_PEC_0_STACK0_NFIR_REG = 0x04010C40ull;
+
+static const uint64_t P9N2_PEC_0_STACK0_NFIR_REG_AND = 0x04010C41ull;
+
+static const uint64_t P9N2_PEC_0_STACK0_NFIR_REG_OR = 0x04010C42ull;
+
+static const uint64_t P9N2_PEC_1_STACK0_NFIR_REG = 0x04011040ull;
+
+static const uint64_t P9N2_PEC_1_STACK0_NFIR_REG_AND = 0x04011041ull;
+
+static const uint64_t P9N2_PEC_1_STACK0_NFIR_REG_OR = 0x04011042ull;
+
+static const uint64_t P9N2_PEC_1_STACK1_NFIR_REG = 0x04011080ull;
+
+static const uint64_t P9N2_PEC_1_STACK1_NFIR_REG_AND = 0x04011081ull;
+
+static const uint64_t P9N2_PEC_1_STACK1_NFIR_REG_OR = 0x04011082ull;
+
+static const uint64_t P9N2_PEC_1_STACK2_NFIR_REG = 0x040110C0ull;
+
+static const uint64_t P9N2_PEC_1_STACK2_NFIR_REG_AND = 0x040110C1ull;
+
+static const uint64_t P9N2_PEC_1_STACK2_NFIR_REG_OR = 0x040110C2ull;
+
+static const uint64_t P9N2_PEC_2_STACK0_NFIR_REG = 0x04011440ull;
+
+static const uint64_t P9N2_PEC_2_STACK0_NFIR_REG_AND = 0x04011441ull;
+
+static const uint64_t P9N2_PEC_2_STACK0_NFIR_REG_OR = 0x04011442ull;
+
+static const uint64_t P9N2_PEC_2_STACK1_NFIR_REG = 0x04011480ull;
+
+static const uint64_t P9N2_PEC_2_STACK1_NFIR_REG_AND = 0x04011481ull;
+
+static const uint64_t P9N2_PEC_2_STACK1_NFIR_REG_OR = 0x04011482ull;
+
+static const uint64_t P9N2_PEC_2_STACK2_NFIR_REG = 0x040114C0ull;
+
+static const uint64_t P9N2_PEC_2_STACK2_NFIR_REG_AND = 0x040114C1ull;
+
+static const uint64_t P9N2_PEC_2_STACK2_NFIR_REG_OR = 0x040114C2ull;
+
+static const uint64_t P9N2_PEC_STACK0_NFIR_REG = 0x04010C40ull;
+
+static const uint64_t P9N2_PEC_STACK0_NFIR_REG_AND = 0x04010C41ull;
+
+static const uint64_t P9N2_PEC_STACK0_NFIR_REG_OR = 0x04010C42ull;
+
+static const uint64_t P9N2_PHB_NFIR_REG = 0x04010C40ull;
+
+static const uint64_t P9N2_PHB_NFIR_REG_AND = 0x04010C41ull;
+
+static const uint64_t P9N2_PHB_NFIR_REG_OR = 0x04010C42ull;
+
+static const uint64_t P9N2_PHB_0_NFIR_REG = 0x04010C40ull;
+
+static const uint64_t P9N2_PHB_0_NFIR_REG_AND = 0x04010C41ull;
+
+static const uint64_t P9N2_PHB_0_NFIR_REG_OR = 0x04010C42ull;
+
+static const uint64_t P9N2_PHB_1_NFIR_REG = 0x04011040ull;
+
+static const uint64_t P9N2_PHB_1_NFIR_REG_AND = 0x04011041ull;
+
+static const uint64_t P9N2_PHB_1_NFIR_REG_OR = 0x04011042ull;
+
+static const uint64_t P9N2_PHB_2_NFIR_REG = 0x04011080ull;
+
+static const uint64_t P9N2_PHB_2_NFIR_REG_AND = 0x04011081ull;
+
+static const uint64_t P9N2_PHB_2_NFIR_REG_OR = 0x04011082ull;
+
+static const uint64_t P9N2_PHB_3_NFIR_REG = 0x04011440ull;
+
+static const uint64_t P9N2_PHB_3_NFIR_REG_AND = 0x04011441ull;
+
+static const uint64_t P9N2_PHB_3_NFIR_REG_OR = 0x04011442ull;
+
+static const uint64_t P9N2_PHB_4_NFIR_REG = 0x04011480ull;
+
+static const uint64_t P9N2_PHB_4_NFIR_REG_AND = 0x04011481ull;
+
+static const uint64_t P9N2_PHB_4_NFIR_REG_OR = 0x04011482ull;
+
+static const uint64_t P9N2_PHB_5_NFIR_REG = 0x040114C0ull;
+
+static const uint64_t P9N2_PHB_5_NFIR_REG_AND = 0x040114C1ull;
+
+static const uint64_t P9N2_PHB_5_NFIR_REG_OR = 0x040114C2ull;
+
+
+static const uint64_t P9N2_PU_NOTRUST_BAR0 = 0x05012B40ull;
+
+
+static const uint64_t P9N2_PU_NOTRUST_BAR0MASK = 0x05012B42ull;
+
+
+static const uint64_t P9N2_PU_NOTRUST_BAR1 = 0x05012B41ull;
+
+
+static const uint64_t P9N2_PU_NOTRUST_BAR1MASK = 0x05012B43ull;
+
+
+static const uint64_t P9N2__SM0_NPU_ATS_DEBUG = 0x05011603ull;
+
+
+static const uint64_t P9N2__SM0_NPU_AT_ECC = 0x05011602ull;
+
+
+static const uint64_t P9N2__SM1_NPU_AT_ESMR = 0x05011628ull;
+
+
+static const uint64_t P9N2__SM1_NPU_AT_ESR = 0x05011627ull;
+
+
+static const uint64_t P9N2__SM1_NPU_AT_FESMR = 0x0501162Aull;
+
+
+static const uint64_t P9N2__SM1_NPU_AT_FESR = 0x05011629ull;
+
+
+static const uint64_t P9N2__SM0_NPU_AT_PMU_CNT = 0x05011601ull;
+
+
+static const uint64_t P9N2__SM0_NPU_AT_PMU_CTRL = 0x05011600ull;
+
+
+static const uint64_t P9N2__SM1_NPU_Q_DMA_R = 0x05011625ull;
+
+
+static const uint64_t P9N2__CTL_NPU_VERSION = 0x05011690ull;
+
+
+static const uint64_t P9N2_PEC_NRDSTKOVR_REG = 0x04010C08ull;
+
+static const uint64_t P9N2_PEC_0_NRDSTKOVR_REG = 0x04010C08ull;
+
+static const uint64_t P9N2_PEC_1_NRDSTKOVR_REG = 0x04011008ull;
+
+static const uint64_t P9N2_PEC_2_NRDSTKOVR_REG = 0x04011408ull;
+
+
+static const uint64_t P9N2_PEC_NSTQSTKOVR_REG = 0x04010C0Aull;
+
+static const uint64_t P9N2_PEC_0_NSTQSTKOVR_REG = 0x04010C0Aull;
+
+static const uint64_t P9N2_PEC_1_NSTQSTKOVR_REG = 0x0401100Aull;
+
+static const uint64_t P9N2_PEC_2_NSTQSTKOVR_REG = 0x0401140Aull;
+
+
+static const uint64_t P9N2_PEC_NWRSTKOVR_REG = 0x04010C09ull;
+
+static const uint64_t P9N2_PEC_0_NWRSTKOVR_REG = 0x04010C09ull;
+
+static const uint64_t P9N2_PEC_1_NWRSTKOVR_REG = 0x04011009ull;
+
+static const uint64_t P9N2_PEC_2_NWRSTKOVR_REG = 0x04011409ull;
+
+
+static const uint64_t P9N2_PU_NXCQ_PB_MODE_REG = 0x02011095ull;
+
+
+static const uint64_t P9N2_PU_NX_CQ_FIR_ACTION0_REG = 0x02011086ull;
+
+static const uint64_t P9N2_PU_NMMU_NX_CQ_FIR_ACTION0_REG = 0x05012C06ull;
+
+
+static const uint64_t P9N2_PU_NX_CQ_FIR_ACTION1_REG = 0x02011087ull;
+
+static const uint64_t P9N2_PU_NMMU_NX_CQ_FIR_ACTION1_REG = 0x05012C07ull;
+
+
+static const uint64_t P9N2_PU_NX_CQ_FIR_MASK_REG = 0x02011083ull;
+
+static const uint64_t P9N2_PU_NX_CQ_FIR_MASK_REG_AND = 0x02011084ull;
+
+static const uint64_t P9N2_PU_NX_CQ_FIR_MASK_REG_OR = 0x02011085ull;
+
+static const uint64_t P9N2_PU_NMMU_NX_CQ_FIR_MASK_REG = 0x05012C03ull;
+
+static const uint64_t P9N2_PU_NMMU_NX_CQ_FIR_MASK_REG_AND = 0x05012C04ull;
+
+static const uint64_t P9N2_PU_NMMU_NX_CQ_FIR_MASK_REG_OR = 0x05012C05ull;
+
+
+static const uint64_t P9N2_PU_NX_CQ_FIR_REG = 0x02011080ull;
+
+static const uint64_t P9N2_PU_NX_CQ_FIR_REG_AND = 0x02011081ull;
+
+static const uint64_t P9N2_PU_NX_CQ_FIR_REG_OR = 0x02011082ull;
+
+static const uint64_t P9N2_PU_NMMU_NX_CQ_FIR_REG = 0x05012C00ull;
+
+static const uint64_t P9N2_PU_NMMU_NX_CQ_FIR_REG_AND = 0x05012C01ull;
+
+static const uint64_t P9N2_PU_NMMU_NX_CQ_FIR_REG_OR = 0x05012C02ull;
+
+
+static const uint64_t P9N2_PU_NX_CQ_FIR_WOF_REG = 0x02011088ull;
+
+static const uint64_t P9N2_PU_NMMU_NX_CQ_FIR_WOF_REG = 0x05012C08ull;
+
+
+static const uint64_t P9N2_PU_NX_DEBUGMUX_CTRL = 0x0201110Aull;
+
+
+static const uint64_t P9N2_PU_NX_DEBUG_SNAPSHOT_0 = 0x020110A4ull;
+
+static const uint64_t P9N2_PU_NMMU_NX_DEBUG_SNAPSHOT_0 = 0x05012C24ull;
+
+
+static const uint64_t P9N2_PU_NX_DEBUG_SNAPSHOT_1 = 0x020110A5ull;
+
+static const uint64_t P9N2_PU_NMMU_NX_DEBUG_SNAPSHOT_1 = 0x05012C25ull;
+
+
+static const uint64_t P9N2_PU_NX_DMA_ENG_FIR = 0x02011100ull;
+
+static const uint64_t P9N2_PU_NX_DMA_ENG_FIR_AND = 0x02011101ull;
+
+static const uint64_t P9N2_PU_NX_DMA_ENG_FIR_OR = 0x02011102ull;
+
+
+static const uint64_t P9N2_PU_NX_DMA_ENG_FIR_ACTION0 = 0x02011106ull;
+
+
+static const uint64_t P9N2_PU_NX_DMA_ENG_FIR_ACTION1 = 0x02011107ull;
+
+
+static const uint64_t P9N2_PU_NX_DMA_ENG_FIR_MASK = 0x02011103ull;
+
+static const uint64_t P9N2_PU_NX_DMA_ENG_FIR_MASK_AND = 0x02011104ull;
+
+static const uint64_t P9N2_PU_NX_DMA_ENG_FIR_MASK_OR = 0x02011105ull;
+
+
+static const uint64_t P9N2_PU_NX_DMA_ENG_FIR_WOF = 0x02011108ull;
+
+
+static const uint64_t P9N2_PU_NX_ERRORINJ_CTRL = 0x0201110Cull;
+
+
+static const uint64_t P9N2_PU_NX_MISC_CONTROL_REG = 0x020110A8ull;
+
+static const uint64_t P9N2_PU_NMMU_NX_MISC_CONTROL_REG = 0x05012C28ull;
+
+
+static const uint64_t P9N2_PU_NX_MMIO_BAR = 0x0201108Dull;
+
+
+static const uint64_t P9N2_PU_NX_PB_DEBUG_REG = 0x02011090ull;
+
+static const uint64_t P9N2_PU_NMMU_NX_PB_DEBUG_REG = 0x05012C10ull;
+
+
+static const uint64_t P9N2_PU_NX_PB_ECC_REG = 0x02011091ull;
+
+static const uint64_t P9N2_PU_NMMU_NX_PB_ECC_REG = 0x05012C11ull;
+
+
+static const uint64_t P9N2_PU_NX_PB_ERR_RPT_0 = 0x020110A2ull;
+
+static const uint64_t P9N2_PU_NMMU_NX_PB_ERR_RPT_0 = 0x05012C22ull;
+
+
+static const uint64_t P9N2_PU_NX_PB_ERR_RPT_1 = 0x020110A1ull;
+
+
+static const uint64_t P9N2_PU_NX_PMU0_CONTROL_REG = 0x020110A6ull;
+
+
+static const uint64_t P9N2_PU_NX_PMU0_COUNTER_REG = 0x020110A7ull;
+
+
+static const uint64_t P9N2_PU_NX_PMU1_CONTROL_REG = 0x020110A9ull;
+
+
+static const uint64_t P9N2_PU_NX_PMU1_COUNTER_REG = 0x020110AAull;
+
+
+static const uint64_t P9N2_PU_NMMU_NX_PMU_CONTROL_REG = 0x05012C26ull;
+
+
+static const uint64_t P9N2_PU_NMMU_NX_PMU_COUNTER_REG = 0x05012C27ull;
+
+
+static const uint64_t P9N2_PU_NX_RNG_BYPASS = 0x020110E4ull;
+
+
+static const uint64_t P9N2_PU_NX_RNG_CFG = 0x020110E0ull;
+
+
+static const uint64_t P9N2_PU_NX_RNG_RDELAY = 0x020110E5ull;
+
+
+static const uint64_t P9N2_PU_NX_RNG_RESET = 0x020110E6ull;
+
+
+static const uint64_t P9N2_PU_NX_RNG_ST0 = 0x020110E1ull;
+
+
+static const uint64_t P9N2_PU_NX_RNG_ST1 = 0x020110E2ull;
+
+
+static const uint64_t P9N2_PU_NX_RNG_ST2 = 0x020110E3ull;
+
+
+static const uint64_t P9N2_PU_NX_RNG_ST3 = 0x020110E8ull;
+
+
+static const uint64_t P9N2_PU_NX_TRIGGER_CTRL = 0x0201110Bull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_CCSR_OCI = 0xC0060480ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_CCSR_OCI1 = 0xC0060488ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_CCSR_OCI2 = 0xC0060490ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_CCSR_SCOM = 0x0006C090ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_CCSR_SCOM1 = 0x0006C091ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_CCSR_SCOM2 = 0x0006C092ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_DERP_OCI = 0xC0060C00ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_DERP_SCOM = 0x0006C180ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_DORP_OCI = 0xC0060C08ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_DORP_SCOM = 0x0006C181ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_G0ISR0_OCI = 0xC0060320ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_G0ISR0_SCOM = 0x0006C064ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_G0ISR1_OCI = 0xC00603A0ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_G0ISR1_SCOM = 0x0006C074ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_G1ISR0_OCI = 0xC0060328ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_G1ISR0_SCOM = 0x0006C065ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_G1ISR1_OCI = 0xC00603A8ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_G1ISR1_SCOM = 0x0006C075ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_G2ISR0_OCI = 0xC0060330ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_G2ISR0_SCOM = 0x0006C066ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_G2ISR1_OCI = 0xC00603B0ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_G2ISR1_SCOM = 0x0006C076ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_G3ISR0_OCI = 0xC0060338ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_G3ISR0_SCOM = 0x0006C067ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_G3ISR1_OCI = 0xC00603B8ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_G3ISR1_SCOM = 0x0006C077ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_O2SCMD0A_OCI = 0xC0063838ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_O2SCMD0A_SCOM = 0x0006C707ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_O2SCMD0B_OCI = 0xC00638B8ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_O2SCMD0B_SCOM = 0x0006C717ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_O2SCMD1A_OCI = 0xC0063938ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_O2SCMD1A_SCOM = 0x0006C727ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_O2SCMD1B_OCI = 0xC00639B8ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_O2SCMD1B_SCOM = 0x0006C737ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_O2SCTRL10A_OCI = 0xC0063810ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_O2SCTRL10A_SCOM = 0x0006C702ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_O2SCTRL10B_OCI = 0xC0063890ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_O2SCTRL10B_SCOM = 0x0006C712ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_O2SCTRL11A_OCI = 0xC0063910ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_O2SCTRL11A_SCOM = 0x0006C722ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_O2SCTRL11B_OCI = 0xC0063990ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_O2SCTRL11B_SCOM = 0x0006C732ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_O2SCTRL20A_OCI = 0xC0063818ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_O2SCTRL20A_SCOM = 0x0006C703ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_O2SCTRL20B_OCI = 0xC0063898ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_O2SCTRL20B_SCOM = 0x0006C713ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_O2SCTRL21A_OCI = 0xC0063918ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_O2SCTRL21A_SCOM = 0x0006C723ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_O2SCTRL21B_OCI = 0xC0063998ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_O2SCTRL21B_SCOM = 0x0006C733ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_O2SCTRLF0A_OCI = 0xC0063800ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_O2SCTRLF0A_SCOM = 0x0006C700ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_O2SCTRLF0B_OCI = 0xC0063880ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_O2SCTRLF0B_SCOM = 0x0006C710ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_O2SCTRLF1A_OCI = 0xC0063900ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_O2SCTRLF1A_SCOM = 0x0006C720ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_O2SCTRLF1B_OCI = 0xC0063980ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_O2SCTRLF1B_SCOM = 0x0006C730ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_O2SCTRLS0A_OCI = 0xC0063808ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_O2SCTRLS0A_SCOM = 0x0006C701ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_O2SCTRLS0B_OCI = 0xC0063888ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_O2SCTRLS0B_SCOM = 0x0006C711ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_O2SCTRLS1A_OCI = 0xC0063908ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_O2SCTRLS1A_SCOM = 0x0006C721ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_O2SCTRLS1B_OCI = 0xC0063988ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_O2SCTRLS1B_SCOM = 0x0006C731ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_O2SRD0A_OCI = 0xC0063848ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_O2SRD0A_SCOM = 0x0006C709ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_O2SRD0B_OCI = 0xC00638C8ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_O2SRD0B_SCOM = 0x0006C719ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_O2SRD1A_OCI = 0xC0063948ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_O2SRD1A_SCOM = 0x0006C729ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_O2SRD1B_OCI = 0xC00639C8ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_O2SRD1B_SCOM = 0x0006C739ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_O2SST0A_OCI = 0xC0063830ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_O2SST0A_SCOM = 0x0006C706ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_O2SST0B_OCI = 0xC00638B0ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_O2SST0B_SCOM = 0x0006C716ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_O2SST1A_OCI = 0xC0063930ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_O2SST1A_SCOM = 0x0006C726ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_O2SST1B_OCI = 0xC00639B0ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_O2SST1B_SCOM = 0x0006C736ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_O2SWD0A_OCI = 0xC0063840ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_O2SWD0A_SCOM = 0x0006C708ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_O2SWD0B_OCI = 0xC00638C0ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_O2SWD0B_SCOM = 0x0006C718ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_O2SWD1A_OCI = 0xC0063940ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_O2SWD1A_SCOM = 0x0006C728ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_O2SWD1B_OCI = 0xC00639C0ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_O2SWD1B_SCOM = 0x0006C738ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBLWCR0_OCI = 0xC0061040ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBLWCR0_SCOM = 0x0006C208ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBLWCR1_OCI = 0xC00610C0ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBLWCR1_SCOM = 0x0006C218ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBLWCR2_OCI = 0xC0061140ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBLWCR2_SCOM = 0x0006C228ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBLWCR3_OCI = 0xC00611C0ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBLWCR3_SCOM = 0x0006C238ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBLWSBR0_OCI = 0xC0061060ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBLWSBR0_SCOM = 0x0006C20Cull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBLWSBR1_OCI = 0xC00610E0ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBLWSBR1_SCOM = 0x0006C21Cull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBLWSBR2_OCI = 0xC0061160ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBLWSBR2_SCOM = 0x0006C22Cull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBLWSBR3_OCI = 0xC00611E0ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBLWSBR3_SCOM = 0x0006C23Cull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBLWSR0_OCI = 0xC0061050ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBLWSR0_SCOM = 0x0006C20Aull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBLWSR1_OCI = 0xC00610D0ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBLWSR1_SCOM = 0x0006C21Aull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBLWSR2_OCI = 0xC0061150ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBLWSR2_SCOM = 0x0006C22Aull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBLWSR3_OCI = 0xC00611D0ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBLWSR3_SCOM = 0x0006C23Aull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBSES0_OCI = 0xC0061030ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBSES0_SCOM = 0x0006C206ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBSES1_OCI = 0xC00610B0ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBSES1_SCOM = 0x0006C216ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBSES2_OCI = 0xC0061130ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBSES2_SCOM = 0x0006C226ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBSES3_OCI = 0xC00611B0ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBSES3_SCOM = 0x0006C236ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBSHBR0_OCI = 0xC0061018ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBSHBR0_SCOM = 0x0006C203ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBSHBR1_OCI = 0xC0061098ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBSHBR1_SCOM = 0x0006C213ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBSHBR2_OCI = 0xC0061118ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBSHBR2_SCOM = 0x0006C223ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBSHBR3_OCI = 0xC0061198ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBSHBR3_SCOM = 0x0006C233ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBSHCS0_OCI = 0xC0061020ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBSHCS0_SCOM = 0x0006C204ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBSHCS1_OCI = 0xC00610A0ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBSHCS1_SCOM = 0x0006C214ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBSHCS2_OCI = 0xC0061120ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBSHCS2_SCOM = 0x0006C224ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBSHCS3_OCI = 0xC00611A0ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBSHCS3_SCOM = 0x0006C234ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBSHI0_OCI = 0xC0061028ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBSHI0_SCOM = 0x0006C205ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBSHI1_OCI = 0xC00610A8ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBSHI1_SCOM = 0x0006C215ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBSHI2_OCI = 0xC0061128ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBSHI2_SCOM = 0x0006C225ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBSHI3_OCI = 0xC00611A8ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBSHI3_SCOM = 0x0006C235ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBSLBR0_OCI = 0xC0061000ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBSLBR0_SCOM = 0x0006C200ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBSLBR1_OCI = 0xC0061080ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBSLBR1_SCOM = 0x0006C210ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBSLBR2_OCI = 0xC0061100ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBSLBR2_SCOM = 0x0006C220ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBSLBR3_OCI = 0xC0061180ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBSLBR3_SCOM = 0x0006C230ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBSLCS0_OCI = 0xC0061008ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBSLCS0_SCOM = 0x0006C201ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBSLCS1_OCI = 0xC0061088ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBSLCS1_SCOM = 0x0006C211ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBSLCS2_OCI = 0xC0061108ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBSLCS2_SCOM = 0x0006C221ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBSLCS3_OCI = 0xC0061188ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBSLCS3_SCOM = 0x0006C231ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBSLI0_OCI = 0xC0061010ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBSLI0_SCOM = 0x0006C202ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBSLI1_OCI = 0xC0061090ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBSLI1_SCOM = 0x0006C212ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBSLI2_OCI = 0xC0061110ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBSLI2_SCOM = 0x0006C222ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBSLI3_OCI = 0xC0061190ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OCBSLI3_SCOM = 0x0006C232ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OCCFLG_OCI = 0xC0060450ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OCCFLG_OCI1 = 0xC0060458ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OCCFLG_OCI2 = 0xC0060460ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OCCFLG_SCOM = 0x0006C08Aull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OCCFLG_SCOM1 = 0x0006C08Bull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OCCFLG_SCOM2 = 0x0006C08Cull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OCCFLG2_OCI = 0xC0060C50ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OCCFLG2_OCI1 = 0xC0060C58ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OCCFLG2_OCI2 = 0xC0060C60ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OCCFLG2_SCOM = 0x0006C18Aull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OCCFLG2_SCOM1 = 0x0006C18Bull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OCCFLG2_SCOM2 = 0x0006C18Cull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OCCHBR_OCI = 0xC0060478ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OCCHBR_SCOM = 0x0006C08Full;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OCCMISC_OCI = 0xC0060400ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OCCMISC_OCI1 = 0xC0060408ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OCCMISC_OCI2 = 0xC0060410ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OCCMISC_SCOM = 0x0006C080ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OCCMISC_SCOM1 = 0x0006C081ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OCCMISC_SCOM2 = 0x0006C082ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OCCS0_OCI = 0xC0060430ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OCCS0_SCOM = 0x0006C086ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OCCS1_OCI = 0xC0060438ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OCCS1_SCOM = 0x0006C087ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OCCS2_OCI = 0xC0060440ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OCCS2_SCOM = 0x0006C088ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OCICFG_OCI = 0xC0060428ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OCICFG_SCOM = 0x0006C085ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OCISR0_OCI = 0xC0060308ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OCISR0_SCOM = 0x0006C061ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OCISR1_OCI = 0xC0060388ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OCISR1_SCOM = 0x0006C071ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_ODISR0_OCI = 0xC0060318ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_ODISR0_SCOM = 0x0006C063ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_ODISR1_OCI = 0xC0060398ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_ODISR1_SCOM = 0x0006C073ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OEHDR_OCI = 0xC0060420ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OEHDR_SCOM = 0x0006C084ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OHTMCR_OCI = 0xC0060418ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OHTMCR_SCOM = 0x0006C083ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OIEPR0_OCI = 0xC0060060ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OIEPR0_OCI1 = 0xC0060068ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OIEPR0_OCI2 = 0xC0060070ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OIEPR0_SCOM = 0x0006C00Cull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OIEPR0_SCOM1 = 0x0006C00Dull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OIEPR0_SCOM2 = 0x0006C00Eull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OIEPR1_OCI = 0xC0060160ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OIEPR1_OCI1 = 0xC0060168ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OIEPR1_OCI2 = 0xC0060170ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OIEPR1_SCOM = 0x0006C02Cull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OIEPR1_SCOM1 = 0x0006C02Dull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OIEPR1_SCOM2 = 0x0006C02Eull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OIMR0_OCI = 0xC0060020ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OIMR0_OCI1 = 0xC0060028ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OIMR0_OCI2 = 0xC0060030ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OIMR0_SCOM = 0x0006C004ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OIMR0_SCOM1 = 0x0006C005ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OIMR0_SCOM2 = 0x0006C006ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OIMR1_OCI = 0xC0060120ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OIMR1_OCI1 = 0xC0060128ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OIMR1_OCI2 = 0xC0060130ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OIMR1_SCOM = 0x0006C024ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OIMR1_SCOM1 = 0x0006C025ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OIMR1_SCOM2 = 0x0006C026ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OIRR0A_OCI = 0xC0060200ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OIRR0A_OCI1 = 0xC0060208ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OIRR0A_OCI2 = 0xC0060210ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OIRR0A_SCOM = 0x0006C040ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OIRR0A_SCOM1 = 0x0006C041ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OIRR0A_SCOM2 = 0x0006C042ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OIRR0B_OCI = 0xC0060220ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OIRR0B_OCI1 = 0xC0060228ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OIRR0B_OCI2 = 0xC0060230ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OIRR0B_SCOM = 0x0006C044ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OIRR0B_SCOM1 = 0x0006C045ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OIRR0B_SCOM2 = 0x0006C046ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OIRR0C_OCI = 0xC0060240ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OIRR0C_OCI1 = 0xC0060248ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OIRR0C_OCI2 = 0xC0060250ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OIRR0C_SCOM = 0x0006C048ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OIRR0C_SCOM1 = 0x0006C049ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OIRR0C_SCOM2 = 0x0006C04Aull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OIRR1A_OCI = 0xC0060280ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OIRR1A_OCI1 = 0xC0060288ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OIRR1A_OCI2 = 0xC0060290ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OIRR1A_SCOM = 0x0006C050ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OIRR1A_SCOM1 = 0x0006C051ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OIRR1A_SCOM2 = 0x0006C052ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OIRR1B_OCI = 0xC00602A0ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OIRR1B_OCI1 = 0xC00602A8ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OIRR1B_OCI2 = 0xC00602B0ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OIRR1B_SCOM = 0x0006C054ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OIRR1B_SCOM1 = 0x0006C055ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OIRR1B_SCOM2 = 0x0006C056ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OIRR1C_OCI = 0xC00602C0ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OIRR1C_OCI1 = 0xC00602C8ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OIRR1C_OCI2 = 0xC00602D0ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OIRR1C_SCOM = 0x0006C058ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OIRR1C_SCOM1 = 0x0006C059ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OIRR1C_SCOM2 = 0x0006C05Aull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OISR0_OCI = 0xC0060000ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OISR0_OCI1 = 0xC0060008ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OISR0_OCI2 = 0xC0060010ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OISR0_SCOM = 0x0006C000ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OISR0_SCOM1 = 0x0006C001ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OISR0_SCOM2 = 0x0006C002ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OISR1_OCI = 0xC0060100ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OISR1_OCI1 = 0xC0060108ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OISR1_OCI2 = 0xC0060110ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OISR1_SCOM = 0x0006C020ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OISR1_SCOM1 = 0x0006C021ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OISR1_SCOM2 = 0x0006C022ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OITR0_OCI = 0xC0060040ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OITR0_OCI1 = 0xC0060048ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OITR0_OCI2 = 0xC0060050ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OITR0_SCOM = 0x0006C008ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OITR0_SCOM1 = 0x0006C009ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OITR0_SCOM2 = 0x0006C00Aull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OITR1_OCI = 0xC0060140ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OITR1_OCI1 = 0xC0060148ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OITR1_OCI2 = 0xC0060150ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OITR1_SCOM = 0x0006C028ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OITR1_SCOM1 = 0x0006C029ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OITR1_SCOM2 = 0x0006C02Aull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_ONISR0_OCI = 0xC0060300ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_ONISR0_SCOM = 0x0006C060ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_ONISR1_OCI = 0xC0060380ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_ONISR1_SCOM = 0x0006C070ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C0_OCI = 0xC0062000ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C0_OCI1 = 0xC0062800ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C0_SCOM = 0x0006C400ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C0_SCOM1 = 0x0006C500ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C1_OCI = 0xC0062008ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C1_OCI1 = 0xC0062808ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C1_SCOM = 0x0006C401ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C1_SCOM1 = 0x0006C501ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C10_OCI = 0xC0062050ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C10_OCI1 = 0xC0062850ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C10_SCOM = 0x0006C40Aull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C10_SCOM1 = 0x0006C50Aull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C11_OCI = 0xC0062058ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C11_OCI1 = 0xC0062858ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C11_SCOM = 0x0006C40Bull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C11_SCOM1 = 0x0006C50Bull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C12_OCI = 0xC0062060ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C12_OCI1 = 0xC0062860ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C12_SCOM = 0x0006C40Cull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C12_SCOM1 = 0x0006C50Cull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C13_OCI = 0xC0062068ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C13_OCI1 = 0xC0062868ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C13_SCOM = 0x0006C40Dull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C13_SCOM1 = 0x0006C50Dull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C14_OCI = 0xC0062070ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C14_OCI1 = 0xC0062870ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C14_SCOM = 0x0006C40Eull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C14_SCOM1 = 0x0006C50Eull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C15_OCI = 0xC0062078ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C15_OCI1 = 0xC0062878ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C15_SCOM = 0x0006C40Full;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C15_SCOM1 = 0x0006C50Full;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C16_OCI = 0xC0062080ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C16_OCI1 = 0xC0062880ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C16_SCOM = 0x0006C410ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C16_SCOM1 = 0x0006C510ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C17_OCI = 0xC0062088ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C17_OCI1 = 0xC0062888ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C17_SCOM = 0x0006C411ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C17_SCOM1 = 0x0006C511ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C18_OCI = 0xC0062090ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C18_OCI1 = 0xC0062890ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C18_SCOM = 0x0006C412ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C18_SCOM1 = 0x0006C512ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C19_OCI = 0xC0062098ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C19_OCI1 = 0xC0062898ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C19_SCOM = 0x0006C413ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C19_SCOM1 = 0x0006C513ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C2_OCI = 0xC0062010ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C2_OCI1 = 0xC0062810ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C2_SCOM = 0x0006C402ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C2_SCOM1 = 0x0006C502ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C20_OCI = 0xC00620A0ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C20_OCI1 = 0xC00628A0ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C20_SCOM = 0x0006C414ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C20_SCOM1 = 0x0006C514ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C21_OCI = 0xC00620A8ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C21_OCI1 = 0xC00628A8ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C21_SCOM = 0x0006C415ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C21_SCOM1 = 0x0006C515ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C22_OCI = 0xC00620B0ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C22_OCI1 = 0xC00628B0ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C22_SCOM = 0x0006C416ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C22_SCOM1 = 0x0006C516ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C23_OCI = 0xC00620B8ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C23_OCI1 = 0xC00628B8ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C23_SCOM = 0x0006C417ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C23_SCOM1 = 0x0006C517ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C3_OCI = 0xC0062018ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C3_OCI1 = 0xC0062818ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C3_SCOM = 0x0006C403ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C3_SCOM1 = 0x0006C503ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C4_OCI = 0xC0062020ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C4_OCI1 = 0xC0062820ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C4_SCOM = 0x0006C404ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C4_SCOM1 = 0x0006C504ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C5_OCI = 0xC0062028ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C5_OCI1 = 0xC0062828ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C5_SCOM = 0x0006C405ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C5_SCOM1 = 0x0006C505ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C6_OCI = 0xC0062030ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C6_OCI1 = 0xC0062830ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C6_SCOM = 0x0006C406ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C6_SCOM1 = 0x0006C506ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C7_OCI = 0xC0062038ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C7_OCI1 = 0xC0062838ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C7_SCOM = 0x0006C407ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C7_SCOM1 = 0x0006C507ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C8_OCI = 0xC0062040ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C8_OCI1 = 0xC0062840ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C8_SCOM = 0x0006C408ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C8_SCOM1 = 0x0006C508ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C9_OCI = 0xC0062048ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C9_OCI1 = 0xC0062848ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C9_SCOM = 0x0006C409ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0C9_SCOM1 = 0x0006C509ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0PRA_OCI = 0xC0063000ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0PRA_OCI1 = 0xC0063008ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0PRA_SCOM = 0x0006C600ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT0PRA_SCOM1 = 0x0006C601ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C0_OCI = 0xC0062100ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C0_OCI1 = 0xC0062900ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C0_SCOM = 0x0006C420ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C0_SCOM1 = 0x0006C520ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C1_OCI = 0xC0062108ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C1_OCI1 = 0xC0062908ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C1_SCOM = 0x0006C421ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C1_SCOM1 = 0x0006C521ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C10_OCI = 0xC0062150ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C10_OCI1 = 0xC0062950ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C10_SCOM = 0x0006C42Aull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C10_SCOM1 = 0x0006C52Aull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C11_OCI = 0xC0062158ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C11_OCI1 = 0xC0062958ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C11_SCOM = 0x0006C42Bull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C11_SCOM1 = 0x0006C52Bull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C12_OCI = 0xC0062160ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C12_OCI1 = 0xC0062960ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C12_SCOM = 0x0006C42Cull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C12_SCOM1 = 0x0006C52Cull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C13_OCI = 0xC0062168ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C13_OCI1 = 0xC0062968ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C13_SCOM = 0x0006C42Dull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C13_SCOM1 = 0x0006C52Dull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C14_OCI = 0xC0062170ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C14_OCI1 = 0xC0062970ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C14_SCOM = 0x0006C42Eull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C14_SCOM1 = 0x0006C52Eull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C15_OCI = 0xC0062178ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C15_OCI1 = 0xC0062978ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C15_SCOM = 0x0006C42Full;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C15_SCOM1 = 0x0006C52Full;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C16_OCI = 0xC0062180ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C16_OCI1 = 0xC0062980ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C16_SCOM = 0x0006C430ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C16_SCOM1 = 0x0006C530ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C17_OCI = 0xC0062188ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C17_OCI1 = 0xC0062988ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C17_SCOM = 0x0006C431ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C17_SCOM1 = 0x0006C531ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C18_OCI = 0xC0062190ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C18_OCI1 = 0xC0062990ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C18_SCOM = 0x0006C432ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C18_SCOM1 = 0x0006C532ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C19_OCI = 0xC0062198ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C19_OCI1 = 0xC0062998ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C19_SCOM = 0x0006C433ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C19_SCOM1 = 0x0006C533ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C2_OCI = 0xC0062110ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C2_OCI1 = 0xC0062910ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C2_SCOM = 0x0006C422ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C2_SCOM1 = 0x0006C522ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C20_OCI = 0xC00621A0ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C20_OCI1 = 0xC00629A0ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C20_SCOM = 0x0006C434ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C20_SCOM1 = 0x0006C534ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C21_OCI = 0xC00621A8ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C21_OCI1 = 0xC00629A8ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C21_SCOM = 0x0006C435ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C21_SCOM1 = 0x0006C535ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C22_OCI = 0xC00621B0ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C22_OCI1 = 0xC00629B0ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C22_SCOM = 0x0006C436ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C22_SCOM1 = 0x0006C536ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C23_OCI = 0xC00621B8ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C23_OCI1 = 0xC00629B8ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C23_SCOM = 0x0006C437ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C23_SCOM1 = 0x0006C537ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C3_OCI = 0xC0062118ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C3_OCI1 = 0xC0062918ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C3_SCOM = 0x0006C423ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C3_SCOM1 = 0x0006C523ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C4_OCI = 0xC0062120ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C4_OCI1 = 0xC0062920ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C4_SCOM = 0x0006C424ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C4_SCOM1 = 0x0006C524ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C5_OCI = 0xC0062128ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C5_OCI1 = 0xC0062928ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C5_SCOM = 0x0006C425ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C5_SCOM1 = 0x0006C525ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C6_OCI = 0xC0062130ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C6_OCI1 = 0xC0062930ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C6_SCOM = 0x0006C426ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C6_SCOM1 = 0x0006C526ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C7_OCI = 0xC0062138ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C7_OCI1 = 0xC0062938ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C7_SCOM = 0x0006C427ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C7_SCOM1 = 0x0006C527ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C8_OCI = 0xC0062140ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C8_OCI1 = 0xC0062940ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C8_SCOM = 0x0006C428ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C8_SCOM1 = 0x0006C528ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C9_OCI = 0xC0062148ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C9_OCI1 = 0xC0062948ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C9_SCOM = 0x0006C429ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1C9_SCOM1 = 0x0006C529ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1PRA_OCI = 0xC0063100ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1PRA_OCI1 = 0xC0063108ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1PRA_SCOM = 0x0006C620ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT1PRA_SCOM1 = 0x0006C621ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C0_OCI = 0xC0062200ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C0_OCI1 = 0xC0062A00ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C0_SCOM = 0x0006C440ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C0_SCOM1 = 0x0006C540ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C1_OCI = 0xC0062208ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C1_OCI1 = 0xC0062A08ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C1_SCOM = 0x0006C441ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C1_SCOM1 = 0x0006C541ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C10_OCI = 0xC0062250ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C10_OCI1 = 0xC0062A50ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C10_SCOM = 0x0006C44Aull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C10_SCOM1 = 0x0006C54Aull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C11_OCI = 0xC0062258ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C11_OCI1 = 0xC0062A58ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C11_SCOM = 0x0006C44Bull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C11_SCOM1 = 0x0006C54Bull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C12_OCI = 0xC0062260ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C12_OCI1 = 0xC0062A60ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C12_SCOM = 0x0006C44Cull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C12_SCOM1 = 0x0006C54Cull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C13_OCI = 0xC0062268ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C13_OCI1 = 0xC0062A68ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C13_SCOM = 0x0006C44Dull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C13_SCOM1 = 0x0006C54Dull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C14_OCI = 0xC0062270ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C14_OCI1 = 0xC0062A70ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C14_SCOM = 0x0006C44Eull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C14_SCOM1 = 0x0006C54Eull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C15_OCI = 0xC0062278ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C15_OCI1 = 0xC0062A78ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C15_SCOM = 0x0006C44Full;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C15_SCOM1 = 0x0006C54Full;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C16_OCI = 0xC0062280ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C16_OCI1 = 0xC0062A80ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C16_SCOM = 0x0006C450ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C16_SCOM1 = 0x0006C550ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C17_OCI = 0xC0062288ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C17_OCI1 = 0xC0062A88ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C17_SCOM = 0x0006C451ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C17_SCOM1 = 0x0006C551ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C18_OCI = 0xC0062290ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C18_OCI1 = 0xC0062A90ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C18_SCOM = 0x0006C452ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C18_SCOM1 = 0x0006C552ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C19_OCI = 0xC0062298ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C19_OCI1 = 0xC0062A98ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C19_SCOM = 0x0006C453ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C19_SCOM1 = 0x0006C553ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C2_OCI = 0xC0062210ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C2_OCI1 = 0xC0062A10ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C2_SCOM = 0x0006C442ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C2_SCOM1 = 0x0006C542ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C20_OCI = 0xC00622A0ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C20_OCI1 = 0xC0062AA0ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C20_SCOM = 0x0006C454ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C20_SCOM1 = 0x0006C554ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C21_OCI = 0xC00622A8ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C21_OCI1 = 0xC0062AA8ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C21_SCOM = 0x0006C455ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C21_SCOM1 = 0x0006C555ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C22_OCI = 0xC00622B0ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C22_OCI1 = 0xC0062AB0ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C22_SCOM = 0x0006C456ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C22_SCOM1 = 0x0006C556ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C23_OCI = 0xC00622B8ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C23_OCI1 = 0xC0062AB8ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C23_SCOM = 0x0006C457ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C23_SCOM1 = 0x0006C557ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C3_OCI = 0xC0062218ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C3_OCI1 = 0xC0062A18ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C3_SCOM = 0x0006C443ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C3_SCOM1 = 0x0006C543ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C4_OCI = 0xC0062220ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C4_OCI1 = 0xC0062A20ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C4_SCOM = 0x0006C444ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C4_SCOM1 = 0x0006C544ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C5_OCI = 0xC0062228ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C5_OCI1 = 0xC0062A28ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C5_SCOM = 0x0006C445ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C5_SCOM1 = 0x0006C545ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C6_OCI = 0xC0062230ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C6_OCI1 = 0xC0062A30ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C6_SCOM = 0x0006C446ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C6_SCOM1 = 0x0006C546ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C7_OCI = 0xC0062238ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C7_OCI1 = 0xC0062A38ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C7_SCOM = 0x0006C447ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C7_SCOM1 = 0x0006C547ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C8_OCI = 0xC0062240ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C8_OCI1 = 0xC0062A40ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C8_SCOM = 0x0006C448ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C8_SCOM1 = 0x0006C548ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C9_OCI = 0xC0062248ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C9_OCI1 = 0xC0062A48ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C9_SCOM = 0x0006C449ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2C9_SCOM1 = 0x0006C549ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2PRA_OCI = 0xC0063200ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2PRA_OCI1 = 0xC0063208ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2PRA_SCOM = 0x0006C640ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT2PRA_SCOM1 = 0x0006C641ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C0_OCI = 0xC0062300ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C0_OCI1 = 0xC0062B00ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C0_SCOM = 0x0006C460ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C0_SCOM1 = 0x0006C560ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C1_OCI = 0xC0062308ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C1_OCI1 = 0xC0062B08ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C1_SCOM = 0x0006C461ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C1_SCOM1 = 0x0006C561ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C10_OCI = 0xC0062350ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C10_OCI1 = 0xC0062B50ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C10_SCOM = 0x0006C46Aull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C10_SCOM1 = 0x0006C56Aull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C11_OCI = 0xC0062358ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C11_OCI1 = 0xC0062B58ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C11_SCOM = 0x0006C46Bull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C11_SCOM1 = 0x0006C56Bull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C12_OCI = 0xC0062360ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C12_OCI1 = 0xC0062B60ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C12_SCOM = 0x0006C46Cull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C12_SCOM1 = 0x0006C56Cull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C13_OCI = 0xC0062368ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C13_OCI1 = 0xC0062B68ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C13_SCOM = 0x0006C46Dull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C13_SCOM1 = 0x0006C56Dull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C14_OCI = 0xC0062370ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C14_OCI1 = 0xC0062B70ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C14_SCOM = 0x0006C46Eull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C14_SCOM1 = 0x0006C56Eull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C15_OCI = 0xC0062378ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C15_OCI1 = 0xC0062B78ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C15_SCOM = 0x0006C46Full;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C15_SCOM1 = 0x0006C56Full;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C16_OCI = 0xC0062380ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C16_OCI1 = 0xC0062B80ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C16_SCOM = 0x0006C470ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C16_SCOM1 = 0x0006C570ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C17_OCI = 0xC0062388ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C17_OCI1 = 0xC0062B88ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C17_SCOM = 0x0006C471ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C17_SCOM1 = 0x0006C571ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C18_OCI = 0xC0062390ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C18_OCI1 = 0xC0062B90ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C18_SCOM = 0x0006C472ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C18_SCOM1 = 0x0006C572ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C19_OCI = 0xC0062398ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C19_OCI1 = 0xC0062B98ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C19_SCOM = 0x0006C473ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C19_SCOM1 = 0x0006C573ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C2_OCI = 0xC0062310ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C2_OCI1 = 0xC0062B10ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C2_SCOM = 0x0006C462ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C2_SCOM1 = 0x0006C562ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C20_OCI = 0xC00623A0ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C20_OCI1 = 0xC0062BA0ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C20_SCOM = 0x0006C474ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C20_SCOM1 = 0x0006C574ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C21_OCI = 0xC00623A8ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C21_OCI1 = 0xC0062BA8ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C21_SCOM = 0x0006C475ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C21_SCOM1 = 0x0006C575ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C22_OCI = 0xC00623B0ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C22_OCI1 = 0xC0062BB0ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C22_SCOM = 0x0006C476ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C22_SCOM1 = 0x0006C576ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C23_OCI = 0xC00623B8ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C23_OCI1 = 0xC0062BB8ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C23_SCOM = 0x0006C477ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C23_SCOM1 = 0x0006C577ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C3_OCI = 0xC0062318ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C3_OCI1 = 0xC0062B18ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C3_SCOM = 0x0006C463ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C3_SCOM1 = 0x0006C563ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C4_OCI = 0xC0062320ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C4_OCI1 = 0xC0062B20ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C4_SCOM = 0x0006C464ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C4_SCOM1 = 0x0006C564ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C5_OCI = 0xC0062328ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C5_OCI1 = 0xC0062B28ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C5_SCOM = 0x0006C465ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C5_SCOM1 = 0x0006C565ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C6_OCI = 0xC0062330ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C6_OCI1 = 0xC0062B30ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C6_SCOM = 0x0006C466ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C6_SCOM1 = 0x0006C566ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C7_OCI = 0xC0062338ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C7_OCI1 = 0xC0062B38ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C7_SCOM = 0x0006C467ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C7_SCOM1 = 0x0006C567ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C8_OCI = 0xC0062340ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C8_OCI1 = 0xC0062B40ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C8_SCOM = 0x0006C468ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C8_SCOM1 = 0x0006C568ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C9_OCI = 0xC0062348ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C9_OCI1 = 0xC0062B48ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C9_SCOM = 0x0006C469ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3C9_SCOM1 = 0x0006C569ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3PRA_OCI = 0xC0063300ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3PRA_OCI1 = 0xC0063308ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3PRA_SCOM = 0x0006C660ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT3PRA_SCOM1 = 0x0006C661ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C0_OCI = 0xC0062400ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C0_OCI1 = 0xC0062C00ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C0_SCOM = 0x0006C480ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C0_SCOM1 = 0x0006C580ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C1_OCI = 0xC0062408ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C1_OCI1 = 0xC0062C08ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C1_SCOM = 0x0006C481ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C1_SCOM1 = 0x0006C581ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C10_OCI = 0xC0062450ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C10_OCI1 = 0xC0062C50ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C10_SCOM = 0x0006C48Aull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C10_SCOM1 = 0x0006C58Aull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C11_OCI = 0xC0062458ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C11_OCI1 = 0xC0062C58ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C11_SCOM = 0x0006C48Bull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C11_SCOM1 = 0x0006C58Bull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C12_OCI = 0xC0062460ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C12_OCI1 = 0xC0062C60ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C12_SCOM = 0x0006C48Cull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C12_SCOM1 = 0x0006C58Cull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C13_OCI = 0xC0062468ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C13_OCI1 = 0xC0062C68ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C13_SCOM = 0x0006C48Dull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C13_SCOM1 = 0x0006C58Dull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C14_OCI = 0xC0062470ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C14_OCI1 = 0xC0062C70ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C14_SCOM = 0x0006C48Eull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C14_SCOM1 = 0x0006C58Eull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C15_OCI = 0xC0062478ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C15_OCI1 = 0xC0062C78ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C15_SCOM = 0x0006C48Full;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C15_SCOM1 = 0x0006C58Full;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C16_OCI = 0xC0062480ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C16_OCI1 = 0xC0062C80ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C16_SCOM = 0x0006C490ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C16_SCOM1 = 0x0006C590ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C17_OCI = 0xC0062488ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C17_OCI1 = 0xC0062C88ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C17_SCOM = 0x0006C491ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C17_SCOM1 = 0x0006C591ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C18_OCI = 0xC0062490ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C18_OCI1 = 0xC0062C90ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C18_SCOM = 0x0006C492ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C18_SCOM1 = 0x0006C592ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C19_OCI = 0xC0062498ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C19_OCI1 = 0xC0062C98ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C19_SCOM = 0x0006C493ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C19_SCOM1 = 0x0006C593ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C2_OCI = 0xC0062410ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C2_OCI1 = 0xC0062C10ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C2_SCOM = 0x0006C482ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C2_SCOM1 = 0x0006C582ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C20_OCI = 0xC00624A0ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C20_OCI1 = 0xC0062CA0ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C20_SCOM = 0x0006C494ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C20_SCOM1 = 0x0006C594ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C21_OCI = 0xC00624A8ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C21_OCI1 = 0xC0062CA8ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C21_SCOM = 0x0006C495ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C21_SCOM1 = 0x0006C595ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C22_OCI = 0xC00624B0ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C22_OCI1 = 0xC0062CB0ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C22_SCOM = 0x0006C496ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C22_SCOM1 = 0x0006C596ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C23_OCI = 0xC00624B8ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C23_OCI1 = 0xC0062CB8ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C23_SCOM = 0x0006C497ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C23_SCOM1 = 0x0006C597ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C3_OCI = 0xC0062418ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C3_OCI1 = 0xC0062C18ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C3_SCOM = 0x0006C483ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C3_SCOM1 = 0x0006C583ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C4_OCI = 0xC0062420ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C4_OCI1 = 0xC0062C20ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C4_SCOM = 0x0006C484ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C4_SCOM1 = 0x0006C584ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C5_OCI = 0xC0062428ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C5_OCI1 = 0xC0062C28ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C5_SCOM = 0x0006C485ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C5_SCOM1 = 0x0006C585ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C6_OCI = 0xC0062430ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C6_OCI1 = 0xC0062C30ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C6_SCOM = 0x0006C486ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C6_SCOM1 = 0x0006C586ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C7_OCI = 0xC0062438ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C7_OCI1 = 0xC0062C38ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C7_SCOM = 0x0006C487ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C7_SCOM1 = 0x0006C587ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C8_OCI = 0xC0062440ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C8_OCI1 = 0xC0062C40ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C8_SCOM = 0x0006C488ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C8_SCOM1 = 0x0006C588ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C9_OCI = 0xC0062448ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C9_OCI1 = 0xC0062C48ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C9_SCOM = 0x0006C489ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4C9_SCOM1 = 0x0006C589ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4PRA_OCI = 0xC0063400ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4PRA_OCI1 = 0xC0063408ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4PRA_SCOM = 0x0006C680ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT4PRA_SCOM1 = 0x0006C681ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C0_OCI = 0xC0062500ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C0_OCI1 = 0xC0062D00ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C0_SCOM = 0x0006C4A0ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C0_SCOM1 = 0x0006C5A0ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C1_OCI = 0xC0062508ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C1_OCI1 = 0xC0062D08ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C1_SCOM = 0x0006C4A1ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C1_SCOM1 = 0x0006C5A1ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C10_OCI = 0xC0062550ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C10_OCI1 = 0xC0062D50ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C10_SCOM = 0x0006C4AAull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C10_SCOM1 = 0x0006C5AAull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C11_OCI = 0xC0062558ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C11_OCI1 = 0xC0062D58ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C11_SCOM = 0x0006C4ABull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C11_SCOM1 = 0x0006C5ABull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C12_OCI = 0xC0062560ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C12_OCI1 = 0xC0062D60ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C12_SCOM = 0x0006C4ACull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C12_SCOM1 = 0x0006C5ACull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C13_OCI = 0xC0062568ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C13_OCI1 = 0xC0062D68ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C13_SCOM = 0x0006C4ADull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C13_SCOM1 = 0x0006C5ADull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C14_OCI = 0xC0062570ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C14_OCI1 = 0xC0062D70ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C14_SCOM = 0x0006C4AEull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C14_SCOM1 = 0x0006C5AEull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C15_OCI = 0xC0062578ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C15_OCI1 = 0xC0062D78ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C15_SCOM = 0x0006C4AFull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C15_SCOM1 = 0x0006C5AFull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C16_OCI = 0xC0062580ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C16_OCI1 = 0xC0062D80ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C16_SCOM = 0x0006C4B0ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C16_SCOM1 = 0x0006C5B0ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C17_OCI = 0xC0062588ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C17_OCI1 = 0xC0062D88ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C17_SCOM = 0x0006C4B1ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C17_SCOM1 = 0x0006C5B1ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C18_OCI = 0xC0062590ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C18_OCI1 = 0xC0062D90ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C18_SCOM = 0x0006C4B2ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C18_SCOM1 = 0x0006C5B2ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C19_OCI = 0xC0062598ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C19_OCI1 = 0xC0062D98ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C19_SCOM = 0x0006C4B3ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C19_SCOM1 = 0x0006C5B3ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C2_OCI = 0xC0062510ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C2_OCI1 = 0xC0062D10ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C2_SCOM = 0x0006C4A2ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C2_SCOM1 = 0x0006C5A2ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C20_OCI = 0xC00625A0ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C20_OCI1 = 0xC0062DA0ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C20_SCOM = 0x0006C4B4ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C20_SCOM1 = 0x0006C5B4ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C21_OCI = 0xC00625A8ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C21_OCI1 = 0xC0062DA8ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C21_SCOM = 0x0006C4B5ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C21_SCOM1 = 0x0006C5B5ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C22_OCI = 0xC00625B0ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C22_OCI1 = 0xC0062DB0ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C22_SCOM = 0x0006C4B6ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C22_SCOM1 = 0x0006C5B6ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C23_OCI = 0xC00625B8ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C23_OCI1 = 0xC0062DB8ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C23_SCOM = 0x0006C4B7ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C23_SCOM1 = 0x0006C5B7ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C3_OCI = 0xC0062518ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C3_OCI1 = 0xC0062D18ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C3_SCOM = 0x0006C4A3ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C3_SCOM1 = 0x0006C5A3ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C4_OCI = 0xC0062520ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C4_OCI1 = 0xC0062D20ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C4_SCOM = 0x0006C4A4ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C4_SCOM1 = 0x0006C5A4ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C5_OCI = 0xC0062528ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C5_OCI1 = 0xC0062D28ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C5_SCOM = 0x0006C4A5ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C5_SCOM1 = 0x0006C5A5ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C6_OCI = 0xC0062530ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C6_OCI1 = 0xC0062D30ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C6_SCOM = 0x0006C4A6ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C6_SCOM1 = 0x0006C5A6ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C7_OCI = 0xC0062538ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C7_OCI1 = 0xC0062D38ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C7_SCOM = 0x0006C4A7ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C7_SCOM1 = 0x0006C5A7ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C8_OCI = 0xC0062540ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C8_OCI1 = 0xC0062D40ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C8_SCOM = 0x0006C4A8ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C8_SCOM1 = 0x0006C5A8ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C9_OCI = 0xC0062548ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C9_OCI1 = 0xC0062D48ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C9_SCOM = 0x0006C4A9ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5C9_SCOM1 = 0x0006C5A9ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5PRA_OCI = 0xC0063500ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5PRA_OCI1 = 0xC0063508ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5PRA_SCOM = 0x0006C6A0ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT5PRA_SCOM1 = 0x0006C6A1ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT6PRB_OCI = 0xC0063600ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT6PRB_OCI1 = 0xC0063608ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT6PRB_SCOM = 0x0006C6C0ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT6PRB_SCOM1 = 0x0006C6C1ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT6Q0_OCI = 0xC0062600ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT6Q0_OCI1 = 0xC0062E00ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT6Q0_SCOM = 0x0006C4C0ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT6Q0_SCOM1 = 0x0006C5C0ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT6Q1_OCI = 0xC0062608ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT6Q1_OCI1 = 0xC0062E08ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT6Q1_SCOM = 0x0006C4C1ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT6Q1_SCOM1 = 0x0006C5C1ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT6Q2_OCI = 0xC0062610ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT6Q2_OCI1 = 0xC0062E10ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT6Q2_SCOM = 0x0006C4C2ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT6Q2_SCOM1 = 0x0006C5C2ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT6Q3_OCI = 0xC0062618ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT6Q3_OCI1 = 0xC0062E18ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT6Q3_SCOM = 0x0006C4C3ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT6Q3_SCOM1 = 0x0006C5C3ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT6Q4_OCI = 0xC0062620ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT6Q4_OCI1 = 0xC0062E20ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT6Q4_SCOM = 0x0006C4C4ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT6Q4_SCOM1 = 0x0006C5C4ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT6Q5_OCI = 0xC0062628ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT6Q5_OCI1 = 0xC0062E28ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT6Q5_SCOM = 0x0006C4C5ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT6Q5_SCOM1 = 0x0006C5C5ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT7PRB_OCI = 0xC0063700ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT7PRB_OCI1 = 0xC0063708ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT7PRB_SCOM = 0x0006C6E0ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT7PRB_SCOM1 = 0x0006C6E1ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT7Q0_OCI = 0xC0062700ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT7Q0_OCI1 = 0xC0062F00ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT7Q0_SCOM = 0x0006C4E0ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT7Q0_SCOM1 = 0x0006C5E0ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT7Q1_OCI = 0xC0062708ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT7Q1_OCI1 = 0xC0062F08ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT7Q1_SCOM = 0x0006C4E1ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT7Q1_SCOM1 = 0x0006C5E1ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT7Q2_OCI = 0xC0062710ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT7Q2_OCI1 = 0xC0062F10ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT7Q2_SCOM = 0x0006C4E2ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT7Q2_SCOM1 = 0x0006C5E2ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT7Q3_OCI = 0xC0062718ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT7Q3_OCI1 = 0xC0062F18ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT7Q3_SCOM = 0x0006C4E3ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT7Q3_SCOM1 = 0x0006C5E3ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT7Q4_OCI = 0xC0062720ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT7Q4_OCI1 = 0xC0062F20ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT7Q4_SCOM = 0x0006C4E4ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT7Q4_SCOM1 = 0x0006C5E4ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT7Q5_OCI = 0xC0062728ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT7Q5_OCI1 = 0xC0062F28ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT7Q5_SCOM = 0x0006C4E5ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OPIT7Q5_SCOM1 = 0x0006C5E5ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OTBR_OCI = 0xC00604F8ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OTBR_SCOM = 0x0006C09Full;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OTR0_OCI = 0xC0060800ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OTR0_SCOM = 0x0006C100ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OTR1_OCI = 0xC0060808ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OTR1_SCOM = 0x0006C101ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OUISR0_OCI = 0xC0060310ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OUISR0_SCOM = 0x0006C062ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_OUISR1_OCI = 0xC0060390ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_OUISR1_SCOM = 0x0006C072ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_QCSR_OCI = 0xC00604A0ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_QCSR_OCI1 = 0xC00604A8ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_QCSR_OCI2 = 0xC00604B0ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_QCSR_SCOM = 0x0006C094ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_QCSR_SCOM1 = 0x0006C095ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_QCSR_SCOM2 = 0x0006C096ull;
+
+
+static const uint64_t P9N2_PU_OCB_OCI_QSSR_OCI = 0xC00604C0ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_QSSR_OCI1 = 0xC00604C8ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_QSSR_OCI2 = 0xC00604D0ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_QSSR_SCOM = 0x0006C098ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_QSSR_SCOM1 = 0x0006C099ull;
+
+static const uint64_t P9N2_PU_OCB_OCI_QSSR_SCOM2 = 0x0006C09Aull;
+
+
+static const uint64_t P9N2_PU_OCB_PIB_OACR = 0x0006D207ull;
+
+
+static const uint64_t P9N2_PU_OCB_PIB_OCBAR0 = 0x0006D010ull;
+
+
+static const uint64_t P9N2_PU_OCB_PIB_OCBAR1 = 0x0006D030ull;
+
+
+static const uint64_t P9N2_PU_OCB_PIB_OCBAR2 = 0x0006D050ull;
+
+
+static const uint64_t P9N2_PU_OCB_PIB_OCBAR3 = 0x0006D070ull;
+
+
+static const uint64_t P9N2_PU_OCB_PIB_OCBCSR0_RO = 0x0006D011ull;
+
+static const uint64_t P9N2_PU_OCB_PIB_OCBCSR0_CLEAR = 0x0006D012ull;
+
+static const uint64_t P9N2_PU_OCB_PIB_OCBCSR0_OR = 0x0006D013ull;
+
+
+static const uint64_t P9N2_PU_OCB_PIB_OCBCSR1_RO = 0x0006D031ull;
+
+static const uint64_t P9N2_PU_OCB_PIB_OCBCSR1_CLEAR = 0x0006D032ull;
+
+static const uint64_t P9N2_PU_OCB_PIB_OCBCSR1_OR = 0x0006D033ull;
+
+
+static const uint64_t P9N2_PU_OCB_PIB_OCBCSR2_RO = 0x0006D051ull;
+
+static const uint64_t P9N2_PU_OCB_PIB_OCBCSR2_CLEAR = 0x0006D052ull;
+
+static const uint64_t P9N2_PU_OCB_PIB_OCBCSR2_OR = 0x0006D053ull;
+
+
+static const uint64_t P9N2_PU_OCB_PIB_OCBCSR3_RO = 0x0006D071ull;
+
+static const uint64_t P9N2_PU_OCB_PIB_OCBCSR3_CLEAR = 0x0006D072ull;
+
+static const uint64_t P9N2_PU_OCB_PIB_OCBCSR3_OR = 0x0006D073ull;
+
+
+static const uint64_t P9N2_PU_OCB_PIB_OCBDR0 = 0x0006D015ull;
+
+
+static const uint64_t P9N2_PU_OCB_PIB_OCBDR1 = 0x0006D035ull;
+
+
+static const uint64_t P9N2_PU_OCB_PIB_OCBDR2 = 0x0006D055ull;
+
+
+static const uint64_t P9N2_PU_OCB_PIB_OCBDR3 = 0x0006D075ull;
+
+
+static const uint64_t P9N2_PU_OCB_PIB_OCBEAR = 0x0006D210ull;
+
+
+static const uint64_t P9N2_PU_OCB_PIB_OCBESR0 = 0x0006D014ull;
+
+
+static const uint64_t P9N2_PU_OCB_PIB_OCBESR1 = 0x0006D034ull;
+
+
+static const uint64_t P9N2_PU_OCB_PIB_OCBESR2 = 0x0006D054ull;
+
+
+static const uint64_t P9N2_PU_OCB_PIB_OCBESR3 = 0x0006D074ull;
+
+
+static const uint64_t P9N2_PU_OCB_PIB_OCDBG = 0x0006D003ull;
+
+
+static const uint64_t P9N2_PU_OCB_PIB_OCR_RO = 0x0006D000ull;
+
+static const uint64_t P9N2_PU_OCB_PIB_OCR_CLEAR = 0x0006D001ull;
+
+static const uint64_t P9N2_PU_OCB_PIB_OCR_OR = 0x0006D002ull;
+
+
+static const uint64_t P9N2_PU_OCB_PIB_OEAR = 0x0006D206ull;
+
+
+static const uint64_t P9N2_PU_OCB_PIB_OESR = 0x0006D204ull;
+
+
+static const uint64_t P9N2_PU_OCB_PIB_OPPCINJ = 0x0006D111ull;
+
+
+static const uint64_t P9N2_PU_OCB_PIB_OREV = 0x0006D202ull;
+
+
+static const uint64_t P9N2_PU_OCB_PIB_OSTOEAR = 0x0006D200ull;
+
+
+static const uint64_t P9N2_PU_OCB_PIB_OSTOESR = 0x0006D201ull;
+
+
+static const uint64_t P9N2_PU_OCB_PIB_OTDCR = 0x0006D110ull;
+
+
+static const uint64_t P9N2_PEC_OPCG_ALIGN = 0x0D030001ull;
+
+static const uint64_t P9N2_PEC_0_OPCG_ALIGN = 0x0D030001ull;
+
+static const uint64_t P9N2_PEC_1_OPCG_ALIGN = 0x0E030001ull;
+
+static const uint64_t P9N2_PEC_2_OPCG_ALIGN = 0x0F030001ull;
+
+
+static const uint64_t P9N2_PEC_OPCG_CAPT1 = 0x0D030010ull;
+
+static const uint64_t P9N2_PEC_0_OPCG_CAPT1 = 0x0D030010ull;
+
+static const uint64_t P9N2_PEC_1_OPCG_CAPT1 = 0x0E030010ull;
+
+static const uint64_t P9N2_PEC_2_OPCG_CAPT1 = 0x0F030010ull;
+
+
+static const uint64_t P9N2_PEC_OPCG_CAPT2 = 0x0D030011ull;
+
+static const uint64_t P9N2_PEC_0_OPCG_CAPT2 = 0x0D030011ull;
+
+static const uint64_t P9N2_PEC_1_OPCG_CAPT2 = 0x0E030011ull;
+
+static const uint64_t P9N2_PEC_2_OPCG_CAPT2 = 0x0F030011ull;
+
+
+static const uint64_t P9N2_PEC_OPCG_CAPT3 = 0x0D030012ull;
+
+static const uint64_t P9N2_PEC_0_OPCG_CAPT3 = 0x0D030012ull;
+
+static const uint64_t P9N2_PEC_1_OPCG_CAPT3 = 0x0E030012ull;
+
+static const uint64_t P9N2_PEC_2_OPCG_CAPT3 = 0x0F030012ull;
+
+
+static const uint64_t P9N2_PEC_OPCG_REG0 = 0x0D030002ull;
+
+static const uint64_t P9N2_PEC_0_OPCG_REG0 = 0x0D030002ull;
+
+static const uint64_t P9N2_PEC_1_OPCG_REG0 = 0x0E030002ull;
+
+static const uint64_t P9N2_PEC_2_OPCG_REG0 = 0x0F030002ull;
+
+
+static const uint64_t P9N2_PEC_OPCG_REG1 = 0x0D030003ull;
+
+static const uint64_t P9N2_PEC_0_OPCG_REG1 = 0x0D030003ull;
+
+static const uint64_t P9N2_PEC_1_OPCG_REG1 = 0x0E030003ull;
+
+static const uint64_t P9N2_PEC_2_OPCG_REG1 = 0x0F030003ull;
+
+
+static const uint64_t P9N2_PEC_OPCG_REG2 = 0x0D030004ull;
+
+static const uint64_t P9N2_PEC_0_OPCG_REG2 = 0x0D030004ull;
+
+static const uint64_t P9N2_PEC_1_OPCG_REG2 = 0x0E030004ull;
+
+static const uint64_t P9N2_PEC_2_OPCG_REG2 = 0x0F030004ull;
+
+
+static const uint64_t P9N2__CTL_OPTICAL_IO_CONFIG = 0x05011683ull;
+
+
+static const uint64_t P9N2_PU_NPU_CTL_OTL_REM0 = 0x0501138Dull;
+
+static const uint64_t P9N2_PU_NPU_SM2_OTL_REM0 = 0x0501135Dull;
+
+static const uint64_t P9N2__CTL_OTL_REM0 = 0x0501158Dull;
+
+static const uint64_t P9N2__SM2_OTL_REM0 = 0x0501155Dull;
+
+
+static const uint64_t P9N2_NV_PA0_CONFIG = 0x050110D4ull;
+
+static const uint64_t P9N2_NV_0_PA0_CONFIG = 0x050110D4ull;
+
+static const uint64_t P9N2_NV_4_PA0_CONFIG = 0x050114D4ull;
+
+static const uint64_t P9N2_PU_NPU2_NTL0_PA0_CONFIG = 0x050112D4ull;
+
+
+static const uint64_t P9N2_NV_PA1_CONFIG = 0x050110D5ull;
+
+static const uint64_t P9N2_NV_0_PA1_CONFIG = 0x050110D5ull;
+
+static const uint64_t P9N2_NV_4_PA1_CONFIG = 0x050114D5ull;
+
+static const uint64_t P9N2_PU_NPU2_NTL0_PA1_CONFIG = 0x050112D5ull;
+
+
+static const uint64_t P9N2_PU_PBABAR0 = 0x05012B00ull;
+
+
+static const uint64_t P9N2_PU_PBABAR1 = 0x05012B01ull;
+
+
+static const uint64_t P9N2_PU_PBABAR2 = 0x05012B02ull;
+
+
+static const uint64_t P9N2_PU_PBABAR3 = 0x05012B03ull;
+
+
+static const uint64_t P9N2_PU_PBABARMSK0 = 0x05012B04ull;
+
+
+static const uint64_t P9N2_PU_PBABARMSK1 = 0x05012B05ull;
+
+
+static const uint64_t P9N2_PU_PBABARMSK2 = 0x05012B06ull;
+
+
+static const uint64_t P9N2_PU_PBABARMSK3 = 0x05012B07ull;
+
+
+static const uint64_t P9N2_PU_PBACFG = 0x0501284Bull;
+
+
+static const uint64_t P9N2_PU_PBAERRRPT0 = 0x0501284Cull;
+
+
+static const uint64_t P9N2_PU_PBAERRRPT1 = 0x0501284Dull;
+
+
+static const uint64_t P9N2_PU_PBAERRRPT2 = 0x0501284Eull;
+
+
+static const uint64_t P9N2_PU_PBAFIR = 0x05012840ull;
+
+static const uint64_t P9N2_PU_PBAFIR_AND = 0x05012841ull;
+
+static const uint64_t P9N2_PU_PBAFIR_OR = 0x05012842ull;
+
+
+static const uint64_t P9N2_PU_PBAFIRACT0 = 0x05012846ull;
+
+
+static const uint64_t P9N2_PU_PBAFIRACT1 = 0x05012847ull;
+
+
+static const uint64_t P9N2_PU_PBAFIRMASK = 0x05012843ull;
+
+static const uint64_t P9N2_PU_PBAFIRMASK_AND = 0x05012844ull;
+
+static const uint64_t P9N2_PU_PBAFIRMASK_OR = 0x05012845ull;
+
+
+static const uint64_t P9N2_PEC_PBAIBHWCFG_REG = 0x0D010800ull;
+
+static const uint64_t P9N2_PEC_0_PBAIBHWCFG_REG = 0x0D010800ull;
+
+static const uint64_t P9N2_PEC_1_PBAIBHWCFG_REG = 0x0E010800ull;
+
+static const uint64_t P9N2_PEC_2_PBAIBHWCFG_REG = 0x0F010800ull;
+
+
+static const uint64_t P9N2_PHB_PBAIBTXCCR_REG = 0x0D01084Dull;
+
+static const uint64_t P9N2_PHB_0_PBAIBTXCCR_REG = 0x0D01084Dull;
+
+static const uint64_t P9N2_PHB_1_PBAIBTXCCR_REG = 0x0E01084Dull;
+
+static const uint64_t P9N2_PHB_2_PBAIBTXCCR_REG = 0x0E01088Dull;
+
+static const uint64_t P9N2_PHB_3_PBAIBTXCCR_REG = 0x0F01084Dull;
+
+static const uint64_t P9N2_PHB_4_PBAIBTXCCR_REG = 0x0F01088Dull;
+
+static const uint64_t P9N2_PHB_5_PBAIBTXCCR_REG = 0x0F0108CDull;
+
+
+static const uint64_t P9N2_PHB_PBAIBTXDCR_REG = 0x0D01084Eull;
+
+static const uint64_t P9N2_PHB_0_PBAIBTXDCR_REG = 0x0D01084Eull;
+
+static const uint64_t P9N2_PHB_1_PBAIBTXDCR_REG = 0x0E01084Eull;
+
+static const uint64_t P9N2_PHB_2_PBAIBTXDCR_REG = 0x0E01088Eull;
+
+static const uint64_t P9N2_PHB_3_PBAIBTXDCR_REG = 0x0F01084Eull;
+
+static const uint64_t P9N2_PHB_4_PBAIBTXDCR_REG = 0x0F01088Eull;
+
+static const uint64_t P9N2_PHB_5_PBAIBTXDCR_REG = 0x0F0108CEull;
+
+
+static const uint64_t P9N2_PHB_PBAIB_CERR_RPT_REG = 0x0D01084Bull;
+
+static const uint64_t P9N2_PHB_0_PBAIB_CERR_RPT_REG = 0x0D01084Bull;
+
+static const uint64_t P9N2_PHB_1_PBAIB_CERR_RPT_REG = 0x0E01084Bull;
+
+static const uint64_t P9N2_PHB_2_PBAIB_CERR_RPT_REG = 0x0E01088Bull;
+
+static const uint64_t P9N2_PHB_3_PBAIB_CERR_RPT_REG = 0x0F01084Bull;
+
+static const uint64_t P9N2_PHB_4_PBAIB_CERR_RPT_REG = 0x0F01088Bull;
+
+static const uint64_t P9N2_PHB_5_PBAIB_CERR_RPT_REG = 0x0F0108CBull;
+
+
+static const uint64_t P9N2_PU_PBAMODE_OCI = 0xC0040000ull;
+
+static const uint64_t P9N2_PU_PBAMODE_PIB = 0x00068000ull;
+
+
+static const uint64_t P9N2_PU_PBAOCCACT = 0x0501284Aull;
+
+
+static const uint64_t P9N2_PU_PBAPBOCR0_OCI = 0xC00400D0ull;
+
+static const uint64_t P9N2_PU_PBAPBOCR0_PIB = 0x0006801Aull;
+
+
+static const uint64_t P9N2_PU_PBAPBOCR1_OCI = 0xC00400D8ull;
+
+static const uint64_t P9N2_PU_PBAPBOCR1_PIB = 0x0006801Bull;
+
+
+static const uint64_t P9N2_PU_PBAPBOCR2_OCI = 0xC00400E0ull;
+
+static const uint64_t P9N2_PU_PBAPBOCR2_PIB = 0x0006801Cull;
+
+
+static const uint64_t P9N2_PU_PBAPBOCR3_OCI = 0xC00400E8ull;
+
+static const uint64_t P9N2_PU_PBAPBOCR3_PIB = 0x0006801Dull;
+
+
+static const uint64_t P9N2_PU_PBAPBOCR4_OCI = 0xC00400F0ull;
+
+static const uint64_t P9N2_PU_PBAPBOCR4_PIB = 0x0006801Eull;
+
+
+static const uint64_t P9N2_PU_PBAPBOCR5_OCI = 0xC00400F8ull;
+
+static const uint64_t P9N2_PU_PBAPBOCR5_PIB = 0x0006801Full;
+
+
+static const uint64_t P9N2_PU_PBARBUFVAL0 = 0x05012850ull;
+
+
+static const uint64_t P9N2_PU_PBARBUFVAL1 = 0x05012851ull;
+
+
+static const uint64_t P9N2_PU_PBARBUFVAL2 = 0x05012852ull;
+
+
+static const uint64_t P9N2_PU_PBARBUFVAL3 = 0x05012853ull;
+
+
+static const uint64_t P9N2_PU_PBARBUFVAL4 = 0x05012854ull;
+
+
+static const uint64_t P9N2_PU_PBARBUFVAL5 = 0x05012855ull;
+
+
+static const uint64_t P9N2_PU_PBASLVCTL0_OCI = 0xC0040020ull;
+
+static const uint64_t P9N2_PU_PBASLVCTL0_PIB = 0x00068004ull;
+
+
+static const uint64_t P9N2_PU_PBASLVCTL1_OCI = 0xC0040028ull;
+
+static const uint64_t P9N2_PU_PBASLVCTL1_PIB = 0x00068005ull;
+
+
+static const uint64_t P9N2_PU_PBASLVCTL2_OCI = 0xC0040030ull;
+
+static const uint64_t P9N2_PU_PBASLVCTL2_PIB = 0x00068006ull;
+
+
+static const uint64_t P9N2_PU_PBASLVCTL3_OCI = 0xC0040038ull;
+
+static const uint64_t P9N2_PU_PBASLVCTL3_PIB = 0x00068007ull;
+
+
+static const uint64_t P9N2_PU_PBASLVRST_OCI = 0xC0040008ull;
+
+static const uint64_t P9N2_PU_PBASLVRST_PIB = 0x00068001ull;
+
+
+static const uint64_t P9N2_PU_PBAWBUFVAL0 = 0x05012858ull;
+
+
+static const uint64_t P9N2_PU_PBAWBUFVAL1 = 0x05012859ull;
+
+
+static const uint64_t P9N2_PU_PBAXCFG_OCI = 0xC0040108ull;
+
+static const uint64_t P9N2_PU_PBAXCFG_PIB = 0x00068021ull;
+
+
+static const uint64_t P9N2_PU_PBAXRCVSTAT_OCI = 0xC0040120ull;
+
+static const uint64_t P9N2_PU_PBAXRCVSTAT_PIB = 0x00068024ull;
+
+
+static const uint64_t P9N2_PU_PBAXSHBR0_OCI = 0xC0040130ull;
+
+static const uint64_t P9N2_PU_PBAXSHBR0_PIB = 0x00068026ull;
+
+
+static const uint64_t P9N2_PU_PBAXSHBR1_OCI = 0xC0040150ull;
+
+static const uint64_t P9N2_PU_PBAXSHBR1_PIB = 0x0006802Aull;
+
+
+static const uint64_t P9N2_PU_PBAXSHCS0_OCI = 0xC0040138ull;
+
+static const uint64_t P9N2_PU_PBAXSHCS0_PIB = 0x00068027ull;
+
+
+static const uint64_t P9N2_PU_PBAXSHCS1_OCI = 0xC0040158ull;
+
+static const uint64_t P9N2_PU_PBAXSHCS1_PIB = 0x0006802Bull;
+
+
+static const uint64_t P9N2_PU_PBAXSHINC0_OCI = 0xC0040140ull;
+
+static const uint64_t P9N2_PU_PBAXSHINC0_PIB = 0x00068028ull;
+
+
+static const uint64_t P9N2_PU_PBAXSHINC1_OCI = 0xC0040160ull;
+
+static const uint64_t P9N2_PU_PBAXSHINC1_PIB = 0x0006802Cull;
+
+
+static const uint64_t P9N2_PU_PBAXSNDSTAT_OCI = 0xC0040110ull;
+
+static const uint64_t P9N2_PU_PBAXSNDSTAT_PIB = 0x00068022ull;
+
+
+static const uint64_t P9N2_PU_PBAXSNDTX_OCI = 0xC0040100ull;
+
+static const uint64_t P9N2_PU_PBAXSNDTX_PIB = 0x00068020ull;
+
+
+static const uint64_t P9N2_PEC_PBCQEINJ_REG = 0x04010C02ull;
+
+static const uint64_t P9N2_PEC_0_PBCQEINJ_REG = 0x04010C02ull;
+
+static const uint64_t P9N2_PEC_1_PBCQEINJ_REG = 0x04011002ull;
+
+static const uint64_t P9N2_PEC_2_PBCQEINJ_REG = 0x04011402ull;
+
+
+static const uint64_t P9N2_PEC_PBCQHWCFG_REG = 0x04010C00ull;
+
+static const uint64_t P9N2_PEC_0_PBCQHWCFG_REG = 0x04010C00ull;
+
+static const uint64_t P9N2_PEC_1_PBCQHWCFG_REG = 0x04011000ull;
+
+static const uint64_t P9N2_PEC_2_PBCQHWCFG_REG = 0x04011400ull;
+
+
+static const uint64_t P9N2_PEC_0_STACK0_PBCQMODE_REG = 0x04010C4Dull;
+
+static const uint64_t P9N2_PEC_1_STACK0_PBCQMODE_REG = 0x0401104Dull;
+
+static const uint64_t P9N2_PEC_1_STACK1_PBCQMODE_REG = 0x0401108Dull;
+
+static const uint64_t P9N2_PEC_1_STACK2_PBCQMODE_REG = 0x040110CDull;
+
+static const uint64_t P9N2_PEC_2_STACK0_PBCQMODE_REG = 0x0401144Dull;
+
+static const uint64_t P9N2_PEC_2_STACK1_PBCQMODE_REG = 0x0401148Dull;
+
+static const uint64_t P9N2_PEC_2_STACK2_PBCQMODE_REG = 0x040114CDull;
+
+static const uint64_t P9N2_PEC_STACK0_PBCQMODE_REG = 0x04010C4Dull;
+
+static const uint64_t P9N2_PHB_PBCQMODE_REG = 0x04010C4Dull;
+
+static const uint64_t P9N2_PHB_0_PBCQMODE_REG = 0x04010C4Dull;
+
+static const uint64_t P9N2_PHB_1_PBCQMODE_REG = 0x0401104Dull;
+
+static const uint64_t P9N2_PHB_2_PBCQMODE_REG = 0x0401108Dull;
+
+static const uint64_t P9N2_PHB_3_PBCQMODE_REG = 0x0401144Dull;
+
+static const uint64_t P9N2_PHB_4_PBCQMODE_REG = 0x0401148Dull;
+
+static const uint64_t P9N2_PHB_5_PBCQMODE_REG = 0x040114CDull;
+
+
+static const uint64_t P9N2_PU_PBE_MAILBOX_00_REG = 0x05013430ull;
+
+
+static const uint64_t P9N2_PU_PBE_MAILBOX_01_REG = 0x05013431ull;
+
+
+static const uint64_t P9N2_PU_PBE_MAILBOX_10_REG = 0x05013432ull;
+
+
+static const uint64_t P9N2_PU_PBE_MAILBOX_11_REG = 0x05013433ull;
+
+
+static const uint64_t P9N2_PU_PBE_MAILBOX_20_REG = 0x05013434ull;
+
+
+static const uint64_t P9N2_PU_PBE_MAILBOX_21_REG = 0x05013435ull;
+
+
+static const uint64_t P9N2_PU_PBE_MAILBOX_30_REG = 0x05013436ull;
+
+
+static const uint64_t P9N2_PU_PBE_MAILBOX_31_REG = 0x05013437ull;
+
+
+static const uint64_t P9N2_PU_PBE_MAILBOX_40_REG = 0x05013438ull;
+
+
+static const uint64_t P9N2_PU_PBE_MAILBOX_41_REG = 0x05013439ull;
+
+
+static const uint64_t P9N2_PU_PBE_MAILBOX_50_REG = 0x0501343Aull;
+
+
+static const uint64_t P9N2_PU_PBE_MAILBOX_51_REG = 0x0501343Bull;
+
+
+static const uint64_t P9N2_PU_PBE_MAILBOX_CTL_REG = 0x0501342Eull;
+
+
+static const uint64_t P9N2_PU_PBE_MAILBOX_DATA_REG = 0x0501342Full;
+
+
+static const uint64_t P9N2_PU_IOE_PBO_MAILBOX_00_REG = 0x05013830ull;
+
+
+static const uint64_t P9N2_PU_IOE_PBO_MAILBOX_01_REG = 0x05013831ull;
+
+
+static const uint64_t P9N2_PU_IOE_PBO_MAILBOX_10_REG = 0x05013832ull;
+
+
+static const uint64_t P9N2_PU_IOE_PBO_MAILBOX_11_REG = 0x05013833ull;
+
+
+static const uint64_t P9N2_PU_IOE_PBO_MAILBOX_20_REG = 0x05013834ull;
+
+
+static const uint64_t P9N2_PU_IOE_PBO_MAILBOX_21_REG = 0x05013835ull;
+
+
+static const uint64_t P9N2_PU_IOE_PBO_MAILBOX_30_REG = 0x05013836ull;
+
+
+static const uint64_t P9N2_PU_IOE_PBO_MAILBOX_31_REG = 0x05013837ull;
+
+
+static const uint64_t P9N2_PU_IOE_PBO_MAILBOX_40_REG = 0x05013838ull;
+
+
+static const uint64_t P9N2_PU_IOE_PBO_MAILBOX_41_REG = 0x05013839ull;
+
+
+static const uint64_t P9N2_PU_IOE_PBO_MAILBOX_50_REG = 0x0501383Aull;
+
+
+static const uint64_t P9N2_PU_IOE_PBO_MAILBOX_51_REG = 0x0501383Bull;
+
+
+static const uint64_t P9N2_PU_IOE_PBO_MAILBOX_60_REG = 0x0501383Cull;
+
+
+static const uint64_t P9N2_PU_IOE_PBO_MAILBOX_61_REG = 0x0501383Dull;
+
+
+static const uint64_t P9N2_PU_IOE_PBO_MAILBOX_70_REG = 0x0501383Eull;
+
+
+static const uint64_t P9N2_PU_IOE_PBO_MAILBOX_71_REG = 0x0501383Full;
+
+
+static const uint64_t P9N2_PU_IOE_PBO_MAILBOX_CTL_REG = 0x0501382Eull;
+
+
+static const uint64_t P9N2_PU_IOE_PBO_MAILBOX_DATA_REG = 0x0501382Full;
+
+
+static const uint64_t P9N2_PU_PB_BOGUS_0D_REG = 0x0501340Dull;
+
+
+static const uint64_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME = 0x05011C13ull;
+
+
+static const uint64_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW = 0x05011C14ull;
+
+
+static const uint64_t P9N2_PU_PB_CENT_SM1_PB_CENT_CR_ERROR = 0x05011C2Cull;
+
+
+static const uint64_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA = 0x05011C17ull;
+
+
+static const uint64_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB = 0x05011C18ull;
+
+
+static const uint64_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPX = 0x05011C19ull;
+
+
+static const uint64_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_SEL = 0x05011C16ull;
+
+
+static const uint64_t P9N2_PU_PB_CENT_SM1_PB_CENT_EXTDAT_COUNTER = 0x05011C25ull;
+
+
+static const uint64_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_ACTION0_REG = 0x05011C06ull;
+
+
+static const uint64_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_ACTION1_REG = 0x05011C07ull;
+
+
+static const uint64_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG = 0x05011C03ull;
+
+static const uint64_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_AND = 0x05011C04ull;
+
+static const uint64_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_OR = 0x05011C05ull;
+
+
+static const uint64_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_REG = 0x05011C00ull;
+
+static const uint64_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_REG_AND = 0x05011C01ull;
+
+static const uint64_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_REG_OR = 0x05011C02ull;
+
+
+static const uint64_t P9N2_PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0 = 0x05011C26ull;
+
+
+static const uint64_t P9N2_PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1 = 0x05011C27ull;
+
+
+static const uint64_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR = 0x05011C0Eull;
+
+
+static const uint64_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT = 0x05011C0Dull;
+
+
+static const uint64_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR = 0x05011C10ull;
+
+
+static const uint64_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT = 0x05011C0Full;
+
+
+static const uint64_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR = 0x05011C0Cull;
+
+
+static const uint64_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT = 0x05011C0Bull;
+
+
+static const uint64_t P9N2_PU_PB_CENT_SM1_PB_CENT_LMPM_COUNTER = 0x05011C23ull;
+
+
+static const uint64_t P9N2_PU_PB_CENT_SM0_PB_CENT_MODE = 0x05011C0Aull;
+
+
+static const uint64_t P9N2_PU_PB_CENT_SM1_PB_CENT_NMPM_COUNTER = 0x05011C22ull;
+
+
+static const uint64_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU0_CNPME_COUNTER = 0x05011C1Aull;
+
+
+static const uint64_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU0_CNPMW_COUNTER = 0x05011C1Eull;
+
+
+static const uint64_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU1_CNPME_COUNTER = 0x05011C1Bull;
+
+
+static const uint64_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU1_CNPMW_COUNTER = 0x05011C1Full;
+
+
+static const uint64_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU2_CNPME_COUNTER = 0x05011C1Cull;
+
+
+static const uint64_t P9N2_PU_PB_CENT_SM1_PB_CENT_PMU2_CNPMW_COUNTER = 0x05011C20ull;
+
+
+static const uint64_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU3_CNPME_COUNTER = 0x05011C1Dull;
+
+
+static const uint64_t P9N2_PU_PB_CENT_SM1_PB_CENT_PMU3_CNPMW_COUNTER = 0x05011C21ull;
+
+
+static const uint64_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER = 0x05011C15ull;
+
+
+static const uint64_t P9N2_PU_PB_CENT_SM1_PB_CENT_RCMD_INTDAT_COUNTER = 0x05011C24ull;
+
+
+static const uint64_t P9N2_PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0 = 0x05011C28ull;
+
+
+static const uint64_t P9N2_PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1 = 0x05011C29ull;
+
+
+static const uint64_t P9N2_PU_PB_CENT_SM0_PB_CENT_SCONFIG_LOAD = 0x05011C11ull;
+
+
+static const uint64_t P9N2_PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0 = 0x05011C2Aull;
+
+
+static const uint64_t P9N2_PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1 = 0x05011C2Bull;
+
+
+static const uint64_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE = 0x05011C12ull;
+
+
+static const uint64_t P9N2_PU_PB_CENT_SM1_PB_CENT_UNUSED_2D = 0x05011C2Dull;
+
+
+static const uint64_t P9N2_PU_PB_CENT_SM1_PB_CENT_UNUSED_36 = 0x05011C36ull;
+
+
+static const uint64_t P9N2_PU_PB_CENT_SM1_PB_CENT_UNUSED_37 = 0x05011C37ull;
+
+
+static const uint64_t P9N2_PU_PB_CHGRATE_CFG = 0x05012422ull;
+
+
+static const uint64_t P9N2_PU_PB_CHGRATE_GP_DP0_HIST = 0x05012424ull;
+
+
+static const uint64_t P9N2_PU_PB_CHGRATE_GP_DP1_HIST = 0x05012425ull;
+
+
+static const uint64_t P9N2_PU_PB_CHGRATE_RNS_DP0_HIST = 0x05012428ull;
+
+
+static const uint64_t P9N2_PU_PB_CHGRATE_RNS_DP1_HIST = 0x05012429ull;
+
+
+static const uint64_t P9N2_PU_PB_CHGRATE_SCONFIG_LOAD = 0x05012423ull;
+
+
+static const uint64_t P9N2_PU_PB_CHGRATE_VG_DP0_HIST = 0x05012426ull;
+
+
+static const uint64_t P9N2_PU_PB_CHGRATE_VG_DP1_HIST = 0x05012427ull;
+
+
+static const uint64_t P9N2_PU_PB_EAST_FIR_ACTION0_REG = 0x05012006ull;
+
+
+static const uint64_t P9N2_PU_PB_EAST_FIR_ACTION1_REG = 0x05012007ull;
+
+
+static const uint64_t P9N2_PU_PB_EAST_FIR_MASK_REG = 0x05012003ull;
+
+static const uint64_t P9N2_PU_PB_EAST_FIR_MASK_REG_AND = 0x05012004ull;
+
+static const uint64_t P9N2_PU_PB_EAST_FIR_MASK_REG_OR = 0x05012005ull;
+
+
+static const uint64_t P9N2_PU_PB_EAST_FIR_REG = 0x05012000ull;
+
+static const uint64_t P9N2_PU_PB_EAST_FIR_REG_AND = 0x05012001ull;
+
+static const uint64_t P9N2_PU_PB_EAST_FIR_REG_OR = 0x05012002ull;
+
+
+static const uint64_t P9N2_PU_PB_EAST_FW_SCRATCH0 = 0x05012013ull;
+
+static const uint64_t P9N2_PU_PB_EAST_FW_SCRATCH0_AND = 0x05012014ull;
+
+static const uint64_t P9N2_PU_PB_EAST_FW_SCRATCH0_OR = 0x05012015ull;
+
+
+static const uint64_t P9N2_PU_PB_EAST_FW_SCRATCH1 = 0x05012016ull;
+
+static const uint64_t P9N2_PU_PB_EAST_FW_SCRATCH1_AND = 0x05012017ull;
+
+static const uint64_t P9N2_PU_PB_EAST_FW_SCRATCH1_OR = 0x05012018ull;
+
+
+static const uint64_t P9N2_PU_PB_EAST_HPA_MODE_CURR = 0x0501200Eull;
+
+
+static const uint64_t P9N2_PU_PB_EAST_HPA_MODE_NEXT = 0x0501200Dull;
+
+
+static const uint64_t P9N2_PU_PB_EAST_HPX_MODE_CURR = 0x05012010ull;
+
+
+static const uint64_t P9N2_PU_PB_EAST_HPX_MODE_NEXT = 0x0501200Full;
+
+
+static const uint64_t P9N2_PU_PB_EAST_HP_MODE_CURR = 0x0501200Cull;
+
+
+static const uint64_t P9N2_PU_PB_EAST_HP_MODE_NEXT = 0x0501200Bull;
+
+
+static const uint64_t P9N2_PU_PB_EAST_MODE = 0x0501200Aull;
+
+
+static const uint64_t P9N2_PU_PB_EAST_SCONFIG_LOAD = 0x05012011ull;
+
+
+static const uint64_t P9N2_PU_PB_EAST_SPARE = 0x05012012ull;
+
+
+static const uint64_t P9N2_PU_PB_ELINK_DATA_01_CFG_REG = 0x05013410ull;
+
+
+static const uint64_t P9N2_PU_PB_ELINK_DATA_23_CFG_REG = 0x05013411ull;
+
+
+static const uint64_t P9N2_PU_PB_ELINK_DATA_45_CFG_REG = 0x05013412ull;
+
+
+static const uint64_t P9N2_PU_PB_ELINK_DLY_0123_REG = 0x0501340Eull;
+
+
+static const uint64_t P9N2_PU_PB_ELINK_DLY_45_REG = 0x0501340Full;
+
+
+static const uint64_t P9N2_PU_PB_ELINK_PMU0 = 0x0501341Bull;
+
+
+static const uint64_t P9N2_PU_PB_ELINK_PMU1 = 0x0501341Cull;
+
+
+static const uint64_t P9N2_PU_PB_ELINK_PMU2 = 0x0501341Dull;
+
+
+static const uint64_t P9N2_PU_PB_ELINK_PMU3 = 0x0501341Eull;
+
+
+static const uint64_t P9N2_PU_PB_ELINK_PMU4 = 0x0501341Full;
+
+
+static const uint64_t P9N2_PU_PB_ELINK_PMU5 = 0x05013420ull;
+
+
+static const uint64_t P9N2_PU_PB_ELINK_PMU6 = 0x05013421ull;
+
+
+static const uint64_t P9N2_PU_PB_ELINK_PMU7 = 0x05013422ull;
+
+
+static const uint64_t P9N2_PU_PB_ELINK_PMU_CTL_REG = 0x0501341Aull;
+
+
+static const uint64_t P9N2_PU_PB_ELINK_RT_DELAY_CTL_REG = 0x05013419ull;
+
+
+static const uint64_t P9N2_PU_PB_ELINK_SYN_01_REG = 0x05013414ull;
+
+
+static const uint64_t P9N2_PU_PB_ELINK_SYN_23_REG = 0x05013415ull;
+
+
+static const uint64_t P9N2_PU_PB_ELINK_SYN_45_REG = 0x05013416ull;
+
+
+static const uint64_t P9N2_PU_PB_EN_DOB_ECC_ERR_REG = 0x05013418ull;
+
+static const uint64_t P9N2_PU_IOE_PB_EN_DOB_ECC_ERR_REG = 0x05013818ull;
+
+
+static const uint64_t P9N2_PU_PB_FM0123_ERR = 0x05013425ull;
+
+static const uint64_t P9N2_PU_IOE_PB_FM0123_ERR = 0x05013825ull;
+
+
+static const uint64_t P9N2_PU_IOE_PB_FM4567_ERR = 0x05013826ull;
+
+
+static const uint64_t P9N2_PU_PB_FM45_ERR = 0x05013426ull;
+
+
+static const uint64_t P9N2_PU_PB_FP01_CFG = 0x0501340Aull;
+
+static const uint64_t P9N2_PU_IOE_PB_FP01_CFG = 0x0501380Aull;
+
+
+static const uint64_t P9N2_PU_PB_FP23_CFG = 0x0501340Bull;
+
+static const uint64_t P9N2_PU_IOE_PB_FP23_CFG = 0x0501380Bull;
+
+
+static const uint64_t P9N2_PU_PB_FP45_CFG = 0x0501340Cull;
+
+static const uint64_t P9N2_PU_IOE_PB_FP45_CFG = 0x0501380Cull;
+
+
+static const uint64_t P9N2_PU_IOE_PB_FP67_CFG = 0x0501380Dull;
+
+
+static const uint64_t P9N2_PU_PB_IOE_FIR_ACTION0_REG = 0x05013406ull;
+
+
+static const uint64_t P9N2_PU_PB_IOE_FIR_ACTION1_REG = 0x05013407ull;
+
+
+static const uint64_t P9N2_PU_PB_IOE_FIR_MASK_REG = 0x05013403ull;
+
+static const uint64_t P9N2_PU_PB_IOE_FIR_MASK_REG_AND = 0x05013404ull;
+
+static const uint64_t P9N2_PU_PB_IOE_FIR_MASK_REG_OR = 0x05013405ull;
+
+
+static const uint64_t P9N2_PU_PB_IOE_FIR_REG = 0x05013400ull;
+
+static const uint64_t P9N2_PU_PB_IOE_FIR_REG_AND = 0x05013401ull;
+
+static const uint64_t P9N2_PU_PB_IOE_FIR_REG_OR = 0x05013402ull;
+
+
+static const uint64_t P9N2_PU_PB_IOE_FIR_WOF_REG = 0x05013408ull;
+
+
+static const uint64_t P9N2_PU_IOE_PB_IOO_FIR_ACTION0_REG = 0x05013806ull;
+
+
+static const uint64_t P9N2_PU_IOE_PB_IOO_FIR_ACTION1_REG = 0x05013807ull;
+
+
+static const uint64_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG = 0x05013803ull;
+
+static const uint64_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_AND = 0x05013804ull;
+
+static const uint64_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_OR = 0x05013805ull;
+
+
+static const uint64_t P9N2_PU_IOE_PB_IOO_FIR_REG = 0x05013800ull;
+
+static const uint64_t P9N2_PU_IOE_PB_IOO_FIR_REG_AND = 0x05013801ull;
+
+static const uint64_t P9N2_PU_IOE_PB_IOO_FIR_REG_OR = 0x05013802ull;
+
+
+static const uint64_t P9N2_PU_IOE_PB_IOO_FIR_WOF_REG = 0x05013808ull;
+
+
+static const uint64_t P9N2_PU_PB_MISC_CFG = 0x05013423ull;
+
+static const uint64_t P9N2_PU_IOE_PB_MISC_CFG = 0x05013823ull;
+
+
+static const uint64_t P9N2_PU_IOE_PB_OLINK_DATA_01_CFG_REG = 0x05013810ull;
+
+
+static const uint64_t P9N2_PU_IOE_PB_OLINK_DATA_23_CFG_REG = 0x05013811ull;
+
+
+static const uint64_t P9N2_PU_IOE_PB_OLINK_DATA_45_CFG_REG = 0x05013812ull;
+
+
+static const uint64_t P9N2_PU_IOE_PB_OLINK_DATA_67_CFG_REG = 0x05013813ull;
+
+
+static const uint64_t P9N2_PU_IOE_PB_OLINK_DLY_0123_REG = 0x0501380Eull;
+
+
+static const uint64_t P9N2_PU_IOE_PB_OLINK_DLY_4567_REG = 0x0501380Full;
+
+
+static const uint64_t P9N2_PU_IOE_PB_OLINK_PMU0 = 0x0501381Bull;
+
+
+static const uint64_t P9N2_PU_IOE_PB_OLINK_PMU1 = 0x0501381Cull;
+
+
+static const uint64_t P9N2_PU_IOE_PB_OLINK_PMU2 = 0x0501381Dull;
+
+
+static const uint64_t P9N2_PU_IOE_PB_OLINK_PMU3 = 0x0501381Eull;
+
+
+static const uint64_t P9N2_PU_IOE_PB_OLINK_PMU4 = 0x0501381Full;
+
+
+static const uint64_t P9N2_PU_IOE_PB_OLINK_PMU5 = 0x05013820ull;
+
+
+static const uint64_t P9N2_PU_IOE_PB_OLINK_PMU6 = 0x05013821ull;
+
+
+static const uint64_t P9N2_PU_IOE_PB_OLINK_PMU7 = 0x05013822ull;
+
+
+static const uint64_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG = 0x0501381Aull;
+
+
+static const uint64_t P9N2_PU_IOE_PB_OLINK_RT_DELAY_CTL_REG = 0x05013819ull;
+
+
+static const uint64_t P9N2_PU_IOE_PB_OLINK_SYN_01_REG = 0x05013814ull;
+
+
+static const uint64_t P9N2_PU_IOE_PB_OLINK_SYN_23_REG = 0x05013815ull;
+
+
+static const uint64_t P9N2_PU_IOE_PB_OLINK_SYN_45_REG = 0x05013816ull;
+
+
+static const uint64_t P9N2_PU_IOE_PB_OLINK_SYN_67_REG = 0x05013817ull;
+
+
+static const uint64_t P9N2_PU_PB_PERFTRACE_CFG_REG = 0x05013429ull;
+
+static const uint64_t P9N2_PU_IOE_PB_PERFTRACE_CFG_REG = 0x05013829ull;
+
+
+static const uint64_t P9N2_PU_PB_PPE_BOGUS_16_REG = 0x05012416ull;
+
+
+static const uint64_t P9N2_PU_PB_PPE_LFIR = 0x05012400ull;
+
+static const uint64_t P9N2_PU_PB_PPE_LFIR_AND = 0x05012401ull;
+
+static const uint64_t P9N2_PU_PB_PPE_LFIR_OR = 0x05012402ull;
+
+
+static const uint64_t P9N2_PU_PB_PPE_LFIRACT0 = 0x05012406ull;
+
+
+static const uint64_t P9N2_PU_PB_PPE_LFIRACT1 = 0x05012407ull;
+
+
+static const uint64_t P9N2_PU_PB_PPE_LFIRMASK = 0x05012403ull;
+
+static const uint64_t P9N2_PU_PB_PPE_LFIRMASK_AND = 0x05012404ull;
+
+static const uint64_t P9N2_PU_PB_PPE_LFIRMASK_OR = 0x05012405ull;
+
+
+static const uint64_t P9N2_PU_PB_PPE_LFIRWOF = 0x05012408ull;
+
+
+static const uint64_t P9N2_PU_PB_PR0123_ERR = 0x05013427ull;
+
+static const uint64_t P9N2_PU_IOE_PB_PR0123_ERR = 0x05013827ull;
+
+
+static const uint64_t P9N2_PU_IOE_PB_PR4567_ERR = 0x05013828ull;
+
+
+static const uint64_t P9N2_PU_PB_PR45_ERR = 0x05013428ull;
+
+
+static const uint64_t P9N2_PU_PB_PSAVE_CFG = 0x0501241Aull;
+
+
+static const uint64_t P9N2_PU_PB_PSAVE_MON_CFG = 0x0501241Bull;
+
+
+static const uint64_t P9N2_PU_PB_PSAVE_X0EVN_HIST = 0x0501241Cull;
+
+
+static const uint64_t P9N2_PU_PB_PSAVE_X0ODD_HIST = 0x0501241Dull;
+
+
+static const uint64_t P9N2_PU_PB_PSAVE_X1EVN_HIST = 0x0501241Eull;
+
+
+static const uint64_t P9N2_PU_PB_PSAVE_X1ODD_HIST = 0x0501241Full;
+
+
+static const uint64_t P9N2_PU_PB_PSAVE_X2EVN_HIST = 0x05012420ull;
+
+
+static const uint64_t P9N2_PU_PB_PSAVE_X2ODD_HIST = 0x05012421ull;
+
+
+static const uint64_t P9N2_PU_PB_SERIAL_SCOM_CENT_0 = 0x9000032005011C11ull;
+
+
+static const uint64_t P9N2_PU_PB_SERIAL_SCOM_CENT_1 = 0x900002E105011C11ull;
+
+
+static const uint64_t P9N2_PU_PB_SERIAL_SCOM_CENT_2 = 0x900002A205011C11ull;
+
+
+static const uint64_t P9N2_PU_PB_SERIAL_SCOM_CENT_3 = 0x9000024305011C11ull;
+
+
+static const uint64_t P9N2_PU_PB_SERIAL_SCOM_CENT_4 = 0x900000F405011C11ull;
+
+
+static const uint64_t P9N2_PU_PB_SERIAL_SCOM_CENT_5 = 0x9000030505011C11ull;
+
+
+static const uint64_t P9N2_PU_PB_SERIAL_SCOM_CENT_6 = 0x9000020605011C11ull;
+
+
+static const uint64_t P9N2_PU_PB_SERIAL_SCOM_CENT_7 = 0x900002C705011C11ull;
+
+
+static const uint64_t P9N2_PU_PB_SERIAL_SCOM_CENT_8 = 0x9000016805011C11ull;
+
+
+static const uint64_t P9N2_PU_PB_SERIAL_SCOM_CENT_9 = 0x900002C905011C11ull;
+
+
+static const uint64_t P9N2_PU_PB_SERIAL_SCOM_CENT_A = 0x900000EA05011C11ull;
+
+
+static const uint64_t P9N2_PU_PB_SERIAL_SCOM_CENT_B = 0x9000007B05011C11ull;
+
+
+static const uint64_t P9N2_PU_PB_SERIAL_SCOM_CENT_C = 0x9000018C05011C11ull;
+
+
+static const uint64_t P9N2_PU_PB_SERIAL_SCOM_CENT_D = 0x9000033D05011C11ull;
+
+
+static const uint64_t P9N2_PU_PB_SERIAL_SCOM_CENT_E = 0x900000AE05011C11ull;
+
+
+static const uint64_t P9N2_PU_PB_SERIAL_SCOM_CENT_F = 0x9000010F05011C11ull;
+
+
+static const uint64_t P9N2_PU_PB_SERIAL_SCOM_EAST_0 = 0x9000034005012011ull;
+
+
+static const uint64_t P9N2_PU_PB_SERIAL_SCOM_EAST_1 = 0x9000026105012011ull;
+
+
+static const uint64_t P9N2_PU_PB_SERIAL_SCOM_EAST_2 = 0x900000B205012011ull;
+
+
+static const uint64_t P9N2_PU_PB_SERIAL_SCOM_EAST_3 = 0x900000B305012011ull;
+
+
+static const uint64_t P9N2_PU_PB_SERIAL_SCOM_WEST_0 = 0x9000034005011811ull;
+
+
+static const uint64_t P9N2_PU_PB_SERIAL_SCOM_WEST_1 = 0x9000026105011811ull;
+
+
+static const uint64_t P9N2_PU_PB_TRACE_CFG = 0x05013424ull;
+
+static const uint64_t P9N2_PU_IOE_PB_TRACE_CFG = 0x05013824ull;
+
+
+static const uint64_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_ACTION0_REG = 0x05011806ull;
+
+
+static const uint64_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_ACTION1_REG = 0x05011807ull;
+
+
+static const uint64_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG = 0x05011803ull;
+
+static const uint64_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_AND = 0x05011804ull;
+
+static const uint64_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_OR = 0x05011805ull;
+
+
+static const uint64_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_REG = 0x05011800ull;
+
+static const uint64_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_REG_AND = 0x05011801ull;
+
+static const uint64_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_REG_OR = 0x05011802ull;
+
+
+static const uint64_t P9N2_PU_PB_WEST_SM0_PB_WEST_FW_SCRATCH0 = 0x05011813ull;
+
+static const uint64_t P9N2_PU_PB_WEST_SM0_PB_WEST_FW_SCRATCH0_AND = 0x05011814ull;
+
+static const uint64_t P9N2_PU_PB_WEST_SM0_PB_WEST_FW_SCRATCH0_OR = 0x05011815ull;
+
+
+static const uint64_t P9N2_PU_PB_WEST_SM0_PB_WEST_FW_SCRATCH1 = 0x05011816ull;
+
+static const uint64_t P9N2_PU_PB_WEST_SM0_PB_WEST_FW_SCRATCH1_AND = 0x05011817ull;
+
+static const uint64_t P9N2_PU_PB_WEST_SM0_PB_WEST_FW_SCRATCH1_OR = 0x05011818ull;
+
+
+static const uint64_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR = 0x0501180Eull;
+
+
+static const uint64_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT = 0x0501180Dull;
+
+
+static const uint64_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR = 0x05011810ull;
+
+
+static const uint64_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT = 0x0501180Full;
+
+
+static const uint64_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR = 0x0501180Cull;
+
+
+static const uint64_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT = 0x0501180Bull;
+
+
+static const uint64_t P9N2_PU_PB_WEST_SM0_PB_WEST_MODE = 0x0501180Aull;
+
+
+static const uint64_t P9N2_PU_PB_WEST_SM0_PB_WEST_SCONFIG_LOAD = 0x05011811ull;
+
+
+static const uint64_t P9N2_PU_PB_WEST_SM0_PB_WEST_SPARE = 0x05011812ull;
+
+
+static const uint64_t P9N2_PEC_PCB_OPCG_GO = 0x0D030020ull;
+
+static const uint64_t P9N2_PEC_0_PCB_OPCG_GO = 0x0D030020ull;
+
+static const uint64_t P9N2_PEC_1_PCB_OPCG_GO = 0x0E030020ull;
+
+static const uint64_t P9N2_PEC_2_PCB_OPCG_GO = 0x0F030020ull;
+
+
+static const uint64_t P9N2_PEC_PCB_OPCG_STOP = 0x0D030030ull;
+
+static const uint64_t P9N2_PEC_0_PCB_OPCG_STOP = 0x0D030030ull;
+
+static const uint64_t P9N2_PEC_1_PCB_OPCG_STOP = 0x0E030030ull;
+
+static const uint64_t P9N2_PEC_2_PCB_OPCG_STOP = 0x0F030030ull;
+
+
+static const uint64_t P9N2_PEC_PCS_M1_CONTROL_REG = 0x80000C010D010C3Full;
+
+static const uint64_t P9N2_PEC_0_PCS_M1_CONTROL_REG = 0x80000C010D010C3Full;
+
+static const uint64_t P9N2_PEC_1_PCS_M1_CONTROL_REG = 0x80000C010E010C3Full;
+
+static const uint64_t P9N2_PEC_2_PCS_M1_CONTROL_REG = 0x80000C010F010C3Full;
+
+
+static const uint64_t P9N2_PEC_PCS_M2_CONTROL_REG = 0x80000C020D010C3Full;
+
+static const uint64_t P9N2_PEC_0_PCS_M2_CONTROL_REG = 0x80000C020D010C3Full;
+
+static const uint64_t P9N2_PEC_1_PCS_M2_CONTROL_REG = 0x80000C020E010C3Full;
+
+static const uint64_t P9N2_PEC_2_PCS_M2_CONTROL_REG = 0x80000C020F010C3Full;
+
+
+static const uint64_t P9N2_PEC_PCS_M3_CONTROL_REG = 0x80000C030D010C3Full;
+
+static const uint64_t P9N2_PEC_0_PCS_M3_CONTROL_REG = 0x80000C030D010C3Full;
+
+static const uint64_t P9N2_PEC_1_PCS_M3_CONTROL_REG = 0x80000C030E010C3Full;
+
+static const uint64_t P9N2_PEC_2_PCS_M3_CONTROL_REG = 0x80000C030F010C3Full;
+
+
+static const uint64_t P9N2_PEC_PCS_M4_CONTROL_REG = 0x80000C040D010C3Full;
+
+static const uint64_t P9N2_PEC_0_PCS_M4_CONTROL_REG = 0x80000C040D010C3Full;
+
+static const uint64_t P9N2_PEC_1_PCS_M4_CONTROL_REG = 0x80000C040E010C3Full;
+
+static const uint64_t P9N2_PEC_2_PCS_M4_CONTROL_REG = 0x80000C040F010C3Full;
+
+
+static const uint64_t P9N2_PEC_PCS_SYS_CONTROL_REG = 0x80000C000D010C3Full;
+
+static const uint64_t P9N2_PEC_0_PCS_SYS_CONTROL_REG = 0x80000C000D010C3Full;
+
+static const uint64_t P9N2_PEC_1_PCS_SYS_CONTROL_REG = 0x80000C000E010C3Full;
+
+static const uint64_t P9N2_PEC_2_PCS_SYS_CONTROL_REG = 0x80000C000F010C3Full;
+
+
+static const uint64_t P9N2_PEC_PECAPP_CNTL_REG = 0x04010C07ull;
+
+static const uint64_t P9N2_PEC_0_PECAPP_CNTL_REG = 0x04010C07ull;
+
+static const uint64_t P9N2_PEC_1_PECAPP_CNTL_REG = 0x04011007ull;
+
+static const uint64_t P9N2_PEC_2_PECAPP_CNTL_REG = 0x04011407ull;
+
+
+static const uint64_t P9N2_PEC_PECAPP_SEC_BAR = 0x0D010801ull;
+
+static const uint64_t P9N2_PEC_0_PECAPP_SEC_BAR = 0x0D010801ull;
+
+static const uint64_t P9N2_PEC_1_PECAPP_SEC_BAR = 0x0E010801ull;
+
+static const uint64_t P9N2_PEC_2_PECAPP_SEC_BAR = 0x0F010801ull;
+
+
+static const uint64_t P9N2_PU_NPU0_CTL_PERF_ADDR_CONFIG = 0x05011080ull;
+
+static const uint64_t P9N2_PU_NPU0_DAT_PERF_ADDR_CONFIG = 0x050110B0ull;
+
+static const uint64_t P9N2_PU_NPU2_CTL_PERF_ADDR_CONFIG = 0x05011280ull;
+
+static const uint64_t P9N2_PU_NPU2_DAT_PERF_ADDR_CONFIG = 0x050112B0ull;
+
+static const uint64_t P9N2_PU_NPU0_SM1_PERF_ADDR_CONFIG = 0x05011020ull;
+
+static const uint64_t P9N2_PU_NPU0_SM2_PERF_ADDR_CONFIG = 0x05011050ull;
+
+static const uint64_t P9N2_PU_NPU2_SM1_PERF_ADDR_CONFIG = 0x05011220ull;
+
+static const uint64_t P9N2_PU_NPU2_SM2_PERF_ADDR_CONFIG = 0x05011250ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_CTL_PERF_ADDR_CONFIG = 0x05011480ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_DAT_PERF_ADDR_CONFIG = 0x050114B0ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM1_PERF_ADDR_CONFIG = 0x05011420ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM2_PERF_ADDR_CONFIG = 0x05011450ull;
+
+
+static const uint64_t P9N2_NV_PERF_CONFIG = 0x050110C7ull;
+
+static const uint64_t P9N2_NV_0_PERF_CONFIG = 0x050110C7ull;
+
+static const uint64_t P9N2_NV_4_PERF_CONFIG = 0x050114C7ull;
+
+static const uint64_t P9N2_PU_NPU0_CTL_PERF_CONFIG = 0x0501109Full;
+
+static const uint64_t P9N2_PU_NPU2_CTL_PERF_CONFIG = 0x0501129Full;
+
+static const uint64_t P9N2_PU_NPU0_SM0_PERF_CONFIG = 0x0501100Full;
+
+static const uint64_t P9N2_PU_NPU0_SM1_PERF_CONFIG = 0x0501103Full;
+
+static const uint64_t P9N2_PU_NPU0_SM3_PERF_CONFIG = 0x0501106Full;
+
+static const uint64_t P9N2_PU_NPU1_SM0_PERF_CONFIG = 0x0501111Eull;
+
+static const uint64_t P9N2_PU_NPU1_SM1_PERF_CONFIG = 0x0501113Eull;
+
+static const uint64_t P9N2_PU_NPU2_NTL0_PERF_CONFIG = 0x050112C7ull;
+
+static const uint64_t P9N2_PU_NPU2_SM0_PERF_CONFIG = 0x0501120Full;
+
+static const uint64_t P9N2_PU_NPU2_SM1_PERF_CONFIG = 0x0501123Full;
+
+static const uint64_t P9N2_PU_NPU2_SM3_PERF_CONFIG = 0x0501126Full;
+
+static const uint64_t P9N2_PU_NPU_MSC_CTL_PERF_CONFIG = 0x0501149Full;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM0_PERF_CONFIG = 0x0501140Full;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM1_PERF_CONFIG = 0x0501143Full;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM3_PERF_CONFIG = 0x0501146Full;
+
+static const uint64_t P9N2_PU_NPU_SM0_PERF_CONFIG = 0x0501131Eull;
+
+static const uint64_t P9N2_PU_NPU_SM1_PERF_CONFIG = 0x0501133Eull;
+
+static const uint64_t P9N2__SM0_PERF_CONFIG = 0x0501151Eull;
+
+static const uint64_t P9N2__SM1_PERF_CONFIG = 0x0501153Eull;
+
+
+static const uint64_t P9N2_NV_PERF_COUNT = 0x050110C6ull;
+
+static const uint64_t P9N2_NV_0_PERF_COUNT = 0x050110C6ull;
+
+static const uint64_t P9N2_NV_4_PERF_COUNT = 0x050114C6ull;
+
+static const uint64_t P9N2_PU_NPU1_SM0_PERF_COUNT = 0x0501111Full;
+
+static const uint64_t P9N2_PU_NPU1_SM1_PERF_COUNT = 0x0501113Full;
+
+static const uint64_t P9N2_PU_NPU2_NTL0_PERF_COUNT = 0x050112C6ull;
+
+static const uint64_t P9N2_PU_NPU_SM0_PERF_COUNT = 0x0501131Full;
+
+static const uint64_t P9N2_PU_NPU_SM1_PERF_COUNT = 0x0501133Full;
+
+static const uint64_t P9N2__SM0_PERF_COUNT = 0x0501151Full;
+
+static const uint64_t P9N2__SM1_PERF_COUNT = 0x0501153Full;
+
+
+static const uint64_t P9N2_NV_PERF_MASK_CONFIG = 0x050110C5ull;
+
+static const uint64_t P9N2_NV_0_PERF_MASK_CONFIG = 0x050110C5ull;
+
+static const uint64_t P9N2_NV_4_PERF_MASK_CONFIG = 0x050114C5ull;
+
+static const uint64_t P9N2_PU_NPU0_CTL_PERF_MASK_CONFIG = 0x05011082ull;
+
+static const uint64_t P9N2_PU_NPU0_DAT_PERF_MASK_CONFIG = 0x050110B2ull;
+
+static const uint64_t P9N2_PU_NPU2_DAT_PERF_MASK_CONFIG = 0x050112B2ull;
+
+static const uint64_t P9N2_PU_NPU2_CTL_PERF_MASK_CONFIG = 0x05011282ull;
+
+static const uint64_t P9N2_PU_NPU0_SM1_PERF_MASK_CONFIG = 0x05011022ull;
+
+static const uint64_t P9N2_PU_NPU0_SM2_PERF_MASK_CONFIG = 0x05011052ull;
+
+static const uint64_t P9N2_PU_NPU2_NTL0_PERF_MASK_CONFIG = 0x050112C5ull;
+
+static const uint64_t P9N2_PU_NPU2_SM1_PERF_MASK_CONFIG = 0x05011222ull;
+
+static const uint64_t P9N2_PU_NPU2_SM2_PERF_MASK_CONFIG = 0x05011252ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_CTL_PERF_MASK_CONFIG = 0x05011482ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_DAT_PERF_MASK_CONFIG = 0x050114B2ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM1_PERF_MASK_CONFIG = 0x05011422ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM2_PERF_MASK_CONFIG = 0x05011452ull;
+
+
+static const uint64_t P9N2_NV_PERF_MATCH_CONFIG = 0x050110C4ull;
+
+static const uint64_t P9N2_NV_0_PERF_MATCH_CONFIG = 0x050110C4ull;
+
+static const uint64_t P9N2_NV_4_PERF_MATCH_CONFIG = 0x050114C4ull;
+
+static const uint64_t P9N2_PU_NPU0_CTL_PERF_MATCH_CONFIG = 0x05011081ull;
+
+static const uint64_t P9N2_PU_NPU0_DAT_PERF_MATCH_CONFIG = 0x050110B1ull;
+
+static const uint64_t P9N2_PU_NPU2_DAT_PERF_MATCH_CONFIG = 0x050112B1ull;
+
+static const uint64_t P9N2_PU_NPU2_CTL_PERF_MATCH_CONFIG = 0x05011281ull;
+
+static const uint64_t P9N2_PU_NPU0_SM1_PERF_MATCH_CONFIG = 0x05011021ull;
+
+static const uint64_t P9N2_PU_NPU0_SM2_PERF_MATCH_CONFIG = 0x05011051ull;
+
+static const uint64_t P9N2_PU_NPU2_NTL0_PERF_MATCH_CONFIG = 0x050112C4ull;
+
+static const uint64_t P9N2_PU_NPU2_SM1_PERF_MATCH_CONFIG = 0x05011221ull;
+
+static const uint64_t P9N2_PU_NPU2_SM2_PERF_MATCH_CONFIG = 0x05011251ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_CTL_PERF_MATCH_CONFIG = 0x05011481ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_DAT_PERF_MATCH_CONFIG = 0x050114B1ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM1_PERF_MATCH_CONFIG = 0x05011421ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM2_PERF_MATCH_CONFIG = 0x05011451ull;
+
+
+static const uint64_t P9N2_PEC_PERTYBOCTL_REG = 0x04010C0Bull;
+
+static const uint64_t P9N2_PEC_0_PERTYBOCTL_REG = 0x04010C0Bull;
+
+static const uint64_t P9N2_PEC_1_PERTYBOCTL_REG = 0x0401100Bull;
+
+static const uint64_t P9N2_PEC_2_PERTYBOCTL_REG = 0x0401140Bull;
+
+
+static const uint64_t P9N2__NTL0_PESTB_ADDR_PE0 = 0x050116D0ull;
+
+
+static const uint64_t P9N2__NTL0_PESTB_ADDR_PE1 = 0x050116D1ull;
+
+
+static const uint64_t P9N2__NTL0_PESTB_ADDR_PE10 = 0x050116DAull;
+
+
+static const uint64_t P9N2__NTL0_PESTB_ADDR_PE11 = 0x050116DBull;
+
+
+static const uint64_t P9N2__NTL0_PESTB_ADDR_PE12 = 0x050116DCull;
+
+
+static const uint64_t P9N2__NTL0_PESTB_ADDR_PE13 = 0x050116DDull;
+
+
+static const uint64_t P9N2__NTL0_PESTB_ADDR_PE14 = 0x050116DEull;
+
+
+static const uint64_t P9N2__NTL0_PESTB_ADDR_PE15 = 0x050116DFull;
+
+
+static const uint64_t P9N2__NTL0_PESTB_ADDR_PE2 = 0x050116D2ull;
+
+
+static const uint64_t P9N2__NTL0_PESTB_ADDR_PE3 = 0x050116D3ull;
+
+
+static const uint64_t P9N2__NTL0_PESTB_ADDR_PE4 = 0x050116D4ull;
+
+
+static const uint64_t P9N2__NTL0_PESTB_ADDR_PE5 = 0x050116D5ull;
+
+
+static const uint64_t P9N2__NTL0_PESTB_ADDR_PE6 = 0x050116D6ull;
+
+
+static const uint64_t P9N2__NTL0_PESTB_ADDR_PE7 = 0x050116D7ull;
+
+
+static const uint64_t P9N2__NTL0_PESTB_ADDR_PE8 = 0x050116D8ull;
+
+
+static const uint64_t P9N2__NTL0_PESTB_ADDR_PE9 = 0x050116D9ull;
+
+
+static const uint64_t P9N2__NTL0_PESTB_DATA_PE0 = 0x050116C0ull;
+
+
+static const uint64_t P9N2__NTL0_PESTB_DATA_PE1 = 0x050116C1ull;
+
+
+static const uint64_t P9N2__NTL0_PESTB_DATA_PE10 = 0x050116CAull;
+
+
+static const uint64_t P9N2__NTL0_PESTB_DATA_PE11 = 0x050116CBull;
+
+
+static const uint64_t P9N2__NTL0_PESTB_DATA_PE12 = 0x050116CCull;
+
+
+static const uint64_t P9N2__NTL0_PESTB_DATA_PE13 = 0x050116CDull;
+
+
+static const uint64_t P9N2__NTL0_PESTB_DATA_PE14 = 0x050116CEull;
+
+
+static const uint64_t P9N2__NTL0_PESTB_DATA_PE15 = 0x050116CFull;
+
+
+static const uint64_t P9N2__NTL0_PESTB_DATA_PE2 = 0x050116C2ull;
+
+
+static const uint64_t P9N2__NTL0_PESTB_DATA_PE3 = 0x050116C3ull;
+
+
+static const uint64_t P9N2__NTL0_PESTB_DATA_PE4 = 0x050116C4ull;
+
+
+static const uint64_t P9N2__NTL0_PESTB_DATA_PE5 = 0x050116C5ull;
+
+
+static const uint64_t P9N2__NTL0_PESTB_DATA_PE6 = 0x050116C6ull;
+
+
+static const uint64_t P9N2__NTL0_PESTB_DATA_PE7 = 0x050116C7ull;
+
+
+static const uint64_t P9N2__NTL0_PESTB_DATA_PE8 = 0x050116C8ull;
+
+
+static const uint64_t P9N2__NTL0_PESTB_DATA_PE9 = 0x050116C9ull;
+
+
+static const uint64_t P9N2_PEC_0_STACK0_PE_DFREEZE_REG = 0x04010C55ull;
+
+static const uint64_t P9N2_PEC_1_STACK0_PE_DFREEZE_REG = 0x04011055ull;
+
+static const uint64_t P9N2_PEC_1_STACK1_PE_DFREEZE_REG = 0x04011095ull;
+
+static const uint64_t P9N2_PEC_1_STACK2_PE_DFREEZE_REG = 0x040110D5ull;
+
+static const uint64_t P9N2_PEC_2_STACK0_PE_DFREEZE_REG = 0x04011455ull;
+
+static const uint64_t P9N2_PEC_2_STACK1_PE_DFREEZE_REG = 0x04011495ull;
+
+static const uint64_t P9N2_PEC_2_STACK2_PE_DFREEZE_REG = 0x040114D5ull;
+
+static const uint64_t P9N2_PEC_STACK0_PE_DFREEZE_REG = 0x04010C55ull;
+
+static const uint64_t P9N2_PHB_PE_DFREEZE_REG = 0x04010C55ull;
+
+static const uint64_t P9N2_PHB_0_PE_DFREEZE_REG = 0x04010C55ull;
+
+static const uint64_t P9N2_PHB_1_PE_DFREEZE_REG = 0x04011055ull;
+
+static const uint64_t P9N2_PHB_2_PE_DFREEZE_REG = 0x04011095ull;
+
+static const uint64_t P9N2_PHB_3_PE_DFREEZE_REG = 0x04011455ull;
+
+static const uint64_t P9N2_PHB_4_PE_DFREEZE_REG = 0x04011495ull;
+
+static const uint64_t P9N2_PHB_5_PE_DFREEZE_REG = 0x040114D5ull;
+
+
+static const uint64_t P9N2_PHB_PFIRACTION0_REG = 0x0D010846ull;
+
+static const uint64_t P9N2_PHB_0_PFIRACTION0_REG = 0x0D010846ull;
+
+static const uint64_t P9N2_PHB_1_PFIRACTION0_REG = 0x0E010846ull;
+
+static const uint64_t P9N2_PHB_2_PFIRACTION0_REG = 0x0E010886ull;
+
+static const uint64_t P9N2_PHB_3_PFIRACTION0_REG = 0x0F010846ull;
+
+static const uint64_t P9N2_PHB_4_PFIRACTION0_REG = 0x0F010886ull;
+
+static const uint64_t P9N2_PHB_5_PFIRACTION0_REG = 0x0F0108C6ull;
+
+
+static const uint64_t P9N2_PHB_PFIRACTION1_REG = 0x0D010847ull;
+
+static const uint64_t P9N2_PHB_0_PFIRACTION1_REG = 0x0D010847ull;
+
+static const uint64_t P9N2_PHB_1_PFIRACTION1_REG = 0x0E010847ull;
+
+static const uint64_t P9N2_PHB_2_PFIRACTION1_REG = 0x0E010887ull;
+
+static const uint64_t P9N2_PHB_3_PFIRACTION1_REG = 0x0F010847ull;
+
+static const uint64_t P9N2_PHB_4_PFIRACTION1_REG = 0x0F010887ull;
+
+static const uint64_t P9N2_PHB_5_PFIRACTION1_REG = 0x0F0108C7ull;
+
+
+static const uint64_t P9N2_PHB_PFIRMASK_REG = 0x0D010843ull;
+
+static const uint64_t P9N2_PHB_PFIRMASK_REG_AND = 0x0D010844ull;
+
+static const uint64_t P9N2_PHB_PFIRMASK_REG_OR = 0x0D010845ull;
+
+static const uint64_t P9N2_PHB_0_PFIRMASK_REG = 0x0D010843ull;
+
+static const uint64_t P9N2_PHB_0_PFIRMASK_REG_AND = 0x0D010844ull;
+
+static const uint64_t P9N2_PHB_0_PFIRMASK_REG_OR = 0x0D010845ull;
+
+static const uint64_t P9N2_PHB_1_PFIRMASK_REG = 0x0E010843ull;
+
+static const uint64_t P9N2_PHB_1_PFIRMASK_REG_AND = 0x0E010844ull;
+
+static const uint64_t P9N2_PHB_1_PFIRMASK_REG_OR = 0x0E010845ull;
+
+static const uint64_t P9N2_PHB_2_PFIRMASK_REG = 0x0E010883ull;
+
+static const uint64_t P9N2_PHB_2_PFIRMASK_REG_AND = 0x0E010884ull;
+
+static const uint64_t P9N2_PHB_2_PFIRMASK_REG_OR = 0x0E010885ull;
+
+static const uint64_t P9N2_PHB_3_PFIRMASK_REG = 0x0F010843ull;
+
+static const uint64_t P9N2_PHB_3_PFIRMASK_REG_AND = 0x0F010844ull;
+
+static const uint64_t P9N2_PHB_3_PFIRMASK_REG_OR = 0x0F010845ull;
+
+static const uint64_t P9N2_PHB_4_PFIRMASK_REG = 0x0F010883ull;
+
+static const uint64_t P9N2_PHB_4_PFIRMASK_REG_AND = 0x0F010884ull;
+
+static const uint64_t P9N2_PHB_4_PFIRMASK_REG_OR = 0x0F010885ull;
+
+static const uint64_t P9N2_PHB_5_PFIRMASK_REG = 0x0F0108C3ull;
+
+static const uint64_t P9N2_PHB_5_PFIRMASK_REG_AND = 0x0F0108C4ull;
+
+static const uint64_t P9N2_PHB_5_PFIRMASK_REG_OR = 0x0F0108C5ull;
+
+
+static const uint64_t P9N2_PHB_PFIRWOF_REG = 0x0D010848ull;
+
+static const uint64_t P9N2_PHB_0_PFIRWOF_REG = 0x0D010848ull;
+
+static const uint64_t P9N2_PHB_1_PFIRWOF_REG = 0x0E010848ull;
+
+static const uint64_t P9N2_PHB_2_PFIRWOF_REG = 0x0E010888ull;
+
+static const uint64_t P9N2_PHB_3_PFIRWOF_REG = 0x0F010848ull;
+
+static const uint64_t P9N2_PHB_4_PFIRWOF_REG = 0x0F010888ull;
+
+static const uint64_t P9N2_PHB_5_PFIRWOF_REG = 0x0F0108C8ull;
+
+
+static const uint64_t P9N2_PHB_PFIR_REG = 0x0D010840ull;
+
+static const uint64_t P9N2_PHB_PFIR_REG_AND = 0x0D010841ull;
+
+static const uint64_t P9N2_PHB_PFIR_REG_OR = 0x0D010842ull;
+
+static const uint64_t P9N2_PHB_0_PFIR_REG = 0x0D010840ull;
+
+static const uint64_t P9N2_PHB_0_PFIR_REG_AND = 0x0D010841ull;
+
+static const uint64_t P9N2_PHB_0_PFIR_REG_OR = 0x0D010842ull;
+
+static const uint64_t P9N2_PHB_1_PFIR_REG = 0x0E010840ull;
+
+static const uint64_t P9N2_PHB_1_PFIR_REG_AND = 0x0E010841ull;
+
+static const uint64_t P9N2_PHB_1_PFIR_REG_OR = 0x0E010842ull;
+
+static const uint64_t P9N2_PHB_2_PFIR_REG = 0x0E010880ull;
+
+static const uint64_t P9N2_PHB_2_PFIR_REG_AND = 0x0E010881ull;
+
+static const uint64_t P9N2_PHB_2_PFIR_REG_OR = 0x0E010882ull;
+
+static const uint64_t P9N2_PHB_3_PFIR_REG = 0x0F010840ull;
+
+static const uint64_t P9N2_PHB_3_PFIR_REG_AND = 0x0F010841ull;
+
+static const uint64_t P9N2_PHB_3_PFIR_REG_OR = 0x0F010842ull;
+
+static const uint64_t P9N2_PHB_4_PFIR_REG = 0x0F010880ull;
+
+static const uint64_t P9N2_PHB_4_PFIR_REG_AND = 0x0F010881ull;
+
+static const uint64_t P9N2_PHB_4_PFIR_REG_OR = 0x0F010882ull;
+
+static const uint64_t P9N2_PHB_5_PFIR_REG = 0x0F0108C0ull;
+
+static const uint64_t P9N2_PHB_5_PFIR_REG_AND = 0x0F0108C1ull;
+
+static const uint64_t P9N2_PHB_5_PFIR_REG_OR = 0x0F0108C2ull;
+
+
+static const uint64_t P9N2_PHB_PHB4_SCOM_HVIAR = 0x0D010900ull;
+
+static const uint64_t P9N2_PHB_0_PHB4_SCOM_HVIAR = 0x0D010900ull;
+
+static const uint64_t P9N2_PHB_1_PHB4_SCOM_HVIAR = 0x0E010900ull;
+
+static const uint64_t P9N2_PHB_2_PHB4_SCOM_HVIAR = 0x0E010940ull;
+
+static const uint64_t P9N2_PHB_3_PHB4_SCOM_HVIAR = 0x0F010900ull;
+
+static const uint64_t P9N2_PHB_4_PHB4_SCOM_HVIAR = 0x0F010940ull;
+
+static const uint64_t P9N2_PHB_5_PHB4_SCOM_HVIAR = 0x0F010980ull;
+
+
+static const uint64_t P9N2_PHB_PHB4_SCOM_UV_SEC_EXCL = 0x0D010904ull;
+
+static const uint64_t P9N2_PHB_0_PHB4_SCOM_UV_SEC_EXCL = 0x0D010904ull;
+
+static const uint64_t P9N2_PHB_1_PHB4_SCOM_UV_SEC_EXCL = 0x0E010904ull;
+
+static const uint64_t P9N2_PHB_2_PHB4_SCOM_UV_SEC_EXCL = 0x0E010944ull;
+
+static const uint64_t P9N2_PHB_3_PHB4_SCOM_UV_SEC_EXCL = 0x0F010904ull;
+
+static const uint64_t P9N2_PHB_4_PHB4_SCOM_UV_SEC_EXCL = 0x0F010944ull;
+
+static const uint64_t P9N2_PHB_5_PHB4_SCOM_UV_SEC_EXCL = 0x0F010984ull;
+
+
+static const uint64_t P9N2_PHB_PHB4_SCOM_UV_SEC_INCL_CMP = 0x0D010906ull;
+
+static const uint64_t P9N2_PHB_0_PHB4_SCOM_UV_SEC_INCL_CMP = 0x0D010906ull;
+
+static const uint64_t P9N2_PHB_1_PHB4_SCOM_UV_SEC_INCL_CMP = 0x0E010906ull;
+
+static const uint64_t P9N2_PHB_2_PHB4_SCOM_UV_SEC_INCL_CMP = 0x0E010946ull;
+
+static const uint64_t P9N2_PHB_3_PHB4_SCOM_UV_SEC_INCL_CMP = 0x0F010906ull;
+
+static const uint64_t P9N2_PHB_4_PHB4_SCOM_UV_SEC_INCL_CMP = 0x0F010946ull;
+
+static const uint64_t P9N2_PHB_5_PHB4_SCOM_UV_SEC_INCL_CMP = 0x0F010986ull;
+
+
+static const uint64_t P9N2_PHB_PHB4_SCOM_UV_SEC_INCL_MSK = 0x0D010907ull;
+
+static const uint64_t P9N2_PHB_0_PHB4_SCOM_UV_SEC_INCL_MSK = 0x0D010907ull;
+
+static const uint64_t P9N2_PHB_1_PHB4_SCOM_UV_SEC_INCL_MSK = 0x0E010907ull;
+
+static const uint64_t P9N2_PHB_2_PHB4_SCOM_UV_SEC_INCL_MSK = 0x0E010947ull;
+
+static const uint64_t P9N2_PHB_3_PHB4_SCOM_UV_SEC_INCL_MSK = 0x0F010907ull;
+
+static const uint64_t P9N2_PHB_4_PHB4_SCOM_UV_SEC_INCL_MSK = 0x0F010947ull;
+
+static const uint64_t P9N2_PHB_5_PHB4_SCOM_UV_SEC_INCL_MSK = 0x0F010987ull;
+
+
+static const uint64_t P9N2_PEC_0_STACK0_PHBBAR_REG = 0x04010C52ull;
+
+static const uint64_t P9N2_PEC_1_STACK0_PHBBAR_REG = 0x04011052ull;
+
+static const uint64_t P9N2_PEC_1_STACK1_PHBBAR_REG = 0x04011092ull;
+
+static const uint64_t P9N2_PEC_1_STACK2_PHBBAR_REG = 0x040110D2ull;
+
+static const uint64_t P9N2_PEC_2_STACK0_PHBBAR_REG = 0x04011452ull;
+
+static const uint64_t P9N2_PEC_2_STACK1_PHBBAR_REG = 0x04011492ull;
+
+static const uint64_t P9N2_PEC_2_STACK2_PHBBAR_REG = 0x040114D2ull;
+
+static const uint64_t P9N2_PEC_STACK0_PHBBAR_REG = 0x04010C52ull;
+
+static const uint64_t P9N2_PHB_PHBBAR_REG = 0x04010C52ull;
+
+static const uint64_t P9N2_PHB_0_PHBBAR_REG = 0x04010C52ull;
+
+static const uint64_t P9N2_PHB_1_PHBBAR_REG = 0x04011052ull;
+
+static const uint64_t P9N2_PHB_2_PHBBAR_REG = 0x04011092ull;
+
+static const uint64_t P9N2_PHB_3_PHBBAR_REG = 0x04011452ull;
+
+static const uint64_t P9N2_PHB_4_PHBBAR_REG = 0x04011492ull;
+
+static const uint64_t P9N2_PHB_5_PHBBAR_REG = 0x040114D2ull;
+
+
+static const uint64_t P9N2_PHB_PHBRESET_REG = 0x0D01084Aull;
+
+static const uint64_t P9N2_PHB_0_PHBRESET_REG = 0x0D01084Aull;
+
+static const uint64_t P9N2_PHB_1_PHBRESET_REG = 0x0E01084Aull;
+
+static const uint64_t P9N2_PHB_2_PHBRESET_REG = 0x0E01088Aull;
+
+static const uint64_t P9N2_PHB_3_PHBRESET_REG = 0x0F01084Aull;
+
+static const uint64_t P9N2_PHB_4_PHBRESET_REG = 0x0F01088Aull;
+
+static const uint64_t P9N2_PHB_5_PHBRESET_REG = 0x0F0108CAull;
+
+
+static const uint64_t P9N2_PU_NPU0_CTL_PHY_BAR = 0x05011096ull;
+
+static const uint64_t P9N2_PU_NPU2_CTL_PHY_BAR = 0x05011296ull;
+
+static const uint64_t P9N2_PU_NPU0_SM0_PHY_BAR = 0x05011006ull;
+
+static const uint64_t P9N2_PU_NPU0_SM1_PHY_BAR = 0x05011036ull;
+
+static const uint64_t P9N2_PU_NPU0_SM3_PHY_BAR = 0x05011066ull;
+
+static const uint64_t P9N2_PU_NPU2_SM0_PHY_BAR = 0x05011206ull;
+
+static const uint64_t P9N2_PU_NPU2_SM1_PHY_BAR = 0x05011236ull;
+
+static const uint64_t P9N2_PU_NPU2_SM3_PHY_BAR = 0x05011266ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_CTL_PHY_BAR = 0x05011496ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM0_PHY_BAR = 0x05011406ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM1_PHY_BAR = 0x05011436ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM3_PHY_BAR = 0x05011466ull;
+
+
+static const uint64_t P9N2_PU_PIBI2CM_ATOMIC_LOCK_REG_B = 0x000A03FFull;
+
+
+static const uint64_t P9N2_PU_PIBI2CM_ATOMIC_LOCK_REG_C = 0x000A13FFull;
+
+
+static const uint64_t P9N2_PU_PIBI2CM_ATOMIC_LOCK_REG_D = 0x000A23FFull;
+
+
+static const uint64_t P9N2_PU_PIBI2CM_ATOMIC_LOCK_REG_E = 0x000A33FFull;
+
+
+static const uint64_t P9N2_PU_PIBI2CM_PROTECT_MODE_REG_B = 0x000A03FEull;
+
+
+static const uint64_t P9N2_PU_PIBI2CM_PROTECT_MODE_REG_C = 0x000A13FEull;
+
+
+static const uint64_t P9N2_PU_PIBI2CM_PROTECT_MODE_REG_D = 0x000A23FEull;
+
+
+static const uint64_t P9N2_PU_PIBI2CM_PROTECT_MODE_REG_E = 0x000A33FEull;
+
+
+static const uint64_t P9N2_PU_PIBMEM_ADDRESS_REGISTER = 0x00088001ull;
+
+
+static const uint64_t P9N2_PU_PIBMEM_ADDRESS_REGISTER_FA = 0x00088007ull;
+
+
+static const uint64_t P9N2_PU_PIBMEM_CONTROL_REGISTER = 0x00088000ull;
+
+
+static const uint64_t P9N2_PU_PIBMEM_REPAIR_REGISTER_0 = 0x0008800Bull;
+
+
+static const uint64_t P9N2_PU_PIBMEM_REPAIR_REGISTER_1 = 0x0008800Cull;
+
+
+static const uint64_t P9N2_PU_PIBMEM_REPAIR_REGISTER_2 = 0x0008800Dull;
+
+
+static const uint64_t P9N2_PU_PIBMEM_REPAIR_REGISTER_3 = 0x0008800Eull;
+
+
+static const uint64_t P9N2_PU_PIBMEM_RESET_REGISTER = 0x00088006ull;
+
+
+static const uint64_t P9N2_PU_PIBMEM_STATUS_REG = 0x00088005ull;
+
+
+static const uint64_t P9N2_PU_PIB_CMD_REG = 0x00090031ull;
+
+
+static const uint64_t P9N2_PU_PIB_DATA_REG = 0x00090032ull;
+
+
+static const uint64_t P9N2_PU_PIB_RESET_REG = 0x00090033ull;
+
+
+static const uint64_t P9N2_PEC_PLL_LOCK_REG = 0x0D0F0019ull;
+
+static const uint64_t P9N2_PEC_0_PLL_LOCK_REG = 0x0D0F0019ull;
+
+static const uint64_t P9N2_PEC_1_PLL_LOCK_REG = 0x0E0F0019ull;
+
+static const uint64_t P9N2_PEC_2_PLL_LOCK_REG = 0x0F0F0019ull;
+
+
+static const uint64_t P9N2_PEC_PMONCTL_REG = 0x04010C04ull;
+
+static const uint64_t P9N2_PEC_0_PMONCTL_REG = 0x04010C04ull;
+
+static const uint64_t P9N2_PEC_1_PMONCTL_REG = 0x04011004ull;
+
+static const uint64_t P9N2_PEC_2_PMONCTL_REG = 0x04011404ull;
+
+
+static const uint64_t P9N2_CAPP_PMU_CNTRA_CFG = 0x02010814ull;
+
+static const uint64_t P9N2_CAPP_0_PMU_CNTRA_CFG = 0x02010814ull;
+
+static const uint64_t P9N2_CAPP_1_PMU_CNTRA_CFG = 0x04010814ull;
+
+
+static const uint64_t P9N2_CAPP_PMU_CNTRA_REG = 0x02010815ull;
+
+static const uint64_t P9N2_CAPP_0_PMU_CNTRA_REG = 0x02010815ull;
+
+static const uint64_t P9N2_CAPP_1_PMU_CNTRA_REG = 0x04010815ull;
+
+
+static const uint64_t P9N2_CAPP_PMU_CNTRB_CFG = 0x02010824ull;
+
+static const uint64_t P9N2_CAPP_0_PMU_CNTRB_CFG = 0x02010824ull;
+
+static const uint64_t P9N2_CAPP_1_PMU_CNTRB_CFG = 0x04010824ull;
+
+
+static const uint64_t P9N2_CAPP_PMU_CNTRB_REG = 0x02010825ull;
+
+static const uint64_t P9N2_CAPP_0_PMU_CNTRB_REG = 0x02010825ull;
+
+static const uint64_t P9N2_CAPP_1_PMU_CNTRB_REG = 0x04010825ull;
+
+
+static const uint64_t P9N2_PU_NPU_CTL_PMU_CONTROL0 = 0x05011382ull;
+
+static const uint64_t P9N2_PU_NPU_NTL0_PMU_CONTROL0 = 0x050113C9ull;
+
+static const uint64_t P9N2_PU_NPU_SM2_PMU_CONTROL0 = 0x05011352ull;
+
+static const uint64_t P9N2__CTL_PMU_CONTROL0 = 0x05011582ull;
+
+static const uint64_t P9N2__NTL0_PMU_CONTROL0 = 0x050115C9ull;
+
+static const uint64_t P9N2__SM2_PMU_CONTROL0 = 0x05011552ull;
+
+
+static const uint64_t P9N2_PU_NPU_CTL_PMU_CONTROL1 = 0x05011383ull;
+
+static const uint64_t P9N2_PU_NPU_SM2_PMU_CONTROL1 = 0x05011353ull;
+
+static const uint64_t P9N2__CTL_PMU_CONTROL1 = 0x05011583ull;
+
+static const uint64_t P9N2__SM2_PMU_CONTROL1 = 0x05011553ull;
+
+
+static const uint64_t P9N2_PU_NPU_CTL_PMU_CONTROL2 = 0x05011384ull;
+
+static const uint64_t P9N2_PU_NPU_SM2_PMU_CONTROL2 = 0x05011354ull;
+
+static const uint64_t P9N2__CTL_PMU_CONTROL2 = 0x05011584ull;
+
+static const uint64_t P9N2__SM2_PMU_CONTROL2 = 0x05011554ull;
+
+
+static const uint64_t P9N2_PU_NPU_CTL_PMU_COUNT = 0x05011385ull;
+
+static const uint64_t P9N2_PU_NPU_NTL0_PMU_COUNT = 0x050113CAull;
+
+static const uint64_t P9N2_PU_NPU_SM2_PMU_COUNT = 0x05011355ull;
+
+static const uint64_t P9N2__CTL_PMU_COUNT = 0x05011585ull;
+
+static const uint64_t P9N2__NTL0_PMU_COUNT = 0x050115CAull;
+
+static const uint64_t P9N2__SM2_PMU_COUNT = 0x05011555ull;
+
+
+static const uint64_t P9N2_PU_PPE_FIR_ACTION0_REG = 0x0C011046ull;
+//DUPS: 0C011046,
+
+static const uint64_t P9N2_PU_PPE_FIR_ACTION1_REG = 0x0C011047ull;
+//DUPS: 0C011047,
+
+static const uint64_t P9N2_PU_PPE_FIR_MASK_REG = 0x0C011043ull;
+//DUPS: 0C011043,
+static const uint64_t P9N2_PU_PPE_FIR_MASK_REG_AND = 0x0C011044ull;
+//DUPS: 0C011044,
+static const uint64_t P9N2_PU_PPE_FIR_MASK_REG_OR = 0x0C011045ull;
+//DUPS: 0C011045,
+
+static const uint64_t P9N2_PU_PPE_FIR_REG = 0x0C011040ull;
+//DUPS: 0C011040,
+static const uint64_t P9N2_PU_PPE_FIR_REG_AND = 0x0C011041ull;
+//DUPS: 0C011041,
+static const uint64_t P9N2_PU_PPE_FIR_REG_OR = 0x0C011042ull;
+//DUPS: 0C011042,
+
+static const uint64_t P9N2_PU_PPE_FIR_WOF_REG = 0x0C011048ull;
+//DUPS: 0C011048,
+
+static const uint64_t P9N2_PU_PPE_XIDBGPRO = 0x000E0005ull;
+//DUPS: 05012415, 09011055, 0C011055,
+
+static const uint64_t P9N2_PU_PPE_XIRAMDBG = 0x000E0003ull;
+//DUPS: 05012413, 09011053, 0C011053,
+
+static const uint64_t P9N2_PU_PPE_XIRAMEDR = 0x000E0004ull;
+//DUPS: 05012414, 09011054, 0C011054,
+
+static const uint64_t P9N2_PU_PPE_XIRAMGA = 0x000E0002ull;
+//DUPS: 05012412, 09011052, 0C011052,
+
+static const uint64_t P9N2_PU_PPE_XIRAMRA = 0x000E0001ull;
+//DUPS: 05012411, 09011051, 0C011051,
+
+static const uint64_t P9N2_PU_PPE_XIXCR = 0x000E0000ull;
+//DUPS: 05012410, 09011050, 0C011050,
+
+static const uint64_t P9N2_PU_NPU1_SM1_PRB_HA_PTR = 0x05011121ull;
+
+static const uint64_t P9N2_PU_NPU1_SM2_PRB_HA_PTR = 0x05011141ull;
+
+static const uint64_t P9N2_PU_NPU_SM1_PRB_HA_PTR = 0x05011321ull;
+
+static const uint64_t P9N2_PU_NPU_SM2_PRB_HA_PTR = 0x05011341ull;
+
+static const uint64_t P9N2__SM1_PRB_HA_PTR = 0x05011521ull;
+
+static const uint64_t P9N2__SM2_PRB_HA_PTR = 0x05011541ull;
+
+
+static const uint64_t P9N2_PEC_PRDSTKOVR_REG = 0x0D010802ull;
+
+static const uint64_t P9N2_PEC_0_PRDSTKOVR_REG = 0x0D010802ull;
+
+static const uint64_t P9N2_PEC_1_PRDSTKOVR_REG = 0x0E010802ull;
+
+static const uint64_t P9N2_PEC_2_PRDSTKOVR_REG = 0x0F010802ull;
+
+
+static const uint64_t P9N2_PEC_PREDV_REG = 0x04010C06ull;
+
+static const uint64_t P9N2_PEC_0_PREDV_REG = 0x04010C06ull;
+
+static const uint64_t P9N2_PEC_1_PREDV_REG = 0x04011006ull;
+
+static const uint64_t P9N2_PEC_2_PREDV_REG = 0x04011406ull;
+
+
+static const uint64_t P9N2_PEC_PRE_COUNTER_REG = 0x0D0F0028ull;
+
+static const uint64_t P9N2_PEC_0_PRE_COUNTER_REG = 0x0D0F0028ull;
+
+static const uint64_t P9N2_PEC_1_PRE_COUNTER_REG = 0x0E0F0028ull;
+
+static const uint64_t P9N2_PEC_2_PRE_COUNTER_REG = 0x0F0F0028ull;
+
+
+static const uint64_t P9N2_PU_PRGM_REGISTER = 0x00010009ull;
+
+
+static const uint64_t P9N2_PEC_PRIMARY_ADDRESS_REG = 0x0D0F0000ull;
+
+static const uint64_t P9N2_PEC_0_PRIMARY_ADDRESS_REG = 0x0D0F0000ull;
+
+static const uint64_t P9N2_PEC_1_PRIMARY_ADDRESS_REG = 0x0E0F0000ull;
+
+static const uint64_t P9N2_PEC_2_PRIMARY_ADDRESS_REG = 0x0F0F0000ull;
+
+
+static const uint64_t P9N2_PU_NPU1_SM1_PRI_CONFIG = 0x05011126ull;
+
+static const uint64_t P9N2_PU_NPU1_SM2_PRI_CONFIG = 0x05011146ull;
+
+static const uint64_t P9N2_PU_NPU_SM1_PRI_CONFIG = 0x05011326ull;
+
+static const uint64_t P9N2_PU_NPU_SM2_PRI_CONFIG = 0x05011346ull;
+
+static const uint64_t P9N2__SM1_PRI_CONFIG = 0x05011526ull;
+
+static const uint64_t P9N2__SM2_PRI_CONFIG = 0x05011546ull;
+
+
+static const uint64_t P9N2_PU_PROBE_PROTECT_STATUS = 0x0001000Aull;
+
+
+static const uint64_t P9N2_PEC_PROTECT_MODE_REG = 0x0D0F03FEull;
+
+static const uint64_t P9N2_PEC_0_PROTECT_MODE_REG = 0x0D0F03FEull;
+
+static const uint64_t P9N2_PEC_1_PROTECT_MODE_REG = 0x0E0F03FEull;
+
+static const uint64_t P9N2_PEC_2_PROTECT_MODE_REG = 0x0F0F03FEull;
+
+
+static const uint64_t P9N2_PU_PRV_MISC_PPE = 0xC0002000ull;
+
+static const uint64_t P9N2_PU_PRV_MISC_PPE1 = 0xC0002010ull;
+
+static const uint64_t P9N2_PU_PRV_MISC_PPE2 = 0xC0002018ull;
+
+
+static const uint64_t P9N2_PU_PSCOM_ERROR_MASK = 0x06010002ull;
+
+
+static const uint64_t P9N2_PEC_PSCOM_ERROR_MASK = 0x0D010002ull;
+
+static const uint64_t P9N2_PEC_0_PSCOM_ERROR_MASK = 0x0D010002ull;
+
+static const uint64_t P9N2_PEC_1_PSCOM_ERROR_MASK = 0x0E010002ull;
+
+static const uint64_t P9N2_PEC_2_PSCOM_ERROR_MASK = 0x0F010002ull;
+
+
+static const uint64_t P9N2_PU_N0_PSCOM_ERROR_MASK = 0x02010002ull;
+
+static const uint64_t P9N2_PU_N1_PSCOM_ERROR_MASK = 0x03010002ull;
+
+static const uint64_t P9N2_PU_N2_PSCOM_ERROR_MASK = 0x04010002ull;
+
+static const uint64_t P9N2_PU_N3_PSCOM_ERROR_MASK = 0x05010002ull;
+
+
+static const uint64_t P9N2_PU_PSCOM_MODE_REG = 0x06010000ull;
+
+
+static const uint64_t P9N2_PEC_PSCOM_MODE_REG = 0x0D010000ull;
+
+static const uint64_t P9N2_PEC_0_PSCOM_MODE_REG = 0x0D010000ull;
+
+static const uint64_t P9N2_PEC_1_PSCOM_MODE_REG = 0x0E010000ull;
+
+static const uint64_t P9N2_PEC_2_PSCOM_MODE_REG = 0x0F010000ull;
+
+
+static const uint64_t P9N2_PU_N0_PSCOM_MODE_REG = 0x02010000ull;
+
+static const uint64_t P9N2_PU_N1_PSCOM_MODE_REG = 0x03010000ull;
+
+static const uint64_t P9N2_PU_N2_PSCOM_MODE_REG = 0x04010000ull;
+
+static const uint64_t P9N2_PU_N3_PSCOM_MODE_REG = 0x05010000ull;
+
+
+static const uint64_t P9N2_PU_PSCOM_STATUS_ERROR_REG = 0x06010001ull;
+
+
+static const uint64_t P9N2_PEC_PSCOM_STATUS_ERROR_REG = 0x0D010001ull;
+
+static const uint64_t P9N2_PEC_0_PSCOM_STATUS_ERROR_REG = 0x0D010001ull;
+
+static const uint64_t P9N2_PEC_1_PSCOM_STATUS_ERROR_REG = 0x0E010001ull;
+
+static const uint64_t P9N2_PEC_2_PSCOM_STATUS_ERROR_REG = 0x0F010001ull;
+
+
+static const uint64_t P9N2_PU_N0_PSCOM_STATUS_ERROR_REG = 0x02010001ull;
+
+static const uint64_t P9N2_PU_N1_PSCOM_STATUS_ERROR_REG = 0x03010001ull;
+
+static const uint64_t P9N2_PU_N2_PSCOM_STATUS_ERROR_REG = 0x04010001ull;
+
+static const uint64_t P9N2_PU_N3_PSCOM_STATUS_ERROR_REG = 0x05010001ull;
+
+
+static const uint64_t P9N2_PU_PSIHB_DEBUG_REG = 0x05012911ull;
+
+
+static const uint64_t P9N2_PU_PSIHB_ERROR_MASK_REG = 0x0501290Full;
+
+
+static const uint64_t P9N2_PU_PSIHB_FIR_ACTION0_REG = 0x05012906ull;
+
+
+static const uint64_t P9N2_PU_PSIHB_FIR_ACTION1_REG = 0x05012907ull;
+
+
+static const uint64_t P9N2_PU_PSIHB_FIR_MASK_REG = 0x05012903ull;
+
+static const uint64_t P9N2_PU_PSIHB_FIR_MASK_REG_AND = 0x05012904ull;
+
+static const uint64_t P9N2_PU_PSIHB_FIR_MASK_REG_OR = 0x05012905ull;
+
+
+static const uint64_t P9N2_PU_PSIHB_FIR_REG = 0x05012900ull;
+
+static const uint64_t P9N2_PU_PSIHB_FIR_REG_AND = 0x05012901ull;
+
+static const uint64_t P9N2_PU_PSIHB_FIR_REG_OR = 0x05012902ull;
+
+
+static const uint64_t P9N2_PU_PSIHB_INTERRUPT_CONTROL = 0x05012915ull;
+
+
+static const uint64_t P9N2_PU_PSIHB_INTERRUPT_LEVEL = 0x05012919ull;
+
+
+static const uint64_t P9N2_PU_PSIHB_INTERRUPT_STATUS = 0x0501291Aull;
+
+
+static const uint64_t P9N2_PU_PSIHB_STATUS_CTL_REG_SCOM = 0x0501290Eull;
+
+static const uint64_t P9N2_PU_PSIHB_STATUS_CTL_REG_SCOM1 = 0x05012912ull;
+
+static const uint64_t P9N2_PU_PSIHB_STATUS_CTL_REG_SCOM2 = 0x05012913ull;
+
+
+static const uint64_t P9N2_PU_PSI_BRIDGE_BAR_REG = 0x0501290Aull;
+
+
+static const uint64_t P9N2_PU_PSI_BRIDGE_FSP_BAR_REG = 0x0501290Bull;
+
+
+static const uint64_t P9N2_PU_PSI_FSP_MMR_REG = 0x0501290Cull;
+
+
+static const uint64_t P9N2_PU_PSI_TCE_ADDR_REG = 0x05012B44ull;
+
+
+static const uint64_t P9N2_CAPP_PSLTTMAP0 = 0x0201082Dull;
+
+static const uint64_t P9N2_CAPP_0_PSLTTMAP0 = 0x0201082Dull;
+
+static const uint64_t P9N2_CAPP_1_PSLTTMAP0 = 0x0401082Dull;
+
+
+static const uint64_t P9N2_CAPP_PSLTTMAP1 = 0x0201082Eull;
+
+static const uint64_t P9N2_CAPP_0_PSLTTMAP1 = 0x0201082Eull;
+
+static const uint64_t P9N2_CAPP_1_PSLTTMAP1 = 0x0401082Eull;
+
+
+static const uint64_t P9N2_CAPP_PSLTTMAP2 = 0x0201082Full;
+
+static const uint64_t P9N2_CAPP_0_PSLTTMAP2 = 0x0201082Full;
+
+static const uint64_t P9N2_CAPP_1_PSLTTMAP2 = 0x0401082Full;
+
+
+static const uint64_t P9N2_CAPP_PSLTTMAP3 = 0x02010830ull;
+
+static const uint64_t P9N2_CAPP_0_PSLTTMAP3 = 0x02010830ull;
+
+static const uint64_t P9N2_CAPP_1_PSLTTMAP3 = 0x04010830ull;
+
+
+static const uint64_t P9N2_PU_PSL_DAR_AN = 0x050115A9ull;
+
+static const uint64_t P9N2_PU_NPU_PSL_DAR_AN = 0x050113A9ull;
+
+static const uint64_t P9N2_PU_NPU_SM3_PSL_DAR_AN = 0x05011379ull;
+
+static const uint64_t P9N2__SM3_PSL_DAR_AN = 0x05011579ull;
+
+
+static const uint64_t P9N2_PU_PSL_DSISR_AN = 0x050115A8ull;
+
+static const uint64_t P9N2_PU_NPU_PSL_DSISR_AN = 0x050113A8ull;
+
+static const uint64_t P9N2_PU_NPU_SM3_PSL_DSISR_AN = 0x05011378ull;
+
+static const uint64_t P9N2__SM3_PSL_DSISR_AN = 0x05011578ull;
+
+
+static const uint64_t P9N2_PU_NPU_DAT_PSL_LLCMD_A0 = 0x050113B1ull;
+
+static const uint64_t P9N2__DAT_PSL_LLCMD_A0 = 0x050115B1ull;
+
+
+static const uint64_t P9N2_PU_PSL_PEHANDLE_AN = 0x050115ABull;
+
+static const uint64_t P9N2_PU_NPU_PSL_PEHANDLE_AN = 0x050113ABull;
+
+static const uint64_t P9N2_PU_NPU_SM3_PSL_PEHANDLE_AN = 0x0501137Bull;
+
+static const uint64_t P9N2__SM3_PSL_PEHANDLE_AN = 0x0501157Bull;
+
+
+static const uint64_t P9N2_PU_NPU_DAT_PSL_SCNTL_A0 = 0x050113B2ull;
+
+static const uint64_t P9N2__DAT_PSL_SCNTL_A0 = 0x050115B2ull;
+
+
+static const uint64_t P9N2_PU_NPU_DAT_PSL_SPAP_A0 = 0x050113B0ull;
+
+static const uint64_t P9N2__DAT_PSL_SPAP_A0 = 0x050115B0ull;
+
+
+static const uint64_t P9N2_PU_NPU_DAT_PSL_SPAP_A1 = 0x050113B3ull;
+
+static const uint64_t P9N2__DAT_PSL_SPAP_A1 = 0x050115B3ull;
+
+
+static const uint64_t P9N2_PU_PSL_TFC_AN = 0x050115AAull;
+
+static const uint64_t P9N2_PU_NPU_PSL_TFC_AN = 0x050113AAull;
+
+static const uint64_t P9N2_PU_NPU_SM3_PSL_TFC_AN = 0x0501137Aull;
+
+static const uint64_t P9N2__SM3_PSL_TFC_AN = 0x0501157Aull;
+
+
+static const uint64_t P9N2_PU_PSU_HOST_DOORBELL_REG = 0x000D0063ull;
+
+static const uint64_t P9N2_PU_PSU_HOST_DOORBELL_REG_AND = 0x000D0064ull;
+
+static const uint64_t P9N2_PU_PSU_HOST_DOORBELL_REG_OR = 0x000D0065ull;
+
+
+static const uint64_t P9N2_PU_PSU_HOST_SBE_MBOX0_REG = 0x000D0050ull;
+
+
+static const uint64_t P9N2_PU_PSU_HOST_SBE_MBOX1_REG = 0x000D0051ull;
+
+
+static const uint64_t P9N2_PU_PSU_HOST_SBE_MBOX2_REG = 0x000D0052ull;
+
+
+static const uint64_t P9N2_PU_PSU_HOST_SBE_MBOX3_REG = 0x000D0053ull;
+
+
+static const uint64_t P9N2_PU_PSU_HOST_SBE_MBOX4_REG = 0x000D0054ull;
+
+
+static const uint64_t P9N2_PU_PSU_HOST_SBE_MBOX5_REG = 0x000D0055ull;
+
+
+static const uint64_t P9N2_PU_PSU_HOST_SBE_MBOX6_REG = 0x000D0056ull;
+
+
+static const uint64_t P9N2_PU_PSU_HOST_SBE_MBOX7_REG = 0x000D0057ull;
+
+
+static const uint64_t P9N2_PU_PSU_INSTR0_ACTCYCLECNT_REG = 0x000D0023ull;
+
+
+static const uint64_t P9N2_PU_PSU_INSTR0_CYCLECNT_REG = 0x000D0022ull;
+
+
+static const uint64_t P9N2_PU_PSU_INSTR0_EVENTCNT_REG = 0x000D0024ull;
+
+
+static const uint64_t P9N2_PU_PSU_INSTR0_FILTER_REG = 0x000D0021ull;
+
+
+static const uint64_t P9N2_PU_PSU_INSTR0_MAXCYCLECNT_REG = 0x000D0025ull;
+
+
+static const uint64_t P9N2_PU_PSU_INSTR0_MINCYCLECNT_REG = 0x000D0026ull;
+
+
+static const uint64_t P9N2_PU_PSU_INSTR0_STOP_TIMER_REG = 0x000D0020ull;
+
+
+static const uint64_t P9N2_PU_PSU_INSTR1_ACTCYCLECNT_REG = 0x000D0033ull;
+
+
+static const uint64_t P9N2_PU_PSU_INSTR1_CYCLECNT_REG = 0x000D0032ull;
+
+
+static const uint64_t P9N2_PU_PSU_INSTR1_EVENTCNT_REG = 0x000D0034ull;
+
+
+static const uint64_t P9N2_PU_PSU_INSTR1_FILTER_REG = 0x000D0031ull;
+
+
+static const uint64_t P9N2_PU_PSU_INSTR1_MAXCYCLECNT_REG = 0x000D0035ull;
+
+
+static const uint64_t P9N2_PU_PSU_INSTR1_MINCYCLECNT_REG = 0x000D0036ull;
+
+
+static const uint64_t P9N2_PU_PSU_INSTR1_STOP_TIMER_REG = 0x000D0030ull;
+
+
+static const uint64_t P9N2_PU_PSU_INSTR2_ACTCYCLECNT_REG = 0x000D0043ull;
+
+
+static const uint64_t P9N2_PU_PSU_INSTR2_CYCLECNT_REG = 0x000D0042ull;
+
+
+static const uint64_t P9N2_PU_PSU_INSTR2_EVENTCNT_REG = 0x000D0044ull;
+
+
+static const uint64_t P9N2_PU_PSU_INSTR2_FILTER_REG = 0x000D0041ull;
+
+
+static const uint64_t P9N2_PU_PSU_INSTR2_MAXCYCLECNT_REG = 0x000D0045ull;
+
+
+static const uint64_t P9N2_PU_PSU_INSTR2_MINCYCLECNT_REG = 0x000D0046ull;
+
+
+static const uint64_t P9N2_PU_PSU_INSTR2_STOP_TIMER_REG = 0x000D0040ull;
+
+
+static const uint64_t P9N2_PU_PSU_INSTR_CTRL_STATUS_REG = 0x000D0010ull;
+
+
+static const uint64_t P9N2_PU_PSU_PIBHIST_2NDLAST_ADDR_TRACE_REG = 0x000D0005ull;
+
+
+static const uint64_t P9N2_PU_PSU_PIBHIST_2NDLAST_REQDATA_TRACE_REG = 0x000D0006ull;
+
+
+static const uint64_t P9N2_PU_PSU_PIBHIST_2NDLAST_RSPDATA_TRACE_REG = 0x000D0007ull;
+
+
+static const uint64_t P9N2_PU_PSU_PIBHIST_CTRL_STATUS_REG = 0x000D0000ull;
+
+
+static const uint64_t P9N2_PU_PSU_PIBHIST_FILTER_REG = 0x000D0001ull;
+
+
+static const uint64_t P9N2_PU_PSU_PIBHIST_LAST_ADDR_TRACE_REG = 0x000D0002ull;
+
+
+static const uint64_t P9N2_PU_PSU_PIBHIST_LAST_REQDATA_TRACE_REG = 0x000D0003ull;
+
+
+static const uint64_t P9N2_PU_PSU_PIBHIST_LAST_RSPDATA_TRACE_REG = 0x000D0004ull;
+
+
+static const uint64_t P9N2_PU_PSU_SBE_DOORBELL_REG = 0x000D0060ull;
+
+static const uint64_t P9N2_PU_PSU_SBE_DOORBELL_REG_AND = 0x000D0061ull;
+
+static const uint64_t P9N2_PU_PSU_SBE_DOORBELL_REG_OR = 0x000D0062ull;
+
+
+static const uint64_t P9N2_PU_RCV_ERRLOG0_REG = 0x00090022ull;
+
+
+static const uint64_t P9N2_PU_RCV_ERRLOG1_REG = 0x00090023ull;
+
+
+static const uint64_t P9N2_PEC_RECOV_INTERRUPT_REG = 0x0D0F001Bull;
+
+static const uint64_t P9N2_PEC_0_RECOV_INTERRUPT_REG = 0x0D0F001Bull;
+
+static const uint64_t P9N2_PEC_1_RECOV_INTERRUPT_REG = 0x0E0F001Bull;
+
+static const uint64_t P9N2_PEC_2_RECOV_INTERRUPT_REG = 0x0F0F001Bull;
+
+
+static const uint64_t P9N2_NV_1_REM0 = 0x050110FDull;
+
+static const uint64_t P9N2_NV_5_REM0 = 0x050114FDull;
+
+static const uint64_t P9N2_PU_NPU2_NTL1_REM0 = 0x050112FDull;
+
+
+static const uint64_t P9N2_NV_1_REM1 = 0x050110FEull;
+
+static const uint64_t P9N2_NV_5_REM1 = 0x050114FEull;
+
+static const uint64_t P9N2_PU_NPU2_NTL1_REM1 = 0x050112FEull;
+
+
+static const uint64_t P9N2_PHB_RESERVED1_REG = 0x0D01084Cull;
+
+static const uint64_t P9N2_PHB_0_RESERVED1_REG = 0x0D01084Cull;
+
+static const uint64_t P9N2_PHB_1_RESERVED1_REG = 0x0E01084Cull;
+
+static const uint64_t P9N2_PHB_2_RESERVED1_REG = 0x0E01088Cull;
+
+static const uint64_t P9N2_PHB_3_RESERVED1_REG = 0x0F01084Cull;
+
+static const uint64_t P9N2_PHB_4_RESERVED1_REG = 0x0F01088Cull;
+
+static const uint64_t P9N2_PHB_5_RESERVED1_REG = 0x0F0108CCull;
+
+
+static const uint64_t P9N2_PU_RESET_REGISTER = 0x00010001ull;
+
+
+static const uint64_t P9N2_PU_RESET_REGISTER_B = 0x000A0001ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+
+static const uint64_t P9N2_PU_RESET_REGISTER_C = 0x000A1001ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+
+static const uint64_t P9N2_PU_RESET_REGISTER_D = 0x000A2001ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+
+static const uint64_t P9N2_PU_RESET_REGISTER_E = 0x000A3001ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+
+static const uint64_t P9N2_PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_B = 0x000A000Dull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+
+static const uint64_t P9N2_PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_C = 0x000A100Dull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+
+static const uint64_t P9N2_PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_D = 0x000A200Dull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+
+static const uint64_t P9N2_PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_E = 0x000A300Dull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+
+static const uint64_t P9N2_PEC_RFIR = 0x0D040001ull;
+
+static const uint64_t P9N2_PEC_0_RFIR = 0x0D040001ull;
+
+static const uint64_t P9N2_PEC_1_RFIR = 0x0E040001ull;
+
+static const uint64_t P9N2_PEC_2_RFIR = 0x0F040001ull;
+
+
+static const uint64_t P9N2_PU_RING_FENCE_MASK_LATCH_REG = 0x06010008ull;
+
+
+static const uint64_t P9N2_PEC_RING_FENCE_MASK_LATCH_REG = 0x0D010008ull;
+
+static const uint64_t P9N2_PEC_0_RING_FENCE_MASK_LATCH_REG = 0x0D010008ull;
+
+static const uint64_t P9N2_PEC_1_RING_FENCE_MASK_LATCH_REG = 0x0E010008ull;
+
+static const uint64_t P9N2_PEC_2_RING_FENCE_MASK_LATCH_REG = 0x0F010008ull;
+
+
+static const uint64_t P9N2_PU_N0_RING_FENCE_MASK_LATCH_REG = 0x02010008ull;
+
+static const uint64_t P9N2_PU_N1_RING_FENCE_MASK_LATCH_REG = 0x03010008ull;
+
+static const uint64_t P9N2_PU_N2_RING_FENCE_MASK_LATCH_REG = 0x04010008ull;
+
+static const uint64_t P9N2_PU_N3_RING_FENCE_MASK_LATCH_REG = 0x05010008ull;
+
+
+static const uint64_t P9N2__CTL_RLX_CONFIG = 0x05011681ull;
+
+
+static const uint64_t P9N2_PU_RNG_FAILED_INT = 0x020110E7ull;
+
+
+static const uint64_t P9N2_PU_NPU1_SM1_RSP_DA_PTR = 0x05011125ull;
+
+static const uint64_t P9N2_PU_NPU1_SM2_RSP_DA_PTR = 0x05011145ull;
+
+static const uint64_t P9N2_PU_NPU_SM1_RSP_DA_PTR = 0x05011325ull;
+
+static const uint64_t P9N2_PU_NPU_SM2_RSP_DA_PTR = 0x05011345ull;
+
+static const uint64_t P9N2__SM1_RSP_DA_PTR = 0x05011525ull;
+
+static const uint64_t P9N2__SM2_RSP_DA_PTR = 0x05011545ull;
+
+
+static const uint64_t P9N2_PU_NPU1_SM1_RSP_HA_PTR = 0x05011123ull;
+
+static const uint64_t P9N2_PU_NPU1_SM2_RSP_HA_PTR = 0x05011143ull;
+
+static const uint64_t P9N2_PU_NPU_SM1_RSP_HA_PTR = 0x05011323ull;
+
+static const uint64_t P9N2_PU_NPU_SM2_RSP_HA_PTR = 0x05011343ull;
+
+static const uint64_t P9N2__SM1_RSP_HA_PTR = 0x05011523ull;
+
+static const uint64_t P9N2__SM2_RSP_HA_PTR = 0x05011543ull;
+
+
+static const uint64_t P9N2_PU_RX_CH_FSM_REG = 0x0501280Dull;
+
+
+static const uint64_t P9N2_PU_RX_CH_INTADDR_REG = 0x05012818ull;
+
+
+static const uint64_t P9N2_PU_RX_CH_MISC_REG = 0x0501281Bull;
+
+
+static const uint64_t P9N2_PU_RX_CTRL_STAT_REG = 0x05012808ull;
+
+
+static const uint64_t P9N2_PU_RX_DBFF_REG0 = 0x05012819ull;
+
+
+static const uint64_t P9N2_PU_RX_DBFF_REG1 = 0x0501281Aull;
+
+
+static const uint64_t P9N2_PU_RX_DF_FSM_REG = 0x0501280Eull;
+
+
+static const uint64_t P9N2_PU_RX_ERROR_REG_WCLEAR = 0x0501280Aull;
+
+static const uint64_t P9N2_PU_RX_ERROR_REG_OR = 0x0501280Cull;
+
+
+static const uint64_t P9N2_PU_RX_ERR_MODE = 0x0501280Full;
+
+
+static const uint64_t P9N2_PU_RX_MASK_REG = 0x0501280Bull;
+
+
+static const uint64_t P9N2_PU_RX_PSI_CNTL = 0x04011820ull;
+
+
+static const uint64_t P9N2_PU_RX_PSI_MODE = 0x04011821ull;
+
+
+static const uint64_t P9N2_PU_RX_PSI_STATUS = 0x04011822ull;
+
+
+static const uint64_t P9N2_PEC_SCAN32 = 0x0D038000ull;
+
+static const uint64_t P9N2_PEC_0_SCAN32 = 0x0D038000ull;
+
+static const uint64_t P9N2_PEC_1_SCAN32 = 0x0E038000ull;
+
+static const uint64_t P9N2_PEC_2_SCAN32 = 0x0F038000ull;
+
+
+static const uint64_t P9N2_PEC_SCAN_CAPTUREDR = 0x0D03C000ull;
+
+static const uint64_t P9N2_PEC_0_SCAN_CAPTUREDR = 0x0D03C000ull;
+
+static const uint64_t P9N2_PEC_1_SCAN_CAPTUREDR = 0x0E03C000ull;
+
+static const uint64_t P9N2_PEC_2_SCAN_CAPTUREDR = 0x0F03C000ull;
+
+
+static const uint64_t P9N2_PEC_SCAN_REGION_TYPE = 0x0D030005ull;
+
+static const uint64_t P9N2_PEC_0_SCAN_REGION_TYPE = 0x0D030005ull;
+
+static const uint64_t P9N2_PEC_1_SCAN_REGION_TYPE = 0x0E030005ull;
+
+static const uint64_t P9N2_PEC_2_SCAN_REGION_TYPE = 0x0F030005ull;
+
+
+static const uint64_t P9N2_PEC_SCOM0X00 = 0x80000B400D010C3Full;
+//DUPS: 800005000D010C3F, 800004000D010C3F, 800000800D010C3F, 800005400D010C3F, 80000A000D010C3F, 800000C00D010C3F, 800001800D010C3F, 800001C00D010C3F, 800003C00D010C3F, 800003800D010C3F, 800002C00D010C3F, 800002800D010C3F, 800009C00D010C3F, 800009800D010C3F, 800008C00D010C3F, 800008800D010C3F, 80000BC00D010C3F, 80000B800D010C3F, 80000AC00D010C3F, 80000A800D010C3F, 800000000D010C3F, 800000400D010C3F, 800001000D010C3F, 800001400D010C3F, 800002000D010C3F, 800002400D010C3F, 800003000D010C3F, 800003400D010C3F, 800008000D010C3F, 800008400D010C3F, 800009000D010C3F, 800009400D010C3F, 80000A400D010C3F, 80000B000D010C3F,
+static const uint64_t P9N2_PEC_0_SCOM0X00 = 0x80000B400D010C3Full;
+//DUPS: 800005000D010C3F, 800004000D010C3F, 800000800D010C3F, 800005400D010C3F, 80000A000D010C3F, 800000C00D010C3F, 800001800D010C3F, 800001C00D010C3F, 800003C00D010C3F, 800003800D010C3F, 800002C00D010C3F, 800002800D010C3F, 800009C00D010C3F, 800009800D010C3F, 800008C00D010C3F, 800008800D010C3F, 80000BC00D010C3F, 80000B800D010C3F, 80000AC00D010C3F, 80000A800D010C3F, 800000000D010C3F, 800000400D010C3F, 800001000D010C3F, 800001400D010C3F, 800002000D010C3F, 800002400D010C3F, 800003000D010C3F, 800003400D010C3F, 800008000D010C3F, 800008400D010C3F, 800009000D010C3F, 800009400D010C3F, 80000A400D010C3F, 80000B000D010C3F,
+static const uint64_t P9N2_PEC_1_SCOM0X00 = 0x80000B400E010C3Full;
+//DUPS: 800005000E010C3F, 800004000E010C3F, 800000800E010C3F, 800005400E010C3F, 80000A000E010C3F, 800000C00E010C3F, 800001800E010C3F, 800001C00E010C3F, 800003C00E010C3F, 800003800E010C3F, 800002C00E010C3F, 800002800E010C3F, 800009C00E010C3F, 800009800E010C3F, 800008C00E010C3F, 800008800E010C3F, 80000BC00E010C3F, 80000B800E010C3F, 80000AC00E010C3F, 80000A800E010C3F, 800000000E010C3F, 800000400E010C3F, 800001000E010C3F, 800001400E010C3F, 800002000E010C3F, 800002400E010C3F, 800003000E010C3F, 800003400E010C3F, 800008000E010C3F, 800008400E010C3F, 800009000E010C3F, 800009400E010C3F, 80000A400E010C3F, 80000B000E010C3F,
+static const uint64_t P9N2_PEC_2_SCOM0X00 = 0x80000B400F010C3Full;
+//DUPS: 800005000F010C3F, 800004000F010C3F, 800000800F010C3F, 800005400F010C3F, 80000A000F010C3F, 800000C00F010C3F, 800001800F010C3F, 800001C00F010C3F, 800003C00F010C3F, 800003800F010C3F, 800002C00F010C3F, 800002800F010C3F, 800009C00F010C3F, 800009800F010C3F, 800008C00F010C3F, 800008800F010C3F, 80000BC00F010C3F, 80000B800F010C3F, 80000AC00F010C3F, 80000A800F010C3F, 800000000F010C3F, 800000400F010C3F, 800001000F010C3F, 800001400F010C3F, 800002000F010C3F, 800002400F010C3F, 800003000F010C3F, 800003400F010C3F, 800008000F010C3F, 800008400F010C3F, 800009000F010C3F, 800009400F010C3F, 80000A400F010C3F, 80000B000F010C3F,
+
+static const uint64_t P9N2_PEC_SCOM0X01 = 0x80000B410D010C3Full;
+//DUPS: 800005010D010C3F, 800005410D010C3F, 80000A010D010C3F, 800000010D010C3F, 800000410D010C3F, 800001010D010C3F, 800001410D010C3F, 800002010D010C3F, 800002410D010C3F, 800003010D010C3F, 800003410D010C3F, 800008010D010C3F, 800008410D010C3F, 800009010D010C3F, 800009410D010C3F, 80000A410D010C3F, 80000B010D010C3F,
+static const uint64_t P9N2_PEC_0_SCOM0X01 = 0x80000B410D010C3Full;
+//DUPS: 800005010D010C3F, 800005410D010C3F, 80000A010D010C3F, 800000010D010C3F, 800000410D010C3F, 800001010D010C3F, 800001410D010C3F, 800002010D010C3F, 800002410D010C3F, 800003010D010C3F, 800003410D010C3F, 800008010D010C3F, 800008410D010C3F, 800009010D010C3F, 800009410D010C3F, 80000A410D010C3F, 80000B010D010C3F,
+static const uint64_t P9N2_PEC_1_SCOM0X01 = 0x80000B410E010C3Full;
+//DUPS: 800005010E010C3F, 800005410E010C3F, 80000A010E010C3F, 800000010E010C3F, 800000410E010C3F, 800001010E010C3F, 800001410E010C3F, 800002010E010C3F, 800002410E010C3F, 800003010E010C3F, 800003410E010C3F, 800008010E010C3F, 800008410E010C3F, 800009010E010C3F, 800009410E010C3F, 80000A410E010C3F, 80000B010E010C3F,
+static const uint64_t P9N2_PEC_2_SCOM0X01 = 0x80000B410F010C3Full;
+//DUPS: 800005010F010C3F, 800005410F010C3F, 80000A010F010C3F, 800000010F010C3F, 800000410F010C3F, 800001010F010C3F, 800001410F010C3F, 800002010F010C3F, 800002410F010C3F, 800003010F010C3F, 800003410F010C3F, 800008010F010C3F, 800008410F010C3F, 800009010F010C3F, 800009410F010C3F, 80000A410F010C3F, 80000B010F010C3F,
+
+static const uint64_t P9N2_PEC_SCOM0X02 = 0x80000B420D010C3Full;
+//DUPS: 800005020D010C3F, 800000820D010C3F, 800005420D010C3F, 80000A020D010C3F, 800000C20D010C3F, 800001820D010C3F, 800001C20D010C3F, 800003C20D010C3F, 800003820D010C3F, 800002C20D010C3F, 800002820D010C3F, 800009C20D010C3F, 800009820D010C3F, 800008C20D010C3F, 800008820D010C3F, 80000BC20D010C3F, 80000B820D010C3F, 80000AC20D010C3F, 80000A820D010C3F, 800000020D010C3F, 800000420D010C3F, 800001020D010C3F, 800001420D010C3F, 800002020D010C3F, 800002420D010C3F, 800003020D010C3F, 800003420D010C3F, 800008020D010C3F, 800008420D010C3F, 800009020D010C3F, 800009420D010C3F, 80000A420D010C3F, 80000B020D010C3F,
+static const uint64_t P9N2_PEC_0_SCOM0X02 = 0x80000B420D010C3Full;
+//DUPS: 800005020D010C3F, 800000820D010C3F, 800005420D010C3F, 80000A020D010C3F, 800000C20D010C3F, 800001820D010C3F, 800001C20D010C3F, 800003C20D010C3F, 800003820D010C3F, 800002C20D010C3F, 800002820D010C3F, 800009C20D010C3F, 800009820D010C3F, 800008C20D010C3F, 800008820D010C3F, 80000BC20D010C3F, 80000B820D010C3F, 80000AC20D010C3F, 80000A820D010C3F, 800000020D010C3F, 800000420D010C3F, 800001020D010C3F, 800001420D010C3F, 800002020D010C3F, 800002420D010C3F, 800003020D010C3F, 800003420D010C3F, 800008020D010C3F, 800008420D010C3F, 800009020D010C3F, 800009420D010C3F, 80000A420D010C3F, 80000B020D010C3F,
+static const uint64_t P9N2_PEC_1_SCOM0X02 = 0x80000B420E010C3Full;
+//DUPS: 800005020E010C3F, 800000820E010C3F, 800005420E010C3F, 80000A020E010C3F, 800000C20E010C3F, 800001820E010C3F, 800001C20E010C3F, 800003C20E010C3F, 800003820E010C3F, 800002C20E010C3F, 800002820E010C3F, 800009C20E010C3F, 800009820E010C3F, 800008C20E010C3F, 800008820E010C3F, 80000BC20E010C3F, 80000B820E010C3F, 80000AC20E010C3F, 80000A820E010C3F, 800000020E010C3F, 800000420E010C3F, 800001020E010C3F, 800001420E010C3F, 800002020E010C3F, 800002420E010C3F, 800003020E010C3F, 800003420E010C3F, 800008020E010C3F, 800008420E010C3F, 800009020E010C3F, 800009420E010C3F, 80000A420E010C3F, 80000B020E010C3F,
+static const uint64_t P9N2_PEC_2_SCOM0X02 = 0x80000B420F010C3Full;
+//DUPS: 800005020F010C3F, 800000820F010C3F, 800005420F010C3F, 80000A020F010C3F, 800000C20F010C3F, 800001820F010C3F, 800001C20F010C3F, 800003C20F010C3F, 800003820F010C3F, 800002C20F010C3F, 800002820F010C3F, 800009C20F010C3F, 800009820F010C3F, 800008C20F010C3F, 800008820F010C3F, 80000BC20F010C3F, 80000B820F010C3F, 80000AC20F010C3F, 80000A820F010C3F, 800000020F010C3F, 800000420F010C3F, 800001020F010C3F, 800001420F010C3F, 800002020F010C3F, 800002420F010C3F, 800003020F010C3F, 800003420F010C3F, 800008020F010C3F, 800008420F010C3F, 800009020F010C3F, 800009420F010C3F, 80000A420F010C3F, 80000B020F010C3F,
+
+static const uint64_t P9N2_PEC_SCOM0X03 = 0x80000B430D010C3Full;
+//DUPS: 800005030D010C3F, 800000830D010C3F, 800005430D010C3F, 80000A030D010C3F, 800000C30D010C3F, 800001830D010C3F, 800001C30D010C3F, 800003C30D010C3F, 800003830D010C3F, 800002C30D010C3F, 800002830D010C3F, 800009C30D010C3F, 800009830D010C3F, 800008C30D010C3F, 800008830D010C3F, 80000BC30D010C3F, 80000B830D010C3F, 80000AC30D010C3F, 80000A830D010C3F, 800000030D010C3F, 800000430D010C3F, 800001030D010C3F, 800001430D010C3F, 800002030D010C3F, 800002430D010C3F, 800003030D010C3F, 800003430D010C3F, 800008030D010C3F, 800008430D010C3F, 800009030D010C3F, 800009430D010C3F, 80000A430D010C3F, 80000B030D010C3F,
+static const uint64_t P9N2_PEC_0_SCOM0X03 = 0x80000B430D010C3Full;
+//DUPS: 800005030D010C3F, 800000830D010C3F, 800005430D010C3F, 80000A030D010C3F, 800000C30D010C3F, 800001830D010C3F, 800001C30D010C3F, 800003C30D010C3F, 800003830D010C3F, 800002C30D010C3F, 800002830D010C3F, 800009C30D010C3F, 800009830D010C3F, 800008C30D010C3F, 800008830D010C3F, 80000BC30D010C3F, 80000B830D010C3F, 80000AC30D010C3F, 80000A830D010C3F, 800000030D010C3F, 800000430D010C3F, 800001030D010C3F, 800001430D010C3F, 800002030D010C3F, 800002430D010C3F, 800003030D010C3F, 800003430D010C3F, 800008030D010C3F, 800008430D010C3F, 800009030D010C3F, 800009430D010C3F, 80000A430D010C3F, 80000B030D010C3F,
+static const uint64_t P9N2_PEC_1_SCOM0X03 = 0x80000B430E010C3Full;
+//DUPS: 800005030E010C3F, 800000830E010C3F, 800005430E010C3F, 80000A030E010C3F, 800000C30E010C3F, 800001830E010C3F, 800001C30E010C3F, 800003C30E010C3F, 800003830E010C3F, 800002C30E010C3F, 800002830E010C3F, 800009C30E010C3F, 800009830E010C3F, 800008C30E010C3F, 800008830E010C3F, 80000BC30E010C3F, 80000B830E010C3F, 80000AC30E010C3F, 80000A830E010C3F, 800000030E010C3F, 800000430E010C3F, 800001030E010C3F, 800001430E010C3F, 800002030E010C3F, 800002430E010C3F, 800003030E010C3F, 800003430E010C3F, 800008030E010C3F, 800008430E010C3F, 800009030E010C3F, 800009430E010C3F, 80000A430E010C3F, 80000B030E010C3F,
+static const uint64_t P9N2_PEC_2_SCOM0X03 = 0x80000B430F010C3Full;
+//DUPS: 800005030F010C3F, 800000830F010C3F, 800005430F010C3F, 80000A030F010C3F, 800000C30F010C3F, 800001830F010C3F, 800001C30F010C3F, 800003C30F010C3F, 800003830F010C3F, 800002C30F010C3F, 800002830F010C3F, 800009C30F010C3F, 800009830F010C3F, 800008C30F010C3F, 800008830F010C3F, 80000BC30F010C3F, 80000B830F010C3F, 80000AC30F010C3F, 80000A830F010C3F, 800000030F010C3F, 800000430F010C3F, 800001030F010C3F, 800001430F010C3F, 800002030F010C3F, 800002430F010C3F, 800003030F010C3F, 800003430F010C3F, 800008030F010C3F, 800008430F010C3F, 800009030F010C3F, 800009430F010C3F, 80000A430F010C3F, 80000B030F010C3F,
+
+static const uint64_t P9N2_PEC_SCOM0X04 = 0x80000B440D010C3Full;
+//DUPS: 800005040D010C3F, 800005440D010C3F, 80000A040D010C3F, 800000040D010C3F, 800000440D010C3F, 800001040D010C3F, 800001440D010C3F, 800002040D010C3F, 800002440D010C3F, 800003040D010C3F, 800003440D010C3F, 800008040D010C3F, 800008440D010C3F, 800009040D010C3F, 800009440D010C3F, 80000A440D010C3F, 80000B040D010C3F,
+static const uint64_t P9N2_PEC_0_SCOM0X04 = 0x80000B440D010C3Full;
+//DUPS: 800005040D010C3F, 800005440D010C3F, 80000A040D010C3F, 800000040D010C3F, 800000440D010C3F, 800001040D010C3F, 800001440D010C3F, 800002040D010C3F, 800002440D010C3F, 800003040D010C3F, 800003440D010C3F, 800008040D010C3F, 800008440D010C3F, 800009040D010C3F, 800009440D010C3F, 80000A440D010C3F, 80000B040D010C3F,
+static const uint64_t P9N2_PEC_1_SCOM0X04 = 0x80000B440E010C3Full;
+//DUPS: 800005040E010C3F, 800005440E010C3F, 80000A040E010C3F, 800000040E010C3F, 800000440E010C3F, 800001040E010C3F, 800001440E010C3F, 800002040E010C3F, 800002440E010C3F, 800003040E010C3F, 800003440E010C3F, 800008040E010C3F, 800008440E010C3F, 800009040E010C3F, 800009440E010C3F, 80000A440E010C3F, 80000B040E010C3F,
+static const uint64_t P9N2_PEC_2_SCOM0X04 = 0x80000B440F010C3Full;
+//DUPS: 800005040F010C3F, 800005440F010C3F, 80000A040F010C3F, 800000040F010C3F, 800000440F010C3F, 800001040F010C3F, 800001440F010C3F, 800002040F010C3F, 800002440F010C3F, 800003040F010C3F, 800003440F010C3F, 800008040F010C3F, 800008440F010C3F, 800009040F010C3F, 800009440F010C3F, 80000A440F010C3F, 80000B040F010C3F,
+
+static const uint64_t P9N2_PEC_SCOM0X05 = 0x80000B450D010C3Full;
+//DUPS: 800004050D010C3F, 80000A050D010C3F, 800000050D010C3F, 800000450D010C3F, 800001050D010C3F, 800001450D010C3F, 800002050D010C3F, 800002450D010C3F, 800003050D010C3F, 800003450D010C3F, 800008050D010C3F, 800008450D010C3F, 800009050D010C3F, 800009450D010C3F, 80000A450D010C3F, 80000B050D010C3F,
+static const uint64_t P9N2_PEC_0_SCOM0X05 = 0x80000B450D010C3Full;
+//DUPS: 800004050D010C3F, 80000A050D010C3F, 800000050D010C3F, 800000450D010C3F, 800001050D010C3F, 800001450D010C3F, 800002050D010C3F, 800002450D010C3F, 800003050D010C3F, 800003450D010C3F, 800008050D010C3F, 800008450D010C3F, 800009050D010C3F, 800009450D010C3F, 80000A450D010C3F, 80000B050D010C3F,
+static const uint64_t P9N2_PEC_1_SCOM0X05 = 0x80000B450E010C3Full;
+//DUPS: 800004050E010C3F, 80000A050E010C3F, 800000050E010C3F, 800000450E010C3F, 800001050E010C3F, 800001450E010C3F, 800002050E010C3F, 800002450E010C3F, 800003050E010C3F, 800003450E010C3F, 800008050E010C3F, 800008450E010C3F, 800009050E010C3F, 800009450E010C3F, 80000A450E010C3F, 80000B050E010C3F,
+static const uint64_t P9N2_PEC_2_SCOM0X05 = 0x80000B450F010C3Full;
+//DUPS: 800004050F010C3F, 80000A050F010C3F, 800000050F010C3F, 800000450F010C3F, 800001050F010C3F, 800001450F010C3F, 800002050F010C3F, 800002450F010C3F, 800003050F010C3F, 800003450F010C3F, 800008050F010C3F, 800008450F010C3F, 800009050F010C3F, 800009450F010C3F, 80000A450F010C3F, 80000B050F010C3F,
+
+static const uint64_t P9N2_PEC_SCOM0X06 = 0x80000B460D010C3Full;
+//DUPS: 800000860D010C3F, 80000A060D010C3F, 800000C60D010C3F, 800001860D010C3F, 800001C60D010C3F, 800003C60D010C3F, 800003860D010C3F, 800002C60D010C3F, 800002860D010C3F, 800009C60D010C3F, 800009860D010C3F, 800008C60D010C3F, 800008860D010C3F, 80000BC60D010C3F, 80000B860D010C3F, 80000AC60D010C3F, 80000A860D010C3F, 800000060D010C3F, 800000460D010C3F, 800001060D010C3F, 800001460D010C3F, 800002060D010C3F, 800002460D010C3F, 800003060D010C3F, 800003460D010C3F, 800008060D010C3F, 800008460D010C3F, 800009060D010C3F, 800009460D010C3F, 80000A460D010C3F, 80000B060D010C3F,
+static const uint64_t P9N2_PEC_0_SCOM0X06 = 0x80000B460D010C3Full;
+//DUPS: 800000860D010C3F, 80000A060D010C3F, 800000C60D010C3F, 800001860D010C3F, 800001C60D010C3F, 800003C60D010C3F, 800003860D010C3F, 800002C60D010C3F, 800002860D010C3F, 800009C60D010C3F, 800009860D010C3F, 800008C60D010C3F, 800008860D010C3F, 80000BC60D010C3F, 80000B860D010C3F, 80000AC60D010C3F, 80000A860D010C3F, 800000060D010C3F, 800000460D010C3F, 800001060D010C3F, 800001460D010C3F, 800002060D010C3F, 800002460D010C3F, 800003060D010C3F, 800003460D010C3F, 800008060D010C3F, 800008460D010C3F, 800009060D010C3F, 800009460D010C3F, 80000A460D010C3F, 80000B060D010C3F,
+static const uint64_t P9N2_PEC_1_SCOM0X06 = 0x80000B460E010C3Full;
+//DUPS: 800000860E010C3F, 80000A060E010C3F, 800000C60E010C3F, 800001860E010C3F, 800001C60E010C3F, 800003C60E010C3F, 800003860E010C3F, 800002C60E010C3F, 800002860E010C3F, 800009C60E010C3F, 800009860E010C3F, 800008C60E010C3F, 800008860E010C3F, 80000BC60E010C3F, 80000B860E010C3F, 80000AC60E010C3F, 80000A860E010C3F, 800000060E010C3F, 800000460E010C3F, 800001060E010C3F, 800001460E010C3F, 800002060E010C3F, 800002460E010C3F, 800003060E010C3F, 800003460E010C3F, 800008060E010C3F, 800008460E010C3F, 800009060E010C3F, 800009460E010C3F, 80000A460E010C3F, 80000B060E010C3F,
+static const uint64_t P9N2_PEC_2_SCOM0X06 = 0x80000B460F010C3Full;
+//DUPS: 800000860F010C3F, 80000A060F010C3F, 800000C60F010C3F, 800001860F010C3F, 800001C60F010C3F, 800003C60F010C3F, 800003860F010C3F, 800002C60F010C3F, 800002860F010C3F, 800009C60F010C3F, 800009860F010C3F, 800008C60F010C3F, 800008860F010C3F, 80000BC60F010C3F, 80000B860F010C3F, 80000AC60F010C3F, 80000A860F010C3F, 800000060F010C3F, 800000460F010C3F, 800001060F010C3F, 800001460F010C3F, 800002060F010C3F, 800002460F010C3F, 800003060F010C3F, 800003460F010C3F, 800008060F010C3F, 800008460F010C3F, 800009060F010C3F, 800009460F010C3F, 80000A460F010C3F, 80000B060F010C3F,
+
+static const uint64_t P9N2_PEC_SCOM0X07 = 0x80000B470D010C3Full;
+//DUPS: 800000870D010C3F, 80000A070D010C3F, 800000C70D010C3F, 800001870D010C3F, 800001C70D010C3F, 800003C70D010C3F, 800003870D010C3F, 800002C70D010C3F, 800002870D010C3F, 800009C70D010C3F, 800009870D010C3F, 800008C70D010C3F, 800008870D010C3F, 80000BC70D010C3F, 80000B870D010C3F, 80000AC70D010C3F, 80000A870D010C3F, 800000070D010C3F, 800000470D010C3F, 800001070D010C3F, 800001470D010C3F, 800002070D010C3F, 800002470D010C3F, 800003070D010C3F, 800003470D010C3F, 800008070D010C3F, 800008470D010C3F, 800009070D010C3F, 800009470D010C3F, 80000A470D010C3F, 80000B070D010C3F,
+static const uint64_t P9N2_PEC_0_SCOM0X07 = 0x80000B470D010C3Full;
+//DUPS: 800000870D010C3F, 80000A070D010C3F, 800000C70D010C3F, 800001870D010C3F, 800001C70D010C3F, 800003C70D010C3F, 800003870D010C3F, 800002C70D010C3F, 800002870D010C3F, 800009C70D010C3F, 800009870D010C3F, 800008C70D010C3F, 800008870D010C3F, 80000BC70D010C3F, 80000B870D010C3F, 80000AC70D010C3F, 80000A870D010C3F, 800000070D010C3F, 800000470D010C3F, 800001070D010C3F, 800001470D010C3F, 800002070D010C3F, 800002470D010C3F, 800003070D010C3F, 800003470D010C3F, 800008070D010C3F, 800008470D010C3F, 800009070D010C3F, 800009470D010C3F, 80000A470D010C3F, 80000B070D010C3F,
+static const uint64_t P9N2_PEC_1_SCOM0X07 = 0x80000B470E010C3Full;
+//DUPS: 800000870E010C3F, 80000A070E010C3F, 800000C70E010C3F, 800001870E010C3F, 800001C70E010C3F, 800003C70E010C3F, 800003870E010C3F, 800002C70E010C3F, 800002870E010C3F, 800009C70E010C3F, 800009870E010C3F, 800008C70E010C3F, 800008870E010C3F, 80000BC70E010C3F, 80000B870E010C3F, 80000AC70E010C3F, 80000A870E010C3F, 800000070E010C3F, 800000470E010C3F, 800001070E010C3F, 800001470E010C3F, 800002070E010C3F, 800002470E010C3F, 800003070E010C3F, 800003470E010C3F, 800008070E010C3F, 800008470E010C3F, 800009070E010C3F, 800009470E010C3F, 80000A470E010C3F, 80000B070E010C3F,
+static const uint64_t P9N2_PEC_2_SCOM0X07 = 0x80000B470F010C3Full;
+//DUPS: 800000870F010C3F, 80000A070F010C3F, 800000C70F010C3F, 800001870F010C3F, 800001C70F010C3F, 800003C70F010C3F, 800003870F010C3F, 800002C70F010C3F, 800002870F010C3F, 800009C70F010C3F, 800009870F010C3F, 800008C70F010C3F, 800008870F010C3F, 80000BC70F010C3F, 80000B870F010C3F, 80000AC70F010C3F, 80000A870F010C3F, 800000070F010C3F, 800000470F010C3F, 800001070F010C3F, 800001470F010C3F, 800002070F010C3F, 800002470F010C3F, 800003070F010C3F, 800003470F010C3F, 800008070F010C3F, 800008470F010C3F, 800009070F010C3F, 800009470F010C3F, 80000A470F010C3F, 80000B070F010C3F,
+
+static const uint64_t P9N2_PEC_SCOM0X08 = 0x80000B480D010C3Full;
+//DUPS: 800000880D010C3F, 80000A080D010C3F, 800000C80D010C3F, 800001880D010C3F, 800001C80D010C3F, 800003C80D010C3F, 800003880D010C3F, 800002C80D010C3F, 800002880D010C3F, 800009C80D010C3F, 800009880D010C3F, 800008C80D010C3F, 800008880D010C3F, 80000BC80D010C3F, 80000B880D010C3F, 80000AC80D010C3F, 80000A880D010C3F, 800000080D010C3F, 800000480D010C3F, 800001080D010C3F, 800001480D010C3F, 800002080D010C3F, 800002480D010C3F, 800003080D010C3F, 800003480D010C3F, 800008080D010C3F, 800008480D010C3F, 800009080D010C3F, 800009480D010C3F, 80000A480D010C3F, 80000B080D010C3F,
+static const uint64_t P9N2_PEC_0_SCOM0X08 = 0x80000B480D010C3Full;
+//DUPS: 800000880D010C3F, 80000A080D010C3F, 800000C80D010C3F, 800001880D010C3F, 800001C80D010C3F, 800003C80D010C3F, 800003880D010C3F, 800002C80D010C3F, 800002880D010C3F, 800009C80D010C3F, 800009880D010C3F, 800008C80D010C3F, 800008880D010C3F, 80000BC80D010C3F, 80000B880D010C3F, 80000AC80D010C3F, 80000A880D010C3F, 800000080D010C3F, 800000480D010C3F, 800001080D010C3F, 800001480D010C3F, 800002080D010C3F, 800002480D010C3F, 800003080D010C3F, 800003480D010C3F, 800008080D010C3F, 800008480D010C3F, 800009080D010C3F, 800009480D010C3F, 80000A480D010C3F, 80000B080D010C3F,
+static const uint64_t P9N2_PEC_1_SCOM0X08 = 0x80000B480E010C3Full;
+//DUPS: 800000880E010C3F, 80000A080E010C3F, 800000C80E010C3F, 800001880E010C3F, 800001C80E010C3F, 800003C80E010C3F, 800003880E010C3F, 800002C80E010C3F, 800002880E010C3F, 800009C80E010C3F, 800009880E010C3F, 800008C80E010C3F, 800008880E010C3F, 80000BC80E010C3F, 80000B880E010C3F, 80000AC80E010C3F, 80000A880E010C3F, 800000080E010C3F, 800000480E010C3F, 800001080E010C3F, 800001480E010C3F, 800002080E010C3F, 800002480E010C3F, 800003080E010C3F, 800003480E010C3F, 800008080E010C3F, 800008480E010C3F, 800009080E010C3F, 800009480E010C3F, 80000A480E010C3F, 80000B080E010C3F,
+static const uint64_t P9N2_PEC_2_SCOM0X08 = 0x80000B480F010C3Full;
+//DUPS: 800000880F010C3F, 80000A080F010C3F, 800000C80F010C3F, 800001880F010C3F, 800001C80F010C3F, 800003C80F010C3F, 800003880F010C3F, 800002C80F010C3F, 800002880F010C3F, 800009C80F010C3F, 800009880F010C3F, 800008C80F010C3F, 800008880F010C3F, 80000BC80F010C3F, 80000B880F010C3F, 80000AC80F010C3F, 80000A880F010C3F, 800000080F010C3F, 800000480F010C3F, 800001080F010C3F, 800001480F010C3F, 800002080F010C3F, 800002480F010C3F, 800003080F010C3F, 800003480F010C3F, 800008080F010C3F, 800008480F010C3F, 800009080F010C3F, 800009480F010C3F, 80000A480F010C3F, 80000B080F010C3F,
+
+static const uint64_t P9N2_PEC_SCOM0X09 = 0x80000BC90D010C3Full;
+//DUPS: 800000C90D010C3F, 800001890D010C3F, 800001C90D010C3F, 800003C90D010C3F, 800003890D010C3F, 800002C90D010C3F, 800002890D010C3F, 800009C90D010C3F, 800009890D010C3F, 800008C90D010C3F, 800008890D010C3F, 80000BC90D010C3F, 80000B890D010C3F, 80000AC90D010C3F, 80000A890D010C3F,
+static const uint64_t P9N2_PEC_0_SCOM0X09 = 0x80000BC90D010C3Full;
+//DUPS: 800000C90D010C3F, 800001890D010C3F, 800001C90D010C3F, 800003C90D010C3F, 800003890D010C3F, 800002C90D010C3F, 800002890D010C3F, 800009C90D010C3F, 800009890D010C3F, 800008C90D010C3F, 800008890D010C3F, 80000BC90D010C3F, 80000B890D010C3F, 80000AC90D010C3F, 80000A890D010C3F,
+static const uint64_t P9N2_PEC_1_SCOM0X09 = 0x80000BC90E010C3Full;
+//DUPS: 800000C90E010C3F, 800001890E010C3F, 800001C90E010C3F, 800003C90E010C3F, 800003890E010C3F, 800002C90E010C3F, 800002890E010C3F, 800009C90E010C3F, 800009890E010C3F, 800008C90E010C3F, 800008890E010C3F, 80000BC90E010C3F, 80000B890E010C3F, 80000AC90E010C3F, 80000A890E010C3F,
+static const uint64_t P9N2_PEC_2_SCOM0X09 = 0x80000BC90F010C3Full;
+//DUPS: 800000C90F010C3F, 800001890F010C3F, 800001C90F010C3F, 800003C90F010C3F, 800003890F010C3F, 800002C90F010C3F, 800002890F010C3F, 800009C90F010C3F, 800009890F010C3F, 800008C90F010C3F, 800008890F010C3F, 80000BC90F010C3F, 80000B890F010C3F, 80000AC90F010C3F, 80000A890F010C3F,
+
+static const uint64_t P9N2_PEC_SCOM0X0A = 0x80000BCA0D010C3Full;
+//DUPS: 800000CA0D010C3F, 8000018A0D010C3F, 800001CA0D010C3F, 800003CA0D010C3F, 8000038A0D010C3F, 800002CA0D010C3F, 8000028A0D010C3F, 800009CA0D010C3F, 8000098A0D010C3F, 800008CA0D010C3F, 8000088A0D010C3F, 80000BCA0D010C3F, 80000B8A0D010C3F, 80000ACA0D010C3F, 80000A8A0D010C3F,
+static const uint64_t P9N2_PEC_0_SCOM0X0A = 0x80000BCA0D010C3Full;
+//DUPS: 800000CA0D010C3F, 8000018A0D010C3F, 800001CA0D010C3F, 800003CA0D010C3F, 8000038A0D010C3F, 800002CA0D010C3F, 8000028A0D010C3F, 800009CA0D010C3F, 8000098A0D010C3F, 800008CA0D010C3F, 8000088A0D010C3F, 80000BCA0D010C3F, 80000B8A0D010C3F, 80000ACA0D010C3F, 80000A8A0D010C3F,
+static const uint64_t P9N2_PEC_1_SCOM0X0A = 0x80000BCA0E010C3Full;
+//DUPS: 800000CA0E010C3F, 8000018A0E010C3F, 800001CA0E010C3F, 800003CA0E010C3F, 8000038A0E010C3F, 800002CA0E010C3F, 8000028A0E010C3F, 800009CA0E010C3F, 8000098A0E010C3F, 800008CA0E010C3F, 8000088A0E010C3F, 80000BCA0E010C3F, 80000B8A0E010C3F, 80000ACA0E010C3F, 80000A8A0E010C3F,
+static const uint64_t P9N2_PEC_2_SCOM0X0A = 0x80000BCA0F010C3Full;
+//DUPS: 800000CA0F010C3F, 8000018A0F010C3F, 800001CA0F010C3F, 800003CA0F010C3F, 8000038A0F010C3F, 800002CA0F010C3F, 8000028A0F010C3F, 800009CA0F010C3F, 8000098A0F010C3F, 800008CA0F010C3F, 8000088A0F010C3F, 80000BCA0F010C3F, 80000B8A0F010C3F, 80000ACA0F010C3F, 80000A8A0F010C3F,
+
+static const uint64_t P9N2_PEC_SCOM0X0B = 0x80000B4B0D010C3Full;
+//DUPS: 8000008B0D010C3F, 80000A0B0D010C3F, 800000CB0D010C3F, 8000018B0D010C3F, 800001CB0D010C3F, 800003CB0D010C3F, 8000038B0D010C3F, 800002CB0D010C3F, 8000028B0D010C3F, 800009CB0D010C3F, 8000098B0D010C3F, 800008CB0D010C3F, 8000088B0D010C3F, 80000BCB0D010C3F, 80000B8B0D010C3F, 80000ACB0D010C3F, 80000A8B0D010C3F, 8000000B0D010C3F, 8000004B0D010C3F, 8000010B0D010C3F, 8000014B0D010C3F, 8000020B0D010C3F, 8000024B0D010C3F, 8000030B0D010C3F, 8000034B0D010C3F, 8000080B0D010C3F, 8000084B0D010C3F, 8000090B0D010C3F, 8000094B0D010C3F, 80000A4B0D010C3F, 80000B0B0D010C3F,
+static const uint64_t P9N2_PEC_0_SCOM0X0B = 0x80000B4B0D010C3Full;
+//DUPS: 8000008B0D010C3F, 80000A0B0D010C3F, 800000CB0D010C3F, 8000018B0D010C3F, 800001CB0D010C3F, 800003CB0D010C3F, 8000038B0D010C3F, 800002CB0D010C3F, 8000028B0D010C3F, 800009CB0D010C3F, 8000098B0D010C3F, 800008CB0D010C3F, 8000088B0D010C3F, 80000BCB0D010C3F, 80000B8B0D010C3F, 80000ACB0D010C3F, 80000A8B0D010C3F, 8000000B0D010C3F, 8000004B0D010C3F, 8000010B0D010C3F, 8000014B0D010C3F, 8000020B0D010C3F, 8000024B0D010C3F, 8000030B0D010C3F, 8000034B0D010C3F, 8000080B0D010C3F, 8000084B0D010C3F, 8000090B0D010C3F, 8000094B0D010C3F, 80000A4B0D010C3F, 80000B0B0D010C3F,
+static const uint64_t P9N2_PEC_1_SCOM0X0B = 0x80000B4B0E010C3Full;
+//DUPS: 8000008B0E010C3F, 80000A0B0E010C3F, 800000CB0E010C3F, 8000018B0E010C3F, 800001CB0E010C3F, 800003CB0E010C3F, 8000038B0E010C3F, 800002CB0E010C3F, 8000028B0E010C3F, 800009CB0E010C3F, 8000098B0E010C3F, 800008CB0E010C3F, 8000088B0E010C3F, 80000BCB0E010C3F, 80000B8B0E010C3F, 80000ACB0E010C3F, 80000A8B0E010C3F, 8000000B0E010C3F, 8000004B0E010C3F, 8000010B0E010C3F, 8000014B0E010C3F, 8000020B0E010C3F, 8000024B0E010C3F, 8000030B0E010C3F, 8000034B0E010C3F, 8000080B0E010C3F, 8000084B0E010C3F, 8000090B0E010C3F, 8000094B0E010C3F, 80000A4B0E010C3F, 80000B0B0E010C3F,
+static const uint64_t P9N2_PEC_2_SCOM0X0B = 0x80000B4B0F010C3Full;
+//DUPS: 8000008B0F010C3F, 80000A0B0F010C3F, 800000CB0F010C3F, 8000018B0F010C3F, 800001CB0F010C3F, 800003CB0F010C3F, 8000038B0F010C3F, 800002CB0F010C3F, 8000028B0F010C3F, 800009CB0F010C3F, 8000098B0F010C3F, 800008CB0F010C3F, 8000088B0F010C3F, 80000BCB0F010C3F, 80000B8B0F010C3F, 80000ACB0F010C3F, 80000A8B0F010C3F, 8000000B0F010C3F, 8000004B0F010C3F, 8000010B0F010C3F, 8000014B0F010C3F, 8000020B0F010C3F, 8000024B0F010C3F, 8000030B0F010C3F, 8000034B0F010C3F, 8000080B0F010C3F, 8000084B0F010C3F, 8000090B0F010C3F, 8000094B0F010C3F, 80000A4B0F010C3F, 80000B0B0F010C3F,
+
+static const uint64_t P9N2_PEC_SCOM0X0C = 0x80000BCC0D010C3Full;
+//DUPS: 800000CC0D010C3F, 8000018C0D010C3F, 800001CC0D010C3F, 800003CC0D010C3F, 8000038C0D010C3F, 800002CC0D010C3F, 8000028C0D010C3F, 800009CC0D010C3F, 8000098C0D010C3F, 800008CC0D010C3F, 8000088C0D010C3F, 80000BCC0D010C3F, 80000B8C0D010C3F, 80000ACC0D010C3F, 80000A8C0D010C3F,
+static const uint64_t P9N2_PEC_0_SCOM0X0C = 0x80000BCC0D010C3Full;
+//DUPS: 800000CC0D010C3F, 8000018C0D010C3F, 800001CC0D010C3F, 800003CC0D010C3F, 8000038C0D010C3F, 800002CC0D010C3F, 8000028C0D010C3F, 800009CC0D010C3F, 8000098C0D010C3F, 800008CC0D010C3F, 8000088C0D010C3F, 80000BCC0D010C3F, 80000B8C0D010C3F, 80000ACC0D010C3F, 80000A8C0D010C3F,
+static const uint64_t P9N2_PEC_1_SCOM0X0C = 0x80000BCC0E010C3Full;
+//DUPS: 800000CC0E010C3F, 8000018C0E010C3F, 800001CC0E010C3F, 800003CC0E010C3F, 8000038C0E010C3F, 800002CC0E010C3F, 8000028C0E010C3F, 800009CC0E010C3F, 8000098C0E010C3F, 800008CC0E010C3F, 8000088C0E010C3F, 80000BCC0E010C3F, 80000B8C0E010C3F, 80000ACC0E010C3F, 80000A8C0E010C3F,
+static const uint64_t P9N2_PEC_2_SCOM0X0C = 0x80000BCC0F010C3Full;
+//DUPS: 800000CC0F010C3F, 8000018C0F010C3F, 800001CC0F010C3F, 800003CC0F010C3F, 8000038C0F010C3F, 800002CC0F010C3F, 8000028C0F010C3F, 800009CC0F010C3F, 8000098C0F010C3F, 800008CC0F010C3F, 8000088C0F010C3F, 80000BCC0F010C3F, 80000B8C0F010C3F, 80000ACC0F010C3F, 80000A8C0F010C3F,
+
+static const uint64_t P9N2_PEC_SCOM0X0D = 0x80000B4D0D010C3Full;
+//DUPS: 8000008D0D010C3F, 80000A0D0D010C3F, 800000CD0D010C3F, 8000018D0D010C3F, 800001CD0D010C3F, 800003CD0D010C3F, 8000038D0D010C3F, 800002CD0D010C3F, 8000028D0D010C3F, 800009CD0D010C3F, 8000098D0D010C3F, 800008CD0D010C3F, 8000088D0D010C3F, 80000BCD0D010C3F, 80000B8D0D010C3F, 80000ACD0D010C3F, 80000A8D0D010C3F, 8000000D0D010C3F, 8000004D0D010C3F, 8000010D0D010C3F, 8000014D0D010C3F, 8000020D0D010C3F, 8000024D0D010C3F, 8000030D0D010C3F, 8000034D0D010C3F, 8000080D0D010C3F, 8000084D0D010C3F, 8000090D0D010C3F, 8000094D0D010C3F, 80000A4D0D010C3F, 80000B0D0D010C3F,
+static const uint64_t P9N2_PEC_0_SCOM0X0D = 0x80000B4D0D010C3Full;
+//DUPS: 8000008D0D010C3F, 80000A0D0D010C3F, 800000CD0D010C3F, 8000018D0D010C3F, 800001CD0D010C3F, 800003CD0D010C3F, 8000038D0D010C3F, 800002CD0D010C3F, 8000028D0D010C3F, 800009CD0D010C3F, 8000098D0D010C3F, 800008CD0D010C3F, 8000088D0D010C3F, 80000BCD0D010C3F, 80000B8D0D010C3F, 80000ACD0D010C3F, 80000A8D0D010C3F, 8000000D0D010C3F, 8000004D0D010C3F, 8000010D0D010C3F, 8000014D0D010C3F, 8000020D0D010C3F, 8000024D0D010C3F, 8000030D0D010C3F, 8000034D0D010C3F, 8000080D0D010C3F, 8000084D0D010C3F, 8000090D0D010C3F, 8000094D0D010C3F, 80000A4D0D010C3F, 80000B0D0D010C3F,
+static const uint64_t P9N2_PEC_1_SCOM0X0D = 0x80000B4D0E010C3Full;
+//DUPS: 8000008D0E010C3F, 80000A0D0E010C3F, 800000CD0E010C3F, 8000018D0E010C3F, 800001CD0E010C3F, 800003CD0E010C3F, 8000038D0E010C3F, 800002CD0E010C3F, 8000028D0E010C3F, 800009CD0E010C3F, 8000098D0E010C3F, 800008CD0E010C3F, 8000088D0E010C3F, 80000BCD0E010C3F, 80000B8D0E010C3F, 80000ACD0E010C3F, 80000A8D0E010C3F, 8000000D0E010C3F, 8000004D0E010C3F, 8000010D0E010C3F, 8000014D0E010C3F, 8000020D0E010C3F, 8000024D0E010C3F, 8000030D0E010C3F, 8000034D0E010C3F, 8000080D0E010C3F, 8000084D0E010C3F, 8000090D0E010C3F, 8000094D0E010C3F, 80000A4D0E010C3F, 80000B0D0E010C3F,
+static const uint64_t P9N2_PEC_2_SCOM0X0D = 0x80000B4D0F010C3Full;
+//DUPS: 8000008D0F010C3F, 80000A0D0F010C3F, 800000CD0F010C3F, 8000018D0F010C3F, 800001CD0F010C3F, 800003CD0F010C3F, 8000038D0F010C3F, 800002CD0F010C3F, 8000028D0F010C3F, 800009CD0F010C3F, 8000098D0F010C3F, 800008CD0F010C3F, 8000088D0F010C3F, 80000BCD0F010C3F, 80000B8D0F010C3F, 80000ACD0F010C3F, 80000A8D0F010C3F, 8000000D0F010C3F, 8000004D0F010C3F, 8000010D0F010C3F, 8000014D0F010C3F, 8000020D0F010C3F, 8000024D0F010C3F, 8000030D0F010C3F, 8000034D0F010C3F, 8000080D0F010C3F, 8000084D0F010C3F, 8000090D0F010C3F, 8000094D0F010C3F, 80000A4D0F010C3F, 80000B0D0F010C3F,
+
+static const uint64_t P9N2_PEC_SCOM0X0E = 0x80000B4E0D010C3Full;
+//DUPS: 8000008E0D010C3F, 80000A0E0D010C3F, 800000CE0D010C3F, 8000018E0D010C3F, 800001CE0D010C3F, 800003CE0D010C3F, 8000038E0D010C3F, 800002CE0D010C3F, 8000028E0D010C3F, 800009CE0D010C3F, 8000098E0D010C3F, 800008CE0D010C3F, 8000088E0D010C3F, 80000BCE0D010C3F, 80000B8E0D010C3F, 80000ACE0D010C3F, 80000A8E0D010C3F, 8000000E0D010C3F, 8000004E0D010C3F, 8000010E0D010C3F, 8000014E0D010C3F, 8000020E0D010C3F, 8000024E0D010C3F, 8000030E0D010C3F, 8000034E0D010C3F, 8000080E0D010C3F, 8000084E0D010C3F, 8000090E0D010C3F, 8000094E0D010C3F, 80000A4E0D010C3F, 80000B0E0D010C3F,
+static const uint64_t P9N2_PEC_0_SCOM0X0E = 0x80000B4E0D010C3Full;
+//DUPS: 8000008E0D010C3F, 80000A0E0D010C3F, 800000CE0D010C3F, 8000018E0D010C3F, 800001CE0D010C3F, 800003CE0D010C3F, 8000038E0D010C3F, 800002CE0D010C3F, 8000028E0D010C3F, 800009CE0D010C3F, 8000098E0D010C3F, 800008CE0D010C3F, 8000088E0D010C3F, 80000BCE0D010C3F, 80000B8E0D010C3F, 80000ACE0D010C3F, 80000A8E0D010C3F, 8000000E0D010C3F, 8000004E0D010C3F, 8000010E0D010C3F, 8000014E0D010C3F, 8000020E0D010C3F, 8000024E0D010C3F, 8000030E0D010C3F, 8000034E0D010C3F, 8000080E0D010C3F, 8000084E0D010C3F, 8000090E0D010C3F, 8000094E0D010C3F, 80000A4E0D010C3F, 80000B0E0D010C3F,
+static const uint64_t P9N2_PEC_1_SCOM0X0E = 0x80000B4E0E010C3Full;
+//DUPS: 8000008E0E010C3F, 80000A0E0E010C3F, 800000CE0E010C3F, 8000018E0E010C3F, 800001CE0E010C3F, 800003CE0E010C3F, 8000038E0E010C3F, 800002CE0E010C3F, 8000028E0E010C3F, 800009CE0E010C3F, 8000098E0E010C3F, 800008CE0E010C3F, 8000088E0E010C3F, 80000BCE0E010C3F, 80000B8E0E010C3F, 80000ACE0E010C3F, 80000A8E0E010C3F, 8000000E0E010C3F, 8000004E0E010C3F, 8000010E0E010C3F, 8000014E0E010C3F, 8000020E0E010C3F, 8000024E0E010C3F, 8000030E0E010C3F, 8000034E0E010C3F, 8000080E0E010C3F, 8000084E0E010C3F, 8000090E0E010C3F, 8000094E0E010C3F, 80000A4E0E010C3F, 80000B0E0E010C3F,
+static const uint64_t P9N2_PEC_2_SCOM0X0E = 0x80000B4E0F010C3Full;
+//DUPS: 8000008E0F010C3F, 80000A0E0F010C3F, 800000CE0F010C3F, 8000018E0F010C3F, 800001CE0F010C3F, 800003CE0F010C3F, 8000038E0F010C3F, 800002CE0F010C3F, 8000028E0F010C3F, 800009CE0F010C3F, 8000098E0F010C3F, 800008CE0F010C3F, 8000088E0F010C3F, 80000BCE0F010C3F, 80000B8E0F010C3F, 80000ACE0F010C3F, 80000A8E0F010C3F, 8000000E0F010C3F, 8000004E0F010C3F, 8000010E0F010C3F, 8000014E0F010C3F, 8000020E0F010C3F, 8000024E0F010C3F, 8000030E0F010C3F, 8000034E0F010C3F, 8000080E0F010C3F, 8000084E0F010C3F, 8000090E0F010C3F, 8000094E0F010C3F, 80000A4E0F010C3F, 80000B0E0F010C3F,
+
+static const uint64_t P9N2_PEC_SCOM0X0F = 0x80000B4F0D010C3Full;
+//DUPS: 8000050F0D010C3F, 8000008F0D010C3F, 8000054F0D010C3F, 80000A0F0D010C3F, 800000CF0D010C3F, 8000018F0D010C3F, 800001CF0D010C3F, 800003CF0D010C3F, 8000038F0D010C3F, 800002CF0D010C3F, 8000028F0D010C3F, 800009CF0D010C3F, 8000098F0D010C3F, 800008CF0D010C3F, 8000088F0D010C3F, 80000BCF0D010C3F, 80000B8F0D010C3F, 80000ACF0D010C3F, 80000A8F0D010C3F, 8000000F0D010C3F, 8000004F0D010C3F, 8000010F0D010C3F, 8000014F0D010C3F, 8000020F0D010C3F, 8000024F0D010C3F, 8000030F0D010C3F, 8000034F0D010C3F, 8000080F0D010C3F, 8000084F0D010C3F, 8000090F0D010C3F, 8000094F0D010C3F, 80000A4F0D010C3F, 80000B0F0D010C3F,
+static const uint64_t P9N2_PEC_0_SCOM0X0F = 0x80000B4F0D010C3Full;
+//DUPS: 8000050F0D010C3F, 8000008F0D010C3F, 8000054F0D010C3F, 80000A0F0D010C3F, 800000CF0D010C3F, 8000018F0D010C3F, 800001CF0D010C3F, 800003CF0D010C3F, 8000038F0D010C3F, 800002CF0D010C3F, 8000028F0D010C3F, 800009CF0D010C3F, 8000098F0D010C3F, 800008CF0D010C3F, 8000088F0D010C3F, 80000BCF0D010C3F, 80000B8F0D010C3F, 80000ACF0D010C3F, 80000A8F0D010C3F, 8000000F0D010C3F, 8000004F0D010C3F, 8000010F0D010C3F, 8000014F0D010C3F, 8000020F0D010C3F, 8000024F0D010C3F, 8000030F0D010C3F, 8000034F0D010C3F, 8000080F0D010C3F, 8000084F0D010C3F, 8000090F0D010C3F, 8000094F0D010C3F, 80000A4F0D010C3F, 80000B0F0D010C3F,
+static const uint64_t P9N2_PEC_1_SCOM0X0F = 0x80000B4F0E010C3Full;
+//DUPS: 8000050F0E010C3F, 8000008F0E010C3F, 8000054F0E010C3F, 80000A0F0E010C3F, 800000CF0E010C3F, 8000018F0E010C3F, 800001CF0E010C3F, 800003CF0E010C3F, 8000038F0E010C3F, 800002CF0E010C3F, 8000028F0E010C3F, 800009CF0E010C3F, 8000098F0E010C3F, 800008CF0E010C3F, 8000088F0E010C3F, 80000BCF0E010C3F, 80000B8F0E010C3F, 80000ACF0E010C3F, 80000A8F0E010C3F, 8000000F0E010C3F, 8000004F0E010C3F, 8000010F0E010C3F, 8000014F0E010C3F, 8000020F0E010C3F, 8000024F0E010C3F, 8000030F0E010C3F, 8000034F0E010C3F, 8000080F0E010C3F, 8000084F0E010C3F, 8000090F0E010C3F, 8000094F0E010C3F, 80000A4F0E010C3F, 80000B0F0E010C3F,
+static const uint64_t P9N2_PEC_2_SCOM0X0F = 0x80000B4F0F010C3Full;
+//DUPS: 8000050F0F010C3F, 8000008F0F010C3F, 8000054F0F010C3F, 80000A0F0F010C3F, 800000CF0F010C3F, 8000018F0F010C3F, 800001CF0F010C3F, 800003CF0F010C3F, 8000038F0F010C3F, 800002CF0F010C3F, 8000028F0F010C3F, 800009CF0F010C3F, 8000098F0F010C3F, 800008CF0F010C3F, 8000088F0F010C3F, 80000BCF0F010C3F, 80000B8F0F010C3F, 80000ACF0F010C3F, 80000A8F0F010C3F, 8000000F0F010C3F, 8000004F0F010C3F, 8000010F0F010C3F, 8000014F0F010C3F, 8000020F0F010C3F, 8000024F0F010C3F, 8000030F0F010C3F, 8000034F0F010C3F, 8000080F0F010C3F, 8000084F0F010C3F, 8000090F0F010C3F, 8000094F0F010C3F, 80000A4F0F010C3F, 80000B0F0F010C3F,
+
+static const uint64_t P9N2_PEC_SCOM0X10 = 0x80000B500D010C3Full;
+//DUPS: 800005100D010C3F, 800000900D010C3F, 800005500D010C3F, 80000A100D010C3F, 800000D00D010C3F, 800001900D010C3F, 800001D00D010C3F, 800003D00D010C3F, 800003900D010C3F, 800002D00D010C3F, 800002900D010C3F, 800009D00D010C3F, 800009900D010C3F, 800008D00D010C3F, 800008900D010C3F, 80000BD00D010C3F, 80000B900D010C3F, 80000AD00D010C3F, 80000A900D010C3F, 800000100D010C3F, 800000500D010C3F, 800001100D010C3F, 800001500D010C3F, 800002100D010C3F, 800002500D010C3F, 800003100D010C3F, 800003500D010C3F, 800008100D010C3F, 800008500D010C3F, 800009100D010C3F, 800009500D010C3F, 80000A500D010C3F, 80000B100D010C3F,
+static const uint64_t P9N2_PEC_0_SCOM0X10 = 0x80000B500D010C3Full;
+//DUPS: 800005100D010C3F, 800000900D010C3F, 800005500D010C3F, 80000A100D010C3F, 800000D00D010C3F, 800001900D010C3F, 800001D00D010C3F, 800003D00D010C3F, 800003900D010C3F, 800002D00D010C3F, 800002900D010C3F, 800009D00D010C3F, 800009900D010C3F, 800008D00D010C3F, 800008900D010C3F, 80000BD00D010C3F, 80000B900D010C3F, 80000AD00D010C3F, 80000A900D010C3F, 800000100D010C3F, 800000500D010C3F, 800001100D010C3F, 800001500D010C3F, 800002100D010C3F, 800002500D010C3F, 800003100D010C3F, 800003500D010C3F, 800008100D010C3F, 800008500D010C3F, 800009100D010C3F, 800009500D010C3F, 80000A500D010C3F, 80000B100D010C3F,
+static const uint64_t P9N2_PEC_1_SCOM0X10 = 0x80000B500E010C3Full;
+//DUPS: 800005100E010C3F, 800000900E010C3F, 800005500E010C3F, 80000A100E010C3F, 800000D00E010C3F, 800001900E010C3F, 800001D00E010C3F, 800003D00E010C3F, 800003900E010C3F, 800002D00E010C3F, 800002900E010C3F, 800009D00E010C3F, 800009900E010C3F, 800008D00E010C3F, 800008900E010C3F, 80000BD00E010C3F, 80000B900E010C3F, 80000AD00E010C3F, 80000A900E010C3F, 800000100E010C3F, 800000500E010C3F, 800001100E010C3F, 800001500E010C3F, 800002100E010C3F, 800002500E010C3F, 800003100E010C3F, 800003500E010C3F, 800008100E010C3F, 800008500E010C3F, 800009100E010C3F, 800009500E010C3F, 80000A500E010C3F, 80000B100E010C3F,
+static const uint64_t P9N2_PEC_2_SCOM0X10 = 0x80000B500F010C3Full;
+//DUPS: 800005100F010C3F, 800000900F010C3F, 800005500F010C3F, 80000A100F010C3F, 800000D00F010C3F, 800001900F010C3F, 800001D00F010C3F, 800003D00F010C3F, 800003900F010C3F, 800002D00F010C3F, 800002900F010C3F, 800009D00F010C3F, 800009900F010C3F, 800008D00F010C3F, 800008900F010C3F, 80000BD00F010C3F, 80000B900F010C3F, 80000AD00F010C3F, 80000A900F010C3F, 800000100F010C3F, 800000500F010C3F, 800001100F010C3F, 800001500F010C3F, 800002100F010C3F, 800002500F010C3F, 800003100F010C3F, 800003500F010C3F, 800008100F010C3F, 800008500F010C3F, 800009100F010C3F, 800009500F010C3F, 80000A500F010C3F, 80000B100F010C3F,
+
+static const uint64_t P9N2_PEC_SCOM0X11 = 0x80000B510D010C3Full;
+//DUPS: 800005110D010C3F, 800000910D010C3F, 800005510D010C3F, 80000A110D010C3F, 800000D10D010C3F, 800001910D010C3F, 800001D10D010C3F, 800003D10D010C3F, 800003910D010C3F, 800002D10D010C3F, 800002910D010C3F, 800009D10D010C3F, 800009910D010C3F, 800008D10D010C3F, 800008910D010C3F, 80000BD10D010C3F, 80000B910D010C3F, 80000AD10D010C3F, 80000A910D010C3F, 800000110D010C3F, 800000510D010C3F, 800001110D010C3F, 800001510D010C3F, 800002110D010C3F, 800002510D010C3F, 800003110D010C3F, 800003510D010C3F, 800008110D010C3F, 800008510D010C3F, 800009110D010C3F, 800009510D010C3F, 80000A510D010C3F, 80000B110D010C3F,
+static const uint64_t P9N2_PEC_0_SCOM0X11 = 0x80000B510D010C3Full;
+//DUPS: 800005110D010C3F, 800000910D010C3F, 800005510D010C3F, 80000A110D010C3F, 800000D10D010C3F, 800001910D010C3F, 800001D10D010C3F, 800003D10D010C3F, 800003910D010C3F, 800002D10D010C3F, 800002910D010C3F, 800009D10D010C3F, 800009910D010C3F, 800008D10D010C3F, 800008910D010C3F, 80000BD10D010C3F, 80000B910D010C3F, 80000AD10D010C3F, 80000A910D010C3F, 800000110D010C3F, 800000510D010C3F, 800001110D010C3F, 800001510D010C3F, 800002110D010C3F, 800002510D010C3F, 800003110D010C3F, 800003510D010C3F, 800008110D010C3F, 800008510D010C3F, 800009110D010C3F, 800009510D010C3F, 80000A510D010C3F, 80000B110D010C3F,
+static const uint64_t P9N2_PEC_1_SCOM0X11 = 0x80000B510E010C3Full;
+//DUPS: 800005110E010C3F, 800000910E010C3F, 800005510E010C3F, 80000A110E010C3F, 800000D10E010C3F, 800001910E010C3F, 800001D10E010C3F, 800003D10E010C3F, 800003910E010C3F, 800002D10E010C3F, 800002910E010C3F, 800009D10E010C3F, 800009910E010C3F, 800008D10E010C3F, 800008910E010C3F, 80000BD10E010C3F, 80000B910E010C3F, 80000AD10E010C3F, 80000A910E010C3F, 800000110E010C3F, 800000510E010C3F, 800001110E010C3F, 800001510E010C3F, 800002110E010C3F, 800002510E010C3F, 800003110E010C3F, 800003510E010C3F, 800008110E010C3F, 800008510E010C3F, 800009110E010C3F, 800009510E010C3F, 80000A510E010C3F, 80000B110E010C3F,
+static const uint64_t P9N2_PEC_2_SCOM0X11 = 0x80000B510F010C3Full;
+//DUPS: 800005110F010C3F, 800000910F010C3F, 800005510F010C3F, 80000A110F010C3F, 800000D10F010C3F, 800001910F010C3F, 800001D10F010C3F, 800003D10F010C3F, 800003910F010C3F, 800002D10F010C3F, 800002910F010C3F, 800009D10F010C3F, 800009910F010C3F, 800008D10F010C3F, 800008910F010C3F, 80000BD10F010C3F, 80000B910F010C3F, 80000AD10F010C3F, 80000A910F010C3F, 800000110F010C3F, 800000510F010C3F, 800001110F010C3F, 800001510F010C3F, 800002110F010C3F, 800002510F010C3F, 800003110F010C3F, 800003510F010C3F, 800008110F010C3F, 800008510F010C3F, 800009110F010C3F, 800009510F010C3F, 80000A510F010C3F, 80000B110F010C3F,
+
+static const uint64_t P9N2_PEC_SCOM0X12 = 0x80000B520D010C3Full;
+//DUPS: 800005120D010C3F, 800000920D010C3F, 800005520D010C3F, 80000A120D010C3F, 800000D20D010C3F, 800001920D010C3F, 800001D20D010C3F, 800003D20D010C3F, 800003920D010C3F, 800002D20D010C3F, 800002920D010C3F, 800009D20D010C3F, 800009920D010C3F, 800008D20D010C3F, 800008920D010C3F, 80000BD20D010C3F, 80000B920D010C3F, 80000AD20D010C3F, 80000A920D010C3F, 800000120D010C3F, 800000520D010C3F, 800001120D010C3F, 800001520D010C3F, 800002120D010C3F, 800002520D010C3F, 800003120D010C3F, 800003520D010C3F, 800008120D010C3F, 800008520D010C3F, 800009120D010C3F, 800009520D010C3F, 80000A520D010C3F, 80000B120D010C3F,
+static const uint64_t P9N2_PEC_0_SCOM0X12 = 0x80000B520D010C3Full;
+//DUPS: 800005120D010C3F, 800000920D010C3F, 800005520D010C3F, 80000A120D010C3F, 800000D20D010C3F, 800001920D010C3F, 800001D20D010C3F, 800003D20D010C3F, 800003920D010C3F, 800002D20D010C3F, 800002920D010C3F, 800009D20D010C3F, 800009920D010C3F, 800008D20D010C3F, 800008920D010C3F, 80000BD20D010C3F, 80000B920D010C3F, 80000AD20D010C3F, 80000A920D010C3F, 800000120D010C3F, 800000520D010C3F, 800001120D010C3F, 800001520D010C3F, 800002120D010C3F, 800002520D010C3F, 800003120D010C3F, 800003520D010C3F, 800008120D010C3F, 800008520D010C3F, 800009120D010C3F, 800009520D010C3F, 80000A520D010C3F, 80000B120D010C3F,
+static const uint64_t P9N2_PEC_1_SCOM0X12 = 0x80000B520E010C3Full;
+//DUPS: 800005120E010C3F, 800000920E010C3F, 800005520E010C3F, 80000A120E010C3F, 800000D20E010C3F, 800001920E010C3F, 800001D20E010C3F, 800003D20E010C3F, 800003920E010C3F, 800002D20E010C3F, 800002920E010C3F, 800009D20E010C3F, 800009920E010C3F, 800008D20E010C3F, 800008920E010C3F, 80000BD20E010C3F, 80000B920E010C3F, 80000AD20E010C3F, 80000A920E010C3F, 800000120E010C3F, 800000520E010C3F, 800001120E010C3F, 800001520E010C3F, 800002120E010C3F, 800002520E010C3F, 800003120E010C3F, 800003520E010C3F, 800008120E010C3F, 800008520E010C3F, 800009120E010C3F, 800009520E010C3F, 80000A520E010C3F, 80000B120E010C3F,
+static const uint64_t P9N2_PEC_2_SCOM0X12 = 0x80000B520F010C3Full;
+//DUPS: 800005120F010C3F, 800000920F010C3F, 800005520F010C3F, 80000A120F010C3F, 800000D20F010C3F, 800001920F010C3F, 800001D20F010C3F, 800003D20F010C3F, 800003920F010C3F, 800002D20F010C3F, 800002920F010C3F, 800009D20F010C3F, 800009920F010C3F, 800008D20F010C3F, 800008920F010C3F, 80000BD20F010C3F, 80000B920F010C3F, 80000AD20F010C3F, 80000A920F010C3F, 800000120F010C3F, 800000520F010C3F, 800001120F010C3F, 800001520F010C3F, 800002120F010C3F, 800002520F010C3F, 800003120F010C3F, 800003520F010C3F, 800008120F010C3F, 800008520F010C3F, 800009120F010C3F, 800009520F010C3F, 80000A520F010C3F, 80000B120F010C3F,
+
+static const uint64_t P9N2_PEC_SCOM0X13 = 0x80000B530D010C3Full;
+//DUPS: 800005130D010C3F, 800000930D010C3F, 800005530D010C3F, 80000A130D010C3F, 800000D30D010C3F, 800001930D010C3F, 800001D30D010C3F, 800003D30D010C3F, 800003930D010C3F, 800002D30D010C3F, 800002930D010C3F, 800009D30D010C3F, 800009930D010C3F, 800008D30D010C3F, 800008930D010C3F, 80000BD30D010C3F, 80000B930D010C3F, 80000AD30D010C3F, 80000A930D010C3F, 800000130D010C3F, 800000530D010C3F, 800001130D010C3F, 800001530D010C3F, 800002130D010C3F, 800002530D010C3F, 800003130D010C3F, 800003530D010C3F, 800008130D010C3F, 800008530D010C3F, 800009130D010C3F, 800009530D010C3F, 80000A530D010C3F, 80000B130D010C3F,
+static const uint64_t P9N2_PEC_0_SCOM0X13 = 0x80000B530D010C3Full;
+//DUPS: 800005130D010C3F, 800000930D010C3F, 800005530D010C3F, 80000A130D010C3F, 800000D30D010C3F, 800001930D010C3F, 800001D30D010C3F, 800003D30D010C3F, 800003930D010C3F, 800002D30D010C3F, 800002930D010C3F, 800009D30D010C3F, 800009930D010C3F, 800008D30D010C3F, 800008930D010C3F, 80000BD30D010C3F, 80000B930D010C3F, 80000AD30D010C3F, 80000A930D010C3F, 800000130D010C3F, 800000530D010C3F, 800001130D010C3F, 800001530D010C3F, 800002130D010C3F, 800002530D010C3F, 800003130D010C3F, 800003530D010C3F, 800008130D010C3F, 800008530D010C3F, 800009130D010C3F, 800009530D010C3F, 80000A530D010C3F, 80000B130D010C3F,
+static const uint64_t P9N2_PEC_1_SCOM0X13 = 0x80000B530E010C3Full;
+//DUPS: 800005130E010C3F, 800000930E010C3F, 800005530E010C3F, 80000A130E010C3F, 800000D30E010C3F, 800001930E010C3F, 800001D30E010C3F, 800003D30E010C3F, 800003930E010C3F, 800002D30E010C3F, 800002930E010C3F, 800009D30E010C3F, 800009930E010C3F, 800008D30E010C3F, 800008930E010C3F, 80000BD30E010C3F, 80000B930E010C3F, 80000AD30E010C3F, 80000A930E010C3F, 800000130E010C3F, 800000530E010C3F, 800001130E010C3F, 800001530E010C3F, 800002130E010C3F, 800002530E010C3F, 800003130E010C3F, 800003530E010C3F, 800008130E010C3F, 800008530E010C3F, 800009130E010C3F, 800009530E010C3F, 80000A530E010C3F, 80000B130E010C3F,
+static const uint64_t P9N2_PEC_2_SCOM0X13 = 0x80000B530F010C3Full;
+//DUPS: 800005130F010C3F, 800000930F010C3F, 800005530F010C3F, 80000A130F010C3F, 800000D30F010C3F, 800001930F010C3F, 800001D30F010C3F, 800003D30F010C3F, 800003930F010C3F, 800002D30F010C3F, 800002930F010C3F, 800009D30F010C3F, 800009930F010C3F, 800008D30F010C3F, 800008930F010C3F, 80000BD30F010C3F, 80000B930F010C3F, 80000AD30F010C3F, 80000A930F010C3F, 800000130F010C3F, 800000530F010C3F, 800001130F010C3F, 800001530F010C3F, 800002130F010C3F, 800002530F010C3F, 800003130F010C3F, 800003530F010C3F, 800008130F010C3F, 800008530F010C3F, 800009130F010C3F, 800009530F010C3F, 80000A530F010C3F, 80000B130F010C3F,
+
+static const uint64_t P9N2_PEC_SCOM0X14 = 0x80000B540D010C3Full;
+//DUPS: 800005140D010C3F, 800000940D010C3F, 800005540D010C3F, 80000A140D010C3F, 800000D40D010C3F, 800001940D010C3F, 800001D40D010C3F, 800003D40D010C3F, 800003940D010C3F, 800002D40D010C3F, 800002940D010C3F, 800009D40D010C3F, 800009940D010C3F, 800008D40D010C3F, 800008940D010C3F, 80000BD40D010C3F, 80000B940D010C3F, 80000AD40D010C3F, 80000A940D010C3F, 800000140D010C3F, 800000540D010C3F, 800001140D010C3F, 800001540D010C3F, 800002140D010C3F, 800002540D010C3F, 800003140D010C3F, 800003540D010C3F, 800008140D010C3F, 800008540D010C3F, 800009140D010C3F, 800009540D010C3F, 80000A540D010C3F, 80000B140D010C3F,
+static const uint64_t P9N2_PEC_0_SCOM0X14 = 0x80000B540D010C3Full;
+//DUPS: 800005140D010C3F, 800000940D010C3F, 800005540D010C3F, 80000A140D010C3F, 800000D40D010C3F, 800001940D010C3F, 800001D40D010C3F, 800003D40D010C3F, 800003940D010C3F, 800002D40D010C3F, 800002940D010C3F, 800009D40D010C3F, 800009940D010C3F, 800008D40D010C3F, 800008940D010C3F, 80000BD40D010C3F, 80000B940D010C3F, 80000AD40D010C3F, 80000A940D010C3F, 800000140D010C3F, 800000540D010C3F, 800001140D010C3F, 800001540D010C3F, 800002140D010C3F, 800002540D010C3F, 800003140D010C3F, 800003540D010C3F, 800008140D010C3F, 800008540D010C3F, 800009140D010C3F, 800009540D010C3F, 80000A540D010C3F, 80000B140D010C3F,
+static const uint64_t P9N2_PEC_1_SCOM0X14 = 0x80000B540E010C3Full;
+//DUPS: 800005140E010C3F, 800000940E010C3F, 800005540E010C3F, 80000A140E010C3F, 800000D40E010C3F, 800001940E010C3F, 800001D40E010C3F, 800003D40E010C3F, 800003940E010C3F, 800002D40E010C3F, 800002940E010C3F, 800009D40E010C3F, 800009940E010C3F, 800008D40E010C3F, 800008940E010C3F, 80000BD40E010C3F, 80000B940E010C3F, 80000AD40E010C3F, 80000A940E010C3F, 800000140E010C3F, 800000540E010C3F, 800001140E010C3F, 800001540E010C3F, 800002140E010C3F, 800002540E010C3F, 800003140E010C3F, 800003540E010C3F, 800008140E010C3F, 800008540E010C3F, 800009140E010C3F, 800009540E010C3F, 80000A540E010C3F, 80000B140E010C3F,
+static const uint64_t P9N2_PEC_2_SCOM0X14 = 0x80000B540F010C3Full;
+//DUPS: 800005140F010C3F, 800000940F010C3F, 800005540F010C3F, 80000A140F010C3F, 800000D40F010C3F, 800001940F010C3F, 800001D40F010C3F, 800003D40F010C3F, 800003940F010C3F, 800002D40F010C3F, 800002940F010C3F, 800009D40F010C3F, 800009940F010C3F, 800008D40F010C3F, 800008940F010C3F, 80000BD40F010C3F, 80000B940F010C3F, 80000AD40F010C3F, 80000A940F010C3F, 800000140F010C3F, 800000540F010C3F, 800001140F010C3F, 800001540F010C3F, 800002140F010C3F, 800002540F010C3F, 800003140F010C3F, 800003540F010C3F, 800008140F010C3F, 800008540F010C3F, 800009140F010C3F, 800009540F010C3F, 80000A540F010C3F, 80000B140F010C3F,
+
+static const uint64_t P9N2_PEC_SCOM0X15 = 0x80000B550D010C3Full;
+//DUPS: 800004150D010C3F, 800000950D010C3F, 80000A150D010C3F, 800000D50D010C3F, 800001950D010C3F, 800001D50D010C3F, 800003D50D010C3F, 800003950D010C3F, 800002D50D010C3F, 800002950D010C3F, 800009D50D010C3F, 800009950D010C3F, 800008D50D010C3F, 800008950D010C3F, 80000BD50D010C3F, 80000B950D010C3F, 80000AD50D010C3F, 80000A950D010C3F, 800000150D010C3F, 800000550D010C3F, 800001150D010C3F, 800001550D010C3F, 800002150D010C3F, 800002550D010C3F, 800003150D010C3F, 800003550D010C3F, 800008150D010C3F, 800008550D010C3F, 800009150D010C3F, 800009550D010C3F, 80000A550D010C3F, 80000B150D010C3F,
+static const uint64_t P9N2_PEC_0_SCOM0X15 = 0x80000B550D010C3Full;
+//DUPS: 800004150D010C3F, 800000950D010C3F, 80000A150D010C3F, 800000D50D010C3F, 800001950D010C3F, 800001D50D010C3F, 800003D50D010C3F, 800003950D010C3F, 800002D50D010C3F, 800002950D010C3F, 800009D50D010C3F, 800009950D010C3F, 800008D50D010C3F, 800008950D010C3F, 80000BD50D010C3F, 80000B950D010C3F, 80000AD50D010C3F, 80000A950D010C3F, 800000150D010C3F, 800000550D010C3F, 800001150D010C3F, 800001550D010C3F, 800002150D010C3F, 800002550D010C3F, 800003150D010C3F, 800003550D010C3F, 800008150D010C3F, 800008550D010C3F, 800009150D010C3F, 800009550D010C3F, 80000A550D010C3F, 80000B150D010C3F,
+static const uint64_t P9N2_PEC_1_SCOM0X15 = 0x80000B550E010C3Full;
+//DUPS: 800004150E010C3F, 800000950E010C3F, 80000A150E010C3F, 800000D50E010C3F, 800001950E010C3F, 800001D50E010C3F, 800003D50E010C3F, 800003950E010C3F, 800002D50E010C3F, 800002950E010C3F, 800009D50E010C3F, 800009950E010C3F, 800008D50E010C3F, 800008950E010C3F, 80000BD50E010C3F, 80000B950E010C3F, 80000AD50E010C3F, 80000A950E010C3F, 800000150E010C3F, 800000550E010C3F, 800001150E010C3F, 800001550E010C3F, 800002150E010C3F, 800002550E010C3F, 800003150E010C3F, 800003550E010C3F, 800008150E010C3F, 800008550E010C3F, 800009150E010C3F, 800009550E010C3F, 80000A550E010C3F, 80000B150E010C3F,
+static const uint64_t P9N2_PEC_2_SCOM0X15 = 0x80000B550F010C3Full;
+//DUPS: 800004150F010C3F, 800000950F010C3F, 80000A150F010C3F, 800000D50F010C3F, 800001950F010C3F, 800001D50F010C3F, 800003D50F010C3F, 800003950F010C3F, 800002D50F010C3F, 800002950F010C3F, 800009D50F010C3F, 800009950F010C3F, 800008D50F010C3F, 800008950F010C3F, 80000BD50F010C3F, 80000B950F010C3F, 80000AD50F010C3F, 80000A950F010C3F, 800000150F010C3F, 800000550F010C3F, 800001150F010C3F, 800001550F010C3F, 800002150F010C3F, 800002550F010C3F, 800003150F010C3F, 800003550F010C3F, 800008150F010C3F, 800008550F010C3F, 800009150F010C3F, 800009550F010C3F, 80000A550F010C3F, 80000B150F010C3F,
+
+static const uint64_t P9N2_PEC_SCOM0X16 = 0x80000B560D010C3Full;
+//DUPS: 800004160D010C3F, 800000960D010C3F, 80000A160D010C3F, 800000D60D010C3F, 800001960D010C3F, 800001D60D010C3F, 800003D60D010C3F, 800003960D010C3F, 800002D60D010C3F, 800002960D010C3F, 800009D60D010C3F, 800009960D010C3F, 800008D60D010C3F, 800008960D010C3F, 80000BD60D010C3F, 80000B960D010C3F, 80000AD60D010C3F, 80000A960D010C3F, 800000160D010C3F, 800000560D010C3F, 800001160D010C3F, 800001560D010C3F, 800002160D010C3F, 800002560D010C3F, 800003160D010C3F, 800003560D010C3F, 800008160D010C3F, 800008560D010C3F, 800009160D010C3F, 800009560D010C3F, 80000A560D010C3F, 80000B160D010C3F,
+static const uint64_t P9N2_PEC_0_SCOM0X16 = 0x80000B560D010C3Full;
+//DUPS: 800004160D010C3F, 800000960D010C3F, 80000A160D010C3F, 800000D60D010C3F, 800001960D010C3F, 800001D60D010C3F, 800003D60D010C3F, 800003960D010C3F, 800002D60D010C3F, 800002960D010C3F, 800009D60D010C3F, 800009960D010C3F, 800008D60D010C3F, 800008960D010C3F, 80000BD60D010C3F, 80000B960D010C3F, 80000AD60D010C3F, 80000A960D010C3F, 800000160D010C3F, 800000560D010C3F, 800001160D010C3F, 800001560D010C3F, 800002160D010C3F, 800002560D010C3F, 800003160D010C3F, 800003560D010C3F, 800008160D010C3F, 800008560D010C3F, 800009160D010C3F, 800009560D010C3F, 80000A560D010C3F, 80000B160D010C3F,
+static const uint64_t P9N2_PEC_1_SCOM0X16 = 0x80000B560E010C3Full;
+//DUPS: 800004160E010C3F, 800000960E010C3F, 80000A160E010C3F, 800000D60E010C3F, 800001960E010C3F, 800001D60E010C3F, 800003D60E010C3F, 800003960E010C3F, 800002D60E010C3F, 800002960E010C3F, 800009D60E010C3F, 800009960E010C3F, 800008D60E010C3F, 800008960E010C3F, 80000BD60E010C3F, 80000B960E010C3F, 80000AD60E010C3F, 80000A960E010C3F, 800000160E010C3F, 800000560E010C3F, 800001160E010C3F, 800001560E010C3F, 800002160E010C3F, 800002560E010C3F, 800003160E010C3F, 800003560E010C3F, 800008160E010C3F, 800008560E010C3F, 800009160E010C3F, 800009560E010C3F, 80000A560E010C3F, 80000B160E010C3F,
+static const uint64_t P9N2_PEC_2_SCOM0X16 = 0x80000B560F010C3Full;
+//DUPS: 800004160F010C3F, 800000960F010C3F, 80000A160F010C3F, 800000D60F010C3F, 800001960F010C3F, 800001D60F010C3F, 800003D60F010C3F, 800003960F010C3F, 800002D60F010C3F, 800002960F010C3F, 800009D60F010C3F, 800009960F010C3F, 800008D60F010C3F, 800008960F010C3F, 80000BD60F010C3F, 80000B960F010C3F, 80000AD60F010C3F, 80000A960F010C3F, 800000160F010C3F, 800000560F010C3F, 800001160F010C3F, 800001560F010C3F, 800002160F010C3F, 800002560F010C3F, 800003160F010C3F, 800003560F010C3F, 800008160F010C3F, 800008560F010C3F, 800009160F010C3F, 800009560F010C3F, 80000A560F010C3F, 80000B160F010C3F,
+
+static const uint64_t P9N2_PEC_SCOM0X17 = 0x80000B570D010C3Full;
+//DUPS: 800004170D010C3F, 800000970D010C3F, 80000A170D010C3F, 800000D70D010C3F, 800001970D010C3F, 800001D70D010C3F, 800003D70D010C3F, 800003970D010C3F, 800002D70D010C3F, 800002970D010C3F, 800009D70D010C3F, 800009970D010C3F, 800008D70D010C3F, 800008970D010C3F, 80000BD70D010C3F, 80000B970D010C3F, 80000AD70D010C3F, 80000A970D010C3F, 800000170D010C3F, 800000570D010C3F, 800001170D010C3F, 800001570D010C3F, 800002170D010C3F, 800002570D010C3F, 800003170D010C3F, 800003570D010C3F, 800008170D010C3F, 800008570D010C3F, 800009170D010C3F, 800009570D010C3F, 80000A570D010C3F, 80000B170D010C3F,
+static const uint64_t P9N2_PEC_0_SCOM0X17 = 0x80000B570D010C3Full;
+//DUPS: 800004170D010C3F, 800000970D010C3F, 80000A170D010C3F, 800000D70D010C3F, 800001970D010C3F, 800001D70D010C3F, 800003D70D010C3F, 800003970D010C3F, 800002D70D010C3F, 800002970D010C3F, 800009D70D010C3F, 800009970D010C3F, 800008D70D010C3F, 800008970D010C3F, 80000BD70D010C3F, 80000B970D010C3F, 80000AD70D010C3F, 80000A970D010C3F, 800000170D010C3F, 800000570D010C3F, 800001170D010C3F, 800001570D010C3F, 800002170D010C3F, 800002570D010C3F, 800003170D010C3F, 800003570D010C3F, 800008170D010C3F, 800008570D010C3F, 800009170D010C3F, 800009570D010C3F, 80000A570D010C3F, 80000B170D010C3F,
+static const uint64_t P9N2_PEC_1_SCOM0X17 = 0x80000B570E010C3Full;
+//DUPS: 800004170E010C3F, 800000970E010C3F, 80000A170E010C3F, 800000D70E010C3F, 800001970E010C3F, 800001D70E010C3F, 800003D70E010C3F, 800003970E010C3F, 800002D70E010C3F, 800002970E010C3F, 800009D70E010C3F, 800009970E010C3F, 800008D70E010C3F, 800008970E010C3F, 80000BD70E010C3F, 80000B970E010C3F, 80000AD70E010C3F, 80000A970E010C3F, 800000170E010C3F, 800000570E010C3F, 800001170E010C3F, 800001570E010C3F, 800002170E010C3F, 800002570E010C3F, 800003170E010C3F, 800003570E010C3F, 800008170E010C3F, 800008570E010C3F, 800009170E010C3F, 800009570E010C3F, 80000A570E010C3F, 80000B170E010C3F,
+static const uint64_t P9N2_PEC_2_SCOM0X17 = 0x80000B570F010C3Full;
+//DUPS: 800004170F010C3F, 800000970F010C3F, 80000A170F010C3F, 800000D70F010C3F, 800001970F010C3F, 800001D70F010C3F, 800003D70F010C3F, 800003970F010C3F, 800002D70F010C3F, 800002970F010C3F, 800009D70F010C3F, 800009970F010C3F, 800008D70F010C3F, 800008970F010C3F, 80000BD70F010C3F, 80000B970F010C3F, 80000AD70F010C3F, 80000A970F010C3F, 800000170F010C3F, 800000570F010C3F, 800001170F010C3F, 800001570F010C3F, 800002170F010C3F, 800002570F010C3F, 800003170F010C3F, 800003570F010C3F, 800008170F010C3F, 800008570F010C3F, 800009170F010C3F, 800009570F010C3F, 80000A570F010C3F, 80000B170F010C3F,
+
+static const uint64_t P9N2_PEC_SCOM0X18 = 0x80000B580D010C3Full;
+//DUPS: 800004180D010C3F, 800000980D010C3F, 80000A180D010C3F, 800000D80D010C3F, 800001980D010C3F, 800001D80D010C3F, 800003D80D010C3F, 800003980D010C3F, 800002D80D010C3F, 800002980D010C3F, 800009D80D010C3F, 800009980D010C3F, 800008D80D010C3F, 800008980D010C3F, 80000BD80D010C3F, 80000B980D010C3F, 80000AD80D010C3F, 80000A980D010C3F, 800000180D010C3F, 800000580D010C3F, 800001180D010C3F, 800001580D010C3F, 800002180D010C3F, 800002580D010C3F, 800003180D010C3F, 800003580D010C3F, 800008180D010C3F, 800008580D010C3F, 800009180D010C3F, 800009580D010C3F, 80000A580D010C3F, 80000B180D010C3F,
+static const uint64_t P9N2_PEC_0_SCOM0X18 = 0x80000B580D010C3Full;
+//DUPS: 800004180D010C3F, 800000980D010C3F, 80000A180D010C3F, 800000D80D010C3F, 800001980D010C3F, 800001D80D010C3F, 800003D80D010C3F, 800003980D010C3F, 800002D80D010C3F, 800002980D010C3F, 800009D80D010C3F, 800009980D010C3F, 800008D80D010C3F, 800008980D010C3F, 80000BD80D010C3F, 80000B980D010C3F, 80000AD80D010C3F, 80000A980D010C3F, 800000180D010C3F, 800000580D010C3F, 800001180D010C3F, 800001580D010C3F, 800002180D010C3F, 800002580D010C3F, 800003180D010C3F, 800003580D010C3F, 800008180D010C3F, 800008580D010C3F, 800009180D010C3F, 800009580D010C3F, 80000A580D010C3F, 80000B180D010C3F,
+static const uint64_t P9N2_PEC_1_SCOM0X18 = 0x80000B580E010C3Full;
+//DUPS: 800004180E010C3F, 800000980E010C3F, 80000A180E010C3F, 800000D80E010C3F, 800001980E010C3F, 800001D80E010C3F, 800003D80E010C3F, 800003980E010C3F, 800002D80E010C3F, 800002980E010C3F, 800009D80E010C3F, 800009980E010C3F, 800008D80E010C3F, 800008980E010C3F, 80000BD80E010C3F, 80000B980E010C3F, 80000AD80E010C3F, 80000A980E010C3F, 800000180E010C3F, 800000580E010C3F, 800001180E010C3F, 800001580E010C3F, 800002180E010C3F, 800002580E010C3F, 800003180E010C3F, 800003580E010C3F, 800008180E010C3F, 800008580E010C3F, 800009180E010C3F, 800009580E010C3F, 80000A580E010C3F, 80000B180E010C3F,
+static const uint64_t P9N2_PEC_2_SCOM0X18 = 0x80000B580F010C3Full;
+//DUPS: 800004180F010C3F, 800000980F010C3F, 80000A180F010C3F, 800000D80F010C3F, 800001980F010C3F, 800001D80F010C3F, 800003D80F010C3F, 800003980F010C3F, 800002D80F010C3F, 800002980F010C3F, 800009D80F010C3F, 800009980F010C3F, 800008D80F010C3F, 800008980F010C3F, 80000BD80F010C3F, 80000B980F010C3F, 80000AD80F010C3F, 80000A980F010C3F, 800000180F010C3F, 800000580F010C3F, 800001180F010C3F, 800001580F010C3F, 800002180F010C3F, 800002580F010C3F, 800003180F010C3F, 800003580F010C3F, 800008180F010C3F, 800008580F010C3F, 800009180F010C3F, 800009580F010C3F, 80000A580F010C3F, 80000B180F010C3F,
+
+static const uint64_t P9N2_PEC_SCOM0X19 = 0x80000B590D010C3Full;
+//DUPS: 800004190D010C3F, 800000990D010C3F, 80000A190D010C3F, 800000D90D010C3F, 800001990D010C3F, 800001D90D010C3F, 800003D90D010C3F, 800003990D010C3F, 800002D90D010C3F, 800002990D010C3F, 800009D90D010C3F, 800009990D010C3F, 800008D90D010C3F, 800008990D010C3F, 80000BD90D010C3F, 80000B990D010C3F, 80000AD90D010C3F, 80000A990D010C3F, 800000190D010C3F, 800000590D010C3F, 800001190D010C3F, 800001590D010C3F, 800002190D010C3F, 800002590D010C3F, 800003190D010C3F, 800003590D010C3F, 800008190D010C3F, 800008590D010C3F, 800009190D010C3F, 800009590D010C3F, 80000A590D010C3F, 80000B190D010C3F,
+static const uint64_t P9N2_PEC_0_SCOM0X19 = 0x80000B590D010C3Full;
+//DUPS: 800004190D010C3F, 800000990D010C3F, 80000A190D010C3F, 800000D90D010C3F, 800001990D010C3F, 800001D90D010C3F, 800003D90D010C3F, 800003990D010C3F, 800002D90D010C3F, 800002990D010C3F, 800009D90D010C3F, 800009990D010C3F, 800008D90D010C3F, 800008990D010C3F, 80000BD90D010C3F, 80000B990D010C3F, 80000AD90D010C3F, 80000A990D010C3F, 800000190D010C3F, 800000590D010C3F, 800001190D010C3F, 800001590D010C3F, 800002190D010C3F, 800002590D010C3F, 800003190D010C3F, 800003590D010C3F, 800008190D010C3F, 800008590D010C3F, 800009190D010C3F, 800009590D010C3F, 80000A590D010C3F, 80000B190D010C3F,
+static const uint64_t P9N2_PEC_1_SCOM0X19 = 0x80000B590E010C3Full;
+//DUPS: 800004190E010C3F, 800000990E010C3F, 80000A190E010C3F, 800000D90E010C3F, 800001990E010C3F, 800001D90E010C3F, 800003D90E010C3F, 800003990E010C3F, 800002D90E010C3F, 800002990E010C3F, 800009D90E010C3F, 800009990E010C3F, 800008D90E010C3F, 800008990E010C3F, 80000BD90E010C3F, 80000B990E010C3F, 80000AD90E010C3F, 80000A990E010C3F, 800000190E010C3F, 800000590E010C3F, 800001190E010C3F, 800001590E010C3F, 800002190E010C3F, 800002590E010C3F, 800003190E010C3F, 800003590E010C3F, 800008190E010C3F, 800008590E010C3F, 800009190E010C3F, 800009590E010C3F, 80000A590E010C3F, 80000B190E010C3F,
+static const uint64_t P9N2_PEC_2_SCOM0X19 = 0x80000B590F010C3Full;
+//DUPS: 800004190F010C3F, 800000990F010C3F, 80000A190F010C3F, 800000D90F010C3F, 800001990F010C3F, 800001D90F010C3F, 800003D90F010C3F, 800003990F010C3F, 800002D90F010C3F, 800002990F010C3F, 800009D90F010C3F, 800009990F010C3F, 800008D90F010C3F, 800008990F010C3F, 80000BD90F010C3F, 80000B990F010C3F, 80000AD90F010C3F, 80000A990F010C3F, 800000190F010C3F, 800000590F010C3F, 800001190F010C3F, 800001590F010C3F, 800002190F010C3F, 800002590F010C3F, 800003190F010C3F, 800003590F010C3F, 800008190F010C3F, 800008590F010C3F, 800009190F010C3F, 800009590F010C3F, 80000A590F010C3F, 80000B190F010C3F,
+
+static const uint64_t P9N2_PEC_SCOM0X1A = 0x80000B5A0D010C3Full;
+//DUPS: 8000041A0D010C3F, 8000009A0D010C3F, 80000A1A0D010C3F, 800000DA0D010C3F, 8000019A0D010C3F, 800001DA0D010C3F, 800003DA0D010C3F, 8000039A0D010C3F, 800002DA0D010C3F, 8000029A0D010C3F, 800009DA0D010C3F, 8000099A0D010C3F, 800008DA0D010C3F, 8000089A0D010C3F, 80000BDA0D010C3F, 80000B9A0D010C3F, 80000ADA0D010C3F, 80000A9A0D010C3F, 8000001A0D010C3F, 8000005A0D010C3F, 8000011A0D010C3F, 8000015A0D010C3F, 8000021A0D010C3F, 8000025A0D010C3F, 8000031A0D010C3F, 8000035A0D010C3F, 8000081A0D010C3F, 8000085A0D010C3F, 8000091A0D010C3F, 8000095A0D010C3F, 80000A5A0D010C3F, 80000B1A0D010C3F,
+static const uint64_t P9N2_PEC_0_SCOM0X1A = 0x80000B5A0D010C3Full;
+//DUPS: 8000041A0D010C3F, 8000009A0D010C3F, 80000A1A0D010C3F, 800000DA0D010C3F, 8000019A0D010C3F, 800001DA0D010C3F, 800003DA0D010C3F, 8000039A0D010C3F, 800002DA0D010C3F, 8000029A0D010C3F, 800009DA0D010C3F, 8000099A0D010C3F, 800008DA0D010C3F, 8000089A0D010C3F, 80000BDA0D010C3F, 80000B9A0D010C3F, 80000ADA0D010C3F, 80000A9A0D010C3F, 8000001A0D010C3F, 8000005A0D010C3F, 8000011A0D010C3F, 8000015A0D010C3F, 8000021A0D010C3F, 8000025A0D010C3F, 8000031A0D010C3F, 8000035A0D010C3F, 8000081A0D010C3F, 8000085A0D010C3F, 8000091A0D010C3F, 8000095A0D010C3F, 80000A5A0D010C3F, 80000B1A0D010C3F,
+static const uint64_t P9N2_PEC_1_SCOM0X1A = 0x80000B5A0E010C3Full;
+//DUPS: 8000041A0E010C3F, 8000009A0E010C3F, 80000A1A0E010C3F, 800000DA0E010C3F, 8000019A0E010C3F, 800001DA0E010C3F, 800003DA0E010C3F, 8000039A0E010C3F, 800002DA0E010C3F, 8000029A0E010C3F, 800009DA0E010C3F, 8000099A0E010C3F, 800008DA0E010C3F, 8000089A0E010C3F, 80000BDA0E010C3F, 80000B9A0E010C3F, 80000ADA0E010C3F, 80000A9A0E010C3F, 8000001A0E010C3F, 8000005A0E010C3F, 8000011A0E010C3F, 8000015A0E010C3F, 8000021A0E010C3F, 8000025A0E010C3F, 8000031A0E010C3F, 8000035A0E010C3F, 8000081A0E010C3F, 8000085A0E010C3F, 8000091A0E010C3F, 8000095A0E010C3F, 80000A5A0E010C3F, 80000B1A0E010C3F,
+static const uint64_t P9N2_PEC_2_SCOM0X1A = 0x80000B5A0F010C3Full;
+//DUPS: 8000041A0F010C3F, 8000009A0F010C3F, 80000A1A0F010C3F, 800000DA0F010C3F, 8000019A0F010C3F, 800001DA0F010C3F, 800003DA0F010C3F, 8000039A0F010C3F, 800002DA0F010C3F, 8000029A0F010C3F, 800009DA0F010C3F, 8000099A0F010C3F, 800008DA0F010C3F, 8000089A0F010C3F, 80000BDA0F010C3F, 80000B9A0F010C3F, 80000ADA0F010C3F, 80000A9A0F010C3F, 8000001A0F010C3F, 8000005A0F010C3F, 8000011A0F010C3F, 8000015A0F010C3F, 8000021A0F010C3F, 8000025A0F010C3F, 8000031A0F010C3F, 8000035A0F010C3F, 8000081A0F010C3F, 8000085A0F010C3F, 8000091A0F010C3F, 8000095A0F010C3F, 80000A5A0F010C3F, 80000B1A0F010C3F,
+
+static const uint64_t P9N2_PEC_SCOM0X1B = 0x80000B5B0D010C3Full;
+//DUPS: 8000009B0D010C3F, 80000A1B0D010C3F, 800000DB0D010C3F, 8000019B0D010C3F, 800001DB0D010C3F, 800003DB0D010C3F, 8000039B0D010C3F, 800002DB0D010C3F, 8000029B0D010C3F, 800009DB0D010C3F, 8000099B0D010C3F, 800008DB0D010C3F, 8000089B0D010C3F, 80000BDB0D010C3F, 80000B9B0D010C3F, 80000ADB0D010C3F, 80000A9B0D010C3F, 8000001B0D010C3F, 8000005B0D010C3F, 8000011B0D010C3F, 8000015B0D010C3F, 8000021B0D010C3F, 8000025B0D010C3F, 8000031B0D010C3F, 8000035B0D010C3F, 8000081B0D010C3F, 8000085B0D010C3F, 8000091B0D010C3F, 8000095B0D010C3F, 80000A5B0D010C3F, 80000B1B0D010C3F,
+static const uint64_t P9N2_PEC_0_SCOM0X1B = 0x80000B5B0D010C3Full;
+//DUPS: 8000009B0D010C3F, 80000A1B0D010C3F, 800000DB0D010C3F, 8000019B0D010C3F, 800001DB0D010C3F, 800003DB0D010C3F, 8000039B0D010C3F, 800002DB0D010C3F, 8000029B0D010C3F, 800009DB0D010C3F, 8000099B0D010C3F, 800008DB0D010C3F, 8000089B0D010C3F, 80000BDB0D010C3F, 80000B9B0D010C3F, 80000ADB0D010C3F, 80000A9B0D010C3F, 8000001B0D010C3F, 8000005B0D010C3F, 8000011B0D010C3F, 8000015B0D010C3F, 8000021B0D010C3F, 8000025B0D010C3F, 8000031B0D010C3F, 8000035B0D010C3F, 8000081B0D010C3F, 8000085B0D010C3F, 8000091B0D010C3F, 8000095B0D010C3F, 80000A5B0D010C3F, 80000B1B0D010C3F,
+static const uint64_t P9N2_PEC_1_SCOM0X1B = 0x80000B5B0E010C3Full;
+//DUPS: 8000009B0E010C3F, 80000A1B0E010C3F, 800000DB0E010C3F, 8000019B0E010C3F, 800001DB0E010C3F, 800003DB0E010C3F, 8000039B0E010C3F, 800002DB0E010C3F, 8000029B0E010C3F, 800009DB0E010C3F, 8000099B0E010C3F, 800008DB0E010C3F, 8000089B0E010C3F, 80000BDB0E010C3F, 80000B9B0E010C3F, 80000ADB0E010C3F, 80000A9B0E010C3F, 8000001B0E010C3F, 8000005B0E010C3F, 8000011B0E010C3F, 8000015B0E010C3F, 8000021B0E010C3F, 8000025B0E010C3F, 8000031B0E010C3F, 8000035B0E010C3F, 8000081B0E010C3F, 8000085B0E010C3F, 8000091B0E010C3F, 8000095B0E010C3F, 80000A5B0E010C3F, 80000B1B0E010C3F,
+static const uint64_t P9N2_PEC_2_SCOM0X1B = 0x80000B5B0F010C3Full;
+//DUPS: 8000009B0F010C3F, 80000A1B0F010C3F, 800000DB0F010C3F, 8000019B0F010C3F, 800001DB0F010C3F, 800003DB0F010C3F, 8000039B0F010C3F, 800002DB0F010C3F, 8000029B0F010C3F, 800009DB0F010C3F, 8000099B0F010C3F, 800008DB0F010C3F, 8000089B0F010C3F, 80000BDB0F010C3F, 80000B9B0F010C3F, 80000ADB0F010C3F, 80000A9B0F010C3F, 8000001B0F010C3F, 8000005B0F010C3F, 8000011B0F010C3F, 8000015B0F010C3F, 8000021B0F010C3F, 8000025B0F010C3F, 8000031B0F010C3F, 8000035B0F010C3F, 8000081B0F010C3F, 8000085B0F010C3F, 8000091B0F010C3F, 8000095B0F010C3F, 80000A5B0F010C3F, 80000B1B0F010C3F,
+
+static const uint64_t P9N2_PEC_SCOM0X1C = 0x80000BDC0D010C3Full;
+//DUPS: 800000DC0D010C3F, 8000019C0D010C3F, 800001DC0D010C3F, 800003DC0D010C3F, 8000039C0D010C3F, 800002DC0D010C3F, 8000029C0D010C3F, 800009DC0D010C3F, 8000099C0D010C3F, 800008DC0D010C3F, 8000089C0D010C3F, 80000BDC0D010C3F, 80000B9C0D010C3F, 80000ADC0D010C3F, 80000A9C0D010C3F,
+static const uint64_t P9N2_PEC_0_SCOM0X1C = 0x80000BDC0D010C3Full;
+//DUPS: 800000DC0D010C3F, 8000019C0D010C3F, 800001DC0D010C3F, 800003DC0D010C3F, 8000039C0D010C3F, 800002DC0D010C3F, 8000029C0D010C3F, 800009DC0D010C3F, 8000099C0D010C3F, 800008DC0D010C3F, 8000089C0D010C3F, 80000BDC0D010C3F, 80000B9C0D010C3F, 80000ADC0D010C3F, 80000A9C0D010C3F,
+static const uint64_t P9N2_PEC_1_SCOM0X1C = 0x80000BDC0E010C3Full;
+//DUPS: 800000DC0E010C3F, 8000019C0E010C3F, 800001DC0E010C3F, 800003DC0E010C3F, 8000039C0E010C3F, 800002DC0E010C3F, 8000029C0E010C3F, 800009DC0E010C3F, 8000099C0E010C3F, 800008DC0E010C3F, 8000089C0E010C3F, 80000BDC0E010C3F, 80000B9C0E010C3F, 80000ADC0E010C3F, 80000A9C0E010C3F,
+static const uint64_t P9N2_PEC_2_SCOM0X1C = 0x80000BDC0F010C3Full;
+//DUPS: 800000DC0F010C3F, 8000019C0F010C3F, 800001DC0F010C3F, 800003DC0F010C3F, 8000039C0F010C3F, 800002DC0F010C3F, 8000029C0F010C3F, 800009DC0F010C3F, 8000099C0F010C3F, 800008DC0F010C3F, 8000089C0F010C3F, 80000BDC0F010C3F, 80000B9C0F010C3F, 80000ADC0F010C3F, 80000A9C0F010C3F,
+
+static const uint64_t P9N2_PEC_SCOM0X1D = 0x80000BDD0D010C3Full;
+//DUPS: 800000DD0D010C3F, 8000019D0D010C3F, 800001DD0D010C3F, 800003DD0D010C3F, 8000039D0D010C3F, 800002DD0D010C3F, 8000029D0D010C3F, 800009DD0D010C3F, 8000099D0D010C3F, 800008DD0D010C3F, 8000089D0D010C3F, 80000BDD0D010C3F, 80000B9D0D010C3F, 80000ADD0D010C3F, 80000A9D0D010C3F,
+static const uint64_t P9N2_PEC_0_SCOM0X1D = 0x80000BDD0D010C3Full;
+//DUPS: 800000DD0D010C3F, 8000019D0D010C3F, 800001DD0D010C3F, 800003DD0D010C3F, 8000039D0D010C3F, 800002DD0D010C3F, 8000029D0D010C3F, 800009DD0D010C3F, 8000099D0D010C3F, 800008DD0D010C3F, 8000089D0D010C3F, 80000BDD0D010C3F, 80000B9D0D010C3F, 80000ADD0D010C3F, 80000A9D0D010C3F,
+static const uint64_t P9N2_PEC_1_SCOM0X1D = 0x80000BDD0E010C3Full;
+//DUPS: 800000DD0E010C3F, 8000019D0E010C3F, 800001DD0E010C3F, 800003DD0E010C3F, 8000039D0E010C3F, 800002DD0E010C3F, 8000029D0E010C3F, 800009DD0E010C3F, 8000099D0E010C3F, 800008DD0E010C3F, 8000089D0E010C3F, 80000BDD0E010C3F, 80000B9D0E010C3F, 80000ADD0E010C3F, 80000A9D0E010C3F,
+static const uint64_t P9N2_PEC_2_SCOM0X1D = 0x80000BDD0F010C3Full;
+//DUPS: 800000DD0F010C3F, 8000019D0F010C3F, 800001DD0F010C3F, 800003DD0F010C3F, 8000039D0F010C3F, 800002DD0F010C3F, 8000029D0F010C3F, 800009DD0F010C3F, 8000099D0F010C3F, 800008DD0F010C3F, 8000089D0F010C3F, 80000BDD0F010C3F, 80000B9D0F010C3F, 80000ADD0F010C3F, 80000A9D0F010C3F,
+
+static const uint64_t P9N2_PEC_SCOM0X1E = 0x80000B5E0D010C3Full;
+//DUPS: 8000009E0D010C3F, 80000A1E0D010C3F, 800000DE0D010C3F, 8000019E0D010C3F, 800001DE0D010C3F, 800003DE0D010C3F, 8000039E0D010C3F, 800002DE0D010C3F, 8000029E0D010C3F, 800009DE0D010C3F, 8000099E0D010C3F, 800008DE0D010C3F, 8000089E0D010C3F, 80000BDE0D010C3F, 80000B9E0D010C3F, 80000ADE0D010C3F, 80000A9E0D010C3F, 8000001E0D010C3F, 8000005E0D010C3F, 8000011E0D010C3F, 8000015E0D010C3F, 8000021E0D010C3F, 8000025E0D010C3F, 8000031E0D010C3F, 8000035E0D010C3F, 8000081E0D010C3F, 8000085E0D010C3F, 8000091E0D010C3F, 8000095E0D010C3F, 80000A5E0D010C3F, 80000B1E0D010C3F,
+static const uint64_t P9N2_PEC_0_SCOM0X1E = 0x80000B5E0D010C3Full;
+//DUPS: 8000009E0D010C3F, 80000A1E0D010C3F, 800000DE0D010C3F, 8000019E0D010C3F, 800001DE0D010C3F, 800003DE0D010C3F, 8000039E0D010C3F, 800002DE0D010C3F, 8000029E0D010C3F, 800009DE0D010C3F, 8000099E0D010C3F, 800008DE0D010C3F, 8000089E0D010C3F, 80000BDE0D010C3F, 80000B9E0D010C3F, 80000ADE0D010C3F, 80000A9E0D010C3F, 8000001E0D010C3F, 8000005E0D010C3F, 8000011E0D010C3F, 8000015E0D010C3F, 8000021E0D010C3F, 8000025E0D010C3F, 8000031E0D010C3F, 8000035E0D010C3F, 8000081E0D010C3F, 8000085E0D010C3F, 8000091E0D010C3F, 8000095E0D010C3F, 80000A5E0D010C3F, 80000B1E0D010C3F,
+static const uint64_t P9N2_PEC_1_SCOM0X1E = 0x80000B5E0E010C3Full;
+//DUPS: 8000009E0E010C3F, 80000A1E0E010C3F, 800000DE0E010C3F, 8000019E0E010C3F, 800001DE0E010C3F, 800003DE0E010C3F, 8000039E0E010C3F, 800002DE0E010C3F, 8000029E0E010C3F, 800009DE0E010C3F, 8000099E0E010C3F, 800008DE0E010C3F, 8000089E0E010C3F, 80000BDE0E010C3F, 80000B9E0E010C3F, 80000ADE0E010C3F, 80000A9E0E010C3F, 8000001E0E010C3F, 8000005E0E010C3F, 8000011E0E010C3F, 8000015E0E010C3F, 8000021E0E010C3F, 8000025E0E010C3F, 8000031E0E010C3F, 8000035E0E010C3F, 8000081E0E010C3F, 8000085E0E010C3F, 8000091E0E010C3F, 8000095E0E010C3F, 80000A5E0E010C3F, 80000B1E0E010C3F,
+static const uint64_t P9N2_PEC_2_SCOM0X1E = 0x80000B5E0F010C3Full;
+//DUPS: 8000009E0F010C3F, 80000A1E0F010C3F, 800000DE0F010C3F, 8000019E0F010C3F, 800001DE0F010C3F, 800003DE0F010C3F, 8000039E0F010C3F, 800002DE0F010C3F, 8000029E0F010C3F, 800009DE0F010C3F, 8000099E0F010C3F, 800008DE0F010C3F, 8000089E0F010C3F, 80000BDE0F010C3F, 80000B9E0F010C3F, 80000ADE0F010C3F, 80000A9E0F010C3F, 8000001E0F010C3F, 8000005E0F010C3F, 8000011E0F010C3F, 8000015E0F010C3F, 8000021E0F010C3F, 8000025E0F010C3F, 8000031E0F010C3F, 8000035E0F010C3F, 8000081E0F010C3F, 8000085E0F010C3F, 8000091E0F010C3F, 8000095E0F010C3F, 80000A5E0F010C3F, 80000B1E0F010C3F,
+
+static const uint64_t P9N2_PEC_SCOM0X1F = 0x80000B5F0D010C3Full;
+//DUPS: 8000009F0D010C3F, 80000A1F0D010C3F, 800000DF0D010C3F, 8000019F0D010C3F, 800001DF0D010C3F, 800003DF0D010C3F, 8000039F0D010C3F, 800002DF0D010C3F, 8000029F0D010C3F, 800009DF0D010C3F, 8000099F0D010C3F, 800008DF0D010C3F, 8000089F0D010C3F, 80000BDF0D010C3F, 80000B9F0D010C3F, 80000ADF0D010C3F, 80000A9F0D010C3F, 8000001F0D010C3F, 8000005F0D010C3F, 8000011F0D010C3F, 8000015F0D010C3F, 8000021F0D010C3F, 8000025F0D010C3F, 8000031F0D010C3F, 8000035F0D010C3F, 8000081F0D010C3F, 8000085F0D010C3F, 8000091F0D010C3F, 8000095F0D010C3F, 80000A5F0D010C3F, 80000B1F0D010C3F,
+static const uint64_t P9N2_PEC_0_SCOM0X1F = 0x80000B5F0D010C3Full;
+//DUPS: 8000009F0D010C3F, 80000A1F0D010C3F, 800000DF0D010C3F, 8000019F0D010C3F, 800001DF0D010C3F, 800003DF0D010C3F, 8000039F0D010C3F, 800002DF0D010C3F, 8000029F0D010C3F, 800009DF0D010C3F, 8000099F0D010C3F, 800008DF0D010C3F, 8000089F0D010C3F, 80000BDF0D010C3F, 80000B9F0D010C3F, 80000ADF0D010C3F, 80000A9F0D010C3F, 8000001F0D010C3F, 8000005F0D010C3F, 8000011F0D010C3F, 8000015F0D010C3F, 8000021F0D010C3F, 8000025F0D010C3F, 8000031F0D010C3F, 8000035F0D010C3F, 8000081F0D010C3F, 8000085F0D010C3F, 8000091F0D010C3F, 8000095F0D010C3F, 80000A5F0D010C3F, 80000B1F0D010C3F,
+static const uint64_t P9N2_PEC_1_SCOM0X1F = 0x80000B5F0E010C3Full;
+//DUPS: 8000009F0E010C3F, 80000A1F0E010C3F, 800000DF0E010C3F, 8000019F0E010C3F, 800001DF0E010C3F, 800003DF0E010C3F, 8000039F0E010C3F, 800002DF0E010C3F, 8000029F0E010C3F, 800009DF0E010C3F, 8000099F0E010C3F, 800008DF0E010C3F, 8000089F0E010C3F, 80000BDF0E010C3F, 80000B9F0E010C3F, 80000ADF0E010C3F, 80000A9F0E010C3F, 8000001F0E010C3F, 8000005F0E010C3F, 8000011F0E010C3F, 8000015F0E010C3F, 8000021F0E010C3F, 8000025F0E010C3F, 8000031F0E010C3F, 8000035F0E010C3F, 8000081F0E010C3F, 8000085F0E010C3F, 8000091F0E010C3F, 8000095F0E010C3F, 80000A5F0E010C3F, 80000B1F0E010C3F,
+static const uint64_t P9N2_PEC_2_SCOM0X1F = 0x80000B5F0F010C3Full;
+//DUPS: 8000009F0F010C3F, 80000A1F0F010C3F, 800000DF0F010C3F, 8000019F0F010C3F, 800001DF0F010C3F, 800003DF0F010C3F, 8000039F0F010C3F, 800002DF0F010C3F, 8000029F0F010C3F, 800009DF0F010C3F, 8000099F0F010C3F, 800008DF0F010C3F, 8000089F0F010C3F, 80000BDF0F010C3F, 80000B9F0F010C3F, 80000ADF0F010C3F, 80000A9F0F010C3F, 8000001F0F010C3F, 8000005F0F010C3F, 8000011F0F010C3F, 8000015F0F010C3F, 8000021F0F010C3F, 8000025F0F010C3F, 8000031F0F010C3F, 8000035F0F010C3F, 8000081F0F010C3F, 8000085F0F010C3F, 8000091F0F010C3F, 8000095F0F010C3F, 80000A5F0F010C3F, 80000B1F0F010C3F,
+
+static const uint64_t P9N2_PEC_SCOM0X20 = 0x80000B600D010C3Full;
+//DUPS: 800000A00D010C3F, 800004200D010C3F, 80000A200D010C3F, 800000E00D010C3F, 800001A00D010C3F, 800001E00D010C3F, 800003E00D010C3F, 800003A00D010C3F, 800002E00D010C3F, 800002A00D010C3F, 800009E00D010C3F, 800009A00D010C3F, 800008E00D010C3F, 800008A00D010C3F, 80000BE00D010C3F, 80000BA00D010C3F, 80000AE00D010C3F, 80000AA00D010C3F, 800000200D010C3F, 800000600D010C3F, 800001200D010C3F, 800001600D010C3F, 800002200D010C3F, 800002600D010C3F, 800003200D010C3F, 800003600D010C3F, 800008200D010C3F, 800008600D010C3F, 800009200D010C3F, 800009600D010C3F, 80000A600D010C3F, 80000B200D010C3F,
+static const uint64_t P9N2_PEC_0_SCOM0X20 = 0x80000B600D010C3Full;
+//DUPS: 800000A00D010C3F, 800004200D010C3F, 80000A200D010C3F, 800000E00D010C3F, 800001A00D010C3F, 800001E00D010C3F, 800003E00D010C3F, 800003A00D010C3F, 800002E00D010C3F, 800002A00D010C3F, 800009E00D010C3F, 800009A00D010C3F, 800008E00D010C3F, 800008A00D010C3F, 80000BE00D010C3F, 80000BA00D010C3F, 80000AE00D010C3F, 80000AA00D010C3F, 800000200D010C3F, 800000600D010C3F, 800001200D010C3F, 800001600D010C3F, 800002200D010C3F, 800002600D010C3F, 800003200D010C3F, 800003600D010C3F, 800008200D010C3F, 800008600D010C3F, 800009200D010C3F, 800009600D010C3F, 80000A600D010C3F, 80000B200D010C3F,
+static const uint64_t P9N2_PEC_1_SCOM0X20 = 0x80000B600E010C3Full;
+//DUPS: 800000A00E010C3F, 800004200E010C3F, 80000A200E010C3F, 800000E00E010C3F, 800001A00E010C3F, 800001E00E010C3F, 800003E00E010C3F, 800003A00E010C3F, 800002E00E010C3F, 800002A00E010C3F, 800009E00E010C3F, 800009A00E010C3F, 800008E00E010C3F, 800008A00E010C3F, 80000BE00E010C3F, 80000BA00E010C3F, 80000AE00E010C3F, 80000AA00E010C3F, 800000200E010C3F, 800000600E010C3F, 800001200E010C3F, 800001600E010C3F, 800002200E010C3F, 800002600E010C3F, 800003200E010C3F, 800003600E010C3F, 800008200E010C3F, 800008600E010C3F, 800009200E010C3F, 800009600E010C3F, 80000A600E010C3F, 80000B200E010C3F,
+static const uint64_t P9N2_PEC_2_SCOM0X20 = 0x80000B600F010C3Full;
+//DUPS: 800000A00F010C3F, 800004200F010C3F, 80000A200F010C3F, 800000E00F010C3F, 800001A00F010C3F, 800001E00F010C3F, 800003E00F010C3F, 800003A00F010C3F, 800002E00F010C3F, 800002A00F010C3F, 800009E00F010C3F, 800009A00F010C3F, 800008E00F010C3F, 800008A00F010C3F, 80000BE00F010C3F, 80000BA00F010C3F, 80000AE00F010C3F, 80000AA00F010C3F, 800000200F010C3F, 800000600F010C3F, 800001200F010C3F, 800001600F010C3F, 800002200F010C3F, 800002600F010C3F, 800003200F010C3F, 800003600F010C3F, 800008200F010C3F, 800008600F010C3F, 800009200F010C3F, 800009600F010C3F, 80000A600F010C3F, 80000B200F010C3F,
+
+static const uint64_t P9N2_PEC_SCOM0X21 = 0x80000B610D010C3Full;
+//DUPS: 800000A10D010C3F, 800004210D010C3F, 80000A210D010C3F, 800000E10D010C3F, 800001A10D010C3F, 800001E10D010C3F, 800003E10D010C3F, 800003A10D010C3F, 800002E10D010C3F, 800002A10D010C3F, 800009E10D010C3F, 800009A10D010C3F, 800008E10D010C3F, 800008A10D010C3F, 80000BE10D010C3F, 80000BA10D010C3F, 80000AE10D010C3F, 80000AA10D010C3F, 800000210D010C3F, 800000610D010C3F, 800001210D010C3F, 800001610D010C3F, 800002210D010C3F, 800002610D010C3F, 800003210D010C3F, 800003610D010C3F, 800008210D010C3F, 800008610D010C3F, 800009210D010C3F, 800009610D010C3F, 80000A610D010C3F, 80000B210D010C3F,
+static const uint64_t P9N2_PEC_0_SCOM0X21 = 0x80000B610D010C3Full;
+//DUPS: 800000A10D010C3F, 800004210D010C3F, 80000A210D010C3F, 800000E10D010C3F, 800001A10D010C3F, 800001E10D010C3F, 800003E10D010C3F, 800003A10D010C3F, 800002E10D010C3F, 800002A10D010C3F, 800009E10D010C3F, 800009A10D010C3F, 800008E10D010C3F, 800008A10D010C3F, 80000BE10D010C3F, 80000BA10D010C3F, 80000AE10D010C3F, 80000AA10D010C3F, 800000210D010C3F, 800000610D010C3F, 800001210D010C3F, 800001610D010C3F, 800002210D010C3F, 800002610D010C3F, 800003210D010C3F, 800003610D010C3F, 800008210D010C3F, 800008610D010C3F, 800009210D010C3F, 800009610D010C3F, 80000A610D010C3F, 80000B210D010C3F,
+static const uint64_t P9N2_PEC_1_SCOM0X21 = 0x80000B610E010C3Full;
+//DUPS: 800000A10E010C3F, 800004210E010C3F, 80000A210E010C3F, 800000E10E010C3F, 800001A10E010C3F, 800001E10E010C3F, 800003E10E010C3F, 800003A10E010C3F, 800002E10E010C3F, 800002A10E010C3F, 800009E10E010C3F, 800009A10E010C3F, 800008E10E010C3F, 800008A10E010C3F, 80000BE10E010C3F, 80000BA10E010C3F, 80000AE10E010C3F, 80000AA10E010C3F, 800000210E010C3F, 800000610E010C3F, 800001210E010C3F, 800001610E010C3F, 800002210E010C3F, 800002610E010C3F, 800003210E010C3F, 800003610E010C3F, 800008210E010C3F, 800008610E010C3F, 800009210E010C3F, 800009610E010C3F, 80000A610E010C3F, 80000B210E010C3F,
+static const uint64_t P9N2_PEC_2_SCOM0X21 = 0x80000B610F010C3Full;
+//DUPS: 800000A10F010C3F, 800004210F010C3F, 80000A210F010C3F, 800000E10F010C3F, 800001A10F010C3F, 800001E10F010C3F, 800003E10F010C3F, 800003A10F010C3F, 800002E10F010C3F, 800002A10F010C3F, 800009E10F010C3F, 800009A10F010C3F, 800008E10F010C3F, 800008A10F010C3F, 80000BE10F010C3F, 80000BA10F010C3F, 80000AE10F010C3F, 80000AA10F010C3F, 800000210F010C3F, 800000610F010C3F, 800001210F010C3F, 800001610F010C3F, 800002210F010C3F, 800002610F010C3F, 800003210F010C3F, 800003610F010C3F, 800008210F010C3F, 800008610F010C3F, 800009210F010C3F, 800009610F010C3F, 80000A610F010C3F, 80000B210F010C3F,
+
+static const uint64_t P9N2_PEC_SCOM0X22 = 0x80000B620D010C3Full;
+//DUPS: 800000A20D010C3F, 800004220D010C3F, 80000A220D010C3F, 800000E20D010C3F, 800001A20D010C3F, 800001E20D010C3F, 800003E20D010C3F, 800003A20D010C3F, 800002E20D010C3F, 800002A20D010C3F, 800009E20D010C3F, 800009A20D010C3F, 800008E20D010C3F, 800008A20D010C3F, 80000BE20D010C3F, 80000BA20D010C3F, 80000AE20D010C3F, 80000AA20D010C3F, 800000220D010C3F, 800000620D010C3F, 800001220D010C3F, 800001620D010C3F, 800002220D010C3F, 800002620D010C3F, 800003220D010C3F, 800003620D010C3F, 800008220D010C3F, 800008620D010C3F, 800009220D010C3F, 800009620D010C3F, 80000A620D010C3F, 80000B220D010C3F,
+static const uint64_t P9N2_PEC_0_SCOM0X22 = 0x80000B620D010C3Full;
+//DUPS: 800000A20D010C3F, 800004220D010C3F, 80000A220D010C3F, 800000E20D010C3F, 800001A20D010C3F, 800001E20D010C3F, 800003E20D010C3F, 800003A20D010C3F, 800002E20D010C3F, 800002A20D010C3F, 800009E20D010C3F, 800009A20D010C3F, 800008E20D010C3F, 800008A20D010C3F, 80000BE20D010C3F, 80000BA20D010C3F, 80000AE20D010C3F, 80000AA20D010C3F, 800000220D010C3F, 800000620D010C3F, 800001220D010C3F, 800001620D010C3F, 800002220D010C3F, 800002620D010C3F, 800003220D010C3F, 800003620D010C3F, 800008220D010C3F, 800008620D010C3F, 800009220D010C3F, 800009620D010C3F, 80000A620D010C3F, 80000B220D010C3F,
+static const uint64_t P9N2_PEC_1_SCOM0X22 = 0x80000B620E010C3Full;
+//DUPS: 800000A20E010C3F, 800004220E010C3F, 80000A220E010C3F, 800000E20E010C3F, 800001A20E010C3F, 800001E20E010C3F, 800003E20E010C3F, 800003A20E010C3F, 800002E20E010C3F, 800002A20E010C3F, 800009E20E010C3F, 800009A20E010C3F, 800008E20E010C3F, 800008A20E010C3F, 80000BE20E010C3F, 80000BA20E010C3F, 80000AE20E010C3F, 80000AA20E010C3F, 800000220E010C3F, 800000620E010C3F, 800001220E010C3F, 800001620E010C3F, 800002220E010C3F, 800002620E010C3F, 800003220E010C3F, 800003620E010C3F, 800008220E010C3F, 800008620E010C3F, 800009220E010C3F, 800009620E010C3F, 80000A620E010C3F, 80000B220E010C3F,
+static const uint64_t P9N2_PEC_2_SCOM0X22 = 0x80000B620F010C3Full;
+//DUPS: 800000A20F010C3F, 800004220F010C3F, 80000A220F010C3F, 800000E20F010C3F, 800001A20F010C3F, 800001E20F010C3F, 800003E20F010C3F, 800003A20F010C3F, 800002E20F010C3F, 800002A20F010C3F, 800009E20F010C3F, 800009A20F010C3F, 800008E20F010C3F, 800008A20F010C3F, 80000BE20F010C3F, 80000BA20F010C3F, 80000AE20F010C3F, 80000AA20F010C3F, 800000220F010C3F, 800000620F010C3F, 800001220F010C3F, 800001620F010C3F, 800002220F010C3F, 800002620F010C3F, 800003220F010C3F, 800003620F010C3F, 800008220F010C3F, 800008620F010C3F, 800009220F010C3F, 800009620F010C3F, 80000A620F010C3F, 80000B220F010C3F,
+
+static const uint64_t P9N2_PEC_SCOM0X23 = 0x80000B630D010C3Full;
+//DUPS: 800000A30D010C3F, 80000A230D010C3F, 800000E30D010C3F, 800001A30D010C3F, 800001E30D010C3F, 800003E30D010C3F, 800003A30D010C3F, 800002E30D010C3F, 800002A30D010C3F, 800009E30D010C3F, 800009A30D010C3F, 800008E30D010C3F, 800008A30D010C3F, 80000BE30D010C3F, 80000BA30D010C3F, 80000AE30D010C3F, 80000AA30D010C3F, 800000230D010C3F, 800000630D010C3F, 800001230D010C3F, 800001630D010C3F, 800002230D010C3F, 800002630D010C3F, 800003230D010C3F, 800003630D010C3F, 800008230D010C3F, 800008630D010C3F, 800009230D010C3F, 800009630D010C3F, 80000A630D010C3F, 80000B230D010C3F,
+static const uint64_t P9N2_PEC_0_SCOM0X23 = 0x80000B630D010C3Full;
+//DUPS: 800000A30D010C3F, 80000A230D010C3F, 800000E30D010C3F, 800001A30D010C3F, 800001E30D010C3F, 800003E30D010C3F, 800003A30D010C3F, 800002E30D010C3F, 800002A30D010C3F, 800009E30D010C3F, 800009A30D010C3F, 800008E30D010C3F, 800008A30D010C3F, 80000BE30D010C3F, 80000BA30D010C3F, 80000AE30D010C3F, 80000AA30D010C3F, 800000230D010C3F, 800000630D010C3F, 800001230D010C3F, 800001630D010C3F, 800002230D010C3F, 800002630D010C3F, 800003230D010C3F, 800003630D010C3F, 800008230D010C3F, 800008630D010C3F, 800009230D010C3F, 800009630D010C3F, 80000A630D010C3F, 80000B230D010C3F,
+static const uint64_t P9N2_PEC_1_SCOM0X23 = 0x80000B630E010C3Full;
+//DUPS: 800000A30E010C3F, 80000A230E010C3F, 800000E30E010C3F, 800001A30E010C3F, 800001E30E010C3F, 800003E30E010C3F, 800003A30E010C3F, 800002E30E010C3F, 800002A30E010C3F, 800009E30E010C3F, 800009A30E010C3F, 800008E30E010C3F, 800008A30E010C3F, 80000BE30E010C3F, 80000BA30E010C3F, 80000AE30E010C3F, 80000AA30E010C3F, 800000230E010C3F, 800000630E010C3F, 800001230E010C3F, 800001630E010C3F, 800002230E010C3F, 800002630E010C3F, 800003230E010C3F, 800003630E010C3F, 800008230E010C3F, 800008630E010C3F, 800009230E010C3F, 800009630E010C3F, 80000A630E010C3F, 80000B230E010C3F,
+static const uint64_t P9N2_PEC_2_SCOM0X23 = 0x80000B630F010C3Full;
+//DUPS: 800000A30F010C3F, 80000A230F010C3F, 800000E30F010C3F, 800001A30F010C3F, 800001E30F010C3F, 800003E30F010C3F, 800003A30F010C3F, 800002E30F010C3F, 800002A30F010C3F, 800009E30F010C3F, 800009A30F010C3F, 800008E30F010C3F, 800008A30F010C3F, 80000BE30F010C3F, 80000BA30F010C3F, 80000AE30F010C3F, 80000AA30F010C3F, 800000230F010C3F, 800000630F010C3F, 800001230F010C3F, 800001630F010C3F, 800002230F010C3F, 800002630F010C3F, 800003230F010C3F, 800003630F010C3F, 800008230F010C3F, 800008630F010C3F, 800009230F010C3F, 800009630F010C3F, 80000A630F010C3F, 80000B230F010C3F,
+
+static const uint64_t P9N2_PEC_SCOM0X24 = 0x80000BE40D010C3Full;
+//DUPS: 800000E40D010C3F, 800001A40D010C3F, 800001E40D010C3F, 800003E40D010C3F, 800003A40D010C3F, 800002E40D010C3F, 800002A40D010C3F, 800009E40D010C3F, 800009A40D010C3F, 800008E40D010C3F, 800008A40D010C3F, 80000BE40D010C3F, 80000BA40D010C3F, 80000AE40D010C3F, 80000AA40D010C3F,
+static const uint64_t P9N2_PEC_0_SCOM0X24 = 0x80000BE40D010C3Full;
+//DUPS: 800000E40D010C3F, 800001A40D010C3F, 800001E40D010C3F, 800003E40D010C3F, 800003A40D010C3F, 800002E40D010C3F, 800002A40D010C3F, 800009E40D010C3F, 800009A40D010C3F, 800008E40D010C3F, 800008A40D010C3F, 80000BE40D010C3F, 80000BA40D010C3F, 80000AE40D010C3F, 80000AA40D010C3F,
+static const uint64_t P9N2_PEC_1_SCOM0X24 = 0x80000BE40E010C3Full;
+//DUPS: 800000E40E010C3F, 800001A40E010C3F, 800001E40E010C3F, 800003E40E010C3F, 800003A40E010C3F, 800002E40E010C3F, 800002A40E010C3F, 800009E40E010C3F, 800009A40E010C3F, 800008E40E010C3F, 800008A40E010C3F, 80000BE40E010C3F, 80000BA40E010C3F, 80000AE40E010C3F, 80000AA40E010C3F,
+static const uint64_t P9N2_PEC_2_SCOM0X24 = 0x80000BE40F010C3Full;
+//DUPS: 800000E40F010C3F, 800001A40F010C3F, 800001E40F010C3F, 800003E40F010C3F, 800003A40F010C3F, 800002E40F010C3F, 800002A40F010C3F, 800009E40F010C3F, 800009A40F010C3F, 800008E40F010C3F, 800008A40F010C3F, 80000BE40F010C3F, 80000BA40F010C3F, 80000AE40F010C3F, 80000AA40F010C3F,
+
+static const uint64_t P9N2_PEC_SCOM0X25 = 0x80000BE50D010C3Full;
+//DUPS: 800000E50D010C3F, 800001A50D010C3F, 800001E50D010C3F, 800003E50D010C3F, 800003A50D010C3F, 800002E50D010C3F, 800002A50D010C3F, 800009E50D010C3F, 800009A50D010C3F, 800008E50D010C3F, 800008A50D010C3F, 80000BE50D010C3F, 80000BA50D010C3F, 80000AE50D010C3F, 80000AA50D010C3F,
+static const uint64_t P9N2_PEC_0_SCOM0X25 = 0x80000BE50D010C3Full;
+//DUPS: 800000E50D010C3F, 800001A50D010C3F, 800001E50D010C3F, 800003E50D010C3F, 800003A50D010C3F, 800002E50D010C3F, 800002A50D010C3F, 800009E50D010C3F, 800009A50D010C3F, 800008E50D010C3F, 800008A50D010C3F, 80000BE50D010C3F, 80000BA50D010C3F, 80000AE50D010C3F, 80000AA50D010C3F,
+static const uint64_t P9N2_PEC_1_SCOM0X25 = 0x80000BE50E010C3Full;
+//DUPS: 800000E50E010C3F, 800001A50E010C3F, 800001E50E010C3F, 800003E50E010C3F, 800003A50E010C3F, 800002E50E010C3F, 800002A50E010C3F, 800009E50E010C3F, 800009A50E010C3F, 800008E50E010C3F, 800008A50E010C3F, 80000BE50E010C3F, 80000BA50E010C3F, 80000AE50E010C3F, 80000AA50E010C3F,
+static const uint64_t P9N2_PEC_2_SCOM0X25 = 0x80000BE50F010C3Full;
+//DUPS: 800000E50F010C3F, 800001A50F010C3F, 800001E50F010C3F, 800003E50F010C3F, 800003A50F010C3F, 800002E50F010C3F, 800002A50F010C3F, 800009E50F010C3F, 800009A50F010C3F, 800008E50F010C3F, 800008A50F010C3F, 80000BE50F010C3F, 80000BA50F010C3F, 80000AE50F010C3F, 80000AA50F010C3F,
+
+static const uint64_t P9N2_PEC_SCOM0X26 = 0x80000BE60D010C3Full;
+//DUPS: 800000E60D010C3F, 800001A60D010C3F, 800001E60D010C3F, 800003E60D010C3F, 800003A60D010C3F, 800002E60D010C3F, 800002A60D010C3F, 800009E60D010C3F, 800009A60D010C3F, 800008E60D010C3F, 800008A60D010C3F, 80000BE60D010C3F, 80000BA60D010C3F, 80000AE60D010C3F, 80000AA60D010C3F,
+static const uint64_t P9N2_PEC_0_SCOM0X26 = 0x80000BE60D010C3Full;
+//DUPS: 800000E60D010C3F, 800001A60D010C3F, 800001E60D010C3F, 800003E60D010C3F, 800003A60D010C3F, 800002E60D010C3F, 800002A60D010C3F, 800009E60D010C3F, 800009A60D010C3F, 800008E60D010C3F, 800008A60D010C3F, 80000BE60D010C3F, 80000BA60D010C3F, 80000AE60D010C3F, 80000AA60D010C3F,
+static const uint64_t P9N2_PEC_1_SCOM0X26 = 0x80000BE60E010C3Full;
+//DUPS: 800000E60E010C3F, 800001A60E010C3F, 800001E60E010C3F, 800003E60E010C3F, 800003A60E010C3F, 800002E60E010C3F, 800002A60E010C3F, 800009E60E010C3F, 800009A60E010C3F, 800008E60E010C3F, 800008A60E010C3F, 80000BE60E010C3F, 80000BA60E010C3F, 80000AE60E010C3F, 80000AA60E010C3F,
+static const uint64_t P9N2_PEC_2_SCOM0X26 = 0x80000BE60F010C3Full;
+//DUPS: 800000E60F010C3F, 800001A60F010C3F, 800001E60F010C3F, 800003E60F010C3F, 800003A60F010C3F, 800002E60F010C3F, 800002A60F010C3F, 800009E60F010C3F, 800009A60F010C3F, 800008E60F010C3F, 800008A60F010C3F, 80000BE60F010C3F, 80000BA60F010C3F, 80000AE60F010C3F, 80000AA60F010C3F,
+
+static const uint64_t P9N2_PEC_SCOM0X27 = 0x80000BE70D010C3Full;
+//DUPS: 800000E70D010C3F, 800001A70D010C3F, 800001E70D010C3F, 800003E70D010C3F, 800003A70D010C3F, 800002E70D010C3F, 800002A70D010C3F, 800009E70D010C3F, 800009A70D010C3F, 800008E70D010C3F, 800008A70D010C3F, 80000BE70D010C3F, 80000BA70D010C3F, 80000AE70D010C3F, 80000AA70D010C3F,
+static const uint64_t P9N2_PEC_0_SCOM0X27 = 0x80000BE70D010C3Full;
+//DUPS: 800000E70D010C3F, 800001A70D010C3F, 800001E70D010C3F, 800003E70D010C3F, 800003A70D010C3F, 800002E70D010C3F, 800002A70D010C3F, 800009E70D010C3F, 800009A70D010C3F, 800008E70D010C3F, 800008A70D010C3F, 80000BE70D010C3F, 80000BA70D010C3F, 80000AE70D010C3F, 80000AA70D010C3F,
+static const uint64_t P9N2_PEC_1_SCOM0X27 = 0x80000BE70E010C3Full;
+//DUPS: 800000E70E010C3F, 800001A70E010C3F, 800001E70E010C3F, 800003E70E010C3F, 800003A70E010C3F, 800002E70E010C3F, 800002A70E010C3F, 800009E70E010C3F, 800009A70E010C3F, 800008E70E010C3F, 800008A70E010C3F, 80000BE70E010C3F, 80000BA70E010C3F, 80000AE70E010C3F, 80000AA70E010C3F,
+static const uint64_t P9N2_PEC_2_SCOM0X27 = 0x80000BE70F010C3Full;
+//DUPS: 800000E70F010C3F, 800001A70F010C3F, 800001E70F010C3F, 800003E70F010C3F, 800003A70F010C3F, 800002E70F010C3F, 800002A70F010C3F, 800009E70F010C3F, 800009A70F010C3F, 800008E70F010C3F, 800008A70F010C3F, 80000BE70F010C3F, 80000BA70F010C3F, 80000AE70F010C3F, 80000AA70F010C3F,
+
+static const uint64_t P9N2_PEC_SCOM0X28 = 0x80000B680D010C3Full;
+//DUPS: 800000A80D010C3F, 80000A280D010C3F, 800000E80D010C3F, 800001A80D010C3F, 800001E80D010C3F, 800003E80D010C3F, 800003A80D010C3F, 800002E80D010C3F, 800002A80D010C3F, 800009E80D010C3F, 800009A80D010C3F, 800008E80D010C3F, 800008A80D010C3F, 80000BE80D010C3F, 80000BA80D010C3F, 80000AE80D010C3F, 80000AA80D010C3F, 800000280D010C3F, 800000680D010C3F, 800001280D010C3F, 800001680D010C3F, 800002280D010C3F, 800002680D010C3F, 800003280D010C3F, 800003680D010C3F, 800008280D010C3F, 800008680D010C3F, 800009280D010C3F, 800009680D010C3F, 80000A680D010C3F, 80000B280D010C3F,
+static const uint64_t P9N2_PEC_0_SCOM0X28 = 0x80000B680D010C3Full;
+//DUPS: 800000A80D010C3F, 80000A280D010C3F, 800000E80D010C3F, 800001A80D010C3F, 800001E80D010C3F, 800003E80D010C3F, 800003A80D010C3F, 800002E80D010C3F, 800002A80D010C3F, 800009E80D010C3F, 800009A80D010C3F, 800008E80D010C3F, 800008A80D010C3F, 80000BE80D010C3F, 80000BA80D010C3F, 80000AE80D010C3F, 80000AA80D010C3F, 800000280D010C3F, 800000680D010C3F, 800001280D010C3F, 800001680D010C3F, 800002280D010C3F, 800002680D010C3F, 800003280D010C3F, 800003680D010C3F, 800008280D010C3F, 800008680D010C3F, 800009280D010C3F, 800009680D010C3F, 80000A680D010C3F, 80000B280D010C3F,
+static const uint64_t P9N2_PEC_1_SCOM0X28 = 0x80000B680E010C3Full;
+//DUPS: 800000A80E010C3F, 80000A280E010C3F, 800000E80E010C3F, 800001A80E010C3F, 800001E80E010C3F, 800003E80E010C3F, 800003A80E010C3F, 800002E80E010C3F, 800002A80E010C3F, 800009E80E010C3F, 800009A80E010C3F, 800008E80E010C3F, 800008A80E010C3F, 80000BE80E010C3F, 80000BA80E010C3F, 80000AE80E010C3F, 80000AA80E010C3F, 800000280E010C3F, 800000680E010C3F, 800001280E010C3F, 800001680E010C3F, 800002280E010C3F, 800002680E010C3F, 800003280E010C3F, 800003680E010C3F, 800008280E010C3F, 800008680E010C3F, 800009280E010C3F, 800009680E010C3F, 80000A680E010C3F, 80000B280E010C3F,
+static const uint64_t P9N2_PEC_2_SCOM0X28 = 0x80000B680F010C3Full;
+//DUPS: 800000A80F010C3F, 80000A280F010C3F, 800000E80F010C3F, 800001A80F010C3F, 800001E80F010C3F, 800003E80F010C3F, 800003A80F010C3F, 800002E80F010C3F, 800002A80F010C3F, 800009E80F010C3F, 800009A80F010C3F, 800008E80F010C3F, 800008A80F010C3F, 80000BE80F010C3F, 80000BA80F010C3F, 80000AE80F010C3F, 80000AA80F010C3F, 800000280F010C3F, 800000680F010C3F, 800001280F010C3F, 800001680F010C3F, 800002280F010C3F, 800002680F010C3F, 800003280F010C3F, 800003680F010C3F, 800008280F010C3F, 800008680F010C3F, 800009280F010C3F, 800009680F010C3F, 80000A680F010C3F, 80000B280F010C3F,
+
+static const uint64_t P9N2_PEC_SCOM0X29 = 0x80000B690D010C3Full;
+//DUPS: 800000A90D010C3F, 80000A290D010C3F, 800000E90D010C3F, 800001A90D010C3F, 800001E90D010C3F, 800003E90D010C3F, 800003A90D010C3F, 800002E90D010C3F, 800002A90D010C3F, 800009E90D010C3F, 800009A90D010C3F, 800008E90D010C3F, 800008A90D010C3F, 80000BE90D010C3F, 80000BA90D010C3F, 80000AE90D010C3F, 80000AA90D010C3F, 800000290D010C3F, 800000690D010C3F, 800001290D010C3F, 800001690D010C3F, 800002290D010C3F, 800002690D010C3F, 800003290D010C3F, 800003690D010C3F, 800008290D010C3F, 800008690D010C3F, 800009290D010C3F, 800009690D010C3F, 80000A690D010C3F, 80000B290D010C3F,
+static const uint64_t P9N2_PEC_0_SCOM0X29 = 0x80000B690D010C3Full;
+//DUPS: 800000A90D010C3F, 80000A290D010C3F, 800000E90D010C3F, 800001A90D010C3F, 800001E90D010C3F, 800003E90D010C3F, 800003A90D010C3F, 800002E90D010C3F, 800002A90D010C3F, 800009E90D010C3F, 800009A90D010C3F, 800008E90D010C3F, 800008A90D010C3F, 80000BE90D010C3F, 80000BA90D010C3F, 80000AE90D010C3F, 80000AA90D010C3F, 800000290D010C3F, 800000690D010C3F, 800001290D010C3F, 800001690D010C3F, 800002290D010C3F, 800002690D010C3F, 800003290D010C3F, 800003690D010C3F, 800008290D010C3F, 800008690D010C3F, 800009290D010C3F, 800009690D010C3F, 80000A690D010C3F, 80000B290D010C3F,
+static const uint64_t P9N2_PEC_1_SCOM0X29 = 0x80000B690E010C3Full;
+//DUPS: 800000A90E010C3F, 80000A290E010C3F, 800000E90E010C3F, 800001A90E010C3F, 800001E90E010C3F, 800003E90E010C3F, 800003A90E010C3F, 800002E90E010C3F, 800002A90E010C3F, 800009E90E010C3F, 800009A90E010C3F, 800008E90E010C3F, 800008A90E010C3F, 80000BE90E010C3F, 80000BA90E010C3F, 80000AE90E010C3F, 80000AA90E010C3F, 800000290E010C3F, 800000690E010C3F, 800001290E010C3F, 800001690E010C3F, 800002290E010C3F, 800002690E010C3F, 800003290E010C3F, 800003690E010C3F, 800008290E010C3F, 800008690E010C3F, 800009290E010C3F, 800009690E010C3F, 80000A690E010C3F, 80000B290E010C3F,
+static const uint64_t P9N2_PEC_2_SCOM0X29 = 0x80000B690F010C3Full;
+//DUPS: 800000A90F010C3F, 80000A290F010C3F, 800000E90F010C3F, 800001A90F010C3F, 800001E90F010C3F, 800003E90F010C3F, 800003A90F010C3F, 800002E90F010C3F, 800002A90F010C3F, 800009E90F010C3F, 800009A90F010C3F, 800008E90F010C3F, 800008A90F010C3F, 80000BE90F010C3F, 80000BA90F010C3F, 80000AE90F010C3F, 80000AA90F010C3F, 800000290F010C3F, 800000690F010C3F, 800001290F010C3F, 800001690F010C3F, 800002290F010C3F, 800002690F010C3F, 800003290F010C3F, 800003690F010C3F, 800008290F010C3F, 800008690F010C3F, 800009290F010C3F, 800009690F010C3F, 80000A690F010C3F, 80000B290F010C3F,
+
+static const uint64_t P9N2_PEC_SCOM0X2A = 0x80000B6A0D010C3Full;
+//DUPS: 800000AA0D010C3F, 80000A2A0D010C3F, 800000EA0D010C3F, 800001AA0D010C3F, 800001EA0D010C3F, 800003EA0D010C3F, 800003AA0D010C3F, 800002EA0D010C3F, 800002AA0D010C3F, 800009EA0D010C3F, 800009AA0D010C3F, 800008EA0D010C3F, 800008AA0D010C3F, 80000BEA0D010C3F, 80000BAA0D010C3F, 80000AEA0D010C3F, 80000AAA0D010C3F, 8000002A0D010C3F, 8000006A0D010C3F, 8000012A0D010C3F, 8000016A0D010C3F, 8000022A0D010C3F, 8000026A0D010C3F, 8000032A0D010C3F, 8000036A0D010C3F, 8000082A0D010C3F, 8000086A0D010C3F, 8000092A0D010C3F, 8000096A0D010C3F, 80000A6A0D010C3F, 80000B2A0D010C3F,
+static const uint64_t P9N2_PEC_0_SCOM0X2A = 0x80000B6A0D010C3Full;
+//DUPS: 800000AA0D010C3F, 80000A2A0D010C3F, 800000EA0D010C3F, 800001AA0D010C3F, 800001EA0D010C3F, 800003EA0D010C3F, 800003AA0D010C3F, 800002EA0D010C3F, 800002AA0D010C3F, 800009EA0D010C3F, 800009AA0D010C3F, 800008EA0D010C3F, 800008AA0D010C3F, 80000BEA0D010C3F, 80000BAA0D010C3F, 80000AEA0D010C3F, 80000AAA0D010C3F, 8000002A0D010C3F, 8000006A0D010C3F, 8000012A0D010C3F, 8000016A0D010C3F, 8000022A0D010C3F, 8000026A0D010C3F, 8000032A0D010C3F, 8000036A0D010C3F, 8000082A0D010C3F, 8000086A0D010C3F, 8000092A0D010C3F, 8000096A0D010C3F, 80000A6A0D010C3F, 80000B2A0D010C3F,
+static const uint64_t P9N2_PEC_1_SCOM0X2A = 0x80000B6A0E010C3Full;
+//DUPS: 800000AA0E010C3F, 80000A2A0E010C3F, 800000EA0E010C3F, 800001AA0E010C3F, 800001EA0E010C3F, 800003EA0E010C3F, 800003AA0E010C3F, 800002EA0E010C3F, 800002AA0E010C3F, 800009EA0E010C3F, 800009AA0E010C3F, 800008EA0E010C3F, 800008AA0E010C3F, 80000BEA0E010C3F, 80000BAA0E010C3F, 80000AEA0E010C3F, 80000AAA0E010C3F, 8000002A0E010C3F, 8000006A0E010C3F, 8000012A0E010C3F, 8000016A0E010C3F, 8000022A0E010C3F, 8000026A0E010C3F, 8000032A0E010C3F, 8000036A0E010C3F, 8000082A0E010C3F, 8000086A0E010C3F, 8000092A0E010C3F, 8000096A0E010C3F, 80000A6A0E010C3F, 80000B2A0E010C3F,
+static const uint64_t P9N2_PEC_2_SCOM0X2A = 0x80000B6A0F010C3Full;
+//DUPS: 800000AA0F010C3F, 80000A2A0F010C3F, 800000EA0F010C3F, 800001AA0F010C3F, 800001EA0F010C3F, 800003EA0F010C3F, 800003AA0F010C3F, 800002EA0F010C3F, 800002AA0F010C3F, 800009EA0F010C3F, 800009AA0F010C3F, 800008EA0F010C3F, 800008AA0F010C3F, 80000BEA0F010C3F, 80000BAA0F010C3F, 80000AEA0F010C3F, 80000AAA0F010C3F, 8000002A0F010C3F, 8000006A0F010C3F, 8000012A0F010C3F, 8000016A0F010C3F, 8000022A0F010C3F, 8000026A0F010C3F, 8000032A0F010C3F, 8000036A0F010C3F, 8000082A0F010C3F, 8000086A0F010C3F, 8000092A0F010C3F, 8000096A0F010C3F, 80000A6A0F010C3F, 80000B2A0F010C3F,
+
+static const uint64_t P9N2_PEC_SCOM0X2B = 0x80000B6B0D010C3Full;
+//DUPS: 80000A2B0D010C3F, 8000002B0D010C3F, 8000006B0D010C3F, 8000012B0D010C3F, 8000016B0D010C3F, 8000022B0D010C3F, 8000026B0D010C3F, 8000032B0D010C3F, 8000036B0D010C3F, 8000082B0D010C3F, 8000086B0D010C3F, 8000092B0D010C3F, 8000096B0D010C3F, 80000A6B0D010C3F, 80000B2B0D010C3F,
+static const uint64_t P9N2_PEC_0_SCOM0X2B = 0x80000B6B0D010C3Full;
+//DUPS: 80000A2B0D010C3F, 8000002B0D010C3F, 8000006B0D010C3F, 8000012B0D010C3F, 8000016B0D010C3F, 8000022B0D010C3F, 8000026B0D010C3F, 8000032B0D010C3F, 8000036B0D010C3F, 8000082B0D010C3F, 8000086B0D010C3F, 8000092B0D010C3F, 8000096B0D010C3F, 80000A6B0D010C3F, 80000B2B0D010C3F,
+static const uint64_t P9N2_PEC_1_SCOM0X2B = 0x80000B6B0E010C3Full;
+//DUPS: 80000A2B0E010C3F, 8000002B0E010C3F, 8000006B0E010C3F, 8000012B0E010C3F, 8000016B0E010C3F, 8000022B0E010C3F, 8000026B0E010C3F, 8000032B0E010C3F, 8000036B0E010C3F, 8000082B0E010C3F, 8000086B0E010C3F, 8000092B0E010C3F, 8000096B0E010C3F, 80000A6B0E010C3F, 80000B2B0E010C3F,
+static const uint64_t P9N2_PEC_2_SCOM0X2B = 0x80000B6B0F010C3Full;
+//DUPS: 80000A2B0F010C3F, 8000002B0F010C3F, 8000006B0F010C3F, 8000012B0F010C3F, 8000016B0F010C3F, 8000022B0F010C3F, 8000026B0F010C3F, 8000032B0F010C3F, 8000036B0F010C3F, 8000082B0F010C3F, 8000086B0F010C3F, 8000092B0F010C3F, 8000096B0F010C3F, 80000A6B0F010C3F, 80000B2B0F010C3F,
+
+static const uint64_t P9N2_PEC_SCOM0X2C = 0x80000B6C0D010C3Full;
+//DUPS: 80000A2C0D010C3F, 8000002C0D010C3F, 8000006C0D010C3F, 8000012C0D010C3F, 8000016C0D010C3F, 8000022C0D010C3F, 8000026C0D010C3F, 8000032C0D010C3F, 8000036C0D010C3F, 8000082C0D010C3F, 8000086C0D010C3F, 8000092C0D010C3F, 8000096C0D010C3F, 80000A6C0D010C3F, 80000B2C0D010C3F,
+static const uint64_t P9N2_PEC_0_SCOM0X2C = 0x80000B6C0D010C3Full;
+//DUPS: 80000A2C0D010C3F, 8000002C0D010C3F, 8000006C0D010C3F, 8000012C0D010C3F, 8000016C0D010C3F, 8000022C0D010C3F, 8000026C0D010C3F, 8000032C0D010C3F, 8000036C0D010C3F, 8000082C0D010C3F, 8000086C0D010C3F, 8000092C0D010C3F, 8000096C0D010C3F, 80000A6C0D010C3F, 80000B2C0D010C3F,
+static const uint64_t P9N2_PEC_1_SCOM0X2C = 0x80000B6C0E010C3Full;
+//DUPS: 80000A2C0E010C3F, 8000002C0E010C3F, 8000006C0E010C3F, 8000012C0E010C3F, 8000016C0E010C3F, 8000022C0E010C3F, 8000026C0E010C3F, 8000032C0E010C3F, 8000036C0E010C3F, 8000082C0E010C3F, 8000086C0E010C3F, 8000092C0E010C3F, 8000096C0E010C3F, 80000A6C0E010C3F, 80000B2C0E010C3F,
+static const uint64_t P9N2_PEC_2_SCOM0X2C = 0x80000B6C0F010C3Full;
+//DUPS: 80000A2C0F010C3F, 8000002C0F010C3F, 8000006C0F010C3F, 8000012C0F010C3F, 8000016C0F010C3F, 8000022C0F010C3F, 8000026C0F010C3F, 8000032C0F010C3F, 8000036C0F010C3F, 8000082C0F010C3F, 8000086C0F010C3F, 8000092C0F010C3F, 8000096C0F010C3F, 80000A6C0F010C3F, 80000B2C0F010C3F,
+
+static const uint64_t P9N2_PEC_SCOM0X2D = 0x80000B6D0D010C3Full;
+//DUPS: 800000AD0D010C3F, 80000A2D0D010C3F, 800000ED0D010C3F, 800001AD0D010C3F, 800001ED0D010C3F, 800003ED0D010C3F, 800003AD0D010C3F, 800002ED0D010C3F, 800002AD0D010C3F, 800009ED0D010C3F, 800009AD0D010C3F, 800008ED0D010C3F, 800008AD0D010C3F, 80000BED0D010C3F, 80000BAD0D010C3F, 80000AED0D010C3F, 80000AAD0D010C3F, 8000002D0D010C3F, 8000006D0D010C3F, 8000012D0D010C3F, 8000016D0D010C3F, 8000022D0D010C3F, 8000026D0D010C3F, 8000032D0D010C3F, 8000036D0D010C3F, 8000082D0D010C3F, 8000086D0D010C3F, 8000092D0D010C3F, 8000096D0D010C3F, 80000A6D0D010C3F, 80000B2D0D010C3F,
+static const uint64_t P9N2_PEC_0_SCOM0X2D = 0x80000B6D0D010C3Full;
+//DUPS: 800000AD0D010C3F, 80000A2D0D010C3F, 800000ED0D010C3F, 800001AD0D010C3F, 800001ED0D010C3F, 800003ED0D010C3F, 800003AD0D010C3F, 800002ED0D010C3F, 800002AD0D010C3F, 800009ED0D010C3F, 800009AD0D010C3F, 800008ED0D010C3F, 800008AD0D010C3F, 80000BED0D010C3F, 80000BAD0D010C3F, 80000AED0D010C3F, 80000AAD0D010C3F, 8000002D0D010C3F, 8000006D0D010C3F, 8000012D0D010C3F, 8000016D0D010C3F, 8000022D0D010C3F, 8000026D0D010C3F, 8000032D0D010C3F, 8000036D0D010C3F, 8000082D0D010C3F, 8000086D0D010C3F, 8000092D0D010C3F, 8000096D0D010C3F, 80000A6D0D010C3F, 80000B2D0D010C3F,
+static const uint64_t P9N2_PEC_1_SCOM0X2D = 0x80000B6D0E010C3Full;
+//DUPS: 800000AD0E010C3F, 80000A2D0E010C3F, 800000ED0E010C3F, 800001AD0E010C3F, 800001ED0E010C3F, 800003ED0E010C3F, 800003AD0E010C3F, 800002ED0E010C3F, 800002AD0E010C3F, 800009ED0E010C3F, 800009AD0E010C3F, 800008ED0E010C3F, 800008AD0E010C3F, 80000BED0E010C3F, 80000BAD0E010C3F, 80000AED0E010C3F, 80000AAD0E010C3F, 8000002D0E010C3F, 8000006D0E010C3F, 8000012D0E010C3F, 8000016D0E010C3F, 8000022D0E010C3F, 8000026D0E010C3F, 8000032D0E010C3F, 8000036D0E010C3F, 8000082D0E010C3F, 8000086D0E010C3F, 8000092D0E010C3F, 8000096D0E010C3F, 80000A6D0E010C3F, 80000B2D0E010C3F,
+static const uint64_t P9N2_PEC_2_SCOM0X2D = 0x80000B6D0F010C3Full;
+//DUPS: 800000AD0F010C3F, 80000A2D0F010C3F, 800000ED0F010C3F, 800001AD0F010C3F, 800001ED0F010C3F, 800003ED0F010C3F, 800003AD0F010C3F, 800002ED0F010C3F, 800002AD0F010C3F, 800009ED0F010C3F, 800009AD0F010C3F, 800008ED0F010C3F, 800008AD0F010C3F, 80000BED0F010C3F, 80000BAD0F010C3F, 80000AED0F010C3F, 80000AAD0F010C3F, 8000002D0F010C3F, 8000006D0F010C3F, 8000012D0F010C3F, 8000016D0F010C3F, 8000022D0F010C3F, 8000026D0F010C3F, 8000032D0F010C3F, 8000036D0F010C3F, 8000082D0F010C3F, 8000086D0F010C3F, 8000092D0F010C3F, 8000096D0F010C3F, 80000A6D0F010C3F, 80000B2D0F010C3F,
+
+static const uint64_t P9N2_PEC_SCOM0X2E = 0x80000B6E0D010C3Full;
+//DUPS: 800000AE0D010C3F, 80000A2E0D010C3F, 800000EE0D010C3F, 800001AE0D010C3F, 800001EE0D010C3F, 800003EE0D010C3F, 800003AE0D010C3F, 800002EE0D010C3F, 800002AE0D010C3F, 800009EE0D010C3F, 800009AE0D010C3F, 800008EE0D010C3F, 800008AE0D010C3F, 80000BEE0D010C3F, 80000BAE0D010C3F, 80000AEE0D010C3F, 80000AAE0D010C3F, 8000002E0D010C3F, 8000006E0D010C3F, 8000012E0D010C3F, 8000016E0D010C3F, 8000022E0D010C3F, 8000026E0D010C3F, 8000032E0D010C3F, 8000036E0D010C3F, 8000082E0D010C3F, 8000086E0D010C3F, 8000092E0D010C3F, 8000096E0D010C3F, 80000A6E0D010C3F, 80000B2E0D010C3F,
+static const uint64_t P9N2_PEC_0_SCOM0X2E = 0x80000B6E0D010C3Full;
+//DUPS: 800000AE0D010C3F, 80000A2E0D010C3F, 800000EE0D010C3F, 800001AE0D010C3F, 800001EE0D010C3F, 800003EE0D010C3F, 800003AE0D010C3F, 800002EE0D010C3F, 800002AE0D010C3F, 800009EE0D010C3F, 800009AE0D010C3F, 800008EE0D010C3F, 800008AE0D010C3F, 80000BEE0D010C3F, 80000BAE0D010C3F, 80000AEE0D010C3F, 80000AAE0D010C3F, 8000002E0D010C3F, 8000006E0D010C3F, 8000012E0D010C3F, 8000016E0D010C3F, 8000022E0D010C3F, 8000026E0D010C3F, 8000032E0D010C3F, 8000036E0D010C3F, 8000082E0D010C3F, 8000086E0D010C3F, 8000092E0D010C3F, 8000096E0D010C3F, 80000A6E0D010C3F, 80000B2E0D010C3F,
+static const uint64_t P9N2_PEC_1_SCOM0X2E = 0x80000B6E0E010C3Full;
+//DUPS: 800000AE0E010C3F, 80000A2E0E010C3F, 800000EE0E010C3F, 800001AE0E010C3F, 800001EE0E010C3F, 800003EE0E010C3F, 800003AE0E010C3F, 800002EE0E010C3F, 800002AE0E010C3F, 800009EE0E010C3F, 800009AE0E010C3F, 800008EE0E010C3F, 800008AE0E010C3F, 80000BEE0E010C3F, 80000BAE0E010C3F, 80000AEE0E010C3F, 80000AAE0E010C3F, 8000002E0E010C3F, 8000006E0E010C3F, 8000012E0E010C3F, 8000016E0E010C3F, 8000022E0E010C3F, 8000026E0E010C3F, 8000032E0E010C3F, 8000036E0E010C3F, 8000082E0E010C3F, 8000086E0E010C3F, 8000092E0E010C3F, 8000096E0E010C3F, 80000A6E0E010C3F, 80000B2E0E010C3F,
+static const uint64_t P9N2_PEC_2_SCOM0X2E = 0x80000B6E0F010C3Full;
+//DUPS: 800000AE0F010C3F, 80000A2E0F010C3F, 800000EE0F010C3F, 800001AE0F010C3F, 800001EE0F010C3F, 800003EE0F010C3F, 800003AE0F010C3F, 800002EE0F010C3F, 800002AE0F010C3F, 800009EE0F010C3F, 800009AE0F010C3F, 800008EE0F010C3F, 800008AE0F010C3F, 80000BEE0F010C3F, 80000BAE0F010C3F, 80000AEE0F010C3F, 80000AAE0F010C3F, 8000002E0F010C3F, 8000006E0F010C3F, 8000012E0F010C3F, 8000016E0F010C3F, 8000022E0F010C3F, 8000026E0F010C3F, 8000032E0F010C3F, 8000036E0F010C3F, 8000082E0F010C3F, 8000086E0F010C3F, 8000092E0F010C3F, 8000096E0F010C3F, 80000A6E0F010C3F, 80000B2E0F010C3F,
+
+static const uint64_t P9N2_PEC_SCOM0X2F = 0x80000B6F0D010C3Full;
+//DUPS: 800000AF0D010C3F, 80000A2F0D010C3F, 800000EF0D010C3F, 800001AF0D010C3F, 800001EF0D010C3F, 800003EF0D010C3F, 800003AF0D010C3F, 800002EF0D010C3F, 800002AF0D010C3F, 800009EF0D010C3F, 800009AF0D010C3F, 800008EF0D010C3F, 800008AF0D010C3F, 80000BEF0D010C3F, 80000BAF0D010C3F, 80000AEF0D010C3F, 80000AAF0D010C3F, 8000002F0D010C3F, 8000006F0D010C3F, 8000012F0D010C3F, 8000016F0D010C3F, 8000022F0D010C3F, 8000026F0D010C3F, 8000032F0D010C3F, 8000036F0D010C3F, 8000082F0D010C3F, 8000086F0D010C3F, 8000092F0D010C3F, 8000096F0D010C3F, 80000A6F0D010C3F, 80000B2F0D010C3F,
+static const uint64_t P9N2_PEC_0_SCOM0X2F = 0x80000B6F0D010C3Full;
+//DUPS: 800000AF0D010C3F, 80000A2F0D010C3F, 800000EF0D010C3F, 800001AF0D010C3F, 800001EF0D010C3F, 800003EF0D010C3F, 800003AF0D010C3F, 800002EF0D010C3F, 800002AF0D010C3F, 800009EF0D010C3F, 800009AF0D010C3F, 800008EF0D010C3F, 800008AF0D010C3F, 80000BEF0D010C3F, 80000BAF0D010C3F, 80000AEF0D010C3F, 80000AAF0D010C3F, 8000002F0D010C3F, 8000006F0D010C3F, 8000012F0D010C3F, 8000016F0D010C3F, 8000022F0D010C3F, 8000026F0D010C3F, 8000032F0D010C3F, 8000036F0D010C3F, 8000082F0D010C3F, 8000086F0D010C3F, 8000092F0D010C3F, 8000096F0D010C3F, 80000A6F0D010C3F, 80000B2F0D010C3F,
+static const uint64_t P9N2_PEC_1_SCOM0X2F = 0x80000B6F0E010C3Full;
+//DUPS: 800000AF0E010C3F, 80000A2F0E010C3F, 800000EF0E010C3F, 800001AF0E010C3F, 800001EF0E010C3F, 800003EF0E010C3F, 800003AF0E010C3F, 800002EF0E010C3F, 800002AF0E010C3F, 800009EF0E010C3F, 800009AF0E010C3F, 800008EF0E010C3F, 800008AF0E010C3F, 80000BEF0E010C3F, 80000BAF0E010C3F, 80000AEF0E010C3F, 80000AAF0E010C3F, 8000002F0E010C3F, 8000006F0E010C3F, 8000012F0E010C3F, 8000016F0E010C3F, 8000022F0E010C3F, 8000026F0E010C3F, 8000032F0E010C3F, 8000036F0E010C3F, 8000082F0E010C3F, 8000086F0E010C3F, 8000092F0E010C3F, 8000096F0E010C3F, 80000A6F0E010C3F, 80000B2F0E010C3F,
+static const uint64_t P9N2_PEC_2_SCOM0X2F = 0x80000B6F0F010C3Full;
+//DUPS: 800000AF0F010C3F, 80000A2F0F010C3F, 800000EF0F010C3F, 800001AF0F010C3F, 800001EF0F010C3F, 800003EF0F010C3F, 800003AF0F010C3F, 800002EF0F010C3F, 800002AF0F010C3F, 800009EF0F010C3F, 800009AF0F010C3F, 800008EF0F010C3F, 800008AF0F010C3F, 80000BEF0F010C3F, 80000BAF0F010C3F, 80000AEF0F010C3F, 80000AAF0F010C3F, 8000002F0F010C3F, 8000006F0F010C3F, 8000012F0F010C3F, 8000016F0F010C3F, 8000022F0F010C3F, 8000026F0F010C3F, 8000032F0F010C3F, 8000036F0F010C3F, 8000082F0F010C3F, 8000086F0F010C3F, 8000092F0F010C3F, 8000096F0F010C3F, 80000A6F0F010C3F, 80000B2F0F010C3F,
+
+static const uint64_t P9N2_PEC_SCOM0X30 = 0x80000B700D010C3Full;
+//DUPS: 800000B00D010C3F, 800004300D010C3F, 80000A300D010C3F, 800000F00D010C3F, 800001B00D010C3F, 800001F00D010C3F, 800003F00D010C3F, 800003B00D010C3F, 800002F00D010C3F, 800002B00D010C3F, 800009F00D010C3F, 800009B00D010C3F, 800008F00D010C3F, 800008B00D010C3F, 80000BF00D010C3F, 80000BB00D010C3F, 80000AF00D010C3F, 80000AB00D010C3F, 800000300D010C3F, 800000700D010C3F, 800001300D010C3F, 800001700D010C3F, 800002300D010C3F, 800002700D010C3F, 800003300D010C3F, 800003700D010C3F, 800008300D010C3F, 800008700D010C3F, 800009300D010C3F, 800009700D010C3F, 80000A700D010C3F, 80000B300D010C3F,
+static const uint64_t P9N2_PEC_0_SCOM0X30 = 0x80000B700D010C3Full;
+//DUPS: 800000B00D010C3F, 800004300D010C3F, 80000A300D010C3F, 800000F00D010C3F, 800001B00D010C3F, 800001F00D010C3F, 800003F00D010C3F, 800003B00D010C3F, 800002F00D010C3F, 800002B00D010C3F, 800009F00D010C3F, 800009B00D010C3F, 800008F00D010C3F, 800008B00D010C3F, 80000BF00D010C3F, 80000BB00D010C3F, 80000AF00D010C3F, 80000AB00D010C3F, 800000300D010C3F, 800000700D010C3F, 800001300D010C3F, 800001700D010C3F, 800002300D010C3F, 800002700D010C3F, 800003300D010C3F, 800003700D010C3F, 800008300D010C3F, 800008700D010C3F, 800009300D010C3F, 800009700D010C3F, 80000A700D010C3F, 80000B300D010C3F,
+static const uint64_t P9N2_PEC_1_SCOM0X30 = 0x80000B700E010C3Full;
+//DUPS: 800000B00E010C3F, 800004300E010C3F, 80000A300E010C3F, 800000F00E010C3F, 800001B00E010C3F, 800001F00E010C3F, 800003F00E010C3F, 800003B00E010C3F, 800002F00E010C3F, 800002B00E010C3F, 800009F00E010C3F, 800009B00E010C3F, 800008F00E010C3F, 800008B00E010C3F, 80000BF00E010C3F, 80000BB00E010C3F, 80000AF00E010C3F, 80000AB00E010C3F, 800000300E010C3F, 800000700E010C3F, 800001300E010C3F, 800001700E010C3F, 800002300E010C3F, 800002700E010C3F, 800003300E010C3F, 800003700E010C3F, 800008300E010C3F, 800008700E010C3F, 800009300E010C3F, 800009700E010C3F, 80000A700E010C3F, 80000B300E010C3F,
+static const uint64_t P9N2_PEC_2_SCOM0X30 = 0x80000B700F010C3Full;
+//DUPS: 800000B00F010C3F, 800004300F010C3F, 80000A300F010C3F, 800000F00F010C3F, 800001B00F010C3F, 800001F00F010C3F, 800003F00F010C3F, 800003B00F010C3F, 800002F00F010C3F, 800002B00F010C3F, 800009F00F010C3F, 800009B00F010C3F, 800008F00F010C3F, 800008B00F010C3F, 80000BF00F010C3F, 80000BB00F010C3F, 80000AF00F010C3F, 80000AB00F010C3F, 800000300F010C3F, 800000700F010C3F, 800001300F010C3F, 800001700F010C3F, 800002300F010C3F, 800002700F010C3F, 800003300F010C3F, 800003700F010C3F, 800008300F010C3F, 800008700F010C3F, 800009300F010C3F, 800009700F010C3F, 80000A700F010C3F, 80000B300F010C3F,
+
+static const uint64_t P9N2_PEC_SCOM0X31 = 0x80000BF10D010C3Full;
+//DUPS: 800004310D010C3F, 800000F10D010C3F, 800001B10D010C3F, 800001F10D010C3F, 800003F10D010C3F, 800003B10D010C3F, 800002F10D010C3F, 800002B10D010C3F, 800009F10D010C3F, 800009B10D010C3F, 800008F10D010C3F, 800008B10D010C3F, 80000BF10D010C3F, 80000BB10D010C3F, 80000AF10D010C3F, 80000AB10D010C3F,
+static const uint64_t P9N2_PEC_0_SCOM0X31 = 0x80000BF10D010C3Full;
+//DUPS: 800004310D010C3F, 800000F10D010C3F, 800001B10D010C3F, 800001F10D010C3F, 800003F10D010C3F, 800003B10D010C3F, 800002F10D010C3F, 800002B10D010C3F, 800009F10D010C3F, 800009B10D010C3F, 800008F10D010C3F, 800008B10D010C3F, 80000BF10D010C3F, 80000BB10D010C3F, 80000AF10D010C3F, 80000AB10D010C3F,
+static const uint64_t P9N2_PEC_1_SCOM0X31 = 0x80000BF10E010C3Full;
+//DUPS: 800004310E010C3F, 800000F10E010C3F, 800001B10E010C3F, 800001F10E010C3F, 800003F10E010C3F, 800003B10E010C3F, 800002F10E010C3F, 800002B10E010C3F, 800009F10E010C3F, 800009B10E010C3F, 800008F10E010C3F, 800008B10E010C3F, 80000BF10E010C3F, 80000BB10E010C3F, 80000AF10E010C3F, 80000AB10E010C3F,
+static const uint64_t P9N2_PEC_2_SCOM0X31 = 0x80000BF10F010C3Full;
+//DUPS: 800004310F010C3F, 800000F10F010C3F, 800001B10F010C3F, 800001F10F010C3F, 800003F10F010C3F, 800003B10F010C3F, 800002F10F010C3F, 800002B10F010C3F, 800009F10F010C3F, 800009B10F010C3F, 800008F10F010C3F, 800008B10F010C3F, 80000BF10F010C3F, 80000BB10F010C3F, 80000AF10F010C3F, 80000AB10F010C3F,
+
+static const uint64_t P9N2_PEC_SCOM0X32 = 0x80000BF20D010C3Full;
+//DUPS: 800004320D010C3F, 800000F20D010C3F, 800001B20D010C3F, 800001F20D010C3F, 800003F20D010C3F, 800003B20D010C3F, 800002F20D010C3F, 800002B20D010C3F, 800009F20D010C3F, 800009B20D010C3F, 800008F20D010C3F, 800008B20D010C3F, 80000BF20D010C3F, 80000BB20D010C3F, 80000AF20D010C3F, 80000AB20D010C3F,
+static const uint64_t P9N2_PEC_0_SCOM0X32 = 0x80000BF20D010C3Full;
+//DUPS: 800004320D010C3F, 800000F20D010C3F, 800001B20D010C3F, 800001F20D010C3F, 800003F20D010C3F, 800003B20D010C3F, 800002F20D010C3F, 800002B20D010C3F, 800009F20D010C3F, 800009B20D010C3F, 800008F20D010C3F, 800008B20D010C3F, 80000BF20D010C3F, 80000BB20D010C3F, 80000AF20D010C3F, 80000AB20D010C3F,
+static const uint64_t P9N2_PEC_1_SCOM0X32 = 0x80000BF20E010C3Full;
+//DUPS: 800004320E010C3F, 800000F20E010C3F, 800001B20E010C3F, 800001F20E010C3F, 800003F20E010C3F, 800003B20E010C3F, 800002F20E010C3F, 800002B20E010C3F, 800009F20E010C3F, 800009B20E010C3F, 800008F20E010C3F, 800008B20E010C3F, 80000BF20E010C3F, 80000BB20E010C3F, 80000AF20E010C3F, 80000AB20E010C3F,
+static const uint64_t P9N2_PEC_2_SCOM0X32 = 0x80000BF20F010C3Full;
+//DUPS: 800004320F010C3F, 800000F20F010C3F, 800001B20F010C3F, 800001F20F010C3F, 800003F20F010C3F, 800003B20F010C3F, 800002F20F010C3F, 800002B20F010C3F, 800009F20F010C3F, 800009B20F010C3F, 800008F20F010C3F, 800008B20F010C3F, 80000BF20F010C3F, 80000BB20F010C3F, 80000AF20F010C3F, 80000AB20F010C3F,
+
+static const uint64_t P9N2_PEC_SCOM0X33 = 0x80000BF30D010C3Full;
+//DUPS: 800004330D010C3F, 800000F30D010C3F, 800001B30D010C3F, 800001F30D010C3F, 800003F30D010C3F, 800003B30D010C3F, 800002F30D010C3F, 800002B30D010C3F, 800009F30D010C3F, 800009B30D010C3F, 800008F30D010C3F, 800008B30D010C3F, 80000BF30D010C3F, 80000BB30D010C3F, 80000AF30D010C3F, 80000AB30D010C3F,
+static const uint64_t P9N2_PEC_0_SCOM0X33 = 0x80000BF30D010C3Full;
+//DUPS: 800004330D010C3F, 800000F30D010C3F, 800001B30D010C3F, 800001F30D010C3F, 800003F30D010C3F, 800003B30D010C3F, 800002F30D010C3F, 800002B30D010C3F, 800009F30D010C3F, 800009B30D010C3F, 800008F30D010C3F, 800008B30D010C3F, 80000BF30D010C3F, 80000BB30D010C3F, 80000AF30D010C3F, 80000AB30D010C3F,
+static const uint64_t P9N2_PEC_1_SCOM0X33 = 0x80000BF30E010C3Full;
+//DUPS: 800004330E010C3F, 800000F30E010C3F, 800001B30E010C3F, 800001F30E010C3F, 800003F30E010C3F, 800003B30E010C3F, 800002F30E010C3F, 800002B30E010C3F, 800009F30E010C3F, 800009B30E010C3F, 800008F30E010C3F, 800008B30E010C3F, 80000BF30E010C3F, 80000BB30E010C3F, 80000AF30E010C3F, 80000AB30E010C3F,
+static const uint64_t P9N2_PEC_2_SCOM0X33 = 0x80000BF30F010C3Full;
+//DUPS: 800004330F010C3F, 800000F30F010C3F, 800001B30F010C3F, 800001F30F010C3F, 800003F30F010C3F, 800003B30F010C3F, 800002F30F010C3F, 800002B30F010C3F, 800009F30F010C3F, 800009B30F010C3F, 800008F30F010C3F, 800008B30F010C3F, 80000BF30F010C3F, 80000BB30F010C3F, 80000AF30F010C3F, 80000AB30F010C3F,
+
+static const uint64_t P9N2_PEC_SCOM0X34 = 0x80000BF40D010C3Full;
+//DUPS: 800004340D010C3F, 800000F40D010C3F, 800001B40D010C3F, 800001F40D010C3F, 800003F40D010C3F, 800003B40D010C3F, 800002F40D010C3F, 800002B40D010C3F, 800009F40D010C3F, 800009B40D010C3F, 800008F40D010C3F, 800008B40D010C3F, 80000BF40D010C3F, 80000BB40D010C3F, 80000AF40D010C3F, 80000AB40D010C3F,
+static const uint64_t P9N2_PEC_0_SCOM0X34 = 0x80000BF40D010C3Full;
+//DUPS: 800004340D010C3F, 800000F40D010C3F, 800001B40D010C3F, 800001F40D010C3F, 800003F40D010C3F, 800003B40D010C3F, 800002F40D010C3F, 800002B40D010C3F, 800009F40D010C3F, 800009B40D010C3F, 800008F40D010C3F, 800008B40D010C3F, 80000BF40D010C3F, 80000BB40D010C3F, 80000AF40D010C3F, 80000AB40D010C3F,
+static const uint64_t P9N2_PEC_1_SCOM0X34 = 0x80000BF40E010C3Full;
+//DUPS: 800004340E010C3F, 800000F40E010C3F, 800001B40E010C3F, 800001F40E010C3F, 800003F40E010C3F, 800003B40E010C3F, 800002F40E010C3F, 800002B40E010C3F, 800009F40E010C3F, 800009B40E010C3F, 800008F40E010C3F, 800008B40E010C3F, 80000BF40E010C3F, 80000BB40E010C3F, 80000AF40E010C3F, 80000AB40E010C3F,
+static const uint64_t P9N2_PEC_2_SCOM0X34 = 0x80000BF40F010C3Full;
+//DUPS: 800004340F010C3F, 800000F40F010C3F, 800001B40F010C3F, 800001F40F010C3F, 800003F40F010C3F, 800003B40F010C3F, 800002F40F010C3F, 800002B40F010C3F, 800009F40F010C3F, 800009B40F010C3F, 800008F40F010C3F, 800008B40F010C3F, 80000BF40F010C3F, 80000BB40F010C3F, 80000AF40F010C3F, 80000AB40F010C3F,
+
+static const uint64_t P9N2_PEC_SCOM0X35 = 0x800004350D010C3Full;
+
+static const uint64_t P9N2_PEC_0_SCOM0X35 = 0x800004350D010C3Full;
+
+static const uint64_t P9N2_PEC_1_SCOM0X35 = 0x800004350E010C3Full;
+
+static const uint64_t P9N2_PEC_2_SCOM0X35 = 0x800004350F010C3Full;
+
+
+static const uint64_t P9N2_PEC_SCOM0X36 = 0x800004360D010C3Full;
+
+static const uint64_t P9N2_PEC_0_SCOM0X36 = 0x800004360D010C3Full;
+
+static const uint64_t P9N2_PEC_1_SCOM0X36 = 0x800004360E010C3Full;
+
+static const uint64_t P9N2_PEC_2_SCOM0X36 = 0x800004360F010C3Full;
+
+
+static const uint64_t P9N2_PEC_SCOM0X37 = 0x800004370D010C3Full;
+
+static const uint64_t P9N2_PEC_0_SCOM0X37 = 0x800004370D010C3Full;
+
+static const uint64_t P9N2_PEC_1_SCOM0X37 = 0x800004370E010C3Full;
+
+static const uint64_t P9N2_PEC_2_SCOM0X37 = 0x800004370F010C3Full;
+
+
+static const uint64_t P9N2_PEC_SCOM0X38 = 0x80000B780D010C3Full;
+//DUPS: 800004380D010C3F, 80000A380D010C3F, 800000380D010C3F, 800000780D010C3F, 800001380D010C3F, 800001780D010C3F, 800002380D010C3F, 800002780D010C3F, 800003380D010C3F, 800003780D010C3F, 800008380D010C3F, 800008780D010C3F, 800009380D010C3F, 800009780D010C3F, 80000A780D010C3F, 80000B380D010C3F,
+static const uint64_t P9N2_PEC_0_SCOM0X38 = 0x80000B780D010C3Full;
+//DUPS: 800004380D010C3F, 80000A380D010C3F, 800000380D010C3F, 800000780D010C3F, 800001380D010C3F, 800001780D010C3F, 800002380D010C3F, 800002780D010C3F, 800003380D010C3F, 800003780D010C3F, 800008380D010C3F, 800008780D010C3F, 800009380D010C3F, 800009780D010C3F, 80000A780D010C3F, 80000B380D010C3F,
+static const uint64_t P9N2_PEC_1_SCOM0X38 = 0x80000B780E010C3Full;
+//DUPS: 800004380E010C3F, 80000A380E010C3F, 800000380E010C3F, 800000780E010C3F, 800001380E010C3F, 800001780E010C3F, 800002380E010C3F, 800002780E010C3F, 800003380E010C3F, 800003780E010C3F, 800008380E010C3F, 800008780E010C3F, 800009380E010C3F, 800009780E010C3F, 80000A780E010C3F, 80000B380E010C3F,
+static const uint64_t P9N2_PEC_2_SCOM0X38 = 0x80000B780F010C3Full;
+//DUPS: 800004380F010C3F, 80000A380F010C3F, 800000380F010C3F, 800000780F010C3F, 800001380F010C3F, 800001780F010C3F, 800002380F010C3F, 800002780F010C3F, 800003380F010C3F, 800003780F010C3F, 800008380F010C3F, 800008780F010C3F, 800009380F010C3F, 800009780F010C3F, 80000A780F010C3F, 80000B380F010C3F,
+
+static const uint64_t P9N2_PEC_SCOM0X39 = 0x80000B790D010C3Full;
+//DUPS: 800004390D010C3F, 80000A390D010C3F, 800000390D010C3F, 800000790D010C3F, 800001390D010C3F, 800001790D010C3F, 800002390D010C3F, 800002790D010C3F, 800003390D010C3F, 800003790D010C3F, 800008390D010C3F, 800008790D010C3F, 800009390D010C3F, 800009790D010C3F, 80000A790D010C3F, 80000B390D010C3F,
+static const uint64_t P9N2_PEC_0_SCOM0X39 = 0x80000B790D010C3Full;
+//DUPS: 800004390D010C3F, 80000A390D010C3F, 800000390D010C3F, 800000790D010C3F, 800001390D010C3F, 800001790D010C3F, 800002390D010C3F, 800002790D010C3F, 800003390D010C3F, 800003790D010C3F, 800008390D010C3F, 800008790D010C3F, 800009390D010C3F, 800009790D010C3F, 80000A790D010C3F, 80000B390D010C3F,
+static const uint64_t P9N2_PEC_1_SCOM0X39 = 0x80000B790E010C3Full;
+//DUPS: 800004390E010C3F, 80000A390E010C3F, 800000390E010C3F, 800000790E010C3F, 800001390E010C3F, 800001790E010C3F, 800002390E010C3F, 800002790E010C3F, 800003390E010C3F, 800003790E010C3F, 800008390E010C3F, 800008790E010C3F, 800009390E010C3F, 800009790E010C3F, 80000A790E010C3F, 80000B390E010C3F,
+static const uint64_t P9N2_PEC_2_SCOM0X39 = 0x80000B790F010C3Full;
+//DUPS: 800004390F010C3F, 80000A390F010C3F, 800000390F010C3F, 800000790F010C3F, 800001390F010C3F, 800001790F010C3F, 800002390F010C3F, 800002790F010C3F, 800003390F010C3F, 800003790F010C3F, 800008390F010C3F, 800008790F010C3F, 800009390F010C3F, 800009790F010C3F, 80000A790F010C3F, 80000B390F010C3F,
+
+static const uint64_t P9N2_PEC_SCOM0X3A = 0x80000B7A0D010C3Full;
+//DUPS: 8000043A0D010C3F, 800000BA0D010C3F, 80000A3A0D010C3F, 800000FA0D010C3F, 800001BA0D010C3F, 800001FA0D010C3F, 800003FA0D010C3F, 800003BA0D010C3F, 800002FA0D010C3F, 800002BA0D010C3F, 800009FA0D010C3F, 800009BA0D010C3F, 800008FA0D010C3F, 800008BA0D010C3F, 80000BFA0D010C3F, 80000BBA0D010C3F, 80000AFA0D010C3F, 80000ABA0D010C3F, 8000003A0D010C3F, 8000007A0D010C3F, 8000013A0D010C3F, 8000017A0D010C3F, 8000023A0D010C3F, 8000027A0D010C3F, 8000033A0D010C3F, 8000037A0D010C3F, 8000083A0D010C3F, 8000087A0D010C3F, 8000093A0D010C3F, 8000097A0D010C3F, 80000A7A0D010C3F, 80000B3A0D010C3F,
+static const uint64_t P9N2_PEC_0_SCOM0X3A = 0x80000B7A0D010C3Full;
+//DUPS: 8000043A0D010C3F, 800000BA0D010C3F, 80000A3A0D010C3F, 800000FA0D010C3F, 800001BA0D010C3F, 800001FA0D010C3F, 800003FA0D010C3F, 800003BA0D010C3F, 800002FA0D010C3F, 800002BA0D010C3F, 800009FA0D010C3F, 800009BA0D010C3F, 800008FA0D010C3F, 800008BA0D010C3F, 80000BFA0D010C3F, 80000BBA0D010C3F, 80000AFA0D010C3F, 80000ABA0D010C3F, 8000003A0D010C3F, 8000007A0D010C3F, 8000013A0D010C3F, 8000017A0D010C3F, 8000023A0D010C3F, 8000027A0D010C3F, 8000033A0D010C3F, 8000037A0D010C3F, 8000083A0D010C3F, 8000087A0D010C3F, 8000093A0D010C3F, 8000097A0D010C3F, 80000A7A0D010C3F, 80000B3A0D010C3F,
+static const uint64_t P9N2_PEC_1_SCOM0X3A = 0x80000B7A0E010C3Full;
+//DUPS: 8000043A0E010C3F, 800000BA0E010C3F, 80000A3A0E010C3F, 800000FA0E010C3F, 800001BA0E010C3F, 800001FA0E010C3F, 800003FA0E010C3F, 800003BA0E010C3F, 800002FA0E010C3F, 800002BA0E010C3F, 800009FA0E010C3F, 800009BA0E010C3F, 800008FA0E010C3F, 800008BA0E010C3F, 80000BFA0E010C3F, 80000BBA0E010C3F, 80000AFA0E010C3F, 80000ABA0E010C3F, 8000003A0E010C3F, 8000007A0E010C3F, 8000013A0E010C3F, 8000017A0E010C3F, 8000023A0E010C3F, 8000027A0E010C3F, 8000033A0E010C3F, 8000037A0E010C3F, 8000083A0E010C3F, 8000087A0E010C3F, 8000093A0E010C3F, 8000097A0E010C3F, 80000A7A0E010C3F, 80000B3A0E010C3F,
+static const uint64_t P9N2_PEC_2_SCOM0X3A = 0x80000B7A0F010C3Full;
+//DUPS: 8000043A0F010C3F, 800000BA0F010C3F, 80000A3A0F010C3F, 800000FA0F010C3F, 800001BA0F010C3F, 800001FA0F010C3F, 800003FA0F010C3F, 800003BA0F010C3F, 800002FA0F010C3F, 800002BA0F010C3F, 800009FA0F010C3F, 800009BA0F010C3F, 800008FA0F010C3F, 800008BA0F010C3F, 80000BFA0F010C3F, 80000BBA0F010C3F, 80000AFA0F010C3F, 80000ABA0F010C3F, 8000003A0F010C3F, 8000007A0F010C3F, 8000013A0F010C3F, 8000017A0F010C3F, 8000023A0F010C3F, 8000027A0F010C3F, 8000033A0F010C3F, 8000037A0F010C3F, 8000083A0F010C3F, 8000087A0F010C3F, 8000093A0F010C3F, 8000097A0F010C3F, 80000A7A0F010C3F, 80000B3A0F010C3F,
+
+static const uint64_t P9N2_PEC_SCOM0X3B = 0x80000B7B0D010C3Full;
+//DUPS: 8000043B0D010C3F, 8000053B0D010C3F, 800000BB0D010C3F, 8000057B0D010C3F, 80000A3B0D010C3F, 800000FB0D010C3F, 800001BB0D010C3F, 800001FB0D010C3F, 800003FB0D010C3F, 800003BB0D010C3F, 800002FB0D010C3F, 800002BB0D010C3F, 800009FB0D010C3F, 800009BB0D010C3F, 800008FB0D010C3F, 800008BB0D010C3F, 80000BFB0D010C3F, 80000BBB0D010C3F, 80000AFB0D010C3F, 80000ABB0D010C3F, 8000003B0D010C3F, 8000007B0D010C3F, 8000013B0D010C3F, 8000017B0D010C3F, 8000023B0D010C3F, 8000027B0D010C3F, 8000033B0D010C3F, 8000037B0D010C3F, 8000083B0D010C3F, 8000087B0D010C3F, 8000093B0D010C3F, 8000097B0D010C3F, 80000A7B0D010C3F, 80000B3B0D010C3F,
+static const uint64_t P9N2_PEC_0_SCOM0X3B = 0x80000B7B0D010C3Full;
+//DUPS: 8000043B0D010C3F, 8000053B0D010C3F, 800000BB0D010C3F, 8000057B0D010C3F, 80000A3B0D010C3F, 800000FB0D010C3F, 800001BB0D010C3F, 800001FB0D010C3F, 800003FB0D010C3F, 800003BB0D010C3F, 800002FB0D010C3F, 800002BB0D010C3F, 800009FB0D010C3F, 800009BB0D010C3F, 800008FB0D010C3F, 800008BB0D010C3F, 80000BFB0D010C3F, 80000BBB0D010C3F, 80000AFB0D010C3F, 80000ABB0D010C3F, 8000003B0D010C3F, 8000007B0D010C3F, 8000013B0D010C3F, 8000017B0D010C3F, 8000023B0D010C3F, 8000027B0D010C3F, 8000033B0D010C3F, 8000037B0D010C3F, 8000083B0D010C3F, 8000087B0D010C3F, 8000093B0D010C3F, 8000097B0D010C3F, 80000A7B0D010C3F, 80000B3B0D010C3F,
+static const uint64_t P9N2_PEC_1_SCOM0X3B = 0x80000B7B0E010C3Full;
+//DUPS: 8000043B0E010C3F, 8000053B0E010C3F, 800000BB0E010C3F, 8000057B0E010C3F, 80000A3B0E010C3F, 800000FB0E010C3F, 800001BB0E010C3F, 800001FB0E010C3F, 800003FB0E010C3F, 800003BB0E010C3F, 800002FB0E010C3F, 800002BB0E010C3F, 800009FB0E010C3F, 800009BB0E010C3F, 800008FB0E010C3F, 800008BB0E010C3F, 80000BFB0E010C3F, 80000BBB0E010C3F, 80000AFB0E010C3F, 80000ABB0E010C3F, 8000003B0E010C3F, 8000007B0E010C3F, 8000013B0E010C3F, 8000017B0E010C3F, 8000023B0E010C3F, 8000027B0E010C3F, 8000033B0E010C3F, 8000037B0E010C3F, 8000083B0E010C3F, 8000087B0E010C3F, 8000093B0E010C3F, 8000097B0E010C3F, 80000A7B0E010C3F, 80000B3B0E010C3F,
+static const uint64_t P9N2_PEC_2_SCOM0X3B = 0x80000B7B0F010C3Full;
+//DUPS: 8000043B0F010C3F, 8000053B0F010C3F, 800000BB0F010C3F, 8000057B0F010C3F, 80000A3B0F010C3F, 800000FB0F010C3F, 800001BB0F010C3F, 800001FB0F010C3F, 800003FB0F010C3F, 800003BB0F010C3F, 800002FB0F010C3F, 800002BB0F010C3F, 800009FB0F010C3F, 800009BB0F010C3F, 800008FB0F010C3F, 800008BB0F010C3F, 80000BFB0F010C3F, 80000BBB0F010C3F, 80000AFB0F010C3F, 80000ABB0F010C3F, 8000003B0F010C3F, 8000007B0F010C3F, 8000013B0F010C3F, 8000017B0F010C3F, 8000023B0F010C3F, 8000027B0F010C3F, 8000033B0F010C3F, 8000037B0F010C3F, 8000083B0F010C3F, 8000087B0F010C3F, 8000093B0F010C3F, 8000097B0F010C3F, 80000A7B0F010C3F, 80000B3B0F010C3F,
+
+static const uint64_t P9N2_PEC_SCOM0X3C = 0x80000B7C0D010C3Full;
+//DUPS: 8000053C0D010C3F, 800000BC0D010C3F, 8000057C0D010C3F, 80000A3C0D010C3F, 800000FC0D010C3F, 800001BC0D010C3F, 800001FC0D010C3F, 800003FC0D010C3F, 800003BC0D010C3F, 800002FC0D010C3F, 800002BC0D010C3F, 800009FC0D010C3F, 800009BC0D010C3F, 800008FC0D010C3F, 800008BC0D010C3F, 80000BFC0D010C3F, 80000BBC0D010C3F, 80000AFC0D010C3F, 80000ABC0D010C3F, 8000003C0D010C3F, 8000007C0D010C3F, 8000013C0D010C3F, 8000017C0D010C3F, 8000023C0D010C3F, 8000027C0D010C3F, 8000033C0D010C3F, 8000037C0D010C3F, 8000083C0D010C3F, 8000087C0D010C3F, 8000093C0D010C3F, 8000097C0D010C3F, 80000A7C0D010C3F, 80000B3C0D010C3F,
+static const uint64_t P9N2_PEC_0_SCOM0X3C = 0x80000B7C0D010C3Full;
+//DUPS: 8000053C0D010C3F, 800000BC0D010C3F, 8000057C0D010C3F, 80000A3C0D010C3F, 800000FC0D010C3F, 800001BC0D010C3F, 800001FC0D010C3F, 800003FC0D010C3F, 800003BC0D010C3F, 800002FC0D010C3F, 800002BC0D010C3F, 800009FC0D010C3F, 800009BC0D010C3F, 800008FC0D010C3F, 800008BC0D010C3F, 80000BFC0D010C3F, 80000BBC0D010C3F, 80000AFC0D010C3F, 80000ABC0D010C3F, 8000003C0D010C3F, 8000007C0D010C3F, 8000013C0D010C3F, 8000017C0D010C3F, 8000023C0D010C3F, 8000027C0D010C3F, 8000033C0D010C3F, 8000037C0D010C3F, 8000083C0D010C3F, 8000087C0D010C3F, 8000093C0D010C3F, 8000097C0D010C3F, 80000A7C0D010C3F, 80000B3C0D010C3F,
+static const uint64_t P9N2_PEC_1_SCOM0X3C = 0x80000B7C0E010C3Full;
+//DUPS: 8000053C0E010C3F, 800000BC0E010C3F, 8000057C0E010C3F, 80000A3C0E010C3F, 800000FC0E010C3F, 800001BC0E010C3F, 800001FC0E010C3F, 800003FC0E010C3F, 800003BC0E010C3F, 800002FC0E010C3F, 800002BC0E010C3F, 800009FC0E010C3F, 800009BC0E010C3F, 800008FC0E010C3F, 800008BC0E010C3F, 80000BFC0E010C3F, 80000BBC0E010C3F, 80000AFC0E010C3F, 80000ABC0E010C3F, 8000003C0E010C3F, 8000007C0E010C3F, 8000013C0E010C3F, 8000017C0E010C3F, 8000023C0E010C3F, 8000027C0E010C3F, 8000033C0E010C3F, 8000037C0E010C3F, 8000083C0E010C3F, 8000087C0E010C3F, 8000093C0E010C3F, 8000097C0E010C3F, 80000A7C0E010C3F, 80000B3C0E010C3F,
+static const uint64_t P9N2_PEC_2_SCOM0X3C = 0x80000B7C0F010C3Full;
+//DUPS: 8000053C0F010C3F, 800000BC0F010C3F, 8000057C0F010C3F, 80000A3C0F010C3F, 800000FC0F010C3F, 800001BC0F010C3F, 800001FC0F010C3F, 800003FC0F010C3F, 800003BC0F010C3F, 800002FC0F010C3F, 800002BC0F010C3F, 800009FC0F010C3F, 800009BC0F010C3F, 800008FC0F010C3F, 800008BC0F010C3F, 80000BFC0F010C3F, 80000BBC0F010C3F, 80000AFC0F010C3F, 80000ABC0F010C3F, 8000003C0F010C3F, 8000007C0F010C3F, 8000013C0F010C3F, 8000017C0F010C3F, 8000023C0F010C3F, 8000027C0F010C3F, 8000033C0F010C3F, 8000037C0F010C3F, 8000083C0F010C3F, 8000087C0F010C3F, 8000093C0F010C3F, 8000097C0F010C3F, 80000A7C0F010C3F, 80000B3C0F010C3F,
+
+static const uint64_t P9N2_PEC_SCOM0X3D = 0x80000B7D0D010C3Full;
+//DUPS: 8000053D0D010C3F, 800000BD0D010C3F, 8000057D0D010C3F, 80000A3D0D010C3F, 800000FD0D010C3F, 800001BD0D010C3F, 800001FD0D010C3F, 800003FD0D010C3F, 800003BD0D010C3F, 800002FD0D010C3F, 800002BD0D010C3F, 800009FD0D010C3F, 800009BD0D010C3F, 800008FD0D010C3F, 800008BD0D010C3F, 80000BFD0D010C3F, 80000BBD0D010C3F, 80000AFD0D010C3F, 80000ABD0D010C3F, 8000003D0D010C3F, 8000007D0D010C3F, 8000013D0D010C3F, 8000017D0D010C3F, 8000023D0D010C3F, 8000027D0D010C3F, 8000033D0D010C3F, 8000037D0D010C3F, 8000083D0D010C3F, 8000087D0D010C3F, 8000093D0D010C3F, 8000097D0D010C3F, 80000A7D0D010C3F, 80000B3D0D010C3F,
+static const uint64_t P9N2_PEC_0_SCOM0X3D = 0x80000B7D0D010C3Full;
+//DUPS: 8000053D0D010C3F, 800000BD0D010C3F, 8000057D0D010C3F, 80000A3D0D010C3F, 800000FD0D010C3F, 800001BD0D010C3F, 800001FD0D010C3F, 800003FD0D010C3F, 800003BD0D010C3F, 800002FD0D010C3F, 800002BD0D010C3F, 800009FD0D010C3F, 800009BD0D010C3F, 800008FD0D010C3F, 800008BD0D010C3F, 80000BFD0D010C3F, 80000BBD0D010C3F, 80000AFD0D010C3F, 80000ABD0D010C3F, 8000003D0D010C3F, 8000007D0D010C3F, 8000013D0D010C3F, 8000017D0D010C3F, 8000023D0D010C3F, 8000027D0D010C3F, 8000033D0D010C3F, 8000037D0D010C3F, 8000083D0D010C3F, 8000087D0D010C3F, 8000093D0D010C3F, 8000097D0D010C3F, 80000A7D0D010C3F, 80000B3D0D010C3F,
+static const uint64_t P9N2_PEC_1_SCOM0X3D = 0x80000B7D0E010C3Full;
+//DUPS: 8000053D0E010C3F, 800000BD0E010C3F, 8000057D0E010C3F, 80000A3D0E010C3F, 800000FD0E010C3F, 800001BD0E010C3F, 800001FD0E010C3F, 800003FD0E010C3F, 800003BD0E010C3F, 800002FD0E010C3F, 800002BD0E010C3F, 800009FD0E010C3F, 800009BD0E010C3F, 800008FD0E010C3F, 800008BD0E010C3F, 80000BFD0E010C3F, 80000BBD0E010C3F, 80000AFD0E010C3F, 80000ABD0E010C3F, 8000003D0E010C3F, 8000007D0E010C3F, 8000013D0E010C3F, 8000017D0E010C3F, 8000023D0E010C3F, 8000027D0E010C3F, 8000033D0E010C3F, 8000037D0E010C3F, 8000083D0E010C3F, 8000087D0E010C3F, 8000093D0E010C3F, 8000097D0E010C3F, 80000A7D0E010C3F, 80000B3D0E010C3F,
+static const uint64_t P9N2_PEC_2_SCOM0X3D = 0x80000B7D0F010C3Full;
+//DUPS: 8000053D0F010C3F, 800000BD0F010C3F, 8000057D0F010C3F, 80000A3D0F010C3F, 800000FD0F010C3F, 800001BD0F010C3F, 800001FD0F010C3F, 800003FD0F010C3F, 800003BD0F010C3F, 800002FD0F010C3F, 800002BD0F010C3F, 800009FD0F010C3F, 800009BD0F010C3F, 800008FD0F010C3F, 800008BD0F010C3F, 80000BFD0F010C3F, 80000BBD0F010C3F, 80000AFD0F010C3F, 80000ABD0F010C3F, 8000003D0F010C3F, 8000007D0F010C3F, 8000013D0F010C3F, 8000017D0F010C3F, 8000023D0F010C3F, 8000027D0F010C3F, 8000033D0F010C3F, 8000037D0F010C3F, 8000083D0F010C3F, 8000087D0F010C3F, 8000093D0F010C3F, 8000097D0F010C3F, 80000A7D0F010C3F, 80000B3D0F010C3F,
+
+static const uint64_t P9N2_PEC_SCOM0X3E = 0x80000B7E0D010C3Full;
+//DUPS: 8000053E0D010C3F, 800000BE0D010C3F, 8000057E0D010C3F, 80000A3E0D010C3F, 800000FE0D010C3F, 800001BE0D010C3F, 800001FE0D010C3F, 800003FE0D010C3F, 800003BE0D010C3F, 800002FE0D010C3F, 800002BE0D010C3F, 800009FE0D010C3F, 800009BE0D010C3F, 800008FE0D010C3F, 800008BE0D010C3F, 80000BFE0D010C3F, 80000BBE0D010C3F, 80000AFE0D010C3F, 80000ABE0D010C3F, 8000003E0D010C3F, 8000007E0D010C3F, 8000013E0D010C3F, 8000017E0D010C3F, 8000023E0D010C3F, 8000027E0D010C3F, 8000033E0D010C3F, 8000037E0D010C3F, 8000083E0D010C3F, 8000087E0D010C3F, 8000093E0D010C3F, 8000097E0D010C3F, 80000A7E0D010C3F, 80000B3E0D010C3F,
+static const uint64_t P9N2_PEC_0_SCOM0X3E = 0x80000B7E0D010C3Full;
+//DUPS: 8000053E0D010C3F, 800000BE0D010C3F, 8000057E0D010C3F, 80000A3E0D010C3F, 800000FE0D010C3F, 800001BE0D010C3F, 800001FE0D010C3F, 800003FE0D010C3F, 800003BE0D010C3F, 800002FE0D010C3F, 800002BE0D010C3F, 800009FE0D010C3F, 800009BE0D010C3F, 800008FE0D010C3F, 800008BE0D010C3F, 80000BFE0D010C3F, 80000BBE0D010C3F, 80000AFE0D010C3F, 80000ABE0D010C3F, 8000003E0D010C3F, 8000007E0D010C3F, 8000013E0D010C3F, 8000017E0D010C3F, 8000023E0D010C3F, 8000027E0D010C3F, 8000033E0D010C3F, 8000037E0D010C3F, 8000083E0D010C3F, 8000087E0D010C3F, 8000093E0D010C3F, 8000097E0D010C3F, 80000A7E0D010C3F, 80000B3E0D010C3F,
+static const uint64_t P9N2_PEC_1_SCOM0X3E = 0x80000B7E0E010C3Full;
+//DUPS: 8000053E0E010C3F, 800000BE0E010C3F, 8000057E0E010C3F, 80000A3E0E010C3F, 800000FE0E010C3F, 800001BE0E010C3F, 800001FE0E010C3F, 800003FE0E010C3F, 800003BE0E010C3F, 800002FE0E010C3F, 800002BE0E010C3F, 800009FE0E010C3F, 800009BE0E010C3F, 800008FE0E010C3F, 800008BE0E010C3F, 80000BFE0E010C3F, 80000BBE0E010C3F, 80000AFE0E010C3F, 80000ABE0E010C3F, 8000003E0E010C3F, 8000007E0E010C3F, 8000013E0E010C3F, 8000017E0E010C3F, 8000023E0E010C3F, 8000027E0E010C3F, 8000033E0E010C3F, 8000037E0E010C3F, 8000083E0E010C3F, 8000087E0E010C3F, 8000093E0E010C3F, 8000097E0E010C3F, 80000A7E0E010C3F, 80000B3E0E010C3F,
+static const uint64_t P9N2_PEC_2_SCOM0X3E = 0x80000B7E0F010C3Full;
+//DUPS: 8000053E0F010C3F, 800000BE0F010C3F, 8000057E0F010C3F, 80000A3E0F010C3F, 800000FE0F010C3F, 800001BE0F010C3F, 800001FE0F010C3F, 800003FE0F010C3F, 800003BE0F010C3F, 800002FE0F010C3F, 800002BE0F010C3F, 800009FE0F010C3F, 800009BE0F010C3F, 800008FE0F010C3F, 800008BE0F010C3F, 80000BFE0F010C3F, 80000BBE0F010C3F, 80000AFE0F010C3F, 80000ABE0F010C3F, 8000003E0F010C3F, 8000007E0F010C3F, 8000013E0F010C3F, 8000017E0F010C3F, 8000023E0F010C3F, 8000027E0F010C3F, 8000033E0F010C3F, 8000037E0F010C3F, 8000083E0F010C3F, 8000087E0F010C3F, 8000093E0F010C3F, 8000097E0F010C3F, 80000A7E0F010C3F, 80000B3E0F010C3F,
+
+static const uint64_t P9N2_PEC_SCOM0X3F = 0x80000B7F0D010C3Full;
+//DUPS: 8000053F0D010C3F, 800000BF0D010C3F, 8000057F0D010C3F, 80000A3F0D010C3F, 800000FF0D010C3F, 800001BF0D010C3F, 800001FF0D010C3F, 800003FF0D010C3F, 800003BF0D010C3F, 800002FF0D010C3F, 800002BF0D010C3F, 800009FF0D010C3F, 800009BF0D010C3F, 800008FF0D010C3F, 800008BF0D010C3F, 80000BFF0D010C3F, 80000BBF0D010C3F, 80000AFF0D010C3F, 80000ABF0D010C3F, 8000003F0D010C3F, 8000007F0D010C3F, 8000013F0D010C3F, 8000017F0D010C3F, 8000023F0D010C3F, 8000027F0D010C3F, 8000033F0D010C3F, 8000037F0D010C3F, 8000083F0D010C3F, 8000087F0D010C3F, 8000093F0D010C3F, 8000097F0D010C3F, 80000A7F0D010C3F, 80000B3F0D010C3F,
+static const uint64_t P9N2_PEC_0_SCOM0X3F = 0x80000B7F0D010C3Full;
+//DUPS: 8000053F0D010C3F, 800000BF0D010C3F, 8000057F0D010C3F, 80000A3F0D010C3F, 800000FF0D010C3F, 800001BF0D010C3F, 800001FF0D010C3F, 800003FF0D010C3F, 800003BF0D010C3F, 800002FF0D010C3F, 800002BF0D010C3F, 800009FF0D010C3F, 800009BF0D010C3F, 800008FF0D010C3F, 800008BF0D010C3F, 80000BFF0D010C3F, 80000BBF0D010C3F, 80000AFF0D010C3F, 80000ABF0D010C3F, 8000003F0D010C3F, 8000007F0D010C3F, 8000013F0D010C3F, 8000017F0D010C3F, 8000023F0D010C3F, 8000027F0D010C3F, 8000033F0D010C3F, 8000037F0D010C3F, 8000083F0D010C3F, 8000087F0D010C3F, 8000093F0D010C3F, 8000097F0D010C3F, 80000A7F0D010C3F, 80000B3F0D010C3F,
+static const uint64_t P9N2_PEC_1_SCOM0X3F = 0x80000B7F0E010C3Full;
+//DUPS: 8000053F0E010C3F, 800000BF0E010C3F, 8000057F0E010C3F, 80000A3F0E010C3F, 800000FF0E010C3F, 800001BF0E010C3F, 800001FF0E010C3F, 800003FF0E010C3F, 800003BF0E010C3F, 800002FF0E010C3F, 800002BF0E010C3F, 800009FF0E010C3F, 800009BF0E010C3F, 800008FF0E010C3F, 800008BF0E010C3F, 80000BFF0E010C3F, 80000BBF0E010C3F, 80000AFF0E010C3F, 80000ABF0E010C3F, 8000003F0E010C3F, 8000007F0E010C3F, 8000013F0E010C3F, 8000017F0E010C3F, 8000023F0E010C3F, 8000027F0E010C3F, 8000033F0E010C3F, 8000037F0E010C3F, 8000083F0E010C3F, 8000087F0E010C3F, 8000093F0E010C3F, 8000097F0E010C3F, 80000A7F0E010C3F, 80000B3F0E010C3F,
+static const uint64_t P9N2_PEC_2_SCOM0X3F = 0x80000B7F0F010C3Full;
+//DUPS: 8000053F0F010C3F, 800000BF0F010C3F, 8000057F0F010C3F, 80000A3F0F010C3F, 800000FF0F010C3F, 800001BF0F010C3F, 800001FF0F010C3F, 800003FF0F010C3F, 800003BF0F010C3F, 800002FF0F010C3F, 800002BF0F010C3F, 800009FF0F010C3F, 800009BF0F010C3F, 800008FF0F010C3F, 800008BF0F010C3F, 80000BFF0F010C3F, 80000BBF0F010C3F, 80000AFF0F010C3F, 80000ABF0F010C3F, 8000003F0F010C3F, 8000007F0F010C3F, 8000013F0F010C3F, 8000017F0F010C3F, 8000023F0F010C3F, 8000027F0F010C3F, 8000033F0F010C3F, 8000037F0F010C3F, 8000083F0F010C3F, 8000087F0F010C3F, 8000093F0F010C3F, 8000097F0F010C3F, 80000A7F0F010C3F, 80000B3F0F010C3F,
+
+static const uint64_t P9N2_PU_SCOM_PPE_CNTL = 0x0C011060ull;
+//DUPS: 0C011060,
+
+static const uint64_t P9N2_PU_SCOM_PPE_FLAGS = 0x0C011063ull;
+//DUPS: 0C011063,
+static const uint64_t P9N2_PU_SCOM_PPE_FLAGS_OR = 0x0C011064ull;
+//DUPS: 0C011064,
+static const uint64_t P9N2_PU_SCOM_PPE_FLAGS_CLEAR = 0x0C011065ull;
+//DUPS: 0C011065,
+
+static const uint64_t P9N2_PU_SCOM_PPE_WORK_REG1 = 0x0C011061ull;
+//DUPS: 0C011061,
+
+static const uint64_t P9N2_PU_SCOM_PPE_WORK_REG2 = 0x0C011062ull;
+//DUPS: 0C011062,
+
+static const uint64_t P9N2_PU_SCRATCH0_PPE = 0xC0001000ull;
+
+static const uint64_t P9N2_PU_SCRATCH0_PPE1 = 0xC0001010ull;
+
+static const uint64_t P9N2_PU_SCRATCH0_PPE2 = 0xC0001018ull;
+
+static const uint64_t P9N2_NV_1_SCRATCH0 = 0x050110F3ull;
+
+static const uint64_t P9N2_NV_5_SCRATCH0 = 0x050114F3ull;
+
+static const uint64_t P9N2_PU_NPU2_NTL1_SCRATCH0 = 0x050112F3ull;
+
+
+static const uint64_t P9N2_PU_SCRATCH1_PPE = 0xC0001020ull;
+
+static const uint64_t P9N2_PU_SCRATCH1_PPE1 = 0xC0001030ull;
+
+static const uint64_t P9N2_PU_SCRATCH1_PPE2 = 0xC0001038ull;
+
+static const uint64_t P9N2_PU_NPU1_SM0_SCRATCH1 = 0x0501110Cull;
+
+static const uint64_t P9N2_PU_NPU1_SM1_SCRATCH1 = 0x0501112Aull;
+
+static const uint64_t P9N2_PU_NPU1_SM2_SCRATCH1 = 0x0501114Aull;
+
+static const uint64_t P9N2_PU_NPU_SM0_SCRATCH1 = 0x0501130Cull;
+
+static const uint64_t P9N2_PU_NPU_SM1_SCRATCH1 = 0x0501132Aull;
+
+static const uint64_t P9N2_PU_NPU_SM2_SCRATCH1 = 0x0501134Aull;
+
+static const uint64_t P9N2__SM0_SCRATCH1 = 0x0501150Cull;
+
+static const uint64_t P9N2__SM1_SCRATCH1 = 0x0501152Aull;
+
+static const uint64_t P9N2__SM2_SCRATCH1 = 0x0501154Aull;
+
+
+static const uint64_t P9N2_PU_SCRATCH2_PPE = 0xC0001040ull;
+
+static const uint64_t P9N2_PU_SCRATCH2_PPE1 = 0xC0001050ull;
+
+static const uint64_t P9N2_PU_SCRATCH2_PPE2 = 0xC0001058ull;
+
+static const uint64_t P9N2_PU_NPU1_SM0_SCRATCH2 = 0x0501111Aull;
+
+static const uint64_t P9N2_PU_NPU1_SM1_SCRATCH2 = 0x0501113Aull;
+
+static const uint64_t P9N2_PU_NPU_SM0_SCRATCH2 = 0x0501131Aull;
+
+static const uint64_t P9N2_PU_NPU_SM1_SCRATCH2 = 0x0501133Aull;
+
+static const uint64_t P9N2__SM0_SCRATCH2 = 0x0501151Aull;
+
+static const uint64_t P9N2__SM1_SCRATCH2 = 0x0501153Aull;
+
+
+static const uint64_t P9N2_PU_SCRATCH3_PPE = 0xC0001060ull;
+
+static const uint64_t P9N2_PU_SCRATCH3_PPE1 = 0xC0001070ull;
+
+static const uint64_t P9N2_PU_SCRATCH3_PPE2 = 0xC0001078ull;
+
+static const uint64_t P9N2_PU_NPU1_SM0_SCRATCH3 = 0x0501111Bull;
+
+static const uint64_t P9N2_PU_NPU1_SM1_SCRATCH3 = 0x0501113Bull;
+
+static const uint64_t P9N2_PU_NPU_SM0_SCRATCH3 = 0x0501131Bull;
+
+static const uint64_t P9N2_PU_NPU_SM1_SCRATCH3 = 0x0501133Bull;
+
+static const uint64_t P9N2__SM0_SCRATCH3 = 0x0501151Bull;
+
+static const uint64_t P9N2__SM1_SCRATCH3 = 0x0501153Bull;
+
+
+static const uint64_t P9N2_PU_SECURITY_SWITCH_REGISTER_SCOM = 0x00010005ull;
+
+static const uint64_t P9N2_PU_SECURITY_SWITCH_REGISTER_SCOM1 = 0x00010006ull;
+
+
+static const uint64_t P9N2_PU_SEND_WC_BASE_ADDR = 0x020110D2ull;
+
+
+static const uint64_t P9N2_PEC_SKITTER_CLKSRC_REG = 0x0D050016ull;
+
+static const uint64_t P9N2_PEC_0_SKITTER_CLKSRC_REG = 0x0D050016ull;
+
+static const uint64_t P9N2_PEC_1_SKITTER_CLKSRC_REG = 0x0E050016ull;
+
+static const uint64_t P9N2_PEC_2_SKITTER_CLKSRC_REG = 0x0F050016ull;
+
+
+static const uint64_t P9N2_PEC_SKITTER_DATA0 = 0x0D050019ull;
+
+static const uint64_t P9N2_PEC_0_SKITTER_DATA0 = 0x0D050019ull;
+
+static const uint64_t P9N2_PEC_1_SKITTER_DATA0 = 0x0E050019ull;
+
+static const uint64_t P9N2_PEC_2_SKITTER_DATA0 = 0x0F050019ull;
+
+
+static const uint64_t P9N2_PEC_SKITTER_DATA1 = 0x0D05001Aull;
+
+static const uint64_t P9N2_PEC_0_SKITTER_DATA1 = 0x0D05001Aull;
+
+static const uint64_t P9N2_PEC_1_SKITTER_DATA1 = 0x0E05001Aull;
+
+static const uint64_t P9N2_PEC_2_SKITTER_DATA1 = 0x0F05001Aull;
+
+
+static const uint64_t P9N2_PEC_SKITTER_DATA2 = 0x0D05001Bull;
+
+static const uint64_t P9N2_PEC_0_SKITTER_DATA2 = 0x0D05001Bull;
+
+static const uint64_t P9N2_PEC_1_SKITTER_DATA2 = 0x0E05001Bull;
+
+static const uint64_t P9N2_PEC_2_SKITTER_DATA2 = 0x0F05001Bull;
+
+
+static const uint64_t P9N2_PEC_SKITTER_FORCE_REG = 0x0D050014ull;
+
+static const uint64_t P9N2_PEC_0_SKITTER_FORCE_REG = 0x0D050014ull;
+
+static const uint64_t P9N2_PEC_1_SKITTER_FORCE_REG = 0x0E050014ull;
+
+static const uint64_t P9N2_PEC_2_SKITTER_FORCE_REG = 0x0F050014ull;
+
+
+static const uint64_t P9N2_PEC_SKITTER_MODE_REG = 0x0D050010ull;
+
+static const uint64_t P9N2_PEC_0_SKITTER_MODE_REG = 0x0D050010ull;
+
+static const uint64_t P9N2_PEC_1_SKITTER_MODE_REG = 0x0E050010ull;
+
+static const uint64_t P9N2_PEC_2_SKITTER_MODE_REG = 0x0F050010ull;
+
+
+static const uint64_t P9N2_PEC_SLAVE_CONFIG_REG = 0x0D0F001Eull;
+
+static const uint64_t P9N2_PEC_0_SLAVE_CONFIG_REG = 0x0D0F001Eull;
+
+static const uint64_t P9N2_PEC_1_SLAVE_CONFIG_REG = 0x0E0F001Eull;
+
+static const uint64_t P9N2_PEC_2_SLAVE_CONFIG_REG = 0x0F0F001Eull;
+
+
+static const uint64_t P9N2_PU_SMF_CONFIG_REG_0 = 0x05013C0Aull;
+
+
+static const uint64_t P9N2_PU_NPU0_SM_STATUS = 0x050110A6ull;
+
+static const uint64_t P9N2_PU_NPU2_SM_STATUS = 0x050112A6ull;
+
+static const uint64_t P9N2_PU_NPU0_SM0_SM_STATUS = 0x05011016ull;
+
+static const uint64_t P9N2_PU_NPU0_SM2_SM_STATUS = 0x05011046ull;
+
+static const uint64_t P9N2_PU_NPU0_SM3_SM_STATUS = 0x05011076ull;
+
+static const uint64_t P9N2_PU_NPU2_SM0_SM_STATUS = 0x05011216ull;
+
+static const uint64_t P9N2_PU_NPU2_SM2_SM_STATUS = 0x05011246ull;
+
+static const uint64_t P9N2_PU_NPU2_SM3_SM_STATUS = 0x05011276ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM_STATUS = 0x050114A6ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM0_SM_STATUS = 0x05011416ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM2_SM_STATUS = 0x05011446ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM3_SM_STATUS = 0x05011476ull;
+
+
+static const uint64_t P9N2_PU_SND_MODE_REG = 0x00090021ull;
+
+
+static const uint64_t P9N2_PU_SND_STAT_REG = 0x00090020ull;
+
+
+static const uint64_t P9N2_PEC_SPATTN_SCOM = 0x0D040004ull;
+
+static const uint64_t P9N2_PEC_SPATTN_SCOM1 = 0x0D040005ull;
+
+static const uint64_t P9N2_PEC_SPATTN_SCOM2 = 0x0D040006ull;
+
+static const uint64_t P9N2_PEC_0_SPATTN_SCOM = 0x0D040004ull;
+
+static const uint64_t P9N2_PEC_0_SPATTN_SCOM1 = 0x0D040005ull;
+
+static const uint64_t P9N2_PEC_0_SPATTN_SCOM2 = 0x0D040006ull;
+
+static const uint64_t P9N2_PEC_1_SPATTN_SCOM = 0x0E040004ull;
+
+static const uint64_t P9N2_PEC_1_SPATTN_SCOM1 = 0x0E040005ull;
+
+static const uint64_t P9N2_PEC_1_SPATTN_SCOM2 = 0x0E040006ull;
+
+static const uint64_t P9N2_PEC_2_SPATTN_SCOM = 0x0F040004ull;
+
+static const uint64_t P9N2_PEC_2_SPATTN_SCOM1 = 0x0F040005ull;
+
+static const uint64_t P9N2_PEC_2_SPATTN_SCOM2 = 0x0F040006ull;
+
+
+static const uint64_t P9N2_PEC_SPA_MASK = 0x0D040007ull;
+
+static const uint64_t P9N2_PEC_0_SPA_MASK = 0x0D040007ull;
+
+static const uint64_t P9N2_PEC_1_SPA_MASK = 0x0E040007ull;
+
+static const uint64_t P9N2_PEC_2_SPA_MASK = 0x0F040007ull;
+
+
+static const uint64_t P9N2_PU_SPIMPSS_ADC_CTRL_REG0 = 0x00070000ull;
+
+
+static const uint64_t P9N2_PU_SPIPSS_100NS_REG = 0x00070028ull;
+
+
+static const uint64_t P9N2_PU_SPIPSS_ADC_CMD_REG = 0x00070004ull;
+
+
+static const uint64_t P9N2_PU_SPIPSS_ADC_CTRL_REG1 = 0x00070001ull;
+
+
+static const uint64_t P9N2_PU_SPIPSS_ADC_CTRL_REG2 = 0x00070002ull;
+
+
+static const uint64_t P9N2_PU_SPIPSS_ADC_RDATA_REG0 = 0x00070020ull;
+
+
+static const uint64_t P9N2_PU_SPIPSS_ADC_RDATA_REG1 = 0x00070021ull;
+
+
+static const uint64_t P9N2_PU_SPIPSS_ADC_RDATA_REG2 = 0x00070022ull;
+
+
+static const uint64_t P9N2_PU_SPIPSS_ADC_RDATA_REG3 = 0x00070023ull;
+
+
+static const uint64_t P9N2_PU_SPIPSS_ADC_RESET_REGISTER = 0x00070005ull;
+
+
+static const uint64_t P9N2_PU_SPIPSS_ADC_STATUS_REG = 0x00070003ull;
+
+
+static const uint64_t P9N2_PU_SPIPSS_ADC_WDATA_REG = 0x00070010ull;
+
+
+static const uint64_t P9N2_PU_SPIPSS_P2S_COMMAND_REG = 0x00070044ull;
+
+
+static const uint64_t P9N2_PU_SPIPSS_P2S_CTRL_REG0 = 0x00070040ull;
+
+
+static const uint64_t P9N2_PU_SPIPSS_P2S_CTRL_REG1 = 0x00070041ull;
+
+
+static const uint64_t P9N2_PU_SPIPSS_P2S_CTRL_REG2 = 0x00070042ull;
+
+
+static const uint64_t P9N2_PU_SPIPSS_P2S_RDATA_REG = 0x00070060ull;
+
+
+static const uint64_t P9N2_PU_SPIPSS_P2S_RESET_REGISTER = 0x00070045ull;
+
+
+static const uint64_t P9N2_PU_SPIPSS_P2S_STATUS_REG = 0x00070043ull;
+
+
+static const uint64_t P9N2_PU_SPIPSS_P2S_WDATA_REG = 0x00070050ull;
+
+
+static const uint64_t P9N2_PU_SRAM_SRBV0_OCI = 0xC0050020ull;
+
+static const uint64_t P9N2_PU_SRAM_SRBV0_SCOM = 0x0006A004ull;
+
+
+static const uint64_t P9N2_PU_SRAM_SRBV1_OCI = 0xC0050028ull;
+
+static const uint64_t P9N2_PU_SRAM_SRBV1_SCOM = 0x0006A005ull;
+
+
+static const uint64_t P9N2_PU_SRAM_SRBV2_OCI = 0xC0050030ull;
+
+static const uint64_t P9N2_PU_SRAM_SRBV2_SCOM = 0x0006A006ull;
+
+
+static const uint64_t P9N2_PU_SRAM_SRBV3_OCI = 0xC0050038ull;
+
+static const uint64_t P9N2_PU_SRAM_SRBV3_SCOM = 0x0006A007ull;
+
+
+static const uint64_t P9N2_PU_SRAM_SRCHSW_OCI = 0xC0050040ull;
+
+static const uint64_t P9N2_PU_SRAM_SRCHSW_SCOM = 0x0006A008ull;
+
+
+static const uint64_t P9N2_PU_SRAM_SREAR_OCI = 0xC0050018ull;
+
+static const uint64_t P9N2_PU_SRAM_SREAR_SCOM = 0x0006A003ull;
+
+
+static const uint64_t P9N2_PU_SRAM_SRMAP_OCI = 0xC0050010ull;
+
+static const uint64_t P9N2_PU_SRAM_SRMAP_SCOM = 0x0006A002ull;
+
+
+static const uint64_t P9N2_PU_SRAM_SRMR_OCI = 0xC0050008ull;
+
+static const uint64_t P9N2_PU_SRAM_SRMR_SCOM = 0x0006A001ull;
+
+
+static const uint64_t P9N2_PU_STATUS_REGISTER = 0x00010002ull;
+
+
+static const uint64_t P9N2_PU_STATUS_REGISTER_B = 0x000A0002ull;
+
+
+static const uint64_t P9N2_PU_STATUS_REGISTER_C = 0x000A1002ull;
+
+
+static const uint64_t P9N2_PU_STATUS_REGISTER_D = 0x000A2002ull;
+
+
+static const uint64_t P9N2_PU_STATUS_REGISTER_E = 0x000A3002ull;
+
+
+static const uint64_t P9N2_PU_STATUS_REGISTER_ENGINE_B = 0x000A000Bull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+
+static const uint64_t P9N2_PU_STATUS_REGISTER_ENGINE_C = 0x000A100Bull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+
+static const uint64_t P9N2_PU_STATUS_REGISTER_ENGINE_D = 0x000A200Bull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+
+static const uint64_t P9N2_PU_STATUS_REGISTER_ENGINE_E = 0x000A300Bull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+
+static const uint64_t P9N2_PEC_SUM_MASK_REG = 0x0D040017ull;
+
+static const uint64_t P9N2_PEC_0_SUM_MASK_REG = 0x0D040017ull;
+
+static const uint64_t P9N2_PEC_1_SUM_MASK_REG = 0x0E040017ull;
+
+static const uint64_t P9N2_PEC_2_SUM_MASK_REG = 0x0F040017ull;
+
+
+static const uint64_t P9N2_PU_SU_CH0_ABORT_CSB = 0x02011043ull;
+
+
+static const uint64_t P9N2_PU_SU_CH1_ABORT_CSB = 0x02011045ull;
+
+
+static const uint64_t P9N2_PU_SU_CH2_ABORT_CSB = 0x02011047ull;
+
+
+static const uint64_t P9N2_PU_SU_CH3_ABORT_CSB = 0x02011049ull;
+
+
+static const uint64_t P9N2_PU_SU_CH4_ABORT_CSB = 0x0201104Bull;
+
+
+static const uint64_t P9N2_PU_SU_CRB_KILL_REQ = 0x02011053ull;
+
+
+static const uint64_t P9N2_PU_SU_DMA_ERROR_REPORT_0 = 0x02011057ull;
+
+
+static const uint64_t P9N2_PU_SU_DMA_ERROR_REPORT_1 = 0x02011058ull;
+
+
+static const uint64_t P9N2_PU_SU_ENGINE_ENABLE = 0x02011041ull;
+
+
+static const uint64_t P9N2_PU_SU_ERAT_ERROR_RPT = 0x020110D7ull;
+
+
+static const uint64_t P9N2_PU_SU_INBOUND_WRITE_CONTROL = 0x02011042ull;
+
+
+static const uint64_t P9N2_PU_SU_PERFMON_CONTROL_0 = 0x02011054ull;
+
+
+static const uint64_t P9N2_PU_SU_PERFMON_CONTROL_1 = 0x02011055ull;
+
+
+static const uint64_t P9N2_PU_SU_STATUS = 0x02011040ull;
+
+
+static const uint64_t P9N2_PU_SU_UMAC_ERROR_RPT = 0x020110D3ull;
+
+
+static const uint64_t P9N2_PU_SU_UMAC_ERROR_RPT1 = 0x020110D8ull;
+
+
+static const uint64_t P9N2_PU_SYM_HI_PRIOR_RCV_FIFO_ASB = 0x020110C7ull;
+
+
+static const uint64_t P9N2_PU_SYM_HI_PRIOR_RCV_FIFO_BAR = 0x020110C1ull;
+
+
+static const uint64_t P9N2_PU_SYM_HI_PRIOR_RCV_FIFO_CNTL = 0x020110C4ull;
+
+
+static const uint64_t P9N2_PU_SYM_LO_PRIOR_RCV_FIFO_ASB = 0x020110D0ull;
+
+
+static const uint64_t P9N2_PU_SYM_LO_PRIOR_RCV_FIFO_BAR = 0x020110CAull;
+
+
+static const uint64_t P9N2_PU_SYM_LO_PRIOR_RCV_FIFO_CNTL = 0x020110CDull;
+
+
+static const uint64_t P9N2_PU_SYM_MAX_BYTE_CNT = 0x0201105Aull;
+
+
+static const uint64_t P9N2_PEC_SYNC_CONFIG = 0x0D030000ull;
+
+static const uint64_t P9N2_PEC_0_SYNC_CONFIG = 0x0D030000ull;
+
+static const uint64_t P9N2_PEC_1_SYNC_CONFIG = 0x0E030000ull;
+
+static const uint64_t P9N2_PEC_2_SYNC_CONFIG = 0x0F030000ull;
+
+
+static const uint64_t P9N2_PU_SYNC_FIR_ACTION0_REG = 0x050129C6ull;
+
+
+static const uint64_t P9N2_PU_SYNC_FIR_ACTION1_REG = 0x050129C7ull;
+
+
+static const uint64_t P9N2_PU_SYNC_FIR_MASK_REG = 0x050129C3ull;
+
+static const uint64_t P9N2_PU_SYNC_FIR_MASK_REG_AND = 0x050129C4ull;
+
+static const uint64_t P9N2_PU_SYNC_FIR_MASK_REG_OR = 0x050129C5ull;
+
+
+static const uint64_t P9N2_PU_SYNC_FIR_REG = 0x050129C0ull;
+
+static const uint64_t P9N2_PU_SYNC_FIR_REG_AND = 0x050129C1ull;
+
+static const uint64_t P9N2_PU_SYNC_FIR_REG_OR = 0x050129C2ull;
+
+
+static const uint64_t P9N2_PU_SYNC_FIR_WOF_REG = 0x050129C8ull;
+
+
+static const uint64_t P9N2__SM1_TCE_KILL = 0x05011624ull;
+
+
+static const uint64_t P9N2__SM2_TEST_CERR = 0x05011641ull;
+
+
+static const uint64_t P9N2_CAPP_TFMR = 0x02010827ull;
+
+static const uint64_t P9N2_CAPP_0_TFMR = 0x02010827ull;
+
+static const uint64_t P9N2_CAPP_1_TFMR = 0x04010827ull;
+
+
+static const uint64_t P9N2_PEC_THERM_MODE_REG = 0x0D05000Full;
+
+static const uint64_t P9N2_PEC_0_THERM_MODE_REG = 0x0D05000Full;
+
+static const uint64_t P9N2_PEC_1_THERM_MODE_REG = 0x0E05000Full;
+
+static const uint64_t P9N2_PEC_2_THERM_MODE_REG = 0x0F05000Full;
+
+
+static const uint64_t P9N2_PEC_TIMEOUT_REG = 0x0D0F0010ull;
+
+static const uint64_t P9N2_PEC_0_TIMEOUT_REG = 0x0D0F0010ull;
+
+static const uint64_t P9N2_PEC_1_TIMEOUT_REG = 0x0E0F0010ull;
+
+static const uint64_t P9N2_PEC_2_TIMEOUT_REG = 0x0F0F0010ull;
+
+
+static const uint64_t P9N2_PEC_TIMESTAMP_COUNTER_READ = 0x0D05001Cull;
+
+static const uint64_t P9N2_PEC_0_TIMESTAMP_COUNTER_READ = 0x0D05001Cull;
+
+static const uint64_t P9N2_PEC_1_TIMESTAMP_COUNTER_READ = 0x0E05001Cull;
+
+static const uint64_t P9N2_PEC_2_TIMESTAMP_COUNTER_READ = 0x0F05001Cull;
+
+
+static const uint64_t P9N2_CAPP_TLBI_ERROR_REPORT = 0x0201080Dull;
+
+static const uint64_t P9N2_CAPP_0_TLBI_ERROR_REPORT = 0x0201080Dull;
+
+static const uint64_t P9N2_CAPP_1_TLBI_ERROR_REPORT = 0x0401080Dull;
+
+
+static const uint64_t P9N2_CAPP_TLBI_FILTER_REG0 = 0x02010870ull;
+
+static const uint64_t P9N2_CAPP_0_TLBI_FILTER_REG0 = 0x02010870ull;
+
+static const uint64_t P9N2_CAPP_1_TLBI_FILTER_REG0 = 0x04010870ull;
+
+
+static const uint64_t P9N2_CAPP_TLBI_FILTER_REG1 = 0x02010871ull;
+
+static const uint64_t P9N2_CAPP_0_TLBI_FILTER_REG1 = 0x02010871ull;
+
+static const uint64_t P9N2_CAPP_1_TLBI_FILTER_REG1 = 0x04010871ull;
+
+
+static const uint64_t P9N2_CAPP_TLBI_FILTER_REG10 = 0x0201087Aull;
+
+static const uint64_t P9N2_CAPP_0_TLBI_FILTER_REG10 = 0x0201087Aull;
+
+static const uint64_t P9N2_CAPP_1_TLBI_FILTER_REG10 = 0x0401087Aull;
+
+
+static const uint64_t P9N2_CAPP_TLBI_FILTER_REG11 = 0x0201087Bull;
+
+static const uint64_t P9N2_CAPP_0_TLBI_FILTER_REG11 = 0x0201087Bull;
+
+static const uint64_t P9N2_CAPP_1_TLBI_FILTER_REG11 = 0x0401087Bull;
+
+
+static const uint64_t P9N2_CAPP_TLBI_FILTER_REG12 = 0x0201087Cull;
+
+static const uint64_t P9N2_CAPP_0_TLBI_FILTER_REG12 = 0x0201087Cull;
+
+static const uint64_t P9N2_CAPP_1_TLBI_FILTER_REG12 = 0x0401087Cull;
+
+
+static const uint64_t P9N2_CAPP_TLBI_FILTER_REG13 = 0x0201087Dull;
+
+static const uint64_t P9N2_CAPP_0_TLBI_FILTER_REG13 = 0x0201087Dull;
+
+static const uint64_t P9N2_CAPP_1_TLBI_FILTER_REG13 = 0x0401087Dull;
+
+
+static const uint64_t P9N2_CAPP_TLBI_FILTER_REG14 = 0x0201087Eull;
+
+static const uint64_t P9N2_CAPP_0_TLBI_FILTER_REG14 = 0x0201087Eull;
+
+static const uint64_t P9N2_CAPP_1_TLBI_FILTER_REG14 = 0x0401087Eull;
+
+
+static const uint64_t P9N2_CAPP_TLBI_FILTER_REG15 = 0x0201087Full;
+
+static const uint64_t P9N2_CAPP_0_TLBI_FILTER_REG15 = 0x0201087Full;
+
+static const uint64_t P9N2_CAPP_1_TLBI_FILTER_REG15 = 0x0401087Full;
+
+
+static const uint64_t P9N2_CAPP_TLBI_FILTER_REG2 = 0x02010872ull;
+
+static const uint64_t P9N2_CAPP_0_TLBI_FILTER_REG2 = 0x02010872ull;
+
+static const uint64_t P9N2_CAPP_1_TLBI_FILTER_REG2 = 0x04010872ull;
+
+
+static const uint64_t P9N2_CAPP_TLBI_FILTER_REG3 = 0x02010873ull;
+
+static const uint64_t P9N2_CAPP_0_TLBI_FILTER_REG3 = 0x02010873ull;
+
+static const uint64_t P9N2_CAPP_1_TLBI_FILTER_REG3 = 0x04010873ull;
+
+
+static const uint64_t P9N2_CAPP_TLBI_FILTER_REG4 = 0x02010874ull;
+
+static const uint64_t P9N2_CAPP_0_TLBI_FILTER_REG4 = 0x02010874ull;
+
+static const uint64_t P9N2_CAPP_1_TLBI_FILTER_REG4 = 0x04010874ull;
+
+
+static const uint64_t P9N2_CAPP_TLBI_FILTER_REG5 = 0x02010875ull;
+
+static const uint64_t P9N2_CAPP_0_TLBI_FILTER_REG5 = 0x02010875ull;
+
+static const uint64_t P9N2_CAPP_1_TLBI_FILTER_REG5 = 0x04010875ull;
+
+
+static const uint64_t P9N2_CAPP_TLBI_FILTER_REG6 = 0x02010876ull;
+
+static const uint64_t P9N2_CAPP_0_TLBI_FILTER_REG6 = 0x02010876ull;
+
+static const uint64_t P9N2_CAPP_1_TLBI_FILTER_REG6 = 0x04010876ull;
+
+
+static const uint64_t P9N2_CAPP_TLBI_FILTER_REG7 = 0x02010877ull;
+
+static const uint64_t P9N2_CAPP_0_TLBI_FILTER_REG7 = 0x02010877ull;
+
+static const uint64_t P9N2_CAPP_1_TLBI_FILTER_REG7 = 0x04010877ull;
+
+
+static const uint64_t P9N2_CAPP_TLBI_FILTER_REG8 = 0x02010878ull;
+
+static const uint64_t P9N2_CAPP_0_TLBI_FILTER_REG8 = 0x02010878ull;
+
+static const uint64_t P9N2_CAPP_1_TLBI_FILTER_REG8 = 0x04010878ull;
+
+
+static const uint64_t P9N2_CAPP_TLBI_FILTER_REG9 = 0x02010879ull;
+
+static const uint64_t P9N2_CAPP_0_TLBI_FILTER_REG9 = 0x02010879ull;
+
+static const uint64_t P9N2_CAPP_1_TLBI_FILTER_REG9 = 0x04010879ull;
+
+
+static const uint64_t P9N2_CAPP_TLBI_QOS = 0x0201084Cull;
+
+static const uint64_t P9N2_CAPP_0_TLBI_QOS = 0x0201084Cull;
+
+static const uint64_t P9N2_CAPP_1_TLBI_QOS = 0x0401084Cull;
+
+
+static const uint64_t P9N2_PU_NPU_CTL_TLX_CREDIT_STATUS = 0x05011391ull;
+
+static const uint64_t P9N2_PU_NPU_SM3_TLX_CREDIT_STATUS = 0x05011361ull;
+
+static const uint64_t P9N2__CTL_TLX_CREDIT_STATUS = 0x05011591ull;
+
+static const uint64_t P9N2__SM3_TLX_CREDIT_STATUS = 0x05011561ull;
+
+
+static const uint64_t P9N2_PU_NPU_CTL_TL_DCP_CREDIT_STATUS = 0x05011393ull;
+
+static const uint64_t P9N2_PU_NPU_SM3_TL_DCP_CREDIT_STATUS = 0x05011363ull;
+
+static const uint64_t P9N2__CTL_TL_DCP_CREDIT_STATUS = 0x05011593ull;
+
+static const uint64_t P9N2__SM3_TL_DCP_CREDIT_STATUS = 0x05011563ull;
+
+
+static const uint64_t P9N2_PU_NPU_CTL_TL_VC_CREDIT_STATUS = 0x05011392ull;
+
+static const uint64_t P9N2_PU_NPU_SM3_TL_VC_CREDIT_STATUS = 0x05011362ull;
+
+static const uint64_t P9N2__CTL_TL_VC_CREDIT_STATUS = 0x05011592ull;
+
+static const uint64_t P9N2__SM3_TL_VC_CREDIT_STATUS = 0x05011562ull;
+
+
+static const uint64_t P9N2_PU_TOD_CMD_REG = 0x0009002Aull;
+
+
+static const uint64_t P9N2_PU_TOD_DATA_RCV_REG = 0x00090029ull;
+
+
+static const uint64_t P9N2_PU_TOD_DATA_SND_REG = 0x00090028ull;
+
+
+static const uint64_t P9N2_CAPP_TOD_SYNC000 = 0x02010826ull;
+
+static const uint64_t P9N2_CAPP_0_TOD_SYNC000 = 0x02010826ull;
+
+static const uint64_t P9N2_CAPP_1_TOD_SYNC000 = 0x04010826ull;
+
+
+static const uint64_t P9N2_PU_TRACE_HI_DATA_REG = 0x07010C40ull;
+//DUPS: 02010400, 02010480, 07010C40, 07010C00, 05010440, 05010400, 050104C0, 05010480, 05010540, 05010500, 050105C0, 05010580, 05010600, 050106C0, 05010680, 08010C40, 08010C00, 03010440, 03010400, 030104C0, 03010480, 03010540, 03010500, 030105C0, 03010580, 03010640, 03010600, 04010440, 04010400,
+
+static const uint64_t P9N2_PEC_TRACE_HI_DATA_REG = 0x0D010400ull;
+
+static const uint64_t P9N2_PEC_0_TRACE_HI_DATA_REG = 0x0D010400ull;
+
+static const uint64_t P9N2_PEC_1_TRACE_HI_DATA_REG = 0x0E010400ull;
+
+static const uint64_t P9N2_PEC_2_TRACE_HI_DATA_REG = 0x0F010400ull;
+
+
+static const uint64_t P9N2_PU_TRACE_LO_DATA_REG = 0x07010C41ull;
+//DUPS: 02010401, 02010481, 07010C41, 07010C01, 05010441, 05010401, 050104C1, 05010481, 05010541, 05010501, 050105C1, 05010581, 05010601, 050106C1, 05010681, 08010C41, 08010C01, 03010441, 03010401, 030104C1, 03010481, 03010541, 03010501, 030105C1, 03010581, 03010641, 03010601, 04010441, 04010401,
+
+static const uint64_t P9N2_PEC_TRACE_LO_DATA_REG = 0x0D010401ull;
+
+static const uint64_t P9N2_PEC_0_TRACE_LO_DATA_REG = 0x0D010401ull;
+
+static const uint64_t P9N2_PEC_1_TRACE_LO_DATA_REG = 0x0E010401ull;
+
+static const uint64_t P9N2_PEC_2_TRACE_LO_DATA_REG = 0x0F010401ull;
+
+
+static const uint64_t P9N2_PU_TRACE_TRCTRL_CONFIG = 0x07010C42ull;
+//DUPS: 02010402, 02010482, 07010C42, 07010C02, 05010442, 05010402, 050104C2, 05010482, 05010542, 05010502, 050105C2, 05010582, 05010602, 050106C2, 05010682, 08010C42, 08010C02, 03010442, 03010402, 030104C2, 03010482, 03010542, 03010502, 030105C2, 03010582, 03010642, 03010602, 04010442, 04010402,
+
+static const uint64_t P9N2_PEC_TRACE_TRCTRL_CONFIG = 0x0D010402ull;
+
+static const uint64_t P9N2_PEC_0_TRACE_TRCTRL_CONFIG = 0x0D010402ull;
+
+static const uint64_t P9N2_PEC_1_TRACE_TRCTRL_CONFIG = 0x0E010402ull;
+
+static const uint64_t P9N2_PEC_2_TRACE_TRCTRL_CONFIG = 0x0F010402ull;
+
+
+static const uint64_t P9N2_PU_TRACE_TRDATA_CONFIG_0 = 0x07010C43ull;
+//DUPS: 02010403, 02010483, 07010C43, 07010C03, 05010443, 05010403, 050104C3, 05010483, 05010543, 05010503, 050105C3, 05010583, 05010603, 050106C3, 05010683, 08010C43, 08010C03, 03010443, 03010403, 030104C3, 03010483, 03010543, 03010503, 030105C3, 03010583, 03010643, 03010603, 04010443, 04010403,
+
+static const uint64_t P9N2_PEC_TRACE_TRDATA_CONFIG_0 = 0x0D010403ull;
+
+static const uint64_t P9N2_PEC_0_TRACE_TRDATA_CONFIG_0 = 0x0D010403ull;
+
+static const uint64_t P9N2_PEC_1_TRACE_TRDATA_CONFIG_0 = 0x0E010403ull;
+
+static const uint64_t P9N2_PEC_2_TRACE_TRDATA_CONFIG_0 = 0x0F010403ull;
+
+
+static const uint64_t P9N2_PU_TRACE_TRDATA_CONFIG_1 = 0x07010C44ull;
+//DUPS: 02010404, 02010484, 07010C44, 07010C04, 05010444, 05010404, 050104C4, 05010484, 05010544, 05010504, 050105C4, 05010584, 05010604, 050106C4, 05010684, 08010C44, 08010C04, 03010444, 03010404, 030104C4, 03010484, 03010544, 03010504, 030105C4, 03010584, 03010644, 03010604, 04010444, 04010404,
+
+static const uint64_t P9N2_PEC_TRACE_TRDATA_CONFIG_1 = 0x0D010404ull;
+
+static const uint64_t P9N2_PEC_0_TRACE_TRDATA_CONFIG_1 = 0x0D010404ull;
+
+static const uint64_t P9N2_PEC_1_TRACE_TRDATA_CONFIG_1 = 0x0E010404ull;
+
+static const uint64_t P9N2_PEC_2_TRACE_TRDATA_CONFIG_1 = 0x0F010404ull;
+
+
+static const uint64_t P9N2_PU_TRACE_TRDATA_CONFIG_2 = 0x07010C45ull;
+//DUPS: 02010405, 02010485, 07010C45, 07010C05, 05010445, 05010405, 050104C5, 05010485, 05010545, 05010505, 050105C5, 05010585, 05010605, 050106C5, 05010685, 08010C45, 08010C05, 03010445, 03010405, 030104C5, 03010485, 03010545, 03010505, 030105C5, 03010585, 03010645, 03010605, 04010445, 04010405,
+
+static const uint64_t P9N2_PEC_TRACE_TRDATA_CONFIG_2 = 0x0D010405ull;
+
+static const uint64_t P9N2_PEC_0_TRACE_TRDATA_CONFIG_2 = 0x0D010405ull;
+
+static const uint64_t P9N2_PEC_1_TRACE_TRDATA_CONFIG_2 = 0x0E010405ull;
+
+static const uint64_t P9N2_PEC_2_TRACE_TRDATA_CONFIG_2 = 0x0F010405ull;
+
+
+static const uint64_t P9N2_PU_TRACE_TRDATA_CONFIG_3 = 0x07010C46ull;
+//DUPS: 02010406, 02010486, 07010C46, 07010C06, 05010446, 05010406, 050104C6, 05010486, 05010546, 05010506, 050105C6, 05010586, 05010606, 050106C6, 05010686, 08010C46, 08010C06, 03010446, 03010406, 030104C6, 03010486, 03010546, 03010506, 030105C6, 03010586, 03010646, 03010606, 04010446, 04010406,
+
+static const uint64_t P9N2_PEC_TRACE_TRDATA_CONFIG_3 = 0x0D010406ull;
+
+static const uint64_t P9N2_PEC_0_TRACE_TRDATA_CONFIG_3 = 0x0D010406ull;
+
+static const uint64_t P9N2_PEC_1_TRACE_TRDATA_CONFIG_3 = 0x0E010406ull;
+
+static const uint64_t P9N2_PEC_2_TRACE_TRDATA_CONFIG_3 = 0x0F010406ull;
+
+
+static const uint64_t P9N2_PU_TRACE_TRDATA_CONFIG_4 = 0x07010C47ull;
+//DUPS: 02010407, 02010487, 07010C47, 07010C07, 05010447, 05010407, 050104C7, 05010487, 05010547, 05010507, 050105C7, 05010587, 05010607, 050106C7, 05010687, 08010C47, 08010C07, 03010447, 03010407, 030104C7, 03010487, 03010547, 03010507, 030105C7, 03010587, 03010647, 03010607, 04010447, 04010407,
+
+static const uint64_t P9N2_PEC_TRACE_TRDATA_CONFIG_4 = 0x0D010407ull;
+
+static const uint64_t P9N2_PEC_0_TRACE_TRDATA_CONFIG_4 = 0x0D010407ull;
+
+static const uint64_t P9N2_PEC_1_TRACE_TRDATA_CONFIG_4 = 0x0E010407ull;
+
+static const uint64_t P9N2_PEC_2_TRACE_TRDATA_CONFIG_4 = 0x0F010407ull;
+
+
+static const uint64_t P9N2_PU_TRACE_TRDATA_CONFIG_5 = 0x07010C48ull;
+//DUPS: 02010408, 02010488, 07010C48, 07010C08, 05010448, 05010408, 050104C8, 05010488, 05010548, 05010508, 050105C8, 05010588, 05010608, 050106C8, 05010688, 08010C48, 08010C08, 03010448, 03010408, 030104C8, 03010488, 03010548, 03010508, 030105C8, 03010588, 03010648, 03010608, 04010448, 04010408,
+
+static const uint64_t P9N2_PEC_TRACE_TRDATA_CONFIG_5 = 0x0D010408ull;
+
+static const uint64_t P9N2_PEC_0_TRACE_TRDATA_CONFIG_5 = 0x0D010408ull;
+
+static const uint64_t P9N2_PEC_1_TRACE_TRDATA_CONFIG_5 = 0x0E010408ull;
+
+static const uint64_t P9N2_PEC_2_TRACE_TRDATA_CONFIG_5 = 0x0F010408ull;
+
+
+static const uint64_t P9N2_PU_TRACE_TRDATA_CONFIG_9 = 0x07010C49ull;
+//DUPS: 02010409, 02010489, 07010C49, 07010C09, 05010449, 05010409, 050104C9, 05010489, 05010549, 05010509, 050105C9, 05010589, 05010609, 050106C9, 05010689, 08010C49, 08010C09, 03010449, 03010409, 030104C9, 03010489, 03010549, 03010509, 030105C9, 03010589, 03010649, 03010609, 04010449, 04010409,
+
+static const uint64_t P9N2_PEC_TRACE_TRDATA_CONFIG_9 = 0x0D010409ull;
+
+static const uint64_t P9N2_PEC_0_TRACE_TRDATA_CONFIG_9 = 0x0D010409ull;
+
+static const uint64_t P9N2_PEC_1_TRACE_TRDATA_CONFIG_9 = 0x0E010409ull;
+
+static const uint64_t P9N2_PEC_2_TRACE_TRDATA_CONFIG_9 = 0x0F010409ull;
+
+
+static const uint64_t P9N2_PU_TRUST_CONTROL = 0x05012B45ull;
+
+
+static const uint64_t P9N2_PEC_0_STACK0_TUNNEL_BAR_REG = 0x04010C56ull;
+
+static const uint64_t P9N2_PEC_1_STACK0_TUNNEL_BAR_REG = 0x04011056ull;
+
+static const uint64_t P9N2_PEC_1_STACK1_TUNNEL_BAR_REG = 0x04011096ull;
+
+static const uint64_t P9N2_PEC_1_STACK2_TUNNEL_BAR_REG = 0x040110D6ull;
+
+static const uint64_t P9N2_PEC_2_STACK0_TUNNEL_BAR_REG = 0x04011456ull;
+
+static const uint64_t P9N2_PEC_2_STACK1_TUNNEL_BAR_REG = 0x04011496ull;
+
+static const uint64_t P9N2_PEC_2_STACK2_TUNNEL_BAR_REG = 0x040114D6ull;
+
+static const uint64_t P9N2_PEC_STACK0_TUNNEL_BAR_REG = 0x04010C56ull;
+
+static const uint64_t P9N2_PHB_TUNNEL_BAR_REG = 0x04010C56ull;
+
+static const uint64_t P9N2_PHB_0_TUNNEL_BAR_REG = 0x04010C56ull;
+
+static const uint64_t P9N2_PHB_1_TUNNEL_BAR_REG = 0x04011056ull;
+
+static const uint64_t P9N2_PHB_2_TUNNEL_BAR_REG = 0x04011096ull;
+
+static const uint64_t P9N2_PHB_3_TUNNEL_BAR_REG = 0x04011456ull;
+
+static const uint64_t P9N2_PHB_4_TUNNEL_BAR_REG = 0x04011496ull;
+
+static const uint64_t P9N2_PHB_5_TUNNEL_BAR_REG = 0x040114D6ull;
+
+
+static const uint64_t P9N2_PU_NPU_CTL_TXI_ERR_INJ = 0x05011395ull;
+
+static const uint64_t P9N2_PU_NPU_SM3_TXI_ERR_INJ = 0x05011365ull;
+
+static const uint64_t P9N2__CTL_TXI_ERR_INJ = 0x05011595ull;
+
+static const uint64_t P9N2__SM3_TXI_ERR_INJ = 0x05011565ull;
+
+
+static const uint64_t P9N2_PU_TX_CH_FSM_REG = 0x05012805ull;
+
+
+static const uint64_t P9N2_PU_TX_CH_INTADDR_REG = 0x05012810ull;
+
+
+static const uint64_t P9N2_PU_TX_CH_MISC_REG = 0x05012813ull;
+
+
+static const uint64_t P9N2_PU_TX_CTRL_STAT_REG = 0x05012800ull;
+
+
+static const uint64_t P9N2_PU_TX_DBFF_REG0 = 0x05012811ull;
+
+
+static const uint64_t P9N2_PU_TX_DBFF_REG1 = 0x05012812ull;
+
+
+static const uint64_t P9N2_PU_TX_DF_FSM_REG = 0x05012806ull;
+
+
+static const uint64_t P9N2_PU_NPU_CTL_TX_DL_CREDIT_STATUS = 0x05011394ull;
+
+static const uint64_t P9N2_PU_NPU_SM3_TX_DL_CREDIT_STATUS = 0x05011364ull;
+
+static const uint64_t P9N2__CTL_TX_DL_CREDIT_STATUS = 0x05011594ull;
+
+static const uint64_t P9N2__SM3_TX_DL_CREDIT_STATUS = 0x05011564ull;
+
+
+static const uint64_t P9N2_PU_TX_ERROR_REG_WCLEAR = 0x05012802ull;
+
+static const uint64_t P9N2_PU_TX_ERROR_REG_OR = 0x05012804ull;
+
+
+static const uint64_t P9N2_PU_TX_ERR_MODE = 0x05012807ull;
+
+
+static const uint64_t P9N2_PU_TX_MASK_REG = 0x05012803ull;
+
+
+static const uint64_t P9N2_PU_TX_PSI_CNTL = 0x04011830ull;
+
+
+static const uint64_t P9N2_PU_TX_PSI_MODE = 0x04011831ull;
+
+
+static const uint64_t P9N2_PU_TX_PSI_STATUS = 0x04011832ull;
+
+
+static const uint64_t P9N2_PU_TX_TO_RT_REG = 0x05012801ull;
+
+
+static const uint64_t P9N2_PU_UMAC_STATUS_CONTROL = 0x020110D5ull;
+
+
+static const uint64_t P9N2_PU_VAS_BUFCTL = 0x0301180Cull;
+
+
+static const uint64_t P9N2_PU_VAS_CAMDATA0 = 0x03011834ull;
+
+
+static const uint64_t P9N2_PU_VAS_CAMDATA1 = 0x03011835ull;
+
+
+static const uint64_t P9N2_PU_VAS_CAMDISPCNTL = 0x03011833ull;
+
+
+static const uint64_t P9N2_PU_VAS_CQERRRPT = 0x03011848ull;
+
+
+static const uint64_t P9N2_PU_VAS_DBGCONT = 0x0301182Eull;
+
+
+static const uint64_t P9N2_PU_VAS_DBGNORTH = 0x0301182Dull;
+
+
+static const uint64_t P9N2_PU_VAS_DBGSOUTH = 0x0301184Cull;
+
+
+static const uint64_t P9N2_PU_VAS_DBGTRIG = 0x0301182Full;
+
+
+static const uint64_t P9N2_PU_VAS_EGERRRPT = 0x0301184Aull;
+
+
+static const uint64_t P9N2_PU_VAS_ERRINJNO = 0x03011832ull;
+
+
+static const uint64_t P9N2_PU_VAS_ERRINJSO = 0x0301184Bull;
+
+
+static const uint64_t P9N2_PU_VAS_FIR_ACTION0_REG = 0x03011806ull;
+
+
+static const uint64_t P9N2_PU_VAS_FIR_ACTION1_REG = 0x03011807ull;
+
+
+static const uint64_t P9N2_PU_VAS_FIR_MASK_REG = 0x03011803ull;
+
+static const uint64_t P9N2_PU_VAS_FIR_MASK_REG_AND = 0x03011804ull;
+
+static const uint64_t P9N2_PU_VAS_FIR_MASK_REG_OR = 0x03011805ull;
+
+
+static const uint64_t P9N2_PU_VAS_FIR_REG = 0x03011800ull;
+
+static const uint64_t P9N2_PU_VAS_FIR_REG_AND = 0x03011801ull;
+
+static const uint64_t P9N2_PU_VAS_FIR_REG_OR = 0x03011802ull;
+
+
+static const uint64_t P9N2_PU_VAS_FIR_WOF_REG = 0x03011808ull;
+
+
+static const uint64_t P9N2_PU_VAS_INERRRPT = 0x0301182Bull;
+
+
+static const uint64_t P9N2_PU_VAS_MISCCTL = 0x0301180Dull;
+
+
+static const uint64_t P9N2_PU_VAS_MMIOCTL = 0x03011829ull;
+
+
+static const uint64_t P9N2_PU_VAS_MMIODATA = 0x0301182Aull;
+
+
+static const uint64_t P9N2_PU_VAS_MMIOECC = 0x03011831ull;
+
+
+static const uint64_t P9N2_PU_VAS_MMIO_BASE_ADDR = 0x020110D4ull;
+
+
+static const uint64_t P9N2_PU_VAS_PBCFG0 = 0x0301184Dull;
+
+
+static const uint64_t P9N2_PU_VAS_PBCFG1 = 0x0301184Eull;
+
+
+static const uint64_t P9N2_PU_VAS_PGMIG1 = 0x03011841ull;
+
+
+static const uint64_t P9N2_PU_VAS_PGMIG2 = 0x03011842ull;
+
+
+static const uint64_t P9N2_PU_VAS_PGMIG3 = 0x03011843ull;
+
+
+static const uint64_t P9N2_PU_VAS_PGMIG4 = 0x03011844ull;
+
+
+static const uint64_t P9N2_PU_VAS_PGMIG5 = 0x03011845ull;
+
+
+static const uint64_t P9N2_PU_VAS_PGMIG6 = 0x03011846ull;
+
+
+static const uint64_t P9N2_PU_VAS_PGMIG7 = 0x03011847ull;
+
+
+static const uint64_t P9N2_PU_VAS_PMCNTL = 0x03011830ull;
+
+
+static const uint64_t P9N2_PU_VAS_RESERVE = 0x03011828ull;
+
+
+static const uint64_t P9N2_PU_VAS_RGERRRPT = 0x0301182Cull;
+
+
+static const uint64_t P9N2_PU_VAS_RMABAR = 0x0301180Eull;
+
+
+static const uint64_t P9N2_PU_VAS_RMABARM = 0x0301180Full;
+
+
+static const uint64_t P9N2_PU_VAS_SOUTHCTL = 0x0301184Full;
+
+
+static const uint64_t P9N2_PU_VAS_UWMBAR = 0x0301180Bull;
+
+
+static const uint64_t P9N2_PU_VAS_WCBSBAR = 0x03011840ull;
+
+
+static const uint64_t P9N2_PU_VAS_WCERRRPT = 0x03011849ull;
+
+
+static const uint64_t P9N2_PU_VAS_WCMBAR = 0x0301180Aull;
+
+
+static const uint64_t P9N2_PU_VAS_WRMON0BAR = 0x03011810ull;
+
+
+static const uint64_t P9N2_PU_VAS_WRMON0CMP = 0x03011820ull;
+
+
+static const uint64_t P9N2_PU_VAS_WRMON0WID = 0x03011818ull;
+
+
+static const uint64_t P9N2_PU_VAS_WRMON1BAR = 0x03011811ull;
+
+
+static const uint64_t P9N2_PU_VAS_WRMON1CMP = 0x03011821ull;
+
+
+static const uint64_t P9N2_PU_VAS_WRMON1WID = 0x03011819ull;
+
+
+static const uint64_t P9N2_PU_VAS_WRMON2BAR = 0x03011812ull;
+
+
+static const uint64_t P9N2_PU_VAS_WRMON2CMP = 0x03011822ull;
+
+
+static const uint64_t P9N2_PU_VAS_WRMON2WID = 0x0301181Aull;
+
+
+static const uint64_t P9N2_PU_VAS_WRMON3BAR = 0x03011813ull;
+
+
+static const uint64_t P9N2_PU_VAS_WRMON3CMP = 0x03011823ull;
+
+
+static const uint64_t P9N2_PU_VAS_WRMON3WID = 0x0301181Bull;
+
+
+static const uint64_t P9N2_PU_VAS_WRMON4BAR = 0x03011814ull;
+
+
+static const uint64_t P9N2_PU_VAS_WRMON4CMP = 0x03011824ull;
+
+
+static const uint64_t P9N2_PU_VAS_WRMON4WID = 0x0301181Cull;
+
+
+static const uint64_t P9N2_PU_VAS_WRMON5BAR = 0x03011815ull;
+
+
+static const uint64_t P9N2_PU_VAS_WRMON5CMP = 0x03011825ull;
+
+
+static const uint64_t P9N2_PU_VAS_WRMON5WID = 0x0301181Dull;
+
+
+static const uint64_t P9N2_PU_VAS_WRMON6BAR = 0x03011816ull;
+
+
+static const uint64_t P9N2_PU_VAS_WRMON6CMP = 0x03011826ull;
+
+
+static const uint64_t P9N2_PU_VAS_WRMON6WID = 0x0301181Eull;
+
+
+static const uint64_t P9N2_PU_VAS_WRMON7BAR = 0x03011817ull;
+
+
+static const uint64_t P9N2_PU_VAS_WRMON7CMP = 0x03011827ull;
+
+
+static const uint64_t P9N2_PU_VAS_WRMON7WID = 0x0301181Full;
+
+
+static const uint64_t P9N2_PEC_VITAL_SCAN_OUT = 0x0D0F0017ull;
+
+static const uint64_t P9N2_PEC_0_VITAL_SCAN_OUT = 0x0D0F0017ull;
+
+static const uint64_t P9N2_PEC_1_VITAL_SCAN_OUT = 0x0E0F0017ull;
+
+static const uint64_t P9N2_PEC_2_VITAL_SCAN_OUT = 0x0F0F0017ull;
+
+
+static const uint64_t P9N2_PU_WATCHDOG_HANG_TIMERS_CNTL = 0x0201105Cull;
+
+
+static const uint64_t P9N2_PU_WATER_MARK_REGISTER_B = 0x000A0007ull;
+
+
+static const uint64_t P9N2_PU_WATER_MARK_REGISTER_C = 0x000A1007ull;
+
+
+static const uint64_t P9N2_PU_WATER_MARK_REGISTER_D = 0x000A2007ull;
+
+
+static const uint64_t P9N2_PU_WATER_MARK_REGISTER_E = 0x000A3007ull;
+
+
+static const uint64_t P9N2_PHB_WOF_REG = 0x0D010910ull;
+
+static const uint64_t P9N2_PHB_0_WOF_REG = 0x0D010910ull;
+
+static const uint64_t P9N2_PHB_1_WOF_REG = 0x0E010910ull;
+
+static const uint64_t P9N2_PHB_2_WOF_REG = 0x0E010950ull;
+
+static const uint64_t P9N2_PHB_3_WOF_REG = 0x0F010910ull;
+
+static const uint64_t P9N2_PHB_4_WOF_REG = 0x0F010950ull;
+
+static const uint64_t P9N2_PHB_5_WOF_REG = 0x0F010990ull;
+
+
+static const uint64_t P9N2_PU_WRITE_PROTECT_ENABLE_REG = 0x06010005ull;
+
+
+static const uint64_t P9N2_PEC_WRITE_PROTECT_ENABLE_REG = 0x0D010005ull;
+
+static const uint64_t P9N2_PEC_0_WRITE_PROTECT_ENABLE_REG = 0x0D010005ull;
+
+static const uint64_t P9N2_PEC_1_WRITE_PROTECT_ENABLE_REG = 0x0E010005ull;
+
+static const uint64_t P9N2_PEC_2_WRITE_PROTECT_ENABLE_REG = 0x0F010005ull;
+
+
+static const uint64_t P9N2_PU_N0_WRITE_PROTECT_ENABLE_REG = 0x02010005ull;
+
+static const uint64_t P9N2_PU_N1_WRITE_PROTECT_ENABLE_REG = 0x03010005ull;
+
+static const uint64_t P9N2_PU_N2_WRITE_PROTECT_ENABLE_REG = 0x04010005ull;
+
+static const uint64_t P9N2_PU_N3_WRITE_PROTECT_ENABLE_REG = 0x05010005ull;
+
+
+static const uint64_t P9N2_PU_WRITE_PROTECT_RINGS_REG = 0x06010006ull;
+
+
+static const uint64_t P9N2_PEC_WRITE_PROTECT_RINGS_REG = 0x0D010006ull;
+
+static const uint64_t P9N2_PEC_0_WRITE_PROTECT_RINGS_REG = 0x0D010006ull;
+
+static const uint64_t P9N2_PEC_1_WRITE_PROTECT_RINGS_REG = 0x0E010006ull;
+
+static const uint64_t P9N2_PEC_2_WRITE_PROTECT_RINGS_REG = 0x0F010006ull;
+
+
+static const uint64_t P9N2_PU_N0_WRITE_PROTECT_RINGS_REG = 0x02010006ull;
+
+static const uint64_t P9N2_PU_N1_WRITE_PROTECT_RINGS_REG = 0x03010006ull;
+
+static const uint64_t P9N2_PU_N2_WRITE_PROTECT_RINGS_REG = 0x04010006ull;
+
+static const uint64_t P9N2_PU_N3_WRITE_PROTECT_RINGS_REG = 0x05010006ull;
+
+
+static const uint64_t P9N2_PEC_XFIR = 0x0D040000ull;
+
+static const uint64_t P9N2_PEC_0_XFIR = 0x0D040000ull;
+
+static const uint64_t P9N2_PEC_1_XFIR = 0x0E040000ull;
+
+static const uint64_t P9N2_PEC_2_XFIR = 0x0F040000ull;
+
+
+static const uint64_t P9N2_CAPP_XPT_CONTROL = 0x0201081Cull;
+
+static const uint64_t P9N2_CAPP_0_XPT_CONTROL = 0x0201081Cull;
+
+static const uint64_t P9N2_CAPP_1_XPT_CONTROL = 0x0401081Cull;
+
+
+static const uint64_t P9N2_CAPP_XPT_ERROR_REPORT = 0x0201080Cull;
+
+static const uint64_t P9N2_CAPP_0_XPT_ERROR_REPORT = 0x0201080Cull;
+
+static const uint64_t P9N2_CAPP_1_XPT_ERROR_REPORT = 0x0401080Cull;
+
+
+static const uint64_t P9N2_CAPP_XPT_PMU_EVENTS_SEL = 0x02010822ull;
+
+static const uint64_t P9N2_CAPP_0_XPT_PMU_EVENTS_SEL = 0x02010822ull;
+
+static const uint64_t P9N2_CAPP_1_XPT_PMU_EVENTS_SEL = 0x04010822ull;
+
+
+static const uint64_t P9N2_PU_XSCOM_BASE_REG = 0x00090010ull;
+
+
+static const uint64_t P9N2_PU_XSCOM_DAT0_REG = 0x0009001Eull;
+
+
+static const uint64_t P9N2_PU_XSCOM_DAT1_REG = 0x0009001Full;
+
+
+static const uint64_t P9N2_PU_XSCOM_ERR_REG = 0x00090013ull;
+
+
+static const uint64_t P9N2_PU_XSCOM_LOG_REG = 0x00090012ull;
+
+
+static const uint64_t P9N2_PU_XSCOM_MODE_REG = 0x00090011ull;
+
+
+static const uint64_t P9N2_PU_XSCOM_RCVED_STAT_REG = 0x00090018ull;
+
+
+static const uint64_t P9N2_PU_NPU_DAT_XSL_ATD = 0x050113BAull;
+
+static const uint64_t P9N2__DAT_XSL_ATD = 0x050115BAull;
+
+
+static const uint64_t P9N2_PU_NPU_DAT_XSL_DBG_WR = 0x050113B6ull;
+
+static const uint64_t P9N2__DAT_XSL_DBG_WR = 0x050115B6ull;
+
+
+static const uint64_t P9N2_PU_NPU_NTL0_XSL_DEBUG0_CONFIG = 0x050113C4ull;
+
+static const uint64_t P9N2__NTL0_XSL_DEBUG0_CONFIG = 0x050115C4ull;
+
+
+static const uint64_t P9N2_PU_NPU_NTL0_XSL_DEBUG1_CONFIG = 0x050113C5ull;
+
+static const uint64_t P9N2__NTL0_XSL_DEBUG1_CONFIG = 0x050115C5ull;
+
+
+static const uint64_t P9N2_PU_NPU_DAT_XSL_DEF = 0x050113B8ull;
+
+static const uint64_t P9N2__DAT_XSL_DEF = 0x050115B8ull;
+
+
+static const uint64_t P9N2_PU_NPU_DAT_XSL_EEI = 0x050113B7ull;
+
+static const uint64_t P9N2__DAT_XSL_EEI = 0x050115B7ull;
+
+
+static const uint64_t P9N2_PU_NPU_DAT_XSL_FEC = 0x050113B9ull;
+
+static const uint64_t P9N2__DAT_XSL_FEC = 0x050115B9ull;
+
+
+static const uint64_t P9N2_PU_NPU_DAT_XSL_GP = 0x050113BBull;
+
+static const uint64_t P9N2__DAT_XSL_GP = 0x050115BBull;
+
+
+static const uint64_t P9N2_PU_NPU_DAT_XSL_INV_ERAT_WR = 0x050113BCull;
+
+static const uint64_t P9N2__DAT_XSL_INV_ERAT_WR = 0x050115BCull;
+
+
+static const uint64_t P9N2_PU_NPU_DAT_XSL_INV_LPP = 0x050113BDull;
+
+static const uint64_t P9N2__DAT_XSL_INV_LPP = 0x050115BDull;
+
+
+static const uint64_t P9N2_PU_NPU_DAT_XSL_PMON = 0x050113B5ull;
+
+static const uint64_t P9N2__DAT_XSL_PMON = 0x050115B5ull;
+
+
+static const uint64_t P9N2_PU_NPU_DAT_XSL_RECOVER = 0x050113B4ull;
+
+static const uint64_t P9N2__DAT_XSL_RECOVER = 0x050115B4ull;
+
+
+static const uint64_t P9N2_PU_NPU_NTL0_XSL_WRAP_CFG = 0x050113C8ull;
+
+static const uint64_t P9N2__NTL0_XSL_WRAP_CFG = 0x050115C8ull;
+
+
+static const uint64_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR = 0x050113C6ull;
+
+static const uint64_t P9N2__NTL0_XSL_WRAP_ERROR = 0x050115C6ull;
+
+
+static const uint64_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERR_MASK = 0x050113C7ull;
+
+static const uint64_t P9N2__NTL0_XSL_WRAP_ERR_MASK = 0x050115C7ull;
+
+
+static const uint64_t P9N2_PEC_XSTOP1 = 0x0D03000Cull;
+
+static const uint64_t P9N2_PEC_0_XSTOP1 = 0x0D03000Cull;
+
+static const uint64_t P9N2_PEC_1_XSTOP1 = 0x0E03000Cull;
+
+static const uint64_t P9N2_PEC_2_XSTOP1 = 0x0F03000Cull;
+
+
+static const uint64_t P9N2_PEC_XSTOP2 = 0x0D03000Dull;
+
+static const uint64_t P9N2_PEC_0_XSTOP2 = 0x0D03000Dull;
+
+static const uint64_t P9N2_PEC_1_XSTOP2 = 0x0E03000Dull;
+
+static const uint64_t P9N2_PEC_2_XSTOP2 = 0x0F03000Dull;
+
+
+static const uint64_t P9N2_PEC_XSTOP3 = 0x0D03000Eull;
+
+static const uint64_t P9N2_PEC_0_XSTOP3 = 0x0D03000Eull;
+
+static const uint64_t P9N2_PEC_1_XSTOP3 = 0x0E03000Eull;
+
+static const uint64_t P9N2_PEC_2_XSTOP3 = 0x0F03000Eull;
+
+
+static const uint64_t P9N2_PEC_XSTOP_INTERRUPT_REG = 0x0D0F001Cull;
+
+static const uint64_t P9N2_PEC_0_XSTOP_INTERRUPT_REG = 0x0D0F001Cull;
+
+static const uint64_t P9N2_PEC_1_XSTOP_INTERRUPT_REG = 0x0E0F001Cull;
+
+static const uint64_t P9N2_PEC_2_XSTOP_INTERRUPT_REG = 0x0F0F001Cull;
+
+
+static const uint64_t P9N2_PU_NPU0_CTL_XTIMER_CONFIG = 0x05011093ull;
+
+static const uint64_t P9N2_PU_NPU2_CTL_XTIMER_CONFIG = 0x05011293ull;
+
+static const uint64_t P9N2_PU_NPU0_SM0_XTIMER_CONFIG = 0x05011003ull;
+
+static const uint64_t P9N2_PU_NPU0_SM1_XTIMER_CONFIG = 0x05011033ull;
+
+static const uint64_t P9N2_PU_NPU0_SM3_XTIMER_CONFIG = 0x05011063ull;
+
+static const uint64_t P9N2_PU_NPU2_SM0_XTIMER_CONFIG = 0x05011203ull;
+
+static const uint64_t P9N2_PU_NPU2_SM1_XTIMER_CONFIG = 0x05011233ull;
+
+static const uint64_t P9N2_PU_NPU2_SM3_XTIMER_CONFIG = 0x05011263ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_CTL_XTIMER_CONFIG = 0x05011493ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM0_XTIMER_CONFIG = 0x05011403ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM1_XTIMER_CONFIG = 0x05011433ull;
+
+static const uint64_t P9N2_PU_NPU_MSC_SM3_XTIMER_CONFIG = 0x05011463ull;
+
+
+static const uint64_t P9N2_PU_XTRA_TRACE_MODE = 0x020107D1ull;
+//DUPS: 050107D1, 030107D1, 040107D1,
+
+static const uint64_t P9N2_PEC_XTRA_TRACE_MODE = 0x0D0107D1ull;
+
+static const uint64_t P9N2_PEC_0_XTRA_TRACE_MODE = 0x0D0107D1ull;
+
+static const uint64_t P9N2_PEC_1_XTRA_TRACE_MODE = 0x0E0107D1ull;
+
+static const uint64_t P9N2_PEC_2_XTRA_TRACE_MODE = 0x0F0107D1ull;
+
+
+static const uint64_t P9N2__SM2_XTS_ATRMISS = 0x0501164Aull;
+
+
+static const uint64_t P9N2__SM2_XTS_ATRMISS2 = 0x0501164Cull;
+
+
+static const uint64_t P9N2__SM2_XTS_ATRMISSCLR = 0x0501164Bull;
+
+
+static const uint64_t P9N2__SM3_XTS_ATSD_HYP0 = 0x05011660ull;
+
+
+static const uint64_t P9N2__SM3_XTS_ATSD_HYP1 = 0x05011661ull;
+
+
+static const uint64_t P9N2__SM3_XTS_ATSD_HYP2 = 0x05011662ull;
+
+
+static const uint64_t P9N2__SM3_XTS_ATSD_HYP3 = 0x05011663ull;
+
+
+static const uint64_t P9N2__SM3_XTS_ATSD_HYP4 = 0x05011664ull;
+
+
+static const uint64_t P9N2__SM3_XTS_ATSD_HYP5 = 0x05011665ull;
+
+
+static const uint64_t P9N2__SM3_XTS_ATSD_HYP6 = 0x05011666ull;
+
+
+static const uint64_t P9N2__SM3_XTS_ATSD_HYP7 = 0x05011667ull;
+
+
+static const uint64_t P9N2__SM2_XTS_CONFIG = 0x05011644ull;
+
+
+static const uint64_t P9N2__SM2_XTS_CONFIG2 = 0x05011645ull;
+
+
+static const uint64_t P9N2__SM2_XTS_CONFIG3 = 0x0501164Dull;
+
+
+static const uint64_t P9N2__SM2_XTS_PMU_CNT = 0x05011648ull;
+
+#endif
+
diff --git a/src/import/chips/p9/common/include/p9n2_misc_scom_addresses_fld.H b/src/import/chips/p9/common/include/p9n2_misc_scom_addresses_fld.H
new file mode 100644
index 000000000..09ed4f5e0
--- /dev/null
+++ b/src/import/chips/p9/common/include/p9n2_misc_scom_addresses_fld.H
@@ -0,0 +1,50340 @@
+/* IBM_PROLOG_BEGIN_TAG */
+/* This is an automatically generated prolog. */
+/* */
+/* $Source: src/import/chips/p9/common/include/p9n2_misc_scom_addresses_fld.H $ */
+/* */
+/* OpenPOWER HostBoot Project */
+/* */
+/* Contributors Listed Below - COPYRIGHT 2017 */
+/* [+] International Business Machines Corp. */
+/* */
+/* */
+/* Licensed under the Apache License, Version 2.0 (the "License"); */
+/* you may not use this file except in compliance with the License. */
+/* You may obtain a copy of the License at */
+/* */
+/* http://www.apache.org/licenses/LICENSE-2.0 */
+/* */
+/* Unless required by applicable law or agreed to in writing, software */
+/* distributed under the License is distributed on an "AS IS" BASIS, */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */
+/* implied. See the License for the specific language governing */
+/* permissions and limitations under the License. */
+/* */
+/* IBM_PROLOG_END_TAG */
+///
+/// @file p9_misc_scom_addresses_fld.H
+/// @brief Defines constants for scom addresses
+///
+// *HWP HWP Owner: Ben Gass <bgass@us.ibm.com>
+// *HWP FW Owner: Thi Tran <thi@us.ibm.com>
+// *HWP Team: SOA
+// *HWP Level: 1
+// *HWP Consumed by: FSP:HB:HS:OCC:SBE:CME:SGPE:PGPE:FPPE:IPPE
+
+#ifndef __P9N2_MISC_SCOM_ADDRESSES_FLD_H
+#define __P9N2_MISC_SCOM_ADDRESSES_FLD_H
+
+#include <stdint.h>
+
+static const uint8_t P9N2_PHB_ACT0_REG_AIB_COMMAND_INVALID = 0 ;
+static const uint8_t P9N2_PHB_ACT0_REG_AIB_ADDRESSING_ERROR = 1 ;
+static const uint8_t P9N2_PHB_ACT0_REG_AIB_ACCESS_ERROR = 2 ;
+static const uint8_t P9N2_PHB_ACT0_REG_PAPR_OUTBOUND_INJECTION_ERROR_TRIGGERED = 3 ;
+static const uint8_t P9N2_PHB_ACT0_REG_AIB_FATAL_CLASS_ERROR = 4 ;
+static const uint8_t P9N2_PHB_ACT0_REG_AIB_INF_CLASS_ERROR = 5 ;
+static const uint8_t P9N2_PHB_ACT0_REG_PE_STOP_STATE_ERROR = 6 ;
+static const uint8_t P9N2_PHB_ACT0_REG_AIB_DAT_ERR_SIGNALED = 7 ;
+static const uint8_t P9N2_PHB_ACT0_REG_OUT_COMMON_ARRAY_FATAL_ERROR = 8 ;
+static const uint8_t P9N2_PHB_ACT0_REG_OUT_COMMON_LATCH_FATAL_ERROR = 9 ;
+static const uint8_t P9N2_PHB_ACT0_REG_OUT_COMMON_LOGIC_FATAL_ERROR = 10 ;
+static const uint8_t P9N2_PHB_ACT0_REG_BLIF_OUT_INTERFACE_PARITY_ERROR = 11 ;
+static const uint8_t P9N2_PHB_ACT0_REG_PCIE_CFG_WRITE_CA_OR_UR_RESPONSE = 12 ;
+static const uint8_t P9N2_PHB_ACT0_REG_MMIO_REQUEST_TIMEOUT = 13 ;
+static const uint8_t P9N2_PHB_ACT0_REG_OUT_RRB_SOURCED_ERROR = 14 ;
+static const uint8_t P9N2_PHB_ACT0_REG_CFG_LOGIC_SIGNALED_ERROR = 15 ;
+static const uint8_t P9N2_PHB_ACT0_REG_RSB_REG_REQUEST_ADDRESS_ERROR = 16 ;
+static const uint8_t P9N2_PHB_ACT0_REG_RSB_FDA_FATAL_ERROR = 17 ;
+static const uint8_t P9N2_PHB_ACT0_REG_RSB_FDA_INF_ERROR = 18 ;
+static const uint8_t P9N2_PHB_ACT0_REG_RSB_FDB_FATAL_ERROR = 19 ;
+static const uint8_t P9N2_PHB_ACT0_REG_RSB_FDB_INF_ERROR = 20 ;
+static const uint8_t P9N2_PHB_ACT0_REG_RSB_ERR_FATAL_ERROR = 21 ;
+static const uint8_t P9N2_PHB_ACT0_REG_RSB_ERR_INF_ERROR = 22 ;
+static const uint8_t P9N2_PHB_ACT0_REG_RSB_DBG_FATAL_ERROR = 23 ;
+static const uint8_t P9N2_PHB_ACT0_REG_RSB_DBG_INF_ERROR = 24 ;
+static const uint8_t P9N2_PHB_ACT0_REG_RSB_PCIE_REQUEST_ACCESS_ERROR = 25 ;
+static const uint8_t P9N2_PHB_ACT0_REG_RSB_BUS_LOGIC_ERROR = 26 ;
+static const uint8_t P9N2_PHB_ACT0_REG_RSB_UVI_FATAL_ERROR = 27 ;
+static const uint8_t P9N2_PHB_ACT0_REG_RSB_UVI_INF_ERROR = 28 ;
+static const uint8_t P9N2_PHB_ACT0_REG_SCOM_FATAL_ERROR = 29 ;
+static const uint8_t P9N2_PHB_ACT0_REG_SCOM_INF_ERROR = 30 ;
+static const uint8_t P9N2_PHB_ACT0_REG_PCIE_MACRO_ERROR_ACTIVE_STATUS = 31 ;
+static const uint8_t P9N2_PHB_ACT0_REG_ARB_IODA_FATAL_ERROR = 32 ;
+static const uint8_t P9N2_PHB_ACT0_REG_ARB_MSI_PE_MATCH_ERROR = 33 ;
+static const uint8_t P9N2_PHB_ACT0_REG_ARB_MSI_ADDRESS_ERROR = 34 ;
+static const uint8_t P9N2_PHB_ACT0_REG_ARB_TVT_ERROR = 35 ;
+static const uint8_t P9N2_PHB_ACT0_REG_ARB_RCVD_FATAL_ERROR_MSG = 36 ;
+static const uint8_t P9N2_PHB_ACT0_REG_ARB_RCVD_NONFATAL_ERROR_MSG = 37 ;
+static const uint8_t P9N2_PHB_ACT0_REG_ARB_RCVD_CORRECTIBLE_ERROR_MSG = 38 ;
+static const uint8_t P9N2_PHB_ACT0_REG_PAPR_INBOUND_INJECTION_ERROR_TRIGGERED = 39 ;
+static const uint8_t P9N2_PHB_ACT0_REG_ARB_COMMON_FATAL_ERROR = 40 ;
+static const uint8_t P9N2_PHB_ACT0_REG_ARB_TABLE_BAR_DISABLED_ERROR = 41 ;
+static const uint8_t P9N2_PHB_ACT0_REG_ARB_BLIF_COMPLETION_ERROR = 42 ;
+static const uint8_t P9N2_PHB_ACT0_REG_ARB_PCT_TIMEOUT_ERROR = 43 ;
+static const uint8_t P9N2_PHB_ACT0_REG_ARB_ECC_CORRECTABLE_ERROR = 44 ;
+static const uint8_t P9N2_PHB_ACT0_REG_ARB_ECC_UNCORRECTABLE_ERROR = 45 ;
+static const uint8_t P9N2_PHB_ACT0_REG_ARB_TLP_POISON_SIGNALED = 46 ;
+static const uint8_t P9N2_PHB_ACT0_REG_ARB_RTT_PENUM_INVALID_ERROR = 47 ;
+static const uint8_t P9N2_PHB_ACT0_REG_MRG_COMMON_FATAL_ERROR = 48 ;
+static const uint8_t P9N2_PHB_ACT0_REG_MRG_TABLE_BAR_DISABLED_ERROR = 49 ;
+static const uint8_t P9N2_PHB_ACT0_REG_MRG_ECC_CORRECTABLE_ERROR = 50 ;
+static const uint8_t P9N2_PHB_ACT0_REG_MRG_ECC_UNCORRECTABLE_ERROR = 51 ;
+static const uint8_t P9N2_PHB_ACT0_REG_MRG_AIB2_TX_TIMEOUT_ERROR = 52 ;
+static const uint8_t P9N2_PHB_ACT0_REG_MRG_MRT_ERROR = 53 ;
+static const uint8_t P9N2_PHB_ACT0_REG_MRG_RESERVED01 = 54 ;
+static const uint8_t P9N2_PHB_ACT0_REG_MRG_RESERVED02 = 55 ;
+static const uint8_t P9N2_PHB_ACT0_REG_TCE_IODA_PAGE_ACCESS_ERROR = 56 ;
+static const uint8_t P9N2_PHB_ACT0_REG_TCE_REQUEST_TIMEOUT_ERROR = 57 ;
+static const uint8_t P9N2_PHB_ACT0_REG_TCE_UNEXPECTED_RESPONSE_ERROR = 58 ;
+static const uint8_t P9N2_PHB_ACT0_REG_TCE_COMMON_FATAL_ERRORS = 59 ;
+static const uint8_t P9N2_PHB_ACT0_REG_TCE_ECC_CORRECTABLE_ERROR = 60 ;
+static const uint8_t P9N2_PHB_ACT0_REG_TCE_ECC_UNCORRECTABLE_ERROR = 61 ;
+static const uint8_t P9N2_PHB_ACT0_REG_TCE_RESERVED01 = 62 ;
+static const uint8_t P9N2_PHB_ACT0_REG_LEM_FIR_INTERNAL_PARITY_ERROR = 63 ;
+
+static const uint8_t P9N2_PHB_ACTION1_REG_AIB_COMMAND_INVALID = 0 ;
+static const uint8_t P9N2_PHB_ACTION1_REG_AIB_ADDRESSING_ERROR = 1 ;
+static const uint8_t P9N2_PHB_ACTION1_REG_AIB_ACCESS_ERROR = 2 ;
+static const uint8_t P9N2_PHB_ACTION1_REG_PAPR_OUTBOUND_INJECTION_ERROR_TRIGGERED = 3 ;
+static const uint8_t P9N2_PHB_ACTION1_REG_AIB_FATAL_CLASS_ERROR = 4 ;
+static const uint8_t P9N2_PHB_ACTION1_REG_AIB_INF_CLASS_ERROR = 5 ;
+static const uint8_t P9N2_PHB_ACTION1_REG_PE_STOP_STATE_ERROR = 6 ;
+static const uint8_t P9N2_PHB_ACTION1_REG_AIB_DAT_ERR_SIGNALED = 7 ;
+static const uint8_t P9N2_PHB_ACTION1_REG_OUT_COMMON_ARRAY_FATAL_ERROR = 8 ;
+static const uint8_t P9N2_PHB_ACTION1_REG_OUT_COMMON_LATCH_FATAL_ERROR = 9 ;
+static const uint8_t P9N2_PHB_ACTION1_REG_OUT_COMMON_LOGIC_FATAL_ERROR = 10 ;
+static const uint8_t P9N2_PHB_ACTION1_REG_BLIF_OUT_INTERFACE_PARITY_ERROR = 11 ;
+static const uint8_t P9N2_PHB_ACTION1_REG_PCIE_CFG_WRITE_CA_OR_UR_RESPONSE = 12 ;
+static const uint8_t P9N2_PHB_ACTION1_REG_MMIO_REQUEST_TIMEOUT = 13 ;
+static const uint8_t P9N2_PHB_ACTION1_REG_OUT_RRB_SOURCED_ERROR = 14 ;
+static const uint8_t P9N2_PHB_ACTION1_REG_CFG_LOGIC_SIGNALED_ERROR = 15 ;
+static const uint8_t P9N2_PHB_ACTION1_REG_RSB_REG_REQUEST_ADDRESS_ERROR = 16 ;
+static const uint8_t P9N2_PHB_ACTION1_REG_RSB_FDA_FATAL_ERROR = 17 ;
+static const uint8_t P9N2_PHB_ACTION1_REG_RSB_FDA_INF_ERROR = 18 ;
+static const uint8_t P9N2_PHB_ACTION1_REG_RSB_FDB_FATAL_ERROR = 19 ;
+static const uint8_t P9N2_PHB_ACTION1_REG_RSB_FDB_INF_ERROR = 20 ;
+static const uint8_t P9N2_PHB_ACTION1_REG_RSB_ERR_FATAL_ERROR = 21 ;
+static const uint8_t P9N2_PHB_ACTION1_REG_RSB_ERR_INF_ERROR = 22 ;
+static const uint8_t P9N2_PHB_ACTION1_REG_RSB_DBG_FATAL_ERROR = 23 ;
+static const uint8_t P9N2_PHB_ACTION1_REG_RSB_DBG_INF_ERROR = 24 ;
+static const uint8_t P9N2_PHB_ACTION1_REG_RSB_PCIE_REQUEST_ACCESS_ERROR = 25 ;
+static const uint8_t P9N2_PHB_ACTION1_REG_RSB_BUS_LOGIC_ERROR = 26 ;
+static const uint8_t P9N2_PHB_ACTION1_REG_RSB_UVI_FATAL_ERROR = 27 ;
+static const uint8_t P9N2_PHB_ACTION1_REG_RSB_UVI_INF_ERROR = 28 ;
+static const uint8_t P9N2_PHB_ACTION1_REG_SCOM_FATAL_ERROR = 29 ;
+static const uint8_t P9N2_PHB_ACTION1_REG_SCOM_INF_ERROR = 30 ;
+static const uint8_t P9N2_PHB_ACTION1_REG_PCIE_MACRO_ERROR_ACTIVE_STATUS = 31 ;
+static const uint8_t P9N2_PHB_ACTION1_REG_ARB_IODA_FATAL_ERROR = 32 ;
+static const uint8_t P9N2_PHB_ACTION1_REG_ARB_MSI_PE_MATCH_ERROR = 33 ;
+static const uint8_t P9N2_PHB_ACTION1_REG_ARB_MSI_ADDRESS_ERROR = 34 ;
+static const uint8_t P9N2_PHB_ACTION1_REG_ARB_TVT_ERROR = 35 ;
+static const uint8_t P9N2_PHB_ACTION1_REG_ARB_RCVD_FATAL_ERROR_MSG = 36 ;
+static const uint8_t P9N2_PHB_ACTION1_REG_ARB_RCVD_NONFATAL_ERROR_MSG = 37 ;
+static const uint8_t P9N2_PHB_ACTION1_REG_ARB_RCVD_CORRECTIBLE_ERROR_MSG = 38 ;
+static const uint8_t P9N2_PHB_ACTION1_REG_PAPR_INBOUND_INJECTION_ERROR_TRIGGERED = 39 ;
+static const uint8_t P9N2_PHB_ACTION1_REG_ARB_COMMON_FATAL_ERROR = 40 ;
+static const uint8_t P9N2_PHB_ACTION1_REG_ARB_TABLE_BAR_DISABLED_ERROR = 41 ;
+static const uint8_t P9N2_PHB_ACTION1_REG_ARB_BLIF_COMPLETION_ERROR = 42 ;
+static const uint8_t P9N2_PHB_ACTION1_REG_ARB_PCT_TIMEOUT_ERROR = 43 ;
+static const uint8_t P9N2_PHB_ACTION1_REG_ARB_ECC_CORRECTABLE_ERROR = 44 ;
+static const uint8_t P9N2_PHB_ACTION1_REG_ARB_ECC_UNCORRECTABLE_ERROR = 45 ;
+static const uint8_t P9N2_PHB_ACTION1_REG_ARB_TLP_POISON_SIGNALED = 46 ;
+static const uint8_t P9N2_PHB_ACTION1_REG_ARB_RTT_PENUM_INVALID_ERROR = 47 ;
+static const uint8_t P9N2_PHB_ACTION1_REG_MRG_COMMON_FATAL_ERROR = 48 ;
+static const uint8_t P9N2_PHB_ACTION1_REG_MRG_TABLE_BAR_DISABLED_ERROR = 49 ;
+static const uint8_t P9N2_PHB_ACTION1_REG_MRG_ECC_CORRECTABLE_ERROR = 50 ;
+static const uint8_t P9N2_PHB_ACTION1_REG_MRG_ECC_UNCORRECTABLE_ERROR = 51 ;
+static const uint8_t P9N2_PHB_ACTION1_REG_MRG_AIB2_TX_TIMEOUT_ERROR = 52 ;
+static const uint8_t P9N2_PHB_ACTION1_REG_MRG_MRT_ERROR = 53 ;
+static const uint8_t P9N2_PHB_ACTION1_REG_MRG_RESERVED01 = 54 ;
+static const uint8_t P9N2_PHB_ACTION1_REG_MRG_RESERVED02 = 55 ;
+static const uint8_t P9N2_PHB_ACTION1_REG_TCE_IODA_PAGE_ACCESS_ERROR = 56 ;
+static const uint8_t P9N2_PHB_ACTION1_REG_TCE_REQUEST_TIMEOUT_ERROR = 57 ;
+static const uint8_t P9N2_PHB_ACTION1_REG_TCE_UNEXPECTED_RESPONSE_ERROR = 58 ;
+static const uint8_t P9N2_PHB_ACTION1_REG_TCE_COMMON_FATAL_ERRORS = 59 ;
+static const uint8_t P9N2_PHB_ACTION1_REG_TCE_ECC_CORRECTABLE_ERROR = 60 ;
+static const uint8_t P9N2_PHB_ACTION1_REG_TCE_ECC_UNCORRECTABLE_ERROR = 61 ;
+static const uint8_t P9N2_PHB_ACTION1_REG_TCE_RESERVED01 = 62 ;
+static const uint8_t P9N2_PHB_ACTION1_REG_LEM_FIR_INTERNAL_PARITY_ERROR = 63 ;
+
+static const uint8_t P9N2_PEC_ADDREXTMASK_REG_PE = 0 ;
+static const uint8_t P9N2_PEC_ADDREXTMASK_REG_PE_LEN = 7 ;
+
+static const uint8_t P9N2_PU_ADDR_0_HASH_FUNCTION_REG_ADDRESS = 0 ;
+static const uint8_t P9N2_PU_ADDR_0_HASH_FUNCTION_REG_ADDRESS_LEN = 64 ;
+
+static const uint8_t P9N2_PU_ADDR_10_HASH_FUNCTION_REG_ADDRESS = 0 ;
+static const uint8_t P9N2_PU_ADDR_10_HASH_FUNCTION_REG_ADDRESS_LEN = 64 ;
+
+static const uint8_t P9N2_PU_ADDR_1_HASH_FUNCTION_REG_ADDRESS = 0 ;
+static const uint8_t P9N2_PU_ADDR_1_HASH_FUNCTION_REG_ADDRESS_LEN = 64 ;
+
+static const uint8_t P9N2_PU_ADDR_2_HASH_FUNCTION_REG_ADDRESS = 0 ;
+static const uint8_t P9N2_PU_ADDR_2_HASH_FUNCTION_REG_ADDRESS_LEN = 64 ;
+
+static const uint8_t P9N2_PU_ADDR_3_HASH_FUNCTION_REG_ADDRESS = 0 ;
+static const uint8_t P9N2_PU_ADDR_3_HASH_FUNCTION_REG_ADDRESS_LEN = 64 ;
+
+static const uint8_t P9N2_PU_ADDR_4_HASH_FUNCTION_REG_ADDRESS = 0 ;
+static const uint8_t P9N2_PU_ADDR_4_HASH_FUNCTION_REG_ADDRESS_LEN = 64 ;
+
+static const uint8_t P9N2_PU_ADDR_5_HASH_FUNCTION_REG_ADDRESS = 0 ;
+static const uint8_t P9N2_PU_ADDR_5_HASH_FUNCTION_REG_ADDRESS_LEN = 64 ;
+
+static const uint8_t P9N2_PU_ADDR_6_HASH_FUNCTION_REG_ADDRESS = 0 ;
+static const uint8_t P9N2_PU_ADDR_6_HASH_FUNCTION_REG_ADDRESS_LEN = 64 ;
+
+static const uint8_t P9N2_PU_ADDR_7_HASH_FUNCTION_REG_ADDRESS = 0 ;
+static const uint8_t P9N2_PU_ADDR_7_HASH_FUNCTION_REG_ADDRESS_LEN = 64 ;
+
+static const uint8_t P9N2_PU_ADDR_8_HASH_FUNCTION_REG_ADDRESS = 0 ;
+static const uint8_t P9N2_PU_ADDR_8_HASH_FUNCTION_REG_ADDRESS_LEN = 64 ;
+
+static const uint8_t P9N2_PU_ADDR_9_HASH_FUNCTION_REG_ADDRESS = 0 ;
+static const uint8_t P9N2_PU_ADDR_9_HASH_FUNCTION_REG_ADDRESS_LEN = 64 ;
+
+static const uint8_t P9N2_PU_N3_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR = 0 ;
+static const uint8_t P9N2_PU_N3_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN = 16 ;
+static const uint8_t P9N2_PU_N3_ADDR_TRAP_REG_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR = 16 ;
+static const uint8_t P9N2_PU_N3_ADDR_TRAP_REG_RESERVED_LAST_LT = 17 ;
+static const uint8_t P9N2_PU_N3_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR = 18 ;
+static const uint8_t P9N2_PU_N3_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN = 13 ;
+static const uint8_t P9N2_PU_N3_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY = 31 ;
+static const uint8_t P9N2_PU_N3_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR = 32 ;
+static const uint8_t P9N2_PU_N3_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION = 33 ;
+static const uint8_t P9N2_PU_N3_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER = 34 ;
+
+static const uint8_t P9N2_PU_N1_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR = 0 ;
+static const uint8_t P9N2_PU_N1_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN = 16 ;
+static const uint8_t P9N2_PU_N1_ADDR_TRAP_REG_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR = 16 ;
+static const uint8_t P9N2_PU_N1_ADDR_TRAP_REG_RESERVED_LAST_LT = 17 ;
+static const uint8_t P9N2_PU_N1_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR = 18 ;
+static const uint8_t P9N2_PU_N1_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN = 13 ;
+static const uint8_t P9N2_PU_N1_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY = 31 ;
+static const uint8_t P9N2_PU_N1_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR = 32 ;
+static const uint8_t P9N2_PU_N1_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION = 33 ;
+static const uint8_t P9N2_PU_N1_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER = 34 ;
+
+static const uint8_t P9N2_PU_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR = 0 ;
+static const uint8_t P9N2_PU_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN = 16 ;
+static const uint8_t P9N2_PU_ADDR_TRAP_REG_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR = 16 ;
+static const uint8_t P9N2_PU_ADDR_TRAP_REG_RESERVED_LAST_LT = 17 ;
+static const uint8_t P9N2_PU_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR = 18 ;
+static const uint8_t P9N2_PU_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN = 13 ;
+static const uint8_t P9N2_PU_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY = 31 ;
+static const uint8_t P9N2_PU_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR = 32 ;
+static const uint8_t P9N2_PU_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION = 33 ;
+static const uint8_t P9N2_PU_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER = 34 ;
+
+static const uint8_t P9N2_PU_N2_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR = 0 ;
+static const uint8_t P9N2_PU_N2_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN = 16 ;
+static const uint8_t P9N2_PU_N2_ADDR_TRAP_REG_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR = 16 ;
+static const uint8_t P9N2_PU_N2_ADDR_TRAP_REG_RESERVED_LAST_LT = 17 ;
+static const uint8_t P9N2_PU_N2_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR = 18 ;
+static const uint8_t P9N2_PU_N2_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN = 13 ;
+static const uint8_t P9N2_PU_N2_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY = 31 ;
+static const uint8_t P9N2_PU_N2_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR = 32 ;
+static const uint8_t P9N2_PU_N2_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION = 33 ;
+static const uint8_t P9N2_PU_N2_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER = 34 ;
+
+static const uint8_t P9N2_PEC_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR = 0 ;
+static const uint8_t P9N2_PEC_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN = 16 ;
+static const uint8_t P9N2_PEC_ADDR_TRAP_REG_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR = 16 ;
+static const uint8_t P9N2_PEC_ADDR_TRAP_REG_RESERVED_LAST_LT = 17 ;
+static const uint8_t P9N2_PEC_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR = 18 ;
+static const uint8_t P9N2_PEC_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN = 13 ;
+static const uint8_t P9N2_PEC_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY = 31 ;
+static const uint8_t P9N2_PEC_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR = 32 ;
+static const uint8_t P9N2_PEC_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION = 33 ;
+static const uint8_t P9N2_PEC_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER = 34 ;
+
+static const uint8_t P9N2_PU_N0_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR = 0 ;
+static const uint8_t P9N2_PU_N0_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN = 16 ;
+static const uint8_t P9N2_PU_N0_ADDR_TRAP_REG_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR = 16 ;
+static const uint8_t P9N2_PU_N0_ADDR_TRAP_REG_RESERVED_LAST_LT = 17 ;
+static const uint8_t P9N2_PU_N0_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR = 18 ;
+static const uint8_t P9N2_PU_N0_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN = 13 ;
+static const uint8_t P9N2_PU_N0_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY = 31 ;
+static const uint8_t P9N2_PU_N0_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR = 32 ;
+static const uint8_t P9N2_PU_N0_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION = 33 ;
+static const uint8_t P9N2_PU_N0_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER = 34 ;
+
+static const uint8_t P9N2_PU_ADS_XSCOM_CMD_REG_RNW = 0 ;
+static const uint8_t P9N2_PU_ADS_XSCOM_CMD_REG_SIZE = 5 ;
+static const uint8_t P9N2_PU_ADS_XSCOM_CMD_REG_SIZE_LEN = 7 ;
+static const uint8_t P9N2_PU_ADS_XSCOM_CMD_REG_ADR = 30 ;
+static const uint8_t P9N2_PU_ADS_XSCOM_CMD_REG_ADR_LEN = 34 ;
+
+static const uint8_t P9N2_PU_ADU_HANG_DIV_REG_DATA = 0 ;
+static const uint8_t P9N2_PU_ADU_HANG_DIV_REG_DATA_LEN = 5 ;
+static const uint8_t P9N2_PU_ADU_HANG_DIV_REG_OPER = 5 ;
+static const uint8_t P9N2_PU_ADU_HANG_DIV_REG_OPER_LEN = 5 ;
+
+static const uint8_t P9N2_PU_ALTD_ADDR_REG_FBC_ADDRESS = 8 ;
+static const uint8_t P9N2_PU_ALTD_ADDR_REG_FBC_ADDRESS_LEN = 56 ;
+
+static const uint8_t P9N2_PU_ALTD_CMD_REG_FBC_START_OP = 2 ;
+static const uint8_t P9N2_PU_ALTD_CMD_REG_FBC_CLEAR_STATUS = 3 ;
+static const uint8_t P9N2_PU_ALTD_CMD_REG_FBC_RESET_FSM = 4 ;
+static const uint8_t P9N2_PU_ALTD_CMD_REG_FBC_RNW = 5 ;
+static const uint8_t P9N2_PU_ALTD_CMD_REG_FBC_AXTYPE = 6 ;
+static const uint8_t P9N2_PU_ALTD_CMD_REG_FBC_DATA_ONLY = 7 ;
+static const uint8_t P9N2_PU_ALTD_CMD_REG_FBC_LOCK_PICK = 10 ;
+static const uint8_t P9N2_PU_ALTD_CMD_REG_FBC_LOCKED = 11 ;
+static const uint8_t P9N2_PU_ALTD_CMD_REG_FBC_LOCK_ID = 12 ;
+static const uint8_t P9N2_PU_ALTD_CMD_REG_FBC_LOCK_ID_LEN = 4 ;
+static const uint8_t P9N2_PU_ALTD_CMD_REG_FBC_SCOPE = 16 ;
+static const uint8_t P9N2_PU_ALTD_CMD_REG_FBC_SCOPE_LEN = 3 ;
+static const uint8_t P9N2_PU_ALTD_CMD_REG_FBC_AUTO_INC = 19 ;
+static const uint8_t P9N2_PU_ALTD_CMD_REG_FBC_DROP_PRIORITY = 20 ;
+static const uint8_t P9N2_PU_ALTD_CMD_REG_FBC_DROP_PRIORITY_MAX = 21 ;
+static const uint8_t P9N2_PU_ALTD_CMD_REG_FBC_OVERWRITE_PBINIT = 22 ;
+static const uint8_t P9N2_PU_ALTD_CMD_REG_FBC_PIB_DIRECT = 23 ;
+static const uint8_t P9N2_PU_ALTD_CMD_REG_FBC_WITH_TM_QUIESCE = 24 ;
+static const uint8_t P9N2_PU_ALTD_CMD_REG_FBC_TTYPE = 25 ;
+static const uint8_t P9N2_PU_ALTD_CMD_REG_FBC_TTYPE_LEN = 7 ;
+static const uint8_t P9N2_PU_ALTD_CMD_REG_FBC_TSIZE = 32 ;
+static const uint8_t P9N2_PU_ALTD_CMD_REG_FBC_TSIZE_LEN = 8 ;
+
+static const uint8_t P9N2_PU_ALTD_DATA_REG_FBC = 0 ;
+static const uint8_t P9N2_PU_ALTD_DATA_REG_FBC_LEN = 64 ;
+
+static const uint8_t P9N2_PU_ALTD_OPTION_REG_FBC_WITH_PBINIT_LOW_WAIT = 22 ;
+static const uint8_t P9N2_PU_ALTD_OPTION_REG_FBC_WITH_PRE_QUIESCE = 23 ;
+static const uint8_t P9N2_PU_ALTD_OPTION_REG_FBC_AFTER_QUIESCE_WAIT_COUNT = 28 ;
+static const uint8_t P9N2_PU_ALTD_OPTION_REG_FBC_AFTER_QUIESCE_WAIT_COUNT_LEN = 20 ;
+static const uint8_t P9N2_PU_ALTD_OPTION_REG_FBC_WITH_POST_INIT = 51 ;
+static const uint8_t P9N2_PU_ALTD_OPTION_REG_FBC_WITH_FAST_PATH = 52 ;
+static const uint8_t P9N2_PU_ALTD_OPTION_REG_FBC_BEFORE_INIT_WAIT_COUNT = 54 ;
+static const uint8_t P9N2_PU_ALTD_OPTION_REG_FBC_BEFORE_INIT_WAIT_COUNT_LEN = 10 ;
+
+static const uint8_t P9N2_PU_ALTD_STATUS_REG_FBC_ALTD_BUSY = 0 ;
+static const uint8_t P9N2_PU_ALTD_STATUS_REG_FBC_WAIT_CMD_ARBIT = 1 ;
+static const uint8_t P9N2_PU_ALTD_STATUS_REG_FBC_ADDR_DONE = 2 ;
+static const uint8_t P9N2_PU_ALTD_STATUS_REG_FBC_DATA_DONE = 3 ;
+static const uint8_t P9N2_PU_ALTD_STATUS_REG_FBC_WAIT_RESP = 4 ;
+static const uint8_t P9N2_PU_ALTD_STATUS_REG_FBC_OVERRUN_ERROR = 5 ;
+static const uint8_t P9N2_PU_ALTD_STATUS_REG_FBC_AUTOINC_ERROR = 6 ;
+static const uint8_t P9N2_PU_ALTD_STATUS_REG_FBC_COMMAND_ERROR = 7 ;
+static const uint8_t P9N2_PU_ALTD_STATUS_REG_FBC_ADDRESS_ERROR = 8 ;
+static const uint8_t P9N2_PU_ALTD_STATUS_REG_FBC_PB_OP_HANG_ERR = 9 ;
+static const uint8_t P9N2_PU_ALTD_STATUS_REG_FBC_PB_DATA_HANG_ERR = 10 ;
+static const uint8_t P9N2_PU_ALTD_STATUS_REG_FBC_PB_UNEXPECT_CRESP_ERR = 11 ;
+static const uint8_t P9N2_PU_ALTD_STATUS_REG_FBC_PB_UNEXPECT_DATA_ERR = 12 ;
+static const uint8_t P9N2_PU_ALTD_STATUS_REG_FBC_WAIT_PIB_DIRECT = 16 ;
+static const uint8_t P9N2_PU_ALTD_STATUS_REG_FBC_PIB_DIRECT_DONE = 17 ;
+static const uint8_t P9N2_PU_ALTD_STATUS_REG_FBC_PBINIT_MISSING = 18 ;
+static const uint8_t P9N2_PU_ALTD_STATUS_REG_FBC_PIB_ERROR = 33 ;
+static const uint8_t P9N2_PU_ALTD_STATUS_REG_FBC_PIB_ERROR_LEN = 5 ;
+static const uint8_t P9N2_PU_ALTD_STATUS_REG_FBC_ECC_CE = 48 ;
+static const uint8_t P9N2_PU_ALTD_STATUS_REG_FBC_ECC_UE = 49 ;
+static const uint8_t P9N2_PU_ALTD_STATUS_REG_FBC_ECC_SUE = 50 ;
+static const uint8_t P9N2_PU_ALTD_STATUS_REG_FBC_CRESP_VALUE = 59 ;
+static const uint8_t P9N2_PU_ALTD_STATUS_REG_FBC_CRESP_VALUE_LEN = 5 ;
+
+static const uint8_t P9N2_PU_NPU_CTL_ALTER_CREDIT_COUNTERS_CRD_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NPU_CTL_ALTER_CREDIT_COUNTERS_CRD_RESERVED = 1 ;
+static const uint8_t P9N2_PU_NPU_CTL_ALTER_CREDIT_COUNTERS_CRD_RESERVED_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_CTL_ALTER_CREDIT_COUNTERS_CRD_TARGET = 4 ;
+static const uint8_t P9N2_PU_NPU_CTL_ALTER_CREDIT_COUNTERS_CRD_TARGET_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_CTL_ALTER_CREDIT_COUNTERS_CRD_VALUE = 8 ;
+static const uint8_t P9N2_PU_NPU_CTL_ALTER_CREDIT_COUNTERS_CRD_VALUE_LEN = 16 ;
+
+static const uint8_t P9N2__CTL_ALTER_CREDIT_COUNTERS_CRD_ENABLE = 0 ;
+static const uint8_t P9N2__CTL_ALTER_CREDIT_COUNTERS_CRD_RESERVED = 1 ;
+static const uint8_t P9N2__CTL_ALTER_CREDIT_COUNTERS_CRD_RESERVED_LEN = 3 ;
+static const uint8_t P9N2__CTL_ALTER_CREDIT_COUNTERS_CRD_TARGET = 4 ;
+static const uint8_t P9N2__CTL_ALTER_CREDIT_COUNTERS_CRD_TARGET_LEN = 4 ;
+static const uint8_t P9N2__CTL_ALTER_CREDIT_COUNTERS_CRD_VALUE = 8 ;
+static const uint8_t P9N2__CTL_ALTER_CREDIT_COUNTERS_CRD_VALUE_LEN = 16 ;
+
+static const uint8_t P9N2__SM3_ALTER_CREDIT_COUNTERS_CRD_ENABLE = 0 ;
+static const uint8_t P9N2__SM3_ALTER_CREDIT_COUNTERS_CRD_RESERVED = 1 ;
+static const uint8_t P9N2__SM3_ALTER_CREDIT_COUNTERS_CRD_RESERVED_LEN = 3 ;
+static const uint8_t P9N2__SM3_ALTER_CREDIT_COUNTERS_CRD_TARGET = 4 ;
+static const uint8_t P9N2__SM3_ALTER_CREDIT_COUNTERS_CRD_TARGET_LEN = 4 ;
+static const uint8_t P9N2__SM3_ALTER_CREDIT_COUNTERS_CRD_VALUE = 8 ;
+static const uint8_t P9N2__SM3_ALTER_CREDIT_COUNTERS_CRD_VALUE_LEN = 16 ;
+
+static const uint8_t P9N2_PU_NPU_SM3_ALTER_CREDIT_COUNTERS_CRD_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NPU_SM3_ALTER_CREDIT_COUNTERS_CRD_RESERVED = 1 ;
+static const uint8_t P9N2_PU_NPU_SM3_ALTER_CREDIT_COUNTERS_CRD_RESERVED_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_SM3_ALTER_CREDIT_COUNTERS_CRD_TARGET = 4 ;
+static const uint8_t P9N2_PU_NPU_SM3_ALTER_CREDIT_COUNTERS_CRD_TARGET_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_SM3_ALTER_CREDIT_COUNTERS_CRD_VALUE = 8 ;
+static const uint8_t P9N2_PU_NPU_SM3_ALTER_CREDIT_COUNTERS_CRD_VALUE_LEN = 16 ;
+
+static const uint8_t P9N2_CAPP_APCFG_SPARE1 = 1 ;
+static const uint8_t P9N2_CAPP_APCFG_APCCTL_PHB_SEL = 2 ;
+static const uint8_t P9N2_CAPP_APCFG_APCCTL_PHB_SEL_LEN = 2 ;
+static const uint8_t P9N2_CAPP_APCFG_HANG_POLL_SCALE = 4 ;
+static const uint8_t P9N2_CAPP_APCFG_HANG_POLL_SCALE_LEN = 4 ;
+static const uint8_t P9N2_CAPP_APCFG_SPEC_HPC_DIR_STATE = 8 ;
+static const uint8_t P9N2_CAPP_APCFG_SPEC_HPC_DIR_STATE_LEN = 5 ;
+static const uint8_t P9N2_CAPP_APCFG_SPARE = 13 ;
+static const uint8_t P9N2_CAPP_APCFG_APCCTL_P9_MODE = 14 ;
+static const uint8_t P9N2_CAPP_APCFG_APCCTL_SYSADDR = 15 ;
+static const uint8_t P9N2_CAPP_APCFG_APCCTL_SYSADDR_LEN = 6 ;
+static const uint8_t P9N2_CAPP_APCFG_APCCTL_MEM_SEL_MODE = 21 ;
+static const uint8_t P9N2_CAPP_APCFG_APCCTL_ENB_FRC_ADDR13 = 22 ;
+static const uint8_t P9N2_CAPP_APCFG_DFS_ISUE_DIR_STATE = 23 ;
+static const uint8_t P9N2_CAPP_APCFG_DFS_ISUE_DIR_STATE_LEN = 5 ;
+
+static const uint8_t P9N2_CAPP_APCLCO_TARGET_VALID = 0 ;
+static const uint8_t P9N2_CAPP_APCLCO_TARGET_VALID_LEN = 12 ;
+static const uint8_t P9N2_CAPP_APCLCO_TARGET_ID0 = 12 ;
+static const uint8_t P9N2_CAPP_APCLCO_TARGET_MIN = 13 ;
+static const uint8_t P9N2_CAPP_APCLCO_TARGET_MIN_LEN = 3 ;
+
+static const uint8_t P9N2_CAPP_APCRDFSMMASK_APC_RDFSM_MASK = 0 ;
+static const uint8_t P9N2_CAPP_APCRDFSMMASK_APC_RDFSM_MASK_LEN = 48 ;
+
+static const uint8_t P9N2_CAPP_APCTL_APCCTL_ENB_CRESP_EXAM = 0 ;
+static const uint8_t P9N2_CAPP_APCTL_APCCTL_ADR_BAR_MODE = 1 ;
+static const uint8_t P9N2_CAPP_APCTL_APCCTL_DISABLE_NN_RN = 2 ;
+static const uint8_t P9N2_CAPP_APCTL_APCCTL_DISABLE_VG_NOT_SYS = 3 ;
+static const uint8_t P9N2_CAPP_APCTL_APCCTL_DISABLE_G = 4 ;
+static const uint8_t P9N2_CAPP_APCTL_APCCTL_DISABLE_LN = 5 ;
+static const uint8_t P9N2_CAPP_APCTL_APCCTL_SKIP_G = 6 ;
+static const uint8_t P9N2_CAPP_APCTL_APCCTL_HANG_ARE = 7 ;
+static const uint8_t P9N2_CAPP_APCTL_APCCTL_HANG_DEAD = 8 ;
+static const uint8_t P9N2_CAPP_APCTL_APCCTL_CFG_BKILL_INC = 9 ;
+static const uint8_t P9N2_CAPP_APCTL_DCACHE_MODE = 10 ;
+static const uint8_t P9N2_CAPP_APCTL_DCACHE_REPORTS_PHYSICAL = 11 ;
+static const uint8_t P9N2_CAPP_APCTL_APCCTL_DISABLE_PSL_CMDQUEUE = 12 ;
+static const uint8_t P9N2_CAPP_APCTL_APCCTL_ENABLE_MASTER_RETRY_BACKOFF = 13 ;
+static const uint8_t P9N2_CAPP_APCTL_SCPTGT_LFSR_MODE = 14 ;
+static const uint8_t P9N2_CAPP_APCTL_SCPTGT_LFSR_MODE_LEN = 3 ;
+static const uint8_t P9N2_CAPP_APCTL_APCCTL_ENABLE_RD_VG_SCOPE_PREDICT = 17 ;
+static const uint8_t P9N2_CAPP_APCTL_SPARE = 18 ;
+static const uint8_t P9N2_CAPP_APCTL_APCCTL_SMF_CONFIG = 19 ;
+static const uint8_t P9N2_CAPP_APCTL_APCCTL_SMF_CONFIG_LEN = 2 ;
+static const uint8_t P9N2_CAPP_APCTL_APCCTL_CHIP_ADDR_EXTENSION_MASK_ENABLE = 21 ;
+static const uint8_t P9N2_CAPP_APCTL_APCCTL_CHIP_ADDR_EXTENSION_MASK_ENABLE_LEN = 7 ;
+static const uint8_t P9N2_CAPP_APCTL_WR_EPSILON_VALUE = 39 ;
+static const uint8_t P9N2_CAPP_APCTL_WR_EPSILON_VALUE_LEN = 7 ;
+static const uint8_t P9N2_CAPP_APCTL_APCCTL_MAX_RETRY = 56 ;
+static const uint8_t P9N2_CAPP_APCTL_APCCTL_MAX_RETRY_LEN = 8 ;
+
+static const uint8_t P9N2_CAPP_APC_ARRY_ADDR_ENCD_ARRAY_SELECT = 2 ;
+static const uint8_t P9N2_CAPP_APC_ARRY_ADDR_APCARY_ADDRESS = 3 ;
+static const uint8_t P9N2_CAPP_APC_ARRY_ADDR_APCARY_ADDRESS_LEN = 9 ;
+
+static const uint8_t P9N2_CAPP_APC_ARRY_RDDATA_APCARY = 0 ;
+static const uint8_t P9N2_CAPP_APC_ARRY_RDDATA_APCARY_LEN = 64 ;
+
+static const uint8_t P9N2_CAPP_APC_ARRY_WRDATA_APCARY = 0 ;
+static const uint8_t P9N2_CAPP_APC_ARRY_WRDATA_APCARY_LEN = 64 ;
+
+static const uint8_t P9N2_CAPP_APC_ERRINJ_ENABLE = 0 ;
+static const uint8_t P9N2_CAPP_APC_ERRINJ_DBLERR = 1 ;
+static const uint8_t P9N2_CAPP_APC_ERRINJ_CONTINUOUS = 2 ;
+static const uint8_t P9N2_CAPP_APC_ERRINJ_TARGET = 7 ;
+static const uint8_t P9N2_CAPP_APC_ERRINJ_TARGET_LEN = 5 ;
+static const uint8_t P9N2_CAPP_APC_ERRINJ_SNP_ERROR_INJECT_ENABLE = 12 ;
+static const uint8_t P9N2_CAPP_APC_ERRINJ_SNP_INJECT_DBL_ECC_ERROR = 13 ;
+static const uint8_t P9N2_CAPP_APC_ERRINJ_SNP_INJECT_CONTINOUS_ERROR = 14 ;
+static const uint8_t P9N2_CAPP_APC_ERRINJ_SNP_ERROR_INJECT_TARGET = 17 ;
+static const uint8_t P9N2_CAPP_APC_ERRINJ_SNP_ERROR_INJECT_TARGET_LEN = 7 ;
+static const uint8_t P9N2_CAPP_APC_ERRINJ_XPT_ERROR_INJECT_ENABLE = 32 ;
+static const uint8_t P9N2_CAPP_APC_ERRINJ_XPT_ERROR_TYPE = 33 ;
+static const uint8_t P9N2_CAPP_APC_ERRINJ_XPT_ERROR_TYPE_LEN = 2 ;
+static const uint8_t P9N2_CAPP_APC_ERRINJ_XPT_INJECT_CONTINUOUS_ERROR = 35 ;
+static const uint8_t P9N2_CAPP_APC_ERRINJ_XPT_ERROR_INJECT_TARGET = 36 ;
+static const uint8_t P9N2_CAPP_APC_ERRINJ_XPT_ERROR_INJECT_TARGET_LEN = 4 ;
+
+static const uint8_t P9N2_CAPP_APC_PMUSEL_GRPSEL = 0 ;
+static const uint8_t P9N2_CAPP_APC_PMUSEL_GRPSEL_LEN = 4 ;
+static const uint8_t P9N2_CAPP_APC_PMUSEL_FSMJ_EVENT_SEL = 6 ;
+static const uint8_t P9N2_CAPP_APC_PMUSEL_FSMJ_EVENT_SEL_LEN = 6 ;
+static const uint8_t P9N2_CAPP_APC_PMUSEL_FSMJ_FSM_SEL = 13 ;
+static const uint8_t P9N2_CAPP_APC_PMUSEL_FSMJ_FSM_SEL_LEN = 7 ;
+
+static const uint8_t P9N2_CAPP_ASE_TUPLE0_LPID = 4 ;
+static const uint8_t P9N2_CAPP_ASE_TUPLE0_LPID_LEN = 12 ;
+static const uint8_t P9N2_CAPP_ASE_TUPLE0_PID = 20 ;
+static const uint8_t P9N2_CAPP_ASE_TUPLE0_PID_LEN = 20 ;
+static const uint8_t P9N2_CAPP_ASE_TUPLE0_TID = 44 ;
+static const uint8_t P9N2_CAPP_ASE_TUPLE0_TID_LEN = 16 ;
+static const uint8_t P9N2_CAPP_ASE_TUPLE0_VALID = 63 ;
+
+static const uint8_t P9N2_CAPP_ASE_TUPLE1_LPID = 4 ;
+static const uint8_t P9N2_CAPP_ASE_TUPLE1_LPID_LEN = 12 ;
+static const uint8_t P9N2_CAPP_ASE_TUPLE1_PID = 20 ;
+static const uint8_t P9N2_CAPP_ASE_TUPLE1_PID_LEN = 20 ;
+static const uint8_t P9N2_CAPP_ASE_TUPLE1_TID = 44 ;
+static const uint8_t P9N2_CAPP_ASE_TUPLE1_TID_LEN = 16 ;
+static const uint8_t P9N2_CAPP_ASE_TUPLE1_VALID = 63 ;
+
+static const uint8_t P9N2_CAPP_ASE_TUPLE2_LPID = 4 ;
+static const uint8_t P9N2_CAPP_ASE_TUPLE2_LPID_LEN = 12 ;
+static const uint8_t P9N2_CAPP_ASE_TUPLE2_PID = 20 ;
+static const uint8_t P9N2_CAPP_ASE_TUPLE2_PID_LEN = 20 ;
+static const uint8_t P9N2_CAPP_ASE_TUPLE2_TID = 44 ;
+static const uint8_t P9N2_CAPP_ASE_TUPLE2_TID_LEN = 16 ;
+static const uint8_t P9N2_CAPP_ASE_TUPLE2_VALID = 63 ;
+
+static const uint8_t P9N2_CAPP_ASE_TUPLE3_LPID = 4 ;
+static const uint8_t P9N2_CAPP_ASE_TUPLE3_LPID_LEN = 12 ;
+static const uint8_t P9N2_CAPP_ASE_TUPLE3_PID = 20 ;
+static const uint8_t P9N2_CAPP_ASE_TUPLE3_PID_LEN = 20 ;
+static const uint8_t P9N2_CAPP_ASE_TUPLE3_TID = 44 ;
+static const uint8_t P9N2_CAPP_ASE_TUPLE3_TID_LEN = 16 ;
+static const uint8_t P9N2_CAPP_ASE_TUPLE3_VALID = 63 ;
+
+static const uint8_t P9N2_PEC_ASSIST_INTERRUPT_REG_ATTN = 0 ;
+static const uint8_t P9N2_PEC_ASSIST_INTERRUPT_REG_RECOV = 1 ;
+static const uint8_t P9N2_PEC_ASSIST_INTERRUPT_REG_XSTOP = 2 ;
+
+static const uint8_t P9N2_PU_N3_ATOMIC_LOCK_MASK_LATCH_REG_MASK = 0 ;
+static const uint8_t P9N2_PU_N3_ATOMIC_LOCK_MASK_LATCH_REG_MASK_LEN = 16 ;
+
+static const uint8_t P9N2_PU_N1_ATOMIC_LOCK_MASK_LATCH_REG_MASK = 0 ;
+static const uint8_t P9N2_PU_N1_ATOMIC_LOCK_MASK_LATCH_REG_MASK_LEN = 16 ;
+
+static const uint8_t P9N2_PU_ATOMIC_LOCK_MASK_LATCH_REG_MASK = 0 ;
+static const uint8_t P9N2_PU_ATOMIC_LOCK_MASK_LATCH_REG_MASK_LEN = 16 ;
+
+static const uint8_t P9N2_PU_N2_ATOMIC_LOCK_MASK_LATCH_REG_MASK = 0 ;
+static const uint8_t P9N2_PU_N2_ATOMIC_LOCK_MASK_LATCH_REG_MASK_LEN = 16 ;
+
+static const uint8_t P9N2_PEC_ATOMIC_LOCK_MASK_LATCH_REG_MASK = 0 ;
+static const uint8_t P9N2_PEC_ATOMIC_LOCK_MASK_LATCH_REG_MASK_LEN = 16 ;
+
+static const uint8_t P9N2_PU_N0_ATOMIC_LOCK_MASK_LATCH_REG_MASK = 0 ;
+static const uint8_t P9N2_PU_N0_ATOMIC_LOCK_MASK_LATCH_REG_MASK_LEN = 16 ;
+
+static const uint8_t P9N2_PEC_ATOMIC_LOCK_REG_ENABLE = 0 ;
+static const uint8_t P9N2_PEC_ATOMIC_LOCK_REG_ID = 1 ;
+static const uint8_t P9N2_PEC_ATOMIC_LOCK_REG_ID_LEN = 4 ;
+static const uint8_t P9N2_PEC_ATOMIC_LOCK_REG_ACTIVITY = 8 ;
+static const uint8_t P9N2_PEC_ATOMIC_LOCK_REG_ACTIVITY_LEN = 8 ;
+
+static const uint8_t P9N2_PU_NPU1_SM1_ATR_HA_PTR_RESERVED1 = 0 ;
+static const uint8_t P9N2_PU_NPU1_SM1_ATR_HA_PTR_RESERVED1_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM1_ATR_HA_PTR_START = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM1_ATR_HA_PTR_START_LEN = 7 ;
+static const uint8_t P9N2_PU_NPU1_SM1_ATR_HA_PTR_RESERVED2 = 12 ;
+static const uint8_t P9N2_PU_NPU1_SM1_ATR_HA_PTR_RESERVED2_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM1_ATR_HA_PTR_END = 17 ;
+static const uint8_t P9N2_PU_NPU1_SM1_ATR_HA_PTR_END_LEN = 7 ;
+
+static const uint8_t P9N2_PU_NPU_SM2_ATR_HA_PTR_RESERVED1 = 0 ;
+static const uint8_t P9N2_PU_NPU_SM2_ATR_HA_PTR_RESERVED1_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM2_ATR_HA_PTR_START = 5 ;
+static const uint8_t P9N2_PU_NPU_SM2_ATR_HA_PTR_START_LEN = 7 ;
+static const uint8_t P9N2_PU_NPU_SM2_ATR_HA_PTR_RESERVED2 = 12 ;
+static const uint8_t P9N2_PU_NPU_SM2_ATR_HA_PTR_RESERVED2_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM2_ATR_HA_PTR_END = 17 ;
+static const uint8_t P9N2_PU_NPU_SM2_ATR_HA_PTR_END_LEN = 7 ;
+
+static const uint8_t P9N2_PU_NPU1_SM2_ATR_HA_PTR_RESERVED1 = 0 ;
+static const uint8_t P9N2_PU_NPU1_SM2_ATR_HA_PTR_RESERVED1_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM2_ATR_HA_PTR_START = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM2_ATR_HA_PTR_START_LEN = 7 ;
+static const uint8_t P9N2_PU_NPU1_SM2_ATR_HA_PTR_RESERVED2 = 12 ;
+static const uint8_t P9N2_PU_NPU1_SM2_ATR_HA_PTR_RESERVED2_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM2_ATR_HA_PTR_END = 17 ;
+static const uint8_t P9N2_PU_NPU1_SM2_ATR_HA_PTR_END_LEN = 7 ;
+
+static const uint8_t P9N2_PU_NPU_SM1_ATR_HA_PTR_RESERVED1 = 0 ;
+static const uint8_t P9N2_PU_NPU_SM1_ATR_HA_PTR_RESERVED1_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM1_ATR_HA_PTR_START = 5 ;
+static const uint8_t P9N2_PU_NPU_SM1_ATR_HA_PTR_START_LEN = 7 ;
+static const uint8_t P9N2_PU_NPU_SM1_ATR_HA_PTR_RESERVED2 = 12 ;
+static const uint8_t P9N2_PU_NPU_SM1_ATR_HA_PTR_RESERVED2_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM1_ATR_HA_PTR_END = 17 ;
+static const uint8_t P9N2_PU_NPU_SM1_ATR_HA_PTR_END_LEN = 7 ;
+
+static const uint8_t P9N2__SM2_ATR_HA_PTR_RESERVED1 = 0 ;
+static const uint8_t P9N2__SM2_ATR_HA_PTR_RESERVED1_LEN = 5 ;
+static const uint8_t P9N2__SM2_ATR_HA_PTR_START = 5 ;
+static const uint8_t P9N2__SM2_ATR_HA_PTR_START_LEN = 7 ;
+static const uint8_t P9N2__SM2_ATR_HA_PTR_RESERVED2 = 12 ;
+static const uint8_t P9N2__SM2_ATR_HA_PTR_RESERVED2_LEN = 5 ;
+static const uint8_t P9N2__SM2_ATR_HA_PTR_END = 17 ;
+static const uint8_t P9N2__SM2_ATR_HA_PTR_END_LEN = 7 ;
+
+static const uint8_t P9N2__SM1_ATR_HA_PTR_RESERVED1 = 0 ;
+static const uint8_t P9N2__SM1_ATR_HA_PTR_RESERVED1_LEN = 5 ;
+static const uint8_t P9N2__SM1_ATR_HA_PTR_START = 5 ;
+static const uint8_t P9N2__SM1_ATR_HA_PTR_START_LEN = 7 ;
+static const uint8_t P9N2__SM1_ATR_HA_PTR_RESERVED2 = 12 ;
+static const uint8_t P9N2__SM1_ATR_HA_PTR_RESERVED2_LEN = 5 ;
+static const uint8_t P9N2__SM1_ATR_HA_PTR_END = 17 ;
+static const uint8_t P9N2__SM1_ATR_HA_PTR_END_LEN = 7 ;
+
+static const uint8_t P9N2__SM0_ATS_CKSW_SPARE = 0 ;
+static const uint8_t P9N2__SM0_ATS_CKSW_SPARE_LEN = 64 ;
+
+static const uint8_t P9N2__SM1_ATS_CTRL_ARB_STOP = 0 ;
+static const uint8_t P9N2__SM1_ATS_CTRL_ARB_STALL = 1 ;
+static const uint8_t P9N2__SM1_ATS_CTRL_TCE_CACHE_DISABLE = 2 ;
+static const uint8_t P9N2__SM1_ATS_CTRL_TCE_CACHE_1W = 3 ;
+static const uint8_t P9N2__SM1_ATS_CTRL_CONFIG_BRAZOS = 4 ;
+static const uint8_t P9N2__SM1_ATS_CTRL_CONFIG_SYNC_WAIT = 5 ;
+static const uint8_t P9N2__SM1_ATS_CTRL_CONFIG_SYNC_WAIT_LEN = 5 ;
+static const uint8_t P9N2__SM1_ATS_CTRL_SPARE = 10 ;
+static const uint8_t P9N2__SM1_ATS_CTRL_SPARE_LEN = 54 ;
+
+static const uint8_t P9N2__SM0_ATS_HOLD_TVT_ENTRY_INVALID_ESR = 0 ;
+static const uint8_t P9N2__SM0_ATS_HOLD_TVT_ADDR_RANGE_ERR_ESR = 1 ;
+static const uint8_t P9N2__SM0_ATS_HOLD_TCE_PAGE_ACCESS_ERR_ESR = 2 ;
+static const uint8_t P9N2__SM0_ATS_HOLD_TCE_CACHE_MULT_HIT_ERR_ESR = 3 ;
+static const uint8_t P9N2__SM0_ATS_HOLD_MLC_ACCESS_ERR_ESR = 4 ;
+static const uint8_t P9N2__SM0_ATS_HOLD_TCE_REQ_TO_ERR_ESR = 5 ;
+static const uint8_t P9N2__SM0_ATS_HOLD_TCD_PERR_ESR = 6 ;
+static const uint8_t P9N2__SM0_ATS_HOLD_TDR_PERR_ESR = 7 ;
+static const uint8_t P9N2__SM0_ATS_HOLD_AT_EA_UE_ESR = 8 ;
+static const uint8_t P9N2__SM0_ATS_HOLD_AT_EA_CE_ESR = 9 ;
+static const uint8_t P9N2__SM0_ATS_HOLD_AT_TDRMEM_UE_ESR = 10 ;
+static const uint8_t P9N2__SM0_ATS_HOLD_AT_TDRMEM_CE_ESR = 11 ;
+static const uint8_t P9N2__SM0_ATS_HOLD_RSPOUT_UE_ESR = 12 ;
+static const uint8_t P9N2__SM0_ATS_HOLD_RSPOUT_CE_ESR = 13 ;
+static const uint8_t P9N2__SM0_ATS_HOLD_TVT_PERR_ESR = 14 ;
+static const uint8_t P9N2__SM0_ATS_HOLD_IODA_ADDR_PERR_ESR = 15 ;
+static const uint8_t P9N2__SM0_ATS_HOLD_CTRLR_PERR_ESR = 16 ;
+static const uint8_t P9N2__SM0_ATS_HOLD_TOR_PERR_ESR = 17 ;
+static const uint8_t P9N2__SM0_ATS_HOLD_INVAL_IODA_TBL_SEL_ESR = 18 ;
+static const uint8_t P9N2__SM0_ATS_HOLD_ESR_RSVD_19 = 19 ;
+
+static const uint8_t P9N2__SM0_ATS_MASK_IDIAL = 0 ;
+static const uint8_t P9N2__SM0_ATS_MASK_IDIAL_LEN = 20 ;
+
+static const uint8_t P9N2__SM1_ATS_TCR_TCE_TIMEOUT = 10 ;
+static const uint8_t P9N2__SM1_ATS_TCR_TCE_TIMEOUT_LEN = 6 ;
+
+static const uint8_t P9N2_PEC_ATTN_INTERRUPT_REG_ATTN = 0 ;
+
+static const uint8_t P9N2_PU_BANK0_MCD_BOT_VALID = 0 ;
+static const uint8_t P9N2_PU_BANK0_MCD_BOT_CPG = 1 ;
+static const uint8_t P9N2_PU_BANK0_MCD_BOT_GRP_MBR_ID = 2 ;
+static const uint8_t P9N2_PU_BANK0_MCD_BOT_ALWAYS_RTY = 3 ;
+static const uint8_t P9N2_PU_BANK0_MCD_BOT_GRP_SIZE = 13 ;
+static const uint8_t P9N2_PU_BANK0_MCD_BOT_GRP_SIZE_LEN = 17 ;
+static const uint8_t P9N2_PU_BANK0_MCD_BOT_GRP_BASE = 33 ;
+static const uint8_t P9N2_PU_BANK0_MCD_BOT_GRP_BASE_LEN = 31 ;
+
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_BOT_VALID = 0 ;
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_BOT_CPG = 1 ;
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_BOT_GRP_MBR_ID = 2 ;
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_BOT_ALWAYS_RTY = 3 ;
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_BOT_GRP_SIZE = 13 ;
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_BOT_GRP_SIZE_LEN = 17 ;
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_BOT_GRP_BASE = 33 ;
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_BOT_GRP_BASE_LEN = 31 ;
+
+static const uint8_t P9N2_PU_BANK0_MCD_CHA_VALID = 0 ;
+static const uint8_t P9N2_PU_BANK0_MCD_CHA_CPG = 1 ;
+static const uint8_t P9N2_PU_BANK0_MCD_CHA_GRP_MBR_ID = 2 ;
+static const uint8_t P9N2_PU_BANK0_MCD_CHA_ALWAYS_RTY = 3 ;
+static const uint8_t P9N2_PU_BANK0_MCD_CHA_GRP_SIZE = 13 ;
+static const uint8_t P9N2_PU_BANK0_MCD_CHA_GRP_SIZE_LEN = 17 ;
+static const uint8_t P9N2_PU_BANK0_MCD_CHA_GRP_BASE = 33 ;
+static const uint8_t P9N2_PU_BANK0_MCD_CHA_GRP_BASE_LEN = 31 ;
+
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_CHA_VALID = 0 ;
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_CHA_CPG = 1 ;
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_CHA_GRP_MBR_ID = 2 ;
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_CHA_ALWAYS_RTY = 3 ;
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_CHA_GRP_SIZE = 13 ;
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_CHA_GRP_SIZE_LEN = 17 ;
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_CHA_GRP_BASE = 33 ;
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_CHA_GRP_BASE_LEN = 31 ;
+
+static const uint8_t P9N2_PU_BANK0_MCD_CMD_CHECK_CMDS = 0 ;
+static const uint8_t P9N2_PU_BANK0_MCD_CMD_CHECK_CMDS_LEN = 19 ;
+static const uint8_t P9N2_PU_BANK0_MCD_CMD_CHECK_CMDS_EN = 31 ;
+static const uint8_t P9N2_PU_BANK0_MCD_CMD_SET_CMDS = 32 ;
+static const uint8_t P9N2_PU_BANK0_MCD_CMD_SET_CMDS_LEN = 19 ;
+static const uint8_t P9N2_PU_BANK0_MCD_CMD_SET_CMDS_EN = 63 ;
+
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_CMD_CHECK_CMDS = 0 ;
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_CMD_CHECK_CMDS_LEN = 19 ;
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_CMD_CHECK_CMDS_EN = 31 ;
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_CMD_SET_CMDS = 32 ;
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_CMD_SET_CMDS_LEN = 19 ;
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_CMD_SET_CMDS_EN = 63 ;
+
+static const uint8_t P9N2_PU_BANK0_MCD_REC_ENABLE = 0 ;
+static const uint8_t P9N2_PU_BANK0_MCD_REC_DONE = 1 ;
+static const uint8_t P9N2_PU_BANK0_MCD_REC_CONTINUOUS = 2 ;
+static const uint8_t P9N2_PU_BANK0_MCD_REC_STATUS = 5 ;
+static const uint8_t P9N2_PU_BANK0_MCD_REC_PACE = 8 ;
+static const uint8_t P9N2_PU_BANK0_MCD_REC_PACE_LEN = 12 ;
+static const uint8_t P9N2_PU_BANK0_MCD_REC_ADDR_ERROR = 20 ;
+static const uint8_t P9N2_PU_BANK0_MCD_REC_ADDR = 21 ;
+static const uint8_t P9N2_PU_BANK0_MCD_REC_ADDR_LEN = 15 ;
+static const uint8_t P9N2_PU_BANK0_MCD_REC_RTY_COUNT = 40 ;
+static const uint8_t P9N2_PU_BANK0_MCD_REC_RTY_COUNT_LEN = 4 ;
+static const uint8_t P9N2_PU_BANK0_MCD_REC_VG_COUNT = 49 ;
+static const uint8_t P9N2_PU_BANK0_MCD_REC_VG_COUNT_LEN = 15 ;
+
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_REC_ENABLE = 0 ;
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_REC_DONE = 1 ;
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_REC_CONTINUOUS = 2 ;
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_REC_STATUS = 5 ;
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_REC_PACE = 8 ;
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_REC_PACE_LEN = 12 ;
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_REC_ADDR_ERROR = 20 ;
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_REC_ADDR = 21 ;
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_REC_ADDR_LEN = 15 ;
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_REC_RTY_COUNT = 40 ;
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_REC_RTY_COUNT_LEN = 4 ;
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_REC_VG_COUNT = 49 ;
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_REC_VG_COUNT_LEN = 15 ;
+
+static const uint8_t P9N2_PU_BANK0_MCD_RW_RDWR_ACCESS_EN = 0 ;
+static const uint8_t P9N2_PU_BANK0_MCD_RW_RDWR_WR_ENABLE = 1 ;
+static const uint8_t P9N2_PU_BANK0_MCD_RW_RDWR_REQ_PEND = 3 ;
+static const uint8_t P9N2_PU_BANK0_MCD_RW_RDWR_READ_STATUS = 4 ;
+static const uint8_t P9N2_PU_BANK0_MCD_RW_RDWR_WRITE_MODE = 5 ;
+static const uint8_t P9N2_PU_BANK0_MCD_RW_RDWR_WRITE_STATUS = 6 ;
+static const uint8_t P9N2_PU_BANK0_MCD_RW_RDWR_ADDR = 17 ;
+static const uint8_t P9N2_PU_BANK0_MCD_RW_RDWR_ADDR_LEN = 15 ;
+static const uint8_t P9N2_PU_BANK0_MCD_RW_RDWR_RDWR_DATA = 32 ;
+static const uint8_t P9N2_PU_BANK0_MCD_RW_RDWR_RDWR_DATA_LEN = 32 ;
+
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_RW_RDWR_ACCESS_EN = 0 ;
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_RW_RDWR_WR_ENABLE = 1 ;
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_RW_RDWR_REQ_PEND = 3 ;
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_RW_RDWR_READ_STATUS = 4 ;
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_RW_RDWR_WRITE_MODE = 5 ;
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_RW_RDWR_WRITE_STATUS = 6 ;
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_RW_RDWR_ADDR = 17 ;
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_RW_RDWR_ADDR_LEN = 15 ;
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_RW_RDWR_RDWR_DATA = 32 ;
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_RW_RDWR_RDWR_DATA_LEN = 32 ;
+
+static const uint8_t P9N2_PU_BANK0_MCD_STR_VALID = 0 ;
+static const uint8_t P9N2_PU_BANK0_MCD_STR_CPG = 1 ;
+static const uint8_t P9N2_PU_BANK0_MCD_STR_GRP_MBR_ID = 2 ;
+static const uint8_t P9N2_PU_BANK0_MCD_STR_ALWAYS_RTY = 3 ;
+static const uint8_t P9N2_PU_BANK0_MCD_STR_GRP_SIZE = 13 ;
+static const uint8_t P9N2_PU_BANK0_MCD_STR_GRP_SIZE_LEN = 17 ;
+static const uint8_t P9N2_PU_BANK0_MCD_STR_GRP_BASE = 33 ;
+static const uint8_t P9N2_PU_BANK0_MCD_STR_GRP_BASE_LEN = 31 ;
+
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_STR_VALID = 0 ;
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_STR_CPG = 1 ;
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_STR_GRP_MBR_ID = 2 ;
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_STR_ALWAYS_RTY = 3 ;
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_STR_GRP_SIZE = 13 ;
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_STR_GRP_SIZE_LEN = 17 ;
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_STR_GRP_BASE = 33 ;
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_STR_GRP_BASE_LEN = 31 ;
+
+static const uint8_t P9N2_PU_BANK0_MCD_TOP_VALID = 0 ;
+static const uint8_t P9N2_PU_BANK0_MCD_TOP_CPG = 1 ;
+static const uint8_t P9N2_PU_BANK0_MCD_TOP_GRP_MBR_ID = 2 ;
+static const uint8_t P9N2_PU_BANK0_MCD_TOP_ALWAYS_RTY = 3 ;
+static const uint8_t P9N2_PU_BANK0_MCD_TOP_GRP_SIZE = 13 ;
+static const uint8_t P9N2_PU_BANK0_MCD_TOP_GRP_SIZE_LEN = 17 ;
+static const uint8_t P9N2_PU_BANK0_MCD_TOP_GRP_BASE = 33 ;
+static const uint8_t P9N2_PU_BANK0_MCD_TOP_GRP_BASE_LEN = 31 ;
+
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_TOP_VALID = 0 ;
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_TOP_CPG = 1 ;
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_TOP_GRP_MBR_ID = 2 ;
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_TOP_ALWAYS_RTY = 3 ;
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_TOP_GRP_SIZE = 13 ;
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_TOP_GRP_SIZE_LEN = 17 ;
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_TOP_GRP_BASE = 33 ;
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_TOP_GRP_BASE_LEN = 31 ;
+
+static const uint8_t P9N2_PU_BANK0_MCD_VGC_AVAIL_GROUPS = 0 ;
+static const uint8_t P9N2_PU_BANK0_MCD_VGC_AVAIL_GROUPS_LEN = 16 ;
+static const uint8_t P9N2_PU_BANK0_MCD_VGC_FAILED_GROUPS = 16 ;
+static const uint8_t P9N2_PU_BANK0_MCD_VGC_FAILED_GROUPS_LEN = 16 ;
+static const uint8_t P9N2_PU_BANK0_MCD_VGC_4X4_MODE = 32 ;
+static const uint8_t P9N2_PU_BANK0_MCD_VGC_HANG_POLL_ENABLE = 33 ;
+static const uint8_t P9N2_PU_BANK0_MCD_VGC_RND_BACKOFF_ENABLE = 34 ;
+static const uint8_t P9N2_PU_BANK0_MCD_VGC_DROP_PRIORITY_MODE = 35 ;
+static const uint8_t P9N2_PU_BANK0_MCD_VGC_MASK_AGV_DISABLE_MODE = 36 ;
+static const uint8_t P9N2_PU_BANK0_MCD_VGC_XLATE_TO_ADDR_ID_ENABLE = 37 ;
+static const uint8_t P9N2_PU_BANK0_MCD_VGC_P8MODE_ENABLE = 38 ;
+static const uint8_t P9N2_PU_BANK0_MCD_VGC_EXT_ADDR_FAC_ENABLE = 39 ;
+static const uint8_t P9N2_PU_BANK0_MCD_VGC_EXT_ADDR_FAC_MASK = 40 ;
+static const uint8_t P9N2_PU_BANK0_MCD_VGC_EXT_ADDR_FAC_MASK_LEN = 7 ;
+static const uint8_t P9N2_PU_BANK0_MCD_VGC_EXT_ADDR_VEC_ENABLE = 47 ;
+static const uint8_t P9N2_PU_BANK0_MCD_VGC_EXT_ADDR_VEC_ENABLE_LEN = 2 ;
+static const uint8_t P9N2_PU_BANK0_MCD_VGC_CS_HW400693_DISABLE = 49 ;
+static const uint8_t P9N2_PU_BANK0_MCD_VGC_ENABLE_RCV_ADDR_DEBUG = 50 ;
+static const uint8_t P9N2_PU_BANK0_MCD_VGC_SPARE = 51 ;
+static const uint8_t P9N2_PU_BANK0_MCD_VGC_SPARE_LEN = 6 ;
+
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_VGC_AVAIL_GROUPS = 0 ;
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_VGC_AVAIL_GROUPS_LEN = 16 ;
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_VGC_FAILED_GROUPS = 16 ;
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_VGC_FAILED_GROUPS_LEN = 16 ;
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_VGC_4X4_MODE = 32 ;
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_VGC_HANG_POLL_ENABLE = 33 ;
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_VGC_RND_BACKOFF_ENABLE = 34 ;
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_VGC_DROP_PRIORITY_MODE = 35 ;
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_VGC_MASK_AGV_DISABLE_MODE = 36 ;
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_VGC_XLATE_TO_ADDR_ID_ENABLE = 37 ;
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_VGC_P8MODE_ENABLE = 38 ;
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_VGC_EXT_ADDR_FAC_ENABLE = 39 ;
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_VGC_EXT_ADDR_FAC_MASK = 40 ;
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_VGC_EXT_ADDR_FAC_MASK_LEN = 7 ;
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_VGC_EXT_ADDR_VEC_ENABLE = 47 ;
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_VGC_EXT_ADDR_VEC_ENABLE_LEN = 2 ;
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_VGC_CS_HW400693_DISABLE = 49 ;
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_VGC_ENABLE_RCV_ADDR_DEBUG = 50 ;
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_VGC_SPARE = 51 ;
+static const uint8_t P9N2_PU_MCD1_BANK0_MCD_VGC_SPARE_LEN = 6 ;
+
+static const uint8_t P9N2_PHB_BARE_REG_PE_MMIO_BAR0_EN = 0 ;
+static const uint8_t P9N2_PHB_BARE_REG_PE_MMIO_BAR1_EN = 1 ;
+static const uint8_t P9N2_PHB_BARE_REG_PE_PHB_BAR_EN = 2 ;
+static const uint8_t P9N2_PHB_BARE_REG_PE_INT_BAR_EN = 3 ;
+
+static const uint8_t P9N2_PEC_STACK0_BARE_REG_PE_MMIO_BAR0_EN = 0 ;
+static const uint8_t P9N2_PEC_STACK0_BARE_REG_PE_MMIO_BAR1_EN = 1 ;
+static const uint8_t P9N2_PEC_STACK0_BARE_REG_PE_PHB_BAR_EN = 2 ;
+static const uint8_t P9N2_PEC_STACK0_BARE_REG_PE_INT_BAR_EN = 3 ;
+
+static const uint8_t P9N2_PU_BCDE_CTL_STOP = 0 ;
+static const uint8_t P9N2_PU_BCDE_CTL_START = 1 ;
+
+static const uint8_t P9N2_PU_BCDE_OCIBAR_ADDR = 0 ;
+static const uint8_t P9N2_PU_BCDE_OCIBAR_ADDR_LEN = 25 ;
+
+static const uint8_t P9N2_PU_BCDE_PBADR_RESERVED_0_1 = 0 ;
+static const uint8_t P9N2_PU_BCDE_PBADR_RESERVED_0_1_LEN = 2 ;
+static const uint8_t P9N2_PU_BCDE_PBADR_PB_OFFSET = 2 ;
+static const uint8_t P9N2_PU_BCDE_PBADR_PB_OFFSET_LEN = 23 ;
+static const uint8_t P9N2_PU_BCDE_PBADR_RESERVED_25_26 = 25 ;
+static const uint8_t P9N2_PU_BCDE_PBADR_RESERVED_25_26_LEN = 2 ;
+static const uint8_t P9N2_PU_BCDE_PBADR_EXTADDR = 27 ;
+static const uint8_t P9N2_PU_BCDE_PBADR_EXTADDR_LEN = 14 ;
+static const uint8_t P9N2_PU_BCDE_PBADR_RESERVED_41_42 = 41 ;
+static const uint8_t P9N2_PU_BCDE_PBADR_RESERVED_41_42_LEN = 2 ;
+
+static const uint8_t P9N2_PU_BCDE_SET_RESERVED_0_1 = 0 ;
+static const uint8_t P9N2_PU_BCDE_SET_RESERVED_0_1_LEN = 2 ;
+static const uint8_t P9N2_PU_BCDE_SET_COPY_LENGTH = 2 ;
+static const uint8_t P9N2_PU_BCDE_SET_COPY_LENGTH_LEN = 6 ;
+
+static const uint8_t P9N2_PU_BCDE_STAT_RUNNING = 0 ;
+static const uint8_t P9N2_PU_BCDE_STAT_WAITING = 1 ;
+static const uint8_t P9N2_PU_BCDE_STAT_WRCMP = 2 ;
+static const uint8_t P9N2_PU_BCDE_STAT_WRCMP_LEN = 6 ;
+static const uint8_t P9N2_PU_BCDE_STAT_RDCMP = 14 ;
+static const uint8_t P9N2_PU_BCDE_STAT_RDCMP_LEN = 6 ;
+static const uint8_t P9N2_PU_BCDE_STAT_DEBUG = 20 ;
+static const uint8_t P9N2_PU_BCDE_STAT_DEBUG_LEN = 9 ;
+static const uint8_t P9N2_PU_BCDE_STAT_STOPPED = 29 ;
+static const uint8_t P9N2_PU_BCDE_STAT_ERROR = 30 ;
+static const uint8_t P9N2_PU_BCDE_STAT_DONE = 31 ;
+
+static const uint8_t P9N2_PU_BCUE_CTL_STOP = 0 ;
+static const uint8_t P9N2_PU_BCUE_CTL_START = 1 ;
+
+static const uint8_t P9N2_PU_BCUE_OCIBAR_ADDR = 0 ;
+static const uint8_t P9N2_PU_BCUE_OCIBAR_ADDR_LEN = 25 ;
+
+static const uint8_t P9N2_PU_BCUE_PBADR_RESERVED_0_1 = 0 ;
+static const uint8_t P9N2_PU_BCUE_PBADR_RESERVED_0_1_LEN = 2 ;
+static const uint8_t P9N2_PU_BCUE_PBADR_PB_OFFSET = 2 ;
+static const uint8_t P9N2_PU_BCUE_PBADR_PB_OFFSET_LEN = 23 ;
+static const uint8_t P9N2_PU_BCUE_PBADR_RESERVED_25_26 = 25 ;
+static const uint8_t P9N2_PU_BCUE_PBADR_RESERVED_25_26_LEN = 2 ;
+static const uint8_t P9N2_PU_BCUE_PBADR_EXTADDR = 27 ;
+static const uint8_t P9N2_PU_BCUE_PBADR_EXTADDR_LEN = 14 ;
+static const uint8_t P9N2_PU_BCUE_PBADR_RESERVED_41_42 = 41 ;
+static const uint8_t P9N2_PU_BCUE_PBADR_RESERVED_41_42_LEN = 2 ;
+
+static const uint8_t P9N2_PU_BCUE_SET_RESERVED_0_1 = 0 ;
+static const uint8_t P9N2_PU_BCUE_SET_RESERVED_0_1_LEN = 2 ;
+static const uint8_t P9N2_PU_BCUE_SET_COPY_LENGTH = 2 ;
+static const uint8_t P9N2_PU_BCUE_SET_COPY_LENGTH_LEN = 6 ;
+
+static const uint8_t P9N2_PU_BCUE_STAT_RUNNING = 0 ;
+static const uint8_t P9N2_PU_BCUE_STAT_WAITING = 1 ;
+static const uint8_t P9N2_PU_BCUE_STAT_WRCMP = 2 ;
+static const uint8_t P9N2_PU_BCUE_STAT_WRCMP_LEN = 6 ;
+static const uint8_t P9N2_PU_BCUE_STAT_RDCMP = 14 ;
+static const uint8_t P9N2_PU_BCUE_STAT_RDCMP_LEN = 6 ;
+static const uint8_t P9N2_PU_BCUE_STAT_DEBUG = 20 ;
+static const uint8_t P9N2_PU_BCUE_STAT_DEBUG_LEN = 9 ;
+static const uint8_t P9N2_PU_BCUE_STAT_STOPPED = 29 ;
+static const uint8_t P9N2_PU_BCUE_STAT_ERROR = 30 ;
+static const uint8_t P9N2_PU_BCUE_STAT_DONE = 31 ;
+
+static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_00_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_00_CONFIG_WILDCARD = 1 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_00_CONFIG_RESERVED = 2 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_00_CONFIG_RESERVED_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_00_CONFIG_PE = 4 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_00_CONFIG_PE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_00_CONFIG_BDF = 8 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_00_CONFIG_BDF_LEN = 16 ;
+
+static const uint8_t P9N2_PU_BDF2PE_00_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_BDF2PE_00_CONFIG_RESERVED = 1 ;
+static const uint8_t P9N2_PU_BDF2PE_00_CONFIG_RESERVED_LEN = 3 ;
+static const uint8_t P9N2_PU_BDF2PE_00_CONFIG_PE = 4 ;
+static const uint8_t P9N2_PU_BDF2PE_00_CONFIG_PE_LEN = 4 ;
+static const uint8_t P9N2_PU_BDF2PE_00_CONFIG_BDF = 8 ;
+static const uint8_t P9N2_PU_BDF2PE_00_CONFIG_BDF_LEN = 16 ;
+
+static const uint8_t P9N2_NV_BDF2PE_00_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_NV_BDF2PE_00_CONFIG_WILDCARD = 1 ;
+static const uint8_t P9N2_NV_BDF2PE_00_CONFIG_RESERVED = 2 ;
+static const uint8_t P9N2_NV_BDF2PE_00_CONFIG_RESERVED_LEN = 2 ;
+static const uint8_t P9N2_NV_BDF2PE_00_CONFIG_PE = 4 ;
+static const uint8_t P9N2_NV_BDF2PE_00_CONFIG_PE_LEN = 4 ;
+static const uint8_t P9N2_NV_BDF2PE_00_CONFIG_BDF = 8 ;
+static const uint8_t P9N2_NV_BDF2PE_00_CONFIG_BDF_LEN = 16 ;
+
+static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_01_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_01_CONFIG_RESERVED = 1 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_01_CONFIG_RESERVED_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_01_CONFIG_PE = 4 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_01_CONFIG_PE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_01_CONFIG_BDF = 8 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_01_CONFIG_BDF_LEN = 16 ;
+
+static const uint8_t P9N2_PU_BDF2PE_01_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_BDF2PE_01_CONFIG_RESERVED = 1 ;
+static const uint8_t P9N2_PU_BDF2PE_01_CONFIG_RESERVED_LEN = 3 ;
+static const uint8_t P9N2_PU_BDF2PE_01_CONFIG_PE = 4 ;
+static const uint8_t P9N2_PU_BDF2PE_01_CONFIG_PE_LEN = 4 ;
+static const uint8_t P9N2_PU_BDF2PE_01_CONFIG_BDF = 8 ;
+static const uint8_t P9N2_PU_BDF2PE_01_CONFIG_BDF_LEN = 16 ;
+
+static const uint8_t P9N2_NV_BDF2PE_01_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_NV_BDF2PE_01_CONFIG_RESERVED = 1 ;
+static const uint8_t P9N2_NV_BDF2PE_01_CONFIG_RESERVED_LEN = 3 ;
+static const uint8_t P9N2_NV_BDF2PE_01_CONFIG_PE = 4 ;
+static const uint8_t P9N2_NV_BDF2PE_01_CONFIG_PE_LEN = 4 ;
+static const uint8_t P9N2_NV_BDF2PE_01_CONFIG_BDF = 8 ;
+static const uint8_t P9N2_NV_BDF2PE_01_CONFIG_BDF_LEN = 16 ;
+
+static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_02_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_02_CONFIG_RESERVED = 1 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_02_CONFIG_RESERVED_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_02_CONFIG_PE = 4 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_02_CONFIG_PE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_02_CONFIG_BDF = 8 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_02_CONFIG_BDF_LEN = 16 ;
+
+static const uint8_t P9N2_PU_BDF2PE_02_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_BDF2PE_02_CONFIG_RESERVED = 1 ;
+static const uint8_t P9N2_PU_BDF2PE_02_CONFIG_RESERVED_LEN = 3 ;
+static const uint8_t P9N2_PU_BDF2PE_02_CONFIG_PE = 4 ;
+static const uint8_t P9N2_PU_BDF2PE_02_CONFIG_PE_LEN = 4 ;
+static const uint8_t P9N2_PU_BDF2PE_02_CONFIG_BDF = 8 ;
+static const uint8_t P9N2_PU_BDF2PE_02_CONFIG_BDF_LEN = 16 ;
+
+static const uint8_t P9N2_NV_BDF2PE_02_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_NV_BDF2PE_02_CONFIG_RESERVED = 1 ;
+static const uint8_t P9N2_NV_BDF2PE_02_CONFIG_RESERVED_LEN = 3 ;
+static const uint8_t P9N2_NV_BDF2PE_02_CONFIG_PE = 4 ;
+static const uint8_t P9N2_NV_BDF2PE_02_CONFIG_PE_LEN = 4 ;
+static const uint8_t P9N2_NV_BDF2PE_02_CONFIG_BDF = 8 ;
+static const uint8_t P9N2_NV_BDF2PE_02_CONFIG_BDF_LEN = 16 ;
+
+static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_10_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_10_CONFIG_WILDCARD = 1 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_10_CONFIG_RESERVED = 2 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_10_CONFIG_RESERVED_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_10_CONFIG_PE = 4 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_10_CONFIG_PE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_10_CONFIG_BDF = 8 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_10_CONFIG_BDF_LEN = 16 ;
+
+static const uint8_t P9N2_PU_BDF2PE_10_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_BDF2PE_10_CONFIG_RESERVED = 1 ;
+static const uint8_t P9N2_PU_BDF2PE_10_CONFIG_RESERVED_LEN = 3 ;
+static const uint8_t P9N2_PU_BDF2PE_10_CONFIG_PE = 4 ;
+static const uint8_t P9N2_PU_BDF2PE_10_CONFIG_PE_LEN = 4 ;
+static const uint8_t P9N2_PU_BDF2PE_10_CONFIG_BDF = 8 ;
+static const uint8_t P9N2_PU_BDF2PE_10_CONFIG_BDF_LEN = 16 ;
+
+static const uint8_t P9N2_NV_BDF2PE_10_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_NV_BDF2PE_10_CONFIG_WILDCARD = 1 ;
+static const uint8_t P9N2_NV_BDF2PE_10_CONFIG_RESERVED = 2 ;
+static const uint8_t P9N2_NV_BDF2PE_10_CONFIG_RESERVED_LEN = 2 ;
+static const uint8_t P9N2_NV_BDF2PE_10_CONFIG_PE = 4 ;
+static const uint8_t P9N2_NV_BDF2PE_10_CONFIG_PE_LEN = 4 ;
+static const uint8_t P9N2_NV_BDF2PE_10_CONFIG_BDF = 8 ;
+static const uint8_t P9N2_NV_BDF2PE_10_CONFIG_BDF_LEN = 16 ;
+
+static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_11_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_11_CONFIG_RESERVED = 1 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_11_CONFIG_RESERVED_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_11_CONFIG_PE = 4 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_11_CONFIG_PE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_11_CONFIG_BDF = 8 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_11_CONFIG_BDF_LEN = 16 ;
+
+static const uint8_t P9N2_PU_BDF2PE_11_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_BDF2PE_11_CONFIG_RESERVED = 1 ;
+static const uint8_t P9N2_PU_BDF2PE_11_CONFIG_RESERVED_LEN = 3 ;
+static const uint8_t P9N2_PU_BDF2PE_11_CONFIG_PE = 4 ;
+static const uint8_t P9N2_PU_BDF2PE_11_CONFIG_PE_LEN = 4 ;
+static const uint8_t P9N2_PU_BDF2PE_11_CONFIG_BDF = 8 ;
+static const uint8_t P9N2_PU_BDF2PE_11_CONFIG_BDF_LEN = 16 ;
+
+static const uint8_t P9N2_NV_BDF2PE_11_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_NV_BDF2PE_11_CONFIG_RESERVED = 1 ;
+static const uint8_t P9N2_NV_BDF2PE_11_CONFIG_RESERVED_LEN = 3 ;
+static const uint8_t P9N2_NV_BDF2PE_11_CONFIG_PE = 4 ;
+static const uint8_t P9N2_NV_BDF2PE_11_CONFIG_PE_LEN = 4 ;
+static const uint8_t P9N2_NV_BDF2PE_11_CONFIG_BDF = 8 ;
+static const uint8_t P9N2_NV_BDF2PE_11_CONFIG_BDF_LEN = 16 ;
+
+static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_12_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_12_CONFIG_RESERVED = 1 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_12_CONFIG_RESERVED_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_12_CONFIG_PE = 4 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_12_CONFIG_PE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_12_CONFIG_BDF = 8 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_BDF2PE_12_CONFIG_BDF_LEN = 16 ;
+
+static const uint8_t P9N2_PU_BDF2PE_12_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_BDF2PE_12_CONFIG_RESERVED = 1 ;
+static const uint8_t P9N2_PU_BDF2PE_12_CONFIG_RESERVED_LEN = 3 ;
+static const uint8_t P9N2_PU_BDF2PE_12_CONFIG_PE = 4 ;
+static const uint8_t P9N2_PU_BDF2PE_12_CONFIG_PE_LEN = 4 ;
+static const uint8_t P9N2_PU_BDF2PE_12_CONFIG_BDF = 8 ;
+static const uint8_t P9N2_PU_BDF2PE_12_CONFIG_BDF_LEN = 16 ;
+
+static const uint8_t P9N2_NV_BDF2PE_12_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_NV_BDF2PE_12_CONFIG_RESERVED = 1 ;
+static const uint8_t P9N2_NV_BDF2PE_12_CONFIG_RESERVED_LEN = 3 ;
+static const uint8_t P9N2_NV_BDF2PE_12_CONFIG_PE = 4 ;
+static const uint8_t P9N2_NV_BDF2PE_12_CONFIG_PE_LEN = 4 ;
+static const uint8_t P9N2_NV_BDF2PE_12_CONFIG_BDF = 8 ;
+static const uint8_t P9N2_NV_BDF2PE_12_CONFIG_BDF_LEN = 16 ;
+
+static const uint8_t P9N2_PU_BDF2PE_20_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_BDF2PE_20_CONFIG_RESERVED = 1 ;
+static const uint8_t P9N2_PU_BDF2PE_20_CONFIG_RESERVED_LEN = 3 ;
+static const uint8_t P9N2_PU_BDF2PE_20_CONFIG_PE = 4 ;
+static const uint8_t P9N2_PU_BDF2PE_20_CONFIG_PE_LEN = 4 ;
+static const uint8_t P9N2_PU_BDF2PE_20_CONFIG_BDF = 8 ;
+static const uint8_t P9N2_PU_BDF2PE_20_CONFIG_BDF_LEN = 16 ;
+
+static const uint8_t P9N2_PU_BDF2PE_21_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_BDF2PE_21_CONFIG_RESERVED = 1 ;
+static const uint8_t P9N2_PU_BDF2PE_21_CONFIG_RESERVED_LEN = 3 ;
+static const uint8_t P9N2_PU_BDF2PE_21_CONFIG_PE = 4 ;
+static const uint8_t P9N2_PU_BDF2PE_21_CONFIG_PE_LEN = 4 ;
+static const uint8_t P9N2_PU_BDF2PE_21_CONFIG_BDF = 8 ;
+static const uint8_t P9N2_PU_BDF2PE_21_CONFIG_BDF_LEN = 16 ;
+
+static const uint8_t P9N2_PU_BDF2PE_22_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_BDF2PE_22_CONFIG_RESERVED = 1 ;
+static const uint8_t P9N2_PU_BDF2PE_22_CONFIG_RESERVED_LEN = 3 ;
+static const uint8_t P9N2_PU_BDF2PE_22_CONFIG_PE = 4 ;
+static const uint8_t P9N2_PU_BDF2PE_22_CONFIG_PE_LEN = 4 ;
+static const uint8_t P9N2_PU_BDF2PE_22_CONFIG_BDF = 8 ;
+static const uint8_t P9N2_PU_BDF2PE_22_CONFIG_BDF_LEN = 16 ;
+
+static const uint8_t P9N2_PU_BDF2PE_30_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_BDF2PE_30_CONFIG_RESERVED = 1 ;
+static const uint8_t P9N2_PU_BDF2PE_30_CONFIG_RESERVED_LEN = 3 ;
+static const uint8_t P9N2_PU_BDF2PE_30_CONFIG_PE = 4 ;
+static const uint8_t P9N2_PU_BDF2PE_30_CONFIG_PE_LEN = 4 ;
+static const uint8_t P9N2_PU_BDF2PE_30_CONFIG_BDF = 8 ;
+static const uint8_t P9N2_PU_BDF2PE_30_CONFIG_BDF_LEN = 16 ;
+
+static const uint8_t P9N2_PU_BDF2PE_31_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_BDF2PE_31_CONFIG_RESERVED = 1 ;
+static const uint8_t P9N2_PU_BDF2PE_31_CONFIG_RESERVED_LEN = 3 ;
+static const uint8_t P9N2_PU_BDF2PE_31_CONFIG_PE = 4 ;
+static const uint8_t P9N2_PU_BDF2PE_31_CONFIG_PE_LEN = 4 ;
+static const uint8_t P9N2_PU_BDF2PE_31_CONFIG_BDF = 8 ;
+static const uint8_t P9N2_PU_BDF2PE_31_CONFIG_BDF_LEN = 16 ;
+
+static const uint8_t P9N2_PU_BDF2PE_32_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_BDF2PE_32_CONFIG_RESERVED = 1 ;
+static const uint8_t P9N2_PU_BDF2PE_32_CONFIG_RESERVED_LEN = 3 ;
+static const uint8_t P9N2_PU_BDF2PE_32_CONFIG_PE = 4 ;
+static const uint8_t P9N2_PU_BDF2PE_32_CONFIG_PE_LEN = 4 ;
+static const uint8_t P9N2_PU_BDF2PE_32_CONFIG_BDF = 8 ;
+static const uint8_t P9N2_PU_BDF2PE_32_CONFIG_BDF_LEN = 16 ;
+
+static const uint8_t P9N2_PU_BDF2PE_40_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_BDF2PE_40_CONFIG_RESERVED = 1 ;
+static const uint8_t P9N2_PU_BDF2PE_40_CONFIG_RESERVED_LEN = 3 ;
+static const uint8_t P9N2_PU_BDF2PE_40_CONFIG_PE = 4 ;
+static const uint8_t P9N2_PU_BDF2PE_40_CONFIG_PE_LEN = 4 ;
+static const uint8_t P9N2_PU_BDF2PE_40_CONFIG_BDF = 8 ;
+static const uint8_t P9N2_PU_BDF2PE_40_CONFIG_BDF_LEN = 16 ;
+
+static const uint8_t P9N2_PU_BDF2PE_41_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_BDF2PE_41_CONFIG_RESERVED = 1 ;
+static const uint8_t P9N2_PU_BDF2PE_41_CONFIG_RESERVED_LEN = 3 ;
+static const uint8_t P9N2_PU_BDF2PE_41_CONFIG_PE = 4 ;
+static const uint8_t P9N2_PU_BDF2PE_41_CONFIG_PE_LEN = 4 ;
+static const uint8_t P9N2_PU_BDF2PE_41_CONFIG_BDF = 8 ;
+static const uint8_t P9N2_PU_BDF2PE_41_CONFIG_BDF_LEN = 16 ;
+
+static const uint8_t P9N2_PU_BDF2PE_42_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_BDF2PE_42_CONFIG_RESERVED = 1 ;
+static const uint8_t P9N2_PU_BDF2PE_42_CONFIG_RESERVED_LEN = 3 ;
+static const uint8_t P9N2_PU_BDF2PE_42_CONFIG_PE = 4 ;
+static const uint8_t P9N2_PU_BDF2PE_42_CONFIG_PE_LEN = 4 ;
+static const uint8_t P9N2_PU_BDF2PE_42_CONFIG_BDF = 8 ;
+static const uint8_t P9N2_PU_BDF2PE_42_CONFIG_BDF_LEN = 16 ;
+
+static const uint8_t P9N2_PU_BDF2PE_50_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_BDF2PE_50_CONFIG_RESERVED = 1 ;
+static const uint8_t P9N2_PU_BDF2PE_50_CONFIG_RESERVED_LEN = 3 ;
+static const uint8_t P9N2_PU_BDF2PE_50_CONFIG_PE = 4 ;
+static const uint8_t P9N2_PU_BDF2PE_50_CONFIG_PE_LEN = 4 ;
+static const uint8_t P9N2_PU_BDF2PE_50_CONFIG_BDF = 8 ;
+static const uint8_t P9N2_PU_BDF2PE_50_CONFIG_BDF_LEN = 16 ;
+
+static const uint8_t P9N2__DAT_BDF2PE_51_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2__DAT_BDF2PE_51_CONFIG_RESERVED = 1 ;
+static const uint8_t P9N2__DAT_BDF2PE_51_CONFIG_RESERVED_LEN = 3 ;
+static const uint8_t P9N2__DAT_BDF2PE_51_CONFIG_PE = 4 ;
+static const uint8_t P9N2__DAT_BDF2PE_51_CONFIG_PE_LEN = 4 ;
+static const uint8_t P9N2__DAT_BDF2PE_51_CONFIG_BDF = 8 ;
+static const uint8_t P9N2__DAT_BDF2PE_51_CONFIG_BDF_LEN = 16 ;
+
+static const uint8_t P9N2__DAT_BDF2PE_52_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2__DAT_BDF2PE_52_CONFIG_RESERVED = 1 ;
+static const uint8_t P9N2__DAT_BDF2PE_52_CONFIG_RESERVED_LEN = 3 ;
+static const uint8_t P9N2__DAT_BDF2PE_52_CONFIG_PE = 4 ;
+static const uint8_t P9N2__DAT_BDF2PE_52_CONFIG_PE_LEN = 4 ;
+static const uint8_t P9N2__DAT_BDF2PE_52_CONFIG_BDF = 8 ;
+static const uint8_t P9N2__DAT_BDF2PE_52_CONFIG_BDF_LEN = 16 ;
+
+static const uint8_t P9N2_PEC_BIST_TC_START_TEST_DC = 0 ;
+static const uint8_t P9N2_PEC_BIST_TC_SRAM_ABIST_MODE_DC = 1 ;
+static const uint8_t P9N2_PEC_BIST_TC_EDRAM_ABIST_MODE_DC = 2 ;
+static const uint8_t P9N2_PEC_BIST_TC_IOBIST_MODE_DC = 3 ;
+static const uint8_t P9N2_PEC_BIST_PERV = 4 ;
+static const uint8_t P9N2_PEC_BIST_UNIT1 = 5 ;
+static const uint8_t P9N2_PEC_BIST_UNIT2 = 6 ;
+static const uint8_t P9N2_PEC_BIST_UNIT3 = 7 ;
+static const uint8_t P9N2_PEC_BIST_UNIT4 = 8 ;
+static const uint8_t P9N2_PEC_BIST_UNIT5 = 9 ;
+static const uint8_t P9N2_PEC_BIST_UNIT6 = 10 ;
+static const uint8_t P9N2_PEC_BIST_UNIT7 = 11 ;
+static const uint8_t P9N2_PEC_BIST_UNIT8 = 12 ;
+static const uint8_t P9N2_PEC_BIST_UNIT9 = 13 ;
+static const uint8_t P9N2_PEC_BIST_UNIT10 = 14 ;
+static const uint8_t P9N2_PEC_BIST_STROBE_WINDOW_EN = 48 ;
+
+static const uint8_t P9N2_CAPP_CAPP_EPOCH_AND_RECOVERY_TMR_CONTROL_TIMER_ENABLE = 1 ;
+static const uint8_t P9N2_CAPP_CAPP_EPOCH_AND_RECOVERY_TMR_CONTROL_TIMER_PERIOD_MASK = 48 ;
+static const uint8_t P9N2_CAPP_CAPP_EPOCH_AND_RECOVERY_TMR_CONTROL_TIMER_PERIOD_MASK_LEN = 16 ;
+
+static const uint8_t P9N2_CAPP_CAPP_ERR_STATUS_CONTROL_ERROR_RECOVERY_INITIATED = 0 ;
+static const uint8_t P9N2_CAPP_CAPP_ERR_STATUS_CONTROL_ERROR_RECOVERY_COMPLETE = 1 ;
+static const uint8_t P9N2_CAPP_CAPP_ERR_STATUS_CONTROL_TLBI_PSL_DEAD = 3 ;
+static const uint8_t P9N2_CAPP_CAPP_ERR_STATUS_CONTROL_TLBI_FENCE = 4 ;
+static const uint8_t P9N2_CAPP_CAPP_ERR_STATUS_CONTROL_RECOVERY_FAILED = 5 ;
+static const uint8_t P9N2_CAPP_CAPP_ERR_STATUS_CONTROL_RTAGFLUSH_FAILED = 6 ;
+static const uint8_t P9N2_CAPP_CAPP_ERR_STATUS_CONTROL_PRECISE_DIR_FLUSH_FAILED = 7 ;
+static const uint8_t P9N2_CAPP_CAPP_ERR_STATUS_CONTROL_COURSE_DIR_FLUSH_FAILED = 8 ;
+static const uint8_t P9N2_CAPP_CAPP_ERR_STATUS_CONTROL_RECOVERY_HANG_DETECTED = 9 ;
+static const uint8_t P9N2_CAPP_CAPP_ERR_STATUS_CONTROL_EPOCH_VALUE = 10 ;
+static const uint8_t P9N2_CAPP_CAPP_ERR_STATUS_CONTROL_EPOCH_VALUE_LEN = 2 ;
+static const uint8_t P9N2_CAPP_CAPP_ERR_STATUS_CONTROL_FORCE_QUIESCE = 14 ;
+static const uint8_t P9N2_CAPP_CAPP_ERR_STATUS_CONTROL_QUIESCE_DONE = 15 ;
+
+static const uint8_t P9N2_PEC_CC_ATOMIC_LOCK_REG_ENABLE = 0 ;
+static const uint8_t P9N2_PEC_CC_ATOMIC_LOCK_REG_ID = 1 ;
+static const uint8_t P9N2_PEC_CC_ATOMIC_LOCK_REG_ID_LEN = 4 ;
+static const uint8_t P9N2_PEC_CC_ATOMIC_LOCK_REG_ACTIVITY = 8 ;
+static const uint8_t P9N2_PEC_CC_ATOMIC_LOCK_REG_ACTIVITY_LEN = 8 ;
+
+static const uint8_t P9N2_PEC_CC_PROTECT_MODE_REG_READ_ENABLE = 0 ;
+static const uint8_t P9N2_PEC_CC_PROTECT_MODE_REG_WRITE_ENABLE = 1 ;
+
+static const uint8_t P9N2_PU_NPU2_NTL1_CERR_ECC_FIRST_BITS = 10 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CERR_ECC_FIRST_BITS_LEN = 54 ;
+
+static const uint8_t P9N2_PU_NPU2_NTL1_CERR_ECC_HOLD_IDIAL_PT_UE = 10 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CERR_ECC_HOLD_IDIAL_PT_UE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CERR_ECC_HOLD_IDIAL_PR_UE = 14 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CERR_ECC_HOLD_IDIAL_PR_UE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CERR_ECC_HOLD_IDIAL_BR_UE = 18 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CERR_ECC_HOLD_IDIAL_BR_UE_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CERR_ECC_HOLD_IDIAL_IR_UE = 20 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CERR_ECC_HOLD_IDIAL_IR_UE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CERR_ECC_HOLD_IDIAL_OR_UE = 24 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CERR_ECC_HOLD_IDIAL_OR_UE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CERR_ECC_HOLD_IDIAL_PT_SUE = 28 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CERR_ECC_HOLD_IDIAL_PT_SUE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CERR_ECC_HOLD_IDIAL_PR_SUE = 32 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CERR_ECC_HOLD_IDIAL_PR_SUE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CERR_ECC_HOLD_IDIAL_BR_SUE = 36 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CERR_ECC_HOLD_IDIAL_BR_SUE_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CERR_ECC_HOLD_IDIAL_IR_SUE = 38 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CERR_ECC_HOLD_IDIAL_IR_SUE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CERR_ECC_HOLD_IDIAL_OR_SUE = 42 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CERR_ECC_HOLD_IDIAL_OR_SUE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CERR_ECC_HOLD_IDIAL_PT_CE = 46 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CERR_ECC_HOLD_IDIAL_PT_CE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CERR_ECC_HOLD_IDIAL_PR_CE = 50 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CERR_ECC_HOLD_IDIAL_PR_CE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CERR_ECC_HOLD_IDIAL_BR_CE = 54 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CERR_ECC_HOLD_IDIAL_BR_CE_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CERR_ECC_HOLD_IDIAL_IR_CE = 56 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CERR_ECC_HOLD_IDIAL_IR_CE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CERR_ECC_HOLD_IDIAL_OR_CE = 60 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CERR_ECC_HOLD_IDIAL_OR_CE_LEN = 4 ;
+
+static const uint8_t P9N2_PU_NPU2_NTL1_CERR_ECC_MASK_BITS = 10 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CERR_ECC_MASK_BITS_LEN = 54 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_1 = 1 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_2 = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_3 = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_4 = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_5 = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_6 = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_7 = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_8 = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_9 = 9 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_10 = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_11 = 11 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_12 = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_13 = 13 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_14 = 14 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_15 = 15 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_16 = 16 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_17 = 17 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_18 = 18 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_19 = 19 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_20 = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_21 = 21 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_22 = 22 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_23 = 23 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_0 = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_1 = 25 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_2 = 26 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_3 = 27 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_4 = 28 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_5 = 29 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_6 = 30 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_7 = 31 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_0 = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_1 = 33 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_2 = 34 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_3 = 35 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_0 = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_1 = 37 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_2 = 38 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_3 = 39 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_4 = 40 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_5 = 41 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_6 = 42 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_7 = 43 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_REG_0 = 44 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_REG_1 = 45 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_REG_2 = 46 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_REG_3 = 47 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_0 = 48 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_1 = 49 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_2 = 50 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_3 = 51 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_4 = 52 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_5 = 53 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_6 = 54 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_7 = 55 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_8 = 56 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_9 = 57 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_10 = 58 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_11 = 59 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_12 = 60 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_13 = 61 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_14 = 62 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_15 = 63 ;
+
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0 = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_1 = 1 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_2 = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_3 = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_4 = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_5 = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_6 = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_7 = 7 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_8 = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_9 = 9 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_10 = 10 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_11 = 11 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_12 = 12 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_13 = 13 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_14 = 14 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_15 = 15 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_16 = 16 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_17 = 17 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_18 = 18 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_19 = 19 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_20 = 20 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_21 = 21 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_22 = 22 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_23 = 23 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_0 = 24 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_1 = 25 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_2 = 26 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_3 = 27 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_4 = 28 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_5 = 29 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_6 = 30 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_7 = 31 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_0 = 32 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_1 = 33 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_2 = 34 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_3 = 35 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_0 = 36 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_1 = 37 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_2 = 38 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_3 = 39 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_4 = 40 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_5 = 41 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_6 = 42 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_7 = 43 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_REG_0 = 44 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_REG_1 = 45 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_REG_2 = 46 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_REG_3 = 47 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_0 = 48 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_1 = 49 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_2 = 50 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_3 = 51 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_4 = 52 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_5 = 53 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_6 = 54 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_7 = 55 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_8 = 56 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_9 = 57 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_10 = 58 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_11 = 59 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_12 = 60 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_13 = 61 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_14 = 62 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_15 = 63 ;
+
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_0 = 0 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_1 = 1 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_2 = 2 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_3 = 3 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_4 = 4 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_5 = 5 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_6 = 6 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_7 = 7 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_0 = 8 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_1 = 9 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_2 = 10 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_3 = 11 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_4 = 12 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_5 = 13 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_6 = 14 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_7 = 15 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_8 = 16 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_9 = 17 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_10 = 18 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_11 = 19 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_12 = 20 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_13 = 21 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_14 = 22 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_15 = 23 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_16 = 24 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_17 = 25 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_18 = 26 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_19 = 27 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_OCR_0 = 28 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_OCR_1 = 29 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_OCR_2 = 30 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_OCR_3 = 31 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_OCR_4 = 32 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_OCR_5 = 33 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_OCR_6 = 34 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_OCR_7 = 35 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_0 = 36 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_1 = 37 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_2 = 38 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_3 = 39 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_4 = 40 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_5 = 41 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_6 = 42 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_7 = 43 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_0 = 44 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_1 = 45 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_2 = 46 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_3 = 47 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_4 = 48 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_5 = 49 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_6 = 50 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_7 = 51 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_REG_0 = 52 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_REG_1 = 53 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_REG_2 = 54 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_REG_3 = 55 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_DUE_0 = 56 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_DUE_1 = 57 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_DUE_2 = 58 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_DUE_3 = 59 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_PEF_0 = 60 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_PEF_1 = 61 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_PEF_2 = 62 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST0_IDIAL_CTL_FIRST_PEF_3 = 63 ;
+
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0 = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_1 = 1 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_2 = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_3 = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_4 = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_5 = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_6 = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_7 = 7 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_8 = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_9 = 9 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_10 = 10 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_11 = 11 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_12 = 12 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_13 = 13 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_14 = 14 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_15 = 15 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_16 = 16 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_17 = 17 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_18 = 18 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_19 = 19 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_20 = 20 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_21 = 21 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_22 = 22 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_23 = 23 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_0 = 24 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_1 = 25 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_2 = 26 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_3 = 27 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_4 = 28 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_5 = 29 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_6 = 30 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_7 = 31 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_0 = 32 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_1 = 33 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_2 = 34 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_3 = 35 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_0 = 36 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_1 = 37 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_2 = 38 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_3 = 39 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_4 = 40 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_5 = 41 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_6 = 42 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_7 = 43 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_REG_0 = 44 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_REG_1 = 45 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_REG_2 = 46 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_REG_3 = 47 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_0 = 48 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_1 = 49 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_2 = 50 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_3 = 51 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_4 = 52 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_5 = 53 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_6 = 54 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_7 = 55 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_8 = 56 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_9 = 57 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_10 = 58 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_11 = 59 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_12 = 60 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_13 = 61 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_14 = 62 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_15 = 63 ;
+
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0 = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_1 = 1 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_2 = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_3 = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_4 = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_5 = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_6 = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_7 = 7 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_8 = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_9 = 9 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_10 = 10 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_11 = 11 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_12 = 12 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_13 = 13 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_14 = 14 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_15 = 15 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_16 = 16 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_17 = 17 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_18 = 18 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_19 = 19 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_20 = 20 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_21 = 21 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_22 = 22 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_23 = 23 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_0 = 24 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_1 = 25 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_2 = 26 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_3 = 27 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_4 = 28 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_5 = 29 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_6 = 30 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_7 = 31 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_0 = 32 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_1 = 33 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_2 = 34 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_3 = 35 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_0 = 36 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_1 = 37 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_2 = 38 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_3 = 39 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_4 = 40 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_5 = 41 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_6 = 42 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_7 = 43 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_REG_0 = 44 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_REG_1 = 45 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_REG_2 = 46 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_REG_3 = 47 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_0 = 48 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_1 = 49 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_2 = 50 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_3 = 51 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_4 = 52 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_5 = 53 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_6 = 54 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_7 = 55 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_8 = 56 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_9 = 57 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_10 = 58 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_11 = 59 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_12 = 60 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_13 = 61 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_14 = 62 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_15 = 63 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_1 = 1 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_2 = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_3 = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_4 = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_5 = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_6 = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_7 = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_8 = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_9 = 9 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_10 = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_11 = 11 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_12 = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_13 = 13 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_14 = 14 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_15 = 15 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_16 = 16 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_17 = 17 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_18 = 18 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_19 = 19 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_20 = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_21 = 21 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_22 = 22 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_23 = 23 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_0 = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_1 = 25 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_2 = 26 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_3 = 27 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_4 = 28 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_5 = 29 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_6 = 30 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_7 = 31 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_0 = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_1 = 33 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_2 = 34 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_3 = 35 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_0 = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_1 = 37 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_2 = 38 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_3 = 39 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_4 = 40 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_5 = 41 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_6 = 42 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_7 = 43 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_REG_0 = 44 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_REG_1 = 45 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_REG_2 = 46 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_REG_3 = 47 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_0 = 48 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_1 = 49 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_2 = 50 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_3 = 51 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_4 = 52 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_5 = 53 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_6 = 54 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_7 = 55 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_8 = 56 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_9 = 57 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_10 = 58 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_11 = 59 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_12 = 60 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_13 = 61 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_14 = 62 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_15 = 63 ;
+
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0 = 0 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_1 = 1 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_2 = 2 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_3 = 3 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_4 = 4 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_5 = 5 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_6 = 6 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_7 = 7 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_8 = 8 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_9 = 9 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_10 = 10 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_11 = 11 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_12 = 12 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_13 = 13 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_14 = 14 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_15 = 15 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_16 = 16 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_17 = 17 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_18 = 18 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_19 = 19 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_20 = 20 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_21 = 21 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_22 = 22 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_23 = 23 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_0 = 24 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_1 = 25 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_2 = 26 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_3 = 27 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_4 = 28 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_5 = 29 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_6 = 30 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_7 = 31 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_0 = 32 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_1 = 33 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_2 = 34 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_3 = 35 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_0 = 36 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_1 = 37 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_2 = 38 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_3 = 39 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_4 = 40 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_5 = 41 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_6 = 42 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_7 = 43 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_REG_0 = 44 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_REG_1 = 45 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_REG_2 = 46 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_REG_3 = 47 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_0 = 48 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_1 = 49 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_2 = 50 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_3 = 51 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_4 = 52 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_5 = 53 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_6 = 54 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_7 = 55 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_8 = 56 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_9 = 57 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_10 = 58 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_11 = 59 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_12 = 60 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_13 = 61 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_14 = 62 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_15 = 63 ;
+
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0 = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_1 = 1 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_2 = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_3 = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_4 = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_5 = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_6 = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_7 = 7 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_8 = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_9 = 9 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_10 = 10 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_11 = 11 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_12 = 12 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_13 = 13 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_14 = 14 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_15 = 15 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_16 = 16 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_17 = 17 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_18 = 18 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_19 = 19 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_20 = 20 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_21 = 21 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_22 = 22 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_23 = 23 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_0 = 24 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_1 = 25 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_2 = 26 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_3 = 27 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_4 = 28 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_5 = 29 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_6 = 30 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_7 = 31 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_0 = 32 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_1 = 33 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_2 = 34 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_3 = 35 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_0 = 36 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_1 = 37 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_2 = 38 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_3 = 39 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_4 = 40 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_5 = 41 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_6 = 42 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_7 = 43 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_REG_0 = 44 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_REG_1 = 45 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_REG_2 = 46 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_REG_3 = 47 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_0 = 48 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_1 = 49 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_2 = 50 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_3 = 51 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_4 = 52 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_5 = 53 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_6 = 54 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_7 = 55 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_8 = 56 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_9 = 57 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_10 = 58 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_11 = 59 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_12 = 60 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_13 = 61 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_14 = 62 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_15 = 63 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_NVF_1 = 1 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_NVF_2 = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_NVF_3 = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_NVF_4 = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_NVF_5 = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_NVF_6 = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_NVF_7 = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_NVF_8 = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_NVF_9 = 9 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_NVF_10 = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_NVF_11 = 11 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_NVF_12 = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_NVF_13 = 13 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_NVF_14 = 14 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_NVF_15 = 15 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_NVF_16 = 16 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_NVF_17 = 17 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_NVF_18 = 18 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_NVF_19 = 19 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_NVF_20 = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_NVF_21 = 21 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_NVF_22 = 22 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_NVF_23 = 23 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_NCF_0 = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_NCF_1 = 25 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_NCF_2 = 26 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_NCF_3 = 27 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_NCF_4 = 28 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_NCF_5 = 29 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_NCF_6 = 30 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_NCF_7 = 31 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_0 = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_1 = 33 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_2 = 34 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_3 = 35 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_PBR_0 = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_PBR_1 = 37 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_PBR_2 = 38 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_PBR_3 = 39 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_PBR_4 = 40 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_PBR_5 = 41 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_PBR_6 = 42 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_PBR_7 = 43 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_REG_0 = 44 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_REG_1 = 45 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_REG_2 = 46 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_REG_3 = 47 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_OCR_0 = 48 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_OCR_1 = 49 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_OCR_2 = 50 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_OCR_3 = 51 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_OCR_4 = 52 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_OCR_5 = 53 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_OCR_6 = 54 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_OCR_7 = 55 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_OCR_8 = 56 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_OCR_9 = 57 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_OCR_10 = 58 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_OCR_11 = 59 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_OCR_12 = 60 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_OCR_13 = 61 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_OCR_14 = 62 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST0_IDIAL_SM_FIRST_OCR_15 = 63 ;
+
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0 = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_1 = 1 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_2 = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_3 = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_4 = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_5 = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_6 = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_7 = 7 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_8 = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_9 = 9 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_10 = 10 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_11 = 11 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_12 = 12 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_13 = 13 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_14 = 14 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_15 = 15 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_16 = 16 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_17 = 17 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_18 = 18 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_19 = 19 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_20 = 20 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_21 = 21 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_22 = 22 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_23 = 23 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_0 = 24 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_1 = 25 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_2 = 26 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_3 = 27 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_4 = 28 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_5 = 29 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_6 = 30 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_7 = 31 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_0 = 32 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_1 = 33 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_2 = 34 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_3 = 35 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_0 = 36 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_1 = 37 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_2 = 38 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_3 = 39 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_4 = 40 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_5 = 41 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_6 = 42 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_7 = 43 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_REG_0 = 44 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_REG_1 = 45 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_REG_2 = 46 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_REG_3 = 47 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_0 = 48 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_1 = 49 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_2 = 50 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_3 = 51 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_4 = 52 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_5 = 53 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_6 = 54 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_7 = 55 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_8 = 56 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_9 = 57 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_10 = 58 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_11 = 59 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_12 = 60 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_13 = 61 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_14 = 62 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_15 = 63 ;
+
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0 = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_1 = 1 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_2 = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_3 = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_4 = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_5 = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_6 = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_7 = 7 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_8 = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_9 = 9 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_10 = 10 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_11 = 11 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_12 = 12 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_13 = 13 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_14 = 14 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_15 = 15 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_16 = 16 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_17 = 17 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_18 = 18 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_19 = 19 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_20 = 20 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_21 = 21 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_22 = 22 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_23 = 23 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_0 = 24 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_1 = 25 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_2 = 26 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_3 = 27 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_4 = 28 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_5 = 29 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_6 = 30 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_7 = 31 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_0 = 32 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_1 = 33 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_2 = 34 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_3 = 35 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_0 = 36 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_1 = 37 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_2 = 38 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_3 = 39 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_4 = 40 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_5 = 41 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_6 = 42 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_7 = 43 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_REG_0 = 44 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_REG_1 = 45 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_REG_2 = 46 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_REG_3 = 47 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_0 = 48 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_1 = 49 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_2 = 50 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_3 = 51 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_4 = 52 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_5 = 53 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_6 = 54 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_7 = 55 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_8 = 56 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_9 = 57 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_10 = 58 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_11 = 59 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_12 = 60 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_13 = 61 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_14 = 62 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_OCR_15 = 63 ;
+
+static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_0 = 0 ;
+static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_1 = 1 ;
+static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_2 = 2 ;
+static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_3 = 3 ;
+static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_4 = 4 ;
+static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_5 = 5 ;
+static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_6 = 6 ;
+static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_7 = 7 ;
+static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_0 = 8 ;
+static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_1 = 9 ;
+static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_2 = 10 ;
+static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_3 = 11 ;
+static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_4 = 12 ;
+static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_5 = 13 ;
+static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_6 = 14 ;
+static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_7 = 15 ;
+static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_8 = 16 ;
+static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_9 = 17 ;
+static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_10 = 18 ;
+static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_11 = 19 ;
+static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_12 = 20 ;
+static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_13 = 21 ;
+static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_14 = 22 ;
+static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_15 = 23 ;
+static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_16 = 24 ;
+static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_17 = 25 ;
+static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_18 = 26 ;
+static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_19 = 27 ;
+static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_OCR_0 = 28 ;
+static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_OCR_1 = 29 ;
+static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_OCR_2 = 30 ;
+static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_OCR_3 = 31 ;
+static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_OCR_4 = 32 ;
+static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_OCR_5 = 33 ;
+static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_OCR_6 = 34 ;
+static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_OCR_7 = 35 ;
+static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_0 = 36 ;
+static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_1 = 37 ;
+static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_2 = 38 ;
+static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_3 = 39 ;
+static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_4 = 40 ;
+static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_5 = 41 ;
+static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_6 = 42 ;
+static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_7 = 43 ;
+static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_0 = 44 ;
+static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_1 = 45 ;
+static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_2 = 46 ;
+static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_3 = 47 ;
+static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_4 = 48 ;
+static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_5 = 49 ;
+static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_6 = 50 ;
+static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_7 = 51 ;
+static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_REG_0 = 52 ;
+static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_REG_1 = 53 ;
+static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_REG_2 = 54 ;
+static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_REG_3 = 55 ;
+static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_DUE_0 = 56 ;
+static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_DUE_1 = 57 ;
+static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_DUE_2 = 58 ;
+static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_DUE_3 = 59 ;
+static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_PEF_0 = 60 ;
+static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_PEF_1 = 61 ;
+static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_PEF_2 = 62 ;
+static const uint8_t P9N2_NV_CERR_FIRST0_IDIAL_CTL_FIRST_PEF_3 = 63 ;
+
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0 = 0 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_1 = 1 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_2 = 2 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_3 = 3 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_4 = 4 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_5 = 5 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_6 = 6 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_7 = 7 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_8 = 8 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_9 = 9 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_10 = 10 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_11 = 11 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_12 = 12 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_13 = 13 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_14 = 14 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_15 = 15 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_16 = 16 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_17 = 17 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_18 = 18 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_19 = 19 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_20 = 20 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_21 = 21 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_22 = 22 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_23 = 23 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_0 = 24 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_1 = 25 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_2 = 26 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_3 = 27 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_4 = 28 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_5 = 29 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_6 = 30 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_7 = 31 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_0 = 32 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_1 = 33 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_2 = 34 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_3 = 35 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_0 = 36 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_1 = 37 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_2 = 38 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_3 = 39 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_4 = 40 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_5 = 41 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_6 = 42 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_7 = 43 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_REG_0 = 44 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_REG_1 = 45 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_REG_2 = 46 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_REG_3 = 47 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_0 = 48 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_1 = 49 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_2 = 50 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_3 = 51 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_4 = 52 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_5 = 53 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_6 = 54 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_7 = 55 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_8 = 56 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_9 = 57 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_10 = 58 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_11 = 59 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_12 = 60 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_13 = 61 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_14 = 62 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST0_IDIAL_SM_FIRST_OCR_15 = 63 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_1 = 1 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_2 = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_3 = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_4 = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_5 = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_6 = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_7 = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_8 = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_9 = 9 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_10 = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_11 = 11 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_12 = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_13 = 13 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_14 = 14 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_15 = 15 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_16 = 16 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_17 = 17 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_18 = 18 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_19 = 19 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_20 = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_21 = 21 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_22 = 22 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_23 = 23 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_0 = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_1 = 25 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_2 = 26 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_3 = 27 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_4 = 28 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_5 = 29 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_6 = 30 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_7 = 31 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_0 = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_1 = 33 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_2 = 34 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_3 = 35 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_0 = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_1 = 37 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_2 = 38 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_3 = 39 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_4 = 40 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_5 = 41 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_6 = 42 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_7 = 43 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_REG_0 = 44 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_REG_1 = 45 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_REG_2 = 46 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_REG_3 = 47 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_0 = 48 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_1 = 49 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_2 = 50 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_3 = 51 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_4 = 52 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_5 = 53 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_6 = 54 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_7 = 55 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_8 = 56 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_9 = 57 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_10 = 58 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_11 = 59 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_12 = 60 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_13 = 61 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_14 = 62 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST0_IDIAL_SM_FIRST_OCR_15 = 63 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_0 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_1 = 1 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_2 = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_3 = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_4 = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_5 = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_6 = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_7 = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_8 = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_9 = 9 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_10 = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_11 = 11 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_12 = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_13 = 13 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_14 = 14 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_15 = 15 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_0 = 16 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_1 = 17 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_2 = 18 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_3 = 19 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_0 = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_1 = 21 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_2 = 22 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_3 = 23 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_0 = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_1 = 25 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_2 = 26 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_3 = 27 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_4 = 28 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_5 = 29 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_6 = 30 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_7 = 31 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_0 = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_1 = 33 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_2 = 34 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_3 = 35 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_4 = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_5 = 37 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_6 = 38 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_7 = 39 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_8 = 40 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_9 = 41 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_10 = 42 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_11 = 43 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_0 = 44 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_1 = 45 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_2 = 46 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_3 = 47 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_4 = 48 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_5 = 49 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_6 = 50 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_7 = 51 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_8 = 52 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_9 = 53 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_10 = 54 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_11 = 55 ;
+
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_0 = 0 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_1 = 1 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_2 = 2 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_3 = 3 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_4 = 4 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_5 = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_6 = 6 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_7 = 7 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_8 = 8 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_9 = 9 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_10 = 10 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_11 = 11 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_12 = 12 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_13 = 13 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_14 = 14 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_15 = 15 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_16 = 16 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_17 = 17 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_18 = 18 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_19 = 19 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_20 = 20 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_21 = 21 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_22 = 22 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_23 = 23 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_24 = 24 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_25 = 25 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_26 = 26 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_27 = 27 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_28 = 28 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_29 = 29 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_30 = 30 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_31 = 31 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_32 = 32 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_33 = 33 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_34 = 34 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_35 = 35 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_36 = 36 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_37 = 37 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_38 = 38 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_39 = 39 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_40 = 40 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_41 = 41 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_42 = 42 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_43 = 43 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_44 = 44 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_45 = 45 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_46 = 46 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_47 = 47 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_48 = 48 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_49 = 49 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_50 = 50 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_51 = 51 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_52 = 52 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_53 = 53 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_54 = 54 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_55 = 55 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_56 = 56 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_57 = 57 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_58 = 58 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_59 = 59 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_60 = 60 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_61 = 61 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_62 = 62 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST1_NTL_63 = 63 ;
+
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_0 = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_1 = 1 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_2 = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_3 = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_4 = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_5 = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_6 = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_7 = 7 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_8 = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_9 = 9 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_10 = 10 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_11 = 11 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_12 = 12 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_13 = 13 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_14 = 14 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_15 = 15 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_0 = 16 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_1 = 17 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_2 = 18 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_3 = 19 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_0 = 20 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_1 = 21 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_2 = 22 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_3 = 23 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_0 = 24 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_1 = 25 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_2 = 26 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_3 = 27 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_4 = 28 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_5 = 29 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_6 = 30 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_7 = 31 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_0 = 32 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_1 = 33 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_2 = 34 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_3 = 35 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_4 = 36 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_5 = 37 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_6 = 38 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_7 = 39 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_8 = 40 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_9 = 41 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_10 = 42 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_11 = 43 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_0 = 44 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_1 = 45 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_2 = 46 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_3 = 47 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_4 = 48 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_5 = 49 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_6 = 50 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_7 = 51 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_8 = 52 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_9 = 53 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_10 = 54 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_11 = 55 ;
+
+static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_0 = 0 ;
+static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_1 = 1 ;
+static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_2 = 2 ;
+static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_3 = 3 ;
+static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_4 = 4 ;
+static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_5 = 5 ;
+static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_6 = 6 ;
+static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_7 = 7 ;
+static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_8 = 8 ;
+static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_9 = 9 ;
+static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_10 = 10 ;
+static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_11 = 11 ;
+static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_12 = 12 ;
+static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_13 = 13 ;
+static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_14 = 14 ;
+static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_15 = 15 ;
+static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_16 = 16 ;
+static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_17 = 17 ;
+static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_18 = 18 ;
+static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_19 = 19 ;
+static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_20 = 20 ;
+static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_21 = 21 ;
+static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_22 = 22 ;
+static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_23 = 23 ;
+static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_24 = 24 ;
+static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_25 = 25 ;
+static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_26 = 26 ;
+static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_27 = 27 ;
+static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_28 = 28 ;
+static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_29 = 29 ;
+static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_30 = 30 ;
+static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_31 = 31 ;
+static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_32 = 32 ;
+static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_33 = 33 ;
+static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_34 = 34 ;
+static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_35 = 35 ;
+static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_36 = 36 ;
+static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_37 = 37 ;
+static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_38 = 38 ;
+static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_39 = 39 ;
+static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_40 = 40 ;
+static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_41 = 41 ;
+static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_42 = 42 ;
+static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_43 = 43 ;
+static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_44 = 44 ;
+static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_45 = 45 ;
+static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_46 = 46 ;
+static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_47 = 47 ;
+static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_48 = 48 ;
+static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_49 = 49 ;
+static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_50 = 50 ;
+static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_51 = 51 ;
+static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_52 = 52 ;
+static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_53 = 53 ;
+static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_54 = 54 ;
+static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_55 = 55 ;
+static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_56 = 56 ;
+static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_57 = 57 ;
+static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_58 = 58 ;
+static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_59 = 59 ;
+static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_60 = 60 ;
+static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_61 = 61 ;
+static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_62 = 62 ;
+static const uint8_t P9N2__SM1_CERR_FIRST1_NTL_63 = 63 ;
+
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_0 = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_1 = 1 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_2 = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_3 = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_4 = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_5 = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_6 = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_7 = 7 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_8 = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_9 = 9 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_10 = 10 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_11 = 11 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_12 = 12 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_13 = 13 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_14 = 14 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_15 = 15 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_0 = 16 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_1 = 17 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_2 = 18 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_3 = 19 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_0 = 20 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_1 = 21 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_2 = 22 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_3 = 23 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_0 = 24 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_1 = 25 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_2 = 26 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_3 = 27 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_4 = 28 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_5 = 29 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_6 = 30 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_7 = 31 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_0 = 32 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_1 = 33 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_2 = 34 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_3 = 35 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_4 = 36 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_5 = 37 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_6 = 38 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_7 = 39 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_8 = 40 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_9 = 41 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_10 = 42 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_11 = 43 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_0 = 44 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_1 = 45 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_2 = 46 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_3 = 47 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_4 = 48 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_5 = 49 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_6 = 50 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_7 = 51 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_8 = 52 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_9 = 53 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_10 = 54 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_11 = 55 ;
+
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_0 = 0 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_1 = 1 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_2 = 2 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_3 = 3 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_4 = 4 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_5 = 5 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_6 = 6 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_7 = 7 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_8 = 8 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_9 = 9 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_10 = 10 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_11 = 11 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_12 = 12 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_13 = 13 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_14 = 14 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_15 = 15 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_0 = 16 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_1 = 17 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_2 = 18 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_3 = 19 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_4 = 20 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_5 = 21 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_6 = 22 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_7 = 23 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_0 = 24 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_1 = 25 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_2 = 26 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_3 = 27 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_4 = 28 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_5 = 29 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_6 = 30 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_7 = 31 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_0 = 32 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_1 = 33 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_2 = 34 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_3 = 35 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_4 = 36 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_5 = 37 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_6 = 38 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_7 = 39 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_0 = 40 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_1 = 41 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_2 = 42 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_3 = 43 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_4 = 44 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_5 = 45 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_6 = 46 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_7 = 47 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_0 = 48 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_1 = 49 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_2 = 50 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_3 = 51 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_4 = 52 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_5 = 53 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_6 = 54 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_7 = 55 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_RSV2_0 = 56 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_RSV2_1 = 57 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_RSV2_2 = 58 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_RSV2_3 = 59 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_RSV3_0 = 60 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_RSV3_1 = 61 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_RSV3_2 = 62 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_FIRST1_IDIAL_CTL_FIRST_RSV3_3 = 63 ;
+
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_0 = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_1 = 1 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_2 = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_3 = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_4 = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_5 = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_6 = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_7 = 7 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_8 = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_9 = 9 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_10 = 10 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_11 = 11 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_12 = 12 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_13 = 13 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_14 = 14 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_15 = 15 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_FWD_0 = 16 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_FWD_1 = 17 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_FWD_2 = 18 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_FWD_3 = 19 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_AUE_0 = 20 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_AUE_1 = 21 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_AUE_2 = 22 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_AUE_3 = 23 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_0 = 24 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_1 = 25 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_2 = 26 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_3 = 27 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_4 = 28 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_5 = 29 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_6 = 30 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_7 = 31 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_0 = 32 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_1 = 33 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_2 = 34 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_3 = 35 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_4 = 36 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_5 = 37 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_6 = 38 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_7 = 39 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_8 = 40 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_9 = 41 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_10 = 42 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_11 = 43 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_0 = 44 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_1 = 45 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_2 = 46 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_3 = 47 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_4 = 48 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_5 = 49 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_6 = 50 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_7 = 51 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_8 = 52 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_9 = 53 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_10 = 54 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_11 = 55 ;
+
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_0 = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_1 = 1 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_2 = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_3 = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_4 = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_5 = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_6 = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_7 = 7 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_8 = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_9 = 9 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_10 = 10 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_11 = 11 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_12 = 12 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_13 = 13 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_14 = 14 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_15 = 15 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_FWD_0 = 16 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_FWD_1 = 17 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_FWD_2 = 18 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_FWD_3 = 19 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_AUE_0 = 20 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_AUE_1 = 21 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_AUE_2 = 22 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_AUE_3 = 23 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_0 = 24 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_1 = 25 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_2 = 26 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_3 = 27 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_4 = 28 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_5 = 29 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_6 = 30 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_7 = 31 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_0 = 32 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_1 = 33 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_2 = 34 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_3 = 35 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_4 = 36 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_5 = 37 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_6 = 38 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_7 = 39 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_8 = 40 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_9 = 41 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_10 = 42 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_11 = 43 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_0 = 44 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_1 = 45 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_2 = 46 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_3 = 47 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_4 = 48 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_5 = 49 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_6 = 50 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_7 = 51 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_8 = 52 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_9 = 53 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_10 = 54 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_11 = 55 ;
+
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_0 = 0 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_1 = 1 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_2 = 2 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_3 = 3 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_4 = 4 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_5 = 5 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_6 = 6 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_7 = 7 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_8 = 8 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_9 = 9 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_10 = 10 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_11 = 11 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_12 = 12 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_13 = 13 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_14 = 14 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_15 = 15 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_0 = 16 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_1 = 17 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_2 = 18 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_3 = 19 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_0 = 20 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_1 = 21 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_2 = 22 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_3 = 23 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_0 = 24 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_1 = 25 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_2 = 26 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_3 = 27 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_4 = 28 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_5 = 29 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_6 = 30 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_7 = 31 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_0 = 32 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_1 = 33 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_2 = 34 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_3 = 35 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_4 = 36 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_5 = 37 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_6 = 38 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_7 = 39 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_8 = 40 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_9 = 41 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_10 = 42 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_11 = 43 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_0 = 44 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_1 = 45 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_2 = 46 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_3 = 47 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_4 = 48 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_5 = 49 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_6 = 50 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_7 = 51 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_8 = 52 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_9 = 53 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_10 = 54 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_11 = 55 ;
+
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_0 = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_1 = 1 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_2 = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_3 = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_4 = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_5 = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_6 = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_7 = 7 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_8 = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_9 = 9 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_10 = 10 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_11 = 11 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_12 = 12 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_13 = 13 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_14 = 14 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_15 = 15 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_0 = 16 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_1 = 17 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_2 = 18 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_3 = 19 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_0 = 20 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_1 = 21 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_2 = 22 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_3 = 23 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_0 = 24 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_1 = 25 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_2 = 26 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_3 = 27 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_4 = 28 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_5 = 29 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_6 = 30 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_7 = 31 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_0 = 32 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_1 = 33 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_2 = 34 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_3 = 35 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_4 = 36 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_5 = 37 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_6 = 38 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_7 = 39 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_8 = 40 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_9 = 41 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_10 = 42 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_11 = 43 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_0 = 44 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_1 = 45 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_2 = 46 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_3 = 47 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_4 = 48 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_5 = 49 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_6 = 50 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_7 = 51 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_8 = 52 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_9 = 53 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_10 = 54 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_11 = 55 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_0 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_1 = 1 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_2 = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_3 = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_4 = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_5 = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_6 = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_7 = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_8 = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_9 = 9 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_10 = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_11 = 11 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_12 = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_13 = 13 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_14 = 14 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_15 = 15 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_0 = 16 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_1 = 17 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_2 = 18 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_3 = 19 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_0 = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_1 = 21 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_2 = 22 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_3 = 23 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_0 = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_1 = 25 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_2 = 26 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_3 = 27 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_4 = 28 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_5 = 29 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_6 = 30 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_7 = 31 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_0 = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_1 = 33 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_2 = 34 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_3 = 35 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_4 = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_5 = 37 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_6 = 38 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_7 = 39 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_8 = 40 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_9 = 41 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_10 = 42 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_11 = 43 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_0 = 44 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_1 = 45 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_2 = 46 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_3 = 47 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_4 = 48 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_5 = 49 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_6 = 50 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_7 = 51 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_8 = 52 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_9 = 53 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_10 = 54 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_11 = 55 ;
+
+static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_0 = 0 ;
+static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_1 = 1 ;
+static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_2 = 2 ;
+static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_3 = 3 ;
+static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_4 = 4 ;
+static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_5 = 5 ;
+static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_6 = 6 ;
+static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_7 = 7 ;
+static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_8 = 8 ;
+static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_9 = 9 ;
+static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_10 = 10 ;
+static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_11 = 11 ;
+static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_12 = 12 ;
+static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_13 = 13 ;
+static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_14 = 14 ;
+static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_15 = 15 ;
+static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_16 = 16 ;
+static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_17 = 17 ;
+static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_18 = 18 ;
+static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_19 = 19 ;
+static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_20 = 20 ;
+static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_21 = 21 ;
+static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_22 = 22 ;
+static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_23 = 23 ;
+static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_24 = 24 ;
+static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_25 = 25 ;
+static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_26 = 26 ;
+static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_27 = 27 ;
+static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_28 = 28 ;
+static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_29 = 29 ;
+static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_30 = 30 ;
+static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_31 = 31 ;
+static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_32 = 32 ;
+static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_33 = 33 ;
+static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_34 = 34 ;
+static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_35 = 35 ;
+static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_36 = 36 ;
+static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_37 = 37 ;
+static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_38 = 38 ;
+static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_39 = 39 ;
+static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_40 = 40 ;
+static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_41 = 41 ;
+static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_42 = 42 ;
+static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_43 = 43 ;
+static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_44 = 44 ;
+static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_45 = 45 ;
+static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_46 = 46 ;
+static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_47 = 47 ;
+static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_48 = 48 ;
+static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_49 = 49 ;
+static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_50 = 50 ;
+static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_51 = 51 ;
+static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_52 = 52 ;
+static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_53 = 53 ;
+static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_54 = 54 ;
+static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_55 = 55 ;
+static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_56 = 56 ;
+static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_57 = 57 ;
+static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_58 = 58 ;
+static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_59 = 59 ;
+static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_60 = 60 ;
+static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_61 = 61 ;
+static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_62 = 62 ;
+static const uint8_t P9N2__SM0_CERR_FIRST1_NTL_63 = 63 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_0 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_1 = 1 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_2 = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_3 = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_4 = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_5 = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_6 = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_7 = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_8 = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_9 = 9 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_10 = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_11 = 11 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_12 = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_13 = 13 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_14 = 14 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_15 = 15 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_FWD_0 = 16 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_FWD_1 = 17 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_FWD_2 = 18 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_FWD_3 = 19 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_AUE_0 = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_AUE_1 = 21 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_AUE_2 = 22 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_AUE_3 = 23 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_PBP_0 = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_PBP_1 = 25 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_PBP_2 = 26 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_PBP_3 = 27 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_PBP_4 = 28 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_PBP_5 = 29 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_PBP_6 = 30 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_PBP_7 = 31 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_PBF_0 = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_PBF_1 = 33 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_PBF_2 = 34 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_PBF_3 = 35 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_PBF_4 = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_PBF_5 = 37 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_PBF_6 = 38 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_PBF_7 = 39 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_PBF_8 = 40 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_PBF_9 = 41 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_PBF_10 = 42 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_PBF_11 = 43 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_PBC_0 = 44 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_PBC_1 = 45 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_PBC_2 = 46 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_PBC_3 = 47 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_PBC_4 = 48 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_PBC_5 = 49 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_PBC_6 = 50 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_PBC_7 = 51 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_PBC_8 = 52 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_PBC_9 = 53 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_PBC_10 = 54 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST1_IDIAL_SM_FIRST_PBC_11 = 55 ;
+
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_0 = 0 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_1 = 1 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_2 = 2 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_3 = 3 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_4 = 4 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_5 = 5 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_6 = 6 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_7 = 7 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_8 = 8 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_9 = 9 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_10 = 10 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_11 = 11 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_12 = 12 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_13 = 13 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_14 = 14 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_15 = 15 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_16 = 16 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_17 = 17 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_18 = 18 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_19 = 19 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_20 = 20 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_21 = 21 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_22 = 22 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_23 = 23 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_24 = 24 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_25 = 25 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_26 = 26 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_27 = 27 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_28 = 28 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_29 = 29 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_30 = 30 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_31 = 31 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_32 = 32 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_33 = 33 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_34 = 34 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_35 = 35 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_36 = 36 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_37 = 37 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_38 = 38 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_39 = 39 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_40 = 40 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_41 = 41 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_42 = 42 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_43 = 43 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_44 = 44 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_45 = 45 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_46 = 46 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_47 = 47 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_48 = 48 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_49 = 49 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_50 = 50 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_51 = 51 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_52 = 52 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_53 = 53 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_54 = 54 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_55 = 55 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_56 = 56 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_57 = 57 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_58 = 58 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_59 = 59 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_60 = 60 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_61 = 61 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_62 = 62 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST1_NTL_63 = 63 ;
+
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_0 = 0 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_1 = 1 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_2 = 2 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_3 = 3 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_4 = 4 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_5 = 5 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_6 = 6 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_7 = 7 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_8 = 8 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_9 = 9 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_10 = 10 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_11 = 11 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_12 = 12 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_13 = 13 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_14 = 14 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_15 = 15 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_16 = 16 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_17 = 17 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_18 = 18 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_19 = 19 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_20 = 20 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_21 = 21 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_22 = 22 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_23 = 23 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_24 = 24 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_25 = 25 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_26 = 26 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_27 = 27 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_28 = 28 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_29 = 29 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_30 = 30 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_31 = 31 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_32 = 32 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_33 = 33 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_34 = 34 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_35 = 35 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_36 = 36 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_37 = 37 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_38 = 38 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_39 = 39 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_40 = 40 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_41 = 41 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_42 = 42 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_43 = 43 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_44 = 44 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_45 = 45 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_46 = 46 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_47 = 47 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_48 = 48 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_49 = 49 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_50 = 50 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_51 = 51 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_52 = 52 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_53 = 53 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_54 = 54 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_55 = 55 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_56 = 56 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_57 = 57 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_58 = 58 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_59 = 59 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_60 = 60 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_61 = 61 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_62 = 62 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST1_NTL_63 = 63 ;
+
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_0 = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_1 = 1 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_2 = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_3 = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_4 = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_5 = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_6 = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_7 = 7 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_8 = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_9 = 9 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_10 = 10 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_11 = 11 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_12 = 12 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_13 = 13 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_14 = 14 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_15 = 15 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_0 = 16 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_1 = 17 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_2 = 18 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_3 = 19 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_0 = 20 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_1 = 21 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_2 = 22 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_3 = 23 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_0 = 24 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_1 = 25 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_2 = 26 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_3 = 27 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_4 = 28 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_5 = 29 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_6 = 30 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_7 = 31 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_0 = 32 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_1 = 33 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_2 = 34 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_3 = 35 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_4 = 36 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_5 = 37 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_6 = 38 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_7 = 39 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_8 = 40 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_9 = 41 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_10 = 42 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_11 = 43 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_0 = 44 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_1 = 45 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_2 = 46 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_3 = 47 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_4 = 48 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_5 = 49 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_6 = 50 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_7 = 51 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_8 = 52 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_9 = 53 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_10 = 54 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_11 = 55 ;
+
+static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_0 = 0 ;
+static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_1 = 1 ;
+static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_2 = 2 ;
+static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_3 = 3 ;
+static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_4 = 4 ;
+static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_5 = 5 ;
+static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_6 = 6 ;
+static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_7 = 7 ;
+static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_8 = 8 ;
+static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_9 = 9 ;
+static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_10 = 10 ;
+static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_11 = 11 ;
+static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_12 = 12 ;
+static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_13 = 13 ;
+static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_14 = 14 ;
+static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_15 = 15 ;
+static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_0 = 16 ;
+static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_1 = 17 ;
+static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_2 = 18 ;
+static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_3 = 19 ;
+static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_4 = 20 ;
+static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_5 = 21 ;
+static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_6 = 22 ;
+static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_7 = 23 ;
+static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_0 = 24 ;
+static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_1 = 25 ;
+static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_2 = 26 ;
+static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_3 = 27 ;
+static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_4 = 28 ;
+static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_5 = 29 ;
+static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_6 = 30 ;
+static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_7 = 31 ;
+static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_0 = 32 ;
+static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_1 = 33 ;
+static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_2 = 34 ;
+static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_3 = 35 ;
+static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_4 = 36 ;
+static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_5 = 37 ;
+static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_6 = 38 ;
+static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_7 = 39 ;
+static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_0 = 40 ;
+static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_1 = 41 ;
+static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_2 = 42 ;
+static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_3 = 43 ;
+static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_4 = 44 ;
+static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_5 = 45 ;
+static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_6 = 46 ;
+static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_7 = 47 ;
+static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_0 = 48 ;
+static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_1 = 49 ;
+static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_2 = 50 ;
+static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_3 = 51 ;
+static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_4 = 52 ;
+static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_5 = 53 ;
+static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_6 = 54 ;
+static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_7 = 55 ;
+static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_RSV2_0 = 56 ;
+static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_RSV2_1 = 57 ;
+static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_RSV2_2 = 58 ;
+static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_RSV2_3 = 59 ;
+static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_RSV3_0 = 60 ;
+static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_RSV3_1 = 61 ;
+static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_RSV3_2 = 62 ;
+static const uint8_t P9N2_NV_CERR_FIRST1_IDIAL_CTL_FIRST_RSV3_3 = 63 ;
+
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_0 = 0 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_1 = 1 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_2 = 2 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_3 = 3 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_4 = 4 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_5 = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_6 = 6 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_7 = 7 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_8 = 8 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_9 = 9 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_10 = 10 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_11 = 11 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_12 = 12 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_13 = 13 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_14 = 14 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_15 = 15 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_16 = 16 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_17 = 17 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_18 = 18 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_19 = 19 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_20 = 20 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_21 = 21 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_22 = 22 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_23 = 23 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_24 = 24 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_25 = 25 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_26 = 26 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_27 = 27 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_28 = 28 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_29 = 29 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_30 = 30 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_31 = 31 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_32 = 32 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_33 = 33 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_34 = 34 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_35 = 35 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_36 = 36 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_37 = 37 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_38 = 38 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_39 = 39 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_40 = 40 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_41 = 41 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_42 = 42 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_43 = 43 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_44 = 44 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_45 = 45 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_46 = 46 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_47 = 47 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_48 = 48 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_49 = 49 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_50 = 50 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_51 = 51 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_52 = 52 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_53 = 53 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_54 = 54 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_55 = 55 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_56 = 56 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_57 = 57 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_58 = 58 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_59 = 59 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_60 = 60 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_61 = 61 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_62 = 62 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST1_NTL_63 = 63 ;
+
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_0 = 0 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_1 = 1 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_2 = 2 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_3 = 3 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_4 = 4 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_5 = 5 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_6 = 6 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_7 = 7 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_8 = 8 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_9 = 9 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_10 = 10 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_11 = 11 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_12 = 12 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_13 = 13 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_14 = 14 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_15 = 15 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_0 = 16 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_1 = 17 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_2 = 18 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_3 = 19 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_0 = 20 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_1 = 21 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_2 = 22 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_3 = 23 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_0 = 24 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_1 = 25 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_2 = 26 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_3 = 27 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_4 = 28 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_5 = 29 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_6 = 30 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_7 = 31 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_0 = 32 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_1 = 33 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_2 = 34 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_3 = 35 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_4 = 36 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_5 = 37 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_6 = 38 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_7 = 39 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_8 = 40 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_9 = 41 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_10 = 42 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_11 = 43 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_0 = 44 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_1 = 45 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_2 = 46 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_3 = 47 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_4 = 48 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_5 = 49 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_6 = 50 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_7 = 51 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_8 = 52 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_9 = 53 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_10 = 54 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_11 = 55 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_0 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_1 = 1 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_2 = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_3 = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_4 = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_5 = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_6 = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_7 = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_8 = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_9 = 9 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_10 = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_11 = 11 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_12 = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_13 = 13 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_14 = 14 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_15 = 15 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_FWD_0 = 16 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_FWD_1 = 17 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_FWD_2 = 18 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_FWD_3 = 19 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_AUE_0 = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_AUE_1 = 21 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_AUE_2 = 22 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_AUE_3 = 23 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_0 = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_1 = 25 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_2 = 26 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_3 = 27 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_4 = 28 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_5 = 29 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_6 = 30 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_7 = 31 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_0 = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_1 = 33 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_2 = 34 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_3 = 35 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_4 = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_5 = 37 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_6 = 38 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_7 = 39 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_8 = 40 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_9 = 41 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_10 = 42 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_11 = 43 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_0 = 44 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_1 = 45 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_2 = 46 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_3 = 47 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_4 = 48 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_5 = 49 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_6 = 50 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_7 = 51 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_8 = 52 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_9 = 53 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_10 = 54 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_11 = 55 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_0 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_1 = 1 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_2 = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_3 = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_4 = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_5 = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_6 = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_7 = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_8 = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_9 = 9 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_10 = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_11 = 11 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_12 = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_13 = 13 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_14 = 14 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_15 = 15 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_16 = 16 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_17 = 17 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_18 = 18 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_19 = 19 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_20 = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_21 = 21 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_22 = 22 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_23 = 23 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_24 = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_25 = 25 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_26 = 26 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_27 = 27 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_28 = 28 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_29 = 29 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_30 = 30 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_31 = 31 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_32 = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_33 = 33 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_34 = 34 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_35 = 35 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_36 = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_37 = 37 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_38 = 38 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_39 = 39 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_40 = 40 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_41 = 41 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_42 = 42 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_43 = 43 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_44 = 44 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_45 = 45 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_46 = 46 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_47 = 47 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_48 = 48 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_49 = 49 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_50 = 50 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_51 = 51 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_52 = 52 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_53 = 53 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_54 = 54 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_55 = 55 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_56 = 56 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_57 = 57 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_58 = 58 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_59 = 59 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_60 = 60 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_61 = 61 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_62 = 62 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_63 = 63 ;
+
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_0 = 0 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_1 = 1 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_2 = 2 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_3 = 3 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_4 = 4 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_5 = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_6 = 6 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_7 = 7 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_8 = 8 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_9 = 9 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_10 = 10 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_11 = 11 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_12 = 12 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_13 = 13 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_14 = 14 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_15 = 15 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_16 = 16 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_17 = 17 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_18 = 18 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_19 = 19 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_20 = 20 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_21 = 21 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_22 = 22 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_23 = 23 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_24 = 24 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_25 = 25 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_26 = 26 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_27 = 27 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_28 = 28 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_29 = 29 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_30 = 30 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_31 = 31 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_32 = 32 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_33 = 33 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_34 = 34 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_35 = 35 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_36 = 36 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_37 = 37 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_38 = 38 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_39 = 39 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_40 = 40 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_41 = 41 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_42 = 42 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_43 = 43 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_44 = 44 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_45 = 45 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_46 = 46 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_47 = 47 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_48 = 48 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_49 = 49 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_50 = 50 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_51 = 51 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_52 = 52 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_53 = 53 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_54 = 54 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_55 = 55 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_56 = 56 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_57 = 57 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_58 = 58 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_59 = 59 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_60 = 60 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_61 = 61 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_62 = 62 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST2_NTL_63 = 63 ;
+
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_0 = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_1 = 1 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_2 = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_3 = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_4 = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_5 = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_6 = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_7 = 7 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_8 = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_9 = 9 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_10 = 10 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_11 = 11 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_12 = 12 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_13 = 13 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_14 = 14 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_15 = 15 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_16 = 16 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_17 = 17 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_18 = 18 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_19 = 19 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_20 = 20 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_21 = 21 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_22 = 22 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_23 = 23 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_24 = 24 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_25 = 25 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_26 = 26 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_27 = 27 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_28 = 28 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_29 = 29 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_30 = 30 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_31 = 31 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_32 = 32 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_33 = 33 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_34 = 34 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_35 = 35 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_36 = 36 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_37 = 37 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_38 = 38 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_39 = 39 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_40 = 40 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_41 = 41 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_42 = 42 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_43 = 43 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_44 = 44 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_45 = 45 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_46 = 46 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_47 = 47 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_48 = 48 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_49 = 49 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_50 = 50 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_51 = 51 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_52 = 52 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_53 = 53 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_54 = 54 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_55 = 55 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_56 = 56 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_57 = 57 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_58 = 58 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_59 = 59 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_60 = 60 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_61 = 61 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_62 = 62 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_63 = 63 ;
+
+static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_0 = 0 ;
+static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_1 = 1 ;
+static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_2 = 2 ;
+static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_3 = 3 ;
+static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_4 = 4 ;
+static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_5 = 5 ;
+static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_6 = 6 ;
+static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_7 = 7 ;
+static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_8 = 8 ;
+static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_9 = 9 ;
+static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_10 = 10 ;
+static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_11 = 11 ;
+static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_12 = 12 ;
+static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_13 = 13 ;
+static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_14 = 14 ;
+static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_15 = 15 ;
+static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_16 = 16 ;
+static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_17 = 17 ;
+static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_18 = 18 ;
+static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_19 = 19 ;
+static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_20 = 20 ;
+static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_21 = 21 ;
+static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_22 = 22 ;
+static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_23 = 23 ;
+static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_24 = 24 ;
+static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_25 = 25 ;
+static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_26 = 26 ;
+static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_27 = 27 ;
+static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_28 = 28 ;
+static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_29 = 29 ;
+static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_30 = 30 ;
+static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_31 = 31 ;
+static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_32 = 32 ;
+static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_33 = 33 ;
+static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_34 = 34 ;
+static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_35 = 35 ;
+static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_36 = 36 ;
+static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_37 = 37 ;
+static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_38 = 38 ;
+static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_39 = 39 ;
+static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_40 = 40 ;
+static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_41 = 41 ;
+static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_42 = 42 ;
+static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_43 = 43 ;
+static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_44 = 44 ;
+static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_45 = 45 ;
+static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_46 = 46 ;
+static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_47 = 47 ;
+static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_48 = 48 ;
+static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_49 = 49 ;
+static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_50 = 50 ;
+static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_51 = 51 ;
+static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_52 = 52 ;
+static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_53 = 53 ;
+static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_54 = 54 ;
+static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_55 = 55 ;
+static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_56 = 56 ;
+static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_57 = 57 ;
+static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_58 = 58 ;
+static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_59 = 59 ;
+static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_60 = 60 ;
+static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_61 = 61 ;
+static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_62 = 62 ;
+static const uint8_t P9N2__SM1_CERR_FIRST2_NTL_63 = 63 ;
+
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_0 = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_1 = 1 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_2 = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_3 = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_4 = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_5 = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_6 = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_7 = 7 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_8 = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_9 = 9 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_10 = 10 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_11 = 11 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_12 = 12 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_13 = 13 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_14 = 14 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_15 = 15 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_16 = 16 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_17 = 17 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_18 = 18 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_19 = 19 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_20 = 20 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_21 = 21 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_22 = 22 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_23 = 23 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_24 = 24 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_25 = 25 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_26 = 26 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_27 = 27 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_28 = 28 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_29 = 29 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_30 = 30 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_31 = 31 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_32 = 32 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_33 = 33 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_34 = 34 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_35 = 35 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_36 = 36 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_37 = 37 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_38 = 38 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_39 = 39 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_40 = 40 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_41 = 41 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_42 = 42 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_43 = 43 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_44 = 44 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_45 = 45 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_46 = 46 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_47 = 47 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_48 = 48 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_49 = 49 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_50 = 50 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_51 = 51 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_52 = 52 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_53 = 53 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_54 = 54 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_55 = 55 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_56 = 56 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_57 = 57 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_58 = 58 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_59 = 59 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_60 = 60 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_61 = 61 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_62 = 62 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_63 = 63 ;
+
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_0 = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_1 = 1 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_2 = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_3 = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_4 = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_5 = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_6 = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_7 = 7 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_8 = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_9 = 9 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_10 = 10 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_11 = 11 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_12 = 12 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_13 = 13 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_14 = 14 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_15 = 15 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_16 = 16 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_17 = 17 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_18 = 18 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_19 = 19 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_20 = 20 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_21 = 21 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_22 = 22 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_23 = 23 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_24 = 24 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_25 = 25 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_26 = 26 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_27 = 27 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_28 = 28 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_29 = 29 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_30 = 30 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_31 = 31 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_32 = 32 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_33 = 33 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_34 = 34 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_35 = 35 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_36 = 36 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_37 = 37 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_38 = 38 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_39 = 39 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_40 = 40 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_41 = 41 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_42 = 42 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_43 = 43 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_44 = 44 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_45 = 45 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_46 = 46 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_47 = 47 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_48 = 48 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_49 = 49 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_50 = 50 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_51 = 51 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_52 = 52 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_53 = 53 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_54 = 54 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_55 = 55 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_56 = 56 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_57 = 57 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_58 = 58 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_59 = 59 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_60 = 60 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_61 = 61 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_62 = 62 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_63 = 63 ;
+
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_0 = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_1 = 1 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_2 = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_3 = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_4 = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_5 = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_6 = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_7 = 7 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_8 = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_9 = 9 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_10 = 10 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_11 = 11 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_12 = 12 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_13 = 13 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_14 = 14 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_15 = 15 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_16 = 16 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_17 = 17 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_18 = 18 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_19 = 19 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_20 = 20 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_21 = 21 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_22 = 22 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_23 = 23 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_24 = 24 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_25 = 25 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_26 = 26 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_27 = 27 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_28 = 28 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_29 = 29 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_30 = 30 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_31 = 31 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_32 = 32 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_33 = 33 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_34 = 34 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_35 = 35 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_36 = 36 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_37 = 37 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_38 = 38 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_39 = 39 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_40 = 40 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_41 = 41 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_42 = 42 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_43 = 43 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_44 = 44 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_45 = 45 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_46 = 46 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_47 = 47 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_48 = 48 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_49 = 49 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_50 = 50 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_51 = 51 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_52 = 52 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_53 = 53 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_54 = 54 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_55 = 55 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_56 = 56 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_57 = 57 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_58 = 58 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_59 = 59 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_60 = 60 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_61 = 61 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_62 = 62 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_63 = 63 ;
+
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_0 = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_1 = 1 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_2 = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_3 = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_4 = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_5 = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_6 = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_7 = 7 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_8 = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_9 = 9 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_10 = 10 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_11 = 11 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_12 = 12 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_13 = 13 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_14 = 14 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_15 = 15 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_16 = 16 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_17 = 17 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_18 = 18 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_19 = 19 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_20 = 20 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_21 = 21 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_22 = 22 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_23 = 23 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_24 = 24 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_25 = 25 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_26 = 26 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_27 = 27 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_28 = 28 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_29 = 29 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_30 = 30 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_31 = 31 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_32 = 32 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_33 = 33 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_34 = 34 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_35 = 35 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_36 = 36 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_37 = 37 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_38 = 38 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_39 = 39 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_40 = 40 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_41 = 41 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_42 = 42 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_43 = 43 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_44 = 44 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_45 = 45 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_46 = 46 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_47 = 47 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_48 = 48 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_49 = 49 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_50 = 50 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_51 = 51 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_52 = 52 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_53 = 53 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_54 = 54 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_55 = 55 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_56 = 56 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_57 = 57 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_58 = 58 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_59 = 59 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_60 = 60 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_61 = 61 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_62 = 62 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_63 = 63 ;
+
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_0 = 0 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_1 = 1 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_2 = 2 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_3 = 3 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_4 = 4 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_5 = 5 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_6 = 6 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_7 = 7 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_8 = 8 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_9 = 9 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_10 = 10 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_11 = 11 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_12 = 12 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_13 = 13 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_14 = 14 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_15 = 15 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_16 = 16 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_17 = 17 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_18 = 18 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_19 = 19 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_20 = 20 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_21 = 21 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_22 = 22 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_23 = 23 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_24 = 24 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_25 = 25 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_26 = 26 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_27 = 27 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_28 = 28 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_29 = 29 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_30 = 30 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_31 = 31 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_32 = 32 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_33 = 33 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_34 = 34 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_35 = 35 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_36 = 36 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_37 = 37 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_38 = 38 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_39 = 39 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_40 = 40 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_41 = 41 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_42 = 42 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_43 = 43 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_44 = 44 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_45 = 45 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_46 = 46 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_47 = 47 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_48 = 48 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_49 = 49 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_50 = 50 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_51 = 51 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_52 = 52 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_53 = 53 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_54 = 54 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_55 = 55 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_56 = 56 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_57 = 57 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_58 = 58 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_59 = 59 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_60 = 60 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_61 = 61 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_62 = 62 ;
+static const uint8_t P9N2_PU_NPU0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_63 = 63 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_0 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_1 = 1 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_2 = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_3 = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_4 = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_5 = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_6 = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_7 = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_8 = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_9 = 9 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_10 = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_11 = 11 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_12 = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_13 = 13 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_14 = 14 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_15 = 15 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_16 = 16 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_17 = 17 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_18 = 18 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_19 = 19 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_20 = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_21 = 21 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_22 = 22 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_23 = 23 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_24 = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_25 = 25 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_26 = 26 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_27 = 27 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_28 = 28 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_29 = 29 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_30 = 30 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_31 = 31 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_32 = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_33 = 33 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_34 = 34 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_35 = 35 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_36 = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_37 = 37 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_38 = 38 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_39 = 39 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_40 = 40 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_41 = 41 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_42 = 42 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_43 = 43 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_44 = 44 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_45 = 45 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_46 = 46 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_47 = 47 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_48 = 48 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_49 = 49 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_50 = 50 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_51 = 51 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_52 = 52 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_53 = 53 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_54 = 54 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_55 = 55 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_56 = 56 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_57 = 57 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_58 = 58 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_59 = 59 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_60 = 60 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_61 = 61 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_62 = 62 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_63 = 63 ;
+
+static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_0 = 0 ;
+static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_1 = 1 ;
+static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_2 = 2 ;
+static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_3 = 3 ;
+static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_4 = 4 ;
+static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_5 = 5 ;
+static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_6 = 6 ;
+static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_7 = 7 ;
+static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_8 = 8 ;
+static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_9 = 9 ;
+static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_10 = 10 ;
+static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_11 = 11 ;
+static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_12 = 12 ;
+static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_13 = 13 ;
+static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_14 = 14 ;
+static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_15 = 15 ;
+static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_16 = 16 ;
+static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_17 = 17 ;
+static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_18 = 18 ;
+static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_19 = 19 ;
+static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_20 = 20 ;
+static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_21 = 21 ;
+static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_22 = 22 ;
+static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_23 = 23 ;
+static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_24 = 24 ;
+static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_25 = 25 ;
+static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_26 = 26 ;
+static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_27 = 27 ;
+static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_28 = 28 ;
+static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_29 = 29 ;
+static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_30 = 30 ;
+static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_31 = 31 ;
+static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_32 = 32 ;
+static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_33 = 33 ;
+static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_34 = 34 ;
+static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_35 = 35 ;
+static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_36 = 36 ;
+static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_37 = 37 ;
+static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_38 = 38 ;
+static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_39 = 39 ;
+static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_40 = 40 ;
+static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_41 = 41 ;
+static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_42 = 42 ;
+static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_43 = 43 ;
+static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_44 = 44 ;
+static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_45 = 45 ;
+static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_46 = 46 ;
+static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_47 = 47 ;
+static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_48 = 48 ;
+static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_49 = 49 ;
+static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_50 = 50 ;
+static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_51 = 51 ;
+static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_52 = 52 ;
+static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_53 = 53 ;
+static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_54 = 54 ;
+static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_55 = 55 ;
+static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_56 = 56 ;
+static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_57 = 57 ;
+static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_58 = 58 ;
+static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_59 = 59 ;
+static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_60 = 60 ;
+static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_61 = 61 ;
+static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_62 = 62 ;
+static const uint8_t P9N2__SM0_CERR_FIRST2_NTL_63 = 63 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_0 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_1 = 1 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_2 = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_3 = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_4 = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_5 = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_6 = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_7 = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_8 = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_9 = 9 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_10 = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_11 = 11 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_12 = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_13 = 13 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_14 = 14 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_15 = 15 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_16 = 16 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_17 = 17 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_18 = 18 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_19 = 19 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_20 = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_21 = 21 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_22 = 22 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_23 = 23 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_24 = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_25 = 25 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_26 = 26 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_27 = 27 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_28 = 28 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_29 = 29 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_30 = 30 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_31 = 31 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_32 = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_33 = 33 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_34 = 34 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_35 = 35 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_36 = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_37 = 37 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_38 = 38 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_39 = 39 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_40 = 40 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_41 = 41 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_42 = 42 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_43 = 43 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_44 = 44 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_45 = 45 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_46 = 46 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_47 = 47 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_48 = 48 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_49 = 49 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_50 = 50 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_51 = 51 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_52 = 52 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_53 = 53 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_54 = 54 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_55 = 55 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_56 = 56 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_57 = 57 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_58 = 58 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_59 = 59 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_60 = 60 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_61 = 61 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_62 = 62 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_FIRST2_IDIAL_SM_FIRST_NLG_63 = 63 ;
+
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_0 = 0 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_1 = 1 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_2 = 2 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_3 = 3 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_4 = 4 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_5 = 5 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_6 = 6 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_7 = 7 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_8 = 8 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_9 = 9 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_10 = 10 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_11 = 11 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_12 = 12 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_13 = 13 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_14 = 14 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_15 = 15 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_16 = 16 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_17 = 17 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_18 = 18 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_19 = 19 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_20 = 20 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_21 = 21 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_22 = 22 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_23 = 23 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_24 = 24 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_25 = 25 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_26 = 26 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_27 = 27 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_28 = 28 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_29 = 29 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_30 = 30 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_31 = 31 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_32 = 32 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_33 = 33 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_34 = 34 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_35 = 35 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_36 = 36 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_37 = 37 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_38 = 38 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_39 = 39 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_40 = 40 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_41 = 41 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_42 = 42 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_43 = 43 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_44 = 44 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_45 = 45 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_46 = 46 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_47 = 47 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_48 = 48 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_49 = 49 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_50 = 50 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_51 = 51 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_52 = 52 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_53 = 53 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_54 = 54 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_55 = 55 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_56 = 56 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_57 = 57 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_58 = 58 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_59 = 59 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_60 = 60 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_61 = 61 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_62 = 62 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST2_NTL_63 = 63 ;
+
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_0 = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_1 = 1 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_2 = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_3 = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_4 = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_5 = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_6 = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_7 = 7 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_8 = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_9 = 9 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_10 = 10 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_11 = 11 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_12 = 12 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_13 = 13 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_14 = 14 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_15 = 15 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_16 = 16 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_17 = 17 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_18 = 18 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_19 = 19 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_20 = 20 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_21 = 21 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_22 = 22 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_23 = 23 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_24 = 24 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_25 = 25 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_26 = 26 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_27 = 27 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_28 = 28 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_29 = 29 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_30 = 30 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_31 = 31 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_32 = 32 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_33 = 33 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_34 = 34 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_35 = 35 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_36 = 36 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_37 = 37 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_38 = 38 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_39 = 39 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_40 = 40 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_41 = 41 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_42 = 42 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_43 = 43 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_44 = 44 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_45 = 45 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_46 = 46 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_47 = 47 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_48 = 48 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_49 = 49 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_50 = 50 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_51 = 51 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_52 = 52 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_53 = 53 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_54 = 54 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_55 = 55 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_56 = 56 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_57 = 57 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_58 = 58 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_59 = 59 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_60 = 60 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_61 = 61 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_62 = 62 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_63 = 63 ;
+
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_0 = 0 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_1 = 1 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_2 = 2 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_3 = 3 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_4 = 4 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_5 = 5 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_6 = 6 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_7 = 7 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_8 = 8 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_9 = 9 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_10 = 10 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_11 = 11 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_12 = 12 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_13 = 13 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_14 = 14 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_15 = 15 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_16 = 16 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_17 = 17 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_18 = 18 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_19 = 19 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_20 = 20 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_21 = 21 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_22 = 22 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_23 = 23 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_24 = 24 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_25 = 25 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_26 = 26 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_27 = 27 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_28 = 28 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_29 = 29 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_30 = 30 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_31 = 31 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_32 = 32 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_33 = 33 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_34 = 34 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_35 = 35 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_36 = 36 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_37 = 37 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_38 = 38 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_39 = 39 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_40 = 40 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_41 = 41 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_42 = 42 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_43 = 43 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_44 = 44 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_45 = 45 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_46 = 46 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_47 = 47 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_48 = 48 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_49 = 49 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_50 = 50 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_51 = 51 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_52 = 52 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_53 = 53 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_54 = 54 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_55 = 55 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_56 = 56 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_57 = 57 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_58 = 58 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_59 = 59 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_60 = 60 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_61 = 61 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_62 = 62 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST2_NTL_63 = 63 ;
+
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_0 = 0 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_1 = 1 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_2 = 2 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_3 = 3 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_4 = 4 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_5 = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_6 = 6 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_7 = 7 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_8 = 8 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_9 = 9 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_10 = 10 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_11 = 11 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_12 = 12 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_13 = 13 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_14 = 14 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_15 = 15 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_16 = 16 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_17 = 17 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_18 = 18 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_19 = 19 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_20 = 20 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_21 = 21 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_22 = 22 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_23 = 23 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_24 = 24 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_25 = 25 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_26 = 26 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_27 = 27 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_28 = 28 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_29 = 29 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_30 = 30 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_31 = 31 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_32 = 32 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_33 = 33 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_34 = 34 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_35 = 35 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_36 = 36 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_37 = 37 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_38 = 38 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_39 = 39 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_40 = 40 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_41 = 41 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_42 = 42 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_43 = 43 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_44 = 44 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_45 = 45 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_46 = 46 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_47 = 47 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_48 = 48 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_49 = 49 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_50 = 50 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_51 = 51 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_52 = 52 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_53 = 53 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_54 = 54 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_55 = 55 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_56 = 56 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_57 = 57 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_58 = 58 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_59 = 59 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_60 = 60 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_61 = 61 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_62 = 62 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST2_NTL_63 = 63 ;
+
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_0 = 0 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_1 = 1 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_2 = 2 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_3 = 3 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_4 = 4 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_5 = 5 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_6 = 6 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_7 = 7 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_8 = 8 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_9 = 9 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_10 = 10 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_11 = 11 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_12 = 12 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_13 = 13 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_14 = 14 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_15 = 15 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_16 = 16 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_17 = 17 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_18 = 18 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_19 = 19 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_20 = 20 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_21 = 21 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_22 = 22 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_23 = 23 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_24 = 24 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_25 = 25 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_26 = 26 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_27 = 27 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_28 = 28 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_29 = 29 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_30 = 30 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_31 = 31 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_32 = 32 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_33 = 33 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_34 = 34 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_35 = 35 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_36 = 36 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_37 = 37 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_38 = 38 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_39 = 39 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_40 = 40 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_41 = 41 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_42 = 42 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_43 = 43 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_44 = 44 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_45 = 45 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_46 = 46 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_47 = 47 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_48 = 48 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_49 = 49 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_50 = 50 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_51 = 51 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_52 = 52 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_53 = 53 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_54 = 54 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_55 = 55 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_56 = 56 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_57 = 57 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_58 = 58 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_59 = 59 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_60 = 60 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_61 = 61 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_62 = 62 ;
+static const uint8_t P9N2_PU_NPU2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_63 = 63 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_0 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_1 = 1 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_2 = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_3 = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_4 = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_5 = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_6 = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_7 = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_8 = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_9 = 9 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_10 = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_11 = 11 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_12 = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_13 = 13 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_14 = 14 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_15 = 15 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_16 = 16 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_17 = 17 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_18 = 18 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_19 = 19 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_20 = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_21 = 21 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_22 = 22 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_23 = 23 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_24 = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_25 = 25 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_26 = 26 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_27 = 27 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_28 = 28 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_29 = 29 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_30 = 30 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_31 = 31 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_32 = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_33 = 33 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_34 = 34 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_35 = 35 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_36 = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_37 = 37 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_38 = 38 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_39 = 39 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_40 = 40 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_41 = 41 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_42 = 42 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_43 = 43 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_44 = 44 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_45 = 45 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_46 = 46 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_47 = 47 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_48 = 48 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_49 = 49 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_50 = 50 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_51 = 51 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_52 = 52 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_53 = 53 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_54 = 54 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_55 = 55 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_56 = 56 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_57 = 57 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_58 = 58 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_59 = 59 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_60 = 60 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_61 = 61 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_62 = 62 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_63 = 63 ;
+
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_0 = 0 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_1 = 1 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_2 = 2 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_3 = 3 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_4 = 4 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_5 = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_6 = 6 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_7 = 7 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_8 = 8 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_9 = 9 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_10 = 10 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_11 = 11 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_12 = 12 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_13 = 13 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_14 = 14 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_15 = 15 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_16 = 16 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_17 = 17 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_18 = 18 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_19 = 19 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_20 = 20 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_21 = 21 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_22 = 22 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_23 = 23 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_24 = 24 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_25 = 25 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_26 = 26 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_27 = 27 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_28 = 28 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_29 = 29 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_30 = 30 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_31 = 31 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_32 = 32 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_33 = 33 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_34 = 34 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_35 = 35 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_36 = 36 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_37 = 37 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_38 = 38 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_39 = 39 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_40 = 40 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_41 = 41 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_42 = 42 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_43 = 43 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_44 = 44 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_45 = 45 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_46 = 46 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_47 = 47 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_48 = 48 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_49 = 49 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_50 = 50 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_51 = 51 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_52 = 52 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_53 = 53 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_54 = 54 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_55 = 55 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_56 = 56 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_57 = 57 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_58 = 58 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_59 = 59 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_60 = 60 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_61 = 61 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_62 = 62 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK1_NTL_63 = 63 ;
+
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_0 = 0 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_1 = 1 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_2 = 2 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_3 = 3 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_4 = 4 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_5 = 5 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_6 = 6 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_7 = 7 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_8 = 8 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_9 = 9 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_10 = 10 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_11 = 11 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_12 = 12 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_13 = 13 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_14 = 14 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_15 = 15 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_16 = 16 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_17 = 17 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_18 = 18 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_19 = 19 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_20 = 20 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_21 = 21 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_22 = 22 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_23 = 23 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_24 = 24 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_25 = 25 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_26 = 26 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_27 = 27 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_28 = 28 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_29 = 29 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_30 = 30 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_31 = 31 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_32 = 32 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_33 = 33 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_34 = 34 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_35 = 35 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_36 = 36 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_37 = 37 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_38 = 38 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_39 = 39 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_40 = 40 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_41 = 41 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_42 = 42 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_43 = 43 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_44 = 44 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_45 = 45 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_46 = 46 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_47 = 47 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_48 = 48 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_49 = 49 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_50 = 50 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_51 = 51 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_52 = 52 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_53 = 53 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_54 = 54 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_55 = 55 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_56 = 56 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_57 = 57 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_58 = 58 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_59 = 59 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_60 = 60 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_61 = 61 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_62 = 62 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK1_NTL_63 = 63 ;
+
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_0 = 0 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_1 = 1 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_2 = 2 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_3 = 3 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_4 = 4 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_5 = 5 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_6 = 6 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_7 = 7 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_8 = 8 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_9 = 9 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_10 = 10 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_11 = 11 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_12 = 12 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_13 = 13 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_14 = 14 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_15 = 15 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_16 = 16 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_17 = 17 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_18 = 18 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_19 = 19 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_20 = 20 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_21 = 21 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_22 = 22 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_23 = 23 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_24 = 24 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_25 = 25 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_26 = 26 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_27 = 27 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_28 = 28 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_29 = 29 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_30 = 30 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_31 = 31 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_32 = 32 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_33 = 33 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_34 = 34 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_35 = 35 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_36 = 36 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_37 = 37 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_38 = 38 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_39 = 39 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_40 = 40 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_41 = 41 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_42 = 42 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_43 = 43 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_44 = 44 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_45 = 45 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_46 = 46 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_47 = 47 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_48 = 48 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_49 = 49 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_50 = 50 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_51 = 51 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_52 = 52 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_53 = 53 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_54 = 54 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_55 = 55 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_56 = 56 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_57 = 57 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_58 = 58 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_59 = 59 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_60 = 60 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_61 = 61 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_62 = 62 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK1_NTL_63 = 63 ;
+
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_0 = 0 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_1 = 1 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_2 = 2 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_3 = 3 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_4 = 4 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_5 = 5 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_6 = 6 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_7 = 7 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_8 = 8 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_9 = 9 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_10 = 10 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_11 = 11 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_12 = 12 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_13 = 13 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_14 = 14 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_15 = 15 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_16 = 16 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_17 = 17 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_18 = 18 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_19 = 19 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_20 = 20 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_21 = 21 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_22 = 22 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_23 = 23 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_24 = 24 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_25 = 25 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_26 = 26 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_27 = 27 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_28 = 28 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_29 = 29 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_30 = 30 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_31 = 31 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_32 = 32 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_33 = 33 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_34 = 34 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_35 = 35 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_36 = 36 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_37 = 37 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_38 = 38 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_39 = 39 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_40 = 40 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_41 = 41 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_42 = 42 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_43 = 43 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_44 = 44 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_45 = 45 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_46 = 46 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_47 = 47 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_48 = 48 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_49 = 49 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_50 = 50 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_51 = 51 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_52 = 52 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_53 = 53 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_54 = 54 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_55 = 55 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_56 = 56 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_57 = 57 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_58 = 58 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_59 = 59 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_60 = 60 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_61 = 61 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_62 = 62 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK1_NTL_63 = 63 ;
+
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_0 = 0 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_1 = 1 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_2 = 2 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_3 = 3 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_4 = 4 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_5 = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_6 = 6 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_7 = 7 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_8 = 8 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_9 = 9 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_10 = 10 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_11 = 11 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_12 = 12 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_13 = 13 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_14 = 14 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_15 = 15 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_16 = 16 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_17 = 17 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_18 = 18 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_19 = 19 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_20 = 20 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_21 = 21 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_22 = 22 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_23 = 23 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_24 = 24 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_25 = 25 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_26 = 26 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_27 = 27 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_28 = 28 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_29 = 29 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_30 = 30 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_31 = 31 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_32 = 32 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_33 = 33 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_34 = 34 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_35 = 35 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_36 = 36 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_37 = 37 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_38 = 38 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_39 = 39 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_40 = 40 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_41 = 41 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_42 = 42 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_43 = 43 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_44 = 44 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_45 = 45 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_46 = 46 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_47 = 47 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_48 = 48 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_49 = 49 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_50 = 50 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_51 = 51 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_52 = 52 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_53 = 53 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_54 = 54 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_55 = 55 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_56 = 56 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_57 = 57 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_58 = 58 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_59 = 59 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_60 = 60 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_61 = 61 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_62 = 62 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK1_NTL_63 = 63 ;
+
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_0 = 0 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_1 = 1 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_2 = 2 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_3 = 3 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_4 = 4 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_5 = 5 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_6 = 6 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_7 = 7 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_8 = 8 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_9 = 9 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_10 = 10 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_11 = 11 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_12 = 12 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_13 = 13 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_14 = 14 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_15 = 15 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_16 = 16 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_17 = 17 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_18 = 18 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_19 = 19 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_20 = 20 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_21 = 21 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_22 = 22 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_23 = 23 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_24 = 24 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_25 = 25 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_26 = 26 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_27 = 27 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_28 = 28 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_29 = 29 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_30 = 30 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_31 = 31 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_32 = 32 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_33 = 33 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_34 = 34 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_35 = 35 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_36 = 36 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_37 = 37 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_38 = 38 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_39 = 39 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_40 = 40 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_41 = 41 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_42 = 42 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_43 = 43 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_44 = 44 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_45 = 45 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_46 = 46 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_47 = 47 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_48 = 48 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_49 = 49 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_50 = 50 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_51 = 51 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_52 = 52 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_53 = 53 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_54 = 54 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_55 = 55 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_56 = 56 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_57 = 57 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_58 = 58 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_59 = 59 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_60 = 60 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_61 = 61 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_62 = 62 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK1_NTL_63 = 63 ;
+
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_0 = 0 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_1 = 1 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_2 = 2 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_3 = 3 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_4 = 4 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_5 = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_6 = 6 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_7 = 7 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_8 = 8 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_9 = 9 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_10 = 10 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_11 = 11 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_12 = 12 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_13 = 13 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_14 = 14 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_15 = 15 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_16 = 16 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_17 = 17 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_18 = 18 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_19 = 19 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_20 = 20 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_21 = 21 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_22 = 22 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_23 = 23 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_24 = 24 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_25 = 25 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_26 = 26 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_27 = 27 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_28 = 28 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_29 = 29 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_30 = 30 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_31 = 31 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_32 = 32 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_33 = 33 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_34 = 34 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_35 = 35 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_36 = 36 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_37 = 37 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_38 = 38 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_39 = 39 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_40 = 40 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_41 = 41 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_42 = 42 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_43 = 43 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_44 = 44 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_45 = 45 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_46 = 46 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_47 = 47 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_48 = 48 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_49 = 49 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_50 = 50 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_51 = 51 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_52 = 52 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_53 = 53 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_54 = 54 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_55 = 55 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_56 = 56 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_57 = 57 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_58 = 58 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_59 = 59 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_60 = 60 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_61 = 61 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_62 = 62 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_FIRST_MASK2_NTL_63 = 63 ;
+
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_0 = 0 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_1 = 1 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_2 = 2 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_3 = 3 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_4 = 4 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_5 = 5 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_6 = 6 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_7 = 7 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_8 = 8 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_9 = 9 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_10 = 10 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_11 = 11 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_12 = 12 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_13 = 13 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_14 = 14 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_15 = 15 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_16 = 16 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_17 = 17 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_18 = 18 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_19 = 19 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_20 = 20 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_21 = 21 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_22 = 22 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_23 = 23 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_24 = 24 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_25 = 25 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_26 = 26 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_27 = 27 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_28 = 28 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_29 = 29 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_30 = 30 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_31 = 31 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_32 = 32 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_33 = 33 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_34 = 34 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_35 = 35 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_36 = 36 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_37 = 37 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_38 = 38 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_39 = 39 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_40 = 40 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_41 = 41 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_42 = 42 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_43 = 43 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_44 = 44 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_45 = 45 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_46 = 46 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_47 = 47 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_48 = 48 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_49 = 49 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_50 = 50 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_51 = 51 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_52 = 52 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_53 = 53 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_54 = 54 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_55 = 55 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_56 = 56 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_57 = 57 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_58 = 58 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_59 = 59 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_60 = 60 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_61 = 61 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_62 = 62 ;
+static const uint8_t P9N2__SM0_CERR_FIRST_MASK2_NTL_63 = 63 ;
+
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_0 = 0 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_1 = 1 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_2 = 2 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_3 = 3 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_4 = 4 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_5 = 5 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_6 = 6 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_7 = 7 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_8 = 8 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_9 = 9 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_10 = 10 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_11 = 11 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_12 = 12 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_13 = 13 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_14 = 14 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_15 = 15 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_16 = 16 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_17 = 17 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_18 = 18 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_19 = 19 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_20 = 20 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_21 = 21 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_22 = 22 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_23 = 23 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_24 = 24 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_25 = 25 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_26 = 26 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_27 = 27 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_28 = 28 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_29 = 29 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_30 = 30 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_31 = 31 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_32 = 32 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_33 = 33 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_34 = 34 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_35 = 35 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_36 = 36 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_37 = 37 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_38 = 38 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_39 = 39 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_40 = 40 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_41 = 41 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_42 = 42 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_43 = 43 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_44 = 44 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_45 = 45 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_46 = 46 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_47 = 47 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_48 = 48 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_49 = 49 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_50 = 50 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_51 = 51 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_52 = 52 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_53 = 53 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_54 = 54 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_55 = 55 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_56 = 56 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_57 = 57 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_58 = 58 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_59 = 59 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_60 = 60 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_61 = 61 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_62 = 62 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_FIRST_MASK2_NTL_63 = 63 ;
+
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_0 = 0 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_1 = 1 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_2 = 2 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_3 = 3 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_4 = 4 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_5 = 5 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_6 = 6 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_7 = 7 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_8 = 8 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_9 = 9 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_10 = 10 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_11 = 11 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_12 = 12 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_13 = 13 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_14 = 14 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_15 = 15 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_16 = 16 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_17 = 17 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_18 = 18 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_19 = 19 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_20 = 20 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_21 = 21 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_22 = 22 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_23 = 23 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_24 = 24 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_25 = 25 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_26 = 26 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_27 = 27 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_28 = 28 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_29 = 29 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_30 = 30 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_31 = 31 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_32 = 32 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_33 = 33 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_34 = 34 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_35 = 35 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_36 = 36 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_37 = 37 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_38 = 38 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_39 = 39 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_40 = 40 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_41 = 41 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_42 = 42 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_43 = 43 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_44 = 44 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_45 = 45 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_46 = 46 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_47 = 47 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_48 = 48 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_49 = 49 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_50 = 50 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_51 = 51 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_52 = 52 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_53 = 53 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_54 = 54 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_55 = 55 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_56 = 56 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_57 = 57 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_58 = 58 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_59 = 59 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_60 = 60 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_61 = 61 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_62 = 62 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_FIRST_MASK2_NTL_63 = 63 ;
+
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_0 = 0 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_1 = 1 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_2 = 2 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_3 = 3 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_4 = 4 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_5 = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_6 = 6 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_7 = 7 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_8 = 8 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_9 = 9 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_10 = 10 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_11 = 11 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_12 = 12 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_13 = 13 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_14 = 14 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_15 = 15 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_16 = 16 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_17 = 17 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_18 = 18 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_19 = 19 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_20 = 20 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_21 = 21 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_22 = 22 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_23 = 23 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_24 = 24 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_25 = 25 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_26 = 26 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_27 = 27 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_28 = 28 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_29 = 29 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_30 = 30 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_31 = 31 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_32 = 32 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_33 = 33 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_34 = 34 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_35 = 35 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_36 = 36 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_37 = 37 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_38 = 38 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_39 = 39 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_40 = 40 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_41 = 41 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_42 = 42 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_43 = 43 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_44 = 44 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_45 = 45 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_46 = 46 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_47 = 47 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_48 = 48 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_49 = 49 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_50 = 50 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_51 = 51 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_52 = 52 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_53 = 53 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_54 = 54 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_55 = 55 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_56 = 56 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_57 = 57 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_58 = 58 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_59 = 59 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_60 = 60 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_61 = 61 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_62 = 62 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_FIRST_MASK2_NTL_63 = 63 ;
+
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_0 = 0 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_1 = 1 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_2 = 2 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_3 = 3 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_4 = 4 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_5 = 5 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_6 = 6 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_7 = 7 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_8 = 8 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_9 = 9 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_10 = 10 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_11 = 11 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_12 = 12 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_13 = 13 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_14 = 14 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_15 = 15 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_16 = 16 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_17 = 17 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_18 = 18 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_19 = 19 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_20 = 20 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_21 = 21 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_22 = 22 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_23 = 23 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_24 = 24 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_25 = 25 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_26 = 26 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_27 = 27 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_28 = 28 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_29 = 29 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_30 = 30 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_31 = 31 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_32 = 32 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_33 = 33 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_34 = 34 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_35 = 35 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_36 = 36 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_37 = 37 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_38 = 38 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_39 = 39 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_40 = 40 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_41 = 41 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_42 = 42 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_43 = 43 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_44 = 44 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_45 = 45 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_46 = 46 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_47 = 47 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_48 = 48 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_49 = 49 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_50 = 50 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_51 = 51 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_52 = 52 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_53 = 53 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_54 = 54 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_55 = 55 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_56 = 56 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_57 = 57 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_58 = 58 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_59 = 59 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_60 = 60 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_61 = 61 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_62 = 62 ;
+static const uint8_t P9N2__SM1_CERR_FIRST_MASK2_NTL_63 = 63 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_1 = 1 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_2 = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_3 = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_4 = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_5 = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_6 = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_7 = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_8 = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_9 = 9 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_10 = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_11 = 11 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_12 = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_13 = 13 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_14 = 14 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_15 = 15 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_16 = 16 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_17 = 17 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_18 = 18 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_19 = 19 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_20 = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_21 = 21 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_22 = 22 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_23 = 23 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_0 = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_1 = 25 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_2 = 26 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_3 = 27 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_4 = 28 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_5 = 29 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_6 = 30 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_7 = 31 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_0 = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_1 = 33 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_2 = 34 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_3 = 35 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_0 = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_1 = 37 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_2 = 38 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_3 = 39 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_4 = 40 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_5 = 41 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_6 = 42 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_7 = 43 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_REG_0 = 44 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_REG_1 = 45 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_REG_2 = 46 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_REG_3 = 47 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_0 = 48 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_1 = 49 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_2 = 50 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_3 = 51 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_4 = 52 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_5 = 53 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_6 = 54 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_7 = 55 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_8 = 56 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_9 = 57 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_10 = 58 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_11 = 59 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_12 = 60 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_13 = 61 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_14 = 62 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_15 = 63 ;
+
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0 = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_1 = 1 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_2 = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_3 = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_4 = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_5 = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_6 = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_7 = 7 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_8 = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_9 = 9 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_10 = 10 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_11 = 11 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_12 = 12 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_13 = 13 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_14 = 14 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_15 = 15 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_16 = 16 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_17 = 17 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_18 = 18 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_19 = 19 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_20 = 20 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_21 = 21 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_22 = 22 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_23 = 23 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_0 = 24 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_1 = 25 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_2 = 26 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_3 = 27 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_4 = 28 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_5 = 29 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_6 = 30 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_7 = 31 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_0 = 32 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_1 = 33 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_2 = 34 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_3 = 35 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_0 = 36 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_1 = 37 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_2 = 38 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_3 = 39 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_4 = 40 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_5 = 41 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_6 = 42 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_7 = 43 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_REG_0 = 44 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_REG_1 = 45 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_REG_2 = 46 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_REG_3 = 47 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_0 = 48 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_1 = 49 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_2 = 50 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_3 = 51 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_4 = 52 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_5 = 53 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_6 = 54 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_7 = 55 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_8 = 56 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_9 = 57 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_10 = 58 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_11 = 59 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_12 = 60 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_13 = 61 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_14 = 62 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_15 = 63 ;
+
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_0 = 0 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_1 = 1 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_2 = 2 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_3 = 3 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_4 = 4 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_5 = 5 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_6 = 6 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_7 = 7 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_0 = 8 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_1 = 9 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_2 = 10 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_3 = 11 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_4 = 12 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_5 = 13 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_6 = 14 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_7 = 15 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_8 = 16 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_9 = 17 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_10 = 18 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_11 = 19 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_12 = 20 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_13 = 21 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_14 = 22 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_15 = 23 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_16 = 24 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_17 = 25 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_18 = 26 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_19 = 27 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_OCR_0 = 28 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_OCR_1 = 29 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_OCR_2 = 30 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_OCR_3 = 31 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_OCR_4 = 32 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_OCR_5 = 33 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_OCR_6 = 34 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_OCR_7 = 35 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_0 = 36 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_1 = 37 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_2 = 38 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_3 = 39 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_4 = 40 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_5 = 41 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_6 = 42 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_7 = 43 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_0 = 44 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_1 = 45 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_2 = 46 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_3 = 47 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_4 = 48 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_5 = 49 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_6 = 50 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_7 = 51 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_REG_0 = 52 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_REG_1 = 53 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_REG_2 = 54 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_REG_3 = 55 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_DUE_0 = 56 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_DUE_1 = 57 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_DUE_2 = 58 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_DUE_3 = 59 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_PEF_0 = 60 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_PEF_1 = 61 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_PEF_2 = 62 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD0_IDIAL_CTL_HOLD_PEF_3 = 63 ;
+
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0 = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_1 = 1 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_2 = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_3 = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_4 = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_5 = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_6 = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_7 = 7 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_8 = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_9 = 9 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_10 = 10 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_11 = 11 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_12 = 12 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_13 = 13 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_14 = 14 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_15 = 15 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_16 = 16 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_17 = 17 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_18 = 18 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_19 = 19 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_20 = 20 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_21 = 21 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_22 = 22 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_23 = 23 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_0 = 24 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_1 = 25 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_2 = 26 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_3 = 27 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_4 = 28 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_5 = 29 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_6 = 30 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_7 = 31 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_0 = 32 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_1 = 33 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_2 = 34 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_3 = 35 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_0 = 36 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_1 = 37 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_2 = 38 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_3 = 39 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_4 = 40 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_5 = 41 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_6 = 42 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_7 = 43 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_REG_0 = 44 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_REG_1 = 45 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_REG_2 = 46 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_REG_3 = 47 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_0 = 48 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_1 = 49 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_2 = 50 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_3 = 51 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_4 = 52 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_5 = 53 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_6 = 54 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_7 = 55 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_8 = 56 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_9 = 57 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_10 = 58 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_11 = 59 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_12 = 60 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_13 = 61 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_14 = 62 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_15 = 63 ;
+
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0 = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_1 = 1 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_2 = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_3 = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_4 = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_5 = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_6 = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_7 = 7 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_8 = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_9 = 9 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_10 = 10 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_11 = 11 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_12 = 12 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_13 = 13 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_14 = 14 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_15 = 15 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_16 = 16 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_17 = 17 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_18 = 18 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_19 = 19 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_20 = 20 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_21 = 21 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_22 = 22 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_23 = 23 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_0 = 24 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_1 = 25 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_2 = 26 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_3 = 27 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_4 = 28 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_5 = 29 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_6 = 30 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_7 = 31 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_0 = 32 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_1 = 33 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_2 = 34 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_3 = 35 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_0 = 36 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_1 = 37 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_2 = 38 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_3 = 39 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_4 = 40 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_5 = 41 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_6 = 42 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_7 = 43 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_REG_0 = 44 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_REG_1 = 45 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_REG_2 = 46 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_REG_3 = 47 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_0 = 48 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_1 = 49 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_2 = 50 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_3 = 51 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_4 = 52 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_5 = 53 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_6 = 54 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_7 = 55 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_8 = 56 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_9 = 57 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_10 = 58 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_11 = 59 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_12 = 60 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_13 = 61 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_14 = 62 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_15 = 63 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_1 = 1 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_2 = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_3 = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_4 = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_5 = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_6 = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_7 = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_8 = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_9 = 9 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_10 = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_11 = 11 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_12 = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_13 = 13 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_14 = 14 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_15 = 15 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_16 = 16 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_17 = 17 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_18 = 18 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_19 = 19 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_20 = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_21 = 21 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_22 = 22 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_23 = 23 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_0 = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_1 = 25 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_2 = 26 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_3 = 27 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_4 = 28 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_5 = 29 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_6 = 30 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_7 = 31 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_0 = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_1 = 33 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_2 = 34 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_3 = 35 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_0 = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_1 = 37 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_2 = 38 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_3 = 39 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_4 = 40 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_5 = 41 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_6 = 42 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_7 = 43 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_REG_0 = 44 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_REG_1 = 45 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_REG_2 = 46 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_REG_3 = 47 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_0 = 48 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_1 = 49 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_2 = 50 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_3 = 51 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_4 = 52 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_5 = 53 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_6 = 54 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_7 = 55 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_8 = 56 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_9 = 57 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_10 = 58 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_11 = 59 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_12 = 60 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_13 = 61 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_14 = 62 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_15 = 63 ;
+
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0 = 0 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_1 = 1 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_2 = 2 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_3 = 3 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_4 = 4 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_5 = 5 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_6 = 6 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_7 = 7 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_8 = 8 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_9 = 9 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_10 = 10 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_11 = 11 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_12 = 12 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_13 = 13 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_14 = 14 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_15 = 15 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_16 = 16 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_17 = 17 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_18 = 18 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_19 = 19 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_20 = 20 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_21 = 21 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_22 = 22 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_23 = 23 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_0 = 24 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_1 = 25 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_2 = 26 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_3 = 27 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_4 = 28 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_5 = 29 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_6 = 30 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_7 = 31 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_0 = 32 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_1 = 33 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_2 = 34 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_3 = 35 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_0 = 36 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_1 = 37 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_2 = 38 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_3 = 39 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_4 = 40 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_5 = 41 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_6 = 42 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_7 = 43 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_REG_0 = 44 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_REG_1 = 45 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_REG_2 = 46 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_REG_3 = 47 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_0 = 48 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_1 = 49 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_2 = 50 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_3 = 51 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_4 = 52 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_5 = 53 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_6 = 54 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_7 = 55 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_8 = 56 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_9 = 57 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_10 = 58 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_11 = 59 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_12 = 60 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_13 = 61 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_14 = 62 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_15 = 63 ;
+
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0 = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_1 = 1 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_2 = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_3 = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_4 = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_5 = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_6 = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_7 = 7 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_8 = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_9 = 9 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_10 = 10 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_11 = 11 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_12 = 12 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_13 = 13 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_14 = 14 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_15 = 15 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_16 = 16 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_17 = 17 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_18 = 18 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_19 = 19 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_20 = 20 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_21 = 21 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_22 = 22 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_23 = 23 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_0 = 24 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_1 = 25 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_2 = 26 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_3 = 27 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_4 = 28 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_5 = 29 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_6 = 30 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_7 = 31 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_0 = 32 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_1 = 33 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_2 = 34 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_3 = 35 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_0 = 36 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_1 = 37 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_2 = 38 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_3 = 39 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_4 = 40 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_5 = 41 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_6 = 42 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_7 = 43 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_REG_0 = 44 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_REG_1 = 45 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_REG_2 = 46 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_REG_3 = 47 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_0 = 48 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_1 = 49 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_2 = 50 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_3 = 51 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_4 = 52 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_5 = 53 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_6 = 54 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_7 = 55 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_8 = 56 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_9 = 57 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_10 = 58 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_11 = 59 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_12 = 60 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_13 = 61 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_14 = 62 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_15 = 63 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_NVF_1 = 1 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_NVF_2 = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_NVF_3 = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_NVF_4 = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_NVF_5 = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_NVF_6 = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_NVF_7 = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_NVF_8 = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_NVF_9 = 9 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_NVF_10 = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_NVF_11 = 11 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_NVF_12 = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_NVF_13 = 13 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_NVF_14 = 14 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_NVF_15 = 15 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_NVF_16 = 16 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_NVF_17 = 17 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_NVF_18 = 18 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_NVF_19 = 19 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_NVF_20 = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_NVF_21 = 21 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_NVF_22 = 22 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_NVF_23 = 23 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_NCF_0 = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_NCF_1 = 25 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_NCF_2 = 26 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_NCF_3 = 27 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_NCF_4 = 28 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_NCF_5 = 29 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_NCF_6 = 30 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_NCF_7 = 31 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_0 = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_1 = 33 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_2 = 34 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_3 = 35 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_PBR_0 = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_PBR_1 = 37 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_PBR_2 = 38 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_PBR_3 = 39 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_PBR_4 = 40 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_PBR_5 = 41 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_PBR_6 = 42 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_PBR_7 = 43 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_REG_0 = 44 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_REG_1 = 45 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_REG_2 = 46 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_REG_3 = 47 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_OCR_0 = 48 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_OCR_1 = 49 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_OCR_2 = 50 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_OCR_3 = 51 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_OCR_4 = 52 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_OCR_5 = 53 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_OCR_6 = 54 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_OCR_7 = 55 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_OCR_8 = 56 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_OCR_9 = 57 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_OCR_10 = 58 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_OCR_11 = 59 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_OCR_12 = 60 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_OCR_13 = 61 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_OCR_14 = 62 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD0_IDIAL_SM_HOLD_OCR_15 = 63 ;
+
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0 = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_1 = 1 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_2 = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_3 = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_4 = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_5 = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_6 = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_7 = 7 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_8 = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_9 = 9 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_10 = 10 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_11 = 11 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_12 = 12 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_13 = 13 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_14 = 14 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_15 = 15 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_16 = 16 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_17 = 17 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_18 = 18 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_19 = 19 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_20 = 20 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_21 = 21 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_22 = 22 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_23 = 23 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_0 = 24 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_1 = 25 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_2 = 26 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_3 = 27 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_4 = 28 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_5 = 29 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_6 = 30 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_7 = 31 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_0 = 32 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_1 = 33 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_2 = 34 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_3 = 35 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_0 = 36 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_1 = 37 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_2 = 38 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_3 = 39 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_4 = 40 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_5 = 41 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_6 = 42 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_7 = 43 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_REG_0 = 44 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_REG_1 = 45 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_REG_2 = 46 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_REG_3 = 47 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_0 = 48 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_1 = 49 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_2 = 50 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_3 = 51 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_4 = 52 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_5 = 53 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_6 = 54 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_7 = 55 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_8 = 56 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_9 = 57 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_10 = 58 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_11 = 59 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_12 = 60 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_13 = 61 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_14 = 62 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_15 = 63 ;
+
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0 = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_1 = 1 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_2 = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_3 = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_4 = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_5 = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_6 = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_7 = 7 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_8 = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_9 = 9 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_10 = 10 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_11 = 11 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_12 = 12 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_13 = 13 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_14 = 14 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_15 = 15 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_16 = 16 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_17 = 17 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_18 = 18 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_19 = 19 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_20 = 20 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_21 = 21 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_22 = 22 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_23 = 23 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_0 = 24 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_1 = 25 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_2 = 26 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_3 = 27 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_4 = 28 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_5 = 29 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_6 = 30 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_7 = 31 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_0 = 32 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_1 = 33 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_2 = 34 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_3 = 35 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_0 = 36 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_1 = 37 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_2 = 38 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_3 = 39 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_4 = 40 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_5 = 41 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_6 = 42 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_7 = 43 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_REG_0 = 44 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_REG_1 = 45 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_REG_2 = 46 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_REG_3 = 47 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_0 = 48 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_1 = 49 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_2 = 50 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_3 = 51 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_4 = 52 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_5 = 53 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_6 = 54 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_7 = 55 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_8 = 56 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_9 = 57 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_10 = 58 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_11 = 59 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_12 = 60 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_13 = 61 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_14 = 62 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_OCR_15 = 63 ;
+
+static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_0 = 0 ;
+static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_1 = 1 ;
+static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_2 = 2 ;
+static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_3 = 3 ;
+static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_4 = 4 ;
+static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_5 = 5 ;
+static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_6 = 6 ;
+static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_7 = 7 ;
+static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_0 = 8 ;
+static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_1 = 9 ;
+static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_2 = 10 ;
+static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_3 = 11 ;
+static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_4 = 12 ;
+static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_5 = 13 ;
+static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_6 = 14 ;
+static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_7 = 15 ;
+static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_8 = 16 ;
+static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_9 = 17 ;
+static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_10 = 18 ;
+static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_11 = 19 ;
+static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_12 = 20 ;
+static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_13 = 21 ;
+static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_14 = 22 ;
+static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_15 = 23 ;
+static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_16 = 24 ;
+static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_17 = 25 ;
+static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_18 = 26 ;
+static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_19 = 27 ;
+static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_OCR_0 = 28 ;
+static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_OCR_1 = 29 ;
+static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_OCR_2 = 30 ;
+static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_OCR_3 = 31 ;
+static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_OCR_4 = 32 ;
+static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_OCR_5 = 33 ;
+static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_OCR_6 = 34 ;
+static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_OCR_7 = 35 ;
+static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_0 = 36 ;
+static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_1 = 37 ;
+static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_2 = 38 ;
+static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_3 = 39 ;
+static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_4 = 40 ;
+static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_5 = 41 ;
+static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_6 = 42 ;
+static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_7 = 43 ;
+static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_0 = 44 ;
+static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_1 = 45 ;
+static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_2 = 46 ;
+static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_3 = 47 ;
+static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_4 = 48 ;
+static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_5 = 49 ;
+static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_6 = 50 ;
+static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_7 = 51 ;
+static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_REG_0 = 52 ;
+static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_REG_1 = 53 ;
+static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_REG_2 = 54 ;
+static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_REG_3 = 55 ;
+static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_DUE_0 = 56 ;
+static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_DUE_1 = 57 ;
+static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_DUE_2 = 58 ;
+static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_DUE_3 = 59 ;
+static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_PEF_0 = 60 ;
+static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_PEF_1 = 61 ;
+static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_PEF_2 = 62 ;
+static const uint8_t P9N2_NV_CERR_HOLD0_IDIAL_CTL_HOLD_PEF_3 = 63 ;
+
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0 = 0 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_1 = 1 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_2 = 2 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_3 = 3 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_4 = 4 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_5 = 5 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_6 = 6 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_7 = 7 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_8 = 8 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_9 = 9 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_10 = 10 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_11 = 11 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_12 = 12 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_13 = 13 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_14 = 14 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_15 = 15 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_16 = 16 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_17 = 17 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_18 = 18 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_19 = 19 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_20 = 20 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_21 = 21 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_22 = 22 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_23 = 23 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_0 = 24 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_1 = 25 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_2 = 26 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_3 = 27 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_4 = 28 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_5 = 29 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_6 = 30 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_7 = 31 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_0 = 32 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_1 = 33 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_2 = 34 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_3 = 35 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_0 = 36 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_1 = 37 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_2 = 38 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_3 = 39 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_4 = 40 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_5 = 41 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_6 = 42 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_7 = 43 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_REG_0 = 44 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_REG_1 = 45 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_REG_2 = 46 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_REG_3 = 47 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_0 = 48 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_1 = 49 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_2 = 50 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_3 = 51 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_4 = 52 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_5 = 53 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_6 = 54 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_7 = 55 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_8 = 56 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_9 = 57 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_10 = 58 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_11 = 59 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_12 = 60 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_13 = 61 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_14 = 62 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD0_IDIAL_SM_HOLD_OCR_15 = 63 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_1 = 1 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_2 = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_3 = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_4 = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_5 = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_6 = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_7 = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_8 = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_9 = 9 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_10 = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_11 = 11 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_12 = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_13 = 13 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_14 = 14 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_15 = 15 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_16 = 16 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_17 = 17 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_18 = 18 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_19 = 19 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_20 = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_21 = 21 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_22 = 22 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_23 = 23 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_0 = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_1 = 25 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_2 = 26 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_3 = 27 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_4 = 28 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_5 = 29 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_6 = 30 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_7 = 31 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_0 = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_1 = 33 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_2 = 34 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_3 = 35 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_0 = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_1 = 37 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_2 = 38 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_3 = 39 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_4 = 40 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_5 = 41 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_6 = 42 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_7 = 43 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_REG_0 = 44 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_REG_1 = 45 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_REG_2 = 46 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_REG_3 = 47 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_0 = 48 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_1 = 49 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_2 = 50 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_3 = 51 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_4 = 52 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_5 = 53 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_6 = 54 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_7 = 55 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_8 = 56 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_9 = 57 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_10 = 58 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_11 = 59 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_12 = 60 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_13 = 61 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_14 = 62 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD0_IDIAL_SM_HOLD_OCR_15 = 63 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_0 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_1 = 1 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_2 = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_3 = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_4 = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_5 = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_6 = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_7 = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_8 = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_9 = 9 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_10 = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_11 = 11 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_12 = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_13 = 13 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_14 = 14 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_15 = 15 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_0 = 16 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_1 = 17 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_2 = 18 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_3 = 19 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_0 = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_1 = 21 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_2 = 22 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_3 = 23 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_0 = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_1 = 25 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_2 = 26 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_3 = 27 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_4 = 28 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_5 = 29 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_6 = 30 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_7 = 31 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_0 = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_1 = 33 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_2 = 34 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_3 = 35 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_4 = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_5 = 37 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_6 = 38 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_7 = 39 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_8 = 40 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_9 = 41 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_10 = 42 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_11 = 43 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_0 = 44 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_1 = 45 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_2 = 46 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_3 = 47 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_4 = 48 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_5 = 49 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_6 = 50 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_7 = 51 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_8 = 52 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_9 = 53 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_10 = 54 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_11 = 55 ;
+
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_0 = 0 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_1 = 1 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_2 = 2 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_3 = 3 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_4 = 4 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_5 = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_6 = 6 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_7 = 7 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_8 = 8 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_9 = 9 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_10 = 10 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_11 = 11 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_12 = 12 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_13 = 13 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_14 = 14 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_15 = 15 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_16 = 16 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_17 = 17 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_18 = 18 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_19 = 19 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_20 = 20 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_21 = 21 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_22 = 22 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_23 = 23 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_24 = 24 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_25 = 25 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_26 = 26 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_27 = 27 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_28 = 28 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_29 = 29 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_30 = 30 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_31 = 31 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_32 = 32 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_33 = 33 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_34 = 34 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_35 = 35 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_36 = 36 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_37 = 37 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_38 = 38 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_39 = 39 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_40 = 40 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_41 = 41 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_42 = 42 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_43 = 43 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_44 = 44 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_45 = 45 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_46 = 46 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_47 = 47 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_48 = 48 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_49 = 49 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_50 = 50 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_51 = 51 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_52 = 52 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_53 = 53 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_54 = 54 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_55 = 55 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_56 = 56 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_57 = 57 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_58 = 58 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_59 = 59 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_60 = 60 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_61 = 61 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_62 = 62 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD1_NTL_63 = 63 ;
+
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_0 = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_1 = 1 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_2 = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_3 = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_4 = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_5 = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_6 = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_7 = 7 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_8 = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_9 = 9 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_10 = 10 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_11 = 11 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_12 = 12 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_13 = 13 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_14 = 14 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_15 = 15 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_0 = 16 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_1 = 17 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_2 = 18 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_3 = 19 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_0 = 20 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_1 = 21 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_2 = 22 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_3 = 23 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_0 = 24 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_1 = 25 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_2 = 26 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_3 = 27 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_4 = 28 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_5 = 29 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_6 = 30 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_7 = 31 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_0 = 32 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_1 = 33 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_2 = 34 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_3 = 35 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_4 = 36 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_5 = 37 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_6 = 38 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_7 = 39 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_8 = 40 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_9 = 41 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_10 = 42 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_11 = 43 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_0 = 44 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_1 = 45 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_2 = 46 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_3 = 47 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_4 = 48 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_5 = 49 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_6 = 50 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_7 = 51 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_8 = 52 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_9 = 53 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_10 = 54 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_11 = 55 ;
+
+static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_0 = 0 ;
+static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_1 = 1 ;
+static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_2 = 2 ;
+static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_3 = 3 ;
+static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_4 = 4 ;
+static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_5 = 5 ;
+static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_6 = 6 ;
+static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_7 = 7 ;
+static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_8 = 8 ;
+static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_9 = 9 ;
+static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_10 = 10 ;
+static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_11 = 11 ;
+static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_12 = 12 ;
+static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_13 = 13 ;
+static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_14 = 14 ;
+static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_15 = 15 ;
+static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_16 = 16 ;
+static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_17 = 17 ;
+static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_18 = 18 ;
+static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_19 = 19 ;
+static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_20 = 20 ;
+static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_21 = 21 ;
+static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_22 = 22 ;
+static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_23 = 23 ;
+static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_24 = 24 ;
+static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_25 = 25 ;
+static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_26 = 26 ;
+static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_27 = 27 ;
+static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_28 = 28 ;
+static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_29 = 29 ;
+static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_30 = 30 ;
+static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_31 = 31 ;
+static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_32 = 32 ;
+static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_33 = 33 ;
+static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_34 = 34 ;
+static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_35 = 35 ;
+static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_36 = 36 ;
+static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_37 = 37 ;
+static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_38 = 38 ;
+static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_39 = 39 ;
+static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_40 = 40 ;
+static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_41 = 41 ;
+static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_42 = 42 ;
+static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_43 = 43 ;
+static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_44 = 44 ;
+static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_45 = 45 ;
+static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_46 = 46 ;
+static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_47 = 47 ;
+static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_48 = 48 ;
+static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_49 = 49 ;
+static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_50 = 50 ;
+static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_51 = 51 ;
+static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_52 = 52 ;
+static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_53 = 53 ;
+static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_54 = 54 ;
+static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_55 = 55 ;
+static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_56 = 56 ;
+static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_57 = 57 ;
+static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_58 = 58 ;
+static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_59 = 59 ;
+static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_60 = 60 ;
+static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_61 = 61 ;
+static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_62 = 62 ;
+static const uint8_t P9N2__SM1_CERR_HOLD1_NTL_63 = 63 ;
+
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_0 = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_1 = 1 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_2 = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_3 = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_4 = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_5 = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_6 = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_7 = 7 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_8 = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_9 = 9 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_10 = 10 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_11 = 11 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_12 = 12 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_13 = 13 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_14 = 14 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_15 = 15 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_0 = 16 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_1 = 17 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_2 = 18 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_3 = 19 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_0 = 20 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_1 = 21 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_2 = 22 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_3 = 23 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_0 = 24 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_1 = 25 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_2 = 26 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_3 = 27 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_4 = 28 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_5 = 29 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_6 = 30 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_7 = 31 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_0 = 32 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_1 = 33 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_2 = 34 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_3 = 35 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_4 = 36 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_5 = 37 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_6 = 38 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_7 = 39 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_8 = 40 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_9 = 41 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_10 = 42 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_11 = 43 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_0 = 44 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_1 = 45 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_2 = 46 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_3 = 47 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_4 = 48 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_5 = 49 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_6 = 50 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_7 = 51 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_8 = 52 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_9 = 53 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_10 = 54 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_11 = 55 ;
+
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_0 = 0 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_1 = 1 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_2 = 2 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_3 = 3 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_4 = 4 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_5 = 5 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_6 = 6 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_7 = 7 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_8 = 8 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_9 = 9 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_10 = 10 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_11 = 11 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_12 = 12 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_13 = 13 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_14 = 14 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_15 = 15 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_0 = 16 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_1 = 17 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_2 = 18 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_3 = 19 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_4 = 20 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_5 = 21 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_6 = 22 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_7 = 23 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_0 = 24 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_1 = 25 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_2 = 26 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_3 = 27 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_4 = 28 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_5 = 29 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_6 = 30 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_7 = 31 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_0 = 32 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_1 = 33 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_2 = 34 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_3 = 35 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_4 = 36 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_5 = 37 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_6 = 38 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_7 = 39 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_0 = 40 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_1 = 41 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_2 = 42 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_3 = 43 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_4 = 44 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_5 = 45 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_6 = 46 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_7 = 47 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_0 = 48 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_1 = 49 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_2 = 50 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_3 = 51 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_4 = 52 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_5 = 53 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_6 = 54 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_7 = 55 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_RSV2_0 = 56 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_RSV2_1 = 57 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_RSV2_2 = 58 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_RSV2_3 = 59 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_RSV3_0 = 60 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_RSV3_1 = 61 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_RSV3_2 = 62 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_HOLD1_IDIAL_CTL_HOLD_RSV3_3 = 63 ;
+
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_0 = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_1 = 1 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_2 = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_3 = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_4 = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_5 = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_6 = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_7 = 7 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_8 = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_9 = 9 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_10 = 10 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_11 = 11 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_12 = 12 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_13 = 13 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_14 = 14 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_15 = 15 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_FWD_0 = 16 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_FWD_1 = 17 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_FWD_2 = 18 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_FWD_3 = 19 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_AUE_0 = 20 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_AUE_1 = 21 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_AUE_2 = 22 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_AUE_3 = 23 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_0 = 24 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_1 = 25 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_2 = 26 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_3 = 27 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_4 = 28 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_5 = 29 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_6 = 30 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_7 = 31 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_0 = 32 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_1 = 33 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_2 = 34 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_3 = 35 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_4 = 36 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_5 = 37 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_6 = 38 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_7 = 39 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_8 = 40 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_9 = 41 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_10 = 42 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_11 = 43 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_0 = 44 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_1 = 45 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_2 = 46 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_3 = 47 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_4 = 48 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_5 = 49 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_6 = 50 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_7 = 51 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_8 = 52 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_9 = 53 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_10 = 54 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_11 = 55 ;
+
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_0 = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_1 = 1 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_2 = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_3 = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_4 = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_5 = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_6 = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_7 = 7 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_8 = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_9 = 9 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_10 = 10 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_11 = 11 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_12 = 12 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_13 = 13 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_14 = 14 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_15 = 15 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_FWD_0 = 16 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_FWD_1 = 17 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_FWD_2 = 18 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_FWD_3 = 19 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_AUE_0 = 20 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_AUE_1 = 21 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_AUE_2 = 22 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_AUE_3 = 23 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_0 = 24 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_1 = 25 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_2 = 26 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_3 = 27 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_4 = 28 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_5 = 29 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_6 = 30 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_7 = 31 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_0 = 32 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_1 = 33 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_2 = 34 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_3 = 35 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_4 = 36 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_5 = 37 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_6 = 38 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_7 = 39 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_8 = 40 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_9 = 41 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_10 = 42 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_11 = 43 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_0 = 44 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_1 = 45 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_2 = 46 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_3 = 47 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_4 = 48 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_5 = 49 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_6 = 50 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_7 = 51 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_8 = 52 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_9 = 53 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_10 = 54 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_11 = 55 ;
+
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_0 = 0 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_1 = 1 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_2 = 2 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_3 = 3 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_4 = 4 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_5 = 5 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_6 = 6 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_7 = 7 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_8 = 8 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_9 = 9 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_10 = 10 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_11 = 11 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_12 = 12 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_13 = 13 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_14 = 14 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_15 = 15 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_0 = 16 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_1 = 17 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_2 = 18 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_3 = 19 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_0 = 20 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_1 = 21 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_2 = 22 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_3 = 23 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_0 = 24 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_1 = 25 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_2 = 26 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_3 = 27 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_4 = 28 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_5 = 29 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_6 = 30 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_7 = 31 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_0 = 32 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_1 = 33 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_2 = 34 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_3 = 35 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_4 = 36 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_5 = 37 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_6 = 38 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_7 = 39 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_8 = 40 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_9 = 41 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_10 = 42 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_11 = 43 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_0 = 44 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_1 = 45 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_2 = 46 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_3 = 47 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_4 = 48 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_5 = 49 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_6 = 50 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_7 = 51 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_8 = 52 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_9 = 53 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_10 = 54 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_11 = 55 ;
+
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_0 = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_1 = 1 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_2 = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_3 = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_4 = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_5 = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_6 = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_7 = 7 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_8 = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_9 = 9 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_10 = 10 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_11 = 11 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_12 = 12 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_13 = 13 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_14 = 14 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_15 = 15 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_0 = 16 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_1 = 17 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_2 = 18 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_3 = 19 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_0 = 20 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_1 = 21 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_2 = 22 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_3 = 23 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_0 = 24 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_1 = 25 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_2 = 26 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_3 = 27 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_4 = 28 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_5 = 29 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_6 = 30 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_7 = 31 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_0 = 32 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_1 = 33 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_2 = 34 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_3 = 35 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_4 = 36 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_5 = 37 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_6 = 38 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_7 = 39 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_8 = 40 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_9 = 41 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_10 = 42 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_11 = 43 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_0 = 44 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_1 = 45 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_2 = 46 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_3 = 47 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_4 = 48 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_5 = 49 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_6 = 50 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_7 = 51 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_8 = 52 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_9 = 53 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_10 = 54 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_11 = 55 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_0 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_1 = 1 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_2 = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_3 = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_4 = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_5 = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_6 = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_7 = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_8 = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_9 = 9 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_10 = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_11 = 11 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_12 = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_13 = 13 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_14 = 14 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_15 = 15 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_0 = 16 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_1 = 17 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_2 = 18 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_3 = 19 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_0 = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_1 = 21 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_2 = 22 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_3 = 23 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_0 = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_1 = 25 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_2 = 26 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_3 = 27 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_4 = 28 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_5 = 29 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_6 = 30 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_7 = 31 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_0 = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_1 = 33 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_2 = 34 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_3 = 35 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_4 = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_5 = 37 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_6 = 38 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_7 = 39 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_8 = 40 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_9 = 41 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_10 = 42 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_11 = 43 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_0 = 44 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_1 = 45 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_2 = 46 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_3 = 47 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_4 = 48 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_5 = 49 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_6 = 50 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_7 = 51 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_8 = 52 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_9 = 53 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_10 = 54 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_11 = 55 ;
+
+static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_0 = 0 ;
+static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_1 = 1 ;
+static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_2 = 2 ;
+static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_3 = 3 ;
+static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_4 = 4 ;
+static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_5 = 5 ;
+static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_6 = 6 ;
+static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_7 = 7 ;
+static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_8 = 8 ;
+static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_9 = 9 ;
+static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_10 = 10 ;
+static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_11 = 11 ;
+static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_12 = 12 ;
+static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_13 = 13 ;
+static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_14 = 14 ;
+static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_15 = 15 ;
+static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_16 = 16 ;
+static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_17 = 17 ;
+static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_18 = 18 ;
+static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_19 = 19 ;
+static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_20 = 20 ;
+static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_21 = 21 ;
+static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_22 = 22 ;
+static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_23 = 23 ;
+static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_24 = 24 ;
+static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_25 = 25 ;
+static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_26 = 26 ;
+static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_27 = 27 ;
+static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_28 = 28 ;
+static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_29 = 29 ;
+static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_30 = 30 ;
+static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_31 = 31 ;
+static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_32 = 32 ;
+static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_33 = 33 ;
+static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_34 = 34 ;
+static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_35 = 35 ;
+static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_36 = 36 ;
+static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_37 = 37 ;
+static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_38 = 38 ;
+static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_39 = 39 ;
+static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_40 = 40 ;
+static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_41 = 41 ;
+static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_42 = 42 ;
+static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_43 = 43 ;
+static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_44 = 44 ;
+static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_45 = 45 ;
+static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_46 = 46 ;
+static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_47 = 47 ;
+static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_48 = 48 ;
+static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_49 = 49 ;
+static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_50 = 50 ;
+static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_51 = 51 ;
+static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_52 = 52 ;
+static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_53 = 53 ;
+static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_54 = 54 ;
+static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_55 = 55 ;
+static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_56 = 56 ;
+static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_57 = 57 ;
+static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_58 = 58 ;
+static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_59 = 59 ;
+static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_60 = 60 ;
+static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_61 = 61 ;
+static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_62 = 62 ;
+static const uint8_t P9N2__SM0_CERR_HOLD1_NTL_63 = 63 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_0 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_1 = 1 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_2 = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_3 = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_4 = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_5 = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_6 = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_7 = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_8 = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_9 = 9 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_10 = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_11 = 11 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_12 = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_13 = 13 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_14 = 14 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_15 = 15 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_FWD_0 = 16 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_FWD_1 = 17 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_FWD_2 = 18 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_FWD_3 = 19 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_AUE_0 = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_AUE_1 = 21 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_AUE_2 = 22 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_AUE_3 = 23 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_PBP_0 = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_PBP_1 = 25 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_PBP_2 = 26 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_PBP_3 = 27 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_PBP_4 = 28 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_PBP_5 = 29 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_PBP_6 = 30 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_PBP_7 = 31 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_PBF_0 = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_PBF_1 = 33 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_PBF_2 = 34 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_PBF_3 = 35 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_PBF_4 = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_PBF_5 = 37 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_PBF_6 = 38 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_PBF_7 = 39 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_PBF_8 = 40 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_PBF_9 = 41 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_PBF_10 = 42 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_PBF_11 = 43 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_PBC_0 = 44 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_PBC_1 = 45 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_PBC_2 = 46 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_PBC_3 = 47 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_PBC_4 = 48 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_PBC_5 = 49 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_PBC_6 = 50 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_PBC_7 = 51 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_PBC_8 = 52 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_PBC_9 = 53 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_PBC_10 = 54 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD1_IDIAL_SM_HOLD_PBC_11 = 55 ;
+
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_0 = 0 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_1 = 1 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_2 = 2 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_3 = 3 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_4 = 4 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_5 = 5 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_6 = 6 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_7 = 7 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_8 = 8 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_9 = 9 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_10 = 10 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_11 = 11 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_12 = 12 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_13 = 13 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_14 = 14 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_15 = 15 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_16 = 16 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_17 = 17 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_18 = 18 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_19 = 19 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_20 = 20 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_21 = 21 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_22 = 22 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_23 = 23 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_24 = 24 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_25 = 25 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_26 = 26 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_27 = 27 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_28 = 28 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_29 = 29 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_30 = 30 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_31 = 31 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_32 = 32 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_33 = 33 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_34 = 34 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_35 = 35 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_36 = 36 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_37 = 37 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_38 = 38 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_39 = 39 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_40 = 40 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_41 = 41 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_42 = 42 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_43 = 43 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_44 = 44 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_45 = 45 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_46 = 46 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_47 = 47 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_48 = 48 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_49 = 49 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_50 = 50 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_51 = 51 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_52 = 52 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_53 = 53 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_54 = 54 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_55 = 55 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_56 = 56 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_57 = 57 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_58 = 58 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_59 = 59 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_60 = 60 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_61 = 61 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_62 = 62 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD1_NTL_63 = 63 ;
+
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_0 = 0 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_1 = 1 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_2 = 2 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_3 = 3 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_4 = 4 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_5 = 5 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_6 = 6 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_7 = 7 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_8 = 8 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_9 = 9 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_10 = 10 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_11 = 11 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_12 = 12 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_13 = 13 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_14 = 14 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_15 = 15 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_16 = 16 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_17 = 17 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_18 = 18 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_19 = 19 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_20 = 20 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_21 = 21 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_22 = 22 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_23 = 23 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_24 = 24 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_25 = 25 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_26 = 26 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_27 = 27 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_28 = 28 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_29 = 29 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_30 = 30 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_31 = 31 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_32 = 32 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_33 = 33 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_34 = 34 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_35 = 35 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_36 = 36 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_37 = 37 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_38 = 38 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_39 = 39 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_40 = 40 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_41 = 41 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_42 = 42 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_43 = 43 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_44 = 44 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_45 = 45 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_46 = 46 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_47 = 47 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_48 = 48 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_49 = 49 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_50 = 50 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_51 = 51 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_52 = 52 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_53 = 53 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_54 = 54 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_55 = 55 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_56 = 56 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_57 = 57 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_58 = 58 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_59 = 59 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_60 = 60 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_61 = 61 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_62 = 62 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD1_NTL_63 = 63 ;
+
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_0 = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_1 = 1 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_2 = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_3 = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_4 = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_5 = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_6 = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_7 = 7 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_8 = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_9 = 9 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_10 = 10 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_11 = 11 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_12 = 12 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_13 = 13 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_14 = 14 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_15 = 15 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_0 = 16 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_1 = 17 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_2 = 18 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_3 = 19 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_0 = 20 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_1 = 21 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_2 = 22 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_3 = 23 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_0 = 24 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_1 = 25 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_2 = 26 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_3 = 27 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_4 = 28 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_5 = 29 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_6 = 30 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_7 = 31 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_0 = 32 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_1 = 33 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_2 = 34 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_3 = 35 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_4 = 36 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_5 = 37 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_6 = 38 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_7 = 39 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_8 = 40 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_9 = 41 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_10 = 42 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_11 = 43 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_0 = 44 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_1 = 45 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_2 = 46 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_3 = 47 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_4 = 48 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_5 = 49 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_6 = 50 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_7 = 51 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_8 = 52 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_9 = 53 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_10 = 54 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_11 = 55 ;
+
+static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_0 = 0 ;
+static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_1 = 1 ;
+static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_2 = 2 ;
+static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_3 = 3 ;
+static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_4 = 4 ;
+static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_5 = 5 ;
+static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_6 = 6 ;
+static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_7 = 7 ;
+static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_8 = 8 ;
+static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_9 = 9 ;
+static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_10 = 10 ;
+static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_11 = 11 ;
+static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_12 = 12 ;
+static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_13 = 13 ;
+static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_14 = 14 ;
+static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_15 = 15 ;
+static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_0 = 16 ;
+static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_1 = 17 ;
+static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_2 = 18 ;
+static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_3 = 19 ;
+static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_4 = 20 ;
+static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_5 = 21 ;
+static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_6 = 22 ;
+static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_7 = 23 ;
+static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_0 = 24 ;
+static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_1 = 25 ;
+static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_2 = 26 ;
+static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_3 = 27 ;
+static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_4 = 28 ;
+static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_5 = 29 ;
+static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_6 = 30 ;
+static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_7 = 31 ;
+static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_0 = 32 ;
+static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_1 = 33 ;
+static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_2 = 34 ;
+static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_3 = 35 ;
+static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_4 = 36 ;
+static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_5 = 37 ;
+static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_6 = 38 ;
+static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_7 = 39 ;
+static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_0 = 40 ;
+static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_1 = 41 ;
+static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_2 = 42 ;
+static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_3 = 43 ;
+static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_4 = 44 ;
+static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_5 = 45 ;
+static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_6 = 46 ;
+static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_7 = 47 ;
+static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_0 = 48 ;
+static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_1 = 49 ;
+static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_2 = 50 ;
+static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_3 = 51 ;
+static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_4 = 52 ;
+static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_5 = 53 ;
+static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_6 = 54 ;
+static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_7 = 55 ;
+static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_RSV2_0 = 56 ;
+static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_RSV2_1 = 57 ;
+static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_RSV2_2 = 58 ;
+static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_RSV2_3 = 59 ;
+static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_RSV3_0 = 60 ;
+static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_RSV3_1 = 61 ;
+static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_RSV3_2 = 62 ;
+static const uint8_t P9N2_NV_CERR_HOLD1_IDIAL_CTL_HOLD_RSV3_3 = 63 ;
+
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_0 = 0 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_1 = 1 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_2 = 2 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_3 = 3 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_4 = 4 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_5 = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_6 = 6 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_7 = 7 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_8 = 8 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_9 = 9 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_10 = 10 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_11 = 11 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_12 = 12 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_13 = 13 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_14 = 14 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_15 = 15 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_16 = 16 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_17 = 17 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_18 = 18 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_19 = 19 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_20 = 20 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_21 = 21 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_22 = 22 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_23 = 23 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_24 = 24 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_25 = 25 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_26 = 26 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_27 = 27 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_28 = 28 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_29 = 29 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_30 = 30 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_31 = 31 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_32 = 32 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_33 = 33 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_34 = 34 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_35 = 35 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_36 = 36 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_37 = 37 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_38 = 38 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_39 = 39 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_40 = 40 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_41 = 41 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_42 = 42 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_43 = 43 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_44 = 44 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_45 = 45 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_46 = 46 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_47 = 47 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_48 = 48 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_49 = 49 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_50 = 50 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_51 = 51 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_52 = 52 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_53 = 53 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_54 = 54 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_55 = 55 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_56 = 56 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_57 = 57 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_58 = 58 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_59 = 59 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_60 = 60 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_61 = 61 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_62 = 62 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD1_NTL_63 = 63 ;
+
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_0 = 0 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_1 = 1 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_2 = 2 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_3 = 3 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_4 = 4 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_5 = 5 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_6 = 6 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_7 = 7 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_8 = 8 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_9 = 9 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_10 = 10 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_11 = 11 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_12 = 12 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_13 = 13 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_14 = 14 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_15 = 15 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_0 = 16 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_1 = 17 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_2 = 18 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_3 = 19 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_0 = 20 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_1 = 21 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_2 = 22 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_3 = 23 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_0 = 24 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_1 = 25 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_2 = 26 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_3 = 27 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_4 = 28 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_5 = 29 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_6 = 30 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_7 = 31 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_0 = 32 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_1 = 33 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_2 = 34 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_3 = 35 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_4 = 36 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_5 = 37 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_6 = 38 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_7 = 39 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_8 = 40 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_9 = 41 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_10 = 42 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_11 = 43 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_0 = 44 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_1 = 45 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_2 = 46 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_3 = 47 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_4 = 48 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_5 = 49 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_6 = 50 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_7 = 51 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_8 = 52 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_9 = 53 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_10 = 54 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_11 = 55 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_0 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_1 = 1 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_2 = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_3 = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_4 = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_5 = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_6 = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_7 = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_8 = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_9 = 9 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_10 = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_11 = 11 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_12 = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_13 = 13 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_14 = 14 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_15 = 15 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_FWD_0 = 16 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_FWD_1 = 17 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_FWD_2 = 18 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_FWD_3 = 19 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_AUE_0 = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_AUE_1 = 21 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_AUE_2 = 22 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_AUE_3 = 23 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_0 = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_1 = 25 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_2 = 26 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_3 = 27 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_4 = 28 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_5 = 29 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_6 = 30 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_7 = 31 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_0 = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_1 = 33 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_2 = 34 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_3 = 35 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_4 = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_5 = 37 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_6 = 38 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_7 = 39 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_8 = 40 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_9 = 41 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_10 = 42 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_11 = 43 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_0 = 44 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_1 = 45 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_2 = 46 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_3 = 47 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_4 = 48 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_5 = 49 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_6 = 50 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_7 = 51 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_8 = 52 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_9 = 53 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_10 = 54 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_11 = 55 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_0 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_1 = 1 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_2 = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_3 = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_4 = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_5 = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_6 = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_7 = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_8 = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_9 = 9 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_10 = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_11 = 11 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_12 = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_13 = 13 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_14 = 14 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_15 = 15 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_16 = 16 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_17 = 17 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_18 = 18 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_19 = 19 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_20 = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_21 = 21 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_22 = 22 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_23 = 23 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_24 = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_25 = 25 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_26 = 26 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_27 = 27 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_28 = 28 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_29 = 29 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_30 = 30 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_31 = 31 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_32 = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_33 = 33 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_34 = 34 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_35 = 35 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_36 = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_37 = 37 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_38 = 38 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_39 = 39 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_40 = 40 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_41 = 41 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_42 = 42 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_43 = 43 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_44 = 44 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_45 = 45 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_46 = 46 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_47 = 47 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_48 = 48 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_49 = 49 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_50 = 50 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_51 = 51 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_52 = 52 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_53 = 53 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_54 = 54 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_55 = 55 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_56 = 56 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_57 = 57 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_58 = 58 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_59 = 59 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_60 = 60 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_61 = 61 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_62 = 62 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_63 = 63 ;
+
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_0 = 0 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_1 = 1 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_2 = 2 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_3 = 3 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_4 = 4 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_5 = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_6 = 6 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_7 = 7 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_8 = 8 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_9 = 9 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_10 = 10 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_11 = 11 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_12 = 12 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_13 = 13 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_14 = 14 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_15 = 15 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_16 = 16 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_17 = 17 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_18 = 18 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_19 = 19 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_20 = 20 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_21 = 21 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_22 = 22 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_23 = 23 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_24 = 24 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_25 = 25 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_26 = 26 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_27 = 27 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_28 = 28 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_29 = 29 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_30 = 30 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_31 = 31 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_32 = 32 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_33 = 33 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_34 = 34 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_35 = 35 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_36 = 36 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_37 = 37 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_38 = 38 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_39 = 39 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_40 = 40 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_41 = 41 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_42 = 42 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_43 = 43 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_44 = 44 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_45 = 45 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_46 = 46 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_47 = 47 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_48 = 48 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_49 = 49 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_50 = 50 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_51 = 51 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_52 = 52 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_53 = 53 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_54 = 54 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_55 = 55 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_56 = 56 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_57 = 57 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_58 = 58 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_59 = 59 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_60 = 60 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_61 = 61 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_62 = 62 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_HOLD2_NTL_63 = 63 ;
+
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_0 = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_1 = 1 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_2 = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_3 = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_4 = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_5 = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_6 = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_7 = 7 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_8 = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_9 = 9 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_10 = 10 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_11 = 11 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_12 = 12 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_13 = 13 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_14 = 14 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_15 = 15 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_16 = 16 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_17 = 17 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_18 = 18 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_19 = 19 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_20 = 20 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_21 = 21 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_22 = 22 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_23 = 23 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_24 = 24 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_25 = 25 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_26 = 26 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_27 = 27 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_28 = 28 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_29 = 29 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_30 = 30 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_31 = 31 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_32 = 32 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_33 = 33 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_34 = 34 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_35 = 35 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_36 = 36 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_37 = 37 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_38 = 38 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_39 = 39 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_40 = 40 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_41 = 41 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_42 = 42 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_43 = 43 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_44 = 44 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_45 = 45 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_46 = 46 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_47 = 47 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_48 = 48 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_49 = 49 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_50 = 50 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_51 = 51 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_52 = 52 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_53 = 53 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_54 = 54 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_55 = 55 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_56 = 56 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_57 = 57 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_58 = 58 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_59 = 59 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_60 = 60 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_61 = 61 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_62 = 62 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_63 = 63 ;
+
+static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_0 = 0 ;
+static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_1 = 1 ;
+static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_2 = 2 ;
+static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_3 = 3 ;
+static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_4 = 4 ;
+static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_5 = 5 ;
+static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_6 = 6 ;
+static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_7 = 7 ;
+static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_8 = 8 ;
+static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_9 = 9 ;
+static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_10 = 10 ;
+static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_11 = 11 ;
+static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_12 = 12 ;
+static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_13 = 13 ;
+static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_14 = 14 ;
+static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_15 = 15 ;
+static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_16 = 16 ;
+static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_17 = 17 ;
+static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_18 = 18 ;
+static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_19 = 19 ;
+static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_20 = 20 ;
+static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_21 = 21 ;
+static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_22 = 22 ;
+static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_23 = 23 ;
+static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_24 = 24 ;
+static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_25 = 25 ;
+static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_26 = 26 ;
+static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_27 = 27 ;
+static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_28 = 28 ;
+static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_29 = 29 ;
+static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_30 = 30 ;
+static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_31 = 31 ;
+static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_32 = 32 ;
+static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_33 = 33 ;
+static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_34 = 34 ;
+static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_35 = 35 ;
+static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_36 = 36 ;
+static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_37 = 37 ;
+static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_38 = 38 ;
+static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_39 = 39 ;
+static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_40 = 40 ;
+static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_41 = 41 ;
+static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_42 = 42 ;
+static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_43 = 43 ;
+static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_44 = 44 ;
+static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_45 = 45 ;
+static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_46 = 46 ;
+static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_47 = 47 ;
+static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_48 = 48 ;
+static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_49 = 49 ;
+static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_50 = 50 ;
+static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_51 = 51 ;
+static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_52 = 52 ;
+static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_53 = 53 ;
+static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_54 = 54 ;
+static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_55 = 55 ;
+static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_56 = 56 ;
+static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_57 = 57 ;
+static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_58 = 58 ;
+static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_59 = 59 ;
+static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_60 = 60 ;
+static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_61 = 61 ;
+static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_62 = 62 ;
+static const uint8_t P9N2__SM1_CERR_HOLD2_NTL_63 = 63 ;
+
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_0 = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_1 = 1 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_2 = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_3 = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_4 = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_5 = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_6 = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_7 = 7 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_8 = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_9 = 9 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_10 = 10 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_11 = 11 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_12 = 12 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_13 = 13 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_14 = 14 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_15 = 15 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_16 = 16 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_17 = 17 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_18 = 18 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_19 = 19 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_20 = 20 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_21 = 21 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_22 = 22 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_23 = 23 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_24 = 24 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_25 = 25 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_26 = 26 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_27 = 27 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_28 = 28 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_29 = 29 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_30 = 30 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_31 = 31 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_32 = 32 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_33 = 33 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_34 = 34 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_35 = 35 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_36 = 36 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_37 = 37 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_38 = 38 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_39 = 39 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_40 = 40 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_41 = 41 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_42 = 42 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_43 = 43 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_44 = 44 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_45 = 45 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_46 = 46 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_47 = 47 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_48 = 48 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_49 = 49 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_50 = 50 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_51 = 51 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_52 = 52 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_53 = 53 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_54 = 54 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_55 = 55 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_56 = 56 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_57 = 57 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_58 = 58 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_59 = 59 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_60 = 60 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_61 = 61 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_62 = 62 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_63 = 63 ;
+
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_0 = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_1 = 1 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_2 = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_3 = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_4 = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_5 = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_6 = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_7 = 7 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_8 = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_9 = 9 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_10 = 10 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_11 = 11 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_12 = 12 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_13 = 13 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_14 = 14 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_15 = 15 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_16 = 16 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_17 = 17 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_18 = 18 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_19 = 19 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_20 = 20 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_21 = 21 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_22 = 22 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_23 = 23 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_24 = 24 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_25 = 25 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_26 = 26 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_27 = 27 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_28 = 28 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_29 = 29 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_30 = 30 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_31 = 31 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_32 = 32 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_33 = 33 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_34 = 34 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_35 = 35 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_36 = 36 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_37 = 37 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_38 = 38 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_39 = 39 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_40 = 40 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_41 = 41 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_42 = 42 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_43 = 43 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_44 = 44 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_45 = 45 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_46 = 46 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_47 = 47 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_48 = 48 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_49 = 49 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_50 = 50 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_51 = 51 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_52 = 52 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_53 = 53 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_54 = 54 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_55 = 55 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_56 = 56 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_57 = 57 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_58 = 58 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_59 = 59 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_60 = 60 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_61 = 61 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_62 = 62 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_63 = 63 ;
+
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_0 = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_1 = 1 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_2 = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_3 = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_4 = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_5 = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_6 = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_7 = 7 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_8 = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_9 = 9 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_10 = 10 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_11 = 11 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_12 = 12 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_13 = 13 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_14 = 14 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_15 = 15 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_16 = 16 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_17 = 17 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_18 = 18 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_19 = 19 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_20 = 20 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_21 = 21 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_22 = 22 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_23 = 23 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_24 = 24 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_25 = 25 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_26 = 26 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_27 = 27 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_28 = 28 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_29 = 29 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_30 = 30 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_31 = 31 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_32 = 32 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_33 = 33 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_34 = 34 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_35 = 35 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_36 = 36 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_37 = 37 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_38 = 38 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_39 = 39 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_40 = 40 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_41 = 41 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_42 = 42 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_43 = 43 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_44 = 44 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_45 = 45 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_46 = 46 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_47 = 47 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_48 = 48 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_49 = 49 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_50 = 50 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_51 = 51 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_52 = 52 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_53 = 53 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_54 = 54 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_55 = 55 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_56 = 56 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_57 = 57 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_58 = 58 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_59 = 59 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_60 = 60 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_61 = 61 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_62 = 62 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_63 = 63 ;
+
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_0 = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_1 = 1 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_2 = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_3 = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_4 = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_5 = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_6 = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_7 = 7 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_8 = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_9 = 9 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_10 = 10 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_11 = 11 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_12 = 12 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_13 = 13 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_14 = 14 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_15 = 15 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_16 = 16 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_17 = 17 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_18 = 18 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_19 = 19 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_20 = 20 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_21 = 21 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_22 = 22 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_23 = 23 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_24 = 24 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_25 = 25 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_26 = 26 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_27 = 27 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_28 = 28 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_29 = 29 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_30 = 30 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_31 = 31 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_32 = 32 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_33 = 33 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_34 = 34 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_35 = 35 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_36 = 36 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_37 = 37 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_38 = 38 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_39 = 39 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_40 = 40 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_41 = 41 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_42 = 42 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_43 = 43 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_44 = 44 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_45 = 45 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_46 = 46 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_47 = 47 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_48 = 48 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_49 = 49 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_50 = 50 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_51 = 51 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_52 = 52 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_53 = 53 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_54 = 54 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_55 = 55 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_56 = 56 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_57 = 57 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_58 = 58 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_59 = 59 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_60 = 60 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_61 = 61 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_62 = 62 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_63 = 63 ;
+
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_0 = 0 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_1 = 1 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_2 = 2 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_3 = 3 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_4 = 4 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_5 = 5 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_6 = 6 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_7 = 7 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_8 = 8 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_9 = 9 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_10 = 10 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_11 = 11 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_12 = 12 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_13 = 13 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_14 = 14 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_15 = 15 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_16 = 16 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_17 = 17 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_18 = 18 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_19 = 19 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_20 = 20 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_21 = 21 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_22 = 22 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_23 = 23 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_24 = 24 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_25 = 25 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_26 = 26 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_27 = 27 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_28 = 28 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_29 = 29 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_30 = 30 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_31 = 31 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_32 = 32 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_33 = 33 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_34 = 34 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_35 = 35 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_36 = 36 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_37 = 37 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_38 = 38 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_39 = 39 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_40 = 40 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_41 = 41 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_42 = 42 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_43 = 43 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_44 = 44 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_45 = 45 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_46 = 46 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_47 = 47 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_48 = 48 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_49 = 49 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_50 = 50 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_51 = 51 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_52 = 52 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_53 = 53 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_54 = 54 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_55 = 55 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_56 = 56 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_57 = 57 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_58 = 58 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_59 = 59 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_60 = 60 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_61 = 61 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_62 = 62 ;
+static const uint8_t P9N2_PU_NPU0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_63 = 63 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_0 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_1 = 1 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_2 = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_3 = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_4 = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_5 = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_6 = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_7 = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_8 = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_9 = 9 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_10 = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_11 = 11 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_12 = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_13 = 13 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_14 = 14 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_15 = 15 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_16 = 16 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_17 = 17 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_18 = 18 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_19 = 19 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_20 = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_21 = 21 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_22 = 22 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_23 = 23 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_24 = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_25 = 25 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_26 = 26 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_27 = 27 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_28 = 28 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_29 = 29 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_30 = 30 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_31 = 31 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_32 = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_33 = 33 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_34 = 34 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_35 = 35 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_36 = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_37 = 37 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_38 = 38 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_39 = 39 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_40 = 40 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_41 = 41 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_42 = 42 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_43 = 43 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_44 = 44 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_45 = 45 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_46 = 46 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_47 = 47 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_48 = 48 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_49 = 49 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_50 = 50 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_51 = 51 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_52 = 52 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_53 = 53 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_54 = 54 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_55 = 55 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_56 = 56 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_57 = 57 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_58 = 58 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_59 = 59 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_60 = 60 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_61 = 61 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_62 = 62 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_63 = 63 ;
+
+static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_0 = 0 ;
+static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_1 = 1 ;
+static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_2 = 2 ;
+static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_3 = 3 ;
+static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_4 = 4 ;
+static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_5 = 5 ;
+static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_6 = 6 ;
+static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_7 = 7 ;
+static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_8 = 8 ;
+static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_9 = 9 ;
+static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_10 = 10 ;
+static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_11 = 11 ;
+static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_12 = 12 ;
+static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_13 = 13 ;
+static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_14 = 14 ;
+static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_15 = 15 ;
+static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_16 = 16 ;
+static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_17 = 17 ;
+static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_18 = 18 ;
+static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_19 = 19 ;
+static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_20 = 20 ;
+static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_21 = 21 ;
+static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_22 = 22 ;
+static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_23 = 23 ;
+static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_24 = 24 ;
+static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_25 = 25 ;
+static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_26 = 26 ;
+static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_27 = 27 ;
+static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_28 = 28 ;
+static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_29 = 29 ;
+static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_30 = 30 ;
+static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_31 = 31 ;
+static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_32 = 32 ;
+static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_33 = 33 ;
+static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_34 = 34 ;
+static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_35 = 35 ;
+static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_36 = 36 ;
+static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_37 = 37 ;
+static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_38 = 38 ;
+static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_39 = 39 ;
+static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_40 = 40 ;
+static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_41 = 41 ;
+static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_42 = 42 ;
+static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_43 = 43 ;
+static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_44 = 44 ;
+static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_45 = 45 ;
+static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_46 = 46 ;
+static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_47 = 47 ;
+static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_48 = 48 ;
+static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_49 = 49 ;
+static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_50 = 50 ;
+static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_51 = 51 ;
+static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_52 = 52 ;
+static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_53 = 53 ;
+static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_54 = 54 ;
+static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_55 = 55 ;
+static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_56 = 56 ;
+static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_57 = 57 ;
+static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_58 = 58 ;
+static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_59 = 59 ;
+static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_60 = 60 ;
+static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_61 = 61 ;
+static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_62 = 62 ;
+static const uint8_t P9N2__SM0_CERR_HOLD2_NTL_63 = 63 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_0 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_1 = 1 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_2 = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_3 = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_4 = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_5 = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_6 = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_7 = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_8 = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_9 = 9 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_10 = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_11 = 11 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_12 = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_13 = 13 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_14 = 14 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_15 = 15 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_16 = 16 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_17 = 17 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_18 = 18 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_19 = 19 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_20 = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_21 = 21 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_22 = 22 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_23 = 23 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_24 = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_25 = 25 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_26 = 26 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_27 = 27 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_28 = 28 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_29 = 29 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_30 = 30 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_31 = 31 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_32 = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_33 = 33 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_34 = 34 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_35 = 35 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_36 = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_37 = 37 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_38 = 38 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_39 = 39 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_40 = 40 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_41 = 41 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_42 = 42 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_43 = 43 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_44 = 44 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_45 = 45 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_46 = 46 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_47 = 47 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_48 = 48 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_49 = 49 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_50 = 50 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_51 = 51 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_52 = 52 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_53 = 53 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_54 = 54 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_55 = 55 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_56 = 56 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_57 = 57 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_58 = 58 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_59 = 59 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_60 = 60 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_61 = 61 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_62 = 62 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_HOLD2_IDIAL_SM_HOLD_NLG_63 = 63 ;
+
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_0 = 0 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_1 = 1 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_2 = 2 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_3 = 3 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_4 = 4 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_5 = 5 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_6 = 6 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_7 = 7 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_8 = 8 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_9 = 9 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_10 = 10 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_11 = 11 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_12 = 12 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_13 = 13 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_14 = 14 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_15 = 15 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_16 = 16 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_17 = 17 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_18 = 18 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_19 = 19 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_20 = 20 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_21 = 21 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_22 = 22 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_23 = 23 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_24 = 24 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_25 = 25 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_26 = 26 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_27 = 27 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_28 = 28 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_29 = 29 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_30 = 30 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_31 = 31 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_32 = 32 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_33 = 33 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_34 = 34 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_35 = 35 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_36 = 36 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_37 = 37 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_38 = 38 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_39 = 39 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_40 = 40 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_41 = 41 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_42 = 42 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_43 = 43 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_44 = 44 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_45 = 45 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_46 = 46 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_47 = 47 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_48 = 48 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_49 = 49 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_50 = 50 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_51 = 51 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_52 = 52 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_53 = 53 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_54 = 54 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_55 = 55 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_56 = 56 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_57 = 57 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_58 = 58 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_59 = 59 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_60 = 60 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_61 = 61 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_62 = 62 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_HOLD2_NTL_63 = 63 ;
+
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_0 = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_1 = 1 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_2 = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_3 = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_4 = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_5 = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_6 = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_7 = 7 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_8 = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_9 = 9 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_10 = 10 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_11 = 11 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_12 = 12 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_13 = 13 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_14 = 14 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_15 = 15 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_16 = 16 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_17 = 17 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_18 = 18 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_19 = 19 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_20 = 20 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_21 = 21 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_22 = 22 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_23 = 23 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_24 = 24 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_25 = 25 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_26 = 26 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_27 = 27 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_28 = 28 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_29 = 29 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_30 = 30 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_31 = 31 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_32 = 32 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_33 = 33 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_34 = 34 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_35 = 35 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_36 = 36 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_37 = 37 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_38 = 38 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_39 = 39 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_40 = 40 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_41 = 41 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_42 = 42 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_43 = 43 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_44 = 44 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_45 = 45 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_46 = 46 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_47 = 47 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_48 = 48 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_49 = 49 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_50 = 50 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_51 = 51 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_52 = 52 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_53 = 53 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_54 = 54 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_55 = 55 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_56 = 56 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_57 = 57 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_58 = 58 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_59 = 59 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_60 = 60 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_61 = 61 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_62 = 62 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_63 = 63 ;
+
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_0 = 0 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_1 = 1 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_2 = 2 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_3 = 3 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_4 = 4 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_5 = 5 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_6 = 6 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_7 = 7 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_8 = 8 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_9 = 9 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_10 = 10 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_11 = 11 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_12 = 12 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_13 = 13 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_14 = 14 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_15 = 15 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_16 = 16 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_17 = 17 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_18 = 18 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_19 = 19 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_20 = 20 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_21 = 21 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_22 = 22 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_23 = 23 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_24 = 24 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_25 = 25 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_26 = 26 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_27 = 27 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_28 = 28 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_29 = 29 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_30 = 30 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_31 = 31 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_32 = 32 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_33 = 33 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_34 = 34 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_35 = 35 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_36 = 36 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_37 = 37 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_38 = 38 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_39 = 39 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_40 = 40 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_41 = 41 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_42 = 42 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_43 = 43 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_44 = 44 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_45 = 45 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_46 = 46 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_47 = 47 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_48 = 48 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_49 = 49 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_50 = 50 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_51 = 51 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_52 = 52 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_53 = 53 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_54 = 54 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_55 = 55 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_56 = 56 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_57 = 57 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_58 = 58 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_59 = 59 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_60 = 60 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_61 = 61 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_62 = 62 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_HOLD2_NTL_63 = 63 ;
+
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_0 = 0 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_1 = 1 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_2 = 2 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_3 = 3 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_4 = 4 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_5 = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_6 = 6 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_7 = 7 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_8 = 8 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_9 = 9 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_10 = 10 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_11 = 11 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_12 = 12 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_13 = 13 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_14 = 14 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_15 = 15 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_16 = 16 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_17 = 17 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_18 = 18 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_19 = 19 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_20 = 20 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_21 = 21 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_22 = 22 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_23 = 23 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_24 = 24 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_25 = 25 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_26 = 26 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_27 = 27 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_28 = 28 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_29 = 29 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_30 = 30 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_31 = 31 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_32 = 32 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_33 = 33 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_34 = 34 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_35 = 35 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_36 = 36 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_37 = 37 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_38 = 38 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_39 = 39 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_40 = 40 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_41 = 41 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_42 = 42 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_43 = 43 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_44 = 44 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_45 = 45 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_46 = 46 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_47 = 47 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_48 = 48 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_49 = 49 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_50 = 50 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_51 = 51 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_52 = 52 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_53 = 53 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_54 = 54 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_55 = 55 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_56 = 56 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_57 = 57 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_58 = 58 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_59 = 59 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_60 = 60 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_61 = 61 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_62 = 62 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_HOLD2_NTL_63 = 63 ;
+
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_0 = 0 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_1 = 1 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_2 = 2 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_3 = 3 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_4 = 4 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_5 = 5 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_6 = 6 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_7 = 7 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_8 = 8 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_9 = 9 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_10 = 10 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_11 = 11 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_12 = 12 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_13 = 13 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_14 = 14 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_15 = 15 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_16 = 16 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_17 = 17 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_18 = 18 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_19 = 19 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_20 = 20 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_21 = 21 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_22 = 22 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_23 = 23 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_24 = 24 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_25 = 25 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_26 = 26 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_27 = 27 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_28 = 28 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_29 = 29 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_30 = 30 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_31 = 31 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_32 = 32 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_33 = 33 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_34 = 34 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_35 = 35 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_36 = 36 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_37 = 37 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_38 = 38 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_39 = 39 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_40 = 40 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_41 = 41 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_42 = 42 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_43 = 43 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_44 = 44 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_45 = 45 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_46 = 46 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_47 = 47 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_48 = 48 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_49 = 49 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_50 = 50 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_51 = 51 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_52 = 52 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_53 = 53 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_54 = 54 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_55 = 55 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_56 = 56 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_57 = 57 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_58 = 58 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_59 = 59 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_60 = 60 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_61 = 61 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_62 = 62 ;
+static const uint8_t P9N2_PU_NPU2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_63 = 63 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_0 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_1 = 1 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_2 = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_3 = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_4 = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_5 = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_6 = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_7 = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_8 = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_9 = 9 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_10 = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_11 = 11 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_12 = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_13 = 13 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_14 = 14 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_15 = 15 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_16 = 16 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_17 = 17 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_18 = 18 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_19 = 19 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_20 = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_21 = 21 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_22 = 22 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_23 = 23 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_24 = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_25 = 25 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_26 = 26 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_27 = 27 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_28 = 28 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_29 = 29 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_30 = 30 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_31 = 31 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_32 = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_33 = 33 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_34 = 34 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_35 = 35 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_36 = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_37 = 37 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_38 = 38 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_39 = 39 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_40 = 40 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_41 = 41 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_42 = 42 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_43 = 43 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_44 = 44 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_45 = 45 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_46 = 46 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_47 = 47 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_48 = 48 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_49 = 49 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_50 = 50 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_51 = 51 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_52 = 52 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_53 = 53 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_54 = 54 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_55 = 55 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_56 = 56 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_57 = 57 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_58 = 58 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_59 = 59 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_60 = 60 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_61 = 61 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_62 = 62 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_63 = 63 ;
+
+static const uint8_t P9N2_PU_NPU2_NTL1_CERR_LOG_FIRST_BITS = 47 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CERR_LOG_FIRST_BITS_LEN = 17 ;
+
+static const uint8_t P9N2_PU_NPU2_NTL1_CERR_LOG_HOLD_IDIAL_BBUF_RDWR = 47 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CERR_LOG_HOLD_IDIAL_IBUF_RDWR = 48 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CERR_LOG_HOLD_IDIAL_OBUF_RDWR = 49 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CERR_LOG_HOLD_IDIAL_RQIN_OVF = 50 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CERR_LOG_HOLD_IDIAL_RQIN_OVF_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CERR_LOG_HOLD_IDIAL_IBUF_CTL_PIPE = 56 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CERR_LOG_HOLD_IDIAL_PBTX_PIPE = 57 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CERR_LOG_HOLD_IDIAL_MRG_IR_PIPE = 58 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CERR_LOG_HOLD_IDIAL_MRG_OR_PIPE = 59 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CERR_LOG_HOLD_IDIAL_AMO_ADDR = 60 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CERR_LOG_HOLD_IDIAL_PBRX_RTAG = 61 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CERR_LOG_HOLD_IDIAL_IBUF_WRITE = 62 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CERR_LOG_HOLD_IDIAL_IBUF_WARB = 63 ;
+
+static const uint8_t P9N2_PU_NPU2_NTL1_CERR_LOG_MASK_BITS = 47 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CERR_LOG_MASK_BITS_LEN = 17 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_0 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_1 = 1 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_2 = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_3 = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_4 = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_5 = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_6 = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_7 = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_8 = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_9 = 9 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_10 = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_11 = 11 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_12 = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_13 = 13 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_14 = 14 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_15 = 15 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_16 = 16 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_17 = 17 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_18 = 18 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_19 = 19 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_20 = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_21 = 21 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_22 = 22 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_23 = 23 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_0 = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_1 = 25 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_2 = 26 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_3 = 27 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_4 = 28 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_5 = 29 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_6 = 30 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_7 = 31 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_ASBE_0 = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_ASBE_1 = 33 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_ASBE_2 = 34 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_ASBE_3 = 35 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_0 = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_1 = 37 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_2 = 38 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_3 = 39 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_4 = 40 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_5 = 41 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_6 = 42 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_7 = 43 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_REG_0 = 44 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_REG_1 = 45 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_REG_2 = 46 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_REG_3 = 47 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_0 = 48 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_1 = 49 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_2 = 50 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_3 = 51 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_4 = 52 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_5 = 53 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_6 = 54 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_7 = 55 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_8 = 56 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_9 = 57 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_10 = 58 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_11 = 59 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_12 = 60 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_13 = 61 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_14 = 62 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_15 = 63 ;
+
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_0 = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_1 = 1 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_2 = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_3 = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_4 = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_5 = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_6 = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_7 = 7 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_8 = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_9 = 9 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_10 = 10 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_11 = 11 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_12 = 12 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_13 = 13 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_14 = 14 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_15 = 15 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_16 = 16 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_17 = 17 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_18 = 18 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_19 = 19 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_20 = 20 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_21 = 21 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_22 = 22 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_23 = 23 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_0 = 24 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_1 = 25 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_2 = 26 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_3 = 27 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_4 = 28 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_5 = 29 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_6 = 30 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_7 = 31 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_ASBE_0 = 32 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_ASBE_1 = 33 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_ASBE_2 = 34 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_ASBE_3 = 35 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_0 = 36 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_1 = 37 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_2 = 38 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_3 = 39 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_4 = 40 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_5 = 41 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_6 = 42 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_7 = 43 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_REG_0 = 44 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_REG_1 = 45 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_REG_2 = 46 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_REG_3 = 47 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_0 = 48 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_1 = 49 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_2 = 50 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_3 = 51 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_4 = 52 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_5 = 53 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_6 = 54 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_7 = 55 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_8 = 56 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_9 = 57 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_10 = 58 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_11 = 59 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_12 = 60 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_13 = 61 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_14 = 62 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_15 = 63 ;
+
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_NCF_0 = 0 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_NCF_1 = 1 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_NCF_2 = 2 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_NCF_3 = 3 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_NCF_4 = 4 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_NCF_5 = 5 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_NCF_6 = 6 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_NCF_7 = 7 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_NVF_0 = 8 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_NVF_1 = 9 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_NVF_2 = 10 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_NVF_3 = 11 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_NVF_4 = 12 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_NVF_5 = 13 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_NVF_6 = 14 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_NVF_7 = 15 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_NVF_8 = 16 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_NVF_9 = 17 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_NVF_10 = 18 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_NVF_11 = 19 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_NVF_12 = 20 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_NVF_13 = 21 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_NVF_14 = 22 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_NVF_15 = 23 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_NVF_16 = 24 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_NVF_17 = 25 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_NVF_18 = 26 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_NVF_19 = 27 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_OCR_0 = 28 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_OCR_1 = 29 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_OCR_2 = 30 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_OCR_3 = 31 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_OCR_4 = 32 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_OCR_5 = 33 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_OCR_6 = 34 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_OCR_7 = 35 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_ASBE_0 = 36 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_ASBE_1 = 37 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_ASBE_2 = 38 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_ASBE_3 = 39 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_ASBE_4 = 40 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_ASBE_5 = 41 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_ASBE_6 = 42 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_ASBE_7 = 43 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_PBR_0 = 44 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_PBR_1 = 45 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_PBR_2 = 46 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_PBR_3 = 47 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_PBR_4 = 48 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_PBR_5 = 49 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_PBR_6 = 50 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_PBR_7 = 51 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_REG_0 = 52 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_REG_1 = 53 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_REG_2 = 54 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_REG_3 = 55 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_DUE_0 = 56 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_DUE_1 = 57 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_DUE_2 = 58 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_DUE_3 = 59 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_PEF_0 = 60 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_PEF_1 = 61 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_PEF_2 = 62 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK0_IDIAL_CTL_MASK_PEF_3 = 63 ;
+
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_0 = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_1 = 1 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_2 = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_3 = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_4 = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_5 = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_6 = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_7 = 7 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_8 = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_9 = 9 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_10 = 10 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_11 = 11 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_12 = 12 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_13 = 13 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_14 = 14 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_15 = 15 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_16 = 16 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_17 = 17 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_18 = 18 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_19 = 19 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_20 = 20 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_21 = 21 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_22 = 22 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_23 = 23 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_0 = 24 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_1 = 25 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_2 = 26 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_3 = 27 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_4 = 28 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_5 = 29 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_6 = 30 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_7 = 31 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_ASBE_0 = 32 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_ASBE_1 = 33 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_ASBE_2 = 34 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_ASBE_3 = 35 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_0 = 36 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_1 = 37 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_2 = 38 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_3 = 39 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_4 = 40 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_5 = 41 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_6 = 42 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_7 = 43 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_REG_0 = 44 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_REG_1 = 45 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_REG_2 = 46 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_REG_3 = 47 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_0 = 48 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_1 = 49 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_2 = 50 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_3 = 51 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_4 = 52 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_5 = 53 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_6 = 54 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_7 = 55 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_8 = 56 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_9 = 57 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_10 = 58 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_11 = 59 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_12 = 60 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_13 = 61 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_14 = 62 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_15 = 63 ;
+
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_0 = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_1 = 1 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_2 = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_3 = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_4 = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_5 = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_6 = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_7 = 7 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_8 = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_9 = 9 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_10 = 10 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_11 = 11 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_12 = 12 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_13 = 13 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_14 = 14 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_15 = 15 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_16 = 16 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_17 = 17 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_18 = 18 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_19 = 19 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_20 = 20 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_21 = 21 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_22 = 22 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_23 = 23 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_0 = 24 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_1 = 25 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_2 = 26 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_3 = 27 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_4 = 28 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_5 = 29 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_6 = 30 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_7 = 31 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_ASBE_0 = 32 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_ASBE_1 = 33 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_ASBE_2 = 34 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_ASBE_3 = 35 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_0 = 36 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_1 = 37 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_2 = 38 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_3 = 39 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_4 = 40 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_5 = 41 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_6 = 42 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_7 = 43 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_REG_0 = 44 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_REG_1 = 45 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_REG_2 = 46 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_REG_3 = 47 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_0 = 48 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_1 = 49 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_2 = 50 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_3 = 51 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_4 = 52 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_5 = 53 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_6 = 54 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_7 = 55 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_8 = 56 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_9 = 57 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_10 = 58 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_11 = 59 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_12 = 60 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_13 = 61 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_14 = 62 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_15 = 63 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_0 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_1 = 1 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_2 = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_3 = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_4 = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_5 = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_6 = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_7 = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_8 = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_9 = 9 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_10 = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_11 = 11 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_12 = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_13 = 13 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_14 = 14 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_15 = 15 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_16 = 16 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_17 = 17 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_18 = 18 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_19 = 19 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_20 = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_21 = 21 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_22 = 22 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_23 = 23 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_0 = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_1 = 25 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_2 = 26 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_3 = 27 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_4 = 28 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_5 = 29 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_6 = 30 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_7 = 31 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_ASBE_0 = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_ASBE_1 = 33 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_ASBE_2 = 34 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_ASBE_3 = 35 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_0 = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_1 = 37 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_2 = 38 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_3 = 39 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_4 = 40 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_5 = 41 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_6 = 42 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_7 = 43 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_REG_0 = 44 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_REG_1 = 45 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_REG_2 = 46 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_REG_3 = 47 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_0 = 48 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_1 = 49 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_2 = 50 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_3 = 51 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_4 = 52 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_5 = 53 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_6 = 54 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_7 = 55 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_8 = 56 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_9 = 57 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_10 = 58 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_11 = 59 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_12 = 60 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_13 = 61 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_14 = 62 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_15 = 63 ;
+
+static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_NVF_0 = 0 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_NVF_1 = 1 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_NVF_2 = 2 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_NVF_3 = 3 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_NVF_4 = 4 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_NVF_5 = 5 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_NVF_6 = 6 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_NVF_7 = 7 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_NVF_8 = 8 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_NVF_9 = 9 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_NVF_10 = 10 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_NVF_11 = 11 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_NVF_12 = 12 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_NVF_13 = 13 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_NVF_14 = 14 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_NVF_15 = 15 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_NVF_16 = 16 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_NVF_17 = 17 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_NVF_18 = 18 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_NVF_19 = 19 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_NVF_20 = 20 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_NVF_21 = 21 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_NVF_22 = 22 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_NVF_23 = 23 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_NCF_0 = 24 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_NCF_1 = 25 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_NCF_2 = 26 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_NCF_3 = 27 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_NCF_4 = 28 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_NCF_5 = 29 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_NCF_6 = 30 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_NCF_7 = 31 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_ASBE_0 = 32 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_ASBE_1 = 33 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_ASBE_2 = 34 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_ASBE_3 = 35 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_PBR_0 = 36 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_PBR_1 = 37 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_PBR_2 = 38 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_PBR_3 = 39 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_PBR_4 = 40 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_PBR_5 = 41 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_PBR_6 = 42 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_PBR_7 = 43 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_REG_0 = 44 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_REG_1 = 45 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_REG_2 = 46 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_REG_3 = 47 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_OCR_0 = 48 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_OCR_1 = 49 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_OCR_2 = 50 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_OCR_3 = 51 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_OCR_4 = 52 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_OCR_5 = 53 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_OCR_6 = 54 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_OCR_7 = 55 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_OCR_8 = 56 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_OCR_9 = 57 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_OCR_10 = 58 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_OCR_11 = 59 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_OCR_12 = 60 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_OCR_13 = 61 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_OCR_14 = 62 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK0_IDIAL_SM_MASK_OCR_15 = 63 ;
+
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_0 = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_1 = 1 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_2 = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_3 = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_4 = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_5 = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_6 = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_7 = 7 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_8 = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_9 = 9 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_10 = 10 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_11 = 11 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_12 = 12 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_13 = 13 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_14 = 14 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_15 = 15 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_16 = 16 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_17 = 17 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_18 = 18 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_19 = 19 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_20 = 20 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_21 = 21 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_22 = 22 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_23 = 23 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_0 = 24 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_1 = 25 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_2 = 26 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_3 = 27 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_4 = 28 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_5 = 29 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_6 = 30 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_7 = 31 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_ASBE_0 = 32 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_ASBE_1 = 33 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_ASBE_2 = 34 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_ASBE_3 = 35 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_0 = 36 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_1 = 37 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_2 = 38 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_3 = 39 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_4 = 40 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_5 = 41 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_6 = 42 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_7 = 43 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_REG_0 = 44 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_REG_1 = 45 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_REG_2 = 46 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_REG_3 = 47 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_0 = 48 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_1 = 49 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_2 = 50 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_3 = 51 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_4 = 52 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_5 = 53 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_6 = 54 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_7 = 55 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_8 = 56 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_9 = 57 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_10 = 58 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_11 = 59 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_12 = 60 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_13 = 61 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_14 = 62 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_15 = 63 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_NVF_0 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_NVF_1 = 1 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_NVF_2 = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_NVF_3 = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_NVF_4 = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_NVF_5 = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_NVF_6 = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_NVF_7 = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_NVF_8 = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_NVF_9 = 9 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_NVF_10 = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_NVF_11 = 11 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_NVF_12 = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_NVF_13 = 13 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_NVF_14 = 14 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_NVF_15 = 15 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_NVF_16 = 16 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_NVF_17 = 17 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_NVF_18 = 18 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_NVF_19 = 19 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_NVF_20 = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_NVF_21 = 21 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_NVF_22 = 22 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_NVF_23 = 23 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_NCF_0 = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_NCF_1 = 25 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_NCF_2 = 26 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_NCF_3 = 27 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_NCF_4 = 28 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_NCF_5 = 29 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_NCF_6 = 30 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_NCF_7 = 31 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_ASBE_0 = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_ASBE_1 = 33 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_ASBE_2 = 34 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_ASBE_3 = 35 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_PBR_0 = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_PBR_1 = 37 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_PBR_2 = 38 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_PBR_3 = 39 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_PBR_4 = 40 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_PBR_5 = 41 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_PBR_6 = 42 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_PBR_7 = 43 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_REG_0 = 44 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_REG_1 = 45 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_REG_2 = 46 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_REG_3 = 47 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_OCR_0 = 48 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_OCR_1 = 49 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_OCR_2 = 50 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_OCR_3 = 51 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_OCR_4 = 52 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_OCR_5 = 53 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_OCR_6 = 54 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_OCR_7 = 55 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_OCR_8 = 56 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_OCR_9 = 57 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_OCR_10 = 58 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_OCR_11 = 59 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_OCR_12 = 60 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_OCR_13 = 61 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_OCR_14 = 62 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK0_IDIAL_SM_MASK_OCR_15 = 63 ;
+
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_0 = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_1 = 1 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_2 = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_3 = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_4 = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_5 = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_6 = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_7 = 7 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_8 = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_9 = 9 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_10 = 10 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_11 = 11 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_12 = 12 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_13 = 13 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_14 = 14 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_15 = 15 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_16 = 16 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_17 = 17 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_18 = 18 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_19 = 19 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_20 = 20 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_21 = 21 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_22 = 22 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_23 = 23 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_0 = 24 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_1 = 25 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_2 = 26 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_3 = 27 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_4 = 28 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_5 = 29 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_6 = 30 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_7 = 31 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_ASBE_0 = 32 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_ASBE_1 = 33 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_ASBE_2 = 34 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_ASBE_3 = 35 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_0 = 36 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_1 = 37 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_2 = 38 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_3 = 39 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_4 = 40 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_5 = 41 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_6 = 42 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_7 = 43 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_REG_0 = 44 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_REG_1 = 45 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_REG_2 = 46 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_REG_3 = 47 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_0 = 48 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_1 = 49 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_2 = 50 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_3 = 51 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_4 = 52 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_5 = 53 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_6 = 54 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_7 = 55 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_8 = 56 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_9 = 57 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_10 = 58 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_11 = 59 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_12 = 60 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_13 = 61 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_14 = 62 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_OCR_15 = 63 ;
+
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_0 = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_1 = 1 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_2 = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_3 = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_4 = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_5 = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_6 = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_7 = 7 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_8 = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_9 = 9 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_10 = 10 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_11 = 11 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_12 = 12 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_13 = 13 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_14 = 14 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_15 = 15 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_16 = 16 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_17 = 17 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_18 = 18 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_19 = 19 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_20 = 20 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_21 = 21 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_22 = 22 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_23 = 23 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_0 = 24 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_1 = 25 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_2 = 26 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_3 = 27 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_4 = 28 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_5 = 29 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_6 = 30 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_7 = 31 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_ASBE_0 = 32 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_ASBE_1 = 33 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_ASBE_2 = 34 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_ASBE_3 = 35 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_0 = 36 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_1 = 37 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_2 = 38 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_3 = 39 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_4 = 40 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_5 = 41 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_6 = 42 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_7 = 43 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_REG_0 = 44 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_REG_1 = 45 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_REG_2 = 46 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_REG_3 = 47 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_0 = 48 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_1 = 49 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_2 = 50 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_3 = 51 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_4 = 52 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_5 = 53 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_6 = 54 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_7 = 55 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_8 = 56 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_9 = 57 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_10 = 58 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_11 = 59 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_12 = 60 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_13 = 61 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_14 = 62 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_OCR_15 = 63 ;
+
+static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_NCF_0 = 0 ;
+static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_NCF_1 = 1 ;
+static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_NCF_2 = 2 ;
+static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_NCF_3 = 3 ;
+static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_NCF_4 = 4 ;
+static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_NCF_5 = 5 ;
+static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_NCF_6 = 6 ;
+static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_NCF_7 = 7 ;
+static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_NVF_0 = 8 ;
+static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_NVF_1 = 9 ;
+static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_NVF_2 = 10 ;
+static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_NVF_3 = 11 ;
+static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_NVF_4 = 12 ;
+static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_NVF_5 = 13 ;
+static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_NVF_6 = 14 ;
+static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_NVF_7 = 15 ;
+static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_NVF_8 = 16 ;
+static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_NVF_9 = 17 ;
+static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_NVF_10 = 18 ;
+static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_NVF_11 = 19 ;
+static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_NVF_12 = 20 ;
+static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_NVF_13 = 21 ;
+static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_NVF_14 = 22 ;
+static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_NVF_15 = 23 ;
+static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_NVF_16 = 24 ;
+static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_NVF_17 = 25 ;
+static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_NVF_18 = 26 ;
+static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_NVF_19 = 27 ;
+static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_OCR_0 = 28 ;
+static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_OCR_1 = 29 ;
+static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_OCR_2 = 30 ;
+static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_OCR_3 = 31 ;
+static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_OCR_4 = 32 ;
+static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_OCR_5 = 33 ;
+static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_OCR_6 = 34 ;
+static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_OCR_7 = 35 ;
+static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_ASBE_0 = 36 ;
+static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_ASBE_1 = 37 ;
+static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_ASBE_2 = 38 ;
+static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_ASBE_3 = 39 ;
+static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_ASBE_4 = 40 ;
+static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_ASBE_5 = 41 ;
+static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_ASBE_6 = 42 ;
+static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_ASBE_7 = 43 ;
+static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_PBR_0 = 44 ;
+static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_PBR_1 = 45 ;
+static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_PBR_2 = 46 ;
+static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_PBR_3 = 47 ;
+static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_PBR_4 = 48 ;
+static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_PBR_5 = 49 ;
+static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_PBR_6 = 50 ;
+static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_PBR_7 = 51 ;
+static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_REG_0 = 52 ;
+static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_REG_1 = 53 ;
+static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_REG_2 = 54 ;
+static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_REG_3 = 55 ;
+static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_DUE_0 = 56 ;
+static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_DUE_1 = 57 ;
+static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_DUE_2 = 58 ;
+static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_DUE_3 = 59 ;
+static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_PEF_0 = 60 ;
+static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_PEF_1 = 61 ;
+static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_PEF_2 = 62 ;
+static const uint8_t P9N2_NV_CERR_MASK0_IDIAL_CTL_MASK_PEF_3 = 63 ;
+
+static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_NVF_0 = 0 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_NVF_1 = 1 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_NVF_2 = 2 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_NVF_3 = 3 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_NVF_4 = 4 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_NVF_5 = 5 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_NVF_6 = 6 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_NVF_7 = 7 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_NVF_8 = 8 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_NVF_9 = 9 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_NVF_10 = 10 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_NVF_11 = 11 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_NVF_12 = 12 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_NVF_13 = 13 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_NVF_14 = 14 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_NVF_15 = 15 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_NVF_16 = 16 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_NVF_17 = 17 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_NVF_18 = 18 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_NVF_19 = 19 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_NVF_20 = 20 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_NVF_21 = 21 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_NVF_22 = 22 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_NVF_23 = 23 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_NCF_0 = 24 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_NCF_1 = 25 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_NCF_2 = 26 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_NCF_3 = 27 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_NCF_4 = 28 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_NCF_5 = 29 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_NCF_6 = 30 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_NCF_7 = 31 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_ASBE_0 = 32 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_ASBE_1 = 33 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_ASBE_2 = 34 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_ASBE_3 = 35 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_PBR_0 = 36 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_PBR_1 = 37 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_PBR_2 = 38 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_PBR_3 = 39 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_PBR_4 = 40 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_PBR_5 = 41 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_PBR_6 = 42 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_PBR_7 = 43 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_REG_0 = 44 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_REG_1 = 45 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_REG_2 = 46 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_REG_3 = 47 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_OCR_0 = 48 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_OCR_1 = 49 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_OCR_2 = 50 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_OCR_3 = 51 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_OCR_4 = 52 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_OCR_5 = 53 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_OCR_6 = 54 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_OCR_7 = 55 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_OCR_8 = 56 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_OCR_9 = 57 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_OCR_10 = 58 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_OCR_11 = 59 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_OCR_12 = 60 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_OCR_13 = 61 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_OCR_14 = 62 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK0_IDIAL_SM_MASK_OCR_15 = 63 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_0 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_1 = 1 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_2 = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_3 = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_4 = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_5 = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_6 = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_7 = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_8 = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_9 = 9 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_10 = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_11 = 11 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_12 = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_13 = 13 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_14 = 14 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_15 = 15 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_16 = 16 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_17 = 17 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_18 = 18 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_19 = 19 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_20 = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_21 = 21 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_22 = 22 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_23 = 23 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_0 = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_1 = 25 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_2 = 26 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_3 = 27 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_4 = 28 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_5 = 29 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_6 = 30 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_7 = 31 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_ASBE_0 = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_ASBE_1 = 33 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_ASBE_2 = 34 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_ASBE_3 = 35 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_0 = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_1 = 37 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_2 = 38 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_3 = 39 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_4 = 40 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_5 = 41 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_6 = 42 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_7 = 43 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_REG_0 = 44 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_REG_1 = 45 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_REG_2 = 46 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_REG_3 = 47 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_0 = 48 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_1 = 49 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_2 = 50 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_3 = 51 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_4 = 52 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_5 = 53 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_6 = 54 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_7 = 55 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_8 = 56 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_9 = 57 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_10 = 58 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_11 = 59 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_12 = 60 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_13 = 61 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_14 = 62 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK0_IDIAL_SM_MASK_OCR_15 = 63 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_0 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_1 = 1 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_2 = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_3 = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_4 = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_5 = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_6 = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_7 = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_8 = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_9 = 9 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_10 = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_11 = 11 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_12 = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_13 = 13 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_14 = 14 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_15 = 15 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_FWD_0 = 16 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_FWD_1 = 17 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_FWD_2 = 18 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_FWD_3 = 19 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_AUE_0 = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_AUE_1 = 21 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_AUE_2 = 22 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_AUE_3 = 23 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_0 = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_1 = 25 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_2 = 26 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_3 = 27 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_4 = 28 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_5 = 29 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_6 = 30 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_7 = 31 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_0 = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_1 = 33 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_2 = 34 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_3 = 35 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_4 = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_5 = 37 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_6 = 38 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_7 = 39 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_8 = 40 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_9 = 41 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_10 = 42 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_11 = 43 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_0 = 44 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_1 = 45 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_2 = 46 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_3 = 47 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_4 = 48 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_5 = 49 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_6 = 50 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_7 = 51 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_8 = 52 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_9 = 53 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_10 = 54 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_11 = 55 ;
+
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_0 = 0 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_1 = 1 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_2 = 2 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_3 = 3 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_4 = 4 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_5 = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_6 = 6 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_7 = 7 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_8 = 8 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_9 = 9 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_10 = 10 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_11 = 11 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_12 = 12 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_13 = 13 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_14 = 14 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_15 = 15 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_16 = 16 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_17 = 17 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_18 = 18 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_19 = 19 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_20 = 20 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_21 = 21 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_22 = 22 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_23 = 23 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_24 = 24 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_25 = 25 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_26 = 26 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_27 = 27 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_28 = 28 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_29 = 29 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_30 = 30 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_31 = 31 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_32 = 32 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_33 = 33 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_34 = 34 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_35 = 35 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_36 = 36 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_37 = 37 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_38 = 38 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_39 = 39 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_40 = 40 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_41 = 41 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_42 = 42 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_43 = 43 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_44 = 44 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_45 = 45 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_46 = 46 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_47 = 47 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_48 = 48 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_49 = 49 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_50 = 50 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_51 = 51 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_52 = 52 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_53 = 53 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_54 = 54 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_55 = 55 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_56 = 56 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_57 = 57 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_58 = 58 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_59 = 59 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_60 = 60 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_61 = 61 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_62 = 62 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK1_NTL_63 = 63 ;
+
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_0 = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_1 = 1 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_2 = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_3 = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_4 = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_5 = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_6 = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_7 = 7 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_8 = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_9 = 9 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_10 = 10 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_11 = 11 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_12 = 12 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_13 = 13 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_14 = 14 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_15 = 15 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_FWD_0 = 16 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_FWD_1 = 17 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_FWD_2 = 18 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_FWD_3 = 19 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_AUE_0 = 20 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_AUE_1 = 21 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_AUE_2 = 22 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_AUE_3 = 23 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_0 = 24 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_1 = 25 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_2 = 26 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_3 = 27 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_4 = 28 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_5 = 29 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_6 = 30 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_7 = 31 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_0 = 32 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_1 = 33 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_2 = 34 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_3 = 35 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_4 = 36 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_5 = 37 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_6 = 38 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_7 = 39 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_8 = 40 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_9 = 41 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_10 = 42 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_11 = 43 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_0 = 44 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_1 = 45 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_2 = 46 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_3 = 47 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_4 = 48 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_5 = 49 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_6 = 50 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_7 = 51 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_8 = 52 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_9 = 53 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_10 = 54 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_11 = 55 ;
+
+static const uint8_t P9N2__SM1_CERR_MASK1_NTL_0 = 0 ;
+static const uint8_t P9N2__SM1_CERR_MASK1_NTL_1 = 1 ;
+static const uint8_t P9N2__SM1_CERR_MASK1_NTL_2 = 2 ;
+static const uint8_t P9N2__SM1_CERR_MASK1_NTL_3 = 3 ;
+static const uint8_t P9N2__SM1_CERR_MASK1_NTL_4 = 4 ;
+static const uint8_t P9N2__SM1_CERR_MASK1_NTL_5 = 5 ;
+static const uint8_t P9N2__SM1_CERR_MASK1_NTL_6 = 6 ;
+static const uint8_t P9N2__SM1_CERR_MASK1_NTL_7 = 7 ;
+static const uint8_t P9N2__SM1_CERR_MASK1_NTL_8 = 8 ;
+static const uint8_t P9N2__SM1_CERR_MASK1_NTL_9 = 9 ;
+static const uint8_t P9N2__SM1_CERR_MASK1_NTL_10 = 10 ;
+static const uint8_t P9N2__SM1_CERR_MASK1_NTL_11 = 11 ;
+static const uint8_t P9N2__SM1_CERR_MASK1_NTL_12 = 12 ;
+static const uint8_t P9N2__SM1_CERR_MASK1_NTL_13 = 13 ;
+static const uint8_t P9N2__SM1_CERR_MASK1_NTL_14 = 14 ;
+static const uint8_t P9N2__SM1_CERR_MASK1_NTL_15 = 15 ;
+static const uint8_t P9N2__SM1_CERR_MASK1_NTL_16 = 16 ;
+static const uint8_t P9N2__SM1_CERR_MASK1_NTL_17 = 17 ;
+static const uint8_t P9N2__SM1_CERR_MASK1_NTL_18 = 18 ;
+static const uint8_t P9N2__SM1_CERR_MASK1_NTL_19 = 19 ;
+static const uint8_t P9N2__SM1_CERR_MASK1_NTL_20 = 20 ;
+static const uint8_t P9N2__SM1_CERR_MASK1_NTL_21 = 21 ;
+static const uint8_t P9N2__SM1_CERR_MASK1_NTL_22 = 22 ;
+static const uint8_t P9N2__SM1_CERR_MASK1_NTL_23 = 23 ;
+static const uint8_t P9N2__SM1_CERR_MASK1_NTL_24 = 24 ;
+static const uint8_t P9N2__SM1_CERR_MASK1_NTL_25 = 25 ;
+static const uint8_t P9N2__SM1_CERR_MASK1_NTL_26 = 26 ;
+static const uint8_t P9N2__SM1_CERR_MASK1_NTL_27 = 27 ;
+static const uint8_t P9N2__SM1_CERR_MASK1_NTL_28 = 28 ;
+static const uint8_t P9N2__SM1_CERR_MASK1_NTL_29 = 29 ;
+static const uint8_t P9N2__SM1_CERR_MASK1_NTL_30 = 30 ;
+static const uint8_t P9N2__SM1_CERR_MASK1_NTL_31 = 31 ;
+static const uint8_t P9N2__SM1_CERR_MASK1_NTL_32 = 32 ;
+static const uint8_t P9N2__SM1_CERR_MASK1_NTL_33 = 33 ;
+static const uint8_t P9N2__SM1_CERR_MASK1_NTL_34 = 34 ;
+static const uint8_t P9N2__SM1_CERR_MASK1_NTL_35 = 35 ;
+static const uint8_t P9N2__SM1_CERR_MASK1_NTL_36 = 36 ;
+static const uint8_t P9N2__SM1_CERR_MASK1_NTL_37 = 37 ;
+static const uint8_t P9N2__SM1_CERR_MASK1_NTL_38 = 38 ;
+static const uint8_t P9N2__SM1_CERR_MASK1_NTL_39 = 39 ;
+static const uint8_t P9N2__SM1_CERR_MASK1_NTL_40 = 40 ;
+static const uint8_t P9N2__SM1_CERR_MASK1_NTL_41 = 41 ;
+static const uint8_t P9N2__SM1_CERR_MASK1_NTL_42 = 42 ;
+static const uint8_t P9N2__SM1_CERR_MASK1_NTL_43 = 43 ;
+static const uint8_t P9N2__SM1_CERR_MASK1_NTL_44 = 44 ;
+static const uint8_t P9N2__SM1_CERR_MASK1_NTL_45 = 45 ;
+static const uint8_t P9N2__SM1_CERR_MASK1_NTL_46 = 46 ;
+static const uint8_t P9N2__SM1_CERR_MASK1_NTL_47 = 47 ;
+static const uint8_t P9N2__SM1_CERR_MASK1_NTL_48 = 48 ;
+static const uint8_t P9N2__SM1_CERR_MASK1_NTL_49 = 49 ;
+static const uint8_t P9N2__SM1_CERR_MASK1_NTL_50 = 50 ;
+static const uint8_t P9N2__SM1_CERR_MASK1_NTL_51 = 51 ;
+static const uint8_t P9N2__SM1_CERR_MASK1_NTL_52 = 52 ;
+static const uint8_t P9N2__SM1_CERR_MASK1_NTL_53 = 53 ;
+static const uint8_t P9N2__SM1_CERR_MASK1_NTL_54 = 54 ;
+static const uint8_t P9N2__SM1_CERR_MASK1_NTL_55 = 55 ;
+static const uint8_t P9N2__SM1_CERR_MASK1_NTL_56 = 56 ;
+static const uint8_t P9N2__SM1_CERR_MASK1_NTL_57 = 57 ;
+static const uint8_t P9N2__SM1_CERR_MASK1_NTL_58 = 58 ;
+static const uint8_t P9N2__SM1_CERR_MASK1_NTL_59 = 59 ;
+static const uint8_t P9N2__SM1_CERR_MASK1_NTL_60 = 60 ;
+static const uint8_t P9N2__SM1_CERR_MASK1_NTL_61 = 61 ;
+static const uint8_t P9N2__SM1_CERR_MASK1_NTL_62 = 62 ;
+static const uint8_t P9N2__SM1_CERR_MASK1_NTL_63 = 63 ;
+
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_0 = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_1 = 1 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_2 = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_3 = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_4 = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_5 = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_6 = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_7 = 7 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_8 = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_9 = 9 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_10 = 10 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_11 = 11 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_12 = 12 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_13 = 13 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_14 = 14 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_15 = 15 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_FWD_0 = 16 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_FWD_1 = 17 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_FWD_2 = 18 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_FWD_3 = 19 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_AUE_0 = 20 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_AUE_1 = 21 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_AUE_2 = 22 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_AUE_3 = 23 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_0 = 24 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_1 = 25 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_2 = 26 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_3 = 27 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_4 = 28 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_5 = 29 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_6 = 30 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_7 = 31 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_0 = 32 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_1 = 33 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_2 = 34 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_3 = 35 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_4 = 36 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_5 = 37 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_6 = 38 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_7 = 39 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_8 = 40 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_9 = 41 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_10 = 42 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_11 = 43 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_0 = 44 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_1 = 45 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_2 = 46 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_3 = 47 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_4 = 48 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_5 = 49 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_6 = 50 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_7 = 51 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_8 = 52 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_9 = 53 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_10 = 54 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_11 = 55 ;
+
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_NLG_0 = 0 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_NLG_1 = 1 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_NLG_2 = 2 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_NLG_3 = 3 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_NLG_4 = 4 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_NLG_5 = 5 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_NLG_6 = 6 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_NLG_7 = 7 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_NLG_8 = 8 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_NLG_9 = 9 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_NLG_10 = 10 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_NLG_11 = 11 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_NLG_12 = 12 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_NLG_13 = 13 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_NLG_14 = 14 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_NLG_15 = 15 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_FWD_0 = 16 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_FWD_1 = 17 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_FWD_2 = 18 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_FWD_3 = 19 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_FWD_4 = 20 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_FWD_5 = 21 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_FWD_6 = 22 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_FWD_7 = 23 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_AUE_0 = 24 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_AUE_1 = 25 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_AUE_2 = 26 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_AUE_3 = 27 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_AUE_4 = 28 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_AUE_5 = 29 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_AUE_6 = 30 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_AUE_7 = 31 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_PBP_0 = 32 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_PBP_1 = 33 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_PBP_2 = 34 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_PBP_3 = 35 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_PBP_4 = 36 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_PBP_5 = 37 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_PBP_6 = 38 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_PBP_7 = 39 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_PBF_0 = 40 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_PBF_1 = 41 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_PBF_2 = 42 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_PBF_3 = 43 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_PBF_4 = 44 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_PBF_5 = 45 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_PBF_6 = 46 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_PBF_7 = 47 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_PBC_0 = 48 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_PBC_1 = 49 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_PBC_2 = 50 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_PBC_3 = 51 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_PBC_4 = 52 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_PBC_5 = 53 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_PBC_6 = 54 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_PBC_7 = 55 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_RSV2_0 = 56 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_RSV2_1 = 57 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_RSV2_2 = 58 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_RSV2_3 = 59 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_RSV3_0 = 60 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_RSV3_1 = 61 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_RSV3_2 = 62 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MASK1_IDIAL_CTL_MASK_RSV3_3 = 63 ;
+
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_0 = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_1 = 1 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_2 = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_3 = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_4 = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_5 = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_6 = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_7 = 7 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_8 = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_9 = 9 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_10 = 10 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_11 = 11 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_12 = 12 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_13 = 13 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_14 = 14 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_15 = 15 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_FWD_0 = 16 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_FWD_1 = 17 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_FWD_2 = 18 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_FWD_3 = 19 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_AUE_0 = 20 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_AUE_1 = 21 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_AUE_2 = 22 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_AUE_3 = 23 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_0 = 24 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_1 = 25 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_2 = 26 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_3 = 27 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_4 = 28 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_5 = 29 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_6 = 30 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_7 = 31 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_0 = 32 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_1 = 33 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_2 = 34 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_3 = 35 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_4 = 36 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_5 = 37 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_6 = 38 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_7 = 39 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_8 = 40 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_9 = 41 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_10 = 42 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_11 = 43 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_0 = 44 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_1 = 45 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_2 = 46 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_3 = 47 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_4 = 48 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_5 = 49 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_6 = 50 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_7 = 51 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_8 = 52 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_9 = 53 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_10 = 54 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_11 = 55 ;
+
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_0 = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_1 = 1 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_2 = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_3 = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_4 = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_5 = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_6 = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_7 = 7 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_8 = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_9 = 9 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_10 = 10 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_11 = 11 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_12 = 12 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_13 = 13 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_14 = 14 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_15 = 15 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_FWD_0 = 16 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_FWD_1 = 17 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_FWD_2 = 18 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_FWD_3 = 19 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_AUE_0 = 20 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_AUE_1 = 21 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_AUE_2 = 22 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_AUE_3 = 23 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_0 = 24 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_1 = 25 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_2 = 26 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_3 = 27 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_4 = 28 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_5 = 29 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_6 = 30 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_7 = 31 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_0 = 32 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_1 = 33 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_2 = 34 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_3 = 35 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_4 = 36 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_5 = 37 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_6 = 38 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_7 = 39 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_8 = 40 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_9 = 41 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_10 = 42 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_11 = 43 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_0 = 44 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_1 = 45 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_2 = 46 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_3 = 47 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_4 = 48 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_5 = 49 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_6 = 50 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_7 = 51 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_8 = 52 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_9 = 53 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_10 = 54 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_11 = 55 ;
+
+static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_NLGX_0 = 0 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_NLGX_1 = 1 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_NLGX_2 = 2 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_NLGX_3 = 3 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_NLGX_4 = 4 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_NLGX_5 = 5 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_NLGX_6 = 6 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_NLGX_7 = 7 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_NLGX_8 = 8 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_NLGX_9 = 9 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_NLGX_10 = 10 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_NLGX_11 = 11 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_NLGX_12 = 12 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_NLGX_13 = 13 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_NLGX_14 = 14 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_NLGX_15 = 15 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_FWD_0 = 16 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_FWD_1 = 17 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_FWD_2 = 18 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_FWD_3 = 19 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_AUE_0 = 20 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_AUE_1 = 21 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_AUE_2 = 22 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_AUE_3 = 23 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_PBP_0 = 24 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_PBP_1 = 25 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_PBP_2 = 26 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_PBP_3 = 27 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_PBP_4 = 28 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_PBP_5 = 29 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_PBP_6 = 30 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_PBP_7 = 31 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_PBF_0 = 32 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_PBF_1 = 33 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_PBF_2 = 34 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_PBF_3 = 35 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_PBF_4 = 36 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_PBF_5 = 37 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_PBF_6 = 38 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_PBF_7 = 39 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_PBF_8 = 40 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_PBF_9 = 41 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_PBF_10 = 42 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_PBF_11 = 43 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_PBC_0 = 44 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_PBC_1 = 45 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_PBC_2 = 46 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_PBC_3 = 47 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_PBC_4 = 48 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_PBC_5 = 49 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_PBC_6 = 50 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_PBC_7 = 51 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_PBC_8 = 52 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_PBC_9 = 53 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_PBC_10 = 54 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK1_IDIAL_SM_MASK_PBC_11 = 55 ;
+
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_0 = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_1 = 1 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_2 = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_3 = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_4 = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_5 = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_6 = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_7 = 7 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_8 = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_9 = 9 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_10 = 10 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_11 = 11 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_12 = 12 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_13 = 13 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_14 = 14 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_15 = 15 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_FWD_0 = 16 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_FWD_1 = 17 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_FWD_2 = 18 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_FWD_3 = 19 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_AUE_0 = 20 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_AUE_1 = 21 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_AUE_2 = 22 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_AUE_3 = 23 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_0 = 24 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_1 = 25 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_2 = 26 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_3 = 27 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_4 = 28 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_5 = 29 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_6 = 30 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_7 = 31 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_0 = 32 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_1 = 33 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_2 = 34 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_3 = 35 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_4 = 36 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_5 = 37 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_6 = 38 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_7 = 39 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_8 = 40 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_9 = 41 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_10 = 42 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_11 = 43 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_0 = 44 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_1 = 45 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_2 = 46 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_3 = 47 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_4 = 48 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_5 = 49 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_6 = 50 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_7 = 51 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_8 = 52 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_9 = 53 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_10 = 54 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_11 = 55 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_0 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_1 = 1 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_2 = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_3 = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_4 = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_5 = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_6 = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_7 = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_8 = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_9 = 9 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_10 = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_11 = 11 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_12 = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_13 = 13 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_14 = 14 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_15 = 15 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_FWD_0 = 16 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_FWD_1 = 17 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_FWD_2 = 18 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_FWD_3 = 19 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_AUE_0 = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_AUE_1 = 21 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_AUE_2 = 22 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_AUE_3 = 23 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_0 = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_1 = 25 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_2 = 26 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_3 = 27 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_4 = 28 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_5 = 29 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_6 = 30 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_7 = 31 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_0 = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_1 = 33 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_2 = 34 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_3 = 35 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_4 = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_5 = 37 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_6 = 38 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_7 = 39 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_8 = 40 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_9 = 41 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_10 = 42 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_11 = 43 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_0 = 44 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_1 = 45 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_2 = 46 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_3 = 47 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_4 = 48 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_5 = 49 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_6 = 50 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_7 = 51 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_8 = 52 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_9 = 53 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_10 = 54 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_11 = 55 ;
+
+static const uint8_t P9N2__SM0_CERR_MASK1_NTL_0 = 0 ;
+static const uint8_t P9N2__SM0_CERR_MASK1_NTL_1 = 1 ;
+static const uint8_t P9N2__SM0_CERR_MASK1_NTL_2 = 2 ;
+static const uint8_t P9N2__SM0_CERR_MASK1_NTL_3 = 3 ;
+static const uint8_t P9N2__SM0_CERR_MASK1_NTL_4 = 4 ;
+static const uint8_t P9N2__SM0_CERR_MASK1_NTL_5 = 5 ;
+static const uint8_t P9N2__SM0_CERR_MASK1_NTL_6 = 6 ;
+static const uint8_t P9N2__SM0_CERR_MASK1_NTL_7 = 7 ;
+static const uint8_t P9N2__SM0_CERR_MASK1_NTL_8 = 8 ;
+static const uint8_t P9N2__SM0_CERR_MASK1_NTL_9 = 9 ;
+static const uint8_t P9N2__SM0_CERR_MASK1_NTL_10 = 10 ;
+static const uint8_t P9N2__SM0_CERR_MASK1_NTL_11 = 11 ;
+static const uint8_t P9N2__SM0_CERR_MASK1_NTL_12 = 12 ;
+static const uint8_t P9N2__SM0_CERR_MASK1_NTL_13 = 13 ;
+static const uint8_t P9N2__SM0_CERR_MASK1_NTL_14 = 14 ;
+static const uint8_t P9N2__SM0_CERR_MASK1_NTL_15 = 15 ;
+static const uint8_t P9N2__SM0_CERR_MASK1_NTL_16 = 16 ;
+static const uint8_t P9N2__SM0_CERR_MASK1_NTL_17 = 17 ;
+static const uint8_t P9N2__SM0_CERR_MASK1_NTL_18 = 18 ;
+static const uint8_t P9N2__SM0_CERR_MASK1_NTL_19 = 19 ;
+static const uint8_t P9N2__SM0_CERR_MASK1_NTL_20 = 20 ;
+static const uint8_t P9N2__SM0_CERR_MASK1_NTL_21 = 21 ;
+static const uint8_t P9N2__SM0_CERR_MASK1_NTL_22 = 22 ;
+static const uint8_t P9N2__SM0_CERR_MASK1_NTL_23 = 23 ;
+static const uint8_t P9N2__SM0_CERR_MASK1_NTL_24 = 24 ;
+static const uint8_t P9N2__SM0_CERR_MASK1_NTL_25 = 25 ;
+static const uint8_t P9N2__SM0_CERR_MASK1_NTL_26 = 26 ;
+static const uint8_t P9N2__SM0_CERR_MASK1_NTL_27 = 27 ;
+static const uint8_t P9N2__SM0_CERR_MASK1_NTL_28 = 28 ;
+static const uint8_t P9N2__SM0_CERR_MASK1_NTL_29 = 29 ;
+static const uint8_t P9N2__SM0_CERR_MASK1_NTL_30 = 30 ;
+static const uint8_t P9N2__SM0_CERR_MASK1_NTL_31 = 31 ;
+static const uint8_t P9N2__SM0_CERR_MASK1_NTL_32 = 32 ;
+static const uint8_t P9N2__SM0_CERR_MASK1_NTL_33 = 33 ;
+static const uint8_t P9N2__SM0_CERR_MASK1_NTL_34 = 34 ;
+static const uint8_t P9N2__SM0_CERR_MASK1_NTL_35 = 35 ;
+static const uint8_t P9N2__SM0_CERR_MASK1_NTL_36 = 36 ;
+static const uint8_t P9N2__SM0_CERR_MASK1_NTL_37 = 37 ;
+static const uint8_t P9N2__SM0_CERR_MASK1_NTL_38 = 38 ;
+static const uint8_t P9N2__SM0_CERR_MASK1_NTL_39 = 39 ;
+static const uint8_t P9N2__SM0_CERR_MASK1_NTL_40 = 40 ;
+static const uint8_t P9N2__SM0_CERR_MASK1_NTL_41 = 41 ;
+static const uint8_t P9N2__SM0_CERR_MASK1_NTL_42 = 42 ;
+static const uint8_t P9N2__SM0_CERR_MASK1_NTL_43 = 43 ;
+static const uint8_t P9N2__SM0_CERR_MASK1_NTL_44 = 44 ;
+static const uint8_t P9N2__SM0_CERR_MASK1_NTL_45 = 45 ;
+static const uint8_t P9N2__SM0_CERR_MASK1_NTL_46 = 46 ;
+static const uint8_t P9N2__SM0_CERR_MASK1_NTL_47 = 47 ;
+static const uint8_t P9N2__SM0_CERR_MASK1_NTL_48 = 48 ;
+static const uint8_t P9N2__SM0_CERR_MASK1_NTL_49 = 49 ;
+static const uint8_t P9N2__SM0_CERR_MASK1_NTL_50 = 50 ;
+static const uint8_t P9N2__SM0_CERR_MASK1_NTL_51 = 51 ;
+static const uint8_t P9N2__SM0_CERR_MASK1_NTL_52 = 52 ;
+static const uint8_t P9N2__SM0_CERR_MASK1_NTL_53 = 53 ;
+static const uint8_t P9N2__SM0_CERR_MASK1_NTL_54 = 54 ;
+static const uint8_t P9N2__SM0_CERR_MASK1_NTL_55 = 55 ;
+static const uint8_t P9N2__SM0_CERR_MASK1_NTL_56 = 56 ;
+static const uint8_t P9N2__SM0_CERR_MASK1_NTL_57 = 57 ;
+static const uint8_t P9N2__SM0_CERR_MASK1_NTL_58 = 58 ;
+static const uint8_t P9N2__SM0_CERR_MASK1_NTL_59 = 59 ;
+static const uint8_t P9N2__SM0_CERR_MASK1_NTL_60 = 60 ;
+static const uint8_t P9N2__SM0_CERR_MASK1_NTL_61 = 61 ;
+static const uint8_t P9N2__SM0_CERR_MASK1_NTL_62 = 62 ;
+static const uint8_t P9N2__SM0_CERR_MASK1_NTL_63 = 63 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_NLGX_0 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_NLGX_1 = 1 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_NLGX_2 = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_NLGX_3 = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_NLGX_4 = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_NLGX_5 = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_NLGX_6 = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_NLGX_7 = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_NLGX_8 = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_NLGX_9 = 9 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_NLGX_10 = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_NLGX_11 = 11 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_NLGX_12 = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_NLGX_13 = 13 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_NLGX_14 = 14 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_NLGX_15 = 15 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_FWD_0 = 16 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_FWD_1 = 17 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_FWD_2 = 18 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_FWD_3 = 19 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_AUE_0 = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_AUE_1 = 21 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_AUE_2 = 22 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_AUE_3 = 23 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_PBP_0 = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_PBP_1 = 25 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_PBP_2 = 26 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_PBP_3 = 27 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_PBP_4 = 28 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_PBP_5 = 29 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_PBP_6 = 30 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_PBP_7 = 31 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_PBF_0 = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_PBF_1 = 33 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_PBF_2 = 34 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_PBF_3 = 35 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_PBF_4 = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_PBF_5 = 37 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_PBF_6 = 38 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_PBF_7 = 39 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_PBF_8 = 40 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_PBF_9 = 41 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_PBF_10 = 42 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_PBF_11 = 43 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_PBC_0 = 44 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_PBC_1 = 45 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_PBC_2 = 46 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_PBC_3 = 47 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_PBC_4 = 48 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_PBC_5 = 49 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_PBC_6 = 50 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_PBC_7 = 51 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_PBC_8 = 52 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_PBC_9 = 53 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_PBC_10 = 54 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK1_IDIAL_SM_MASK_PBC_11 = 55 ;
+
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_0 = 0 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_1 = 1 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_2 = 2 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_3 = 3 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_4 = 4 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_5 = 5 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_6 = 6 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_7 = 7 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_8 = 8 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_9 = 9 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_10 = 10 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_11 = 11 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_12 = 12 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_13 = 13 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_14 = 14 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_15 = 15 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_16 = 16 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_17 = 17 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_18 = 18 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_19 = 19 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_20 = 20 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_21 = 21 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_22 = 22 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_23 = 23 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_24 = 24 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_25 = 25 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_26 = 26 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_27 = 27 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_28 = 28 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_29 = 29 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_30 = 30 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_31 = 31 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_32 = 32 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_33 = 33 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_34 = 34 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_35 = 35 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_36 = 36 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_37 = 37 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_38 = 38 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_39 = 39 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_40 = 40 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_41 = 41 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_42 = 42 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_43 = 43 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_44 = 44 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_45 = 45 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_46 = 46 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_47 = 47 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_48 = 48 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_49 = 49 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_50 = 50 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_51 = 51 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_52 = 52 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_53 = 53 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_54 = 54 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_55 = 55 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_56 = 56 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_57 = 57 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_58 = 58 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_59 = 59 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_60 = 60 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_61 = 61 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_62 = 62 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK1_NTL_63 = 63 ;
+
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_0 = 0 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_1 = 1 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_2 = 2 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_3 = 3 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_4 = 4 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_5 = 5 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_6 = 6 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_7 = 7 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_8 = 8 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_9 = 9 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_10 = 10 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_11 = 11 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_12 = 12 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_13 = 13 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_14 = 14 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_15 = 15 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_16 = 16 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_17 = 17 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_18 = 18 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_19 = 19 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_20 = 20 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_21 = 21 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_22 = 22 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_23 = 23 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_24 = 24 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_25 = 25 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_26 = 26 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_27 = 27 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_28 = 28 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_29 = 29 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_30 = 30 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_31 = 31 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_32 = 32 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_33 = 33 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_34 = 34 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_35 = 35 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_36 = 36 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_37 = 37 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_38 = 38 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_39 = 39 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_40 = 40 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_41 = 41 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_42 = 42 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_43 = 43 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_44 = 44 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_45 = 45 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_46 = 46 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_47 = 47 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_48 = 48 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_49 = 49 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_50 = 50 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_51 = 51 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_52 = 52 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_53 = 53 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_54 = 54 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_55 = 55 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_56 = 56 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_57 = 57 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_58 = 58 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_59 = 59 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_60 = 60 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_61 = 61 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_62 = 62 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK1_NTL_63 = 63 ;
+
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_0 = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_1 = 1 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_2 = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_3 = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_4 = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_5 = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_6 = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_7 = 7 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_8 = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_9 = 9 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_10 = 10 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_11 = 11 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_12 = 12 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_13 = 13 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_14 = 14 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_15 = 15 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_FWD_0 = 16 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_FWD_1 = 17 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_FWD_2 = 18 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_FWD_3 = 19 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_AUE_0 = 20 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_AUE_1 = 21 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_AUE_2 = 22 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_AUE_3 = 23 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_0 = 24 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_1 = 25 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_2 = 26 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_3 = 27 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_4 = 28 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_5 = 29 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_6 = 30 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_7 = 31 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_0 = 32 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_1 = 33 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_2 = 34 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_3 = 35 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_4 = 36 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_5 = 37 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_6 = 38 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_7 = 39 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_8 = 40 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_9 = 41 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_10 = 42 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_11 = 43 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_0 = 44 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_1 = 45 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_2 = 46 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_3 = 47 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_4 = 48 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_5 = 49 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_6 = 50 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_7 = 51 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_8 = 52 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_9 = 53 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_10 = 54 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_11 = 55 ;
+
+static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_NLG_0 = 0 ;
+static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_NLG_1 = 1 ;
+static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_NLG_2 = 2 ;
+static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_NLG_3 = 3 ;
+static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_NLG_4 = 4 ;
+static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_NLG_5 = 5 ;
+static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_NLG_6 = 6 ;
+static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_NLG_7 = 7 ;
+static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_NLG_8 = 8 ;
+static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_NLG_9 = 9 ;
+static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_NLG_10 = 10 ;
+static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_NLG_11 = 11 ;
+static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_NLG_12 = 12 ;
+static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_NLG_13 = 13 ;
+static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_NLG_14 = 14 ;
+static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_NLG_15 = 15 ;
+static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_FWD_0 = 16 ;
+static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_FWD_1 = 17 ;
+static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_FWD_2 = 18 ;
+static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_FWD_3 = 19 ;
+static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_FWD_4 = 20 ;
+static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_FWD_5 = 21 ;
+static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_FWD_6 = 22 ;
+static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_FWD_7 = 23 ;
+static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_AUE_0 = 24 ;
+static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_AUE_1 = 25 ;
+static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_AUE_2 = 26 ;
+static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_AUE_3 = 27 ;
+static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_AUE_4 = 28 ;
+static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_AUE_5 = 29 ;
+static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_AUE_6 = 30 ;
+static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_AUE_7 = 31 ;
+static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_PBP_0 = 32 ;
+static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_PBP_1 = 33 ;
+static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_PBP_2 = 34 ;
+static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_PBP_3 = 35 ;
+static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_PBP_4 = 36 ;
+static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_PBP_5 = 37 ;
+static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_PBP_6 = 38 ;
+static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_PBP_7 = 39 ;
+static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_PBF_0 = 40 ;
+static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_PBF_1 = 41 ;
+static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_PBF_2 = 42 ;
+static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_PBF_3 = 43 ;
+static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_PBF_4 = 44 ;
+static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_PBF_5 = 45 ;
+static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_PBF_6 = 46 ;
+static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_PBF_7 = 47 ;
+static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_PBC_0 = 48 ;
+static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_PBC_1 = 49 ;
+static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_PBC_2 = 50 ;
+static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_PBC_3 = 51 ;
+static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_PBC_4 = 52 ;
+static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_PBC_5 = 53 ;
+static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_PBC_6 = 54 ;
+static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_PBC_7 = 55 ;
+static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_RSV2_0 = 56 ;
+static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_RSV2_1 = 57 ;
+static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_RSV2_2 = 58 ;
+static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_RSV2_3 = 59 ;
+static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_RSV3_0 = 60 ;
+static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_RSV3_1 = 61 ;
+static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_RSV3_2 = 62 ;
+static const uint8_t P9N2_NV_CERR_MASK1_IDIAL_CTL_MASK_RSV3_3 = 63 ;
+
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_0 = 0 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_1 = 1 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_2 = 2 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_3 = 3 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_4 = 4 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_5 = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_6 = 6 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_7 = 7 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_8 = 8 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_9 = 9 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_10 = 10 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_11 = 11 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_12 = 12 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_13 = 13 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_14 = 14 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_15 = 15 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_16 = 16 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_17 = 17 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_18 = 18 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_19 = 19 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_20 = 20 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_21 = 21 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_22 = 22 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_23 = 23 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_24 = 24 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_25 = 25 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_26 = 26 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_27 = 27 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_28 = 28 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_29 = 29 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_30 = 30 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_31 = 31 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_32 = 32 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_33 = 33 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_34 = 34 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_35 = 35 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_36 = 36 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_37 = 37 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_38 = 38 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_39 = 39 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_40 = 40 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_41 = 41 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_42 = 42 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_43 = 43 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_44 = 44 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_45 = 45 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_46 = 46 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_47 = 47 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_48 = 48 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_49 = 49 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_50 = 50 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_51 = 51 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_52 = 52 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_53 = 53 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_54 = 54 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_55 = 55 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_56 = 56 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_57 = 57 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_58 = 58 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_59 = 59 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_60 = 60 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_61 = 61 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_62 = 62 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK1_NTL_63 = 63 ;
+
+static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_NLGX_0 = 0 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_NLGX_1 = 1 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_NLGX_2 = 2 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_NLGX_3 = 3 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_NLGX_4 = 4 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_NLGX_5 = 5 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_NLGX_6 = 6 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_NLGX_7 = 7 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_NLGX_8 = 8 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_NLGX_9 = 9 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_NLGX_10 = 10 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_NLGX_11 = 11 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_NLGX_12 = 12 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_NLGX_13 = 13 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_NLGX_14 = 14 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_NLGX_15 = 15 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_FWD_0 = 16 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_FWD_1 = 17 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_FWD_2 = 18 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_FWD_3 = 19 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_AUE_0 = 20 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_AUE_1 = 21 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_AUE_2 = 22 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_AUE_3 = 23 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_PBP_0 = 24 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_PBP_1 = 25 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_PBP_2 = 26 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_PBP_3 = 27 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_PBP_4 = 28 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_PBP_5 = 29 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_PBP_6 = 30 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_PBP_7 = 31 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_PBF_0 = 32 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_PBF_1 = 33 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_PBF_2 = 34 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_PBF_3 = 35 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_PBF_4 = 36 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_PBF_5 = 37 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_PBF_6 = 38 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_PBF_7 = 39 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_PBF_8 = 40 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_PBF_9 = 41 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_PBF_10 = 42 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_PBF_11 = 43 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_PBC_0 = 44 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_PBC_1 = 45 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_PBC_2 = 46 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_PBC_3 = 47 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_PBC_4 = 48 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_PBC_5 = 49 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_PBC_6 = 50 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_PBC_7 = 51 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_PBC_8 = 52 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_PBC_9 = 53 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_PBC_10 = 54 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK1_IDIAL_SM_MASK_PBC_11 = 55 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_0 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_1 = 1 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_2 = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_3 = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_4 = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_5 = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_6 = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_7 = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_8 = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_9 = 9 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_10 = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_11 = 11 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_12 = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_13 = 13 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_14 = 14 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_15 = 15 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_FWD_0 = 16 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_FWD_1 = 17 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_FWD_2 = 18 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_FWD_3 = 19 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_AUE_0 = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_AUE_1 = 21 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_AUE_2 = 22 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_AUE_3 = 23 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_0 = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_1 = 25 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_2 = 26 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_3 = 27 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_4 = 28 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_5 = 29 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_6 = 30 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_7 = 31 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_0 = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_1 = 33 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_2 = 34 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_3 = 35 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_4 = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_5 = 37 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_6 = 38 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_7 = 39 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_8 = 40 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_9 = 41 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_10 = 42 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_11 = 43 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_0 = 44 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_1 = 45 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_2 = 46 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_3 = 47 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_4 = 48 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_5 = 49 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_6 = 50 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_7 = 51 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_8 = 52 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_9 = 53 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_10 = 54 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_11 = 55 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_0 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_1 = 1 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_2 = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_3 = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_4 = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_5 = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_6 = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_7 = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_8 = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_9 = 9 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_10 = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_11 = 11 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_12 = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_13 = 13 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_14 = 14 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_15 = 15 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_16 = 16 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_17 = 17 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_18 = 18 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_19 = 19 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_20 = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_21 = 21 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_22 = 22 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_23 = 23 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_24 = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_25 = 25 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_26 = 26 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_27 = 27 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_28 = 28 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_29 = 29 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_30 = 30 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_31 = 31 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_32 = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_33 = 33 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_34 = 34 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_35 = 35 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_36 = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_37 = 37 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_38 = 38 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_39 = 39 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_40 = 40 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_41 = 41 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_42 = 42 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_43 = 43 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_44 = 44 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_45 = 45 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_46 = 46 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_47 = 47 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_48 = 48 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_49 = 49 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_50 = 50 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_51 = 51 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_52 = 52 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_53 = 53 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_54 = 54 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_55 = 55 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_56 = 56 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_57 = 57 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_58 = 58 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_59 = 59 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_60 = 60 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_61 = 61 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_62 = 62 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_63 = 63 ;
+
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_0 = 0 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_1 = 1 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_2 = 2 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_3 = 3 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_4 = 4 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_5 = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_6 = 6 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_7 = 7 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_8 = 8 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_9 = 9 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_10 = 10 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_11 = 11 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_12 = 12 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_13 = 13 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_14 = 14 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_15 = 15 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_16 = 16 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_17 = 17 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_18 = 18 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_19 = 19 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_20 = 20 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_21 = 21 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_22 = 22 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_23 = 23 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_24 = 24 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_25 = 25 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_26 = 26 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_27 = 27 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_28 = 28 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_29 = 29 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_30 = 30 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_31 = 31 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_32 = 32 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_33 = 33 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_34 = 34 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_35 = 35 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_36 = 36 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_37 = 37 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_38 = 38 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_39 = 39 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_40 = 40 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_41 = 41 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_42 = 42 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_43 = 43 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_44 = 44 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_45 = 45 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_46 = 46 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_47 = 47 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_48 = 48 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_49 = 49 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_50 = 50 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_51 = 51 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_52 = 52 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_53 = 53 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_54 = 54 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_55 = 55 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_56 = 56 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_57 = 57 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_58 = 58 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_59 = 59 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_60 = 60 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_61 = 61 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_62 = 62 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CERR_MASK2_NTL_63 = 63 ;
+
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_0 = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_1 = 1 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_2 = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_3 = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_4 = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_5 = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_6 = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_7 = 7 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_8 = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_9 = 9 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_10 = 10 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_11 = 11 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_12 = 12 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_13 = 13 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_14 = 14 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_15 = 15 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_16 = 16 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_17 = 17 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_18 = 18 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_19 = 19 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_20 = 20 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_21 = 21 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_22 = 22 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_23 = 23 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_24 = 24 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_25 = 25 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_26 = 26 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_27 = 27 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_28 = 28 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_29 = 29 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_30 = 30 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_31 = 31 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_32 = 32 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_33 = 33 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_34 = 34 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_35 = 35 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_36 = 36 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_37 = 37 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_38 = 38 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_39 = 39 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_40 = 40 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_41 = 41 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_42 = 42 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_43 = 43 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_44 = 44 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_45 = 45 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_46 = 46 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_47 = 47 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_48 = 48 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_49 = 49 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_50 = 50 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_51 = 51 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_52 = 52 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_53 = 53 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_54 = 54 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_55 = 55 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_56 = 56 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_57 = 57 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_58 = 58 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_59 = 59 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_60 = 60 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_61 = 61 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_62 = 62 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_63 = 63 ;
+
+static const uint8_t P9N2__SM1_CERR_MASK2_NTL_0 = 0 ;
+static const uint8_t P9N2__SM1_CERR_MASK2_NTL_1 = 1 ;
+static const uint8_t P9N2__SM1_CERR_MASK2_NTL_2 = 2 ;
+static const uint8_t P9N2__SM1_CERR_MASK2_NTL_3 = 3 ;
+static const uint8_t P9N2__SM1_CERR_MASK2_NTL_4 = 4 ;
+static const uint8_t P9N2__SM1_CERR_MASK2_NTL_5 = 5 ;
+static const uint8_t P9N2__SM1_CERR_MASK2_NTL_6 = 6 ;
+static const uint8_t P9N2__SM1_CERR_MASK2_NTL_7 = 7 ;
+static const uint8_t P9N2__SM1_CERR_MASK2_NTL_8 = 8 ;
+static const uint8_t P9N2__SM1_CERR_MASK2_NTL_9 = 9 ;
+static const uint8_t P9N2__SM1_CERR_MASK2_NTL_10 = 10 ;
+static const uint8_t P9N2__SM1_CERR_MASK2_NTL_11 = 11 ;
+static const uint8_t P9N2__SM1_CERR_MASK2_NTL_12 = 12 ;
+static const uint8_t P9N2__SM1_CERR_MASK2_NTL_13 = 13 ;
+static const uint8_t P9N2__SM1_CERR_MASK2_NTL_14 = 14 ;
+static const uint8_t P9N2__SM1_CERR_MASK2_NTL_15 = 15 ;
+static const uint8_t P9N2__SM1_CERR_MASK2_NTL_16 = 16 ;
+static const uint8_t P9N2__SM1_CERR_MASK2_NTL_17 = 17 ;
+static const uint8_t P9N2__SM1_CERR_MASK2_NTL_18 = 18 ;
+static const uint8_t P9N2__SM1_CERR_MASK2_NTL_19 = 19 ;
+static const uint8_t P9N2__SM1_CERR_MASK2_NTL_20 = 20 ;
+static const uint8_t P9N2__SM1_CERR_MASK2_NTL_21 = 21 ;
+static const uint8_t P9N2__SM1_CERR_MASK2_NTL_22 = 22 ;
+static const uint8_t P9N2__SM1_CERR_MASK2_NTL_23 = 23 ;
+static const uint8_t P9N2__SM1_CERR_MASK2_NTL_24 = 24 ;
+static const uint8_t P9N2__SM1_CERR_MASK2_NTL_25 = 25 ;
+static const uint8_t P9N2__SM1_CERR_MASK2_NTL_26 = 26 ;
+static const uint8_t P9N2__SM1_CERR_MASK2_NTL_27 = 27 ;
+static const uint8_t P9N2__SM1_CERR_MASK2_NTL_28 = 28 ;
+static const uint8_t P9N2__SM1_CERR_MASK2_NTL_29 = 29 ;
+static const uint8_t P9N2__SM1_CERR_MASK2_NTL_30 = 30 ;
+static const uint8_t P9N2__SM1_CERR_MASK2_NTL_31 = 31 ;
+static const uint8_t P9N2__SM1_CERR_MASK2_NTL_32 = 32 ;
+static const uint8_t P9N2__SM1_CERR_MASK2_NTL_33 = 33 ;
+static const uint8_t P9N2__SM1_CERR_MASK2_NTL_34 = 34 ;
+static const uint8_t P9N2__SM1_CERR_MASK2_NTL_35 = 35 ;
+static const uint8_t P9N2__SM1_CERR_MASK2_NTL_36 = 36 ;
+static const uint8_t P9N2__SM1_CERR_MASK2_NTL_37 = 37 ;
+static const uint8_t P9N2__SM1_CERR_MASK2_NTL_38 = 38 ;
+static const uint8_t P9N2__SM1_CERR_MASK2_NTL_39 = 39 ;
+static const uint8_t P9N2__SM1_CERR_MASK2_NTL_40 = 40 ;
+static const uint8_t P9N2__SM1_CERR_MASK2_NTL_41 = 41 ;
+static const uint8_t P9N2__SM1_CERR_MASK2_NTL_42 = 42 ;
+static const uint8_t P9N2__SM1_CERR_MASK2_NTL_43 = 43 ;
+static const uint8_t P9N2__SM1_CERR_MASK2_NTL_44 = 44 ;
+static const uint8_t P9N2__SM1_CERR_MASK2_NTL_45 = 45 ;
+static const uint8_t P9N2__SM1_CERR_MASK2_NTL_46 = 46 ;
+static const uint8_t P9N2__SM1_CERR_MASK2_NTL_47 = 47 ;
+static const uint8_t P9N2__SM1_CERR_MASK2_NTL_48 = 48 ;
+static const uint8_t P9N2__SM1_CERR_MASK2_NTL_49 = 49 ;
+static const uint8_t P9N2__SM1_CERR_MASK2_NTL_50 = 50 ;
+static const uint8_t P9N2__SM1_CERR_MASK2_NTL_51 = 51 ;
+static const uint8_t P9N2__SM1_CERR_MASK2_NTL_52 = 52 ;
+static const uint8_t P9N2__SM1_CERR_MASK2_NTL_53 = 53 ;
+static const uint8_t P9N2__SM1_CERR_MASK2_NTL_54 = 54 ;
+static const uint8_t P9N2__SM1_CERR_MASK2_NTL_55 = 55 ;
+static const uint8_t P9N2__SM1_CERR_MASK2_NTL_56 = 56 ;
+static const uint8_t P9N2__SM1_CERR_MASK2_NTL_57 = 57 ;
+static const uint8_t P9N2__SM1_CERR_MASK2_NTL_58 = 58 ;
+static const uint8_t P9N2__SM1_CERR_MASK2_NTL_59 = 59 ;
+static const uint8_t P9N2__SM1_CERR_MASK2_NTL_60 = 60 ;
+static const uint8_t P9N2__SM1_CERR_MASK2_NTL_61 = 61 ;
+static const uint8_t P9N2__SM1_CERR_MASK2_NTL_62 = 62 ;
+static const uint8_t P9N2__SM1_CERR_MASK2_NTL_63 = 63 ;
+
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_0 = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_1 = 1 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_2 = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_3 = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_4 = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_5 = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_6 = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_7 = 7 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_8 = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_9 = 9 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_10 = 10 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_11 = 11 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_12 = 12 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_13 = 13 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_14 = 14 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_15 = 15 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_16 = 16 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_17 = 17 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_18 = 18 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_19 = 19 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_20 = 20 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_21 = 21 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_22 = 22 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_23 = 23 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_24 = 24 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_25 = 25 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_26 = 26 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_27 = 27 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_28 = 28 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_29 = 29 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_30 = 30 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_31 = 31 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_32 = 32 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_33 = 33 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_34 = 34 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_35 = 35 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_36 = 36 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_37 = 37 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_38 = 38 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_39 = 39 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_40 = 40 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_41 = 41 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_42 = 42 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_43 = 43 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_44 = 44 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_45 = 45 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_46 = 46 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_47 = 47 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_48 = 48 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_49 = 49 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_50 = 50 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_51 = 51 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_52 = 52 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_53 = 53 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_54 = 54 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_55 = 55 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_56 = 56 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_57 = 57 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_58 = 58 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_59 = 59 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_60 = 60 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_61 = 61 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_62 = 62 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_63 = 63 ;
+
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_0 = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_1 = 1 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_2 = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_3 = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_4 = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_5 = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_6 = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_7 = 7 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_8 = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_9 = 9 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_10 = 10 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_11 = 11 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_12 = 12 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_13 = 13 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_14 = 14 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_15 = 15 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_16 = 16 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_17 = 17 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_18 = 18 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_19 = 19 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_20 = 20 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_21 = 21 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_22 = 22 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_23 = 23 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_24 = 24 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_25 = 25 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_26 = 26 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_27 = 27 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_28 = 28 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_29 = 29 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_30 = 30 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_31 = 31 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_32 = 32 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_33 = 33 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_34 = 34 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_35 = 35 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_36 = 36 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_37 = 37 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_38 = 38 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_39 = 39 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_40 = 40 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_41 = 41 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_42 = 42 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_43 = 43 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_44 = 44 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_45 = 45 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_46 = 46 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_47 = 47 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_48 = 48 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_49 = 49 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_50 = 50 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_51 = 51 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_52 = 52 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_53 = 53 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_54 = 54 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_55 = 55 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_56 = 56 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_57 = 57 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_58 = 58 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_59 = 59 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_60 = 60 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_61 = 61 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_62 = 62 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_63 = 63 ;
+
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_0 = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_1 = 1 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_2 = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_3 = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_4 = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_5 = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_6 = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_7 = 7 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_8 = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_9 = 9 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_10 = 10 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_11 = 11 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_12 = 12 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_13 = 13 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_14 = 14 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_15 = 15 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_16 = 16 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_17 = 17 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_18 = 18 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_19 = 19 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_20 = 20 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_21 = 21 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_22 = 22 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_23 = 23 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_24 = 24 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_25 = 25 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_26 = 26 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_27 = 27 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_28 = 28 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_29 = 29 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_30 = 30 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_31 = 31 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_32 = 32 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_33 = 33 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_34 = 34 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_35 = 35 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_36 = 36 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_37 = 37 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_38 = 38 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_39 = 39 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_40 = 40 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_41 = 41 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_42 = 42 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_43 = 43 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_44 = 44 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_45 = 45 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_46 = 46 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_47 = 47 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_48 = 48 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_49 = 49 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_50 = 50 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_51 = 51 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_52 = 52 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_53 = 53 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_54 = 54 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_55 = 55 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_56 = 56 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_57 = 57 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_58 = 58 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_59 = 59 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_60 = 60 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_61 = 61 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_62 = 62 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_63 = 63 ;
+
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_0 = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_1 = 1 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_2 = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_3 = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_4 = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_5 = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_6 = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_7 = 7 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_8 = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_9 = 9 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_10 = 10 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_11 = 11 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_12 = 12 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_13 = 13 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_14 = 14 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_15 = 15 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_16 = 16 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_17 = 17 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_18 = 18 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_19 = 19 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_20 = 20 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_21 = 21 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_22 = 22 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_23 = 23 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_24 = 24 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_25 = 25 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_26 = 26 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_27 = 27 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_28 = 28 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_29 = 29 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_30 = 30 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_31 = 31 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_32 = 32 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_33 = 33 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_34 = 34 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_35 = 35 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_36 = 36 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_37 = 37 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_38 = 38 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_39 = 39 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_40 = 40 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_41 = 41 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_42 = 42 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_43 = 43 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_44 = 44 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_45 = 45 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_46 = 46 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_47 = 47 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_48 = 48 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_49 = 49 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_50 = 50 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_51 = 51 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_52 = 52 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_53 = 53 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_54 = 54 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_55 = 55 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_56 = 56 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_57 = 57 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_58 = 58 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_59 = 59 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_60 = 60 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_61 = 61 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_62 = 62 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_63 = 63 ;
+
+static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_0 = 0 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_1 = 1 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_2 = 2 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_3 = 3 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_4 = 4 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_5 = 5 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_6 = 6 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_7 = 7 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_8 = 8 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_9 = 9 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_10 = 10 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_11 = 11 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_12 = 12 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_13 = 13 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_14 = 14 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_15 = 15 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_16 = 16 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_17 = 17 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_18 = 18 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_19 = 19 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_20 = 20 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_21 = 21 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_22 = 22 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_23 = 23 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_24 = 24 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_25 = 25 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_26 = 26 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_27 = 27 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_28 = 28 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_29 = 29 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_30 = 30 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_31 = 31 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_32 = 32 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_33 = 33 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_34 = 34 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_35 = 35 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_36 = 36 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_37 = 37 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_38 = 38 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_39 = 39 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_40 = 40 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_41 = 41 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_42 = 42 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_43 = 43 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_44 = 44 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_45 = 45 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_46 = 46 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_47 = 47 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_48 = 48 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_49 = 49 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_50 = 50 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_51 = 51 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_52 = 52 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_53 = 53 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_54 = 54 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_55 = 55 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_56 = 56 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_57 = 57 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_58 = 58 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_59 = 59 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_60 = 60 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_61 = 61 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_62 = 62 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MASK2_IDIAL_SM_MASK_NLG_63 = 63 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_0 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_1 = 1 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_2 = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_3 = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_4 = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_5 = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_6 = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_7 = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_8 = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_9 = 9 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_10 = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_11 = 11 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_12 = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_13 = 13 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_14 = 14 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_15 = 15 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_16 = 16 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_17 = 17 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_18 = 18 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_19 = 19 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_20 = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_21 = 21 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_22 = 22 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_23 = 23 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_24 = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_25 = 25 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_26 = 26 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_27 = 27 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_28 = 28 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_29 = 29 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_30 = 30 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_31 = 31 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_32 = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_33 = 33 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_34 = 34 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_35 = 35 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_36 = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_37 = 37 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_38 = 38 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_39 = 39 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_40 = 40 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_41 = 41 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_42 = 42 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_43 = 43 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_44 = 44 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_45 = 45 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_46 = 46 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_47 = 47 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_48 = 48 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_49 = 49 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_50 = 50 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_51 = 51 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_52 = 52 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_53 = 53 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_54 = 54 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_55 = 55 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_56 = 56 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_57 = 57 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_58 = 58 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_59 = 59 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_60 = 60 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_61 = 61 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_62 = 62 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_63 = 63 ;
+
+static const uint8_t P9N2__SM0_CERR_MASK2_NTL_0 = 0 ;
+static const uint8_t P9N2__SM0_CERR_MASK2_NTL_1 = 1 ;
+static const uint8_t P9N2__SM0_CERR_MASK2_NTL_2 = 2 ;
+static const uint8_t P9N2__SM0_CERR_MASK2_NTL_3 = 3 ;
+static const uint8_t P9N2__SM0_CERR_MASK2_NTL_4 = 4 ;
+static const uint8_t P9N2__SM0_CERR_MASK2_NTL_5 = 5 ;
+static const uint8_t P9N2__SM0_CERR_MASK2_NTL_6 = 6 ;
+static const uint8_t P9N2__SM0_CERR_MASK2_NTL_7 = 7 ;
+static const uint8_t P9N2__SM0_CERR_MASK2_NTL_8 = 8 ;
+static const uint8_t P9N2__SM0_CERR_MASK2_NTL_9 = 9 ;
+static const uint8_t P9N2__SM0_CERR_MASK2_NTL_10 = 10 ;
+static const uint8_t P9N2__SM0_CERR_MASK2_NTL_11 = 11 ;
+static const uint8_t P9N2__SM0_CERR_MASK2_NTL_12 = 12 ;
+static const uint8_t P9N2__SM0_CERR_MASK2_NTL_13 = 13 ;
+static const uint8_t P9N2__SM0_CERR_MASK2_NTL_14 = 14 ;
+static const uint8_t P9N2__SM0_CERR_MASK2_NTL_15 = 15 ;
+static const uint8_t P9N2__SM0_CERR_MASK2_NTL_16 = 16 ;
+static const uint8_t P9N2__SM0_CERR_MASK2_NTL_17 = 17 ;
+static const uint8_t P9N2__SM0_CERR_MASK2_NTL_18 = 18 ;
+static const uint8_t P9N2__SM0_CERR_MASK2_NTL_19 = 19 ;
+static const uint8_t P9N2__SM0_CERR_MASK2_NTL_20 = 20 ;
+static const uint8_t P9N2__SM0_CERR_MASK2_NTL_21 = 21 ;
+static const uint8_t P9N2__SM0_CERR_MASK2_NTL_22 = 22 ;
+static const uint8_t P9N2__SM0_CERR_MASK2_NTL_23 = 23 ;
+static const uint8_t P9N2__SM0_CERR_MASK2_NTL_24 = 24 ;
+static const uint8_t P9N2__SM0_CERR_MASK2_NTL_25 = 25 ;
+static const uint8_t P9N2__SM0_CERR_MASK2_NTL_26 = 26 ;
+static const uint8_t P9N2__SM0_CERR_MASK2_NTL_27 = 27 ;
+static const uint8_t P9N2__SM0_CERR_MASK2_NTL_28 = 28 ;
+static const uint8_t P9N2__SM0_CERR_MASK2_NTL_29 = 29 ;
+static const uint8_t P9N2__SM0_CERR_MASK2_NTL_30 = 30 ;
+static const uint8_t P9N2__SM0_CERR_MASK2_NTL_31 = 31 ;
+static const uint8_t P9N2__SM0_CERR_MASK2_NTL_32 = 32 ;
+static const uint8_t P9N2__SM0_CERR_MASK2_NTL_33 = 33 ;
+static const uint8_t P9N2__SM0_CERR_MASK2_NTL_34 = 34 ;
+static const uint8_t P9N2__SM0_CERR_MASK2_NTL_35 = 35 ;
+static const uint8_t P9N2__SM0_CERR_MASK2_NTL_36 = 36 ;
+static const uint8_t P9N2__SM0_CERR_MASK2_NTL_37 = 37 ;
+static const uint8_t P9N2__SM0_CERR_MASK2_NTL_38 = 38 ;
+static const uint8_t P9N2__SM0_CERR_MASK2_NTL_39 = 39 ;
+static const uint8_t P9N2__SM0_CERR_MASK2_NTL_40 = 40 ;
+static const uint8_t P9N2__SM0_CERR_MASK2_NTL_41 = 41 ;
+static const uint8_t P9N2__SM0_CERR_MASK2_NTL_42 = 42 ;
+static const uint8_t P9N2__SM0_CERR_MASK2_NTL_43 = 43 ;
+static const uint8_t P9N2__SM0_CERR_MASK2_NTL_44 = 44 ;
+static const uint8_t P9N2__SM0_CERR_MASK2_NTL_45 = 45 ;
+static const uint8_t P9N2__SM0_CERR_MASK2_NTL_46 = 46 ;
+static const uint8_t P9N2__SM0_CERR_MASK2_NTL_47 = 47 ;
+static const uint8_t P9N2__SM0_CERR_MASK2_NTL_48 = 48 ;
+static const uint8_t P9N2__SM0_CERR_MASK2_NTL_49 = 49 ;
+static const uint8_t P9N2__SM0_CERR_MASK2_NTL_50 = 50 ;
+static const uint8_t P9N2__SM0_CERR_MASK2_NTL_51 = 51 ;
+static const uint8_t P9N2__SM0_CERR_MASK2_NTL_52 = 52 ;
+static const uint8_t P9N2__SM0_CERR_MASK2_NTL_53 = 53 ;
+static const uint8_t P9N2__SM0_CERR_MASK2_NTL_54 = 54 ;
+static const uint8_t P9N2__SM0_CERR_MASK2_NTL_55 = 55 ;
+static const uint8_t P9N2__SM0_CERR_MASK2_NTL_56 = 56 ;
+static const uint8_t P9N2__SM0_CERR_MASK2_NTL_57 = 57 ;
+static const uint8_t P9N2__SM0_CERR_MASK2_NTL_58 = 58 ;
+static const uint8_t P9N2__SM0_CERR_MASK2_NTL_59 = 59 ;
+static const uint8_t P9N2__SM0_CERR_MASK2_NTL_60 = 60 ;
+static const uint8_t P9N2__SM0_CERR_MASK2_NTL_61 = 61 ;
+static const uint8_t P9N2__SM0_CERR_MASK2_NTL_62 = 62 ;
+static const uint8_t P9N2__SM0_CERR_MASK2_NTL_63 = 63 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_0 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_1 = 1 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_2 = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_3 = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_4 = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_5 = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_6 = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_7 = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_8 = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_9 = 9 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_10 = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_11 = 11 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_12 = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_13 = 13 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_14 = 14 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_15 = 15 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_16 = 16 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_17 = 17 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_18 = 18 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_19 = 19 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_20 = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_21 = 21 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_22 = 22 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_23 = 23 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_24 = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_25 = 25 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_26 = 26 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_27 = 27 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_28 = 28 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_29 = 29 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_30 = 30 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_31 = 31 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_32 = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_33 = 33 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_34 = 34 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_35 = 35 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_36 = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_37 = 37 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_38 = 38 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_39 = 39 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_40 = 40 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_41 = 41 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_42 = 42 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_43 = 43 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_44 = 44 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_45 = 45 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_46 = 46 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_47 = 47 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_48 = 48 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_49 = 49 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_50 = 50 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_51 = 51 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_52 = 52 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_53 = 53 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_54 = 54 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_55 = 55 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_56 = 56 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_57 = 57 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_58 = 58 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_59 = 59 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_60 = 60 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_61 = 61 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_62 = 62 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MASK2_IDIAL_SM_MASK_NLG_63 = 63 ;
+
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_0 = 0 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_1 = 1 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_2 = 2 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_3 = 3 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_4 = 4 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_5 = 5 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_6 = 6 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_7 = 7 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_8 = 8 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_9 = 9 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_10 = 10 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_11 = 11 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_12 = 12 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_13 = 13 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_14 = 14 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_15 = 15 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_16 = 16 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_17 = 17 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_18 = 18 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_19 = 19 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_20 = 20 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_21 = 21 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_22 = 22 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_23 = 23 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_24 = 24 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_25 = 25 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_26 = 26 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_27 = 27 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_28 = 28 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_29 = 29 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_30 = 30 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_31 = 31 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_32 = 32 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_33 = 33 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_34 = 34 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_35 = 35 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_36 = 36 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_37 = 37 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_38 = 38 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_39 = 39 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_40 = 40 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_41 = 41 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_42 = 42 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_43 = 43 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_44 = 44 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_45 = 45 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_46 = 46 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_47 = 47 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_48 = 48 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_49 = 49 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_50 = 50 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_51 = 51 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_52 = 52 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_53 = 53 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_54 = 54 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_55 = 55 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_56 = 56 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_57 = 57 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_58 = 58 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_59 = 59 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_60 = 60 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_61 = 61 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_62 = 62 ;
+static const uint8_t P9N2_PU_NPU_SM0_CERR_MASK2_NTL_63 = 63 ;
+
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_0 = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_1 = 1 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_2 = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_3 = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_4 = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_5 = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_6 = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_7 = 7 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_8 = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_9 = 9 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_10 = 10 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_11 = 11 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_12 = 12 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_13 = 13 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_14 = 14 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_15 = 15 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_16 = 16 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_17 = 17 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_18 = 18 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_19 = 19 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_20 = 20 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_21 = 21 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_22 = 22 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_23 = 23 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_24 = 24 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_25 = 25 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_26 = 26 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_27 = 27 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_28 = 28 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_29 = 29 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_30 = 30 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_31 = 31 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_32 = 32 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_33 = 33 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_34 = 34 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_35 = 35 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_36 = 36 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_37 = 37 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_38 = 38 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_39 = 39 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_40 = 40 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_41 = 41 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_42 = 42 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_43 = 43 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_44 = 44 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_45 = 45 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_46 = 46 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_47 = 47 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_48 = 48 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_49 = 49 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_50 = 50 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_51 = 51 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_52 = 52 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_53 = 53 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_54 = 54 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_55 = 55 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_56 = 56 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_57 = 57 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_58 = 58 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_59 = 59 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_60 = 60 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_61 = 61 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_62 = 62 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_63 = 63 ;
+
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_0 = 0 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_1 = 1 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_2 = 2 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_3 = 3 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_4 = 4 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_5 = 5 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_6 = 6 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_7 = 7 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_8 = 8 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_9 = 9 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_10 = 10 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_11 = 11 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_12 = 12 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_13 = 13 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_14 = 14 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_15 = 15 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_16 = 16 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_17 = 17 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_18 = 18 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_19 = 19 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_20 = 20 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_21 = 21 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_22 = 22 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_23 = 23 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_24 = 24 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_25 = 25 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_26 = 26 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_27 = 27 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_28 = 28 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_29 = 29 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_30 = 30 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_31 = 31 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_32 = 32 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_33 = 33 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_34 = 34 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_35 = 35 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_36 = 36 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_37 = 37 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_38 = 38 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_39 = 39 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_40 = 40 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_41 = 41 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_42 = 42 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_43 = 43 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_44 = 44 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_45 = 45 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_46 = 46 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_47 = 47 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_48 = 48 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_49 = 49 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_50 = 50 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_51 = 51 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_52 = 52 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_53 = 53 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_54 = 54 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_55 = 55 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_56 = 56 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_57 = 57 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_58 = 58 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_59 = 59 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_60 = 60 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_61 = 61 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_62 = 62 ;
+static const uint8_t P9N2_PU_NPU_SM1_CERR_MASK2_NTL_63 = 63 ;
+
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_0 = 0 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_1 = 1 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_2 = 2 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_3 = 3 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_4 = 4 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_5 = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_6 = 6 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_7 = 7 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_8 = 8 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_9 = 9 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_10 = 10 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_11 = 11 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_12 = 12 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_13 = 13 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_14 = 14 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_15 = 15 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_16 = 16 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_17 = 17 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_18 = 18 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_19 = 19 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_20 = 20 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_21 = 21 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_22 = 22 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_23 = 23 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_24 = 24 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_25 = 25 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_26 = 26 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_27 = 27 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_28 = 28 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_29 = 29 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_30 = 30 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_31 = 31 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_32 = 32 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_33 = 33 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_34 = 34 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_35 = 35 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_36 = 36 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_37 = 37 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_38 = 38 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_39 = 39 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_40 = 40 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_41 = 41 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_42 = 42 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_43 = 43 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_44 = 44 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_45 = 45 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_46 = 46 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_47 = 47 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_48 = 48 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_49 = 49 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_50 = 50 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_51 = 51 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_52 = 52 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_53 = 53 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_54 = 54 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_55 = 55 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_56 = 56 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_57 = 57 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_58 = 58 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_59 = 59 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_60 = 60 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_61 = 61 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_62 = 62 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CERR_MASK2_NTL_63 = 63 ;
+
+static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_0 = 0 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_1 = 1 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_2 = 2 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_3 = 3 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_4 = 4 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_5 = 5 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_6 = 6 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_7 = 7 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_8 = 8 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_9 = 9 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_10 = 10 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_11 = 11 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_12 = 12 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_13 = 13 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_14 = 14 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_15 = 15 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_16 = 16 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_17 = 17 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_18 = 18 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_19 = 19 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_20 = 20 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_21 = 21 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_22 = 22 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_23 = 23 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_24 = 24 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_25 = 25 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_26 = 26 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_27 = 27 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_28 = 28 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_29 = 29 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_30 = 30 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_31 = 31 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_32 = 32 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_33 = 33 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_34 = 34 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_35 = 35 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_36 = 36 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_37 = 37 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_38 = 38 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_39 = 39 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_40 = 40 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_41 = 41 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_42 = 42 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_43 = 43 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_44 = 44 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_45 = 45 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_46 = 46 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_47 = 47 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_48 = 48 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_49 = 49 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_50 = 50 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_51 = 51 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_52 = 52 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_53 = 53 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_54 = 54 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_55 = 55 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_56 = 56 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_57 = 57 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_58 = 58 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_59 = 59 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_60 = 60 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_61 = 61 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_62 = 62 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MASK2_IDIAL_SM_MASK_NLG_63 = 63 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_0 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_1 = 1 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_2 = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_3 = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_4 = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_5 = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_6 = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_7 = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_8 = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_9 = 9 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_10 = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_11 = 11 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_12 = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_13 = 13 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_14 = 14 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_15 = 15 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_16 = 16 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_17 = 17 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_18 = 18 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_19 = 19 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_20 = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_21 = 21 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_22 = 22 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_23 = 23 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_24 = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_25 = 25 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_26 = 26 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_27 = 27 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_28 = 28 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_29 = 29 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_30 = 30 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_31 = 31 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_32 = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_33 = 33 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_34 = 34 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_35 = 35 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_36 = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_37 = 37 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_38 = 38 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_39 = 39 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_40 = 40 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_41 = 41 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_42 = 42 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_43 = 43 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_44 = 44 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_45 = 45 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_46 = 46 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_47 = 47 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_48 = 48 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_49 = 49 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_50 = 50 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_51 = 51 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_52 = 52 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_53 = 53 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_54 = 54 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_55 = 55 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_56 = 56 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_57 = 57 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_58 = 58 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_59 = 59 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_60 = 60 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_61 = 61 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_62 = 62 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_63 = 63 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MESSAGE0_MESSAGE_BITS0 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MESSAGE0_MESSAGE_BITS0_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MESSAGE0_MESSAGE_BITS0 = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MESSAGE0_MESSAGE_BITS0_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MESSAGE0_MESSAGE_BITS0 = 0 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MESSAGE0_MESSAGE_BITS0_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MESSAGE0_MESSAGE_BITS0 = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MESSAGE0_MESSAGE_BITS0_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MESSAGE0_MESSAGE_BITS0 = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MESSAGE0_MESSAGE_BITS0_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MESSAGE0_MESSAGE_BITS0 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MESSAGE0_MESSAGE_BITS0_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU0_CERR_MESSAGE0_MESSAGE_BITS0 = 0 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MESSAGE0_MESSAGE_BITS0_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MESSAGE0_MESSAGE_BITS0 = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MESSAGE0_MESSAGE_BITS0_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MESSAGE0_MESSAGE_BITS0 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MESSAGE0_MESSAGE_BITS0_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MESSAGE0_MESSAGE_BITS0 = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MESSAGE0_MESSAGE_BITS0_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MESSAGE0_MESSAGE_BITS0 = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MESSAGE0_MESSAGE_BITS0_LEN = 64 ;
+
+static const uint8_t P9N2_NV_CERR_MESSAGE0_MESSAGE_BITS0 = 0 ;
+static const uint8_t P9N2_NV_CERR_MESSAGE0_MESSAGE_BITS0_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU2_CERR_MESSAGE0_MESSAGE_BITS0 = 0 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MESSAGE0_MESSAGE_BITS0_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MESSAGE0_MESSAGE_BITS0 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MESSAGE0_MESSAGE_BITS0_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MESSAGE1_MESSAGE_BITS1 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MESSAGE1_MESSAGE_BITS1_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MESSAGE1_MESSAGE_BITS1 = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MESSAGE1_MESSAGE_BITS1_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MESSAGE1_MESSAGE_BITS1 = 0 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CERR_MESSAGE1_MESSAGE_BITS1_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MESSAGE1_MESSAGE_BITS1 = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MESSAGE1_MESSAGE_BITS1_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MESSAGE1_MESSAGE_BITS1 = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MESSAGE1_MESSAGE_BITS1_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MESSAGE1_MESSAGE_BITS1 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MESSAGE1_MESSAGE_BITS1_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU0_CERR_MESSAGE1_MESSAGE_BITS1 = 0 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MESSAGE1_MESSAGE_BITS1_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MESSAGE1_MESSAGE_BITS1 = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MESSAGE1_MESSAGE_BITS1_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MESSAGE1_MESSAGE_BITS1 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MESSAGE1_MESSAGE_BITS1_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MESSAGE1_MESSAGE_BITS1 = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MESSAGE1_MESSAGE_BITS1_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MESSAGE1_MESSAGE_BITS1 = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MESSAGE1_MESSAGE_BITS1_LEN = 64 ;
+
+static const uint8_t P9N2_NV_CERR_MESSAGE1_MESSAGE_BITS1 = 0 ;
+static const uint8_t P9N2_NV_CERR_MESSAGE1_MESSAGE_BITS1_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU2_CERR_MESSAGE1_MESSAGE_BITS1 = 0 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MESSAGE1_MESSAGE_BITS1_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MESSAGE1_MESSAGE_BITS1 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MESSAGE1_MESSAGE_BITS1_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MESSAGE2_MESSAGE_BITS2 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MESSAGE2_MESSAGE_BITS2_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MESSAGE2_MESSAGE_BITS2 = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MESSAGE2_MESSAGE_BITS2_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MESSAGE2_MESSAGE_BITS2 = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MESSAGE2_MESSAGE_BITS2_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MESSAGE2_MESSAGE_BITS2 = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MESSAGE2_MESSAGE_BITS2_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MESSAGE2_MESSAGE_BITS2 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MESSAGE2_MESSAGE_BITS2_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU0_CERR_MESSAGE2_MESSAGE_BITS2 = 0 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MESSAGE2_MESSAGE_BITS2_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MESSAGE2_MESSAGE_BITS2 = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MESSAGE2_MESSAGE_BITS2_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MESSAGE2_MESSAGE_BITS2 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MESSAGE2_MESSAGE_BITS2_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MESSAGE2_MESSAGE_BITS2 = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MESSAGE2_MESSAGE_BITS2_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MESSAGE2_MESSAGE_BITS2 = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MESSAGE2_MESSAGE_BITS2_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU2_CERR_MESSAGE2_MESSAGE_BITS2 = 0 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MESSAGE2_MESSAGE_BITS2_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MESSAGE2_MESSAGE_BITS2 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MESSAGE2_MESSAGE_BITS2_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MESSAGE3_MESSAGE_BITS3 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MESSAGE3_MESSAGE_BITS3_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MESSAGE3_MESSAGE_BITS3 = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MESSAGE3_MESSAGE_BITS3_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MESSAGE3_MESSAGE_BITS3 = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MESSAGE3_MESSAGE_BITS3_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MESSAGE3_MESSAGE_BITS3 = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MESSAGE3_MESSAGE_BITS3_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MESSAGE3_MESSAGE_BITS3 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MESSAGE3_MESSAGE_BITS3_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU0_CERR_MESSAGE3_MESSAGE_BITS3 = 0 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MESSAGE3_MESSAGE_BITS3_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MESSAGE3_MESSAGE_BITS3 = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MESSAGE3_MESSAGE_BITS3_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MESSAGE3_MESSAGE_BITS3 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MESSAGE3_MESSAGE_BITS3_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MESSAGE3_MESSAGE_BITS3 = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MESSAGE3_MESSAGE_BITS3_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MESSAGE3_MESSAGE_BITS3 = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MESSAGE3_MESSAGE_BITS3_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU2_CERR_MESSAGE3_MESSAGE_BITS3 = 0 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MESSAGE3_MESSAGE_BITS3_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MESSAGE3_MESSAGE_BITS3 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MESSAGE3_MESSAGE_BITS3_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MESSAGE4_MESSAGE_BITS4 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MESSAGE4_MESSAGE_BITS4_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MESSAGE4_MESSAGE_BITS4 = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CERR_MESSAGE4_MESSAGE_BITS4_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MESSAGE4_MESSAGE_BITS4 = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CERR_MESSAGE4_MESSAGE_BITS4_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MESSAGE4_MESSAGE_BITS4 = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CERR_MESSAGE4_MESSAGE_BITS4_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MESSAGE4_MESSAGE_BITS4 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CERR_MESSAGE4_MESSAGE_BITS4_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU0_CERR_MESSAGE4_MESSAGE_BITS4 = 0 ;
+static const uint8_t P9N2_PU_NPU0_CERR_MESSAGE4_MESSAGE_BITS4_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MESSAGE4_MESSAGE_BITS4 = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MESSAGE4_MESSAGE_BITS4_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MESSAGE4_MESSAGE_BITS4 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_CERR_MESSAGE4_MESSAGE_BITS4_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MESSAGE4_MESSAGE_BITS4 = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MESSAGE4_MESSAGE_BITS4_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MESSAGE4_MESSAGE_BITS4 = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CERR_MESSAGE4_MESSAGE_BITS4_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU2_CERR_MESSAGE4_MESSAGE_BITS4 = 0 ;
+static const uint8_t P9N2_PU_NPU2_CERR_MESSAGE4_MESSAGE_BITS4_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MESSAGE4_MESSAGE_BITS4 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CERR_MESSAGE4_MESSAGE_BITS4_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MESSAGE5_MESSAGE_BITS5 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MESSAGE5_MESSAGE_BITS5_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_DAT_CERR_MESSAGE5_MESSAGE_BITS5 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_CERR_MESSAGE5_MESSAGE_BITS5_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MESSAGE5_MESSAGE_BITS5 = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MESSAGE5_MESSAGE_BITS5_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CERR_MESSAGE5_MESSAGE_BITS5 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CERR_MESSAGE5_MESSAGE_BITS5_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MESSAGE5_MESSAGE_BITS5 = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MESSAGE5_MESSAGE_BITS5_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU2_SM1_CERR_MESSAGE5_MESSAGE_BITS5 = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CERR_MESSAGE5_MESSAGE_BITS5_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU0_CTL_CERR_MESSAGE5_MESSAGE_BITS5 = 0 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CERR_MESSAGE5_MESSAGE_BITS5_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU2_CTL_CERR_MESSAGE5_MESSAGE_BITS5 = 0 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CERR_MESSAGE5_MESSAGE_BITS5_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU0_SM1_CERR_MESSAGE5_MESSAGE_BITS5 = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CERR_MESSAGE5_MESSAGE_BITS5_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU2_DAT_CERR_MESSAGE5_MESSAGE_BITS5 = 0 ;
+static const uint8_t P9N2_PU_NPU2_DAT_CERR_MESSAGE5_MESSAGE_BITS5_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CERR_MESSAGE5_MESSAGE_BITS5 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CERR_MESSAGE5_MESSAGE_BITS5_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU0_DAT_CERR_MESSAGE5_MESSAGE_BITS5 = 0 ;
+static const uint8_t P9N2_PU_NPU0_DAT_CERR_MESSAGE5_MESSAGE_BITS5_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MESSAGE6_MESSAGE_BITS6 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CERR_MESSAGE6_MESSAGE_BITS6_LEN = 24 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_DAT_CERR_MESSAGE6_MESSAGE_BITS6 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_CERR_MESSAGE6_MESSAGE_BITS6_LEN = 24 ;
+
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MESSAGE6_MESSAGE_BITS6 = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CERR_MESSAGE6_MESSAGE_BITS6_LEN = 24 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CERR_MESSAGE6_MESSAGE_BITS6 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CERR_MESSAGE6_MESSAGE_BITS6_LEN = 24 ;
+
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MESSAGE6_MESSAGE_BITS6 = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CERR_MESSAGE6_MESSAGE_BITS6_LEN = 24 ;
+
+static const uint8_t P9N2_PU_NPU2_SM1_CERR_MESSAGE6_MESSAGE_BITS6 = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CERR_MESSAGE6_MESSAGE_BITS6_LEN = 24 ;
+
+static const uint8_t P9N2_PU_NPU0_CTL_CERR_MESSAGE6_MESSAGE_BITS6 = 0 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CERR_MESSAGE6_MESSAGE_BITS6_LEN = 24 ;
+
+static const uint8_t P9N2_PU_NPU2_CTL_CERR_MESSAGE6_MESSAGE_BITS6 = 0 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CERR_MESSAGE6_MESSAGE_BITS6_LEN = 24 ;
+
+static const uint8_t P9N2_PU_NPU0_SM1_CERR_MESSAGE6_MESSAGE_BITS6 = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CERR_MESSAGE6_MESSAGE_BITS6_LEN = 24 ;
+
+static const uint8_t P9N2_PU_NPU2_DAT_CERR_MESSAGE6_MESSAGE_BITS6 = 0 ;
+static const uint8_t P9N2_PU_NPU2_DAT_CERR_MESSAGE6_MESSAGE_BITS6_LEN = 24 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CERR_MESSAGE6_MESSAGE_BITS6 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CERR_MESSAGE6_MESSAGE_BITS6_LEN = 24 ;
+
+static const uint8_t P9N2_PU_NPU0_DAT_CERR_MESSAGE6_MESSAGE_BITS6 = 0 ;
+static const uint8_t P9N2_PU_NPU0_DAT_CERR_MESSAGE6_MESSAGE_BITS6_LEN = 24 ;
+
+static const uint8_t P9N2_PU_NPU2_NTL1_CERR_PTY_FIRST_BITS = 37 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CERR_PTY_FIRST_BITS_LEN = 27 ;
+
+static const uint8_t P9N2_PU_NPU2_NTL1_CERR_PTY_HOLD_IDIAL_INHIBIT_CONFIG = 37 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CERR_PTY_HOLD_IDIAL_MISC_STATE = 38 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CERR_PTY_HOLD_IDIAL_MRG_STATE = 39 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CERR_PTY_HOLD_IDIAL_OBUF_STATE = 40 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CERR_PTY_HOLD_IDIAL_PBTX_STATE = 41 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CERR_PTY_HOLD_IDIAL_RQIN_STATE = 42 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CERR_PTY_HOLD_IDIAL_IBUF_STATE = 43 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CERR_PTY_HOLD_IDIAL_ERRINJ = 44 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CERR_PTY_HOLD_IDIAL_PBTX_AMO = 45 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CERR_PTY_HOLD_IDIAL_PBTX_AMO_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CERR_PTY_HOLD_IDIAL_IBRD = 49 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CERR_PTY_HOLD_IDIAL_IBRD_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CERR_PTY_HOLD_IDIAL_OBRD = 53 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CERR_PTY_HOLD_IDIAL_OBRD_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CERR_PTY_HOLD_IDIAL_BBRD = 57 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CERR_PTY_HOLD_IDIAL_BBRD_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CERR_PTY_HOLD_IDIAL_PBRX_RTAG = 59 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CERR_PTY_HOLD_IDIAL_ECC_CONFIG = 60 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CERR_PTY_HOLD_IDIAL_CONFIG1 = 61 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CERR_PTY_HOLD_IDIAL_DEBUG0_CONFIG = 62 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CERR_PTY_HOLD_IDIAL_DEBUG1_CONFIG = 63 ;
+
+static const uint8_t P9N2_PU_NPU2_NTL1_CERR_PTY_MASK_BITS = 37 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CERR_PTY_MASK_BITS_LEN = 27 ;
+
+static const uint8_t P9N2_PU_NPU_CTL_CHKSW0_CONFIG_INHIBIT_EN = 0 ;
+static const uint8_t P9N2_PU_NPU_CTL_CHKSW0_CONFIG_INHIBIT_PACE_ENABLE_CMD = 1 ;
+static const uint8_t P9N2_PU_NPU_CTL_CHKSW0_CONFIG_INHIBIT_PACE_ENABLE_CMD_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_CTL_CHKSW0_CONFIG_INHIBIT_PACE_DISABLE_CMD = 4 ;
+static const uint8_t P9N2_PU_NPU_CTL_CHKSW0_CONFIG_INHIBIT_PACE_DISABLE_CMD_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_CTL_CHKSW0_CONFIG_INHIBIT_PACE_ENABLE_RESP = 7 ;
+static const uint8_t P9N2_PU_NPU_CTL_CHKSW0_CONFIG_INHIBIT_PACE_ENABLE_RESP_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_CTL_CHKSW0_CONFIG_INHIBIT_PACE_DISABLE_RESP = 10 ;
+static const uint8_t P9N2_PU_NPU_CTL_CHKSW0_CONFIG_INHIBIT_PACE_DISABLE_RESP_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_CTL_CHKSW0_CONFIG_OTL_RXO_SNGLTHRD_XSL_OPS = 13 ;
+static const uint8_t P9N2_PU_NPU_CTL_CHKSW0_CONFIG_OTL_RXO_DIS_EARLY_READ = 14 ;
+static const uint8_t P9N2_PU_NPU_CTL_CHKSW0_CONFIG_OTL_CHKSW00 = 15 ;
+static const uint8_t P9N2_PU_NPU_CTL_CHKSW0_CONFIG_OTL_CHKSW00_LEN = 17 ;
+static const uint8_t P9N2_PU_NPU_CTL_CHKSW0_CONFIG_OTL_CHKSW01 = 32 ;
+static const uint8_t P9N2_PU_NPU_CTL_CHKSW0_CONFIG_OTL_CHKSW01_LEN = 32 ;
+
+static const uint8_t P9N2_PU_NPU_SM2_CHKSW0_CONFIG_INHIBIT_EN = 0 ;
+static const uint8_t P9N2_PU_NPU_SM2_CHKSW0_CONFIG_INHIBIT_PACE_ENABLE_CMD = 1 ;
+static const uint8_t P9N2_PU_NPU_SM2_CHKSW0_CONFIG_INHIBIT_PACE_ENABLE_CMD_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_SM2_CHKSW0_CONFIG_INHIBIT_PACE_DISABLE_CMD = 4 ;
+static const uint8_t P9N2_PU_NPU_SM2_CHKSW0_CONFIG_INHIBIT_PACE_DISABLE_CMD_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_SM2_CHKSW0_CONFIG_INHIBIT_PACE_ENABLE_RESP = 7 ;
+static const uint8_t P9N2_PU_NPU_SM2_CHKSW0_CONFIG_INHIBIT_PACE_ENABLE_RESP_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_SM2_CHKSW0_CONFIG_INHIBIT_PACE_DISABLE_RESP = 10 ;
+static const uint8_t P9N2_PU_NPU_SM2_CHKSW0_CONFIG_INHIBIT_PACE_DISABLE_RESP_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_SM2_CHKSW0_CONFIG_OTL_RXO_SNGLTHRD_XSL_OPS = 13 ;
+static const uint8_t P9N2_PU_NPU_SM2_CHKSW0_CONFIG_OTL_RXO_DIS_EARLY_READ = 14 ;
+static const uint8_t P9N2_PU_NPU_SM2_CHKSW0_CONFIG_OTL_CHKSW00 = 15 ;
+static const uint8_t P9N2_PU_NPU_SM2_CHKSW0_CONFIG_OTL_CHKSW00_LEN = 17 ;
+static const uint8_t P9N2_PU_NPU_SM2_CHKSW0_CONFIG_OTL_CHKSW01 = 32 ;
+static const uint8_t P9N2_PU_NPU_SM2_CHKSW0_CONFIG_OTL_CHKSW01_LEN = 32 ;
+
+static const uint8_t P9N2__CTL_CHKSW0_CONFIG_INHIBIT_EN = 0 ;
+static const uint8_t P9N2__CTL_CHKSW0_CONFIG_INHIBIT_PACE_ENABLE_CMD = 1 ;
+static const uint8_t P9N2__CTL_CHKSW0_CONFIG_INHIBIT_PACE_ENABLE_CMD_LEN = 3 ;
+static const uint8_t P9N2__CTL_CHKSW0_CONFIG_INHIBIT_PACE_DISABLE_CMD = 4 ;
+static const uint8_t P9N2__CTL_CHKSW0_CONFIG_INHIBIT_PACE_DISABLE_CMD_LEN = 3 ;
+static const uint8_t P9N2__CTL_CHKSW0_CONFIG_INHIBIT_PACE_ENABLE_RESP = 7 ;
+static const uint8_t P9N2__CTL_CHKSW0_CONFIG_INHIBIT_PACE_ENABLE_RESP_LEN = 3 ;
+static const uint8_t P9N2__CTL_CHKSW0_CONFIG_INHIBIT_PACE_DISABLE_RESP = 10 ;
+static const uint8_t P9N2__CTL_CHKSW0_CONFIG_INHIBIT_PACE_DISABLE_RESP_LEN = 3 ;
+static const uint8_t P9N2__CTL_CHKSW0_CONFIG_OTL_RXO_SNGLTHRD_XSL_OPS = 13 ;
+static const uint8_t P9N2__CTL_CHKSW0_CONFIG_OTL_RXO_DIS_EARLY_READ = 14 ;
+static const uint8_t P9N2__CTL_CHKSW0_CONFIG_OTL_CHKSW00 = 15 ;
+static const uint8_t P9N2__CTL_CHKSW0_CONFIG_OTL_CHKSW00_LEN = 17 ;
+static const uint8_t P9N2__CTL_CHKSW0_CONFIG_OTL_CHKSW01 = 32 ;
+static const uint8_t P9N2__CTL_CHKSW0_CONFIG_OTL_CHKSW01_LEN = 32 ;
+
+static const uint8_t P9N2__SM2_CHKSW0_CONFIG_INHIBIT_EN = 0 ;
+static const uint8_t P9N2__SM2_CHKSW0_CONFIG_INHIBIT_PACE_ENABLE_CMD = 1 ;
+static const uint8_t P9N2__SM2_CHKSW0_CONFIG_INHIBIT_PACE_ENABLE_CMD_LEN = 3 ;
+static const uint8_t P9N2__SM2_CHKSW0_CONFIG_INHIBIT_PACE_DISABLE_CMD = 4 ;
+static const uint8_t P9N2__SM2_CHKSW0_CONFIG_INHIBIT_PACE_DISABLE_CMD_LEN = 3 ;
+static const uint8_t P9N2__SM2_CHKSW0_CONFIG_INHIBIT_PACE_ENABLE_RESP = 7 ;
+static const uint8_t P9N2__SM2_CHKSW0_CONFIG_INHIBIT_PACE_ENABLE_RESP_LEN = 3 ;
+static const uint8_t P9N2__SM2_CHKSW0_CONFIG_INHIBIT_PACE_DISABLE_RESP = 10 ;
+static const uint8_t P9N2__SM2_CHKSW0_CONFIG_INHIBIT_PACE_DISABLE_RESP_LEN = 3 ;
+static const uint8_t P9N2__SM2_CHKSW0_CONFIG_OTL_RXO_SNGLTHRD_XSL_OPS = 13 ;
+static const uint8_t P9N2__SM2_CHKSW0_CONFIG_OTL_RXO_DIS_EARLY_READ = 14 ;
+static const uint8_t P9N2__SM2_CHKSW0_CONFIG_OTL_CHKSW00 = 15 ;
+static const uint8_t P9N2__SM2_CHKSW0_CONFIG_OTL_CHKSW00_LEN = 17 ;
+static const uint8_t P9N2__SM2_CHKSW0_CONFIG_OTL_CHKSW01 = 32 ;
+static const uint8_t P9N2__SM2_CHKSW0_CONFIG_OTL_CHKSW01_LEN = 32 ;
+
+static const uint8_t P9N2_PEC_CLK_REGION_CLOCK_CMD = 0 ;
+static const uint8_t P9N2_PEC_CLK_REGION_CLOCK_CMD_LEN = 2 ;
+static const uint8_t P9N2_PEC_CLK_REGION_SLAVE_MODE = 2 ;
+static const uint8_t P9N2_PEC_CLK_REGION_MASTER_MODE = 3 ;
+static const uint8_t P9N2_PEC_CLK_REGION_CLOCK_PERV = 4 ;
+static const uint8_t P9N2_PEC_CLK_REGION_CLOCK_UNIT1 = 5 ;
+static const uint8_t P9N2_PEC_CLK_REGION_CLOCK_UNIT2 = 6 ;
+static const uint8_t P9N2_PEC_CLK_REGION_CLOCK_UNIT3 = 7 ;
+static const uint8_t P9N2_PEC_CLK_REGION_CLOCK_UNIT4 = 8 ;
+static const uint8_t P9N2_PEC_CLK_REGION_CLOCK_UNIT5 = 9 ;
+static const uint8_t P9N2_PEC_CLK_REGION_CLOCK_UNIT6 = 10 ;
+static const uint8_t P9N2_PEC_CLK_REGION_CLOCK_UNIT7 = 11 ;
+static const uint8_t P9N2_PEC_CLK_REGION_CLOCK_UNIT8 = 12 ;
+static const uint8_t P9N2_PEC_CLK_REGION_CLOCK_UNIT9 = 13 ;
+static const uint8_t P9N2_PEC_CLK_REGION_CLOCK_UNIT10 = 14 ;
+static const uint8_t P9N2_PEC_CLK_REGION_SEL_THOLD_SL = 48 ;
+static const uint8_t P9N2_PEC_CLK_REGION_SEL_THOLD_NSL = 49 ;
+static const uint8_t P9N2_PEC_CLK_REGION_SEL_THOLD_ARY = 50 ;
+static const uint8_t P9N2_PEC_CLK_REGION_CLOCK_PULSE_USE_EVEN = 52 ;
+
+static const uint8_t P9N2_PEC_CLOCK_STAT_ARY_STATUS_PERV = 4 ;
+static const uint8_t P9N2_PEC_CLOCK_STAT_ARY_STATUS_UNIT1 = 5 ;
+static const uint8_t P9N2_PEC_CLOCK_STAT_ARY_STATUS_UNIT2 = 6 ;
+static const uint8_t P9N2_PEC_CLOCK_STAT_ARY_STATUS_UNIT3 = 7 ;
+static const uint8_t P9N2_PEC_CLOCK_STAT_ARY_STATUS_UNIT4 = 8 ;
+static const uint8_t P9N2_PEC_CLOCK_STAT_ARY_STATUS_UNIT5 = 9 ;
+static const uint8_t P9N2_PEC_CLOCK_STAT_ARY_STATUS_UNIT6 = 10 ;
+static const uint8_t P9N2_PEC_CLOCK_STAT_ARY_STATUS_UNIT7 = 11 ;
+static const uint8_t P9N2_PEC_CLOCK_STAT_ARY_STATUS_UNIT8 = 12 ;
+static const uint8_t P9N2_PEC_CLOCK_STAT_ARY_STATUS_UNIT9 = 13 ;
+static const uint8_t P9N2_PEC_CLOCK_STAT_ARY_STATUS_UNIT10 = 14 ;
+
+static const uint8_t P9N2_PEC_CLOCK_STAT_NSL_STATUS_PERV = 4 ;
+static const uint8_t P9N2_PEC_CLOCK_STAT_NSL_STATUS_UNIT1 = 5 ;
+static const uint8_t P9N2_PEC_CLOCK_STAT_NSL_STATUS_UNIT2 = 6 ;
+static const uint8_t P9N2_PEC_CLOCK_STAT_NSL_STATUS_UNIT3 = 7 ;
+static const uint8_t P9N2_PEC_CLOCK_STAT_NSL_STATUS_UNIT4 = 8 ;
+static const uint8_t P9N2_PEC_CLOCK_STAT_NSL_STATUS_UNIT5 = 9 ;
+static const uint8_t P9N2_PEC_CLOCK_STAT_NSL_STATUS_UNIT6 = 10 ;
+static const uint8_t P9N2_PEC_CLOCK_STAT_NSL_STATUS_UNIT7 = 11 ;
+static const uint8_t P9N2_PEC_CLOCK_STAT_NSL_STATUS_UNIT8 = 12 ;
+static const uint8_t P9N2_PEC_CLOCK_STAT_NSL_STATUS_UNIT9 = 13 ;
+static const uint8_t P9N2_PEC_CLOCK_STAT_NSL_STATUS_UNIT10 = 14 ;
+
+static const uint8_t P9N2_PEC_CLOCK_STAT_SL_STATUS_PERV = 4 ;
+static const uint8_t P9N2_PEC_CLOCK_STAT_SL_STATUS_UNIT1 = 5 ;
+static const uint8_t P9N2_PEC_CLOCK_STAT_SL_STATUS_UNIT2 = 6 ;
+static const uint8_t P9N2_PEC_CLOCK_STAT_SL_STATUS_UNIT3 = 7 ;
+static const uint8_t P9N2_PEC_CLOCK_STAT_SL_STATUS_UNIT4 = 8 ;
+static const uint8_t P9N2_PEC_CLOCK_STAT_SL_STATUS_UNIT5 = 9 ;
+static const uint8_t P9N2_PEC_CLOCK_STAT_SL_STATUS_UNIT6 = 10 ;
+static const uint8_t P9N2_PEC_CLOCK_STAT_SL_STATUS_UNIT7 = 11 ;
+static const uint8_t P9N2_PEC_CLOCK_STAT_SL_STATUS_UNIT8 = 12 ;
+static const uint8_t P9N2_PEC_CLOCK_STAT_SL_STATUS_UNIT9 = 13 ;
+static const uint8_t P9N2_PEC_CLOCK_STAT_SL_STATUS_UNIT10 = 14 ;
+
+static const uint8_t P9N2_PU_CME4_CME_LCL_DBG_EN = 0 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_DBG_HALT_ON_XSTOP = 1 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_DBG_HALT_ON_TRIG = 2 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_DBG_RESERVED3 = 3 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_DBG_EN_INTR_ADDR = 4 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_DBG_EN_TRACE_EXTRA = 5 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_DBG_EN_TRACE_STALL = 6 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_DBG_EN_WAIT_CYCLES = 7 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_DBG_EN_FULL_SPEED = 8 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_DBG_RESERVED9 = 9 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_DBG_TRACE_MODE_SEL = 10 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_DBG_TRACE_MODE_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_DBG_RESERVED12_15 = 12 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_DBG_RESERVED12_15_LEN = 4 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_DBG_FIR_TRIGGER = 16 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_DBG_MIB_GPIO = 17 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_DBG_MIB_GPIO_LEN = 3 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_DBG_TRACE_DATA_SEL = 20 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_DBG_TRACE_DATA_SEL_LEN = 4 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_DBG_HALT_INPUT = 24 ;
+
+static const uint8_t P9N2_PU_CME3_CME_LCL_DBG_EN = 0 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_DBG_HALT_ON_XSTOP = 1 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_DBG_HALT_ON_TRIG = 2 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_DBG_RESERVED3 = 3 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_DBG_EN_INTR_ADDR = 4 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_DBG_EN_TRACE_EXTRA = 5 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_DBG_EN_TRACE_STALL = 6 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_DBG_EN_WAIT_CYCLES = 7 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_DBG_EN_FULL_SPEED = 8 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_DBG_RESERVED9 = 9 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_DBG_TRACE_MODE_SEL = 10 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_DBG_TRACE_MODE_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_DBG_RESERVED12_15 = 12 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_DBG_RESERVED12_15_LEN = 4 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_DBG_FIR_TRIGGER = 16 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_DBG_MIB_GPIO = 17 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_DBG_MIB_GPIO_LEN = 3 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_DBG_TRACE_DATA_SEL = 20 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_DBG_TRACE_DATA_SEL_LEN = 4 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_DBG_HALT_INPUT = 24 ;
+
+static const uint8_t P9N2_PU_CME11_CME_LCL_DBG_EN = 0 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_DBG_HALT_ON_XSTOP = 1 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_DBG_HALT_ON_TRIG = 2 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_DBG_RESERVED3 = 3 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_DBG_EN_INTR_ADDR = 4 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_DBG_EN_TRACE_EXTRA = 5 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_DBG_EN_TRACE_STALL = 6 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_DBG_EN_WAIT_CYCLES = 7 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_DBG_EN_FULL_SPEED = 8 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_DBG_RESERVED9 = 9 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_DBG_TRACE_MODE_SEL = 10 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_DBG_TRACE_MODE_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_DBG_RESERVED12_15 = 12 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_DBG_RESERVED12_15_LEN = 4 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_DBG_FIR_TRIGGER = 16 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_DBG_MIB_GPIO = 17 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_DBG_MIB_GPIO_LEN = 3 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_DBG_TRACE_DATA_SEL = 20 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_DBG_TRACE_DATA_SEL_LEN = 4 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_DBG_HALT_INPUT = 24 ;
+
+static const uint8_t P9N2_PU_CME2_CME_LCL_DBG_EN = 0 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_DBG_HALT_ON_XSTOP = 1 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_DBG_HALT_ON_TRIG = 2 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_DBG_RESERVED3 = 3 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_DBG_EN_INTR_ADDR = 4 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_DBG_EN_TRACE_EXTRA = 5 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_DBG_EN_TRACE_STALL = 6 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_DBG_EN_WAIT_CYCLES = 7 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_DBG_EN_FULL_SPEED = 8 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_DBG_RESERVED9 = 9 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_DBG_TRACE_MODE_SEL = 10 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_DBG_TRACE_MODE_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_DBG_RESERVED12_15 = 12 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_DBG_RESERVED12_15_LEN = 4 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_DBG_FIR_TRIGGER = 16 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_DBG_MIB_GPIO = 17 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_DBG_MIB_GPIO_LEN = 3 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_DBG_TRACE_DATA_SEL = 20 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_DBG_TRACE_DATA_SEL_LEN = 4 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_DBG_HALT_INPUT = 24 ;
+
+static const uint8_t P9N2_PU_CME5_CME_LCL_DBG_EN = 0 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_DBG_HALT_ON_XSTOP = 1 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_DBG_HALT_ON_TRIG = 2 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_DBG_RESERVED3 = 3 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_DBG_EN_INTR_ADDR = 4 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_DBG_EN_TRACE_EXTRA = 5 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_DBG_EN_TRACE_STALL = 6 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_DBG_EN_WAIT_CYCLES = 7 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_DBG_EN_FULL_SPEED = 8 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_DBG_RESERVED9 = 9 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_DBG_TRACE_MODE_SEL = 10 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_DBG_TRACE_MODE_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_DBG_RESERVED12_15 = 12 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_DBG_RESERVED12_15_LEN = 4 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_DBG_FIR_TRIGGER = 16 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_DBG_MIB_GPIO = 17 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_DBG_MIB_GPIO_LEN = 3 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_DBG_TRACE_DATA_SEL = 20 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_DBG_TRACE_DATA_SEL_LEN = 4 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_DBG_HALT_INPUT = 24 ;
+
+static const uint8_t P9N2_PU_CME9_CME_LCL_DBG_EN = 0 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_DBG_HALT_ON_XSTOP = 1 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_DBG_HALT_ON_TRIG = 2 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_DBG_RESERVED3 = 3 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_DBG_EN_INTR_ADDR = 4 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_DBG_EN_TRACE_EXTRA = 5 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_DBG_EN_TRACE_STALL = 6 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_DBG_EN_WAIT_CYCLES = 7 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_DBG_EN_FULL_SPEED = 8 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_DBG_RESERVED9 = 9 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_DBG_TRACE_MODE_SEL = 10 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_DBG_TRACE_MODE_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_DBG_RESERVED12_15 = 12 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_DBG_RESERVED12_15_LEN = 4 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_DBG_FIR_TRIGGER = 16 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_DBG_MIB_GPIO = 17 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_DBG_MIB_GPIO_LEN = 3 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_DBG_TRACE_DATA_SEL = 20 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_DBG_TRACE_DATA_SEL_LEN = 4 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_DBG_HALT_INPUT = 24 ;
+
+static const uint8_t P9N2_PU_CME6_CME_LCL_DBG_EN = 0 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_DBG_HALT_ON_XSTOP = 1 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_DBG_HALT_ON_TRIG = 2 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_DBG_RESERVED3 = 3 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_DBG_EN_INTR_ADDR = 4 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_DBG_EN_TRACE_EXTRA = 5 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_DBG_EN_TRACE_STALL = 6 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_DBG_EN_WAIT_CYCLES = 7 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_DBG_EN_FULL_SPEED = 8 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_DBG_RESERVED9 = 9 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_DBG_TRACE_MODE_SEL = 10 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_DBG_TRACE_MODE_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_DBG_RESERVED12_15 = 12 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_DBG_RESERVED12_15_LEN = 4 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_DBG_FIR_TRIGGER = 16 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_DBG_MIB_GPIO = 17 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_DBG_MIB_GPIO_LEN = 3 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_DBG_TRACE_DATA_SEL = 20 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_DBG_TRACE_DATA_SEL_LEN = 4 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_DBG_HALT_INPUT = 24 ;
+
+static const uint8_t P9N2_PU_CME10_CME_LCL_DBG_EN = 0 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_DBG_HALT_ON_XSTOP = 1 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_DBG_HALT_ON_TRIG = 2 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_DBG_RESERVED3 = 3 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_DBG_EN_INTR_ADDR = 4 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_DBG_EN_TRACE_EXTRA = 5 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_DBG_EN_TRACE_STALL = 6 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_DBG_EN_WAIT_CYCLES = 7 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_DBG_EN_FULL_SPEED = 8 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_DBG_RESERVED9 = 9 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_DBG_TRACE_MODE_SEL = 10 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_DBG_TRACE_MODE_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_DBG_RESERVED12_15 = 12 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_DBG_RESERVED12_15_LEN = 4 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_DBG_FIR_TRIGGER = 16 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_DBG_MIB_GPIO = 17 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_DBG_MIB_GPIO_LEN = 3 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_DBG_TRACE_DATA_SEL = 20 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_DBG_TRACE_DATA_SEL_LEN = 4 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_DBG_HALT_INPUT = 24 ;
+
+static const uint8_t P9N2_PU_CME8_CME_LCL_DBG_EN = 0 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_DBG_HALT_ON_XSTOP = 1 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_DBG_HALT_ON_TRIG = 2 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_DBG_RESERVED3 = 3 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_DBG_EN_INTR_ADDR = 4 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_DBG_EN_TRACE_EXTRA = 5 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_DBG_EN_TRACE_STALL = 6 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_DBG_EN_WAIT_CYCLES = 7 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_DBG_EN_FULL_SPEED = 8 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_DBG_RESERVED9 = 9 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_DBG_TRACE_MODE_SEL = 10 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_DBG_TRACE_MODE_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_DBG_RESERVED12_15 = 12 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_DBG_RESERVED12_15_LEN = 4 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_DBG_FIR_TRIGGER = 16 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_DBG_MIB_GPIO = 17 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_DBG_MIB_GPIO_LEN = 3 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_DBG_TRACE_DATA_SEL = 20 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_DBG_TRACE_DATA_SEL_LEN = 4 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_DBG_HALT_INPUT = 24 ;
+
+static const uint8_t P9N2_PU_CME1_CME_LCL_DBG_EN = 0 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_DBG_HALT_ON_XSTOP = 1 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_DBG_HALT_ON_TRIG = 2 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_DBG_RESERVED3 = 3 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_DBG_EN_INTR_ADDR = 4 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_DBG_EN_TRACE_EXTRA = 5 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_DBG_EN_TRACE_STALL = 6 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_DBG_EN_WAIT_CYCLES = 7 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_DBG_EN_FULL_SPEED = 8 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_DBG_RESERVED9 = 9 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_DBG_TRACE_MODE_SEL = 10 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_DBG_TRACE_MODE_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_DBG_RESERVED12_15 = 12 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_DBG_RESERVED12_15_LEN = 4 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_DBG_FIR_TRIGGER = 16 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_DBG_MIB_GPIO = 17 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_DBG_MIB_GPIO_LEN = 3 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_DBG_TRACE_DATA_SEL = 20 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_DBG_TRACE_DATA_SEL_LEN = 4 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_DBG_HALT_INPUT = 24 ;
+
+static const uint8_t P9N2_PU_CME0_CME_LCL_DBG_EN = 0 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_DBG_HALT_ON_XSTOP = 1 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_DBG_HALT_ON_TRIG = 2 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_DBG_RESERVED3 = 3 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_DBG_EN_INTR_ADDR = 4 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_DBG_EN_TRACE_EXTRA = 5 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_DBG_EN_TRACE_STALL = 6 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_DBG_EN_WAIT_CYCLES = 7 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_DBG_EN_FULL_SPEED = 8 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_DBG_RESERVED9 = 9 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_DBG_TRACE_MODE_SEL = 10 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_DBG_TRACE_MODE_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_DBG_RESERVED12_15 = 12 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_DBG_RESERVED12_15_LEN = 4 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_DBG_FIR_TRIGGER = 16 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_DBG_MIB_GPIO = 17 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_DBG_MIB_GPIO_LEN = 3 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_DBG_TRACE_DATA_SEL = 20 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_DBG_TRACE_DATA_SEL_LEN = 4 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_DBG_HALT_INPUT = 24 ;
+
+static const uint8_t P9N2_PU_CME7_CME_LCL_DBG_EN = 0 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_DBG_HALT_ON_XSTOP = 1 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_DBG_HALT_ON_TRIG = 2 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_DBG_RESERVED3 = 3 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_DBG_EN_INTR_ADDR = 4 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_DBG_EN_TRACE_EXTRA = 5 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_DBG_EN_TRACE_STALL = 6 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_DBG_EN_WAIT_CYCLES = 7 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_DBG_EN_FULL_SPEED = 8 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_DBG_RESERVED9 = 9 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_DBG_TRACE_MODE_SEL = 10 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_DBG_TRACE_MODE_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_DBG_RESERVED12_15 = 12 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_DBG_RESERVED12_15_LEN = 4 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_DBG_FIR_TRIGGER = 16 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_DBG_MIB_GPIO = 17 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_DBG_MIB_GPIO_LEN = 3 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_DBG_TRACE_DATA_SEL = 20 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_DBG_TRACE_DATA_SEL_LEN = 4 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_DBG_HALT_INPUT = 24 ;
+
+static const uint8_t P9N2_PU_CME4_CME_LCL_EIMR_INTERRUPT_MASK = 0 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_EIMR_INTERRUPT_MASK_LEN = 44 ;
+
+static const uint8_t P9N2_PU_CME3_CME_LCL_EIMR_INTERRUPT_MASK = 0 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_EIMR_INTERRUPT_MASK_LEN = 44 ;
+
+static const uint8_t P9N2_PU_CME11_CME_LCL_EIMR_INTERRUPT_MASK = 0 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_EIMR_INTERRUPT_MASK_LEN = 44 ;
+
+static const uint8_t P9N2_PU_CME2_CME_LCL_EIMR_INTERRUPT_MASK = 0 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_EIMR_INTERRUPT_MASK_LEN = 44 ;
+
+static const uint8_t P9N2_PU_CME5_CME_LCL_EIMR_INTERRUPT_MASK = 0 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_EIMR_INTERRUPT_MASK_LEN = 44 ;
+
+static const uint8_t P9N2_PU_CME9_CME_LCL_EIMR_INTERRUPT_MASK = 0 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_EIMR_INTERRUPT_MASK_LEN = 44 ;
+
+static const uint8_t P9N2_PU_CME6_CME_LCL_EIMR_INTERRUPT_MASK = 0 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_EIMR_INTERRUPT_MASK_LEN = 44 ;
+
+static const uint8_t P9N2_PU_CME10_CME_LCL_EIMR_INTERRUPT_MASK = 0 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_EIMR_INTERRUPT_MASK_LEN = 44 ;
+
+static const uint8_t P9N2_PU_CME8_CME_LCL_EIMR_INTERRUPT_MASK = 0 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_EIMR_INTERRUPT_MASK_LEN = 44 ;
+
+static const uint8_t P9N2_PU_CME1_CME_LCL_EIMR_INTERRUPT_MASK = 0 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_EIMR_INTERRUPT_MASK_LEN = 44 ;
+
+static const uint8_t P9N2_PU_CME0_CME_LCL_EIMR_INTERRUPT_MASK = 0 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_EIMR_INTERRUPT_MASK_LEN = 44 ;
+
+static const uint8_t P9N2_PU_CME7_CME_LCL_EIMR_INTERRUPT_MASK = 0 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_EIMR_INTERRUPT_MASK_LEN = 44 ;
+
+static const uint8_t P9N2_PU_CME4_CME_LCL_EINR_INTERRUPT_INPUT = 0 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_EINR_INTERRUPT_INPUT_LEN = 44 ;
+
+static const uint8_t P9N2_PU_CME3_CME_LCL_EINR_INTERRUPT_INPUT = 0 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_EINR_INTERRUPT_INPUT_LEN = 44 ;
+
+static const uint8_t P9N2_PU_CME11_CME_LCL_EINR_INTERRUPT_INPUT = 0 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_EINR_INTERRUPT_INPUT_LEN = 44 ;
+
+static const uint8_t P9N2_PU_CME2_CME_LCL_EINR_INTERRUPT_INPUT = 0 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_EINR_INTERRUPT_INPUT_LEN = 44 ;
+
+static const uint8_t P9N2_PU_CME5_CME_LCL_EINR_INTERRUPT_INPUT = 0 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_EINR_INTERRUPT_INPUT_LEN = 44 ;
+
+static const uint8_t P9N2_PU_CME9_CME_LCL_EINR_INTERRUPT_INPUT = 0 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_EINR_INTERRUPT_INPUT_LEN = 44 ;
+
+static const uint8_t P9N2_PU_CME6_CME_LCL_EINR_INTERRUPT_INPUT = 0 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_EINR_INTERRUPT_INPUT_LEN = 44 ;
+
+static const uint8_t P9N2_PU_CME10_CME_LCL_EINR_INTERRUPT_INPUT = 0 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_EINR_INTERRUPT_INPUT_LEN = 44 ;
+
+static const uint8_t P9N2_PU_CME8_CME_LCL_EINR_INTERRUPT_INPUT = 0 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_EINR_INTERRUPT_INPUT_LEN = 44 ;
+
+static const uint8_t P9N2_PU_CME1_CME_LCL_EINR_INTERRUPT_INPUT = 0 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_EINR_INTERRUPT_INPUT_LEN = 44 ;
+
+static const uint8_t P9N2_PU_CME0_CME_LCL_EINR_INTERRUPT_INPUT = 0 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_EINR_INTERRUPT_INPUT_LEN = 44 ;
+
+static const uint8_t P9N2_PU_CME7_CME_LCL_EINR_INTERRUPT_INPUT = 0 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_EINR_INTERRUPT_INPUT_LEN = 44 ;
+
+static const uint8_t P9N2_PU_CME4_CME_LCL_EIPR_INTERRUPT_POLARITY = 0 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_EIPR_INTERRUPT_POLARITY_LEN = 44 ;
+
+static const uint8_t P9N2_PU_CME3_CME_LCL_EIPR_INTERRUPT_POLARITY = 0 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_EIPR_INTERRUPT_POLARITY_LEN = 44 ;
+
+static const uint8_t P9N2_PU_CME11_CME_LCL_EIPR_INTERRUPT_POLARITY = 0 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_EIPR_INTERRUPT_POLARITY_LEN = 44 ;
+
+static const uint8_t P9N2_PU_CME2_CME_LCL_EIPR_INTERRUPT_POLARITY = 0 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_EIPR_INTERRUPT_POLARITY_LEN = 44 ;
+
+static const uint8_t P9N2_PU_CME5_CME_LCL_EIPR_INTERRUPT_POLARITY = 0 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_EIPR_INTERRUPT_POLARITY_LEN = 44 ;
+
+static const uint8_t P9N2_PU_CME9_CME_LCL_EIPR_INTERRUPT_POLARITY = 0 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_EIPR_INTERRUPT_POLARITY_LEN = 44 ;
+
+static const uint8_t P9N2_PU_CME6_CME_LCL_EIPR_INTERRUPT_POLARITY = 0 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_EIPR_INTERRUPT_POLARITY_LEN = 44 ;
+
+static const uint8_t P9N2_PU_CME10_CME_LCL_EIPR_INTERRUPT_POLARITY = 0 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_EIPR_INTERRUPT_POLARITY_LEN = 44 ;
+
+static const uint8_t P9N2_PU_CME8_CME_LCL_EIPR_INTERRUPT_POLARITY = 0 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_EIPR_INTERRUPT_POLARITY_LEN = 44 ;
+
+static const uint8_t P9N2_PU_CME1_CME_LCL_EIPR_INTERRUPT_POLARITY = 0 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_EIPR_INTERRUPT_POLARITY_LEN = 44 ;
+
+static const uint8_t P9N2_PU_CME0_CME_LCL_EIPR_INTERRUPT_POLARITY = 0 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_EIPR_INTERRUPT_POLARITY_LEN = 44 ;
+
+static const uint8_t P9N2_PU_CME7_CME_LCL_EIPR_INTERRUPT_POLARITY = 0 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_EIPR_INTERRUPT_POLARITY_LEN = 44 ;
+
+static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_DEBUGGER = 0 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_DEBUG_TRIGGER = 1 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_QUAD_CHECKSTOP = 2 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_PVREF_FAIL = 3 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_OCC_HEARTBEAT_LOST = 4 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_CORE_CHECKSTOP = 5 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_DROPOUT_DETECT = 6 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_INTERCME_DIRECT_IN_0 = 7 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_BCE_BUSY_HIGH = 8 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_BCE_TIMEOUT = 9 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_DOORBELL3_C0 = 10 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_DOORBELL3_C1 = 11 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_PC_INTR_PENDING_C0 = 12 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_PC_INTR_PENDING_C1 = 13 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_SPECIAL_WAKEUP_C0 = 14 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_SPECIAL_WAKEUP_C1 = 15 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_REG_WAKEUP_C0 = 16 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_REG_WAKEUP_C1 = 17 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_DOORBELL2_C0 = 18 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_DOORBELL2_C1 = 19 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C0 = 20 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C1 = 21 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_L2_PURGE_DONE = 22 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_NCU_PURGE_DONE = 23 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_CHTM_PURGE_DONE_C0 = 24 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_CHTM_PURGE_DONE_C1 = 25 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_BCE_BUSY_LOW = 26 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_FINAL_VDM_DATA01 = 27 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_FINAL_VDM_DATA01_LEN = 2 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_COMM_RECVD = 29 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_COMM_SEND_ACK = 30 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_COMM_SEND_NACK = 31 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_BLOCK_REG_WAKEUP_C0 = 32 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_BLOCK_REG_WAKEUP_C1 = 33 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_PMCR_UPDATE_C0 = 34 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_PMCR_UPDATE_C1 = 35 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_DOORBELL0_C0 = 36 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_DOORBELL0_C1 = 37 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2 = 38 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2_LEN = 2 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_DOORBELL1_C0 = 40 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_DOORBELL1_C1 = 41 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_RESERVED_42_43 = 42 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_EISR_RESERVED_42_43_LEN = 2 ;
+
+static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_DEBUGGER = 0 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_DEBUG_TRIGGER = 1 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_QUAD_CHECKSTOP = 2 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_PVREF_FAIL = 3 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_OCC_HEARTBEAT_LOST = 4 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_CORE_CHECKSTOP = 5 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_DROPOUT_DETECT = 6 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_INTERCME_DIRECT_IN_0 = 7 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_BCE_BUSY_HIGH = 8 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_BCE_TIMEOUT = 9 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_DOORBELL3_C0 = 10 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_DOORBELL3_C1 = 11 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_PC_INTR_PENDING_C0 = 12 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_PC_INTR_PENDING_C1 = 13 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_SPECIAL_WAKEUP_C0 = 14 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_SPECIAL_WAKEUP_C1 = 15 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_REG_WAKEUP_C0 = 16 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_REG_WAKEUP_C1 = 17 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_DOORBELL2_C0 = 18 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_DOORBELL2_C1 = 19 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C0 = 20 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C1 = 21 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_L2_PURGE_DONE = 22 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_NCU_PURGE_DONE = 23 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_CHTM_PURGE_DONE_C0 = 24 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_CHTM_PURGE_DONE_C1 = 25 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_BCE_BUSY_LOW = 26 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_FINAL_VDM_DATA01 = 27 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_FINAL_VDM_DATA01_LEN = 2 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_COMM_RECVD = 29 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_COMM_SEND_ACK = 30 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_COMM_SEND_NACK = 31 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_BLOCK_REG_WAKEUP_C0 = 32 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_BLOCK_REG_WAKEUP_C1 = 33 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_PMCR_UPDATE_C0 = 34 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_PMCR_UPDATE_C1 = 35 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_DOORBELL0_C0 = 36 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_DOORBELL0_C1 = 37 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2 = 38 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2_LEN = 2 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_DOORBELL1_C0 = 40 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_DOORBELL1_C1 = 41 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_RESERVED_42_43 = 42 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_EISR_RESERVED_42_43_LEN = 2 ;
+
+static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_DEBUGGER = 0 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_DEBUG_TRIGGER = 1 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_QUAD_CHECKSTOP = 2 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_PVREF_FAIL = 3 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_OCC_HEARTBEAT_LOST = 4 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_CORE_CHECKSTOP = 5 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_DROPOUT_DETECT = 6 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_INTERCME_DIRECT_IN_0 = 7 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_BCE_BUSY_HIGH = 8 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_BCE_TIMEOUT = 9 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_DOORBELL3_C0 = 10 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_DOORBELL3_C1 = 11 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_PC_INTR_PENDING_C0 = 12 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_PC_INTR_PENDING_C1 = 13 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_SPECIAL_WAKEUP_C0 = 14 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_SPECIAL_WAKEUP_C1 = 15 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_REG_WAKEUP_C0 = 16 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_REG_WAKEUP_C1 = 17 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_DOORBELL2_C0 = 18 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_DOORBELL2_C1 = 19 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C0 = 20 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C1 = 21 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_L2_PURGE_DONE = 22 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_NCU_PURGE_DONE = 23 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_CHTM_PURGE_DONE_C0 = 24 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_CHTM_PURGE_DONE_C1 = 25 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_BCE_BUSY_LOW = 26 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_FINAL_VDM_DATA01 = 27 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_FINAL_VDM_DATA01_LEN = 2 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_COMM_RECVD = 29 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_COMM_SEND_ACK = 30 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_COMM_SEND_NACK = 31 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_BLOCK_REG_WAKEUP_C0 = 32 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_BLOCK_REG_WAKEUP_C1 = 33 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_PMCR_UPDATE_C0 = 34 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_PMCR_UPDATE_C1 = 35 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_DOORBELL0_C0 = 36 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_DOORBELL0_C1 = 37 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2 = 38 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2_LEN = 2 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_DOORBELL1_C0 = 40 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_DOORBELL1_C1 = 41 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_RESERVED_42_43 = 42 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_EISR_RESERVED_42_43_LEN = 2 ;
+
+static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_DEBUGGER = 0 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_DEBUG_TRIGGER = 1 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_QUAD_CHECKSTOP = 2 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_PVREF_FAIL = 3 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_OCC_HEARTBEAT_LOST = 4 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_CORE_CHECKSTOP = 5 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_DROPOUT_DETECT = 6 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_INTERCME_DIRECT_IN_0 = 7 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_BCE_BUSY_HIGH = 8 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_BCE_TIMEOUT = 9 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_DOORBELL3_C0 = 10 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_DOORBELL3_C1 = 11 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_PC_INTR_PENDING_C0 = 12 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_PC_INTR_PENDING_C1 = 13 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_SPECIAL_WAKEUP_C0 = 14 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_SPECIAL_WAKEUP_C1 = 15 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_REG_WAKEUP_C0 = 16 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_REG_WAKEUP_C1 = 17 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_DOORBELL2_C0 = 18 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_DOORBELL2_C1 = 19 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C0 = 20 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C1 = 21 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_L2_PURGE_DONE = 22 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_NCU_PURGE_DONE = 23 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_CHTM_PURGE_DONE_C0 = 24 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_CHTM_PURGE_DONE_C1 = 25 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_BCE_BUSY_LOW = 26 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_FINAL_VDM_DATA01 = 27 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_FINAL_VDM_DATA01_LEN = 2 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_COMM_RECVD = 29 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_COMM_SEND_ACK = 30 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_COMM_SEND_NACK = 31 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_BLOCK_REG_WAKEUP_C0 = 32 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_BLOCK_REG_WAKEUP_C1 = 33 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_PMCR_UPDATE_C0 = 34 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_PMCR_UPDATE_C1 = 35 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_DOORBELL0_C0 = 36 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_DOORBELL0_C1 = 37 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2 = 38 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2_LEN = 2 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_DOORBELL1_C0 = 40 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_DOORBELL1_C1 = 41 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_RESERVED_42_43 = 42 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_EISR_RESERVED_42_43_LEN = 2 ;
+
+static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_DEBUGGER = 0 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_DEBUG_TRIGGER = 1 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_QUAD_CHECKSTOP = 2 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_PVREF_FAIL = 3 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_OCC_HEARTBEAT_LOST = 4 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_CORE_CHECKSTOP = 5 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_DROPOUT_DETECT = 6 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_INTERCME_DIRECT_IN_0 = 7 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_BCE_BUSY_HIGH = 8 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_BCE_TIMEOUT = 9 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_DOORBELL3_C0 = 10 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_DOORBELL3_C1 = 11 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_PC_INTR_PENDING_C0 = 12 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_PC_INTR_PENDING_C1 = 13 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_SPECIAL_WAKEUP_C0 = 14 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_SPECIAL_WAKEUP_C1 = 15 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_REG_WAKEUP_C0 = 16 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_REG_WAKEUP_C1 = 17 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_DOORBELL2_C0 = 18 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_DOORBELL2_C1 = 19 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C0 = 20 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C1 = 21 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_L2_PURGE_DONE = 22 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_NCU_PURGE_DONE = 23 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_CHTM_PURGE_DONE_C0 = 24 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_CHTM_PURGE_DONE_C1 = 25 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_BCE_BUSY_LOW = 26 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_FINAL_VDM_DATA01 = 27 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_FINAL_VDM_DATA01_LEN = 2 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_COMM_RECVD = 29 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_COMM_SEND_ACK = 30 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_COMM_SEND_NACK = 31 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_BLOCK_REG_WAKEUP_C0 = 32 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_BLOCK_REG_WAKEUP_C1 = 33 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_PMCR_UPDATE_C0 = 34 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_PMCR_UPDATE_C1 = 35 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_DOORBELL0_C0 = 36 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_DOORBELL0_C1 = 37 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2 = 38 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2_LEN = 2 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_DOORBELL1_C0 = 40 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_DOORBELL1_C1 = 41 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_RESERVED_42_43 = 42 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_EISR_RESERVED_42_43_LEN = 2 ;
+
+static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_DEBUGGER = 0 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_DEBUG_TRIGGER = 1 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_QUAD_CHECKSTOP = 2 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_PVREF_FAIL = 3 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_OCC_HEARTBEAT_LOST = 4 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_CORE_CHECKSTOP = 5 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_DROPOUT_DETECT = 6 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_INTERCME_DIRECT_IN_0 = 7 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_BCE_BUSY_HIGH = 8 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_BCE_TIMEOUT = 9 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_DOORBELL3_C0 = 10 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_DOORBELL3_C1 = 11 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_PC_INTR_PENDING_C0 = 12 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_PC_INTR_PENDING_C1 = 13 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_SPECIAL_WAKEUP_C0 = 14 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_SPECIAL_WAKEUP_C1 = 15 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_REG_WAKEUP_C0 = 16 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_REG_WAKEUP_C1 = 17 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_DOORBELL2_C0 = 18 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_DOORBELL2_C1 = 19 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C0 = 20 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C1 = 21 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_L2_PURGE_DONE = 22 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_NCU_PURGE_DONE = 23 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_CHTM_PURGE_DONE_C0 = 24 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_CHTM_PURGE_DONE_C1 = 25 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_BCE_BUSY_LOW = 26 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_FINAL_VDM_DATA01 = 27 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_FINAL_VDM_DATA01_LEN = 2 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_COMM_RECVD = 29 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_COMM_SEND_ACK = 30 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_COMM_SEND_NACK = 31 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_BLOCK_REG_WAKEUP_C0 = 32 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_BLOCK_REG_WAKEUP_C1 = 33 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_PMCR_UPDATE_C0 = 34 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_PMCR_UPDATE_C1 = 35 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_DOORBELL0_C0 = 36 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_DOORBELL0_C1 = 37 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2 = 38 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2_LEN = 2 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_DOORBELL1_C0 = 40 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_DOORBELL1_C1 = 41 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_RESERVED_42_43 = 42 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_EISR_RESERVED_42_43_LEN = 2 ;
+
+static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_DEBUGGER = 0 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_DEBUG_TRIGGER = 1 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_QUAD_CHECKSTOP = 2 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_PVREF_FAIL = 3 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_OCC_HEARTBEAT_LOST = 4 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_CORE_CHECKSTOP = 5 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_DROPOUT_DETECT = 6 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_INTERCME_DIRECT_IN_0 = 7 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_BCE_BUSY_HIGH = 8 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_BCE_TIMEOUT = 9 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_DOORBELL3_C0 = 10 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_DOORBELL3_C1 = 11 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_PC_INTR_PENDING_C0 = 12 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_PC_INTR_PENDING_C1 = 13 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_SPECIAL_WAKEUP_C0 = 14 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_SPECIAL_WAKEUP_C1 = 15 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_REG_WAKEUP_C0 = 16 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_REG_WAKEUP_C1 = 17 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_DOORBELL2_C0 = 18 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_DOORBELL2_C1 = 19 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C0 = 20 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C1 = 21 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_L2_PURGE_DONE = 22 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_NCU_PURGE_DONE = 23 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_CHTM_PURGE_DONE_C0 = 24 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_CHTM_PURGE_DONE_C1 = 25 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_BCE_BUSY_LOW = 26 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_FINAL_VDM_DATA01 = 27 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_FINAL_VDM_DATA01_LEN = 2 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_COMM_RECVD = 29 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_COMM_SEND_ACK = 30 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_COMM_SEND_NACK = 31 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_BLOCK_REG_WAKEUP_C0 = 32 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_BLOCK_REG_WAKEUP_C1 = 33 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_PMCR_UPDATE_C0 = 34 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_PMCR_UPDATE_C1 = 35 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_DOORBELL0_C0 = 36 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_DOORBELL0_C1 = 37 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2 = 38 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2_LEN = 2 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_DOORBELL1_C0 = 40 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_DOORBELL1_C1 = 41 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_RESERVED_42_43 = 42 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_EISR_RESERVED_42_43_LEN = 2 ;
+
+static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_DEBUGGER = 0 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_DEBUG_TRIGGER = 1 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_QUAD_CHECKSTOP = 2 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_PVREF_FAIL = 3 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_OCC_HEARTBEAT_LOST = 4 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_CORE_CHECKSTOP = 5 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_DROPOUT_DETECT = 6 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_INTERCME_DIRECT_IN_0 = 7 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_BCE_BUSY_HIGH = 8 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_BCE_TIMEOUT = 9 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_DOORBELL3_C0 = 10 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_DOORBELL3_C1 = 11 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_PC_INTR_PENDING_C0 = 12 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_PC_INTR_PENDING_C1 = 13 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_SPECIAL_WAKEUP_C0 = 14 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_SPECIAL_WAKEUP_C1 = 15 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_REG_WAKEUP_C0 = 16 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_REG_WAKEUP_C1 = 17 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_DOORBELL2_C0 = 18 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_DOORBELL2_C1 = 19 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C0 = 20 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C1 = 21 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_L2_PURGE_DONE = 22 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_NCU_PURGE_DONE = 23 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_CHTM_PURGE_DONE_C0 = 24 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_CHTM_PURGE_DONE_C1 = 25 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_BCE_BUSY_LOW = 26 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_FINAL_VDM_DATA01 = 27 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_FINAL_VDM_DATA01_LEN = 2 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_COMM_RECVD = 29 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_COMM_SEND_ACK = 30 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_COMM_SEND_NACK = 31 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_BLOCK_REG_WAKEUP_C0 = 32 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_BLOCK_REG_WAKEUP_C1 = 33 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_PMCR_UPDATE_C0 = 34 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_PMCR_UPDATE_C1 = 35 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_DOORBELL0_C0 = 36 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_DOORBELL0_C1 = 37 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2 = 38 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2_LEN = 2 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_DOORBELL1_C0 = 40 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_DOORBELL1_C1 = 41 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_RESERVED_42_43 = 42 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_EISR_RESERVED_42_43_LEN = 2 ;
+
+static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_DEBUGGER = 0 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_DEBUG_TRIGGER = 1 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_QUAD_CHECKSTOP = 2 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_PVREF_FAIL = 3 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_OCC_HEARTBEAT_LOST = 4 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_CORE_CHECKSTOP = 5 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_DROPOUT_DETECT = 6 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_INTERCME_DIRECT_IN_0 = 7 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_BCE_BUSY_HIGH = 8 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_BCE_TIMEOUT = 9 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_DOORBELL3_C0 = 10 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_DOORBELL3_C1 = 11 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_PC_INTR_PENDING_C0 = 12 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_PC_INTR_PENDING_C1 = 13 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_SPECIAL_WAKEUP_C0 = 14 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_SPECIAL_WAKEUP_C1 = 15 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_REG_WAKEUP_C0 = 16 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_REG_WAKEUP_C1 = 17 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_DOORBELL2_C0 = 18 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_DOORBELL2_C1 = 19 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C0 = 20 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C1 = 21 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_L2_PURGE_DONE = 22 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_NCU_PURGE_DONE = 23 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_CHTM_PURGE_DONE_C0 = 24 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_CHTM_PURGE_DONE_C1 = 25 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_BCE_BUSY_LOW = 26 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_FINAL_VDM_DATA01 = 27 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_FINAL_VDM_DATA01_LEN = 2 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_COMM_RECVD = 29 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_COMM_SEND_ACK = 30 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_COMM_SEND_NACK = 31 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_BLOCK_REG_WAKEUP_C0 = 32 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_BLOCK_REG_WAKEUP_C1 = 33 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_PMCR_UPDATE_C0 = 34 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_PMCR_UPDATE_C1 = 35 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_DOORBELL0_C0 = 36 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_DOORBELL0_C1 = 37 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2 = 38 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2_LEN = 2 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_DOORBELL1_C0 = 40 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_DOORBELL1_C1 = 41 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_RESERVED_42_43 = 42 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_EISR_RESERVED_42_43_LEN = 2 ;
+
+static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_DEBUGGER = 0 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_DEBUG_TRIGGER = 1 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_QUAD_CHECKSTOP = 2 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_PVREF_FAIL = 3 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_OCC_HEARTBEAT_LOST = 4 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_CORE_CHECKSTOP = 5 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_DROPOUT_DETECT = 6 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_INTERCME_DIRECT_IN_0 = 7 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_BCE_BUSY_HIGH = 8 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_BCE_TIMEOUT = 9 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_DOORBELL3_C0 = 10 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_DOORBELL3_C1 = 11 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_PC_INTR_PENDING_C0 = 12 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_PC_INTR_PENDING_C1 = 13 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_SPECIAL_WAKEUP_C0 = 14 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_SPECIAL_WAKEUP_C1 = 15 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_REG_WAKEUP_C0 = 16 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_REG_WAKEUP_C1 = 17 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_DOORBELL2_C0 = 18 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_DOORBELL2_C1 = 19 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C0 = 20 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C1 = 21 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_L2_PURGE_DONE = 22 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_NCU_PURGE_DONE = 23 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_CHTM_PURGE_DONE_C0 = 24 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_CHTM_PURGE_DONE_C1 = 25 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_BCE_BUSY_LOW = 26 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_FINAL_VDM_DATA01 = 27 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_FINAL_VDM_DATA01_LEN = 2 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_COMM_RECVD = 29 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_COMM_SEND_ACK = 30 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_COMM_SEND_NACK = 31 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_BLOCK_REG_WAKEUP_C0 = 32 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_BLOCK_REG_WAKEUP_C1 = 33 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_PMCR_UPDATE_C0 = 34 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_PMCR_UPDATE_C1 = 35 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_DOORBELL0_C0 = 36 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_DOORBELL0_C1 = 37 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2 = 38 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2_LEN = 2 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_DOORBELL1_C0 = 40 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_DOORBELL1_C1 = 41 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_RESERVED_42_43 = 42 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_EISR_RESERVED_42_43_LEN = 2 ;
+
+static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_DEBUGGER = 0 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_DEBUG_TRIGGER = 1 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_QUAD_CHECKSTOP = 2 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_PVREF_FAIL = 3 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_OCC_HEARTBEAT_LOST = 4 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_CORE_CHECKSTOP = 5 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_DROPOUT_DETECT = 6 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_INTERCME_DIRECT_IN_0 = 7 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_BCE_BUSY_HIGH = 8 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_BCE_TIMEOUT = 9 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_DOORBELL3_C0 = 10 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_DOORBELL3_C1 = 11 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_PC_INTR_PENDING_C0 = 12 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_PC_INTR_PENDING_C1 = 13 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_SPECIAL_WAKEUP_C0 = 14 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_SPECIAL_WAKEUP_C1 = 15 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_REG_WAKEUP_C0 = 16 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_REG_WAKEUP_C1 = 17 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_DOORBELL2_C0 = 18 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_DOORBELL2_C1 = 19 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C0 = 20 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C1 = 21 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_L2_PURGE_DONE = 22 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_NCU_PURGE_DONE = 23 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_CHTM_PURGE_DONE_C0 = 24 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_CHTM_PURGE_DONE_C1 = 25 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_BCE_BUSY_LOW = 26 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_FINAL_VDM_DATA01 = 27 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_FINAL_VDM_DATA01_LEN = 2 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_COMM_RECVD = 29 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_COMM_SEND_ACK = 30 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_COMM_SEND_NACK = 31 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_BLOCK_REG_WAKEUP_C0 = 32 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_BLOCK_REG_WAKEUP_C1 = 33 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_PMCR_UPDATE_C0 = 34 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_PMCR_UPDATE_C1 = 35 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_DOORBELL0_C0 = 36 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_DOORBELL0_C1 = 37 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2 = 38 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2_LEN = 2 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_DOORBELL1_C0 = 40 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_DOORBELL1_C1 = 41 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_RESERVED_42_43 = 42 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_EISR_RESERVED_42_43_LEN = 2 ;
+
+static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_DEBUGGER = 0 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_DEBUG_TRIGGER = 1 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_QUAD_CHECKSTOP = 2 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_PVREF_FAIL = 3 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_OCC_HEARTBEAT_LOST = 4 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_CORE_CHECKSTOP = 5 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_DROPOUT_DETECT = 6 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_INTERCME_DIRECT_IN_0 = 7 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_BCE_BUSY_HIGH = 8 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_BCE_TIMEOUT = 9 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_DOORBELL3_C0 = 10 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_DOORBELL3_C1 = 11 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_PC_INTR_PENDING_C0 = 12 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_PC_INTR_PENDING_C1 = 13 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_SPECIAL_WAKEUP_C0 = 14 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_SPECIAL_WAKEUP_C1 = 15 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_REG_WAKEUP_C0 = 16 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_REG_WAKEUP_C1 = 17 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_DOORBELL2_C0 = 18 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_DOORBELL2_C1 = 19 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C0 = 20 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C1 = 21 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_L2_PURGE_DONE = 22 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_NCU_PURGE_DONE = 23 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_CHTM_PURGE_DONE_C0 = 24 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_CHTM_PURGE_DONE_C1 = 25 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_BCE_BUSY_LOW = 26 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_FINAL_VDM_DATA01 = 27 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_FINAL_VDM_DATA01_LEN = 2 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_COMM_RECVD = 29 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_COMM_SEND_ACK = 30 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_COMM_SEND_NACK = 31 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_BLOCK_REG_WAKEUP_C0 = 32 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_BLOCK_REG_WAKEUP_C1 = 33 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_PMCR_UPDATE_C0 = 34 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_PMCR_UPDATE_C1 = 35 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_DOORBELL0_C0 = 36 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_DOORBELL0_C1 = 37 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2 = 38 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2_LEN = 2 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_DOORBELL1_C0 = 40 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_DOORBELL1_C1 = 41 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_RESERVED_42_43 = 42 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_EISR_RESERVED_42_43_LEN = 2 ;
+
+static const uint8_t P9N2_PU_CME4_CME_LCL_EISTR_INTERRUPT_STATUS = 0 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_EISTR_INTERRUPT_STATUS_LEN = 44 ;
+
+static const uint8_t P9N2_PU_CME3_CME_LCL_EISTR_INTERRUPT_STATUS = 0 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_EISTR_INTERRUPT_STATUS_LEN = 44 ;
+
+static const uint8_t P9N2_PU_CME11_CME_LCL_EISTR_INTERRUPT_STATUS = 0 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_EISTR_INTERRUPT_STATUS_LEN = 44 ;
+
+static const uint8_t P9N2_PU_CME2_CME_LCL_EISTR_INTERRUPT_STATUS = 0 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_EISTR_INTERRUPT_STATUS_LEN = 44 ;
+
+static const uint8_t P9N2_PU_CME5_CME_LCL_EISTR_INTERRUPT_STATUS = 0 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_EISTR_INTERRUPT_STATUS_LEN = 44 ;
+
+static const uint8_t P9N2_PU_CME9_CME_LCL_EISTR_INTERRUPT_STATUS = 0 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_EISTR_INTERRUPT_STATUS_LEN = 44 ;
+
+static const uint8_t P9N2_PU_CME6_CME_LCL_EISTR_INTERRUPT_STATUS = 0 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_EISTR_INTERRUPT_STATUS_LEN = 44 ;
+
+static const uint8_t P9N2_PU_CME10_CME_LCL_EISTR_INTERRUPT_STATUS = 0 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_EISTR_INTERRUPT_STATUS_LEN = 44 ;
+
+static const uint8_t P9N2_PU_CME8_CME_LCL_EISTR_INTERRUPT_STATUS = 0 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_EISTR_INTERRUPT_STATUS_LEN = 44 ;
+
+static const uint8_t P9N2_PU_CME1_CME_LCL_EISTR_INTERRUPT_STATUS = 0 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_EISTR_INTERRUPT_STATUS_LEN = 44 ;
+
+static const uint8_t P9N2_PU_CME0_CME_LCL_EISTR_INTERRUPT_STATUS = 0 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_EISTR_INTERRUPT_STATUS_LEN = 44 ;
+
+static const uint8_t P9N2_PU_CME7_CME_LCL_EISTR_INTERRUPT_STATUS = 0 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_EISTR_INTERRUPT_STATUS_LEN = 44 ;
+
+static const uint8_t P9N2_PU_CME4_CME_LCL_EITR_INTERRUPT_TYPE = 0 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_EITR_INTERRUPT_TYPE_LEN = 44 ;
+
+static const uint8_t P9N2_PU_CME3_CME_LCL_EITR_INTERRUPT_TYPE = 0 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_EITR_INTERRUPT_TYPE_LEN = 44 ;
+
+static const uint8_t P9N2_PU_CME11_CME_LCL_EITR_INTERRUPT_TYPE = 0 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_EITR_INTERRUPT_TYPE_LEN = 44 ;
+
+static const uint8_t P9N2_PU_CME2_CME_LCL_EITR_INTERRUPT_TYPE = 0 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_EITR_INTERRUPT_TYPE_LEN = 44 ;
+
+static const uint8_t P9N2_PU_CME5_CME_LCL_EITR_INTERRUPT_TYPE = 0 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_EITR_INTERRUPT_TYPE_LEN = 44 ;
+
+static const uint8_t P9N2_PU_CME9_CME_LCL_EITR_INTERRUPT_TYPE = 0 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_EITR_INTERRUPT_TYPE_LEN = 44 ;
+
+static const uint8_t P9N2_PU_CME6_CME_LCL_EITR_INTERRUPT_TYPE = 0 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_EITR_INTERRUPT_TYPE_LEN = 44 ;
+
+static const uint8_t P9N2_PU_CME10_CME_LCL_EITR_INTERRUPT_TYPE = 0 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_EITR_INTERRUPT_TYPE_LEN = 44 ;
+
+static const uint8_t P9N2_PU_CME8_CME_LCL_EITR_INTERRUPT_TYPE = 0 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_EITR_INTERRUPT_TYPE_LEN = 44 ;
+
+static const uint8_t P9N2_PU_CME1_CME_LCL_EITR_INTERRUPT_TYPE = 0 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_EITR_INTERRUPT_TYPE_LEN = 44 ;
+
+static const uint8_t P9N2_PU_CME0_CME_LCL_EITR_INTERRUPT_TYPE = 0 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_EITR_INTERRUPT_TYPE_LEN = 44 ;
+
+static const uint8_t P9N2_PU_CME7_CME_LCL_EITR_INTERRUPT_TYPE = 0 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_EITR_INTERRUPT_TYPE_LEN = 44 ;
+
+static const uint8_t P9N2_PU_CME4_CME_LCL_ICCR_COMM_ACK = 0 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_ICCR_COMM_NACK = 1 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT = 5 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT_LEN = 3 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN = 9 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN_LEN = 3 ;
+
+static const uint8_t P9N2_PU_CME3_CME_LCL_ICCR_COMM_ACK = 0 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_ICCR_COMM_NACK = 1 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT = 5 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT_LEN = 3 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN = 9 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN_LEN = 3 ;
+
+static const uint8_t P9N2_PU_CME11_CME_LCL_ICCR_COMM_ACK = 0 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_ICCR_COMM_NACK = 1 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT = 5 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT_LEN = 3 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN = 9 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN_LEN = 3 ;
+
+static const uint8_t P9N2_PU_CME2_CME_LCL_ICCR_COMM_ACK = 0 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_ICCR_COMM_NACK = 1 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT = 5 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT_LEN = 3 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN = 9 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN_LEN = 3 ;
+
+static const uint8_t P9N2_PU_CME5_CME_LCL_ICCR_COMM_ACK = 0 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_ICCR_COMM_NACK = 1 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT = 5 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT_LEN = 3 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN = 9 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN_LEN = 3 ;
+
+static const uint8_t P9N2_PU_CME9_CME_LCL_ICCR_COMM_ACK = 0 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_ICCR_COMM_NACK = 1 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT = 5 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT_LEN = 3 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN = 9 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN_LEN = 3 ;
+
+static const uint8_t P9N2_PU_CME6_CME_LCL_ICCR_COMM_ACK = 0 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_ICCR_COMM_NACK = 1 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT = 5 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT_LEN = 3 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN = 9 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN_LEN = 3 ;
+
+static const uint8_t P9N2_PU_CME10_CME_LCL_ICCR_COMM_ACK = 0 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_ICCR_COMM_NACK = 1 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT = 5 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT_LEN = 3 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN = 9 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN_LEN = 3 ;
+
+static const uint8_t P9N2_PU_CME8_CME_LCL_ICCR_COMM_ACK = 0 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_ICCR_COMM_NACK = 1 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT = 5 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT_LEN = 3 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN = 9 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN_LEN = 3 ;
+
+static const uint8_t P9N2_PU_CME1_CME_LCL_ICCR_COMM_ACK = 0 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_ICCR_COMM_NACK = 1 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT = 5 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT_LEN = 3 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN = 9 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN_LEN = 3 ;
+
+static const uint8_t P9N2_PU_CME0_CME_LCL_ICCR_COMM_ACK = 0 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_ICCR_COMM_NACK = 1 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT = 5 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT_LEN = 3 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN = 9 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN_LEN = 3 ;
+
+static const uint8_t P9N2_PU_CME7_CME_LCL_ICCR_COMM_ACK = 0 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_ICCR_COMM_NACK = 1 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT = 5 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT_LEN = 3 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN = 9 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN_LEN = 3 ;
+
+static const uint8_t P9N2_PU_CME4_CME_LCL_ICRR_COMM_RECV = 0 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_ICRR_COMM_RECV_LEN = 32 ;
+
+static const uint8_t P9N2_PU_CME3_CME_LCL_ICRR_COMM_RECV = 0 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_ICRR_COMM_RECV_LEN = 32 ;
+
+static const uint8_t P9N2_PU_CME11_CME_LCL_ICRR_COMM_RECV = 0 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_ICRR_COMM_RECV_LEN = 32 ;
+
+static const uint8_t P9N2_PU_CME2_CME_LCL_ICRR_COMM_RECV = 0 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_ICRR_COMM_RECV_LEN = 32 ;
+
+static const uint8_t P9N2_PU_CME5_CME_LCL_ICRR_COMM_RECV = 0 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_ICRR_COMM_RECV_LEN = 32 ;
+
+static const uint8_t P9N2_PU_CME9_CME_LCL_ICRR_COMM_RECV = 0 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_ICRR_COMM_RECV_LEN = 32 ;
+
+static const uint8_t P9N2_PU_CME6_CME_LCL_ICRR_COMM_RECV = 0 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_ICRR_COMM_RECV_LEN = 32 ;
+
+static const uint8_t P9N2_PU_CME10_CME_LCL_ICRR_COMM_RECV = 0 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_ICRR_COMM_RECV_LEN = 32 ;
+
+static const uint8_t P9N2_PU_CME8_CME_LCL_ICRR_COMM_RECV = 0 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_ICRR_COMM_RECV_LEN = 32 ;
+
+static const uint8_t P9N2_PU_CME1_CME_LCL_ICRR_COMM_RECV = 0 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_ICRR_COMM_RECV_LEN = 32 ;
+
+static const uint8_t P9N2_PU_CME0_CME_LCL_ICRR_COMM_RECV = 0 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_ICRR_COMM_RECV_LEN = 32 ;
+
+static const uint8_t P9N2_PU_CME7_CME_LCL_ICRR_COMM_RECV = 0 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_ICRR_COMM_RECV_LEN = 32 ;
+
+static const uint8_t P9N2_PU_CME4_CME_LCL_ICSR_COMM_SEND = 0 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_ICSR_COMM_SEND_LEN = 32 ;
+
+static const uint8_t P9N2_PU_CME3_CME_LCL_ICSR_COMM_SEND = 0 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_ICSR_COMM_SEND_LEN = 32 ;
+
+static const uint8_t P9N2_PU_CME11_CME_LCL_ICSR_COMM_SEND = 0 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_ICSR_COMM_SEND_LEN = 32 ;
+
+static const uint8_t P9N2_PU_CME2_CME_LCL_ICSR_COMM_SEND = 0 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_ICSR_COMM_SEND_LEN = 32 ;
+
+static const uint8_t P9N2_PU_CME5_CME_LCL_ICSR_COMM_SEND = 0 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_ICSR_COMM_SEND_LEN = 32 ;
+
+static const uint8_t P9N2_PU_CME9_CME_LCL_ICSR_COMM_SEND = 0 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_ICSR_COMM_SEND_LEN = 32 ;
+
+static const uint8_t P9N2_PU_CME6_CME_LCL_ICSR_COMM_SEND = 0 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_ICSR_COMM_SEND_LEN = 32 ;
+
+static const uint8_t P9N2_PU_CME10_CME_LCL_ICSR_COMM_SEND = 0 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_ICSR_COMM_SEND_LEN = 32 ;
+
+static const uint8_t P9N2_PU_CME8_CME_LCL_ICSR_COMM_SEND = 0 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_ICSR_COMM_SEND_LEN = 32 ;
+
+static const uint8_t P9N2_PU_CME1_CME_LCL_ICSR_COMM_SEND = 0 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_ICSR_COMM_SEND_LEN = 32 ;
+
+static const uint8_t P9N2_PU_CME0_CME_LCL_ICSR_COMM_SEND = 0 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_ICSR_COMM_SEND_LEN = 32 ;
+
+static const uint8_t P9N2_PU_CME7_CME_LCL_ICSR_COMM_SEND = 0 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_ICSR_COMM_SEND_LEN = 32 ;
+
+static const uint8_t P9N2_PU_CME4_CME_LCL_PECESR0_PECE_C_N_T0 = 0 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_PECESR0_PECE_C_N_T0_LEN = 6 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_PECESR0_PECE_C_N_T1 = 8 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_PECESR0_PECE_C_N_T1_LEN = 6 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_PECESR0_PECE_C_N_T2 = 16 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_PECESR0_PECE_C_N_T2_LEN = 6 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_PECESR0_PECE_C_N_T3 = 24 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_PECESR0_PECE_C_N_T3_LEN = 6 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_PECESR0_USE_PECE = 32 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_PECESR0_USE_PECE_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME3_CME_LCL_PECESR0_PECE_C_N_T0 = 0 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_PECESR0_PECE_C_N_T0_LEN = 6 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_PECESR0_PECE_C_N_T1 = 8 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_PECESR0_PECE_C_N_T1_LEN = 6 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_PECESR0_PECE_C_N_T2 = 16 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_PECESR0_PECE_C_N_T2_LEN = 6 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_PECESR0_PECE_C_N_T3 = 24 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_PECESR0_PECE_C_N_T3_LEN = 6 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_PECESR0_USE_PECE = 32 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_PECESR0_USE_PECE_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME11_CME_LCL_PECESR0_PECE_C_N_T0 = 0 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_PECESR0_PECE_C_N_T0_LEN = 6 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_PECESR0_PECE_C_N_T1 = 8 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_PECESR0_PECE_C_N_T1_LEN = 6 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_PECESR0_PECE_C_N_T2 = 16 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_PECESR0_PECE_C_N_T2_LEN = 6 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_PECESR0_PECE_C_N_T3 = 24 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_PECESR0_PECE_C_N_T3_LEN = 6 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_PECESR0_USE_PECE = 32 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_PECESR0_USE_PECE_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME2_CME_LCL_PECESR0_PECE_C_N_T0 = 0 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_PECESR0_PECE_C_N_T0_LEN = 6 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_PECESR0_PECE_C_N_T1 = 8 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_PECESR0_PECE_C_N_T1_LEN = 6 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_PECESR0_PECE_C_N_T2 = 16 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_PECESR0_PECE_C_N_T2_LEN = 6 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_PECESR0_PECE_C_N_T3 = 24 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_PECESR0_PECE_C_N_T3_LEN = 6 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_PECESR0_USE_PECE = 32 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_PECESR0_USE_PECE_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME5_CME_LCL_PECESR0_PECE_C_N_T0 = 0 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_PECESR0_PECE_C_N_T0_LEN = 6 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_PECESR0_PECE_C_N_T1 = 8 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_PECESR0_PECE_C_N_T1_LEN = 6 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_PECESR0_PECE_C_N_T2 = 16 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_PECESR0_PECE_C_N_T2_LEN = 6 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_PECESR0_PECE_C_N_T3 = 24 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_PECESR0_PECE_C_N_T3_LEN = 6 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_PECESR0_USE_PECE = 32 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_PECESR0_USE_PECE_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME9_CME_LCL_PECESR0_PECE_C_N_T0 = 0 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_PECESR0_PECE_C_N_T0_LEN = 6 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_PECESR0_PECE_C_N_T1 = 8 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_PECESR0_PECE_C_N_T1_LEN = 6 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_PECESR0_PECE_C_N_T2 = 16 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_PECESR0_PECE_C_N_T2_LEN = 6 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_PECESR0_PECE_C_N_T3 = 24 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_PECESR0_PECE_C_N_T3_LEN = 6 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_PECESR0_USE_PECE = 32 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_PECESR0_USE_PECE_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME6_CME_LCL_PECESR0_PECE_C_N_T0 = 0 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_PECESR0_PECE_C_N_T0_LEN = 6 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_PECESR0_PECE_C_N_T1 = 8 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_PECESR0_PECE_C_N_T1_LEN = 6 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_PECESR0_PECE_C_N_T2 = 16 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_PECESR0_PECE_C_N_T2_LEN = 6 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_PECESR0_PECE_C_N_T3 = 24 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_PECESR0_PECE_C_N_T3_LEN = 6 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_PECESR0_USE_PECE = 32 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_PECESR0_USE_PECE_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME10_CME_LCL_PECESR0_PECE_C_N_T0 = 0 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_PECESR0_PECE_C_N_T0_LEN = 6 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_PECESR0_PECE_C_N_T1 = 8 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_PECESR0_PECE_C_N_T1_LEN = 6 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_PECESR0_PECE_C_N_T2 = 16 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_PECESR0_PECE_C_N_T2_LEN = 6 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_PECESR0_PECE_C_N_T3 = 24 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_PECESR0_PECE_C_N_T3_LEN = 6 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_PECESR0_USE_PECE = 32 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_PECESR0_USE_PECE_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME8_CME_LCL_PECESR0_PECE_C_N_T0 = 0 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_PECESR0_PECE_C_N_T0_LEN = 6 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_PECESR0_PECE_C_N_T1 = 8 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_PECESR0_PECE_C_N_T1_LEN = 6 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_PECESR0_PECE_C_N_T2 = 16 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_PECESR0_PECE_C_N_T2_LEN = 6 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_PECESR0_PECE_C_N_T3 = 24 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_PECESR0_PECE_C_N_T3_LEN = 6 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_PECESR0_USE_PECE = 32 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_PECESR0_USE_PECE_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME1_CME_LCL_PECESR0_PECE_C_N_T0 = 0 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_PECESR0_PECE_C_N_T0_LEN = 6 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_PECESR0_PECE_C_N_T1 = 8 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_PECESR0_PECE_C_N_T1_LEN = 6 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_PECESR0_PECE_C_N_T2 = 16 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_PECESR0_PECE_C_N_T2_LEN = 6 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_PECESR0_PECE_C_N_T3 = 24 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_PECESR0_PECE_C_N_T3_LEN = 6 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_PECESR0_USE_PECE = 32 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_PECESR0_USE_PECE_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME0_CME_LCL_PECESR0_PECE_C_N_T0 = 0 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_PECESR0_PECE_C_N_T0_LEN = 6 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_PECESR0_PECE_C_N_T1 = 8 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_PECESR0_PECE_C_N_T1_LEN = 6 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_PECESR0_PECE_C_N_T2 = 16 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_PECESR0_PECE_C_N_T2_LEN = 6 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_PECESR0_PECE_C_N_T3 = 24 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_PECESR0_PECE_C_N_T3_LEN = 6 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_PECESR0_USE_PECE = 32 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_PECESR0_USE_PECE_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME7_CME_LCL_PECESR0_PECE_C_N_T0 = 0 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_PECESR0_PECE_C_N_T0_LEN = 6 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_PECESR0_PECE_C_N_T1 = 8 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_PECESR0_PECE_C_N_T1_LEN = 6 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_PECESR0_PECE_C_N_T2 = 16 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_PECESR0_PECE_C_N_T2_LEN = 6 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_PECESR0_PECE_C_N_T3 = 24 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_PECESR0_PECE_C_N_T3_LEN = 6 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_PECESR0_USE_PECE = 32 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_PECESR0_USE_PECE_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME4_CME_LCL_PECESR1_PECE_C_N_T0 = 0 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_PECESR1_PECE_C_N_T0_LEN = 6 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_PECESR1_PECE_C_N_T1 = 8 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_PECESR1_PECE_C_N_T1_LEN = 6 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_PECESR1_PECE_C_N_T2 = 16 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_PECESR1_PECE_C_N_T2_LEN = 6 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_PECESR1_PECE_C_N_T3 = 24 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_PECESR1_PECE_C_N_T3_LEN = 6 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_PECESR1_USE_PECE = 32 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_PECESR1_USE_PECE_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME3_CME_LCL_PECESR1_PECE_C_N_T0 = 0 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_PECESR1_PECE_C_N_T0_LEN = 6 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_PECESR1_PECE_C_N_T1 = 8 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_PECESR1_PECE_C_N_T1_LEN = 6 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_PECESR1_PECE_C_N_T2 = 16 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_PECESR1_PECE_C_N_T2_LEN = 6 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_PECESR1_PECE_C_N_T3 = 24 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_PECESR1_PECE_C_N_T3_LEN = 6 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_PECESR1_USE_PECE = 32 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_PECESR1_USE_PECE_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME11_CME_LCL_PECESR1_PECE_C_N_T0 = 0 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_PECESR1_PECE_C_N_T0_LEN = 6 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_PECESR1_PECE_C_N_T1 = 8 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_PECESR1_PECE_C_N_T1_LEN = 6 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_PECESR1_PECE_C_N_T2 = 16 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_PECESR1_PECE_C_N_T2_LEN = 6 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_PECESR1_PECE_C_N_T3 = 24 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_PECESR1_PECE_C_N_T3_LEN = 6 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_PECESR1_USE_PECE = 32 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_PECESR1_USE_PECE_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME2_CME_LCL_PECESR1_PECE_C_N_T0 = 0 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_PECESR1_PECE_C_N_T0_LEN = 6 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_PECESR1_PECE_C_N_T1 = 8 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_PECESR1_PECE_C_N_T1_LEN = 6 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_PECESR1_PECE_C_N_T2 = 16 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_PECESR1_PECE_C_N_T2_LEN = 6 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_PECESR1_PECE_C_N_T3 = 24 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_PECESR1_PECE_C_N_T3_LEN = 6 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_PECESR1_USE_PECE = 32 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_PECESR1_USE_PECE_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME5_CME_LCL_PECESR1_PECE_C_N_T0 = 0 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_PECESR1_PECE_C_N_T0_LEN = 6 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_PECESR1_PECE_C_N_T1 = 8 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_PECESR1_PECE_C_N_T1_LEN = 6 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_PECESR1_PECE_C_N_T2 = 16 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_PECESR1_PECE_C_N_T2_LEN = 6 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_PECESR1_PECE_C_N_T3 = 24 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_PECESR1_PECE_C_N_T3_LEN = 6 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_PECESR1_USE_PECE = 32 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_PECESR1_USE_PECE_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME9_CME_LCL_PECESR1_PECE_C_N_T0 = 0 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_PECESR1_PECE_C_N_T0_LEN = 6 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_PECESR1_PECE_C_N_T1 = 8 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_PECESR1_PECE_C_N_T1_LEN = 6 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_PECESR1_PECE_C_N_T2 = 16 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_PECESR1_PECE_C_N_T2_LEN = 6 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_PECESR1_PECE_C_N_T3 = 24 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_PECESR1_PECE_C_N_T3_LEN = 6 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_PECESR1_USE_PECE = 32 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_PECESR1_USE_PECE_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME6_CME_LCL_PECESR1_PECE_C_N_T0 = 0 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_PECESR1_PECE_C_N_T0_LEN = 6 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_PECESR1_PECE_C_N_T1 = 8 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_PECESR1_PECE_C_N_T1_LEN = 6 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_PECESR1_PECE_C_N_T2 = 16 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_PECESR1_PECE_C_N_T2_LEN = 6 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_PECESR1_PECE_C_N_T3 = 24 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_PECESR1_PECE_C_N_T3_LEN = 6 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_PECESR1_USE_PECE = 32 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_PECESR1_USE_PECE_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME10_CME_LCL_PECESR1_PECE_C_N_T0 = 0 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_PECESR1_PECE_C_N_T0_LEN = 6 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_PECESR1_PECE_C_N_T1 = 8 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_PECESR1_PECE_C_N_T1_LEN = 6 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_PECESR1_PECE_C_N_T2 = 16 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_PECESR1_PECE_C_N_T2_LEN = 6 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_PECESR1_PECE_C_N_T3 = 24 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_PECESR1_PECE_C_N_T3_LEN = 6 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_PECESR1_USE_PECE = 32 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_PECESR1_USE_PECE_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME8_CME_LCL_PECESR1_PECE_C_N_T0 = 0 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_PECESR1_PECE_C_N_T0_LEN = 6 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_PECESR1_PECE_C_N_T1 = 8 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_PECESR1_PECE_C_N_T1_LEN = 6 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_PECESR1_PECE_C_N_T2 = 16 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_PECESR1_PECE_C_N_T2_LEN = 6 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_PECESR1_PECE_C_N_T3 = 24 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_PECESR1_PECE_C_N_T3_LEN = 6 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_PECESR1_USE_PECE = 32 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_PECESR1_USE_PECE_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME1_CME_LCL_PECESR1_PECE_C_N_T0 = 0 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_PECESR1_PECE_C_N_T0_LEN = 6 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_PECESR1_PECE_C_N_T1 = 8 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_PECESR1_PECE_C_N_T1_LEN = 6 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_PECESR1_PECE_C_N_T2 = 16 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_PECESR1_PECE_C_N_T2_LEN = 6 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_PECESR1_PECE_C_N_T3 = 24 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_PECESR1_PECE_C_N_T3_LEN = 6 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_PECESR1_USE_PECE = 32 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_PECESR1_USE_PECE_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME0_CME_LCL_PECESR1_PECE_C_N_T0 = 0 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_PECESR1_PECE_C_N_T0_LEN = 6 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_PECESR1_PECE_C_N_T1 = 8 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_PECESR1_PECE_C_N_T1_LEN = 6 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_PECESR1_PECE_C_N_T2 = 16 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_PECESR1_PECE_C_N_T2_LEN = 6 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_PECESR1_PECE_C_N_T3 = 24 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_PECESR1_PECE_C_N_T3_LEN = 6 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_PECESR1_USE_PECE = 32 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_PECESR1_USE_PECE_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME7_CME_LCL_PECESR1_PECE_C_N_T0 = 0 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_PECESR1_PECE_C_N_T0_LEN = 6 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_PECESR1_PECE_C_N_T1 = 8 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_PECESR1_PECE_C_N_T1_LEN = 6 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_PECESR1_PECE_C_N_T2 = 16 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_PECESR1_PECE_C_N_T2_LEN = 6 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_PECESR1_PECE_C_N_T3 = 24 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_PECESR1_PECE_C_N_T3_LEN = 6 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_PECESR1_USE_PECE = 32 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_PECESR1_USE_PECE_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_PM_ENTRY_ACK_C0_ACTUAL = 0 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_PM_ENTRY_ACK_C1_ACTUAL = 1 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C0_ACTUAL = 2 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C1_ACTUAL = 3 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_PM_EXIT_C0_ACTUAL = 4 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_PM_EXIT_C1_ACTUAL = 5 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_RESERVED_6_8 = 6 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_RESERVED_6_8_LEN = 3 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_FUSED_CORE_MODE = 9 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_PCBMUX_GRANT_C0 = 10 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_PCBMUX_GRANT_C1 = 11 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_PCB_RSP_OOB_0123_C0 = 12 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_PCB_RSP_OOB_0123_C0_LEN = 4 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL = 16 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL = 17 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_RESERVED_18_19 = 18 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_RESERVED_18_19_LEN = 2 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C0 = 20 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C0_LEN = 4 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C1 = 24 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C1_LEN = 4 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_RESERVED_28_29 = 28 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_RESERVED_28_29_LEN = 2 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1 = 30 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN = 2 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_PC_UNMASKED_ATTN_C0 = 32 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_PC_UNMASKED_ATTN_C1 = 33 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_PM_STATE_ACTIVE_C0 = 34 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_PM_STATE_ACTIVE_C1 = 35 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_PM_STATE_C0 = 36 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_PM_STATE_C0_LEN = 4 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_PM_STATE_C1 = 40 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_PM_STATE_C1_LEN = 4 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_PM_STATE_ALL_HV_C0 = 44 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_PM_STATE_ALL_HV_C1 = 45 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_PC_INSTR_RUNNING_C0 = 46 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_PC_INSTR_RUNNING_C1 = 47 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_PC_NON_HV_RUNNING_C0 = 48 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN = 4 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_PC_NON_HV_RUNNING_C1 = 52 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN = 4 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0 = 56 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1 = 57 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_PCB_RSP_OOB_9_C0 = 58 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_PCB_RSP_OOB_9_C1 = 59 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_PCB_RSP_OOB_0123_C1 = 60 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_SISR_PCB_RSP_OOB_0123_C1_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_PM_ENTRY_ACK_C0_ACTUAL = 0 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_PM_ENTRY_ACK_C1_ACTUAL = 1 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C0_ACTUAL = 2 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C1_ACTUAL = 3 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_PM_EXIT_C0_ACTUAL = 4 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_PM_EXIT_C1_ACTUAL = 5 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_RESERVED_6_8 = 6 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_RESERVED_6_8_LEN = 3 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_FUSED_CORE_MODE = 9 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_PCBMUX_GRANT_C0 = 10 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_PCBMUX_GRANT_C1 = 11 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_PCB_RSP_OOB_0123_C0 = 12 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_PCB_RSP_OOB_0123_C0_LEN = 4 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL = 16 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL = 17 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_RESERVED_18_19 = 18 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_RESERVED_18_19_LEN = 2 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C0 = 20 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C0_LEN = 4 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C1 = 24 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C1_LEN = 4 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_RESERVED_28_29 = 28 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_RESERVED_28_29_LEN = 2 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1 = 30 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN = 2 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_PC_UNMASKED_ATTN_C0 = 32 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_PC_UNMASKED_ATTN_C1 = 33 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_PM_STATE_ACTIVE_C0 = 34 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_PM_STATE_ACTIVE_C1 = 35 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_PM_STATE_C0 = 36 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_PM_STATE_C0_LEN = 4 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_PM_STATE_C1 = 40 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_PM_STATE_C1_LEN = 4 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_PM_STATE_ALL_HV_C0 = 44 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_PM_STATE_ALL_HV_C1 = 45 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_PC_INSTR_RUNNING_C0 = 46 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_PC_INSTR_RUNNING_C1 = 47 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_PC_NON_HV_RUNNING_C0 = 48 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN = 4 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_PC_NON_HV_RUNNING_C1 = 52 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN = 4 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0 = 56 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1 = 57 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_PCB_RSP_OOB_9_C0 = 58 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_PCB_RSP_OOB_9_C1 = 59 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_PCB_RSP_OOB_0123_C1 = 60 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_SISR_PCB_RSP_OOB_0123_C1_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_PM_ENTRY_ACK_C0_ACTUAL = 0 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_PM_ENTRY_ACK_C1_ACTUAL = 1 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C0_ACTUAL = 2 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C1_ACTUAL = 3 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_PM_EXIT_C0_ACTUAL = 4 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_PM_EXIT_C1_ACTUAL = 5 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_RESERVED_6_8 = 6 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_RESERVED_6_8_LEN = 3 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_FUSED_CORE_MODE = 9 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_PCBMUX_GRANT_C0 = 10 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_PCBMUX_GRANT_C1 = 11 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_PCB_RSP_OOB_0123_C0 = 12 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_PCB_RSP_OOB_0123_C0_LEN = 4 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL = 16 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL = 17 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_RESERVED_18_19 = 18 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_RESERVED_18_19_LEN = 2 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C0 = 20 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C0_LEN = 4 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C1 = 24 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C1_LEN = 4 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_RESERVED_28_29 = 28 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_RESERVED_28_29_LEN = 2 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1 = 30 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN = 2 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_PC_UNMASKED_ATTN_C0 = 32 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_PC_UNMASKED_ATTN_C1 = 33 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_PM_STATE_ACTIVE_C0 = 34 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_PM_STATE_ACTIVE_C1 = 35 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_PM_STATE_C0 = 36 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_PM_STATE_C0_LEN = 4 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_PM_STATE_C1 = 40 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_PM_STATE_C1_LEN = 4 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_PM_STATE_ALL_HV_C0 = 44 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_PM_STATE_ALL_HV_C1 = 45 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_PC_INSTR_RUNNING_C0 = 46 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_PC_INSTR_RUNNING_C1 = 47 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_PC_NON_HV_RUNNING_C0 = 48 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN = 4 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_PC_NON_HV_RUNNING_C1 = 52 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN = 4 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0 = 56 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1 = 57 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_PCB_RSP_OOB_9_C0 = 58 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_PCB_RSP_OOB_9_C1 = 59 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_PCB_RSP_OOB_0123_C1 = 60 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_SISR_PCB_RSP_OOB_0123_C1_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_PM_ENTRY_ACK_C0_ACTUAL = 0 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_PM_ENTRY_ACK_C1_ACTUAL = 1 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C0_ACTUAL = 2 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C1_ACTUAL = 3 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_PM_EXIT_C0_ACTUAL = 4 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_PM_EXIT_C1_ACTUAL = 5 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_RESERVED_6_8 = 6 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_RESERVED_6_8_LEN = 3 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_FUSED_CORE_MODE = 9 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_PCBMUX_GRANT_C0 = 10 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_PCBMUX_GRANT_C1 = 11 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_PCB_RSP_OOB_0123_C0 = 12 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_PCB_RSP_OOB_0123_C0_LEN = 4 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL = 16 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL = 17 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_RESERVED_18_19 = 18 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_RESERVED_18_19_LEN = 2 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C0 = 20 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C0_LEN = 4 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C1 = 24 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C1_LEN = 4 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_RESERVED_28_29 = 28 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_RESERVED_28_29_LEN = 2 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1 = 30 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN = 2 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_PC_UNMASKED_ATTN_C0 = 32 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_PC_UNMASKED_ATTN_C1 = 33 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_PM_STATE_ACTIVE_C0 = 34 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_PM_STATE_ACTIVE_C1 = 35 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_PM_STATE_C0 = 36 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_PM_STATE_C0_LEN = 4 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_PM_STATE_C1 = 40 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_PM_STATE_C1_LEN = 4 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_PM_STATE_ALL_HV_C0 = 44 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_PM_STATE_ALL_HV_C1 = 45 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_PC_INSTR_RUNNING_C0 = 46 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_PC_INSTR_RUNNING_C1 = 47 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_PC_NON_HV_RUNNING_C0 = 48 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN = 4 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_PC_NON_HV_RUNNING_C1 = 52 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN = 4 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0 = 56 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1 = 57 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_PCB_RSP_OOB_9_C0 = 58 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_PCB_RSP_OOB_9_C1 = 59 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_PCB_RSP_OOB_0123_C1 = 60 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_SISR_PCB_RSP_OOB_0123_C1_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_PM_ENTRY_ACK_C0_ACTUAL = 0 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_PM_ENTRY_ACK_C1_ACTUAL = 1 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C0_ACTUAL = 2 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C1_ACTUAL = 3 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_PM_EXIT_C0_ACTUAL = 4 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_PM_EXIT_C1_ACTUAL = 5 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_RESERVED_6_8 = 6 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_RESERVED_6_8_LEN = 3 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_FUSED_CORE_MODE = 9 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_PCBMUX_GRANT_C0 = 10 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_PCBMUX_GRANT_C1 = 11 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_PCB_RSP_OOB_0123_C0 = 12 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_PCB_RSP_OOB_0123_C0_LEN = 4 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL = 16 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL = 17 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_RESERVED_18_19 = 18 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_RESERVED_18_19_LEN = 2 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C0 = 20 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C0_LEN = 4 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C1 = 24 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C1_LEN = 4 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_RESERVED_28_29 = 28 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_RESERVED_28_29_LEN = 2 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1 = 30 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN = 2 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_PC_UNMASKED_ATTN_C0 = 32 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_PC_UNMASKED_ATTN_C1 = 33 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_PM_STATE_ACTIVE_C0 = 34 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_PM_STATE_ACTIVE_C1 = 35 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_PM_STATE_C0 = 36 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_PM_STATE_C0_LEN = 4 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_PM_STATE_C1 = 40 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_PM_STATE_C1_LEN = 4 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_PM_STATE_ALL_HV_C0 = 44 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_PM_STATE_ALL_HV_C1 = 45 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_PC_INSTR_RUNNING_C0 = 46 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_PC_INSTR_RUNNING_C1 = 47 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_PC_NON_HV_RUNNING_C0 = 48 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN = 4 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_PC_NON_HV_RUNNING_C1 = 52 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN = 4 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0 = 56 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1 = 57 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_PCB_RSP_OOB_9_C0 = 58 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_PCB_RSP_OOB_9_C1 = 59 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_PCB_RSP_OOB_0123_C1 = 60 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_SISR_PCB_RSP_OOB_0123_C1_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_PM_ENTRY_ACK_C0_ACTUAL = 0 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_PM_ENTRY_ACK_C1_ACTUAL = 1 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C0_ACTUAL = 2 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C1_ACTUAL = 3 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_PM_EXIT_C0_ACTUAL = 4 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_PM_EXIT_C1_ACTUAL = 5 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_RESERVED_6_8 = 6 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_RESERVED_6_8_LEN = 3 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_FUSED_CORE_MODE = 9 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_PCBMUX_GRANT_C0 = 10 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_PCBMUX_GRANT_C1 = 11 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_PCB_RSP_OOB_0123_C0 = 12 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_PCB_RSP_OOB_0123_C0_LEN = 4 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL = 16 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL = 17 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_RESERVED_18_19 = 18 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_RESERVED_18_19_LEN = 2 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C0 = 20 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C0_LEN = 4 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C1 = 24 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C1_LEN = 4 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_RESERVED_28_29 = 28 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_RESERVED_28_29_LEN = 2 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1 = 30 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN = 2 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_PC_UNMASKED_ATTN_C0 = 32 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_PC_UNMASKED_ATTN_C1 = 33 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_PM_STATE_ACTIVE_C0 = 34 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_PM_STATE_ACTIVE_C1 = 35 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_PM_STATE_C0 = 36 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_PM_STATE_C0_LEN = 4 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_PM_STATE_C1 = 40 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_PM_STATE_C1_LEN = 4 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_PM_STATE_ALL_HV_C0 = 44 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_PM_STATE_ALL_HV_C1 = 45 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_PC_INSTR_RUNNING_C0 = 46 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_PC_INSTR_RUNNING_C1 = 47 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_PC_NON_HV_RUNNING_C0 = 48 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN = 4 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_PC_NON_HV_RUNNING_C1 = 52 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN = 4 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0 = 56 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1 = 57 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_PCB_RSP_OOB_9_C0 = 58 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_PCB_RSP_OOB_9_C1 = 59 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_PCB_RSP_OOB_0123_C1 = 60 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_SISR_PCB_RSP_OOB_0123_C1_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_PM_ENTRY_ACK_C0_ACTUAL = 0 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_PM_ENTRY_ACK_C1_ACTUAL = 1 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C0_ACTUAL = 2 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C1_ACTUAL = 3 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_PM_EXIT_C0_ACTUAL = 4 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_PM_EXIT_C1_ACTUAL = 5 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_RESERVED_6_8 = 6 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_RESERVED_6_8_LEN = 3 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_FUSED_CORE_MODE = 9 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_PCBMUX_GRANT_C0 = 10 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_PCBMUX_GRANT_C1 = 11 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_PCB_RSP_OOB_0123_C0 = 12 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_PCB_RSP_OOB_0123_C0_LEN = 4 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL = 16 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL = 17 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_RESERVED_18_19 = 18 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_RESERVED_18_19_LEN = 2 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C0 = 20 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C0_LEN = 4 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C1 = 24 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C1_LEN = 4 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_RESERVED_28_29 = 28 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_RESERVED_28_29_LEN = 2 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1 = 30 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN = 2 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_PC_UNMASKED_ATTN_C0 = 32 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_PC_UNMASKED_ATTN_C1 = 33 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_PM_STATE_ACTIVE_C0 = 34 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_PM_STATE_ACTIVE_C1 = 35 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_PM_STATE_C0 = 36 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_PM_STATE_C0_LEN = 4 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_PM_STATE_C1 = 40 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_PM_STATE_C1_LEN = 4 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_PM_STATE_ALL_HV_C0 = 44 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_PM_STATE_ALL_HV_C1 = 45 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_PC_INSTR_RUNNING_C0 = 46 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_PC_INSTR_RUNNING_C1 = 47 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_PC_NON_HV_RUNNING_C0 = 48 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN = 4 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_PC_NON_HV_RUNNING_C1 = 52 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN = 4 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0 = 56 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1 = 57 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_PCB_RSP_OOB_9_C0 = 58 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_PCB_RSP_OOB_9_C1 = 59 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_PCB_RSP_OOB_0123_C1 = 60 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_SISR_PCB_RSP_OOB_0123_C1_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_PM_ENTRY_ACK_C0_ACTUAL = 0 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_PM_ENTRY_ACK_C1_ACTUAL = 1 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C0_ACTUAL = 2 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C1_ACTUAL = 3 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_PM_EXIT_C0_ACTUAL = 4 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_PM_EXIT_C1_ACTUAL = 5 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_RESERVED_6_8 = 6 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_RESERVED_6_8_LEN = 3 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_FUSED_CORE_MODE = 9 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_PCBMUX_GRANT_C0 = 10 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_PCBMUX_GRANT_C1 = 11 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_PCB_RSP_OOB_0123_C0 = 12 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_PCB_RSP_OOB_0123_C0_LEN = 4 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL = 16 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL = 17 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_RESERVED_18_19 = 18 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_RESERVED_18_19_LEN = 2 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C0 = 20 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C0_LEN = 4 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C1 = 24 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C1_LEN = 4 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_RESERVED_28_29 = 28 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_RESERVED_28_29_LEN = 2 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1 = 30 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN = 2 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_PC_UNMASKED_ATTN_C0 = 32 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_PC_UNMASKED_ATTN_C1 = 33 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_PM_STATE_ACTIVE_C0 = 34 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_PM_STATE_ACTIVE_C1 = 35 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_PM_STATE_C0 = 36 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_PM_STATE_C0_LEN = 4 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_PM_STATE_C1 = 40 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_PM_STATE_C1_LEN = 4 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_PM_STATE_ALL_HV_C0 = 44 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_PM_STATE_ALL_HV_C1 = 45 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_PC_INSTR_RUNNING_C0 = 46 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_PC_INSTR_RUNNING_C1 = 47 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_PC_NON_HV_RUNNING_C0 = 48 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN = 4 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_PC_NON_HV_RUNNING_C1 = 52 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN = 4 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0 = 56 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1 = 57 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_PCB_RSP_OOB_9_C0 = 58 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_PCB_RSP_OOB_9_C1 = 59 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_PCB_RSP_OOB_0123_C1 = 60 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_SISR_PCB_RSP_OOB_0123_C1_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_PM_ENTRY_ACK_C0_ACTUAL = 0 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_PM_ENTRY_ACK_C1_ACTUAL = 1 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C0_ACTUAL = 2 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C1_ACTUAL = 3 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_PM_EXIT_C0_ACTUAL = 4 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_PM_EXIT_C1_ACTUAL = 5 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_RESERVED_6_8 = 6 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_RESERVED_6_8_LEN = 3 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_FUSED_CORE_MODE = 9 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_PCBMUX_GRANT_C0 = 10 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_PCBMUX_GRANT_C1 = 11 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_PCB_RSP_OOB_0123_C0 = 12 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_PCB_RSP_OOB_0123_C0_LEN = 4 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL = 16 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL = 17 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_RESERVED_18_19 = 18 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_RESERVED_18_19_LEN = 2 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C0 = 20 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C0_LEN = 4 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C1 = 24 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C1_LEN = 4 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_RESERVED_28_29 = 28 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_RESERVED_28_29_LEN = 2 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1 = 30 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN = 2 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_PC_UNMASKED_ATTN_C0 = 32 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_PC_UNMASKED_ATTN_C1 = 33 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_PM_STATE_ACTIVE_C0 = 34 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_PM_STATE_ACTIVE_C1 = 35 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_PM_STATE_C0 = 36 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_PM_STATE_C0_LEN = 4 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_PM_STATE_C1 = 40 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_PM_STATE_C1_LEN = 4 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_PM_STATE_ALL_HV_C0 = 44 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_PM_STATE_ALL_HV_C1 = 45 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_PC_INSTR_RUNNING_C0 = 46 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_PC_INSTR_RUNNING_C1 = 47 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_PC_NON_HV_RUNNING_C0 = 48 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN = 4 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_PC_NON_HV_RUNNING_C1 = 52 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN = 4 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0 = 56 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1 = 57 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_PCB_RSP_OOB_9_C0 = 58 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_PCB_RSP_OOB_9_C1 = 59 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_PCB_RSP_OOB_0123_C1 = 60 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_SISR_PCB_RSP_OOB_0123_C1_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_PM_ENTRY_ACK_C0_ACTUAL = 0 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_PM_ENTRY_ACK_C1_ACTUAL = 1 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C0_ACTUAL = 2 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C1_ACTUAL = 3 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_PM_EXIT_C0_ACTUAL = 4 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_PM_EXIT_C1_ACTUAL = 5 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_RESERVED_6_8 = 6 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_RESERVED_6_8_LEN = 3 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_FUSED_CORE_MODE = 9 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_PCBMUX_GRANT_C0 = 10 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_PCBMUX_GRANT_C1 = 11 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_PCB_RSP_OOB_0123_C0 = 12 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_PCB_RSP_OOB_0123_C0_LEN = 4 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL = 16 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL = 17 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_RESERVED_18_19 = 18 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_RESERVED_18_19_LEN = 2 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C0 = 20 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C0_LEN = 4 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C1 = 24 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C1_LEN = 4 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_RESERVED_28_29 = 28 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_RESERVED_28_29_LEN = 2 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1 = 30 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN = 2 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_PC_UNMASKED_ATTN_C0 = 32 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_PC_UNMASKED_ATTN_C1 = 33 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_PM_STATE_ACTIVE_C0 = 34 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_PM_STATE_ACTIVE_C1 = 35 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_PM_STATE_C0 = 36 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_PM_STATE_C0_LEN = 4 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_PM_STATE_C1 = 40 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_PM_STATE_C1_LEN = 4 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_PM_STATE_ALL_HV_C0 = 44 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_PM_STATE_ALL_HV_C1 = 45 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_PC_INSTR_RUNNING_C0 = 46 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_PC_INSTR_RUNNING_C1 = 47 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_PC_NON_HV_RUNNING_C0 = 48 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN = 4 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_PC_NON_HV_RUNNING_C1 = 52 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN = 4 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0 = 56 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1 = 57 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_PCB_RSP_OOB_9_C0 = 58 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_PCB_RSP_OOB_9_C1 = 59 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_PCB_RSP_OOB_0123_C1 = 60 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_SISR_PCB_RSP_OOB_0123_C1_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_PM_ENTRY_ACK_C0_ACTUAL = 0 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_PM_ENTRY_ACK_C1_ACTUAL = 1 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C0_ACTUAL = 2 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C1_ACTUAL = 3 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_PM_EXIT_C0_ACTUAL = 4 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_PM_EXIT_C1_ACTUAL = 5 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_RESERVED_6_8 = 6 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_RESERVED_6_8_LEN = 3 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_FUSED_CORE_MODE = 9 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_PCBMUX_GRANT_C0 = 10 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_PCBMUX_GRANT_C1 = 11 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_PCB_RSP_OOB_0123_C0 = 12 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_PCB_RSP_OOB_0123_C0_LEN = 4 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL = 16 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL = 17 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_RESERVED_18_19 = 18 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_RESERVED_18_19_LEN = 2 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C0 = 20 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C0_LEN = 4 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C1 = 24 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C1_LEN = 4 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_RESERVED_28_29 = 28 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_RESERVED_28_29_LEN = 2 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1 = 30 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN = 2 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_PC_UNMASKED_ATTN_C0 = 32 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_PC_UNMASKED_ATTN_C1 = 33 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_PM_STATE_ACTIVE_C0 = 34 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_PM_STATE_ACTIVE_C1 = 35 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_PM_STATE_C0 = 36 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_PM_STATE_C0_LEN = 4 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_PM_STATE_C1 = 40 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_PM_STATE_C1_LEN = 4 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_PM_STATE_ALL_HV_C0 = 44 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_PM_STATE_ALL_HV_C1 = 45 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_PC_INSTR_RUNNING_C0 = 46 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_PC_INSTR_RUNNING_C1 = 47 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_PC_NON_HV_RUNNING_C0 = 48 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN = 4 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_PC_NON_HV_RUNNING_C1 = 52 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN = 4 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0 = 56 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1 = 57 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_PCB_RSP_OOB_9_C0 = 58 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_PCB_RSP_OOB_9_C1 = 59 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_PCB_RSP_OOB_0123_C1 = 60 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_SISR_PCB_RSP_OOB_0123_C1_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_PM_ENTRY_ACK_C0_ACTUAL = 0 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_PM_ENTRY_ACK_C1_ACTUAL = 1 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C0_ACTUAL = 2 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C1_ACTUAL = 3 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_PM_EXIT_C0_ACTUAL = 4 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_PM_EXIT_C1_ACTUAL = 5 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_RESERVED_6_8 = 6 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_RESERVED_6_8_LEN = 3 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_FUSED_CORE_MODE = 9 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_PCBMUX_GRANT_C0 = 10 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_PCBMUX_GRANT_C1 = 11 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_PCB_RSP_OOB_0123_C0 = 12 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_PCB_RSP_OOB_0123_C0_LEN = 4 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL = 16 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL = 17 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_RESERVED_18_19 = 18 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_RESERVED_18_19_LEN = 2 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C0 = 20 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C0_LEN = 4 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C1 = 24 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C1_LEN = 4 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_RESERVED_28_29 = 28 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_RESERVED_28_29_LEN = 2 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1 = 30 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN = 2 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_PC_UNMASKED_ATTN_C0 = 32 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_PC_UNMASKED_ATTN_C1 = 33 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_PM_STATE_ACTIVE_C0 = 34 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_PM_STATE_ACTIVE_C1 = 35 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_PM_STATE_C0 = 36 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_PM_STATE_C0_LEN = 4 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_PM_STATE_C1 = 40 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_PM_STATE_C1_LEN = 4 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_PM_STATE_ALL_HV_C0 = 44 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_PM_STATE_ALL_HV_C1 = 45 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_PC_INSTR_RUNNING_C0 = 46 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_PC_INSTR_RUNNING_C1 = 47 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_PC_NON_HV_RUNNING_C0 = 48 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN = 4 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_PC_NON_HV_RUNNING_C1 = 52 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN = 4 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0 = 56 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1 = 57 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_PCB_RSP_OOB_9_C0 = 58 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_PCB_RSP_OOB_9_C1 = 59 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_PCB_RSP_OOB_0123_C1 = 60 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_SISR_PCB_RSP_OOB_0123_C1_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME4_CME_LCL_TSEL_FIT_SEL = 0 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_TSEL_FIT_SEL_LEN = 4 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_TSEL_WATCHDOG_SEL = 4 ;
+static const uint8_t P9N2_PU_CME4_CME_LCL_TSEL_WATCHDOG_SEL_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME3_CME_LCL_TSEL_FIT_SEL = 0 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_TSEL_FIT_SEL_LEN = 4 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_TSEL_WATCHDOG_SEL = 4 ;
+static const uint8_t P9N2_PU_CME3_CME_LCL_TSEL_WATCHDOG_SEL_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME11_CME_LCL_TSEL_FIT_SEL = 0 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_TSEL_FIT_SEL_LEN = 4 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_TSEL_WATCHDOG_SEL = 4 ;
+static const uint8_t P9N2_PU_CME11_CME_LCL_TSEL_WATCHDOG_SEL_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME2_CME_LCL_TSEL_FIT_SEL = 0 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_TSEL_FIT_SEL_LEN = 4 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_TSEL_WATCHDOG_SEL = 4 ;
+static const uint8_t P9N2_PU_CME2_CME_LCL_TSEL_WATCHDOG_SEL_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME5_CME_LCL_TSEL_FIT_SEL = 0 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_TSEL_FIT_SEL_LEN = 4 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_TSEL_WATCHDOG_SEL = 4 ;
+static const uint8_t P9N2_PU_CME5_CME_LCL_TSEL_WATCHDOG_SEL_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME9_CME_LCL_TSEL_FIT_SEL = 0 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_TSEL_FIT_SEL_LEN = 4 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_TSEL_WATCHDOG_SEL = 4 ;
+static const uint8_t P9N2_PU_CME9_CME_LCL_TSEL_WATCHDOG_SEL_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME6_CME_LCL_TSEL_FIT_SEL = 0 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_TSEL_FIT_SEL_LEN = 4 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_TSEL_WATCHDOG_SEL = 4 ;
+static const uint8_t P9N2_PU_CME6_CME_LCL_TSEL_WATCHDOG_SEL_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME10_CME_LCL_TSEL_FIT_SEL = 0 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_TSEL_FIT_SEL_LEN = 4 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_TSEL_WATCHDOG_SEL = 4 ;
+static const uint8_t P9N2_PU_CME10_CME_LCL_TSEL_WATCHDOG_SEL_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME8_CME_LCL_TSEL_FIT_SEL = 0 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_TSEL_FIT_SEL_LEN = 4 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_TSEL_WATCHDOG_SEL = 4 ;
+static const uint8_t P9N2_PU_CME8_CME_LCL_TSEL_WATCHDOG_SEL_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME1_CME_LCL_TSEL_FIT_SEL = 0 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_TSEL_FIT_SEL_LEN = 4 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_TSEL_WATCHDOG_SEL = 4 ;
+static const uint8_t P9N2_PU_CME1_CME_LCL_TSEL_WATCHDOG_SEL_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME0_CME_LCL_TSEL_FIT_SEL = 0 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_TSEL_FIT_SEL_LEN = 4 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_TSEL_WATCHDOG_SEL = 4 ;
+static const uint8_t P9N2_PU_CME0_CME_LCL_TSEL_WATCHDOG_SEL_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME7_CME_LCL_TSEL_FIT_SEL = 0 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_TSEL_FIT_SEL_LEN = 4 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_TSEL_WATCHDOG_SEL = 4 ;
+static const uint8_t P9N2_PU_CME7_CME_LCL_TSEL_WATCHDOG_SEL_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME4_CME_SCOM_AFSR_INST_CYCLE_SAMPLE = 0 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_AFSR_INST_CYCLE_SAMPLE_LEN = 20 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE = 32 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE_LEN = 20 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_AFSR_SAMPLE_VALID = 63 ;
+
+static const uint8_t P9N2_PU_CME3_CME_SCOM_AFSR_INST_CYCLE_SAMPLE = 0 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_AFSR_INST_CYCLE_SAMPLE_LEN = 20 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE = 32 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE_LEN = 20 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_AFSR_SAMPLE_VALID = 63 ;
+
+static const uint8_t P9N2_PU_CME11_CME_SCOM_AFSR_INST_CYCLE_SAMPLE = 0 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_AFSR_INST_CYCLE_SAMPLE_LEN = 20 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE = 32 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE_LEN = 20 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_AFSR_SAMPLE_VALID = 63 ;
+
+static const uint8_t P9N2_PU_CME2_CME_SCOM_AFSR_INST_CYCLE_SAMPLE = 0 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_AFSR_INST_CYCLE_SAMPLE_LEN = 20 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE = 32 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE_LEN = 20 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_AFSR_SAMPLE_VALID = 63 ;
+
+static const uint8_t P9N2_PU_CME5_CME_SCOM_AFSR_INST_CYCLE_SAMPLE = 0 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_AFSR_INST_CYCLE_SAMPLE_LEN = 20 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE = 32 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE_LEN = 20 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_AFSR_SAMPLE_VALID = 63 ;
+
+static const uint8_t P9N2_PU_CME9_CME_SCOM_AFSR_INST_CYCLE_SAMPLE = 0 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_AFSR_INST_CYCLE_SAMPLE_LEN = 20 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE = 32 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE_LEN = 20 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_AFSR_SAMPLE_VALID = 63 ;
+
+static const uint8_t P9N2_PU_CME6_CME_SCOM_AFSR_INST_CYCLE_SAMPLE = 0 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_AFSR_INST_CYCLE_SAMPLE_LEN = 20 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE = 32 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE_LEN = 20 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_AFSR_SAMPLE_VALID = 63 ;
+
+static const uint8_t P9N2_PU_CME10_CME_SCOM_AFSR_INST_CYCLE_SAMPLE = 0 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_AFSR_INST_CYCLE_SAMPLE_LEN = 20 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE = 32 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE_LEN = 20 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_AFSR_SAMPLE_VALID = 63 ;
+
+static const uint8_t P9N2_PU_CME8_CME_SCOM_AFSR_INST_CYCLE_SAMPLE = 0 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_AFSR_INST_CYCLE_SAMPLE_LEN = 20 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE = 32 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE_LEN = 20 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_AFSR_SAMPLE_VALID = 63 ;
+
+static const uint8_t P9N2_PU_CME1_CME_SCOM_AFSR_INST_CYCLE_SAMPLE = 0 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_AFSR_INST_CYCLE_SAMPLE_LEN = 20 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE = 32 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE_LEN = 20 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_AFSR_SAMPLE_VALID = 63 ;
+
+static const uint8_t P9N2_PU_CME0_CME_SCOM_AFSR_INST_CYCLE_SAMPLE = 0 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_AFSR_INST_CYCLE_SAMPLE_LEN = 20 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE = 32 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE_LEN = 20 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_AFSR_SAMPLE_VALID = 63 ;
+
+static const uint8_t P9N2_PU_CME7_CME_SCOM_AFSR_INST_CYCLE_SAMPLE = 0 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_AFSR_INST_CYCLE_SAMPLE_LEN = 20 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE = 32 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE_LEN = 20 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_AFSR_SAMPLE_VALID = 63 ;
+
+static const uint8_t P9N2_PU_CME4_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE = 0 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE_LEN = 20 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE = 32 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE_LEN = 20 ;
+
+static const uint8_t P9N2_PU_CME3_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE = 0 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE_LEN = 20 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE = 32 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE_LEN = 20 ;
+
+static const uint8_t P9N2_PU_CME11_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE = 0 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE_LEN = 20 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE = 32 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE_LEN = 20 ;
+
+static const uint8_t P9N2_PU_CME2_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE = 0 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE_LEN = 20 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE = 32 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE_LEN = 20 ;
+
+static const uint8_t P9N2_PU_CME5_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE = 0 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE_LEN = 20 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE = 32 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE_LEN = 20 ;
+
+static const uint8_t P9N2_PU_CME9_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE = 0 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE_LEN = 20 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE = 32 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE_LEN = 20 ;
+
+static const uint8_t P9N2_PU_CME6_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE = 0 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE_LEN = 20 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE = 32 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE_LEN = 20 ;
+
+static const uint8_t P9N2_PU_CME10_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE = 0 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE_LEN = 20 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE = 32 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE_LEN = 20 ;
+
+static const uint8_t P9N2_PU_CME8_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE = 0 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE_LEN = 20 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE = 32 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE_LEN = 20 ;
+
+static const uint8_t P9N2_PU_CME1_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE = 0 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE_LEN = 20 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE = 32 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE_LEN = 20 ;
+
+static const uint8_t P9N2_PU_CME0_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE = 0 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE_LEN = 20 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE = 32 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE_LEN = 20 ;
+
+static const uint8_t P9N2_PU_CME7_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE = 0 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE_LEN = 20 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE = 32 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE_LEN = 20 ;
+
+static const uint8_t P9N2_PU_CME4_CME_SCOM_BCECSR_BUSY = 0 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_BCECSR_ERROR = 1 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_BCECSR_RNW = 4 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_BCECSR_BARSEL = 5 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_BCECSR_PRIORITY = 6 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_BCECSR_INJECT_ERR = 7 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_BCECSR_TYPE = 13 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_BCECSR_TYPE_LEN = 3 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_BCECSR_NUM_BLOCKS = 17 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_BCECSR_NUM_BLOCKS_LEN = 11 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_BCECSR_SBASE = 28 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_BCECSR_SBASE_LEN = 12 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_BCECSR_MBASE = 42 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_BCECSR_MBASE_LEN = 22 ;
+
+static const uint8_t P9N2_PU_CME3_CME_SCOM_BCECSR_BUSY = 0 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_BCECSR_ERROR = 1 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_BCECSR_RNW = 4 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_BCECSR_BARSEL = 5 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_BCECSR_PRIORITY = 6 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_BCECSR_INJECT_ERR = 7 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_BCECSR_TYPE = 13 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_BCECSR_TYPE_LEN = 3 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_BCECSR_NUM_BLOCKS = 17 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_BCECSR_NUM_BLOCKS_LEN = 11 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_BCECSR_SBASE = 28 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_BCECSR_SBASE_LEN = 12 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_BCECSR_MBASE = 42 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_BCECSR_MBASE_LEN = 22 ;
+
+static const uint8_t P9N2_PU_CME11_CME_SCOM_BCECSR_BUSY = 0 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_BCECSR_ERROR = 1 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_BCECSR_RNW = 4 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_BCECSR_BARSEL = 5 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_BCECSR_PRIORITY = 6 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_BCECSR_INJECT_ERR = 7 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_BCECSR_TYPE = 13 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_BCECSR_TYPE_LEN = 3 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_BCECSR_NUM_BLOCKS = 17 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_BCECSR_NUM_BLOCKS_LEN = 11 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_BCECSR_SBASE = 28 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_BCECSR_SBASE_LEN = 12 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_BCECSR_MBASE = 42 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_BCECSR_MBASE_LEN = 22 ;
+
+static const uint8_t P9N2_PU_CME2_CME_SCOM_BCECSR_BUSY = 0 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_BCECSR_ERROR = 1 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_BCECSR_RNW = 4 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_BCECSR_BARSEL = 5 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_BCECSR_PRIORITY = 6 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_BCECSR_INJECT_ERR = 7 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_BCECSR_TYPE = 13 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_BCECSR_TYPE_LEN = 3 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_BCECSR_NUM_BLOCKS = 17 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_BCECSR_NUM_BLOCKS_LEN = 11 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_BCECSR_SBASE = 28 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_BCECSR_SBASE_LEN = 12 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_BCECSR_MBASE = 42 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_BCECSR_MBASE_LEN = 22 ;
+
+static const uint8_t P9N2_PU_CME5_CME_SCOM_BCECSR_BUSY = 0 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_BCECSR_ERROR = 1 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_BCECSR_RNW = 4 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_BCECSR_BARSEL = 5 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_BCECSR_PRIORITY = 6 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_BCECSR_INJECT_ERR = 7 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_BCECSR_TYPE = 13 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_BCECSR_TYPE_LEN = 3 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_BCECSR_NUM_BLOCKS = 17 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_BCECSR_NUM_BLOCKS_LEN = 11 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_BCECSR_SBASE = 28 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_BCECSR_SBASE_LEN = 12 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_BCECSR_MBASE = 42 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_BCECSR_MBASE_LEN = 22 ;
+
+static const uint8_t P9N2_PU_CME9_CME_SCOM_BCECSR_BUSY = 0 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_BCECSR_ERROR = 1 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_BCECSR_RNW = 4 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_BCECSR_BARSEL = 5 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_BCECSR_PRIORITY = 6 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_BCECSR_INJECT_ERR = 7 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_BCECSR_TYPE = 13 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_BCECSR_TYPE_LEN = 3 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_BCECSR_NUM_BLOCKS = 17 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_BCECSR_NUM_BLOCKS_LEN = 11 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_BCECSR_SBASE = 28 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_BCECSR_SBASE_LEN = 12 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_BCECSR_MBASE = 42 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_BCECSR_MBASE_LEN = 22 ;
+
+static const uint8_t P9N2_PU_CME6_CME_SCOM_BCECSR_BUSY = 0 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_BCECSR_ERROR = 1 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_BCECSR_RNW = 4 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_BCECSR_BARSEL = 5 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_BCECSR_PRIORITY = 6 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_BCECSR_INJECT_ERR = 7 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_BCECSR_TYPE = 13 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_BCECSR_TYPE_LEN = 3 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_BCECSR_NUM_BLOCKS = 17 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_BCECSR_NUM_BLOCKS_LEN = 11 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_BCECSR_SBASE = 28 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_BCECSR_SBASE_LEN = 12 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_BCECSR_MBASE = 42 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_BCECSR_MBASE_LEN = 22 ;
+
+static const uint8_t P9N2_PU_CME10_CME_SCOM_BCECSR_BUSY = 0 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_BCECSR_ERROR = 1 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_BCECSR_RNW = 4 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_BCECSR_BARSEL = 5 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_BCECSR_PRIORITY = 6 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_BCECSR_INJECT_ERR = 7 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_BCECSR_TYPE = 13 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_BCECSR_TYPE_LEN = 3 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_BCECSR_NUM_BLOCKS = 17 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_BCECSR_NUM_BLOCKS_LEN = 11 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_BCECSR_SBASE = 28 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_BCECSR_SBASE_LEN = 12 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_BCECSR_MBASE = 42 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_BCECSR_MBASE_LEN = 22 ;
+
+static const uint8_t P9N2_PU_CME8_CME_SCOM_BCECSR_BUSY = 0 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_BCECSR_ERROR = 1 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_BCECSR_RNW = 4 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_BCECSR_BARSEL = 5 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_BCECSR_PRIORITY = 6 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_BCECSR_INJECT_ERR = 7 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_BCECSR_TYPE = 13 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_BCECSR_TYPE_LEN = 3 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_BCECSR_NUM_BLOCKS = 17 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_BCECSR_NUM_BLOCKS_LEN = 11 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_BCECSR_SBASE = 28 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_BCECSR_SBASE_LEN = 12 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_BCECSR_MBASE = 42 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_BCECSR_MBASE_LEN = 22 ;
+
+static const uint8_t P9N2_PU_CME1_CME_SCOM_BCECSR_BUSY = 0 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_BCECSR_ERROR = 1 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_BCECSR_RNW = 4 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_BCECSR_BARSEL = 5 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_BCECSR_PRIORITY = 6 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_BCECSR_INJECT_ERR = 7 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_BCECSR_TYPE = 13 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_BCECSR_TYPE_LEN = 3 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_BCECSR_NUM_BLOCKS = 17 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_BCECSR_NUM_BLOCKS_LEN = 11 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_BCECSR_SBASE = 28 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_BCECSR_SBASE_LEN = 12 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_BCECSR_MBASE = 42 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_BCECSR_MBASE_LEN = 22 ;
+
+static const uint8_t P9N2_PU_CME0_CME_SCOM_BCECSR_BUSY = 0 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_BCECSR_ERROR = 1 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_BCECSR_RNW = 4 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_BCECSR_BARSEL = 5 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_BCECSR_PRIORITY = 6 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_BCECSR_INJECT_ERR = 7 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_BCECSR_TYPE = 13 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_BCECSR_TYPE_LEN = 3 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_BCECSR_NUM_BLOCKS = 17 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_BCECSR_NUM_BLOCKS_LEN = 11 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_BCECSR_SBASE = 28 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_BCECSR_SBASE_LEN = 12 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_BCECSR_MBASE = 42 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_BCECSR_MBASE_LEN = 22 ;
+
+static const uint8_t P9N2_PU_CME7_CME_SCOM_BCECSR_BUSY = 0 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_BCECSR_ERROR = 1 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_BCECSR_RNW = 4 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_BCECSR_BARSEL = 5 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_BCECSR_PRIORITY = 6 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_BCECSR_INJECT_ERR = 7 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_BCECSR_TYPE = 13 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_BCECSR_TYPE_LEN = 3 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_BCECSR_NUM_BLOCKS = 17 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_BCECSR_NUM_BLOCKS_LEN = 11 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_BCECSR_SBASE = 28 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_BCECSR_SBASE_LEN = 12 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_BCECSR_MBASE = 42 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_BCECSR_MBASE_LEN = 22 ;
+
+static const uint8_t P9N2_PU_CME4_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT = 0 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT_LEN = 24 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT = 24 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT_LEN = 8 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT = 32 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT_LEN = 24 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT = 56 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT_LEN = 8 ;
+
+static const uint8_t P9N2_PU_CME3_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT = 0 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT_LEN = 24 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT = 24 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT_LEN = 8 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT = 32 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT_LEN = 24 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT = 56 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT_LEN = 8 ;
+
+static const uint8_t P9N2_PU_CME11_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT = 0 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT_LEN = 24 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT = 24 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT_LEN = 8 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT = 32 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT_LEN = 24 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT = 56 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT_LEN = 8 ;
+
+static const uint8_t P9N2_PU_CME2_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT = 0 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT_LEN = 24 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT = 24 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT_LEN = 8 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT = 32 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT_LEN = 24 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT = 56 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT_LEN = 8 ;
+
+static const uint8_t P9N2_PU_CME5_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT = 0 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT_LEN = 24 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT = 24 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT_LEN = 8 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT = 32 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT_LEN = 24 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT = 56 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT_LEN = 8 ;
+
+static const uint8_t P9N2_PU_CME9_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT = 0 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT_LEN = 24 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT = 24 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT_LEN = 8 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT = 32 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT_LEN = 24 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT = 56 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT_LEN = 8 ;
+
+static const uint8_t P9N2_PU_CME6_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT = 0 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT_LEN = 24 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT = 24 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT_LEN = 8 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT = 32 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT_LEN = 24 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT = 56 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT_LEN = 8 ;
+
+static const uint8_t P9N2_PU_CME10_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT = 0 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT_LEN = 24 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT = 24 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT_LEN = 8 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT = 32 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT_LEN = 24 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT = 56 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT_LEN = 8 ;
+
+static const uint8_t P9N2_PU_CME8_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT = 0 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT_LEN = 24 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT = 24 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT_LEN = 8 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT = 32 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT_LEN = 24 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT = 56 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT_LEN = 8 ;
+
+static const uint8_t P9N2_PU_CME1_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT = 0 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT_LEN = 24 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT = 24 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT_LEN = 8 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT = 32 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT_LEN = 24 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT = 56 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT_LEN = 8 ;
+
+static const uint8_t P9N2_PU_CME0_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT = 0 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT_LEN = 24 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT = 24 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT_LEN = 8 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT = 32 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT_LEN = 24 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT = 56 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT_LEN = 8 ;
+
+static const uint8_t P9N2_PU_CME7_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT = 0 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT_LEN = 24 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT = 24 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT_LEN = 8 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT = 32 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT_LEN = 24 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT = 56 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT_LEN = 8 ;
+
+static const uint8_t P9N2_PU_CME4_CME_SCOM_FLAGS_DATA = 0 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_FLAGS_DATA_LEN = 32 ;
+
+static const uint8_t P9N2_PU_CME3_CME_SCOM_FLAGS_DATA = 0 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_FLAGS_DATA_LEN = 32 ;
+
+static const uint8_t P9N2_PU_CME11_CME_SCOM_FLAGS_DATA = 0 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_FLAGS_DATA_LEN = 32 ;
+
+static const uint8_t P9N2_PU_CME2_CME_SCOM_FLAGS_DATA = 0 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_FLAGS_DATA_LEN = 32 ;
+
+static const uint8_t P9N2_PU_CME5_CME_SCOM_FLAGS_DATA = 0 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_FLAGS_DATA_LEN = 32 ;
+
+static const uint8_t P9N2_PU_CME9_CME_SCOM_FLAGS_DATA = 0 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_FLAGS_DATA_LEN = 32 ;
+
+static const uint8_t P9N2_PU_CME6_CME_SCOM_FLAGS_DATA = 0 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_FLAGS_DATA_LEN = 32 ;
+
+static const uint8_t P9N2_PU_CME10_CME_SCOM_FLAGS_DATA = 0 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_FLAGS_DATA_LEN = 32 ;
+
+static const uint8_t P9N2_PU_CME8_CME_SCOM_FLAGS_DATA = 0 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_FLAGS_DATA_LEN = 32 ;
+
+static const uint8_t P9N2_PU_CME1_CME_SCOM_FLAGS_DATA = 0 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_FLAGS_DATA_LEN = 32 ;
+
+static const uint8_t P9N2_PU_CME0_CME_SCOM_FLAGS_DATA = 0 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_FLAGS_DATA_LEN = 32 ;
+
+static const uint8_t P9N2_PU_CME7_CME_SCOM_FLAGS_DATA = 0 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_FLAGS_DATA_LEN = 32 ;
+
+static const uint8_t P9N2_PU_CME4_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD = 0 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD_LEN = 24 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD = 24 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD_LEN = 8 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_IDCR_DROPOUT_TIMER_MODE = 32 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_IDCR_DROPOUT_CHAR_MODE = 33 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE = 34 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE_LEN = 2 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE = 36 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE_LEN = 2 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_IDCR_CACHE_DROPOUT_ENABLE = 38 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_IDCR_SPARE = 39 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_IDCR_DROPOUT_NOTIFY_ENABLE = 40 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_IDCR_SPARE41_43 = 41 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_IDCR_SPARE41_43_LEN = 3 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE = 59 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE_LEN = 5 ;
+
+static const uint8_t P9N2_PU_CME3_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD = 0 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD_LEN = 24 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD = 24 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD_LEN = 8 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_IDCR_DROPOUT_TIMER_MODE = 32 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_IDCR_DROPOUT_CHAR_MODE = 33 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE = 34 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE_LEN = 2 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE = 36 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE_LEN = 2 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_IDCR_CACHE_DROPOUT_ENABLE = 38 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_IDCR_SPARE = 39 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_IDCR_DROPOUT_NOTIFY_ENABLE = 40 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_IDCR_SPARE41_43 = 41 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_IDCR_SPARE41_43_LEN = 3 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE = 59 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE_LEN = 5 ;
+
+static const uint8_t P9N2_PU_CME11_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD = 0 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD_LEN = 24 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD = 24 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD_LEN = 8 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_IDCR_DROPOUT_TIMER_MODE = 32 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_IDCR_DROPOUT_CHAR_MODE = 33 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE = 34 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE_LEN = 2 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE = 36 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE_LEN = 2 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_IDCR_CACHE_DROPOUT_ENABLE = 38 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_IDCR_SPARE = 39 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_IDCR_DROPOUT_NOTIFY_ENABLE = 40 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_IDCR_SPARE41_43 = 41 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_IDCR_SPARE41_43_LEN = 3 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE = 59 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE_LEN = 5 ;
+
+static const uint8_t P9N2_PU_CME2_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD = 0 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD_LEN = 24 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD = 24 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD_LEN = 8 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_IDCR_DROPOUT_TIMER_MODE = 32 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_IDCR_DROPOUT_CHAR_MODE = 33 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE = 34 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE_LEN = 2 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE = 36 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE_LEN = 2 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_IDCR_CACHE_DROPOUT_ENABLE = 38 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_IDCR_SPARE = 39 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_IDCR_DROPOUT_NOTIFY_ENABLE = 40 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_IDCR_SPARE41_43 = 41 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_IDCR_SPARE41_43_LEN = 3 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE = 59 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE_LEN = 5 ;
+
+static const uint8_t P9N2_PU_CME5_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD = 0 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD_LEN = 24 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD = 24 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD_LEN = 8 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_IDCR_DROPOUT_TIMER_MODE = 32 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_IDCR_DROPOUT_CHAR_MODE = 33 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE = 34 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE_LEN = 2 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE = 36 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE_LEN = 2 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_IDCR_CACHE_DROPOUT_ENABLE = 38 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_IDCR_SPARE = 39 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_IDCR_DROPOUT_NOTIFY_ENABLE = 40 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_IDCR_SPARE41_43 = 41 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_IDCR_SPARE41_43_LEN = 3 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE = 59 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE_LEN = 5 ;
+
+static const uint8_t P9N2_PU_CME9_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD = 0 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD_LEN = 24 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD = 24 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD_LEN = 8 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_IDCR_DROPOUT_TIMER_MODE = 32 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_IDCR_DROPOUT_CHAR_MODE = 33 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE = 34 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE_LEN = 2 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE = 36 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE_LEN = 2 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_IDCR_CACHE_DROPOUT_ENABLE = 38 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_IDCR_SPARE = 39 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_IDCR_DROPOUT_NOTIFY_ENABLE = 40 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_IDCR_SPARE41_43 = 41 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_IDCR_SPARE41_43_LEN = 3 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE = 59 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE_LEN = 5 ;
+
+static const uint8_t P9N2_PU_CME6_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD = 0 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD_LEN = 24 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD = 24 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD_LEN = 8 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_IDCR_DROPOUT_TIMER_MODE = 32 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_IDCR_DROPOUT_CHAR_MODE = 33 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE = 34 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE_LEN = 2 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE = 36 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE_LEN = 2 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_IDCR_CACHE_DROPOUT_ENABLE = 38 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_IDCR_SPARE = 39 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_IDCR_DROPOUT_NOTIFY_ENABLE = 40 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_IDCR_SPARE41_43 = 41 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_IDCR_SPARE41_43_LEN = 3 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE = 59 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE_LEN = 5 ;
+
+static const uint8_t P9N2_PU_CME10_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD = 0 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD_LEN = 24 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD = 24 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD_LEN = 8 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_IDCR_DROPOUT_TIMER_MODE = 32 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_IDCR_DROPOUT_CHAR_MODE = 33 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE = 34 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE_LEN = 2 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE = 36 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE_LEN = 2 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_IDCR_CACHE_DROPOUT_ENABLE = 38 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_IDCR_SPARE = 39 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_IDCR_DROPOUT_NOTIFY_ENABLE = 40 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_IDCR_SPARE41_43 = 41 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_IDCR_SPARE41_43_LEN = 3 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE = 59 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE_LEN = 5 ;
+
+static const uint8_t P9N2_PU_CME8_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD = 0 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD_LEN = 24 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD = 24 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD_LEN = 8 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_IDCR_DROPOUT_TIMER_MODE = 32 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_IDCR_DROPOUT_CHAR_MODE = 33 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE = 34 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE_LEN = 2 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE = 36 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE_LEN = 2 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_IDCR_CACHE_DROPOUT_ENABLE = 38 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_IDCR_SPARE = 39 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_IDCR_DROPOUT_NOTIFY_ENABLE = 40 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_IDCR_SPARE41_43 = 41 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_IDCR_SPARE41_43_LEN = 3 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE = 59 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE_LEN = 5 ;
+
+static const uint8_t P9N2_PU_CME1_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD = 0 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD_LEN = 24 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD = 24 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD_LEN = 8 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_IDCR_DROPOUT_TIMER_MODE = 32 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_IDCR_DROPOUT_CHAR_MODE = 33 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE = 34 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE_LEN = 2 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE = 36 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE_LEN = 2 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_IDCR_CACHE_DROPOUT_ENABLE = 38 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_IDCR_SPARE = 39 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_IDCR_DROPOUT_NOTIFY_ENABLE = 40 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_IDCR_SPARE41_43 = 41 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_IDCR_SPARE41_43_LEN = 3 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE = 59 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE_LEN = 5 ;
+
+static const uint8_t P9N2_PU_CME0_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD = 0 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD_LEN = 24 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD = 24 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD_LEN = 8 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_IDCR_DROPOUT_TIMER_MODE = 32 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_IDCR_DROPOUT_CHAR_MODE = 33 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE = 34 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE_LEN = 2 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE = 36 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE_LEN = 2 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_IDCR_CACHE_DROPOUT_ENABLE = 38 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_IDCR_SPARE = 39 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_IDCR_DROPOUT_NOTIFY_ENABLE = 40 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_IDCR_SPARE41_43 = 41 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_IDCR_SPARE41_43_LEN = 3 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE = 59 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE_LEN = 5 ;
+
+static const uint8_t P9N2_PU_CME7_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD = 0 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD_LEN = 24 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD = 24 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD_LEN = 8 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_IDCR_DROPOUT_TIMER_MODE = 32 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_IDCR_DROPOUT_CHAR_MODE = 33 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE = 34 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE_LEN = 2 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE = 36 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE_LEN = 2 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_IDCR_CACHE_DROPOUT_ENABLE = 38 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_IDCR_SPARE = 39 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_IDCR_DROPOUT_NOTIFY_ENABLE = 40 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_IDCR_SPARE41_43 = 41 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_IDCR_SPARE41_43_LEN = 3 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE = 59 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE_LEN = 5 ;
+
+static const uint8_t P9N2_PU_CME4_CME_SCOM_LMCR_PMCR_OVERRIDE_EN = 0 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_LMCR_PSCR_OVERRIDE_EN = 1 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_LMCR_PMSR_OVERRIDE_EN = 2 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_LMCR_BCECSR_OVERRIDE_EN = 3 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_LMCR_IDR_LCL_SAMPLE_EN = 4 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_LMCR_VDM_LCL_SAMPLE_EN = 5 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_LMCR_FREQ_LCL_SAMPLE_EN = 6 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_LMCR_LOCK_PCB_ON_ERR = 7 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_LMCR_QUEUED_WR_EN = 8 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_LMCR_QUEUED_RD_EN = 9 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_LMCR_MASK_PURGE_INTERFACE = 10 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_LMCR_AUTO_BLOCK_REG_WAKEUP_DISABLE = 11 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_LMCR_C0_AUTO_SPECIAL_WAKEUP_DISABLE = 12 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_LMCR_C1_AUTO_SPECIAL_WAKEUP_DISABLE = 13 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE = 14 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE = 15 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_LMCR_STOP_OVERRIDE_MODE = 16 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_LMCR_STOP_ACTIVE_MASK = 17 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_LMCR_AUTO_STOP1_DISABLE = 18 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_LMCR_STOP1_ACTIVE_ENABLE = 19 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_LMCR_FENCE_EISR = 20 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_LMCR_PC_DISABLE_DROOP = 21 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_LMCR_BLOCK_PM_EXIT_DISABLE = 22 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_LMCR_SPARE_23 = 23 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_LMCR_AVG_FREQ_TSEL = 24 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_LMCR_AVG_FREQ_TSEL_LEN = 4 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_LMCR_SPARE_28_31 = 28 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_LMCR_SPARE_28_31_LEN = 4 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_LMCR_RESET_IMPRECISE_QERR = 32 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_LMCR_SET_ECC_INJECT_ERR = 33 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_LMCR_SPARE_34 = 34 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_LMCR_OOB_ERR_DISABLE = 35 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_LMCR_OOB_ERR_DISABLE_LEN = 5 ;
+
+static const uint8_t P9N2_PU_CME3_CME_SCOM_LMCR_PMCR_OVERRIDE_EN = 0 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_LMCR_PSCR_OVERRIDE_EN = 1 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_LMCR_PMSR_OVERRIDE_EN = 2 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_LMCR_BCECSR_OVERRIDE_EN = 3 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_LMCR_IDR_LCL_SAMPLE_EN = 4 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_LMCR_VDM_LCL_SAMPLE_EN = 5 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_LMCR_FREQ_LCL_SAMPLE_EN = 6 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_LMCR_LOCK_PCB_ON_ERR = 7 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_LMCR_QUEUED_WR_EN = 8 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_LMCR_QUEUED_RD_EN = 9 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_LMCR_MASK_PURGE_INTERFACE = 10 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_LMCR_AUTO_BLOCK_REG_WAKEUP_DISABLE = 11 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_LMCR_C0_AUTO_SPECIAL_WAKEUP_DISABLE = 12 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_LMCR_C1_AUTO_SPECIAL_WAKEUP_DISABLE = 13 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE = 14 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE = 15 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_LMCR_STOP_OVERRIDE_MODE = 16 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_LMCR_STOP_ACTIVE_MASK = 17 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_LMCR_AUTO_STOP1_DISABLE = 18 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_LMCR_STOP1_ACTIVE_ENABLE = 19 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_LMCR_FENCE_EISR = 20 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_LMCR_PC_DISABLE_DROOP = 21 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_LMCR_BLOCK_PM_EXIT_DISABLE = 22 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_LMCR_SPARE_23 = 23 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_LMCR_AVG_FREQ_TSEL = 24 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_LMCR_AVG_FREQ_TSEL_LEN = 4 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_LMCR_SPARE_28_31 = 28 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_LMCR_SPARE_28_31_LEN = 4 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_LMCR_RESET_IMPRECISE_QERR = 32 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_LMCR_SET_ECC_INJECT_ERR = 33 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_LMCR_SPARE_34 = 34 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_LMCR_OOB_ERR_DISABLE = 35 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_LMCR_OOB_ERR_DISABLE_LEN = 5 ;
+
+static const uint8_t P9N2_PU_CME11_CME_SCOM_LMCR_PMCR_OVERRIDE_EN = 0 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_LMCR_PSCR_OVERRIDE_EN = 1 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_LMCR_PMSR_OVERRIDE_EN = 2 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_LMCR_BCECSR_OVERRIDE_EN = 3 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_LMCR_IDR_LCL_SAMPLE_EN = 4 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_LMCR_VDM_LCL_SAMPLE_EN = 5 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_LMCR_FREQ_LCL_SAMPLE_EN = 6 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_LMCR_LOCK_PCB_ON_ERR = 7 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_LMCR_QUEUED_WR_EN = 8 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_LMCR_QUEUED_RD_EN = 9 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_LMCR_MASK_PURGE_INTERFACE = 10 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_LMCR_AUTO_BLOCK_REG_WAKEUP_DISABLE = 11 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_LMCR_C0_AUTO_SPECIAL_WAKEUP_DISABLE = 12 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_LMCR_C1_AUTO_SPECIAL_WAKEUP_DISABLE = 13 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE = 14 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE = 15 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_LMCR_STOP_OVERRIDE_MODE = 16 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_LMCR_STOP_ACTIVE_MASK = 17 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_LMCR_AUTO_STOP1_DISABLE = 18 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_LMCR_STOP1_ACTIVE_ENABLE = 19 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_LMCR_FENCE_EISR = 20 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_LMCR_PC_DISABLE_DROOP = 21 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_LMCR_BLOCK_PM_EXIT_DISABLE = 22 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_LMCR_SPARE_23 = 23 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_LMCR_AVG_FREQ_TSEL = 24 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_LMCR_AVG_FREQ_TSEL_LEN = 4 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_LMCR_SPARE_28_31 = 28 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_LMCR_SPARE_28_31_LEN = 4 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_LMCR_RESET_IMPRECISE_QERR = 32 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_LMCR_SET_ECC_INJECT_ERR = 33 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_LMCR_SPARE_34 = 34 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_LMCR_OOB_ERR_DISABLE = 35 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_LMCR_OOB_ERR_DISABLE_LEN = 5 ;
+
+static const uint8_t P9N2_PU_CME2_CME_SCOM_LMCR_PMCR_OVERRIDE_EN = 0 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_LMCR_PSCR_OVERRIDE_EN = 1 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_LMCR_PMSR_OVERRIDE_EN = 2 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_LMCR_BCECSR_OVERRIDE_EN = 3 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_LMCR_IDR_LCL_SAMPLE_EN = 4 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_LMCR_VDM_LCL_SAMPLE_EN = 5 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_LMCR_FREQ_LCL_SAMPLE_EN = 6 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_LMCR_LOCK_PCB_ON_ERR = 7 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_LMCR_QUEUED_WR_EN = 8 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_LMCR_QUEUED_RD_EN = 9 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_LMCR_MASK_PURGE_INTERFACE = 10 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_LMCR_AUTO_BLOCK_REG_WAKEUP_DISABLE = 11 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_LMCR_C0_AUTO_SPECIAL_WAKEUP_DISABLE = 12 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_LMCR_C1_AUTO_SPECIAL_WAKEUP_DISABLE = 13 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE = 14 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE = 15 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_LMCR_STOP_OVERRIDE_MODE = 16 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_LMCR_STOP_ACTIVE_MASK = 17 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_LMCR_AUTO_STOP1_DISABLE = 18 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_LMCR_STOP1_ACTIVE_ENABLE = 19 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_LMCR_FENCE_EISR = 20 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_LMCR_PC_DISABLE_DROOP = 21 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_LMCR_BLOCK_PM_EXIT_DISABLE = 22 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_LMCR_SPARE_23 = 23 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_LMCR_AVG_FREQ_TSEL = 24 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_LMCR_AVG_FREQ_TSEL_LEN = 4 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_LMCR_SPARE_28_31 = 28 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_LMCR_SPARE_28_31_LEN = 4 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_LMCR_RESET_IMPRECISE_QERR = 32 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_LMCR_SET_ECC_INJECT_ERR = 33 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_LMCR_SPARE_34 = 34 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_LMCR_OOB_ERR_DISABLE = 35 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_LMCR_OOB_ERR_DISABLE_LEN = 5 ;
+
+static const uint8_t P9N2_PU_CME5_CME_SCOM_LMCR_PMCR_OVERRIDE_EN = 0 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_LMCR_PSCR_OVERRIDE_EN = 1 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_LMCR_PMSR_OVERRIDE_EN = 2 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_LMCR_BCECSR_OVERRIDE_EN = 3 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_LMCR_IDR_LCL_SAMPLE_EN = 4 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_LMCR_VDM_LCL_SAMPLE_EN = 5 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_LMCR_FREQ_LCL_SAMPLE_EN = 6 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_LMCR_LOCK_PCB_ON_ERR = 7 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_LMCR_QUEUED_WR_EN = 8 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_LMCR_QUEUED_RD_EN = 9 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_LMCR_MASK_PURGE_INTERFACE = 10 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_LMCR_AUTO_BLOCK_REG_WAKEUP_DISABLE = 11 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_LMCR_C0_AUTO_SPECIAL_WAKEUP_DISABLE = 12 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_LMCR_C1_AUTO_SPECIAL_WAKEUP_DISABLE = 13 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE = 14 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE = 15 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_LMCR_STOP_OVERRIDE_MODE = 16 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_LMCR_STOP_ACTIVE_MASK = 17 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_LMCR_AUTO_STOP1_DISABLE = 18 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_LMCR_STOP1_ACTIVE_ENABLE = 19 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_LMCR_FENCE_EISR = 20 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_LMCR_PC_DISABLE_DROOP = 21 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_LMCR_BLOCK_PM_EXIT_DISABLE = 22 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_LMCR_SPARE_23 = 23 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_LMCR_AVG_FREQ_TSEL = 24 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_LMCR_AVG_FREQ_TSEL_LEN = 4 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_LMCR_SPARE_28_31 = 28 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_LMCR_SPARE_28_31_LEN = 4 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_LMCR_RESET_IMPRECISE_QERR = 32 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_LMCR_SET_ECC_INJECT_ERR = 33 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_LMCR_SPARE_34 = 34 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_LMCR_OOB_ERR_DISABLE = 35 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_LMCR_OOB_ERR_DISABLE_LEN = 5 ;
+
+static const uint8_t P9N2_PU_CME9_CME_SCOM_LMCR_PMCR_OVERRIDE_EN = 0 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_LMCR_PSCR_OVERRIDE_EN = 1 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_LMCR_PMSR_OVERRIDE_EN = 2 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_LMCR_BCECSR_OVERRIDE_EN = 3 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_LMCR_IDR_LCL_SAMPLE_EN = 4 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_LMCR_VDM_LCL_SAMPLE_EN = 5 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_LMCR_FREQ_LCL_SAMPLE_EN = 6 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_LMCR_LOCK_PCB_ON_ERR = 7 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_LMCR_QUEUED_WR_EN = 8 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_LMCR_QUEUED_RD_EN = 9 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_LMCR_MASK_PURGE_INTERFACE = 10 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_LMCR_AUTO_BLOCK_REG_WAKEUP_DISABLE = 11 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_LMCR_C0_AUTO_SPECIAL_WAKEUP_DISABLE = 12 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_LMCR_C1_AUTO_SPECIAL_WAKEUP_DISABLE = 13 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE = 14 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE = 15 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_LMCR_STOP_OVERRIDE_MODE = 16 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_LMCR_STOP_ACTIVE_MASK = 17 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_LMCR_AUTO_STOP1_DISABLE = 18 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_LMCR_STOP1_ACTIVE_ENABLE = 19 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_LMCR_FENCE_EISR = 20 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_LMCR_PC_DISABLE_DROOP = 21 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_LMCR_BLOCK_PM_EXIT_DISABLE = 22 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_LMCR_SPARE_23 = 23 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_LMCR_AVG_FREQ_TSEL = 24 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_LMCR_AVG_FREQ_TSEL_LEN = 4 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_LMCR_SPARE_28_31 = 28 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_LMCR_SPARE_28_31_LEN = 4 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_LMCR_RESET_IMPRECISE_QERR = 32 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_LMCR_SET_ECC_INJECT_ERR = 33 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_LMCR_SPARE_34 = 34 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_LMCR_OOB_ERR_DISABLE = 35 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_LMCR_OOB_ERR_DISABLE_LEN = 5 ;
+
+static const uint8_t P9N2_PU_CME6_CME_SCOM_LMCR_PMCR_OVERRIDE_EN = 0 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_LMCR_PSCR_OVERRIDE_EN = 1 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_LMCR_PMSR_OVERRIDE_EN = 2 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_LMCR_BCECSR_OVERRIDE_EN = 3 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_LMCR_IDR_LCL_SAMPLE_EN = 4 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_LMCR_VDM_LCL_SAMPLE_EN = 5 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_LMCR_FREQ_LCL_SAMPLE_EN = 6 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_LMCR_LOCK_PCB_ON_ERR = 7 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_LMCR_QUEUED_WR_EN = 8 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_LMCR_QUEUED_RD_EN = 9 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_LMCR_MASK_PURGE_INTERFACE = 10 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_LMCR_AUTO_BLOCK_REG_WAKEUP_DISABLE = 11 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_LMCR_C0_AUTO_SPECIAL_WAKEUP_DISABLE = 12 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_LMCR_C1_AUTO_SPECIAL_WAKEUP_DISABLE = 13 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE = 14 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE = 15 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_LMCR_STOP_OVERRIDE_MODE = 16 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_LMCR_STOP_ACTIVE_MASK = 17 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_LMCR_AUTO_STOP1_DISABLE = 18 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_LMCR_STOP1_ACTIVE_ENABLE = 19 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_LMCR_FENCE_EISR = 20 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_LMCR_PC_DISABLE_DROOP = 21 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_LMCR_BLOCK_PM_EXIT_DISABLE = 22 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_LMCR_SPARE_23 = 23 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_LMCR_AVG_FREQ_TSEL = 24 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_LMCR_AVG_FREQ_TSEL_LEN = 4 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_LMCR_SPARE_28_31 = 28 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_LMCR_SPARE_28_31_LEN = 4 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_LMCR_RESET_IMPRECISE_QERR = 32 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_LMCR_SET_ECC_INJECT_ERR = 33 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_LMCR_SPARE_34 = 34 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_LMCR_OOB_ERR_DISABLE = 35 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_LMCR_OOB_ERR_DISABLE_LEN = 5 ;
+
+static const uint8_t P9N2_PU_CME10_CME_SCOM_LMCR_PMCR_OVERRIDE_EN = 0 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_LMCR_PSCR_OVERRIDE_EN = 1 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_LMCR_PMSR_OVERRIDE_EN = 2 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_LMCR_BCECSR_OVERRIDE_EN = 3 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_LMCR_IDR_LCL_SAMPLE_EN = 4 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_LMCR_VDM_LCL_SAMPLE_EN = 5 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_LMCR_FREQ_LCL_SAMPLE_EN = 6 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_LMCR_LOCK_PCB_ON_ERR = 7 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_LMCR_QUEUED_WR_EN = 8 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_LMCR_QUEUED_RD_EN = 9 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_LMCR_MASK_PURGE_INTERFACE = 10 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_LMCR_AUTO_BLOCK_REG_WAKEUP_DISABLE = 11 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_LMCR_C0_AUTO_SPECIAL_WAKEUP_DISABLE = 12 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_LMCR_C1_AUTO_SPECIAL_WAKEUP_DISABLE = 13 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE = 14 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE = 15 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_LMCR_STOP_OVERRIDE_MODE = 16 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_LMCR_STOP_ACTIVE_MASK = 17 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_LMCR_AUTO_STOP1_DISABLE = 18 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_LMCR_STOP1_ACTIVE_ENABLE = 19 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_LMCR_FENCE_EISR = 20 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_LMCR_PC_DISABLE_DROOP = 21 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_LMCR_BLOCK_PM_EXIT_DISABLE = 22 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_LMCR_SPARE_23 = 23 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_LMCR_AVG_FREQ_TSEL = 24 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_LMCR_AVG_FREQ_TSEL_LEN = 4 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_LMCR_SPARE_28_31 = 28 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_LMCR_SPARE_28_31_LEN = 4 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_LMCR_RESET_IMPRECISE_QERR = 32 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_LMCR_SET_ECC_INJECT_ERR = 33 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_LMCR_SPARE_34 = 34 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_LMCR_OOB_ERR_DISABLE = 35 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_LMCR_OOB_ERR_DISABLE_LEN = 5 ;
+
+static const uint8_t P9N2_PU_CME8_CME_SCOM_LMCR_PMCR_OVERRIDE_EN = 0 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_LMCR_PSCR_OVERRIDE_EN = 1 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_LMCR_PMSR_OVERRIDE_EN = 2 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_LMCR_BCECSR_OVERRIDE_EN = 3 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_LMCR_IDR_LCL_SAMPLE_EN = 4 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_LMCR_VDM_LCL_SAMPLE_EN = 5 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_LMCR_FREQ_LCL_SAMPLE_EN = 6 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_LMCR_LOCK_PCB_ON_ERR = 7 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_LMCR_QUEUED_WR_EN = 8 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_LMCR_QUEUED_RD_EN = 9 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_LMCR_MASK_PURGE_INTERFACE = 10 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_LMCR_AUTO_BLOCK_REG_WAKEUP_DISABLE = 11 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_LMCR_C0_AUTO_SPECIAL_WAKEUP_DISABLE = 12 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_LMCR_C1_AUTO_SPECIAL_WAKEUP_DISABLE = 13 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE = 14 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE = 15 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_LMCR_STOP_OVERRIDE_MODE = 16 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_LMCR_STOP_ACTIVE_MASK = 17 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_LMCR_AUTO_STOP1_DISABLE = 18 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_LMCR_STOP1_ACTIVE_ENABLE = 19 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_LMCR_FENCE_EISR = 20 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_LMCR_PC_DISABLE_DROOP = 21 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_LMCR_BLOCK_PM_EXIT_DISABLE = 22 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_LMCR_SPARE_23 = 23 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_LMCR_AVG_FREQ_TSEL = 24 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_LMCR_AVG_FREQ_TSEL_LEN = 4 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_LMCR_SPARE_28_31 = 28 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_LMCR_SPARE_28_31_LEN = 4 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_LMCR_RESET_IMPRECISE_QERR = 32 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_LMCR_SET_ECC_INJECT_ERR = 33 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_LMCR_SPARE_34 = 34 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_LMCR_OOB_ERR_DISABLE = 35 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_LMCR_OOB_ERR_DISABLE_LEN = 5 ;
+
+static const uint8_t P9N2_PU_CME1_CME_SCOM_LMCR_PMCR_OVERRIDE_EN = 0 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_LMCR_PSCR_OVERRIDE_EN = 1 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_LMCR_PMSR_OVERRIDE_EN = 2 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_LMCR_BCECSR_OVERRIDE_EN = 3 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_LMCR_IDR_LCL_SAMPLE_EN = 4 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_LMCR_VDM_LCL_SAMPLE_EN = 5 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_LMCR_FREQ_LCL_SAMPLE_EN = 6 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_LMCR_LOCK_PCB_ON_ERR = 7 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_LMCR_QUEUED_WR_EN = 8 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_LMCR_QUEUED_RD_EN = 9 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_LMCR_MASK_PURGE_INTERFACE = 10 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_LMCR_AUTO_BLOCK_REG_WAKEUP_DISABLE = 11 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_LMCR_C0_AUTO_SPECIAL_WAKEUP_DISABLE = 12 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_LMCR_C1_AUTO_SPECIAL_WAKEUP_DISABLE = 13 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE = 14 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE = 15 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_LMCR_STOP_OVERRIDE_MODE = 16 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_LMCR_STOP_ACTIVE_MASK = 17 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_LMCR_AUTO_STOP1_DISABLE = 18 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_LMCR_STOP1_ACTIVE_ENABLE = 19 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_LMCR_FENCE_EISR = 20 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_LMCR_PC_DISABLE_DROOP = 21 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_LMCR_BLOCK_PM_EXIT_DISABLE = 22 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_LMCR_SPARE_23 = 23 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_LMCR_AVG_FREQ_TSEL = 24 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_LMCR_AVG_FREQ_TSEL_LEN = 4 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_LMCR_SPARE_28_31 = 28 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_LMCR_SPARE_28_31_LEN = 4 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_LMCR_RESET_IMPRECISE_QERR = 32 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_LMCR_SET_ECC_INJECT_ERR = 33 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_LMCR_SPARE_34 = 34 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_LMCR_OOB_ERR_DISABLE = 35 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_LMCR_OOB_ERR_DISABLE_LEN = 5 ;
+
+static const uint8_t P9N2_PU_CME0_CME_SCOM_LMCR_PMCR_OVERRIDE_EN = 0 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_LMCR_PSCR_OVERRIDE_EN = 1 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_LMCR_PMSR_OVERRIDE_EN = 2 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_LMCR_BCECSR_OVERRIDE_EN = 3 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_LMCR_IDR_LCL_SAMPLE_EN = 4 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_LMCR_VDM_LCL_SAMPLE_EN = 5 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_LMCR_FREQ_LCL_SAMPLE_EN = 6 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_LMCR_LOCK_PCB_ON_ERR = 7 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_LMCR_QUEUED_WR_EN = 8 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_LMCR_QUEUED_RD_EN = 9 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_LMCR_MASK_PURGE_INTERFACE = 10 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_LMCR_AUTO_BLOCK_REG_WAKEUP_DISABLE = 11 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_LMCR_C0_AUTO_SPECIAL_WAKEUP_DISABLE = 12 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_LMCR_C1_AUTO_SPECIAL_WAKEUP_DISABLE = 13 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE = 14 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE = 15 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_LMCR_STOP_OVERRIDE_MODE = 16 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_LMCR_STOP_ACTIVE_MASK = 17 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_LMCR_AUTO_STOP1_DISABLE = 18 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_LMCR_STOP1_ACTIVE_ENABLE = 19 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_LMCR_FENCE_EISR = 20 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_LMCR_PC_DISABLE_DROOP = 21 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_LMCR_BLOCK_PM_EXIT_DISABLE = 22 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_LMCR_SPARE_23 = 23 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_LMCR_AVG_FREQ_TSEL = 24 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_LMCR_AVG_FREQ_TSEL_LEN = 4 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_LMCR_SPARE_28_31 = 28 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_LMCR_SPARE_28_31_LEN = 4 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_LMCR_RESET_IMPRECISE_QERR = 32 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_LMCR_SET_ECC_INJECT_ERR = 33 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_LMCR_SPARE_34 = 34 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_LMCR_OOB_ERR_DISABLE = 35 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_LMCR_OOB_ERR_DISABLE_LEN = 5 ;
+
+static const uint8_t P9N2_PU_CME7_CME_SCOM_LMCR_PMCR_OVERRIDE_EN = 0 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_LMCR_PSCR_OVERRIDE_EN = 1 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_LMCR_PMSR_OVERRIDE_EN = 2 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_LMCR_BCECSR_OVERRIDE_EN = 3 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_LMCR_IDR_LCL_SAMPLE_EN = 4 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_LMCR_VDM_LCL_SAMPLE_EN = 5 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_LMCR_FREQ_LCL_SAMPLE_EN = 6 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_LMCR_LOCK_PCB_ON_ERR = 7 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_LMCR_QUEUED_WR_EN = 8 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_LMCR_QUEUED_RD_EN = 9 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_LMCR_MASK_PURGE_INTERFACE = 10 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_LMCR_AUTO_BLOCK_REG_WAKEUP_DISABLE = 11 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_LMCR_C0_AUTO_SPECIAL_WAKEUP_DISABLE = 12 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_LMCR_C1_AUTO_SPECIAL_WAKEUP_DISABLE = 13 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE = 14 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE = 15 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_LMCR_STOP_OVERRIDE_MODE = 16 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_LMCR_STOP_ACTIVE_MASK = 17 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_LMCR_AUTO_STOP1_DISABLE = 18 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_LMCR_STOP1_ACTIVE_ENABLE = 19 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_LMCR_FENCE_EISR = 20 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_LMCR_PC_DISABLE_DROOP = 21 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_LMCR_BLOCK_PM_EXIT_DISABLE = 22 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_LMCR_SPARE_23 = 23 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_LMCR_AVG_FREQ_TSEL = 24 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_LMCR_AVG_FREQ_TSEL_LEN = 4 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_LMCR_SPARE_28_31 = 28 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_LMCR_SPARE_28_31_LEN = 4 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_LMCR_RESET_IMPRECISE_QERR = 32 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_LMCR_SET_ECC_INJECT_ERR = 33 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_LMCR_SPARE_34 = 34 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_LMCR_OOB_ERR_DISABLE = 35 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_LMCR_OOB_ERR_DISABLE_LEN = 5 ;
+
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PMCRS0_DATA = 0 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PMCRS0_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PMCRS0_DATA = 0 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PMCRS0_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PMCRS0_DATA = 0 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PMCRS0_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PMCRS0_DATA = 0 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PMCRS0_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PMCRS0_DATA = 0 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PMCRS0_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PMCRS0_DATA = 0 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PMCRS0_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PMCRS0_DATA = 0 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PMCRS0_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PMCRS0_DATA = 0 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PMCRS0_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PMCRS0_DATA = 0 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PMCRS0_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PMCRS0_DATA = 0 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PMCRS0_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PMCRS0_DATA = 0 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PMCRS0_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PMCRS0_DATA = 0 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PMCRS0_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PMCRS1_DATA = 0 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PMCRS1_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PMCRS1_DATA = 0 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PMCRS1_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PMCRS1_DATA = 0 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PMCRS1_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PMCRS1_DATA = 0 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PMCRS1_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PMCRS1_DATA = 0 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PMCRS1_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PMCRS1_DATA = 0 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PMCRS1_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PMCRS1_DATA = 0 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PMCRS1_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PMCRS1_DATA = 0 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PMCRS1_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PMCRS1_DATA = 0 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PMCRS1_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PMCRS1_DATA = 0 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PMCRS1_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PMCRS1_DATA = 0 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PMCRS1_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PMCRS1_DATA = 0 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PMCRS1_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PMSRS0_DATA = 0 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PMSRS0_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PMSRS0_DATA = 0 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PMSRS0_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PMSRS0_DATA = 0 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PMSRS0_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PMSRS0_DATA = 0 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PMSRS0_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PMSRS0_DATA = 0 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PMSRS0_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PMSRS0_DATA = 0 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PMSRS0_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PMSRS0_DATA = 0 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PMSRS0_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PMSRS0_DATA = 0 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PMSRS0_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PMSRS0_DATA = 0 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PMSRS0_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PMSRS0_DATA = 0 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PMSRS0_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PMSRS0_DATA = 0 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PMSRS0_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PMSRS0_DATA = 0 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PMSRS0_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PMSRS1_DATA = 0 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PMSRS1_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PMSRS1_DATA = 0 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PMSRS1_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PMSRS1_DATA = 0 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PMSRS1_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PMSRS1_DATA = 0 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PMSRS1_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PMSRS1_DATA = 0 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PMSRS1_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PMSRS1_DATA = 0 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PMSRS1_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PMSRS1_DATA = 0 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PMSRS1_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PMSRS1_DATA = 0 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PMSRS1_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PMSRS1_DATA = 0 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PMSRS1_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PMSRS1_DATA = 0 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PMSRS1_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PMSRS1_DATA = 0 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PMSRS1_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PMSRS1_DATA = 0 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PMSRS1_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS00_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS00_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS00_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS00_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS00_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS00_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS00_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS00_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS00_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS00_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS00_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS00_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS00_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS00_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS00_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS00_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS00_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS00_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS00_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS00_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS00_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS00_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS00_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS00_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS00_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS00_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS00_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS00_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS00_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS00_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS00_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS00_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS00_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS00_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS00_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS00_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS00_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS00_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS00_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS00_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS00_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS00_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS00_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS00_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS00_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS00_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS00_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS00_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS00_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS00_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS00_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS00_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS00_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS00_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS00_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS00_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS00_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS00_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS00_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS00_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS00_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS00_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS00_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS00_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS00_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS00_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS00_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS00_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS00_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS00_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS00_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS00_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS00_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS00_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS00_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS00_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS00_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS00_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS00_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS00_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS00_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS00_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS00_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS00_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS00_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS00_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS00_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS00_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS00_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS00_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS00_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS00_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS00_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS00_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS00_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS00_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS00_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS00_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS00_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS00_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS00_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS00_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS00_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS00_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS00_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS00_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS00_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS00_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS00_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS00_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS00_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS00_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS00_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS00_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS00_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS00_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS00_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS00_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS00_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS00_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS01_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS01_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS01_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS01_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS01_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS01_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS01_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS01_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS01_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS01_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS01_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS01_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS01_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS01_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS01_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS01_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS01_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS01_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS01_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS01_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS01_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS01_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS01_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS01_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS01_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS01_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS01_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS01_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS01_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS01_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS01_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS01_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS01_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS01_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS01_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS01_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS01_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS01_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS01_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS01_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS01_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS01_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS01_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS01_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS01_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS01_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS01_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS01_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS01_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS01_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS01_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS01_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS01_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS01_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS01_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS01_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS01_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS01_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS01_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS01_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS01_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS01_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS01_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS01_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS01_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS01_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS01_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS01_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS01_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS01_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS01_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS01_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS01_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS01_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS01_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS01_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS01_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS01_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS01_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS01_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS01_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS01_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS01_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS01_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS01_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS01_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS01_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS01_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS01_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS01_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS01_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS01_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS01_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS01_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS01_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS01_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS01_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS01_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS01_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS01_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS01_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS01_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS01_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS01_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS01_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS01_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS01_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS01_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS01_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS01_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS01_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS01_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS01_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS01_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS01_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS01_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS01_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS01_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS01_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS01_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS02_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS02_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS02_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS02_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS02_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS02_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS02_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS02_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS02_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS02_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS02_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS02_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS02_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS02_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS02_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS02_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS02_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS02_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS02_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS02_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS02_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS02_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS02_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS02_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS02_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS02_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS02_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS02_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS02_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS02_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS02_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS02_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS02_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS02_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS02_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS02_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS02_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS02_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS02_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS02_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS02_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS02_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS02_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS02_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS02_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS02_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS02_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS02_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS02_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS02_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS02_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS02_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS02_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS02_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS02_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS02_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS02_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS02_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS02_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS02_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS02_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS02_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS02_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS02_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS02_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS02_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS02_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS02_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS02_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS02_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS02_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS02_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS02_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS02_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS02_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS02_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS02_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS02_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS02_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS02_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS02_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS02_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS02_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS02_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS02_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS02_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS02_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS02_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS02_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS02_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS02_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS02_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS02_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS02_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS02_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS02_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS02_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS02_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS02_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS02_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS02_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS02_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS02_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS02_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS02_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS02_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS02_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS02_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS02_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS02_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS02_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS02_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS02_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS02_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS02_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS02_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS02_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS02_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS02_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS02_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS03_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS03_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS03_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS03_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS03_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS03_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS03_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS03_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS03_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS03_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS03_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS03_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS03_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS03_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS03_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS03_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS03_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS03_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS03_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS03_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS03_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS03_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS03_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS03_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS03_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS03_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS03_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS03_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS03_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS03_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS03_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS03_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS03_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS03_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS03_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS03_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS03_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS03_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS03_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS03_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS03_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS03_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS03_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS03_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS03_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS03_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS03_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS03_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS03_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS03_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS03_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS03_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS03_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS03_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS03_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS03_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS03_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS03_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS03_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS03_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS03_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS03_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS03_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS03_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS03_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS03_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS03_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS03_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS03_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS03_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS03_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS03_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS03_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS03_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS03_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS03_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS03_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS03_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS03_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS03_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS03_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS03_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS03_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS03_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS03_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS03_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS03_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS03_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS03_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS03_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS03_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS03_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS03_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS03_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS03_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS03_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS03_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS03_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS03_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS03_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS03_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS03_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS03_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS03_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS03_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS03_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS03_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS03_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS03_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS03_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS03_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS03_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS03_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS03_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS03_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS03_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS03_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS03_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS03_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS03_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS10_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS10_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS10_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS10_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS10_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS10_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS10_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS10_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS10_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS10_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS10_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS10_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS10_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS10_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS10_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS10_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS10_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS10_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS10_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS10_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS10_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS10_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS10_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS10_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS10_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS10_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS10_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS10_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS10_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS10_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS10_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS10_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS10_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS10_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS10_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS10_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS10_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS10_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS10_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS10_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS10_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS10_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS10_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS10_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS10_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS10_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS10_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS10_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS10_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS10_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS10_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS10_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS10_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS10_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS10_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS10_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS10_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS10_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS10_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS10_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS10_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS10_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS10_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS10_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS10_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS10_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS10_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS10_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS10_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS10_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS10_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS10_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS10_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS10_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS10_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS10_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS10_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS10_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS10_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS10_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS10_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS10_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS10_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS10_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS10_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS10_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS10_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS10_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS10_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS10_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS10_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS10_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS10_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS10_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS10_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS10_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS10_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS10_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS10_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS10_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS10_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS10_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS10_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS10_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS10_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS10_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS10_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS10_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS10_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS10_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS10_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS10_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS10_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS10_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS10_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS10_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS10_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS10_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS10_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS10_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS11_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS11_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS11_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS11_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS11_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS11_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS11_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS11_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS11_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS11_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS11_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS11_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS11_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS11_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS11_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS11_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS11_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS11_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS11_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS11_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS11_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS11_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS11_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS11_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS11_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS11_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS11_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS11_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS11_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS11_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS11_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS11_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS11_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS11_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS11_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS11_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS11_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS11_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS11_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS11_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS11_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS11_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS11_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS11_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS11_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS11_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS11_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS11_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS11_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS11_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS11_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS11_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS11_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS11_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS11_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS11_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS11_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS11_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS11_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS11_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS11_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS11_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS11_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS11_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS11_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS11_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS11_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS11_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS11_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS11_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS11_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS11_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS11_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS11_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS11_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS11_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS11_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS11_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS11_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS11_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS11_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS11_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS11_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS11_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS11_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS11_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS11_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS11_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS11_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS11_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS11_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS11_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS11_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS11_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS11_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS11_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS11_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS11_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS11_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS11_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS11_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS11_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS11_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS11_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS11_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS11_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS11_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS11_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS11_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS11_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS11_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS11_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS11_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS11_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS11_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS11_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS11_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS11_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS11_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS11_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS12_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS12_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS12_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS12_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS12_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS12_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS12_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS12_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS12_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS12_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS12_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS12_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS12_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS12_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS12_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS12_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS12_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS12_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS12_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS12_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS12_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS12_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS12_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS12_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS12_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS12_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS12_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS12_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS12_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS12_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS12_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS12_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS12_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS12_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS12_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS12_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS12_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS12_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS12_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS12_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS12_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS12_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS12_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS12_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS12_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS12_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS12_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS12_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS12_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS12_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS12_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS12_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS12_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS12_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS12_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS12_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS12_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS12_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS12_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS12_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS12_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS12_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS12_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS12_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS12_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS12_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS12_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS12_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS12_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS12_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS12_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS12_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS12_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS12_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS12_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS12_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS12_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS12_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS12_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS12_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS12_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS12_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS12_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS12_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS12_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS12_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS12_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS12_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS12_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS12_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS12_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS12_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS12_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS12_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS12_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS12_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS12_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS12_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS12_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS12_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS12_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS12_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS12_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS12_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS12_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS12_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS12_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS12_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS12_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS12_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS12_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS12_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS12_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS12_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS12_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS12_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS12_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS12_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS12_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS12_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS13_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS13_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS13_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS13_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS13_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS13_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS13_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS13_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS13_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS13_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS13_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS13_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS13_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS13_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS13_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS13_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS13_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS13_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS13_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS13_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS13_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS13_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS13_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS13_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS13_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS13_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS13_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS13_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS13_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS13_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS13_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS13_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS13_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS13_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS13_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS13_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS13_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS13_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS13_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS13_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS13_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS13_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS13_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS13_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS13_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS13_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS13_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS13_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS13_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS13_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS13_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS13_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS13_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS13_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS13_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS13_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS13_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS13_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS13_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS13_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS13_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS13_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS13_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS13_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS13_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS13_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS13_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS13_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS13_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS13_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS13_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS13_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS13_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS13_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS13_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS13_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS13_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS13_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS13_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS13_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS13_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS13_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS13_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS13_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS13_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS13_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS13_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS13_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS13_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS13_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS13_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS13_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS13_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS13_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS13_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS13_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS13_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS13_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS13_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS13_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS13_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS13_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS13_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS13_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS13_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS13_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS13_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS13_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS13_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS13_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS13_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS13_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS13_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS13_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS13_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS13_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS13_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS13_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS13_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS13_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME4_CME_SCOM_QFMR_TIMEBASE = 0 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_QFMR_TIMEBASE_LEN = 32 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_QFMR_CYCLES = 32 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_QFMR_CYCLES_LEN = 32 ;
+
+static const uint8_t P9N2_PU_CME3_CME_SCOM_QFMR_TIMEBASE = 0 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_QFMR_TIMEBASE_LEN = 32 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_QFMR_CYCLES = 32 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_QFMR_CYCLES_LEN = 32 ;
+
+static const uint8_t P9N2_PU_CME11_CME_SCOM_QFMR_TIMEBASE = 0 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_QFMR_TIMEBASE_LEN = 32 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_QFMR_CYCLES = 32 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_QFMR_CYCLES_LEN = 32 ;
+
+static const uint8_t P9N2_PU_CME2_CME_SCOM_QFMR_TIMEBASE = 0 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_QFMR_TIMEBASE_LEN = 32 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_QFMR_CYCLES = 32 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_QFMR_CYCLES_LEN = 32 ;
+
+static const uint8_t P9N2_PU_CME5_CME_SCOM_QFMR_TIMEBASE = 0 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_QFMR_TIMEBASE_LEN = 32 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_QFMR_CYCLES = 32 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_QFMR_CYCLES_LEN = 32 ;
+
+static const uint8_t P9N2_PU_CME9_CME_SCOM_QFMR_TIMEBASE = 0 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_QFMR_TIMEBASE_LEN = 32 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_QFMR_CYCLES = 32 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_QFMR_CYCLES_LEN = 32 ;
+
+static const uint8_t P9N2_PU_CME6_CME_SCOM_QFMR_TIMEBASE = 0 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_QFMR_TIMEBASE_LEN = 32 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_QFMR_CYCLES = 32 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_QFMR_CYCLES_LEN = 32 ;
+
+static const uint8_t P9N2_PU_CME10_CME_SCOM_QFMR_TIMEBASE = 0 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_QFMR_TIMEBASE_LEN = 32 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_QFMR_CYCLES = 32 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_QFMR_CYCLES_LEN = 32 ;
+
+static const uint8_t P9N2_PU_CME8_CME_SCOM_QFMR_TIMEBASE = 0 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_QFMR_TIMEBASE_LEN = 32 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_QFMR_CYCLES = 32 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_QFMR_CYCLES_LEN = 32 ;
+
+static const uint8_t P9N2_PU_CME1_CME_SCOM_QFMR_TIMEBASE = 0 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_QFMR_TIMEBASE_LEN = 32 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_QFMR_CYCLES = 32 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_QFMR_CYCLES_LEN = 32 ;
+
+static const uint8_t P9N2_PU_CME0_CME_SCOM_QFMR_TIMEBASE = 0 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_QFMR_TIMEBASE_LEN = 32 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_QFMR_CYCLES = 32 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_QFMR_CYCLES_LEN = 32 ;
+
+static const uint8_t P9N2_PU_CME7_CME_SCOM_QFMR_TIMEBASE = 0 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_QFMR_TIMEBASE_LEN = 32 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_QFMR_CYCLES = 32 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_QFMR_CYCLES_LEN = 32 ;
+
+static const uint8_t P9N2_PU_CME4_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT = 0 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT_LEN = 24 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT = 24 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT_LEN = 8 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_QIDSR_DROPOUT_SAMPLE = 32 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_QIDSR_DROPOUT_SAMPLE_LEN = 3 ;
+
+static const uint8_t P9N2_PU_CME3_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT = 0 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT_LEN = 24 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT = 24 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT_LEN = 8 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_QIDSR_DROPOUT_SAMPLE = 32 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_QIDSR_DROPOUT_SAMPLE_LEN = 3 ;
+
+static const uint8_t P9N2_PU_CME11_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT = 0 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT_LEN = 24 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT = 24 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT_LEN = 8 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_QIDSR_DROPOUT_SAMPLE = 32 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_QIDSR_DROPOUT_SAMPLE_LEN = 3 ;
+
+static const uint8_t P9N2_PU_CME2_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT = 0 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT_LEN = 24 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT = 24 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT_LEN = 8 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_QIDSR_DROPOUT_SAMPLE = 32 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_QIDSR_DROPOUT_SAMPLE_LEN = 3 ;
+
+static const uint8_t P9N2_PU_CME5_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT = 0 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT_LEN = 24 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT = 24 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT_LEN = 8 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_QIDSR_DROPOUT_SAMPLE = 32 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_QIDSR_DROPOUT_SAMPLE_LEN = 3 ;
+
+static const uint8_t P9N2_PU_CME9_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT = 0 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT_LEN = 24 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT = 24 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT_LEN = 8 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_QIDSR_DROPOUT_SAMPLE = 32 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_QIDSR_DROPOUT_SAMPLE_LEN = 3 ;
+
+static const uint8_t P9N2_PU_CME6_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT = 0 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT_LEN = 24 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT = 24 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT_LEN = 8 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_QIDSR_DROPOUT_SAMPLE = 32 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_QIDSR_DROPOUT_SAMPLE_LEN = 3 ;
+
+static const uint8_t P9N2_PU_CME10_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT = 0 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT_LEN = 24 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT = 24 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT_LEN = 8 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_QIDSR_DROPOUT_SAMPLE = 32 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_QIDSR_DROPOUT_SAMPLE_LEN = 3 ;
+
+static const uint8_t P9N2_PU_CME8_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT = 0 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT_LEN = 24 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT = 24 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT_LEN = 8 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_QIDSR_DROPOUT_SAMPLE = 32 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_QIDSR_DROPOUT_SAMPLE_LEN = 3 ;
+
+static const uint8_t P9N2_PU_CME1_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT = 0 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT_LEN = 24 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT = 24 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT_LEN = 8 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_QIDSR_DROPOUT_SAMPLE = 32 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_QIDSR_DROPOUT_SAMPLE_LEN = 3 ;
+
+static const uint8_t P9N2_PU_CME0_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT = 0 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT_LEN = 24 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT = 24 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT_LEN = 8 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_QIDSR_DROPOUT_SAMPLE = 32 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_QIDSR_DROPOUT_SAMPLE_LEN = 3 ;
+
+static const uint8_t P9N2_PU_CME7_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT = 0 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT_LEN = 24 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT = 24 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT_LEN = 8 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_QIDSR_DROPOUT_SAMPLE = 32 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_QIDSR_DROPOUT_SAMPLE_LEN = 3 ;
+
+static const uint8_t P9N2_PU_CME4_CME_SCOM_SICR_PM_ENTRY_ACK_C0 = 0 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_SICR_PM_ENTRY_ACK_C1 = 1 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C0 = 2 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C1 = 3 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_SICR_PM_EXIT_C0 = 4 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_SICR_PM_EXIT_C1 = 5 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0 = 6 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1 = 7 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0 = 8 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1 = 9 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_SICR_PCBMUX_REQ_C0 = 10 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_SICR_PCBMUX_REQ_C1 = 11 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_SICR_RESERVED_12_15 = 12 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_SICR_RESERVED_12_15_LEN = 4 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C0 = 16 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C1 = 17 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_SICR_L2_PURGE = 18 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_SICR_L2_PURGE_ABORT = 19 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_SICR_PC_THROTTLE_REQ = 20 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_SICR_NCU_TLBIE_QUIESCE = 21 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_SICR_NCU_PURGE = 22 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_SICR_NCU_PURGE_ABORT = 23 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_SICR_CHTM_PURGE_C0 = 24 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_SICR_CHTM_PURGE_C1 = 25 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_SICR_HMI_REQUEST_C0 = 26 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_SICR_HMI_REQUEST_C1 = 27 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_SICR_PPM_SPARE_OUT_C0 = 28 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_SICR_PPM_SPARE_OUT_C1 = 29 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_SICR_RESERVED_30_31 = 30 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_SICR_RESERVED_30_31_LEN = 2 ;
+
+static const uint8_t P9N2_PU_CME3_CME_SCOM_SICR_PM_ENTRY_ACK_C0 = 0 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_SICR_PM_ENTRY_ACK_C1 = 1 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C0 = 2 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C1 = 3 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_SICR_PM_EXIT_C0 = 4 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_SICR_PM_EXIT_C1 = 5 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0 = 6 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1 = 7 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0 = 8 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1 = 9 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_SICR_PCBMUX_REQ_C0 = 10 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_SICR_PCBMUX_REQ_C1 = 11 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_SICR_RESERVED_12_15 = 12 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_SICR_RESERVED_12_15_LEN = 4 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C0 = 16 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C1 = 17 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_SICR_L2_PURGE = 18 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_SICR_L2_PURGE_ABORT = 19 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_SICR_PC_THROTTLE_REQ = 20 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_SICR_NCU_TLBIE_QUIESCE = 21 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_SICR_NCU_PURGE = 22 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_SICR_NCU_PURGE_ABORT = 23 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_SICR_CHTM_PURGE_C0 = 24 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_SICR_CHTM_PURGE_C1 = 25 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_SICR_HMI_REQUEST_C0 = 26 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_SICR_HMI_REQUEST_C1 = 27 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_SICR_PPM_SPARE_OUT_C0 = 28 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_SICR_PPM_SPARE_OUT_C1 = 29 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_SICR_RESERVED_30_31 = 30 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_SICR_RESERVED_30_31_LEN = 2 ;
+
+static const uint8_t P9N2_PU_CME11_CME_SCOM_SICR_PM_ENTRY_ACK_C0 = 0 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_SICR_PM_ENTRY_ACK_C1 = 1 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C0 = 2 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C1 = 3 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_SICR_PM_EXIT_C0 = 4 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_SICR_PM_EXIT_C1 = 5 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0 = 6 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1 = 7 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0 = 8 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1 = 9 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_SICR_PCBMUX_REQ_C0 = 10 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_SICR_PCBMUX_REQ_C1 = 11 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_SICR_RESERVED_12_15 = 12 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_SICR_RESERVED_12_15_LEN = 4 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C0 = 16 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C1 = 17 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_SICR_L2_PURGE = 18 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_SICR_L2_PURGE_ABORT = 19 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_SICR_PC_THROTTLE_REQ = 20 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_SICR_NCU_TLBIE_QUIESCE = 21 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_SICR_NCU_PURGE = 22 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_SICR_NCU_PURGE_ABORT = 23 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_SICR_CHTM_PURGE_C0 = 24 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_SICR_CHTM_PURGE_C1 = 25 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_SICR_HMI_REQUEST_C0 = 26 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_SICR_HMI_REQUEST_C1 = 27 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_SICR_PPM_SPARE_OUT_C0 = 28 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_SICR_PPM_SPARE_OUT_C1 = 29 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_SICR_RESERVED_30_31 = 30 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_SICR_RESERVED_30_31_LEN = 2 ;
+
+static const uint8_t P9N2_PU_CME2_CME_SCOM_SICR_PM_ENTRY_ACK_C0 = 0 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_SICR_PM_ENTRY_ACK_C1 = 1 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C0 = 2 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C1 = 3 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_SICR_PM_EXIT_C0 = 4 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_SICR_PM_EXIT_C1 = 5 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0 = 6 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1 = 7 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0 = 8 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1 = 9 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_SICR_PCBMUX_REQ_C0 = 10 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_SICR_PCBMUX_REQ_C1 = 11 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_SICR_RESERVED_12_15 = 12 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_SICR_RESERVED_12_15_LEN = 4 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C0 = 16 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C1 = 17 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_SICR_L2_PURGE = 18 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_SICR_L2_PURGE_ABORT = 19 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_SICR_PC_THROTTLE_REQ = 20 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_SICR_NCU_TLBIE_QUIESCE = 21 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_SICR_NCU_PURGE = 22 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_SICR_NCU_PURGE_ABORT = 23 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_SICR_CHTM_PURGE_C0 = 24 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_SICR_CHTM_PURGE_C1 = 25 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_SICR_HMI_REQUEST_C0 = 26 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_SICR_HMI_REQUEST_C1 = 27 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_SICR_PPM_SPARE_OUT_C0 = 28 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_SICR_PPM_SPARE_OUT_C1 = 29 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_SICR_RESERVED_30_31 = 30 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_SICR_RESERVED_30_31_LEN = 2 ;
+
+static const uint8_t P9N2_PU_CME5_CME_SCOM_SICR_PM_ENTRY_ACK_C0 = 0 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_SICR_PM_ENTRY_ACK_C1 = 1 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C0 = 2 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C1 = 3 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_SICR_PM_EXIT_C0 = 4 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_SICR_PM_EXIT_C1 = 5 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0 = 6 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1 = 7 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0 = 8 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1 = 9 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_SICR_PCBMUX_REQ_C0 = 10 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_SICR_PCBMUX_REQ_C1 = 11 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_SICR_RESERVED_12_15 = 12 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_SICR_RESERVED_12_15_LEN = 4 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C0 = 16 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C1 = 17 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_SICR_L2_PURGE = 18 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_SICR_L2_PURGE_ABORT = 19 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_SICR_PC_THROTTLE_REQ = 20 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_SICR_NCU_TLBIE_QUIESCE = 21 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_SICR_NCU_PURGE = 22 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_SICR_NCU_PURGE_ABORT = 23 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_SICR_CHTM_PURGE_C0 = 24 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_SICR_CHTM_PURGE_C1 = 25 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_SICR_HMI_REQUEST_C0 = 26 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_SICR_HMI_REQUEST_C1 = 27 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_SICR_PPM_SPARE_OUT_C0 = 28 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_SICR_PPM_SPARE_OUT_C1 = 29 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_SICR_RESERVED_30_31 = 30 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_SICR_RESERVED_30_31_LEN = 2 ;
+
+static const uint8_t P9N2_PU_CME9_CME_SCOM_SICR_PM_ENTRY_ACK_C0 = 0 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_SICR_PM_ENTRY_ACK_C1 = 1 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C0 = 2 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C1 = 3 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_SICR_PM_EXIT_C0 = 4 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_SICR_PM_EXIT_C1 = 5 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0 = 6 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1 = 7 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0 = 8 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1 = 9 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_SICR_PCBMUX_REQ_C0 = 10 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_SICR_PCBMUX_REQ_C1 = 11 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_SICR_RESERVED_12_15 = 12 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_SICR_RESERVED_12_15_LEN = 4 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C0 = 16 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C1 = 17 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_SICR_L2_PURGE = 18 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_SICR_L2_PURGE_ABORT = 19 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_SICR_PC_THROTTLE_REQ = 20 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_SICR_NCU_TLBIE_QUIESCE = 21 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_SICR_NCU_PURGE = 22 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_SICR_NCU_PURGE_ABORT = 23 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_SICR_CHTM_PURGE_C0 = 24 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_SICR_CHTM_PURGE_C1 = 25 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_SICR_HMI_REQUEST_C0 = 26 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_SICR_HMI_REQUEST_C1 = 27 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_SICR_PPM_SPARE_OUT_C0 = 28 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_SICR_PPM_SPARE_OUT_C1 = 29 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_SICR_RESERVED_30_31 = 30 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_SICR_RESERVED_30_31_LEN = 2 ;
+
+static const uint8_t P9N2_PU_CME6_CME_SCOM_SICR_PM_ENTRY_ACK_C0 = 0 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_SICR_PM_ENTRY_ACK_C1 = 1 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C0 = 2 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C1 = 3 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_SICR_PM_EXIT_C0 = 4 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_SICR_PM_EXIT_C1 = 5 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0 = 6 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1 = 7 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0 = 8 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1 = 9 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_SICR_PCBMUX_REQ_C0 = 10 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_SICR_PCBMUX_REQ_C1 = 11 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_SICR_RESERVED_12_15 = 12 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_SICR_RESERVED_12_15_LEN = 4 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C0 = 16 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C1 = 17 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_SICR_L2_PURGE = 18 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_SICR_L2_PURGE_ABORT = 19 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_SICR_PC_THROTTLE_REQ = 20 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_SICR_NCU_TLBIE_QUIESCE = 21 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_SICR_NCU_PURGE = 22 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_SICR_NCU_PURGE_ABORT = 23 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_SICR_CHTM_PURGE_C0 = 24 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_SICR_CHTM_PURGE_C1 = 25 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_SICR_HMI_REQUEST_C0 = 26 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_SICR_HMI_REQUEST_C1 = 27 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_SICR_PPM_SPARE_OUT_C0 = 28 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_SICR_PPM_SPARE_OUT_C1 = 29 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_SICR_RESERVED_30_31 = 30 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_SICR_RESERVED_30_31_LEN = 2 ;
+
+static const uint8_t P9N2_PU_CME10_CME_SCOM_SICR_PM_ENTRY_ACK_C0 = 0 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_SICR_PM_ENTRY_ACK_C1 = 1 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C0 = 2 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C1 = 3 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_SICR_PM_EXIT_C0 = 4 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_SICR_PM_EXIT_C1 = 5 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0 = 6 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1 = 7 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0 = 8 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1 = 9 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_SICR_PCBMUX_REQ_C0 = 10 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_SICR_PCBMUX_REQ_C1 = 11 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_SICR_RESERVED_12_15 = 12 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_SICR_RESERVED_12_15_LEN = 4 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C0 = 16 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C1 = 17 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_SICR_L2_PURGE = 18 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_SICR_L2_PURGE_ABORT = 19 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_SICR_PC_THROTTLE_REQ = 20 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_SICR_NCU_TLBIE_QUIESCE = 21 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_SICR_NCU_PURGE = 22 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_SICR_NCU_PURGE_ABORT = 23 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_SICR_CHTM_PURGE_C0 = 24 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_SICR_CHTM_PURGE_C1 = 25 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_SICR_HMI_REQUEST_C0 = 26 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_SICR_HMI_REQUEST_C1 = 27 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_SICR_PPM_SPARE_OUT_C0 = 28 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_SICR_PPM_SPARE_OUT_C1 = 29 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_SICR_RESERVED_30_31 = 30 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_SICR_RESERVED_30_31_LEN = 2 ;
+
+static const uint8_t P9N2_PU_CME8_CME_SCOM_SICR_PM_ENTRY_ACK_C0 = 0 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_SICR_PM_ENTRY_ACK_C1 = 1 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C0 = 2 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C1 = 3 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_SICR_PM_EXIT_C0 = 4 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_SICR_PM_EXIT_C1 = 5 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0 = 6 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1 = 7 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0 = 8 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1 = 9 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_SICR_PCBMUX_REQ_C0 = 10 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_SICR_PCBMUX_REQ_C1 = 11 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_SICR_RESERVED_12_15 = 12 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_SICR_RESERVED_12_15_LEN = 4 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C0 = 16 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C1 = 17 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_SICR_L2_PURGE = 18 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_SICR_L2_PURGE_ABORT = 19 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_SICR_PC_THROTTLE_REQ = 20 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_SICR_NCU_TLBIE_QUIESCE = 21 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_SICR_NCU_PURGE = 22 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_SICR_NCU_PURGE_ABORT = 23 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_SICR_CHTM_PURGE_C0 = 24 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_SICR_CHTM_PURGE_C1 = 25 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_SICR_HMI_REQUEST_C0 = 26 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_SICR_HMI_REQUEST_C1 = 27 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_SICR_PPM_SPARE_OUT_C0 = 28 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_SICR_PPM_SPARE_OUT_C1 = 29 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_SICR_RESERVED_30_31 = 30 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_SICR_RESERVED_30_31_LEN = 2 ;
+
+static const uint8_t P9N2_PU_CME1_CME_SCOM_SICR_PM_ENTRY_ACK_C0 = 0 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_SICR_PM_ENTRY_ACK_C1 = 1 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C0 = 2 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C1 = 3 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_SICR_PM_EXIT_C0 = 4 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_SICR_PM_EXIT_C1 = 5 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0 = 6 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1 = 7 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0 = 8 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1 = 9 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_SICR_PCBMUX_REQ_C0 = 10 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_SICR_PCBMUX_REQ_C1 = 11 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_SICR_RESERVED_12_15 = 12 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_SICR_RESERVED_12_15_LEN = 4 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C0 = 16 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C1 = 17 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_SICR_L2_PURGE = 18 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_SICR_L2_PURGE_ABORT = 19 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_SICR_PC_THROTTLE_REQ = 20 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_SICR_NCU_TLBIE_QUIESCE = 21 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_SICR_NCU_PURGE = 22 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_SICR_NCU_PURGE_ABORT = 23 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_SICR_CHTM_PURGE_C0 = 24 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_SICR_CHTM_PURGE_C1 = 25 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_SICR_HMI_REQUEST_C0 = 26 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_SICR_HMI_REQUEST_C1 = 27 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_SICR_PPM_SPARE_OUT_C0 = 28 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_SICR_PPM_SPARE_OUT_C1 = 29 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_SICR_RESERVED_30_31 = 30 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_SICR_RESERVED_30_31_LEN = 2 ;
+
+static const uint8_t P9N2_PU_CME0_CME_SCOM_SICR_PM_ENTRY_ACK_C0 = 0 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_SICR_PM_ENTRY_ACK_C1 = 1 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C0 = 2 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C1 = 3 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_SICR_PM_EXIT_C0 = 4 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_SICR_PM_EXIT_C1 = 5 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0 = 6 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1 = 7 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0 = 8 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1 = 9 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_SICR_PCBMUX_REQ_C0 = 10 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_SICR_PCBMUX_REQ_C1 = 11 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_SICR_RESERVED_12_15 = 12 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_SICR_RESERVED_12_15_LEN = 4 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C0 = 16 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C1 = 17 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_SICR_L2_PURGE = 18 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_SICR_L2_PURGE_ABORT = 19 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_SICR_PC_THROTTLE_REQ = 20 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_SICR_NCU_TLBIE_QUIESCE = 21 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_SICR_NCU_PURGE = 22 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_SICR_NCU_PURGE_ABORT = 23 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_SICR_CHTM_PURGE_C0 = 24 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_SICR_CHTM_PURGE_C1 = 25 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_SICR_HMI_REQUEST_C0 = 26 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_SICR_HMI_REQUEST_C1 = 27 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_SICR_PPM_SPARE_OUT_C0 = 28 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_SICR_PPM_SPARE_OUT_C1 = 29 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_SICR_RESERVED_30_31 = 30 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_SICR_RESERVED_30_31_LEN = 2 ;
+
+static const uint8_t P9N2_PU_CME7_CME_SCOM_SICR_PM_ENTRY_ACK_C0 = 0 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_SICR_PM_ENTRY_ACK_C1 = 1 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C0 = 2 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C1 = 3 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_SICR_PM_EXIT_C0 = 4 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_SICR_PM_EXIT_C1 = 5 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0 = 6 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1 = 7 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0 = 8 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1 = 9 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_SICR_PCBMUX_REQ_C0 = 10 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_SICR_PCBMUX_REQ_C1 = 11 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_SICR_RESERVED_12_15 = 12 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_SICR_RESERVED_12_15_LEN = 4 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C0 = 16 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C1 = 17 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_SICR_L2_PURGE = 18 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_SICR_L2_PURGE_ABORT = 19 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_SICR_PC_THROTTLE_REQ = 20 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_SICR_NCU_TLBIE_QUIESCE = 21 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_SICR_NCU_PURGE = 22 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_SICR_NCU_PURGE_ABORT = 23 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_SICR_CHTM_PURGE_C0 = 24 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_SICR_CHTM_PURGE_C1 = 25 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_SICR_HMI_REQUEST_C0 = 26 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_SICR_HMI_REQUEST_C1 = 27 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_SICR_PPM_SPARE_OUT_C0 = 28 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_SICR_PPM_SPARE_OUT_C1 = 29 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_SICR_RESERVED_30_31 = 30 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_SICR_RESERVED_30_31_LEN = 2 ;
+
+static const uint8_t P9N2_PU_CME4_CME_SCOM_SRTCH0_DATA = 0 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_SRTCH0_DATA_LEN = 32 ;
+
+static const uint8_t P9N2_PU_CME3_CME_SCOM_SRTCH0_DATA = 0 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_SRTCH0_DATA_LEN = 32 ;
+
+static const uint8_t P9N2_PU_CME11_CME_SCOM_SRTCH0_DATA = 0 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_SRTCH0_DATA_LEN = 32 ;
+
+static const uint8_t P9N2_PU_CME2_CME_SCOM_SRTCH0_DATA = 0 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_SRTCH0_DATA_LEN = 32 ;
+
+static const uint8_t P9N2_PU_CME5_CME_SCOM_SRTCH0_DATA = 0 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_SRTCH0_DATA_LEN = 32 ;
+
+static const uint8_t P9N2_PU_CME9_CME_SCOM_SRTCH0_DATA = 0 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_SRTCH0_DATA_LEN = 32 ;
+
+static const uint8_t P9N2_PU_CME6_CME_SCOM_SRTCH0_DATA = 0 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_SRTCH0_DATA_LEN = 32 ;
+
+static const uint8_t P9N2_PU_CME10_CME_SCOM_SRTCH0_DATA = 0 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_SRTCH0_DATA_LEN = 32 ;
+
+static const uint8_t P9N2_PU_CME8_CME_SCOM_SRTCH0_DATA = 0 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_SRTCH0_DATA_LEN = 32 ;
+
+static const uint8_t P9N2_PU_CME1_CME_SCOM_SRTCH0_DATA = 0 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_SRTCH0_DATA_LEN = 32 ;
+
+static const uint8_t P9N2_PU_CME0_CME_SCOM_SRTCH0_DATA = 0 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_SRTCH0_DATA_LEN = 32 ;
+
+static const uint8_t P9N2_PU_CME7_CME_SCOM_SRTCH0_DATA = 0 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_SRTCH0_DATA_LEN = 32 ;
+
+static const uint8_t P9N2_PU_CME4_CME_SCOM_SRTCH1_DATA = 0 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_SRTCH1_DATA_LEN = 32 ;
+
+static const uint8_t P9N2_PU_CME3_CME_SCOM_SRTCH1_DATA = 0 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_SRTCH1_DATA_LEN = 32 ;
+
+static const uint8_t P9N2_PU_CME11_CME_SCOM_SRTCH1_DATA = 0 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_SRTCH1_DATA_LEN = 32 ;
+
+static const uint8_t P9N2_PU_CME2_CME_SCOM_SRTCH1_DATA = 0 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_SRTCH1_DATA_LEN = 32 ;
+
+static const uint8_t P9N2_PU_CME5_CME_SCOM_SRTCH1_DATA = 0 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_SRTCH1_DATA_LEN = 32 ;
+
+static const uint8_t P9N2_PU_CME9_CME_SCOM_SRTCH1_DATA = 0 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_SRTCH1_DATA_LEN = 32 ;
+
+static const uint8_t P9N2_PU_CME6_CME_SCOM_SRTCH1_DATA = 0 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_SRTCH1_DATA_LEN = 32 ;
+
+static const uint8_t P9N2_PU_CME10_CME_SCOM_SRTCH1_DATA = 0 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_SRTCH1_DATA_LEN = 32 ;
+
+static const uint8_t P9N2_PU_CME8_CME_SCOM_SRTCH1_DATA = 0 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_SRTCH1_DATA_LEN = 32 ;
+
+static const uint8_t P9N2_PU_CME1_CME_SCOM_SRTCH1_DATA = 0 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_SRTCH1_DATA_LEN = 32 ;
+
+static const uint8_t P9N2_PU_CME0_CME_SCOM_SRTCH1_DATA = 0 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_SRTCH1_DATA_LEN = 32 ;
+
+static const uint8_t P9N2_PU_CME7_CME_SCOM_SRTCH1_DATA = 0 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_SRTCH1_DATA_LEN = 32 ;
+
+static const uint8_t P9N2_PU_CME4_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD = 0 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD_LEN = 16 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD = 16 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD_LEN = 12 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD = 28 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD_LEN = 8 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_VCCR_DROOP_PROFILE_TYPE = 36 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_VCCR_DROOP_PROFILE_TYPE_LEN = 2 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_VCCR_DROOP_TIMER_MODE = 38 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_VCCR_DROOP_CHAR_MODE = 39 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_VCCR_DROOP_NOTIFY_ENABLE = 40 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_VCCR_SPARE41_43 = 41 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_VCCR_SPARE41_43_LEN = 3 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_VCCR_DROOP_SAMPLE_RATE = 59 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_VCCR_DROOP_SAMPLE_RATE_LEN = 5 ;
+
+static const uint8_t P9N2_PU_CME3_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD = 0 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD_LEN = 16 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD = 16 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD_LEN = 12 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD = 28 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD_LEN = 8 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_VCCR_DROOP_PROFILE_TYPE = 36 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_VCCR_DROOP_PROFILE_TYPE_LEN = 2 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_VCCR_DROOP_TIMER_MODE = 38 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_VCCR_DROOP_CHAR_MODE = 39 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_VCCR_DROOP_NOTIFY_ENABLE = 40 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_VCCR_SPARE41_43 = 41 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_VCCR_SPARE41_43_LEN = 3 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_VCCR_DROOP_SAMPLE_RATE = 59 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_VCCR_DROOP_SAMPLE_RATE_LEN = 5 ;
+
+static const uint8_t P9N2_PU_CME11_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD = 0 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD_LEN = 16 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD = 16 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD_LEN = 12 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD = 28 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD_LEN = 8 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_VCCR_DROOP_PROFILE_TYPE = 36 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_VCCR_DROOP_PROFILE_TYPE_LEN = 2 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_VCCR_DROOP_TIMER_MODE = 38 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_VCCR_DROOP_CHAR_MODE = 39 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_VCCR_DROOP_NOTIFY_ENABLE = 40 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_VCCR_SPARE41_43 = 41 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_VCCR_SPARE41_43_LEN = 3 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_VCCR_DROOP_SAMPLE_RATE = 59 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_VCCR_DROOP_SAMPLE_RATE_LEN = 5 ;
+
+static const uint8_t P9N2_PU_CME2_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD = 0 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD_LEN = 16 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD = 16 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD_LEN = 12 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD = 28 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD_LEN = 8 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_VCCR_DROOP_PROFILE_TYPE = 36 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_VCCR_DROOP_PROFILE_TYPE_LEN = 2 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_VCCR_DROOP_TIMER_MODE = 38 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_VCCR_DROOP_CHAR_MODE = 39 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_VCCR_DROOP_NOTIFY_ENABLE = 40 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_VCCR_SPARE41_43 = 41 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_VCCR_SPARE41_43_LEN = 3 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_VCCR_DROOP_SAMPLE_RATE = 59 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_VCCR_DROOP_SAMPLE_RATE_LEN = 5 ;
+
+static const uint8_t P9N2_PU_CME5_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD = 0 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD_LEN = 16 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD = 16 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD_LEN = 12 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD = 28 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD_LEN = 8 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_VCCR_DROOP_PROFILE_TYPE = 36 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_VCCR_DROOP_PROFILE_TYPE_LEN = 2 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_VCCR_DROOP_TIMER_MODE = 38 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_VCCR_DROOP_CHAR_MODE = 39 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_VCCR_DROOP_NOTIFY_ENABLE = 40 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_VCCR_SPARE41_43 = 41 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_VCCR_SPARE41_43_LEN = 3 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_VCCR_DROOP_SAMPLE_RATE = 59 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_VCCR_DROOP_SAMPLE_RATE_LEN = 5 ;
+
+static const uint8_t P9N2_PU_CME9_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD = 0 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD_LEN = 16 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD = 16 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD_LEN = 12 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD = 28 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD_LEN = 8 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_VCCR_DROOP_PROFILE_TYPE = 36 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_VCCR_DROOP_PROFILE_TYPE_LEN = 2 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_VCCR_DROOP_TIMER_MODE = 38 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_VCCR_DROOP_CHAR_MODE = 39 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_VCCR_DROOP_NOTIFY_ENABLE = 40 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_VCCR_SPARE41_43 = 41 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_VCCR_SPARE41_43_LEN = 3 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_VCCR_DROOP_SAMPLE_RATE = 59 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_VCCR_DROOP_SAMPLE_RATE_LEN = 5 ;
+
+static const uint8_t P9N2_PU_CME6_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD = 0 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD_LEN = 16 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD = 16 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD_LEN = 12 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD = 28 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD_LEN = 8 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_VCCR_DROOP_PROFILE_TYPE = 36 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_VCCR_DROOP_PROFILE_TYPE_LEN = 2 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_VCCR_DROOP_TIMER_MODE = 38 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_VCCR_DROOP_CHAR_MODE = 39 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_VCCR_DROOP_NOTIFY_ENABLE = 40 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_VCCR_SPARE41_43 = 41 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_VCCR_SPARE41_43_LEN = 3 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_VCCR_DROOP_SAMPLE_RATE = 59 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_VCCR_DROOP_SAMPLE_RATE_LEN = 5 ;
+
+static const uint8_t P9N2_PU_CME10_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD = 0 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD_LEN = 16 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD = 16 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD_LEN = 12 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD = 28 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD_LEN = 8 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_VCCR_DROOP_PROFILE_TYPE = 36 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_VCCR_DROOP_PROFILE_TYPE_LEN = 2 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_VCCR_DROOP_TIMER_MODE = 38 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_VCCR_DROOP_CHAR_MODE = 39 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_VCCR_DROOP_NOTIFY_ENABLE = 40 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_VCCR_SPARE41_43 = 41 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_VCCR_SPARE41_43_LEN = 3 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_VCCR_DROOP_SAMPLE_RATE = 59 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_VCCR_DROOP_SAMPLE_RATE_LEN = 5 ;
+
+static const uint8_t P9N2_PU_CME8_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD = 0 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD_LEN = 16 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD = 16 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD_LEN = 12 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD = 28 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD_LEN = 8 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_VCCR_DROOP_PROFILE_TYPE = 36 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_VCCR_DROOP_PROFILE_TYPE_LEN = 2 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_VCCR_DROOP_TIMER_MODE = 38 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_VCCR_DROOP_CHAR_MODE = 39 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_VCCR_DROOP_NOTIFY_ENABLE = 40 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_VCCR_SPARE41_43 = 41 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_VCCR_SPARE41_43_LEN = 3 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_VCCR_DROOP_SAMPLE_RATE = 59 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_VCCR_DROOP_SAMPLE_RATE_LEN = 5 ;
+
+static const uint8_t P9N2_PU_CME1_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD = 0 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD_LEN = 16 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD = 16 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD_LEN = 12 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD = 28 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD_LEN = 8 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_VCCR_DROOP_PROFILE_TYPE = 36 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_VCCR_DROOP_PROFILE_TYPE_LEN = 2 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_VCCR_DROOP_TIMER_MODE = 38 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_VCCR_DROOP_CHAR_MODE = 39 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_VCCR_DROOP_NOTIFY_ENABLE = 40 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_VCCR_SPARE41_43 = 41 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_VCCR_SPARE41_43_LEN = 3 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_VCCR_DROOP_SAMPLE_RATE = 59 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_VCCR_DROOP_SAMPLE_RATE_LEN = 5 ;
+
+static const uint8_t P9N2_PU_CME0_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD = 0 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD_LEN = 16 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD = 16 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD_LEN = 12 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD = 28 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD_LEN = 8 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_VCCR_DROOP_PROFILE_TYPE = 36 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_VCCR_DROOP_PROFILE_TYPE_LEN = 2 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_VCCR_DROOP_TIMER_MODE = 38 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_VCCR_DROOP_CHAR_MODE = 39 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_VCCR_DROOP_NOTIFY_ENABLE = 40 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_VCCR_SPARE41_43 = 41 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_VCCR_SPARE41_43_LEN = 3 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_VCCR_DROOP_SAMPLE_RATE = 59 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_VCCR_DROOP_SAMPLE_RATE_LEN = 5 ;
+
+static const uint8_t P9N2_PU_CME7_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD = 0 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD_LEN = 16 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD = 16 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD_LEN = 12 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD = 28 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD_LEN = 8 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_VCCR_DROOP_PROFILE_TYPE = 36 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_VCCR_DROOP_PROFILE_TYPE_LEN = 2 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_VCCR_DROOP_TIMER_MODE = 38 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_VCCR_DROOP_CHAR_MODE = 39 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_VCCR_DROOP_NOTIFY_ENABLE = 40 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_VCCR_SPARE41_43 = 41 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_VCCR_SPARE41_43_LEN = 3 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_VCCR_DROOP_SAMPLE_RATE = 59 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_VCCR_DROOP_SAMPLE_RATE_LEN = 5 ;
+
+static const uint8_t P9N2_PU_CME4_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR = 0 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR_LEN = 16 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR = 16 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR_LEN = 24 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR = 40 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR_LEN = 24 ;
+
+static const uint8_t P9N2_PU_CME3_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR = 0 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR_LEN = 16 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR = 16 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR_LEN = 24 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR = 40 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR_LEN = 24 ;
+
+static const uint8_t P9N2_PU_CME11_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR = 0 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR_LEN = 16 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR = 16 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR_LEN = 24 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR = 40 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR_LEN = 24 ;
+
+static const uint8_t P9N2_PU_CME2_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR = 0 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR_LEN = 16 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR = 16 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR_LEN = 24 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR = 40 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR_LEN = 24 ;
+
+static const uint8_t P9N2_PU_CME5_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR = 0 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR_LEN = 16 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR = 16 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR_LEN = 24 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR = 40 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR_LEN = 24 ;
+
+static const uint8_t P9N2_PU_CME9_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR = 0 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR_LEN = 16 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR = 16 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR_LEN = 24 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR = 40 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR_LEN = 24 ;
+
+static const uint8_t P9N2_PU_CME6_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR = 0 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR_LEN = 16 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR = 16 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR_LEN = 24 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR = 40 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR_LEN = 24 ;
+
+static const uint8_t P9N2_PU_CME10_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR = 0 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR_LEN = 16 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR = 16 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR_LEN = 24 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR = 40 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR_LEN = 24 ;
+
+static const uint8_t P9N2_PU_CME8_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR = 0 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR_LEN = 16 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR = 16 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR_LEN = 24 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR = 40 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR_LEN = 24 ;
+
+static const uint8_t P9N2_PU_CME1_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR = 0 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR_LEN = 16 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR = 16 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR_LEN = 24 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR = 40 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR_LEN = 24 ;
+
+static const uint8_t P9N2_PU_CME0_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR = 0 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR_LEN = 16 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR = 16 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR_LEN = 24 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR = 40 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR_LEN = 24 ;
+
+static const uint8_t P9N2_PU_CME7_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR = 0 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR_LEN = 16 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR = 16 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR_LEN = 24 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR = 40 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR_LEN = 24 ;
+
+static const uint8_t P9N2_PU_CME4_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY = 0 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY_LEN = 4 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA = 4 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA = 8 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA = 12 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA = 16 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA = 20 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY = 32 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY_LEN = 4 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA = 36 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA = 40 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA = 44 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA = 48 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA = 52 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME3_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY = 0 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY_LEN = 4 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA = 4 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA = 8 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA = 12 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA = 16 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA = 20 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY = 32 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY_LEN = 4 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA = 36 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA = 40 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA = 44 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA = 48 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA = 52 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME11_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY = 0 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY_LEN = 4 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA = 4 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA = 8 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA = 12 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA = 16 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA = 20 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY = 32 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY_LEN = 4 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA = 36 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA = 40 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA = 44 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA = 48 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA = 52 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME2_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY = 0 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY_LEN = 4 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA = 4 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA = 8 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA = 12 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA = 16 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA = 20 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY = 32 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY_LEN = 4 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA = 36 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA = 40 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA = 44 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA = 48 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA = 52 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME5_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY = 0 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY_LEN = 4 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA = 4 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA = 8 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA = 12 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA = 16 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA = 20 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY = 32 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY_LEN = 4 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA = 36 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA = 40 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA = 44 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA = 48 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA = 52 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME9_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY = 0 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY_LEN = 4 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA = 4 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA = 8 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA = 12 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA = 16 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA = 20 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY = 32 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY_LEN = 4 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA = 36 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA = 40 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA = 44 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA = 48 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA = 52 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME6_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY = 0 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY_LEN = 4 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA = 4 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA = 8 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA = 12 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA = 16 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA = 20 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY = 32 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY_LEN = 4 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA = 36 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA = 40 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA = 44 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA = 48 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA = 52 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME10_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY = 0 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY_LEN = 4 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA = 4 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA = 8 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA = 12 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA = 16 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA = 20 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY = 32 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY_LEN = 4 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA = 36 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA = 40 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA = 44 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA = 48 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA = 52 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME8_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY = 0 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY_LEN = 4 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA = 4 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA = 8 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA = 12 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA = 16 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA = 20 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY = 32 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY_LEN = 4 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA = 36 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA = 40 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA = 44 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA = 48 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA = 52 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME1_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY = 0 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY_LEN = 4 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA = 4 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA = 8 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA = 12 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA = 16 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA = 20 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY = 32 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY_LEN = 4 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA = 36 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA = 40 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA = 44 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA = 48 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA = 52 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME0_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY = 0 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY_LEN = 4 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA = 4 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA = 8 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA = 12 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA = 16 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA = 20 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY = 32 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY_LEN = 4 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA = 36 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA = 40 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA = 44 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA = 48 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA = 52 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME7_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY = 0 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY_LEN = 4 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA = 4 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA = 8 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA = 12 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA = 16 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA = 20 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY = 32 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY_LEN = 4 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA = 36 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA = 40 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA = 44 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA = 48 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA = 52 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA_LEN = 4 ;
+
+static const uint8_t P9N2_PU_CME4_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR = 0 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR_LEN = 16 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR = 16 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR_LEN = 16 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR = 32 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR_LEN = 12 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR = 44 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR_LEN = 12 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR = 56 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR_LEN = 8 ;
+
+static const uint8_t P9N2_PU_CME3_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR = 0 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR_LEN = 16 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR = 16 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR_LEN = 16 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR = 32 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR_LEN = 12 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR = 44 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR_LEN = 12 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR = 56 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR_LEN = 8 ;
+
+static const uint8_t P9N2_PU_CME11_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR = 0 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR_LEN = 16 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR = 16 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR_LEN = 16 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR = 32 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR_LEN = 12 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR = 44 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR_LEN = 12 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR = 56 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR_LEN = 8 ;
+
+static const uint8_t P9N2_PU_CME2_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR = 0 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR_LEN = 16 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR = 16 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR_LEN = 16 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR = 32 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR_LEN = 12 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR = 44 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR_LEN = 12 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR = 56 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR_LEN = 8 ;
+
+static const uint8_t P9N2_PU_CME5_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR = 0 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR_LEN = 16 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR = 16 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR_LEN = 16 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR = 32 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR_LEN = 12 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR = 44 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR_LEN = 12 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR = 56 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR_LEN = 8 ;
+
+static const uint8_t P9N2_PU_CME9_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR = 0 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR_LEN = 16 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR = 16 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR_LEN = 16 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR = 32 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR_LEN = 12 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR = 44 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR_LEN = 12 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR = 56 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR_LEN = 8 ;
+
+static const uint8_t P9N2_PU_CME6_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR = 0 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR_LEN = 16 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR = 16 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR_LEN = 16 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR = 32 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR_LEN = 12 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR = 44 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR_LEN = 12 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR = 56 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR_LEN = 8 ;
+
+static const uint8_t P9N2_PU_CME10_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR = 0 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR_LEN = 16 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR = 16 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR_LEN = 16 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR = 32 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR_LEN = 12 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR = 44 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR_LEN = 12 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR = 56 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR_LEN = 8 ;
+
+static const uint8_t P9N2_PU_CME8_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR = 0 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR_LEN = 16 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR = 16 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR_LEN = 16 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR = 32 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR_LEN = 12 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR = 44 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR_LEN = 12 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR = 56 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR_LEN = 8 ;
+
+static const uint8_t P9N2_PU_CME1_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR = 0 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR_LEN = 16 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR = 16 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR_LEN = 16 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR = 32 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR_LEN = 12 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR = 44 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR_LEN = 12 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR = 56 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR_LEN = 8 ;
+
+static const uint8_t P9N2_PU_CME0_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR = 0 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR_LEN = 16 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR = 16 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR_LEN = 16 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR = 32 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR_LEN = 12 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR = 44 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR_LEN = 12 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR = 56 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR_LEN = 8 ;
+
+static const uint8_t P9N2_PU_CME7_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR = 0 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR_LEN = 16 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR = 16 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR_LEN = 16 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR = 32 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR_LEN = 12 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR = 44 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR_LEN = 12 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR = 56 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR_LEN = 8 ;
+
+static const uint8_t P9N2_PU_CME4_CME_SCOM_VNCR_VDM_NO_DROOP_CTR = 16 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_VNCR_VDM_NO_DROOP_CTR_LEN = 24 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_VNCR_VDM_OVERVOLT_CTR = 40 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_VNCR_VDM_OVERVOLT_CTR_LEN = 24 ;
+
+static const uint8_t P9N2_PU_CME3_CME_SCOM_VNCR_VDM_NO_DROOP_CTR = 16 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_VNCR_VDM_NO_DROOP_CTR_LEN = 24 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_VNCR_VDM_OVERVOLT_CTR = 40 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_VNCR_VDM_OVERVOLT_CTR_LEN = 24 ;
+
+static const uint8_t P9N2_PU_CME11_CME_SCOM_VNCR_VDM_NO_DROOP_CTR = 16 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_VNCR_VDM_NO_DROOP_CTR_LEN = 24 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_VNCR_VDM_OVERVOLT_CTR = 40 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_VNCR_VDM_OVERVOLT_CTR_LEN = 24 ;
+
+static const uint8_t P9N2_PU_CME2_CME_SCOM_VNCR_VDM_NO_DROOP_CTR = 16 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_VNCR_VDM_NO_DROOP_CTR_LEN = 24 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_VNCR_VDM_OVERVOLT_CTR = 40 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_VNCR_VDM_OVERVOLT_CTR_LEN = 24 ;
+
+static const uint8_t P9N2_PU_CME5_CME_SCOM_VNCR_VDM_NO_DROOP_CTR = 16 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_VNCR_VDM_NO_DROOP_CTR_LEN = 24 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_VNCR_VDM_OVERVOLT_CTR = 40 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_VNCR_VDM_OVERVOLT_CTR_LEN = 24 ;
+
+static const uint8_t P9N2_PU_CME9_CME_SCOM_VNCR_VDM_NO_DROOP_CTR = 16 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_VNCR_VDM_NO_DROOP_CTR_LEN = 24 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_VNCR_VDM_OVERVOLT_CTR = 40 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_VNCR_VDM_OVERVOLT_CTR_LEN = 24 ;
+
+static const uint8_t P9N2_PU_CME6_CME_SCOM_VNCR_VDM_NO_DROOP_CTR = 16 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_VNCR_VDM_NO_DROOP_CTR_LEN = 24 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_VNCR_VDM_OVERVOLT_CTR = 40 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_VNCR_VDM_OVERVOLT_CTR_LEN = 24 ;
+
+static const uint8_t P9N2_PU_CME10_CME_SCOM_VNCR_VDM_NO_DROOP_CTR = 16 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_VNCR_VDM_NO_DROOP_CTR_LEN = 24 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_VNCR_VDM_OVERVOLT_CTR = 40 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_VNCR_VDM_OVERVOLT_CTR_LEN = 24 ;
+
+static const uint8_t P9N2_PU_CME8_CME_SCOM_VNCR_VDM_NO_DROOP_CTR = 16 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_VNCR_VDM_NO_DROOP_CTR_LEN = 24 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_VNCR_VDM_OVERVOLT_CTR = 40 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_VNCR_VDM_OVERVOLT_CTR_LEN = 24 ;
+
+static const uint8_t P9N2_PU_CME1_CME_SCOM_VNCR_VDM_NO_DROOP_CTR = 16 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_VNCR_VDM_NO_DROOP_CTR_LEN = 24 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_VNCR_VDM_OVERVOLT_CTR = 40 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_VNCR_VDM_OVERVOLT_CTR_LEN = 24 ;
+
+static const uint8_t P9N2_PU_CME0_CME_SCOM_VNCR_VDM_NO_DROOP_CTR = 16 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_VNCR_VDM_NO_DROOP_CTR_LEN = 24 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_VNCR_VDM_OVERVOLT_CTR = 40 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_VNCR_VDM_OVERVOLT_CTR_LEN = 24 ;
+
+static const uint8_t P9N2_PU_CME7_CME_SCOM_VNCR_VDM_NO_DROOP_CTR = 16 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_VNCR_VDM_NO_DROOP_CTR_LEN = 24 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_VNCR_VDM_OVERVOLT_CTR = 40 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_VNCR_VDM_OVERVOLT_CTR_LEN = 24 ;
+
+static const uint8_t P9N2_PU_CME4_CME_SCOM_XIPCBMD0_PCBM_DATA = 0 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_XIPCBMD0_PCBM_DATA_LEN = 27 ;
+
+static const uint8_t P9N2_PU_CME3_CME_SCOM_XIPCBMD0_PCBM_DATA = 0 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_XIPCBMD0_PCBM_DATA_LEN = 27 ;
+
+static const uint8_t P9N2_PU_CME11_CME_SCOM_XIPCBMD0_PCBM_DATA = 0 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_XIPCBMD0_PCBM_DATA_LEN = 27 ;
+
+static const uint8_t P9N2_PU_CME2_CME_SCOM_XIPCBMD0_PCBM_DATA = 0 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_XIPCBMD0_PCBM_DATA_LEN = 27 ;
+
+static const uint8_t P9N2_PU_CME5_CME_SCOM_XIPCBMD0_PCBM_DATA = 0 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_XIPCBMD0_PCBM_DATA_LEN = 27 ;
+
+static const uint8_t P9N2_PU_CME9_CME_SCOM_XIPCBMD0_PCBM_DATA = 0 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_XIPCBMD0_PCBM_DATA_LEN = 27 ;
+
+static const uint8_t P9N2_PU_CME6_CME_SCOM_XIPCBMD0_PCBM_DATA = 0 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_XIPCBMD0_PCBM_DATA_LEN = 27 ;
+
+static const uint8_t P9N2_PU_CME10_CME_SCOM_XIPCBMD0_PCBM_DATA = 0 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_XIPCBMD0_PCBM_DATA_LEN = 27 ;
+
+static const uint8_t P9N2_PU_CME8_CME_SCOM_XIPCBMD0_PCBM_DATA = 0 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_XIPCBMD0_PCBM_DATA_LEN = 27 ;
+
+static const uint8_t P9N2_PU_CME1_CME_SCOM_XIPCBMD0_PCBM_DATA = 0 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_XIPCBMD0_PCBM_DATA_LEN = 27 ;
+
+static const uint8_t P9N2_PU_CME0_CME_SCOM_XIPCBMD0_PCBM_DATA = 0 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_XIPCBMD0_PCBM_DATA_LEN = 27 ;
+
+static const uint8_t P9N2_PU_CME7_CME_SCOM_XIPCBMD0_PCBM_DATA = 0 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_XIPCBMD0_PCBM_DATA_LEN = 27 ;
+
+static const uint8_t P9N2_PU_CME4_CME_SCOM_XIPCBMD1_PCBM_DATA = 0 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_XIPCBMD1_PCBM_DATA_LEN = 27 ;
+
+static const uint8_t P9N2_PU_CME3_CME_SCOM_XIPCBMD1_PCBM_DATA = 0 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_XIPCBMD1_PCBM_DATA_LEN = 27 ;
+
+static const uint8_t P9N2_PU_CME11_CME_SCOM_XIPCBMD1_PCBM_DATA = 0 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_XIPCBMD1_PCBM_DATA_LEN = 27 ;
+
+static const uint8_t P9N2_PU_CME2_CME_SCOM_XIPCBMD1_PCBM_DATA = 0 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_XIPCBMD1_PCBM_DATA_LEN = 27 ;
+
+static const uint8_t P9N2_PU_CME5_CME_SCOM_XIPCBMD1_PCBM_DATA = 0 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_XIPCBMD1_PCBM_DATA_LEN = 27 ;
+
+static const uint8_t P9N2_PU_CME9_CME_SCOM_XIPCBMD1_PCBM_DATA = 0 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_XIPCBMD1_PCBM_DATA_LEN = 27 ;
+
+static const uint8_t P9N2_PU_CME6_CME_SCOM_XIPCBMD1_PCBM_DATA = 0 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_XIPCBMD1_PCBM_DATA_LEN = 27 ;
+
+static const uint8_t P9N2_PU_CME10_CME_SCOM_XIPCBMD1_PCBM_DATA = 0 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_XIPCBMD1_PCBM_DATA_LEN = 27 ;
+
+static const uint8_t P9N2_PU_CME8_CME_SCOM_XIPCBMD1_PCBM_DATA = 0 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_XIPCBMD1_PCBM_DATA_LEN = 27 ;
+
+static const uint8_t P9N2_PU_CME1_CME_SCOM_XIPCBMD1_PCBM_DATA = 0 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_XIPCBMD1_PCBM_DATA_LEN = 27 ;
+
+static const uint8_t P9N2_PU_CME0_CME_SCOM_XIPCBMD1_PCBM_DATA = 0 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_XIPCBMD1_PCBM_DATA_LEN = 27 ;
+
+static const uint8_t P9N2_PU_CME7_CME_SCOM_XIPCBMD1_PCBM_DATA = 0 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_XIPCBMD1_PCBM_DATA_LEN = 27 ;
+
+static const uint8_t P9N2_PU_CME4_CME_SCOM_XIPCBMI0_PCBM_INFO = 0 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_XIPCBMI0_PCBM_INFO_LEN = 7 ;
+
+static const uint8_t P9N2_PU_CME3_CME_SCOM_XIPCBMI0_PCBM_INFO = 0 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_XIPCBMI0_PCBM_INFO_LEN = 7 ;
+
+static const uint8_t P9N2_PU_CME11_CME_SCOM_XIPCBMI0_PCBM_INFO = 0 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_XIPCBMI0_PCBM_INFO_LEN = 7 ;
+
+static const uint8_t P9N2_PU_CME2_CME_SCOM_XIPCBMI0_PCBM_INFO = 0 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_XIPCBMI0_PCBM_INFO_LEN = 7 ;
+
+static const uint8_t P9N2_PU_CME5_CME_SCOM_XIPCBMI0_PCBM_INFO = 0 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_XIPCBMI0_PCBM_INFO_LEN = 7 ;
+
+static const uint8_t P9N2_PU_CME9_CME_SCOM_XIPCBMI0_PCBM_INFO = 0 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_XIPCBMI0_PCBM_INFO_LEN = 7 ;
+
+static const uint8_t P9N2_PU_CME6_CME_SCOM_XIPCBMI0_PCBM_INFO = 0 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_XIPCBMI0_PCBM_INFO_LEN = 7 ;
+
+static const uint8_t P9N2_PU_CME10_CME_SCOM_XIPCBMI0_PCBM_INFO = 0 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_XIPCBMI0_PCBM_INFO_LEN = 7 ;
+
+static const uint8_t P9N2_PU_CME8_CME_SCOM_XIPCBMI0_PCBM_INFO = 0 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_XIPCBMI0_PCBM_INFO_LEN = 7 ;
+
+static const uint8_t P9N2_PU_CME1_CME_SCOM_XIPCBMI0_PCBM_INFO = 0 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_XIPCBMI0_PCBM_INFO_LEN = 7 ;
+
+static const uint8_t P9N2_PU_CME0_CME_SCOM_XIPCBMI0_PCBM_INFO = 0 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_XIPCBMI0_PCBM_INFO_LEN = 7 ;
+
+static const uint8_t P9N2_PU_CME7_CME_SCOM_XIPCBMI0_PCBM_INFO = 0 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_XIPCBMI0_PCBM_INFO_LEN = 7 ;
+
+static const uint8_t P9N2_PU_CME4_CME_SCOM_XIPCBMI1_PCBM_INFO = 0 ;
+static const uint8_t P9N2_PU_CME4_CME_SCOM_XIPCBMI1_PCBM_INFO_LEN = 7 ;
+
+static const uint8_t P9N2_PU_CME3_CME_SCOM_XIPCBMI1_PCBM_INFO = 0 ;
+static const uint8_t P9N2_PU_CME3_CME_SCOM_XIPCBMI1_PCBM_INFO_LEN = 7 ;
+
+static const uint8_t P9N2_PU_CME11_CME_SCOM_XIPCBMI1_PCBM_INFO = 0 ;
+static const uint8_t P9N2_PU_CME11_CME_SCOM_XIPCBMI1_PCBM_INFO_LEN = 7 ;
+
+static const uint8_t P9N2_PU_CME2_CME_SCOM_XIPCBMI1_PCBM_INFO = 0 ;
+static const uint8_t P9N2_PU_CME2_CME_SCOM_XIPCBMI1_PCBM_INFO_LEN = 7 ;
+
+static const uint8_t P9N2_PU_CME5_CME_SCOM_XIPCBMI1_PCBM_INFO = 0 ;
+static const uint8_t P9N2_PU_CME5_CME_SCOM_XIPCBMI1_PCBM_INFO_LEN = 7 ;
+
+static const uint8_t P9N2_PU_CME9_CME_SCOM_XIPCBMI1_PCBM_INFO = 0 ;
+static const uint8_t P9N2_PU_CME9_CME_SCOM_XIPCBMI1_PCBM_INFO_LEN = 7 ;
+
+static const uint8_t P9N2_PU_CME6_CME_SCOM_XIPCBMI1_PCBM_INFO = 0 ;
+static const uint8_t P9N2_PU_CME6_CME_SCOM_XIPCBMI1_PCBM_INFO_LEN = 7 ;
+
+static const uint8_t P9N2_PU_CME10_CME_SCOM_XIPCBMI1_PCBM_INFO = 0 ;
+static const uint8_t P9N2_PU_CME10_CME_SCOM_XIPCBMI1_PCBM_INFO_LEN = 7 ;
+
+static const uint8_t P9N2_PU_CME8_CME_SCOM_XIPCBMI1_PCBM_INFO = 0 ;
+static const uint8_t P9N2_PU_CME8_CME_SCOM_XIPCBMI1_PCBM_INFO_LEN = 7 ;
+
+static const uint8_t P9N2_PU_CME1_CME_SCOM_XIPCBMI1_PCBM_INFO = 0 ;
+static const uint8_t P9N2_PU_CME1_CME_SCOM_XIPCBMI1_PCBM_INFO_LEN = 7 ;
+
+static const uint8_t P9N2_PU_CME0_CME_SCOM_XIPCBMI1_PCBM_INFO = 0 ;
+static const uint8_t P9N2_PU_CME0_CME_SCOM_XIPCBMI1_PCBM_INFO_LEN = 7 ;
+
+static const uint8_t P9N2_PU_CME7_CME_SCOM_XIPCBMI1_PCBM_INFO = 0 ;
+static const uint8_t P9N2_PU_CME7_CME_SCOM_XIPCBMI1_PCBM_INFO_LEN = 7 ;
+
+static const uint8_t P9N2_PU_COMMAND_REGISTER_CMD_REG_BIT_WITHSTART = 0 ;
+static const uint8_t P9N2_PU_COMMAND_REGISTER_CMD_REG_BIT_WITHADDR = 1 ;
+static const uint8_t P9N2_PU_COMMAND_REGISTER_CMD_REG_BIT_READCONT = 2 ;
+static const uint8_t P9N2_PU_COMMAND_REGISTER_CMD_REG_BIT_WITHSTOP = 3 ;
+static const uint8_t P9N2_PU_COMMAND_REGISTER_CMD_REG_LENGTH = 4 ;
+static const uint8_t P9N2_PU_COMMAND_REGISTER_CMD_REG_LENGTH_LEN = 4 ;
+static const uint8_t P9N2_PU_COMMAND_REGISTER_UNUSED_8_14 = 8 ;
+static const uint8_t P9N2_PU_COMMAND_REGISTER_UNUSED_8_14_LEN = 7 ;
+static const uint8_t P9N2_PU_COMMAND_REGISTER_CMD_REG_BIT_RNW = 15 ;
+static const uint8_t P9N2_PU_COMMAND_REGISTER_UNUSED_16_22 = 16 ;
+static const uint8_t P9N2_PU_COMMAND_REGISTER_UNUSED_16_22_LEN = 7 ;
+static const uint8_t P9N2_PU_COMMAND_REGISTER_REG_ADDR_LENGTH = 23 ;
+static const uint8_t P9N2_PU_COMMAND_REGISTER_REG_ADDR_LENGTH_LEN = 3 ;
+static const uint8_t P9N2_PU_COMMAND_REGISTER_UNUSED_26_31 = 26 ;
+static const uint8_t P9N2_PU_COMMAND_REGISTER_UNUSED_26_31_LEN = 6 ;
+static const uint8_t P9N2_PU_COMMAND_REGISTER_CMD_REG_ADDR_1 = 32 ;
+static const uint8_t P9N2_PU_COMMAND_REGISTER_CMD_REG_ADDR_1_LEN = 8 ;
+static const uint8_t P9N2_PU_COMMAND_REGISTER_CMD_REG_ADDR_2 = 40 ;
+static const uint8_t P9N2_PU_COMMAND_REGISTER_CMD_REG_ADDR_2_LEN = 8 ;
+static const uint8_t P9N2_PU_COMMAND_REGISTER_CMD_REG_ADDR_3 = 48 ;
+static const uint8_t P9N2_PU_COMMAND_REGISTER_CMD_REG_ADDR_3_LEN = 8 ;
+static const uint8_t P9N2_PU_COMMAND_REGISTER_CMD_REG_ADDR_4 = 56 ;
+static const uint8_t P9N2_PU_COMMAND_REGISTER_CMD_REG_ADDR_4_LEN = 8 ;
+
+static const uint8_t P9N2_PU_COMMAND_REGISTER_B_WITH_START_0 = 0 ;
+static const uint8_t P9N2_PU_COMMAND_REGISTER_B_WITH_ADDRESS_0 = 1 ;
+static const uint8_t P9N2_PU_COMMAND_REGISTER_B_READ_CONTINUE_0 = 2 ;
+static const uint8_t P9N2_PU_COMMAND_REGISTER_B_WITH_STOP_0 = 3 ;
+static const uint8_t P9N2_PU_COMMAND_REGISTER_B_NOT_USED_0 = 4 ;
+static const uint8_t P9N2_PU_COMMAND_REGISTER_B_NOT_USED_0_LEN = 4 ;
+static const uint8_t P9N2_PU_COMMAND_REGISTER_B_DEVICE_ADDRESS_0 = 8 ;
+static const uint8_t P9N2_PU_COMMAND_REGISTER_B_DEVICE_ADDRESS_0_LEN = 7 ;
+static const uint8_t P9N2_PU_COMMAND_REGISTER_B_READ_NOT_WRITE_0 = 15 ;
+static const uint8_t P9N2_PU_COMMAND_REGISTER_B_LENGTH_IN_BYTES_0 = 16 ;
+static const uint8_t P9N2_PU_COMMAND_REGISTER_B_LENGTH_IN_BYTES_0_LEN = 16 ;
+static const uint8_t P9N2_PU_COMMAND_REGISTER_B_PEEK_DATA1_0 = 32 ;
+static const uint8_t P9N2_PU_COMMAND_REGISTER_B_PEEK_DATA1_0_LEN = 8 ;
+static const uint8_t P9N2_PU_COMMAND_REGISTER_B_LBUS_PARITY_ERR1_0 = 40 ;
+
+static const uint8_t P9N2_PU_COMMAND_REGISTER_C_WITH_START_1 = 0 ;
+static const uint8_t P9N2_PU_COMMAND_REGISTER_C_WITH_ADDRESS_1 = 1 ;
+static const uint8_t P9N2_PU_COMMAND_REGISTER_C_READ_CONTINUE_1 = 2 ;
+static const uint8_t P9N2_PU_COMMAND_REGISTER_C_WITH_STOP_1 = 3 ;
+static const uint8_t P9N2_PU_COMMAND_REGISTER_C_NOT_USED_1 = 4 ;
+static const uint8_t P9N2_PU_COMMAND_REGISTER_C_NOT_USED_1_LEN = 4 ;
+static const uint8_t P9N2_PU_COMMAND_REGISTER_C_DEVICE_ADDRESS_1 = 8 ;
+static const uint8_t P9N2_PU_COMMAND_REGISTER_C_DEVICE_ADDRESS_1_LEN = 7 ;
+static const uint8_t P9N2_PU_COMMAND_REGISTER_C_READ_NOT_WRITE_1 = 15 ;
+static const uint8_t P9N2_PU_COMMAND_REGISTER_C_LENGTH_IN_BYTES_1 = 16 ;
+static const uint8_t P9N2_PU_COMMAND_REGISTER_C_LENGTH_IN_BYTES_1_LEN = 16 ;
+static const uint8_t P9N2_PU_COMMAND_REGISTER_C_PEEK_DATA1_1 = 32 ;
+static const uint8_t P9N2_PU_COMMAND_REGISTER_C_PEEK_DATA1_1_LEN = 8 ;
+static const uint8_t P9N2_PU_COMMAND_REGISTER_C_LBUS_PARITY_ERR1_1 = 40 ;
+
+static const uint8_t P9N2_PU_COMMAND_REGISTER_D_WITH_START_2 = 0 ;
+static const uint8_t P9N2_PU_COMMAND_REGISTER_D_WITH_ADDRESS_2 = 1 ;
+static const uint8_t P9N2_PU_COMMAND_REGISTER_D_READ_CONTINUE_2 = 2 ;
+static const uint8_t P9N2_PU_COMMAND_REGISTER_D_WITH_STOP_2 = 3 ;
+static const uint8_t P9N2_PU_COMMAND_REGISTER_D_NOT_USED_2 = 4 ;
+static const uint8_t P9N2_PU_COMMAND_REGISTER_D_NOT_USED_2_LEN = 4 ;
+static const uint8_t P9N2_PU_COMMAND_REGISTER_D_DEVICE_ADDRESS_2 = 8 ;
+static const uint8_t P9N2_PU_COMMAND_REGISTER_D_DEVICE_ADDRESS_2_LEN = 7 ;
+static const uint8_t P9N2_PU_COMMAND_REGISTER_D_READ_NOT_WRITE_2 = 15 ;
+static const uint8_t P9N2_PU_COMMAND_REGISTER_D_LENGTH_IN_BYTES_2 = 16 ;
+static const uint8_t P9N2_PU_COMMAND_REGISTER_D_LENGTH_IN_BYTES_2_LEN = 16 ;
+static const uint8_t P9N2_PU_COMMAND_REGISTER_D_PEEK_DATA1_2 = 32 ;
+static const uint8_t P9N2_PU_COMMAND_REGISTER_D_PEEK_DATA1_2_LEN = 8 ;
+static const uint8_t P9N2_PU_COMMAND_REGISTER_D_LBUS_PARITY_ERR1_2 = 40 ;
+
+static const uint8_t P9N2_PU_COMMAND_REGISTER_E_WITH_START_3 = 0 ;
+static const uint8_t P9N2_PU_COMMAND_REGISTER_E_WITH_ADDRESS_3 = 1 ;
+static const uint8_t P9N2_PU_COMMAND_REGISTER_E_READ_CONTINUE_3 = 2 ;
+static const uint8_t P9N2_PU_COMMAND_REGISTER_E_WITH_STOP_3 = 3 ;
+static const uint8_t P9N2_PU_COMMAND_REGISTER_E_NOT_USED_3 = 4 ;
+static const uint8_t P9N2_PU_COMMAND_REGISTER_E_NOT_USED_3_LEN = 4 ;
+static const uint8_t P9N2_PU_COMMAND_REGISTER_E_DEVICE_ADDRESS_3 = 8 ;
+static const uint8_t P9N2_PU_COMMAND_REGISTER_E_DEVICE_ADDRESS_3_LEN = 7 ;
+static const uint8_t P9N2_PU_COMMAND_REGISTER_E_READ_NOT_WRITE_3 = 15 ;
+static const uint8_t P9N2_PU_COMMAND_REGISTER_E_LENGTH_IN_BYTES_3 = 16 ;
+static const uint8_t P9N2_PU_COMMAND_REGISTER_E_LENGTH_IN_BYTES_3_LEN = 16 ;
+static const uint8_t P9N2_PU_COMMAND_REGISTER_E_PEEK_DATA1_3 = 32 ;
+static const uint8_t P9N2_PU_COMMAND_REGISTER_E_PEEK_DATA1_3_LEN = 8 ;
+static const uint8_t P9N2_PU_COMMAND_REGISTER_E_LBUS_PARITY_ERR1_3 = 40 ;
+
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG0_CONFIG_OTL_EN = 0 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG0_CONFIG_OTL_BLOCK_PE_HANDLE = 1 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG0_CONFIG_OTL_BRICKID = 2 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG0_CONFIG_OTL_BRICKID_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG0_CONFIG_OTL_PE_MASK = 4 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG0_CONFIG_OTL_PE_MASK_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG0_CONFIG_OTL_ERAT_HASH_0 = 8 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG0_CONFIG_OTL_ERAT_HASH_0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG0_CONFIG_OTL_ERAT_HASH_1 = 14 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG0_CONFIG_OTL_ERAT_HASH_1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG0_CONFIG_OTL_ERAT_HASH_2 = 20 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG0_CONFIG_OTL_ERAT_HASH_2_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG0_CONFIG_OTL_ERAT_HASH_3 = 26 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG0_CONFIG_OTL_ERAT_HASH_3_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG0_CONFIG_OTL_CFIFO0_LO_ENABLE1 = 32 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG0_CONFIG_OTL_CFIFO0_LO_ENABLE2 = 33 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG0_CONFIG_OTL_CFIFO0_HI_ENABLE1 = 34 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG0_CONFIG_OTL_CFIFO0_HI_ENABLE2 = 35 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG0_CONFIG_OTL_CFIFO1_ENABLE1 = 36 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG0_CONFIG_OTL_CFIFO1_ENABLE2 = 37 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG0_CONFIG_OTL_RFIFO_ENABLE1 = 38 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG0_CONFIG_OTL_RFIFO_ENABLE2 = 39 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG0_CONFIG_OTL_ACTAG_ENABLE1 = 40 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG0_CONFIG_OTL_ACTAG_ENABLE2 = 41 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG0_CONFIG_OTL_CDFIFO_LO_ENABLE1 = 42 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG0_CONFIG_OTL_CDFIFO_LO_ENABLE2 = 43 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG0_CONFIG_OTL_CDFIFO_HI_ENABLE1 = 44 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG0_CONFIG_OTL_CDFIFO_HI_ENABLE2 = 45 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG0_CONFIG_OTL_RDFIFO_LO_ENABLE1 = 46 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG0_CONFIG_OTL_RDFIFO_LO_ENABLE2 = 47 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG0_CONFIG_OTL_RDFIFO_HI_ENABLE1 = 48 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG0_CONFIG_OTL_RDFIFO_HI_ENABLE2 = 49 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG0_CONFIG_OTL_BLOCK_TID_OVERRIDE = 50 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG0_CONFIG_OTL_SPARE = 51 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG0_CONFIG_OTL_SPARE_LEN = 13 ;
+
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_RESERVED1 = 0 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_MA_DSA_OPT_CLAIM_UR = 1 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_MA_DSA_OPT_FLUSH_UR = 2 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_MA_DSA_OPT_RP_MODE = 3 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_ADR_BAR_MODE = 4 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_DISABLE_NN_RN = 5 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_DISABLE_VG_NOT_SYS = 6 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_DISABLE_G = 7 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_DISABLE_LN = 8 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_SKIP_G = 9 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_MA_MCRESP_OPT_WRP = 10 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_INJ = 11 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_DMA = 12 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_INC_PRI_MASK = 13 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_INC_PRI_MASK_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_RESERVED2 = 16 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_MA_RSNOOP_OPT_B = 17 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_MA_RSNOOP_OPT_C = 18 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_MA_SCRESP_OPT_A = 19 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_MA_SCRESP_OPT_B = 20 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_MA_SCRESP_OPT_C = 21 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_RESERVED4 = 22 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_MACH_CORRENAB = 23 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_MACH_INJECT_ENABLE1 = 24 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_MACH_INJECT_ENABLE2 = 25 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_RXO_CORRENAB = 26 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_RXO_INJECT_ENABLE1 = 27 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_RXO_INJECT_ENABLE2 = 28 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_RSI_CORRENAB = 29 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_RSI_INJECT_ENABLE1 = 30 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_RSI_INJECT_ENABLE2 = 31 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM = 32 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_MA_DSA_OPT_DMA_UPG = 34 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_EVAPORATE_BY_LCO = 35 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_MRBGP_TRACK_ALL = 36 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_MRBSP_TRACK_ALL = 37 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_ENABLE_PBUS = 38 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_BRAZOS_MODE = 39 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_ENABLE_SNARF_CPM = 40 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_PREALLOC2_REQ0 = 41 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_PREALLOC2_PRB0 = 42 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_PREALLOC2_REQ1 = 43 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_PREALLOC2_PRB1 = 44 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_PREALLOC2_XATS = 45 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_DISABLE_INJECT = 46 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_DCACHE_MODE = 47 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_DCACHE_REPORTS_PHYSICAL = 48 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_RSI_DISABLE_DATIN_FASTPATH = 49 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_PCKT_BLK_PRB = 50 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_P9P9_MODE = 51 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_FORBID_MMIO_READ_GT_32 = 52 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_FORBID_MMIO_ATOMIC = 53 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_OPT_SNOOP_CP = 54 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_MRBCP_TRACK_ALL = 55 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_RESTRICT_CHIP_GROUP = 56 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_OCAPI_MODE = 57 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_NVLINK_MODE = 58 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_PREALLOC2_INTS = 59 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_PREALLOC2_PWR0 = 60 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_PREALLOC2_PWR1 = 61 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_ENABLE_CONTEXT_LCO = 62 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG0_CONFIG_MA_DSA_OPT_FAIL_WAKE = 63 ;
+
+static const uint8_t P9N2__SM2_CONFIG0_CONFIG_OTL_EN = 0 ;
+static const uint8_t P9N2__SM2_CONFIG0_CONFIG_OTL_BLOCK_PE_HANDLE = 1 ;
+static const uint8_t P9N2__SM2_CONFIG0_CONFIG_OTL_BRICKID = 2 ;
+static const uint8_t P9N2__SM2_CONFIG0_CONFIG_OTL_BRICKID_LEN = 2 ;
+static const uint8_t P9N2__SM2_CONFIG0_CONFIG_OTL_PE_MASK = 4 ;
+static const uint8_t P9N2__SM2_CONFIG0_CONFIG_OTL_PE_MASK_LEN = 4 ;
+static const uint8_t P9N2__SM2_CONFIG0_CONFIG_OTL_ERAT_HASH_0 = 8 ;
+static const uint8_t P9N2__SM2_CONFIG0_CONFIG_OTL_ERAT_HASH_0_LEN = 6 ;
+static const uint8_t P9N2__SM2_CONFIG0_CONFIG_OTL_ERAT_HASH_1 = 14 ;
+static const uint8_t P9N2__SM2_CONFIG0_CONFIG_OTL_ERAT_HASH_1_LEN = 6 ;
+static const uint8_t P9N2__SM2_CONFIG0_CONFIG_OTL_ERAT_HASH_2 = 20 ;
+static const uint8_t P9N2__SM2_CONFIG0_CONFIG_OTL_ERAT_HASH_2_LEN = 6 ;
+static const uint8_t P9N2__SM2_CONFIG0_CONFIG_OTL_ERAT_HASH_3 = 26 ;
+static const uint8_t P9N2__SM2_CONFIG0_CONFIG_OTL_ERAT_HASH_3_LEN = 6 ;
+static const uint8_t P9N2__SM2_CONFIG0_CONFIG_OTL_CFIFO0_LO_ENABLE1 = 32 ;
+static const uint8_t P9N2__SM2_CONFIG0_CONFIG_OTL_CFIFO0_LO_ENABLE2 = 33 ;
+static const uint8_t P9N2__SM2_CONFIG0_CONFIG_OTL_CFIFO0_HI_ENABLE1 = 34 ;
+static const uint8_t P9N2__SM2_CONFIG0_CONFIG_OTL_CFIFO0_HI_ENABLE2 = 35 ;
+static const uint8_t P9N2__SM2_CONFIG0_CONFIG_OTL_CFIFO1_ENABLE1 = 36 ;
+static const uint8_t P9N2__SM2_CONFIG0_CONFIG_OTL_CFIFO1_ENABLE2 = 37 ;
+static const uint8_t P9N2__SM2_CONFIG0_CONFIG_OTL_RFIFO_ENABLE1 = 38 ;
+static const uint8_t P9N2__SM2_CONFIG0_CONFIG_OTL_RFIFO_ENABLE2 = 39 ;
+static const uint8_t P9N2__SM2_CONFIG0_CONFIG_OTL_ACTAG_ENABLE1 = 40 ;
+static const uint8_t P9N2__SM2_CONFIG0_CONFIG_OTL_ACTAG_ENABLE2 = 41 ;
+static const uint8_t P9N2__SM2_CONFIG0_CONFIG_OTL_CDFIFO_LO_ENABLE1 = 42 ;
+static const uint8_t P9N2__SM2_CONFIG0_CONFIG_OTL_CDFIFO_LO_ENABLE2 = 43 ;
+static const uint8_t P9N2__SM2_CONFIG0_CONFIG_OTL_CDFIFO_HI_ENABLE1 = 44 ;
+static const uint8_t P9N2__SM2_CONFIG0_CONFIG_OTL_CDFIFO_HI_ENABLE2 = 45 ;
+static const uint8_t P9N2__SM2_CONFIG0_CONFIG_OTL_RDFIFO_LO_ENABLE1 = 46 ;
+static const uint8_t P9N2__SM2_CONFIG0_CONFIG_OTL_RDFIFO_LO_ENABLE2 = 47 ;
+static const uint8_t P9N2__SM2_CONFIG0_CONFIG_OTL_RDFIFO_HI_ENABLE1 = 48 ;
+static const uint8_t P9N2__SM2_CONFIG0_CONFIG_OTL_RDFIFO_HI_ENABLE2 = 49 ;
+static const uint8_t P9N2__SM2_CONFIG0_CONFIG_OTL_BLOCK_TID_OVERRIDE = 50 ;
+static const uint8_t P9N2__SM2_CONFIG0_CONFIG_OTL_SPARE = 51 ;
+static const uint8_t P9N2__SM2_CONFIG0_CONFIG_OTL_SPARE_LEN = 13 ;
+
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_RESERVED1 = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_MA_DSA_OPT_CLAIM_UR = 1 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_MA_DSA_OPT_FLUSH_UR = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_MA_DSA_OPT_RP_MODE = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_ADR_BAR_MODE = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_DISABLE_NN_RN = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_DISABLE_VG_NOT_SYS = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_DISABLE_G = 7 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_DISABLE_LN = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_SKIP_G = 9 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_MA_MCRESP_OPT_WRP = 10 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_INJ = 11 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_DMA = 12 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_INC_PRI_MASK = 13 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_INC_PRI_MASK_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_RESERVED2 = 16 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_MA_RSNOOP_OPT_B = 17 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_MA_RSNOOP_OPT_C = 18 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_MA_SCRESP_OPT_A = 19 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_MA_SCRESP_OPT_B = 20 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_MA_SCRESP_OPT_C = 21 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_RESERVED4 = 22 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_MACH_CORRENAB = 23 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_MACH_INJECT_ENABLE1 = 24 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_MACH_INJECT_ENABLE2 = 25 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_RXO_CORRENAB = 26 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_RXO_INJECT_ENABLE1 = 27 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_RXO_INJECT_ENABLE2 = 28 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_RSI_CORRENAB = 29 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_RSI_INJECT_ENABLE1 = 30 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_RSI_INJECT_ENABLE2 = 31 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM = 32 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_MA_DSA_OPT_DMA_UPG = 34 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_EVAPORATE_BY_LCO = 35 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_MRBGP_TRACK_ALL = 36 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_MRBSP_TRACK_ALL = 37 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_ENABLE_PBUS = 38 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_BRAZOS_MODE = 39 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_ENABLE_SNARF_CPM = 40 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_PREALLOC2_REQ0 = 41 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_PREALLOC2_PRB0 = 42 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_PREALLOC2_REQ1 = 43 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_PREALLOC2_PRB1 = 44 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_PREALLOC2_XATS = 45 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_DISABLE_INJECT = 46 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_DCACHE_MODE = 47 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_DCACHE_REPORTS_PHYSICAL = 48 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_RSI_DISABLE_DATIN_FASTPATH = 49 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_PCKT_BLK_PRB = 50 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_P9P9_MODE = 51 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_FORBID_MMIO_READ_GT_32 = 52 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_FORBID_MMIO_ATOMIC = 53 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_OPT_SNOOP_CP = 54 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_MRBCP_TRACK_ALL = 55 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_RESTRICT_CHIP_GROUP = 56 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_OCAPI_MODE = 57 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_NVLINK_MODE = 58 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_PREALLOC2_INTS = 59 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_PREALLOC2_PWR0 = 60 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_PREALLOC2_PWR1 = 61 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_ENABLE_CONTEXT_LCO = 62 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG0_CONFIG_MA_DSA_OPT_FAIL_WAKE = 63 ;
+
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_RESERVED1 = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_MA_DSA_OPT_CLAIM_UR = 1 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_MA_DSA_OPT_FLUSH_UR = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_MA_DSA_OPT_RP_MODE = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_ADR_BAR_MODE = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_DISABLE_NN_RN = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_DISABLE_VG_NOT_SYS = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_DISABLE_G = 7 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_DISABLE_LN = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_SKIP_G = 9 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_MA_MCRESP_OPT_WRP = 10 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_INJ = 11 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_DMA = 12 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_INC_PRI_MASK = 13 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_INC_PRI_MASK_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_RESERVED2 = 16 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_MA_RSNOOP_OPT_B = 17 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_MA_RSNOOP_OPT_C = 18 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_MA_SCRESP_OPT_A = 19 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_MA_SCRESP_OPT_B = 20 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_MA_SCRESP_OPT_C = 21 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_RESERVED4 = 22 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_MACH_CORRENAB = 23 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_MACH_INJECT_ENABLE1 = 24 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_MACH_INJECT_ENABLE2 = 25 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_RXO_CORRENAB = 26 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_RXO_INJECT_ENABLE1 = 27 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_RXO_INJECT_ENABLE2 = 28 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_RSI_CORRENAB = 29 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_RSI_INJECT_ENABLE1 = 30 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_RSI_INJECT_ENABLE2 = 31 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM = 32 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_MA_DSA_OPT_DMA_UPG = 34 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_EVAPORATE_BY_LCO = 35 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_MRBGP_TRACK_ALL = 36 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_MRBSP_TRACK_ALL = 37 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_ENABLE_PBUS = 38 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_BRAZOS_MODE = 39 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_ENABLE_SNARF_CPM = 40 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_PREALLOC2_REQ0 = 41 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_PREALLOC2_PRB0 = 42 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_PREALLOC2_REQ1 = 43 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_PREALLOC2_PRB1 = 44 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_PREALLOC2_XATS = 45 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_DISABLE_INJECT = 46 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_DCACHE_MODE = 47 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_DCACHE_REPORTS_PHYSICAL = 48 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_RSI_DISABLE_DATIN_FASTPATH = 49 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_PCKT_BLK_PRB = 50 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_P9P9_MODE = 51 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_FORBID_MMIO_READ_GT_32 = 52 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_FORBID_MMIO_ATOMIC = 53 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_OPT_SNOOP_CP = 54 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_MRBCP_TRACK_ALL = 55 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_RESTRICT_CHIP_GROUP = 56 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_OCAPI_MODE = 57 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_NVLINK_MODE = 58 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_PREALLOC2_INTS = 59 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_PREALLOC2_PWR0 = 60 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_PREALLOC2_PWR1 = 61 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_ENABLE_CONTEXT_LCO = 62 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG0_CONFIG_MA_DSA_OPT_FAIL_WAKE = 63 ;
+
+static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG0_RESERVED0 = 0 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG0_RESERVED1 = 1 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG0_RESERVED1_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG0_CONFIG_ADR_BAR_MODE = 4 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG0_CONFIG_GEN_HEAD_DELAY = 5 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG0_CONFIG_GEN_HEAD_DELAY_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG0_CONFIG_MRBGP_DIV2_COUNT_AT_EXP = 10 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG0_CONFIG_MRBSP_DIV2_COUNT_AT_EXP = 11 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG0_CONFIG_MRBGP_DIS_DYN_ADJ = 12 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG0_CONFIG_MRBSP_DIS_DYN_ADJ = 13 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG0_CONFIG_MRBGP_DIS_DYN_LVL_ADJ = 14 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG0_CONFIG_MRBSP_DIS_DYN_LVL_ADJ = 15 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG0_CONFIG_MRBGP_THRESH1 = 16 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG0_CONFIG_MRBGP_THRESH1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG0_CONFIG_MRBGP_THRESH2 = 22 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG0_CONFIG_MRBGP_THRESH2_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG0_CONFIG_MRBSP_THRESH1 = 28 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG0_CONFIG_MRBSP_THRESH1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG0_CONFIG_MRBSP_THRESH2 = 34 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG0_CONFIG_MRBSP_THRESH2_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG0_CONFIG_MRBGP_MAX_LEVEL = 40 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG0_CONFIG_MRBGP_MAX_LEVEL_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG0_CONFIG_MRBSP_MAX_LEVEL = 44 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG0_CONFIG_MRBSP_MAX_LEVEL_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG0_CONFIG_BRAZOS_MODE = 48 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG0_CONFIG_DISABLE_PBM_ECC_COR = 49 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG0_CONFIG_LAB_RANDOMIZE_PE_01 = 50 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG0_CONFIG_LAB_RANDOMIZE_PE_23 = 51 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG0_CONFIG_OCAPI_MODE = 52 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG0_CONFIG_NVLINK_MODE = 53 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG0_CONFIG_RANDOMIZE_INT_SLICE = 54 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG0_CONFIG_OTL0_ENABLE = 55 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG0_CONFIG_OTL1_ENABLE = 56 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG0_CONFIG_DISABLE_2CREDS_TO_OTL = 57 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG0_CONFIG_RESTRICT_RSPIN_CREDIT_TO1 = 58 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG0_RESERVED2 = 59 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG0_RESERVED2_LEN = 5 ;
+
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_RESERVED1 = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_MA_DSA_OPT_CLAIM_UR = 1 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_MA_DSA_OPT_FLUSH_UR = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_MA_DSA_OPT_RP_MODE = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_ADR_BAR_MODE = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_DISABLE_NN_RN = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_DISABLE_VG_NOT_SYS = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_DISABLE_G = 7 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_DISABLE_LN = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_SKIP_G = 9 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_MA_MCRESP_OPT_WRP = 10 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_INJ = 11 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_DMA = 12 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_INC_PRI_MASK = 13 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_INC_PRI_MASK_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_RESERVED2 = 16 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_MA_RSNOOP_OPT_B = 17 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_MA_RSNOOP_OPT_C = 18 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_MA_SCRESP_OPT_A = 19 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_MA_SCRESP_OPT_B = 20 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_MA_SCRESP_OPT_C = 21 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_RESERVED4 = 22 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_MACH_CORRENAB = 23 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_MACH_INJECT_ENABLE1 = 24 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_MACH_INJECT_ENABLE2 = 25 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_RXO_CORRENAB = 26 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_RXO_INJECT_ENABLE1 = 27 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_RXO_INJECT_ENABLE2 = 28 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_RSI_CORRENAB = 29 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_RSI_INJECT_ENABLE1 = 30 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_RSI_INJECT_ENABLE2 = 31 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM = 32 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_MA_DSA_OPT_DMA_UPG = 34 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_EVAPORATE_BY_LCO = 35 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_MRBGP_TRACK_ALL = 36 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_MRBSP_TRACK_ALL = 37 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_ENABLE_PBUS = 38 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_BRAZOS_MODE = 39 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_ENABLE_SNARF_CPM = 40 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_PREALLOC2_REQ0 = 41 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_PREALLOC2_PRB0 = 42 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_PREALLOC2_REQ1 = 43 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_PREALLOC2_PRB1 = 44 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_PREALLOC2_XATS = 45 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_DISABLE_INJECT = 46 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_DCACHE_MODE = 47 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_DCACHE_REPORTS_PHYSICAL = 48 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_RSI_DISABLE_DATIN_FASTPATH = 49 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_PCKT_BLK_PRB = 50 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_P9P9_MODE = 51 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_FORBID_MMIO_READ_GT_32 = 52 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_FORBID_MMIO_ATOMIC = 53 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_OPT_SNOOP_CP = 54 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_MRBCP_TRACK_ALL = 55 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_RESTRICT_CHIP_GROUP = 56 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_OCAPI_MODE = 57 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_NVLINK_MODE = 58 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_PREALLOC2_INTS = 59 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_PREALLOC2_PWR0 = 60 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_PREALLOC2_PWR1 = 61 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_ENABLE_CONTEXT_LCO = 62 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG0_CONFIG_MA_DSA_OPT_FAIL_WAKE = 63 ;
+
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_RESERVED1 = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_MA_DSA_OPT_CLAIM_UR = 1 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_MA_DSA_OPT_FLUSH_UR = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_MA_DSA_OPT_RP_MODE = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_ADR_BAR_MODE = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_DISABLE_NN_RN = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_DISABLE_VG_NOT_SYS = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_DISABLE_G = 7 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_DISABLE_LN = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_SKIP_G = 9 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_MA_MCRESP_OPT_WRP = 10 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_INJ = 11 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_DMA = 12 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_INC_PRI_MASK = 13 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_INC_PRI_MASK_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_RESERVED2 = 16 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_MA_RSNOOP_OPT_B = 17 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_MA_RSNOOP_OPT_C = 18 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_MA_SCRESP_OPT_A = 19 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_MA_SCRESP_OPT_B = 20 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_MA_SCRESP_OPT_C = 21 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_RESERVED4 = 22 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_MACH_CORRENAB = 23 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_MACH_INJECT_ENABLE1 = 24 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_MACH_INJECT_ENABLE2 = 25 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_RXO_CORRENAB = 26 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_RXO_INJECT_ENABLE1 = 27 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_RXO_INJECT_ENABLE2 = 28 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_RSI_CORRENAB = 29 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_RSI_INJECT_ENABLE1 = 30 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_RSI_INJECT_ENABLE2 = 31 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM = 32 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_MA_DSA_OPT_DMA_UPG = 34 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_EVAPORATE_BY_LCO = 35 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_MRBGP_TRACK_ALL = 36 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_MRBSP_TRACK_ALL = 37 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_ENABLE_PBUS = 38 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_BRAZOS_MODE = 39 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_ENABLE_SNARF_CPM = 40 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_PREALLOC2_REQ0 = 41 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_PREALLOC2_PRB0 = 42 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_PREALLOC2_REQ1 = 43 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_PREALLOC2_PRB1 = 44 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_PREALLOC2_XATS = 45 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_DISABLE_INJECT = 46 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_DCACHE_MODE = 47 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_DCACHE_REPORTS_PHYSICAL = 48 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_RSI_DISABLE_DATIN_FASTPATH = 49 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_PCKT_BLK_PRB = 50 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_P9P9_MODE = 51 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_FORBID_MMIO_READ_GT_32 = 52 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_FORBID_MMIO_ATOMIC = 53 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_OPT_SNOOP_CP = 54 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_MRBCP_TRACK_ALL = 55 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_RESTRICT_CHIP_GROUP = 56 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_OCAPI_MODE = 57 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_NVLINK_MODE = 58 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_PREALLOC2_INTS = 59 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_PREALLOC2_PWR0 = 60 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_PREALLOC2_PWR1 = 61 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_ENABLE_CONTEXT_LCO = 62 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG0_CONFIG_MA_DSA_OPT_FAIL_WAKE = 63 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_RESERVED1 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_MA_DSA_OPT_CLAIM_UR = 1 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_MA_DSA_OPT_FLUSH_UR = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_MA_DSA_OPT_RP_MODE = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_ADR_BAR_MODE = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_DISABLE_NN_RN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_DISABLE_VG_NOT_SYS = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_DISABLE_G = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_DISABLE_LN = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_SKIP_G = 9 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_MA_MCRESP_OPT_WRP = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_INJ = 11 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_DMA = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_INC_PRI_MASK = 13 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_INC_PRI_MASK_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_RESERVED2 = 16 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_MA_RSNOOP_OPT_B = 17 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_MA_RSNOOP_OPT_C = 18 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_MA_SCRESP_OPT_A = 19 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_MA_SCRESP_OPT_B = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_MA_SCRESP_OPT_C = 21 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_RESERVED4 = 22 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_MACH_CORRENAB = 23 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_MACH_INJECT_ENABLE1 = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_MACH_INJECT_ENABLE2 = 25 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_RXO_CORRENAB = 26 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_RXO_INJECT_ENABLE1 = 27 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_RXO_INJECT_ENABLE2 = 28 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_RSI_CORRENAB = 29 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_RSI_INJECT_ENABLE1 = 30 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_RSI_INJECT_ENABLE2 = 31 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_MA_DSA_OPT_DMA_UPG = 34 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_EVAPORATE_BY_LCO = 35 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_MRBGP_TRACK_ALL = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_MRBSP_TRACK_ALL = 37 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_ENABLE_PBUS = 38 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_BRAZOS_MODE = 39 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_ENABLE_SNARF_CPM = 40 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_PREALLOC2_REQ0 = 41 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_PREALLOC2_PRB0 = 42 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_PREALLOC2_REQ1 = 43 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_PREALLOC2_PRB1 = 44 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_PREALLOC2_XATS = 45 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_DISABLE_INJECT = 46 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_DCACHE_MODE = 47 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_DCACHE_REPORTS_PHYSICAL = 48 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_RSI_DISABLE_DATIN_FASTPATH = 49 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_PCKT_BLK_PRB = 50 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_P9P9_MODE = 51 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_FORBID_MMIO_READ_GT_32 = 52 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_FORBID_MMIO_ATOMIC = 53 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_OPT_SNOOP_CP = 54 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_MRBCP_TRACK_ALL = 55 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_RESTRICT_CHIP_GROUP = 56 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_OCAPI_MODE = 57 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_NVLINK_MODE = 58 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_PREALLOC2_INTS = 59 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_PREALLOC2_PWR0 = 60 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_PREALLOC2_PWR1 = 61 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_ENABLE_CONTEXT_LCO = 62 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG0_CONFIG_MA_DSA_OPT_FAIL_WAKE = 63 ;
+
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG0_CONFIG_OTL_EN = 0 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG0_CONFIG_OTL_BLOCK_PE_HANDLE = 1 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG0_CONFIG_OTL_BRICKID = 2 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG0_CONFIG_OTL_BRICKID_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG0_CONFIG_OTL_PE_MASK = 4 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG0_CONFIG_OTL_PE_MASK_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG0_CONFIG_OTL_ERAT_HASH_0 = 8 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG0_CONFIG_OTL_ERAT_HASH_0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG0_CONFIG_OTL_ERAT_HASH_1 = 14 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG0_CONFIG_OTL_ERAT_HASH_1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG0_CONFIG_OTL_ERAT_HASH_2 = 20 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG0_CONFIG_OTL_ERAT_HASH_2_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG0_CONFIG_OTL_ERAT_HASH_3 = 26 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG0_CONFIG_OTL_ERAT_HASH_3_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG0_CONFIG_OTL_CFIFO0_LO_ENABLE1 = 32 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG0_CONFIG_OTL_CFIFO0_LO_ENABLE2 = 33 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG0_CONFIG_OTL_CFIFO0_HI_ENABLE1 = 34 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG0_CONFIG_OTL_CFIFO0_HI_ENABLE2 = 35 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG0_CONFIG_OTL_CFIFO1_ENABLE1 = 36 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG0_CONFIG_OTL_CFIFO1_ENABLE2 = 37 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG0_CONFIG_OTL_RFIFO_ENABLE1 = 38 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG0_CONFIG_OTL_RFIFO_ENABLE2 = 39 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG0_CONFIG_OTL_ACTAG_ENABLE1 = 40 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG0_CONFIG_OTL_ACTAG_ENABLE2 = 41 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG0_CONFIG_OTL_CDFIFO_LO_ENABLE1 = 42 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG0_CONFIG_OTL_CDFIFO_LO_ENABLE2 = 43 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG0_CONFIG_OTL_CDFIFO_HI_ENABLE1 = 44 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG0_CONFIG_OTL_CDFIFO_HI_ENABLE2 = 45 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG0_CONFIG_OTL_RDFIFO_LO_ENABLE1 = 46 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG0_CONFIG_OTL_RDFIFO_LO_ENABLE2 = 47 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG0_CONFIG_OTL_RDFIFO_HI_ENABLE1 = 48 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG0_CONFIG_OTL_RDFIFO_HI_ENABLE2 = 49 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG0_CONFIG_OTL_BLOCK_TID_OVERRIDE = 50 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG0_CONFIG_OTL_SPARE = 51 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG0_CONFIG_OTL_SPARE_LEN = 13 ;
+
+static const uint8_t P9N2__CTL_CONFIG0_CONFIG_OTL_EN = 0 ;
+static const uint8_t P9N2__CTL_CONFIG0_CONFIG_OTL_BLOCK_PE_HANDLE = 1 ;
+static const uint8_t P9N2__CTL_CONFIG0_CONFIG_OTL_BRICKID = 2 ;
+static const uint8_t P9N2__CTL_CONFIG0_CONFIG_OTL_BRICKID_LEN = 2 ;
+static const uint8_t P9N2__CTL_CONFIG0_CONFIG_OTL_PE_MASK = 4 ;
+static const uint8_t P9N2__CTL_CONFIG0_CONFIG_OTL_PE_MASK_LEN = 4 ;
+static const uint8_t P9N2__CTL_CONFIG0_CONFIG_OTL_ERAT_HASH_0 = 8 ;
+static const uint8_t P9N2__CTL_CONFIG0_CONFIG_OTL_ERAT_HASH_0_LEN = 6 ;
+static const uint8_t P9N2__CTL_CONFIG0_CONFIG_OTL_ERAT_HASH_1 = 14 ;
+static const uint8_t P9N2__CTL_CONFIG0_CONFIG_OTL_ERAT_HASH_1_LEN = 6 ;
+static const uint8_t P9N2__CTL_CONFIG0_CONFIG_OTL_ERAT_HASH_2 = 20 ;
+static const uint8_t P9N2__CTL_CONFIG0_CONFIG_OTL_ERAT_HASH_2_LEN = 6 ;
+static const uint8_t P9N2__CTL_CONFIG0_CONFIG_OTL_ERAT_HASH_3 = 26 ;
+static const uint8_t P9N2__CTL_CONFIG0_CONFIG_OTL_ERAT_HASH_3_LEN = 6 ;
+static const uint8_t P9N2__CTL_CONFIG0_CONFIG_OTL_CFIFO0_LO_ENABLE1 = 32 ;
+static const uint8_t P9N2__CTL_CONFIG0_CONFIG_OTL_CFIFO0_LO_ENABLE2 = 33 ;
+static const uint8_t P9N2__CTL_CONFIG0_CONFIG_OTL_CFIFO0_HI_ENABLE1 = 34 ;
+static const uint8_t P9N2__CTL_CONFIG0_CONFIG_OTL_CFIFO0_HI_ENABLE2 = 35 ;
+static const uint8_t P9N2__CTL_CONFIG0_CONFIG_OTL_CFIFO1_ENABLE1 = 36 ;
+static const uint8_t P9N2__CTL_CONFIG0_CONFIG_OTL_CFIFO1_ENABLE2 = 37 ;
+static const uint8_t P9N2__CTL_CONFIG0_CONFIG_OTL_RFIFO_ENABLE1 = 38 ;
+static const uint8_t P9N2__CTL_CONFIG0_CONFIG_OTL_RFIFO_ENABLE2 = 39 ;
+static const uint8_t P9N2__CTL_CONFIG0_CONFIG_OTL_ACTAG_ENABLE1 = 40 ;
+static const uint8_t P9N2__CTL_CONFIG0_CONFIG_OTL_ACTAG_ENABLE2 = 41 ;
+static const uint8_t P9N2__CTL_CONFIG0_CONFIG_OTL_CDFIFO_LO_ENABLE1 = 42 ;
+static const uint8_t P9N2__CTL_CONFIG0_CONFIG_OTL_CDFIFO_LO_ENABLE2 = 43 ;
+static const uint8_t P9N2__CTL_CONFIG0_CONFIG_OTL_CDFIFO_HI_ENABLE1 = 44 ;
+static const uint8_t P9N2__CTL_CONFIG0_CONFIG_OTL_CDFIFO_HI_ENABLE2 = 45 ;
+static const uint8_t P9N2__CTL_CONFIG0_CONFIG_OTL_RDFIFO_LO_ENABLE1 = 46 ;
+static const uint8_t P9N2__CTL_CONFIG0_CONFIG_OTL_RDFIFO_LO_ENABLE2 = 47 ;
+static const uint8_t P9N2__CTL_CONFIG0_CONFIG_OTL_RDFIFO_HI_ENABLE1 = 48 ;
+static const uint8_t P9N2__CTL_CONFIG0_CONFIG_OTL_RDFIFO_HI_ENABLE2 = 49 ;
+static const uint8_t P9N2__CTL_CONFIG0_CONFIG_OTL_BLOCK_TID_OVERRIDE = 50 ;
+static const uint8_t P9N2__CTL_CONFIG0_CONFIG_OTL_SPARE = 51 ;
+static const uint8_t P9N2__CTL_CONFIG0_CONFIG_OTL_SPARE_LEN = 13 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_RESERVED1 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_MA_DSA_OPT_CLAIM_UR = 1 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_MA_DSA_OPT_FLUSH_UR = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_MA_DSA_OPT_RP_MODE = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_ADR_BAR_MODE = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_DISABLE_NN_RN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_DISABLE_VG_NOT_SYS = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_DISABLE_G = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_DISABLE_LN = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_SKIP_G = 9 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_MA_MCRESP_OPT_WRP = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_INJ = 11 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_DMA = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_INC_PRI_MASK = 13 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_INC_PRI_MASK_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_RESERVED2 = 16 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_MA_RSNOOP_OPT_B = 17 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_MA_RSNOOP_OPT_C = 18 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_MA_SCRESP_OPT_A = 19 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_MA_SCRESP_OPT_B = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_MA_SCRESP_OPT_C = 21 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_RESERVED4 = 22 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_MACH_CORRENAB = 23 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_MACH_INJECT_ENABLE1 = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_MACH_INJECT_ENABLE2 = 25 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_RXO_CORRENAB = 26 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_RXO_INJECT_ENABLE1 = 27 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_RXO_INJECT_ENABLE2 = 28 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_RSI_CORRENAB = 29 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_RSI_INJECT_ENABLE1 = 30 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_RSI_INJECT_ENABLE2 = 31 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_MA_DSA_OPT_DMA_UPG = 34 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_EVAPORATE_BY_LCO = 35 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_MRBGP_TRACK_ALL = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_MRBSP_TRACK_ALL = 37 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_ENABLE_PBUS = 38 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_BRAZOS_MODE = 39 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_ENABLE_SNARF_CPM = 40 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_PREALLOC2_REQ0 = 41 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_PREALLOC2_PRB0 = 42 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_PREALLOC2_REQ1 = 43 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_PREALLOC2_PRB1 = 44 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_PREALLOC2_XATS = 45 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_DISABLE_INJECT = 46 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_DCACHE_MODE = 47 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_DCACHE_REPORTS_PHYSICAL = 48 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_RSI_DISABLE_DATIN_FASTPATH = 49 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_PCKT_BLK_PRB = 50 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_P9P9_MODE = 51 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_FORBID_MMIO_READ_GT_32 = 52 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_FORBID_MMIO_ATOMIC = 53 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_OPT_SNOOP_CP = 54 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_MRBCP_TRACK_ALL = 55 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_RESTRICT_CHIP_GROUP = 56 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_OCAPI_MODE = 57 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_NVLINK_MODE = 58 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_PREALLOC2_INTS = 59 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_PREALLOC2_PWR0 = 60 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_PREALLOC2_PWR1 = 61 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_ENABLE_CONTEXT_LCO = 62 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG0_CONFIG_MA_DSA_OPT_FAIL_WAKE = 63 ;
+
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_RESERVED1 = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_MA_DSA_OPT_CLAIM_UR = 1 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_MA_DSA_OPT_FLUSH_UR = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_MA_DSA_OPT_RP_MODE = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_ADR_BAR_MODE = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_DISABLE_NN_RN = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_DISABLE_VG_NOT_SYS = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_DISABLE_G = 7 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_DISABLE_LN = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_SKIP_G = 9 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_MA_MCRESP_OPT_WRP = 10 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_INJ = 11 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_DMA = 12 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_INC_PRI_MASK = 13 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_INC_PRI_MASK_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_RESERVED2 = 16 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_MA_RSNOOP_OPT_B = 17 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_MA_RSNOOP_OPT_C = 18 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_MA_SCRESP_OPT_A = 19 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_MA_SCRESP_OPT_B = 20 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_MA_SCRESP_OPT_C = 21 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_RESERVED4 = 22 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_MACH_CORRENAB = 23 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_MACH_INJECT_ENABLE1 = 24 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_MACH_INJECT_ENABLE2 = 25 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_RXO_CORRENAB = 26 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_RXO_INJECT_ENABLE1 = 27 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_RXO_INJECT_ENABLE2 = 28 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_RSI_CORRENAB = 29 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_RSI_INJECT_ENABLE1 = 30 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_RSI_INJECT_ENABLE2 = 31 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM = 32 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_MA_DSA_OPT_DMA_UPG = 34 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_EVAPORATE_BY_LCO = 35 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_MRBGP_TRACK_ALL = 36 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_MRBSP_TRACK_ALL = 37 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_ENABLE_PBUS = 38 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_BRAZOS_MODE = 39 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_ENABLE_SNARF_CPM = 40 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_PREALLOC2_REQ0 = 41 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_PREALLOC2_PRB0 = 42 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_PREALLOC2_REQ1 = 43 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_PREALLOC2_PRB1 = 44 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_PREALLOC2_XATS = 45 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_DISABLE_INJECT = 46 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_DCACHE_MODE = 47 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_DCACHE_REPORTS_PHYSICAL = 48 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_RSI_DISABLE_DATIN_FASTPATH = 49 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_PCKT_BLK_PRB = 50 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_P9P9_MODE = 51 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_FORBID_MMIO_READ_GT_32 = 52 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_FORBID_MMIO_ATOMIC = 53 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_OPT_SNOOP_CP = 54 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_MRBCP_TRACK_ALL = 55 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_RESTRICT_CHIP_GROUP = 56 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_OCAPI_MODE = 57 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_NVLINK_MODE = 58 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_PREALLOC2_INTS = 59 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_PREALLOC2_PWR0 = 60 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_PREALLOC2_PWR1 = 61 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_ENABLE_CONTEXT_LCO = 62 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG0_CONFIG_MA_DSA_OPT_FAIL_WAKE = 63 ;
+
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_RESERVED1 = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_MA_DSA_OPT_CLAIM_UR = 1 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_MA_DSA_OPT_FLUSH_UR = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_MA_DSA_OPT_RP_MODE = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_ADR_BAR_MODE = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_DISABLE_NN_RN = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_DISABLE_VG_NOT_SYS = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_DISABLE_G = 7 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_DISABLE_LN = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_SKIP_G = 9 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_MA_MCRESP_OPT_WRP = 10 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_INJ = 11 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_DMA = 12 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_INC_PRI_MASK = 13 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_INC_PRI_MASK_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_RESERVED2 = 16 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_MA_RSNOOP_OPT_B = 17 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_MA_RSNOOP_OPT_C = 18 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_MA_SCRESP_OPT_A = 19 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_MA_SCRESP_OPT_B = 20 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_MA_SCRESP_OPT_C = 21 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_RESERVED4 = 22 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_MACH_CORRENAB = 23 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_MACH_INJECT_ENABLE1 = 24 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_MACH_INJECT_ENABLE2 = 25 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_RXO_CORRENAB = 26 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_RXO_INJECT_ENABLE1 = 27 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_RXO_INJECT_ENABLE2 = 28 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_RSI_CORRENAB = 29 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_RSI_INJECT_ENABLE1 = 30 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_RSI_INJECT_ENABLE2 = 31 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM = 32 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_MA_DSA_OPT_DMA_UPG = 34 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_EVAPORATE_BY_LCO = 35 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_MRBGP_TRACK_ALL = 36 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_MRBSP_TRACK_ALL = 37 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_ENABLE_PBUS = 38 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_BRAZOS_MODE = 39 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_ENABLE_SNARF_CPM = 40 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_PREALLOC2_REQ0 = 41 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_PREALLOC2_PRB0 = 42 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_PREALLOC2_REQ1 = 43 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_PREALLOC2_PRB1 = 44 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_PREALLOC2_XATS = 45 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_DISABLE_INJECT = 46 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_DCACHE_MODE = 47 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_DCACHE_REPORTS_PHYSICAL = 48 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_RSI_DISABLE_DATIN_FASTPATH = 49 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_PCKT_BLK_PRB = 50 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_P9P9_MODE = 51 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_FORBID_MMIO_READ_GT_32 = 52 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_FORBID_MMIO_ATOMIC = 53 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_OPT_SNOOP_CP = 54 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_MRBCP_TRACK_ALL = 55 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_RESTRICT_CHIP_GROUP = 56 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_OCAPI_MODE = 57 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_NVLINK_MODE = 58 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_PREALLOC2_INTS = 59 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_PREALLOC2_PWR0 = 60 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_PREALLOC2_PWR1 = 61 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_ENABLE_CONTEXT_LCO = 62 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG0_CONFIG_MA_DSA_OPT_FAIL_WAKE = 63 ;
+
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_RESERVED1 = 0 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_MA_DSA_OPT_CLAIM_UR = 1 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_MA_DSA_OPT_FLUSH_UR = 2 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_MA_DSA_OPT_RP_MODE = 3 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_ADR_BAR_MODE = 4 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_DISABLE_NN_RN = 5 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_DISABLE_VG_NOT_SYS = 6 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_DISABLE_G = 7 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_DISABLE_LN = 8 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_SKIP_G = 9 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_MA_MCRESP_OPT_WRP = 10 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_INJ = 11 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_DMA = 12 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_INC_PRI_MASK = 13 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_INC_PRI_MASK_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_RESERVED2 = 16 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_MA_RSNOOP_OPT_B = 17 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_MA_RSNOOP_OPT_C = 18 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_MA_SCRESP_OPT_A = 19 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_MA_SCRESP_OPT_B = 20 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_MA_SCRESP_OPT_C = 21 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_RESERVED4 = 22 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_MACH_CORRENAB = 23 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_MACH_INJECT_ENABLE1 = 24 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_MACH_INJECT_ENABLE2 = 25 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_RXO_CORRENAB = 26 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_RXO_INJECT_ENABLE1 = 27 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_RXO_INJECT_ENABLE2 = 28 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_RSI_CORRENAB = 29 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_RSI_INJECT_ENABLE1 = 30 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_RSI_INJECT_ENABLE2 = 31 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM = 32 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_MA_DSA_OPT_DMA_UPG = 34 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_EVAPORATE_BY_LCO = 35 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_MRBGP_TRACK_ALL = 36 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_MRBSP_TRACK_ALL = 37 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_ENABLE_PBUS = 38 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_BRAZOS_MODE = 39 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_ENABLE_SNARF_CPM = 40 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_PREALLOC2_REQ0 = 41 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_PREALLOC2_PRB0 = 42 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_PREALLOC2_REQ1 = 43 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_PREALLOC2_PRB1 = 44 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_PREALLOC2_XATS = 45 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_DISABLE_INJECT = 46 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_DCACHE_MODE = 47 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_DCACHE_REPORTS_PHYSICAL = 48 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_RSI_DISABLE_DATIN_FASTPATH = 49 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_PCKT_BLK_PRB = 50 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_P9P9_MODE = 51 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_FORBID_MMIO_READ_GT_32 = 52 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_FORBID_MMIO_ATOMIC = 53 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_OPT_SNOOP_CP = 54 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_MRBCP_TRACK_ALL = 55 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_RESTRICT_CHIP_GROUP = 56 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_OCAPI_MODE = 57 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_NVLINK_MODE = 58 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_PREALLOC2_INTS = 59 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_PREALLOC2_PWR0 = 60 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_PREALLOC2_PWR1 = 61 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_ENABLE_CONTEXT_LCO = 62 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG0_CONFIG_MA_DSA_OPT_FAIL_WAKE = 63 ;
+
+static const uint8_t P9N2_NV_CONFIG0_RESERVED0 = 0 ;
+static const uint8_t P9N2_NV_CONFIG0_RESERVED1 = 1 ;
+static const uint8_t P9N2_NV_CONFIG0_RESERVED1_LEN = 3 ;
+static const uint8_t P9N2_NV_CONFIG0_CONFIG_ADR_BAR_MODE = 4 ;
+static const uint8_t P9N2_NV_CONFIG0_CONFIG_GEN_HEAD_DELAY = 5 ;
+static const uint8_t P9N2_NV_CONFIG0_CONFIG_GEN_HEAD_DELAY_LEN = 5 ;
+static const uint8_t P9N2_NV_CONFIG0_CONFIG_MRBGP_DIV2_COUNT_AT_EXP = 10 ;
+static const uint8_t P9N2_NV_CONFIG0_CONFIG_MRBSP_DIV2_COUNT_AT_EXP = 11 ;
+static const uint8_t P9N2_NV_CONFIG0_CONFIG_MRBGP_DIS_DYN_ADJ = 12 ;
+static const uint8_t P9N2_NV_CONFIG0_CONFIG_MRBSP_DIS_DYN_ADJ = 13 ;
+static const uint8_t P9N2_NV_CONFIG0_CONFIG_MRBGP_DIS_DYN_LVL_ADJ = 14 ;
+static const uint8_t P9N2_NV_CONFIG0_CONFIG_MRBSP_DIS_DYN_LVL_ADJ = 15 ;
+static const uint8_t P9N2_NV_CONFIG0_CONFIG_MRBGP_THRESH1 = 16 ;
+static const uint8_t P9N2_NV_CONFIG0_CONFIG_MRBGP_THRESH1_LEN = 6 ;
+static const uint8_t P9N2_NV_CONFIG0_CONFIG_MRBGP_THRESH2 = 22 ;
+static const uint8_t P9N2_NV_CONFIG0_CONFIG_MRBGP_THRESH2_LEN = 6 ;
+static const uint8_t P9N2_NV_CONFIG0_CONFIG_MRBSP_THRESH1 = 28 ;
+static const uint8_t P9N2_NV_CONFIG0_CONFIG_MRBSP_THRESH1_LEN = 6 ;
+static const uint8_t P9N2_NV_CONFIG0_CONFIG_MRBSP_THRESH2 = 34 ;
+static const uint8_t P9N2_NV_CONFIG0_CONFIG_MRBSP_THRESH2_LEN = 6 ;
+static const uint8_t P9N2_NV_CONFIG0_CONFIG_MRBGP_MAX_LEVEL = 40 ;
+static const uint8_t P9N2_NV_CONFIG0_CONFIG_MRBGP_MAX_LEVEL_LEN = 4 ;
+static const uint8_t P9N2_NV_CONFIG0_CONFIG_MRBSP_MAX_LEVEL = 44 ;
+static const uint8_t P9N2_NV_CONFIG0_CONFIG_MRBSP_MAX_LEVEL_LEN = 4 ;
+static const uint8_t P9N2_NV_CONFIG0_CONFIG_BRAZOS_MODE = 48 ;
+static const uint8_t P9N2_NV_CONFIG0_CONFIG_DISABLE_PBM_ECC_COR = 49 ;
+static const uint8_t P9N2_NV_CONFIG0_CONFIG_LAB_RANDOMIZE_PE_01 = 50 ;
+static const uint8_t P9N2_NV_CONFIG0_CONFIG_LAB_RANDOMIZE_PE_23 = 51 ;
+static const uint8_t P9N2_NV_CONFIG0_CONFIG_OCAPI_MODE = 52 ;
+static const uint8_t P9N2_NV_CONFIG0_CONFIG_NVLINK_MODE = 53 ;
+static const uint8_t P9N2_NV_CONFIG0_CONFIG_RANDOMIZE_INT_SLICE = 54 ;
+static const uint8_t P9N2_NV_CONFIG0_CONFIG_OTL0_ENABLE = 55 ;
+static const uint8_t P9N2_NV_CONFIG0_CONFIG_OTL1_ENABLE = 56 ;
+static const uint8_t P9N2_NV_CONFIG0_CONFIG_DISABLE_2CREDS_TO_OTL = 57 ;
+static const uint8_t P9N2_NV_CONFIG0_CONFIG_RESTRICT_RSPIN_CREDIT_TO1 = 58 ;
+static const uint8_t P9N2_NV_CONFIG0_RESERVED2 = 59 ;
+static const uint8_t P9N2_NV_CONFIG0_RESERVED2_LEN = 5 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_RESERVED1 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_MA_DSA_OPT_CLAIM_UR = 1 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_MA_DSA_OPT_FLUSH_UR = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_MA_DSA_OPT_RP_MODE = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_ADR_BAR_MODE = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_DISABLE_NN_RN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_DISABLE_VG_NOT_SYS = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_DISABLE_G = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_DISABLE_LN = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_SKIP_G = 9 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_MA_MCRESP_OPT_WRP = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_INJ = 11 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_DMA = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_INC_PRI_MASK = 13 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_INC_PRI_MASK_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_RESERVED2 = 16 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_MA_RSNOOP_OPT_B = 17 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_MA_RSNOOP_OPT_C = 18 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_MA_SCRESP_OPT_A = 19 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_MA_SCRESP_OPT_B = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_MA_SCRESP_OPT_C = 21 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_RESERVED4 = 22 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_MACH_CORRENAB = 23 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_MACH_INJECT_ENABLE1 = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_MACH_INJECT_ENABLE2 = 25 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_RXO_CORRENAB = 26 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_RXO_INJECT_ENABLE1 = 27 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_RXO_INJECT_ENABLE2 = 28 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_RSI_CORRENAB = 29 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_RSI_INJECT_ENABLE1 = 30 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_RSI_INJECT_ENABLE2 = 31 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_MA_DSA_OPT_DMA_UPG = 34 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_EVAPORATE_BY_LCO = 35 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_MRBGP_TRACK_ALL = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_MRBSP_TRACK_ALL = 37 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_ENABLE_PBUS = 38 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_BRAZOS_MODE = 39 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_ENABLE_SNARF_CPM = 40 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_PREALLOC2_REQ0 = 41 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_PREALLOC2_PRB0 = 42 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_PREALLOC2_REQ1 = 43 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_PREALLOC2_PRB1 = 44 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_PREALLOC2_XATS = 45 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_DISABLE_INJECT = 46 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_DCACHE_MODE = 47 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_DCACHE_REPORTS_PHYSICAL = 48 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_RSI_DISABLE_DATIN_FASTPATH = 49 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_PCKT_BLK_PRB = 50 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_P9P9_MODE = 51 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_FORBID_MMIO_READ_GT_32 = 52 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_FORBID_MMIO_ATOMIC = 53 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_OPT_SNOOP_CP = 54 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_MRBCP_TRACK_ALL = 55 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_RESTRICT_CHIP_GROUP = 56 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_OCAPI_MODE = 57 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_NVLINK_MODE = 58 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_PREALLOC2_INTS = 59 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_PREALLOC2_PWR0 = 60 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_PREALLOC2_PWR1 = 61 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_ENABLE_CONTEXT_LCO = 62 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG0_CONFIG_MA_DSA_OPT_FAIL_WAKE = 63 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_RESERVED1 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_MA_DSA_OPT_CLAIM_UR = 1 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_MA_DSA_OPT_FLUSH_UR = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_MA_DSA_OPT_RP_MODE = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_ADR_BAR_MODE = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_DISABLE_NN_RN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_DISABLE_VG_NOT_SYS = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_DISABLE_G = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_DISABLE_LN = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_SKIP_G = 9 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_MA_MCRESP_OPT_WRP = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_INJ = 11 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_DMA = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_INC_PRI_MASK = 13 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_INC_PRI_MASK_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_RESERVED2 = 16 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_MA_RSNOOP_OPT_B = 17 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_MA_RSNOOP_OPT_C = 18 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_MA_SCRESP_OPT_A = 19 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_MA_SCRESP_OPT_B = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_MA_SCRESP_OPT_C = 21 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_RESERVED4 = 22 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_MACH_CORRENAB = 23 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_MACH_INJECT_ENABLE1 = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_MACH_INJECT_ENABLE2 = 25 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_RXO_CORRENAB = 26 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_RXO_INJECT_ENABLE1 = 27 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_RXO_INJECT_ENABLE2 = 28 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_RSI_CORRENAB = 29 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_RSI_INJECT_ENABLE1 = 30 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_RSI_INJECT_ENABLE2 = 31 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_MA_DSA_OPT_DMA_UPG = 34 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_EVAPORATE_BY_LCO = 35 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_MRBGP_TRACK_ALL = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_MRBSP_TRACK_ALL = 37 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_ENABLE_PBUS = 38 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_BRAZOS_MODE = 39 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_ENABLE_SNARF_CPM = 40 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_PREALLOC2_REQ0 = 41 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_PREALLOC2_PRB0 = 42 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_PREALLOC2_REQ1 = 43 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_PREALLOC2_PRB1 = 44 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_PREALLOC2_XATS = 45 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_DISABLE_INJECT = 46 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_DCACHE_MODE = 47 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_DCACHE_REPORTS_PHYSICAL = 48 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_RSI_DISABLE_DATIN_FASTPATH = 49 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_PCKT_BLK_PRB = 50 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_P9P9_MODE = 51 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_FORBID_MMIO_READ_GT_32 = 52 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_FORBID_MMIO_ATOMIC = 53 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_OPT_SNOOP_CP = 54 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_MRBCP_TRACK_ALL = 55 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_RESTRICT_CHIP_GROUP = 56 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_OCAPI_MODE = 57 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_NVLINK_MODE = 58 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_PREALLOC2_INTS = 59 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_PREALLOC2_PWR0 = 60 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_PREALLOC2_PWR1 = 61 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_ENABLE_CONTEXT_LCO = 62 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG0_CONFIG_MA_DSA_OPT_FAIL_WAKE = 63 ;
+
+static const uint8_t P9N2_PU_NPU1_SM2_CONFIG1_COMPRESSED_RSP_ENA = 0 ;
+static const uint8_t P9N2_PU_NPU1_SM2_CONFIG1_RESERVED1 = 1 ;
+static const uint8_t P9N2_PU_NPU1_SM2_CONFIG1_RESERVED1_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU1_SM2_CONFIG1_CREQ_AE_ALWAYS = 4 ;
+static const uint8_t P9N2_PU_NPU1_SM2_CONFIG1_DGD_AE_ALWAYS = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM2_CONFIG1_RSP_AE_ALWAYS = 6 ;
+static const uint8_t P9N2_PU_NPU1_SM2_CONFIG1_RESERVED2 = 7 ;
+static const uint8_t P9N2_PU_NPU1_SM2_CONFIG1_NTL_RESET = 8 ;
+static const uint8_t P9N2_PU_NPU1_SM2_CONFIG1_NTL_RESET_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU1_SM2_CONFIG1_RESERVED3 = 10 ;
+static const uint8_t P9N2_PU_NPU1_SM2_CONFIG1_RESERVED3_LEN = 54 ;
+
+static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG1_MGR_CREDIT = 0 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG1_MGR_CREDIT_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG1_MRG_PBTX_NBUF = 2 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG1_MRG_PBTX_NBUF_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG1_MRG_RDBF_NBUF = 5 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG1_MRG_RDBF_NBUF_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG1_MRG_IBWR_NBUF = 9 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG1_MRG_IBWR_NBUF_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG1_MRG_IBRD_NBUF = 13 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG1_MRG_IBRD_NBUF_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG1_MRG_BBRD_NBUF = 16 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG1_MRG_BBRD_NBUF_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG1_MRG_OBRD_NBUF = 19 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG1_MRG_OBRD_NBUF_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG1_MRG_CR_DIS = 22 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG1_MRG_CTLW_CR_DIS = 23 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG1_NTLR_PAUSE_THRESH = 24 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG1_NTLR_PAUSE_THRESH_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG1_CTLR_HP_THRESH = 26 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG1_CTLR_HP_THRESH_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG1_NTLW_PAUSE_THRESH = 28 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG1_NTLW_PAUSE_THRESH_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG1_CTLW_HP_THRESH = 30 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG1_CTLW_HP_THRESH_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG1_PBTX_REDUCE_RTAG = 32 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG1_PBTX_DELAY_BDONE = 33 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG1_PBTX_FLIP_IMIN_BIG = 34 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG1_PBTX_FLIP_IMIN_LITTLE = 35 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG1_ALU_SAFE_LATENCY = 36 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG1_ALU_FLIP_ENDIAN_BIG = 37 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG1_ALU_FLIP_ENDIAN_LITTLE = 38 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG1_PBTX_EARLY_AFTAG = 39 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG1_CONFIG_OCAPI_MODE = 40 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG1_CONFIG_NVLINK_MODE = 41 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG1_CHKNSW_HW405659 = 42 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG1_RESERVED1 = 43 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG1_RESERVED1_LEN = 21 ;
+
+static const uint8_t P9N2_PU_NPU1_SM1_CONFIG1_COMPRESSED_RSP_ENA = 0 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CONFIG1_RESERVED1 = 1 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CONFIG1_RESERVED1_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CONFIG1_CREQ_AE_ALWAYS = 4 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CONFIG1_DGD_AE_ALWAYS = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CONFIG1_RSP_AE_ALWAYS = 6 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CONFIG1_RESERVED2 = 7 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CONFIG1_NTL_RESET = 8 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CONFIG1_NTL_RESET_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CONFIG1_RESERVED3 = 10 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CONFIG1_RESERVED3_LEN = 54 ;
+
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK = 0 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ = 4 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB = 8 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG1_CONFIG_ARB_NONCRR_SAFETY = 12 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG1_CONFIG_ARB_NONCRR_SAFETY_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG1_CONFIG_EPSILON_WLN_COUNT = 16 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG1_CONFIG_EPSILON_WLN_COUNT_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL = 28 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA = 32 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG1_CONFIG_ADDR_EX_MASK_ENA = 36 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG1_CONFIG_ADDR_EX_MASK_ENA_LEN = 7 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG1_CONFIG_PCKT_LONG_CL_DMA_INJ = 43 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG1_CONFIG_PCKT_LONG_PR_DMA_INJ = 44 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG1_CONFIG_PCKT_LONG_MIN_COUNT = 45 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG1_CONFIG_PCKT_LONG_MIN_COUNT_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG1_CONFIG_PCKT_LONG_USES_HANG = 51 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG1_CONFIG_DONT_RETRY_LCO_LONG = 52 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG1_CONFIG_DONT_RETRY_LCO_LONG_STRESSED = 53 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG1_CONFIG_DONT_RETRY_LCO_SHORT = 54 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG1_CONFIG_DONT_RETRY_LCO_SHORT_STRESSED = 55 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG1_CONFIG_STOP_ASB_AT_LN_SCOPE = 56 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG1_CONFIG_STOP_ASB_AT_G_SCOPE = 57 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG1_CONFIG_CHICKEN_DISABLE_HW405632_RELAXED_PROBE = 58 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG1_CONFIG_CHICKEN_HW406785_DISABLE_FIX = 59 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG1_RESERVED = 60 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG1_RESERVED_LEN = 4 ;
+
+static const uint8_t P9N2__SM2_CONFIG1_COMPRESSED_RSP_ENA = 0 ;
+static const uint8_t P9N2__SM2_CONFIG1_RESERVED1 = 1 ;
+static const uint8_t P9N2__SM2_CONFIG1_RESERVED1_LEN = 3 ;
+static const uint8_t P9N2__SM2_CONFIG1_CREQ_AE_ALWAYS = 4 ;
+static const uint8_t P9N2__SM2_CONFIG1_DGD_AE_ALWAYS = 5 ;
+static const uint8_t P9N2__SM2_CONFIG1_RSP_AE_ALWAYS = 6 ;
+static const uint8_t P9N2__SM2_CONFIG1_RESERVED2 = 7 ;
+static const uint8_t P9N2__SM2_CONFIG1_NTL_RESET = 8 ;
+static const uint8_t P9N2__SM2_CONFIG1_NTL_RESET_LEN = 2 ;
+static const uint8_t P9N2__SM2_CONFIG1_RESERVED3 = 10 ;
+static const uint8_t P9N2__SM2_CONFIG1_RESERVED3_LEN = 54 ;
+
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG1_CONFIG_ARB_NONCRR_SAFETY = 12 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG1_CONFIG_ARB_NONCRR_SAFETY_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG1_CONFIG_EPSILON_WLN_COUNT = 16 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG1_CONFIG_EPSILON_WLN_COUNT_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL = 28 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA = 32 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG1_CONFIG_ADDR_EX_MASK_ENA = 36 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG1_CONFIG_ADDR_EX_MASK_ENA_LEN = 7 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG1_CONFIG_PCKT_LONG_CL_DMA_INJ = 43 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG1_CONFIG_PCKT_LONG_PR_DMA_INJ = 44 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG1_CONFIG_PCKT_LONG_MIN_COUNT = 45 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG1_CONFIG_PCKT_LONG_MIN_COUNT_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG1_CONFIG_PCKT_LONG_USES_HANG = 51 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG1_CONFIG_DONT_RETRY_LCO_LONG = 52 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG1_CONFIG_DONT_RETRY_LCO_LONG_STRESSED = 53 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG1_CONFIG_DONT_RETRY_LCO_SHORT = 54 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG1_CONFIG_DONT_RETRY_LCO_SHORT_STRESSED = 55 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG1_CONFIG_STOP_ASB_AT_LN_SCOPE = 56 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG1_CONFIG_STOP_ASB_AT_G_SCOPE = 57 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG1_CONFIG_CHICKEN_DISABLE_HW405632_RELAXED_PROBE = 58 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG1_CONFIG_CHICKEN_HW406785_DISABLE_FIX = 59 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG1_RESERVED = 60 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG1_RESERVED_LEN = 4 ;
+
+static const uint8_t P9N2__SM1_CONFIG1_COMPRESSED_RSP_ENA = 0 ;
+static const uint8_t P9N2__SM1_CONFIG1_RESERVED1 = 1 ;
+static const uint8_t P9N2__SM1_CONFIG1_RESERVED1_LEN = 3 ;
+static const uint8_t P9N2__SM1_CONFIG1_CREQ_AE_ALWAYS = 4 ;
+static const uint8_t P9N2__SM1_CONFIG1_DGD_AE_ALWAYS = 5 ;
+static const uint8_t P9N2__SM1_CONFIG1_RSP_AE_ALWAYS = 6 ;
+static const uint8_t P9N2__SM1_CONFIG1_RESERVED2 = 7 ;
+static const uint8_t P9N2__SM1_CONFIG1_NTL_RESET = 8 ;
+static const uint8_t P9N2__SM1_CONFIG1_NTL_RESET_LEN = 2 ;
+static const uint8_t P9N2__SM1_CONFIG1_RESERVED3 = 10 ;
+static const uint8_t P9N2__SM1_CONFIG1_RESERVED3_LEN = 54 ;
+
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG1_CONFIG_ARB_NONCRR_SAFETY = 12 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG1_CONFIG_ARB_NONCRR_SAFETY_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG1_CONFIG_EPSILON_WLN_COUNT = 16 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG1_CONFIG_EPSILON_WLN_COUNT_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL = 28 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA = 32 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG1_CONFIG_ADDR_EX_MASK_ENA = 36 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG1_CONFIG_ADDR_EX_MASK_ENA_LEN = 7 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG1_CONFIG_PCKT_LONG_CL_DMA_INJ = 43 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG1_CONFIG_PCKT_LONG_PR_DMA_INJ = 44 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG1_CONFIG_PCKT_LONG_MIN_COUNT = 45 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG1_CONFIG_PCKT_LONG_MIN_COUNT_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG1_CONFIG_PCKT_LONG_USES_HANG = 51 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG1_CONFIG_DONT_RETRY_LCO_LONG = 52 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG1_CONFIG_DONT_RETRY_LCO_LONG_STRESSED = 53 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG1_CONFIG_DONT_RETRY_LCO_SHORT = 54 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG1_CONFIG_DONT_RETRY_LCO_SHORT_STRESSED = 55 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG1_CONFIG_STOP_ASB_AT_LN_SCOPE = 56 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG1_CONFIG_STOP_ASB_AT_G_SCOPE = 57 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG1_CONFIG_CHICKEN_DISABLE_HW405632_RELAXED_PROBE = 58 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG1_CONFIG_CHICKEN_HW406785_DISABLE_FIX = 59 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG1_RESERVED = 60 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG1_RESERVED_LEN = 4 ;
+
+static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG1_CONFIG_MRBCP_DIV2_COUNT_AT_EXP = 0 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG1_CONFIG_MRBCP_DIS_DYN_ADJ = 1 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG1_CONFIG_MRBCP_DIS_DYN_LVL_ADJ = 2 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG1_CONFIG_MRBCP_THRESH1 = 3 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG1_CONFIG_MRBCP_THRESH1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG1_CONFIG_MRBCP_THRESH2 = 9 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG1_CONFIG_MRBCP_THRESH2_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG1_CONFIG_MRBCP_MAX_LEVEL = 15 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG1_CONFIG_MRBCP_MAX_LEVEL_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG1_RESERVED1 = 19 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG1_CONFIG_CTL_FIR_TO_INHIBIT_MASK = 20 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG1_CONFIG_CTL_FIR_TO_INHIBIT_MASK_LEN = 16 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG1_CONFIG_BRK0_FENCE_TO_INHIBIT_MASK = 36 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG1_CONFIG_BRK1_FENCE_TO_INHIBIT_MASK = 37 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG1_CONFIG_CHICKEN_HW405869_DISABLE_PATCH = 38 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG1_RESERVED2 = 39 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG1_RESERVED2_LEN = 25 ;
+
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG1_CONFIG_ARB_NONCRR_SAFETY = 12 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG1_CONFIG_ARB_NONCRR_SAFETY_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG1_CONFIG_EPSILON_WLN_COUNT = 16 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG1_CONFIG_EPSILON_WLN_COUNT_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL = 28 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA = 32 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG1_CONFIG_ADDR_EX_MASK_ENA = 36 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG1_CONFIG_ADDR_EX_MASK_ENA_LEN = 7 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG1_CONFIG_PCKT_LONG_CL_DMA_INJ = 43 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG1_CONFIG_PCKT_LONG_PR_DMA_INJ = 44 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG1_CONFIG_PCKT_LONG_MIN_COUNT = 45 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG1_CONFIG_PCKT_LONG_MIN_COUNT_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG1_CONFIG_PCKT_LONG_USES_HANG = 51 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG1_CONFIG_DONT_RETRY_LCO_LONG = 52 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG1_CONFIG_DONT_RETRY_LCO_LONG_STRESSED = 53 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG1_CONFIG_DONT_RETRY_LCO_SHORT = 54 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG1_CONFIG_DONT_RETRY_LCO_SHORT_STRESSED = 55 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG1_CONFIG_STOP_ASB_AT_LN_SCOPE = 56 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG1_CONFIG_STOP_ASB_AT_G_SCOPE = 57 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG1_CONFIG_CHICKEN_DISABLE_HW405632_RELAXED_PROBE = 58 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG1_CONFIG_CHICKEN_HW406785_DISABLE_FIX = 59 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG1_RESERVED = 60 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG1_RESERVED_LEN = 4 ;
+
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG1_CONFIG_ARB_NONCRR_SAFETY = 12 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG1_CONFIG_ARB_NONCRR_SAFETY_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG1_CONFIG_EPSILON_WLN_COUNT = 16 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG1_CONFIG_EPSILON_WLN_COUNT_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL = 28 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA = 32 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG1_CONFIG_ADDR_EX_MASK_ENA = 36 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG1_CONFIG_ADDR_EX_MASK_ENA_LEN = 7 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG1_CONFIG_PCKT_LONG_CL_DMA_INJ = 43 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG1_CONFIG_PCKT_LONG_PR_DMA_INJ = 44 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG1_CONFIG_PCKT_LONG_MIN_COUNT = 45 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG1_CONFIG_PCKT_LONG_MIN_COUNT_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG1_CONFIG_PCKT_LONG_USES_HANG = 51 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG1_CONFIG_DONT_RETRY_LCO_LONG = 52 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG1_CONFIG_DONT_RETRY_LCO_LONG_STRESSED = 53 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG1_CONFIG_DONT_RETRY_LCO_SHORT = 54 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG1_CONFIG_DONT_RETRY_LCO_SHORT_STRESSED = 55 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG1_CONFIG_STOP_ASB_AT_LN_SCOPE = 56 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG1_CONFIG_STOP_ASB_AT_G_SCOPE = 57 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG1_CONFIG_CHICKEN_DISABLE_HW405632_RELAXED_PROBE = 58 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG1_CONFIG_CHICKEN_HW406785_DISABLE_FIX = 59 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG1_RESERVED = 60 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG1_RESERVED_LEN = 4 ;
+
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG1_COMPRESSED_RSP_ENA = 0 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG1_RESERVED1 = 1 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG1_RESERVED1_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG1_CREQ_AE_ALWAYS = 4 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG1_DGD_AE_ALWAYS = 5 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG1_RSP_AE_ALWAYS = 6 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG1_RESERVED2 = 7 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG1_NTL_RESET = 8 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG1_NTL_RESET_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG1_RESERVED3 = 10 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG1_RESERVED3_LEN = 54 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG1_CONFIG_ARB_NONCRR_SAFETY = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG1_CONFIG_ARB_NONCRR_SAFETY_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG1_CONFIG_EPSILON_WLN_COUNT = 16 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG1_CONFIG_EPSILON_WLN_COUNT_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL = 28 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG1_CONFIG_ADDR_EX_MASK_ENA = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG1_CONFIG_ADDR_EX_MASK_ENA_LEN = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG1_CONFIG_PCKT_LONG_CL_DMA_INJ = 43 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG1_CONFIG_PCKT_LONG_PR_DMA_INJ = 44 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG1_CONFIG_PCKT_LONG_MIN_COUNT = 45 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG1_CONFIG_PCKT_LONG_MIN_COUNT_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG1_CONFIG_PCKT_LONG_USES_HANG = 51 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG1_CONFIG_DONT_RETRY_LCO_LONG = 52 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG1_CONFIG_DONT_RETRY_LCO_LONG_STRESSED = 53 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG1_CONFIG_DONT_RETRY_LCO_SHORT = 54 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG1_CONFIG_DONT_RETRY_LCO_SHORT_STRESSED = 55 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG1_CONFIG_STOP_ASB_AT_LN_SCOPE = 56 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG1_CONFIG_STOP_ASB_AT_G_SCOPE = 57 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG1_CONFIG_CHICKEN_DISABLE_HW405632_RELAXED_PROBE = 58 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG1_CONFIG_CHICKEN_HW406785_DISABLE_FIX = 59 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG1_RESERVED = 60 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG1_RESERVED_LEN = 4 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG1_CONFIG_ARB_NONCRR_SAFETY = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG1_CONFIG_ARB_NONCRR_SAFETY_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG1_CONFIG_EPSILON_WLN_COUNT = 16 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG1_CONFIG_EPSILON_WLN_COUNT_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL = 28 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG1_CONFIG_ADDR_EX_MASK_ENA = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG1_CONFIG_ADDR_EX_MASK_ENA_LEN = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG1_CONFIG_PCKT_LONG_CL_DMA_INJ = 43 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG1_CONFIG_PCKT_LONG_PR_DMA_INJ = 44 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG1_CONFIG_PCKT_LONG_MIN_COUNT = 45 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG1_CONFIG_PCKT_LONG_MIN_COUNT_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG1_CONFIG_PCKT_LONG_USES_HANG = 51 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG1_CONFIG_DONT_RETRY_LCO_LONG = 52 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG1_CONFIG_DONT_RETRY_LCO_LONG_STRESSED = 53 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG1_CONFIG_DONT_RETRY_LCO_SHORT = 54 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG1_CONFIG_DONT_RETRY_LCO_SHORT_STRESSED = 55 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG1_CONFIG_STOP_ASB_AT_LN_SCOPE = 56 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG1_CONFIG_STOP_ASB_AT_G_SCOPE = 57 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG1_CONFIG_CHICKEN_DISABLE_HW405632_RELAXED_PROBE = 58 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG1_CONFIG_CHICKEN_HW406785_DISABLE_FIX = 59 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG1_RESERVED = 60 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG1_RESERVED_LEN = 4 ;
+
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG1_CONFIG_ARB_NONCRR_SAFETY = 12 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG1_CONFIG_ARB_NONCRR_SAFETY_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG1_CONFIG_EPSILON_WLN_COUNT = 16 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG1_CONFIG_EPSILON_WLN_COUNT_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL = 28 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA = 32 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG1_CONFIG_ADDR_EX_MASK_ENA = 36 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG1_CONFIG_ADDR_EX_MASK_ENA_LEN = 7 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG1_CONFIG_PCKT_LONG_CL_DMA_INJ = 43 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG1_CONFIG_PCKT_LONG_PR_DMA_INJ = 44 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG1_CONFIG_PCKT_LONG_MIN_COUNT = 45 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG1_CONFIG_PCKT_LONG_MIN_COUNT_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG1_CONFIG_PCKT_LONG_USES_HANG = 51 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG1_CONFIG_DONT_RETRY_LCO_LONG = 52 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG1_CONFIG_DONT_RETRY_LCO_LONG_STRESSED = 53 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG1_CONFIG_DONT_RETRY_LCO_SHORT = 54 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG1_CONFIG_DONT_RETRY_LCO_SHORT_STRESSED = 55 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG1_CONFIG_STOP_ASB_AT_LN_SCOPE = 56 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG1_CONFIG_STOP_ASB_AT_G_SCOPE = 57 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG1_CONFIG_CHICKEN_DISABLE_HW405632_RELAXED_PROBE = 58 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG1_CONFIG_CHICKEN_HW406785_DISABLE_FIX = 59 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG1_RESERVED = 60 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG1_RESERVED_LEN = 4 ;
+
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG1_CONFIG_ARB_NONCRR_SAFETY = 12 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG1_CONFIG_ARB_NONCRR_SAFETY_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG1_CONFIG_EPSILON_WLN_COUNT = 16 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG1_CONFIG_EPSILON_WLN_COUNT_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL = 28 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA = 32 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG1_CONFIG_ADDR_EX_MASK_ENA = 36 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG1_CONFIG_ADDR_EX_MASK_ENA_LEN = 7 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG1_CONFIG_PCKT_LONG_CL_DMA_INJ = 43 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG1_CONFIG_PCKT_LONG_PR_DMA_INJ = 44 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG1_CONFIG_PCKT_LONG_MIN_COUNT = 45 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG1_CONFIG_PCKT_LONG_MIN_COUNT_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG1_CONFIG_PCKT_LONG_USES_HANG = 51 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG1_CONFIG_DONT_RETRY_LCO_LONG = 52 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG1_CONFIG_DONT_RETRY_LCO_LONG_STRESSED = 53 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG1_CONFIG_DONT_RETRY_LCO_SHORT = 54 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG1_CONFIG_DONT_RETRY_LCO_SHORT_STRESSED = 55 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG1_CONFIG_STOP_ASB_AT_LN_SCOPE = 56 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG1_CONFIG_STOP_ASB_AT_G_SCOPE = 57 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG1_CONFIG_CHICKEN_DISABLE_HW405632_RELAXED_PROBE = 58 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG1_CONFIG_CHICKEN_HW406785_DISABLE_FIX = 59 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG1_RESERVED = 60 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG1_RESERVED_LEN = 4 ;
+
+static const uint8_t P9N2_PU_NPU_SM1_CONFIG1_COMPRESSED_RSP_ENA = 0 ;
+static const uint8_t P9N2_PU_NPU_SM1_CONFIG1_RESERVED1 = 1 ;
+static const uint8_t P9N2_PU_NPU_SM1_CONFIG1_RESERVED1_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_SM1_CONFIG1_CREQ_AE_ALWAYS = 4 ;
+static const uint8_t P9N2_PU_NPU_SM1_CONFIG1_DGD_AE_ALWAYS = 5 ;
+static const uint8_t P9N2_PU_NPU_SM1_CONFIG1_RSP_AE_ALWAYS = 6 ;
+static const uint8_t P9N2_PU_NPU_SM1_CONFIG1_RESERVED2 = 7 ;
+static const uint8_t P9N2_PU_NPU_SM1_CONFIG1_NTL_RESET = 8 ;
+static const uint8_t P9N2_PU_NPU_SM1_CONFIG1_NTL_RESET_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_SM1_CONFIG1_RESERVED3 = 10 ;
+static const uint8_t P9N2_PU_NPU_SM1_CONFIG1_RESERVED3_LEN = 54 ;
+
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK = 0 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ = 4 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB = 8 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG1_CONFIG_ARB_NONCRR_SAFETY = 12 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG1_CONFIG_ARB_NONCRR_SAFETY_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG1_CONFIG_EPSILON_WLN_COUNT = 16 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG1_CONFIG_EPSILON_WLN_COUNT_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL = 28 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA = 32 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG1_CONFIG_ADDR_EX_MASK_ENA = 36 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG1_CONFIG_ADDR_EX_MASK_ENA_LEN = 7 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG1_CONFIG_PCKT_LONG_CL_DMA_INJ = 43 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG1_CONFIG_PCKT_LONG_PR_DMA_INJ = 44 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG1_CONFIG_PCKT_LONG_MIN_COUNT = 45 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG1_CONFIG_PCKT_LONG_MIN_COUNT_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG1_CONFIG_PCKT_LONG_USES_HANG = 51 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG1_CONFIG_DONT_RETRY_LCO_LONG = 52 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG1_CONFIG_DONT_RETRY_LCO_LONG_STRESSED = 53 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG1_CONFIG_DONT_RETRY_LCO_SHORT = 54 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG1_CONFIG_DONT_RETRY_LCO_SHORT_STRESSED = 55 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG1_CONFIG_STOP_ASB_AT_LN_SCOPE = 56 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG1_CONFIG_STOP_ASB_AT_G_SCOPE = 57 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG1_CONFIG_CHICKEN_DISABLE_HW405632_RELAXED_PROBE = 58 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG1_CONFIG_CHICKEN_HW406785_DISABLE_FIX = 59 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG1_RESERVED = 60 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG1_RESERVED_LEN = 4 ;
+
+static const uint8_t P9N2_NV_CONFIG1_CONFIG_MRBCP_DIV2_COUNT_AT_EXP = 0 ;
+static const uint8_t P9N2_NV_CONFIG1_CONFIG_MRBCP_DIS_DYN_ADJ = 1 ;
+static const uint8_t P9N2_NV_CONFIG1_CONFIG_MRBCP_DIS_DYN_LVL_ADJ = 2 ;
+static const uint8_t P9N2_NV_CONFIG1_CONFIG_MRBCP_THRESH1 = 3 ;
+static const uint8_t P9N2_NV_CONFIG1_CONFIG_MRBCP_THRESH1_LEN = 6 ;
+static const uint8_t P9N2_NV_CONFIG1_CONFIG_MRBCP_THRESH2 = 9 ;
+static const uint8_t P9N2_NV_CONFIG1_CONFIG_MRBCP_THRESH2_LEN = 6 ;
+static const uint8_t P9N2_NV_CONFIG1_CONFIG_MRBCP_MAX_LEVEL = 15 ;
+static const uint8_t P9N2_NV_CONFIG1_CONFIG_MRBCP_MAX_LEVEL_LEN = 4 ;
+static const uint8_t P9N2_NV_CONFIG1_RESERVED1 = 19 ;
+static const uint8_t P9N2_NV_CONFIG1_CONFIG_CTL_FIR_TO_INHIBIT_MASK = 20 ;
+static const uint8_t P9N2_NV_CONFIG1_CONFIG_CTL_FIR_TO_INHIBIT_MASK_LEN = 16 ;
+static const uint8_t P9N2_NV_CONFIG1_CONFIG_BRK0_FENCE_TO_INHIBIT_MASK = 36 ;
+static const uint8_t P9N2_NV_CONFIG1_CONFIG_BRK1_FENCE_TO_INHIBIT_MASK = 37 ;
+static const uint8_t P9N2_NV_CONFIG1_CONFIG_CHICKEN_HW405869_DISABLE_PATCH = 38 ;
+static const uint8_t P9N2_NV_CONFIG1_RESERVED2 = 39 ;
+static const uint8_t P9N2_NV_CONFIG1_RESERVED2_LEN = 25 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG1_CONFIG_ARB_NONCRR_SAFETY = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG1_CONFIG_ARB_NONCRR_SAFETY_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG1_CONFIG_EPSILON_WLN_COUNT = 16 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG1_CONFIG_EPSILON_WLN_COUNT_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL = 28 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG1_CONFIG_ADDR_EX_MASK_ENA = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG1_CONFIG_ADDR_EX_MASK_ENA_LEN = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG1_CONFIG_PCKT_LONG_CL_DMA_INJ = 43 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG1_CONFIG_PCKT_LONG_PR_DMA_INJ = 44 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG1_CONFIG_PCKT_LONG_MIN_COUNT = 45 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG1_CONFIG_PCKT_LONG_MIN_COUNT_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG1_CONFIG_PCKT_LONG_USES_HANG = 51 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG1_CONFIG_DONT_RETRY_LCO_LONG = 52 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG1_CONFIG_DONT_RETRY_LCO_LONG_STRESSED = 53 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG1_CONFIG_DONT_RETRY_LCO_SHORT = 54 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG1_CONFIG_DONT_RETRY_LCO_SHORT_STRESSED = 55 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG1_CONFIG_STOP_ASB_AT_LN_SCOPE = 56 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG1_CONFIG_STOP_ASB_AT_G_SCOPE = 57 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG1_CONFIG_CHICKEN_DISABLE_HW405632_RELAXED_PROBE = 58 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG1_CONFIG_CHICKEN_HW406785_DISABLE_FIX = 59 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG1_RESERVED = 60 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG1_RESERVED_LEN = 4 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG1_CONFIG_ARB_NONCRR_SAFETY = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG1_CONFIG_ARB_NONCRR_SAFETY_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG1_CONFIG_EPSILON_WLN_COUNT = 16 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG1_CONFIG_EPSILON_WLN_COUNT_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL = 28 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG1_CONFIG_ADDR_EX_MASK_ENA = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG1_CONFIG_ADDR_EX_MASK_ENA_LEN = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG1_CONFIG_PCKT_LONG_CL_DMA_INJ = 43 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG1_CONFIG_PCKT_LONG_PR_DMA_INJ = 44 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG1_CONFIG_PCKT_LONG_MIN_COUNT = 45 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG1_CONFIG_PCKT_LONG_MIN_COUNT_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG1_CONFIG_PCKT_LONG_USES_HANG = 51 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG1_CONFIG_DONT_RETRY_LCO_LONG = 52 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG1_CONFIG_DONT_RETRY_LCO_LONG_STRESSED = 53 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG1_CONFIG_DONT_RETRY_LCO_SHORT = 54 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG1_CONFIG_DONT_RETRY_LCO_SHORT_STRESSED = 55 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG1_CONFIG_STOP_ASB_AT_LN_SCOPE = 56 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG1_CONFIG_STOP_ASB_AT_G_SCOPE = 57 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG1_CONFIG_CHICKEN_DISABLE_HW405632_RELAXED_PROBE = 58 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG1_CONFIG_CHICKEN_HW406785_DISABLE_FIX = 59 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG1_RESERVED = 60 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG1_RESERVED_LEN = 4 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CONFIG2_CONFIG_FIR_TO_INHIBIT_MASK = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CONFIG2_CONFIG_FIR_TO_INHIBIT_MASK_LEN = 14 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CONFIG2_CONFIG_BRK0_FENCE_TO_INHIBIT_MASK = 14 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CONFIG2_CONFIG_BRK1_FENCE_TO_INHIBIT_MASK = 15 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CONFIG2_RESERVED = 16 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_CONFIG2_RESERVED_LEN = 48 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_DAT_CONFIG2_CONFIG_FIR_TO_INHIBIT_MASK = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_CONFIG2_CONFIG_FIR_TO_INHIBIT_MASK_LEN = 14 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_CONFIG2_CONFIG_BRK0_FENCE_TO_INHIBIT_MASK = 14 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_CONFIG2_CONFIG_BRK1_FENCE_TO_INHIBIT_MASK = 15 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_CONFIG2_RESERVED = 16 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_CONFIG2_RESERVED_LEN = 48 ;
+
+static const uint8_t P9N2_PU_NPU1_SM1_CONFIG2_BRICK_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CONFIG2_RSP_CTL_CRED_SINGLE_ENA = 1 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CONFIG2_CREQ_BE_128 = 2 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CONFIG2_DGD_BE_128 = 3 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CONFIG2_WR_SPLIT_UT0_ENA = 4 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CONFIG2_WR_SPLIT_UT1_ENA = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CONFIG2_BRICK_DEBUG_MODE = 6 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CONFIG2_P9_TO_P9_MODE = 7 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CONFIG2_RESERVED1 = 8 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CONFIG2_RESERVED1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CONFIG2_CAM256_MAX_CNT = 10 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CONFIG2_CAM256_MAX_CNT_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CONFIG2_NDL_RX_PARITY_ENA = 16 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CONFIG2_NDL_TX_PARITY_ENA = 17 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CONFIG2_NDL_PRI_PARITY_ENA = 18 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CONFIG2_RCV_CREDIT_OVERFLOW_ENA = 19 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CONFIG2_HDR_ARR_ECC_CORR_ENA = 20 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CONFIG2_DAT_ARR_ECC_CORR_ENA = 21 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CONFIG2_TX_DATA_ECC_CORR_ENA = 22 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CONFIG2_RESERVED2 = 23 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CONFIG2_PARITY_ERROR_SUE_ENA = 24 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CONFIG2_DATA_POISON_SUE_ENA = 25 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CONFIG2_HDR_ARR_ECC_SUE_ENA = 26 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CONFIG2_DAT_ARR_ECC_SUE_ENA = 27 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CONFIG2_TX_ECC_DATA_POISON_ENA = 28 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CONFIG2_RESERVED3 = 29 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CONFIG2_RESERVED3_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CONFIG2_PRI_STATE_MACHINE_RESET = 32 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CONFIG2_RESERVED4 = 33 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CONFIG2_RESERVED4_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CONFIG2_CREQ_CTL_CRED_SINGLE_ENA = 36 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CONFIG2_DGD_CTL_CRED_SINGLE_ENA = 37 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CONFIG2_ATSD_CTL_CRED_SINGLE_ENA = 38 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CONFIG2_RESERVED5 = 39 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CONFIG2_RESERVED5_LEN = 25 ;
+
+static const uint8_t P9N2_PU_NPU0_SM2_CONFIG2_CONFIG_FIR_TO_INHIBIT_MASK = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CONFIG2_CONFIG_FIR_TO_INHIBIT_MASK_LEN = 14 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CONFIG2_CONFIG_BRK0_FENCE_TO_INHIBIT_MASK = 14 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CONFIG2_CONFIG_BRK1_FENCE_TO_INHIBIT_MASK = 15 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CONFIG2_RESERVED = 16 ;
+static const uint8_t P9N2_PU_NPU0_SM2_CONFIG2_RESERVED_LEN = 48 ;
+
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG2_CONFIG_FIR_TO_INHIBIT_MASK = 0 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG2_CONFIG_FIR_TO_INHIBIT_MASK_LEN = 14 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG2_CONFIG_BRK0_FENCE_TO_INHIBIT_MASK = 14 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG2_CONFIG_BRK1_FENCE_TO_INHIBIT_MASK = 15 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG2_RESERVED = 16 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG2_RESERVED_LEN = 48 ;
+
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG2_CONFIG_FIR_TO_INHIBIT_MASK = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG2_CONFIG_FIR_TO_INHIBIT_MASK_LEN = 14 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG2_CONFIG_BRK0_FENCE_TO_INHIBIT_MASK = 14 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG2_CONFIG_BRK1_FENCE_TO_INHIBIT_MASK = 15 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG2_RESERVED = 16 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG2_RESERVED_LEN = 48 ;
+
+static const uint8_t P9N2_PU_NPU2_DAT_CONFIG2_CONFIG_FIR_TO_INHIBIT_MASK = 0 ;
+static const uint8_t P9N2_PU_NPU2_DAT_CONFIG2_CONFIG_FIR_TO_INHIBIT_MASK_LEN = 14 ;
+static const uint8_t P9N2_PU_NPU2_DAT_CONFIG2_CONFIG_BRK0_FENCE_TO_INHIBIT_MASK = 14 ;
+static const uint8_t P9N2_PU_NPU2_DAT_CONFIG2_CONFIG_BRK1_FENCE_TO_INHIBIT_MASK = 15 ;
+static const uint8_t P9N2_PU_NPU2_DAT_CONFIG2_RESERVED = 16 ;
+static const uint8_t P9N2_PU_NPU2_DAT_CONFIG2_RESERVED_LEN = 48 ;
+
+static const uint8_t P9N2__SM1_CONFIG2_BRICK_ENABLE = 0 ;
+static const uint8_t P9N2__SM1_CONFIG2_RSP_CTL_CRED_SINGLE_ENA = 1 ;
+static const uint8_t P9N2__SM1_CONFIG2_CREQ_BE_128 = 2 ;
+static const uint8_t P9N2__SM1_CONFIG2_DGD_BE_128 = 3 ;
+static const uint8_t P9N2__SM1_CONFIG2_WR_SPLIT_UT0_ENA = 4 ;
+static const uint8_t P9N2__SM1_CONFIG2_WR_SPLIT_UT1_ENA = 5 ;
+static const uint8_t P9N2__SM1_CONFIG2_BRICK_DEBUG_MODE = 6 ;
+static const uint8_t P9N2__SM1_CONFIG2_P9_TO_P9_MODE = 7 ;
+static const uint8_t P9N2__SM1_CONFIG2_RESERVED1 = 8 ;
+static const uint8_t P9N2__SM1_CONFIG2_RESERVED1_LEN = 2 ;
+static const uint8_t P9N2__SM1_CONFIG2_CAM256_MAX_CNT = 10 ;
+static const uint8_t P9N2__SM1_CONFIG2_CAM256_MAX_CNT_LEN = 6 ;
+static const uint8_t P9N2__SM1_CONFIG2_NDL_RX_PARITY_ENA = 16 ;
+static const uint8_t P9N2__SM1_CONFIG2_NDL_TX_PARITY_ENA = 17 ;
+static const uint8_t P9N2__SM1_CONFIG2_NDL_PRI_PARITY_ENA = 18 ;
+static const uint8_t P9N2__SM1_CONFIG2_RCV_CREDIT_OVERFLOW_ENA = 19 ;
+static const uint8_t P9N2__SM1_CONFIG2_HDR_ARR_ECC_CORR_ENA = 20 ;
+static const uint8_t P9N2__SM1_CONFIG2_DAT_ARR_ECC_CORR_ENA = 21 ;
+static const uint8_t P9N2__SM1_CONFIG2_TX_DATA_ECC_CORR_ENA = 22 ;
+static const uint8_t P9N2__SM1_CONFIG2_RESERVED2 = 23 ;
+static const uint8_t P9N2__SM1_CONFIG2_PARITY_ERROR_SUE_ENA = 24 ;
+static const uint8_t P9N2__SM1_CONFIG2_DATA_POISON_SUE_ENA = 25 ;
+static const uint8_t P9N2__SM1_CONFIG2_HDR_ARR_ECC_SUE_ENA = 26 ;
+static const uint8_t P9N2__SM1_CONFIG2_DAT_ARR_ECC_SUE_ENA = 27 ;
+static const uint8_t P9N2__SM1_CONFIG2_TX_ECC_DATA_POISON_ENA = 28 ;
+static const uint8_t P9N2__SM1_CONFIG2_RESERVED3 = 29 ;
+static const uint8_t P9N2__SM1_CONFIG2_RESERVED3_LEN = 3 ;
+static const uint8_t P9N2__SM1_CONFIG2_PRI_STATE_MACHINE_RESET = 32 ;
+static const uint8_t P9N2__SM1_CONFIG2_RESERVED4 = 33 ;
+static const uint8_t P9N2__SM1_CONFIG2_RESERVED4_LEN = 3 ;
+static const uint8_t P9N2__SM1_CONFIG2_CREQ_CTL_CRED_SINGLE_ENA = 36 ;
+static const uint8_t P9N2__SM1_CONFIG2_DGD_CTL_CRED_SINGLE_ENA = 37 ;
+static const uint8_t P9N2__SM1_CONFIG2_ATSD_CTL_CRED_SINGLE_ENA = 38 ;
+static const uint8_t P9N2__SM1_CONFIG2_RESERVED5 = 39 ;
+static const uint8_t P9N2__SM1_CONFIG2_RESERVED5_LEN = 25 ;
+
+static const uint8_t P9N2_PU_NPU0_DAT_CONFIG2_CONFIG_FIR_TO_INHIBIT_MASK = 0 ;
+static const uint8_t P9N2_PU_NPU0_DAT_CONFIG2_CONFIG_FIR_TO_INHIBIT_MASK_LEN = 14 ;
+static const uint8_t P9N2_PU_NPU0_DAT_CONFIG2_CONFIG_BRK0_FENCE_TO_INHIBIT_MASK = 14 ;
+static const uint8_t P9N2_PU_NPU0_DAT_CONFIG2_CONFIG_BRK1_FENCE_TO_INHIBIT_MASK = 15 ;
+static const uint8_t P9N2_PU_NPU0_DAT_CONFIG2_RESERVED = 16 ;
+static const uint8_t P9N2_PU_NPU0_DAT_CONFIG2_RESERVED_LEN = 48 ;
+
+static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG2_IDIAL = 0 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG2_IDIAL_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU2_SM2_CONFIG2_CONFIG_FIR_TO_INHIBIT_MASK = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CONFIG2_CONFIG_FIR_TO_INHIBIT_MASK_LEN = 14 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CONFIG2_CONFIG_BRK0_FENCE_TO_INHIBIT_MASK = 14 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CONFIG2_CONFIG_BRK1_FENCE_TO_INHIBIT_MASK = 15 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CONFIG2_RESERVED = 16 ;
+static const uint8_t P9N2_PU_NPU2_SM2_CONFIG2_RESERVED_LEN = 48 ;
+
+static const uint8_t P9N2__SM0_CONFIG2_BRICK_ENABLE = 0 ;
+static const uint8_t P9N2__SM0_CONFIG2_RSP_CTL_CRED_SINGLE_ENA = 1 ;
+static const uint8_t P9N2__SM0_CONFIG2_CREQ_BE_128 = 2 ;
+static const uint8_t P9N2__SM0_CONFIG2_DGD_BE_128 = 3 ;
+static const uint8_t P9N2__SM0_CONFIG2_WR_SPLIT_UT0_ENA = 4 ;
+static const uint8_t P9N2__SM0_CONFIG2_WR_SPLIT_UT1_ENA = 5 ;
+static const uint8_t P9N2__SM0_CONFIG2_BRICK_DEBUG_MODE = 6 ;
+static const uint8_t P9N2__SM0_CONFIG2_P9_TO_P9_MODE = 7 ;
+static const uint8_t P9N2__SM0_CONFIG2_RESERVED1 = 8 ;
+static const uint8_t P9N2__SM0_CONFIG2_RESERVED1_LEN = 2 ;
+static const uint8_t P9N2__SM0_CONFIG2_CAM256_MAX_CNT = 10 ;
+static const uint8_t P9N2__SM0_CONFIG2_CAM256_MAX_CNT_LEN = 6 ;
+static const uint8_t P9N2__SM0_CONFIG2_NDL_RX_PARITY_ENA = 16 ;
+static const uint8_t P9N2__SM0_CONFIG2_NDL_TX_PARITY_ENA = 17 ;
+static const uint8_t P9N2__SM0_CONFIG2_NDL_PRI_PARITY_ENA = 18 ;
+static const uint8_t P9N2__SM0_CONFIG2_RCV_CREDIT_OVERFLOW_ENA = 19 ;
+static const uint8_t P9N2__SM0_CONFIG2_HDR_ARR_ECC_CORR_ENA = 20 ;
+static const uint8_t P9N2__SM0_CONFIG2_DAT_ARR_ECC_CORR_ENA = 21 ;
+static const uint8_t P9N2__SM0_CONFIG2_TX_DATA_ECC_CORR_ENA = 22 ;
+static const uint8_t P9N2__SM0_CONFIG2_RESERVED2 = 23 ;
+static const uint8_t P9N2__SM0_CONFIG2_PARITY_ERROR_SUE_ENA = 24 ;
+static const uint8_t P9N2__SM0_CONFIG2_DATA_POISON_SUE_ENA = 25 ;
+static const uint8_t P9N2__SM0_CONFIG2_HDR_ARR_ECC_SUE_ENA = 26 ;
+static const uint8_t P9N2__SM0_CONFIG2_DAT_ARR_ECC_SUE_ENA = 27 ;
+static const uint8_t P9N2__SM0_CONFIG2_TX_ECC_DATA_POISON_ENA = 28 ;
+static const uint8_t P9N2__SM0_CONFIG2_RESERVED3 = 29 ;
+static const uint8_t P9N2__SM0_CONFIG2_RESERVED3_LEN = 3 ;
+static const uint8_t P9N2__SM0_CONFIG2_PRI_STATE_MACHINE_RESET = 32 ;
+static const uint8_t P9N2__SM0_CONFIG2_RESERVED4 = 33 ;
+static const uint8_t P9N2__SM0_CONFIG2_RESERVED4_LEN = 3 ;
+static const uint8_t P9N2__SM0_CONFIG2_CREQ_CTL_CRED_SINGLE_ENA = 36 ;
+static const uint8_t P9N2__SM0_CONFIG2_DGD_CTL_CRED_SINGLE_ENA = 37 ;
+static const uint8_t P9N2__SM0_CONFIG2_ATSD_CTL_CRED_SINGLE_ENA = 38 ;
+static const uint8_t P9N2__SM0_CONFIG2_RESERVED5 = 39 ;
+static const uint8_t P9N2__SM0_CONFIG2_RESERVED5_LEN = 25 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG2_CONFIG_FIR_TO_INHIBIT_MASK = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG2_CONFIG_FIR_TO_INHIBIT_MASK_LEN = 14 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG2_CONFIG_BRK0_FENCE_TO_INHIBIT_MASK = 14 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG2_CONFIG_BRK1_FENCE_TO_INHIBIT_MASK = 15 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG2_RESERVED = 16 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG2_RESERVED_LEN = 48 ;
+
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG2_CONFIG_FIR_TO_INHIBIT_MASK = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG2_CONFIG_FIR_TO_INHIBIT_MASK_LEN = 14 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG2_CONFIG_BRK0_FENCE_TO_INHIBIT_MASK = 14 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG2_CONFIG_BRK1_FENCE_TO_INHIBIT_MASK = 15 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG2_RESERVED = 16 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG2_RESERVED_LEN = 48 ;
+
+static const uint8_t P9N2_PU_NPU_SM0_CONFIG2_BRICK_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NPU_SM0_CONFIG2_RSP_CTL_CRED_SINGLE_ENA = 1 ;
+static const uint8_t P9N2_PU_NPU_SM0_CONFIG2_CREQ_BE_128 = 2 ;
+static const uint8_t P9N2_PU_NPU_SM0_CONFIG2_DGD_BE_128 = 3 ;
+static const uint8_t P9N2_PU_NPU_SM0_CONFIG2_WR_SPLIT_UT0_ENA = 4 ;
+static const uint8_t P9N2_PU_NPU_SM0_CONFIG2_WR_SPLIT_UT1_ENA = 5 ;
+static const uint8_t P9N2_PU_NPU_SM0_CONFIG2_BRICK_DEBUG_MODE = 6 ;
+static const uint8_t P9N2_PU_NPU_SM0_CONFIG2_P9_TO_P9_MODE = 7 ;
+static const uint8_t P9N2_PU_NPU_SM0_CONFIG2_RESERVED1 = 8 ;
+static const uint8_t P9N2_PU_NPU_SM0_CONFIG2_RESERVED1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_SM0_CONFIG2_CAM256_MAX_CNT = 10 ;
+static const uint8_t P9N2_PU_NPU_SM0_CONFIG2_CAM256_MAX_CNT_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_SM0_CONFIG2_NDL_RX_PARITY_ENA = 16 ;
+static const uint8_t P9N2_PU_NPU_SM0_CONFIG2_NDL_TX_PARITY_ENA = 17 ;
+static const uint8_t P9N2_PU_NPU_SM0_CONFIG2_NDL_PRI_PARITY_ENA = 18 ;
+static const uint8_t P9N2_PU_NPU_SM0_CONFIG2_RCV_CREDIT_OVERFLOW_ENA = 19 ;
+static const uint8_t P9N2_PU_NPU_SM0_CONFIG2_HDR_ARR_ECC_CORR_ENA = 20 ;
+static const uint8_t P9N2_PU_NPU_SM0_CONFIG2_DAT_ARR_ECC_CORR_ENA = 21 ;
+static const uint8_t P9N2_PU_NPU_SM0_CONFIG2_TX_DATA_ECC_CORR_ENA = 22 ;
+static const uint8_t P9N2_PU_NPU_SM0_CONFIG2_RESERVED2 = 23 ;
+static const uint8_t P9N2_PU_NPU_SM0_CONFIG2_PARITY_ERROR_SUE_ENA = 24 ;
+static const uint8_t P9N2_PU_NPU_SM0_CONFIG2_DATA_POISON_SUE_ENA = 25 ;
+static const uint8_t P9N2_PU_NPU_SM0_CONFIG2_HDR_ARR_ECC_SUE_ENA = 26 ;
+static const uint8_t P9N2_PU_NPU_SM0_CONFIG2_DAT_ARR_ECC_SUE_ENA = 27 ;
+static const uint8_t P9N2_PU_NPU_SM0_CONFIG2_TX_ECC_DATA_POISON_ENA = 28 ;
+static const uint8_t P9N2_PU_NPU_SM0_CONFIG2_RESERVED3 = 29 ;
+static const uint8_t P9N2_PU_NPU_SM0_CONFIG2_RESERVED3_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_SM0_CONFIG2_PRI_STATE_MACHINE_RESET = 32 ;
+static const uint8_t P9N2_PU_NPU_SM0_CONFIG2_RESERVED4 = 33 ;
+static const uint8_t P9N2_PU_NPU_SM0_CONFIG2_RESERVED4_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_SM0_CONFIG2_CREQ_CTL_CRED_SINGLE_ENA = 36 ;
+static const uint8_t P9N2_PU_NPU_SM0_CONFIG2_DGD_CTL_CRED_SINGLE_ENA = 37 ;
+static const uint8_t P9N2_PU_NPU_SM0_CONFIG2_ATSD_CTL_CRED_SINGLE_ENA = 38 ;
+static const uint8_t P9N2_PU_NPU_SM0_CONFIG2_RESERVED5 = 39 ;
+static const uint8_t P9N2_PU_NPU_SM0_CONFIG2_RESERVED5_LEN = 25 ;
+
+static const uint8_t P9N2_PU_NPU_SM1_CONFIG2_BRICK_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NPU_SM1_CONFIG2_RSP_CTL_CRED_SINGLE_ENA = 1 ;
+static const uint8_t P9N2_PU_NPU_SM1_CONFIG2_CREQ_BE_128 = 2 ;
+static const uint8_t P9N2_PU_NPU_SM1_CONFIG2_DGD_BE_128 = 3 ;
+static const uint8_t P9N2_PU_NPU_SM1_CONFIG2_WR_SPLIT_UT0_ENA = 4 ;
+static const uint8_t P9N2_PU_NPU_SM1_CONFIG2_WR_SPLIT_UT1_ENA = 5 ;
+static const uint8_t P9N2_PU_NPU_SM1_CONFIG2_BRICK_DEBUG_MODE = 6 ;
+static const uint8_t P9N2_PU_NPU_SM1_CONFIG2_P9_TO_P9_MODE = 7 ;
+static const uint8_t P9N2_PU_NPU_SM1_CONFIG2_RESERVED1 = 8 ;
+static const uint8_t P9N2_PU_NPU_SM1_CONFIG2_RESERVED1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_SM1_CONFIG2_CAM256_MAX_CNT = 10 ;
+static const uint8_t P9N2_PU_NPU_SM1_CONFIG2_CAM256_MAX_CNT_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_SM1_CONFIG2_NDL_RX_PARITY_ENA = 16 ;
+static const uint8_t P9N2_PU_NPU_SM1_CONFIG2_NDL_TX_PARITY_ENA = 17 ;
+static const uint8_t P9N2_PU_NPU_SM1_CONFIG2_NDL_PRI_PARITY_ENA = 18 ;
+static const uint8_t P9N2_PU_NPU_SM1_CONFIG2_RCV_CREDIT_OVERFLOW_ENA = 19 ;
+static const uint8_t P9N2_PU_NPU_SM1_CONFIG2_HDR_ARR_ECC_CORR_ENA = 20 ;
+static const uint8_t P9N2_PU_NPU_SM1_CONFIG2_DAT_ARR_ECC_CORR_ENA = 21 ;
+static const uint8_t P9N2_PU_NPU_SM1_CONFIG2_TX_DATA_ECC_CORR_ENA = 22 ;
+static const uint8_t P9N2_PU_NPU_SM1_CONFIG2_RESERVED2 = 23 ;
+static const uint8_t P9N2_PU_NPU_SM1_CONFIG2_PARITY_ERROR_SUE_ENA = 24 ;
+static const uint8_t P9N2_PU_NPU_SM1_CONFIG2_DATA_POISON_SUE_ENA = 25 ;
+static const uint8_t P9N2_PU_NPU_SM1_CONFIG2_HDR_ARR_ECC_SUE_ENA = 26 ;
+static const uint8_t P9N2_PU_NPU_SM1_CONFIG2_DAT_ARR_ECC_SUE_ENA = 27 ;
+static const uint8_t P9N2_PU_NPU_SM1_CONFIG2_TX_ECC_DATA_POISON_ENA = 28 ;
+static const uint8_t P9N2_PU_NPU_SM1_CONFIG2_RESERVED3 = 29 ;
+static const uint8_t P9N2_PU_NPU_SM1_CONFIG2_RESERVED3_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_SM1_CONFIG2_PRI_STATE_MACHINE_RESET = 32 ;
+static const uint8_t P9N2_PU_NPU_SM1_CONFIG2_RESERVED4 = 33 ;
+static const uint8_t P9N2_PU_NPU_SM1_CONFIG2_RESERVED4_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_SM1_CONFIG2_CREQ_CTL_CRED_SINGLE_ENA = 36 ;
+static const uint8_t P9N2_PU_NPU_SM1_CONFIG2_DGD_CTL_CRED_SINGLE_ENA = 37 ;
+static const uint8_t P9N2_PU_NPU_SM1_CONFIG2_ATSD_CTL_CRED_SINGLE_ENA = 38 ;
+static const uint8_t P9N2_PU_NPU_SM1_CONFIG2_RESERVED5 = 39 ;
+static const uint8_t P9N2_PU_NPU_SM1_CONFIG2_RESERVED5_LEN = 25 ;
+
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG2_CONFIG_FIR_TO_INHIBIT_MASK = 0 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG2_CONFIG_FIR_TO_INHIBIT_MASK_LEN = 14 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG2_CONFIG_BRK0_FENCE_TO_INHIBIT_MASK = 14 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG2_CONFIG_BRK1_FENCE_TO_INHIBIT_MASK = 15 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG2_RESERVED = 16 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG2_RESERVED_LEN = 48 ;
+
+static const uint8_t P9N2_NV_CONFIG2_IDIAL = 0 ;
+static const uint8_t P9N2_NV_CONFIG2_IDIAL_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU1_SM0_CONFIG2_BRICK_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CONFIG2_RSP_CTL_CRED_SINGLE_ENA = 1 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CONFIG2_CREQ_BE_128 = 2 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CONFIG2_DGD_BE_128 = 3 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CONFIG2_WR_SPLIT_UT0_ENA = 4 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CONFIG2_WR_SPLIT_UT1_ENA = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CONFIG2_BRICK_DEBUG_MODE = 6 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CONFIG2_P9_TO_P9_MODE = 7 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CONFIG2_RESERVED1 = 8 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CONFIG2_RESERVED1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CONFIG2_CAM256_MAX_CNT = 10 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CONFIG2_CAM256_MAX_CNT_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CONFIG2_NDL_RX_PARITY_ENA = 16 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CONFIG2_NDL_TX_PARITY_ENA = 17 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CONFIG2_NDL_PRI_PARITY_ENA = 18 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CONFIG2_RCV_CREDIT_OVERFLOW_ENA = 19 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CONFIG2_HDR_ARR_ECC_CORR_ENA = 20 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CONFIG2_DAT_ARR_ECC_CORR_ENA = 21 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CONFIG2_TX_DATA_ECC_CORR_ENA = 22 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CONFIG2_RESERVED2 = 23 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CONFIG2_PARITY_ERROR_SUE_ENA = 24 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CONFIG2_DATA_POISON_SUE_ENA = 25 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CONFIG2_HDR_ARR_ECC_SUE_ENA = 26 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CONFIG2_DAT_ARR_ECC_SUE_ENA = 27 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CONFIG2_TX_ECC_DATA_POISON_ENA = 28 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CONFIG2_RESERVED3 = 29 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CONFIG2_RESERVED3_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CONFIG2_PRI_STATE_MACHINE_RESET = 32 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CONFIG2_RESERVED4 = 33 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CONFIG2_RESERVED4_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CONFIG2_CREQ_CTL_CRED_SINGLE_ENA = 36 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CONFIG2_DGD_CTL_CRED_SINGLE_ENA = 37 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CONFIG2_ATSD_CTL_CRED_SINGLE_ENA = 38 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CONFIG2_RESERVED5 = 39 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CONFIG2_RESERVED5_LEN = 25 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG2_CONFIG_FIR_TO_INHIBIT_MASK = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG2_CONFIG_FIR_TO_INHIBIT_MASK_LEN = 14 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG2_CONFIG_BRK0_FENCE_TO_INHIBIT_MASK = 14 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG2_CONFIG_BRK1_FENCE_TO_INHIBIT_MASK = 15 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG2_RESERVED = 16 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG2_RESERVED_LEN = 48 ;
+
+static const uint8_t P9N2_PU_NPU1_SM1_CONFIG3_RESERVED1 = 0 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CONFIG3_RESERVED1_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG3_IDIAL = 0 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CONFIG3_IDIAL_LEN = 64 ;
+
+static const uint8_t P9N2__SM0_CONFIG3_RESERVED1 = 0 ;
+static const uint8_t P9N2__SM0_CONFIG3_RESERVED1_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU_SM0_CONFIG3_RESERVED1 = 0 ;
+static const uint8_t P9N2_PU_NPU_SM0_CONFIG3_RESERVED1_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU_SM1_CONFIG3_RESERVED1 = 0 ;
+static const uint8_t P9N2_PU_NPU_SM1_CONFIG3_RESERVED1_LEN = 64 ;
+
+static const uint8_t P9N2_NV_CONFIG3_IDIAL = 0 ;
+static const uint8_t P9N2_NV_CONFIG3_IDIAL_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU1_SM0_CONFIG3_RESERVED1 = 0 ;
+static const uint8_t P9N2_PU_NPU1_SM0_CONFIG3_RESERVED1_LEN = 64 ;
+
+static const uint8_t P9N2__SM1_CONFIG3_RESERVED1 = 0 ;
+static const uint8_t P9N2__SM1_CONFIG3_RESERVED1_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG_ADDR0_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG_ADDR0_STATUS = 1 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG_ADDR0_STATUS_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG_ADDR0_BUS_NUMBER = 4 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG_ADDR0_BUS_NUMBER_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG_ADDR0_DEVICE_NUMBER = 12 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG_ADDR0_DEVICE_NUMBER_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG_ADDR0_FUNCTION_NUMBER = 17 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG_ADDR0_FUNCTION_NUMBER_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG_ADDR0_REGISTER_NUMBER = 20 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG_ADDR0_REGISTER_NUMBER_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG_ADDR0_TYPE = 32 ;
+
+static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG_ADDR1_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG_ADDR1_STATUS = 1 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG_ADDR1_STATUS_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG_ADDR1_BUS_NUMBER = 4 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG_ADDR1_BUS_NUMBER_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG_ADDR1_DEVICE_NUMBER = 12 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG_ADDR1_DEVICE_NUMBER_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG_ADDR1_FUNCTION_NUMBER = 17 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG_ADDR1_FUNCTION_NUMBER_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG_ADDR1_REGISTER_NUMBER = 20 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG_ADDR1_REGISTER_NUMBER_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG_ADDR1_TYPE = 32 ;
+
+static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG_DATA0_DATA = 0 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG_DATA0_DATA_LEN = 32 ;
+
+static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG_DATA1_DATA = 0 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_CONFIG_DATA1_DATA_LEN = 32 ;
+
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG0_BYTE0 = 0 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG0_BYTE0_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG0_BYTE1 = 5 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG0_BYTE1_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG0_BYTE2 = 10 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG0_BYTE2_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG0_BYTE3 = 15 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG0_BYTE3_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG0_BYTE4 = 20 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG0_BYTE4_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG0_BYTE5 = 25 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG0_BYTE5_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG0_BYTE6 = 30 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG0_BYTE6_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG0_BYTE7 = 35 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG0_BYTE7_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG0_BYTE8 = 40 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG0_BYTE8_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG0_BYTE9 = 45 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG0_BYTE9_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG0_BYTE10 = 50 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG0_BYTE10_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG0_RESERVED = 55 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG0_RESERVED_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG0_DEBUG_ACT = 63 ;
+
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG0_BYTE0 = 0 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG0_BYTE0_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG0_BYTE1 = 5 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG0_BYTE1_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG0_BYTE2 = 10 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG0_BYTE2_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG0_BYTE3 = 15 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG0_BYTE3_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG0_BYTE4 = 20 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG0_BYTE4_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG0_BYTE5 = 25 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG0_BYTE5_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG0_BYTE6 = 30 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG0_BYTE6_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG0_BYTE7 = 35 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG0_BYTE7_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG0_BYTE8 = 40 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG0_BYTE8_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG0_BYTE9 = 45 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG0_BYTE9_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG0_BYTE10 = 50 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG0_BYTE10_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG0_RESERVED = 55 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG0_RESERVED_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG0_DEBUG_ACT = 63 ;
+
+static const uint8_t P9N2__CTL_CONFIG_DEBUG0_BYTE0 = 0 ;
+static const uint8_t P9N2__CTL_CONFIG_DEBUG0_BYTE0_LEN = 5 ;
+static const uint8_t P9N2__CTL_CONFIG_DEBUG0_BYTE1 = 5 ;
+static const uint8_t P9N2__CTL_CONFIG_DEBUG0_BYTE1_LEN = 5 ;
+static const uint8_t P9N2__CTL_CONFIG_DEBUG0_BYTE2 = 10 ;
+static const uint8_t P9N2__CTL_CONFIG_DEBUG0_BYTE2_LEN = 5 ;
+static const uint8_t P9N2__CTL_CONFIG_DEBUG0_BYTE3 = 15 ;
+static const uint8_t P9N2__CTL_CONFIG_DEBUG0_BYTE3_LEN = 5 ;
+static const uint8_t P9N2__CTL_CONFIG_DEBUG0_BYTE4 = 20 ;
+static const uint8_t P9N2__CTL_CONFIG_DEBUG0_BYTE4_LEN = 5 ;
+static const uint8_t P9N2__CTL_CONFIG_DEBUG0_BYTE5 = 25 ;
+static const uint8_t P9N2__CTL_CONFIG_DEBUG0_BYTE5_LEN = 5 ;
+static const uint8_t P9N2__CTL_CONFIG_DEBUG0_BYTE6 = 30 ;
+static const uint8_t P9N2__CTL_CONFIG_DEBUG0_BYTE6_LEN = 5 ;
+static const uint8_t P9N2__CTL_CONFIG_DEBUG0_BYTE7 = 35 ;
+static const uint8_t P9N2__CTL_CONFIG_DEBUG0_BYTE7_LEN = 5 ;
+static const uint8_t P9N2__CTL_CONFIG_DEBUG0_BYTE8 = 40 ;
+static const uint8_t P9N2__CTL_CONFIG_DEBUG0_BYTE8_LEN = 5 ;
+static const uint8_t P9N2__CTL_CONFIG_DEBUG0_BYTE9 = 45 ;
+static const uint8_t P9N2__CTL_CONFIG_DEBUG0_BYTE9_LEN = 5 ;
+static const uint8_t P9N2__CTL_CONFIG_DEBUG0_BYTE10 = 50 ;
+static const uint8_t P9N2__CTL_CONFIG_DEBUG0_BYTE10_LEN = 5 ;
+static const uint8_t P9N2__CTL_CONFIG_DEBUG0_RESERVED = 55 ;
+static const uint8_t P9N2__CTL_CONFIG_DEBUG0_RESERVED_LEN = 8 ;
+static const uint8_t P9N2__CTL_CONFIG_DEBUG0_DEBUG_ACT = 63 ;
+
+static const uint8_t P9N2__SM2_CONFIG_DEBUG0_BYTE0 = 0 ;
+static const uint8_t P9N2__SM2_CONFIG_DEBUG0_BYTE0_LEN = 5 ;
+static const uint8_t P9N2__SM2_CONFIG_DEBUG0_BYTE1 = 5 ;
+static const uint8_t P9N2__SM2_CONFIG_DEBUG0_BYTE1_LEN = 5 ;
+static const uint8_t P9N2__SM2_CONFIG_DEBUG0_BYTE2 = 10 ;
+static const uint8_t P9N2__SM2_CONFIG_DEBUG0_BYTE2_LEN = 5 ;
+static const uint8_t P9N2__SM2_CONFIG_DEBUG0_BYTE3 = 15 ;
+static const uint8_t P9N2__SM2_CONFIG_DEBUG0_BYTE3_LEN = 5 ;
+static const uint8_t P9N2__SM2_CONFIG_DEBUG0_BYTE4 = 20 ;
+static const uint8_t P9N2__SM2_CONFIG_DEBUG0_BYTE4_LEN = 5 ;
+static const uint8_t P9N2__SM2_CONFIG_DEBUG0_BYTE5 = 25 ;
+static const uint8_t P9N2__SM2_CONFIG_DEBUG0_BYTE5_LEN = 5 ;
+static const uint8_t P9N2__SM2_CONFIG_DEBUG0_BYTE6 = 30 ;
+static const uint8_t P9N2__SM2_CONFIG_DEBUG0_BYTE6_LEN = 5 ;
+static const uint8_t P9N2__SM2_CONFIG_DEBUG0_BYTE7 = 35 ;
+static const uint8_t P9N2__SM2_CONFIG_DEBUG0_BYTE7_LEN = 5 ;
+static const uint8_t P9N2__SM2_CONFIG_DEBUG0_BYTE8 = 40 ;
+static const uint8_t P9N2__SM2_CONFIG_DEBUG0_BYTE8_LEN = 5 ;
+static const uint8_t P9N2__SM2_CONFIG_DEBUG0_BYTE9 = 45 ;
+static const uint8_t P9N2__SM2_CONFIG_DEBUG0_BYTE9_LEN = 5 ;
+static const uint8_t P9N2__SM2_CONFIG_DEBUG0_BYTE10 = 50 ;
+static const uint8_t P9N2__SM2_CONFIG_DEBUG0_BYTE10_LEN = 5 ;
+static const uint8_t P9N2__SM2_CONFIG_DEBUG0_RESERVED = 55 ;
+static const uint8_t P9N2__SM2_CONFIG_DEBUG0_RESERVED_LEN = 8 ;
+static const uint8_t P9N2__SM2_CONFIG_DEBUG0_DEBUG_ACT = 63 ;
+
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG1_BYTE0 = 0 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG1_BYTE0_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG1_BYTE1 = 5 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG1_BYTE1_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG1_BYTE2 = 10 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG1_BYTE2_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG1_BYTE3 = 15 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG1_BYTE3_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG1_BYTE4 = 20 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG1_BYTE4_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG1_BYTE5 = 25 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG1_BYTE5_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG1_BYTE6 = 30 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG1_BYTE6_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG1_BYTE7 = 35 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG1_BYTE7_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG1_BYTE8 = 40 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG1_BYTE8_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG1_BYTE9 = 45 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG1_BYTE9_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG1_BYTE10 = 50 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG1_BYTE10_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG1_RESERVED = 55 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_DEBUG1_RESERVED_LEN = 9 ;
+
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG1_BYTE0 = 0 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG1_BYTE0_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG1_BYTE1 = 5 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG1_BYTE1_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG1_BYTE2 = 10 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG1_BYTE2_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG1_BYTE3 = 15 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG1_BYTE3_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG1_BYTE4 = 20 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG1_BYTE4_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG1_BYTE5 = 25 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG1_BYTE5_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG1_BYTE6 = 30 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG1_BYTE6_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG1_BYTE7 = 35 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG1_BYTE7_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG1_BYTE8 = 40 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG1_BYTE8_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG1_BYTE9 = 45 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG1_BYTE9_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG1_BYTE10 = 50 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG1_BYTE10_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG1_RESERVED = 55 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_DEBUG1_RESERVED_LEN = 9 ;
+
+static const uint8_t P9N2__CTL_CONFIG_DEBUG1_BYTE0 = 0 ;
+static const uint8_t P9N2__CTL_CONFIG_DEBUG1_BYTE0_LEN = 5 ;
+static const uint8_t P9N2__CTL_CONFIG_DEBUG1_BYTE1 = 5 ;
+static const uint8_t P9N2__CTL_CONFIG_DEBUG1_BYTE1_LEN = 5 ;
+static const uint8_t P9N2__CTL_CONFIG_DEBUG1_BYTE2 = 10 ;
+static const uint8_t P9N2__CTL_CONFIG_DEBUG1_BYTE2_LEN = 5 ;
+static const uint8_t P9N2__CTL_CONFIG_DEBUG1_BYTE3 = 15 ;
+static const uint8_t P9N2__CTL_CONFIG_DEBUG1_BYTE3_LEN = 5 ;
+static const uint8_t P9N2__CTL_CONFIG_DEBUG1_BYTE4 = 20 ;
+static const uint8_t P9N2__CTL_CONFIG_DEBUG1_BYTE4_LEN = 5 ;
+static const uint8_t P9N2__CTL_CONFIG_DEBUG1_BYTE5 = 25 ;
+static const uint8_t P9N2__CTL_CONFIG_DEBUG1_BYTE5_LEN = 5 ;
+static const uint8_t P9N2__CTL_CONFIG_DEBUG1_BYTE6 = 30 ;
+static const uint8_t P9N2__CTL_CONFIG_DEBUG1_BYTE6_LEN = 5 ;
+static const uint8_t P9N2__CTL_CONFIG_DEBUG1_BYTE7 = 35 ;
+static const uint8_t P9N2__CTL_CONFIG_DEBUG1_BYTE7_LEN = 5 ;
+static const uint8_t P9N2__CTL_CONFIG_DEBUG1_BYTE8 = 40 ;
+static const uint8_t P9N2__CTL_CONFIG_DEBUG1_BYTE8_LEN = 5 ;
+static const uint8_t P9N2__CTL_CONFIG_DEBUG1_BYTE9 = 45 ;
+static const uint8_t P9N2__CTL_CONFIG_DEBUG1_BYTE9_LEN = 5 ;
+static const uint8_t P9N2__CTL_CONFIG_DEBUG1_BYTE10 = 50 ;
+static const uint8_t P9N2__CTL_CONFIG_DEBUG1_BYTE10_LEN = 5 ;
+static const uint8_t P9N2__CTL_CONFIG_DEBUG1_RESERVED = 55 ;
+static const uint8_t P9N2__CTL_CONFIG_DEBUG1_RESERVED_LEN = 9 ;
+
+static const uint8_t P9N2__SM2_CONFIG_DEBUG1_BYTE0 = 0 ;
+static const uint8_t P9N2__SM2_CONFIG_DEBUG1_BYTE0_LEN = 5 ;
+static const uint8_t P9N2__SM2_CONFIG_DEBUG1_BYTE1 = 5 ;
+static const uint8_t P9N2__SM2_CONFIG_DEBUG1_BYTE1_LEN = 5 ;
+static const uint8_t P9N2__SM2_CONFIG_DEBUG1_BYTE2 = 10 ;
+static const uint8_t P9N2__SM2_CONFIG_DEBUG1_BYTE2_LEN = 5 ;
+static const uint8_t P9N2__SM2_CONFIG_DEBUG1_BYTE3 = 15 ;
+static const uint8_t P9N2__SM2_CONFIG_DEBUG1_BYTE3_LEN = 5 ;
+static const uint8_t P9N2__SM2_CONFIG_DEBUG1_BYTE4 = 20 ;
+static const uint8_t P9N2__SM2_CONFIG_DEBUG1_BYTE4_LEN = 5 ;
+static const uint8_t P9N2__SM2_CONFIG_DEBUG1_BYTE5 = 25 ;
+static const uint8_t P9N2__SM2_CONFIG_DEBUG1_BYTE5_LEN = 5 ;
+static const uint8_t P9N2__SM2_CONFIG_DEBUG1_BYTE6 = 30 ;
+static const uint8_t P9N2__SM2_CONFIG_DEBUG1_BYTE6_LEN = 5 ;
+static const uint8_t P9N2__SM2_CONFIG_DEBUG1_BYTE7 = 35 ;
+static const uint8_t P9N2__SM2_CONFIG_DEBUG1_BYTE7_LEN = 5 ;
+static const uint8_t P9N2__SM2_CONFIG_DEBUG1_BYTE8 = 40 ;
+static const uint8_t P9N2__SM2_CONFIG_DEBUG1_BYTE8_LEN = 5 ;
+static const uint8_t P9N2__SM2_CONFIG_DEBUG1_BYTE9 = 45 ;
+static const uint8_t P9N2__SM2_CONFIG_DEBUG1_BYTE9_LEN = 5 ;
+static const uint8_t P9N2__SM2_CONFIG_DEBUG1_BYTE10 = 50 ;
+static const uint8_t P9N2__SM2_CONFIG_DEBUG1_BYTE10_LEN = 5 ;
+static const uint8_t P9N2__SM2_CONFIG_DEBUG1_RESERVED = 55 ;
+static const uint8_t P9N2__SM2_CONFIG_DEBUG1_RESERVED_LEN = 9 ;
+
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_WRENA = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_RDENA = 1 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_AWENA = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_ARENA = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_PECSEL = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_PECSEL_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_GRPCHP = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_GRPCHP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMIN = 10 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMIN_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMAX = 15 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMAX_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMIN = 20 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMIN_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMAX = 26 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMAX_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_WRENA = 32 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_RDENA = 33 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_AWENA = 34 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_ARENA = 35 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_PECSEL = 36 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_PECSEL_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_GRPCHP = 38 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_GRPCHP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMIN = 42 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMIN_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMAX = 47 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMAX_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMIN = 52 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMIN_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMAX = 58 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMAX_LEN = 6 ;
+
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_WRENA = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_RDENA = 1 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_AWENA = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_ARENA = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_PECSEL = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_PECSEL_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_GRPCHP = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_GRPCHP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMIN = 10 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMIN_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMAX = 15 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMAX_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMIN = 20 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMIN_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMAX = 26 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMAX_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_WRENA = 32 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_RDENA = 33 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_AWENA = 34 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_ARENA = 35 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_PECSEL = 36 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_PECSEL_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_GRPCHP = 38 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_GRPCHP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMIN = 42 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMIN_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMAX = 47 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMAX_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMIN = 52 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMIN_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMAX = 58 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMAX_LEN = 6 ;
+
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_WRENA = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_RDENA = 1 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_AWENA = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_ARENA = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_PECSEL = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_PECSEL_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_GRPCHP = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_GRPCHP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMIN = 10 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMIN_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMAX = 15 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMAX_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMIN = 20 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMIN_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMAX = 26 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMAX_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_WRENA = 32 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_RDENA = 33 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_AWENA = 34 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_ARENA = 35 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_PECSEL = 36 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_PECSEL_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_GRPCHP = 38 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_GRPCHP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMIN = 42 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMIN_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMAX = 47 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMAX_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMIN = 52 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMIN_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMAX = 58 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMAX_LEN = 6 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_WRENA = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_RDENA = 1 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_AWENA = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_ARENA = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_PECSEL = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_PECSEL_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_GRPCHP = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_GRPCHP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMIN = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMIN_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMAX = 15 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMAX_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMIN = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMIN_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMAX = 26 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMAX_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_WRENA = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_RDENA = 33 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_AWENA = 34 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_ARENA = 35 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_PECSEL = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_PECSEL_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_GRPCHP = 38 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_GRPCHP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMIN = 42 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMIN_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMAX = 47 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMAX_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMIN = 52 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMIN_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMAX = 58 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMAX_LEN = 6 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_WRENA = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_RDENA = 1 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_AWENA = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_ARENA = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_PECSEL = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_PECSEL_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_GRPCHP = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_GRPCHP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMIN = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMIN_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMAX = 15 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMAX_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMIN = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMIN_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMAX = 26 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMAX_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_WRENA = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_RDENA = 33 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_AWENA = 34 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_ARENA = 35 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_PECSEL = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_PECSEL_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_GRPCHP = 38 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_GRPCHP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMIN = 42 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMIN_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMAX = 47 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMAX_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMIN = 52 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMIN_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMAX = 58 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMAX_LEN = 6 ;
+
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_WRENA = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_RDENA = 1 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_AWENA = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_ARENA = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_PECSEL = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_PECSEL_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_GRPCHP = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_GRPCHP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMIN = 10 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMIN_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMAX = 15 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMAX_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMIN = 20 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMIN_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMAX = 26 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMAX_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_WRENA = 32 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_RDENA = 33 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_AWENA = 34 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_ARENA = 35 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_PECSEL = 36 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_PECSEL_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_GRPCHP = 38 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_GRPCHP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMIN = 42 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMIN_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMAX = 47 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMAX_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMIN = 52 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMIN_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMAX = 58 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMAX_LEN = 6 ;
+
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_WRENA = 0 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_RDENA = 1 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_AWENA = 2 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_ARENA = 3 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_PECSEL = 4 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_PECSEL_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_GRPCHP = 6 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_GRPCHP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMIN = 10 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMIN_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMAX = 15 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMAX_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMIN = 20 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMIN_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMAX = 26 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMAX_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_WRENA = 32 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_RDENA = 33 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_AWENA = 34 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_ARENA = 35 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_PECSEL = 36 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_PECSEL_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_GRPCHP = 38 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_GRPCHP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMIN = 42 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMIN_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMAX = 47 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMAX_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMIN = 52 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMIN_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMAX = 58 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMAX_LEN = 6 ;
+
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_WRENA = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_RDENA = 1 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_AWENA = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_ARENA = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_PECSEL = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_PECSEL_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_GRPCHP = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_GRPCHP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMIN = 10 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMIN_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMAX = 15 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMAX_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMIN = 20 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMIN_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMAX = 26 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMAX_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_WRENA = 32 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_RDENA = 33 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_AWENA = 34 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_ARENA = 35 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_PECSEL = 36 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_PECSEL_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_GRPCHP = 38 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_GRPCHP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMIN = 42 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMIN_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMAX = 47 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMAX_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMIN = 52 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMIN_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMAX = 58 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMAX_LEN = 6 ;
+
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_WRENA = 0 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_RDENA = 1 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_AWENA = 2 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_ARENA = 3 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_PECSEL = 4 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_PECSEL_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_GRPCHP = 6 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_GRPCHP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMIN = 10 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMIN_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMAX = 15 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMAX_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMIN = 20 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMIN_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMAX = 26 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMAX_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_WRENA = 32 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_RDENA = 33 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_AWENA = 34 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_ARENA = 35 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_PECSEL = 36 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_PECSEL_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_GRPCHP = 38 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_GRPCHP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMIN = 42 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMIN_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMAX = 47 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMAX_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMIN = 52 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMIN_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMAX = 58 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMAX_LEN = 6 ;
+
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_WRENA = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_RDENA = 1 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_AWENA = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_ARENA = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_PECSEL = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_PECSEL_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_GRPCHP = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_GRPCHP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMIN = 10 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMIN_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMAX = 15 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMAX_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMIN = 20 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMIN_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMAX = 26 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMAX_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_WRENA = 32 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_RDENA = 33 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_AWENA = 34 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_ARENA = 35 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_PECSEL = 36 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_PECSEL_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_GRPCHP = 38 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_GRPCHP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMIN = 42 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMIN_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMAX = 47 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMAX_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMIN = 52 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMIN_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMAX = 58 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMAX_LEN = 6 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_WRENA = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_RDENA = 1 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_AWENA = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_ARENA = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_PECSEL = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_PECSEL_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_GRPCHP = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_GRPCHP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMIN = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMIN_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMAX = 15 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMAX_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMIN = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMIN_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMAX = 26 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMAX_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_WRENA = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_RDENA = 33 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_AWENA = 34 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_ARENA = 35 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_PECSEL = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_PECSEL_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_GRPCHP = 38 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_GRPCHP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMIN = 42 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMIN_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMAX = 47 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMAX_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMIN = 52 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMIN_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMAX = 58 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMAX_LEN = 6 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_WRENA = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_RDENA = 1 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_AWENA = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_ARENA = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_PECSEL = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_PECSEL_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_GRPCHP = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_GRPCHP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMIN = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMIN_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMAX = 15 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_WRMAX_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMIN = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMIN_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMAX = 26 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_RDMAX_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_WRENA = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_RDENA = 33 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_AWENA = 34 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_ARENA = 35 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_PECSEL = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_PECSEL_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_GRPCHP = 38 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_GRPCHP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMIN = 42 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMIN_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMAX = 47 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_WRMAX_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMIN = 52 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMIN_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMAX = 58 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_RDMAX_LEN = 6 ;
+
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_WRENA = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_RDENA = 1 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_AWENA = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_ARENA = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_PECSEL = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_PECSEL_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_GRPCHP = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_GRPCHP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMIN = 10 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMIN_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMAX = 15 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMAX_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMIN = 20 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMIN_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMAX = 26 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMAX_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_WRENA = 32 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_RDENA = 33 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_AWENA = 34 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_ARENA = 35 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_PECSEL = 36 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_PECSEL_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_GRPCHP = 38 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_GRPCHP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMIN = 42 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMIN_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMAX = 47 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMAX_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMIN = 52 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMIN_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMAX = 58 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMAX_LEN = 6 ;
+
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_WRENA = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_RDENA = 1 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_AWENA = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_ARENA = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_PECSEL = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_PECSEL_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_GRPCHP = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_GRPCHP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMIN = 10 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMIN_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMAX = 15 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMAX_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMIN = 20 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMIN_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMAX = 26 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMAX_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_WRENA = 32 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_RDENA = 33 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_AWENA = 34 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_ARENA = 35 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_PECSEL = 36 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_PECSEL_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_GRPCHP = 38 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_GRPCHP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMIN = 42 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMIN_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMAX = 47 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMAX_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMIN = 52 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMIN_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMAX = 58 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMAX_LEN = 6 ;
+
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_WRENA = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_RDENA = 1 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_AWENA = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_ARENA = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_PECSEL = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_PECSEL_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_GRPCHP = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_GRPCHP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMIN = 10 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMIN_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMAX = 15 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMAX_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMIN = 20 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMIN_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMAX = 26 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMAX_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_WRENA = 32 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_RDENA = 33 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_AWENA = 34 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_ARENA = 35 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_PECSEL = 36 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_PECSEL_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_GRPCHP = 38 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_GRPCHP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMIN = 42 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMIN_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMAX = 47 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMAX_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMIN = 52 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMIN_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMAX = 58 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMAX_LEN = 6 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_WRENA = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_RDENA = 1 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_AWENA = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_ARENA = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_PECSEL = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_PECSEL_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_GRPCHP = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_GRPCHP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMIN = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMIN_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMAX = 15 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMAX_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMIN = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMIN_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMAX = 26 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMAX_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_WRENA = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_RDENA = 33 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_AWENA = 34 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_ARENA = 35 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_PECSEL = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_PECSEL_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_GRPCHP = 38 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_GRPCHP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMIN = 42 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMIN_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMAX = 47 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMAX_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMIN = 52 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMIN_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMAX = 58 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMAX_LEN = 6 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_WRENA = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_RDENA = 1 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_AWENA = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_ARENA = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_PECSEL = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_PECSEL_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_GRPCHP = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_GRPCHP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMIN = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMIN_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMAX = 15 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMAX_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMIN = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMIN_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMAX = 26 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMAX_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_WRENA = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_RDENA = 33 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_AWENA = 34 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_ARENA = 35 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_PECSEL = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_PECSEL_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_GRPCHP = 38 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_GRPCHP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMIN = 42 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMIN_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMAX = 47 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMAX_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMIN = 52 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMIN_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMAX = 58 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMAX_LEN = 6 ;
+
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_WRENA = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_RDENA = 1 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_AWENA = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_ARENA = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_PECSEL = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_PECSEL_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_GRPCHP = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_GRPCHP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMIN = 10 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMIN_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMAX = 15 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMAX_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMIN = 20 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMIN_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMAX = 26 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMAX_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_WRENA = 32 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_RDENA = 33 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_AWENA = 34 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_ARENA = 35 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_PECSEL = 36 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_PECSEL_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_GRPCHP = 38 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_GRPCHP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMIN = 42 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMIN_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMAX = 47 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMAX_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMIN = 52 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMIN_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMAX = 58 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMAX_LEN = 6 ;
+
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_WRENA = 0 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_RDENA = 1 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_AWENA = 2 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_ARENA = 3 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_PECSEL = 4 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_PECSEL_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_GRPCHP = 6 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_GRPCHP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMIN = 10 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMIN_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMAX = 15 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMAX_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMIN = 20 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMIN_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMAX = 26 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMAX_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_WRENA = 32 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_RDENA = 33 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_AWENA = 34 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_ARENA = 35 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_PECSEL = 36 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_PECSEL_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_GRPCHP = 38 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_GRPCHP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMIN = 42 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMIN_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMAX = 47 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMAX_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMIN = 52 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMIN_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMAX = 58 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMAX_LEN = 6 ;
+
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_WRENA = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_RDENA = 1 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_AWENA = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_ARENA = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_PECSEL = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_PECSEL_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_GRPCHP = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_GRPCHP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMIN = 10 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMIN_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMAX = 15 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMAX_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMIN = 20 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMIN_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMAX = 26 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMAX_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_WRENA = 32 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_RDENA = 33 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_AWENA = 34 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_ARENA = 35 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_PECSEL = 36 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_PECSEL_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_GRPCHP = 38 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_GRPCHP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMIN = 42 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMIN_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMAX = 47 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMAX_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMIN = 52 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMIN_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMAX = 58 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMAX_LEN = 6 ;
+
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_WRENA = 0 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_RDENA = 1 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_AWENA = 2 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_ARENA = 3 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_PECSEL = 4 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_PECSEL_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_GRPCHP = 6 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_GRPCHP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMIN = 10 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMIN_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMAX = 15 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMAX_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMIN = 20 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMIN_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMAX = 26 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMAX_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_WRENA = 32 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_RDENA = 33 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_AWENA = 34 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_ARENA = 35 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_PECSEL = 36 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_PECSEL_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_GRPCHP = 38 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_GRPCHP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMIN = 42 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMIN_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMAX = 47 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMAX_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMIN = 52 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMIN_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMAX = 58 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMAX_LEN = 6 ;
+
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_WRENA = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_RDENA = 1 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_AWENA = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_ARENA = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_PECSEL = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_PECSEL_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_GRPCHP = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_GRPCHP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMIN = 10 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMIN_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMAX = 15 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMAX_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMIN = 20 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMIN_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMAX = 26 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMAX_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_WRENA = 32 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_RDENA = 33 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_AWENA = 34 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_ARENA = 35 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_PECSEL = 36 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_PECSEL_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_GRPCHP = 38 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_GRPCHP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMIN = 42 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMIN_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMAX = 47 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMAX_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMIN = 52 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMIN_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMAX = 58 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMAX_LEN = 6 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_WRENA = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_RDENA = 1 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_AWENA = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_ARENA = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_PECSEL = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_PECSEL_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_GRPCHP = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_GRPCHP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMIN = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMIN_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMAX = 15 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMAX_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMIN = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMIN_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMAX = 26 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMAX_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_WRENA = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_RDENA = 33 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_AWENA = 34 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_ARENA = 35 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_PECSEL = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_PECSEL_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_GRPCHP = 38 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_GRPCHP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMIN = 42 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMIN_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMAX = 47 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMAX_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMIN = 52 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMIN_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMAX = 58 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMAX_LEN = 6 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_WRENA = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_RDENA = 1 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_AWENA = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_ARENA = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_PECSEL = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_PECSEL_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_GRPCHP = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_GRPCHP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMIN = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMIN_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMAX = 15 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_WRMAX_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMIN = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMIN_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMAX = 26 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_RDMAX_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_WRENA = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_RDENA = 33 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_AWENA = 34 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_ARENA = 35 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_PECSEL = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_PECSEL_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_GRPCHP = 38 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_GRPCHP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMIN = 42 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMIN_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMAX = 47 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_WRMAX_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMIN = 52 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMIN_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMAX = 58 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED1_RELAXED_SOURCE3_RDMAX_LEN = 6 ;
+
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W_HP = 1 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_INJ = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_PR_DMA_INJ = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_DMA_PR_W = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_CL_RD_NC_F0 = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_U = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_S = 7 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_U = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_S = 9 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_ADD = 10 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_AND = 11 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_OR = 12 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_XOR = 13 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_U = 14 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_S = 15 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_U = 16 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_S = 17 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_ADD = 18 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_AND = 19 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_OR = 20 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_XOR = 21 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_E = 22 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_U = 23 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_RESERVED1 = 24 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_RESERVED1_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_SOURCE4_WRENA = 28 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_SOURCE4_RDENA = 29 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_SOURCE4_AWENA = 30 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_SOURCE4_ARENA = 31 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_SOURCE5_WRENA = 32 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_SOURCE5_RDENA = 33 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_SOURCE5_AWENA = 34 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_SOURCE5_ARENA = 35 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_SOURCE6_WRENA = 36 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_SOURCE6_RDENA = 37 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_SOURCE6_AWENA = 38 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_SOURCE6_ARENA = 39 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_SOURCE7_WRENA = 40 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_SOURCE7_RDENA = 41 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_SOURCE7_AWENA = 42 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_SOURCE7_ARENA = 43 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_SOURCE8_WRENA = 44 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_SOURCE8_RDENA = 45 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_SOURCE8_AWENA = 46 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_SOURCE8_ARENA = 47 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_RESERVED2 = 48 ;
+static const uint8_t P9N2_PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_RESERVED2_LEN = 4 ;
+
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W_HP = 1 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_INJ = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_PR_DMA_INJ = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_DMA_PR_W = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_CL_RD_NC_F0 = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_U = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_S = 7 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_U = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_S = 9 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_ADD = 10 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_AND = 11 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_OR = 12 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_XOR = 13 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_U = 14 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_S = 15 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_U = 16 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_S = 17 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_ADD = 18 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_AND = 19 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_OR = 20 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_XOR = 21 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_E = 22 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_U = 23 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_RESERVED1 = 24 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_RESERVED1_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_SOURCE4_WRENA = 28 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_SOURCE4_RDENA = 29 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_SOURCE4_AWENA = 30 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_SOURCE4_ARENA = 31 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_SOURCE5_WRENA = 32 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_SOURCE5_RDENA = 33 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_SOURCE5_AWENA = 34 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_SOURCE5_ARENA = 35 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_SOURCE6_WRENA = 36 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_SOURCE6_RDENA = 37 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_SOURCE6_AWENA = 38 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_SOURCE6_ARENA = 39 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_SOURCE7_WRENA = 40 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_SOURCE7_RDENA = 41 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_SOURCE7_AWENA = 42 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_SOURCE7_ARENA = 43 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_SOURCE8_WRENA = 44 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_SOURCE8_RDENA = 45 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_SOURCE8_AWENA = 46 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_SOURCE8_ARENA = 47 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_RESERVED2 = 48 ;
+static const uint8_t P9N2_PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_RESERVED2_LEN = 4 ;
+
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W_HP = 1 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_INJ = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_PR_DMA_INJ = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_DMA_PR_W = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_CL_RD_NC_F0 = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_U = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_S = 7 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_U = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_S = 9 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_ADD = 10 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_AND = 11 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_OR = 12 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_XOR = 13 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_U = 14 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_S = 15 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_U = 16 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_S = 17 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_ADD = 18 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_AND = 19 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_OR = 20 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_XOR = 21 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_E = 22 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_U = 23 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_RESERVED1 = 24 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_RESERVED1_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_SOURCE4_WRENA = 28 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_SOURCE4_RDENA = 29 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_SOURCE4_AWENA = 30 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_SOURCE4_ARENA = 31 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_SOURCE5_WRENA = 32 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_SOURCE5_RDENA = 33 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_SOURCE5_AWENA = 34 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_SOURCE5_ARENA = 35 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_SOURCE6_WRENA = 36 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_SOURCE6_RDENA = 37 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_SOURCE6_AWENA = 38 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_SOURCE6_ARENA = 39 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_SOURCE7_WRENA = 40 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_SOURCE7_RDENA = 41 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_SOURCE7_AWENA = 42 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_SOURCE7_ARENA = 43 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_SOURCE8_WRENA = 44 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_SOURCE8_RDENA = 45 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_SOURCE8_AWENA = 46 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_SOURCE8_ARENA = 47 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_RESERVED2 = 48 ;
+static const uint8_t P9N2_PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_RESERVED2_LEN = 4 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W_HP = 1 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_INJ = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_CMD_PR_DMA_INJ = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_CMD_DMA_PR_W = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_CMD_CL_RD_NC_F0 = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_U = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_S = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_U = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_S = 9 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_ADD = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_AND = 11 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_OR = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_XOR = 13 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_U = 14 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_S = 15 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_U = 16 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_S = 17 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_ADD = 18 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_AND = 19 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_OR = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_XOR = 21 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_E = 22 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_U = 23 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_RESERVED1 = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_RESERVED1_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_SOURCE4_WRENA = 28 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_SOURCE4_RDENA = 29 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_SOURCE4_AWENA = 30 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_SOURCE4_ARENA = 31 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_SOURCE5_WRENA = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_SOURCE5_RDENA = 33 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_SOURCE5_AWENA = 34 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_SOURCE5_ARENA = 35 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_SOURCE6_WRENA = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_SOURCE6_RDENA = 37 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_SOURCE6_AWENA = 38 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_SOURCE6_ARENA = 39 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_SOURCE7_WRENA = 40 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_SOURCE7_RDENA = 41 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_SOURCE7_AWENA = 42 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_SOURCE7_ARENA = 43 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_SOURCE8_WRENA = 44 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_SOURCE8_RDENA = 45 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_SOURCE8_AWENA = 46 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_SOURCE8_ARENA = 47 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_RESERVED2 = 48 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_CONFIG_RELAXED2_RELAXED_RESERVED2_LEN = 4 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W_HP = 1 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_INJ = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_CMD_PR_DMA_INJ = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_CMD_DMA_PR_W = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_CMD_CL_RD_NC_F0 = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_U = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_S = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_U = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_S = 9 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_ADD = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_AND = 11 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_OR = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_XOR = 13 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_U = 14 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_S = 15 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_U = 16 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_S = 17 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_ADD = 18 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_AND = 19 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_OR = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_XOR = 21 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_E = 22 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_U = 23 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_RESERVED1 = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_RESERVED1_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_SOURCE4_WRENA = 28 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_SOURCE4_RDENA = 29 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_SOURCE4_AWENA = 30 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_SOURCE4_ARENA = 31 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_SOURCE5_WRENA = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_SOURCE5_RDENA = 33 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_SOURCE5_AWENA = 34 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_SOURCE5_ARENA = 35 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_SOURCE6_WRENA = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_SOURCE6_RDENA = 37 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_SOURCE6_AWENA = 38 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_SOURCE6_ARENA = 39 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_SOURCE7_WRENA = 40 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_SOURCE7_RDENA = 41 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_SOURCE7_AWENA = 42 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_SOURCE7_ARENA = 43 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_SOURCE8_WRENA = 44 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_SOURCE8_RDENA = 45 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_SOURCE8_AWENA = 46 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_SOURCE8_ARENA = 47 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_RESERVED2 = 48 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_CONFIG_RELAXED2_RELAXED_RESERVED2_LEN = 4 ;
+
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W_HP = 1 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_INJ = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_PR_DMA_INJ = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_DMA_PR_W = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_CL_RD_NC_F0 = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_U = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_S = 7 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_U = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_S = 9 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_ADD = 10 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_AND = 11 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_OR = 12 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_XOR = 13 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_U = 14 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_S = 15 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_U = 16 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_S = 17 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_ADD = 18 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_AND = 19 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_OR = 20 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_XOR = 21 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_E = 22 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_U = 23 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_RESERVED1 = 24 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_RESERVED1_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_SOURCE4_WRENA = 28 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_SOURCE4_RDENA = 29 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_SOURCE4_AWENA = 30 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_SOURCE4_ARENA = 31 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_SOURCE5_WRENA = 32 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_SOURCE5_RDENA = 33 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_SOURCE5_AWENA = 34 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_SOURCE5_ARENA = 35 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_SOURCE6_WRENA = 36 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_SOURCE6_RDENA = 37 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_SOURCE6_AWENA = 38 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_SOURCE6_ARENA = 39 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_SOURCE7_WRENA = 40 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_SOURCE7_RDENA = 41 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_SOURCE7_AWENA = 42 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_SOURCE7_ARENA = 43 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_SOURCE8_WRENA = 44 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_SOURCE8_RDENA = 45 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_SOURCE8_AWENA = 46 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_SOURCE8_ARENA = 47 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_RESERVED2 = 48 ;
+static const uint8_t P9N2_PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_RESERVED2_LEN = 4 ;
+
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W = 0 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W_HP = 1 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_INJ = 2 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_CMD_PR_DMA_INJ = 3 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_CMD_DMA_PR_W = 4 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_CMD_CL_RD_NC_F0 = 5 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_U = 6 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_S = 7 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_U = 8 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_S = 9 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMW_ADD = 10 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMW_AND = 11 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMW_OR = 12 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMW_XOR = 13 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_U = 14 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_S = 15 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_U = 16 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_S = 17 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_ADD = 18 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_AND = 19 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_OR = 20 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_XOR = 21 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_E = 22 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_U = 23 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_RESERVED1 = 24 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_RESERVED1_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_SOURCE4_WRENA = 28 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_SOURCE4_RDENA = 29 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_SOURCE4_AWENA = 30 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_SOURCE4_ARENA = 31 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_SOURCE5_WRENA = 32 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_SOURCE5_RDENA = 33 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_SOURCE5_AWENA = 34 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_SOURCE5_ARENA = 35 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_SOURCE6_WRENA = 36 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_SOURCE6_RDENA = 37 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_SOURCE6_AWENA = 38 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_SOURCE6_ARENA = 39 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_SOURCE7_WRENA = 40 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_SOURCE7_RDENA = 41 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_SOURCE7_AWENA = 42 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_SOURCE7_ARENA = 43 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_SOURCE8_WRENA = 44 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_SOURCE8_RDENA = 45 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_SOURCE8_AWENA = 46 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_SOURCE8_ARENA = 47 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_RESERVED2 = 48 ;
+static const uint8_t P9N2_PU_NPU0_CTL_CONFIG_RELAXED2_RELAXED_RESERVED2_LEN = 4 ;
+
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W_HP = 1 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_INJ = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_PR_DMA_INJ = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_DMA_PR_W = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_CL_RD_NC_F0 = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_U = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_S = 7 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_U = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_S = 9 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_ADD = 10 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_AND = 11 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_OR = 12 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_XOR = 13 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_U = 14 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_S = 15 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_U = 16 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_S = 17 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_ADD = 18 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_AND = 19 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_OR = 20 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_XOR = 21 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_E = 22 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_U = 23 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_RESERVED1 = 24 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_RESERVED1_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_SOURCE4_WRENA = 28 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_SOURCE4_RDENA = 29 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_SOURCE4_AWENA = 30 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_SOURCE4_ARENA = 31 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_SOURCE5_WRENA = 32 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_SOURCE5_RDENA = 33 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_SOURCE5_AWENA = 34 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_SOURCE5_ARENA = 35 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_SOURCE6_WRENA = 36 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_SOURCE6_RDENA = 37 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_SOURCE6_AWENA = 38 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_SOURCE6_ARENA = 39 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_SOURCE7_WRENA = 40 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_SOURCE7_RDENA = 41 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_SOURCE7_AWENA = 42 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_SOURCE7_ARENA = 43 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_SOURCE8_WRENA = 44 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_SOURCE8_RDENA = 45 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_SOURCE8_AWENA = 46 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_SOURCE8_ARENA = 47 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_RESERVED2 = 48 ;
+static const uint8_t P9N2_PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_RESERVED2_LEN = 4 ;
+
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W = 0 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W_HP = 1 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_INJ = 2 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_CMD_PR_DMA_INJ = 3 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_CMD_DMA_PR_W = 4 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_CMD_CL_RD_NC_F0 = 5 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_U = 6 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_S = 7 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_U = 8 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_S = 9 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMW_ADD = 10 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMW_AND = 11 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMW_OR = 12 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMW_XOR = 13 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_U = 14 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_S = 15 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_U = 16 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_S = 17 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_ADD = 18 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_AND = 19 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_OR = 20 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_XOR = 21 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_E = 22 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_U = 23 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_RESERVED1 = 24 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_RESERVED1_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_SOURCE4_WRENA = 28 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_SOURCE4_RDENA = 29 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_SOURCE4_AWENA = 30 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_SOURCE4_ARENA = 31 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_SOURCE5_WRENA = 32 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_SOURCE5_RDENA = 33 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_SOURCE5_AWENA = 34 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_SOURCE5_ARENA = 35 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_SOURCE6_WRENA = 36 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_SOURCE6_RDENA = 37 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_SOURCE6_AWENA = 38 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_SOURCE6_ARENA = 39 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_SOURCE7_WRENA = 40 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_SOURCE7_RDENA = 41 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_SOURCE7_AWENA = 42 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_SOURCE7_ARENA = 43 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_SOURCE8_WRENA = 44 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_SOURCE8_RDENA = 45 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_SOURCE8_AWENA = 46 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_SOURCE8_ARENA = 47 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_RESERVED2 = 48 ;
+static const uint8_t P9N2_PU_NPU2_CTL_CONFIG_RELAXED2_RELAXED_RESERVED2_LEN = 4 ;
+
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W_HP = 1 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_INJ = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_PR_DMA_INJ = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_DMA_PR_W = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_CL_RD_NC_F0 = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_U = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_S = 7 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_U = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_S = 9 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_ADD = 10 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_AND = 11 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_OR = 12 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_XOR = 13 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_U = 14 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_S = 15 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_U = 16 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_S = 17 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_ADD = 18 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_AND = 19 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_OR = 20 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_XOR = 21 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_E = 22 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_U = 23 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_RESERVED1 = 24 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_RESERVED1_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_SOURCE4_WRENA = 28 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_SOURCE4_RDENA = 29 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_SOURCE4_AWENA = 30 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_SOURCE4_ARENA = 31 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_SOURCE5_WRENA = 32 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_SOURCE5_RDENA = 33 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_SOURCE5_AWENA = 34 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_SOURCE5_ARENA = 35 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_SOURCE6_WRENA = 36 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_SOURCE6_RDENA = 37 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_SOURCE6_AWENA = 38 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_SOURCE6_ARENA = 39 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_SOURCE7_WRENA = 40 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_SOURCE7_RDENA = 41 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_SOURCE7_AWENA = 42 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_SOURCE7_ARENA = 43 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_SOURCE8_WRENA = 44 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_SOURCE8_RDENA = 45 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_SOURCE8_AWENA = 46 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_SOURCE8_ARENA = 47 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_RESERVED2 = 48 ;
+static const uint8_t P9N2_PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_RESERVED2_LEN = 4 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W_HP = 1 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_INJ = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_CMD_PR_DMA_INJ = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_CMD_DMA_PR_W = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_CMD_CL_RD_NC_F0 = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_U = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_S = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_U = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_S = 9 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMW_ADD = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMW_AND = 11 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMW_OR = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMW_XOR = 13 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_U = 14 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_S = 15 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_U = 16 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_S = 17 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_ADD = 18 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_AND = 19 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_OR = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_XOR = 21 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_E = 22 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_U = 23 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_RESERVED1 = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_RESERVED1_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_SOURCE4_WRENA = 28 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_SOURCE4_RDENA = 29 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_SOURCE4_AWENA = 30 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_SOURCE4_ARENA = 31 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_SOURCE5_WRENA = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_SOURCE5_RDENA = 33 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_SOURCE5_AWENA = 34 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_SOURCE5_ARENA = 35 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_SOURCE6_WRENA = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_SOURCE6_RDENA = 37 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_SOURCE6_AWENA = 38 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_SOURCE6_ARENA = 39 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_SOURCE7_WRENA = 40 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_SOURCE7_RDENA = 41 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_SOURCE7_AWENA = 42 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_SOURCE7_ARENA = 43 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_SOURCE8_WRENA = 44 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_SOURCE8_RDENA = 45 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_SOURCE8_AWENA = 46 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_SOURCE8_ARENA = 47 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_RESERVED2 = 48 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_CONFIG_RELAXED2_RELAXED_RESERVED2_LEN = 4 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W_HP = 1 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_INJ = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_CMD_PR_DMA_INJ = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_CMD_DMA_PR_W = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_CMD_CL_RD_NC_F0 = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_U = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_S = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_U = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_S = 9 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_ADD = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_AND = 11 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_OR = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_XOR = 13 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_U = 14 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_S = 15 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_U = 16 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_S = 17 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_ADD = 18 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_AND = 19 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_OR = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_XOR = 21 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_E = 22 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_U = 23 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_RESERVED1 = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_RESERVED1_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_SOURCE4_WRENA = 28 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_SOURCE4_RDENA = 29 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_SOURCE4_AWENA = 30 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_SOURCE4_ARENA = 31 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_SOURCE5_WRENA = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_SOURCE5_RDENA = 33 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_SOURCE5_AWENA = 34 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_SOURCE5_ARENA = 35 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_SOURCE6_WRENA = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_SOURCE6_RDENA = 37 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_SOURCE6_AWENA = 38 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_SOURCE6_ARENA = 39 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_SOURCE7_WRENA = 40 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_SOURCE7_RDENA = 41 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_SOURCE7_AWENA = 42 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_SOURCE7_ARENA = 43 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_SOURCE8_WRENA = 44 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_SOURCE8_RDENA = 45 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_SOURCE8_AWENA = 46 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_SOURCE8_ARENA = 47 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_RESERVED2 = 48 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_CONFIG_RELAXED2_RELAXED_RESERVED2_LEN = 4 ;
+
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TLX_CREDITS_VC0 = 0 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TLX_CREDITS_VC0_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TLX_CREDITS_VC1 = 8 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TLX_CREDITS_VC1_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TLX_CREDITS_VC2 = 16 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TLX_CREDITS_VC2_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TLX_CREDITS_VC3 = 24 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TLX_CREDITS_VC3_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TLX_CREDITS_DCP0 = 32 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TLX_CREDITS_DCP0_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TLX_CREDITS_SPARE = 40 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TLX_CREDITS_SPARE_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TLX_CREDITS_DCP2 = 48 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TLX_CREDITS_DCP2_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TLX_CREDITS_DCP3 = 56 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TLX_CREDITS_DCP3_LEN = 8 ;
+
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TLX_CREDITS_VC0 = 0 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TLX_CREDITS_VC0_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TLX_CREDITS_VC1 = 8 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TLX_CREDITS_VC1_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TLX_CREDITS_VC2 = 16 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TLX_CREDITS_VC2_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TLX_CREDITS_VC3 = 24 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TLX_CREDITS_VC3_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TLX_CREDITS_DCP0 = 32 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TLX_CREDITS_DCP0_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TLX_CREDITS_SPARE = 40 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TLX_CREDITS_SPARE_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TLX_CREDITS_DCP2 = 48 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TLX_CREDITS_DCP2_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TLX_CREDITS_DCP3 = 56 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TLX_CREDITS_DCP3_LEN = 8 ;
+
+static const uint8_t P9N2__CTL_CONFIG_TLX_CREDITS_VC0 = 0 ;
+static const uint8_t P9N2__CTL_CONFIG_TLX_CREDITS_VC0_LEN = 8 ;
+static const uint8_t P9N2__CTL_CONFIG_TLX_CREDITS_VC1 = 8 ;
+static const uint8_t P9N2__CTL_CONFIG_TLX_CREDITS_VC1_LEN = 8 ;
+static const uint8_t P9N2__CTL_CONFIG_TLX_CREDITS_VC2 = 16 ;
+static const uint8_t P9N2__CTL_CONFIG_TLX_CREDITS_VC2_LEN = 8 ;
+static const uint8_t P9N2__CTL_CONFIG_TLX_CREDITS_VC3 = 24 ;
+static const uint8_t P9N2__CTL_CONFIG_TLX_CREDITS_VC3_LEN = 8 ;
+static const uint8_t P9N2__CTL_CONFIG_TLX_CREDITS_DCP0 = 32 ;
+static const uint8_t P9N2__CTL_CONFIG_TLX_CREDITS_DCP0_LEN = 8 ;
+static const uint8_t P9N2__CTL_CONFIG_TLX_CREDITS_SPARE = 40 ;
+static const uint8_t P9N2__CTL_CONFIG_TLX_CREDITS_SPARE_LEN = 8 ;
+static const uint8_t P9N2__CTL_CONFIG_TLX_CREDITS_DCP2 = 48 ;
+static const uint8_t P9N2__CTL_CONFIG_TLX_CREDITS_DCP2_LEN = 8 ;
+static const uint8_t P9N2__CTL_CONFIG_TLX_CREDITS_DCP3 = 56 ;
+static const uint8_t P9N2__CTL_CONFIG_TLX_CREDITS_DCP3_LEN = 8 ;
+
+static const uint8_t P9N2__SM2_CONFIG_TLX_CREDITS_VC0 = 0 ;
+static const uint8_t P9N2__SM2_CONFIG_TLX_CREDITS_VC0_LEN = 8 ;
+static const uint8_t P9N2__SM2_CONFIG_TLX_CREDITS_VC1 = 8 ;
+static const uint8_t P9N2__SM2_CONFIG_TLX_CREDITS_VC1_LEN = 8 ;
+static const uint8_t P9N2__SM2_CONFIG_TLX_CREDITS_VC2 = 16 ;
+static const uint8_t P9N2__SM2_CONFIG_TLX_CREDITS_VC2_LEN = 8 ;
+static const uint8_t P9N2__SM2_CONFIG_TLX_CREDITS_VC3 = 24 ;
+static const uint8_t P9N2__SM2_CONFIG_TLX_CREDITS_VC3_LEN = 8 ;
+static const uint8_t P9N2__SM2_CONFIG_TLX_CREDITS_DCP0 = 32 ;
+static const uint8_t P9N2__SM2_CONFIG_TLX_CREDITS_DCP0_LEN = 8 ;
+static const uint8_t P9N2__SM2_CONFIG_TLX_CREDITS_SPARE = 40 ;
+static const uint8_t P9N2__SM2_CONFIG_TLX_CREDITS_SPARE_LEN = 8 ;
+static const uint8_t P9N2__SM2_CONFIG_TLX_CREDITS_DCP2 = 48 ;
+static const uint8_t P9N2__SM2_CONFIG_TLX_CREDITS_DCP2_LEN = 8 ;
+static const uint8_t P9N2__SM2_CONFIG_TLX_CREDITS_DCP3 = 56 ;
+static const uint8_t P9N2__SM2_CONFIG_TLX_CREDITS_DCP3_LEN = 8 ;
+
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TX_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TX_TEMP1_EN = 1 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TX_TEMP2_EN = 2 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TX_TEMP3_EN = 3 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TX_SPARE1 = 4 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TX_DRDY_WAIT = 5 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TX_DRDY_WAIT_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TX_TEMP0_RATE = 8 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TX_TEMP0_RATE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TX_TEMP1_RATE = 12 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TX_TEMP1_RATE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TX_TEMP2_RATE = 16 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TX_TEMP2_RATE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TX_TEMP3_RATE = 20 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TX_TEMP3_RATE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TX_SPARE2 = 24 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TX_SPARE2_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TX_CRET_FREQ = 32 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TX_CRET_FREQ_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TX_AGE_FREQ = 35 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TX_AGE_FREQ_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TX_RS2_HPWAIT = 40 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TX_RS2_HPWAIT_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TX_RQ4_HPWAIT = 46 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TX_RQ4_HPWAIT_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TX_RQ6_HPWAIT = 52 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TX_RQ6_HPWAIT_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TX_CBUF_ECC_DIS = 58 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TX_STOP_LINK = 59 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TX_STOP_ON_UE = 60 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TX_T0_MASK_CRTN0 = 61 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TX_T123_MASK_CRTN0 = 62 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TX_SPARE3 = 63 ;
+
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TX_SPARE0 = 0 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TX_TEMP1_EN = 1 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TX_TEMP2_EN = 2 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TX_TEMP3_EN = 3 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TX_SPARE1 = 4 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TX_DRDY_WAIT = 5 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TX_DRDY_WAIT_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TX_TEMP0_RATE = 8 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TX_TEMP0_RATE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TX_TEMP1_RATE = 12 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TX_TEMP1_RATE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TX_TEMP2_RATE = 16 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TX_TEMP2_RATE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TX_TEMP3_RATE = 20 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TX_TEMP3_RATE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TX_SPARE2 = 24 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TX_SPARE2_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TX_CRET_FREQ = 32 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TX_CRET_FREQ_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TX_AGE_FREQ = 35 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TX_AGE_FREQ_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TX_RS2_HPWAIT = 40 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TX_RS2_HPWAIT_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TX_RQ4_HPWAIT = 46 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TX_RQ4_HPWAIT_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TX_RQ6_HPWAIT = 52 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TX_RQ6_HPWAIT_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TX_CBUF_ECC_DIS = 58 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TX_STOP_LINK = 59 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TX_STOP_ON_UE = 60 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TX_T0_MASK_CRTN0 = 61 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TX_T123_MASK_CRTN0 = 62 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TX_SPARE3 = 63 ;
+
+static const uint8_t P9N2__CTL_CONFIG_TX_SPARE0 = 0 ;
+static const uint8_t P9N2__CTL_CONFIG_TX_TEMP1_EN = 1 ;
+static const uint8_t P9N2__CTL_CONFIG_TX_TEMP2_EN = 2 ;
+static const uint8_t P9N2__CTL_CONFIG_TX_TEMP3_EN = 3 ;
+static const uint8_t P9N2__CTL_CONFIG_TX_SPARE1 = 4 ;
+static const uint8_t P9N2__CTL_CONFIG_TX_DRDY_WAIT = 5 ;
+static const uint8_t P9N2__CTL_CONFIG_TX_DRDY_WAIT_LEN = 3 ;
+static const uint8_t P9N2__CTL_CONFIG_TX_TEMP0_RATE = 8 ;
+static const uint8_t P9N2__CTL_CONFIG_TX_TEMP0_RATE_LEN = 4 ;
+static const uint8_t P9N2__CTL_CONFIG_TX_TEMP1_RATE = 12 ;
+static const uint8_t P9N2__CTL_CONFIG_TX_TEMP1_RATE_LEN = 4 ;
+static const uint8_t P9N2__CTL_CONFIG_TX_TEMP2_RATE = 16 ;
+static const uint8_t P9N2__CTL_CONFIG_TX_TEMP2_RATE_LEN = 4 ;
+static const uint8_t P9N2__CTL_CONFIG_TX_TEMP3_RATE = 20 ;
+static const uint8_t P9N2__CTL_CONFIG_TX_TEMP3_RATE_LEN = 4 ;
+static const uint8_t P9N2__CTL_CONFIG_TX_SPARE2 = 24 ;
+static const uint8_t P9N2__CTL_CONFIG_TX_SPARE2_LEN = 8 ;
+static const uint8_t P9N2__CTL_CONFIG_TX_CRET_FREQ = 32 ;
+static const uint8_t P9N2__CTL_CONFIG_TX_CRET_FREQ_LEN = 3 ;
+static const uint8_t P9N2__CTL_CONFIG_TX_AGE_FREQ = 35 ;
+static const uint8_t P9N2__CTL_CONFIG_TX_AGE_FREQ_LEN = 5 ;
+static const uint8_t P9N2__CTL_CONFIG_TX_RS2_HPWAIT = 40 ;
+static const uint8_t P9N2__CTL_CONFIG_TX_RS2_HPWAIT_LEN = 6 ;
+static const uint8_t P9N2__CTL_CONFIG_TX_RQ4_HPWAIT = 46 ;
+static const uint8_t P9N2__CTL_CONFIG_TX_RQ4_HPWAIT_LEN = 6 ;
+static const uint8_t P9N2__CTL_CONFIG_TX_RQ6_HPWAIT = 52 ;
+static const uint8_t P9N2__CTL_CONFIG_TX_RQ6_HPWAIT_LEN = 6 ;
+static const uint8_t P9N2__CTL_CONFIG_TX_CBUF_ECC_DIS = 58 ;
+static const uint8_t P9N2__CTL_CONFIG_TX_STOP_LINK = 59 ;
+static const uint8_t P9N2__CTL_CONFIG_TX_STOP_ON_UE = 60 ;
+static const uint8_t P9N2__CTL_CONFIG_TX_T0_MASK_CRTN0 = 61 ;
+static const uint8_t P9N2__CTL_CONFIG_TX_T123_MASK_CRTN0 = 62 ;
+static const uint8_t P9N2__CTL_CONFIG_TX_SPARE3 = 63 ;
+
+static const uint8_t P9N2__SM2_CONFIG_TX_SPARE0 = 0 ;
+static const uint8_t P9N2__SM2_CONFIG_TX_TEMP1_EN = 1 ;
+static const uint8_t P9N2__SM2_CONFIG_TX_TEMP2_EN = 2 ;
+static const uint8_t P9N2__SM2_CONFIG_TX_TEMP3_EN = 3 ;
+static const uint8_t P9N2__SM2_CONFIG_TX_SPARE1 = 4 ;
+static const uint8_t P9N2__SM2_CONFIG_TX_DRDY_WAIT = 5 ;
+static const uint8_t P9N2__SM2_CONFIG_TX_DRDY_WAIT_LEN = 3 ;
+static const uint8_t P9N2__SM2_CONFIG_TX_TEMP0_RATE = 8 ;
+static const uint8_t P9N2__SM2_CONFIG_TX_TEMP0_RATE_LEN = 4 ;
+static const uint8_t P9N2__SM2_CONFIG_TX_TEMP1_RATE = 12 ;
+static const uint8_t P9N2__SM2_CONFIG_TX_TEMP1_RATE_LEN = 4 ;
+static const uint8_t P9N2__SM2_CONFIG_TX_TEMP2_RATE = 16 ;
+static const uint8_t P9N2__SM2_CONFIG_TX_TEMP2_RATE_LEN = 4 ;
+static const uint8_t P9N2__SM2_CONFIG_TX_TEMP3_RATE = 20 ;
+static const uint8_t P9N2__SM2_CONFIG_TX_TEMP3_RATE_LEN = 4 ;
+static const uint8_t P9N2__SM2_CONFIG_TX_SPARE2 = 24 ;
+static const uint8_t P9N2__SM2_CONFIG_TX_SPARE2_LEN = 8 ;
+static const uint8_t P9N2__SM2_CONFIG_TX_CRET_FREQ = 32 ;
+static const uint8_t P9N2__SM2_CONFIG_TX_CRET_FREQ_LEN = 3 ;
+static const uint8_t P9N2__SM2_CONFIG_TX_AGE_FREQ = 35 ;
+static const uint8_t P9N2__SM2_CONFIG_TX_AGE_FREQ_LEN = 5 ;
+static const uint8_t P9N2__SM2_CONFIG_TX_RS2_HPWAIT = 40 ;
+static const uint8_t P9N2__SM2_CONFIG_TX_RS2_HPWAIT_LEN = 6 ;
+static const uint8_t P9N2__SM2_CONFIG_TX_RQ4_HPWAIT = 46 ;
+static const uint8_t P9N2__SM2_CONFIG_TX_RQ4_HPWAIT_LEN = 6 ;
+static const uint8_t P9N2__SM2_CONFIG_TX_RQ6_HPWAIT = 52 ;
+static const uint8_t P9N2__SM2_CONFIG_TX_RQ6_HPWAIT_LEN = 6 ;
+static const uint8_t P9N2__SM2_CONFIG_TX_CBUF_ECC_DIS = 58 ;
+static const uint8_t P9N2__SM2_CONFIG_TX_STOP_LINK = 59 ;
+static const uint8_t P9N2__SM2_CONFIG_TX_STOP_ON_UE = 60 ;
+static const uint8_t P9N2__SM2_CONFIG_TX_T0_MASK_CRTN0 = 61 ;
+static const uint8_t P9N2__SM2_CONFIG_TX_T123_MASK_CRTN0 = 62 ;
+static const uint8_t P9N2__SM2_CONFIG_TX_SPARE3 = 63 ;
+
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TX2_TX_SEND_EN = 0 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TX2_TX_SPARE4 = 1 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TX2_TX_SPARE4_LEN = 3 ;
+
+static const uint8_t P9N2__CTL_CONFIG_TX2_TX_SEND_EN = 0 ;
+static const uint8_t P9N2__CTL_CONFIG_TX2_TX_SPARE4 = 1 ;
+static const uint8_t P9N2__CTL_CONFIG_TX2_TX_SPARE4_LEN = 3 ;
+
+static const uint8_t P9N2__SM3_CONFIG_TX2_TX_SEND_EN = 0 ;
+static const uint8_t P9N2__SM3_CONFIG_TX2_TX_SPARE4 = 1 ;
+static const uint8_t P9N2__SM3_CONFIG_TX2_TX_SPARE4_LEN = 3 ;
+
+static const uint8_t P9N2_PU_NPU_SM3_CONFIG_TX2_TX_SEND_EN = 0 ;
+static const uint8_t P9N2_PU_NPU_SM3_CONFIG_TX2_TX_SPARE4 = 1 ;
+static const uint8_t P9N2_PU_NPU_SM3_CONFIG_TX2_TX_SPARE4_LEN = 3 ;
+
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TX_DLC_DL_CREDITS = 0 ;
+static const uint8_t P9N2_PU_NPU_CTL_CONFIG_TX_DLC_DL_CREDITS_LEN = 10 ;
+
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TX_DLC_DL_CREDITS = 0 ;
+static const uint8_t P9N2_PU_NPU_SM2_CONFIG_TX_DLC_DL_CREDITS_LEN = 10 ;
+
+static const uint8_t P9N2__CTL_CONFIG_TX_DLC_DL_CREDITS = 0 ;
+static const uint8_t P9N2__CTL_CONFIG_TX_DLC_DL_CREDITS_LEN = 10 ;
+
+static const uint8_t P9N2__SM2_CONFIG_TX_DLC_DL_CREDITS = 0 ;
+static const uint8_t P9N2__SM2_CONFIG_TX_DLC_DL_CREDITS_LEN = 10 ;
+
+static const uint8_t P9N2_PEC_CONTROL_REG_RESET_TRIP_HISTORY = 0 ;
+static const uint8_t P9N2_PEC_CONTROL_REG_RESET_SAMPLE_PULSE_CNT = 1 ;
+static const uint8_t P9N2_PEC_CONTROL_REG_F_RESET_CPM_RD = 2 ;
+static const uint8_t P9N2_PEC_CONTROL_REG_F_RESET_CPM_WR = 3 ;
+static const uint8_t P9N2_PEC_CONTROL_REG_RESET_SAMPLE_DTS = 4 ;
+static const uint8_t P9N2_PEC_CONTROL_REG_FORCE_SAMPLE_DTS = 5 ;
+static const uint8_t P9N2_PEC_CONTROL_REG_FORCE_SAMPLE_DTS_INTERRUPTIBLE = 6 ;
+static const uint8_t P9N2_PEC_CONTROL_REG_FORCE_RESET_THRES_L1RESULTS = 7 ;
+static const uint8_t P9N2_PEC_CONTROL_REG_FORCE_RESET_THRES_L2RESULTS = 8 ;
+static const uint8_t P9N2_PEC_CONTROL_REG_FORCE_RESET_THRES_L3RESULTS = 9 ;
+static const uint8_t P9N2_PEC_CONTROL_REG_FORCE_MEASURE_VOLT_INTERRUPTIBLE = 10 ;
+static const uint8_t P9N2_PEC_CONTROL_REG_FORCE_RESET_MEASURE_VOLT = 11 ;
+static const uint8_t P9N2_PEC_CONTROL_REG_FORCE_SHIFT_SENSOR = 12 ;
+
+static const uint8_t P9N2_PU_CONTROL_REGISTER_B_PIB_CNTR_REG_BIT_WITHSTART_0 = 0 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_B_PIB_CNTR_REG_BIT_WITHADDR_0 = 1 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_B_PIB_CNTR_REG_BIT_READCONT_0 = 2 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_B_PIB_CNTR_REG_BIT_WITHSTOP_0 = 3 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_B_PIB_CNTR_REG_LENGTH_0 = 4 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_B_PIB_CNTR_REG_LENGTH_0_LEN = 4 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_B_PIB_CNTR_REG_ADDR_0 = 8 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_B_PIB_CNTR_REG_ADDR_0_LEN = 7 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_B_PIB_CNTR_REG_BIT_RNW_0 = 15 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_B_PIB_CNTR_REG_SPEED_0 = 16 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_B_PIB_CNTR_REG_SPEED_0_LEN = 2 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_B_PIB_CNTR_REG_PORT_NUMBER_0 = 18 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_B_PIB_CNTR_REG_PORT_NUMBER_0_LEN = 5 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_B_REG_ADDR_LEN_0 = 23 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_B_REG_ADDR_LEN_0_LEN = 3 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_B_ENH_MODE_0 = 26 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_B_ECC_ENABLE_0 = 27 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_B_ECCCHK_DISABLE_0 = 28 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_B_UNUSED_0 = 29 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_B_FAST_MODE_INTERRUPT_STERRING_BITS_0 = 30 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_B_FAST_MODE_INTERRUPT_STERRING_BITS_0_LEN = 2 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_B_PIB_CNTR_REG_DATA_1_0 = 32 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_B_PIB_CNTR_REG_DATA_1_0_LEN = 8 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_B_PIB_CNTR_REG_DATA_2_0 = 40 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_B_PIB_CNTR_REG_DATA_2_0_LEN = 8 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_B_PIB_CNTR_REG_DATA_3_0 = 48 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_B_PIB_CNTR_REG_DATA_3_0_LEN = 8 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_B_PIB_CNTR_REG_DATA_4_0 = 56 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_B_PIB_CNTR_REG_DATA_4_0_LEN = 8 ;
+
+static const uint8_t P9N2_PU_CONTROL_REGISTER_C_PIB_CNTR_REG_BIT_WITHSTART_1 = 0 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_C_PIB_CNTR_REG_BIT_WITHADDR_1 = 1 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_C_PIB_CNTR_REG_BIT_READCONT_1 = 2 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_C_PIB_CNTR_REG_BIT_WITHSTOP_1 = 3 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_C_PIB_CNTR_REG_LENGTH_1 = 4 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_C_PIB_CNTR_REG_LENGTH_1_LEN = 4 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_C_PIB_CNTR_REG_ADDR_1 = 8 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_C_PIB_CNTR_REG_ADDR_1_LEN = 7 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_C_PIB_CNTR_REG_BIT_RNW_1 = 15 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_C_PIB_CNTR_REG_SPEED_1 = 16 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_C_PIB_CNTR_REG_SPEED_1_LEN = 2 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_C_PIB_CNTR_REG_PORT_NUMBER_1 = 18 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_C_PIB_CNTR_REG_PORT_NUMBER_1_LEN = 5 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_C_REG_ADDR_LEN_1 = 23 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_C_REG_ADDR_LEN_1_LEN = 3 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_C_ENH_MODE_1 = 26 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_C_ECC_ENABLE_1 = 27 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_C_ECCCHK_DISABLE_1 = 28 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_C_UNUSED_1 = 29 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_C_FAST_MODE_INTERRUPT_STERRING_BITS_1 = 30 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_C_FAST_MODE_INTERRUPT_STERRING_BITS_1_LEN = 2 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_C_PIB_CNTR_REG_DATA_1_1 = 32 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_C_PIB_CNTR_REG_DATA_1_1_LEN = 8 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_C_PIB_CNTR_REG_DATA_2_1 = 40 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_C_PIB_CNTR_REG_DATA_2_1_LEN = 8 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_C_PIB_CNTR_REG_DATA_3_1 = 48 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_C_PIB_CNTR_REG_DATA_3_1_LEN = 8 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_C_PIB_CNTR_REG_DATA_4_1 = 56 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_C_PIB_CNTR_REG_DATA_4_1_LEN = 8 ;
+
+static const uint8_t P9N2_PU_CONTROL_REGISTER_D_PIB_CNTR_REG_BIT_WITHSTART_2 = 0 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_D_PIB_CNTR_REG_BIT_WITHADDR_2 = 1 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_D_PIB_CNTR_REG_BIT_READCONT_2 = 2 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_D_PIB_CNTR_REG_BIT_WITHSTOP_2 = 3 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_D_PIB_CNTR_REG_LENGTH_2 = 4 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_D_PIB_CNTR_REG_LENGTH_2_LEN = 4 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_D_PIB_CNTR_REG_ADDR_2 = 8 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_D_PIB_CNTR_REG_ADDR_2_LEN = 7 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_D_PIB_CNTR_REG_BIT_RNW_2 = 15 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_D_PIB_CNTR_REG_SPEED_2 = 16 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_D_PIB_CNTR_REG_SPEED_2_LEN = 2 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_D_PIB_CNTR_REG_PORT_NUMBER_2 = 18 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_D_PIB_CNTR_REG_PORT_NUMBER_2_LEN = 5 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_D_REG_ADDR_LEN_2 = 23 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_D_REG_ADDR_LEN_2_LEN = 3 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_D_ENH_MODE_2 = 26 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_D_ECC_ENABLE_2 = 27 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_D_ECCCHK_DISABLE_2 = 28 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_D_UNUSED_2 = 29 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_D_FAST_MODE_INTERRUPT_STERRING_BITS_2 = 30 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_D_FAST_MODE_INTERRUPT_STERRING_BITS_2_LEN = 2 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_D_PIB_CNTR_REG_DATA_1_2 = 32 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_D_PIB_CNTR_REG_DATA_1_2_LEN = 8 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_D_PIB_CNTR_REG_DATA_2_2 = 40 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_D_PIB_CNTR_REG_DATA_2_2_LEN = 8 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_D_PIB_CNTR_REG_DATA_3_2 = 48 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_D_PIB_CNTR_REG_DATA_3_2_LEN = 8 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_D_PIB_CNTR_REG_DATA_4_2 = 56 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_D_PIB_CNTR_REG_DATA_4_2_LEN = 8 ;
+
+static const uint8_t P9N2_PU_CONTROL_REGISTER_E_PIB_CNTR_REG_BIT_WITHSTART_3 = 0 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_E_PIB_CNTR_REG_BIT_WITHADDR_3 = 1 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_E_PIB_CNTR_REG_BIT_READCONT_3 = 2 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_E_PIB_CNTR_REG_BIT_WITHSTOP_3 = 3 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_E_PIB_CNTR_REG_LENGTH_3 = 4 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_E_PIB_CNTR_REG_LENGTH_3_LEN = 4 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_E_PIB_CNTR_REG_ADDR_3 = 8 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_E_PIB_CNTR_REG_ADDR_3_LEN = 7 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_E_PIB_CNTR_REG_BIT_RNW_3 = 15 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_E_PIB_CNTR_REG_SPEED_3 = 16 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_E_PIB_CNTR_REG_SPEED_3_LEN = 2 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_E_PIB_CNTR_REG_PORT_NUMBER_3 = 18 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_E_PIB_CNTR_REG_PORT_NUMBER_3_LEN = 5 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_E_REG_ADDR_LEN_3 = 23 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_E_REG_ADDR_LEN_3_LEN = 3 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_E_ENH_MODE_3 = 26 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_E_ECC_ENABLE_3 = 27 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_E_ECCCHK_DISABLE_3 = 28 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_E_UNUSED_3 = 29 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_E_FAST_MODE_INTERRUPT_STERRING_BITS_3 = 30 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_E_FAST_MODE_INTERRUPT_STERRING_BITS_3_LEN = 2 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_E_PIB_CNTR_REG_DATA_1_3 = 32 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_E_PIB_CNTR_REG_DATA_1_3_LEN = 8 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_E_PIB_CNTR_REG_DATA_2_3 = 40 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_E_PIB_CNTR_REG_DATA_2_3_LEN = 8 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_E_PIB_CNTR_REG_DATA_3_3 = 48 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_E_PIB_CNTR_REG_DATA_3_3_LEN = 8 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_E_PIB_CNTR_REG_DATA_4_3 = 56 ;
+static const uint8_t P9N2_PU_CONTROL_REGISTER_E_PIB_CNTR_REG_DATA_4_3_LEN = 8 ;
+
+static const uint8_t P9N2_PEC_CPLT_CONF0_CTRL_MISC_PROBE0_SEL_DC = 0 ;
+static const uint8_t P9N2_PEC_CPLT_CONF0_CTRL_MISC_PROBE0_SEL_DC_LEN = 6 ;
+static const uint8_t P9N2_PEC_CPLT_CONF0_RESERVED_6C = 6 ;
+static const uint8_t P9N2_PEC_CPLT_CONF0_RESERVED_7C = 7 ;
+static const uint8_t P9N2_PEC_CPLT_CONF0_CTRL_MISC_PROBE1_SEL_DC = 8 ;
+static const uint8_t P9N2_PEC_CPLT_CONF0_CTRL_MISC_PROBE1_SEL_DC_LEN = 6 ;
+static const uint8_t P9N2_PEC_CPLT_CONF0_RESERVED_14C = 14 ;
+static const uint8_t P9N2_PEC_CPLT_CONF0_RESERVED_15C = 15 ;
+static const uint8_t P9N2_PEC_CPLT_CONF0_CTRL_MISC_PROBE2_SEL_DC = 16 ;
+static const uint8_t P9N2_PEC_CPLT_CONF0_CTRL_MISC_PROBE2_SEL_DC_LEN = 6 ;
+static const uint8_t P9N2_PEC_CPLT_CONF0_RESERVED_22C = 22 ;
+static const uint8_t P9N2_PEC_CPLT_CONF0_RESERVED_23C = 23 ;
+static const uint8_t P9N2_PEC_CPLT_CONF0_CTRL_MISC_PROBE3_SEL_DC = 24 ;
+static const uint8_t P9N2_PEC_CPLT_CONF0_CTRL_MISC_PROBE3_SEL_DC_LEN = 6 ;
+static const uint8_t P9N2_PEC_CPLT_CONF0_RESERVED_30C = 30 ;
+static const uint8_t P9N2_PEC_CPLT_CONF0_RESERVED_31C = 31 ;
+static const uint8_t P9N2_PEC_CPLT_CONF0_CTRL_CC_OFLOW_FEH_SEL_DC = 32 ;
+static const uint8_t P9N2_PEC_CPLT_CONF0_CTRL_CC_SCAN_PROTECT_DC = 33 ;
+static const uint8_t P9N2_PEC_CPLT_CONF0_CTRL_CC_SDIS_DC_N = 34 ;
+static const uint8_t P9N2_PEC_CPLT_CONF0_CTRL_CC_SCAN_DIAG = 35 ;
+static const uint8_t P9N2_PEC_CPLT_CONF0_RESERVED_TEST_CONTROL_36C = 36 ;
+static const uint8_t P9N2_PEC_CPLT_CONF0_RESERVED_TEST_CONTROL_37C = 37 ;
+static const uint8_t P9N2_PEC_CPLT_CONF0_RESERVED_TEST_CONTROL_38C = 38 ;
+static const uint8_t P9N2_PEC_CPLT_CONF0_RESERVED_TEST_CONTROL_39C = 39 ;
+static const uint8_t P9N2_PEC_CPLT_CONF0_CTRL_EPS_MASK_VITL_PCB_ERR_DC = 40 ;
+static const uint8_t P9N2_PEC_CPLT_CONF0_CTRL_CC_MASK_VITL_SCAN_OPCG_ERR_DC = 41 ;
+static const uint8_t P9N2_PEC_CPLT_CONF0_RESERVED_42C = 42 ;
+static const uint8_t P9N2_PEC_CPLT_CONF0_RESERVED_43C = 43 ;
+static const uint8_t P9N2_PEC_CPLT_CONF0_TC_PCB_DBG_GLB_BRCST_EN = 44 ;
+static const uint8_t P9N2_PEC_CPLT_CONF0_FREE_USAGE_45C = 45 ;
+static const uint8_t P9N2_PEC_CPLT_CONF0_FREE_USAGE_46C = 46 ;
+static const uint8_t P9N2_PEC_CPLT_CONF0_FREE_USAGE_47C = 47 ;
+static const uint8_t P9N2_PEC_CPLT_CONF0_TC_UNIT_GROUP_ID_DC = 48 ;
+static const uint8_t P9N2_PEC_CPLT_CONF0_TC_UNIT_GROUP_ID_DC_LEN = 4 ;
+static const uint8_t P9N2_PEC_CPLT_CONF0_TC_UNIT_CHIP_ID_DC = 52 ;
+static const uint8_t P9N2_PEC_CPLT_CONF0_TC_UNIT_CHIP_ID_DC_LEN = 3 ;
+static const uint8_t P9N2_PEC_CPLT_CONF0_RESERVED_ID_55C = 55 ;
+static const uint8_t P9N2_PEC_CPLT_CONF0_TC_UNIT_SYS_ID_DC = 56 ;
+static const uint8_t P9N2_PEC_CPLT_CONF0_TC_UNIT_SYS_ID_DC_LEN = 5 ;
+static const uint8_t P9N2_PEC_CPLT_CONF0_RESERVED_ID_61C = 61 ;
+static const uint8_t P9N2_PEC_CPLT_CONF0_RESERVED_ID_62C = 62 ;
+static const uint8_t P9N2_PEC_CPLT_CONF0_RESERVED_ID_63C = 63 ;
+
+static const uint8_t P9N2_PEC_CPLT_CONF1_UNUSED_0D = 0 ;
+static const uint8_t P9N2_PEC_CPLT_CONF1_UNUSED_1D = 1 ;
+static const uint8_t P9N2_PEC_CPLT_CONF1_UNUSED_2D = 2 ;
+static const uint8_t P9N2_PEC_CPLT_CONF1_UNUSED_3D = 3 ;
+static const uint8_t P9N2_PEC_CPLT_CONF1_TC_PCI0_IOVALID = 4 ;
+static const uint8_t P9N2_PEC_CPLT_CONF1_UNUSED_5D = 5 ;
+static const uint8_t P9N2_PEC_CPLT_CONF1_UNUSED_6D = 6 ;
+static const uint8_t P9N2_PEC_CPLT_CONF1_UNUSED_7D = 7 ;
+static const uint8_t P9N2_PEC_CPLT_CONF1_UNUSED_8D = 8 ;
+static const uint8_t P9N2_PEC_CPLT_CONF1_UNUSED_9D = 9 ;
+static const uint8_t P9N2_PEC_CPLT_CONF1_UNUSED_10D = 10 ;
+static const uint8_t P9N2_PEC_CPLT_CONF1_UNUSED_11D = 11 ;
+static const uint8_t P9N2_PEC_CPLT_CONF1_TC_PCI0_SWAP_DC = 12 ;
+static const uint8_t P9N2_PEC_CPLT_CONF1_TC_PCI0_LANE_CFG_DC = 13 ;
+static const uint8_t P9N2_PEC_CPLT_CONF1_TC_PCI0_LANE_CFG_DC_LEN = 2 ;
+static const uint8_t P9N2_PEC_CPLT_CONF1_TC_PCI0_RATIO_OVERRIDE = 15 ;
+static const uint8_t P9N2_PEC_CPLT_CONF1_TC_PCI0_RATIO_DC = 16 ;
+static const uint8_t P9N2_PEC_CPLT_CONF1_TC_PCI0_RATIO_DC_LEN = 3 ;
+static const uint8_t P9N2_PEC_CPLT_CONF1_UNUSED_19D = 19 ;
+static const uint8_t P9N2_PEC_CPLT_CONF1_UNUSED_20D = 20 ;
+static const uint8_t P9N2_PEC_CPLT_CONF1_UNUSED_21D = 21 ;
+static const uint8_t P9N2_PEC_CPLT_CONF1_UNUSED_22D = 22 ;
+static const uint8_t P9N2_PEC_CPLT_CONF1_UNUSED_23D = 23 ;
+static const uint8_t P9N2_PEC_CPLT_CONF1_UNUSED_24D = 24 ;
+static const uint8_t P9N2_PEC_CPLT_CONF1_UNUSED_25D = 25 ;
+static const uint8_t P9N2_PEC_CPLT_CONF1_UNUSED_26D = 26 ;
+static const uint8_t P9N2_PEC_CPLT_CONF1_UNUSED_27D = 27 ;
+static const uint8_t P9N2_PEC_CPLT_CONF1_TC_IOP_SYS_RESET_PCS = 28 ;
+static const uint8_t P9N2_PEC_CPLT_CONF1_TC_IOP_SYS_RESET_PMA = 29 ;
+static const uint8_t P9N2_PEC_CPLT_CONF1_TC_IOP_HSSPORWREN = 30 ;
+static const uint8_t P9N2_PEC_CPLT_CONF1_UNUSED_31D = 31 ;
+
+static const uint8_t P9N2_PEC_CPLT_CTRL0_CTRL_CC_ABSTCLK_MUXSEL_DC = 0 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL0_TC_UNIT_SYNCCLK_MUXSEL_DC = 1 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL0_CTRL_CC_FLUSHMODE_INH_DC = 2 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL0_CTRL_CC_FORCE_ALIGN_DC = 3 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL0_TC_UNIT_ARY_WRT_THRU_DC = 4 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL0_UNUSED_5A = 5 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL0_UNUSED_6A = 6 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL0_UNUSED_7A = 7 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL0_CTRL_CC_ABIST_RECOV_DISABLE_DC = 8 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL0_UNUSED_9A = 9 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL0_UNUSED_10A = 10 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL0_RESERVED_11A = 11 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL0_TC_SKIT_MODE_BIST_DC = 12 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL0_TC_UNIT_DETERMINISTIC_TEST_ENABLE_DC = 13 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL0_TC_UNIT_CONSTRAIN_SAFESCAN_DC = 14 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL0_TC_UNIT_RRFA_TEST_ENABLE_DC = 15 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL0_UNUSED_16A = 16 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL0_UNUSED_17A = 17 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL0_RESERVED_18A = 18 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL0_RESERVED_19A = 19 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL0_UNUSED_20A = 20 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL0_UNUSED_21A = 21 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL0_UNUSED_22A = 22 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL0_UNUSED_23A = 23 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL0_UNUSED_24A = 24 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL0_UNUSED_25A = 25 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL0_UNUSED_26A = 26 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL0_UNUSED_27A = 27 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL0_TC_BSC_WRAPSEL_DC = 28 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL0_TC_BSC_INTMODE_DC = 29 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL0_TC_BSC_INV_DC = 30 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL0_TC_BSC_EXTMODE_DC = 31 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL0_TC_REFCLK_DRVR_EN_DC = 32 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL0_RESERVED_33A = 33 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL0_RESERVED_34A = 34 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL0_RESERVED_35A = 35 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL0_UNUSED_36A = 36 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL0_UNUSED_37A = 37 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL0_RESERVED_38A = 38 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL0_RESERVED_39A = 39 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL0_CTRL_MISC_CLKDIV_SEL_DC = 40 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL0_CTRL_MISC_CLKDIV_SEL_DC_LEN = 2 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL0_RESERVED_42A = 42 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL0_RESERVED_43A = 43 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL0_UNUSED_44A = 44 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL0_UNUSED_45A = 45 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL0_UNUSED_46A = 46 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL0_CTRL_CC_PIN_LBIST_DC = 47 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL0_FREE_USAGE_48A = 48 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL0_FREE_USAGE_49A = 49 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL0_FREE_USAGE_50A = 50 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL0_FREE_USAGE_51A = 51 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL0_FREE_USAGE_52A = 52 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL0_FREE_USAGE_53A = 53 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL0_FREE_USAGE_54A = 54 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL0_FREE_USAGE_55A = 55 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL0_FREE_USAGE_56A = 56 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL0_FREE_USAGE_57A = 57 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL0_FREE_USAGE_58A = 58 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL0_FREE_USAGE_59A = 59 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL0_FREE_USAGE_60A = 60 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL0_FREE_USAGE_61A = 61 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL0_FREE_USAGE_62A = 62 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL0_FREE_USAGE_63A = 63 ;
+
+static const uint8_t P9N2_PEC_CPLT_CTRL1_UNUSED_0B = 0 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL1_UNUSED_1B = 1 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL1_UNUSED_2B = 2 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL1_TC_VITL_REGION_FENCE = 3 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL1_TC_PERV_REGION_FENCE = 4 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL1_TC_REGION1_FENCE = 5 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL1_TC_REGION2_FENCE = 6 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL1_UNUSED_7B = 7 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL1_UNUSED_8B = 8 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL1_UNUSED_9B = 9 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL1_UNUSED_10B = 10 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL1_UNUSED_11B = 11 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL1_UNUSED_12B = 12 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL1_UNUSED_13B = 13 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL1_UNUSED_14B = 14 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL1_RESERVED = 15 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL1_TC_UNIT_MULTICYCLE_TEST_FENCE = 16 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL1_UNUSED_17B = 17 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL1_UNUSED_18B = 18 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL1_UNUSED_19B = 19 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL1_UNUSED_20B = 20 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL1_UNUSED_21B = 21 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL1_UNUSED_22B = 22 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL1_UNUSED_23B = 23 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL1_UNUSED_24B = 24 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL1_UNUSED_25B = 25 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL1_UNUSED_26B = 26 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL1_UNUSED_27B = 27 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL1_UNUSED_28B = 28 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL1_UNUSED_29B = 29 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL1_UNUSED_30B = 30 ;
+static const uint8_t P9N2_PEC_CPLT_CTRL1_UNUSED_31B = 31 ;
+
+static const uint8_t P9N2_PEC_CPLT_MASK0_CPLTMASK0 = 0 ;
+static const uint8_t P9N2_PEC_CPLT_MASK0_CPLTMASK0_LEN = 24 ;
+
+static const uint8_t P9N2_PEC_CPLT_STAT0_ABIST_DONE_DC = 0 ;
+static const uint8_t P9N2_PEC_CPLT_STAT0_UNUSED = 1 ;
+static const uint8_t P9N2_PEC_CPLT_STAT0_RESERVED_2E = 2 ;
+static const uint8_t P9N2_PEC_CPLT_STAT0_RESERVED_3E = 3 ;
+static const uint8_t P9N2_PEC_CPLT_STAT0_TC_DIAG_PORT0_OUT = 4 ;
+static const uint8_t P9N2_PEC_CPLT_STAT0_TC_DIAG_PORT1_OUT = 5 ;
+static const uint8_t P9N2_PEC_CPLT_STAT0_RESERVED_6E = 6 ;
+static const uint8_t P9N2_PEC_CPLT_STAT0_PLL_DESTOUT = 7 ;
+static const uint8_t P9N2_PEC_CPLT_STAT0_CC_CTRL_OPCG_DONE_DC = 8 ;
+static const uint8_t P9N2_PEC_CPLT_STAT0_CC_CTRL_CHIPLET_IS_ALIGNED_DC = 9 ;
+static const uint8_t P9N2_PEC_CPLT_STAT0_IOPCI_TC_HSSPRTREADYA = 10 ;
+static const uint8_t P9N2_PEC_CPLT_STAT0_IOPCI_TC_HSSPRTREADYB = 11 ;
+static const uint8_t P9N2_PEC_CPLT_STAT0_FREE_USAGE_12E = 12 ;
+static const uint8_t P9N2_PEC_CPLT_STAT0_FREE_USAGE_13E = 13 ;
+static const uint8_t P9N2_PEC_CPLT_STAT0_FREE_USAGE_14E = 14 ;
+static const uint8_t P9N2_PEC_CPLT_STAT0_FREE_USAGE_15E = 15 ;
+static const uint8_t P9N2_PEC_CPLT_STAT0_FREE_USAGE_16E = 16 ;
+static const uint8_t P9N2_PEC_CPLT_STAT0_FREE_USAGE_17E = 17 ;
+static const uint8_t P9N2_PEC_CPLT_STAT0_FREE_USAGE_18E = 18 ;
+static const uint8_t P9N2_PEC_CPLT_STAT0_FREE_USAGE_19E = 19 ;
+static const uint8_t P9N2_PEC_CPLT_STAT0_FREE_USAGE_20E = 20 ;
+static const uint8_t P9N2_PEC_CPLT_STAT0_FREE_USAGE_21E = 21 ;
+static const uint8_t P9N2_PEC_CPLT_STAT0_FREE_USAGE_22E = 22 ;
+static const uint8_t P9N2_PEC_CPLT_STAT0_FREE_USAGE_23E = 23 ;
+
+static const uint8_t P9N2_PHB_CQSTAT_REG_PE_INBOUND_ACTIVE = 0 ;
+static const uint8_t P9N2_PHB_CQSTAT_REG_PE_OUTBOUND_ACTIVE = 1 ;
+
+static const uint8_t P9N2_PEC_STACK0_CQSTAT_REG_PE_INBOUND_ACTIVE = 0 ;
+static const uint8_t P9N2_PEC_STACK0_CQSTAT_REG_PE_OUTBOUND_ACTIVE = 1 ;
+
+static const uint8_t P9N2_PU_NPU1_SM1_CREQ_DA_PTR_RESERVED1 = 0 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CREQ_DA_PTR_RESERVED1_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CREQ_DA_PTR_START = 3 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CREQ_DA_PTR_START_LEN = 9 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CREQ_DA_PTR_RESERVED2 = 12 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CREQ_DA_PTR_RESERVED2_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CREQ_DA_PTR_END = 15 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CREQ_DA_PTR_END_LEN = 9 ;
+
+static const uint8_t P9N2_PU_NPU_SM2_CREQ_DA_PTR_RESERVED1 = 0 ;
+static const uint8_t P9N2_PU_NPU_SM2_CREQ_DA_PTR_RESERVED1_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_SM2_CREQ_DA_PTR_START = 3 ;
+static const uint8_t P9N2_PU_NPU_SM2_CREQ_DA_PTR_START_LEN = 9 ;
+static const uint8_t P9N2_PU_NPU_SM2_CREQ_DA_PTR_RESERVED2 = 12 ;
+static const uint8_t P9N2_PU_NPU_SM2_CREQ_DA_PTR_RESERVED2_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_SM2_CREQ_DA_PTR_END = 15 ;
+static const uint8_t P9N2_PU_NPU_SM2_CREQ_DA_PTR_END_LEN = 9 ;
+
+static const uint8_t P9N2_PU_NPU1_SM2_CREQ_DA_PTR_RESERVED1 = 0 ;
+static const uint8_t P9N2_PU_NPU1_SM2_CREQ_DA_PTR_RESERVED1_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU1_SM2_CREQ_DA_PTR_START = 3 ;
+static const uint8_t P9N2_PU_NPU1_SM2_CREQ_DA_PTR_START_LEN = 9 ;
+static const uint8_t P9N2_PU_NPU1_SM2_CREQ_DA_PTR_RESERVED2 = 12 ;
+static const uint8_t P9N2_PU_NPU1_SM2_CREQ_DA_PTR_RESERVED2_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU1_SM2_CREQ_DA_PTR_END = 15 ;
+static const uint8_t P9N2_PU_NPU1_SM2_CREQ_DA_PTR_END_LEN = 9 ;
+
+static const uint8_t P9N2_PU_NPU_SM1_CREQ_DA_PTR_RESERVED1 = 0 ;
+static const uint8_t P9N2_PU_NPU_SM1_CREQ_DA_PTR_RESERVED1_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_SM1_CREQ_DA_PTR_START = 3 ;
+static const uint8_t P9N2_PU_NPU_SM1_CREQ_DA_PTR_START_LEN = 9 ;
+static const uint8_t P9N2_PU_NPU_SM1_CREQ_DA_PTR_RESERVED2 = 12 ;
+static const uint8_t P9N2_PU_NPU_SM1_CREQ_DA_PTR_RESERVED2_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_SM1_CREQ_DA_PTR_END = 15 ;
+static const uint8_t P9N2_PU_NPU_SM1_CREQ_DA_PTR_END_LEN = 9 ;
+
+static const uint8_t P9N2__SM2_CREQ_DA_PTR_RESERVED1 = 0 ;
+static const uint8_t P9N2__SM2_CREQ_DA_PTR_RESERVED1_LEN = 3 ;
+static const uint8_t P9N2__SM2_CREQ_DA_PTR_START = 3 ;
+static const uint8_t P9N2__SM2_CREQ_DA_PTR_START_LEN = 9 ;
+static const uint8_t P9N2__SM2_CREQ_DA_PTR_RESERVED2 = 12 ;
+static const uint8_t P9N2__SM2_CREQ_DA_PTR_RESERVED2_LEN = 3 ;
+static const uint8_t P9N2__SM2_CREQ_DA_PTR_END = 15 ;
+static const uint8_t P9N2__SM2_CREQ_DA_PTR_END_LEN = 9 ;
+
+static const uint8_t P9N2__SM1_CREQ_DA_PTR_RESERVED1 = 0 ;
+static const uint8_t P9N2__SM1_CREQ_DA_PTR_RESERVED1_LEN = 3 ;
+static const uint8_t P9N2__SM1_CREQ_DA_PTR_START = 3 ;
+static const uint8_t P9N2__SM1_CREQ_DA_PTR_START_LEN = 9 ;
+static const uint8_t P9N2__SM1_CREQ_DA_PTR_RESERVED2 = 12 ;
+static const uint8_t P9N2__SM1_CREQ_DA_PTR_RESERVED2_LEN = 3 ;
+static const uint8_t P9N2__SM1_CREQ_DA_PTR_END = 15 ;
+static const uint8_t P9N2__SM1_CREQ_DA_PTR_END_LEN = 9 ;
+
+static const uint8_t P9N2_PU_NPU1_SM1_CREQ_HA_PTR_RESERVED1 = 0 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CREQ_HA_PTR_RESERVED1_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CREQ_HA_PTR_START = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CREQ_HA_PTR_START_LEN = 7 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CREQ_HA_PTR_RESERVED2 = 12 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CREQ_HA_PTR_RESERVED2_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CREQ_HA_PTR_END = 17 ;
+static const uint8_t P9N2_PU_NPU1_SM1_CREQ_HA_PTR_END_LEN = 7 ;
+
+static const uint8_t P9N2_PU_NPU_SM2_CREQ_HA_PTR_RESERVED1 = 0 ;
+static const uint8_t P9N2_PU_NPU_SM2_CREQ_HA_PTR_RESERVED1_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM2_CREQ_HA_PTR_START = 5 ;
+static const uint8_t P9N2_PU_NPU_SM2_CREQ_HA_PTR_START_LEN = 7 ;
+static const uint8_t P9N2_PU_NPU_SM2_CREQ_HA_PTR_RESERVED2 = 12 ;
+static const uint8_t P9N2_PU_NPU_SM2_CREQ_HA_PTR_RESERVED2_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM2_CREQ_HA_PTR_END = 17 ;
+static const uint8_t P9N2_PU_NPU_SM2_CREQ_HA_PTR_END_LEN = 7 ;
+
+static const uint8_t P9N2_PU_NPU1_SM2_CREQ_HA_PTR_RESERVED1 = 0 ;
+static const uint8_t P9N2_PU_NPU1_SM2_CREQ_HA_PTR_RESERVED1_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM2_CREQ_HA_PTR_START = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM2_CREQ_HA_PTR_START_LEN = 7 ;
+static const uint8_t P9N2_PU_NPU1_SM2_CREQ_HA_PTR_RESERVED2 = 12 ;
+static const uint8_t P9N2_PU_NPU1_SM2_CREQ_HA_PTR_RESERVED2_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM2_CREQ_HA_PTR_END = 17 ;
+static const uint8_t P9N2_PU_NPU1_SM2_CREQ_HA_PTR_END_LEN = 7 ;
+
+static const uint8_t P9N2_PU_NPU_SM1_CREQ_HA_PTR_RESERVED1 = 0 ;
+static const uint8_t P9N2_PU_NPU_SM1_CREQ_HA_PTR_RESERVED1_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM1_CREQ_HA_PTR_START = 5 ;
+static const uint8_t P9N2_PU_NPU_SM1_CREQ_HA_PTR_START_LEN = 7 ;
+static const uint8_t P9N2_PU_NPU_SM1_CREQ_HA_PTR_RESERVED2 = 12 ;
+static const uint8_t P9N2_PU_NPU_SM1_CREQ_HA_PTR_RESERVED2_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM1_CREQ_HA_PTR_END = 17 ;
+static const uint8_t P9N2_PU_NPU_SM1_CREQ_HA_PTR_END_LEN = 7 ;
+
+static const uint8_t P9N2__SM2_CREQ_HA_PTR_RESERVED1 = 0 ;
+static const uint8_t P9N2__SM2_CREQ_HA_PTR_RESERVED1_LEN = 5 ;
+static const uint8_t P9N2__SM2_CREQ_HA_PTR_START = 5 ;
+static const uint8_t P9N2__SM2_CREQ_HA_PTR_START_LEN = 7 ;
+static const uint8_t P9N2__SM2_CREQ_HA_PTR_RESERVED2 = 12 ;
+static const uint8_t P9N2__SM2_CREQ_HA_PTR_RESERVED2_LEN = 5 ;
+static const uint8_t P9N2__SM2_CREQ_HA_PTR_END = 17 ;
+static const uint8_t P9N2__SM2_CREQ_HA_PTR_END_LEN = 7 ;
+
+static const uint8_t P9N2__SM1_CREQ_HA_PTR_RESERVED1 = 0 ;
+static const uint8_t P9N2__SM1_CREQ_HA_PTR_RESERVED1_LEN = 5 ;
+static const uint8_t P9N2__SM1_CREQ_HA_PTR_START = 5 ;
+static const uint8_t P9N2__SM1_CREQ_HA_PTR_START_LEN = 7 ;
+static const uint8_t P9N2__SM1_CREQ_HA_PTR_RESERVED2 = 12 ;
+static const uint8_t P9N2__SM1_CREQ_HA_PTR_RESERVED2_LEN = 5 ;
+static const uint8_t P9N2__SM1_CREQ_HA_PTR_END = 17 ;
+static const uint8_t P9N2__SM1_CREQ_HA_PTR_END_LEN = 7 ;
+
+static const uint8_t P9N2_PU_CSAR_SRAM_ADDRESS = 16 ;
+static const uint8_t P9N2_PU_CSAR_SRAM_ADDRESS_LEN = 13 ;
+
+static const uint8_t P9N2_PU_CSCR_SRAM_ACCESS_MODE = 0 ;
+static const uint8_t P9N2_PU_CSCR_SRAM_SCRUB_ENABLE = 1 ;
+static const uint8_t P9N2_PU_CSCR_ECC_CORRECT_DIS = 2 ;
+static const uint8_t P9N2_PU_CSCR_ECC_DETECT_DIS = 3 ;
+static const uint8_t P9N2_PU_CSCR_ECC_INJECT_TYPE = 4 ;
+static const uint8_t P9N2_PU_CSCR_ECC_INJECT_ERR = 5 ;
+static const uint8_t P9N2_PU_CSCR_SPARE_6_7 = 6 ;
+static const uint8_t P9N2_PU_CSCR_SPARE_6_7_LEN = 2 ;
+static const uint8_t P9N2_PU_CSCR_SRAM_SCRUB_INDEX = 47 ;
+static const uint8_t P9N2_PU_CSCR_SRAM_SCRUB_INDEX_LEN = 13 ;
+
+static const uint8_t P9N2_PU_CSDR_SRAM_DATA = 0 ;
+static const uint8_t P9N2_PU_CSDR_SRAM_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_SM_MMIO0 = 0 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_SM_MMIO1 = 1 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_SM_MMIO2 = 2 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_SM_MMIO3 = 3 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_MRBGP = 4 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_MRBGP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_MRBSP = 8 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_MRBSP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_FENCE0 = 12 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_FENCE0_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_FENCE1 = 16 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_FENCE1_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_LPCTH = 20 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_LPCTH_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_PBM_STATE = 22 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_PBM_STATE_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_BRK0_RLX = 28 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_BRK1_RLX = 29 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_BRK0_NVL = 30 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_BRK1_NVL = 31 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_ATS_SYNC = 32 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_NMMU = 33 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_PBLN = 34 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_PBNNG = 35 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_PBRNVG = 36 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_NVREQ0 = 37 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_NVDGD0 = 38 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_NVREQ1 = 39 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_NVDGD1 = 40 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_ATSREQ = 41 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_MMIO = 42 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_PBRS = 43 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_NVRS0 = 44 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_NVRS1 = 45 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_XARS = 46 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_ATRR = 47 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_BRK0_AM_FENCED = 48 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_BRK0_AM_FENCED_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_BRK1_AM_FENCED = 50 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_BRK1_AM_FENCED_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_BRK0_NTL_REQ_FENCE = 52 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_BRK0_NTL_REQ_FENCE_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_BRK1_NTL_REQ_FENCE = 54 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_BRK1_NTL_REQ_FENCE_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_MRBCP = 56 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_MRBCP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_BRK0_MISC_FENCE = 60 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_BRK1_MISC_FENCE = 61 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_RESERVED = 62 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_CTL_STATUS_RESERVED_LEN = 2 ;
+
+static const uint8_t P9N2_NV_CTL_STATUS_SM_MMIO0 = 0 ;
+static const uint8_t P9N2_NV_CTL_STATUS_SM_MMIO1 = 1 ;
+static const uint8_t P9N2_NV_CTL_STATUS_SM_MMIO2 = 2 ;
+static const uint8_t P9N2_NV_CTL_STATUS_SM_MMIO3 = 3 ;
+static const uint8_t P9N2_NV_CTL_STATUS_MRBGP = 4 ;
+static const uint8_t P9N2_NV_CTL_STATUS_MRBGP_LEN = 4 ;
+static const uint8_t P9N2_NV_CTL_STATUS_MRBSP = 8 ;
+static const uint8_t P9N2_NV_CTL_STATUS_MRBSP_LEN = 4 ;
+static const uint8_t P9N2_NV_CTL_STATUS_FENCE0 = 12 ;
+static const uint8_t P9N2_NV_CTL_STATUS_FENCE0_LEN = 4 ;
+static const uint8_t P9N2_NV_CTL_STATUS_FENCE1 = 16 ;
+static const uint8_t P9N2_NV_CTL_STATUS_FENCE1_LEN = 4 ;
+static const uint8_t P9N2_NV_CTL_STATUS_LPCTH = 20 ;
+static const uint8_t P9N2_NV_CTL_STATUS_LPCTH_LEN = 2 ;
+static const uint8_t P9N2_NV_CTL_STATUS_PBM_STATE = 22 ;
+static const uint8_t P9N2_NV_CTL_STATUS_PBM_STATE_LEN = 6 ;
+static const uint8_t P9N2_NV_CTL_STATUS_BRK0_RLX = 28 ;
+static const uint8_t P9N2_NV_CTL_STATUS_BRK1_RLX = 29 ;
+static const uint8_t P9N2_NV_CTL_STATUS_BRK0_NVL = 30 ;
+static const uint8_t P9N2_NV_CTL_STATUS_BRK1_NVL = 31 ;
+static const uint8_t P9N2_NV_CTL_STATUS_ATS_SYNC = 32 ;
+static const uint8_t P9N2_NV_CTL_STATUS_NMMU = 33 ;
+static const uint8_t P9N2_NV_CTL_STATUS_PBLN = 34 ;
+static const uint8_t P9N2_NV_CTL_STATUS_PBNNG = 35 ;
+static const uint8_t P9N2_NV_CTL_STATUS_PBRNVG = 36 ;
+static const uint8_t P9N2_NV_CTL_STATUS_NVREQ0 = 37 ;
+static const uint8_t P9N2_NV_CTL_STATUS_NVDGD0 = 38 ;
+static const uint8_t P9N2_NV_CTL_STATUS_NVREQ1 = 39 ;
+static const uint8_t P9N2_NV_CTL_STATUS_NVDGD1 = 40 ;
+static const uint8_t P9N2_NV_CTL_STATUS_ATSREQ = 41 ;
+static const uint8_t P9N2_NV_CTL_STATUS_MMIO = 42 ;
+static const uint8_t P9N2_NV_CTL_STATUS_PBRS = 43 ;
+static const uint8_t P9N2_NV_CTL_STATUS_NVRS0 = 44 ;
+static const uint8_t P9N2_NV_CTL_STATUS_NVRS1 = 45 ;
+static const uint8_t P9N2_NV_CTL_STATUS_XARS = 46 ;
+static const uint8_t P9N2_NV_CTL_STATUS_ATRR = 47 ;
+static const uint8_t P9N2_NV_CTL_STATUS_BRK0_AM_FENCED = 48 ;
+static const uint8_t P9N2_NV_CTL_STATUS_BRK0_AM_FENCED_LEN = 2 ;
+static const uint8_t P9N2_NV_CTL_STATUS_BRK1_AM_FENCED = 50 ;
+static const uint8_t P9N2_NV_CTL_STATUS_BRK1_AM_FENCED_LEN = 2 ;
+static const uint8_t P9N2_NV_CTL_STATUS_BRK0_NTL_REQ_FENCE = 52 ;
+static const uint8_t P9N2_NV_CTL_STATUS_BRK0_NTL_REQ_FENCE_LEN = 2 ;
+static const uint8_t P9N2_NV_CTL_STATUS_BRK1_NTL_REQ_FENCE = 54 ;
+static const uint8_t P9N2_NV_CTL_STATUS_BRK1_NTL_REQ_FENCE_LEN = 2 ;
+static const uint8_t P9N2_NV_CTL_STATUS_MRBCP = 56 ;
+static const uint8_t P9N2_NV_CTL_STATUS_MRBCP_LEN = 4 ;
+static const uint8_t P9N2_NV_CTL_STATUS_BRK0_MISC_FENCE = 60 ;
+static const uint8_t P9N2_NV_CTL_STATUS_BRK1_MISC_FENCE = 61 ;
+static const uint8_t P9N2_NV_CTL_STATUS_RESERVED = 62 ;
+static const uint8_t P9N2_NV_CTL_STATUS_RESERVED_LEN = 2 ;
+
+static const uint8_t P9N2_PEC_CTRL_ATOMIC_LOCK_REG_ENABLE = 0 ;
+static const uint8_t P9N2_PEC_CTRL_ATOMIC_LOCK_REG_ID = 1 ;
+static const uint8_t P9N2_PEC_CTRL_ATOMIC_LOCK_REG_ID_LEN = 4 ;
+static const uint8_t P9N2_PEC_CTRL_ATOMIC_LOCK_REG_ACTIVITY = 8 ;
+static const uint8_t P9N2_PEC_CTRL_ATOMIC_LOCK_REG_ACTIVITY_LEN = 8 ;
+
+static const uint8_t P9N2_PEC_CTRL_PROTECT_MODE_REG_READ_ENABLE = 0 ;
+static const uint8_t P9N2_PEC_CTRL_PROTECT_MODE_REG_WRITE_ENABLE = 1 ;
+
+static const uint8_t P9N2_CAPP_CXA_SNP_ARRAY_ADDR_REG_ADDRESS = 1 ;
+static const uint8_t P9N2_CAPP_CXA_SNP_ARRAY_ADDR_REG_ADDRESS_LEN = 15 ;
+
+static const uint8_t P9N2_CAPP_CXA_SNP_ARRAY_READ_REG_DATA = 0 ;
+static const uint8_t P9N2_CAPP_CXA_SNP_ARRAY_READ_REG_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_CAPP_CXA_SNP_ARRAY_WRITE_REG_DATA = 0 ;
+static const uint8_t P9N2_CAPP_CXA_SNP_ARRAY_WRITE_REG_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_CAPP_CXA_SNP_CAPI_CFG_REG_ENABLE_TTYPE_DECODE = 0 ;
+static const uint8_t P9N2_CAPP_CXA_SNP_CAPI_CFG_REG_PRECISE_DIR_SIZE = 2 ;
+static const uint8_t P9N2_CAPP_CXA_SNP_CAPI_CFG_REG_PRECISE_DIR_SIZE_LEN = 2 ;
+static const uint8_t P9N2_CAPP_CXA_SNP_CAPI_CFG_REG_MCD_CHICKEN_SWITCH = 6 ;
+static const uint8_t P9N2_CAPP_CXA_SNP_CAPI_CFG_REG_BHR_DIR_STATE = 7 ;
+static const uint8_t P9N2_CAPP_CXA_SNP_CAPI_CFG_REG_BHR_DIR_STATE_LEN = 5 ;
+static const uint8_t P9N2_CAPP_CXA_SNP_CAPI_CFG_REG_LPC_MODE = 12 ;
+static const uint8_t P9N2_CAPP_CXA_SNP_CAPI_CFG_REG_LPC_MODE_LEN = 2 ;
+static const uint8_t P9N2_CAPP_CXA_SNP_CAPI_CFG_REG_CT_COMPARE_VECTOR = 32 ;
+static const uint8_t P9N2_CAPP_CXA_SNP_CAPI_CFG_REG_CT_COMPARE_VECTOR_LEN = 6 ;
+static const uint8_t P9N2_CAPP_CXA_SNP_CAPI_CFG_REG_EPOCH_TEST_VECTOR = 40 ;
+static const uint8_t P9N2_CAPP_CXA_SNP_CAPI_CFG_REG_EPOCH_TEST_VECTOR_LEN = 24 ;
+
+static const uint8_t P9N2_CAPP_CXA_SNP_CNTL_REG_READ_EPSILON_MODE = 0 ;
+static const uint8_t P9N2_CAPP_CXA_SNP_CNTL_REG_READ_EPSILON_TIER0 = 3 ;
+static const uint8_t P9N2_CAPP_CXA_SNP_CNTL_REG_READ_EPSILON_TIER0_LEN = 9 ;
+static const uint8_t P9N2_CAPP_CXA_SNP_CNTL_REG_READ_EPSILON_TIER1 = 15 ;
+static const uint8_t P9N2_CAPP_CXA_SNP_CNTL_REG_READ_EPSILON_TIER1_LEN = 9 ;
+static const uint8_t P9N2_CAPP_CXA_SNP_CNTL_REG_READ_EPSILON_TIER2 = 25 ;
+static const uint8_t P9N2_CAPP_CXA_SNP_CNTL_REG_READ_EPSILON_TIER2_LEN = 11 ;
+static const uint8_t P9N2_CAPP_CXA_SNP_CNTL_REG_ADDRESS_PIPELINE_MASTERWAIT_COUNT = 45 ;
+static const uint8_t P9N2_CAPP_CXA_SNP_CNTL_REG_ADDRESS_PIPELINE_MASTERWAIT_COUNT_LEN = 3 ;
+static const uint8_t P9N2_CAPP_CXA_SNP_CNTL_REG_DATA_HANG_POLL_SCALE = 48 ;
+static const uint8_t P9N2_CAPP_CXA_SNP_CNTL_REG_DATA_HANG_POLL_SCALE_LEN = 4 ;
+
+static const uint8_t P9N2_CAPP_CXA_SNP_ERROR_REPORT_REG_C_ERR_RPT_HOLD_DATA = 0 ;
+static const uint8_t P9N2_CAPP_CXA_SNP_ERROR_REPORT_REG_C_ERR_RPT_HOLD_DATA_LEN = 32 ;
+
+static const uint8_t P9N2_CAPP_CXA_SNP_PHB_TTAG_FILTER_REG_FILTER = 0 ;
+static const uint8_t P9N2_CAPP_CXA_SNP_PHB_TTAG_FILTER_REG_FILTER_LEN = 48 ;
+
+static const uint8_t P9N2_CAPP_CXA_SNP_PMU_EVENTS_SELECT_REG_GROUP = 0 ;
+static const uint8_t P9N2_CAPP_CXA_SNP_PMU_EVENTS_SELECT_REG_GROUP_LEN = 4 ;
+static const uint8_t P9N2_CAPP_CXA_SNP_PMU_EVENTS_SELECT_REG_FSMJ_EVENT = 6 ;
+static const uint8_t P9N2_CAPP_CXA_SNP_PMU_EVENTS_SELECT_REG_FSMJ_EVENT_LEN = 6 ;
+static const uint8_t P9N2_CAPP_CXA_SNP_PMU_EVENTS_SELECT_REG_FSMJ_FSM = 14 ;
+static const uint8_t P9N2_CAPP_CXA_SNP_PMU_EVENTS_SELECT_REG_FSMJ_FSM_LEN = 6 ;
+
+static const uint8_t P9N2_CAPP_CXA_TRIGCTL_PORTSEL = 0 ;
+static const uint8_t P9N2_CAPP_CXA_TRIGCTL_PORTSEL_LEN = 4 ;
+static const uint8_t P9N2_CAPP_CXA_TRIGCTL_APC0_ENABLE = 4 ;
+static const uint8_t P9N2_CAPP_CXA_TRIGCTL_APC1_ENABLE = 5 ;
+static const uint8_t P9N2_CAPP_CXA_TRIGCTL_SNPFE_TRIGGER_ENABLE = 6 ;
+static const uint8_t P9N2_CAPP_CXA_TRIGCTL_SNPFE_DIR_TRIGGER_ENABLE = 7 ;
+static const uint8_t P9N2_CAPP_CXA_TRIGCTL_SNPBE_TRIGGER_ENABLE = 8 ;
+static const uint8_t P9N2_CAPP_CXA_TRIGCTL_SNPBE_UOP_TRIGGER_ENABLE = 9 ;
+static const uint8_t P9N2_CAPP_CXA_TRIGCTL_TLBI_TRIGGER_SEL = 10 ;
+static const uint8_t P9N2_CAPP_CXA_TRIGCTL_XPT_TRIGGER_SEL = 11 ;
+static const uint8_t P9N2_CAPP_CXA_TRIGCTL_SNP_MUX_PORT_SEL = 12 ;
+static const uint8_t P9N2_CAPP_CXA_TRIGCTL_SNP_MUX_PORT_SEL_LEN = 4 ;
+static const uint8_t P9N2_CAPP_CXA_TRIGCTL_XPT_MUX_PORT_SEL = 16 ;
+static const uint8_t P9N2_CAPP_CXA_TRIGCTL_XPT_MUX_PORT_SEL_LEN = 4 ;
+
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_TL_CRD_OVF = 0 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_ACTAG_IDX = 1 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_ACTAG_INV = 2 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_OPC_RSVD = 3 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RTC_POS = 4 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_TMPL = 5 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_TMPL_UNS = 6 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_TMPL_X00 = 7 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CTLFLIT_OVERRUN = 8 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_UNEXPECTED_DATA_FLIT = 9 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_LINK_DOWN = 10 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_BAD_DATA_RECEIVED_CMD = 11 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_BAD_DATA_RECEIVED_RESP = 12 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RESPONSE_NOT_ALLOWED = 13 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_MISC_PERR = 14 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_TXO_PERR = 15 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_PERR_FRMD = 16 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_PERR_FRMC = 17 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_TXO_CBUF_CE = 18 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_TXO_CBUF_UE = 19 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_TXI_DBUF_CE = 20 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_TXI_DBUF_UE = 21 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CDFIFO_LO_CE = 22 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CDFIFO_LO_UE = 23 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CDFIFO_HI_CE = 24 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CDFIFO_HI_UE = 25 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RDFIFO_LO_CE = 26 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RDFIFO_LO_UE = 27 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RDFIFO_HI_CE = 28 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RDFIFO_HI_UE = 29 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CFIFO0_LO_CE = 30 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CFIFO0_LO_UE = 31 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CFIFO0_HI_CE = 32 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CFIFO0_HI_UE = 33 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CFIFO1_CE = 34 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CFIFO1_UE = 35 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RFIFO_CE = 36 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RFIFO_UE = 37 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_ACTAG_CE = 38 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_ACTAG_UE = 39 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_SBE11 = 40 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_UE11 = 41 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_SBE12 = 42 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_UE12 = 43 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_SBE2 = 44 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_UE2 = 45 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_ILLEGAL_BDF_PASID_ERROR = 46 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_BAD_PE_HANDLE_ERROR = 47 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_OPCODE_VIOLATION_ERROR = 48 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_0B_WR_VIOLATION_ERROR = 49 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_PL_VIOLATION_INTRP_REQ_D = 50 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_HASHCAM_DECR_ERROR = 51 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_HASHCAM_OVERFLOW_ERROR = 52 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_HASHCAM_UNDERFLOW_ERROR = 53 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_CMD_ARRAY_OVERFLOW = 54 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_CMD2_52_ERROR = 55 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_DAT_ARY_CE = 56 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_DAT_ARY_UE = 57 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CFIFO_OVERRUN = 58 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RFIFO_OVERRUN = 59 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CDFIFO_OVERRUN = 60 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RDFIFO_OVERRUN = 61 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_DRL_RANGE = 62 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_PKTFIELDRSVDVAL_DLEQ0 = 63 ;
+
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_TL_CRD_OVF = 0 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_ACTAG_IDX = 1 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_ACTAG_INV = 2 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_OPC_RSVD = 3 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RTC_POS = 4 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_TMPL = 5 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_TMPL_UNS = 6 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_TMPL_X00 = 7 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CTLFLIT_OVERRUN = 8 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_UNEXPECTED_DATA_FLIT = 9 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_LINK_DOWN = 10 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_BAD_DATA_RECEIVED_CMD = 11 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_BAD_DATA_RECEIVED_RESP = 12 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RESPONSE_NOT_ALLOWED = 13 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_MISC_PERR = 14 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_TXO_PERR = 15 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_PERR_FRMD = 16 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_PERR_FRMC = 17 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_TXO_CBUF_CE = 18 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_TXO_CBUF_UE = 19 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_TXI_DBUF_CE = 20 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_TXI_DBUF_UE = 21 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CDFIFO_LO_CE = 22 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CDFIFO_LO_UE = 23 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CDFIFO_HI_CE = 24 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CDFIFO_HI_UE = 25 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RDFIFO_LO_CE = 26 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RDFIFO_LO_UE = 27 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RDFIFO_HI_CE = 28 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RDFIFO_HI_UE = 29 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CFIFO0_LO_CE = 30 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CFIFO0_LO_UE = 31 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CFIFO0_HI_CE = 32 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CFIFO0_HI_UE = 33 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CFIFO1_CE = 34 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CFIFO1_UE = 35 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RFIFO_CE = 36 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RFIFO_UE = 37 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_ACTAG_CE = 38 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_ACTAG_UE = 39 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_SBE11 = 40 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_UE11 = 41 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_SBE12 = 42 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_UE12 = 43 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_SBE2 = 44 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_UE2 = 45 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_ILLEGAL_BDF_PASID_ERROR = 46 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_BAD_PE_HANDLE_ERROR = 47 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_OPCODE_VIOLATION_ERROR = 48 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_0B_WR_VIOLATION_ERROR = 49 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_PL_VIOLATION_INTRP_REQ_D = 50 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_HASHCAM_DECR_ERROR = 51 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_HASHCAM_OVERFLOW_ERROR = 52 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_HASHCAM_UNDERFLOW_ERROR = 53 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_CMD_ARRAY_OVERFLOW = 54 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_CMD2_52_ERROR = 55 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_DAT_ARY_CE = 56 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_DAT_ARY_UE = 57 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CFIFO_OVERRUN = 58 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RFIFO_OVERRUN = 59 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CDFIFO_OVERRUN = 60 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RDFIFO_OVERRUN = 61 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_DRL_RANGE = 62 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_PKTFIELDRSVDVAL_DLEQ0 = 63 ;
+
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_TL_CRD_OVF = 0 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_ACTAG_IDX = 1 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_ACTAG_INV = 2 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_OPC_RSVD = 3 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RTC_POS = 4 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_TMPL = 5 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_TMPL_UNS = 6 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_TMPL_X00 = 7 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CTLFLIT_OVERRUN = 8 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_UNEXPECTED_DATA_FLIT = 9 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_LINK_DOWN = 10 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_BAD_DATA_RECEIVED_CMD = 11 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_BAD_DATA_RECEIVED_RESP = 12 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RESPONSE_NOT_ALLOWED = 13 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_MISC_PERR = 14 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_TXO_PERR = 15 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_PERR_FRMD = 16 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_PERR_FRMC = 17 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_TXO_CBUF_CE = 18 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_TXO_CBUF_UE = 19 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_TXI_DBUF_CE = 20 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_TXI_DBUF_UE = 21 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CDFIFO_LO_CE = 22 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CDFIFO_LO_UE = 23 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CDFIFO_HI_CE = 24 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CDFIFO_HI_UE = 25 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RDFIFO_LO_CE = 26 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RDFIFO_LO_UE = 27 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RDFIFO_HI_CE = 28 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RDFIFO_HI_UE = 29 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CFIFO0_LO_CE = 30 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CFIFO0_LO_UE = 31 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CFIFO0_HI_CE = 32 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CFIFO0_HI_UE = 33 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CFIFO1_CE = 34 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CFIFO1_UE = 35 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RFIFO_CE = 36 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RFIFO_UE = 37 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_ACTAG_CE = 38 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_ACTAG_UE = 39 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_SBE11 = 40 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_UE11 = 41 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_SBE12 = 42 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_UE12 = 43 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_SBE2 = 44 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_UE2 = 45 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_ILLEGAL_BDF_PASID_ERROR = 46 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_BAD_PE_HANDLE_ERROR = 47 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_OPCODE_VIOLATION_ERROR = 48 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_0B_WR_VIOLATION_ERROR = 49 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_PL_VIOLATION_INTRP_REQ_D = 50 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_HASHCAM_DECR_ERROR = 51 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_HASHCAM_OVERFLOW_ERROR = 52 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_HASHCAM_UNDERFLOW_ERROR = 53 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_CMD_ARRAY_OVERFLOW = 54 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_CMD2_52_ERROR = 55 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_DAT_ARY_CE = 56 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_DAT_ARY_UE = 57 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CFIFO_OVERRUN = 58 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RFIFO_OVERRUN = 59 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CDFIFO_OVERRUN = 60 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RDFIFO_OVERRUN = 61 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_DRL_RANGE = 62 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_PKTFIELDRSVDVAL_DLEQ0 = 63 ;
+
+static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_TL_CRD_OVF = 0 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_ACTAG_IDX = 1 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_ACTAG_INV = 2 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_OPC_RSVD = 3 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RTC_POS = 4 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_TMPL = 5 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_TMPL_UNS = 6 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_TMPL_X00 = 7 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CTLFLIT_OVERRUN = 8 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_UNEXPECTED_DATA_FLIT = 9 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_LINK_DOWN = 10 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_BAD_DATA_RECEIVED_CMD = 11 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_BAD_DATA_RECEIVED_RESP = 12 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RESPONSE_NOT_ALLOWED = 13 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_MISC_PERR = 14 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_TXO_PERR = 15 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_PERR_FRMD = 16 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_PERR_FRMC = 17 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_TXO_CBUF_CE = 18 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_TXO_CBUF_UE = 19 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_TXI_DBUF_CE = 20 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_TXI_DBUF_UE = 21 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CDFIFO_LO_CE = 22 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CDFIFO_LO_UE = 23 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CDFIFO_HI_CE = 24 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CDFIFO_HI_UE = 25 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RDFIFO_LO_CE = 26 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RDFIFO_LO_UE = 27 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RDFIFO_HI_CE = 28 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RDFIFO_HI_UE = 29 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CFIFO0_LO_CE = 30 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CFIFO0_LO_UE = 31 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CFIFO0_HI_CE = 32 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CFIFO0_HI_UE = 33 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CFIFO1_CE = 34 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CFIFO1_UE = 35 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RFIFO_CE = 36 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RFIFO_UE = 37 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_ACTAG_CE = 38 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_ACTAG_UE = 39 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_SBE11 = 40 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_UE11 = 41 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_SBE12 = 42 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_UE12 = 43 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_SBE2 = 44 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_UE2 = 45 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_ILLEGAL_BDF_PASID_ERROR = 46 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_BAD_PE_HANDLE_ERROR = 47 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_OPCODE_VIOLATION_ERROR = 48 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_0B_WR_VIOLATION_ERROR = 49 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_PL_VIOLATION_INTRP_REQ_D = 50 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_HASHCAM_DECR_ERROR = 51 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_HASHCAM_OVERFLOW_ERROR = 52 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_HASHCAM_UNDERFLOW_ERROR = 53 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_CMD_ARRAY_OVERFLOW = 54 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_CMD2_52_ERROR = 55 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_DAT_ARY_CE = 56 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXO_DAT_ARY_UE = 57 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CFIFO_OVERRUN = 58 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RFIFO_OVERRUN = 59 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_CDFIFO_OVERRUN = 60 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_RDFIFO_OVERRUN = 61 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_DRL_RANGE = 62 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_HOLD0_OTL_HOLD_RXI_PKTFIELDRSVDVAL_DLEQ0 = 63 ;
+
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD1_OTL_SPARE00 = 0 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD1_OTL_SPARE01 = 1 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD1_OTL_SPARE02 = 2 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD1_OTL_SPARE03 = 3 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD1_OTL_SPARE04 = 4 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD1_OTL_SPARE05 = 5 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD1_OTL_SPARE06 = 6 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD1_OTL_SPARE07 = 7 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD1_OTL_SPARE08 = 8 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD1_OTL_SPARE09 = 9 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD1_OTL_SPARE10 = 10 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD1_OTL_SPARE11 = 11 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD1_OTL_SPARE12 = 12 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD1_OTL_SPARE13 = 13 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD1_OTL_SPARE14 = 14 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_HOLD1_OTL_SPARE15 = 15 ;
+
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD1_OTL_SPARE00 = 0 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD1_OTL_SPARE01 = 1 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD1_OTL_SPARE02 = 2 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD1_OTL_SPARE03 = 3 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD1_OTL_SPARE04 = 4 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD1_OTL_SPARE05 = 5 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD1_OTL_SPARE06 = 6 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD1_OTL_SPARE07 = 7 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD1_OTL_SPARE08 = 8 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD1_OTL_SPARE09 = 9 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD1_OTL_SPARE10 = 10 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD1_OTL_SPARE11 = 11 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD1_OTL_SPARE12 = 12 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD1_OTL_SPARE13 = 13 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD1_OTL_SPARE14 = 14 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_HOLD1_OTL_SPARE15 = 15 ;
+
+static const uint8_t P9N2__SM3_C_ERR_RPT_HOLD1_OTL_SPARE00 = 0 ;
+static const uint8_t P9N2__SM3_C_ERR_RPT_HOLD1_OTL_SPARE01 = 1 ;
+static const uint8_t P9N2__SM3_C_ERR_RPT_HOLD1_OTL_SPARE02 = 2 ;
+static const uint8_t P9N2__SM3_C_ERR_RPT_HOLD1_OTL_SPARE03 = 3 ;
+static const uint8_t P9N2__SM3_C_ERR_RPT_HOLD1_OTL_SPARE04 = 4 ;
+static const uint8_t P9N2__SM3_C_ERR_RPT_HOLD1_OTL_SPARE05 = 5 ;
+static const uint8_t P9N2__SM3_C_ERR_RPT_HOLD1_OTL_SPARE06 = 6 ;
+static const uint8_t P9N2__SM3_C_ERR_RPT_HOLD1_OTL_SPARE07 = 7 ;
+static const uint8_t P9N2__SM3_C_ERR_RPT_HOLD1_OTL_SPARE08 = 8 ;
+static const uint8_t P9N2__SM3_C_ERR_RPT_HOLD1_OTL_SPARE09 = 9 ;
+static const uint8_t P9N2__SM3_C_ERR_RPT_HOLD1_OTL_SPARE10 = 10 ;
+static const uint8_t P9N2__SM3_C_ERR_RPT_HOLD1_OTL_SPARE11 = 11 ;
+static const uint8_t P9N2__SM3_C_ERR_RPT_HOLD1_OTL_SPARE12 = 12 ;
+static const uint8_t P9N2__SM3_C_ERR_RPT_HOLD1_OTL_SPARE13 = 13 ;
+static const uint8_t P9N2__SM3_C_ERR_RPT_HOLD1_OTL_SPARE14 = 14 ;
+static const uint8_t P9N2__SM3_C_ERR_RPT_HOLD1_OTL_SPARE15 = 15 ;
+
+static const uint8_t P9N2_PU_NPU_SM3_C_ERR_RPT_HOLD1_OTL_SPARE00 = 0 ;
+static const uint8_t P9N2_PU_NPU_SM3_C_ERR_RPT_HOLD1_OTL_SPARE01 = 1 ;
+static const uint8_t P9N2_PU_NPU_SM3_C_ERR_RPT_HOLD1_OTL_SPARE02 = 2 ;
+static const uint8_t P9N2_PU_NPU_SM3_C_ERR_RPT_HOLD1_OTL_SPARE03 = 3 ;
+static const uint8_t P9N2_PU_NPU_SM3_C_ERR_RPT_HOLD1_OTL_SPARE04 = 4 ;
+static const uint8_t P9N2_PU_NPU_SM3_C_ERR_RPT_HOLD1_OTL_SPARE05 = 5 ;
+static const uint8_t P9N2_PU_NPU_SM3_C_ERR_RPT_HOLD1_OTL_SPARE06 = 6 ;
+static const uint8_t P9N2_PU_NPU_SM3_C_ERR_RPT_HOLD1_OTL_SPARE07 = 7 ;
+static const uint8_t P9N2_PU_NPU_SM3_C_ERR_RPT_HOLD1_OTL_SPARE08 = 8 ;
+static const uint8_t P9N2_PU_NPU_SM3_C_ERR_RPT_HOLD1_OTL_SPARE09 = 9 ;
+static const uint8_t P9N2_PU_NPU_SM3_C_ERR_RPT_HOLD1_OTL_SPARE10 = 10 ;
+static const uint8_t P9N2_PU_NPU_SM3_C_ERR_RPT_HOLD1_OTL_SPARE11 = 11 ;
+static const uint8_t P9N2_PU_NPU_SM3_C_ERR_RPT_HOLD1_OTL_SPARE12 = 12 ;
+static const uint8_t P9N2_PU_NPU_SM3_C_ERR_RPT_HOLD1_OTL_SPARE13 = 13 ;
+static const uint8_t P9N2_PU_NPU_SM3_C_ERR_RPT_HOLD1_OTL_SPARE14 = 14 ;
+static const uint8_t P9N2_PU_NPU_SM3_C_ERR_RPT_HOLD1_OTL_SPARE15 = 15 ;
+
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK000 = 0 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK001 = 1 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK002 = 2 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK003 = 3 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK004 = 4 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK005 = 5 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK006 = 6 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK007 = 7 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK008 = 8 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK009 = 9 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK010 = 10 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK011 = 11 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK012 = 12 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK013 = 13 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK014 = 14 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK015 = 15 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK016 = 16 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK017 = 17 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK018 = 18 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK019 = 19 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK020 = 20 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK021 = 21 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK022 = 22 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK023 = 23 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK024 = 24 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK025 = 25 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK026 = 26 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK027 = 27 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK028 = 28 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK029 = 29 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK030 = 30 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK031 = 31 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK032 = 32 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK033 = 33 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK034 = 34 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK035 = 35 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK036 = 36 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK037 = 37 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK038 = 38 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK039 = 39 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK040 = 40 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK041 = 41 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK042 = 42 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK043 = 43 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK044 = 44 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK045 = 45 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK046 = 46 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK047 = 47 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK048 = 48 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK049 = 49 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK050 = 50 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK051 = 51 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK052 = 52 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK053 = 53 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK054 = 54 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK055 = 55 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK056 = 56 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK057 = 57 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK058 = 58 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK059 = 59 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK060 = 60 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK061 = 61 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK062 = 62 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK0_OTL_MASK063 = 63 ;
+
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK000 = 0 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK001 = 1 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK002 = 2 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK003 = 3 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK004 = 4 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK005 = 5 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK006 = 6 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK007 = 7 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK008 = 8 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK009 = 9 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK010 = 10 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK011 = 11 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK012 = 12 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK013 = 13 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK014 = 14 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK015 = 15 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK016 = 16 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK017 = 17 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK018 = 18 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK019 = 19 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK020 = 20 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK021 = 21 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK022 = 22 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK023 = 23 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK024 = 24 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK025 = 25 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK026 = 26 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK027 = 27 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK028 = 28 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK029 = 29 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK030 = 30 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK031 = 31 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK032 = 32 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK033 = 33 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK034 = 34 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK035 = 35 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK036 = 36 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK037 = 37 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK038 = 38 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK039 = 39 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK040 = 40 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK041 = 41 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK042 = 42 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK043 = 43 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK044 = 44 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK045 = 45 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK046 = 46 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK047 = 47 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK048 = 48 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK049 = 49 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK050 = 50 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK051 = 51 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK052 = 52 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK053 = 53 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK054 = 54 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK055 = 55 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK056 = 56 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK057 = 57 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK058 = 58 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK059 = 59 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK060 = 60 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK061 = 61 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK062 = 62 ;
+static const uint8_t P9N2_PU_NPU_SM2_C_ERR_RPT_MASK0_OTL_MASK063 = 63 ;
+
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK000 = 0 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK001 = 1 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK002 = 2 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK003 = 3 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK004 = 4 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK005 = 5 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK006 = 6 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK007 = 7 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK008 = 8 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK009 = 9 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK010 = 10 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK011 = 11 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK012 = 12 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK013 = 13 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK014 = 14 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK015 = 15 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK016 = 16 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK017 = 17 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK018 = 18 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK019 = 19 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK020 = 20 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK021 = 21 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK022 = 22 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK023 = 23 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK024 = 24 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK025 = 25 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK026 = 26 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK027 = 27 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK028 = 28 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK029 = 29 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK030 = 30 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK031 = 31 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK032 = 32 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK033 = 33 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK034 = 34 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK035 = 35 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK036 = 36 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK037 = 37 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK038 = 38 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK039 = 39 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK040 = 40 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK041 = 41 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK042 = 42 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK043 = 43 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK044 = 44 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK045 = 45 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK046 = 46 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK047 = 47 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK048 = 48 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK049 = 49 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK050 = 50 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK051 = 51 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK052 = 52 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK053 = 53 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK054 = 54 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK055 = 55 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK056 = 56 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK057 = 57 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK058 = 58 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK059 = 59 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK060 = 60 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK061 = 61 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK062 = 62 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK0_OTL_MASK063 = 63 ;
+
+static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK000 = 0 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK001 = 1 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK002 = 2 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK003 = 3 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK004 = 4 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK005 = 5 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK006 = 6 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK007 = 7 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK008 = 8 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK009 = 9 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK010 = 10 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK011 = 11 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK012 = 12 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK013 = 13 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK014 = 14 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK015 = 15 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK016 = 16 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK017 = 17 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK018 = 18 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK019 = 19 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK020 = 20 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK021 = 21 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK022 = 22 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK023 = 23 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK024 = 24 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK025 = 25 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK026 = 26 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK027 = 27 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK028 = 28 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK029 = 29 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK030 = 30 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK031 = 31 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK032 = 32 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK033 = 33 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK034 = 34 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK035 = 35 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK036 = 36 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK037 = 37 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK038 = 38 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK039 = 39 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK040 = 40 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK041 = 41 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK042 = 42 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK043 = 43 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK044 = 44 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK045 = 45 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK046 = 46 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK047 = 47 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK048 = 48 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK049 = 49 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK050 = 50 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK051 = 51 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK052 = 52 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK053 = 53 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK054 = 54 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK055 = 55 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK056 = 56 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK057 = 57 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK058 = 58 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK059 = 59 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK060 = 60 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK061 = 61 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK062 = 62 ;
+static const uint8_t P9N2__SM2_C_ERR_RPT_MASK0_OTL_MASK063 = 63 ;
+
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK1_OTL_MASK100 = 0 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK1_OTL_MASK101 = 1 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK1_OTL_MASK102 = 2 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK1_OTL_MASK103 = 3 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK1_OTL_MASK104 = 4 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK1_OTL_MASK105 = 5 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK1_OTL_MASK106 = 6 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK1_OTL_MASK107 = 7 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK1_OTL_MASK108 = 8 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK1_OTL_MASK109 = 9 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK1_OTL_MASK110 = 10 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK1_OTL_MASK111 = 11 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK1_OTL_MASK112 = 12 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK1_OTL_MASK113 = 13 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK1_OTL_MASK114 = 14 ;
+static const uint8_t P9N2_PU_NPU_CTL_C_ERR_RPT_MASK1_OTL_MASK115 = 15 ;
+
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK1_OTL_MASK100 = 0 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK1_OTL_MASK101 = 1 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK1_OTL_MASK102 = 2 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK1_OTL_MASK103 = 3 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK1_OTL_MASK104 = 4 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK1_OTL_MASK105 = 5 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK1_OTL_MASK106 = 6 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK1_OTL_MASK107 = 7 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK1_OTL_MASK108 = 8 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK1_OTL_MASK109 = 9 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK1_OTL_MASK110 = 10 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK1_OTL_MASK111 = 11 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK1_OTL_MASK112 = 12 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK1_OTL_MASK113 = 13 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK1_OTL_MASK114 = 14 ;
+static const uint8_t P9N2__CTL_C_ERR_RPT_MASK1_OTL_MASK115 = 15 ;
+
+static const uint8_t P9N2__SM3_C_ERR_RPT_MASK1_OTL_MASK100 = 0 ;
+static const uint8_t P9N2__SM3_C_ERR_RPT_MASK1_OTL_MASK101 = 1 ;
+static const uint8_t P9N2__SM3_C_ERR_RPT_MASK1_OTL_MASK102 = 2 ;
+static const uint8_t P9N2__SM3_C_ERR_RPT_MASK1_OTL_MASK103 = 3 ;
+static const uint8_t P9N2__SM3_C_ERR_RPT_MASK1_OTL_MASK104 = 4 ;
+static const uint8_t P9N2__SM3_C_ERR_RPT_MASK1_OTL_MASK105 = 5 ;
+static const uint8_t P9N2__SM3_C_ERR_RPT_MASK1_OTL_MASK106 = 6 ;
+static const uint8_t P9N2__SM3_C_ERR_RPT_MASK1_OTL_MASK107 = 7 ;
+static const uint8_t P9N2__SM3_C_ERR_RPT_MASK1_OTL_MASK108 = 8 ;
+static const uint8_t P9N2__SM3_C_ERR_RPT_MASK1_OTL_MASK109 = 9 ;
+static const uint8_t P9N2__SM3_C_ERR_RPT_MASK1_OTL_MASK110 = 10 ;
+static const uint8_t P9N2__SM3_C_ERR_RPT_MASK1_OTL_MASK111 = 11 ;
+static const uint8_t P9N2__SM3_C_ERR_RPT_MASK1_OTL_MASK112 = 12 ;
+static const uint8_t P9N2__SM3_C_ERR_RPT_MASK1_OTL_MASK113 = 13 ;
+static const uint8_t P9N2__SM3_C_ERR_RPT_MASK1_OTL_MASK114 = 14 ;
+static const uint8_t P9N2__SM3_C_ERR_RPT_MASK1_OTL_MASK115 = 15 ;
+
+static const uint8_t P9N2_PU_NPU_SM3_C_ERR_RPT_MASK1_OTL_MASK100 = 0 ;
+static const uint8_t P9N2_PU_NPU_SM3_C_ERR_RPT_MASK1_OTL_MASK101 = 1 ;
+static const uint8_t P9N2_PU_NPU_SM3_C_ERR_RPT_MASK1_OTL_MASK102 = 2 ;
+static const uint8_t P9N2_PU_NPU_SM3_C_ERR_RPT_MASK1_OTL_MASK103 = 3 ;
+static const uint8_t P9N2_PU_NPU_SM3_C_ERR_RPT_MASK1_OTL_MASK104 = 4 ;
+static const uint8_t P9N2_PU_NPU_SM3_C_ERR_RPT_MASK1_OTL_MASK105 = 5 ;
+static const uint8_t P9N2_PU_NPU_SM3_C_ERR_RPT_MASK1_OTL_MASK106 = 6 ;
+static const uint8_t P9N2_PU_NPU_SM3_C_ERR_RPT_MASK1_OTL_MASK107 = 7 ;
+static const uint8_t P9N2_PU_NPU_SM3_C_ERR_RPT_MASK1_OTL_MASK108 = 8 ;
+static const uint8_t P9N2_PU_NPU_SM3_C_ERR_RPT_MASK1_OTL_MASK109 = 9 ;
+static const uint8_t P9N2_PU_NPU_SM3_C_ERR_RPT_MASK1_OTL_MASK110 = 10 ;
+static const uint8_t P9N2_PU_NPU_SM3_C_ERR_RPT_MASK1_OTL_MASK111 = 11 ;
+static const uint8_t P9N2_PU_NPU_SM3_C_ERR_RPT_MASK1_OTL_MASK112 = 12 ;
+static const uint8_t P9N2_PU_NPU_SM3_C_ERR_RPT_MASK1_OTL_MASK113 = 13 ;
+static const uint8_t P9N2_PU_NPU_SM3_C_ERR_RPT_MASK1_OTL_MASK114 = 14 ;
+static const uint8_t P9N2_PU_NPU_SM3_C_ERR_RPT_MASK1_OTL_MASK115 = 15 ;
+
+static const uint8_t P9N2_PU_DATA0TO7_REGISTER_B_PIB_0 = 0 ;
+static const uint8_t P9N2_PU_DATA0TO7_REGISTER_B_PIB_0_LEN = 64 ;
+
+static const uint8_t P9N2_PU_DATA0TO7_REGISTER_C_PIB_1 = 0 ;
+static const uint8_t P9N2_PU_DATA0TO7_REGISTER_C_PIB_1_LEN = 64 ;
+
+static const uint8_t P9N2_PU_DATA0TO7_REGISTER_D_PIB_2 = 0 ;
+static const uint8_t P9N2_PU_DATA0TO7_REGISTER_D_PIB_2_LEN = 64 ;
+
+static const uint8_t P9N2_PU_DATA0TO7_REGISTER_E_PIB_3 = 0 ;
+static const uint8_t P9N2_PU_DATA0TO7_REGISTER_E_PIB_3_LEN = 64 ;
+
+static const uint8_t P9N2_PU_DATA8TO15_REGISTER_B_PIB_0 = 0 ;
+static const uint8_t P9N2_PU_DATA8TO15_REGISTER_B_PIB_0_LEN = 64 ;
+
+static const uint8_t P9N2_PU_DATA8TO15_REGISTER_C_PIB_1 = 0 ;
+static const uint8_t P9N2_PU_DATA8TO15_REGISTER_C_PIB_1_LEN = 64 ;
+
+static const uint8_t P9N2_PU_DATA8TO15_REGISTER_D_PIB_2 = 0 ;
+static const uint8_t P9N2_PU_DATA8TO15_REGISTER_D_PIB_2_LEN = 64 ;
+
+static const uint8_t P9N2_PU_DATA8TO15_REGISTER_E_PIB_3 = 0 ;
+static const uint8_t P9N2_PU_DATA8TO15_REGISTER_E_PIB_3_LEN = 64 ;
+
+static const uint8_t P9N2_PU_DATATAG_0_HASH_FUNCTION_REG_FUNCTION = 0 ;
+static const uint8_t P9N2_PU_DATATAG_0_HASH_FUNCTION_REG_FUNCTION_LEN = 64 ;
+
+static const uint8_t P9N2_PU_DATATAG_1_HASH_FUNCTION_REG_FUNCTION = 0 ;
+static const uint8_t P9N2_PU_DATATAG_1_HASH_FUNCTION_REG_FUNCTION_LEN = 64 ;
+
+static const uint8_t P9N2_PU_DATATAG_2_HASH_FUNCTION_REG_FUNCTION = 0 ;
+static const uint8_t P9N2_PU_DATATAG_2_HASH_FUNCTION_REG_FUNCTION_LEN = 64 ;
+
+static const uint8_t P9N2_PU_DATATAG_3_HASH_FUNCTION_REG_FUNCTION = 0 ;
+static const uint8_t P9N2_PU_DATATAG_3_HASH_FUNCTION_REG_FUNCTION_LEN = 64 ;
+
+static const uint8_t P9N2_PU_DATATAG_4_HASH_FUNCTION_REG_FUNCTION = 0 ;
+static const uint8_t P9N2_PU_DATATAG_4_HASH_FUNCTION_REG_FUNCTION_LEN = 64 ;
+
+static const uint8_t P9N2_PU_DATATAG_5_HASH_FUNCTION_REG_FUNCTION = 0 ;
+static const uint8_t P9N2_PU_DATATAG_5_HASH_FUNCTION_REG_FUNCTION_LEN = 64 ;
+
+static const uint8_t P9N2_PU_DATA_REGISTER_OTP = 0 ;
+static const uint8_t P9N2_PU_DATA_REGISTER_OTP_LEN = 64 ;
+
+static const uint8_t P9N2__CTL_DA_ADDR_MISC = 0 ;
+static const uint8_t P9N2__CTL_DA_ADDR_MISC_LEN = 24 ;
+static const uint8_t P9N2__CTL_DA_ADDR_MISC_LENGTH = 24 ;
+static const uint8_t P9N2__CTL_DA_ADDR_MISC_LENGTH_LEN = 2 ;
+static const uint8_t P9N2__CTL_DA_ADDR_MISC_RSVD = 26 ;
+static const uint8_t P9N2__CTL_DA_ADDR_MISC_RSVD_LEN = 38 ;
+
+static const uint8_t P9N2_PEC_DBG_CBS_CC_RESET_EP = 0 ;
+static const uint8_t P9N2_PEC_DBG_CBS_CC_OPCG_IP = 1 ;
+static const uint8_t P9N2_PEC_DBG_CBS_CC_VITL_CLKOFF = 2 ;
+static const uint8_t P9N2_PEC_DBG_CBS_CC_TEST_ENABLE = 3 ;
+static const uint8_t P9N2_PEC_DBG_CBS_CC_REQ = 4 ;
+static const uint8_t P9N2_PEC_DBG_CBS_CC_CMD = 5 ;
+static const uint8_t P9N2_PEC_DBG_CBS_CC_CMD_LEN = 3 ;
+static const uint8_t P9N2_PEC_DBG_CBS_CC_STATE = 8 ;
+static const uint8_t P9N2_PEC_DBG_CBS_CC_STATE_LEN = 5 ;
+static const uint8_t P9N2_PEC_DBG_CBS_CC_SECURITY_DEBUG_MODE = 13 ;
+static const uint8_t P9N2_PEC_DBG_CBS_CC_PROTOCOL_ERROR = 14 ;
+static const uint8_t P9N2_PEC_DBG_CBS_CC_PCB_IDLE = 15 ;
+static const uint8_t P9N2_PEC_DBG_CBS_CC_CURRENT_OPCG_MODE = 16 ;
+static const uint8_t P9N2_PEC_DBG_CBS_CC_CURRENT_OPCG_MODE_LEN = 4 ;
+static const uint8_t P9N2_PEC_DBG_CBS_CC_LAST_OPCG_MODE = 20 ;
+static const uint8_t P9N2_PEC_DBG_CBS_CC_LAST_OPCG_MODE_LEN = 4 ;
+static const uint8_t P9N2_PEC_DBG_CBS_CC_PCB_ERROR = 24 ;
+static const uint8_t P9N2_PEC_DBG_CBS_CC_PARITY_ERROR = 25 ;
+static const uint8_t P9N2_PEC_DBG_CBS_CC_ERROR = 26 ;
+static const uint8_t P9N2_PEC_DBG_CBS_CC_CHIPLET_IS_ALIGNED = 27 ;
+static const uint8_t P9N2_PEC_DBG_CBS_CC_PCB_REQUEST_SINCE_RESET = 28 ;
+static const uint8_t P9N2_PEC_DBG_CBS_CC_PARANOIA_TEST_ENABLE_CHANGE = 29 ;
+static const uint8_t P9N2_PEC_DBG_CBS_CC_PARANOIA_VITL_CLKOFF_CHANGE = 30 ;
+static const uint8_t P9N2_PEC_DBG_CBS_CC_TP_TPFSI_ACK = 31 ;
+
+static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_1_COND1_SEL_A = 0 ;
+static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_1_COND1_SEL_A_LEN = 8 ;
+static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_1_COND1_SEL_B = 8 ;
+static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_1_COND1_SEL_B_LEN = 8 ;
+static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_1_COND2_SEL_A = 16 ;
+static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_1_COND2_SEL_A_LEN = 8 ;
+static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_1_COND2_SEL_B = 24 ;
+static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_1_COND2_SEL_B_LEN = 8 ;
+static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_1_C1_INAROW_MODE = 32 ;
+static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE1 = 33 ;
+static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE1 = 34 ;
+static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE1 = 35 ;
+static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_1_UNUSED = 36 ;
+static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_1_UNUSED_LEN = 3 ;
+static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_1_C2_INAROW_MODE = 39 ;
+static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE2 = 40 ;
+static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE2 = 41 ;
+static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE2 = 42 ;
+static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_1_UNUSED_2 = 43 ;
+static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_1_UNUSED_2_LEN = 3 ;
+static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_1_COND3_ENABLE_RESET = 46 ;
+static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_1_EXACT_TO_MODE = 47 ;
+static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_1_RESET_C2TIMER_ON_C1 = 48 ;
+static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_1_RESET_C3_ON_C0 = 49 ;
+static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_1_SLOW_TO_MODE = 50 ;
+static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_1_EXACT_RESET_C3_ON_TO = 51 ;
+static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_1_C1_COUNT_LT = 52 ;
+static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_1_C1_COUNT_LT_LEN = 4 ;
+static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_1_C2_COUNT_LT = 56 ;
+static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_1_C2_COUNT_LT_LEN = 4 ;
+static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_1_RESET_C3_SELECT = 60 ;
+static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_1_RESET_C3_SELECT_LEN = 3 ;
+
+static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_1_COND1_SEL_A = 0 ;
+static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_1_COND1_SEL_A_LEN = 8 ;
+static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_1_COND1_SEL_B = 8 ;
+static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_1_COND1_SEL_B_LEN = 8 ;
+static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_1_COND2_SEL_A = 16 ;
+static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_1_COND2_SEL_A_LEN = 8 ;
+static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_1_COND2_SEL_B = 24 ;
+static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_1_COND2_SEL_B_LEN = 8 ;
+static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_1_C1_INAROW_MODE = 32 ;
+static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE1 = 33 ;
+static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE1 = 34 ;
+static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE1 = 35 ;
+static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_1_UNUSED = 36 ;
+static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_1_UNUSED_LEN = 3 ;
+static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_1_C2_INAROW_MODE = 39 ;
+static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE2 = 40 ;
+static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE2 = 41 ;
+static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE2 = 42 ;
+static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_1_UNUSED_2 = 43 ;
+static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_1_UNUSED_2_LEN = 3 ;
+static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_1_COND3_ENABLE_RESET = 46 ;
+static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_1_EXACT_TO_MODE = 47 ;
+static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_1_RESET_C2TIMER_ON_C1 = 48 ;
+static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_1_RESET_C3_ON_C0 = 49 ;
+static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_1_SLOW_TO_MODE = 50 ;
+static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_1_EXACT_RESET_C3_ON_TO = 51 ;
+static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_1_C1_COUNT_LT = 52 ;
+static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_1_C1_COUNT_LT_LEN = 4 ;
+static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_1_C2_COUNT_LT = 56 ;
+static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_1_C2_COUNT_LT_LEN = 4 ;
+static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_1_RESET_C3_SELECT = 60 ;
+static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_1_RESET_C3_SELECT_LEN = 3 ;
+
+static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_1_COND1_SEL_A = 0 ;
+static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_1_COND1_SEL_A_LEN = 8 ;
+static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_1_COND1_SEL_B = 8 ;
+static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_1_COND1_SEL_B_LEN = 8 ;
+static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_1_COND2_SEL_A = 16 ;
+static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_1_COND2_SEL_A_LEN = 8 ;
+static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_1_COND2_SEL_B = 24 ;
+static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_1_COND2_SEL_B_LEN = 8 ;
+static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_1_C1_INAROW_MODE = 32 ;
+static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE1 = 33 ;
+static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE1 = 34 ;
+static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE1 = 35 ;
+static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_1_UNUSED = 36 ;
+static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_1_UNUSED_LEN = 3 ;
+static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_1_C2_INAROW_MODE = 39 ;
+static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE2 = 40 ;
+static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE2 = 41 ;
+static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE2 = 42 ;
+static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_1_UNUSED_2 = 43 ;
+static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_1_UNUSED_2_LEN = 3 ;
+static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_1_COND3_ENABLE_RESET = 46 ;
+static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_1_EXACT_TO_MODE = 47 ;
+static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_1_RESET_C2TIMER_ON_C1 = 48 ;
+static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_1_RESET_C3_ON_C0 = 49 ;
+static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_1_SLOW_TO_MODE = 50 ;
+static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_1_EXACT_RESET_C3_ON_TO = 51 ;
+static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_1_C1_COUNT_LT = 52 ;
+static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_1_C1_COUNT_LT_LEN = 4 ;
+static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_1_C2_COUNT_LT = 56 ;
+static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_1_C2_COUNT_LT_LEN = 4 ;
+static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_1_RESET_C3_SELECT = 60 ;
+static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_1_RESET_C3_SELECT_LEN = 3 ;
+
+static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_1_COND1_SEL_A = 0 ;
+static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_1_COND1_SEL_A_LEN = 8 ;
+static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_1_COND1_SEL_B = 8 ;
+static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_1_COND1_SEL_B_LEN = 8 ;
+static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_1_COND2_SEL_A = 16 ;
+static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_1_COND2_SEL_A_LEN = 8 ;
+static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_1_COND2_SEL_B = 24 ;
+static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_1_COND2_SEL_B_LEN = 8 ;
+static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_1_C1_INAROW_MODE = 32 ;
+static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE1 = 33 ;
+static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE1 = 34 ;
+static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE1 = 35 ;
+static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_1_UNUSED = 36 ;
+static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_1_UNUSED_LEN = 3 ;
+static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_1_C2_INAROW_MODE = 39 ;
+static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE2 = 40 ;
+static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE2 = 41 ;
+static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE2 = 42 ;
+static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_1_UNUSED_2 = 43 ;
+static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_1_UNUSED_2_LEN = 3 ;
+static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_1_COND3_ENABLE_RESET = 46 ;
+static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_1_EXACT_TO_MODE = 47 ;
+static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_1_RESET_C2TIMER_ON_C1 = 48 ;
+static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_1_RESET_C3_ON_C0 = 49 ;
+static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_1_SLOW_TO_MODE = 50 ;
+static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_1_EXACT_RESET_C3_ON_TO = 51 ;
+static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_1_C1_COUNT_LT = 52 ;
+static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_1_C1_COUNT_LT_LEN = 4 ;
+static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_1_C2_COUNT_LT = 56 ;
+static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_1_C2_COUNT_LT_LEN = 4 ;
+static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_1_RESET_C3_SELECT = 60 ;
+static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_1_RESET_C3_SELECT_LEN = 3 ;
+
+static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_1_COND1_SEL_A = 0 ;
+static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_1_COND1_SEL_A_LEN = 8 ;
+static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_1_COND1_SEL_B = 8 ;
+static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_1_COND1_SEL_B_LEN = 8 ;
+static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_1_COND2_SEL_A = 16 ;
+static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_1_COND2_SEL_A_LEN = 8 ;
+static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_1_COND2_SEL_B = 24 ;
+static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_1_COND2_SEL_B_LEN = 8 ;
+static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_1_C1_INAROW_MODE = 32 ;
+static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE1 = 33 ;
+static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE1 = 34 ;
+static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE1 = 35 ;
+static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_1_UNUSED = 36 ;
+static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_1_UNUSED_LEN = 3 ;
+static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_1_C2_INAROW_MODE = 39 ;
+static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE2 = 40 ;
+static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE2 = 41 ;
+static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE2 = 42 ;
+static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_1_UNUSED_2 = 43 ;
+static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_1_UNUSED_2_LEN = 3 ;
+static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_1_COND3_ENABLE_RESET = 46 ;
+static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_1_EXACT_TO_MODE = 47 ;
+static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_1_RESET_C2TIMER_ON_C1 = 48 ;
+static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_1_RESET_C3_ON_C0 = 49 ;
+static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_1_SLOW_TO_MODE = 50 ;
+static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_1_EXACT_RESET_C3_ON_TO = 51 ;
+static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_1_C1_COUNT_LT = 52 ;
+static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_1_C1_COUNT_LT_LEN = 4 ;
+static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_1_C2_COUNT_LT = 56 ;
+static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_1_C2_COUNT_LT_LEN = 4 ;
+static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_1_RESET_C3_SELECT = 60 ;
+static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_1_RESET_C3_SELECT_LEN = 3 ;
+
+static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A = 0 ;
+static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN = 5 ;
+static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B = 5 ;
+static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN = 5 ;
+static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A = 10 ;
+static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN = 5 ;
+static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B = 15 ;
+static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN = 5 ;
+static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_2_TO_CMP_LT = 20 ;
+static const uint8_t P9N2_PU_N3_DBG_INST1_COND_REG_2_TO_CMP_LT_LEN = 24 ;
+
+static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A = 0 ;
+static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN = 5 ;
+static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B = 5 ;
+static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN = 5 ;
+static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A = 10 ;
+static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN = 5 ;
+static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B = 15 ;
+static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN = 5 ;
+static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_2_TO_CMP_LT = 20 ;
+static const uint8_t P9N2_PU_N1_DBG_INST1_COND_REG_2_TO_CMP_LT_LEN = 24 ;
+
+static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A = 0 ;
+static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN = 5 ;
+static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B = 5 ;
+static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN = 5 ;
+static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A = 10 ;
+static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN = 5 ;
+static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B = 15 ;
+static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN = 5 ;
+static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_2_TO_CMP_LT = 20 ;
+static const uint8_t P9N2_PU_N2_DBG_INST1_COND_REG_2_TO_CMP_LT_LEN = 24 ;
+
+static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A = 0 ;
+static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN = 5 ;
+static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B = 5 ;
+static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN = 5 ;
+static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A = 10 ;
+static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN = 5 ;
+static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B = 15 ;
+static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN = 5 ;
+static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_2_TO_CMP_LT = 20 ;
+static const uint8_t P9N2_PEC_DBG_INST1_COND_REG_2_TO_CMP_LT_LEN = 24 ;
+
+static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A = 0 ;
+static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN = 5 ;
+static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B = 5 ;
+static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN = 5 ;
+static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A = 10 ;
+static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN = 5 ;
+static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B = 15 ;
+static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN = 5 ;
+static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_2_TO_CMP_LT = 20 ;
+static const uint8_t P9N2_PU_N0_DBG_INST1_COND_REG_2_TO_CMP_LT_LEN = 24 ;
+
+static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_1_COND1_SEL_A = 0 ;
+static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_1_COND1_SEL_A_LEN = 8 ;
+static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_1_COND1_SEL_B = 8 ;
+static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_1_COND1_SEL_B_LEN = 8 ;
+static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_1_COND2_SEL_A = 16 ;
+static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_1_COND2_SEL_A_LEN = 8 ;
+static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_1_COND2_SEL_B = 24 ;
+static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_1_COND2_SEL_B_LEN = 8 ;
+static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_1_C1_INAROW_MODE = 32 ;
+static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE1 = 33 ;
+static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE1 = 34 ;
+static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE1 = 35 ;
+static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_1_UNUSED = 36 ;
+static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_1_UNUSED_LEN = 3 ;
+static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_1_C2_INAROW_MODE = 39 ;
+static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE2 = 40 ;
+static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE2 = 41 ;
+static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE2 = 42 ;
+static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_1_UNUSED_2 = 43 ;
+static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_1_UNUSED_2_LEN = 3 ;
+static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_1_COND3_ENABLE_RESET = 46 ;
+static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_1_EXACT_TO_MODE = 47 ;
+static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_1_RESET_C2TIMER_ON_C1 = 48 ;
+static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_1_RESET_C3_ON_C0 = 49 ;
+static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_1_SLOW_TO_MODE = 50 ;
+static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_1_EXACT_RESET_C3_ON_TO = 51 ;
+static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_1_C1_COUNT_LT = 52 ;
+static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_1_C1_COUNT_LT_LEN = 4 ;
+static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_1_C2_COUNT_LT = 56 ;
+static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_1_C2_COUNT_LT_LEN = 4 ;
+static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_1_RESET_C3_SELECT = 60 ;
+static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_1_RESET_C3_SELECT_LEN = 3 ;
+
+static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_1_COND1_SEL_A = 0 ;
+static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_1_COND1_SEL_A_LEN = 8 ;
+static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_1_COND1_SEL_B = 8 ;
+static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_1_COND1_SEL_B_LEN = 8 ;
+static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_1_COND2_SEL_A = 16 ;
+static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_1_COND2_SEL_A_LEN = 8 ;
+static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_1_COND2_SEL_B = 24 ;
+static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_1_COND2_SEL_B_LEN = 8 ;
+static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_1_C1_INAROW_MODE = 32 ;
+static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE1 = 33 ;
+static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE1 = 34 ;
+static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE1 = 35 ;
+static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_1_UNUSED = 36 ;
+static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_1_UNUSED_LEN = 3 ;
+static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_1_C2_INAROW_MODE = 39 ;
+static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE2 = 40 ;
+static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE2 = 41 ;
+static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE2 = 42 ;
+static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_1_UNUSED_2 = 43 ;
+static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_1_UNUSED_2_LEN = 3 ;
+static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_1_COND3_ENABLE_RESET = 46 ;
+static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_1_EXACT_TO_MODE = 47 ;
+static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_1_RESET_C2TIMER_ON_C1 = 48 ;
+static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_1_RESET_C3_ON_C0 = 49 ;
+static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_1_SLOW_TO_MODE = 50 ;
+static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_1_EXACT_RESET_C3_ON_TO = 51 ;
+static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_1_C1_COUNT_LT = 52 ;
+static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_1_C1_COUNT_LT_LEN = 4 ;
+static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_1_C2_COUNT_LT = 56 ;
+static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_1_C2_COUNT_LT_LEN = 4 ;
+static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_1_RESET_C3_SELECT = 60 ;
+static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_1_RESET_C3_SELECT_LEN = 3 ;
+
+static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_1_COND1_SEL_A = 0 ;
+static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_1_COND1_SEL_A_LEN = 8 ;
+static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_1_COND1_SEL_B = 8 ;
+static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_1_COND1_SEL_B_LEN = 8 ;
+static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_1_COND2_SEL_A = 16 ;
+static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_1_COND2_SEL_A_LEN = 8 ;
+static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_1_COND2_SEL_B = 24 ;
+static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_1_COND2_SEL_B_LEN = 8 ;
+static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_1_C1_INAROW_MODE = 32 ;
+static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE1 = 33 ;
+static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE1 = 34 ;
+static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE1 = 35 ;
+static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_1_UNUSED = 36 ;
+static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_1_UNUSED_LEN = 3 ;
+static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_1_C2_INAROW_MODE = 39 ;
+static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE2 = 40 ;
+static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE2 = 41 ;
+static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE2 = 42 ;
+static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_1_UNUSED_2 = 43 ;
+static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_1_UNUSED_2_LEN = 3 ;
+static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_1_COND3_ENABLE_RESET = 46 ;
+static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_1_EXACT_TO_MODE = 47 ;
+static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_1_RESET_C2TIMER_ON_C1 = 48 ;
+static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_1_RESET_C3_ON_C0 = 49 ;
+static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_1_SLOW_TO_MODE = 50 ;
+static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_1_EXACT_RESET_C3_ON_TO = 51 ;
+static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_1_C1_COUNT_LT = 52 ;
+static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_1_C1_COUNT_LT_LEN = 4 ;
+static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_1_C2_COUNT_LT = 56 ;
+static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_1_C2_COUNT_LT_LEN = 4 ;
+static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_1_RESET_C3_SELECT = 60 ;
+static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_1_RESET_C3_SELECT_LEN = 3 ;
+
+static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_1_COND1_SEL_A = 0 ;
+static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_1_COND1_SEL_A_LEN = 8 ;
+static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_1_COND1_SEL_B = 8 ;
+static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_1_COND1_SEL_B_LEN = 8 ;
+static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_1_COND2_SEL_A = 16 ;
+static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_1_COND2_SEL_A_LEN = 8 ;
+static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_1_COND2_SEL_B = 24 ;
+static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_1_COND2_SEL_B_LEN = 8 ;
+static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_1_C1_INAROW_MODE = 32 ;
+static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE1 = 33 ;
+static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE1 = 34 ;
+static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE1 = 35 ;
+static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_1_UNUSED = 36 ;
+static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_1_UNUSED_LEN = 3 ;
+static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_1_C2_INAROW_MODE = 39 ;
+static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE2 = 40 ;
+static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE2 = 41 ;
+static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE2 = 42 ;
+static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_1_UNUSED_2 = 43 ;
+static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_1_UNUSED_2_LEN = 3 ;
+static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_1_COND3_ENABLE_RESET = 46 ;
+static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_1_EXACT_TO_MODE = 47 ;
+static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_1_RESET_C2TIMER_ON_C1 = 48 ;
+static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_1_RESET_C3_ON_C0 = 49 ;
+static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_1_SLOW_TO_MODE = 50 ;
+static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_1_EXACT_RESET_C3_ON_TO = 51 ;
+static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_1_C1_COUNT_LT = 52 ;
+static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_1_C1_COUNT_LT_LEN = 4 ;
+static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_1_C2_COUNT_LT = 56 ;
+static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_1_C2_COUNT_LT_LEN = 4 ;
+static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_1_RESET_C3_SELECT = 60 ;
+static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_1_RESET_C3_SELECT_LEN = 3 ;
+
+static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_1_COND1_SEL_A = 0 ;
+static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_1_COND1_SEL_A_LEN = 8 ;
+static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_1_COND1_SEL_B = 8 ;
+static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_1_COND1_SEL_B_LEN = 8 ;
+static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_1_COND2_SEL_A = 16 ;
+static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_1_COND2_SEL_A_LEN = 8 ;
+static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_1_COND2_SEL_B = 24 ;
+static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_1_COND2_SEL_B_LEN = 8 ;
+static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_1_C1_INAROW_MODE = 32 ;
+static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE1 = 33 ;
+static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE1 = 34 ;
+static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE1 = 35 ;
+static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_1_UNUSED = 36 ;
+static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_1_UNUSED_LEN = 3 ;
+static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_1_C2_INAROW_MODE = 39 ;
+static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE2 = 40 ;
+static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE2 = 41 ;
+static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE2 = 42 ;
+static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_1_UNUSED_2 = 43 ;
+static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_1_UNUSED_2_LEN = 3 ;
+static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_1_COND3_ENABLE_RESET = 46 ;
+static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_1_EXACT_TO_MODE = 47 ;
+static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_1_RESET_C2TIMER_ON_C1 = 48 ;
+static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_1_RESET_C3_ON_C0 = 49 ;
+static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_1_SLOW_TO_MODE = 50 ;
+static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_1_EXACT_RESET_C3_ON_TO = 51 ;
+static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_1_C1_COUNT_LT = 52 ;
+static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_1_C1_COUNT_LT_LEN = 4 ;
+static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_1_C2_COUNT_LT = 56 ;
+static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_1_C2_COUNT_LT_LEN = 4 ;
+static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_1_RESET_C3_SELECT = 60 ;
+static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_1_RESET_C3_SELECT_LEN = 3 ;
+
+static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A = 0 ;
+static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN = 5 ;
+static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B = 5 ;
+static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN = 5 ;
+static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A = 10 ;
+static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN = 5 ;
+static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B = 15 ;
+static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN = 5 ;
+static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_2_TO_CMP_LT = 20 ;
+static const uint8_t P9N2_PU_N3_DBG_INST2_COND_REG_2_TO_CMP_LT_LEN = 24 ;
+
+static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A = 0 ;
+static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN = 5 ;
+static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B = 5 ;
+static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN = 5 ;
+static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A = 10 ;
+static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN = 5 ;
+static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B = 15 ;
+static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN = 5 ;
+static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_2_TO_CMP_LT = 20 ;
+static const uint8_t P9N2_PU_N1_DBG_INST2_COND_REG_2_TO_CMP_LT_LEN = 24 ;
+
+static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A = 0 ;
+static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN = 5 ;
+static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B = 5 ;
+static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN = 5 ;
+static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A = 10 ;
+static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN = 5 ;
+static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B = 15 ;
+static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN = 5 ;
+static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_2_TO_CMP_LT = 20 ;
+static const uint8_t P9N2_PU_N2_DBG_INST2_COND_REG_2_TO_CMP_LT_LEN = 24 ;
+
+static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A = 0 ;
+static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN = 5 ;
+static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B = 5 ;
+static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN = 5 ;
+static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A = 10 ;
+static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN = 5 ;
+static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B = 15 ;
+static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN = 5 ;
+static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_2_TO_CMP_LT = 20 ;
+static const uint8_t P9N2_PEC_DBG_INST2_COND_REG_2_TO_CMP_LT_LEN = 24 ;
+
+static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A = 0 ;
+static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN = 5 ;
+static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B = 5 ;
+static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN = 5 ;
+static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A = 10 ;
+static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN = 5 ;
+static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B = 15 ;
+static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN = 5 ;
+static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_2_TO_CMP_LT = 20 ;
+static const uint8_t P9N2_PU_N0_DBG_INST2_COND_REG_2_TO_CMP_LT_LEN = 24 ;
+
+static const uint8_t P9N2_PU_N3_DBG_MODE_REG_GLB_BRCST = 0 ;
+static const uint8_t P9N2_PU_N3_DBG_MODE_REG_GLB_BRCST_LEN = 3 ;
+static const uint8_t P9N2_PU_N3_DBG_MODE_REG_TRACE_SEL = 3 ;
+static const uint8_t P9N2_PU_N3_DBG_MODE_REG_TRACE_SEL_LEN = 3 ;
+static const uint8_t P9N2_PU_N3_DBG_MODE_REG_TRIG_SEL = 6 ;
+static const uint8_t P9N2_PU_N3_DBG_MODE_REG_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_N3_DBG_MODE_REG_STOP_ON_XSTOP_SELECTION = 8 ;
+static const uint8_t P9N2_PU_N3_DBG_MODE_REG_STOP_ON_RECOV_ERR_SELECTION = 9 ;
+static const uint8_t P9N2_PU_N3_DBG_MODE_REG_STOP_ON_SPATTN_SELECTION = 10 ;
+static const uint8_t P9N2_PU_N3_DBG_MODE_REG_FREEZE_SEL = 11 ;
+static const uint8_t P9N2_PU_N3_DBG_MODE_REG_SYNC_BRCST = 12 ;
+static const uint8_t P9N2_PU_N3_DBG_MODE_REG_SYNC_BRCST_LEN = 2 ;
+
+static const uint8_t P9N2_PU_N1_DBG_MODE_REG_GLB_BRCST = 0 ;
+static const uint8_t P9N2_PU_N1_DBG_MODE_REG_GLB_BRCST_LEN = 3 ;
+static const uint8_t P9N2_PU_N1_DBG_MODE_REG_TRACE_SEL = 3 ;
+static const uint8_t P9N2_PU_N1_DBG_MODE_REG_TRACE_SEL_LEN = 3 ;
+static const uint8_t P9N2_PU_N1_DBG_MODE_REG_TRIG_SEL = 6 ;
+static const uint8_t P9N2_PU_N1_DBG_MODE_REG_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_N1_DBG_MODE_REG_STOP_ON_XSTOP_SELECTION = 8 ;
+static const uint8_t P9N2_PU_N1_DBG_MODE_REG_STOP_ON_RECOV_ERR_SELECTION = 9 ;
+static const uint8_t P9N2_PU_N1_DBG_MODE_REG_STOP_ON_SPATTN_SELECTION = 10 ;
+static const uint8_t P9N2_PU_N1_DBG_MODE_REG_FREEZE_SEL = 11 ;
+static const uint8_t P9N2_PU_N1_DBG_MODE_REG_SYNC_BRCST = 12 ;
+static const uint8_t P9N2_PU_N1_DBG_MODE_REG_SYNC_BRCST_LEN = 2 ;
+
+static const uint8_t P9N2_PU_N2_DBG_MODE_REG_GLB_BRCST = 0 ;
+static const uint8_t P9N2_PU_N2_DBG_MODE_REG_GLB_BRCST_LEN = 3 ;
+static const uint8_t P9N2_PU_N2_DBG_MODE_REG_TRACE_SEL = 3 ;
+static const uint8_t P9N2_PU_N2_DBG_MODE_REG_TRACE_SEL_LEN = 3 ;
+static const uint8_t P9N2_PU_N2_DBG_MODE_REG_TRIG_SEL = 6 ;
+static const uint8_t P9N2_PU_N2_DBG_MODE_REG_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_N2_DBG_MODE_REG_STOP_ON_XSTOP_SELECTION = 8 ;
+static const uint8_t P9N2_PU_N2_DBG_MODE_REG_STOP_ON_RECOV_ERR_SELECTION = 9 ;
+static const uint8_t P9N2_PU_N2_DBG_MODE_REG_STOP_ON_SPATTN_SELECTION = 10 ;
+static const uint8_t P9N2_PU_N2_DBG_MODE_REG_FREEZE_SEL = 11 ;
+static const uint8_t P9N2_PU_N2_DBG_MODE_REG_SYNC_BRCST = 12 ;
+static const uint8_t P9N2_PU_N2_DBG_MODE_REG_SYNC_BRCST_LEN = 2 ;
+
+static const uint8_t P9N2_PEC_DBG_MODE_REG_GLB_BRCST = 0 ;
+static const uint8_t P9N2_PEC_DBG_MODE_REG_GLB_BRCST_LEN = 3 ;
+static const uint8_t P9N2_PEC_DBG_MODE_REG_TRACE_SEL = 3 ;
+static const uint8_t P9N2_PEC_DBG_MODE_REG_TRACE_SEL_LEN = 3 ;
+static const uint8_t P9N2_PEC_DBG_MODE_REG_TRIG_SEL = 6 ;
+static const uint8_t P9N2_PEC_DBG_MODE_REG_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_PEC_DBG_MODE_REG_STOP_ON_XSTOP_SELECTION = 8 ;
+static const uint8_t P9N2_PEC_DBG_MODE_REG_STOP_ON_RECOV_ERR_SELECTION = 9 ;
+static const uint8_t P9N2_PEC_DBG_MODE_REG_STOP_ON_SPATTN_SELECTION = 10 ;
+static const uint8_t P9N2_PEC_DBG_MODE_REG_FREEZE_SEL = 11 ;
+static const uint8_t P9N2_PEC_DBG_MODE_REG_SYNC_BRCST = 12 ;
+static const uint8_t P9N2_PEC_DBG_MODE_REG_SYNC_BRCST_LEN = 2 ;
+
+static const uint8_t P9N2_PU_N0_DBG_MODE_REG_GLB_BRCST = 0 ;
+static const uint8_t P9N2_PU_N0_DBG_MODE_REG_GLB_BRCST_LEN = 3 ;
+static const uint8_t P9N2_PU_N0_DBG_MODE_REG_TRACE_SEL = 3 ;
+static const uint8_t P9N2_PU_N0_DBG_MODE_REG_TRACE_SEL_LEN = 3 ;
+static const uint8_t P9N2_PU_N0_DBG_MODE_REG_TRIG_SEL = 6 ;
+static const uint8_t P9N2_PU_N0_DBG_MODE_REG_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_N0_DBG_MODE_REG_STOP_ON_XSTOP_SELECTION = 8 ;
+static const uint8_t P9N2_PU_N0_DBG_MODE_REG_STOP_ON_RECOV_ERR_SELECTION = 9 ;
+static const uint8_t P9N2_PU_N0_DBG_MODE_REG_STOP_ON_SPATTN_SELECTION = 10 ;
+static const uint8_t P9N2_PU_N0_DBG_MODE_REG_FREEZE_SEL = 11 ;
+static const uint8_t P9N2_PU_N0_DBG_MODE_REG_SYNC_BRCST = 12 ;
+static const uint8_t P9N2_PU_N0_DBG_MODE_REG_SYNC_BRCST_LEN = 2 ;
+
+static const uint8_t P9N2_PU_N3_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE = 0 ;
+static const uint8_t P9N2_PU_N3_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE_LEN = 16 ;
+static const uint8_t P9N2_PU_N3_DBG_TRACE_MODE_REG_2_IMM_FREEZE = 16 ;
+static const uint8_t P9N2_PU_N3_DBG_TRACE_MODE_REG_2_STOP_ON_ERR = 17 ;
+static const uint8_t P9N2_PU_N3_DBG_TRACE_MODE_REG_2_BANK_ON_RUNN_MATCH = 18 ;
+static const uint8_t P9N2_PU_N3_DBG_TRACE_MODE_REG_2_FORCE_TEST = 19 ;
+static const uint8_t P9N2_PU_N3_DBG_TRACE_MODE_REG_2_ACCUM_HIST = 20 ;
+static const uint8_t P9N2_PU_N3_DBG_TRACE_MODE_REG_2_FRZ_COUNT_ON_FRZ = 21 ;
+
+static const uint8_t P9N2_PU_N1_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE = 0 ;
+static const uint8_t P9N2_PU_N1_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE_LEN = 16 ;
+static const uint8_t P9N2_PU_N1_DBG_TRACE_MODE_REG_2_IMM_FREEZE = 16 ;
+static const uint8_t P9N2_PU_N1_DBG_TRACE_MODE_REG_2_STOP_ON_ERR = 17 ;
+static const uint8_t P9N2_PU_N1_DBG_TRACE_MODE_REG_2_BANK_ON_RUNN_MATCH = 18 ;
+static const uint8_t P9N2_PU_N1_DBG_TRACE_MODE_REG_2_FORCE_TEST = 19 ;
+static const uint8_t P9N2_PU_N1_DBG_TRACE_MODE_REG_2_ACCUM_HIST = 20 ;
+static const uint8_t P9N2_PU_N1_DBG_TRACE_MODE_REG_2_FRZ_COUNT_ON_FRZ = 21 ;
+
+static const uint8_t P9N2_PU_N2_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE = 0 ;
+static const uint8_t P9N2_PU_N2_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE_LEN = 16 ;
+static const uint8_t P9N2_PU_N2_DBG_TRACE_MODE_REG_2_IMM_FREEZE = 16 ;
+static const uint8_t P9N2_PU_N2_DBG_TRACE_MODE_REG_2_STOP_ON_ERR = 17 ;
+static const uint8_t P9N2_PU_N2_DBG_TRACE_MODE_REG_2_BANK_ON_RUNN_MATCH = 18 ;
+static const uint8_t P9N2_PU_N2_DBG_TRACE_MODE_REG_2_FORCE_TEST = 19 ;
+static const uint8_t P9N2_PU_N2_DBG_TRACE_MODE_REG_2_ACCUM_HIST = 20 ;
+static const uint8_t P9N2_PU_N2_DBG_TRACE_MODE_REG_2_FRZ_COUNT_ON_FRZ = 21 ;
+
+static const uint8_t P9N2_PEC_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE = 0 ;
+static const uint8_t P9N2_PEC_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE_LEN = 16 ;
+static const uint8_t P9N2_PEC_DBG_TRACE_MODE_REG_2_IMM_FREEZE = 16 ;
+static const uint8_t P9N2_PEC_DBG_TRACE_MODE_REG_2_STOP_ON_ERR = 17 ;
+static const uint8_t P9N2_PEC_DBG_TRACE_MODE_REG_2_BANK_ON_RUNN_MATCH = 18 ;
+static const uint8_t P9N2_PEC_DBG_TRACE_MODE_REG_2_FORCE_TEST = 19 ;
+static const uint8_t P9N2_PEC_DBG_TRACE_MODE_REG_2_ACCUM_HIST = 20 ;
+static const uint8_t P9N2_PEC_DBG_TRACE_MODE_REG_2_FRZ_COUNT_ON_FRZ = 21 ;
+
+static const uint8_t P9N2_PU_N0_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE = 0 ;
+static const uint8_t P9N2_PU_N0_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE_LEN = 16 ;
+static const uint8_t P9N2_PU_N0_DBG_TRACE_MODE_REG_2_IMM_FREEZE = 16 ;
+static const uint8_t P9N2_PU_N0_DBG_TRACE_MODE_REG_2_STOP_ON_ERR = 17 ;
+static const uint8_t P9N2_PU_N0_DBG_TRACE_MODE_REG_2_BANK_ON_RUNN_MATCH = 18 ;
+static const uint8_t P9N2_PU_N0_DBG_TRACE_MODE_REG_2_FORCE_TEST = 19 ;
+static const uint8_t P9N2_PU_N0_DBG_TRACE_MODE_REG_2_ACCUM_HIST = 20 ;
+static const uint8_t P9N2_PU_N0_DBG_TRACE_MODE_REG_2_FRZ_COUNT_ON_FRZ = 21 ;
+
+static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_0_INST1_COND3_ENABLE = 0 ;
+static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_0_INST2_COND3_ENABLE = 1 ;
+static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_0_INST3_COND3_ENABLE = 2 ;
+static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_0_INST4_COND3_ENABLE = 3 ;
+static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_0_INST1_SLOW_LFSR_MODE = 4 ;
+static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_0_INST2_SLOW_LFSR_MODE = 5 ;
+static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_0_INST3_SLOW_LFSR_MODE = 6 ;
+static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_0_INST4_SLOW_LFSR_MODE = 7 ;
+static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL = 8 ;
+static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL = 10 ;
+static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL = 12 ;
+static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL = 14 ;
+static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL = 16 ;
+static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL = 18 ;
+static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_0_EXT_TRIG_ON_STOP = 32 ;
+static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_0_EXT_TRIG_ON_FREEZE = 33 ;
+static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL = 34 ;
+static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL_LEN = 5 ;
+static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL = 39 ;
+static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL_LEN = 5 ;
+static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_0_PC_TP_TRIG_SEL = 44 ;
+static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_0_PC_TP_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_0_ARM_SEL = 46 ;
+static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_0_ARM_SEL_LEN = 4 ;
+static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL = 50 ;
+static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL_LEN = 4 ;
+static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL = 54 ;
+static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL_LEN = 4 ;
+
+static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_0_INST1_COND3_ENABLE = 0 ;
+static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_0_INST2_COND3_ENABLE = 1 ;
+static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_0_INST3_COND3_ENABLE = 2 ;
+static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_0_INST4_COND3_ENABLE = 3 ;
+static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_0_INST1_SLOW_LFSR_MODE = 4 ;
+static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_0_INST2_SLOW_LFSR_MODE = 5 ;
+static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_0_INST3_SLOW_LFSR_MODE = 6 ;
+static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_0_INST4_SLOW_LFSR_MODE = 7 ;
+static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL = 8 ;
+static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL = 10 ;
+static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL = 12 ;
+static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL = 14 ;
+static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL = 16 ;
+static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL = 18 ;
+static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_0_EXT_TRIG_ON_STOP = 32 ;
+static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_0_EXT_TRIG_ON_FREEZE = 33 ;
+static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL = 34 ;
+static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL_LEN = 5 ;
+static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL = 39 ;
+static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL_LEN = 5 ;
+static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_0_PC_TP_TRIG_SEL = 44 ;
+static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_0_PC_TP_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_0_ARM_SEL = 46 ;
+static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_0_ARM_SEL_LEN = 4 ;
+static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL = 50 ;
+static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL_LEN = 4 ;
+static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL = 54 ;
+static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL_LEN = 4 ;
+
+static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_0_INST1_COND3_ENABLE = 0 ;
+static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_0_INST2_COND3_ENABLE = 1 ;
+static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_0_INST3_COND3_ENABLE = 2 ;
+static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_0_INST4_COND3_ENABLE = 3 ;
+static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_0_INST1_SLOW_LFSR_MODE = 4 ;
+static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_0_INST2_SLOW_LFSR_MODE = 5 ;
+static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_0_INST3_SLOW_LFSR_MODE = 6 ;
+static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_0_INST4_SLOW_LFSR_MODE = 7 ;
+static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL = 8 ;
+static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL = 10 ;
+static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL = 12 ;
+static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL = 14 ;
+static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL = 16 ;
+static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL = 18 ;
+static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_0_EXT_TRIG_ON_STOP = 32 ;
+static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_0_EXT_TRIG_ON_FREEZE = 33 ;
+static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL = 34 ;
+static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL_LEN = 5 ;
+static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL = 39 ;
+static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL_LEN = 5 ;
+static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_0_PC_TP_TRIG_SEL = 44 ;
+static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_0_PC_TP_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_0_ARM_SEL = 46 ;
+static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_0_ARM_SEL_LEN = 4 ;
+static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL = 50 ;
+static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL_LEN = 4 ;
+static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL = 54 ;
+static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL_LEN = 4 ;
+
+static const uint8_t P9N2_PEC_DBG_TRACE_REG_0_INST1_COND3_ENABLE = 0 ;
+static const uint8_t P9N2_PEC_DBG_TRACE_REG_0_INST2_COND3_ENABLE = 1 ;
+static const uint8_t P9N2_PEC_DBG_TRACE_REG_0_INST3_COND3_ENABLE = 2 ;
+static const uint8_t P9N2_PEC_DBG_TRACE_REG_0_INST4_COND3_ENABLE = 3 ;
+static const uint8_t P9N2_PEC_DBG_TRACE_REG_0_INST1_SLOW_LFSR_MODE = 4 ;
+static const uint8_t P9N2_PEC_DBG_TRACE_REG_0_INST2_SLOW_LFSR_MODE = 5 ;
+static const uint8_t P9N2_PEC_DBG_TRACE_REG_0_INST3_SLOW_LFSR_MODE = 6 ;
+static const uint8_t P9N2_PEC_DBG_TRACE_REG_0_INST4_SLOW_LFSR_MODE = 7 ;
+static const uint8_t P9N2_PEC_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL = 8 ;
+static const uint8_t P9N2_PEC_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_PEC_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL = 10 ;
+static const uint8_t P9N2_PEC_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_PEC_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL = 12 ;
+static const uint8_t P9N2_PEC_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_PEC_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL = 14 ;
+static const uint8_t P9N2_PEC_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_PEC_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL = 16 ;
+static const uint8_t P9N2_PEC_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_PEC_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL = 18 ;
+static const uint8_t P9N2_PEC_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_PEC_DBG_TRACE_REG_0_EXT_TRIG_ON_STOP = 32 ;
+static const uint8_t P9N2_PEC_DBG_TRACE_REG_0_EXT_TRIG_ON_FREEZE = 33 ;
+static const uint8_t P9N2_PEC_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL = 34 ;
+static const uint8_t P9N2_PEC_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL_LEN = 5 ;
+static const uint8_t P9N2_PEC_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL = 39 ;
+static const uint8_t P9N2_PEC_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL_LEN = 5 ;
+static const uint8_t P9N2_PEC_DBG_TRACE_REG_0_PC_TP_TRIG_SEL = 44 ;
+static const uint8_t P9N2_PEC_DBG_TRACE_REG_0_PC_TP_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_PEC_DBG_TRACE_REG_0_ARM_SEL = 46 ;
+static const uint8_t P9N2_PEC_DBG_TRACE_REG_0_ARM_SEL_LEN = 4 ;
+static const uint8_t P9N2_PEC_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL = 50 ;
+static const uint8_t P9N2_PEC_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL_LEN = 4 ;
+static const uint8_t P9N2_PEC_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL = 54 ;
+static const uint8_t P9N2_PEC_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL_LEN = 4 ;
+
+static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_0_INST1_COND3_ENABLE = 0 ;
+static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_0_INST2_COND3_ENABLE = 1 ;
+static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_0_INST3_COND3_ENABLE = 2 ;
+static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_0_INST4_COND3_ENABLE = 3 ;
+static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_0_INST1_SLOW_LFSR_MODE = 4 ;
+static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_0_INST2_SLOW_LFSR_MODE = 5 ;
+static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_0_INST3_SLOW_LFSR_MODE = 6 ;
+static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_0_INST4_SLOW_LFSR_MODE = 7 ;
+static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL = 8 ;
+static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL = 10 ;
+static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL = 12 ;
+static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL = 14 ;
+static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL = 16 ;
+static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL = 18 ;
+static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_0_EXT_TRIG_ON_STOP = 32 ;
+static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_0_EXT_TRIG_ON_FREEZE = 33 ;
+static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL = 34 ;
+static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL_LEN = 5 ;
+static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL = 39 ;
+static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL_LEN = 5 ;
+static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_0_PC_TP_TRIG_SEL = 44 ;
+static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_0_PC_TP_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_0_ARM_SEL = 46 ;
+static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_0_ARM_SEL_LEN = 4 ;
+static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL = 50 ;
+static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL_LEN = 4 ;
+static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL = 54 ;
+static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL_LEN = 4 ;
+
+static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO = 0 ;
+static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO_LEN = 2 ;
+static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO = 2 ;
+static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO_LEN = 2 ;
+static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO = 4 ;
+static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO_LEN = 2 ;
+static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO = 6 ;
+static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO_LEN = 2 ;
+static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO = 8 ;
+static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO_LEN = 2 ;
+static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO = 10 ;
+static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO_LEN = 2 ;
+static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_WAITN = 24 ;
+static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_WAITN = 25 ;
+static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_WAITN = 26 ;
+static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_WAITN = 27 ;
+static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_WAITN = 28 ;
+static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_WAITN = 29 ;
+static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_BANK = 36 ;
+static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_BANK = 37 ;
+static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_BANK = 38 ;
+static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_BANK = 39 ;
+static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_BANK = 40 ;
+static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_BANK = 41 ;
+static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT = 48 ;
+static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT_LEN = 3 ;
+static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_SELECTOR = 51 ;
+static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT = 52 ;
+static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT_LEN = 3 ;
+static const uint8_t P9N2_PU_N3_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_SELECTOR = 55 ;
+
+static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO = 0 ;
+static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO_LEN = 2 ;
+static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO = 2 ;
+static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO_LEN = 2 ;
+static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO = 4 ;
+static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO_LEN = 2 ;
+static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO = 6 ;
+static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO_LEN = 2 ;
+static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO = 8 ;
+static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO_LEN = 2 ;
+static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO = 10 ;
+static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO_LEN = 2 ;
+static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_WAITN = 24 ;
+static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_WAITN = 25 ;
+static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_WAITN = 26 ;
+static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_WAITN = 27 ;
+static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_WAITN = 28 ;
+static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_WAITN = 29 ;
+static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_BANK = 36 ;
+static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_BANK = 37 ;
+static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_BANK = 38 ;
+static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_BANK = 39 ;
+static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_BANK = 40 ;
+static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_BANK = 41 ;
+static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT = 48 ;
+static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT_LEN = 3 ;
+static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_SELECTOR = 51 ;
+static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT = 52 ;
+static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT_LEN = 3 ;
+static const uint8_t P9N2_PU_N1_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_SELECTOR = 55 ;
+
+static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO = 0 ;
+static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO_LEN = 2 ;
+static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO = 2 ;
+static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO_LEN = 2 ;
+static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO = 4 ;
+static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO_LEN = 2 ;
+static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO = 6 ;
+static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO_LEN = 2 ;
+static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO = 8 ;
+static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO_LEN = 2 ;
+static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO = 10 ;
+static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO_LEN = 2 ;
+static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_WAITN = 24 ;
+static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_WAITN = 25 ;
+static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_WAITN = 26 ;
+static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_WAITN = 27 ;
+static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_WAITN = 28 ;
+static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_WAITN = 29 ;
+static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_BANK = 36 ;
+static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_BANK = 37 ;
+static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_BANK = 38 ;
+static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_BANK = 39 ;
+static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_BANK = 40 ;
+static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_BANK = 41 ;
+static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT = 48 ;
+static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT_LEN = 3 ;
+static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_SELECTOR = 51 ;
+static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT = 52 ;
+static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT_LEN = 3 ;
+static const uint8_t P9N2_PU_N2_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_SELECTOR = 55 ;
+
+static const uint8_t P9N2_PEC_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO = 0 ;
+static const uint8_t P9N2_PEC_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO_LEN = 2 ;
+static const uint8_t P9N2_PEC_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO = 2 ;
+static const uint8_t P9N2_PEC_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO_LEN = 2 ;
+static const uint8_t P9N2_PEC_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO = 4 ;
+static const uint8_t P9N2_PEC_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO_LEN = 2 ;
+static const uint8_t P9N2_PEC_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO = 6 ;
+static const uint8_t P9N2_PEC_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO_LEN = 2 ;
+static const uint8_t P9N2_PEC_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO = 8 ;
+static const uint8_t P9N2_PEC_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO_LEN = 2 ;
+static const uint8_t P9N2_PEC_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO = 10 ;
+static const uint8_t P9N2_PEC_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO_LEN = 2 ;
+static const uint8_t P9N2_PEC_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_WAITN = 24 ;
+static const uint8_t P9N2_PEC_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_WAITN = 25 ;
+static const uint8_t P9N2_PEC_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_WAITN = 26 ;
+static const uint8_t P9N2_PEC_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_WAITN = 27 ;
+static const uint8_t P9N2_PEC_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_WAITN = 28 ;
+static const uint8_t P9N2_PEC_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_WAITN = 29 ;
+static const uint8_t P9N2_PEC_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_BANK = 36 ;
+static const uint8_t P9N2_PEC_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_BANK = 37 ;
+static const uint8_t P9N2_PEC_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_BANK = 38 ;
+static const uint8_t P9N2_PEC_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_BANK = 39 ;
+static const uint8_t P9N2_PEC_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_BANK = 40 ;
+static const uint8_t P9N2_PEC_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_BANK = 41 ;
+static const uint8_t P9N2_PEC_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT = 48 ;
+static const uint8_t P9N2_PEC_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT_LEN = 3 ;
+static const uint8_t P9N2_PEC_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_SELECTOR = 51 ;
+static const uint8_t P9N2_PEC_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT = 52 ;
+static const uint8_t P9N2_PEC_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT_LEN = 3 ;
+static const uint8_t P9N2_PEC_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_SELECTOR = 55 ;
+
+static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO = 0 ;
+static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO_LEN = 2 ;
+static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO = 2 ;
+static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO_LEN = 2 ;
+static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO = 4 ;
+static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO_LEN = 2 ;
+static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO = 6 ;
+static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO_LEN = 2 ;
+static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO = 8 ;
+static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO_LEN = 2 ;
+static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO = 10 ;
+static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO_LEN = 2 ;
+static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_WAITN = 24 ;
+static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_WAITN = 25 ;
+static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_WAITN = 26 ;
+static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_WAITN = 27 ;
+static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_WAITN = 28 ;
+static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_WAITN = 29 ;
+static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_BANK = 36 ;
+static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_BANK = 37 ;
+static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_BANK = 38 ;
+static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_BANK = 39 ;
+static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_BANK = 40 ;
+static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_BANK = 41 ;
+static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT = 48 ;
+static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT_LEN = 3 ;
+static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_SELECTOR = 51 ;
+static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT = 52 ;
+static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT_LEN = 3 ;
+static const uint8_t P9N2_PU_N0_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_SELECTOR = 55 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG0_CONFIG_POD0 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG0_CONFIG_POD0_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG0_CONFIG_POD1 = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG0_CONFIG_POD1_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG0_CONFIG_POD2 = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG0_CONFIG_POD2_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG0_CONFIG_POD3 = 15 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG0_CONFIG_POD3_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG0_CONFIG_POD4 = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG0_CONFIG_POD4_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG0_CONFIG_POD5 = 25 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG0_CONFIG_POD5_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG0_CONFIG_POD6 = 30 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG0_CONFIG_POD6_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG0_CONFIG_POD7 = 35 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG0_CONFIG_POD7_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG0_CONFIG_POD8 = 40 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG0_CONFIG_POD8_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG0_CONFIG_POD9 = 45 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG0_CONFIG_POD9_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG0_CONFIG_POD10 = 50 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG0_CONFIG_POD10_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG0_CONFIG_RESERVED1 = 55 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG0_CONFIG_RESERVED1_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG0_CONFIG_ACT = 63 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG0_CONFIG_POD0 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG0_CONFIG_POD0_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG0_CONFIG_POD1 = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG0_CONFIG_POD1_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG0_CONFIG_POD2 = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG0_CONFIG_POD2_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG0_CONFIG_POD3 = 15 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG0_CONFIG_POD3_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG0_CONFIG_POD4 = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG0_CONFIG_POD4_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG0_CONFIG_POD5 = 25 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG0_CONFIG_POD5_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG0_CONFIG_POD6 = 30 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG0_CONFIG_POD6_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG0_CONFIG_POD7 = 35 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG0_CONFIG_POD7_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG0_CONFIG_POD8 = 40 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG0_CONFIG_POD8_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG0_CONFIG_POD9 = 45 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG0_CONFIG_POD9_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG0_CONFIG_POD10 = 50 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG0_CONFIG_POD10_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG0_CONFIG_RESERVED1 = 55 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG0_CONFIG_RESERVED1_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG0_CONFIG_ACT = 63 ;
+
+static const uint8_t P9N2_PU_NPU1_SM1_DEBUG0_CONFIG_POD0 = 0 ;
+static const uint8_t P9N2_PU_NPU1_SM1_DEBUG0_CONFIG_POD0_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM1_DEBUG0_CONFIG_POD1 = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM1_DEBUG0_CONFIG_POD1_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM1_DEBUG0_CONFIG_POD2 = 10 ;
+static const uint8_t P9N2_PU_NPU1_SM1_DEBUG0_CONFIG_POD2_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM1_DEBUG0_CONFIG_POD3 = 15 ;
+static const uint8_t P9N2_PU_NPU1_SM1_DEBUG0_CONFIG_POD3_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM1_DEBUG0_CONFIG_POD4 = 20 ;
+static const uint8_t P9N2_PU_NPU1_SM1_DEBUG0_CONFIG_POD4_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM1_DEBUG0_CONFIG_POD5 = 25 ;
+static const uint8_t P9N2_PU_NPU1_SM1_DEBUG0_CONFIG_POD5_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM1_DEBUG0_CONFIG_POD6 = 30 ;
+static const uint8_t P9N2_PU_NPU1_SM1_DEBUG0_CONFIG_POD6_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM1_DEBUG0_CONFIG_POD7 = 35 ;
+static const uint8_t P9N2_PU_NPU1_SM1_DEBUG0_CONFIG_POD7_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM1_DEBUG0_CONFIG_POD8 = 40 ;
+static const uint8_t P9N2_PU_NPU1_SM1_DEBUG0_CONFIG_POD8_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM1_DEBUG0_CONFIG_POD9 = 45 ;
+static const uint8_t P9N2_PU_NPU1_SM1_DEBUG0_CONFIG_POD9_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM1_DEBUG0_CONFIG_POD10 = 50 ;
+static const uint8_t P9N2_PU_NPU1_SM1_DEBUG0_CONFIG_POD10_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM1_DEBUG0_CONFIG_RESERVED1 = 55 ;
+static const uint8_t P9N2_PU_NPU1_SM1_DEBUG0_CONFIG_RESERVED1_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU1_SM1_DEBUG0_CONFIG_ACT = 63 ;
+
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG0_CONFIG_POD0 = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG0_CONFIG_POD0_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG0_CONFIG_POD1 = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG0_CONFIG_POD1_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG0_CONFIG_POD2 = 10 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG0_CONFIG_POD2_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG0_CONFIG_POD3 = 15 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG0_CONFIG_POD3_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG0_CONFIG_POD4 = 20 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG0_CONFIG_POD4_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG0_CONFIG_POD5 = 25 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG0_CONFIG_POD5_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG0_CONFIG_POD6 = 30 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG0_CONFIG_POD6_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG0_CONFIG_POD7 = 35 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG0_CONFIG_POD7_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG0_CONFIG_POD8 = 40 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG0_CONFIG_POD8_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG0_CONFIG_POD9 = 45 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG0_CONFIG_POD9_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG0_CONFIG_POD10 = 50 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG0_CONFIG_POD10_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG0_CONFIG_RESERVED1 = 55 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG0_CONFIG_RESERVED1_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG0_CONFIG_ACT = 63 ;
+
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG0_CONFIG_POD0 = 0 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG0_CONFIG_POD0_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG0_CONFIG_POD1 = 5 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG0_CONFIG_POD1_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG0_CONFIG_POD2 = 10 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG0_CONFIG_POD2_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG0_CONFIG_POD3 = 15 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG0_CONFIG_POD3_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG0_CONFIG_POD4 = 20 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG0_CONFIG_POD4_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG0_CONFIG_POD5 = 25 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG0_CONFIG_POD5_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG0_CONFIG_POD6 = 30 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG0_CONFIG_POD6_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG0_CONFIG_POD7 = 35 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG0_CONFIG_POD7_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG0_CONFIG_POD8 = 40 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG0_CONFIG_POD8_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG0_CONFIG_POD9 = 45 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG0_CONFIG_POD9_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG0_CONFIG_POD10 = 50 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG0_CONFIG_POD10_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG0_CONFIG_RESERVED1 = 55 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG0_CONFIG_RESERVED1_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG0_CONFIG_ACT = 63 ;
+
+static const uint8_t P9N2__SM2_DEBUG0_CONFIG_POD0 = 0 ;
+static const uint8_t P9N2__SM2_DEBUG0_CONFIG_POD0_LEN = 5 ;
+static const uint8_t P9N2__SM2_DEBUG0_CONFIG_POD1 = 5 ;
+static const uint8_t P9N2__SM2_DEBUG0_CONFIG_POD1_LEN = 5 ;
+static const uint8_t P9N2__SM2_DEBUG0_CONFIG_POD2 = 10 ;
+static const uint8_t P9N2__SM2_DEBUG0_CONFIG_POD2_LEN = 5 ;
+static const uint8_t P9N2__SM2_DEBUG0_CONFIG_POD3 = 15 ;
+static const uint8_t P9N2__SM2_DEBUG0_CONFIG_POD3_LEN = 5 ;
+static const uint8_t P9N2__SM2_DEBUG0_CONFIG_POD4 = 20 ;
+static const uint8_t P9N2__SM2_DEBUG0_CONFIG_POD4_LEN = 5 ;
+static const uint8_t P9N2__SM2_DEBUG0_CONFIG_POD5 = 25 ;
+static const uint8_t P9N2__SM2_DEBUG0_CONFIG_POD5_LEN = 5 ;
+static const uint8_t P9N2__SM2_DEBUG0_CONFIG_POD6 = 30 ;
+static const uint8_t P9N2__SM2_DEBUG0_CONFIG_POD6_LEN = 5 ;
+static const uint8_t P9N2__SM2_DEBUG0_CONFIG_POD7 = 35 ;
+static const uint8_t P9N2__SM2_DEBUG0_CONFIG_POD7_LEN = 5 ;
+static const uint8_t P9N2__SM2_DEBUG0_CONFIG_POD8 = 40 ;
+static const uint8_t P9N2__SM2_DEBUG0_CONFIG_POD8_LEN = 5 ;
+static const uint8_t P9N2__SM2_DEBUG0_CONFIG_POD9 = 45 ;
+static const uint8_t P9N2__SM2_DEBUG0_CONFIG_POD9_LEN = 5 ;
+static const uint8_t P9N2__SM2_DEBUG0_CONFIG_POD10 = 50 ;
+static const uint8_t P9N2__SM2_DEBUG0_CONFIG_POD10_LEN = 5 ;
+static const uint8_t P9N2__SM2_DEBUG0_CONFIG_RESERVED1 = 55 ;
+static const uint8_t P9N2__SM2_DEBUG0_CONFIG_RESERVED1_LEN = 8 ;
+static const uint8_t P9N2__SM2_DEBUG0_CONFIG_ACT = 63 ;
+
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG0_CONFIG_POD0 = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG0_CONFIG_POD0_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG0_CONFIG_POD1 = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG0_CONFIG_POD1_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG0_CONFIG_POD2 = 10 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG0_CONFIG_POD2_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG0_CONFIG_POD3 = 15 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG0_CONFIG_POD3_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG0_CONFIG_POD4 = 20 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG0_CONFIG_POD4_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG0_CONFIG_POD5 = 25 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG0_CONFIG_POD5_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG0_CONFIG_POD6 = 30 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG0_CONFIG_POD6_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG0_CONFIG_POD7 = 35 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG0_CONFIG_POD7_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG0_CONFIG_POD8 = 40 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG0_CONFIG_POD8_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG0_CONFIG_POD9 = 45 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG0_CONFIG_POD9_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG0_CONFIG_POD10 = 50 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG0_CONFIG_POD10_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG0_CONFIG_RESERVED1 = 55 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG0_CONFIG_RESERVED1_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG0_CONFIG_ACT = 63 ;
+
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG0_CONFIG_POD0 = 0 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG0_CONFIG_POD0_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG0_CONFIG_POD1 = 5 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG0_CONFIG_POD1_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG0_CONFIG_POD2 = 10 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG0_CONFIG_POD2_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG0_CONFIG_POD3 = 15 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG0_CONFIG_POD3_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG0_CONFIG_POD4 = 20 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG0_CONFIG_POD4_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG0_CONFIG_POD5 = 25 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG0_CONFIG_POD5_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG0_CONFIG_POD6 = 30 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG0_CONFIG_POD6_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG0_CONFIG_POD7 = 35 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG0_CONFIG_POD7_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG0_CONFIG_POD8 = 40 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG0_CONFIG_POD8_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG0_CONFIG_POD9 = 45 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG0_CONFIG_POD9_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG0_CONFIG_POD10 = 50 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG0_CONFIG_POD10_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG0_CONFIG_RESERVED1 = 55 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG0_CONFIG_RESERVED1_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG0_CONFIG_ACT = 63 ;
+
+static const uint8_t P9N2__SM1_DEBUG0_CONFIG_POD0 = 0 ;
+static const uint8_t P9N2__SM1_DEBUG0_CONFIG_POD0_LEN = 5 ;
+static const uint8_t P9N2__SM1_DEBUG0_CONFIG_POD1 = 5 ;
+static const uint8_t P9N2__SM1_DEBUG0_CONFIG_POD1_LEN = 5 ;
+static const uint8_t P9N2__SM1_DEBUG0_CONFIG_POD2 = 10 ;
+static const uint8_t P9N2__SM1_DEBUG0_CONFIG_POD2_LEN = 5 ;
+static const uint8_t P9N2__SM1_DEBUG0_CONFIG_POD3 = 15 ;
+static const uint8_t P9N2__SM1_DEBUG0_CONFIG_POD3_LEN = 5 ;
+static const uint8_t P9N2__SM1_DEBUG0_CONFIG_POD4 = 20 ;
+static const uint8_t P9N2__SM1_DEBUG0_CONFIG_POD4_LEN = 5 ;
+static const uint8_t P9N2__SM1_DEBUG0_CONFIG_POD5 = 25 ;
+static const uint8_t P9N2__SM1_DEBUG0_CONFIG_POD5_LEN = 5 ;
+static const uint8_t P9N2__SM1_DEBUG0_CONFIG_POD6 = 30 ;
+static const uint8_t P9N2__SM1_DEBUG0_CONFIG_POD6_LEN = 5 ;
+static const uint8_t P9N2__SM1_DEBUG0_CONFIG_POD7 = 35 ;
+static const uint8_t P9N2__SM1_DEBUG0_CONFIG_POD7_LEN = 5 ;
+static const uint8_t P9N2__SM1_DEBUG0_CONFIG_POD8 = 40 ;
+static const uint8_t P9N2__SM1_DEBUG0_CONFIG_POD8_LEN = 5 ;
+static const uint8_t P9N2__SM1_DEBUG0_CONFIG_POD9 = 45 ;
+static const uint8_t P9N2__SM1_DEBUG0_CONFIG_POD9_LEN = 5 ;
+static const uint8_t P9N2__SM1_DEBUG0_CONFIG_POD10 = 50 ;
+static const uint8_t P9N2__SM1_DEBUG0_CONFIG_POD10_LEN = 5 ;
+static const uint8_t P9N2__SM1_DEBUG0_CONFIG_RESERVED1 = 55 ;
+static const uint8_t P9N2__SM1_DEBUG0_CONFIG_RESERVED1_LEN = 8 ;
+static const uint8_t P9N2__SM1_DEBUG0_CONFIG_ACT = 63 ;
+
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG0_CONFIG_POD0 = 0 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG0_CONFIG_POD0_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG0_CONFIG_POD1 = 5 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG0_CONFIG_POD1_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG0_CONFIG_POD2 = 10 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG0_CONFIG_POD2_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG0_CONFIG_POD3 = 15 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG0_CONFIG_POD3_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG0_CONFIG_POD4 = 20 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG0_CONFIG_POD4_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG0_CONFIG_POD5 = 25 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG0_CONFIG_POD5_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG0_CONFIG_POD6 = 30 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG0_CONFIG_POD6_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG0_CONFIG_POD7 = 35 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG0_CONFIG_POD7_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG0_CONFIG_POD8 = 40 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG0_CONFIG_POD8_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG0_CONFIG_POD9 = 45 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG0_CONFIG_POD9_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG0_CONFIG_POD10 = 50 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG0_CONFIG_POD10_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG0_CONFIG_RESERVED1 = 55 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG0_CONFIG_RESERVED1_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG0_CONFIG_ACT = 63 ;
+
+static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG0_CONFIG_POD0 = 0 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG0_CONFIG_POD0_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG0_CONFIG_POD1 = 5 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG0_CONFIG_POD1_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG0_CONFIG_POD2 = 10 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG0_CONFIG_POD2_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG0_CONFIG_POD3 = 15 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG0_CONFIG_POD3_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG0_CONFIG_POD4 = 20 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG0_CONFIG_POD4_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG0_CONFIG_POD5 = 25 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG0_CONFIG_POD5_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG0_CONFIG_POD6 = 30 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG0_CONFIG_POD6_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG0_CONFIG_POD7 = 35 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG0_CONFIG_POD7_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG0_CONFIG_POD8 = 40 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG0_CONFIG_POD8_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG0_CONFIG_POD9 = 45 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG0_CONFIG_POD9_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG0_CONFIG_POD10 = 50 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG0_CONFIG_POD10_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG0_CONFIG_RESERVED1 = 55 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG0_CONFIG_RESERVED1_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG0_CONFIG_ACT = 63 ;
+
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG0_CONFIG_POD0 = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG0_CONFIG_POD0_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG0_CONFIG_POD1 = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG0_CONFIG_POD1_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG0_CONFIG_POD2 = 10 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG0_CONFIG_POD2_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG0_CONFIG_POD3 = 15 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG0_CONFIG_POD3_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG0_CONFIG_POD4 = 20 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG0_CONFIG_POD4_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG0_CONFIG_POD5 = 25 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG0_CONFIG_POD5_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG0_CONFIG_POD6 = 30 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG0_CONFIG_POD6_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG0_CONFIG_POD7 = 35 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG0_CONFIG_POD7_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG0_CONFIG_POD8 = 40 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG0_CONFIG_POD8_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG0_CONFIG_POD9 = 45 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG0_CONFIG_POD9_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG0_CONFIG_POD10 = 50 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG0_CONFIG_POD10_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG0_CONFIG_RESERVED1 = 55 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG0_CONFIG_RESERVED1_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG0_CONFIG_ACT = 63 ;
+
+static const uint8_t P9N2__SM0_DEBUG0_CONFIG_POD0 = 0 ;
+static const uint8_t P9N2__SM0_DEBUG0_CONFIG_POD0_LEN = 5 ;
+static const uint8_t P9N2__SM0_DEBUG0_CONFIG_POD1 = 5 ;
+static const uint8_t P9N2__SM0_DEBUG0_CONFIG_POD1_LEN = 5 ;
+static const uint8_t P9N2__SM0_DEBUG0_CONFIG_POD2 = 10 ;
+static const uint8_t P9N2__SM0_DEBUG0_CONFIG_POD2_LEN = 5 ;
+static const uint8_t P9N2__SM0_DEBUG0_CONFIG_POD3 = 15 ;
+static const uint8_t P9N2__SM0_DEBUG0_CONFIG_POD3_LEN = 5 ;
+static const uint8_t P9N2__SM0_DEBUG0_CONFIG_POD4 = 20 ;
+static const uint8_t P9N2__SM0_DEBUG0_CONFIG_POD4_LEN = 5 ;
+static const uint8_t P9N2__SM0_DEBUG0_CONFIG_POD5 = 25 ;
+static const uint8_t P9N2__SM0_DEBUG0_CONFIG_POD5_LEN = 5 ;
+static const uint8_t P9N2__SM0_DEBUG0_CONFIG_POD6 = 30 ;
+static const uint8_t P9N2__SM0_DEBUG0_CONFIG_POD6_LEN = 5 ;
+static const uint8_t P9N2__SM0_DEBUG0_CONFIG_POD7 = 35 ;
+static const uint8_t P9N2__SM0_DEBUG0_CONFIG_POD7_LEN = 5 ;
+static const uint8_t P9N2__SM0_DEBUG0_CONFIG_POD8 = 40 ;
+static const uint8_t P9N2__SM0_DEBUG0_CONFIG_POD8_LEN = 5 ;
+static const uint8_t P9N2__SM0_DEBUG0_CONFIG_POD9 = 45 ;
+static const uint8_t P9N2__SM0_DEBUG0_CONFIG_POD9_LEN = 5 ;
+static const uint8_t P9N2__SM0_DEBUG0_CONFIG_POD10 = 50 ;
+static const uint8_t P9N2__SM0_DEBUG0_CONFIG_POD10_LEN = 5 ;
+static const uint8_t P9N2__SM0_DEBUG0_CONFIG_RESERVED1 = 55 ;
+static const uint8_t P9N2__SM0_DEBUG0_CONFIG_RESERVED1_LEN = 8 ;
+static const uint8_t P9N2__SM0_DEBUG0_CONFIG_ACT = 63 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG0_CONFIG_POD0 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG0_CONFIG_POD0_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG0_CONFIG_POD1 = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG0_CONFIG_POD1_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG0_CONFIG_POD2 = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG0_CONFIG_POD2_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG0_CONFIG_POD3 = 15 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG0_CONFIG_POD3_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG0_CONFIG_POD4 = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG0_CONFIG_POD4_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG0_CONFIG_POD5 = 25 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG0_CONFIG_POD5_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG0_CONFIG_POD6 = 30 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG0_CONFIG_POD6_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG0_CONFIG_POD7 = 35 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG0_CONFIG_POD7_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG0_CONFIG_POD8 = 40 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG0_CONFIG_POD8_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG0_CONFIG_POD9 = 45 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG0_CONFIG_POD9_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG0_CONFIG_POD10 = 50 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG0_CONFIG_POD10_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG0_CONFIG_RESERVED1 = 55 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG0_CONFIG_RESERVED1_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG0_CONFIG_ACT = 63 ;
+
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG0_CONFIG_POD0 = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG0_CONFIG_POD0_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG0_CONFIG_POD1 = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG0_CONFIG_POD1_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG0_CONFIG_POD2 = 10 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG0_CONFIG_POD2_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG0_CONFIG_POD3 = 15 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG0_CONFIG_POD3_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG0_CONFIG_POD4 = 20 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG0_CONFIG_POD4_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG0_CONFIG_POD5 = 25 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG0_CONFIG_POD5_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG0_CONFIG_POD6 = 30 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG0_CONFIG_POD6_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG0_CONFIG_POD7 = 35 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG0_CONFIG_POD7_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG0_CONFIG_POD8 = 40 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG0_CONFIG_POD8_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG0_CONFIG_POD9 = 45 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG0_CONFIG_POD9_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG0_CONFIG_POD10 = 50 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG0_CONFIG_POD10_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG0_CONFIG_RESERVED1 = 55 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG0_CONFIG_RESERVED1_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG0_CONFIG_ACT = 63 ;
+
+static const uint8_t P9N2_PU_NPU_SM0_DEBUG0_CONFIG_POD0 = 0 ;
+static const uint8_t P9N2_PU_NPU_SM0_DEBUG0_CONFIG_POD0_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM0_DEBUG0_CONFIG_POD1 = 5 ;
+static const uint8_t P9N2_PU_NPU_SM0_DEBUG0_CONFIG_POD1_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM0_DEBUG0_CONFIG_POD2 = 10 ;
+static const uint8_t P9N2_PU_NPU_SM0_DEBUG0_CONFIG_POD2_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM0_DEBUG0_CONFIG_POD3 = 15 ;
+static const uint8_t P9N2_PU_NPU_SM0_DEBUG0_CONFIG_POD3_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM0_DEBUG0_CONFIG_POD4 = 20 ;
+static const uint8_t P9N2_PU_NPU_SM0_DEBUG0_CONFIG_POD4_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM0_DEBUG0_CONFIG_POD5 = 25 ;
+static const uint8_t P9N2_PU_NPU_SM0_DEBUG0_CONFIG_POD5_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM0_DEBUG0_CONFIG_POD6 = 30 ;
+static const uint8_t P9N2_PU_NPU_SM0_DEBUG0_CONFIG_POD6_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM0_DEBUG0_CONFIG_POD7 = 35 ;
+static const uint8_t P9N2_PU_NPU_SM0_DEBUG0_CONFIG_POD7_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM0_DEBUG0_CONFIG_POD8 = 40 ;
+static const uint8_t P9N2_PU_NPU_SM0_DEBUG0_CONFIG_POD8_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM0_DEBUG0_CONFIG_POD9 = 45 ;
+static const uint8_t P9N2_PU_NPU_SM0_DEBUG0_CONFIG_POD9_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM0_DEBUG0_CONFIG_POD10 = 50 ;
+static const uint8_t P9N2_PU_NPU_SM0_DEBUG0_CONFIG_POD10_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM0_DEBUG0_CONFIG_RESERVED1 = 55 ;
+static const uint8_t P9N2_PU_NPU_SM0_DEBUG0_CONFIG_RESERVED1_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_SM0_DEBUG0_CONFIG_ACT = 63 ;
+
+static const uint8_t P9N2_PU_NPU_SM1_DEBUG0_CONFIG_POD0 = 0 ;
+static const uint8_t P9N2_PU_NPU_SM1_DEBUG0_CONFIG_POD0_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM1_DEBUG0_CONFIG_POD1 = 5 ;
+static const uint8_t P9N2_PU_NPU_SM1_DEBUG0_CONFIG_POD1_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM1_DEBUG0_CONFIG_POD2 = 10 ;
+static const uint8_t P9N2_PU_NPU_SM1_DEBUG0_CONFIG_POD2_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM1_DEBUG0_CONFIG_POD3 = 15 ;
+static const uint8_t P9N2_PU_NPU_SM1_DEBUG0_CONFIG_POD3_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM1_DEBUG0_CONFIG_POD4 = 20 ;
+static const uint8_t P9N2_PU_NPU_SM1_DEBUG0_CONFIG_POD4_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM1_DEBUG0_CONFIG_POD5 = 25 ;
+static const uint8_t P9N2_PU_NPU_SM1_DEBUG0_CONFIG_POD5_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM1_DEBUG0_CONFIG_POD6 = 30 ;
+static const uint8_t P9N2_PU_NPU_SM1_DEBUG0_CONFIG_POD6_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM1_DEBUG0_CONFIG_POD7 = 35 ;
+static const uint8_t P9N2_PU_NPU_SM1_DEBUG0_CONFIG_POD7_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM1_DEBUG0_CONFIG_POD8 = 40 ;
+static const uint8_t P9N2_PU_NPU_SM1_DEBUG0_CONFIG_POD8_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM1_DEBUG0_CONFIG_POD9 = 45 ;
+static const uint8_t P9N2_PU_NPU_SM1_DEBUG0_CONFIG_POD9_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM1_DEBUG0_CONFIG_POD10 = 50 ;
+static const uint8_t P9N2_PU_NPU_SM1_DEBUG0_CONFIG_POD10_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM1_DEBUG0_CONFIG_RESERVED1 = 55 ;
+static const uint8_t P9N2_PU_NPU_SM1_DEBUG0_CONFIG_RESERVED1_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_SM1_DEBUG0_CONFIG_ACT = 63 ;
+
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG0_CONFIG_POD0 = 0 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG0_CONFIG_POD0_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG0_CONFIG_POD1 = 5 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG0_CONFIG_POD1_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG0_CONFIG_POD2 = 10 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG0_CONFIG_POD2_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG0_CONFIG_POD3 = 15 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG0_CONFIG_POD3_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG0_CONFIG_POD4 = 20 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG0_CONFIG_POD4_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG0_CONFIG_POD5 = 25 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG0_CONFIG_POD5_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG0_CONFIG_POD6 = 30 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG0_CONFIG_POD6_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG0_CONFIG_POD7 = 35 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG0_CONFIG_POD7_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG0_CONFIG_POD8 = 40 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG0_CONFIG_POD8_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG0_CONFIG_POD9 = 45 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG0_CONFIG_POD9_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG0_CONFIG_POD10 = 50 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG0_CONFIG_POD10_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG0_CONFIG_RESERVED1 = 55 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG0_CONFIG_RESERVED1_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG0_CONFIG_ACT = 63 ;
+
+static const uint8_t P9N2_NV_DEBUG0_CONFIG_POD0 = 0 ;
+static const uint8_t P9N2_NV_DEBUG0_CONFIG_POD0_LEN = 5 ;
+static const uint8_t P9N2_NV_DEBUG0_CONFIG_POD1 = 5 ;
+static const uint8_t P9N2_NV_DEBUG0_CONFIG_POD1_LEN = 5 ;
+static const uint8_t P9N2_NV_DEBUG0_CONFIG_POD2 = 10 ;
+static const uint8_t P9N2_NV_DEBUG0_CONFIG_POD2_LEN = 5 ;
+static const uint8_t P9N2_NV_DEBUG0_CONFIG_POD3 = 15 ;
+static const uint8_t P9N2_NV_DEBUG0_CONFIG_POD3_LEN = 5 ;
+static const uint8_t P9N2_NV_DEBUG0_CONFIG_POD4 = 20 ;
+static const uint8_t P9N2_NV_DEBUG0_CONFIG_POD4_LEN = 5 ;
+static const uint8_t P9N2_NV_DEBUG0_CONFIG_POD5 = 25 ;
+static const uint8_t P9N2_NV_DEBUG0_CONFIG_POD5_LEN = 5 ;
+static const uint8_t P9N2_NV_DEBUG0_CONFIG_POD6 = 30 ;
+static const uint8_t P9N2_NV_DEBUG0_CONFIG_POD6_LEN = 5 ;
+static const uint8_t P9N2_NV_DEBUG0_CONFIG_POD7 = 35 ;
+static const uint8_t P9N2_NV_DEBUG0_CONFIG_POD7_LEN = 5 ;
+static const uint8_t P9N2_NV_DEBUG0_CONFIG_POD8 = 40 ;
+static const uint8_t P9N2_NV_DEBUG0_CONFIG_POD8_LEN = 5 ;
+static const uint8_t P9N2_NV_DEBUG0_CONFIG_POD9 = 45 ;
+static const uint8_t P9N2_NV_DEBUG0_CONFIG_POD9_LEN = 5 ;
+static const uint8_t P9N2_NV_DEBUG0_CONFIG_POD10 = 50 ;
+static const uint8_t P9N2_NV_DEBUG0_CONFIG_POD10_LEN = 5 ;
+static const uint8_t P9N2_NV_DEBUG0_CONFIG_RESERVED1 = 55 ;
+static const uint8_t P9N2_NV_DEBUG0_CONFIG_RESERVED1_LEN = 8 ;
+static const uint8_t P9N2_NV_DEBUG0_CONFIG_ACT = 63 ;
+
+static const uint8_t P9N2_PU_NPU1_SM0_DEBUG0_CONFIG_POD0 = 0 ;
+static const uint8_t P9N2_PU_NPU1_SM0_DEBUG0_CONFIG_POD0_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM0_DEBUG0_CONFIG_POD1 = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM0_DEBUG0_CONFIG_POD1_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM0_DEBUG0_CONFIG_POD2 = 10 ;
+static const uint8_t P9N2_PU_NPU1_SM0_DEBUG0_CONFIG_POD2_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM0_DEBUG0_CONFIG_POD3 = 15 ;
+static const uint8_t P9N2_PU_NPU1_SM0_DEBUG0_CONFIG_POD3_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM0_DEBUG0_CONFIG_POD4 = 20 ;
+static const uint8_t P9N2_PU_NPU1_SM0_DEBUG0_CONFIG_POD4_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM0_DEBUG0_CONFIG_POD5 = 25 ;
+static const uint8_t P9N2_PU_NPU1_SM0_DEBUG0_CONFIG_POD5_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM0_DEBUG0_CONFIG_POD6 = 30 ;
+static const uint8_t P9N2_PU_NPU1_SM0_DEBUG0_CONFIG_POD6_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM0_DEBUG0_CONFIG_POD7 = 35 ;
+static const uint8_t P9N2_PU_NPU1_SM0_DEBUG0_CONFIG_POD7_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM0_DEBUG0_CONFIG_POD8 = 40 ;
+static const uint8_t P9N2_PU_NPU1_SM0_DEBUG0_CONFIG_POD8_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM0_DEBUG0_CONFIG_POD9 = 45 ;
+static const uint8_t P9N2_PU_NPU1_SM0_DEBUG0_CONFIG_POD9_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM0_DEBUG0_CONFIG_POD10 = 50 ;
+static const uint8_t P9N2_PU_NPU1_SM0_DEBUG0_CONFIG_POD10_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM0_DEBUG0_CONFIG_RESERVED1 = 55 ;
+static const uint8_t P9N2_PU_NPU1_SM0_DEBUG0_CONFIG_RESERVED1_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU1_SM0_DEBUG0_CONFIG_ACT = 63 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG0_CONFIG_POD0 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG0_CONFIG_POD0_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG0_CONFIG_POD1 = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG0_CONFIG_POD1_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG0_CONFIG_POD2 = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG0_CONFIG_POD2_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG0_CONFIG_POD3 = 15 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG0_CONFIG_POD3_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG0_CONFIG_POD4 = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG0_CONFIG_POD4_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG0_CONFIG_POD5 = 25 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG0_CONFIG_POD5_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG0_CONFIG_POD6 = 30 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG0_CONFIG_POD6_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG0_CONFIG_POD7 = 35 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG0_CONFIG_POD7_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG0_CONFIG_POD8 = 40 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG0_CONFIG_POD8_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG0_CONFIG_POD9 = 45 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG0_CONFIG_POD9_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG0_CONFIG_POD10 = 50 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG0_CONFIG_POD10_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG0_CONFIG_RESERVED1 = 55 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG0_CONFIG_RESERVED1_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG0_CONFIG_ACT = 63 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG1_CONFIG_POD0 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG1_CONFIG_POD0_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG1_CONFIG_POD1 = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG1_CONFIG_POD1_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG1_CONFIG_POD2 = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG1_CONFIG_POD2_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG1_CONFIG_POD3 = 15 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG1_CONFIG_POD3_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG1_CONFIG_POD4 = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG1_CONFIG_POD4_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG1_CONFIG_POD5 = 25 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG1_CONFIG_POD5_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG1_CONFIG_POD6 = 30 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG1_CONFIG_POD6_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG1_CONFIG_POD7 = 35 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG1_CONFIG_POD7_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG1_CONFIG_POD8 = 40 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG1_CONFIG_POD8_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG1_CONFIG_POD9 = 45 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG1_CONFIG_POD9_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG1_CONFIG_POD10 = 50 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG1_CONFIG_POD10_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG1_CONFIG_RESERVED1 = 55 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG1_CONFIG_RESERVED1_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG1_CONFIG_ACT = 63 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG1_CONFIG_POD0 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG1_CONFIG_POD0_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG1_CONFIG_POD1 = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG1_CONFIG_POD1_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG1_CONFIG_POD2 = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG1_CONFIG_POD2_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG1_CONFIG_POD3 = 15 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG1_CONFIG_POD3_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG1_CONFIG_POD4 = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG1_CONFIG_POD4_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG1_CONFIG_POD5 = 25 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG1_CONFIG_POD5_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG1_CONFIG_POD6 = 30 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG1_CONFIG_POD6_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG1_CONFIG_POD7 = 35 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG1_CONFIG_POD7_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG1_CONFIG_POD8 = 40 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG1_CONFIG_POD8_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG1_CONFIG_POD9 = 45 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG1_CONFIG_POD9_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG1_CONFIG_POD10 = 50 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG1_CONFIG_POD10_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG1_CONFIG_RESERVED1 = 55 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG1_CONFIG_RESERVED1_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG1_CONFIG_ACT = 63 ;
+
+static const uint8_t P9N2_PU_NPU1_SM1_DEBUG1_CONFIG_POD0 = 0 ;
+static const uint8_t P9N2_PU_NPU1_SM1_DEBUG1_CONFIG_POD0_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM1_DEBUG1_CONFIG_POD1 = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM1_DEBUG1_CONFIG_POD1_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM1_DEBUG1_CONFIG_POD2 = 10 ;
+static const uint8_t P9N2_PU_NPU1_SM1_DEBUG1_CONFIG_POD2_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM1_DEBUG1_CONFIG_POD3 = 15 ;
+static const uint8_t P9N2_PU_NPU1_SM1_DEBUG1_CONFIG_POD3_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM1_DEBUG1_CONFIG_POD4 = 20 ;
+static const uint8_t P9N2_PU_NPU1_SM1_DEBUG1_CONFIG_POD4_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM1_DEBUG1_CONFIG_POD5 = 25 ;
+static const uint8_t P9N2_PU_NPU1_SM1_DEBUG1_CONFIG_POD5_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM1_DEBUG1_CONFIG_POD6 = 30 ;
+static const uint8_t P9N2_PU_NPU1_SM1_DEBUG1_CONFIG_POD6_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM1_DEBUG1_CONFIG_POD7 = 35 ;
+static const uint8_t P9N2_PU_NPU1_SM1_DEBUG1_CONFIG_POD7_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM1_DEBUG1_CONFIG_POD8 = 40 ;
+static const uint8_t P9N2_PU_NPU1_SM1_DEBUG1_CONFIG_POD8_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM1_DEBUG1_CONFIG_POD9 = 45 ;
+static const uint8_t P9N2_PU_NPU1_SM1_DEBUG1_CONFIG_POD9_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM1_DEBUG1_CONFIG_POD10 = 50 ;
+static const uint8_t P9N2_PU_NPU1_SM1_DEBUG1_CONFIG_POD10_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM1_DEBUG1_CONFIG_RESERVED1 = 55 ;
+static const uint8_t P9N2_PU_NPU1_SM1_DEBUG1_CONFIG_RESERVED1_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU1_SM1_DEBUG1_CONFIG_ACT = 63 ;
+
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG1_CONFIG_POD0 = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG1_CONFIG_POD0_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG1_CONFIG_POD1 = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG1_CONFIG_POD1_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG1_CONFIG_POD2 = 10 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG1_CONFIG_POD2_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG1_CONFIG_POD3 = 15 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG1_CONFIG_POD3_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG1_CONFIG_POD4 = 20 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG1_CONFIG_POD4_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG1_CONFIG_POD5 = 25 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG1_CONFIG_POD5_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG1_CONFIG_POD6 = 30 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG1_CONFIG_POD6_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG1_CONFIG_POD7 = 35 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG1_CONFIG_POD7_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG1_CONFIG_POD8 = 40 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG1_CONFIG_POD8_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG1_CONFIG_POD9 = 45 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG1_CONFIG_POD9_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG1_CONFIG_POD10 = 50 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG1_CONFIG_POD10_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG1_CONFIG_RESERVED1 = 55 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG1_CONFIG_RESERVED1_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG1_CONFIG_ACT = 63 ;
+
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG1_CONFIG_POD0 = 0 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG1_CONFIG_POD0_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG1_CONFIG_POD1 = 5 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG1_CONFIG_POD1_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG1_CONFIG_POD2 = 10 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG1_CONFIG_POD2_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG1_CONFIG_POD3 = 15 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG1_CONFIG_POD3_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG1_CONFIG_POD4 = 20 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG1_CONFIG_POD4_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG1_CONFIG_POD5 = 25 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG1_CONFIG_POD5_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG1_CONFIG_POD6 = 30 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG1_CONFIG_POD6_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG1_CONFIG_POD7 = 35 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG1_CONFIG_POD7_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG1_CONFIG_POD8 = 40 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG1_CONFIG_POD8_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG1_CONFIG_POD9 = 45 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG1_CONFIG_POD9_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG1_CONFIG_POD10 = 50 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG1_CONFIG_POD10_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG1_CONFIG_RESERVED1 = 55 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG1_CONFIG_RESERVED1_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG1_CONFIG_ACT = 63 ;
+
+static const uint8_t P9N2__SM2_DEBUG1_CONFIG_POD0 = 0 ;
+static const uint8_t P9N2__SM2_DEBUG1_CONFIG_POD0_LEN = 5 ;
+static const uint8_t P9N2__SM2_DEBUG1_CONFIG_POD1 = 5 ;
+static const uint8_t P9N2__SM2_DEBUG1_CONFIG_POD1_LEN = 5 ;
+static const uint8_t P9N2__SM2_DEBUG1_CONFIG_POD2 = 10 ;
+static const uint8_t P9N2__SM2_DEBUG1_CONFIG_POD2_LEN = 5 ;
+static const uint8_t P9N2__SM2_DEBUG1_CONFIG_POD3 = 15 ;
+static const uint8_t P9N2__SM2_DEBUG1_CONFIG_POD3_LEN = 5 ;
+static const uint8_t P9N2__SM2_DEBUG1_CONFIG_POD4 = 20 ;
+static const uint8_t P9N2__SM2_DEBUG1_CONFIG_POD4_LEN = 5 ;
+static const uint8_t P9N2__SM2_DEBUG1_CONFIG_POD5 = 25 ;
+static const uint8_t P9N2__SM2_DEBUG1_CONFIG_POD5_LEN = 5 ;
+static const uint8_t P9N2__SM2_DEBUG1_CONFIG_POD6 = 30 ;
+static const uint8_t P9N2__SM2_DEBUG1_CONFIG_POD6_LEN = 5 ;
+static const uint8_t P9N2__SM2_DEBUG1_CONFIG_POD7 = 35 ;
+static const uint8_t P9N2__SM2_DEBUG1_CONFIG_POD7_LEN = 5 ;
+static const uint8_t P9N2__SM2_DEBUG1_CONFIG_POD8 = 40 ;
+static const uint8_t P9N2__SM2_DEBUG1_CONFIG_POD8_LEN = 5 ;
+static const uint8_t P9N2__SM2_DEBUG1_CONFIG_POD9 = 45 ;
+static const uint8_t P9N2__SM2_DEBUG1_CONFIG_POD9_LEN = 5 ;
+static const uint8_t P9N2__SM2_DEBUG1_CONFIG_POD10 = 50 ;
+static const uint8_t P9N2__SM2_DEBUG1_CONFIG_POD10_LEN = 5 ;
+static const uint8_t P9N2__SM2_DEBUG1_CONFIG_RESERVED1 = 55 ;
+static const uint8_t P9N2__SM2_DEBUG1_CONFIG_RESERVED1_LEN = 8 ;
+static const uint8_t P9N2__SM2_DEBUG1_CONFIG_ACT = 63 ;
+
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG1_CONFIG_POD0 = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG1_CONFIG_POD0_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG1_CONFIG_POD1 = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG1_CONFIG_POD1_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG1_CONFIG_POD2 = 10 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG1_CONFIG_POD2_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG1_CONFIG_POD3 = 15 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG1_CONFIG_POD3_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG1_CONFIG_POD4 = 20 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG1_CONFIG_POD4_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG1_CONFIG_POD5 = 25 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG1_CONFIG_POD5_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG1_CONFIG_POD6 = 30 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG1_CONFIG_POD6_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG1_CONFIG_POD7 = 35 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG1_CONFIG_POD7_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG1_CONFIG_POD8 = 40 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG1_CONFIG_POD8_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG1_CONFIG_POD9 = 45 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG1_CONFIG_POD9_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG1_CONFIG_POD10 = 50 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG1_CONFIG_POD10_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG1_CONFIG_RESERVED1 = 55 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG1_CONFIG_RESERVED1_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG1_CONFIG_ACT = 63 ;
+
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG1_CONFIG_POD0 = 0 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG1_CONFIG_POD0_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG1_CONFIG_POD1 = 5 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG1_CONFIG_POD1_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG1_CONFIG_POD2 = 10 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG1_CONFIG_POD2_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG1_CONFIG_POD3 = 15 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG1_CONFIG_POD3_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG1_CONFIG_POD4 = 20 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG1_CONFIG_POD4_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG1_CONFIG_POD5 = 25 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG1_CONFIG_POD5_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG1_CONFIG_POD6 = 30 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG1_CONFIG_POD6_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG1_CONFIG_POD7 = 35 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG1_CONFIG_POD7_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG1_CONFIG_POD8 = 40 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG1_CONFIG_POD8_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG1_CONFIG_POD9 = 45 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG1_CONFIG_POD9_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG1_CONFIG_POD10 = 50 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG1_CONFIG_POD10_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG1_CONFIG_RESERVED1 = 55 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG1_CONFIG_RESERVED1_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG1_CONFIG_ACT = 63 ;
+
+static const uint8_t P9N2__SM1_DEBUG1_CONFIG_POD0 = 0 ;
+static const uint8_t P9N2__SM1_DEBUG1_CONFIG_POD0_LEN = 5 ;
+static const uint8_t P9N2__SM1_DEBUG1_CONFIG_POD1 = 5 ;
+static const uint8_t P9N2__SM1_DEBUG1_CONFIG_POD1_LEN = 5 ;
+static const uint8_t P9N2__SM1_DEBUG1_CONFIG_POD2 = 10 ;
+static const uint8_t P9N2__SM1_DEBUG1_CONFIG_POD2_LEN = 5 ;
+static const uint8_t P9N2__SM1_DEBUG1_CONFIG_POD3 = 15 ;
+static const uint8_t P9N2__SM1_DEBUG1_CONFIG_POD3_LEN = 5 ;
+static const uint8_t P9N2__SM1_DEBUG1_CONFIG_POD4 = 20 ;
+static const uint8_t P9N2__SM1_DEBUG1_CONFIG_POD4_LEN = 5 ;
+static const uint8_t P9N2__SM1_DEBUG1_CONFIG_POD5 = 25 ;
+static const uint8_t P9N2__SM1_DEBUG1_CONFIG_POD5_LEN = 5 ;
+static const uint8_t P9N2__SM1_DEBUG1_CONFIG_POD6 = 30 ;
+static const uint8_t P9N2__SM1_DEBUG1_CONFIG_POD6_LEN = 5 ;
+static const uint8_t P9N2__SM1_DEBUG1_CONFIG_POD7 = 35 ;
+static const uint8_t P9N2__SM1_DEBUG1_CONFIG_POD7_LEN = 5 ;
+static const uint8_t P9N2__SM1_DEBUG1_CONFIG_POD8 = 40 ;
+static const uint8_t P9N2__SM1_DEBUG1_CONFIG_POD8_LEN = 5 ;
+static const uint8_t P9N2__SM1_DEBUG1_CONFIG_POD9 = 45 ;
+static const uint8_t P9N2__SM1_DEBUG1_CONFIG_POD9_LEN = 5 ;
+static const uint8_t P9N2__SM1_DEBUG1_CONFIG_POD10 = 50 ;
+static const uint8_t P9N2__SM1_DEBUG1_CONFIG_POD10_LEN = 5 ;
+static const uint8_t P9N2__SM1_DEBUG1_CONFIG_RESERVED1 = 55 ;
+static const uint8_t P9N2__SM1_DEBUG1_CONFIG_RESERVED1_LEN = 8 ;
+static const uint8_t P9N2__SM1_DEBUG1_CONFIG_ACT = 63 ;
+
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG1_CONFIG_POD0 = 0 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG1_CONFIG_POD0_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG1_CONFIG_POD1 = 5 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG1_CONFIG_POD1_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG1_CONFIG_POD2 = 10 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG1_CONFIG_POD2_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG1_CONFIG_POD3 = 15 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG1_CONFIG_POD3_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG1_CONFIG_POD4 = 20 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG1_CONFIG_POD4_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG1_CONFIG_POD5 = 25 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG1_CONFIG_POD5_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG1_CONFIG_POD6 = 30 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG1_CONFIG_POD6_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG1_CONFIG_POD7 = 35 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG1_CONFIG_POD7_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG1_CONFIG_POD8 = 40 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG1_CONFIG_POD8_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG1_CONFIG_POD9 = 45 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG1_CONFIG_POD9_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG1_CONFIG_POD10 = 50 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG1_CONFIG_POD10_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG1_CONFIG_RESERVED1 = 55 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG1_CONFIG_RESERVED1_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG1_CONFIG_ACT = 63 ;
+
+static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG1_CONFIG_POD0 = 0 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG1_CONFIG_POD0_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG1_CONFIG_POD1 = 5 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG1_CONFIG_POD1_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG1_CONFIG_POD2 = 10 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG1_CONFIG_POD2_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG1_CONFIG_POD3 = 15 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG1_CONFIG_POD3_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG1_CONFIG_POD4 = 20 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG1_CONFIG_POD4_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG1_CONFIG_POD5 = 25 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG1_CONFIG_POD5_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG1_CONFIG_POD6 = 30 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG1_CONFIG_POD6_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG1_CONFIG_POD7 = 35 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG1_CONFIG_POD7_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG1_CONFIG_POD8 = 40 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG1_CONFIG_POD8_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG1_CONFIG_POD9 = 45 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG1_CONFIG_POD9_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG1_CONFIG_POD10 = 50 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG1_CONFIG_POD10_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG1_CONFIG_RESERVED1 = 55 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG1_CONFIG_RESERVED1_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_DEBUG1_CONFIG_ACT = 63 ;
+
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG1_CONFIG_POD0 = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG1_CONFIG_POD0_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG1_CONFIG_POD1 = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG1_CONFIG_POD1_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG1_CONFIG_POD2 = 10 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG1_CONFIG_POD2_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG1_CONFIG_POD3 = 15 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG1_CONFIG_POD3_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG1_CONFIG_POD4 = 20 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG1_CONFIG_POD4_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG1_CONFIG_POD5 = 25 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG1_CONFIG_POD5_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG1_CONFIG_POD6 = 30 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG1_CONFIG_POD6_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG1_CONFIG_POD7 = 35 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG1_CONFIG_POD7_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG1_CONFIG_POD8 = 40 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG1_CONFIG_POD8_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG1_CONFIG_POD9 = 45 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG1_CONFIG_POD9_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG1_CONFIG_POD10 = 50 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG1_CONFIG_POD10_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG1_CONFIG_RESERVED1 = 55 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG1_CONFIG_RESERVED1_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG1_CONFIG_ACT = 63 ;
+
+static const uint8_t P9N2__SM0_DEBUG1_CONFIG_POD0 = 0 ;
+static const uint8_t P9N2__SM0_DEBUG1_CONFIG_POD0_LEN = 5 ;
+static const uint8_t P9N2__SM0_DEBUG1_CONFIG_POD1 = 5 ;
+static const uint8_t P9N2__SM0_DEBUG1_CONFIG_POD1_LEN = 5 ;
+static const uint8_t P9N2__SM0_DEBUG1_CONFIG_POD2 = 10 ;
+static const uint8_t P9N2__SM0_DEBUG1_CONFIG_POD2_LEN = 5 ;
+static const uint8_t P9N2__SM0_DEBUG1_CONFIG_POD3 = 15 ;
+static const uint8_t P9N2__SM0_DEBUG1_CONFIG_POD3_LEN = 5 ;
+static const uint8_t P9N2__SM0_DEBUG1_CONFIG_POD4 = 20 ;
+static const uint8_t P9N2__SM0_DEBUG1_CONFIG_POD4_LEN = 5 ;
+static const uint8_t P9N2__SM0_DEBUG1_CONFIG_POD5 = 25 ;
+static const uint8_t P9N2__SM0_DEBUG1_CONFIG_POD5_LEN = 5 ;
+static const uint8_t P9N2__SM0_DEBUG1_CONFIG_POD6 = 30 ;
+static const uint8_t P9N2__SM0_DEBUG1_CONFIG_POD6_LEN = 5 ;
+static const uint8_t P9N2__SM0_DEBUG1_CONFIG_POD7 = 35 ;
+static const uint8_t P9N2__SM0_DEBUG1_CONFIG_POD7_LEN = 5 ;
+static const uint8_t P9N2__SM0_DEBUG1_CONFIG_POD8 = 40 ;
+static const uint8_t P9N2__SM0_DEBUG1_CONFIG_POD8_LEN = 5 ;
+static const uint8_t P9N2__SM0_DEBUG1_CONFIG_POD9 = 45 ;
+static const uint8_t P9N2__SM0_DEBUG1_CONFIG_POD9_LEN = 5 ;
+static const uint8_t P9N2__SM0_DEBUG1_CONFIG_POD10 = 50 ;
+static const uint8_t P9N2__SM0_DEBUG1_CONFIG_POD10_LEN = 5 ;
+static const uint8_t P9N2__SM0_DEBUG1_CONFIG_RESERVED1 = 55 ;
+static const uint8_t P9N2__SM0_DEBUG1_CONFIG_RESERVED1_LEN = 8 ;
+static const uint8_t P9N2__SM0_DEBUG1_CONFIG_ACT = 63 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG1_CONFIG_POD0 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG1_CONFIG_POD0_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG1_CONFIG_POD1 = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG1_CONFIG_POD1_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG1_CONFIG_POD2 = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG1_CONFIG_POD2_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG1_CONFIG_POD3 = 15 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG1_CONFIG_POD3_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG1_CONFIG_POD4 = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG1_CONFIG_POD4_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG1_CONFIG_POD5 = 25 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG1_CONFIG_POD5_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG1_CONFIG_POD6 = 30 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG1_CONFIG_POD6_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG1_CONFIG_POD7 = 35 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG1_CONFIG_POD7_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG1_CONFIG_POD8 = 40 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG1_CONFIG_POD8_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG1_CONFIG_POD9 = 45 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG1_CONFIG_POD9_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG1_CONFIG_POD10 = 50 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG1_CONFIG_POD10_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG1_CONFIG_RESERVED1 = 55 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG1_CONFIG_RESERVED1_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG1_CONFIG_ACT = 63 ;
+
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG1_CONFIG_POD0 = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG1_CONFIG_POD0_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG1_CONFIG_POD1 = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG1_CONFIG_POD1_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG1_CONFIG_POD2 = 10 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG1_CONFIG_POD2_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG1_CONFIG_POD3 = 15 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG1_CONFIG_POD3_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG1_CONFIG_POD4 = 20 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG1_CONFIG_POD4_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG1_CONFIG_POD5 = 25 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG1_CONFIG_POD5_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG1_CONFIG_POD6 = 30 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG1_CONFIG_POD6_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG1_CONFIG_POD7 = 35 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG1_CONFIG_POD7_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG1_CONFIG_POD8 = 40 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG1_CONFIG_POD8_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG1_CONFIG_POD9 = 45 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG1_CONFIG_POD9_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG1_CONFIG_POD10 = 50 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG1_CONFIG_POD10_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG1_CONFIG_RESERVED1 = 55 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG1_CONFIG_RESERVED1_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG1_CONFIG_ACT = 63 ;
+
+static const uint8_t P9N2_PU_NPU_SM0_DEBUG1_CONFIG_POD0 = 0 ;
+static const uint8_t P9N2_PU_NPU_SM0_DEBUG1_CONFIG_POD0_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM0_DEBUG1_CONFIG_POD1 = 5 ;
+static const uint8_t P9N2_PU_NPU_SM0_DEBUG1_CONFIG_POD1_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM0_DEBUG1_CONFIG_POD2 = 10 ;
+static const uint8_t P9N2_PU_NPU_SM0_DEBUG1_CONFIG_POD2_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM0_DEBUG1_CONFIG_POD3 = 15 ;
+static const uint8_t P9N2_PU_NPU_SM0_DEBUG1_CONFIG_POD3_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM0_DEBUG1_CONFIG_POD4 = 20 ;
+static const uint8_t P9N2_PU_NPU_SM0_DEBUG1_CONFIG_POD4_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM0_DEBUG1_CONFIG_POD5 = 25 ;
+static const uint8_t P9N2_PU_NPU_SM0_DEBUG1_CONFIG_POD5_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM0_DEBUG1_CONFIG_POD6 = 30 ;
+static const uint8_t P9N2_PU_NPU_SM0_DEBUG1_CONFIG_POD6_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM0_DEBUG1_CONFIG_POD7 = 35 ;
+static const uint8_t P9N2_PU_NPU_SM0_DEBUG1_CONFIG_POD7_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM0_DEBUG1_CONFIG_POD8 = 40 ;
+static const uint8_t P9N2_PU_NPU_SM0_DEBUG1_CONFIG_POD8_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM0_DEBUG1_CONFIG_POD9 = 45 ;
+static const uint8_t P9N2_PU_NPU_SM0_DEBUG1_CONFIG_POD9_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM0_DEBUG1_CONFIG_POD10 = 50 ;
+static const uint8_t P9N2_PU_NPU_SM0_DEBUG1_CONFIG_POD10_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM0_DEBUG1_CONFIG_RESERVED1 = 55 ;
+static const uint8_t P9N2_PU_NPU_SM0_DEBUG1_CONFIG_RESERVED1_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_SM0_DEBUG1_CONFIG_ACT = 63 ;
+
+static const uint8_t P9N2_PU_NPU_SM1_DEBUG1_CONFIG_POD0 = 0 ;
+static const uint8_t P9N2_PU_NPU_SM1_DEBUG1_CONFIG_POD0_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM1_DEBUG1_CONFIG_POD1 = 5 ;
+static const uint8_t P9N2_PU_NPU_SM1_DEBUG1_CONFIG_POD1_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM1_DEBUG1_CONFIG_POD2 = 10 ;
+static const uint8_t P9N2_PU_NPU_SM1_DEBUG1_CONFIG_POD2_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM1_DEBUG1_CONFIG_POD3 = 15 ;
+static const uint8_t P9N2_PU_NPU_SM1_DEBUG1_CONFIG_POD3_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM1_DEBUG1_CONFIG_POD4 = 20 ;
+static const uint8_t P9N2_PU_NPU_SM1_DEBUG1_CONFIG_POD4_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM1_DEBUG1_CONFIG_POD5 = 25 ;
+static const uint8_t P9N2_PU_NPU_SM1_DEBUG1_CONFIG_POD5_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM1_DEBUG1_CONFIG_POD6 = 30 ;
+static const uint8_t P9N2_PU_NPU_SM1_DEBUG1_CONFIG_POD6_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM1_DEBUG1_CONFIG_POD7 = 35 ;
+static const uint8_t P9N2_PU_NPU_SM1_DEBUG1_CONFIG_POD7_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM1_DEBUG1_CONFIG_POD8 = 40 ;
+static const uint8_t P9N2_PU_NPU_SM1_DEBUG1_CONFIG_POD8_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM1_DEBUG1_CONFIG_POD9 = 45 ;
+static const uint8_t P9N2_PU_NPU_SM1_DEBUG1_CONFIG_POD9_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM1_DEBUG1_CONFIG_POD10 = 50 ;
+static const uint8_t P9N2_PU_NPU_SM1_DEBUG1_CONFIG_POD10_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM1_DEBUG1_CONFIG_RESERVED1 = 55 ;
+static const uint8_t P9N2_PU_NPU_SM1_DEBUG1_CONFIG_RESERVED1_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_SM1_DEBUG1_CONFIG_ACT = 63 ;
+
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG1_CONFIG_POD0 = 0 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG1_CONFIG_POD0_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG1_CONFIG_POD1 = 5 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG1_CONFIG_POD1_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG1_CONFIG_POD2 = 10 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG1_CONFIG_POD2_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG1_CONFIG_POD3 = 15 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG1_CONFIG_POD3_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG1_CONFIG_POD4 = 20 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG1_CONFIG_POD4_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG1_CONFIG_POD5 = 25 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG1_CONFIG_POD5_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG1_CONFIG_POD6 = 30 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG1_CONFIG_POD6_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG1_CONFIG_POD7 = 35 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG1_CONFIG_POD7_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG1_CONFIG_POD8 = 40 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG1_CONFIG_POD8_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG1_CONFIG_POD9 = 45 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG1_CONFIG_POD9_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG1_CONFIG_POD10 = 50 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG1_CONFIG_POD10_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG1_CONFIG_RESERVED1 = 55 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG1_CONFIG_RESERVED1_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG1_CONFIG_ACT = 63 ;
+
+static const uint8_t P9N2_NV_DEBUG1_CONFIG_POD0 = 0 ;
+static const uint8_t P9N2_NV_DEBUG1_CONFIG_POD0_LEN = 5 ;
+static const uint8_t P9N2_NV_DEBUG1_CONFIG_POD1 = 5 ;
+static const uint8_t P9N2_NV_DEBUG1_CONFIG_POD1_LEN = 5 ;
+static const uint8_t P9N2_NV_DEBUG1_CONFIG_POD2 = 10 ;
+static const uint8_t P9N2_NV_DEBUG1_CONFIG_POD2_LEN = 5 ;
+static const uint8_t P9N2_NV_DEBUG1_CONFIG_POD3 = 15 ;
+static const uint8_t P9N2_NV_DEBUG1_CONFIG_POD3_LEN = 5 ;
+static const uint8_t P9N2_NV_DEBUG1_CONFIG_POD4 = 20 ;
+static const uint8_t P9N2_NV_DEBUG1_CONFIG_POD4_LEN = 5 ;
+static const uint8_t P9N2_NV_DEBUG1_CONFIG_POD5 = 25 ;
+static const uint8_t P9N2_NV_DEBUG1_CONFIG_POD5_LEN = 5 ;
+static const uint8_t P9N2_NV_DEBUG1_CONFIG_POD6 = 30 ;
+static const uint8_t P9N2_NV_DEBUG1_CONFIG_POD6_LEN = 5 ;
+static const uint8_t P9N2_NV_DEBUG1_CONFIG_POD7 = 35 ;
+static const uint8_t P9N2_NV_DEBUG1_CONFIG_POD7_LEN = 5 ;
+static const uint8_t P9N2_NV_DEBUG1_CONFIG_POD8 = 40 ;
+static const uint8_t P9N2_NV_DEBUG1_CONFIG_POD8_LEN = 5 ;
+static const uint8_t P9N2_NV_DEBUG1_CONFIG_POD9 = 45 ;
+static const uint8_t P9N2_NV_DEBUG1_CONFIG_POD9_LEN = 5 ;
+static const uint8_t P9N2_NV_DEBUG1_CONFIG_POD10 = 50 ;
+static const uint8_t P9N2_NV_DEBUG1_CONFIG_POD10_LEN = 5 ;
+static const uint8_t P9N2_NV_DEBUG1_CONFIG_RESERVED1 = 55 ;
+static const uint8_t P9N2_NV_DEBUG1_CONFIG_RESERVED1_LEN = 8 ;
+static const uint8_t P9N2_NV_DEBUG1_CONFIG_ACT = 63 ;
+
+static const uint8_t P9N2_PU_NPU1_SM0_DEBUG1_CONFIG_POD0 = 0 ;
+static const uint8_t P9N2_PU_NPU1_SM0_DEBUG1_CONFIG_POD0_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM0_DEBUG1_CONFIG_POD1 = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM0_DEBUG1_CONFIG_POD1_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM0_DEBUG1_CONFIG_POD2 = 10 ;
+static const uint8_t P9N2_PU_NPU1_SM0_DEBUG1_CONFIG_POD2_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM0_DEBUG1_CONFIG_POD3 = 15 ;
+static const uint8_t P9N2_PU_NPU1_SM0_DEBUG1_CONFIG_POD3_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM0_DEBUG1_CONFIG_POD4 = 20 ;
+static const uint8_t P9N2_PU_NPU1_SM0_DEBUG1_CONFIG_POD4_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM0_DEBUG1_CONFIG_POD5 = 25 ;
+static const uint8_t P9N2_PU_NPU1_SM0_DEBUG1_CONFIG_POD5_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM0_DEBUG1_CONFIG_POD6 = 30 ;
+static const uint8_t P9N2_PU_NPU1_SM0_DEBUG1_CONFIG_POD6_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM0_DEBUG1_CONFIG_POD7 = 35 ;
+static const uint8_t P9N2_PU_NPU1_SM0_DEBUG1_CONFIG_POD7_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM0_DEBUG1_CONFIG_POD8 = 40 ;
+static const uint8_t P9N2_PU_NPU1_SM0_DEBUG1_CONFIG_POD8_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM0_DEBUG1_CONFIG_POD9 = 45 ;
+static const uint8_t P9N2_PU_NPU1_SM0_DEBUG1_CONFIG_POD9_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM0_DEBUG1_CONFIG_POD10 = 50 ;
+static const uint8_t P9N2_PU_NPU1_SM0_DEBUG1_CONFIG_POD10_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM0_DEBUG1_CONFIG_RESERVED1 = 55 ;
+static const uint8_t P9N2_PU_NPU1_SM0_DEBUG1_CONFIG_RESERVED1_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU1_SM0_DEBUG1_CONFIG_ACT = 63 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG1_CONFIG_POD0 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG1_CONFIG_POD0_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG1_CONFIG_POD1 = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG1_CONFIG_POD1_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG1_CONFIG_POD2 = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG1_CONFIG_POD2_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG1_CONFIG_POD3 = 15 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG1_CONFIG_POD3_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG1_CONFIG_POD4 = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG1_CONFIG_POD4_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG1_CONFIG_POD5 = 25 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG1_CONFIG_POD5_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG1_CONFIG_POD6 = 30 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG1_CONFIG_POD6_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG1_CONFIG_POD7 = 35 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG1_CONFIG_POD7_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG1_CONFIG_POD8 = 40 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG1_CONFIG_POD8_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG1_CONFIG_POD9 = 45 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG1_CONFIG_POD9_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG1_CONFIG_POD10 = 50 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG1_CONFIG_POD10_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG1_CONFIG_RESERVED1 = 55 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG1_CONFIG_RESERVED1_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG1_CONFIG_ACT = 63 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE0 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE1 = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE2 = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE2_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE3 = 18 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE3_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE4 = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE4_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE5 = 30 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE5_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE6 = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE6_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE7 = 42 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE7_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE8 = 48 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE8_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE9 = 54 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE9_LEN = 6 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE0 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE1 = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE2 = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE2_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE3 = 18 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE3_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE4 = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE4_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE5 = 30 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE5_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE6 = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE6_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE7 = 42 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE7_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE8 = 48 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE8_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE9 = 54 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE9_LEN = 6 ;
+
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE0 = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE1 = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE2 = 12 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE2_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE3 = 18 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE3_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE4 = 24 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE4_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE5 = 30 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE5_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE6 = 36 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE6_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE7 = 42 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE7_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE8 = 48 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE8_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE9 = 54 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE9_LEN = 6 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE0 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE1 = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE2 = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE2_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE3 = 18 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE3_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE4 = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE4_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE5 = 30 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE5_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE6 = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE6_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE7 = 42 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE7_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE8 = 48 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE8_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE9 = 54 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE9_LEN = 6 ;
+
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE0 = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE1 = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE2 = 12 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE2_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE3 = 18 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE3_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE4 = 24 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE4_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE5 = 30 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE5_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE6 = 36 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE6_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE7 = 42 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE7_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE8 = 48 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE8_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE9 = 54 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG3_CONFIG_DEBUG_MACH_BYTE9_LEN = 6 ;
+
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE0 = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE1 = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE2 = 12 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE2_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE3 = 18 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE3_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE4 = 24 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE4_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE5 = 30 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE5_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE6 = 36 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE6_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE7 = 42 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE7_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE8 = 48 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE8_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE9 = 54 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE9_LEN = 6 ;
+
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE0 = 0 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE1 = 6 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE2 = 12 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE2_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE3 = 18 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE3_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE4 = 24 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE4_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE5 = 30 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE5_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE6 = 36 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE6_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE7 = 42 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE7_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE8 = 48 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE8_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE9 = 54 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE9_LEN = 6 ;
+
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE0 = 0 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE1 = 6 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE2 = 12 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE2_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE3 = 18 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE3_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE4 = 24 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE4_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE5 = 30 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE5_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE6 = 36 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE6_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE7 = 42 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE7_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE8 = 48 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE8_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE9 = 54 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE9_LEN = 6 ;
+
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE0 = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE1 = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE2 = 12 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE2_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE3 = 18 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE3_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE4 = 24 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE4_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE5 = 30 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE5_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE6 = 36 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE6_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE7 = 42 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE7_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE8 = 48 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE8_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE9 = 54 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG3_CONFIG_DEBUG_MACH_BYTE9_LEN = 6 ;
+
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE0 = 0 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE1 = 6 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE2 = 12 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE2_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE3 = 18 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE3_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE4 = 24 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE4_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE5 = 30 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE5_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE6 = 36 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE6_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE7 = 42 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE7_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE8 = 48 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE8_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE9 = 54 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE9_LEN = 6 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE0 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE1 = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE2 = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE2_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE3 = 18 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE3_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE4 = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE4_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE5 = 30 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE5_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE6 = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE6_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE7 = 42 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE7_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE8 = 48 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE8_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE9 = 54 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG3_CONFIG_DEBUG_MACH_BYTE9_LEN = 6 ;
+
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE0 = 0 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE1 = 6 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE2 = 12 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE2_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE3 = 18 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE3_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE4 = 24 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE4_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE5 = 30 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE5_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE6 = 36 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE6_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE7 = 42 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE7_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE8 = 48 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE8_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE9 = 54 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG3_CONFIG_DEBUG_MACH_BYTE9_LEN = 6 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE10 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE10_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE11 = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE11_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE12 = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE12_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE13 = 18 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE13_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE14 = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE14_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE15 = 30 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE15_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE16 = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE16_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG4_CONFIG_DEBUG_MACH_RESERVED1 = 42 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_DEBUG4_CONFIG_DEBUG_MACH_ACT = 43 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE10 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE10_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE11 = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE11_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE12 = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE12_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE13 = 18 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE13_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE14 = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE14_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE15 = 30 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE15_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE16 = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE16_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG4_CONFIG_DEBUG_MACH_RESERVED1 = 42 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_DEBUG4_CONFIG_DEBUG_MACH_ACT = 43 ;
+
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE10 = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE10_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE11 = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE11_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE12 = 12 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE12_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE13 = 18 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE13_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE14 = 24 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE14_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE15 = 30 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE15_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE16 = 36 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE16_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG4_CONFIG_DEBUG_MACH_RESERVED1 = 42 ;
+static const uint8_t P9N2_PU_NPU2_SM2_DEBUG4_CONFIG_DEBUG_MACH_ACT = 43 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE10 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE10_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE11 = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE11_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE12 = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE12_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE13 = 18 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE13_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE14 = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE14_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE15 = 30 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE15_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE16 = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE16_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG4_CONFIG_DEBUG_MACH_RESERVED1 = 42 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_DEBUG4_CONFIG_DEBUG_MACH_ACT = 43 ;
+
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE10 = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE10_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE11 = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE11_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE12 = 12 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE12_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE13 = 18 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE13_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE14 = 24 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE14_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE15 = 30 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE15_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE16 = 36 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG4_CONFIG_DEBUG_MACH_BYTE16_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG4_CONFIG_DEBUG_MACH_RESERVED1 = 42 ;
+static const uint8_t P9N2_PU_NPU0_SM2_DEBUG4_CONFIG_DEBUG_MACH_ACT = 43 ;
+
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE10 = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE10_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE11 = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE11_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE12 = 12 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE12_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE13 = 18 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE13_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE14 = 24 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE14_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE15 = 30 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE15_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE16 = 36 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE16_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG4_CONFIG_DEBUG_MACH_RESERVED1 = 42 ;
+static const uint8_t P9N2_PU_NPU2_SM1_DEBUG4_CONFIG_DEBUG_MACH_ACT = 43 ;
+
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE10 = 0 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE10_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE11 = 6 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE11_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE12 = 12 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE12_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE13 = 18 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE13_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE14 = 24 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE14_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE15 = 30 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE15_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE16 = 36 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE16_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG4_CONFIG_DEBUG_MACH_RESERVED1 = 42 ;
+static const uint8_t P9N2_PU_NPU0_CTL_DEBUG4_CONFIG_DEBUG_MACH_ACT = 43 ;
+
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE10 = 0 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE10_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE11 = 6 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE11_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE12 = 12 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE12_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE13 = 18 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE13_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE14 = 24 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE14_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE15 = 30 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE15_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE16 = 36 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE16_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG4_CONFIG_DEBUG_MACH_RESERVED1 = 42 ;
+static const uint8_t P9N2_PU_NPU2_CTL_DEBUG4_CONFIG_DEBUG_MACH_ACT = 43 ;
+
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE10 = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE10_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE11 = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE11_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE12 = 12 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE12_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE13 = 18 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE13_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE14 = 24 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE14_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE15 = 30 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE15_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE16 = 36 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG4_CONFIG_DEBUG_MACH_BYTE16_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG4_CONFIG_DEBUG_MACH_RESERVED1 = 42 ;
+static const uint8_t P9N2_PU_NPU0_SM1_DEBUG4_CONFIG_DEBUG_MACH_ACT = 43 ;
+
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE10 = 0 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE10_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE11 = 6 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE11_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE12 = 12 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE12_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE13 = 18 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE13_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE14 = 24 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE14_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE15 = 30 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE15_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE16 = 36 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE16_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG4_CONFIG_DEBUG_MACH_RESERVED1 = 42 ;
+static const uint8_t P9N2_PU_NPU2_DAT_DEBUG4_CONFIG_DEBUG_MACH_ACT = 43 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE10 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE10_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE11 = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE11_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE12 = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE12_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE13 = 18 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE13_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE14 = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE14_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE15 = 30 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE15_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE16 = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG4_CONFIG_DEBUG_MACH_BYTE16_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG4_CONFIG_DEBUG_MACH_RESERVED1 = 42 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_DEBUG4_CONFIG_DEBUG_MACH_ACT = 43 ;
+
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE10 = 0 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE10_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE11 = 6 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE11_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE12 = 12 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE12_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE13 = 18 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE13_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE14 = 24 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE14_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE15 = 30 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE15_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE16 = 36 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG4_CONFIG_DEBUG_MACH_BYTE16_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG4_CONFIG_DEBUG_MACH_RESERVED1 = 42 ;
+static const uint8_t P9N2_PU_NPU0_DAT_DEBUG4_CONFIG_DEBUG_MACH_ACT = 43 ;
+
+static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS0BYTE0 = 0 ;
+static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS0BYTE0_LEN = 2 ;
+static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS0BYTE1 = 2 ;
+static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS0BYTE1_LEN = 2 ;
+static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS0BYTE2 = 4 ;
+static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS0BYTE2_LEN = 2 ;
+static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS0BYTE3 = 6 ;
+static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS0BYTE3_LEN = 2 ;
+static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS0BYTE4 = 8 ;
+static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS0BYTE4_LEN = 2 ;
+static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS0BYTE5 = 10 ;
+static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS0BYTE5_LEN = 2 ;
+static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS0BYTE6 = 12 ;
+static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS0BYTE6_LEN = 2 ;
+static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS0BYTE7 = 14 ;
+static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS0BYTE7_LEN = 2 ;
+static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS0BYTE8 = 16 ;
+static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS0BYTE8_LEN = 2 ;
+static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS0BYTE9 = 18 ;
+static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS0BYTE9_LEN = 2 ;
+static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS0BYTE10 = 20 ;
+static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS0BYTE10_LEN = 2 ;
+static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS1BYTE0 = 22 ;
+static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS1BYTE0_LEN = 2 ;
+static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS1BYTE1 = 24 ;
+static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS1BYTE1_LEN = 2 ;
+static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS1BYTE2 = 26 ;
+static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS1BYTE2_LEN = 2 ;
+static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS1BYTE3 = 28 ;
+static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS1BYTE3_LEN = 2 ;
+static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS1BYTE4 = 30 ;
+static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS1BYTE4_LEN = 2 ;
+static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS1BYTE5 = 32 ;
+static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS1BYTE5_LEN = 2 ;
+static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS1BYTE6 = 34 ;
+static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS1BYTE6_LEN = 2 ;
+static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS1BYTE7 = 36 ;
+static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS1BYTE7_LEN = 2 ;
+static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS1BYTE8 = 38 ;
+static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS1BYTE8_LEN = 2 ;
+static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS1BYTE9 = 40 ;
+static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS1BYTE9_LEN = 2 ;
+static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS1BYTE10 = 42 ;
+static const uint8_t P9N2__CTL_DEBUG_CONFIG_MISC_BUS1BYTE10_LEN = 2 ;
+static const uint8_t P9N2__CTL_DEBUG_CONFIG_RESERVED = 44 ;
+static const uint8_t P9N2__CTL_DEBUG_CONFIG_RESERVED_LEN = 19 ;
+static const uint8_t P9N2__CTL_DEBUG_CONFIG_ACT = 63 ;
+
+static const uint8_t P9N2_CAPP_DEBUG_CONTROL_BLOCK_MUX_PORT_SEL = 0 ;
+static const uint8_t P9N2_CAPP_DEBUG_CONTROL_BLOCK_MUX_PORT_SEL_LEN = 4 ;
+static const uint8_t P9N2_CAPP_DEBUG_CONTROL_BLOCK_SEL = 4 ;
+static const uint8_t P9N2_CAPP_DEBUG_CONTROL_BLOCK_SEL_LEN = 8 ;
+
+static const uint8_t P9N2_PEC_DEBUG_TRACE_CONTROL_SCOM_TRACE_START = 0 ;
+static const uint8_t P9N2_PEC_DEBUG_TRACE_CONTROL_SCOM_TRACE_STOP = 1 ;
+static const uint8_t P9N2_PEC_DEBUG_TRACE_CONTROL_SCOM_TRACE_RESET = 2 ;
+
+static const uint8_t P9N2_PU_DEBUG_TRACE_CONTROL_SCOM_TRACE_START = 0 ;
+static const uint8_t P9N2_PU_DEBUG_TRACE_CONTROL_SCOM_TRACE_STOP = 1 ;
+static const uint8_t P9N2_PU_DEBUG_TRACE_CONTROL_SCOM_TRACE_RESET = 2 ;
+
+static const uint8_t P9N2_CAPP_DFSUOP1_WORD = 0 ;
+static const uint8_t P9N2_CAPP_DFSUOP1_WORD_LEN = 56 ;
+
+static const uint8_t P9N2_PU_DISABLE_FORCE_PFET_OFF_REG = 0 ;
+static const uint8_t P9N2_PU_DISABLE_FORCE_PFET_OFF_REG_LEN = 30 ;
+static const uint8_t P9N2_PU_DISABLE_FORCE_PFET_OFF_RESERVED = 30 ;
+static const uint8_t P9N2_PU_DISABLE_FORCE_PFET_OFF_RESERVED_LEN = 12 ;
+
+static const uint8_t P9N2__SM1_DMA_SYNC_START_READ = 0 ;
+static const uint8_t P9N2__SM1_DMA_SYNC_READ_COMPLETE = 1 ;
+static const uint8_t P9N2__SM1_DMA_SYNC_START_WRITE = 2 ;
+static const uint8_t P9N2__SM1_DMA_SYNC_WRITE_COMPLETE = 3 ;
+
+static const uint8_t P9N2_PU_DMA_UP_ADDR_BASE_UPPER_BITS = 0 ;
+static const uint8_t P9N2_PU_DMA_UP_ADDR_BASE_UPPER_BITS_LEN = 8 ;
+static const uint8_t P9N2_PU_DMA_UP_ADDR_ESCAPE_ADDRESS = 16 ;
+static const uint8_t P9N2_PU_DMA_UP_ADDR_ESCAPE_ADDRESS_LEN = 48 ;
+
+static const uint8_t P9N2_PU_DMA_VAS_MMIO_BAR_BAR = 8 ;
+static const uint8_t P9N2_PU_DMA_VAS_MMIO_BAR_BAR_LEN = 31 ;
+
+static const uint8_t P9N2_PEC_DRPPRICTL_REG_PE_DROPPRIORITYMASK = 0 ;
+static const uint8_t P9N2_PEC_DRPPRICTL_REG_PE_DROPPRIORITYMASK_LEN = 6 ;
+static const uint8_t P9N2_PEC_DRPPRICTL_REG_PE_ENABLE_CTAG_DROP_PRIORITY = 6 ;
+static const uint8_t P9N2_PEC_DRPPRICTL_REG_PE_ENABLE_IO_CMD_PACING = 7 ;
+static const uint8_t P9N2_PEC_DRPPRICTL_REG_PE_DROPPACECOUNT = 8 ;
+static const uint8_t P9N2_PEC_DRPPRICTL_REG_PE_DROPPACECOUNT_LEN = 9 ;
+static const uint8_t P9N2_PEC_DRPPRICTL_REG_PE_DROPPACEINC = 17 ;
+static const uint8_t P9N2_PEC_DRPPRICTL_REG_PE_DROPPACEINC_LEN = 6 ;
+static const uint8_t P9N2_PEC_DRPPRICTL_REG_PE_RTYDROPDIVIDER = 23 ;
+static const uint8_t P9N2_PEC_DRPPRICTL_REG_PE_RTYDROPDIVIDER_LEN = 3 ;
+
+static const uint8_t P9N2_PEC_DTS_RESULT0_0_RESULT = 0 ;
+static const uint8_t P9N2_PEC_DTS_RESULT0_0_RESULT_LEN = 16 ;
+static const uint8_t P9N2_PEC_DTS_RESULT0_1_RESULT = 16 ;
+static const uint8_t P9N2_PEC_DTS_RESULT0_1_RESULT_LEN = 16 ;
+
+static const uint8_t P9N2_PEC_DTS_TRC_RESULT_TIMESTAMP_COUNTER_VALUE = 0 ;
+static const uint8_t P9N2_PEC_DTS_TRC_RESULT_TIMESTAMP_COUNTER_VALUE_LEN = 44 ;
+static const uint8_t P9N2_PEC_DTS_TRC_RESULT_TIMESTAMP_COUNTER_OVERFLOW_ERR = 44 ;
+static const uint8_t P9N2_PEC_DTS_TRC_RESULT_1 = 48 ;
+static const uint8_t P9N2_PEC_DTS_TRC_RESULT_1_LEN = 16 ;
+
+static const uint8_t P9N2_PU_NPU2_NTL1_ECC_CONFIG_PBTX_AMO_IGNORE_XUE = 0 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_ECC_CONFIG_SUE_DIS_BR_PERR = 1 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_ECC_CONFIG_SUE_DIS_IR_PERR = 2 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_ECC_CONFIG_SUE_DIS_OR_PERR = 3 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_ECC_CONFIG_CORR_DIS_PT = 4 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_ECC_CONFIG_CORR_DIS_PR = 5 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_ECC_CONFIG_CORR_DIS_BR = 6 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_ECC_CONFIG_CORR_DIS_IR = 7 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_ECC_CONFIG_CORR_DIS_OR = 8 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_ECC_CONFIG_SUE_DIS_PT = 9 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_ECC_CONFIG_SUE_DIS_PR = 10 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_ECC_CONFIG_SUE_DIS_BR = 11 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_ECC_CONFIG_SUE_DIS_IR = 12 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_ECC_CONFIG_SUE_DIS_OR = 13 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_ECC_CONFIG_RESERVED = 14 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_ECC_CONFIG_RESERVED_LEN = 18 ;
+
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART0_REGISTER_PART_0 = 0 ;
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART0_REGISTER_PART_0_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART0_REGISTER_PART_0 = 0 ;
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART0_REGISTER_PART_0_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART10_REGISTER_PART_10 = 0 ;
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART10_REGISTER_PART_10_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART10_REGISTER_PART_10 = 0 ;
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART10_REGISTER_PART_10_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART11_REGISTER_PART_11 = 0 ;
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART11_REGISTER_PART_11_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART11_REGISTER_PART_11 = 0 ;
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART11_REGISTER_PART_11_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART12_REGISTER_PART_12 = 0 ;
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART12_REGISTER_PART_12_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART12_REGISTER_PART_12 = 0 ;
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART12_REGISTER_PART_12_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART13_REGISTER_PART_13 = 0 ;
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART13_REGISTER_PART_13_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART13_REGISTER_PART_13 = 0 ;
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART13_REGISTER_PART_13_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART14_REGISTER_PART_14 = 0 ;
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART14_REGISTER_PART_14_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART14_REGISTER_PART_14 = 0 ;
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART14_REGISTER_PART_14_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART15_REGISTER_PART_15 = 0 ;
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART15_REGISTER_PART_15_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART15_REGISTER_PART_15 = 0 ;
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART15_REGISTER_PART_15_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART16_REGISTER_PART_16 = 0 ;
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART16_REGISTER_PART_16_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART16_REGISTER_PART_16 = 0 ;
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART16_REGISTER_PART_16_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART17_REGISTER_PART_17 = 0 ;
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART17_REGISTER_PART_17_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART17_REGISTER_PART_17 = 0 ;
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART17_REGISTER_PART_17_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART18_REGISTER_PART_18 = 0 ;
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART18_REGISTER_PART_18_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART18_REGISTER_PART_18 = 0 ;
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART18_REGISTER_PART_18_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART19_REGISTER_PART_19 = 0 ;
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART19_REGISTER_PART_19_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART19_REGISTER_PART_19 = 0 ;
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART19_REGISTER_PART_19_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART1_REGISTER_PART_1 = 0 ;
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART1_REGISTER_PART_1_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART1_REGISTER_PART_1 = 0 ;
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART1_REGISTER_PART_1_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART20_REGISTER_PART_20 = 0 ;
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART20_REGISTER_PART_20_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART20_REGISTER_PART_20 = 0 ;
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART20_REGISTER_PART_20_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART21_REGISTER_PART_21 = 0 ;
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART21_REGISTER_PART_21_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART21_REGISTER_PART_21 = 0 ;
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART21_REGISTER_PART_21_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART22_REGISTER_PART_22 = 0 ;
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART22_REGISTER_PART_22_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART22_REGISTER_PART_22 = 0 ;
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART22_REGISTER_PART_22_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART23_REGISTER_PART_23 = 0 ;
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART23_REGISTER_PART_23_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART23_REGISTER_PART_23 = 0 ;
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART23_REGISTER_PART_23_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART24_REGISTER_PART_24 = 0 ;
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART24_REGISTER_PART_24_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART24_REGISTER_PART_24 = 0 ;
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART24_REGISTER_PART_24_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART25_REGISTER_PART_25 = 0 ;
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART25_REGISTER_PART_25_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART25_REGISTER_PART_25 = 0 ;
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART25_REGISTER_PART_25_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART26_REGISTER_PART_26 = 0 ;
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART26_REGISTER_PART_26_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART26_REGISTER_PART_26 = 0 ;
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART26_REGISTER_PART_26_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART27_REGISTER_PART_27 = 0 ;
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART27_REGISTER_PART_27_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART27_REGISTER_PART_27 = 0 ;
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART27_REGISTER_PART_27_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART28_REGISTER_PART_28 = 0 ;
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART28_REGISTER_PART_28_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART28_REGISTER_PART_28 = 0 ;
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART28_REGISTER_PART_28_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART29_REGISTER_PART_29 = 0 ;
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART29_REGISTER_PART_29_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART29_REGISTER_PART_29 = 0 ;
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART29_REGISTER_PART_29_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART2_REGISTER_PART_2 = 0 ;
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART2_REGISTER_PART_2_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART2_REGISTER_PART_2 = 0 ;
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART2_REGISTER_PART_2_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART30_REGISTER_PART_30 = 0 ;
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART30_REGISTER_PART_30_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART30_REGISTER_PART_30 = 0 ;
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART30_REGISTER_PART_30_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART31_REGISTER_PART_31 = 0 ;
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART31_REGISTER_PART_31_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART31_REGISTER_PART_31 = 0 ;
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART31_REGISTER_PART_31_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART32_REGISTER_PART_32 = 0 ;
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART32_REGISTER_PART_32_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART32_REGISTER_PART_32 = 0 ;
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART32_REGISTER_PART_32_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART33_REGISTER_PART_33 = 0 ;
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART33_REGISTER_PART_33_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART33_REGISTER_PART_33 = 0 ;
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART33_REGISTER_PART_33_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART34_REGISTER_PART_34 = 0 ;
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART34_REGISTER_PART_34_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART34_REGISTER_PART_34 = 0 ;
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART34_REGISTER_PART_34_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART35_REGISTER_PART_35 = 0 ;
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART35_REGISTER_PART_35_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART35_REGISTER_PART_35 = 0 ;
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART35_REGISTER_PART_35_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART36_REGISTER_PART_36 = 0 ;
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART36_REGISTER_PART_36_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART36_REGISTER_PART_36 = 0 ;
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART36_REGISTER_PART_36_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART37_REGISTER_PART_37 = 0 ;
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART37_REGISTER_PART_37_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART37_REGISTER_PART_37 = 0 ;
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART37_REGISTER_PART_37_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART38_REGISTER_PART_38 = 0 ;
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART38_REGISTER_PART_38_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART38_REGISTER_PART_38 = 0 ;
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART38_REGISTER_PART_38_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART39_REGISTER_PART_39 = 0 ;
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART39_REGISTER_PART_39_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART39_REGISTER_PART_39 = 0 ;
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART39_REGISTER_PART_39_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART3_REGISTER_PART_3 = 0 ;
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART3_REGISTER_PART_3_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART3_REGISTER_PART_3 = 0 ;
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART3_REGISTER_PART_3_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART40_REGISTER_PART_40 = 0 ;
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART40_REGISTER_PART_40_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART40_REGISTER_PART_40 = 0 ;
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART40_REGISTER_PART_40_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART41_REGISTER_PART_41 = 0 ;
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART41_REGISTER_PART_41_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART41_REGISTER_PART_41 = 0 ;
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART41_REGISTER_PART_41_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART42_REGISTER_PART_42 = 0 ;
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART42_REGISTER_PART_42_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART42_REGISTER_PART_42 = 0 ;
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART42_REGISTER_PART_42_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART43_REGISTER_PART_43 = 0 ;
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART43_REGISTER_PART_43_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART43_REGISTER_PART_43 = 0 ;
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART43_REGISTER_PART_43_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART44_REGISTER_PART_44 = 0 ;
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART44_REGISTER_PART_44_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART44_REGISTER_PART_44 = 0 ;
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART44_REGISTER_PART_44_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART45_REGISTER_PART_45 = 0 ;
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART45_REGISTER_PART_45_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART45_REGISTER_PART_45 = 0 ;
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART45_REGISTER_PART_45_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART46_REGISTER_PART_46 = 0 ;
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART46_REGISTER_PART_46_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART46_REGISTER_PART_46 = 0 ;
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART46_REGISTER_PART_46_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART47_REGISTER_PART_47 = 0 ;
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART47_REGISTER_PART_47_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART47_REGISTER_PART_47 = 0 ;
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART47_REGISTER_PART_47_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART48_REGISTER_PART_48 = 0 ;
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART48_REGISTER_PART_48_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART48_REGISTER_PART_48 = 0 ;
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART48_REGISTER_PART_48_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART49_REGISTER_PART_49 = 0 ;
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART49_REGISTER_PART_49_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART49_REGISTER_PART_49 = 0 ;
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART49_REGISTER_PART_49_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART4_REGISTER_PART_4 = 0 ;
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART4_REGISTER_PART_4_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART4_REGISTER_PART_4 = 0 ;
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART4_REGISTER_PART_4_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART50_REGISTER_PART_50 = 0 ;
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART50_REGISTER_PART_50_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART50_REGISTER_PART_50 = 0 ;
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART50_REGISTER_PART_50_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART51_REGISTER_PART_51 = 0 ;
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART51_REGISTER_PART_51_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART51_REGISTER_PART_51 = 0 ;
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART51_REGISTER_PART_51_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART52_REGISTER_PART_52 = 0 ;
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART52_REGISTER_PART_52_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART52_REGISTER_PART_52 = 0 ;
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART52_REGISTER_PART_52_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART53_REGISTER_PART_53 = 0 ;
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART53_REGISTER_PART_53_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART53_REGISTER_PART_53 = 0 ;
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART53_REGISTER_PART_53_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART54_REGISTER_PART_54 = 0 ;
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART54_REGISTER_PART_54_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART54_REGISTER_PART_54 = 0 ;
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART54_REGISTER_PART_54_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART55_REGISTER_PART_55 = 0 ;
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART55_REGISTER_PART_55_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART55_REGISTER_PART_55 = 0 ;
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART55_REGISTER_PART_55_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART56_REGISTER_PART_56 = 0 ;
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART56_REGISTER_PART_56_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART56_REGISTER_PART_56 = 0 ;
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART56_REGISTER_PART_56_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART57_REGISTER_PART_57 = 0 ;
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART57_REGISTER_PART_57_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART57_REGISTER_PART_57 = 0 ;
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART57_REGISTER_PART_57_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART58_REGISTER_PART_58 = 0 ;
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART58_REGISTER_PART_58_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART58_REGISTER_PART_58 = 0 ;
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART58_REGISTER_PART_58_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART59_REGISTER_PART_59 = 0 ;
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART59_REGISTER_PART_59_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART59_REGISTER_PART_59 = 0 ;
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART59_REGISTER_PART_59_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART5_REGISTER_PART_5 = 0 ;
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART5_REGISTER_PART_5_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART5_REGISTER_PART_5 = 0 ;
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART5_REGISTER_PART_5_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART60_REGISTER_PART_60 = 0 ;
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART60_REGISTER_PART_60_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART60_REGISTER_PART_60 = 0 ;
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART60_REGISTER_PART_60_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART61_REGISTER_PART_61 = 0 ;
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART61_REGISTER_PART_61_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART61_REGISTER_PART_61 = 0 ;
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART61_REGISTER_PART_61_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART62_REGISTER_PART_62 = 0 ;
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART62_REGISTER_PART_62_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART62_REGISTER_PART_62 = 0 ;
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART62_REGISTER_PART_62_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART63_REGISTER_PART_63 = 0 ;
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART63_REGISTER_PART_63_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART63_REGISTER_PART_63 = 0 ;
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART63_REGISTER_PART_63_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART6_REGISTER_PART_6 = 0 ;
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART6_REGISTER_PART_6_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART6_REGISTER_PART_6 = 0 ;
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART6_REGISTER_PART_6_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART7_REGISTER_PART_7 = 0 ;
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART7_REGISTER_PART_7_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART7_REGISTER_PART_7 = 0 ;
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART7_REGISTER_PART_7_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART8_REGISTER_PART_8 = 0 ;
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART8_REGISTER_PART_8_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART8_REGISTER_PART_8 = 0 ;
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART8_REGISTER_PART_8_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART9_REGISTER_PART_9 = 0 ;
+static const uint8_t P9N2_PU_OTPROM0_ECID_PART9_REGISTER_PART_9_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART9_REGISTER_PART_9 = 0 ;
+static const uint8_t P9N2_PU_OTPROM1_ECID_PART9_REGISTER_PART_9_LEN = 64 ;
+
+static const uint8_t P9N2_PEC_EDRAM_STATUS_STAT = 0 ;
+static const uint8_t P9N2_PEC_EDRAM_STATUS_STAT_LEN = 4 ;
+
+static const uint8_t P9N2_PU_EECNT_REG_EECNT = 0 ;
+static const uint8_t P9N2_PU_EECNT_REG_EECNT_LEN = 6 ;
+
+static const uint8_t P9N2_PU_EFT_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_LPID = 4 ;
+static const uint8_t P9N2_PU_EFT_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_LPID_LEN = 12 ;
+static const uint8_t P9N2_PU_EFT_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_PID = 20 ;
+static const uint8_t P9N2_PU_EFT_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_PID_LEN = 20 ;
+static const uint8_t P9N2_PU_EFT_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_TID = 44 ;
+static const uint8_t P9N2_PU_EFT_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_TID_LEN = 16 ;
+static const uint8_t P9N2_PU_EFT_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_ENABLE = 63 ;
+
+static const uint8_t P9N2_PU_EFT_HI_PRIOR_RCV_FIFO_BAR_PRIORITY = 8 ;
+static const uint8_t P9N2_PU_EFT_HI_PRIOR_RCV_FIFO_BAR_PRIORITY_LEN = 46 ;
+static const uint8_t P9N2_PU_EFT_HI_PRIOR_RCV_FIFO_BAR_PRIORITY_SIZE = 54 ;
+static const uint8_t P9N2_PU_EFT_HI_PRIOR_RCV_FIFO_BAR_PRIORITY_SIZE_LEN = 3 ;
+
+static const uint8_t P9N2_PU_EFT_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_READ_OFFSET = 4 ;
+static const uint8_t P9N2_PU_EFT_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_READ_OFFSET_LEN = 8 ;
+static const uint8_t P9N2_PU_EFT_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_QUEUED = 15 ;
+static const uint8_t P9N2_PU_EFT_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_QUEUED_LEN = 9 ;
+static const uint8_t P9N2_PU_EFT_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_PRIMAX = 27 ;
+static const uint8_t P9N2_PU_EFT_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_PRIMAX_LEN = 9 ;
+
+static const uint8_t P9N2_PU_EFT_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_LPID = 4 ;
+static const uint8_t P9N2_PU_EFT_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_LPID_LEN = 12 ;
+static const uint8_t P9N2_PU_EFT_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_PID = 20 ;
+static const uint8_t P9N2_PU_EFT_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_PID_LEN = 20 ;
+static const uint8_t P9N2_PU_EFT_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_TID = 44 ;
+static const uint8_t P9N2_PU_EFT_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_TID_LEN = 16 ;
+static const uint8_t P9N2_PU_EFT_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_ENABLE = 63 ;
+
+static const uint8_t P9N2_PU_EFT_LO_PRIOR_RCV_FIFO_BAR_PRIORITY = 8 ;
+static const uint8_t P9N2_PU_EFT_LO_PRIOR_RCV_FIFO_BAR_PRIORITY_LEN = 46 ;
+static const uint8_t P9N2_PU_EFT_LO_PRIOR_RCV_FIFO_BAR_PRIORITY_SIZE = 54 ;
+static const uint8_t P9N2_PU_EFT_LO_PRIOR_RCV_FIFO_BAR_PRIORITY_SIZE_LEN = 3 ;
+
+static const uint8_t P9N2_PU_EFT_LO_PRIOR_RCV_FIFO_CNTL_PRIORITY_READ_OFFSET = 4 ;
+static const uint8_t P9N2_PU_EFT_LO_PRIOR_RCV_FIFO_CNTL_PRIORITY_READ_OFFSET_LEN = 8 ;
+static const uint8_t P9N2_PU_EFT_LO_PRIOR_RCV_FIFO_CNTL_PRIORITY_QUEUED = 15 ;
+static const uint8_t P9N2_PU_EFT_LO_PRIOR_RCV_FIFO_CNTL_PRIORITY_QUEUED_LEN = 9 ;
+
+static const uint8_t P9N2_PU_EFT_MAX_BYTE_CNT_LIMIT = 0 ;
+static const uint8_t P9N2_PU_EFT_MAX_BYTE_CNT_LIMIT_LEN = 5 ;
+static const uint8_t P9N2_PU_EFT_MAX_BYTE_CNT_SRC_DDE = 5 ;
+static const uint8_t P9N2_PU_EFT_MAX_BYTE_CNT_SRC_DDE_LEN = 8 ;
+static const uint8_t P9N2_PU_EFT_MAX_BYTE_CNT_TARGET_DDE = 13 ;
+static const uint8_t P9N2_PU_EFT_MAX_BYTE_CNT_TARGET_DDE_LEN = 8 ;
+static const uint8_t P9N2_PU_EFT_MAX_BYTE_CNT_LO_PRIOR_LIMIT = 21 ;
+static const uint8_t P9N2_PU_EFT_MAX_BYTE_CNT_LO_PRIOR_LIMIT_LEN = 5 ;
+
+static const uint8_t P9N2_PU_ENHCA_FIR_ACTION0_REG_DPX0_DAT_UE = 0 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_ACTION0_REG_DPX0_DAT_SUE = 1 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_ACTION0_REG_DPX0_DAT_CE = 2 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_ACTION0_REG_CO_DROP_COUNTER_FULL = 4 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_ACTION0_REG_DATA_HANG_DETECT = 5 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_ACTION0_REG_UNEXPECTED_DATA_OR_CRESP = 6 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_ACTION0_REG_INTERNAL_ERROR = 7 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_ACTION0_REG_ADU_PBDAT_XSTOP_ERROR = 8 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_ACTION0_REG_ADU_ALTDSM_XSTOP_ERROR = 9 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_ACTION0_REG_ADU_XCSMP_XSTOP_ERROR = 10 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_ACTION0_REG_ADU_PBADR_XSTOP_ERROR = 11 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_ACTION0_REG_ADU_SND_XSTOP_ERROR = 12 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_ACTION0_REG_ADU_RCV_XSTOP_ERROR = 13 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_ACTION0_REG_ADU_PBDAT_RECOV_ERROR = 14 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_ACTION0_REG_ADU_ALTDSM_RECOV_ERROR = 15 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_ACTION0_REG_ADU_XCSMP_RECOV_ERROR = 16 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_ACTION0_REG_ADU_PBADR_RECOV_ERROR = 17 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_ACTION0_REG_ADU_SND_RECOV_ERROR = 18 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_ACTION0_REG_ADU_RCV_RRC = 19 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_ACTION0_REG_NHTM_SCON_E = 20 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_ACTION0_REG_SCOM_ERROR = 22 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_ACTION0_REG_PARITY_ERROR = 23 ;
+
+static const uint8_t P9N2_PU_ENHCA_FIR_ACTION1_REG_DPX0_DAT_UE = 0 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_ACTION1_REG_DPX0_DAT_SUE = 1 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_ACTION1_REG_DPX0_DAT_CE = 2 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_ACTION1_REG_CO_DROP_COUNTER_FULL = 4 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_ACTION1_REG_DATA_HANG_DETECT = 5 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_ACTION1_REG_UNEXPECTED_DATA_OR_CRESP = 6 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_ACTION1_REG_INTERNAL_ERROR = 7 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_ACTION1_REG_ADU_PBDAT_XSTOP_ERROR = 8 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_ACTION1_REG_ADU_ALTDSM_XSTOP_ERROR = 9 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_ACTION1_REG_ADU_XCSMP_XSTOP_ERROR = 10 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_ACTION1_REG_ADU_PBADR_XSTOP_ERROR = 11 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_ACTION1_REG_ADU_SND_XSTOP_ERROR = 12 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_ACTION1_REG_ADU_RCV_XSTOP_ERROR = 13 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_ACTION1_REG_ADU_PBDAT_RECOV_ERROR = 14 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_ACTION1_REG_ADU_ALTDSM_RECOV_ERROR = 15 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_ACTION1_REG_ADU_XCSMP_RECOV_ERROR = 16 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_ACTION1_REG_ADU_PBADR_RECOV_ERROR = 17 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_ACTION1_REG_ADU_SND_RECOV_ERROR = 18 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_ACTION1_REG_ADU_RCV_RRC = 19 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_ACTION1_REG_NHTM_SCON_E = 20 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_ACTION1_REG_SCOM_ERROR = 22 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_ACTION1_REG_PARITY_ERROR = 23 ;
+
+static const uint8_t P9N2_PU_ENHCA_FIR_MASK_REG_DPX0_DAT_UE = 0 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_MASK_REG_DPX0_DAT_SUE = 1 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_MASK_REG_DPX0_DAT_CE = 2 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_MASK_REG_CO_DROP_COUNTER_FULL = 4 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_MASK_REG_DATA_HANG_DETECT = 5 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_MASK_REG_UNEXPECTED_DATA_OR_CRESP = 6 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_MASK_REG_INTERNAL_ERROR = 7 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_MASK_REG_ADU_PBDAT_XSTOP_ERROR = 8 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_MASK_REG_ADU_ALTDSM_XSTOP_ERROR = 9 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_MASK_REG_ADU_XCSMP_XSTOP_ERROR = 10 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_MASK_REG_ADU_PBADR_XSTOP_ERROR = 11 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_MASK_REG_ADU_SND_XSTOP_ERROR = 12 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_MASK_REG_ADU_RCV_XSTOP_ERROR = 13 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_MASK_REG_ADU_PBDAT_RECOV_ERROR = 14 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_MASK_REG_ADU_ALTDSM_RECOV_ERROR = 15 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_MASK_REG_ADU_XCSMP_RECOV_ERROR = 16 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_MASK_REG_ADU_PBADR_RECOV_ERROR = 17 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_MASK_REG_ADU_SND_RECOV_ERROR = 18 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_MASK_REG_ADU_RCV_RRC = 19 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_MASK_REG_NHTM_SCON_E = 20 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_MASK_REG_SPARE_ERROR_MASK = 21 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_MASK_REG_SCOM_ERROR = 22 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_MASK_REG_PARITY_ERROR = 23 ;
+
+static const uint8_t P9N2_PU_ENHCA_FIR_REG_DPX0_DAT_UE = 0 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_REG_DPX0_DAT_SUE = 1 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_REG_DPX0_DAT_CE = 2 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_REG_CO_DROP_COUNTER_FULL = 4 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_REG_DATA_HANG_DETECT = 5 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_REG_UNEXPECTED_DATA_OR_CRESP = 6 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_REG_INTERNAL_ERROR = 7 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_REG_ADU_PBDAT_XSTOP_ERROR = 8 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_REG_ADU_ALTDSM_XSTOP_ERROR = 9 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_REG_ADU_XCSMP_XSTOP_ERROR = 10 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_REG_ADU_PBADR_XSTOP_ERROR = 11 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_REG_ADU_SND_XSTOP_ERROR = 12 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_REG_ADU_RCV_XSTOP_ERROR = 13 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_REG_ADU_PBDAT_RECOV_ERROR = 14 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_REG_ADU_ALTDSM_RECOV_ERROR = 15 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_REG_ADU_XCSMP_RECOV_ERROR = 16 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_REG_ADU_PBADR_RECOV_ERROR = 17 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_REG_ADU_SND_RECOV_ERROR = 18 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_REG_ADU_RCV_RRC = 19 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_REG_NHTM_SCON_E = 20 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_REG_SPARE_ERROR = 21 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_REG_SCOM_ERROR = 22 ;
+static const uint8_t P9N2_PU_ENHCA_FIR_REG_PARITY_ERROR = 23 ;
+
+static const uint8_t P9N2_PU_NPU0_SM0_EPSILON_CONFIG_RATE = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM0_EPSILON_CONFIG_RATE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM0_EPSILON_CONFIG_W0_COUNT = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM0_EPSILON_CONFIG_W0_COUNT_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU0_SM0_EPSILON_CONFIG_W1_COUNT = 16 ;
+static const uint8_t P9N2_PU_NPU0_SM0_EPSILON_CONFIG_W1_COUNT_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU0_SM0_EPSILON_CONFIG_R0_COUNT = 28 ;
+static const uint8_t P9N2_PU_NPU0_SM0_EPSILON_CONFIG_R0_COUNT_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU0_SM0_EPSILON_CONFIG_R1_COUNT = 40 ;
+static const uint8_t P9N2_PU_NPU0_SM0_EPSILON_CONFIG_R1_COUNT_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU0_SM0_EPSILON_CONFIG_R2_COUNT = 52 ;
+static const uint8_t P9N2_PU_NPU0_SM0_EPSILON_CONFIG_R2_COUNT_LEN = 12 ;
+
+static const uint8_t P9N2_PU_NPU2_SM3_EPSILON_CONFIG_RATE = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM3_EPSILON_CONFIG_RATE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM3_EPSILON_CONFIG_W0_COUNT = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM3_EPSILON_CONFIG_W0_COUNT_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU2_SM3_EPSILON_CONFIG_W1_COUNT = 16 ;
+static const uint8_t P9N2_PU_NPU2_SM3_EPSILON_CONFIG_W1_COUNT_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU2_SM3_EPSILON_CONFIG_R0_COUNT = 28 ;
+static const uint8_t P9N2_PU_NPU2_SM3_EPSILON_CONFIG_R0_COUNT_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU2_SM3_EPSILON_CONFIG_R1_COUNT = 40 ;
+static const uint8_t P9N2_PU_NPU2_SM3_EPSILON_CONFIG_R1_COUNT_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU2_SM3_EPSILON_CONFIG_R2_COUNT = 52 ;
+static const uint8_t P9N2_PU_NPU2_SM3_EPSILON_CONFIG_R2_COUNT_LEN = 12 ;
+
+static const uint8_t P9N2_PU_NPU0_SM3_EPSILON_CONFIG_RATE = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM3_EPSILON_CONFIG_RATE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM3_EPSILON_CONFIG_W0_COUNT = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM3_EPSILON_CONFIG_W0_COUNT_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU0_SM3_EPSILON_CONFIG_W1_COUNT = 16 ;
+static const uint8_t P9N2_PU_NPU0_SM3_EPSILON_CONFIG_W1_COUNT_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU0_SM3_EPSILON_CONFIG_R0_COUNT = 28 ;
+static const uint8_t P9N2_PU_NPU0_SM3_EPSILON_CONFIG_R0_COUNT_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU0_SM3_EPSILON_CONFIG_R1_COUNT = 40 ;
+static const uint8_t P9N2_PU_NPU0_SM3_EPSILON_CONFIG_R1_COUNT_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU0_SM3_EPSILON_CONFIG_R2_COUNT = 52 ;
+static const uint8_t P9N2_PU_NPU0_SM3_EPSILON_CONFIG_R2_COUNT_LEN = 12 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM0_EPSILON_CONFIG_RATE = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_EPSILON_CONFIG_RATE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_EPSILON_CONFIG_W0_COUNT = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_EPSILON_CONFIG_W0_COUNT_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_EPSILON_CONFIG_W1_COUNT = 16 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_EPSILON_CONFIG_W1_COUNT_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_EPSILON_CONFIG_R0_COUNT = 28 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_EPSILON_CONFIG_R0_COUNT_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_EPSILON_CONFIG_R1_COUNT = 40 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_EPSILON_CONFIG_R1_COUNT_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_EPSILON_CONFIG_R2_COUNT = 52 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_EPSILON_CONFIG_R2_COUNT_LEN = 12 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM1_EPSILON_CONFIG_RATE = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_EPSILON_CONFIG_RATE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_EPSILON_CONFIG_W0_COUNT = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_EPSILON_CONFIG_W0_COUNT_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_EPSILON_CONFIG_W1_COUNT = 16 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_EPSILON_CONFIG_W1_COUNT_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_EPSILON_CONFIG_R0_COUNT = 28 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_EPSILON_CONFIG_R0_COUNT_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_EPSILON_CONFIG_R1_COUNT = 40 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_EPSILON_CONFIG_R1_COUNT_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_EPSILON_CONFIG_R2_COUNT = 52 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_EPSILON_CONFIG_R2_COUNT_LEN = 12 ;
+
+static const uint8_t P9N2_PU_NPU2_SM1_EPSILON_CONFIG_RATE = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM1_EPSILON_CONFIG_RATE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM1_EPSILON_CONFIG_W0_COUNT = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM1_EPSILON_CONFIG_W0_COUNT_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU2_SM1_EPSILON_CONFIG_W1_COUNT = 16 ;
+static const uint8_t P9N2_PU_NPU2_SM1_EPSILON_CONFIG_W1_COUNT_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU2_SM1_EPSILON_CONFIG_R0_COUNT = 28 ;
+static const uint8_t P9N2_PU_NPU2_SM1_EPSILON_CONFIG_R0_COUNT_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU2_SM1_EPSILON_CONFIG_R1_COUNT = 40 ;
+static const uint8_t P9N2_PU_NPU2_SM1_EPSILON_CONFIG_R1_COUNT_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU2_SM1_EPSILON_CONFIG_R2_COUNT = 52 ;
+static const uint8_t P9N2_PU_NPU2_SM1_EPSILON_CONFIG_R2_COUNT_LEN = 12 ;
+
+static const uint8_t P9N2_PU_NPU0_CTL_EPSILON_CONFIG_RATE = 0 ;
+static const uint8_t P9N2_PU_NPU0_CTL_EPSILON_CONFIG_RATE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_CTL_EPSILON_CONFIG_W0_COUNT = 4 ;
+static const uint8_t P9N2_PU_NPU0_CTL_EPSILON_CONFIG_W0_COUNT_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU0_CTL_EPSILON_CONFIG_W1_COUNT = 16 ;
+static const uint8_t P9N2_PU_NPU0_CTL_EPSILON_CONFIG_W1_COUNT_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU0_CTL_EPSILON_CONFIG_R0_COUNT = 28 ;
+static const uint8_t P9N2_PU_NPU0_CTL_EPSILON_CONFIG_R0_COUNT_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU0_CTL_EPSILON_CONFIG_R1_COUNT = 40 ;
+static const uint8_t P9N2_PU_NPU0_CTL_EPSILON_CONFIG_R1_COUNT_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU0_CTL_EPSILON_CONFIG_R2_COUNT = 52 ;
+static const uint8_t P9N2_PU_NPU0_CTL_EPSILON_CONFIG_R2_COUNT_LEN = 12 ;
+
+static const uint8_t P9N2_PU_NPU2_SM0_EPSILON_CONFIG_RATE = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM0_EPSILON_CONFIG_RATE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM0_EPSILON_CONFIG_W0_COUNT = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM0_EPSILON_CONFIG_W0_COUNT_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU2_SM0_EPSILON_CONFIG_W1_COUNT = 16 ;
+static const uint8_t P9N2_PU_NPU2_SM0_EPSILON_CONFIG_W1_COUNT_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU2_SM0_EPSILON_CONFIG_R0_COUNT = 28 ;
+static const uint8_t P9N2_PU_NPU2_SM0_EPSILON_CONFIG_R0_COUNT_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU2_SM0_EPSILON_CONFIG_R1_COUNT = 40 ;
+static const uint8_t P9N2_PU_NPU2_SM0_EPSILON_CONFIG_R1_COUNT_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU2_SM0_EPSILON_CONFIG_R2_COUNT = 52 ;
+static const uint8_t P9N2_PU_NPU2_SM0_EPSILON_CONFIG_R2_COUNT_LEN = 12 ;
+
+static const uint8_t P9N2_PU_NPU2_CTL_EPSILON_CONFIG_RATE = 0 ;
+static const uint8_t P9N2_PU_NPU2_CTL_EPSILON_CONFIG_RATE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_CTL_EPSILON_CONFIG_W0_COUNT = 4 ;
+static const uint8_t P9N2_PU_NPU2_CTL_EPSILON_CONFIG_W0_COUNT_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU2_CTL_EPSILON_CONFIG_W1_COUNT = 16 ;
+static const uint8_t P9N2_PU_NPU2_CTL_EPSILON_CONFIG_W1_COUNT_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU2_CTL_EPSILON_CONFIG_R0_COUNT = 28 ;
+static const uint8_t P9N2_PU_NPU2_CTL_EPSILON_CONFIG_R0_COUNT_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU2_CTL_EPSILON_CONFIG_R1_COUNT = 40 ;
+static const uint8_t P9N2_PU_NPU2_CTL_EPSILON_CONFIG_R1_COUNT_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU2_CTL_EPSILON_CONFIG_R2_COUNT = 52 ;
+static const uint8_t P9N2_PU_NPU2_CTL_EPSILON_CONFIG_R2_COUNT_LEN = 12 ;
+
+static const uint8_t P9N2_PU_NPU0_SM1_EPSILON_CONFIG_RATE = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM1_EPSILON_CONFIG_RATE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM1_EPSILON_CONFIG_W0_COUNT = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM1_EPSILON_CONFIG_W0_COUNT_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU0_SM1_EPSILON_CONFIG_W1_COUNT = 16 ;
+static const uint8_t P9N2_PU_NPU0_SM1_EPSILON_CONFIG_W1_COUNT_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU0_SM1_EPSILON_CONFIG_R0_COUNT = 28 ;
+static const uint8_t P9N2_PU_NPU0_SM1_EPSILON_CONFIG_R0_COUNT_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU0_SM1_EPSILON_CONFIG_R1_COUNT = 40 ;
+static const uint8_t P9N2_PU_NPU0_SM1_EPSILON_CONFIG_R1_COUNT_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU0_SM1_EPSILON_CONFIG_R2_COUNT = 52 ;
+static const uint8_t P9N2_PU_NPU0_SM1_EPSILON_CONFIG_R2_COUNT_LEN = 12 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_CTL_EPSILON_CONFIG_RATE = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_EPSILON_CONFIG_RATE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_EPSILON_CONFIG_W0_COUNT = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_EPSILON_CONFIG_W0_COUNT_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_EPSILON_CONFIG_W1_COUNT = 16 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_EPSILON_CONFIG_W1_COUNT_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_EPSILON_CONFIG_R0_COUNT = 28 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_EPSILON_CONFIG_R0_COUNT_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_EPSILON_CONFIG_R1_COUNT = 40 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_EPSILON_CONFIG_R1_COUNT_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_EPSILON_CONFIG_R2_COUNT = 52 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_EPSILON_CONFIG_R2_COUNT_LEN = 12 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM3_EPSILON_CONFIG_RATE = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_EPSILON_CONFIG_RATE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_EPSILON_CONFIG_W0_COUNT = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_EPSILON_CONFIG_W0_COUNT_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_EPSILON_CONFIG_W1_COUNT = 16 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_EPSILON_CONFIG_W1_COUNT_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_EPSILON_CONFIG_R0_COUNT = 28 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_EPSILON_CONFIG_R0_COUNT_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_EPSILON_CONFIG_R1_COUNT = 40 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_EPSILON_CONFIG_R1_COUNT_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_EPSILON_CONFIG_R2_COUNT = 52 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_EPSILON_CONFIG_R2_COUNT_LEN = 12 ;
+
+static const uint8_t P9N2_PU_ERAT_STATUS_CONTROL_FORCE_BYPASS = 0 ;
+static const uint8_t P9N2_PU_ERAT_STATUS_CONTROL_IDLE = 1 ;
+static const uint8_t P9N2_PU_ERAT_STATUS_CONTROL_VALID_ENTRY = 2 ;
+static const uint8_t P9N2_PU_ERAT_STATUS_CONTROL_DISABLE_HIT_UNDER_BARRIER = 3 ;
+static const uint8_t P9N2_PU_ERAT_STATUS_CONTROL_DISABLE_PROMOTE = 6 ;
+static const uint8_t P9N2_PU_ERAT_STATUS_CONTROL_DISABLE_CHECKIN_HANG_TIMER = 7 ;
+static const uint8_t P9N2_PU_ERAT_STATUS_CONTROL_DISABLE_CHECKOUT_HANG_TIMER = 8 ;
+static const uint8_t P9N2_PU_ERAT_STATUS_CONTROL_SPECULATIVE_CHECKIN_COUNT = 9 ;
+static const uint8_t P9N2_PU_ERAT_STATUS_CONTROL_SPECULATIVE_CHECKIN_COUNT_LEN = 3 ;
+
+static const uint8_t P9N2__CTL_ERROR_BRICK_GROUP_CONFIG_ERR_BRK0 = 0 ;
+static const uint8_t P9N2__CTL_ERROR_BRICK_GROUP_CONFIG_ERR_BRK0_LEN = 6 ;
+static const uint8_t P9N2__CTL_ERROR_BRICK_GROUP_CONFIG_ERR_BRK1 = 6 ;
+static const uint8_t P9N2__CTL_ERROR_BRICK_GROUP_CONFIG_ERR_BRK1_LEN = 6 ;
+static const uint8_t P9N2__CTL_ERROR_BRICK_GROUP_CONFIG_ERR_BRK2 = 12 ;
+static const uint8_t P9N2__CTL_ERROR_BRICK_GROUP_CONFIG_ERR_BRK2_LEN = 6 ;
+static const uint8_t P9N2__CTL_ERROR_BRICK_GROUP_CONFIG_ERR_BRK3 = 18 ;
+static const uint8_t P9N2__CTL_ERROR_BRICK_GROUP_CONFIG_ERR_BRK3_LEN = 6 ;
+static const uint8_t P9N2__CTL_ERROR_BRICK_GROUP_CONFIG_ERR_BRK4 = 24 ;
+static const uint8_t P9N2__CTL_ERROR_BRICK_GROUP_CONFIG_ERR_BRK4_LEN = 6 ;
+static const uint8_t P9N2__CTL_ERROR_BRICK_GROUP_CONFIG_ERR_BRK5 = 30 ;
+static const uint8_t P9N2__CTL_ERROR_BRICK_GROUP_CONFIG_ERR_BRK5_LEN = 6 ;
+
+static const uint8_t P9N2_PEC_ERROR_REG_CE = 0 ;
+static const uint8_t P9N2_PEC_ERROR_REG_CHIPLET_ERRORS = 1 ;
+static const uint8_t P9N2_PEC_ERROR_REG_CHIPLET_ERRORS_LEN = 3 ;
+static const uint8_t P9N2_PEC_ERROR_REG_PARITY = 4 ;
+static const uint8_t P9N2_PEC_ERROR_REG_DATA_BUFFER = 5 ;
+static const uint8_t P9N2_PEC_ERROR_REG_ADDR_BUFFER = 6 ;
+static const uint8_t P9N2_PEC_ERROR_REG_PCB_FSM = 7 ;
+static const uint8_t P9N2_PEC_ERROR_REG_CL_FSM = 8 ;
+static const uint8_t P9N2_PEC_ERROR_REG_INT_RX_FSM = 9 ;
+static const uint8_t P9N2_PEC_ERROR_REG_INT_TX_FSM = 10 ;
+static const uint8_t P9N2_PEC_ERROR_REG_INT_TYPE = 11 ;
+static const uint8_t P9N2_PEC_ERROR_REG_CL_DATA = 12 ;
+static const uint8_t P9N2_PEC_ERROR_REG_INFO = 13 ;
+static const uint8_t P9N2_PEC_ERROR_REG_UNUSED_0 = 14 ;
+static const uint8_t P9N2_PEC_ERROR_REG_CHIPLET_ATOMIC_LOCK = 15 ;
+static const uint8_t P9N2_PEC_ERROR_REG_PCB_INTERFACE = 16 ;
+static const uint8_t P9N2_PEC_ERROR_REG_CHIPLET_OFFLINE = 17 ;
+static const uint8_t P9N2_PEC_ERROR_REG_EDRAM_SEQUENCE_ERR = 18 ;
+static const uint8_t P9N2_PEC_ERROR_REG_CTRL_PARITY = 19 ;
+static const uint8_t P9N2_PEC_ERROR_REG_ADDRESS_PARITY = 20 ;
+static const uint8_t P9N2_PEC_ERROR_REG_TIMEOUT_PARITY = 21 ;
+static const uint8_t P9N2_PEC_ERROR_REG_CONFIG_PARITY = 22 ;
+static const uint8_t P9N2_PEC_ERROR_REG_UNUSED_1 = 23 ;
+static const uint8_t P9N2_PEC_ERROR_REG_DIV_PARITY = 24 ;
+static const uint8_t P9N2_PEC_ERROR_REG_PLL_UNLOCK = 25 ;
+static const uint8_t P9N2_PEC_ERROR_REG_PLL_UNLOCK_LEN = 4 ;
+
+static const uint8_t P9N2_PU_NPU_CTL_ERROR_SIG_RXI_ERRSIGRXI_CAPTURED = 0 ;
+static const uint8_t P9N2_PU_NPU_CTL_ERROR_SIG_RXI_ERRSIGRXI_ENCODE = 1 ;
+static const uint8_t P9N2_PU_NPU_CTL_ERROR_SIG_RXI_ERRSIGRXI_ENCODE_LEN = 7 ;
+static const uint8_t P9N2_PU_NPU_CTL_ERROR_SIG_RXI_ERRSIGRXI_SIGNATURE = 8 ;
+static const uint8_t P9N2_PU_NPU_CTL_ERROR_SIG_RXI_ERRSIGRXI_SIGNATURE_LEN = 56 ;
+
+static const uint8_t P9N2_PU_NPU_SM2_ERROR_SIG_RXI_ERRSIGRXI_CAPTURED = 0 ;
+static const uint8_t P9N2_PU_NPU_SM2_ERROR_SIG_RXI_ERRSIGRXI_ENCODE = 1 ;
+static const uint8_t P9N2_PU_NPU_SM2_ERROR_SIG_RXI_ERRSIGRXI_ENCODE_LEN = 7 ;
+static const uint8_t P9N2_PU_NPU_SM2_ERROR_SIG_RXI_ERRSIGRXI_SIGNATURE = 8 ;
+static const uint8_t P9N2_PU_NPU_SM2_ERROR_SIG_RXI_ERRSIGRXI_SIGNATURE_LEN = 56 ;
+
+static const uint8_t P9N2__CTL_ERROR_SIG_RXI_ERRSIGRXI_CAPTURED = 0 ;
+static const uint8_t P9N2__CTL_ERROR_SIG_RXI_ERRSIGRXI_ENCODE = 1 ;
+static const uint8_t P9N2__CTL_ERROR_SIG_RXI_ERRSIGRXI_ENCODE_LEN = 7 ;
+static const uint8_t P9N2__CTL_ERROR_SIG_RXI_ERRSIGRXI_SIGNATURE = 8 ;
+static const uint8_t P9N2__CTL_ERROR_SIG_RXI_ERRSIGRXI_SIGNATURE_LEN = 56 ;
+
+static const uint8_t P9N2__SM2_ERROR_SIG_RXI_ERRSIGRXI_CAPTURED = 0 ;
+static const uint8_t P9N2__SM2_ERROR_SIG_RXI_ERRSIGRXI_ENCODE = 1 ;
+static const uint8_t P9N2__SM2_ERROR_SIG_RXI_ERRSIGRXI_ENCODE_LEN = 7 ;
+static const uint8_t P9N2__SM2_ERROR_SIG_RXI_ERRSIGRXI_SIGNATURE = 8 ;
+static const uint8_t P9N2__SM2_ERROR_SIG_RXI_ERRSIGRXI_SIGNATURE_LEN = 56 ;
+
+static const uint8_t P9N2_PU_NPU_CTL_ERROR_SIG_RXO_ERRSIGRXO_TYPE = 0 ;
+static const uint8_t P9N2_PU_NPU_CTL_ERROR_SIG_RXO_ERRSIGRXO_TYPE_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_CTL_ERROR_SIG_RXO_RSV3 = 3 ;
+static const uint8_t P9N2_PU_NPU_CTL_ERROR_SIG_RXO_ERRSIGRXO_AFUTAG = 4 ;
+static const uint8_t P9N2_PU_NPU_CTL_ERROR_SIG_RXO_ERRSIGRXO_AFUTAG_LEN = 16 ;
+static const uint8_t P9N2_PU_NPU_CTL_ERROR_SIG_RXO_ERRSIGRXO_OPCODE = 20 ;
+static const uint8_t P9N2_PU_NPU_CTL_ERROR_SIG_RXO_ERRSIGRXO_OPCODE_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_CTL_ERROR_SIG_RXO_ERRSIGRXO_ACTAG = 28 ;
+static const uint8_t P9N2_PU_NPU_CTL_ERROR_SIG_RXO_ERRSIGRXO_ACTAG_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU_CTL_ERROR_SIG_RXO_ERRSIGRXO_QINDEX = 40 ;
+static const uint8_t P9N2_PU_NPU_CTL_ERROR_SIG_RXO_ERRSIGRXO_QINDEX_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_CTL_ERROR_SIG_RXO_ERRSIGRXO_PE_HANDLE = 46 ;
+static const uint8_t P9N2_PU_NPU_CTL_ERROR_SIG_RXO_ERRSIGRXO_PE_HANDLE_LEN = 16 ;
+
+static const uint8_t P9N2_PU_NPU_SM2_ERROR_SIG_RXO_ERRSIGRXO_TYPE = 0 ;
+static const uint8_t P9N2_PU_NPU_SM2_ERROR_SIG_RXO_ERRSIGRXO_TYPE_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_SM2_ERROR_SIG_RXO_RSV3 = 3 ;
+static const uint8_t P9N2_PU_NPU_SM2_ERROR_SIG_RXO_ERRSIGRXO_AFUTAG = 4 ;
+static const uint8_t P9N2_PU_NPU_SM2_ERROR_SIG_RXO_ERRSIGRXO_AFUTAG_LEN = 16 ;
+static const uint8_t P9N2_PU_NPU_SM2_ERROR_SIG_RXO_ERRSIGRXO_OPCODE = 20 ;
+static const uint8_t P9N2_PU_NPU_SM2_ERROR_SIG_RXO_ERRSIGRXO_OPCODE_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_SM2_ERROR_SIG_RXO_ERRSIGRXO_ACTAG = 28 ;
+static const uint8_t P9N2_PU_NPU_SM2_ERROR_SIG_RXO_ERRSIGRXO_ACTAG_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU_SM2_ERROR_SIG_RXO_ERRSIGRXO_QINDEX = 40 ;
+static const uint8_t P9N2_PU_NPU_SM2_ERROR_SIG_RXO_ERRSIGRXO_QINDEX_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_SM2_ERROR_SIG_RXO_ERRSIGRXO_PE_HANDLE = 46 ;
+static const uint8_t P9N2_PU_NPU_SM2_ERROR_SIG_RXO_ERRSIGRXO_PE_HANDLE_LEN = 16 ;
+
+static const uint8_t P9N2__CTL_ERROR_SIG_RXO_ERRSIGRXO_TYPE = 0 ;
+static const uint8_t P9N2__CTL_ERROR_SIG_RXO_ERRSIGRXO_TYPE_LEN = 3 ;
+static const uint8_t P9N2__CTL_ERROR_SIG_RXO_RSV3 = 3 ;
+static const uint8_t P9N2__CTL_ERROR_SIG_RXO_ERRSIGRXO_AFUTAG = 4 ;
+static const uint8_t P9N2__CTL_ERROR_SIG_RXO_ERRSIGRXO_AFUTAG_LEN = 16 ;
+static const uint8_t P9N2__CTL_ERROR_SIG_RXO_ERRSIGRXO_OPCODE = 20 ;
+static const uint8_t P9N2__CTL_ERROR_SIG_RXO_ERRSIGRXO_OPCODE_LEN = 8 ;
+static const uint8_t P9N2__CTL_ERROR_SIG_RXO_ERRSIGRXO_ACTAG = 28 ;
+static const uint8_t P9N2__CTL_ERROR_SIG_RXO_ERRSIGRXO_ACTAG_LEN = 12 ;
+static const uint8_t P9N2__CTL_ERROR_SIG_RXO_ERRSIGRXO_QINDEX = 40 ;
+static const uint8_t P9N2__CTL_ERROR_SIG_RXO_ERRSIGRXO_QINDEX_LEN = 6 ;
+static const uint8_t P9N2__CTL_ERROR_SIG_RXO_ERRSIGRXO_PE_HANDLE = 46 ;
+static const uint8_t P9N2__CTL_ERROR_SIG_RXO_ERRSIGRXO_PE_HANDLE_LEN = 16 ;
+
+static const uint8_t P9N2__SM2_ERROR_SIG_RXO_ERRSIGRXO_TYPE = 0 ;
+static const uint8_t P9N2__SM2_ERROR_SIG_RXO_ERRSIGRXO_TYPE_LEN = 3 ;
+static const uint8_t P9N2__SM2_ERROR_SIG_RXO_RSV3 = 3 ;
+static const uint8_t P9N2__SM2_ERROR_SIG_RXO_ERRSIGRXO_AFUTAG = 4 ;
+static const uint8_t P9N2__SM2_ERROR_SIG_RXO_ERRSIGRXO_AFUTAG_LEN = 16 ;
+static const uint8_t P9N2__SM2_ERROR_SIG_RXO_ERRSIGRXO_OPCODE = 20 ;
+static const uint8_t P9N2__SM2_ERROR_SIG_RXO_ERRSIGRXO_OPCODE_LEN = 8 ;
+static const uint8_t P9N2__SM2_ERROR_SIG_RXO_ERRSIGRXO_ACTAG = 28 ;
+static const uint8_t P9N2__SM2_ERROR_SIG_RXO_ERRSIGRXO_ACTAG_LEN = 12 ;
+static const uint8_t P9N2__SM2_ERROR_SIG_RXO_ERRSIGRXO_QINDEX = 40 ;
+static const uint8_t P9N2__SM2_ERROR_SIG_RXO_ERRSIGRXO_QINDEX_LEN = 6 ;
+static const uint8_t P9N2__SM2_ERROR_SIG_RXO_ERRSIGRXO_PE_HANDLE = 46 ;
+static const uint8_t P9N2__SM2_ERROR_SIG_RXO_ERRSIGRXO_PE_HANDLE_LEN = 16 ;
+
+static const uint8_t P9N2_PEC_ERROR_STATUS_PCB_WRITE_NOT_ALLOWED_ERR = 0 ;
+static const uint8_t P9N2_PEC_ERROR_STATUS_PCB_READ_NOT_ALLOWED_ERR = 1 ;
+static const uint8_t P9N2_PEC_ERROR_STATUS_PCB_PARITY_ON_CMD_ERR = 2 ;
+static const uint8_t P9N2_PEC_ERROR_STATUS_PCB_ADDRESS_NOT_VALID_ERR = 3 ;
+static const uint8_t P9N2_PEC_ERROR_STATUS_PCB_PARITY_ON_ADDR_ERR = 4 ;
+static const uint8_t P9N2_PEC_ERROR_STATUS_PCB_PARITY_ON_DATA_ERR = 5 ;
+static const uint8_t P9N2_PEC_ERROR_STATUS_PCB_PROTECTED_ACCESS_INVALID_ERR = 6 ;
+static const uint8_t P9N2_PEC_ERROR_STATUS_PCB_PARITY_ON_SPCIF_ERR = 7 ;
+static const uint8_t P9N2_PEC_ERROR_STATUS_PCB_WRITE_AND_OPCG_IP_ERR = 8 ;
+static const uint8_t P9N2_PEC_ERROR_STATUS_SCAN_READ_AND_OPCG_IP_ERR = 9 ;
+static const uint8_t P9N2_PEC_ERROR_STATUS_CLOCK_CMD_CONFLICT_ERR = 10 ;
+static const uint8_t P9N2_PEC_ERROR_STATUS_SCAN_COLLISION_ERR = 11 ;
+static const uint8_t P9N2_PEC_ERROR_STATUS_PREVENTED_SCAN_COLLISION_ERR = 12 ;
+static const uint8_t P9N2_PEC_ERROR_STATUS_OPCG_TRIGGER_ERR = 13 ;
+static const uint8_t P9N2_PEC_ERROR_STATUS_PHASE_CNT_CORRUPTION_ERR = 14 ;
+static const uint8_t P9N2_PEC_ERROR_STATUS_CLOCK_CMD_PREVENTED_ERR = 15 ;
+static const uint8_t P9N2_PEC_ERROR_STATUS_PARITY_ON_OPCG_SM_ERR = 16 ;
+static const uint8_t P9N2_PEC_ERROR_STATUS_PARITY_ON_CLOCK_MUX_REG_ERR = 17 ;
+static const uint8_t P9N2_PEC_ERROR_STATUS_PARITY_ON_OPCG_REG_ERR = 18 ;
+static const uint8_t P9N2_PEC_ERROR_STATUS_PARITY_ON_SYNC_CONFIG_REG_ERR = 19 ;
+static const uint8_t P9N2_PEC_ERROR_STATUS_PARITY_ON_XSTOP_REG_ERR = 20 ;
+static const uint8_t P9N2_PEC_ERROR_STATUS_PARITY_ON_GPIO_REG_ERR = 21 ;
+static const uint8_t P9N2_PEC_ERROR_STATUS_CLKCMD_REQUEST_ERR = 22 ;
+static const uint8_t P9N2_PEC_ERROR_STATUS_CBS_PROTOCOL_ERR = 23 ;
+static const uint8_t P9N2_PEC_ERROR_STATUS_VITL_ALIGN_ERR = 24 ;
+static const uint8_t P9N2_PEC_ERROR_STATUS_UNIT_SYNC_LVL_ERR = 25 ;
+static const uint8_t P9N2_PEC_ERROR_STATUS_PARITY_ON_SELFBOOT_CMD_STATE_ERR = 26 ;
+static const uint8_t P9N2_PEC_ERROR_STATUS_OPCG_STOPPED_BY_PCB_ERR = 27 ;
+static const uint8_t P9N2_PEC_ERROR_STATUS_EDRAM_SCAN_PREVENTED_ERR = 28 ;
+static const uint8_t P9N2_PEC_ERROR_STATUS_UNUSED_ERROR29 = 29 ;
+static const uint8_t P9N2_PEC_ERROR_STATUS_UNUSED_ERROR30 = 30 ;
+static const uint8_t P9N2_PEC_ERROR_STATUS_UNUSED_ERROR31 = 31 ;
+
+static const uint8_t P9N2_CAPP_ERRRPT_APC_COLLISION = 0 ;
+static const uint8_t P9N2_CAPP_ERRRPT_FSM_SM_ERROR = 1 ;
+static const uint8_t P9N2_CAPP_ERRRPT_RBUFSM_ERROR = 2 ;
+static const uint8_t P9N2_CAPP_ERRRPT_WBUF_SM_ERROR = 3 ;
+static const uint8_t P9N2_CAPP_ERRRPT_PERR_BAR_REG = 4 ;
+static const uint8_t P9N2_CAPP_ERRRPT_PERR_NONBAR_REG = 5 ;
+static const uint8_t P9N2_CAPP_ERRRPT_RTAG_HANG_EPOCH = 6 ;
+static const uint8_t P9N2_CAPP_ERRRPT_CRSP0_REGS_CE_ERR = 7 ;
+static const uint8_t P9N2_CAPP_ERRRPT_CRSP1_REGS_CE_ERR = 8 ;
+static const uint8_t P9N2_CAPP_ERRRPT_UOP_REGS_CE_ERR = 9 ;
+static const uint8_t P9N2_CAPP_ERRRPT_CRSP0_REGS_UE_ERR = 10 ;
+static const uint8_t P9N2_CAPP_ERRRPT_CRSP1_REGS_UE_ERR = 11 ;
+static const uint8_t P9N2_CAPP_ERRRPT_UOP_REGS_UE_ERR = 12 ;
+static const uint8_t P9N2_CAPP_ERRRPT_CRSP0_REGS_ATAG_PERR = 13 ;
+static const uint8_t P9N2_CAPP_ERRRPT_CRSP0_REGS_TTAG_PERR = 14 ;
+static const uint8_t P9N2_CAPP_ERRRPT_CRSP1_REGS_ATAG_PERR = 15 ;
+static const uint8_t P9N2_CAPP_ERRRPT_CRSP1_REGS_TTAG_PERR = 16 ;
+static const uint8_t P9N2_CAPP_ERRRPT_FIR_ACTION1 = 17 ;
+static const uint8_t P9N2_CAPP_ERRRPT_FIR_ACTION2 = 18 ;
+static const uint8_t P9N2_CAPP_ERRRPT_FIR_ACTION3 = 19 ;
+static const uint8_t P9N2_CAPP_ERRRPT_UNEXPECTED_CRESP = 20 ;
+static const uint8_t P9N2_CAPP_ERRRPT_LD_CLASS_ARE_ERROR = 21 ;
+static const uint8_t P9N2_CAPP_ERRRPT_ST_CLASS_ARE_ERROR = 22 ;
+static const uint8_t P9N2_CAPP_ERRRPT_LD_CLASS_ACK_DEAD = 23 ;
+static const uint8_t P9N2_CAPP_ERRRPT_FOREIGN_OP_HANG = 24 ;
+static const uint8_t P9N2_CAPP_ERRRPT_DOMESTIC_OP_HANG = 25 ;
+static const uint8_t P9N2_CAPP_ERRRPT_ST_CLASS_ACK_DEAD = 26 ;
+static const uint8_t P9N2_CAPP_ERRRPT_ACTIVATE_FSMERR = 27 ;
+static const uint8_t P9N2_CAPP_ERRRPT_SPARE1 = 28 ;
+static const uint8_t P9N2_CAPP_ERRRPT_SPARE2 = 29 ;
+static const uint8_t P9N2_CAPP_ERRRPT_CMDQ_CE_ERR = 30 ;
+static const uint8_t P9N2_CAPP_ERRRPT_CMDQ_UE_ERR = 31 ;
+static const uint8_t P9N2_CAPP_ERRRPT_CRSP2_REGS_CE_ERR = 32 ;
+static const uint8_t P9N2_CAPP_ERRRPT_CRSP3_REGS_CE_ERR = 33 ;
+static const uint8_t P9N2_CAPP_ERRRPT_CRSP2_REGS_UE_ERR = 34 ;
+static const uint8_t P9N2_CAPP_ERRRPT_CRSP3_REGS_UE_ERR = 35 ;
+static const uint8_t P9N2_CAPP_ERRRPT_CRSP2_REGS_ATAG_PERR = 36 ;
+static const uint8_t P9N2_CAPP_ERRRPT_CRSP3_REGS_ATAG_PERR = 37 ;
+static const uint8_t P9N2_CAPP_ERRRPT_CRSP2_REGS_TTAG_PERR = 38 ;
+static const uint8_t P9N2_CAPP_ERRRPT_CRSP3_REGS_TTAG_PERR = 39 ;
+static const uint8_t P9N2_CAPP_ERRRPT_SNPRTAG_REGS_CE_ERR0 = 40 ;
+static const uint8_t P9N2_CAPP_ERRRPT_SNPRTAG_REGS_CE_ERR1 = 41 ;
+static const uint8_t P9N2_CAPP_ERRRPT_SNPRTAG_REGS_CE_ERR2 = 42 ;
+static const uint8_t P9N2_CAPP_ERRRPT_SNPRTAG_REGS_UE_ERR0 = 43 ;
+static const uint8_t P9N2_CAPP_ERRRPT_SNPRTAG_REGS_UE_ERR1 = 44 ;
+static const uint8_t P9N2_CAPP_ERRRPT_SNPRTAG_REGS_UE_ERR2 = 45 ;
+
+static const uint8_t P9N2__SM2_ERR_FIRST_BITS = 0 ;
+static const uint8_t P9N2__SM2_ERR_FIRST_BITS_LEN = 64 ;
+
+static const uint8_t P9N2__SM2_ERR_HOLD_DEBUG0_CONFIG_P = 0 ;
+static const uint8_t P9N2__SM2_ERR_HOLD_DEBUG1_CONFIG_P = 1 ;
+static const uint8_t P9N2__SM2_ERR_HOLD_XTS_CONFIG_P = 2 ;
+static const uint8_t P9N2__SM2_ERR_HOLD_XTS_CONFIG2_P = 3 ;
+static const uint8_t P9N2__SM2_ERR_HOLD_XTS_CONFIG3_P = 4 ;
+static const uint8_t P9N2__SM2_ERR_HOLD_UNUSED1 = 5 ;
+static const uint8_t P9N2__SM2_ERR_HOLD_UNUSED1_LEN = 3 ;
+static const uint8_t P9N2__SM2_ERR_HOLD_SNP_REG_ERR0 = 8 ;
+static const uint8_t P9N2__SM2_ERR_HOLD_SNP_REG_ERR1 = 9 ;
+static const uint8_t P9N2__SM2_ERR_HOLD_SNP_REG_ERR2 = 10 ;
+static const uint8_t P9N2__SM2_ERR_HOLD_SNP_REG_ERR3 = 11 ;
+static const uint8_t P9N2__SM2_ERR_HOLD_SNP_REG_ERR4 = 12 ;
+static const uint8_t P9N2__SM2_ERR_HOLD_SNP_REG_ERR5 = 13 ;
+static const uint8_t P9N2__SM2_ERR_HOLD_SNP_REG_ERR6 = 14 ;
+static const uint8_t P9N2__SM2_ERR_HOLD_ATR_SM_STATE = 15 ;
+static const uint8_t P9N2__SM2_ERR_HOLD_ATSD_SM_STATE = 16 ;
+static const uint8_t P9N2__SM2_ERR_HOLD_ATR_TIMEOUT = 17 ;
+static const uint8_t P9N2__SM2_ERR_HOLD_ATSD_TIMEOUT = 18 ;
+static const uint8_t P9N2__SM2_ERR_HOLD_ATSD_BAD_TAG = 19 ;
+static const uint8_t P9N2__SM2_ERR_HOLD_MAP_REG_ERR2 = 20 ;
+static const uint8_t P9N2__SM2_ERR_HOLD_MAP_REG_ERR3 = 21 ;
+static const uint8_t P9N2__SM2_ERR_HOLD_MAP_REG_ERR4 = 22 ;
+static const uint8_t P9N2__SM2_ERR_HOLD_ATR_ARBSTATE = 23 ;
+static const uint8_t P9N2__SM2_ERR_HOLD_ATR_RADDR_BND = 24 ;
+static const uint8_t P9N2__SM2_ERR_HOLD_UNUSED2 = 25 ;
+static const uint8_t P9N2__SM2_ERR_HOLD_UNUSED2_LEN = 7 ;
+static const uint8_t P9N2__SM2_ERR_HOLD_IFC_REG_CERR0 = 32 ;
+static const uint8_t P9N2__SM2_ERR_HOLD_IFC_REG_CERR1 = 33 ;
+static const uint8_t P9N2__SM2_ERR_HOLD_IFC_REG_CERR2 = 34 ;
+static const uint8_t P9N2__SM2_ERR_HOLD_MAP_REG_CERR0 = 35 ;
+static const uint8_t P9N2__SM2_ERR_HOLD_MAP_REG_CERR1 = 36 ;
+static const uint8_t P9N2__SM2_ERR_HOLD_UNUSED3 = 37 ;
+static const uint8_t P9N2__SM2_ERR_HOLD_UNUSED3_LEN = 11 ;
+static const uint8_t P9N2__SM2_ERR_HOLD_IFC_REG_ERR0 = 48 ;
+static const uint8_t P9N2__SM2_ERR_HOLD_IFC_REG_ERR1 = 49 ;
+static const uint8_t P9N2__SM2_ERR_HOLD_IFC_REG_ERR2 = 50 ;
+static const uint8_t P9N2__SM2_ERR_HOLD_IFC_REG_ERR3 = 51 ;
+static const uint8_t P9N2__SM2_ERR_HOLD_IFC_REG_ERR4 = 52 ;
+static const uint8_t P9N2__SM2_ERR_HOLD_IFC_REG_ERR5 = 53 ;
+static const uint8_t P9N2__SM2_ERR_HOLD_IFC_REG_ERR6 = 54 ;
+static const uint8_t P9N2__SM2_ERR_HOLD_IFC_REG_ERR7 = 55 ;
+static const uint8_t P9N2__SM2_ERR_HOLD_IFC_REG_ERR8 = 56 ;
+static const uint8_t P9N2__SM2_ERR_HOLD_MAP_REG_ERR0 = 57 ;
+static const uint8_t P9N2__SM2_ERR_HOLD_MAP_REG_ERR1 = 58 ;
+static const uint8_t P9N2__SM2_ERR_HOLD_UNUSED4 = 59 ;
+static const uint8_t P9N2__SM2_ERR_HOLD_UNUSED4_LEN = 4 ;
+static const uint8_t P9N2__SM2_ERR_HOLD_ATR_MISS_IRQ = 63 ;
+
+static const uint8_t P9N2__CTL_ERR_INFO_NPU_RING_ADDR_MISC = 0 ;
+static const uint8_t P9N2__CTL_ERR_INFO_NPU_RING_ADDR_MISC_LEN = 24 ;
+static const uint8_t P9N2__CTL_ERR_INFO_NPU_RING_ADDR_MISC_LENR = 24 ;
+static const uint8_t P9N2__CTL_ERR_INFO_NPU_RING_ADDR_MISC_LENR_LEN = 2 ;
+static const uint8_t P9N2__CTL_ERR_INFO_NPU_RING_ADDR_MISC_RNW = 26 ;
+static const uint8_t P9N2__CTL_ERR_INFO_NPU_RING_ADDR_MISC_DA_OP = 27 ;
+
+static const uint8_t P9N2__SM2_ERR_MASK_BITS = 0 ;
+static const uint8_t P9N2__SM2_ERR_MASK_BITS_LEN = 64 ;
+
+static const uint8_t P9N2__CTL_ERR_SCOPE_CTL_CONFIG_CTL = 0 ;
+static const uint8_t P9N2__CTL_ERR_SCOPE_CTL_CONFIG_CTL_LEN = 16 ;
+
+static const uint8_t P9N2_PEC_ERR_STATUS_REG_SERIAL_SHIFTCNT_MODEREG_PARITY_ERR_HOLD = 0 ;
+static const uint8_t P9N2_PEC_ERR_STATUS_REG_THERM_MODEREG_PARITY_ERR_HOLD = 1 ;
+static const uint8_t P9N2_PEC_ERR_STATUS_REG_SKITTER_MODEREG_PARITY_ERR_HOLD = 2 ;
+static const uint8_t P9N2_PEC_ERR_STATUS_REG_SKITTER_FORCEREG_PARITY_ERR_HOLD = 3 ;
+static const uint8_t P9N2_PEC_ERR_STATUS_REG_SCAN_INIT_VERSION_REG_PARITY_ERR_HOLD = 4 ;
+static const uint8_t P9N2_PEC_ERR_STATUS_REG_VOLT_MODEREG_PARITY_ERR_HOLD = 5 ;
+static const uint8_t P9N2_PEC_ERR_STATUS_REG_SKITTER_CLKSRCREG_PARITY_ERR_HOLD = 6 ;
+static const uint8_t P9N2_PEC_ERR_STATUS_REG_COUNT_STATE_ERR_HOLD = 7 ;
+static const uint8_t P9N2_PEC_ERR_STATUS_REG_RUN_STATE_ERR_HOLD = 8 ;
+static const uint8_t P9N2_PEC_ERR_STATUS_REG_THRES_THERM_STATE_ERR_HOLD = 9 ;
+static const uint8_t P9N2_PEC_ERR_STATUS_REG_THRES_THERM_OVERFLOW_ERR_HOLD = 10 ;
+static const uint8_t P9N2_PEC_ERR_STATUS_REG_SHIFTER_PARITY_ERR_HOLD = 11 ;
+static const uint8_t P9N2_PEC_ERR_STATUS_REG_SHIFTER_VALID_ERR_HOLD = 12 ;
+static const uint8_t P9N2_PEC_ERR_STATUS_REG_TIMEOUT_ERR_HOLD = 13 ;
+static const uint8_t P9N2_PEC_ERR_STATUS_REG_F_SKITTER_ERR_HOLD = 14 ;
+static const uint8_t P9N2_PEC_ERR_STATUS_REG_PCB_ERR_HOLD_OUT = 15 ;
+static const uint8_t P9N2_PEC_ERR_STATUS_REG_SERIAL_SHIFTCNT_MODEREG_PARITY_MASK = 16 ;
+static const uint8_t P9N2_PEC_ERR_STATUS_REG_THERM_MODEREG_PARITY_MASK = 17 ;
+static const uint8_t P9N2_PEC_ERR_STATUS_REG_SKITTER_MODEREG_PARITY_MASK = 18 ;
+static const uint8_t P9N2_PEC_ERR_STATUS_REG_SKITTER_FORCEREG_PARITY_MASK = 19 ;
+static const uint8_t P9N2_PEC_ERR_STATUS_REG_SCAN_INIT_VERSION_PARITY_MASK = 20 ;
+static const uint8_t P9N2_PEC_ERR_STATUS_REG_VOLT_MODEREG_PARITY_MASK = 21 ;
+static const uint8_t P9N2_PEC_ERR_STATUS_REG_COUNT_STATE_MASK = 23 ;
+static const uint8_t P9N2_PEC_ERR_STATUS_REG_RUN_STATE_MASK = 24 ;
+static const uint8_t P9N2_PEC_ERR_STATUS_REG_THRES_STATE_MASK = 25 ;
+static const uint8_t P9N2_PEC_ERR_STATUS_REG_OVERFLOW_MASK = 26 ;
+static const uint8_t P9N2_PEC_ERR_STATUS_REG_SHIFTER_PARITY_MASK = 27 ;
+static const uint8_t P9N2_PEC_ERR_STATUS_REG_SHIFTER_VALID_MASK = 28 ;
+static const uint8_t P9N2_PEC_ERR_STATUS_REG_TIMEOUT_MASK = 29 ;
+static const uint8_t P9N2_PEC_ERR_STATUS_REG_F_SKITTER_READ_MASK = 30 ;
+static const uint8_t P9N2_PEC_ERR_STATUS_REG_PCB_MASK = 31 ;
+static const uint8_t P9N2_PEC_ERR_STATUS_REG_COUNT_STATE_LT = 40 ;
+static const uint8_t P9N2_PEC_ERR_STATUS_REG_COUNT_STATE_LT_LEN = 4 ;
+static const uint8_t P9N2_PEC_ERR_STATUS_REG_RUN_STATE_LT = 44 ;
+static const uint8_t P9N2_PEC_ERR_STATUS_REG_RUN_STATE_LT_LEN = 3 ;
+static const uint8_t P9N2_PEC_ERR_STATUS_REG_SHIFT_DTS_LT = 47 ;
+static const uint8_t P9N2_PEC_ERR_STATUS_REG_SHIFT_VOLT_LT = 48 ;
+static const uint8_t P9N2_PEC_ERR_STATUS_REG_READ_STATE_LT = 49 ;
+static const uint8_t P9N2_PEC_ERR_STATUS_REG_READ_STATE_LT_LEN = 2 ;
+static const uint8_t P9N2_PEC_ERR_STATUS_REG_WRITE_STATE_LT = 51 ;
+static const uint8_t P9N2_PEC_ERR_STATUS_REG_WRITE_STATE_LT_LEN = 4 ;
+static const uint8_t P9N2_PEC_ERR_STATUS_REG_SAMPLE_DTS_LT = 55 ;
+static const uint8_t P9N2_PEC_ERR_STATUS_REG_MEASURE_VOLT_LT = 56 ;
+static const uint8_t P9N2_PEC_ERR_STATUS_REG_READ_CPM_LT = 57 ;
+static const uint8_t P9N2_PEC_ERR_STATUS_REG_WRITE_CPM_LT = 58 ;
+static const uint8_t P9N2_PEC_ERR_STATUS_REG_UNUSED = 59 ;
+
+static const uint8_t P9N2_PU_ESB_CI_BASE_BASE = 8 ;
+static const uint8_t P9N2_PU_ESB_CI_BASE_BASE_LEN = 40 ;
+static const uint8_t P9N2_PU_ESB_CI_BASE_VALID = 63 ;
+
+static const uint8_t P9N2_PU_ESB_NOTIFY_ADDR = 8 ;
+static const uint8_t P9N2_PU_ESB_NOTIFY_ADDR_LEN = 53 ;
+static const uint8_t P9N2_PU_ESB_NOTIFY_VALID = 63 ;
+
+static const uint8_t P9N2_PU_EXPORT_REGL_CTRL_TP_NX_ALLOW_CRYPTO_DC = 0 ;
+static const uint8_t P9N2_PU_EXPORT_REGL_CTRL_TP_EX_FUSE_VMX_CRYPTO_DIS_DC = 1 ;
+static const uint8_t P9N2_PU_EXPORT_REGL_CTRL_TP_EX_FUSE_FP_THROTTLE_EN_DC = 2 ;
+static const uint8_t P9N2_PU_EXPORT_REGL_CTRL_TP_PB_FUSE_TOPOLOGY_2CHIP = 3 ;
+static const uint8_t P9N2_PU_EXPORT_REGL_CTRL_TP_PB_FUSE_TOPOLOGY_GROUP = 4 ;
+static const uint8_t P9N2_PU_EXPORT_REGL_CTRL_TP_PB_FUSE_TOPOLOGY_GROUP_LEN = 2 ;
+static const uint8_t P9N2_PU_EXPORT_REGL_CTRL_TP_NP_NVLINK_DISABLE = 6 ;
+static const uint8_t P9N2_PU_EXPORT_REGL_CTRL_OTP_PCBMS_HW_MODE_SEL_DC = 7 ;
+static const uint8_t P9N2_PU_EXPORT_REGL_CTRL_OTP_PCBMS_FUSED_CORE_MODE_SEL0_DC = 8 ;
+static const uint8_t P9N2_PU_EXPORT_REGL_CTRL_OTP_PCBMS_FUSED_CORE_MODE_SEL1_DC = 9 ;
+
+static const uint8_t P9N2_PU_EXTENDED_STATUS_B_MSM_CURR_STATE_0 = 11 ;
+static const uint8_t P9N2_PU_EXTENDED_STATUS_B_MSM_CURR_STATE_0_LEN = 5 ;
+static const uint8_t P9N2_PU_EXTENDED_STATUS_B_SELF_BUSY_0 = 25 ;
+static const uint8_t P9N2_PU_EXTENDED_STATUS_B_PEEK_DATA1_0 = 32 ;
+static const uint8_t P9N2_PU_EXTENDED_STATUS_B_PEEK_DATA1_0_LEN = 8 ;
+static const uint8_t P9N2_PU_EXTENDED_STATUS_B_LBUS_PARITY_ERR1_0 = 40 ;
+
+static const uint8_t P9N2_PU_EXTENDED_STATUS_C_MSM_CURR_STATE_1 = 11 ;
+static const uint8_t P9N2_PU_EXTENDED_STATUS_C_MSM_CURR_STATE_1_LEN = 5 ;
+static const uint8_t P9N2_PU_EXTENDED_STATUS_C_SELF_BUSY_1 = 25 ;
+static const uint8_t P9N2_PU_EXTENDED_STATUS_C_PEEK_DATA1_1 = 32 ;
+static const uint8_t P9N2_PU_EXTENDED_STATUS_C_PEEK_DATA1_1_LEN = 8 ;
+static const uint8_t P9N2_PU_EXTENDED_STATUS_C_LBUS_PARITY_ERR1_1 = 40 ;
+
+static const uint8_t P9N2_PU_EXTENDED_STATUS_D_MSM_CURR_STATE_2 = 11 ;
+static const uint8_t P9N2_PU_EXTENDED_STATUS_D_MSM_CURR_STATE_2_LEN = 5 ;
+static const uint8_t P9N2_PU_EXTENDED_STATUS_D_SELF_BUSY_2 = 25 ;
+static const uint8_t P9N2_PU_EXTENDED_STATUS_D_PEEK_DATA1_2 = 32 ;
+static const uint8_t P9N2_PU_EXTENDED_STATUS_D_PEEK_DATA1_2_LEN = 8 ;
+static const uint8_t P9N2_PU_EXTENDED_STATUS_D_LBUS_PARITY_ERR1_2 = 40 ;
+
+static const uint8_t P9N2_PU_EXTENDED_STATUS_E_MSM_CURR_STATE_3 = 11 ;
+static const uint8_t P9N2_PU_EXTENDED_STATUS_E_MSM_CURR_STATE_3_LEN = 5 ;
+static const uint8_t P9N2_PU_EXTENDED_STATUS_E_SELF_BUSY_3 = 25 ;
+static const uint8_t P9N2_PU_EXTENDED_STATUS_E_PEEK_DATA1_3 = 32 ;
+static const uint8_t P9N2_PU_EXTENDED_STATUS_E_PEEK_DATA1_3_LEN = 8 ;
+static const uint8_t P9N2_PU_EXTENDED_STATUS_E_LBUS_PARITY_ERR1_3 = 40 ;
+
+static const uint8_t P9N2_PU_PB_CENT_SM1_EXTFIR_ACTION0_REG_ACTION0 = 0 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_EXTFIR_ACTION0_REG_ACTION0_LEN = 8 ;
+
+static const uint8_t P9N2_PU_PB_CENT_SM1_EXTFIR_ACTION1_REG_ACTION1 = 0 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_EXTFIR_ACTION1_REG_ACTION1_LEN = 8 ;
+
+static const uint8_t P9N2_PU_PB_CENT_SM1_EXTFIR_MASK_REG_PB_X0_FIR_ERR = 0 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_EXTFIR_MASK_REG_PB_X1_FIR_ERR = 1 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_EXTFIR_MASK_REG_PB_X2_FIR_ERR = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_EXTFIR_MASK_REG_PB_X3_FIR_ERR = 3 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_EXTFIR_MASK_REG_PB_X4_FIR_ERR = 4 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_EXTFIR_MASK_REG_PB_X5_FIR_ERR = 5 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_EXTFIR_MASK_REG_PB_X6_FIR_ERR = 6 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_EXTFIR_MASK_REG_SCOM_ERROR = 7 ;
+
+static const uint8_t P9N2_PU_PB_CENT_SM1_EXTFIR_REG_PB_X0_FIR_ERR = 0 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_EXTFIR_REG_PB_X1_FIR_ERR = 1 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_EXTFIR_REG_PB_X2_FIR_ERR = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_EXTFIR_REG_PB_X3_FIR_ERR = 3 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_EXTFIR_REG_PB_X4_FIR_ERR = 4 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_EXTFIR_REG_PB_X5_FIR_ERR = 5 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_EXTFIR_REG_PB_X6_FIR_ERR = 6 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_EXTFIR_REG_SCOM_ERROR = 7 ;
+
+static const uint8_t P9N2__CTL_FENCE_0_CONFIG_0 = 0 ;
+static const uint8_t P9N2__CTL_FENCE_0_CONFIG_0_LEN = 64 ;
+
+static const uint8_t P9N2__CTL_FENCE_1_CONFIG_1 = 0 ;
+static const uint8_t P9N2__CTL_FENCE_1_CONFIG_1_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU_SM0_FENCE_2_CONFIG_2 = 0 ;
+static const uint8_t P9N2_PU_NPU_SM0_FENCE_2_CONFIG_2_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU2_NTL1_FENCE_CONTROL0_FENCE0_REQUEST = 0 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_FENCE_CONTROL0_FENCE0_REQUEST_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_FENCE_CONTROL0_RESERVED = 2 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_FENCE_CONTROL0_RESERVED_LEN = 2 ;
+
+static const uint8_t P9N2_PU_NPU2_NTL1_FENCE_CONTROL1_FENCE1_REQUEST = 0 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_FENCE_CONTROL1_FENCE1_REQUEST_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_FENCE_CONTROL1_RESERVED = 2 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_FENCE_CONTROL1_RESERVED_LEN = 2 ;
+
+static const uint8_t P9N2__CTL_FENCE_STATE_BRK0 = 0 ;
+static const uint8_t P9N2__CTL_FENCE_STATE_BRK1 = 1 ;
+static const uint8_t P9N2__CTL_FENCE_STATE_BRK2 = 2 ;
+static const uint8_t P9N2__CTL_FENCE_STATE_BRK3 = 3 ;
+static const uint8_t P9N2__CTL_FENCE_STATE_BRK4 = 4 ;
+static const uint8_t P9N2__CTL_FENCE_STATE_BRK5 = 5 ;
+
+static const uint8_t P9N2_PU_FI2C_CFG_PIBI2CM_PIB_SLAVE_ID = 0 ;
+static const uint8_t P9N2_PU_FI2C_CFG_PIBI2CM_PIB_SLAVE_ID_LEN = 16 ;
+static const uint8_t P9N2_PU_FI2C_CFG_ECC_ENABLE = 16 ;
+static const uint8_t P9N2_PU_FI2C_CFG_DISABLE_ECC_CHK = 17 ;
+static const uint8_t P9N2_PU_FI2C_CFG_I2C_SPEED_MUX = 18 ;
+static const uint8_t P9N2_PU_FI2C_CFG_I2C_SPEED_MUX_LEN = 2 ;
+static const uint8_t P9N2_PU_FI2C_CFG_BIT_RATE_DIVISOR_VALUE = 20 ;
+static const uint8_t P9N2_PU_FI2C_CFG_BIT_RATE_DIVISOR_VALUE_LEN = 16 ;
+static const uint8_t P9N2_PU_FI2C_CFG_I2C_BUS_HELD_MODE_ENABLE = 36 ;
+static const uint8_t P9N2_PU_FI2C_CFG_PIPELINE_ENABLE = 37 ;
+static const uint8_t P9N2_PU_FI2C_CFG_BACKUP_SEEPROM_SELECT = 38 ;
+static const uint8_t P9N2_PU_FI2C_CFG_FORCE_RESET = 39 ;
+static const uint8_t P9N2_PU_FI2C_CFG_RESET_PIB = 40 ;
+static const uint8_t P9N2_PU_FI2C_CFG_DISABLE_TIMEOUT = 41 ;
+static const uint8_t P9N2_PU_FI2C_CFG_RESERVED_FOR_CONFIGS = 42 ;
+static const uint8_t P9N2_PU_FI2C_CFG_RESERVED_FOR_CONFIGS_LEN = 18 ;
+
+static const uint8_t P9N2_PU_FI2C_SCFG0_REGISTER_VALID = 0 ;
+static const uint8_t P9N2_PU_FI2C_SCFG0_RESERVED_3 = 1 ;
+static const uint8_t P9N2_PU_FI2C_SCFG0_RESERVED_4 = 2 ;
+static const uint8_t P9N2_PU_FI2C_SCFG0_RESERVED_4_LEN = 2 ;
+static const uint8_t P9N2_PU_FI2C_SCFG0_RESERVED_5 = 4 ;
+static const uint8_t P9N2_PU_FI2C_SCFG0_RESERVED_5_LEN = 4 ;
+static const uint8_t P9N2_PU_FI2C_SCFG0_DEVICE_ID = 8 ;
+static const uint8_t P9N2_PU_FI2C_SCFG0_DEVICE_ID_LEN = 7 ;
+static const uint8_t P9N2_PU_FI2C_SCFG0_ECC_ENABLE = 15 ;
+static const uint8_t P9N2_PU_FI2C_SCFG0_MEMORY_SIZE_IN_PPE_ADDR_MAP = 16 ;
+static const uint8_t P9N2_PU_FI2C_SCFG0_MEMORY_SIZE_IN_PPE_ADDR_MAP_LEN = 16 ;
+static const uint8_t P9N2_PU_FI2C_SCFG0_START_SEEPROM_ADDRESS = 32 ;
+static const uint8_t P9N2_PU_FI2C_SCFG0_START_SEEPROM_ADDRESS_LEN = 16 ;
+static const uint8_t P9N2_PU_FI2C_SCFG0_START_PPE_ADDR = 48 ;
+static const uint8_t P9N2_PU_FI2C_SCFG0_START_PPE_ADDR_LEN = 16 ;
+
+static const uint8_t P9N2_PU_FI2C_SCFG1_REGISTER_VALID = 0 ;
+static const uint8_t P9N2_PU_FI2C_SCFG1_RESERVED_6 = 1 ;
+static const uint8_t P9N2_PU_FI2C_SCFG1_RESERVED_7 = 2 ;
+static const uint8_t P9N2_PU_FI2C_SCFG1_RESERVED_7_LEN = 2 ;
+static const uint8_t P9N2_PU_FI2C_SCFG1_RESERVED_8 = 4 ;
+static const uint8_t P9N2_PU_FI2C_SCFG1_RESERVED_8_LEN = 4 ;
+static const uint8_t P9N2_PU_FI2C_SCFG1_DEVICE_ID = 8 ;
+static const uint8_t P9N2_PU_FI2C_SCFG1_DEVICE_ID_LEN = 7 ;
+static const uint8_t P9N2_PU_FI2C_SCFG1_ECC_ENABLE = 15 ;
+static const uint8_t P9N2_PU_FI2C_SCFG1_MEMORY_SIZE_IN_PPE_ADDR_MAP = 16 ;
+static const uint8_t P9N2_PU_FI2C_SCFG1_MEMORY_SIZE_IN_PPE_ADDR_MAP_LEN = 16 ;
+static const uint8_t P9N2_PU_FI2C_SCFG1_START_SEEPROM_ADDRESS = 32 ;
+static const uint8_t P9N2_PU_FI2C_SCFG1_START_SEEPROM_ADDRESS_LEN = 16 ;
+static const uint8_t P9N2_PU_FI2C_SCFG1_START_PPE_ADDR = 48 ;
+static const uint8_t P9N2_PU_FI2C_SCFG1_START_PPE_ADDR_LEN = 16 ;
+
+static const uint8_t P9N2_PU_FI2C_SCFG2_REGISTER_VALID = 0 ;
+static const uint8_t P9N2_PU_FI2C_SCFG2_RESERVED_9 = 1 ;
+static const uint8_t P9N2_PU_FI2C_SCFG2_RESERVED_10 = 2 ;
+static const uint8_t P9N2_PU_FI2C_SCFG2_RESERVED_10_LEN = 2 ;
+static const uint8_t P9N2_PU_FI2C_SCFG2_RESERVED_11 = 4 ;
+static const uint8_t P9N2_PU_FI2C_SCFG2_RESERVED_11_LEN = 4 ;
+static const uint8_t P9N2_PU_FI2C_SCFG2_DEVICE_ID = 8 ;
+static const uint8_t P9N2_PU_FI2C_SCFG2_DEVICE_ID_LEN = 7 ;
+static const uint8_t P9N2_PU_FI2C_SCFG2_ECC_ENABLE = 15 ;
+static const uint8_t P9N2_PU_FI2C_SCFG2_MEMORY_SIZE_IN_PPE_ADDR_MAP = 16 ;
+static const uint8_t P9N2_PU_FI2C_SCFG2_MEMORY_SIZE_IN_PPE_ADDR_MAP_LEN = 16 ;
+static const uint8_t P9N2_PU_FI2C_SCFG2_START_SEEPROM_ADDRESS = 32 ;
+static const uint8_t P9N2_PU_FI2C_SCFG2_START_SEEPROM_ADDRESS_LEN = 16 ;
+static const uint8_t P9N2_PU_FI2C_SCFG2_START_PPE_ADDR = 48 ;
+static const uint8_t P9N2_PU_FI2C_SCFG2_START_PPE_ADDR_LEN = 16 ;
+
+static const uint8_t P9N2_PU_FI2C_SCFG3_REGISTER_VALID = 0 ;
+static const uint8_t P9N2_PU_FI2C_SCFG3_RESERVED_12 = 1 ;
+static const uint8_t P9N2_PU_FI2C_SCFG3_RESERVED_13 = 2 ;
+static const uint8_t P9N2_PU_FI2C_SCFG3_RESERVED_13_LEN = 2 ;
+static const uint8_t P9N2_PU_FI2C_SCFG3_RESERVED_14 = 4 ;
+static const uint8_t P9N2_PU_FI2C_SCFG3_RESERVED_14_LEN = 4 ;
+static const uint8_t P9N2_PU_FI2C_SCFG3_DEVICE_ID = 8 ;
+static const uint8_t P9N2_PU_FI2C_SCFG3_DEVICE_ID_LEN = 7 ;
+static const uint8_t P9N2_PU_FI2C_SCFG3_ECC_ENABLE = 15 ;
+static const uint8_t P9N2_PU_FI2C_SCFG3_MEMORY_SIZE_IN_PPE_ADDR_MAP = 16 ;
+static const uint8_t P9N2_PU_FI2C_SCFG3_MEMORY_SIZE_IN_PPE_ADDR_MAP_LEN = 16 ;
+static const uint8_t P9N2_PU_FI2C_SCFG3_START_SEEPROM_ADDRESS = 32 ;
+static const uint8_t P9N2_PU_FI2C_SCFG3_START_SEEPROM_ADDRESS_LEN = 16 ;
+static const uint8_t P9N2_PU_FI2C_SCFG3_START_PPE_ADDR = 48 ;
+static const uint8_t P9N2_PU_FI2C_SCFG3_START_PPE_ADDR_LEN = 16 ;
+
+static const uint8_t P9N2_PU_FI2C_STAT_PIB_RESPONSE_INFO = 0 ;
+static const uint8_t P9N2_PU_FI2C_STAT_PIB_RESPONSE_INFO_LEN = 3 ;
+static const uint8_t P9N2_PU_FI2C_STAT_I2CM_PIB_ERRORS = 3 ;
+static const uint8_t P9N2_PU_FI2C_STAT_I2CM_PIB_ERRORS_LEN = 6 ;
+static const uint8_t P9N2_PU_FI2C_STAT_I2CM_ECC_ERRORS = 9 ;
+static const uint8_t P9N2_PU_FI2C_STAT_I2CM_ECC_ERRORS_LEN = 3 ;
+static const uint8_t P9N2_PU_FI2C_STAT_I2CM_I2C_ERRORS = 12 ;
+static const uint8_t P9N2_PU_FI2C_STAT_I2CM_I2C_ERRORS_LEN = 7 ;
+static const uint8_t P9N2_PU_FI2C_STAT_ERR_ADDR_BEYOND_RANGE = 19 ;
+static const uint8_t P9N2_PU_FI2C_STAT_ERR_ADDR_OVERLAP = 20 ;
+static const uint8_t P9N2_PU_FI2C_STAT_PIB_ABORT = 21 ;
+static const uint8_t P9N2_PU_FI2C_STAT_TIMEOUT_ON_I2C_STATUS_RD = 22 ;
+static const uint8_t P9N2_PU_FI2C_STAT_RESERVED_FOR_ERRS = 23 ;
+static const uint8_t P9N2_PU_FI2C_STAT_RESERVED_FOR_ERRS_LEN = 9 ;
+static const uint8_t P9N2_PU_FI2C_STAT_LOCKED_PIBM_ADDR = 32 ;
+static const uint8_t P9N2_PU_FI2C_STAT_LOCKED_PIBM_ADDR_LEN = 8 ;
+static const uint8_t P9N2_PU_FI2C_STAT_LOCKED_FSM_RESET_ONGOING = 40 ;
+static const uint8_t P9N2_PU_FI2C_STAT_RESERVED_FOR_ADDRESS = 41 ;
+static const uint8_t P9N2_PU_FI2C_STAT_RESERVED_FOR_ADDRESS_LEN = 2 ;
+static const uint8_t P9N2_PU_FI2C_STAT_LOCKED_FSM_STATE = 43 ;
+static const uint8_t P9N2_PU_FI2C_STAT_LOCKED_FSM_STATE_LEN = 5 ;
+static const uint8_t P9N2_PU_FI2C_STAT_LOCKED_SEEPROM_ADDRESS = 48 ;
+static const uint8_t P9N2_PU_FI2C_STAT_LOCKED_SEEPROM_ADDRESS_LEN = 16 ;
+
+static const uint8_t P9N2_PU_FIFO1_REGISTER_READ_B_FIFO_BITS_READ0_0 = 0 ;
+static const uint8_t P9N2_PU_FIFO1_REGISTER_READ_B_FIFO_BITS_READ0_0_LEN = 8 ;
+static const uint8_t P9N2_PU_FIFO1_REGISTER_READ_B_PEEK_DATA1_0 = 32 ;
+static const uint8_t P9N2_PU_FIFO1_REGISTER_READ_B_PEEK_DATA1_0_LEN = 8 ;
+static const uint8_t P9N2_PU_FIFO1_REGISTER_READ_B_LBUS_PARITY_ERR1_0 = 40 ;
+
+static const uint8_t P9N2_PU_FIFO1_REGISTER_READ_C_FIFO_BITS_READ0_1 = 0 ;
+static const uint8_t P9N2_PU_FIFO1_REGISTER_READ_C_FIFO_BITS_READ0_1_LEN = 8 ;
+static const uint8_t P9N2_PU_FIFO1_REGISTER_READ_C_PEEK_DATA1_1 = 32 ;
+static const uint8_t P9N2_PU_FIFO1_REGISTER_READ_C_PEEK_DATA1_1_LEN = 8 ;
+static const uint8_t P9N2_PU_FIFO1_REGISTER_READ_C_LBUS_PARITY_ERR1_1 = 40 ;
+
+static const uint8_t P9N2_PU_FIFO1_REGISTER_READ_D_FIFO_BITS_READ0_2 = 0 ;
+static const uint8_t P9N2_PU_FIFO1_REGISTER_READ_D_FIFO_BITS_READ0_2_LEN = 8 ;
+static const uint8_t P9N2_PU_FIFO1_REGISTER_READ_D_PEEK_DATA1_2 = 32 ;
+static const uint8_t P9N2_PU_FIFO1_REGISTER_READ_D_PEEK_DATA1_2_LEN = 8 ;
+static const uint8_t P9N2_PU_FIFO1_REGISTER_READ_D_LBUS_PARITY_ERR1_2 = 40 ;
+
+static const uint8_t P9N2_PU_FIFO1_REGISTER_READ_E_FIFO_BITS_READ0_3 = 0 ;
+static const uint8_t P9N2_PU_FIFO1_REGISTER_READ_E_FIFO_BITS_READ0_3_LEN = 8 ;
+static const uint8_t P9N2_PU_FIFO1_REGISTER_READ_E_PEEK_DATA1_3 = 32 ;
+static const uint8_t P9N2_PU_FIFO1_REGISTER_READ_E_PEEK_DATA1_3_LEN = 8 ;
+static const uint8_t P9N2_PU_FIFO1_REGISTER_READ_E_LBUS_PARITY_ERR1_3 = 40 ;
+
+static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_B_FIFO_BITS_READ0_0 = 0 ;
+static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_B_FIFO_BITS_READ0_0_LEN = 8 ;
+static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_B_FIFO_BITS_READ2_0 = 8 ;
+static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_B_FIFO_BITS_READ2_0_LEN = 8 ;
+static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_B_FIFO_BITS_READ3_0 = 16 ;
+static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_B_FIFO_BITS_READ3_0_LEN = 8 ;
+static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_B_FIFO_BITS_READ4_0 = 24 ;
+static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_B_FIFO_BITS_READ4_0_LEN = 8 ;
+static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_B_PEEK_DATA1_0 = 32 ;
+static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_B_PEEK_DATA1_0_LEN = 8 ;
+static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_B_LBUS_PARITY_ERR1_0 = 40 ;
+
+static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_C_FIFO_BITS_READ0_1 = 0 ;
+static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_C_FIFO_BITS_READ0_1_LEN = 8 ;
+static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_C_FIFO_BITS_READ2_1 = 8 ;
+static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_C_FIFO_BITS_READ2_1_LEN = 8 ;
+static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_C_FIFO_BITS_READ3_1 = 16 ;
+static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_C_FIFO_BITS_READ3_1_LEN = 8 ;
+static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_C_FIFO_BITS_READ4_1 = 24 ;
+static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_C_FIFO_BITS_READ4_1_LEN = 8 ;
+static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_C_PEEK_DATA1_1 = 32 ;
+static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_C_PEEK_DATA1_1_LEN = 8 ;
+static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_C_LBUS_PARITY_ERR1_1 = 40 ;
+
+static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_D_FIFO_BITS_READ0_2 = 0 ;
+static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_D_FIFO_BITS_READ0_2_LEN = 8 ;
+static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_D_FIFO_BITS_READ2_2 = 8 ;
+static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_D_FIFO_BITS_READ2_2_LEN = 8 ;
+static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_D_FIFO_BITS_READ3_2 = 16 ;
+static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_D_FIFO_BITS_READ3_2_LEN = 8 ;
+static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_D_FIFO_BITS_READ4_2 = 24 ;
+static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_D_FIFO_BITS_READ4_2_LEN = 8 ;
+static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_D_PEEK_DATA1_2 = 32 ;
+static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_D_PEEK_DATA1_2_LEN = 8 ;
+static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_D_LBUS_PARITY_ERR1_2 = 40 ;
+
+static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_E_FIFO_BITS_READ0_3 = 0 ;
+static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_E_FIFO_BITS_READ0_3_LEN = 8 ;
+static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_E_FIFO_BITS_READ2_3 = 8 ;
+static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_E_FIFO_BITS_READ2_3_LEN = 8 ;
+static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_E_FIFO_BITS_READ3_3 = 16 ;
+static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_E_FIFO_BITS_READ3_3_LEN = 8 ;
+static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_E_FIFO_BITS_READ4_3 = 24 ;
+static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_E_FIFO_BITS_READ4_3_LEN = 8 ;
+static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_E_PEEK_DATA1_3 = 32 ;
+static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_E_PEEK_DATA1_3_LEN = 8 ;
+static const uint8_t P9N2_PU_FIFO4_REGISTER_READ_E_LBUS_PARITY_ERR1_3 = 40 ;
+
+static const uint8_t P9N2_CAPP_FIR_ACTION0_REG_ACTION0 = 0 ;
+static const uint8_t P9N2_CAPP_FIR_ACTION0_REG_ACTION0_LEN = 53 ;
+
+static const uint8_t P9N2_PEC_FIR_ACTION0_REG_ACTION0 = 0 ;
+static const uint8_t P9N2_PEC_FIR_ACTION0_REG_ACTION0_LEN = 37 ;
+
+static const uint8_t P9N2_PU_FIR_ACTION0_REG_ACTION0 = 0 ;
+static const uint8_t P9N2_PU_FIR_ACTION0_REG_ACTION0_LEN = 7 ;
+
+static const uint8_t P9N2_PU_FIR_ACTION0_REG_0_0 = 0 ;
+static const uint8_t P9N2_PU_FIR_ACTION0_REG_0_0_LEN = 64 ;
+
+static const uint8_t P9N2_PU_FIR_ACTION0_REG_1_1 = 0 ;
+static const uint8_t P9N2_PU_FIR_ACTION0_REG_1_1_LEN = 64 ;
+
+static const uint8_t P9N2_PU_FIR_ACTION0_REG_2_2 = 0 ;
+static const uint8_t P9N2_PU_FIR_ACTION0_REG_2_2_LEN = 64 ;
+
+static const uint8_t P9N2_CAPP_FIR_ACTION1_REG_ACTION1 = 0 ;
+static const uint8_t P9N2_CAPP_FIR_ACTION1_REG_ACTION1_LEN = 53 ;
+
+static const uint8_t P9N2_PEC_FIR_ACTION1_REG_ACTION1 = 0 ;
+static const uint8_t P9N2_PEC_FIR_ACTION1_REG_ACTION1_LEN = 37 ;
+
+static const uint8_t P9N2_PU_FIR_ACTION1_REG_ACTION1 = 0 ;
+static const uint8_t P9N2_PU_FIR_ACTION1_REG_ACTION1_LEN = 7 ;
+
+static const uint8_t P9N2_PU_FIR_ACTION1_REG_0_0 = 0 ;
+static const uint8_t P9N2_PU_FIR_ACTION1_REG_0_0_LEN = 64 ;
+
+static const uint8_t P9N2_PU_FIR_ACTION1_REG_1_1 = 0 ;
+static const uint8_t P9N2_PU_FIR_ACTION1_REG_1_1_LEN = 64 ;
+
+static const uint8_t P9N2_PU_FIR_ACTION1_REG_2_2 = 0 ;
+static const uint8_t P9N2_PU_FIR_ACTION1_REG_2_2_LEN = 64 ;
+
+static const uint8_t P9N2_PEC_FIR_MASK_IN0 = 0 ;
+static const uint8_t P9N2_PEC_FIR_MASK_IN1 = 1 ;
+static const uint8_t P9N2_PEC_FIR_MASK_IN2 = 2 ;
+static const uint8_t P9N2_PEC_FIR_MASK_IN3 = 3 ;
+static const uint8_t P9N2_PEC_FIR_MASK_IN4 = 4 ;
+static const uint8_t P9N2_PEC_FIR_MASK_IN5 = 5 ;
+static const uint8_t P9N2_PEC_FIR_MASK_IN6 = 6 ;
+static const uint8_t P9N2_PEC_FIR_MASK_IN7 = 7 ;
+static const uint8_t P9N2_PEC_FIR_MASK_IN7_LEN = 19 ;
+static const uint8_t P9N2_PEC_FIR_MASK_IN26 = 26 ;
+
+static const uint8_t P9N2_CAPP_FIR_MASK_REG_BAR_PE = 0 ;
+static const uint8_t P9N2_CAPP_FIR_MASK_REG_REGISTER_PE = 1 ;
+static const uint8_t P9N2_CAPP_FIR_MASK_REG_MASTER_ARRAY_CE = 2 ;
+static const uint8_t P9N2_CAPP_FIR_MASK_REG_MASTER_ARRAY_UE = 3 ;
+static const uint8_t P9N2_CAPP_FIR_MASK_REG_TIMER_EXPIRED_RECOV_ERROR = 4 ;
+static const uint8_t P9N2_CAPP_FIR_MASK_REG_TIMER_EXPIRED_XSTOP_ERROR = 5 ;
+static const uint8_t P9N2_CAPP_FIR_MASK_REG_PSL_CMD_UE = 6 ;
+static const uint8_t P9N2_CAPP_FIR_MASK_REG_PSL_CMD_SUE = 7 ;
+static const uint8_t P9N2_CAPP_FIR_MASK_REG_SNOOP_ARRAY_CE = 8 ;
+static const uint8_t P9N2_CAPP_FIR_MASK_REG_SNOOP_ARRAY_UE = 9 ;
+static const uint8_t P9N2_CAPP_FIR_MASK_REG_RECOVERY_FAILED = 10 ;
+static const uint8_t P9N2_CAPP_FIR_MASK_REG_ILLEGAL_LPC_BAR_ACCESS = 11 ;
+static const uint8_t P9N2_CAPP_FIR_MASK_REG_XPT_RECOVERABLE_ERROR = 12 ;
+static const uint8_t P9N2_CAPP_FIR_MASK_REG_MASTER_RECOVERABLE_ERROR = 13 ;
+static const uint8_t P9N2_CAPP_FIR_MASK_REG_SNOOPER_RECOVERABLE_ERROR = 14 ;
+static const uint8_t P9N2_CAPP_FIR_MASK_REG_SECURE_SCOM_ERROR = 15 ;
+static const uint8_t P9N2_CAPP_FIR_MASK_REG_MASTER_SYS_XSTOP_ERROR = 16 ;
+static const uint8_t P9N2_CAPP_FIR_MASK_REG_SNOOPER_SYS_XSTOP_ERROR = 17 ;
+static const uint8_t P9N2_CAPP_FIR_MASK_REG_XPT_SYS_XSTOP_ERROR = 18 ;
+static const uint8_t P9N2_CAPP_FIR_MASK_REG_MUOP_ERROR_1 = 19 ;
+static const uint8_t P9N2_CAPP_FIR_MASK_REG_MUOP_ERROR_2 = 20 ;
+static const uint8_t P9N2_CAPP_FIR_MASK_REG_MUOP_ERROR_3 = 21 ;
+static const uint8_t P9N2_CAPP_FIR_MASK_REG_SUOP_ERROR_1 = 22 ;
+static const uint8_t P9N2_CAPP_FIR_MASK_REG_SUOP_ERROR_2 = 23 ;
+static const uint8_t P9N2_CAPP_FIR_MASK_REG_SUOP_ERROR_3 = 24 ;
+static const uint8_t P9N2_CAPP_FIR_MASK_REG_POWERBUS_MISC_ERROR = 25 ;
+static const uint8_t P9N2_CAPP_FIR_MASK_REG_POWERBUS_INTERFACE_PE = 26 ;
+static const uint8_t P9N2_CAPP_FIR_MASK_REG_POWERBUS_DATA_HANG_ERROR = 27 ;
+static const uint8_t P9N2_CAPP_FIR_MASK_REG_POWERBUS_HANG_ERROR = 28 ;
+static const uint8_t P9N2_CAPP_FIR_MASK_REG_LD_CLASS_CMD_ADDR_ERR = 29 ;
+static const uint8_t P9N2_CAPP_FIR_MASK_REG_ST_CLASS_CMD_ADDR_ERR = 30 ;
+static const uint8_t P9N2_CAPP_FIR_MASK_REG_PHB_LINK_DOWN = 31 ;
+static const uint8_t P9N2_CAPP_FIR_MASK_REG_LD_CLASS_CMD_FOREIGN_LINK_FAIL = 32 ;
+static const uint8_t P9N2_CAPP_FIR_MASK_REG_FOREIGN_LINK_HANG_ERROR = 33 ;
+static const uint8_t P9N2_CAPP_FIR_MASK_REG_XPT_POWERBUS_CE = 34 ;
+static const uint8_t P9N2_CAPP_FIR_MASK_REG_XPT_POWERBUS_UE = 35 ;
+static const uint8_t P9N2_CAPP_FIR_MASK_REG_XPT_POWERBUS_SUE = 36 ;
+static const uint8_t P9N2_CAPP_FIR_MASK_REG_TLBI_TIMEOUT = 37 ;
+static const uint8_t P9N2_CAPP_FIR_MASK_REG_TLBI_SOT_ERR = 38 ;
+static const uint8_t P9N2_CAPP_FIR_MASK_REG_TLBI_BAD_OP_ERR = 39 ;
+static const uint8_t P9N2_CAPP_FIR_MASK_REG_TLBI_SEQ_NUM_PARITY_ERR = 40 ;
+static const uint8_t P9N2_CAPP_FIR_MASK_REG_ST_CLASS_CMD_FOREIGN_LINK_FAIL = 41 ;
+static const uint8_t P9N2_CAPP_FIR_MASK_REG_TIME_BASE_ERR = 42 ;
+static const uint8_t P9N2_CAPP_FIR_MASK_REG_TRANSPORT_INFORMATIONAL_ERR = 43 ;
+static const uint8_t P9N2_CAPP_FIR_MASK_REG_APC_ARRAY_CMD_CE_ERPT = 44 ;
+static const uint8_t P9N2_CAPP_FIR_MASK_REG_APC_ARRAY_CMD_UE_ERPT = 45 ;
+static const uint8_t P9N2_CAPP_FIR_MASK_REG_PSL_CREDIT_TIMEOUT_ERR = 46 ;
+static const uint8_t P9N2_CAPP_FIR_MASK_REG_SPARE_2 = 47 ;
+static const uint8_t P9N2_CAPP_FIR_MASK_REG_SPARE_3 = 48 ;
+static const uint8_t P9N2_CAPP_FIR_MASK_REG_HYPERVISOR = 49 ;
+static const uint8_t P9N2_CAPP_FIR_MASK_REG_SECURE_MEM_ACCESS = 50 ;
+static const uint8_t P9N2_CAPP_FIR_MASK_REG_SCOM_ERR2 = 51 ;
+static const uint8_t P9N2_CAPP_FIR_MASK_REG_SCOM_ERR = 52 ;
+
+static const uint8_t P9N2_PEC_FIR_MASK_REG_HSSCALERR = 0 ;
+static const uint8_t P9N2_PEC_FIR_MASK_REG_HSSPLLAERR = 1 ;
+static const uint8_t P9N2_PEC_FIR_MASK_REG_HSSPLLBERR = 2 ;
+static const uint8_t P9N2_PEC_FIR_MASK_REG_TXAERR = 3 ;
+static const uint8_t P9N2_PEC_FIR_MASK_REG_TXBERR = 4 ;
+static const uint8_t P9N2_PEC_FIR_MASK_REG_TXCERR = 5 ;
+static const uint8_t P9N2_PEC_FIR_MASK_REG_TXDERR = 6 ;
+static const uint8_t P9N2_PEC_FIR_MASK_REG_TXEERR = 7 ;
+static const uint8_t P9N2_PEC_FIR_MASK_REG_TXFERR = 8 ;
+static const uint8_t P9N2_PEC_FIR_MASK_REG_TXGERR = 9 ;
+static const uint8_t P9N2_PEC_FIR_MASK_REG_TXHERR = 10 ;
+static const uint8_t P9N2_PEC_FIR_MASK_REG_TXIERR = 11 ;
+static const uint8_t P9N2_PEC_FIR_MASK_REG_TXJERR = 12 ;
+static const uint8_t P9N2_PEC_FIR_MASK_REG_TXKERR = 13 ;
+static const uint8_t P9N2_PEC_FIR_MASK_REG_TXLERR = 14 ;
+static const uint8_t P9N2_PEC_FIR_MASK_REG_TXMERR = 15 ;
+static const uint8_t P9N2_PEC_FIR_MASK_REG_TXNERR = 16 ;
+static const uint8_t P9N2_PEC_FIR_MASK_REG_TXOERR = 17 ;
+static const uint8_t P9N2_PEC_FIR_MASK_REG_TXPERR = 18 ;
+static const uint8_t P9N2_PEC_FIR_MASK_REG_RXAERR = 19 ;
+static const uint8_t P9N2_PEC_FIR_MASK_REG_RXBERR = 20 ;
+static const uint8_t P9N2_PEC_FIR_MASK_REG_RXCERR = 21 ;
+static const uint8_t P9N2_PEC_FIR_MASK_REG_RXDERR = 22 ;
+static const uint8_t P9N2_PEC_FIR_MASK_REG_RXEERR = 23 ;
+static const uint8_t P9N2_PEC_FIR_MASK_REG_RXFERR = 24 ;
+static const uint8_t P9N2_PEC_FIR_MASK_REG_RXGERR = 25 ;
+static const uint8_t P9N2_PEC_FIR_MASK_REG_RXHERR = 26 ;
+static const uint8_t P9N2_PEC_FIR_MASK_REG_RXIERR = 27 ;
+static const uint8_t P9N2_PEC_FIR_MASK_REG_RXJERR = 28 ;
+static const uint8_t P9N2_PEC_FIR_MASK_REG_RXKERR = 29 ;
+static const uint8_t P9N2_PEC_FIR_MASK_REG_RXLERR = 30 ;
+static const uint8_t P9N2_PEC_FIR_MASK_REG_RXMERR = 31 ;
+static const uint8_t P9N2_PEC_FIR_MASK_REG_RXNERR = 32 ;
+static const uint8_t P9N2_PEC_FIR_MASK_REG_RXOERR = 33 ;
+static const uint8_t P9N2_PEC_FIR_MASK_REG_RXPERR = 34 ;
+static const uint8_t P9N2_PEC_FIR_MASK_REG_SCOM_PERR0 = 35 ;
+static const uint8_t P9N2_PEC_FIR_MASK_REG_SCOM_PERR1 = 36 ;
+
+static const uint8_t P9N2_PU_FIR_MASK_REG_PSI_RESERVED0 = 0 ;
+static const uint8_t P9N2_PU_FIR_MASK_REG_PSI_RESERVED1 = 1 ;
+static const uint8_t P9N2_PU_FIR_MASK_REG_PSI_RESERVED2 = 2 ;
+static const uint8_t P9N2_PU_FIR_MASK_REG_PSI_RESERVED3 = 3 ;
+static const uint8_t P9N2_PU_FIR_MASK_REG_PSI_RESERVED4 = 4 ;
+static const uint8_t P9N2_PU_FIR_MASK_REG_INTERNAL_SCOM_ERROR = 5 ;
+static const uint8_t P9N2_PU_FIR_MASK_REG_INTERNAL_SCOM_ERROR_CLONE = 6 ;
+
+static const uint8_t P9N2_PU_FIR_MASK_REGISTER_ECC_UNCORRECTED_ERR_PIB = 3 ;
+static const uint8_t P9N2_PU_FIR_MASK_REGISTER_BAD_ARRAY_ADDR_PIB = 5 ;
+static const uint8_t P9N2_PU_FIR_MASK_REGISTER_WRT_RST_INTRPT_PIB = 6 ;
+static const uint8_t P9N2_PU_FIR_MASK_REGISTER_RD_RST_INTRPT_PIB = 7 ;
+static const uint8_t P9N2_PU_FIR_MASK_REGISTER_ECC_UNCORRECTED_ERR_FACES = 22 ;
+static const uint8_t P9N2_PU_FIR_MASK_REGISTER_BAD_ARRAY_ADDR_FACES = 24 ;
+static const uint8_t P9N2_PU_FIR_MASK_REGISTER_WRT_RST_INTRPT_FACES = 25 ;
+static const uint8_t P9N2_PU_FIR_MASK_REGISTER_RD_RST_INTRPT_FACES = 26 ;
+
+static const uint8_t P9N2_PU_FIR_MASK_REG_0_0 = 0 ;
+static const uint8_t P9N2_PU_FIR_MASK_REG_0_0_LEN = 64 ;
+
+static const uint8_t P9N2_PU_FIR_MASK_REG_1_1 = 0 ;
+static const uint8_t P9N2_PU_FIR_MASK_REG_1_1_LEN = 64 ;
+
+static const uint8_t P9N2_PU_FIR_MASK_REG_2_2 = 0 ;
+static const uint8_t P9N2_PU_FIR_MASK_REG_2_2_LEN = 64 ;
+
+static const uint8_t P9N2_CAPP_FIR_REG_BAR_PE = 0 ;
+static const uint8_t P9N2_CAPP_FIR_REG_REGISTER_PE = 1 ;
+static const uint8_t P9N2_CAPP_FIR_REG_MASTER_ARRAY_CE = 2 ;
+static const uint8_t P9N2_CAPP_FIR_REG_MASTER_ARRAY_UE = 3 ;
+static const uint8_t P9N2_CAPP_FIR_REG_TIMER_EXPIRED_RECOV_ERROR = 4 ;
+static const uint8_t P9N2_CAPP_FIR_REG_TIMER_EXPIRED_XSTOP_ERROR = 5 ;
+static const uint8_t P9N2_CAPP_FIR_REG_PSL_CMD_UE = 6 ;
+static const uint8_t P9N2_CAPP_FIR_REG_PSL_CMD_SUE = 7 ;
+static const uint8_t P9N2_CAPP_FIR_REG_SNOOP_ARRAY_CE = 8 ;
+static const uint8_t P9N2_CAPP_FIR_REG_SNOOP_ARRAY_UE = 9 ;
+static const uint8_t P9N2_CAPP_FIR_REG_RECOVERY_FAILED = 10 ;
+static const uint8_t P9N2_CAPP_FIR_REG_ILLEGAL_LPC_BAR_ACCESS = 11 ;
+static const uint8_t P9N2_CAPP_FIR_REG_XPT_RECOVERABLE_ERROR = 12 ;
+static const uint8_t P9N2_CAPP_FIR_REG_MASTER_RECOVERABLE_ERROR = 13 ;
+static const uint8_t P9N2_CAPP_FIR_REG_SNOOPER_RECOVERABLE_ERROR = 14 ;
+static const uint8_t P9N2_CAPP_FIR_REG_SECURE_SCOM_ERROR = 15 ;
+static const uint8_t P9N2_CAPP_FIR_REG_MASTER_SYS_XSTOP_ERROR = 16 ;
+static const uint8_t P9N2_CAPP_FIR_REG_SNOOPER_SYS_XSTOP_ERROR = 17 ;
+static const uint8_t P9N2_CAPP_FIR_REG_XPT_SYS_XSTOP_ERROR = 18 ;
+static const uint8_t P9N2_CAPP_FIR_REG_MUOP_ERROR_1 = 19 ;
+static const uint8_t P9N2_CAPP_FIR_REG_MUOP_ERROR_2 = 20 ;
+static const uint8_t P9N2_CAPP_FIR_REG_MUOP_ERROR_3 = 21 ;
+static const uint8_t P9N2_CAPP_FIR_REG_SUOP_ERROR_1 = 22 ;
+static const uint8_t P9N2_CAPP_FIR_REG_SUOP_ERROR_2 = 23 ;
+static const uint8_t P9N2_CAPP_FIR_REG_SUOP_ERROR_3 = 24 ;
+static const uint8_t P9N2_CAPP_FIR_REG_POWERBUS_MISC_ERROR = 25 ;
+static const uint8_t P9N2_CAPP_FIR_REG_POWERBUS_INTERFACE_PE = 26 ;
+static const uint8_t P9N2_CAPP_FIR_REG_POWERBUS_DATA_HANG_ERROR = 27 ;
+static const uint8_t P9N2_CAPP_FIR_REG_POWERBUS_HANG_ERROR = 28 ;
+static const uint8_t P9N2_CAPP_FIR_REG_LD_CLASS_CMD_ADDR_ERR = 29 ;
+static const uint8_t P9N2_CAPP_FIR_REG_ST_CLASS_CMD_ADDR_ERR = 30 ;
+static const uint8_t P9N2_CAPP_FIR_REG_PHB_LINK_DOWN = 31 ;
+static const uint8_t P9N2_CAPP_FIR_REG_LD_CLASS_CMD_FOREIGN_LINK_FAIL = 32 ;
+static const uint8_t P9N2_CAPP_FIR_REG_FOREIGN_LINK_HANG_ERROR = 33 ;
+static const uint8_t P9N2_CAPP_FIR_REG_XPT_POWERBUS_CE = 34 ;
+static const uint8_t P9N2_CAPP_FIR_REG_XPT_POWERBUS_UE = 35 ;
+static const uint8_t P9N2_CAPP_FIR_REG_XPT_POWERBUS_SUE = 36 ;
+static const uint8_t P9N2_CAPP_FIR_REG_TLBI_TIMEOUT = 37 ;
+static const uint8_t P9N2_CAPP_FIR_REG_TLBI_SOT_ERR = 38 ;
+static const uint8_t P9N2_CAPP_FIR_REG_TLBI_BAD_OP_ERR = 39 ;
+static const uint8_t P9N2_CAPP_FIR_REG_TLBI_SEQ_NUM_PARITY_ERR = 40 ;
+static const uint8_t P9N2_CAPP_FIR_REG_ST_CLASS_CMD_FOREIGN_LINK_FAIL = 41 ;
+static const uint8_t P9N2_CAPP_FIR_REG_TIME_BASE_ERR = 42 ;
+static const uint8_t P9N2_CAPP_FIR_REG_TRANSPORT_INFORMATIONAL_ERR = 43 ;
+static const uint8_t P9N2_CAPP_FIR_REG_APC_ARRAY_CMD_CE_ERPT = 44 ;
+static const uint8_t P9N2_CAPP_FIR_REG_APC_ARRAY_CMD_UE_ERPT = 45 ;
+static const uint8_t P9N2_CAPP_FIR_REG_PSL_CREDIT_TIMEOUT_ERR = 46 ;
+static const uint8_t P9N2_CAPP_FIR_REG_SPARE_2 = 47 ;
+static const uint8_t P9N2_CAPP_FIR_REG_HYPERVISOR = 48 ;
+static const uint8_t P9N2_CAPP_FIR_REG_SPARE_3 = 49 ;
+static const uint8_t P9N2_CAPP_FIR_REG_SECURE_MEM_ACCESS = 50 ;
+static const uint8_t P9N2_CAPP_FIR_REG_SCOM_ERR2 = 51 ;
+static const uint8_t P9N2_CAPP_FIR_REG_SCOM_ERR = 52 ;
+
+static const uint8_t P9N2_PU_FIR_REG_PSI_RESERVED0 = 0 ;
+static const uint8_t P9N2_PU_FIR_REG_PSI_RESERVED1 = 1 ;
+static const uint8_t P9N2_PU_FIR_REG_PSI_RESERVED2 = 2 ;
+static const uint8_t P9N2_PU_FIR_REG_PSI_RESERVED3 = 3 ;
+static const uint8_t P9N2_PU_FIR_REG_PSI_RESERVED4 = 4 ;
+static const uint8_t P9N2_PU_FIR_REG_INTERNAL_SCOM_ERROR = 5 ;
+static const uint8_t P9N2_PU_FIR_REG_INTERNAL_SCOM_ERROR_CLONE = 6 ;
+
+static const uint8_t P9N2_PHB_FIR_REG_AIB_COMMAND_INVALID = 0 ;
+static const uint8_t P9N2_PHB_FIR_REG_AIB_ADDRESS_INVALID = 1 ;
+static const uint8_t P9N2_PHB_FIR_REG_AIB_ACCESS_ERROR = 2 ;
+static const uint8_t P9N2_PHB_FIR_REG_PAPR_OUTBOUND_INJECT_ERROR = 3 ;
+static const uint8_t P9N2_PHB_FIR_REG_AIB_FATAL_CLASS_ERROR = 4 ;
+static const uint8_t P9N2_PHB_FIR_REG_AIB_INF_CLASS_ERROR = 6 ;
+static const uint8_t P9N2_PHB_FIR_REG_PE_STOP_STATE_SIGNALED = 7 ;
+static const uint8_t P9N2_PHB_FIR_REG_OUT_COMMON_ARRAY_FATAL_ERROR = 8 ;
+static const uint8_t P9N2_PHB_FIR_REG_OUT_COMMON_LATCH_FATAL_ERROR = 9 ;
+static const uint8_t P9N2_PHB_FIR_REG_OUT_COMMON_LOGIC_FATAL_ERROR = 10 ;
+static const uint8_t P9N2_PHB_FIR_REG_BLIF_OUT_INTERFACE_PARITY_ERROR = 11 ;
+static const uint8_t P9N2_PHB_FIR_REG_CFG_WRITE_CA_OR_UR_RESPONSE = 12 ;
+static const uint8_t P9N2_PHB_FIR_REG_MMIO_REQUEST_TIMEOUT = 13 ;
+static const uint8_t P9N2_PHB_FIR_REG_OUT_RRB_SOURCED_ERROR = 14 ;
+static const uint8_t P9N2_PHB_FIR_REG_CFG_LOGIC_SIGNALED_ERROR = 15 ;
+static const uint8_t P9N2_PHB_FIR_REG_RSB_REQUEST_ADDRESS_ERROR = 16 ;
+static const uint8_t P9N2_PHB_FIR_REG_RSB_FDA_FATAL_ERROR = 17 ;
+static const uint8_t P9N2_PHB_FIR_REG_RSB_FDA_INF_ERROR = 18 ;
+static const uint8_t P9N2_PHB_FIR_REG_RSB_FDB_FATAL_ERROR = 19 ;
+static const uint8_t P9N2_PHB_FIR_REG_RSB_FDB_INF_ERROR = 20 ;
+static const uint8_t P9N2_PHB_FIR_REG_RSB_ERR_FATAL_ERROR = 21 ;
+static const uint8_t P9N2_PHB_FIR_REG_RSB_ERR_INF_ERROR = 22 ;
+static const uint8_t P9N2_PHB_FIR_REG_RSB_DBG_FATAL_ERROR = 23 ;
+static const uint8_t P9N2_PHB_FIR_REG_RSB_DBG_INF_ERROR = 24 ;
+static const uint8_t P9N2_PHB_FIR_REG_PCIE_REQUEST_ACCESS_ERROR = 25 ;
+static const uint8_t P9N2_PHB_FIR_REG_RSB_BUS_LOGIC_ERROR = 26 ;
+static const uint8_t P9N2_PHB_FIR_REG_RSB_UVI_FATAL_ERROR = 27 ;
+static const uint8_t P9N2_PHB_FIR_REG_RSB_UVI_INF_ERROR = 28 ;
+static const uint8_t P9N2_PHB_FIR_REG_SCOM_FATAL_ERROR = 29 ;
+static const uint8_t P9N2_PHB_FIR_REG_SCOM_INF_ERROR = 30 ;
+static const uint8_t P9N2_PHB_FIR_REG_PCIE_MACRO_ERROR_ACTIVE_STATUS = 31 ;
+static const uint8_t P9N2_PHB_FIR_REG_ARB_IODA_FATAL_ERROR = 32 ;
+static const uint8_t P9N2_PHB_FIR_REG_ARB_MSI_PE_MATCH_ERROR = 33 ;
+static const uint8_t P9N2_PHB_FIR_REG_ARB_MSI_ADDRESS_ERROR = 34 ;
+static const uint8_t P9N2_PHB_FIR_REG_ARB_TVT_ERROR = 35 ;
+static const uint8_t P9N2_PHB_FIR_REG_ARB_RCVD_FATAL_ERROR_MSG = 36 ;
+static const uint8_t P9N2_PHB_FIR_REG_ARB_RCVD_NONFATAL_ERROR_MSG = 37 ;
+static const uint8_t P9N2_PHB_FIR_REG_ARB_RCVD_CORRECTIBLE_ERROR_MSG = 38 ;
+static const uint8_t P9N2_PHB_FIR_REG_PAPR_INBOUND_INJECT_ERROR = 39 ;
+static const uint8_t P9N2_PHB_FIR_REG_ARB_COMMON_FATAL_ERROR = 40 ;
+static const uint8_t P9N2_PHB_FIR_REG_ARB_TABLE_BAR_DISABLED_ERROR = 41 ;
+static const uint8_t P9N2_PHB_FIR_REG_ARB_BLIF_COMPLETION_ERROR = 42 ;
+static const uint8_t P9N2_PHB_FIR_REG_ARB_PCT_TIMEOUT_ERROR = 43 ;
+static const uint8_t P9N2_PHB_FIR_REG_ARB_ECC_CORRECTABLE_ERROR = 44 ;
+static const uint8_t P9N2_PHB_FIR_REG_ARB_ECC_UNCORRECTABLE_ERROR = 45 ;
+static const uint8_t P9N2_PHB_FIR_REG_ARB_TLP_POISON_SIGNALED = 46 ;
+static const uint8_t P9N2_PHB_FIR_REG_ARB_RTT_PENUM_INVALID_ERROR = 47 ;
+static const uint8_t P9N2_PHB_FIR_REG_MRG_COMMON_FATAL_ERROR = 48 ;
+static const uint8_t P9N2_PHB_FIR_REG_MRG_TABLE_BAR_DISABLED_ERROR = 49 ;
+static const uint8_t P9N2_PHB_FIR_REG_MRG_ECC_CORRECTABLE_ERROR = 50 ;
+static const uint8_t P9N2_PHB_FIR_REG_MRG_ECC_UNCORRECTABLE_ERROR = 51 ;
+static const uint8_t P9N2_PHB_FIR_REG_MRG_AIB2_TX_TIMEOUT_ERROR = 52 ;
+static const uint8_t P9N2_PHB_FIR_REG_MRG_MRT_ERROR = 53 ;
+static const uint8_t P9N2_PHB_FIR_REG_MRG_RESERVED01 = 54 ;
+static const uint8_t P9N2_PHB_FIR_REG_MRG_RESERVED02 = 55 ;
+static const uint8_t P9N2_PHB_FIR_REG_TCE_IODA_PAGE_ACCESS_ERROR = 56 ;
+static const uint8_t P9N2_PHB_FIR_REG_TCE_REQUEST_TIMEOUT_ERROR = 57 ;
+static const uint8_t P9N2_PHB_FIR_REG_TCE_UNEXPECTED_RESPONSE_ERROR = 58 ;
+static const uint8_t P9N2_PHB_FIR_REG_TCE_COMMON_FATAL_ERROR = 59 ;
+static const uint8_t P9N2_PHB_FIR_REG_TCE_ECC_CORRECTABLE_ERROR = 60 ;
+static const uint8_t P9N2_PHB_FIR_REG_TCE_ECC_UNCORRECTABLE_ERROR = 61 ;
+static const uint8_t P9N2_PHB_FIR_REG_TCE_RESERVED01 = 62 ;
+static const uint8_t P9N2_PHB_FIR_REG_INTERNAL_PARITY_ERROR = 63 ;
+
+static const uint8_t P9N2_PU_FIR_REG_0_NTL_ARRAY_CE = 0 ;
+static const uint8_t P9N2_PU_FIR_REG_0_NTL_ARRAY_HDR_UE = 1 ;
+static const uint8_t P9N2_PU_FIR_REG_0_NTL_ARRAY_DATA_UE = 2 ;
+static const uint8_t P9N2_PU_FIR_REG_0_NTL_NVL_FLIT_PERR = 3 ;
+static const uint8_t P9N2_PU_FIR_REG_0_NTL_NVL_DATA_PERR = 4 ;
+static const uint8_t P9N2_PU_FIR_REG_0_NTL_NVL_PKT_MALFOR = 5 ;
+static const uint8_t P9N2_PU_FIR_REG_0_NTL_NVL_PKT_UNSUPPORTED = 6 ;
+static const uint8_t P9N2_PU_FIR_REG_0_NTL_NVL_CONFIG_ERR = 7 ;
+static const uint8_t P9N2_PU_FIR_REG_0_NTL_NVL_CRC_ERR = 8 ;
+static const uint8_t P9N2_PU_FIR_REG_0_NTL_PRI_ERR = 9 ;
+static const uint8_t P9N2_PU_FIR_REG_0_NTL_LOGIC_ERR = 10 ;
+static const uint8_t P9N2_PU_FIR_REG_0_NTL_LMD_POISON = 11 ;
+static const uint8_t P9N2_PU_FIR_REG_0_NTL_ARRAY_DATA_SUE = 12 ;
+static const uint8_t P9N2_PU_FIR_REG_0_CTL_ARRAY_CE = 13 ;
+static const uint8_t P9N2_PU_FIR_REG_0_CTL_PBUS_RECOV_ERR = 14 ;
+static const uint8_t P9N2_PU_FIR_REG_0_CTL_RING_ERR = 15 ;
+static const uint8_t P9N2_PU_FIR_REG_0_CTL_MMIO_ST_DATA_UE = 16 ;
+static const uint8_t P9N2_PU_FIR_REG_0_CTL_PEF = 17 ;
+static const uint8_t P9N2_PU_FIR_REG_0_CTL_NVL_CFG_ERR = 18 ;
+static const uint8_t P9N2_PU_FIR_REG_0_CTL_NVL_FATAL_ERR = 19 ;
+static const uint8_t P9N2_PU_FIR_REG_0_RESERVED_1 = 20 ;
+static const uint8_t P9N2_PU_FIR_REG_0_CTL_ARRAY_UE = 21 ;
+static const uint8_t P9N2_PU_FIR_REG_0_CTL_PBUS_PERR = 22 ;
+static const uint8_t P9N2_PU_FIR_REG_0_CTL_PBUS_FATAL_ERR = 23 ;
+static const uint8_t P9N2_PU_FIR_REG_0_CTL_PBUS_CONFIG_ERR = 24 ;
+static const uint8_t P9N2_PU_FIR_REG_0_CTL_FWD_PROGRESS_ERR = 25 ;
+static const uint8_t P9N2_PU_FIR_REG_0_CTL_LOGIC_ERR = 26 ;
+static const uint8_t P9N2_PU_FIR_REG_0_CTL_RSVD_14 = 27 ;
+static const uint8_t P9N2_PU_FIR_REG_0_CTL_RSVD_15 = 28 ;
+static const uint8_t P9N2_PU_FIR_REG_0_DAT_DATA_BE_UE = 29 ;
+static const uint8_t P9N2_PU_FIR_REG_0_DAT_DATA_BE_CE = 30 ;
+static const uint8_t P9N2_PU_FIR_REG_0_DAT_DATA_BE_PERR = 31 ;
+static const uint8_t P9N2_PU_FIR_REG_0_DAT_CREG_PERR = 32 ;
+static const uint8_t P9N2_PU_FIR_REG_0_DAT_RTAG_PERR = 33 ;
+static const uint8_t P9N2_PU_FIR_REG_0_DAT_STATE_PERR = 34 ;
+static const uint8_t P9N2_PU_FIR_REG_0_DAT_LOGIC_ERR = 35 ;
+static const uint8_t P9N2_PU_FIR_REG_0_DAT_DATA_BE_SUE = 36 ;
+static const uint8_t P9N2_PU_FIR_REG_0_DAT_PBRX_SUE = 37 ;
+static const uint8_t P9N2_PU_FIR_REG_0_DAT_RSVD_9 = 38 ;
+static const uint8_t P9N2_PU_FIR_REG_0_DAT_RSVD_10 = 39 ;
+static const uint8_t P9N2_PU_FIR_REG_0_XTS_INT = 40 ;
+static const uint8_t P9N2_PU_FIR_REG_0_XTS_SRAM_CE = 41 ;
+static const uint8_t P9N2_PU_FIR_REG_0_XTS_SRAM_UE = 42 ;
+static const uint8_t P9N2_PU_FIR_REG_0_XTS_PROTOCOL_CE = 43 ;
+static const uint8_t P9N2_PU_FIR_REG_0_XTS_PROTOCOL_UE = 44 ;
+static const uint8_t P9N2_PU_FIR_REG_0_XTS_PBUS_PROTOCOL = 45 ;
+static const uint8_t P9N2_PU_FIR_REG_0_XTS_RSVD_6 = 46 ;
+static const uint8_t P9N2_PU_FIR_REG_0_XTS_RSVD_7 = 47 ;
+static const uint8_t P9N2_PU_FIR_REG_0_XTS_RSVD_8 = 48 ;
+static const uint8_t P9N2_PU_FIR_REG_0_XTS_RSVD_9 = 49 ;
+static const uint8_t P9N2_PU_FIR_REG_0_XTS_RSVD_10 = 50 ;
+static const uint8_t P9N2_PU_FIR_REG_0_XTS_RSVD_11 = 51 ;
+static const uint8_t P9N2_PU_FIR_REG_0_XTS_RSVD_12 = 52 ;
+static const uint8_t P9N2_PU_FIR_REG_0_XTS_RSVD_13 = 53 ;
+static const uint8_t P9N2_PU_FIR_REG_0_XTS_RSVD_14 = 54 ;
+static const uint8_t P9N2_PU_FIR_REG_0_XTS_RSVD_15 = 55 ;
+static const uint8_t P9N2_PU_FIR_REG_0_XTS_RSVD_16 = 56 ;
+static const uint8_t P9N2_PU_FIR_REG_0_XTS_RSVD_17 = 57 ;
+static const uint8_t P9N2_PU_FIR_REG_0_XTS_RSVD_18 = 58 ;
+static const uint8_t P9N2_PU_FIR_REG_0_XTS_RSVD_19 = 59 ;
+static const uint8_t P9N2_PU_FIR_REG_0_FIR0_RSVD_60 = 60 ;
+static const uint8_t P9N2_PU_FIR_REG_0_FIR0_RSVD_61 = 61 ;
+static const uint8_t P9N2_PU_FIR_REG_0_PARITY_ERR2 = 62 ;
+static const uint8_t P9N2_PU_FIR_REG_0_PARITY_ERR = 63 ;
+
+static const uint8_t P9N2_PU_FIR_REG_1_NDL_BRK0_STALL = 0 ;
+static const uint8_t P9N2_PU_FIR_REG_1_NDL_BRK0_NOSTALL = 1 ;
+static const uint8_t P9N2_PU_FIR_REG_1_NDL_BRK1_STALL = 2 ;
+static const uint8_t P9N2_PU_FIR_REG_1_NDL_BRK1_NOSTALL = 3 ;
+static const uint8_t P9N2_PU_FIR_REG_1_NDL_BRK2_STALL = 4 ;
+static const uint8_t P9N2_PU_FIR_REG_1_NDL_BRK2_NOSTALL = 5 ;
+static const uint8_t P9N2_PU_FIR_REG_1_NDL_BRK3_STALL = 6 ;
+static const uint8_t P9N2_PU_FIR_REG_1_NDL_BRK3_NOSTALL = 7 ;
+static const uint8_t P9N2_PU_FIR_REG_1_NDL_BRK4_STALL = 8 ;
+static const uint8_t P9N2_PU_FIR_REG_1_NDL_BRK4_NOSTALL = 9 ;
+static const uint8_t P9N2_PU_FIR_REG_1_NDL_BRK5_STALL = 10 ;
+static const uint8_t P9N2_PU_FIR_REG_1_NDL_BRK5_NOSTALL = 11 ;
+static const uint8_t P9N2_PU_FIR_REG_1_MISC_RING_ERR = 12 ;
+static const uint8_t P9N2_PU_FIR_REG_1_MISC_INT_RA_PERR = 13 ;
+static const uint8_t P9N2_PU_FIR_REG_1_MISC_DA_ADDR_PERR = 14 ;
+static const uint8_t P9N2_PU_FIR_REG_1_MISC_CTRL_PERR = 15 ;
+static const uint8_t P9N2_PU_FIR_REG_1_MISC_NMMU_ERR = 16 ;
+static const uint8_t P9N2_PU_FIR_REG_1_ATS_TVT_ENTRY_INVALID = 17 ;
+static const uint8_t P9N2_PU_FIR_REG_1_ATS_TVT_ADDR_RANGE_ERR = 18 ;
+static const uint8_t P9N2_PU_FIR_REG_1_ATS_TCE_PAGE_ACCESS_CA_ERR = 19 ;
+static const uint8_t P9N2_PU_FIR_REG_1_ATS_TCE_CACHE_MULT_HIT_ERR = 20 ;
+static const uint8_t P9N2_PU_FIR_REG_1_ATS_TCE_PAGE_ACCESS_TW_ERR = 21 ;
+static const uint8_t P9N2_PU_FIR_REG_1_ATS_TCE_REQ_TO_ERR = 22 ;
+static const uint8_t P9N2_PU_FIR_REG_1_ATS_TCD_PERR = 23 ;
+static const uint8_t P9N2_PU_FIR_REG_1_ATS_TDR_PERR = 24 ;
+static const uint8_t P9N2_PU_FIR_REG_1_ATS_AT_EA_UE = 25 ;
+static const uint8_t P9N2_PU_FIR_REG_1_ATS_AT_EA_CE = 26 ;
+static const uint8_t P9N2_PU_FIR_REG_1_ATS_AT_TDRMEM_UE = 27 ;
+static const uint8_t P9N2_PU_FIR_REG_1_ATS_AT_TDRMEM_CE = 28 ;
+static const uint8_t P9N2_PU_FIR_REG_1_ATS_AT_RSPOUT_UE = 29 ;
+static const uint8_t P9N2_PU_FIR_REG_1_ATS_AT_RSPOUT_CE = 30 ;
+static const uint8_t P9N2_PU_FIR_REG_1_ATS_TVT_PERR = 31 ;
+static const uint8_t P9N2_PU_FIR_REG_1_ATS_IODA_ADDR_PERR = 32 ;
+static const uint8_t P9N2_PU_FIR_REG_1_ATS_NPU_CTRL_PERR = 33 ;
+static const uint8_t P9N2_PU_FIR_REG_1_ATS_NPU_TOR_PERR = 34 ;
+static const uint8_t P9N2_PU_FIR_REG_1_ATS_INVAL_IODA_TBL_SEL = 35 ;
+static const uint8_t P9N2_PU_FIR_REG_1_ATS_RSVD_19 = 36 ;
+static const uint8_t P9N2_PU_FIR_REG_1_FIR1_RSVD_37 = 37 ;
+static const uint8_t P9N2_PU_FIR_REG_1_FIR1_RSVD_38 = 38 ;
+static const uint8_t P9N2_PU_FIR_REG_1_FIR1_RSVD_39 = 39 ;
+static const uint8_t P9N2_PU_FIR_REG_1_FIR1_RSVD_40 = 40 ;
+static const uint8_t P9N2_PU_FIR_REG_1_FIR1_RSVD_41 = 41 ;
+static const uint8_t P9N2_PU_FIR_REG_1_FIR1_RSVD_42 = 42 ;
+static const uint8_t P9N2_PU_FIR_REG_1_FIR1_RSVD_43 = 43 ;
+static const uint8_t P9N2_PU_FIR_REG_1_FIR1_RSVD_44 = 44 ;
+static const uint8_t P9N2_PU_FIR_REG_1_FIR1_RSVD_45 = 45 ;
+static const uint8_t P9N2_PU_FIR_REG_1_FIR1_RSVD_46 = 46 ;
+static const uint8_t P9N2_PU_FIR_REG_1_FIR1_RSVD_47 = 47 ;
+static const uint8_t P9N2_PU_FIR_REG_1_FIR1_RSVD_48 = 48 ;
+static const uint8_t P9N2_PU_FIR_REG_1_FIR1_RSVD_49 = 49 ;
+static const uint8_t P9N2_PU_FIR_REG_1_FIR1_RSVD_50 = 50 ;
+static const uint8_t P9N2_PU_FIR_REG_1_FIR1_RSVD_51 = 51 ;
+static const uint8_t P9N2_PU_FIR_REG_1_FIR1_RSVD_52 = 52 ;
+static const uint8_t P9N2_PU_FIR_REG_1_FIR1_RSVD_53 = 53 ;
+static const uint8_t P9N2_PU_FIR_REG_1_FIR1_RSVD_54 = 54 ;
+static const uint8_t P9N2_PU_FIR_REG_1_FIR1_RSVD_55 = 55 ;
+static const uint8_t P9N2_PU_FIR_REG_1_FIR1_RSVD_56 = 56 ;
+static const uint8_t P9N2_PU_FIR_REG_1_FIR1_RSVD_57 = 57 ;
+static const uint8_t P9N2_PU_FIR_REG_1_FIR1_RSVD_58 = 58 ;
+static const uint8_t P9N2_PU_FIR_REG_1_FIR1_RSVD_59 = 59 ;
+static const uint8_t P9N2_PU_FIR_REG_1_SCOMSAT00_ERR = 60 ;
+static const uint8_t P9N2_PU_FIR_REG_1_SCOMSAT01_ERR = 61 ;
+static const uint8_t P9N2_PU_FIR_REG_1_PARITY_ERR2 = 62 ;
+static const uint8_t P9N2_PU_FIR_REG_1_PARITY_ERR = 63 ;
+
+static const uint8_t P9N2_PU_FIR_REG_2_OTL_BRK2_XLAT_FAULT = 0 ;
+static const uint8_t P9N2_PU_FIR_REG_2_OTL_BRK3_XLAT_FAULT = 1 ;
+static const uint8_t P9N2_PU_FIR_REG_2_OTL_BRK4_XLAT_FAULT = 2 ;
+static const uint8_t P9N2_PU_FIR_REG_2_OTL_BRK5_XLAT_FAULT = 3 ;
+static const uint8_t P9N2_PU_FIR_REG_2_OTL_TL_CRD_OVF = 4 ;
+static const uint8_t P9N2_PU_FIR_REG_2_OTL_RXI_ACTAG_IDX = 5 ;
+static const uint8_t P9N2_PU_FIR_REG_2_OTL_RXI_ACTAG_INV = 6 ;
+static const uint8_t P9N2_PU_FIR_REG_2_OTL_RXI_OPC_RSVD = 7 ;
+static const uint8_t P9N2_PU_FIR_REG_2_OTL_RXI_RTC_POS = 8 ;
+static const uint8_t P9N2_PU_FIR_REG_2_OTL_RXI_TMPL = 9 ;
+static const uint8_t P9N2_PU_FIR_REG_2_OTL_RXI_TMPL_UNS = 10 ;
+static const uint8_t P9N2_PU_FIR_REG_2_OTL_RXI_TMPL_X00 = 11 ;
+static const uint8_t P9N2_PU_FIR_REG_2_OTL_RXI_CTLFLIT_OVERRUN = 12 ;
+static const uint8_t P9N2_PU_FIR_REG_2_OTL_RXI_UNEXPECTED_DATA_FLIT = 13 ;
+static const uint8_t P9N2_PU_FIR_REG_2_OTL_RXI_LINK_DOWN = 14 ;
+static const uint8_t P9N2_PU_FIR_REG_2_OTL_RXI_BAD_DATA_RECEIVED_CMD = 15 ;
+static const uint8_t P9N2_PU_FIR_REG_2_OTL_RXI_BAD_DATA_RECEIVED_RESP_RXI_BAD_DATA_RECEIVED_RESP = 16 ;
+static const uint8_t P9N2_PU_FIR_REG_2_OTL_RXI_RESPONSE_NOT_ALLOWED = 17 ;
+static const uint8_t P9N2_PU_FIR_REG_2_OTL_PERR = 18 ;
+static const uint8_t P9N2_PU_FIR_REG_2_OTL_CE = 19 ;
+static const uint8_t P9N2_PU_FIR_REG_2_OTL_UE = 20 ;
+static const uint8_t P9N2_PU_FIR_REG_2_OTL_RXO_OP_ERRORS = 21 ;
+static const uint8_t P9N2_PU_FIR_REG_2_OTL_RXO_INTERNAL_ERRORS = 22 ;
+static const uint8_t P9N2_PU_FIR_REG_2_OTL_RXI_FIFO_OVERRUN = 23 ;
+static const uint8_t P9N2_PU_FIR_REG_2_OTL_RXI_CNTL_FLIT_DATA_RUN_LENGTH_INV = 24 ;
+static const uint8_t P9N2_PU_FIR_REG_2_OTL_RXI_OPCODE_UTIL_DL_EQ_ZERO = 25 ;
+static const uint8_t P9N2_PU_FIR_REG_2_OTL_RSVD_22 = 26 ;
+static const uint8_t P9N2_PU_FIR_REG_2_OTL_RSVD_23 = 27 ;
+static const uint8_t P9N2_PU_FIR_REG_2_OTL_RSVD_24 = 28 ;
+static const uint8_t P9N2_PU_FIR_REG_2_OTL_RSVD_25 = 29 ;
+static const uint8_t P9N2_PU_FIR_REG_2_OTL_RSVD_26 = 30 ;
+static const uint8_t P9N2_PU_FIR_REG_2_OTL_RSVD_27 = 31 ;
+static const uint8_t P9N2_PU_FIR_REG_2_OTL_RSVD_28 = 32 ;
+static const uint8_t P9N2_PU_FIR_REG_2_OTL_RSVD_29 = 33 ;
+static const uint8_t P9N2_PU_FIR_REG_2_OTL_RSVD_30 = 34 ;
+static const uint8_t P9N2_PU_FIR_REG_2_OTL_RSVD_31 = 35 ;
+static const uint8_t P9N2_PU_FIR_REG_2_XSL_MMIO_INVALIDATE_REQ_WHILE_1_INPROG = 36 ;
+static const uint8_t P9N2_PU_FIR_REG_2_XSL_UNEXPECTED_ITAG_PORT_0 = 37 ;
+static const uint8_t P9N2_PU_FIR_REG_2_XSL_UNEXPECTED_ITAG_PORT_1 = 38 ;
+static const uint8_t P9N2_PU_FIR_REG_2_XSL_UNEXPECTED_RD_PEE_COMPLETION = 39 ;
+static const uint8_t P9N2_PU_FIR_REG_2_XSL_UNEXPECTED_CO_RESP = 40 ;
+static const uint8_t P9N2_PU_FIR_REG_2_XSL_XLAT_REQ_WHILE_SPAP_INVALID = 41 ;
+static const uint8_t P9N2_PU_FIR_REG_2_XSL_INVALID_PEE = 42 ;
+static const uint8_t P9N2_PU_FIR_REG_2_XSL_BLOOM_FILTER_PROTECT_ERR = 43 ;
+static const uint8_t P9N2_PU_FIR_REG_2_XSL_RSVD_8 = 44 ;
+static const uint8_t P9N2_PU_FIR_REG_2_XSL_RSVD_9 = 45 ;
+static const uint8_t P9N2_PU_FIR_REG_2_XSL_CE = 46 ;
+static const uint8_t P9N2_PU_FIR_REG_2_XSL_UE = 47 ;
+static const uint8_t P9N2_PU_FIR_REG_2_XSL_SLBI_TLBI_BUFF_OVERFLOW = 48 ;
+static const uint8_t P9N2_PU_FIR_REG_2_XSL_SBE_CORR_ERR_PB_CHKOUT_RSP_DATA = 49 ;
+static const uint8_t P9N2_PU_FIR_REG_2_XSL_UE_PB_CHKOUT_RSP_DATA = 50 ;
+static const uint8_t P9N2_PU_FIR_REG_2_XSL_SUE_PB_CHKOUT_RSP_DATA = 51 ;
+static const uint8_t P9N2_PU_FIR_REG_2_XSL_RSVD_16 = 52 ;
+static const uint8_t P9N2_PU_FIR_REG_2_XSL_RSVD_17 = 53 ;
+static const uint8_t P9N2_PU_FIR_REG_2_FIR2_RSVD_54 = 54 ;
+static const uint8_t P9N2_PU_FIR_REG_2_FIR2_RSVD_55 = 55 ;
+static const uint8_t P9N2_PU_FIR_REG_2_FIR2_RSVD_56 = 56 ;
+static const uint8_t P9N2_PU_FIR_REG_2_FIR2_RSVD_57 = 57 ;
+static const uint8_t P9N2_PU_FIR_REG_2_FIR2_RSVD_58 = 58 ;
+static const uint8_t P9N2_PU_FIR_REG_2_FIR2_RSVD_59 = 59 ;
+static const uint8_t P9N2_PU_FIR_REG_2_SCOMSAT10_ERR = 60 ;
+static const uint8_t P9N2_PU_FIR_REG_2_SCOMSAT11_ERR = 61 ;
+static const uint8_t P9N2_PU_FIR_REG_2_PARITY_ERR2 = 62 ;
+static const uint8_t P9N2_PU_FIR_REG_2_PARITY_ERR = 63 ;
+
+static const uint8_t P9N2_PEC_FIR_STATUS_REG_HSSCALERR = 0 ;
+static const uint8_t P9N2_PEC_FIR_STATUS_REG_HSSPLLAERR = 1 ;
+static const uint8_t P9N2_PEC_FIR_STATUS_REG_HSSPLLBERR = 2 ;
+static const uint8_t P9N2_PEC_FIR_STATUS_REG_TXAERR = 3 ;
+static const uint8_t P9N2_PEC_FIR_STATUS_REG_TXBERR = 4 ;
+static const uint8_t P9N2_PEC_FIR_STATUS_REG_TXCERR = 5 ;
+static const uint8_t P9N2_PEC_FIR_STATUS_REG_TXDERR = 6 ;
+static const uint8_t P9N2_PEC_FIR_STATUS_REG_TXEERR = 7 ;
+static const uint8_t P9N2_PEC_FIR_STATUS_REG_TXFERR = 8 ;
+static const uint8_t P9N2_PEC_FIR_STATUS_REG_TXGERR = 9 ;
+static const uint8_t P9N2_PEC_FIR_STATUS_REG_TXHERR = 10 ;
+static const uint8_t P9N2_PEC_FIR_STATUS_REG_TXIERR = 11 ;
+static const uint8_t P9N2_PEC_FIR_STATUS_REG_TXJERR = 12 ;
+static const uint8_t P9N2_PEC_FIR_STATUS_REG_TXKERR = 13 ;
+static const uint8_t P9N2_PEC_FIR_STATUS_REG_TXLERR = 14 ;
+static const uint8_t P9N2_PEC_FIR_STATUS_REG_TXMERR = 15 ;
+static const uint8_t P9N2_PEC_FIR_STATUS_REG_TXNERR = 16 ;
+static const uint8_t P9N2_PEC_FIR_STATUS_REG_TXOERR = 17 ;
+static const uint8_t P9N2_PEC_FIR_STATUS_REG_TXPERR = 18 ;
+static const uint8_t P9N2_PEC_FIR_STATUS_REG_RXAERR = 19 ;
+static const uint8_t P9N2_PEC_FIR_STATUS_REG_RXBERR = 20 ;
+static const uint8_t P9N2_PEC_FIR_STATUS_REG_RXCERR = 21 ;
+static const uint8_t P9N2_PEC_FIR_STATUS_REG_RXDERR = 22 ;
+static const uint8_t P9N2_PEC_FIR_STATUS_REG_RXEERR = 23 ;
+static const uint8_t P9N2_PEC_FIR_STATUS_REG_RXFERR = 24 ;
+static const uint8_t P9N2_PEC_FIR_STATUS_REG_RXGERR = 25 ;
+static const uint8_t P9N2_PEC_FIR_STATUS_REG_RXHERR = 26 ;
+static const uint8_t P9N2_PEC_FIR_STATUS_REG_RXIERR = 27 ;
+static const uint8_t P9N2_PEC_FIR_STATUS_REG_RXJERR = 28 ;
+static const uint8_t P9N2_PEC_FIR_STATUS_REG_RXKERR = 29 ;
+static const uint8_t P9N2_PEC_FIR_STATUS_REG_RXLERR = 30 ;
+static const uint8_t P9N2_PEC_FIR_STATUS_REG_RXMERR = 31 ;
+static const uint8_t P9N2_PEC_FIR_STATUS_REG_RXNERR = 32 ;
+static const uint8_t P9N2_PEC_FIR_STATUS_REG_RXOERR = 33 ;
+static const uint8_t P9N2_PEC_FIR_STATUS_REG_RXPERR = 34 ;
+static const uint8_t P9N2_PEC_FIR_STATUS_REG_SCOM_PERR0 = 35 ;
+static const uint8_t P9N2_PEC_FIR_STATUS_REG_SCOM_PERR1 = 36 ;
+
+static const uint8_t P9N2_PEC_FIR_WOF_REG_WOF = 0 ;
+static const uint8_t P9N2_PEC_FIR_WOF_REG_WOF_LEN = 37 ;
+
+static const uint8_t P9N2_PU_FIR_WOF_REG_WOF = 0 ;
+static const uint8_t P9N2_PU_FIR_WOF_REG_WOF_LEN = 7 ;
+
+static const uint8_t P9N2_CAPP_FLUSHCPIG_FLUSH_CP_IG_STATE_MAP = 0 ;
+static const uint8_t P9N2_CAPP_FLUSHCPIG_FLUSH_CP_IG_STATE_MAP_LEN = 32 ;
+
+static const uint8_t P9N2_CAPP_FLUSHSHUE_FLUSH_SUE_STATE_MAP = 0 ;
+static const uint8_t P9N2_CAPP_FLUSHSHUE_FLUSH_SUE_STATE_MAP_LEN = 32 ;
+
+static const uint8_t P9N2_PU_FORCE_ECC_REG_ALTD_DATA_ITAG = 0 ;
+static const uint8_t P9N2_PU_FORCE_ECC_REG_ALTD_DATA_TX = 1 ;
+static const uint8_t P9N2_PU_FORCE_ECC_REG_ALTD_DATA_TX_LEN = 16 ;
+static const uint8_t P9N2_PU_FORCE_ECC_REG_ALTD_DATA_TX_OVERWRITE = 17 ;
+
+static const uint8_t P9N2__CTL_FREEZE_0_CONFIG_0 = 0 ;
+static const uint8_t P9N2__CTL_FREEZE_0_CONFIG_0_LEN = 64 ;
+
+static const uint8_t P9N2__CTL_FREEZE_1_CONFIG_1 = 0 ;
+static const uint8_t P9N2__CTL_FREEZE_1_CONFIG_1_LEN = 64 ;
+
+static const uint8_t P9N2__CTL_FREEZE_STATE_BDF2PE_00 = 0 ;
+static const uint8_t P9N2__CTL_FREEZE_STATE_BDF2PE_01 = 1 ;
+static const uint8_t P9N2__CTL_FREEZE_STATE_BDF2PE_02 = 2 ;
+static const uint8_t P9N2__CTL_FREEZE_STATE_BDF2PE_10 = 3 ;
+static const uint8_t P9N2__CTL_FREEZE_STATE_BDF2PE_11 = 4 ;
+static const uint8_t P9N2__CTL_FREEZE_STATE_BDF2PE_12 = 5 ;
+static const uint8_t P9N2__CTL_FREEZE_STATE_BDF2PE_20 = 6 ;
+static const uint8_t P9N2__CTL_FREEZE_STATE_BDF2PE_21 = 7 ;
+static const uint8_t P9N2__CTL_FREEZE_STATE_BDF2PE_22 = 8 ;
+static const uint8_t P9N2__CTL_FREEZE_STATE_BDF2PE_30 = 9 ;
+static const uint8_t P9N2__CTL_FREEZE_STATE_BDF2PE_31 = 10 ;
+static const uint8_t P9N2__CTL_FREEZE_STATE_BDF2PE_32 = 11 ;
+static const uint8_t P9N2__CTL_FREEZE_STATE_BDF2PE_40 = 12 ;
+static const uint8_t P9N2__CTL_FREEZE_STATE_BDF2PE_41 = 13 ;
+static const uint8_t P9N2__CTL_FREEZE_STATE_BDF2PE_42 = 14 ;
+static const uint8_t P9N2__CTL_FREEZE_STATE_BDF2PE_50 = 15 ;
+static const uint8_t P9N2__CTL_FREEZE_STATE_BDF2PE_51 = 16 ;
+static const uint8_t P9N2__CTL_FREEZE_STATE_BDF2PE_52 = 17 ;
+
+static const uint8_t P9N2_PU_FSB_DOWNFIFO_DATA_IN_DNFIFO_DATA_IN_PORT = 0 ;
+static const uint8_t P9N2_PU_FSB_DOWNFIFO_DATA_IN_DNFIFO_DATA_IN_PORT_LEN = 32 ;
+
+static const uint8_t P9N2_PU_FSB_DOWNFIFO_MTC_DNFIFO_MCT = 0 ;
+static const uint8_t P9N2_PU_FSB_DOWNFIFO_MTC_DNFIFO_MCT_LEN = 32 ;
+
+static const uint8_t P9N2_PU_FSB_DOWNFIFO_REQ_RESET_DNFIFO_REQ_RESET = 0 ;
+
+static const uint8_t P9N2_PU_FSB_DOWNFIFO_SIG_EOT_DNFIFO_SIGNAL = 0 ;
+
+static const uint8_t P9N2_PU_FSB_DOWNFIFO_STATUS_DNFIFO_REQ_RESET_FR_SBE = 6 ;
+static const uint8_t P9N2_PU_FSB_DOWNFIFO_STATUS_DNFIFO_REQ_RESET_FR_SP = 7 ;
+static const uint8_t P9N2_PU_FSB_DOWNFIFO_STATUS_DNFIFO_DEQUEUED_EOT_FLAG = 8 ;
+static const uint8_t P9N2_PU_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_FULL = 10 ;
+static const uint8_t P9N2_PU_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_EMPTY = 11 ;
+static const uint8_t P9N2_PU_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_ENTRY_COUNT = 12 ;
+static const uint8_t P9N2_PU_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_ENTRY_COUNT_LEN = 4 ;
+static const uint8_t P9N2_PU_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_VALID_FLAGS = 16 ;
+static const uint8_t P9N2_PU_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_VALID_FLAGS_LEN = 8 ;
+static const uint8_t P9N2_PU_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_EOT_FLAGS = 24 ;
+static const uint8_t P9N2_PU_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_EOT_FLAGS_LEN = 8 ;
+
+static const uint8_t P9N2_PU_FSB_UPFIFO_ACK_EOT_UPFIFO_ACK = 0 ;
+
+static const uint8_t P9N2_PU_FSB_UPFIFO_DATA_OUT_UPFIFO_DATA_OUT_PORT = 0 ;
+static const uint8_t P9N2_PU_FSB_UPFIFO_DATA_OUT_UPFIFO_DATA_OUT_PORT_LEN = 32 ;
+
+static const uint8_t P9N2_PU_FSB_UPFIFO_RESET_UPFIFO_RESET = 0 ;
+
+static const uint8_t P9N2_PU_FSB_UPFIFO_STATUS_REQ_RESET_FR_SP = 6 ;
+static const uint8_t P9N2_PU_FSB_UPFIFO_STATUS_REQ_RESET_FR_SBE = 7 ;
+static const uint8_t P9N2_PU_FSB_UPFIFO_STATUS_DEQUEUED_EOT_FLAG = 8 ;
+static const uint8_t P9N2_PU_FSB_UPFIFO_STATUS_FIFO_FULL = 10 ;
+static const uint8_t P9N2_PU_FSB_UPFIFO_STATUS_FIFO_EMPTY = 11 ;
+static const uint8_t P9N2_PU_FSB_UPFIFO_STATUS_FIFO_ENTRY_COUNT = 12 ;
+static const uint8_t P9N2_PU_FSB_UPFIFO_STATUS_FIFO_ENTRY_COUNT_LEN = 4 ;
+static const uint8_t P9N2_PU_FSB_UPFIFO_STATUS_FIFO_VALID_FLAGS = 16 ;
+static const uint8_t P9N2_PU_FSB_UPFIFO_STATUS_FIFO_VALID_FLAGS_LEN = 8 ;
+static const uint8_t P9N2_PU_FSB_UPFIFO_STATUS_FIFO_EOT_FLAGS = 24 ;
+static const uint8_t P9N2_PU_FSB_UPFIFO_STATUS_FIFO_EOT_FLAGS_LEN = 8 ;
+
+static const uint8_t P9N2_PU_NPU0_SM0_GENID_BAR_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM0_GENID_BAR_RESERVED1 = 1 ;
+static const uint8_t P9N2_PU_NPU0_SM0_GENID_BAR_RESERVED1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM0_GENID_BAR_CONFIG_GROUP = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM0_GENID_BAR_CONFIG_GROUP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM0_GENID_BAR_CONFIG_CHIP = 7 ;
+static const uint8_t P9N2_PU_NPU0_SM0_GENID_BAR_CONFIG_CHIP_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM0_GENID_BAR_CONFIG_ADDR = 10 ;
+static const uint8_t P9N2_PU_NPU0_SM0_GENID_BAR_CONFIG_ADDR_LEN = 26 ;
+static const uint8_t P9N2_PU_NPU0_SM0_GENID_BAR_RESERVED2 = 36 ;
+static const uint8_t P9N2_PU_NPU0_SM0_GENID_BAR_RESERVED2_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM0_GENID_BAR_CONFIG_POISON = 39 ;
+
+static const uint8_t P9N2_PU_NPU2_SM3_GENID_BAR_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM3_GENID_BAR_RESERVED1 = 1 ;
+static const uint8_t P9N2_PU_NPU2_SM3_GENID_BAR_RESERVED1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM3_GENID_BAR_CONFIG_GROUP = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM3_GENID_BAR_CONFIG_GROUP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM3_GENID_BAR_CONFIG_CHIP = 7 ;
+static const uint8_t P9N2_PU_NPU2_SM3_GENID_BAR_CONFIG_CHIP_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM3_GENID_BAR_CONFIG_ADDR = 10 ;
+static const uint8_t P9N2_PU_NPU2_SM3_GENID_BAR_CONFIG_ADDR_LEN = 26 ;
+static const uint8_t P9N2_PU_NPU2_SM3_GENID_BAR_RESERVED2 = 36 ;
+static const uint8_t P9N2_PU_NPU2_SM3_GENID_BAR_RESERVED2_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM3_GENID_BAR_CONFIG_POISON = 39 ;
+
+static const uint8_t P9N2_PU_NPU0_SM3_GENID_BAR_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM3_GENID_BAR_RESERVED1 = 1 ;
+static const uint8_t P9N2_PU_NPU0_SM3_GENID_BAR_RESERVED1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM3_GENID_BAR_CONFIG_GROUP = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM3_GENID_BAR_CONFIG_GROUP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM3_GENID_BAR_CONFIG_CHIP = 7 ;
+static const uint8_t P9N2_PU_NPU0_SM3_GENID_BAR_CONFIG_CHIP_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM3_GENID_BAR_CONFIG_ADDR = 10 ;
+static const uint8_t P9N2_PU_NPU0_SM3_GENID_BAR_CONFIG_ADDR_LEN = 26 ;
+static const uint8_t P9N2_PU_NPU0_SM3_GENID_BAR_RESERVED2 = 36 ;
+static const uint8_t P9N2_PU_NPU0_SM3_GENID_BAR_RESERVED2_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM3_GENID_BAR_CONFIG_POISON = 39 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM0_GENID_BAR_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_GENID_BAR_RESERVED1 = 1 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_GENID_BAR_RESERVED1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_GENID_BAR_CONFIG_GROUP = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_GENID_BAR_CONFIG_GROUP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_GENID_BAR_CONFIG_CHIP = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_GENID_BAR_CONFIG_CHIP_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_GENID_BAR_CONFIG_ADDR = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_GENID_BAR_CONFIG_ADDR_LEN = 26 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_GENID_BAR_RESERVED2 = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_GENID_BAR_RESERVED2_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_GENID_BAR_CONFIG_POISON = 39 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM1_GENID_BAR_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_GENID_BAR_RESERVED1 = 1 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_GENID_BAR_RESERVED1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_GENID_BAR_CONFIG_GROUP = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_GENID_BAR_CONFIG_GROUP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_GENID_BAR_CONFIG_CHIP = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_GENID_BAR_CONFIG_CHIP_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_GENID_BAR_CONFIG_ADDR = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_GENID_BAR_CONFIG_ADDR_LEN = 26 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_GENID_BAR_RESERVED2 = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_GENID_BAR_RESERVED2_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_GENID_BAR_CONFIG_POISON = 39 ;
+
+static const uint8_t P9N2_PU_NPU2_SM1_GENID_BAR_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM1_GENID_BAR_RESERVED1 = 1 ;
+static const uint8_t P9N2_PU_NPU2_SM1_GENID_BAR_RESERVED1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM1_GENID_BAR_CONFIG_GROUP = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM1_GENID_BAR_CONFIG_GROUP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM1_GENID_BAR_CONFIG_CHIP = 7 ;
+static const uint8_t P9N2_PU_NPU2_SM1_GENID_BAR_CONFIG_CHIP_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM1_GENID_BAR_CONFIG_ADDR = 10 ;
+static const uint8_t P9N2_PU_NPU2_SM1_GENID_BAR_CONFIG_ADDR_LEN = 26 ;
+static const uint8_t P9N2_PU_NPU2_SM1_GENID_BAR_RESERVED2 = 36 ;
+static const uint8_t P9N2_PU_NPU2_SM1_GENID_BAR_RESERVED2_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM1_GENID_BAR_CONFIG_POISON = 39 ;
+
+static const uint8_t P9N2_PU_NPU0_CTL_GENID_BAR_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NPU0_CTL_GENID_BAR_RESERVED1 = 1 ;
+static const uint8_t P9N2_PU_NPU0_CTL_GENID_BAR_RESERVED1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU0_CTL_GENID_BAR_CONFIG_GROUP = 3 ;
+static const uint8_t P9N2_PU_NPU0_CTL_GENID_BAR_CONFIG_GROUP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_CTL_GENID_BAR_CONFIG_CHIP = 7 ;
+static const uint8_t P9N2_PU_NPU0_CTL_GENID_BAR_CONFIG_CHIP_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU0_CTL_GENID_BAR_CONFIG_ADDR = 10 ;
+static const uint8_t P9N2_PU_NPU0_CTL_GENID_BAR_CONFIG_ADDR_LEN = 26 ;
+static const uint8_t P9N2_PU_NPU0_CTL_GENID_BAR_RESERVED2 = 36 ;
+static const uint8_t P9N2_PU_NPU0_CTL_GENID_BAR_RESERVED2_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU0_CTL_GENID_BAR_CONFIG_POISON = 39 ;
+
+static const uint8_t P9N2_PU_NPU2_SM0_GENID_BAR_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM0_GENID_BAR_RESERVED1 = 1 ;
+static const uint8_t P9N2_PU_NPU2_SM0_GENID_BAR_RESERVED1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM0_GENID_BAR_CONFIG_GROUP = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM0_GENID_BAR_CONFIG_GROUP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM0_GENID_BAR_CONFIG_CHIP = 7 ;
+static const uint8_t P9N2_PU_NPU2_SM0_GENID_BAR_CONFIG_CHIP_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM0_GENID_BAR_CONFIG_ADDR = 10 ;
+static const uint8_t P9N2_PU_NPU2_SM0_GENID_BAR_CONFIG_ADDR_LEN = 26 ;
+static const uint8_t P9N2_PU_NPU2_SM0_GENID_BAR_RESERVED2 = 36 ;
+static const uint8_t P9N2_PU_NPU2_SM0_GENID_BAR_RESERVED2_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM0_GENID_BAR_CONFIG_POISON = 39 ;
+
+static const uint8_t P9N2_PU_NPU2_CTL_GENID_BAR_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NPU2_CTL_GENID_BAR_RESERVED1 = 1 ;
+static const uint8_t P9N2_PU_NPU2_CTL_GENID_BAR_RESERVED1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_CTL_GENID_BAR_CONFIG_GROUP = 3 ;
+static const uint8_t P9N2_PU_NPU2_CTL_GENID_BAR_CONFIG_GROUP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_CTL_GENID_BAR_CONFIG_CHIP = 7 ;
+static const uint8_t P9N2_PU_NPU2_CTL_GENID_BAR_CONFIG_CHIP_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU2_CTL_GENID_BAR_CONFIG_ADDR = 10 ;
+static const uint8_t P9N2_PU_NPU2_CTL_GENID_BAR_CONFIG_ADDR_LEN = 26 ;
+static const uint8_t P9N2_PU_NPU2_CTL_GENID_BAR_RESERVED2 = 36 ;
+static const uint8_t P9N2_PU_NPU2_CTL_GENID_BAR_RESERVED2_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU2_CTL_GENID_BAR_CONFIG_POISON = 39 ;
+
+static const uint8_t P9N2_PU_NPU0_SM1_GENID_BAR_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM1_GENID_BAR_RESERVED1 = 1 ;
+static const uint8_t P9N2_PU_NPU0_SM1_GENID_BAR_RESERVED1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM1_GENID_BAR_CONFIG_GROUP = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM1_GENID_BAR_CONFIG_GROUP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM1_GENID_BAR_CONFIG_CHIP = 7 ;
+static const uint8_t P9N2_PU_NPU0_SM1_GENID_BAR_CONFIG_CHIP_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM1_GENID_BAR_CONFIG_ADDR = 10 ;
+static const uint8_t P9N2_PU_NPU0_SM1_GENID_BAR_CONFIG_ADDR_LEN = 26 ;
+static const uint8_t P9N2_PU_NPU0_SM1_GENID_BAR_RESERVED2 = 36 ;
+static const uint8_t P9N2_PU_NPU0_SM1_GENID_BAR_RESERVED2_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM1_GENID_BAR_CONFIG_POISON = 39 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_CTL_GENID_BAR_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_GENID_BAR_RESERVED1 = 1 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_GENID_BAR_RESERVED1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_GENID_BAR_CONFIG_GROUP = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_GENID_BAR_CONFIG_GROUP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_GENID_BAR_CONFIG_CHIP = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_GENID_BAR_CONFIG_CHIP_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_GENID_BAR_CONFIG_ADDR = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_GENID_BAR_CONFIG_ADDR_LEN = 26 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_GENID_BAR_RESERVED2 = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_GENID_BAR_RESERVED2_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_GENID_BAR_CONFIG_POISON = 39 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM3_GENID_BAR_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_GENID_BAR_RESERVED1 = 1 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_GENID_BAR_RESERVED1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_GENID_BAR_CONFIG_GROUP = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_GENID_BAR_CONFIG_GROUP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_GENID_BAR_CONFIG_CHIP = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_GENID_BAR_CONFIG_CHIP_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_GENID_BAR_CONFIG_ADDR = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_GENID_BAR_CONFIG_ADDR_LEN = 26 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_GENID_BAR_RESERVED2 = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_GENID_BAR_RESERVED2_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_GENID_BAR_CONFIG_POISON = 39 ;
+
+static const uint8_t P9N2_PU_NPU2_NTL1_GENID_HEAD0_RESERVED = 0 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_GENID_HEAD0_RESERVED_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_GENID_HEAD0_COUNT = 2 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_GENID_HEAD0_COUNT_LEN = 62 ;
+
+static const uint8_t P9N2_PU_NPU2_NTL1_GENID_HEAD1_RESERVED = 0 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_GENID_HEAD1_RESERVED_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_GENID_HEAD1_COUNT = 2 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_GENID_HEAD1_COUNT_LEN = 62 ;
+
+static const uint8_t P9N2_PU_NPU2_NTL1_GENID_TAIL0_RESERVED = 0 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_GENID_TAIL0_RESERVED_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_GENID_TAIL0_COUNT = 2 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_GENID_TAIL0_COUNT_LEN = 62 ;
+
+static const uint8_t P9N2_PU_NPU2_NTL1_GENID_TAIL1_RESERVED = 0 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_GENID_TAIL1_RESERVED_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_GENID_TAIL1_COUNT = 2 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_GENID_TAIL1_COUNT_LEN = 62 ;
+
+static const uint8_t P9N2_PU_GPE0_GPEDBG_EN_DBG = 0 ;
+static const uint8_t P9N2_PU_GPE0_GPEDBG_HALT_ON_XSTOP = 1 ;
+static const uint8_t P9N2_PU_GPE0_GPEDBG_HALT_ON_TRIG = 2 ;
+static const uint8_t P9N2_PU_GPE0_GPEDBG_RESERVED3 = 3 ;
+static const uint8_t P9N2_PU_GPE0_GPEDBG_EN_INTR_ADDR = 4 ;
+static const uint8_t P9N2_PU_GPE0_GPEDBG_EN_TRACE_EXTRA = 5 ;
+static const uint8_t P9N2_PU_GPE0_GPEDBG_EN_TRACE_STALL = 6 ;
+static const uint8_t P9N2_PU_GPE0_GPEDBG_EN_WAIT_CYCLES = 7 ;
+static const uint8_t P9N2_PU_GPE0_GPEDBG_EN_FULL_SPEED = 8 ;
+static const uint8_t P9N2_PU_GPE0_GPEDBG_RESERVED9 = 9 ;
+static const uint8_t P9N2_PU_GPE0_GPEDBG_TRACE_MODE_SEL = 10 ;
+static const uint8_t P9N2_PU_GPE0_GPEDBG_TRACE_MODE_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_GPE0_GPEDBG_RESERVED12_15 = 12 ;
+static const uint8_t P9N2_PU_GPE0_GPEDBG_RESERVED12_15_LEN = 4 ;
+static const uint8_t P9N2_PU_GPE0_GPEDBG_FIR_TRIGGER = 16 ;
+static const uint8_t P9N2_PU_GPE0_GPEDBG_SPARE = 17 ;
+static const uint8_t P9N2_PU_GPE0_GPEDBG_SPARE_LEN = 3 ;
+static const uint8_t P9N2_PU_GPE0_GPEDBG_TRACE_DATA_SEL = 20 ;
+static const uint8_t P9N2_PU_GPE0_GPEDBG_TRACE_DATA_SEL_LEN = 4 ;
+
+static const uint8_t P9N2_PU_GPE0_GPEIVPR_IVPR = 0 ;
+static const uint8_t P9N2_PU_GPE0_GPEIVPR_IVPR_LEN = 23 ;
+
+static const uint8_t P9N2_PU_GPE0_GPEMACR_MEM_LOW_PRIORITY = 0 ;
+static const uint8_t P9N2_PU_GPE0_GPEMACR_MEM_LOW_PRIORITY_LEN = 2 ;
+static const uint8_t P9N2_PU_GPE0_GPEMACR_MEM_HIGH_PRIORITY = 2 ;
+static const uint8_t P9N2_PU_GPE0_GPEMACR_MEM_HIGH_PRIORITY_LEN = 2 ;
+static const uint8_t P9N2_PU_GPE0_GPEMACR_LOCAL_LOW_PRIORITY = 4 ;
+static const uint8_t P9N2_PU_GPE0_GPEMACR_LOCAL_LOW_PRIORITY_LEN = 2 ;
+static const uint8_t P9N2_PU_GPE0_GPEMACR_LOCAL_HIGH_PRIORITY = 6 ;
+static const uint8_t P9N2_PU_GPE0_GPEMACR_LOCAL_HIGH_PRIORITY_LEN = 2 ;
+static const uint8_t P9N2_PU_GPE0_GPEMACR_SRAM_LOW_PRIORITY = 8 ;
+static const uint8_t P9N2_PU_GPE0_GPEMACR_SRAM_LOW_PRIORITY_LEN = 2 ;
+static const uint8_t P9N2_PU_GPE0_GPEMACR_SRAM_HIGH_PRIORITY = 10 ;
+static const uint8_t P9N2_PU_GPE0_GPEMACR_SRAM_HIGH_PRIORITY_LEN = 2 ;
+
+static const uint8_t P9N2_PU_GPE0_GPENXIXCR_PPE_XIXCR_XCR = 1 ;
+static const uint8_t P9N2_PU_GPE0_GPENXIXCR_PPE_XIXCR_XCR_LEN = 3 ;
+
+static const uint8_t P9N2_PU_GPE0_GPESTR_PBASE = 12 ;
+static const uint8_t P9N2_PU_GPE0_GPESTR_PBASE_LEN = 10 ;
+static const uint8_t P9N2_PU_GPE0_GPESTR_SIZE = 29 ;
+static const uint8_t P9N2_PU_GPE0_GPESTR_SIZE_LEN = 3 ;
+
+static const uint8_t P9N2_PU_GPE0_GPETSEL_WATCHDOG_SEL = 0 ;
+static const uint8_t P9N2_PU_GPE0_GPETSEL_WATCHDOG_SEL_LEN = 4 ;
+static const uint8_t P9N2_PU_GPE0_GPETSEL_FIT_SEL = 4 ;
+static const uint8_t P9N2_PU_GPE0_GPETSEL_FIT_SEL_LEN = 4 ;
+
+static const uint8_t P9N2_PU_GPE0_GPEXIEDR_PPE_XIRAMEDR_EDR = 0 ;
+static const uint8_t P9N2_PU_GPE0_GPEXIEDR_PPE_XIRAMEDR_EDR_LEN = 32 ;
+
+static const uint8_t P9N2_PU_GPE0_GPEXIIAR_IAR = 0 ;
+static const uint8_t P9N2_PU_GPE0_GPEXIIAR_IAR_LEN = 30 ;
+
+static const uint8_t P9N2_PU_GPE0_GPEXIIR_PPE_XIRAMGA_IR = 0 ;
+static const uint8_t P9N2_PU_GPE0_GPEXIIR_PPE_XIRAMGA_IR_LEN = 32 ;
+
+static const uint8_t P9N2_PU_GPE0_GPEXISPRG0_PPE_XIRAMRA_SPRG0 = 0 ;
+static const uint8_t P9N2_PU_GPE0_GPEXISPRG0_PPE_XIRAMRA_SPRG0_LEN = 32 ;
+
+static const uint8_t P9N2_PU_GPE0_GPEXIXCR_PPE_XIXCR_XCR = 1 ;
+static const uint8_t P9N2_PU_GPE0_GPEXIXCR_PPE_XIXCR_XCR_LEN = 3 ;
+
+static const uint8_t P9N2_PU_GPE0_GPEXIXSR_XSR_HS = 0 ;
+static const uint8_t P9N2_PU_GPE0_GPEXIXSR_XSR_HC = 1 ;
+static const uint8_t P9N2_PU_GPE0_GPEXIXSR_XSR_HC_LEN = 3 ;
+static const uint8_t P9N2_PU_GPE0_GPEXIXSR_XSR_HCP = 4 ;
+static const uint8_t P9N2_PU_GPE0_GPEXIXSR_XSR_RIP = 5 ;
+static const uint8_t P9N2_PU_GPE0_GPEXIXSR_XSR_SIP = 6 ;
+static const uint8_t P9N2_PU_GPE0_GPEXIXSR_XSR_TRAP = 7 ;
+static const uint8_t P9N2_PU_GPE0_GPEXIXSR_XSR_IAC = 8 ;
+static const uint8_t P9N2_PU_GPE0_GPEXIXSR_NULL_MSR_SIBRC = 9 ;
+static const uint8_t P9N2_PU_GPE0_GPEXIXSR_NULL_MSR_SIBRC_LEN = 3 ;
+static const uint8_t P9N2_PU_GPE0_GPEXIXSR_XSR_DACR = 12 ;
+static const uint8_t P9N2_PU_GPE0_GPEXIXSR_XSR_DACW = 13 ;
+static const uint8_t P9N2_PU_GPE0_GPEXIXSR_NULL_MSR_WE = 14 ;
+static const uint8_t P9N2_PU_GPE0_GPEXIXSR_XSR_TRH = 15 ;
+static const uint8_t P9N2_PU_GPE0_GPEXIXSR_XSR_SMS = 16 ;
+static const uint8_t P9N2_PU_GPE0_GPEXIXSR_XSR_SMS_LEN = 4 ;
+static const uint8_t P9N2_PU_GPE0_GPEXIXSR_NULL_MSR_LP = 20 ;
+static const uint8_t P9N2_PU_GPE0_GPEXIXSR_XSR_EP = 21 ;
+static const uint8_t P9N2_PU_GPE0_GPEXIXSR_XSR_PTR = 24 ;
+static const uint8_t P9N2_PU_GPE0_GPEXIXSR_XSR_ST = 25 ;
+static const uint8_t P9N2_PU_GPE0_GPEXIXSR_XSR_MFE = 28 ;
+static const uint8_t P9N2_PU_GPE0_GPEXIXSR_XSR_MCS = 29 ;
+static const uint8_t P9N2_PU_GPE0_GPEXIXSR_XSR_MCS_LEN = 3 ;
+
+static const uint8_t P9N2_PU_GPE0_MIB_XIDCAC_DCACHE_TAG_ADDR = 0 ;
+static const uint8_t P9N2_PU_GPE0_MIB_XIDCAC_DCACHE_TAG_ADDR_LEN = 27 ;
+static const uint8_t P9N2_PU_GPE0_MIB_XIDCAC_DCACHE_ERR = 32 ;
+static const uint8_t P9N2_PU_GPE0_MIB_XIDCAC_DCACHE_POPULATE_PENDING = 35 ;
+static const uint8_t P9N2_PU_GPE0_MIB_XIDCAC_DCACHE_VALID = 36 ;
+static const uint8_t P9N2_PU_GPE0_MIB_XIDCAC_DCACHE_VALID_LEN = 2 ;
+
+static const uint8_t P9N2_PU_GPE0_MIB_XIICAC_ICACHE_TAG_ADDR = 0 ;
+static const uint8_t P9N2_PU_GPE0_MIB_XIICAC_ICACHE_TAG_ADDR_LEN = 27 ;
+static const uint8_t P9N2_PU_GPE0_MIB_XIICAC_ICACHE_ERR = 32 ;
+static const uint8_t P9N2_PU_GPE0_MIB_XIICAC_XISIB_PIB_IFETCH_PENDING = 34 ;
+static const uint8_t P9N2_PU_GPE0_MIB_XIICAC_XIMEM_MEM_IFETCH_PENDING = 35 ;
+static const uint8_t P9N2_PU_GPE0_MIB_XIICAC_ICACHE_VALID = 36 ;
+static const uint8_t P9N2_PU_GPE0_MIB_XIICAC_ICACHE_VALID_LEN = 4 ;
+static const uint8_t P9N2_PU_GPE0_MIB_XIICAC_ICACHE_LINE2_VALID = 40 ;
+static const uint8_t P9N2_PU_GPE0_MIB_XIICAC_ICACHE_LINE2_VALID_LEN = 4 ;
+static const uint8_t P9N2_PU_GPE0_MIB_XIICAC_ICACHE_LINE_PTR = 45 ;
+static const uint8_t P9N2_PU_GPE0_MIB_XIICAC_ICACHE_LINE2_ERR = 46 ;
+static const uint8_t P9N2_PU_GPE0_MIB_XIICAC_ICACHE_PREFETCH_PENDING = 47 ;
+
+static const uint8_t P9N2_PU_GPE0_MIB_XIMEM_MEM_ADDR = 0 ;
+static const uint8_t P9N2_PU_GPE0_MIB_XIMEM_MEM_ADDR_LEN = 32 ;
+static const uint8_t P9N2_PU_GPE0_MIB_XIMEM_MEM_R_NW = 32 ;
+static const uint8_t P9N2_PU_GPE0_MIB_XIMEM_MEM_BUSY = 33 ;
+static const uint8_t P9N2_PU_GPE0_MIB_XIMEM_MEM_IMPRECISE_ERROR_PENDING = 34 ;
+static const uint8_t P9N2_PU_GPE0_MIB_XIMEM_MEM_BYTE_ENABLE = 35 ;
+static const uint8_t P9N2_PU_GPE0_MIB_XIMEM_MEM_BYTE_ENABLE_LEN = 8 ;
+static const uint8_t P9N2_PU_GPE0_MIB_XIMEM_MEM_LINE_MODE = 43 ;
+static const uint8_t P9N2_PU_GPE0_MIB_XIMEM_MEM_ERROR = 49 ;
+static const uint8_t P9N2_PU_GPE0_MIB_XIMEM_MEM_ERROR_LEN = 3 ;
+static const uint8_t P9N2_PU_GPE0_MIB_XIMEM_MEM_IFETCH_PENDING = 62 ;
+static const uint8_t P9N2_PU_GPE0_MIB_XIMEM_MEM_DATAOP_PENDING = 63 ;
+
+static const uint8_t P9N2_PU_GPE0_MIB_XISGB_STORE_ADDRESS = 0 ;
+static const uint8_t P9N2_PU_GPE0_MIB_XISGB_STORE_ADDRESS_LEN = 32 ;
+static const uint8_t P9N2_PU_GPE0_MIB_XISGB_XIMEM_MEM_IMPRECISE_ERROR_PENDING = 35 ;
+static const uint8_t P9N2_PU_GPE0_MIB_XISGB_SGB_BYTE_VALID = 36 ;
+static const uint8_t P9N2_PU_GPE0_MIB_XISGB_SGB_BYTE_VALID_LEN = 4 ;
+static const uint8_t P9N2_PU_GPE0_MIB_XISGB_SGB_FLUSH_PENDING = 63 ;
+
+static const uint8_t P9N2_PU_GPE0_MIB_XISIB_PIB_ADDR = 0 ;
+static const uint8_t P9N2_PU_GPE0_MIB_XISIB_PIB_ADDR_LEN = 32 ;
+static const uint8_t P9N2_PU_GPE0_MIB_XISIB_PIB_R_NW = 32 ;
+static const uint8_t P9N2_PU_GPE0_MIB_XISIB_PIB_BUSY = 33 ;
+static const uint8_t P9N2_PU_GPE0_MIB_XISIB_PIB_IMPRECISE_ERROR_PENDING = 34 ;
+static const uint8_t P9N2_PU_GPE0_MIB_XISIB_PIB_RSP_INFO = 49 ;
+static const uint8_t P9N2_PU_GPE0_MIB_XISIB_PIB_RSP_INFO_LEN = 3 ;
+static const uint8_t P9N2_PU_GPE0_MIB_XISIB_PIB_IFETCH_PENDING = 62 ;
+static const uint8_t P9N2_PU_GPE0_MIB_XISIB_PIB_DATAOP_PENDING = 63 ;
+
+static const uint8_t P9N2_PU_GPE0_PPE_XIDBGPRO_XSR_HS = 0 ;
+static const uint8_t P9N2_PU_GPE0_PPE_XIDBGPRO_XSR_HC = 1 ;
+static const uint8_t P9N2_PU_GPE0_PPE_XIDBGPRO_XSR_HC_LEN = 3 ;
+static const uint8_t P9N2_PU_GPE0_PPE_XIDBGPRO_XSR_HCP = 4 ;
+static const uint8_t P9N2_PU_GPE0_PPE_XIDBGPRO_XSR_RIP = 5 ;
+static const uint8_t P9N2_PU_GPE0_PPE_XIDBGPRO_XSR_SIP = 6 ;
+static const uint8_t P9N2_PU_GPE0_PPE_XIDBGPRO_XSR_TRAP = 7 ;
+static const uint8_t P9N2_PU_GPE0_PPE_XIDBGPRO_XSR_IAC = 8 ;
+static const uint8_t P9N2_PU_GPE0_PPE_XIDBGPRO_NULL_MSR_SIBRC = 9 ;
+static const uint8_t P9N2_PU_GPE0_PPE_XIDBGPRO_NULL_MSR_SIBRC_LEN = 3 ;
+static const uint8_t P9N2_PU_GPE0_PPE_XIDBGPRO_XSR_DACR = 12 ;
+static const uint8_t P9N2_PU_GPE0_PPE_XIDBGPRO_XSR_DACW = 13 ;
+static const uint8_t P9N2_PU_GPE0_PPE_XIDBGPRO_NULL_MSR_WE = 14 ;
+static const uint8_t P9N2_PU_GPE0_PPE_XIDBGPRO_XSR_TRH = 15 ;
+static const uint8_t P9N2_PU_GPE0_PPE_XIDBGPRO_XSR_SMS = 16 ;
+static const uint8_t P9N2_PU_GPE0_PPE_XIDBGPRO_XSR_SMS_LEN = 4 ;
+static const uint8_t P9N2_PU_GPE0_PPE_XIDBGPRO_NULL_MSR_LP = 20 ;
+static const uint8_t P9N2_PU_GPE0_PPE_XIDBGPRO_XSR_EP = 21 ;
+static const uint8_t P9N2_PU_GPE0_PPE_XIDBGPRO_XSR_PTR = 24 ;
+static const uint8_t P9N2_PU_GPE0_PPE_XIDBGPRO_XSR_ST = 25 ;
+static const uint8_t P9N2_PU_GPE0_PPE_XIDBGPRO_XSR_MFE = 28 ;
+static const uint8_t P9N2_PU_GPE0_PPE_XIDBGPRO_XSR_MCS = 29 ;
+static const uint8_t P9N2_PU_GPE0_PPE_XIDBGPRO_XSR_MCS_LEN = 3 ;
+static const uint8_t P9N2_PU_GPE0_PPE_XIDBGPRO_IAR = 32 ;
+static const uint8_t P9N2_PU_GPE0_PPE_XIDBGPRO_IAR_LEN = 30 ;
+
+static const uint8_t P9N2_PU_GPE0_PPE_XIRAMDBG_XSR_HS = 0 ;
+static const uint8_t P9N2_PU_GPE0_PPE_XIRAMDBG_XSR_HC = 1 ;
+static const uint8_t P9N2_PU_GPE0_PPE_XIRAMDBG_XSR_HC_LEN = 3 ;
+static const uint8_t P9N2_PU_GPE0_PPE_XIRAMDBG_XSR_HCP = 4 ;
+static const uint8_t P9N2_PU_GPE0_PPE_XIRAMDBG_XSR_RIP = 5 ;
+static const uint8_t P9N2_PU_GPE0_PPE_XIRAMDBG_XSR_SIP = 6 ;
+static const uint8_t P9N2_PU_GPE0_PPE_XIRAMDBG_XSR_TRAP = 7 ;
+static const uint8_t P9N2_PU_GPE0_PPE_XIRAMDBG_XSR_IAC = 8 ;
+static const uint8_t P9N2_PU_GPE0_PPE_XIRAMDBG_NULL_MSR_SIBRC = 9 ;
+static const uint8_t P9N2_PU_GPE0_PPE_XIRAMDBG_NULL_MSR_SIBRC_LEN = 3 ;
+static const uint8_t P9N2_PU_GPE0_PPE_XIRAMDBG_XSR_DACR = 12 ;
+static const uint8_t P9N2_PU_GPE0_PPE_XIRAMDBG_XSR_DACW = 13 ;
+static const uint8_t P9N2_PU_GPE0_PPE_XIRAMDBG_NULL_MSR_WE = 14 ;
+static const uint8_t P9N2_PU_GPE0_PPE_XIRAMDBG_XSR_TRH = 15 ;
+static const uint8_t P9N2_PU_GPE0_PPE_XIRAMDBG_XSR_SMS = 16 ;
+static const uint8_t P9N2_PU_GPE0_PPE_XIRAMDBG_XSR_SMS_LEN = 4 ;
+static const uint8_t P9N2_PU_GPE0_PPE_XIRAMDBG_NULL_MSR_LP = 20 ;
+static const uint8_t P9N2_PU_GPE0_PPE_XIRAMDBG_XSR_EP = 21 ;
+static const uint8_t P9N2_PU_GPE0_PPE_XIRAMDBG_XSR_PTR = 24 ;
+static const uint8_t P9N2_PU_GPE0_PPE_XIRAMDBG_XSR_ST = 25 ;
+static const uint8_t P9N2_PU_GPE0_PPE_XIRAMDBG_XSR_MFE = 28 ;
+static const uint8_t P9N2_PU_GPE0_PPE_XIRAMDBG_XSR_MCS = 29 ;
+static const uint8_t P9N2_PU_GPE0_PPE_XIRAMDBG_XSR_MCS_LEN = 3 ;
+static const uint8_t P9N2_PU_GPE0_PPE_XIRAMDBG_XIRAMRA_SPRG0 = 32 ;
+static const uint8_t P9N2_PU_GPE0_PPE_XIRAMDBG_XIRAMRA_SPRG0_LEN = 32 ;
+
+static const uint8_t P9N2_PU_GPE0_PPE_XIRAMEDR_XIRAMGA_IR = 0 ;
+static const uint8_t P9N2_PU_GPE0_PPE_XIRAMEDR_XIRAMGA_IR_LEN = 32 ;
+static const uint8_t P9N2_PU_GPE0_PPE_XIRAMEDR_EDR = 32 ;
+static const uint8_t P9N2_PU_GPE0_PPE_XIRAMEDR_EDR_LEN = 32 ;
+
+static const uint8_t P9N2_PU_GPE0_PPE_XIRAMGA_IR = 0 ;
+static const uint8_t P9N2_PU_GPE0_PPE_XIRAMGA_IR_LEN = 32 ;
+static const uint8_t P9N2_PU_GPE0_PPE_XIRAMGA_XIRAMRA_SPRG0 = 32 ;
+static const uint8_t P9N2_PU_GPE0_PPE_XIRAMGA_XIRAMRA_SPRG0_LEN = 32 ;
+
+static const uint8_t P9N2_PU_GPE0_PPE_XIRAMRA_XIXCR_XCR = 1 ;
+static const uint8_t P9N2_PU_GPE0_PPE_XIRAMRA_XIXCR_XCR_LEN = 3 ;
+static const uint8_t P9N2_PU_GPE0_PPE_XIRAMRA_SPRG0 = 32 ;
+static const uint8_t P9N2_PU_GPE0_PPE_XIRAMRA_SPRG0_LEN = 32 ;
+
+static const uint8_t P9N2_PU_GPE0_PPE_XIXCR_XCR = 1 ;
+static const uint8_t P9N2_PU_GPE0_PPE_XIXCR_XCR_LEN = 3 ;
+
+static const uint8_t P9N2_PU_GPE1_GPEDBG_EN_DBG = 0 ;
+static const uint8_t P9N2_PU_GPE1_GPEDBG_HALT_ON_XSTOP = 1 ;
+static const uint8_t P9N2_PU_GPE1_GPEDBG_HALT_ON_TRIG = 2 ;
+static const uint8_t P9N2_PU_GPE1_GPEDBG_RESERVED3 = 3 ;
+static const uint8_t P9N2_PU_GPE1_GPEDBG_EN_INTR_ADDR = 4 ;
+static const uint8_t P9N2_PU_GPE1_GPEDBG_EN_TRACE_EXTRA = 5 ;
+static const uint8_t P9N2_PU_GPE1_GPEDBG_EN_TRACE_STALL = 6 ;
+static const uint8_t P9N2_PU_GPE1_GPEDBG_EN_WAIT_CYCLES = 7 ;
+static const uint8_t P9N2_PU_GPE1_GPEDBG_EN_FULL_SPEED = 8 ;
+static const uint8_t P9N2_PU_GPE1_GPEDBG_RESERVED9 = 9 ;
+static const uint8_t P9N2_PU_GPE1_GPEDBG_TRACE_MODE_SEL = 10 ;
+static const uint8_t P9N2_PU_GPE1_GPEDBG_TRACE_MODE_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_GPE1_GPEDBG_RESERVED12_15 = 12 ;
+static const uint8_t P9N2_PU_GPE1_GPEDBG_RESERVED12_15_LEN = 4 ;
+static const uint8_t P9N2_PU_GPE1_GPEDBG_FIR_TRIGGER = 16 ;
+static const uint8_t P9N2_PU_GPE1_GPEDBG_SPARE = 17 ;
+static const uint8_t P9N2_PU_GPE1_GPEDBG_SPARE_LEN = 3 ;
+static const uint8_t P9N2_PU_GPE1_GPEDBG_TRACE_DATA_SEL = 20 ;
+static const uint8_t P9N2_PU_GPE1_GPEDBG_TRACE_DATA_SEL_LEN = 4 ;
+
+static const uint8_t P9N2_PU_GPE1_GPEIVPR_IVPR = 0 ;
+static const uint8_t P9N2_PU_GPE1_GPEIVPR_IVPR_LEN = 23 ;
+
+static const uint8_t P9N2_PU_GPE1_GPEMACR_MEM_LOW_PRIORITY = 0 ;
+static const uint8_t P9N2_PU_GPE1_GPEMACR_MEM_LOW_PRIORITY_LEN = 2 ;
+static const uint8_t P9N2_PU_GPE1_GPEMACR_MEM_HIGH_PRIORITY = 2 ;
+static const uint8_t P9N2_PU_GPE1_GPEMACR_MEM_HIGH_PRIORITY_LEN = 2 ;
+static const uint8_t P9N2_PU_GPE1_GPEMACR_LOCAL_LOW_PRIORITY = 4 ;
+static const uint8_t P9N2_PU_GPE1_GPEMACR_LOCAL_LOW_PRIORITY_LEN = 2 ;
+static const uint8_t P9N2_PU_GPE1_GPEMACR_LOCAL_HIGH_PRIORITY = 6 ;
+static const uint8_t P9N2_PU_GPE1_GPEMACR_LOCAL_HIGH_PRIORITY_LEN = 2 ;
+static const uint8_t P9N2_PU_GPE1_GPEMACR_SRAM_LOW_PRIORITY = 8 ;
+static const uint8_t P9N2_PU_GPE1_GPEMACR_SRAM_LOW_PRIORITY_LEN = 2 ;
+static const uint8_t P9N2_PU_GPE1_GPEMACR_SRAM_HIGH_PRIORITY = 10 ;
+static const uint8_t P9N2_PU_GPE1_GPEMACR_SRAM_HIGH_PRIORITY_LEN = 2 ;
+
+static const uint8_t P9N2_PU_GPE1_GPENXIXCR_PPE_XIXCR_XCR = 1 ;
+static const uint8_t P9N2_PU_GPE1_GPENXIXCR_PPE_XIXCR_XCR_LEN = 3 ;
+
+static const uint8_t P9N2_PU_GPE1_GPESTR_PBASE = 12 ;
+static const uint8_t P9N2_PU_GPE1_GPESTR_PBASE_LEN = 10 ;
+static const uint8_t P9N2_PU_GPE1_GPESTR_SIZE = 29 ;
+static const uint8_t P9N2_PU_GPE1_GPESTR_SIZE_LEN = 3 ;
+
+static const uint8_t P9N2_PU_GPE1_GPETSEL_WATCHDOG_SEL = 0 ;
+static const uint8_t P9N2_PU_GPE1_GPETSEL_WATCHDOG_SEL_LEN = 4 ;
+static const uint8_t P9N2_PU_GPE1_GPETSEL_FIT_SEL = 4 ;
+static const uint8_t P9N2_PU_GPE1_GPETSEL_FIT_SEL_LEN = 4 ;
+
+static const uint8_t P9N2_PU_GPE1_GPEXIEDR_PPE_XIRAMEDR_EDR = 0 ;
+static const uint8_t P9N2_PU_GPE1_GPEXIEDR_PPE_XIRAMEDR_EDR_LEN = 32 ;
+
+static const uint8_t P9N2_PU_GPE1_GPEXIIAR_IAR = 0 ;
+static const uint8_t P9N2_PU_GPE1_GPEXIIAR_IAR_LEN = 30 ;
+
+static const uint8_t P9N2_PU_GPE1_GPEXIIR_PPE_XIRAMGA_IR = 0 ;
+static const uint8_t P9N2_PU_GPE1_GPEXIIR_PPE_XIRAMGA_IR_LEN = 32 ;
+
+static const uint8_t P9N2_PU_GPE1_GPEXISPRG0_PPE_XIRAMRA_SPRG0 = 0 ;
+static const uint8_t P9N2_PU_GPE1_GPEXISPRG0_PPE_XIRAMRA_SPRG0_LEN = 32 ;
+
+static const uint8_t P9N2_PU_GPE1_GPEXIXCR_PPE_XIXCR_XCR = 1 ;
+static const uint8_t P9N2_PU_GPE1_GPEXIXCR_PPE_XIXCR_XCR_LEN = 3 ;
+
+static const uint8_t P9N2_PU_GPE1_GPEXIXSR_XSR_HS = 0 ;
+static const uint8_t P9N2_PU_GPE1_GPEXIXSR_XSR_HC = 1 ;
+static const uint8_t P9N2_PU_GPE1_GPEXIXSR_XSR_HC_LEN = 3 ;
+static const uint8_t P9N2_PU_GPE1_GPEXIXSR_XSR_HCP = 4 ;
+static const uint8_t P9N2_PU_GPE1_GPEXIXSR_XSR_RIP = 5 ;
+static const uint8_t P9N2_PU_GPE1_GPEXIXSR_XSR_SIP = 6 ;
+static const uint8_t P9N2_PU_GPE1_GPEXIXSR_XSR_TRAP = 7 ;
+static const uint8_t P9N2_PU_GPE1_GPEXIXSR_XSR_IAC = 8 ;
+static const uint8_t P9N2_PU_GPE1_GPEXIXSR_NULL_MSR_SIBRC = 9 ;
+static const uint8_t P9N2_PU_GPE1_GPEXIXSR_NULL_MSR_SIBRC_LEN = 3 ;
+static const uint8_t P9N2_PU_GPE1_GPEXIXSR_XSR_DACR = 12 ;
+static const uint8_t P9N2_PU_GPE1_GPEXIXSR_XSR_DACW = 13 ;
+static const uint8_t P9N2_PU_GPE1_GPEXIXSR_NULL_MSR_WE = 14 ;
+static const uint8_t P9N2_PU_GPE1_GPEXIXSR_XSR_TRH = 15 ;
+static const uint8_t P9N2_PU_GPE1_GPEXIXSR_XSR_SMS = 16 ;
+static const uint8_t P9N2_PU_GPE1_GPEXIXSR_XSR_SMS_LEN = 4 ;
+static const uint8_t P9N2_PU_GPE1_GPEXIXSR_NULL_MSR_LP = 20 ;
+static const uint8_t P9N2_PU_GPE1_GPEXIXSR_XSR_EP = 21 ;
+static const uint8_t P9N2_PU_GPE1_GPEXIXSR_XSR_PTR = 24 ;
+static const uint8_t P9N2_PU_GPE1_GPEXIXSR_XSR_ST = 25 ;
+static const uint8_t P9N2_PU_GPE1_GPEXIXSR_XSR_MFE = 28 ;
+static const uint8_t P9N2_PU_GPE1_GPEXIXSR_XSR_MCS = 29 ;
+static const uint8_t P9N2_PU_GPE1_GPEXIXSR_XSR_MCS_LEN = 3 ;
+
+static const uint8_t P9N2_PU_GPE1_MIB_XIDCAC_DCACHE_TAG_ADDR = 0 ;
+static const uint8_t P9N2_PU_GPE1_MIB_XIDCAC_DCACHE_TAG_ADDR_LEN = 27 ;
+static const uint8_t P9N2_PU_GPE1_MIB_XIDCAC_DCACHE_ERR = 32 ;
+static const uint8_t P9N2_PU_GPE1_MIB_XIDCAC_DCACHE_POPULATE_PENDING = 35 ;
+static const uint8_t P9N2_PU_GPE1_MIB_XIDCAC_DCACHE_VALID = 36 ;
+static const uint8_t P9N2_PU_GPE1_MIB_XIDCAC_DCACHE_VALID_LEN = 2 ;
+
+static const uint8_t P9N2_PU_GPE1_MIB_XIICAC_ICACHE_TAG_ADDR = 0 ;
+static const uint8_t P9N2_PU_GPE1_MIB_XIICAC_ICACHE_TAG_ADDR_LEN = 27 ;
+static const uint8_t P9N2_PU_GPE1_MIB_XIICAC_ICACHE_ERR = 32 ;
+static const uint8_t P9N2_PU_GPE1_MIB_XIICAC_XISIB_PIB_IFETCH_PENDING = 34 ;
+static const uint8_t P9N2_PU_GPE1_MIB_XIICAC_XIMEM_MEM_IFETCH_PENDING = 35 ;
+static const uint8_t P9N2_PU_GPE1_MIB_XIICAC_ICACHE_VALID = 36 ;
+static const uint8_t P9N2_PU_GPE1_MIB_XIICAC_ICACHE_VALID_LEN = 4 ;
+static const uint8_t P9N2_PU_GPE1_MIB_XIICAC_ICACHE_LINE2_VALID = 40 ;
+static const uint8_t P9N2_PU_GPE1_MIB_XIICAC_ICACHE_LINE2_VALID_LEN = 4 ;
+static const uint8_t P9N2_PU_GPE1_MIB_XIICAC_ICACHE_LINE_PTR = 45 ;
+static const uint8_t P9N2_PU_GPE1_MIB_XIICAC_ICACHE_LINE2_ERR = 46 ;
+static const uint8_t P9N2_PU_GPE1_MIB_XIICAC_ICACHE_PREFETCH_PENDING = 47 ;
+
+static const uint8_t P9N2_PU_GPE1_MIB_XIMEM_MEM_ADDR = 0 ;
+static const uint8_t P9N2_PU_GPE1_MIB_XIMEM_MEM_ADDR_LEN = 32 ;
+static const uint8_t P9N2_PU_GPE1_MIB_XIMEM_MEM_R_NW = 32 ;
+static const uint8_t P9N2_PU_GPE1_MIB_XIMEM_MEM_BUSY = 33 ;
+static const uint8_t P9N2_PU_GPE1_MIB_XIMEM_MEM_IMPRECISE_ERROR_PENDING = 34 ;
+static const uint8_t P9N2_PU_GPE1_MIB_XIMEM_MEM_BYTE_ENABLE = 35 ;
+static const uint8_t P9N2_PU_GPE1_MIB_XIMEM_MEM_BYTE_ENABLE_LEN = 8 ;
+static const uint8_t P9N2_PU_GPE1_MIB_XIMEM_MEM_LINE_MODE = 43 ;
+static const uint8_t P9N2_PU_GPE1_MIB_XIMEM_MEM_ERROR = 49 ;
+static const uint8_t P9N2_PU_GPE1_MIB_XIMEM_MEM_ERROR_LEN = 3 ;
+static const uint8_t P9N2_PU_GPE1_MIB_XIMEM_MEM_IFETCH_PENDING = 62 ;
+static const uint8_t P9N2_PU_GPE1_MIB_XIMEM_MEM_DATAOP_PENDING = 63 ;
+
+static const uint8_t P9N2_PU_GPE1_MIB_XISGB_STORE_ADDRESS = 0 ;
+static const uint8_t P9N2_PU_GPE1_MIB_XISGB_STORE_ADDRESS_LEN = 32 ;
+static const uint8_t P9N2_PU_GPE1_MIB_XISGB_XIMEM_MEM_IMPRECISE_ERROR_PENDING = 35 ;
+static const uint8_t P9N2_PU_GPE1_MIB_XISGB_SGB_BYTE_VALID = 36 ;
+static const uint8_t P9N2_PU_GPE1_MIB_XISGB_SGB_BYTE_VALID_LEN = 4 ;
+static const uint8_t P9N2_PU_GPE1_MIB_XISGB_SGB_FLUSH_PENDING = 63 ;
+
+static const uint8_t P9N2_PU_GPE1_MIB_XISIB_PIB_ADDR = 0 ;
+static const uint8_t P9N2_PU_GPE1_MIB_XISIB_PIB_ADDR_LEN = 32 ;
+static const uint8_t P9N2_PU_GPE1_MIB_XISIB_PIB_R_NW = 32 ;
+static const uint8_t P9N2_PU_GPE1_MIB_XISIB_PIB_BUSY = 33 ;
+static const uint8_t P9N2_PU_GPE1_MIB_XISIB_PIB_IMPRECISE_ERROR_PENDING = 34 ;
+static const uint8_t P9N2_PU_GPE1_MIB_XISIB_PIB_RSP_INFO = 49 ;
+static const uint8_t P9N2_PU_GPE1_MIB_XISIB_PIB_RSP_INFO_LEN = 3 ;
+static const uint8_t P9N2_PU_GPE1_MIB_XISIB_PIB_IFETCH_PENDING = 62 ;
+static const uint8_t P9N2_PU_GPE1_MIB_XISIB_PIB_DATAOP_PENDING = 63 ;
+
+static const uint8_t P9N2_PU_GPE1_PPE_XIDBGPRO_XSR_HS = 0 ;
+static const uint8_t P9N2_PU_GPE1_PPE_XIDBGPRO_XSR_HC = 1 ;
+static const uint8_t P9N2_PU_GPE1_PPE_XIDBGPRO_XSR_HC_LEN = 3 ;
+static const uint8_t P9N2_PU_GPE1_PPE_XIDBGPRO_XSR_HCP = 4 ;
+static const uint8_t P9N2_PU_GPE1_PPE_XIDBGPRO_XSR_RIP = 5 ;
+static const uint8_t P9N2_PU_GPE1_PPE_XIDBGPRO_XSR_SIP = 6 ;
+static const uint8_t P9N2_PU_GPE1_PPE_XIDBGPRO_XSR_TRAP = 7 ;
+static const uint8_t P9N2_PU_GPE1_PPE_XIDBGPRO_XSR_IAC = 8 ;
+static const uint8_t P9N2_PU_GPE1_PPE_XIDBGPRO_NULL_MSR_SIBRC = 9 ;
+static const uint8_t P9N2_PU_GPE1_PPE_XIDBGPRO_NULL_MSR_SIBRC_LEN = 3 ;
+static const uint8_t P9N2_PU_GPE1_PPE_XIDBGPRO_XSR_DACR = 12 ;
+static const uint8_t P9N2_PU_GPE1_PPE_XIDBGPRO_XSR_DACW = 13 ;
+static const uint8_t P9N2_PU_GPE1_PPE_XIDBGPRO_NULL_MSR_WE = 14 ;
+static const uint8_t P9N2_PU_GPE1_PPE_XIDBGPRO_XSR_TRH = 15 ;
+static const uint8_t P9N2_PU_GPE1_PPE_XIDBGPRO_XSR_SMS = 16 ;
+static const uint8_t P9N2_PU_GPE1_PPE_XIDBGPRO_XSR_SMS_LEN = 4 ;
+static const uint8_t P9N2_PU_GPE1_PPE_XIDBGPRO_NULL_MSR_LP = 20 ;
+static const uint8_t P9N2_PU_GPE1_PPE_XIDBGPRO_XSR_EP = 21 ;
+static const uint8_t P9N2_PU_GPE1_PPE_XIDBGPRO_XSR_PTR = 24 ;
+static const uint8_t P9N2_PU_GPE1_PPE_XIDBGPRO_XSR_ST = 25 ;
+static const uint8_t P9N2_PU_GPE1_PPE_XIDBGPRO_XSR_MFE = 28 ;
+static const uint8_t P9N2_PU_GPE1_PPE_XIDBGPRO_XSR_MCS = 29 ;
+static const uint8_t P9N2_PU_GPE1_PPE_XIDBGPRO_XSR_MCS_LEN = 3 ;
+static const uint8_t P9N2_PU_GPE1_PPE_XIDBGPRO_IAR = 32 ;
+static const uint8_t P9N2_PU_GPE1_PPE_XIDBGPRO_IAR_LEN = 30 ;
+
+static const uint8_t P9N2_PU_GPE1_PPE_XIRAMDBG_XSR_HS = 0 ;
+static const uint8_t P9N2_PU_GPE1_PPE_XIRAMDBG_XSR_HC = 1 ;
+static const uint8_t P9N2_PU_GPE1_PPE_XIRAMDBG_XSR_HC_LEN = 3 ;
+static const uint8_t P9N2_PU_GPE1_PPE_XIRAMDBG_XSR_HCP = 4 ;
+static const uint8_t P9N2_PU_GPE1_PPE_XIRAMDBG_XSR_RIP = 5 ;
+static const uint8_t P9N2_PU_GPE1_PPE_XIRAMDBG_XSR_SIP = 6 ;
+static const uint8_t P9N2_PU_GPE1_PPE_XIRAMDBG_XSR_TRAP = 7 ;
+static const uint8_t P9N2_PU_GPE1_PPE_XIRAMDBG_XSR_IAC = 8 ;
+static const uint8_t P9N2_PU_GPE1_PPE_XIRAMDBG_NULL_MSR_SIBRC = 9 ;
+static const uint8_t P9N2_PU_GPE1_PPE_XIRAMDBG_NULL_MSR_SIBRC_LEN = 3 ;
+static const uint8_t P9N2_PU_GPE1_PPE_XIRAMDBG_XSR_DACR = 12 ;
+static const uint8_t P9N2_PU_GPE1_PPE_XIRAMDBG_XSR_DACW = 13 ;
+static const uint8_t P9N2_PU_GPE1_PPE_XIRAMDBG_NULL_MSR_WE = 14 ;
+static const uint8_t P9N2_PU_GPE1_PPE_XIRAMDBG_XSR_TRH = 15 ;
+static const uint8_t P9N2_PU_GPE1_PPE_XIRAMDBG_XSR_SMS = 16 ;
+static const uint8_t P9N2_PU_GPE1_PPE_XIRAMDBG_XSR_SMS_LEN = 4 ;
+static const uint8_t P9N2_PU_GPE1_PPE_XIRAMDBG_NULL_MSR_LP = 20 ;
+static const uint8_t P9N2_PU_GPE1_PPE_XIRAMDBG_XSR_EP = 21 ;
+static const uint8_t P9N2_PU_GPE1_PPE_XIRAMDBG_XSR_PTR = 24 ;
+static const uint8_t P9N2_PU_GPE1_PPE_XIRAMDBG_XSR_ST = 25 ;
+static const uint8_t P9N2_PU_GPE1_PPE_XIRAMDBG_XSR_MFE = 28 ;
+static const uint8_t P9N2_PU_GPE1_PPE_XIRAMDBG_XSR_MCS = 29 ;
+static const uint8_t P9N2_PU_GPE1_PPE_XIRAMDBG_XSR_MCS_LEN = 3 ;
+static const uint8_t P9N2_PU_GPE1_PPE_XIRAMDBG_XIRAMRA_SPRG0 = 32 ;
+static const uint8_t P9N2_PU_GPE1_PPE_XIRAMDBG_XIRAMRA_SPRG0_LEN = 32 ;
+
+static const uint8_t P9N2_PU_GPE1_PPE_XIRAMEDR_XIRAMGA_IR = 0 ;
+static const uint8_t P9N2_PU_GPE1_PPE_XIRAMEDR_XIRAMGA_IR_LEN = 32 ;
+static const uint8_t P9N2_PU_GPE1_PPE_XIRAMEDR_EDR = 32 ;
+static const uint8_t P9N2_PU_GPE1_PPE_XIRAMEDR_EDR_LEN = 32 ;
+
+static const uint8_t P9N2_PU_GPE1_PPE_XIRAMGA_IR = 0 ;
+static const uint8_t P9N2_PU_GPE1_PPE_XIRAMGA_IR_LEN = 32 ;
+static const uint8_t P9N2_PU_GPE1_PPE_XIRAMGA_XIRAMRA_SPRG0 = 32 ;
+static const uint8_t P9N2_PU_GPE1_PPE_XIRAMGA_XIRAMRA_SPRG0_LEN = 32 ;
+
+static const uint8_t P9N2_PU_GPE1_PPE_XIRAMRA_XIXCR_XCR = 1 ;
+static const uint8_t P9N2_PU_GPE1_PPE_XIRAMRA_XIXCR_XCR_LEN = 3 ;
+static const uint8_t P9N2_PU_GPE1_PPE_XIRAMRA_SPRG0 = 32 ;
+static const uint8_t P9N2_PU_GPE1_PPE_XIRAMRA_SPRG0_LEN = 32 ;
+
+static const uint8_t P9N2_PU_GPE1_PPE_XIXCR_XCR = 1 ;
+static const uint8_t P9N2_PU_GPE1_PPE_XIXCR_XCR_LEN = 3 ;
+
+static const uint8_t P9N2_PU_GPE2_GPEDBG_EN_DBG = 0 ;
+static const uint8_t P9N2_PU_GPE2_GPEDBG_HALT_ON_XSTOP = 1 ;
+static const uint8_t P9N2_PU_GPE2_GPEDBG_HALT_ON_TRIG = 2 ;
+static const uint8_t P9N2_PU_GPE2_GPEDBG_RESERVED3 = 3 ;
+static const uint8_t P9N2_PU_GPE2_GPEDBG_EN_INTR_ADDR = 4 ;
+static const uint8_t P9N2_PU_GPE2_GPEDBG_EN_TRACE_EXTRA = 5 ;
+static const uint8_t P9N2_PU_GPE2_GPEDBG_EN_TRACE_STALL = 6 ;
+static const uint8_t P9N2_PU_GPE2_GPEDBG_EN_WAIT_CYCLES = 7 ;
+static const uint8_t P9N2_PU_GPE2_GPEDBG_EN_FULL_SPEED = 8 ;
+static const uint8_t P9N2_PU_GPE2_GPEDBG_RESERVED9 = 9 ;
+static const uint8_t P9N2_PU_GPE2_GPEDBG_TRACE_MODE_SEL = 10 ;
+static const uint8_t P9N2_PU_GPE2_GPEDBG_TRACE_MODE_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_GPE2_GPEDBG_RESERVED12_15 = 12 ;
+static const uint8_t P9N2_PU_GPE2_GPEDBG_RESERVED12_15_LEN = 4 ;
+static const uint8_t P9N2_PU_GPE2_GPEDBG_FIR_TRIGGER = 16 ;
+static const uint8_t P9N2_PU_GPE2_GPEDBG_SPARE = 17 ;
+static const uint8_t P9N2_PU_GPE2_GPEDBG_SPARE_LEN = 3 ;
+static const uint8_t P9N2_PU_GPE2_GPEDBG_TRACE_DATA_SEL = 20 ;
+static const uint8_t P9N2_PU_GPE2_GPEDBG_TRACE_DATA_SEL_LEN = 4 ;
+
+static const uint8_t P9N2_PU_GPE2_GPEIVPR_IVPR = 0 ;
+static const uint8_t P9N2_PU_GPE2_GPEIVPR_IVPR_LEN = 23 ;
+
+static const uint8_t P9N2_PU_GPE2_GPEMACR_MEM_LOW_PRIORITY = 0 ;
+static const uint8_t P9N2_PU_GPE2_GPEMACR_MEM_LOW_PRIORITY_LEN = 2 ;
+static const uint8_t P9N2_PU_GPE2_GPEMACR_MEM_HIGH_PRIORITY = 2 ;
+static const uint8_t P9N2_PU_GPE2_GPEMACR_MEM_HIGH_PRIORITY_LEN = 2 ;
+static const uint8_t P9N2_PU_GPE2_GPEMACR_LOCAL_LOW_PRIORITY = 4 ;
+static const uint8_t P9N2_PU_GPE2_GPEMACR_LOCAL_LOW_PRIORITY_LEN = 2 ;
+static const uint8_t P9N2_PU_GPE2_GPEMACR_LOCAL_HIGH_PRIORITY = 6 ;
+static const uint8_t P9N2_PU_GPE2_GPEMACR_LOCAL_HIGH_PRIORITY_LEN = 2 ;
+static const uint8_t P9N2_PU_GPE2_GPEMACR_SRAM_LOW_PRIORITY = 8 ;
+static const uint8_t P9N2_PU_GPE2_GPEMACR_SRAM_LOW_PRIORITY_LEN = 2 ;
+static const uint8_t P9N2_PU_GPE2_GPEMACR_SRAM_HIGH_PRIORITY = 10 ;
+static const uint8_t P9N2_PU_GPE2_GPEMACR_SRAM_HIGH_PRIORITY_LEN = 2 ;
+
+static const uint8_t P9N2_PU_GPE2_GPENXIXCR_PPE_XIXCR_XCR = 1 ;
+static const uint8_t P9N2_PU_GPE2_GPENXIXCR_PPE_XIXCR_XCR_LEN = 3 ;
+
+static const uint8_t P9N2_PU_GPE2_GPESTR_PBASE = 12 ;
+static const uint8_t P9N2_PU_GPE2_GPESTR_PBASE_LEN = 10 ;
+static const uint8_t P9N2_PU_GPE2_GPESTR_SIZE = 29 ;
+static const uint8_t P9N2_PU_GPE2_GPESTR_SIZE_LEN = 3 ;
+
+static const uint8_t P9N2_PU_GPE2_GPETSEL_WATCHDOG_SEL = 0 ;
+static const uint8_t P9N2_PU_GPE2_GPETSEL_WATCHDOG_SEL_LEN = 4 ;
+static const uint8_t P9N2_PU_GPE2_GPETSEL_FIT_SEL = 4 ;
+static const uint8_t P9N2_PU_GPE2_GPETSEL_FIT_SEL_LEN = 4 ;
+
+static const uint8_t P9N2_PU_GPE2_GPEXIEDR_PPE_XIRAMEDR_EDR = 0 ;
+static const uint8_t P9N2_PU_GPE2_GPEXIEDR_PPE_XIRAMEDR_EDR_LEN = 32 ;
+
+static const uint8_t P9N2_PU_GPE2_GPEXIIAR_IAR = 0 ;
+static const uint8_t P9N2_PU_GPE2_GPEXIIAR_IAR_LEN = 30 ;
+
+static const uint8_t P9N2_PU_GPE2_GPEXIIR_PPE_XIRAMGA_IR = 0 ;
+static const uint8_t P9N2_PU_GPE2_GPEXIIR_PPE_XIRAMGA_IR_LEN = 32 ;
+
+static const uint8_t P9N2_PU_GPE2_GPEXISPRG0_PPE_XIRAMRA_SPRG0 = 0 ;
+static const uint8_t P9N2_PU_GPE2_GPEXISPRG0_PPE_XIRAMRA_SPRG0_LEN = 32 ;
+
+static const uint8_t P9N2_PU_GPE2_GPEXIXCR_PPE_XIXCR_XCR = 1 ;
+static const uint8_t P9N2_PU_GPE2_GPEXIXCR_PPE_XIXCR_XCR_LEN = 3 ;
+
+static const uint8_t P9N2_PU_GPE2_GPEXIXSR_XSR_HS = 0 ;
+static const uint8_t P9N2_PU_GPE2_GPEXIXSR_XSR_HC = 1 ;
+static const uint8_t P9N2_PU_GPE2_GPEXIXSR_XSR_HC_LEN = 3 ;
+static const uint8_t P9N2_PU_GPE2_GPEXIXSR_XSR_HCP = 4 ;
+static const uint8_t P9N2_PU_GPE2_GPEXIXSR_XSR_RIP = 5 ;
+static const uint8_t P9N2_PU_GPE2_GPEXIXSR_XSR_SIP = 6 ;
+static const uint8_t P9N2_PU_GPE2_GPEXIXSR_XSR_TRAP = 7 ;
+static const uint8_t P9N2_PU_GPE2_GPEXIXSR_XSR_IAC = 8 ;
+static const uint8_t P9N2_PU_GPE2_GPEXIXSR_NULL_MSR_SIBRC = 9 ;
+static const uint8_t P9N2_PU_GPE2_GPEXIXSR_NULL_MSR_SIBRC_LEN = 3 ;
+static const uint8_t P9N2_PU_GPE2_GPEXIXSR_XSR_DACR = 12 ;
+static const uint8_t P9N2_PU_GPE2_GPEXIXSR_XSR_DACW = 13 ;
+static const uint8_t P9N2_PU_GPE2_GPEXIXSR_NULL_MSR_WE = 14 ;
+static const uint8_t P9N2_PU_GPE2_GPEXIXSR_XSR_TRH = 15 ;
+static const uint8_t P9N2_PU_GPE2_GPEXIXSR_XSR_SMS = 16 ;
+static const uint8_t P9N2_PU_GPE2_GPEXIXSR_XSR_SMS_LEN = 4 ;
+static const uint8_t P9N2_PU_GPE2_GPEXIXSR_NULL_MSR_LP = 20 ;
+static const uint8_t P9N2_PU_GPE2_GPEXIXSR_XSR_EP = 21 ;
+static const uint8_t P9N2_PU_GPE2_GPEXIXSR_XSR_PTR = 24 ;
+static const uint8_t P9N2_PU_GPE2_GPEXIXSR_XSR_ST = 25 ;
+static const uint8_t P9N2_PU_GPE2_GPEXIXSR_XSR_MFE = 28 ;
+static const uint8_t P9N2_PU_GPE2_GPEXIXSR_XSR_MCS = 29 ;
+static const uint8_t P9N2_PU_GPE2_GPEXIXSR_XSR_MCS_LEN = 3 ;
+
+static const uint8_t P9N2_PU_GPE2_MIB_XIDCAC_DCACHE_TAG_ADDR = 0 ;
+static const uint8_t P9N2_PU_GPE2_MIB_XIDCAC_DCACHE_TAG_ADDR_LEN = 27 ;
+static const uint8_t P9N2_PU_GPE2_MIB_XIDCAC_DCACHE_ERR = 32 ;
+static const uint8_t P9N2_PU_GPE2_MIB_XIDCAC_DCACHE_POPULATE_PENDING = 35 ;
+static const uint8_t P9N2_PU_GPE2_MIB_XIDCAC_DCACHE_VALID = 36 ;
+static const uint8_t P9N2_PU_GPE2_MIB_XIDCAC_DCACHE_VALID_LEN = 2 ;
+
+static const uint8_t P9N2_PU_GPE2_MIB_XIICAC_ICACHE_TAG_ADDR = 0 ;
+static const uint8_t P9N2_PU_GPE2_MIB_XIICAC_ICACHE_TAG_ADDR_LEN = 27 ;
+static const uint8_t P9N2_PU_GPE2_MIB_XIICAC_ICACHE_ERR = 32 ;
+static const uint8_t P9N2_PU_GPE2_MIB_XIICAC_XISIB_PIB_IFETCH_PENDING = 34 ;
+static const uint8_t P9N2_PU_GPE2_MIB_XIICAC_XIMEM_MEM_IFETCH_PENDING = 35 ;
+static const uint8_t P9N2_PU_GPE2_MIB_XIICAC_ICACHE_VALID = 36 ;
+static const uint8_t P9N2_PU_GPE2_MIB_XIICAC_ICACHE_VALID_LEN = 4 ;
+static const uint8_t P9N2_PU_GPE2_MIB_XIICAC_ICACHE_LINE2_VALID = 40 ;
+static const uint8_t P9N2_PU_GPE2_MIB_XIICAC_ICACHE_LINE2_VALID_LEN = 4 ;
+static const uint8_t P9N2_PU_GPE2_MIB_XIICAC_ICACHE_LINE_PTR = 45 ;
+static const uint8_t P9N2_PU_GPE2_MIB_XIICAC_ICACHE_LINE2_ERR = 46 ;
+static const uint8_t P9N2_PU_GPE2_MIB_XIICAC_ICACHE_PREFETCH_PENDING = 47 ;
+
+static const uint8_t P9N2_PU_GPE2_MIB_XIMEM_MEM_ADDR = 0 ;
+static const uint8_t P9N2_PU_GPE2_MIB_XIMEM_MEM_ADDR_LEN = 32 ;
+static const uint8_t P9N2_PU_GPE2_MIB_XIMEM_MEM_R_NW = 32 ;
+static const uint8_t P9N2_PU_GPE2_MIB_XIMEM_MEM_BUSY = 33 ;
+static const uint8_t P9N2_PU_GPE2_MIB_XIMEM_MEM_IMPRECISE_ERROR_PENDING = 34 ;
+static const uint8_t P9N2_PU_GPE2_MIB_XIMEM_MEM_BYTE_ENABLE = 35 ;
+static const uint8_t P9N2_PU_GPE2_MIB_XIMEM_MEM_BYTE_ENABLE_LEN = 8 ;
+static const uint8_t P9N2_PU_GPE2_MIB_XIMEM_MEM_LINE_MODE = 43 ;
+static const uint8_t P9N2_PU_GPE2_MIB_XIMEM_MEM_ERROR = 49 ;
+static const uint8_t P9N2_PU_GPE2_MIB_XIMEM_MEM_ERROR_LEN = 3 ;
+static const uint8_t P9N2_PU_GPE2_MIB_XIMEM_MEM_IFETCH_PENDING = 62 ;
+static const uint8_t P9N2_PU_GPE2_MIB_XIMEM_MEM_DATAOP_PENDING = 63 ;
+
+static const uint8_t P9N2_PU_GPE2_MIB_XISGB_STORE_ADDRESS = 0 ;
+static const uint8_t P9N2_PU_GPE2_MIB_XISGB_STORE_ADDRESS_LEN = 32 ;
+static const uint8_t P9N2_PU_GPE2_MIB_XISGB_XIMEM_MEM_IMPRECISE_ERROR_PENDING = 35 ;
+static const uint8_t P9N2_PU_GPE2_MIB_XISGB_SGB_BYTE_VALID = 36 ;
+static const uint8_t P9N2_PU_GPE2_MIB_XISGB_SGB_BYTE_VALID_LEN = 4 ;
+static const uint8_t P9N2_PU_GPE2_MIB_XISGB_SGB_FLUSH_PENDING = 63 ;
+
+static const uint8_t P9N2_PU_GPE2_MIB_XISIB_PIB_ADDR = 0 ;
+static const uint8_t P9N2_PU_GPE2_MIB_XISIB_PIB_ADDR_LEN = 32 ;
+static const uint8_t P9N2_PU_GPE2_MIB_XISIB_PIB_R_NW = 32 ;
+static const uint8_t P9N2_PU_GPE2_MIB_XISIB_PIB_BUSY = 33 ;
+static const uint8_t P9N2_PU_GPE2_MIB_XISIB_PIB_IMPRECISE_ERROR_PENDING = 34 ;
+static const uint8_t P9N2_PU_GPE2_MIB_XISIB_PIB_RSP_INFO = 49 ;
+static const uint8_t P9N2_PU_GPE2_MIB_XISIB_PIB_RSP_INFO_LEN = 3 ;
+static const uint8_t P9N2_PU_GPE2_MIB_XISIB_PIB_IFETCH_PENDING = 62 ;
+static const uint8_t P9N2_PU_GPE2_MIB_XISIB_PIB_DATAOP_PENDING = 63 ;
+
+static const uint8_t P9N2_PU_GPE2_PPE_XIDBGPRO_XSR_HS = 0 ;
+static const uint8_t P9N2_PU_GPE2_PPE_XIDBGPRO_XSR_HC = 1 ;
+static const uint8_t P9N2_PU_GPE2_PPE_XIDBGPRO_XSR_HC_LEN = 3 ;
+static const uint8_t P9N2_PU_GPE2_PPE_XIDBGPRO_XSR_HCP = 4 ;
+static const uint8_t P9N2_PU_GPE2_PPE_XIDBGPRO_XSR_RIP = 5 ;
+static const uint8_t P9N2_PU_GPE2_PPE_XIDBGPRO_XSR_SIP = 6 ;
+static const uint8_t P9N2_PU_GPE2_PPE_XIDBGPRO_XSR_TRAP = 7 ;
+static const uint8_t P9N2_PU_GPE2_PPE_XIDBGPRO_XSR_IAC = 8 ;
+static const uint8_t P9N2_PU_GPE2_PPE_XIDBGPRO_NULL_MSR_SIBRC = 9 ;
+static const uint8_t P9N2_PU_GPE2_PPE_XIDBGPRO_NULL_MSR_SIBRC_LEN = 3 ;
+static const uint8_t P9N2_PU_GPE2_PPE_XIDBGPRO_XSR_DACR = 12 ;
+static const uint8_t P9N2_PU_GPE2_PPE_XIDBGPRO_XSR_DACW = 13 ;
+static const uint8_t P9N2_PU_GPE2_PPE_XIDBGPRO_NULL_MSR_WE = 14 ;
+static const uint8_t P9N2_PU_GPE2_PPE_XIDBGPRO_XSR_TRH = 15 ;
+static const uint8_t P9N2_PU_GPE2_PPE_XIDBGPRO_XSR_SMS = 16 ;
+static const uint8_t P9N2_PU_GPE2_PPE_XIDBGPRO_XSR_SMS_LEN = 4 ;
+static const uint8_t P9N2_PU_GPE2_PPE_XIDBGPRO_NULL_MSR_LP = 20 ;
+static const uint8_t P9N2_PU_GPE2_PPE_XIDBGPRO_XSR_EP = 21 ;
+static const uint8_t P9N2_PU_GPE2_PPE_XIDBGPRO_XSR_PTR = 24 ;
+static const uint8_t P9N2_PU_GPE2_PPE_XIDBGPRO_XSR_ST = 25 ;
+static const uint8_t P9N2_PU_GPE2_PPE_XIDBGPRO_XSR_MFE = 28 ;
+static const uint8_t P9N2_PU_GPE2_PPE_XIDBGPRO_XSR_MCS = 29 ;
+static const uint8_t P9N2_PU_GPE2_PPE_XIDBGPRO_XSR_MCS_LEN = 3 ;
+static const uint8_t P9N2_PU_GPE2_PPE_XIDBGPRO_IAR = 32 ;
+static const uint8_t P9N2_PU_GPE2_PPE_XIDBGPRO_IAR_LEN = 30 ;
+
+static const uint8_t P9N2_PU_GPE2_PPE_XIRAMDBG_XSR_HS = 0 ;
+static const uint8_t P9N2_PU_GPE2_PPE_XIRAMDBG_XSR_HC = 1 ;
+static const uint8_t P9N2_PU_GPE2_PPE_XIRAMDBG_XSR_HC_LEN = 3 ;
+static const uint8_t P9N2_PU_GPE2_PPE_XIRAMDBG_XSR_HCP = 4 ;
+static const uint8_t P9N2_PU_GPE2_PPE_XIRAMDBG_XSR_RIP = 5 ;
+static const uint8_t P9N2_PU_GPE2_PPE_XIRAMDBG_XSR_SIP = 6 ;
+static const uint8_t P9N2_PU_GPE2_PPE_XIRAMDBG_XSR_TRAP = 7 ;
+static const uint8_t P9N2_PU_GPE2_PPE_XIRAMDBG_XSR_IAC = 8 ;
+static const uint8_t P9N2_PU_GPE2_PPE_XIRAMDBG_NULL_MSR_SIBRC = 9 ;
+static const uint8_t P9N2_PU_GPE2_PPE_XIRAMDBG_NULL_MSR_SIBRC_LEN = 3 ;
+static const uint8_t P9N2_PU_GPE2_PPE_XIRAMDBG_XSR_DACR = 12 ;
+static const uint8_t P9N2_PU_GPE2_PPE_XIRAMDBG_XSR_DACW = 13 ;
+static const uint8_t P9N2_PU_GPE2_PPE_XIRAMDBG_NULL_MSR_WE = 14 ;
+static const uint8_t P9N2_PU_GPE2_PPE_XIRAMDBG_XSR_TRH = 15 ;
+static const uint8_t P9N2_PU_GPE2_PPE_XIRAMDBG_XSR_SMS = 16 ;
+static const uint8_t P9N2_PU_GPE2_PPE_XIRAMDBG_XSR_SMS_LEN = 4 ;
+static const uint8_t P9N2_PU_GPE2_PPE_XIRAMDBG_NULL_MSR_LP = 20 ;
+static const uint8_t P9N2_PU_GPE2_PPE_XIRAMDBG_XSR_EP = 21 ;
+static const uint8_t P9N2_PU_GPE2_PPE_XIRAMDBG_XSR_PTR = 24 ;
+static const uint8_t P9N2_PU_GPE2_PPE_XIRAMDBG_XSR_ST = 25 ;
+static const uint8_t P9N2_PU_GPE2_PPE_XIRAMDBG_XSR_MFE = 28 ;
+static const uint8_t P9N2_PU_GPE2_PPE_XIRAMDBG_XSR_MCS = 29 ;
+static const uint8_t P9N2_PU_GPE2_PPE_XIRAMDBG_XSR_MCS_LEN = 3 ;
+static const uint8_t P9N2_PU_GPE2_PPE_XIRAMDBG_XIRAMRA_SPRG0 = 32 ;
+static const uint8_t P9N2_PU_GPE2_PPE_XIRAMDBG_XIRAMRA_SPRG0_LEN = 32 ;
+
+static const uint8_t P9N2_PU_GPE2_PPE_XIRAMEDR_XIRAMGA_IR = 0 ;
+static const uint8_t P9N2_PU_GPE2_PPE_XIRAMEDR_XIRAMGA_IR_LEN = 32 ;
+static const uint8_t P9N2_PU_GPE2_PPE_XIRAMEDR_EDR = 32 ;
+static const uint8_t P9N2_PU_GPE2_PPE_XIRAMEDR_EDR_LEN = 32 ;
+
+static const uint8_t P9N2_PU_GPE2_PPE_XIRAMGA_IR = 0 ;
+static const uint8_t P9N2_PU_GPE2_PPE_XIRAMGA_IR_LEN = 32 ;
+static const uint8_t P9N2_PU_GPE2_PPE_XIRAMGA_XIRAMRA_SPRG0 = 32 ;
+static const uint8_t P9N2_PU_GPE2_PPE_XIRAMGA_XIRAMRA_SPRG0_LEN = 32 ;
+
+static const uint8_t P9N2_PU_GPE2_PPE_XIRAMRA_XIXCR_XCR = 1 ;
+static const uint8_t P9N2_PU_GPE2_PPE_XIRAMRA_XIXCR_XCR_LEN = 3 ;
+static const uint8_t P9N2_PU_GPE2_PPE_XIRAMRA_SPRG0 = 32 ;
+static const uint8_t P9N2_PU_GPE2_PPE_XIRAMRA_SPRG0_LEN = 32 ;
+
+static const uint8_t P9N2_PU_GPE2_PPE_XIXCR_XCR = 1 ;
+static const uint8_t P9N2_PU_GPE2_PPE_XIXCR_XCR_LEN = 3 ;
+
+static const uint8_t P9N2_PU_GPE3_GPEDBG_EN_DBG = 0 ;
+static const uint8_t P9N2_PU_GPE3_GPEDBG_HALT_ON_XSTOP = 1 ;
+static const uint8_t P9N2_PU_GPE3_GPEDBG_HALT_ON_TRIG = 2 ;
+static const uint8_t P9N2_PU_GPE3_GPEDBG_RESERVED3 = 3 ;
+static const uint8_t P9N2_PU_GPE3_GPEDBG_EN_INTR_ADDR = 4 ;
+static const uint8_t P9N2_PU_GPE3_GPEDBG_EN_TRACE_EXTRA = 5 ;
+static const uint8_t P9N2_PU_GPE3_GPEDBG_EN_TRACE_STALL = 6 ;
+static const uint8_t P9N2_PU_GPE3_GPEDBG_EN_WAIT_CYCLES = 7 ;
+static const uint8_t P9N2_PU_GPE3_GPEDBG_EN_FULL_SPEED = 8 ;
+static const uint8_t P9N2_PU_GPE3_GPEDBG_RESERVED9 = 9 ;
+static const uint8_t P9N2_PU_GPE3_GPEDBG_TRACE_MODE_SEL = 10 ;
+static const uint8_t P9N2_PU_GPE3_GPEDBG_TRACE_MODE_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_GPE3_GPEDBG_RESERVED12_15 = 12 ;
+static const uint8_t P9N2_PU_GPE3_GPEDBG_RESERVED12_15_LEN = 4 ;
+static const uint8_t P9N2_PU_GPE3_GPEDBG_FIR_TRIGGER = 16 ;
+static const uint8_t P9N2_PU_GPE3_GPEDBG_SPARE = 17 ;
+static const uint8_t P9N2_PU_GPE3_GPEDBG_SPARE_LEN = 3 ;
+static const uint8_t P9N2_PU_GPE3_GPEDBG_TRACE_DATA_SEL = 20 ;
+static const uint8_t P9N2_PU_GPE3_GPEDBG_TRACE_DATA_SEL_LEN = 4 ;
+
+static const uint8_t P9N2_PU_GPE3_GPEIVPR_IVPR = 0 ;
+static const uint8_t P9N2_PU_GPE3_GPEIVPR_IVPR_LEN = 23 ;
+
+static const uint8_t P9N2_PU_GPE3_GPEMACR_MEM_LOW_PRIORITY = 0 ;
+static const uint8_t P9N2_PU_GPE3_GPEMACR_MEM_LOW_PRIORITY_LEN = 2 ;
+static const uint8_t P9N2_PU_GPE3_GPEMACR_MEM_HIGH_PRIORITY = 2 ;
+static const uint8_t P9N2_PU_GPE3_GPEMACR_MEM_HIGH_PRIORITY_LEN = 2 ;
+static const uint8_t P9N2_PU_GPE3_GPEMACR_LOCAL_LOW_PRIORITY = 4 ;
+static const uint8_t P9N2_PU_GPE3_GPEMACR_LOCAL_LOW_PRIORITY_LEN = 2 ;
+static const uint8_t P9N2_PU_GPE3_GPEMACR_LOCAL_HIGH_PRIORITY = 6 ;
+static const uint8_t P9N2_PU_GPE3_GPEMACR_LOCAL_HIGH_PRIORITY_LEN = 2 ;
+static const uint8_t P9N2_PU_GPE3_GPEMACR_SRAM_LOW_PRIORITY = 8 ;
+static const uint8_t P9N2_PU_GPE3_GPEMACR_SRAM_LOW_PRIORITY_LEN = 2 ;
+static const uint8_t P9N2_PU_GPE3_GPEMACR_SRAM_HIGH_PRIORITY = 10 ;
+static const uint8_t P9N2_PU_GPE3_GPEMACR_SRAM_HIGH_PRIORITY_LEN = 2 ;
+
+static const uint8_t P9N2_PU_GPE3_GPENXIXCR_PPE_XIXCR_XCR = 1 ;
+static const uint8_t P9N2_PU_GPE3_GPENXIXCR_PPE_XIXCR_XCR_LEN = 3 ;
+
+static const uint8_t P9N2_PU_GPE3_GPESTR_PBASE = 12 ;
+static const uint8_t P9N2_PU_GPE3_GPESTR_PBASE_LEN = 10 ;
+static const uint8_t P9N2_PU_GPE3_GPESTR_SIZE = 29 ;
+static const uint8_t P9N2_PU_GPE3_GPESTR_SIZE_LEN = 3 ;
+
+static const uint8_t P9N2_PU_GPE3_GPETSEL_WATCHDOG_SEL = 0 ;
+static const uint8_t P9N2_PU_GPE3_GPETSEL_WATCHDOG_SEL_LEN = 4 ;
+static const uint8_t P9N2_PU_GPE3_GPETSEL_FIT_SEL = 4 ;
+static const uint8_t P9N2_PU_GPE3_GPETSEL_FIT_SEL_LEN = 4 ;
+
+static const uint8_t P9N2_PU_GPE3_GPEXIEDR_PPE_XIRAMEDR_EDR = 0 ;
+static const uint8_t P9N2_PU_GPE3_GPEXIEDR_PPE_XIRAMEDR_EDR_LEN = 32 ;
+
+static const uint8_t P9N2_PU_GPE3_GPEXIIAR_IAR = 0 ;
+static const uint8_t P9N2_PU_GPE3_GPEXIIAR_IAR_LEN = 30 ;
+
+static const uint8_t P9N2_PU_GPE3_GPEXIIR_PPE_XIRAMGA_IR = 0 ;
+static const uint8_t P9N2_PU_GPE3_GPEXIIR_PPE_XIRAMGA_IR_LEN = 32 ;
+
+static const uint8_t P9N2_PU_GPE3_GPEXISPRG0_PPE_XIRAMRA_SPRG0 = 0 ;
+static const uint8_t P9N2_PU_GPE3_GPEXISPRG0_PPE_XIRAMRA_SPRG0_LEN = 32 ;
+
+static const uint8_t P9N2_PU_GPE3_GPEXIXCR_PPE_XIXCR_XCR = 1 ;
+static const uint8_t P9N2_PU_GPE3_GPEXIXCR_PPE_XIXCR_XCR_LEN = 3 ;
+
+static const uint8_t P9N2_PU_GPE3_GPEXIXSR_XSR_HS = 0 ;
+static const uint8_t P9N2_PU_GPE3_GPEXIXSR_XSR_HC = 1 ;
+static const uint8_t P9N2_PU_GPE3_GPEXIXSR_XSR_HC_LEN = 3 ;
+static const uint8_t P9N2_PU_GPE3_GPEXIXSR_XSR_HCP = 4 ;
+static const uint8_t P9N2_PU_GPE3_GPEXIXSR_XSR_RIP = 5 ;
+static const uint8_t P9N2_PU_GPE3_GPEXIXSR_XSR_SIP = 6 ;
+static const uint8_t P9N2_PU_GPE3_GPEXIXSR_XSR_TRAP = 7 ;
+static const uint8_t P9N2_PU_GPE3_GPEXIXSR_XSR_IAC = 8 ;
+static const uint8_t P9N2_PU_GPE3_GPEXIXSR_NULL_MSR_SIBRC = 9 ;
+static const uint8_t P9N2_PU_GPE3_GPEXIXSR_NULL_MSR_SIBRC_LEN = 3 ;
+static const uint8_t P9N2_PU_GPE3_GPEXIXSR_XSR_DACR = 12 ;
+static const uint8_t P9N2_PU_GPE3_GPEXIXSR_XSR_DACW = 13 ;
+static const uint8_t P9N2_PU_GPE3_GPEXIXSR_NULL_MSR_WE = 14 ;
+static const uint8_t P9N2_PU_GPE3_GPEXIXSR_XSR_TRH = 15 ;
+static const uint8_t P9N2_PU_GPE3_GPEXIXSR_XSR_SMS = 16 ;
+static const uint8_t P9N2_PU_GPE3_GPEXIXSR_XSR_SMS_LEN = 4 ;
+static const uint8_t P9N2_PU_GPE3_GPEXIXSR_NULL_MSR_LP = 20 ;
+static const uint8_t P9N2_PU_GPE3_GPEXIXSR_XSR_EP = 21 ;
+static const uint8_t P9N2_PU_GPE3_GPEXIXSR_XSR_PTR = 24 ;
+static const uint8_t P9N2_PU_GPE3_GPEXIXSR_XSR_ST = 25 ;
+static const uint8_t P9N2_PU_GPE3_GPEXIXSR_XSR_MFE = 28 ;
+static const uint8_t P9N2_PU_GPE3_GPEXIXSR_XSR_MCS = 29 ;
+static const uint8_t P9N2_PU_GPE3_GPEXIXSR_XSR_MCS_LEN = 3 ;
+
+static const uint8_t P9N2_PU_GPE3_MIB_XIDCAC_DCACHE_TAG_ADDR = 0 ;
+static const uint8_t P9N2_PU_GPE3_MIB_XIDCAC_DCACHE_TAG_ADDR_LEN = 27 ;
+static const uint8_t P9N2_PU_GPE3_MIB_XIDCAC_DCACHE_ERR = 32 ;
+static const uint8_t P9N2_PU_GPE3_MIB_XIDCAC_DCACHE_POPULATE_PENDING = 35 ;
+static const uint8_t P9N2_PU_GPE3_MIB_XIDCAC_DCACHE_VALID = 36 ;
+static const uint8_t P9N2_PU_GPE3_MIB_XIDCAC_DCACHE_VALID_LEN = 2 ;
+
+static const uint8_t P9N2_PU_GPE3_MIB_XIICAC_ICACHE_TAG_ADDR = 0 ;
+static const uint8_t P9N2_PU_GPE3_MIB_XIICAC_ICACHE_TAG_ADDR_LEN = 27 ;
+static const uint8_t P9N2_PU_GPE3_MIB_XIICAC_ICACHE_ERR = 32 ;
+static const uint8_t P9N2_PU_GPE3_MIB_XIICAC_XISIB_PIB_IFETCH_PENDING = 34 ;
+static const uint8_t P9N2_PU_GPE3_MIB_XIICAC_XIMEM_MEM_IFETCH_PENDING = 35 ;
+static const uint8_t P9N2_PU_GPE3_MIB_XIICAC_ICACHE_VALID = 36 ;
+static const uint8_t P9N2_PU_GPE3_MIB_XIICAC_ICACHE_VALID_LEN = 4 ;
+static const uint8_t P9N2_PU_GPE3_MIB_XIICAC_ICACHE_LINE2_VALID = 40 ;
+static const uint8_t P9N2_PU_GPE3_MIB_XIICAC_ICACHE_LINE2_VALID_LEN = 4 ;
+static const uint8_t P9N2_PU_GPE3_MIB_XIICAC_ICACHE_LINE_PTR = 45 ;
+static const uint8_t P9N2_PU_GPE3_MIB_XIICAC_ICACHE_LINE2_ERR = 46 ;
+static const uint8_t P9N2_PU_GPE3_MIB_XIICAC_ICACHE_PREFETCH_PENDING = 47 ;
+
+static const uint8_t P9N2_PU_GPE3_MIB_XIMEM_MEM_ADDR = 0 ;
+static const uint8_t P9N2_PU_GPE3_MIB_XIMEM_MEM_ADDR_LEN = 32 ;
+static const uint8_t P9N2_PU_GPE3_MIB_XIMEM_MEM_R_NW = 32 ;
+static const uint8_t P9N2_PU_GPE3_MIB_XIMEM_MEM_BUSY = 33 ;
+static const uint8_t P9N2_PU_GPE3_MIB_XIMEM_MEM_IMPRECISE_ERROR_PENDING = 34 ;
+static const uint8_t P9N2_PU_GPE3_MIB_XIMEM_MEM_BYTE_ENABLE = 35 ;
+static const uint8_t P9N2_PU_GPE3_MIB_XIMEM_MEM_BYTE_ENABLE_LEN = 8 ;
+static const uint8_t P9N2_PU_GPE3_MIB_XIMEM_MEM_LINE_MODE = 43 ;
+static const uint8_t P9N2_PU_GPE3_MIB_XIMEM_MEM_ERROR = 49 ;
+static const uint8_t P9N2_PU_GPE3_MIB_XIMEM_MEM_ERROR_LEN = 3 ;
+static const uint8_t P9N2_PU_GPE3_MIB_XIMEM_MEM_IFETCH_PENDING = 62 ;
+static const uint8_t P9N2_PU_GPE3_MIB_XIMEM_MEM_DATAOP_PENDING = 63 ;
+
+static const uint8_t P9N2_PU_GPE3_MIB_XISGB_STORE_ADDRESS = 0 ;
+static const uint8_t P9N2_PU_GPE3_MIB_XISGB_STORE_ADDRESS_LEN = 32 ;
+static const uint8_t P9N2_PU_GPE3_MIB_XISGB_XIMEM_MEM_IMPRECISE_ERROR_PENDING = 35 ;
+static const uint8_t P9N2_PU_GPE3_MIB_XISGB_SGB_BYTE_VALID = 36 ;
+static const uint8_t P9N2_PU_GPE3_MIB_XISGB_SGB_BYTE_VALID_LEN = 4 ;
+static const uint8_t P9N2_PU_GPE3_MIB_XISGB_SGB_FLUSH_PENDING = 63 ;
+
+static const uint8_t P9N2_PU_GPE3_MIB_XISIB_PIB_ADDR = 0 ;
+static const uint8_t P9N2_PU_GPE3_MIB_XISIB_PIB_ADDR_LEN = 32 ;
+static const uint8_t P9N2_PU_GPE3_MIB_XISIB_PIB_R_NW = 32 ;
+static const uint8_t P9N2_PU_GPE3_MIB_XISIB_PIB_BUSY = 33 ;
+static const uint8_t P9N2_PU_GPE3_MIB_XISIB_PIB_IMPRECISE_ERROR_PENDING = 34 ;
+static const uint8_t P9N2_PU_GPE3_MIB_XISIB_PIB_RSP_INFO = 49 ;
+static const uint8_t P9N2_PU_GPE3_MIB_XISIB_PIB_RSP_INFO_LEN = 3 ;
+static const uint8_t P9N2_PU_GPE3_MIB_XISIB_PIB_IFETCH_PENDING = 62 ;
+static const uint8_t P9N2_PU_GPE3_MIB_XISIB_PIB_DATAOP_PENDING = 63 ;
+
+static const uint8_t P9N2_PU_GPE3_PPE_XIDBGPRO_XSR_HS = 0 ;
+static const uint8_t P9N2_PU_GPE3_PPE_XIDBGPRO_XSR_HC = 1 ;
+static const uint8_t P9N2_PU_GPE3_PPE_XIDBGPRO_XSR_HC_LEN = 3 ;
+static const uint8_t P9N2_PU_GPE3_PPE_XIDBGPRO_XSR_HCP = 4 ;
+static const uint8_t P9N2_PU_GPE3_PPE_XIDBGPRO_XSR_RIP = 5 ;
+static const uint8_t P9N2_PU_GPE3_PPE_XIDBGPRO_XSR_SIP = 6 ;
+static const uint8_t P9N2_PU_GPE3_PPE_XIDBGPRO_XSR_TRAP = 7 ;
+static const uint8_t P9N2_PU_GPE3_PPE_XIDBGPRO_XSR_IAC = 8 ;
+static const uint8_t P9N2_PU_GPE3_PPE_XIDBGPRO_NULL_MSR_SIBRC = 9 ;
+static const uint8_t P9N2_PU_GPE3_PPE_XIDBGPRO_NULL_MSR_SIBRC_LEN = 3 ;
+static const uint8_t P9N2_PU_GPE3_PPE_XIDBGPRO_XSR_DACR = 12 ;
+static const uint8_t P9N2_PU_GPE3_PPE_XIDBGPRO_XSR_DACW = 13 ;
+static const uint8_t P9N2_PU_GPE3_PPE_XIDBGPRO_NULL_MSR_WE = 14 ;
+static const uint8_t P9N2_PU_GPE3_PPE_XIDBGPRO_XSR_TRH = 15 ;
+static const uint8_t P9N2_PU_GPE3_PPE_XIDBGPRO_XSR_SMS = 16 ;
+static const uint8_t P9N2_PU_GPE3_PPE_XIDBGPRO_XSR_SMS_LEN = 4 ;
+static const uint8_t P9N2_PU_GPE3_PPE_XIDBGPRO_NULL_MSR_LP = 20 ;
+static const uint8_t P9N2_PU_GPE3_PPE_XIDBGPRO_XSR_EP = 21 ;
+static const uint8_t P9N2_PU_GPE3_PPE_XIDBGPRO_XSR_PTR = 24 ;
+static const uint8_t P9N2_PU_GPE3_PPE_XIDBGPRO_XSR_ST = 25 ;
+static const uint8_t P9N2_PU_GPE3_PPE_XIDBGPRO_XSR_MFE = 28 ;
+static const uint8_t P9N2_PU_GPE3_PPE_XIDBGPRO_XSR_MCS = 29 ;
+static const uint8_t P9N2_PU_GPE3_PPE_XIDBGPRO_XSR_MCS_LEN = 3 ;
+static const uint8_t P9N2_PU_GPE3_PPE_XIDBGPRO_IAR = 32 ;
+static const uint8_t P9N2_PU_GPE3_PPE_XIDBGPRO_IAR_LEN = 30 ;
+
+static const uint8_t P9N2_PU_GPE3_PPE_XIRAMDBG_XSR_HS = 0 ;
+static const uint8_t P9N2_PU_GPE3_PPE_XIRAMDBG_XSR_HC = 1 ;
+static const uint8_t P9N2_PU_GPE3_PPE_XIRAMDBG_XSR_HC_LEN = 3 ;
+static const uint8_t P9N2_PU_GPE3_PPE_XIRAMDBG_XSR_HCP = 4 ;
+static const uint8_t P9N2_PU_GPE3_PPE_XIRAMDBG_XSR_RIP = 5 ;
+static const uint8_t P9N2_PU_GPE3_PPE_XIRAMDBG_XSR_SIP = 6 ;
+static const uint8_t P9N2_PU_GPE3_PPE_XIRAMDBG_XSR_TRAP = 7 ;
+static const uint8_t P9N2_PU_GPE3_PPE_XIRAMDBG_XSR_IAC = 8 ;
+static const uint8_t P9N2_PU_GPE3_PPE_XIRAMDBG_NULL_MSR_SIBRC = 9 ;
+static const uint8_t P9N2_PU_GPE3_PPE_XIRAMDBG_NULL_MSR_SIBRC_LEN = 3 ;
+static const uint8_t P9N2_PU_GPE3_PPE_XIRAMDBG_XSR_DACR = 12 ;
+static const uint8_t P9N2_PU_GPE3_PPE_XIRAMDBG_XSR_DACW = 13 ;
+static const uint8_t P9N2_PU_GPE3_PPE_XIRAMDBG_NULL_MSR_WE = 14 ;
+static const uint8_t P9N2_PU_GPE3_PPE_XIRAMDBG_XSR_TRH = 15 ;
+static const uint8_t P9N2_PU_GPE3_PPE_XIRAMDBG_XSR_SMS = 16 ;
+static const uint8_t P9N2_PU_GPE3_PPE_XIRAMDBG_XSR_SMS_LEN = 4 ;
+static const uint8_t P9N2_PU_GPE3_PPE_XIRAMDBG_NULL_MSR_LP = 20 ;
+static const uint8_t P9N2_PU_GPE3_PPE_XIRAMDBG_XSR_EP = 21 ;
+static const uint8_t P9N2_PU_GPE3_PPE_XIRAMDBG_XSR_PTR = 24 ;
+static const uint8_t P9N2_PU_GPE3_PPE_XIRAMDBG_XSR_ST = 25 ;
+static const uint8_t P9N2_PU_GPE3_PPE_XIRAMDBG_XSR_MFE = 28 ;
+static const uint8_t P9N2_PU_GPE3_PPE_XIRAMDBG_XSR_MCS = 29 ;
+static const uint8_t P9N2_PU_GPE3_PPE_XIRAMDBG_XSR_MCS_LEN = 3 ;
+static const uint8_t P9N2_PU_GPE3_PPE_XIRAMDBG_XIRAMRA_SPRG0 = 32 ;
+static const uint8_t P9N2_PU_GPE3_PPE_XIRAMDBG_XIRAMRA_SPRG0_LEN = 32 ;
+
+static const uint8_t P9N2_PU_GPE3_PPE_XIRAMEDR_XIRAMGA_IR = 0 ;
+static const uint8_t P9N2_PU_GPE3_PPE_XIRAMEDR_XIRAMGA_IR_LEN = 32 ;
+static const uint8_t P9N2_PU_GPE3_PPE_XIRAMEDR_EDR = 32 ;
+static const uint8_t P9N2_PU_GPE3_PPE_XIRAMEDR_EDR_LEN = 32 ;
+
+static const uint8_t P9N2_PU_GPE3_PPE_XIRAMGA_IR = 0 ;
+static const uint8_t P9N2_PU_GPE3_PPE_XIRAMGA_IR_LEN = 32 ;
+static const uint8_t P9N2_PU_GPE3_PPE_XIRAMGA_XIRAMRA_SPRG0 = 32 ;
+static const uint8_t P9N2_PU_GPE3_PPE_XIRAMGA_XIRAMRA_SPRG0_LEN = 32 ;
+
+static const uint8_t P9N2_PU_GPE3_PPE_XIRAMRA_XIXCR_XCR = 1 ;
+static const uint8_t P9N2_PU_GPE3_PPE_XIRAMRA_XIXCR_XCR_LEN = 3 ;
+static const uint8_t P9N2_PU_GPE3_PPE_XIRAMRA_SPRG0 = 32 ;
+static const uint8_t P9N2_PU_GPE3_PPE_XIRAMRA_SPRG0_LEN = 32 ;
+
+static const uint8_t P9N2_PU_GPE3_PPE_XIXCR_XCR = 1 ;
+static const uint8_t P9N2_PU_GPE3_PPE_XIXCR_XCR_LEN = 3 ;
+
+static const uint8_t P9N2_PU_GPIO_INPUT_DIN_0 = 0 ;
+static const uint8_t P9N2_PU_GPIO_INPUT_DIN_1 = 1 ;
+static const uint8_t P9N2_PU_GPIO_INPUT_DIN_2 = 2 ;
+
+static const uint8_t P9N2_PU_GPIO_INT_COND_INT_COND_0 = 0 ;
+static const uint8_t P9N2_PU_GPIO_INT_COND_INT_COND_1 = 1 ;
+static const uint8_t P9N2_PU_GPIO_INT_COND_INT_COND_2 = 2 ;
+
+static const uint8_t P9N2_PU_GPIO_INT_ENABLE_EN_0 = 0 ;
+static const uint8_t P9N2_PU_GPIO_INT_ENABLE_EN_1 = 1 ;
+static const uint8_t P9N2_PU_GPIO_INT_ENABLE_EN_2 = 2 ;
+
+static const uint8_t P9N2_PU_GPIO_INT_POLARITY_POL_0 = 0 ;
+static const uint8_t P9N2_PU_GPIO_INT_POLARITY_POL_1 = 1 ;
+static const uint8_t P9N2_PU_GPIO_INT_POLARITY_POL_2 = 2 ;
+
+static const uint8_t P9N2_PU_GPIO_INT_STATUS_STAT_0 = 0 ;
+static const uint8_t P9N2_PU_GPIO_INT_STATUS_STAT_1 = 1 ;
+static const uint8_t P9N2_PU_GPIO_INT_STATUS_STAT_2 = 2 ;
+
+static const uint8_t P9N2_PU_GPIO_OUTPUT_DO_0 = 0 ;
+static const uint8_t P9N2_PU_GPIO_OUTPUT_DO_1 = 1 ;
+static const uint8_t P9N2_PU_GPIO_OUTPUT_DO_2 = 2 ;
+
+static const uint8_t P9N2_PU_GPIO_OUTPUT_EN_DO_0 = 0 ;
+static const uint8_t P9N2_PU_GPIO_OUTPUT_EN_DO_1 = 1 ;
+static const uint8_t P9N2_PU_GPIO_OUTPUT_EN_DO_2 = 2 ;
+
+static const uint8_t P9N2_PU_NPU0_SM0_GPU0_BAR_CONFIG_MEMSELMATCH = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM0_GPU0_BAR_CONFIG_MEMSELMATCH_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM0_GPU0_BAR_CONFIG_GROUP = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM0_GPU0_BAR_CONFIG_GROUP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM0_GPU0_BAR_CONFIG_CHIP = 7 ;
+static const uint8_t P9N2_PU_NPU0_SM0_GPU0_BAR_CONFIG_CHIP_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM0_GPU0_BAR_CONFIG_ADDR = 10 ;
+static const uint8_t P9N2_PU_NPU0_SM0_GPU0_BAR_CONFIG_ADDR_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU0_SM0_GPU0_BAR_CONFIG_POISON = 22 ;
+static const uint8_t P9N2_PU_NPU0_SM0_GPU0_BAR_CONFIG_GRANULE = 23 ;
+static const uint8_t P9N2_PU_NPU0_SM0_GPU0_BAR_CONFIG_SIZE = 24 ;
+static const uint8_t P9N2_PU_NPU0_SM0_GPU0_BAR_CONFIG_SIZE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM0_GPU0_BAR_CONFIG_MODE = 28 ;
+static const uint8_t P9N2_PU_NPU0_SM0_GPU0_BAR_CONFIG_MODE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM0_GPU0_BAR_CONFIG_RESERVED2 = 32 ;
+static const uint8_t P9N2_PU_NPU0_SM0_GPU0_BAR_CONFIG_MASK = 33 ;
+static const uint8_t P9N2_PU_NPU0_SM0_GPU0_BAR_CONFIG_MASK_LEN = 7 ;
+
+static const uint8_t P9N2_PU_NPU2_SM3_GPU0_BAR_CONFIG_MEMSELMATCH = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM3_GPU0_BAR_CONFIG_MEMSELMATCH_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM3_GPU0_BAR_CONFIG_GROUP = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM3_GPU0_BAR_CONFIG_GROUP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM3_GPU0_BAR_CONFIG_CHIP = 7 ;
+static const uint8_t P9N2_PU_NPU2_SM3_GPU0_BAR_CONFIG_CHIP_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM3_GPU0_BAR_CONFIG_ADDR = 10 ;
+static const uint8_t P9N2_PU_NPU2_SM3_GPU0_BAR_CONFIG_ADDR_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU2_SM3_GPU0_BAR_CONFIG_POISON = 22 ;
+static const uint8_t P9N2_PU_NPU2_SM3_GPU0_BAR_CONFIG_GRANULE = 23 ;
+static const uint8_t P9N2_PU_NPU2_SM3_GPU0_BAR_CONFIG_SIZE = 24 ;
+static const uint8_t P9N2_PU_NPU2_SM3_GPU0_BAR_CONFIG_SIZE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM3_GPU0_BAR_CONFIG_MODE = 28 ;
+static const uint8_t P9N2_PU_NPU2_SM3_GPU0_BAR_CONFIG_MODE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM3_GPU0_BAR_CONFIG_RESERVED2 = 32 ;
+static const uint8_t P9N2_PU_NPU2_SM3_GPU0_BAR_CONFIG_MASK = 33 ;
+static const uint8_t P9N2_PU_NPU2_SM3_GPU0_BAR_CONFIG_MASK_LEN = 7 ;
+
+static const uint8_t P9N2_PU_NPU0_SM3_GPU0_BAR_CONFIG_MEMSELMATCH = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM3_GPU0_BAR_CONFIG_MEMSELMATCH_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM3_GPU0_BAR_CONFIG_GROUP = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM3_GPU0_BAR_CONFIG_GROUP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM3_GPU0_BAR_CONFIG_CHIP = 7 ;
+static const uint8_t P9N2_PU_NPU0_SM3_GPU0_BAR_CONFIG_CHIP_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM3_GPU0_BAR_CONFIG_ADDR = 10 ;
+static const uint8_t P9N2_PU_NPU0_SM3_GPU0_BAR_CONFIG_ADDR_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU0_SM3_GPU0_BAR_CONFIG_POISON = 22 ;
+static const uint8_t P9N2_PU_NPU0_SM3_GPU0_BAR_CONFIG_GRANULE = 23 ;
+static const uint8_t P9N2_PU_NPU0_SM3_GPU0_BAR_CONFIG_SIZE = 24 ;
+static const uint8_t P9N2_PU_NPU0_SM3_GPU0_BAR_CONFIG_SIZE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM3_GPU0_BAR_CONFIG_MODE = 28 ;
+static const uint8_t P9N2_PU_NPU0_SM3_GPU0_BAR_CONFIG_MODE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM3_GPU0_BAR_CONFIG_RESERVED2 = 32 ;
+static const uint8_t P9N2_PU_NPU0_SM3_GPU0_BAR_CONFIG_MASK = 33 ;
+static const uint8_t P9N2_PU_NPU0_SM3_GPU0_BAR_CONFIG_MASK_LEN = 7 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM0_GPU0_BAR_CONFIG_MEMSELMATCH = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_GPU0_BAR_CONFIG_MEMSELMATCH_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_GPU0_BAR_CONFIG_GROUP = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_GPU0_BAR_CONFIG_GROUP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_GPU0_BAR_CONFIG_CHIP = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_GPU0_BAR_CONFIG_CHIP_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_GPU0_BAR_CONFIG_ADDR = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_GPU0_BAR_CONFIG_ADDR_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_GPU0_BAR_CONFIG_POISON = 22 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_GPU0_BAR_CONFIG_GRANULE = 23 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_GPU0_BAR_CONFIG_SIZE = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_GPU0_BAR_CONFIG_SIZE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_GPU0_BAR_CONFIG_MODE = 28 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_GPU0_BAR_CONFIG_MODE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_GPU0_BAR_CONFIG_RESERVED2 = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_GPU0_BAR_CONFIG_MASK = 33 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_GPU0_BAR_CONFIG_MASK_LEN = 7 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM1_GPU0_BAR_CONFIG_MEMSELMATCH = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_GPU0_BAR_CONFIG_MEMSELMATCH_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_GPU0_BAR_CONFIG_GROUP = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_GPU0_BAR_CONFIG_GROUP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_GPU0_BAR_CONFIG_CHIP = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_GPU0_BAR_CONFIG_CHIP_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_GPU0_BAR_CONFIG_ADDR = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_GPU0_BAR_CONFIG_ADDR_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_GPU0_BAR_CONFIG_POISON = 22 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_GPU0_BAR_CONFIG_GRANULE = 23 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_GPU0_BAR_CONFIG_SIZE = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_GPU0_BAR_CONFIG_SIZE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_GPU0_BAR_CONFIG_MODE = 28 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_GPU0_BAR_CONFIG_MODE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_GPU0_BAR_CONFIG_RESERVED2 = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_GPU0_BAR_CONFIG_MASK = 33 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_GPU0_BAR_CONFIG_MASK_LEN = 7 ;
+
+static const uint8_t P9N2_PU_NPU2_SM1_GPU0_BAR_CONFIG_MEMSELMATCH = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM1_GPU0_BAR_CONFIG_MEMSELMATCH_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM1_GPU0_BAR_CONFIG_GROUP = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM1_GPU0_BAR_CONFIG_GROUP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM1_GPU0_BAR_CONFIG_CHIP = 7 ;
+static const uint8_t P9N2_PU_NPU2_SM1_GPU0_BAR_CONFIG_CHIP_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM1_GPU0_BAR_CONFIG_ADDR = 10 ;
+static const uint8_t P9N2_PU_NPU2_SM1_GPU0_BAR_CONFIG_ADDR_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU2_SM1_GPU0_BAR_CONFIG_POISON = 22 ;
+static const uint8_t P9N2_PU_NPU2_SM1_GPU0_BAR_CONFIG_GRANULE = 23 ;
+static const uint8_t P9N2_PU_NPU2_SM1_GPU0_BAR_CONFIG_SIZE = 24 ;
+static const uint8_t P9N2_PU_NPU2_SM1_GPU0_BAR_CONFIG_SIZE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM1_GPU0_BAR_CONFIG_MODE = 28 ;
+static const uint8_t P9N2_PU_NPU2_SM1_GPU0_BAR_CONFIG_MODE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM1_GPU0_BAR_CONFIG_RESERVED2 = 32 ;
+static const uint8_t P9N2_PU_NPU2_SM1_GPU0_BAR_CONFIG_MASK = 33 ;
+static const uint8_t P9N2_PU_NPU2_SM1_GPU0_BAR_CONFIG_MASK_LEN = 7 ;
+
+static const uint8_t P9N2_PU_NPU0_CTL_GPU0_BAR_CONFIG_MEMSELMATCH = 0 ;
+static const uint8_t P9N2_PU_NPU0_CTL_GPU0_BAR_CONFIG_MEMSELMATCH_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU0_CTL_GPU0_BAR_CONFIG_GROUP = 3 ;
+static const uint8_t P9N2_PU_NPU0_CTL_GPU0_BAR_CONFIG_GROUP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_CTL_GPU0_BAR_CONFIG_CHIP = 7 ;
+static const uint8_t P9N2_PU_NPU0_CTL_GPU0_BAR_CONFIG_CHIP_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU0_CTL_GPU0_BAR_CONFIG_ADDR = 10 ;
+static const uint8_t P9N2_PU_NPU0_CTL_GPU0_BAR_CONFIG_ADDR_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU0_CTL_GPU0_BAR_CONFIG_POISON = 22 ;
+static const uint8_t P9N2_PU_NPU0_CTL_GPU0_BAR_CONFIG_GRANULE = 23 ;
+static const uint8_t P9N2_PU_NPU0_CTL_GPU0_BAR_CONFIG_SIZE = 24 ;
+static const uint8_t P9N2_PU_NPU0_CTL_GPU0_BAR_CONFIG_SIZE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_CTL_GPU0_BAR_CONFIG_MODE = 28 ;
+static const uint8_t P9N2_PU_NPU0_CTL_GPU0_BAR_CONFIG_MODE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_CTL_GPU0_BAR_CONFIG_RESERVED2 = 32 ;
+static const uint8_t P9N2_PU_NPU0_CTL_GPU0_BAR_CONFIG_MASK = 33 ;
+static const uint8_t P9N2_PU_NPU0_CTL_GPU0_BAR_CONFIG_MASK_LEN = 7 ;
+
+static const uint8_t P9N2_PU_NPU2_SM0_GPU0_BAR_CONFIG_MEMSELMATCH = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM0_GPU0_BAR_CONFIG_MEMSELMATCH_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM0_GPU0_BAR_CONFIG_GROUP = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM0_GPU0_BAR_CONFIG_GROUP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM0_GPU0_BAR_CONFIG_CHIP = 7 ;
+static const uint8_t P9N2_PU_NPU2_SM0_GPU0_BAR_CONFIG_CHIP_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM0_GPU0_BAR_CONFIG_ADDR = 10 ;
+static const uint8_t P9N2_PU_NPU2_SM0_GPU0_BAR_CONFIG_ADDR_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU2_SM0_GPU0_BAR_CONFIG_POISON = 22 ;
+static const uint8_t P9N2_PU_NPU2_SM0_GPU0_BAR_CONFIG_GRANULE = 23 ;
+static const uint8_t P9N2_PU_NPU2_SM0_GPU0_BAR_CONFIG_SIZE = 24 ;
+static const uint8_t P9N2_PU_NPU2_SM0_GPU0_BAR_CONFIG_SIZE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM0_GPU0_BAR_CONFIG_MODE = 28 ;
+static const uint8_t P9N2_PU_NPU2_SM0_GPU0_BAR_CONFIG_MODE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM0_GPU0_BAR_CONFIG_RESERVED2 = 32 ;
+static const uint8_t P9N2_PU_NPU2_SM0_GPU0_BAR_CONFIG_MASK = 33 ;
+static const uint8_t P9N2_PU_NPU2_SM0_GPU0_BAR_CONFIG_MASK_LEN = 7 ;
+
+static const uint8_t P9N2_PU_NPU2_CTL_GPU0_BAR_CONFIG_MEMSELMATCH = 0 ;
+static const uint8_t P9N2_PU_NPU2_CTL_GPU0_BAR_CONFIG_MEMSELMATCH_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU2_CTL_GPU0_BAR_CONFIG_GROUP = 3 ;
+static const uint8_t P9N2_PU_NPU2_CTL_GPU0_BAR_CONFIG_GROUP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_CTL_GPU0_BAR_CONFIG_CHIP = 7 ;
+static const uint8_t P9N2_PU_NPU2_CTL_GPU0_BAR_CONFIG_CHIP_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU2_CTL_GPU0_BAR_CONFIG_ADDR = 10 ;
+static const uint8_t P9N2_PU_NPU2_CTL_GPU0_BAR_CONFIG_ADDR_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU2_CTL_GPU0_BAR_CONFIG_POISON = 22 ;
+static const uint8_t P9N2_PU_NPU2_CTL_GPU0_BAR_CONFIG_GRANULE = 23 ;
+static const uint8_t P9N2_PU_NPU2_CTL_GPU0_BAR_CONFIG_SIZE = 24 ;
+static const uint8_t P9N2_PU_NPU2_CTL_GPU0_BAR_CONFIG_SIZE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_CTL_GPU0_BAR_CONFIG_MODE = 28 ;
+static const uint8_t P9N2_PU_NPU2_CTL_GPU0_BAR_CONFIG_MODE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_CTL_GPU0_BAR_CONFIG_RESERVED2 = 32 ;
+static const uint8_t P9N2_PU_NPU2_CTL_GPU0_BAR_CONFIG_MASK = 33 ;
+static const uint8_t P9N2_PU_NPU2_CTL_GPU0_BAR_CONFIG_MASK_LEN = 7 ;
+
+static const uint8_t P9N2_PU_NPU0_SM1_GPU0_BAR_CONFIG_MEMSELMATCH = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM1_GPU0_BAR_CONFIG_MEMSELMATCH_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM1_GPU0_BAR_CONFIG_GROUP = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM1_GPU0_BAR_CONFIG_GROUP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM1_GPU0_BAR_CONFIG_CHIP = 7 ;
+static const uint8_t P9N2_PU_NPU0_SM1_GPU0_BAR_CONFIG_CHIP_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM1_GPU0_BAR_CONFIG_ADDR = 10 ;
+static const uint8_t P9N2_PU_NPU0_SM1_GPU0_BAR_CONFIG_ADDR_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU0_SM1_GPU0_BAR_CONFIG_POISON = 22 ;
+static const uint8_t P9N2_PU_NPU0_SM1_GPU0_BAR_CONFIG_GRANULE = 23 ;
+static const uint8_t P9N2_PU_NPU0_SM1_GPU0_BAR_CONFIG_SIZE = 24 ;
+static const uint8_t P9N2_PU_NPU0_SM1_GPU0_BAR_CONFIG_SIZE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM1_GPU0_BAR_CONFIG_MODE = 28 ;
+static const uint8_t P9N2_PU_NPU0_SM1_GPU0_BAR_CONFIG_MODE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM1_GPU0_BAR_CONFIG_RESERVED2 = 32 ;
+static const uint8_t P9N2_PU_NPU0_SM1_GPU0_BAR_CONFIG_MASK = 33 ;
+static const uint8_t P9N2_PU_NPU0_SM1_GPU0_BAR_CONFIG_MASK_LEN = 7 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_CTL_GPU0_BAR_CONFIG_MEMSELMATCH = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_GPU0_BAR_CONFIG_MEMSELMATCH_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_GPU0_BAR_CONFIG_GROUP = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_GPU0_BAR_CONFIG_GROUP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_GPU0_BAR_CONFIG_CHIP = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_GPU0_BAR_CONFIG_CHIP_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_GPU0_BAR_CONFIG_ADDR = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_GPU0_BAR_CONFIG_ADDR_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_GPU0_BAR_CONFIG_POISON = 22 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_GPU0_BAR_CONFIG_GRANULE = 23 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_GPU0_BAR_CONFIG_SIZE = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_GPU0_BAR_CONFIG_SIZE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_GPU0_BAR_CONFIG_MODE = 28 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_GPU0_BAR_CONFIG_MODE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_GPU0_BAR_CONFIG_RESERVED2 = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_GPU0_BAR_CONFIG_MASK = 33 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_GPU0_BAR_CONFIG_MASK_LEN = 7 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM3_GPU0_BAR_CONFIG_MEMSELMATCH = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_GPU0_BAR_CONFIG_MEMSELMATCH_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_GPU0_BAR_CONFIG_GROUP = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_GPU0_BAR_CONFIG_GROUP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_GPU0_BAR_CONFIG_CHIP = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_GPU0_BAR_CONFIG_CHIP_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_GPU0_BAR_CONFIG_ADDR = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_GPU0_BAR_CONFIG_ADDR_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_GPU0_BAR_CONFIG_POISON = 22 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_GPU0_BAR_CONFIG_GRANULE = 23 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_GPU0_BAR_CONFIG_SIZE = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_GPU0_BAR_CONFIG_SIZE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_GPU0_BAR_CONFIG_MODE = 28 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_GPU0_BAR_CONFIG_MODE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_GPU0_BAR_CONFIG_RESERVED2 = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_GPU0_BAR_CONFIG_MASK = 33 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_GPU0_BAR_CONFIG_MASK_LEN = 7 ;
+
+static const uint8_t P9N2_PU_NPU0_SM0_GPU1_BAR_CONFIG_MEMSELMATCH = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM0_GPU1_BAR_CONFIG_MEMSELMATCH_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM0_GPU1_BAR_CONFIG_GROUP = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM0_GPU1_BAR_CONFIG_GROUP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM0_GPU1_BAR_CONFIG_CHIP = 7 ;
+static const uint8_t P9N2_PU_NPU0_SM0_GPU1_BAR_CONFIG_CHIP_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM0_GPU1_BAR_CONFIG_ADDR = 10 ;
+static const uint8_t P9N2_PU_NPU0_SM0_GPU1_BAR_CONFIG_ADDR_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU0_SM0_GPU1_BAR_CONFIG_POISON = 22 ;
+static const uint8_t P9N2_PU_NPU0_SM0_GPU1_BAR_CONFIG_GRANULE = 23 ;
+static const uint8_t P9N2_PU_NPU0_SM0_GPU1_BAR_CONFIG_SIZE = 24 ;
+static const uint8_t P9N2_PU_NPU0_SM0_GPU1_BAR_CONFIG_SIZE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM0_GPU1_BAR_CONFIG_MODE = 28 ;
+static const uint8_t P9N2_PU_NPU0_SM0_GPU1_BAR_CONFIG_MODE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM0_GPU1_BAR_CONFIG_RESERVED2 = 32 ;
+static const uint8_t P9N2_PU_NPU0_SM0_GPU1_BAR_CONFIG_MASK = 33 ;
+static const uint8_t P9N2_PU_NPU0_SM0_GPU1_BAR_CONFIG_MASK_LEN = 7 ;
+
+static const uint8_t P9N2_PU_NPU2_SM3_GPU1_BAR_CONFIG_MEMSELMATCH = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM3_GPU1_BAR_CONFIG_MEMSELMATCH_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM3_GPU1_BAR_CONFIG_GROUP = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM3_GPU1_BAR_CONFIG_GROUP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM3_GPU1_BAR_CONFIG_CHIP = 7 ;
+static const uint8_t P9N2_PU_NPU2_SM3_GPU1_BAR_CONFIG_CHIP_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM3_GPU1_BAR_CONFIG_ADDR = 10 ;
+static const uint8_t P9N2_PU_NPU2_SM3_GPU1_BAR_CONFIG_ADDR_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU2_SM3_GPU1_BAR_CONFIG_POISON = 22 ;
+static const uint8_t P9N2_PU_NPU2_SM3_GPU1_BAR_CONFIG_GRANULE = 23 ;
+static const uint8_t P9N2_PU_NPU2_SM3_GPU1_BAR_CONFIG_SIZE = 24 ;
+static const uint8_t P9N2_PU_NPU2_SM3_GPU1_BAR_CONFIG_SIZE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM3_GPU1_BAR_CONFIG_MODE = 28 ;
+static const uint8_t P9N2_PU_NPU2_SM3_GPU1_BAR_CONFIG_MODE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM3_GPU1_BAR_CONFIG_RESERVED2 = 32 ;
+static const uint8_t P9N2_PU_NPU2_SM3_GPU1_BAR_CONFIG_MASK = 33 ;
+static const uint8_t P9N2_PU_NPU2_SM3_GPU1_BAR_CONFIG_MASK_LEN = 7 ;
+
+static const uint8_t P9N2_PU_NPU0_SM3_GPU1_BAR_CONFIG_MEMSELMATCH = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM3_GPU1_BAR_CONFIG_MEMSELMATCH_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM3_GPU1_BAR_CONFIG_GROUP = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM3_GPU1_BAR_CONFIG_GROUP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM3_GPU1_BAR_CONFIG_CHIP = 7 ;
+static const uint8_t P9N2_PU_NPU0_SM3_GPU1_BAR_CONFIG_CHIP_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM3_GPU1_BAR_CONFIG_ADDR = 10 ;
+static const uint8_t P9N2_PU_NPU0_SM3_GPU1_BAR_CONFIG_ADDR_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU0_SM3_GPU1_BAR_CONFIG_POISON = 22 ;
+static const uint8_t P9N2_PU_NPU0_SM3_GPU1_BAR_CONFIG_GRANULE = 23 ;
+static const uint8_t P9N2_PU_NPU0_SM3_GPU1_BAR_CONFIG_SIZE = 24 ;
+static const uint8_t P9N2_PU_NPU0_SM3_GPU1_BAR_CONFIG_SIZE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM3_GPU1_BAR_CONFIG_MODE = 28 ;
+static const uint8_t P9N2_PU_NPU0_SM3_GPU1_BAR_CONFIG_MODE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM3_GPU1_BAR_CONFIG_RESERVED2 = 32 ;
+static const uint8_t P9N2_PU_NPU0_SM3_GPU1_BAR_CONFIG_MASK = 33 ;
+static const uint8_t P9N2_PU_NPU0_SM3_GPU1_BAR_CONFIG_MASK_LEN = 7 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM0_GPU1_BAR_CONFIG_MEMSELMATCH = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_GPU1_BAR_CONFIG_MEMSELMATCH_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_GPU1_BAR_CONFIG_GROUP = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_GPU1_BAR_CONFIG_GROUP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_GPU1_BAR_CONFIG_CHIP = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_GPU1_BAR_CONFIG_CHIP_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_GPU1_BAR_CONFIG_ADDR = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_GPU1_BAR_CONFIG_ADDR_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_GPU1_BAR_CONFIG_POISON = 22 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_GPU1_BAR_CONFIG_GRANULE = 23 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_GPU1_BAR_CONFIG_SIZE = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_GPU1_BAR_CONFIG_SIZE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_GPU1_BAR_CONFIG_MODE = 28 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_GPU1_BAR_CONFIG_MODE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_GPU1_BAR_CONFIG_RESERVED2 = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_GPU1_BAR_CONFIG_MASK = 33 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_GPU1_BAR_CONFIG_MASK_LEN = 7 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM1_GPU1_BAR_CONFIG_MEMSELMATCH = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_GPU1_BAR_CONFIG_MEMSELMATCH_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_GPU1_BAR_CONFIG_GROUP = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_GPU1_BAR_CONFIG_GROUP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_GPU1_BAR_CONFIG_CHIP = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_GPU1_BAR_CONFIG_CHIP_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_GPU1_BAR_CONFIG_ADDR = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_GPU1_BAR_CONFIG_ADDR_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_GPU1_BAR_CONFIG_POISON = 22 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_GPU1_BAR_CONFIG_GRANULE = 23 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_GPU1_BAR_CONFIG_SIZE = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_GPU1_BAR_CONFIG_SIZE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_GPU1_BAR_CONFIG_MODE = 28 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_GPU1_BAR_CONFIG_MODE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_GPU1_BAR_CONFIG_RESERVED2 = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_GPU1_BAR_CONFIG_MASK = 33 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_GPU1_BAR_CONFIG_MASK_LEN = 7 ;
+
+static const uint8_t P9N2_PU_NPU2_SM1_GPU1_BAR_CONFIG_MEMSELMATCH = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM1_GPU1_BAR_CONFIG_MEMSELMATCH_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM1_GPU1_BAR_CONFIG_GROUP = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM1_GPU1_BAR_CONFIG_GROUP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM1_GPU1_BAR_CONFIG_CHIP = 7 ;
+static const uint8_t P9N2_PU_NPU2_SM1_GPU1_BAR_CONFIG_CHIP_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM1_GPU1_BAR_CONFIG_ADDR = 10 ;
+static const uint8_t P9N2_PU_NPU2_SM1_GPU1_BAR_CONFIG_ADDR_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU2_SM1_GPU1_BAR_CONFIG_POISON = 22 ;
+static const uint8_t P9N2_PU_NPU2_SM1_GPU1_BAR_CONFIG_GRANULE = 23 ;
+static const uint8_t P9N2_PU_NPU2_SM1_GPU1_BAR_CONFIG_SIZE = 24 ;
+static const uint8_t P9N2_PU_NPU2_SM1_GPU1_BAR_CONFIG_SIZE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM1_GPU1_BAR_CONFIG_MODE = 28 ;
+static const uint8_t P9N2_PU_NPU2_SM1_GPU1_BAR_CONFIG_MODE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM1_GPU1_BAR_CONFIG_RESERVED2 = 32 ;
+static const uint8_t P9N2_PU_NPU2_SM1_GPU1_BAR_CONFIG_MASK = 33 ;
+static const uint8_t P9N2_PU_NPU2_SM1_GPU1_BAR_CONFIG_MASK_LEN = 7 ;
+
+static const uint8_t P9N2_PU_NPU0_CTL_GPU1_BAR_CONFIG_MEMSELMATCH = 0 ;
+static const uint8_t P9N2_PU_NPU0_CTL_GPU1_BAR_CONFIG_MEMSELMATCH_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU0_CTL_GPU1_BAR_CONFIG_GROUP = 3 ;
+static const uint8_t P9N2_PU_NPU0_CTL_GPU1_BAR_CONFIG_GROUP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_CTL_GPU1_BAR_CONFIG_CHIP = 7 ;
+static const uint8_t P9N2_PU_NPU0_CTL_GPU1_BAR_CONFIG_CHIP_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU0_CTL_GPU1_BAR_CONFIG_ADDR = 10 ;
+static const uint8_t P9N2_PU_NPU0_CTL_GPU1_BAR_CONFIG_ADDR_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU0_CTL_GPU1_BAR_CONFIG_POISON = 22 ;
+static const uint8_t P9N2_PU_NPU0_CTL_GPU1_BAR_CONFIG_GRANULE = 23 ;
+static const uint8_t P9N2_PU_NPU0_CTL_GPU1_BAR_CONFIG_SIZE = 24 ;
+static const uint8_t P9N2_PU_NPU0_CTL_GPU1_BAR_CONFIG_SIZE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_CTL_GPU1_BAR_CONFIG_MODE = 28 ;
+static const uint8_t P9N2_PU_NPU0_CTL_GPU1_BAR_CONFIG_MODE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_CTL_GPU1_BAR_CONFIG_RESERVED2 = 32 ;
+static const uint8_t P9N2_PU_NPU0_CTL_GPU1_BAR_CONFIG_MASK = 33 ;
+static const uint8_t P9N2_PU_NPU0_CTL_GPU1_BAR_CONFIG_MASK_LEN = 7 ;
+
+static const uint8_t P9N2_PU_NPU2_SM0_GPU1_BAR_CONFIG_MEMSELMATCH = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM0_GPU1_BAR_CONFIG_MEMSELMATCH_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM0_GPU1_BAR_CONFIG_GROUP = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM0_GPU1_BAR_CONFIG_GROUP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM0_GPU1_BAR_CONFIG_CHIP = 7 ;
+static const uint8_t P9N2_PU_NPU2_SM0_GPU1_BAR_CONFIG_CHIP_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM0_GPU1_BAR_CONFIG_ADDR = 10 ;
+static const uint8_t P9N2_PU_NPU2_SM0_GPU1_BAR_CONFIG_ADDR_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU2_SM0_GPU1_BAR_CONFIG_POISON = 22 ;
+static const uint8_t P9N2_PU_NPU2_SM0_GPU1_BAR_CONFIG_GRANULE = 23 ;
+static const uint8_t P9N2_PU_NPU2_SM0_GPU1_BAR_CONFIG_SIZE = 24 ;
+static const uint8_t P9N2_PU_NPU2_SM0_GPU1_BAR_CONFIG_SIZE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM0_GPU1_BAR_CONFIG_MODE = 28 ;
+static const uint8_t P9N2_PU_NPU2_SM0_GPU1_BAR_CONFIG_MODE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM0_GPU1_BAR_CONFIG_RESERVED2 = 32 ;
+static const uint8_t P9N2_PU_NPU2_SM0_GPU1_BAR_CONFIG_MASK = 33 ;
+static const uint8_t P9N2_PU_NPU2_SM0_GPU1_BAR_CONFIG_MASK_LEN = 7 ;
+
+static const uint8_t P9N2_PU_NPU2_CTL_GPU1_BAR_CONFIG_MEMSELMATCH = 0 ;
+static const uint8_t P9N2_PU_NPU2_CTL_GPU1_BAR_CONFIG_MEMSELMATCH_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU2_CTL_GPU1_BAR_CONFIG_GROUP = 3 ;
+static const uint8_t P9N2_PU_NPU2_CTL_GPU1_BAR_CONFIG_GROUP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_CTL_GPU1_BAR_CONFIG_CHIP = 7 ;
+static const uint8_t P9N2_PU_NPU2_CTL_GPU1_BAR_CONFIG_CHIP_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU2_CTL_GPU1_BAR_CONFIG_ADDR = 10 ;
+static const uint8_t P9N2_PU_NPU2_CTL_GPU1_BAR_CONFIG_ADDR_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU2_CTL_GPU1_BAR_CONFIG_POISON = 22 ;
+static const uint8_t P9N2_PU_NPU2_CTL_GPU1_BAR_CONFIG_GRANULE = 23 ;
+static const uint8_t P9N2_PU_NPU2_CTL_GPU1_BAR_CONFIG_SIZE = 24 ;
+static const uint8_t P9N2_PU_NPU2_CTL_GPU1_BAR_CONFIG_SIZE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_CTL_GPU1_BAR_CONFIG_MODE = 28 ;
+static const uint8_t P9N2_PU_NPU2_CTL_GPU1_BAR_CONFIG_MODE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_CTL_GPU1_BAR_CONFIG_RESERVED2 = 32 ;
+static const uint8_t P9N2_PU_NPU2_CTL_GPU1_BAR_CONFIG_MASK = 33 ;
+static const uint8_t P9N2_PU_NPU2_CTL_GPU1_BAR_CONFIG_MASK_LEN = 7 ;
+
+static const uint8_t P9N2_PU_NPU0_SM1_GPU1_BAR_CONFIG_MEMSELMATCH = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM1_GPU1_BAR_CONFIG_MEMSELMATCH_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM1_GPU1_BAR_CONFIG_GROUP = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM1_GPU1_BAR_CONFIG_GROUP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM1_GPU1_BAR_CONFIG_CHIP = 7 ;
+static const uint8_t P9N2_PU_NPU0_SM1_GPU1_BAR_CONFIG_CHIP_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM1_GPU1_BAR_CONFIG_ADDR = 10 ;
+static const uint8_t P9N2_PU_NPU0_SM1_GPU1_BAR_CONFIG_ADDR_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU0_SM1_GPU1_BAR_CONFIG_POISON = 22 ;
+static const uint8_t P9N2_PU_NPU0_SM1_GPU1_BAR_CONFIG_GRANULE = 23 ;
+static const uint8_t P9N2_PU_NPU0_SM1_GPU1_BAR_CONFIG_SIZE = 24 ;
+static const uint8_t P9N2_PU_NPU0_SM1_GPU1_BAR_CONFIG_SIZE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM1_GPU1_BAR_CONFIG_MODE = 28 ;
+static const uint8_t P9N2_PU_NPU0_SM1_GPU1_BAR_CONFIG_MODE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM1_GPU1_BAR_CONFIG_RESERVED2 = 32 ;
+static const uint8_t P9N2_PU_NPU0_SM1_GPU1_BAR_CONFIG_MASK = 33 ;
+static const uint8_t P9N2_PU_NPU0_SM1_GPU1_BAR_CONFIG_MASK_LEN = 7 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_CTL_GPU1_BAR_CONFIG_MEMSELMATCH = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_GPU1_BAR_CONFIG_MEMSELMATCH_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_GPU1_BAR_CONFIG_GROUP = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_GPU1_BAR_CONFIG_GROUP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_GPU1_BAR_CONFIG_CHIP = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_GPU1_BAR_CONFIG_CHIP_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_GPU1_BAR_CONFIG_ADDR = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_GPU1_BAR_CONFIG_ADDR_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_GPU1_BAR_CONFIG_POISON = 22 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_GPU1_BAR_CONFIG_GRANULE = 23 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_GPU1_BAR_CONFIG_SIZE = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_GPU1_BAR_CONFIG_SIZE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_GPU1_BAR_CONFIG_MODE = 28 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_GPU1_BAR_CONFIG_MODE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_GPU1_BAR_CONFIG_RESERVED2 = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_GPU1_BAR_CONFIG_MASK = 33 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_GPU1_BAR_CONFIG_MASK_LEN = 7 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM3_GPU1_BAR_CONFIG_MEMSELMATCH = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_GPU1_BAR_CONFIG_MEMSELMATCH_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_GPU1_BAR_CONFIG_GROUP = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_GPU1_BAR_CONFIG_GROUP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_GPU1_BAR_CONFIG_CHIP = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_GPU1_BAR_CONFIG_CHIP_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_GPU1_BAR_CONFIG_ADDR = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_GPU1_BAR_CONFIG_ADDR_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_GPU1_BAR_CONFIG_POISON = 22 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_GPU1_BAR_CONFIG_GRANULE = 23 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_GPU1_BAR_CONFIG_SIZE = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_GPU1_BAR_CONFIG_SIZE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_GPU1_BAR_CONFIG_MODE = 28 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_GPU1_BAR_CONFIG_MODE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_GPU1_BAR_CONFIG_RESERVED2 = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_GPU1_BAR_CONFIG_MASK = 33 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_GPU1_BAR_CONFIG_MASK_LEN = 7 ;
+
+static const uint8_t P9N2_PEC_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN0 = 0 ;
+static const uint8_t P9N2_PEC_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN1 = 1 ;
+static const uint8_t P9N2_PEC_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN2 = 2 ;
+static const uint8_t P9N2_PEC_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN3 = 3 ;
+static const uint8_t P9N2_PEC_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN4 = 4 ;
+static const uint8_t P9N2_PEC_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN5 = 5 ;
+static const uint8_t P9N2_PEC_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN6 = 6 ;
+static const uint8_t P9N2_PEC_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN7 = 7 ;
+static const uint8_t P9N2_PEC_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN8 = 8 ;
+static const uint8_t P9N2_PEC_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN9 = 9 ;
+static const uint8_t P9N2_PEC_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN10 = 10 ;
+static const uint8_t P9N2_PEC_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN11 = 11 ;
+
+static const uint8_t P9N2_PEC_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN0 = 0 ;
+static const uint8_t P9N2_PEC_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN1 = 1 ;
+static const uint8_t P9N2_PEC_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN2 = 2 ;
+static const uint8_t P9N2_PEC_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN3 = 3 ;
+static const uint8_t P9N2_PEC_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN4 = 4 ;
+static const uint8_t P9N2_PEC_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN5 = 5 ;
+static const uint8_t P9N2_PEC_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN6 = 6 ;
+static const uint8_t P9N2_PEC_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN7 = 7 ;
+static const uint8_t P9N2_PEC_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN8 = 8 ;
+static const uint8_t P9N2_PEC_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN9 = 9 ;
+static const uint8_t P9N2_PEC_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN10 = 10 ;
+static const uint8_t P9N2_PEC_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN11 = 11 ;
+
+static const uint8_t P9N2_PEC_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN0 = 0 ;
+static const uint8_t P9N2_PEC_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN1 = 1 ;
+static const uint8_t P9N2_PEC_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN2 = 2 ;
+static const uint8_t P9N2_PEC_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN3 = 3 ;
+static const uint8_t P9N2_PEC_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN4 = 4 ;
+static const uint8_t P9N2_PEC_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN5 = 5 ;
+static const uint8_t P9N2_PEC_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN6 = 6 ;
+static const uint8_t P9N2_PEC_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN7 = 7 ;
+static const uint8_t P9N2_PEC_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN8 = 8 ;
+static const uint8_t P9N2_PEC_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN9 = 9 ;
+static const uint8_t P9N2_PEC_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN10 = 10 ;
+static const uint8_t P9N2_PEC_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN11 = 11 ;
+
+static const uint8_t P9N2_PEC_GXSTOP_TRIG_REG_GXSTP_IN0 = 0 ;
+static const uint8_t P9N2_PEC_GXSTOP_TRIG_REG_GXSTP_IN1 = 1 ;
+static const uint8_t P9N2_PEC_GXSTOP_TRIG_REG_GXSTP_IN2 = 2 ;
+static const uint8_t P9N2_PEC_GXSTOP_TRIG_REG_GXSTP_IN3 = 3 ;
+static const uint8_t P9N2_PEC_GXSTOP_TRIG_REG_GXSTP_IN4 = 4 ;
+static const uint8_t P9N2_PEC_GXSTOP_TRIG_REG_GXSTP_IN5 = 5 ;
+static const uint8_t P9N2_PEC_GXSTOP_TRIG_REG_GXSTP_IN6 = 6 ;
+static const uint8_t P9N2_PEC_GXSTOP_TRIG_REG_GXSTP_IN7 = 7 ;
+static const uint8_t P9N2_PEC_GXSTOP_TRIG_REG_GXSTP_IN8 = 8 ;
+static const uint8_t P9N2_PEC_GXSTOP_TRIG_REG_GXSTP_IN9 = 9 ;
+static const uint8_t P9N2_PEC_GXSTOP_TRIG_REG_GXSTP_IN10 = 10 ;
+static const uint8_t P9N2_PEC_GXSTOP_TRIG_REG_GXSTP_IN11 = 11 ;
+
+static const uint8_t P9N2_PU_GZIP_CONTROL_REG_DISABLE_NEAR_HISTORY = 0 ;
+static const uint8_t P9N2_PU_GZIP_CONTROL_REG_DISABLE_FAR_HISTORY = 1 ;
+static const uint8_t P9N2_PU_GZIP_CONTROL_REG_DISABLE_EXTRA_HASH_ACCESSES = 2 ;
+static const uint8_t P9N2_PU_GZIP_CONTROL_REG_DISABLE_EXTRA_FIFO_ACCESSES = 3 ;
+static const uint8_t P9N2_PU_GZIP_CONTROL_REG_HASH_SIZE_MASK = 8 ;
+static const uint8_t P9N2_PU_GZIP_CONTROL_REG_HASH_SIZE_MASK_LEN = 8 ;
+
+static const uint8_t P9N2_PU_GZIP_ERRRPT_HOLD_REG_HOLD = 0 ;
+static const uint8_t P9N2_PU_GZIP_ERRRPT_HOLD_REG_HOLD_LEN = 12 ;
+
+static const uint8_t P9N2_PU_GZIP_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_LPID = 4 ;
+static const uint8_t P9N2_PU_GZIP_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_LPID_LEN = 12 ;
+static const uint8_t P9N2_PU_GZIP_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_PID = 20 ;
+static const uint8_t P9N2_PU_GZIP_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_PID_LEN = 20 ;
+static const uint8_t P9N2_PU_GZIP_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_TID = 44 ;
+static const uint8_t P9N2_PU_GZIP_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_TID_LEN = 16 ;
+static const uint8_t P9N2_PU_GZIP_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_ENABLE = 63 ;
+
+static const uint8_t P9N2_PU_GZIP_HI_PRIOR_RCV_FIFO_BAR_PRIORITY = 8 ;
+static const uint8_t P9N2_PU_GZIP_HI_PRIOR_RCV_FIFO_BAR_PRIORITY_LEN = 46 ;
+static const uint8_t P9N2_PU_GZIP_HI_PRIOR_RCV_FIFO_BAR_PRIORITY_SIZE = 54 ;
+static const uint8_t P9N2_PU_GZIP_HI_PRIOR_RCV_FIFO_BAR_PRIORITY_SIZE_LEN = 3 ;
+
+static const uint8_t P9N2_PU_GZIP_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_READ_OFFSET = 4 ;
+static const uint8_t P9N2_PU_GZIP_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_READ_OFFSET_LEN = 8 ;
+static const uint8_t P9N2_PU_GZIP_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_QUEUED = 15 ;
+static const uint8_t P9N2_PU_GZIP_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_QUEUED_LEN = 9 ;
+static const uint8_t P9N2_PU_GZIP_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_PRIMAX = 27 ;
+static const uint8_t P9N2_PU_GZIP_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_PRIMAX_LEN = 9 ;
+
+static const uint8_t P9N2_PU_GZIP_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_LPID = 4 ;
+static const uint8_t P9N2_PU_GZIP_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_LPID_LEN = 12 ;
+static const uint8_t P9N2_PU_GZIP_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_PID = 20 ;
+static const uint8_t P9N2_PU_GZIP_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_PID_LEN = 20 ;
+static const uint8_t P9N2_PU_GZIP_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_TID = 44 ;
+static const uint8_t P9N2_PU_GZIP_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_TID_LEN = 16 ;
+static const uint8_t P9N2_PU_GZIP_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_ENABLE = 63 ;
+
+static const uint8_t P9N2_PU_GZIP_LO_PRIOR_RCV_FIFO_BAR_PRIORITY = 8 ;
+static const uint8_t P9N2_PU_GZIP_LO_PRIOR_RCV_FIFO_BAR_PRIORITY_LEN = 46 ;
+static const uint8_t P9N2_PU_GZIP_LO_PRIOR_RCV_FIFO_BAR_PRIORITY_SIZE = 54 ;
+static const uint8_t P9N2_PU_GZIP_LO_PRIOR_RCV_FIFO_BAR_PRIORITY_SIZE_LEN = 3 ;
+
+static const uint8_t P9N2_PU_GZIP_LO_PRIOR_RCV_FIFO_CNTL_PRIORITY_READ_OFFSET = 4 ;
+static const uint8_t P9N2_PU_GZIP_LO_PRIOR_RCV_FIFO_CNTL_PRIORITY_READ_OFFSET_LEN = 8 ;
+static const uint8_t P9N2_PU_GZIP_LO_PRIOR_RCV_FIFO_CNTL_PRIORITY_QUEUED = 15 ;
+static const uint8_t P9N2_PU_GZIP_LO_PRIOR_RCV_FIFO_CNTL_PRIORITY_QUEUED_LEN = 9 ;
+
+static const uint8_t P9N2_PU_GZIP_MAX_BYTE_CNT_LOW = 0 ;
+static const uint8_t P9N2_PU_GZIP_MAX_BYTE_CNT_LOW_LEN = 5 ;
+static const uint8_t P9N2_PU_GZIP_MAX_BYTE_CNT_HIGH = 5 ;
+static const uint8_t P9N2_PU_GZIP_MAX_BYTE_CNT_HIGH_LEN = 5 ;
+static const uint8_t P9N2_PU_GZIP_MAX_BYTE_CNT_THRESHOLD = 10 ;
+static const uint8_t P9N2_PU_GZIP_MAX_BYTE_CNT_SRC_DDE = 11 ;
+static const uint8_t P9N2_PU_GZIP_MAX_BYTE_CNT_SRC_DDE_LEN = 8 ;
+static const uint8_t P9N2_PU_GZIP_MAX_BYTE_CNT_TARGET_DDE = 19 ;
+static const uint8_t P9N2_PU_GZIP_MAX_BYTE_CNT_TARGET_DDE_LEN = 8 ;
+
+static const uint8_t P9N2_PEC_HANG_PULSE_0_REG_0 = 0 ;
+static const uint8_t P9N2_PEC_HANG_PULSE_0_REG_0_LEN = 6 ;
+static const uint8_t P9N2_PEC_HANG_PULSE_0_REG_SUPPRESS = 6 ;
+
+static const uint8_t P9N2_PEC_HANG_PULSE_1_REG_1 = 0 ;
+static const uint8_t P9N2_PEC_HANG_PULSE_1_REG_1_LEN = 6 ;
+static const uint8_t P9N2_PEC_HANG_PULSE_1_REG_SUPPRESS = 6 ;
+
+static const uint8_t P9N2_PEC_HANG_PULSE_2_REG_2 = 0 ;
+static const uint8_t P9N2_PEC_HANG_PULSE_2_REG_2_LEN = 6 ;
+static const uint8_t P9N2_PEC_HANG_PULSE_2_REG_SUPPRESS = 6 ;
+
+static const uint8_t P9N2_PEC_HANG_PULSE_3_REG_3 = 0 ;
+static const uint8_t P9N2_PEC_HANG_PULSE_3_REG_3_LEN = 6 ;
+static const uint8_t P9N2_PEC_HANG_PULSE_3_REG_SUPPRESS = 6 ;
+
+static const uint8_t P9N2_PEC_HANG_PULSE_4_REG_4 = 0 ;
+static const uint8_t P9N2_PEC_HANG_PULSE_4_REG_4_LEN = 6 ;
+static const uint8_t P9N2_PEC_HANG_PULSE_4_REG_SUPPRESS = 6 ;
+
+static const uint8_t P9N2_PEC_HANG_PULSE_5_REG_5 = 0 ;
+static const uint8_t P9N2_PEC_HANG_PULSE_5_REG_5_LEN = 6 ;
+static const uint8_t P9N2_PEC_HANG_PULSE_5_REG_SUPPRESS = 6 ;
+
+static const uint8_t P9N2_PEC_HANG_PULSE_6_REG_6 = 0 ;
+static const uint8_t P9N2_PEC_HANG_PULSE_6_REG_6_LEN = 6 ;
+static const uint8_t P9N2_PEC_HANG_PULSE_6_REG_SUPPRESS = 6 ;
+
+static const uint8_t P9N2_PU_HCA_BAR_ADDR = 8 ;
+static const uint8_t P9N2_PU_HCA_BAR_ADDR_LEN = 24 ;
+static const uint8_t P9N2_PU_HCA_BAR_RANGE = 32 ;
+static const uint8_t P9N2_PU_HCA_BAR_RANGE_LEN = 11 ;
+static const uint8_t P9N2_PU_HCA_BAR_PAGE_SIZE_64K = 62 ;
+static const uint8_t P9N2_PU_HCA_BAR_VALID = 63 ;
+
+static const uint8_t P9N2_PU_HCA_COUNT_BAR_ADDR = 21 ;
+static const uint8_t P9N2_PU_HCA_COUNT_BAR_ADDR_LEN = 24 ;
+static const uint8_t P9N2_PU_HCA_COUNT_BAR_VALID = 63 ;
+
+static const uint8_t P9N2_PU_HCA_DECAY1_DECAY_SCOM_VALID = 0 ;
+static const uint8_t P9N2_PU_HCA_DECAY1_DECAY_SCOM_COUNT = 32 ;
+static const uint8_t P9N2_PU_HCA_DECAY1_DECAY_SCOM_COUNT_LEN = 32 ;
+
+static const uint8_t P9N2_PU_HCA_DECAY2_DECAY_SCOM_DELAY = 0 ;
+static const uint8_t P9N2_PU_HCA_DECAY2_DECAY_SCOM_DELAY_LEN = 30 ;
+static const uint8_t P9N2_PU_HCA_DECAY2_DECAY_ADDR_COND = 30 ;
+static const uint8_t P9N2_PU_HCA_DECAY2_DECAY_ADDR_COND_LEN = 11 ;
+static const uint8_t P9N2_PU_HCA_DECAY2_DECAY_ADDR = 41 ;
+static const uint8_t P9N2_PU_HCA_DECAY2_DECAY_ADDR_LEN = 16 ;
+
+static const uint8_t P9N2_PU_HCA_DROP_CASTOUT_COUNTER = 16 ;
+static const uint8_t P9N2_PU_HCA_DROP_CASTOUT_COUNTER_LEN = 16 ;
+
+static const uint8_t P9N2_PU_HCA_MIRROR_BAR_ADDR = 8 ;
+static const uint8_t P9N2_PU_HCA_MIRROR_BAR_ADDR_LEN = 25 ;
+static const uint8_t P9N2_PU_HCA_MIRROR_BAR_VALID = 63 ;
+
+static const uint8_t P9N2_PU_HCA_MODES_PB_32_1 = 3 ;
+static const uint8_t P9N2_PU_HCA_MODES_PB_16_1 = 4 ;
+static const uint8_t P9N2_PU_HCA_MODES_TRACE_SELECT = 5 ;
+static const uint8_t P9N2_PU_HCA_MODES_TRACE_SELECT_LEN = 8 ;
+static const uint8_t P9N2_PU_HCA_MODES_HANG_DIVIDER_CMD = 16 ;
+static const uint8_t P9N2_PU_HCA_MODES_HANG_DIVIDER_CMD_LEN = 5 ;
+static const uint8_t P9N2_PU_HCA_MODES_HANG_DIVIDER_DATA = 21 ;
+static const uint8_t P9N2_PU_HCA_MODES_HANG_DIVIDER_DATA_LEN = 5 ;
+static const uint8_t P9N2_PU_HCA_MODES_EPSILON_COUNT = 33 ;
+static const uint8_t P9N2_PU_HCA_MODES_EPSILON_COUNT_LEN = 12 ;
+static const uint8_t P9N2_PU_HCA_MODES_EPSILON_DIVIDER = 45 ;
+static const uint8_t P9N2_PU_HCA_MODES_EPSILON_DIVIDER_LEN = 4 ;
+
+static const uint8_t P9N2_PU_HCA_REF_BAR_ADDR = 21 ;
+static const uint8_t P9N2_PU_HCA_REF_BAR_ADDR_LEN = 25 ;
+static const uint8_t P9N2_PU_HCA_REF_BAR_VALID = 63 ;
+
+static const uint8_t P9N2_PEC_HEARTBEAT_REG_DEAD = 0 ;
+
+static const uint8_t P9N2_PU_NPU0_SM0_HIGH_WATER_CONFIG_XATS = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM0_HIGH_WATER_CONFIG_XATS_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM0_HIGH_WATER_CONFIG_PWR0 = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM0_HIGH_WATER_CONFIG_PWR0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM0_HIGH_WATER_CONFIG_PWR1 = 12 ;
+static const uint8_t P9N2_PU_NPU0_SM0_HIGH_WATER_CONFIG_PWR1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM0_HIGH_WATER_CONFIG_REQ0 = 18 ;
+static const uint8_t P9N2_PU_NPU0_SM0_HIGH_WATER_CONFIG_REQ0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM0_HIGH_WATER_CONFIG_PRB0 = 24 ;
+static const uint8_t P9N2_PU_NPU0_SM0_HIGH_WATER_CONFIG_PRB0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM0_HIGH_WATER_CONFIG_REQ1 = 30 ;
+static const uint8_t P9N2_PU_NPU0_SM0_HIGH_WATER_CONFIG_REQ1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM0_HIGH_WATER_CONFIG_PRB1 = 36 ;
+static const uint8_t P9N2_PU_NPU0_SM0_HIGH_WATER_CONFIG_PRB1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM0_HIGH_WATER_CONFIG_INTS = 42 ;
+static const uint8_t P9N2_PU_NPU0_SM0_HIGH_WATER_CONFIG_INTS_LEN = 6 ;
+
+static const uint8_t P9N2_PU_NPU2_SM3_HIGH_WATER_CONFIG_XATS = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM3_HIGH_WATER_CONFIG_XATS_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM3_HIGH_WATER_CONFIG_PWR0 = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM3_HIGH_WATER_CONFIG_PWR0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM3_HIGH_WATER_CONFIG_PWR1 = 12 ;
+static const uint8_t P9N2_PU_NPU2_SM3_HIGH_WATER_CONFIG_PWR1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM3_HIGH_WATER_CONFIG_REQ0 = 18 ;
+static const uint8_t P9N2_PU_NPU2_SM3_HIGH_WATER_CONFIG_REQ0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM3_HIGH_WATER_CONFIG_PRB0 = 24 ;
+static const uint8_t P9N2_PU_NPU2_SM3_HIGH_WATER_CONFIG_PRB0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM3_HIGH_WATER_CONFIG_REQ1 = 30 ;
+static const uint8_t P9N2_PU_NPU2_SM3_HIGH_WATER_CONFIG_REQ1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM3_HIGH_WATER_CONFIG_PRB1 = 36 ;
+static const uint8_t P9N2_PU_NPU2_SM3_HIGH_WATER_CONFIG_PRB1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM3_HIGH_WATER_CONFIG_INTS = 42 ;
+static const uint8_t P9N2_PU_NPU2_SM3_HIGH_WATER_CONFIG_INTS_LEN = 6 ;
+
+static const uint8_t P9N2_PU_NPU0_SM3_HIGH_WATER_CONFIG_XATS = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM3_HIGH_WATER_CONFIG_XATS_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM3_HIGH_WATER_CONFIG_PWR0 = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM3_HIGH_WATER_CONFIG_PWR0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM3_HIGH_WATER_CONFIG_PWR1 = 12 ;
+static const uint8_t P9N2_PU_NPU0_SM3_HIGH_WATER_CONFIG_PWR1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM3_HIGH_WATER_CONFIG_REQ0 = 18 ;
+static const uint8_t P9N2_PU_NPU0_SM3_HIGH_WATER_CONFIG_REQ0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM3_HIGH_WATER_CONFIG_PRB0 = 24 ;
+static const uint8_t P9N2_PU_NPU0_SM3_HIGH_WATER_CONFIG_PRB0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM3_HIGH_WATER_CONFIG_REQ1 = 30 ;
+static const uint8_t P9N2_PU_NPU0_SM3_HIGH_WATER_CONFIG_REQ1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM3_HIGH_WATER_CONFIG_PRB1 = 36 ;
+static const uint8_t P9N2_PU_NPU0_SM3_HIGH_WATER_CONFIG_PRB1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM3_HIGH_WATER_CONFIG_INTS = 42 ;
+static const uint8_t P9N2_PU_NPU0_SM3_HIGH_WATER_CONFIG_INTS_LEN = 6 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM0_HIGH_WATER_CONFIG_XATS = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_HIGH_WATER_CONFIG_XATS_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_HIGH_WATER_CONFIG_PWR0 = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_HIGH_WATER_CONFIG_PWR0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_HIGH_WATER_CONFIG_PWR1 = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_HIGH_WATER_CONFIG_PWR1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_HIGH_WATER_CONFIG_REQ0 = 18 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_HIGH_WATER_CONFIG_REQ0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_HIGH_WATER_CONFIG_PRB0 = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_HIGH_WATER_CONFIG_PRB0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_HIGH_WATER_CONFIG_REQ1 = 30 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_HIGH_WATER_CONFIG_REQ1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_HIGH_WATER_CONFIG_PRB1 = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_HIGH_WATER_CONFIG_PRB1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_HIGH_WATER_CONFIG_INTS = 42 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_HIGH_WATER_CONFIG_INTS_LEN = 6 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM1_HIGH_WATER_CONFIG_XATS = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_HIGH_WATER_CONFIG_XATS_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_HIGH_WATER_CONFIG_PWR0 = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_HIGH_WATER_CONFIG_PWR0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_HIGH_WATER_CONFIG_PWR1 = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_HIGH_WATER_CONFIG_PWR1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_HIGH_WATER_CONFIG_REQ0 = 18 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_HIGH_WATER_CONFIG_REQ0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_HIGH_WATER_CONFIG_PRB0 = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_HIGH_WATER_CONFIG_PRB0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_HIGH_WATER_CONFIG_REQ1 = 30 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_HIGH_WATER_CONFIG_REQ1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_HIGH_WATER_CONFIG_PRB1 = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_HIGH_WATER_CONFIG_PRB1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_HIGH_WATER_CONFIG_INTS = 42 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_HIGH_WATER_CONFIG_INTS_LEN = 6 ;
+
+static const uint8_t P9N2_PU_NPU2_SM1_HIGH_WATER_CONFIG_XATS = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM1_HIGH_WATER_CONFIG_XATS_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM1_HIGH_WATER_CONFIG_PWR0 = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM1_HIGH_WATER_CONFIG_PWR0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM1_HIGH_WATER_CONFIG_PWR1 = 12 ;
+static const uint8_t P9N2_PU_NPU2_SM1_HIGH_WATER_CONFIG_PWR1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM1_HIGH_WATER_CONFIG_REQ0 = 18 ;
+static const uint8_t P9N2_PU_NPU2_SM1_HIGH_WATER_CONFIG_REQ0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM1_HIGH_WATER_CONFIG_PRB0 = 24 ;
+static const uint8_t P9N2_PU_NPU2_SM1_HIGH_WATER_CONFIG_PRB0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM1_HIGH_WATER_CONFIG_REQ1 = 30 ;
+static const uint8_t P9N2_PU_NPU2_SM1_HIGH_WATER_CONFIG_REQ1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM1_HIGH_WATER_CONFIG_PRB1 = 36 ;
+static const uint8_t P9N2_PU_NPU2_SM1_HIGH_WATER_CONFIG_PRB1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM1_HIGH_WATER_CONFIG_INTS = 42 ;
+static const uint8_t P9N2_PU_NPU2_SM1_HIGH_WATER_CONFIG_INTS_LEN = 6 ;
+
+static const uint8_t P9N2_PU_NPU0_CTL_HIGH_WATER_CONFIG_XATS = 0 ;
+static const uint8_t P9N2_PU_NPU0_CTL_HIGH_WATER_CONFIG_XATS_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_CTL_HIGH_WATER_CONFIG_PWR0 = 6 ;
+static const uint8_t P9N2_PU_NPU0_CTL_HIGH_WATER_CONFIG_PWR0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_CTL_HIGH_WATER_CONFIG_PWR1 = 12 ;
+static const uint8_t P9N2_PU_NPU0_CTL_HIGH_WATER_CONFIG_PWR1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_CTL_HIGH_WATER_CONFIG_REQ0 = 18 ;
+static const uint8_t P9N2_PU_NPU0_CTL_HIGH_WATER_CONFIG_REQ0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_CTL_HIGH_WATER_CONFIG_PRB0 = 24 ;
+static const uint8_t P9N2_PU_NPU0_CTL_HIGH_WATER_CONFIG_PRB0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_CTL_HIGH_WATER_CONFIG_REQ1 = 30 ;
+static const uint8_t P9N2_PU_NPU0_CTL_HIGH_WATER_CONFIG_REQ1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_CTL_HIGH_WATER_CONFIG_PRB1 = 36 ;
+static const uint8_t P9N2_PU_NPU0_CTL_HIGH_WATER_CONFIG_PRB1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_CTL_HIGH_WATER_CONFIG_INTS = 42 ;
+static const uint8_t P9N2_PU_NPU0_CTL_HIGH_WATER_CONFIG_INTS_LEN = 6 ;
+
+static const uint8_t P9N2_PU_NPU2_SM0_HIGH_WATER_CONFIG_XATS = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM0_HIGH_WATER_CONFIG_XATS_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM0_HIGH_WATER_CONFIG_PWR0 = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM0_HIGH_WATER_CONFIG_PWR0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM0_HIGH_WATER_CONFIG_PWR1 = 12 ;
+static const uint8_t P9N2_PU_NPU2_SM0_HIGH_WATER_CONFIG_PWR1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM0_HIGH_WATER_CONFIG_REQ0 = 18 ;
+static const uint8_t P9N2_PU_NPU2_SM0_HIGH_WATER_CONFIG_REQ0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM0_HIGH_WATER_CONFIG_PRB0 = 24 ;
+static const uint8_t P9N2_PU_NPU2_SM0_HIGH_WATER_CONFIG_PRB0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM0_HIGH_WATER_CONFIG_REQ1 = 30 ;
+static const uint8_t P9N2_PU_NPU2_SM0_HIGH_WATER_CONFIG_REQ1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM0_HIGH_WATER_CONFIG_PRB1 = 36 ;
+static const uint8_t P9N2_PU_NPU2_SM0_HIGH_WATER_CONFIG_PRB1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM0_HIGH_WATER_CONFIG_INTS = 42 ;
+static const uint8_t P9N2_PU_NPU2_SM0_HIGH_WATER_CONFIG_INTS_LEN = 6 ;
+
+static const uint8_t P9N2_PU_NPU2_CTL_HIGH_WATER_CONFIG_XATS = 0 ;
+static const uint8_t P9N2_PU_NPU2_CTL_HIGH_WATER_CONFIG_XATS_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_CTL_HIGH_WATER_CONFIG_PWR0 = 6 ;
+static const uint8_t P9N2_PU_NPU2_CTL_HIGH_WATER_CONFIG_PWR0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_CTL_HIGH_WATER_CONFIG_PWR1 = 12 ;
+static const uint8_t P9N2_PU_NPU2_CTL_HIGH_WATER_CONFIG_PWR1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_CTL_HIGH_WATER_CONFIG_REQ0 = 18 ;
+static const uint8_t P9N2_PU_NPU2_CTL_HIGH_WATER_CONFIG_REQ0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_CTL_HIGH_WATER_CONFIG_PRB0 = 24 ;
+static const uint8_t P9N2_PU_NPU2_CTL_HIGH_WATER_CONFIG_PRB0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_CTL_HIGH_WATER_CONFIG_REQ1 = 30 ;
+static const uint8_t P9N2_PU_NPU2_CTL_HIGH_WATER_CONFIG_REQ1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_CTL_HIGH_WATER_CONFIG_PRB1 = 36 ;
+static const uint8_t P9N2_PU_NPU2_CTL_HIGH_WATER_CONFIG_PRB1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_CTL_HIGH_WATER_CONFIG_INTS = 42 ;
+static const uint8_t P9N2_PU_NPU2_CTL_HIGH_WATER_CONFIG_INTS_LEN = 6 ;
+
+static const uint8_t P9N2_PU_NPU0_SM1_HIGH_WATER_CONFIG_XATS = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM1_HIGH_WATER_CONFIG_XATS_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM1_HIGH_WATER_CONFIG_PWR0 = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM1_HIGH_WATER_CONFIG_PWR0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM1_HIGH_WATER_CONFIG_PWR1 = 12 ;
+static const uint8_t P9N2_PU_NPU0_SM1_HIGH_WATER_CONFIG_PWR1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM1_HIGH_WATER_CONFIG_REQ0 = 18 ;
+static const uint8_t P9N2_PU_NPU0_SM1_HIGH_WATER_CONFIG_REQ0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM1_HIGH_WATER_CONFIG_PRB0 = 24 ;
+static const uint8_t P9N2_PU_NPU0_SM1_HIGH_WATER_CONFIG_PRB0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM1_HIGH_WATER_CONFIG_REQ1 = 30 ;
+static const uint8_t P9N2_PU_NPU0_SM1_HIGH_WATER_CONFIG_REQ1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM1_HIGH_WATER_CONFIG_PRB1 = 36 ;
+static const uint8_t P9N2_PU_NPU0_SM1_HIGH_WATER_CONFIG_PRB1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM1_HIGH_WATER_CONFIG_INTS = 42 ;
+static const uint8_t P9N2_PU_NPU0_SM1_HIGH_WATER_CONFIG_INTS_LEN = 6 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_CTL_HIGH_WATER_CONFIG_XATS = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_HIGH_WATER_CONFIG_XATS_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_HIGH_WATER_CONFIG_PWR0 = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_HIGH_WATER_CONFIG_PWR0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_HIGH_WATER_CONFIG_PWR1 = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_HIGH_WATER_CONFIG_PWR1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_HIGH_WATER_CONFIG_REQ0 = 18 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_HIGH_WATER_CONFIG_REQ0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_HIGH_WATER_CONFIG_PRB0 = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_HIGH_WATER_CONFIG_PRB0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_HIGH_WATER_CONFIG_REQ1 = 30 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_HIGH_WATER_CONFIG_REQ1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_HIGH_WATER_CONFIG_PRB1 = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_HIGH_WATER_CONFIG_PRB1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_HIGH_WATER_CONFIG_INTS = 42 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_HIGH_WATER_CONFIG_INTS_LEN = 6 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM3_HIGH_WATER_CONFIG_XATS = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_HIGH_WATER_CONFIG_XATS_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_HIGH_WATER_CONFIG_PWR0 = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_HIGH_WATER_CONFIG_PWR0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_HIGH_WATER_CONFIG_PWR1 = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_HIGH_WATER_CONFIG_PWR1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_HIGH_WATER_CONFIG_REQ0 = 18 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_HIGH_WATER_CONFIG_REQ0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_HIGH_WATER_CONFIG_PRB0 = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_HIGH_WATER_CONFIG_PRB0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_HIGH_WATER_CONFIG_REQ1 = 30 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_HIGH_WATER_CONFIG_REQ1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_HIGH_WATER_CONFIG_PRB1 = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_HIGH_WATER_CONFIG_PRB1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_HIGH_WATER_CONFIG_INTS = 42 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_HIGH_WATER_CONFIG_INTS_LEN = 6 ;
+
+static const uint8_t P9N2_PEC_HOSTATTN_IN0 = 0 ;
+static const uint8_t P9N2_PEC_HOSTATTN_IN1 = 1 ;
+static const uint8_t P9N2_PEC_HOSTATTN_IN2 = 2 ;
+static const uint8_t P9N2_PEC_HOSTATTN_IN3 = 3 ;
+static const uint8_t P9N2_PEC_HOSTATTN_IN4 = 4 ;
+static const uint8_t P9N2_PEC_HOSTATTN_IN5 = 5 ;
+static const uint8_t P9N2_PEC_HOSTATTN_IN6 = 6 ;
+static const uint8_t P9N2_PEC_HOSTATTN_IN7 = 7 ;
+static const uint8_t P9N2_PEC_HOSTATTN_IN8 = 8 ;
+static const uint8_t P9N2_PEC_HOSTATTN_IN9 = 9 ;
+static const uint8_t P9N2_PEC_HOSTATTN_IN10 = 10 ;
+static const uint8_t P9N2_PEC_HOSTATTN_IN11 = 11 ;
+static const uint8_t P9N2_PEC_HOSTATTN_IN12 = 12 ;
+static const uint8_t P9N2_PEC_HOSTATTN_IN13 = 13 ;
+static const uint8_t P9N2_PEC_HOSTATTN_IN14 = 14 ;
+static const uint8_t P9N2_PEC_HOSTATTN_IN15 = 15 ;
+static const uint8_t P9N2_PEC_HOSTATTN_IN16 = 16 ;
+static const uint8_t P9N2_PEC_HOSTATTN_IN17 = 17 ;
+static const uint8_t P9N2_PEC_HOSTATTN_IN18 = 18 ;
+static const uint8_t P9N2_PEC_HOSTATTN_IN19 = 19 ;
+static const uint8_t P9N2_PEC_HOSTATTN_IN20 = 20 ;
+static const uint8_t P9N2_PEC_HOSTATTN_IN21 = 21 ;
+static const uint8_t P9N2_PEC_HOSTATTN_IN22 = 22 ;
+
+static const uint8_t P9N2_PEC_HOSTATTN_MASK_IN = 0 ;
+static const uint8_t P9N2_PEC_HOSTATTN_MASK_IN_LEN = 22 ;
+
+static const uint8_t P9N2_PU_HTM0_HTM_CFG_HTMSC_OPER_HANG_DIV_RATIO = 0 ;
+static const uint8_t P9N2_PU_HTM0_HTM_CFG_HTMSC_OPER_HANG_DIV_RATIO_LEN = 5 ;
+static const uint8_t P9N2_PU_HTM0_HTM_CFG_HTMSC_RTY_DRP_COUNT = 5 ;
+static const uint8_t P9N2_PU_HTM0_HTM_CFG_HTMSC_RTY_DRP_COUNT_LEN = 4 ;
+static const uint8_t P9N2_PU_HTM0_HTM_CFG_HTMSC_DIS_DRP_PRIORITY_INCR = 9 ;
+static const uint8_t P9N2_PU_HTM0_HTM_CFG_HTMSC_DIS_RETRY_BACKOFF = 10 ;
+static const uint8_t P9N2_PU_HTM0_HTM_CFG_HTMSC_DIS_OPER_HANG = 11 ;
+
+static const uint8_t P9N2_PU_HTM1_HTM_CFG_HTMSC_OPER_HANG_DIV_RATIO = 0 ;
+static const uint8_t P9N2_PU_HTM1_HTM_CFG_HTMSC_OPER_HANG_DIV_RATIO_LEN = 5 ;
+static const uint8_t P9N2_PU_HTM1_HTM_CFG_HTMSC_RTY_DRP_COUNT = 5 ;
+static const uint8_t P9N2_PU_HTM1_HTM_CFG_HTMSC_RTY_DRP_COUNT_LEN = 4 ;
+static const uint8_t P9N2_PU_HTM1_HTM_CFG_HTMSC_DIS_DRP_PRIORITY_INCR = 9 ;
+static const uint8_t P9N2_PU_HTM1_HTM_CFG_HTMSC_DIS_RETRY_BACKOFF = 10 ;
+static const uint8_t P9N2_PU_HTM1_HTM_CFG_HTMSC_DIS_OPER_HANG = 11 ;
+
+static const uint8_t P9N2_PU_HTM0_HTM_CTRL_HTMSC_TRIG = 0 ;
+static const uint8_t P9N2_PU_HTM0_HTM_CTRL_HTMSC_TRIG_LEN = 2 ;
+static const uint8_t P9N2_PU_HTM0_HTM_CTRL_HTMSC_MARK = 4 ;
+static const uint8_t P9N2_PU_HTM0_HTM_CTRL_HTMSC_MARK_LEN = 2 ;
+static const uint8_t P9N2_PU_HTM0_HTM_CTRL_HTMSC_DBG0_STOP = 6 ;
+static const uint8_t P9N2_PU_HTM0_HTM_CTRL_HTMSC_DBG1_STOP = 7 ;
+static const uint8_t P9N2_PU_HTM0_HTM_CTRL_HTMSC_RUN_STOP = 8 ;
+static const uint8_t P9N2_PU_HTM0_HTM_CTRL_HTMSC_OTHER_DBG0_STOP = 9 ;
+static const uint8_t P9N2_PU_HTM0_HTM_CTRL_HTMSC_SPARE1012 = 10 ;
+static const uint8_t P9N2_PU_HTM0_HTM_CTRL_HTMSC_SPARE1012_LEN = 3 ;
+static const uint8_t P9N2_PU_HTM0_HTM_CTRL_HTMSC_XSTOP_STOP = 13 ;
+static const uint8_t P9N2_PU_HTM0_HTM_CTRL_HTMSC_SPARE1415 = 14 ;
+static const uint8_t P9N2_PU_HTM0_HTM_CTRL_HTMSC_SPARE1415_LEN = 2 ;
+
+static const uint8_t P9N2_PU_HTM1_HTM_CTRL_HTMSC_TRIG = 0 ;
+static const uint8_t P9N2_PU_HTM1_HTM_CTRL_HTMSC_TRIG_LEN = 2 ;
+static const uint8_t P9N2_PU_HTM1_HTM_CTRL_HTMSC_MARK = 4 ;
+static const uint8_t P9N2_PU_HTM1_HTM_CTRL_HTMSC_MARK_LEN = 2 ;
+static const uint8_t P9N2_PU_HTM1_HTM_CTRL_HTMSC_DBG0_STOP = 6 ;
+static const uint8_t P9N2_PU_HTM1_HTM_CTRL_HTMSC_DBG1_STOP = 7 ;
+static const uint8_t P9N2_PU_HTM1_HTM_CTRL_HTMSC_RUN_STOP = 8 ;
+static const uint8_t P9N2_PU_HTM1_HTM_CTRL_HTMSC_OTHER_DBG0_STOP = 9 ;
+static const uint8_t P9N2_PU_HTM1_HTM_CTRL_HTMSC_SPARE1012 = 10 ;
+static const uint8_t P9N2_PU_HTM1_HTM_CTRL_HTMSC_SPARE1012_LEN = 3 ;
+static const uint8_t P9N2_PU_HTM1_HTM_CTRL_HTMSC_XSTOP_STOP = 13 ;
+static const uint8_t P9N2_PU_HTM1_HTM_CTRL_HTMSC_SPARE1415 = 14 ;
+static const uint8_t P9N2_PU_HTM1_HTM_CTRL_HTMSC_SPARE1415_LEN = 2 ;
+
+static const uint8_t P9N2_PU_HTM0_HTM_FILT_HTMSC_PAT = 0 ;
+static const uint8_t P9N2_PU_HTM0_HTM_FILT_HTMSC_PAT_LEN = 23 ;
+static const uint8_t P9N2_PU_HTM0_HTM_FILT_HTMSC_CRESP_PAT = 27 ;
+static const uint8_t P9N2_PU_HTM0_HTM_FILT_HTMSC_CRESP_PAT_LEN = 5 ;
+static const uint8_t P9N2_PU_HTM0_HTM_FILT_HTMSC_MASK = 32 ;
+static const uint8_t P9N2_PU_HTM0_HTM_FILT_HTMSC_MASK_LEN = 23 ;
+static const uint8_t P9N2_PU_HTM0_HTM_FILT_HTMSC_CRESP_MASK = 59 ;
+static const uint8_t P9N2_PU_HTM0_HTM_FILT_HTMSC_CRESP_MASK_LEN = 5 ;
+
+static const uint8_t P9N2_PU_HTM1_HTM_FILT_HTMSC_PAT = 0 ;
+static const uint8_t P9N2_PU_HTM1_HTM_FILT_HTMSC_PAT_LEN = 23 ;
+static const uint8_t P9N2_PU_HTM1_HTM_FILT_HTMSC_CRESP_PAT = 27 ;
+static const uint8_t P9N2_PU_HTM1_HTM_FILT_HTMSC_CRESP_PAT_LEN = 5 ;
+static const uint8_t P9N2_PU_HTM1_HTM_FILT_HTMSC_MASK = 32 ;
+static const uint8_t P9N2_PU_HTM1_HTM_FILT_HTMSC_MASK_LEN = 23 ;
+static const uint8_t P9N2_PU_HTM1_HTM_FILT_HTMSC_CRESP_MASK = 59 ;
+static const uint8_t P9N2_PU_HTM1_HTM_FILT_HTMSC_CRESP_MASK_LEN = 5 ;
+
+static const uint8_t P9N2_PU_HTM0_HTM_FLEX_HTMSC_FMUX_RGRPSEL0 = 0 ;
+static const uint8_t P9N2_PU_HTM0_HTM_FLEX_HTMSC_FMUX_RGRPSEL0_LEN = 4 ;
+static const uint8_t P9N2_PU_HTM0_HTM_FLEX_HTMSC_FMUX_RGRPSEL1 = 4 ;
+static const uint8_t P9N2_PU_HTM0_HTM_FLEX_HTMSC_FMUX_RGRPSEL1_LEN = 4 ;
+static const uint8_t P9N2_PU_HTM0_HTM_FLEX_HTMSC_FMUX_RGRPSEL2 = 8 ;
+static const uint8_t P9N2_PU_HTM0_HTM_FLEX_HTMSC_FMUX_RGRPSEL2_LEN = 4 ;
+static const uint8_t P9N2_PU_HTM0_HTM_FLEX_HTMSC_FMUX_RGRPSEL3 = 12 ;
+static const uint8_t P9N2_PU_HTM0_HTM_FLEX_HTMSC_FMUX_RGRPSEL3_LEN = 4 ;
+static const uint8_t P9N2_PU_HTM0_HTM_FLEX_HTMSC_FMUX_RGRPSEL4 = 16 ;
+static const uint8_t P9N2_PU_HTM0_HTM_FLEX_HTMSC_FMUX_RGRPSEL4_LEN = 4 ;
+static const uint8_t P9N2_PU_HTM0_HTM_FLEX_HTMSC_FMUX_RGRPSEL5 = 20 ;
+static const uint8_t P9N2_PU_HTM0_HTM_FLEX_HTMSC_FMUX_RGRPSEL5_LEN = 4 ;
+static const uint8_t P9N2_PU_HTM0_HTM_FLEX_HTMSC_FMUX_CGRPSEL0 = 24 ;
+static const uint8_t P9N2_PU_HTM0_HTM_FLEX_HTMSC_FMUX_CGRPSEL0_LEN = 4 ;
+static const uint8_t P9N2_PU_HTM0_HTM_FLEX_HTMSC_FMUX_CGRPSEL1 = 28 ;
+static const uint8_t P9N2_PU_HTM0_HTM_FLEX_HTMSC_FMUX_CGRPSEL1_LEN = 4 ;
+static const uint8_t P9N2_PU_HTM0_HTM_FLEX_HTMSC_FMUX_CGRPSEL2 = 32 ;
+static const uint8_t P9N2_PU_HTM0_HTM_FLEX_HTMSC_FMUX_CGRPSEL2_LEN = 4 ;
+
+static const uint8_t P9N2_PU_HTM1_HTM_FLEX_HTMSC_FMUX_RGRPSEL0 = 0 ;
+static const uint8_t P9N2_PU_HTM1_HTM_FLEX_HTMSC_FMUX_RGRPSEL0_LEN = 4 ;
+static const uint8_t P9N2_PU_HTM1_HTM_FLEX_HTMSC_FMUX_RGRPSEL1 = 4 ;
+static const uint8_t P9N2_PU_HTM1_HTM_FLEX_HTMSC_FMUX_RGRPSEL1_LEN = 4 ;
+static const uint8_t P9N2_PU_HTM1_HTM_FLEX_HTMSC_FMUX_RGRPSEL2 = 8 ;
+static const uint8_t P9N2_PU_HTM1_HTM_FLEX_HTMSC_FMUX_RGRPSEL2_LEN = 4 ;
+static const uint8_t P9N2_PU_HTM1_HTM_FLEX_HTMSC_FMUX_RGRPSEL3 = 12 ;
+static const uint8_t P9N2_PU_HTM1_HTM_FLEX_HTMSC_FMUX_RGRPSEL3_LEN = 4 ;
+static const uint8_t P9N2_PU_HTM1_HTM_FLEX_HTMSC_FMUX_RGRPSEL4 = 16 ;
+static const uint8_t P9N2_PU_HTM1_HTM_FLEX_HTMSC_FMUX_RGRPSEL4_LEN = 4 ;
+static const uint8_t P9N2_PU_HTM1_HTM_FLEX_HTMSC_FMUX_RGRPSEL5 = 20 ;
+static const uint8_t P9N2_PU_HTM1_HTM_FLEX_HTMSC_FMUX_RGRPSEL5_LEN = 4 ;
+static const uint8_t P9N2_PU_HTM1_HTM_FLEX_HTMSC_FMUX_CGRPSEL0 = 24 ;
+static const uint8_t P9N2_PU_HTM1_HTM_FLEX_HTMSC_FMUX_CGRPSEL0_LEN = 4 ;
+static const uint8_t P9N2_PU_HTM1_HTM_FLEX_HTMSC_FMUX_CGRPSEL1 = 28 ;
+static const uint8_t P9N2_PU_HTM1_HTM_FLEX_HTMSC_FMUX_CGRPSEL1_LEN = 4 ;
+static const uint8_t P9N2_PU_HTM1_HTM_FLEX_HTMSC_FMUX_CGRPSEL2 = 32 ;
+static const uint8_t P9N2_PU_HTM1_HTM_FLEX_HTMSC_FMUX_CGRPSEL2_LEN = 4 ;
+
+static const uint8_t P9N2_PU_HTM0_HTM_LAST_ADDRESS = 8 ;
+static const uint8_t P9N2_PU_HTM0_HTM_LAST_ADDRESS_LEN = 49 ;
+
+static const uint8_t P9N2_PU_HTM1_HTM_LAST_ADDRESS = 8 ;
+static const uint8_t P9N2_PU_HTM1_HTM_LAST_ADDRESS_LEN = 49 ;
+
+static const uint8_t P9N2_PU_HTM0_HTM_MEM_HTMSC_ALLOC = 0 ;
+static const uint8_t P9N2_PU_HTM0_HTM_MEM_HTMSC_SCOPE = 1 ;
+static const uint8_t P9N2_PU_HTM0_HTM_MEM_HTMSC_SCOPE_LEN = 3 ;
+static const uint8_t P9N2_PU_HTM0_HTM_MEM_HTMSC_PRIORITY = 4 ;
+static const uint8_t P9N2_PU_HTM0_HTM_MEM_HTMSC_SIZE_SMALL = 5 ;
+static const uint8_t P9N2_PU_HTM0_HTM_MEM_HTMSC_SPARE67 = 6 ;
+static const uint8_t P9N2_PU_HTM0_HTM_MEM_HTMSC_SPARE67_LEN = 2 ;
+static const uint8_t P9N2_PU_HTM0_HTM_MEM_HTMSC_BASE = 8 ;
+static const uint8_t P9N2_PU_HTM0_HTM_MEM_HTMSC_BASE_LEN = 32 ;
+static const uint8_t P9N2_PU_HTM0_HTM_MEM_HTMSC_SIZE = 40 ;
+static const uint8_t P9N2_PU_HTM0_HTM_MEM_HTMSC_SIZE_LEN = 9 ;
+
+static const uint8_t P9N2_PU_HTM1_HTM_MEM_HTMSC_ALLOC = 0 ;
+static const uint8_t P9N2_PU_HTM1_HTM_MEM_HTMSC_SCOPE = 1 ;
+static const uint8_t P9N2_PU_HTM1_HTM_MEM_HTMSC_SCOPE_LEN = 3 ;
+static const uint8_t P9N2_PU_HTM1_HTM_MEM_HTMSC_PRIORITY = 4 ;
+static const uint8_t P9N2_PU_HTM1_HTM_MEM_HTMSC_SIZE_SMALL = 5 ;
+static const uint8_t P9N2_PU_HTM1_HTM_MEM_HTMSC_SPARE67 = 6 ;
+static const uint8_t P9N2_PU_HTM1_HTM_MEM_HTMSC_SPARE67_LEN = 2 ;
+static const uint8_t P9N2_PU_HTM1_HTM_MEM_HTMSC_BASE = 8 ;
+static const uint8_t P9N2_PU_HTM1_HTM_MEM_HTMSC_BASE_LEN = 32 ;
+static const uint8_t P9N2_PU_HTM1_HTM_MEM_HTMSC_SIZE = 40 ;
+static const uint8_t P9N2_PU_HTM1_HTM_MEM_HTMSC_SIZE_LEN = 9 ;
+
+static const uint8_t P9N2_PU_HTM0_HTM_MODE_HTMSC_ENABLE = 0 ;
+static const uint8_t P9N2_PU_HTM0_HTM_MODE_HTMSC_CONTENT_SEL = 1 ;
+static const uint8_t P9N2_PU_HTM0_HTM_MODE_HTMSC_CONTENT_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_HTM0_HTM_MODE_HTMSC_SPARE3 = 3 ;
+static const uint8_t P9N2_PU_HTM0_HTM_MODE_HTMSC_CAPTURE = 4 ;
+static const uint8_t P9N2_PU_HTM0_HTM_MODE_HTMSC_CAPTURE_LEN = 9 ;
+static const uint8_t P9N2_PU_HTM0_HTM_MODE_HTMSC_WRAP = 13 ;
+static const uint8_t P9N2_PU_HTM0_HTM_MODE_HTMSC_DIS_TSTAMP = 14 ;
+static const uint8_t P9N2_PU_HTM0_HTM_MODE_HTMSC_SINGLE_TSTAMP = 15 ;
+static const uint8_t P9N2_PU_HTM0_HTM_MODE_HTMSC_SPARE16 = 16 ;
+static const uint8_t P9N2_PU_HTM0_HTM_MODE_HTMSC_MARKERS_ONLY = 17 ;
+static const uint8_t P9N2_PU_HTM0_HTM_MODE_HTMSC_DIS_FORCE_GROUP_SCOPE = 18 ;
+static const uint8_t P9N2_PU_HTM0_HTM_MODE_HTMSC_SYNC_STAMP_FORCE = 19 ;
+static const uint8_t P9N2_PU_HTM0_HTM_MODE_HTMSC_SYNC_STAMP_FORCE_LEN = 3 ;
+static const uint8_t P9N2_PU_HTM0_HTM_MODE_HTMSC_WRITETOIO = 22 ;
+static const uint8_t P9N2_PU_HTM0_HTM_MODE_HTMSC_SPARE23 = 23 ;
+static const uint8_t P9N2_PU_HTM0_HTM_MODE_HTMSC_VGTARGET = 24 ;
+static const uint8_t P9N2_PU_HTM0_HTM_MODE_HTMSC_VGTARGET_LEN = 16 ;
+static const uint8_t P9N2_PU_HTM0_HTM_MODE_HTMSC_SPARE4043 = 40 ;
+static const uint8_t P9N2_PU_HTM0_HTM_MODE_HTMSC_SPARE4043_LEN = 4 ;
+
+static const uint8_t P9N2_PU_HTM1_HTM_MODE_HTMSC_ENABLE = 0 ;
+static const uint8_t P9N2_PU_HTM1_HTM_MODE_HTMSC_CONTENT_SEL = 1 ;
+static const uint8_t P9N2_PU_HTM1_HTM_MODE_HTMSC_CONTENT_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_HTM1_HTM_MODE_HTMSC_SPARE3 = 3 ;
+static const uint8_t P9N2_PU_HTM1_HTM_MODE_HTMSC_CAPTURE = 4 ;
+static const uint8_t P9N2_PU_HTM1_HTM_MODE_HTMSC_CAPTURE_LEN = 9 ;
+static const uint8_t P9N2_PU_HTM1_HTM_MODE_HTMSC_WRAP = 13 ;
+static const uint8_t P9N2_PU_HTM1_HTM_MODE_HTMSC_DIS_TSTAMP = 14 ;
+static const uint8_t P9N2_PU_HTM1_HTM_MODE_HTMSC_SINGLE_TSTAMP = 15 ;
+static const uint8_t P9N2_PU_HTM1_HTM_MODE_HTMSC_SPARE16 = 16 ;
+static const uint8_t P9N2_PU_HTM1_HTM_MODE_HTMSC_MARKERS_ONLY = 17 ;
+static const uint8_t P9N2_PU_HTM1_HTM_MODE_HTMSC_DIS_FORCE_GROUP_SCOPE = 18 ;
+static const uint8_t P9N2_PU_HTM1_HTM_MODE_HTMSC_SYNC_STAMP_FORCE = 19 ;
+static const uint8_t P9N2_PU_HTM1_HTM_MODE_HTMSC_SYNC_STAMP_FORCE_LEN = 3 ;
+static const uint8_t P9N2_PU_HTM1_HTM_MODE_HTMSC_WRITETOIO = 22 ;
+static const uint8_t P9N2_PU_HTM1_HTM_MODE_HTMSC_SPARE23 = 23 ;
+static const uint8_t P9N2_PU_HTM1_HTM_MODE_HTMSC_VGTARGET = 24 ;
+static const uint8_t P9N2_PU_HTM1_HTM_MODE_HTMSC_VGTARGET_LEN = 16 ;
+static const uint8_t P9N2_PU_HTM1_HTM_MODE_HTMSC_SPARE4043 = 40 ;
+static const uint8_t P9N2_PU_HTM1_HTM_MODE_HTMSC_SPARE4043_LEN = 4 ;
+
+static const uint8_t P9N2_PU_HTM0_HTM_STAT_HTMCO_STATUS_SPARE = 0 ;
+static const uint8_t P9N2_PU_HTM0_HTM_STAT_HTMCO_STATUS_SPARE_LEN = 2 ;
+static const uint8_t P9N2_PU_HTM0_HTM_STAT_HTMCO_STATUS_CRESP_OV = 2 ;
+static const uint8_t P9N2_PU_HTM0_HTM_STAT_HTMCO_STATUS_REPAIR = 3 ;
+static const uint8_t P9N2_PU_HTM0_HTM_STAT_HTMCO_STATUS_BUF_WAIT = 4 ;
+static const uint8_t P9N2_PU_HTM0_HTM_STAT_STATUS_TRIG_DROPPED_Q = 5 ;
+static const uint8_t P9N2_PU_HTM0_HTM_STAT_HTMCO_STATUS_ADDR_ERROR = 6 ;
+static const uint8_t P9N2_PU_HTM0_HTM_STAT_STATUS_REC_DROPPED_Q = 7 ;
+static const uint8_t P9N2_PU_HTM0_HTM_STAT_HTMCO_STATUS_INIT = 8 ;
+static const uint8_t P9N2_PU_HTM0_HTM_STAT_HTMCO_STATUS_PREREQ = 9 ;
+static const uint8_t P9N2_PU_HTM0_HTM_STAT_HTMCO_STATUS_READY = 10 ;
+static const uint8_t P9N2_PU_HTM0_HTM_STAT_HTMCO_STATUS_TRACING = 11 ;
+static const uint8_t P9N2_PU_HTM0_HTM_STAT_HTMCO_STATUS_PAUSED = 12 ;
+static const uint8_t P9N2_PU_HTM0_HTM_STAT_HTMCO_STATUS_FLUSH = 13 ;
+static const uint8_t P9N2_PU_HTM0_HTM_STAT_HTMCO_STATUS_COMPLETE = 14 ;
+static const uint8_t P9N2_PU_HTM0_HTM_STAT_HTMCO_STATUS_ENABLE = 15 ;
+static const uint8_t P9N2_PU_HTM0_HTM_STAT_HTMCO_STATUS_STAMP = 16 ;
+static const uint8_t P9N2_PU_HTM0_HTM_STAT_STATUS_SCOM_ERROR = 17 ;
+static const uint8_t P9N2_PU_HTM0_HTM_STAT_STATUS_PARITY_ERROR = 18 ;
+static const uint8_t P9N2_PU_HTM0_HTM_STAT_STATUS_INVALID_CRESP = 19 ;
+
+static const uint8_t P9N2_PU_HTM1_HTM_STAT_HTMCO_STATUS_SPARE = 0 ;
+static const uint8_t P9N2_PU_HTM1_HTM_STAT_HTMCO_STATUS_SPARE_LEN = 2 ;
+static const uint8_t P9N2_PU_HTM1_HTM_STAT_HTMCO_STATUS_CRESP_OV = 2 ;
+static const uint8_t P9N2_PU_HTM1_HTM_STAT_HTMCO_STATUS_REPAIR = 3 ;
+static const uint8_t P9N2_PU_HTM1_HTM_STAT_HTMCO_STATUS_BUF_WAIT = 4 ;
+static const uint8_t P9N2_PU_HTM1_HTM_STAT_STATUS_TRIG_DROPPED_Q = 5 ;
+static const uint8_t P9N2_PU_HTM1_HTM_STAT_HTMCO_STATUS_ADDR_ERROR = 6 ;
+static const uint8_t P9N2_PU_HTM1_HTM_STAT_STATUS_REC_DROPPED_Q = 7 ;
+static const uint8_t P9N2_PU_HTM1_HTM_STAT_HTMCO_STATUS_INIT = 8 ;
+static const uint8_t P9N2_PU_HTM1_HTM_STAT_HTMCO_STATUS_PREREQ = 9 ;
+static const uint8_t P9N2_PU_HTM1_HTM_STAT_HTMCO_STATUS_READY = 10 ;
+static const uint8_t P9N2_PU_HTM1_HTM_STAT_HTMCO_STATUS_TRACING = 11 ;
+static const uint8_t P9N2_PU_HTM1_HTM_STAT_HTMCO_STATUS_PAUSED = 12 ;
+static const uint8_t P9N2_PU_HTM1_HTM_STAT_HTMCO_STATUS_FLUSH = 13 ;
+static const uint8_t P9N2_PU_HTM1_HTM_STAT_HTMCO_STATUS_COMPLETE = 14 ;
+static const uint8_t P9N2_PU_HTM1_HTM_STAT_HTMCO_STATUS_ENABLE = 15 ;
+static const uint8_t P9N2_PU_HTM1_HTM_STAT_HTMCO_STATUS_STAMP = 16 ;
+static const uint8_t P9N2_PU_HTM1_HTM_STAT_STATUS_SCOM_ERROR = 17 ;
+static const uint8_t P9N2_PU_HTM1_HTM_STAT_STATUS_PARITY_ERROR = 18 ;
+static const uint8_t P9N2_PU_HTM1_HTM_STAT_STATUS_INVALID_CRESP = 19 ;
+
+static const uint8_t P9N2_PU_HTM0_HTM_TRIG_HTMSC_START = 0 ;
+static const uint8_t P9N2_PU_HTM0_HTM_TRIG_HTMSC_STOP = 1 ;
+static const uint8_t P9N2_PU_HTM0_HTM_TRIG_HTMSC_PAUSE = 2 ;
+static const uint8_t P9N2_PU_HTM0_HTM_TRIG_HTMSC_STOP_ALT = 3 ;
+static const uint8_t P9N2_PU_HTM0_HTM_TRIG_HTMSC_RESET = 4 ;
+static const uint8_t P9N2_PU_HTM0_HTM_TRIG_HTMSC_MARK_VALID = 5 ;
+static const uint8_t P9N2_PU_HTM0_HTM_TRIG_HTMSC_MARK_TYPE = 6 ;
+static const uint8_t P9N2_PU_HTM0_HTM_TRIG_HTMSC_MARK_TYPE_LEN = 10 ;
+
+static const uint8_t P9N2_PU_HTM1_HTM_TRIG_HTMSC_START = 0 ;
+static const uint8_t P9N2_PU_HTM1_HTM_TRIG_HTMSC_STOP = 1 ;
+static const uint8_t P9N2_PU_HTM1_HTM_TRIG_HTMSC_PAUSE = 2 ;
+static const uint8_t P9N2_PU_HTM1_HTM_TRIG_HTMSC_STOP_ALT = 3 ;
+static const uint8_t P9N2_PU_HTM1_HTM_TRIG_HTMSC_RESET = 4 ;
+static const uint8_t P9N2_PU_HTM1_HTM_TRIG_HTMSC_MARK_VALID = 5 ;
+static const uint8_t P9N2_PU_HTM1_HTM_TRIG_HTMSC_MARK_TYPE = 6 ;
+static const uint8_t P9N2_PU_HTM1_HTM_TRIG_HTMSC_MARK_TYPE_LEN = 10 ;
+
+static const uint8_t P9N2_PU_HTM0_HTM_TTYPEFILT_HTMSC_PAT = 1 ;
+static const uint8_t P9N2_PU_HTM0_HTM_TTYPEFILT_HTMSC_PAT_LEN = 7 ;
+static const uint8_t P9N2_PU_HTM0_HTM_TTYPEFILT_HTMSC_TSIZEFILT_PAT = 8 ;
+static const uint8_t P9N2_PU_HTM0_HTM_TTYPEFILT_HTMSC_TSIZEFILT_PAT_LEN = 8 ;
+static const uint8_t P9N2_PU_HTM0_HTM_TTYPEFILT_HTMSC_MASK = 17 ;
+static const uint8_t P9N2_PU_HTM0_HTM_TTYPEFILT_HTMSC_MASK_LEN = 7 ;
+static const uint8_t P9N2_PU_HTM0_HTM_TTYPEFILT_HTMSC_TSIZEFILT_MASK = 24 ;
+static const uint8_t P9N2_PU_HTM0_HTM_TTYPEFILT_HTMSC_TSIZEFILT_MASK_LEN = 8 ;
+static const uint8_t P9N2_PU_HTM0_HTM_TTYPEFILT_HTMSC_INVERT = 32 ;
+static const uint8_t P9N2_PU_HTM0_HTM_TTYPEFILT_HTMSC_CRESPFILT_INVERT = 33 ;
+
+static const uint8_t P9N2_PU_HTM1_HTM_TTYPEFILT_HTMSC_PAT = 1 ;
+static const uint8_t P9N2_PU_HTM1_HTM_TTYPEFILT_HTMSC_PAT_LEN = 7 ;
+static const uint8_t P9N2_PU_HTM1_HTM_TTYPEFILT_HTMSC_TSIZEFILT_PAT = 8 ;
+static const uint8_t P9N2_PU_HTM1_HTM_TTYPEFILT_HTMSC_TSIZEFILT_PAT_LEN = 8 ;
+static const uint8_t P9N2_PU_HTM1_HTM_TTYPEFILT_HTMSC_MASK = 17 ;
+static const uint8_t P9N2_PU_HTM1_HTM_TTYPEFILT_HTMSC_MASK_LEN = 7 ;
+static const uint8_t P9N2_PU_HTM1_HTM_TTYPEFILT_HTMSC_TSIZEFILT_MASK = 24 ;
+static const uint8_t P9N2_PU_HTM1_HTM_TTYPEFILT_HTMSC_TSIZEFILT_MASK_LEN = 8 ;
+static const uint8_t P9N2_PU_HTM1_HTM_TTYPEFILT_HTMSC_INVERT = 32 ;
+static const uint8_t P9N2_PU_HTM1_HTM_TTYPEFILT_HTMSC_CRESPFILT_INVERT = 33 ;
+
+static const uint8_t P9N2_PU_I2C_BUSY_REGISTER_B_PEEK_DATA1_0 = 32 ;
+static const uint8_t P9N2_PU_I2C_BUSY_REGISTER_B_PEEK_DATA1_0_LEN = 8 ;
+static const uint8_t P9N2_PU_I2C_BUSY_REGISTER_B_LBUS_PARITY_ERR1_0 = 40 ;
+
+static const uint8_t P9N2_PU_I2C_BUSY_REGISTER_C_PEEK_DATA1_1 = 32 ;
+static const uint8_t P9N2_PU_I2C_BUSY_REGISTER_C_PEEK_DATA1_1_LEN = 8 ;
+static const uint8_t P9N2_PU_I2C_BUSY_REGISTER_C_LBUS_PARITY_ERR1_1 = 40 ;
+
+static const uint8_t P9N2_PU_I2C_BUSY_REGISTER_D_PEEK_DATA1_2 = 32 ;
+static const uint8_t P9N2_PU_I2C_BUSY_REGISTER_D_PEEK_DATA1_2_LEN = 8 ;
+static const uint8_t P9N2_PU_I2C_BUSY_REGISTER_D_LBUS_PARITY_ERR1_2 = 40 ;
+
+static const uint8_t P9N2_PU_I2C_BUSY_REGISTER_E_PEEK_DATA1_3 = 32 ;
+static const uint8_t P9N2_PU_I2C_BUSY_REGISTER_E_PEEK_DATA1_3_LEN = 8 ;
+static const uint8_t P9N2_PU_I2C_BUSY_REGISTER_E_LBUS_PARITY_ERR1_3 = 40 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM2_INHIBIT_CONFIG_LFREQ0 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_INHIBIT_CONFIG_LFREQ0_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_INHIBIT_CONFIG_PFREQ0 = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_INHIBIT_CONFIG_PFREQ0_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_INHIBIT_CONFIG_BLOCKY0 = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_INHIBIT_CONFIG_ONESHOT0 = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_INHIBIT_CONFIG_DEST0 = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_INHIBIT_CONFIG_DEST0_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_INHIBIT_CONFIG_LFREQ1 = 16 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_INHIBIT_CONFIG_LFREQ1_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_INHIBIT_CONFIG_PFREQ1 = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_INHIBIT_CONFIG_PFREQ1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_INHIBIT_CONFIG_BLOCKY1 = 22 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_INHIBIT_CONFIG_ONESHOT1 = 23 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_INHIBIT_CONFIG_DEST1 = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_INHIBIT_CONFIG_DEST1_LEN = 8 ;
+
+static const uint8_t P9N2_PU_NPU0_SM0_INHIBIT_CONFIG_LFREQ0 = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM0_INHIBIT_CONFIG_LFREQ0_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM0_INHIBIT_CONFIG_PFREQ0 = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM0_INHIBIT_CONFIG_PFREQ0_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM0_INHIBIT_CONFIG_BLOCKY0 = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM0_INHIBIT_CONFIG_ONESHOT0 = 7 ;
+static const uint8_t P9N2_PU_NPU0_SM0_INHIBIT_CONFIG_DEST0 = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM0_INHIBIT_CONFIG_DEST0_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM0_INHIBIT_CONFIG_LFREQ1 = 16 ;
+static const uint8_t P9N2_PU_NPU0_SM0_INHIBIT_CONFIG_LFREQ1_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM0_INHIBIT_CONFIG_PFREQ1 = 20 ;
+static const uint8_t P9N2_PU_NPU0_SM0_INHIBIT_CONFIG_PFREQ1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM0_INHIBIT_CONFIG_BLOCKY1 = 22 ;
+static const uint8_t P9N2_PU_NPU0_SM0_INHIBIT_CONFIG_ONESHOT1 = 23 ;
+static const uint8_t P9N2_PU_NPU0_SM0_INHIBIT_CONFIG_DEST1 = 24 ;
+static const uint8_t P9N2_PU_NPU0_SM0_INHIBIT_CONFIG_DEST1_LEN = 8 ;
+
+static const uint8_t P9N2_PU_NPU2_NTL0_INHIBIT_CONFIG_LFREQ0 = 0 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_INHIBIT_CONFIG_LFREQ0_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_INHIBIT_CONFIG_PFREQ0 = 4 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_INHIBIT_CONFIG_PFREQ0_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_INHIBIT_CONFIG_BLOCKY0 = 6 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_INHIBIT_CONFIG_ONESHOT0 = 7 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_INHIBIT_CONFIG_DEST0 = 8 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_INHIBIT_CONFIG_DEST0_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_INHIBIT_CONFIG_LFREQ1 = 16 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_INHIBIT_CONFIG_LFREQ1_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_INHIBIT_CONFIG_PFREQ1 = 20 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_INHIBIT_CONFIG_PFREQ1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_INHIBIT_CONFIG_BLOCKY1 = 22 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_INHIBIT_CONFIG_ONESHOT1 = 23 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_INHIBIT_CONFIG_DEST1 = 24 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_INHIBIT_CONFIG_DEST1_LEN = 8 ;
+
+static const uint8_t P9N2_PU_NPU2_SM3_INHIBIT_CONFIG_LFREQ0 = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM3_INHIBIT_CONFIG_LFREQ0_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM3_INHIBIT_CONFIG_PFREQ0 = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM3_INHIBIT_CONFIG_PFREQ0_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM3_INHIBIT_CONFIG_BLOCKY0 = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM3_INHIBIT_CONFIG_ONESHOT0 = 7 ;
+static const uint8_t P9N2_PU_NPU2_SM3_INHIBIT_CONFIG_DEST0 = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM3_INHIBIT_CONFIG_DEST0_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM3_INHIBIT_CONFIG_LFREQ1 = 16 ;
+static const uint8_t P9N2_PU_NPU2_SM3_INHIBIT_CONFIG_LFREQ1_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM3_INHIBIT_CONFIG_PFREQ1 = 20 ;
+static const uint8_t P9N2_PU_NPU2_SM3_INHIBIT_CONFIG_PFREQ1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM3_INHIBIT_CONFIG_BLOCKY1 = 22 ;
+static const uint8_t P9N2_PU_NPU2_SM3_INHIBIT_CONFIG_ONESHOT1 = 23 ;
+static const uint8_t P9N2_PU_NPU2_SM3_INHIBIT_CONFIG_DEST1 = 24 ;
+static const uint8_t P9N2_PU_NPU2_SM3_INHIBIT_CONFIG_DEST1_LEN = 8 ;
+
+static const uint8_t P9N2_PU_NPU0_SM3_INHIBIT_CONFIG_LFREQ0 = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM3_INHIBIT_CONFIG_LFREQ0_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM3_INHIBIT_CONFIG_PFREQ0 = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM3_INHIBIT_CONFIG_PFREQ0_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM3_INHIBIT_CONFIG_BLOCKY0 = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM3_INHIBIT_CONFIG_ONESHOT0 = 7 ;
+static const uint8_t P9N2_PU_NPU0_SM3_INHIBIT_CONFIG_DEST0 = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM3_INHIBIT_CONFIG_DEST0_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM3_INHIBIT_CONFIG_LFREQ1 = 16 ;
+static const uint8_t P9N2_PU_NPU0_SM3_INHIBIT_CONFIG_LFREQ1_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM3_INHIBIT_CONFIG_PFREQ1 = 20 ;
+static const uint8_t P9N2_PU_NPU0_SM3_INHIBIT_CONFIG_PFREQ1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM3_INHIBIT_CONFIG_BLOCKY1 = 22 ;
+static const uint8_t P9N2_PU_NPU0_SM3_INHIBIT_CONFIG_ONESHOT1 = 23 ;
+static const uint8_t P9N2_PU_NPU0_SM3_INHIBIT_CONFIG_DEST1 = 24 ;
+static const uint8_t P9N2_PU_NPU0_SM3_INHIBIT_CONFIG_DEST1_LEN = 8 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM0_INHIBIT_CONFIG_LFREQ0 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_INHIBIT_CONFIG_LFREQ0_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_INHIBIT_CONFIG_PFREQ0 = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_INHIBIT_CONFIG_PFREQ0_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_INHIBIT_CONFIG_BLOCKY0 = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_INHIBIT_CONFIG_ONESHOT0 = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_INHIBIT_CONFIG_DEST0 = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_INHIBIT_CONFIG_DEST0_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_INHIBIT_CONFIG_LFREQ1 = 16 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_INHIBIT_CONFIG_LFREQ1_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_INHIBIT_CONFIG_PFREQ1 = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_INHIBIT_CONFIG_PFREQ1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_INHIBIT_CONFIG_BLOCKY1 = 22 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_INHIBIT_CONFIG_ONESHOT1 = 23 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_INHIBIT_CONFIG_DEST1 = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_INHIBIT_CONFIG_DEST1_LEN = 8 ;
+
+static const uint8_t P9N2_PU_NPU0_INHIBIT_CONFIG_LFREQ0 = 0 ;
+static const uint8_t P9N2_PU_NPU0_INHIBIT_CONFIG_LFREQ0_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_INHIBIT_CONFIG_PFREQ0 = 4 ;
+static const uint8_t P9N2_PU_NPU0_INHIBIT_CONFIG_PFREQ0_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU0_INHIBIT_CONFIG_BLOCKY0 = 6 ;
+static const uint8_t P9N2_PU_NPU0_INHIBIT_CONFIG_ONESHOT0 = 7 ;
+static const uint8_t P9N2_PU_NPU0_INHIBIT_CONFIG_DEST0 = 8 ;
+static const uint8_t P9N2_PU_NPU0_INHIBIT_CONFIG_DEST0_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU0_INHIBIT_CONFIG_LFREQ1 = 16 ;
+static const uint8_t P9N2_PU_NPU0_INHIBIT_CONFIG_LFREQ1_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_INHIBIT_CONFIG_PFREQ1 = 20 ;
+static const uint8_t P9N2_PU_NPU0_INHIBIT_CONFIG_PFREQ1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU0_INHIBIT_CONFIG_BLOCKY1 = 22 ;
+static const uint8_t P9N2_PU_NPU0_INHIBIT_CONFIG_ONESHOT1 = 23 ;
+static const uint8_t P9N2_PU_NPU0_INHIBIT_CONFIG_DEST1 = 24 ;
+static const uint8_t P9N2_PU_NPU0_INHIBIT_CONFIG_DEST1_LEN = 8 ;
+
+static const uint8_t P9N2_PU_NPU2_SM2_INHIBIT_CONFIG_LFREQ0 = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM2_INHIBIT_CONFIG_LFREQ0_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM2_INHIBIT_CONFIG_PFREQ0 = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM2_INHIBIT_CONFIG_PFREQ0_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM2_INHIBIT_CONFIG_BLOCKY0 = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM2_INHIBIT_CONFIG_ONESHOT0 = 7 ;
+static const uint8_t P9N2_PU_NPU2_SM2_INHIBIT_CONFIG_DEST0 = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM2_INHIBIT_CONFIG_DEST0_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM2_INHIBIT_CONFIG_LFREQ1 = 16 ;
+static const uint8_t P9N2_PU_NPU2_SM2_INHIBIT_CONFIG_LFREQ1_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM2_INHIBIT_CONFIG_PFREQ1 = 20 ;
+static const uint8_t P9N2_PU_NPU2_SM2_INHIBIT_CONFIG_PFREQ1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM2_INHIBIT_CONFIG_BLOCKY1 = 22 ;
+static const uint8_t P9N2_PU_NPU2_SM2_INHIBIT_CONFIG_ONESHOT1 = 23 ;
+static const uint8_t P9N2_PU_NPU2_SM2_INHIBIT_CONFIG_DEST1 = 24 ;
+static const uint8_t P9N2_PU_NPU2_SM2_INHIBIT_CONFIG_DEST1_LEN = 8 ;
+
+static const uint8_t P9N2__CTL_INHIBIT_CONFIG_LFREQ = 0 ;
+static const uint8_t P9N2__CTL_INHIBIT_CONFIG_LFREQ_LEN = 4 ;
+static const uint8_t P9N2__CTL_INHIBIT_CONFIG_IFREQ = 4 ;
+static const uint8_t P9N2__CTL_INHIBIT_CONFIG_DEST = 5 ;
+static const uint8_t P9N2__CTL_INHIBIT_CONFIG_DEST_LEN = 3 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_INHIBIT_CONFIG_LFREQ0 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_INHIBIT_CONFIG_LFREQ0_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_INHIBIT_CONFIG_PFREQ0 = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_INHIBIT_CONFIG_PFREQ0_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_INHIBIT_CONFIG_BLOCKY0 = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_INHIBIT_CONFIG_ONESHOT0 = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_INHIBIT_CONFIG_DEST0 = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_INHIBIT_CONFIG_DEST0_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_INHIBIT_CONFIG_LFREQ1 = 16 ;
+static const uint8_t P9N2_PU_NPU_MSC_INHIBIT_CONFIG_LFREQ1_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_INHIBIT_CONFIG_PFREQ1 = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_INHIBIT_CONFIG_PFREQ1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_INHIBIT_CONFIG_BLOCKY1 = 22 ;
+static const uint8_t P9N2_PU_NPU_MSC_INHIBIT_CONFIG_ONESHOT1 = 23 ;
+static const uint8_t P9N2_PU_NPU_MSC_INHIBIT_CONFIG_DEST1 = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_INHIBIT_CONFIG_DEST1_LEN = 8 ;
+
+static const uint8_t P9N2_PU_NPU0_SM2_INHIBIT_CONFIG_LFREQ0 = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM2_INHIBIT_CONFIG_LFREQ0_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM2_INHIBIT_CONFIG_PFREQ0 = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM2_INHIBIT_CONFIG_PFREQ0_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM2_INHIBIT_CONFIG_BLOCKY0 = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM2_INHIBIT_CONFIG_ONESHOT0 = 7 ;
+static const uint8_t P9N2_PU_NPU0_SM2_INHIBIT_CONFIG_DEST0 = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM2_INHIBIT_CONFIG_DEST0_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM2_INHIBIT_CONFIG_LFREQ1 = 16 ;
+static const uint8_t P9N2_PU_NPU0_SM2_INHIBIT_CONFIG_LFREQ1_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM2_INHIBIT_CONFIG_PFREQ1 = 20 ;
+static const uint8_t P9N2_PU_NPU0_SM2_INHIBIT_CONFIG_PFREQ1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM2_INHIBIT_CONFIG_BLOCKY1 = 22 ;
+static const uint8_t P9N2_PU_NPU0_SM2_INHIBIT_CONFIG_ONESHOT1 = 23 ;
+static const uint8_t P9N2_PU_NPU0_SM2_INHIBIT_CONFIG_DEST1 = 24 ;
+static const uint8_t P9N2_PU_NPU0_SM2_INHIBIT_CONFIG_DEST1_LEN = 8 ;
+
+static const uint8_t P9N2_PU_NPU2_SM0_INHIBIT_CONFIG_LFREQ0 = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM0_INHIBIT_CONFIG_LFREQ0_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM0_INHIBIT_CONFIG_PFREQ0 = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM0_INHIBIT_CONFIG_PFREQ0_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM0_INHIBIT_CONFIG_BLOCKY0 = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM0_INHIBIT_CONFIG_ONESHOT0 = 7 ;
+static const uint8_t P9N2_PU_NPU2_SM0_INHIBIT_CONFIG_DEST0 = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM0_INHIBIT_CONFIG_DEST0_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM0_INHIBIT_CONFIG_LFREQ1 = 16 ;
+static const uint8_t P9N2_PU_NPU2_SM0_INHIBIT_CONFIG_LFREQ1_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM0_INHIBIT_CONFIG_PFREQ1 = 20 ;
+static const uint8_t P9N2_PU_NPU2_SM0_INHIBIT_CONFIG_PFREQ1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM0_INHIBIT_CONFIG_BLOCKY1 = 22 ;
+static const uint8_t P9N2_PU_NPU2_SM0_INHIBIT_CONFIG_ONESHOT1 = 23 ;
+static const uint8_t P9N2_PU_NPU2_SM0_INHIBIT_CONFIG_DEST1 = 24 ;
+static const uint8_t P9N2_PU_NPU2_SM0_INHIBIT_CONFIG_DEST1_LEN = 8 ;
+
+static const uint8_t P9N2_NV_INHIBIT_CONFIG_LFREQ0 = 0 ;
+static const uint8_t P9N2_NV_INHIBIT_CONFIG_LFREQ0_LEN = 4 ;
+static const uint8_t P9N2_NV_INHIBIT_CONFIG_PFREQ0 = 4 ;
+static const uint8_t P9N2_NV_INHIBIT_CONFIG_PFREQ0_LEN = 2 ;
+static const uint8_t P9N2_NV_INHIBIT_CONFIG_BLOCKY0 = 6 ;
+static const uint8_t P9N2_NV_INHIBIT_CONFIG_ONESHOT0 = 7 ;
+static const uint8_t P9N2_NV_INHIBIT_CONFIG_DEST0 = 8 ;
+static const uint8_t P9N2_NV_INHIBIT_CONFIG_DEST0_LEN = 8 ;
+static const uint8_t P9N2_NV_INHIBIT_CONFIG_LFREQ1 = 16 ;
+static const uint8_t P9N2_NV_INHIBIT_CONFIG_LFREQ1_LEN = 4 ;
+static const uint8_t P9N2_NV_INHIBIT_CONFIG_PFREQ1 = 20 ;
+static const uint8_t P9N2_NV_INHIBIT_CONFIG_PFREQ1_LEN = 2 ;
+static const uint8_t P9N2_NV_INHIBIT_CONFIG_BLOCKY1 = 22 ;
+static const uint8_t P9N2_NV_INHIBIT_CONFIG_ONESHOT1 = 23 ;
+static const uint8_t P9N2_NV_INHIBIT_CONFIG_DEST1 = 24 ;
+static const uint8_t P9N2_NV_INHIBIT_CONFIG_DEST1_LEN = 8 ;
+
+static const uint8_t P9N2_PU_NPU2_INHIBIT_CONFIG_LFREQ0 = 0 ;
+static const uint8_t P9N2_PU_NPU2_INHIBIT_CONFIG_LFREQ0_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_INHIBIT_CONFIG_PFREQ0 = 4 ;
+static const uint8_t P9N2_PU_NPU2_INHIBIT_CONFIG_PFREQ0_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_INHIBIT_CONFIG_BLOCKY0 = 6 ;
+static const uint8_t P9N2_PU_NPU2_INHIBIT_CONFIG_ONESHOT0 = 7 ;
+static const uint8_t P9N2_PU_NPU2_INHIBIT_CONFIG_DEST0 = 8 ;
+static const uint8_t P9N2_PU_NPU2_INHIBIT_CONFIG_DEST0_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU2_INHIBIT_CONFIG_LFREQ1 = 16 ;
+static const uint8_t P9N2_PU_NPU2_INHIBIT_CONFIG_LFREQ1_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_INHIBIT_CONFIG_PFREQ1 = 20 ;
+static const uint8_t P9N2_PU_NPU2_INHIBIT_CONFIG_PFREQ1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_INHIBIT_CONFIG_BLOCKY1 = 22 ;
+static const uint8_t P9N2_PU_NPU2_INHIBIT_CONFIG_ONESHOT1 = 23 ;
+static const uint8_t P9N2_PU_NPU2_INHIBIT_CONFIG_DEST1 = 24 ;
+static const uint8_t P9N2_PU_NPU2_INHIBIT_CONFIG_DEST1_LEN = 8 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM3_INHIBIT_CONFIG_LFREQ0 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_INHIBIT_CONFIG_LFREQ0_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_INHIBIT_CONFIG_PFREQ0 = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_INHIBIT_CONFIG_PFREQ0_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_INHIBIT_CONFIG_BLOCKY0 = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_INHIBIT_CONFIG_ONESHOT0 = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_INHIBIT_CONFIG_DEST0 = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_INHIBIT_CONFIG_DEST0_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_INHIBIT_CONFIG_LFREQ1 = 16 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_INHIBIT_CONFIG_LFREQ1_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_INHIBIT_CONFIG_PFREQ1 = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_INHIBIT_CONFIG_PFREQ1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_INHIBIT_CONFIG_BLOCKY1 = 22 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_INHIBIT_CONFIG_ONESHOT1 = 23 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_INHIBIT_CONFIG_DEST1 = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_INHIBIT_CONFIG_DEST1_LEN = 8 ;
+
+static const uint8_t P9N2_PEC_INJECT_REG_THERM_TRIP = 0 ;
+static const uint8_t P9N2_PEC_INJECT_REG_THERM_TRIP_LEN = 2 ;
+static const uint8_t P9N2_PEC_INJECT_REG_THERM_MODE = 2 ;
+static const uint8_t P9N2_PEC_INJECT_REG_THERM_MODE_LEN = 2 ;
+
+static const uint8_t P9N2_PHB_INTBAR_REG_PE_INT_BAR = 0 ;
+static const uint8_t P9N2_PHB_INTBAR_REG_PE_INT_BAR_LEN = 28 ;
+
+static const uint8_t P9N2_PEC_STACK0_INTBAR_REG_PE_INT_BAR = 0 ;
+static const uint8_t P9N2_PEC_STACK0_INTBAR_REG_PE_INT_BAR_LEN = 28 ;
+
+static const uint8_t P9N2_PU_INTERRUPTS_B_PEEK_DATA1_0 = 32 ;
+static const uint8_t P9N2_PU_INTERRUPTS_B_PEEK_DATA1_0_LEN = 8 ;
+static const uint8_t P9N2_PU_INTERRUPTS_B_LBUS_PARITY_ERR1_0 = 40 ;
+
+static const uint8_t P9N2_PU_INTERRUPTS_C_PEEK_DATA1_1 = 32 ;
+static const uint8_t P9N2_PU_INTERRUPTS_C_PEEK_DATA1_1_LEN = 8 ;
+static const uint8_t P9N2_PU_INTERRUPTS_C_LBUS_PARITY_ERR1_1 = 40 ;
+
+static const uint8_t P9N2_PU_INTERRUPTS_D_PEEK_DATA1_2 = 32 ;
+static const uint8_t P9N2_PU_INTERRUPTS_D_PEEK_DATA1_2_LEN = 8 ;
+static const uint8_t P9N2_PU_INTERRUPTS_D_LBUS_PARITY_ERR1_2 = 40 ;
+
+static const uint8_t P9N2_PU_INTERRUPTS_E_PEEK_DATA1_3 = 32 ;
+static const uint8_t P9N2_PU_INTERRUPTS_E_PEEK_DATA1_3_LEN = 8 ;
+static const uint8_t P9N2_PU_INTERRUPTS_E_LBUS_PARITY_ERR1_3 = 40 ;
+
+static const uint8_t P9N2_PU_INTERRUPT_COND_B_INVALID_CMD_0 = 16 ;
+static const uint8_t P9N2_PU_INTERRUPT_COND_B_LBUS_PARITY_ERROR_0 = 17 ;
+static const uint8_t P9N2_PU_INTERRUPT_COND_B_BE_OV_ERROR_0 = 18 ;
+static const uint8_t P9N2_PU_INTERRUPT_COND_B_BE_ACC_ERROR_0 = 19 ;
+static const uint8_t P9N2_PU_INTERRUPT_COND_B_ARBITRATION_LOST_ERROR_0 = 20 ;
+static const uint8_t P9N2_PU_INTERRUPT_COND_B_NACK_RECEIVED_ERROR_0 = 21 ;
+static const uint8_t P9N2_PU_INTERRUPT_COND_B_DATA_REQUEST_0 = 22 ;
+static const uint8_t P9N2_PU_INTERRUPT_COND_B_STOP_ERROR_0 = 24 ;
+static const uint8_t P9N2_PU_INTERRUPT_COND_B_PEEK_DATA1_0 = 32 ;
+static const uint8_t P9N2_PU_INTERRUPT_COND_B_PEEK_DATA1_0_LEN = 8 ;
+static const uint8_t P9N2_PU_INTERRUPT_COND_B_LBUS_PARITY_ERR1_0 = 40 ;
+
+static const uint8_t P9N2_PU_INTERRUPT_COND_C_INVALID_CMD_1 = 16 ;
+static const uint8_t P9N2_PU_INTERRUPT_COND_C_LBUS_PARITY_ERROR_1 = 17 ;
+static const uint8_t P9N2_PU_INTERRUPT_COND_C_BE_OV_ERROR_1 = 18 ;
+static const uint8_t P9N2_PU_INTERRUPT_COND_C_BE_ACC_ERROR_1 = 19 ;
+static const uint8_t P9N2_PU_INTERRUPT_COND_C_ARBITRATION_LOST_ERROR_1 = 20 ;
+static const uint8_t P9N2_PU_INTERRUPT_COND_C_NACK_RECEIVED_ERROR_1 = 21 ;
+static const uint8_t P9N2_PU_INTERRUPT_COND_C_DATA_REQUEST_1 = 22 ;
+static const uint8_t P9N2_PU_INTERRUPT_COND_C_STOP_ERROR_1 = 24 ;
+static const uint8_t P9N2_PU_INTERRUPT_COND_C_PEEK_DATA1_1 = 32 ;
+static const uint8_t P9N2_PU_INTERRUPT_COND_C_PEEK_DATA1_1_LEN = 8 ;
+static const uint8_t P9N2_PU_INTERRUPT_COND_C_LBUS_PARITY_ERR1_1 = 40 ;
+
+static const uint8_t P9N2_PU_INTERRUPT_COND_D_INVALID_CMD_2 = 16 ;
+static const uint8_t P9N2_PU_INTERRUPT_COND_D_LBUS_PARITY_ERROR_2 = 17 ;
+static const uint8_t P9N2_PU_INTERRUPT_COND_D_BE_OV_ERROR_2 = 18 ;
+static const uint8_t P9N2_PU_INTERRUPT_COND_D_BE_ACC_ERROR_2 = 19 ;
+static const uint8_t P9N2_PU_INTERRUPT_COND_D_ARBITRATION_LOST_ERROR_2 = 20 ;
+static const uint8_t P9N2_PU_INTERRUPT_COND_D_NACK_RECEIVED_ERROR_2 = 21 ;
+static const uint8_t P9N2_PU_INTERRUPT_COND_D_DATA_REQUEST_2 = 22 ;
+static const uint8_t P9N2_PU_INTERRUPT_COND_D_STOP_ERROR_2 = 24 ;
+static const uint8_t P9N2_PU_INTERRUPT_COND_D_PEEK_DATA1_2 = 32 ;
+static const uint8_t P9N2_PU_INTERRUPT_COND_D_PEEK_DATA1_2_LEN = 8 ;
+static const uint8_t P9N2_PU_INTERRUPT_COND_D_LBUS_PARITY_ERR1_2 = 40 ;
+
+static const uint8_t P9N2_PU_INTERRUPT_COND_E_INVALID_CMD_3 = 16 ;
+static const uint8_t P9N2_PU_INTERRUPT_COND_E_LBUS_PARITY_ERROR_3 = 17 ;
+static const uint8_t P9N2_PU_INTERRUPT_COND_E_BE_OV_ERROR_3 = 18 ;
+static const uint8_t P9N2_PU_INTERRUPT_COND_E_BE_ACC_ERROR_3 = 19 ;
+static const uint8_t P9N2_PU_INTERRUPT_COND_E_ARBITRATION_LOST_ERROR_3 = 20 ;
+static const uint8_t P9N2_PU_INTERRUPT_COND_E_NACK_RECEIVED_ERROR_3 = 21 ;
+static const uint8_t P9N2_PU_INTERRUPT_COND_E_DATA_REQUEST_3 = 22 ;
+static const uint8_t P9N2_PU_INTERRUPT_COND_E_STOP_ERROR_3 = 24 ;
+static const uint8_t P9N2_PU_INTERRUPT_COND_E_PEEK_DATA1_3 = 32 ;
+static const uint8_t P9N2_PU_INTERRUPT_COND_E_PEEK_DATA1_3_LEN = 8 ;
+static const uint8_t P9N2_PU_INTERRUPT_COND_E_LBUS_PARITY_ERR1_3 = 40 ;
+
+static const uint8_t P9N2_PU_INTERRUPT_MASK_REGISTER_B_INT_0 = 16 ;
+static const uint8_t P9N2_PU_INTERRUPT_MASK_REGISTER_B_INT_0_LEN = 16 ;
+
+static const uint8_t P9N2_PU_INTERRUPT_MASK_REGISTER_C_INT_1 = 16 ;
+static const uint8_t P9N2_PU_INTERRUPT_MASK_REGISTER_C_INT_1_LEN = 16 ;
+
+static const uint8_t P9N2_PU_INTERRUPT_MASK_REGISTER_D_INT_2 = 16 ;
+static const uint8_t P9N2_PU_INTERRUPT_MASK_REGISTER_D_INT_2_LEN = 16 ;
+
+static const uint8_t P9N2_PU_INTERRUPT_MASK_REGISTER_E_INT_3 = 16 ;
+static const uint8_t P9N2_PU_INTERRUPT_MASK_REGISTER_E_INT_3_LEN = 16 ;
+
+static const uint8_t P9N2_PU_INTERRUPT_MASK_REGISTER_READ_B_INT_0 = 16 ;
+static const uint8_t P9N2_PU_INTERRUPT_MASK_REGISTER_READ_B_INT_0_LEN = 16 ;
+static const uint8_t P9N2_PU_INTERRUPT_MASK_REGISTER_READ_B_PEEK_DATA1_0 = 32 ;
+static const uint8_t P9N2_PU_INTERRUPT_MASK_REGISTER_READ_B_PEEK_DATA1_0_LEN = 8 ;
+static const uint8_t P9N2_PU_INTERRUPT_MASK_REGISTER_READ_B_LBUS_PARITY_ERR1_0 = 40 ;
+
+static const uint8_t P9N2_PU_INTERRUPT_MASK_REGISTER_READ_C_INT_1 = 16 ;
+static const uint8_t P9N2_PU_INTERRUPT_MASK_REGISTER_READ_C_INT_1_LEN = 16 ;
+static const uint8_t P9N2_PU_INTERRUPT_MASK_REGISTER_READ_C_PEEK_DATA1_1 = 32 ;
+static const uint8_t P9N2_PU_INTERRUPT_MASK_REGISTER_READ_C_PEEK_DATA1_1_LEN = 8 ;
+static const uint8_t P9N2_PU_INTERRUPT_MASK_REGISTER_READ_C_LBUS_PARITY_ERR1_1 = 40 ;
+
+static const uint8_t P9N2_PU_INTERRUPT_MASK_REGISTER_READ_D_INT_2 = 16 ;
+static const uint8_t P9N2_PU_INTERRUPT_MASK_REGISTER_READ_D_INT_2_LEN = 16 ;
+static const uint8_t P9N2_PU_INTERRUPT_MASK_REGISTER_READ_D_PEEK_DATA1_2 = 32 ;
+static const uint8_t P9N2_PU_INTERRUPT_MASK_REGISTER_READ_D_PEEK_DATA1_2_LEN = 8 ;
+static const uint8_t P9N2_PU_INTERRUPT_MASK_REGISTER_READ_D_LBUS_PARITY_ERR1_2 = 40 ;
+
+static const uint8_t P9N2_PU_INTERRUPT_MASK_REGISTER_READ_E_INT_3 = 16 ;
+static const uint8_t P9N2_PU_INTERRUPT_MASK_REGISTER_READ_E_INT_3_LEN = 16 ;
+static const uint8_t P9N2_PU_INTERRUPT_MASK_REGISTER_READ_E_PEEK_DATA1_3 = 32 ;
+static const uint8_t P9N2_PU_INTERRUPT_MASK_REGISTER_READ_E_PEEK_DATA1_3_LEN = 8 ;
+static const uint8_t P9N2_PU_INTERRUPT_MASK_REGISTER_READ_E_LBUS_PARITY_ERR1_3 = 40 ;
+
+static const uint8_t P9N2__CTL_INT_0_CONFIG_0 = 0 ;
+static const uint8_t P9N2__CTL_INT_0_CONFIG_0_LEN = 64 ;
+
+static const uint8_t P9N2__CTL_INT_1_CONFIG_1 = 0 ;
+static const uint8_t P9N2__CTL_INT_1_CONFIG_1_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU_SM0_INT_2_CONFIG_2 = 0 ;
+static const uint8_t P9N2_PU_NPU_SM0_INT_2_CONFIG_2_LEN = 64 ;
+
+static const uint8_t P9N2__CTL_INT_BAR_CONFIG = 0 ;
+static const uint8_t P9N2__CTL_INT_BAR_CONFIG_LEN = 39 ;
+
+static const uint8_t P9N2_PU_INT_CQ_ACTION0_ACTION0 = 0 ;
+static const uint8_t P9N2_PU_INT_CQ_ACTION0_ACTION0_LEN = 64 ;
+
+static const uint8_t P9N2_PU_INT_CQ_ACTION1_ACTION1 = 0 ;
+static const uint8_t P9N2_PU_INT_CQ_ACTION1_ACTION1_LEN = 64 ;
+
+static const uint8_t P9N2_PU_INT_CQ_AIB_CTL_DIS_ECCCHK_IN = 0 ;
+static const uint8_t P9N2_PU_INT_CQ_AIB_CTL_EXTRA_CMD_SPACING_0_2 = 1 ;
+static const uint8_t P9N2_PU_INT_CQ_AIB_CTL_EXTRA_CMD_SPACING_0_2_LEN = 3 ;
+static const uint8_t P9N2_PU_INT_CQ_AIB_CTL_EXTRA_DAT_SPACING_0_3 = 4 ;
+static const uint8_t P9N2_PU_INT_CQ_AIB_CTL_EXTRA_DAT_SPACING_0_3_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_CQ_AIB_CTL_PC_PRIORITY_LIMIT_0_3 = 8 ;
+static const uint8_t P9N2_PU_INT_CQ_AIB_CTL_PC_PRIORITY_LIMIT_0_3_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_CQ_AIB_CTL_VC_PRIORITY_LIMIT_0_3 = 12 ;
+static const uint8_t P9N2_PU_INT_CQ_AIB_CTL_VC_PRIORITY_LIMIT_0_3_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_CQ_AIB_CTL_PRIORITY_LIMIT_0_3 = 16 ;
+static const uint8_t P9N2_PU_INT_CQ_AIB_CTL_PRIORITY_LIMIT_0_3_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_CQ_AIB_CTL_BLOCK_CMD_OVERLAP = 20 ;
+static const uint8_t P9N2_PU_INT_CQ_AIB_CTL_RESERVED_21_31 = 21 ;
+static const uint8_t P9N2_PU_INT_CQ_AIB_CTL_RESERVED_21_31_LEN = 11 ;
+static const uint8_t P9N2_PU_INT_CQ_AIB_CTL_CH0_CMD_CREDITS_0_5 = 32 ;
+static const uint8_t P9N2_PU_INT_CQ_AIB_CTL_CH0_CMD_CREDITS_0_5_LEN = 6 ;
+static const uint8_t P9N2_PU_INT_CQ_AIB_CTL_CH1_CMD_CREDITS_0_5 = 38 ;
+static const uint8_t P9N2_PU_INT_CQ_AIB_CTL_CH1_CMD_CREDITS_0_5_LEN = 6 ;
+static const uint8_t P9N2_PU_INT_CQ_AIB_CTL_CH1_DAT_CREDITS_0_5 = 44 ;
+static const uint8_t P9N2_PU_INT_CQ_AIB_CTL_CH1_DAT_CREDITS_0_5_LEN = 6 ;
+static const uint8_t P9N2_PU_INT_CQ_AIB_CTL_CH2_CMD_CREDITS_PC_0_5 = 50 ;
+static const uint8_t P9N2_PU_INT_CQ_AIB_CTL_CH2_CMD_CREDITS_PC_0_5_LEN = 6 ;
+static const uint8_t P9N2_PU_INT_CQ_AIB_CTL_CH2_CMD_CREDITS_VC_0_5 = 56 ;
+static const uint8_t P9N2_PU_INT_CQ_AIB_CTL_CH2_CMD_CREDITS_VC_0_5_LEN = 6 ;
+static const uint8_t P9N2_PU_INT_CQ_AIB_CTL_RESERVED_62 = 62 ;
+static const uint8_t P9N2_PU_INT_CQ_AIB_CTL_REINIT_CREDITS = 63 ;
+
+static const uint8_t P9N2_PU_INT_CQ_CFG_LDQ_LDQ_IVE_MIN_0_4 = 0 ;
+static const uint8_t P9N2_PU_INT_CQ_CFG_LDQ_LDQ_IVE_MIN_0_4_LEN = 5 ;
+static const uint8_t P9N2_PU_INT_CQ_CFG_LDQ_LDQ_IVE_MAX_0_4 = 5 ;
+static const uint8_t P9N2_PU_INT_CQ_CFG_LDQ_LDQ_IVE_MAX_0_4_LEN = 5 ;
+static const uint8_t P9N2_PU_INT_CQ_CFG_LDQ_LDQ_EQD_MIN_0_4 = 10 ;
+static const uint8_t P9N2_PU_INT_CQ_CFG_LDQ_LDQ_EQD_MIN_0_4_LEN = 5 ;
+static const uint8_t P9N2_PU_INT_CQ_CFG_LDQ_LDQ_EQD_MAX_0_4 = 15 ;
+static const uint8_t P9N2_PU_INT_CQ_CFG_LDQ_LDQ_EQD_MAX_0_4_LEN = 5 ;
+static const uint8_t P9N2_PU_INT_CQ_CFG_LDQ_LDQ_THR_MIN_0_4 = 20 ;
+static const uint8_t P9N2_PU_INT_CQ_CFG_LDQ_LDQ_THR_MIN_0_4_LEN = 5 ;
+static const uint8_t P9N2_PU_INT_CQ_CFG_LDQ_LDQ_THR_MAX_0_4 = 25 ;
+static const uint8_t P9N2_PU_INT_CQ_CFG_LDQ_LDQ_THR_MAX_0_4_LEN = 5 ;
+static const uint8_t P9N2_PU_INT_CQ_CFG_LDQ_LDQ_VPC_MIN_0_4 = 30 ;
+static const uint8_t P9N2_PU_INT_CQ_CFG_LDQ_LDQ_VPC_MIN_0_4_LEN = 5 ;
+static const uint8_t P9N2_PU_INT_CQ_CFG_LDQ_LDQ_VPC_MAX_0_4 = 35 ;
+static const uint8_t P9N2_PU_INT_CQ_CFG_LDQ_LDQ_VPC_MAX_0_4_LEN = 5 ;
+static const uint8_t P9N2_PU_INT_CQ_CFG_LDQ_LDQ_REG_MIN_0_4 = 40 ;
+static const uint8_t P9N2_PU_INT_CQ_CFG_LDQ_LDQ_REG_MIN_0_4_LEN = 5 ;
+static const uint8_t P9N2_PU_INT_CQ_CFG_LDQ_LDQ_REG_MAX_0_4 = 45 ;
+static const uint8_t P9N2_PU_INT_CQ_CFG_LDQ_LDQ_REG_MAX_0_4_LEN = 5 ;
+static const uint8_t P9N2_PU_INT_CQ_CFG_LDQ_LDQ_REG_ORDER_ALL = 50 ;
+static const uint8_t P9N2_PU_INT_CQ_CFG_LDQ_RESERVED_51_63 = 51 ;
+static const uint8_t P9N2_PU_INT_CQ_CFG_LDQ_RESERVED_51_63_LEN = 13 ;
+
+static const uint8_t P9N2_PU_INT_CQ_CFG_PB_GEN_ADDR_BAR_MODE = 0 ;
+static const uint8_t P9N2_PU_INT_CQ_CFG_PB_GEN_PUMP_MODE = 1 ;
+static const uint8_t P9N2_PU_INT_CQ_CFG_PB_GEN_PHYP_SCOPE = 2 ;
+static const uint8_t P9N2_PU_INT_CQ_CFG_PB_GEN_INIT = 3 ;
+static const uint8_t P9N2_PU_INT_CQ_CFG_PB_GEN_MODE_128K_VP = 4 ;
+static const uint8_t P9N2_PU_INT_CQ_CFG_PB_GEN_ADDR_EXT_MASK_EN_15_21 = 5 ;
+static const uint8_t P9N2_PU_INT_CQ_CFG_PB_GEN_ADDR_EXT_MASK_EN_15_21_LEN = 7 ;
+static const uint8_t P9N2_PU_INT_CQ_CFG_PB_GEN_SMF_CONFIG_0_1 = 12 ;
+static const uint8_t P9N2_PU_INT_CQ_CFG_PB_GEN_SMF_CONFIG_0_1_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_CQ_CFG_PB_GEN_ADDR_OPT = 14 ;
+static const uint8_t P9N2_PU_INT_CQ_CFG_PB_GEN_ADDR_OPT_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_CQ_CFG_PB_GEN_RESERVED_16 = 16 ;
+static const uint8_t P9N2_PU_INT_CQ_CFG_PB_GEN_GROUP_ID_0_3 = 17 ;
+static const uint8_t P9N2_PU_INT_CQ_CFG_PB_GEN_GROUP_ID_0_3_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_CQ_CFG_PB_GEN_CHIP_ID_0_2 = 21 ;
+static const uint8_t P9N2_PU_INT_CQ_CFG_PB_GEN_CHIP_ID_0_2_LEN = 3 ;
+static const uint8_t P9N2_PU_INT_CQ_CFG_PB_GEN_UNIT_ID_0_7 = 24 ;
+static const uint8_t P9N2_PU_INT_CQ_CFG_PB_GEN_UNIT_ID_0_7_LEN = 8 ;
+
+static const uint8_t P9N2_PU_INT_CQ_CFG_STQ1_STQ_IPI_MIN_0_4 = 0 ;
+static const uint8_t P9N2_PU_INT_CQ_CFG_STQ1_STQ_IPI_MIN_0_4_LEN = 5 ;
+static const uint8_t P9N2_PU_INT_CQ_CFG_STQ1_STQ_IPI_MAX_0_4 = 5 ;
+static const uint8_t P9N2_PU_INT_CQ_CFG_STQ1_STQ_IPI_MAX_0_4_LEN = 5 ;
+static const uint8_t P9N2_PU_INT_CQ_CFG_STQ1_STQ_HW_MIN_0_4 = 10 ;
+static const uint8_t P9N2_PU_INT_CQ_CFG_STQ1_STQ_HW_MIN_0_4_LEN = 5 ;
+static const uint8_t P9N2_PU_INT_CQ_CFG_STQ1_STQ_HW_MAX_0_4 = 15 ;
+static const uint8_t P9N2_PU_INT_CQ_CFG_STQ1_STQ_HW_MAX_0_4_LEN = 5 ;
+static const uint8_t P9N2_PU_INT_CQ_CFG_STQ1_STQ_OS_MIN_0_4 = 20 ;
+static const uint8_t P9N2_PU_INT_CQ_CFG_STQ1_STQ_OS_MIN_0_4_LEN = 5 ;
+static const uint8_t P9N2_PU_INT_CQ_CFG_STQ1_STQ_OS_MAX_0_4 = 25 ;
+static const uint8_t P9N2_PU_INT_CQ_CFG_STQ1_STQ_OS_MAX_0_4_LEN = 5 ;
+static const uint8_t P9N2_PU_INT_CQ_CFG_STQ1_STQ_HYP_MIN_0_4 = 30 ;
+static const uint8_t P9N2_PU_INT_CQ_CFG_STQ1_STQ_HYP_MIN_0_4_LEN = 5 ;
+static const uint8_t P9N2_PU_INT_CQ_CFG_STQ1_STQ_HYP_MAX_0_4 = 35 ;
+static const uint8_t P9N2_PU_INT_CQ_CFG_STQ1_STQ_HYP_MAX_0_4_LEN = 5 ;
+static const uint8_t P9N2_PU_INT_CQ_CFG_STQ1_STQ_RDI_MIN_0_4 = 40 ;
+static const uint8_t P9N2_PU_INT_CQ_CFG_STQ1_STQ_RDI_MIN_0_4_LEN = 5 ;
+static const uint8_t P9N2_PU_INT_CQ_CFG_STQ1_STQ_RDI_MAX_0_4 = 45 ;
+static const uint8_t P9N2_PU_INT_CQ_CFG_STQ1_STQ_RDI_MAX_0_4_LEN = 5 ;
+static const uint8_t P9N2_PU_INT_CQ_CFG_STQ1_STQ_THR_MIN_0_4 = 50 ;
+static const uint8_t P9N2_PU_INT_CQ_CFG_STQ1_STQ_THR_MIN_0_4_LEN = 5 ;
+static const uint8_t P9N2_PU_INT_CQ_CFG_STQ1_STQ_THR_MAX_0_4 = 55 ;
+static const uint8_t P9N2_PU_INT_CQ_CFG_STQ1_STQ_THR_MAX_0_4_LEN = 5 ;
+static const uint8_t P9N2_PU_INT_CQ_CFG_STQ1_RESERVED_60_63 = 60 ;
+static const uint8_t P9N2_PU_INT_CQ_CFG_STQ1_RESERVED_60_63_LEN = 4 ;
+
+static const uint8_t P9N2_PU_INT_CQ_CFG_STQ2_STQ_VPC_MIN_0_4 = 0 ;
+static const uint8_t P9N2_PU_INT_CQ_CFG_STQ2_STQ_VPC_MIN_0_4_LEN = 5 ;
+static const uint8_t P9N2_PU_INT_CQ_CFG_STQ2_STQ_VPC_MAX_0_4 = 5 ;
+static const uint8_t P9N2_PU_INT_CQ_CFG_STQ2_STQ_VPC_MAX_0_4_LEN = 5 ;
+static const uint8_t P9N2_PU_INT_CQ_CFG_STQ2_STQ_REG_MIN_0_4 = 10 ;
+static const uint8_t P9N2_PU_INT_CQ_CFG_STQ2_STQ_REG_MIN_0_4_LEN = 5 ;
+static const uint8_t P9N2_PU_INT_CQ_CFG_STQ2_STQ_REG_MAX_0_4 = 15 ;
+static const uint8_t P9N2_PU_INT_CQ_CFG_STQ2_STQ_REG_MAX_0_4_LEN = 5 ;
+static const uint8_t P9N2_PU_INT_CQ_CFG_STQ2_RESERVED_20_31 = 20 ;
+static const uint8_t P9N2_PU_INT_CQ_CFG_STQ2_RESERVED_20_31_LEN = 12 ;
+
+static const uint8_t P9N2_PU_INT_CQ_CNPM_SEL_PMON_MUX_BYTE0_0_2 = 0 ;
+static const uint8_t P9N2_PU_INT_CQ_CNPM_SEL_PMON_MUX_BYTE0_0_2_LEN = 3 ;
+static const uint8_t P9N2_PU_INT_CQ_CNPM_SEL_PMON_MUX_BYTE1_0_2 = 3 ;
+static const uint8_t P9N2_PU_INT_CQ_CNPM_SEL_PMON_MUX_BYTE1_0_2_LEN = 3 ;
+static const uint8_t P9N2_PU_INT_CQ_CNPM_SEL_PMON_MUX_BYTE2_0_2 = 6 ;
+static const uint8_t P9N2_PU_INT_CQ_CNPM_SEL_PMON_MUX_BYTE2_0_2_LEN = 3 ;
+static const uint8_t P9N2_PU_INT_CQ_CNPM_SEL_PMON_MUX_BYTE3_0_2 = 9 ;
+static const uint8_t P9N2_PU_INT_CQ_CNPM_SEL_PMON_MUX_BYTE3_0_2_LEN = 3 ;
+static const uint8_t P9N2_PU_INT_CQ_CNPM_SEL_RESERVED_12_23 = 12 ;
+static const uint8_t P9N2_PU_INT_CQ_CNPM_SEL_RESERVED_12_23_LEN = 12 ;
+static const uint8_t P9N2_PU_INT_CQ_CNPM_SEL_EBUS_ENABLE_0_15 = 24 ;
+static const uint8_t P9N2_PU_INT_CQ_CNPM_SEL_EBUS_ENABLE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_PU_INT_CQ_ERR_INFO0_INFO_CAPTURED = 0 ;
+static const uint8_t P9N2_PU_INT_CQ_ERR_INFO0_RCMD0_ADDR_PERR = 1 ;
+static const uint8_t P9N2_PU_INT_CQ_ERR_INFO0_RCMD1_ADDR_PERR = 2 ;
+static const uint8_t P9N2_PU_INT_CQ_ERR_INFO0_RCMD2_ADDR_PERR = 3 ;
+static const uint8_t P9N2_PU_INT_CQ_ERR_INFO0_RCMD3_ADDR_PERR = 4 ;
+static const uint8_t P9N2_PU_INT_CQ_ERR_INFO0_RCMD0_TTAG_PERR = 5 ;
+static const uint8_t P9N2_PU_INT_CQ_ERR_INFO0_RCMD1_TTAG_PERR = 6 ;
+static const uint8_t P9N2_PU_INT_CQ_ERR_INFO0_RCMD2_TTAG_PERR = 7 ;
+static const uint8_t P9N2_PU_INT_CQ_ERR_INFO0_RCMD3_TTAG_PERR = 8 ;
+static const uint8_t P9N2_PU_INT_CQ_ERR_INFO0_CR0_TTAG_PERR = 9 ;
+static const uint8_t P9N2_PU_INT_CQ_ERR_INFO0_CR1_TTAG_PERR = 10 ;
+static const uint8_t P9N2_PU_INT_CQ_ERR_INFO0_CR2_TTAG_PERR = 11 ;
+static const uint8_t P9N2_PU_INT_CQ_ERR_INFO0_CR3_TTAG_PERR = 12 ;
+static const uint8_t P9N2_PU_INT_CQ_ERR_INFO0_CR0_ATAG_PERR = 13 ;
+static const uint8_t P9N2_PU_INT_CQ_ERR_INFO0_CR1_ATAG_PERR = 14 ;
+static const uint8_t P9N2_PU_INT_CQ_ERR_INFO0_CR2_ATAG_PERR = 15 ;
+static const uint8_t P9N2_PU_INT_CQ_ERR_INFO0_CR3_ATAG_PERR = 16 ;
+static const uint8_t P9N2_PU_INT_CQ_ERR_INFO0_RTAG_PERR = 17 ;
+
+static const uint8_t P9N2_PU_INT_CQ_ERR_INFO1_INFO_CAPTURED = 0 ;
+static const uint8_t P9N2_PU_INT_CQ_ERR_INFO1_CI_WRITE = 1 ;
+static const uint8_t P9N2_PU_INT_CQ_ERR_INFO1_CI_READ = 2 ;
+static const uint8_t P9N2_PU_INT_CQ_ERR_INFO1_DMA_WRITE = 3 ;
+static const uint8_t P9N2_PU_INT_CQ_ERR_INFO1_TSIZE_4_6 = 4 ;
+static const uint8_t P9N2_PU_INT_CQ_ERR_INFO1_TSIZE_4_6_LEN = 3 ;
+static const uint8_t P9N2_PU_INT_CQ_ERR_INFO1_BAR_VEC_0_3 = 7 ;
+static const uint8_t P9N2_PU_INT_CQ_ERR_INFO1_BAR_VEC_0_3_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_CQ_ERR_INFO1_TTAG_0_16 = 11 ;
+static const uint8_t P9N2_PU_INT_CQ_ERR_INFO1_TTAG_0_16_LEN = 17 ;
+static const uint8_t P9N2_PU_INT_CQ_ERR_INFO1_ADDRESS_28_63 = 28 ;
+static const uint8_t P9N2_PU_INT_CQ_ERR_INFO1_ADDRESS_28_63_LEN = 36 ;
+
+static const uint8_t P9N2_PU_INT_CQ_ERR_INFO2_INFO_CAPTURED = 0 ;
+static const uint8_t P9N2_PU_INT_CQ_ERR_INFO2_RESERVED_1_5 = 1 ;
+static const uint8_t P9N2_PU_INT_CQ_ERR_INFO2_RESERVED_1_5_LEN = 5 ;
+static const uint8_t P9N2_PU_INT_CQ_ERR_INFO2_HI = 6 ;
+static const uint8_t P9N2_PU_INT_CQ_ERR_INFO2_LO = 7 ;
+static const uint8_t P9N2_PU_INT_CQ_ERR_INFO2_RD_ADDR_0_7 = 8 ;
+static const uint8_t P9N2_PU_INT_CQ_ERR_INFO2_RD_ADDR_0_7_LEN = 8 ;
+static const uint8_t P9N2_PU_INT_CQ_ERR_INFO2_SYN_HI_0_7 = 16 ;
+static const uint8_t P9N2_PU_INT_CQ_ERR_INFO2_SYN_HI_0_7_LEN = 8 ;
+static const uint8_t P9N2_PU_INT_CQ_ERR_INFO2_SYN_LO_0_7 = 24 ;
+static const uint8_t P9N2_PU_INT_CQ_ERR_INFO2_SYN_LO_0_7_LEN = 8 ;
+
+static const uint8_t P9N2_PU_INT_CQ_ERR_INFO3_INFO_CAPTURED = 0 ;
+static const uint8_t P9N2_PU_INT_CQ_ERR_INFO3_STQ_FSM_PERR = 1 ;
+static const uint8_t P9N2_PU_INT_CQ_ERR_INFO3_LDQ_FSM_PERR = 2 ;
+static const uint8_t P9N2_PU_INT_CQ_ERR_INFO3_WRQ_FSM_PERR = 3 ;
+static const uint8_t P9N2_PU_INT_CQ_ERR_INFO3_RDQ_FSM_PERR = 4 ;
+static const uint8_t P9N2_PU_INT_CQ_ERR_INFO3_INTQ_FSM_PERR = 5 ;
+static const uint8_t P9N2_PU_INT_CQ_ERR_INFO3_WRQ_OVERFLOW = 6 ;
+static const uint8_t P9N2_PU_INT_CQ_ERR_INFO3_RDQ_OVERFLOW = 7 ;
+static const uint8_t P9N2_PU_INT_CQ_ERR_INFO3_INTQ_OVERFLOW = 8 ;
+
+static const uint8_t P9N2_PU_INT_CQ_ERR_RPT_HOLD_HOLD_0_48 = 0 ;
+static const uint8_t P9N2_PU_INT_CQ_ERR_RPT_HOLD_HOLD_0_48_LEN = 49 ;
+
+static const uint8_t P9N2_PU_INT_CQ_FIR_PI_ECC_CE = 0 ;
+static const uint8_t P9N2_PU_INT_CQ_FIR_PI_ECC_UE = 1 ;
+static const uint8_t P9N2_PU_INT_CQ_FIR_PI_ECC_SUE = 2 ;
+static const uint8_t P9N2_PU_INT_CQ_FIR_ST_ECC_CE = 3 ;
+static const uint8_t P9N2_PU_INT_CQ_FIR_ST_ECC_UE = 4 ;
+static const uint8_t P9N2_PU_INT_CQ_FIR_LD_ECC_CE = 5 ;
+static const uint8_t P9N2_PU_INT_CQ_FIR_LD_ECC_UE = 6 ;
+static const uint8_t P9N2_PU_INT_CQ_FIR_CL_ECC_CE = 7 ;
+static const uint8_t P9N2_PU_INT_CQ_FIR_CL_ECC_UE = 8 ;
+static const uint8_t P9N2_PU_INT_CQ_FIR_WR_ECC_CE = 9 ;
+static const uint8_t P9N2_PU_INT_CQ_FIR_WR_ECC_UE = 10 ;
+static const uint8_t P9N2_PU_INT_CQ_FIR_RD_ECC_CE = 11 ;
+static const uint8_t P9N2_PU_INT_CQ_FIR_RD_ECC_UE = 12 ;
+static const uint8_t P9N2_PU_INT_CQ_FIR_AI_ECC_CE = 13 ;
+static const uint8_t P9N2_PU_INT_CQ_FIR_AI_ECC_UE = 14 ;
+static const uint8_t P9N2_PU_INT_CQ_FIR_AIB_IN_CMD_CTL_PERR = 15 ;
+static const uint8_t P9N2_PU_INT_CQ_FIR_AIB_IN_CMD_PERR = 16 ;
+static const uint8_t P9N2_PU_INT_CQ_FIR_AIB_IN_DAT_CTL_PERR = 17 ;
+static const uint8_t P9N2_PU_INT_CQ_FIR_PB_PARITY_ERROR = 18 ;
+static const uint8_t P9N2_PU_INT_CQ_FIR_PB_RCMDX_CI_ERR1 = 19 ;
+static const uint8_t P9N2_PU_INT_CQ_FIR_PB_RCMDX_CI_ERR2 = 20 ;
+static const uint8_t P9N2_PU_INT_CQ_FIR_PB_RCMDX_CI_ERR3 = 21 ;
+static const uint8_t P9N2_PU_INT_CQ_FIR_RCVD_POISONED_CIST_DATA = 22 ;
+static const uint8_t P9N2_PU_INT_CQ_FIR_MRT_ERR_NOT_VALID = 23 ;
+static const uint8_t P9N2_PU_INT_CQ_FIR_MRT_ERR_PSIZE = 24 ;
+static const uint8_t P9N2_PU_INT_CQ_FIR_SCOM_S_ERR = 25 ;
+static const uint8_t P9N2_PU_INT_CQ_FIR_TCTXT_PRESP_ERROR = 26 ;
+static const uint8_t P9N2_PU_INT_CQ_FIR_WRQ_OP_HANG = 27 ;
+static const uint8_t P9N2_PU_INT_CQ_FIR_RDQ_OP_HANG = 28 ;
+static const uint8_t P9N2_PU_INT_CQ_FIR_INTQ_OP_HANG = 29 ;
+static const uint8_t P9N2_PU_INT_CQ_FIR_RDQ_DATA_HANG = 30 ;
+static const uint8_t P9N2_PU_INT_CQ_FIR_STQ_DATA_HANG = 31 ;
+static const uint8_t P9N2_PU_INT_CQ_FIR_LDQ_DATA_HANG = 32 ;
+static const uint8_t P9N2_PU_INT_CQ_FIR_WRQ_BAD_CRESP = 33 ;
+static const uint8_t P9N2_PU_INT_CQ_FIR_RDQ_BAD_CRESP = 34 ;
+static const uint8_t P9N2_PU_INT_CQ_FIR_INTQ_BAD_CRESP = 35 ;
+static const uint8_t P9N2_PU_INT_CQ_FIR_BAD_128K_VP_OP = 36 ;
+static const uint8_t P9N2_PU_INT_CQ_FIR_RDQ_ABORT_OP = 37 ;
+static const uint8_t P9N2_PU_INT_CQ_FIR_PC_CRD_PERR = 38 ;
+static const uint8_t P9N2_PU_INT_CQ_FIR_PC_CRD_AVAIL_PERR = 39 ;
+static const uint8_t P9N2_PU_INT_CQ_FIR_VC_CRD_PERR = 40 ;
+static const uint8_t P9N2_PU_INT_CQ_FIR_VC_CRD_AVAIL_PERR = 41 ;
+static const uint8_t P9N2_PU_INT_CQ_FIR_CMD_QX_SEVERE_ERR = 42 ;
+static const uint8_t P9N2_PU_INT_CQ_FIR_RDQ_ABORT_TRM = 43 ;
+static const uint8_t P9N2_PU_INT_CQ_FIR_UNSOLICITED_CRESP = 44 ;
+static const uint8_t P9N2_PU_INT_CQ_FIR_UNSOLICITED_PBDATA = 45 ;
+static const uint8_t P9N2_PU_INT_CQ_FIR_FIR_PARITY_ERR = 46 ;
+static const uint8_t P9N2_PU_INT_CQ_FIR_PGM_DBG_ACCESS = 47 ;
+static const uint8_t P9N2_PU_INT_CQ_FIR_RESERVED_48 = 48 ;
+static const uint8_t P9N2_PU_INT_CQ_FIR_PC_FATAL_ERROR_0_2 = 49 ;
+static const uint8_t P9N2_PU_INT_CQ_FIR_PC_FATAL_ERROR_0_2_LEN = 3 ;
+static const uint8_t P9N2_PU_INT_CQ_FIR_PC_RECOV_ERROR_0_2 = 52 ;
+static const uint8_t P9N2_PU_INT_CQ_FIR_PC_RECOV_ERROR_0_2_LEN = 3 ;
+static const uint8_t P9N2_PU_INT_CQ_FIR_PC_INFO_ERROR_0_2 = 55 ;
+static const uint8_t P9N2_PU_INT_CQ_FIR_PC_INFO_ERROR_0_2_LEN = 3 ;
+static const uint8_t P9N2_PU_INT_CQ_FIR_VC_FATAL_ERROR_0_1 = 58 ;
+static const uint8_t P9N2_PU_INT_CQ_FIR_VC_FATAL_ERROR_0_1_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_CQ_FIR_VC_RECOV_ERROR_0_1 = 60 ;
+static const uint8_t P9N2_PU_INT_CQ_FIR_VC_RECOV_ERROR_0_1_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_CQ_FIR_VC_INFO_ERROR_0_1 = 62 ;
+static const uint8_t P9N2_PU_INT_CQ_FIR_VC_INFO_ERROR_0_1_LEN = 2 ;
+
+static const uint8_t P9N2_PU_INT_CQ_FIRMASK_FIR_MASK = 0 ;
+static const uint8_t P9N2_PU_INT_CQ_FIRMASK_FIR_MASK_LEN = 64 ;
+
+static const uint8_t P9N2_PU_INT_CQ_IC_BAR_VALID = 0 ;
+static const uint8_t P9N2_PU_INT_CQ_IC_BAR_PAGE_SIZE_64K = 1 ;
+static const uint8_t P9N2_PU_INT_CQ_IC_BAR_ADDR_8_48 = 8 ;
+static const uint8_t P9N2_PU_INT_CQ_IC_BAR_ADDR_8_48_LEN = 41 ;
+
+static const uint8_t P9N2_PU_INT_CQ_MSGSND_CORES_ENABLED_0_23 = 0 ;
+static const uint8_t P9N2_PU_INT_CQ_MSGSND_CORES_ENABLED_0_23_LEN = 24 ;
+
+static const uint8_t P9N2_PU_INT_CQ_PBC_LIMIT_LCL_POLL_BCST_RTY_MON = 0 ;
+static const uint8_t P9N2_PU_INT_CQ_PBC_LIMIT_MAX_LCL_ALL_0_4 = 1 ;
+static const uint8_t P9N2_PU_INT_CQ_PBC_LIMIT_MAX_LCL_ALL_0_4_LEN = 5 ;
+static const uint8_t P9N2_PU_INT_CQ_PBC_LIMIT_MAX_LCL_GRP_0_4 = 6 ;
+static const uint8_t P9N2_PU_INT_CQ_PBC_LIMIT_MAX_LCL_GRP_0_4_LEN = 5 ;
+static const uint8_t P9N2_PU_INT_CQ_PBC_LIMIT_MAX_LCL_GRP_DROP_0_4 = 11 ;
+static const uint8_t P9N2_PU_INT_CQ_PBC_LIMIT_MAX_LCL_GRP_DROP_0_4_LEN = 5 ;
+static const uint8_t P9N2_PU_INT_CQ_PBC_LIMIT_RMT_POLL_BCST_RTY_MON = 16 ;
+static const uint8_t P9N2_PU_INT_CQ_PBC_LIMIT_MAX_RMT_ALL_0_4 = 17 ;
+static const uint8_t P9N2_PU_INT_CQ_PBC_LIMIT_MAX_RMT_ALL_0_4_LEN = 5 ;
+static const uint8_t P9N2_PU_INT_CQ_PBC_LIMIT_MAX_RMT_GRP_0_4 = 22 ;
+static const uint8_t P9N2_PU_INT_CQ_PBC_LIMIT_MAX_RMT_GRP_0_4_LEN = 5 ;
+static const uint8_t P9N2_PU_INT_CQ_PBC_LIMIT_MAX_RMT_GRP_DROP_0_4 = 27 ;
+static const uint8_t P9N2_PU_INT_CQ_PBC_LIMIT_MAX_RMT_GRP_DROP_0_4_LEN = 5 ;
+static const uint8_t P9N2_PU_INT_CQ_PBC_LIMIT_DROP_RESTORE_TIMER_0_2 = 32 ;
+static const uint8_t P9N2_PU_INT_CQ_PBC_LIMIT_DROP_RESTORE_TIMER_0_2_LEN = 3 ;
+static const uint8_t P9N2_PU_INT_CQ_PBC_LIMIT_RESERVED_35_39 = 35 ;
+static const uint8_t P9N2_PU_INT_CQ_PBC_LIMIT_RESERVED_35_39_LEN = 5 ;
+
+static const uint8_t P9N2_PU_INT_CQ_PBI_CTL_DIS_ECCCHK = 0 ;
+static const uint8_t P9N2_PU_INT_CQ_PBI_CTL_DIS_ECCCHK_STO = 1 ;
+static const uint8_t P9N2_PU_INT_CQ_PBI_CTL_RESERVED_2 = 2 ;
+static const uint8_t P9N2_PU_INT_CQ_PBI_CTL_RESERVED_3 = 3 ;
+static const uint8_t P9N2_PU_INT_CQ_PBI_CTL_RESERVED_4 = 4 ;
+static const uint8_t P9N2_PU_INT_CQ_PBI_CTL_PAGE_SIZE_64K_PC = 5 ;
+static const uint8_t P9N2_PU_INT_CQ_PBI_CTL_PAGE_SIZE_64K_VC = 6 ;
+static const uint8_t P9N2_PU_INT_CQ_PBI_CTL_LINUX_TRIG_MODE = 7 ;
+static const uint8_t P9N2_PU_INT_CQ_PBI_CTL_TRACE_BUS_SEL_0_1 = 8 ;
+static const uint8_t P9N2_PU_INT_CQ_PBI_CTL_TRACE_BUS_SEL_0_1_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_CQ_PBI_CTL_TRACE_SEL_0_1 = 10 ;
+static const uint8_t P9N2_PU_INT_CQ_PBI_CTL_TRACE_SEL_0_1_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_CQ_PBI_CTL_DIS_DMA_W = 12 ;
+static const uint8_t P9N2_PU_INT_CQ_PBI_CTL_STRICT_IPI_RULES = 13 ;
+static const uint8_t P9N2_PU_INT_CQ_PBI_CTL_FORCE_ECC_CE = 14 ;
+static const uint8_t P9N2_PU_INT_CQ_PBI_CTL_FORCE_ECC_UE = 15 ;
+static const uint8_t P9N2_PU_INT_CQ_PBI_CTL_FORCE_ECC_SEL = 16 ;
+static const uint8_t P9N2_PU_INT_CQ_PBI_CTL_SPEC_CILD_G = 17 ;
+static const uint8_t P9N2_PU_INT_CQ_PBI_CTL_EN_SPEC_CILD_IVE = 18 ;
+static const uint8_t P9N2_PU_INT_CQ_PBI_CTL_EN_SPEC_CILD_EQD = 19 ;
+static const uint8_t P9N2_PU_INT_CQ_PBI_CTL_EN_SPEC_CILD_VPC_HW = 20 ;
+static const uint8_t P9N2_PU_INT_CQ_PBI_CTL_EN_SPEC_CILD_VPC_SW = 21 ;
+static const uint8_t P9N2_PU_INT_CQ_PBI_CTL_FORCE_TM_LOCAL = 22 ;
+static const uint8_t P9N2_PU_INT_CQ_PBI_CTL_DIS_VPC_ORDER = 23 ;
+static const uint8_t P9N2_PU_INT_CQ_PBI_CTL_EN_SYNC_ORDER = 24 ;
+static const uint8_t P9N2_PU_INT_CQ_PBI_CTL_RESERVED_25_31 = 25 ;
+static const uint8_t P9N2_PU_INT_CQ_PBI_CTL_RESERVED_25_31_LEN = 7 ;
+
+static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_DIS_ECCCHK_LDO = 0 ;
+static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_DIS_ECCCHK_WRO = 1 ;
+static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_DIS_ECCCHK_CLO = 2 ;
+static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_EN_7BIT_EQC_ORDER = 3 ;
+static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_STRICT_ORDER = 4 ;
+static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_FORCE_MAX_SCOPE_INTRP = 5 ;
+static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_FORCE_VG_SYS_INTRP = 6 ;
+static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_DROP_PRI_INTRP = 7 ;
+static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_DROP_PRI_HPC_READ = 8 ;
+static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_DROP_PRI_DMA = 9 ;
+static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_DROP_MASK_0_5 = 10 ;
+static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_DROP_MASK_0_5_LEN = 6 ;
+static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_SLOW_CMD_RATE = 16 ;
+static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_EN_RANDOM_BACKOFF = 17 ;
+static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_EN_POLL_BACKOFF = 18 ;
+static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_EN_CILD_BACKOFF = 19 ;
+static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_FORCE_ECC_CE = 20 ;
+static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_FORCE_ECC_UE = 21 ;
+static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_FORCE_ECC_SEL_0_1 = 22 ;
+static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_FORCE_ECC_SEL_0_1_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_DISABLE_INJECT = 24 ;
+static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_FORCE_CL_INJECT = 25 ;
+static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_FORCE_PR_INJECT = 26 ;
+static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_HANG_ON_ADDR_ERROR = 27 ;
+static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_HANG_ON_ACK_DEAD = 28 ;
+static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_POLL_BCST_RTY_MON = 29 ;
+static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_MAX_POLL_BCAST_1_0_4 = 30 ;
+static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_MAX_POLL_BCAST_1_0_4_LEN = 5 ;
+static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_MAX_POLL_BCAST_2_0_4 = 35 ;
+static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_MAX_POLL_BCAST_2_0_4_LEN = 5 ;
+static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_MAX_POLL_BCAST_3_0_4 = 40 ;
+static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_MAX_POLL_BCAST_3_0_4_LEN = 5 ;
+static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_DISABLE_NN_RN = 45 ;
+static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_DISABLE_VG_NOT_SYS = 46 ;
+static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_DISABLE_G = 47 ;
+static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_DISABLE_LN = 48 ;
+static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_SKIP_G = 49 ;
+static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_WRQ_CMD_REJ_DISABLE = 50 ;
+static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_RDQ_CMD_REJ_DISABLE = 51 ;
+static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_INTQ_CMD_REJ_DISABLE = 52 ;
+static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_DIS_WRQ_INTRP_ORDER = 53 ;
+static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_DIS_RDQ_INTRP_ORDER = 54 ;
+static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_DROP_PRI_CI_WR = 55 ;
+static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_DROP_PRI_CI_RD = 56 ;
+static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_DIS_NGRP_INTRP_ORDER = 57 ;
+static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_DIS_GRP_INTRP_ORDER = 58 ;
+static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_RESERVED_59_63 = 59 ;
+static const uint8_t P9N2_PU_INT_CQ_PBO_CTL_RESERVED_59_63_LEN = 5 ;
+
+static const uint8_t P9N2_PU_INT_CQ_PC_BAR_VALID = 0 ;
+static const uint8_t P9N2_PU_INT_CQ_PC_BAR_ADDR_8_38 = 8 ;
+static const uint8_t P9N2_PU_INT_CQ_PC_BAR_ADDR_8_38_LEN = 31 ;
+
+static const uint8_t P9N2_PU_INT_CQ_PC_BARM_ADDR_25_38 = 25 ;
+static const uint8_t P9N2_PU_INT_CQ_PC_BARM_ADDR_25_38_LEN = 14 ;
+
+static const uint8_t P9N2_PU_INT_CQ_PMC_0_COUNT_47 = 16 ;
+static const uint8_t P9N2_PU_INT_CQ_PMC_0_COUNT_47_LEN = 48 ;
+
+static const uint8_t P9N2_PU_INT_CQ_PMC_1_COUNT_0_47 = 16 ;
+static const uint8_t P9N2_PU_INT_CQ_PMC_1_COUNT_0_47_LEN = 48 ;
+
+static const uint8_t P9N2_PU_INT_CQ_PMC_2_COUNT_0_47 = 16 ;
+static const uint8_t P9N2_PU_INT_CQ_PMC_2_COUNT_0_47_LEN = 48 ;
+
+static const uint8_t P9N2_PU_INT_CQ_PMC_3_COUNT_0_47 = 16 ;
+static const uint8_t P9N2_PU_INT_CQ_PMC_3_COUNT_0_47_LEN = 48 ;
+
+static const uint8_t P9N2_PU_INT_CQ_PMC_4_COUNT_0_47 = 16 ;
+static const uint8_t P9N2_PU_INT_CQ_PMC_4_COUNT_0_47_LEN = 48 ;
+
+static const uint8_t P9N2_PU_INT_CQ_PMC_5_COUNT_0_47 = 16 ;
+static const uint8_t P9N2_PU_INT_CQ_PMC_5_COUNT_0_47_LEN = 48 ;
+
+static const uint8_t P9N2_PU_INT_CQ_PMC_6_COUNT_0_47 = 16 ;
+static const uint8_t P9N2_PU_INT_CQ_PMC_6_COUNT_0_47_LEN = 48 ;
+
+static const uint8_t P9N2_PU_INT_CQ_PMC_7_COUNT_0_47 = 16 ;
+static const uint8_t P9N2_PU_INT_CQ_PMC_7_COUNT_0_47_LEN = 48 ;
+
+static const uint8_t P9N2_PU_INT_CQ_PM_CTL_ENABLE_0_7 = 0 ;
+static const uint8_t P9N2_PU_INT_CQ_PM_CTL_ENABLE_0_7_LEN = 8 ;
+static const uint8_t P9N2_PU_INT_CQ_PM_CTL_RESET_0_7 = 8 ;
+static const uint8_t P9N2_PU_INT_CQ_PM_CTL_RESET_0_7_LEN = 8 ;
+static const uint8_t P9N2_PU_INT_CQ_PM_CTL_SOURCE_SUBUNIT_0_1 = 16 ;
+static const uint8_t P9N2_PU_INT_CQ_PM_CTL_SOURCE_SUBUNIT_0_1_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_CQ_PM_CTL_GROUP_SEL_0_4 = 18 ;
+static const uint8_t P9N2_PU_INT_CQ_PM_CTL_GROUP_SEL_0_4_LEN = 5 ;
+
+static const uint8_t P9N2_PU_INT_CQ_RST_CTL_SYNC_RESET = 0 ;
+static const uint8_t P9N2_PU_INT_CQ_RST_CTL_QUIESCE_PB = 1 ;
+static const uint8_t P9N2_PU_INT_CQ_RST_CTL_MASTER_IDLE = 2 ;
+static const uint8_t P9N2_PU_INT_CQ_RST_CTL_SLAVE_IDLE = 3 ;
+static const uint8_t P9N2_PU_INT_CQ_RST_CTL_PB_BAR_RESET = 4 ;
+static const uint8_t P9N2_PU_INT_CQ_RST_CTL_RESERVED_5_7 = 5 ;
+static const uint8_t P9N2_PU_INT_CQ_RST_CTL_RESERVED_5_7_LEN = 3 ;
+
+static const uint8_t P9N2_PU_INT_CQ_SWI_RSP_HIST_DONE = 0 ;
+static const uint8_t P9N2_PU_INT_CQ_SWI_RSP_POLL_DONE = 1 ;
+static const uint8_t P9N2_PU_INT_CQ_SWI_RSP_BCAST_DONE = 2 ;
+static const uint8_t P9N2_PU_INT_CQ_SWI_RSP_ASSIGN_DONE = 3 ;
+static const uint8_t P9N2_PU_INT_CQ_SWI_RSP_BLK_UPDT_DONE = 4 ;
+static const uint8_t P9N2_PU_INT_CQ_SWI_RSP_Z = 5 ;
+static const uint8_t P9N2_PU_INT_CQ_SWI_RSP_O = 6 ;
+static const uint8_t P9N2_PU_INT_CQ_SWI_RSP_M = 7 ;
+static const uint8_t P9N2_PU_INT_CQ_SWI_RSP_CRESP_0_4 = 8 ;
+static const uint8_t P9N2_PU_INT_CQ_SWI_RSP_CRESP_0_4_LEN = 5 ;
+static const uint8_t P9N2_PU_INT_CQ_SWI_RSP_RESERVED_13 = 13 ;
+static const uint8_t P9N2_PU_INT_CQ_SWI_RSP_COLLISON = 14 ;
+static const uint8_t P9N2_PU_INT_CQ_SWI_RSP_PRECLUDE = 15 ;
+static const uint8_t P9N2_PU_INT_CQ_SWI_RSP_ATAG_0_15 = 16 ;
+static const uint8_t P9N2_PU_INT_CQ_SWI_RSP_ATAG_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_PU_INT_CQ_TAR_AUTO_INC = 0 ;
+static const uint8_t P9N2_PU_INT_CQ_TAR_TABLE_SEL_0_3 = 12 ;
+static const uint8_t P9N2_PU_INT_CQ_TAR_TABLE_SEL_0_3_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_CQ_TAR_ENTRY_SEL_0_5 = 26 ;
+static const uint8_t P9N2_PU_INT_CQ_TAR_ENTRY_SEL_0_5_LEN = 6 ;
+
+static const uint8_t P9N2_PU_INT_CQ_TM1_BAR_VALID = 0 ;
+static const uint8_t P9N2_PU_INT_CQ_TM1_BAR_PAGE_SIZE_64K = 1 ;
+static const uint8_t P9N2_PU_INT_CQ_TM1_BAR_ADDR_8_49 = 8 ;
+static const uint8_t P9N2_PU_INT_CQ_TM1_BAR_ADDR_8_49_LEN = 42 ;
+
+static const uint8_t P9N2_PU_INT_CQ_TM2_BAR_VALID = 0 ;
+static const uint8_t P9N2_PU_INT_CQ_TM2_BAR_PAGE_SIZE_64K = 1 ;
+static const uint8_t P9N2_PU_INT_CQ_TM2_BAR_ADDR_8_49 = 8 ;
+static const uint8_t P9N2_PU_INT_CQ_TM2_BAR_ADDR_8_49_LEN = 42 ;
+
+static const uint8_t P9N2_PU_INT_CQ_VC_BAR_VALID = 0 ;
+static const uint8_t P9N2_PU_INT_CQ_VC_BAR_ADDR_8_37 = 8 ;
+static const uint8_t P9N2_PU_INT_CQ_VC_BAR_ADDR_8_37_LEN = 30 ;
+
+static const uint8_t P9N2_PU_INT_CQ_VC_BARM_ADDR_22_37 = 22 ;
+static const uint8_t P9N2_PU_INT_CQ_VC_BARM_ADDR_22_37_LEN = 16 ;
+
+static const uint8_t P9N2_PU_INT_CQ_WOF_WOF = 0 ;
+static const uint8_t P9N2_PU_INT_CQ_WOF_WOF_LEN = 64 ;
+
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE0_ERR_VLD = 0 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE0_ERR_LVL = 1 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE0_ERR_LVL_LEN = 35 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE0_ERR_CQ = 36 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE0_ERR_CQ_LEN = 12 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE0_ERR_RSVD0 = 48 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE0_ERR_RSVD0_LEN = 16 ;
+
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE1_ERR_VLD = 0 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE1_ERR_LVL = 1 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE1_ERR_LVL_LEN = 35 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE1_ERR_CQ = 36 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE1_ERR_CQ_LEN = 12 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE1_ERR_RSVD0 = 48 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE1_ERR_RSVD0_LEN = 16 ;
+
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE10_ERR_VLD = 0 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE10_ERR_LVL = 1 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE10_ERR_LVL_LEN = 35 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE10_ERR_CQ = 36 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE10_ERR_CQ_LEN = 12 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE10_ERR_RSVD0 = 48 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE10_ERR_RSVD0_LEN = 16 ;
+
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE11_ERR_VLD = 0 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE11_ERR_LVL = 1 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE11_ERR_LVL_LEN = 35 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE11_ERR_CQ = 36 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE11_ERR_CQ_LEN = 12 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE11_ERR_RSVD0 = 48 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE11_ERR_RSVD0_LEN = 16 ;
+
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE12_ERR_VLD = 0 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE12_ERR_LVL = 1 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE12_ERR_LVL_LEN = 35 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE12_ERR_CQ = 36 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE12_ERR_CQ_LEN = 12 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE12_ERR_RSVD0 = 48 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE12_ERR_RSVD0_LEN = 16 ;
+
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE13_ERR_VLD = 0 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE13_ERR_LVL = 1 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE13_ERR_LVL_LEN = 35 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE13_ERR_CQ = 36 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE13_ERR_CQ_LEN = 12 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE13_ERR_RSVD0 = 48 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE13_ERR_RSVD0_LEN = 16 ;
+
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE14_ERR_VLD = 0 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE14_ERR_LVL = 1 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE14_ERR_LVL_LEN = 35 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE14_ERR_CQ = 36 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE14_ERR_CQ_LEN = 12 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE14_ERR_RSVD0 = 48 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE14_ERR_RSVD0_LEN = 16 ;
+
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE15_ERR_VLD = 0 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE15_ERR_LVL = 1 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE15_ERR_LVL_LEN = 35 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE15_ERR_CQ = 36 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE15_ERR_CQ_LEN = 12 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE15_ERR_RSVD0 = 48 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE15_ERR_RSVD0_LEN = 16 ;
+
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE2_ERR_VLD = 0 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE2_ERR_LVL = 1 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE2_ERR_LVL_LEN = 35 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE2_ERR_CQ = 36 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE2_ERR_CQ_LEN = 12 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE2_ERR_RSVD0 = 48 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE2_ERR_RSVD0_LEN = 16 ;
+
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE3_ERR_VLD = 0 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE3_ERR_LVL = 1 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE3_ERR_LVL_LEN = 35 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE3_ERR_CQ = 36 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE3_ERR_CQ_LEN = 12 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE3_ERR_RSVD0 = 48 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE3_ERR_RSVD0_LEN = 16 ;
+
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE4_ERR_VLD = 0 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE4_ERR_LVL = 1 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE4_ERR_LVL_LEN = 35 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE4_ERR_CQ = 36 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE4_ERR_CQ_LEN = 12 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE4_ERR_RSVD0 = 48 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE4_ERR_RSVD0_LEN = 16 ;
+
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE5_ERR_VLD = 0 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE5_ERR_LVL = 1 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE5_ERR_LVL_LEN = 35 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE5_ERR_CQ = 36 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE5_ERR_CQ_LEN = 12 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE5_ERR_RSVD0 = 48 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE5_ERR_RSVD0_LEN = 16 ;
+
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE6_ERR_VLD = 0 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE6_ERR_LVL = 1 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE6_ERR_LVL_LEN = 35 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE6_ERR_CQ = 36 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE6_ERR_CQ_LEN = 12 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE6_ERR_RSVD0 = 48 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE6_ERR_RSVD0_LEN = 16 ;
+
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE7_ERR_VLD = 0 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE7_ERR_LVL = 1 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE7_ERR_LVL_LEN = 35 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE7_ERR_CQ = 36 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE7_ERR_CQ_LEN = 12 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE7_ERR_RSVD0 = 48 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE7_ERR_RSVD0_LEN = 16 ;
+
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE8_ERR_VLD = 0 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE8_ERR_LVL = 1 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE8_ERR_LVL_LEN = 35 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE8_ERR_CQ = 36 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE8_ERR_CQ_LEN = 12 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE8_ERR_RSVD0 = 48 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE8_ERR_RSVD0_LEN = 16 ;
+
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE9_ERR_VLD = 0 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE9_ERR_LVL = 1 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE9_ERR_LVL_LEN = 35 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE9_ERR_CQ = 36 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE9_ERR_CQ_LEN = 12 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE9_ERR_RSVD0 = 48 ;
+static const uint8_t P9N2__NTL1_INT_LOG_0_PE9_ERR_RSVD0_LEN = 16 ;
+
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE0_ERR_VLD = 0 ;
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE0_ERR_DETAIL = 1 ;
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE0_ERR_DETAIL_LEN = 32 ;
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE0_ERR_RSVD0 = 33 ;
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE0_ERR_RSVD0_LEN = 31 ;
+
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE1_ERR_VLD = 0 ;
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE1_ERR_DETAIL = 1 ;
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE1_ERR_DETAIL_LEN = 32 ;
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE1_ERR_RSVD0 = 33 ;
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE1_ERR_RSVD0_LEN = 31 ;
+
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE10_ERR_VLD = 0 ;
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE10_ERR_DETAIL = 1 ;
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE10_ERR_DETAIL_LEN = 32 ;
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE10_ERR_RSVD0 = 33 ;
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE10_ERR_RSVD0_LEN = 31 ;
+
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE11_ERR_VLD = 0 ;
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE11_ERR_DETAIL = 1 ;
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE11_ERR_DETAIL_LEN = 32 ;
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE11_ERR_RSVD0 = 33 ;
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE11_ERR_RSVD0_LEN = 31 ;
+
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE12_ERR_VLD = 0 ;
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE12_ERR_DETAIL = 1 ;
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE12_ERR_DETAIL_LEN = 32 ;
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE12_ERR_RSVD0 = 33 ;
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE12_ERR_RSVD0_LEN = 31 ;
+
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE13_ERR_VLD = 0 ;
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE13_ERR_DETAIL = 1 ;
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE13_ERR_DETAIL_LEN = 32 ;
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE13_ERR_RSVD0 = 33 ;
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE13_ERR_RSVD0_LEN = 31 ;
+
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE14_ERR_VLD = 0 ;
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE14_ERR_DETAIL = 1 ;
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE14_ERR_DETAIL_LEN = 32 ;
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE14_ERR_RSVD0 = 33 ;
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE14_ERR_RSVD0_LEN = 31 ;
+
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE15_ERR_VLD = 0 ;
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE15_ERR_DETAIL = 1 ;
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE15_ERR_DETAIL_LEN = 32 ;
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE15_ERR_RSVD0 = 33 ;
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE15_ERR_RSVD0_LEN = 31 ;
+
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE2_ERR_VLD = 0 ;
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE2_ERR_DETAIL = 1 ;
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE2_ERR_DETAIL_LEN = 32 ;
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE2_ERR_RSVD0 = 33 ;
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE2_ERR_RSVD0_LEN = 31 ;
+
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE3_ERR_VLD = 0 ;
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE3_ERR_DETAIL = 1 ;
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE3_ERR_DETAIL_LEN = 32 ;
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE3_ERR_RSVD0 = 33 ;
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE3_ERR_RSVD0_LEN = 31 ;
+
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE4_ERR_VLD = 0 ;
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE4_ERR_DETAIL = 1 ;
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE4_ERR_DETAIL_LEN = 32 ;
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE4_ERR_RSVD0 = 33 ;
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE4_ERR_RSVD0_LEN = 31 ;
+
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE5_ERR_VLD = 0 ;
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE5_ERR_DETAIL = 1 ;
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE5_ERR_DETAIL_LEN = 32 ;
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE5_ERR_RSVD0 = 33 ;
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE5_ERR_RSVD0_LEN = 31 ;
+
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE6_ERR_VLD = 0 ;
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE6_ERR_DETAIL = 1 ;
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE6_ERR_DETAIL_LEN = 32 ;
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE6_ERR_RSVD0 = 33 ;
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE6_ERR_RSVD0_LEN = 31 ;
+
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE7_ERR_VLD = 0 ;
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE7_ERR_DETAIL = 1 ;
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE7_ERR_DETAIL_LEN = 32 ;
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE7_ERR_RSVD0 = 33 ;
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE7_ERR_RSVD0_LEN = 31 ;
+
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE8_ERR_VLD = 0 ;
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE8_ERR_DETAIL = 1 ;
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE8_ERR_DETAIL_LEN = 32 ;
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE8_ERR_RSVD0 = 33 ;
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE8_ERR_RSVD0_LEN = 31 ;
+
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE9_ERR_VLD = 0 ;
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE9_ERR_DETAIL = 1 ;
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE9_ERR_DETAIL_LEN = 32 ;
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE9_ERR_RSVD0 = 33 ;
+static const uint8_t P9N2__NTL1_INT_LOG_1_PE9_ERR_RSVD0_LEN = 31 ;
+
+static const uint8_t P9N2_PU_INT_PC_AIB_RX_CRD_CMD_RESERVED_0_1 = 0 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_RX_CRD_CMD_RESERVED_0_1_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_RX_CRD_CMD_CH0_MAX = 2 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_RX_CRD_CMD_CH0_MAX_LEN = 6 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_RX_CRD_CMD_RESERVED_8_9 = 8 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_RX_CRD_CMD_RESERVED_8_9_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_RX_CRD_CMD_CH1_MAX = 10 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_RX_CRD_CMD_CH1_MAX_LEN = 6 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_RX_CRD_CMD_RESERVED_16_17 = 16 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_RX_CRD_CMD_RESERVED_16_17_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_RX_CRD_CMD_CH2_MAX = 18 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_RX_CRD_CMD_CH2_MAX_LEN = 6 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_RX_CRD_CMD_RESERVED_24_25 = 24 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_RX_CRD_CMD_RESERVED_24_25_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_RX_CRD_CMD_CH3_MAX = 26 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_RX_CRD_CMD_CH3_MAX_LEN = 6 ;
+
+static const uint8_t P9N2_PU_INT_PC_AIB_RX_CRD_DAT_RESERVED_0_1 = 0 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_RX_CRD_DAT_RESERVED_0_1_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_RX_CRD_DAT_CH0_MAX = 2 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_RX_CRD_DAT_CH0_MAX_LEN = 6 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_RX_CRD_DAT_RESERVED_8_9 = 8 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_RX_CRD_DAT_RESERVED_8_9_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_RX_CRD_DAT_CH1_MAX = 10 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_RX_CRD_DAT_CH1_MAX_LEN = 6 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_RX_CRD_DAT_RESERVED_16_17 = 16 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_RX_CRD_DAT_RESERVED_16_17_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_RX_CRD_DAT_CH2_MAX = 18 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_RX_CRD_DAT_CH2_MAX_LEN = 6 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_RX_CRD_DAT_RESERVED_24_25 = 24 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_RX_CRD_DAT_RESERVED_24_25_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_RX_CRD_DAT_CH3_MAX = 26 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_RX_CRD_DAT_CH3_MAX_LEN = 6 ;
+
+static const uint8_t P9N2_PU_INT_PC_AIB_RX_CRD_INIT_INIT_REQUEST = 0 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_RX_CRD_INIT_RESERVED_1_7 = 1 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_RX_CRD_INIT_RESERVED_1_7_LEN = 7 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_RX_CRD_INIT_INIT_TIMER = 8 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_RX_CRD_INIT_INIT_TIMER_LEN = 8 ;
+
+static const uint8_t P9N2_PU_INT_PC_AIB_TX_CRD_CRD_INIT_REQUEST = 24 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_TX_CRD_RESERVED_25 = 25 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_TX_CRD_RSD_DMA_READ = 26 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_TX_CRD_RSD_DMA_READ_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_TX_CRD_RSD_VPC_LD_RMT = 28 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_TX_CRD_RSD_VPC_LD_RMT_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_TX_CRD_RSD_AT_MACRO = 30 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_TX_CRD_RSD_AT_MACRO_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_TX_CRD_RESERVED_32_34 = 32 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_TX_CRD_RESERVED_32_34_LEN = 3 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_TX_CRD_READ_POOL = 35 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_TX_CRD_READ_POOL_LEN = 5 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_TX_CRD_RESERVED_40_47 = 40 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_TX_CRD_RESERVED_40_47_LEN = 8 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_TX_CRD_RSD_TCTXT_WRITE = 48 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_TX_CRD_RSD_TCTXT_WRITE_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_TX_CRD_RESERVED_50_51 = 50 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_TX_CRD_RESERVED_50_51_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_TX_CRD_RSD_DMA_WRITE = 52 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_TX_CRD_RSD_DMA_WRITE_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_TX_CRD_RSD_VPC_ST_RMT = 54 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_TX_CRD_RSD_VPC_ST_RMT_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_TX_CRD_RSD_VPC_ST_RMT_VC = 56 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_TX_CRD_RSD_VPC_ST_RMT_VC_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_TX_CRD_RESERVED_58 = 58 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_TX_CRD_WRITE_POOL = 59 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_TX_CRD_WRITE_POOL_LEN = 5 ;
+
+static const uint8_t P9N2_PU_INT_PC_AIB_TX_ORDER_TCTXT_RSP_WR_ORDERING = 12 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_TX_ORDER_RELAXED_DMA_RD_WR_ORDERING = 13 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_TX_ORDER_RELAXED_RMT_WR_ORDERING = 14 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_TX_ORDER_RELAXED_RMT_VC_WR_ORDERING = 15 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_TX_ORDER_REGS_ORDERING_TAG = 16 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_TX_ORDER_REGS_ORDERING_TAG_LEN = 8 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_TX_ORDER_VPC_DMA_ORDERING_TAG = 24 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_TX_ORDER_VPC_DMA_ORDERING_TAG_LEN = 8 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_TX_ORDER_VPC_LD_RSP_ORDERING_TAG = 32 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_TX_ORDER_VPC_LD_RSP_ORDERING_TAG_LEN = 8 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_TX_ORDER_VPC_LD_RMT_ORDERING_TAG = 40 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_TX_ORDER_VPC_LD_RMT_ORDERING_TAG_LEN = 8 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_TX_ORDER_VPC_ST_RMT_ORDERING_TAG = 48 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_TX_ORDER_VPC_ST_RMT_ORDERING_TAG_LEN = 8 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_TX_ORDER_VPC_ST_RMT_VC_ORDERING_TAG = 56 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_TX_ORDER_VPC_ST_RMT_VC_ORDERING_TAG_LEN = 8 ;
+
+static const uint8_t P9N2_PU_INT_PC_AIB_TX_PRIO_ATX_LIMIT_AT_DEM_IN_PIPE = 40 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_TX_PRIO_RESERVED_41_43 = 41 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_TX_PRIO_RESERVED_41_43_LEN = 3 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_TX_PRIO_ATX_FOR_REGS = 44 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_TX_PRIO_ATX_FOR_REGS_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_TX_PRIO_ATX_FOR_TCTXT_RSP_WR = 46 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_TX_PRIO_ATX_FOR_TCTXT_RSP_WR_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_TX_PRIO_ATX_FOR_BLCK_UPD = 48 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_TX_PRIO_ATX_FOR_BLCK_UPD_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_TX_PRIO_RESERVED_50_51 = 50 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_TX_PRIO_RESERVED_50_51_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_TX_PRIO_ATX_FOR_VPC_DMA = 52 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_TX_PRIO_ATX_FOR_VPC_DMA_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_TX_PRIO_ATX_FOR_VPC_CI_LD = 54 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_TX_PRIO_ATX_FOR_VPC_CI_LD_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_TX_PRIO_ATX_FOR_VPC_LD_RMT = 56 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_TX_PRIO_ATX_FOR_VPC_LD_RMT_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_TX_PRIO_ATX_FOR_VPC_ST_LCL_VC = 58 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_TX_PRIO_ATX_FOR_VPC_ST_LCL_VC_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_TX_PRIO_ATX_FOR_VPC_ST_RMT = 60 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_TX_PRIO_ATX_FOR_VPC_ST_RMT_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_TX_PRIO_ATX_FOR_VPC_ST_RMT_VC = 62 ;
+static const uint8_t P9N2_PU_INT_PC_AIB_TX_PRIO_ATX_FOR_VPC_ST_RMT_VC_LEN = 2 ;
+
+static const uint8_t P9N2_PU_INT_PC_AT_KILL_VALID = 0 ;
+static const uint8_t P9N2_PU_INT_PC_AT_KILL_RESERVED_24_26 = 24 ;
+static const uint8_t P9N2_PU_INT_PC_AT_KILL_RESERVED_24_26_LEN = 3 ;
+static const uint8_t P9N2_PU_INT_PC_AT_KILL_BLOCKID = 27 ;
+static const uint8_t P9N2_PU_INT_PC_AT_KILL_BLOCKID_LEN = 5 ;
+static const uint8_t P9N2_PU_INT_PC_AT_KILL_OFFSET = 48 ;
+static const uint8_t P9N2_PU_INT_PC_AT_KILL_OFFSET_LEN = 13 ;
+static const uint8_t P9N2_PU_INT_PC_AT_KILL_RESERVED_61_63 = 61 ;
+static const uint8_t P9N2_PU_INT_PC_AT_KILL_RESERVED_61_63_LEN = 3 ;
+
+static const uint8_t P9N2_PU_INT_PC_AT_KILL_MASK_RESERVED_24_26 = 24 ;
+static const uint8_t P9N2_PU_INT_PC_AT_KILL_MASK_RESERVED_24_26_LEN = 3 ;
+static const uint8_t P9N2_PU_INT_PC_AT_KILL_MASK_BLOCKID = 27 ;
+static const uint8_t P9N2_PU_INT_PC_AT_KILL_MASK_BLOCKID_LEN = 5 ;
+static const uint8_t P9N2_PU_INT_PC_AT_KILL_MASK_OFFSET = 48 ;
+static const uint8_t P9N2_PU_INT_PC_AT_KILL_MASK_OFFSET_LEN = 13 ;
+static const uint8_t P9N2_PU_INT_PC_AT_KILL_MASK_RESERVED_61_63 = 61 ;
+static const uint8_t P9N2_PU_INT_PC_AT_KILL_MASK_RESERVED_61_63_LEN = 3 ;
+
+static const uint8_t P9N2_PU_INT_PC_DBG_ECC_DIS_CRESP_CORR = 0 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_ECC_DIS_ARX_DAT_CORR = 1 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_ECC_DIS_ARX_DAT_CORR_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_ECC_DIS_ARX_TAG_CORR = 3 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_ECC_DIS_MMIO_LDST_CORR = 4 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_ECC_DIS_MMIO_RSP_CORR = 5 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_ECC_DIS_VRQ_QUEUE_CORR = 6 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_ECC_DIS_AVX_CORR = 7 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_ECC_DIS_ATX_CMD_CORR = 8 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_ECC_DIS_ATX_BAR_CORR = 9 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_ECC_DIS_ATX_AT_CORR = 10 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_ECC_RESERVED_11_15 = 11 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_ECC_RESERVED_11_15_LEN = 5 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_ECC_FORCE_SINGLE_BIT_ERR = 16 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_ECC_FORCE_DOUBLE_BIT_ERR = 17 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_ECC_RESERVED_18_19 = 18 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_ECC_RESERVED_18_19_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_ECC_ARY_SELECT_ARX_TAG_SRAM = 20 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_ECC_ARY_SELECT_CRESP_SRAM = 21 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_ECC_ARY_SELECT_CMD_RSP_SRAM = 22 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_ECC_ARY_SELECT_CMD_VRQ_SRAM = 23 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_ECC_ARY_SELECT_ATX_CMD_SSA = 24 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_ECC_ARY_SELECT_ATX_CMD_SSA_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_ECC_ARY_SELECT_ATX_VPC_SSA = 26 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_ECC_ARY_SELECT_ATX_VPC_SSA_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_ECC_ARY_SELECT_ATX_BAR_SRAM = 28 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_ECC_ARY_SELECT_ATX_AT_SSA = 29 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_ECC_ARY_SELECT_ATX_AIB = 30 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_ECC_ARY_SELECT_ATX_AIB_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_ECC_RESERVED_32_37 = 32 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_ECC_RESERVED_32_37_LEN = 6 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_ECC_ATX_AIB_REQ_IDLE = 38 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_ECC_ATX_AIB_ARB_IDLE = 39 ;
+
+static const uint8_t P9N2_PU_INT_PC_DBG_INT_DBG_VLD = 0 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_INT_RESERVED_1_3 = 1 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_INT_RESERVED_1_3_LEN = 3 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_INT_DBG_LEVEL = 4 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_INT_DBG_LEVEL_LEN = 3 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_INT_RESERVED_7_8 = 7 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_INT_RESERVED_7_8_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_INT_DBG_THRDID = 9 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_INT_DBG_THRDID_LEN = 7 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_INT_RESERVED_16 = 16 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_INT_DBG_THRDID_MASK = 17 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_INT_DBG_THRDID_MASK_LEN = 7 ;
+
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_EN_ARX_CMD = 0 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_EN_ARX_VPC_REGS = 1 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_EN_CRESP_CMD = 2 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_EN_CRESP_RCMD = 3 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_EN_CRESP_CRESP = 4 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_EN_CRESP_CAM_01 = 5 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_EN_CRESP_CAM_23 = 6 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_EN_CMD_MMIO_LDST_UTIL = 7 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_EN_CMD_MMIO_LDST_CMD = 8 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_EN_CMD_MMIO_DONE_REQ = 9 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_EN_CMD_MMIO_PCMD_ARB = 10 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_EN_CMD_ARB = 11 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_EN_CMD_PROC_RCMD = 12 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_EN_CMD_PROC_MMIO = 13 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_EN_CMD_PROC_VPC = 14 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_EN_CMD_VRQ_PEND = 15 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_EN_CMD_VRQ_ARB = 16 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_EN_CMD_VRQ_ARB_DETAIL1 = 17 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_EN_CMD_VRQ_ARB_DETAIL2 = 18 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_EN_CMD_BLCK = 19 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_EN_ATX_CMD_LAT1 = 20 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_EN_ATX_CMD_LAT2 = 21 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_EN_ATX_CMD_LAT3 = 22 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_EN_ATX_ARB = 23 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_RESERVED_24_31 = 24 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_RESERVED_24_31_LEN = 8 ;
+
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX0_CNT_R0 = 0 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX0_CNT_R0_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX0_CNT_R1R = 4 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX0_CNT_R1R_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX0_CNT_R1W = 8 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX0_CNT_R1W_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX0_CNT_R2 = 12 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX0_CNT_R2_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX0_CNT_R3 = 16 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX0_CNT_R3_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX0_CNT_R4R = 20 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX0_CNT_R4R_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX0_CNT_R4W = 24 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX0_CNT_R4W_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX0_CNT_R5 = 28 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX0_CNT_R5_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX0_CNT_R6 = 32 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX0_CNT_R6_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX0_CNT_R7 = 36 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX0_CNT_R7_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX0_CNT_R8 = 40 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX0_CNT_R8_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX0_CNT_R9 = 44 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX0_CNT_R9_LEN = 4 ;
+
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX1_CNT_R0 = 0 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX1_CNT_R0_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX1_CNT_R1R = 4 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX1_CNT_R1R_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX1_CNT_R1W = 8 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX1_CNT_R1W_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX1_CNT_R2 = 12 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX1_CNT_R2_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX1_CNT_R3 = 16 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX1_CNT_R3_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX1_CNT_R4R = 20 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX1_CNT_R4R_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX1_CNT_R4W = 24 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX1_CNT_R4W_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX1_CNT_R5 = 28 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX1_CNT_R5_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX1_CNT_R6 = 32 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX1_CNT_R6_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX1_CNT_R7 = 36 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX1_CNT_R7_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX1_CNT_R8 = 40 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX1_CNT_R8_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX1_CNT_R9 = 44 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX1_CNT_R9_LEN = 4 ;
+
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX2_CNT_R0 = 0 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX2_CNT_R0_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX2_CNT_R1R = 4 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX2_CNT_R1R_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX2_CNT_R1W = 8 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX2_CNT_R1W_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX2_CNT_R2 = 12 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX2_CNT_R2_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX2_CNT_R3 = 16 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX2_CNT_R3_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX2_CNT_R4R = 20 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX2_CNT_R4R_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX2_CNT_R4W = 24 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX2_CNT_R4W_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX2_CNT_R5 = 28 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX2_CNT_R5_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX2_CNT_R6 = 32 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX2_CNT_R6_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX2_CNT_R7 = 36 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX2_CNT_R7_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX2_CNT_R8 = 40 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX2_CNT_R8_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX2_CNT_R9 = 44 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_PMC_ATX2_CNT_R9_LEN = 4 ;
+
+static const uint8_t P9N2_PU_INT_PC_DBG_TMOT_RESERVED_0_1 = 0 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_TMOT_RESERVED_0_1_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_TMOT_ARX_TIMEOUT = 2 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_TMOT_ARX_TIMEOUT_LEN = 6 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_TMOT_RESERVED_8_9 = 8 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_TMOT_RESERVED_8_9_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_TMOT_MMIO_LDST_TIMEOUT = 10 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_TMOT_MMIO_LDST_TIMEOUT_LEN = 6 ;
+
+static const uint8_t P9N2_PU_INT_PC_DBG_TRACE_RESERVED_0 = 0 ;
+static const uint8_t P9N2_PU_INT_PC_DBG_TRACE_RESERVED_1 = 1 ;
+
+static const uint8_t P9N2_PU_INT_PC_EQD_BLOCK_MODE_MODE = 0 ;
+static const uint8_t P9N2_PU_INT_PC_EQD_BLOCK_MODE_MODE_LEN = 32 ;
+
+static const uint8_t P9N2_PU_INT_PC_ERR0_CFG0_ERROR_CONFIG0 = 0 ;
+static const uint8_t P9N2_PU_INT_PC_ERR0_CFG0_ERROR_CONFIG0_LEN = 64 ;
+
+static const uint8_t P9N2_PU_INT_PC_ERR0_CFG1_ERROR_CONFIG0 = 0 ;
+static const uint8_t P9N2_PU_INT_PC_ERR0_CFG1_ERROR_CONFIG0_LEN = 64 ;
+
+static const uint8_t P9N2_PU_INT_PC_ERR0_FATAL_ERROR = 0 ;
+static const uint8_t P9N2_PU_INT_PC_ERR0_FATAL_ERROR_LEN = 64 ;
+
+static const uint8_t P9N2_PU_INT_PC_ERR0_INFO_ERROR = 0 ;
+static const uint8_t P9N2_PU_INT_PC_ERR0_INFO_ERROR_LEN = 64 ;
+
+static const uint8_t P9N2_PU_INT_PC_ERR0_RECOV_ERROR = 0 ;
+static const uint8_t P9N2_PU_INT_PC_ERR0_RECOV_ERROR_LEN = 64 ;
+
+static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_ARX_CREDIT_ERROR = 0 ;
+static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_ARX_CMD_ERROR = 1 ;
+static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_ARX_DAT_ERROR = 2 ;
+static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_ARX_ROUTE_ERROR = 3 ;
+static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_ARX_PARITY_ERROR = 4 ;
+static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_ARX_AIB_ECC_CE = 5 ;
+static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_ARX_AIB_ECC_UE = 6 ;
+static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_ARX_TAG_ECC_CE = 7 ;
+static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_ARX_TAG_ECC_UE = 8 ;
+static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_ARX_TIMEOUT_ERROR = 9 ;
+static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_RESERVED_10 = 10 ;
+static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_AVX_ARX_OVERFLOW_ERROR = 11 ;
+static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_AVX_ARX_DAT_ERROR = 12 ;
+static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_AVX_ARX_PARITY_ERROR = 13 ;
+static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_AVX_ATX_OVERFLOW_ERROR = 14 ;
+static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_AVX_ATX_DAT_ERROR = 15 ;
+static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_AVX_ATX_PARITY_ERROR = 16 ;
+static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_AVX_ATX_ECC_CE = 17 ;
+static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_AVX_ATX_ECC_UE = 18 ;
+static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_AVX_TCTXT_OVERFLOW_ERROR = 19 ;
+static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_AVX_ATX_ADDR_ERROR = 20 ;
+static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_RESERVED_21 = 21 ;
+static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_MMIO_LDST_PRIO_ERROR = 22 ;
+static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_MMIO_LDST_USR_ERROR = 23 ;
+static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_MMIO_LDST_OS_ERROR = 24 ;
+static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_MMIO_LDST_HYP_ERROR = 25 ;
+static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_MMIO_LDST_ULT_ERROR = 26 ;
+static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_PROC_MMIO_INVALID_ERROR = 27 ;
+static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_PROC_MMIO_USR_ERROR = 28 ;
+static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_PROC_MMIO_OS_ERROR = 29 ;
+static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_PROC_MMIO_HYP_ERROR = 30 ;
+static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_PROC_MMIO_ULT_ERROR = 31 ;
+static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_ATX_CMD_FIFO_ERROR = 32 ;
+static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_ATX_VPC_FIFO_ERROR = 33 ;
+static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_ATX_SLOT_OVERFLOW_ERROR = 34 ;
+static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_ATX_BAR_INVALID_ERROR = 35 ;
+static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_ATX_BAR_OFFSET_ERROR = 36 ;
+static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_ATX_TAG_UNDERFLOW_ERROR = 37 ;
+static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_ATX_TAG_RELEASE_ERROR = 38 ;
+static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_ATX_CREDIT_UNDERFLOW_ERROR = 39 ;
+static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_ATX_CREDIT_OVERFLOW_ERROR = 40 ;
+static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_RESERVED_41 = 41 ;
+static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_ATX_PARITY_ERROR = 42 ;
+static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_ATX_ECC_CE = 43 ;
+static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_ATX_CMD_ECC_UE = 44 ;
+static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_ATX_VPC_ECC_UE = 45 ;
+static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_ATX_BAR_ECC_UE = 46 ;
+static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_ATX_AT_CAM_STATE_ERROR = 47 ;
+static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_ATX_AT_CAM_MULTIHIT_ERROR = 48 ;
+static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_ATX_AT_PARITY_ERROR = 49 ;
+static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_ATX_AT_PREF_REQ_ERROR = 50 ;
+static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_ATX_AT_PREF_SLOTID_ERROR = 51 ;
+static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_ATX_AT_PREFQ_OVERFLOW_ERROR = 52 ;
+static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_ATX_AT_PREFQ_UNDERFLOW_ERROR = 53 ;
+static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_ATX_AT_RD_REQ_CMD_ERROR = 54 ;
+static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_ATX_AT_BAR_VALID_ERROR = 55 ;
+static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_ATX_AT_BAR_PAGE_SIZE_ERROR = 56 ;
+static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_ATX_AT_BAR_INDIR_ERROR = 57 ;
+static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_ATX_AT_ECC_CE = 58 ;
+static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_ATX_AT_ECC_UE = 59 ;
+static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_RESERVED_60 = 60 ;
+static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_REGS_PARITY_ERROR = 61 ;
+static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_SCOM0_ERROR = 62 ;
+static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_SCOM1_ERROR = 63 ;
+
+static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_DETAIL_DETAIL = 0 ;
+static const uint8_t P9N2_PU_INT_PC_ERR0_WOF_DETAIL_DETAIL_LEN = 64 ;
+
+static const uint8_t P9N2_PU_INT_PC_ERR1_CFG0_ERROR_CONFIG0 = 0 ;
+static const uint8_t P9N2_PU_INT_PC_ERR1_CFG0_ERROR_CONFIG0_LEN = 64 ;
+
+static const uint8_t P9N2_PU_INT_PC_ERR1_CFG1_ERROR_CONFIG0 = 0 ;
+static const uint8_t P9N2_PU_INT_PC_ERR1_CFG1_ERROR_CONFIG0_LEN = 64 ;
+
+static const uint8_t P9N2_PU_INT_PC_ERR1_FATAL_ERROR = 0 ;
+static const uint8_t P9N2_PU_INT_PC_ERR1_FATAL_ERROR_LEN = 64 ;
+
+static const uint8_t P9N2_PU_INT_PC_ERR1_INFO_ERROR = 0 ;
+static const uint8_t P9N2_PU_INT_PC_ERR1_INFO_ERROR_LEN = 64 ;
+
+static const uint8_t P9N2_PU_INT_PC_ERR1_RECOV_ERROR = 0 ;
+static const uint8_t P9N2_PU_INT_PC_ERR1_RECOV_ERROR_LEN = 64 ;
+
+static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_CMD_ARB_CONFIG_ERROR = 0 ;
+static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_CMD_ARB_PARITY_ERROR = 1 ;
+static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_CMD_ARB_VPC_RSP_ERROR = 2 ;
+static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_RESERVED_3 = 3 ;
+static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_CRESP_BLK_GRP_ERROR = 4 ;
+static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_CRESP_CAM_ALLOC_ERROR = 5 ;
+static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_CRESP_CAM_STATE_ERROR = 6 ;
+static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_CRESP_CAM_RCMD_MULTIHIT_ERROR = 7 ;
+static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_CRESP_CAM_RCMD_ASSIGN_ERROR = 8 ;
+static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_CRESP_CAM_CRESP_SEQ_ERROR = 9 ;
+static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_CRESP_CAM_CRESP_REQ_ACK_ERROR = 10 ;
+static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_CRESP_PARITY_ERROR = 11 ;
+static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_CRESP_ECC_CE = 12 ;
+static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_CRESP_ECC_UE = 13 ;
+static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_CMD_PIPE_PARITY_ERROR = 14 ;
+static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_TCTXT_PARITY_ERROR = 15 ;
+static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_RESERVED_16 = 16 ;
+static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_BLK_CNT_OVERFLOW_ERROR = 17 ;
+static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_BLK_CNT_UNDERFLOW_ERROR = 18 ;
+static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_BLK_PARITY_ERROR = 19 ;
+static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_RESERVED_20 = 20 ;
+static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_PROC_RCMD_THRD_MULTIHIT_ERROR = 21 ;
+static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_PROC_RCMD_THRD_ASSIGN_ERROR = 22 ;
+static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_PROC_RCMD_PRESP_MULTIHIT_ERROR = 23 ;
+static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_PROC_RCMD_CRESP_SET_ERROR = 24 ;
+static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_PROC_CRESP_HIT_ERROR = 25 ;
+static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_PROC_LSI_HIT_ERROR = 26 ;
+static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_PROC_MMIO_DATA_CNFLT_ERROR = 27 ;
+static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_PROC_MMIO_DATA_RSP_ERROR = 28 ;
+static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_PROC_VRQ_CMD_ERROR = 29 ;
+static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_PROC_VRQ_REQ_ERROR = 30 ;
+static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_PROC_PARITY_ERROR = 31 ;
+static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_MMIO_LDST_STATE_VLD_ERROR = 32 ;
+static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_MMIO_LDST_STATE_PEND_ERROR = 33 ;
+static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_MMIO_LDST_STATE_WAIT_ERROR = 34 ;
+static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_MMIO_LDST_STATE_TMOT_ERROR = 35 ;
+static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_MMIO_LDST_LD_OVERFLOW_ERROR = 36 ;
+static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_MMIO_LDST_ST_OVERFLOW_ERROR = 37 ;
+static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_MMIO_LDST_PARITY_ERROR = 38 ;
+static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_MMIO_LDST_ECC_CE = 39 ;
+static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_MMIO_LDST_ECC_UE = 40 ;
+static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_MMIO_DONE_CTRL_ERROR = 41 ;
+static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_MMIO_DONE_PARITY_ERROR = 42 ;
+static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_MMIO_PCMD_CFG_ERROR = 43 ;
+static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_MMIO_PCMD_FIFO_ERROR = 44 ;
+static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_MMIO_PCMD_PARITY_ERROR = 45 ;
+static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_MMIO_RSP_DATA_ERROR = 46 ;
+static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_MMIO_RSP_LVL_ERROR = 47 ;
+static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_MMIO_RSP_VPD_ERROR = 48 ;
+static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_MMIO_RSP_PARITY_ERROR = 49 ;
+static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_MMIO_RSP_ECC_CE = 50 ;
+static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_MMIO_RSP_ECC_UE = 51 ;
+static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_RESERVED_52 = 52 ;
+static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_RESERVED_53 = 53 ;
+static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_VRQ_CFG_QSIZE_ERROR = 54 ;
+static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_VRQ_CFG_PEND_ARB_ERROR = 55 ;
+static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_VRQ_CFG_VPC_ARB_ERROR = 56 ;
+static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_VRQ_CFG_VPC_CRED_ERROR = 57 ;
+static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_VRQ_CTRL_ERROR = 58 ;
+static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_VRQ_PARITY_ERROR = 59 ;
+static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_VRQ_OVERFLOW_ERROR = 60 ;
+static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_VRQ_UNDERFLOW_ERROR = 61 ;
+static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_VRQ_ECC_CE = 62 ;
+static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_VRQ_ECC_UE = 63 ;
+
+static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_DETAIL_DETAIL = 0 ;
+static const uint8_t P9N2_PU_INT_PC_ERR1_WOF_DETAIL_DETAIL_LEN = 64 ;
+
+static const uint8_t P9N2_PU_INT_PC_GLOBAL_CFG_INDIRECT_MODE = 32 ;
+static const uint8_t P9N2_PU_INT_PC_GLOBAL_CFG_HOSTBOOT_MODE = 33 ;
+static const uint8_t P9N2_PU_INT_PC_GLOBAL_CFG_RESERVED_34_39 = 34 ;
+static const uint8_t P9N2_PU_INT_PC_GLOBAL_CFG_RESERVED_34_39_LEN = 6 ;
+static const uint8_t P9N2_PU_INT_PC_GLOBAL_CFG_CFG_CHIPID_OVERRIDE = 40 ;
+static const uint8_t P9N2_PU_INT_PC_GLOBAL_CFG_RESERVED_41_43 = 41 ;
+static const uint8_t P9N2_PU_INT_PC_GLOBAL_CFG_RESERVED_41_43_LEN = 3 ;
+static const uint8_t P9N2_PU_INT_PC_GLOBAL_CFG_CFG_CHIPID = 44 ;
+static const uint8_t P9N2_PU_INT_PC_GLOBAL_CFG_CFG_CHIPID_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_GLOBAL_CFG_CFG_VPD_END_PRIO_SEL = 48 ;
+static const uint8_t P9N2_PU_INT_PC_GLOBAL_CFG_CFG_VPD_END_PRIO_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_PC_GLOBAL_CFG_RESERVED_50_51 = 50 ;
+static const uint8_t P9N2_PU_INT_PC_GLOBAL_CFG_RESERVED_50_51_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_PC_GLOBAL_CFG_CFG_VPD_BG_TABLE_COMPRESS = 52 ;
+static const uint8_t P9N2_PU_INT_PC_GLOBAL_CFG_CFG_VPD_BG_TABLE_COMPRESS_LEN = 4 ;
+
+static const uint8_t P9N2_PU_INT_PC_IVE_BLOCK_MODE_MODE = 0 ;
+static const uint8_t P9N2_PU_INT_PC_IVE_BLOCK_MODE_MODE_LEN = 32 ;
+
+static const uint8_t P9N2_PU_INT_PC_LSI_TRIG_EOI_LBS1_CMD_Q_BIT = 63 ;
+
+static const uint8_t P9N2_PU_INT_PC_LSI_TRIG_LD_LBS1_CMD_P_BIT = 62 ;
+static const uint8_t P9N2_PU_INT_PC_LSI_TRIG_LD_LBS1_CMD_Q_BIT = 63 ;
+
+static const uint8_t P9N2_PU_INT_PC_MMIO_ARB_CFG_LDST_PRIO_SET_LD = 0 ;
+static const uint8_t P9N2_PU_INT_PC_MMIO_ARB_CFG_LDST_PRIO_SET_LD_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_PC_MMIO_ARB_CFG_LDST_PRIO_RSP_LD = 2 ;
+static const uint8_t P9N2_PU_INT_PC_MMIO_ARB_CFG_LDST_PRIO_RSP_LD_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_PC_MMIO_ARB_RESERVED_4_5 = 4 ;
+static const uint8_t P9N2_PU_INT_PC_MMIO_ARB_RESERVED_4_5_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_PC_MMIO_ARB_CFG_DONE_PARSE_PULL_RR_SEL = 6 ;
+static const uint8_t P9N2_PU_INT_PC_MMIO_ARB_CFG_DONE_PARSE_PULL_RR_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_PC_MMIO_ARB_CFG_DONE_PARSE_IACK_RR_SEL = 8 ;
+static const uint8_t P9N2_PU_INT_PC_MMIO_ARB_CFG_DONE_PARSE_IACK_RR_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_PC_MMIO_ARB_CFG_DONE_PULL_PRIO_HYP = 10 ;
+static const uint8_t P9N2_PU_INT_PC_MMIO_ARB_CFG_DONE_PULL_PRIO_HYP_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_PC_MMIO_ARB_CFG_DONE_IACK_PRIO_HYP = 12 ;
+static const uint8_t P9N2_PU_INT_PC_MMIO_ARB_CFG_DONE_IACK_PRIO_HYP_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_PC_MMIO_ARB_CFG_DONE_PRIO_IACK = 14 ;
+static const uint8_t P9N2_PU_INT_PC_MMIO_ARB_CFG_DONE_PRIO_IACK_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_PC_MMIO_ARB_RESERVED_16 = 16 ;
+static const uint8_t P9N2_PU_INT_PC_MMIO_ARB_CFG_PCMD_PRIO_LDST_SET = 17 ;
+static const uint8_t P9N2_PU_INT_PC_MMIO_ARB_CFG_PCMD_PRIO_LDST_SET_LEN = 3 ;
+static const uint8_t P9N2_PU_INT_PC_MMIO_ARB_RESERVED_20 = 20 ;
+static const uint8_t P9N2_PU_INT_PC_MMIO_ARB_CFG_PCMD_PRIO_LDST_RSP = 21 ;
+static const uint8_t P9N2_PU_INT_PC_MMIO_ARB_CFG_PCMD_PRIO_LDST_RSP_LEN = 3 ;
+static const uint8_t P9N2_PU_INT_PC_MMIO_ARB_RESERVED_24 = 24 ;
+static const uint8_t P9N2_PU_INT_PC_MMIO_ARB_CFG_PCMD_PRIO_DONE = 25 ;
+static const uint8_t P9N2_PU_INT_PC_MMIO_ARB_CFG_PCMD_PRIO_DONE_LEN = 3 ;
+static const uint8_t P9N2_PU_INT_PC_MMIO_ARB_RESERVED_28 = 28 ;
+static const uint8_t P9N2_PU_INT_PC_MMIO_ARB_CFG_PCMD_PRIO_RR = 29 ;
+static const uint8_t P9N2_PU_INT_PC_MMIO_ARB_CFG_PCMD_PRIO_RR_LEN = 3 ;
+
+static const uint8_t P9N2_PU_INT_PC_PCMD_ARB_RESERVED_0 = 0 ;
+static const uint8_t P9N2_PU_INT_PC_PCMD_ARB_CFG_PRIO_LSI = 1 ;
+static const uint8_t P9N2_PU_INT_PC_PCMD_ARB_CFG_PRIO_LSI_LEN = 3 ;
+static const uint8_t P9N2_PU_INT_PC_PCMD_ARB_RESERVED_4 = 4 ;
+static const uint8_t P9N2_PU_INT_PC_PCMD_ARB_CFG_PRIO_MMIO = 5 ;
+static const uint8_t P9N2_PU_INT_PC_PCMD_ARB_CFG_PRIO_MMIO_LEN = 3 ;
+static const uint8_t P9N2_PU_INT_PC_PCMD_ARB_RESERVED_8 = 8 ;
+static const uint8_t P9N2_PU_INT_PC_PCMD_ARB_CFG_PRIO_VRQ_REQ = 9 ;
+static const uint8_t P9N2_PU_INT_PC_PCMD_ARB_CFG_PRIO_VRQ_REQ_LEN = 3 ;
+static const uint8_t P9N2_PU_INT_PC_PCMD_ARB_RESERVED_12 = 12 ;
+static const uint8_t P9N2_PU_INT_PC_PCMD_ARB_CFG_PRIO_VRQ_RSP = 13 ;
+static const uint8_t P9N2_PU_INT_PC_PCMD_ARB_CFG_PRIO_VRQ_RSP_LEN = 3 ;
+static const uint8_t P9N2_PU_INT_PC_PCMD_ARB_RESERVED_16 = 16 ;
+static const uint8_t P9N2_PU_INT_PC_PCMD_ARB_CFG_PRIO_RR = 17 ;
+static const uint8_t P9N2_PU_INT_PC_PCMD_ARB_CFG_PRIO_RR_LEN = 3 ;
+
+static const uint8_t P9N2_PU_INT_PC_VPC_ADDITIONAL_PERF_1_P0_IS_IDLE = 0 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_ADDITIONAL_PERF_1_P1_IS_IDLE = 1 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_ADDITIONAL_PERF_1_RESERVED_2_9 = 2 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_ADDITIONAL_PERF_1_RESERVED_2_9_LEN = 8 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_ADDITIONAL_PERF_1_MAX_PTAG_IN_USE = 10 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_ADDITIONAL_PERF_1_MAX_PTAG_IN_USE_LEN = 6 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_ADDITIONAL_PERF_1_RESERVED_16_27 = 16 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_ADDITIONAL_PERF_1_RESERVED_16_27_LEN = 12 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_ADDITIONAL_PERF_1_MAX_UNLOCK_IN_FIFO = 28 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_ADDITIONAL_PERF_1_MAX_UNLOCK_IN_FIFO_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_ADDITIONAL_PERF_1_RESERVED_32_33 = 32 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_ADDITIONAL_PERF_1_RESERVED_32_33_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_ADDITIONAL_PERF_1_MAX_OUTSTANDING_WB = 34 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_ADDITIONAL_PERF_1_MAX_OUTSTANDING_WB_LEN = 6 ;
+
+static const uint8_t P9N2_PU_INT_PC_VPC_ADDITIONAL_PERF_2_RESERVED_0_1 = 0 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_ADDITIONAL_PERF_2_RESERVED_0_1_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_VPD_FETCH = 2 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_VPD_FETCH_LEN = 6 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_ADDITIONAL_PERF_2_RESERVED_8_9 = 8 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_ADDITIONAL_PERF_2_RESERVED_8_9_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_CI_LOAD = 10 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_CI_LOAD_LEN = 6 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_ADDITIONAL_PERF_2_RESERVED_16_17 = 16 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_ADDITIONAL_PERF_2_RESERVED_16_17_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_ST_RMT = 18 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_ST_RMT_LEN = 6 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_ADDITIONAL_PERF_2_RESERVED_24_25 = 24 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_ADDITIONAL_PERF_2_RESERVED_24_25_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_ST_RMT_VC = 26 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_ST_RMT_VC_LEN = 6 ;
+
+static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_EN_ENABLE = 0 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_EN_ENABLE_LEN = 32 ;
+
+static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA0_VP = 0 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA0_SECURE = 7 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA0_PGOFFIRSTLS = 26 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA0_PGOFFIRSTLS_LEN = 6 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA0_IVE_BLOCK = 32 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA0_IVE_BLOCK_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA0_IVE_INDEX = 36 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA0_IVE_INDEX_LEN = 28 ;
+
+static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA2_IPB = 16 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA2_IPB_LEN = 8 ;
+
+static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA3_MIG_REG = 0 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA3_MIG_REG_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA3_CL = 8 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA3_CL_LEN = 48 ;
+
+static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA4_VG = 0 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA4_SATURATE_VALUE = 20 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA4_SATURATE_VALUE_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA4_PGOFNEXTLS = 26 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA4_PGOFNEXTLS_LEN = 6 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA4_EQD_BLOCK = 36 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA4_EQD_BLOCK_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA4_EQD_INDEX = 40 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA4_EQD_INDEX_LEN = 23 ;
+
+static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA5_BKLG0 = 2 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA5_BKLG0_LEN = 22 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA5_BKLG1 = 26 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA5_BKLG1_LEN = 22 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA5_BKLG2_1 = 50 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA5_BKLG2_1_LEN = 14 ;
+
+static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA6_BKLG2_2 = 0 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA6_BKLG2_2_LEN = 8 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA6_BKLG3 = 10 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA6_BKLG3_LEN = 22 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA6_BKLG4 = 34 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA6_BKLG4_LEN = 22 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA6_BKLG5_1 = 58 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA6_BKLG5_1_LEN = 6 ;
+
+static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA7_BKLG5_2 = 0 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA7_BKLG5_2_LEN = 16 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA7_BKLG6 = 18 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA7_BKLG6_LEN = 22 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA7_BKLG7 = 42 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_DATA7_BKLG7_LEN = 22 ;
+
+static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_SPEC_CONFLICT = 0 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_SPEC_RESERVED_1_7 = 1 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_SPEC_RESERVED_1_7_LEN = 7 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_SPEC_FULL = 8 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_SPEC_RESERVED_9_26 = 9 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_SPEC_RESERVED_9_26_LEN = 18 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_SPEC_BLOCKID = 27 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_SPEC_BLOCKID_LEN = 5 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_SPEC_RESERVED_32_44 = 32 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_SPEC_RESERVED_32_44_LEN = 13 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_SPEC_OFFSET = 45 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_CACHE_WATCH_SPEC_OFFSET_LEN = 19 ;
+
+static const uint8_t P9N2_PU_INT_PC_VPC_CONFIG_RESERVED_24_25 = 24 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_CONFIG_RESERVED_24_25_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_CONFIG_PTAG_MAX_IN_USE = 26 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_CONFIG_PTAG_MAX_IN_USE_LEN = 6 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_CONFIG_RESERVED_32 = 32 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_CONFIG_SYNC_DONE = 33 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_CONFIG_SYNC_DONE_LEN = 3 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_CONFIG_RESERVED_36_39 = 36 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_CONFIG_RESERVED_36_39_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_CONFIG_LCL_FIRST_GRPSCAN_ENA = 40 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_CONFIG_LCL_FIRST_GRPSCAN_RMT_ENA = 41 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_CONFIG_RMT_FIRST_GRPSCAN_ENA = 42 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_CONFIG_LSMFB_SCAN_ALL_PRIO_ENA = 43 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_CONFIG_P0_BACK2BACK_MODE_ENA = 44 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_CONFIG_P0_BACK2BACK_MODE_ENA_LEN = 3 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_CONFIG_RESERVED_47_50 = 47 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_CONFIG_RESERVED_47_50_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_CONFIG_ENHANCED_HASH = 51 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_CONFIG_BG_SCAN_RATE = 52 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_CONFIG_BG_SCAN_RATE_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_CONFIG_RESERVED_56_57 = 56 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_CONFIG_RESERVED_56_57_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_CONFIG_FORCE_INVALIDATE = 58 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_CONFIG_MAX_ENTRIES_IN_MODIFIED = 59 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_CONFIG_MAX_ENTRIES_IN_MODIFIED_LEN = 5 ;
+
+static const uint8_t P9N2_PU_INT_PC_VPC_DEBUG_RESERVED_0_29 = 0 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_DEBUG_RESERVED_0_29_LEN = 30 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_DEBUG_DIS_LD_ECC_CORRECTION = 30 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_DEBUG_DIS_TAG_ECC_CORRECTION = 31 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_DEBUG_DIS_TAG_ECC_CORRECTION_LEN = 8 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_DEBUG_DIS_STATE_ECC_CORRECTION = 39 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_DEBUG_DIS_STATE_ECC_CORRECTION_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_DEBUG_DIS_PTAG_ECC_CORRECTION = 41 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_DEBUG_DIS_PTAG_ECC_CORRECTION_LEN = 3 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_DEBUG_DIS_DATA_ECC_CORRECTION = 44 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_DEBUG_DIS_DATA_ECC_CORRECTION_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_DEBUG_FORCE_SINGLE_BIT_ECC_ERR = 48 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_DEBUG_FORCE_DOUBLE_BIT_ECC_ERR = 49 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_DEBUG_ECC_ERR_INJ_PARTITION_SEL = 50 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_DEBUG_ECC_ERR_INJ_PARTITION_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_DEBUG_ECC_ERR_INJ_ARRAY_SEL = 52 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_DEBUG_ECC_ERR_INJ_ARRAY_SEL_LEN = 5 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_DEBUG_PMC_ENABLE = 57 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_DEBUG_TRACE_ENABLE = 58 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_DEBUG_RESERVED_59 = 59 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_DEBUG_USE_WATCH_TO_READ_CTRL_ARY = 60 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_DEBUG_CACHE_CTRL_ARY_SELECT = 61 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_DEBUG_CACHE_CTRL_ARY_SELECT_LEN = 3 ;
+
+static const uint8_t P9N2_PU_INT_PC_VPC_ERR_CFG0_ERROR_CONFIG = 0 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_ERR_CFG0_ERROR_CONFIG_LEN = 64 ;
+
+static const uint8_t P9N2_PU_INT_PC_VPC_ERR_CFG1_ERROR_CONFIG = 0 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_ERR_CFG1_ERROR_CONFIG_LEN = 64 ;
+
+static const uint8_t P9N2_PU_INT_PC_VPC_FATAL_ERR_ERROR = 0 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_FATAL_ERR_ERROR_LEN = 64 ;
+
+static const uint8_t P9N2_PU_INT_PC_VPC_INFO_ERR_ERROR = 0 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_INFO_ERR_ERROR_LEN = 64 ;
+
+static const uint8_t P9N2_PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_RESERVED_0_25 = 0 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_RESERVED_0_25_LEN = 26 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_CI_STORE_RMT = 26 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_CI_STORE_RMT_LEN = 6 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_RESERVED_32_33 = 32 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_RESERVED_32_33_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_CI_STORE_RMT_VC = 34 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_CI_STORE_RMT_VC_LEN = 6 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_RESERVED_40_41 = 40 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_RESERVED_40_41_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_CI_LOAD = 42 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_CI_LOAD_LEN = 6 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_RESERVED_48_49 = 48 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_RESERVED_48_49_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_VPD_DMA_READ = 50 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_VPD_DMA_READ_LEN = 6 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_RESERVED_56_57 = 56 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_RESERVED_56_57_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_VPD_DMA_WRITE = 58 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_VPD_DMA_WRITE_LEN = 6 ;
+
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_VRQ_PULL = 0 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_VRQ_PULL_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_VRQ_PUSH_LOCAL = 4 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_VRQ_PUSH_LOCAL_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_VRQ_PUSH_REMOTE = 8 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_VRQ_PUSH_REMOTE_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_NON_SPEC_VC_LOAD = 12 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_NON_SPEC_VC_LOAD_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_NON_SPEC_SW_LOAD = 16 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_NON_SPEC_SW_LOAD_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_NON_SPEC_LOAD = 20 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_NON_SPEC_LOAD_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_LOCAL_GROUP_SCAN = 24 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_LOCAL_GROUP_SCAN_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_VRQ_CACHE_HIT = 28 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_VRQ_CACHE_HIT_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_LD_CACHE_HIT = 32 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_LD_CACHE_HIT_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_GROUP_SCAN_CACHE_HIT = 36 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_GROUP_SCAN_CACHE_HIT_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_LRU = 40 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_LRU_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_FIRST_USABLE = 44 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_FIRST_USABLE_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_RETRY = 48 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_RETRY_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_TOO_MANY_ENTRIES = 52 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_TOO_MANY_ENTRIES_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_1_RESERVED_56_63 = 56 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_1_RESERVED_56_63_LEN = 8 ;
+
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_VPD_WB = 0 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_VPD_WB_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_VPD_FETCH = 4 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_VPD_FETCH_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RSP_LCL_TCTXT = 8 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RSP_LCL_TCTXT_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RSP_LCL_VC = 12 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RSP_LCL_VC_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RSP_RMT = 16 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RSP_RMT_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RSP_RMT_VC = 20 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RSP_RMT_VC_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RSP_SW_LD = 24 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RSP_SW_LD_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RMT_PULL_1STVP = 28 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RMT_PULL_1STVP_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RMT_PULL_1STGRP = 32 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RMT_PULL_1STGRP_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RMT_PULL_VP = 36 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RMT_PULL_VP_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RMT_PULL_GRP = 40 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RMT_PULL_GRP_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_LCL_PRESS_RELIEF = 44 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_LCL_PRESS_RELIEF_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_LCL_REDIST = 48 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_LCL_REDIST_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RMT_PUSH = 52 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RMT_PUSH_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RMT_PUSH_VC = 56 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RMT_PUSH_VC_LEN = 4 ;
+
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_LCL_GRPSCAN_REPLAY = 0 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_LCL_GRPSCAN_REPLAY_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_VPD_FETCH_REPLAY = 4 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_VPD_FETCH_REPLAY_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_RSP_TCTXT_REPLAY = 8 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_RSP_TCTXT_REPLAY_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_RSP_ATX_REPLAY = 12 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_RSP_ATX_REPLAY_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_LD_REQ_REPLAY = 16 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_LD_REQ_REPLAY_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_ST_LCL_REPLAY = 20 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_ST_LCL_REPLAY_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_ST_RMT_REPLAY = 24 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_ST_RMT_REPLAY_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_ST_RMT_VC_REPLAY = 28 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_ST_RMT_VC_REPLAY_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_SAME_VPD_REPLAY = 32 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_SAME_VPD_REPLAY_LEN = 4 ;
+
+static const uint8_t P9N2_PU_INT_PC_VPC_RECOV_ERR_ERROR = 0 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_RECOV_ERR_ERROR_LEN = 64 ;
+
+static const uint8_t P9N2_PU_INT_PC_VPC_SCRUB_MASK_BLOCKID = 27 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_SCRUB_MASK_BLOCKID_LEN = 5 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_SCRUB_MASK_RESERVED_32_44 = 32 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_SCRUB_MASK_RESERVED_32_44_LEN = 13 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_SCRUB_MASK_OFFSET = 45 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_SCRUB_MASK_OFFSET_LEN = 19 ;
+
+static const uint8_t P9N2_PU_INT_PC_VPC_SCRUB_TRIG_VALID = 0 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_SCRUB_TRIG_WANT_CACHE_DISABLE = 1 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_SCRUB_TRIG_WANT_INVALIDATE = 2 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_SCRUB_TRIG_BLOCKID = 27 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_SCRUB_TRIG_BLOCKID_LEN = 5 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_SCRUB_TRIG_RESERVED_32_44 = 32 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_SCRUB_TRIG_RESERVED_32_44_LEN = 13 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_SCRUB_TRIG_OFFSET = 45 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_SCRUB_TRIG_OFFSET_LEN = 19 ;
+
+static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_RESERVED_0 = 0 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_SCRUB_WB_CREDIT_ERROR = 1 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_P1_P0_PTAG_ERROR = 2 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_PTAG_IN_USE_ERROR = 3 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_SYNC_OVERFLOW_ERROR = 4 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_P0_PARITY_ERROR = 5 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_P0_TAG_SRAM_ECC_UE = 6 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_P0_STATE_SRAM_ECC_UE = 7 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_RESERVED_8_9 = 8 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_RESERVED_8_9_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_ATX_WB_CREDIT_OVERFLOW_ERROR = 10 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_UNLOCK_FIFO_OVERFLOW_ERROR = 11 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_RESERVED_12_13 = 12 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_RESERVED_12_13_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_P0_SRAM_ECC_CE = 14 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_RESERVED_15 = 15 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_CL_INDEX_CAM_ERROR = 16 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_AIB_CREDIT_ERROR = 17 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_RESERVED_18_19 = 18 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_RESERVED_18_19_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_REPLAY_ERROR = 20 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_P1_PARITY_ERROR = 21 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_RESERVED_22_23 = 22 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_RESERVED_22_23_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_P1_DATA_SRAM_ECC_UE = 24 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_P1_PTAG_SRAM_ECC_UE = 25 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_ATX_CREDIT_OVERFLOW_ERROR = 26 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_RESERVED_27_28 = 27 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_RESERVED_27_28_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_P1_SRAM_ECC_CE = 29 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_P1_PROC_SW_ERROR = 30 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_P1_PROC_HW_ERROR = 31 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_LD_TAG_ERROR = 32 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_LD_OVERFLOW = 33 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_LD_SRAM_ECC_UE = 34 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_LD_SRAM_ECC_CE = 35 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_RESERVED_36_52 = 36 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_RESERVED_36_52_LEN = 17 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_REGS_PARITY_ERROR = 53 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_WATCH_PARITY_ERROR = 54 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_PARITY_ERROR = 55 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_RESERVED_56_62 = 56 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_RESERVED_56_62_LEN = 7 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_WATCH_NOT_OWNED_BLOCKID = 63 ;
+
+static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_DETAIL_ERROR = 0 ;
+static const uint8_t P9N2_PU_INT_PC_VPC_WOF_ERR_DETAIL_ERROR_LEN = 64 ;
+
+static const uint8_t P9N2_PU_INT_PC_VPD_BLOCK_MODE_MODE = 0 ;
+static const uint8_t P9N2_PU_INT_PC_VPD_BLOCK_MODE_MODE_LEN = 64 ;
+
+static const uint8_t P9N2_PU_INT_PC_VRQ_CFG_CFG_CORE_PUSH_EN = 0 ;
+static const uint8_t P9N2_PU_INT_PC_VRQ_CFG_RESERVED_1_2 = 1 ;
+static const uint8_t P9N2_PU_INT_PC_VRQ_CFG_RESERVED_1_2_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_PC_VRQ_CFG_CFG_QUEUE_SIZE_PULL = 3 ;
+static const uint8_t P9N2_PU_INT_PC_VRQ_CFG_CFG_QUEUE_SIZE_PULL_LEN = 5 ;
+static const uint8_t P9N2_PU_INT_PC_VRQ_CFG_RESERVED_8_10 = 8 ;
+static const uint8_t P9N2_PU_INT_PC_VRQ_CFG_RESERVED_8_10_LEN = 3 ;
+static const uint8_t P9N2_PU_INT_PC_VRQ_CFG_CFG_QUEUE_SIZE_PUSH_LCL = 11 ;
+static const uint8_t P9N2_PU_INT_PC_VRQ_CFG_CFG_QUEUE_SIZE_PUSH_LCL_LEN = 5 ;
+
+static const uint8_t P9N2_PU_INT_PC_VRQ_PEND_ARB_CFG_PARSE_QUERY_RR_SEL = 0 ;
+static const uint8_t P9N2_PU_INT_PC_VRQ_PEND_ARB_RESERVED_1 = 1 ;
+static const uint8_t P9N2_PU_INT_PC_VRQ_PEND_ARB_CFG_PARSE_PULL_RR_SEL = 2 ;
+static const uint8_t P9N2_PU_INT_PC_VRQ_PEND_ARB_CFG_PARSE_PULL_RR_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_PC_VRQ_PEND_ARB_CFG_PARSE_PUSH_RR_SEL = 4 ;
+static const uint8_t P9N2_PU_INT_PC_VRQ_PEND_ARB_CFG_PARSE_PUSH_RR_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_PC_VRQ_PEND_ARB_RESERVED_6_7 = 6 ;
+static const uint8_t P9N2_PU_INT_PC_VRQ_PEND_ARB_RESERVED_6_7_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_PC_VRQ_PEND_ARB_CFG_PULL_PRIO_HYP = 8 ;
+static const uint8_t P9N2_PU_INT_PC_VRQ_PEND_ARB_CFG_PULL_PRIO_HYP_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_PC_VRQ_PEND_ARB_CFG_PUSH_PRIO_HYP = 10 ;
+static const uint8_t P9N2_PU_INT_PC_VRQ_PEND_ARB_CFG_PUSH_PRIO_HYP_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_PC_VRQ_PEND_ARB_RESERVED_12_16 = 12 ;
+static const uint8_t P9N2_PU_INT_PC_VRQ_PEND_ARB_RESERVED_12_16_LEN = 5 ;
+static const uint8_t P9N2_PU_INT_PC_VRQ_PEND_ARB_CFG_PRIO_QUERY = 17 ;
+static const uint8_t P9N2_PU_INT_PC_VRQ_PEND_ARB_CFG_PRIO_QUERY_LEN = 3 ;
+static const uint8_t P9N2_PU_INT_PC_VRQ_PEND_ARB_RESERVED_20 = 20 ;
+static const uint8_t P9N2_PU_INT_PC_VRQ_PEND_ARB_CFG_PRIO_PUSH = 21 ;
+static const uint8_t P9N2_PU_INT_PC_VRQ_PEND_ARB_CFG_PRIO_PUSH_LEN = 3 ;
+static const uint8_t P9N2_PU_INT_PC_VRQ_PEND_ARB_RESERVED_24 = 24 ;
+static const uint8_t P9N2_PU_INT_PC_VRQ_PEND_ARB_CFG_PRIO_PULL = 25 ;
+static const uint8_t P9N2_PU_INT_PC_VRQ_PEND_ARB_CFG_PRIO_PULL_LEN = 3 ;
+static const uint8_t P9N2_PU_INT_PC_VRQ_PEND_ARB_RESERVED_28 = 28 ;
+static const uint8_t P9N2_PU_INT_PC_VRQ_PEND_ARB_CFG_PRIO_RR = 29 ;
+static const uint8_t P9N2_PU_INT_PC_VRQ_PEND_ARB_CFG_PRIO_RR_LEN = 3 ;
+
+static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_ARB_RESERVED_0 = 0 ;
+static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_ARB_CFG_PRIO_RSVD = 1 ;
+static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_ARB_CFG_PRIO_RSVD_LEN = 3 ;
+static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_ARB_CFG_STALL_PULL = 4 ;
+static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_ARB_CFG_PRIO_PULL = 5 ;
+static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_ARB_CFG_PRIO_PULL_LEN = 3 ;
+static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_ARB_CFG_STALL_PUSH_LCL = 8 ;
+static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_ARB_CFG_PRIO_PUSH_LCL = 9 ;
+static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_ARB_CFG_PRIO_PUSH_LCL_LEN = 3 ;
+static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_ARB_CFG_STALL_PUSH_ARX = 12 ;
+static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_ARB_CFG_PRIO_PUSH_ARX = 13 ;
+static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_ARB_CFG_PRIO_PUSH_ARX_LEN = 3 ;
+static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_ARB_RESERVED_16 = 16 ;
+static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_ARB_CFG_PRIO_RR = 17 ;
+static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_ARB_CFG_PRIO_RR_LEN = 3 ;
+
+static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_CRD_RESERVED_0_1 = 0 ;
+static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_CRD_RESERVED_0_1_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_CRD_CFG_PULL_RSVD = 2 ;
+static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_CRD_CFG_PULL_RSVD_LEN = 6 ;
+static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_CRD_RESERVED_8_9 = 8 ;
+static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_CRD_RESERVED_8_9_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_CRD_CFG_PULL_LMIT = 10 ;
+static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_CRD_CFG_PULL_LMIT_LEN = 6 ;
+static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_CRD_RESERVED_16_17 = 16 ;
+static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_CRD_RESERVED_16_17_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_CRD_CFG_PUSH_LCL_RSVD = 18 ;
+static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_CRD_CFG_PUSH_LCL_RSVD_LEN = 6 ;
+static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_CRD_RESERVED_24_25 = 24 ;
+static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_CRD_RESERVED_24_25_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_CRD_CFG_PUSH_LCL_LMIT = 26 ;
+static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_CRD_CFG_PUSH_LCL_LMIT_LEN = 6 ;
+static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_CRD_RESERVED_32_33 = 32 ;
+static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_CRD_RESERVED_32_33_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_CRD_CFG_PUSH_ARX_RSVD = 34 ;
+static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_CRD_CFG_PUSH_ARX_RSVD_LEN = 6 ;
+static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_CRD_RESERVED_40_41 = 40 ;
+static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_CRD_RESERVED_40_41_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_CRD_CFG_PUSH_ARX_LMIT = 42 ;
+static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_CRD_CFG_PUSH_ARX_LMIT_LEN = 6 ;
+static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_CRD_RESERVED_48_49 = 48 ;
+static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_CRD_RESERVED_48_49_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_CRD_CFG_MAX = 50 ;
+static const uint8_t P9N2_PU_INT_PC_VRQ_VPC_CRD_CFG_MAX_LEN = 6 ;
+
+static const uint8_t P9N2_PU_INT_PC_VSD_TABLE_ADDR_AUTO_INCREMENT = 0 ;
+static const uint8_t P9N2_PU_INT_PC_VSD_TABLE_ADDR_RESERVED_1_3 = 1 ;
+static const uint8_t P9N2_PU_INT_PC_VSD_TABLE_ADDR_RESERVED_1_3_LEN = 3 ;
+static const uint8_t P9N2_PU_INT_PC_VSD_TABLE_ADDR_RESERVED_12 = 12 ;
+static const uint8_t P9N2_PU_INT_PC_VSD_TABLE_ADDR_SELECT = 13 ;
+static const uint8_t P9N2_PU_INT_PC_VSD_TABLE_ADDR_SELECT_LEN = 3 ;
+static const uint8_t P9N2_PU_INT_PC_VSD_TABLE_ADDR_RESERVED_24_26 = 24 ;
+static const uint8_t P9N2_PU_INT_PC_VSD_TABLE_ADDR_RESERVED_24_26_LEN = 3 ;
+static const uint8_t P9N2_PU_INT_PC_VSD_TABLE_ADDR_ADDRESS = 27 ;
+static const uint8_t P9N2_PU_INT_PC_VSD_TABLE_ADDR_ADDRESS_LEN = 5 ;
+
+static const uint8_t P9N2__CTL_INT_REQ_INTERRUPT_00 = 0 ;
+static const uint8_t P9N2__CTL_INT_REQ_INTERRUPT_01 = 1 ;
+static const uint8_t P9N2__CTL_INT_REQ_INTERRUPT_02 = 2 ;
+static const uint8_t P9N2__CTL_INT_REQ_INTERRUPT_03 = 3 ;
+static const uint8_t P9N2__CTL_INT_REQ_INTERRUPT_04 = 4 ;
+static const uint8_t P9N2__CTL_INT_REQ_INTERRUPT_05 = 5 ;
+static const uint8_t P9N2__CTL_INT_REQ_INTERRUPT_06 = 6 ;
+static const uint8_t P9N2__CTL_INT_REQ_INTERRUPT_07 = 7 ;
+static const uint8_t P9N2__CTL_INT_REQ_INTERRUPT_08 = 8 ;
+static const uint8_t P9N2__CTL_INT_REQ_INTERRUPT_09 = 9 ;
+static const uint8_t P9N2__CTL_INT_REQ_INTERRUPT_10 = 10 ;
+static const uint8_t P9N2__CTL_INT_REQ_INTERRUPT_11 = 11 ;
+static const uint8_t P9N2__CTL_INT_REQ_INTERRUPT_12 = 12 ;
+static const uint8_t P9N2__CTL_INT_REQ_INTERRUPT_13 = 13 ;
+static const uint8_t P9N2__CTL_INT_REQ_INTERRUPT_14 = 14 ;
+static const uint8_t P9N2__CTL_INT_REQ_INTERRUPT_15 = 15 ;
+static const uint8_t P9N2__CTL_INT_REQ_INTERRUPT_16 = 16 ;
+static const uint8_t P9N2__CTL_INT_REQ_INTERRUPT_17 = 17 ;
+static const uint8_t P9N2__CTL_INT_REQ_INTERRUPT_18 = 18 ;
+static const uint8_t P9N2__CTL_INT_REQ_INTERRUPT_19 = 19 ;
+static const uint8_t P9N2__CTL_INT_REQ_INTERRUPT_20 = 20 ;
+static const uint8_t P9N2__CTL_INT_REQ_INTERRUPT_21 = 21 ;
+static const uint8_t P9N2__CTL_INT_REQ_INTERRUPT_22 = 22 ;
+static const uint8_t P9N2__CTL_INT_REQ_INTERRUPT_23 = 23 ;
+static const uint8_t P9N2__CTL_INT_REQ_INTERRUPT_24 = 24 ;
+static const uint8_t P9N2__CTL_INT_REQ_INTERRUPT_25 = 25 ;
+static const uint8_t P9N2__CTL_INT_REQ_INTERRUPT_26 = 26 ;
+static const uint8_t P9N2__CTL_INT_REQ_INTERRUPT_27 = 27 ;
+static const uint8_t P9N2__CTL_INT_REQ_INTERRUPT_28 = 28 ;
+static const uint8_t P9N2__CTL_INT_REQ_INTERRUPT_29 = 29 ;
+static const uint8_t P9N2__CTL_INT_REQ_INTERRUPT_30 = 30 ;
+static const uint8_t P9N2__CTL_INT_REQ_INTERRUPT_31 = 31 ;
+static const uint8_t P9N2__CTL_INT_REQ_INTERRUPT_32 = 32 ;
+static const uint8_t P9N2__CTL_INT_REQ_INTERRUPT_33 = 33 ;
+static const uint8_t P9N2__CTL_INT_REQ_INTERRUPT_34 = 34 ;
+
+static const uint8_t P9N2_PU_INT_TCTXT_CFG_CFG_BLOCK_GROUP_EN = 0 ;
+static const uint8_t P9N2_PU_INT_TCTXT_CFG_CFG_TARGET_EN = 1 ;
+static const uint8_t P9N2_PU_INT_TCTXT_CFG_CFG_LGS_EN = 2 ;
+static const uint8_t P9N2_PU_INT_TCTXT_CFG_CFG_STORE_ACK = 3 ;
+static const uint8_t P9N2_PU_INT_TCTXT_CFG_CFG_FUSE_CORE_EN = 4 ;
+static const uint8_t P9N2_PU_INT_TCTXT_CFG_RESERVED_5 = 5 ;
+static const uint8_t P9N2_PU_INT_TCTXT_CFG_CFG_SMT_MODE = 6 ;
+static const uint8_t P9N2_PU_INT_TCTXT_CFG_CFG_SMT_MODE_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_TCTXT_CFG_CFG_HARD_CHIPID_IN_BLOCK_EN = 8 ;
+static const uint8_t P9N2_PU_INT_TCTXT_CFG_CFG_CHIPID_OVERRIDE = 9 ;
+static const uint8_t P9N2_PU_INT_TCTXT_CFG_RESERVED_10_11 = 10 ;
+static const uint8_t P9N2_PU_INT_TCTXT_CFG_RESERVED_10_11_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_TCTXT_CFG_CFG_CHIPID = 12 ;
+static const uint8_t P9N2_PU_INT_TCTXT_CFG_CFG_CHIPID_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_TCTXT_CFG_CFG_EN = 16 ;
+static const uint8_t P9N2_PU_INT_TCTXT_CFG_CFG_MSGSND = 17 ;
+static const uint8_t P9N2_PU_INT_TCTXT_CFG_RESERVED_18_19 = 18 ;
+static const uint8_t P9N2_PU_INT_TCTXT_CFG_RESERVED_18_19_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_TCTXT_CFG_CFG_PULSE_WIDTH = 20 ;
+static const uint8_t P9N2_PU_INT_TCTXT_CFG_CFG_PULSE_WIDTH_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_TCTXT_CFG_RESERVED_24 = 24 ;
+static const uint8_t P9N2_PU_INT_TCTXT_CFG_CFG_COMPLEX_STORE_DIS = 25 ;
+static const uint8_t P9N2_PU_INT_TCTXT_CFG_CFG_COMPLEX_STORE_DIS_LEN = 3 ;
+static const uint8_t P9N2_PU_INT_TCTXT_CFG_RESERVED_28_29 = 28 ;
+static const uint8_t P9N2_PU_INT_TCTXT_CFG_RESERVED_28_29_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_TCTXT_CFG_CFG_LGS_AGE = 30 ;
+static const uint8_t P9N2_PU_INT_TCTXT_CFG_CFG_LGS_AGE_LEN = 2 ;
+
+static const uint8_t P9N2_PU_INT_TCTXT_EN0_CFG_THRD_C0_EN = 0 ;
+static const uint8_t P9N2_PU_INT_TCTXT_EN0_CFG_THRD_C0_EN_LEN = 8 ;
+static const uint8_t P9N2_PU_INT_TCTXT_EN0_CFG_THRD_C1_EN = 8 ;
+static const uint8_t P9N2_PU_INT_TCTXT_EN0_CFG_THRD_C1_EN_LEN = 8 ;
+static const uint8_t P9N2_PU_INT_TCTXT_EN0_CFG_THRD_C2_EN = 16 ;
+static const uint8_t P9N2_PU_INT_TCTXT_EN0_CFG_THRD_C2_EN_LEN = 8 ;
+static const uint8_t P9N2_PU_INT_TCTXT_EN0_CFG_THRD_C3_EN = 24 ;
+static const uint8_t P9N2_PU_INT_TCTXT_EN0_CFG_THRD_C3_EN_LEN = 8 ;
+static const uint8_t P9N2_PU_INT_TCTXT_EN0_CFG_THRD_C4_EN = 32 ;
+static const uint8_t P9N2_PU_INT_TCTXT_EN0_CFG_THRD_C4_EN_LEN = 8 ;
+static const uint8_t P9N2_PU_INT_TCTXT_EN0_CFG_THRD_C5_EN = 40 ;
+static const uint8_t P9N2_PU_INT_TCTXT_EN0_CFG_THRD_C5_EN_LEN = 8 ;
+static const uint8_t P9N2_PU_INT_TCTXT_EN0_CFG_THRD_C6_EN = 48 ;
+static const uint8_t P9N2_PU_INT_TCTXT_EN0_CFG_THRD_C6_EN_LEN = 8 ;
+static const uint8_t P9N2_PU_INT_TCTXT_EN0_CFG_THRD_C7_EN = 56 ;
+static const uint8_t P9N2_PU_INT_TCTXT_EN0_CFG_THRD_C7_EN_LEN = 8 ;
+
+static const uint8_t P9N2_PU_INT_TCTXT_EN1_CFG_THRD_C8_EN = 0 ;
+static const uint8_t P9N2_PU_INT_TCTXT_EN1_CFG_THRD_C8_EN_LEN = 8 ;
+static const uint8_t P9N2_PU_INT_TCTXT_EN1_CFG_THRD_C9_EN = 8 ;
+static const uint8_t P9N2_PU_INT_TCTXT_EN1_CFG_THRD_C9_EN_LEN = 8 ;
+static const uint8_t P9N2_PU_INT_TCTXT_EN1_CFG_THRD_C10_EN = 16 ;
+static const uint8_t P9N2_PU_INT_TCTXT_EN1_CFG_THRD_C10_EN_LEN = 8 ;
+static const uint8_t P9N2_PU_INT_TCTXT_EN1_CFG_THRD_C11_EN = 24 ;
+static const uint8_t P9N2_PU_INT_TCTXT_EN1_CFG_THRD_C11_EN_LEN = 8 ;
+
+static const uint8_t P9N2_PU_INT_TCTXT_INDIR0_INDIR_VLD = 0 ;
+static const uint8_t P9N2_PU_INT_TCTXT_INDIR0_INDIR_THRDID = 9 ;
+static const uint8_t P9N2_PU_INT_TCTXT_INDIR0_INDIR_THRDID_LEN = 7 ;
+
+static const uint8_t P9N2_PU_INT_TCTXT_INDIR1_INDIR_VLD = 0 ;
+static const uint8_t P9N2_PU_INT_TCTXT_INDIR1_INDIR_THRDID = 9 ;
+static const uint8_t P9N2_PU_INT_TCTXT_INDIR1_INDIR_THRDID_LEN = 7 ;
+
+static const uint8_t P9N2_PU_INT_TCTXT_INDIR2_INDIR_VLD = 0 ;
+static const uint8_t P9N2_PU_INT_TCTXT_INDIR2_INDIR_THRDID = 9 ;
+static const uint8_t P9N2_PU_INT_TCTXT_INDIR2_INDIR_THRDID_LEN = 7 ;
+
+static const uint8_t P9N2_PU_INT_TCTXT_INDIR3_INDIR_VLD = 0 ;
+static const uint8_t P9N2_PU_INT_TCTXT_INDIR3_INDIR_THRDID = 9 ;
+static const uint8_t P9N2_PU_INT_TCTXT_INDIR3_INDIR_THRDID_LEN = 7 ;
+
+static const uint8_t P9N2_PU_INT_TCTXT_TRACK_CFG_BLOCK_EN = 0 ;
+static const uint8_t P9N2_PU_INT_TCTXT_TRACK_CFG_BLOCK_RESET = 1 ;
+static const uint8_t P9N2_PU_INT_TCTXT_TRACK_RESERVED_2_3 = 2 ;
+static const uint8_t P9N2_PU_INT_TCTXT_TRACK_RESERVED_2_3_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_TCTXT_TRACK_CFG_BLOCK_FILTER_EN = 4 ;
+static const uint8_t P9N2_PU_INT_TCTXT_TRACK_CFG_BLOCK_FILTER_VPC_EN = 5 ;
+static const uint8_t P9N2_PU_INT_TCTXT_TRACK_RESERVED_6_9 = 6 ;
+static const uint8_t P9N2_PU_INT_TCTXT_TRACK_RESERVED_6_9_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_TCTXT_TRACK_CFG_BLOCK_RESET_DELAY = 10 ;
+static const uint8_t P9N2_PU_INT_TCTXT_TRACK_CFG_BLOCK_RESET_DELAY_LEN = 6 ;
+static const uint8_t P9N2_PU_INT_TCTXT_TRACK_CFG_BLOCK_EN_VEC = 48 ;
+static const uint8_t P9N2_PU_INT_TCTXT_TRACK_CFG_BLOCK_EN_VEC_LEN = 16 ;
+
+static const uint8_t P9N2_PU_INT_VC_AIB_TIMEOUT_DELAY = 58 ;
+static const uint8_t P9N2_PU_INT_VC_AIB_TIMEOUT_DELAY_LEN = 6 ;
+
+static const uint8_t P9N2_PU_INT_VC_AIB_TX_CMD_PRIORITY_PREVENT_MTP_AT_DEM_IN_PIPE = 32 ;
+static const uint8_t P9N2_PU_INT_VC_AIB_TX_CMD_PRIORITY_RESERVED_33_43 = 33 ;
+static const uint8_t P9N2_PU_INT_VC_AIB_TX_CMD_PRIORITY_RESERVED_33_43_LEN = 11 ;
+static const uint8_t P9N2_PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_REGS = 44 ;
+static const uint8_t P9N2_PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_REGS_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_IRQ = 46 ;
+static const uint8_t P9N2_PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_IRQ_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_IVC = 48 ;
+static const uint8_t P9N2_PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_IVC_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_VC_AIB_TX_CMD_PRIORITY_RESERVED_50_51 = 50 ;
+static const uint8_t P9N2_PU_INT_VC_AIB_TX_CMD_PRIORITY_RESERVED_50_51_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_SBC_EOI_RESP = 52 ;
+static const uint8_t P9N2_PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_SBC_EOI_RESP_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_SBC_DMA = 54 ;
+static const uint8_t P9N2_PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_SBC_DMA_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_TRIG_FWD = 56 ;
+static const uint8_t P9N2_PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_TRIG_FWD_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_EQC_EOI_EQP = 58 ;
+static const uint8_t P9N2_PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_EQC_EOI_EQP_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_LSS_CI_LOAD = 60 ;
+static const uint8_t P9N2_PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_LSS_CI_LOAD_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_EQD_DMA = 62 ;
+static const uint8_t P9N2_PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_EQD_DMA_LEN = 2 ;
+
+static const uint8_t P9N2_PU_INT_VC_AIB_TX_ORDERING_TAG_1_REGS = 24 ;
+static const uint8_t P9N2_PU_INT_VC_AIB_TX_ORDERING_TAG_1_REGS_LEN = 8 ;
+static const uint8_t P9N2_PU_INT_VC_AIB_TX_ORDERING_TAG_1_IRQ = 32 ;
+static const uint8_t P9N2_PU_INT_VC_AIB_TX_ORDERING_TAG_1_IRQ_LEN = 8 ;
+static const uint8_t P9N2_PU_INT_VC_AIB_TX_ORDERING_TAG_1_IVC = 40 ;
+static const uint8_t P9N2_PU_INT_VC_AIB_TX_ORDERING_TAG_1_IVC_LEN = 8 ;
+static const uint8_t P9N2_PU_INT_VC_AIB_TX_ORDERING_TAG_1_SBC_DMA = 48 ;
+static const uint8_t P9N2_PU_INT_VC_AIB_TX_ORDERING_TAG_1_SBC_DMA_LEN = 8 ;
+static const uint8_t P9N2_PU_INT_VC_AIB_TX_ORDERING_TAG_1_SBC_EOI = 56 ;
+static const uint8_t P9N2_PU_INT_VC_AIB_TX_ORDERING_TAG_1_SBC_EOI_LEN = 8 ;
+
+static const uint8_t P9N2_PU_INT_VC_AIB_TX_ORDERING_TAG_2_RELAXED_TRIG_FWD = 20 ;
+static const uint8_t P9N2_PU_INT_VC_AIB_TX_ORDERING_TAG_2_RELAXED_WR_EQP = 21 ;
+static const uint8_t P9N2_PU_INT_VC_AIB_TX_ORDERING_TAG_2_RELAXED_WR_DMA = 22 ;
+static const uint8_t P9N2_PU_INT_VC_AIB_TX_ORDERING_TAG_2_DISABLE_IDX_IN_AIBTAG = 23 ;
+static const uint8_t P9N2_PU_INT_VC_AIB_TX_ORDERING_TAG_2_EQC_EOI_ESBE = 24 ;
+static const uint8_t P9N2_PU_INT_VC_AIB_TX_ORDERING_TAG_2_EQC_EOI_ESBE_LEN = 8 ;
+static const uint8_t P9N2_PU_INT_VC_AIB_TX_ORDERING_TAG_2_EQC_CISTORE = 32 ;
+static const uint8_t P9N2_PU_INT_VC_AIB_TX_ORDERING_TAG_2_EQC_CISTORE_LEN = 8 ;
+static const uint8_t P9N2_PU_INT_VC_AIB_TX_ORDERING_TAG_2_EQC_EOI_EQP = 40 ;
+static const uint8_t P9N2_PU_INT_VC_AIB_TX_ORDERING_TAG_2_EQC_EOI_EQP_LEN = 8 ;
+static const uint8_t P9N2_PU_INT_VC_AIB_TX_ORDERING_TAG_2_EQC_CILOAD = 48 ;
+static const uint8_t P9N2_PU_INT_VC_AIB_TX_ORDERING_TAG_2_EQC_CILOAD_LEN = 8 ;
+static const uint8_t P9N2_PU_INT_VC_AIB_TX_ORDERING_TAG_2_EQC_DMA = 56 ;
+static const uint8_t P9N2_PU_INT_VC_AIB_TX_ORDERING_TAG_2_EQC_DMA_LEN = 8 ;
+
+static const uint8_t P9N2_PU_INT_VC_ATX_INIT_CREDIT_COUNT_CRD_REQUEST = 24 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_INIT_CREDIT_COUNT_RESERVED_25 = 25 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_INIT_CREDIT_COUNT_RSD_CRD_DMA_READ = 26 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_INIT_CREDIT_COUNT_RSD_CRD_DMA_READ_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_INIT_CREDIT_COUNT_RSD_CRD_AT_MACRO = 28 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_INIT_CREDIT_COUNT_RSD_CRD_AT_MACRO_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_INIT_CREDIT_COUNT_RSD_CRD_EQC_DOING_CI_LOAD = 30 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_INIT_CREDIT_COUNT_RSD_CRD_EQC_DOING_CI_LOAD_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_INIT_CREDIT_COUNT_RESERVED_32_33 = 32 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_INIT_CREDIT_COUNT_RESERVED_32_33_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_INIT_CREDIT_COUNT_READ_CRD_POOL = 34 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_INIT_CREDIT_COUNT_READ_CRD_POOL_LEN = 6 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_INIT_CREDIT_COUNT_RESERVED_40_47 = 40 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_INIT_CREDIT_COUNT_RESERVED_40_47_LEN = 8 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_INIT_CREDIT_COUNT_RSD_CRD_DMA_WRITE = 48 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_INIT_CREDIT_COUNT_RSD_CRD_DMA_WRITE_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_INIT_CREDIT_COUNT_RSD_CRD_EQ_POST = 50 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_INIT_CREDIT_COUNT_RSD_CRD_EQ_POST_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_INIT_CREDIT_COUNT_RSD_CRD_TRIG_FWD_1 = 52 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_INIT_CREDIT_COUNT_RSD_CRD_TRIG_FWD_1_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_INIT_CREDIT_COUNT_RSD_CRD_TRIG_FWD_2 = 54 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_INIT_CREDIT_COUNT_RSD_CRD_TRIG_FWD_2_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_INIT_CREDIT_COUNT_RESERVED_56_58 = 56 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_INIT_CREDIT_COUNT_RESERVED_56_58_LEN = 3 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_INIT_CREDIT_COUNT_WRITE_CRD_POOL = 59 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_INIT_CREDIT_COUNT_WRITE_CRD_POOL_LEN = 5 ;
+
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R0 = 0 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R0_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R1R = 4 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R1R_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R1W = 8 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R1W_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R2 = 12 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R2_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R3 = 16 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R3_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R4 = 20 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R4_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R5R = 24 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R5R_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R5W = 28 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R5W_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R6 = 32 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R6_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R7RSP = 36 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R7RSP_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R7INT = 40 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R7INT_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R7EQP = 44 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R7EQP_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R8 = 48 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R8_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R9 = 52 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R9_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R10R = 56 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R10R_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R10W = 60 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R10W_LEN = 4 ;
+
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R0 = 0 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R0_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R1R = 4 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R1R_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R1W = 8 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R1W_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R2 = 12 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R2_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R3 = 16 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R3_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R4 = 20 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R4_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R5R = 24 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R5R_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R5W = 28 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R5W_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R6 = 32 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R6_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R7RSP = 36 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R7RSP_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R7INT = 40 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R7INT_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R7EQP = 44 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R7EQP_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R8 = 48 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R8_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R9 = 52 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R9_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R10R = 56 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R10R_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R10W = 60 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R10W_LEN = 4 ;
+
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R0 = 0 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R0_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R1R = 4 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R1R_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R1W = 8 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R1W_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R2 = 12 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R2_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R3 = 16 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R3_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R4 = 20 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R4_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R5R = 24 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R5R_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R5W = 28 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R5W_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R6 = 32 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R6_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R7RSP = 36 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R7RSP_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R7INT = 40 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R7INT_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R7EQP = 44 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R7EQP_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R8 = 48 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R8_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R9 = 52 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R9_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R10R = 56 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R10R_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R10W = 60 ;
+static const uint8_t P9N2_PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R10W_LEN = 4 ;
+
+static const uint8_t P9N2_PU_INT_VC_AT_MACRO_KILL_VALID = 0 ;
+static const uint8_t P9N2_PU_INT_VC_AT_MACRO_KILL_VST_TYPE = 14 ;
+static const uint8_t P9N2_PU_INT_VC_AT_MACRO_KILL_VST_TYPE_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_VC_AT_MACRO_KILL_BLOCKID = 27 ;
+static const uint8_t P9N2_PU_INT_VC_AT_MACRO_KILL_BLOCKID_LEN = 5 ;
+static const uint8_t P9N2_PU_INT_VC_AT_MACRO_KILL_OFFSET = 48 ;
+static const uint8_t P9N2_PU_INT_VC_AT_MACRO_KILL_OFFSET_LEN = 13 ;
+
+static const uint8_t P9N2_PU_INT_VC_AT_MACRO_KILL_MASK_BLOCKID = 27 ;
+static const uint8_t P9N2_PU_INT_VC_AT_MACRO_KILL_MASK_BLOCKID_LEN = 5 ;
+static const uint8_t P9N2_PU_INT_VC_AT_MACRO_KILL_MASK_OFFSET = 48 ;
+static const uint8_t P9N2_PU_INT_VC_AT_MACRO_KILL_MASK_OFFSET_LEN = 13 ;
+
+static const uint8_t P9N2_PU_INT_VC_EQC_ADDITIONAL_PERF_1_P0_IS_IDLE = 0 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_ADDITIONAL_PERF_1_P1_IS_IDLE = 1 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_ADDITIONAL_PERF_1_MAX_PTAG_IN_USE = 8 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_ADDITIONAL_PERF_1_MAX_PTAG_IN_USE_LEN = 8 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_ADDITIONAL_PERF_1_MAX_OUTSTANDING_EOI = 16 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_ADDITIONAL_PERF_1_MAX_OUTSTANDING_EOI_LEN = 8 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_ADDITIONAL_PERF_1_MAX_UNLOCK_IN_FIFO = 24 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_ADDITIONAL_PERF_1_MAX_UNLOCK_IN_FIFO_LEN = 8 ;
+
+static const uint8_t P9N2_PU_INT_VC_EQC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_EQD_FETCH = 0 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_EQD_FETCH_LEN = 8 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_EQP = 8 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_EQP_LEN = 8 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_ADDITIONAL_PERF_2_MAX_OUTSTANDING = 16 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_LEN = 8 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_CI_LOAD = 24 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_CI_LOAD_LEN = 8 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_CI_STORE = 32 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_CI_STORE_LEN = 8 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_EQD_WRITE = 40 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_EQD_WRITE_LEN = 8 ;
+
+static const uint8_t P9N2_PU_INT_VC_EQC_CACHE_EN_ENABLE = 0 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_CACHE_EN_ENABLE_LEN = 16 ;
+
+static const uint8_t P9N2_PU_INT_VC_EQC_CACHE_WATCH_DATA0_DATA = 0 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_CACHE_WATCH_DATA0_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_PU_INT_VC_EQC_CACHE_WATCH_DATA1_DATA = 0 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_CACHE_WATCH_DATA1_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_PU_INT_VC_EQC_CACHE_WATCH_DATA2_DATA = 0 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_CACHE_WATCH_DATA2_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_PU_INT_VC_EQC_CACHE_WATCH_DATA3_DATA = 0 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_CACHE_WATCH_DATA3_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_PU_INT_VC_EQC_CACHE_WATCH_SPEC_CONFLICT = 0 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_CACHE_WATCH_SPEC_RESERVED_1_7 = 1 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_CACHE_WATCH_SPEC_RESERVED_1_7_LEN = 7 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_CACHE_WATCH_SPEC_FULL = 8 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_CACHE_WATCH_SPEC_RESERVED_9_27 = 9 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_CACHE_WATCH_SPEC_RESERVED_9_27_LEN = 19 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_CACHE_WATCH_SPEC_BLOCKID = 28 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_CACHE_WATCH_SPEC_BLOCKID_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_CACHE_WATCH_SPEC_RESERVED_32_39 = 32 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_CACHE_WATCH_SPEC_RESERVED_32_39_LEN = 8 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_CACHE_WATCH_SPEC_OFFSET = 40 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_CACHE_WATCH_SPEC_OFFSET_LEN = 24 ;
+
+static const uint8_t P9N2_PU_INT_VC_EQC_CONFIG_PAGE_OFFSET_CFG = 16 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_CONFIG_PAGE_OFFSET_CFG_LEN = 16 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_CONFIG_SYNC_DONE = 32 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_CONFIG_SYNC_DONE_LEN = 5 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_CONFIG_RESERVED_37 = 37 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_CONFIG_ENABLE_EQP_ADD_INTERLEAVE = 38 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_CONFIG_ENABLE_END_S_BIT = 39 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_CONFIG_ENABLE_END_U_BIT = 40 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_CONFIG_ENABLE_END_C_BIT = 41 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_CONFIG_ENABLE_MORE_QSZ = 42 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_CONFIG_SKIP_ESCALATE = 43 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_CONFIG_RESERVED_44_45 = 44 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_CONFIG_RESERVED_44_45_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_CONFIG_MAX_PTAG_IN_USE = 46 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_CONFIG_MAX_PTAG_IN_USE_LEN = 6 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_CONFIG_BG_SCAN_RATE = 52 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_CONFIG_BG_SCAN_RATE_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_CONFIG_RESERVED_56_57 = 56 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_CONFIG_RESERVED_56_57_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_CONFIG_FORCE_INVALIDATE = 58 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_CONFIG_MAX_ENTRIES_IN_MODIFIED = 59 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_CONFIG_MAX_ENTRIES_IN_MODIFIED_LEN = 5 ;
+
+static const uint8_t P9N2_PU_INT_VC_EQC_DEBUG_RESERVED_0_32 = 0 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_DEBUG_RESERVED_0_32_LEN = 33 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_DEBUG_DIS_ARX_ECC_CORRECTION = 33 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_DEBUG_DIS_TAG_ECC_CORRECTION = 34 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_DEBUG_DIS_TAG_ECC_CORRECTION_LEN = 8 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_DEBUG_DIS_STATE_ECC_CORRECTION = 42 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_DEBUG_DIS_STATE_ECC_CORRECTION_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_DEBUG_DIS_CTRLBUF_ECC_CORRECTION = 44 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_DEBUG_DIS_DATA_ECC_CORRECTION = 45 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_DEBUG_DIS_DATA_ECC_CORRECTION_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_DEBUG_FORCE_SINGLE_BIT_ECC_ERR = 49 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_DEBUG_FORCE_DOUBLE_BIT_ECC_ERR = 50 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_DEBUG_ECC_ERR_INJ_ARRAY_SEL = 51 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_DEBUG_ECC_ERR_INJ_ARRAY_SEL_LEN = 5 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_DEBUG_TRACE_ENABLE = 56 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_DEBUG_RESERVED_57_58 = 57 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_DEBUG_RESERVED_57_58_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_DEBUG_RESERVED_59 = 59 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_DEBUG_USE_WATCH_TO_READ_CTRL_ARY = 60 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_DEBUG_CACHE_CTRL_ARY_SELECT = 61 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_DEBUG_CACHE_CTRL_ARY_SELECT_LEN = 3 ;
+
+static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_EQ_TRIGGER_FROM_IPI = 0 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_EQ_TRIGGER_FROM_IPI_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_EQ_TRIGGER_FROM_HWD = 4 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_EQ_TRIGGER_FROM_HWD_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_EQ_TRIGGER_FROM_1ESC = 8 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_EQ_TRIGGER_FROM_1ESC_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_EQ_TRIGGER_FROM_2ESC = 12 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_EQ_TRIGGER_FROM_2ESC_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_EQ_TRIGGER_FROM_REDIS = 16 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_EQ_TRIGGER_FROM_REDIS_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_NON_SPEC_EOI = 20 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_NON_SPEC_EOI_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_LOCAL_ESCALATE = 24 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_LOCAL_ESCALATE_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_EQ_TRIG_CACHE_HIT = 28 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_EQ_TRIG_CACHE_HIT_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_EOI_CACHE_HIT = 32 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_EOI_CACHE_HIT_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_LOCAL_ESC_CACHE_HIT = 36 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_LOCAL_ESC_CACHE_HIT_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_LRU = 40 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_LRU_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_FIRST_USABLE = 44 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_FIRST_USABLE_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_RETRY = 48 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_RETRY_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_TOO_MANY_ENTRIES = 52 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_TOO_MANY_ENTRIES_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_1_RESERVED_56_63 = 56 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_1_RESERVED_56_63_LEN = 8 ;
+
+static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_EQD_FETCH = 0 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_EQD_FETCH_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_EQP = 4 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_EQP_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_RESUME = 8 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_RESUME_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_EBB = 12 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_EBB_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_VP = 16 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_VP_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_LS = 20 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_LS_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_BROADCAST_BL = 24 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_BROADCAST_BL_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_EQ_FWD = 28 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_EQ_FWD_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_ESCALATE = 32 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_ESCALATE_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_LOCAL_VPC_UPD = 36 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_LOCAL_VPC_UPD_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_REMOTE_VPC_UPD = 40 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_REMOTE_VPC_UPD_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_LOCAL_SBC_UPD = 44 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_LOCAL_SBC_UPD_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_REMOTE_SBC_UPD = 48 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_REMOTE_SBC_UPD_LEN = 4 ;
+
+static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_EQD_FETCH_REPLAY = 0 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_EQD_FETCH_REPLAY_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_EQP_REPLAY = 4 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_EQP_REPLAY_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_REPLAY = 8 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_REPLAY_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_CI_STORE_REPLAY = 12 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_CI_STORE_REPLAY_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_LOCAL_ESC_REPLAY = 16 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_LOCAL_ESC_REPLAY_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_REMOTE_CI_LOAD_REPLAY = 20 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_REMOTE_CI_LOAD_REPLAY_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_LOCAL_VPC_REPLAY = 24 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_LOCAL_VPC_REPLAY_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_LOCAL_SBC_REPLAY = 28 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_LOCAL_SBC_REPLAY_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_EOI_RESP_REPLAY = 32 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_EOI_RESP_REPLAY_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_NEW_CMD_STALLED = 36 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_NEW_CMD_STALLED_LEN = 4 ;
+
+static const uint8_t P9N2_PU_INT_VC_EQC_SCRUB_MASK_BLOCKID = 28 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_SCRUB_MASK_BLOCKID_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_SCRUB_MASK_RESERVED_32_39 = 32 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_SCRUB_MASK_RESERVED_32_39_LEN = 8 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_SCRUB_MASK_OFFSET = 40 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_SCRUB_MASK_OFFSET_LEN = 24 ;
+
+static const uint8_t P9N2_PU_INT_VC_EQC_SCRUB_TRIG_VALID = 0 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_SCRUB_TRIG_WANT_CACHE_DISABLE = 1 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_SCRUB_TRIG_WANT_INVALIDATE = 2 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_SCRUB_TRIG_BLOCKID = 28 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_SCRUB_TRIG_BLOCKID_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_SCRUB_TRIG_RESERVED_32_39 = 32 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_SCRUB_TRIG_RESERVED_32_39_LEN = 8 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_SCRUB_TRIG_OFFSET = 40 ;
+static const uint8_t P9N2_PU_INT_VC_EQC_SCRUB_TRIG_OFFSET_LEN = 24 ;
+
+static const uint8_t P9N2_PU_INT_VC_EQD_BLOCK_MODE_MODE = 0 ;
+static const uint8_t P9N2_PU_INT_VC_EQD_BLOCK_MODE_MODE_LEN = 32 ;
+
+static const uint8_t P9N2_PU_INT_VC_ERR_CFG_G0R0_ERROR_CONFIG = 0 ;
+static const uint8_t P9N2_PU_INT_VC_ERR_CFG_G0R0_ERROR_CONFIG_LEN = 56 ;
+
+static const uint8_t P9N2_PU_INT_VC_ERR_CFG_G0R1_ERROR_CONFIG = 0 ;
+static const uint8_t P9N2_PU_INT_VC_ERR_CFG_G0R1_ERROR_CONFIG_LEN = 56 ;
+
+static const uint8_t P9N2_PU_INT_VC_ERR_CFG_G1R0_ERROR_CONFIG = 0 ;
+static const uint8_t P9N2_PU_INT_VC_ERR_CFG_G1R0_ERROR_CONFIG_LEN = 44 ;
+
+static const uint8_t P9N2_PU_INT_VC_ERR_CFG_G1R1_ERROR_CONFIG = 0 ;
+static const uint8_t P9N2_PU_INT_VC_ERR_CFG_G1R1_ERROR_CONFIG_LEN = 44 ;
+
+static const uint8_t P9N2_PU_INT_VC_FATAL_ERR_G0_ERROR = 0 ;
+static const uint8_t P9N2_PU_INT_VC_FATAL_ERR_G0_ERROR_LEN = 55 ;
+
+static const uint8_t P9N2_PU_INT_VC_FATAL_ERR_G1_ERROR = 0 ;
+static const uint8_t P9N2_PU_INT_VC_FATAL_ERR_G1_ERROR_LEN = 43 ;
+
+static const uint8_t P9N2_PU_INT_VC_GLOBAL_CONFIG_INDIRECT_MODE = 32 ;
+static const uint8_t P9N2_PU_INT_VC_GLOBAL_CONFIG_EQD_4B_WRITE_MODE = 33 ;
+static const uint8_t P9N2_PU_INT_VC_GLOBAL_CONFIG_RESERVED_34_63 = 34 ;
+static const uint8_t P9N2_PU_INT_VC_GLOBAL_CONFIG_RESERVED_34_63_LEN = 30 ;
+
+static const uint8_t P9N2_PU_INT_VC_INFO_ERR_G0_ERROR = 0 ;
+static const uint8_t P9N2_PU_INT_VC_INFO_ERR_G0_ERROR_LEN = 55 ;
+
+static const uint8_t P9N2_PU_INT_VC_INFO_ERR_G1_ERROR = 0 ;
+static const uint8_t P9N2_PU_INT_VC_INFO_ERR_G1_ERROR_LEN = 43 ;
+
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_0_RESERVED_20 = 0 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_0_RESERVED_20_LEN = 21 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_0_PREFETCH_DISTANCE = 21 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_0_PREFETCH_DISTANCE_LEN = 6 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_0_MAX_CRD_TO_CQ = 27 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_0_MAX_CRD_TO_CQ_LEN = 5 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_0_RESERVED_32_34 = 32 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_0_RESERVED_32_34_LEN = 3 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_0_MAX_CRD_TO_PC = 35 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_0_MAX_CRD_TO_PC_LEN = 5 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_0_RESERVED_40_41 = 40 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_0_RESERVED_40_41_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_0_PREFETCH_DISABLE = 42 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_0_QUEUE_DISABLE = 43 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_0_IVC_INTF_DISABLE = 44 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_0_ENABLE_MEMORY_BACKING = 45 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_0_MEM_SIZE = 46 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_0_MEM_SIZE_LEN = 6 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_0_RESERVED_52 = 52 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_0_NB_WRITE_SLOT = 53 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_0_NB_WRITE_SLOT_LEN = 3 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_0_RESERVED_56 = 56 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_0_NB_CLEAN_SLOT = 57 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_0_NB_CLEAN_SLOT_LEN = 3 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_0_FULL_WRITEBACK_ENABLE = 60 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_0_QUEUE_NOT_EMPTY = 61 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_0_CREDIT_UPDATE_PENDING = 62 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_0_FIFO_FULL = 63 ;
+
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_1_RESERVED_0_20 = 0 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_1_RESERVED_0_20_LEN = 21 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_1_PREFETCH_DISTANCE = 21 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_1_PREFETCH_DISTANCE_LEN = 6 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_1_MAX_CRD_TO_CQ = 27 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_1_MAX_CRD_TO_CQ_LEN = 5 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_1_RESERVED_32_34 = 32 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_1_RESERVED_32_34_LEN = 3 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_1_MAX_CRD_TO_PC = 35 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_1_MAX_CRD_TO_PC_LEN = 5 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_1_RESERVED_40_41 = 40 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_1_RESERVED_40_41_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_1_PREFETCH_DISABLE = 42 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_1_QUEUE_DISABLE = 43 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_1_IVC_INTF_DISABLE = 44 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_1_ENABLE_MEMORY_BACKING = 45 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_1_MEM_SIZE = 46 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_1_MEM_SIZE_LEN = 6 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_1_RESERVED_52 = 52 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_1_NB_WRITE_SLOT = 53 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_1_NB_WRITE_SLOT_LEN = 3 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_1_RESERVED_56 = 56 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_1_NB_CLEAN_SLOT = 57 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_1_NB_CLEAN_SLOT_LEN = 3 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_1_FULL_WRITEBACK_ENABLE = 60 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_1_QUEUE_NOT_EMPTY = 61 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_1_CREDIT_UPDATE_PENDING = 62 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_1_FIFO_FULL = 63 ;
+
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_2_RESERVED_0_20 = 0 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_2_RESERVED_0_20_LEN = 21 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_2_PREFETCH_DISTANCE = 21 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_2_PREFETCH_DISTANCE_LEN = 6 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_2_MAX_CRD_TO_CQ = 27 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_2_MAX_CRD_TO_CQ_LEN = 5 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_2_RESERVED_32_34 = 32 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_2_RESERVED_32_34_LEN = 3 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_2_MAX_CRD_TO_PC = 35 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_2_MAX_CRD_TO_PC_LEN = 5 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_2_RESERVED_40_41 = 40 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_2_RESERVED_40_41_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_2_PREFETCH_DISABLE = 42 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_2_QUEUE_DISABLE = 43 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_2_IVC_INTF_DISABLE = 44 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_2_ENABLE_MEMORY_BACKING = 45 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_2_MEM_SIZE = 46 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_2_MEM_SIZE_LEN = 6 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_2_RESERVED_52 = 52 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_2_NB_WRITE_SLOT = 53 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_2_NB_WRITE_SLOT_LEN = 3 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_2_RESERVED_56 = 56 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_2_NB_CLEAN_SLOT = 57 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_2_NB_CLEAN_SLOT_LEN = 3 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_2_FULL_WRITEBACK_ENABLE = 60 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_2_QUEUE_NOT_EMPTY = 61 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_2_CREDIT_UPDATE_PENDING = 62 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_2_FIFO_FULL = 63 ;
+
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_3_RESERVED_0_20 = 0 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_3_RESERVED_0_20_LEN = 21 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_3_PREFETCH_DISTANCE = 21 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_3_PREFETCH_DISTANCE_LEN = 6 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_3_MAX_CRD_TO_CQ = 27 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_3_MAX_CRD_TO_CQ_LEN = 5 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_3_RESERVED_32_34 = 32 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_3_RESERVED_32_34_LEN = 3 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_3_MAX_CRD_TO_PC = 35 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_3_MAX_CRD_TO_PC_LEN = 5 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_3_RESERVED_40_41 = 40 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_3_RESERVED_40_41_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_3_PREFETCH_DISABLE = 42 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_3_QUEUE_DISABLE = 43 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_3_IVC_INTF_DISABLE = 44 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_3_ENABLE_MEMORY_BACKING = 45 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_3_MEM_SIZE = 46 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_3_MEM_SIZE_LEN = 6 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_3_RESERVED_52 = 52 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_3_NB_WRITE_SLOT = 53 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_3_NB_WRITE_SLOT_LEN = 3 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_3_RESERVED_56 = 56 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_3_NB_CLEAN_SLOT = 57 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_3_NB_CLEAN_SLOT_LEN = 3 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_3_FULL_WRITEBACK_ENABLE = 60 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_3_QUEUE_NOT_EMPTY = 61 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_3_CREDIT_UPDATE_PENDING = 62 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_3_FIFO_FULL = 63 ;
+
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_4_RESERVED_0_20 = 0 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_4_RESERVED_0_20_LEN = 21 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_4_PREFETCH_DISTANCE = 21 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_4_PREFETCH_DISTANCE_LEN = 6 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_4_MAX_CRD_TO_CQ = 27 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_4_MAX_CRD_TO_CQ_LEN = 5 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_4_RESERVED_32_34 = 32 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_4_RESERVED_32_34_LEN = 3 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_4_MAX_CRD_TO_PC = 35 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_4_MAX_CRD_TO_PC_LEN = 5 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_4_RESERVED_40_41 = 40 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_4_RESERVED_40_41_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_4_PREFETCH_DISABLE = 42 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_4_QUEUE_DISABLE = 43 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_4_IVC_INTF_DISABLE = 44 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_4_ENABLE_MEMORY_BACKING = 45 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_4_MEM_SIZE = 46 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_4_MEM_SIZE_LEN = 6 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_4_RESERVED_52 = 52 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_4_NB_WRITE_SLOT = 53 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_4_NB_WRITE_SLOT_LEN = 3 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_4_RESERVED_56 = 56 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_4_NB_CLEAN_SLOT = 57 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_4_NB_CLEAN_SLOT_LEN = 3 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_4_FULL_WRITEBACK_ENABLE = 60 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_4_QUEUE_NOT_EMPTY = 61 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_4_CREDIT_UPDATE_PENDING = 62 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_4_FIFO_FULL = 63 ;
+
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_5_RESERVED_0_20 = 0 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_5_RESERVED_0_20_LEN = 21 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_5_PREFETCH_DISTANCE = 21 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_5_PREFETCH_DISTANCE_LEN = 6 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_5_MAX_CRD_TO_CQ = 27 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_5_MAX_CRD_TO_CQ_LEN = 5 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_5_RESERVED_32_34 = 32 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_5_RESERVED_32_34_LEN = 3 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_5_MAX_CRD_TO_PC = 35 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_5_MAX_CRD_TO_PC_LEN = 5 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_5_RESERVED_40_41 = 40 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_5_RESERVED_40_41_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_5_PREFETCH_DISABLE = 42 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_5_QUEUE_DISABLE = 43 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_5_IVC_INTF_DISABLE = 44 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_5_ENABLE_MEMORY_BACKING = 45 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_5_MEM_SIZE = 46 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_5_MEM_SIZE_LEN = 6 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_5_RESERVED_52 = 52 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_5_NB_WRITE_SLOT = 53 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_5_NB_WRITE_SLOT_LEN = 3 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_5_RESERVED_56 = 56 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_5_NB_CLEAN_SLOT = 57 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_5_NB_CLEAN_SLOT_LEN = 3 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_5_FULL_WRITEBACK_ENABLE = 60 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_5_QUEUE_NOT_EMPTY = 61 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_5_CREDIT_UPDATE_PENDING = 62 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_CONFIG_5_FIFO_FULL = 63 ;
+
+static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_0_CNT_TRIG_FROM_AIB = 0 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_0_CNT_TRIG_FROM_AIB_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_0_CNT_TRIG_DROPPED = 4 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_0_CNT_TRIG_DROPPED_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_0_CNT_TRIG_FWD_TO_EQC = 8 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_0_CNT_TRIG_FWD_TO_EQC_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_0_CNT_DMA_WR = 12 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_0_CNT_DMA_WR_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_0_CNT_DMA_RD = 16 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_0_CNT_DMA_RD_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_0_CNT_FIFO_FULL = 20 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_0_CNT_FIFO_FULL_LEN = 4 ;
+
+static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_1_CNT_TRIG_FROM_AIB = 0 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_1_CNT_TRIG_FROM_AIB_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_1_CNT_TRIG_DROPPED = 4 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_1_CNT_TRIG_DROPPED_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_1_CNT_TRIG_FWD_TO_EQC = 8 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_1_CNT_TRIG_FWD_TO_EQC_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_1_CNT_DMA_WR = 12 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_1_CNT_DMA_WR_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_1_CNT_DMA_RD = 16 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_1_CNT_DMA_RD_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_1_CNT_FIFO_FULL = 20 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_1_CNT_FIFO_FULL_LEN = 4 ;
+
+static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_2_CNT_TRIG_FROM_AIB = 0 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_2_CNT_TRIG_FROM_AIB_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_2_CNT_TRIG_DROPPED = 4 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_2_CNT_TRIG_DROPPED_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_2_CNT_TRIG_FWD_TO_EQC = 8 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_2_CNT_TRIG_FWD_TO_EQC_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_2_CNT_DMA_WR = 12 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_2_CNT_DMA_WR_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_2_CNT_DMA_RD = 16 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_2_CNT_DMA_RD_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_2_CNT_FIFO_FULL = 20 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_2_CNT_FIFO_FULL_LEN = 4 ;
+
+static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_3_CNT_TRIG_FROM_AIB = 0 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_3_CNT_TRIG_FROM_AIB_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_3_CNT_TRIG_DROPPED = 4 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_3_CNT_TRIG_DROPPED_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_3_CNT_TRIG_FWD_TO_EQC = 8 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_3_CNT_TRIG_FWD_TO_EQC_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_3_CNT_DMA_WR = 12 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_3_CNT_DMA_WR_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_3_CNT_DMA_RD = 16 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_3_CNT_DMA_RD_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_3_CNT_FIFO_FULL = 20 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_3_CNT_FIFO_FULL_LEN = 4 ;
+
+static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_4_CNT_TRIG_FROM_AIB = 0 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_4_CNT_TRIG_FROM_AIB_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_4_CNT_TRIG_DROPPED = 4 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_4_CNT_TRIG_DROPPED_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_4_CNT_TRIG_FWD_TO_EQC = 8 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_4_CNT_TRIG_FWD_TO_EQC_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_4_CNT_DMA_WR = 12 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_4_CNT_DMA_WR_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_4_CNT_DMA_RD = 16 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_4_CNT_DMA_RD_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_4_CNT_FIFO_FULL = 20 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_4_CNT_FIFO_FULL_LEN = 4 ;
+
+static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_5_CNT_TRIG_FROM_AIB = 0 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_5_CNT_TRIG_FROM_AIB_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_5_CNT_TRIG_DROPPED = 4 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_5_CNT_TRIG_DROPPED_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_5_CNT_TRIG_FWD_TO_EQC = 8 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_5_CNT_TRIG_FWD_TO_EQC_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_5_CNT_DMA_WR = 12 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_5_CNT_DMA_WR_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_5_CNT_DMA_RD = 16 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_5_CNT_DMA_RD_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_5_CNT_FIFO_FULL = 20 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_PERF_EVENT_SEL_5_CNT_FIFO_FULL_LEN = 4 ;
+
+static const uint8_t P9N2_PU_INT_VC_IRQ_TO_EQC_CREDITS_IPI_PRIORITY = 0 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_TO_EQC_CREDITS_IPI_PRIORITY_LEN = 3 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_TO_EQC_CREDITS_IPI_RSD = 3 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_TO_EQC_CREDITS_IPI_RSD_LEN = 5 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_TO_EQC_CREDITS_HWD_PRIORITY = 8 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_TO_EQC_CREDITS_HWD_PRIORITY_LEN = 3 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_TO_EQC_CREDITS_HWD_RSD = 11 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_TO_EQC_CREDITS_HWD_RSD_LEN = 5 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_TO_EQC_CREDITS_ESC1_PRIORITY = 16 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_TO_EQC_CREDITS_ESC1_PRIORITY_LEN = 3 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_TO_EQC_CREDITS_ESC1_RSD = 19 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_TO_EQC_CREDITS_ESC1_RSD_LEN = 5 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_TO_EQC_CREDITS_ESC2_PRIORITY = 24 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_TO_EQC_CREDITS_ESC2_PRIORITY_LEN = 3 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_TO_EQC_CREDITS_ESC2_RSD = 27 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_TO_EQC_CREDITS_ESC2_RSD_LEN = 5 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_TO_EQC_CREDITS_REDIS_PRIORITY = 32 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_TO_EQC_CREDITS_REDIS_PRIORITY_LEN = 3 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_TO_EQC_CREDITS_REDIS_RSD = 35 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_TO_EQC_CREDITS_REDIS_RSD_LEN = 5 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_TO_EQC_CREDITS_RESERVED_40_42 = 40 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_TO_EQC_CREDITS_RESERVED_40_42_LEN = 3 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_TO_EQC_CREDITS_POOL = 43 ;
+static const uint8_t P9N2_PU_INT_VC_IRQ_TO_EQC_CREDITS_POOL_LEN = 5 ;
+
+static const uint8_t P9N2_PU_INT_VC_IVC_ADDITIONAL_PERF_P0_IS_IDLE = 0 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_ADDITIONAL_PERF_P1_IS_IDLE = 1 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_ADDITIONAL_PERF_MAX_PTAG_IN_USE = 8 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_ADDITIONAL_PERF_MAX_PTAG_IN_USE_LEN = 8 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_ADDITIONAL_PERF_MAX_UNLOCK_IN_FIFO = 24 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_ADDITIONAL_PERF_MAX_UNLOCK_IN_FIFO_LEN = 8 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_ADDITIONAL_PERF_MAX_OUTSTANDING_IVE_FETCH = 48 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_ADDITIONAL_PERF_MAX_OUTSTANDING_IVE_FETCH_LEN = 8 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_ADDITIONAL_PERF_MAX_OUTSTANDING_SBC_LOOKUP = 56 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_ADDITIONAL_PERF_MAX_OUTSTANDING_SBC_LOOKUP_LEN = 8 ;
+
+static const uint8_t P9N2_PU_INT_VC_IVC_CACHE_EN_ENABLE = 0 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_CACHE_EN_ENABLE_LEN = 16 ;
+
+static const uint8_t P9N2_PU_INT_VC_IVC_CACHE_WATCH_ADDR_SET_INDEX = 54 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_CACHE_WATCH_ADDR_SET_INDEX_LEN = 6 ;
+
+static const uint8_t P9N2_PU_INT_VC_IVC_CACHE_WATCH_DATA_DATA = 0 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_CACHE_WATCH_DATA_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_PU_INT_VC_IVC_DEBUG_RESERVED_32 = 32 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_DEBUG_MAX_PTAG_IN_USE = 33 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_DEBUG_MAX_PTAG_IN_USE_LEN = 5 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_DEBUG_DIS_TAG_ECC_CORRECTION = 38 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_DEBUG_DIS_TAG_ECC_CORRECTION_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_DEBUG_DIS_STATE_ECC_CORRECTION = 42 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_DEBUG_RESERVED_43_44 = 43 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_DEBUG_RESERVED_43_44_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_DEBUG_DIS_DATA_ECC_CORRECTION = 45 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_DEBUG_DIS_DATA_ECC_CORRECTION_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_DEBUG_RESERVED_47_48 = 47 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_DEBUG_RESERVED_47_48_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_DEBUG_FORCE_SINGLE_BIT_ECC_ERR = 49 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_DEBUG_FORCE_DOUBLE_BIT_ECC_ERR = 50 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_DEBUG_ECC_ERR_INJ_ARRAY_SEL = 51 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_DEBUG_ECC_ERR_INJ_ARRAY_SEL_LEN = 5 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_DEBUG_TRACE_ENABLE = 56 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_DEBUG_RESERVED_57_58 = 57 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_DEBUG_RESERVED_57_58_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_DEBUG_FAST_SB_LOOKUP_DISABLE = 59 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_DEBUG_CACHE_CTRL_ARY_SELECT = 60 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_DEBUG_CACHE_CTRL_ARY_SELECT_LEN = 4 ;
+
+static const uint8_t P9N2_PU_INT_VC_IVC_HASH_1_RESERVED_0 = 0 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_HASH_1_HWD_0 = 1 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_HASH_1_HWD_0_LEN = 7 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_HASH_1_RESERVED_8 = 8 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_HASH_1_HWD = 9 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_HASH_1_HWD_LEN = 7 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_HASH_1_RESERVED_16 = 16 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_HASH_1_HWD_2 = 17 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_HASH_1_HWD_2_LEN = 7 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_HASH_1_RESERVED_24 = 24 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_HASH_1_HWD_3 = 25 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_HASH_1_HWD_3_LEN = 7 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_HASH_1_RESERVED_32 = 32 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_HASH_1_HWD_4 = 33 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_HASH_1_HWD_4_LEN = 7 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_HASH_1_RESERVED_40 = 40 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_HASH_1_HWD_5 = 41 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_HASH_1_HWD_5_LEN = 7 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_HASH_1_RESERVED_48 = 48 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_HASH_1_HWD_6 = 49 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_HASH_1_HWD_6_LEN = 7 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_HASH_1_RESERVED_56 = 56 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_HASH_1_HWD_7 = 57 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_HASH_1_HWD_7_LEN = 7 ;
+
+static const uint8_t P9N2_PU_INT_VC_IVC_HASH_2_RESERVED_0 = 0 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_HASH_2_HWD_8 = 1 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_HASH_2_HWD_8_LEN = 7 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_HASH_2_RESERVED_8 = 8 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_HASH_2_HWD_9 = 9 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_HASH_2_HWD_9_LEN = 7 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_HASH_2_RESERVED_16 = 16 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_HASH_2_HWD_10 = 17 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_HASH_2_HWD_10_LEN = 7 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_HASH_2_RESERVED_24 = 24 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_HASH_2_HWD_11 = 25 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_HASH_2_HWD_11_LEN = 7 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_HASH_2_RESERVED_32 = 32 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_HASH_2_HWD_12 = 33 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_HASH_2_HWD_12_LEN = 7 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_HASH_2_RESERVED_40 = 40 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_HASH_2_HWD_13 = 41 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_HASH_2_HWD_13_LEN = 7 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_HASH_2_RESERVED_48 = 48 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_HASH_2_HWD_14 = 49 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_HASH_2_HWD_14_LEN = 7 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_HASH_2_RESERVED_56 = 56 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_HASH_2_HWD_15 = 57 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_HASH_2_HWD_15_LEN = 7 ;
+
+static const uint8_t P9N2_PU_INT_VC_IVC_HASH_3_RESERVED_0 = 0 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_HASH_3_IPI = 1 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_HASH_3_IPI_LEN = 7 ;
+
+static const uint8_t P9N2_PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_IPI_DOES_PRF_IVE = 0 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_IPI_DOES_PRF_IVE_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_IPI_DOES_PRF_IVE_SBC = 4 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_IPI_DOES_PRF_IVE_SBC_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_HWD_DOES_PRF_IVE = 8 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_HWD_DOES_PRF_IVE_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_IPI_DOES_DEM_IVE = 12 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_IPI_DOES_DEM_IVE_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_IPI_DOES_DEM_IVE_SBC = 16 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_IPI_DOES_DEM_IVE_SBC_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_PERF_EVENT_SEL_1_CND_HWD_DOES_DEM_IVE = 20 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_PERF_EVENT_SEL_1_CND_HWD_DOES_DEM_IVE_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_PRF_CACHE_HIT = 24 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_PRF_CACHE_HIT_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_DEM_CACHE_HIT = 28 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_DEM_CACHE_HIT_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_LRU = 32 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_LRU_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_1ST_USABLE = 36 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_1ST_USABLE_LEN = 4 ;
+
+static const uint8_t P9N2_PU_INT_VC_IVC_PERF_EVENT_SEL_2_CNT_IVE_FETCH = 0 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_PERF_EVENT_SEL_2_CNT_IVE_FETCH_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_PERF_EVENT_SEL_2_CNT_SBC_LOOKUP = 4 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_PERF_EVENT_SEL_2_CNT_SBC_LOOKUP_LEN = 4 ;
+
+static const uint8_t P9N2_PU_INT_VC_IVC_PERF_EVENT_SEL_3_CNT_IVE_FETCH_REPLAY = 0 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_PERF_EVENT_SEL_3_CNT_IVE_FETCH_REPLAY_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_PERF_EVENT_SEL_3_CNT_SBC_LOOKUP_REPLAY = 4 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_PERF_EVENT_SEL_3_CNT_SBC_LOOKUP_REPLAY_LEN = 4 ;
+
+static const uint8_t P9N2_PU_INT_VC_IVC_SCRUB_MASK_BLOCKID = 28 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_SCRUB_MASK_BLOCKID_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_SCRUB_MASK_RESERVED_32_35 = 32 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_SCRUB_MASK_RESERVED_32_35_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_SCRUB_MASK_OFFSET = 36 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_SCRUB_MASK_OFFSET_LEN = 28 ;
+
+static const uint8_t P9N2_PU_INT_VC_IVC_SCRUB_TRIG_VALID = 0 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_SCRUB_TRIG_WANT_CACHE_DISABLE = 1 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_SCRUB_TRIG_BLOCKID = 28 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_SCRUB_TRIG_BLOCKID_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_SCRUB_TRIG_RESERVED_32_35 = 32 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_SCRUB_TRIG_RESERVED_32_35_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_SCRUB_TRIG_OFFSET = 36 ;
+static const uint8_t P9N2_PU_INT_VC_IVC_SCRUB_TRIG_OFFSET_LEN = 28 ;
+
+static const uint8_t P9N2_PU_INT_VC_IVE_ISB_BLOCK_MODE_MODE = 32 ;
+static const uint8_t P9N2_PU_INT_VC_IVE_ISB_BLOCK_MODE_MODE_LEN = 32 ;
+
+static const uint8_t P9N2_PU_INT_VC_LBS6_DEBUG_DIS_AIB_IN_ECC_CORRECTION = 0 ;
+static const uint8_t P9N2_PU_INT_VC_LBS6_DEBUG_DIS_IRQ_ECC_CORRECTION = 1 ;
+static const uint8_t P9N2_PU_INT_VC_LBS6_DEBUG_DIS_AT_SRAM_ECC_CORRECTION = 2 ;
+static const uint8_t P9N2_PU_INT_VC_LBS6_DEBUG_DIS_BAR_SRAM_ECC_CORRECTION = 3 ;
+static const uint8_t P9N2_PU_INT_VC_LBS6_DEBUG_DIS_TAG_SRAM_ECC_CORRECTION = 4 ;
+static const uint8_t P9N2_PU_INT_VC_LBS6_DEBUG_IRQ_TRACE_ENABLE = 5 ;
+static const uint8_t P9N2_PU_INT_VC_LBS6_DEBUG_FORCE_SINGLE_BIT_ECC_ERR = 6 ;
+static const uint8_t P9N2_PU_INT_VC_LBS6_DEBUG_FORCE_DOUBLE_BIT_ECC_ERR = 7 ;
+static const uint8_t P9N2_PU_INT_VC_LBS6_DEBUG_TRIG_TRACE_ENABLE = 8 ;
+static const uint8_t P9N2_PU_INT_VC_LBS6_DEBUG_RESERVED_9 = 9 ;
+static const uint8_t P9N2_PU_INT_VC_LBS6_DEBUG_ECC_ERR_INJ_SELECTION = 10 ;
+static const uint8_t P9N2_PU_INT_VC_LBS6_DEBUG_ECC_ERR_INJ_SELECTION_LEN = 6 ;
+static const uint8_t P9N2_PU_INT_VC_LBS6_DEBUG_ATX_CACHE_SLOTS_IDLE = 16 ;
+static const uint8_t P9N2_PU_INT_VC_LBS6_DEBUG_ATX_IS_IDLE = 17 ;
+
+static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_RESERVED_0_17 = 0 ;
+static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_RESERVED_0_17_LEN = 18 ;
+static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_CI_STORE = 18 ;
+static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_CI_STORE_LEN = 6 ;
+static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_RESERVED_24_25 = 24 ;
+static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_RESERVED_24_25_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_REQUEST = 26 ;
+static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_REQUEST_LEN = 6 ;
+static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_RESERVED_32_33 = 32 ;
+static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_RESERVED_32_33_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_EQ_POST = 34 ;
+static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_EQ_POST_LEN = 6 ;
+static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_RESERVED_40_41 = 40 ;
+static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_RESERVED_40_41_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_CI_LOAD = 42 ;
+static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_CI_LOAD_LEN = 6 ;
+static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_RESERVED_48_49 = 48 ;
+static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_RESERVED_48_49_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_EQD_DMA_READ = 50 ;
+static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_EQD_DMA_READ_LEN = 6 ;
+static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_RESERVED_56_57 = 56 ;
+static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_RESERVED_56_57_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_EQD_DMA_WRITE = 58 ;
+static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_EQD_DMA_WRITE_LEN = 6 ;
+
+static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_IRQ_DMA_RESERVED_0_17 = 0 ;
+static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_IRQ_DMA_RESERVED_0_17_LEN = 18 ;
+static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_IRQ_DMA_DMA_READ = 18 ;
+static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_IRQ_DMA_DMA_READ_LEN = 6 ;
+static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_IRQ_DMA_RESERVED_24_25 = 24 ;
+static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_IRQ_DMA_RESERVED_24_25_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_IRQ_DMA_DMA_WRITE = 26 ;
+static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_IRQ_DMA_DMA_WRITE_LEN = 6 ;
+
+static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_IVC_CMD_RESERVED_48_50 = 48 ;
+static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_IVC_CMD_RESERVED_48_50_LEN = 3 ;
+static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_IVC_CMD_SBC_LOOKUP = 51 ;
+static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_IVC_CMD_SBC_LOOKUP_LEN = 5 ;
+static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_IVC_CMD_RESERVED_56_58 = 56 ;
+static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_IVC_CMD_RESERVED_56_58_LEN = 3 ;
+static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_IVC_CMD_DMA_READ = 59 ;
+static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_IVC_CMD_DMA_READ_LEN = 5 ;
+
+static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_SBC_CMD_RESERVED_48_50 = 48 ;
+static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_SBC_CMD_RESERVED_48_50_LEN = 3 ;
+static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_SBC_CMD_DMA_READ = 51 ;
+static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_SBC_CMD_DMA_READ_LEN = 5 ;
+static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_SBC_CMD_RESERVED_56_58 = 56 ;
+static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_SBC_CMD_RESERVED_56_58_LEN = 3 ;
+static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_SBC_CMD_DMA_WRITE = 59 ;
+static const uint8_t P9N2_PU_INT_VC_MAX_OUTSTANDING_SBC_CMD_DMA_WRITE_LEN = 5 ;
+
+static const uint8_t P9N2_PU_INT_VC_RECOV_ERR_G0_ERROR = 0 ;
+static const uint8_t P9N2_PU_INT_VC_RECOV_ERR_G0_ERROR_LEN = 55 ;
+
+static const uint8_t P9N2_PU_INT_VC_RECOV_ERR_G1_ERROR = 0 ;
+static const uint8_t P9N2_PU_INT_VC_RECOV_ERR_G1_ERROR_LEN = 43 ;
+
+static const uint8_t P9N2_PU_INT_VC_SBC_ADDITIONAL_PERF_P0_IS_IDLE = 0 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_ADDITIONAL_PERF_P1_IS_IDLE = 1 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_ADDITIONAL_PERF_MAX_PTAG_IN_USE = 8 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_ADDITIONAL_PERF_MAX_PTAG_IN_USE_LEN = 8 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_ADDITIONAL_PERF_MAX_OUTSTANDING_SOFT_EOI = 16 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_ADDITIONAL_PERF_MAX_OUTSTANDING_SOFT_EOI_LEN = 8 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_ADDITIONAL_PERF_MAX_UNLOCK_IN_FIFO = 24 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_ADDITIONAL_PERF_MAX_UNLOCK_IN_FIFO_LEN = 8 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_ADDITIONAL_PERF_MAX_OUTSTANDING_ISB_FETCH = 48 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_ADDITIONAL_PERF_MAX_OUTSTANDING_ISB_FETCH_LEN = 8 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_ADDITIONAL_PERF_MAX_OUTSTANDING_ISB_WRITE = 56 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_ADDITIONAL_PERF_MAX_OUTSTANDING_ISB_WRITE_LEN = 8 ;
+
+static const uint8_t P9N2_PU_INT_VC_SBC_CACHE_EN_ENABLE = 0 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_CACHE_EN_ENABLE_LEN = 16 ;
+
+static const uint8_t P9N2_PU_INT_VC_SBC_CACHE_WATCH_ADDR_SET_INDEX = 54 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_CACHE_WATCH_ADDR_SET_INDEX_LEN = 6 ;
+
+static const uint8_t P9N2_PU_INT_VC_SBC_CACHE_WATCH_DATA_DATA = 0 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_CACHE_WATCH_DATA_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_PU_INT_VC_SBC_CONFIG_ENABLE_COMPLEX_CI_STORE = 44 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_CONFIG_ENABLE_COMPLEX_CI_STORE_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_CONFIG_RESERVED_46 = 46 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_CONFIG_MAX_PTAG_IN_USE = 47 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_CONFIG_MAX_PTAG_IN_USE_LEN = 5 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_CONFIG_BG_SCAN_RATE = 52 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_CONFIG_BG_SCAN_RATE_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_CONFIG_RESERVED_56_57 = 56 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_CONFIG_RESERVED_56_57_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_CONFIG_FORCE_INVALIDATE = 58 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_CONFIG_DONT_UPDATE_ON_PRF = 59 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_CONFIG_MAX_ENTRIES_IN_MODIFIED = 60 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_CONFIG_MAX_ENTRIES_IN_MODIFIED_LEN = 4 ;
+
+static const uint8_t P9N2_PU_INT_VC_SBC_DEBUG_RESERVED_32_33 = 32 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_DEBUG_RESERVED_32_33_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_DEBUG_DIS_TAG_ECC_CORRECTION = 34 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_DEBUG_DIS_TAG_ECC_CORRECTION_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_DEBUG_RESERVED_38_41 = 38 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_DEBUG_RESERVED_38_41_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_DEBUG_DIS_STATE_ECC_CORRECTION = 42 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_DEBUG_RESERVED_43_44 = 43 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_DEBUG_RESERVED_43_44_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_DEBUG_DIS_DATA_ECC_CORRECTION = 45 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_DEBUG_DIS_DATA_ECC_CORRECTION_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_DEBUG_RESERVED_47_48 = 47 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_DEBUG_RESERVED_47_48_LEN = 2 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_DEBUG_FORCE_SINGLE_BIT_ECC_ERR = 49 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_DEBUG_FORCE_DOUBLE_BIT_ECC_ERR = 50 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_DEBUG_ECC_ERR_INJ_ARRAY_SEL = 51 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_DEBUG_ECC_ERR_INJ_ARRAY_SEL_LEN = 5 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_DEBUG_TRACE_ENABLE = 56 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_DEBUG_RESERVED_57_59 = 57 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_DEBUG_RESERVED_57_59_LEN = 3 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_DEBUG_CACHE_CTRL_ARY_SELECT = 60 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_DEBUG_CACHE_CTRL_ARY_SELECT_LEN = 4 ;
+
+static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_IVC_PRF = 0 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_IVC_PRF_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_IVC_DEMAND = 4 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_IVC_DEMAND_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_EQC_COMMAND = 8 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_EQC_COMMAND_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_NON_SPEC_EOI_OWNED = 12 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_NON_SPEC_EOI_OWNED_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_NON_SPEC_EOI_NOTOWNED = 16 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_NON_SPEC_EOI_NOTOWNED_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_SPEC_EOI = 20 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_SPEC_EOI_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_SPEC_EOI_CACHE_HIT = 24 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_SPEC_EOI_CACHE_HIT_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_PRF_CACHE_HIT = 28 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_PRF_CACHE_HIT_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_OTHER_CACHE_HIT = 32 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_OTHER_CACHE_HIT_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_LRU = 36 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_LRU_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_1ST_USABLE = 40 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_1ST_USABLE_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_RETRY = 44 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_RETRY_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_TOO_MANY_ENTRIES = 48 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_TOO_MANY_ENTRIES_LEN = 4 ;
+
+static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_2_CNT_ISB_FETCH = 0 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_2_CNT_ISB_FETCH_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_2_CNT_IVVC_RESP = 4 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_2_CNT_IVVC_RESP_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_2_RESERVED_8_11 = 8 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_2_RESERVED_8_11_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_2_CNT_ISB_WRITE = 12 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_2_CNT_ISB_WRITE_LEN = 4 ;
+
+static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_3_CNT_ISB_FETCH_REPLAY = 0 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_3_CNT_ISB_FETCH_REPLAY_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_3_CNT_IVC_RESP_REPLAY = 4 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_3_CNT_IVC_RESP_REPLAY_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_3_CNT_EOI_RESP_REPLAY = 8 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_PERF_EVENT_SEL_3_CNT_EOI_RESP_REPLAY_LEN = 4 ;
+
+static const uint8_t P9N2_PU_INT_VC_SBC_SCRUB_MASK_BLOCKID = 28 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_SCRUB_MASK_BLOCKID_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_SCRUB_MASK_RESERVED_32_40 = 32 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_SCRUB_MASK_RESERVED_32_40_LEN = 9 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_SCRUB_MASK_OFFSET = 41 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_SCRUB_MASK_OFFSET_LEN = 23 ;
+
+static const uint8_t P9N2_PU_INT_VC_SBC_SCRUB_TRIG_VALID = 0 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_SCRUB_TRIG_WANT_CACHE_DISABLE = 1 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_SCRUB_TRIG_WANT_INVALIDATE = 2 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_SCRUB_TRIG_BLOCKID = 28 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_SCRUB_TRIG_BLOCKID_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_SCRUB_TRIG_RESERVED_32_40 = 32 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_SCRUB_TRIG_RESERVED_32_40_LEN = 9 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_SCRUB_TRIG_OFFSET = 41 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_SCRUB_TRIG_OFFSET_LEN = 23 ;
+
+static const uint8_t P9N2_PU_INT_VC_SBC_SOFTWR_ADDR_BLOCKID = 28 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_SOFTWR_ADDR_BLOCKID_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_SOFTWR_ADDR_RESERVED_32_35 = 32 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_SOFTWR_ADDR_RESERVED_32_35_LEN = 4 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_SOFTWR_ADDR_OFFSET = 36 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_SOFTWR_ADDR_OFFSET_LEN = 23 ;
+
+static const uint8_t P9N2_PU_INT_VC_SBC_SOFTWR_DATA_PQ_STATE = 0 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_SOFTWR_DATA_PQ_STATE_LEN = 64 ;
+
+static const uint8_t P9N2_PU_INT_VC_SBC_SOFTWR_MASK_MSK = 0 ;
+static const uint8_t P9N2_PU_INT_VC_SBC_SOFTWR_MASK_MSK_LEN = 32 ;
+
+static const uint8_t P9N2_PU_INT_VC_VPS_BLOCK_MODE_MODE = 0 ;
+static const uint8_t P9N2_PU_INT_VC_VPS_BLOCK_MODE_MODE_LEN = 64 ;
+
+static const uint8_t P9N2_PU_INT_VC_VSD_TABLE_ADDR_AUTO_INCREMENT = 0 ;
+static const uint8_t P9N2_PU_INT_VC_VSD_TABLE_ADDR_SELECT = 13 ;
+static const uint8_t P9N2_PU_INT_VC_VSD_TABLE_ADDR_SELECT_LEN = 3 ;
+static const uint8_t P9N2_PU_INT_VC_VSD_TABLE_ADDR_RESERVED_16_26 = 16 ;
+static const uint8_t P9N2_PU_INT_VC_VSD_TABLE_ADDR_RESERVED_16_26_LEN = 11 ;
+static const uint8_t P9N2_PU_INT_VC_VSD_TABLE_ADDR_ADDRESS = 27 ;
+static const uint8_t P9N2_PU_INT_VC_VSD_TABLE_ADDR_ADDRESS_LEN = 5 ;
+
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_IRQ_FIFO_INVALID_STATE = 0 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_IRQ_FIFO_CRD_ERROR = 1 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_IRQ_FIFO_OFFSET_ERROR = 2 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_IRQ_FIFO_DATA_ERROR = 3 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_IRQ_FIFO_ACCESS_ERROR = 4 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_IRQ_FIFO_OVERFLOW = 5 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_IRQ_FIFO_IDX_ERROR = 6 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_IRQ_FIFO_UNDERFLOW = 7 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_IRQ_FIFO_DIR_STATE_ERROR = 8 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_IRQ_FIFO_DIR_WR_ERROR = 9 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_IRQ_FIFO_DIR_RD_ERROR = 10 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_IRQ_FIFO_ECC_UE = 11 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_IRQ_EQC_CREDIT_ERROR = 12 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_IRQ_TRIG_CRD_ERROR = 13 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_IRQ_EFIFO_DIN_ERROR = 14 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_IRQ_INPUT_BUF_ERROR = 15 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_IRQ_EQ_ERROR = 16 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_IRQ_PQ_ERROR = 17 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_IRQ_EQPQ_ERROR = 18 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_IRQ_FIFO_ECC_CE = 19 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_ARX_CTRL_PTY_ERROR = 20 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_ARX_CMD_PTY_ERROR = 21 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_REGS_SCOM_INTERNAL_ERROR = 22 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_ARX_TAG_SRAM_ECC_UE = 23 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_ARX_AIB_DATA_ECC_UE = 24 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_REGS_PARITY_ERROR = 25 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_REGS_CMD_CRD_ERROR = 26 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_REGS_DATA_CRD_ERROR = 27 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_ARX_AIB_CMD_ERROR = 28 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_ARX_AIB_RESP_TIMEOUT = 29 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_ARX_AIB_DATA_ECC_CE = 30 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_ARX_TAG_SRAM_ECC_CE = 31 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_ATX_LACK_OF_TAG = 32 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_ATX_TAG_RELEASE_ERROR = 33 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_AT_BAD_CAM_STATE = 34 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_AT_MULTIPLE_HIT = 35 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_AT_PARITY_ERROR = 36 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_AT_MULTIPLE_PRF_RQ = 37 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_AT_TOO_LARGE_SLOTID = 38 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_AT_PRF_OVERFLOW = 39 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_AT_PRF_UNDERFLOW = 40 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_AT_INVALID_CMD = 41 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_AT_INVALID_IND_BAR = 42 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_AT_INVALID_IND_PZ = 43 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_AT_INVALID_I = 44 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_ATX_CRD_PARITY_ERROR = 45 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_ATX_AT_SRAM_ECC_UE = 46 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_ATX_BAR_SRAM_ECC_UE = 47 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_ATX_WB_SRAM_ECC_UE = 48 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_ATX_SLOT_OVERFLOW = 49 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_ATX_CRD_OVERFLOW = 50 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_ATX_CRD_UNDERFLOW = 51 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_ATX_INVALID_BAR = 52 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_ATX_PAGE_OVERFLOW = 53 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_ATX_SRAM_ECC_CE = 54 ;
+
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_DETAIL_ERROR = 0 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G0_DETAIL_ERROR_LEN = 64 ;
+
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_EQC_CL_INDEX_ERROR = 0 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_EQC_CRD_OR_RESP_ERROR = 1 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_EQC_PTAG_ASSIGN_ERROR = 2 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_EQC_PTAG_RELEASE_ERROR = 3 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_EQC_REPLAY_ERROR = 4 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_EQC_PARITY_ERROR = 5 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_EQC_TAG_SRAM_ECC_UE = 6 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_EQC_STATE_SRAM_ECC_UE = 7 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_EQC_DATA_SRAM_ECC_UE = 8 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_EQC_CTRL_SRAM_ECC_UE = 9 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_EQC_ARX_DATA_ECC_UE = 10 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_EQC_UNLOCK_FIFO_OVERFLOW = 11 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_EQC_EOI_OVERFLOW = 12 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_EQC_EOI_TAG_ERROR = 13 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_EQC_SRAM_ECC_CE = 14 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_EQC_PROCESSING_ERROR = 15 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_EQC_WATCH_ERROR = 16 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_EQC_CFG_ERROR_OR_MULTISYNC = 17 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_IVC_AIB_RESP_ERROR = 18 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_IVC_PTAG_ASSIGN_ERROR = 19 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_IVC_PTAG_RELEASE_ERROR = 20 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_IVC_REPLAY_ERROR = 21 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_IVC_PARITY_ERROR = 22 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_IVC_TAG_SRAM_ECC_UE = 23 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_IVC_STATE_SRAM_ECC_UE = 24 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_IVC_DATA_SRAM_ECC_UE = 25 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_IVC_UNLOCK_FIFO_OVERFLOW = 26 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_IVC_SRAM_ECC_CE = 27 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_IVC_PROCESSING_ERROR = 28 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_SBC_CL_INDEX_ERROR = 29 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_SBC_CRD_OR_RESP_ERROR = 30 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_SBC_PTAG_ASSIGN_ERROR = 31 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_SBC_PTAG_RELEASE_ERROR = 32 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_SBC_REPLAY_ERROR = 33 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_SBC_PARITY_ERROR = 34 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_SBC_TAG_SRAM_ECC_UE = 35 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_SBC_STATE_SRAM_ECC_UE = 36 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_SBC_DATA_SRAM_ECC_UE = 37 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_SBC_UNLOCK_FIFO_OVERFLOW = 38 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_SBC_EOI_OVERFLOW = 39 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_SBC_EOI_TAG_ERROR = 40 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_SBC_SRAM_ECC_CE = 41 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_SBC_PROCESSING_ERROR = 42 ;
+
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_DETAIL_ERROR = 0 ;
+static const uint8_t P9N2_PU_INT_VC_WOF_ERR_G1_DETAIL_ERROR_LEN = 64 ;
+
+static const uint8_t P9N2__SM1_IODA_ADDR_AUTO_INCREMENT = 0 ;
+static const uint8_t P9N2__SM1_IODA_ADDR_TABLE_SELECT = 11 ;
+static const uint8_t P9N2__SM1_IODA_ADDR_TABLE_SELECT_LEN = 5 ;
+static const uint8_t P9N2__SM1_IODA_ADDR_TABLE_ADDRESS = 54 ;
+static const uint8_t P9N2__SM1_IODA_ADDR_TABLE_ADDRESS_LEN = 10 ;
+
+static const uint8_t P9N2__SM1_IODA_DAT0_TABLE_DATA = 0 ;
+static const uint8_t P9N2__SM1_IODA_DAT0_TABLE_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_PU_IO_DATA_REG_PCB_TMP = 0 ;
+static const uint8_t P9N2_PU_IO_DATA_REG_PCB_TMP_LEN = 64 ;
+
+static const uint8_t P9N2_PU_IVT_OFFSET_PAYLOAD = 0 ;
+static const uint8_t P9N2_PU_IVT_OFFSET_PAYLOAD_LEN = 28 ;
+
+static const uint8_t P9N2_PU_JTG_PIB_OJCFG_JTAG_SRC_SEL = 0 ;
+static const uint8_t P9N2_PU_JTG_PIB_OJCFG_RUN_TCK = 1 ;
+static const uint8_t P9N2_PU_JTG_PIB_OJCFG_TCK_WIDTH = 2 ;
+static const uint8_t P9N2_PU_JTG_PIB_OJCFG_TCK_WIDTH_LEN = 3 ;
+static const uint8_t P9N2_PU_JTG_PIB_OJCFG_JTAG_TRST_B = 5 ;
+static const uint8_t P9N2_PU_JTG_PIB_OJCFG_DBG_HALT = 6 ;
+
+static const uint8_t P9N2_PU_JTG_PIB_OJIC_START_JTAG_CMD = 0 ;
+static const uint8_t P9N2_PU_JTG_PIB_OJIC_DO_IR = 1 ;
+static const uint8_t P9N2_PU_JTG_PIB_OJIC_DO_DR = 2 ;
+static const uint8_t P9N2_PU_JTG_PIB_OJIC_DO_TAP_RESET = 3 ;
+static const uint8_t P9N2_PU_JTG_PIB_OJIC_WR_VALID = 4 ;
+static const uint8_t P9N2_PU_JTG_PIB_OJIC_JTAG_INSTR = 12 ;
+static const uint8_t P9N2_PU_JTG_PIB_OJIC_JTAG_INSTR_LEN = 4 ;
+
+static const uint8_t P9N2_PU_JTG_PIB_OJSTAT_JTAG_INPROG = 0 ;
+static const uint8_t P9N2_PU_JTG_PIB_OJSTAT_SRC_SEL_EQ1_ERR = 1 ;
+static const uint8_t P9N2_PU_JTG_PIB_OJSTAT_RUN_TCK_EQ0_ERR = 2 ;
+static const uint8_t P9N2_PU_JTG_PIB_OJSTAT_TRST_B_EQ0_ERR = 3 ;
+static const uint8_t P9N2_PU_JTG_PIB_OJSTAT_IR_DR_EQ0_ERR = 4 ;
+static const uint8_t P9N2_PU_JTG_PIB_OJSTAT_INPROG_WR_ERR = 5 ;
+static const uint8_t P9N2_PU_JTG_PIB_OJSTAT_FSM_ERROR = 6 ;
+
+static const uint8_t P9N2_PU_JTG_PIB_OJTDI_JTAG_TDI = 0 ;
+static const uint8_t P9N2_PU_JTG_PIB_OJTDI_JTAG_TDI_LEN = 32 ;
+
+static const uint8_t P9N2_PU_JTG_PIB_OJTDO_JTAG_TDO = 0 ;
+static const uint8_t P9N2_PU_JTG_PIB_OJTDO_JTAG_TDO_LEN = 32 ;
+static const uint8_t P9N2_PU_JTG_PIB_OJTDO_OJCFG_JTAG_SRC_SEL = 32 ;
+static const uint8_t P9N2_PU_JTG_PIB_OJTDO_OJCFG_RUN_TCK = 33 ;
+static const uint8_t P9N2_PU_JTG_PIB_OJTDO_OJCFG_TCK_WIDTH = 34 ;
+static const uint8_t P9N2_PU_JTG_PIB_OJTDO_OJCFG_TCK_WIDTH_LEN = 3 ;
+static const uint8_t P9N2_PU_JTG_PIB_OJTDO_OJCFG_JTAG_TRST_B = 37 ;
+static const uint8_t P9N2_PU_JTG_PIB_OJTDO_OJCFG_DBG_HALT = 38 ;
+static const uint8_t P9N2_PU_JTG_PIB_OJTDO_OJSTAT_JTAG_INPROG = 40 ;
+static const uint8_t P9N2_PU_JTG_PIB_OJTDO_OJSTAT_SRC_SEL_EQ1_ERR = 41 ;
+static const uint8_t P9N2_PU_JTG_PIB_OJTDO_OJSTAT_RUN_TCK_EQ0_ERR = 42 ;
+static const uint8_t P9N2_PU_JTG_PIB_OJTDO_OJSTAT_TRST_B_EQ0_ERR = 43 ;
+static const uint8_t P9N2_PU_JTG_PIB_OJTDO_OJSTAT_IR_DR_EQ0_ERR = 44 ;
+static const uint8_t P9N2_PU_JTG_PIB_OJTDO_OJSTAT_INPROG_WR_ERR = 45 ;
+static const uint8_t P9N2_PU_JTG_PIB_OJTDO_OJSTAT_FSM_ERROR = 46 ;
+static const uint8_t P9N2_PU_JTG_PIB_OJTDO_OJIC_DO_IR = 49 ;
+static const uint8_t P9N2_PU_JTG_PIB_OJTDO_OJIC_DO_DR = 50 ;
+static const uint8_t P9N2_PU_JTG_PIB_OJTDO_OJIC_DO_TAP_RESET = 51 ;
+static const uint8_t P9N2_PU_JTG_PIB_OJTDO_OJIC_WR_VALID = 52 ;
+static const uint8_t P9N2_PU_JTG_PIB_OJTDO_OJIC_JTAG_INSTR = 60 ;
+static const uint8_t P9N2_PU_JTG_PIB_OJTDO_OJIC_JTAG_INSTR_LEN = 4 ;
+
+static const uint8_t P9N2__CTL_LCO_CONFIG_V_TARG = 0 ;
+static const uint8_t P9N2__CTL_LCO_CONFIG_V_TARG_LEN = 12 ;
+static const uint8_t P9N2__CTL_LCO_CONFIG_E_TARG_MIN = 12 ;
+static const uint8_t P9N2__CTL_LCO_CONFIG_E_TARG_MIN_LEN = 4 ;
+static const uint8_t P9N2__CTL_LCO_CONFIG_RAND_EVENT = 16 ;
+static const uint8_t P9N2__CTL_LCO_CONFIG_RAND_EVENT_LEN = 4 ;
+
+static const uint8_t P9N2_CAPP_LINK_DELAY_TIMER_VALUE = 0 ;
+static const uint8_t P9N2_CAPP_LINK_DELAY_TIMER_VALUE_LEN = 29 ;
+static const uint8_t P9N2_CAPP_LINK_DELAY_TIMER_VALID = 32 ;
+static const uint8_t P9N2_CAPP_LINK_DELAY_TIMER_RESP_PKT_RCV = 33 ;
+static const uint8_t P9N2_CAPP_LINK_DELAY_TIMER_SECURE_ERR = 34 ;
+
+static const uint8_t P9N2_PEC_LOCAL_FIR_IN0 = 0 ;
+static const uint8_t P9N2_PEC_LOCAL_FIR_IN1 = 1 ;
+static const uint8_t P9N2_PEC_LOCAL_FIR_IN2 = 2 ;
+static const uint8_t P9N2_PEC_LOCAL_FIR_IN3 = 3 ;
+static const uint8_t P9N2_PEC_LOCAL_FIR_IN4 = 4 ;
+static const uint8_t P9N2_PEC_LOCAL_FIR_IN5 = 5 ;
+static const uint8_t P9N2_PEC_LOCAL_FIR_IN6 = 6 ;
+static const uint8_t P9N2_PEC_LOCAL_FIR_IN7 = 7 ;
+static const uint8_t P9N2_PEC_LOCAL_FIR_IN8 = 8 ;
+static const uint8_t P9N2_PEC_LOCAL_FIR_IN9 = 9 ;
+static const uint8_t P9N2_PEC_LOCAL_FIR_IN10 = 10 ;
+static const uint8_t P9N2_PEC_LOCAL_FIR_IN11 = 11 ;
+static const uint8_t P9N2_PEC_LOCAL_FIR_IN12 = 12 ;
+static const uint8_t P9N2_PEC_LOCAL_FIR_IN13 = 13 ;
+static const uint8_t P9N2_PEC_LOCAL_FIR_IN14 = 14 ;
+static const uint8_t P9N2_PEC_LOCAL_FIR_IN15 = 15 ;
+static const uint8_t P9N2_PEC_LOCAL_FIR_IN16 = 16 ;
+static const uint8_t P9N2_PEC_LOCAL_FIR_IN17 = 17 ;
+static const uint8_t P9N2_PEC_LOCAL_FIR_IN18 = 18 ;
+static const uint8_t P9N2_PEC_LOCAL_FIR_IN19 = 19 ;
+static const uint8_t P9N2_PEC_LOCAL_FIR_IN20 = 20 ;
+static const uint8_t P9N2_PEC_LOCAL_FIR_IN21 = 21 ;
+static const uint8_t P9N2_PEC_LOCAL_FIR_IN22 = 22 ;
+static const uint8_t P9N2_PEC_LOCAL_FIR_IN23 = 23 ;
+static const uint8_t P9N2_PEC_LOCAL_FIR_IN24 = 24 ;
+static const uint8_t P9N2_PEC_LOCAL_FIR_IN25 = 25 ;
+static const uint8_t P9N2_PEC_LOCAL_FIR_IN26 = 26 ;
+static const uint8_t P9N2_PEC_LOCAL_FIR_IN27 = 27 ;
+static const uint8_t P9N2_PEC_LOCAL_FIR_IN28 = 28 ;
+static const uint8_t P9N2_PEC_LOCAL_FIR_IN29 = 29 ;
+static const uint8_t P9N2_PEC_LOCAL_FIR_IN30 = 30 ;
+static const uint8_t P9N2_PEC_LOCAL_FIR_IN31 = 31 ;
+static const uint8_t P9N2_PEC_LOCAL_FIR_IN32 = 32 ;
+static const uint8_t P9N2_PEC_LOCAL_FIR_IN33 = 33 ;
+static const uint8_t P9N2_PEC_LOCAL_FIR_IN34 = 34 ;
+static const uint8_t P9N2_PEC_LOCAL_FIR_IN35 = 35 ;
+static const uint8_t P9N2_PEC_LOCAL_FIR_IN36 = 36 ;
+static const uint8_t P9N2_PEC_LOCAL_FIR_IN37 = 37 ;
+static const uint8_t P9N2_PEC_LOCAL_FIR_IN38 = 38 ;
+static const uint8_t P9N2_PEC_LOCAL_FIR_IN39 = 39 ;
+static const uint8_t P9N2_PEC_LOCAL_FIR_IN40 = 40 ;
+static const uint8_t P9N2_PEC_LOCAL_FIR_IN41 = 41 ;
+
+static const uint8_t P9N2_PEC_LOCAL_FIR_ACTION0_IN = 0 ;
+static const uint8_t P9N2_PEC_LOCAL_FIR_ACTION0_IN_LEN = 42 ;
+
+static const uint8_t P9N2_PEC_LOCAL_FIR_ACTION1_IN = 0 ;
+static const uint8_t P9N2_PEC_LOCAL_FIR_ACTION1_IN_LEN = 42 ;
+
+static const uint8_t P9N2_PEC_LOCAL_FIR_MASK_LFIR_IN = 0 ;
+static const uint8_t P9N2_PEC_LOCAL_FIR_MASK_LFIR_IN_LEN = 42 ;
+
+static const uint8_t P9N2_PEC_LOCAL_XSTOP_ERR_IN0 = 0 ;
+static const uint8_t P9N2_PEC_LOCAL_XSTOP_ERR_IN1 = 1 ;
+static const uint8_t P9N2_PEC_LOCAL_XSTOP_ERR_IN2 = 2 ;
+static const uint8_t P9N2_PEC_LOCAL_XSTOP_ERR_IN3 = 3 ;
+static const uint8_t P9N2_PEC_LOCAL_XSTOP_ERR_IN4 = 4 ;
+static const uint8_t P9N2_PEC_LOCAL_XSTOP_ERR_IN5 = 5 ;
+static const uint8_t P9N2_PEC_LOCAL_XSTOP_ERR_IN6 = 6 ;
+static const uint8_t P9N2_PEC_LOCAL_XSTOP_ERR_IN7 = 7 ;
+static const uint8_t P9N2_PEC_LOCAL_XSTOP_ERR_IN8 = 8 ;
+static const uint8_t P9N2_PEC_LOCAL_XSTOP_ERR_IN9 = 9 ;
+static const uint8_t P9N2_PEC_LOCAL_XSTOP_ERR_IN10 = 10 ;
+static const uint8_t P9N2_PEC_LOCAL_XSTOP_ERR_IN11 = 11 ;
+static const uint8_t P9N2_PEC_LOCAL_XSTOP_ERR_IN12 = 12 ;
+static const uint8_t P9N2_PEC_LOCAL_XSTOP_ERR_IN13 = 13 ;
+static const uint8_t P9N2_PEC_LOCAL_XSTOP_ERR_IN14 = 14 ;
+static const uint8_t P9N2_PEC_LOCAL_XSTOP_ERR_IN15 = 15 ;
+static const uint8_t P9N2_PEC_LOCAL_XSTOP_ERR_IN16 = 16 ;
+static const uint8_t P9N2_PEC_LOCAL_XSTOP_ERR_IN17 = 17 ;
+static const uint8_t P9N2_PEC_LOCAL_XSTOP_ERR_IN18 = 18 ;
+static const uint8_t P9N2_PEC_LOCAL_XSTOP_ERR_IN19 = 19 ;
+static const uint8_t P9N2_PEC_LOCAL_XSTOP_ERR_IN20 = 20 ;
+static const uint8_t P9N2_PEC_LOCAL_XSTOP_ERR_IN21 = 21 ;
+static const uint8_t P9N2_PEC_LOCAL_XSTOP_ERR_IN22 = 22 ;
+
+static const uint8_t P9N2_PEC_LOCAL_XSTOP_MASK_IN = 0 ;
+static const uint8_t P9N2_PEC_LOCAL_XSTOP_MASK_IN_LEN = 22 ;
+
+static const uint8_t P9N2_PU_NPU1_SM1_LOW_PWR_LP_MODE_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NPU1_SM1_LOW_PWR_LP_ONLY_MODE = 1 ;
+static const uint8_t P9N2_PU_NPU1_SM1_LOW_PWR_LP_TIMER_TICK_CONFIG = 2 ;
+static const uint8_t P9N2_PU_NPU1_SM1_LOW_PWR_LP_TIMER_TICK_CONFIG_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU1_SM1_LOW_PWR_LP_MIN_CRED_THRESH = 8 ;
+static const uint8_t P9N2_PU_NPU1_SM1_LOW_PWR_LP_MIN_CRED_THRESH_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU1_SM1_LOW_PWR_LP_MAX_CRED_THRESH = 20 ;
+static const uint8_t P9N2_PU_NPU1_SM1_LOW_PWR_LP_MAX_CRED_THRESH_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU1_SM1_LOW_PWR_LP_CNT_THRESH = 32 ;
+static const uint8_t P9N2_PU_NPU1_SM1_LOW_PWR_LP_CNT_THRESH_LEN = 12 ;
+
+static const uint8_t P9N2_PU_NPU_SM2_LOW_PWR_LP_MODE_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NPU_SM2_LOW_PWR_LP_ONLY_MODE = 1 ;
+static const uint8_t P9N2_PU_NPU_SM2_LOW_PWR_LP_TIMER_TICK_CONFIG = 2 ;
+static const uint8_t P9N2_PU_NPU_SM2_LOW_PWR_LP_TIMER_TICK_CONFIG_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_SM2_LOW_PWR_LP_MIN_CRED_THRESH = 8 ;
+static const uint8_t P9N2_PU_NPU_SM2_LOW_PWR_LP_MIN_CRED_THRESH_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU_SM2_LOW_PWR_LP_MAX_CRED_THRESH = 20 ;
+static const uint8_t P9N2_PU_NPU_SM2_LOW_PWR_LP_MAX_CRED_THRESH_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU_SM2_LOW_PWR_LP_CNT_THRESH = 32 ;
+static const uint8_t P9N2_PU_NPU_SM2_LOW_PWR_LP_CNT_THRESH_LEN = 12 ;
+
+static const uint8_t P9N2_PU_NPU1_SM2_LOW_PWR_LP_MODE_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NPU1_SM2_LOW_PWR_LP_ONLY_MODE = 1 ;
+static const uint8_t P9N2_PU_NPU1_SM2_LOW_PWR_LP_TIMER_TICK_CONFIG = 2 ;
+static const uint8_t P9N2_PU_NPU1_SM2_LOW_PWR_LP_TIMER_TICK_CONFIG_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU1_SM2_LOW_PWR_LP_MIN_CRED_THRESH = 8 ;
+static const uint8_t P9N2_PU_NPU1_SM2_LOW_PWR_LP_MIN_CRED_THRESH_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU1_SM2_LOW_PWR_LP_MAX_CRED_THRESH = 20 ;
+static const uint8_t P9N2_PU_NPU1_SM2_LOW_PWR_LP_MAX_CRED_THRESH_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU1_SM2_LOW_PWR_LP_CNT_THRESH = 32 ;
+static const uint8_t P9N2_PU_NPU1_SM2_LOW_PWR_LP_CNT_THRESH_LEN = 12 ;
+
+static const uint8_t P9N2_PU_NPU_SM1_LOW_PWR_LP_MODE_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NPU_SM1_LOW_PWR_LP_ONLY_MODE = 1 ;
+static const uint8_t P9N2_PU_NPU_SM1_LOW_PWR_LP_TIMER_TICK_CONFIG = 2 ;
+static const uint8_t P9N2_PU_NPU_SM1_LOW_PWR_LP_TIMER_TICK_CONFIG_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_SM1_LOW_PWR_LP_MIN_CRED_THRESH = 8 ;
+static const uint8_t P9N2_PU_NPU_SM1_LOW_PWR_LP_MIN_CRED_THRESH_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU_SM1_LOW_PWR_LP_MAX_CRED_THRESH = 20 ;
+static const uint8_t P9N2_PU_NPU_SM1_LOW_PWR_LP_MAX_CRED_THRESH_LEN = 12 ;
+static const uint8_t P9N2_PU_NPU_SM1_LOW_PWR_LP_CNT_THRESH = 32 ;
+static const uint8_t P9N2_PU_NPU_SM1_LOW_PWR_LP_CNT_THRESH_LEN = 12 ;
+
+static const uint8_t P9N2__SM2_LOW_PWR_LP_MODE_ENABLE = 0 ;
+static const uint8_t P9N2__SM2_LOW_PWR_LP_ONLY_MODE = 1 ;
+static const uint8_t P9N2__SM2_LOW_PWR_LP_TIMER_TICK_CONFIG = 2 ;
+static const uint8_t P9N2__SM2_LOW_PWR_LP_TIMER_TICK_CONFIG_LEN = 6 ;
+static const uint8_t P9N2__SM2_LOW_PWR_LP_MIN_CRED_THRESH = 8 ;
+static const uint8_t P9N2__SM2_LOW_PWR_LP_MIN_CRED_THRESH_LEN = 12 ;
+static const uint8_t P9N2__SM2_LOW_PWR_LP_MAX_CRED_THRESH = 20 ;
+static const uint8_t P9N2__SM2_LOW_PWR_LP_MAX_CRED_THRESH_LEN = 12 ;
+static const uint8_t P9N2__SM2_LOW_PWR_LP_CNT_THRESH = 32 ;
+static const uint8_t P9N2__SM2_LOW_PWR_LP_CNT_THRESH_LEN = 12 ;
+
+static const uint8_t P9N2__SM1_LOW_PWR_LP_MODE_ENABLE = 0 ;
+static const uint8_t P9N2__SM1_LOW_PWR_LP_ONLY_MODE = 1 ;
+static const uint8_t P9N2__SM1_LOW_PWR_LP_TIMER_TICK_CONFIG = 2 ;
+static const uint8_t P9N2__SM1_LOW_PWR_LP_TIMER_TICK_CONFIG_LEN = 6 ;
+static const uint8_t P9N2__SM1_LOW_PWR_LP_MIN_CRED_THRESH = 8 ;
+static const uint8_t P9N2__SM1_LOW_PWR_LP_MIN_CRED_THRESH_LEN = 12 ;
+static const uint8_t P9N2__SM1_LOW_PWR_LP_MAX_CRED_THRESH = 20 ;
+static const uint8_t P9N2__SM1_LOW_PWR_LP_MAX_CRED_THRESH_LEN = 12 ;
+static const uint8_t P9N2__SM1_LOW_PWR_LP_CNT_THRESH = 32 ;
+static const uint8_t P9N2__SM1_LOW_PWR_LP_CNT_THRESH_LEN = 12 ;
+
+static const uint8_t P9N2_PU_NPU0_SM0_LOW_WATER_CONFIG_XATS = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM0_LOW_WATER_CONFIG_XATS_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM0_LOW_WATER_CONFIG_PWR0 = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM0_LOW_WATER_CONFIG_PWR0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM0_LOW_WATER_CONFIG_PWR1 = 12 ;
+static const uint8_t P9N2_PU_NPU0_SM0_LOW_WATER_CONFIG_PWR1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM0_LOW_WATER_CONFIG_REQ0 = 18 ;
+static const uint8_t P9N2_PU_NPU0_SM0_LOW_WATER_CONFIG_REQ0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM0_LOW_WATER_CONFIG_PRB0 = 24 ;
+static const uint8_t P9N2_PU_NPU0_SM0_LOW_WATER_CONFIG_PRB0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM0_LOW_WATER_CONFIG_REQ1 = 30 ;
+static const uint8_t P9N2_PU_NPU0_SM0_LOW_WATER_CONFIG_REQ1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM0_LOW_WATER_CONFIG_PRB1 = 36 ;
+static const uint8_t P9N2_PU_NPU0_SM0_LOW_WATER_CONFIG_PRB1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM0_LOW_WATER_CONFIG_MAX_MACHINES = 42 ;
+static const uint8_t P9N2_PU_NPU0_SM0_LOW_WATER_CONFIG_MAX_MACHINES_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM0_LOW_WATER_RESERVED1 = 48 ;
+static const uint8_t P9N2_PU_NPU0_SM0_LOW_WATER_RESERVED1_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM0_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC = 51 ;
+static const uint8_t P9N2_PU_NPU0_SM0_LOW_WATER_CONFIG_INTS = 52 ;
+static const uint8_t P9N2_PU_NPU0_SM0_LOW_WATER_CONFIG_INTS_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM0_LOW_WATER_RESERVED2 = 58 ;
+static const uint8_t P9N2_PU_NPU0_SM0_LOW_WATER_RESERVED2_LEN = 2 ;
+
+static const uint8_t P9N2_PU_NPU2_SM3_LOW_WATER_CONFIG_XATS = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM3_LOW_WATER_CONFIG_XATS_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM3_LOW_WATER_CONFIG_PWR0 = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM3_LOW_WATER_CONFIG_PWR0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM3_LOW_WATER_CONFIG_PWR1 = 12 ;
+static const uint8_t P9N2_PU_NPU2_SM3_LOW_WATER_CONFIG_PWR1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM3_LOW_WATER_CONFIG_REQ0 = 18 ;
+static const uint8_t P9N2_PU_NPU2_SM3_LOW_WATER_CONFIG_REQ0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM3_LOW_WATER_CONFIG_PRB0 = 24 ;
+static const uint8_t P9N2_PU_NPU2_SM3_LOW_WATER_CONFIG_PRB0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM3_LOW_WATER_CONFIG_REQ1 = 30 ;
+static const uint8_t P9N2_PU_NPU2_SM3_LOW_WATER_CONFIG_REQ1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM3_LOW_WATER_CONFIG_PRB1 = 36 ;
+static const uint8_t P9N2_PU_NPU2_SM3_LOW_WATER_CONFIG_PRB1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM3_LOW_WATER_CONFIG_MAX_MACHINES = 42 ;
+static const uint8_t P9N2_PU_NPU2_SM3_LOW_WATER_CONFIG_MAX_MACHINES_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM3_LOW_WATER_RESERVED1 = 48 ;
+static const uint8_t P9N2_PU_NPU2_SM3_LOW_WATER_RESERVED1_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM3_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC = 51 ;
+static const uint8_t P9N2_PU_NPU2_SM3_LOW_WATER_CONFIG_INTS = 52 ;
+static const uint8_t P9N2_PU_NPU2_SM3_LOW_WATER_CONFIG_INTS_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM3_LOW_WATER_RESERVED2 = 58 ;
+static const uint8_t P9N2_PU_NPU2_SM3_LOW_WATER_RESERVED2_LEN = 2 ;
+
+static const uint8_t P9N2_PU_NPU0_SM3_LOW_WATER_CONFIG_XATS = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM3_LOW_WATER_CONFIG_XATS_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM3_LOW_WATER_CONFIG_PWR0 = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM3_LOW_WATER_CONFIG_PWR0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM3_LOW_WATER_CONFIG_PWR1 = 12 ;
+static const uint8_t P9N2_PU_NPU0_SM3_LOW_WATER_CONFIG_PWR1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM3_LOW_WATER_CONFIG_REQ0 = 18 ;
+static const uint8_t P9N2_PU_NPU0_SM3_LOW_WATER_CONFIG_REQ0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM3_LOW_WATER_CONFIG_PRB0 = 24 ;
+static const uint8_t P9N2_PU_NPU0_SM3_LOW_WATER_CONFIG_PRB0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM3_LOW_WATER_CONFIG_REQ1 = 30 ;
+static const uint8_t P9N2_PU_NPU0_SM3_LOW_WATER_CONFIG_REQ1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM3_LOW_WATER_CONFIG_PRB1 = 36 ;
+static const uint8_t P9N2_PU_NPU0_SM3_LOW_WATER_CONFIG_PRB1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM3_LOW_WATER_CONFIG_MAX_MACHINES = 42 ;
+static const uint8_t P9N2_PU_NPU0_SM3_LOW_WATER_CONFIG_MAX_MACHINES_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM3_LOW_WATER_RESERVED1 = 48 ;
+static const uint8_t P9N2_PU_NPU0_SM3_LOW_WATER_RESERVED1_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM3_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC = 51 ;
+static const uint8_t P9N2_PU_NPU0_SM3_LOW_WATER_CONFIG_INTS = 52 ;
+static const uint8_t P9N2_PU_NPU0_SM3_LOW_WATER_CONFIG_INTS_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM3_LOW_WATER_RESERVED2 = 58 ;
+static const uint8_t P9N2_PU_NPU0_SM3_LOW_WATER_RESERVED2_LEN = 2 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM0_LOW_WATER_CONFIG_XATS = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_LOW_WATER_CONFIG_XATS_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_LOW_WATER_CONFIG_PWR0 = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_LOW_WATER_CONFIG_PWR0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_LOW_WATER_CONFIG_PWR1 = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_LOW_WATER_CONFIG_PWR1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_LOW_WATER_CONFIG_REQ0 = 18 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_LOW_WATER_CONFIG_REQ0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_LOW_WATER_CONFIG_PRB0 = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_LOW_WATER_CONFIG_PRB0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_LOW_WATER_CONFIG_REQ1 = 30 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_LOW_WATER_CONFIG_REQ1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_LOW_WATER_CONFIG_PRB1 = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_LOW_WATER_CONFIG_PRB1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_LOW_WATER_CONFIG_MAX_MACHINES = 42 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_LOW_WATER_CONFIG_MAX_MACHINES_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_LOW_WATER_RESERVED1 = 48 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_LOW_WATER_RESERVED1_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC = 51 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_LOW_WATER_CONFIG_INTS = 52 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_LOW_WATER_CONFIG_INTS_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_LOW_WATER_RESERVED2 = 58 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_LOW_WATER_RESERVED2_LEN = 2 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM1_LOW_WATER_CONFIG_XATS = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_LOW_WATER_CONFIG_XATS_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_LOW_WATER_CONFIG_PWR0 = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_LOW_WATER_CONFIG_PWR0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_LOW_WATER_CONFIG_PWR1 = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_LOW_WATER_CONFIG_PWR1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_LOW_WATER_CONFIG_REQ0 = 18 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_LOW_WATER_CONFIG_REQ0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_LOW_WATER_CONFIG_PRB0 = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_LOW_WATER_CONFIG_PRB0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_LOW_WATER_CONFIG_REQ1 = 30 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_LOW_WATER_CONFIG_REQ1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_LOW_WATER_CONFIG_PRB1 = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_LOW_WATER_CONFIG_PRB1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_LOW_WATER_CONFIG_MAX_MACHINES = 42 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_LOW_WATER_CONFIG_MAX_MACHINES_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_LOW_WATER_RESERVED1 = 48 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_LOW_WATER_RESERVED1_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC = 51 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_LOW_WATER_CONFIG_INTS = 52 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_LOW_WATER_CONFIG_INTS_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_LOW_WATER_RESERVED2 = 58 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_LOW_WATER_RESERVED2_LEN = 2 ;
+
+static const uint8_t P9N2_PU_NPU2_SM1_LOW_WATER_CONFIG_XATS = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM1_LOW_WATER_CONFIG_XATS_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM1_LOW_WATER_CONFIG_PWR0 = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM1_LOW_WATER_CONFIG_PWR0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM1_LOW_WATER_CONFIG_PWR1 = 12 ;
+static const uint8_t P9N2_PU_NPU2_SM1_LOW_WATER_CONFIG_PWR1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM1_LOW_WATER_CONFIG_REQ0 = 18 ;
+static const uint8_t P9N2_PU_NPU2_SM1_LOW_WATER_CONFIG_REQ0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM1_LOW_WATER_CONFIG_PRB0 = 24 ;
+static const uint8_t P9N2_PU_NPU2_SM1_LOW_WATER_CONFIG_PRB0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM1_LOW_WATER_CONFIG_REQ1 = 30 ;
+static const uint8_t P9N2_PU_NPU2_SM1_LOW_WATER_CONFIG_REQ1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM1_LOW_WATER_CONFIG_PRB1 = 36 ;
+static const uint8_t P9N2_PU_NPU2_SM1_LOW_WATER_CONFIG_PRB1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM1_LOW_WATER_CONFIG_MAX_MACHINES = 42 ;
+static const uint8_t P9N2_PU_NPU2_SM1_LOW_WATER_CONFIG_MAX_MACHINES_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM1_LOW_WATER_RESERVED1 = 48 ;
+static const uint8_t P9N2_PU_NPU2_SM1_LOW_WATER_RESERVED1_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM1_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC = 51 ;
+static const uint8_t P9N2_PU_NPU2_SM1_LOW_WATER_CONFIG_INTS = 52 ;
+static const uint8_t P9N2_PU_NPU2_SM1_LOW_WATER_CONFIG_INTS_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM1_LOW_WATER_RESERVED2 = 58 ;
+static const uint8_t P9N2_PU_NPU2_SM1_LOW_WATER_RESERVED2_LEN = 2 ;
+
+static const uint8_t P9N2_PU_NPU0_CTL_LOW_WATER_CONFIG_XATS = 0 ;
+static const uint8_t P9N2_PU_NPU0_CTL_LOW_WATER_CONFIG_XATS_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_CTL_LOW_WATER_CONFIG_PWR0 = 6 ;
+static const uint8_t P9N2_PU_NPU0_CTL_LOW_WATER_CONFIG_PWR0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_CTL_LOW_WATER_CONFIG_PWR1 = 12 ;
+static const uint8_t P9N2_PU_NPU0_CTL_LOW_WATER_CONFIG_PWR1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_CTL_LOW_WATER_CONFIG_REQ0 = 18 ;
+static const uint8_t P9N2_PU_NPU0_CTL_LOW_WATER_CONFIG_REQ0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_CTL_LOW_WATER_CONFIG_PRB0 = 24 ;
+static const uint8_t P9N2_PU_NPU0_CTL_LOW_WATER_CONFIG_PRB0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_CTL_LOW_WATER_CONFIG_REQ1 = 30 ;
+static const uint8_t P9N2_PU_NPU0_CTL_LOW_WATER_CONFIG_REQ1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_CTL_LOW_WATER_CONFIG_PRB1 = 36 ;
+static const uint8_t P9N2_PU_NPU0_CTL_LOW_WATER_CONFIG_PRB1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_CTL_LOW_WATER_CONFIG_MAX_MACHINES = 42 ;
+static const uint8_t P9N2_PU_NPU0_CTL_LOW_WATER_CONFIG_MAX_MACHINES_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_CTL_LOW_WATER_RESERVED1 = 48 ;
+static const uint8_t P9N2_PU_NPU0_CTL_LOW_WATER_RESERVED1_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU0_CTL_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC = 51 ;
+static const uint8_t P9N2_PU_NPU0_CTL_LOW_WATER_CONFIG_INTS = 52 ;
+static const uint8_t P9N2_PU_NPU0_CTL_LOW_WATER_CONFIG_INTS_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_CTL_LOW_WATER_RESERVED2 = 58 ;
+static const uint8_t P9N2_PU_NPU0_CTL_LOW_WATER_RESERVED2_LEN = 2 ;
+
+static const uint8_t P9N2_PU_NPU2_SM0_LOW_WATER_CONFIG_XATS = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM0_LOW_WATER_CONFIG_XATS_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM0_LOW_WATER_CONFIG_PWR0 = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM0_LOW_WATER_CONFIG_PWR0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM0_LOW_WATER_CONFIG_PWR1 = 12 ;
+static const uint8_t P9N2_PU_NPU2_SM0_LOW_WATER_CONFIG_PWR1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM0_LOW_WATER_CONFIG_REQ0 = 18 ;
+static const uint8_t P9N2_PU_NPU2_SM0_LOW_WATER_CONFIG_REQ0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM0_LOW_WATER_CONFIG_PRB0 = 24 ;
+static const uint8_t P9N2_PU_NPU2_SM0_LOW_WATER_CONFIG_PRB0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM0_LOW_WATER_CONFIG_REQ1 = 30 ;
+static const uint8_t P9N2_PU_NPU2_SM0_LOW_WATER_CONFIG_REQ1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM0_LOW_WATER_CONFIG_PRB1 = 36 ;
+static const uint8_t P9N2_PU_NPU2_SM0_LOW_WATER_CONFIG_PRB1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM0_LOW_WATER_CONFIG_MAX_MACHINES = 42 ;
+static const uint8_t P9N2_PU_NPU2_SM0_LOW_WATER_CONFIG_MAX_MACHINES_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM0_LOW_WATER_RESERVED1 = 48 ;
+static const uint8_t P9N2_PU_NPU2_SM0_LOW_WATER_RESERVED1_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM0_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC = 51 ;
+static const uint8_t P9N2_PU_NPU2_SM0_LOW_WATER_CONFIG_INTS = 52 ;
+static const uint8_t P9N2_PU_NPU2_SM0_LOW_WATER_CONFIG_INTS_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM0_LOW_WATER_RESERVED2 = 58 ;
+static const uint8_t P9N2_PU_NPU2_SM0_LOW_WATER_RESERVED2_LEN = 2 ;
+
+static const uint8_t P9N2_PU_NPU2_CTL_LOW_WATER_CONFIG_XATS = 0 ;
+static const uint8_t P9N2_PU_NPU2_CTL_LOW_WATER_CONFIG_XATS_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_CTL_LOW_WATER_CONFIG_PWR0 = 6 ;
+static const uint8_t P9N2_PU_NPU2_CTL_LOW_WATER_CONFIG_PWR0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_CTL_LOW_WATER_CONFIG_PWR1 = 12 ;
+static const uint8_t P9N2_PU_NPU2_CTL_LOW_WATER_CONFIG_PWR1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_CTL_LOW_WATER_CONFIG_REQ0 = 18 ;
+static const uint8_t P9N2_PU_NPU2_CTL_LOW_WATER_CONFIG_REQ0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_CTL_LOW_WATER_CONFIG_PRB0 = 24 ;
+static const uint8_t P9N2_PU_NPU2_CTL_LOW_WATER_CONFIG_PRB0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_CTL_LOW_WATER_CONFIG_REQ1 = 30 ;
+static const uint8_t P9N2_PU_NPU2_CTL_LOW_WATER_CONFIG_REQ1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_CTL_LOW_WATER_CONFIG_PRB1 = 36 ;
+static const uint8_t P9N2_PU_NPU2_CTL_LOW_WATER_CONFIG_PRB1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_CTL_LOW_WATER_CONFIG_MAX_MACHINES = 42 ;
+static const uint8_t P9N2_PU_NPU2_CTL_LOW_WATER_CONFIG_MAX_MACHINES_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_CTL_LOW_WATER_RESERVED1 = 48 ;
+static const uint8_t P9N2_PU_NPU2_CTL_LOW_WATER_RESERVED1_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU2_CTL_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC = 51 ;
+static const uint8_t P9N2_PU_NPU2_CTL_LOW_WATER_CONFIG_INTS = 52 ;
+static const uint8_t P9N2_PU_NPU2_CTL_LOW_WATER_CONFIG_INTS_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_CTL_LOW_WATER_RESERVED2 = 58 ;
+static const uint8_t P9N2_PU_NPU2_CTL_LOW_WATER_RESERVED2_LEN = 2 ;
+
+static const uint8_t P9N2_PU_NPU0_SM1_LOW_WATER_CONFIG_XATS = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM1_LOW_WATER_CONFIG_XATS_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM1_LOW_WATER_CONFIG_PWR0 = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM1_LOW_WATER_CONFIG_PWR0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM1_LOW_WATER_CONFIG_PWR1 = 12 ;
+static const uint8_t P9N2_PU_NPU0_SM1_LOW_WATER_CONFIG_PWR1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM1_LOW_WATER_CONFIG_REQ0 = 18 ;
+static const uint8_t P9N2_PU_NPU0_SM1_LOW_WATER_CONFIG_REQ0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM1_LOW_WATER_CONFIG_PRB0 = 24 ;
+static const uint8_t P9N2_PU_NPU0_SM1_LOW_WATER_CONFIG_PRB0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM1_LOW_WATER_CONFIG_REQ1 = 30 ;
+static const uint8_t P9N2_PU_NPU0_SM1_LOW_WATER_CONFIG_REQ1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM1_LOW_WATER_CONFIG_PRB1 = 36 ;
+static const uint8_t P9N2_PU_NPU0_SM1_LOW_WATER_CONFIG_PRB1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM1_LOW_WATER_CONFIG_MAX_MACHINES = 42 ;
+static const uint8_t P9N2_PU_NPU0_SM1_LOW_WATER_CONFIG_MAX_MACHINES_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM1_LOW_WATER_RESERVED1 = 48 ;
+static const uint8_t P9N2_PU_NPU0_SM1_LOW_WATER_RESERVED1_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM1_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC = 51 ;
+static const uint8_t P9N2_PU_NPU0_SM1_LOW_WATER_CONFIG_INTS = 52 ;
+static const uint8_t P9N2_PU_NPU0_SM1_LOW_WATER_CONFIG_INTS_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM1_LOW_WATER_RESERVED2 = 58 ;
+static const uint8_t P9N2_PU_NPU0_SM1_LOW_WATER_RESERVED2_LEN = 2 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_CTL_LOW_WATER_CONFIG_XATS = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_LOW_WATER_CONFIG_XATS_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_LOW_WATER_CONFIG_PWR0 = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_LOW_WATER_CONFIG_PWR0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_LOW_WATER_CONFIG_PWR1 = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_LOW_WATER_CONFIG_PWR1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_LOW_WATER_CONFIG_REQ0 = 18 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_LOW_WATER_CONFIG_REQ0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_LOW_WATER_CONFIG_PRB0 = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_LOW_WATER_CONFIG_PRB0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_LOW_WATER_CONFIG_REQ1 = 30 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_LOW_WATER_CONFIG_REQ1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_LOW_WATER_CONFIG_PRB1 = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_LOW_WATER_CONFIG_PRB1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_LOW_WATER_CONFIG_MAX_MACHINES = 42 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_LOW_WATER_CONFIG_MAX_MACHINES_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_LOW_WATER_RESERVED1 = 48 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_LOW_WATER_RESERVED1_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC = 51 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_LOW_WATER_CONFIG_INTS = 52 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_LOW_WATER_CONFIG_INTS_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_LOW_WATER_RESERVED2 = 58 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_LOW_WATER_RESERVED2_LEN = 2 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM3_LOW_WATER_CONFIG_XATS = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_LOW_WATER_CONFIG_XATS_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_LOW_WATER_CONFIG_PWR0 = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_LOW_WATER_CONFIG_PWR0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_LOW_WATER_CONFIG_PWR1 = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_LOW_WATER_CONFIG_PWR1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_LOW_WATER_CONFIG_REQ0 = 18 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_LOW_WATER_CONFIG_REQ0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_LOW_WATER_CONFIG_PRB0 = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_LOW_WATER_CONFIG_PRB0_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_LOW_WATER_CONFIG_REQ1 = 30 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_LOW_WATER_CONFIG_REQ1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_LOW_WATER_CONFIG_PRB1 = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_LOW_WATER_CONFIG_PRB1_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_LOW_WATER_CONFIG_MAX_MACHINES = 42 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_LOW_WATER_CONFIG_MAX_MACHINES_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_LOW_WATER_RESERVED1 = 48 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_LOW_WATER_RESERVED1_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC = 51 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_LOW_WATER_CONFIG_INTS = 52 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_LOW_WATER_CONFIG_INTS_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_LOW_WATER_RESERVED2 = 58 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_LOW_WATER_RESERVED2_LEN = 2 ;
+
+static const uint8_t P9N2_PU_NPU2_NTL0_LPCTH_CONFIG_BUSY_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_LPCTH_CONFIG_WINDOW_SELECT = 1 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_LPCTH_CONFIG_WINDOW_SELECT_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_LPCTH_CONFIG_THRESH_0 = 4 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_LPCTH_CONFIG_THRESH_0_LEN = 10 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_LPCTH_CONFIG_THRESH_1 = 14 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_LPCTH_CONFIG_THRESH_1_LEN = 10 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_LPCTH_CONFIG_THRESH_2 = 24 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_LPCTH_CONFIG_THRESH_2_LEN = 10 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_LPCTH_CONFIG_RESERVED1 = 34 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_LPCTH_CONFIG_RESERVED1_LEN = 2 ;
+
+static const uint8_t P9N2_NV_LPCTH_CONFIG_BUSY_ENABLE = 0 ;
+static const uint8_t P9N2_NV_LPCTH_CONFIG_WINDOW_SELECT = 1 ;
+static const uint8_t P9N2_NV_LPCTH_CONFIG_WINDOW_SELECT_LEN = 3 ;
+static const uint8_t P9N2_NV_LPCTH_CONFIG_THRESH_0 = 4 ;
+static const uint8_t P9N2_NV_LPCTH_CONFIG_THRESH_0_LEN = 10 ;
+static const uint8_t P9N2_NV_LPCTH_CONFIG_THRESH_1 = 14 ;
+static const uint8_t P9N2_NV_LPCTH_CONFIG_THRESH_1_LEN = 10 ;
+static const uint8_t P9N2_NV_LPCTH_CONFIG_THRESH_2 = 24 ;
+static const uint8_t P9N2_NV_LPCTH_CONFIG_THRESH_2_LEN = 10 ;
+static const uint8_t P9N2_NV_LPCTH_CONFIG_RESERVED1 = 34 ;
+static const uint8_t P9N2_NV_LPCTH_CONFIG_RESERVED1_LEN = 2 ;
+
+static const uint8_t P9N2_PU_LPC_BASE_REG_BASE = 8 ;
+static const uint8_t P9N2_PU_LPC_BASE_REG_BASE_LEN = 24 ;
+static const uint8_t P9N2_PU_LPC_BASE_REG_DISABLE = 63 ;
+
+static const uint8_t P9N2_PU_LPC_CMD_REG_RNW = 0 ;
+static const uint8_t P9N2_PU_LPC_CMD_REG_SIZE = 5 ;
+static const uint8_t P9N2_PU_LPC_CMD_REG_SIZE_LEN = 7 ;
+static const uint8_t P9N2_PU_LPC_CMD_REG_ADR = 32 ;
+static const uint8_t P9N2_PU_LPC_CMD_REG_ADR_LEN = 32 ;
+
+static const uint8_t P9N2_PU_LPC_DATA_REG_DATA = 0 ;
+static const uint8_t P9N2_PU_LPC_DATA_REG_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_PU_LPC_STATUS_REG_DONE = 0 ;
+static const uint8_t P9N2_PU_LPC_STATUS_REG_VALID = 10 ;
+static const uint8_t P9N2_PU_LPC_STATUS_REG_ACK = 11 ;
+
+static const uint8_t P9N2_PHB_MASK_REG_AIB_COMMAND_INVALID = 0 ;
+static const uint8_t P9N2_PHB_MASK_REG_AIB_ADDRESSING_ERROR = 1 ;
+static const uint8_t P9N2_PHB_MASK_REG_AIB_ACCESS_ERROR = 2 ;
+static const uint8_t P9N2_PHB_MASK_REG_PAPR_OUTBOUND_INJECTION_ERROR_TRIGGERED = 3 ;
+static const uint8_t P9N2_PHB_MASK_REG_AIB_FATAL_CLASS_ERROR = 4 ;
+static const uint8_t P9N2_PHB_MASK_REG_AIB_INF_CLASS_ERROR = 5 ;
+static const uint8_t P9N2_PHB_MASK_REG_PE_STOP_STATE_ERROR = 6 ;
+static const uint8_t P9N2_PHB_MASK_REG_AIB_DAT_ERR_SIGNALED = 7 ;
+static const uint8_t P9N2_PHB_MASK_REG_OUT_COMMON_ARRAY_FATAL_ERROR = 8 ;
+static const uint8_t P9N2_PHB_MASK_REG_OUT_COMMON_LATCH_FATAL_ERROR = 9 ;
+static const uint8_t P9N2_PHB_MASK_REG_OUT_COMMON_LOGIC_FATAL_ERROR = 10 ;
+static const uint8_t P9N2_PHB_MASK_REG_BLIF_OUT_INTERFACE_PARITY_ERROR = 11 ;
+static const uint8_t P9N2_PHB_MASK_REG_PCIE_CFG_WRITE_CA_OR_UR_RESPONSE = 12 ;
+static const uint8_t P9N2_PHB_MASK_REG_MMIO_REQUEST_TIMEOUT = 13 ;
+static const uint8_t P9N2_PHB_MASK_REG_OUT_RRB_SOURCED_ERROR = 14 ;
+static const uint8_t P9N2_PHB_MASK_REG_CFG_LOGIC_SIGNALED_ERROR = 15 ;
+static const uint8_t P9N2_PHB_MASK_REG_RSB_REG_REQUEST_ADDRESS_ERROR = 16 ;
+static const uint8_t P9N2_PHB_MASK_REG_RSB_FDA_FATAL_ERROR = 17 ;
+static const uint8_t P9N2_PHB_MASK_REG_RSB_FDA_INF_ERROR = 18 ;
+static const uint8_t P9N2_PHB_MASK_REG_RSB_FDB_FATAL_ERROR = 19 ;
+static const uint8_t P9N2_PHB_MASK_REG_RSB_FDB_INF_ERROR = 20 ;
+static const uint8_t P9N2_PHB_MASK_REG_RSB_ERR_FATAL_ERROR = 21 ;
+static const uint8_t P9N2_PHB_MASK_REG_RSB_ERR_INF_ERROR = 22 ;
+static const uint8_t P9N2_PHB_MASK_REG_RSB_DBG_FATAL_ERROR = 23 ;
+static const uint8_t P9N2_PHB_MASK_REG_RSB_DBG_INF_ERROR = 24 ;
+static const uint8_t P9N2_PHB_MASK_REG_RSB_PCIE_REQUEST_ACCESS_ERROR = 25 ;
+static const uint8_t P9N2_PHB_MASK_REG_RSB_BUS_LOGIC_ERROR = 26 ;
+static const uint8_t P9N2_PHB_MASK_REG_RSB_UVI_FATAL_ERROR = 27 ;
+static const uint8_t P9N2_PHB_MASK_REG_RSB_UVI_INF_ERROR = 28 ;
+static const uint8_t P9N2_PHB_MASK_REG_SCOM_FATAL_ERROR = 29 ;
+static const uint8_t P9N2_PHB_MASK_REG_SCOM_INF_ERROR = 30 ;
+static const uint8_t P9N2_PHB_MASK_REG_PCIE_MACRO_ERROR_ACTIVE_STATUS = 31 ;
+static const uint8_t P9N2_PHB_MASK_REG_ARB_IODA_FATAL_ERROR = 32 ;
+static const uint8_t P9N2_PHB_MASK_REG_ARB_MSI_PE_MATCH_ERROR = 33 ;
+static const uint8_t P9N2_PHB_MASK_REG_ARB_MSI_ADDRESS_ERROR = 34 ;
+static const uint8_t P9N2_PHB_MASK_REG_ARB_TVT_ERROR = 35 ;
+static const uint8_t P9N2_PHB_MASK_REG_ARB_RCVD_FATAL_ERROR_MSG = 36 ;
+static const uint8_t P9N2_PHB_MASK_REG_ARB_RCVD_NONFATAL_ERROR_MSG = 37 ;
+static const uint8_t P9N2_PHB_MASK_REG_ARB_RCVD_CORRECTIBLE_ERROR_MSG = 38 ;
+static const uint8_t P9N2_PHB_MASK_REG_PAPR_INBOUND_INJECTION_ERROR_TRIGGERED = 39 ;
+static const uint8_t P9N2_PHB_MASK_REG_ARB_COMMON_FATAL_ERROR = 40 ;
+static const uint8_t P9N2_PHB_MASK_REG_ARB_TABLE_BAR_DISABLED_ERROR = 41 ;
+static const uint8_t P9N2_PHB_MASK_REG_ARB_BLIF_COMPLETION_ERROR = 42 ;
+static const uint8_t P9N2_PHB_MASK_REG_ARB_PCT_TIMEOUT_ERROR = 43 ;
+static const uint8_t P9N2_PHB_MASK_REG_ARB_ECC_CORRECTABLE_ERROR = 44 ;
+static const uint8_t P9N2_PHB_MASK_REG_ARB_ECC_UNCORRECTABLE_ERROR = 45 ;
+static const uint8_t P9N2_PHB_MASK_REG_ARB_TLP_POISON_SIGNALED = 46 ;
+static const uint8_t P9N2_PHB_MASK_REG_ARB_RTT_PENUM_INVALID_ERROR = 47 ;
+static const uint8_t P9N2_PHB_MASK_REG_MRG_COMMON_FATAL_ERROR = 48 ;
+static const uint8_t P9N2_PHB_MASK_REG_MRG_TABLE_BAR_DISABLED_ERROR = 49 ;
+static const uint8_t P9N2_PHB_MASK_REG_MRG_ECC_CORRECTABLE_ERROR = 50 ;
+static const uint8_t P9N2_PHB_MASK_REG_MRG_ECC_UNCORRECTABLE_ERROR = 51 ;
+static const uint8_t P9N2_PHB_MASK_REG_MRG_AIB2_TX_TIMEOUT_ERROR = 52 ;
+static const uint8_t P9N2_PHB_MASK_REG_MRG_MRT_ERROR = 53 ;
+static const uint8_t P9N2_PHB_MASK_REG_MRG_RESERVED01 = 54 ;
+static const uint8_t P9N2_PHB_MASK_REG_MRG_RESERVED02 = 55 ;
+static const uint8_t P9N2_PHB_MASK_REG_TCE_IODA_PAGE_ACCESS_ERROR = 56 ;
+static const uint8_t P9N2_PHB_MASK_REG_TCE_REQUEST_TIMEOUT_ERROR = 57 ;
+static const uint8_t P9N2_PHB_MASK_REG_TCE_UNEXPECTED_RESPONSE_ERROR = 58 ;
+static const uint8_t P9N2_PHB_MASK_REG_TCE_COMMON_FATAL_ERRORS = 59 ;
+static const uint8_t P9N2_PHB_MASK_REG_TCE_ECC_CORRECTABLE_ERROR = 60 ;
+static const uint8_t P9N2_PHB_MASK_REG_TCE_ECC_UNCORRECTABLE_ERROR = 61 ;
+static const uint8_t P9N2_PHB_MASK_REG_TCE_RESERVED01 = 62 ;
+static const uint8_t P9N2_PHB_MASK_REG_LEM_FIR_INTERNAL_PARITY_ERROR = 63 ;
+
+static const uint8_t P9N2_PU_MCC_FIR_REG_MCD_ARRAY_ECC_UE_ERR = 0 ;
+static const uint8_t P9N2_PU_MCC_FIR_REG_MCD_ARRAY_ECC_CE_ERR = 1 ;
+static const uint8_t P9N2_PU_MCC_FIR_REG_MCD_PB_ADDR_PARITY_ERR = 2 ;
+static const uint8_t P9N2_PU_MCC_FIR_REG_MCD_SM_OR_CASE_ERR = 3 ;
+static const uint8_t P9N2_PU_MCC_FIR_REG_MCD_CL_PROBE_PB_HANG_ERR = 4 ;
+static const uint8_t P9N2_PU_MCC_FIR_REG_MCD_CRESP_ADDR_ERR = 5 ;
+static const uint8_t P9N2_PU_MCC_FIR_REG_MCD_UNSOLICITED_CRESP_ERR = 6 ;
+static const uint8_t P9N2_PU_MCC_FIR_REG_MCD_TTAG_PARITY_ERR = 7 ;
+static const uint8_t P9N2_PU_MCC_FIR_REG_MCD_UPDATE_ERR = 8 ;
+static const uint8_t P9N2_PU_MCC_FIR_REG_MCD_ACK_DEAD_CRESP_ERR = 9 ;
+static const uint8_t P9N2_PU_MCC_FIR_REG_MCD_SCOM_ERR = 10 ;
+static const uint8_t P9N2_PU_MCC_FIR_REG_MCD_SCOM_ERR_DUP = 11 ;
+
+static const uint8_t P9N2_PU_MCD1_MCC_FIR_REG_MCD_ARRAY_ECC_UE_ERR = 0 ;
+static const uint8_t P9N2_PU_MCD1_MCC_FIR_REG_MCD_ARRAY_ECC_CE_ERR = 1 ;
+static const uint8_t P9N2_PU_MCD1_MCC_FIR_REG_MCD_PB_ADDR_PARITY_ERR = 2 ;
+static const uint8_t P9N2_PU_MCD1_MCC_FIR_REG_MCD_SM_OR_CASE_ERR = 3 ;
+static const uint8_t P9N2_PU_MCD1_MCC_FIR_REG_MCD_CL_PROBE_PB_HANG_ERR = 4 ;
+static const uint8_t P9N2_PU_MCD1_MCC_FIR_REG_MCD_CRESP_ADDR_ERR = 5 ;
+static const uint8_t P9N2_PU_MCD1_MCC_FIR_REG_MCD_UNSOLICITED_CRESP_ERR = 6 ;
+static const uint8_t P9N2_PU_MCD1_MCC_FIR_REG_MCD_TTAG_PARITY_ERR = 7 ;
+static const uint8_t P9N2_PU_MCD1_MCC_FIR_REG_MCD_UPDATE_ERR = 8 ;
+static const uint8_t P9N2_PU_MCD1_MCC_FIR_REG_MCD_ACK_DEAD_CRESP_ERR = 9 ;
+static const uint8_t P9N2_PU_MCD1_MCC_FIR_REG_MCD_SCOM_ERR = 10 ;
+static const uint8_t P9N2_PU_MCD1_MCC_FIR_REG_MCD_SCOM_ERR_DUP = 11 ;
+
+static const uint8_t P9N2_PU_MCD_DBG_TRACE_ENABLE = 3 ;
+static const uint8_t P9N2_PU_MCD_DBG_TRACE_SELECT = 4 ;
+static const uint8_t P9N2_PU_MCD_DBG_TRACE_SELECT_LEN = 4 ;
+static const uint8_t P9N2_PU_MCD_DBG_ERR_INJ_ENABLE = 8 ;
+static const uint8_t P9N2_PU_MCD_DBG_ERR_INJ_TYPE = 9 ;
+static const uint8_t P9N2_PU_MCD_DBG_ERR_INJ_ACTION = 10 ;
+static const uint8_t P9N2_PU_MCD_DBG_ERR_INJ_ARRAY_SEL = 11 ;
+static const uint8_t P9N2_PU_MCD_DBG_ERR_INJ_ARRAY_SEL_LEN = 4 ;
+static const uint8_t P9N2_PU_MCD_DBG_ERR_INJ_STATUS = 15 ;
+static const uint8_t P9N2_PU_MCD_DBG_PMU_ENABLE = 19 ;
+static const uint8_t P9N2_PU_MCD_DBG_PMU_SELECT_LOW = 20 ;
+static const uint8_t P9N2_PU_MCD_DBG_PMU_SELECT_LOW_LEN = 3 ;
+static const uint8_t P9N2_PU_MCD_DBG_PMU_SELECT_HIGH = 23 ;
+static const uint8_t P9N2_PU_MCD_DBG_PMU_SELECT_HIGH_LEN = 3 ;
+static const uint8_t P9N2_PU_MCD_DBG_PMU_BUS_ENABLE = 32 ;
+static const uint8_t P9N2_PU_MCD_DBG_PMU_BUS_ENABLE_LEN = 16 ;
+static const uint8_t P9N2_PU_MCD_DBG_RECOVER_ADDR = 48 ;
+static const uint8_t P9N2_PU_MCD_DBG_RECOVER_ADDR_LEN = 15 ;
+
+static const uint8_t P9N2_PU_MCD1_MCD_DBG_TRACE_ENABLE = 3 ;
+static const uint8_t P9N2_PU_MCD1_MCD_DBG_TRACE_SELECT = 4 ;
+static const uint8_t P9N2_PU_MCD1_MCD_DBG_TRACE_SELECT_LEN = 4 ;
+static const uint8_t P9N2_PU_MCD1_MCD_DBG_ERR_INJ_ENABLE = 8 ;
+static const uint8_t P9N2_PU_MCD1_MCD_DBG_ERR_INJ_TYPE = 9 ;
+static const uint8_t P9N2_PU_MCD1_MCD_DBG_ERR_INJ_ACTION = 10 ;
+static const uint8_t P9N2_PU_MCD1_MCD_DBG_ERR_INJ_ARRAY_SEL = 11 ;
+static const uint8_t P9N2_PU_MCD1_MCD_DBG_ERR_INJ_ARRAY_SEL_LEN = 4 ;
+static const uint8_t P9N2_PU_MCD1_MCD_DBG_ERR_INJ_STATUS = 15 ;
+static const uint8_t P9N2_PU_MCD1_MCD_DBG_PMU_ENABLE = 19 ;
+static const uint8_t P9N2_PU_MCD1_MCD_DBG_PMU_SELECT_LOW = 20 ;
+static const uint8_t P9N2_PU_MCD1_MCD_DBG_PMU_SELECT_LOW_LEN = 3 ;
+static const uint8_t P9N2_PU_MCD1_MCD_DBG_PMU_SELECT_HIGH = 23 ;
+static const uint8_t P9N2_PU_MCD1_MCD_DBG_PMU_SELECT_HIGH_LEN = 3 ;
+static const uint8_t P9N2_PU_MCD1_MCD_DBG_PMU_BUS_ENABLE = 32 ;
+static const uint8_t P9N2_PU_MCD1_MCD_DBG_PMU_BUS_ENABLE_LEN = 16 ;
+static const uint8_t P9N2_PU_MCD1_MCD_DBG_RECOVER_ADDR = 48 ;
+static const uint8_t P9N2_PU_MCD1_MCD_DBG_RECOVER_ADDR_LEN = 15 ;
+
+static const uint8_t P9N2_PU_MCD_ECAP_ECC_CLEAR = 0 ;
+static const uint8_t P9N2_PU_MCD_ECAP_ECC_UE = 2 ;
+static const uint8_t P9N2_PU_MCD_ECAP_ECC_CE = 3 ;
+static const uint8_t P9N2_PU_MCD_ECAP_ECC_ERROR_COUNT = 4 ;
+static const uint8_t P9N2_PU_MCD_ECAP_ECC_ERROR_COUNT_LEN = 4 ;
+static const uint8_t P9N2_PU_MCD_ECAP_ECC_ERROR_ADDR = 10 ;
+static const uint8_t P9N2_PU_MCD_ECAP_ECC_ERROR_ADDR_LEN = 14 ;
+static const uint8_t P9N2_PU_MCD_ECAP_ECC_SYNDROME = 24 ;
+static const uint8_t P9N2_PU_MCD_ECAP_ECC_SYNDROME_LEN = 8 ;
+static const uint8_t P9N2_PU_MCD_ECAP_SLICE0_CFG_ECC_UE_ERR = 33 ;
+static const uint8_t P9N2_PU_MCD_ECAP_SLICE0_CFG_ECC_CE_ERR = 34 ;
+static const uint8_t P9N2_PU_MCD_ECAP_SLICE1_CFG_ECC_UE_ERR = 35 ;
+static const uint8_t P9N2_PU_MCD_ECAP_SLICE1_CFG_ECC_CE_ERR = 36 ;
+static const uint8_t P9N2_PU_MCD_ECAP_SLICE2_CFG_ECC_UE_ERR = 37 ;
+static const uint8_t P9N2_PU_MCD_ECAP_SLICE2_CFG_ECC_CE_ERR = 38 ;
+static const uint8_t P9N2_PU_MCD_ECAP_SLICE3_CFG_ECC_UE_ERR = 39 ;
+static const uint8_t P9N2_PU_MCD_ECAP_SLICE3_CFG_ECC_CE_ERR = 40 ;
+static const uint8_t P9N2_PU_MCD_ECAP_PRESP_RTY_OTHER = 41 ;
+static const uint8_t P9N2_PU_MCD_ECAP_REC_SM_ERROR_ERR = 42 ;
+static const uint8_t P9N2_PU_MCD_ECAP_REC_PB_SM_ERROR_ERR = 43 ;
+static const uint8_t P9N2_PU_MCD_ECAP_ADDR_ERROR_PULSE = 44 ;
+static const uint8_t P9N2_PU_MCD_ECAP_RCMD0_ADDR_PARITY_ERROR = 45 ;
+static const uint8_t P9N2_PU_MCD_ECAP_RCMD1_ADDR_PARITY_ERROR = 46 ;
+static const uint8_t P9N2_PU_MCD_ECAP_RCMD2_ADDR_PARITY_ERROR = 47 ;
+static const uint8_t P9N2_PU_MCD_ECAP_RCMD3_ADDR_PARITY_ERROR = 48 ;
+static const uint8_t P9N2_PU_MCD_ECAP_WARB_INVALID_CASE_ERROR = 49 ;
+static const uint8_t P9N2_PU_MCD_ECAP_INVALID_CRESP_ERROR = 50 ;
+static const uint8_t P9N2_PU_MCD_ECAP_TTAG_PARITY_ERROR = 51 ;
+static const uint8_t P9N2_PU_MCD_ECAP_RDADDR_ARB_BAD_HAND = 52 ;
+static const uint8_t P9N2_PU_MCD_ECAP_RDWR_UPDATE_ERROR = 53 ;
+static const uint8_t P9N2_PU_MCD_ECAP_REC_UPDATE_ERROR = 54 ;
+static const uint8_t P9N2_PU_MCD_ECAP_REC_ACK_DEAD_ERROR = 55 ;
+
+static const uint8_t P9N2_PU_MCD1_MCD_ECAP_ECC_CLEAR = 0 ;
+static const uint8_t P9N2_PU_MCD1_MCD_ECAP_ECC_UE = 2 ;
+static const uint8_t P9N2_PU_MCD1_MCD_ECAP_ECC_CE = 3 ;
+static const uint8_t P9N2_PU_MCD1_MCD_ECAP_ECC_ERROR_COUNT = 4 ;
+static const uint8_t P9N2_PU_MCD1_MCD_ECAP_ECC_ERROR_COUNT_LEN = 4 ;
+static const uint8_t P9N2_PU_MCD1_MCD_ECAP_ECC_ERROR_ADDR = 10 ;
+static const uint8_t P9N2_PU_MCD1_MCD_ECAP_ECC_ERROR_ADDR_LEN = 14 ;
+static const uint8_t P9N2_PU_MCD1_MCD_ECAP_ECC_SYNDROME = 24 ;
+static const uint8_t P9N2_PU_MCD1_MCD_ECAP_ECC_SYNDROME_LEN = 8 ;
+static const uint8_t P9N2_PU_MCD1_MCD_ECAP_SLICE0_CFG_ECC_UE_ERR = 33 ;
+static const uint8_t P9N2_PU_MCD1_MCD_ECAP_SLICE0_CFG_ECC_CE_ERR = 34 ;
+static const uint8_t P9N2_PU_MCD1_MCD_ECAP_SLICE1_CFG_ECC_UE_ERR = 35 ;
+static const uint8_t P9N2_PU_MCD1_MCD_ECAP_SLICE1_CFG_ECC_CE_ERR = 36 ;
+static const uint8_t P9N2_PU_MCD1_MCD_ECAP_SLICE2_CFG_ECC_UE_ERR = 37 ;
+static const uint8_t P9N2_PU_MCD1_MCD_ECAP_SLICE2_CFG_ECC_CE_ERR = 38 ;
+static const uint8_t P9N2_PU_MCD1_MCD_ECAP_SLICE3_CFG_ECC_UE_ERR = 39 ;
+static const uint8_t P9N2_PU_MCD1_MCD_ECAP_SLICE3_CFG_ECC_CE_ERR = 40 ;
+static const uint8_t P9N2_PU_MCD1_MCD_ECAP_PRESP_RTY_OTHER = 41 ;
+static const uint8_t P9N2_PU_MCD1_MCD_ECAP_REC_SM_ERROR_ERR = 42 ;
+static const uint8_t P9N2_PU_MCD1_MCD_ECAP_REC_PB_SM_ERROR_ERR = 43 ;
+static const uint8_t P9N2_PU_MCD1_MCD_ECAP_ADDR_ERROR_PULSE = 44 ;
+static const uint8_t P9N2_PU_MCD1_MCD_ECAP_RCMD0_ADDR_PARITY_ERROR = 45 ;
+static const uint8_t P9N2_PU_MCD1_MCD_ECAP_RCMD1_ADDR_PARITY_ERROR = 46 ;
+static const uint8_t P9N2_PU_MCD1_MCD_ECAP_RCMD2_ADDR_PARITY_ERROR = 47 ;
+static const uint8_t P9N2_PU_MCD1_MCD_ECAP_RCMD3_ADDR_PARITY_ERROR = 48 ;
+static const uint8_t P9N2_PU_MCD1_MCD_ECAP_WARB_INVALID_CASE_ERROR = 49 ;
+static const uint8_t P9N2_PU_MCD1_MCD_ECAP_INVALID_CRESP_ERROR = 50 ;
+static const uint8_t P9N2_PU_MCD1_MCD_ECAP_TTAG_PARITY_ERROR = 51 ;
+static const uint8_t P9N2_PU_MCD1_MCD_ECAP_RDADDR_ARB_BAD_HAND = 52 ;
+static const uint8_t P9N2_PU_MCD1_MCD_ECAP_RDWR_UPDATE_ERROR = 53 ;
+static const uint8_t P9N2_PU_MCD1_MCD_ECAP_REC_UPDATE_ERROR = 54 ;
+static const uint8_t P9N2_PU_MCD1_MCD_ECAP_REC_ACK_DEAD_ERROR = 55 ;
+
+static const uint8_t P9N2_PU_MCD_FIR_ACTION0_REG_ACTION0 = 0 ;
+static const uint8_t P9N2_PU_MCD_FIR_ACTION0_REG_ACTION0_LEN = 12 ;
+
+static const uint8_t P9N2_PU_MCD1_MCD_FIR_ACTION0_REG_ACTION0 = 0 ;
+static const uint8_t P9N2_PU_MCD1_MCD_FIR_ACTION0_REG_ACTION0_LEN = 12 ;
+
+static const uint8_t P9N2_PU_MCD_FIR_ACTION1_REG_ACTION1 = 0 ;
+static const uint8_t P9N2_PU_MCD_FIR_ACTION1_REG_ACTION1_LEN = 12 ;
+
+static const uint8_t P9N2_PU_MCD1_MCD_FIR_ACTION1_REG_ACTION1 = 0 ;
+static const uint8_t P9N2_PU_MCD1_MCD_FIR_ACTION1_REG_ACTION1_LEN = 12 ;
+
+static const uint8_t P9N2_PU_MCD_FIR_MASK_REG_ARRAY_ECC_UE = 0 ;
+static const uint8_t P9N2_PU_MCD_FIR_MASK_REG_ARRAY_ECC_CE = 1 ;
+static const uint8_t P9N2_PU_MCD_FIR_MASK_REG_PB_ADDR_PARITY = 2 ;
+static const uint8_t P9N2_PU_MCD_FIR_MASK_REG_SM_OR_CASE = 3 ;
+static const uint8_t P9N2_PU_MCD_FIR_MASK_REG_CL_PROBE_PB_HANG = 4 ;
+static const uint8_t P9N2_PU_MCD_FIR_MASK_REG_CRESP_ADDR = 5 ;
+static const uint8_t P9N2_PU_MCD_FIR_MASK_REG_UNSOLICITED_CRESP = 6 ;
+static const uint8_t P9N2_PU_MCD_FIR_MASK_REG_TTAG_PARITY = 7 ;
+static const uint8_t P9N2_PU_MCD_FIR_MASK_REG_UPDATE_ERR = 8 ;
+static const uint8_t P9N2_PU_MCD_FIR_MASK_REG_ACK_DEAD_CRESP = 9 ;
+static const uint8_t P9N2_PU_MCD_FIR_MASK_REG_SCOM_ERR = 10 ;
+static const uint8_t P9N2_PU_MCD_FIR_MASK_REG_SCOM_ERR_DUP = 11 ;
+
+static const uint8_t P9N2_PU_MCD1_MCD_FIR_MASK_REG_ARRAY_ECC_UE = 0 ;
+static const uint8_t P9N2_PU_MCD1_MCD_FIR_MASK_REG_ARRAY_ECC_CE = 1 ;
+static const uint8_t P9N2_PU_MCD1_MCD_FIR_MASK_REG_PB_ADDR_PARITY = 2 ;
+static const uint8_t P9N2_PU_MCD1_MCD_FIR_MASK_REG_SM_OR_CASE = 3 ;
+static const uint8_t P9N2_PU_MCD1_MCD_FIR_MASK_REG_CL_PROBE_PB_HANG = 4 ;
+static const uint8_t P9N2_PU_MCD1_MCD_FIR_MASK_REG_CRESP_ADDR = 5 ;
+static const uint8_t P9N2_PU_MCD1_MCD_FIR_MASK_REG_UNSOLICITED_CRESP = 6 ;
+static const uint8_t P9N2_PU_MCD1_MCD_FIR_MASK_REG_TTAG_PARITY = 7 ;
+static const uint8_t P9N2_PU_MCD1_MCD_FIR_MASK_REG_UPDATE_ERR = 8 ;
+static const uint8_t P9N2_PU_MCD1_MCD_FIR_MASK_REG_ACK_DEAD_CRESP = 9 ;
+static const uint8_t P9N2_PU_MCD1_MCD_FIR_MASK_REG_SCOM_ERR = 10 ;
+static const uint8_t P9N2_PU_MCD1_MCD_FIR_MASK_REG_SCOM_ERR_DUP = 11 ;
+
+static const uint8_t P9N2_PU_MIB_XIICAC_ICACHE_TAG_ADDR = 0 ;
+static const uint8_t P9N2_PU_MIB_XIICAC_ICACHE_TAG_ADDR_LEN = 27 ;
+static const uint8_t P9N2_PU_MIB_XIICAC_ICACHE_ERR = 32 ;
+static const uint8_t P9N2_PU_MIB_XIICAC_PIB_IFETCH_PENDING = 34 ;
+static const uint8_t P9N2_PU_MIB_XIICAC_XIMEM_MEM_IFETCH_PENDING = 35 ;
+static const uint8_t P9N2_PU_MIB_XIICAC_ICACHE_VALID = 36 ;
+static const uint8_t P9N2_PU_MIB_XIICAC_ICACHE_VALID_LEN = 4 ;
+static const uint8_t P9N2_PU_MIB_XIICAC_ICACHE_LINE2_VALID = 40 ;
+static const uint8_t P9N2_PU_MIB_XIICAC_ICACHE_LINE2_VALID_LEN = 4 ;
+static const uint8_t P9N2_PU_MIB_XIICAC_ICACHE_LINE_PTR = 45 ;
+static const uint8_t P9N2_PU_MIB_XIICAC_ICACHE_LINE2_ERR = 46 ;
+static const uint8_t P9N2_PU_MIB_XIICAC_ICACHE_PREFETCH_PENDING = 47 ;
+
+static const uint8_t P9N2_PU_MIB_XIMEM_MEM_ADDR = 0 ;
+static const uint8_t P9N2_PU_MIB_XIMEM_MEM_ADDR_LEN = 32 ;
+static const uint8_t P9N2_PU_MIB_XIMEM_MEM_R_NW = 32 ;
+static const uint8_t P9N2_PU_MIB_XIMEM_MEM_BUSY = 33 ;
+static const uint8_t P9N2_PU_MIB_XIMEM_MEM_IMPRECISE_ERROR_PENDING = 34 ;
+static const uint8_t P9N2_PU_MIB_XIMEM_MEM_BYTE_ENABLE = 35 ;
+static const uint8_t P9N2_PU_MIB_XIMEM_MEM_BYTE_ENABLE_LEN = 8 ;
+static const uint8_t P9N2_PU_MIB_XIMEM_MEM_LINE_MODE = 43 ;
+static const uint8_t P9N2_PU_MIB_XIMEM_MEM_ERROR = 49 ;
+static const uint8_t P9N2_PU_MIB_XIMEM_MEM_ERROR_LEN = 3 ;
+static const uint8_t P9N2_PU_MIB_XIMEM_MEM_IFETCH_PENDING = 62 ;
+static const uint8_t P9N2_PU_MIB_XIMEM_MEM_DATAOP_PENDING = 63 ;
+
+static const uint8_t P9N2_PU_MIB_XISGB_STORE_ADDRESS = 0 ;
+static const uint8_t P9N2_PU_MIB_XISGB_STORE_ADDRESS_LEN = 32 ;
+static const uint8_t P9N2_PU_MIB_XISGB_XIMEM_MEM_IMPRECISE_ERROR_PENDING = 35 ;
+static const uint8_t P9N2_PU_MIB_XISGB_SGB_BYTE_VALID = 36 ;
+static const uint8_t P9N2_PU_MIB_XISGB_SGB_BYTE_VALID_LEN = 4 ;
+static const uint8_t P9N2_PU_MIB_XISGB_SGB_FLUSH_PENDING = 63 ;
+
+static const uint8_t P9N2_PU_MIB_XISIB_PIB_ADDR = 0 ;
+static const uint8_t P9N2_PU_MIB_XISIB_PIB_ADDR_LEN = 32 ;
+static const uint8_t P9N2_PU_MIB_XISIB_PIB_R_NW = 32 ;
+static const uint8_t P9N2_PU_MIB_XISIB_PIB_BUSY = 33 ;
+static const uint8_t P9N2_PU_MIB_XISIB_PIB_IMPRECISE_ERROR_PENDING = 34 ;
+static const uint8_t P9N2_PU_MIB_XISIB_PIB_RSP_INFO = 49 ;
+static const uint8_t P9N2_PU_MIB_XISIB_PIB_RSP_INFO_LEN = 3 ;
+static const uint8_t P9N2_PU_MIB_XISIB_PIB_IFETCH_PENDING = 62 ;
+static const uint8_t P9N2_PU_MIB_XISIB_PIB_DATAOP_PENDING = 63 ;
+
+static const uint8_t P9N2__CTL_MISC_CONFIG_SYNC_WAIT = 0 ;
+static const uint8_t P9N2__CTL_MISC_CONFIG_SYNC_WAIT_LEN = 5 ;
+static const uint8_t P9N2__CTL_MISC_CONFIG_PERF_ENABLE = 5 ;
+static const uint8_t P9N2__CTL_MISC_CONFIG_PERF_PE_MASK = 6 ;
+static const uint8_t P9N2__CTL_MISC_CONFIG_PERF_PE_MATCH = 7 ;
+static const uint8_t P9N2__CTL_MISC_CONFIG_PERF_PE_MATCH_LEN = 4 ;
+static const uint8_t P9N2__CTL_MISC_CONFIG_IPI_PS = 11 ;
+static const uint8_t P9N2__CTL_MISC_CONFIG_IPI_OS = 12 ;
+static const uint8_t P9N2__CTL_MISC_CONFIG_OC_ATS_SYNC_START = 13 ;
+static const uint8_t P9N2__CTL_MISC_CONFIG_CQ_RESP_VALID_ENABLE = 14 ;
+static const uint8_t P9N2__CTL_MISC_CONFIG_RSVD = 15 ;
+static const uint8_t P9N2__CTL_MISC_CONFIG_RSVD_LEN = 49 ;
+
+static const uint8_t P9N2__CTL_MISC_HOLD_IDIAL_NDL0_STALL = 0 ;
+static const uint8_t P9N2__CTL_MISC_HOLD_IDIAL_NDL0_NOSTALL = 1 ;
+static const uint8_t P9N2__CTL_MISC_HOLD_IDIAL_NDL1_STALL = 2 ;
+static const uint8_t P9N2__CTL_MISC_HOLD_IDIAL_NDL1_NOSTALL = 3 ;
+static const uint8_t P9N2__CTL_MISC_HOLD_IDIAL_NDL2_STALL = 4 ;
+static const uint8_t P9N2__CTL_MISC_HOLD_IDIAL_NDL2_NOSTALL = 5 ;
+static const uint8_t P9N2__CTL_MISC_HOLD_IDIAL_NDL3_STALL = 6 ;
+static const uint8_t P9N2__CTL_MISC_HOLD_IDIAL_NDL3_NOSTALL = 7 ;
+static const uint8_t P9N2__CTL_MISC_HOLD_IDIAL_NDL4_STALL = 8 ;
+static const uint8_t P9N2__CTL_MISC_HOLD_IDIAL_NDL4_NOSTALL = 9 ;
+static const uint8_t P9N2__CTL_MISC_HOLD_IDIAL_NDL5_STALL = 10 ;
+static const uint8_t P9N2__CTL_MISC_HOLD_IDIAL_NDL5_NOSTALL = 11 ;
+static const uint8_t P9N2__CTL_MISC_HOLD_IDIAL_RING_ERRP = 12 ;
+static const uint8_t P9N2__CTL_MISC_HOLD_IDIAL_IBAR_ERRP = 13 ;
+static const uint8_t P9N2__CTL_MISC_HOLD_IDIAL_SCOMDAA_ERRP = 14 ;
+static const uint8_t P9N2__CTL_MISC_HOLD_IDIAL_CNTL_ERRP = 15 ;
+static const uint8_t P9N2__CTL_MISC_HOLD_IDIAL_MM_LOCAL_XSTOP = 16 ;
+static const uint8_t P9N2__CTL_MISC_HOLD_IDIAL_RX10_FAULT = 17 ;
+static const uint8_t P9N2__CTL_MISC_HOLD_IDIAL_RX11_FAULT = 18 ;
+static const uint8_t P9N2__CTL_MISC_HOLD_IDIAL_RX20_FAULT = 19 ;
+static const uint8_t P9N2__CTL_MISC_HOLD_IDIAL_RX21_FAULT = 20 ;
+
+static const uint8_t P9N2__CTL_MISC_MASK_IDIAL = 0 ;
+static const uint8_t P9N2__CTL_MISC_MASK_IDIAL_LEN = 21 ;
+
+static const uint8_t P9N2_PU_NMMU_MMCQ_PB_MODE_REG_DMA_WR_DISABLE_LN = 0 ;
+static const uint8_t P9N2_PU_NMMU_MMCQ_PB_MODE_REG_DMA_WR_DISABLE_GROUP = 1 ;
+static const uint8_t P9N2_PU_NMMU_MMCQ_PB_MODE_REG_DMA_WR_DISABLE_VG_NOT_SYS = 2 ;
+static const uint8_t P9N2_PU_NMMU_MMCQ_PB_MODE_REG_DMA_WR_DISABLE_NN_RN = 3 ;
+static const uint8_t P9N2_PU_NMMU_MMCQ_PB_MODE_REG_DMA_RD_DISABLE_LN = 4 ;
+static const uint8_t P9N2_PU_NMMU_MMCQ_PB_MODE_REG_DMA_RD_DISABLE_GROUP = 5 ;
+static const uint8_t P9N2_PU_NMMU_MMCQ_PB_MODE_REG_DMA_RD_DISABLE_VG_NOT_SYS = 6 ;
+static const uint8_t P9N2_PU_NMMU_MMCQ_PB_MODE_REG_DMA_RD_DISABLE_NN_RN = 7 ;
+static const uint8_t P9N2_PU_NMMU_MMCQ_PB_MODE_REG_LCO_CRED_MASK = 8 ;
+static const uint8_t P9N2_PU_NMMU_MMCQ_PB_MODE_REG_LCO_CRED_MASK_LEN = 3 ;
+static const uint8_t P9N2_PU_NMMU_MMCQ_PB_MODE_REG_LCO_TARG_MIN = 11 ;
+static const uint8_t P9N2_PU_NMMU_MMCQ_PB_MODE_REG_LCO_TARG_MIN_LEN = 4 ;
+static const uint8_t P9N2_PU_NMMU_MMCQ_PB_MODE_REG_LCO_TARG_CONFIG = 15 ;
+static const uint8_t P9N2_PU_NMMU_MMCQ_PB_MODE_REG_LCO_TARG_CONFIG_LEN = 12 ;
+static const uint8_t P9N2_PU_NMMU_MMCQ_PB_MODE_REG_UNUSED = 27 ;
+static const uint8_t P9N2_PU_NMMU_MMCQ_PB_MODE_REG_UNUSED_LEN = 4 ;
+static const uint8_t P9N2_PU_NMMU_MMCQ_PB_MODE_REG_NX_FREEZE_MODES = 31 ;
+static const uint8_t P9N2_PU_NMMU_MMCQ_PB_MODE_REG_NX_FREEZE_MODES_LEN = 2 ;
+static const uint8_t P9N2_PU_NMMU_MMCQ_PB_MODE_REG_ADDR_BAR = 33 ;
+static const uint8_t P9N2_PU_NMMU_MMCQ_PB_MODE_REG_SKIP_G = 34 ;
+static const uint8_t P9N2_PU_NMMU_MMCQ_PB_MODE_REG_RESERVED = 35 ;
+static const uint8_t P9N2_PU_NMMU_MMCQ_PB_MODE_REG_RESERVED_LEN = 2 ;
+static const uint8_t P9N2_PU_NMMU_MMCQ_PB_MODE_REG_NXCQ_HANG_SM_ON_ARE = 37 ;
+static const uint8_t P9N2_PU_NMMU_MMCQ_PB_MODE_REG_NXCQ_HANG_SM_ON_LINK_FAIL = 38 ;
+static const uint8_t P9N2_PU_NMMU_MMCQ_PB_MODE_REG_CFG_PUMP = 39 ;
+static const uint8_t P9N2_PU_NMMU_MMCQ_PB_MODE_REG_DMA_RD_VG_RESET_TIMER_MASK = 40 ;
+static const uint8_t P9N2_PU_NMMU_MMCQ_PB_MODE_REG_DMA_RD_VG_RESET_TIMER_MASK_LEN = 8 ;
+static const uint8_t P9N2_PU_NMMU_MMCQ_PB_MODE_REG_DMA_WR_VG_RESET_TIMER_MASK = 48 ;
+static const uint8_t P9N2_PU_NMMU_MMCQ_PB_MODE_REG_DMA_WR_VG_RESET_TIMER_MASK_LEN = 8 ;
+static const uint8_t P9N2_PU_NMMU_MMCQ_PB_MODE_REG_ADDR_EXT_MASK = 56 ;
+static const uint8_t P9N2_PU_NMMU_MMCQ_PB_MODE_REG_ADDR_EXT_MASK_LEN = 7 ;
+
+static const uint8_t P9N2_PHB_MMIOBAR0_MASK_REG_PE_MMIO_MASK0 = 0 ;
+static const uint8_t P9N2_PHB_MMIOBAR0_MASK_REG_PE_MMIO_MASK0_LEN = 40 ;
+
+static const uint8_t P9N2_PEC_STACK0_MMIOBAR0_MASK_REG_PE_MMIO_MASK0 = 0 ;
+static const uint8_t P9N2_PEC_STACK0_MMIOBAR0_MASK_REG_PE_MMIO_MASK0_LEN = 40 ;
+
+static const uint8_t P9N2_PHB_MMIOBAR0_REG_PE_MMIO_BAR0 = 0 ;
+static const uint8_t P9N2_PHB_MMIOBAR0_REG_PE_MMIO_BAR0_LEN = 40 ;
+
+static const uint8_t P9N2_PEC_STACK0_MMIOBAR0_REG_PE_MMIO_BAR0 = 0 ;
+static const uint8_t P9N2_PEC_STACK0_MMIOBAR0_REG_PE_MMIO_BAR0_LEN = 40 ;
+
+static const uint8_t P9N2_PHB_MMIOBAR1_MASK_REG_PE_MMIO_MASK1 = 0 ;
+static const uint8_t P9N2_PHB_MMIOBAR1_MASK_REG_PE_MMIO_MASK1_LEN = 40 ;
+
+static const uint8_t P9N2_PEC_STACK0_MMIOBAR1_MASK_REG_PE_MMIO_MASK1 = 0 ;
+static const uint8_t P9N2_PEC_STACK0_MMIOBAR1_MASK_REG_PE_MMIO_MASK1_LEN = 40 ;
+
+static const uint8_t P9N2_PHB_MMIOBAR1_REG_PE_MMIO_BAR1 = 0 ;
+static const uint8_t P9N2_PHB_MMIOBAR1_REG_PE_MMIO_BAR1_LEN = 40 ;
+
+static const uint8_t P9N2_PEC_STACK0_MMIOBAR1_REG_PE_MMIO_BAR1 = 0 ;
+static const uint8_t P9N2_PEC_STACK0_MMIOBAR1_REG_PE_MMIO_BAR1_LEN = 40 ;
+
+static const uint8_t P9N2_PU_NPU2_NTL0_MMIOPA0_CONFIG_RESERVED1 = 0 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_MMIOPA0_CONFIG_ADDR = 1 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_MMIOPA0_CONFIG_ADDR_LEN = 35 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_MMIOPA0_CONFIG_RESERVED2 = 36 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_MMIOPA0_CONFIG_RESERVED2_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_MMIOPA0_CONFIG_SIZE = 39 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_MMIOPA0_CONFIG_SIZE_LEN = 5 ;
+
+static const uint8_t P9N2_NV_MMIOPA0_CONFIG_RESERVED1 = 0 ;
+static const uint8_t P9N2_NV_MMIOPA0_CONFIG_ADDR = 1 ;
+static const uint8_t P9N2_NV_MMIOPA0_CONFIG_ADDR_LEN = 35 ;
+static const uint8_t P9N2_NV_MMIOPA0_CONFIG_RESERVED2 = 36 ;
+static const uint8_t P9N2_NV_MMIOPA0_CONFIG_RESERVED2_LEN = 3 ;
+static const uint8_t P9N2_NV_MMIOPA0_CONFIG_SIZE = 39 ;
+static const uint8_t P9N2_NV_MMIOPA0_CONFIG_SIZE_LEN = 5 ;
+
+static const uint8_t P9N2_PU_NPU2_NTL0_MMIOPA1_CONFIG_RESERVED1 = 0 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_MMIOPA1_CONFIG_ADDR = 1 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_MMIOPA1_CONFIG_ADDR_LEN = 35 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_MMIOPA1_CONFIG_RESERVED2 = 36 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_MMIOPA1_CONFIG_RESERVED2_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_MMIOPA1_CONFIG_SIZE = 39 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_MMIOPA1_CONFIG_SIZE_LEN = 5 ;
+
+static const uint8_t P9N2_NV_MMIOPA1_CONFIG_RESERVED1 = 0 ;
+static const uint8_t P9N2_NV_MMIOPA1_CONFIG_ADDR = 1 ;
+static const uint8_t P9N2_NV_MMIOPA1_CONFIG_ADDR_LEN = 35 ;
+static const uint8_t P9N2_NV_MMIOPA1_CONFIG_RESERVED2 = 36 ;
+static const uint8_t P9N2_NV_MMIOPA1_CONFIG_RESERVED2_LEN = 3 ;
+static const uint8_t P9N2_NV_MMIOPA1_CONFIG_SIZE = 39 ;
+static const uint8_t P9N2_NV_MMIOPA1_CONFIG_SIZE_LEN = 5 ;
+
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_MISC_RESERVED_0 = 0 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_MISC_BKINV_INTERLOCK_DIS = 1 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_MISC_DYN_ST_MODE_EN = 2 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_MISC_DYN_ST_MODE_HANGP_EN = 3 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_MISC_LFSR_DIS = 8 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_MISC_FBC_LFSR_DIS = 9 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_MISC_FBC_INV_AMORT_DIS = 10 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_MISC_RESERVED_10_11 = 11 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_MISC_FBC_DIN_ECC_CHK_DIS = 12 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_MISC_FBC_XLAT_ECC_CHK_DIS = 13 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_MISC_FBC_XLAT_PROT_ERR_CHK_DIS = 14 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_MISC_FBC_XLAT_TIMEOUT_CHK_DIS = 15 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_MISC_CO_PROT_ERR_CHK_DIS = 16 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_MISC_CO_TIMEOUT_CHK_DIS = 17 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_MISC_CKIN_PROT_ERR_CHK_DIS = 18 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_MISC_CKIN_TIMEOUT_CHK_DIS = 19 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_MISC_INV_PROT_ERR_CHK_DIS = 20 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_MISC_INV_TIMEOUT_CHK_DIS = 21 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_MISC_TW_PROT_ERR_CHK_DIS = 22 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_MISC_TW_TIMEOUT_CHK_DIS = 23 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_MISC_FBC_SNP_PROT_ERR_CHK_DIS = 24 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_MISC_FBC_SNP_TIMEOUT_CHK_DIS = 25 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_MISC_FBC_CMD_PROT_ERR_CHK_DIS = 26 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_MISC_RESERVED_27 = 27 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_MISC_DYN_ST_MODE_THRESHOLD = 28 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_MISC_DYN_ST_MODE_THRESHOLD_LEN = 4 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_MISC_HANG_PLS_MULT = 32 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_MISC_HANG_PLS_MULT_LEN = 16 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_MISC_NCU_SNP_TLBIE_INC_RATE = 48 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_MISC_NCU_SNP_TLBIE_INC_RATE_LEN = 8 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_MISC_NCU_SNP_TLBIE_DEC_RATE = 56 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_MISC_NCU_SNP_TLBIE_DEC_RATE_LEN = 8 ;
+
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SLB_MBR_DIS = 0 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SLB_MBR_DIS_LEN = 16 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SLB_SNGL_THD_EN = 16 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SLB_CAC_ALLOC_DIS = 17 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SLB_DMAP_MODE_EN = 18 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SLB_ALT_SEGSZ_DIS = 19 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SLB_DIR_PERR_CHK_DIS = 20 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SLB_CAC_PERR_CHK_DIS = 21 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SLB_LRU_PERR_CHK_DIS = 22 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SLB_MULTIHIT_CHK_DIS = 23 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SLB_ISS505_FIX_DIS = 24 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SLB_ISS510_FIX_DIS = 25 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SLB_ISS511_FIX_DIS = 26 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SLB_ISS544_FIX_DIS = 27 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SLB_ISS554_FIX_DIS = 28 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SLB_ISS560_FIX_DIS = 29 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SLB_DD2_ISS584_FIX_DIS = 30 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SLB_RESERVED_31 = 31 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SLB_DBG_BUS0_STG0_SEL = 32 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SLB_DBG_BUS0_STG0_SEL_LEN = 4 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SLB_DBG_BUS1_STG0_SEL = 36 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SLB_DBG_BUS1_STG0_SEL_LEN = 4 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SLB_RESERVED_40_51 = 40 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SLB_RESERVED_40_51_LEN = 12 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SLB_ISS542_FIX_DIS = 52 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SLB_RESERVED_53_56 = 53 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SLB_RESERVED_53_56_LEN = 4 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SLB_TWSM_11_1_MODE_ENA = 57 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SLB_SNGL_SHOT_ENA = 58 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SLB_FBC_SNGL_SHOT_HOLDOFF_ENA = 59 ;
+
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM_TWSM_DIS = 0 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM_TWSM_DIS_LEN = 12 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM_CKINSM_DIS = 12 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM_CKINSM_DIS_LEN = 8 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM_INV_SINGLE_THREAD_EN = 20 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_CXT_CAC_DIS = 21 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM_RESERVED_22_23 = 22 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM_RESERVED_22_23_LEN = 2 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM_ISS487_EN = 24 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM_RESERVED_25 = 25 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM_ISS526_EN = 26 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM_RESERVED_27_29 = 27 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM_RESERVED_27_29_LEN = 3 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_MPSS_DIS = 31 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM_NCU_SNP_TLBIE_CNT_THRESH = 32 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM_NCU_SNP_TLBIE_CNT_THRESH_LEN = 8 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_ATT_HPT_SAO_FOLD_DIS = 40 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_ATT_RDX_SAO_FOLD_DIS = 41 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_ATT_RDX_NIO_FOLD_DIS = 42 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_ATT_RDX_TIO_FOLD_DIS = 43 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_LCO_RDX_EN = 44 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_LCO_ABRT_IF_UPRC = 45 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_LCO_ABRT_IF_PF = 46 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM_RESERVED_47 = 47 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM_RESERVED_48 = 48 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM_RESERVED_49 = 49 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM_RESERVED_50 = 50 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_LCO_RDX_PDE_EN = 51 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_RDX_PWC_DIS = 52 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_RDX_INT_PWC_DIS = 53 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_RDX_INT_TLB_DIS = 54 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_RDX_PWC_SPLIT_EN = 55 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_RDX_PWC_VA_HASH = 56 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM_RESERVED_57 = 57 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_PTE_UPD_INTR_EN = 58 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM_NCU_SNP_TLBIE_PACING_CNT_EN = 59 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM_DYN_ST_FREQ_MULT = 60 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_SM_DYN_ST_FREQ_MULT_LEN = 4 ;
+
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB_MBR_DIS = 0 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB_MBR_DIS_LEN = 16 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB_SNGL_THD_EN = 16 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB_CAC_ALLOC_DIS = 17 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB_DMAP_MODE_EN = 18 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB_MPSS_DIS = 19 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB_HASH_LPID_DIS = 20 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB_HASH_PID_DIS = 21 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB_DIR_PERR_CHK_DIS = 22 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB_CAC_PERR_CHK_DIS = 23 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB_LRU_PERR_CHK_DIS = 24 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB_MULTIHIT_CHK_DIS = 25 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB_EA_RANGE_CHK_DIS = 26 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB_ISS426_FIX_DIS = 27 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB_ISS486_FIX_DIS = 28 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB_ISS505_FIX_DIS = 29 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB_ISS510_FIX_DIS = 30 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB_ISS512_FIX_DIS = 31 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB_DBG_BUS0_STG0_SEL = 32 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB_DBG_BUS0_STG0_SEL_LEN = 4 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB_DBG_BUS1_STG0_SEL = 36 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB_DBG_BUS1_STG0_SEL_LEN = 4 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB_ISS534_FIX_DIS = 40 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB_ISS537_FIX_DIS = 41 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB_ISS540_FIX_DIS = 42 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB_ISS543_FIX_DIS = 43 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB_GUEST_PREF_PGSZ = 44 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB_GUEST_PREF_PGSZ_LEN = 4 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB_HOST_PREF_PGSZ = 48 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB_HOST_PREF_PGSZ_LEN = 4 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB_ISS542_FIX_DIS = 52 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB_ISS543B_FIX_EN = 53 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB_ISS567_FIX_DIS = 54 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB_ISS586_FIX_DIS = 55 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB_MPSS_PREF_PGSZ_ENA = 56 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB_TWSM_11_1_MODE_ENA = 57 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB_SNGL_SHOT_ENA = 58 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_CTL_TLB_SLB_SNGL_SHOT_HOLDOFF_ENA = 59 ;
+
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_XLAT_CTL_REG0_HRMOR = 0 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_XLAT_CTL_REG0_HRMOR_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_XLAT_CTL_REG1_PTCR = 0 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_XLAT_CTL_REG1_PTCR_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_XLAT_CTL_REG2_URMOR = 0 ;
+static const uint8_t P9N2_PU_NMMU_MM_CFG_NMMU_XLAT_CTL_REG2_URMOR_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NMMU_MM_EPSILON_COUNTER_VALUE_WR_TIER_1_CNT_VAL = 0 ;
+static const uint8_t P9N2_PU_NMMU_MM_EPSILON_COUNTER_VALUE_WR_TIER_1_CNT_VAL_LEN = 12 ;
+static const uint8_t P9N2_PU_NMMU_MM_EPSILON_COUNTER_VALUE_WR_TIER_1_DIV_VAL = 12 ;
+static const uint8_t P9N2_PU_NMMU_MM_EPSILON_COUNTER_VALUE_WR_TIER_1_DIV_VAL_LEN = 4 ;
+static const uint8_t P9N2_PU_NMMU_MM_EPSILON_COUNTER_VALUE_WR_TIER_2_CNT_VAL = 16 ;
+static const uint8_t P9N2_PU_NMMU_MM_EPSILON_COUNTER_VALUE_WR_TIER_2_CNT_VAL_LEN = 12 ;
+static const uint8_t P9N2_PU_NMMU_MM_EPSILON_COUNTER_VALUE_WR_TIER_2_DIV_VAL = 28 ;
+static const uint8_t P9N2_PU_NMMU_MM_EPSILON_COUNTER_VALUE_WR_TIER_2_DIV_VAL_LEN = 4 ;
+static const uint8_t P9N2_PU_NMMU_MM_EPSILON_COUNTER_VALUE_DISABLE = 32 ;
+
+static const uint8_t P9N2_PU_NMMU_MM_FIR1_ACTION0_REG_ACTION0 = 0 ;
+static const uint8_t P9N2_PU_NMMU_MM_FIR1_ACTION0_REG_ACTION0_LEN = 48 ;
+
+static const uint8_t P9N2_PU_NMMU_MM_FIR1_ACTION1_REG_ACTION1 = 0 ;
+static const uint8_t P9N2_PU_NMMU_MM_FIR1_ACTION1_REG_ACTION1_LEN = 48 ;
+
+static const uint8_t P9N2_PU_NMMU_MM_FIR1_MASK_REG_MASK = 0 ;
+static const uint8_t P9N2_PU_NMMU_MM_FIR1_MASK_REG_MASK_LEN = 48 ;
+
+static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_FBC_XLAT_ARY_ECC_CE_DET = 0 ;
+static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_FBC_XLAT_ARY_ECC_UE_DET = 1 ;
+static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_FBC_XLAT_ARY_ECC_SUE_DET = 2 ;
+static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_FBC_CQRD_ARY_ECC_CE_DET = 3 ;
+static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_FBC_CQRD_ARY_ECC_UE_DET = 4 ;
+static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_FBC_CQRD_ARY_ECC_SUE_DET = 5 ;
+static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_FBC_XLAT_PROT_ERR_DET = 6 ;
+static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_FBC_XLAT_TIMEOUT_DET = 7 ;
+static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_SLB_DIR_PERR_DET = 8 ;
+static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_SLB_CAC_PERR_DET = 9 ;
+static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_SLB_LRU_PERR_DET = 10 ;
+static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_SLB_MULTIHIT_DET = 11 ;
+static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_TLB_DIR_PERR_DET = 12 ;
+static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_TLB_CAC_PERR_DET = 13 ;
+static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_TLB_LRU_PERR_DET = 14 ;
+static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_TLB_MULTIHIT_DET = 15 ;
+static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_TW_SEG_FAULT_DET = 16 ;
+static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_TW_PG_FAULT_NOPTE_DET = 17 ;
+static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_TW_PG_FAULT_BPCHK_DET = 18 ;
+static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_TW_PG_FAULT_VPCHK_DET = 19 ;
+static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_TW_PG_FAULT_SEID_DET = 20 ;
+static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_TW_ADD_ERR_CR_RD_DET = 21 ;
+static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_TW_PTE_UPD_FAIL_DET = 22 ;
+static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_TW_ADD_ERR_CR_WR_DET = 23 ;
+static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_TW_RDX_CFG_GUEST_DET = 24 ;
+static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_TW_RDX_CFG_HOST_DET = 25 ;
+static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_TW_INVALID_WIMG_DET = 26 ;
+static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_TW_INV_RDX_QUAD_DET = 27 ;
+static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_TW_FOREIGN_ADDR_DET = 28 ;
+static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_TW_PREFETCH_ABT_DET = 29 ;
+static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_TW_CXT_CAC_PERR_DET = 30 ;
+static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_TW_RDX_PWC_PERR_DET = 31 ;
+static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_TW_SM_CTL_ERR_DET = 32 ;
+static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_CO_SM_CTL_ERR_DET = 33 ;
+static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_CI_SM_CTL_ERR_DET = 34 ;
+static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_INV_SM_CTL_ERR_DET = 35 ;
+static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_TW_TIMEOUT_ERR_DET = 36 ;
+static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_CO_TIMEOUT_ERR_DET = 37 ;
+static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_CI_TIMEOUT_ERR_DET = 38 ;
+static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_INV_TIMEOUT_ERR_DET = 39 ;
+static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_NX0_LXSTOP_ERR_DET = 40 ;
+static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_CP0_LXSTOP_ERR_DET = 41 ;
+static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_CP1_LXSTOP_ERR_DET = 42 ;
+static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_NPU_LXSTOP_ERR_DET = 43 ;
+static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_FBC_LXSTOP_ERR_DET = 44 ;
+static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_SPARE = 45 ;
+static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_SCOM_PE_FIR = 46 ;
+static const uint8_t P9N2_PU_NMMU_MM_FIR1_REG_SCOM_PE_DUP_FIR = 47 ;
+
+static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_EN = 0 ;
+static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_PRV_BUS0_STG2_SEL = 1 ;
+static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_PRV_BUS1_STG2_SEL = 2 ;
+static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_FBC_BUS0_STG2_SEL = 3 ;
+static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_FBC_BUS1_STG2_SEL = 4 ;
+static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_MSC_BUS0_STG2_SEL = 5 ;
+static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_MSC_BUS1_STG2_SEL = 6 ;
+static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_SLB_BUS0_STG2_SEL = 7 ;
+static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_SLB_BUS1_STG2_SEL = 8 ;
+static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_TW_BUS0_STG2_SEL = 9 ;
+static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_TW_BUS1_STG2_SEL = 10 ;
+static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_RDX_BUS0_STG2_SEL = 11 ;
+static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_RDX_BUS1_STG2_SEL = 12 ;
+static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_TLB_BUS0_STG2_SEL = 13 ;
+static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_TLB_BUS1_STG2_SEL = 14 ;
+static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_FBC_BUS0_STG1_SEL = 15 ;
+static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_FBC_BUS1_STG1_SEL = 16 ;
+static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_MSC_BUS0_STG1_SEL = 17 ;
+static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_MSC_BUS1_STG1_SEL = 18 ;
+static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_SLB_BUS0_STG1_SEL = 19 ;
+static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_SLB_BUS1_STG1_SEL = 20 ;
+static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_TW_BUS0_STG1_SEL = 21 ;
+static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_TW_BUS1_STG1_SEL = 22 ;
+static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_RDX_BUS0_STG1_SEL = 23 ;
+static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_RDX_BUS1_STG1_SEL = 24 ;
+static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_TLB_BUS0_STG1_SEL = 25 ;
+static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_TLB_BUS1_STG1_SEL = 26 ;
+static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_RESERVED_27_31 = 27 ;
+static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_RESERVED_27_31_LEN = 5 ;
+static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_FBC_BUS0_STG0_SEL = 32 ;
+static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_FBC_BUS0_STG0_SEL_LEN = 4 ;
+static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_FBC_BUS1_STG0_SEL = 36 ;
+static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_FBC_BUS1_STG0_SEL_LEN = 4 ;
+static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_MSC_BUS0_STG0_SEL = 40 ;
+static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_MSC_BUS0_STG0_SEL_LEN = 4 ;
+static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_MSC_BUS1_STG0_SEL = 44 ;
+static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_MSC_BUS1_STG0_SEL_LEN = 4 ;
+static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_TW_BUS0_STG0_SEL = 48 ;
+static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_TW_BUS0_STG0_SEL_LEN = 6 ;
+static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_TW_BUS1_STG0_SEL = 54 ;
+static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_TW_BUS1_STG0_SEL_LEN = 6 ;
+static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_RDX_BUS0_STG0_SEL = 60 ;
+static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_RDX_BUS0_STG0_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_RDX_BUS1_STG0_SEL = 62 ;
+static const uint8_t P9N2_PU_NMMU_MM_NMMU_DBG_MODE_RDX_BUS1_STG0_SEL_LEN = 2 ;
+
+static const uint8_t P9N2_PU_NMMU_MM_NMMU_ERR_INJ_INJ = 0 ;
+static const uint8_t P9N2_PU_NMMU_MM_NMMU_ERR_INJ_INJ_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NMMU_MM_NMMU_ERR_LOG_LOG = 0 ;
+static const uint8_t P9N2_PU_NMMU_MM_NMMU_ERR_LOG_LOG_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NMMU_MM_NMMU_FLT_STAT_REG_STAT = 0 ;
+static const uint8_t P9N2_PU_NMMU_MM_NMMU_FLT_STAT_REG_STAT_LEN = 16 ;
+
+static const uint8_t P9N2_PU_NMMU_MM_NMMU_PMU0_CNT_REG_CNT = 0 ;
+static const uint8_t P9N2_PU_NMMU_MM_NMMU_PMU0_CNT_REG_CNT_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NMMU_MM_NMMU_PMU0_CTL_REG_CTL = 0 ;
+static const uint8_t P9N2_PU_NMMU_MM_NMMU_PMU0_CTL_REG_CTL_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NMMU_MM_NMMU_PMU1_CNT_REG_CNT = 0 ;
+static const uint8_t P9N2_PU_NMMU_MM_NMMU_PMU1_CNT_REG_CNT_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NMMU_MM_NMMU_PMU1_CTL_REG_CTL = 0 ;
+static const uint8_t P9N2_PU_NMMU_MM_NMMU_PMU1_CTL_REG_CTL_LEN = 64 ;
+
+static const uint8_t P9N2_PEC_MODE_REG_IN0 = 0 ;
+static const uint8_t P9N2_PEC_MODE_REG_IN1 = 1 ;
+static const uint8_t P9N2_PEC_MODE_REG_IN2 = 2 ;
+static const uint8_t P9N2_PEC_MODE_REG_IN3 = 3 ;
+static const uint8_t P9N2_PEC_MODE_REG_IN4 = 4 ;
+static const uint8_t P9N2_PEC_MODE_REG_IN5 = 5 ;
+static const uint8_t P9N2_PEC_MODE_REG_IN6 = 6 ;
+static const uint8_t P9N2_PEC_MODE_REG_IN7 = 7 ;
+static const uint8_t P9N2_PEC_MODE_REG_IN8 = 8 ;
+static const uint8_t P9N2_PEC_MODE_REG_IN9 = 9 ;
+static const uint8_t P9N2_PEC_MODE_REG_IN10 = 10 ;
+static const uint8_t P9N2_PEC_MODE_REG_IN11 = 11 ;
+static const uint8_t P9N2_PEC_MODE_REG_IN = 12 ;
+static const uint8_t P9N2_PEC_MODE_REG_IN_LEN = 4 ;
+
+static const uint8_t P9N2_PU_MODE_REGISTER_DCOMP_ENABLE = 0 ;
+static const uint8_t P9N2_PU_MODE_REGISTER_ECC_ENABLE = 1 ;
+static const uint8_t P9N2_PU_MODE_REGISTER_PROGRAM_ENABLE = 2 ;
+static const uint8_t P9N2_PU_MODE_REGISTER_ECC_CHK_DISABLE = 3 ;
+static const uint8_t P9N2_PU_MODE_REGISTER_UNUSED_4_15 = 4 ;
+static const uint8_t P9N2_PU_MODE_REGISTER_UNUSED_4_15_LEN = 12 ;
+static const uint8_t P9N2_PU_MODE_REGISTER_CLK_RATE_SEL = 16 ;
+static const uint8_t P9N2_PU_MODE_REGISTER_CLK_RATE_SEL_LEN = 16 ;
+
+static const uint8_t P9N2_PU_MODE_REGISTER_B_BIT_RATE_DIVISOR_0 = 0 ;
+static const uint8_t P9N2_PU_MODE_REGISTER_B_BIT_RATE_DIVISOR_0_LEN = 16 ;
+static const uint8_t P9N2_PU_MODE_REGISTER_B_PORT_NUMBER_0 = 16 ;
+static const uint8_t P9N2_PU_MODE_REGISTER_B_PORT_NUMBER_0_LEN = 6 ;
+static const uint8_t P9N2_PU_MODE_REGISTER_B_FGAT_0 = 28 ;
+static const uint8_t P9N2_PU_MODE_REGISTER_B_DIAG_0 = 29 ;
+static const uint8_t P9N2_PU_MODE_REGISTER_B_PACING_ALLOW_0 = 30 ;
+static const uint8_t P9N2_PU_MODE_REGISTER_B_WRAP_0 = 31 ;
+static const uint8_t P9N2_PU_MODE_REGISTER_B_PEEK_DATA1_0 = 32 ;
+static const uint8_t P9N2_PU_MODE_REGISTER_B_PEEK_DATA1_0_LEN = 8 ;
+static const uint8_t P9N2_PU_MODE_REGISTER_B_LBUS_PARITY_ERR1_0 = 40 ;
+
+static const uint8_t P9N2_PU_MODE_REGISTER_C_BIT_RATE_DIVISOR_1 = 0 ;
+static const uint8_t P9N2_PU_MODE_REGISTER_C_BIT_RATE_DIVISOR_1_LEN = 16 ;
+static const uint8_t P9N2_PU_MODE_REGISTER_C_PORT_NUMBER_1 = 16 ;
+static const uint8_t P9N2_PU_MODE_REGISTER_C_PORT_NUMBER_1_LEN = 6 ;
+static const uint8_t P9N2_PU_MODE_REGISTER_C_FGAT_1 = 28 ;
+static const uint8_t P9N2_PU_MODE_REGISTER_C_DIAG_1 = 29 ;
+static const uint8_t P9N2_PU_MODE_REGISTER_C_PACING_ALLOW_1 = 30 ;
+static const uint8_t P9N2_PU_MODE_REGISTER_C_WRAP_1 = 31 ;
+static const uint8_t P9N2_PU_MODE_REGISTER_C_PEEK_DATA1_1 = 32 ;
+static const uint8_t P9N2_PU_MODE_REGISTER_C_PEEK_DATA1_1_LEN = 8 ;
+static const uint8_t P9N2_PU_MODE_REGISTER_C_LBUS_PARITY_ERR1_1 = 40 ;
+
+static const uint8_t P9N2_PU_MODE_REGISTER_D_BIT_RATE_DIVISOR_2 = 0 ;
+static const uint8_t P9N2_PU_MODE_REGISTER_D_BIT_RATE_DIVISOR_2_LEN = 16 ;
+static const uint8_t P9N2_PU_MODE_REGISTER_D_PORT_NUMBER_2 = 16 ;
+static const uint8_t P9N2_PU_MODE_REGISTER_D_PORT_NUMBER_2_LEN = 6 ;
+static const uint8_t P9N2_PU_MODE_REGISTER_D_FGAT_2 = 28 ;
+static const uint8_t P9N2_PU_MODE_REGISTER_D_DIAG_2 = 29 ;
+static const uint8_t P9N2_PU_MODE_REGISTER_D_PACING_ALLOW_2 = 30 ;
+static const uint8_t P9N2_PU_MODE_REGISTER_D_WRAP_2 = 31 ;
+static const uint8_t P9N2_PU_MODE_REGISTER_D_PEEK_DATA1_2 = 32 ;
+static const uint8_t P9N2_PU_MODE_REGISTER_D_PEEK_DATA1_2_LEN = 8 ;
+static const uint8_t P9N2_PU_MODE_REGISTER_D_LBUS_PARITY_ERR1_2 = 40 ;
+
+static const uint8_t P9N2_PU_MODE_REGISTER_E_BIT_RATE_DIVISOR_3 = 0 ;
+static const uint8_t P9N2_PU_MODE_REGISTER_E_BIT_RATE_DIVISOR_3_LEN = 16 ;
+static const uint8_t P9N2_PU_MODE_REGISTER_E_PORT_NUMBER_3 = 16 ;
+static const uint8_t P9N2_PU_MODE_REGISTER_E_PORT_NUMBER_3_LEN = 6 ;
+static const uint8_t P9N2_PU_MODE_REGISTER_E_FGAT_3 = 28 ;
+static const uint8_t P9N2_PU_MODE_REGISTER_E_DIAG_3 = 29 ;
+static const uint8_t P9N2_PU_MODE_REGISTER_E_PACING_ALLOW_3 = 30 ;
+static const uint8_t P9N2_PU_MODE_REGISTER_E_WRAP_3 = 31 ;
+static const uint8_t P9N2_PU_MODE_REGISTER_E_PEEK_DATA1_3 = 32 ;
+static const uint8_t P9N2_PU_MODE_REGISTER_E_PEEK_DATA1_3_LEN = 8 ;
+static const uint8_t P9N2_PU_MODE_REGISTER_E_LBUS_PARITY_ERR1_3 = 40 ;
+
+static const uint8_t P9N2_PEC_MULTICAST_GROUP_1_MULTICAST1 = 3 ;
+static const uint8_t P9N2_PEC_MULTICAST_GROUP_1_MULTICAST1_LEN = 3 ;
+
+static const uint8_t P9N2_PEC_MULTICAST_GROUP_2_MULTICAST2 = 3 ;
+static const uint8_t P9N2_PEC_MULTICAST_GROUP_2_MULTICAST2_LEN = 3 ;
+
+static const uint8_t P9N2_PEC_MULTICAST_GROUP_3_MULTICAST3 = 3 ;
+static const uint8_t P9N2_PEC_MULTICAST_GROUP_3_MULTICAST3_LEN = 3 ;
+
+static const uint8_t P9N2_PEC_MULTICAST_GROUP_4_MULTICAST4 = 3 ;
+static const uint8_t P9N2_PEC_MULTICAST_GROUP_4_MULTICAST4_LEN = 3 ;
+
+static const uint8_t P9N2_PU_NPU0_SM0_NDT0_BAR_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM0_NDT0_BAR_RESERVED1 = 1 ;
+static const uint8_t P9N2_PU_NPU0_SM0_NDT0_BAR_RESERVED1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM0_NDT0_BAR_CONFIG_GROUP = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM0_NDT0_BAR_CONFIG_GROUP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM0_NDT0_BAR_CONFIG_CHIP = 7 ;
+static const uint8_t P9N2_PU_NPU0_SM0_NDT0_BAR_CONFIG_CHIP_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM0_NDT0_BAR_CONFIG_ADDR = 10 ;
+static const uint8_t P9N2_PU_NPU0_SM0_NDT0_BAR_CONFIG_ADDR_LEN = 26 ;
+static const uint8_t P9N2_PU_NPU0_SM0_NDT0_BAR_CONFIG_POISON = 36 ;
+static const uint8_t P9N2_PU_NPU0_SM0_NDT0_BAR_RESERVED2 = 37 ;
+static const uint8_t P9N2_PU_NPU0_SM0_NDT0_BAR_RESERVED2_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM0_NDT0_BAR_CONFIG_SIZE = 39 ;
+static const uint8_t P9N2_PU_NPU0_SM0_NDT0_BAR_CONFIG_SIZE_LEN = 5 ;
+
+static const uint8_t P9N2_PU_NPU2_SM3_NDT0_BAR_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM3_NDT0_BAR_RESERVED1 = 1 ;
+static const uint8_t P9N2_PU_NPU2_SM3_NDT0_BAR_RESERVED1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM3_NDT0_BAR_CONFIG_GROUP = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM3_NDT0_BAR_CONFIG_GROUP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM3_NDT0_BAR_CONFIG_CHIP = 7 ;
+static const uint8_t P9N2_PU_NPU2_SM3_NDT0_BAR_CONFIG_CHIP_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM3_NDT0_BAR_CONFIG_ADDR = 10 ;
+static const uint8_t P9N2_PU_NPU2_SM3_NDT0_BAR_CONFIG_ADDR_LEN = 26 ;
+static const uint8_t P9N2_PU_NPU2_SM3_NDT0_BAR_CONFIG_POISON = 36 ;
+static const uint8_t P9N2_PU_NPU2_SM3_NDT0_BAR_RESERVED2 = 37 ;
+static const uint8_t P9N2_PU_NPU2_SM3_NDT0_BAR_RESERVED2_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM3_NDT0_BAR_CONFIG_SIZE = 39 ;
+static const uint8_t P9N2_PU_NPU2_SM3_NDT0_BAR_CONFIG_SIZE_LEN = 5 ;
+
+static const uint8_t P9N2_PU_NPU0_SM3_NDT0_BAR_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM3_NDT0_BAR_RESERVED1 = 1 ;
+static const uint8_t P9N2_PU_NPU0_SM3_NDT0_BAR_RESERVED1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM3_NDT0_BAR_CONFIG_GROUP = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM3_NDT0_BAR_CONFIG_GROUP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM3_NDT0_BAR_CONFIG_CHIP = 7 ;
+static const uint8_t P9N2_PU_NPU0_SM3_NDT0_BAR_CONFIG_CHIP_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM3_NDT0_BAR_CONFIG_ADDR = 10 ;
+static const uint8_t P9N2_PU_NPU0_SM3_NDT0_BAR_CONFIG_ADDR_LEN = 26 ;
+static const uint8_t P9N2_PU_NPU0_SM3_NDT0_BAR_CONFIG_POISON = 36 ;
+static const uint8_t P9N2_PU_NPU0_SM3_NDT0_BAR_RESERVED2 = 37 ;
+static const uint8_t P9N2_PU_NPU0_SM3_NDT0_BAR_RESERVED2_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM3_NDT0_BAR_CONFIG_SIZE = 39 ;
+static const uint8_t P9N2_PU_NPU0_SM3_NDT0_BAR_CONFIG_SIZE_LEN = 5 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM0_NDT0_BAR_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_NDT0_BAR_RESERVED1 = 1 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_NDT0_BAR_RESERVED1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_NDT0_BAR_CONFIG_GROUP = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_NDT0_BAR_CONFIG_GROUP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_NDT0_BAR_CONFIG_CHIP = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_NDT0_BAR_CONFIG_CHIP_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_NDT0_BAR_CONFIG_ADDR = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_NDT0_BAR_CONFIG_ADDR_LEN = 26 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_NDT0_BAR_CONFIG_POISON = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_NDT0_BAR_RESERVED2 = 37 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_NDT0_BAR_RESERVED2_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_NDT0_BAR_CONFIG_SIZE = 39 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_NDT0_BAR_CONFIG_SIZE_LEN = 5 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM1_NDT0_BAR_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_NDT0_BAR_RESERVED1 = 1 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_NDT0_BAR_RESERVED1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_NDT0_BAR_CONFIG_GROUP = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_NDT0_BAR_CONFIG_GROUP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_NDT0_BAR_CONFIG_CHIP = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_NDT0_BAR_CONFIG_CHIP_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_NDT0_BAR_CONFIG_ADDR = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_NDT0_BAR_CONFIG_ADDR_LEN = 26 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_NDT0_BAR_CONFIG_POISON = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_NDT0_BAR_RESERVED2 = 37 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_NDT0_BAR_RESERVED2_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_NDT0_BAR_CONFIG_SIZE = 39 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_NDT0_BAR_CONFIG_SIZE_LEN = 5 ;
+
+static const uint8_t P9N2_PU_NPU2_SM1_NDT0_BAR_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM1_NDT0_BAR_RESERVED1 = 1 ;
+static const uint8_t P9N2_PU_NPU2_SM1_NDT0_BAR_RESERVED1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM1_NDT0_BAR_CONFIG_GROUP = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM1_NDT0_BAR_CONFIG_GROUP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM1_NDT0_BAR_CONFIG_CHIP = 7 ;
+static const uint8_t P9N2_PU_NPU2_SM1_NDT0_BAR_CONFIG_CHIP_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM1_NDT0_BAR_CONFIG_ADDR = 10 ;
+static const uint8_t P9N2_PU_NPU2_SM1_NDT0_BAR_CONFIG_ADDR_LEN = 26 ;
+static const uint8_t P9N2_PU_NPU2_SM1_NDT0_BAR_CONFIG_POISON = 36 ;
+static const uint8_t P9N2_PU_NPU2_SM1_NDT0_BAR_RESERVED2 = 37 ;
+static const uint8_t P9N2_PU_NPU2_SM1_NDT0_BAR_RESERVED2_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM1_NDT0_BAR_CONFIG_SIZE = 39 ;
+static const uint8_t P9N2_PU_NPU2_SM1_NDT0_BAR_CONFIG_SIZE_LEN = 5 ;
+
+static const uint8_t P9N2_PU_NPU0_CTL_NDT0_BAR_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NPU0_CTL_NDT0_BAR_RESERVED1 = 1 ;
+static const uint8_t P9N2_PU_NPU0_CTL_NDT0_BAR_RESERVED1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU0_CTL_NDT0_BAR_CONFIG_GROUP = 3 ;
+static const uint8_t P9N2_PU_NPU0_CTL_NDT0_BAR_CONFIG_GROUP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_CTL_NDT0_BAR_CONFIG_CHIP = 7 ;
+static const uint8_t P9N2_PU_NPU0_CTL_NDT0_BAR_CONFIG_CHIP_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU0_CTL_NDT0_BAR_CONFIG_ADDR = 10 ;
+static const uint8_t P9N2_PU_NPU0_CTL_NDT0_BAR_CONFIG_ADDR_LEN = 26 ;
+static const uint8_t P9N2_PU_NPU0_CTL_NDT0_BAR_CONFIG_POISON = 36 ;
+static const uint8_t P9N2_PU_NPU0_CTL_NDT0_BAR_RESERVED2 = 37 ;
+static const uint8_t P9N2_PU_NPU0_CTL_NDT0_BAR_RESERVED2_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU0_CTL_NDT0_BAR_CONFIG_SIZE = 39 ;
+static const uint8_t P9N2_PU_NPU0_CTL_NDT0_BAR_CONFIG_SIZE_LEN = 5 ;
+
+static const uint8_t P9N2_PU_NPU2_SM0_NDT0_BAR_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM0_NDT0_BAR_RESERVED1 = 1 ;
+static const uint8_t P9N2_PU_NPU2_SM0_NDT0_BAR_RESERVED1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM0_NDT0_BAR_CONFIG_GROUP = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM0_NDT0_BAR_CONFIG_GROUP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM0_NDT0_BAR_CONFIG_CHIP = 7 ;
+static const uint8_t P9N2_PU_NPU2_SM0_NDT0_BAR_CONFIG_CHIP_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM0_NDT0_BAR_CONFIG_ADDR = 10 ;
+static const uint8_t P9N2_PU_NPU2_SM0_NDT0_BAR_CONFIG_ADDR_LEN = 26 ;
+static const uint8_t P9N2_PU_NPU2_SM0_NDT0_BAR_CONFIG_POISON = 36 ;
+static const uint8_t P9N2_PU_NPU2_SM0_NDT0_BAR_RESERVED2 = 37 ;
+static const uint8_t P9N2_PU_NPU2_SM0_NDT0_BAR_RESERVED2_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM0_NDT0_BAR_CONFIG_SIZE = 39 ;
+static const uint8_t P9N2_PU_NPU2_SM0_NDT0_BAR_CONFIG_SIZE_LEN = 5 ;
+
+static const uint8_t P9N2_PU_NPU2_CTL_NDT0_BAR_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NPU2_CTL_NDT0_BAR_RESERVED1 = 1 ;
+static const uint8_t P9N2_PU_NPU2_CTL_NDT0_BAR_RESERVED1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_CTL_NDT0_BAR_CONFIG_GROUP = 3 ;
+static const uint8_t P9N2_PU_NPU2_CTL_NDT0_BAR_CONFIG_GROUP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_CTL_NDT0_BAR_CONFIG_CHIP = 7 ;
+static const uint8_t P9N2_PU_NPU2_CTL_NDT0_BAR_CONFIG_CHIP_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU2_CTL_NDT0_BAR_CONFIG_ADDR = 10 ;
+static const uint8_t P9N2_PU_NPU2_CTL_NDT0_BAR_CONFIG_ADDR_LEN = 26 ;
+static const uint8_t P9N2_PU_NPU2_CTL_NDT0_BAR_CONFIG_POISON = 36 ;
+static const uint8_t P9N2_PU_NPU2_CTL_NDT0_BAR_RESERVED2 = 37 ;
+static const uint8_t P9N2_PU_NPU2_CTL_NDT0_BAR_RESERVED2_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_CTL_NDT0_BAR_CONFIG_SIZE = 39 ;
+static const uint8_t P9N2_PU_NPU2_CTL_NDT0_BAR_CONFIG_SIZE_LEN = 5 ;
+
+static const uint8_t P9N2_PU_NPU0_SM1_NDT0_BAR_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM1_NDT0_BAR_RESERVED1 = 1 ;
+static const uint8_t P9N2_PU_NPU0_SM1_NDT0_BAR_RESERVED1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM1_NDT0_BAR_CONFIG_GROUP = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM1_NDT0_BAR_CONFIG_GROUP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM1_NDT0_BAR_CONFIG_CHIP = 7 ;
+static const uint8_t P9N2_PU_NPU0_SM1_NDT0_BAR_CONFIG_CHIP_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM1_NDT0_BAR_CONFIG_ADDR = 10 ;
+static const uint8_t P9N2_PU_NPU0_SM1_NDT0_BAR_CONFIG_ADDR_LEN = 26 ;
+static const uint8_t P9N2_PU_NPU0_SM1_NDT0_BAR_CONFIG_POISON = 36 ;
+static const uint8_t P9N2_PU_NPU0_SM1_NDT0_BAR_RESERVED2 = 37 ;
+static const uint8_t P9N2_PU_NPU0_SM1_NDT0_BAR_RESERVED2_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM1_NDT0_BAR_CONFIG_SIZE = 39 ;
+static const uint8_t P9N2_PU_NPU0_SM1_NDT0_BAR_CONFIG_SIZE_LEN = 5 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_CTL_NDT0_BAR_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_NDT0_BAR_RESERVED1 = 1 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_NDT0_BAR_RESERVED1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_NDT0_BAR_CONFIG_GROUP = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_NDT0_BAR_CONFIG_GROUP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_NDT0_BAR_CONFIG_CHIP = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_NDT0_BAR_CONFIG_CHIP_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_NDT0_BAR_CONFIG_ADDR = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_NDT0_BAR_CONFIG_ADDR_LEN = 26 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_NDT0_BAR_CONFIG_POISON = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_NDT0_BAR_RESERVED2 = 37 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_NDT0_BAR_RESERVED2_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_NDT0_BAR_CONFIG_SIZE = 39 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_NDT0_BAR_CONFIG_SIZE_LEN = 5 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM3_NDT0_BAR_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_NDT0_BAR_RESERVED1 = 1 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_NDT0_BAR_RESERVED1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_NDT0_BAR_CONFIG_GROUP = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_NDT0_BAR_CONFIG_GROUP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_NDT0_BAR_CONFIG_CHIP = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_NDT0_BAR_CONFIG_CHIP_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_NDT0_BAR_CONFIG_ADDR = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_NDT0_BAR_CONFIG_ADDR_LEN = 26 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_NDT0_BAR_CONFIG_POISON = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_NDT0_BAR_RESERVED2 = 37 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_NDT0_BAR_RESERVED2_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_NDT0_BAR_CONFIG_SIZE = 39 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_NDT0_BAR_CONFIG_SIZE_LEN = 5 ;
+
+static const uint8_t P9N2_PU_NPU0_SM0_NDT1_BAR_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM0_NDT1_BAR_RESERVED1 = 1 ;
+static const uint8_t P9N2_PU_NPU0_SM0_NDT1_BAR_RESERVED1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM0_NDT1_BAR_CONFIG_GROUP = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM0_NDT1_BAR_CONFIG_GROUP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM0_NDT1_BAR_CONFIG_CHIP = 7 ;
+static const uint8_t P9N2_PU_NPU0_SM0_NDT1_BAR_CONFIG_CHIP_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM0_NDT1_BAR_CONFIG_ADDR = 10 ;
+static const uint8_t P9N2_PU_NPU0_SM0_NDT1_BAR_CONFIG_ADDR_LEN = 26 ;
+static const uint8_t P9N2_PU_NPU0_SM0_NDT1_BAR_CONFIG_POISON = 36 ;
+static const uint8_t P9N2_PU_NPU0_SM0_NDT1_BAR_RESERVED2 = 37 ;
+static const uint8_t P9N2_PU_NPU0_SM0_NDT1_BAR_RESERVED2_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM0_NDT1_BAR_CONFIG_SIZE = 39 ;
+static const uint8_t P9N2_PU_NPU0_SM0_NDT1_BAR_CONFIG_SIZE_LEN = 5 ;
+
+static const uint8_t P9N2_PU_NPU2_SM3_NDT1_BAR_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM3_NDT1_BAR_RESERVED1 = 1 ;
+static const uint8_t P9N2_PU_NPU2_SM3_NDT1_BAR_RESERVED1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM3_NDT1_BAR_CONFIG_GROUP = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM3_NDT1_BAR_CONFIG_GROUP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM3_NDT1_BAR_CONFIG_CHIP = 7 ;
+static const uint8_t P9N2_PU_NPU2_SM3_NDT1_BAR_CONFIG_CHIP_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM3_NDT1_BAR_CONFIG_ADDR = 10 ;
+static const uint8_t P9N2_PU_NPU2_SM3_NDT1_BAR_CONFIG_ADDR_LEN = 26 ;
+static const uint8_t P9N2_PU_NPU2_SM3_NDT1_BAR_CONFIG_POISON = 36 ;
+static const uint8_t P9N2_PU_NPU2_SM3_NDT1_BAR_RESERVED2 = 37 ;
+static const uint8_t P9N2_PU_NPU2_SM3_NDT1_BAR_RESERVED2_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM3_NDT1_BAR_CONFIG_SIZE = 39 ;
+static const uint8_t P9N2_PU_NPU2_SM3_NDT1_BAR_CONFIG_SIZE_LEN = 5 ;
+
+static const uint8_t P9N2_PU_NPU0_SM3_NDT1_BAR_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM3_NDT1_BAR_RESERVED1 = 1 ;
+static const uint8_t P9N2_PU_NPU0_SM3_NDT1_BAR_RESERVED1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM3_NDT1_BAR_CONFIG_GROUP = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM3_NDT1_BAR_CONFIG_GROUP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM3_NDT1_BAR_CONFIG_CHIP = 7 ;
+static const uint8_t P9N2_PU_NPU0_SM3_NDT1_BAR_CONFIG_CHIP_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM3_NDT1_BAR_CONFIG_ADDR = 10 ;
+static const uint8_t P9N2_PU_NPU0_SM3_NDT1_BAR_CONFIG_ADDR_LEN = 26 ;
+static const uint8_t P9N2_PU_NPU0_SM3_NDT1_BAR_CONFIG_POISON = 36 ;
+static const uint8_t P9N2_PU_NPU0_SM3_NDT1_BAR_RESERVED2 = 37 ;
+static const uint8_t P9N2_PU_NPU0_SM3_NDT1_BAR_RESERVED2_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM3_NDT1_BAR_CONFIG_SIZE = 39 ;
+static const uint8_t P9N2_PU_NPU0_SM3_NDT1_BAR_CONFIG_SIZE_LEN = 5 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM0_NDT1_BAR_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_NDT1_BAR_RESERVED1 = 1 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_NDT1_BAR_RESERVED1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_NDT1_BAR_CONFIG_GROUP = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_NDT1_BAR_CONFIG_GROUP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_NDT1_BAR_CONFIG_CHIP = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_NDT1_BAR_CONFIG_CHIP_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_NDT1_BAR_CONFIG_ADDR = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_NDT1_BAR_CONFIG_ADDR_LEN = 26 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_NDT1_BAR_CONFIG_POISON = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_NDT1_BAR_RESERVED2 = 37 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_NDT1_BAR_RESERVED2_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_NDT1_BAR_CONFIG_SIZE = 39 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_NDT1_BAR_CONFIG_SIZE_LEN = 5 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM1_NDT1_BAR_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_NDT1_BAR_RESERVED1 = 1 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_NDT1_BAR_RESERVED1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_NDT1_BAR_CONFIG_GROUP = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_NDT1_BAR_CONFIG_GROUP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_NDT1_BAR_CONFIG_CHIP = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_NDT1_BAR_CONFIG_CHIP_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_NDT1_BAR_CONFIG_ADDR = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_NDT1_BAR_CONFIG_ADDR_LEN = 26 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_NDT1_BAR_CONFIG_POISON = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_NDT1_BAR_RESERVED2 = 37 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_NDT1_BAR_RESERVED2_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_NDT1_BAR_CONFIG_SIZE = 39 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_NDT1_BAR_CONFIG_SIZE_LEN = 5 ;
+
+static const uint8_t P9N2_PU_NPU2_SM1_NDT1_BAR_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM1_NDT1_BAR_RESERVED1 = 1 ;
+static const uint8_t P9N2_PU_NPU2_SM1_NDT1_BAR_RESERVED1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM1_NDT1_BAR_CONFIG_GROUP = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM1_NDT1_BAR_CONFIG_GROUP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM1_NDT1_BAR_CONFIG_CHIP = 7 ;
+static const uint8_t P9N2_PU_NPU2_SM1_NDT1_BAR_CONFIG_CHIP_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM1_NDT1_BAR_CONFIG_ADDR = 10 ;
+static const uint8_t P9N2_PU_NPU2_SM1_NDT1_BAR_CONFIG_ADDR_LEN = 26 ;
+static const uint8_t P9N2_PU_NPU2_SM1_NDT1_BAR_CONFIG_POISON = 36 ;
+static const uint8_t P9N2_PU_NPU2_SM1_NDT1_BAR_RESERVED2 = 37 ;
+static const uint8_t P9N2_PU_NPU2_SM1_NDT1_BAR_RESERVED2_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM1_NDT1_BAR_CONFIG_SIZE = 39 ;
+static const uint8_t P9N2_PU_NPU2_SM1_NDT1_BAR_CONFIG_SIZE_LEN = 5 ;
+
+static const uint8_t P9N2_PU_NPU0_CTL_NDT1_BAR_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NPU0_CTL_NDT1_BAR_RESERVED1 = 1 ;
+static const uint8_t P9N2_PU_NPU0_CTL_NDT1_BAR_RESERVED1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU0_CTL_NDT1_BAR_CONFIG_GROUP = 3 ;
+static const uint8_t P9N2_PU_NPU0_CTL_NDT1_BAR_CONFIG_GROUP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_CTL_NDT1_BAR_CONFIG_CHIP = 7 ;
+static const uint8_t P9N2_PU_NPU0_CTL_NDT1_BAR_CONFIG_CHIP_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU0_CTL_NDT1_BAR_CONFIG_ADDR = 10 ;
+static const uint8_t P9N2_PU_NPU0_CTL_NDT1_BAR_CONFIG_ADDR_LEN = 26 ;
+static const uint8_t P9N2_PU_NPU0_CTL_NDT1_BAR_CONFIG_POISON = 36 ;
+static const uint8_t P9N2_PU_NPU0_CTL_NDT1_BAR_RESERVED2 = 37 ;
+static const uint8_t P9N2_PU_NPU0_CTL_NDT1_BAR_RESERVED2_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU0_CTL_NDT1_BAR_CONFIG_SIZE = 39 ;
+static const uint8_t P9N2_PU_NPU0_CTL_NDT1_BAR_CONFIG_SIZE_LEN = 5 ;
+
+static const uint8_t P9N2_PU_NPU2_SM0_NDT1_BAR_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM0_NDT1_BAR_RESERVED1 = 1 ;
+static const uint8_t P9N2_PU_NPU2_SM0_NDT1_BAR_RESERVED1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM0_NDT1_BAR_CONFIG_GROUP = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM0_NDT1_BAR_CONFIG_GROUP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM0_NDT1_BAR_CONFIG_CHIP = 7 ;
+static const uint8_t P9N2_PU_NPU2_SM0_NDT1_BAR_CONFIG_CHIP_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM0_NDT1_BAR_CONFIG_ADDR = 10 ;
+static const uint8_t P9N2_PU_NPU2_SM0_NDT1_BAR_CONFIG_ADDR_LEN = 26 ;
+static const uint8_t P9N2_PU_NPU2_SM0_NDT1_BAR_CONFIG_POISON = 36 ;
+static const uint8_t P9N2_PU_NPU2_SM0_NDT1_BAR_RESERVED2 = 37 ;
+static const uint8_t P9N2_PU_NPU2_SM0_NDT1_BAR_RESERVED2_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM0_NDT1_BAR_CONFIG_SIZE = 39 ;
+static const uint8_t P9N2_PU_NPU2_SM0_NDT1_BAR_CONFIG_SIZE_LEN = 5 ;
+
+static const uint8_t P9N2_PU_NPU2_CTL_NDT1_BAR_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NPU2_CTL_NDT1_BAR_RESERVED1 = 1 ;
+static const uint8_t P9N2_PU_NPU2_CTL_NDT1_BAR_RESERVED1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_CTL_NDT1_BAR_CONFIG_GROUP = 3 ;
+static const uint8_t P9N2_PU_NPU2_CTL_NDT1_BAR_CONFIG_GROUP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_CTL_NDT1_BAR_CONFIG_CHIP = 7 ;
+static const uint8_t P9N2_PU_NPU2_CTL_NDT1_BAR_CONFIG_CHIP_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU2_CTL_NDT1_BAR_CONFIG_ADDR = 10 ;
+static const uint8_t P9N2_PU_NPU2_CTL_NDT1_BAR_CONFIG_ADDR_LEN = 26 ;
+static const uint8_t P9N2_PU_NPU2_CTL_NDT1_BAR_CONFIG_POISON = 36 ;
+static const uint8_t P9N2_PU_NPU2_CTL_NDT1_BAR_RESERVED2 = 37 ;
+static const uint8_t P9N2_PU_NPU2_CTL_NDT1_BAR_RESERVED2_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_CTL_NDT1_BAR_CONFIG_SIZE = 39 ;
+static const uint8_t P9N2_PU_NPU2_CTL_NDT1_BAR_CONFIG_SIZE_LEN = 5 ;
+
+static const uint8_t P9N2_PU_NPU0_SM1_NDT1_BAR_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM1_NDT1_BAR_RESERVED1 = 1 ;
+static const uint8_t P9N2_PU_NPU0_SM1_NDT1_BAR_RESERVED1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM1_NDT1_BAR_CONFIG_GROUP = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM1_NDT1_BAR_CONFIG_GROUP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM1_NDT1_BAR_CONFIG_CHIP = 7 ;
+static const uint8_t P9N2_PU_NPU0_SM1_NDT1_BAR_CONFIG_CHIP_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM1_NDT1_BAR_CONFIG_ADDR = 10 ;
+static const uint8_t P9N2_PU_NPU0_SM1_NDT1_BAR_CONFIG_ADDR_LEN = 26 ;
+static const uint8_t P9N2_PU_NPU0_SM1_NDT1_BAR_CONFIG_POISON = 36 ;
+static const uint8_t P9N2_PU_NPU0_SM1_NDT1_BAR_RESERVED2 = 37 ;
+static const uint8_t P9N2_PU_NPU0_SM1_NDT1_BAR_RESERVED2_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM1_NDT1_BAR_CONFIG_SIZE = 39 ;
+static const uint8_t P9N2_PU_NPU0_SM1_NDT1_BAR_CONFIG_SIZE_LEN = 5 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_CTL_NDT1_BAR_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_NDT1_BAR_RESERVED1 = 1 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_NDT1_BAR_RESERVED1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_NDT1_BAR_CONFIG_GROUP = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_NDT1_BAR_CONFIG_GROUP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_NDT1_BAR_CONFIG_CHIP = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_NDT1_BAR_CONFIG_CHIP_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_NDT1_BAR_CONFIG_ADDR = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_NDT1_BAR_CONFIG_ADDR_LEN = 26 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_NDT1_BAR_CONFIG_POISON = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_NDT1_BAR_RESERVED2 = 37 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_NDT1_BAR_RESERVED2_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_NDT1_BAR_CONFIG_SIZE = 39 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_NDT1_BAR_CONFIG_SIZE_LEN = 5 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM3_NDT1_BAR_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_NDT1_BAR_RESERVED1 = 1 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_NDT1_BAR_RESERVED1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_NDT1_BAR_CONFIG_GROUP = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_NDT1_BAR_CONFIG_GROUP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_NDT1_BAR_CONFIG_CHIP = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_NDT1_BAR_CONFIG_CHIP_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_NDT1_BAR_CONFIG_ADDR = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_NDT1_BAR_CONFIG_ADDR_LEN = 26 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_NDT1_BAR_CONFIG_POISON = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_NDT1_BAR_RESERVED2 = 37 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_NDT1_BAR_RESERVED2_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_NDT1_BAR_CONFIG_SIZE = 39 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_NDT1_BAR_CONFIG_SIZE_LEN = 5 ;
+
+static const uint8_t P9N2_PEC_NESTTRC_REG_TRACE_MUX_SEL_A = 0 ;
+static const uint8_t P9N2_PEC_NESTTRC_REG_TRACE_MUX_SEL_A_LEN = 4 ;
+static const uint8_t P9N2_PEC_NESTTRC_REG_TRACE_MUX_SEL_B = 4 ;
+static const uint8_t P9N2_PEC_NESTTRC_REG_TRACE_MUX_SEL_B_LEN = 4 ;
+static const uint8_t P9N2_PEC_NESTTRC_REG_TRACE_MUX_SEL_C = 8 ;
+static const uint8_t P9N2_PEC_NESTTRC_REG_TRACE_MUX_SEL_C_LEN = 4 ;
+static const uint8_t P9N2_PEC_NESTTRC_REG_TRACE_MUX_SEL_D = 12 ;
+static const uint8_t P9N2_PEC_NESTTRC_REG_TRACE_MUX_SEL_D_LEN = 4 ;
+static const uint8_t P9N2_PEC_NESTTRC_REG_TRACE_ENABLE = 16 ;
+
+static const uint8_t P9N2_PEC_STACK0_NET_CTRL0_CHIPLET_ENABLE = 0 ;
+static const uint8_t P9N2_PEC_STACK0_NET_CTRL0_PCB_EP_RESET = 1 ;
+static const uint8_t P9N2_PEC_STACK0_NET_CTRL0_CLK_ASYNC_RESET = 2 ;
+static const uint8_t P9N2_PEC_STACK0_NET_CTRL0_PLL_TEST_EN = 3 ;
+static const uint8_t P9N2_PEC_STACK0_NET_CTRL0_PLL_RESET = 4 ;
+static const uint8_t P9N2_PEC_STACK0_NET_CTRL0_PLL_BYPASS = 5 ;
+static const uint8_t P9N2_PEC_STACK0_NET_CTRL0_VITAL_SCAN = 6 ;
+static const uint8_t P9N2_PEC_STACK0_NET_CTRL0_VITAL_SCAN_IN = 7 ;
+static const uint8_t P9N2_PEC_STACK0_NET_CTRL0_VITAL_PHASE = 8 ;
+static const uint8_t P9N2_PEC_STACK0_NET_CTRL0_FLUSH_ALIGN_OVR = 9 ;
+static const uint8_t P9N2_PEC_STACK0_NET_CTRL0_VITAL_AL = 10 ;
+static const uint8_t P9N2_PEC_STACK0_NET_CTRL0_ACT_DIS = 11 ;
+static const uint8_t P9N2_PEC_STACK0_NET_CTRL0_MPW1 = 12 ;
+static const uint8_t P9N2_PEC_STACK0_NET_CTRL0_MPW2 = 13 ;
+static const uint8_t P9N2_PEC_STACK0_NET_CTRL0_MPW3 = 14 ;
+static const uint8_t P9N2_PEC_STACK0_NET_CTRL0_DELAY_LCLKR = 15 ;
+static const uint8_t P9N2_PEC_STACK0_NET_CTRL0_VITAL_THOLD = 16 ;
+static const uint8_t P9N2_PEC_STACK0_NET_CTRL0_FLUSH_SCAN_N = 17 ;
+static const uint8_t P9N2_PEC_STACK0_NET_CTRL0_FENCE_EN = 18 ;
+static const uint8_t P9N2_PEC_STACK0_NET_CTRL0_CPLT_RCTRL = 19 ;
+static const uint8_t P9N2_PEC_STACK0_NET_CTRL0_CPLT_DCTRL = 20 ;
+static const uint8_t P9N2_PEC_STACK0_NET_CTRL0_ADJ_FUNC_CLKSEL = 22 ;
+static const uint8_t P9N2_PEC_STACK0_NET_CTRL0_TP_FENCE_PCB = 25 ;
+static const uint8_t P9N2_PEC_STACK0_NET_CTRL0_LVLTRANS_FENCE = 26 ;
+static const uint8_t P9N2_PEC_STACK0_NET_CTRL0_ARRAY_WRITE_ASSIST_EN = 27 ;
+static const uint8_t P9N2_PEC_STACK0_NET_CTRL0_HTB_INTEST = 28 ;
+static const uint8_t P9N2_PEC_STACK0_NET_CTRL0_HTB_EXTEST = 29 ;
+static const uint8_t P9N2_PEC_STACK0_NET_CTRL0_PM_ACCESS = 30 ;
+static const uint8_t P9N2_PEC_STACK0_NET_CTRL0_PLLFORCE_OUT_EN = 31 ;
+
+static const uint8_t P9N2_PEC_STACK0_NET_CTRL1_PLL_CLKIN_SEL = 0 ;
+static const uint8_t P9N2_PEC_STACK0_NET_CTRL1_CLK_DCC_BYPASS_EN = 1 ;
+static const uint8_t P9N2_PEC_STACK0_NET_CTRL1_CLK_PDLY_BYPASS_EN = 2 ;
+static const uint8_t P9N2_PEC_STACK0_NET_CTRL1_CLK_DIV_BYPASS_EN = 3 ;
+static const uint8_t P9N2_PEC_STACK0_NET_CTRL1_REFCLK_CLKMUX0_SEL = 4 ;
+static const uint8_t P9N2_PEC_STACK0_NET_CTRL1_REFCLK_CLKMUX1_SEL = 5 ;
+static const uint8_t P9N2_PEC_STACK0_NET_CTRL1_PLL_BNDY_BYPASS_EN = 6 ;
+static const uint8_t P9N2_PEC_STACK0_NET_CTRL1_DPLL_TEST_SEL = 8 ;
+static const uint8_t P9N2_PEC_STACK0_NET_CTRL1_DPLL_TEST_SEL_LEN = 8 ;
+static const uint8_t P9N2_PEC_STACK0_NET_CTRL1_SB_STRENGTH = 16 ;
+static const uint8_t P9N2_PEC_STACK0_NET_CTRL1_SB_STRENGTH_LEN = 4 ;
+static const uint8_t P9N2_PEC_STACK0_NET_CTRL1_ASYNC_TYPE = 20 ;
+static const uint8_t P9N2_PEC_STACK0_NET_CTRL1_ASYNC_OBS = 21 ;
+static const uint8_t P9N2_PEC_STACK0_NET_CTRL1_CPM_CAL_SET = 22 ;
+static const uint8_t P9N2_PEC_STACK0_NET_CTRL1_SENSEADJ_RESET0 = 23 ;
+static const uint8_t P9N2_PEC_STACK0_NET_CTRL1_SENSEADJ_RESET1 = 24 ;
+static const uint8_t P9N2_PEC_STACK0_NET_CTRL1_CLK_PULSE_EN = 25 ;
+static const uint8_t P9N2_PEC_STACK0_NET_CTRL1_CLK_PULSE_MODE = 26 ;
+static const uint8_t P9N2_PEC_STACK0_NET_CTRL1_CLK_PULSE_MODE_LEN = 2 ;
+static const uint8_t P9N2_PEC_STACK0_NET_CTRL1_PCB_ACCESS = 28 ;
+static const uint8_t P9N2_PEC_STACK0_NET_CTRL1_PCB_ACCESS_LEN = 4 ;
+
+static const uint8_t P9N2_PHB_NFIRACTION0_REG_NFIRACTION0 = 0 ;
+static const uint8_t P9N2_PHB_NFIRACTION0_REG_NFIRACTION0_LEN = 30 ;
+
+static const uint8_t P9N2_PEC_STACK0_NFIRACTION0_REG_NFIRACTION0 = 0 ;
+static const uint8_t P9N2_PEC_STACK0_NFIRACTION0_REG_NFIRACTION0_LEN = 30 ;
+
+static const uint8_t P9N2_PHB_NFIRACTION1_REG_NFIRACTION1 = 0 ;
+static const uint8_t P9N2_PHB_NFIRACTION1_REG_NFIRACTION1_LEN = 30 ;
+
+static const uint8_t P9N2_PEC_STACK0_NFIRACTION1_REG_NFIRACTION1 = 0 ;
+static const uint8_t P9N2_PEC_STACK0_NFIRACTION1_REG_NFIRACTION1_LEN = 30 ;
+
+static const uint8_t P9N2_PHB_NFIRMASK_REG_NFIRMASK = 0 ;
+static const uint8_t P9N2_PHB_NFIRMASK_REG_NFIRMASK_LEN = 30 ;
+
+static const uint8_t P9N2_PEC_STACK0_NFIRMASK_REG_NFIRMASK = 0 ;
+static const uint8_t P9N2_PEC_STACK0_NFIRMASK_REG_NFIRMASK_LEN = 30 ;
+
+static const uint8_t P9N2_PHB_NFIR_REG_NFIRNFIR = 0 ;
+static const uint8_t P9N2_PHB_NFIR_REG_NFIRNFIR_LEN = 30 ;
+
+static const uint8_t P9N2_PEC_STACK0_NFIR_REG_NFIRNFIR = 0 ;
+static const uint8_t P9N2_PEC_STACK0_NFIR_REG_NFIRNFIR_LEN = 30 ;
+
+static const uint8_t P9N2_PU_NOTRUST_BAR0_UNTRUSTED = 14 ;
+static const uint8_t P9N2_PU_NOTRUST_BAR0_UNTRUSTED_LEN = 30 ;
+
+static const uint8_t P9N2_PU_NOTRUST_BAR0MASK_UNTRUSTED = 14 ;
+static const uint8_t P9N2_PU_NOTRUST_BAR0MASK_UNTRUSTED_LEN = 30 ;
+
+static const uint8_t P9N2_PU_NOTRUST_BAR1_UNTRUSTED = 14 ;
+static const uint8_t P9N2_PU_NOTRUST_BAR1_UNTRUSTED_LEN = 30 ;
+
+static const uint8_t P9N2_PU_NOTRUST_BAR1MASK_UNTRUSTED = 14 ;
+static const uint8_t P9N2_PU_NOTRUST_BAR1MASK_UNTRUSTED_LEN = 30 ;
+
+static const uint8_t P9N2__SM0_NPU_ATS_DEBUG_ENABLE = 0 ;
+static const uint8_t P9N2__SM0_NPU_ATS_DEBUG_0_SELECT = 1 ;
+static const uint8_t P9N2__SM0_NPU_ATS_DEBUG_0_SELECT_LEN = 3 ;
+static const uint8_t P9N2__SM0_NPU_ATS_DEBUG_1_SELECT = 4 ;
+static const uint8_t P9N2__SM0_NPU_ATS_DEBUG_1_SELECT_LEN = 3 ;
+
+static const uint8_t P9N2__SM0_NPU_AT_ECC_INJECT_MODE = 0 ;
+static const uint8_t P9N2__SM0_NPU_AT_ECC_INJECT_MODE_LEN = 2 ;
+static const uint8_t P9N2__SM0_NPU_AT_ECC_INJECT_TYPE = 2 ;
+static const uint8_t P9N2__SM0_NPU_AT_ECC_INJECT_TYPE_LEN = 2 ;
+static const uint8_t P9N2__SM0_NPU_AT_ECC_INJECT_ENABLE = 4 ;
+static const uint8_t P9N2__SM0_NPU_AT_ECC_ARRAY_SELECT = 5 ;
+static const uint8_t P9N2__SM0_NPU_AT_ECC_ARRAY_SELECT_LEN = 4 ;
+
+static const uint8_t P9N2__SM1_NPU_AT_ESMR_IDIAL_ATS_ESR_MSK = 0 ;
+static const uint8_t P9N2__SM1_NPU_AT_ESMR_IDIAL_ATS_ESR_MSK_LEN = 20 ;
+
+static const uint8_t P9N2__SM1_NPU_AT_ESR_IDIAL_ATS = 0 ;
+static const uint8_t P9N2__SM1_NPU_AT_ESR_IDIAL_ATS_LEN = 20 ;
+
+static const uint8_t P9N2__SM1_NPU_AT_FESMR_IDIAL_ATS_FER_MSK = 0 ;
+static const uint8_t P9N2__SM1_NPU_AT_FESMR_IDIAL_ATS_FER_MSK_LEN = 20 ;
+
+static const uint8_t P9N2__SM1_NPU_AT_FESR_FIRST_ERROR_CAPTURED = 0 ;
+static const uint8_t P9N2__SM1_NPU_AT_FESR_FIRST_ERROR_SPARE = 1 ;
+static const uint8_t P9N2__SM1_NPU_AT_FESR_FIRST_ERROR_SPARE_LEN = 2 ;
+static const uint8_t P9N2__SM1_NPU_AT_FESR_FIRST_ERROR_DECODE = 3 ;
+static const uint8_t P9N2__SM1_NPU_AT_FESR_FIRST_ERROR_DECODE_LEN = 5 ;
+static const uint8_t P9N2__SM1_NPU_AT_FESR_FIRST_ERROR_INFO = 8 ;
+static const uint8_t P9N2__SM1_NPU_AT_FESR_FIRST_ERROR_INFO_LEN = 56 ;
+
+static const uint8_t P9N2__SM0_NPU_AT_PMU_CNT_CNT0 = 0 ;
+static const uint8_t P9N2__SM0_NPU_AT_PMU_CNT_CNT0_LEN = 16 ;
+static const uint8_t P9N2__SM0_NPU_AT_PMU_CNT_CNT1 = 16 ;
+static const uint8_t P9N2__SM0_NPU_AT_PMU_CNT_CNT1_LEN = 16 ;
+static const uint8_t P9N2__SM0_NPU_AT_PMU_CNT_CNT2 = 32 ;
+static const uint8_t P9N2__SM0_NPU_AT_PMU_CNT_CNT2_LEN = 16 ;
+static const uint8_t P9N2__SM0_NPU_AT_PMU_CNT_CNT3 = 48 ;
+static const uint8_t P9N2__SM0_NPU_AT_PMU_CNT_CNT3_LEN = 16 ;
+
+static const uint8_t P9N2__SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2__SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_RESETMODE = 1 ;
+static const uint8_t P9N2__SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_FREEZEMODE = 2 ;
+static const uint8_t P9N2__SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_DISABLE_PMISC = 3 ;
+static const uint8_t P9N2__SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_PMISC_MODE = 4 ;
+static const uint8_t P9N2__SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_CASCADE = 5 ;
+static const uint8_t P9N2__SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_CASCADE_LEN = 3 ;
+static const uint8_t P9N2__SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_PRESCALE_C0 = 8 ;
+static const uint8_t P9N2__SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_PRESCALE_C0_LEN = 2 ;
+static const uint8_t P9N2__SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_PRESCALE_C1 = 10 ;
+static const uint8_t P9N2__SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_PRESCALE_C1_LEN = 2 ;
+static const uint8_t P9N2__SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_PRESCALE_C2 = 12 ;
+static const uint8_t P9N2__SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_PRESCALE_C2_LEN = 2 ;
+static const uint8_t P9N2__SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_PRESCALE_C3 = 14 ;
+static const uint8_t P9N2__SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_PRESCALE_C3_LEN = 2 ;
+static const uint8_t P9N2__SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_OPERATION_C0 = 16 ;
+static const uint8_t P9N2__SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_OPERATION_C0_LEN = 2 ;
+static const uint8_t P9N2__SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_OPERATION_C1 = 18 ;
+static const uint8_t P9N2__SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_OPERATION_C1_LEN = 2 ;
+static const uint8_t P9N2__SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_OPERATION_C2 = 20 ;
+static const uint8_t P9N2__SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_OPERATION_C2_LEN = 2 ;
+static const uint8_t P9N2__SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_OPERATION_C3 = 22 ;
+static const uint8_t P9N2__SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_OPERATION_C3_LEN = 2 ;
+static const uint8_t P9N2__SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_EVENTS = 24 ;
+static const uint8_t P9N2__SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_EVENTS_LEN = 3 ;
+static const uint8_t P9N2__SM0_NPU_AT_PMU_CTRL_CFG_PE_MATCH0 = 27 ;
+static const uint8_t P9N2__SM0_NPU_AT_PMU_CTRL_CFG_PE_MATCH0_LEN = 5 ;
+static const uint8_t P9N2__SM0_NPU_AT_PMU_CTRL_CFG_PE_MATCH1 = 32 ;
+static const uint8_t P9N2__SM0_NPU_AT_PMU_CTRL_CFG_PE_MATCH1_LEN = 5 ;
+static const uint8_t P9N2__SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_SPARE = 37 ;
+static const uint8_t P9N2__SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_SPARE_LEN = 5 ;
+
+static const uint8_t P9N2__SM1_NPU_Q_DMA_R_QUIESCE = 0 ;
+static const uint8_t P9N2__SM1_NPU_Q_DMA_R_QUIESCE_AUTO_RESET = 1 ;
+static const uint8_t P9N2__SM1_NPU_Q_DMA_R_RESPONSE = 4 ;
+static const uint8_t P9N2__SM1_NPU_Q_DMA_R_TCE_RESPONSE = 6 ;
+
+static const uint8_t P9N2__CTL_NPU_VERSION_RSVD0 = 0 ;
+static const uint8_t P9N2__CTL_NPU_VERSION_RSVD0_LEN = 24 ;
+static const uint8_t P9N2__CTL_NPU_VERSION_MAJOR = 24 ;
+static const uint8_t P9N2__CTL_NPU_VERSION_MAJOR_LEN = 8 ;
+static const uint8_t P9N2__CTL_NPU_VERSION_RSVD1 = 32 ;
+static const uint8_t P9N2__CTL_NPU_VERSION_RSVD1_LEN = 16 ;
+static const uint8_t P9N2__CTL_NPU_VERSION_MINOR = 48 ;
+static const uint8_t P9N2__CTL_NPU_VERSION_MINOR_LEN = 16 ;
+
+static const uint8_t P9N2_PEC_NRDSTKOVR_REG_STK0 = 0 ;
+static const uint8_t P9N2_PEC_NRDSTKOVR_REG_STK0_LEN = 32 ;
+static const uint8_t P9N2_PEC_NRDSTKOVR_REG_STK1 = 32 ;
+static const uint8_t P9N2_PEC_NRDSTKOVR_REG_STK1_LEN = 16 ;
+static const uint8_t P9N2_PEC_NRDSTKOVR_REG_ENABLE = 48 ;
+
+static const uint8_t P9N2_PEC_NSTQSTKOVR_REG_STK0 = 0 ;
+static const uint8_t P9N2_PEC_NSTQSTKOVR_REG_STK0_LEN = 8 ;
+static const uint8_t P9N2_PEC_NSTQSTKOVR_REG_STK1 = 8 ;
+static const uint8_t P9N2_PEC_NSTQSTKOVR_REG_STK1_LEN = 4 ;
+static const uint8_t P9N2_PEC_NSTQSTKOVR_REG_ENABLE = 12 ;
+
+static const uint8_t P9N2_PEC_NWRSTKOVR_REG_STK0 = 0 ;
+static const uint8_t P9N2_PEC_NWRSTKOVR_REG_STK0_LEN = 16 ;
+static const uint8_t P9N2_PEC_NWRSTKOVR_REG_STK1 = 16 ;
+static const uint8_t P9N2_PEC_NWRSTKOVR_REG_STK1_LEN = 8 ;
+static const uint8_t P9N2_PEC_NWRSTKOVR_REG_ENABLE = 24 ;
+
+static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_DMA_WR_DISABLE_LN = 0 ;
+static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_DMA_WR_DISABLE_GROUP = 1 ;
+static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_DMA_WR_DISABLE_VG_NOT_SYS = 2 ;
+static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_DMA_WR_DISABLE_NN_RN = 3 ;
+static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_DMA_RD_DISABLE_LN = 4 ;
+static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_DMA_RD_DISABLE_GROUP = 5 ;
+static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_DMA_RD_DISABLE_VG_NOT_SYS = 6 ;
+static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_DMA_RD_DISABLE_NN_RN = 7 ;
+static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_UMAC_WR_DISABLE_LN = 8 ;
+static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_UMAC_WR_DISABLE_GROUP = 9 ;
+static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_UMAC_WR_DISABLE_VG_NOT_SYS = 10 ;
+static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_UMAC_WR_DISABLE_NN_RN = 11 ;
+static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_UMAC_RD_DISABLE_LN = 12 ;
+static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_UMAC_RD_DISABLE_GROUP = 13 ;
+static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_UMAC_RD_DISABLE_VG_NOT_SYS = 14 ;
+static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_UMAC_RD_DISABLE_NN_RN = 15 ;
+static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_NX_FREEZE_MODES = 16 ;
+static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_NX_FREEZE_MODES_LEN = 2 ;
+static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_RESERVED = 18 ;
+static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_RESERVED_LEN = 2 ;
+static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_DMA_WR_NOT_INJECT = 20 ;
+static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_DMA_PARTIAL_WRT_NOT_INJECT = 21 ;
+static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_RD_GO_M_QOS = 22 ;
+static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_ADDR_BAR = 23 ;
+static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_SKIP_G = 24 ;
+static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_DATA_ARB_LFSR_CONFIG = 25 ;
+static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_DATA_ARB_LFSR_CONFIG_LEN = 2 ;
+static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_HANG_SM_ON_ARE = 27 ;
+static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_HANG_SM_ON_LINK_FAIL = 28 ;
+static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_CFG_PUMP = 29 ;
+static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_DISABLE_FLOW_SCOPE = 30 ;
+static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_DISABLE_PMU_SNOOPING = 31 ;
+static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_ENDABLE_PMU_CNT_RESET = 32 ;
+static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_DISABLE_WRP = 33 ;
+static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_SMF_CONFIG = 34 ;
+static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_SMF_CONFIG_LEN = 2 ;
+static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_UNUSED = 36 ;
+static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_UNUSED_LEN = 4 ;
+static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_DMA_RD_VG_RESET_TIMER_MASK = 40 ;
+static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_DMA_RD_VG_RESET_TIMER_MASK_LEN = 8 ;
+static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_DMA_WR_VG_RESET_TIMER_MASK = 48 ;
+static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_DMA_WR_VG_RESET_TIMER_MASK_LEN = 8 ;
+static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_ADDR_EXT_MASK = 56 ;
+static const uint8_t P9N2_PU_NXCQ_PB_MODE_REG_ADDR_EXT_MASK_LEN = 7 ;
+
+static const uint8_t P9N2_PU_NMMU_NX_CQ_FIR_ACTION0_REG_ACTION0 = 0 ;
+static const uint8_t P9N2_PU_NMMU_NX_CQ_FIR_ACTION0_REG_ACTION0_LEN = 22 ;
+
+static const uint8_t P9N2_PU_NX_CQ_FIR_ACTION0_REG_ACTION0 = 0 ;
+static const uint8_t P9N2_PU_NX_CQ_FIR_ACTION0_REG_ACTION0_LEN = 44 ;
+
+static const uint8_t P9N2_PU_NMMU_NX_CQ_FIR_ACTION1_REG_ACTION1 = 0 ;
+static const uint8_t P9N2_PU_NMMU_NX_CQ_FIR_ACTION1_REG_ACTION1_LEN = 21 ;
+
+static const uint8_t P9N2_PU_NX_CQ_FIR_ACTION1_REG_ACTION1 = 0 ;
+static const uint8_t P9N2_PU_NX_CQ_FIR_ACTION1_REG_ACTION1_LEN = 44 ;
+
+static const uint8_t P9N2_PU_NMMU_NX_CQ_FIR_MASK_REG_MASK = 0 ;
+static const uint8_t P9N2_PU_NMMU_NX_CQ_FIR_MASK_REG_MASK_LEN = 22 ;
+
+static const uint8_t P9N2_PU_NX_CQ_FIR_MASK_REG_MASK = 0 ;
+static const uint8_t P9N2_PU_NX_CQ_FIR_MASK_REG_MASK_LEN = 44 ;
+
+static const uint8_t P9N2_PU_NMMU_NX_CQ_FIR_REG_PBI_PE = 0 ;
+static const uint8_t P9N2_PU_NMMU_NX_CQ_FIR_REG_PBUS_CMD_HANG = 1 ;
+static const uint8_t P9N2_PU_NMMU_NX_CQ_FIR_REG_PBUS_READ_ARE = 2 ;
+static const uint8_t P9N2_PU_NMMU_NX_CQ_FIR_REG_PBUS_WRITE_ARE = 3 ;
+static const uint8_t P9N2_PU_NMMU_NX_CQ_FIR_REG_PBUS_MISC_HW = 4 ;
+static const uint8_t P9N2_PU_NMMU_NX_CQ_FIR_REG_RSVD = 5 ;
+static const uint8_t P9N2_PU_NMMU_NX_CQ_FIR_REG_PBUS_XLAT_ECC_UE = 6 ;
+static const uint8_t P9N2_PU_NMMU_NX_CQ_FIR_REG_PBUS_XLAT_ECC_SUE = 7 ;
+static const uint8_t P9N2_PU_NMMU_NX_CQ_FIR_REG_PBUS_ECC_CE = 8 ;
+static const uint8_t P9N2_PU_NMMU_NX_CQ_FIR_REG_PBUS_ECC_UE = 9 ;
+static const uint8_t P9N2_PU_NMMU_NX_CQ_FIR_REG_PBUS_ECC_SUE = 10 ;
+static const uint8_t P9N2_PU_NMMU_NX_CQ_FIR_REG_INBD_LCO_ARRAY_ECC_CE = 11 ;
+static const uint8_t P9N2_PU_NMMU_NX_CQ_FIR_REG_INBD_LCO_ARRAY_ECC_UE = 12 ;
+static const uint8_t P9N2_PU_NMMU_NX_CQ_FIR_REG_INBD_LCO_ARRAY_ECC_SUE = 13 ;
+static const uint8_t P9N2_PU_NMMU_NX_CQ_FIR_REG_INBD_ARRAY_ECC_CE = 14 ;
+static const uint8_t P9N2_PU_NMMU_NX_CQ_FIR_REG_INBD_ARRAY_ECC_UE = 15 ;
+static const uint8_t P9N2_PU_NMMU_NX_CQ_FIR_REG_INT_STATE_ERR = 16 ;
+static const uint8_t P9N2_PU_NMMU_NX_CQ_FIR_REG_PBUS_LOAD_LINK_ERR = 17 ;
+static const uint8_t P9N2_PU_NMMU_NX_CQ_FIR_REG_PBUS_STORE_LINK_ERR = 18 ;
+static const uint8_t P9N2_PU_NMMU_NX_CQ_FIR_REG_PBUS_LINK_ABORT = 19 ;
+static const uint8_t P9N2_PU_NMMU_NX_CQ_FIR_REG_SCOM_PE = 20 ;
+static const uint8_t P9N2_PU_NMMU_NX_CQ_FIR_REG_SCOM_PE_DUP = 21 ;
+
+static const uint8_t P9N2_PU_NX_CQ_FIR_REG_PBI_PE = 0 ;
+static const uint8_t P9N2_PU_NX_CQ_FIR_REG_PBUS_ECC_CE = 1 ;
+static const uint8_t P9N2_PU_NX_CQ_FIR_REG_PBUS_ECC_UE = 2 ;
+static const uint8_t P9N2_PU_NX_CQ_FIR_REG_PBUS_ECC_SUE = 3 ;
+static const uint8_t P9N2_PU_NX_CQ_FIR_REG_INBD_ARRAY_ECC_CE = 4 ;
+static const uint8_t P9N2_PU_NX_CQ_FIR_REG_INBD_ARRAY_ECC_UE = 5 ;
+static const uint8_t P9N2_PU_NX_CQ_FIR_REG_PASTE_REJECT = 6 ;
+static const uint8_t P9N2_PU_NX_CQ_FIR_REG_PBUS_CMD_HANG = 7 ;
+static const uint8_t P9N2_PU_NX_CQ_FIR_REG_PBUS_READ_ARE = 8 ;
+static const uint8_t P9N2_PU_NX_CQ_FIR_REG_PBUS_WRITE_ARE = 9 ;
+static const uint8_t P9N2_PU_NX_CQ_FIR_REG_PBUS_MISC_HW = 10 ;
+static const uint8_t P9N2_PU_NX_CQ_FIR_REG_MMIO_BAR_PE = 11 ;
+static const uint8_t P9N2_PU_NX_CQ_FIR_REG_UMAC_WC_INT_ADDR_UE = 12 ;
+static const uint8_t P9N2_PU_NX_CQ_FIR_REG_PBUS_LOAD_LINK_ERR = 13 ;
+static const uint8_t P9N2_PU_NX_CQ_FIR_REG_PBUS_STORE_LINK_ERR = 14 ;
+static const uint8_t P9N2_PU_NX_CQ_FIR_REG_PBUS_LINK_ABORT = 15 ;
+static const uint8_t P9N2_PU_NX_CQ_FIR_REG_PBI_INTERNAL_HANG = 16 ;
+static const uint8_t P9N2_PU_NX_CQ_FIR_REG_ERAT_ARRAY_PE = 17 ;
+static const uint8_t P9N2_PU_NX_CQ_FIR_REG_ERAT_ARRAY_CE = 18 ;
+static const uint8_t P9N2_PU_NX_CQ_FIR_REG_ERAT_ARRAY_UE = 19 ;
+static const uint8_t P9N2_PU_NX_CQ_FIR_REG_ERAT_ARRAY_SUE = 20 ;
+static const uint8_t P9N2_PU_NX_CQ_FIR_REG_ERAT_CICO_HANG = 21 ;
+static const uint8_t P9N2_PU_NX_CQ_FIR_REG_ERAT_CNTRL_ERR = 22 ;
+static const uint8_t P9N2_PU_NX_CQ_FIR_REG_PB_XLAT_DATA_UE = 23 ;
+static const uint8_t P9N2_PU_NX_CQ_FIR_REG_PB_XLAT_DATA_SUE = 24 ;
+static const uint8_t P9N2_PU_NX_CQ_FIR_REG_UMAC_LD_LINK_ERR = 25 ;
+static const uint8_t P9N2_PU_NX_CQ_FIR_REG_UMAC_LINK_ABORT = 26 ;
+static const uint8_t P9N2_PU_NX_CQ_FIR_REG_UMAC_CRB_UE = 27 ;
+static const uint8_t P9N2_PU_NX_CQ_FIR_REG_UMAC_CRB_SUE = 28 ;
+static const uint8_t P9N2_PU_NX_CQ_FIR_REG_ERAT_LOCAL_CSTOP = 29 ;
+static const uint8_t P9N2_PU_NX_CQ_FIR_REG_OTHER_SCOM_PE = 30 ;
+static const uint8_t P9N2_PU_NX_CQ_FIR_REG_RNG_SCOM_WRITE = 31 ;
+static const uint8_t P9N2_PU_NX_CQ_FIR_REG_RNG_FIRST_FAIL = 32 ;
+static const uint8_t P9N2_PU_NX_CQ_FIR_REG_RNG_SECOND_FAIL = 33 ;
+static const uint8_t P9N2_PU_NX_CQ_FIR_REG_RNG_CNTRL_LOGIC_ERR = 34 ;
+static const uint8_t P9N2_PU_NX_CQ_FIR_REG_NMMU_LOCAL_XSTOP = 35 ;
+static const uint8_t P9N2_PU_NX_CQ_FIR_REG_VAS_LOCAL_XSTOP = 36 ;
+static const uint8_t P9N2_PU_NX_CQ_FIR_REG_PBCQ_CNTRL_LOGIC_ERR = 37 ;
+static const uint8_t P9N2_PU_NX_CQ_FIR_REG_FAILED_LINK_ON_INTERRUPT = 38 ;
+static const uint8_t P9N2_PU_NX_CQ_FIR_REG_UMAC_WC_INT_ADDR_SUE = 39 ;
+static const uint8_t P9N2_PU_NX_CQ_FIR_REG_SPARE_40 = 40 ;
+static const uint8_t P9N2_PU_NX_CQ_FIR_REG_SPARE_41 = 41 ;
+static const uint8_t P9N2_PU_NX_CQ_FIR_REG_SCOM_PE = 42 ;
+static const uint8_t P9N2_PU_NX_CQ_FIR_REG_SCOM_PE_DUP = 43 ;
+
+static const uint8_t P9N2_PU_NX_DEBUGMUX_CTRL_BITS = 47 ;
+static const uint8_t P9N2_PU_NX_DEBUGMUX_CTRL_BITS_LEN = 14 ;
+
+static const uint8_t P9N2_PU_NMMU_NX_DEBUG_SNAPSHOT_0_B0_63 = 0 ;
+static const uint8_t P9N2_PU_NMMU_NX_DEBUG_SNAPSHOT_0_B0_63_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NX_DEBUG_SNAPSHOT_0_B0_63 = 0 ;
+static const uint8_t P9N2_PU_NX_DEBUG_SNAPSHOT_0_B0_63_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NMMU_NX_DEBUG_SNAPSHOT_1_B64_87 = 0 ;
+static const uint8_t P9N2_PU_NMMU_NX_DEBUG_SNAPSHOT_1_B64_87_LEN = 24 ;
+
+static const uint8_t P9N2_PU_NX_DEBUG_SNAPSHOT_1_B64_87 = 0 ;
+static const uint8_t P9N2_PU_NX_DEBUG_SNAPSHOT_1_B64_87_LEN = 24 ;
+
+static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_HANG_TIMER = 0 ;
+static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_SHM_INVALID_STATE = 1 ;
+static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_RESERVED_02 = 2 ;
+static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_RESERVED_03 = 3 ;
+static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_CH0_842_ECC_CE = 4 ;
+static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_CH0_842_ECC_UE = 5 ;
+static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_CH1_842_ECC_CE = 6 ;
+static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_CH1_842_ECC_UE = 7 ;
+static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_NONZERO_CSB_CC = 8 ;
+static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_ECC_CE = 9 ;
+static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_OUTWR_INRD_ECC_CE = 10 ;
+static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_CH4_GZIP_ECC_CE = 11 ;
+static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_CH4_GZIP_ECC_UE = 12 ;
+static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_CH4_GZIP_PE = 13 ;
+static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_OTHER_SCOM_SAT = 14 ;
+static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_INVALID_STATE_UNRECOV = 15 ;
+static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_INVALID_STATE_RECOV = 16 ;
+static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_ECC_UE = 17 ;
+static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_OUTWR_INRD_ECC_UE = 18 ;
+static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_INRD_DONE_ERR = 19 ;
+static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_CH0_842_INVALID_STATE = 20 ;
+static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_CH1_842_INVALID_STATE = 21 ;
+static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_CH2_SYM_INVALID_STATE = 22 ;
+static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_CH3_SYM_INVALID_STATE = 23 ;
+static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_CH4_GZIP_INVALID_STATE = 24 ;
+static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_RESERVED_25 = 25 ;
+static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_RESERVED_26 = 26 ;
+static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_RESERVED_27 = 27 ;
+static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_RESERVED_28 = 28 ;
+static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_RESERVED_29 = 29 ;
+static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_RESERVED_30 = 30 ;
+static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_CRB_ECC_UE = 31 ;
+static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_CRB_ECC_SUE = 32 ;
+static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_OUTWR_INRD_ECC_SUE = 33 ;
+static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_CH0_842_WATCHDOG = 34 ;
+static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_CH1_842_WATCHDOG = 35 ;
+static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_CH2_SYM_WATCHDOG = 36 ;
+static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_CH3_SYM_WATCHDOG = 37 ;
+static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_RESERVED_38 = 38 ;
+static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_CH4_GZIP_WATCHDOG = 39 ;
+static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_RESERVED_40 = 40 ;
+static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_RESERVED_41 = 41 ;
+static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_RESERVED_42 = 42 ;
+static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_RESERVED_43 = 43 ;
+static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_RESERVED_44 = 44 ;
+static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_RESERVED_45 = 45 ;
+static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_RESERVED_46 = 46 ;
+static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_RESERVED_47 = 47 ;
+static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_SCOM_PE = 48 ;
+static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_SCOM_PE_DUP = 49 ;
+
+static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_ACTION0_BITS = 0 ;
+static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_ACTION0_BITS_LEN = 50 ;
+
+static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_ACTION1_BITS = 0 ;
+static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_ACTION1_BITS_LEN = 50 ;
+
+static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_MASK_BITS = 0 ;
+static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_MASK_BITS_LEN = 50 ;
+
+static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_WOF_BITS = 0 ;
+static const uint8_t P9N2_PU_NX_DMA_ENG_FIR_WOF_BITS_LEN = 50 ;
+
+static const uint8_t P9N2_PU_NX_ERRORINJ_CTRL_CH0EFT_ENA = 2 ;
+static const uint8_t P9N2_PU_NX_ERRORINJ_CTRL_CH0EFT_TYPE = 3 ;
+static const uint8_t P9N2_PU_NX_ERRORINJ_CTRL_CH0EFT_ACTION = 4 ;
+static const uint8_t P9N2_PU_NX_ERRORINJ_CTRL_CH0EFT_SELECT = 5 ;
+static const uint8_t P9N2_PU_NX_ERRORINJ_CTRL_CH0EFT_SELECT_LEN = 4 ;
+static const uint8_t P9N2_PU_NX_ERRORINJ_CTRL_CH1EFT_ENA = 9 ;
+static const uint8_t P9N2_PU_NX_ERRORINJ_CTRL_CH1EFT_TYPE = 10 ;
+static const uint8_t P9N2_PU_NX_ERRORINJ_CTRL_CH1EFT_ACTION = 11 ;
+static const uint8_t P9N2_PU_NX_ERRORINJ_CTRL_CH1EFT_SELECT = 12 ;
+static const uint8_t P9N2_PU_NX_ERRORINJ_CTRL_CH1EFT_SELECT_LEN = 4 ;
+static const uint8_t P9N2_PU_NX_ERRORINJ_CTRL_DMA_INWR_ENA = 23 ;
+static const uint8_t P9N2_PU_NX_ERRORINJ_CTRL_DMA_INWR_TYPE = 24 ;
+static const uint8_t P9N2_PU_NX_ERRORINJ_CTRL_DMA_INWR_ACTION = 25 ;
+static const uint8_t P9N2_PU_NX_ERRORINJ_CTRL_DMA_OUTWR_ENA = 26 ;
+static const uint8_t P9N2_PU_NX_ERRORINJ_CTRL_DMA_OUTWR_TYPE = 27 ;
+static const uint8_t P9N2_PU_NX_ERRORINJ_CTRL_DMA_OUTWR_ACTION = 28 ;
+static const uint8_t P9N2_PU_NX_ERRORINJ_CTRL_DMA_INGARRAY_ENA = 29 ;
+static const uint8_t P9N2_PU_NX_ERRORINJ_CTRL_DMA_INGARRAY_TYPE = 30 ;
+static const uint8_t P9N2_PU_NX_ERRORINJ_CTRL_DMA_INGARRAY_ACTION = 31 ;
+static const uint8_t P9N2_PU_NX_ERRORINJ_CTRL_DMA_INGARRAY_SELECT = 32 ;
+static const uint8_t P9N2_PU_NX_ERRORINJ_CTRL_DMA_INGARRAY_SELECT_LEN = 4 ;
+static const uint8_t P9N2_PU_NX_ERRORINJ_CTRL_DMA_EGRARRAY_ENA = 36 ;
+static const uint8_t P9N2_PU_NX_ERRORINJ_CTRL_DMA_EGRARRAY_TYPE = 37 ;
+static const uint8_t P9N2_PU_NX_ERRORINJ_CTRL_DMA_EGRARRAY_ACTION = 38 ;
+static const uint8_t P9N2_PU_NX_ERRORINJ_CTRL_DMA_EGRARRAY_SELECT = 39 ;
+static const uint8_t P9N2_PU_NX_ERRORINJ_CTRL_DMA_EGRARRAY_SELECT_LEN = 4 ;
+static const uint8_t P9N2_PU_NX_ERRORINJ_CTRL_DMA_CRBARRAY_ENA = 43 ;
+static const uint8_t P9N2_PU_NX_ERRORINJ_CTRL_DMA_CRBARRAY_TYPE = 44 ;
+static const uint8_t P9N2_PU_NX_ERRORINJ_CTRL_DMA_CRBARRAY_ACTION = 45 ;
+static const uint8_t P9N2_PU_NX_ERRORINJ_CTRL_DMA_CRBARRAY_SELECT = 46 ;
+static const uint8_t P9N2_PU_NX_ERRORINJ_CTRL_CH4GZIP_ENA = 48 ;
+static const uint8_t P9N2_PU_NX_ERRORINJ_CTRL_CH4GZIP_TYPE = 49 ;
+static const uint8_t P9N2_PU_NX_ERRORINJ_CTRL_CH4GZIP_ACTION = 50 ;
+static const uint8_t P9N2_PU_NX_ERRORINJ_CTRL_CH4GZIP_SELECT = 51 ;
+static const uint8_t P9N2_PU_NX_ERRORINJ_CTRL_CH4GZIP_SELECT_LEN = 8 ;
+static const uint8_t P9N2_PU_NX_ERRORINJ_CTRL_DMA_OUTWR_QW0_UEINJ_ENA = 59 ;
+static const uint8_t P9N2_PU_NX_ERRORINJ_CTRL_DMA_OUTWR_QW4_UEINJ_ENA = 60 ;
+
+static const uint8_t P9N2_PU_NMMU_NX_MISC_CONTROL_REG_HANG_POLL_SCALE = 4 ;
+static const uint8_t P9N2_PU_NMMU_NX_MISC_CONTROL_REG_HANG_POLL_SCALE_LEN = 4 ;
+static const uint8_t P9N2_PU_NMMU_NX_MISC_CONTROL_REG_HANG_DATA_SCALE = 8 ;
+static const uint8_t P9N2_PU_NMMU_NX_MISC_CONTROL_REG_HANG_DATA_SCALE_LEN = 4 ;
+static const uint8_t P9N2_PU_NMMU_NX_MISC_CONTROL_REG_HANG_SHM_SCALE = 12 ;
+static const uint8_t P9N2_PU_NMMU_NX_MISC_CONTROL_REG_HANG_SHM_SCALE_LEN = 4 ;
+
+static const uint8_t P9N2_PU_NX_MISC_CONTROL_REG_HANG_POLL_SCALE = 4 ;
+static const uint8_t P9N2_PU_NX_MISC_CONTROL_REG_HANG_POLL_SCALE_LEN = 4 ;
+static const uint8_t P9N2_PU_NX_MISC_CONTROL_REG_HANG_DATA_SCALE = 8 ;
+static const uint8_t P9N2_PU_NX_MISC_CONTROL_REG_HANG_DATA_SCALE_LEN = 4 ;
+static const uint8_t P9N2_PU_NX_MISC_CONTROL_REG_HANG_SHM_SCALE = 12 ;
+static const uint8_t P9N2_PU_NX_MISC_CONTROL_REG_HANG_SHM_SCALE_LEN = 4 ;
+static const uint8_t P9N2_PU_NX_MISC_CONTROL_REG_ERAT_DATA_POLL_SCALE = 16 ;
+static const uint8_t P9N2_PU_NX_MISC_CONTROL_REG_ERAT_DATA_POLL_SCALE_LEN = 4 ;
+
+static const uint8_t P9N2_PU_NX_MMIO_BAR_BAR = 8 ;
+static const uint8_t P9N2_PU_NX_MMIO_BAR_BAR_LEN = 44 ;
+static const uint8_t P9N2_PU_NX_MMIO_BAR_ENABLE = 52 ;
+
+static const uint8_t P9N2_PU_NMMU_NX_PB_DEBUG_REG_NXCQ_TRACE_CNTL = 0 ;
+static const uint8_t P9N2_PU_NMMU_NX_PB_DEBUG_REG_NXCQ_TRACE_CNTL_LEN = 8 ;
+
+static const uint8_t P9N2_PU_NX_PB_DEBUG_REG_NXCQ_TRACE_CNTL = 0 ;
+static const uint8_t P9N2_PU_NX_PB_DEBUG_REG_NXCQ_TRACE_CNTL_LEN = 8 ;
+
+static const uint8_t P9N2_PU_NMMU_NX_PB_ECC_REG_NXCQ_INJECT_MODE = 0 ;
+static const uint8_t P9N2_PU_NMMU_NX_PB_ECC_REG_NXCQ_INJECT_MODE_LEN = 2 ;
+static const uint8_t P9N2_PU_NMMU_NX_PB_ECC_REG_NXCQ_INJECT_TYPE = 2 ;
+static const uint8_t P9N2_PU_NMMU_NX_PB_ECC_REG_NXCQ_INJECT_TYPE_LEN = 2 ;
+static const uint8_t P9N2_PU_NMMU_NX_PB_ECC_REG_NXCQ_PBCQ_INJECT_ENABLE = 4 ;
+static const uint8_t P9N2_PU_NMMU_NX_PB_ECC_REG_NXCQ_PBCQ_ARRAY = 5 ;
+static const uint8_t P9N2_PU_NMMU_NX_PB_ECC_REG_NXCQ_PBCQ_ARRAY_LEN = 4 ;
+
+static const uint8_t P9N2_PU_NX_PB_ECC_REG_NXCQ_INJECT_MODE = 0 ;
+static const uint8_t P9N2_PU_NX_PB_ECC_REG_NXCQ_INJECT_MODE_LEN = 2 ;
+static const uint8_t P9N2_PU_NX_PB_ECC_REG_NXCQ_INJECT_TYPE = 2 ;
+static const uint8_t P9N2_PU_NX_PB_ECC_REG_NXCQ_INJECT_TYPE_LEN = 2 ;
+static const uint8_t P9N2_PU_NX_PB_ECC_REG_NXCQ_PBCQ_INJECT_ENABLE = 4 ;
+static const uint8_t P9N2_PU_NX_PB_ECC_REG_NXCQ_PBCQ_ARRAY = 5 ;
+static const uint8_t P9N2_PU_NX_PB_ECC_REG_NXCQ_PBCQ_ARRAY_LEN = 4 ;
+static const uint8_t P9N2_PU_NX_PB_ECC_REG_NXCQ_RNG_INJECT_ENABLE = 16 ;
+static const uint8_t P9N2_PU_NX_PB_ECC_REG_NXCQ_RNG_INJECT_ACTION = 17 ;
+static const uint8_t P9N2_PU_NX_PB_ECC_REG_NXCQ_ERAT_ARRAY_ENABLE = 24 ;
+static const uint8_t P9N2_PU_NX_PB_ECC_REG_NXCQ_ERAT_ARRAY_TYPE = 25 ;
+static const uint8_t P9N2_PU_NX_PB_ECC_REG_NXCQ_ERAT_ARRAY_ACTION = 26 ;
+static const uint8_t P9N2_PU_NX_PB_ECC_REG_NXCQ_ERAT_ARRAY_SELECT = 27 ;
+static const uint8_t P9N2_PU_NX_PB_ECC_REG_NXCQ_ERAT_ARRAY_SELECT_LEN = 4 ;
+
+static const uint8_t P9N2_PU_NMMU_NX_PB_ERR_RPT_0_NX_PBI_ERR_RPT_OUT = 0 ;
+static const uint8_t P9N2_PU_NMMU_NX_PB_ERR_RPT_0_NX_PBI_ERR_RPT_OUT_LEN = 52 ;
+static const uint8_t P9N2_PU_NMMU_NX_PB_ERR_RPT_0_PBI_WRITE_IDLE = 52 ;
+
+static const uint8_t P9N2_PU_NX_PB_ERR_RPT_0_NX_PBI_ERR_RPT_OUT = 0 ;
+static const uint8_t P9N2_PU_NX_PB_ERR_RPT_0_NX_PBI_ERR_RPT_OUT_LEN = 63 ;
+static const uint8_t P9N2_PU_NX_PB_ERR_RPT_0_PBI_WRITE_IDLE = 63 ;
+
+static const uint8_t P9N2_PU_NX_PB_ERR_RPT_1_NX_PBI_ERR_RPT_OUT = 0 ;
+static const uint8_t P9N2_PU_NX_PB_ERR_RPT_1_NX_PBI_ERR_RPT_OUT_LEN = 11 ;
+
+static const uint8_t P9N2_PU_NX_PMU0_CONTROL_REG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NX_PMU0_CONTROL_REG_FREEZE = 1 ;
+static const uint8_t P9N2_PU_NX_PMU0_CONTROL_REG_RESET = 2 ;
+static const uint8_t P9N2_PU_NX_PMU0_CONTROL_REG_DIS_GLOB_SCOM = 3 ;
+static const uint8_t P9N2_PU_NX_PMU0_CONTROL_REG_PRESCALAR_SEL0 = 4 ;
+static const uint8_t P9N2_PU_NX_PMU0_CONTROL_REG_PRESCALAR_SEL0_LEN = 2 ;
+static const uint8_t P9N2_PU_NX_PMU0_CONTROL_REG_PRESCALAR_SEL1 = 6 ;
+static const uint8_t P9N2_PU_NX_PMU0_CONTROL_REG_PRESCALAR_SEL1_LEN = 2 ;
+static const uint8_t P9N2_PU_NX_PMU0_CONTROL_REG_PRESCALAR_SEL2 = 8 ;
+static const uint8_t P9N2_PU_NX_PMU0_CONTROL_REG_PRESCALAR_SEL2_LEN = 2 ;
+static const uint8_t P9N2_PU_NX_PMU0_CONTROL_REG_PRESCALAR_SEL3 = 10 ;
+static const uint8_t P9N2_PU_NX_PMU0_CONTROL_REG_PRESCALAR_SEL3_LEN = 2 ;
+static const uint8_t P9N2_PU_NX_PMU0_CONTROL_REG_CNT0_PAIR_OP = 12 ;
+static const uint8_t P9N2_PU_NX_PMU0_CONTROL_REG_CNT0_PAIR_OP_LEN = 2 ;
+static const uint8_t P9N2_PU_NX_PMU0_CONTROL_REG_CNT1_PAIR_OP = 14 ;
+static const uint8_t P9N2_PU_NX_PMU0_CONTROL_REG_CNT1_PAIR_OP_LEN = 2 ;
+static const uint8_t P9N2_PU_NX_PMU0_CONTROL_REG_CNT2_PAIR_OP = 16 ;
+static const uint8_t P9N2_PU_NX_PMU0_CONTROL_REG_CNT2_PAIR_OP_LEN = 2 ;
+static const uint8_t P9N2_PU_NX_PMU0_CONTROL_REG_CNT3_PAIR_OP = 18 ;
+static const uint8_t P9N2_PU_NX_PMU0_CONTROL_REG_CNT3_PAIR_OP_LEN = 2 ;
+static const uint8_t P9N2_PU_NX_PMU0_CONTROL_REG_CNT0_MUX_SEL = 20 ;
+static const uint8_t P9N2_PU_NX_PMU0_CONTROL_REG_CNT0_MUX_SEL_LEN = 3 ;
+static const uint8_t P9N2_PU_NX_PMU0_CONTROL_REG_CNT1_MUX_SEL = 23 ;
+static const uint8_t P9N2_PU_NX_PMU0_CONTROL_REG_CNT1_MUX_SEL_LEN = 3 ;
+static const uint8_t P9N2_PU_NX_PMU0_CONTROL_REG_CNT2_MUX_SEL = 26 ;
+static const uint8_t P9N2_PU_NX_PMU0_CONTROL_REG_CNT2_MUX_SEL_LEN = 3 ;
+static const uint8_t P9N2_PU_NX_PMU0_CONTROL_REG_CNT3_MUX_SEL = 29 ;
+static const uint8_t P9N2_PU_NX_PMU0_CONTROL_REG_CNT3_MUX_SEL_LEN = 3 ;
+static const uint8_t P9N2_PU_NX_PMU0_CONTROL_REG_FREEZE_ON_OVERFLOW = 32 ;
+static const uint8_t P9N2_PU_NX_PMU0_CONTROL_REG_CASCADE = 33 ;
+static const uint8_t P9N2_PU_NX_PMU0_CONTROL_REG_CASCADE_LEN = 3 ;
+
+static const uint8_t P9N2_PU_NX_PMU0_COUNTER_REG_0 = 0 ;
+static const uint8_t P9N2_PU_NX_PMU0_COUNTER_REG_0_LEN = 16 ;
+static const uint8_t P9N2_PU_NX_PMU0_COUNTER_REG_1 = 16 ;
+static const uint8_t P9N2_PU_NX_PMU0_COUNTER_REG_1_LEN = 16 ;
+static const uint8_t P9N2_PU_NX_PMU0_COUNTER_REG_2 = 32 ;
+static const uint8_t P9N2_PU_NX_PMU0_COUNTER_REG_2_LEN = 16 ;
+static const uint8_t P9N2_PU_NX_PMU0_COUNTER_REG_3 = 48 ;
+static const uint8_t P9N2_PU_NX_PMU0_COUNTER_REG_3_LEN = 16 ;
+
+static const uint8_t P9N2_PU_NX_PMU1_CONTROL_REG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NX_PMU1_CONTROL_REG_FREEZE = 1 ;
+static const uint8_t P9N2_PU_NX_PMU1_CONTROL_REG_RESET = 2 ;
+static const uint8_t P9N2_PU_NX_PMU1_CONTROL_REG_DIS_GLOB_SCOM = 3 ;
+static const uint8_t P9N2_PU_NX_PMU1_CONTROL_REG_PRESCALAR_SEL0 = 4 ;
+static const uint8_t P9N2_PU_NX_PMU1_CONTROL_REG_PRESCALAR_SEL0_LEN = 2 ;
+static const uint8_t P9N2_PU_NX_PMU1_CONTROL_REG_PRESCALAR_SEL1 = 6 ;
+static const uint8_t P9N2_PU_NX_PMU1_CONTROL_REG_PRESCALAR_SEL1_LEN = 2 ;
+static const uint8_t P9N2_PU_NX_PMU1_CONTROL_REG_PRESCALAR_SEL2 = 8 ;
+static const uint8_t P9N2_PU_NX_PMU1_CONTROL_REG_PRESCALAR_SEL2_LEN = 2 ;
+static const uint8_t P9N2_PU_NX_PMU1_CONTROL_REG_PRESCALAR_SEL3 = 10 ;
+static const uint8_t P9N2_PU_NX_PMU1_CONTROL_REG_PRESCALAR_SEL3_LEN = 2 ;
+static const uint8_t P9N2_PU_NX_PMU1_CONTROL_REG_CNT0_PAIR_OP = 12 ;
+static const uint8_t P9N2_PU_NX_PMU1_CONTROL_REG_CNT0_PAIR_OP_LEN = 2 ;
+static const uint8_t P9N2_PU_NX_PMU1_CONTROL_REG_CNT1_PAIR_OP = 14 ;
+static const uint8_t P9N2_PU_NX_PMU1_CONTROL_REG_CNT1_PAIR_OP_LEN = 2 ;
+static const uint8_t P9N2_PU_NX_PMU1_CONTROL_REG_CNT2_PAIR_OP = 16 ;
+static const uint8_t P9N2_PU_NX_PMU1_CONTROL_REG_CNT2_PAIR_OP_LEN = 2 ;
+static const uint8_t P9N2_PU_NX_PMU1_CONTROL_REG_CNT3_PAIR_OP = 18 ;
+static const uint8_t P9N2_PU_NX_PMU1_CONTROL_REG_CNT3_PAIR_OP_LEN = 2 ;
+static const uint8_t P9N2_PU_NX_PMU1_CONTROL_REG_CNT0_MUX_SEL = 20 ;
+static const uint8_t P9N2_PU_NX_PMU1_CONTROL_REG_CNT0_MUX_SEL_LEN = 3 ;
+static const uint8_t P9N2_PU_NX_PMU1_CONTROL_REG_CNT1_MUX_SEL = 23 ;
+static const uint8_t P9N2_PU_NX_PMU1_CONTROL_REG_CNT1_MUX_SEL_LEN = 3 ;
+static const uint8_t P9N2_PU_NX_PMU1_CONTROL_REG_CNT2_MUX_SEL = 26 ;
+static const uint8_t P9N2_PU_NX_PMU1_CONTROL_REG_CNT2_MUX_SEL_LEN = 3 ;
+static const uint8_t P9N2_PU_NX_PMU1_CONTROL_REG_CNT3_MUX_SEL = 29 ;
+static const uint8_t P9N2_PU_NX_PMU1_CONTROL_REG_CNT3_MUX_SEL_LEN = 3 ;
+static const uint8_t P9N2_PU_NX_PMU1_CONTROL_REG_FREEZE_ON_OVERFLOW = 32 ;
+static const uint8_t P9N2_PU_NX_PMU1_CONTROL_REG_CASCADE = 33 ;
+static const uint8_t P9N2_PU_NX_PMU1_CONTROL_REG_CASCADE_LEN = 3 ;
+
+static const uint8_t P9N2_PU_NX_PMU1_COUNTER_REG_0 = 0 ;
+static const uint8_t P9N2_PU_NX_PMU1_COUNTER_REG_0_LEN = 16 ;
+static const uint8_t P9N2_PU_NX_PMU1_COUNTER_REG_1 = 16 ;
+static const uint8_t P9N2_PU_NX_PMU1_COUNTER_REG_1_LEN = 16 ;
+static const uint8_t P9N2_PU_NX_PMU1_COUNTER_REG_2 = 32 ;
+static const uint8_t P9N2_PU_NX_PMU1_COUNTER_REG_2_LEN = 16 ;
+static const uint8_t P9N2_PU_NX_PMU1_COUNTER_REG_3 = 48 ;
+static const uint8_t P9N2_PU_NX_PMU1_COUNTER_REG_3_LEN = 16 ;
+
+static const uint8_t P9N2_PU_NMMU_NX_PMU_CONTROL_REG_CNT0_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NMMU_NX_PMU_CONTROL_REG_CNT1_ENABLE = 1 ;
+static const uint8_t P9N2_PU_NMMU_NX_PMU_CONTROL_REG_CNT2_ENABLE = 2 ;
+static const uint8_t P9N2_PU_NMMU_NX_PMU_CONTROL_REG_CNT3_ENABLE = 3 ;
+static const uint8_t P9N2_PU_NMMU_NX_PMU_CONTROL_REG_PRESCALER_SEL = 4 ;
+static const uint8_t P9N2_PU_NMMU_NX_PMU_CONTROL_REG_PRESCALER_SEL_LEN = 3 ;
+static const uint8_t P9N2_PU_NMMU_NX_PMU_CONTROL_REG_CNT0_POSEDGE_SEL = 7 ;
+static const uint8_t P9N2_PU_NMMU_NX_PMU_CONTROL_REG_CNT1_POSEDGE_SEL = 8 ;
+static const uint8_t P9N2_PU_NMMU_NX_PMU_CONTROL_REG_CNT2_POSEDGE_SEL = 9 ;
+static const uint8_t P9N2_PU_NMMU_NX_PMU_CONTROL_REG_CNT3_POSEDGE_SEL = 10 ;
+static const uint8_t P9N2_PU_NMMU_NX_PMU_CONTROL_REG_RESET = 11 ;
+static const uint8_t P9N2_PU_NMMU_NX_PMU_CONTROL_REG_CNT0_EVENT_SEL = 12 ;
+static const uint8_t P9N2_PU_NMMU_NX_PMU_CONTROL_REG_CNT0_EVENT_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_NMMU_NX_PMU_CONTROL_REG_CNT0_BIT_PAIR_SEL = 14 ;
+static const uint8_t P9N2_PU_NMMU_NX_PMU_CONTROL_REG_CNT0_BIT_PAIR_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_NMMU_NX_PMU_CONTROL_REG_CNT1_EVENT_SEL = 16 ;
+static const uint8_t P9N2_PU_NMMU_NX_PMU_CONTROL_REG_CNT1_EVENT_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_NMMU_NX_PMU_CONTROL_REG_CNT1_BIT_PAIR_SEL = 18 ;
+static const uint8_t P9N2_PU_NMMU_NX_PMU_CONTROL_REG_CNT1_BIT_PAIR_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_NMMU_NX_PMU_CONTROL_REG_CNT2_EVENT_SEL = 20 ;
+static const uint8_t P9N2_PU_NMMU_NX_PMU_CONTROL_REG_CNT2_EVENT_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_NMMU_NX_PMU_CONTROL_REG_CNT2_BIT_PAIR_SEL = 22 ;
+static const uint8_t P9N2_PU_NMMU_NX_PMU_CONTROL_REG_CNT2_BIT_PAIR_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_NMMU_NX_PMU_CONTROL_REG_CNT3_EVENT_SEL = 24 ;
+static const uint8_t P9N2_PU_NMMU_NX_PMU_CONTROL_REG_CNT3_EVENT_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_NMMU_NX_PMU_CONTROL_REG_CNT3_BIT_PAIR_SEL = 26 ;
+static const uint8_t P9N2_PU_NMMU_NX_PMU_CONTROL_REG_CNT3_BIT_PAIR_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_NMMU_NX_PMU_CONTROL_REG_PORT_SEL = 28 ;
+static const uint8_t P9N2_PU_NMMU_NX_PMU_CONTROL_REG_PORT_SEL_LEN = 2 ;
+
+static const uint8_t P9N2_PU_NMMU_NX_PMU_COUNTER_REG_0 = 0 ;
+static const uint8_t P9N2_PU_NMMU_NX_PMU_COUNTER_REG_0_LEN = 16 ;
+static const uint8_t P9N2_PU_NMMU_NX_PMU_COUNTER_REG_1 = 16 ;
+static const uint8_t P9N2_PU_NMMU_NX_PMU_COUNTER_REG_1_LEN = 16 ;
+static const uint8_t P9N2_PU_NMMU_NX_PMU_COUNTER_REG_2 = 32 ;
+static const uint8_t P9N2_PU_NMMU_NX_PMU_COUNTER_REG_2_LEN = 16 ;
+static const uint8_t P9N2_PU_NMMU_NX_PMU_COUNTER_REG_3 = 48 ;
+static const uint8_t P9N2_PU_NMMU_NX_PMU_COUNTER_REG_3_LEN = 16 ;
+
+static const uint8_t P9N2_PU_NX_RNG_BYPASS_RRN_DATA = 0 ;
+static const uint8_t P9N2_PU_NX_RNG_BYPASS_RRN_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NX_RNG_CFG_FAIL_REG = 0 ;
+static const uint8_t P9N2_PU_NX_RNG_CFG_FAIL_REG_LEN = 10 ;
+static const uint8_t P9N2_PU_NX_RNG_CFG_RNG0_FAIL = 10 ;
+static const uint8_t P9N2_PU_NX_RNG_CFG_RNG1_FAIL = 11 ;
+static const uint8_t P9N2_PU_NX_RNG_CFG_INTERRUPT_SENT = 12 ;
+static const uint8_t P9N2_PU_NX_RNG_CFG_BIST_ENABLE = 16 ;
+static const uint8_t P9N2_PU_NX_RNG_CFG_BIST_COMPLETE = 17 ;
+static const uint8_t P9N2_PU_NX_RNG_CFG_RNG0_BIST_FAIL = 18 ;
+static const uint8_t P9N2_PU_NX_RNG_CFG_RNG1_BIST_FAIL = 19 ;
+static const uint8_t P9N2_PU_NX_RNG_CFG_BIST_BIT_FAIL_TH = 20 ;
+static const uint8_t P9N2_PU_NX_RNG_CFG_BIST_BIT_FAIL_TH_LEN = 3 ;
+static const uint8_t P9N2_PU_NX_RNG_CFG_RNG0_INJ_CONTINOUS_ERROR = 23 ;
+static const uint8_t P9N2_PU_NX_RNG_CFG_RNG1_INJ_CONTINOUS_ERROR = 24 ;
+static const uint8_t P9N2_PU_NX_RNG_CFG_ST2_RESET_PERIOD = 30 ;
+static const uint8_t P9N2_PU_NX_RNG_CFG_ST2_RESET_PERIOD_LEN = 8 ;
+static const uint8_t P9N2_PU_NX_RNG_CFG_RRN_BYPASS_ENABLE = 38 ;
+static const uint8_t P9N2_PU_NX_RNG_CFG_MASK_TOGGLE_ENABLE = 39 ;
+static const uint8_t P9N2_PU_NX_RNG_CFG_SAMPTEST_ENABLE = 40 ;
+static const uint8_t P9N2_PU_NX_RNG_CFG_REPTEST_ENABLE = 41 ;
+static const uint8_t P9N2_PU_NX_RNG_CFG_ADAPTEST_1BIT_ENABLE = 42 ;
+static const uint8_t P9N2_PU_NX_RNG_CFG_ADAPTEST_ENABLE = 43 ;
+static const uint8_t P9N2_PU_NX_RNG_CFG_COND_STARTUP_TEST_FAIL = 44 ;
+static const uint8_t P9N2_PU_NX_RNG_CFG_PACE_RATE = 46 ;
+static const uint8_t P9N2_PU_NX_RNG_CFG_PACE_RATE_LEN = 16 ;
+static const uint8_t P9N2_PU_NX_RNG_CFG_ENABLE = 63 ;
+
+static const uint8_t P9N2_PU_NX_RNG_RDELAY_CQ_FILL_THRESHOLD = 0 ;
+static const uint8_t P9N2_PU_NX_RNG_RDELAY_CQ_FILL_THRESHOLD_LEN = 2 ;
+static const uint8_t P9N2_PU_NX_RNG_RDELAY_CQ_DRAIN_THRESHOLD = 2 ;
+static const uint8_t P9N2_PU_NX_RNG_RDELAY_CQ_DRAIN_THRESHOLD_LEN = 2 ;
+static const uint8_t P9N2_PU_NX_RNG_RDELAY_CQ_LFSR_RESEED_EN = 6 ;
+static const uint8_t P9N2_PU_NX_RNG_RDELAY_CQ_READ_RTY_RATIO = 7 ;
+static const uint8_t P9N2_PU_NX_RNG_RDELAY_CQ_READ_RTY_RATIO_LEN = 5 ;
+
+static const uint8_t P9N2_PU_NX_RNG_RESET_RESET = 0 ;
+
+static const uint8_t P9N2_PU_NX_RNG_ST0_REPTEST_MATCH_TH = 0 ;
+static const uint8_t P9N2_PU_NX_RNG_ST0_REPTEST_MATCH_TH_LEN = 2 ;
+static const uint8_t P9N2_PU_NX_RNG_ST0_REPTEST_SOFT_FAIL_TH = 2 ;
+static const uint8_t P9N2_PU_NX_RNG_ST0_REPTEST_SOFT_FAIL_TH_LEN = 5 ;
+static const uint8_t P9N2_PU_NX_RNG_ST0_ADAPTEST_SAMPLE_SIZE = 7 ;
+static const uint8_t P9N2_PU_NX_RNG_ST0_ADAPTEST_SAMPLE_SIZE_LEN = 2 ;
+static const uint8_t P9N2_PU_NX_RNG_ST0_ADAPTEST_WINDOW_SIZE = 9 ;
+static const uint8_t P9N2_PU_NX_RNG_ST0_ADAPTEST_WINDOW_SIZE_LEN = 3 ;
+static const uint8_t P9N2_PU_NX_RNG_ST0_ADAPTEST_RRN_RNG0_MATCH_TH = 12 ;
+static const uint8_t P9N2_PU_NX_RNG_ST0_ADAPTEST_RRN_RNG0_MATCH_TH_LEN = 12 ;
+static const uint8_t P9N2_PU_NX_RNG_ST0_ADAPTEST_RRN_RNG1_MATCH_TH = 24 ;
+static const uint8_t P9N2_PU_NX_RNG_ST0_ADAPTEST_RRN_RNG1_MATCH_TH_LEN = 12 ;
+static const uint8_t P9N2_PU_NX_RNG_ST0_ADAPTEST_CRN_RNG0_MATCH_TH = 36 ;
+static const uint8_t P9N2_PU_NX_RNG_ST0_ADAPTEST_CRN_RNG0_MATCH_TH_LEN = 12 ;
+static const uint8_t P9N2_PU_NX_RNG_ST0_ADAPTEST_CRN_RNG1_MATCH_TH = 48 ;
+static const uint8_t P9N2_PU_NX_RNG_ST0_ADAPTEST_CRN_RNG1_MATCH_TH_LEN = 12 ;
+
+static const uint8_t P9N2_PU_NX_RNG_ST1_ADAPTEST_SOFT_FAIL_TH = 0 ;
+static const uint8_t P9N2_PU_NX_RNG_ST1_ADAPTEST_SOFT_FAIL_TH_LEN = 7 ;
+static const uint8_t P9N2_PU_NX_RNG_ST1_ADAPTEST_1BIT_MATCH_TH_MIN = 7 ;
+static const uint8_t P9N2_PU_NX_RNG_ST1_ADAPTEST_1BIT_MATCH_TH_MIN_LEN = 16 ;
+static const uint8_t P9N2_PU_NX_RNG_ST1_ADAPTEST_1BIT_MATCH_TH_MAX = 23 ;
+static const uint8_t P9N2_PU_NX_RNG_ST1_ADAPTEST_1BIT_MATCH_TH_MAX_LEN = 16 ;
+
+static const uint8_t P9N2_PU_NX_RNG_ST2_ADAPTEST_SOFT_FAIL_COUNT_RRN_RNG0 = 0 ;
+static const uint8_t P9N2_PU_NX_RNG_ST2_ADAPTEST_SOFT_FAIL_COUNT_RRN_RNG0_LEN = 8 ;
+static const uint8_t P9N2_PU_NX_RNG_ST2_ADAPTEST_SOFT_FAIL_COUNT_RRN_RNG1 = 8 ;
+static const uint8_t P9N2_PU_NX_RNG_ST2_ADAPTEST_SOFT_FAIL_COUNT_RRN_RNG1_LEN = 8 ;
+static const uint8_t P9N2_PU_NX_RNG_ST2_ADAPTEST_SOFT_FAIL_COUNT_CRN_RNG0 = 16 ;
+static const uint8_t P9N2_PU_NX_RNG_ST2_ADAPTEST_SOFT_FAIL_COUNT_CRN_RNG0_LEN = 8 ;
+static const uint8_t P9N2_PU_NX_RNG_ST2_ADAPTEST_SOFT_FAIL_COUNT_CRN_RNG1 = 24 ;
+static const uint8_t P9N2_PU_NX_RNG_ST2_ADAPTEST_SOFT_FAIL_COUNT_CRN_RNG1_LEN = 8 ;
+static const uint8_t P9N2_PU_NX_RNG_ST2_REPTEST_SOFT_FAIL_COUNT_RNG0 = 32 ;
+static const uint8_t P9N2_PU_NX_RNG_ST2_REPTEST_SOFT_FAIL_COUNT_RNG0_LEN = 6 ;
+static const uint8_t P9N2_PU_NX_RNG_ST2_REPTEST_SOFT_FAIL_COUNT_RNG1 = 38 ;
+static const uint8_t P9N2_PU_NX_RNG_ST2_REPTEST_SOFT_FAIL_COUNT_RNG1_LEN = 6 ;
+
+static const uint8_t P9N2_PU_NX_RNG_ST3_SAMPTEST_RRN_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NX_RNG_ST3_SAMPTEST_WINDOW_SIZE = 1 ;
+static const uint8_t P9N2_PU_NX_RNG_ST3_SAMPTEST_WINDOW_SIZE_LEN = 3 ;
+static const uint8_t P9N2_PU_NX_RNG_ST3_SAMPTEST_MATCH_TH_MIN = 4 ;
+static const uint8_t P9N2_PU_NX_RNG_ST3_SAMPTEST_MATCH_TH_MIN_LEN = 16 ;
+static const uint8_t P9N2_PU_NX_RNG_ST3_SAMPTEST_MATCH_TH_MAX = 20 ;
+static const uint8_t P9N2_PU_NX_RNG_ST3_SAMPTEST_MATCH_TH_MAX_LEN = 16 ;
+
+static const uint8_t P9N2_PU_NX_TRIGGER_CTRL_BITS = 50 ;
+static const uint8_t P9N2_PU_NX_TRIGGER_CTRL_BITS_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_CCSR_CORE_CONFIG = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_CCSR_CORE_CONFIG_LEN = 24 ;
+static const uint8_t P9N2_PU_OCB_OCI_CCSR_RESERVED_24 = 24 ;
+static const uint8_t P9N2_PU_OCB_OCI_CCSR_RESERVED_24_LEN = 7 ;
+static const uint8_t P9N2_PU_OCB_OCI_CCSR_CHANGE_IN_PROGRESS = 31 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_DERP_DIVIDEND = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_DERP_DIVIDEND_LEN = 32 ;
+static const uint8_t P9N2_PU_OCB_OCI_DERP_DIVISOR = 32 ;
+static const uint8_t P9N2_PU_OCB_OCI_DERP_DIVISOR_LEN = 32 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_DORP_QUOTIENT = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_DORP_QUOTIENT_LEN = 32 ;
+static const uint8_t P9N2_PU_OCB_OCI_DORP_REMAINDER = 32 ;
+static const uint8_t P9N2_PU_OCB_OCI_DORP_REMAINDER_LEN = 32 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_G0ISR0_INTERRUPT_GPE0_STATUS_N = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_G0ISR0_INTERRUPT_GPE0_STATUS_N_LEN = 32 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_G0ISR1_INTERRUPT_GPE0_STATUS_N = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_G0ISR1_INTERRUPT_GPE0_STATUS_N_LEN = 32 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_G1ISR0_INTERRUPT_GPE1_STATUS_N = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_G1ISR0_INTERRUPT_GPE1_STATUS_N_LEN = 32 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_G1ISR1_INTERRUPT_GPE1_STATUS_N = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_G1ISR1_INTERRUPT_GPE1_STATUS_N_LEN = 32 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_G2ISR0_INTERRUPT_GPE2_STATUS_N = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_G2ISR0_INTERRUPT_GPE2_STATUS_N_LEN = 32 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_G2ISR1_INTERRUPT_GPE2_STATUS_N = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_G2ISR1_INTERRUPT_GPE2_STATUS_N_LEN = 32 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_G3ISR0_INTERRUPT_GPE3_STATUS_N = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_G3ISR0_INTERRUPT_GPE3_STATUS_N_LEN = 32 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_G3ISR1_INTERRUPT_GPE3_STATUS_N = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_G3ISR1_INTERRUPT_GPE3_STATUS_N_LEN = 32 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_O2SCMD0A_O2SCMD_A_N_RESERVED_0 = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCMD0A_O2S_CLEAR_STICKY_BITS_A_N = 1 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_O2SCMD0B_O2SCMD_A_N_RESERVED_0 = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCMD0B_O2S_CLEAR_STICKY_BITS_A_N = 1 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_O2SCMD1A_O2SCMD_A_N_RESERVED_0 = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCMD1A_O2S_CLEAR_STICKY_BITS_A_N = 1 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_O2SCMD1B_O2SCMD_A_N_RESERVED_0 = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCMD1B_O2S_CLEAR_STICKY_BITS_A_N = 1 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL10A_O2S_BRIDGE_ENABLE_A_N = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL10A_O2SCTRL1_A_N_RESERVED_1 = 1 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL10A_O2S_CPOL_A_N = 2 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL10A_O2S_CPHA_A_N = 3 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL10A_O2S_CLOCK_DIVIDER_A_N = 4 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL10A_O2S_CLOCK_DIVIDER_A_N_LEN = 10 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL10A_O2SCTRL1_A_N_RESERVED_14_16 = 14 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL10A_O2SCTRL1_A_N_RESERVED_14_16_LEN = 3 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL10A_O2S_NR_OF_FRAMES_A_N = 17 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL10B_O2S_BRIDGE_ENABLE_A_N = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL10B_O2SCTRL1_A_N_RESERVED_1 = 1 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL10B_O2S_CPOL_A_N = 2 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL10B_O2S_CPHA_A_N = 3 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL10B_O2S_CLOCK_DIVIDER_A_N = 4 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL10B_O2S_CLOCK_DIVIDER_A_N_LEN = 10 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL10B_O2SCTRL1_A_N_RESERVED_14_16 = 14 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL10B_O2SCTRL1_A_N_RESERVED_14_16_LEN = 3 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL10B_O2S_NR_OF_FRAMES_A_N = 17 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL11A_O2S_BRIDGE_ENABLE_A_N = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL11A_O2SCTRL1_A_N_RESERVED_1 = 1 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL11A_O2S_CPOL_A_N = 2 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL11A_O2S_CPHA_A_N = 3 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL11A_O2S_CLOCK_DIVIDER_A_N = 4 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL11A_O2S_CLOCK_DIVIDER_A_N_LEN = 10 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL11A_O2SCTRL1_A_N_RESERVED_14_16 = 14 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL11A_O2SCTRL1_A_N_RESERVED_14_16_LEN = 3 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL11A_O2S_NR_OF_FRAMES_A_N = 17 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL11B_O2S_BRIDGE_ENABLE_A_N = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL11B_O2SCTRL1_A_N_RESERVED_1 = 1 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL11B_O2S_CPOL_A_N = 2 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL11B_O2S_CPHA_A_N = 3 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL11B_O2S_CLOCK_DIVIDER_A_N = 4 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL11B_O2S_CLOCK_DIVIDER_A_N_LEN = 10 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL11B_O2SCTRL1_A_N_RESERVED_14_16 = 14 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL11B_O2SCTRL1_A_N_RESERVED_14_16_LEN = 3 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL11B_O2S_NR_OF_FRAMES_A_N = 17 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL20A_O2S_INTER_FRAME_DELAY_A_N = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL20A_O2S_INTER_FRAME_DELAY_A_N_LEN = 17 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL20B_O2S_INTER_FRAME_DELAY_A_N = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL20B_O2S_INTER_FRAME_DELAY_A_N_LEN = 17 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL21A_O2S_INTER_FRAME_DELAY_A_N = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL21A_O2S_INTER_FRAME_DELAY_A_N_LEN = 17 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL21B_O2S_INTER_FRAME_DELAY_A_N = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRL21B_O2S_INTER_FRAME_DELAY_A_N_LEN = 17 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLF0A_O2S_FRAME_SIZE_A_N = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLF0A_O2S_FRAME_SIZE_A_N_LEN = 6 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLF0A_O2S_OUT_COUNT1_A_N = 6 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLF0A_O2S_OUT_COUNT1_A_N_LEN = 6 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLF0A_O2S_IN_DELAY1_A_N = 12 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLF0A_O2S_IN_DELAY1_A_N_LEN = 6 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLF0A_O2S_IN_COUNT1_A_N = 18 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLF0A_O2S_IN_COUNT1_A_N_LEN = 6 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLF0B_O2S_FRAME_SIZE_A_N = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLF0B_O2S_FRAME_SIZE_A_N_LEN = 6 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLF0B_O2S_OUT_COUNT1_A_N = 6 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLF0B_O2S_OUT_COUNT1_A_N_LEN = 6 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLF0B_O2S_IN_DELAY1_A_N = 12 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLF0B_O2S_IN_DELAY1_A_N_LEN = 6 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLF0B_O2S_IN_COUNT1_A_N = 18 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLF0B_O2S_IN_COUNT1_A_N_LEN = 6 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLF1A_O2S_FRAME_SIZE_A_N = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLF1A_O2S_FRAME_SIZE_A_N_LEN = 6 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLF1A_O2S_OUT_COUNT1_A_N = 6 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLF1A_O2S_OUT_COUNT1_A_N_LEN = 6 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLF1A_O2S_IN_DELAY1_A_N = 12 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLF1A_O2S_IN_DELAY1_A_N_LEN = 6 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLF1A_O2S_IN_COUNT1_A_N = 18 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLF1A_O2S_IN_COUNT1_A_N_LEN = 6 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLF1B_O2S_FRAME_SIZE_A_N = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLF1B_O2S_FRAME_SIZE_A_N_LEN = 6 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLF1B_O2S_OUT_COUNT1_A_N = 6 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLF1B_O2S_OUT_COUNT1_A_N_LEN = 6 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLF1B_O2S_IN_DELAY1_A_N = 12 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLF1B_O2S_IN_DELAY1_A_N_LEN = 6 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLF1B_O2S_IN_COUNT1_A_N = 18 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLF1B_O2S_IN_COUNT1_A_N_LEN = 6 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLS0A_O2S_OUT_COUNT2_A_N = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLS0A_O2S_OUT_COUNT2_A_N_LEN = 6 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLS0A_O2S_IN_DELAY2_A_N = 6 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLS0A_O2S_IN_DELAY2_A_N_LEN = 6 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLS0A_O2S_IN_COUNT2_A_N = 12 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLS0A_O2S_IN_COUNT2_A_N_LEN = 6 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLS0B_O2S_OUT_COUNT2_A_N = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLS0B_O2S_OUT_COUNT2_A_N_LEN = 6 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLS0B_O2S_IN_DELAY2_A_N = 6 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLS0B_O2S_IN_DELAY2_A_N_LEN = 6 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLS0B_O2S_IN_COUNT2_A_N = 12 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLS0B_O2S_IN_COUNT2_A_N_LEN = 6 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLS1A_O2S_OUT_COUNT2_A_N = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLS1A_O2S_OUT_COUNT2_A_N_LEN = 6 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLS1A_O2S_IN_DELAY2_A_N = 6 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLS1A_O2S_IN_DELAY2_A_N_LEN = 6 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLS1A_O2S_IN_COUNT2_A_N = 12 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLS1A_O2S_IN_COUNT2_A_N_LEN = 6 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLS1B_O2S_OUT_COUNT2_A_N = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLS1B_O2S_OUT_COUNT2_A_N_LEN = 6 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLS1B_O2S_IN_DELAY2_A_N = 6 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLS1B_O2S_IN_DELAY2_A_N_LEN = 6 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLS1B_O2S_IN_COUNT2_A_N = 12 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SCTRLS1B_O2S_IN_COUNT2_A_N_LEN = 6 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_O2SRD0A_O2S_RDATA_A_N = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SRD0A_O2S_RDATA_A_N_LEN = 32 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_O2SRD0B_O2S_RDATA_A_N = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SRD0B_O2S_RDATA_A_N_LEN = 32 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_O2SRD1A_O2S_RDATA_A_N = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SRD1A_O2S_RDATA_A_N_LEN = 32 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_O2SRD1B_O2S_RDATA_A_N = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SRD1B_O2S_RDATA_A_N_LEN = 32 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_O2SST0A_O2S_ONGOING_A_N = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SST0A_O2SST_A_N_RESERVED_1_4 = 1 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SST0A_O2SST_A_N_RESERVED_1_4_LEN = 4 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SST0A_O2S_WRITE_WHILE_BRIDGE_BUSY_ERR_A_N = 5 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SST0A_O2SST_A_N_RESERVED_6 = 6 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SST0A_O2S_FSM_ERR_A_N = 7 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_O2SST0B_O2S_ONGOING_A_N = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SST0B_O2SST_A_N_RESERVED_1_4 = 1 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SST0B_O2SST_A_N_RESERVED_1_4_LEN = 4 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SST0B_O2S_WRITE_WHILE_BRIDGE_BUSY_ERR_A_N = 5 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SST0B_O2SST_A_N_RESERVED_6 = 6 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SST0B_O2S_FSM_ERR_A_N = 7 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_O2SST1A_O2S_ONGOING_A_N = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SST1A_O2SST_A_N_RESERVED_1_4 = 1 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SST1A_O2SST_A_N_RESERVED_1_4_LEN = 4 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SST1A_O2S_WRITE_WHILE_BRIDGE_BUSY_ERR_A_N = 5 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SST1A_O2SST_A_N_RESERVED_6 = 6 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SST1A_O2S_FSM_ERR_A_N = 7 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_O2SST1B_O2S_ONGOING_A_N = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SST1B_O2SST_A_N_RESERVED_1_4 = 1 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SST1B_O2SST_A_N_RESERVED_1_4_LEN = 4 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SST1B_O2S_WRITE_WHILE_BRIDGE_BUSY_ERR_A_N = 5 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SST1B_O2SST_A_N_RESERVED_6 = 6 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SST1B_O2S_FSM_ERR_A_N = 7 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_O2SWD0A_O2S_WDATA_A_N = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SWD0A_O2S_WDATA_A_N_LEN = 32 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_O2SWD0B_O2S_WDATA_A_N = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SWD0B_O2S_WDATA_A_N_LEN = 32 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_O2SWD1A_O2S_WDATA_A_N = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SWD1A_O2S_WDATA_A_N_LEN = 32 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_O2SWD1B_O2S_WDATA_A_N = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_O2SWD1B_O2S_WDATA_A_N_LEN = 32 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OCBLWCR0_LINEAR_WINDOW_ENABLE = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBLWCR0_SPARE_0 = 1 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBLWCR0_SPARE_0_LEN = 2 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBLWCR0_LINEAR_WINDOW_BAR = 3 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBLWCR0_LINEAR_WINDOW_BAR_LEN = 17 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBLWCR0_LINEAR_WINDOW_MASK = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBLWCR0_LINEAR_WINDOW_MASK_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OCBLWCR1_LINEAR_WINDOW_ENABLE = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBLWCR1_SPARE_0 = 1 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBLWCR1_SPARE_0_LEN = 2 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBLWCR1_LINEAR_WINDOW_BAR = 3 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBLWCR1_LINEAR_WINDOW_BAR_LEN = 17 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBLWCR1_LINEAR_WINDOW_MASK = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBLWCR1_LINEAR_WINDOW_MASK_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OCBLWCR2_LINEAR_WINDOW_ENABLE = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBLWCR2_SPARE_0 = 1 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBLWCR2_SPARE_0_LEN = 2 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBLWCR2_LINEAR_WINDOW_BAR = 3 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBLWCR2_LINEAR_WINDOW_BAR_LEN = 17 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBLWCR2_LINEAR_WINDOW_MASK = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBLWCR2_LINEAR_WINDOW_MASK_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OCBLWCR3_LINEAR_WINDOW_ENABLE = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBLWCR3_SPARE_0 = 1 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBLWCR3_SPARE_0_LEN = 2 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBLWCR3_LINEAR_WINDOW_BAR = 3 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBLWCR3_LINEAR_WINDOW_BAR_LEN = 17 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBLWCR3_LINEAR_WINDOW_MASK = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBLWCR3_LINEAR_WINDOW_MASK_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OCBLWSBR0_LINEAR_WINDOW_REGION = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBLWSBR0_LINEAR_WINDOW_REGION_LEN = 3 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBLWSBR0_LINEAR_WINDOW_BASE = 3 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBLWSBR0_LINEAR_WINDOW_BASE_LEN = 7 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OCBLWSBR1_LINEAR_WINDOW_REGION = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBLWSBR1_LINEAR_WINDOW_REGION_LEN = 3 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBLWSBR1_LINEAR_WINDOW_BASE = 3 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBLWSBR1_LINEAR_WINDOW_BASE_LEN = 7 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OCBLWSBR2_LINEAR_WINDOW_REGION = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBLWSBR2_LINEAR_WINDOW_REGION_LEN = 3 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBLWSBR2_LINEAR_WINDOW_BASE = 3 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBLWSBR2_LINEAR_WINDOW_BASE_LEN = 7 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OCBLWSBR3_LINEAR_WINDOW_REGION = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBLWSBR3_LINEAR_WINDOW_REGION_LEN = 3 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBLWSBR3_LINEAR_WINDOW_BASE = 3 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBLWSBR3_LINEAR_WINDOW_BASE_LEN = 7 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OCBLWSR0_LINEAR_WINDOW_SCRESP = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBLWSR0_LINEAR_WINDOW_SCRESP_LEN = 3 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBLWSR0_SPARE0 = 3 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBLWSR0_SPARE0_LEN = 5 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OCBLWSR1_LINEAR_WINDOW_SCRESP = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBLWSR1_LINEAR_WINDOW_SCRESP_LEN = 3 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBLWSR1_SPARE0 = 3 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBLWSR1_SPARE0_LEN = 5 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OCBLWSR2_LINEAR_WINDOW_SCRESP = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBLWSR2_LINEAR_WINDOW_SCRESP_LEN = 3 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBLWSR2_SPARE0 = 3 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBLWSR2_SPARE0_LEN = 5 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OCBLWSR3_LINEAR_WINDOW_SCRESP = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBLWSR3_LINEAR_WINDOW_SCRESP_LEN = 3 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBLWSR3_SPARE0 = 3 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBLWSR3_SPARE0_LEN = 5 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OCBSES0_PUSH_READ_UNDERFLOW = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSES0_PULL_WRITE_OVERFLOW = 1 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OCBSES1_PUSH_READ_UNDERFLOW = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSES1_PULL_WRITE_OVERFLOW = 1 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OCBSES2_PUSH_READ_UNDERFLOW = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSES2_PULL_WRITE_OVERFLOW = 1 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OCBSES3_PUSH_READ_UNDERFLOW = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSES3_PULL_WRITE_OVERFLOW = 1 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OCBSHBR0_PUSH_REGION = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSHBR0_PUSH_REGION_LEN = 3 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSHBR0_PUSH_START = 3 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSHBR0_PUSH_START_LEN = 26 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OCBSHBR1_PUSH_REGION = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSHBR1_PUSH_REGION_LEN = 3 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSHBR1_PUSH_START = 3 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSHBR1_PUSH_START_LEN = 26 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OCBSHBR2_PUSH_REGION = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSHBR2_PUSH_REGION_LEN = 3 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSHBR2_PUSH_START = 3 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSHBR2_PUSH_START_LEN = 26 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OCBSHBR3_PUSH_REGION = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSHBR3_PUSH_REGION_LEN = 3 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSHBR3_PUSH_START = 3 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSHBR3_PUSH_START_LEN = 26 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS0_PUSH_FULL = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS0_PUSH_EMPTY = 1 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS0_SPARE = 2 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS0_SPARE_LEN = 2 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS0_PUSH_INTR_ACTION_0_1 = 4 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS0_PUSH_INTR_ACTION_0_1_LEN = 2 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS0_PUSH_LENGTH = 6 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS0_PUSH_LENGTH_LEN = 5 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS0_PUSH_WRITE_PTR = 13 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS0_PUSH_WRITE_PTR_LEN = 5 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS0_PUSH_READ_PTR = 21 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS0_PUSH_READ_PTR_LEN = 5 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS0_PUSH_ENABLE = 31 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS1_PUSH_FULL = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS1_PUSH_EMPTY = 1 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS1_SPARE = 2 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS1_SPARE_LEN = 2 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS1_PUSH_INTR_ACTION_0_1 = 4 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS1_PUSH_INTR_ACTION_0_1_LEN = 2 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS1_PUSH_LENGTH = 6 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS1_PUSH_LENGTH_LEN = 5 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS1_PUSH_WRITE_PTR = 13 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS1_PUSH_WRITE_PTR_LEN = 5 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS1_PUSH_READ_PTR = 21 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS1_PUSH_READ_PTR_LEN = 5 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS1_PUSH_ENABLE = 31 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS2_PUSH_FULL = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS2_PUSH_EMPTY = 1 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS2_SPARE = 2 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS2_SPARE_LEN = 2 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS2_PUSH_INTR_ACTION_0_1 = 4 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS2_PUSH_INTR_ACTION_0_1_LEN = 2 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS2_PUSH_LENGTH = 6 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS2_PUSH_LENGTH_LEN = 5 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS2_PUSH_WRITE_PTR = 13 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS2_PUSH_WRITE_PTR_LEN = 5 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS2_PUSH_READ_PTR = 21 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS2_PUSH_READ_PTR_LEN = 5 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS2_PUSH_ENABLE = 31 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS3_PUSH_FULL = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS3_PUSH_EMPTY = 1 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS3_SPARE = 2 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS3_SPARE_LEN = 2 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS3_PUSH_INTR_ACTION_0_1 = 4 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS3_PUSH_INTR_ACTION_0_1_LEN = 2 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS3_PUSH_LENGTH = 6 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS3_PUSH_LENGTH_LEN = 5 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS3_PUSH_WRITE_PTR = 13 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS3_PUSH_WRITE_PTR_LEN = 5 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS3_PUSH_READ_PTR = 21 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS3_PUSH_READ_PTR_LEN = 5 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSHCS3_PUSH_ENABLE = 31 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OCBSLBR0_PULL_REGION = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSLBR0_PULL_REGION_LEN = 3 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSLBR0_PULL_START = 3 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSLBR0_PULL_START_LEN = 26 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OCBSLBR1_PULL_REGION = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSLBR1_PULL_REGION_LEN = 3 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSLBR1_PULL_START = 3 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSLBR1_PULL_START_LEN = 26 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OCBSLBR2_PULL_REGION = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSLBR2_PULL_REGION_LEN = 3 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSLBR2_PULL_START = 3 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSLBR2_PULL_START_LEN = 26 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OCBSLBR3_PULL_REGION = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSLBR3_PULL_REGION_LEN = 3 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSLBR3_PULL_START = 3 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSLBR3_PULL_START_LEN = 26 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS0_PULL_FULL = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS0_PULL_EMPTY = 1 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS0_SPARE = 2 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS0_SPARE_LEN = 2 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS0_PULL_INTR_ACTION_0_1 = 4 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS0_PULL_INTR_ACTION_0_1_LEN = 2 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS0_PULL_LENGTH = 6 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS0_PULL_LENGTH_LEN = 5 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS0_PULL_WRITE_PTR = 13 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS0_PULL_WRITE_PTR_LEN = 5 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS0_PULL_READ_PTR = 21 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS0_PULL_READ_PTR_LEN = 5 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS0_PULL_ENABLE = 31 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS1_PULL_FULL = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS1_PULL_EMPTY = 1 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS1_SPARE = 2 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS1_SPARE_LEN = 2 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS1_PULL_INTR_ACTION_0_1 = 4 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS1_PULL_INTR_ACTION_0_1_LEN = 2 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS1_PULL_LENGTH = 6 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS1_PULL_LENGTH_LEN = 5 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS1_PULL_WRITE_PTR = 13 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS1_PULL_WRITE_PTR_LEN = 5 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS1_PULL_READ_PTR = 21 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS1_PULL_READ_PTR_LEN = 5 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS1_PULL_ENABLE = 31 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS2_PULL_FULL = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS2_PULL_EMPTY = 1 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS2_SPARE = 2 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS2_SPARE_LEN = 2 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS2_PULL_INTR_ACTION_0_1 = 4 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS2_PULL_INTR_ACTION_0_1_LEN = 2 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS2_PULL_LENGTH = 6 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS2_PULL_LENGTH_LEN = 5 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS2_PULL_WRITE_PTR = 13 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS2_PULL_WRITE_PTR_LEN = 5 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS2_PULL_READ_PTR = 21 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS2_PULL_READ_PTR_LEN = 5 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS2_PULL_ENABLE = 31 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS3_PULL_FULL = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS3_PULL_EMPTY = 1 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS3_SPARE = 2 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS3_SPARE_LEN = 2 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS3_PULL_INTR_ACTION_0_1 = 4 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS3_PULL_INTR_ACTION_0_1_LEN = 2 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS3_PULL_LENGTH = 6 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS3_PULL_LENGTH_LEN = 5 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS3_PULL_WRITE_PTR = 13 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS3_PULL_WRITE_PTR_LEN = 5 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS3_PULL_READ_PTR = 21 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS3_PULL_READ_PTR_LEN = 5 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCBSLCS3_PULL_ENABLE = 31 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OCCFLG_OCC_FLAGS = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCCFLG_OCC_FLAGS_LEN = 32 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OCCFLG2_OCC_FLAGS = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCCFLG2_OCC_FLAGS_LEN = 32 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OCCHBR_OCC_HEARTBEAT_COUNT = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCCHBR_OCC_HEARTBEAT_COUNT_LEN = 16 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCCHBR_OCC_HEARTBEAT_EN = 16 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OCCMISC_CORE_EXT_INTR = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCCMISC_SPARE_1_3 = 1 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCCMISC_SPARE_1_3_LEN = 3 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCCMISC_PVREF_ERROR_EN = 4 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCCMISC_PVREF_ERROR_EN_LEN = 2 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCCMISC_PVREF_ERROR_GROSS = 6 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCCMISC_PVREF_ERROR_FINE = 7 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCCMISC_FIRMWARE_FAULT = 8 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCCMISC_FIRMWARE_NOTIFY = 9 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCCMISC_SPARE = 10 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCCMISC_SPARE_LEN = 6 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCCMISC_I2CM_INTR_STATUS = 16 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCCMISC_I2CM_INTR_STATUS_LEN = 3 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OCCS0_OCC_SCRATCH_N = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCCS0_OCC_SCRATCH_N_LEN = 32 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OCCS1_OCC_SCRATCH_N = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCCS1_OCC_SCRATCH_N_LEN = 32 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OCCS2_OCC_SCRATCH_N = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCCS2_OCC_SCRATCH_N_LEN = 32 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OCICFG_M0_PRIORITY = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCICFG_M0_PRIORITY_LEN = 2 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCICFG_M1_PRIORITY = 2 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCICFG_M1_PRIORITY_LEN = 2 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCICFG_M2_PRIORITY = 4 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCICFG_M2_PRIORITY_LEN = 2 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCICFG_M3_PRIORITY = 6 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCICFG_M3_PRIORITY_LEN = 2 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCICFG_M4_PRIORITY = 8 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCICFG_M4_PRIORITY_LEN = 2 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCICFG_M5_PRIORITY = 10 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCICFG_M5_PRIORITY_LEN = 2 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCICFG_M6_PRIORITY = 12 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCICFG_M6_PRIORITY_LEN = 2 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCICFG_M7_PRIORITY = 14 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCICFG_M7_PRIORITY_LEN = 2 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCICFG_M0_PRIORITY_SEL = 16 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCICFG_M1_PRIORITY_SEL = 17 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCICFG_M2_PRIORITY_SEL = 18 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCICFG_M3_PRIORITY_SEL = 19 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCICFG_OCICFG_RESERVED_20 = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCICFG_M5_PRIORITY_SEL = 21 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCICFG_OCICFG_RESERVED_23 = 22 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCICFG_M7_PRIORITY_SEL = 23 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCICFG_PLBARB_LOCKERR = 24 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCICFG_SPARE_24_31 = 25 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCICFG_SPARE_24_31_LEN = 7 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OCISR0_INTERRUPT_CRIT_STATUS_N = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCISR0_INTERRUPT_CRIT_STATUS_N_LEN = 32 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OCISR1_INTERRUPT_CRIT_STATUS_N = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_OCISR1_INTERRUPT_CRIT_STATUS_N_LEN = 32 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_ODISR0_INTERRUPT_DEBUG_STATUS_N = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_ODISR0_INTERRUPT_DEBUG_STATUS_N_LEN = 32 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_ODISR1_INTERRUPT_DEBUG_STATUS_N = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_ODISR1_INTERRUPT_DEBUG_STATUS_N_LEN = 32 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OEHDR_EVENT2HALT_DELAY = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_OEHDR_EVENT2HALT_DELAY_LEN = 20 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OHTMCR_HTM_SRC_SEL = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_OHTMCR_HTM_SRC_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_OCB_OCI_OHTMCR_HTM_STOP = 2 ;
+static const uint8_t P9N2_PU_OCB_OCI_OHTMCR_HTM_MARKER_SLAVE_ADRS = 3 ;
+static const uint8_t P9N2_PU_OCB_OCI_OHTMCR_HTM_MARKER_SLAVE_ADRS_LEN = 3 ;
+static const uint8_t P9N2_PU_OCB_OCI_OHTMCR_EVENT2HALT_MODE = 6 ;
+static const uint8_t P9N2_PU_OCB_OCI_OHTMCR_EVENT2HALT_MODE_LEN = 2 ;
+static const uint8_t P9N2_PU_OCB_OCI_OHTMCR_EVENT2HALT_EN = 8 ;
+static const uint8_t P9N2_PU_OCB_OCI_OHTMCR_EVENT2HALT_EN_LEN = 11 ;
+static const uint8_t P9N2_PU_OCB_OCI_OHTMCR_HTM_GPE_SRC_SEL = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OHTMCR_HTM_GPE_SRC_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_OCB_OCI_OHTMCR_EVENT2HALT_OCC = 23 ;
+static const uint8_t P9N2_PU_OCB_OCI_OHTMCR_EVENT2HALT_GPE0 = 24 ;
+static const uint8_t P9N2_PU_OCB_OCI_OHTMCR_EVENT2HALT_GPE1 = 25 ;
+static const uint8_t P9N2_PU_OCB_OCI_OHTMCR_EVENT2HALT_GPE2 = 26 ;
+static const uint8_t P9N2_PU_OCB_OCI_OHTMCR_EVENT2HALT_GPE3 = 27 ;
+static const uint8_t P9N2_PU_OCB_OCI_OHTMCR_EVENT2HALT_HALT_STATE = 31 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OIEPR0_INTERRUPT_EDGE_POL_N = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_OIEPR0_INTERRUPT_EDGE_POL_N_LEN = 32 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OIEPR1_INTERRUPT_EDGE_POL_N = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_OIEPR1_INTERRUPT_EDGE_POL_N_LEN = 32 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OIMR0_INTERRUPT_MASK_N = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_OIMR0_INTERRUPT_MASK_N_LEN = 32 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OIMR1_INTERRUPT_MASK_N = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_OIMR1_INTERRUPT_MASK_N_LEN = 32 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OIRR0A_INTERRUPT_ROUTE_A_N = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_OIRR0A_INTERRUPT_ROUTE_A_N_LEN = 32 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OIRR0B_INTERRUPT_ROUTE_A_N = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_OIRR0B_INTERRUPT_ROUTE_A_N_LEN = 32 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OIRR0C_INTERRUPT_ROUTE_A_N = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_OIRR0C_INTERRUPT_ROUTE_A_N_LEN = 32 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OIRR1A_INTERRUPT_ROUTE_A_N = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_OIRR1A_INTERRUPT_ROUTE_A_N_LEN = 32 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OIRR1B_INTERRUPT_ROUTE_A_N = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_OIRR1B_INTERRUPT_ROUTE_A_N_LEN = 32 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OIRR1C_INTERRUPT_ROUTE_A_N = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_OIRR1C_INTERRUPT_ROUTE_A_N_LEN = 32 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OISR0_DEBUGGER = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_OISR0_TRACE_TRIGGER = 1 ;
+static const uint8_t P9N2_PU_OCB_OCI_OISR0_OCC_ERROR = 2 ;
+static const uint8_t P9N2_PU_OCB_OCI_OISR0_PBA_ERROR = 3 ;
+static const uint8_t P9N2_PU_OCB_OCI_OISR0_SRT_ERROR = 4 ;
+static const uint8_t P9N2_PU_OCB_OCI_OISR0_GPE0_ERROR = 5 ;
+static const uint8_t P9N2_PU_OCB_OCI_OISR0_GPE1_ERROR = 6 ;
+static const uint8_t P9N2_PU_OCB_OCI_OISR0_GPE2_ERROR = 7 ;
+static const uint8_t P9N2_PU_OCB_OCI_OISR0_GPE3_ERROR = 8 ;
+static const uint8_t P9N2_PU_OCB_OCI_OISR0_PPC405_HALT = 9 ;
+static const uint8_t P9N2_PU_OCB_OCI_OISR0_ERROR = 10 ;
+static const uint8_t P9N2_PU_OCB_OCI_OISR0_SPARE_11 = 11 ;
+static const uint8_t P9N2_PU_OCB_OCI_OISR0_CHECK_STOP_PPC405 = 12 ;
+static const uint8_t P9N2_PU_OCB_OCI_OISR0_CHECK_STOP_GPE0 = 13 ;
+static const uint8_t P9N2_PU_OCB_OCI_OISR0_CHECK_STOP_GPE1 = 14 ;
+static const uint8_t P9N2_PU_OCB_OCI_OISR0_CHECK_STOP_GPE2 = 15 ;
+static const uint8_t P9N2_PU_OCB_OCI_OISR0_CHECK_STOP_GPE3 = 16 ;
+static const uint8_t P9N2_PU_OCB_OCI_OISR0_OCC_MALF_ALERT = 17 ;
+static const uint8_t P9N2_PU_OCB_OCI_OISR0_ADU_MALF_ALERT = 18 ;
+static const uint8_t P9N2_PU_OCB_OCI_OISR0_EXTERNAL_TRAP = 19 ;
+static const uint8_t P9N2_PU_OCB_OCI_OISR0_IVRM_PVREF_ERROR = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OISR0_OCC_TIMER0 = 21 ;
+static const uint8_t P9N2_PU_OCB_OCI_OISR0_OCC_TIMER1 = 22 ;
+static const uint8_t P9N2_PU_OCB_OCI_OISR0_AVS_SLAVE0 = 23 ;
+static const uint8_t P9N2_PU_OCB_OCI_OISR0_AVS_SLAVE1 = 24 ;
+static const uint8_t P9N2_PU_OCB_OCI_OISR0_IPI0_HI_PRIORITY = 25 ;
+static const uint8_t P9N2_PU_OCB_OCI_OISR0_IPI1_HI_PRIORITY = 26 ;
+static const uint8_t P9N2_PU_OCB_OCI_OISR0_IPI2_HI_PRIORITY = 27 ;
+static const uint8_t P9N2_PU_OCB_OCI_OISR0_IPI3_HI_PRIORITY = 28 ;
+static const uint8_t P9N2_PU_OCB_OCI_OISR0_IPI4_HI_PRIORITY = 29 ;
+static const uint8_t P9N2_PU_OCB_OCI_OISR0_ADCFSM_ONGOING = 30 ;
+static const uint8_t P9N2_PU_OCB_OCI_OISR0_I2CM_INTER = 31 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OISR1_PBAX_OCC_SEND_ATTN = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_OISR1_PBAX_OCC_PUSH0 = 1 ;
+static const uint8_t P9N2_PU_OCB_OCI_OISR1_PBAX_OCC_PUSH1 = 2 ;
+static const uint8_t P9N2_PU_OCB_OCI_OISR1_PBA_BCDE_ATTN = 3 ;
+static const uint8_t P9N2_PU_OCB_OCI_OISR1_PBA_BCUE_ATTN = 4 ;
+static const uint8_t P9N2_PU_OCB_OCI_OISR1_OCC_STRM0_PULL = 5 ;
+static const uint8_t P9N2_PU_OCB_OCI_OISR1_OCC_STRM0_PUSH = 6 ;
+static const uint8_t P9N2_PU_OCB_OCI_OISR1_OCC_STRM1_PULL = 7 ;
+static const uint8_t P9N2_PU_OCB_OCI_OISR1_OCC_STRM1_PUSH = 8 ;
+static const uint8_t P9N2_PU_OCB_OCI_OISR1_OCC_STRM2_PULL = 9 ;
+static const uint8_t P9N2_PU_OCB_OCI_OISR1_OCC_STRM2_PUSH = 10 ;
+static const uint8_t P9N2_PU_OCB_OCI_OISR1_OCC_STRM3_PULL = 11 ;
+static const uint8_t P9N2_PU_OCB_OCI_OISR1_OCC_STRM3_PUSH = 12 ;
+static const uint8_t P9N2_PU_OCB_OCI_OISR1_PMC_PCB_INTR_TYPE0_PENDING = 13 ;
+static const uint8_t P9N2_PU_OCB_OCI_OISR1_PMC_PCB_INTR_TYPE1_PENDING = 14 ;
+static const uint8_t P9N2_PU_OCB_OCI_OISR1_PMC_PCB_INTR_TYPE2_PENDING = 15 ;
+static const uint8_t P9N2_PU_OCB_OCI_OISR1_PMC_PCB_INTR_TYPE3_PENDING = 16 ;
+static const uint8_t P9N2_PU_OCB_OCI_OISR1_PMC_PCB_INTR_TYPE4_PENDING = 17 ;
+static const uint8_t P9N2_PU_OCB_OCI_OISR1_PMC_PCB_INTR_TYPE5_PENDING = 18 ;
+static const uint8_t P9N2_PU_OCB_OCI_OISR1_PMC_PCB_INTR_TYPE6_PENDING = 19 ;
+static const uint8_t P9N2_PU_OCB_OCI_OISR1_PMC_PCB_INTR_TYPE7_PENDING = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OISR1_PMC_O2S_0A_ONGOING = 21 ;
+static const uint8_t P9N2_PU_OCB_OCI_OISR1_PMC_O2S_0B_ONGOING = 22 ;
+static const uint8_t P9N2_PU_OCB_OCI_OISR1_PMC_O2S_1A_ONGOING = 23 ;
+static const uint8_t P9N2_PU_OCB_OCI_OISR1_PMC_O2S_1B_ONGOING = 24 ;
+static const uint8_t P9N2_PU_OCB_OCI_OISR1_PSSBRIDGE_ONGOING = 25 ;
+static const uint8_t P9N2_PU_OCB_OCI_OISR1_IPI0_LO_PRIORITY = 26 ;
+static const uint8_t P9N2_PU_OCB_OCI_OISR1_IPI1_LO_PRIORITY = 27 ;
+static const uint8_t P9N2_PU_OCB_OCI_OISR1_IPI2_LO_PRIORITY = 28 ;
+static const uint8_t P9N2_PU_OCB_OCI_OISR1_IPI3_LO_PRIORITY = 29 ;
+static const uint8_t P9N2_PU_OCB_OCI_OISR1_IPI4_LO_PRIORITY = 30 ;
+static const uint8_t P9N2_PU_OCB_OCI_OISR1_SPARE_31 = 31 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OITR0_INTERRUPT_TYPE_N = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_OITR0_INTERRUPT_TYPE_N_LEN = 32 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OITR1_INTERRUPT_TYPE_N = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_OITR1_INTERRUPT_TYPE_N_LEN = 32 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_ONISR0_INTERRUPT_NONCRIT_STATUS_N = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_ONISR0_INTERRUPT_NONCRIT_STATUS_N_LEN = 32 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_ONISR1_INTERRUPT_NONCRIT_STATUS_N = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_ONISR1_INTERRUPT_NONCRIT_STATUS_N_LEN = 32 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT0C0_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT0C0_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT0C1_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT0C1_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT0C10_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT0C10_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT0C11_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT0C11_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT0C12_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT0C12_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT0C13_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT0C13_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT0C14_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT0C14_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT0C15_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT0C15_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT0C16_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT0C16_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT0C17_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT0C17_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT0C18_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT0C18_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT0C19_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT0C19_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT0C2_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT0C2_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT0C20_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT0C20_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT0C21_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT0C21_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT0C22_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT0C22_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT0C23_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT0C23_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT0C3_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT0C3_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT0C4_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT0C4_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT0C5_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT0C5_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT0C6_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT0C6_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT0C7_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT0C7_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT0C8_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT0C8_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT0C9_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT0C9_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_0 = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_1 = 1 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_2 = 2 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_3 = 3 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_4 = 4 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_5 = 5 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_6 = 6 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_7 = 7 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_8 = 8 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_9 = 9 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_10 = 10 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_11 = 11 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_12 = 12 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_13 = 13 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_14 = 14 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_15 = 15 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_16 = 16 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_17 = 17 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_18 = 18 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_19 = 19 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_20 = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_21 = 21 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_22 = 22 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_23 = 23 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT1C0_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT1C0_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT1C1_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT1C1_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT1C10_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT1C10_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT1C11_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT1C11_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT1C12_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT1C12_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT1C13_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT1C13_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT1C14_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT1C14_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT1C15_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT1C15_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT1C16_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT1C16_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT1C17_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT1C17_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT1C18_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT1C18_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT1C19_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT1C19_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT1C2_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT1C2_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT1C20_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT1C20_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT1C21_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT1C21_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT1C22_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT1C22_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT1C23_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT1C23_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT1C3_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT1C3_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT1C4_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT1C4_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT1C5_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT1C5_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT1C6_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT1C6_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT1C7_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT1C7_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT1C8_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT1C8_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT1C9_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT1C9_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_0 = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_1 = 1 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_2 = 2 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_3 = 3 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_4 = 4 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_5 = 5 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_6 = 6 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_7 = 7 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_8 = 8 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_9 = 9 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_10 = 10 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_11 = 11 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_12 = 12 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_13 = 13 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_14 = 14 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_15 = 15 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_16 = 16 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_17 = 17 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_18 = 18 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_19 = 19 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_20 = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_21 = 21 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_22 = 22 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_23 = 23 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT2C0_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT2C0_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT2C1_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT2C1_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT2C10_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT2C10_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT2C11_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT2C11_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT2C12_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT2C12_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT2C13_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT2C13_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT2C14_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT2C14_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT2C15_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT2C15_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT2C16_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT2C16_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT2C17_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT2C17_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT2C18_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT2C18_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT2C19_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT2C19_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT2C2_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT2C2_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT2C20_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT2C20_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT2C21_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT2C21_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT2C22_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT2C22_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT2C23_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT2C23_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT2C3_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT2C3_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT2C4_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT2C4_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT2C5_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT2C5_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT2C6_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT2C6_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT2C7_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT2C7_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT2C8_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT2C8_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT2C9_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT2C9_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_0 = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_1 = 1 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_2 = 2 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_3 = 3 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_4 = 4 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_5 = 5 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_6 = 6 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_7 = 7 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_8 = 8 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_9 = 9 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_10 = 10 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_11 = 11 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_12 = 12 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_13 = 13 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_14 = 14 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_15 = 15 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_16 = 16 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_17 = 17 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_18 = 18 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_19 = 19 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_20 = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_21 = 21 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_22 = 22 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_23 = 23 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT3C0_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT3C0_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT3C1_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT3C1_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT3C10_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT3C10_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT3C11_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT3C11_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT3C12_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT3C12_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT3C13_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT3C13_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT3C14_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT3C14_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT3C15_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT3C15_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT3C16_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT3C16_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT3C17_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT3C17_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT3C18_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT3C18_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT3C19_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT3C19_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT3C2_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT3C2_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT3C20_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT3C20_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT3C21_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT3C21_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT3C22_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT3C22_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT3C23_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT3C23_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT3C3_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT3C3_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT3C4_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT3C4_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT3C5_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT3C5_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT3C6_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT3C6_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT3C7_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT3C7_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT3C8_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT3C8_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT3C9_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT3C9_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_0 = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_1 = 1 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_2 = 2 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_3 = 3 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_4 = 4 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_5 = 5 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_6 = 6 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_7 = 7 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_8 = 8 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_9 = 9 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_10 = 10 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_11 = 11 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_12 = 12 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_13 = 13 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_14 = 14 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_15 = 15 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_16 = 16 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_17 = 17 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_18 = 18 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_19 = 19 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_20 = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_21 = 21 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_22 = 22 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_23 = 23 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT4C0_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT4C0_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT4C1_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT4C1_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT4C10_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT4C10_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT4C11_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT4C11_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT4C12_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT4C12_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT4C13_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT4C13_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT4C14_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT4C14_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT4C15_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT4C15_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT4C16_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT4C16_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT4C17_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT4C17_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT4C18_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT4C18_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT4C19_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT4C19_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT4C2_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT4C2_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT4C20_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT4C20_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT4C21_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT4C21_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT4C22_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT4C22_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT4C23_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT4C23_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT4C3_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT4C3_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT4C4_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT4C4_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT4C5_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT4C5_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT4C6_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT4C6_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT4C7_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT4C7_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT4C8_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT4C8_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT4C9_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT4C9_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_0 = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_1 = 1 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_2 = 2 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_3 = 3 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_4 = 4 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_5 = 5 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_6 = 6 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_7 = 7 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_8 = 8 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_9 = 9 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_10 = 10 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_11 = 11 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_12 = 12 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_13 = 13 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_14 = 14 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_15 = 15 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_16 = 16 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_17 = 17 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_18 = 18 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_19 = 19 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_20 = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_21 = 21 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_22 = 22 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_23 = 23 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT5C0_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT5C0_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT5C1_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT5C1_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT5C10_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT5C10_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT5C11_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT5C11_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT5C12_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT5C12_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT5C13_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT5C13_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT5C14_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT5C14_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT5C15_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT5C15_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT5C16_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT5C16_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT5C17_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT5C17_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT5C18_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT5C18_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT5C19_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT5C19_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT5C2_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT5C2_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT5C20_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT5C20_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT5C21_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT5C21_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT5C22_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT5C22_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT5C23_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT5C23_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT5C3_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT5C3_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT5C4_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT5C4_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT5C5_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT5C5_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT5C6_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT5C6_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT5C7_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT5C7_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT5C8_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT5C8_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT5C9_PCB_INTR_TYPE_A_CORE_N = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT5C9_PCB_INTR_TYPE_A_CORE_N_LEN = 12 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_0 = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_1 = 1 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_2 = 2 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_3 = 3 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_4 = 4 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_5 = 5 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_6 = 6 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_7 = 7 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_8 = 8 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_9 = 9 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_10 = 10 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_11 = 11 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_12 = 12 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_13 = 13 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_14 = 14 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_15 = 15 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_16 = 16 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_17 = 17 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_18 = 18 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_19 = 19 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_20 = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_21 = 21 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_22 = 22 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_23 = 23 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT6PRB_PCB_INTR_TYPE_N_PENDING_0 = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT6PRB_PCB_INTR_TYPE_N_PENDING_1 = 1 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT6PRB_PCB_INTR_TYPE_N_PENDING_2 = 2 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT6PRB_PCB_INTR_TYPE_N_PENDING_3 = 3 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT6PRB_PCB_INTR_TYPE_N_PENDING_4 = 4 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT6PRB_PCB_INTR_TYPE_N_PENDING_5 = 5 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT6Q0_PCB_INTR_TYPE_A_QUAD_N = 28 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT6Q0_PCB_INTR_TYPE_A_QUAD_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT6Q1_PCB_INTR_TYPE_A_QUAD_N = 28 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT6Q1_PCB_INTR_TYPE_A_QUAD_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT6Q2_PCB_INTR_TYPE_A_QUAD_N = 28 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT6Q2_PCB_INTR_TYPE_A_QUAD_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT6Q3_PCB_INTR_TYPE_A_QUAD_N = 28 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT6Q3_PCB_INTR_TYPE_A_QUAD_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT6Q4_PCB_INTR_TYPE_A_QUAD_N = 28 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT6Q4_PCB_INTR_TYPE_A_QUAD_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT6Q5_PCB_INTR_TYPE_A_QUAD_N = 28 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT6Q5_PCB_INTR_TYPE_A_QUAD_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT7PRB_PCB_INTR_TYPE_N_PENDING_0 = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT7PRB_PCB_INTR_TYPE_N_PENDING_1 = 1 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT7PRB_PCB_INTR_TYPE_N_PENDING_2 = 2 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT7PRB_PCB_INTR_TYPE_N_PENDING_3 = 3 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT7PRB_PCB_INTR_TYPE_N_PENDING_4 = 4 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT7PRB_PCB_INTR_TYPE_N_PENDING_5 = 5 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT7Q0_PCB_INTR_TYPE_A_QUAD_N = 28 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT7Q0_PCB_INTR_TYPE_A_QUAD_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT7Q1_PCB_INTR_TYPE_A_QUAD_N = 28 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT7Q1_PCB_INTR_TYPE_A_QUAD_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT7Q2_PCB_INTR_TYPE_A_QUAD_N = 28 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT7Q2_PCB_INTR_TYPE_A_QUAD_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT7Q3_PCB_INTR_TYPE_A_QUAD_N = 28 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT7Q3_PCB_INTR_TYPE_A_QUAD_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT7Q4_PCB_INTR_TYPE_A_QUAD_N = 28 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT7Q4_PCB_INTR_TYPE_A_QUAD_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OPIT7Q5_PCB_INTR_TYPE_A_QUAD_N = 28 ;
+static const uint8_t P9N2_PU_OCB_OCI_OPIT7Q5_PCB_INTR_TYPE_A_QUAD_N_LEN = 4 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OTBR_TIMEBASE = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_OTBR_TIMEBASE_LEN = 32 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OTR0_TIMEOUT_N = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_OTR0_CONTROL_N = 1 ;
+static const uint8_t P9N2_PU_OCB_OCI_OTR0_AUTO_RELOAD_N = 2 ;
+static const uint8_t P9N2_PU_OCB_OCI_OTR0_SPARE_N = 3 ;
+static const uint8_t P9N2_PU_OCB_OCI_OTR0_SPARE_N_LEN = 13 ;
+static const uint8_t P9N2_PU_OCB_OCI_OTR0_TIMER_N = 16 ;
+static const uint8_t P9N2_PU_OCB_OCI_OTR0_TIMER_N_LEN = 16 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OTR1_TIMEOUT_N = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_OTR1_CONTROL_N = 1 ;
+static const uint8_t P9N2_PU_OCB_OCI_OTR1_AUTO_RELOAD_N = 2 ;
+static const uint8_t P9N2_PU_OCB_OCI_OTR1_SPARE_N = 3 ;
+static const uint8_t P9N2_PU_OCB_OCI_OTR1_SPARE_N_LEN = 13 ;
+static const uint8_t P9N2_PU_OCB_OCI_OTR1_TIMER_N = 16 ;
+static const uint8_t P9N2_PU_OCB_OCI_OTR1_TIMER_N_LEN = 16 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OUISR0_INTERRUPT_UNCON_STATUS_N = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_OUISR0_INTERRUPT_UNCON_STATUS_N_LEN = 32 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_OUISR1_INTERRUPT_UNCON_STATUS_N = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_OUISR1_INTERRUPT_UNCON_STATUS_N_LEN = 32 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_QCSR_EX_CONFIG = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_QCSR_EX_CONFIG_LEN = 12 ;
+static const uint8_t P9N2_PU_OCB_OCI_QCSR_RESERVED_12_30 = 12 ;
+static const uint8_t P9N2_PU_OCB_OCI_QCSR_RESERVED_12_30_LEN = 19 ;
+static const uint8_t P9N2_PU_OCB_OCI_QCSR_CHANGE_IN_PROGRESS = 31 ;
+
+static const uint8_t P9N2_PU_OCB_OCI_QSSR_L2_STOPPED = 0 ;
+static const uint8_t P9N2_PU_OCB_OCI_QSSR_L2_STOPPED_LEN = 12 ;
+static const uint8_t P9N2_PU_OCB_OCI_QSSR_RESERVED_12_13 = 12 ;
+static const uint8_t P9N2_PU_OCB_OCI_QSSR_RESERVED_12_13_LEN = 2 ;
+static const uint8_t P9N2_PU_OCB_OCI_QSSR_QUAD_STOPPED = 14 ;
+static const uint8_t P9N2_PU_OCB_OCI_QSSR_QUAD_STOPPED_LEN = 6 ;
+static const uint8_t P9N2_PU_OCB_OCI_QSSR_STOP_ENTRY_ONGOING = 20 ;
+static const uint8_t P9N2_PU_OCB_OCI_QSSR_STOP_ENTRY_ONGOING_LEN = 6 ;
+static const uint8_t P9N2_PU_OCB_OCI_QSSR_STOP_EXIT_ONGOING = 26 ;
+static const uint8_t P9N2_PU_OCB_OCI_QSSR_STOP_EXIT_ONGOING_LEN = 6 ;
+
+static const uint8_t P9N2_PU_OCB_PIB_OACR_OCI_PRIORITY_MODE = 0 ;
+static const uint8_t P9N2_PU_OCB_PIB_OACR_OCI_PRIORITY_ORDER = 1 ;
+static const uint8_t P9N2_PU_OCB_PIB_OACR_OCI_PRIORITY_ORDER_LEN = 3 ;
+static const uint8_t P9N2_PU_OCB_PIB_OACR_OCI_HI_BUS_MODE = 4 ;
+static const uint8_t P9N2_PU_OCB_PIB_OACR_OCI_READ_PIPELINE_CONTROL = 5 ;
+static const uint8_t P9N2_PU_OCB_PIB_OACR_OCI_READ_PIPELINE_CONTROL_LEN = 2 ;
+static const uint8_t P9N2_PU_OCB_PIB_OACR_OCI_WRITE_PIPELINE_CONTROL = 7 ;
+
+static const uint8_t P9N2_PU_OCB_PIB_OCBAR0_OCI_REGION = 0 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBAR0_OCI_REGION_LEN = 3 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBAR0_ADDRESS = 3 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBAR0_ADDRESS_LEN = 26 ;
+
+static const uint8_t P9N2_PU_OCB_PIB_OCBAR1_OCI_REGION = 0 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBAR1_OCI_REGION_LEN = 3 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBAR1_ADDRESS = 3 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBAR1_ADDRESS_LEN = 26 ;
+
+static const uint8_t P9N2_PU_OCB_PIB_OCBAR2_OCI_REGION = 0 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBAR2_OCI_REGION_LEN = 3 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBAR2_ADDRESS = 3 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBAR2_ADDRESS_LEN = 26 ;
+
+static const uint8_t P9N2_PU_OCB_PIB_OCBAR3_OCI_REGION = 0 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBAR3_OCI_REGION_LEN = 3 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBAR3_ADDRESS = 3 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBAR3_ADDRESS_LEN = 26 ;
+
+static const uint8_t P9N2_PU_OCB_PIB_OCBCSR0_PULL_READ_UNDERFLOW = 0 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBCSR0_PUSH_WRITE_OVERFLOW = 1 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBCSR0_PULL_READ_UNDERFLOW_EN = 2 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBCSR0_PUSH_WRITE_OVERFLOW_EN = 3 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBCSR0_STREAM_MODE = 4 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBCSR0_STREAM_TYPE = 5 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBCSR0_SPARE0 = 6 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBCSR0_SPARE0_LEN = 2 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBCSR0_OCI_TIMEOUT = 8 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBCSR0_OCI_READ_DATA_PARITY = 9 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBCSR0_OCI_SLAVE_ERROR = 10 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBCSR0_ADDR_PARITY_ERR = 11 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBCSR0_DATA_PARITY_ERR = 12 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBCSR0_SPARE1 = 13 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBCSR0_FSM_ERR = 14 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBCSR0_SPARE2 = 15 ;
+
+static const uint8_t P9N2_PU_OCB_PIB_OCBCSR1_PULL_READ_UNDERFLOW = 0 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBCSR1_PUSH_WRITE_OVERFLOW = 1 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBCSR1_PULL_READ_UNDERFLOW_EN = 2 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBCSR1_PUSH_WRITE_OVERFLOW_EN = 3 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBCSR1_STREAM_MODE = 4 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBCSR1_STREAM_TYPE = 5 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBCSR1_SPARE0 = 6 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBCSR1_SPARE0_LEN = 2 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBCSR1_OCI_TIMEOUT = 8 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBCSR1_OCI_READ_DATA_PARITY = 9 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBCSR1_OCI_SLAVE_ERROR = 10 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBCSR1_ADDR_PARITY_ERR = 11 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBCSR1_DATA_PARITY_ERR = 12 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBCSR1_SPARE1 = 13 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBCSR1_FSM_ERR = 14 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBCSR1_SPARE2 = 15 ;
+
+static const uint8_t P9N2_PU_OCB_PIB_OCBCSR2_PULL_READ_UNDERFLOW = 0 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBCSR2_PUSH_WRITE_OVERFLOW = 1 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBCSR2_PULL_READ_UNDERFLOW_EN = 2 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBCSR2_PUSH_WRITE_OVERFLOW_EN = 3 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBCSR2_STREAM_MODE = 4 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBCSR2_STREAM_TYPE = 5 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBCSR2_SPARE0 = 6 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBCSR2_SPARE0_LEN = 2 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBCSR2_OCI_TIMEOUT = 8 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBCSR2_OCI_READ_DATA_PARITY = 9 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBCSR2_OCI_SLAVE_ERROR = 10 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBCSR2_ADDR_PARITY_ERR = 11 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBCSR2_DATA_PARITY_ERR = 12 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBCSR2_SPARE1 = 13 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBCSR2_FSM_ERR = 14 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBCSR2_SPARE2 = 15 ;
+
+static const uint8_t P9N2_PU_OCB_PIB_OCBCSR3_PULL_READ_UNDERFLOW = 0 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBCSR3_PUSH_WRITE_OVERFLOW = 1 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBCSR3_PULL_READ_UNDERFLOW_EN = 2 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBCSR3_PUSH_WRITE_OVERFLOW_EN = 3 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBCSR3_STREAM_MODE = 4 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBCSR3_STREAM_TYPE = 5 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBCSR3_SPARE0 = 6 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBCSR3_SPARE0_LEN = 2 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBCSR3_OCI_TIMEOUT = 8 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBCSR3_OCI_READ_DATA_PARITY = 9 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBCSR3_OCI_SLAVE_ERROR = 10 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBCSR3_ADDR_PARITY_ERR = 11 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBCSR3_DATA_PARITY_ERR = 12 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBCSR3_SPARE1 = 13 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBCSR3_FSM_ERR = 14 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBCSR3_SPARE2 = 15 ;
+
+static const uint8_t P9N2_PU_OCB_PIB_OCBDR0_DATA = 0 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBDR0_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OCB_PIB_OCBDR1_DATA = 0 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBDR1_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OCB_PIB_OCBDR2_DATA = 0 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBDR2_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OCB_PIB_OCBDR3_DATA = 0 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBDR3_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_PU_OCB_PIB_OCBEAR_ERROR_ADDRESS = 0 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBEAR_ERROR_ADDRESS_LEN = 32 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBEAR_RESERVED_32_34 = 32 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBEAR_RESERVED_32_34_LEN = 3 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBEAR_DIRECT_BRIDGE_SOURCE = 35 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBEAR_INDIRECT_BRIDGE_0_SOURCE = 36 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBEAR_INDIRECT_BRIDGE_1_SOURCE = 37 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBEAR_INDIRECT_BRIDGE_2_SOURCE = 38 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBEAR_INDIRECT_BRIDGE_3_SOURCE = 39 ;
+
+static const uint8_t P9N2_PU_OCB_PIB_OCBESR0_ERROR_ADDR = 0 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBESR0_ERROR_ADDR_LEN = 32 ;
+
+static const uint8_t P9N2_PU_OCB_PIB_OCBESR1_ERROR_ADDR = 0 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBESR1_ERROR_ADDR_LEN = 32 ;
+
+static const uint8_t P9N2_PU_OCB_PIB_OCBESR2_ERROR_ADDR = 0 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBESR2_ERROR_ADDR_LEN = 32 ;
+
+static const uint8_t P9N2_PU_OCB_PIB_OCBESR3_ERROR_ADDR = 0 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCBESR3_ERROR_ADDR_LEN = 32 ;
+
+static const uint8_t P9N2_PU_OCB_PIB_OCDBG_MST_DIS_ABUSPAREN = 0 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCDBG_MST_DIS_BEPAREN = 1 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCDBG_MST_DIS_WRDBUSPAREN = 2 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCDBG_MST_DIS_RDDBUSPAR = 3 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCDBG_MST_SPARE = 4 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCDBG_SLV_DIS_SACK = 5 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCDBG_SLV_DIS_ABUSPAR = 6 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCDBG_SLV_DIS_BEPAR = 7 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCDBG_SLV_DIS_BE = 8 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCDBG_SLV_DIS_WRDBUSPAR = 9 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCDBG_SLV_DIS_RDDBUSPAREN = 10 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCDBG_SLV_SPARE = 11 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCDBG_SPARE = 12 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCDBG_SPARE_LEN = 4 ;
+
+static const uint8_t P9N2_PU_OCB_PIB_OCR_CORE_RESET = 0 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCR_CHIP_RESET = 1 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCR_SYSTEM_RESET = 2 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCR_OCI_ARB_RESET = 3 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCR_TRACE_DISABLE = 4 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCR_TRACE_EVENT = 5 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCR_DBG_UNCONDITIONAL_EVENT = 6 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCR_EXT_INTERRUPT = 7 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCR_CRITICAL_INTERRUPT = 8 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCR_SLAVE_RESET_TO_405_ENABLE = 9 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCR_OCC_DBG_HALT = 10 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCR_SPARE = 11 ;
+static const uint8_t P9N2_PU_OCB_PIB_OCR_SPARE_LEN = 5 ;
+
+static const uint8_t P9N2_PU_OCB_PIB_OEAR_OCI_TIMEOUT_ADDR = 0 ;
+static const uint8_t P9N2_PU_OCB_PIB_OEAR_OCI_TIMEOUT_ADDR_LEN = 32 ;
+
+static const uint8_t P9N2_PU_OCB_PIB_OESR_OCI_M0_TIMEOUT_ERROR = 0 ;
+static const uint8_t P9N2_PU_OCB_PIB_OESR_OCI_M0_RW_STATUS = 1 ;
+static const uint8_t P9N2_PU_OCB_PIB_OESR_OCI_M0_FLCK = 2 ;
+static const uint8_t P9N2_PU_OCB_PIB_OESR_OCI_M0_OEAR_LOCK = 3 ;
+static const uint8_t P9N2_PU_OCB_PIB_OESR_OCI_M1_TIMEOUT_ERROR = 4 ;
+static const uint8_t P9N2_PU_OCB_PIB_OESR_OCI_M1_RW_STATUS = 5 ;
+static const uint8_t P9N2_PU_OCB_PIB_OESR_OCI_M1_FLCK = 6 ;
+static const uint8_t P9N2_PU_OCB_PIB_OESR_OCI_M1_OEAR_LOCK = 7 ;
+static const uint8_t P9N2_PU_OCB_PIB_OESR_OCI_M2_TIMEOUT_ERROR = 8 ;
+static const uint8_t P9N2_PU_OCB_PIB_OESR_OCI_M2_RW_STATUS = 9 ;
+static const uint8_t P9N2_PU_OCB_PIB_OESR_OCI_M2_FLCK = 10 ;
+static const uint8_t P9N2_PU_OCB_PIB_OESR_OCI_M2_OEAR_LOCK = 11 ;
+static const uint8_t P9N2_PU_OCB_PIB_OESR_OCI_M3_TIMEOUT_ERROR = 12 ;
+static const uint8_t P9N2_PU_OCB_PIB_OESR_OCI_M3_RW_STATUS = 13 ;
+static const uint8_t P9N2_PU_OCB_PIB_OESR_OCI_M3_FLCK = 14 ;
+static const uint8_t P9N2_PU_OCB_PIB_OESR_OCI_M3_OEAR_LOCK = 15 ;
+static const uint8_t P9N2_PU_OCB_PIB_OESR_OCI_M4_TIMEOUT_ERROR = 16 ;
+static const uint8_t P9N2_PU_OCB_PIB_OESR_OCI_M4_RW_STATUS = 17 ;
+static const uint8_t P9N2_PU_OCB_PIB_OESR_OCI_M4_FLCK = 18 ;
+static const uint8_t P9N2_PU_OCB_PIB_OESR_OCI_M4_OEAR_LOCK = 19 ;
+static const uint8_t P9N2_PU_OCB_PIB_OESR_OCI_M5_TIMEOUT_ERROR = 20 ;
+static const uint8_t P9N2_PU_OCB_PIB_OESR_OCI_M5_RW_STATUS = 21 ;
+static const uint8_t P9N2_PU_OCB_PIB_OESR_OCI_M5_FLCK = 22 ;
+static const uint8_t P9N2_PU_OCB_PIB_OESR_OCI_M5_OEAR_LOCK = 23 ;
+static const uint8_t P9N2_PU_OCB_PIB_OESR_OCI_M6_TIMEOUT_ERROR = 24 ;
+static const uint8_t P9N2_PU_OCB_PIB_OESR_OCI_M6_RW_STATUS = 25 ;
+static const uint8_t P9N2_PU_OCB_PIB_OESR_OCI_M6_FLCK = 26 ;
+static const uint8_t P9N2_PU_OCB_PIB_OESR_OCI_M6_OEAR_LOCK = 27 ;
+static const uint8_t P9N2_PU_OCB_PIB_OESR_OCI_M7_TIMEOUT_ERROR = 28 ;
+static const uint8_t P9N2_PU_OCB_PIB_OESR_OCI_M7_RW_STATUS = 29 ;
+static const uint8_t P9N2_PU_OCB_PIB_OESR_OCI_M7_FLCK = 30 ;
+static const uint8_t P9N2_PU_OCB_PIB_OESR_OCI_M7_OEAR_LOCK = 31 ;
+
+static const uint8_t P9N2_PU_OCB_PIB_OPPCINJ_OCI_ERR_INJ_DCU = 0 ;
+static const uint8_t P9N2_PU_OCB_PIB_OPPCINJ_OCI_ERR_INJ_ICU = 1 ;
+static const uint8_t P9N2_PU_OCB_PIB_OPPCINJ_OCI_ERR_INJ_CE_UE = 2 ;
+static const uint8_t P9N2_PU_OCB_PIB_OPPCINJ_OCI_ERR_INJ_SINGL_CONT = 3 ;
+
+static const uint8_t P9N2_PU_OCB_PIB_OSTOEAR_OCC_SPCL_TIMEOUT_ADDR = 0 ;
+static const uint8_t P9N2_PU_OCB_PIB_OSTOEAR_OCC_SPCL_TIMEOUT_ADDR_LEN = 32 ;
+
+static const uint8_t P9N2_PU_OCB_PIB_OSTOESR_ICU_TIMEOUT_ERROR = 0 ;
+static const uint8_t P9N2_PU_OCB_PIB_OSTOESR_ICU_RNW = 1 ;
+static const uint8_t P9N2_PU_OCB_PIB_OSTOESR_RESERVED_2_3 = 2 ;
+static const uint8_t P9N2_PU_OCB_PIB_OSTOESR_RESERVED_2_3_LEN = 2 ;
+static const uint8_t P9N2_PU_OCB_PIB_OSTOESR_DCU_TIMEOUT_ERROR = 4 ;
+static const uint8_t P9N2_PU_OCB_PIB_OSTOESR_DCU_RNW = 5 ;
+static const uint8_t P9N2_PU_OCB_PIB_OSTOESR_RESERVED_6_7 = 6 ;
+static const uint8_t P9N2_PU_OCB_PIB_OSTOESR_RESERVED_6_7_LEN = 2 ;
+
+static const uint8_t P9N2_PU_OCB_PIB_OTDCR_TRACE_BUS_EN = 0 ;
+static const uint8_t P9N2_PU_OCB_PIB_OTDCR_TRACE_MUX_SEL = 1 ;
+static const uint8_t P9N2_PU_OCB_PIB_OTDCR_OCC_TRACE_MUX_SEL = 2 ;
+static const uint8_t P9N2_PU_OCB_PIB_OTDCR_OCC_TRACE_MUX_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_OCB_PIB_OTDCR_OCI_TRACE_MUX_SEL = 4 ;
+static const uint8_t P9N2_PU_OCB_PIB_OTDCR_OCI_TRACE_MUX_SEL_LEN = 4 ;
+
+static const uint8_t P9N2_PEC_OPCG_ALIGN_INOP = 0 ;
+static const uint8_t P9N2_PEC_OPCG_ALIGN_INOP_LEN = 4 ;
+static const uint8_t P9N2_PEC_OPCG_ALIGN_SNOP = 4 ;
+static const uint8_t P9N2_PEC_OPCG_ALIGN_SNOP_LEN = 4 ;
+static const uint8_t P9N2_PEC_OPCG_ALIGN_ENOP = 8 ;
+static const uint8_t P9N2_PEC_OPCG_ALIGN_ENOP_LEN = 4 ;
+static const uint8_t P9N2_PEC_OPCG_ALIGN_INOP_WAIT = 12 ;
+static const uint8_t P9N2_PEC_OPCG_ALIGN_INOP_WAIT_LEN = 8 ;
+static const uint8_t P9N2_PEC_OPCG_ALIGN_SNOP_WAIT = 20 ;
+static const uint8_t P9N2_PEC_OPCG_ALIGN_SNOP_WAIT_LEN = 12 ;
+static const uint8_t P9N2_PEC_OPCG_ALIGN_ENOP_WAIT = 32 ;
+static const uint8_t P9N2_PEC_OPCG_ALIGN_ENOP_WAIT_LEN = 8 ;
+static const uint8_t P9N2_PEC_OPCG_ALIGN_INOP_FORCE_SG = 40 ;
+static const uint8_t P9N2_PEC_OPCG_ALIGN_SNOP_FORCE_SG = 41 ;
+static const uint8_t P9N2_PEC_OPCG_ALIGN_ENOP_FORCE_SG = 42 ;
+static const uint8_t P9N2_PEC_OPCG_ALIGN_NO_WAIT_ON_CLK_CMD = 43 ;
+static const uint8_t P9N2_PEC_OPCG_ALIGN_SOURCE_SELECT = 44 ;
+static const uint8_t P9N2_PEC_OPCG_ALIGN_SOURCE_SELECT_LEN = 2 ;
+static const uint8_t P9N2_PEC_OPCG_ALIGN_UNUSED46 = 46 ;
+static const uint8_t P9N2_PEC_OPCG_ALIGN_SCAN_RATIO = 47 ;
+static const uint8_t P9N2_PEC_OPCG_ALIGN_SCAN_RATIO_LEN = 5 ;
+static const uint8_t P9N2_PEC_OPCG_ALIGN_WAIT_CYCLES = 52 ;
+static const uint8_t P9N2_PEC_OPCG_ALIGN_WAIT_CYCLES_LEN = 12 ;
+
+static const uint8_t P9N2_PEC_OPCG_CAPT1_COUNT = 0 ;
+static const uint8_t P9N2_PEC_OPCG_CAPT1_COUNT_LEN = 4 ;
+static const uint8_t P9N2_PEC_OPCG_CAPT1_SEQ_01 = 4 ;
+static const uint8_t P9N2_PEC_OPCG_CAPT1_SEQ_01_LEN = 5 ;
+static const uint8_t P9N2_PEC_OPCG_CAPT1_SEQ_02 = 9 ;
+static const uint8_t P9N2_PEC_OPCG_CAPT1_SEQ_02_LEN = 5 ;
+static const uint8_t P9N2_PEC_OPCG_CAPT1_SEQ_03 = 14 ;
+static const uint8_t P9N2_PEC_OPCG_CAPT1_SEQ_03_LEN = 5 ;
+static const uint8_t P9N2_PEC_OPCG_CAPT1_SEQ_04 = 19 ;
+static const uint8_t P9N2_PEC_OPCG_CAPT1_SEQ_04_LEN = 5 ;
+static const uint8_t P9N2_PEC_OPCG_CAPT1_SEQ_05 = 24 ;
+static const uint8_t P9N2_PEC_OPCG_CAPT1_SEQ_05_LEN = 5 ;
+static const uint8_t P9N2_PEC_OPCG_CAPT1_SEQ_06 = 29 ;
+static const uint8_t P9N2_PEC_OPCG_CAPT1_SEQ_06_LEN = 5 ;
+static const uint8_t P9N2_PEC_OPCG_CAPT1_SEQ_07 = 34 ;
+static const uint8_t P9N2_PEC_OPCG_CAPT1_SEQ_07_LEN = 5 ;
+static const uint8_t P9N2_PEC_OPCG_CAPT1_SEQ_08 = 39 ;
+static const uint8_t P9N2_PEC_OPCG_CAPT1_SEQ_08_LEN = 5 ;
+static const uint8_t P9N2_PEC_OPCG_CAPT1_SEQ_09 = 44 ;
+static const uint8_t P9N2_PEC_OPCG_CAPT1_SEQ_09_LEN = 5 ;
+static const uint8_t P9N2_PEC_OPCG_CAPT1_SEQ_10 = 49 ;
+static const uint8_t P9N2_PEC_OPCG_CAPT1_SEQ_10_LEN = 5 ;
+static const uint8_t P9N2_PEC_OPCG_CAPT1_SEQ_11 = 54 ;
+static const uint8_t P9N2_PEC_OPCG_CAPT1_SEQ_11_LEN = 5 ;
+static const uint8_t P9N2_PEC_OPCG_CAPT1_SEQ_12 = 59 ;
+static const uint8_t P9N2_PEC_OPCG_CAPT1_SEQ_12_LEN = 5 ;
+
+static const uint8_t P9N2_PEC_OPCG_CAPT2_UNUSED = 0 ;
+static const uint8_t P9N2_PEC_OPCG_CAPT2_UNUSED_LEN = 4 ;
+static const uint8_t P9N2_PEC_OPCG_CAPT2_SEQ_13_01EVEN = 4 ;
+static const uint8_t P9N2_PEC_OPCG_CAPT2_SEQ_13_01EVEN_LEN = 5 ;
+static const uint8_t P9N2_PEC_OPCG_CAPT2_SEQ_14_01ODD = 9 ;
+static const uint8_t P9N2_PEC_OPCG_CAPT2_SEQ_14_01ODD_LEN = 5 ;
+static const uint8_t P9N2_PEC_OPCG_CAPT2_SEQ_15_02EVEN = 14 ;
+static const uint8_t P9N2_PEC_OPCG_CAPT2_SEQ_15_02EVEN_LEN = 5 ;
+static const uint8_t P9N2_PEC_OPCG_CAPT2_SEQ_16_02ODD = 19 ;
+static const uint8_t P9N2_PEC_OPCG_CAPT2_SEQ_16_02ODD_LEN = 5 ;
+static const uint8_t P9N2_PEC_OPCG_CAPT2_SEQ_17_03EVEN = 24 ;
+static const uint8_t P9N2_PEC_OPCG_CAPT2_SEQ_17_03EVEN_LEN = 5 ;
+static const uint8_t P9N2_PEC_OPCG_CAPT2_SEQ_18_03ODD = 29 ;
+static const uint8_t P9N2_PEC_OPCG_CAPT2_SEQ_18_03ODD_LEN = 5 ;
+static const uint8_t P9N2_PEC_OPCG_CAPT2_SEQ_19_04EVEN = 34 ;
+static const uint8_t P9N2_PEC_OPCG_CAPT2_SEQ_19_04EVEN_LEN = 5 ;
+static const uint8_t P9N2_PEC_OPCG_CAPT2_SEQ_20_04ODD = 39 ;
+static const uint8_t P9N2_PEC_OPCG_CAPT2_SEQ_20_04ODD_LEN = 5 ;
+static const uint8_t P9N2_PEC_OPCG_CAPT2_SEQ_21_05EVEN = 44 ;
+static const uint8_t P9N2_PEC_OPCG_CAPT2_SEQ_21_05EVEN_LEN = 5 ;
+static const uint8_t P9N2_PEC_OPCG_CAPT2_SEQ_22_05ODD = 49 ;
+static const uint8_t P9N2_PEC_OPCG_CAPT2_SEQ_22_05ODD_LEN = 5 ;
+static const uint8_t P9N2_PEC_OPCG_CAPT2_SEQ_23_06EVEN = 54 ;
+static const uint8_t P9N2_PEC_OPCG_CAPT2_SEQ_23_06EVEN_LEN = 5 ;
+static const uint8_t P9N2_PEC_OPCG_CAPT2_SEQ_24_06ODD = 59 ;
+static const uint8_t P9N2_PEC_OPCG_CAPT2_SEQ_24_06ODD_LEN = 5 ;
+
+static const uint8_t P9N2_PEC_OPCG_CAPT3_UNUSED = 0 ;
+static const uint8_t P9N2_PEC_OPCG_CAPT3_UNUSED_LEN = 4 ;
+static const uint8_t P9N2_PEC_OPCG_CAPT3_SEQ_07EVEN = 4 ;
+static const uint8_t P9N2_PEC_OPCG_CAPT3_SEQ_07EVEN_LEN = 5 ;
+static const uint8_t P9N2_PEC_OPCG_CAPT3_SEQ_07ODD = 9 ;
+static const uint8_t P9N2_PEC_OPCG_CAPT3_SEQ_07ODD_LEN = 5 ;
+static const uint8_t P9N2_PEC_OPCG_CAPT3_SEQ_08EVEN = 14 ;
+static const uint8_t P9N2_PEC_OPCG_CAPT3_SEQ_08EVEN_LEN = 5 ;
+static const uint8_t P9N2_PEC_OPCG_CAPT3_SEQ_08ODD = 19 ;
+static const uint8_t P9N2_PEC_OPCG_CAPT3_SEQ_08ODD_LEN = 5 ;
+static const uint8_t P9N2_PEC_OPCG_CAPT3_SEQ_09EVEN = 24 ;
+static const uint8_t P9N2_PEC_OPCG_CAPT3_SEQ_09EVEN_LEN = 5 ;
+static const uint8_t P9N2_PEC_OPCG_CAPT3_SEQ_09ODD = 29 ;
+static const uint8_t P9N2_PEC_OPCG_CAPT3_SEQ_09ODD_LEN = 5 ;
+static const uint8_t P9N2_PEC_OPCG_CAPT3_SEQ_10EVEN = 34 ;
+static const uint8_t P9N2_PEC_OPCG_CAPT3_SEQ_10EVEN_LEN = 5 ;
+static const uint8_t P9N2_PEC_OPCG_CAPT3_SEQ_10ODD = 39 ;
+static const uint8_t P9N2_PEC_OPCG_CAPT3_SEQ_10ODD_LEN = 5 ;
+static const uint8_t P9N2_PEC_OPCG_CAPT3_SEQ_11EVEN = 44 ;
+static const uint8_t P9N2_PEC_OPCG_CAPT3_SEQ_11EVEN_LEN = 5 ;
+static const uint8_t P9N2_PEC_OPCG_CAPT3_SEQ_11ODD = 49 ;
+static const uint8_t P9N2_PEC_OPCG_CAPT3_SEQ_11ODD_LEN = 5 ;
+static const uint8_t P9N2_PEC_OPCG_CAPT3_SEQ_12EVEN = 54 ;
+static const uint8_t P9N2_PEC_OPCG_CAPT3_SEQ_12EVEN_LEN = 5 ;
+static const uint8_t P9N2_PEC_OPCG_CAPT3_SEQ_12ODD = 59 ;
+static const uint8_t P9N2_PEC_OPCG_CAPT3_SEQ_12ODD_LEN = 5 ;
+
+static const uint8_t P9N2_PEC_OPCG_REG0_RUNN_MODE = 0 ;
+static const uint8_t P9N2_PEC_OPCG_REG0_GO = 1 ;
+static const uint8_t P9N2_PEC_OPCG_REG0_RUN_SCAN0 = 2 ;
+static const uint8_t P9N2_PEC_OPCG_REG0_SCAN0_MODE = 3 ;
+static const uint8_t P9N2_PEC_OPCG_REG0_IN_SLAVE_MODE = 4 ;
+static const uint8_t P9N2_PEC_OPCG_REG0_IN_MASTER_MODE = 5 ;
+static const uint8_t P9N2_PEC_OPCG_REG0_KEEP_MS_MODE = 6 ;
+static const uint8_t P9N2_PEC_OPCG_REG0_TRIGGER_ON_UNIT0_SYNC_LVL = 7 ;
+static const uint8_t P9N2_PEC_OPCG_REG0_TRIGGER_ON_UNIT1_SYNC_LVL = 8 ;
+static const uint8_t P9N2_PEC_OPCG_REG0_RUN_CHIPLET_SCAN0 = 9 ;
+static const uint8_t P9N2_PEC_OPCG_REG0_RUN_CHIPLET_SCAN0_NO_PLL = 10 ;
+static const uint8_t P9N2_PEC_OPCG_REG0_RUN_ON_UPDATE_DR = 11 ;
+static const uint8_t P9N2_PEC_OPCG_REG0_RUN_ON_CAPTURE_DR = 12 ;
+static const uint8_t P9N2_PEC_OPCG_REG0_STOP_RUNN_ON_XSTOP = 13 ;
+static const uint8_t P9N2_PEC_OPCG_REG0_STARTS_BIST = 14 ;
+static const uint8_t P9N2_PEC_OPCG_REG0_UNUSED1520 = 15 ;
+static const uint8_t P9N2_PEC_OPCG_REG0_UNUSED1520_LEN = 6 ;
+static const uint8_t P9N2_PEC_OPCG_REG0_LOOP_COUNT = 21 ;
+static const uint8_t P9N2_PEC_OPCG_REG0_LOOP_COUNT_LEN = 43 ;
+
+static const uint8_t P9N2_PEC_OPCG_REG1_SCAN_COUNT = 0 ;
+static const uint8_t P9N2_PEC_OPCG_REG1_SCAN_COUNT_LEN = 12 ;
+static const uint8_t P9N2_PEC_OPCG_REG1_MISR_A_VAL = 12 ;
+static const uint8_t P9N2_PEC_OPCG_REG1_MISR_A_VAL_LEN = 12 ;
+static const uint8_t P9N2_PEC_OPCG_REG1_MISR_B_VAL = 24 ;
+static const uint8_t P9N2_PEC_OPCG_REG1_MISR_B_VAL_LEN = 12 ;
+static const uint8_t P9N2_PEC_OPCG_REG1_MISR_INIT_WAIT = 36 ;
+static const uint8_t P9N2_PEC_OPCG_REG1_MISR_INIT_WAIT_LEN = 12 ;
+static const uint8_t P9N2_PEC_OPCG_REG1_SUPPRESS_LAST_RUNN_CLK = 48 ;
+static const uint8_t P9N2_PEC_OPCG_REG1_SCAN_CLK_USE_EVEN = 49 ;
+static const uint8_t P9N2_PEC_OPCG_REG1_UNUSED2 = 50 ;
+static const uint8_t P9N2_PEC_OPCG_REG1_UNUSED2_LEN = 2 ;
+static const uint8_t P9N2_PEC_OPCG_REG1_RTIM_THOLD_FORCE = 52 ;
+static const uint8_t P9N2_PEC_OPCG_REG1_DISABLE_ARY_CLK_DURING_FILL = 53 ;
+static const uint8_t P9N2_PEC_OPCG_REG1_SG_HIGH_DURING_FILL = 54 ;
+static const uint8_t P9N2_PEC_OPCG_REG1_LBIST_SKITTER_CTL = 55 ;
+static const uint8_t P9N2_PEC_OPCG_REG1_LBIST_SKITTER_CTL_LEN = 2 ;
+static const uint8_t P9N2_PEC_OPCG_REG1_MISR_MODE = 57 ;
+static const uint8_t P9N2_PEC_OPCG_REG1_INFINITE_MODE = 58 ;
+static const uint8_t P9N2_PEC_OPCG_REG1_NSL_FILL_COUNT = 59 ;
+static const uint8_t P9N2_PEC_OPCG_REG1_NSL_FILL_COUNT_LEN = 5 ;
+
+static const uint8_t P9N2_PEC_OPCG_REG2_GO2 = 0 ;
+static const uint8_t P9N2_PEC_OPCG_REG2_PRPG_WEIGHTING = 1 ;
+static const uint8_t P9N2_PEC_OPCG_REG2_PRPG_WEIGHTING_LEN = 3 ;
+static const uint8_t P9N2_PEC_OPCG_REG2_PRPG_VALUE = 4 ;
+static const uint8_t P9N2_PEC_OPCG_REG2_PRPG_VALUE_LEN = 12 ;
+static const uint8_t P9N2_PEC_OPCG_REG2_PRPG_A_VAL = 16 ;
+static const uint8_t P9N2_PEC_OPCG_REG2_PRPG_A_VAL_LEN = 12 ;
+static const uint8_t P9N2_PEC_OPCG_REG2_PRPG_B_VAL = 28 ;
+static const uint8_t P9N2_PEC_OPCG_REG2_PRPG_B_VAL_LEN = 12 ;
+static const uint8_t P9N2_PEC_OPCG_REG2_PRPG_MODE = 40 ;
+static const uint8_t P9N2_PEC_OPCG_REG2_UNUSED41_63 = 41 ;
+static const uint8_t P9N2_PEC_OPCG_REG2_UNUSED41_63_LEN = 23 ;
+
+static const uint8_t P9N2__CTL_OPTICAL_IO_CONFIG_NDLMUX_BRK0TO2 = 0 ;
+static const uint8_t P9N2__CTL_OPTICAL_IO_CONFIG_NDLMUX_BRK0TO2_LEN = 3 ;
+static const uint8_t P9N2__CTL_OPTICAL_IO_CONFIG_OCMUX_BRK0TO1 = 3 ;
+static const uint8_t P9N2__CTL_OPTICAL_IO_CONFIG_OCMUX_BRK0TO1_LEN = 2 ;
+static const uint8_t P9N2__CTL_OPTICAL_IO_CONFIG_OCMUX_BRK4TO5 = 5 ;
+static const uint8_t P9N2__CTL_OPTICAL_IO_CONFIG_OCMUX_BRK4TO5_LEN = 2 ;
+
+static const uint8_t P9N2_PU_NPU_CTL_OTL_REM0_CRD_TL_OVF_VC0 = 0 ;
+static const uint8_t P9N2_PU_NPU_CTL_OTL_REM0_CRD_TL_OVF_VC1 = 1 ;
+static const uint8_t P9N2_PU_NPU_CTL_OTL_REM0_CRD_TL_OVF_VC2 = 2 ;
+static const uint8_t P9N2_PU_NPU_CTL_OTL_REM0_CRD_TL_OVF_RSVD3 = 3 ;
+static const uint8_t P9N2_PU_NPU_CTL_OTL_REM0_CRD_TL_OVF_DCP0 = 4 ;
+static const uint8_t P9N2_PU_NPU_CTL_OTL_REM0_CRD_TL_OVF_DCP1 = 5 ;
+static const uint8_t P9N2_PU_NPU_CTL_OTL_REM0_CRD_TL_OVF_RSVD6 = 6 ;
+static const uint8_t P9N2_PU_NPU_CTL_OTL_REM0_CRD_TL_OVF_RSVD7 = 7 ;
+
+static const uint8_t P9N2_PU_NPU_SM2_OTL_REM0_CRD_TL_OVF_VC0 = 0 ;
+static const uint8_t P9N2_PU_NPU_SM2_OTL_REM0_CRD_TL_OVF_VC1 = 1 ;
+static const uint8_t P9N2_PU_NPU_SM2_OTL_REM0_CRD_TL_OVF_VC2 = 2 ;
+static const uint8_t P9N2_PU_NPU_SM2_OTL_REM0_CRD_TL_OVF_RSVD3 = 3 ;
+static const uint8_t P9N2_PU_NPU_SM2_OTL_REM0_CRD_TL_OVF_DCP0 = 4 ;
+static const uint8_t P9N2_PU_NPU_SM2_OTL_REM0_CRD_TL_OVF_DCP1 = 5 ;
+static const uint8_t P9N2_PU_NPU_SM2_OTL_REM0_CRD_TL_OVF_RSVD6 = 6 ;
+static const uint8_t P9N2_PU_NPU_SM2_OTL_REM0_CRD_TL_OVF_RSVD7 = 7 ;
+
+static const uint8_t P9N2__CTL_OTL_REM0_CRD_TL_OVF_VC0 = 0 ;
+static const uint8_t P9N2__CTL_OTL_REM0_CRD_TL_OVF_VC1 = 1 ;
+static const uint8_t P9N2__CTL_OTL_REM0_CRD_TL_OVF_VC2 = 2 ;
+static const uint8_t P9N2__CTL_OTL_REM0_CRD_TL_OVF_RSVD3 = 3 ;
+static const uint8_t P9N2__CTL_OTL_REM0_CRD_TL_OVF_DCP0 = 4 ;
+static const uint8_t P9N2__CTL_OTL_REM0_CRD_TL_OVF_DCP1 = 5 ;
+static const uint8_t P9N2__CTL_OTL_REM0_CRD_TL_OVF_RSVD6 = 6 ;
+static const uint8_t P9N2__CTL_OTL_REM0_CRD_TL_OVF_RSVD7 = 7 ;
+
+static const uint8_t P9N2__SM2_OTL_REM0_CRD_TL_OVF_VC0 = 0 ;
+static const uint8_t P9N2__SM2_OTL_REM0_CRD_TL_OVF_VC1 = 1 ;
+static const uint8_t P9N2__SM2_OTL_REM0_CRD_TL_OVF_VC2 = 2 ;
+static const uint8_t P9N2__SM2_OTL_REM0_CRD_TL_OVF_RSVD3 = 3 ;
+static const uint8_t P9N2__SM2_OTL_REM0_CRD_TL_OVF_DCP0 = 4 ;
+static const uint8_t P9N2__SM2_OTL_REM0_CRD_TL_OVF_DCP1 = 5 ;
+static const uint8_t P9N2__SM2_OTL_REM0_CRD_TL_OVF_RSVD6 = 6 ;
+static const uint8_t P9N2__SM2_OTL_REM0_CRD_TL_OVF_RSVD7 = 7 ;
+
+static const uint8_t P9N2_PU_NPU2_NTL0_PA0_CONFIG_MEMSELMATCH = 0 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_PA0_CONFIG_MEMSELMATCH_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_PA0_CONFIG_GRANULE = 3 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_PA0_CONFIG_SIZE = 4 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_PA0_CONFIG_SIZE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_PA0_CONFIG_MODE = 8 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_PA0_CONFIG_MODE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_PA0_CONFIG_RESERVED = 12 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_PA0_CONFIG_MASK = 13 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_PA0_CONFIG_MASK_LEN = 7 ;
+
+static const uint8_t P9N2_NV_PA0_CONFIG_MEMSELMATCH = 0 ;
+static const uint8_t P9N2_NV_PA0_CONFIG_MEMSELMATCH_LEN = 3 ;
+static const uint8_t P9N2_NV_PA0_CONFIG_GRANULE = 3 ;
+static const uint8_t P9N2_NV_PA0_CONFIG_SIZE = 4 ;
+static const uint8_t P9N2_NV_PA0_CONFIG_SIZE_LEN = 4 ;
+static const uint8_t P9N2_NV_PA0_CONFIG_MODE = 8 ;
+static const uint8_t P9N2_NV_PA0_CONFIG_MODE_LEN = 4 ;
+static const uint8_t P9N2_NV_PA0_CONFIG_RESERVED = 12 ;
+static const uint8_t P9N2_NV_PA0_CONFIG_MASK = 13 ;
+static const uint8_t P9N2_NV_PA0_CONFIG_MASK_LEN = 7 ;
+
+static const uint8_t P9N2_PU_NPU2_NTL0_PA1_CONFIG_MEMSELMATCH = 0 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_PA1_CONFIG_MEMSELMATCH_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_PA1_CONFIG_GRANULE = 3 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_PA1_CONFIG_SIZE = 4 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_PA1_CONFIG_SIZE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_PA1_CONFIG_MODE = 8 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_PA1_CONFIG_MODE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_PA1_CONFIG_RESERVED = 12 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_PA1_CONFIG_MASK = 13 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_PA1_CONFIG_MASK_LEN = 7 ;
+
+static const uint8_t P9N2_NV_PA1_CONFIG_MEMSELMATCH = 0 ;
+static const uint8_t P9N2_NV_PA1_CONFIG_MEMSELMATCH_LEN = 3 ;
+static const uint8_t P9N2_NV_PA1_CONFIG_GRANULE = 3 ;
+static const uint8_t P9N2_NV_PA1_CONFIG_SIZE = 4 ;
+static const uint8_t P9N2_NV_PA1_CONFIG_SIZE_LEN = 4 ;
+static const uint8_t P9N2_NV_PA1_CONFIG_MODE = 8 ;
+static const uint8_t P9N2_NV_PA1_CONFIG_MODE_LEN = 4 ;
+static const uint8_t P9N2_NV_PA1_CONFIG_RESERVED = 12 ;
+static const uint8_t P9N2_NV_PA1_CONFIG_MASK = 13 ;
+static const uint8_t P9N2_NV_PA1_CONFIG_MASK_LEN = 7 ;
+
+static const uint8_t P9N2_PU_PBABAR0_CMD_SCOPE = 0 ;
+static const uint8_t P9N2_PU_PBABAR0_CMD_SCOPE_LEN = 3 ;
+static const uint8_t P9N2_PU_PBABAR0_RESERVED_3 = 3 ;
+static const uint8_t P9N2_PU_PBABAR0_ADDR = 8 ;
+static const uint8_t P9N2_PU_PBABAR0_ADDR_LEN = 36 ;
+static const uint8_t P9N2_PU_PBABAR0_VTARGET = 48 ;
+static const uint8_t P9N2_PU_PBABAR0_VTARGET_LEN = 16 ;
+
+static const uint8_t P9N2_PU_PBABAR1_CMD_SCOPE = 0 ;
+static const uint8_t P9N2_PU_PBABAR1_CMD_SCOPE_LEN = 3 ;
+static const uint8_t P9N2_PU_PBABAR1_RESERVED_3 = 3 ;
+static const uint8_t P9N2_PU_PBABAR1_ADDR = 8 ;
+static const uint8_t P9N2_PU_PBABAR1_ADDR_LEN = 36 ;
+static const uint8_t P9N2_PU_PBABAR1_VTARGET = 48 ;
+static const uint8_t P9N2_PU_PBABAR1_VTARGET_LEN = 16 ;
+
+static const uint8_t P9N2_PU_PBABAR2_CMD_SCOPE = 0 ;
+static const uint8_t P9N2_PU_PBABAR2_CMD_SCOPE_LEN = 3 ;
+static const uint8_t P9N2_PU_PBABAR2_RESERVED_3 = 3 ;
+static const uint8_t P9N2_PU_PBABAR2_ADDR = 8 ;
+static const uint8_t P9N2_PU_PBABAR2_ADDR_LEN = 36 ;
+static const uint8_t P9N2_PU_PBABAR2_VTARGET = 48 ;
+static const uint8_t P9N2_PU_PBABAR2_VTARGET_LEN = 16 ;
+
+static const uint8_t P9N2_PU_PBABAR3_CMD_SCOPE = 0 ;
+static const uint8_t P9N2_PU_PBABAR3_CMD_SCOPE_LEN = 3 ;
+static const uint8_t P9N2_PU_PBABAR3_RESERVED_3 = 3 ;
+static const uint8_t P9N2_PU_PBABAR3_ADDR = 8 ;
+static const uint8_t P9N2_PU_PBABAR3_ADDR_LEN = 36 ;
+static const uint8_t P9N2_PU_PBABAR3_VTARGET = 48 ;
+static const uint8_t P9N2_PU_PBABAR3_VTARGET_LEN = 16 ;
+
+static const uint8_t P9N2_PU_PBABARMSK0_MSK = 23 ;
+static const uint8_t P9N2_PU_PBABARMSK0_MSK_LEN = 21 ;
+
+static const uint8_t P9N2_PU_PBABARMSK1_MSK = 23 ;
+static const uint8_t P9N2_PU_PBABARMSK1_MSK_LEN = 21 ;
+
+static const uint8_t P9N2_PU_PBABARMSK2_MSK = 23 ;
+static const uint8_t P9N2_PU_PBABARMSK2_MSK_LEN = 21 ;
+
+static const uint8_t P9N2_PU_PBABARMSK3_MSK = 23 ;
+static const uint8_t P9N2_PU_PBABARMSK3_MSK_LEN = 21 ;
+
+static const uint8_t P9N2_PU_PBACFG_PBREQ_SLVFW_MAX_PRIORITY = 0 ;
+static const uint8_t P9N2_PU_PBACFG_PBREQ_EXIT_ON_HANG = 1 ;
+static const uint8_t P9N2_PU_PBACFG_PBREQ_BCE_MAX_PRIORITY = 2 ;
+static const uint8_t P9N2_PU_PBACFG_PBREQ_EXIT_ON_HANG_PBAX = 3 ;
+static const uint8_t P9N2_PU_PBACFG_PBREQ_DATA_HANG_DIV = 4 ;
+static const uint8_t P9N2_PU_PBACFG_PBREQ_DATA_HANG_DIV_LEN = 5 ;
+static const uint8_t P9N2_PU_PBACFG_PBREQ_OPER_HANG_DIV = 9 ;
+static const uint8_t P9N2_PU_PBACFG_PBREQ_OPER_HANG_DIV_LEN = 5 ;
+static const uint8_t P9N2_PU_PBACFG_PBREQ_DROP_PRIORITY_MASK = 14 ;
+static const uint8_t P9N2_PU_PBACFG_PBREQ_DROP_PRIORITY_MASK_LEN = 6 ;
+static const uint8_t P9N2_PU_PBACFG_PBREQ_EXIT_HANG_DIV = 20 ;
+static const uint8_t P9N2_PU_PBACFG_PBREQ_EXIT_HANG_DIV_LEN = 4 ;
+static const uint8_t P9N2_PU_PBACFG_CHSW_HANG_ON_ADRERROR = 24 ;
+static const uint8_t P9N2_PU_PBACFG_CHSW_DIS_OCIABUSPAR_CHECK = 25 ;
+static const uint8_t P9N2_PU_PBACFG_CHSW_DIS_OCIBEPAR_CHECK = 26 ;
+static const uint8_t P9N2_PU_PBACFG_CHSW_HANG_ON_DERROR = 27 ;
+static const uint8_t P9N2_PU_PBACFG_RESERVED_28 = 28 ;
+static const uint8_t P9N2_PU_PBACFG_CHSW_DIS_WRITE_MATCH_REARB = 29 ;
+static const uint8_t P9N2_PU_PBACFG_CHSW_DIS_OCIDATAPAR_GEN = 30 ;
+static const uint8_t P9N2_PU_PBACFG_CHSW_DIS_OCIDATAPAR_CHECK = 31 ;
+static const uint8_t P9N2_PU_PBACFG_CHSW_DIS_OPER_HANG = 32 ;
+static const uint8_t P9N2_PU_PBACFG_CHSW_DIS_DATA_HANG = 33 ;
+static const uint8_t P9N2_PU_PBACFG_CHSW_DIS_ECC_CHECK = 34 ;
+static const uint8_t P9N2_PU_PBACFG_CHSW_DIS_RETRY_BACKOFF = 35 ;
+static const uint8_t P9N2_PU_PBACFG_CHSW_EXIT_ON_INVALID_CRESP = 36 ;
+static const uint8_t P9N2_PU_PBACFG_RESERVED_37 = 37 ;
+static const uint8_t P9N2_PU_PBACFG_CHSW_DIS_GROUP_SCOPE = 38 ;
+static const uint8_t P9N2_PU_PBACFG_CHSW_DIS_RTAG_PARITY_CHK = 39 ;
+static const uint8_t P9N2_PU_PBACFG_CHSW_DIS_PB_PARITY_CHK = 40 ;
+static const uint8_t P9N2_PU_PBACFG_CHSW_SKIP_GROUP_SCOPE = 41 ;
+static const uint8_t P9N2_PU_PBACFG_CHSW_USE_PR_DMA_INJ = 42 ;
+static const uint8_t P9N2_PU_PBACFG_CHSW_USE_CL_DMA_INJ = 43 ;
+static const uint8_t P9N2_PU_PBACFG_RESERVED_44_47 = 44 ;
+static const uint8_t P9N2_PU_PBACFG_RESERVED_44_47_LEN = 4 ;
+
+static const uint8_t P9N2_PU_PBAERRRPT0_CERR_PB_RDDATATO_FW = 0 ;
+static const uint8_t P9N2_PU_PBAERRRPT0_CERR_PB_RDDATATO_FW_LEN = 6 ;
+static const uint8_t P9N2_PU_PBAERRRPT0_CERR_PB_RDADRERR_FW = 6 ;
+static const uint8_t P9N2_PU_PBAERRRPT0_CERR_PB_RDADRERR_FW_LEN = 6 ;
+static const uint8_t P9N2_PU_PBAERRRPT0_CERR_PB_WRADRERR_FW = 12 ;
+static const uint8_t P9N2_PU_PBAERRRPT0_CERR_PB_WRADRERR_FW_LEN = 4 ;
+static const uint8_t P9N2_PU_PBAERRRPT0_CERR_PB_ACKDEAD_FW_RD = 16 ;
+static const uint8_t P9N2_PU_PBAERRRPT0_CERR_PB_ACKDEAD_FW_RD_LEN = 6 ;
+static const uint8_t P9N2_PU_PBAERRRPT0_CERR_PB_ACKDEAD_FW_WR = 22 ;
+static const uint8_t P9N2_PU_PBAERRRPT0_CERR_PB_ACKDEAD_FW_WR_LEN = 2 ;
+static const uint8_t P9N2_PU_PBAERRRPT0_CERR_PB_UNEXPCRESP = 24 ;
+static const uint8_t P9N2_PU_PBAERRRPT0_CERR_PB_UNEXPCRESP_LEN = 11 ;
+static const uint8_t P9N2_PU_PBAERRRPT0_CERR_PB_UNEXPDATA = 35 ;
+static const uint8_t P9N2_PU_PBAERRRPT0_CERR_PB_UNEXPDATA_LEN = 6 ;
+
+static const uint8_t P9N2_PU_PBAERRRPT1_CERR_PB_BADCRESP = 0 ;
+static const uint8_t P9N2_PU_PBAERRRPT1_CERR_PB_BADCRESP_LEN = 12 ;
+static const uint8_t P9N2_PU_PBAERRRPT1_CERR_PB_OPERTO = 12 ;
+static const uint8_t P9N2_PU_PBAERRRPT1_CERR_PB_OPERTO_LEN = 12 ;
+static const uint8_t P9N2_PU_PBAERRRPT1_RESERVED_24_29 = 24 ;
+static const uint8_t P9N2_PU_PBAERRRPT1_RESERVED_24_29_LEN = 6 ;
+static const uint8_t P9N2_PU_PBAERRRPT1_CERR_BCDE_SETUP_ERR = 30 ;
+static const uint8_t P9N2_PU_PBAERRRPT1_CERR_BCDE_SETUP_ERR_LEN = 2 ;
+static const uint8_t P9N2_PU_PBAERRRPT1_CERR_BCUE_SETUP_ERR = 32 ;
+static const uint8_t P9N2_PU_PBAERRRPT1_CERR_BCUE_SETUP_ERR_LEN = 2 ;
+static const uint8_t P9N2_PU_PBAERRRPT1_CERR_BCUE_OCI_DATAERR = 34 ;
+static const uint8_t P9N2_PU_PBAERRRPT1_CERR_BCUE_OCI_DATAERR_LEN = 2 ;
+
+static const uint8_t P9N2_PU_PBAERRRPT2_CERR_SLV_INTERNAL_ERR = 0 ;
+static const uint8_t P9N2_PU_PBAERRRPT2_CERR_SLV_INTERNAL_ERR_LEN = 8 ;
+static const uint8_t P9N2_PU_PBAERRRPT2_CERR_BCDE_INTERNAL_ERR = 8 ;
+static const uint8_t P9N2_PU_PBAERRRPT2_CERR_BCDE_INTERNAL_ERR_LEN = 4 ;
+static const uint8_t P9N2_PU_PBAERRRPT2_CERR_BCUE_INTERNAL_ERR = 12 ;
+static const uint8_t P9N2_PU_PBAERRRPT2_CERR_BCUE_INTERNAL_ERR_LEN = 4 ;
+static const uint8_t P9N2_PU_PBAERRRPT2_CERR_BAR_PARITY_ERR = 16 ;
+static const uint8_t P9N2_PU_PBAERRRPT2_CERR_SCOMTB_ERR = 17 ;
+static const uint8_t P9N2_PU_PBAERRRPT2_CERR_SPARE = 18 ;
+static const uint8_t P9N2_PU_PBAERRRPT2_CERR_SPARE_LEN = 2 ;
+static const uint8_t P9N2_PU_PBAERRRPT2_CERR_PBDOUT_PARITY_ERR = 20 ;
+static const uint8_t P9N2_PU_PBAERRRPT2_CERR_PB_PARITY_ERR = 21 ;
+static const uint8_t P9N2_PU_PBAERRRPT2_CERR_PB_PARITY_ERR_LEN = 3 ;
+static const uint8_t P9N2_PU_PBAERRRPT2_CERR_AXFLOW_ERR = 24 ;
+static const uint8_t P9N2_PU_PBAERRRPT2_CERR_AXFLOW_ERR_LEN = 5 ;
+static const uint8_t P9N2_PU_PBAERRRPT2_CERR_AXPUSH_WRERR = 29 ;
+static const uint8_t P9N2_PU_PBAERRRPT2_CERR_AXPUSH_WRERR_LEN = 2 ;
+
+static const uint8_t P9N2_PU_PBAFIR_OCI_APAR_ERR = 0 ;
+static const uint8_t P9N2_PU_PBAFIR_PB_RDADRERR_FW = 1 ;
+static const uint8_t P9N2_PU_PBAFIR_PB_RDDATATO_FW = 2 ;
+static const uint8_t P9N2_PU_PBAFIR_PB_SUE_FW = 3 ;
+static const uint8_t P9N2_PU_PBAFIR_PB_UE_FW = 4 ;
+static const uint8_t P9N2_PU_PBAFIR_PB_CE_FW = 5 ;
+static const uint8_t P9N2_PU_PBAFIR_OCI_SLAVE_INIT = 6 ;
+static const uint8_t P9N2_PU_PBAFIR_OCI_WRPAR_ERR = 7 ;
+static const uint8_t P9N2_PU_PBAFIR_RESERVED_8 = 8 ;
+static const uint8_t P9N2_PU_PBAFIR_PB_UNEXPCRESP = 9 ;
+static const uint8_t P9N2_PU_PBAFIR_PB_UNEXPDATA = 10 ;
+static const uint8_t P9N2_PU_PBAFIR_PB_PARITY_ERR = 11 ;
+static const uint8_t P9N2_PU_PBAFIR_PB_WRADRERR_FW = 12 ;
+static const uint8_t P9N2_PU_PBAFIR_PB_BADCRESP = 13 ;
+static const uint8_t P9N2_PU_PBAFIR_PB_ACKDEAD_FW_RD = 14 ;
+static const uint8_t P9N2_PU_PBAFIR_PB_OPERTO = 15 ;
+static const uint8_t P9N2_PU_PBAFIR_BCUE_SETUP_ERR = 16 ;
+static const uint8_t P9N2_PU_PBAFIR_BCUE_PB_ACK_DEAD = 17 ;
+static const uint8_t P9N2_PU_PBAFIR_BCUE_PB_ADRERR = 18 ;
+static const uint8_t P9N2_PU_PBAFIR_BCUE_OCI_DATERR = 19 ;
+static const uint8_t P9N2_PU_PBAFIR_BCDE_SETUP_ERR = 20 ;
+static const uint8_t P9N2_PU_PBAFIR_BCDE_PB_ACK_DEAD = 21 ;
+static const uint8_t P9N2_PU_PBAFIR_BCDE_PB_ADRERR = 22 ;
+static const uint8_t P9N2_PU_PBAFIR_BCDE_RDDATATO_ERR = 23 ;
+static const uint8_t P9N2_PU_PBAFIR_BCDE_SUE_ERR = 24 ;
+static const uint8_t P9N2_PU_PBAFIR_BCDE_UE_ERR = 25 ;
+static const uint8_t P9N2_PU_PBAFIR_BCDE_CE = 26 ;
+static const uint8_t P9N2_PU_PBAFIR_BCDE_OCI_DATERR = 27 ;
+static const uint8_t P9N2_PU_PBAFIR_INTERNAL_ERR = 28 ;
+static const uint8_t P9N2_PU_PBAFIR_ILLEGAL_CACHE_OP = 29 ;
+static const uint8_t P9N2_PU_PBAFIR_OCI_BAD_REG_ADDR = 30 ;
+static const uint8_t P9N2_PU_PBAFIR_AXPUSH_WRERR = 31 ;
+static const uint8_t P9N2_PU_PBAFIR_AXRCV_DLO_ERR = 32 ;
+static const uint8_t P9N2_PU_PBAFIR_AXRCV_DLO_TO = 33 ;
+static const uint8_t P9N2_PU_PBAFIR_AXRCV_RSVDATA_TO = 34 ;
+static const uint8_t P9N2_PU_PBAFIR_AXFLOW_ERR = 35 ;
+static const uint8_t P9N2_PU_PBAFIR_AXSND_DHI_RTYTO = 36 ;
+static const uint8_t P9N2_PU_PBAFIR_AXSND_DLO_RTYTO = 37 ;
+static const uint8_t P9N2_PU_PBAFIR_AXSND_RSVTO = 38 ;
+static const uint8_t P9N2_PU_PBAFIR_AXSND_RSVERR = 39 ;
+static const uint8_t P9N2_PU_PBAFIR_PB_ACKDEAD_FW_WR = 40 ;
+static const uint8_t P9N2_PU_PBAFIR_RESERVED_41 = 41 ;
+static const uint8_t P9N2_PU_PBAFIR_RESERVED_42 = 42 ;
+static const uint8_t P9N2_PU_PBAFIR_RESERVED_43 = 43 ;
+static const uint8_t P9N2_PU_PBAFIR_FIR_PARITY_ERR2 = 44 ;
+static const uint8_t P9N2_PU_PBAFIR_FIR_PARITY_ERR = 45 ;
+
+static const uint8_t P9N2_PU_PBAFIRACT0_FIR_ACTION0 = 0 ;
+static const uint8_t P9N2_PU_PBAFIRACT0_FIR_ACTION0_LEN = 46 ;
+
+static const uint8_t P9N2_PU_PBAFIRACT1_FIR_ACTION1 = 0 ;
+static const uint8_t P9N2_PU_PBAFIRACT1_FIR_ACTION1_LEN = 46 ;
+
+static const uint8_t P9N2_PU_PBAFIRMASK_OCI_APAR_ERR_MASK = 0 ;
+static const uint8_t P9N2_PU_PBAFIRMASK_PB_RDADRERR_FW_MASK = 1 ;
+static const uint8_t P9N2_PU_PBAFIRMASK_PB_RDDATATO_FW_MASK = 2 ;
+static const uint8_t P9N2_PU_PBAFIRMASK_PB_SUE_FW_MASK = 3 ;
+static const uint8_t P9N2_PU_PBAFIRMASK_PB_UE_FW_MASK = 4 ;
+static const uint8_t P9N2_PU_PBAFIRMASK_PB_CE_FW_MASK = 5 ;
+static const uint8_t P9N2_PU_PBAFIRMASK_OCI_SLAVE_INIT_MASK = 6 ;
+static const uint8_t P9N2_PU_PBAFIRMASK_OCI_WRPAR_ERR_MASK = 7 ;
+static const uint8_t P9N2_PU_PBAFIRMASK_RESERVED_8 = 8 ;
+static const uint8_t P9N2_PU_PBAFIRMASK_PB_UNEXPCRESP_MASK = 9 ;
+static const uint8_t P9N2_PU_PBAFIRMASK_PB_UNEXPDATA_MASK = 10 ;
+static const uint8_t P9N2_PU_PBAFIRMASK_PB_PARITY_ERR_MASK = 11 ;
+static const uint8_t P9N2_PU_PBAFIRMASK_PB_WRADRERR_FW_MASK = 12 ;
+static const uint8_t P9N2_PU_PBAFIRMASK_PB_BADCRESP_MASK = 13 ;
+static const uint8_t P9N2_PU_PBAFIRMASK_PB_ACKDEAD_FW_RD_MASK = 14 ;
+static const uint8_t P9N2_PU_PBAFIRMASK_PB_OPERTO_MASK = 15 ;
+static const uint8_t P9N2_PU_PBAFIRMASK_BCUE_SETUP_ERR_MASK = 16 ;
+static const uint8_t P9N2_PU_PBAFIRMASK_BCUE_PB_ACK_DEAD_MASK = 17 ;
+static const uint8_t P9N2_PU_PBAFIRMASK_BCUE_PB_ADRERR_MASK = 18 ;
+static const uint8_t P9N2_PU_PBAFIRMASK_BCUE_OCI_DATERR_MASK = 19 ;
+static const uint8_t P9N2_PU_PBAFIRMASK_BCDE_SETUP_ERR_MASK = 20 ;
+static const uint8_t P9N2_PU_PBAFIRMASK_BCDE_PB_ACK_DEAD_MASK = 21 ;
+static const uint8_t P9N2_PU_PBAFIRMASK_BCDE_PB_ADRERR_MASK = 22 ;
+static const uint8_t P9N2_PU_PBAFIRMASK_BCDE_RDDATATO_ERR_MASK = 23 ;
+static const uint8_t P9N2_PU_PBAFIRMASK_BCDE_SUE_ERR_MASK = 24 ;
+static const uint8_t P9N2_PU_PBAFIRMASK_BCDE_UE_ERR_MASK = 25 ;
+static const uint8_t P9N2_PU_PBAFIRMASK_BCDE_CE_MASK = 26 ;
+static const uint8_t P9N2_PU_PBAFIRMASK_BCDE_OCI_DATERR_MASK = 27 ;
+static const uint8_t P9N2_PU_PBAFIRMASK_INTERNAL_ERR_MASK = 28 ;
+static const uint8_t P9N2_PU_PBAFIRMASK_ILLEGAL_CACHE_OP_MASK = 29 ;
+static const uint8_t P9N2_PU_PBAFIRMASK_OCI_BAD_REG_ADDR_MASK = 30 ;
+static const uint8_t P9N2_PU_PBAFIRMASK_AXPUSH_WRERR_MASK = 31 ;
+static const uint8_t P9N2_PU_PBAFIRMASK_AXRCV_DLO_ERR_MASK = 32 ;
+static const uint8_t P9N2_PU_PBAFIRMASK_AXRCV_DLO_TO_MASK = 33 ;
+static const uint8_t P9N2_PU_PBAFIRMASK_AXRCV_RSVDATA_TO_MASK = 34 ;
+static const uint8_t P9N2_PU_PBAFIRMASK_AXFLOW_ERR_MASK = 35 ;
+static const uint8_t P9N2_PU_PBAFIRMASK_AXSND_DHI_RTYTO_MASK = 36 ;
+static const uint8_t P9N2_PU_PBAFIRMASK_AXSND_DLO_RTYTO_MASK = 37 ;
+static const uint8_t P9N2_PU_PBAFIRMASK_AXSND_RSVTO_MASK = 38 ;
+static const uint8_t P9N2_PU_PBAFIRMASK_AXSND_RSVERR_MASK = 39 ;
+static const uint8_t P9N2_PU_PBAFIRMASK_PB_ACKDEAD_FW_WR_MASK = 40 ;
+static const uint8_t P9N2_PU_PBAFIRMASK_RESERVED_41_43 = 41 ;
+static const uint8_t P9N2_PU_PBAFIRMASK_RESERVED_41_43_LEN = 3 ;
+static const uint8_t P9N2_PU_PBAFIRMASK_FIR_PARITY_ERR2_MASK = 44 ;
+static const uint8_t P9N2_PU_PBAFIRMASK_FIR_PARITY_ERR_MASK = 45 ;
+
+static const uint8_t P9N2_PEC_PBAIBHWCFG_REG_RESERVED0 = 0 ;
+static const uint8_t P9N2_PEC_PBAIBHWCFG_REG_RESERVED0_LEN = 16 ;
+static const uint8_t P9N2_PEC_PBAIBHWCFG_REG_PE_OSMB_DATASTART_MODE = 16 ;
+static const uint8_t P9N2_PEC_PBAIBHWCFG_REG_PE_OSMB_DATASTART_MODE_LEN = 3 ;
+static const uint8_t P9N2_PEC_PBAIBHWCFG_REG_RESERVED1 = 19 ;
+static const uint8_t P9N2_PEC_PBAIBHWCFG_REG_PE_TX_RESP_HWM = 20 ;
+static const uint8_t P9N2_PEC_PBAIBHWCFG_REG_PE_TX_RESP_HWM_LEN = 4 ;
+static const uint8_t P9N2_PEC_PBAIBHWCFG_REG_PE_TX_RESP_LWM = 24 ;
+static const uint8_t P9N2_PEC_PBAIBHWCFG_REG_PE_TX_RESP_LWM_LEN = 4 ;
+static const uint8_t P9N2_PEC_PBAIBHWCFG_REG_PE_OSMB_EARLYEMPTY_MODE = 28 ;
+static const uint8_t P9N2_PEC_PBAIBHWCFG_REG_PE_OSMB_EARLYEMPTY_MODE_LEN = 2 ;
+static const uint8_t P9N2_PEC_PBAIBHWCFG_REG_PE_PCIE_CLK_TRACE_EN = 30 ;
+static const uint8_t P9N2_PEC_PBAIBHWCFG_REG_PE_SELECT_ETU_TRACE = 31 ;
+static const uint8_t P9N2_PEC_PBAIBHWCFG_REG_PE_PCI_CLK_TRACE_SEL = 32 ;
+static const uint8_t P9N2_PEC_PBAIBHWCFG_REG_PE_PCI_CLK_TRACE_SEL_LEN = 4 ;
+static const uint8_t P9N2_PEC_PBAIBHWCFG_REG_PE_ISMB_ERROR_INJECT = 36 ;
+static const uint8_t P9N2_PEC_PBAIBHWCFG_REG_PE_ISMB_ERROR_INJECT_LEN = 3 ;
+static const uint8_t P9N2_PEC_PBAIBHWCFG_REG_RESERVED2 = 39 ;
+static const uint8_t P9N2_PEC_PBAIBHWCFG_REG_PE_OSMB_HOL_BLK_CNT = 40 ;
+static const uint8_t P9N2_PEC_PBAIBHWCFG_REG_PE_OSMB_HOL_BLK_CNT_LEN = 3 ;
+
+static const uint8_t P9N2_PHB_PBAIBTXCCR_REG_PBAIB_TX_CH0_CCA = 0 ;
+static const uint8_t P9N2_PHB_PBAIBTXCCR_REG_PBAIB_TX_CH0_CCA_LEN = 3 ;
+static const uint8_t P9N2_PHB_PBAIBTXCCR_REG_PBAIB_TX_CH0_CCR = 10 ;
+static const uint8_t P9N2_PHB_PBAIBTXCCR_REG_PBAIB_TX_CH0_CCR_LEN = 6 ;
+static const uint8_t P9N2_PHB_PBAIBTXCCR_REG_PBAIB_TX_CH1_CCA = 16 ;
+static const uint8_t P9N2_PHB_PBAIBTXCCR_REG_PBAIB_TX_CH1_CCA_LEN = 3 ;
+static const uint8_t P9N2_PHB_PBAIBTXCCR_REG_PBAIB_TX_CH1_CCR = 26 ;
+static const uint8_t P9N2_PHB_PBAIBTXCCR_REG_PBAIB_TX_CH1_CCR_LEN = 6 ;
+static const uint8_t P9N2_PHB_PBAIBTXCCR_REG_PBAIB_TX_CH2_CCA = 32 ;
+static const uint8_t P9N2_PHB_PBAIBTXCCR_REG_PBAIB_TX_CH2_CCA_LEN = 3 ;
+static const uint8_t P9N2_PHB_PBAIBTXCCR_REG_PBAIB_TX_CH2_CCR = 41 ;
+static const uint8_t P9N2_PHB_PBAIBTXCCR_REG_PBAIB_TX_CH2_CCR_LEN = 7 ;
+static const uint8_t P9N2_PHB_PBAIBTXCCR_REG_PBAIB_TX_CH3_CCA = 48 ;
+static const uint8_t P9N2_PHB_PBAIBTXCCR_REG_PBAIB_TX_CH3_CCA_LEN = 3 ;
+static const uint8_t P9N2_PHB_PBAIBTXCCR_REG_PBAIB_TX_CH3_CCR = 58 ;
+static const uint8_t P9N2_PHB_PBAIBTXCCR_REG_PBAIB_TX_CH3_CCR_LEN = 6 ;
+
+static const uint8_t P9N2_PHB_PBAIBTXDCR_REG_PBAIB_TX_CH0_DCR = 9 ;
+static const uint8_t P9N2_PHB_PBAIBTXDCR_REG_PBAIB_TX_CH0_DCR_LEN = 7 ;
+static const uint8_t P9N2_PHB_PBAIBTXDCR_REG_PBAIB_TX_CH1_DCR = 26 ;
+static const uint8_t P9N2_PHB_PBAIBTXDCR_REG_PBAIB_TX_CH1_DCR_LEN = 6 ;
+static const uint8_t P9N2_PHB_PBAIBTXDCR_REG_PBAIB_TX_CH3_DCR = 58 ;
+static const uint8_t P9N2_PHB_PBAIBTXDCR_REG_PBAIB_TX_CH3_DCR_LEN = 6 ;
+
+static const uint8_t P9N2_PHB_PBAIB_CERR_RPT_REG_PBAIBHWCFG_PE = 0 ;
+static const uint8_t P9N2_PHB_PBAIB_CERR_RPT_REG_PHBRESET_PE = 1 ;
+static const uint8_t P9N2_PHB_PBAIB_CERR_RPT_REG_PBAIBTXCITR_PE = 2 ;
+static const uint8_t P9N2_PHB_PBAIB_CERR_RPT_REG_PBAIBTXCCR_PE = 3 ;
+static const uint8_t P9N2_PHB_PBAIB_CERR_RPT_REG_PBAIBTXDCR_PE = 4 ;
+static const uint8_t P9N2_PHB_PBAIB_CERR_RPT_REG_PEAIB_OVERRUN = 5 ;
+static const uint8_t P9N2_PHB_PBAIB_CERR_RPT_REG_PEAIB_QCNT_ERR = 6 ;
+static const uint8_t P9N2_PHB_PBAIB_CERR_RPT_REG_PEAIB_TX_DAT_ERR = 7 ;
+static const uint8_t P9N2_PHB_PBAIB_CERR_RPT_REG_PEAIB_CMD_PE = 8 ;
+static const uint8_t P9N2_PHB_PBAIB_CERR_RPT_REG_PEAIB_DAT_PE = 9 ;
+static const uint8_t P9N2_PHB_PBAIB_CERR_RPT_REG_PEAIB_CMD_CRD_AVAIL_PE = 10 ;
+static const uint8_t P9N2_PHB_PBAIB_CERR_RPT_REG_PEAIB_DAT_CRD_AVAIL_PE = 11 ;
+static const uint8_t P9N2_PHB_PBAIB_CERR_RPT_REG_PEAIB_CMD_CRD_PE = 12 ;
+static const uint8_t P9N2_PHB_PBAIB_CERR_RPT_REG_PEAIB_DAT_CRD_PE = 13 ;
+static const uint8_t P9N2_PHB_PBAIB_CERR_RPT_REG_PHBRESET_SCOM_ERR = 14 ;
+static const uint8_t P9N2_PHB_PBAIB_CERR_RPT_REG_ASYNC_ERROR = 15 ;
+static const uint8_t P9N2_PHB_PBAIB_CERR_RPT_REG_AIB_STACK_SCOM_ERR = 16 ;
+static const uint8_t P9N2_PHB_PBAIB_CERR_RPT_REG_AIB_PEC_SCOM_ERR = 17 ;
+static const uint8_t P9N2_PHB_PBAIB_CERR_RPT_REG_PBAIB_FENCE_PCIE = 18 ;
+
+static const uint8_t P9N2_PU_PBAMODE_RESERVED_0_3 = 0 ;
+static const uint8_t P9N2_PU_PBAMODE_RESERVED_0_3_LEN = 4 ;
+static const uint8_t P9N2_PU_PBAMODE_DIS_REARB = 4 ;
+static const uint8_t P9N2_PU_PBAMODE_DIS_MSTID_MATCH_PREF_INV = 5 ;
+static const uint8_t P9N2_PU_PBAMODE_DIS_SLAVE_RDPIPE = 6 ;
+static const uint8_t P9N2_PU_PBAMODE_DIS_SLAVE_WRPIPE = 7 ;
+static const uint8_t P9N2_PU_PBAMODE_EN_MARKER_ACK = 8 ;
+static const uint8_t P9N2_PU_PBAMODE_RESERVED_9 = 9 ;
+static const uint8_t P9N2_PU_PBAMODE_EN_SECOND_WRBUF = 10 ;
+static const uint8_t P9N2_PU_PBAMODE_DIS_REREQUEST_TO = 11 ;
+static const uint8_t P9N2_PU_PBAMODE_INJECT_TYPE = 12 ;
+static const uint8_t P9N2_PU_PBAMODE_INJECT_TYPE_LEN = 2 ;
+static const uint8_t P9N2_PU_PBAMODE_INJECT_MODE = 14 ;
+static const uint8_t P9N2_PU_PBAMODE_INJECT_MODE_LEN = 2 ;
+static const uint8_t P9N2_PU_PBAMODE_PBA_REGION = 16 ;
+static const uint8_t P9N2_PU_PBAMODE_PBA_REGION_LEN = 2 ;
+static const uint8_t P9N2_PU_PBAMODE_OCI_MARKER_SPACE = 18 ;
+static const uint8_t P9N2_PU_PBAMODE_OCI_MARKER_SPACE_LEN = 3 ;
+static const uint8_t P9N2_PU_PBAMODE_BCDE_OCITRANS = 21 ;
+static const uint8_t P9N2_PU_PBAMODE_BCDE_OCITRANS_LEN = 2 ;
+static const uint8_t P9N2_PU_PBAMODE_BCUE_OCITRANS = 23 ;
+static const uint8_t P9N2_PU_PBAMODE_BCUE_OCITRANS_LEN = 2 ;
+static const uint8_t P9N2_PU_PBAMODE_DIS_MASTER_RD_PIPE = 25 ;
+static const uint8_t P9N2_PU_PBAMODE_DIS_MASTER_WR_PIPE = 26 ;
+static const uint8_t P9N2_PU_PBAMODE_EN_SLV_FAIRNESS = 27 ;
+static const uint8_t P9N2_PU_PBAMODE_EN_EVENT_COUNT = 28 ;
+static const uint8_t P9N2_PU_PBAMODE_PB_NOCI_EVENT_SEL = 29 ;
+static const uint8_t P9N2_PU_PBAMODE_SLV_EVENT_MUX = 30 ;
+static const uint8_t P9N2_PU_PBAMODE_SLV_EVENT_MUX_LEN = 2 ;
+static const uint8_t P9N2_PU_PBAMODE_ENABLE_DEBUG_BUS = 32 ;
+static const uint8_t P9N2_PU_PBAMODE_DEBUG_PB_NOT_OCI = 33 ;
+static const uint8_t P9N2_PU_PBAMODE_DEBUG_OCI_MODE = 34 ;
+static const uint8_t P9N2_PU_PBAMODE_DEBUG_OCI_MODE_LEN = 5 ;
+static const uint8_t P9N2_PU_PBAMODE_RESERVED_39 = 39 ;
+static const uint8_t P9N2_PU_PBAMODE_OCISLV_FAIRNESS_MASK = 40 ;
+static const uint8_t P9N2_PU_PBAMODE_OCISLV_FAIRNESS_MASK_LEN = 5 ;
+static const uint8_t P9N2_PU_PBAMODE_OCISLV_REREQ_HANG_DIV = 45 ;
+static const uint8_t P9N2_PU_PBAMODE_OCISLV_REREQ_HANG_DIV_LEN = 5 ;
+static const uint8_t P9N2_PU_PBAMODE_DIS_CHGRATE_COUNT = 50 ;
+static const uint8_t P9N2_PU_PBAMODE_PBREQ_EVENT_MUX = 51 ;
+static const uint8_t P9N2_PU_PBAMODE_PBREQ_EVENT_MUX_LEN = 2 ;
+static const uint8_t P9N2_PU_PBAMODE_RESERVED_53_63 = 53 ;
+static const uint8_t P9N2_PU_PBAMODE_RESERVED_53_63_LEN = 11 ;
+
+static const uint8_t P9N2_PU_PBAOCCACT_OCC_ACTION_SET = 0 ;
+static const uint8_t P9N2_PU_PBAOCCACT_OCC_ACTION_SET_LEN = 44 ;
+
+static const uint8_t P9N2_PU_PBAPBOCR0_EVENT = 16 ;
+static const uint8_t P9N2_PU_PBAPBOCR0_EVENT_LEN = 16 ;
+static const uint8_t P9N2_PU_PBAPBOCR0_ACCUM = 44 ;
+static const uint8_t P9N2_PU_PBAPBOCR0_ACCUM_LEN = 20 ;
+
+static const uint8_t P9N2_PU_PBAPBOCR1_EVENT = 16 ;
+static const uint8_t P9N2_PU_PBAPBOCR1_EVENT_LEN = 16 ;
+static const uint8_t P9N2_PU_PBAPBOCR1_ACCUM = 44 ;
+static const uint8_t P9N2_PU_PBAPBOCR1_ACCUM_LEN = 20 ;
+
+static const uint8_t P9N2_PU_PBAPBOCR2_EVENT = 16 ;
+static const uint8_t P9N2_PU_PBAPBOCR2_EVENT_LEN = 16 ;
+static const uint8_t P9N2_PU_PBAPBOCR2_ACCUM = 44 ;
+static const uint8_t P9N2_PU_PBAPBOCR2_ACCUM_LEN = 20 ;
+
+static const uint8_t P9N2_PU_PBAPBOCR3_EVENT = 16 ;
+static const uint8_t P9N2_PU_PBAPBOCR3_EVENT_LEN = 16 ;
+static const uint8_t P9N2_PU_PBAPBOCR3_ACCUM = 44 ;
+static const uint8_t P9N2_PU_PBAPBOCR3_ACCUM_LEN = 20 ;
+
+static const uint8_t P9N2_PU_PBAPBOCR4_EVENT = 16 ;
+static const uint8_t P9N2_PU_PBAPBOCR4_EVENT_LEN = 16 ;
+static const uint8_t P9N2_PU_PBAPBOCR4_ACCUM = 44 ;
+static const uint8_t P9N2_PU_PBAPBOCR4_ACCUM_LEN = 20 ;
+
+static const uint8_t P9N2_PU_PBAPBOCR5_EVENT = 16 ;
+static const uint8_t P9N2_PU_PBAPBOCR5_EVENT_LEN = 16 ;
+static const uint8_t P9N2_PU_PBAPBOCR5_ACCUM = 44 ;
+static const uint8_t P9N2_PU_PBAPBOCR5_ACCUM_LEN = 20 ;
+
+static const uint8_t P9N2_PU_PBARBUFVAL0_RD_SLVNUM = 0 ;
+static const uint8_t P9N2_PU_PBARBUFVAL0_RD_SLVNUM_LEN = 2 ;
+static const uint8_t P9N2_PU_PBARBUFVAL0_CUR_RD_ADDR = 2 ;
+static const uint8_t P9N2_PU_PBARBUFVAL0_CUR_RD_ADDR_LEN = 23 ;
+static const uint8_t P9N2_PU_PBARBUFVAL0_PREFETCH = 28 ;
+static const uint8_t P9N2_PU_PBARBUFVAL0_ABORT = 31 ;
+static const uint8_t P9N2_PU_PBARBUFVAL0_BUFFER_STATUS = 33 ;
+static const uint8_t P9N2_PU_PBARBUFVAL0_BUFFER_STATUS_LEN = 7 ;
+static const uint8_t P9N2_PU_PBARBUFVAL0_MASTERID = 41 ;
+static const uint8_t P9N2_PU_PBARBUFVAL0_MASTERID_LEN = 3 ;
+
+static const uint8_t P9N2_PU_PBARBUFVAL1_RD_SLVNUM = 0 ;
+static const uint8_t P9N2_PU_PBARBUFVAL1_RD_SLVNUM_LEN = 2 ;
+static const uint8_t P9N2_PU_PBARBUFVAL1_CUR_RD_ADDR = 2 ;
+static const uint8_t P9N2_PU_PBARBUFVAL1_CUR_RD_ADDR_LEN = 23 ;
+static const uint8_t P9N2_PU_PBARBUFVAL1_PREFETCH = 28 ;
+static const uint8_t P9N2_PU_PBARBUFVAL1_ABORT = 31 ;
+static const uint8_t P9N2_PU_PBARBUFVAL1_BUFFER_STATUS = 33 ;
+static const uint8_t P9N2_PU_PBARBUFVAL1_BUFFER_STATUS_LEN = 7 ;
+static const uint8_t P9N2_PU_PBARBUFVAL1_MASTERID = 41 ;
+static const uint8_t P9N2_PU_PBARBUFVAL1_MASTERID_LEN = 3 ;
+
+static const uint8_t P9N2_PU_PBARBUFVAL2_RD_SLVNUM = 0 ;
+static const uint8_t P9N2_PU_PBARBUFVAL2_RD_SLVNUM_LEN = 2 ;
+static const uint8_t P9N2_PU_PBARBUFVAL2_CUR_RD_ADDR = 2 ;
+static const uint8_t P9N2_PU_PBARBUFVAL2_CUR_RD_ADDR_LEN = 23 ;
+static const uint8_t P9N2_PU_PBARBUFVAL2_PREFETCH = 28 ;
+static const uint8_t P9N2_PU_PBARBUFVAL2_ABORT = 31 ;
+static const uint8_t P9N2_PU_PBARBUFVAL2_BUFFER_STATUS = 33 ;
+static const uint8_t P9N2_PU_PBARBUFVAL2_BUFFER_STATUS_LEN = 7 ;
+static const uint8_t P9N2_PU_PBARBUFVAL2_MASTERID = 41 ;
+static const uint8_t P9N2_PU_PBARBUFVAL2_MASTERID_LEN = 3 ;
+
+static const uint8_t P9N2_PU_PBARBUFVAL3_RD_SLVNUM = 0 ;
+static const uint8_t P9N2_PU_PBARBUFVAL3_RD_SLVNUM_LEN = 2 ;
+static const uint8_t P9N2_PU_PBARBUFVAL3_CUR_RD_ADDR = 2 ;
+static const uint8_t P9N2_PU_PBARBUFVAL3_CUR_RD_ADDR_LEN = 23 ;
+static const uint8_t P9N2_PU_PBARBUFVAL3_PREFETCH = 28 ;
+static const uint8_t P9N2_PU_PBARBUFVAL3_ABORT = 31 ;
+static const uint8_t P9N2_PU_PBARBUFVAL3_BUFFER_STATUS = 33 ;
+static const uint8_t P9N2_PU_PBARBUFVAL3_BUFFER_STATUS_LEN = 7 ;
+static const uint8_t P9N2_PU_PBARBUFVAL3_MASTERID = 41 ;
+static const uint8_t P9N2_PU_PBARBUFVAL3_MASTERID_LEN = 3 ;
+
+static const uint8_t P9N2_PU_PBARBUFVAL4_RD_SLVNUM = 0 ;
+static const uint8_t P9N2_PU_PBARBUFVAL4_RD_SLVNUM_LEN = 2 ;
+static const uint8_t P9N2_PU_PBARBUFVAL4_CUR_RD_ADDR = 2 ;
+static const uint8_t P9N2_PU_PBARBUFVAL4_CUR_RD_ADDR_LEN = 23 ;
+static const uint8_t P9N2_PU_PBARBUFVAL4_PREFETCH = 28 ;
+static const uint8_t P9N2_PU_PBARBUFVAL4_ABORT = 31 ;
+static const uint8_t P9N2_PU_PBARBUFVAL4_BUFFER_STATUS = 33 ;
+static const uint8_t P9N2_PU_PBARBUFVAL4_BUFFER_STATUS_LEN = 7 ;
+static const uint8_t P9N2_PU_PBARBUFVAL4_MASTERID = 41 ;
+static const uint8_t P9N2_PU_PBARBUFVAL4_MASTERID_LEN = 3 ;
+
+static const uint8_t P9N2_PU_PBARBUFVAL5_RD_SLVNUM = 0 ;
+static const uint8_t P9N2_PU_PBARBUFVAL5_RD_SLVNUM_LEN = 2 ;
+static const uint8_t P9N2_PU_PBARBUFVAL5_CUR_RD_ADDR = 2 ;
+static const uint8_t P9N2_PU_PBARBUFVAL5_CUR_RD_ADDR_LEN = 23 ;
+static const uint8_t P9N2_PU_PBARBUFVAL5_PREFETCH = 28 ;
+static const uint8_t P9N2_PU_PBARBUFVAL5_ABORT = 31 ;
+static const uint8_t P9N2_PU_PBARBUFVAL5_BUFFER_STATUS = 33 ;
+static const uint8_t P9N2_PU_PBARBUFVAL5_BUFFER_STATUS_LEN = 7 ;
+static const uint8_t P9N2_PU_PBARBUFVAL5_MASTERID = 41 ;
+static const uint8_t P9N2_PU_PBARBUFVAL5_MASTERID_LEN = 3 ;
+
+static const uint8_t P9N2_PU_PBASLVCTL0_ENABLE = 0 ;
+static const uint8_t P9N2_PU_PBASLVCTL0_MID_MATCH_VALUE = 1 ;
+static const uint8_t P9N2_PU_PBASLVCTL0_MID_MATCH_VALUE_LEN = 3 ;
+static const uint8_t P9N2_PU_PBASLVCTL0_RESERVED_4 = 4 ;
+static const uint8_t P9N2_PU_PBASLVCTL0_MID_CARE_MASK = 5 ;
+static const uint8_t P9N2_PU_PBASLVCTL0_MID_CARE_MASK_LEN = 3 ;
+static const uint8_t P9N2_PU_PBASLVCTL0_WRITE_TTYPE = 8 ;
+static const uint8_t P9N2_PU_PBASLVCTL0_WRITE_TTYPE_LEN = 3 ;
+static const uint8_t P9N2_PU_PBASLVCTL0_RESERVED_11_14 = 11 ;
+static const uint8_t P9N2_PU_PBASLVCTL0_RESERVED_11_14_LEN = 4 ;
+static const uint8_t P9N2_PU_PBASLVCTL0_READ_TTYPE = 15 ;
+static const uint8_t P9N2_PU_PBASLVCTL0_READ_PREFETCH_CTL = 16 ;
+static const uint8_t P9N2_PU_PBASLVCTL0_READ_PREFETCH_CTL_LEN = 2 ;
+static const uint8_t P9N2_PU_PBASLVCTL0_BUF_INVALIDATE_CTL = 18 ;
+static const uint8_t P9N2_PU_PBASLVCTL0_BUF_ALLOC_W = 19 ;
+static const uint8_t P9N2_PU_PBASLVCTL0_BUF_ALLOC_A = 20 ;
+static const uint8_t P9N2_PU_PBASLVCTL0_BUF_ALLOC_B = 21 ;
+static const uint8_t P9N2_PU_PBASLVCTL0_BUF_ALLOC_C = 22 ;
+static const uint8_t P9N2_PU_PBASLVCTL0_RESERVED_23 = 23 ;
+static const uint8_t P9N2_PU_PBASLVCTL0_DIS_WRITE_GATHER = 24 ;
+static const uint8_t P9N2_PU_PBASLVCTL0_WR_GATHER_TIMEOUT = 25 ;
+static const uint8_t P9N2_PU_PBASLVCTL0_WR_GATHER_TIMEOUT_LEN = 3 ;
+static const uint8_t P9N2_PU_PBASLVCTL0_WRITE_TSIZE = 28 ;
+static const uint8_t P9N2_PU_PBASLVCTL0_WRITE_TSIZE_LEN = 8 ;
+static const uint8_t P9N2_PU_PBASLVCTL0_EXTADDR = 36 ;
+static const uint8_t P9N2_PU_PBASLVCTL0_EXTADDR_LEN = 14 ;
+static const uint8_t P9N2_PU_PBASLVCTL0_RESERVED_50 = 50 ;
+
+static const uint8_t P9N2_PU_PBASLVCTL1_ENABLE = 0 ;
+static const uint8_t P9N2_PU_PBASLVCTL1_MID_MATCH_VALUE = 1 ;
+static const uint8_t P9N2_PU_PBASLVCTL1_MID_MATCH_VALUE_LEN = 3 ;
+static const uint8_t P9N2_PU_PBASLVCTL1_RESERVED_4 = 4 ;
+static const uint8_t P9N2_PU_PBASLVCTL1_MID_CARE_MASK = 5 ;
+static const uint8_t P9N2_PU_PBASLVCTL1_MID_CARE_MASK_LEN = 3 ;
+static const uint8_t P9N2_PU_PBASLVCTL1_WRITE_TTYPE = 8 ;
+static const uint8_t P9N2_PU_PBASLVCTL1_WRITE_TTYPE_LEN = 3 ;
+static const uint8_t P9N2_PU_PBASLVCTL1_RESERVED_11_14 = 11 ;
+static const uint8_t P9N2_PU_PBASLVCTL1_RESERVED_11_14_LEN = 4 ;
+static const uint8_t P9N2_PU_PBASLVCTL1_READ_TTYPE = 15 ;
+static const uint8_t P9N2_PU_PBASLVCTL1_READ_PREFETCH_CTL = 16 ;
+static const uint8_t P9N2_PU_PBASLVCTL1_READ_PREFETCH_CTL_LEN = 2 ;
+static const uint8_t P9N2_PU_PBASLVCTL1_BUF_INVALIDATE_CTL = 18 ;
+static const uint8_t P9N2_PU_PBASLVCTL1_BUF_ALLOC_W = 19 ;
+static const uint8_t P9N2_PU_PBASLVCTL1_BUF_ALLOC_A = 20 ;
+static const uint8_t P9N2_PU_PBASLVCTL1_BUF_ALLOC_B = 21 ;
+static const uint8_t P9N2_PU_PBASLVCTL1_BUF_ALLOC_C = 22 ;
+static const uint8_t P9N2_PU_PBASLVCTL1_RESERVED_23 = 23 ;
+static const uint8_t P9N2_PU_PBASLVCTL1_DIS_WRITE_GATHER = 24 ;
+static const uint8_t P9N2_PU_PBASLVCTL1_WR_GATHER_TIMEOUT = 25 ;
+static const uint8_t P9N2_PU_PBASLVCTL1_WR_GATHER_TIMEOUT_LEN = 3 ;
+static const uint8_t P9N2_PU_PBASLVCTL1_WRITE_TSIZE = 28 ;
+static const uint8_t P9N2_PU_PBASLVCTL1_WRITE_TSIZE_LEN = 8 ;
+static const uint8_t P9N2_PU_PBASLVCTL1_EXTADDR = 36 ;
+static const uint8_t P9N2_PU_PBASLVCTL1_EXTADDR_LEN = 14 ;
+static const uint8_t P9N2_PU_PBASLVCTL1_RESERVED_50 = 50 ;
+
+static const uint8_t P9N2_PU_PBASLVCTL2_ENABLE = 0 ;
+static const uint8_t P9N2_PU_PBASLVCTL2_MID_MATCH_VALUE = 1 ;
+static const uint8_t P9N2_PU_PBASLVCTL2_MID_MATCH_VALUE_LEN = 3 ;
+static const uint8_t P9N2_PU_PBASLVCTL2_RESERVED_4 = 4 ;
+static const uint8_t P9N2_PU_PBASLVCTL2_MID_CARE_MASK = 5 ;
+static const uint8_t P9N2_PU_PBASLVCTL2_MID_CARE_MASK_LEN = 3 ;
+static const uint8_t P9N2_PU_PBASLVCTL2_WRITE_TTYPE = 8 ;
+static const uint8_t P9N2_PU_PBASLVCTL2_WRITE_TTYPE_LEN = 3 ;
+static const uint8_t P9N2_PU_PBASLVCTL2_RESERVED_11_14 = 11 ;
+static const uint8_t P9N2_PU_PBASLVCTL2_RESERVED_11_14_LEN = 4 ;
+static const uint8_t P9N2_PU_PBASLVCTL2_READ_TTYPE = 15 ;
+static const uint8_t P9N2_PU_PBASLVCTL2_READ_PREFETCH_CTL = 16 ;
+static const uint8_t P9N2_PU_PBASLVCTL2_READ_PREFETCH_CTL_LEN = 2 ;
+static const uint8_t P9N2_PU_PBASLVCTL2_BUF_INVALIDATE_CTL = 18 ;
+static const uint8_t P9N2_PU_PBASLVCTL2_BUF_ALLOC_W = 19 ;
+static const uint8_t P9N2_PU_PBASLVCTL2_BUF_ALLOC_A = 20 ;
+static const uint8_t P9N2_PU_PBASLVCTL2_BUF_ALLOC_B = 21 ;
+static const uint8_t P9N2_PU_PBASLVCTL2_BUF_ALLOC_C = 22 ;
+static const uint8_t P9N2_PU_PBASLVCTL2_RESERVED_23 = 23 ;
+static const uint8_t P9N2_PU_PBASLVCTL2_DIS_WRITE_GATHER = 24 ;
+static const uint8_t P9N2_PU_PBASLVCTL2_WR_GATHER_TIMEOUT = 25 ;
+static const uint8_t P9N2_PU_PBASLVCTL2_WR_GATHER_TIMEOUT_LEN = 3 ;
+static const uint8_t P9N2_PU_PBASLVCTL2_WRITE_TSIZE = 28 ;
+static const uint8_t P9N2_PU_PBASLVCTL2_WRITE_TSIZE_LEN = 8 ;
+static const uint8_t P9N2_PU_PBASLVCTL2_EXTADDR = 36 ;
+static const uint8_t P9N2_PU_PBASLVCTL2_EXTADDR_LEN = 14 ;
+static const uint8_t P9N2_PU_PBASLVCTL2_RESERVED_50 = 50 ;
+
+static const uint8_t P9N2_PU_PBASLVCTL3_ENABLE = 0 ;
+static const uint8_t P9N2_PU_PBASLVCTL3_MID_MATCH_VALUE = 1 ;
+static const uint8_t P9N2_PU_PBASLVCTL3_MID_MATCH_VALUE_LEN = 3 ;
+static const uint8_t P9N2_PU_PBASLVCTL3_RESERVED_4 = 4 ;
+static const uint8_t P9N2_PU_PBASLVCTL3_MID_CARE_MASK = 5 ;
+static const uint8_t P9N2_PU_PBASLVCTL3_MID_CARE_MASK_LEN = 3 ;
+static const uint8_t P9N2_PU_PBASLVCTL3_WRITE_TTYPE = 8 ;
+static const uint8_t P9N2_PU_PBASLVCTL3_WRITE_TTYPE_LEN = 3 ;
+static const uint8_t P9N2_PU_PBASLVCTL3_RESERVED_11_14 = 11 ;
+static const uint8_t P9N2_PU_PBASLVCTL3_RESERVED_11_14_LEN = 4 ;
+static const uint8_t P9N2_PU_PBASLVCTL3_READ_TTYPE = 15 ;
+static const uint8_t P9N2_PU_PBASLVCTL3_READ_PREFETCH_CTL = 16 ;
+static const uint8_t P9N2_PU_PBASLVCTL3_READ_PREFETCH_CTL_LEN = 2 ;
+static const uint8_t P9N2_PU_PBASLVCTL3_BUF_INVALIDATE_CTL = 18 ;
+static const uint8_t P9N2_PU_PBASLVCTL3_BUF_ALLOC_W = 19 ;
+static const uint8_t P9N2_PU_PBASLVCTL3_BUF_ALLOC_A = 20 ;
+static const uint8_t P9N2_PU_PBASLVCTL3_BUF_ALLOC_B = 21 ;
+static const uint8_t P9N2_PU_PBASLVCTL3_BUF_ALLOC_C = 22 ;
+static const uint8_t P9N2_PU_PBASLVCTL3_RESERVED_23 = 23 ;
+static const uint8_t P9N2_PU_PBASLVCTL3_DIS_WRITE_GATHER = 24 ;
+static const uint8_t P9N2_PU_PBASLVCTL3_WR_GATHER_TIMEOUT = 25 ;
+static const uint8_t P9N2_PU_PBASLVCTL3_WR_GATHER_TIMEOUT_LEN = 3 ;
+static const uint8_t P9N2_PU_PBASLVCTL3_WRITE_TSIZE = 28 ;
+static const uint8_t P9N2_PU_PBASLVCTL3_WRITE_TSIZE_LEN = 8 ;
+static const uint8_t P9N2_PU_PBASLVCTL3_EXTADDR = 36 ;
+static const uint8_t P9N2_PU_PBASLVCTL3_EXTADDR_LEN = 14 ;
+static const uint8_t P9N2_PU_PBASLVCTL3_RESERVED_50 = 50 ;
+
+static const uint8_t P9N2_PU_PBASLVRST_SET = 0 ;
+static const uint8_t P9N2_PU_PBASLVRST_SET_LEN = 3 ;
+static const uint8_t P9N2_PU_PBASLVRST_IN_PROG = 4 ;
+static const uint8_t P9N2_PU_PBASLVRST_IN_PROG_LEN = 4 ;
+static const uint8_t P9N2_PU_PBASLVRST_BUSY_STATUS = 8 ;
+static const uint8_t P9N2_PU_PBASLVRST_BUSY_STATUS_LEN = 4 ;
+static const uint8_t P9N2_PU_PBASLVRST_SCOPE_ATTN_BAR = 12 ;
+static const uint8_t P9N2_PU_PBASLVRST_SCOPE_ATTN_BAR_LEN = 2 ;
+
+static const uint8_t P9N2_PU_PBAWBUFVAL0_WR_SLVNUM = 0 ;
+static const uint8_t P9N2_PU_PBAWBUFVAL0_WR_SLVNUM_LEN = 2 ;
+static const uint8_t P9N2_PU_PBAWBUFVAL0_START_WR_ADDR = 2 ;
+static const uint8_t P9N2_PU_PBAWBUFVAL0_START_WR_ADDR_LEN = 30 ;
+static const uint8_t P9N2_PU_PBAWBUFVAL0_WR_BUFFER_STATUS = 35 ;
+static const uint8_t P9N2_PU_PBAWBUFVAL0_WR_BUFFER_STATUS_LEN = 5 ;
+static const uint8_t P9N2_PU_PBAWBUFVAL0_WR_BYTE_COUNT = 41 ;
+static const uint8_t P9N2_PU_PBAWBUFVAL0_WR_BYTE_COUNT_LEN = 7 ;
+
+static const uint8_t P9N2_PU_PBAWBUFVAL1_WR_SLVNUM = 0 ;
+static const uint8_t P9N2_PU_PBAWBUFVAL1_WR_SLVNUM_LEN = 2 ;
+static const uint8_t P9N2_PU_PBAWBUFVAL1_START_WR_ADDR = 2 ;
+static const uint8_t P9N2_PU_PBAWBUFVAL1_START_WR_ADDR_LEN = 30 ;
+static const uint8_t P9N2_PU_PBAWBUFVAL1_WR_BUFFER_STATUS = 35 ;
+static const uint8_t P9N2_PU_PBAWBUFVAL1_WR_BUFFER_STATUS_LEN = 5 ;
+static const uint8_t P9N2_PU_PBAWBUFVAL1_WR_BYTE_COUNT = 41 ;
+static const uint8_t P9N2_PU_PBAWBUFVAL1_WR_BYTE_COUNT_LEN = 7 ;
+
+static const uint8_t P9N2_PU_PBAXCFG_PBAX_EN = 0 ;
+static const uint8_t P9N2_PU_PBAXCFG_RESERVATION_EN = 1 ;
+static const uint8_t P9N2_PU_PBAXCFG_SND_RESET = 2 ;
+static const uint8_t P9N2_PU_PBAXCFG_RCV_RESET = 3 ;
+static const uint8_t P9N2_PU_PBAXCFG_RCV_GROUPID = 4 ;
+static const uint8_t P9N2_PU_PBAXCFG_RCV_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PBAXCFG_RCV_CHIPID = 8 ;
+static const uint8_t P9N2_PU_PBAXCFG_RCV_CHIPID_LEN = 3 ;
+static const uint8_t P9N2_PU_PBAXCFG_RESERVED_11 = 11 ;
+static const uint8_t P9N2_PU_PBAXCFG_RCV_BRDCST_GROUP = 12 ;
+static const uint8_t P9N2_PU_PBAXCFG_RCV_BRDCST_GROUP_LEN = 8 ;
+static const uint8_t P9N2_PU_PBAXCFG_RCV_DATATO_DIV = 20 ;
+static const uint8_t P9N2_PU_PBAXCFG_RCV_DATATO_DIV_LEN = 5 ;
+static const uint8_t P9N2_PU_PBAXCFG_RESERVED_25_26 = 25 ;
+static const uint8_t P9N2_PU_PBAXCFG_RESERVED_25_26_LEN = 2 ;
+static const uint8_t P9N2_PU_PBAXCFG_SND_RETRY_COUNT_OVERCOM = 27 ;
+static const uint8_t P9N2_PU_PBAXCFG_SND_RETRY_THRESH = 28 ;
+static const uint8_t P9N2_PU_PBAXCFG_SND_RETRY_THRESH_LEN = 8 ;
+static const uint8_t P9N2_PU_PBAXCFG_SND_RSVTO_DIV = 36 ;
+static const uint8_t P9N2_PU_PBAXCFG_SND_RSVTO_DIV_LEN = 5 ;
+
+static const uint8_t P9N2_PU_PBAXRCVSTAT_RCV_IN_PROGRESS = 0 ;
+static const uint8_t P9N2_PU_PBAXRCVSTAT_RCV_ERROR = 1 ;
+static const uint8_t P9N2_PU_PBAXRCVSTAT_RCV_WRITE_IN_PROGRESS = 2 ;
+static const uint8_t P9N2_PU_PBAXRCVSTAT_RCV_RESERVATION_SET = 3 ;
+static const uint8_t P9N2_PU_PBAXRCVSTAT_RCV_CAPTURE = 4 ;
+static const uint8_t P9N2_PU_PBAXRCVSTAT_RCV_CAPTURE_LEN = 16 ;
+
+static const uint8_t P9N2_PU_PBAXSHBR0_PUSH_START = 0 ;
+static const uint8_t P9N2_PU_PBAXSHBR0_PUSH_START_LEN = 29 ;
+
+static const uint8_t P9N2_PU_PBAXSHBR1_PUSH_START = 0 ;
+static const uint8_t P9N2_PU_PBAXSHBR1_PUSH_START_LEN = 29 ;
+
+static const uint8_t P9N2_PU_PBAXSHCS0_PUSH_FULL = 0 ;
+static const uint8_t P9N2_PU_PBAXSHCS0_PUSH_EMPTY = 1 ;
+static const uint8_t P9N2_PU_PBAXSHCS0_RESERVED_2_3 = 2 ;
+static const uint8_t P9N2_PU_PBAXSHCS0_RESERVED_2_3_LEN = 2 ;
+static const uint8_t P9N2_PU_PBAXSHCS0_PUSH_INTR_ACTION_0_1 = 4 ;
+static const uint8_t P9N2_PU_PBAXSHCS0_PUSH_INTR_ACTION_0_1_LEN = 2 ;
+static const uint8_t P9N2_PU_PBAXSHCS0_PUSH_LENGTH = 6 ;
+static const uint8_t P9N2_PU_PBAXSHCS0_PUSH_LENGTH_LEN = 5 ;
+static const uint8_t P9N2_PU_PBAXSHCS0_PUSH_WRITE_PTR = 13 ;
+static const uint8_t P9N2_PU_PBAXSHCS0_PUSH_WRITE_PTR_LEN = 5 ;
+static const uint8_t P9N2_PU_PBAXSHCS0_PUSH_READ_PTR = 21 ;
+static const uint8_t P9N2_PU_PBAXSHCS0_PUSH_READ_PTR_LEN = 5 ;
+static const uint8_t P9N2_PU_PBAXSHCS0_PUSH_ENABLE = 31 ;
+
+static const uint8_t P9N2_PU_PBAXSHCS1_PUSH_FULL = 0 ;
+static const uint8_t P9N2_PU_PBAXSHCS1_PUSH_EMPTY = 1 ;
+static const uint8_t P9N2_PU_PBAXSHCS1_RESERVED_2_3 = 2 ;
+static const uint8_t P9N2_PU_PBAXSHCS1_RESERVED_2_3_LEN = 2 ;
+static const uint8_t P9N2_PU_PBAXSHCS1_PUSH_INTR_ACTION_0_1 = 4 ;
+static const uint8_t P9N2_PU_PBAXSHCS1_PUSH_INTR_ACTION_0_1_LEN = 2 ;
+static const uint8_t P9N2_PU_PBAXSHCS1_PUSH_LENGTH = 6 ;
+static const uint8_t P9N2_PU_PBAXSHCS1_PUSH_LENGTH_LEN = 5 ;
+static const uint8_t P9N2_PU_PBAXSHCS1_PUSH_WRITE_PTR = 13 ;
+static const uint8_t P9N2_PU_PBAXSHCS1_PUSH_WRITE_PTR_LEN = 5 ;
+static const uint8_t P9N2_PU_PBAXSHCS1_PUSH_READ_PTR = 21 ;
+static const uint8_t P9N2_PU_PBAXSHCS1_PUSH_READ_PTR_LEN = 5 ;
+static const uint8_t P9N2_PU_PBAXSHCS1_PUSH_ENABLE = 31 ;
+
+static const uint8_t P9N2_PU_PBAXSNDSTAT_SND_IN_PROGRESS = 0 ;
+static const uint8_t P9N2_PU_PBAXSNDSTAT_SND_ERROR = 1 ;
+static const uint8_t P9N2_PU_PBAXSNDSTAT_SND_PHASE_STATUS = 2 ;
+static const uint8_t P9N2_PU_PBAXSNDSTAT_SND_PHASE_STATUS_LEN = 2 ;
+static const uint8_t P9N2_PU_PBAXSNDSTAT_SND_CNT_STATUS = 4 ;
+static const uint8_t P9N2_PU_PBAXSNDSTAT_SND_CNT_STATUS_LEN = 4 ;
+static const uint8_t P9N2_PU_PBAXSNDSTAT_SND_RETRY_COUNT = 8 ;
+static const uint8_t P9N2_PU_PBAXSNDSTAT_SND_RETRY_COUNT_LEN = 8 ;
+
+static const uint8_t P9N2_PU_PBAXSNDTX_SND_SCOPE = 0 ;
+static const uint8_t P9N2_PU_PBAXSNDTX_SND_SCOPE_LEN = 3 ;
+static const uint8_t P9N2_PU_PBAXSNDTX_SND_QID = 3 ;
+static const uint8_t P9N2_PU_PBAXSNDTX_SND_TYPE = 4 ;
+static const uint8_t P9N2_PU_PBAXSNDTX_SND_RESERVATION = 5 ;
+static const uint8_t P9N2_PU_PBAXSNDTX_RESERVED_6_7 = 6 ;
+static const uint8_t P9N2_PU_PBAXSNDTX_RESERVED_6_7_LEN = 2 ;
+static const uint8_t P9N2_PU_PBAXSNDTX_SND_GROUPID = 8 ;
+static const uint8_t P9N2_PU_PBAXSNDTX_SND_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PBAXSNDTX_SND_CHIPID = 12 ;
+static const uint8_t P9N2_PU_PBAXSNDTX_SND_CHIPID_LEN = 3 ;
+static const uint8_t P9N2_PU_PBAXSNDTX_RESERVED_15 = 15 ;
+static const uint8_t P9N2_PU_PBAXSNDTX_VG_TARGE = 16 ;
+static const uint8_t P9N2_PU_PBAXSNDTX_VG_TARGE_LEN = 16 ;
+static const uint8_t P9N2_PU_PBAXSNDTX_SND_STOP = 59 ;
+static const uint8_t P9N2_PU_PBAXSNDTX_SND_CNT = 60 ;
+static const uint8_t P9N2_PU_PBAXSNDTX_SND_CNT_LEN = 4 ;
+
+static const uint8_t P9N2_PEC_PBCQEINJ_REG_PE_INJECT_TYPE = 0 ;
+static const uint8_t P9N2_PEC_PBCQEINJ_REG_PE_INJECT_TYPE_LEN = 2 ;
+static const uint8_t P9N2_PEC_PBCQEINJ_REG_PE_CQ_ECC_INJECT_ENABLE = 2 ;
+static const uint8_t P9N2_PEC_PBCQEINJ_REG_PE_CQ_SRAM_ARRAY = 3 ;
+static const uint8_t P9N2_PEC_PBCQEINJ_REG_PE_CQ_SRAM_ARRAY_LEN = 4 ;
+static const uint8_t P9N2_PEC_PBCQEINJ_REG_PE_CQ_PAR_INJECT_ENABLE = 7 ;
+static const uint8_t P9N2_PEC_PBCQEINJ_REG_PE_CQ_REGISTER_ARRAY = 8 ;
+static const uint8_t P9N2_PEC_PBCQEINJ_REG_PE_CQ_REGISTER_ARRAY_LEN = 3 ;
+static const uint8_t P9N2_PEC_PBCQEINJ_REG_PE_CONSTANT_EINJ = 11 ;
+
+static const uint8_t P9N2_PEC_PBCQHWCFG_REG_HANG_POLL_SCALE = 0 ;
+static const uint8_t P9N2_PEC_PBCQHWCFG_REG_HANG_POLL_SCALE_LEN = 4 ;
+static const uint8_t P9N2_PEC_PBCQHWCFG_REG_HANG_DATA_SCALE = 4 ;
+static const uint8_t P9N2_PEC_PBCQHWCFG_REG_HANG_DATA_SCALE_LEN = 4 ;
+static const uint8_t P9N2_PEC_PBCQHWCFG_REG_HANG_PE_SCALE = 8 ;
+static const uint8_t P9N2_PEC_PBCQHWCFG_REG_HANG_PE_SCALE_LEN = 4 ;
+static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_BLOCK_CQPB_PB_INIT = 12 ;
+static const uint8_t P9N2_PEC_PBCQHWCFG_REG_DISABLE_RCMD_CLKGATE = 13 ;
+static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_HANG_SM_ON_ARE = 14 ;
+static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_DISABLE_PCI_CLK_CHECK = 15 ;
+static const uint8_t P9N2_PEC_PBCQHWCFG_REG_LFSR_ARB_MODE = 16 ;
+static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_ENABLE_DMAR_IOPACING = 17 ;
+static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_ENABLE_DMAW_IOPACING = 18 ;
+static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_ADR_BAR_MODE = 19 ;
+static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_STQ_ALLOCATION = 20 ;
+static const uint8_t P9N2_PEC_PBCQHWCFG_REG_DISABLE_LPC_CMDS = 21 ;
+static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_DISABLE_OOO_MODE = 22 ;
+static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_OSMB_EARLY_START = 23 ;
+static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_OSMB_EARLY_START_LEN = 4 ;
+static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_QFIFO_HOLD_MODE = 27 ;
+static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_QFIFO_HOLD_MODE_LEN = 2 ;
+static const uint8_t P9N2_PEC_PBCQHWCFG_REG_RESERVED1 = 29 ;
+static const uint8_t P9N2_PEC_PBCQHWCFG_REG_RESERVED1_LEN = 3 ;
+static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_WR_STRICT_ORDER_MODE = 32 ;
+static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_CHANNEL_STREAMING_EN = 33 ;
+static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_WR_CACHE_INJECT_MODE = 34 ;
+static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_WR_CACHE_INJECT_MODE_LEN = 2 ;
+static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_ENABLE_NEW_FLOW_CACHE_INJECT = 36 ;
+static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_DISABLE_INJ_ON_RESEND = 37 ;
+static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_FORCE_DISABLED_CTAG_TO_FOLLOW_FLOW = 38 ;
+static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_ENABLE_ENH_FLOW = 39 ;
+static const uint8_t P9N2_PEC_PBCQHWCFG_REG_RESERVED2 = 40 ;
+static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_DISABLE_WR_VG = 41 ;
+static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_DISABLE_WR_SCOPE_GROUP = 42 ;
+static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_DISABLE_INTWR_VG = 43 ;
+static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_DISABLE_INTWR_SCOPE_GROUP = 44 ;
+static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_DISABLE_INTWR_SCOPE_NODE = 45 ;
+static const uint8_t P9N2_PEC_PBCQHWCFG_REG_RESERVED3 = 46 ;
+static const uint8_t P9N2_PEC_PBCQHWCFG_REG_RESERVED3_LEN = 2 ;
+static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_RD_WRITE_ORDERING = 48 ;
+static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_RD_WRITE_ORDERING_LEN = 2 ;
+static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_DISABLE_RD_SCOPE_NODAL = 50 ;
+static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_DISABLE_RD_SCOPE_GROUP = 51 ;
+static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_DISABLE_RD_SCOPE_RNNN = 52 ;
+static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_ENABLE_RD_SKIP_GROUP = 53 ;
+static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_DISABLE_RD_VG = 54 ;
+static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_DISABLE_TCE_SCOPE_NODAL = 55 ;
+static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_DISABLE_TCE_SCOPE_GROUP = 56 ;
+static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_DISABLE_TCE_SCOPE_RNNN = 57 ;
+static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_ENABLE_TCE_SKIP_GROUP = 58 ;
+static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_DISABLE_TCE_VG = 59 ;
+static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_DISABLE_TCE_ARBITRATION = 60 ;
+static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_DISABLE_CQ_TCE_ARBITRATION = 61 ;
+static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_DISABLE_MC_PREFETCH = 62 ;
+static const uint8_t P9N2_PEC_PBCQHWCFG_REG_PE_IGNORE_SFSTAT = 63 ;
+
+static const uint8_t P9N2_PHB_PBCQMODE_REG_PE_PEER2PEER_MODDE = 0 ;
+static const uint8_t P9N2_PHB_PBCQMODE_REG_PE_ENHANCED_PEER2PEER_MODDE = 1 ;
+
+static const uint8_t P9N2_PEC_STACK0_PBCQMODE_REG_PE_PEER2PEER_MODDE = 0 ;
+static const uint8_t P9N2_PEC_STACK0_PBCQMODE_REG_PE_ENHANCED_PEER2PEER_MODDE = 1 ;
+
+static const uint8_t P9N2_PU_PBE_MAILBOX_CTL_REG_MB_VALID = 0 ;
+static const uint8_t P9N2_PU_PBE_MAILBOX_CTL_REG_MB_WR_NOT_RD = 1 ;
+static const uint8_t P9N2_PU_PBE_MAILBOX_CTL_REG_MB_BAD_ADDR = 2 ;
+static const uint8_t P9N2_PU_PBE_MAILBOX_CTL_REG_MB_LINK_DOWN = 3 ;
+static const uint8_t P9N2_PU_PBE_MAILBOX_CTL_REG_MB_CORRUPT = 4 ;
+static const uint8_t P9N2_PU_PBE_MAILBOX_CTL_REG_MB_SENT = 5 ;
+static const uint8_t P9N2_PU_PBE_MAILBOX_CTL_REG_MB_BAD_WRITE = 6 ;
+static const uint8_t P9N2_PU_PBE_MAILBOX_CTL_REG_MB_RESET = 7 ;
+static const uint8_t P9N2_PU_PBE_MAILBOX_CTL_REG_ID = 8 ;
+static const uint8_t P9N2_PU_PBE_MAILBOX_CTL_REG_MB_LINK_ID = 9 ;
+static const uint8_t P9N2_PU_PBE_MAILBOX_CTL_REG_MB_LINK_ID_LEN = 3 ;
+static const uint8_t P9N2_PU_PBE_MAILBOX_CTL_REG_MB_SPARE = 12 ;
+static const uint8_t P9N2_PU_PBE_MAILBOX_CTL_REG_MB_SPARE_LEN = 4 ;
+
+static const uint8_t P9N2_PU_IOE_PBO_MAILBOX_CTL_REG_MB_VALID = 0 ;
+static const uint8_t P9N2_PU_IOE_PBO_MAILBOX_CTL_REG_MB_WR_NOT_RD = 1 ;
+static const uint8_t P9N2_PU_IOE_PBO_MAILBOX_CTL_REG_MB_BAD_ADDR = 2 ;
+static const uint8_t P9N2_PU_IOE_PBO_MAILBOX_CTL_REG_MB_LINK_DOWN = 3 ;
+static const uint8_t P9N2_PU_IOE_PBO_MAILBOX_CTL_REG_MB_CORRUPT = 4 ;
+static const uint8_t P9N2_PU_IOE_PBO_MAILBOX_CTL_REG_MB_SENT = 5 ;
+static const uint8_t P9N2_PU_IOE_PBO_MAILBOX_CTL_REG_MB_BAD_WRITE = 6 ;
+static const uint8_t P9N2_PU_IOE_PBO_MAILBOX_CTL_REG_MB_RESET = 7 ;
+static const uint8_t P9N2_PU_IOE_PBO_MAILBOX_CTL_REG_ID = 8 ;
+static const uint8_t P9N2_PU_IOE_PBO_MAILBOX_CTL_REG_MB_LINK_ID = 9 ;
+static const uint8_t P9N2_PU_IOE_PBO_MAILBOX_CTL_REG_MB_LINK_ID_LEN = 3 ;
+static const uint8_t P9N2_PU_IOE_PBO_MAILBOX_CTL_REG_MB_SPARE = 12 ;
+static const uint8_t P9N2_PU_IOE_PBO_MAILBOX_CTL_REG_MB_SPARE_LEN = 4 ;
+
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_EN = 0 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_RESET_MODE = 1 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_COUNTER_MODE = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_GLOBAL_PMISC_DIS = 3 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_GLOBAL_PMISC_MODE = 4 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_EXTERNAL_FREEZE = 5 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_0_1_OP = 6 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_0_1_OP_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_2_3_OP = 8 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_2_3_OP_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_4_5_OP = 10 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_4_5_OP_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_6_7_OP = 12 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_6_7_OP_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_8_9_OP = 14 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_8_9_OP_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_10_11_OP = 16 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_10_11_OP_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_12_13_OP = 18 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_12_13_OP_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_14_15_OP = 20 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_14_15_OP_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_16_17_OP = 22 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_16_17_OP_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_18_19_OP = 24 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_18_19_OP_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_20_21_OP = 26 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_20_21_OP_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_22_23_OP = 28 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_22_23_OP_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_24_25_OP = 30 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_24_25_OP_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_26_27_OP = 32 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_26_27_OP_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_28_29_OP = 34 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_28_29_OP_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_30_31_OP = 36 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_30_31_OP_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_CASCADE_PMU0 = 38 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_CASCADE_PMU0_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_CASCADE_PMU1 = 41 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_CASCADE_PMU1_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_CASCADE_PMU2 = 44 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_CASCADE_PMU2_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_CASCADE_PMU3 = 47 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_CASCADE_PMU3_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_MASK = 50 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_MC2_MCS0_MASK = 51 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_MC2_MCS1_MASK = 52 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_MC3_MCS0_MASK = 53 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_MC3_MCS1_MASK = 54 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_PB_CFG_CNPME_MASK = 55 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_MCD_MASK = 56 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_PE0_MASK = 57 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_PE1_MASK = 58 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_PE2_MASK = 59 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_VAS_MASK = 60 ;
+
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_EN = 0 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_RESET_MODE = 1 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_COUNTER_MODE = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_GLOBAL_PMISC_DIS = 3 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_GLOBAL_PMISC_MODE = 4 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_EXTERNAL_FREEZE = 5 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_0_1_OP = 6 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_0_1_OP_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_2_3_OP = 8 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_2_3_OP_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_4_5_OP = 10 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_4_5_OP_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_6_7_OP = 12 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_6_7_OP_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_8_9_OP = 14 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_8_9_OP_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_10_11_OP = 16 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_10_11_OP_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_12_13_OP = 18 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_12_13_OP_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_14_15_OP = 20 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_14_15_OP_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_16_17_OP = 22 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_16_17_OP_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_18_19_OP = 24 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_18_19_OP_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_20_21_OP = 26 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_20_21_OP_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_22_23_OP = 28 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_22_23_OP_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_24_25_OP = 30 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_24_25_OP_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_26_27_OP = 32 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_26_27_OP_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_28_29_OP = 34 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_28_29_OP_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_30_31_OP = 36 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_30_31_OP_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_CASCADE_PMU0 = 38 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_CASCADE_PMU0_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_CASCADE_PMU1 = 41 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_CASCADE_PMU1_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_CASCADE_PMU2 = 44 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_CASCADE_PMU2_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_CASCADE_PMU3 = 47 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_CASCADE_PMU3_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_MASK = 50 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_MC0_MCS0_MASK = 51 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_MC0_MCS1_MASK = 52 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_MC1_MCS0_MASK = 53 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_MC1_MCS1_MASK = 54 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_INT_MASK = 56 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_PE0_MASK = 57 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_PE1_MASK = 58 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_PE2_MASK = 59 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_CNPMW_PB_CFG_CNPMW_MASK = 60 ;
+
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_CR_ERROR_PB_CRESP_ERROR = 0 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_CR_ERROR_PB_CRESP_ADDR_ERROR = 1 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_CR_ERROR_PB_CFG_CRESP_ERROR_OTHER = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_CR_ERROR_PB_CFG_CRESP_TTYPE = 3 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_CR_ERROR_PB_CFG_CRESP_TTYPE_LEN = 7 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_CR_ERROR_PB_CFG_CRESP_TSIZE = 10 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_CR_ERROR_PB_CFG_CRESP_TSIZE_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_CR_ERROR_PB_CFG_CRESP_TTAG = 18 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_CR_ERROR_PB_CFG_CRESP_TTAG_LEN = 22 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_CR_ERROR_PB_CFG_CRESP_SCOPE = 40 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_CR_ERROR_PB_CFG_CRESP_SCOPE_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_CR_ERROR_PB_CFG_CRESP = 43 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_CR_ERROR_PB_CFG_CRESP_LEN = 5 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_CR_ERROR_PB_CFG_PRESP = 48 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_CR_ERROR_PB_CFG_PRESP_LEN = 14 ;
+
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_TTYPE = 0 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_TTYPE_LEN = 7 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_TTYPE_MASK = 7 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_TTYPE_MASK_LEN = 7 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_TSIZE = 14 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_TSIZE_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_TSIZE_MASK = 22 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_TSIZE_MASK_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_TTAG = 30 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_TTAG_LEN = 10 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_TTAG_MASK = 40 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_TTAG_MASK_LEN = 10 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_CRESP = 50 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_CRESP_LEN = 5 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_CRESP_MASK = 55 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_CRESP_MASK_LEN = 5 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_CRESP_POLARITY = 60 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_SCOPE = 61 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_SCOPE_LEN = 3 ;
+
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_TTYPE = 0 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_TTYPE_LEN = 7 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_TTYPE_MASK = 7 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_TTYPE_MASK_LEN = 7 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_TSIZE = 14 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_TSIZE_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_TSIZE_MASK = 22 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_TSIZE_MASK_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_TTAG = 30 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_TTAG_LEN = 10 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_TTAG_MASK = 40 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_TTAG_MASK_LEN = 10 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_CRESP = 50 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_CRESP_LEN = 5 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_CRESP_MASK = 55 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_CRESP_MASK_LEN = 5 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_CRESP_POLARITY = 60 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_SCOPE = 61 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_SCOPE_LEN = 3 ;
+
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPX_CFG_COMPA_SCOPE_MASK = 0 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPX_CFG_COMPA_SCOPE_MASK_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPX_CFG_COMPA_PRESP = 3 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPX_CFG_COMPA_PRESP_LEN = 14 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPX_CFG_COMPA_PRESP_MASK = 17 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPX_CFG_COMPA_PRESP_MASK_LEN = 14 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPX_CFG_COMPB_SCOPE_MASK = 32 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPX_CFG_COMPB_SCOPE_MASK_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPX_CFG_COMPB_PRESP = 35 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPX_CFG_COMPB_PRESP_LEN = 14 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPX_CFG_COMPB_PRESP_MASK = 49 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_COMPX_CFG_COMPB_PRESP_MASK_LEN = 14 ;
+
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL0 = 0 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL0_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL1 = 3 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL1_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL2 = 6 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL2_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL3 = 9 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL3_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL4 = 12 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL4_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL5 = 15 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL5_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL6 = 18 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL6_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL7 = 21 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL7_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_CNPME_BITWISE_ENABLE = 24 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_CNPME_BITWISE_ENABLE_LEN = 16 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_CNPMW_BITWISE_ENABLE = 40 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_CNPMW_BITWISE_ENABLE_LEN = 16 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_PORT = 56 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_PORT_SEL2 = 57 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_CHSW_HW405366 = 58 ;
+
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_EXTDAT_COUNTER_PB_APM_EXTDATASND_CNT = 0 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_EXTDAT_COUNTER_PB_APM_EXTDATASND_CNT_LEN = 32 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_EXTDAT_COUNTER_PB_APM_EXTDATARCV_CNT = 32 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_EXTDAT_COUNTER_PB_APM_EXTDATARCV_CNT_LEN = 32 ;
+
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_ACTION0_REG_ACTION0 = 0 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_ACTION0_REG_ACTION0_LEN = 18 ;
+
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_ACTION1_REG_ACTION1 = 0 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_ACTION1_REG_ACTION1_LEN = 18 ;
+
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_PROTOCOL_ERROR = 0 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_OVERFLOW_ERROR = 1 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_HW_PARITY_ERROR = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_SPARE_3 = 3 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_COHERENCY_ERROR = 4 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_CRESP_ADDR_ERROR = 5 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_CRESP_ERROR = 6 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_HANG_RECOVERY_LIMIT_ERROR = 7 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_DATA_ROUTE_ERROR = 8 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_HANG_RECOVERY_GTE_LEVEL1 = 9 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_FORCE_MP_IPL = 10 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_SBE_IPL = 11 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_SPARE_12 = 12 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_SPARE_13 = 13 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_SPARE_14 = 14 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_SPARE_15 = 15 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_SCOM_ERR = 16 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_SCOM_ERR_DUP = 17 ;
+
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_REG_PROTOCOL_ERROR = 0 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_REG_OVERFLOW_ERROR = 1 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_REG_HW_PARITY_ERROR = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_REG_SPARE_3 = 3 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_REG_COHERENCY_ERROR = 4 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_REG_CRESP_ADDR_ERROR = 5 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_REG_CRESP_ERROR = 6 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_REG_HANG_RECOVERY_LIMIT_ERROR = 7 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_REG_DATA_ROUTE_ERROR = 8 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_REG_HANG_RECOVERY_GTE_LEVEL1 = 9 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_REG_FORCE_MP_IPL = 10 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_REG_SBE_IPL = 11 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_REG_SPARE_12 = 12 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_REG_SPARE_13 = 13 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_REG_SPARE_14 = 14 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_REG_SPARE_15 = 15 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_REG_SCOM_ERR = 16 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_FIR_REG_SCOM_ERR_DUP = 17 ;
+
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL0 = 0 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL0_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL1 = 8 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL1_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL2 = 16 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL2_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL3 = 24 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL3_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL4 = 32 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL4_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL5 = 40 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL5_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL6 = 48 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL6_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL7 = 56 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL7_LEN = 8 ;
+
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL0 = 0 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL0_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL1 = 8 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL1_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL2 = 16 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL2_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL3 = 24 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL3_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL4 = 32 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL4_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL5 = 40 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL5_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL6 = 48 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL6_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL7 = 56 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL7_LEN = 8 ;
+
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X0TOA0_EN = 0 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X0TOA1_EN = 1 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X0TOA2_EN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X0TOA3_EN = 3 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X1TOA0_EN = 4 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X1TOA1_EN = 5 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X1TOA2_EN = 6 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X1TOA3_EN = 7 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X2TOA0_EN = 8 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X2TOA1_EN = 9 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X2TOA2_EN = 10 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X2TOA3_EN = 11 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X0TOA0_GROUPID = 16 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X0TOA0_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X0TOA1_GROUPID = 20 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X0TOA1_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X0TOA2_GROUPID = 24 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X0TOA2_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X0TOA3_GROUPID = 28 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X0TOA3_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X1TOA0_GROUPID = 32 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X1TOA0_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X1TOA1_GROUPID = 36 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X1TOA1_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X1TOA2_GROUPID = 40 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X1TOA2_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X1TOA3_GROUPID = 44 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X1TOA3_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X2TOA0_GROUPID = 48 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X2TOA0_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X2TOA1_GROUPID = 52 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X2TOA1_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X2TOA2_GROUPID = 56 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X2TOA2_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X2TOA3_GROUPID = 60 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR_PB_CFG_CENT_LINK_X2TOA3_GROUPID_LEN = 4 ;
+
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X0TOA0_EN = 0 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X0TOA1_EN = 1 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X0TOA2_EN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X0TOA3_EN = 3 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X1TOA0_EN = 4 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X1TOA1_EN = 5 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X1TOA2_EN = 6 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X1TOA3_EN = 7 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X2TOA0_EN = 8 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X2TOA1_EN = 9 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X2TOA2_EN = 10 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X2TOA3_EN = 11 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X0TOA0_GROUPID = 16 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X0TOA0_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X0TOA1_GROUPID = 20 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X0TOA1_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X0TOA2_GROUPID = 24 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X0TOA2_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X0TOA3_GROUPID = 28 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X0TOA3_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X1TOA0_GROUPID = 32 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X1TOA0_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X1TOA1_GROUPID = 36 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X1TOA1_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X1TOA2_GROUPID = 40 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X1TOA2_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X1TOA3_GROUPID = 44 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X1TOA3_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X2TOA0_GROUPID = 48 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X2TOA0_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X2TOA1_GROUPID = 52 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X2TOA1_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X2TOA2_GROUPID = 56 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X2TOA2_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X2TOA3_GROUPID = 60 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT_PB_CFG_CENT_LINK_X2TOA3_GROUPID_LEN = 4 ;
+
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X0_EN = 0 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X1_EN = 1 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X2_EN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X3_EN = 3 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X4_EN = 4 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X5_EN = 5 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X6_EN = 6 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_NX0_ADDR_DIS = 8 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_NX1_ADDR_DIS = 9 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_NX2_ADDR_DIS = 10 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_NX3_ADDR_DIS = 11 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_NX4_ADDR_DIS = 12 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_NX5_ADDR_DIS = 13 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_NX6_ADDR_DIS = 14 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X0_CHIPID = 16 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X0_CHIPID_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X1_CHIPID = 19 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X1_CHIPID_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X2_CHIPID = 22 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X2_CHIPID_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X3_CHIPID = 25 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X3_CHIPID_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X4_CHIPID = 28 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X4_CHIPID_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X5_CHIPID = 31 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X5_CHIPID_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X6_CHIPID = 34 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X6_CHIPID_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_X_AGGREGATE = 37 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_X_FP_DISABLED = 48 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_X_INDIRECT_EN = 49 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_X_GATHER_ENABLE = 50 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_X_CMD_RATE = 56 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_X_CMD_RATE_LEN = 8 ;
+
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X0_EN = 0 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X1_EN = 1 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X2_EN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X3_EN = 3 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X4_EN = 4 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X5_EN = 5 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X6_EN = 6 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_NX0_ADDR_DIS = 8 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_NX1_ADDR_DIS = 9 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_NX2_ADDR_DIS = 10 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_NX3_ADDR_DIS = 11 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_NX4_ADDR_DIS = 12 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_NX5_ADDR_DIS = 13 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_NX6_ADDR_DIS = 14 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X0_CHIPID = 16 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X0_CHIPID_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X1_CHIPID = 19 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X1_CHIPID_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X2_CHIPID = 22 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X2_CHIPID_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X3_CHIPID = 25 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X3_CHIPID_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X4_CHIPID = 28 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X4_CHIPID_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X5_CHIPID = 31 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X5_CHIPID_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X6_CHIPID = 34 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X6_CHIPID_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_X_AGGREGATE = 37 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_X_FP_DISABLED = 48 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_X_INDIRECT_EN = 49 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_X_GATHER_ENABLE = 50 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_X_CMD_RATE = 56 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_X_CMD_RATE_LEN = 8 ;
+
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_MASTER_CHIP = 0 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_TM_MASTER = 1 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_CHG_RATE_GP_MASTER = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_CHG_RATE_SP_MASTER = 3 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_A0_EN = 4 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_A1_EN = 5 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_A2_EN = 6 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_A3_EN = 7 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_NA0_ADDR_DIS = 8 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_NA1_ADDR_DIS = 9 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_NA2_ADDR_DIS = 10 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_NA3_ADDR_DIS = 11 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_A0_GROUPID = 12 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_A0_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_A1_GROUPID = 16 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_A1_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_A2_GROUPID = 20 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_A2_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_A3_GROUPID = 24 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_A3_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_A_AGGREGATE = 28 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_HOP = 29 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_SMP_OPTICS = 30 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_PB_CFG_CENT_CAPI_MODE = 31 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_OPT0 = 32 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_OPT0_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_OPT1 = 34 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_OPT1_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_OPT2 = 36 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_OPT2_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_OPT3 = 38 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_OPT3_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_XLATE_ADDR_TO_ID = 40 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_XLATE_ADDR_TO_ID_LEN = 7 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_PB_CFG_CENT_SPARE01 = 47 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_PB_CFG_CENT_SPARE01_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_PB_CFG_CENT_A_INDIRECT_EN = 49 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_A_GATHER_ENABLE = 50 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_PB_CFG_CENT_SPARE2 = 51 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_PHYP_IS_GROUP = 52 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_ADDR_BAR = 53 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_PUMP = 54 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_DCACHE_CAPP = 55 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_A_CMD_RATE = 56 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_A_CMD_RATE_LEN = 8 ;
+
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_MASTER_CHIP = 0 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_TM_MASTER = 1 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_CHG_RATE_GP_MASTER = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_CHG_RATE_SP_MASTER = 3 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_A0_EN = 4 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_A1_EN = 5 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_A2_EN = 6 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_A3_EN = 7 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_NA0_ADDR_DIS = 8 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_NA1_ADDR_DIS = 9 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_NA2_ADDR_DIS = 10 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_NA3_ADDR_DIS = 11 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_A0_GROUPID = 12 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_A0_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_A1_GROUPID = 16 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_A1_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_A2_GROUPID = 20 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_A2_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_A3_GROUPID = 24 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_A3_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_A_AGGREGATE = 28 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_HOP = 29 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_SMP_OPTICS = 30 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_CAPI = 31 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_OPT0 = 32 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_OPT0_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_OPT1 = 34 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_OPT1_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_OPT2 = 36 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_OPT2_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_OPT3 = 38 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_OPT3_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_XLATE_ADDR_TO_ID = 40 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_XLATE_ADDR_TO_ID_LEN = 7 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_PB_CFG_CENT_SPARE01 = 47 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_PB_CFG_CENT_SPARE01_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_PB_CFG_CENT_A_INDIRECT_EN = 49 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_A_GATHER_ENABLE = 50 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_PB_CFG_CENT_SPARE2 = 51 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_PHYP_IS_GROUP = 52 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_ADDR_BAR = 53 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_PUMP = 54 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_DCACHE_CAPP = 55 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_A_CMD_RATE = 56 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_A_CMD_RATE_LEN = 8 ;
+
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_LMPM_COUNTER_CFG_APM_DD1_MODE = 0 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_LMPM_COUNTER_CFG_APM_SEL = 1 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_LMPM_COUNTER_CFG_APM_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_LMPM_COUNTER_CFG_PMU_FREEZE_MODE = 4 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_LMPM_COUNTER_CFG_APM_LM_HI_COMP = 8 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_LMPM_COUNTER_CFG_APM_LM_HI_COMP_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_LMPM_COUNTER_CFG_APM_LM_LO_COMP = 12 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_LMPM_COUNTER_CFG_APM_LM_LO_COMP_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_LMPM_COUNTER_PB_APM_LM_LO_CNT = 16 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_LMPM_COUNTER_PB_APM_LM_LO_CNT_LEN = 24 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_LMPM_COUNTER_PB_APM_LM_HI_CNT = 40 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_LMPM_COUNTER_PB_APM_LM_HI_CNT_LEN = 24 ;
+
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_MODE_PB_CENT_PBIXXX_INIT = 0 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_MODE_PB_CENT_DBG_MAX_HANG_STAGE_REACHED = 1 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_MODE_PB_CENT_DBG_MAX_HANG_STAGE_REACHED_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_MODE_CFG_CHIP_IS_SYSTEM = 4 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_MODE_CFG_HNG_CHK_DISABLE = 8 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_MODE_DBG_CLR_MAX_HANG_STAGE = 9 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_MODE_CFG_SW_AB_WAIT = 12 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_MODE_CFG_SW_AB_WAIT_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_MODE_CFG_SP_HW_MARK = 16 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_MODE_CFG_SP_HW_MARK_LEN = 7 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_MODE_CFG_GP_HW_MARK = 23 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_MODE_CFG_GP_HW_MARK_LEN = 7 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_MODE_CFG_LCL_HW_MARK = 30 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_MODE_CFG_LCL_HW_MARK_LEN = 6 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_MODE_CFG_CPU_RATIO_OVERRIDE = 36 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_MODE_CFG_CPU_RATIO_OVERRIDE_LEN = 6 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_MODE_CFG_CHIP_ADDR_EXTENSION_MASK = 42 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_MODE_CFG_CHIP_ADDR_EXTENSION_MASK_LEN = 7 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_MODE_CFG_PPE_SERIAL_CONTROL = 56 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_MODE_CFG_REQ_GATHER_ENABLE = 57 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_MODE_CFG_SWITCH_CD_PULSE = 58 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_MODE_CFG_SWITCH_OPTION_AB = 59 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_MODE_CFG_SERIAL_READ_ENABLE = 60 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_MODE_CFG_SERIAL_READ_SEL = 61 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_MODE_CFG_SERIAL_READ_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_MODE_CFG_RESET_ERROR_CAPTURE = 63 ;
+
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_NMPM_COUNTER_CFG_APM_ENABLE = 0 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_NMPM_COUNTER_CFG_APM_SAMPLE_SEL = 1 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_NMPM_COUNTER_CFG_APM_SAMPLE_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_NMPM_COUNTER_CFG_PMUCNT_EN = 3 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_NMPM_COUNTER_CFG_PMUCNT_SEL = 4 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_NMPM_COUNTER_CFG_PMUCNT_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_NMPM_COUNTER_CFG_APM_NM_HI_COMP = 8 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_NMPM_COUNTER_CFG_APM_NM_HI_COMP_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_NMPM_COUNTER_CFG_APM_NM_LO_COMP = 12 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_NMPM_COUNTER_CFG_APM_NM_LO_COMP_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_NMPM_COUNTER_PB_APM_NM_LO_CNT = 16 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_NMPM_COUNTER_PB_APM_NM_LO_CNT_LEN = 24 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_NMPM_COUNTER_PB_APM_NM_HI_CNT = 40 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_NMPM_COUNTER_PB_APM_NM_HI_CNT_LEN = 24 ;
+
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU0_CNPME_COUNTER_PBH_EVENT_PMU0_CNPME_COUNTER0 = 0 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU0_CNPME_COUNTER_PBH_EVENT_PMU0_CNPME_COUNTER0_LEN = 16 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU0_CNPME_COUNTER_PBH_EVENT_PMU0_CNPME_COUNTER1 = 16 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU0_CNPME_COUNTER_PBH_EVENT_PMU0_CNPME_COUNTER1_LEN = 16 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU0_CNPME_COUNTER_PBH_EVENT_PMU0_CNPME_COUNTER2 = 32 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU0_CNPME_COUNTER_PBH_EVENT_PMU0_CNPME_COUNTER2_LEN = 16 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU0_CNPME_COUNTER_PBH_EVENT_PMU0_CNPME_COUNTER3 = 48 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU0_CNPME_COUNTER_PBH_EVENT_PMU0_CNPME_COUNTER3_LEN = 16 ;
+
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU0_CNPMW_COUNTER_PBH_EVENT_PMU0_CNPMW_COUNTER0 = 0 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU0_CNPMW_COUNTER_PBH_EVENT_PMU0_CNPMW_COUNTER0_LEN = 16 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU0_CNPMW_COUNTER_PBH_EVENT_PMU0_CNPMW_COUNTER1 = 16 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU0_CNPMW_COUNTER_PBH_EVENT_PMU0_CNPMW_COUNTER1_LEN = 16 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU0_CNPMW_COUNTER_PBH_EVENT_PMU0_CNPMW_COUNTER2 = 32 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU0_CNPMW_COUNTER_PBH_EVENT_PMU0_CNPMW_COUNTER2_LEN = 16 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU0_CNPMW_COUNTER_PBH_EVENT_PMU0_CNPMW_COUNTER3 = 48 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU0_CNPMW_COUNTER_PBH_EVENT_PMU0_CNPMW_COUNTER3_LEN = 16 ;
+
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU1_CNPME_COUNTER_PBH_EVENT_PMU1_CNPME_COUNTER0 = 0 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU1_CNPME_COUNTER_PBH_EVENT_PMU1_CNPME_COUNTER0_LEN = 16 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU1_CNPME_COUNTER_PBH_EVENT_PMU1_CNPME_COUNTER1 = 16 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU1_CNPME_COUNTER_PBH_EVENT_PMU1_CNPME_COUNTER1_LEN = 16 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU1_CNPME_COUNTER_PBH_EVENT_PMU1_CNPME_COUNTER2 = 32 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU1_CNPME_COUNTER_PBH_EVENT_PMU1_CNPME_COUNTER2_LEN = 16 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU1_CNPME_COUNTER_PBH_EVENT_PMU1_CNPME_COUNTER3 = 48 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU1_CNPME_COUNTER_PBH_EVENT_PMU1_CNPME_COUNTER3_LEN = 16 ;
+
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU1_CNPMW_COUNTER_PBH_EVENT_PMU1_CNPMW_COUNTER0 = 0 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU1_CNPMW_COUNTER_PBH_EVENT_PMU1_CNPMW_COUNTER0_LEN = 16 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU1_CNPMW_COUNTER_PBH_EVENT_PMU1_CNPMW_COUNTER1 = 16 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU1_CNPMW_COUNTER_PBH_EVENT_PMU1_CNPMW_COUNTER1_LEN = 16 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU1_CNPMW_COUNTER_PBH_EVENT_PMU1_CNPMW_COUNTER2 = 32 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU1_CNPMW_COUNTER_PBH_EVENT_PMU1_CNPMW_COUNTER2_LEN = 16 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU1_CNPMW_COUNTER_PBH_EVENT_PMU1_CNPMW_COUNTER3 = 48 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU1_CNPMW_COUNTER_PBH_EVENT_PMU1_CNPMW_COUNTER3_LEN = 16 ;
+
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU2_CNPME_COUNTER_PBH_EVENT_PMU2_CNPME_COUNTER0 = 0 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU2_CNPME_COUNTER_PBH_EVENT_PMU2_CNPME_COUNTER0_LEN = 16 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU2_CNPME_COUNTER_PBH_EVENT_PMU2_CNPME_COUNTER1 = 16 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU2_CNPME_COUNTER_PBH_EVENT_PMU2_CNPME_COUNTER1_LEN = 16 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU2_CNPME_COUNTER_PBH_EVENT_PMU2_CNPME_COUNTER2 = 32 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU2_CNPME_COUNTER_PBH_EVENT_PMU2_CNPME_COUNTER2_LEN = 16 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU2_CNPME_COUNTER_PBH_EVENT_PMU2_CNPME_COUNTER3 = 48 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU2_CNPME_COUNTER_PBH_EVENT_PMU2_CNPME_COUNTER3_LEN = 16 ;
+
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_PMU2_CNPMW_COUNTER_PBH_EVENT_PMU2_CNPMW_COUNTER0 = 0 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_PMU2_CNPMW_COUNTER_PBH_EVENT_PMU2_CNPMW_COUNTER0_LEN = 16 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_PMU2_CNPMW_COUNTER_PBH_EVENT_PMU2_CNPMW_COUNTER1 = 16 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_PMU2_CNPMW_COUNTER_PBH_EVENT_PMU2_CNPMW_COUNTER1_LEN = 16 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_PMU2_CNPMW_COUNTER_PBH_EVENT_PMU2_CNPMW_COUNTER2 = 32 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_PMU2_CNPMW_COUNTER_PBH_EVENT_PMU2_CNPMW_COUNTER2_LEN = 16 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_PMU2_CNPMW_COUNTER_PBH_EVENT_PMU2_CNPMW_COUNTER3 = 48 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_PMU2_CNPMW_COUNTER_PBH_EVENT_PMU2_CNPMW_COUNTER3_LEN = 16 ;
+
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU3_CNPME_COUNTER_PBH_EVENT_PMU3_CNPME_COUNTER0 = 0 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU3_CNPME_COUNTER_PBH_EVENT_PMU3_CNPME_COUNTER0_LEN = 16 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU3_CNPME_COUNTER_PBH_EVENT_PMU3_CNPME_COUNTER1 = 16 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU3_CNPME_COUNTER_PBH_EVENT_PMU3_CNPME_COUNTER1_LEN = 16 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU3_CNPME_COUNTER_PBH_EVENT_PMU3_CNPME_COUNTER2 = 32 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU3_CNPME_COUNTER_PBH_EVENT_PMU3_CNPME_COUNTER2_LEN = 16 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU3_CNPME_COUNTER_PBH_EVENT_PMU3_CNPME_COUNTER3 = 48 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU3_CNPME_COUNTER_PBH_EVENT_PMU3_CNPME_COUNTER3_LEN = 16 ;
+
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_PMU3_CNPMW_COUNTER_PBH_EVENT_PMU3_CNPMW_COUNTER0 = 0 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_PMU3_CNPMW_COUNTER_PBH_EVENT_PMU3_CNPMW_COUNTER0_LEN = 16 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_PMU3_CNPMW_COUNTER_PBH_EVENT_PMU3_CNPMW_COUNTER1 = 16 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_PMU3_CNPMW_COUNTER_PBH_EVENT_PMU3_CNPMW_COUNTER1_LEN = 16 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_PMU3_CNPMW_COUNTER_PBH_EVENT_PMU3_CNPMW_COUNTER2 = 32 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_PMU3_CNPMW_COUNTER_PBH_EVENT_PMU3_CNPMW_COUNTER2_LEN = 16 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_PMU3_CNPMW_COUNTER_PBH_EVENT_PMU3_CNPMW_COUNTER3 = 48 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_PMU3_CNPMW_COUNTER_PBH_EVENT_PMU3_CNPMW_COUNTER3_LEN = 16 ;
+
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP0_C0 = 0 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP0_C0_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP0_C1 = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP0_C1_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP0_C2 = 4 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP0_C2_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP0_C3 = 6 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP0_C3_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP1_C0 = 8 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP1_C0_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP1_C1 = 10 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP1_C1_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP1_C2 = 12 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP1_C2_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP1_C3 = 14 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP1_C3_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP2_C0 = 16 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP2_C0_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP2_C1 = 18 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP2_C1_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP2_C2 = 20 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP2_C2_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP2_C3 = 22 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP2_C3_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP3_C0 = 24 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP3_C0_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP3_C1 = 26 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP3_C1_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP3_C2 = 28 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP3_C2_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP3_C3 = 30 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP3_C3_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP0_C0 = 33 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP0_C1 = 34 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP0_C1_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP0_C2 = 36 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP0_C2_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP0_C3 = 38 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP0_C3_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP1_C0 = 40 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP1_C0_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP1_C1 = 42 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP1_C1_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP1_C2 = 44 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP1_C2_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP1_C3 = 46 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP1_C3_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP2_C0 = 48 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP2_C0_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP2_C1 = 50 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP2_C1_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP2_C2 = 52 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP2_C2_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP2_C3 = 54 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP2_C3_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP3_C0 = 56 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP3_C0_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP3_C1 = 58 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP3_C1_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP3_C2 = 60 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP3_C2_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP3_C3 = 62 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP3_C3_LEN = 2 ;
+
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_RCMD_INTDAT_COUNTER_PB_APM_RCMD_CNT = 0 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_RCMD_INTDAT_COUNTER_PB_APM_RCMD_CNT_LEN = 32 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_RCMD_INTDAT_COUNTER_PB_APM_INTDATA_CNT = 32 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_RCMD_INTDAT_COUNTER_PB_APM_INTDATA_CNT_LEN = 32 ;
+
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL0 = 0 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL0_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL1 = 8 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL1_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL2 = 16 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL2_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL3 = 24 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL3_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL4 = 32 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL4_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL5 = 40 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL5_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL6 = 48 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL6_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL7 = 56 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL7_LEN = 8 ;
+
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL0 = 0 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL0_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL1 = 8 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL1_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL2 = 16 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL2_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL3 = 24 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL3_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL4 = 32 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL4_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL5 = 40 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL5_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL6 = 48 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL6_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL7 = 56 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL7_LEN = 8 ;
+
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_SCONFIG_LOAD_CFG = 0 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_SCONFIG_LOAD_CFG_SLOW = 1 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_SCONFIG_LOAD_CFG_SHIFT_COUNT = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_SCONFIG_LOAD_CFG_SHIFT_COUNT_LEN = 6 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_SCONFIG_LOAD_CFG_SELECT = 8 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_SCONFIG_LOAD_CFG_SELECT_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_SCONFIG_LOAD_CFG_SHIFT_DATA = 12 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_SCONFIG_LOAD_CFG_SHIFT_DATA_LEN = 52 ;
+
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL0 = 0 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL0_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL1 = 8 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL1_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL2 = 16 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL2_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL3 = 24 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL3_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL4 = 32 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL4_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL5 = 40 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL5_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL6 = 48 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL6_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL7 = 56 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL7_LEN = 8 ;
+
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL0 = 0 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL0_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL1 = 8 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL1_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL2 = 16 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL2_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL3 = 24 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL3_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL4 = 32 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL4_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL5 = 40 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL5_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL6 = 48 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL6_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL7 = 56 ;
+static const uint8_t P9N2_PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL7_LEN = 8 ;
+
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELSN0 = 0 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELSN0_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELSN1 = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELSN1_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELSN2 = 4 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELSN2_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELSN3 = 6 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELSN3_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELCR0 = 8 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELCR0_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELCR1 = 10 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELCR1_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELCR2 = 12 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELCR2_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELCR3 = 14 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELCR3_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PBIEN_DBG_0_SEL = 16 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PBIEN_DBG_0_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PBIEN_DBG_1_SEL = 18 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PBIEN_DBG_1_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PBIES_DBG_0_SEL = 20 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PBIES_DBG_0_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PBIES_DBG_1_SEL = 22 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PBIES_DBG_1_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PBIOT_DBG_0_SEL = 24 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PBIOT_DBG_0_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PBIOT_DBG_1_SEL = 26 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PBIOT_DBG_1_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PBIOT_SEL = 28 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELRT = 29 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELRT_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PERFTRACE_EN = 32 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PERFTRACE_TRIG = 33 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PERFTRACE_COUNTER_SEL = 34 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PERFTRACE_COUNTER_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PERFTRACE_COUNTER_MATCH = 36 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PERFTRACE_COUNTER_MATCH_LEN = 16 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_ENABLE_PERFTRACE_PRESCALE = 52 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_ENABLE_PERFTRACE_FIXED_WIN = 53 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PERFTRACE_GRP1_SEL = 54 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PERFTRACE_GRP2_SEL = 55 ;
+static const uint8_t P9N2_PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_DATA_ACT = 63 ;
+
+static const uint8_t P9N2_PU_PB_CHGRATE_CFG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_CFG_SERIAL_SWITCH_CD = 1 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_CFG_RESET_GP_DP0_HIST = 2 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_CFG_RESET_GP_DP1_HIST = 3 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_CFG_RESET_VG_DP0_HIST = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_CFG_RESET_VG_DP1_HIST = 5 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_CFG_RESET_RNS_DP0_HIST = 6 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_CFG_RESET_RNS_DP1_HIST = 7 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_CFG_SPARE1 = 8 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_CFG_SPARE1_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_CFG_GP_DP0_OVERFLOW = 32 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_CFG_GP_DP1_OVERFLOW = 33 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_CFG_VG_DP0_OVERFLOW = 34 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_CFG_VG_DP1_OVERFLOW = 35 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_CFG_RNS_DP0_OVERFLOW = 36 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_CFG_RNS_DP1_OVERFLOW = 37 ;
+
+static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP0_HIST_VALID_LVL_00 = 0 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP0_HIST_VALID_LVL_00_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP0_HIST_VALID_LVL_01 = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP0_HIST_VALID_LVL_01_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP0_HIST_VALID_LVL_02 = 8 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP0_HIST_VALID_LVL_02_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP0_HIST_VALID_LVL_03 = 12 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP0_HIST_VALID_LVL_03_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP0_HIST_VALID_LVL_04 = 16 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP0_HIST_VALID_LVL_04_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP0_HIST_VALID_LVL_05 = 20 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP0_HIST_VALID_LVL_05_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP0_HIST_VALID_LVL_06 = 24 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP0_HIST_VALID_LVL_06_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP0_HIST_VALID_LVL_07 = 28 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP0_HIST_VALID_LVL_07_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP0_HIST_VALID_LVL_08 = 32 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP0_HIST_VALID_LVL_08_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP0_HIST_VALID_LVL_09 = 36 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP0_HIST_VALID_LVL_09_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP0_HIST_VALID_LVL_10 = 40 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP0_HIST_VALID_LVL_10_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP0_HIST_VALID_LVL_11 = 44 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP0_HIST_VALID_LVL_11_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP0_HIST_VALID_LVL_12 = 48 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP0_HIST_VALID_LVL_12_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP0_HIST_VALID_LVL_13 = 52 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP0_HIST_VALID_LVL_13_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP0_HIST_VALID_LVL_14 = 56 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP0_HIST_VALID_LVL_14_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP0_HIST_VALID_LVL_15 = 60 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP0_HIST_VALID_LVL_15_LEN = 4 ;
+
+static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP1_HIST_VALID_LVL_00 = 0 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP1_HIST_VALID_LVL_00_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP1_HIST_VALID_LVL_01 = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP1_HIST_VALID_LVL_01_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP1_HIST_VALID_LVL_02 = 8 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP1_HIST_VALID_LVL_02_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP1_HIST_VALID_LVL_03 = 12 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP1_HIST_VALID_LVL_03_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP1_HIST_VALID_LVL_04 = 16 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP1_HIST_VALID_LVL_04_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP1_HIST_VALID_LVL_05 = 20 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP1_HIST_VALID_LVL_05_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP1_HIST_VALID_LVL_06 = 24 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP1_HIST_VALID_LVL_06_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP1_HIST_VALID_LVL_07 = 28 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP1_HIST_VALID_LVL_07_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP1_HIST_VALID_LVL_08 = 32 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP1_HIST_VALID_LVL_08_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP1_HIST_VALID_LVL_09 = 36 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP1_HIST_VALID_LVL_09_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP1_HIST_VALID_LVL_10 = 40 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP1_HIST_VALID_LVL_10_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP1_HIST_VALID_LVL_11 = 44 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP1_HIST_VALID_LVL_11_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP1_HIST_VALID_LVL_12 = 48 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP1_HIST_VALID_LVL_12_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP1_HIST_VALID_LVL_13 = 52 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP1_HIST_VALID_LVL_13_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP1_HIST_VALID_LVL_14 = 56 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP1_HIST_VALID_LVL_14_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP1_HIST_VALID_LVL_15 = 60 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_GP_DP1_HIST_VALID_LVL_15_LEN = 4 ;
+
+static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP0_HIST_VALID_LVL_00 = 0 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP0_HIST_VALID_LVL_00_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP0_HIST_VALID_LVL_01 = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP0_HIST_VALID_LVL_01_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP0_HIST_VALID_LVL_02 = 8 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP0_HIST_VALID_LVL_02_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP0_HIST_VALID_LVL_03 = 12 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP0_HIST_VALID_LVL_03_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP0_HIST_VALID_LVL_04 = 16 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP0_HIST_VALID_LVL_04_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP0_HIST_VALID_LVL_05 = 20 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP0_HIST_VALID_LVL_05_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP0_HIST_VALID_LVL_06 = 24 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP0_HIST_VALID_LVL_06_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP0_HIST_VALID_LVL_07 = 28 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP0_HIST_VALID_LVL_07_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP0_HIST_VALID_LVL_08 = 32 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP0_HIST_VALID_LVL_08_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP0_HIST_VALID_LVL_09 = 36 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP0_HIST_VALID_LVL_09_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP0_HIST_VALID_LVL_10 = 40 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP0_HIST_VALID_LVL_10_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP0_HIST_VALID_LVL_11 = 44 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP0_HIST_VALID_LVL_11_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP0_HIST_VALID_LVL_12 = 48 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP0_HIST_VALID_LVL_12_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP0_HIST_VALID_LVL_13 = 52 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP0_HIST_VALID_LVL_13_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP0_HIST_VALID_LVL_14 = 56 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP0_HIST_VALID_LVL_14_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP0_HIST_VALID_LVL_15 = 60 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP0_HIST_VALID_LVL_15_LEN = 4 ;
+
+static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP1_HIST_VALID_LVL_00 = 0 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP1_HIST_VALID_LVL_00_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP1_HIST_VALID_LVL_01 = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP1_HIST_VALID_LVL_01_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP1_HIST_VALID_LVL_02 = 8 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP1_HIST_VALID_LVL_02_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP1_HIST_VALID_LVL_03 = 12 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP1_HIST_VALID_LVL_03_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP1_HIST_VALID_LVL_04 = 16 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP1_HIST_VALID_LVL_04_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP1_HIST_VALID_LVL_05 = 20 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP1_HIST_VALID_LVL_05_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP1_HIST_VALID_LVL_06 = 24 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP1_HIST_VALID_LVL_06_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP1_HIST_VALID_LVL_07 = 28 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP1_HIST_VALID_LVL_07_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP1_HIST_VALID_LVL_08 = 32 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP1_HIST_VALID_LVL_08_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP1_HIST_VALID_LVL_09 = 36 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP1_HIST_VALID_LVL_09_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP1_HIST_VALID_LVL_10 = 40 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP1_HIST_VALID_LVL_10_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP1_HIST_VALID_LVL_11 = 44 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP1_HIST_VALID_LVL_11_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP1_HIST_VALID_LVL_12 = 48 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP1_HIST_VALID_LVL_12_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP1_HIST_VALID_LVL_13 = 52 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP1_HIST_VALID_LVL_13_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP1_HIST_VALID_LVL_14 = 56 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP1_HIST_VALID_LVL_14_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP1_HIST_VALID_LVL_15 = 60 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_RNS_DP1_HIST_VALID_LVL_15_LEN = 4 ;
+
+static const uint8_t P9N2_PU_PB_CHGRATE_SCONFIG_LOAD_PB_CFG_SCONFIG_LOAD = 0 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_SCONFIG_LOAD_PB_CFG_SCONFIG_SLOW = 1 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_SCONFIG_LOAD_PB_CFG_SCONFIG_SHIFT_COUNT = 2 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_SCONFIG_LOAD_PB_CFG_SCONFIG_SHIFT_COUNT_LEN = 6 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_SCONFIG_LOAD_PB_CFG_SCONFIG_SELECT = 8 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_SCONFIG_LOAD_PB_CFG_SCONFIG_SELECT_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_SCONFIG_LOAD_PB_CFG_SCONFIG_SHIFT_DATA = 12 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_SCONFIG_LOAD_PB_CFG_SCONFIG_SHIFT_DATA_LEN = 52 ;
+
+static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP0_HIST_VALID_LVL_00 = 0 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP0_HIST_VALID_LVL_00_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP0_HIST_VALID_LVL_01 = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP0_HIST_VALID_LVL_01_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP0_HIST_VALID_LVL_02 = 8 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP0_HIST_VALID_LVL_02_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP0_HIST_VALID_LVL_03 = 12 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP0_HIST_VALID_LVL_03_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP0_HIST_VALID_LVL_04 = 16 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP0_HIST_VALID_LVL_04_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP0_HIST_VALID_LVL_05 = 20 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP0_HIST_VALID_LVL_05_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP0_HIST_VALID_LVL_06 = 24 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP0_HIST_VALID_LVL_06_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP0_HIST_VALID_LVL_07 = 28 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP0_HIST_VALID_LVL_07_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP0_HIST_VALID_LVL_08 = 32 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP0_HIST_VALID_LVL_08_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP0_HIST_VALID_LVL_09 = 36 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP0_HIST_VALID_LVL_09_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP0_HIST_VALID_LVL_10 = 40 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP0_HIST_VALID_LVL_10_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP0_HIST_VALID_LVL_11 = 44 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP0_HIST_VALID_LVL_11_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP0_HIST_VALID_LVL_12 = 48 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP0_HIST_VALID_LVL_12_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP0_HIST_VALID_LVL_13 = 52 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP0_HIST_VALID_LVL_13_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP0_HIST_VALID_LVL_14 = 56 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP0_HIST_VALID_LVL_14_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP0_HIST_VALID_LVL_15 = 60 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP0_HIST_VALID_LVL_15_LEN = 4 ;
+
+static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP1_HIST_VALID_LVL_00 = 0 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP1_HIST_VALID_LVL_00_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP1_HIST_VALID_LVL_01 = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP1_HIST_VALID_LVL_01_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP1_HIST_VALID_LVL_02 = 8 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP1_HIST_VALID_LVL_02_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP1_HIST_VALID_LVL_03 = 12 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP1_HIST_VALID_LVL_03_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP1_HIST_VALID_LVL_04 = 16 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP1_HIST_VALID_LVL_04_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP1_HIST_VALID_LVL_05 = 20 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP1_HIST_VALID_LVL_05_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP1_HIST_VALID_LVL_06 = 24 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP1_HIST_VALID_LVL_06_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP1_HIST_VALID_LVL_07 = 28 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP1_HIST_VALID_LVL_07_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP1_HIST_VALID_LVL_08 = 32 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP1_HIST_VALID_LVL_08_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP1_HIST_VALID_LVL_09 = 36 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP1_HIST_VALID_LVL_09_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP1_HIST_VALID_LVL_10 = 40 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP1_HIST_VALID_LVL_10_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP1_HIST_VALID_LVL_11 = 44 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP1_HIST_VALID_LVL_11_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP1_HIST_VALID_LVL_12 = 48 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP1_HIST_VALID_LVL_12_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP1_HIST_VALID_LVL_13 = 52 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP1_HIST_VALID_LVL_13_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP1_HIST_VALID_LVL_14 = 56 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP1_HIST_VALID_LVL_14_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP1_HIST_VALID_LVL_15 = 60 ;
+static const uint8_t P9N2_PU_PB_CHGRATE_VG_DP1_HIST_VALID_LVL_15_LEN = 4 ;
+
+static const uint8_t P9N2_PU_PB_EAST_FIR_ACTION0_REG_ACTION0 = 0 ;
+static const uint8_t P9N2_PU_PB_EAST_FIR_ACTION0_REG_ACTION0_LEN = 34 ;
+
+static const uint8_t P9N2_PU_PB_EAST_FIR_ACTION1_REG_ACTION1 = 0 ;
+static const uint8_t P9N2_PU_PB_EAST_FIR_ACTION1_REG_ACTION1_LEN = 34 ;
+
+static const uint8_t P9N2_PU_PB_EAST_FIR_MASK_REG_PBIEQ04_PBH_HW1_ERROR = 0 ;
+static const uint8_t P9N2_PU_PB_EAST_FIR_MASK_REG_PBIEQ04_PBH_HW2_ERROR = 1 ;
+static const uint8_t P9N2_PU_PB_EAST_FIR_MASK_REG_PBIEQ04_PBH_PROTOCOL_ERROR = 2 ;
+static const uint8_t P9N2_PU_PB_EAST_FIR_MASK_REG_PBIEQ04_PBH_OVERFLOW_ERROR = 3 ;
+static const uint8_t P9N2_PU_PB_EAST_FIR_MASK_REG_PBIEQ05_PBH_HW1_ERROR = 4 ;
+static const uint8_t P9N2_PU_PB_EAST_FIR_MASK_REG_PBIEQ05_PBH_HW2_ERROR = 5 ;
+static const uint8_t P9N2_PU_PB_EAST_FIR_MASK_REG_PBIEQ05_PBH_PROTOCOL_ERROR = 6 ;
+static const uint8_t P9N2_PU_PB_EAST_FIR_MASK_REG_PBIEQ05_PBH_OVERFLOW_ERROR = 7 ;
+static const uint8_t P9N2_PU_PB_EAST_FIR_MASK_REG_SPARE_8 = 8 ;
+static const uint8_t P9N2_PU_PB_EAST_FIR_MASK_REG_SPARE_9 = 9 ;
+static const uint8_t P9N2_PU_PB_EAST_FIR_MASK_REG_SPARE_10 = 10 ;
+static const uint8_t P9N2_PU_PB_EAST_FIR_MASK_REG_SPARE_11 = 11 ;
+static const uint8_t P9N2_PU_PB_EAST_FIR_MASK_REG_SPARE_12 = 12 ;
+static const uint8_t P9N2_PU_PB_EAST_FIR_MASK_REG_SPARE_13 = 13 ;
+static const uint8_t P9N2_PU_PB_EAST_FIR_MASK_REG_SPARE_14 = 14 ;
+static const uint8_t P9N2_PU_PB_EAST_FIR_MASK_REG_SPARE_15 = 15 ;
+static const uint8_t P9N2_PU_PB_EAST_FIR_MASK_REG_OVERFLOW_CHECKSTOP = 16 ;
+static const uint8_t P9N2_PU_PB_EAST_FIR_MASK_REG_PROTOCOL_CHECKSTOP = 17 ;
+static const uint8_t P9N2_PU_PB_EAST_FIR_MASK_REG_ROUTE_CHECKSTOP = 18 ;
+static const uint8_t P9N2_PU_PB_EAST_FIR_MASK_REG_SPARE_19 = 19 ;
+static const uint8_t P9N2_PU_PB_EAST_FIR_MASK_REG_SPARE_20 = 20 ;
+static const uint8_t P9N2_PU_PB_EAST_FIR_MASK_REG_SPARE_21 = 21 ;
+static const uint8_t P9N2_PU_PB_EAST_FIR_MASK_REG_SPARE_22 = 22 ;
+static const uint8_t P9N2_PU_PB_EAST_FIR_MASK_REG_SPARE_23 = 23 ;
+static const uint8_t P9N2_PU_PB_EAST_FIR_MASK_REG_SPARE_24 = 24 ;
+static const uint8_t P9N2_PU_PB_EAST_FIR_MASK_REG_SPARE_25 = 25 ;
+static const uint8_t P9N2_PU_PB_EAST_FIR_MASK_REG_SPARE_26 = 26 ;
+static const uint8_t P9N2_PU_PB_EAST_FIR_MASK_REG_SPARE_27 = 27 ;
+static const uint8_t P9N2_PU_PB_EAST_FIR_MASK_REG_SPARE_28 = 28 ;
+static const uint8_t P9N2_PU_PB_EAST_FIR_MASK_REG_SPARE_29 = 29 ;
+static const uint8_t P9N2_PU_PB_EAST_FIR_MASK_REG_SPARE_30 = 30 ;
+static const uint8_t P9N2_PU_PB_EAST_FIR_MASK_REG_SPARE_31 = 31 ;
+static const uint8_t P9N2_PU_PB_EAST_FIR_MASK_REG_SCOM_ERR = 32 ;
+static const uint8_t P9N2_PU_PB_EAST_FIR_MASK_REG_SCOM_ERR_DUP = 33 ;
+
+static const uint8_t P9N2_PU_PB_EAST_FIR_REG_PBIEQ04_PBH_HW1_ERROR = 0 ;
+static const uint8_t P9N2_PU_PB_EAST_FIR_REG_PBIEQ04_PBH_HW2_ERROR = 1 ;
+static const uint8_t P9N2_PU_PB_EAST_FIR_REG_PBIEQ04_PBH_PROTOCOL_ERROR = 2 ;
+static const uint8_t P9N2_PU_PB_EAST_FIR_REG_PBIEQ04_PBH_OVERFLOW_ERROR = 3 ;
+static const uint8_t P9N2_PU_PB_EAST_FIR_REG_PBIEQ05_PBH_HW1_ERROR = 4 ;
+static const uint8_t P9N2_PU_PB_EAST_FIR_REG_PBIEQ05_PBH_HW2_ERROR = 5 ;
+static const uint8_t P9N2_PU_PB_EAST_FIR_REG_PBIEQ05_PBH_PROTOCOL_ERROR = 6 ;
+static const uint8_t P9N2_PU_PB_EAST_FIR_REG_PBIEQ05_PBH_OVERFLOW_ERROR = 7 ;
+static const uint8_t P9N2_PU_PB_EAST_FIR_REG_SPARE_8 = 8 ;
+static const uint8_t P9N2_PU_PB_EAST_FIR_REG_SPARE_9 = 9 ;
+static const uint8_t P9N2_PU_PB_EAST_FIR_REG_SPARE_10 = 10 ;
+static const uint8_t P9N2_PU_PB_EAST_FIR_REG_SPARE_11 = 11 ;
+static const uint8_t P9N2_PU_PB_EAST_FIR_REG_SPARE_12 = 12 ;
+static const uint8_t P9N2_PU_PB_EAST_FIR_REG_SPARE_13 = 13 ;
+static const uint8_t P9N2_PU_PB_EAST_FIR_REG_SPARE_14 = 14 ;
+static const uint8_t P9N2_PU_PB_EAST_FIR_REG_SPARE_15 = 15 ;
+static const uint8_t P9N2_PU_PB_EAST_FIR_REG_OVERFLOW_CHECKSTOP = 16 ;
+static const uint8_t P9N2_PU_PB_EAST_FIR_REG_PROTOCOL_CHECKSTOP = 17 ;
+static const uint8_t P9N2_PU_PB_EAST_FIR_REG_ROUTE_CHECKSTOP = 18 ;
+static const uint8_t P9N2_PU_PB_EAST_FIR_REG_SPARE_19 = 19 ;
+static const uint8_t P9N2_PU_PB_EAST_FIR_REG_SPARE_20 = 20 ;
+static const uint8_t P9N2_PU_PB_EAST_FIR_REG_SPARE_21 = 21 ;
+static const uint8_t P9N2_PU_PB_EAST_FIR_REG_SPARE_22 = 22 ;
+static const uint8_t P9N2_PU_PB_EAST_FIR_REG_SPARE_23 = 23 ;
+static const uint8_t P9N2_PU_PB_EAST_FIR_REG_SPARE_24 = 24 ;
+static const uint8_t P9N2_PU_PB_EAST_FIR_REG_SPARE_25 = 25 ;
+static const uint8_t P9N2_PU_PB_EAST_FIR_REG_SPARE_26 = 26 ;
+static const uint8_t P9N2_PU_PB_EAST_FIR_REG_SPARE_27 = 27 ;
+static const uint8_t P9N2_PU_PB_EAST_FIR_REG_SPARE_28 = 28 ;
+static const uint8_t P9N2_PU_PB_EAST_FIR_REG_SPARE_29 = 29 ;
+static const uint8_t P9N2_PU_PB_EAST_FIR_REG_SPARE_30 = 30 ;
+static const uint8_t P9N2_PU_PB_EAST_FIR_REG_SPARE_31 = 31 ;
+static const uint8_t P9N2_PU_PB_EAST_FIR_REG_SCOM_ERR = 32 ;
+static const uint8_t P9N2_PU_PB_EAST_FIR_REG_SCOM_ERR_DUP = 33 ;
+
+static const uint8_t P9N2_PU_PB_EAST_FW_SCRATCH0_PB_EAST_FW_SCRATCH0 = 0 ;
+static const uint8_t P9N2_PU_PB_EAST_FW_SCRATCH0_PB_EAST_FW_SCRATCH0_LEN = 64 ;
+
+static const uint8_t P9N2_PU_PB_EAST_FW_SCRATCH1_PB_EAST_FW_SCRATCH1 = 0 ;
+static const uint8_t P9N2_PU_PB_EAST_FW_SCRATCH1_PB_EAST_FW_SCRATCH1_LEN = 64 ;
+
+static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X0TOA0_EN = 0 ;
+static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X0TOA1_EN = 1 ;
+static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X0TOA2_EN = 2 ;
+static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X0TOA3_EN = 3 ;
+static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X1TOA0_EN = 4 ;
+static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X1TOA1_EN = 5 ;
+static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X1TOA2_EN = 6 ;
+static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X1TOA3_EN = 7 ;
+static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X2TOA0_EN = 8 ;
+static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X2TOA1_EN = 9 ;
+static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X2TOA2_EN = 10 ;
+static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X2TOA3_EN = 11 ;
+static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X0TOA0_GROUPID = 16 ;
+static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X0TOA0_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X0TOA1_GROUPID = 20 ;
+static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X0TOA1_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X0TOA2_GROUPID = 24 ;
+static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X0TOA2_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X0TOA3_GROUPID = 28 ;
+static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X0TOA3_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X1TOA0_GROUPID = 32 ;
+static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X1TOA0_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X1TOA1_GROUPID = 36 ;
+static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X1TOA1_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X1TOA2_GROUPID = 40 ;
+static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X1TOA2_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X1TOA3_GROUPID = 44 ;
+static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X1TOA3_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X2TOA0_GROUPID = 48 ;
+static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X2TOA0_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X2TOA1_GROUPID = 52 ;
+static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X2TOA1_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X2TOA2_GROUPID = 56 ;
+static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X2TOA2_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X2TOA3_GROUPID = 60 ;
+static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_CURR_PB_CFG_EAST_LINK_X2TOA3_GROUPID_LEN = 4 ;
+
+static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X0TOA0_EN = 0 ;
+static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X0TOA1_EN = 1 ;
+static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X0TOA2_EN = 2 ;
+static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X0TOA3_EN = 3 ;
+static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X1TOA0_EN = 4 ;
+static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X1TOA1_EN = 5 ;
+static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X1TOA2_EN = 6 ;
+static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X1TOA3_EN = 7 ;
+static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X2TOA0_EN = 8 ;
+static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X2TOA1_EN = 9 ;
+static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X2TOA2_EN = 10 ;
+static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X2TOA3_EN = 11 ;
+static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X0TOA0_GROUPID = 16 ;
+static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X0TOA0_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X0TOA1_GROUPID = 20 ;
+static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X0TOA1_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X0TOA2_GROUPID = 24 ;
+static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X0TOA2_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X0TOA3_GROUPID = 28 ;
+static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X0TOA3_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X1TOA0_GROUPID = 32 ;
+static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X1TOA0_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X1TOA1_GROUPID = 36 ;
+static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X1TOA1_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X1TOA2_GROUPID = 40 ;
+static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X1TOA2_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X1TOA3_GROUPID = 44 ;
+static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X1TOA3_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X2TOA0_GROUPID = 48 ;
+static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X2TOA0_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X2TOA1_GROUPID = 52 ;
+static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X2TOA1_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X2TOA2_GROUPID = 56 ;
+static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X2TOA2_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X2TOA3_GROUPID = 60 ;
+static const uint8_t P9N2_PU_PB_EAST_HPA_MODE_NEXT_PB_CFG_EAST_LINK_X2TOA3_GROUPID_LEN = 4 ;
+
+static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X0_EN = 0 ;
+static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X1_EN = 1 ;
+static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X2_EN = 2 ;
+static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X3_EN = 3 ;
+static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X4_EN = 4 ;
+static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X5_EN = 5 ;
+static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X6_EN = 6 ;
+static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_NX0_ADDR_DIS = 8 ;
+static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_NX1_ADDR_DIS = 9 ;
+static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_NX2_ADDR_DIS = 10 ;
+static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_NX3_ADDR_DIS = 11 ;
+static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_NX4_ADDR_DIS = 12 ;
+static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_NX5_ADDR_DIS = 13 ;
+static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_NX6_ADDR_DIS = 14 ;
+static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X0_CHIPID = 16 ;
+static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X0_CHIPID_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X1_CHIPID = 19 ;
+static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X1_CHIPID_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X2_CHIPID = 22 ;
+static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X2_CHIPID_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X3_CHIPID = 25 ;
+static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X3_CHIPID_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X4_CHIPID = 28 ;
+static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X4_CHIPID_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X5_CHIPID = 31 ;
+static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X5_CHIPID_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X6_CHIPID = 34 ;
+static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X6_CHIPID_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_CURR_CFG_X_AGGREGATE = 37 ;
+static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_CURR_CFG_X_FP_DISABLED = 48 ;
+static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_CURR_CFG_X_INDIRECT_EN = 49 ;
+static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_CURR_CFG_X_GATHER_ENABLE = 50 ;
+static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_CURR_CFG_X_CMD_RATE = 56 ;
+static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_CURR_CFG_X_CMD_RATE_LEN = 8 ;
+
+static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X0_EN = 0 ;
+static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X1_EN = 1 ;
+static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X2_EN = 2 ;
+static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X3_EN = 3 ;
+static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X4_EN = 4 ;
+static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X5_EN = 5 ;
+static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X6_EN = 6 ;
+static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_NX0_ADDR_DIS = 8 ;
+static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_NX1_ADDR_DIS = 9 ;
+static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_NX2_ADDR_DIS = 10 ;
+static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_NX3_ADDR_DIS = 11 ;
+static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_NX4_ADDR_DIS = 12 ;
+static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_NX5_ADDR_DIS = 13 ;
+static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_NX6_ADDR_DIS = 14 ;
+static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X0_CHIPID = 16 ;
+static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X0_CHIPID_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X1_CHIPID = 19 ;
+static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X1_CHIPID_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X2_CHIPID = 22 ;
+static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X2_CHIPID_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X3_CHIPID = 25 ;
+static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X3_CHIPID_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X4_CHIPID = 28 ;
+static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X4_CHIPID_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X5_CHIPID = 31 ;
+static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X5_CHIPID_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X6_CHIPID = 34 ;
+static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X6_CHIPID_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_NEXT_CFG_X_AGGREGATE = 37 ;
+static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_NEXT_CFG_X_FP_DISABLED = 48 ;
+static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_NEXT_CFG_X_INDIRECT_EN = 49 ;
+static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_NEXT_CFG_X_GATHER_ENABLE = 50 ;
+static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_NEXT_CFG_X_CMD_RATE = 56 ;
+static const uint8_t P9N2_PU_PB_EAST_HPX_MODE_NEXT_CFG_X_CMD_RATE_LEN = 8 ;
+
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_MASTER_CHIP = 0 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_TM_MASTER = 1 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_CHG_RATE_GP_MASTER = 2 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_CHG_RATE_SP_MASTER = 3 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_LINK_A0_EN = 4 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_LINK_A1_EN = 5 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_LINK_A2_EN = 6 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_LINK_A3_EN = 7 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_LINK_NA0_ADDR_DIS = 8 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_LINK_NA1_ADDR_DIS = 9 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_LINK_NA2_ADDR_DIS = 10 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_LINK_NA3_ADDR_DIS = 11 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_LINK_A0_GROUPID = 12 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_LINK_A0_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_LINK_A1_GROUPID = 16 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_LINK_A1_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_LINK_A2_GROUPID = 20 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_LINK_A2_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_LINK_A3_GROUPID = 24 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_LINK_A3_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_A_AGGREGATE = 28 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_HOP = 29 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_SMP_OPTICS = 30 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_PB_CFG_EAST_CAPI_MODE = 31 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_OPT0 = 32 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_OPT0_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_OPT1 = 34 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_OPT1_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_OPT2 = 36 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_OPT2_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_OPT3 = 38 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_OPT3_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_XLATE_ADDR_TO_ID = 40 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_XLATE_ADDR_TO_ID_LEN = 7 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_PB_CFG_EAST_SPARE01 = 47 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_PB_CFG_EAST_SPARE01_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_PB_CFG_EAST_A_INDIRECT_EN = 49 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_A_GATHER_ENABLE = 50 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_PB_CFG_EAST_SPARE2 = 51 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_PHYP_IS_GROUP = 52 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_ADDR_BAR = 53 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_PUMP = 54 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_DCACHE_CAPP = 55 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_A_CMD_RATE = 56 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_CURR_CFG_A_CMD_RATE_LEN = 8 ;
+
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_MASTER_CHIP = 0 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_TM_MASTER = 1 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_CHG_RATE_GP_MASTER = 2 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_CHG_RATE_SP_MASTER = 3 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_A0_EN = 4 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_A1_EN = 5 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_A2_EN = 6 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_A3_EN = 7 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_NA0_ADDR_DIS = 8 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_NA1_ADDR_DIS = 9 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_NA2_ADDR_DIS = 10 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_NA3_ADDR_DIS = 11 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_A0_GROUPID = 12 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_A0_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_A1_GROUPID = 16 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_A1_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_A2_GROUPID = 20 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_A2_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_A3_GROUPID = 24 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_A3_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_A_AGGREGATE = 28 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_HOP = 29 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_SMP_OPTICS = 30 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_CAPI = 31 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_OPT0 = 32 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_OPT0_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_OPT1 = 34 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_OPT1_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_OPT2 = 36 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_OPT2_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_OPT3 = 38 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_OPT3_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_XLATE_ADDR_TO_ID = 40 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_XLATE_ADDR_TO_ID_LEN = 7 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_PB_CFG_EAST_SPARE01 = 47 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_PB_CFG_EAST_SPARE01_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_PB_CFG_EAST_A_INDIRECT_EN = 49 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_A_GATHER_ENABLE = 50 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_PB_CFG_EAST_SPARE2 = 51 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_PHYP_IS_GROUP = 52 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_ADDR_BAR = 53 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_PUMP = 54 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_DCACHE_CAPP = 55 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_A_CMD_RATE = 56 ;
+static const uint8_t P9N2_PU_PB_EAST_HP_MODE_NEXT_CFG_A_CMD_RATE_LEN = 8 ;
+
+static const uint8_t P9N2_PU_PB_EAST_MODE_PB_EAST_PBIXXX_INIT = 0 ;
+static const uint8_t P9N2_PU_PB_EAST_MODE_CFG_CHIP_IS_SYSTEM = 4 ;
+static const uint8_t P9N2_PU_PB_EAST_MODE_CFG_HNG_CHK_DISABLE = 8 ;
+static const uint8_t P9N2_PU_PB_EAST_MODE_DBG_CLR_MAX_HANG_STAGE = 9 ;
+static const uint8_t P9N2_PU_PB_EAST_MODE_CFG_SW_AB_WAIT = 12 ;
+static const uint8_t P9N2_PU_PB_EAST_MODE_CFG_SW_AB_WAIT_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_EAST_MODE_CFG_SP_HW_MARK = 16 ;
+static const uint8_t P9N2_PU_PB_EAST_MODE_CFG_SP_HW_MARK_LEN = 7 ;
+static const uint8_t P9N2_PU_PB_EAST_MODE_CFG_GP_HW_MARK = 23 ;
+static const uint8_t P9N2_PU_PB_EAST_MODE_CFG_GP_HW_MARK_LEN = 7 ;
+static const uint8_t P9N2_PU_PB_EAST_MODE_CFG_LCL_HW_MARK = 30 ;
+static const uint8_t P9N2_PU_PB_EAST_MODE_CFG_LCL_HW_MARK_LEN = 6 ;
+static const uint8_t P9N2_PU_PB_EAST_MODE_PB_CFG_EAST_CPU_RATIO_OVERRIDE = 36 ;
+static const uint8_t P9N2_PU_PB_EAST_MODE_PB_CFG_EAST_CPU_RATIO_OVERRIDE_LEN = 6 ;
+static const uint8_t P9N2_PU_PB_EAST_MODE_CFG_CHIP_ADDR_EXTENSION_MASK = 42 ;
+static const uint8_t P9N2_PU_PB_EAST_MODE_CFG_CHIP_ADDR_EXTENSION_MASK_LEN = 7 ;
+static const uint8_t P9N2_PU_PB_EAST_MODE_CFG_PPE_SERIAL_CONTROL = 56 ;
+static const uint8_t P9N2_PU_PB_EAST_MODE_CFG_REQ_GATHER_ENABLE = 57 ;
+static const uint8_t P9N2_PU_PB_EAST_MODE_CFG_SWITCH_CD_PULSE = 58 ;
+static const uint8_t P9N2_PU_PB_EAST_MODE_CFG_SWITCH_OPTION_AB = 59 ;
+static const uint8_t P9N2_PU_PB_EAST_MODE_CFG_SERIAL_READ_ENABLE = 60 ;
+static const uint8_t P9N2_PU_PB_EAST_MODE_CFG_SERIAL_READ_SEL = 61 ;
+static const uint8_t P9N2_PU_PB_EAST_MODE_CFG_SERIAL_READ_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_EAST_MODE_PB_CFG_EAST_RESET_ERROR_CAPTURE = 63 ;
+
+static const uint8_t P9N2_PU_PB_EAST_SCONFIG_LOAD_CFG = 0 ;
+static const uint8_t P9N2_PU_PB_EAST_SCONFIG_LOAD_CFG_SLOW = 1 ;
+static const uint8_t P9N2_PU_PB_EAST_SCONFIG_LOAD_CFG_SHIFT_COUNT = 2 ;
+static const uint8_t P9N2_PU_PB_EAST_SCONFIG_LOAD_CFG_SHIFT_COUNT_LEN = 6 ;
+static const uint8_t P9N2_PU_PB_EAST_SCONFIG_LOAD_CFG_SELECT = 8 ;
+static const uint8_t P9N2_PU_PB_EAST_SCONFIG_LOAD_CFG_SELECT_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_EAST_SCONFIG_LOAD_CFG_SHIFT_DATA = 12 ;
+static const uint8_t P9N2_PU_PB_EAST_SCONFIG_LOAD_CFG_SHIFT_DATA_LEN = 52 ;
+
+static const uint8_t P9N2_PU_PB_EAST_SPARE_SPARE = 0 ;
+static const uint8_t P9N2_PU_PB_EAST_SPARE_SPARE_LEN = 64 ;
+
+static const uint8_t P9N2_PU_PB_ELINK_DATA_01_CFG_REG_LINK0_DOB_LIMIT = 1 ;
+static const uint8_t P9N2_PU_PB_ELINK_DATA_01_CFG_REG_LINK0_DOB_LIMIT_LEN = 7 ;
+static const uint8_t P9N2_PU_PB_ELINK_DATA_01_CFG_REG_LINK0_DOB_VC0_LIMIT = 9 ;
+static const uint8_t P9N2_PU_PB_ELINK_DATA_01_CFG_REG_LINK0_DOB_VC0_LIMIT_LEN = 7 ;
+static const uint8_t P9N2_PU_PB_ELINK_DATA_01_CFG_REG_LINK0_DOB_VC1_LIMIT = 17 ;
+static const uint8_t P9N2_PU_PB_ELINK_DATA_01_CFG_REG_LINK0_DOB_VC1_LIMIT_LEN = 7 ;
+static const uint8_t P9N2_PU_PB_ELINK_DATA_01_CFG_REG_LINK01_DIB_VC_LIMIT = 24 ;
+static const uint8_t P9N2_PU_PB_ELINK_DATA_01_CFG_REG_LINK01_DIB_VC_LIMIT_LEN = 5 ;
+static const uint8_t P9N2_PU_PB_ELINK_DATA_01_CFG_REG_LINK1_DOB_LIMIT = 33 ;
+static const uint8_t P9N2_PU_PB_ELINK_DATA_01_CFG_REG_LINK1_DOB_LIMIT_LEN = 7 ;
+static const uint8_t P9N2_PU_PB_ELINK_DATA_01_CFG_REG_LINK1_DOB_VC0_LIMIT = 41 ;
+static const uint8_t P9N2_PU_PB_ELINK_DATA_01_CFG_REG_LINK1_DOB_VC0_LIMIT_LEN = 7 ;
+static const uint8_t P9N2_PU_PB_ELINK_DATA_01_CFG_REG_LINK1_DOB_VC1_LIMIT = 49 ;
+static const uint8_t P9N2_PU_PB_ELINK_DATA_01_CFG_REG_LINK1_DOB_VC1_LIMIT_LEN = 7 ;
+
+static const uint8_t P9N2_PU_PB_ELINK_DATA_23_CFG_REG_LINK2_DOB_LIMIT = 1 ;
+static const uint8_t P9N2_PU_PB_ELINK_DATA_23_CFG_REG_LINK2_DOB_LIMIT_LEN = 7 ;
+static const uint8_t P9N2_PU_PB_ELINK_DATA_23_CFG_REG_LINK2_DOB_VC0_LIMIT = 9 ;
+static const uint8_t P9N2_PU_PB_ELINK_DATA_23_CFG_REG_LINK2_DOB_VC0_LIMIT_LEN = 7 ;
+static const uint8_t P9N2_PU_PB_ELINK_DATA_23_CFG_REG_LINK2_DOB_VC1_LIMIT = 17 ;
+static const uint8_t P9N2_PU_PB_ELINK_DATA_23_CFG_REG_LINK2_DOB_VC1_LIMIT_LEN = 7 ;
+static const uint8_t P9N2_PU_PB_ELINK_DATA_23_CFG_REG_LINK23_DIB_VC_LIMIT = 24 ;
+static const uint8_t P9N2_PU_PB_ELINK_DATA_23_CFG_REG_LINK23_DIB_VC_LIMIT_LEN = 5 ;
+static const uint8_t P9N2_PU_PB_ELINK_DATA_23_CFG_REG_LINK3_DOB_LIMIT = 33 ;
+static const uint8_t P9N2_PU_PB_ELINK_DATA_23_CFG_REG_LINK3_DOB_LIMIT_LEN = 7 ;
+static const uint8_t P9N2_PU_PB_ELINK_DATA_23_CFG_REG_LINK3_DOB_VC0_LIMIT = 41 ;
+static const uint8_t P9N2_PU_PB_ELINK_DATA_23_CFG_REG_LINK3_DOB_VC0_LIMIT_LEN = 7 ;
+static const uint8_t P9N2_PU_PB_ELINK_DATA_23_CFG_REG_LINK3_DOB_VC1_LIMIT = 49 ;
+static const uint8_t P9N2_PU_PB_ELINK_DATA_23_CFG_REG_LINK3_DOB_VC1_LIMIT_LEN = 7 ;
+
+static const uint8_t P9N2_PU_PB_ELINK_DATA_45_CFG_REG_LINK4_DOB_LIMIT = 1 ;
+static const uint8_t P9N2_PU_PB_ELINK_DATA_45_CFG_REG_LINK4_DOB_LIMIT_LEN = 7 ;
+static const uint8_t P9N2_PU_PB_ELINK_DATA_45_CFG_REG_LINK4_DOB_VC0_LIMIT = 9 ;
+static const uint8_t P9N2_PU_PB_ELINK_DATA_45_CFG_REG_LINK4_DOB_VC0_LIMIT_LEN = 7 ;
+static const uint8_t P9N2_PU_PB_ELINK_DATA_45_CFG_REG_LINK4_DOB_VC1_LIMIT = 17 ;
+static const uint8_t P9N2_PU_PB_ELINK_DATA_45_CFG_REG_LINK4_DOB_VC1_LIMIT_LEN = 7 ;
+static const uint8_t P9N2_PU_PB_ELINK_DATA_45_CFG_REG_LINK45_DIB_VC_LIMIT = 24 ;
+static const uint8_t P9N2_PU_PB_ELINK_DATA_45_CFG_REG_LINK45_DIB_VC_LIMIT_LEN = 5 ;
+static const uint8_t P9N2_PU_PB_ELINK_DATA_45_CFG_REG_LINK5_DOB_LIMIT = 33 ;
+static const uint8_t P9N2_PU_PB_ELINK_DATA_45_CFG_REG_LINK5_DOB_LIMIT_LEN = 7 ;
+static const uint8_t P9N2_PU_PB_ELINK_DATA_45_CFG_REG_LINK5_DOB_VC0_LIMIT = 41 ;
+static const uint8_t P9N2_PU_PB_ELINK_DATA_45_CFG_REG_LINK5_DOB_VC0_LIMIT_LEN = 7 ;
+static const uint8_t P9N2_PU_PB_ELINK_DATA_45_CFG_REG_LINK5_DOB_VC1_LIMIT = 49 ;
+static const uint8_t P9N2_PU_PB_ELINK_DATA_45_CFG_REG_LINK5_DOB_VC1_LIMIT_LEN = 7 ;
+
+static const uint8_t P9N2_PU_PB_ELINK_DLY_0123_REG_FMR0_LINK_DELAY = 4 ;
+static const uint8_t P9N2_PU_PB_ELINK_DLY_0123_REG_FMR0_LINK_DELAY_LEN = 12 ;
+static const uint8_t P9N2_PU_PB_ELINK_DLY_0123_REG_FMR1_LINK_DELAY = 20 ;
+static const uint8_t P9N2_PU_PB_ELINK_DLY_0123_REG_FMR1_LINK_DELAY_LEN = 12 ;
+static const uint8_t P9N2_PU_PB_ELINK_DLY_0123_REG_FMR2_LINK_DELAY = 36 ;
+static const uint8_t P9N2_PU_PB_ELINK_DLY_0123_REG_FMR2_LINK_DELAY_LEN = 12 ;
+static const uint8_t P9N2_PU_PB_ELINK_DLY_0123_REG_FMR3_LINK_DELAY = 52 ;
+static const uint8_t P9N2_PU_PB_ELINK_DLY_0123_REG_FMR3_LINK_DELAY_LEN = 12 ;
+
+static const uint8_t P9N2_PU_PB_ELINK_DLY_45_REG_FMR4_LINK_DELAY = 4 ;
+static const uint8_t P9N2_PU_PB_ELINK_DLY_45_REG_FMR4_LINK_DELAY_LEN = 12 ;
+static const uint8_t P9N2_PU_PB_ELINK_DLY_45_REG_FMR5_LINK_DELAY = 20 ;
+static const uint8_t P9N2_PU_PB_ELINK_DLY_45_REG_FMR5_LINK_DELAY_LEN = 12 ;
+
+static const uint8_t P9N2_PU_PB_ELINK_PMU0_COUNTER0 = 0 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU0_COUNTER0_LEN = 16 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU0_COUNTER1 = 16 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU0_COUNTER1_LEN = 16 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU0_COUNTER2 = 32 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU0_COUNTER2_LEN = 16 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU0_COUNTER3 = 48 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU0_COUNTER3_LEN = 16 ;
+
+static const uint8_t P9N2_PU_PB_ELINK_PMU1_COUNTER0 = 0 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU1_COUNTER0_LEN = 16 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU1_COUNTER1 = 16 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU1_COUNTER1_LEN = 16 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU1_COUNTER2 = 32 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU1_COUNTER2_LEN = 16 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU1_COUNTER3 = 48 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU1_COUNTER3_LEN = 16 ;
+
+static const uint8_t P9N2_PU_PB_ELINK_PMU2_COUNTER0 = 0 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU2_COUNTER0_LEN = 16 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU2_COUNTER1 = 16 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU2_COUNTER1_LEN = 16 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU2_COUNTER2 = 32 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU2_COUNTER2_LEN = 16 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU2_COUNTER3 = 48 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU2_COUNTER3_LEN = 16 ;
+
+static const uint8_t P9N2_PU_PB_ELINK_PMU3_COUNTER0 = 0 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU3_COUNTER0_LEN = 16 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU3_COUNTER1 = 16 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU3_COUNTER1_LEN = 16 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU3_COUNTER2 = 32 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU3_COUNTER2_LEN = 16 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU3_COUNTER3 = 48 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU3_COUNTER3_LEN = 16 ;
+
+static const uint8_t P9N2_PU_PB_ELINK_PMU4_COUNTER0 = 0 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU4_COUNTER0_LEN = 16 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU4_COUNTER1 = 16 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU4_COUNTER1_LEN = 16 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU4_COUNTER2 = 32 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU4_COUNTER2_LEN = 16 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU4_COUNTER3 = 48 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU4_COUNTER3_LEN = 16 ;
+
+static const uint8_t P9N2_PU_PB_ELINK_PMU5_COUNTER0 = 0 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU5_COUNTER0_LEN = 16 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU5_COUNTER1 = 16 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU5_COUNTER1_LEN = 16 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU5_COUNTER2 = 32 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU5_COUNTER2_LEN = 16 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU5_COUNTER3 = 48 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU5_COUNTER3_LEN = 16 ;
+
+static const uint8_t P9N2_PU_PB_ELINK_PMU6_COUNTER0 = 0 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU6_COUNTER0_LEN = 16 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU6_COUNTER1 = 16 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU6_COUNTER1_LEN = 16 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU6_COUNTER2 = 32 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU6_COUNTER2_LEN = 16 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU6_COUNTER3 = 48 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU6_COUNTER3_LEN = 16 ;
+
+static const uint8_t P9N2_PU_PB_ELINK_PMU7_COUNTER0 = 0 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU7_COUNTER0_LEN = 16 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU7_COUNTER1 = 16 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU7_COUNTER1_LEN = 16 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU7_COUNTER2 = 32 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU7_COUNTER2_LEN = 16 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU7_COUNTER3 = 48 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU7_COUNTER3_LEN = 16 ;
+
+static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_PMU0_ENABLE = 0 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_PMU1_ENABLE = 1 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_PMU2_ENABLE = 2 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_PMU3_ENABLE = 3 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_PMU4_ENABLE = 4 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_PMU5_ENABLE = 5 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_PMU6_ENABLE = 6 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_PMU7_ENABLE = 7 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_PMULET_FREEZE_MODE = 8 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_COMMON_FREEZE_MODE = 9 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_PMULET_RESET_MODE = 10 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_EVENT0_SEL = 11 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_EVENT1_SEL = 12 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_EVENT1_SEL_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_EVENT2_SEL = 16 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_EVENT2_SEL_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_EVENT3_SEL = 20 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_EVENT3_SEL_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_PMU0_SIZE = 24 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_PMU0_SIZE_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_PMU1_SIZE = 26 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_PMU1_SIZE_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_PMU2_SIZE = 28 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_PMU2_SIZE_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_PMU3_SIZE = 30 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_PMU3_SIZE_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_PMU01_LINK_SELECT = 32 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_PMU23_LINK_SELECT = 33 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_PMU45_LINK_SELECT = 34 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_PMU67_LINK_SELECT = 35 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_PMU0145_EVENT0_MODE = 36 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_PMU0145_EVENT0_MODE_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_PMU0145_EVENT1_MODE = 38 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_PMU0145_EVENT1_MODE_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_PMU0145_EVENT2_MODE = 40 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_PMU0145_EVENT2_MODE_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_PMU0145_EVENT3_MODE = 42 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_PMU0145_EVENT3_MODE_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_PMU2367_EVENT0_MODE = 44 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_PMU2367_EVENT0_MODE_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_PMU2367_EVENT1_MODE = 46 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_PMU2367_EVENT1_MODE_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_PMU2367_EVENT2_MODE = 48 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_PMU2367_EVENT2_MODE_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_PMU2367_EVENT3_MODE = 50 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_PMU2367_EVENT3_MODE_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_ENABLE_GLOBAL_RUN = 52 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_GLOBAL_RUN_MODE = 53 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_SPARE = 54 ;
+static const uint8_t P9N2_PU_PB_ELINK_PMU_CTL_REG_SPARE_LEN = 10 ;
+
+static const uint8_t P9N2_PU_PB_ELINK_RT_DELAY_CTL_REG_SET = 0 ;
+static const uint8_t P9N2_PU_PB_ELINK_RT_DELAY_CTL_REG_SET_LEN = 6 ;
+static const uint8_t P9N2_PU_PB_ELINK_RT_DELAY_CTL_REG_RT_SPARE0 = 6 ;
+static const uint8_t P9N2_PU_PB_ELINK_RT_DELAY_CTL_REG_RT_SPARE0_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_ELINK_RT_DELAY_CTL_REG_STAT = 8 ;
+static const uint8_t P9N2_PU_PB_ELINK_RT_DELAY_CTL_REG_STAT_LEN = 6 ;
+
+static const uint8_t P9N2_PU_PB_ELINK_SYN_01_REG_DOB00_SCOM_SYN0 = 0 ;
+static const uint8_t P9N2_PU_PB_ELINK_SYN_01_REG_DOB00_SCOM_SYN0_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_ELINK_SYN_01_REG_DOB00_SCOM_SYN1 = 8 ;
+static const uint8_t P9N2_PU_PB_ELINK_SYN_01_REG_DOB00_SCOM_SYN1_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_ELINK_SYN_01_REG_DOB00_SCOM_SYN2 = 16 ;
+static const uint8_t P9N2_PU_PB_ELINK_SYN_01_REG_DOB00_SCOM_SYN2_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_ELINK_SYN_01_REG_DOB00_SCOM_SYN3 = 24 ;
+static const uint8_t P9N2_PU_PB_ELINK_SYN_01_REG_DOB00_SCOM_SYN3_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_ELINK_SYN_01_REG_DOB01_SCOM_SYN0 = 32 ;
+static const uint8_t P9N2_PU_PB_ELINK_SYN_01_REG_DOB01_SCOM_SYN0_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_ELINK_SYN_01_REG_DOB01_SCOM_SYN1 = 40 ;
+static const uint8_t P9N2_PU_PB_ELINK_SYN_01_REG_DOB01_SCOM_SYN1_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_ELINK_SYN_01_REG_DOB01_SCOM_SYN2 = 48 ;
+static const uint8_t P9N2_PU_PB_ELINK_SYN_01_REG_DOB01_SCOM_SYN2_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_ELINK_SYN_01_REG_DOB01_SCOM_SYN3 = 56 ;
+static const uint8_t P9N2_PU_PB_ELINK_SYN_01_REG_DOB01_SCOM_SYN3_LEN = 8 ;
+
+static const uint8_t P9N2_PU_PB_ELINK_SYN_23_REG_DOB02_SCOM_SYN0 = 0 ;
+static const uint8_t P9N2_PU_PB_ELINK_SYN_23_REG_DOB02_SCOM_SYN0_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_ELINK_SYN_23_REG_DOB02_SCOM_SYN1 = 8 ;
+static const uint8_t P9N2_PU_PB_ELINK_SYN_23_REG_DOB02_SCOM_SYN1_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_ELINK_SYN_23_REG_DOB02_SCOM_SYN2 = 16 ;
+static const uint8_t P9N2_PU_PB_ELINK_SYN_23_REG_DOB02_SCOM_SYN2_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_ELINK_SYN_23_REG_DOB02_SCOM_SYN3 = 24 ;
+static const uint8_t P9N2_PU_PB_ELINK_SYN_23_REG_DOB02_SCOM_SYN3_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_ELINK_SYN_23_REG_DOB03_SCOM_SYN0 = 32 ;
+static const uint8_t P9N2_PU_PB_ELINK_SYN_23_REG_DOB03_SCOM_SYN0_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_ELINK_SYN_23_REG_DOB03_SCOM_SYN1 = 40 ;
+static const uint8_t P9N2_PU_PB_ELINK_SYN_23_REG_DOB03_SCOM_SYN1_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_ELINK_SYN_23_REG_DOB03_SCOM_SYN2 = 48 ;
+static const uint8_t P9N2_PU_PB_ELINK_SYN_23_REG_DOB03_SCOM_SYN2_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_ELINK_SYN_23_REG_DOB03_SCOM_SYN3 = 56 ;
+static const uint8_t P9N2_PU_PB_ELINK_SYN_23_REG_DOB03_SCOM_SYN3_LEN = 8 ;
+
+static const uint8_t P9N2_PU_PB_ELINK_SYN_45_REG_DOB04_SCOM_SYN0 = 0 ;
+static const uint8_t P9N2_PU_PB_ELINK_SYN_45_REG_DOB04_SCOM_SYN0_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_ELINK_SYN_45_REG_DOB04_SCOM_SYN1 = 8 ;
+static const uint8_t P9N2_PU_PB_ELINK_SYN_45_REG_DOB04_SCOM_SYN1_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_ELINK_SYN_45_REG_DOB04_SCOM_SYN2 = 16 ;
+static const uint8_t P9N2_PU_PB_ELINK_SYN_45_REG_DOB04_SCOM_SYN2_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_ELINK_SYN_45_REG_DOB04_SCOM_SYN3 = 24 ;
+static const uint8_t P9N2_PU_PB_ELINK_SYN_45_REG_DOB04_SCOM_SYN3_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_ELINK_SYN_45_REG_DOB05_SCOM_SYN0 = 32 ;
+static const uint8_t P9N2_PU_PB_ELINK_SYN_45_REG_DOB05_SCOM_SYN0_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_ELINK_SYN_45_REG_DOB05_SCOM_SYN1 = 40 ;
+static const uint8_t P9N2_PU_PB_ELINK_SYN_45_REG_DOB05_SCOM_SYN1_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_ELINK_SYN_45_REG_DOB05_SCOM_SYN2 = 48 ;
+static const uint8_t P9N2_PU_PB_ELINK_SYN_45_REG_DOB05_SCOM_SYN2_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_ELINK_SYN_45_REG_DOB05_SCOM_SYN3 = 56 ;
+static const uint8_t P9N2_PU_PB_ELINK_SYN_45_REG_DOB05_SCOM_SYN3_LEN = 8 ;
+
+static const uint8_t P9N2_PU_PB_EN_DOB_ECC_ERR_REG_DOB01_UE = 0 ;
+static const uint8_t P9N2_PU_PB_EN_DOB_ECC_ERR_REG_DOB01_UE_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_EN_DOB_ECC_ERR_REG_DOB01_CE = 4 ;
+static const uint8_t P9N2_PU_PB_EN_DOB_ECC_ERR_REG_DOB01_CE_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_EN_DOB_ECC_ERR_REG_DOB01_SUE = 8 ;
+static const uint8_t P9N2_PU_PB_EN_DOB_ECC_ERR_REG_DOB01_SUE_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_EN_DOB_ECC_ERR_REG_DOB23_UE = 12 ;
+static const uint8_t P9N2_PU_PB_EN_DOB_ECC_ERR_REG_DOB23_UE_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_EN_DOB_ECC_ERR_REG_DOB23_CE = 16 ;
+static const uint8_t P9N2_PU_PB_EN_DOB_ECC_ERR_REG_DOB23_CE_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_EN_DOB_ECC_ERR_REG_DOB23_SUE = 20 ;
+static const uint8_t P9N2_PU_PB_EN_DOB_ECC_ERR_REG_DOB23_SUE_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_EN_DOB_ECC_ERR_REG_DOB45_UE = 24 ;
+static const uint8_t P9N2_PU_PB_EN_DOB_ECC_ERR_REG_DOB45_UE_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_EN_DOB_ECC_ERR_REG_DOB45_CE = 28 ;
+static const uint8_t P9N2_PU_PB_EN_DOB_ECC_ERR_REG_DOB45_CE_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_EN_DOB_ECC_ERR_REG_DOB45_SUE = 32 ;
+static const uint8_t P9N2_PU_PB_EN_DOB_ECC_ERR_REG_DOB45_SUE_LEN = 4 ;
+
+static const uint8_t P9N2_PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB01_UE = 0 ;
+static const uint8_t P9N2_PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB01_UE_LEN = 4 ;
+static const uint8_t P9N2_PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB01_CE = 4 ;
+static const uint8_t P9N2_PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB01_CE_LEN = 4 ;
+static const uint8_t P9N2_PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB01_SUE = 8 ;
+static const uint8_t P9N2_PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB01_SUE_LEN = 4 ;
+static const uint8_t P9N2_PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB23_UE = 12 ;
+static const uint8_t P9N2_PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB23_UE_LEN = 4 ;
+static const uint8_t P9N2_PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB23_CE = 16 ;
+static const uint8_t P9N2_PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB23_CE_LEN = 4 ;
+static const uint8_t P9N2_PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB23_SUE = 20 ;
+static const uint8_t P9N2_PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB23_SUE_LEN = 4 ;
+static const uint8_t P9N2_PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB45_UE = 24 ;
+static const uint8_t P9N2_PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB45_UE_LEN = 4 ;
+static const uint8_t P9N2_PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB45_CE = 28 ;
+static const uint8_t P9N2_PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB45_CE_LEN = 4 ;
+static const uint8_t P9N2_PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB45_SUE = 32 ;
+static const uint8_t P9N2_PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB45_SUE_LEN = 4 ;
+static const uint8_t P9N2_PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB67_UE = 36 ;
+static const uint8_t P9N2_PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB67_UE_LEN = 4 ;
+static const uint8_t P9N2_PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB67_CE = 40 ;
+static const uint8_t P9N2_PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB67_CE_LEN = 4 ;
+static const uint8_t P9N2_PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB67_SUE = 44 ;
+static const uint8_t P9N2_PU_IOE_PB_EN_DOB_ECC_ERR_REG_DOB67_SUE_LEN = 4 ;
+
+static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR0_CONTROL_ERROR = 0 ;
+static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR0_ADDR_PERR = 1 ;
+static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR0_CC0_CREDITERR = 2 ;
+static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR0_CC1_CREDITERR = 3 ;
+static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR0_CC2_CREDITERR = 4 ;
+static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR0_CC3_CREDITERR = 5 ;
+static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR0_DAT_HI_PERR = 6 ;
+static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR0_DAT_LO_PERR = 7 ;
+static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR0_FRAME_CREDITERR = 8 ;
+static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR0_PC0_CREDITERR = 9 ;
+static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR0_PC1_CREDITERR = 10 ;
+static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR0_PRSP_PTYERR = 11 ;
+static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR0_TTAG_PERR = 12 ;
+static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR0_VC0_CREDITERR = 13 ;
+static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR0_VC1_CREDITERR = 14 ;
+static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR0_RTAG_PTYERR = 15 ;
+static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR1_CONTROL_ERROR = 16 ;
+static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR1_ADDR_PERR = 17 ;
+static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR1_CC0_CREDITERR = 18 ;
+static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR1_CC1_CREDITERR = 19 ;
+static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR1_CC2_CREDITERR = 20 ;
+static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR1_CC3_CREDITERR = 21 ;
+static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR1_DAT_HI_PERR = 22 ;
+static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR1_DAT_LO_PERR = 23 ;
+static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR1_FRAME_CREDITERR = 24 ;
+static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR1_PC0_CREDITERR = 25 ;
+static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR1_PC1_CREDITERR = 26 ;
+static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR1_PRSP_PTYERR = 27 ;
+static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR1_TTAG_PERR = 28 ;
+static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR1_VC0_CREDITERR = 29 ;
+static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR1_VC1_CREDITERR = 30 ;
+static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR1_RTAG_PTYERR = 31 ;
+static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR2_CONTROL_ERROR = 32 ;
+static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR2_ADDR_PERR = 33 ;
+static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR2_CC0_CREDITERR = 34 ;
+static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR2_CC1_CREDITERR = 35 ;
+static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR2_CC2_CREDITERR = 36 ;
+static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR2_CC3_CREDITERR = 37 ;
+static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR2_DAT_HI_PERR = 38 ;
+static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR2_DAT_LO_PERR = 39 ;
+static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR2_FRAME_CREDITERR = 40 ;
+static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR2_PC0_CREDITERR = 41 ;
+static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR2_PC1_CREDITERR = 42 ;
+static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR2_PRSP_PTYERR = 43 ;
+static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR2_TTAG_PERR = 44 ;
+static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR2_VC0_CREDITERR = 45 ;
+static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR2_VC1_CREDITERR = 46 ;
+static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR2_RTAG_PTYERR = 47 ;
+static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR3_CONTROL_ERROR = 48 ;
+static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR3_ADDR_PERR = 49 ;
+static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR3_CC0_CREDITERR = 50 ;
+static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR3_CC1_CREDITERR = 51 ;
+static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR3_CC2_CREDITERR = 52 ;
+static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR3_CC3_CREDITERR = 53 ;
+static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR3_DAT_HI_PERR = 54 ;
+static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR3_DAT_LO_PERR = 55 ;
+static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR3_FRAME_CREDITERR = 56 ;
+static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR3_PC0_CREDITERR = 57 ;
+static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR3_PC1_CREDITERR = 58 ;
+static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR3_PRSP_PTYERR = 59 ;
+static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR3_TTAG_PERR = 60 ;
+static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR3_VC0_CREDITERR = 61 ;
+static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR3_VC1_CREDITERR = 62 ;
+static const uint8_t P9N2_PU_PB_FM0123_ERR_FMR3_RTAG_PTYERR = 63 ;
+
+static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR0_CONTROL_ERROR = 0 ;
+static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR0_ADDR_PERR = 1 ;
+static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR0_CC0_CREDITERR = 2 ;
+static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR0_CC1_CREDITERR = 3 ;
+static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR0_CC2_CREDITERR = 4 ;
+static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR0_CC3_CREDITERR = 5 ;
+static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR0_DAT_HI_PERR = 6 ;
+static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR0_DAT_LO_PERR = 7 ;
+static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR0_FRAME_CREDITERR = 8 ;
+static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR0_PC0_CREDITERR = 9 ;
+static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR0_PC1_CREDITERR = 10 ;
+static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR0_PRSP_PTYERR = 11 ;
+static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR0_TTAG_PERR = 12 ;
+static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR0_VC0_CREDITERR = 13 ;
+static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR0_VC1_CREDITERR = 14 ;
+static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR0_RTAG_PTYERR = 15 ;
+static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR1_CONTROL_ERROR = 16 ;
+static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR1_ADDR_PERR = 17 ;
+static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR1_CC0_CREDITERR = 18 ;
+static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR1_CC1_CREDITERR = 19 ;
+static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR1_CC2_CREDITERR = 20 ;
+static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR1_CC3_CREDITERR = 21 ;
+static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR1_DAT_HI_PERR = 22 ;
+static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR1_DAT_LO_PERR = 23 ;
+static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR1_FRAME_CREDITERR = 24 ;
+static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR1_PC0_CREDITERR = 25 ;
+static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR1_PC1_CREDITERR = 26 ;
+static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR1_PRSP_PTYERR = 27 ;
+static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR1_TTAG_PERR = 28 ;
+static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR1_VC0_CREDITERR = 29 ;
+static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR1_VC1_CREDITERR = 30 ;
+static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR1_RTAG_PTYERR = 31 ;
+static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR2_CONTROL_ERROR = 32 ;
+static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR2_ADDR_PERR = 33 ;
+static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR2_CC0_CREDITERR = 34 ;
+static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR2_CC1_CREDITERR = 35 ;
+static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR2_CC2_CREDITERR = 36 ;
+static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR2_CC3_CREDITERR = 37 ;
+static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR2_DAT_HI_PERR = 38 ;
+static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR2_DAT_LO_PERR = 39 ;
+static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR2_FRAME_CREDITERR = 40 ;
+static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR2_PC0_CREDITERR = 41 ;
+static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR2_PC1_CREDITERR = 42 ;
+static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR2_PRSP_PTYERR = 43 ;
+static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR2_TTAG_PERR = 44 ;
+static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR2_VC0_CREDITERR = 45 ;
+static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR2_VC1_CREDITERR = 46 ;
+static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR2_RTAG_PTYERR = 47 ;
+static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR3_CONTROL_ERROR = 48 ;
+static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR3_ADDR_PERR = 49 ;
+static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR3_CC0_CREDITERR = 50 ;
+static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR3_CC1_CREDITERR = 51 ;
+static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR3_CC2_CREDITERR = 52 ;
+static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR3_CC3_CREDITERR = 53 ;
+static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR3_DAT_HI_PERR = 54 ;
+static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR3_DAT_LO_PERR = 55 ;
+static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR3_FRAME_CREDITERR = 56 ;
+static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR3_PC0_CREDITERR = 57 ;
+static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR3_PC1_CREDITERR = 58 ;
+static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR3_PRSP_PTYERR = 59 ;
+static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR3_TTAG_PERR = 60 ;
+static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR3_VC0_CREDITERR = 61 ;
+static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR3_VC1_CREDITERR = 62 ;
+static const uint8_t P9N2_PU_IOE_PB_FM0123_ERR_FMR3_RTAG_PTYERR = 63 ;
+
+static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR4_CONTROL_ERROR = 0 ;
+static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR4_ADDR_PERR = 1 ;
+static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR4_CC0_CREDITERR = 2 ;
+static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR4_CC1_CREDITERR = 3 ;
+static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR4_CC2_CREDITERR = 4 ;
+static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR4_CC3_CREDITERR = 5 ;
+static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR4_DAT_HI_PERR = 6 ;
+static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR4_DAT_LO_PERR = 7 ;
+static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR4_FRAME_CREDITERR = 8 ;
+static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR4_PC0_CREDITERR = 9 ;
+static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR4_PC1_CREDITERR = 10 ;
+static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR4_PRSP_PTYERR = 11 ;
+static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR4_TTAG_PERR = 12 ;
+static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR4_VC0_CREDITERR = 13 ;
+static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR4_VC1_CREDITERR = 14 ;
+static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR4_RTAG_PTYERR = 15 ;
+static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR5_CONTROL_ERROR = 16 ;
+static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR5_ADDR_PERR = 17 ;
+static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR5_CC0_CREDITERR = 18 ;
+static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR5_CC1_CREDITERR = 19 ;
+static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR5_CC2_CREDITERR = 20 ;
+static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR5_CC3_CREDITERR = 21 ;
+static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR5_DAT_HI_PERR = 22 ;
+static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR5_DAT_LO_PERR = 23 ;
+static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR5_FRAME_CREDITERR = 24 ;
+static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR5_PC0_CREDITERR = 25 ;
+static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR5_PC1_CREDITERR = 26 ;
+static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR5_PRSP_PTYERR = 27 ;
+static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR5_TTAG_PERR = 28 ;
+static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR5_VC0_CREDITERR = 29 ;
+static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR5_VC1_CREDITERR = 30 ;
+static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR5_RTAG_PTYERR = 31 ;
+static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR6_CONTROL_ERROR = 32 ;
+static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR6_ADDR_PERR = 33 ;
+static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR6_CC0_CREDITERR = 34 ;
+static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR6_CC1_CREDITERR = 35 ;
+static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR6_CC2_CREDITERR = 36 ;
+static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR6_CC3_CREDITERR = 37 ;
+static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR6_DAT_HI_PERR = 38 ;
+static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR6_DAT_LO_PERR = 39 ;
+static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR6_FRAME_CREDITERR = 40 ;
+static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR6_PC0_CREDITERR = 41 ;
+static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR6_PC1_CREDITERR = 42 ;
+static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR6_PRSP_PTYERR = 43 ;
+static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR6_TTAG_PERR = 44 ;
+static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR6_VC0_CREDITERR = 45 ;
+static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR6_VC1_CREDITERR = 46 ;
+static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR6_RTAG_PTYERR = 47 ;
+static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR7_CONTROL_ERROR = 48 ;
+static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR7_ADDR_PERR = 49 ;
+static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR7_CC0_CREDITERR = 50 ;
+static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR7_CC1_CREDITERR = 51 ;
+static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR7_CC2_CREDITERR = 52 ;
+static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR7_CC3_CREDITERR = 53 ;
+static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR7_DAT_HI_PERR = 54 ;
+static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR7_DAT_LO_PERR = 55 ;
+static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR7_FRAME_CREDITERR = 56 ;
+static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR7_PC0_CREDITERR = 57 ;
+static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR7_PC1_CREDITERR = 58 ;
+static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR7_PRSP_PTYERR = 59 ;
+static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR7_TTAG_PERR = 60 ;
+static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR7_VC0_CREDITERR = 61 ;
+static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR7_VC1_CREDITERR = 62 ;
+static const uint8_t P9N2_PU_IOE_PB_FM4567_ERR_FMR7_RTAG_PTYERR = 63 ;
+
+static const uint8_t P9N2_PU_PB_FM45_ERR_FMR4_CONTROL_ERROR = 0 ;
+static const uint8_t P9N2_PU_PB_FM45_ERR_FMR4_ADDR_PERR = 1 ;
+static const uint8_t P9N2_PU_PB_FM45_ERR_FMR4_CC0_CREDITERR = 2 ;
+static const uint8_t P9N2_PU_PB_FM45_ERR_FMR4_CC1_CREDITERR = 3 ;
+static const uint8_t P9N2_PU_PB_FM45_ERR_FMR4_CC2_CREDITERR = 4 ;
+static const uint8_t P9N2_PU_PB_FM45_ERR_FMR4_CC3_CREDITERR = 5 ;
+static const uint8_t P9N2_PU_PB_FM45_ERR_FMR4_DAT_HI_PERR = 6 ;
+static const uint8_t P9N2_PU_PB_FM45_ERR_FMR4_DAT_LO_PERR = 7 ;
+static const uint8_t P9N2_PU_PB_FM45_ERR_FMR4_FRAME_CREDITERR = 8 ;
+static const uint8_t P9N2_PU_PB_FM45_ERR_FMR4_PC0_CREDITERR = 9 ;
+static const uint8_t P9N2_PU_PB_FM45_ERR_FMR4_PC1_CREDITERR = 10 ;
+static const uint8_t P9N2_PU_PB_FM45_ERR_FMR4_PRSP_PTYERR = 11 ;
+static const uint8_t P9N2_PU_PB_FM45_ERR_FMR4_TTAG_PERR = 12 ;
+static const uint8_t P9N2_PU_PB_FM45_ERR_FMR4_VC0_CREDITERR = 13 ;
+static const uint8_t P9N2_PU_PB_FM45_ERR_FMR4_VC1_CREDITERR = 14 ;
+static const uint8_t P9N2_PU_PB_FM45_ERR_FMR4_RTAG_PTYERR = 15 ;
+static const uint8_t P9N2_PU_PB_FM45_ERR_FMR5_CONTROL_ERROR = 16 ;
+static const uint8_t P9N2_PU_PB_FM45_ERR_FMR5_ADDR_PERR = 17 ;
+static const uint8_t P9N2_PU_PB_FM45_ERR_FMR5_CC0_CREDITERR = 18 ;
+static const uint8_t P9N2_PU_PB_FM45_ERR_FMR5_CC1_CREDITERR = 19 ;
+static const uint8_t P9N2_PU_PB_FM45_ERR_FMR5_CC2_CREDITERR = 20 ;
+static const uint8_t P9N2_PU_PB_FM45_ERR_FMR5_CC3_CREDITERR = 21 ;
+static const uint8_t P9N2_PU_PB_FM45_ERR_FMR5_DAT_HI_PERR = 22 ;
+static const uint8_t P9N2_PU_PB_FM45_ERR_FMR5_DAT_LO_PERR = 23 ;
+static const uint8_t P9N2_PU_PB_FM45_ERR_FMR5_FRAME_CREDITERR = 24 ;
+static const uint8_t P9N2_PU_PB_FM45_ERR_FMR5_PC0_CREDITERR = 25 ;
+static const uint8_t P9N2_PU_PB_FM45_ERR_FMR5_PC1_CREDITERR = 26 ;
+static const uint8_t P9N2_PU_PB_FM45_ERR_FMR5_PRSP_PTYERR = 27 ;
+static const uint8_t P9N2_PU_PB_FM45_ERR_FMR5_TTAG_PERR = 28 ;
+static const uint8_t P9N2_PU_PB_FM45_ERR_FMR5_VC0_CREDITERR = 29 ;
+static const uint8_t P9N2_PU_PB_FM45_ERR_FMR5_VC1_CREDITERR = 30 ;
+static const uint8_t P9N2_PU_PB_FM45_ERR_FMR5_RTAG_PTYERR = 31 ;
+
+static const uint8_t P9N2_PU_PB_FP01_CFG_FP0_CREDIT_PRIORITY_4_NOT_8 = 0 ;
+static const uint8_t P9N2_PU_PB_FP01_CFG_FP0_DISABLE_GATHERING = 1 ;
+static const uint8_t P9N2_PU_PB_FP01_CFG_FP0_DISABLE_CMD_COMPRESSION = 2 ;
+static const uint8_t P9N2_PU_PB_FP01_CFG_FP0_DISABLE_PRSP_COMPRESSION = 3 ;
+static const uint8_t P9N2_PU_PB_FP01_CFG_FP0_LL_CREDIT_LO_LIMIT = 4 ;
+static const uint8_t P9N2_PU_PB_FP01_CFG_FP0_LL_CREDIT_LO_LIMIT_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_FP01_CFG_FP0_LL_CREDIT_HI_LIMIT = 12 ;
+static const uint8_t P9N2_PU_PB_FP01_CFG_FP0_LL_CREDIT_HI_LIMIT_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_FP01_CFG_FP0_FMR_DISABLE = 20 ;
+static const uint8_t P9N2_PU_PB_FP01_CFG_FP0_FMR_SPARE = 21 ;
+static const uint8_t P9N2_PU_PB_FP01_CFG_CMD_EXP_TIME = 22 ;
+static const uint8_t P9N2_PU_PB_FP01_CFG_CMD_EXP_TIME_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_FP01_CFG_FP0_RUN_AFTER_FRAME_ERROR = 24 ;
+static const uint8_t P9N2_PU_PB_FP01_CFG_FP0_PRS_DISABLE = 25 ;
+static const uint8_t P9N2_PU_PB_FP01_CFG_FP0_PRS_SPARE = 26 ;
+static const uint8_t P9N2_PU_PB_FP01_CFG_FP0_PRS_SPARE_LEN = 6 ;
+static const uint8_t P9N2_PU_PB_FP01_CFG_FP1_CREDIT_PRIORITY_4_NOT_8 = 32 ;
+static const uint8_t P9N2_PU_PB_FP01_CFG_FP1_DISABLE_GATHERING = 33 ;
+static const uint8_t P9N2_PU_PB_FP01_CFG_FP1_DISABLE_CMD_COMPRESSION = 34 ;
+static const uint8_t P9N2_PU_PB_FP01_CFG_FP1_DISABLE_PRSP_COMPRESSION = 35 ;
+static const uint8_t P9N2_PU_PB_FP01_CFG_FP1_LL_CREDIT_LO_LIMIT = 36 ;
+static const uint8_t P9N2_PU_PB_FP01_CFG_FP1_LL_CREDIT_LO_LIMIT_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_FP01_CFG_FP1_LL_CREDIT_HI_LIMIT = 44 ;
+static const uint8_t P9N2_PU_PB_FP01_CFG_FP1_LL_CREDIT_HI_LIMIT_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_FP01_CFG_FP1_FMR_DISABLE = 52 ;
+static const uint8_t P9N2_PU_PB_FP01_CFG_FP1_FMR_SPARE = 53 ;
+static const uint8_t P9N2_PU_PB_FP01_CFG_FP1_FMR_SPARE_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_FP01_CFG_FP1_RUN_AFTER_FRAME_ERROR = 56 ;
+static const uint8_t P9N2_PU_PB_FP01_CFG_FP1_PRS_DISABLE = 57 ;
+static const uint8_t P9N2_PU_PB_FP01_CFG_FP1_PRS_SPARE = 58 ;
+static const uint8_t P9N2_PU_PB_FP01_CFG_FP1_PRS_SPARE_LEN = 6 ;
+
+static const uint8_t P9N2_PU_IOE_PB_FP01_CFG_FP0_CREDIT_PRIORITY_4_NOT_8 = 0 ;
+static const uint8_t P9N2_PU_IOE_PB_FP01_CFG_FP0_DISABLE_GATHERING = 1 ;
+static const uint8_t P9N2_PU_IOE_PB_FP01_CFG_FP0_DISABLE_CMD_COMPRESSION = 2 ;
+static const uint8_t P9N2_PU_IOE_PB_FP01_CFG_FP0_DISABLE_PRSP_COMPRESSION = 3 ;
+static const uint8_t P9N2_PU_IOE_PB_FP01_CFG_FP0_LL_CREDIT_LO_LIMIT = 4 ;
+static const uint8_t P9N2_PU_IOE_PB_FP01_CFG_FP0_LL_CREDIT_LO_LIMIT_LEN = 8 ;
+static const uint8_t P9N2_PU_IOE_PB_FP01_CFG_FP0_LL_CREDIT_HI_LIMIT = 12 ;
+static const uint8_t P9N2_PU_IOE_PB_FP01_CFG_FP0_LL_CREDIT_HI_LIMIT_LEN = 8 ;
+static const uint8_t P9N2_PU_IOE_PB_FP01_CFG_FP0_FMR_DISABLE = 20 ;
+static const uint8_t P9N2_PU_IOE_PB_FP01_CFG_FP0_FMR_SPARE = 21 ;
+static const uint8_t P9N2_PU_IOE_PB_FP01_CFG_CMD_EXP_TIME = 22 ;
+static const uint8_t P9N2_PU_IOE_PB_FP01_CFG_CMD_EXP_TIME_LEN = 2 ;
+static const uint8_t P9N2_PU_IOE_PB_FP01_CFG_FP0_RUN_AFTER_FRAME_ERROR = 24 ;
+static const uint8_t P9N2_PU_IOE_PB_FP01_CFG_FP0_PRS_DISABLE = 25 ;
+static const uint8_t P9N2_PU_IOE_PB_FP01_CFG_FP0_PRS_SPARE = 26 ;
+static const uint8_t P9N2_PU_IOE_PB_FP01_CFG_FP0_PRS_SPARE_LEN = 6 ;
+static const uint8_t P9N2_PU_IOE_PB_FP01_CFG_FP1_CREDIT_PRIORITY_4_NOT_8 = 32 ;
+static const uint8_t P9N2_PU_IOE_PB_FP01_CFG_FP1_DISABLE_GATHERING = 33 ;
+static const uint8_t P9N2_PU_IOE_PB_FP01_CFG_FP1_DISABLE_CMD_COMPRESSION = 34 ;
+static const uint8_t P9N2_PU_IOE_PB_FP01_CFG_FP1_DISABLE_PRSP_COMPRESSION = 35 ;
+static const uint8_t P9N2_PU_IOE_PB_FP01_CFG_FP1_LL_CREDIT_LO_LIMIT = 36 ;
+static const uint8_t P9N2_PU_IOE_PB_FP01_CFG_FP1_LL_CREDIT_LO_LIMIT_LEN = 8 ;
+static const uint8_t P9N2_PU_IOE_PB_FP01_CFG_FP1_LL_CREDIT_HI_LIMIT = 44 ;
+static const uint8_t P9N2_PU_IOE_PB_FP01_CFG_FP1_LL_CREDIT_HI_LIMIT_LEN = 8 ;
+static const uint8_t P9N2_PU_IOE_PB_FP01_CFG_FP1_FMR_DISABLE = 52 ;
+static const uint8_t P9N2_PU_IOE_PB_FP01_CFG_FP1_FMR_SPARE = 53 ;
+static const uint8_t P9N2_PU_IOE_PB_FP01_CFG_FP1_FMR_SPARE_LEN = 3 ;
+static const uint8_t P9N2_PU_IOE_PB_FP01_CFG_FP1_RUN_AFTER_FRAME_ERROR = 56 ;
+static const uint8_t P9N2_PU_IOE_PB_FP01_CFG_FP1_PRS_DISABLE = 57 ;
+static const uint8_t P9N2_PU_IOE_PB_FP01_CFG_FP1_PRS_SPARE = 58 ;
+static const uint8_t P9N2_PU_IOE_PB_FP01_CFG_FP1_PRS_SPARE_LEN = 6 ;
+
+static const uint8_t P9N2_PU_PB_FP23_CFG_FP2_CREDIT_PRIORITY_4_NOT_8 = 0 ;
+static const uint8_t P9N2_PU_PB_FP23_CFG_FP2_DISABLE_GATHERING = 1 ;
+static const uint8_t P9N2_PU_PB_FP23_CFG_FP2_DISABLE_CMD_COMPRESSION = 2 ;
+static const uint8_t P9N2_PU_PB_FP23_CFG_FP2_DISABLE_PRSP_COMPRESSION = 3 ;
+static const uint8_t P9N2_PU_PB_FP23_CFG_FP2_LL_CREDIT_LO_LIMIT = 4 ;
+static const uint8_t P9N2_PU_PB_FP23_CFG_FP2_LL_CREDIT_LO_LIMIT_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_FP23_CFG_FP2_LL_CREDIT_HI_LIMIT = 12 ;
+static const uint8_t P9N2_PU_PB_FP23_CFG_FP2_LL_CREDIT_HI_LIMIT_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_FP23_CFG_FP2_FMR_DISABLE = 20 ;
+static const uint8_t P9N2_PU_PB_FP23_CFG_FP2_FMR_SPARE = 21 ;
+static const uint8_t P9N2_PU_PB_FP23_CFG_CMD_EXP_TIME = 22 ;
+static const uint8_t P9N2_PU_PB_FP23_CFG_CMD_EXP_TIME_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_FP23_CFG_FP2_RUN_AFTER_FRAME_ERROR = 24 ;
+static const uint8_t P9N2_PU_PB_FP23_CFG_FP2_PRS_DISABLE = 25 ;
+static const uint8_t P9N2_PU_PB_FP23_CFG_FP2_PRS_SPARE = 26 ;
+static const uint8_t P9N2_PU_PB_FP23_CFG_FP2_PRS_SPARE_LEN = 6 ;
+static const uint8_t P9N2_PU_PB_FP23_CFG_FP3_CREDIT_PRIORITY_4_NOT_8 = 32 ;
+static const uint8_t P9N2_PU_PB_FP23_CFG_FP3_DISABLE_GATHERING = 33 ;
+static const uint8_t P9N2_PU_PB_FP23_CFG_FP3_DISABLE_CMD_COMPRESSION = 34 ;
+static const uint8_t P9N2_PU_PB_FP23_CFG_FP3_DISABLE_PRSP_COMPRESSION = 35 ;
+static const uint8_t P9N2_PU_PB_FP23_CFG_FP3_LL_CREDIT_LO_LIMIT = 36 ;
+static const uint8_t P9N2_PU_PB_FP23_CFG_FP3_LL_CREDIT_LO_LIMIT_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_FP23_CFG_FP3_LL_CREDIT_HI_LIMIT = 44 ;
+static const uint8_t P9N2_PU_PB_FP23_CFG_FP3_LL_CREDIT_HI_LIMIT_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_FP23_CFG_FP3_FMR_DISABLE = 52 ;
+static const uint8_t P9N2_PU_PB_FP23_CFG_FP3_FMR_SPARE = 53 ;
+static const uint8_t P9N2_PU_PB_FP23_CFG_FP3_FMR_SPARE_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_FP23_CFG_FP3_RUN_AFTER_FRAME_ERROR = 56 ;
+static const uint8_t P9N2_PU_PB_FP23_CFG_FP3_PRS_DISABLE = 57 ;
+static const uint8_t P9N2_PU_PB_FP23_CFG_FP3_PRS_SPARE = 58 ;
+static const uint8_t P9N2_PU_PB_FP23_CFG_FP3_PRS_SPARE_LEN = 6 ;
+
+static const uint8_t P9N2_PU_IOE_PB_FP23_CFG_FP2_CREDIT_PRIORITY_4_NOT_8 = 0 ;
+static const uint8_t P9N2_PU_IOE_PB_FP23_CFG_FP2_DISABLE_GATHERING = 1 ;
+static const uint8_t P9N2_PU_IOE_PB_FP23_CFG_FP2_DISABLE_CMD_COMPRESSION = 2 ;
+static const uint8_t P9N2_PU_IOE_PB_FP23_CFG_FP2_DISABLE_PRSP_COMPRESSION = 3 ;
+static const uint8_t P9N2_PU_IOE_PB_FP23_CFG_FP2_LL_CREDIT_LO_LIMIT = 4 ;
+static const uint8_t P9N2_PU_IOE_PB_FP23_CFG_FP2_LL_CREDIT_LO_LIMIT_LEN = 8 ;
+static const uint8_t P9N2_PU_IOE_PB_FP23_CFG_FP2_LL_CREDIT_HI_LIMIT = 12 ;
+static const uint8_t P9N2_PU_IOE_PB_FP23_CFG_FP2_LL_CREDIT_HI_LIMIT_LEN = 8 ;
+static const uint8_t P9N2_PU_IOE_PB_FP23_CFG_FP2_FMR_DISABLE = 20 ;
+static const uint8_t P9N2_PU_IOE_PB_FP23_CFG_FP2_FMR_SPARE = 21 ;
+static const uint8_t P9N2_PU_IOE_PB_FP23_CFG_CMD_EXP_TIME = 22 ;
+static const uint8_t P9N2_PU_IOE_PB_FP23_CFG_CMD_EXP_TIME_LEN = 2 ;
+static const uint8_t P9N2_PU_IOE_PB_FP23_CFG_FP2_RUN_AFTER_FRAME_ERROR = 24 ;
+static const uint8_t P9N2_PU_IOE_PB_FP23_CFG_FP2_PRS_DISABLE = 25 ;
+static const uint8_t P9N2_PU_IOE_PB_FP23_CFG_FP2_PRS_SPARE = 26 ;
+static const uint8_t P9N2_PU_IOE_PB_FP23_CFG_FP2_PRS_SPARE_LEN = 6 ;
+static const uint8_t P9N2_PU_IOE_PB_FP23_CFG_FP3_CREDIT_PRIORITY_4_NOT_8 = 32 ;
+static const uint8_t P9N2_PU_IOE_PB_FP23_CFG_FP3_DISABLE_GATHERING = 33 ;
+static const uint8_t P9N2_PU_IOE_PB_FP23_CFG_FP3_DISABLE_CMD_COMPRESSION = 34 ;
+static const uint8_t P9N2_PU_IOE_PB_FP23_CFG_FP3_DISABLE_PRSP_COMPRESSION = 35 ;
+static const uint8_t P9N2_PU_IOE_PB_FP23_CFG_FP3_LL_CREDIT_LO_LIMIT = 36 ;
+static const uint8_t P9N2_PU_IOE_PB_FP23_CFG_FP3_LL_CREDIT_LO_LIMIT_LEN = 8 ;
+static const uint8_t P9N2_PU_IOE_PB_FP23_CFG_FP3_LL_CREDIT_HI_LIMIT = 44 ;
+static const uint8_t P9N2_PU_IOE_PB_FP23_CFG_FP3_LL_CREDIT_HI_LIMIT_LEN = 8 ;
+static const uint8_t P9N2_PU_IOE_PB_FP23_CFG_FP3_FMR_DISABLE = 52 ;
+static const uint8_t P9N2_PU_IOE_PB_FP23_CFG_FP3_FMR_SPARE = 53 ;
+static const uint8_t P9N2_PU_IOE_PB_FP23_CFG_FP3_FMR_SPARE_LEN = 3 ;
+static const uint8_t P9N2_PU_IOE_PB_FP23_CFG_FP3_RUN_AFTER_FRAME_ERROR = 56 ;
+static const uint8_t P9N2_PU_IOE_PB_FP23_CFG_FP3_PRS_DISABLE = 57 ;
+static const uint8_t P9N2_PU_IOE_PB_FP23_CFG_FP3_PRS_SPARE = 58 ;
+static const uint8_t P9N2_PU_IOE_PB_FP23_CFG_FP3_PRS_SPARE_LEN = 6 ;
+
+static const uint8_t P9N2_PU_PB_FP45_CFG_FP4_CREDIT_PRIORITY_4_NOT_8 = 0 ;
+static const uint8_t P9N2_PU_PB_FP45_CFG_FP4_DISABLE_GATHERING = 1 ;
+static const uint8_t P9N2_PU_PB_FP45_CFG_FP4_DISABLE_CMD_COMPRESSION = 2 ;
+static const uint8_t P9N2_PU_PB_FP45_CFG_FP4_DISABLE_PRSP_COMPRESSION = 3 ;
+static const uint8_t P9N2_PU_PB_FP45_CFG_FP4_LL_CREDIT_LO_LIMIT = 4 ;
+static const uint8_t P9N2_PU_PB_FP45_CFG_FP4_LL_CREDIT_LO_LIMIT_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_FP45_CFG_FP4_LL_CREDIT_HI_LIMIT = 12 ;
+static const uint8_t P9N2_PU_PB_FP45_CFG_FP4_LL_CREDIT_HI_LIMIT_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_FP45_CFG_FP4_FMR_DISABLE = 20 ;
+static const uint8_t P9N2_PU_PB_FP45_CFG_FP4_FMR_SPARE = 21 ;
+static const uint8_t P9N2_PU_PB_FP45_CFG_CMD_EXP_TIME = 22 ;
+static const uint8_t P9N2_PU_PB_FP45_CFG_CMD_EXP_TIME_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_FP45_CFG_FP4_RUN_AFTER_FRAME_ERROR = 24 ;
+static const uint8_t P9N2_PU_PB_FP45_CFG_FP4_PRS_DISABLE = 25 ;
+static const uint8_t P9N2_PU_PB_FP45_CFG_FP4_PRS_SPARE = 26 ;
+static const uint8_t P9N2_PU_PB_FP45_CFG_FP4_PRS_SPARE_LEN = 6 ;
+static const uint8_t P9N2_PU_PB_FP45_CFG_FP5_CREDIT_PRIORITY_4_NOT_8 = 32 ;
+static const uint8_t P9N2_PU_PB_FP45_CFG_FP5_DISABLE_GATHERING = 33 ;
+static const uint8_t P9N2_PU_PB_FP45_CFG_FP5_DISABLE_CMD_COMPRESSION = 34 ;
+static const uint8_t P9N2_PU_PB_FP45_CFG_FP5_DISABLE_PRSP_COMPRESSION = 35 ;
+static const uint8_t P9N2_PU_PB_FP45_CFG_FP5_LL_CREDIT_LO_LIMIT = 36 ;
+static const uint8_t P9N2_PU_PB_FP45_CFG_FP5_LL_CREDIT_LO_LIMIT_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_FP45_CFG_FP5_LL_CREDIT_HI_LIMIT = 44 ;
+static const uint8_t P9N2_PU_PB_FP45_CFG_FP5_LL_CREDIT_HI_LIMIT_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_FP45_CFG_FP5_FMR_DISABLE = 52 ;
+static const uint8_t P9N2_PU_PB_FP45_CFG_FP5_FMR_SPARE = 53 ;
+static const uint8_t P9N2_PU_PB_FP45_CFG_FP5_FMR_SPARE_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_FP45_CFG_FP5_RUN_AFTER_FRAME_ERROR = 56 ;
+static const uint8_t P9N2_PU_PB_FP45_CFG_FP5_PRS_DISABLE = 57 ;
+static const uint8_t P9N2_PU_PB_FP45_CFG_FP5_PRS_SPARE = 58 ;
+static const uint8_t P9N2_PU_PB_FP45_CFG_FP5_PRS_SPARE_LEN = 6 ;
+
+static const uint8_t P9N2_PU_IOE_PB_FP45_CFG_FP4_CREDIT_PRIORITY_4_NOT_8 = 0 ;
+static const uint8_t P9N2_PU_IOE_PB_FP45_CFG_FP4_DISABLE_GATHERING = 1 ;
+static const uint8_t P9N2_PU_IOE_PB_FP45_CFG_FP4_DISABLE_CMD_COMPRESSION = 2 ;
+static const uint8_t P9N2_PU_IOE_PB_FP45_CFG_FP4_DISABLE_PRSP_COMPRESSION = 3 ;
+static const uint8_t P9N2_PU_IOE_PB_FP45_CFG_FP4_LL_CREDIT_LO_LIMIT = 4 ;
+static const uint8_t P9N2_PU_IOE_PB_FP45_CFG_FP4_LL_CREDIT_LO_LIMIT_LEN = 8 ;
+static const uint8_t P9N2_PU_IOE_PB_FP45_CFG_FP4_LL_CREDIT_HI_LIMIT = 12 ;
+static const uint8_t P9N2_PU_IOE_PB_FP45_CFG_FP4_LL_CREDIT_HI_LIMIT_LEN = 8 ;
+static const uint8_t P9N2_PU_IOE_PB_FP45_CFG_FP4_FMR_DISABLE = 20 ;
+static const uint8_t P9N2_PU_IOE_PB_FP45_CFG_FP4_FMR_SPARE = 21 ;
+static const uint8_t P9N2_PU_IOE_PB_FP45_CFG_CMD_EXP_TIME = 22 ;
+static const uint8_t P9N2_PU_IOE_PB_FP45_CFG_CMD_EXP_TIME_LEN = 2 ;
+static const uint8_t P9N2_PU_IOE_PB_FP45_CFG_FP4_RUN_AFTER_FRAME_ERROR = 24 ;
+static const uint8_t P9N2_PU_IOE_PB_FP45_CFG_FP4_PRS_DISABLE = 25 ;
+static const uint8_t P9N2_PU_IOE_PB_FP45_CFG_FP4_PRS_SPARE = 26 ;
+static const uint8_t P9N2_PU_IOE_PB_FP45_CFG_FP4_PRS_SPARE_LEN = 6 ;
+static const uint8_t P9N2_PU_IOE_PB_FP45_CFG_FP5_CREDIT_PRIORITY_4_NOT_8 = 32 ;
+static const uint8_t P9N2_PU_IOE_PB_FP45_CFG_FP5_DISABLE_GATHERING = 33 ;
+static const uint8_t P9N2_PU_IOE_PB_FP45_CFG_FP5_DISABLE_CMD_COMPRESSION = 34 ;
+static const uint8_t P9N2_PU_IOE_PB_FP45_CFG_FP5_DISABLE_PRSP_COMPRESSION = 35 ;
+static const uint8_t P9N2_PU_IOE_PB_FP45_CFG_FP5_LL_CREDIT_LO_LIMIT = 36 ;
+static const uint8_t P9N2_PU_IOE_PB_FP45_CFG_FP5_LL_CREDIT_LO_LIMIT_LEN = 8 ;
+static const uint8_t P9N2_PU_IOE_PB_FP45_CFG_FP5_LL_CREDIT_HI_LIMIT = 44 ;
+static const uint8_t P9N2_PU_IOE_PB_FP45_CFG_FP5_LL_CREDIT_HI_LIMIT_LEN = 8 ;
+static const uint8_t P9N2_PU_IOE_PB_FP45_CFG_FP5_FMR_DISABLE = 52 ;
+static const uint8_t P9N2_PU_IOE_PB_FP45_CFG_FP5_FMR_SPARE = 53 ;
+static const uint8_t P9N2_PU_IOE_PB_FP45_CFG_FP5_FMR_SPARE_LEN = 3 ;
+static const uint8_t P9N2_PU_IOE_PB_FP45_CFG_FP5_RUN_AFTER_FRAME_ERROR = 56 ;
+static const uint8_t P9N2_PU_IOE_PB_FP45_CFG_FP5_PRS_DISABLE = 57 ;
+static const uint8_t P9N2_PU_IOE_PB_FP45_CFG_FP5_PRS_SPARE = 58 ;
+static const uint8_t P9N2_PU_IOE_PB_FP45_CFG_FP5_PRS_SPARE_LEN = 6 ;
+
+static const uint8_t P9N2_PU_IOE_PB_FP67_CFG_FP6_CREDIT_PRIORITY_4_NOT_8 = 0 ;
+static const uint8_t P9N2_PU_IOE_PB_FP67_CFG_FP6_DISABLE_GATHERING = 1 ;
+static const uint8_t P9N2_PU_IOE_PB_FP67_CFG_FP6_DISABLE_CMD_COMPRESSION = 2 ;
+static const uint8_t P9N2_PU_IOE_PB_FP67_CFG_FP6_DISABLE_PRSP_COMPRESSION = 3 ;
+static const uint8_t P9N2_PU_IOE_PB_FP67_CFG_FP6_LL_CREDIT_LO_LIMIT = 4 ;
+static const uint8_t P9N2_PU_IOE_PB_FP67_CFG_FP6_LL_CREDIT_LO_LIMIT_LEN = 8 ;
+static const uint8_t P9N2_PU_IOE_PB_FP67_CFG_FP6_LL_CREDIT_HI_LIMIT = 12 ;
+static const uint8_t P9N2_PU_IOE_PB_FP67_CFG_FP6_LL_CREDIT_HI_LIMIT_LEN = 8 ;
+static const uint8_t P9N2_PU_IOE_PB_FP67_CFG_FP6_FMR_DISABLE = 20 ;
+static const uint8_t P9N2_PU_IOE_PB_FP67_CFG_FP6_FMR_SPARE = 21 ;
+static const uint8_t P9N2_PU_IOE_PB_FP67_CFG_CMD_EXP_TIME = 22 ;
+static const uint8_t P9N2_PU_IOE_PB_FP67_CFG_CMD_EXP_TIME_LEN = 2 ;
+static const uint8_t P9N2_PU_IOE_PB_FP67_CFG_FP6_RUN_AFTER_FRAME_ERROR = 24 ;
+static const uint8_t P9N2_PU_IOE_PB_FP67_CFG_FP6_PRS_DISABLE = 25 ;
+static const uint8_t P9N2_PU_IOE_PB_FP67_CFG_FP6_PRS_SPARE = 26 ;
+static const uint8_t P9N2_PU_IOE_PB_FP67_CFG_FP6_PRS_SPARE_LEN = 6 ;
+static const uint8_t P9N2_PU_IOE_PB_FP67_CFG_FP7_CREDIT_PRIORITY_4_NOT_8 = 32 ;
+static const uint8_t P9N2_PU_IOE_PB_FP67_CFG_FP7_DISABLE_GATHERING = 33 ;
+static const uint8_t P9N2_PU_IOE_PB_FP67_CFG_FP7_DISABLE_CMD_COMPRESSION = 34 ;
+static const uint8_t P9N2_PU_IOE_PB_FP67_CFG_FP7_DISABLE_PRSP_COMPRESSION = 35 ;
+static const uint8_t P9N2_PU_IOE_PB_FP67_CFG_FP7_LL_CREDIT_LO_LIMIT = 36 ;
+static const uint8_t P9N2_PU_IOE_PB_FP67_CFG_FP7_LL_CREDIT_LO_LIMIT_LEN = 8 ;
+static const uint8_t P9N2_PU_IOE_PB_FP67_CFG_FP7_LL_CREDIT_HI_LIMIT = 44 ;
+static const uint8_t P9N2_PU_IOE_PB_FP67_CFG_FP7_LL_CREDIT_HI_LIMIT_LEN = 8 ;
+static const uint8_t P9N2_PU_IOE_PB_FP67_CFG_FP7_FMR_DISABLE = 52 ;
+static const uint8_t P9N2_PU_IOE_PB_FP67_CFG_FP7_FMR_SPARE = 53 ;
+static const uint8_t P9N2_PU_IOE_PB_FP67_CFG_FP7_FMR_SPARE_LEN = 3 ;
+static const uint8_t P9N2_PU_IOE_PB_FP67_CFG_FP7_RUN_AFTER_FRAME_ERROR = 56 ;
+static const uint8_t P9N2_PU_IOE_PB_FP67_CFG_FP7_PRS_DISABLE = 57 ;
+static const uint8_t P9N2_PU_IOE_PB_FP67_CFG_FP7_PRS_SPARE = 58 ;
+static const uint8_t P9N2_PU_IOE_PB_FP67_CFG_FP7_PRS_SPARE_LEN = 6 ;
+
+static const uint8_t P9N2_PU_PB_IOE_FIR_ACTION0_REG_ACTION0 = 0 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_ACTION0_REG_ACTION0_LEN = 64 ;
+
+static const uint8_t P9N2_PU_PB_IOE_FIR_ACTION1_REG_ACTION1 = 0 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_ACTION1_REG_ACTION1_LEN = 64 ;
+
+static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_FMR00_TRAINED = 0 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_FMR01_TRAINED = 1 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_FMR02_TRAINED = 2 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_FMR03_TRAINED = 3 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_FMR04_TRAINED = 4 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_FMR05_TRAINED = 5 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_RSV6 = 6 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_RSV7 = 7 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_DOB01_UE = 8 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_DOB01_CE = 9 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_DOB01_SUE = 10 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_DOB23_UE = 11 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_DOB23_CE = 12 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_DOB23_SUE = 13 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_DOB45_UE = 14 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_DOB45_CE = 15 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_DOB45_SUE = 16 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_RSV17 = 17 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_RSV18 = 18 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_RSV19 = 19 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_FRAMER00_ATTN = 20 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_FRAMER01_ATTN = 21 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_FRAMER02_ATTN = 22 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_FRAMER03_ATTN = 23 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_FRAMER04_ATTN = 24 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_FRAMER05_ATTN = 25 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_RSV26 = 26 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_RSV27 = 27 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_PARSER00_ATTN = 28 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_PARSER01_ATTN = 29 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_PARSER02_ATTN = 30 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_PARSER03_ATTN = 31 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_PARSER04_ATTN = 32 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_PARSER05_ATTN = 33 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_RSV34 = 34 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_RSV35 = 35 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_MB00_SPATTN = 36 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_MB01_SPATTN = 37 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_MB10_SPATTN = 38 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_MB11_SPATTN = 39 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_MB20_SPATTN = 40 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_MB21_SPATTN = 41 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_MB30_SPATTN = 42 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_MB31_SPATTN = 43 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_MB40_SPATTN = 44 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_MB41_SPATTN = 45 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_MB50_SPATTN = 46 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_MB51_SPATTN = 47 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_DOB01_ERR = 52 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_DOB23_ERR = 53 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_DOB45_ERR = 54 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_DIB01_ERR = 56 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_DIB23_ERR = 57 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_DIB45_ERR = 58 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_SCOM_ERR_DUP = 62 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_MASK_REG_SCOM_ERR = 63 ;
+
+static const uint8_t P9N2_PU_PB_IOE_FIR_REG_FMR00_TRAINED = 0 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_REG_FMR01_TRAINED = 1 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_REG_FMR02_TRAINED = 2 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_REG_FMR03_TRAINED = 3 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_REG_FMR04_TRAINED = 4 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_REG_FMR05_TRAINED = 5 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_REG_RSV6 = 6 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_REG_RSV7 = 7 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_REG_DOB01_UE = 8 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_REG_DOB01_CE = 9 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_REG_DOB01_SUE = 10 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_REG_DOB23_UE = 11 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_REG_DOB23_CE = 12 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_REG_DOB23_SUE = 13 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_REG_DOB45_UE = 14 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_REG_DOB45_CE = 15 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_REG_DOB45_SUE = 16 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_REG_RSV17 = 17 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_REG_RSV18 = 18 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_REG_RSV19 = 19 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_REG_FRAMER00_ATTN = 20 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_REG_FRAMER01_ATTN = 21 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_REG_FRAMER02_ATTN = 22 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_REG_FRAMER03_ATTN = 23 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_REG_FRAMER04_ATTN = 24 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_REG_FRAMER05_ATTN = 25 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_REG_RSV26 = 26 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_REG_RSV27 = 27 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_REG_PARSER00_ATTN = 28 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_REG_PARSER01_ATTN = 29 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_REG_PARSER02_ATTN = 30 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_REG_PARSER03_ATTN = 31 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_REG_PARSER04_ATTN = 32 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_REG_PARSER05_ATTN = 33 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_REG_RSV34 = 34 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_REG_RSV35 = 35 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_REG_MB00_SPATTN = 36 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_REG_MB01_SPATTN = 37 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_REG_MB10_SPATTN = 38 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_REG_MB11_SPATTN = 39 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_REG_MB20_SPATTN = 40 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_REG_MB21_SPATTN = 41 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_REG_MB30_SPATTN = 42 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_REG_MB31_SPATTN = 43 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_REG_MB40_SPATTN = 44 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_REG_MB41_SPATTN = 45 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_REG_MB50_SPATTN = 46 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_REG_MB51_SPATTN = 47 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_REG_DOB01_ERR = 52 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_REG_DOB23_ERR = 53 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_REG_DOB45_ERR = 54 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_REG_DIB01_ERR = 56 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_REG_DIB23_ERR = 57 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_REG_DIB45_ERR = 58 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_REG_SCOM_ERR_DUP = 62 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_REG_SCOM_ERR = 63 ;
+
+static const uint8_t P9N2_PU_PB_IOE_FIR_WOF_REG_WOF = 0 ;
+static const uint8_t P9N2_PU_PB_IOE_FIR_WOF_REG_WOF_LEN = 64 ;
+
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_ACTION0_REG_ACTION0 = 0 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_ACTION0_REG_ACTION0_LEN = 64 ;
+
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_ACTION1_REG_ACTION1 = 0 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_ACTION1_REG_ACTION1_LEN = 64 ;
+
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_FMR00_TRAINED = 0 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_FMR01_TRAINED = 1 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_FMR02_TRAINED = 2 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_FMR03_TRAINED = 3 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_FMR04_TRAINED = 4 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_FMR05_TRAINED = 5 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_FMR06_TRAINED = 6 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_FMR07_TRAINED = 7 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_DOB01_UE = 8 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_DOB01_CE = 9 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_DOB01_SUE = 10 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_DOB23_UE = 11 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_DOB23_CE = 12 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_DOB23_SUE = 13 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_DOB45_UE = 14 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_DOB45_CE = 15 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_DOB45_SUE = 16 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_DOB67_UE = 17 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_DOB67_CE = 18 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_DOB67_SUE = 19 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_FRAMER00_ATTN = 20 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_FRAMER01_ATTN = 21 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_FRAMER02_ATTN = 22 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_FRAMER03_ATTN = 23 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_FRAMER04_ATTN = 24 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_FRAMER05_ATTN = 25 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_FRAMER06_ATTN = 26 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_FRAMER07_ATTN = 27 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_PARSER00_ATTN = 28 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_PARSER01_ATTN = 29 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_PARSER02_ATTN = 30 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_PARSER03_ATTN = 31 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_PARSER04_ATTN = 32 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_PARSER05_ATTN = 33 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_PARSER06_ATTN = 34 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_PARSER07_ATTN = 35 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_MB00_SPATTN = 36 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_MB01_SPATTN = 37 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_MB10_SPATTN = 38 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_MB11_SPATTN = 39 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_MB20_SPATTN = 40 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_MB21_SPATTN = 41 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_MB30_SPATTN = 42 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_MB31_SPATTN = 43 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_MB40_SPATTN = 44 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_MB41_SPATTN = 45 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_MB50_SPATTN = 46 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_MB51_SPATTN = 47 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_MB60_SPATTN = 48 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_MB61_SPATTN = 49 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_MB70_SPATTN = 50 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_MB71_SPATTN = 51 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_DOB01_ERR = 52 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_DOB23_ERR = 53 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_DOB45_ERR = 54 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_DOB67_ERR = 55 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_DIB01_ERR = 56 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_DIB23_ERR = 57 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_DIB45_ERR = 58 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_DIB67_ERR = 59 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_SCOM_ERR_DUP = 62 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_MASK_REG_SCOM_ERR = 63 ;
+
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_FMR00_TRAINED = 0 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_FMR01_TRAINED = 1 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_FMR02_TRAINED = 2 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_FMR03_TRAINED = 3 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_FMR04_TRAINED = 4 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_FMR05_TRAINED = 5 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_FMR06_TRAINED = 6 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_FMR07_TRAINED = 7 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_DOB01_UE = 8 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_DOB01_CE = 9 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_DOB01_SUE = 10 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_DOB23_UE = 11 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_DOB23_CE = 12 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_DOB23_SUE = 13 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_DOB45_UE = 14 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_DOB45_CE = 15 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_DOB45_SUE = 16 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_DOB67_UE = 17 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_DOB67_CE = 18 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_DOB67_SUE = 19 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_FRAMER00_ATTN = 20 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_FRAMER01_ATTN = 21 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_FRAMER02_ATTN = 22 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_FRAMER03_ATTN = 23 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_FRAMER04_ATTN = 24 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_FRAMER05_ATTN = 25 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_FRAMER06_ATTN = 26 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_FRAMER07_ATTN = 27 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_PARSER00_ATTN = 28 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_PARSER01_ATTN = 29 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_PARSER02_ATTN = 30 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_PARSER03_ATTN = 31 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_PARSER04_ATTN = 32 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_PARSER05_ATTN = 33 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_PARSER06_ATTN = 34 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_PARSER07_ATTN = 35 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_MB00_SPATTN = 36 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_MB01_SPATTN = 37 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_MB10_SPATTN = 38 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_MB11_SPATTN = 39 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_MB20_SPATTN = 40 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_MB21_SPATTN = 41 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_MB30_SPATTN = 42 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_MB31_SPATTN = 43 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_MB40_SPATTN = 44 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_MB41_SPATTN = 45 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_MB50_SPATTN = 46 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_MB51_SPATTN = 47 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_MB60_SPATTN = 48 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_MB61_SPATTN = 49 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_MB70_SPATTN = 50 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_MB71_SPATTN = 51 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_DOB01_ERR = 52 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_DOB23_ERR = 53 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_DOB45_ERR = 54 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_DOB67_ERR = 55 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_DIB01_ERR = 56 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_DIB23_ERR = 57 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_DIB45_ERR = 58 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_DIB67_ERR = 59 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_SCOM_ERR_DUP = 62 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_REG_SCOM_ERR = 63 ;
+
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_WOF_REG_WOF = 0 ;
+static const uint8_t P9N2_PU_IOE_PB_IOO_FIR_WOF_REG_WOF_LEN = 64 ;
+
+static const uint8_t P9N2_PU_PB_MISC_CFG_IOE01_IS_LOGICAL_PAIR = 0 ;
+static const uint8_t P9N2_PU_PB_MISC_CFG_IOE23_IS_LOGICAL_PAIR = 1 ;
+static const uint8_t P9N2_PU_PB_MISC_CFG_IOE45_IS_LOGICAL_PAIR = 2 ;
+static const uint8_t P9N2_PU_PB_MISC_CFG_SPARE3 = 3 ;
+static const uint8_t P9N2_PU_PB_MISC_CFG_SCOM_LINK01_RESET_KEEPER = 4 ;
+static const uint8_t P9N2_PU_PB_MISC_CFG_SCOM_LINK23_RESET_KEEPER = 5 ;
+static const uint8_t P9N2_PU_PB_MISC_CFG_SCOM_LINK45_RESET_KEEPER = 6 ;
+static const uint8_t P9N2_PU_PB_MISC_CFG_SPARE7 = 7 ;
+static const uint8_t P9N2_PU_PB_MISC_CFG_SPARE8 = 8 ;
+static const uint8_t P9N2_PU_PB_MISC_CFG_SPARE9 = 9 ;
+static const uint8_t P9N2_PU_PB_MISC_CFG_SPARE10 = 10 ;
+static const uint8_t P9N2_PU_PB_MISC_CFG_SPARE11 = 11 ;
+static const uint8_t P9N2_PU_PB_MISC_CFG_LINK_AVP_MODE = 12 ;
+static const uint8_t P9N2_PU_PB_MISC_CFG_SPARE13 = 13 ;
+static const uint8_t P9N2_PU_PB_MISC_CFG_SPARE14 = 14 ;
+static const uint8_t P9N2_PU_PB_MISC_CFG_SPARE15 = 15 ;
+
+static const uint8_t P9N2_PU_IOE_PB_MISC_CFG_IOO01_IS_LOGICAL_PAIR = 0 ;
+static const uint8_t P9N2_PU_IOE_PB_MISC_CFG_IOO23_IS_LOGICAL_PAIR = 1 ;
+static const uint8_t P9N2_PU_IOE_PB_MISC_CFG_IOO45_IS_LOGICAL_PAIR = 2 ;
+static const uint8_t P9N2_PU_IOE_PB_MISC_CFG_IOO67_IS_LOGICAL_PAIR = 3 ;
+static const uint8_t P9N2_PU_IOE_PB_MISC_CFG_SCOM_LINK01_RESET_KEEPER = 4 ;
+static const uint8_t P9N2_PU_IOE_PB_MISC_CFG_SCOM_LINK23_RESET_KEEPER = 5 ;
+static const uint8_t P9N2_PU_IOE_PB_MISC_CFG_SCOM_LINK45_RESET_KEEPER = 6 ;
+static const uint8_t P9N2_PU_IOE_PB_MISC_CFG_SCOM_LINK67_RESET_KEEPER = 7 ;
+static const uint8_t P9N2_PU_IOE_PB_MISC_CFG_LINKS01_TOD_ENABLE = 8 ;
+static const uint8_t P9N2_PU_IOE_PB_MISC_CFG_LINKS23_TOD_ENABLE = 9 ;
+static const uint8_t P9N2_PU_IOE_PB_MISC_CFG_LINKS45_TOD_ENABLE = 10 ;
+static const uint8_t P9N2_PU_IOE_PB_MISC_CFG_LINKS67_TOD_ENABLE = 11 ;
+static const uint8_t P9N2_PU_IOE_PB_MISC_CFG_LINK_AVP_MODE = 12 ;
+static const uint8_t P9N2_PU_IOE_PB_MISC_CFG_SEL_03_NPU_NOT = 13 ;
+static const uint8_t P9N2_PU_IOE_PB_MISC_CFG_SEL_04_NPU_NOT = 14 ;
+static const uint8_t P9N2_PU_IOE_PB_MISC_CFG_SEL_05_NPU_NOT = 15 ;
+static const uint8_t P9N2_PU_IOE_PB_MISC_CFG_SPARE = 16 ;
+static const uint8_t P9N2_PU_IOE_PB_MISC_CFG_SPARE_LEN = 4 ;
+
+static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_01_CFG_REG_LINK0_DOB_LIMIT = 1 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_01_CFG_REG_LINK0_DOB_LIMIT_LEN = 7 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_01_CFG_REG_LINK0_DOB_VC0_LIMIT = 9 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_01_CFG_REG_LINK0_DOB_VC0_LIMIT_LEN = 7 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_01_CFG_REG_LINK0_DOB_VC1_LIMIT = 17 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_01_CFG_REG_LINK0_DOB_VC1_LIMIT_LEN = 7 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_01_CFG_REG_LINK01_DIB_VC_LIMIT = 24 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_01_CFG_REG_LINK01_DIB_VC_LIMIT_LEN = 5 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_01_CFG_REG_LINK1_DOB_LIMIT = 33 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_01_CFG_REG_LINK1_DOB_LIMIT_LEN = 7 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_01_CFG_REG_LINK1_DOB_VC0_LIMIT = 41 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_01_CFG_REG_LINK1_DOB_VC0_LIMIT_LEN = 7 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_01_CFG_REG_LINK1_DOB_VC1_LIMIT = 49 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_01_CFG_REG_LINK1_DOB_VC1_LIMIT_LEN = 7 ;
+
+static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_23_CFG_REG_LINK2_DOB_LIMIT = 1 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_23_CFG_REG_LINK2_DOB_LIMIT_LEN = 7 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_23_CFG_REG_LINK2_DOB_VC0_LIMIT = 9 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_23_CFG_REG_LINK2_DOB_VC0_LIMIT_LEN = 7 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_23_CFG_REG_LINK2_DOB_VC1_LIMIT = 17 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_23_CFG_REG_LINK2_DOB_VC1_LIMIT_LEN = 7 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_23_CFG_REG_LINK23_DIB_VC_LIMIT = 24 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_23_CFG_REG_LINK23_DIB_VC_LIMIT_LEN = 5 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_23_CFG_REG_LINK3_DOB_LIMIT = 33 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_23_CFG_REG_LINK3_DOB_LIMIT_LEN = 7 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_23_CFG_REG_LINK3_DOB_VC0_LIMIT = 41 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_23_CFG_REG_LINK3_DOB_VC0_LIMIT_LEN = 7 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_23_CFG_REG_LINK3_DOB_VC1_LIMIT = 49 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_23_CFG_REG_LINK3_DOB_VC1_LIMIT_LEN = 7 ;
+
+static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_45_CFG_REG_LINK4_DOB_LIMIT = 1 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_45_CFG_REG_LINK4_DOB_LIMIT_LEN = 7 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_45_CFG_REG_LINK4_DOB_VC0_LIMIT = 9 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_45_CFG_REG_LINK4_DOB_VC0_LIMIT_LEN = 7 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_45_CFG_REG_LINK4_DOB_VC1_LIMIT = 17 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_45_CFG_REG_LINK4_DOB_VC1_LIMIT_LEN = 7 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_45_CFG_REG_LINK45_DIB_VC_LIMIT = 24 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_45_CFG_REG_LINK45_DIB_VC_LIMIT_LEN = 5 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_45_CFG_REG_LINK5_DOB_LIMIT = 33 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_45_CFG_REG_LINK5_DOB_LIMIT_LEN = 7 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_45_CFG_REG_LINK5_DOB_VC0_LIMIT = 41 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_45_CFG_REG_LINK5_DOB_VC0_LIMIT_LEN = 7 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_45_CFG_REG_LINK5_DOB_VC1_LIMIT = 49 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_45_CFG_REG_LINK5_DOB_VC1_LIMIT_LEN = 7 ;
+
+static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_67_CFG_REG_LINK6_DOB_LIMIT = 1 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_67_CFG_REG_LINK6_DOB_LIMIT_LEN = 7 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_67_CFG_REG_LINK6_DOB_VC0_LIMIT = 9 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_67_CFG_REG_LINK6_DOB_VC0_LIMIT_LEN = 7 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_67_CFG_REG_LINK6_DOB_VC1_LIMIT = 17 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_67_CFG_REG_LINK6_DOB_VC1_LIMIT_LEN = 7 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_67_CFG_REG_LINK67_DIB_VC_LIMIT = 24 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_67_CFG_REG_LINK67_DIB_VC_LIMIT_LEN = 5 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_67_CFG_REG_LINK7_DOB_LIMIT = 33 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_67_CFG_REG_LINK7_DOB_LIMIT_LEN = 7 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_67_CFG_REG_LINK7_DOB_VC0_LIMIT = 41 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_67_CFG_REG_LINK7_DOB_VC0_LIMIT_LEN = 7 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_67_CFG_REG_LINK7_DOB_VC1_LIMIT = 49 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_DATA_67_CFG_REG_LINK7_DOB_VC1_LIMIT_LEN = 7 ;
+
+static const uint8_t P9N2_PU_IOE_PB_OLINK_DLY_0123_REG_FMR0_LINK_DELAY = 4 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_DLY_0123_REG_FMR0_LINK_DELAY_LEN = 12 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_DLY_0123_REG_FMR1_LINK_DELAY = 20 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_DLY_0123_REG_FMR1_LINK_DELAY_LEN = 12 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_DLY_0123_REG_FMR2_LINK_DELAY = 36 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_DLY_0123_REG_FMR2_LINK_DELAY_LEN = 12 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_DLY_0123_REG_FMR3_LINK_DELAY = 52 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_DLY_0123_REG_FMR3_LINK_DELAY_LEN = 12 ;
+
+static const uint8_t P9N2_PU_IOE_PB_OLINK_DLY_4567_REG_FMR4_LINK_DELAY = 4 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_DLY_4567_REG_FMR4_LINK_DELAY_LEN = 12 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_DLY_4567_REG_FMR5_LINK_DELAY = 20 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_DLY_4567_REG_FMR5_LINK_DELAY_LEN = 12 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_DLY_4567_REG_FMR6_LINK_DELAY = 36 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_DLY_4567_REG_FMR6_LINK_DELAY_LEN = 12 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_DLY_4567_REG_FMR7_LINK_DELAY = 52 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_DLY_4567_REG_FMR7_LINK_DELAY_LEN = 12 ;
+
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU0_COUNTER0 = 0 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU0_COUNTER0_LEN = 16 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU0_COUNTER1 = 16 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU0_COUNTER1_LEN = 16 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU0_COUNTER2 = 32 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU0_COUNTER2_LEN = 16 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU0_COUNTER3 = 48 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU0_COUNTER3_LEN = 16 ;
+
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU1_COUNTER0 = 0 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU1_COUNTER0_LEN = 16 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU1_COUNTER1 = 16 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU1_COUNTER1_LEN = 16 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU1_COUNTER2 = 32 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU1_COUNTER2_LEN = 16 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU1_COUNTER3 = 48 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU1_COUNTER3_LEN = 16 ;
+
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU2_COUNTER0 = 0 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU2_COUNTER0_LEN = 16 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU2_COUNTER1 = 16 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU2_COUNTER1_LEN = 16 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU2_COUNTER2 = 32 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU2_COUNTER2_LEN = 16 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU2_COUNTER3 = 48 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU2_COUNTER3_LEN = 16 ;
+
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU3_COUNTER0 = 0 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU3_COUNTER0_LEN = 16 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU3_COUNTER1 = 16 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU3_COUNTER1_LEN = 16 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU3_COUNTER2 = 32 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU3_COUNTER2_LEN = 16 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU3_COUNTER3 = 48 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU3_COUNTER3_LEN = 16 ;
+
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU4_COUNTER0 = 0 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU4_COUNTER0_LEN = 16 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU4_COUNTER1 = 16 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU4_COUNTER1_LEN = 16 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU4_COUNTER2 = 32 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU4_COUNTER2_LEN = 16 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU4_COUNTER3 = 48 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU4_COUNTER3_LEN = 16 ;
+
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU5_COUNTER0 = 0 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU5_COUNTER0_LEN = 16 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU5_COUNTER1 = 16 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU5_COUNTER1_LEN = 16 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU5_COUNTER2 = 32 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU5_COUNTER2_LEN = 16 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU5_COUNTER3 = 48 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU5_COUNTER3_LEN = 16 ;
+
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU6_COUNTER0 = 0 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU6_COUNTER0_LEN = 16 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU6_COUNTER1 = 16 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU6_COUNTER1_LEN = 16 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU6_COUNTER2 = 32 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU6_COUNTER2_LEN = 16 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU6_COUNTER3 = 48 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU6_COUNTER3_LEN = 16 ;
+
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU7_COUNTER0 = 0 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU7_COUNTER0_LEN = 16 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU7_COUNTER1 = 16 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU7_COUNTER1_LEN = 16 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU7_COUNTER2 = 32 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU7_COUNTER2_LEN = 16 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU7_COUNTER3 = 48 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU7_COUNTER3_LEN = 16 ;
+
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_PMU0_ENABLE = 0 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_PMU1_ENABLE = 1 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_PMU2_ENABLE = 2 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_PMU3_ENABLE = 3 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_PMU4_ENABLE = 4 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_PMU5_ENABLE = 5 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_PMU6_ENABLE = 6 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_PMU7_ENABLE = 7 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_PMULET_FREEZE_MODE = 8 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_COMMON_FREEZE_MODE = 9 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_PMULET_RESET_MODE = 10 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_EVENT0_SEL = 11 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_EVENT1_SEL = 12 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_EVENT1_SEL_LEN = 4 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_EVENT2_SEL = 16 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_EVENT2_SEL_LEN = 4 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_EVENT3_SEL = 20 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_EVENT3_SEL_LEN = 4 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_PMU0_SIZE = 24 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_PMU0_SIZE_LEN = 2 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_PMU1_SIZE = 26 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_PMU1_SIZE_LEN = 2 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_PMU2_SIZE = 28 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_PMU2_SIZE_LEN = 2 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_PMU3_SIZE = 30 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_PMU3_SIZE_LEN = 2 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_PMU01_LINK_SELECT = 32 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_PMU23_LINK_SELECT = 33 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_PMU45_LINK_SELECT = 34 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_PMU67_LINK_SELECT = 35 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_PMU0145_EVENT0_MODE = 36 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_PMU0145_EVENT0_MODE_LEN = 2 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_PMU0145_EVENT1_MODE = 38 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_PMU0145_EVENT1_MODE_LEN = 2 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_PMU0145_EVENT2_MODE = 40 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_PMU0145_EVENT2_MODE_LEN = 2 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_PMU0145_EVENT3_MODE = 42 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_PMU0145_EVENT3_MODE_LEN = 2 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_PMU2367_EVENT0_MODE = 44 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_PMU2367_EVENT0_MODE_LEN = 2 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_PMU2367_EVENT1_MODE = 46 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_PMU2367_EVENT1_MODE_LEN = 2 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_PMU2367_EVENT2_MODE = 48 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_PMU2367_EVENT2_MODE_LEN = 2 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_PMU2367_EVENT3_MODE = 50 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_PMU2367_EVENT3_MODE_LEN = 2 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_ENABLE_GLOBAL_RUN = 52 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_GLOBAL_RUN_MODE = 53 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_SPARE = 54 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_PMU_CTL_REG_SPARE_LEN = 10 ;
+
+static const uint8_t P9N2_PU_IOE_PB_OLINK_RT_DELAY_CTL_REG_SET = 0 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_RT_DELAY_CTL_REG_SET_LEN = 8 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_RT_DELAY_CTL_REG_STAT = 8 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_RT_DELAY_CTL_REG_STAT_LEN = 8 ;
+
+static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_01_REG_DOB00_SCOM_SYN0 = 0 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_01_REG_DOB00_SCOM_SYN0_LEN = 8 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_01_REG_DOB00_SCOM_SYN1 = 8 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_01_REG_DOB00_SCOM_SYN1_LEN = 8 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_01_REG_DOB00_SCOM_SYN2 = 16 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_01_REG_DOB00_SCOM_SYN2_LEN = 8 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_01_REG_DOB00_SCOM_SYN3 = 24 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_01_REG_DOB00_SCOM_SYN3_LEN = 8 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_01_REG_DOB01_SCOM_SYN0 = 32 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_01_REG_DOB01_SCOM_SYN0_LEN = 8 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_01_REG_DOB01_SCOM_SYN1 = 40 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_01_REG_DOB01_SCOM_SYN1_LEN = 8 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_01_REG_DOB01_SCOM_SYN2 = 48 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_01_REG_DOB01_SCOM_SYN2_LEN = 8 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_01_REG_DOB01_SCOM_SYN3 = 56 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_01_REG_DOB01_SCOM_SYN3_LEN = 8 ;
+
+static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_23_REG_DOB02_SCOM_SYN0 = 0 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_23_REG_DOB02_SCOM_SYN0_LEN = 8 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_23_REG_DOB02_SCOM_SYN1 = 8 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_23_REG_DOB02_SCOM_SYN1_LEN = 8 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_23_REG_DOB02_SCOM_SYN2 = 16 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_23_REG_DOB02_SCOM_SYN2_LEN = 8 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_23_REG_DOB02_SCOM_SYN3 = 24 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_23_REG_DOB02_SCOM_SYN3_LEN = 8 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_23_REG_DOB03_SCOM_SYN0 = 32 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_23_REG_DOB03_SCOM_SYN0_LEN = 8 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_23_REG_DOB03_SCOM_SYN1 = 40 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_23_REG_DOB03_SCOM_SYN1_LEN = 8 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_23_REG_DOB03_SCOM_SYN2 = 48 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_23_REG_DOB03_SCOM_SYN2_LEN = 8 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_23_REG_DOB03_SCOM_SYN3 = 56 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_23_REG_DOB03_SCOM_SYN3_LEN = 8 ;
+
+static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_45_REG_DOB04_SCOM_SYN0 = 0 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_45_REG_DOB04_SCOM_SYN0_LEN = 8 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_45_REG_DOB04_SCOM_SYN1 = 8 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_45_REG_DOB04_SCOM_SYN1_LEN = 8 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_45_REG_DOB04_SCOM_SYN2 = 16 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_45_REG_DOB04_SCOM_SYN2_LEN = 8 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_45_REG_DOB04_SCOM_SYN3 = 24 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_45_REG_DOB04_SCOM_SYN3_LEN = 8 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_45_REG_DOB05_SCOM_SYN0 = 32 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_45_REG_DOB05_SCOM_SYN0_LEN = 8 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_45_REG_DOB05_SCOM_SYN1 = 40 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_45_REG_DOB05_SCOM_SYN1_LEN = 8 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_45_REG_DOB05_SCOM_SYN2 = 48 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_45_REG_DOB05_SCOM_SYN2_LEN = 8 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_45_REG_DOB05_SCOM_SYN3 = 56 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_45_REG_DOB05_SCOM_SYN3_LEN = 8 ;
+
+static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_67_REG_DOB06_SCOM_SYN0 = 0 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_67_REG_DOB06_SCOM_SYN0_LEN = 8 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_67_REG_DOB06_SCOM_SYN1 = 8 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_67_REG_DOB06_SCOM_SYN1_LEN = 8 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_67_REG_DOB06_SCOM_SYN2 = 16 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_67_REG_DOB06_SCOM_SYN2_LEN = 8 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_67_REG_DOB06_SCOM_SYN3 = 24 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_67_REG_DOB06_SCOM_SYN3_LEN = 8 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_67_REG_DOB07_SCOM_SYN0 = 32 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_67_REG_DOB07_SCOM_SYN0_LEN = 8 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_67_REG_DOB07_SCOM_SYN1 = 40 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_67_REG_DOB07_SCOM_SYN1_LEN = 8 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_67_REG_DOB07_SCOM_SYN2 = 48 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_67_REG_DOB07_SCOM_SYN2_LEN = 8 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_67_REG_DOB07_SCOM_SYN3 = 56 ;
+static const uint8_t P9N2_PU_IOE_PB_OLINK_SYN_67_REG_DOB07_SCOM_SYN3_LEN = 8 ;
+
+static const uint8_t P9N2_PU_PB_PERFTRACE_CFG_REG_HI_ENABLE = 0 ;
+static const uint8_t P9N2_PU_PB_PERFTRACE_CFG_REG_HI_FIXED_WINDOW_MODE = 1 ;
+static const uint8_t P9N2_PU_PB_PERFTRACE_CFG_REG_HI_PRESCALE_MODE = 2 ;
+static const uint8_t P9N2_PU_PB_PERFTRACE_CFG_REG_PTSPARE6 = 3 ;
+static const uint8_t P9N2_PU_PB_PERFTRACE_CFG_REG_LO_ENABLE = 4 ;
+static const uint8_t P9N2_PU_PB_PERFTRACE_CFG_REG_LO_FIXED_WINDOW_MODE = 5 ;
+static const uint8_t P9N2_PU_PB_PERFTRACE_CFG_REG_LO_PRESCALE_MODE = 6 ;
+static const uint8_t P9N2_PU_PB_PERFTRACE_CFG_REG_PTSPARE7 = 7 ;
+static const uint8_t P9N2_PU_PB_PERFTRACE_CFG_REG_HI_SELECT = 8 ;
+static const uint8_t P9N2_PU_PB_PERFTRACE_CFG_REG_HI_SELECT_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_PERFTRACE_CFG_REG_LO_SELECT = 12 ;
+static const uint8_t P9N2_PU_PB_PERFTRACE_CFG_REG_LO_SELECT_LEN = 4 ;
+
+static const uint8_t P9N2_PU_IOE_PB_PERFTRACE_CFG_REG_HI_ENABLE = 0 ;
+static const uint8_t P9N2_PU_IOE_PB_PERFTRACE_CFG_REG_HI_FIXED_WINDOW_MODE = 1 ;
+static const uint8_t P9N2_PU_IOE_PB_PERFTRACE_CFG_REG_HI_PRESCALE_MODE = 2 ;
+static const uint8_t P9N2_PU_IOE_PB_PERFTRACE_CFG_REG_PTSPARE6 = 3 ;
+static const uint8_t P9N2_PU_IOE_PB_PERFTRACE_CFG_REG_LO_ENABLE = 4 ;
+static const uint8_t P9N2_PU_IOE_PB_PERFTRACE_CFG_REG_LO_FIXED_WINDOW_MODE = 5 ;
+static const uint8_t P9N2_PU_IOE_PB_PERFTRACE_CFG_REG_LO_PRESCALE_MODE = 6 ;
+static const uint8_t P9N2_PU_IOE_PB_PERFTRACE_CFG_REG_PTSPARE7 = 7 ;
+static const uint8_t P9N2_PU_IOE_PB_PERFTRACE_CFG_REG_HI_SELECT = 8 ;
+static const uint8_t P9N2_PU_IOE_PB_PERFTRACE_CFG_REG_HI_SELECT_LEN = 4 ;
+static const uint8_t P9N2_PU_IOE_PB_PERFTRACE_CFG_REG_LO_SELECT = 12 ;
+static const uint8_t P9N2_PU_IOE_PB_PERFTRACE_CFG_REG_LO_SELECT_LEN = 4 ;
+
+static const uint8_t P9N2_PU_PB_PPE_LFIR_INTERNAL_ERROR = 0 ;
+static const uint8_t P9N2_PU_PB_PPE_LFIR_EXTERNAL_ERROR = 1 ;
+static const uint8_t P9N2_PU_PB_PPE_LFIR_PROGRESS_ERROR = 2 ;
+static const uint8_t P9N2_PU_PB_PPE_LFIR_BREAKPOINT_ERROR = 3 ;
+static const uint8_t P9N2_PU_PB_PPE_LFIR_WATCHDOG = 4 ;
+static const uint8_t P9N2_PU_PB_PPE_LFIR_HALTED = 5 ;
+static const uint8_t P9N2_PU_PB_PPE_LFIR_DEBUG_TRIGGER = 6 ;
+static const uint8_t P9N2_PU_PB_PPE_LFIR_SRAM_UE = 7 ;
+static const uint8_t P9N2_PU_PB_PPE_LFIR_SRAM_CE = 8 ;
+static const uint8_t P9N2_PU_PB_PPE_LFIR_SRAM_SCRUB_ERR = 9 ;
+static const uint8_t P9N2_PU_PB_PPE_LFIR_BCE_ERROR = 10 ;
+static const uint8_t P9N2_PU_PB_PPE_LFIR_SPARE11 = 11 ;
+static const uint8_t P9N2_PU_PB_PPE_LFIR_FIR_PARITY_ERR_DUP = 12 ;
+static const uint8_t P9N2_PU_PB_PPE_LFIR_FIR_PARITY_ERR = 13 ;
+
+static const uint8_t P9N2_PU_PB_PPE_LFIRACT0_FIR_ACTION0 = 0 ;
+static const uint8_t P9N2_PU_PB_PPE_LFIRACT0_FIR_ACTION0_LEN = 14 ;
+
+static const uint8_t P9N2_PU_PB_PPE_LFIRACT1_FIR_ACTION1 = 0 ;
+static const uint8_t P9N2_PU_PB_PPE_LFIRACT1_FIR_ACTION1_LEN = 14 ;
+
+static const uint8_t P9N2_PU_PB_PPE_LFIRMASK_FIR_MASK = 0 ;
+static const uint8_t P9N2_PU_PB_PPE_LFIRMASK_FIR_MASK_LEN = 14 ;
+
+static const uint8_t P9N2_PU_PB_PPE_LFIRWOF_LFIR_WOF = 0 ;
+static const uint8_t P9N2_PU_PB_PPE_LFIRWOF_LFIR_WOF_LEN = 14 ;
+
+static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS0_ADDRESS_PTY = 0 ;
+static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS0_ATAG_PTY = 1 ;
+static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS0_CC0_CREDITERR = 2 ;
+static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS0_CC1_CREDITERR = 3 ;
+static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS0_CC2_CREDITERR = 4 ;
+static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS0_CC3_CREDITERR = 5 ;
+static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS0_CONTROL_ERROR = 6 ;
+static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS0_PR0_CREDITERR = 7 ;
+static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS0_PR1_CREDITERR = 8 ;
+static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS0_RTAG_PTY = 9 ;
+static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS0_TTAG_PTY = 10 ;
+static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS0_VC0_CREDITERR = 11 ;
+static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS0_VC1_CREDITERR = 12 ;
+static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS1_ADDRESS_PTY = 16 ;
+static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS1_ATAG_PTY = 17 ;
+static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS1_CC0_CREDITERR = 18 ;
+static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS1_CC1_CREDITERR = 19 ;
+static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS1_CC2_CREDITERR = 20 ;
+static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS1_CC3_CREDITERR = 21 ;
+static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS1_CONTROL_ERROR = 22 ;
+static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS1_PR0_CREDITERR = 23 ;
+static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS1_PR1_CREDITERR = 24 ;
+static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS1_RTAG_PTY = 25 ;
+static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS1_TTAG_PTY = 26 ;
+static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS1_VC0_CREDITERR = 27 ;
+static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS1_VC1_CREDITERR = 28 ;
+static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS2_ADDRESS_PTY = 32 ;
+static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS2_ATAG_PTY = 33 ;
+static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS2_CC0_CREDITERR = 34 ;
+static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS2_CC1_CREDITERR = 35 ;
+static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS2_CC2_CREDITERR = 36 ;
+static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS2_CC3_CREDITERR = 37 ;
+static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS2_CONTROL_ERROR = 38 ;
+static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS2_PR0_CREDITERR = 39 ;
+static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS2_PR1_CREDITERR = 40 ;
+static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS2_RTAG_PTY = 41 ;
+static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS2_TTAG_PTY = 42 ;
+static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS2_VC0_CREDITERR = 43 ;
+static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS2_VC1_CREDITERR = 44 ;
+static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS3_ADDRESS_PTY = 48 ;
+static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS3_ATAG_PTY = 49 ;
+static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS3_CC0_CREDITERR = 50 ;
+static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS3_CC1_CREDITERR = 51 ;
+static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS3_CC2_CREDITERR = 52 ;
+static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS3_CC3_CREDITERR = 53 ;
+static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS3_CONTROL_ERROR = 54 ;
+static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS3_PR0_CREDITERR = 55 ;
+static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS3_PR1_CREDITERR = 56 ;
+static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS3_RTAG_PTY = 57 ;
+static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS3_TTAG_PTY = 58 ;
+static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS3_VC0_CREDITERR = 59 ;
+static const uint8_t P9N2_PU_PB_PR0123_ERR_PRS3_VC1_CREDITERR = 60 ;
+static const uint8_t P9N2_PU_PB_PR0123_ERR_LINK_DOWNQ_E_HOLD = 61 ;
+
+static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS0_ADDRESS_PTY = 0 ;
+static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS0_ATAG_PTY = 1 ;
+static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS0_CC0_CREDITERR = 2 ;
+static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS0_CC1_CREDITERR = 3 ;
+static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS0_CC2_CREDITERR = 4 ;
+static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS0_CC3_CREDITERR = 5 ;
+static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS0_CONTROL_ERROR = 6 ;
+static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS0_PR0_CREDITERR = 7 ;
+static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS0_PR1_CREDITERR = 8 ;
+static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS0_RTAG_PTY = 9 ;
+static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS0_TTAG_PTY = 10 ;
+static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS0_VC0_CREDITERR = 11 ;
+static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS0_VC1_CREDITERR = 12 ;
+static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS1_ADDRESS_PTY = 16 ;
+static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS1_ATAG_PTY = 17 ;
+static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS1_CC0_CREDITERR = 18 ;
+static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS1_CC1_CREDITERR = 19 ;
+static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS1_CC2_CREDITERR = 20 ;
+static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS1_CC3_CREDITERR = 21 ;
+static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS1_CONTROL_ERROR = 22 ;
+static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS1_PR0_CREDITERR = 23 ;
+static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS1_PR1_CREDITERR = 24 ;
+static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS1_RTAG_PTY = 25 ;
+static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS1_TTAG_PTY = 26 ;
+static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS1_VC0_CREDITERR = 27 ;
+static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS1_VC1_CREDITERR = 28 ;
+static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS2_ADDRESS_PTY = 32 ;
+static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS2_ATAG_PTY = 33 ;
+static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS2_CC0_CREDITERR = 34 ;
+static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS2_CC1_CREDITERR = 35 ;
+static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS2_CC2_CREDITERR = 36 ;
+static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS2_CC3_CREDITERR = 37 ;
+static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS2_CONTROL_ERROR = 38 ;
+static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS2_PR0_CREDITERR = 39 ;
+static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS2_PR1_CREDITERR = 40 ;
+static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS2_RTAG_PTY = 41 ;
+static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS2_TTAG_PTY = 42 ;
+static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS2_VC0_CREDITERR = 43 ;
+static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS2_VC1_CREDITERR = 44 ;
+static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS3_ADDRESS_PTY = 48 ;
+static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS3_ATAG_PTY = 49 ;
+static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS3_CC0_CREDITERR = 50 ;
+static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS3_CC1_CREDITERR = 51 ;
+static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS3_CC2_CREDITERR = 52 ;
+static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS3_CC3_CREDITERR = 53 ;
+static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS3_CONTROL_ERROR = 54 ;
+static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS3_PR0_CREDITERR = 55 ;
+static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS3_PR1_CREDITERR = 56 ;
+static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS3_RTAG_PTY = 57 ;
+static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS3_TTAG_PTY = 58 ;
+static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS3_VC0_CREDITERR = 59 ;
+static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_PRS3_VC1_CREDITERR = 60 ;
+static const uint8_t P9N2_PU_IOE_PB_PR0123_ERR_LINK_DOWNQ_E_HOLD = 61 ;
+
+static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS4_ADDRESS_PTY = 0 ;
+static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS4_ATAG_PTY = 1 ;
+static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS4_CC0_CREDITERR = 2 ;
+static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS4_CC1_CREDITERR = 3 ;
+static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS4_CC2_CREDITERR = 4 ;
+static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS4_CC3_CREDITERR = 5 ;
+static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS4_CONTROL_ERROR = 6 ;
+static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS4_PR0_CREDITERR = 7 ;
+static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS4_PR1_CREDITERR = 8 ;
+static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS4_RTAG_PTY = 9 ;
+static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS4_TTAG_PTY = 10 ;
+static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS4_VC0_CREDITERR = 11 ;
+static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS4_VC1_CREDITERR = 12 ;
+static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS5_ADDRESS_PTY = 16 ;
+static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS5_ATAG_PTY = 17 ;
+static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS5_CC0_CREDITERR = 18 ;
+static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS5_CC1_CREDITERR = 19 ;
+static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS5_CC2_CREDITERR = 20 ;
+static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS5_CC3_CREDITERR = 21 ;
+static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS5_CONTROL_ERROR = 22 ;
+static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS5_PR0_CREDITERR = 23 ;
+static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS5_PR1_CREDITERR = 24 ;
+static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS5_RTAG_PTY = 25 ;
+static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS5_TTAG_PTY = 26 ;
+static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS5_VC0_CREDITERR = 27 ;
+static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS5_VC1_CREDITERR = 28 ;
+static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS6_ADDRESS_PTY = 32 ;
+static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS6_ATAG_PTY = 33 ;
+static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS6_CC0_CREDITERR = 34 ;
+static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS6_CC1_CREDITERR = 35 ;
+static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS6_CC2_CREDITERR = 36 ;
+static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS6_CC3_CREDITERR = 37 ;
+static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS6_CONTROL_ERROR = 38 ;
+static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS6_PR0_CREDITERR = 39 ;
+static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS6_PR1_CREDITERR = 40 ;
+static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS6_RTAG_PTY = 41 ;
+static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS6_TTAG_PTY = 42 ;
+static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS6_VC0_CREDITERR = 43 ;
+static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS6_VC1_CREDITERR = 44 ;
+static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS7_ADDRESS_PTY = 48 ;
+static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS7_ATAG_PTY = 49 ;
+static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS7_CC0_CREDITERR = 50 ;
+static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS7_CC1_CREDITERR = 51 ;
+static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS7_CC2_CREDITERR = 52 ;
+static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS7_CC3_CREDITERR = 53 ;
+static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS7_CONTROL_ERROR = 54 ;
+static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS7_PR0_CREDITERR = 55 ;
+static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS7_PR1_CREDITERR = 56 ;
+static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS7_RTAG_PTY = 57 ;
+static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS7_TTAG_PTY = 58 ;
+static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS7_VC0_CREDITERR = 59 ;
+static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_PRS7_VC1_CREDITERR = 60 ;
+static const uint8_t P9N2_PU_IOE_PB_PR4567_ERR_LINK_DOWNQ_E_HOLD = 61 ;
+
+static const uint8_t P9N2_PU_PB_PR45_ERR_PRS4_ADDRESS_PTY = 0 ;
+static const uint8_t P9N2_PU_PB_PR45_ERR_PRS4_ATAG_PTY = 1 ;
+static const uint8_t P9N2_PU_PB_PR45_ERR_PRS4_CC0_CREDITERR = 2 ;
+static const uint8_t P9N2_PU_PB_PR45_ERR_PRS4_CC1_CREDITERR = 3 ;
+static const uint8_t P9N2_PU_PB_PR45_ERR_PRS4_CC2_CREDITERR = 4 ;
+static const uint8_t P9N2_PU_PB_PR45_ERR_PRS4_CC3_CREDITERR = 5 ;
+static const uint8_t P9N2_PU_PB_PR45_ERR_PRS4_CONTROL_ERROR = 6 ;
+static const uint8_t P9N2_PU_PB_PR45_ERR_PRS4_PR0_CREDITERR = 7 ;
+static const uint8_t P9N2_PU_PB_PR45_ERR_PRS4_PR1_CREDITERR = 8 ;
+static const uint8_t P9N2_PU_PB_PR45_ERR_PRS4_RTAG_PTY = 9 ;
+static const uint8_t P9N2_PU_PB_PR45_ERR_PRS4_TTAG_PTY = 10 ;
+static const uint8_t P9N2_PU_PB_PR45_ERR_PRS4_VC0_CREDITERR = 11 ;
+static const uint8_t P9N2_PU_PB_PR45_ERR_PRS4_VC1_CREDITERR = 12 ;
+static const uint8_t P9N2_PU_PB_PR45_ERR_PRS5_ADDRESS_PTY = 16 ;
+static const uint8_t P9N2_PU_PB_PR45_ERR_PRS5_ATAG_PTY = 17 ;
+static const uint8_t P9N2_PU_PB_PR45_ERR_PRS5_CC0_CREDITERR = 18 ;
+static const uint8_t P9N2_PU_PB_PR45_ERR_PRS5_CC1_CREDITERR = 19 ;
+static const uint8_t P9N2_PU_PB_PR45_ERR_PRS5_CC2_CREDITERR = 20 ;
+static const uint8_t P9N2_PU_PB_PR45_ERR_PRS5_CC3_CREDITERR = 21 ;
+static const uint8_t P9N2_PU_PB_PR45_ERR_PRS5_CONTROL_ERROR = 22 ;
+static const uint8_t P9N2_PU_PB_PR45_ERR_PRS5_PR0_CREDITERR = 23 ;
+static const uint8_t P9N2_PU_PB_PR45_ERR_PRS5_PR1_CREDITERR = 24 ;
+static const uint8_t P9N2_PU_PB_PR45_ERR_PRS5_RTAG_PTY = 25 ;
+static const uint8_t P9N2_PU_PB_PR45_ERR_PRS5_TTAG_PTY = 26 ;
+static const uint8_t P9N2_PU_PB_PR45_ERR_PRS5_VC0_CREDITERR = 27 ;
+static const uint8_t P9N2_PU_PB_PR45_ERR_PRS5_VC1_CREDITERR = 28 ;
+static const uint8_t P9N2_PU_PB_PR45_ERR_LINK_DOWNQ_E_HOLD = 29 ;
+
+static const uint8_t P9N2_PU_PB_PSAVE_CFG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_PB_PSAVE_CFG_X0_ACT = 1 ;
+static const uint8_t P9N2_PU_PB_PSAVE_CFG_X1_ACT = 2 ;
+static const uint8_t P9N2_PU_PB_PSAVE_CFG_X2_ACT = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_CFG_PS_SPARE1 = 4 ;
+static const uint8_t P9N2_PU_PB_PSAVE_CFG_WSIZE = 5 ;
+static const uint8_t P9N2_PU_PB_PSAVE_CFG_WSIZE_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_CFG_LUC = 8 ;
+static const uint8_t P9N2_PU_PB_PSAVE_CFG_LUC_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_PSAVE_CFG_HUC = 16 ;
+static const uint8_t P9N2_PU_PB_PSAVE_CFG_HUC_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_PSAVE_CFG_LUT = 27 ;
+static const uint8_t P9N2_PU_PB_PSAVE_CFG_LUT_LEN = 5 ;
+static const uint8_t P9N2_PU_PB_PSAVE_CFG_HUT = 35 ;
+static const uint8_t P9N2_PU_PB_PSAVE_CFG_HUT_LEN = 5 ;
+
+static const uint8_t P9N2_PU_PB_PSAVE_MON_CFG_X0_LO = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_MON_CFG_X0_LO_LEN = 5 ;
+static const uint8_t P9N2_PU_PB_PSAVE_MON_CFG_X0_HI = 11 ;
+static const uint8_t P9N2_PU_PB_PSAVE_MON_CFG_X0_HI_LEN = 5 ;
+static const uint8_t P9N2_PU_PB_PSAVE_MON_CFG_X1_LO = 19 ;
+static const uint8_t P9N2_PU_PB_PSAVE_MON_CFG_X1_LO_LEN = 5 ;
+static const uint8_t P9N2_PU_PB_PSAVE_MON_CFG_X1_HI = 27 ;
+static const uint8_t P9N2_PU_PB_PSAVE_MON_CFG_X1_HI_LEN = 5 ;
+static const uint8_t P9N2_PU_PB_PSAVE_MON_CFG_X2_LO = 35 ;
+static const uint8_t P9N2_PU_PB_PSAVE_MON_CFG_X2_LO_LEN = 5 ;
+static const uint8_t P9N2_PU_PB_PSAVE_MON_CFG_X2_HI = 43 ;
+static const uint8_t P9N2_PU_PB_PSAVE_MON_CFG_X2_HI_LEN = 5 ;
+
+static const uint8_t P9N2_PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_00 = 0 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_00_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_01 = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_01_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_02 = 6 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_02_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_03 = 9 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_03_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_04 = 12 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_04_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_05 = 15 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_05_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_06 = 18 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_06_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_07 = 21 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_07_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_08 = 24 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_08_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_09 = 27 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_09_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_10 = 30 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_10_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_11 = 33 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_11_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_12 = 36 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_12_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_13 = 39 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_13_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_14 = 42 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_14_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_15 = 45 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X0EVN_HIST_TDM_HUT_LUT_15_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X0EVN_HIST_X0_WIN_ID = 56 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X0EVN_HIST_X0_WIN_ID_LEN = 8 ;
+
+static const uint8_t P9N2_PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_00 = 0 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_00_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_01 = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_01_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_02 = 6 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_02_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_03 = 9 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_03_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_04 = 12 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_04_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_05 = 15 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_05_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_06 = 18 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_06_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_07 = 21 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_07_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_08 = 24 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_08_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_09 = 27 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_09_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_10 = 30 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_10_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_11 = 33 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_11_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_12 = 36 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_12_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_13 = 39 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_13_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_14 = 42 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_14_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_15 = 45 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X0ODD_HIST_TDM_HUT_LUT_15_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X0ODD_HIST_X0_WIN_ID = 56 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X0ODD_HIST_X0_WIN_ID_LEN = 8 ;
+
+static const uint8_t P9N2_PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_00 = 0 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_00_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_01 = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_01_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_02 = 6 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_02_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_03 = 9 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_03_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_04 = 12 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_04_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_05 = 15 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_05_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_06 = 18 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_06_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_07 = 21 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_07_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_08 = 24 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_08_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_09 = 27 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_09_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_10 = 30 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_10_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_11 = 33 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_11_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_12 = 36 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_12_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_13 = 39 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_13_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_14 = 42 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_14_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_15 = 45 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X1EVN_HIST_TDM_HUT_LUT_15_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X1EVN_HIST_X1_WIN_ID = 56 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X1EVN_HIST_X1_WIN_ID_LEN = 8 ;
+
+static const uint8_t P9N2_PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_00 = 0 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_00_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_01 = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_01_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_02 = 6 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_02_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_03 = 9 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_03_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_04 = 12 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_04_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_05 = 15 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_05_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_06 = 18 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_06_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_07 = 21 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_07_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_08 = 24 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_08_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_09 = 27 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_09_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_10 = 30 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_10_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_11 = 33 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_11_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_12 = 36 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_12_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_13 = 39 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_13_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_14 = 42 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_14_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_15 = 45 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X1ODD_HIST_TDM_HUT_LUT_15_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X1ODD_HIST_X1_WIN_ID = 56 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X1ODD_HIST_X1_WIN_ID_LEN = 8 ;
+
+static const uint8_t P9N2_PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_00 = 0 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_00_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_01 = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_01_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_02 = 6 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_02_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_03 = 9 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_03_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_04 = 12 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_04_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_05 = 15 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_05_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_06 = 18 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_06_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_07 = 21 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_07_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_08 = 24 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_08_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_09 = 27 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_09_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_10 = 30 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_10_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_11 = 33 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_11_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_12 = 36 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_12_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_13 = 39 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_13_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_14 = 42 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_14_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_15 = 45 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X2EVN_HIST_TDM_HUT_LUT_15_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X2EVN_HIST_X2_WIN_ID = 56 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X2EVN_HIST_X2_WIN_ID_LEN = 8 ;
+
+static const uint8_t P9N2_PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_00 = 0 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_00_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_01 = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_01_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_02 = 6 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_02_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_03 = 9 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_03_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_04 = 12 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_04_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_05 = 15 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_05_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_06 = 18 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_06_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_07 = 21 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_07_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_08 = 24 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_08_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_09 = 27 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_09_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_10 = 30 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_10_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_11 = 33 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_11_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_12 = 36 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_12_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_13 = 39 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_13_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_14 = 42 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_14_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_15 = 45 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X2ODD_HIST_TDM_HUT_LUT_15_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X2ODD_HIST_X2_WIN_ID = 56 ;
+static const uint8_t P9N2_PU_PB_PSAVE_X2ODD_HIST_X2_WIN_ID_LEN = 8 ;
+
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_0_CFG_CHG_RATE_GP_LOW_RTY_THRESHOLD_NEXT = 14 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_0_CFG_CHG_RATE_GP_LOW_RTY_THRESHOLD_NEXT_LEN = 10 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_0_CFG_CHG_RATE_GP_HIGH_RTY_THRESHOLD_NEXT = 24 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_0_CFG_CHG_RATE_GP_HIGH_RTY_THRESHOLD_NEXT_LEN = 10 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_0_CFG_CHG_RATE_RGP_LOW_RTY_THRESHOLD_NEXT = 34 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_0_CFG_CHG_RATE_RGP_LOW_RTY_THRESHOLD_NEXT_LEN = 10 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_0_CFG_CHG_RATE_RGP_HIGH_RTY_THRESHOLD_NEXT = 44 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_0_CFG_CHG_RATE_RGP_HIGH_RTY_THRESHOLD_NEXT_LEN = 10 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_0_CFG_CHG_RATE_SP_LOW_RTY_THRESHOLD_NEXT = 54 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_0_CFG_CHG_RATE_SP_LOW_RTY_THRESHOLD_NEXT_LEN = 10 ;
+
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_1_CFG_CHG_RATE_SP_HIGH_RTY_THRESHOLD_NEXT = 18 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_1_CFG_CHG_RATE_SP_HIGH_RTY_THRESHOLD_NEXT_LEN = 10 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_1_CFG_CHG_RATE_GP_CRESP_SAMPLE_TIME_NEXT = 28 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_1_CFG_CHG_RATE_GP_CRESP_SAMPLE_TIME_NEXT_LEN = 12 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_1_CFG_CHG_RATE_RGP_CRESP_SAMPLE_TIME_NEXT = 40 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_1_CFG_CHG_RATE_RGP_CRESP_SAMPLE_TIME_NEXT_LEN = 12 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_1_CFG_CHG_RATE_SP_CRESP_SAMPLE_TIME_NEXT = 52 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_1_CFG_CHG_RATE_SP_CRESP_SAMPLE_TIME_NEXT_LEN = 12 ;
+
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_2_CFG_CHG_RATE_GP_REQ_SAMPLE_TIME_NEXT = 22 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_2_CFG_CHG_RATE_GP_REQ_SAMPLE_TIME_NEXT_LEN = 12 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_2_CFG_CHG_RATE_SP_REQ_SAMPLE_TIME_NEXT = 34 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_2_CFG_CHG_RATE_SP_REQ_SAMPLE_TIME_NEXT_LEN = 12 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_2_CFG_CHG_RATE_GP_LOW_JUMP_NEXT = 46 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_2_CFG_CHG_RATE_GP_LOW_JUMP_NEXT_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_2_CFG_CHG_RATE_GP_HIGH_JUMP_NEXT = 49 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_2_CFG_CHG_RATE_GP_HIGH_JUMP_NEXT_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_2_CFG_CHG_RATE_SP_LOW_JUMP_NEXT = 52 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_2_CFG_CHG_RATE_SP_LOW_JUMP_NEXT_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_2_CFG_CHG_RATE_SP_HIGH_JUMP_NEXT = 55 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_2_CFG_CHG_RATE_SP_HIGH_JUMP_NEXT_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_2_CFG_CHG_RATE_RGP_LOW_JUMP_NEXT = 58 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_2_CFG_CHG_RATE_RGP_LOW_JUMP_NEXT_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_2_CFG_CHG_RATE_RGP_HIGH_JUMP_NEXT = 61 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_2_CFG_CHG_RATE_RGP_HIGH_JUMP_NEXT_LEN = 3 ;
+
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_3_CFG_HANG0_CMD_RATE_NEXT = 28 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_3_CFG_HANG0_CMD_RATE_NEXT_LEN = 5 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_3_CFG_HANG1_CMD_RATE_NEXT = 33 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_3_CFG_HANG1_CMD_RATE_NEXT_LEN = 5 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_3_CFG_HANG2_CMD_RATE_NEXT = 38 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_3_CFG_HANG2_CMD_RATE_NEXT_LEN = 5 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_3_CFG_HANG3_CMD_RATE_NEXT = 43 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_3_CFG_HANG3_CMD_RATE_NEXT_LEN = 5 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_3_CFG_HANG4_CMD_RATE_NEXT = 48 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_3_CFG_HANG4_CMD_RATE_NEXT_LEN = 5 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_3_CFG_HANG5_CMD_RATE_NEXT = 53 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_3_CFG_HANG5_CMD_RATE_NEXT_LEN = 5 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_3_CFG_HANG6_CMD_RATE_NEXT = 58 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_3_CFG_HANG6_CMD_RATE_NEXT_LEN = 5 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_3_CFG_USE_SLOW_GO_RATE_NEXT = 63 ;
+
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_4_CFG_CPO_JUMP_LEVEL_NEXT = 49 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_4_CFG_CPO_JUMP_LEVEL_NEXT_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_4_CFG_CPO_RTY_LEVEL_NEXT = 52 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_4_CFG_CPO_RTY_LEVEL_NEXT_LEN = 6 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_4_CFG_P7_SLEEP_BACKOFF_NEXT = 58 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_4_CFG_P7_SLEEP_BACKOFF_NEXT_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_4_CFG_RTY_PERCENTAGE_NEXT = 60 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_4_CFG_RTY_PERCENTAGE_NEXT_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_4_CFG_INCLUDE_LPC_RTY_NEXT = 63 ;
+
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_5_CFG_GP_LVL0_CHGRATE_CLK_DIV_NEXT = 16 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_5_CFG_GP_LVL0_CHGRATE_CLK_DIV_NEXT_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_5_CFG_GP_LVL1_CHGRATE_CLK_DIV_NEXT = 19 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_5_CFG_GP_LVL1_CHGRATE_CLK_DIV_NEXT_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_5_CFG_GP_LVL2_CHGRATE_CLK_DIV_NEXT = 22 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_5_CFG_GP_LVL2_CHGRATE_CLK_DIV_NEXT_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_5_CFG_GP_LVL3_CHGRATE_CLK_DIV_NEXT = 25 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_5_CFG_GP_LVL3_CHGRATE_CLK_DIV_NEXT_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_5_CFG_GP_LVL4_CHGRATE_CLK_DIV_NEXT = 28 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_5_CFG_GP_LVL4_CHGRATE_CLK_DIV_NEXT_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_5_CFG_GP_LVL5_CHGRATE_CLK_DIV_NEXT = 31 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_5_CFG_GP_LVL5_CHGRATE_CLK_DIV_NEXT_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_5_CFG_GP_LVL6_CHGRATE_CLK_DIV_NEXT = 34 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_5_CFG_GP_LVL6_CHGRATE_CLK_DIV_NEXT_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_5_CFG_GP_LVL7_CHGRATE_CLK_DIV_NEXT = 37 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_5_CFG_GP_LVL7_CHGRATE_CLK_DIV_NEXT_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_5_CFG_RGP_LVL0_CHGRATE_CLK_DIV_NEXT = 40 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_5_CFG_RGP_LVL0_CHGRATE_CLK_DIV_NEXT_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_5_CFG_RGP_LVL1_CHGRATE_CLK_DIV_NEXT = 43 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_5_CFG_RGP_LVL1_CHGRATE_CLK_DIV_NEXT_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_5_CFG_RGP_LVL2_CHGRATE_CLK_DIV_NEXT = 46 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_5_CFG_RGP_LVL2_CHGRATE_CLK_DIV_NEXT_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_5_CFG_RGP_LVL3_CHGRATE_CLK_DIV_NEXT = 49 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_5_CFG_RGP_LVL3_CHGRATE_CLK_DIV_NEXT_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_5_CFG_RGP_LVL4_CHGRATE_CLK_DIV_NEXT = 52 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_5_CFG_RGP_LVL4_CHGRATE_CLK_DIV_NEXT_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_5_CFG_RGP_LVL5_CHGRATE_CLK_DIV_NEXT = 55 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_5_CFG_RGP_LVL5_CHGRATE_CLK_DIV_NEXT_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_5_CFG_RGP_LVL6_CHGRATE_CLK_DIV_NEXT = 58 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_5_CFG_RGP_LVL6_CHGRATE_CLK_DIV_NEXT_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_5_CFG_RGP_LVL7_CHGRATE_CLK_DIV_NEXT = 61 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_5_CFG_RGP_LVL7_CHGRATE_CLK_DIV_NEXT_LEN = 3 ;
+
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_6_CFG_SP_LVL0_CHGRATE_CLK_DIV_NEXT = 32 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_6_CFG_SP_LVL0_CHGRATE_CLK_DIV_NEXT_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_6_CFG_SP_LVL1_CHGRATE_CLK_DIV_NEXT = 35 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_6_CFG_SP_LVL1_CHGRATE_CLK_DIV_NEXT_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_6_CFG_SP_LVL2_CHGRATE_CLK_DIV_NEXT = 38 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_6_CFG_SP_LVL2_CHGRATE_CLK_DIV_NEXT_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_6_CFG_SP_LVL3_CHGRATE_CLK_DIV_NEXT = 41 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_6_CFG_SP_LVL3_CHGRATE_CLK_DIV_NEXT_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_6_CFG_SP_LVL4_CHGRATE_CLK_DIV_NEXT = 44 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_6_CFG_SP_LVL4_CHGRATE_CLK_DIV_NEXT_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_6_CFG_SP_LVL5_CHGRATE_CLK_DIV_NEXT = 47 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_6_CFG_SP_LVL5_CHGRATE_CLK_DIV_NEXT_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_6_CFG_SP_LVL6_CHGRATE_CLK_DIV_NEXT = 50 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_6_CFG_SP_LVL6_CHGRATE_CLK_DIV_NEXT_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_6_CFG_SP_LVL7_CHGRATE_CLK_DIV_NEXT = 53 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_6_CFG_SP_LVL7_CHGRATE_CLK_DIV_NEXT_LEN = 3 ;
+
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_7_CFG_ONE_HOP_STARVE_LIMIT_0_NEXT = 20 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_7_CFG_ONE_HOP_STARVE_LIMIT_0_NEXT_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_7_CFG_NP_CMD_RATE_DP0_0_NEXT = 28 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_7_CFG_NP_CMD_RATE_DP0_0_NEXT_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_7_CFG_NP_CMD_RATE_DP1_0_NEXT = 36 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_7_CFG_NP_CMD_RATE_DP1_0_NEXT_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_7_CFG_SINGLE_LINK_CREDIT_NEXT = 44 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_7_CFG_XX_HOP_RANDOM_TOK_DISABLE_NEXT = 45 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_7_CFG_UX_ARB_RANDOM_TOK_DISABLE_NEXT = 46 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_7_CFG_EAST_WEST_FAIRNESS_DISABLE_NEXT = 47 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_7_CFG_WEST_FORCED_WEIGHT_EN_NEXT = 48 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_7_CFG_WEST_FORCED_WEIGHT_0_NEXT = 49 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_7_CFG_WEST_FORCED_WEIGHT_0_NEXT_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_7_CFG_EAST_FORCED_WEIGHT_EN_NEXT = 52 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_7_CFG_EAST_FORCED_WEIGHT_0_NEXT = 53 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_7_CFG_EAST_FORCED_WEIGHT_0_NEXT_LEN = 3 ;
+
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_8_CFG_DYNAMIC_WEST_WEIGHT_ADDER_0_NEXT = 41 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_8_CFG_DYNAMIC_WEST_WEIGHT_ADDER_0_NEXT_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_8_CFG_DYNAMIC_EAST_WEIGHT_ADDER_0_NEXT = 43 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_8_CFG_DYNAMIC_EAST_WEIGHT_ADDER_0_NEXT_LEN = 2 ;
+
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_9_SPARE = 32 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_9_SPARE_LEN = 32 ;
+
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_A_CFG_NXTP_TOKEN_INIT = 38 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_A_CFG_NXTP_TOKEN_INIT_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_A_CFG_LINK_TOK_AGG_THRESHOLD_NEXT = 42 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_A_CFG_LINK_TOK_AGG_THRESHOLD_NEXT_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_A_CFG_ON_TOK_SEL_NEXT = 46 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_A_CFG_ON_TOK_SEL_NEXT_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_A_CFG_LOAD_TOKEN_INIT_NEXT = 50 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_A_CFG_OFF_TOK_SEL_NEXT = 51 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_A_CFG_OFF_TOK_SEL_NEXT_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_A_CFG_A3_ON_TOK_SEL_NEXT = 54 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_A_CFG_A3_ON_TOK_SEL_NEXT_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_A_CFG_A3_OFF_TOK_SEL_NEXT = 57 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_A_CFG_A3_OFF_TOK_SEL_NEXT_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_A_CFG_REMOTE_HOLD_CNT_NEXT = 60 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_A_CFG_REMOTE_HOLD_CNT_NEXT_LEN = 4 ;
+
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_B_CFG_EX_TOKEN_INIT_NEXT = 51 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_B_CFG_EX_TOKEN_INIT_NEXT_LEN = 5 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_B_CFG_VAS_TOKEN_INIT_NEXT = 58 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_B_CFG_VAS_TOKEN_INIT_NEXT_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_B_CFG_REMOTE_HOLD_CNT_NEXT = 60 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_B_CFG_REMOTE_HOLD_CNT_NEXT_LEN = 4 ;
+
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_C_PB_CFG_MAX_OUTSTANDING = 36 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_C_PB_CFG_MAX_OUTSTANDING_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_C_PB_CFG_FORCE_TRUNK = 39 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_C_PB_CFG_FORCE_EVEN_TRUNK = 40 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_C_PB_CFG_STV_CNT = 41 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_C_PB_CFG_STV_CNT_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_C_PB_CFG_STV_EN = 49 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_C_PB_CFG_ANY_TIMEZONE = 50 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_C_PB_CFG_ENABLE_FP = 51 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_C_PB_CFG_GATHER_EX_EN = 52 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_C_PB_CFG_GATHER_ENES_EN = 53 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_C_PB_CFG_BLOCK_LOCAL_REQ = 54 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_C_PB_CFG_GATHER_FLAG_EN = 55 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_C_PB_CFG_BUBBLE_EN = 56 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_C_PB_CFG_GATHER_SEQ_EN = 57 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_C_CFG_REMOTE_HOLD_CNT_NEXT = 60 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_C_CFG_REMOTE_HOLD_CNT_NEXT_LEN = 4 ;
+
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_D_PB_CFG_LOCK_ON_LINKS = 12 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_D_PB_CFG_X_ON_LINK_TOK_AGG_THRESHOLD = 13 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_D_PB_CFG_X_ON_LINK_TOK_AGG_THRESHOLD_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_D_PB_CFG_X_OFF_LINK_TOK_AGG_THRESHOLD = 17 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_D_PB_CFG_X_OFF_LINK_TOK_AGG_THRESHOLD_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_D_PB_CFG_A_LINK_TOK_AGG_THRESHOLD = 21 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_D_PB_CFG_A_LINK_TOK_AGG_THRESHOLD_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_D_CFG_A_ON_TOK_SEL_NEXT = 25 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_D_CFG_A_ON_TOK_SEL_NEXT_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_D_CFG_A_OFF_TOK_SEL_NEXT = 28 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_D_CFG_A_OFF_TOK_SEL_NEXT_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_D_CFG_A3_ON_TOK_SEL_NEXT = 31 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_D_CFG_A3_ON_TOK_SEL_NEXT_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_D_PB_CFG_PASTHRU_X_PRIORITY = 34 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_D_PB_CFG_PASTHRU_X_PRIORITY_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_D_PB_CFG_PASTHRU_A_PRIORITY = 42 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_D_PB_CFG_PASTHRU_A_PRIORITY_LEN = 8 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_D_CFG_X_OFF_TOK_SEL_NEXT = 50 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_D_CFG_X_OFF_TOK_SEL_NEXT_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_D_CFG_X_ON_TOK_SEL_NEXT = 52 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_D_CFG_X_ON_TOK_SEL_NEXT_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_D_CFG_A3_OFF_TOK_SEL_NEXT = 54 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_D_CFG_A3_OFF_TOK_SEL_NEXT_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_D_PB_CFG_A_LINK_TOK_IND_THRESHOLD = 57 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_D_PB_CFG_A_LINK_TOK_IND_THRESHOLD_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_D_CFG_LOAD_TOKEN_INIT_NEXT = 59 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_D_CFG_X_ON_RING_DIS_NEXT = 60 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_D_PB_CFG_FORCE_STV_PRIORITY = 61 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_D_PB_CFG_FORCE_HP_MEM_PRIORITY = 62 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_D_PB_CFG_PASTHRU_ENABLE = 63 ;
+
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_E_PB_CFG_BYPASS_HP_ENABLE = 55 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_E_PB_CFG_REMOTE_C_DELAY_FORCE = 56 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_E_PB_CFG_MAX_OUTSTANDING = 57 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_E_PB_CFG_MAX_OUTSTANDING_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_E_PB_CFG_GATHER_EN = 60 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_E_PB_CFG_SPARE_MODE = 61 ;
+
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_F_PBIEN_CFG_LINK_DOFF_ARBMODE_NEXT = 45 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_F_PBIEN_CFG_LINK_DOFF_ARBMODE_NEXT_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_F_PBIEN_CFG_LINK_DOFF_VCINIT_NEXT = 49 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_F_PBIEN_CFG_LINK_DOFF_VCINIT_NEXT_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_F_PBIEN_CFG_UNIT_DOFF_ARBMODE_NEXT = 52 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_F_PBIEN_CFG_UNIT_DOFF_ARBMODE_NEXT_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_F_PBIEN_CFG_LINK_DON_VCINIT_NEXT = 54 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_F_PBIEN_CFG_LINK_DON_VCINIT_NEXT_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_F_PBIEN_CFG_LINK_DON_ARBMODE_NEXT = 57 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_F_PBIEN_CFG_LINK_DON_ARBMODE_NEXT_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_F_PBIEN_CFG_UNIT_DON_ARBMODE_NEXT = 59 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_F_PBIEN_CFG_UNIT_DON_ARBMODE_NEXT_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_F_PBIEN_CFG_LINK_VA_DOFF_VCINIT_NEXT = 61 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_CENT_F_PBIEN_CFG_LINK_VA_DOFF_VCINIT_NEXT_LEN = 3 ;
+
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_0_CFG_LATE_RD_MODE_NEXT = 15 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_0_CFG_DELAY_SP_RD_NEXT = 16 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_0_CFG_DELAY_SP_RD_NEXT_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_0_HW070772_DIS_NEXT = 20 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_0_CFG_NOP_MODE_NEXT = 21 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_0_CFG_NOP_MODE_NEXT_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_0_CFG_FORCE_FA_ALLOCATION_NEXT = 31 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_0_CFG_INITIAL_REQ_DLY_NEXT = 34 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_0_CFG_INITIAL_REQ_DLY_NEXT_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_0_CFG_DCTR_LAUNCH_NEXT = 37 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_0_CFG_DCTR_LAUNCH_NEXT_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_0_CFG_OUTSTANDING_REQ_COUNT_NEXT = 39 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_0_CFG_REQ_ID_ASSIGNMENT_MODE_NEXT = 40 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_0_CFG_ALLOW_FRAGMENTATION_NEXT = 41 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_0_CFG_DREQ_ID_NEXT = 42 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_0_CFG_DVAL_LAUNCH_NEXT = 48 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_0_CFG_DVAL_LAUNCH_NEXT_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_0_CFG_HSHAKE_NEXT = 50 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_0_CFG_DONE_LAUNCH_NEXT = 52 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_0_CFG_SPARE_MODE_NEXT = 53 ;
+
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_1_CFG_EARLY_REQ_MODE_NEXT = 28 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_1_CFG_HSHAKE_NEXT = 33 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_1_CFG_SPARE_MODE_NEXT = 38 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_1_CFG_DCTR_LAUNCH_NEXT = 41 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_1_CFG_DCTR_LAUNCH_NEXT_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_1_PB_CFG_DAT_I2C_SPARE_MODE_NEXT = 43 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_1_CFG_DREQ_LAUNCH_NEXT = 46 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_1_CFG_DREQ_LAUNCH_NEXT_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_1_PB_CFG_DAT_C2I_SPARE_MODE_NEXT = 48 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_1_CFG_L3_NOT_USE_DCBFL_NEXT = 50 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_1_CFG_PTY_INJECT_NEXT = 53 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_1_PB_CFG_RCMD_SPARE_MODE_NEXT = 54 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_1_CFG_DONE_LAUNCH_NEXT = 55 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_1_CFG_PTY_RD_CAPTURE_NEXT = 57 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_1_CFG_PTY_RD_CAPTURE_NEXT_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_1_PB_CFG_FP_I2CRCTL_SPARE_MODE_NEXT = 59 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_1_CFG_DVAL_LAUNCH_NEXT = 60 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_1_CFG_DVAL_LAUNCH_NEXT_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_1_PB_CFG_FP_C2ISCTL_HSHAKE_NEXT = 62 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_1_PB_CFG_FP_C2ISCTL_SPARE_MODE_NEXT = 63 ;
+
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_2_CFG_CMD_OC_EXPIRATION_TIME_NEXT = 54 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_2_CFG_CMD_OC_EXPIRATION_TIME_NEXT_LEN = 5 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_2_CFG_CMD_OC_EARLY_EXPIRATION_TIME_NEXT = 59 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_2_CFG_CMD_OC_EARLY_EXPIRATION_TIME_NEXT_LEN = 5 ;
+
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_3_CFG_CMD_OC_EXPIRATION_TIME_NEXT = 54 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_3_CFG_CMD_OC_EXPIRATION_TIME_NEXT_LEN = 5 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_3_CFG_CMD_OC_EARLY_EXPIRATION_TIME_NEXT = 59 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_EAST_3_CFG_CMD_OC_EARLY_EXPIRATION_TIME_NEXT_LEN = 5 ;
+
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_0_CFG_LATE_RD_MODE_NEXT = 15 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_0_CFG_DELAY_SP_RD_NEXT = 16 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_0_CFG_DELAY_SP_RD_NEXT_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_0_HW070772_DIS_NEXT = 20 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_0_CFG_NOP_MODE_NEXT = 21 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_0_CFG_NOP_MODE_NEXT_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_0_CFG_FORCE_FA_ALLOCATION_NEXT = 31 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_0_CFG_INITIAL_REQ_DLY_NEXT = 34 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_0_CFG_INITIAL_REQ_DLY_NEXT_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_0_CFG_DCTR_LAUNCH_NEXT = 37 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_0_CFG_DCTR_LAUNCH_NEXT_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_0_CFG_OUTSTANDING_REQ_COUNT_NEXT = 39 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_0_CFG_REQ_ID_ASSIGNMENT_MODE_NEXT = 40 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_0_CFG_ALLOW_FRAGMENTATION_NEXT = 41 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_0_CFG_DREQ_ID_NEXT = 42 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_0_CFG_DVAL_LAUNCH_NEXT = 48 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_0_CFG_DVAL_LAUNCH_NEXT_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_0_CFG_HSHAKE_NEXT = 50 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_0_CFG_DONE_LAUNCH_NEXT = 52 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_0_CFG_SPARE_MODE_NEXT = 53 ;
+
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_1_CFG_EARLY_REQ_MODE_NEXT = 28 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_1_CFG_HSHAKE_NEXT = 33 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_1_CFG_SPARE_MODE_NEXT = 38 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_1_CFG_DCTR_LAUNCH_NEXT = 41 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_1_CFG_DCTR_LAUNCH_NEXT_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_1_PB_CFG_DAT_I2C_SPARE_MODE_NEXT = 43 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_1_CFG_DREQ_LAUNCH_NEXT = 46 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_1_CFG_DREQ_LAUNCH_NEXT_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_1_PB_CFG_DAT_C2I_SPARE_MODE_NEXT = 48 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_1_CFG_L3_NOT_USE_DCBFL_NEXT = 50 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_1_CFG_PTY_INJECT_NEXT = 53 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_1_PB_CFG_RCMD_SPARE_MODE_NEXT = 54 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_1_CFG_DONE_LAUNCH_NEXT = 55 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_1_CFG_PTY_RD_CAPTURE_NEXT = 57 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_1_CFG_PTY_RD_CAPTURE_NEXT_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_1_PB_CFG_FP_I2CRCTL_SPARE_MODE_NEXT = 59 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_1_CFG_DVAL_LAUNCH_NEXT = 60 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_1_CFG_DVAL_LAUNCH_NEXT_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_1_PB_CFG_FP_C2ISCTL_HSHAKE_NEXT = 62 ;
+static const uint8_t P9N2_PU_PB_SERIAL_SCOM_WEST_1_PB_CFG_FP_C2ISCTL_SPARE_MODE_NEXT = 63 ;
+
+static const uint8_t P9N2_PU_PB_TRACE_CFG_LINK00_HI = 0 ;
+static const uint8_t P9N2_PU_PB_TRACE_CFG_LINK00_HI_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_TRACE_CFG_LINK00_LO = 4 ;
+static const uint8_t P9N2_PU_PB_TRACE_CFG_LINK00_LO_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_TRACE_CFG_LINK01_HI = 8 ;
+static const uint8_t P9N2_PU_PB_TRACE_CFG_LINK01_HI_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_TRACE_CFG_LINK01_LO = 12 ;
+static const uint8_t P9N2_PU_PB_TRACE_CFG_LINK01_LO_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_TRACE_CFG_LINK02_HI = 16 ;
+static const uint8_t P9N2_PU_PB_TRACE_CFG_LINK02_HI_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_TRACE_CFG_LINK02_LO = 20 ;
+static const uint8_t P9N2_PU_PB_TRACE_CFG_LINK02_LO_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_TRACE_CFG_LINK03_HI = 24 ;
+static const uint8_t P9N2_PU_PB_TRACE_CFG_LINK03_HI_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_TRACE_CFG_LINK03_LO = 28 ;
+static const uint8_t P9N2_PU_PB_TRACE_CFG_LINK03_LO_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_TRACE_CFG_LINK04_HI = 32 ;
+static const uint8_t P9N2_PU_PB_TRACE_CFG_LINK04_HI_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_TRACE_CFG_LINK04_LO = 36 ;
+static const uint8_t P9N2_PU_PB_TRACE_CFG_LINK04_LO_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_TRACE_CFG_LINK05_HI = 40 ;
+static const uint8_t P9N2_PU_PB_TRACE_CFG_LINK05_HI_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_TRACE_CFG_LINK05_LO = 44 ;
+static const uint8_t P9N2_PU_PB_TRACE_CFG_LINK05_LO_LEN = 4 ;
+
+static const uint8_t P9N2_PU_IOE_PB_TRACE_CFG_LINK00_HI = 0 ;
+static const uint8_t P9N2_PU_IOE_PB_TRACE_CFG_LINK00_HI_LEN = 4 ;
+static const uint8_t P9N2_PU_IOE_PB_TRACE_CFG_LINK00_LO = 4 ;
+static const uint8_t P9N2_PU_IOE_PB_TRACE_CFG_LINK00_LO_LEN = 4 ;
+static const uint8_t P9N2_PU_IOE_PB_TRACE_CFG_LINK01_HI = 8 ;
+static const uint8_t P9N2_PU_IOE_PB_TRACE_CFG_LINK01_HI_LEN = 4 ;
+static const uint8_t P9N2_PU_IOE_PB_TRACE_CFG_LINK01_LO = 12 ;
+static const uint8_t P9N2_PU_IOE_PB_TRACE_CFG_LINK01_LO_LEN = 4 ;
+static const uint8_t P9N2_PU_IOE_PB_TRACE_CFG_LINK02_HI = 16 ;
+static const uint8_t P9N2_PU_IOE_PB_TRACE_CFG_LINK02_HI_LEN = 4 ;
+static const uint8_t P9N2_PU_IOE_PB_TRACE_CFG_LINK02_LO = 20 ;
+static const uint8_t P9N2_PU_IOE_PB_TRACE_CFG_LINK02_LO_LEN = 4 ;
+static const uint8_t P9N2_PU_IOE_PB_TRACE_CFG_LINK03_HI = 24 ;
+static const uint8_t P9N2_PU_IOE_PB_TRACE_CFG_LINK03_HI_LEN = 4 ;
+static const uint8_t P9N2_PU_IOE_PB_TRACE_CFG_LINK03_LO = 28 ;
+static const uint8_t P9N2_PU_IOE_PB_TRACE_CFG_LINK03_LO_LEN = 4 ;
+static const uint8_t P9N2_PU_IOE_PB_TRACE_CFG_LINK04_HI = 32 ;
+static const uint8_t P9N2_PU_IOE_PB_TRACE_CFG_LINK04_HI_LEN = 4 ;
+static const uint8_t P9N2_PU_IOE_PB_TRACE_CFG_LINK04_LO = 36 ;
+static const uint8_t P9N2_PU_IOE_PB_TRACE_CFG_LINK04_LO_LEN = 4 ;
+static const uint8_t P9N2_PU_IOE_PB_TRACE_CFG_LINK05_HI = 40 ;
+static const uint8_t P9N2_PU_IOE_PB_TRACE_CFG_LINK05_HI_LEN = 4 ;
+static const uint8_t P9N2_PU_IOE_PB_TRACE_CFG_LINK05_LO = 44 ;
+static const uint8_t P9N2_PU_IOE_PB_TRACE_CFG_LINK05_LO_LEN = 4 ;
+static const uint8_t P9N2_PU_IOE_PB_TRACE_CFG_LINK06_HI = 48 ;
+static const uint8_t P9N2_PU_IOE_PB_TRACE_CFG_LINK06_HI_LEN = 4 ;
+static const uint8_t P9N2_PU_IOE_PB_TRACE_CFG_LINK06_LO = 52 ;
+static const uint8_t P9N2_PU_IOE_PB_TRACE_CFG_LINK06_LO_LEN = 4 ;
+static const uint8_t P9N2_PU_IOE_PB_TRACE_CFG_LINK07_HI = 56 ;
+static const uint8_t P9N2_PU_IOE_PB_TRACE_CFG_LINK07_HI_LEN = 4 ;
+static const uint8_t P9N2_PU_IOE_PB_TRACE_CFG_LINK07_LO = 60 ;
+static const uint8_t P9N2_PU_IOE_PB_TRACE_CFG_LINK07_LO_LEN = 4 ;
+
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_ACTION0_REG_ACTION0 = 0 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_ACTION0_REG_ACTION0_LEN = 34 ;
+
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_ACTION1_REG_ACTION1 = 0 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_ACTION1_REG_ACTION1_LEN = 34 ;
+
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ00_PBH_HW1_ERROR = 0 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ00_PBH_HW2_ERROR = 1 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ00_PBH_PROTOCOL_ERROR = 2 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ00_PBH_OVERFLOW_ERROR = 3 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ01_PBH_HW1_ERROR = 4 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ01_PBH_HW2_ERROR = 5 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ01_PBH_PROTOCOL_ERROR = 6 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ01_PBH_OVERFLOW_ERROR = 7 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ02_PBH_HW1_ERROR = 8 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ02_PBH_HW2_ERROR = 9 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ02_PBH_PROTOCOL_ERROR = 10 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ02_PBH_OVERFLOW_ERROR = 11 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ03_PBH_HW1_ERROR = 12 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ03_PBH_HW2_ERROR = 13 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ03_PBH_PROTOCOL_ERROR = 14 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ03_PBH_OVERFLOW_ERROR = 15 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_16 = 16 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_17 = 17 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_18 = 18 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_19 = 19 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_20 = 20 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_21 = 21 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_22 = 22 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_23 = 23 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_24 = 24 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_25 = 25 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_26 = 26 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_27 = 27 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_28 = 28 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_29 = 29 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_30 = 30 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_31 = 31 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SCOM_ERR = 32 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SCOM_ERR_DUP = 33 ;
+
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ00_PBH_HW1_ERROR = 0 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ00_PBH_HW2_ERROR = 1 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ00_PBH_PROTOCOL_ERROR = 2 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ00_PBH_OVERFLOW_ERROR = 3 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ01_PBH_HW1_ERROR = 4 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ01_PBH_HW2_ERROR = 5 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ01_PBH_PROTOCOL_ERROR = 6 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ01_PBH_OVERFLOW_ERROR = 7 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ02_PBH_HW1_ERROR = 8 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ02_PBH_HW2_ERROR = 9 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ02_PBH_PROTOCOL_ERROR = 10 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ02_PBH_OVERFLOW_ERROR = 11 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ03_PBH_HW1_ERROR = 12 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ03_PBH_HW2_ERROR = 13 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ03_PBH_PROTOCOL_ERROR = 14 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ03_PBH_OVERFLOW_ERROR = 15 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_16 = 16 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_17 = 17 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_18 = 18 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_19 = 19 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_20 = 20 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_21 = 21 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_22 = 22 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_23 = 23 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_24 = 24 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_25 = 25 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_26 = 26 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_27 = 27 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_28 = 28 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_29 = 29 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_30 = 30 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_31 = 31 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_REG_SCOM_ERR = 32 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FIR_REG_SCOM_ERR_DUP = 33 ;
+
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FW_SCRATCH0_PB_WEST_FW_SCRATCH0 = 0 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FW_SCRATCH0_PB_WEST_FW_SCRATCH0_LEN = 64 ;
+
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FW_SCRATCH1_PB_WEST_FW_SCRATCH1 = 0 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_FW_SCRATCH1_PB_WEST_FW_SCRATCH1_LEN = 64 ;
+
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X0TOA0_EN = 0 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X0TOA1_EN = 1 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X0TOA2_EN = 2 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X0TOA3_EN = 3 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X1TOA0_EN = 4 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X1TOA1_EN = 5 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X1TOA2_EN = 6 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X1TOA3_EN = 7 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X2TOA0_EN = 8 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X2TOA1_EN = 9 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X2TOA2_EN = 10 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X2TOA3_EN = 11 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X0TOA0_GROUPID = 16 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X0TOA0_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X0TOA1_GROUPID = 20 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X0TOA1_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X0TOA2_GROUPID = 24 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X0TOA2_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X0TOA3_GROUPID = 28 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X0TOA3_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X1TOA0_GROUPID = 32 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X1TOA0_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X1TOA1_GROUPID = 36 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X1TOA1_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X1TOA2_GROUPID = 40 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X1TOA2_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X1TOA3_GROUPID = 44 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X1TOA3_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X2TOA0_GROUPID = 48 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X2TOA0_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X2TOA1_GROUPID = 52 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X2TOA1_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X2TOA2_GROUPID = 56 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X2TOA2_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X2TOA3_GROUPID = 60 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR_PB_CFG_WEST_LINK_X2TOA3_GROUPID_LEN = 4 ;
+
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X0TOA0_EN = 0 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X0TOA1_EN = 1 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X0TOA2_EN = 2 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X0TOA3_EN = 3 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X1TOA0_EN = 4 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X1TOA1_EN = 5 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X1TOA2_EN = 6 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X1TOA3_EN = 7 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X2TOA0_EN = 8 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X2TOA1_EN = 9 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X2TOA2_EN = 10 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X2TOA3_EN = 11 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X0TOA0_GROUPID = 16 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X0TOA0_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X0TOA1_GROUPID = 20 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X0TOA1_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X0TOA2_GROUPID = 24 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X0TOA2_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X0TOA3_GROUPID = 28 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X0TOA3_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X1TOA0_GROUPID = 32 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X1TOA0_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X1TOA1_GROUPID = 36 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X1TOA1_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X1TOA2_GROUPID = 40 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X1TOA2_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X1TOA3_GROUPID = 44 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X1TOA3_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X2TOA0_GROUPID = 48 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X2TOA0_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X2TOA1_GROUPID = 52 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X2TOA1_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X2TOA2_GROUPID = 56 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X2TOA2_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X2TOA3_GROUPID = 60 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT_PB_CFG_WEST_LINK_X2TOA3_GROUPID_LEN = 4 ;
+
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X0_EN = 0 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X1_EN = 1 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X2_EN = 2 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X3_EN = 3 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X4_EN = 4 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X5_EN = 5 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X6_EN = 6 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_NX0_ADDR_DIS = 8 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_NX1_ADDR_DIS = 9 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_NX2_ADDR_DIS = 10 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_NX3_ADDR_DIS = 11 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_NX4_ADDR_DIS = 12 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_NX5_ADDR_DIS = 13 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_NX6_ADDR_DIS = 14 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X0_CHIPID = 16 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X0_CHIPID_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X1_CHIPID = 19 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X1_CHIPID_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X2_CHIPID = 22 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X2_CHIPID_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X3_CHIPID = 25 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X3_CHIPID_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X4_CHIPID = 28 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X4_CHIPID_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X5_CHIPID = 31 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X5_CHIPID_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X6_CHIPID = 34 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X6_CHIPID_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_X_AGGREGATE = 37 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_X_FP_DISABLED = 48 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_X_INDIRECT_EN = 49 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_X_GATHER_ENABLE = 50 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_X_CMD_RATE = 56 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_X_CMD_RATE_LEN = 8 ;
+
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X0_EN = 0 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X1_EN = 1 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X2_EN = 2 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X3_EN = 3 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X4_EN = 4 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X5_EN = 5 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X6_EN = 6 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_NX0_ADDR_DIS = 8 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_NX1_ADDR_DIS = 9 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_NX2_ADDR_DIS = 10 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_NX3_ADDR_DIS = 11 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_NX4_ADDR_DIS = 12 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_NX5_ADDR_DIS = 13 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_NX6_ADDR_DIS = 14 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X0_CHIPID = 16 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X0_CHIPID_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X1_CHIPID = 19 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X1_CHIPID_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X2_CHIPID = 22 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X2_CHIPID_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X3_CHIPID = 25 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X3_CHIPID_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X4_CHIPID = 28 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X4_CHIPID_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X5_CHIPID = 31 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X5_CHIPID_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X6_CHIPID = 34 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X6_CHIPID_LEN = 3 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_X_AGGREGATE = 37 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_X_FP_DISABLED = 48 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_X_INDIRECT_EN = 49 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_X_GATHER_ENABLE = 50 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_X_CMD_RATE = 56 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_X_CMD_RATE_LEN = 8 ;
+
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_MASTER_CHIP = 0 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_TM_MASTER = 1 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_CHG_RATE_GP_MASTER = 2 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_CHG_RATE_SP_MASTER = 3 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_A0_EN = 4 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_A1_EN = 5 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_A2_EN = 6 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_A3_EN = 7 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_NA0_ADDR_DIS = 8 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_NA1_ADDR_DIS = 9 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_NA2_ADDR_DIS = 10 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_NA3_ADDR_DIS = 11 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_A0_GROUPID = 12 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_A0_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_A1_GROUPID = 16 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_A1_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_A2_GROUPID = 20 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_A2_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_A3_GROUPID = 24 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_A3_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_A_AGGREGATE = 28 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_HOP = 29 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_SMP_OPTICS = 30 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_PB_CFG_WEST_CAPI_MODE = 31 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_OPT0 = 32 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_OPT0_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_OPT1 = 34 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_OPT1_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_OPT2 = 36 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_OPT2_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_OPT3 = 38 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_OPT3_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_XLATE_ADDR_TO_ID = 40 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_XLATE_ADDR_TO_ID_LEN = 7 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_PB_CFG_WEST_SPARE01 = 47 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_PB_CFG_WEST_SPARE01_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_PB_CFG_WEST_A_INDIRECT_EN = 49 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_A_GATHER_ENABLE = 50 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_PB_CFG_WEST_SPARE2 = 51 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_PHYP_IS_GROUP = 52 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_ADDR_BAR = 53 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_PUMP = 54 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_DCACHE_CAPP = 55 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_A_CMD_RATE = 56 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_A_CMD_RATE_LEN = 8 ;
+
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_MASTER_CHIP = 0 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_TM_MASTER = 1 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_CHG_RATE_GP_MASTER = 2 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_CHG_RATE_SP_MASTER = 3 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_A0_EN = 4 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_A1_EN = 5 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_A2_EN = 6 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_A3_EN = 7 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_NA0_ADDR_DIS = 8 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_NA1_ADDR_DIS = 9 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_NA2_ADDR_DIS = 10 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_NA3_ADDR_DIS = 11 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_A0_GROUPID = 12 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_A0_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_A1_GROUPID = 16 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_A1_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_A2_GROUPID = 20 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_A2_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_A3_GROUPID = 24 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_A3_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_A_AGGREGATE = 28 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_HOP = 29 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_SMP_OPTICS = 30 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_CAPI = 31 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_OPT0 = 32 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_OPT0_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_OPT1 = 34 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_OPT1_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_OPT2 = 36 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_OPT2_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_OPT3 = 38 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_OPT3_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_XLATE_ADDR_TO_ID = 40 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_XLATE_ADDR_TO_ID_LEN = 7 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_PB_CFG_WEST_SPARE01 = 47 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_PB_CFG_WEST_SPARE01_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_PB_CFG_WEST_A_INDIRECT_EN = 49 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_A_GATHER_ENABLE = 50 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_PB_CFG_WEST_SPARE2 = 51 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_PHYP_IS_GROUP = 52 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_ADDR_BAR = 53 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_PUMP = 54 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_DCACHE_CAPP = 55 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_A_CMD_RATE = 56 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_A_CMD_RATE_LEN = 8 ;
+
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_MODE_PB_WEST_PBIXXX_INIT = 0 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_MODE_CFG_CHIP_IS_SYSTEM = 4 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_MODE_CFG_HNG_CHK_DISABLE = 8 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_MODE_DBG_CLR_MAX_HANG_STAGE = 9 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_MODE_CFG_SW_AB_WAIT = 12 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_MODE_CFG_SW_AB_WAIT_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_MODE_CFG_SP_HW_MARK = 16 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_MODE_CFG_SP_HW_MARK_LEN = 7 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_MODE_CFG_GP_HW_MARK = 23 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_MODE_CFG_GP_HW_MARK_LEN = 7 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_MODE_CFG_LCL_HW_MARK = 30 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_MODE_CFG_LCL_HW_MARK_LEN = 6 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_MODE_PB_CFG_WEST_CPU_RATIO_OVERRIDE = 36 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_MODE_PB_CFG_WEST_CPU_RATIO_OVERRIDE_LEN = 6 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_MODE_CFG_CHIP_ADDR_EXTENSION_MASK = 42 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_MODE_CFG_CHIP_ADDR_EXTENSION_MASK_LEN = 7 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_MODE_CFG_PPE_SERIAL_CONTROL = 56 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_MODE_CFG_REQ_GATHER_ENABLE = 57 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_MODE_CFG_SWITCH_CD_PULSE = 58 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_MODE_CFG_SWITCH_OPTION_AB = 59 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_MODE_CFG_SERIAL_READ_ENABLE = 60 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_MODE_CFG_SERIAL_READ_SEL = 61 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_MODE_CFG_SERIAL_READ_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_MODE_PB_CFG_WEST_RESET_ERROR_CAPTURE = 63 ;
+
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_SCONFIG_LOAD_CFG = 0 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_SCONFIG_LOAD_CFG_SLOW = 1 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_SCONFIG_LOAD_CFG_SHIFT_COUNT = 2 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_SCONFIG_LOAD_CFG_SHIFT_COUNT_LEN = 6 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_SCONFIG_LOAD_CFG_SELECT = 8 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_SCONFIG_LOAD_CFG_SELECT_LEN = 4 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_SCONFIG_LOAD_CFG_SHIFT_DATA = 12 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_SCONFIG_LOAD_CFG_SHIFT_DATA_LEN = 52 ;
+
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_SPARE_PB_WEST_SPARE = 0 ;
+static const uint8_t P9N2_PU_PB_WEST_SM0_PB_WEST_SPARE_PB_WEST_SPARE_LEN = 64 ;
+
+static const uint8_t P9N2_PEC_PCB_OPCG_GO_OPCGGO = 0 ;
+
+static const uint8_t P9N2_PEC_PCB_OPCG_STOP_OPCGSTOP = 0 ;
+
+static const uint8_t P9N2_PEC_PCS_M1_CONTROL_REG_CONTROL = 48 ;
+static const uint8_t P9N2_PEC_PCS_M1_CONTROL_REG_CONTROL_LEN = 16 ;
+
+static const uint8_t P9N2_PEC_PCS_M2_CONTROL_REG_CONTROL = 48 ;
+static const uint8_t P9N2_PEC_PCS_M2_CONTROL_REG_CONTROL_LEN = 16 ;
+
+static const uint8_t P9N2_PEC_PCS_M3_CONTROL_REG_CONTROL = 48 ;
+static const uint8_t P9N2_PEC_PCS_M3_CONTROL_REG_CONTROL_LEN = 16 ;
+
+static const uint8_t P9N2_PEC_PCS_M4_CONTROL_REG_CONTROL = 48 ;
+static const uint8_t P9N2_PEC_PCS_M4_CONTROL_REG_CONTROL_LEN = 16 ;
+
+static const uint8_t P9N2_PEC_PCS_SYS_CONTROL_REG_CONTROL = 48 ;
+static const uint8_t P9N2_PEC_PCS_SYS_CONTROL_REG_CONTROL_LEN = 16 ;
+
+static const uint8_t P9N2_PEC_PECAPP_CNTL_REG_PE_CAPP_EN = 0 ;
+static const uint8_t P9N2_PEC_PECAPP_CNTL_REG_PE_CAPP_P8_MODE = 1 ;
+static const uint8_t P9N2_PEC_PECAPP_CNTL_REG_PE_CAPP_NUM_MSG_ENG = 12 ;
+static const uint8_t P9N2_PEC_PECAPP_CNTL_REG_PE_CAPP_NUM_MSG_ENG_LEN = 4 ;
+static const uint8_t P9N2_PEC_PECAPP_CNTL_REG_PE_CAPP_APC_ENG = 16 ;
+static const uint8_t P9N2_PEC_PECAPP_CNTL_REG_PE_CAPP_APC_ENG_LEN = 48 ;
+
+static const uint8_t P9N2_PEC_PECAPP_SEC_BAR_PE_CAPP = 0 ;
+static const uint8_t P9N2_PEC_PECAPP_SEC_BAR_PE_CAPP_LEN = 26 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_ADDR_CONFIG_SIZE = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_ADDR_CONFIG_SIZE_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_ADDR_CONFIG_MATCH = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_ADDR_CONFIG_MATCH_LEN = 35 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_ADDR_CONFIG_RESERVED1 = 41 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_ADDR_CONFIG_RESERVED1_LEN = 3 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_ADDR_CONFIG_SIZE = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_ADDR_CONFIG_SIZE_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_ADDR_CONFIG_MATCH = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_ADDR_CONFIG_MATCH_LEN = 35 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_ADDR_CONFIG_RESERVED1 = 41 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_ADDR_CONFIG_RESERVED1_LEN = 3 ;
+
+static const uint8_t P9N2_PU_NPU2_SM2_PERF_ADDR_CONFIG_SIZE = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM2_PERF_ADDR_CONFIG_SIZE_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM2_PERF_ADDR_CONFIG_MATCH = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM2_PERF_ADDR_CONFIG_MATCH_LEN = 35 ;
+static const uint8_t P9N2_PU_NPU2_SM2_PERF_ADDR_CONFIG_RESERVED1 = 41 ;
+static const uint8_t P9N2_PU_NPU2_SM2_PERF_ADDR_CONFIG_RESERVED1_LEN = 3 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_ADDR_CONFIG_SIZE = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_ADDR_CONFIG_SIZE_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_ADDR_CONFIG_MATCH = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_ADDR_CONFIG_MATCH_LEN = 35 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_ADDR_CONFIG_RESERVED1 = 41 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_ADDR_CONFIG_RESERVED1_LEN = 3 ;
+
+static const uint8_t P9N2_PU_NPU0_SM2_PERF_ADDR_CONFIG_SIZE = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM2_PERF_ADDR_CONFIG_SIZE_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM2_PERF_ADDR_CONFIG_MATCH = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM2_PERF_ADDR_CONFIG_MATCH_LEN = 35 ;
+static const uint8_t P9N2_PU_NPU0_SM2_PERF_ADDR_CONFIG_RESERVED1 = 41 ;
+static const uint8_t P9N2_PU_NPU0_SM2_PERF_ADDR_CONFIG_RESERVED1_LEN = 3 ;
+
+static const uint8_t P9N2_PU_NPU2_SM1_PERF_ADDR_CONFIG_SIZE = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM1_PERF_ADDR_CONFIG_SIZE_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM1_PERF_ADDR_CONFIG_MATCH = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM1_PERF_ADDR_CONFIG_MATCH_LEN = 35 ;
+static const uint8_t P9N2_PU_NPU2_SM1_PERF_ADDR_CONFIG_RESERVED1 = 41 ;
+static const uint8_t P9N2_PU_NPU2_SM1_PERF_ADDR_CONFIG_RESERVED1_LEN = 3 ;
+
+static const uint8_t P9N2_PU_NPU0_CTL_PERF_ADDR_CONFIG_SIZE = 0 ;
+static const uint8_t P9N2_PU_NPU0_CTL_PERF_ADDR_CONFIG_SIZE_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_CTL_PERF_ADDR_CONFIG_MATCH = 6 ;
+static const uint8_t P9N2_PU_NPU0_CTL_PERF_ADDR_CONFIG_MATCH_LEN = 35 ;
+static const uint8_t P9N2_PU_NPU0_CTL_PERF_ADDR_CONFIG_RESERVED1 = 41 ;
+static const uint8_t P9N2_PU_NPU0_CTL_PERF_ADDR_CONFIG_RESERVED1_LEN = 3 ;
+
+static const uint8_t P9N2_PU_NPU2_CTL_PERF_ADDR_CONFIG_SIZE = 0 ;
+static const uint8_t P9N2_PU_NPU2_CTL_PERF_ADDR_CONFIG_SIZE_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_CTL_PERF_ADDR_CONFIG_MATCH = 6 ;
+static const uint8_t P9N2_PU_NPU2_CTL_PERF_ADDR_CONFIG_MATCH_LEN = 35 ;
+static const uint8_t P9N2_PU_NPU2_CTL_PERF_ADDR_CONFIG_RESERVED1 = 41 ;
+static const uint8_t P9N2_PU_NPU2_CTL_PERF_ADDR_CONFIG_RESERVED1_LEN = 3 ;
+
+static const uint8_t P9N2_PU_NPU0_SM1_PERF_ADDR_CONFIG_SIZE = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM1_PERF_ADDR_CONFIG_SIZE_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM1_PERF_ADDR_CONFIG_MATCH = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM1_PERF_ADDR_CONFIG_MATCH_LEN = 35 ;
+static const uint8_t P9N2_PU_NPU0_SM1_PERF_ADDR_CONFIG_RESERVED1 = 41 ;
+static const uint8_t P9N2_PU_NPU0_SM1_PERF_ADDR_CONFIG_RESERVED1_LEN = 3 ;
+
+static const uint8_t P9N2_PU_NPU2_DAT_PERF_ADDR_CONFIG_SIZE = 0 ;
+static const uint8_t P9N2_PU_NPU2_DAT_PERF_ADDR_CONFIG_SIZE_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_DAT_PERF_ADDR_CONFIG_MATCH = 6 ;
+static const uint8_t P9N2_PU_NPU2_DAT_PERF_ADDR_CONFIG_MATCH_LEN = 35 ;
+static const uint8_t P9N2_PU_NPU2_DAT_PERF_ADDR_CONFIG_RESERVED1 = 41 ;
+static const uint8_t P9N2_PU_NPU2_DAT_PERF_ADDR_CONFIG_RESERVED1_LEN = 3 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_ADDR_CONFIG_SIZE = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_ADDR_CONFIG_SIZE_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_ADDR_CONFIG_MATCH = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_ADDR_CONFIG_MATCH_LEN = 35 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_ADDR_CONFIG_RESERVED1 = 41 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_ADDR_CONFIG_RESERVED1_LEN = 3 ;
+
+static const uint8_t P9N2_PU_NPU0_DAT_PERF_ADDR_CONFIG_SIZE = 0 ;
+static const uint8_t P9N2_PU_NPU0_DAT_PERF_ADDR_CONFIG_SIZE_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_DAT_PERF_ADDR_CONFIG_MATCH = 6 ;
+static const uint8_t P9N2_PU_NPU0_DAT_PERF_ADDR_CONFIG_MATCH_LEN = 35 ;
+static const uint8_t P9N2_PU_NPU0_DAT_PERF_ADDR_CONFIG_RESERVED1 = 41 ;
+static const uint8_t P9N2_PU_NPU0_DAT_PERF_ADDR_CONFIG_RESERVED1_LEN = 3 ;
+
+static const uint8_t P9N2_PU_NPU1_SM1_PERF_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NPU1_SM1_PERF_CONFIG_RESETMODE = 1 ;
+static const uint8_t P9N2_PU_NPU1_SM1_PERF_CONFIG_FREEZEMODE = 2 ;
+static const uint8_t P9N2_PU_NPU1_SM1_PERF_CONFIG_DISABLE_PMISC = 3 ;
+static const uint8_t P9N2_PU_NPU1_SM1_PERF_CONFIG_PMISC_MODE = 4 ;
+static const uint8_t P9N2_PU_NPU1_SM1_PERF_CONFIG_CASCADE = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM1_PERF_CONFIG_CASCADE_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU1_SM1_PERF_CONFIG_PRESCALE_C0 = 8 ;
+static const uint8_t P9N2_PU_NPU1_SM1_PERF_CONFIG_PRESCALE_C0_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU1_SM1_PERF_CONFIG_PRESCALE_C1 = 10 ;
+static const uint8_t P9N2_PU_NPU1_SM1_PERF_CONFIG_PRESCALE_C1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU1_SM1_PERF_CONFIG_PRESCALE_C2 = 12 ;
+static const uint8_t P9N2_PU_NPU1_SM1_PERF_CONFIG_PRESCALE_C2_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU1_SM1_PERF_CONFIG_PRESCALE_C3 = 14 ;
+static const uint8_t P9N2_PU_NPU1_SM1_PERF_CONFIG_PRESCALE_C3_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU1_SM1_PERF_CONFIG_EVENT0 = 16 ;
+static const uint8_t P9N2_PU_NPU1_SM1_PERF_CONFIG_EVENT0_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU1_SM1_PERF_CONFIG_EVENT1 = 24 ;
+static const uint8_t P9N2_PU_NPU1_SM1_PERF_CONFIG_EVENT1_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU1_SM1_PERF_CONFIG_EVENT2 = 32 ;
+static const uint8_t P9N2_PU_NPU1_SM1_PERF_CONFIG_EVENT2_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU1_SM1_PERF_CONFIG_EVENT3 = 40 ;
+static const uint8_t P9N2_PU_NPU1_SM1_PERF_CONFIG_EVENT3_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU1_SM1_PERF_CONFIG_LATENCY = 48 ;
+static const uint8_t P9N2_PU_NPU1_SM1_PERF_CONFIG_LATENCY_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU1_SM1_PERF_CONFIG_RESERVED = 51 ;
+static const uint8_t P9N2_PU_NPU1_SM1_PERF_CONFIG_RESERVED_LEN = 13 ;
+
+static const uint8_t P9N2_PU_NPU0_CTL_PERF_CONFIG_LATSTART = 0 ;
+static const uint8_t P9N2_PU_NPU0_CTL_PERF_CONFIG_LATSTART_LEN = 9 ;
+static const uint8_t P9N2_PU_NPU0_CTL_PERF_CONFIG_LATCANCEL = 9 ;
+static const uint8_t P9N2_PU_NPU0_CTL_PERF_CONFIG_LATCANCEL_LEN = 9 ;
+static const uint8_t P9N2_PU_NPU0_CTL_PERF_CONFIG_LATFINISH = 18 ;
+static const uint8_t P9N2_PU_NPU0_CTL_PERF_CONFIG_LATFINISH_LEN = 9 ;
+static const uint8_t P9N2_PU_NPU0_CTL_PERF_CONFIG_RESERVED1 = 27 ;
+static const uint8_t P9N2_PU_NPU0_CTL_PERF_CONFIG_EVENT0 = 28 ;
+static const uint8_t P9N2_PU_NPU0_CTL_PERF_CONFIG_EVENT0_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU0_CTL_PERF_CONFIG_EVENT1 = 36 ;
+static const uint8_t P9N2_PU_NPU0_CTL_PERF_CONFIG_EVENT1_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU0_CTL_PERF_CONFIG_EVENT2 = 44 ;
+static const uint8_t P9N2_PU_NPU0_CTL_PERF_CONFIG_EVENT2_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU0_CTL_PERF_CONFIG_EVENT3 = 52 ;
+static const uint8_t P9N2_PU_NPU0_CTL_PERF_CONFIG_EVENT3_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU0_CTL_PERF_CONFIG_RESERVED2 = 60 ;
+static const uint8_t P9N2_PU_NPU0_CTL_PERF_CONFIG_RESERVED2_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU0_CTL_PERF_CONFIG_LATFILTER = 62 ;
+static const uint8_t P9N2_PU_NPU0_CTL_PERF_CONFIG_ACT = 63 ;
+
+static const uint8_t P9N2_PU_NPU0_SM1_PERF_CONFIG_LATSTART = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM1_PERF_CONFIG_LATSTART_LEN = 9 ;
+static const uint8_t P9N2_PU_NPU0_SM1_PERF_CONFIG_LATCANCEL = 9 ;
+static const uint8_t P9N2_PU_NPU0_SM1_PERF_CONFIG_LATCANCEL_LEN = 9 ;
+static const uint8_t P9N2_PU_NPU0_SM1_PERF_CONFIG_LATFINISH = 18 ;
+static const uint8_t P9N2_PU_NPU0_SM1_PERF_CONFIG_LATFINISH_LEN = 9 ;
+static const uint8_t P9N2_PU_NPU0_SM1_PERF_CONFIG_RESERVED1 = 27 ;
+static const uint8_t P9N2_PU_NPU0_SM1_PERF_CONFIG_EVENT0 = 28 ;
+static const uint8_t P9N2_PU_NPU0_SM1_PERF_CONFIG_EVENT0_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM1_PERF_CONFIG_EVENT1 = 36 ;
+static const uint8_t P9N2_PU_NPU0_SM1_PERF_CONFIG_EVENT1_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM1_PERF_CONFIG_EVENT2 = 44 ;
+static const uint8_t P9N2_PU_NPU0_SM1_PERF_CONFIG_EVENT2_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM1_PERF_CONFIG_EVENT3 = 52 ;
+static const uint8_t P9N2_PU_NPU0_SM1_PERF_CONFIG_EVENT3_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM1_PERF_CONFIG_RESERVED2 = 60 ;
+static const uint8_t P9N2_PU_NPU0_SM1_PERF_CONFIG_RESERVED2_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM1_PERF_CONFIG_LATFILTER = 62 ;
+static const uint8_t P9N2_PU_NPU0_SM1_PERF_CONFIG_ACT = 63 ;
+
+static const uint8_t P9N2__SM1_PERF_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2__SM1_PERF_CONFIG_RESETMODE = 1 ;
+static const uint8_t P9N2__SM1_PERF_CONFIG_FREEZEMODE = 2 ;
+static const uint8_t P9N2__SM1_PERF_CONFIG_DISABLE_PMISC = 3 ;
+static const uint8_t P9N2__SM1_PERF_CONFIG_PMISC_MODE = 4 ;
+static const uint8_t P9N2__SM1_PERF_CONFIG_CASCADE = 5 ;
+static const uint8_t P9N2__SM1_PERF_CONFIG_CASCADE_LEN = 3 ;
+static const uint8_t P9N2__SM1_PERF_CONFIG_PRESCALE_C0 = 8 ;
+static const uint8_t P9N2__SM1_PERF_CONFIG_PRESCALE_C0_LEN = 2 ;
+static const uint8_t P9N2__SM1_PERF_CONFIG_PRESCALE_C1 = 10 ;
+static const uint8_t P9N2__SM1_PERF_CONFIG_PRESCALE_C1_LEN = 2 ;
+static const uint8_t P9N2__SM1_PERF_CONFIG_PRESCALE_C2 = 12 ;
+static const uint8_t P9N2__SM1_PERF_CONFIG_PRESCALE_C2_LEN = 2 ;
+static const uint8_t P9N2__SM1_PERF_CONFIG_PRESCALE_C3 = 14 ;
+static const uint8_t P9N2__SM1_PERF_CONFIG_PRESCALE_C3_LEN = 2 ;
+static const uint8_t P9N2__SM1_PERF_CONFIG_EVENT0 = 16 ;
+static const uint8_t P9N2__SM1_PERF_CONFIG_EVENT0_LEN = 8 ;
+static const uint8_t P9N2__SM1_PERF_CONFIG_EVENT1 = 24 ;
+static const uint8_t P9N2__SM1_PERF_CONFIG_EVENT1_LEN = 8 ;
+static const uint8_t P9N2__SM1_PERF_CONFIG_EVENT2 = 32 ;
+static const uint8_t P9N2__SM1_PERF_CONFIG_EVENT2_LEN = 8 ;
+static const uint8_t P9N2__SM1_PERF_CONFIG_EVENT3 = 40 ;
+static const uint8_t P9N2__SM1_PERF_CONFIG_EVENT3_LEN = 8 ;
+static const uint8_t P9N2__SM1_PERF_CONFIG_LATENCY = 48 ;
+static const uint8_t P9N2__SM1_PERF_CONFIG_LATENCY_LEN = 3 ;
+static const uint8_t P9N2__SM1_PERF_CONFIG_RESERVED = 51 ;
+static const uint8_t P9N2__SM1_PERF_CONFIG_RESERVED_LEN = 13 ;
+
+static const uint8_t P9N2_PU_NPU0_SM0_PERF_CONFIG_LATSTART = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM0_PERF_CONFIG_LATSTART_LEN = 9 ;
+static const uint8_t P9N2_PU_NPU0_SM0_PERF_CONFIG_LATCANCEL = 9 ;
+static const uint8_t P9N2_PU_NPU0_SM0_PERF_CONFIG_LATCANCEL_LEN = 9 ;
+static const uint8_t P9N2_PU_NPU0_SM0_PERF_CONFIG_LATFINISH = 18 ;
+static const uint8_t P9N2_PU_NPU0_SM0_PERF_CONFIG_LATFINISH_LEN = 9 ;
+static const uint8_t P9N2_PU_NPU0_SM0_PERF_CONFIG_RESERVED1 = 27 ;
+static const uint8_t P9N2_PU_NPU0_SM0_PERF_CONFIG_EVENT0 = 28 ;
+static const uint8_t P9N2_PU_NPU0_SM0_PERF_CONFIG_EVENT0_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM0_PERF_CONFIG_EVENT1 = 36 ;
+static const uint8_t P9N2_PU_NPU0_SM0_PERF_CONFIG_EVENT1_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM0_PERF_CONFIG_EVENT2 = 44 ;
+static const uint8_t P9N2_PU_NPU0_SM0_PERF_CONFIG_EVENT2_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM0_PERF_CONFIG_EVENT3 = 52 ;
+static const uint8_t P9N2_PU_NPU0_SM0_PERF_CONFIG_EVENT3_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM0_PERF_CONFIG_RESERVED2 = 60 ;
+static const uint8_t P9N2_PU_NPU0_SM0_PERF_CONFIG_RESERVED2_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM0_PERF_CONFIG_LATFILTER = 62 ;
+static const uint8_t P9N2_PU_NPU0_SM0_PERF_CONFIG_ACT = 63 ;
+
+static const uint8_t P9N2_PU_NPU2_NTL0_PERF_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_PERF_CONFIG_RESETMODE = 1 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_PERF_CONFIG_FREEZEMODE = 2 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_PERF_CONFIG_DISABLE_PMISC = 3 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_PERF_CONFIG_PMISC_MODE = 4 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_PERF_CONFIG_CASCADE = 5 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_PERF_CONFIG_CASCADE_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_PERF_CONFIG_PRESCALE_C0 = 8 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_PERF_CONFIG_PRESCALE_C0_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_PERF_CONFIG_PRESCALE_C1 = 10 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_PERF_CONFIG_PRESCALE_C1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_PERF_CONFIG_PRESCALE_C2 = 12 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_PERF_CONFIG_PRESCALE_C2_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_PERF_CONFIG_PRESCALE_C3 = 14 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_PERF_CONFIG_PRESCALE_C3_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_PERF_CONFIG_EVENT0 = 16 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_PERF_CONFIG_EVENT0_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_PERF_CONFIG_EVENT1 = 24 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_PERF_CONFIG_EVENT1_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_PERF_CONFIG_EVENT2 = 32 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_PERF_CONFIG_EVENT2_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_PERF_CONFIG_EVENT3 = 40 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_PERF_CONFIG_EVENT3_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_PERF_CONFIG_LATSTART = 48 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_PERF_CONFIG_LATSTART_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_PERF_CONFIG_LATCANCEL = 53 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_PERF_CONFIG_LATCANCEL_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_PERF_CONFIG_LATFINISH = 58 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_PERF_CONFIG_LATFINISH_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_PERF_CONFIG_LATFILTER = 63 ;
+
+static const uint8_t P9N2_PU_NPU0_SM3_PERF_CONFIG_LATSTART = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM3_PERF_CONFIG_LATSTART_LEN = 9 ;
+static const uint8_t P9N2_PU_NPU0_SM3_PERF_CONFIG_LATCANCEL = 9 ;
+static const uint8_t P9N2_PU_NPU0_SM3_PERF_CONFIG_LATCANCEL_LEN = 9 ;
+static const uint8_t P9N2_PU_NPU0_SM3_PERF_CONFIG_LATFINISH = 18 ;
+static const uint8_t P9N2_PU_NPU0_SM3_PERF_CONFIG_LATFINISH_LEN = 9 ;
+static const uint8_t P9N2_PU_NPU0_SM3_PERF_CONFIG_RESERVED1 = 27 ;
+static const uint8_t P9N2_PU_NPU0_SM3_PERF_CONFIG_EVENT0 = 28 ;
+static const uint8_t P9N2_PU_NPU0_SM3_PERF_CONFIG_EVENT0_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM3_PERF_CONFIG_EVENT1 = 36 ;
+static const uint8_t P9N2_PU_NPU0_SM3_PERF_CONFIG_EVENT1_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM3_PERF_CONFIG_EVENT2 = 44 ;
+static const uint8_t P9N2_PU_NPU0_SM3_PERF_CONFIG_EVENT2_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM3_PERF_CONFIG_EVENT3 = 52 ;
+static const uint8_t P9N2_PU_NPU0_SM3_PERF_CONFIG_EVENT3_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM3_PERF_CONFIG_RESERVED2 = 60 ;
+static const uint8_t P9N2_PU_NPU0_SM3_PERF_CONFIG_RESERVED2_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM3_PERF_CONFIG_LATFILTER = 62 ;
+static const uint8_t P9N2_PU_NPU0_SM3_PERF_CONFIG_ACT = 63 ;
+
+static const uint8_t P9N2_PU_NPU2_SM3_PERF_CONFIG_LATSTART = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM3_PERF_CONFIG_LATSTART_LEN = 9 ;
+static const uint8_t P9N2_PU_NPU2_SM3_PERF_CONFIG_LATCANCEL = 9 ;
+static const uint8_t P9N2_PU_NPU2_SM3_PERF_CONFIG_LATCANCEL_LEN = 9 ;
+static const uint8_t P9N2_PU_NPU2_SM3_PERF_CONFIG_LATFINISH = 18 ;
+static const uint8_t P9N2_PU_NPU2_SM3_PERF_CONFIG_LATFINISH_LEN = 9 ;
+static const uint8_t P9N2_PU_NPU2_SM3_PERF_CONFIG_RESERVED1 = 27 ;
+static const uint8_t P9N2_PU_NPU2_SM3_PERF_CONFIG_EVENT0 = 28 ;
+static const uint8_t P9N2_PU_NPU2_SM3_PERF_CONFIG_EVENT0_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM3_PERF_CONFIG_EVENT1 = 36 ;
+static const uint8_t P9N2_PU_NPU2_SM3_PERF_CONFIG_EVENT1_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM3_PERF_CONFIG_EVENT2 = 44 ;
+static const uint8_t P9N2_PU_NPU2_SM3_PERF_CONFIG_EVENT2_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM3_PERF_CONFIG_EVENT3 = 52 ;
+static const uint8_t P9N2_PU_NPU2_SM3_PERF_CONFIG_EVENT3_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM3_PERF_CONFIG_RESERVED2 = 60 ;
+static const uint8_t P9N2_PU_NPU2_SM3_PERF_CONFIG_RESERVED2_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM3_PERF_CONFIG_LATFILTER = 62 ;
+static const uint8_t P9N2_PU_NPU2_SM3_PERF_CONFIG_ACT = 63 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM0_PERF_CONFIG_LATSTART = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_PERF_CONFIG_LATSTART_LEN = 9 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_PERF_CONFIG_LATCANCEL = 9 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_PERF_CONFIG_LATCANCEL_LEN = 9 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_PERF_CONFIG_LATFINISH = 18 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_PERF_CONFIG_LATFINISH_LEN = 9 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_PERF_CONFIG_RESERVED1 = 27 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_PERF_CONFIG_EVENT0 = 28 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_PERF_CONFIG_EVENT0_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_PERF_CONFIG_EVENT1 = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_PERF_CONFIG_EVENT1_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_PERF_CONFIG_EVENT2 = 44 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_PERF_CONFIG_EVENT2_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_PERF_CONFIG_EVENT3 = 52 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_PERF_CONFIG_EVENT3_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_PERF_CONFIG_RESERVED2 = 60 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_PERF_CONFIG_RESERVED2_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_PERF_CONFIG_LATFILTER = 62 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_PERF_CONFIG_ACT = 63 ;
+
+static const uint8_t P9N2__SM0_PERF_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2__SM0_PERF_CONFIG_RESETMODE = 1 ;
+static const uint8_t P9N2__SM0_PERF_CONFIG_FREEZEMODE = 2 ;
+static const uint8_t P9N2__SM0_PERF_CONFIG_DISABLE_PMISC = 3 ;
+static const uint8_t P9N2__SM0_PERF_CONFIG_PMISC_MODE = 4 ;
+static const uint8_t P9N2__SM0_PERF_CONFIG_CASCADE = 5 ;
+static const uint8_t P9N2__SM0_PERF_CONFIG_CASCADE_LEN = 3 ;
+static const uint8_t P9N2__SM0_PERF_CONFIG_PRESCALE_C0 = 8 ;
+static const uint8_t P9N2__SM0_PERF_CONFIG_PRESCALE_C0_LEN = 2 ;
+static const uint8_t P9N2__SM0_PERF_CONFIG_PRESCALE_C1 = 10 ;
+static const uint8_t P9N2__SM0_PERF_CONFIG_PRESCALE_C1_LEN = 2 ;
+static const uint8_t P9N2__SM0_PERF_CONFIG_PRESCALE_C2 = 12 ;
+static const uint8_t P9N2__SM0_PERF_CONFIG_PRESCALE_C2_LEN = 2 ;
+static const uint8_t P9N2__SM0_PERF_CONFIG_PRESCALE_C3 = 14 ;
+static const uint8_t P9N2__SM0_PERF_CONFIG_PRESCALE_C3_LEN = 2 ;
+static const uint8_t P9N2__SM0_PERF_CONFIG_EVENT0 = 16 ;
+static const uint8_t P9N2__SM0_PERF_CONFIG_EVENT0_LEN = 8 ;
+static const uint8_t P9N2__SM0_PERF_CONFIG_EVENT1 = 24 ;
+static const uint8_t P9N2__SM0_PERF_CONFIG_EVENT1_LEN = 8 ;
+static const uint8_t P9N2__SM0_PERF_CONFIG_EVENT2 = 32 ;
+static const uint8_t P9N2__SM0_PERF_CONFIG_EVENT2_LEN = 8 ;
+static const uint8_t P9N2__SM0_PERF_CONFIG_EVENT3 = 40 ;
+static const uint8_t P9N2__SM0_PERF_CONFIG_EVENT3_LEN = 8 ;
+static const uint8_t P9N2__SM0_PERF_CONFIG_LATENCY = 48 ;
+static const uint8_t P9N2__SM0_PERF_CONFIG_LATENCY_LEN = 3 ;
+static const uint8_t P9N2__SM0_PERF_CONFIG_RESERVED = 51 ;
+static const uint8_t P9N2__SM0_PERF_CONFIG_RESERVED_LEN = 13 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_CONFIG_LATSTART = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_CONFIG_LATSTART_LEN = 9 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_CONFIG_LATCANCEL = 9 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_CONFIG_LATCANCEL_LEN = 9 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_CONFIG_LATFINISH = 18 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_CONFIG_LATFINISH_LEN = 9 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_CONFIG_RESERVED1 = 27 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_CONFIG_EVENT0 = 28 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_CONFIG_EVENT0_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_CONFIG_EVENT1 = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_CONFIG_EVENT1_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_CONFIG_EVENT2 = 44 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_CONFIG_EVENT2_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_CONFIG_EVENT3 = 52 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_CONFIG_EVENT3_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_CONFIG_RESERVED2 = 60 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_CONFIG_RESERVED2_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_CONFIG_LATFILTER = 62 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_CONFIG_ACT = 63 ;
+
+static const uint8_t P9N2_PU_NPU2_SM1_PERF_CONFIG_LATSTART = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM1_PERF_CONFIG_LATSTART_LEN = 9 ;
+static const uint8_t P9N2_PU_NPU2_SM1_PERF_CONFIG_LATCANCEL = 9 ;
+static const uint8_t P9N2_PU_NPU2_SM1_PERF_CONFIG_LATCANCEL_LEN = 9 ;
+static const uint8_t P9N2_PU_NPU2_SM1_PERF_CONFIG_LATFINISH = 18 ;
+static const uint8_t P9N2_PU_NPU2_SM1_PERF_CONFIG_LATFINISH_LEN = 9 ;
+static const uint8_t P9N2_PU_NPU2_SM1_PERF_CONFIG_RESERVED1 = 27 ;
+static const uint8_t P9N2_PU_NPU2_SM1_PERF_CONFIG_EVENT0 = 28 ;
+static const uint8_t P9N2_PU_NPU2_SM1_PERF_CONFIG_EVENT0_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM1_PERF_CONFIG_EVENT1 = 36 ;
+static const uint8_t P9N2_PU_NPU2_SM1_PERF_CONFIG_EVENT1_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM1_PERF_CONFIG_EVENT2 = 44 ;
+static const uint8_t P9N2_PU_NPU2_SM1_PERF_CONFIG_EVENT2_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM1_PERF_CONFIG_EVENT3 = 52 ;
+static const uint8_t P9N2_PU_NPU2_SM1_PERF_CONFIG_EVENT3_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM1_PERF_CONFIG_RESERVED2 = 60 ;
+static const uint8_t P9N2_PU_NPU2_SM1_PERF_CONFIG_RESERVED2_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM1_PERF_CONFIG_LATFILTER = 62 ;
+static const uint8_t P9N2_PU_NPU2_SM1_PERF_CONFIG_ACT = 63 ;
+
+static const uint8_t P9N2_PU_NPU_SM0_PERF_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NPU_SM0_PERF_CONFIG_RESETMODE = 1 ;
+static const uint8_t P9N2_PU_NPU_SM0_PERF_CONFIG_FREEZEMODE = 2 ;
+static const uint8_t P9N2_PU_NPU_SM0_PERF_CONFIG_DISABLE_PMISC = 3 ;
+static const uint8_t P9N2_PU_NPU_SM0_PERF_CONFIG_PMISC_MODE = 4 ;
+static const uint8_t P9N2_PU_NPU_SM0_PERF_CONFIG_CASCADE = 5 ;
+static const uint8_t P9N2_PU_NPU_SM0_PERF_CONFIG_CASCADE_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_SM0_PERF_CONFIG_PRESCALE_C0 = 8 ;
+static const uint8_t P9N2_PU_NPU_SM0_PERF_CONFIG_PRESCALE_C0_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_SM0_PERF_CONFIG_PRESCALE_C1 = 10 ;
+static const uint8_t P9N2_PU_NPU_SM0_PERF_CONFIG_PRESCALE_C1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_SM0_PERF_CONFIG_PRESCALE_C2 = 12 ;
+static const uint8_t P9N2_PU_NPU_SM0_PERF_CONFIG_PRESCALE_C2_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_SM0_PERF_CONFIG_PRESCALE_C3 = 14 ;
+static const uint8_t P9N2_PU_NPU_SM0_PERF_CONFIG_PRESCALE_C3_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_SM0_PERF_CONFIG_EVENT0 = 16 ;
+static const uint8_t P9N2_PU_NPU_SM0_PERF_CONFIG_EVENT0_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_SM0_PERF_CONFIG_EVENT1 = 24 ;
+static const uint8_t P9N2_PU_NPU_SM0_PERF_CONFIG_EVENT1_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_SM0_PERF_CONFIG_EVENT2 = 32 ;
+static const uint8_t P9N2_PU_NPU_SM0_PERF_CONFIG_EVENT2_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_SM0_PERF_CONFIG_EVENT3 = 40 ;
+static const uint8_t P9N2_PU_NPU_SM0_PERF_CONFIG_EVENT3_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_SM0_PERF_CONFIG_LATENCY = 48 ;
+static const uint8_t P9N2_PU_NPU_SM0_PERF_CONFIG_LATENCY_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_SM0_PERF_CONFIG_RESERVED = 51 ;
+static const uint8_t P9N2_PU_NPU_SM0_PERF_CONFIG_RESERVED_LEN = 13 ;
+
+static const uint8_t P9N2_PU_NPU_SM1_PERF_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NPU_SM1_PERF_CONFIG_RESETMODE = 1 ;
+static const uint8_t P9N2_PU_NPU_SM1_PERF_CONFIG_FREEZEMODE = 2 ;
+static const uint8_t P9N2_PU_NPU_SM1_PERF_CONFIG_DISABLE_PMISC = 3 ;
+static const uint8_t P9N2_PU_NPU_SM1_PERF_CONFIG_PMISC_MODE = 4 ;
+static const uint8_t P9N2_PU_NPU_SM1_PERF_CONFIG_CASCADE = 5 ;
+static const uint8_t P9N2_PU_NPU_SM1_PERF_CONFIG_CASCADE_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_SM1_PERF_CONFIG_PRESCALE_C0 = 8 ;
+static const uint8_t P9N2_PU_NPU_SM1_PERF_CONFIG_PRESCALE_C0_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_SM1_PERF_CONFIG_PRESCALE_C1 = 10 ;
+static const uint8_t P9N2_PU_NPU_SM1_PERF_CONFIG_PRESCALE_C1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_SM1_PERF_CONFIG_PRESCALE_C2 = 12 ;
+static const uint8_t P9N2_PU_NPU_SM1_PERF_CONFIG_PRESCALE_C2_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_SM1_PERF_CONFIG_PRESCALE_C3 = 14 ;
+static const uint8_t P9N2_PU_NPU_SM1_PERF_CONFIG_PRESCALE_C3_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_SM1_PERF_CONFIG_EVENT0 = 16 ;
+static const uint8_t P9N2_PU_NPU_SM1_PERF_CONFIG_EVENT0_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_SM1_PERF_CONFIG_EVENT1 = 24 ;
+static const uint8_t P9N2_PU_NPU_SM1_PERF_CONFIG_EVENT1_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_SM1_PERF_CONFIG_EVENT2 = 32 ;
+static const uint8_t P9N2_PU_NPU_SM1_PERF_CONFIG_EVENT2_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_SM1_PERF_CONFIG_EVENT3 = 40 ;
+static const uint8_t P9N2_PU_NPU_SM1_PERF_CONFIG_EVENT3_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_SM1_PERF_CONFIG_LATENCY = 48 ;
+static const uint8_t P9N2_PU_NPU_SM1_PERF_CONFIG_LATENCY_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_SM1_PERF_CONFIG_RESERVED = 51 ;
+static const uint8_t P9N2_PU_NPU_SM1_PERF_CONFIG_RESERVED_LEN = 13 ;
+
+static const uint8_t P9N2_PU_NPU2_SM0_PERF_CONFIG_LATSTART = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM0_PERF_CONFIG_LATSTART_LEN = 9 ;
+static const uint8_t P9N2_PU_NPU2_SM0_PERF_CONFIG_LATCANCEL = 9 ;
+static const uint8_t P9N2_PU_NPU2_SM0_PERF_CONFIG_LATCANCEL_LEN = 9 ;
+static const uint8_t P9N2_PU_NPU2_SM0_PERF_CONFIG_LATFINISH = 18 ;
+static const uint8_t P9N2_PU_NPU2_SM0_PERF_CONFIG_LATFINISH_LEN = 9 ;
+static const uint8_t P9N2_PU_NPU2_SM0_PERF_CONFIG_RESERVED1 = 27 ;
+static const uint8_t P9N2_PU_NPU2_SM0_PERF_CONFIG_EVENT0 = 28 ;
+static const uint8_t P9N2_PU_NPU2_SM0_PERF_CONFIG_EVENT0_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM0_PERF_CONFIG_EVENT1 = 36 ;
+static const uint8_t P9N2_PU_NPU2_SM0_PERF_CONFIG_EVENT1_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM0_PERF_CONFIG_EVENT2 = 44 ;
+static const uint8_t P9N2_PU_NPU2_SM0_PERF_CONFIG_EVENT2_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM0_PERF_CONFIG_EVENT3 = 52 ;
+static const uint8_t P9N2_PU_NPU2_SM0_PERF_CONFIG_EVENT3_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM0_PERF_CONFIG_RESERVED2 = 60 ;
+static const uint8_t P9N2_PU_NPU2_SM0_PERF_CONFIG_RESERVED2_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM0_PERF_CONFIG_LATFILTER = 62 ;
+static const uint8_t P9N2_PU_NPU2_SM0_PERF_CONFIG_ACT = 63 ;
+
+static const uint8_t P9N2_PU_NPU2_CTL_PERF_CONFIG_LATSTART = 0 ;
+static const uint8_t P9N2_PU_NPU2_CTL_PERF_CONFIG_LATSTART_LEN = 9 ;
+static const uint8_t P9N2_PU_NPU2_CTL_PERF_CONFIG_LATCANCEL = 9 ;
+static const uint8_t P9N2_PU_NPU2_CTL_PERF_CONFIG_LATCANCEL_LEN = 9 ;
+static const uint8_t P9N2_PU_NPU2_CTL_PERF_CONFIG_LATFINISH = 18 ;
+static const uint8_t P9N2_PU_NPU2_CTL_PERF_CONFIG_LATFINISH_LEN = 9 ;
+static const uint8_t P9N2_PU_NPU2_CTL_PERF_CONFIG_RESERVED1 = 27 ;
+static const uint8_t P9N2_PU_NPU2_CTL_PERF_CONFIG_EVENT0 = 28 ;
+static const uint8_t P9N2_PU_NPU2_CTL_PERF_CONFIG_EVENT0_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU2_CTL_PERF_CONFIG_EVENT1 = 36 ;
+static const uint8_t P9N2_PU_NPU2_CTL_PERF_CONFIG_EVENT1_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU2_CTL_PERF_CONFIG_EVENT2 = 44 ;
+static const uint8_t P9N2_PU_NPU2_CTL_PERF_CONFIG_EVENT2_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU2_CTL_PERF_CONFIG_EVENT3 = 52 ;
+static const uint8_t P9N2_PU_NPU2_CTL_PERF_CONFIG_EVENT3_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU2_CTL_PERF_CONFIG_RESERVED2 = 60 ;
+static const uint8_t P9N2_PU_NPU2_CTL_PERF_CONFIG_RESERVED2_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_CTL_PERF_CONFIG_LATFILTER = 62 ;
+static const uint8_t P9N2_PU_NPU2_CTL_PERF_CONFIG_ACT = 63 ;
+
+static const uint8_t P9N2_NV_PERF_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_NV_PERF_CONFIG_RESETMODE = 1 ;
+static const uint8_t P9N2_NV_PERF_CONFIG_FREEZEMODE = 2 ;
+static const uint8_t P9N2_NV_PERF_CONFIG_DISABLE_PMISC = 3 ;
+static const uint8_t P9N2_NV_PERF_CONFIG_PMISC_MODE = 4 ;
+static const uint8_t P9N2_NV_PERF_CONFIG_CASCADE = 5 ;
+static const uint8_t P9N2_NV_PERF_CONFIG_CASCADE_LEN = 3 ;
+static const uint8_t P9N2_NV_PERF_CONFIG_PRESCALE_C0 = 8 ;
+static const uint8_t P9N2_NV_PERF_CONFIG_PRESCALE_C0_LEN = 2 ;
+static const uint8_t P9N2_NV_PERF_CONFIG_PRESCALE_C1 = 10 ;
+static const uint8_t P9N2_NV_PERF_CONFIG_PRESCALE_C1_LEN = 2 ;
+static const uint8_t P9N2_NV_PERF_CONFIG_PRESCALE_C2 = 12 ;
+static const uint8_t P9N2_NV_PERF_CONFIG_PRESCALE_C2_LEN = 2 ;
+static const uint8_t P9N2_NV_PERF_CONFIG_PRESCALE_C3 = 14 ;
+static const uint8_t P9N2_NV_PERF_CONFIG_PRESCALE_C3_LEN = 2 ;
+static const uint8_t P9N2_NV_PERF_CONFIG_EVENT0 = 16 ;
+static const uint8_t P9N2_NV_PERF_CONFIG_EVENT0_LEN = 8 ;
+static const uint8_t P9N2_NV_PERF_CONFIG_EVENT1 = 24 ;
+static const uint8_t P9N2_NV_PERF_CONFIG_EVENT1_LEN = 8 ;
+static const uint8_t P9N2_NV_PERF_CONFIG_EVENT2 = 32 ;
+static const uint8_t P9N2_NV_PERF_CONFIG_EVENT2_LEN = 8 ;
+static const uint8_t P9N2_NV_PERF_CONFIG_EVENT3 = 40 ;
+static const uint8_t P9N2_NV_PERF_CONFIG_EVENT3_LEN = 8 ;
+static const uint8_t P9N2_NV_PERF_CONFIG_LATSTART = 48 ;
+static const uint8_t P9N2_NV_PERF_CONFIG_LATSTART_LEN = 5 ;
+static const uint8_t P9N2_NV_PERF_CONFIG_LATCANCEL = 53 ;
+static const uint8_t P9N2_NV_PERF_CONFIG_LATCANCEL_LEN = 5 ;
+static const uint8_t P9N2_NV_PERF_CONFIG_LATFINISH = 58 ;
+static const uint8_t P9N2_NV_PERF_CONFIG_LATFINISH_LEN = 5 ;
+static const uint8_t P9N2_NV_PERF_CONFIG_LATFILTER = 63 ;
+
+static const uint8_t P9N2_PU_NPU1_SM0_PERF_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NPU1_SM0_PERF_CONFIG_RESETMODE = 1 ;
+static const uint8_t P9N2_PU_NPU1_SM0_PERF_CONFIG_FREEZEMODE = 2 ;
+static const uint8_t P9N2_PU_NPU1_SM0_PERF_CONFIG_DISABLE_PMISC = 3 ;
+static const uint8_t P9N2_PU_NPU1_SM0_PERF_CONFIG_PMISC_MODE = 4 ;
+static const uint8_t P9N2_PU_NPU1_SM0_PERF_CONFIG_CASCADE = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM0_PERF_CONFIG_CASCADE_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU1_SM0_PERF_CONFIG_PRESCALE_C0 = 8 ;
+static const uint8_t P9N2_PU_NPU1_SM0_PERF_CONFIG_PRESCALE_C0_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU1_SM0_PERF_CONFIG_PRESCALE_C1 = 10 ;
+static const uint8_t P9N2_PU_NPU1_SM0_PERF_CONFIG_PRESCALE_C1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU1_SM0_PERF_CONFIG_PRESCALE_C2 = 12 ;
+static const uint8_t P9N2_PU_NPU1_SM0_PERF_CONFIG_PRESCALE_C2_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU1_SM0_PERF_CONFIG_PRESCALE_C3 = 14 ;
+static const uint8_t P9N2_PU_NPU1_SM0_PERF_CONFIG_PRESCALE_C3_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU1_SM0_PERF_CONFIG_EVENT0 = 16 ;
+static const uint8_t P9N2_PU_NPU1_SM0_PERF_CONFIG_EVENT0_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU1_SM0_PERF_CONFIG_EVENT1 = 24 ;
+static const uint8_t P9N2_PU_NPU1_SM0_PERF_CONFIG_EVENT1_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU1_SM0_PERF_CONFIG_EVENT2 = 32 ;
+static const uint8_t P9N2_PU_NPU1_SM0_PERF_CONFIG_EVENT2_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU1_SM0_PERF_CONFIG_EVENT3 = 40 ;
+static const uint8_t P9N2_PU_NPU1_SM0_PERF_CONFIG_EVENT3_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU1_SM0_PERF_CONFIG_LATENCY = 48 ;
+static const uint8_t P9N2_PU_NPU1_SM0_PERF_CONFIG_LATENCY_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU1_SM0_PERF_CONFIG_RESERVED = 51 ;
+static const uint8_t P9N2_PU_NPU1_SM0_PERF_CONFIG_RESERVED_LEN = 13 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_CONFIG_LATSTART = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_CONFIG_LATSTART_LEN = 9 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_CONFIG_LATCANCEL = 9 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_CONFIG_LATCANCEL_LEN = 9 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_CONFIG_LATFINISH = 18 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_CONFIG_LATFINISH_LEN = 9 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_CONFIG_RESERVED1 = 27 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_CONFIG_EVENT0 = 28 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_CONFIG_EVENT0_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_CONFIG_EVENT1 = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_CONFIG_EVENT1_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_CONFIG_EVENT2 = 44 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_CONFIG_EVENT2_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_CONFIG_EVENT3 = 52 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_CONFIG_EVENT3_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_CONFIG_RESERVED2 = 60 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_CONFIG_RESERVED2_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_CONFIG_LATFILTER = 62 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_CONFIG_ACT = 63 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM3_PERF_CONFIG_LATSTART = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_PERF_CONFIG_LATSTART_LEN = 9 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_PERF_CONFIG_LATCANCEL = 9 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_PERF_CONFIG_LATCANCEL_LEN = 9 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_PERF_CONFIG_LATFINISH = 18 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_PERF_CONFIG_LATFINISH_LEN = 9 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_PERF_CONFIG_RESERVED1 = 27 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_PERF_CONFIG_EVENT0 = 28 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_PERF_CONFIG_EVENT0_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_PERF_CONFIG_EVENT1 = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_PERF_CONFIG_EVENT1_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_PERF_CONFIG_EVENT2 = 44 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_PERF_CONFIG_EVENT2_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_PERF_CONFIG_EVENT3 = 52 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_PERF_CONFIG_EVENT3_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_PERF_CONFIG_RESERVED2 = 60 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_PERF_CONFIG_RESERVED2_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_PERF_CONFIG_LATFILTER = 62 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_PERF_CONFIG_ACT = 63 ;
+
+static const uint8_t P9N2_PU_NPU1_SM1_PERF_COUNT_IDIAL_COUNT0 = 0 ;
+static const uint8_t P9N2_PU_NPU1_SM1_PERF_COUNT_IDIAL_COUNT0_LEN = 16 ;
+static const uint8_t P9N2_PU_NPU1_SM1_PERF_COUNT_IDIAL_COUNT1 = 16 ;
+static const uint8_t P9N2_PU_NPU1_SM1_PERF_COUNT_IDIAL_COUNT1_LEN = 16 ;
+static const uint8_t P9N2_PU_NPU1_SM1_PERF_COUNT_IDIAL_COUNT2 = 32 ;
+static const uint8_t P9N2_PU_NPU1_SM1_PERF_COUNT_IDIAL_COUNT2_LEN = 16 ;
+static const uint8_t P9N2_PU_NPU1_SM1_PERF_COUNT_IDIAL_COUNT3 = 48 ;
+static const uint8_t P9N2_PU_NPU1_SM1_PERF_COUNT_IDIAL_COUNT3_LEN = 16 ;
+
+static const uint8_t P9N2_PU_NPU2_NTL0_PERF_COUNT_IDIAL_COUNT0 = 0 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_PERF_COUNT_IDIAL_COUNT0_LEN = 16 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_PERF_COUNT_IDIAL_COUNT1 = 16 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_PERF_COUNT_IDIAL_COUNT1_LEN = 16 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_PERF_COUNT_IDIAL_COUNT2 = 32 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_PERF_COUNT_IDIAL_COUNT2_LEN = 16 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_PERF_COUNT_IDIAL_COUNT3 = 48 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_PERF_COUNT_IDIAL_COUNT3_LEN = 16 ;
+
+static const uint8_t P9N2__SM0_PERF_COUNT_IDIAL_COUNT0 = 0 ;
+static const uint8_t P9N2__SM0_PERF_COUNT_IDIAL_COUNT0_LEN = 16 ;
+static const uint8_t P9N2__SM0_PERF_COUNT_IDIAL_COUNT1 = 16 ;
+static const uint8_t P9N2__SM0_PERF_COUNT_IDIAL_COUNT1_LEN = 16 ;
+static const uint8_t P9N2__SM0_PERF_COUNT_IDIAL_COUNT2 = 32 ;
+static const uint8_t P9N2__SM0_PERF_COUNT_IDIAL_COUNT2_LEN = 16 ;
+static const uint8_t P9N2__SM0_PERF_COUNT_IDIAL_COUNT3 = 48 ;
+static const uint8_t P9N2__SM0_PERF_COUNT_IDIAL_COUNT3_LEN = 16 ;
+
+static const uint8_t P9N2_PU_NPU_SM0_PERF_COUNT_IDIAL_COUNT0 = 0 ;
+static const uint8_t P9N2_PU_NPU_SM0_PERF_COUNT_IDIAL_COUNT0_LEN = 16 ;
+static const uint8_t P9N2_PU_NPU_SM0_PERF_COUNT_IDIAL_COUNT1 = 16 ;
+static const uint8_t P9N2_PU_NPU_SM0_PERF_COUNT_IDIAL_COUNT1_LEN = 16 ;
+static const uint8_t P9N2_PU_NPU_SM0_PERF_COUNT_IDIAL_COUNT2 = 32 ;
+static const uint8_t P9N2_PU_NPU_SM0_PERF_COUNT_IDIAL_COUNT2_LEN = 16 ;
+static const uint8_t P9N2_PU_NPU_SM0_PERF_COUNT_IDIAL_COUNT3 = 48 ;
+static const uint8_t P9N2_PU_NPU_SM0_PERF_COUNT_IDIAL_COUNT3_LEN = 16 ;
+
+static const uint8_t P9N2_PU_NPU_SM1_PERF_COUNT_IDIAL_COUNT0 = 0 ;
+static const uint8_t P9N2_PU_NPU_SM1_PERF_COUNT_IDIAL_COUNT0_LEN = 16 ;
+static const uint8_t P9N2_PU_NPU_SM1_PERF_COUNT_IDIAL_COUNT1 = 16 ;
+static const uint8_t P9N2_PU_NPU_SM1_PERF_COUNT_IDIAL_COUNT1_LEN = 16 ;
+static const uint8_t P9N2_PU_NPU_SM1_PERF_COUNT_IDIAL_COUNT2 = 32 ;
+static const uint8_t P9N2_PU_NPU_SM1_PERF_COUNT_IDIAL_COUNT2_LEN = 16 ;
+static const uint8_t P9N2_PU_NPU_SM1_PERF_COUNT_IDIAL_COUNT3 = 48 ;
+static const uint8_t P9N2_PU_NPU_SM1_PERF_COUNT_IDIAL_COUNT3_LEN = 16 ;
+
+static const uint8_t P9N2_NV_PERF_COUNT_IDIAL_COUNT0 = 0 ;
+static const uint8_t P9N2_NV_PERF_COUNT_IDIAL_COUNT0_LEN = 16 ;
+static const uint8_t P9N2_NV_PERF_COUNT_IDIAL_COUNT1 = 16 ;
+static const uint8_t P9N2_NV_PERF_COUNT_IDIAL_COUNT1_LEN = 16 ;
+static const uint8_t P9N2_NV_PERF_COUNT_IDIAL_COUNT2 = 32 ;
+static const uint8_t P9N2_NV_PERF_COUNT_IDIAL_COUNT2_LEN = 16 ;
+static const uint8_t P9N2_NV_PERF_COUNT_IDIAL_COUNT3 = 48 ;
+static const uint8_t P9N2_NV_PERF_COUNT_IDIAL_COUNT3_LEN = 16 ;
+
+static const uint8_t P9N2_PU_NPU1_SM0_PERF_COUNT_IDIAL_COUNT0 = 0 ;
+static const uint8_t P9N2_PU_NPU1_SM0_PERF_COUNT_IDIAL_COUNT0_LEN = 16 ;
+static const uint8_t P9N2_PU_NPU1_SM0_PERF_COUNT_IDIAL_COUNT1 = 16 ;
+static const uint8_t P9N2_PU_NPU1_SM0_PERF_COUNT_IDIAL_COUNT1_LEN = 16 ;
+static const uint8_t P9N2_PU_NPU1_SM0_PERF_COUNT_IDIAL_COUNT2 = 32 ;
+static const uint8_t P9N2_PU_NPU1_SM0_PERF_COUNT_IDIAL_COUNT2_LEN = 16 ;
+static const uint8_t P9N2_PU_NPU1_SM0_PERF_COUNT_IDIAL_COUNT3 = 48 ;
+static const uint8_t P9N2_PU_NPU1_SM0_PERF_COUNT_IDIAL_COUNT3_LEN = 16 ;
+
+static const uint8_t P9N2__SM1_PERF_COUNT_IDIAL_COUNT0 = 0 ;
+static const uint8_t P9N2__SM1_PERF_COUNT_IDIAL_COUNT0_LEN = 16 ;
+static const uint8_t P9N2__SM1_PERF_COUNT_IDIAL_COUNT1 = 16 ;
+static const uint8_t P9N2__SM1_PERF_COUNT_IDIAL_COUNT1_LEN = 16 ;
+static const uint8_t P9N2__SM1_PERF_COUNT_IDIAL_COUNT2 = 32 ;
+static const uint8_t P9N2__SM1_PERF_COUNT_IDIAL_COUNT2_LEN = 16 ;
+static const uint8_t P9N2__SM1_PERF_COUNT_IDIAL_COUNT3 = 48 ;
+static const uint8_t P9N2__SM1_PERF_COUNT_IDIAL_COUNT3_LEN = 16 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MASK_CONFIG_SRC_BUS = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MASK_CONFIG_SRC_BUS_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MASK_CONFIG_TTYPE = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MASK_CONFIG_TTYPE_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MASK_CONFIG_TSIZE = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MASK_CONFIG_TSIZE_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MASK_CONFIG_NVBE = 18 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MASK_CONFIG_UT = 19 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MASK_CONFIG_ATYPE = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MASK_CONFIG_ATYPE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MASK_CONFIG_CRESP = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MASK_CONFIG_CRESP_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MASK_CONFIG_SCOPE = 29 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MASK_CONFIG_SCOPE_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MASK_CONFIG_MCMD = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MASK_CONFIG_MCMD_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MASK_CONFIG_ALLOC = 40 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MASK_CONFIG_ALLOC_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MASK_CONFIG_RESERVED1 = 46 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MASK_CONFIG_RESERVED1_LEN = 2 ;
+
+static const uint8_t P9N2_PU_NPU2_NTL0_PERF_MASK_CONFIG_NMCMD = 0 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_PERF_MASK_CONFIG_NMCMD_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_PERF_MASK_CONFIG_NMEXCMD = 8 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_PERF_MASK_CONFIG_NMEXCMD_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_PERF_MASK_CONFIG_BE = 13 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_PERF_MASK_CONFIG_CS = 14 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_PERF_MASK_CONFIG_CS_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_PERF_MASK_CONFIG_AECS = 20 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_PERF_MASK_CONFIG_AECS_LEN = 16 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_PERF_MASK_CONFIG_PE = 36 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_PERF_MASK_CONFIG_PE_LEN = 4 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MASK_CONFIG_SRC_BUS = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MASK_CONFIG_SRC_BUS_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MASK_CONFIG_TTYPE = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MASK_CONFIG_TTYPE_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MASK_CONFIG_TSIZE = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MASK_CONFIG_TSIZE_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MASK_CONFIG_NVBE = 18 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MASK_CONFIG_UT = 19 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MASK_CONFIG_ATYPE = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MASK_CONFIG_ATYPE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MASK_CONFIG_CRESP = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MASK_CONFIG_CRESP_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MASK_CONFIG_SCOPE = 29 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MASK_CONFIG_SCOPE_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MASK_CONFIG_MCMD = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MASK_CONFIG_MCMD_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MASK_CONFIG_ALLOC = 40 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MASK_CONFIG_ALLOC_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MASK_CONFIG_RESERVED1 = 46 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MASK_CONFIG_RESERVED1_LEN = 2 ;
+
+static const uint8_t P9N2_PU_NPU2_SM2_PERF_MASK_CONFIG_SRC_BUS = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM2_PERF_MASK_CONFIG_SRC_BUS_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM2_PERF_MASK_CONFIG_TTYPE = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM2_PERF_MASK_CONFIG_TTYPE_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM2_PERF_MASK_CONFIG_TSIZE = 10 ;
+static const uint8_t P9N2_PU_NPU2_SM2_PERF_MASK_CONFIG_TSIZE_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM2_PERF_MASK_CONFIG_NVBE = 18 ;
+static const uint8_t P9N2_PU_NPU2_SM2_PERF_MASK_CONFIG_UT = 19 ;
+static const uint8_t P9N2_PU_NPU2_SM2_PERF_MASK_CONFIG_ATYPE = 20 ;
+static const uint8_t P9N2_PU_NPU2_SM2_PERF_MASK_CONFIG_ATYPE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM2_PERF_MASK_CONFIG_CRESP = 24 ;
+static const uint8_t P9N2_PU_NPU2_SM2_PERF_MASK_CONFIG_CRESP_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM2_PERF_MASK_CONFIG_SCOPE = 29 ;
+static const uint8_t P9N2_PU_NPU2_SM2_PERF_MASK_CONFIG_SCOPE_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM2_PERF_MASK_CONFIG_MCMD = 32 ;
+static const uint8_t P9N2_PU_NPU2_SM2_PERF_MASK_CONFIG_MCMD_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM2_PERF_MASK_CONFIG_ALLOC = 40 ;
+static const uint8_t P9N2_PU_NPU2_SM2_PERF_MASK_CONFIG_ALLOC_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM2_PERF_MASK_CONFIG_RESERVED1 = 46 ;
+static const uint8_t P9N2_PU_NPU2_SM2_PERF_MASK_CONFIG_RESERVED1_LEN = 2 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MASK_CONFIG_SRC_BUS = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MASK_CONFIG_SRC_BUS_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MASK_CONFIG_TTYPE = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MASK_CONFIG_TTYPE_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MASK_CONFIG_TSIZE = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MASK_CONFIG_TSIZE_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MASK_CONFIG_NVBE = 18 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MASK_CONFIG_UT = 19 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MASK_CONFIG_ATYPE = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MASK_CONFIG_ATYPE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MASK_CONFIG_CRESP = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MASK_CONFIG_CRESP_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MASK_CONFIG_SCOPE = 29 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MASK_CONFIG_SCOPE_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MASK_CONFIG_MCMD = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MASK_CONFIG_MCMD_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MASK_CONFIG_ALLOC = 40 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MASK_CONFIG_ALLOC_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MASK_CONFIG_RESERVED1 = 46 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MASK_CONFIG_RESERVED1_LEN = 2 ;
+
+static const uint8_t P9N2_PU_NPU0_SM2_PERF_MASK_CONFIG_SRC_BUS = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM2_PERF_MASK_CONFIG_SRC_BUS_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM2_PERF_MASK_CONFIG_TTYPE = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM2_PERF_MASK_CONFIG_TTYPE_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM2_PERF_MASK_CONFIG_TSIZE = 10 ;
+static const uint8_t P9N2_PU_NPU0_SM2_PERF_MASK_CONFIG_TSIZE_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM2_PERF_MASK_CONFIG_NVBE = 18 ;
+static const uint8_t P9N2_PU_NPU0_SM2_PERF_MASK_CONFIG_UT = 19 ;
+static const uint8_t P9N2_PU_NPU0_SM2_PERF_MASK_CONFIG_ATYPE = 20 ;
+static const uint8_t P9N2_PU_NPU0_SM2_PERF_MASK_CONFIG_ATYPE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM2_PERF_MASK_CONFIG_CRESP = 24 ;
+static const uint8_t P9N2_PU_NPU0_SM2_PERF_MASK_CONFIG_CRESP_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM2_PERF_MASK_CONFIG_SCOPE = 29 ;
+static const uint8_t P9N2_PU_NPU0_SM2_PERF_MASK_CONFIG_SCOPE_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM2_PERF_MASK_CONFIG_MCMD = 32 ;
+static const uint8_t P9N2_PU_NPU0_SM2_PERF_MASK_CONFIG_MCMD_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM2_PERF_MASK_CONFIG_ALLOC = 40 ;
+static const uint8_t P9N2_PU_NPU0_SM2_PERF_MASK_CONFIG_ALLOC_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM2_PERF_MASK_CONFIG_RESERVED1 = 46 ;
+static const uint8_t P9N2_PU_NPU0_SM2_PERF_MASK_CONFIG_RESERVED1_LEN = 2 ;
+
+static const uint8_t P9N2_PU_NPU2_SM1_PERF_MASK_CONFIG_SRC_BUS = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM1_PERF_MASK_CONFIG_SRC_BUS_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM1_PERF_MASK_CONFIG_TTYPE = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM1_PERF_MASK_CONFIG_TTYPE_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM1_PERF_MASK_CONFIG_TSIZE = 10 ;
+static const uint8_t P9N2_PU_NPU2_SM1_PERF_MASK_CONFIG_TSIZE_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM1_PERF_MASK_CONFIG_NVBE = 18 ;
+static const uint8_t P9N2_PU_NPU2_SM1_PERF_MASK_CONFIG_UT = 19 ;
+static const uint8_t P9N2_PU_NPU2_SM1_PERF_MASK_CONFIG_ATYPE = 20 ;
+static const uint8_t P9N2_PU_NPU2_SM1_PERF_MASK_CONFIG_ATYPE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM1_PERF_MASK_CONFIG_CRESP = 24 ;
+static const uint8_t P9N2_PU_NPU2_SM1_PERF_MASK_CONFIG_CRESP_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM1_PERF_MASK_CONFIG_SCOPE = 29 ;
+static const uint8_t P9N2_PU_NPU2_SM1_PERF_MASK_CONFIG_SCOPE_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM1_PERF_MASK_CONFIG_MCMD = 32 ;
+static const uint8_t P9N2_PU_NPU2_SM1_PERF_MASK_CONFIG_MCMD_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM1_PERF_MASK_CONFIG_ALLOC = 40 ;
+static const uint8_t P9N2_PU_NPU2_SM1_PERF_MASK_CONFIG_ALLOC_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM1_PERF_MASK_CONFIG_RESERVED1 = 46 ;
+static const uint8_t P9N2_PU_NPU2_SM1_PERF_MASK_CONFIG_RESERVED1_LEN = 2 ;
+
+static const uint8_t P9N2_PU_NPU0_CTL_PERF_MASK_CONFIG_SRC_BUS = 0 ;
+static const uint8_t P9N2_PU_NPU0_CTL_PERF_MASK_CONFIG_SRC_BUS_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU0_CTL_PERF_MASK_CONFIG_TTYPE = 2 ;
+static const uint8_t P9N2_PU_NPU0_CTL_PERF_MASK_CONFIG_TTYPE_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU0_CTL_PERF_MASK_CONFIG_TSIZE = 10 ;
+static const uint8_t P9N2_PU_NPU0_CTL_PERF_MASK_CONFIG_TSIZE_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU0_CTL_PERF_MASK_CONFIG_NVBE = 18 ;
+static const uint8_t P9N2_PU_NPU0_CTL_PERF_MASK_CONFIG_UT = 19 ;
+static const uint8_t P9N2_PU_NPU0_CTL_PERF_MASK_CONFIG_ATYPE = 20 ;
+static const uint8_t P9N2_PU_NPU0_CTL_PERF_MASK_CONFIG_ATYPE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_CTL_PERF_MASK_CONFIG_CRESP = 24 ;
+static const uint8_t P9N2_PU_NPU0_CTL_PERF_MASK_CONFIG_CRESP_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_CTL_PERF_MASK_CONFIG_SCOPE = 29 ;
+static const uint8_t P9N2_PU_NPU0_CTL_PERF_MASK_CONFIG_SCOPE_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU0_CTL_PERF_MASK_CONFIG_MCMD = 32 ;
+static const uint8_t P9N2_PU_NPU0_CTL_PERF_MASK_CONFIG_MCMD_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU0_CTL_PERF_MASK_CONFIG_ALLOC = 40 ;
+static const uint8_t P9N2_PU_NPU0_CTL_PERF_MASK_CONFIG_ALLOC_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_CTL_PERF_MASK_CONFIG_RESERVED1 = 46 ;
+static const uint8_t P9N2_PU_NPU0_CTL_PERF_MASK_CONFIG_RESERVED1_LEN = 2 ;
+
+static const uint8_t P9N2_NV_PERF_MASK_CONFIG_NMCMD = 0 ;
+static const uint8_t P9N2_NV_PERF_MASK_CONFIG_NMCMD_LEN = 8 ;
+static const uint8_t P9N2_NV_PERF_MASK_CONFIG_NMEXCMD = 8 ;
+static const uint8_t P9N2_NV_PERF_MASK_CONFIG_NMEXCMD_LEN = 5 ;
+static const uint8_t P9N2_NV_PERF_MASK_CONFIG_BE = 13 ;
+static const uint8_t P9N2_NV_PERF_MASK_CONFIG_CS = 14 ;
+static const uint8_t P9N2_NV_PERF_MASK_CONFIG_CS_LEN = 6 ;
+static const uint8_t P9N2_NV_PERF_MASK_CONFIG_AECS = 20 ;
+static const uint8_t P9N2_NV_PERF_MASK_CONFIG_AECS_LEN = 16 ;
+static const uint8_t P9N2_NV_PERF_MASK_CONFIG_PE = 36 ;
+static const uint8_t P9N2_NV_PERF_MASK_CONFIG_PE_LEN = 4 ;
+
+static const uint8_t P9N2_PU_NPU2_CTL_PERF_MASK_CONFIG_SRC_BUS = 0 ;
+static const uint8_t P9N2_PU_NPU2_CTL_PERF_MASK_CONFIG_SRC_BUS_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_CTL_PERF_MASK_CONFIG_TTYPE = 2 ;
+static const uint8_t P9N2_PU_NPU2_CTL_PERF_MASK_CONFIG_TTYPE_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU2_CTL_PERF_MASK_CONFIG_TSIZE = 10 ;
+static const uint8_t P9N2_PU_NPU2_CTL_PERF_MASK_CONFIG_TSIZE_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU2_CTL_PERF_MASK_CONFIG_NVBE = 18 ;
+static const uint8_t P9N2_PU_NPU2_CTL_PERF_MASK_CONFIG_UT = 19 ;
+static const uint8_t P9N2_PU_NPU2_CTL_PERF_MASK_CONFIG_ATYPE = 20 ;
+static const uint8_t P9N2_PU_NPU2_CTL_PERF_MASK_CONFIG_ATYPE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_CTL_PERF_MASK_CONFIG_CRESP = 24 ;
+static const uint8_t P9N2_PU_NPU2_CTL_PERF_MASK_CONFIG_CRESP_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_CTL_PERF_MASK_CONFIG_SCOPE = 29 ;
+static const uint8_t P9N2_PU_NPU2_CTL_PERF_MASK_CONFIG_SCOPE_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU2_CTL_PERF_MASK_CONFIG_MCMD = 32 ;
+static const uint8_t P9N2_PU_NPU2_CTL_PERF_MASK_CONFIG_MCMD_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU2_CTL_PERF_MASK_CONFIG_ALLOC = 40 ;
+static const uint8_t P9N2_PU_NPU2_CTL_PERF_MASK_CONFIG_ALLOC_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_CTL_PERF_MASK_CONFIG_RESERVED1 = 46 ;
+static const uint8_t P9N2_PU_NPU2_CTL_PERF_MASK_CONFIG_RESERVED1_LEN = 2 ;
+
+static const uint8_t P9N2_PU_NPU0_SM1_PERF_MASK_CONFIG_SRC_BUS = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM1_PERF_MASK_CONFIG_SRC_BUS_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM1_PERF_MASK_CONFIG_TTYPE = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM1_PERF_MASK_CONFIG_TTYPE_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM1_PERF_MASK_CONFIG_TSIZE = 10 ;
+static const uint8_t P9N2_PU_NPU0_SM1_PERF_MASK_CONFIG_TSIZE_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM1_PERF_MASK_CONFIG_NVBE = 18 ;
+static const uint8_t P9N2_PU_NPU0_SM1_PERF_MASK_CONFIG_UT = 19 ;
+static const uint8_t P9N2_PU_NPU0_SM1_PERF_MASK_CONFIG_ATYPE = 20 ;
+static const uint8_t P9N2_PU_NPU0_SM1_PERF_MASK_CONFIG_ATYPE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM1_PERF_MASK_CONFIG_CRESP = 24 ;
+static const uint8_t P9N2_PU_NPU0_SM1_PERF_MASK_CONFIG_CRESP_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM1_PERF_MASK_CONFIG_SCOPE = 29 ;
+static const uint8_t P9N2_PU_NPU0_SM1_PERF_MASK_CONFIG_SCOPE_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM1_PERF_MASK_CONFIG_MCMD = 32 ;
+static const uint8_t P9N2_PU_NPU0_SM1_PERF_MASK_CONFIG_MCMD_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM1_PERF_MASK_CONFIG_ALLOC = 40 ;
+static const uint8_t P9N2_PU_NPU0_SM1_PERF_MASK_CONFIG_ALLOC_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM1_PERF_MASK_CONFIG_RESERVED1 = 46 ;
+static const uint8_t P9N2_PU_NPU0_SM1_PERF_MASK_CONFIG_RESERVED1_LEN = 2 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MASK_CONFIG_SRC_BUS = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MASK_CONFIG_SRC_BUS_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MASK_CONFIG_TTYPE = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MASK_CONFIG_TTYPE_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MASK_CONFIG_TSIZE = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MASK_CONFIG_TSIZE_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MASK_CONFIG_NVBE = 18 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MASK_CONFIG_UT = 19 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MASK_CONFIG_ATYPE = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MASK_CONFIG_ATYPE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MASK_CONFIG_CRESP = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MASK_CONFIG_CRESP_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MASK_CONFIG_SCOPE = 29 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MASK_CONFIG_SCOPE_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MASK_CONFIG_MCMD = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MASK_CONFIG_MCMD_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MASK_CONFIG_ALLOC = 40 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MASK_CONFIG_ALLOC_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MASK_CONFIG_RESERVED1 = 46 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MASK_CONFIG_RESERVED1_LEN = 2 ;
+
+static const uint8_t P9N2_PU_NPU2_DAT_PERF_MASK_CONFIG_SRC_BUS = 0 ;
+static const uint8_t P9N2_PU_NPU2_DAT_PERF_MASK_CONFIG_SRC_BUS_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_DAT_PERF_MASK_CONFIG_TTYPE = 2 ;
+static const uint8_t P9N2_PU_NPU2_DAT_PERF_MASK_CONFIG_TTYPE_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU2_DAT_PERF_MASK_CONFIG_TSIZE = 10 ;
+static const uint8_t P9N2_PU_NPU2_DAT_PERF_MASK_CONFIG_TSIZE_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU2_DAT_PERF_MASK_CONFIG_NVBE = 18 ;
+static const uint8_t P9N2_PU_NPU2_DAT_PERF_MASK_CONFIG_UT = 19 ;
+static const uint8_t P9N2_PU_NPU2_DAT_PERF_MASK_CONFIG_ATYPE = 20 ;
+static const uint8_t P9N2_PU_NPU2_DAT_PERF_MASK_CONFIG_ATYPE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_DAT_PERF_MASK_CONFIG_CRESP = 24 ;
+static const uint8_t P9N2_PU_NPU2_DAT_PERF_MASK_CONFIG_CRESP_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_DAT_PERF_MASK_CONFIG_SCOPE = 29 ;
+static const uint8_t P9N2_PU_NPU2_DAT_PERF_MASK_CONFIG_SCOPE_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU2_DAT_PERF_MASK_CONFIG_MCMD = 32 ;
+static const uint8_t P9N2_PU_NPU2_DAT_PERF_MASK_CONFIG_MCMD_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU2_DAT_PERF_MASK_CONFIG_ALLOC = 40 ;
+static const uint8_t P9N2_PU_NPU2_DAT_PERF_MASK_CONFIG_ALLOC_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_DAT_PERF_MASK_CONFIG_RESERVED1 = 46 ;
+static const uint8_t P9N2_PU_NPU2_DAT_PERF_MASK_CONFIG_RESERVED1_LEN = 2 ;
+
+static const uint8_t P9N2_PU_NPU0_DAT_PERF_MASK_CONFIG_SRC_BUS = 0 ;
+static const uint8_t P9N2_PU_NPU0_DAT_PERF_MASK_CONFIG_SRC_BUS_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU0_DAT_PERF_MASK_CONFIG_TTYPE = 2 ;
+static const uint8_t P9N2_PU_NPU0_DAT_PERF_MASK_CONFIG_TTYPE_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU0_DAT_PERF_MASK_CONFIG_TSIZE = 10 ;
+static const uint8_t P9N2_PU_NPU0_DAT_PERF_MASK_CONFIG_TSIZE_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU0_DAT_PERF_MASK_CONFIG_NVBE = 18 ;
+static const uint8_t P9N2_PU_NPU0_DAT_PERF_MASK_CONFIG_UT = 19 ;
+static const uint8_t P9N2_PU_NPU0_DAT_PERF_MASK_CONFIG_ATYPE = 20 ;
+static const uint8_t P9N2_PU_NPU0_DAT_PERF_MASK_CONFIG_ATYPE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_DAT_PERF_MASK_CONFIG_CRESP = 24 ;
+static const uint8_t P9N2_PU_NPU0_DAT_PERF_MASK_CONFIG_CRESP_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_DAT_PERF_MASK_CONFIG_SCOPE = 29 ;
+static const uint8_t P9N2_PU_NPU0_DAT_PERF_MASK_CONFIG_SCOPE_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU0_DAT_PERF_MASK_CONFIG_MCMD = 32 ;
+static const uint8_t P9N2_PU_NPU0_DAT_PERF_MASK_CONFIG_MCMD_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU0_DAT_PERF_MASK_CONFIG_ALLOC = 40 ;
+static const uint8_t P9N2_PU_NPU0_DAT_PERF_MASK_CONFIG_ALLOC_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_DAT_PERF_MASK_CONFIG_RESERVED1 = 46 ;
+static const uint8_t P9N2_PU_NPU0_DAT_PERF_MASK_CONFIG_RESERVED1_LEN = 2 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MATCH_CONFIG_SRC_BUS = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MATCH_CONFIG_SRC_BUS_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MATCH_CONFIG_TTYPE = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MATCH_CONFIG_TTYPE_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MATCH_CONFIG_TSIZE = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MATCH_CONFIG_TSIZE_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MATCH_CONFIG_NVBE = 18 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MATCH_CONFIG_UT = 19 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MATCH_CONFIG_ATYPE = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MATCH_CONFIG_ATYPE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MATCH_CONFIG_CRESP = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MATCH_CONFIG_CRESP_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MATCH_CONFIG_SCOPE = 29 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MATCH_CONFIG_SCOPE_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MATCH_CONFIG_MCMD = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MATCH_CONFIG_MCMD_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MATCH_CONFIG_ALLOC = 40 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MATCH_CONFIG_ALLOC_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MATCH_CONFIG_RESERVED1 = 46 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_PERF_MATCH_CONFIG_RESERVED1_LEN = 2 ;
+
+static const uint8_t P9N2_PU_NPU2_NTL0_PERF_MATCH_CONFIG_NMCMD = 0 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_PERF_MATCH_CONFIG_NMCMD_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_PERF_MATCH_CONFIG_NMEXCMD = 8 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_PERF_MATCH_CONFIG_NMEXCMD_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_PERF_MATCH_CONFIG_BE = 13 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_PERF_MATCH_CONFIG_CS = 14 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_PERF_MATCH_CONFIG_CS_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_PERF_MATCH_CONFIG_AECS = 20 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_PERF_MATCH_CONFIG_AECS_LEN = 16 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_PERF_MATCH_CONFIG_PE = 36 ;
+static const uint8_t P9N2_PU_NPU2_NTL0_PERF_MATCH_CONFIG_PE_LEN = 4 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MATCH_CONFIG_SRC_BUS = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MATCH_CONFIG_SRC_BUS_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MATCH_CONFIG_TTYPE = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MATCH_CONFIG_TTYPE_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MATCH_CONFIG_TSIZE = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MATCH_CONFIG_TSIZE_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MATCH_CONFIG_NVBE = 18 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MATCH_CONFIG_UT = 19 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MATCH_CONFIG_ATYPE = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MATCH_CONFIG_ATYPE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MATCH_CONFIG_CRESP = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MATCH_CONFIG_CRESP_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MATCH_CONFIG_SCOPE = 29 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MATCH_CONFIG_SCOPE_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MATCH_CONFIG_MCMD = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MATCH_CONFIG_MCMD_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MATCH_CONFIG_ALLOC = 40 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MATCH_CONFIG_ALLOC_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MATCH_CONFIG_RESERVED1 = 46 ;
+static const uint8_t P9N2_PU_NPU_MSC_DAT_PERF_MATCH_CONFIG_RESERVED1_LEN = 2 ;
+
+static const uint8_t P9N2_PU_NPU2_SM2_PERF_MATCH_CONFIG_SRC_BUS = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM2_PERF_MATCH_CONFIG_SRC_BUS_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM2_PERF_MATCH_CONFIG_TTYPE = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM2_PERF_MATCH_CONFIG_TTYPE_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM2_PERF_MATCH_CONFIG_TSIZE = 10 ;
+static const uint8_t P9N2_PU_NPU2_SM2_PERF_MATCH_CONFIG_TSIZE_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM2_PERF_MATCH_CONFIG_NVBE = 18 ;
+static const uint8_t P9N2_PU_NPU2_SM2_PERF_MATCH_CONFIG_UT = 19 ;
+static const uint8_t P9N2_PU_NPU2_SM2_PERF_MATCH_CONFIG_ATYPE = 20 ;
+static const uint8_t P9N2_PU_NPU2_SM2_PERF_MATCH_CONFIG_ATYPE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM2_PERF_MATCH_CONFIG_CRESP = 24 ;
+static const uint8_t P9N2_PU_NPU2_SM2_PERF_MATCH_CONFIG_CRESP_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM2_PERF_MATCH_CONFIG_SCOPE = 29 ;
+static const uint8_t P9N2_PU_NPU2_SM2_PERF_MATCH_CONFIG_SCOPE_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM2_PERF_MATCH_CONFIG_MCMD = 32 ;
+static const uint8_t P9N2_PU_NPU2_SM2_PERF_MATCH_CONFIG_MCMD_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM2_PERF_MATCH_CONFIG_ALLOC = 40 ;
+static const uint8_t P9N2_PU_NPU2_SM2_PERF_MATCH_CONFIG_ALLOC_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM2_PERF_MATCH_CONFIG_RESERVED1 = 46 ;
+static const uint8_t P9N2_PU_NPU2_SM2_PERF_MATCH_CONFIG_RESERVED1_LEN = 2 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MATCH_CONFIG_SRC_BUS = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MATCH_CONFIG_SRC_BUS_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MATCH_CONFIG_TTYPE = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MATCH_CONFIG_TTYPE_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MATCH_CONFIG_TSIZE = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MATCH_CONFIG_TSIZE_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MATCH_CONFIG_NVBE = 18 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MATCH_CONFIG_UT = 19 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MATCH_CONFIG_ATYPE = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MATCH_CONFIG_ATYPE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MATCH_CONFIG_CRESP = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MATCH_CONFIG_CRESP_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MATCH_CONFIG_SCOPE = 29 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MATCH_CONFIG_SCOPE_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MATCH_CONFIG_MCMD = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MATCH_CONFIG_MCMD_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MATCH_CONFIG_ALLOC = 40 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MATCH_CONFIG_ALLOC_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MATCH_CONFIG_RESERVED1 = 46 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_PERF_MATCH_CONFIG_RESERVED1_LEN = 2 ;
+
+static const uint8_t P9N2_PU_NPU0_SM2_PERF_MATCH_CONFIG_SRC_BUS = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM2_PERF_MATCH_CONFIG_SRC_BUS_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM2_PERF_MATCH_CONFIG_TTYPE = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM2_PERF_MATCH_CONFIG_TTYPE_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM2_PERF_MATCH_CONFIG_TSIZE = 10 ;
+static const uint8_t P9N2_PU_NPU0_SM2_PERF_MATCH_CONFIG_TSIZE_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM2_PERF_MATCH_CONFIG_NVBE = 18 ;
+static const uint8_t P9N2_PU_NPU0_SM2_PERF_MATCH_CONFIG_UT = 19 ;
+static const uint8_t P9N2_PU_NPU0_SM2_PERF_MATCH_CONFIG_ATYPE = 20 ;
+static const uint8_t P9N2_PU_NPU0_SM2_PERF_MATCH_CONFIG_ATYPE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM2_PERF_MATCH_CONFIG_CRESP = 24 ;
+static const uint8_t P9N2_PU_NPU0_SM2_PERF_MATCH_CONFIG_CRESP_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM2_PERF_MATCH_CONFIG_SCOPE = 29 ;
+static const uint8_t P9N2_PU_NPU0_SM2_PERF_MATCH_CONFIG_SCOPE_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM2_PERF_MATCH_CONFIG_MCMD = 32 ;
+static const uint8_t P9N2_PU_NPU0_SM2_PERF_MATCH_CONFIG_MCMD_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM2_PERF_MATCH_CONFIG_ALLOC = 40 ;
+static const uint8_t P9N2_PU_NPU0_SM2_PERF_MATCH_CONFIG_ALLOC_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM2_PERF_MATCH_CONFIG_RESERVED1 = 46 ;
+static const uint8_t P9N2_PU_NPU0_SM2_PERF_MATCH_CONFIG_RESERVED1_LEN = 2 ;
+
+static const uint8_t P9N2_PU_NPU2_SM1_PERF_MATCH_CONFIG_SRC_BUS = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM1_PERF_MATCH_CONFIG_SRC_BUS_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM1_PERF_MATCH_CONFIG_TTYPE = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM1_PERF_MATCH_CONFIG_TTYPE_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM1_PERF_MATCH_CONFIG_TSIZE = 10 ;
+static const uint8_t P9N2_PU_NPU2_SM1_PERF_MATCH_CONFIG_TSIZE_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM1_PERF_MATCH_CONFIG_NVBE = 18 ;
+static const uint8_t P9N2_PU_NPU2_SM1_PERF_MATCH_CONFIG_UT = 19 ;
+static const uint8_t P9N2_PU_NPU2_SM1_PERF_MATCH_CONFIG_ATYPE = 20 ;
+static const uint8_t P9N2_PU_NPU2_SM1_PERF_MATCH_CONFIG_ATYPE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM1_PERF_MATCH_CONFIG_CRESP = 24 ;
+static const uint8_t P9N2_PU_NPU2_SM1_PERF_MATCH_CONFIG_CRESP_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM1_PERF_MATCH_CONFIG_SCOPE = 29 ;
+static const uint8_t P9N2_PU_NPU2_SM1_PERF_MATCH_CONFIG_SCOPE_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM1_PERF_MATCH_CONFIG_MCMD = 32 ;
+static const uint8_t P9N2_PU_NPU2_SM1_PERF_MATCH_CONFIG_MCMD_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM1_PERF_MATCH_CONFIG_ALLOC = 40 ;
+static const uint8_t P9N2_PU_NPU2_SM1_PERF_MATCH_CONFIG_ALLOC_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM1_PERF_MATCH_CONFIG_RESERVED1 = 46 ;
+static const uint8_t P9N2_PU_NPU2_SM1_PERF_MATCH_CONFIG_RESERVED1_LEN = 2 ;
+
+static const uint8_t P9N2_PU_NPU0_CTL_PERF_MATCH_CONFIG_SRC_BUS = 0 ;
+static const uint8_t P9N2_PU_NPU0_CTL_PERF_MATCH_CONFIG_SRC_BUS_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU0_CTL_PERF_MATCH_CONFIG_TTYPE = 2 ;
+static const uint8_t P9N2_PU_NPU0_CTL_PERF_MATCH_CONFIG_TTYPE_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU0_CTL_PERF_MATCH_CONFIG_TSIZE = 10 ;
+static const uint8_t P9N2_PU_NPU0_CTL_PERF_MATCH_CONFIG_TSIZE_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU0_CTL_PERF_MATCH_CONFIG_NVBE = 18 ;
+static const uint8_t P9N2_PU_NPU0_CTL_PERF_MATCH_CONFIG_UT = 19 ;
+static const uint8_t P9N2_PU_NPU0_CTL_PERF_MATCH_CONFIG_ATYPE = 20 ;
+static const uint8_t P9N2_PU_NPU0_CTL_PERF_MATCH_CONFIG_ATYPE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_CTL_PERF_MATCH_CONFIG_CRESP = 24 ;
+static const uint8_t P9N2_PU_NPU0_CTL_PERF_MATCH_CONFIG_CRESP_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_CTL_PERF_MATCH_CONFIG_SCOPE = 29 ;
+static const uint8_t P9N2_PU_NPU0_CTL_PERF_MATCH_CONFIG_SCOPE_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU0_CTL_PERF_MATCH_CONFIG_MCMD = 32 ;
+static const uint8_t P9N2_PU_NPU0_CTL_PERF_MATCH_CONFIG_MCMD_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU0_CTL_PERF_MATCH_CONFIG_ALLOC = 40 ;
+static const uint8_t P9N2_PU_NPU0_CTL_PERF_MATCH_CONFIG_ALLOC_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_CTL_PERF_MATCH_CONFIG_RESERVED1 = 46 ;
+static const uint8_t P9N2_PU_NPU0_CTL_PERF_MATCH_CONFIG_RESERVED1_LEN = 2 ;
+
+static const uint8_t P9N2_NV_PERF_MATCH_CONFIG_NMCMD = 0 ;
+static const uint8_t P9N2_NV_PERF_MATCH_CONFIG_NMCMD_LEN = 8 ;
+static const uint8_t P9N2_NV_PERF_MATCH_CONFIG_NMEXCMD = 8 ;
+static const uint8_t P9N2_NV_PERF_MATCH_CONFIG_NMEXCMD_LEN = 5 ;
+static const uint8_t P9N2_NV_PERF_MATCH_CONFIG_BE = 13 ;
+static const uint8_t P9N2_NV_PERF_MATCH_CONFIG_CS = 14 ;
+static const uint8_t P9N2_NV_PERF_MATCH_CONFIG_CS_LEN = 6 ;
+static const uint8_t P9N2_NV_PERF_MATCH_CONFIG_AECS = 20 ;
+static const uint8_t P9N2_NV_PERF_MATCH_CONFIG_AECS_LEN = 16 ;
+static const uint8_t P9N2_NV_PERF_MATCH_CONFIG_PE = 36 ;
+static const uint8_t P9N2_NV_PERF_MATCH_CONFIG_PE_LEN = 4 ;
+
+static const uint8_t P9N2_PU_NPU2_CTL_PERF_MATCH_CONFIG_SRC_BUS = 0 ;
+static const uint8_t P9N2_PU_NPU2_CTL_PERF_MATCH_CONFIG_SRC_BUS_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_CTL_PERF_MATCH_CONFIG_TTYPE = 2 ;
+static const uint8_t P9N2_PU_NPU2_CTL_PERF_MATCH_CONFIG_TTYPE_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU2_CTL_PERF_MATCH_CONFIG_TSIZE = 10 ;
+static const uint8_t P9N2_PU_NPU2_CTL_PERF_MATCH_CONFIG_TSIZE_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU2_CTL_PERF_MATCH_CONFIG_NVBE = 18 ;
+static const uint8_t P9N2_PU_NPU2_CTL_PERF_MATCH_CONFIG_UT = 19 ;
+static const uint8_t P9N2_PU_NPU2_CTL_PERF_MATCH_CONFIG_ATYPE = 20 ;
+static const uint8_t P9N2_PU_NPU2_CTL_PERF_MATCH_CONFIG_ATYPE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_CTL_PERF_MATCH_CONFIG_CRESP = 24 ;
+static const uint8_t P9N2_PU_NPU2_CTL_PERF_MATCH_CONFIG_CRESP_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_CTL_PERF_MATCH_CONFIG_SCOPE = 29 ;
+static const uint8_t P9N2_PU_NPU2_CTL_PERF_MATCH_CONFIG_SCOPE_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU2_CTL_PERF_MATCH_CONFIG_MCMD = 32 ;
+static const uint8_t P9N2_PU_NPU2_CTL_PERF_MATCH_CONFIG_MCMD_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU2_CTL_PERF_MATCH_CONFIG_ALLOC = 40 ;
+static const uint8_t P9N2_PU_NPU2_CTL_PERF_MATCH_CONFIG_ALLOC_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_CTL_PERF_MATCH_CONFIG_RESERVED1 = 46 ;
+static const uint8_t P9N2_PU_NPU2_CTL_PERF_MATCH_CONFIG_RESERVED1_LEN = 2 ;
+
+static const uint8_t P9N2_PU_NPU0_SM1_PERF_MATCH_CONFIG_SRC_BUS = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM1_PERF_MATCH_CONFIG_SRC_BUS_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM1_PERF_MATCH_CONFIG_TTYPE = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM1_PERF_MATCH_CONFIG_TTYPE_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM1_PERF_MATCH_CONFIG_TSIZE = 10 ;
+static const uint8_t P9N2_PU_NPU0_SM1_PERF_MATCH_CONFIG_TSIZE_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM1_PERF_MATCH_CONFIG_NVBE = 18 ;
+static const uint8_t P9N2_PU_NPU0_SM1_PERF_MATCH_CONFIG_UT = 19 ;
+static const uint8_t P9N2_PU_NPU0_SM1_PERF_MATCH_CONFIG_ATYPE = 20 ;
+static const uint8_t P9N2_PU_NPU0_SM1_PERF_MATCH_CONFIG_ATYPE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM1_PERF_MATCH_CONFIG_CRESP = 24 ;
+static const uint8_t P9N2_PU_NPU0_SM1_PERF_MATCH_CONFIG_CRESP_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM1_PERF_MATCH_CONFIG_SCOPE = 29 ;
+static const uint8_t P9N2_PU_NPU0_SM1_PERF_MATCH_CONFIG_SCOPE_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM1_PERF_MATCH_CONFIG_MCMD = 32 ;
+static const uint8_t P9N2_PU_NPU0_SM1_PERF_MATCH_CONFIG_MCMD_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM1_PERF_MATCH_CONFIG_ALLOC = 40 ;
+static const uint8_t P9N2_PU_NPU0_SM1_PERF_MATCH_CONFIG_ALLOC_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM1_PERF_MATCH_CONFIG_RESERVED1 = 46 ;
+static const uint8_t P9N2_PU_NPU0_SM1_PERF_MATCH_CONFIG_RESERVED1_LEN = 2 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MATCH_CONFIG_SRC_BUS = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MATCH_CONFIG_SRC_BUS_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MATCH_CONFIG_TTYPE = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MATCH_CONFIG_TTYPE_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MATCH_CONFIG_TSIZE = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MATCH_CONFIG_TSIZE_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MATCH_CONFIG_NVBE = 18 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MATCH_CONFIG_UT = 19 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MATCH_CONFIG_ATYPE = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MATCH_CONFIG_ATYPE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MATCH_CONFIG_CRESP = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MATCH_CONFIG_CRESP_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MATCH_CONFIG_SCOPE = 29 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MATCH_CONFIG_SCOPE_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MATCH_CONFIG_MCMD = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MATCH_CONFIG_MCMD_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MATCH_CONFIG_ALLOC = 40 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MATCH_CONFIG_ALLOC_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MATCH_CONFIG_RESERVED1 = 46 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_PERF_MATCH_CONFIG_RESERVED1_LEN = 2 ;
+
+static const uint8_t P9N2_PU_NPU2_DAT_PERF_MATCH_CONFIG_SRC_BUS = 0 ;
+static const uint8_t P9N2_PU_NPU2_DAT_PERF_MATCH_CONFIG_SRC_BUS_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_DAT_PERF_MATCH_CONFIG_TTYPE = 2 ;
+static const uint8_t P9N2_PU_NPU2_DAT_PERF_MATCH_CONFIG_TTYPE_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU2_DAT_PERF_MATCH_CONFIG_TSIZE = 10 ;
+static const uint8_t P9N2_PU_NPU2_DAT_PERF_MATCH_CONFIG_TSIZE_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU2_DAT_PERF_MATCH_CONFIG_NVBE = 18 ;
+static const uint8_t P9N2_PU_NPU2_DAT_PERF_MATCH_CONFIG_UT = 19 ;
+static const uint8_t P9N2_PU_NPU2_DAT_PERF_MATCH_CONFIG_ATYPE = 20 ;
+static const uint8_t P9N2_PU_NPU2_DAT_PERF_MATCH_CONFIG_ATYPE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_DAT_PERF_MATCH_CONFIG_CRESP = 24 ;
+static const uint8_t P9N2_PU_NPU2_DAT_PERF_MATCH_CONFIG_CRESP_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_DAT_PERF_MATCH_CONFIG_SCOPE = 29 ;
+static const uint8_t P9N2_PU_NPU2_DAT_PERF_MATCH_CONFIG_SCOPE_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU2_DAT_PERF_MATCH_CONFIG_MCMD = 32 ;
+static const uint8_t P9N2_PU_NPU2_DAT_PERF_MATCH_CONFIG_MCMD_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU2_DAT_PERF_MATCH_CONFIG_ALLOC = 40 ;
+static const uint8_t P9N2_PU_NPU2_DAT_PERF_MATCH_CONFIG_ALLOC_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_DAT_PERF_MATCH_CONFIG_RESERVED1 = 46 ;
+static const uint8_t P9N2_PU_NPU2_DAT_PERF_MATCH_CONFIG_RESERVED1_LEN = 2 ;
+
+static const uint8_t P9N2_PU_NPU0_DAT_PERF_MATCH_CONFIG_SRC_BUS = 0 ;
+static const uint8_t P9N2_PU_NPU0_DAT_PERF_MATCH_CONFIG_SRC_BUS_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU0_DAT_PERF_MATCH_CONFIG_TTYPE = 2 ;
+static const uint8_t P9N2_PU_NPU0_DAT_PERF_MATCH_CONFIG_TTYPE_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU0_DAT_PERF_MATCH_CONFIG_TSIZE = 10 ;
+static const uint8_t P9N2_PU_NPU0_DAT_PERF_MATCH_CONFIG_TSIZE_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU0_DAT_PERF_MATCH_CONFIG_NVBE = 18 ;
+static const uint8_t P9N2_PU_NPU0_DAT_PERF_MATCH_CONFIG_UT = 19 ;
+static const uint8_t P9N2_PU_NPU0_DAT_PERF_MATCH_CONFIG_ATYPE = 20 ;
+static const uint8_t P9N2_PU_NPU0_DAT_PERF_MATCH_CONFIG_ATYPE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_DAT_PERF_MATCH_CONFIG_CRESP = 24 ;
+static const uint8_t P9N2_PU_NPU0_DAT_PERF_MATCH_CONFIG_CRESP_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU0_DAT_PERF_MATCH_CONFIG_SCOPE = 29 ;
+static const uint8_t P9N2_PU_NPU0_DAT_PERF_MATCH_CONFIG_SCOPE_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU0_DAT_PERF_MATCH_CONFIG_MCMD = 32 ;
+static const uint8_t P9N2_PU_NPU0_DAT_PERF_MATCH_CONFIG_MCMD_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU0_DAT_PERF_MATCH_CONFIG_ALLOC = 40 ;
+static const uint8_t P9N2_PU_NPU0_DAT_PERF_MATCH_CONFIG_ALLOC_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_DAT_PERF_MATCH_CONFIG_RESERVED1 = 46 ;
+static const uint8_t P9N2_PU_NPU0_DAT_PERF_MATCH_CONFIG_RESERVED1_LEN = 2 ;
+
+static const uint8_t P9N2_PEC_PERTYBOCTL_REG_GRP_NOTJUSTOWN_DIS = 0 ;
+static const uint8_t P9N2_PEC_PERTYBOCTL_REG_GRP_DYN_ADJ_DIS = 1 ;
+static const uint8_t P9N2_PEC_PERTYBOCTL_REG_GRP_DYN_LVL_ADJ_DIS = 2 ;
+static const uint8_t P9N2_PEC_PERTYBOCTL_REG_GRP_RTY_CNTR_DIV2_EN = 3 ;
+static const uint8_t P9N2_PEC_PERTYBOCTL_REG_GRP_MAX_LVL_CNT_QUAL = 4 ;
+static const uint8_t P9N2_PEC_PERTYBOCTL_REG_GRP_MAX_LVL_CNT_QUAL_LEN = 4 ;
+static const uint8_t P9N2_PEC_PERTYBOCTL_REG_GRP_CNT_THRESHHLD1_QUAL = 8 ;
+static const uint8_t P9N2_PEC_PERTYBOCTL_REG_GRP_CNT_THRESHHLD1_QUAL_LEN = 6 ;
+static const uint8_t P9N2_PEC_PERTYBOCTL_REG_GRP_CNT_THRESHHLD2_QUAL = 14 ;
+static const uint8_t P9N2_PEC_PERTYBOCTL_REG_GRP_CNT_THRESHHLD2_QUAL_LEN = 6 ;
+static const uint8_t P9N2_PEC_PERTYBOCTL_REG_GRP_MSTR_RTY_BACKOFF_EN = 20 ;
+static const uint8_t P9N2_PEC_PERTYBOCTL_REG_SYS_NOTJUSTOWN_DIS = 21 ;
+static const uint8_t P9N2_PEC_PERTYBOCTL_REG_SYS_DYN_ADJ_DIS = 22 ;
+static const uint8_t P9N2_PEC_PERTYBOCTL_REG_SYS_DYN_LVL_ADJ_DIS = 23 ;
+static const uint8_t P9N2_PEC_PERTYBOCTL_REG_SYS_RTY_CNTR_DIV2_EN = 24 ;
+static const uint8_t P9N2_PEC_PERTYBOCTL_REG_SYS_MAX_LVL_CNT_QUAL = 25 ;
+static const uint8_t P9N2_PEC_PERTYBOCTL_REG_SYS_MAX_LVL_CNT_QUAL_LEN = 4 ;
+static const uint8_t P9N2_PEC_PERTYBOCTL_REG_SYS_CNT_THRESHHLD1_QUAL = 29 ;
+static const uint8_t P9N2_PEC_PERTYBOCTL_REG_SYS_CNT_THRESHHLD1_QUAL_LEN = 6 ;
+static const uint8_t P9N2_PEC_PERTYBOCTL_REG_SYS_CNT_THRESHHLD2_QUAL = 35 ;
+static const uint8_t P9N2_PEC_PERTYBOCTL_REG_SYS_CNT_THRESHHLD2_QUAL_LEN = 6 ;
+static const uint8_t P9N2_PEC_PERTYBOCTL_REG_SYS_MSTR_RTY_BACKOFF_EN = 41 ;
+
+static const uint8_t P9N2__NTL0_PESTB_ADDR_PE0_DMA_STOPPED_STATE = 0 ;
+static const uint8_t P9N2__NTL0_PESTB_ADDR_PE0_DMA_STOPPED_STATE_LEN = 37 ;
+
+static const uint8_t P9N2__NTL0_PESTB_ADDR_PE1_DMA_STOPPED_STATE = 0 ;
+static const uint8_t P9N2__NTL0_PESTB_ADDR_PE1_DMA_STOPPED_STATE_LEN = 37 ;
+
+static const uint8_t P9N2__NTL0_PESTB_ADDR_PE10_DMA_STOPPED_STATE = 0 ;
+static const uint8_t P9N2__NTL0_PESTB_ADDR_PE10_DMA_STOPPED_STATE_LEN = 37 ;
+
+static const uint8_t P9N2__NTL0_PESTB_ADDR_PE11_DMA_STOPPED_STATE = 0 ;
+static const uint8_t P9N2__NTL0_PESTB_ADDR_PE11_DMA_STOPPED_STATE_LEN = 37 ;
+
+static const uint8_t P9N2__NTL0_PESTB_ADDR_PE12_DMA_STOPPED_STATE = 0 ;
+static const uint8_t P9N2__NTL0_PESTB_ADDR_PE12_DMA_STOPPED_STATE_LEN = 37 ;
+
+static const uint8_t P9N2__NTL0_PESTB_ADDR_PE13_DMA_STOPPED_STATE = 0 ;
+static const uint8_t P9N2__NTL0_PESTB_ADDR_PE13_DMA_STOPPED_STATE_LEN = 37 ;
+
+static const uint8_t P9N2__NTL0_PESTB_ADDR_PE14_DMA_STOPPED_STATE = 0 ;
+static const uint8_t P9N2__NTL0_PESTB_ADDR_PE14_DMA_STOPPED_STATE_LEN = 37 ;
+
+static const uint8_t P9N2__NTL0_PESTB_ADDR_PE15_DMA_STOPPED_STATE = 0 ;
+static const uint8_t P9N2__NTL0_PESTB_ADDR_PE15_DMA_STOPPED_STATE_LEN = 37 ;
+
+static const uint8_t P9N2__NTL0_PESTB_ADDR_PE2_DMA_STOPPED_STATE = 0 ;
+static const uint8_t P9N2__NTL0_PESTB_ADDR_PE2_DMA_STOPPED_STATE_LEN = 37 ;
+
+static const uint8_t P9N2__NTL0_PESTB_ADDR_PE3_DMA_STOPPED_STATE = 0 ;
+static const uint8_t P9N2__NTL0_PESTB_ADDR_PE3_DMA_STOPPED_STATE_LEN = 37 ;
+
+static const uint8_t P9N2__NTL0_PESTB_ADDR_PE4_DMA_STOPPED_STATE = 0 ;
+static const uint8_t P9N2__NTL0_PESTB_ADDR_PE4_DMA_STOPPED_STATE_LEN = 37 ;
+
+static const uint8_t P9N2__NTL0_PESTB_ADDR_PE5_DMA_STOPPED_STATE = 0 ;
+static const uint8_t P9N2__NTL0_PESTB_ADDR_PE5_DMA_STOPPED_STATE_LEN = 37 ;
+
+static const uint8_t P9N2__NTL0_PESTB_ADDR_PE6_DMA_STOPPED_STATE = 0 ;
+static const uint8_t P9N2__NTL0_PESTB_ADDR_PE6_DMA_STOPPED_STATE_LEN = 37 ;
+
+static const uint8_t P9N2__NTL0_PESTB_ADDR_PE7_DMA_STOPPED_STATE = 0 ;
+static const uint8_t P9N2__NTL0_PESTB_ADDR_PE7_DMA_STOPPED_STATE_LEN = 37 ;
+
+static const uint8_t P9N2__NTL0_PESTB_ADDR_PE8_DMA_STOPPED_STATE = 0 ;
+static const uint8_t P9N2__NTL0_PESTB_ADDR_PE8_DMA_STOPPED_STATE_LEN = 37 ;
+
+static const uint8_t P9N2__NTL0_PESTB_ADDR_PE9_DMA_STOPPED_STATE = 0 ;
+static const uint8_t P9N2__NTL0_PESTB_ADDR_PE9_DMA_STOPPED_STATE_LEN = 37 ;
+
+static const uint8_t P9N2__NTL0_PESTB_DATA_PE0_DMA_STOPPED_STATE = 0 ;
+
+static const uint8_t P9N2__NTL0_PESTB_DATA_PE1_DMA_STOPPED_STATE = 0 ;
+
+static const uint8_t P9N2__NTL0_PESTB_DATA_PE10_DMA_STOPPED_STATE = 0 ;
+
+static const uint8_t P9N2__NTL0_PESTB_DATA_PE11_DMA_STOPPED_STATE = 0 ;
+
+static const uint8_t P9N2__NTL0_PESTB_DATA_PE12_DMA_STOPPED_STATE = 0 ;
+
+static const uint8_t P9N2__NTL0_PESTB_DATA_PE13_DMA_STOPPED_STATE = 0 ;
+
+static const uint8_t P9N2__NTL0_PESTB_DATA_PE14_DMA_STOPPED_STATE = 0 ;
+
+static const uint8_t P9N2__NTL0_PESTB_DATA_PE15_DMA_STOPPED_STATE = 0 ;
+
+static const uint8_t P9N2__NTL0_PESTB_DATA_PE2_DMA_STOPPED_STATE = 0 ;
+
+static const uint8_t P9N2__NTL0_PESTB_DATA_PE3_DMA_STOPPED_STATE = 0 ;
+
+static const uint8_t P9N2__NTL0_PESTB_DATA_PE4_DMA_STOPPED_STATE = 0 ;
+
+static const uint8_t P9N2__NTL0_PESTB_DATA_PE5_DMA_STOPPED_STATE = 0 ;
+
+static const uint8_t P9N2__NTL0_PESTB_DATA_PE6_DMA_STOPPED_STATE = 0 ;
+
+static const uint8_t P9N2__NTL0_PESTB_DATA_PE7_DMA_STOPPED_STATE = 0 ;
+
+static const uint8_t P9N2__NTL0_PESTB_DATA_PE8_DMA_STOPPED_STATE = 0 ;
+
+static const uint8_t P9N2__NTL0_PESTB_DATA_PE9_DMA_STOPPED_STATE = 0 ;
+
+static const uint8_t P9N2_PHB_PE_DFREEZE_REG_DFREEZE = 0 ;
+static const uint8_t P9N2_PHB_PE_DFREEZE_REG_DFREEZE_LEN = 28 ;
+
+static const uint8_t P9N2_PEC_STACK0_PE_DFREEZE_REG_DFREEZE = 0 ;
+static const uint8_t P9N2_PEC_STACK0_PE_DFREEZE_REG_DFREEZE_LEN = 28 ;
+
+static const uint8_t P9N2_PHB_PFIRACTION0_REG_PFIRACTION0 = 0 ;
+static const uint8_t P9N2_PHB_PFIRACTION0_REG_PFIRACTION0_LEN = 7 ;
+
+static const uint8_t P9N2_PHB_PFIRACTION1_REG_PFIRACTION1 = 0 ;
+static const uint8_t P9N2_PHB_PFIRACTION1_REG_PFIRACTION1_LEN = 7 ;
+
+static const uint8_t P9N2_PHB_PFIRMASK_REG_PFIRMASK = 0 ;
+static const uint8_t P9N2_PHB_PFIRMASK_REG_PFIRMASK_LEN = 7 ;
+
+static const uint8_t P9N2_PHB_PFIR_REG_PFIRPFIR = 0 ;
+static const uint8_t P9N2_PHB_PFIR_REG_PFIRPFIR_LEN = 7 ;
+
+static const uint8_t P9N2_PHB_PHB4_SCOM_HVIAR_HV_REQ_ADDR_VLD = 0 ;
+static const uint8_t P9N2_PHB_PHB4_SCOM_HVIAR_HV_REQ_4B = 1 ;
+static const uint8_t P9N2_PHB_PHB4_SCOM_HVIAR_HV_AUTO_INC = 2 ;
+static const uint8_t P9N2_PHB_PHB4_SCOM_HVIAR_HV_REQ_ADDR_VALUE = 51 ;
+static const uint8_t P9N2_PHB_PHB4_SCOM_HVIAR_HV_REQ_ADDR_VALUE_LEN = 11 ;
+
+static const uint8_t P9N2_PHB_PHB4_SCOM_UV_SEC_EXCL_ENABLE = 0 ;
+static const uint8_t P9N2_PHB_PHB4_SCOM_UV_SEC_EXCL_CMP_VALUE = 12 ;
+static const uint8_t P9N2_PHB_PHB4_SCOM_UV_SEC_EXCL_CMP_VALUE_LEN = 8 ;
+static const uint8_t P9N2_PHB_PHB4_SCOM_UV_SEC_EXCL_MSK_VALUE = 44 ;
+static const uint8_t P9N2_PHB_PHB4_SCOM_UV_SEC_EXCL_MSK_VALUE_LEN = 8 ;
+
+static const uint8_t P9N2_PHB_PHB4_SCOM_UV_SEC_INCL_CMP_ENABLE = 0 ;
+static const uint8_t P9N2_PHB_PHB4_SCOM_UV_SEC_INCL_CMP_VALUE = 12 ;
+static const uint8_t P9N2_PHB_PHB4_SCOM_UV_SEC_INCL_CMP_VALUE_LEN = 40 ;
+
+static const uint8_t P9N2_PHB_PHB4_SCOM_UV_SEC_INCL_MSK_VALUE = 12 ;
+static const uint8_t P9N2_PHB_PHB4_SCOM_UV_SEC_INCL_MSK_VALUE_LEN = 40 ;
+
+static const uint8_t P9N2_PHB_PHBBAR_REG_PE_PHB_BAR = 0 ;
+static const uint8_t P9N2_PHB_PHBBAR_REG_PE_PHB_BAR_LEN = 42 ;
+
+static const uint8_t P9N2_PEC_STACK0_PHBBAR_REG_PE_PHB_BAR = 0 ;
+static const uint8_t P9N2_PEC_STACK0_PHBBAR_REG_PE_PHB_BAR_LEN = 42 ;
+
+static const uint8_t P9N2_PHB_PHBRESET_REG_PE_ETU_RESET = 0 ;
+
+static const uint8_t P9N2_PU_NPU0_SM0_PHY_BAR_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM0_PHY_BAR_RESERVED1 = 1 ;
+static const uint8_t P9N2_PU_NPU0_SM0_PHY_BAR_RESERVED1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM0_PHY_BAR_CONFIG_GROUP = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM0_PHY_BAR_CONFIG_GROUP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM0_PHY_BAR_CONFIG_CHIP = 7 ;
+static const uint8_t P9N2_PU_NPU0_SM0_PHY_BAR_CONFIG_CHIP_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM0_PHY_BAR_CONFIG_ADDR = 10 ;
+static const uint8_t P9N2_PU_NPU0_SM0_PHY_BAR_CONFIG_ADDR_LEN = 21 ;
+static const uint8_t P9N2_PU_NPU0_SM0_PHY_BAR_CONFIG_POISON = 31 ;
+
+static const uint8_t P9N2_PU_NPU2_SM3_PHY_BAR_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM3_PHY_BAR_RESERVED1 = 1 ;
+static const uint8_t P9N2_PU_NPU2_SM3_PHY_BAR_RESERVED1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM3_PHY_BAR_CONFIG_GROUP = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM3_PHY_BAR_CONFIG_GROUP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM3_PHY_BAR_CONFIG_CHIP = 7 ;
+static const uint8_t P9N2_PU_NPU2_SM3_PHY_BAR_CONFIG_CHIP_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM3_PHY_BAR_CONFIG_ADDR = 10 ;
+static const uint8_t P9N2_PU_NPU2_SM3_PHY_BAR_CONFIG_ADDR_LEN = 21 ;
+static const uint8_t P9N2_PU_NPU2_SM3_PHY_BAR_CONFIG_POISON = 31 ;
+
+static const uint8_t P9N2_PU_NPU0_SM3_PHY_BAR_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM3_PHY_BAR_RESERVED1 = 1 ;
+static const uint8_t P9N2_PU_NPU0_SM3_PHY_BAR_RESERVED1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM3_PHY_BAR_CONFIG_GROUP = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM3_PHY_BAR_CONFIG_GROUP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM3_PHY_BAR_CONFIG_CHIP = 7 ;
+static const uint8_t P9N2_PU_NPU0_SM3_PHY_BAR_CONFIG_CHIP_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM3_PHY_BAR_CONFIG_ADDR = 10 ;
+static const uint8_t P9N2_PU_NPU0_SM3_PHY_BAR_CONFIG_ADDR_LEN = 21 ;
+static const uint8_t P9N2_PU_NPU0_SM3_PHY_BAR_CONFIG_POISON = 31 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM0_PHY_BAR_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_PHY_BAR_RESERVED1 = 1 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_PHY_BAR_RESERVED1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_PHY_BAR_CONFIG_GROUP = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_PHY_BAR_CONFIG_GROUP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_PHY_BAR_CONFIG_CHIP = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_PHY_BAR_CONFIG_CHIP_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_PHY_BAR_CONFIG_ADDR = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_PHY_BAR_CONFIG_ADDR_LEN = 21 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_PHY_BAR_CONFIG_POISON = 31 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM1_PHY_BAR_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_PHY_BAR_RESERVED1 = 1 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_PHY_BAR_RESERVED1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_PHY_BAR_CONFIG_GROUP = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_PHY_BAR_CONFIG_GROUP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_PHY_BAR_CONFIG_CHIP = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_PHY_BAR_CONFIG_CHIP_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_PHY_BAR_CONFIG_ADDR = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_PHY_BAR_CONFIG_ADDR_LEN = 21 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_PHY_BAR_CONFIG_POISON = 31 ;
+
+static const uint8_t P9N2_PU_NPU2_SM1_PHY_BAR_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM1_PHY_BAR_RESERVED1 = 1 ;
+static const uint8_t P9N2_PU_NPU2_SM1_PHY_BAR_RESERVED1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM1_PHY_BAR_CONFIG_GROUP = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM1_PHY_BAR_CONFIG_GROUP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM1_PHY_BAR_CONFIG_CHIP = 7 ;
+static const uint8_t P9N2_PU_NPU2_SM1_PHY_BAR_CONFIG_CHIP_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM1_PHY_BAR_CONFIG_ADDR = 10 ;
+static const uint8_t P9N2_PU_NPU2_SM1_PHY_BAR_CONFIG_ADDR_LEN = 21 ;
+static const uint8_t P9N2_PU_NPU2_SM1_PHY_BAR_CONFIG_POISON = 31 ;
+
+static const uint8_t P9N2_PU_NPU0_CTL_PHY_BAR_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NPU0_CTL_PHY_BAR_RESERVED1 = 1 ;
+static const uint8_t P9N2_PU_NPU0_CTL_PHY_BAR_RESERVED1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU0_CTL_PHY_BAR_CONFIG_GROUP = 3 ;
+static const uint8_t P9N2_PU_NPU0_CTL_PHY_BAR_CONFIG_GROUP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_CTL_PHY_BAR_CONFIG_CHIP = 7 ;
+static const uint8_t P9N2_PU_NPU0_CTL_PHY_BAR_CONFIG_CHIP_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU0_CTL_PHY_BAR_CONFIG_ADDR = 10 ;
+static const uint8_t P9N2_PU_NPU0_CTL_PHY_BAR_CONFIG_ADDR_LEN = 21 ;
+static const uint8_t P9N2_PU_NPU0_CTL_PHY_BAR_CONFIG_POISON = 31 ;
+
+static const uint8_t P9N2_PU_NPU2_SM0_PHY_BAR_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM0_PHY_BAR_RESERVED1 = 1 ;
+static const uint8_t P9N2_PU_NPU2_SM0_PHY_BAR_RESERVED1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM0_PHY_BAR_CONFIG_GROUP = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM0_PHY_BAR_CONFIG_GROUP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM0_PHY_BAR_CONFIG_CHIP = 7 ;
+static const uint8_t P9N2_PU_NPU2_SM0_PHY_BAR_CONFIG_CHIP_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM0_PHY_BAR_CONFIG_ADDR = 10 ;
+static const uint8_t P9N2_PU_NPU2_SM0_PHY_BAR_CONFIG_ADDR_LEN = 21 ;
+static const uint8_t P9N2_PU_NPU2_SM0_PHY_BAR_CONFIG_POISON = 31 ;
+
+static const uint8_t P9N2_PU_NPU2_CTL_PHY_BAR_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NPU2_CTL_PHY_BAR_RESERVED1 = 1 ;
+static const uint8_t P9N2_PU_NPU2_CTL_PHY_BAR_RESERVED1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_CTL_PHY_BAR_CONFIG_GROUP = 3 ;
+static const uint8_t P9N2_PU_NPU2_CTL_PHY_BAR_CONFIG_GROUP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_CTL_PHY_BAR_CONFIG_CHIP = 7 ;
+static const uint8_t P9N2_PU_NPU2_CTL_PHY_BAR_CONFIG_CHIP_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU2_CTL_PHY_BAR_CONFIG_ADDR = 10 ;
+static const uint8_t P9N2_PU_NPU2_CTL_PHY_BAR_CONFIG_ADDR_LEN = 21 ;
+static const uint8_t P9N2_PU_NPU2_CTL_PHY_BAR_CONFIG_POISON = 31 ;
+
+static const uint8_t P9N2_PU_NPU0_SM1_PHY_BAR_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM1_PHY_BAR_RESERVED1 = 1 ;
+static const uint8_t P9N2_PU_NPU0_SM1_PHY_BAR_RESERVED1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM1_PHY_BAR_CONFIG_GROUP = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM1_PHY_BAR_CONFIG_GROUP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM1_PHY_BAR_CONFIG_CHIP = 7 ;
+static const uint8_t P9N2_PU_NPU0_SM1_PHY_BAR_CONFIG_CHIP_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM1_PHY_BAR_CONFIG_ADDR = 10 ;
+static const uint8_t P9N2_PU_NPU0_SM1_PHY_BAR_CONFIG_ADDR_LEN = 21 ;
+static const uint8_t P9N2_PU_NPU0_SM1_PHY_BAR_CONFIG_POISON = 31 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_CTL_PHY_BAR_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_PHY_BAR_RESERVED1 = 1 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_PHY_BAR_RESERVED1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_PHY_BAR_CONFIG_GROUP = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_PHY_BAR_CONFIG_GROUP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_PHY_BAR_CONFIG_CHIP = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_PHY_BAR_CONFIG_CHIP_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_PHY_BAR_CONFIG_ADDR = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_PHY_BAR_CONFIG_ADDR_LEN = 21 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_PHY_BAR_CONFIG_POISON = 31 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM3_PHY_BAR_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_PHY_BAR_RESERVED1 = 1 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_PHY_BAR_RESERVED1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_PHY_BAR_CONFIG_GROUP = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_PHY_BAR_CONFIG_GROUP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_PHY_BAR_CONFIG_CHIP = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_PHY_BAR_CONFIG_CHIP_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_PHY_BAR_CONFIG_ADDR = 10 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_PHY_BAR_CONFIG_ADDR_LEN = 21 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_PHY_BAR_CONFIG_POISON = 31 ;
+
+static const uint8_t P9N2_PU_PIBI2CM_ATOMIC_LOCK_REG_B_CC_ENABLE_0 = 0 ;
+static const uint8_t P9N2_PU_PIBI2CM_ATOMIC_LOCK_REG_B_CC_ID_0 = 1 ;
+static const uint8_t P9N2_PU_PIBI2CM_ATOMIC_LOCK_REG_B_CC_ID_0_LEN = 4 ;
+static const uint8_t P9N2_PU_PIBI2CM_ATOMIC_LOCK_REG_B_CC_ACTIVITY_0 = 8 ;
+static const uint8_t P9N2_PU_PIBI2CM_ATOMIC_LOCK_REG_B_CC_ACTIVITY_0_LEN = 8 ;
+
+static const uint8_t P9N2_PU_PIBI2CM_ATOMIC_LOCK_REG_C_CC_ENABLE_1 = 0 ;
+static const uint8_t P9N2_PU_PIBI2CM_ATOMIC_LOCK_REG_C_CC_ID_1 = 1 ;
+static const uint8_t P9N2_PU_PIBI2CM_ATOMIC_LOCK_REG_C_CC_ID_1_LEN = 4 ;
+static const uint8_t P9N2_PU_PIBI2CM_ATOMIC_LOCK_REG_C_CC_ACTIVITY_1 = 8 ;
+static const uint8_t P9N2_PU_PIBI2CM_ATOMIC_LOCK_REG_C_CC_ACTIVITY_1_LEN = 8 ;
+
+static const uint8_t P9N2_PU_PIBI2CM_ATOMIC_LOCK_REG_D_CC_ENABLE_2 = 0 ;
+static const uint8_t P9N2_PU_PIBI2CM_ATOMIC_LOCK_REG_D_CC_ID_2 = 1 ;
+static const uint8_t P9N2_PU_PIBI2CM_ATOMIC_LOCK_REG_D_CC_ID_2_LEN = 4 ;
+static const uint8_t P9N2_PU_PIBI2CM_ATOMIC_LOCK_REG_D_CC_ACTIVITY_2 = 8 ;
+static const uint8_t P9N2_PU_PIBI2CM_ATOMIC_LOCK_REG_D_CC_ACTIVITY_2_LEN = 8 ;
+
+static const uint8_t P9N2_PU_PIBI2CM_ATOMIC_LOCK_REG_E_CC_ENABLE_3 = 0 ;
+static const uint8_t P9N2_PU_PIBI2CM_ATOMIC_LOCK_REG_E_CC_ID_3 = 1 ;
+static const uint8_t P9N2_PU_PIBI2CM_ATOMIC_LOCK_REG_E_CC_ID_3_LEN = 4 ;
+static const uint8_t P9N2_PU_PIBI2CM_ATOMIC_LOCK_REG_E_CC_ACTIVITY_3 = 8 ;
+static const uint8_t P9N2_PU_PIBI2CM_ATOMIC_LOCK_REG_E_CC_ACTIVITY_3_LEN = 8 ;
+
+static const uint8_t P9N2_PU_PIBI2CM_PROTECT_MODE_REG_B_CC_READ_ENABLE_0 = 0 ;
+static const uint8_t P9N2_PU_PIBI2CM_PROTECT_MODE_REG_B_CC_WRITE_ENABLE_0 = 1 ;
+
+static const uint8_t P9N2_PU_PIBI2CM_PROTECT_MODE_REG_C_CC_READ_ENABLE_1 = 0 ;
+static const uint8_t P9N2_PU_PIBI2CM_PROTECT_MODE_REG_C_CC_WRITE_ENABLE_1 = 1 ;
+
+static const uint8_t P9N2_PU_PIBI2CM_PROTECT_MODE_REG_D_CC_READ_ENABLE_2 = 0 ;
+static const uint8_t P9N2_PU_PIBI2CM_PROTECT_MODE_REG_D_CC_WRITE_ENABLE_2 = 1 ;
+
+static const uint8_t P9N2_PU_PIBI2CM_PROTECT_MODE_REG_E_CC_READ_ENABLE_3 = 0 ;
+static const uint8_t P9N2_PU_PIBI2CM_PROTECT_MODE_REG_E_CC_WRITE_ENABLE_3 = 1 ;
+
+static const uint8_t P9N2_PU_PIBMEM_ADDRESS_REGISTER_POINTER = 48 ;
+static const uint8_t P9N2_PU_PIBMEM_ADDRESS_REGISTER_POINTER_LEN = 16 ;
+
+static const uint8_t P9N2_PU_PIBMEM_ADDRESS_REGISTER_FA_POINTER = 48 ;
+static const uint8_t P9N2_PU_PIBMEM_ADDRESS_REGISTER_FA_POINTER_LEN = 16 ;
+
+static const uint8_t P9N2_PU_PIBMEM_CONTROL_REGISTER_AUTO_PRE_INCREMENT_PIB = 0 ;
+static const uint8_t P9N2_PU_PIBMEM_CONTROL_REGISTER_AUTO_POST_DECREMENT_PIB = 1 ;
+static const uint8_t P9N2_PU_PIBMEM_CONTROL_REGISTER_DISABLE_ECC = 2 ;
+static const uint8_t P9N2_PU_PIBMEM_CONTROL_REGISTER_AUTO_PRE_INCREMENT_FACES = 3 ;
+static const uint8_t P9N2_PU_PIBMEM_CONTROL_REGISTER_AUTO_POST_DECREMENT_FACES = 4 ;
+static const uint8_t P9N2_PU_PIBMEM_CONTROL_REGISTER_CHKSW_AR012 = 5 ;
+
+static const uint8_t P9N2_PU_PIBMEM_REPAIR_REGISTER_0_DATA = 0 ;
+static const uint8_t P9N2_PU_PIBMEM_REPAIR_REGISTER_0_DATA_LEN = 2 ;
+
+static const uint8_t P9N2_PU_PIBMEM_REPAIR_REGISTER_1_DATA = 0 ;
+static const uint8_t P9N2_PU_PIBMEM_REPAIR_REGISTER_1_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_PU_PIBMEM_REPAIR_REGISTER_2_DATA = 0 ;
+static const uint8_t P9N2_PU_PIBMEM_REPAIR_REGISTER_2_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_PU_PIBMEM_REPAIR_REGISTER_3_DATA = 0 ;
+static const uint8_t P9N2_PU_PIBMEM_REPAIR_REGISTER_3_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_PU_PIBMEM_RESET_REGISTER_RESET = 0 ;
+static const uint8_t P9N2_PU_PIBMEM_RESET_REGISTER_RESET_LEN = 2 ;
+
+static const uint8_t P9N2_PU_PIBMEM_STATUS_REG_ADDR_INVALID_PIB = 0 ;
+static const uint8_t P9N2_PU_PIBMEM_STATUS_REG_WRITE_INVALID_PIB = 1 ;
+static const uint8_t P9N2_PU_PIBMEM_STATUS_REG_READ_INVALID_PIB = 2 ;
+static const uint8_t P9N2_PU_PIBMEM_STATUS_REG_ECC_UNCORRECTED_ERROR_PIB = 3 ;
+static const uint8_t P9N2_PU_PIBMEM_STATUS_REG_ECC_CORRECTED_ERROR_PIB = 4 ;
+static const uint8_t P9N2_PU_PIBMEM_STATUS_REG_BAD_ARRAY_ADDRESS_PIB = 5 ;
+static const uint8_t P9N2_PU_PIBMEM_STATUS_REG_WRITE_RST_INTERRUPT_PIB = 6 ;
+static const uint8_t P9N2_PU_PIBMEM_STATUS_REG_READ_RST_INTERRUPT_PIB = 7 ;
+static const uint8_t P9N2_PU_PIBMEM_STATUS_REG_FSM_PRESENT_STATE = 12 ;
+static const uint8_t P9N2_PU_PIBMEM_STATUS_REG_FSM_PRESENT_STATE_LEN = 7 ;
+static const uint8_t P9N2_PU_PIBMEM_STATUS_REG_ADDR_INVALID_FACES = 19 ;
+static const uint8_t P9N2_PU_PIBMEM_STATUS_REG_WRITE_INVALID_FACES = 20 ;
+static const uint8_t P9N2_PU_PIBMEM_STATUS_REG_READ_INVALID_FACES = 21 ;
+static const uint8_t P9N2_PU_PIBMEM_STATUS_REG_ECC_UNCORRECTED_ERROR_FACES = 22 ;
+static const uint8_t P9N2_PU_PIBMEM_STATUS_REG_ECC_CORRECTED_ERROR_FACES = 23 ;
+static const uint8_t P9N2_PU_PIBMEM_STATUS_REG_BAD_ARRAY_ADDRESS_FACES = 24 ;
+static const uint8_t P9N2_PU_PIBMEM_STATUS_REG_WRITE_RST_INTERRUPT_FACES = 25 ;
+static const uint8_t P9N2_PU_PIBMEM_STATUS_REG_READ_RST_INTERRUPT_FACES = 26 ;
+static const uint8_t P9N2_PU_PIBMEM_STATUS_REG_ADDR_RESET_INTR_PIB = 32 ;
+static const uint8_t P9N2_PU_PIBMEM_STATUS_REG_ADDR_RESET_INTR_PIB_LEN = 16 ;
+static const uint8_t P9N2_PU_PIBMEM_STATUS_REG_ADDR_RESET_INTR_FACES = 48 ;
+static const uint8_t P9N2_PU_PIBMEM_STATUS_REG_ADDR_RESET_INTR_FACES_LEN = 16 ;
+
+static const uint8_t P9N2_PU_PIB_CMD_REG_RNW = 0 ;
+static const uint8_t P9N2_PU_PIB_CMD_REG_ADR = 30 ;
+static const uint8_t P9N2_PU_PIB_CMD_REG_ADR_LEN = 31 ;
+
+static const uint8_t P9N2_PU_PIB_DATA_REG_DATA = 0 ;
+static const uint8_t P9N2_PU_PIB_DATA_REG_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_PU_PIB_RESET_REG_RESET = 0 ;
+static const uint8_t P9N2_PU_PIB_RESET_REG_STATE = 1 ;
+static const uint8_t P9N2_PU_PIB_RESET_REG_ABORTED_CMD = 2 ;
+
+static const uint8_t P9N2_PEC_PLL_LOCK_REG_LOCK = 0 ;
+static const uint8_t P9N2_PEC_PLL_LOCK_REG_LOCK_LEN = 4 ;
+
+static const uint8_t P9N2_PEC_PMONCTL_REG_PE_PMON_EN = 0 ;
+static const uint8_t P9N2_PEC_PMONCTL_REG_PE_PMON_EN_LEN = 16 ;
+static const uint8_t P9N2_PEC_PMONCTL_REG_RESERVED = 16 ;
+static const uint8_t P9N2_PEC_PMONCTL_REG_PE_PMON_ALL_ENGINES = 17 ;
+static const uint8_t P9N2_PEC_PMONCTL_REG_PE_PMON_STK = 18 ;
+static const uint8_t P9N2_PEC_PMONCTL_REG_PE_PMON_STK_LEN = 2 ;
+static const uint8_t P9N2_PEC_PMONCTL_REG_PE_PMON_RD_TYPE = 20 ;
+static const uint8_t P9N2_PEC_PMONCTL_REG_PE_PMON_RD_TYPE_LEN = 2 ;
+static const uint8_t P9N2_PEC_PMONCTL_REG_PE_PMON_MUX_BYTE0 = 22 ;
+static const uint8_t P9N2_PEC_PMONCTL_REG_PE_PMON_MUX_BYTE0_LEN = 3 ;
+static const uint8_t P9N2_PEC_PMONCTL_REG_PE_PMON_MUX_BYTE1 = 25 ;
+static const uint8_t P9N2_PEC_PMONCTL_REG_PE_PMON_MUX_BYTE1_LEN = 3 ;
+
+static const uint8_t P9N2_CAPP_PMU_CNTRA_CFG_PMUA_ENABLE = 0 ;
+static const uint8_t P9N2_CAPP_PMU_CNTRA_CFG_PMUA_CASCADE_SELECT = 1 ;
+static const uint8_t P9N2_CAPP_PMU_CNTRA_CFG_PMUA_CASCADE_SELECT_LEN = 3 ;
+static const uint8_t P9N2_CAPP_PMU_CNTRA_CFG_PMUA_COUNTER_FREEZE_MODE = 7 ;
+static const uint8_t P9N2_CAPP_PMU_CNTRA_CFG_PMUA_COUNTER_RESET_MODE = 8 ;
+static const uint8_t P9N2_CAPP_PMU_CNTRA_CFG_PMUA_COUNTER0_PRESCALER_SELECT = 9 ;
+static const uint8_t P9N2_CAPP_PMU_CNTRA_CFG_PMUA_COUNTER0_PRESCALER_SELECT_LEN = 2 ;
+static const uint8_t P9N2_CAPP_PMU_CNTRA_CFG_PMUA_COUNTER0_BIT_PAIR_SELECT = 11 ;
+static const uint8_t P9N2_CAPP_PMU_CNTRA_CFG_PMUA_COUNTER0_BIT_PAIR_SELECT_LEN = 2 ;
+static const uint8_t P9N2_CAPP_PMU_CNTRA_CFG_PMUA_COUNTER1_PRESCALER_SELECT = 16 ;
+static const uint8_t P9N2_CAPP_PMU_CNTRA_CFG_PMUA_COUNTER1_PRESCALER_SELECT_LEN = 2 ;
+static const uint8_t P9N2_CAPP_PMU_CNTRA_CFG_PMUA_COUNTER1_BIT_PAIR_SELECT = 18 ;
+static const uint8_t P9N2_CAPP_PMU_CNTRA_CFG_PMUA_COUNTER1_BIT_PAIR_SELECT_LEN = 2 ;
+static const uint8_t P9N2_CAPP_PMU_CNTRA_CFG_PMUA_COUNTER2_PRESCALER_SELECT = 23 ;
+static const uint8_t P9N2_CAPP_PMU_CNTRA_CFG_PMUA_COUNTER2_PRESCALER_SELECT_LEN = 2 ;
+static const uint8_t P9N2_CAPP_PMU_CNTRA_CFG_PMUA_COUNTER2_BIT_PAIR_SELECT = 25 ;
+static const uint8_t P9N2_CAPP_PMU_CNTRA_CFG_PMUA_COUNTER2_BIT_PAIR_SELECT_LEN = 2 ;
+static const uint8_t P9N2_CAPP_PMU_CNTRA_CFG_PMUA_COUNTER3_PRESCALER_SELECT = 30 ;
+static const uint8_t P9N2_CAPP_PMU_CNTRA_CFG_PMUA_COUNTER3_PRESCALER_SELECT_LEN = 2 ;
+static const uint8_t P9N2_CAPP_PMU_CNTRA_CFG_PMUA_COUNTER3_BIT_PAIR_SELECT = 32 ;
+static const uint8_t P9N2_CAPP_PMU_CNTRA_CFG_PMUA_COUNTER3_BIT_PAIR_SELECT_LEN = 2 ;
+static const uint8_t P9N2_CAPP_PMU_CNTRA_CFG_PMUA_PORT_SELECT = 37 ;
+static const uint8_t P9N2_CAPP_PMU_CNTRA_CFG_PMUA_PORT_SELECT_LEN = 2 ;
+
+static const uint8_t P9N2_CAPP_PMU_CNTRA_REG_COUNTERA_0 = 0 ;
+static const uint8_t P9N2_CAPP_PMU_CNTRA_REG_COUNTERA_0_LEN = 16 ;
+static const uint8_t P9N2_CAPP_PMU_CNTRA_REG_COUNTERA_1 = 16 ;
+static const uint8_t P9N2_CAPP_PMU_CNTRA_REG_COUNTERA_1_LEN = 16 ;
+static const uint8_t P9N2_CAPP_PMU_CNTRA_REG_COUNTERA_2 = 32 ;
+static const uint8_t P9N2_CAPP_PMU_CNTRA_REG_COUNTERA_2_LEN = 16 ;
+static const uint8_t P9N2_CAPP_PMU_CNTRA_REG_COUNTERA_3 = 48 ;
+static const uint8_t P9N2_CAPP_PMU_CNTRA_REG_COUNTERA_3_LEN = 16 ;
+
+static const uint8_t P9N2_CAPP_PMU_CNTRB_CFG_PMUB_ENABLE = 0 ;
+static const uint8_t P9N2_CAPP_PMU_CNTRB_CFG_PMUB_CASCADE_SELECT = 1 ;
+static const uint8_t P9N2_CAPP_PMU_CNTRB_CFG_PMUB_CASCADE_SELECT_LEN = 3 ;
+static const uint8_t P9N2_CAPP_PMU_CNTRB_CFG_PMUB_COUNTER_FREEZE_MODE = 7 ;
+static const uint8_t P9N2_CAPP_PMU_CNTRB_CFG_PMUB_COUNTER_RESET_MODE = 8 ;
+static const uint8_t P9N2_CAPP_PMU_CNTRB_CFG_PMUB_COUNTER0_PRESCALER_SELECT = 9 ;
+static const uint8_t P9N2_CAPP_PMU_CNTRB_CFG_PMUB_COUNTER0_PRESCALER_SELECT_LEN = 2 ;
+static const uint8_t P9N2_CAPP_PMU_CNTRB_CFG_PMUB_COUNTER0_BIT_PAIR_SELECT = 11 ;
+static const uint8_t P9N2_CAPP_PMU_CNTRB_CFG_PMUB_COUNTER0_BIT_PAIR_SELECT_LEN = 2 ;
+static const uint8_t P9N2_CAPP_PMU_CNTRB_CFG_PMUB_COUNTER1_PRESCALER_SELECT = 16 ;
+static const uint8_t P9N2_CAPP_PMU_CNTRB_CFG_PMUB_COUNTER1_PRESCALER_SELECT_LEN = 2 ;
+static const uint8_t P9N2_CAPP_PMU_CNTRB_CFG_PMUB_COUNTER1_BIT_PAIR_SELECT = 18 ;
+static const uint8_t P9N2_CAPP_PMU_CNTRB_CFG_PMUB_COUNTER1_BIT_PAIR_SELECT_LEN = 2 ;
+static const uint8_t P9N2_CAPP_PMU_CNTRB_CFG_PMUB_COUNTER2_PRESCALER_SELECT = 23 ;
+static const uint8_t P9N2_CAPP_PMU_CNTRB_CFG_PMUB_COUNTER2_PRESCALER_SELECT_LEN = 2 ;
+static const uint8_t P9N2_CAPP_PMU_CNTRB_CFG_PMUB_COUNTER2_BIT_PAIR_SELECT = 25 ;
+static const uint8_t P9N2_CAPP_PMU_CNTRB_CFG_PMUB_COUNTER2_BIT_PAIR_SELECT_LEN = 2 ;
+static const uint8_t P9N2_CAPP_PMU_CNTRB_CFG_PMUB_COUNTER3_PRESCALER_SELECT = 30 ;
+static const uint8_t P9N2_CAPP_PMU_CNTRB_CFG_PMUB_COUNTER3_PRESCALER_SELECT_LEN = 2 ;
+static const uint8_t P9N2_CAPP_PMU_CNTRB_CFG_PMUB_COUNTER3_BIT_PAIR_SELECT = 32 ;
+static const uint8_t P9N2_CAPP_PMU_CNTRB_CFG_PMUB_COUNTER3_BIT_PAIR_SELECT_LEN = 2 ;
+static const uint8_t P9N2_CAPP_PMU_CNTRB_CFG_PMUB_PORT_SELECT = 37 ;
+static const uint8_t P9N2_CAPP_PMU_CNTRB_CFG_PMUB_PORT_SELECT_LEN = 2 ;
+
+static const uint8_t P9N2_CAPP_PMU_CNTRB_REG_COUNTERB_0 = 0 ;
+static const uint8_t P9N2_CAPP_PMU_CNTRB_REG_COUNTERB_0_LEN = 16 ;
+static const uint8_t P9N2_CAPP_PMU_CNTRB_REG_COUNTERB_1 = 16 ;
+static const uint8_t P9N2_CAPP_PMU_CNTRB_REG_COUNTERB_1_LEN = 16 ;
+static const uint8_t P9N2_CAPP_PMU_CNTRB_REG_COUNTERB_2 = 32 ;
+static const uint8_t P9N2_CAPP_PMU_CNTRB_REG_COUNTERB_2_LEN = 16 ;
+static const uint8_t P9N2_CAPP_PMU_CNTRB_REG_COUNTERB_3 = 48 ;
+static const uint8_t P9N2_CAPP_PMU_CNTRB_REG_COUNTERB_3_LEN = 16 ;
+
+static const uint8_t P9N2__NTL0_PMU_CONTROL0_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2__NTL0_PMU_CONTROL0_CONFIG_RESETMODE = 1 ;
+static const uint8_t P9N2__NTL0_PMU_CONTROL0_CONFIG_FREEZEMODE = 2 ;
+static const uint8_t P9N2__NTL0_PMU_CONTROL0_CONFIG_DISABLE_PMISC = 3 ;
+static const uint8_t P9N2__NTL0_PMU_CONTROL0_CONFIG_PMISC_MODE = 4 ;
+static const uint8_t P9N2__NTL0_PMU_CONTROL0_CONFIG_CASCADE = 5 ;
+static const uint8_t P9N2__NTL0_PMU_CONTROL0_CONFIG_CASCADE_LEN = 3 ;
+static const uint8_t P9N2__NTL0_PMU_CONTROL0_CONFIG_PRESCALE_C0 = 8 ;
+static const uint8_t P9N2__NTL0_PMU_CONTROL0_CONFIG_PRESCALE_C0_LEN = 2 ;
+static const uint8_t P9N2__NTL0_PMU_CONTROL0_CONFIG_PRESCALE_C1 = 10 ;
+static const uint8_t P9N2__NTL0_PMU_CONTROL0_CONFIG_PRESCALE_C1_LEN = 2 ;
+static const uint8_t P9N2__NTL0_PMU_CONTROL0_CONFIG_PRESCALE_C2 = 12 ;
+static const uint8_t P9N2__NTL0_PMU_CONTROL0_CONFIG_PRESCALE_C2_LEN = 2 ;
+static const uint8_t P9N2__NTL0_PMU_CONTROL0_CONFIG_PRESCALE_C3 = 14 ;
+static const uint8_t P9N2__NTL0_PMU_CONTROL0_CONFIG_PRESCALE_C3_LEN = 2 ;
+static const uint8_t P9N2__NTL0_PMU_CONTROL0_CONFIG_OPERATION_C0 = 16 ;
+static const uint8_t P9N2__NTL0_PMU_CONTROL0_CONFIG_OPERATION_C0_LEN = 2 ;
+static const uint8_t P9N2__NTL0_PMU_CONTROL0_CONFIG_OPERATION_C1 = 18 ;
+static const uint8_t P9N2__NTL0_PMU_CONTROL0_CONFIG_OPERATION_C1_LEN = 2 ;
+static const uint8_t P9N2__NTL0_PMU_CONTROL0_CONFIG_OPERATION_C2 = 20 ;
+static const uint8_t P9N2__NTL0_PMU_CONTROL0_CONFIG_OPERATION_C2_LEN = 2 ;
+static const uint8_t P9N2__NTL0_PMU_CONTROL0_CONFIG_OPERATION_C3 = 22 ;
+static const uint8_t P9N2__NTL0_PMU_CONTROL0_CONFIG_OPERATION_C3_LEN = 2 ;
+static const uint8_t P9N2__NTL0_PMU_CONTROL0_CONFIG_EVENTS_C0 = 24 ;
+static const uint8_t P9N2__NTL0_PMU_CONTROL0_CONFIG_EVENTS_C0_LEN = 8 ;
+static const uint8_t P9N2__NTL0_PMU_CONTROL0_CONFIG_EVENTS_C1 = 32 ;
+static const uint8_t P9N2__NTL0_PMU_CONTROL0_CONFIG_EVENTS_C1_LEN = 8 ;
+static const uint8_t P9N2__NTL0_PMU_CONTROL0_CONFIG_EVENTS_C2 = 40 ;
+static const uint8_t P9N2__NTL0_PMU_CONTROL0_CONFIG_EVENTS_C2_LEN = 8 ;
+static const uint8_t P9N2__NTL0_PMU_CONTROL0_CONFIG_EVENTS_C3 = 48 ;
+static const uint8_t P9N2__NTL0_PMU_CONTROL0_CONFIG_EVENTS_C3_LEN = 8 ;
+static const uint8_t P9N2__NTL0_PMU_CONTROL0_CONFIG_RESERVED0 = 56 ;
+static const uint8_t P9N2__NTL0_PMU_CONTROL0_CONFIG_RESERVED0_LEN = 8 ;
+
+static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL0_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL0_CONFIG_RESETMODE = 1 ;
+static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL0_CONFIG_FREEZEMODE = 2 ;
+static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL0_CONFIG_DISABLE_PMISC = 3 ;
+static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL0_CONFIG_PMISC_MODE = 4 ;
+static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL0_CONFIG_CASCADE = 5 ;
+static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL0_CONFIG_CASCADE_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL0_CONFIG_PRESCALE_C0 = 8 ;
+static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL0_CONFIG_PRESCALE_C0_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL0_CONFIG_PRESCALE_C1 = 10 ;
+static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL0_CONFIG_PRESCALE_C1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL0_CONFIG_PRESCALE_C2 = 12 ;
+static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL0_CONFIG_PRESCALE_C2_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL0_CONFIG_PRESCALE_C3 = 14 ;
+static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL0_CONFIG_PRESCALE_C3_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL0_CONFIG_OPERATION_C0 = 16 ;
+static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL0_CONFIG_OPERATION_C0_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL0_CONFIG_OPERATION_C1 = 18 ;
+static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL0_CONFIG_OPERATION_C1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL0_CONFIG_OPERATION_C2 = 20 ;
+static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL0_CONFIG_OPERATION_C2_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL0_CONFIG_OPERATION_C3 = 22 ;
+static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL0_CONFIG_OPERATION_C3_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL0_CONFIG_EVENTS_C0 = 24 ;
+static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL0_CONFIG_EVENTS_C0_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL0_CONFIG_EVENTS_C1 = 32 ;
+static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL0_CONFIG_EVENTS_C1_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL0_CONFIG_EVENTS_C2 = 40 ;
+static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL0_CONFIG_EVENTS_C2_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL0_CONFIG_EVENTS_C3 = 48 ;
+static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL0_CONFIG_EVENTS_C3_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL0_CONFIG_RESERVED0 = 56 ;
+static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL0_CONFIG_RESERVED0_LEN = 8 ;
+
+static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL0_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL0_CONFIG_RESETMODE = 1 ;
+static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL0_CONFIG_FREEZEMODE = 2 ;
+static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL0_CONFIG_DISABLE_PMISC = 3 ;
+static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL0_CONFIG_PMISC_MODE = 4 ;
+static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL0_CONFIG_CASCADE = 5 ;
+static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL0_CONFIG_CASCADE_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL0_CONFIG_PRESCALE_C0 = 8 ;
+static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL0_CONFIG_PRESCALE_C0_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL0_CONFIG_PRESCALE_C1 = 10 ;
+static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL0_CONFIG_PRESCALE_C1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL0_CONFIG_PRESCALE_C2 = 12 ;
+static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL0_CONFIG_PRESCALE_C2_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL0_CONFIG_PRESCALE_C3 = 14 ;
+static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL0_CONFIG_PRESCALE_C3_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL0_CONFIG_OPERATION_C0 = 16 ;
+static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL0_CONFIG_OPERATION_C0_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL0_CONFIG_OPERATION_C1 = 18 ;
+static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL0_CONFIG_OPERATION_C1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL0_CONFIG_OPERATION_C2 = 20 ;
+static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL0_CONFIG_OPERATION_C2_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL0_CONFIG_OPERATION_C3 = 22 ;
+static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL0_CONFIG_OPERATION_C3_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL0_CONFIG_EVENTS_C0 = 24 ;
+static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL0_CONFIG_EVENTS_C0_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL0_CONFIG_EVENTS_C1 = 32 ;
+static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL0_CONFIG_EVENTS_C1_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL0_CONFIG_EVENTS_C2 = 40 ;
+static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL0_CONFIG_EVENTS_C2_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL0_CONFIG_EVENTS_C3 = 48 ;
+static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL0_CONFIG_EVENTS_C3_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL0_CONFIG_RESERVED0 = 56 ;
+static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL0_CONFIG_RESERVED0_LEN = 8 ;
+
+static const uint8_t P9N2_PU_NPU_NTL0_PMU_CONTROL0_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NPU_NTL0_PMU_CONTROL0_CONFIG_RESETMODE = 1 ;
+static const uint8_t P9N2_PU_NPU_NTL0_PMU_CONTROL0_CONFIG_FREEZEMODE = 2 ;
+static const uint8_t P9N2_PU_NPU_NTL0_PMU_CONTROL0_CONFIG_DISABLE_PMISC = 3 ;
+static const uint8_t P9N2_PU_NPU_NTL0_PMU_CONTROL0_CONFIG_PMISC_MODE = 4 ;
+static const uint8_t P9N2_PU_NPU_NTL0_PMU_CONTROL0_CONFIG_CASCADE = 5 ;
+static const uint8_t P9N2_PU_NPU_NTL0_PMU_CONTROL0_CONFIG_CASCADE_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_NTL0_PMU_CONTROL0_CONFIG_PRESCALE_C0 = 8 ;
+static const uint8_t P9N2_PU_NPU_NTL0_PMU_CONTROL0_CONFIG_PRESCALE_C0_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_NTL0_PMU_CONTROL0_CONFIG_PRESCALE_C1 = 10 ;
+static const uint8_t P9N2_PU_NPU_NTL0_PMU_CONTROL0_CONFIG_PRESCALE_C1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_NTL0_PMU_CONTROL0_CONFIG_PRESCALE_C2 = 12 ;
+static const uint8_t P9N2_PU_NPU_NTL0_PMU_CONTROL0_CONFIG_PRESCALE_C2_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_NTL0_PMU_CONTROL0_CONFIG_PRESCALE_C3 = 14 ;
+static const uint8_t P9N2_PU_NPU_NTL0_PMU_CONTROL0_CONFIG_PRESCALE_C3_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_NTL0_PMU_CONTROL0_CONFIG_OPERATION_C0 = 16 ;
+static const uint8_t P9N2_PU_NPU_NTL0_PMU_CONTROL0_CONFIG_OPERATION_C0_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_NTL0_PMU_CONTROL0_CONFIG_OPERATION_C1 = 18 ;
+static const uint8_t P9N2_PU_NPU_NTL0_PMU_CONTROL0_CONFIG_OPERATION_C1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_NTL0_PMU_CONTROL0_CONFIG_OPERATION_C2 = 20 ;
+static const uint8_t P9N2_PU_NPU_NTL0_PMU_CONTROL0_CONFIG_OPERATION_C2_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_NTL0_PMU_CONTROL0_CONFIG_OPERATION_C3 = 22 ;
+static const uint8_t P9N2_PU_NPU_NTL0_PMU_CONTROL0_CONFIG_OPERATION_C3_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_NTL0_PMU_CONTROL0_CONFIG_EVENTS_C0 = 24 ;
+static const uint8_t P9N2_PU_NPU_NTL0_PMU_CONTROL0_CONFIG_EVENTS_C0_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_NTL0_PMU_CONTROL0_CONFIG_EVENTS_C1 = 32 ;
+static const uint8_t P9N2_PU_NPU_NTL0_PMU_CONTROL0_CONFIG_EVENTS_C1_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_NTL0_PMU_CONTROL0_CONFIG_EVENTS_C2 = 40 ;
+static const uint8_t P9N2_PU_NPU_NTL0_PMU_CONTROL0_CONFIG_EVENTS_C2_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_NTL0_PMU_CONTROL0_CONFIG_EVENTS_C3 = 48 ;
+static const uint8_t P9N2_PU_NPU_NTL0_PMU_CONTROL0_CONFIG_EVENTS_C3_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_NTL0_PMU_CONTROL0_CONFIG_RESERVED0 = 56 ;
+static const uint8_t P9N2_PU_NPU_NTL0_PMU_CONTROL0_CONFIG_RESERVED0_LEN = 8 ;
+
+static const uint8_t P9N2__CTL_PMU_CONTROL0_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2__CTL_PMU_CONTROL0_CONFIG_RESETMODE = 1 ;
+static const uint8_t P9N2__CTL_PMU_CONTROL0_CONFIG_FREEZEMODE = 2 ;
+static const uint8_t P9N2__CTL_PMU_CONTROL0_CONFIG_DISABLE_PMISC = 3 ;
+static const uint8_t P9N2__CTL_PMU_CONTROL0_CONFIG_PMISC_MODE = 4 ;
+static const uint8_t P9N2__CTL_PMU_CONTROL0_CONFIG_CASCADE = 5 ;
+static const uint8_t P9N2__CTL_PMU_CONTROL0_CONFIG_CASCADE_LEN = 3 ;
+static const uint8_t P9N2__CTL_PMU_CONTROL0_CONFIG_PRESCALE_C0 = 8 ;
+static const uint8_t P9N2__CTL_PMU_CONTROL0_CONFIG_PRESCALE_C0_LEN = 2 ;
+static const uint8_t P9N2__CTL_PMU_CONTROL0_CONFIG_PRESCALE_C1 = 10 ;
+static const uint8_t P9N2__CTL_PMU_CONTROL0_CONFIG_PRESCALE_C1_LEN = 2 ;
+static const uint8_t P9N2__CTL_PMU_CONTROL0_CONFIG_PRESCALE_C2 = 12 ;
+static const uint8_t P9N2__CTL_PMU_CONTROL0_CONFIG_PRESCALE_C2_LEN = 2 ;
+static const uint8_t P9N2__CTL_PMU_CONTROL0_CONFIG_PRESCALE_C3 = 14 ;
+static const uint8_t P9N2__CTL_PMU_CONTROL0_CONFIG_PRESCALE_C3_LEN = 2 ;
+static const uint8_t P9N2__CTL_PMU_CONTROL0_CONFIG_OPERATION_C0 = 16 ;
+static const uint8_t P9N2__CTL_PMU_CONTROL0_CONFIG_OPERATION_C0_LEN = 2 ;
+static const uint8_t P9N2__CTL_PMU_CONTROL0_CONFIG_OPERATION_C1 = 18 ;
+static const uint8_t P9N2__CTL_PMU_CONTROL0_CONFIG_OPERATION_C1_LEN = 2 ;
+static const uint8_t P9N2__CTL_PMU_CONTROL0_CONFIG_OPERATION_C2 = 20 ;
+static const uint8_t P9N2__CTL_PMU_CONTROL0_CONFIG_OPERATION_C2_LEN = 2 ;
+static const uint8_t P9N2__CTL_PMU_CONTROL0_CONFIG_OPERATION_C3 = 22 ;
+static const uint8_t P9N2__CTL_PMU_CONTROL0_CONFIG_OPERATION_C3_LEN = 2 ;
+static const uint8_t P9N2__CTL_PMU_CONTROL0_CONFIG_EVENTS_C0 = 24 ;
+static const uint8_t P9N2__CTL_PMU_CONTROL0_CONFIG_EVENTS_C0_LEN = 8 ;
+static const uint8_t P9N2__CTL_PMU_CONTROL0_CONFIG_EVENTS_C1 = 32 ;
+static const uint8_t P9N2__CTL_PMU_CONTROL0_CONFIG_EVENTS_C1_LEN = 8 ;
+static const uint8_t P9N2__CTL_PMU_CONTROL0_CONFIG_EVENTS_C2 = 40 ;
+static const uint8_t P9N2__CTL_PMU_CONTROL0_CONFIG_EVENTS_C2_LEN = 8 ;
+static const uint8_t P9N2__CTL_PMU_CONTROL0_CONFIG_EVENTS_C3 = 48 ;
+static const uint8_t P9N2__CTL_PMU_CONTROL0_CONFIG_EVENTS_C3_LEN = 8 ;
+static const uint8_t P9N2__CTL_PMU_CONTROL0_CONFIG_RESERVED0 = 56 ;
+static const uint8_t P9N2__CTL_PMU_CONTROL0_CONFIG_RESERVED0_LEN = 8 ;
+
+static const uint8_t P9N2__SM2_PMU_CONTROL0_CONFIG_ENABLE = 0 ;
+static const uint8_t P9N2__SM2_PMU_CONTROL0_CONFIG_RESETMODE = 1 ;
+static const uint8_t P9N2__SM2_PMU_CONTROL0_CONFIG_FREEZEMODE = 2 ;
+static const uint8_t P9N2__SM2_PMU_CONTROL0_CONFIG_DISABLE_PMISC = 3 ;
+static const uint8_t P9N2__SM2_PMU_CONTROL0_CONFIG_PMISC_MODE = 4 ;
+static const uint8_t P9N2__SM2_PMU_CONTROL0_CONFIG_CASCADE = 5 ;
+static const uint8_t P9N2__SM2_PMU_CONTROL0_CONFIG_CASCADE_LEN = 3 ;
+static const uint8_t P9N2__SM2_PMU_CONTROL0_CONFIG_PRESCALE_C0 = 8 ;
+static const uint8_t P9N2__SM2_PMU_CONTROL0_CONFIG_PRESCALE_C0_LEN = 2 ;
+static const uint8_t P9N2__SM2_PMU_CONTROL0_CONFIG_PRESCALE_C1 = 10 ;
+static const uint8_t P9N2__SM2_PMU_CONTROL0_CONFIG_PRESCALE_C1_LEN = 2 ;
+static const uint8_t P9N2__SM2_PMU_CONTROL0_CONFIG_PRESCALE_C2 = 12 ;
+static const uint8_t P9N2__SM2_PMU_CONTROL0_CONFIG_PRESCALE_C2_LEN = 2 ;
+static const uint8_t P9N2__SM2_PMU_CONTROL0_CONFIG_PRESCALE_C3 = 14 ;
+static const uint8_t P9N2__SM2_PMU_CONTROL0_CONFIG_PRESCALE_C3_LEN = 2 ;
+static const uint8_t P9N2__SM2_PMU_CONTROL0_CONFIG_OPERATION_C0 = 16 ;
+static const uint8_t P9N2__SM2_PMU_CONTROL0_CONFIG_OPERATION_C0_LEN = 2 ;
+static const uint8_t P9N2__SM2_PMU_CONTROL0_CONFIG_OPERATION_C1 = 18 ;
+static const uint8_t P9N2__SM2_PMU_CONTROL0_CONFIG_OPERATION_C1_LEN = 2 ;
+static const uint8_t P9N2__SM2_PMU_CONTROL0_CONFIG_OPERATION_C2 = 20 ;
+static const uint8_t P9N2__SM2_PMU_CONTROL0_CONFIG_OPERATION_C2_LEN = 2 ;
+static const uint8_t P9N2__SM2_PMU_CONTROL0_CONFIG_OPERATION_C3 = 22 ;
+static const uint8_t P9N2__SM2_PMU_CONTROL0_CONFIG_OPERATION_C3_LEN = 2 ;
+static const uint8_t P9N2__SM2_PMU_CONTROL0_CONFIG_EVENTS_C0 = 24 ;
+static const uint8_t P9N2__SM2_PMU_CONTROL0_CONFIG_EVENTS_C0_LEN = 8 ;
+static const uint8_t P9N2__SM2_PMU_CONTROL0_CONFIG_EVENTS_C1 = 32 ;
+static const uint8_t P9N2__SM2_PMU_CONTROL0_CONFIG_EVENTS_C1_LEN = 8 ;
+static const uint8_t P9N2__SM2_PMU_CONTROL0_CONFIG_EVENTS_C2 = 40 ;
+static const uint8_t P9N2__SM2_PMU_CONTROL0_CONFIG_EVENTS_C2_LEN = 8 ;
+static const uint8_t P9N2__SM2_PMU_CONTROL0_CONFIG_EVENTS_C3 = 48 ;
+static const uint8_t P9N2__SM2_PMU_CONTROL0_CONFIG_EVENTS_C3_LEN = 8 ;
+static const uint8_t P9N2__SM2_PMU_CONTROL0_CONFIG_RESERVED0 = 56 ;
+static const uint8_t P9N2__SM2_PMU_CONTROL0_CONFIG_RESERVED0_LEN = 8 ;
+
+static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL1_CONFIG_C01_OPCODEA = 0 ;
+static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL1_CONFIG_C01_OPCODEA_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL1_CONFIG_C01_OPCODEB = 8 ;
+static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL1_CONFIG_C01_OPCODEB_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL1_CONFIG_C23_OPCODEA = 16 ;
+static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL1_CONFIG_C23_OPCODEA_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL1_CONFIG_C23_OPCODEB = 24 ;
+static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL1_CONFIG_C23_OPCODEB_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL1_CONFIG_OPCODE_LATENCY = 32 ;
+static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL1_CONFIG_OPCODE_LATENCY_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL1_CONFIG_RESERVED1 = 40 ;
+static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL1_CONFIG_RESERVED1_LEN = 24 ;
+
+static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL1_CONFIG_C01_OPCODEA = 0 ;
+static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL1_CONFIG_C01_OPCODEA_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL1_CONFIG_C01_OPCODEB = 8 ;
+static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL1_CONFIG_C01_OPCODEB_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL1_CONFIG_C23_OPCODEA = 16 ;
+static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL1_CONFIG_C23_OPCODEA_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL1_CONFIG_C23_OPCODEB = 24 ;
+static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL1_CONFIG_C23_OPCODEB_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL1_CONFIG_OPCODE_LATENCY = 32 ;
+static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL1_CONFIG_OPCODE_LATENCY_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL1_CONFIG_RESERVED1 = 40 ;
+static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL1_CONFIG_RESERVED1_LEN = 24 ;
+
+static const uint8_t P9N2__CTL_PMU_CONTROL1_CONFIG_C01_OPCODEA = 0 ;
+static const uint8_t P9N2__CTL_PMU_CONTROL1_CONFIG_C01_OPCODEA_LEN = 8 ;
+static const uint8_t P9N2__CTL_PMU_CONTROL1_CONFIG_C01_OPCODEB = 8 ;
+static const uint8_t P9N2__CTL_PMU_CONTROL1_CONFIG_C01_OPCODEB_LEN = 8 ;
+static const uint8_t P9N2__CTL_PMU_CONTROL1_CONFIG_C23_OPCODEA = 16 ;
+static const uint8_t P9N2__CTL_PMU_CONTROL1_CONFIG_C23_OPCODEA_LEN = 8 ;
+static const uint8_t P9N2__CTL_PMU_CONTROL1_CONFIG_C23_OPCODEB = 24 ;
+static const uint8_t P9N2__CTL_PMU_CONTROL1_CONFIG_C23_OPCODEB_LEN = 8 ;
+static const uint8_t P9N2__CTL_PMU_CONTROL1_CONFIG_OPCODE_LATENCY = 32 ;
+static const uint8_t P9N2__CTL_PMU_CONTROL1_CONFIG_OPCODE_LATENCY_LEN = 8 ;
+static const uint8_t P9N2__CTL_PMU_CONTROL1_CONFIG_RESERVED1 = 40 ;
+static const uint8_t P9N2__CTL_PMU_CONTROL1_CONFIG_RESERVED1_LEN = 24 ;
+
+static const uint8_t P9N2__SM2_PMU_CONTROL1_CONFIG_C01_OPCODEA = 0 ;
+static const uint8_t P9N2__SM2_PMU_CONTROL1_CONFIG_C01_OPCODEA_LEN = 8 ;
+static const uint8_t P9N2__SM2_PMU_CONTROL1_CONFIG_C01_OPCODEB = 8 ;
+static const uint8_t P9N2__SM2_PMU_CONTROL1_CONFIG_C01_OPCODEB_LEN = 8 ;
+static const uint8_t P9N2__SM2_PMU_CONTROL1_CONFIG_C23_OPCODEA = 16 ;
+static const uint8_t P9N2__SM2_PMU_CONTROL1_CONFIG_C23_OPCODEA_LEN = 8 ;
+static const uint8_t P9N2__SM2_PMU_CONTROL1_CONFIG_C23_OPCODEB = 24 ;
+static const uint8_t P9N2__SM2_PMU_CONTROL1_CONFIG_C23_OPCODEB_LEN = 8 ;
+static const uint8_t P9N2__SM2_PMU_CONTROL1_CONFIG_OPCODE_LATENCY = 32 ;
+static const uint8_t P9N2__SM2_PMU_CONTROL1_CONFIG_OPCODE_LATENCY_LEN = 8 ;
+static const uint8_t P9N2__SM2_PMU_CONTROL1_CONFIG_RESERVED1 = 40 ;
+static const uint8_t P9N2__SM2_PMU_CONTROL1_CONFIG_RESERVED1_LEN = 24 ;
+
+static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL2_CONFIG_C01_DCMASKA = 0 ;
+static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL2_CONFIG_C01_DCMASKA_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL2_CONFIG_C01_DCMASKB = 8 ;
+static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL2_CONFIG_C01_DCMASKB_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL2_CONFIG_C23_DCMASKA = 16 ;
+static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL2_CONFIG_C23_DCMASKA_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL2_CONFIG_C23_DCMASKB = 24 ;
+static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL2_CONFIG_C23_DCMASKB_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL2_CONFIG_DCMASK_LATENCY = 32 ;
+static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL2_CONFIG_DCMASK_LATENCY_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL2_CONFIG_RESERVED2 = 40 ;
+static const uint8_t P9N2_PU_NPU_CTL_PMU_CONTROL2_CONFIG_RESERVED2_LEN = 24 ;
+
+static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL2_CONFIG_C01_DCMASKA = 0 ;
+static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL2_CONFIG_C01_DCMASKA_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL2_CONFIG_C01_DCMASKB = 8 ;
+static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL2_CONFIG_C01_DCMASKB_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL2_CONFIG_C23_DCMASKA = 16 ;
+static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL2_CONFIG_C23_DCMASKA_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL2_CONFIG_C23_DCMASKB = 24 ;
+static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL2_CONFIG_C23_DCMASKB_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL2_CONFIG_DCMASK_LATENCY = 32 ;
+static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL2_CONFIG_DCMASK_LATENCY_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL2_CONFIG_RESERVED2 = 40 ;
+static const uint8_t P9N2_PU_NPU_SM2_PMU_CONTROL2_CONFIG_RESERVED2_LEN = 24 ;
+
+static const uint8_t P9N2__CTL_PMU_CONTROL2_CONFIG_C01_DCMASKA = 0 ;
+static const uint8_t P9N2__CTL_PMU_CONTROL2_CONFIG_C01_DCMASKA_LEN = 8 ;
+static const uint8_t P9N2__CTL_PMU_CONTROL2_CONFIG_C01_DCMASKB = 8 ;
+static const uint8_t P9N2__CTL_PMU_CONTROL2_CONFIG_C01_DCMASKB_LEN = 8 ;
+static const uint8_t P9N2__CTL_PMU_CONTROL2_CONFIG_C23_DCMASKA = 16 ;
+static const uint8_t P9N2__CTL_PMU_CONTROL2_CONFIG_C23_DCMASKA_LEN = 8 ;
+static const uint8_t P9N2__CTL_PMU_CONTROL2_CONFIG_C23_DCMASKB = 24 ;
+static const uint8_t P9N2__CTL_PMU_CONTROL2_CONFIG_C23_DCMASKB_LEN = 8 ;
+static const uint8_t P9N2__CTL_PMU_CONTROL2_CONFIG_DCMASK_LATENCY = 32 ;
+static const uint8_t P9N2__CTL_PMU_CONTROL2_CONFIG_DCMASK_LATENCY_LEN = 8 ;
+static const uint8_t P9N2__CTL_PMU_CONTROL2_CONFIG_RESERVED2 = 40 ;
+static const uint8_t P9N2__CTL_PMU_CONTROL2_CONFIG_RESERVED2_LEN = 24 ;
+
+static const uint8_t P9N2__SM2_PMU_CONTROL2_CONFIG_C01_DCMASKA = 0 ;
+static const uint8_t P9N2__SM2_PMU_CONTROL2_CONFIG_C01_DCMASKA_LEN = 8 ;
+static const uint8_t P9N2__SM2_PMU_CONTROL2_CONFIG_C01_DCMASKB = 8 ;
+static const uint8_t P9N2__SM2_PMU_CONTROL2_CONFIG_C01_DCMASKB_LEN = 8 ;
+static const uint8_t P9N2__SM2_PMU_CONTROL2_CONFIG_C23_DCMASKA = 16 ;
+static const uint8_t P9N2__SM2_PMU_CONTROL2_CONFIG_C23_DCMASKA_LEN = 8 ;
+static const uint8_t P9N2__SM2_PMU_CONTROL2_CONFIG_C23_DCMASKB = 24 ;
+static const uint8_t P9N2__SM2_PMU_CONTROL2_CONFIG_C23_DCMASKB_LEN = 8 ;
+static const uint8_t P9N2__SM2_PMU_CONTROL2_CONFIG_DCMASK_LATENCY = 32 ;
+static const uint8_t P9N2__SM2_PMU_CONTROL2_CONFIG_DCMASK_LATENCY_LEN = 8 ;
+static const uint8_t P9N2__SM2_PMU_CONTROL2_CONFIG_RESERVED2 = 40 ;
+static const uint8_t P9N2__SM2_PMU_CONTROL2_CONFIG_RESERVED2_LEN = 24 ;
+
+static const uint8_t P9N2__NTL0_PMU_COUNT_CONFIG_COUNT0 = 0 ;
+static const uint8_t P9N2__NTL0_PMU_COUNT_CONFIG_COUNT0_LEN = 16 ;
+static const uint8_t P9N2__NTL0_PMU_COUNT_CONFIG_COUNT1 = 16 ;
+static const uint8_t P9N2__NTL0_PMU_COUNT_CONFIG_COUNT1_LEN = 16 ;
+static const uint8_t P9N2__NTL0_PMU_COUNT_CONFIG_COUNT2 = 32 ;
+static const uint8_t P9N2__NTL0_PMU_COUNT_CONFIG_COUNT2_LEN = 16 ;
+static const uint8_t P9N2__NTL0_PMU_COUNT_CONFIG_COUNT3 = 48 ;
+static const uint8_t P9N2__NTL0_PMU_COUNT_CONFIG_COUNT3_LEN = 16 ;
+
+static const uint8_t P9N2_PU_NPU_CTL_PMU_COUNT_CONFIG_COUNT0 = 0 ;
+static const uint8_t P9N2_PU_NPU_CTL_PMU_COUNT_CONFIG_COUNT0_LEN = 16 ;
+static const uint8_t P9N2_PU_NPU_CTL_PMU_COUNT_CONFIG_COUNT1 = 16 ;
+static const uint8_t P9N2_PU_NPU_CTL_PMU_COUNT_CONFIG_COUNT1_LEN = 16 ;
+static const uint8_t P9N2_PU_NPU_CTL_PMU_COUNT_CONFIG_COUNT2 = 32 ;
+static const uint8_t P9N2_PU_NPU_CTL_PMU_COUNT_CONFIG_COUNT2_LEN = 16 ;
+static const uint8_t P9N2_PU_NPU_CTL_PMU_COUNT_CONFIG_COUNT3 = 48 ;
+static const uint8_t P9N2_PU_NPU_CTL_PMU_COUNT_CONFIG_COUNT3_LEN = 16 ;
+
+static const uint8_t P9N2_PU_NPU_SM2_PMU_COUNT_CONFIG_COUNT0 = 0 ;
+static const uint8_t P9N2_PU_NPU_SM2_PMU_COUNT_CONFIG_COUNT0_LEN = 16 ;
+static const uint8_t P9N2_PU_NPU_SM2_PMU_COUNT_CONFIG_COUNT1 = 16 ;
+static const uint8_t P9N2_PU_NPU_SM2_PMU_COUNT_CONFIG_COUNT1_LEN = 16 ;
+static const uint8_t P9N2_PU_NPU_SM2_PMU_COUNT_CONFIG_COUNT2 = 32 ;
+static const uint8_t P9N2_PU_NPU_SM2_PMU_COUNT_CONFIG_COUNT2_LEN = 16 ;
+static const uint8_t P9N2_PU_NPU_SM2_PMU_COUNT_CONFIG_COUNT3 = 48 ;
+static const uint8_t P9N2_PU_NPU_SM2_PMU_COUNT_CONFIG_COUNT3_LEN = 16 ;
+
+static const uint8_t P9N2_PU_NPU_NTL0_PMU_COUNT_CONFIG_COUNT0 = 0 ;
+static const uint8_t P9N2_PU_NPU_NTL0_PMU_COUNT_CONFIG_COUNT0_LEN = 16 ;
+static const uint8_t P9N2_PU_NPU_NTL0_PMU_COUNT_CONFIG_COUNT1 = 16 ;
+static const uint8_t P9N2_PU_NPU_NTL0_PMU_COUNT_CONFIG_COUNT1_LEN = 16 ;
+static const uint8_t P9N2_PU_NPU_NTL0_PMU_COUNT_CONFIG_COUNT2 = 32 ;
+static const uint8_t P9N2_PU_NPU_NTL0_PMU_COUNT_CONFIG_COUNT2_LEN = 16 ;
+static const uint8_t P9N2_PU_NPU_NTL0_PMU_COUNT_CONFIG_COUNT3 = 48 ;
+static const uint8_t P9N2_PU_NPU_NTL0_PMU_COUNT_CONFIG_COUNT3_LEN = 16 ;
+
+static const uint8_t P9N2__CTL_PMU_COUNT_CONFIG_COUNT0 = 0 ;
+static const uint8_t P9N2__CTL_PMU_COUNT_CONFIG_COUNT0_LEN = 16 ;
+static const uint8_t P9N2__CTL_PMU_COUNT_CONFIG_COUNT1 = 16 ;
+static const uint8_t P9N2__CTL_PMU_COUNT_CONFIG_COUNT1_LEN = 16 ;
+static const uint8_t P9N2__CTL_PMU_COUNT_CONFIG_COUNT2 = 32 ;
+static const uint8_t P9N2__CTL_PMU_COUNT_CONFIG_COUNT2_LEN = 16 ;
+static const uint8_t P9N2__CTL_PMU_COUNT_CONFIG_COUNT3 = 48 ;
+static const uint8_t P9N2__CTL_PMU_COUNT_CONFIG_COUNT3_LEN = 16 ;
+
+static const uint8_t P9N2__SM2_PMU_COUNT_CONFIG_COUNT0 = 0 ;
+static const uint8_t P9N2__SM2_PMU_COUNT_CONFIG_COUNT0_LEN = 16 ;
+static const uint8_t P9N2__SM2_PMU_COUNT_CONFIG_COUNT1 = 16 ;
+static const uint8_t P9N2__SM2_PMU_COUNT_CONFIG_COUNT1_LEN = 16 ;
+static const uint8_t P9N2__SM2_PMU_COUNT_CONFIG_COUNT2 = 32 ;
+static const uint8_t P9N2__SM2_PMU_COUNT_CONFIG_COUNT2_LEN = 16 ;
+static const uint8_t P9N2__SM2_PMU_COUNT_CONFIG_COUNT3 = 48 ;
+static const uint8_t P9N2__SM2_PMU_COUNT_CONFIG_COUNT3_LEN = 16 ;
+
+static const uint8_t P9N2_PU_PPE_FIR_ACTION0_REG_ACTION0 = 0 ;
+static const uint8_t P9N2_PU_PPE_FIR_ACTION0_REG_ACTION0_LEN = 13 ;
+
+static const uint8_t P9N2_PU_PPE_FIR_ACTION1_REG_ACTION1 = 0 ;
+static const uint8_t P9N2_PU_PPE_FIR_ACTION1_REG_ACTION1_LEN = 13 ;
+
+static const uint8_t P9N2_PU_PPE_FIR_MASK_REG_ERROR = 0 ;
+static const uint8_t P9N2_PU_PPE_FIR_MASK_REG_ERROR_LEN = 4 ;
+static const uint8_t P9N2_PU_PPE_FIR_MASK_REG_HALTED = 4 ;
+static const uint8_t P9N2_PU_PPE_FIR_MASK_REG_WATCHDOG_TIMEOUT = 5 ;
+static const uint8_t P9N2_PU_PPE_FIR_MASK_REG_MMIO_DATA_IN = 6 ;
+static const uint8_t P9N2_PU_PPE_FIR_MASK_REG_ARB_MISSED_SCRUB_TICK = 7 ;
+static const uint8_t P9N2_PU_PPE_FIR_MASK_REG_ARB_ARY_UE = 8 ;
+static const uint8_t P9N2_PU_PPE_FIR_MASK_REG_ARB_ARY_CE = 9 ;
+static const uint8_t P9N2_PU_PPE_FIR_MASK_REG_RESERVED = 10 ;
+static const uint8_t P9N2_PU_PPE_FIR_MASK_REG_INTERNAL_SCOM_ERROR = 11 ;
+static const uint8_t P9N2_PU_PPE_FIR_MASK_REG_INTERNAL_SCOM_ERROR_CLONE = 12 ;
+
+static const uint8_t P9N2_PU_PPE_FIR_REG_ERROR = 0 ;
+static const uint8_t P9N2_PU_PPE_FIR_REG_ERROR_LEN = 4 ;
+static const uint8_t P9N2_PU_PPE_FIR_REG_HALTED = 4 ;
+static const uint8_t P9N2_PU_PPE_FIR_REG_WATCHDOG_TIMEOUT = 5 ;
+static const uint8_t P9N2_PU_PPE_FIR_REG_MMIO_DATA_IN = 6 ;
+static const uint8_t P9N2_PU_PPE_FIR_REG_ARB_MISSED_SCRUB_TICK = 7 ;
+static const uint8_t P9N2_PU_PPE_FIR_REG_ARB_ARY_UE = 8 ;
+static const uint8_t P9N2_PU_PPE_FIR_REG_ARB_ARY_CE = 9 ;
+static const uint8_t P9N2_PU_PPE_FIR_REG_RESERVED = 10 ;
+static const uint8_t P9N2_PU_PPE_FIR_REG_SCOMFIR_ERROR = 11 ;
+static const uint8_t P9N2_PU_PPE_FIR_REG_SCOMFIR_ERROR_CLONE = 12 ;
+
+static const uint8_t P9N2_PU_PPE_FIR_WOF_REG_WOF = 0 ;
+static const uint8_t P9N2_PU_PPE_FIR_WOF_REG_WOF_LEN = 13 ;
+
+static const uint8_t P9N2_PU_PPE_XIDBGPRO_XSR_HS = 0 ;
+static const uint8_t P9N2_PU_PPE_XIDBGPRO_XSR_HC = 1 ;
+static const uint8_t P9N2_PU_PPE_XIDBGPRO_XSR_HC_LEN = 3 ;
+static const uint8_t P9N2_PU_PPE_XIDBGPRO_XSR_HCP = 4 ;
+static const uint8_t P9N2_PU_PPE_XIDBGPRO_XSR_RIP = 5 ;
+static const uint8_t P9N2_PU_PPE_XIDBGPRO_XSR_SIP = 6 ;
+static const uint8_t P9N2_PU_PPE_XIDBGPRO_XSR_TRAP = 7 ;
+static const uint8_t P9N2_PU_PPE_XIDBGPRO_XSR_IAC = 8 ;
+static const uint8_t P9N2_PU_PPE_XIDBGPRO_NULL_MSR_SIBRC = 9 ;
+static const uint8_t P9N2_PU_PPE_XIDBGPRO_NULL_MSR_SIBRC_LEN = 3 ;
+static const uint8_t P9N2_PU_PPE_XIDBGPRO_XSR_DACR = 12 ;
+static const uint8_t P9N2_PU_PPE_XIDBGPRO_XSR_DACW = 13 ;
+static const uint8_t P9N2_PU_PPE_XIDBGPRO_NULL_MSR_WE = 14 ;
+static const uint8_t P9N2_PU_PPE_XIDBGPRO_XSR_TRH = 15 ;
+static const uint8_t P9N2_PU_PPE_XIDBGPRO_XSR_SMS = 16 ;
+static const uint8_t P9N2_PU_PPE_XIDBGPRO_XSR_SMS_LEN = 4 ;
+static const uint8_t P9N2_PU_PPE_XIDBGPRO_NULL_MSR_LP = 20 ;
+static const uint8_t P9N2_PU_PPE_XIDBGPRO_XSR_EP = 21 ;
+static const uint8_t P9N2_PU_PPE_XIDBGPRO_XSR_PTR = 24 ;
+static const uint8_t P9N2_PU_PPE_XIDBGPRO_XSR_ST = 25 ;
+static const uint8_t P9N2_PU_PPE_XIDBGPRO_XSR_MFE = 28 ;
+static const uint8_t P9N2_PU_PPE_XIDBGPRO_XSR_MCS = 29 ;
+static const uint8_t P9N2_PU_PPE_XIDBGPRO_XSR_MCS_LEN = 3 ;
+static const uint8_t P9N2_PU_PPE_XIDBGPRO_IAR = 32 ;
+static const uint8_t P9N2_PU_PPE_XIDBGPRO_IAR_LEN = 30 ;
+
+static const uint8_t P9N2_PU_PPE_XIRAMDBG_XSR_HS = 0 ;
+static const uint8_t P9N2_PU_PPE_XIRAMDBG_XSR_HC = 1 ;
+static const uint8_t P9N2_PU_PPE_XIRAMDBG_XSR_HC_LEN = 3 ;
+static const uint8_t P9N2_PU_PPE_XIRAMDBG_XSR_HCP = 4 ;
+static const uint8_t P9N2_PU_PPE_XIRAMDBG_XSR_RIP = 5 ;
+static const uint8_t P9N2_PU_PPE_XIRAMDBG_XSR_SIP = 6 ;
+static const uint8_t P9N2_PU_PPE_XIRAMDBG_XSR_TRAP = 7 ;
+static const uint8_t P9N2_PU_PPE_XIRAMDBG_XSR_IAC = 8 ;
+static const uint8_t P9N2_PU_PPE_XIRAMDBG_NULL_MSR_SIBRC = 9 ;
+static const uint8_t P9N2_PU_PPE_XIRAMDBG_NULL_MSR_SIBRC_LEN = 3 ;
+static const uint8_t P9N2_PU_PPE_XIRAMDBG_XSR_DACR = 12 ;
+static const uint8_t P9N2_PU_PPE_XIRAMDBG_XSR_DACW = 13 ;
+static const uint8_t P9N2_PU_PPE_XIRAMDBG_NULL_MSR_WE = 14 ;
+static const uint8_t P9N2_PU_PPE_XIRAMDBG_XSR_TRH = 15 ;
+static const uint8_t P9N2_PU_PPE_XIRAMDBG_XSR_SMS = 16 ;
+static const uint8_t P9N2_PU_PPE_XIRAMDBG_XSR_SMS_LEN = 4 ;
+static const uint8_t P9N2_PU_PPE_XIRAMDBG_NULL_MSR_LP = 20 ;
+static const uint8_t P9N2_PU_PPE_XIRAMDBG_XSR_EP = 21 ;
+static const uint8_t P9N2_PU_PPE_XIRAMDBG_XSR_PTR = 24 ;
+static const uint8_t P9N2_PU_PPE_XIRAMDBG_XSR_ST = 25 ;
+static const uint8_t P9N2_PU_PPE_XIRAMDBG_XSR_MFE = 28 ;
+static const uint8_t P9N2_PU_PPE_XIRAMDBG_XSR_MCS = 29 ;
+static const uint8_t P9N2_PU_PPE_XIRAMDBG_XSR_MCS_LEN = 3 ;
+static const uint8_t P9N2_PU_PPE_XIRAMDBG_XIRAMRA_SPRG0 = 32 ;
+static const uint8_t P9N2_PU_PPE_XIRAMDBG_XIRAMRA_SPRG0_LEN = 32 ;
+
+static const uint8_t P9N2_PU_PPE_XIRAMEDR_XIRAMGA_IR = 0 ;
+static const uint8_t P9N2_PU_PPE_XIRAMEDR_XIRAMGA_IR_LEN = 32 ;
+static const uint8_t P9N2_PU_PPE_XIRAMEDR_EDR = 32 ;
+static const uint8_t P9N2_PU_PPE_XIRAMEDR_EDR_LEN = 32 ;
+
+static const uint8_t P9N2_PU_PPE_XIRAMGA_IR = 0 ;
+static const uint8_t P9N2_PU_PPE_XIRAMGA_IR_LEN = 32 ;
+static const uint8_t P9N2_PU_PPE_XIRAMGA_XIRAMRA_SPRG0 = 32 ;
+static const uint8_t P9N2_PU_PPE_XIRAMGA_XIRAMRA_SPRG0_LEN = 32 ;
+
+static const uint8_t P9N2_PU_PPE_XIRAMRA_XIXCR_XCR = 1 ;
+static const uint8_t P9N2_PU_PPE_XIRAMRA_XIXCR_XCR_LEN = 3 ;
+static const uint8_t P9N2_PU_PPE_XIRAMRA_SPRG0 = 32 ;
+static const uint8_t P9N2_PU_PPE_XIRAMRA_SPRG0_LEN = 32 ;
+
+static const uint8_t P9N2_PU_PPE_XIXCR_XCR = 1 ;
+static const uint8_t P9N2_PU_PPE_XIXCR_XCR_LEN = 3 ;
+
+static const uint8_t P9N2_PU_NPU1_SM1_PRB_HA_PTR_RESERVED1 = 0 ;
+static const uint8_t P9N2_PU_NPU1_SM1_PRB_HA_PTR_RESERVED1_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM1_PRB_HA_PTR_START = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM1_PRB_HA_PTR_START_LEN = 7 ;
+static const uint8_t P9N2_PU_NPU1_SM1_PRB_HA_PTR_RESERVED2 = 12 ;
+static const uint8_t P9N2_PU_NPU1_SM1_PRB_HA_PTR_RESERVED2_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM1_PRB_HA_PTR_END = 17 ;
+static const uint8_t P9N2_PU_NPU1_SM1_PRB_HA_PTR_END_LEN = 7 ;
+
+static const uint8_t P9N2_PU_NPU_SM2_PRB_HA_PTR_RESERVED1 = 0 ;
+static const uint8_t P9N2_PU_NPU_SM2_PRB_HA_PTR_RESERVED1_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM2_PRB_HA_PTR_START = 5 ;
+static const uint8_t P9N2_PU_NPU_SM2_PRB_HA_PTR_START_LEN = 7 ;
+static const uint8_t P9N2_PU_NPU_SM2_PRB_HA_PTR_RESERVED2 = 12 ;
+static const uint8_t P9N2_PU_NPU_SM2_PRB_HA_PTR_RESERVED2_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM2_PRB_HA_PTR_END = 17 ;
+static const uint8_t P9N2_PU_NPU_SM2_PRB_HA_PTR_END_LEN = 7 ;
+
+static const uint8_t P9N2_PU_NPU1_SM2_PRB_HA_PTR_RESERVED1 = 0 ;
+static const uint8_t P9N2_PU_NPU1_SM2_PRB_HA_PTR_RESERVED1_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM2_PRB_HA_PTR_START = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM2_PRB_HA_PTR_START_LEN = 7 ;
+static const uint8_t P9N2_PU_NPU1_SM2_PRB_HA_PTR_RESERVED2 = 12 ;
+static const uint8_t P9N2_PU_NPU1_SM2_PRB_HA_PTR_RESERVED2_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM2_PRB_HA_PTR_END = 17 ;
+static const uint8_t P9N2_PU_NPU1_SM2_PRB_HA_PTR_END_LEN = 7 ;
+
+static const uint8_t P9N2_PU_NPU_SM1_PRB_HA_PTR_RESERVED1 = 0 ;
+static const uint8_t P9N2_PU_NPU_SM1_PRB_HA_PTR_RESERVED1_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM1_PRB_HA_PTR_START = 5 ;
+static const uint8_t P9N2_PU_NPU_SM1_PRB_HA_PTR_START_LEN = 7 ;
+static const uint8_t P9N2_PU_NPU_SM1_PRB_HA_PTR_RESERVED2 = 12 ;
+static const uint8_t P9N2_PU_NPU_SM1_PRB_HA_PTR_RESERVED2_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM1_PRB_HA_PTR_END = 17 ;
+static const uint8_t P9N2_PU_NPU_SM1_PRB_HA_PTR_END_LEN = 7 ;
+
+static const uint8_t P9N2__SM2_PRB_HA_PTR_RESERVED1 = 0 ;
+static const uint8_t P9N2__SM2_PRB_HA_PTR_RESERVED1_LEN = 5 ;
+static const uint8_t P9N2__SM2_PRB_HA_PTR_START = 5 ;
+static const uint8_t P9N2__SM2_PRB_HA_PTR_START_LEN = 7 ;
+static const uint8_t P9N2__SM2_PRB_HA_PTR_RESERVED2 = 12 ;
+static const uint8_t P9N2__SM2_PRB_HA_PTR_RESERVED2_LEN = 5 ;
+static const uint8_t P9N2__SM2_PRB_HA_PTR_END = 17 ;
+static const uint8_t P9N2__SM2_PRB_HA_PTR_END_LEN = 7 ;
+
+static const uint8_t P9N2__SM1_PRB_HA_PTR_RESERVED1 = 0 ;
+static const uint8_t P9N2__SM1_PRB_HA_PTR_RESERVED1_LEN = 5 ;
+static const uint8_t P9N2__SM1_PRB_HA_PTR_START = 5 ;
+static const uint8_t P9N2__SM1_PRB_HA_PTR_START_LEN = 7 ;
+static const uint8_t P9N2__SM1_PRB_HA_PTR_RESERVED2 = 12 ;
+static const uint8_t P9N2__SM1_PRB_HA_PTR_RESERVED2_LEN = 5 ;
+static const uint8_t P9N2__SM1_PRB_HA_PTR_END = 17 ;
+static const uint8_t P9N2__SM1_PRB_HA_PTR_END_LEN = 7 ;
+
+static const uint8_t P9N2_PEC_PRDSTKOVR_REG_STK0 = 0 ;
+static const uint8_t P9N2_PEC_PRDSTKOVR_REG_STK0_LEN = 32 ;
+static const uint8_t P9N2_PEC_PRDSTKOVR_REG_STK1 = 32 ;
+static const uint8_t P9N2_PEC_PRDSTKOVR_REG_STK1_LEN = 16 ;
+static const uint8_t P9N2_PEC_PRDSTKOVR_REG_ENABLE = 48 ;
+
+static const uint8_t P9N2_PEC_PREDV_REG_PE_RD_TIMEOUT_MASK = 0 ;
+static const uint8_t P9N2_PEC_PREDV_REG_PE_RD_TIMEOUT_MASK_LEN = 8 ;
+static const uint8_t P9N2_PEC_PREDV_REG_PE_WR_TIMEOUT_MASK = 8 ;
+static const uint8_t P9N2_PEC_PREDV_REG_PE_WR_TIMEOUT_MASK_LEN = 8 ;
+
+static const uint8_t P9N2_PEC_PRE_COUNTER_REG_COUNTER = 0 ;
+static const uint8_t P9N2_PEC_PRE_COUNTER_REG_COUNTER_LEN = 8 ;
+
+static const uint8_t P9N2_PU_PRGM_REGISTER_PRGM_ADDR = 0 ;
+static const uint8_t P9N2_PU_PRGM_REGISTER_PRGM_ADDR_LEN = 32 ;
+static const uint8_t P9N2_PU_PRGM_REGISTER_PRG_BIT_LOCATION = 32 ;
+static const uint8_t P9N2_PU_PRGM_REGISTER_PRG_BIT_LOCATION_LEN = 6 ;
+
+static const uint8_t P9N2_PEC_PRIMARY_ADDRESS_REG_PRIMARY_ADDRESS = 0 ;
+static const uint8_t P9N2_PEC_PRIMARY_ADDRESS_REG_PRIMARY_ADDRESS_LEN = 6 ;
+
+static const uint8_t P9N2_PU_NPU1_SM1_PRI_CONFIG_NDL = 0 ;
+static const uint8_t P9N2_PU_NPU1_SM1_PRI_CONFIG_NDL_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU1_SM1_PRI_CONFIG_PHY = 2 ;
+static const uint8_t P9N2_PU_NPU1_SM1_PRI_CONFIG_PHY_LEN = 2 ;
+
+static const uint8_t P9N2_PU_NPU_SM2_PRI_CONFIG_NDL = 0 ;
+static const uint8_t P9N2_PU_NPU_SM2_PRI_CONFIG_NDL_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_SM2_PRI_CONFIG_PHY = 2 ;
+static const uint8_t P9N2_PU_NPU_SM2_PRI_CONFIG_PHY_LEN = 2 ;
+
+static const uint8_t P9N2_PU_NPU1_SM2_PRI_CONFIG_NDL = 0 ;
+static const uint8_t P9N2_PU_NPU1_SM2_PRI_CONFIG_NDL_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU1_SM2_PRI_CONFIG_PHY = 2 ;
+static const uint8_t P9N2_PU_NPU1_SM2_PRI_CONFIG_PHY_LEN = 2 ;
+
+static const uint8_t P9N2_PU_NPU_SM1_PRI_CONFIG_NDL = 0 ;
+static const uint8_t P9N2_PU_NPU_SM1_PRI_CONFIG_NDL_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_SM1_PRI_CONFIG_PHY = 2 ;
+static const uint8_t P9N2_PU_NPU_SM1_PRI_CONFIG_PHY_LEN = 2 ;
+
+static const uint8_t P9N2__SM2_PRI_CONFIG_NDL = 0 ;
+static const uint8_t P9N2__SM2_PRI_CONFIG_NDL_LEN = 2 ;
+static const uint8_t P9N2__SM2_PRI_CONFIG_PHY = 2 ;
+static const uint8_t P9N2__SM2_PRI_CONFIG_PHY_LEN = 2 ;
+
+static const uint8_t P9N2__SM1_PRI_CONFIG_NDL = 0 ;
+static const uint8_t P9N2__SM1_PRI_CONFIG_NDL_LEN = 2 ;
+static const uint8_t P9N2__SM1_PRI_CONFIG_PHY = 2 ;
+static const uint8_t P9N2__SM1_PRI_CONFIG_PHY_LEN = 2 ;
+
+static const uint8_t P9N2_PU_PROBE_PROTECT_STATUS_BITS = 0 ;
+static const uint8_t P9N2_PU_PROBE_PROTECT_STATUS_BITS_LEN = 42 ;
+
+static const uint8_t P9N2_PEC_PROTECT_MODE_REG_READ_ENABLE = 0 ;
+static const uint8_t P9N2_PEC_PROTECT_MODE_REG_WRITE_ENABLE = 1 ;
+
+static const uint8_t P9N2_PU_PRV_MISC_TPSBE_TPBR_SBE_INTR = 0 ;
+static const uint8_t P9N2_PU_PRV_MISC_CHKSW_AR012 = 1 ;
+static const uint8_t P9N2_PU_PRV_MISC_RESERVED_18 = 2 ;
+static const uint8_t P9N2_PU_PRV_MISC_RESERVED_18_LEN = 2 ;
+static const uint8_t P9N2_PU_PRV_MISC_SBE_EXTERNAL_FIRS = 4 ;
+static const uint8_t P9N2_PU_PRV_MISC_SBE_EXTERNAL_FIRS_LEN = 4 ;
+static const uint8_t P9N2_PU_PRV_MISC_RESERVED_17 = 8 ;
+static const uint8_t P9N2_PU_PRV_MISC_RESERVED_17_LEN = 4 ;
+static const uint8_t P9N2_PU_PRV_MISC_TPSBE_TPIO_TPM_RESET = 12 ;
+static const uint8_t P9N2_PU_PRV_MISC_TPSBE_TPOCC_HALT_COMPLEX = 13 ;
+static const uint8_t P9N2_PU_PRV_MISC_RESERVED_16 = 14 ;
+static const uint8_t P9N2_PU_PRV_MISC_RESERVED_16_LEN = 2 ;
+static const uint8_t P9N2_PU_PRV_MISC_I2C_TIMEOUT_VALUE = 16 ;
+static const uint8_t P9N2_PU_PRV_MISC_I2C_TIMEOUT_VALUE_LEN = 32 ;
+
+static const uint8_t P9N2_PU_N3_PSCOM_ERROR_MASK_PCB_WDATA_PARITY = 0 ;
+static const uint8_t P9N2_PU_N3_PSCOM_ERROR_MASK_PCB_ADDRESS_PARITY = 1 ;
+static const uint8_t P9N2_PU_N3_PSCOM_ERROR_MASK_DL_RETURN_WDATA_PARITY = 2 ;
+static const uint8_t P9N2_PU_N3_PSCOM_ERROR_MASK_DL_RETURN_P0 = 3 ;
+static const uint8_t P9N2_PU_N3_PSCOM_ERROR_MASK_UL_RDATA_PARITY = 4 ;
+static const uint8_t P9N2_PU_N3_PSCOM_ERROR_MASK_UL_P0 = 5 ;
+static const uint8_t P9N2_PU_N3_PSCOM_ERROR_MASK_PARITY_ON_INTERFACE_MACHINE = 6 ;
+static const uint8_t P9N2_PU_N3_PSCOM_ERROR_MASK_PARITY_ON_P2S_MACHINE = 7 ;
+static const uint8_t P9N2_PU_N3_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 8 ;
+static const uint8_t P9N2_PU_N3_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 9 ;
+static const uint8_t P9N2_PU_N3_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 10 ;
+static const uint8_t P9N2_PU_N3_PSCOM_ERROR_MASK_PARALLEL_WRITE_NVLD = 11 ;
+static const uint8_t P9N2_PU_N3_PSCOM_ERROR_MASK_PARALLEL_READ_NVLD = 12 ;
+static const uint8_t P9N2_PU_N3_PSCOM_ERROR_MASK_PARALLEL_ADDR_INVALID = 13 ;
+static const uint8_t P9N2_PU_N3_PSCOM_ERROR_MASK_PCB_COMMAND_PARITY = 14 ;
+static const uint8_t P9N2_PU_N3_PSCOM_ERROR_MASK_GENERAL_TIMEOUT = 15 ;
+static const uint8_t P9N2_PU_N3_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 16 ;
+static const uint8_t P9N2_PU_N3_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 17 ;
+
+static const uint8_t P9N2_PU_N1_PSCOM_ERROR_MASK_PCB_WDATA_PARITY = 0 ;
+static const uint8_t P9N2_PU_N1_PSCOM_ERROR_MASK_PCB_ADDRESS_PARITY = 1 ;
+static const uint8_t P9N2_PU_N1_PSCOM_ERROR_MASK_DL_RETURN_WDATA_PARITY = 2 ;
+static const uint8_t P9N2_PU_N1_PSCOM_ERROR_MASK_DL_RETURN_P0 = 3 ;
+static const uint8_t P9N2_PU_N1_PSCOM_ERROR_MASK_UL_RDATA_PARITY = 4 ;
+static const uint8_t P9N2_PU_N1_PSCOM_ERROR_MASK_UL_P0 = 5 ;
+static const uint8_t P9N2_PU_N1_PSCOM_ERROR_MASK_PARITY_ON_INTERFACE_MACHINE = 6 ;
+static const uint8_t P9N2_PU_N1_PSCOM_ERROR_MASK_PARITY_ON_P2S_MACHINE = 7 ;
+static const uint8_t P9N2_PU_N1_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 8 ;
+static const uint8_t P9N2_PU_N1_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 9 ;
+static const uint8_t P9N2_PU_N1_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 10 ;
+static const uint8_t P9N2_PU_N1_PSCOM_ERROR_MASK_PARALLEL_WRITE_NVLD = 11 ;
+static const uint8_t P9N2_PU_N1_PSCOM_ERROR_MASK_PARALLEL_READ_NVLD = 12 ;
+static const uint8_t P9N2_PU_N1_PSCOM_ERROR_MASK_PARALLEL_ADDR_INVALID = 13 ;
+static const uint8_t P9N2_PU_N1_PSCOM_ERROR_MASK_PCB_COMMAND_PARITY = 14 ;
+static const uint8_t P9N2_PU_N1_PSCOM_ERROR_MASK_GENERAL_TIMEOUT = 15 ;
+static const uint8_t P9N2_PU_N1_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 16 ;
+static const uint8_t P9N2_PU_N1_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 17 ;
+
+static const uint8_t P9N2_PU_PSCOM_ERROR_MASK_PCB_WDATA_PARITY = 0 ;
+static const uint8_t P9N2_PU_PSCOM_ERROR_MASK_PCB_ADDRESS_PARITY = 1 ;
+static const uint8_t P9N2_PU_PSCOM_ERROR_MASK_DL_RETURN_WDATA_PARITY = 2 ;
+static const uint8_t P9N2_PU_PSCOM_ERROR_MASK_DL_RETURN_P0 = 3 ;
+static const uint8_t P9N2_PU_PSCOM_ERROR_MASK_UL_RDATA_PARITY = 4 ;
+static const uint8_t P9N2_PU_PSCOM_ERROR_MASK_UL_P0 = 5 ;
+static const uint8_t P9N2_PU_PSCOM_ERROR_MASK_PARITY_ON_INTERFACE_MACHINE = 6 ;
+static const uint8_t P9N2_PU_PSCOM_ERROR_MASK_PARITY_ON_P2S_MACHINE = 7 ;
+static const uint8_t P9N2_PU_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 8 ;
+static const uint8_t P9N2_PU_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 9 ;
+static const uint8_t P9N2_PU_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 10 ;
+static const uint8_t P9N2_PU_PSCOM_ERROR_MASK_PARALLEL_WRITE_NVLD = 11 ;
+static const uint8_t P9N2_PU_PSCOM_ERROR_MASK_PARALLEL_READ_NVLD = 12 ;
+static const uint8_t P9N2_PU_PSCOM_ERROR_MASK_PARALLEL_ADDR_INVALID = 13 ;
+static const uint8_t P9N2_PU_PSCOM_ERROR_MASK_PCB_COMMAND_PARITY = 14 ;
+static const uint8_t P9N2_PU_PSCOM_ERROR_MASK_GENERAL_TIMEOUT = 15 ;
+static const uint8_t P9N2_PU_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 16 ;
+static const uint8_t P9N2_PU_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 17 ;
+
+static const uint8_t P9N2_PU_N2_PSCOM_ERROR_MASK_PCB_WDATA_PARITY = 0 ;
+static const uint8_t P9N2_PU_N2_PSCOM_ERROR_MASK_PCB_ADDRESS_PARITY = 1 ;
+static const uint8_t P9N2_PU_N2_PSCOM_ERROR_MASK_DL_RETURN_WDATA_PARITY = 2 ;
+static const uint8_t P9N2_PU_N2_PSCOM_ERROR_MASK_DL_RETURN_P0 = 3 ;
+static const uint8_t P9N2_PU_N2_PSCOM_ERROR_MASK_UL_RDATA_PARITY = 4 ;
+static const uint8_t P9N2_PU_N2_PSCOM_ERROR_MASK_UL_P0 = 5 ;
+static const uint8_t P9N2_PU_N2_PSCOM_ERROR_MASK_PARITY_ON_INTERFACE_MACHINE = 6 ;
+static const uint8_t P9N2_PU_N2_PSCOM_ERROR_MASK_PARITY_ON_P2S_MACHINE = 7 ;
+static const uint8_t P9N2_PU_N2_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 8 ;
+static const uint8_t P9N2_PU_N2_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 9 ;
+static const uint8_t P9N2_PU_N2_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 10 ;
+static const uint8_t P9N2_PU_N2_PSCOM_ERROR_MASK_PARALLEL_WRITE_NVLD = 11 ;
+static const uint8_t P9N2_PU_N2_PSCOM_ERROR_MASK_PARALLEL_READ_NVLD = 12 ;
+static const uint8_t P9N2_PU_N2_PSCOM_ERROR_MASK_PARALLEL_ADDR_INVALID = 13 ;
+static const uint8_t P9N2_PU_N2_PSCOM_ERROR_MASK_PCB_COMMAND_PARITY = 14 ;
+static const uint8_t P9N2_PU_N2_PSCOM_ERROR_MASK_GENERAL_TIMEOUT = 15 ;
+static const uint8_t P9N2_PU_N2_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 16 ;
+static const uint8_t P9N2_PU_N2_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 17 ;
+
+static const uint8_t P9N2_PEC_PSCOM_ERROR_MASK_PCB_WDATA_PARITY = 0 ;
+static const uint8_t P9N2_PEC_PSCOM_ERROR_MASK_PCB_ADDRESS_PARITY = 1 ;
+static const uint8_t P9N2_PEC_PSCOM_ERROR_MASK_DL_RETURN_WDATA_PARITY = 2 ;
+static const uint8_t P9N2_PEC_PSCOM_ERROR_MASK_DL_RETURN_P0 = 3 ;
+static const uint8_t P9N2_PEC_PSCOM_ERROR_MASK_UL_RDATA_PARITY = 4 ;
+static const uint8_t P9N2_PEC_PSCOM_ERROR_MASK_UL_P0 = 5 ;
+static const uint8_t P9N2_PEC_PSCOM_ERROR_MASK_PARITY_ON_INTERFACE_MACHINE = 6 ;
+static const uint8_t P9N2_PEC_PSCOM_ERROR_MASK_PARITY_ON_P2S_MACHINE = 7 ;
+static const uint8_t P9N2_PEC_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 8 ;
+static const uint8_t P9N2_PEC_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 9 ;
+static const uint8_t P9N2_PEC_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 10 ;
+static const uint8_t P9N2_PEC_PSCOM_ERROR_MASK_PARALLEL_WRITE_NVLD = 11 ;
+static const uint8_t P9N2_PEC_PSCOM_ERROR_MASK_PARALLEL_READ_NVLD = 12 ;
+static const uint8_t P9N2_PEC_PSCOM_ERROR_MASK_PARALLEL_ADDR_INVALID = 13 ;
+static const uint8_t P9N2_PEC_PSCOM_ERROR_MASK_PCB_COMMAND_PARITY = 14 ;
+static const uint8_t P9N2_PEC_PSCOM_ERROR_MASK_GENERAL_TIMEOUT = 15 ;
+static const uint8_t P9N2_PEC_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 16 ;
+static const uint8_t P9N2_PEC_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 17 ;
+
+static const uint8_t P9N2_PU_N0_PSCOM_ERROR_MASK_PCB_WDATA_PARITY = 0 ;
+static const uint8_t P9N2_PU_N0_PSCOM_ERROR_MASK_PCB_ADDRESS_PARITY = 1 ;
+static const uint8_t P9N2_PU_N0_PSCOM_ERROR_MASK_DL_RETURN_WDATA_PARITY = 2 ;
+static const uint8_t P9N2_PU_N0_PSCOM_ERROR_MASK_DL_RETURN_P0 = 3 ;
+static const uint8_t P9N2_PU_N0_PSCOM_ERROR_MASK_UL_RDATA_PARITY = 4 ;
+static const uint8_t P9N2_PU_N0_PSCOM_ERROR_MASK_UL_P0 = 5 ;
+static const uint8_t P9N2_PU_N0_PSCOM_ERROR_MASK_PARITY_ON_INTERFACE_MACHINE = 6 ;
+static const uint8_t P9N2_PU_N0_PSCOM_ERROR_MASK_PARITY_ON_P2S_MACHINE = 7 ;
+static const uint8_t P9N2_PU_N0_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 8 ;
+static const uint8_t P9N2_PU_N0_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 9 ;
+static const uint8_t P9N2_PU_N0_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 10 ;
+static const uint8_t P9N2_PU_N0_PSCOM_ERROR_MASK_PARALLEL_WRITE_NVLD = 11 ;
+static const uint8_t P9N2_PU_N0_PSCOM_ERROR_MASK_PARALLEL_READ_NVLD = 12 ;
+static const uint8_t P9N2_PU_N0_PSCOM_ERROR_MASK_PARALLEL_ADDR_INVALID = 13 ;
+static const uint8_t P9N2_PU_N0_PSCOM_ERROR_MASK_PCB_COMMAND_PARITY = 14 ;
+static const uint8_t P9N2_PU_N0_PSCOM_ERROR_MASK_GENERAL_TIMEOUT = 15 ;
+static const uint8_t P9N2_PU_N0_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 16 ;
+static const uint8_t P9N2_PU_N0_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 17 ;
+
+static const uint8_t P9N2_PU_N3_PSCOM_MODE_REG_ABORT_ON_PCB_ADDR_PARITY_ERROR = 0 ;
+static const uint8_t P9N2_PU_N3_PSCOM_MODE_REG_ABORT_ON_PCB_WDATA_PARITY_ERROR = 1 ;
+static const uint8_t P9N2_PU_N3_PSCOM_MODE_REG_UNUSED_BIT_2 = 2 ;
+static const uint8_t P9N2_PU_N3_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR = 3 ;
+static const uint8_t P9N2_PU_N3_PSCOM_MODE_REG_WATCHDOG_ENABLE = 4 ;
+static const uint8_t P9N2_PU_N3_PSCOM_MODE_REG_SCOM_HANG_LIMIT = 5 ;
+static const uint8_t P9N2_PU_N3_PSCOM_MODE_REG_SCOM_HANG_LIMIT_LEN = 2 ;
+static const uint8_t P9N2_PU_N3_PSCOM_MODE_REG_FORCE_ALL_RINGS = 7 ;
+static const uint8_t P9N2_PU_N3_PSCOM_MODE_REG_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE = 8 ;
+static const uint8_t P9N2_PU_N3_PSCOM_MODE_REG_RESERVED_LT = 9 ;
+static const uint8_t P9N2_PU_N3_PSCOM_MODE_REG_RESERVED_LT_LEN = 3 ;
+
+static const uint8_t P9N2_PU_N1_PSCOM_MODE_REG_ABORT_ON_PCB_ADDR_PARITY_ERROR = 0 ;
+static const uint8_t P9N2_PU_N1_PSCOM_MODE_REG_ABORT_ON_PCB_WDATA_PARITY_ERROR = 1 ;
+static const uint8_t P9N2_PU_N1_PSCOM_MODE_REG_UNUSED_BIT_2 = 2 ;
+static const uint8_t P9N2_PU_N1_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR = 3 ;
+static const uint8_t P9N2_PU_N1_PSCOM_MODE_REG_WATCHDOG_ENABLE = 4 ;
+static const uint8_t P9N2_PU_N1_PSCOM_MODE_REG_SCOM_HANG_LIMIT = 5 ;
+static const uint8_t P9N2_PU_N1_PSCOM_MODE_REG_SCOM_HANG_LIMIT_LEN = 2 ;
+static const uint8_t P9N2_PU_N1_PSCOM_MODE_REG_FORCE_ALL_RINGS = 7 ;
+static const uint8_t P9N2_PU_N1_PSCOM_MODE_REG_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE = 8 ;
+static const uint8_t P9N2_PU_N1_PSCOM_MODE_REG_RESERVED_LT = 9 ;
+static const uint8_t P9N2_PU_N1_PSCOM_MODE_REG_RESERVED_LT_LEN = 3 ;
+
+static const uint8_t P9N2_PU_PSCOM_MODE_REG_ABORT_ON_PCB_ADDR_PARITY_ERROR = 0 ;
+static const uint8_t P9N2_PU_PSCOM_MODE_REG_ABORT_ON_PCB_WDATA_PARITY_ERROR = 1 ;
+static const uint8_t P9N2_PU_PSCOM_MODE_REG_UNUSED_BIT_2 = 2 ;
+static const uint8_t P9N2_PU_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR = 3 ;
+static const uint8_t P9N2_PU_PSCOM_MODE_REG_WATCHDOG_ENABLE = 4 ;
+static const uint8_t P9N2_PU_PSCOM_MODE_REG_SCOM_HANG_LIMIT = 5 ;
+static const uint8_t P9N2_PU_PSCOM_MODE_REG_SCOM_HANG_LIMIT_LEN = 2 ;
+static const uint8_t P9N2_PU_PSCOM_MODE_REG_FORCE_ALL_RINGS = 7 ;
+static const uint8_t P9N2_PU_PSCOM_MODE_REG_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE = 8 ;
+static const uint8_t P9N2_PU_PSCOM_MODE_REG_RESERVED_LT = 9 ;
+static const uint8_t P9N2_PU_PSCOM_MODE_REG_RESERVED_LT_LEN = 3 ;
+
+static const uint8_t P9N2_PU_N2_PSCOM_MODE_REG_ABORT_ON_PCB_ADDR_PARITY_ERROR = 0 ;
+static const uint8_t P9N2_PU_N2_PSCOM_MODE_REG_ABORT_ON_PCB_WDATA_PARITY_ERROR = 1 ;
+static const uint8_t P9N2_PU_N2_PSCOM_MODE_REG_UNUSED_BIT_2 = 2 ;
+static const uint8_t P9N2_PU_N2_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR = 3 ;
+static const uint8_t P9N2_PU_N2_PSCOM_MODE_REG_WATCHDOG_ENABLE = 4 ;
+static const uint8_t P9N2_PU_N2_PSCOM_MODE_REG_SCOM_HANG_LIMIT = 5 ;
+static const uint8_t P9N2_PU_N2_PSCOM_MODE_REG_SCOM_HANG_LIMIT_LEN = 2 ;
+static const uint8_t P9N2_PU_N2_PSCOM_MODE_REG_FORCE_ALL_RINGS = 7 ;
+static const uint8_t P9N2_PU_N2_PSCOM_MODE_REG_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE = 8 ;
+static const uint8_t P9N2_PU_N2_PSCOM_MODE_REG_RESERVED_LT = 9 ;
+static const uint8_t P9N2_PU_N2_PSCOM_MODE_REG_RESERVED_LT_LEN = 3 ;
+
+static const uint8_t P9N2_PEC_PSCOM_MODE_REG_ABORT_ON_PCB_ADDR_PARITY_ERROR = 0 ;
+static const uint8_t P9N2_PEC_PSCOM_MODE_REG_ABORT_ON_PCB_WDATA_PARITY_ERROR = 1 ;
+static const uint8_t P9N2_PEC_PSCOM_MODE_REG_UNUSED_BIT_2 = 2 ;
+static const uint8_t P9N2_PEC_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR = 3 ;
+static const uint8_t P9N2_PEC_PSCOM_MODE_REG_WATCHDOG_ENABLE = 4 ;
+static const uint8_t P9N2_PEC_PSCOM_MODE_REG_SCOM_HANG_LIMIT = 5 ;
+static const uint8_t P9N2_PEC_PSCOM_MODE_REG_SCOM_HANG_LIMIT_LEN = 2 ;
+static const uint8_t P9N2_PEC_PSCOM_MODE_REG_FORCE_ALL_RINGS = 7 ;
+static const uint8_t P9N2_PEC_PSCOM_MODE_REG_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE = 8 ;
+static const uint8_t P9N2_PEC_PSCOM_MODE_REG_RESERVED_LT = 9 ;
+static const uint8_t P9N2_PEC_PSCOM_MODE_REG_RESERVED_LT_LEN = 3 ;
+
+static const uint8_t P9N2_PU_N0_PSCOM_MODE_REG_ABORT_ON_PCB_ADDR_PARITY_ERROR = 0 ;
+static const uint8_t P9N2_PU_N0_PSCOM_MODE_REG_ABORT_ON_PCB_WDATA_PARITY_ERROR = 1 ;
+static const uint8_t P9N2_PU_N0_PSCOM_MODE_REG_UNUSED_BIT_2 = 2 ;
+static const uint8_t P9N2_PU_N0_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR = 3 ;
+static const uint8_t P9N2_PU_N0_PSCOM_MODE_REG_WATCHDOG_ENABLE = 4 ;
+static const uint8_t P9N2_PU_N0_PSCOM_MODE_REG_SCOM_HANG_LIMIT = 5 ;
+static const uint8_t P9N2_PU_N0_PSCOM_MODE_REG_SCOM_HANG_LIMIT_LEN = 2 ;
+static const uint8_t P9N2_PU_N0_PSCOM_MODE_REG_FORCE_ALL_RINGS = 7 ;
+static const uint8_t P9N2_PU_N0_PSCOM_MODE_REG_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE = 8 ;
+static const uint8_t P9N2_PU_N0_PSCOM_MODE_REG_RESERVED_LT = 9 ;
+static const uint8_t P9N2_PU_N0_PSCOM_MODE_REG_RESERVED_LT_LEN = 3 ;
+
+static const uint8_t P9N2_PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_WDATA_PARITY = 0 ;
+static const uint8_t P9N2_PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_ADDRESS_PARITY = 1 ;
+static const uint8_t P9N2_PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_WDATA_PARITY = 2 ;
+static const uint8_t P9N2_PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_P0 = 3 ;
+static const uint8_t P9N2_PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_RDATA_PARITY = 4 ;
+static const uint8_t P9N2_PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_P0 = 5 ;
+static const uint8_t P9N2_PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE = 6 ;
+static const uint8_t P9N2_PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_P2S_MACHINE = 7 ;
+static const uint8_t P9N2_PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 8 ;
+static const uint8_t P9N2_PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 9 ;
+static const uint8_t P9N2_PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 10 ;
+static const uint8_t P9N2_PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_WRITE_NVLD = 11 ;
+static const uint8_t P9N2_PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_READ_NVLD = 12 ;
+static const uint8_t P9N2_PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_ADDR_INVALID = 13 ;
+static const uint8_t P9N2_PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_COMMAND_PARITY = 14 ;
+static const uint8_t P9N2_PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_GENERAL_TIMEOUT = 15 ;
+static const uint8_t P9N2_PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 16 ;
+static const uint8_t P9N2_PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 17 ;
+static const uint8_t P9N2_PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_WDATA_PARITY = 18 ;
+static const uint8_t P9N2_PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_ADDRESS_PARITY = 19 ;
+static const uint8_t P9N2_PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_WDATA_PARITY = 20 ;
+static const uint8_t P9N2_PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_P0 = 21 ;
+static const uint8_t P9N2_PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_RDATA_PARITY = 22 ;
+static const uint8_t P9N2_PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_P0 = 23 ;
+static const uint8_t P9N2_PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_INTERFACE_MACHINE = 24 ;
+static const uint8_t P9N2_PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_P2S_MACHINE = 25 ;
+static const uint8_t P9N2_PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 26 ;
+static const uint8_t P9N2_PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 27 ;
+static const uint8_t P9N2_PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 28 ;
+static const uint8_t P9N2_PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_WRITE_NVLD = 29 ;
+static const uint8_t P9N2_PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_READ_NVLD = 30 ;
+static const uint8_t P9N2_PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_ADDR_INVALID = 31 ;
+static const uint8_t P9N2_PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_COMMAND_PARITY = 32 ;
+static const uint8_t P9N2_PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_GENERAL_TIMEOUT = 33 ;
+static const uint8_t P9N2_PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 34 ;
+static const uint8_t P9N2_PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 35 ;
+
+static const uint8_t P9N2_PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_WDATA_PARITY = 0 ;
+static const uint8_t P9N2_PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_ADDRESS_PARITY = 1 ;
+static const uint8_t P9N2_PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_WDATA_PARITY = 2 ;
+static const uint8_t P9N2_PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_P0 = 3 ;
+static const uint8_t P9N2_PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_RDATA_PARITY = 4 ;
+static const uint8_t P9N2_PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_P0 = 5 ;
+static const uint8_t P9N2_PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE = 6 ;
+static const uint8_t P9N2_PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_P2S_MACHINE = 7 ;
+static const uint8_t P9N2_PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 8 ;
+static const uint8_t P9N2_PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 9 ;
+static const uint8_t P9N2_PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 10 ;
+static const uint8_t P9N2_PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_WRITE_NVLD = 11 ;
+static const uint8_t P9N2_PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_READ_NVLD = 12 ;
+static const uint8_t P9N2_PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_ADDR_INVALID = 13 ;
+static const uint8_t P9N2_PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_COMMAND_PARITY = 14 ;
+static const uint8_t P9N2_PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_GENERAL_TIMEOUT = 15 ;
+static const uint8_t P9N2_PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 16 ;
+static const uint8_t P9N2_PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 17 ;
+static const uint8_t P9N2_PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_WDATA_PARITY = 18 ;
+static const uint8_t P9N2_PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_ADDRESS_PARITY = 19 ;
+static const uint8_t P9N2_PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_WDATA_PARITY = 20 ;
+static const uint8_t P9N2_PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_P0 = 21 ;
+static const uint8_t P9N2_PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_RDATA_PARITY = 22 ;
+static const uint8_t P9N2_PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_P0 = 23 ;
+static const uint8_t P9N2_PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_INTERFACE_MACHINE = 24 ;
+static const uint8_t P9N2_PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_P2S_MACHINE = 25 ;
+static const uint8_t P9N2_PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 26 ;
+static const uint8_t P9N2_PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 27 ;
+static const uint8_t P9N2_PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 28 ;
+static const uint8_t P9N2_PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_WRITE_NVLD = 29 ;
+static const uint8_t P9N2_PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_READ_NVLD = 30 ;
+static const uint8_t P9N2_PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_ADDR_INVALID = 31 ;
+static const uint8_t P9N2_PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_COMMAND_PARITY = 32 ;
+static const uint8_t P9N2_PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_GENERAL_TIMEOUT = 33 ;
+static const uint8_t P9N2_PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 34 ;
+static const uint8_t P9N2_PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 35 ;
+
+static const uint8_t P9N2_PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_WDATA_PARITY = 0 ;
+static const uint8_t P9N2_PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_ADDRESS_PARITY = 1 ;
+static const uint8_t P9N2_PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_WDATA_PARITY = 2 ;
+static const uint8_t P9N2_PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_P0 = 3 ;
+static const uint8_t P9N2_PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_RDATA_PARITY = 4 ;
+static const uint8_t P9N2_PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_P0 = 5 ;
+static const uint8_t P9N2_PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE = 6 ;
+static const uint8_t P9N2_PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_P2S_MACHINE = 7 ;
+static const uint8_t P9N2_PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 8 ;
+static const uint8_t P9N2_PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 9 ;
+static const uint8_t P9N2_PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 10 ;
+static const uint8_t P9N2_PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_WRITE_NVLD = 11 ;
+static const uint8_t P9N2_PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_READ_NVLD = 12 ;
+static const uint8_t P9N2_PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_ADDR_INVALID = 13 ;
+static const uint8_t P9N2_PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_COMMAND_PARITY = 14 ;
+static const uint8_t P9N2_PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_GENERAL_TIMEOUT = 15 ;
+static const uint8_t P9N2_PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 16 ;
+static const uint8_t P9N2_PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 17 ;
+static const uint8_t P9N2_PU_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_WDATA_PARITY = 18 ;
+static const uint8_t P9N2_PU_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_ADDRESS_PARITY = 19 ;
+static const uint8_t P9N2_PU_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_WDATA_PARITY = 20 ;
+static const uint8_t P9N2_PU_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_P0 = 21 ;
+static const uint8_t P9N2_PU_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_RDATA_PARITY = 22 ;
+static const uint8_t P9N2_PU_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_P0 = 23 ;
+static const uint8_t P9N2_PU_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_INTERFACE_MACHINE = 24 ;
+static const uint8_t P9N2_PU_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_P2S_MACHINE = 25 ;
+static const uint8_t P9N2_PU_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 26 ;
+static const uint8_t P9N2_PU_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 27 ;
+static const uint8_t P9N2_PU_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 28 ;
+static const uint8_t P9N2_PU_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_WRITE_NVLD = 29 ;
+static const uint8_t P9N2_PU_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_READ_NVLD = 30 ;
+static const uint8_t P9N2_PU_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_ADDR_INVALID = 31 ;
+static const uint8_t P9N2_PU_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_COMMAND_PARITY = 32 ;
+static const uint8_t P9N2_PU_PSCOM_STATUS_ERROR_REG_TRAPPED_GENERAL_TIMEOUT = 33 ;
+static const uint8_t P9N2_PU_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 34 ;
+static const uint8_t P9N2_PU_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 35 ;
+
+static const uint8_t P9N2_PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_WDATA_PARITY = 0 ;
+static const uint8_t P9N2_PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_ADDRESS_PARITY = 1 ;
+static const uint8_t P9N2_PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_WDATA_PARITY = 2 ;
+static const uint8_t P9N2_PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_P0 = 3 ;
+static const uint8_t P9N2_PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_RDATA_PARITY = 4 ;
+static const uint8_t P9N2_PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_P0 = 5 ;
+static const uint8_t P9N2_PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE = 6 ;
+static const uint8_t P9N2_PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_P2S_MACHINE = 7 ;
+static const uint8_t P9N2_PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 8 ;
+static const uint8_t P9N2_PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 9 ;
+static const uint8_t P9N2_PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 10 ;
+static const uint8_t P9N2_PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_WRITE_NVLD = 11 ;
+static const uint8_t P9N2_PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_READ_NVLD = 12 ;
+static const uint8_t P9N2_PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_ADDR_INVALID = 13 ;
+static const uint8_t P9N2_PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_COMMAND_PARITY = 14 ;
+static const uint8_t P9N2_PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_GENERAL_TIMEOUT = 15 ;
+static const uint8_t P9N2_PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 16 ;
+static const uint8_t P9N2_PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 17 ;
+static const uint8_t P9N2_PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_WDATA_PARITY = 18 ;
+static const uint8_t P9N2_PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_ADDRESS_PARITY = 19 ;
+static const uint8_t P9N2_PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_WDATA_PARITY = 20 ;
+static const uint8_t P9N2_PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_P0 = 21 ;
+static const uint8_t P9N2_PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_RDATA_PARITY = 22 ;
+static const uint8_t P9N2_PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_P0 = 23 ;
+static const uint8_t P9N2_PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_INTERFACE_MACHINE = 24 ;
+static const uint8_t P9N2_PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_P2S_MACHINE = 25 ;
+static const uint8_t P9N2_PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 26 ;
+static const uint8_t P9N2_PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 27 ;
+static const uint8_t P9N2_PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 28 ;
+static const uint8_t P9N2_PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_WRITE_NVLD = 29 ;
+static const uint8_t P9N2_PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_READ_NVLD = 30 ;
+static const uint8_t P9N2_PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_ADDR_INVALID = 31 ;
+static const uint8_t P9N2_PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_COMMAND_PARITY = 32 ;
+static const uint8_t P9N2_PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_GENERAL_TIMEOUT = 33 ;
+static const uint8_t P9N2_PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 34 ;
+static const uint8_t P9N2_PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 35 ;
+
+static const uint8_t P9N2_PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_WDATA_PARITY = 0 ;
+static const uint8_t P9N2_PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_ADDRESS_PARITY = 1 ;
+static const uint8_t P9N2_PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_WDATA_PARITY = 2 ;
+static const uint8_t P9N2_PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_P0 = 3 ;
+static const uint8_t P9N2_PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_RDATA_PARITY = 4 ;
+static const uint8_t P9N2_PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_P0 = 5 ;
+static const uint8_t P9N2_PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE = 6 ;
+static const uint8_t P9N2_PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_P2S_MACHINE = 7 ;
+static const uint8_t P9N2_PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 8 ;
+static const uint8_t P9N2_PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 9 ;
+static const uint8_t P9N2_PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 10 ;
+static const uint8_t P9N2_PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_WRITE_NVLD = 11 ;
+static const uint8_t P9N2_PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_READ_NVLD = 12 ;
+static const uint8_t P9N2_PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_ADDR_INVALID = 13 ;
+static const uint8_t P9N2_PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_COMMAND_PARITY = 14 ;
+static const uint8_t P9N2_PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_GENERAL_TIMEOUT = 15 ;
+static const uint8_t P9N2_PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 16 ;
+static const uint8_t P9N2_PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 17 ;
+static const uint8_t P9N2_PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_WDATA_PARITY = 18 ;
+static const uint8_t P9N2_PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_ADDRESS_PARITY = 19 ;
+static const uint8_t P9N2_PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_WDATA_PARITY = 20 ;
+static const uint8_t P9N2_PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_P0 = 21 ;
+static const uint8_t P9N2_PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_RDATA_PARITY = 22 ;
+static const uint8_t P9N2_PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_P0 = 23 ;
+static const uint8_t P9N2_PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_INTERFACE_MACHINE = 24 ;
+static const uint8_t P9N2_PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_P2S_MACHINE = 25 ;
+static const uint8_t P9N2_PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 26 ;
+static const uint8_t P9N2_PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 27 ;
+static const uint8_t P9N2_PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 28 ;
+static const uint8_t P9N2_PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_WRITE_NVLD = 29 ;
+static const uint8_t P9N2_PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_READ_NVLD = 30 ;
+static const uint8_t P9N2_PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_ADDR_INVALID = 31 ;
+static const uint8_t P9N2_PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_COMMAND_PARITY = 32 ;
+static const uint8_t P9N2_PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_GENERAL_TIMEOUT = 33 ;
+static const uint8_t P9N2_PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 34 ;
+static const uint8_t P9N2_PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 35 ;
+
+static const uint8_t P9N2_PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_WDATA_PARITY = 0 ;
+static const uint8_t P9N2_PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_ADDRESS_PARITY = 1 ;
+static const uint8_t P9N2_PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_WDATA_PARITY = 2 ;
+static const uint8_t P9N2_PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_P0 = 3 ;
+static const uint8_t P9N2_PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_RDATA_PARITY = 4 ;
+static const uint8_t P9N2_PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_P0 = 5 ;
+static const uint8_t P9N2_PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE = 6 ;
+static const uint8_t P9N2_PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_P2S_MACHINE = 7 ;
+static const uint8_t P9N2_PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 8 ;
+static const uint8_t P9N2_PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 9 ;
+static const uint8_t P9N2_PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 10 ;
+static const uint8_t P9N2_PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_WRITE_NVLD = 11 ;
+static const uint8_t P9N2_PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_READ_NVLD = 12 ;
+static const uint8_t P9N2_PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_ADDR_INVALID = 13 ;
+static const uint8_t P9N2_PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_COMMAND_PARITY = 14 ;
+static const uint8_t P9N2_PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_GENERAL_TIMEOUT = 15 ;
+static const uint8_t P9N2_PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 16 ;
+static const uint8_t P9N2_PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 17 ;
+static const uint8_t P9N2_PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_WDATA_PARITY = 18 ;
+static const uint8_t P9N2_PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_ADDRESS_PARITY = 19 ;
+static const uint8_t P9N2_PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_WDATA_PARITY = 20 ;
+static const uint8_t P9N2_PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_P0 = 21 ;
+static const uint8_t P9N2_PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_RDATA_PARITY = 22 ;
+static const uint8_t P9N2_PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_P0 = 23 ;
+static const uint8_t P9N2_PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_INTERFACE_MACHINE = 24 ;
+static const uint8_t P9N2_PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_P2S_MACHINE = 25 ;
+static const uint8_t P9N2_PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 26 ;
+static const uint8_t P9N2_PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 27 ;
+static const uint8_t P9N2_PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 28 ;
+static const uint8_t P9N2_PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_WRITE_NVLD = 29 ;
+static const uint8_t P9N2_PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_READ_NVLD = 30 ;
+static const uint8_t P9N2_PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_ADDR_INVALID = 31 ;
+static const uint8_t P9N2_PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_COMMAND_PARITY = 32 ;
+static const uint8_t P9N2_PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_GENERAL_TIMEOUT = 33 ;
+static const uint8_t P9N2_PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 34 ;
+static const uint8_t P9N2_PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 35 ;
+
+static const uint8_t P9N2_PU_PSIHB_DEBUG_REG_PSIHB2FSP_INJ_ERR_BITS = 0 ;
+static const uint8_t P9N2_PU_PSIHB_DEBUG_REG_PSIHB2FSP_INJ_ERR_BITS_LEN = 2 ;
+static const uint8_t P9N2_PU_PSIHB_DEBUG_REG_PSIHB2FSP_INJ_ONCE = 2 ;
+static const uint8_t P9N2_PU_PSIHB_DEBUG_REG_PSIHB2FSP_INJ_CONST = 3 ;
+static const uint8_t P9N2_PU_PSIHB_DEBUG_REG_PSIHB2PB_INJ_ERR_BITS = 8 ;
+static const uint8_t P9N2_PU_PSIHB_DEBUG_REG_PSIHB2PB_INJ_ERR_BITS_LEN = 2 ;
+static const uint8_t P9N2_PU_PSIHB_DEBUG_REG_PSIHB2PB_INJ_ONCE = 10 ;
+static const uint8_t P9N2_PU_PSIHB_DEBUG_REG_PSIHB2PB_INJ_CONST = 11 ;
+static const uint8_t P9N2_PU_PSIHB_DEBUG_REG_TRACE_SEL = 16 ;
+static const uint8_t P9N2_PU_PSIHB_DEBUG_REG_TRACE_SEL_LEN = 4 ;
+
+static const uint8_t P9N2_PU_PSIHB_ERROR_MASK_REG_DISABLE_1 = 16 ;
+static const uint8_t P9N2_PU_PSIHB_ERROR_MASK_REG_DISABLE_1_LEN = 12 ;
+static const uint8_t P9N2_PU_PSIHB_ERROR_MASK_REG_INTERRUPT_DISABLE = 32 ;
+static const uint8_t P9N2_PU_PSIHB_ERROR_MASK_REG_INTERRUPT_DISABLE_LEN = 12 ;
+static const uint8_t P9N2_PU_PSIHB_ERROR_MASK_REG_DISABLE_2 = 48 ;
+static const uint8_t P9N2_PU_PSIHB_ERROR_MASK_REG_DISABLE_2_LEN = 5 ;
+
+static const uint8_t P9N2_PU_PSIHB_FIR_ACTION0_REG_PB_ECC_ERR_CE = 0 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_ACTION0_REG_PB_ECC_ERR_UE = 1 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_ACTION0_REG_PB_ECC_ERR_SUE = 2 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_ACTION0_REG_INTERRUPT_FROM_ERROR = 3 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_ACTION0_REG_INTERRUPT_FROM_FSP = 4 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_ACTION0_REG_FSP_ECC_ERR_CE = 5 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_ACTION0_REG_FSP_ECC_ERR_UE = 6 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_ACTION0_REG_ERROR_STATE = 7 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_ACTION0_REG_INVALID_TTYPE = 8 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_ACTION0_REG_INVALID_CRESP = 9 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_ACTION0_REG_PB_DATA_TIME_OUT = 10 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_ACTION0_REG_PB_PARITY_ERROR = 11 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_ACTION0_REG_FSP_ACCESS_TRUSTED_SPACE = 12 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_ACTION0_REG_UNEXPECTED_PB = 13 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_ACTION0_REG_INTERRUPT_CHANGE_WHILE_ACTIVE = 14 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_ACTION0_REG_INTERRUPT0_ADDRESS_ERROR = 15 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_ACTION0_REG_INTERRUPT1_ADDRESS_ERROR = 16 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_ACTION0_REG_INTERRUPT2_ADDRESS_ERROR = 17 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_ACTION0_REG_INTERRUPT3_ADDRESS_ERROR = 18 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_ACTION0_REG_INTERRUPT4_ADDRESS_ERROR = 19 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_ACTION0_REG_INTERRUPT5_ADDRESS_ERROR = 20 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_ACTION0_REG_TCBR_TP_PSI_GLB_ERR_0 = 21 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_ACTION0_REG_TCBR_TP_PSI_GLB_ERR_1 = 22 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_ACTION0_REG_UPSTREAM = 23 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_ACTION0_REG_SPARE = 24 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_ACTION0_REG_SPARE_LEN = 3 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_ACTION0_REG_SCOM_ERROR = 27 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_ACTION0_REG_PARITY_ERROR = 28 ;
+
+static const uint8_t P9N2_PU_PSIHB_FIR_ACTION1_REG_PB_ECC_ERR_CE = 0 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_ACTION1_REG_PB_ECC_ERR_UE = 1 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_ACTION1_REG_PB_ECC_ERR_SUE = 2 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_ACTION1_REG_INTERRUPT_FROM_ERROR = 3 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_ACTION1_REG_INTERRUPT_FROM_FSP = 4 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_ACTION1_REG_FSP_ECC_ERR_CE = 5 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_ACTION1_REG_FSP_ECC_ERR_UE = 6 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_ACTION1_REG_ERROR_STATE = 7 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_ACTION1_REG_INVALID_TTYPE = 8 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_ACTION1_REG_INVALID_CRESP = 9 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_ACTION1_REG_PB_DATA_TIME_OUT = 10 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_ACTION1_REG_PB_PARITY_ERROR = 11 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_ACTION1_REG_FSP_ACCESS_TRUSTED_SPACE = 12 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_ACTION1_REG_UNEXPECTED_PB = 13 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_ACTION1_REG_INTERRUPT_CHANGE_WHILE_ACTIVE = 14 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_ACTION1_REG_INTERRUPT0_ADDRESS_ERROR = 15 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_ACTION1_REG_INTERRUPT1_ADDRESS_ERROR = 16 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_ACTION1_REG_INTERRUPT2_ADDRESS_ERROR = 17 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_ACTION1_REG_INTERRUPT3_ADDRESS_ERROR = 18 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_ACTION1_REG_INTERRUPT4_ADDRESS_ERROR = 19 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_ACTION1_REG_INTERRUPT5_ADDRESS_ERROR = 20 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_ACTION1_REG_TCBR_TP_PSI_GLB_ERR_0 = 21 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_ACTION1_REG_TCBR_TP_PSI_GLB_ERR_1 = 22 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_ACTION1_REG_UPSTREAM = 23 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_ACTION1_REG_SPARE = 24 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_ACTION1_REG_SPARE_LEN = 3 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_ACTION1_REG_SCOM_ERROR = 27 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_ACTION1_REG_PARITY_ERROR = 28 ;
+
+static const uint8_t P9N2_PU_PSIHB_FIR_MASK_REG_PB_ECC_ERR_CE = 0 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_MASK_REG_PB_ECC_ERR_UE = 1 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_MASK_REG_PB_ECC_ERR_SUE = 2 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_MASK_REG_INTERRUPT_FROM_ERROR = 3 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_MASK_REG_INTERRUPT_FROM_FSP = 4 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_MASK_REG_FSP_ECC_ERR_CE = 5 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_MASK_REG_FSP_ECC_ERR_UE = 6 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_MASK_REG_ERROR_STATE = 7 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_MASK_REG_INVALID_TTYPE = 8 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_MASK_REG_INVALID_CRESP = 9 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_MASK_REG_PB_DATA_TIME_OUT = 10 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_MASK_REG_PB_PARITY_ERROR = 11 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_MASK_REG_FSP_ACCESS_TRUSTED_SPACE = 12 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_MASK_REG_UNEXPECTED_PB = 13 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_MASK_REG_INTERRUPT_CHANGE_WHILE_ACTIVE = 14 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_MASK_REG_INTERRUPT0_ADDRESS_ERROR = 15 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_MASK_REG_INTERRUPT1_ADDRESS_ERROR = 16 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_MASK_REG_INTERRUPT2_ADDRESS_ERROR = 17 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_MASK_REG_INTERRUPT3_ADDRESS_ERROR = 18 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_MASK_REG_INTERRUPT4_ADDRESS_ERROR = 19 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_MASK_REG_INTERRUPT5_ADDRESS_ERROR = 20 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_MASK_REG_TCBR_TP_PSI_GLB_ERR_0 = 21 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_MASK_REG_TCBR_TP_PSI_GLB_ERR_1 = 22 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_MASK_REG_UPSTREAM = 23 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_MASK_REG_SPARE = 24 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_MASK_REG_SPARE_LEN = 3 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_MASK_REG_SCOM_ERROR = 27 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_MASK_REG_PARITY_ERROR = 28 ;
+
+static const uint8_t P9N2_PU_PSIHB_FIR_REG_PB_ECC_ERR_CE = 0 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_REG_PB_ECC_ERR_UE = 1 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_REG_PB_ECC_ERR_SUE = 2 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_REG_INTERRUPT_FROM_ERROR = 3 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_REG_INTERRUPT_FROM_FSP = 4 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_REG_FSP_ECC_ERR_CE = 5 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_REG_FSP_ECC_ERR_UE = 6 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_REG_ERROR_STATE = 7 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_REG_INVALID_TTYPE = 8 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_REG_INVALID_CRESP = 9 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_REG_PB_DATA_TIME_OUT = 10 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_REG_PB_PARITY_ERROR = 11 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_REG_FSP_ACCESS_TRUSTED_SPACE = 12 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_REG_UNEXPECTED_PB = 13 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_REG_INTERRUPT_CHANGE_WHILE_ACTIVE = 14 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_REG_INTERRUPT0_ADDRESS_ERROR = 15 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_REG_INTERRUPT1_ADDRESS_ERROR = 16 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_REG_INTERRUPT2_ADDRESS_ERROR = 17 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_REG_INTERRUPT3_ADDRESS_ERROR = 18 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_REG_INTERRUPT4_ADDRESS_ERROR = 19 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_REG_INTERRUPT5_ADDRESS_ERROR = 20 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_REG_TCBR_TP_PSI_GLB_ERR_0 = 21 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_REG_TCBR_TP_PSI_GLB_ERR_1 = 22 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_REG_UPSTREAM = 23 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_REG_SPARE = 24 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_REG_SPARE_LEN = 3 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_REG_SCOM_ERROR = 27 ;
+static const uint8_t P9N2_PU_PSIHB_FIR_REG_PARITY_ERROR = 28 ;
+
+static const uint8_t P9N2_PU_PSIHB_INTERRUPT_CONTROL_ESB_OR_LSI_INTERRUPTS = 0 ;
+static const uint8_t P9N2_PU_PSIHB_INTERRUPT_CONTROL_SM_RESET = 1 ;
+
+static const uint8_t P9N2_PU_PSIHB_INTERRUPT_LEVEL_PSI_INTERRUPT_HIGH = 0 ;
+static const uint8_t P9N2_PU_PSIHB_INTERRUPT_LEVEL_OCC_INTERRUPT_HIGH = 1 ;
+static const uint8_t P9N2_PU_PSIHB_INTERRUPT_LEVEL_FSI_INTERRUPT_HIGH = 2 ;
+static const uint8_t P9N2_PU_PSIHB_INTERRUPT_LEVEL_LPC_INTERRUPT_HIGH = 3 ;
+static const uint8_t P9N2_PU_PSIHB_INTERRUPT_LEVEL_LOCAL_INTERRUPT_HIGH = 4 ;
+static const uint8_t P9N2_PU_PSIHB_INTERRUPT_LEVEL_SYSTEM_ATTENTION_HIGH = 5 ;
+static const uint8_t P9N2_PU_PSIHB_INTERRUPT_LEVEL_TPM_INTERRUPT_HIGH = 6 ;
+static const uint8_t P9N2_PU_PSIHB_INTERRUPT_LEVEL_LPC_OTHER_INTERRUPT_HIGH = 7 ;
+static const uint8_t P9N2_PU_PSIHB_INTERRUPT_LEVEL_LPC_OTHER_INTERRUPT_HIGH_LEN = 4 ;
+static const uint8_t P9N2_PU_PSIHB_INTERRUPT_LEVEL_SBE_OR_I2C_INTERRUPT_HIGH = 11 ;
+static const uint8_t P9N2_PU_PSIHB_INTERRUPT_LEVEL_DIO_INTERRUPT_HIGH = 12 ;
+static const uint8_t P9N2_PU_PSIHB_INTERRUPT_LEVEL_PSU_INTERRUPT_HIGH = 13 ;
+static const uint8_t P9N2_PU_PSIHB_INTERRUPT_LEVEL_I2C_C_INTERRUPT_HIGH = 14 ;
+static const uint8_t P9N2_PU_PSIHB_INTERRUPT_LEVEL_I2C_D_INTERRUPT_HIGH = 15 ;
+static const uint8_t P9N2_PU_PSIHB_INTERRUPT_LEVEL_I2C_E_INTERRUPT_HIGH = 16 ;
+static const uint8_t P9N2_PU_PSIHB_INTERRUPT_LEVEL_RESERVED = 17 ;
+static const uint8_t P9N2_PU_PSIHB_INTERRUPT_LEVEL_RESERVED_LEN = 2 ;
+static const uint8_t P9N2_PU_PSIHB_INTERRUPT_LEVEL_PURE_SBE_INTERRUPT_HIGH = 19 ;
+
+static const uint8_t P9N2_PU_PSIHB_INTERRUPT_STATUS_PSI_INTERRUPT_PENDING = 0 ;
+static const uint8_t P9N2_PU_PSIHB_INTERRUPT_STATUS_OCC_INTERRUPT_PENDING = 1 ;
+static const uint8_t P9N2_PU_PSIHB_INTERRUPT_STATUS_FSI_INTERRUPT_PENDING = 2 ;
+static const uint8_t P9N2_PU_PSIHB_INTERRUPT_STATUS_LPC_INTERRUPT_PENDING = 3 ;
+static const uint8_t P9N2_PU_PSIHB_INTERRUPT_STATUS_LOCAL_INTERRUPT_PENDING = 4 ;
+static const uint8_t P9N2_PU_PSIHB_INTERRUPT_STATUS_SYSTEM_ATTENTION = 5 ;
+static const uint8_t P9N2_PU_PSIHB_INTERRUPT_STATUS_TPM_INTERRUPT_PENDING = 6 ;
+static const uint8_t P9N2_PU_PSIHB_INTERRUPT_STATUS_LPC_OTHER_INTERRUPT_PENDING = 7 ;
+static const uint8_t P9N2_PU_PSIHB_INTERRUPT_STATUS_LPC_OTHER_INTERRUPT_PENDING_LEN = 4 ;
+static const uint8_t P9N2_PU_PSIHB_INTERRUPT_STATUS_SBE_INTERRUPT_PENDING = 11 ;
+static const uint8_t P9N2_PU_PSIHB_INTERRUPT_STATUS_DIO_INTERRUPT_PENDING = 12 ;
+static const uint8_t P9N2_PU_PSIHB_INTERRUPT_STATUS_PSU_INTERRUPT_PENDING = 13 ;
+
+static const uint8_t P9N2_PU_PSIHB_STATUS_CTL_REG_FSP_CMD_ENABLE = 0 ;
+static const uint8_t P9N2_PU_PSIHB_STATUS_CTL_REG_FSP_MMIO_ENABLE = 1 ;
+static const uint8_t P9N2_PU_PSIHB_STATUS_CTL_REG_PHBCSR_SPARE = 2 ;
+static const uint8_t P9N2_PU_PSIHB_STATUS_CTL_REG_FSP_INT_ENABLE = 3 ;
+static const uint8_t P9N2_PU_PSIHB_STATUS_CTL_REG_FSP_ERR_RSP_ENABLE = 4 ;
+static const uint8_t P9N2_PU_PSIHB_STATUS_CTL_REG_PSI_LINK_ENABLE = 5 ;
+static const uint8_t P9N2_PU_PSIHB_STATUS_CTL_REG_FSP_RESET = 6 ;
+static const uint8_t P9N2_PU_PSIHB_STATUS_CTL_REG_PSIHBC_RESET = 7 ;
+static const uint8_t P9N2_PU_PSIHB_STATUS_CTL_REG_FSP_MMIO_MASK = 8 ;
+static const uint8_t P9N2_PU_PSIHB_STATUS_CTL_REG_FSP_MMIO_MASK_LEN = 4 ;
+static const uint8_t P9N2_PU_PSIHB_STATUS_CTL_REG_ST_EOI_ENABLE = 12 ;
+static const uint8_t P9N2_PU_PSIHB_STATUS_CTL_REG_CEC_PSI_INTERRUPT = 16 ;
+static const uint8_t P9N2_PU_PSIHB_STATUS_CTL_REG_FSP_INTERRUPT = 17 ;
+static const uint8_t P9N2_PU_PSIHB_STATUS_CTL_REG_FSP_LINK_ACTIVE = 18 ;
+static const uint8_t P9N2_PU_PSIHB_STATUS_CTL_REG_FSP_OUTBOUND_ACTIVE = 19 ;
+static const uint8_t P9N2_PU_PSIHB_STATUS_CTL_REG_FSP_INBOUND_ACTIVE = 20 ;
+static const uint8_t P9N2_PU_PSIHB_STATUS_CTL_REG_PSIFSP_LOAD_OUTSTANDING = 21 ;
+static const uint8_t P9N2_PU_PSIHB_STATUS_CTL_REG_PSIFSP_DMAR_OUTSTANDING = 22 ;
+static const uint8_t P9N2_PU_PSIHB_STATUS_CTL_REG_PSIFSP_INT_BUSY = 23 ;
+static const uint8_t P9N2_PU_PSIHB_STATUS_CTL_REG_PSI_XMIT_ERROR = 32 ;
+static const uint8_t P9N2_PU_PSIHB_STATUS_CTL_REG_PSI_LINK_INACTIVE_TRANS = 33 ;
+static const uint8_t P9N2_PU_PSIHB_STATUS_CTL_REG_PSIFSP_ACK_TIMEOUT = 34 ;
+static const uint8_t P9N2_PU_PSIHB_STATUS_CTL_REG_PSIFSP_MMIO_LOAD_TIMEOUT = 35 ;
+static const uint8_t P9N2_PU_PSIHB_STATUS_CTL_REG_PSIFSP_MMIO_LENGTH_ERR = 36 ;
+static const uint8_t P9N2_PU_PSIHB_STATUS_CTL_REG_PSIFSP_MMIO_ADDR_ERR = 37 ;
+static const uint8_t P9N2_PU_PSIHB_STATUS_CTL_REG_PSIFSP_MMIO_TYPE_ERR = 38 ;
+static const uint8_t P9N2_PU_PSIHB_STATUS_CTL_REG_PSI_UE = 39 ;
+static const uint8_t P9N2_PU_PSIHB_STATUS_CTL_REG_PSIFSP_PERR = 40 ;
+static const uint8_t P9N2_PU_PSIHB_STATUS_CTL_REG_PSI_ALERT1 = 41 ;
+static const uint8_t P9N2_PU_PSIHB_STATUS_CTL_REG_PSI_ALERT2 = 42 ;
+static const uint8_t P9N2_PU_PSIHB_STATUS_CTL_REG_PSIFSP_DMA_ERR = 43 ;
+static const uint8_t P9N2_PU_PSIHB_STATUS_CTL_REG_PSIFSP_DMA_ADDR_ERR = 48 ;
+static const uint8_t P9N2_PU_PSIHB_STATUS_CTL_REG_PSIFSP_TCE_EXTENT_ERR = 49 ;
+static const uint8_t P9N2_PU_PSIHB_STATUS_CTL_REG_PSIFSP_PAGE_FAULT = 50 ;
+static const uint8_t P9N2_PU_PSIHB_STATUS_CTL_REG_PSIFSP_INV_OP = 51 ;
+static const uint8_t P9N2_PU_PSIHB_STATUS_CTL_REG_FSP_INV_READ = 52 ;
+
+static const uint8_t P9N2_PU_PSI_BRIDGE_BAR_REG_BAR = 8 ;
+static const uint8_t P9N2_PU_PSI_BRIDGE_BAR_REG_BAR_LEN = 36 ;
+static const uint8_t P9N2_PU_PSI_BRIDGE_BAR_REG_EN = 63 ;
+
+static const uint8_t P9N2_PU_PSI_BRIDGE_FSP_BAR_REG_BAR = 8 ;
+static const uint8_t P9N2_PU_PSI_BRIDGE_FSP_BAR_REG_BAR_LEN = 36 ;
+
+static const uint8_t P9N2_PU_PSI_FSP_MMR_REG_MMR = 32 ;
+static const uint8_t P9N2_PU_PSI_FSP_MMR_REG_MMR_LEN = 12 ;
+
+static const uint8_t P9N2_PU_PSI_TCE_ADDR_REG_ADDR = 14 ;
+static const uint8_t P9N2_PU_PSI_TCE_ADDR_REG_ADDR_LEN = 34 ;
+static const uint8_t P9N2_PU_PSI_TCE_ADDR_REG_ENTRIES = 61 ;
+static const uint8_t P9N2_PU_PSI_TCE_ADDR_REG_ENTRIES_LEN = 3 ;
+
+static const uint8_t P9N2_CAPP_PSLTTMAP0_VALID = 0 ;
+static const uint8_t P9N2_CAPP_PSLTTMAP0_TTYPE_MATCH = 1 ;
+static const uint8_t P9N2_CAPP_PSLTTMAP0_TTYPE_MATCH_LEN = 5 ;
+static const uint8_t P9N2_CAPP_PSLTTMAP0_TSIZE_MATCH = 6 ;
+static const uint8_t P9N2_CAPP_PSLTTMAP0_TSIZE_MATCH_LEN = 7 ;
+static const uint8_t P9N2_CAPP_PSLTTMAP0_TSIZE_MASK = 13 ;
+static const uint8_t P9N2_CAPP_PSLTTMAP0_TSIZE_MASK_LEN = 7 ;
+static const uint8_t P9N2_CAPP_PSLTTMAP0_TTYPE_REPLACE = 20 ;
+static const uint8_t P9N2_CAPP_PSLTTMAP0_TTYPE_REPLACE_LEN = 6 ;
+
+static const uint8_t P9N2_CAPP_PSLTTMAP1_VALID = 0 ;
+static const uint8_t P9N2_CAPP_PSLTTMAP1_TTYPE_MATCH = 1 ;
+static const uint8_t P9N2_CAPP_PSLTTMAP1_TTYPE_MATCH_LEN = 5 ;
+static const uint8_t P9N2_CAPP_PSLTTMAP1_TSIZE_MATCH = 6 ;
+static const uint8_t P9N2_CAPP_PSLTTMAP1_TSIZE_MATCH_LEN = 7 ;
+static const uint8_t P9N2_CAPP_PSLTTMAP1_TSIZE_MASK = 13 ;
+static const uint8_t P9N2_CAPP_PSLTTMAP1_TSIZE_MASK_LEN = 7 ;
+static const uint8_t P9N2_CAPP_PSLTTMAP1_TTYPE_REPLACE = 20 ;
+static const uint8_t P9N2_CAPP_PSLTTMAP1_TTYPE_REPLACE_LEN = 6 ;
+
+static const uint8_t P9N2_CAPP_PSLTTMAP2_VALID = 0 ;
+static const uint8_t P9N2_CAPP_PSLTTMAP2_TTYPE_MATCH = 1 ;
+static const uint8_t P9N2_CAPP_PSLTTMAP2_TTYPE_MATCH_LEN = 5 ;
+static const uint8_t P9N2_CAPP_PSLTTMAP2_TSIZE_MATCH = 6 ;
+static const uint8_t P9N2_CAPP_PSLTTMAP2_TSIZE_MATCH_LEN = 7 ;
+static const uint8_t P9N2_CAPP_PSLTTMAP2_TSIZE_MASK = 13 ;
+static const uint8_t P9N2_CAPP_PSLTTMAP2_TSIZE_MASK_LEN = 7 ;
+static const uint8_t P9N2_CAPP_PSLTTMAP2_TTYPE_REPLACE = 20 ;
+static const uint8_t P9N2_CAPP_PSLTTMAP2_TTYPE_REPLACE_LEN = 6 ;
+
+static const uint8_t P9N2_CAPP_PSLTTMAP3_VALID = 0 ;
+static const uint8_t P9N2_CAPP_PSLTTMAP3_TTYPE_MATCH = 1 ;
+static const uint8_t P9N2_CAPP_PSLTTMAP3_TTYPE_MATCH_LEN = 5 ;
+static const uint8_t P9N2_CAPP_PSLTTMAP3_TSIZE_MATCH = 6 ;
+static const uint8_t P9N2_CAPP_PSLTTMAP3_TSIZE_MATCH_LEN = 7 ;
+static const uint8_t P9N2_CAPP_PSLTTMAP3_TSIZE_MASK = 13 ;
+static const uint8_t P9N2_CAPP_PSLTTMAP3_TSIZE_MASK_LEN = 7 ;
+static const uint8_t P9N2_CAPP_PSLTTMAP3_TTYPE_REPLACE = 20 ;
+static const uint8_t P9N2_CAPP_PSLTTMAP3_TTYPE_REPLACE_LEN = 6 ;
+
+static const uint8_t P9N2_PU_NPU_PSL_DAR_AN_CO_EA = 0 ;
+static const uint8_t P9N2_PU_NPU_PSL_DAR_AN_CO_EA_LEN = 64 ;
+
+static const uint8_t P9N2_PU_PSL_DAR_AN_CO_EA = 0 ;
+static const uint8_t P9N2_PU_PSL_DAR_AN_CO_EA_LEN = 64 ;
+
+static const uint8_t P9N2__SM3_PSL_DAR_AN_CO_EA = 0 ;
+static const uint8_t P9N2__SM3_PSL_DAR_AN_CO_EA_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU_SM3_PSL_DAR_AN_CO_EA = 0 ;
+static const uint8_t P9N2_PU_NPU_SM3_PSL_DAR_AN_CO_EA_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU_PSL_DSISR_AN_TF = 3 ;
+static const uint8_t P9N2_PU_NPU_PSL_DSISR_AN_S = 38 ;
+static const uint8_t P9N2_PU_NPU_PSL_DSISR_AN_CO_RSP = 56 ;
+static const uint8_t P9N2_PU_NPU_PSL_DSISR_AN_CO_RSP_LEN = 8 ;
+
+static const uint8_t P9N2_PU_PSL_DSISR_AN_TF = 3 ;
+static const uint8_t P9N2_PU_PSL_DSISR_AN_S = 38 ;
+static const uint8_t P9N2_PU_PSL_DSISR_AN_CO_RSP = 56 ;
+static const uint8_t P9N2_PU_PSL_DSISR_AN_CO_RSP_LEN = 8 ;
+
+static const uint8_t P9N2__SM3_PSL_DSISR_AN_TF = 3 ;
+static const uint8_t P9N2__SM3_PSL_DSISR_AN_S = 38 ;
+static const uint8_t P9N2__SM3_PSL_DSISR_AN_CO_RSP = 56 ;
+static const uint8_t P9N2__SM3_PSL_DSISR_AN_CO_RSP_LEN = 8 ;
+
+static const uint8_t P9N2_PU_NPU_SM3_PSL_DSISR_AN_TF = 3 ;
+static const uint8_t P9N2_PU_NPU_SM3_PSL_DSISR_AN_S = 38 ;
+static const uint8_t P9N2_PU_NPU_SM3_PSL_DSISR_AN_CO_RSP = 56 ;
+static const uint8_t P9N2_PU_NPU_SM3_PSL_DSISR_AN_CO_RSP_LEN = 8 ;
+
+static const uint8_t P9N2_PU_NPU_DAT_PSL_LLCMD_A0_COMMAND_DIAL = 0 ;
+static const uint8_t P9N2_PU_NPU_DAT_PSL_LLCMD_A0_COMMAND_DIAL_LEN = 16 ;
+static const uint8_t P9N2_PU_NPU_DAT_PSL_LLCMD_A0_PENDING_DIAL = 16 ;
+static const uint8_t P9N2_PU_NPU_DAT_PSL_LLCMD_A0_LINK_DIAL = 48 ;
+static const uint8_t P9N2_PU_NPU_DAT_PSL_LLCMD_A0_LINK_DIAL_LEN = 16 ;
+
+static const uint8_t P9N2__DAT_PSL_LLCMD_A0_COMMAND_DIAL = 0 ;
+static const uint8_t P9N2__DAT_PSL_LLCMD_A0_COMMAND_DIAL_LEN = 16 ;
+static const uint8_t P9N2__DAT_PSL_LLCMD_A0_PENDING_DIAL = 16 ;
+static const uint8_t P9N2__DAT_PSL_LLCMD_A0_LINK_DIAL = 48 ;
+static const uint8_t P9N2__DAT_PSL_LLCMD_A0_LINK_DIAL_LEN = 16 ;
+
+static const uint8_t P9N2_PU_NPU_PSL_PEHANDLE_AN_AFUTAG = 16 ;
+static const uint8_t P9N2_PU_NPU_PSL_PEHANDLE_AN_AFUTAG_LEN = 16 ;
+static const uint8_t P9N2_PU_NPU_PSL_PEHANDLE_AN_PE_HANDLE = 48 ;
+static const uint8_t P9N2_PU_NPU_PSL_PEHANDLE_AN_PE_HANDLE_LEN = 16 ;
+
+static const uint8_t P9N2_PU_PSL_PEHANDLE_AN_AFUTAG = 16 ;
+static const uint8_t P9N2_PU_PSL_PEHANDLE_AN_AFUTAG_LEN = 16 ;
+static const uint8_t P9N2_PU_PSL_PEHANDLE_AN_PE_HANDLE = 48 ;
+static const uint8_t P9N2_PU_PSL_PEHANDLE_AN_PE_HANDLE_LEN = 16 ;
+
+static const uint8_t P9N2__SM3_PSL_PEHANDLE_AN_AFUTAG = 16 ;
+static const uint8_t P9N2__SM3_PSL_PEHANDLE_AN_AFUTAG_LEN = 16 ;
+static const uint8_t P9N2__SM3_PSL_PEHANDLE_AN_PE_HANDLE = 48 ;
+static const uint8_t P9N2__SM3_PSL_PEHANDLE_AN_PE_HANDLE_LEN = 16 ;
+
+static const uint8_t P9N2_PU_NPU_SM3_PSL_PEHANDLE_AN_AFUTAG = 16 ;
+static const uint8_t P9N2_PU_NPU_SM3_PSL_PEHANDLE_AN_AFUTAG_LEN = 16 ;
+static const uint8_t P9N2_PU_NPU_SM3_PSL_PEHANDLE_AN_PE_HANDLE = 48 ;
+static const uint8_t P9N2_PU_NPU_SM3_PSL_PEHANDLE_AN_PE_HANDLE_LEN = 16 ;
+
+static const uint8_t P9N2_PU_NPU_DAT_PSL_SCNTL_A0_MULTI_AFU_DIAL = 0 ;
+static const uint8_t P9N2_PU_NPU_DAT_PSL_SCNTL_A0_PC_DIAL = 48 ;
+static const uint8_t P9N2_PU_NPU_DAT_PSL_SCNTL_A0_SS_DIAL = 54 ;
+static const uint8_t P9N2_PU_NPU_DAT_PSL_SCNTL_A0_SS_DIAL_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_DAT_PSL_SCNTL_A0_SC_DIAL = 63 ;
+
+static const uint8_t P9N2__DAT_PSL_SCNTL_A0_MULTI_AFU_DIAL = 0 ;
+static const uint8_t P9N2__DAT_PSL_SCNTL_A0_PC_DIAL = 48 ;
+static const uint8_t P9N2__DAT_PSL_SCNTL_A0_SS_DIAL = 54 ;
+static const uint8_t P9N2__DAT_PSL_SCNTL_A0_SS_DIAL_LEN = 2 ;
+static const uint8_t P9N2__DAT_PSL_SCNTL_A0_SC_DIAL = 63 ;
+
+static const uint8_t P9N2_PU_NPU_DAT_PSL_SPAP_A0_ADDR_DIAL = 4 ;
+static const uint8_t P9N2_PU_NPU_DAT_PSL_SPAP_A0_ADDR_DIAL_LEN = 48 ;
+static const uint8_t P9N2_PU_NPU_DAT_PSL_SPAP_A0_VALID_DIAL = 63 ;
+
+static const uint8_t P9N2__DAT_PSL_SPAP_A0_ADDR_DIAL = 4 ;
+static const uint8_t P9N2__DAT_PSL_SPAP_A0_ADDR_DIAL_LEN = 48 ;
+static const uint8_t P9N2__DAT_PSL_SPAP_A0_VALID_DIAL = 63 ;
+
+static const uint8_t P9N2_PU_NPU_DAT_PSL_SPAP_A1_ADDR_DIAL = 4 ;
+static const uint8_t P9N2_PU_NPU_DAT_PSL_SPAP_A1_ADDR_DIAL_LEN = 48 ;
+static const uint8_t P9N2_PU_NPU_DAT_PSL_SPAP_A1_VALID_DIAL = 63 ;
+
+static const uint8_t P9N2__DAT_PSL_SPAP_A1_ADDR_DIAL = 4 ;
+static const uint8_t P9N2__DAT_PSL_SPAP_A1_ADDR_DIAL_LEN = 48 ;
+static const uint8_t P9N2__DAT_PSL_SPAP_A1_VALID_DIAL = 63 ;
+
+static const uint8_t P9N2_PU_NPU_PSL_TFC_AN_ACK = 28 ;
+static const uint8_t P9N2_PU_NPU_PSL_TFC_AN_C = 29 ;
+static const uint8_t P9N2_PU_NPU_PSL_TFC_AN_AE = 30 ;
+static const uint8_t P9N2_PU_NPU_PSL_TFC_AN_R = 31 ;
+
+static const uint8_t P9N2_PU_PSL_TFC_AN_ACK = 28 ;
+static const uint8_t P9N2_PU_PSL_TFC_AN_C = 29 ;
+static const uint8_t P9N2_PU_PSL_TFC_AN_AE = 30 ;
+static const uint8_t P9N2_PU_PSL_TFC_AN_R = 31 ;
+
+static const uint8_t P9N2__SM3_PSL_TFC_AN_ACK = 28 ;
+static const uint8_t P9N2__SM3_PSL_TFC_AN_C = 29 ;
+static const uint8_t P9N2__SM3_PSL_TFC_AN_AE = 30 ;
+static const uint8_t P9N2__SM3_PSL_TFC_AN_R = 31 ;
+
+static const uint8_t P9N2_PU_NPU_SM3_PSL_TFC_AN_ACK = 28 ;
+static const uint8_t P9N2_PU_NPU_SM3_PSL_TFC_AN_C = 29 ;
+static const uint8_t P9N2_PU_NPU_SM3_PSL_TFC_AN_AE = 30 ;
+static const uint8_t P9N2_PU_NPU_SM3_PSL_TFC_AN_R = 31 ;
+
+static const uint8_t P9N2_PU_PSU_HOST_DOORBELL_REG_0 = 0 ;
+static const uint8_t P9N2_PU_PSU_HOST_DOORBELL_REG_1 = 1 ;
+static const uint8_t P9N2_PU_PSU_HOST_DOORBELL_REG_2 = 2 ;
+static const uint8_t P9N2_PU_PSU_HOST_DOORBELL_REG_3 = 3 ;
+static const uint8_t P9N2_PU_PSU_HOST_DOORBELL_REG_4 = 4 ;
+static const uint8_t P9N2_PU_PSU_HOST_DOORBELL_REG_5 = 5 ;
+static const uint8_t P9N2_PU_PSU_HOST_DOORBELL_REG_6 = 6 ;
+static const uint8_t P9N2_PU_PSU_HOST_DOORBELL_REG_7 = 7 ;
+static const uint8_t P9N2_PU_PSU_HOST_DOORBELL_REG_8 = 8 ;
+static const uint8_t P9N2_PU_PSU_HOST_DOORBELL_REG_9 = 9 ;
+static const uint8_t P9N2_PU_PSU_HOST_DOORBELL_REG_10 = 10 ;
+static const uint8_t P9N2_PU_PSU_HOST_DOORBELL_REG_11 = 11 ;
+static const uint8_t P9N2_PU_PSU_HOST_DOORBELL_REG_12 = 12 ;
+static const uint8_t P9N2_PU_PSU_HOST_DOORBELL_REG_13 = 13 ;
+static const uint8_t P9N2_PU_PSU_HOST_DOORBELL_REG_14 = 14 ;
+static const uint8_t P9N2_PU_PSU_HOST_DOORBELL_REG_15 = 15 ;
+static const uint8_t P9N2_PU_PSU_HOST_DOORBELL_REG_MASK_0 = 16 ;
+static const uint8_t P9N2_PU_PSU_HOST_DOORBELL_REG_MASK_1 = 17 ;
+static const uint8_t P9N2_PU_PSU_HOST_DOORBELL_REG_MASK_2 = 18 ;
+static const uint8_t P9N2_PU_PSU_HOST_DOORBELL_REG_MASK_3 = 19 ;
+static const uint8_t P9N2_PU_PSU_HOST_DOORBELL_REG_MASK_4 = 20 ;
+static const uint8_t P9N2_PU_PSU_HOST_DOORBELL_REG_MASK_5 = 21 ;
+static const uint8_t P9N2_PU_PSU_HOST_DOORBELL_REG_MASK_6 = 22 ;
+static const uint8_t P9N2_PU_PSU_HOST_DOORBELL_REG_MASK_7 = 23 ;
+static const uint8_t P9N2_PU_PSU_HOST_DOORBELL_REG_MASK_8 = 24 ;
+static const uint8_t P9N2_PU_PSU_HOST_DOORBELL_REG_MASK_9 = 25 ;
+static const uint8_t P9N2_PU_PSU_HOST_DOORBELL_REG_MASK_10 = 26 ;
+static const uint8_t P9N2_PU_PSU_HOST_DOORBELL_REG_MASK_11 = 27 ;
+static const uint8_t P9N2_PU_PSU_HOST_DOORBELL_REG_MASK_12 = 28 ;
+static const uint8_t P9N2_PU_PSU_HOST_DOORBELL_REG_MASK_13 = 29 ;
+static const uint8_t P9N2_PU_PSU_HOST_DOORBELL_REG_MASK_14 = 30 ;
+static const uint8_t P9N2_PU_PSU_HOST_DOORBELL_REG_MASK_15 = 31 ;
+
+static const uint8_t P9N2_PU_PSU_HOST_SBE_MBOX0_REG_MBOX0 = 0 ;
+static const uint8_t P9N2_PU_PSU_HOST_SBE_MBOX0_REG_MBOX0_LEN = 64 ;
+
+static const uint8_t P9N2_PU_PSU_HOST_SBE_MBOX1_REG_MBOX1 = 0 ;
+static const uint8_t P9N2_PU_PSU_HOST_SBE_MBOX1_REG_MBOX1_LEN = 64 ;
+
+static const uint8_t P9N2_PU_PSU_HOST_SBE_MBOX2_REG_MBOX2 = 0 ;
+static const uint8_t P9N2_PU_PSU_HOST_SBE_MBOX2_REG_MBOX2_LEN = 64 ;
+
+static const uint8_t P9N2_PU_PSU_HOST_SBE_MBOX3_REG_MBOX3 = 0 ;
+static const uint8_t P9N2_PU_PSU_HOST_SBE_MBOX3_REG_MBOX3_LEN = 64 ;
+
+static const uint8_t P9N2_PU_PSU_HOST_SBE_MBOX4_REG_MBOX4 = 0 ;
+static const uint8_t P9N2_PU_PSU_HOST_SBE_MBOX4_REG_MBOX4_LEN = 64 ;
+
+static const uint8_t P9N2_PU_PSU_HOST_SBE_MBOX5_REG_MBOX5 = 0 ;
+static const uint8_t P9N2_PU_PSU_HOST_SBE_MBOX5_REG_MBOX5_LEN = 64 ;
+
+static const uint8_t P9N2_PU_PSU_HOST_SBE_MBOX6_REG_MBOX6 = 0 ;
+static const uint8_t P9N2_PU_PSU_HOST_SBE_MBOX6_REG_MBOX6_LEN = 64 ;
+
+static const uint8_t P9N2_PU_PSU_HOST_SBE_MBOX7_REG_MBOX7 = 0 ;
+static const uint8_t P9N2_PU_PSU_HOST_SBE_MBOX7_REG_MBOX7_LEN = 64 ;
+
+static const uint8_t P9N2_PU_PSU_INSTR0_ACTCYCLECNT_REG_ACTCYCLECNT = 0 ;
+static const uint8_t P9N2_PU_PSU_INSTR0_ACTCYCLECNT_REG_ACTCYCLECNT_LEN = 40 ;
+
+static const uint8_t P9N2_PU_PSU_INSTR0_CYCLECNT_REG_CYCLECNT = 0 ;
+static const uint8_t P9N2_PU_PSU_INSTR0_CYCLECNT_REG_CYCLECNT_LEN = 40 ;
+
+static const uint8_t P9N2_PU_PSU_INSTR0_EVENTCNT_REG_EVENTCNT = 0 ;
+static const uint8_t P9N2_PU_PSU_INSTR0_EVENTCNT_REG_EVENTCNT_LEN = 16 ;
+
+static const uint8_t P9N2_PU_PSU_INSTR0_FILTER_REG_CONTENT = 0 ;
+static const uint8_t P9N2_PU_PSU_INSTR0_FILTER_REG_CONTENT_LEN = 32 ;
+static const uint8_t P9N2_PU_PSU_INSTR0_FILTER_REG_MASK = 32 ;
+static const uint8_t P9N2_PU_PSU_INSTR0_FILTER_REG_MASK_LEN = 32 ;
+
+static const uint8_t P9N2_PU_PSU_INSTR0_MAXCYCLECNT_REG_MAXCYCLECNT = 0 ;
+static const uint8_t P9N2_PU_PSU_INSTR0_MAXCYCLECNT_REG_MAXCYCLECNT_LEN = 40 ;
+
+static const uint8_t P9N2_PU_PSU_INSTR0_MINCYCLECNT_REG_MINCYCLECNT = 0 ;
+static const uint8_t P9N2_PU_PSU_INSTR0_MINCYCLECNT_REG_MINCYCLECNT_LEN = 40 ;
+
+static const uint8_t P9N2_PU_PSU_INSTR0_STOP_TIMER_REG_TIMER = 0 ;
+static const uint8_t P9N2_PU_PSU_INSTR0_STOP_TIMER_REG_TIMER_LEN = 40 ;
+
+static const uint8_t P9N2_PU_PSU_INSTR1_ACTCYCLECNT_REG_ACTCYCLECNT = 0 ;
+static const uint8_t P9N2_PU_PSU_INSTR1_ACTCYCLECNT_REG_ACTCYCLECNT_LEN = 40 ;
+
+static const uint8_t P9N2_PU_PSU_INSTR1_CYCLECNT_REG_CYCLECNT = 0 ;
+static const uint8_t P9N2_PU_PSU_INSTR1_CYCLECNT_REG_CYCLECNT_LEN = 40 ;
+
+static const uint8_t P9N2_PU_PSU_INSTR1_EVENTCNT_REG_EVENTCNT = 0 ;
+static const uint8_t P9N2_PU_PSU_INSTR1_EVENTCNT_REG_EVENTCNT_LEN = 16 ;
+
+static const uint8_t P9N2_PU_PSU_INSTR1_FILTER_REG_CONTENT = 0 ;
+static const uint8_t P9N2_PU_PSU_INSTR1_FILTER_REG_CONTENT_LEN = 32 ;
+static const uint8_t P9N2_PU_PSU_INSTR1_FILTER_REG_MASK = 32 ;
+static const uint8_t P9N2_PU_PSU_INSTR1_FILTER_REG_MASK_LEN = 32 ;
+
+static const uint8_t P9N2_PU_PSU_INSTR1_MAXCYCLECNT_REG_MAXCYCLECNT = 0 ;
+static const uint8_t P9N2_PU_PSU_INSTR1_MAXCYCLECNT_REG_MAXCYCLECNT_LEN = 40 ;
+
+static const uint8_t P9N2_PU_PSU_INSTR1_MINCYCLECNT_REG_MINCYCLECNT = 0 ;
+static const uint8_t P9N2_PU_PSU_INSTR1_MINCYCLECNT_REG_MINCYCLECNT_LEN = 40 ;
+
+static const uint8_t P9N2_PU_PSU_INSTR1_STOP_TIMER_REG_TIMER = 0 ;
+static const uint8_t P9N2_PU_PSU_INSTR1_STOP_TIMER_REG_TIMER_LEN = 40 ;
+
+static const uint8_t P9N2_PU_PSU_INSTR2_ACTCYCLECNT_REG_ACTCYCLECNT = 0 ;
+static const uint8_t P9N2_PU_PSU_INSTR2_ACTCYCLECNT_REG_ACTCYCLECNT_LEN = 40 ;
+
+static const uint8_t P9N2_PU_PSU_INSTR2_CYCLECNT_REG_CYCLECNT = 0 ;
+static const uint8_t P9N2_PU_PSU_INSTR2_CYCLECNT_REG_CYCLECNT_LEN = 40 ;
+
+static const uint8_t P9N2_PU_PSU_INSTR2_EVENTCNT_REG_EVENTCNT = 0 ;
+static const uint8_t P9N2_PU_PSU_INSTR2_EVENTCNT_REG_EVENTCNT_LEN = 16 ;
+
+static const uint8_t P9N2_PU_PSU_INSTR2_FILTER_REG_CONTENT = 0 ;
+static const uint8_t P9N2_PU_PSU_INSTR2_FILTER_REG_CONTENT_LEN = 32 ;
+static const uint8_t P9N2_PU_PSU_INSTR2_FILTER_REG_MASK = 32 ;
+static const uint8_t P9N2_PU_PSU_INSTR2_FILTER_REG_MASK_LEN = 32 ;
+
+static const uint8_t P9N2_PU_PSU_INSTR2_MAXCYCLECNT_REG_MAXCYCLECNT = 0 ;
+static const uint8_t P9N2_PU_PSU_INSTR2_MAXCYCLECNT_REG_MAXCYCLECNT_LEN = 40 ;
+
+static const uint8_t P9N2_PU_PSU_INSTR2_MINCYCLECNT_REG_MINCYCLECNT = 0 ;
+static const uint8_t P9N2_PU_PSU_INSTR2_MINCYCLECNT_REG_MINCYCLECNT_LEN = 40 ;
+
+static const uint8_t P9N2_PU_PSU_INSTR2_STOP_TIMER_REG_TIMER = 0 ;
+static const uint8_t P9N2_PU_PSU_INSTR2_STOP_TIMER_REG_TIMER_LEN = 40 ;
+
+static const uint8_t P9N2_PU_PSU_INSTR_CTRL_STATUS_REG_INSTR0_MODE = 0 ;
+static const uint8_t P9N2_PU_PSU_INSTR_CTRL_STATUS_REG_INSTR0_MODE_LEN = 2 ;
+static const uint8_t P9N2_PU_PSU_INSTR_CTRL_STATUS_REG_INSTR0_STOP_TIMER_EN = 2 ;
+static const uint8_t P9N2_PU_PSU_INSTR_CTRL_STATUS_REG_INSTR0_STOP_ON_ERROR_GT = 3 ;
+static const uint8_t P9N2_PU_PSU_INSTR_CTRL_STATUS_REG_INSTR0_STOP_ON_ERROR_GT_LEN = 3 ;
+static const uint8_t P9N2_PU_PSU_INSTR_CTRL_STATUS_REG_INSTR0_START = 6 ;
+static const uint8_t P9N2_PU_PSU_INSTR_CTRL_STATUS_REG_INSTR0_STOP = 7 ;
+static const uint8_t P9N2_PU_PSU_INSTR_CTRL_STATUS_REG_INSTR1_MODE = 8 ;
+static const uint8_t P9N2_PU_PSU_INSTR_CTRL_STATUS_REG_INSTR1_MODE_LEN = 2 ;
+static const uint8_t P9N2_PU_PSU_INSTR_CTRL_STATUS_REG_INSTR1_STOP_TIMER_EN = 10 ;
+static const uint8_t P9N2_PU_PSU_INSTR_CTRL_STATUS_REG_INSTR1_STOP_ON_ERROR_GT = 11 ;
+static const uint8_t P9N2_PU_PSU_INSTR_CTRL_STATUS_REG_INSTR1_STOP_ON_ERROR_GT_LEN = 3 ;
+static const uint8_t P9N2_PU_PSU_INSTR_CTRL_STATUS_REG_INSTR1_START = 14 ;
+static const uint8_t P9N2_PU_PSU_INSTR_CTRL_STATUS_REG_INSTR1_STOP = 15 ;
+static const uint8_t P9N2_PU_PSU_INSTR_CTRL_STATUS_REG_INSTR2_MODE = 16 ;
+static const uint8_t P9N2_PU_PSU_INSTR_CTRL_STATUS_REG_INSTR2_MODE_LEN = 2 ;
+static const uint8_t P9N2_PU_PSU_INSTR_CTRL_STATUS_REG_INSTR2_STOP_TIMER_EN = 18 ;
+static const uint8_t P9N2_PU_PSU_INSTR_CTRL_STATUS_REG_INSTR2_STOP_ON_ERROR_GT = 19 ;
+static const uint8_t P9N2_PU_PSU_INSTR_CTRL_STATUS_REG_INSTR2_STOP_ON_ERROR_GT_LEN = 3 ;
+static const uint8_t P9N2_PU_PSU_INSTR_CTRL_STATUS_REG_INSTR2_START = 22 ;
+static const uint8_t P9N2_PU_PSU_INSTR_CTRL_STATUS_REG_INSTR2_STOP = 23 ;
+static const uint8_t P9N2_PU_PSU_INSTR_CTRL_STATUS_REG_INSTR0_CYCLECNT_RUNNING = 24 ;
+static const uint8_t P9N2_PU_PSU_INSTR_CTRL_STATUS_REG_INSTR0_BUSYCNT_RUNNING = 25 ;
+static const uint8_t P9N2_PU_PSU_INSTR_CTRL_STATUS_REG_INSTR1_CYCLECNT_RUNNING = 26 ;
+static const uint8_t P9N2_PU_PSU_INSTR_CTRL_STATUS_REG_INSTR1_BUSYCNT_RUNNING = 27 ;
+static const uint8_t P9N2_PU_PSU_INSTR_CTRL_STATUS_REG_INSTR2_CYCLECNT_RUNNING = 28 ;
+static const uint8_t P9N2_PU_PSU_INSTR_CTRL_STATUS_REG_INSTR2_BUSYCNT_RUNNING = 29 ;
+static const uint8_t P9N2_PU_PSU_INSTR_CTRL_STATUS_REG_INSTR0_STOPPED_ON_ERROR = 30 ;
+static const uint8_t P9N2_PU_PSU_INSTR_CTRL_STATUS_REG_INSTR1_STOPPED_ON_ERROR = 31 ;
+static const uint8_t P9N2_PU_PSU_INSTR_CTRL_STATUS_REG_INSTR2_STOPPED_ON_ERROR = 32 ;
+static const uint8_t P9N2_PU_PSU_INSTR_CTRL_STATUS_REG_INSTR0_RESET = 33 ;
+static const uint8_t P9N2_PU_PSU_INSTR_CTRL_STATUS_REG_INSTR1_RESET = 34 ;
+static const uint8_t P9N2_PU_PSU_INSTR_CTRL_STATUS_REG_INSTR2_RESET = 35 ;
+static const uint8_t P9N2_PU_PSU_INSTR_CTRL_STATUS_REG_INCLUDE_TRAFFIC = 36 ;
+static const uint8_t P9N2_PU_PSU_INSTR_CTRL_STATUS_REG_RESERVED = 37 ;
+static const uint8_t P9N2_PU_PSU_INSTR_CTRL_STATUS_REG_RESERVED_LEN = 3 ;
+
+static const uint8_t P9N2_PU_PSU_PIBHIST_2NDLAST_ADDR_TRACE_REG_HIST = 0 ;
+static const uint8_t P9N2_PU_PSU_PIBHIST_2NDLAST_ADDR_TRACE_REG_HIST_LEN = 64 ;
+
+static const uint8_t P9N2_PU_PSU_PIBHIST_2NDLAST_REQDATA_TRACE_REG_HIST = 0 ;
+static const uint8_t P9N2_PU_PSU_PIBHIST_2NDLAST_REQDATA_TRACE_REG_HIST_LEN = 64 ;
+
+static const uint8_t P9N2_PU_PSU_PIBHIST_2NDLAST_RSPDATA_TRACE_REG_HIST = 0 ;
+static const uint8_t P9N2_PU_PSU_PIBHIST_2NDLAST_RSPDATA_TRACE_REG_HIST_LEN = 64 ;
+
+static const uint8_t P9N2_PU_PSU_PIBHIST_CTRL_STATUS_REG_HIST_MANUAL_MODE_EN = 0 ;
+static const uint8_t P9N2_PU_PSU_PIBHIST_CTRL_STATUS_REG_HIST_START_NOT_STOP = 1 ;
+static const uint8_t P9N2_PU_PSU_PIBHIST_CTRL_STATUS_REG_HIST_FREEZE_HISTORY = 2 ;
+static const uint8_t P9N2_PU_PSU_PIBHIST_CTRL_STATUS_REG_HIST_RESET_HISTORY = 3 ;
+static const uint8_t P9N2_PU_PSU_PIBHIST_CTRL_STATUS_REG_HIST_TRACE_TRAFFIC = 4 ;
+static const uint8_t P9N2_PU_PSU_PIBHIST_CTRL_STATUS_REG_HIST_STOP_ON_ERROR_GT = 5 ;
+static const uint8_t P9N2_PU_PSU_PIBHIST_CTRL_STATUS_REG_HIST_STOP_ON_ERROR_GT_LEN = 3 ;
+static const uint8_t P9N2_PU_PSU_PIBHIST_CTRL_STATUS_REG_HIST_FILTER_RD_NOT_WR = 8 ;
+static const uint8_t P9N2_PU_PSU_PIBHIST_CTRL_STATUS_REG_HIST_FILTER_MASK_RD_NOT_WR = 9 ;
+static const uint8_t P9N2_PU_PSU_PIBHIST_CTRL_STATUS_REG_HIST_RESERVED = 10 ;
+static const uint8_t P9N2_PU_PSU_PIBHIST_CTRL_STATUS_REG_HIST_RESERVED_LEN = 6 ;
+
+static const uint8_t P9N2_PU_PSU_PIBHIST_FILTER_REG_HIST_ADDRESS = 0 ;
+static const uint8_t P9N2_PU_PSU_PIBHIST_FILTER_REG_HIST_ADDRESS_LEN = 32 ;
+static const uint8_t P9N2_PU_PSU_PIBHIST_FILTER_REG_HIST_MASK = 32 ;
+static const uint8_t P9N2_PU_PSU_PIBHIST_FILTER_REG_HIST_MASK_LEN = 32 ;
+
+static const uint8_t P9N2_PU_PSU_PIBHIST_LAST_ADDR_TRACE_REG_HIST = 0 ;
+static const uint8_t P9N2_PU_PSU_PIBHIST_LAST_ADDR_TRACE_REG_HIST_LEN = 64 ;
+
+static const uint8_t P9N2_PU_PSU_PIBHIST_LAST_REQDATA_TRACE_REG_HIST = 0 ;
+static const uint8_t P9N2_PU_PSU_PIBHIST_LAST_REQDATA_TRACE_REG_HIST_LEN = 64 ;
+
+static const uint8_t P9N2_PU_PSU_PIBHIST_LAST_RSPDATA_TRACE_REG_HIST = 0 ;
+static const uint8_t P9N2_PU_PSU_PIBHIST_LAST_RSPDATA_TRACE_REG_HIST_LEN = 64 ;
+
+static const uint8_t P9N2_PU_PSU_SBE_DOORBELL_REG_0 = 0 ;
+static const uint8_t P9N2_PU_PSU_SBE_DOORBELL_REG_1 = 1 ;
+static const uint8_t P9N2_PU_PSU_SBE_DOORBELL_REG_2 = 2 ;
+static const uint8_t P9N2_PU_PSU_SBE_DOORBELL_REG_3 = 3 ;
+static const uint8_t P9N2_PU_PSU_SBE_DOORBELL_REG_4 = 4 ;
+static const uint8_t P9N2_PU_PSU_SBE_DOORBELL_REG_5 = 5 ;
+static const uint8_t P9N2_PU_PSU_SBE_DOORBELL_REG_6 = 6 ;
+static const uint8_t P9N2_PU_PSU_SBE_DOORBELL_REG_7 = 7 ;
+static const uint8_t P9N2_PU_PSU_SBE_DOORBELL_REG_8 = 8 ;
+static const uint8_t P9N2_PU_PSU_SBE_DOORBELL_REG_9 = 9 ;
+static const uint8_t P9N2_PU_PSU_SBE_DOORBELL_REG_10 = 10 ;
+static const uint8_t P9N2_PU_PSU_SBE_DOORBELL_REG_11 = 11 ;
+static const uint8_t P9N2_PU_PSU_SBE_DOORBELL_REG_12 = 12 ;
+static const uint8_t P9N2_PU_PSU_SBE_DOORBELL_REG_13 = 13 ;
+static const uint8_t P9N2_PU_PSU_SBE_DOORBELL_REG_14 = 14 ;
+static const uint8_t P9N2_PU_PSU_SBE_DOORBELL_REG_15 = 15 ;
+static const uint8_t P9N2_PU_PSU_SBE_DOORBELL_REG_MASK_0 = 16 ;
+static const uint8_t P9N2_PU_PSU_SBE_DOORBELL_REG_MASK_1 = 17 ;
+static const uint8_t P9N2_PU_PSU_SBE_DOORBELL_REG_MASK_2 = 18 ;
+static const uint8_t P9N2_PU_PSU_SBE_DOORBELL_REG_MASK_3 = 19 ;
+static const uint8_t P9N2_PU_PSU_SBE_DOORBELL_REG_MASK_4 = 20 ;
+static const uint8_t P9N2_PU_PSU_SBE_DOORBELL_REG_MASK_5 = 21 ;
+static const uint8_t P9N2_PU_PSU_SBE_DOORBELL_REG_MASK_6 = 22 ;
+static const uint8_t P9N2_PU_PSU_SBE_DOORBELL_REG_MASK_7 = 23 ;
+static const uint8_t P9N2_PU_PSU_SBE_DOORBELL_REG_MASK_8 = 24 ;
+static const uint8_t P9N2_PU_PSU_SBE_DOORBELL_REG_MASK_9 = 25 ;
+static const uint8_t P9N2_PU_PSU_SBE_DOORBELL_REG_MASK_10 = 26 ;
+static const uint8_t P9N2_PU_PSU_SBE_DOORBELL_REG_MASK_11 = 27 ;
+static const uint8_t P9N2_PU_PSU_SBE_DOORBELL_REG_MASK_12 = 28 ;
+static const uint8_t P9N2_PU_PSU_SBE_DOORBELL_REG_MASK_13 = 29 ;
+static const uint8_t P9N2_PU_PSU_SBE_DOORBELL_REG_MASK_14 = 30 ;
+static const uint8_t P9N2_PU_PSU_SBE_DOORBELL_REG_MASK_15 = 31 ;
+
+static const uint8_t P9N2_PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP0 = 0 ;
+static const uint8_t P9N2_PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP0_LEN = 8 ;
+static const uint8_t P9N2_PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP1 = 8 ;
+static const uint8_t P9N2_PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP1_LEN = 8 ;
+static const uint8_t P9N2_PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP2 = 16 ;
+static const uint8_t P9N2_PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP2_LEN = 8 ;
+static const uint8_t P9N2_PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP3 = 24 ;
+static const uint8_t P9N2_PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP3_LEN = 8 ;
+static const uint8_t P9N2_PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP4 = 32 ;
+static const uint8_t P9N2_PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP4_LEN = 8 ;
+static const uint8_t P9N2_PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP5 = 40 ;
+static const uint8_t P9N2_PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP5_LEN = 8 ;
+static const uint8_t P9N2_PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP6 = 48 ;
+static const uint8_t P9N2_PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP6_LEN = 8 ;
+static const uint8_t P9N2_PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP7 = 56 ;
+static const uint8_t P9N2_PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP7_LEN = 8 ;
+
+static const uint8_t P9N2_PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP8 = 0 ;
+static const uint8_t P9N2_PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP8_LEN = 8 ;
+static const uint8_t P9N2_PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP9 = 8 ;
+static const uint8_t P9N2_PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP9_LEN = 8 ;
+static const uint8_t P9N2_PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP10 = 16 ;
+static const uint8_t P9N2_PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP10_LEN = 8 ;
+static const uint8_t P9N2_PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP11 = 24 ;
+static const uint8_t P9N2_PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP11_LEN = 8 ;
+static const uint8_t P9N2_PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP12 = 32 ;
+static const uint8_t P9N2_PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP12_LEN = 8 ;
+static const uint8_t P9N2_PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP13 = 40 ;
+static const uint8_t P9N2_PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP13_LEN = 8 ;
+static const uint8_t P9N2_PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP14 = 48 ;
+static const uint8_t P9N2_PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP14_LEN = 8 ;
+static const uint8_t P9N2_PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP15 = 56 ;
+static const uint8_t P9N2_PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP15_LEN = 8 ;
+
+static const uint8_t P9N2_PEC_RECOV_INTERRUPT_REG_RECOV = 0 ;
+
+static const uint8_t P9N2_PU_NPU2_NTL1_REM0_IBUF_WSRC = 17 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_REM0_IBUF_WSRC_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_REM0_IBUF_RSRC = 22 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_REM0_IBUF_RSRC_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_REM0_IBUF_AIDX = 24 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_REM0_IBUF_AIDX_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_REM0_IBUF_ABANK = 32 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_REM0_IBUF_ABANK_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_REM0_OBUF_WSRC = 34 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_REM0_OBUF_WSRC_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_REM0_OBUF_RSRC = 36 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_REM0_OBUF_RSRC_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_REM0_OBUF_AIDX = 42 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_REM0_OBUF_AIDX_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_REM0_OBUF_ABANK = 50 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_REM0_OBUF_ABANK_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_REM0_BBUF_WSRC = 52 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_REM0_BBUF_WSRC_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_REM0_BBUF_RSRC = 54 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_REM0_BBUF_RSRC_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_REM0_BBUF_AIDX = 56 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_REM0_BBUF_AIDX_LEN = 8 ;
+
+static const uint8_t P9N2_PU_NPU2_NTL1_REM1_PBRX_RTAG = 34 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_REM1_PBRX_RTAG_LEN = 22 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_REM1_ALU_ADR = 56 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_REM1_ALU_ADR_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_REM1_ALU_TYPE = 59 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_REM1_ALU_TYPE_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_REM1_ALU_SZ = 63 ;
+
+static const uint8_t P9N2_PU_RESET_REGISTER_CHICKEN_SWITCH = 0 ;
+
+static const uint8_t P9N2_PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_B_RESID_FE_LEN_0 = 0 ;
+static const uint8_t P9N2_PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_B_RESID_FE_LEN_0_LEN = 16 ;
+static const uint8_t P9N2_PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_B_PEEK_DATA1_0 = 32 ;
+static const uint8_t P9N2_PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_B_PEEK_DATA1_0_LEN = 8 ;
+static const uint8_t P9N2_PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_B_LBUS_PARITY_ERR1_0 = 40 ;
+
+static const uint8_t P9N2_PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_C_RESID_FE_LEN_1 = 0 ;
+static const uint8_t P9N2_PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_C_RESID_FE_LEN_1_LEN = 16 ;
+static const uint8_t P9N2_PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_C_PEEK_DATA1_1 = 32 ;
+static const uint8_t P9N2_PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_C_PEEK_DATA1_1_LEN = 8 ;
+static const uint8_t P9N2_PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_C_LBUS_PARITY_ERR1_1 = 40 ;
+
+static const uint8_t P9N2_PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_D_RESID_FE_LEN_2 = 0 ;
+static const uint8_t P9N2_PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_D_RESID_FE_LEN_2_LEN = 16 ;
+static const uint8_t P9N2_PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_D_PEEK_DATA1_2 = 32 ;
+static const uint8_t P9N2_PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_D_PEEK_DATA1_2_LEN = 8 ;
+static const uint8_t P9N2_PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_D_LBUS_PARITY_ERR1_2 = 40 ;
+
+static const uint8_t P9N2_PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_E_RESID_FE_LEN_3 = 0 ;
+static const uint8_t P9N2_PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_E_RESID_FE_LEN_3_LEN = 16 ;
+static const uint8_t P9N2_PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_E_PEEK_DATA1_3 = 32 ;
+static const uint8_t P9N2_PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_E_PEEK_DATA1_3_LEN = 8 ;
+static const uint8_t P9N2_PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_E_LBUS_PARITY_ERR1_3 = 40 ;
+
+static const uint8_t P9N2_PEC_RFIR_IN0 = 0 ;
+static const uint8_t P9N2_PEC_RFIR_LFIR_RECOV_ERR = 1 ;
+static const uint8_t P9N2_PEC_RFIR_IN4 = 2 ;
+static const uint8_t P9N2_PEC_RFIR_IN5 = 3 ;
+static const uint8_t P9N2_PEC_RFIR_IN6 = 4 ;
+static const uint8_t P9N2_PEC_RFIR_IN7 = 5 ;
+static const uint8_t P9N2_PEC_RFIR_IN7_LEN = 19 ;
+
+static const uint8_t P9N2_PU_N3_RING_FENCE_MASK_LATCH_REG_ENABLE = 1 ;
+static const uint8_t P9N2_PU_N3_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN = 15 ;
+
+static const uint8_t P9N2_PU_N1_RING_FENCE_MASK_LATCH_REG_ENABLE = 1 ;
+static const uint8_t P9N2_PU_N1_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN = 15 ;
+
+static const uint8_t P9N2_PU_RING_FENCE_MASK_LATCH_REG_ENABLE = 1 ;
+static const uint8_t P9N2_PU_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN = 15 ;
+
+static const uint8_t P9N2_PU_N2_RING_FENCE_MASK_LATCH_REG_ENABLE = 1 ;
+static const uint8_t P9N2_PU_N2_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN = 15 ;
+
+static const uint8_t P9N2_PEC_RING_FENCE_MASK_LATCH_REG_ENABLE = 1 ;
+static const uint8_t P9N2_PEC_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN = 15 ;
+
+static const uint8_t P9N2_PU_N0_RING_FENCE_MASK_LATCH_REG_ENABLE = 1 ;
+static const uint8_t P9N2_PU_N0_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN = 15 ;
+
+static const uint8_t P9N2__CTL_RLX_CONFIG_BRK0_CLUSTER = 0 ;
+static const uint8_t P9N2__CTL_RLX_CONFIG_BRK0_CLUSTER_LEN = 3 ;
+static const uint8_t P9N2__CTL_RLX_CONFIG_BRK1_CLUSTER = 3 ;
+static const uint8_t P9N2__CTL_RLX_CONFIG_BRK1_CLUSTER_LEN = 3 ;
+static const uint8_t P9N2__CTL_RLX_CONFIG_BRK2_CLUSTER = 6 ;
+static const uint8_t P9N2__CTL_RLX_CONFIG_BRK2_CLUSTER_LEN = 3 ;
+static const uint8_t P9N2__CTL_RLX_CONFIG_BRK3_CLUSTER = 9 ;
+static const uint8_t P9N2__CTL_RLX_CONFIG_BRK3_CLUSTER_LEN = 3 ;
+static const uint8_t P9N2__CTL_RLX_CONFIG_BRK4_CLUSTER = 12 ;
+static const uint8_t P9N2__CTL_RLX_CONFIG_BRK4_CLUSTER_LEN = 3 ;
+static const uint8_t P9N2__CTL_RLX_CONFIG_BRK5_CLUSTER = 15 ;
+static const uint8_t P9N2__CTL_RLX_CONFIG_BRK5_CLUSTER_LEN = 3 ;
+static const uint8_t P9N2__CTL_RLX_CONFIG_RESERVED1 = 18 ;
+static const uint8_t P9N2__CTL_RLX_CONFIG_RESERVED1_LEN = 2 ;
+static const uint8_t P9N2__CTL_RLX_CONFIG_SYNC_BRK = 20 ;
+static const uint8_t P9N2__CTL_RLX_CONFIG_SYNC_BRK_LEN = 6 ;
+static const uint8_t P9N2__CTL_RLX_CONFIG_IDIAL_ISSYNC = 26 ;
+static const uint8_t P9N2__CTL_RLX_CONFIG_IDIAL_ISSYNC_LEN = 6 ;
+
+static const uint8_t P9N2_PU_RNG_FAILED_INT_ENABLE = 0 ;
+static const uint8_t P9N2_PU_RNG_FAILED_INT_ADDRESS = 8 ;
+static const uint8_t P9N2_PU_RNG_FAILED_INT_ADDRESS_LEN = 44 ;
+
+static const uint8_t P9N2_PU_NPU1_SM1_RSP_DA_PTR_RESERVED1 = 0 ;
+static const uint8_t P9N2_PU_NPU1_SM1_RSP_DA_PTR_RESERVED1_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU1_SM1_RSP_DA_PTR_START = 3 ;
+static const uint8_t P9N2_PU_NPU1_SM1_RSP_DA_PTR_START_LEN = 9 ;
+static const uint8_t P9N2_PU_NPU1_SM1_RSP_DA_PTR_RESERVED2 = 12 ;
+static const uint8_t P9N2_PU_NPU1_SM1_RSP_DA_PTR_RESERVED2_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU1_SM1_RSP_DA_PTR_END = 15 ;
+static const uint8_t P9N2_PU_NPU1_SM1_RSP_DA_PTR_END_LEN = 9 ;
+
+static const uint8_t P9N2_PU_NPU_SM2_RSP_DA_PTR_RESERVED1 = 0 ;
+static const uint8_t P9N2_PU_NPU_SM2_RSP_DA_PTR_RESERVED1_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_SM2_RSP_DA_PTR_START = 3 ;
+static const uint8_t P9N2_PU_NPU_SM2_RSP_DA_PTR_START_LEN = 9 ;
+static const uint8_t P9N2_PU_NPU_SM2_RSP_DA_PTR_RESERVED2 = 12 ;
+static const uint8_t P9N2_PU_NPU_SM2_RSP_DA_PTR_RESERVED2_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_SM2_RSP_DA_PTR_END = 15 ;
+static const uint8_t P9N2_PU_NPU_SM2_RSP_DA_PTR_END_LEN = 9 ;
+
+static const uint8_t P9N2_PU_NPU1_SM2_RSP_DA_PTR_RESERVED1 = 0 ;
+static const uint8_t P9N2_PU_NPU1_SM2_RSP_DA_PTR_RESERVED1_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU1_SM2_RSP_DA_PTR_START = 3 ;
+static const uint8_t P9N2_PU_NPU1_SM2_RSP_DA_PTR_START_LEN = 9 ;
+static const uint8_t P9N2_PU_NPU1_SM2_RSP_DA_PTR_RESERVED2 = 12 ;
+static const uint8_t P9N2_PU_NPU1_SM2_RSP_DA_PTR_RESERVED2_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU1_SM2_RSP_DA_PTR_END = 15 ;
+static const uint8_t P9N2_PU_NPU1_SM2_RSP_DA_PTR_END_LEN = 9 ;
+
+static const uint8_t P9N2_PU_NPU_SM1_RSP_DA_PTR_RESERVED1 = 0 ;
+static const uint8_t P9N2_PU_NPU_SM1_RSP_DA_PTR_RESERVED1_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_SM1_RSP_DA_PTR_START = 3 ;
+static const uint8_t P9N2_PU_NPU_SM1_RSP_DA_PTR_START_LEN = 9 ;
+static const uint8_t P9N2_PU_NPU_SM1_RSP_DA_PTR_RESERVED2 = 12 ;
+static const uint8_t P9N2_PU_NPU_SM1_RSP_DA_PTR_RESERVED2_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_SM1_RSP_DA_PTR_END = 15 ;
+static const uint8_t P9N2_PU_NPU_SM1_RSP_DA_PTR_END_LEN = 9 ;
+
+static const uint8_t P9N2__SM2_RSP_DA_PTR_RESERVED1 = 0 ;
+static const uint8_t P9N2__SM2_RSP_DA_PTR_RESERVED1_LEN = 3 ;
+static const uint8_t P9N2__SM2_RSP_DA_PTR_START = 3 ;
+static const uint8_t P9N2__SM2_RSP_DA_PTR_START_LEN = 9 ;
+static const uint8_t P9N2__SM2_RSP_DA_PTR_RESERVED2 = 12 ;
+static const uint8_t P9N2__SM2_RSP_DA_PTR_RESERVED2_LEN = 3 ;
+static const uint8_t P9N2__SM2_RSP_DA_PTR_END = 15 ;
+static const uint8_t P9N2__SM2_RSP_DA_PTR_END_LEN = 9 ;
+
+static const uint8_t P9N2__SM1_RSP_DA_PTR_RESERVED1 = 0 ;
+static const uint8_t P9N2__SM1_RSP_DA_PTR_RESERVED1_LEN = 3 ;
+static const uint8_t P9N2__SM1_RSP_DA_PTR_START = 3 ;
+static const uint8_t P9N2__SM1_RSP_DA_PTR_START_LEN = 9 ;
+static const uint8_t P9N2__SM1_RSP_DA_PTR_RESERVED2 = 12 ;
+static const uint8_t P9N2__SM1_RSP_DA_PTR_RESERVED2_LEN = 3 ;
+static const uint8_t P9N2__SM1_RSP_DA_PTR_END = 15 ;
+static const uint8_t P9N2__SM1_RSP_DA_PTR_END_LEN = 9 ;
+
+static const uint8_t P9N2_PU_NPU1_SM1_RSP_HA_PTR_RESERVED1 = 0 ;
+static const uint8_t P9N2_PU_NPU1_SM1_RSP_HA_PTR_RESERVED1_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM1_RSP_HA_PTR_START = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM1_RSP_HA_PTR_START_LEN = 7 ;
+static const uint8_t P9N2_PU_NPU1_SM1_RSP_HA_PTR_RESERVED2 = 12 ;
+static const uint8_t P9N2_PU_NPU1_SM1_RSP_HA_PTR_RESERVED2_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM1_RSP_HA_PTR_END = 17 ;
+static const uint8_t P9N2_PU_NPU1_SM1_RSP_HA_PTR_END_LEN = 7 ;
+
+static const uint8_t P9N2_PU_NPU_SM2_RSP_HA_PTR_RESERVED1 = 0 ;
+static const uint8_t P9N2_PU_NPU_SM2_RSP_HA_PTR_RESERVED1_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM2_RSP_HA_PTR_START = 5 ;
+static const uint8_t P9N2_PU_NPU_SM2_RSP_HA_PTR_START_LEN = 7 ;
+static const uint8_t P9N2_PU_NPU_SM2_RSP_HA_PTR_RESERVED2 = 12 ;
+static const uint8_t P9N2_PU_NPU_SM2_RSP_HA_PTR_RESERVED2_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM2_RSP_HA_PTR_END = 17 ;
+static const uint8_t P9N2_PU_NPU_SM2_RSP_HA_PTR_END_LEN = 7 ;
+
+static const uint8_t P9N2_PU_NPU1_SM2_RSP_HA_PTR_RESERVED1 = 0 ;
+static const uint8_t P9N2_PU_NPU1_SM2_RSP_HA_PTR_RESERVED1_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM2_RSP_HA_PTR_START = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM2_RSP_HA_PTR_START_LEN = 7 ;
+static const uint8_t P9N2_PU_NPU1_SM2_RSP_HA_PTR_RESERVED2 = 12 ;
+static const uint8_t P9N2_PU_NPU1_SM2_RSP_HA_PTR_RESERVED2_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU1_SM2_RSP_HA_PTR_END = 17 ;
+static const uint8_t P9N2_PU_NPU1_SM2_RSP_HA_PTR_END_LEN = 7 ;
+
+static const uint8_t P9N2_PU_NPU_SM1_RSP_HA_PTR_RESERVED1 = 0 ;
+static const uint8_t P9N2_PU_NPU_SM1_RSP_HA_PTR_RESERVED1_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM1_RSP_HA_PTR_START = 5 ;
+static const uint8_t P9N2_PU_NPU_SM1_RSP_HA_PTR_START_LEN = 7 ;
+static const uint8_t P9N2_PU_NPU_SM1_RSP_HA_PTR_RESERVED2 = 12 ;
+static const uint8_t P9N2_PU_NPU_SM1_RSP_HA_PTR_RESERVED2_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_SM1_RSP_HA_PTR_END = 17 ;
+static const uint8_t P9N2_PU_NPU_SM1_RSP_HA_PTR_END_LEN = 7 ;
+
+static const uint8_t P9N2__SM2_RSP_HA_PTR_RESERVED1 = 0 ;
+static const uint8_t P9N2__SM2_RSP_HA_PTR_RESERVED1_LEN = 5 ;
+static const uint8_t P9N2__SM2_RSP_HA_PTR_START = 5 ;
+static const uint8_t P9N2__SM2_RSP_HA_PTR_START_LEN = 7 ;
+static const uint8_t P9N2__SM2_RSP_HA_PTR_RESERVED2 = 12 ;
+static const uint8_t P9N2__SM2_RSP_HA_PTR_RESERVED2_LEN = 5 ;
+static const uint8_t P9N2__SM2_RSP_HA_PTR_END = 17 ;
+static const uint8_t P9N2__SM2_RSP_HA_PTR_END_LEN = 7 ;
+
+static const uint8_t P9N2__SM1_RSP_HA_PTR_RESERVED1 = 0 ;
+static const uint8_t P9N2__SM1_RSP_HA_PTR_RESERVED1_LEN = 5 ;
+static const uint8_t P9N2__SM1_RSP_HA_PTR_START = 5 ;
+static const uint8_t P9N2__SM1_RSP_HA_PTR_START_LEN = 7 ;
+static const uint8_t P9N2__SM1_RSP_HA_PTR_RESERVED2 = 12 ;
+static const uint8_t P9N2__SM1_RSP_HA_PTR_RESERVED2_LEN = 5 ;
+static const uint8_t P9N2__SM1_RSP_HA_PTR_END = 17 ;
+static const uint8_t P9N2__SM1_RSP_HA_PTR_END_LEN = 7 ;
+
+static const uint8_t P9N2_PU_RX_CH_FSM_REG_RX_CH_FSM = 0 ;
+static const uint8_t P9N2_PU_RX_CH_FSM_REG_RX_CH_FSM_LEN = 2 ;
+
+static const uint8_t P9N2_PU_RX_CH_INTADDR_REG_SCOM_MODE_0 = 0 ;
+static const uint8_t P9N2_PU_RX_CH_INTADDR_REG_SCOM_MODE_1 = 1 ;
+static const uint8_t P9N2_PU_RX_CH_INTADDR_REG_SCOM_MODE_2 = 2 ;
+static const uint8_t P9N2_PU_RX_CH_INTADDR_REG_SCOM_MODE_3 = 3 ;
+static const uint8_t P9N2_PU_RX_CH_INTADDR_REG_SCOM_MODE_4 = 4 ;
+static const uint8_t P9N2_PU_RX_CH_INTADDR_REG_SCOM_MODE_5 = 5 ;
+static const uint8_t P9N2_PU_RX_CH_INTADDR_REG_SCOM_MODE_6 = 6 ;
+static const uint8_t P9N2_PU_RX_CH_INTADDR_REG_SCOM_MODE_7 = 7 ;
+
+static const uint8_t P9N2_PU_RX_CH_MISC_REG_FSM0 = 0 ;
+static const uint8_t P9N2_PU_RX_CH_MISC_REG_FSM0_LEN = 3 ;
+static const uint8_t P9N2_PU_RX_CH_MISC_REG_FSM1 = 3 ;
+static const uint8_t P9N2_PU_RX_CH_MISC_REG_FSM1_LEN = 4 ;
+static const uint8_t P9N2_PU_RX_CH_MISC_REG_TFRAMESIZE = 7 ;
+static const uint8_t P9N2_PU_RX_CH_MISC_REG_TFRAMESIZE_LEN = 5 ;
+static const uint8_t P9N2_PU_RX_CH_MISC_REG_WEN0 = 12 ;
+static const uint8_t P9N2_PU_RX_CH_MISC_REG_WEN1 = 13 ;
+static const uint8_t P9N2_PU_RX_CH_MISC_REG_WEN2 = 14 ;
+static const uint8_t P9N2_PU_RX_CH_MISC_REG_EN_SCRD = 15 ;
+static const uint8_t P9N2_PU_RX_CH_MISC_REG_STTRTOGX = 16 ;
+
+static const uint8_t P9N2_PU_RX_CTRL_STAT_REG_ENABLE_SCWR_TO_RXRF = 0 ;
+static const uint8_t P9N2_PU_RX_CTRL_STAT_REG_RXSC = 1 ;
+static const uint8_t P9N2_PU_RX_CTRL_STAT_REG_DISABLE_ECC_COR_RXRF_PSI = 2 ;
+static const uint8_t P9N2_PU_RX_CTRL_STAT_REG_CRC_MODE = 3 ;
+static const uint8_t P9N2_PU_RX_CTRL_STAT_REG_ENABLE_SCRD_FR_RXRF = 4 ;
+static const uint8_t P9N2_PU_RX_CTRL_STAT_REG_ENABLE_STREAMING_MODE = 5 ;
+static const uint8_t P9N2_PU_RX_CTRL_STAT_REG_CHIP_INTERFACEMODE = 6 ;
+static const uint8_t P9N2_PU_RX_CTRL_STAT_REG_CHIP_PERSONALISATION = 7 ;
+
+static const uint8_t P9N2_PU_RX_DBFF_REG0_DATA_BUFF0 = 0 ;
+static const uint8_t P9N2_PU_RX_DBFF_REG0_DATA_BUFF0_LEN = 32 ;
+
+static const uint8_t P9N2_PU_RX_DBFF_REG1_DATA_BUFF1 = 0 ;
+static const uint8_t P9N2_PU_RX_DBFF_REG1_DATA_BUFF1_LEN = 32 ;
+
+static const uint8_t P9N2_PU_RX_DF_FSM_REG_RX_DF_FSM = 0 ;
+static const uint8_t P9N2_PU_RX_DF_FSM_REG_RX_DF_FSM_LEN = 4 ;
+
+static const uint8_t P9N2_PU_RX_ERROR_REG_C1_PSIRXINS_RFGSHIFT_PCK = 0 ;
+static const uint8_t P9N2_PU_RX_ERROR_REG_C1_PSIRXINS_RZRTMP_PCK = 1 ;
+static const uint8_t P9N2_PU_RX_ERROR_REG_C1_PSIRXINS_DATA_PCK = 2 ;
+static const uint8_t P9N2_PU_RX_ERROR_REG_C1_PSIRXEI_SHIFT_PCK = 3 ;
+static const uint8_t P9N2_PU_RX_ERROR_REG_C1_PSIRXEI_TRANSMIT_PCK = 4 ;
+static const uint8_t P9N2_PU_RX_ERROR_REG_C1_PSIRXINS_OVERRUN = 5 ;
+static const uint8_t P9N2_PU_RX_ERROR_REG_C1_PSIRXBFF_DATA_PCK = 6 ;
+static const uint8_t P9N2_PU_RX_ERROR_REG_C2_PSIRXBFF_DATAO_PCK = 7 ;
+static const uint8_t P9N2_PU_RX_ERROR_REG_C2_PSIRXBFF_RFC_PCK = 8 ;
+static const uint8_t P9N2_PU_RX_ERROR_REG_C2_PSIRXLC_FSM_PCK = 9 ;
+static const uint8_t P9N2_PU_RX_ERROR_REG_C3_PSIRXLC_DATA_BUFF_PCK = 10 ;
+static const uint8_t P9N2_PU_RX_ERROR_REG_C2_PSIRXLC_DATA_PCK = 11 ;
+static const uint8_t P9N2_PU_RX_ERROR_REG_C2_PSIRXLC_RADDR_PCK = 12 ;
+static const uint8_t P9N2_PU_RX_ERROR_REG_C2_PSIRXLC_RCTRL_PCK = 13 ;
+static const uint8_t P9N2_PU_RX_ERROR_REG_C3_PSIRXLC_UE_RF = 14 ;
+static const uint8_t P9N2_PU_RX_ERROR_REG_C0_PSIRXLC_CE_RF = 15 ;
+static const uint8_t P9N2_PU_RX_ERROR_REG_C2_PSIRXLC_DATA_GXST1_PCK_2N = 16 ;
+static const uint8_t P9N2_PU_RX_ERROR_REG_C2_PSIRFACC_RADDR_PCK = 17 ;
+static const uint8_t P9N2_PU_RX_ERROR_REG_C2_PSIRFACC_RCTRL_PCK = 18 ;
+static const uint8_t P9N2_PU_RX_ERROR_REG_C3_PSIRFACC_RFSM_PCK = 19 ;
+static const uint8_t P9N2_PU_RX_ERROR_REG_C3_PSIRFACC_RDL_FSM_PCK = 20 ;
+static const uint8_t P9N2_PU_RX_ERROR_REG_C4_PSIRFACC_RXSC_PCK = 21 ;
+static const uint8_t P9N2_PU_RX_ERROR_REG_C0_PSIRFACC_RLINK_STATE_LT_02 = 22 ;
+static const uint8_t P9N2_PU_RX_ERROR_REG_C0_PSIRFACC_C_RXDATA_RDY_ERR = 23 ;
+static const uint8_t P9N2_PU_RX_ERROR_REG_C0_ERRACK_RISE = 24 ;
+
+static const uint8_t P9N2_PU_RX_ERR_MODE_RX_ERR_MODE_0 = 0 ;
+static const uint8_t P9N2_PU_RX_ERR_MODE_RX_ERR_MODE_1 = 1 ;
+
+static const uint8_t P9N2_PU_RX_MASK_REG_PSIRXINS_RFGSHIFT_PCK = 0 ;
+static const uint8_t P9N2_PU_RX_MASK_REG_PSIRXINS_RZRTMP_PCK = 1 ;
+static const uint8_t P9N2_PU_RX_MASK_REG_PSIRXINS_DATA_PCK = 2 ;
+static const uint8_t P9N2_PU_RX_MASK_REG_PSIRXEI_SHIFT_PCK = 3 ;
+static const uint8_t P9N2_PU_RX_MASK_REG_PSIRXEI_TRANSMIT_PCK = 4 ;
+static const uint8_t P9N2_PU_RX_MASK_REG_PSIRXINS_OVERRUN = 5 ;
+static const uint8_t P9N2_PU_RX_MASK_REG_PSIRXBFF_DATA_PCK = 6 ;
+static const uint8_t P9N2_PU_RX_MASK_REG_PSIRXBFF_DATAO_PCK = 7 ;
+static const uint8_t P9N2_PU_RX_MASK_REG_PSIRXBFF_RFC_PCK = 8 ;
+static const uint8_t P9N2_PU_RX_MASK_REG_PSIRXLC_FSM_PCK = 9 ;
+static const uint8_t P9N2_PU_RX_MASK_REG_PSIRXLC_DATA_BUFF_PCK = 10 ;
+static const uint8_t P9N2_PU_RX_MASK_REG_PSIRXLC_DATA_PCK = 11 ;
+static const uint8_t P9N2_PU_RX_MASK_REG_PSIRXLC_RADDR_PCK = 12 ;
+static const uint8_t P9N2_PU_RX_MASK_REG_PSIRXLC_RCTRL_PCK = 13 ;
+static const uint8_t P9N2_PU_RX_MASK_REG_PSIRXLC_UE_RF = 14 ;
+static const uint8_t P9N2_PU_RX_MASK_REG_PSIRXLC_CE_RF = 15 ;
+static const uint8_t P9N2_PU_RX_MASK_REG_PSIRXLC_DATA_GXST1_PCK_2N = 16 ;
+static const uint8_t P9N2_PU_RX_MASK_REG_PSIRFACC_RADDR_PCK = 17 ;
+static const uint8_t P9N2_PU_RX_MASK_REG_PSIRFACC_RCTRL_PCK = 18 ;
+static const uint8_t P9N2_PU_RX_MASK_REG_PSIRFACC_RFSM_PCK = 19 ;
+static const uint8_t P9N2_PU_RX_MASK_REG_PSIRFACC_RDL_FSM_PCK = 20 ;
+static const uint8_t P9N2_PU_RX_MASK_REG_PSIRFACC_RXSC_PCK = 21 ;
+static const uint8_t P9N2_PU_RX_MASK_REG_PSIRFACC_RLINK_STATE_LT_02 = 22 ;
+static const uint8_t P9N2_PU_RX_MASK_REG_PSIRFACC_C_RXDATA_RDY_ERR = 23 ;
+static const uint8_t P9N2_PU_RX_MASK_REG_C0_ERRACK_RISE = 24 ;
+
+static const uint8_t P9N2_PU_RX_PSI_CNTL_RX_PSI_IORESET_WO_PULSE_SLOW_SIGNAL = 0 ;
+static const uint8_t P9N2_PU_RX_PSI_CNTL_PATTERN_CHECK_EN = 1 ;
+static const uint8_t P9N2_PU_RX_PSI_CNTL_PATTERN_SEL = 2 ;
+static const uint8_t P9N2_PU_RX_PSI_CNTL_PATTERN_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_RX_PSI_CNTL_CLK_INVERT = 4 ;
+static const uint8_t P9N2_PU_RX_PSI_CNTL_LANE_INVERT = 5 ;
+static const uint8_t P9N2_PU_RX_PSI_CNTL_PDWN = 6 ;
+static const uint8_t P9N2_PU_RX_PSI_CNTL_CLK_DLY = 7 ;
+static const uint8_t P9N2_PU_RX_PSI_CNTL_CLK_DLY_LEN = 7 ;
+static const uint8_t P9N2_PU_RX_PSI_CNTL_DATA_DLY = 14 ;
+static const uint8_t P9N2_PU_RX_PSI_CNTL_DATA_DLY_LEN = 7 ;
+static const uint8_t P9N2_PU_RX_PSI_CNTL_DEGLITCH_CLK_DLY = 21 ;
+static const uint8_t P9N2_PU_RX_PSI_CNTL_DEGLITCH_CLK_DLY_LEN = 5 ;
+static const uint8_t P9N2_PU_RX_PSI_CNTL_DEGLITCH_DATA_DLY = 26 ;
+static const uint8_t P9N2_PU_RX_PSI_CNTL_DEGLITCH_DATA_DLY_LEN = 5 ;
+
+static const uint8_t P9N2_PU_RX_PSI_MODE_VREF = 0 ;
+static const uint8_t P9N2_PU_RX_PSI_MODE_VREF_LEN = 8 ;
+static const uint8_t P9N2_PU_RX_PSI_MODE_TERM_TEST = 12 ;
+static const uint8_t P9N2_PU_RX_PSI_MODE_TERM_ENC = 15 ;
+static const uint8_t P9N2_PU_RX_PSI_MODE_TERM_ENC_LEN = 5 ;
+static const uint8_t P9N2_PU_RX_PSI_MODE_PEAK = 20 ;
+static const uint8_t P9N2_PU_RX_PSI_MODE_PEAK_LEN = 3 ;
+static const uint8_t P9N2_PU_RX_PSI_MODE_SPARE = 24 ;
+static const uint8_t P9N2_PU_RX_PSI_MODE_SPARE_LEN = 8 ;
+
+static const uint8_t P9N2_PU_RX_PSI_STATUS_RX_PSI_PATTERN_CHECK_PASS_RO_SIGNAL = 0 ;
+static const uint8_t P9N2_PU_RX_PSI_STATUS_RX_PSI_PATTERN_CHECK_FAIL_RO_SIGNAL = 1 ;
+static const uint8_t P9N2_PU_RX_PSI_STATUS_RX_PSI_NO_PATTERN_FOUND_RO_SIGNAL = 2 ;
+static const uint8_t P9N2_PU_RX_PSI_STATUS_LD_UNLD_DLY = 4 ;
+static const uint8_t P9N2_PU_RX_PSI_STATUS_LD_UNLD_DLY_LEN = 4 ;
+static const uint8_t P9N2_PU_RX_PSI_STATUS_OVER_OR_UNDERRUN_ERR = 8 ;
+static const uint8_t P9N2_PU_RX_PSI_STATUS_CLEAR = 9 ;
+static const uint8_t P9N2_PU_RX_PSI_STATUS_SPARE = 10 ;
+static const uint8_t P9N2_PU_RX_PSI_STATUS_SPARE_LEN = 6 ;
+
+static const uint8_t P9N2_PEC_SCAN32_SCAN32_REG = 0 ;
+static const uint8_t P9N2_PEC_SCAN32_SCAN32_REG_LEN = 32 ;
+
+static const uint8_t P9N2_PEC_SCAN_CAPTUREDR_SCAN_CAPTUREDR_REG = 0 ;
+static const uint8_t P9N2_PEC_SCAN_CAPTUREDR_SCAN_CAPTUREDR_REG_LEN = 32 ;
+
+static const uint8_t P9N2_PEC_SCAN_REGION_TYPE_SYSTEM_FAST_INIT = 0 ;
+static const uint8_t P9N2_PEC_SCAN_REGION_TYPE_VITL = 3 ;
+static const uint8_t P9N2_PEC_SCAN_REGION_TYPE_PERV = 4 ;
+static const uint8_t P9N2_PEC_SCAN_REGION_TYPE_UNIT1 = 5 ;
+static const uint8_t P9N2_PEC_SCAN_REGION_TYPE_UNIT2 = 6 ;
+static const uint8_t P9N2_PEC_SCAN_REGION_TYPE_UNIT3 = 7 ;
+static const uint8_t P9N2_PEC_SCAN_REGION_TYPE_UNIT4 = 8 ;
+static const uint8_t P9N2_PEC_SCAN_REGION_TYPE_UNIT5 = 9 ;
+static const uint8_t P9N2_PEC_SCAN_REGION_TYPE_UNIT6 = 10 ;
+static const uint8_t P9N2_PEC_SCAN_REGION_TYPE_UNIT7 = 11 ;
+static const uint8_t P9N2_PEC_SCAN_REGION_TYPE_UNIT8 = 12 ;
+static const uint8_t P9N2_PEC_SCAN_REGION_TYPE_UNIT9 = 13 ;
+static const uint8_t P9N2_PEC_SCAN_REGION_TYPE_UNIT10 = 14 ;
+static const uint8_t P9N2_PEC_SCAN_REGION_TYPE_FUNC = 48 ;
+static const uint8_t P9N2_PEC_SCAN_REGION_TYPE_CFG = 49 ;
+static const uint8_t P9N2_PEC_SCAN_REGION_TYPE_CCFG_GPTR = 50 ;
+static const uint8_t P9N2_PEC_SCAN_REGION_TYPE_REGF = 51 ;
+static const uint8_t P9N2_PEC_SCAN_REGION_TYPE_LBIST = 52 ;
+static const uint8_t P9N2_PEC_SCAN_REGION_TYPE_ABIST = 53 ;
+static const uint8_t P9N2_PEC_SCAN_REGION_TYPE_REPR = 54 ;
+static const uint8_t P9N2_PEC_SCAN_REGION_TYPE_TIME = 55 ;
+static const uint8_t P9N2_PEC_SCAN_REGION_TYPE_BNDY = 56 ;
+static const uint8_t P9N2_PEC_SCAN_REGION_TYPE_FARR = 57 ;
+static const uint8_t P9N2_PEC_SCAN_REGION_TYPE_CMSK = 58 ;
+static const uint8_t P9N2_PEC_SCAN_REGION_TYPE_INEX = 59 ;
+
+static const uint8_t P9N2_PEC_SCOM0X00_LINKEN = 48 ;
+static const uint8_t P9N2_PEC_SCOM0X00_LINKRST = 49 ;
+static const uint8_t P9N2_PEC_SCOM0X00_CFGPTR = 51 ;
+static const uint8_t P9N2_PEC_SCOM0X00_CFGPTR_LEN = 2 ;
+static const uint8_t P9N2_PEC_SCOM0X00_CFGEXT = 53 ;
+static const uint8_t P9N2_PEC_SCOM0X00_CFGACT = 54 ;
+static const uint8_t P9N2_PEC_SCOM0X00_RXLOOP = 55 ;
+static const uint8_t P9N2_PEC_SCOM0X00_TXRSTEN = 56 ;
+static const uint8_t P9N2_PEC_SCOM0X00_PLLSEL = 57 ;
+static const uint8_t P9N2_PEC_SCOM0X00_DCKSEL = 59 ;
+static const uint8_t P9N2_PEC_SCOM0X00_BWSEL = 60 ;
+static const uint8_t P9N2_PEC_SCOM0X00_BWSEL_LEN = 2 ;
+static const uint8_t P9N2_PEC_SCOM0X00_RTSEL = 62 ;
+static const uint8_t P9N2_PEC_SCOM0X00_RTSEL_LEN = 2 ;
+
+static const uint8_t P9N2_PEC_SCOM0X01_SPSEL = 50 ;
+static const uint8_t P9N2_PEC_SCOM0X01_SPSEL_LEN = 2 ;
+static const uint8_t P9N2_PEC_SCOM0X01_FRCERR = 52 ;
+static const uint8_t P9N2_PEC_SCOM0X01_ERROR = 54 ;
+static const uint8_t P9N2_PEC_SCOM0X01_SYNC = 55 ;
+static const uint8_t P9N2_PEC_SCOM0X01_TPGMD = 57 ;
+static const uint8_t P9N2_PEC_SCOM0X01_MPCHK = 58 ;
+static const uint8_t P9N2_PEC_SCOM0X01_PRST = 59 ;
+static const uint8_t P9N2_PEC_SCOM0X01_TPSEL = 60 ;
+static const uint8_t P9N2_PEC_SCOM0X01_TPSEL_LEN = 4 ;
+
+static const uint8_t P9N2_PEC_SCOM0X02_ZCALOVRD = 55 ;
+static const uint8_t P9N2_PEC_SCOM0X02_OCOEF = 60 ;
+static const uint8_t P9N2_PEC_SCOM0X02_COEFRST = 61 ;
+static const uint8_t P9N2_PEC_SCOM0X02_OSEG = 62 ;
+static const uint8_t P9N2_PEC_SCOM0X02_ALOAD = 63 ;
+
+static const uint8_t P9N2_PEC_SCOM0X03_ASPAREC = 53 ;
+static const uint8_t P9N2_PEC_SCOM0X03_ASPAREC_LEN = 3 ;
+static const uint8_t P9N2_PEC_SCOM0X03_DRVHIZ = 58 ;
+static const uint8_t P9N2_PEC_SCOM0X03_SASIMP = 59 ;
+static const uint8_t P9N2_PEC_SCOM0X03_SSTBW = 63 ;
+
+static const uint8_t P9N2_PEC_SCOM0X04_DCCEN = 59 ;
+
+static const uint8_t P9N2_PEC_SCOM0X05_CSSTEP = 48 ;
+static const uint8_t P9N2_PEC_SCOM0X05_CSLOCK = 49 ;
+static const uint8_t P9N2_PEC_SCOM0X05_ALIGNSAM = 56 ;
+static const uint8_t P9N2_PEC_SCOM0X05_RSYNCC = 57 ;
+static const uint8_t P9N2_PEC_SCOM0X05_THRSHCNT = 58 ;
+static const uint8_t P9N2_PEC_SCOM0X05_THRSHCNT_LEN = 4 ;
+static const uint8_t P9N2_PEC_SCOM0X05_THRSHMULT = 62 ;
+static const uint8_t P9N2_PEC_SCOM0X05_THRSHMULT_LEN = 2 ;
+
+static const uint8_t P9N2_PEC_SCOM0X06_CALSSTN = 50 ;
+static const uint8_t P9N2_PEC_SCOM0X06_CALSSTN_LEN = 7 ;
+static const uint8_t P9N2_PEC_SCOM0X06_CALSSTP = 57 ;
+static const uint8_t P9N2_PEC_SCOM0X06_CALSSTP_LEN = 7 ;
+
+static const uint8_t P9N2_PEC_SCOM0X07_OFFSET = 53 ;
+static const uint8_t P9N2_PEC_SCOM0X07_OFFSET_LEN = 5 ;
+static const uint8_t P9N2_PEC_SCOM0X07_OVRDOFF = 58 ;
+static const uint8_t P9N2_PEC_SCOM0X07_OFFSETOVRD = 59 ;
+static const uint8_t P9N2_PEC_SCOM0X07_OFFSETOVRD_LEN = 5 ;
+
+static const uint8_t P9N2_PEC_SCOM0X08_MARGIN = 51 ;
+static const uint8_t P9N2_PEC_SCOM0X08_MARGIN_LEN = 3 ;
+static const uint8_t P9N2_PEC_SCOM0X08_POSTCOEF = 54 ;
+static const uint8_t P9N2_PEC_SCOM0X08_POSTCOEF_LEN = 5 ;
+static const uint8_t P9N2_PEC_SCOM0X08_PRECOEFF = 59 ;
+static const uint8_t P9N2_PEC_SCOM0X08_PRECOEFF_LEN = 5 ;
+
+static const uint8_t P9N2_PEC_SCOM0X09_BYTE1 = 48 ;
+static const uint8_t P9N2_PEC_SCOM0X09_BYTE1_LEN = 8 ;
+static const uint8_t P9N2_PEC_SCOM0X09_BYTE0 = 56 ;
+static const uint8_t P9N2_PEC_SCOM0X09_BYTE0_LEN = 8 ;
+
+static const uint8_t P9N2_PEC_SCOM0X0A_REQWOV = 48 ;
+static const uint8_t P9N2_PEC_SCOM0X0A_SMODE = 53 ;
+static const uint8_t P9N2_PEC_SCOM0X0A_SMODE_LEN = 3 ;
+static const uint8_t P9N2_PEC_SCOM0X0A_ADCORR = 56 ;
+static const uint8_t P9N2_PEC_SCOM0X0A_TRAINEN = 57 ;
+static const uint8_t P9N2_PEC_SCOM0X0A_ASAMPQ = 58 ;
+static const uint8_t P9N2_PEC_SCOM0X0A_ASAMPQ_LEN = 3 ;
+static const uint8_t P9N2_PEC_SCOM0X0A_ASAMP = 61 ;
+static const uint8_t P9N2_PEC_SCOM0X0A_ASAMP_LEN = 3 ;
+
+static const uint8_t P9N2_PEC_SCOM0X0B_MARGIN = 51 ;
+static const uint8_t P9N2_PEC_SCOM0X0B_MARGIN_LEN = 3 ;
+static const uint8_t P9N2_PEC_SCOM0X0B_POSTCOEFF = 54 ;
+static const uint8_t P9N2_PEC_SCOM0X0B_POSTCOEFF_LEN = 5 ;
+static const uint8_t P9N2_PEC_SCOM0X0B_PRECOEFF = 59 ;
+static const uint8_t P9N2_PEC_SCOM0X0B_PRECOEFF_LEN = 5 ;
+
+static const uint8_t P9N2_PEC_SCOM0X0C_PEAK = 48 ;
+static const uint8_t P9N2_PEC_SCOM0X0C_PEAK_LEN = 6 ;
+static const uint8_t P9N2_PEC_SCOM0X0C_SHORTV = 54 ;
+static const uint8_t P9N2_PEC_SCOM0X0C_PEAKIND = 56 ;
+static const uint8_t P9N2_PEC_SCOM0X0C_PEAKIND_LEN = 2 ;
+static const uint8_t P9N2_PEC_SCOM0X0C_VGAIN = 58 ;
+static const uint8_t P9N2_PEC_SCOM0X0C_VGAIN_LEN = 6 ;
+
+static const uint8_t P9N2_PEC_SCOM0X0D_TXPOL = 57 ;
+static const uint8_t P9N2_PEC_SCOM0X0D_TXPOL_LEN = 3 ;
+static const uint8_t P9N2_PEC_SCOM0X0D_LBPOL = 60 ;
+static const uint8_t P9N2_PEC_SCOM0X0D_NXTPOL = 61 ;
+static const uint8_t P9N2_PEC_SCOM0X0D_NXTPOL_LEN = 3 ;
+
+static const uint8_t P9N2_PEC_SCOM0X0E_REFVOLT = 52 ;
+static const uint8_t P9N2_PEC_SCOM0X0E_REFVOLT_LEN = 8 ;
+static const uint8_t P9N2_PEC_SCOM0X0E_PRESULT = 60 ;
+static const uint8_t P9N2_PEC_SCOM0X0E_NRESULT = 61 ;
+static const uint8_t P9N2_PEC_SCOM0X0E_TDREN = 63 ;
+
+static const uint8_t P9N2_PEC_SCOM0X0F_OFFSET = 59 ;
+static const uint8_t P9N2_PEC_SCOM0X0F_OFFSET_LEN = 5 ;
+
+static const uint8_t P9N2_PEC_SCOM0X10_PRESEG0P = 53 ;
+static const uint8_t P9N2_PEC_SCOM0X10_PRESEG0P_LEN = 11 ;
+
+static const uint8_t P9N2_PEC_SCOM0X11_PRESEG1P = 53 ;
+static const uint8_t P9N2_PEC_SCOM0X11_PRESEG1P_LEN = 11 ;
+
+static const uint8_t P9N2_PEC_SCOM0X12_MAINSEG0P = 49 ;
+static const uint8_t P9N2_PEC_SCOM0X12_MAINSEG0P_LEN = 15 ;
+
+static const uint8_t P9N2_PEC_SCOM0X13_MAINSEG1P = 49 ;
+static const uint8_t P9N2_PEC_SCOM0X13_MAINSEG1P_LEN = 15 ;
+
+static const uint8_t P9N2_PEC_SCOM0X14_POSTSEG0P = 50 ;
+static const uint8_t P9N2_PEC_SCOM0X14_POSTSEG0P_LEN = 14 ;
+
+static const uint8_t P9N2_PEC_SCOM0X15_POSTSEG1P = 50 ;
+static const uint8_t P9N2_PEC_SCOM0X15_POSTSEG1P_LEN = 14 ;
+
+static const uint8_t P9N2_PEC_SCOM0X16_PRESEG0N = 53 ;
+static const uint8_t P9N2_PEC_SCOM0X16_PRESEG0N_LEN = 11 ;
+
+static const uint8_t P9N2_PEC_SCOM0X17_PRESEG1N = 53 ;
+static const uint8_t P9N2_PEC_SCOM0X17_PRESEG1N_LEN = 11 ;
+
+static const uint8_t P9N2_PEC_SCOM0X18_MAINSEG0N = 49 ;
+static const uint8_t P9N2_PEC_SCOM0X18_MAINSEG0N_LEN = 15 ;
+
+static const uint8_t P9N2_PEC_SCOM0X19_MAINSEG1N = 49 ;
+static const uint8_t P9N2_PEC_SCOM0X19_MAINSEG1N_LEN = 15 ;
+
+static const uint8_t P9N2_PEC_SCOM0X1A_POSTSEG0N = 50 ;
+static const uint8_t P9N2_PEC_SCOM0X1A_POSTSEG0N_LEN = 14 ;
+
+static const uint8_t P9N2_PEC_SCOM0X1B_POSTSEG1N = 50 ;
+static const uint8_t P9N2_PEC_SCOM0X1B_POSTSEG1N_LEN = 14 ;
+
+static const uint8_t P9N2_PEC_SCOM0X1C_DPCMD = 49 ;
+static const uint8_t P9N2_PEC_SCOM0X1C_DPCCVG = 50 ;
+static const uint8_t P9N2_PEC_SCOM0X1C_DPCTGT = 52 ;
+static const uint8_t P9N2_PEC_SCOM0X1C_DPCTGT_LEN = 3 ;
+static const uint8_t P9N2_PEC_SCOM0X1C_BLKH1T = 55 ;
+static const uint8_t P9N2_PEC_SCOM0X1C_BLKOAE = 56 ;
+static const uint8_t P9N2_PEC_SCOM0X1C_H1TGT = 57 ;
+static const uint8_t P9N2_PEC_SCOM0X1C_H1TGT_LEN = 3 ;
+static const uint8_t P9N2_PEC_SCOM0X1C_OAE = 60 ;
+static const uint8_t P9N2_PEC_SCOM0X1C_OAE_LEN = 4 ;
+
+static const uint8_t P9N2_PEC_SCOM0X1D_OLS = 48 ;
+static const uint8_t P9N2_PEC_SCOM0X1D_OLS_LEN = 5 ;
+static const uint8_t P9N2_PEC_SCOM0X1D_OES = 53 ;
+static const uint8_t P9N2_PEC_SCOM0X1D_OES_LEN = 5 ;
+static const uint8_t P9N2_PEC_SCOM0X1D_BLKODEC = 58 ;
+static const uint8_t P9N2_PEC_SCOM0X1D_VIEWSCAN = 59 ;
+static const uint8_t P9N2_PEC_SCOM0X1D_ODEC = 60 ;
+static const uint8_t P9N2_PEC_SCOM0X1D_ODEC_LEN = 4 ;
+
+static const uint8_t P9N2_PEC_SCOM0X1E_XDATA = 48 ;
+static const uint8_t P9N2_PEC_SCOM0X1E_XDATA_LEN = 16 ;
+
+static const uint8_t P9N2_PEC_SCOM0X1F_XADDR = 58 ;
+static const uint8_t P9N2_PEC_SCOM0X1F_XADDR_LEN = 5 ;
+
+static const uint8_t P9N2_PEC_SCOM0X20_XDAT10 = 48 ;
+static const uint8_t P9N2_PEC_SCOM0X20_XDAT10_LEN = 16 ;
+
+static const uint8_t P9N2_PEC_SCOM0X21_XDAT32 = 48 ;
+static const uint8_t P9N2_PEC_SCOM0X21_XDAT32_LEN = 16 ;
+
+static const uint8_t P9N2_PEC_SCOM0X22_XDAT54 = 48 ;
+static const uint8_t P9N2_PEC_SCOM0X22_XDAT54_LEN = 16 ;
+
+static const uint8_t P9N2_PEC_SCOM0X23_XDAT76 = 48 ;
+static const uint8_t P9N2_PEC_SCOM0X23_XDAT76_LEN = 16 ;
+
+static const uint8_t P9N2_PEC_SCOM0X24_LOFO4 = 50 ;
+static const uint8_t P9N2_PEC_SCOM0X24_LOFO4_LEN = 6 ;
+static const uint8_t P9N2_PEC_SCOM0X24_LOFO3 = 58 ;
+static const uint8_t P9N2_PEC_SCOM0X24_LOFO3_LEN = 6 ;
+
+static const uint8_t P9N2_PEC_SCOM0X25_E1AMP = 50 ;
+static const uint8_t P9N2_PEC_SCOM0X25_E1AMP_LEN = 6 ;
+static const uint8_t P9N2_PEC_SCOM0X25_E0AMP = 58 ;
+static const uint8_t P9N2_PEC_SCOM0X25_E0AMP_LEN = 6 ;
+
+static const uint8_t P9N2_PEC_SCOM0X26_FINITLOFF = 48 ;
+static const uint8_t P9N2_PEC_SCOM0X26_LFREG = 51 ;
+static const uint8_t P9N2_PEC_SCOM0X26_LFRC = 52 ;
+static const uint8_t P9N2_PEC_SCOM0X26_LFSEL = 53 ;
+static const uint8_t P9N2_PEC_SCOM0X26_LFSEL_LEN = 3 ;
+static const uint8_t P9N2_PEC_SCOM0X26_PKINIT = 58 ;
+static const uint8_t P9N2_PEC_SCOM0X26_PKINIT_LEN = 6 ;
+
+static const uint8_t P9N2_PEC_SCOM0X27_SDPDOV = 48 ;
+static const uint8_t P9N2_PEC_SCOM0X27_OFFAMP = 51 ;
+static const uint8_t P9N2_PEC_SCOM0X27_OFFAMP_LEN = 5 ;
+static const uint8_t P9N2_PEC_SCOM0X27_SDACDC = 56 ;
+static const uint8_t P9N2_PEC_SCOM0X27_SDPDN = 57 ;
+static const uint8_t P9N2_PEC_SCOM0X27_SIGDET = 58 ;
+static const uint8_t P9N2_PEC_SCOM0X27_SDLVL = 59 ;
+static const uint8_t P9N2_PEC_SCOM0X27_SDLVL_LEN = 5 ;
+
+static const uint8_t P9N2_PEC_SCOM0X28_DCCTIMEDOUT = 48 ;
+static const uint8_t P9N2_PEC_SCOM0X28_DCCTIMEEN = 49 ;
+static const uint8_t P9N2_PEC_SCOM0X28_DCCLOCK = 50 ;
+static const uint8_t P9N2_PEC_SCOM0X28_DCCOFFSET = 51 ;
+static const uint8_t P9N2_PEC_SCOM0X28_DCCOFFSET_LEN = 5 ;
+static const uint8_t P9N2_PEC_SCOM0X28_DCCSTEP = 56 ;
+static const uint8_t P9N2_PEC_SCOM0X28_DCCSTEP_LEN = 2 ;
+static const uint8_t P9N2_PEC_SCOM0X28_DCCASTEP = 58 ;
+static const uint8_t P9N2_PEC_SCOM0X28_DCCASTEP_LEN = 5 ;
+static const uint8_t P9N2_PEC_SCOM0X28_DCCAEN = 63 ;
+
+static const uint8_t P9N2_PEC_SCOM0X29_DCCOUT = 51 ;
+static const uint8_t P9N2_PEC_SCOM0X29_DCCCLK = 52 ;
+static const uint8_t P9N2_PEC_SCOM0X29_DCCHOLD = 53 ;
+static const uint8_t P9N2_PEC_SCOM0X29_DCCSIGN = 54 ;
+static const uint8_t P9N2_PEC_SCOM0X29_DCCSIGN_LEN = 2 ;
+static const uint8_t P9N2_PEC_SCOM0X29_DCCAMP = 56 ;
+static const uint8_t P9N2_PEC_SCOM0X29_DCCAMP_LEN = 7 ;
+static const uint8_t P9N2_PEC_SCOM0X29_DCCOEN = 63 ;
+
+static const uint8_t P9N2_PEC_SCOM0X2A_DCCTMOUT = 48 ;
+static const uint8_t P9N2_PEC_SCOM0X2A_DCCTMOUT_LEN = 16 ;
+
+static const uint8_t P9N2_PEC_SCOM0X2B_DCCASIGNNEG = 55 ;
+static const uint8_t P9N2_PEC_SCOM0X2B_DCCASIGNPOS = 56 ;
+static const uint8_t P9N2_PEC_SCOM0X2B_DCCAAMP = 57 ;
+static const uint8_t P9N2_PEC_SCOM0X2B_DCCAAMP_LEN = 7 ;
+
+static const uint8_t P9N2_PEC_SCOM0X2C_VREFSEL = 48 ;
+static const uint8_t P9N2_PEC_SCOM0X2C_VREFSEL_LEN = 5 ;
+static const uint8_t P9N2_PEC_SCOM0X2C_RDETCNTL = 53 ;
+static const uint8_t P9N2_PEC_SCOM0X2C_RDETCNTL_LEN = 5 ;
+static const uint8_t P9N2_PEC_SCOM0X2C_RDETDRV = 58 ;
+static const uint8_t P9N2_PEC_SCOM0X2C_RDETDRV_LEN = 3 ;
+static const uint8_t P9N2_PEC_SCOM0X2C_RDETWAIT = 61 ;
+static const uint8_t P9N2_PEC_SCOM0X2C_RDETWAIT_LEN = 3 ;
+
+static const uint8_t P9N2_PEC_SCOM0X2D_RCVDETMFT = 48 ;
+static const uint8_t P9N2_PEC_SCOM0X2D_RDETOUTN = 55 ;
+static const uint8_t P9N2_PEC_SCOM0X2D_RDETOUTP = 56 ;
+static const uint8_t P9N2_PEC_SCOM0X2D_RDETRSLT1 = 57 ;
+static const uint8_t P9N2_PEC_SCOM0X2D_RDETRSLT2 = 58 ;
+static const uint8_t P9N2_PEC_SCOM0X2D_RDETEN = 59 ;
+static const uint8_t P9N2_PEC_SCOM0X2D_RDETOVRD = 60 ;
+static const uint8_t P9N2_PEC_SCOM0X2D_RDETVAL = 61 ;
+static const uint8_t P9N2_PEC_SCOM0X2D_RDETBYP = 62 ;
+static const uint8_t P9N2_PEC_SCOM0X2D_RDETFRC = 63 ;
+
+static const uint8_t P9N2_PEC_SCOM0X2E_TXEQ1 = 48 ;
+static const uint8_t P9N2_PEC_SCOM0X2E_TXEQ1_LEN = 16 ;
+
+static const uint8_t P9N2_PEC_SCOM0X2F_TXEQ2 = 48 ;
+static const uint8_t P9N2_PEC_SCOM0X2F_TXEQ2_LEN = 16 ;
+
+static const uint8_t P9N2_PEC_SCOM0X30_PDC2CLK = 56 ;
+static const uint8_t P9N2_PEC_SCOM0X30_SPARE = 57 ;
+static const uint8_t P9N2_PEC_SCOM0X30_PDM3 = 58 ;
+static const uint8_t P9N2_PEC_SCOM0X30_PDM2 = 59 ;
+static const uint8_t P9N2_PEC_SCOM0X30_PDM1 = 60 ;
+static const uint8_t P9N2_PEC_SCOM0X30_PDSER = 61 ;
+static const uint8_t P9N2_PEC_SCOM0X30_PDTSTVRCV = 62 ;
+static const uint8_t P9N2_PEC_SCOM0X30_PDSST = 63 ;
+
+static const uint8_t P9N2_PEC_SCOM0X31_H_VALUE = 51 ;
+static const uint8_t P9N2_PEC_SCOM0X31_H_VALUE_LEN = 12 ;
+
+static const uint8_t P9N2_PEC_SCOM0X32_LOFFFBINV = 49 ;
+static const uint8_t P9N2_PEC_SCOM0X32_H1CALFBINV = 50 ;
+static const uint8_t P9N2_PEC_SCOM0X32_H1AFBINV = 51 ;
+static const uint8_t P9N2_PEC_SCOM0X32_INITLOFFFBINV = 52 ;
+static const uint8_t P9N2_PEC_SCOM0X32_SDFBINV = 53 ;
+static const uint8_t P9N2_PEC_SCOM0X32_H0FBINV = 54 ;
+static const uint8_t P9N2_PEC_SCOM0X32_CMFBINV = 55 ;
+static const uint8_t P9N2_PEC_SCOM0X32_LOFFSGNINV = 58 ;
+static const uint8_t P9N2_PEC_SCOM0X32_H212SGNINV = 59 ;
+static const uint8_t P9N2_PEC_SCOM0X32_H1SGNINV = 60 ;
+static const uint8_t P9N2_PEC_SCOM0X32_ASGNINV = 61 ;
+static const uint8_t P9N2_PEC_SCOM0X32_SDSGNINV = 62 ;
+static const uint8_t P9N2_PEC_SCOM0X32_OFFSGNINV = 63 ;
+
+static const uint8_t P9N2_PEC_SCOM0X33_KPGAIN = 56 ;
+static const uint8_t P9N2_PEC_SCOM0X33_KPGAIN_LEN = 5 ;
+static const uint8_t P9N2_PEC_SCOM0X33_KIGAIN = 61 ;
+static const uint8_t P9N2_PEC_SCOM0X33_KIGAIN_LEN = 3 ;
+
+static const uint8_t P9N2_PEC_SCOM0X34_H1SNMT = 48 ;
+static const uint8_t P9N2_PEC_SCOM0X34_TUNE4 = 49 ;
+static const uint8_t P9N2_PEC_SCOM0X34_TUNE3 = 50 ;
+static const uint8_t P9N2_PEC_SCOM0X34_TUNE2 = 51 ;
+static const uint8_t P9N2_PEC_SCOM0X34_TUNE1 = 52 ;
+static const uint8_t P9N2_PEC_SCOM0X34_TUNE0 = 53 ;
+static const uint8_t P9N2_PEC_SCOM0X34_TENZP = 54 ;
+static const uint8_t P9N2_PEC_SCOM0X34_TENZN = 55 ;
+static const uint8_t P9N2_PEC_SCOM0X34_TRFIX = 56 ;
+static const uint8_t P9N2_PEC_SCOM0X34_TREFBNKA = 57 ;
+static const uint8_t P9N2_PEC_SCOM0X34_TREFBNKB = 58 ;
+static const uint8_t P9N2_PEC_SCOM0X34_TREFODD = 59 ;
+static const uint8_t P9N2_PEC_SCOM0X34_TREFPOL = 60 ;
+static const uint8_t P9N2_PEC_SCOM0X34_TREFSPE = 61 ;
+static const uint8_t P9N2_PEC_SCOM0X34_TREFEN1 = 62 ;
+static const uint8_t P9N2_PEC_SCOM0X34_TREFEN2 = 63 ;
+
+static const uint8_t P9N2_PEC_SCOM0X35_WAIT = 48 ;
+static const uint8_t P9N2_PEC_SCOM0X35_WAIT_LEN = 8 ;
+static const uint8_t P9N2_PEC_SCOM0X35_AVGS = 56 ;
+static const uint8_t P9N2_PEC_SCOM0X35_AVGS_LEN = 3 ;
+static const uint8_t P9N2_PEC_SCOM0X35_COPY = 60 ;
+static const uint8_t P9N2_PEC_SCOM0X35_CLEAR = 61 ;
+static const uint8_t P9N2_PEC_SCOM0X35_START = 62 ;
+static const uint8_t P9N2_PEC_SCOM0X35_ENABLE = 63 ;
+
+static const uint8_t P9N2_PEC_SCOM0X36_SUM1 = 48 ;
+static const uint8_t P9N2_PEC_SCOM0X36_SUM1_LEN = 16 ;
+
+static const uint8_t P9N2_PEC_SCOM0X37_SUM2 = 48 ;
+static const uint8_t P9N2_PEC_SCOM0X37_SUM2_LEN = 16 ;
+
+static const uint8_t P9N2_PEC_SCOM0X38_NFAILID = 49 ;
+static const uint8_t P9N2_PEC_SCOM0X38_NFAILID_LEN = 15 ;
+
+static const uint8_t P9N2_PEC_SCOM0X39_PFAILID = 49 ;
+static const uint8_t P9N2_PEC_SCOM0X39_PFAILID_LEN = 15 ;
+
+static const uint8_t P9N2_PEC_SCOM0X3A_TOTFAILS = 55 ;
+static const uint8_t P9N2_PEC_SCOM0X3A_TOTFAILS_LEN = 9 ;
+
+static const uint8_t P9N2_PEC_SCOM0X3B_PFFSEQ = 48 ;
+static const uint8_t P9N2_PEC_SCOM0X3B_PFFSEQ_LEN = 8 ;
+static const uint8_t P9N2_PEC_SCOM0X3B_NFFSEQ = 56 ;
+static const uint8_t P9N2_PEC_SCOM0X3B_NFFSEQ_LEN = 8 ;
+
+static const uint8_t P9N2_PEC_SCOM0X3C_DRVPERR = 48 ;
+static const uint8_t P9N2_PEC_SCOM0X3C_DRVNERR = 49 ;
+static const uint8_t P9N2_PEC_SCOM0X3C_DTESTEN = 51 ;
+static const uint8_t P9N2_PEC_SCOM0X3C_LSBEN = 52 ;
+static const uint8_t P9N2_PEC_SCOM0X3C_TSTRCVP = 53 ;
+static const uint8_t P9N2_PEC_SCOM0X3C_TSTRCVN = 54 ;
+static const uint8_t P9N2_PEC_SCOM0X3C_SEQNUM = 56 ;
+static const uint8_t P9N2_PEC_SCOM0X3C_SEQNUM_LEN = 8 ;
+
+static const uint8_t P9N2_PEC_SCOM0X3D_TSTCNT = 48 ;
+static const uint8_t P9N2_PEC_SCOM0X3D_TSTCNT_LEN = 13 ;
+static const uint8_t P9N2_PEC_SCOM0X3D_SLEWCODE = 61 ;
+static const uint8_t P9N2_PEC_SCOM0X3D_SLEWCODE_LEN = 2 ;
+static const uint8_t P9N2_PEC_SCOM0X3D_ASEGEN = 63 ;
+
+static const uint8_t P9N2_PEC_SCOM0X3E_AECMDVAL = 49 ;
+static const uint8_t P9N2_PEC_SCOM0X3E_AECMD1312 = 50 ;
+static const uint8_t P9N2_PEC_SCOM0X3E_AECMD1312_LEN = 2 ;
+static const uint8_t P9N2_PEC_SCOM0X3E_ASODD = 52 ;
+static const uint8_t P9N2_PEC_SCOM0X3E_ASODD_LEN = 3 ;
+static const uint8_t P9N2_PEC_SCOM0X3E_ASEVEN = 55 ;
+static const uint8_t P9N2_PEC_SCOM0X3E_ASEVEN_LEN = 3 ;
+static const uint8_t P9N2_PEC_SCOM0X3E_AECMD50 = 58 ;
+static const uint8_t P9N2_PEC_SCOM0X3E_AECMD50_LEN = 6 ;
+
+static const uint8_t P9N2_PEC_SCOM0X3F_TSTDCLKEN = 48 ;
+static const uint8_t P9N2_PEC_SCOM0X3F_TSTCTL = 49 ;
+static const uint8_t P9N2_PEC_SCOM0X3F_TSTCTL_LEN = 6 ;
+static const uint8_t P9N2_PEC_SCOM0X3F_STSTMD = 55 ;
+static const uint8_t P9N2_PEC_SCOM0X3F_BSOUT = 57 ;
+static const uint8_t P9N2_PEC_SCOM0X3F_BSIN = 58 ;
+static const uint8_t P9N2_PEC_SCOM0X3F_JTAGAMPL = 59 ;
+static const uint8_t P9N2_PEC_SCOM0X3F_JTAGAMPL_LEN = 2 ;
+static const uint8_t P9N2_PEC_SCOM0X3F_JTAGOE = 61 ;
+static const uint8_t P9N2_PEC_SCOM0X3F_TXOE = 62 ;
+static const uint8_t P9N2_PEC_SCOM0X3F_OBS = 63 ;
+
+static const uint8_t P9N2_PU_SCOM_PPE_CNTL_IORESET = 0 ;
+static const uint8_t P9N2_PU_SCOM_PPE_CNTL_PDWN = 1 ;
+static const uint8_t P9N2_PU_SCOM_PPE_CNTL_INTERRUPT = 2 ;
+static const uint8_t P9N2_PU_SCOM_PPE_CNTL_ARB_ECC_INJECT_ERR = 3 ;
+static const uint8_t P9N2_PU_SCOM_PPE_CNTL_SPARES = 4 ;
+static const uint8_t P9N2_PU_SCOM_PPE_CNTL_SPARES_LEN = 12 ;
+
+static const uint8_t P9N2_PU_SCOM_PPE_FLAGS_FIELD = 0 ;
+static const uint8_t P9N2_PU_SCOM_PPE_FLAGS_FIELD_LEN = 16 ;
+
+static const uint8_t P9N2_PU_SCOM_PPE_WORK_REG1_WORK1 = 0 ;
+static const uint8_t P9N2_PU_SCOM_PPE_WORK_REG1_WORK1_LEN = 32 ;
+
+static const uint8_t P9N2_PU_SCOM_PPE_WORK_REG2_WORK2 = 0 ;
+static const uint8_t P9N2_PU_SCOM_PPE_WORK_REG2_WORK2_LEN = 32 ;
+
+static const uint8_t P9N2_PU_SCRATCH0_SCRATCH_N = 0 ;
+static const uint8_t P9N2_PU_SCRATCH0_SCRATCH_N_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU2_NTL1_SCRATCH0_IDIAL = 0 ;
+static const uint8_t P9N2_PU_NPU2_NTL1_SCRATCH0_IDIAL_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU1_SM1_SCRATCH1_IDIAL = 0 ;
+static const uint8_t P9N2_PU_NPU1_SM1_SCRATCH1_IDIAL_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU_SM2_SCRATCH1_IDIAL = 0 ;
+static const uint8_t P9N2_PU_NPU_SM2_SCRATCH1_IDIAL_LEN = 64 ;
+
+static const uint8_t P9N2__SM0_SCRATCH1_IDIAL = 0 ;
+static const uint8_t P9N2__SM0_SCRATCH1_IDIAL_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU_SM0_SCRATCH1_IDIAL = 0 ;
+static const uint8_t P9N2_PU_NPU_SM0_SCRATCH1_IDIAL_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU1_SM2_SCRATCH1_IDIAL = 0 ;
+static const uint8_t P9N2_PU_NPU1_SM2_SCRATCH1_IDIAL_LEN = 64 ;
+
+static const uint8_t P9N2_PU_SCRATCH1_SCRATCH_N = 0 ;
+static const uint8_t P9N2_PU_SCRATCH1_SCRATCH_N_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU_SM1_SCRATCH1_IDIAL = 0 ;
+static const uint8_t P9N2_PU_NPU_SM1_SCRATCH1_IDIAL_LEN = 64 ;
+
+static const uint8_t P9N2__SM2_SCRATCH1_IDIAL = 0 ;
+static const uint8_t P9N2__SM2_SCRATCH1_IDIAL_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU1_SM0_SCRATCH1_IDIAL = 0 ;
+static const uint8_t P9N2_PU_NPU1_SM0_SCRATCH1_IDIAL_LEN = 64 ;
+
+static const uint8_t P9N2__SM1_SCRATCH1_IDIAL = 0 ;
+static const uint8_t P9N2__SM1_SCRATCH1_IDIAL_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU1_SM1_SCRATCH2_IDIAL = 0 ;
+static const uint8_t P9N2_PU_NPU1_SM1_SCRATCH2_IDIAL_LEN = 64 ;
+
+static const uint8_t P9N2__SM0_SCRATCH2_IDIAL = 0 ;
+static const uint8_t P9N2__SM0_SCRATCH2_IDIAL_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU_SM0_SCRATCH2_IDIAL = 0 ;
+static const uint8_t P9N2_PU_NPU_SM0_SCRATCH2_IDIAL_LEN = 64 ;
+
+static const uint8_t P9N2_PU_SCRATCH2_SCRATCH_N = 0 ;
+static const uint8_t P9N2_PU_SCRATCH2_SCRATCH_N_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU_SM1_SCRATCH2_IDIAL = 0 ;
+static const uint8_t P9N2_PU_NPU_SM1_SCRATCH2_IDIAL_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU1_SM0_SCRATCH2_IDIAL = 0 ;
+static const uint8_t P9N2_PU_NPU1_SM0_SCRATCH2_IDIAL_LEN = 64 ;
+
+static const uint8_t P9N2__SM1_SCRATCH2_IDIAL = 0 ;
+static const uint8_t P9N2__SM1_SCRATCH2_IDIAL_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU1_SM1_SCRATCH3_IDIAL = 0 ;
+static const uint8_t P9N2_PU_NPU1_SM1_SCRATCH3_IDIAL_LEN = 64 ;
+
+static const uint8_t P9N2__SM0_SCRATCH3_IDIAL = 0 ;
+static const uint8_t P9N2__SM0_SCRATCH3_IDIAL_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU_SM0_SCRATCH3_IDIAL = 0 ;
+static const uint8_t P9N2_PU_NPU_SM0_SCRATCH3_IDIAL_LEN = 64 ;
+
+static const uint8_t P9N2_PU_SCRATCH3_SCRATCH_N = 0 ;
+static const uint8_t P9N2_PU_SCRATCH3_SCRATCH_N_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU_SM1_SCRATCH3_IDIAL = 0 ;
+static const uint8_t P9N2_PU_NPU_SM1_SCRATCH3_IDIAL_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU1_SM0_SCRATCH3_IDIAL = 0 ;
+static const uint8_t P9N2_PU_NPU1_SM0_SCRATCH3_IDIAL_LEN = 64 ;
+
+static const uint8_t P9N2__SM1_SCRATCH3_IDIAL = 0 ;
+static const uint8_t P9N2__SM1_SCRATCH3_IDIAL_LEN = 64 ;
+
+static const uint8_t P9N2_PU_SECURITY_SWITCH_REGISTER_SECURE_ACCESS = 0 ;
+static const uint8_t P9N2_PU_SECURITY_SWITCH_REGISTER_LATE_LAUNCH_PRIMARY = 1 ;
+static const uint8_t P9N2_PU_SECURITY_SWITCH_REGISTER_LATE_LAUNCH_SECONDARY = 2 ;
+static const uint8_t P9N2_PU_SECURITY_SWITCH_REGISTER_LOCAL_QUIESCE_ACHIEVED = 3 ;
+static const uint8_t P9N2_PU_SECURITY_SWITCH_REGISTER_SEEPROM_UPDATE_LOCK = 4 ;
+static const uint8_t P9N2_PU_SECURITY_SWITCH_REGISTER_LOCALITY_4_ACCESS = 5 ;
+static const uint8_t P9N2_PU_SECURITY_SWITCH_REGISTER_SECURE_DEBUG = 6 ;
+static const uint8_t P9N2_PU_SECURITY_SWITCH_REGISTER_CMFSI_ACCESS_PROTCT = 7 ;
+static const uint8_t P9N2_PU_SECURITY_SWITCH_REGISTER_ABUS_LOCK = 8 ;
+static const uint8_t P9N2_PU_SECURITY_SWITCH_REGISTER_NX_RAND_NUM_GEN_LOCK = 9 ;
+static const uint8_t P9N2_PU_SECURITY_SWITCH_REGISTER_PROT_EX_SPARE0 = 10 ;
+static const uint8_t P9N2_PU_SECURITY_SWITCH_REGISTER_PROT_EX_SPARE1 = 11 ;
+static const uint8_t P9N2_PU_SECURITY_SWITCH_REGISTER_I2CM_TPM_DECONFIG_PROTECT = 12 ;
+static const uint8_t P9N2_PU_SECURITY_SWITCH_REGISTER_PROT_TP_SPARE0 = 13 ;
+static const uint8_t P9N2_PU_SECURITY_SWITCH_REGISTER_PROT_TP_SPARE1 = 14 ;
+static const uint8_t P9N2_PU_SECURITY_SWITCH_REGISTER_PROT_TP_SPARE2 = 15 ;
+
+static const uint8_t P9N2_PU_SEND_WC_BASE_ADDR_BAR = 8 ;
+static const uint8_t P9N2_PU_SEND_WC_BASE_ADDR_BAR_LEN = 33 ;
+
+static const uint8_t P9N2_PEC_SKITTER_CLKSRC_REG_SKITTER0 = 0 ;
+static const uint8_t P9N2_PEC_SKITTER_CLKSRC_REG_SKITTER0_LEN = 3 ;
+static const uint8_t P9N2_PEC_SKITTER_CLKSRC_REG_SKITTER0_DELAY_SELECT = 36 ;
+static const uint8_t P9N2_PEC_SKITTER_CLKSRC_REG_SKITTER0_DELAY_SELECT_LEN = 2 ;
+
+static const uint8_t P9N2_PEC_SKITTER_FORCE_REG_F_READ = 0 ;
+
+static const uint8_t P9N2_PEC_SKITTER_MODE_REG_HOLD_SAMPLE = 0 ;
+static const uint8_t P9N2_PEC_SKITTER_MODE_REG_DISABLE_STICKINESS = 1 ;
+static const uint8_t P9N2_PEC_SKITTER_MODE_REG_UNUSED1 = 2 ;
+static const uint8_t P9N2_PEC_SKITTER_MODE_REG_UNUSED1_LEN = 2 ;
+static const uint8_t P9N2_PEC_SKITTER_MODE_REG_HOLD_DBGTRIG_SEL = 4 ;
+static const uint8_t P9N2_PEC_SKITTER_MODE_REG_HOLD_DBGTRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_PEC_SKITTER_MODE_REG_RESET_TRIG_SEL = 6 ;
+static const uint8_t P9N2_PEC_SKITTER_MODE_REG_RESET_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_PEC_SKITTER_MODE_REG_SAMPLE_GUTS = 8 ;
+static const uint8_t P9N2_PEC_SKITTER_MODE_REG_SAMPLE_GUTS_LEN = 2 ;
+static const uint8_t P9N2_PEC_SKITTER_MODE_REG_HOLD_SAMPLE_WITH_TRIGGER = 44 ;
+static const uint8_t P9N2_PEC_SKITTER_MODE_REG_DATA_V_LT = 45 ;
+
+static const uint8_t P9N2_PEC_SLAVE_CONFIG_REG_CFG_DISABLE_PERV_THOLD_CHECK = 0 ;
+static const uint8_t P9N2_PEC_SLAVE_CONFIG_REG_CFG_DISABLE_MALF_PULSE_GEN = 1 ;
+static const uint8_t P9N2_PEC_SLAVE_CONFIG_REG_CFG_STOP_HANG_CNT_SYS_XSTP = 2 ;
+static const uint8_t P9N2_PEC_SLAVE_CONFIG_REG_CFG_DISABLE_CL_ATOMIC_LOCK = 3 ;
+static const uint8_t P9N2_PEC_SLAVE_CONFIG_REG_CFG_DISABLE_HEARTBEAT = 4 ;
+static const uint8_t P9N2_PEC_SLAVE_CONFIG_REG_CFG_DISABLE_FORCE_TO_ZERO = 5 ;
+static const uint8_t P9N2_PEC_SLAVE_CONFIG_REG_CFG_PM_DISABLE = 6 ;
+static const uint8_t P9N2_PEC_SLAVE_CONFIG_REG_CFG_PM_MUX_DISABLE = 7 ;
+static const uint8_t P9N2_PEC_SLAVE_CONFIG_REG_ERROR_MASK = 8 ;
+static const uint8_t P9N2_PEC_SLAVE_CONFIG_REG_ERROR_MASK_LEN = 6 ;
+
+static const uint8_t P9N2_PU_SMF_CONFIG_REG_0_CONFIG0 = 0 ;
+static const uint8_t P9N2_PU_SMF_CONFIG_REG_0_CONFIG0_LEN = 2 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM2_SM_STATUS_CREQ0 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_SM_STATUS_PRB0 = 1 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_SM_STATUS_CREQ1 = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_SM_STATUS_PRB1 = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_SM_STATUS_XATS = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_SM_STATUS_PWR0 = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_SM_STATUS_PWR1 = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_SM_STATUS_CHGRATE = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_SM_STATUS_MRBGP = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_SM_STATUS_MRBGP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_SM_STATUS_MRBSP = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_SM_STATUS_MRBSP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_SM_STATUS_FENCE0 = 16 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_SM_STATUS_FENCE0_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_SM_STATUS_FENCE1 = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_SM_STATUS_FENCE1_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_SM_STATUS_PBLN = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_SM_STATUS_PBNNG = 25 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_SM_STATUS_PBRNVG = 26 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_SM_STATUS_N0REQ = 27 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_SM_STATUS_N0DGD = 28 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_SM_STATUS_N1REQ = 29 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_SM_STATUS_N1DGD = 30 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_SM_STATUS_MMIO = 31 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_SM_STATUS_ATSXLATE = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_SM_STATUS_PBRSP = 33 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_SM_STATUS_N0RSP = 34 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_SM_STATUS_N1RSP = 35 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_SM_STATUS_XARSP = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_SM_STATUS_SACOLL = 37 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_SM_STATUS_FREE = 38 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_SM_STATUS_RESERVED1 = 39 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_SM_STATUS_MRBCP = 40 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_SM_STATUS_MRBCP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_SM_STATUS_PERF_LSTATE = 44 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_SM_STATUS_PERF_LSTATE_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_SM_STATUS_RESERVED2 = 46 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM2_SM_STATUS_RESERVED2_LEN = 2 ;
+
+static const uint8_t P9N2_PU_NPU0_SM0_SM_STATUS_CREQ0 = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM0_SM_STATUS_PRB0 = 1 ;
+static const uint8_t P9N2_PU_NPU0_SM0_SM_STATUS_CREQ1 = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM0_SM_STATUS_PRB1 = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM0_SM_STATUS_XATS = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM0_SM_STATUS_PWR0 = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM0_SM_STATUS_PWR1 = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM0_SM_STATUS_CHGRATE = 7 ;
+static const uint8_t P9N2_PU_NPU0_SM0_SM_STATUS_MRBGP = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM0_SM_STATUS_MRBGP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM0_SM_STATUS_MRBSP = 12 ;
+static const uint8_t P9N2_PU_NPU0_SM0_SM_STATUS_MRBSP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM0_SM_STATUS_FENCE0 = 16 ;
+static const uint8_t P9N2_PU_NPU0_SM0_SM_STATUS_FENCE0_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM0_SM_STATUS_FENCE1 = 20 ;
+static const uint8_t P9N2_PU_NPU0_SM0_SM_STATUS_FENCE1_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM0_SM_STATUS_PBLN = 24 ;
+static const uint8_t P9N2_PU_NPU0_SM0_SM_STATUS_PBNNG = 25 ;
+static const uint8_t P9N2_PU_NPU0_SM0_SM_STATUS_PBRNVG = 26 ;
+static const uint8_t P9N2_PU_NPU0_SM0_SM_STATUS_N0REQ = 27 ;
+static const uint8_t P9N2_PU_NPU0_SM0_SM_STATUS_N0DGD = 28 ;
+static const uint8_t P9N2_PU_NPU0_SM0_SM_STATUS_N1REQ = 29 ;
+static const uint8_t P9N2_PU_NPU0_SM0_SM_STATUS_N1DGD = 30 ;
+static const uint8_t P9N2_PU_NPU0_SM0_SM_STATUS_MMIO = 31 ;
+static const uint8_t P9N2_PU_NPU0_SM0_SM_STATUS_ATSXLATE = 32 ;
+static const uint8_t P9N2_PU_NPU0_SM0_SM_STATUS_PBRSP = 33 ;
+static const uint8_t P9N2_PU_NPU0_SM0_SM_STATUS_N0RSP = 34 ;
+static const uint8_t P9N2_PU_NPU0_SM0_SM_STATUS_N1RSP = 35 ;
+static const uint8_t P9N2_PU_NPU0_SM0_SM_STATUS_XARSP = 36 ;
+static const uint8_t P9N2_PU_NPU0_SM0_SM_STATUS_SACOLL = 37 ;
+static const uint8_t P9N2_PU_NPU0_SM0_SM_STATUS_FREE = 38 ;
+static const uint8_t P9N2_PU_NPU0_SM0_SM_STATUS_RESERVED1 = 39 ;
+static const uint8_t P9N2_PU_NPU0_SM0_SM_STATUS_MRBCP = 40 ;
+static const uint8_t P9N2_PU_NPU0_SM0_SM_STATUS_MRBCP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM0_SM_STATUS_PERF_LSTATE = 44 ;
+static const uint8_t P9N2_PU_NPU0_SM0_SM_STATUS_PERF_LSTATE_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM0_SM_STATUS_RESERVED2 = 46 ;
+static const uint8_t P9N2_PU_NPU0_SM0_SM_STATUS_RESERVED2_LEN = 2 ;
+
+static const uint8_t P9N2_PU_NPU2_SM3_SM_STATUS_CREQ0 = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM3_SM_STATUS_PRB0 = 1 ;
+static const uint8_t P9N2_PU_NPU2_SM3_SM_STATUS_CREQ1 = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM3_SM_STATUS_PRB1 = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM3_SM_STATUS_XATS = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM3_SM_STATUS_PWR0 = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM3_SM_STATUS_PWR1 = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM3_SM_STATUS_CHGRATE = 7 ;
+static const uint8_t P9N2_PU_NPU2_SM3_SM_STATUS_MRBGP = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM3_SM_STATUS_MRBGP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM3_SM_STATUS_MRBSP = 12 ;
+static const uint8_t P9N2_PU_NPU2_SM3_SM_STATUS_MRBSP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM3_SM_STATUS_FENCE0 = 16 ;
+static const uint8_t P9N2_PU_NPU2_SM3_SM_STATUS_FENCE0_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM3_SM_STATUS_FENCE1 = 20 ;
+static const uint8_t P9N2_PU_NPU2_SM3_SM_STATUS_FENCE1_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM3_SM_STATUS_PBLN = 24 ;
+static const uint8_t P9N2_PU_NPU2_SM3_SM_STATUS_PBNNG = 25 ;
+static const uint8_t P9N2_PU_NPU2_SM3_SM_STATUS_PBRNVG = 26 ;
+static const uint8_t P9N2_PU_NPU2_SM3_SM_STATUS_N0REQ = 27 ;
+static const uint8_t P9N2_PU_NPU2_SM3_SM_STATUS_N0DGD = 28 ;
+static const uint8_t P9N2_PU_NPU2_SM3_SM_STATUS_N1REQ = 29 ;
+static const uint8_t P9N2_PU_NPU2_SM3_SM_STATUS_N1DGD = 30 ;
+static const uint8_t P9N2_PU_NPU2_SM3_SM_STATUS_MMIO = 31 ;
+static const uint8_t P9N2_PU_NPU2_SM3_SM_STATUS_ATSXLATE = 32 ;
+static const uint8_t P9N2_PU_NPU2_SM3_SM_STATUS_PBRSP = 33 ;
+static const uint8_t P9N2_PU_NPU2_SM3_SM_STATUS_N0RSP = 34 ;
+static const uint8_t P9N2_PU_NPU2_SM3_SM_STATUS_N1RSP = 35 ;
+static const uint8_t P9N2_PU_NPU2_SM3_SM_STATUS_XARSP = 36 ;
+static const uint8_t P9N2_PU_NPU2_SM3_SM_STATUS_SACOLL = 37 ;
+static const uint8_t P9N2_PU_NPU2_SM3_SM_STATUS_FREE = 38 ;
+static const uint8_t P9N2_PU_NPU2_SM3_SM_STATUS_RESERVED1 = 39 ;
+static const uint8_t P9N2_PU_NPU2_SM3_SM_STATUS_MRBCP = 40 ;
+static const uint8_t P9N2_PU_NPU2_SM3_SM_STATUS_MRBCP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM3_SM_STATUS_PERF_LSTATE = 44 ;
+static const uint8_t P9N2_PU_NPU2_SM3_SM_STATUS_PERF_LSTATE_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM3_SM_STATUS_RESERVED2 = 46 ;
+static const uint8_t P9N2_PU_NPU2_SM3_SM_STATUS_RESERVED2_LEN = 2 ;
+
+static const uint8_t P9N2_PU_NPU0_SM3_SM_STATUS_CREQ0 = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM3_SM_STATUS_PRB0 = 1 ;
+static const uint8_t P9N2_PU_NPU0_SM3_SM_STATUS_CREQ1 = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM3_SM_STATUS_PRB1 = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM3_SM_STATUS_XATS = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM3_SM_STATUS_PWR0 = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM3_SM_STATUS_PWR1 = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM3_SM_STATUS_CHGRATE = 7 ;
+static const uint8_t P9N2_PU_NPU0_SM3_SM_STATUS_MRBGP = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM3_SM_STATUS_MRBGP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM3_SM_STATUS_MRBSP = 12 ;
+static const uint8_t P9N2_PU_NPU0_SM3_SM_STATUS_MRBSP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM3_SM_STATUS_FENCE0 = 16 ;
+static const uint8_t P9N2_PU_NPU0_SM3_SM_STATUS_FENCE0_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM3_SM_STATUS_FENCE1 = 20 ;
+static const uint8_t P9N2_PU_NPU0_SM3_SM_STATUS_FENCE1_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM3_SM_STATUS_PBLN = 24 ;
+static const uint8_t P9N2_PU_NPU0_SM3_SM_STATUS_PBNNG = 25 ;
+static const uint8_t P9N2_PU_NPU0_SM3_SM_STATUS_PBRNVG = 26 ;
+static const uint8_t P9N2_PU_NPU0_SM3_SM_STATUS_N0REQ = 27 ;
+static const uint8_t P9N2_PU_NPU0_SM3_SM_STATUS_N0DGD = 28 ;
+static const uint8_t P9N2_PU_NPU0_SM3_SM_STATUS_N1REQ = 29 ;
+static const uint8_t P9N2_PU_NPU0_SM3_SM_STATUS_N1DGD = 30 ;
+static const uint8_t P9N2_PU_NPU0_SM3_SM_STATUS_MMIO = 31 ;
+static const uint8_t P9N2_PU_NPU0_SM3_SM_STATUS_ATSXLATE = 32 ;
+static const uint8_t P9N2_PU_NPU0_SM3_SM_STATUS_PBRSP = 33 ;
+static const uint8_t P9N2_PU_NPU0_SM3_SM_STATUS_N0RSP = 34 ;
+static const uint8_t P9N2_PU_NPU0_SM3_SM_STATUS_N1RSP = 35 ;
+static const uint8_t P9N2_PU_NPU0_SM3_SM_STATUS_XARSP = 36 ;
+static const uint8_t P9N2_PU_NPU0_SM3_SM_STATUS_SACOLL = 37 ;
+static const uint8_t P9N2_PU_NPU0_SM3_SM_STATUS_FREE = 38 ;
+static const uint8_t P9N2_PU_NPU0_SM3_SM_STATUS_RESERVED1 = 39 ;
+static const uint8_t P9N2_PU_NPU0_SM3_SM_STATUS_MRBCP = 40 ;
+static const uint8_t P9N2_PU_NPU0_SM3_SM_STATUS_MRBCP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM3_SM_STATUS_PERF_LSTATE = 44 ;
+static const uint8_t P9N2_PU_NPU0_SM3_SM_STATUS_PERF_LSTATE_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM3_SM_STATUS_RESERVED2 = 46 ;
+static const uint8_t P9N2_PU_NPU0_SM3_SM_STATUS_RESERVED2_LEN = 2 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM0_SM_STATUS_CREQ0 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_SM_STATUS_PRB0 = 1 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_SM_STATUS_CREQ1 = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_SM_STATUS_PRB1 = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_SM_STATUS_XATS = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_SM_STATUS_PWR0 = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_SM_STATUS_PWR1 = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_SM_STATUS_CHGRATE = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_SM_STATUS_MRBGP = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_SM_STATUS_MRBGP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_SM_STATUS_MRBSP = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_SM_STATUS_MRBSP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_SM_STATUS_FENCE0 = 16 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_SM_STATUS_FENCE0_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_SM_STATUS_FENCE1 = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_SM_STATUS_FENCE1_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_SM_STATUS_PBLN = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_SM_STATUS_PBNNG = 25 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_SM_STATUS_PBRNVG = 26 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_SM_STATUS_N0REQ = 27 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_SM_STATUS_N0DGD = 28 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_SM_STATUS_N1REQ = 29 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_SM_STATUS_N1DGD = 30 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_SM_STATUS_MMIO = 31 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_SM_STATUS_ATSXLATE = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_SM_STATUS_PBRSP = 33 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_SM_STATUS_N0RSP = 34 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_SM_STATUS_N1RSP = 35 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_SM_STATUS_XARSP = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_SM_STATUS_SACOLL = 37 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_SM_STATUS_FREE = 38 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_SM_STATUS_RESERVED1 = 39 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_SM_STATUS_MRBCP = 40 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_SM_STATUS_MRBCP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_SM_STATUS_PERF_LSTATE = 44 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_SM_STATUS_PERF_LSTATE_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_SM_STATUS_RESERVED2 = 46 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_SM_STATUS_RESERVED2_LEN = 2 ;
+
+static const uint8_t P9N2_PU_NPU0_SM_STATUS_CREQ0 = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM_STATUS_PRB0 = 1 ;
+static const uint8_t P9N2_PU_NPU0_SM_STATUS_CREQ1 = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM_STATUS_PRB1 = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM_STATUS_XATS = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM_STATUS_PWR0 = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM_STATUS_PWR1 = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM_STATUS_CHGRATE = 7 ;
+static const uint8_t P9N2_PU_NPU0_SM_STATUS_MRBGP = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM_STATUS_MRBGP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM_STATUS_MRBSP = 12 ;
+static const uint8_t P9N2_PU_NPU0_SM_STATUS_MRBSP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM_STATUS_FENCE0 = 16 ;
+static const uint8_t P9N2_PU_NPU0_SM_STATUS_FENCE0_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM_STATUS_FENCE1 = 20 ;
+static const uint8_t P9N2_PU_NPU0_SM_STATUS_FENCE1_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM_STATUS_PBLN = 24 ;
+static const uint8_t P9N2_PU_NPU0_SM_STATUS_PBNNG = 25 ;
+static const uint8_t P9N2_PU_NPU0_SM_STATUS_PBRNVG = 26 ;
+static const uint8_t P9N2_PU_NPU0_SM_STATUS_N0REQ = 27 ;
+static const uint8_t P9N2_PU_NPU0_SM_STATUS_N0DGD = 28 ;
+static const uint8_t P9N2_PU_NPU0_SM_STATUS_N1REQ = 29 ;
+static const uint8_t P9N2_PU_NPU0_SM_STATUS_N1DGD = 30 ;
+static const uint8_t P9N2_PU_NPU0_SM_STATUS_MMIO = 31 ;
+static const uint8_t P9N2_PU_NPU0_SM_STATUS_ATSXLATE = 32 ;
+static const uint8_t P9N2_PU_NPU0_SM_STATUS_PBRSP = 33 ;
+static const uint8_t P9N2_PU_NPU0_SM_STATUS_N0RSP = 34 ;
+static const uint8_t P9N2_PU_NPU0_SM_STATUS_N1RSP = 35 ;
+static const uint8_t P9N2_PU_NPU0_SM_STATUS_XARSP = 36 ;
+static const uint8_t P9N2_PU_NPU0_SM_STATUS_SACOLL = 37 ;
+static const uint8_t P9N2_PU_NPU0_SM_STATUS_FREE = 38 ;
+static const uint8_t P9N2_PU_NPU0_SM_STATUS_RESERVED1 = 39 ;
+static const uint8_t P9N2_PU_NPU0_SM_STATUS_MRBCP = 40 ;
+static const uint8_t P9N2_PU_NPU0_SM_STATUS_MRBCP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM_STATUS_PERF_LSTATE = 44 ;
+static const uint8_t P9N2_PU_NPU0_SM_STATUS_PERF_LSTATE_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM_STATUS_RESERVED2 = 46 ;
+static const uint8_t P9N2_PU_NPU0_SM_STATUS_RESERVED2_LEN = 2 ;
+
+static const uint8_t P9N2_PU_NPU2_SM2_SM_STATUS_CREQ0 = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM2_SM_STATUS_PRB0 = 1 ;
+static const uint8_t P9N2_PU_NPU2_SM2_SM_STATUS_CREQ1 = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM2_SM_STATUS_PRB1 = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM2_SM_STATUS_XATS = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM2_SM_STATUS_PWR0 = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM2_SM_STATUS_PWR1 = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM2_SM_STATUS_CHGRATE = 7 ;
+static const uint8_t P9N2_PU_NPU2_SM2_SM_STATUS_MRBGP = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM2_SM_STATUS_MRBGP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM2_SM_STATUS_MRBSP = 12 ;
+static const uint8_t P9N2_PU_NPU2_SM2_SM_STATUS_MRBSP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM2_SM_STATUS_FENCE0 = 16 ;
+static const uint8_t P9N2_PU_NPU2_SM2_SM_STATUS_FENCE0_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM2_SM_STATUS_FENCE1 = 20 ;
+static const uint8_t P9N2_PU_NPU2_SM2_SM_STATUS_FENCE1_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM2_SM_STATUS_PBLN = 24 ;
+static const uint8_t P9N2_PU_NPU2_SM2_SM_STATUS_PBNNG = 25 ;
+static const uint8_t P9N2_PU_NPU2_SM2_SM_STATUS_PBRNVG = 26 ;
+static const uint8_t P9N2_PU_NPU2_SM2_SM_STATUS_N0REQ = 27 ;
+static const uint8_t P9N2_PU_NPU2_SM2_SM_STATUS_N0DGD = 28 ;
+static const uint8_t P9N2_PU_NPU2_SM2_SM_STATUS_N1REQ = 29 ;
+static const uint8_t P9N2_PU_NPU2_SM2_SM_STATUS_N1DGD = 30 ;
+static const uint8_t P9N2_PU_NPU2_SM2_SM_STATUS_MMIO = 31 ;
+static const uint8_t P9N2_PU_NPU2_SM2_SM_STATUS_ATSXLATE = 32 ;
+static const uint8_t P9N2_PU_NPU2_SM2_SM_STATUS_PBRSP = 33 ;
+static const uint8_t P9N2_PU_NPU2_SM2_SM_STATUS_N0RSP = 34 ;
+static const uint8_t P9N2_PU_NPU2_SM2_SM_STATUS_N1RSP = 35 ;
+static const uint8_t P9N2_PU_NPU2_SM2_SM_STATUS_XARSP = 36 ;
+static const uint8_t P9N2_PU_NPU2_SM2_SM_STATUS_SACOLL = 37 ;
+static const uint8_t P9N2_PU_NPU2_SM2_SM_STATUS_FREE = 38 ;
+static const uint8_t P9N2_PU_NPU2_SM2_SM_STATUS_RESERVED1 = 39 ;
+static const uint8_t P9N2_PU_NPU2_SM2_SM_STATUS_MRBCP = 40 ;
+static const uint8_t P9N2_PU_NPU2_SM2_SM_STATUS_MRBCP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM2_SM_STATUS_PERF_LSTATE = 44 ;
+static const uint8_t P9N2_PU_NPU2_SM2_SM_STATUS_PERF_LSTATE_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM2_SM_STATUS_RESERVED2 = 46 ;
+static const uint8_t P9N2_PU_NPU2_SM2_SM_STATUS_RESERVED2_LEN = 2 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM_STATUS_CREQ0 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM_STATUS_PRB0 = 1 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM_STATUS_CREQ1 = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM_STATUS_PRB1 = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM_STATUS_XATS = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM_STATUS_PWR0 = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM_STATUS_PWR1 = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM_STATUS_CHGRATE = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM_STATUS_MRBGP = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM_STATUS_MRBGP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM_STATUS_MRBSP = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM_STATUS_MRBSP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM_STATUS_FENCE0 = 16 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM_STATUS_FENCE0_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM_STATUS_FENCE1 = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM_STATUS_FENCE1_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM_STATUS_PBLN = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM_STATUS_PBNNG = 25 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM_STATUS_PBRNVG = 26 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM_STATUS_N0REQ = 27 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM_STATUS_N0DGD = 28 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM_STATUS_N1REQ = 29 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM_STATUS_N1DGD = 30 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM_STATUS_MMIO = 31 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM_STATUS_ATSXLATE = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM_STATUS_PBRSP = 33 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM_STATUS_N0RSP = 34 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM_STATUS_N1RSP = 35 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM_STATUS_XARSP = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM_STATUS_SACOLL = 37 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM_STATUS_FREE = 38 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM_STATUS_RESERVED1 = 39 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM_STATUS_MRBCP = 40 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM_STATUS_MRBCP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM_STATUS_PERF_LSTATE = 44 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM_STATUS_PERF_LSTATE_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM_STATUS_RESERVED2 = 46 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM_STATUS_RESERVED2_LEN = 2 ;
+
+static const uint8_t P9N2_PU_NPU0_SM2_SM_STATUS_CREQ0 = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM2_SM_STATUS_PRB0 = 1 ;
+static const uint8_t P9N2_PU_NPU0_SM2_SM_STATUS_CREQ1 = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM2_SM_STATUS_PRB1 = 3 ;
+static const uint8_t P9N2_PU_NPU0_SM2_SM_STATUS_XATS = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM2_SM_STATUS_PWR0 = 5 ;
+static const uint8_t P9N2_PU_NPU0_SM2_SM_STATUS_PWR1 = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM2_SM_STATUS_CHGRATE = 7 ;
+static const uint8_t P9N2_PU_NPU0_SM2_SM_STATUS_MRBGP = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM2_SM_STATUS_MRBGP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM2_SM_STATUS_MRBSP = 12 ;
+static const uint8_t P9N2_PU_NPU0_SM2_SM_STATUS_MRBSP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM2_SM_STATUS_FENCE0 = 16 ;
+static const uint8_t P9N2_PU_NPU0_SM2_SM_STATUS_FENCE0_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM2_SM_STATUS_FENCE1 = 20 ;
+static const uint8_t P9N2_PU_NPU0_SM2_SM_STATUS_FENCE1_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM2_SM_STATUS_PBLN = 24 ;
+static const uint8_t P9N2_PU_NPU0_SM2_SM_STATUS_PBNNG = 25 ;
+static const uint8_t P9N2_PU_NPU0_SM2_SM_STATUS_PBRNVG = 26 ;
+static const uint8_t P9N2_PU_NPU0_SM2_SM_STATUS_N0REQ = 27 ;
+static const uint8_t P9N2_PU_NPU0_SM2_SM_STATUS_N0DGD = 28 ;
+static const uint8_t P9N2_PU_NPU0_SM2_SM_STATUS_N1REQ = 29 ;
+static const uint8_t P9N2_PU_NPU0_SM2_SM_STATUS_N1DGD = 30 ;
+static const uint8_t P9N2_PU_NPU0_SM2_SM_STATUS_MMIO = 31 ;
+static const uint8_t P9N2_PU_NPU0_SM2_SM_STATUS_ATSXLATE = 32 ;
+static const uint8_t P9N2_PU_NPU0_SM2_SM_STATUS_PBRSP = 33 ;
+static const uint8_t P9N2_PU_NPU0_SM2_SM_STATUS_N0RSP = 34 ;
+static const uint8_t P9N2_PU_NPU0_SM2_SM_STATUS_N1RSP = 35 ;
+static const uint8_t P9N2_PU_NPU0_SM2_SM_STATUS_XARSP = 36 ;
+static const uint8_t P9N2_PU_NPU0_SM2_SM_STATUS_SACOLL = 37 ;
+static const uint8_t P9N2_PU_NPU0_SM2_SM_STATUS_FREE = 38 ;
+static const uint8_t P9N2_PU_NPU0_SM2_SM_STATUS_RESERVED1 = 39 ;
+static const uint8_t P9N2_PU_NPU0_SM2_SM_STATUS_MRBCP = 40 ;
+static const uint8_t P9N2_PU_NPU0_SM2_SM_STATUS_MRBCP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU0_SM2_SM_STATUS_PERF_LSTATE = 44 ;
+static const uint8_t P9N2_PU_NPU0_SM2_SM_STATUS_PERF_LSTATE_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM2_SM_STATUS_RESERVED2 = 46 ;
+static const uint8_t P9N2_PU_NPU0_SM2_SM_STATUS_RESERVED2_LEN = 2 ;
+
+static const uint8_t P9N2_PU_NPU2_SM0_SM_STATUS_CREQ0 = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM0_SM_STATUS_PRB0 = 1 ;
+static const uint8_t P9N2_PU_NPU2_SM0_SM_STATUS_CREQ1 = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM0_SM_STATUS_PRB1 = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM0_SM_STATUS_XATS = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM0_SM_STATUS_PWR0 = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM0_SM_STATUS_PWR1 = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM0_SM_STATUS_CHGRATE = 7 ;
+static const uint8_t P9N2_PU_NPU2_SM0_SM_STATUS_MRBGP = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM0_SM_STATUS_MRBGP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM0_SM_STATUS_MRBSP = 12 ;
+static const uint8_t P9N2_PU_NPU2_SM0_SM_STATUS_MRBSP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM0_SM_STATUS_FENCE0 = 16 ;
+static const uint8_t P9N2_PU_NPU2_SM0_SM_STATUS_FENCE0_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM0_SM_STATUS_FENCE1 = 20 ;
+static const uint8_t P9N2_PU_NPU2_SM0_SM_STATUS_FENCE1_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM0_SM_STATUS_PBLN = 24 ;
+static const uint8_t P9N2_PU_NPU2_SM0_SM_STATUS_PBNNG = 25 ;
+static const uint8_t P9N2_PU_NPU2_SM0_SM_STATUS_PBRNVG = 26 ;
+static const uint8_t P9N2_PU_NPU2_SM0_SM_STATUS_N0REQ = 27 ;
+static const uint8_t P9N2_PU_NPU2_SM0_SM_STATUS_N0DGD = 28 ;
+static const uint8_t P9N2_PU_NPU2_SM0_SM_STATUS_N1REQ = 29 ;
+static const uint8_t P9N2_PU_NPU2_SM0_SM_STATUS_N1DGD = 30 ;
+static const uint8_t P9N2_PU_NPU2_SM0_SM_STATUS_MMIO = 31 ;
+static const uint8_t P9N2_PU_NPU2_SM0_SM_STATUS_ATSXLATE = 32 ;
+static const uint8_t P9N2_PU_NPU2_SM0_SM_STATUS_PBRSP = 33 ;
+static const uint8_t P9N2_PU_NPU2_SM0_SM_STATUS_N0RSP = 34 ;
+static const uint8_t P9N2_PU_NPU2_SM0_SM_STATUS_N1RSP = 35 ;
+static const uint8_t P9N2_PU_NPU2_SM0_SM_STATUS_XARSP = 36 ;
+static const uint8_t P9N2_PU_NPU2_SM0_SM_STATUS_SACOLL = 37 ;
+static const uint8_t P9N2_PU_NPU2_SM0_SM_STATUS_FREE = 38 ;
+static const uint8_t P9N2_PU_NPU2_SM0_SM_STATUS_RESERVED1 = 39 ;
+static const uint8_t P9N2_PU_NPU2_SM0_SM_STATUS_MRBCP = 40 ;
+static const uint8_t P9N2_PU_NPU2_SM0_SM_STATUS_MRBCP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM0_SM_STATUS_PERF_LSTATE = 44 ;
+static const uint8_t P9N2_PU_NPU2_SM0_SM_STATUS_PERF_LSTATE_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM0_SM_STATUS_RESERVED2 = 46 ;
+static const uint8_t P9N2_PU_NPU2_SM0_SM_STATUS_RESERVED2_LEN = 2 ;
+
+static const uint8_t P9N2_PU_NPU2_SM_STATUS_CREQ0 = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM_STATUS_PRB0 = 1 ;
+static const uint8_t P9N2_PU_NPU2_SM_STATUS_CREQ1 = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM_STATUS_PRB1 = 3 ;
+static const uint8_t P9N2_PU_NPU2_SM_STATUS_XATS = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM_STATUS_PWR0 = 5 ;
+static const uint8_t P9N2_PU_NPU2_SM_STATUS_PWR1 = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM_STATUS_CHGRATE = 7 ;
+static const uint8_t P9N2_PU_NPU2_SM_STATUS_MRBGP = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM_STATUS_MRBGP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM_STATUS_MRBSP = 12 ;
+static const uint8_t P9N2_PU_NPU2_SM_STATUS_MRBSP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM_STATUS_FENCE0 = 16 ;
+static const uint8_t P9N2_PU_NPU2_SM_STATUS_FENCE0_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM_STATUS_FENCE1 = 20 ;
+static const uint8_t P9N2_PU_NPU2_SM_STATUS_FENCE1_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM_STATUS_PBLN = 24 ;
+static const uint8_t P9N2_PU_NPU2_SM_STATUS_PBNNG = 25 ;
+static const uint8_t P9N2_PU_NPU2_SM_STATUS_PBRNVG = 26 ;
+static const uint8_t P9N2_PU_NPU2_SM_STATUS_N0REQ = 27 ;
+static const uint8_t P9N2_PU_NPU2_SM_STATUS_N0DGD = 28 ;
+static const uint8_t P9N2_PU_NPU2_SM_STATUS_N1REQ = 29 ;
+static const uint8_t P9N2_PU_NPU2_SM_STATUS_N1DGD = 30 ;
+static const uint8_t P9N2_PU_NPU2_SM_STATUS_MMIO = 31 ;
+static const uint8_t P9N2_PU_NPU2_SM_STATUS_ATSXLATE = 32 ;
+static const uint8_t P9N2_PU_NPU2_SM_STATUS_PBRSP = 33 ;
+static const uint8_t P9N2_PU_NPU2_SM_STATUS_N0RSP = 34 ;
+static const uint8_t P9N2_PU_NPU2_SM_STATUS_N1RSP = 35 ;
+static const uint8_t P9N2_PU_NPU2_SM_STATUS_XARSP = 36 ;
+static const uint8_t P9N2_PU_NPU2_SM_STATUS_SACOLL = 37 ;
+static const uint8_t P9N2_PU_NPU2_SM_STATUS_FREE = 38 ;
+static const uint8_t P9N2_PU_NPU2_SM_STATUS_RESERVED1 = 39 ;
+static const uint8_t P9N2_PU_NPU2_SM_STATUS_MRBCP = 40 ;
+static const uint8_t P9N2_PU_NPU2_SM_STATUS_MRBCP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU2_SM_STATUS_PERF_LSTATE = 44 ;
+static const uint8_t P9N2_PU_NPU2_SM_STATUS_PERF_LSTATE_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM_STATUS_RESERVED2 = 46 ;
+static const uint8_t P9N2_PU_NPU2_SM_STATUS_RESERVED2_LEN = 2 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM3_SM_STATUS_CREQ0 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_SM_STATUS_PRB0 = 1 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_SM_STATUS_CREQ1 = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_SM_STATUS_PRB1 = 3 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_SM_STATUS_XATS = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_SM_STATUS_PWR0 = 5 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_SM_STATUS_PWR1 = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_SM_STATUS_CHGRATE = 7 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_SM_STATUS_MRBGP = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_SM_STATUS_MRBGP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_SM_STATUS_MRBSP = 12 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_SM_STATUS_MRBSP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_SM_STATUS_FENCE0 = 16 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_SM_STATUS_FENCE0_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_SM_STATUS_FENCE1 = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_SM_STATUS_FENCE1_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_SM_STATUS_PBLN = 24 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_SM_STATUS_PBNNG = 25 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_SM_STATUS_PBRNVG = 26 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_SM_STATUS_N0REQ = 27 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_SM_STATUS_N0DGD = 28 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_SM_STATUS_N1REQ = 29 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_SM_STATUS_N1DGD = 30 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_SM_STATUS_MMIO = 31 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_SM_STATUS_ATSXLATE = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_SM_STATUS_PBRSP = 33 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_SM_STATUS_N0RSP = 34 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_SM_STATUS_N1RSP = 35 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_SM_STATUS_XARSP = 36 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_SM_STATUS_SACOLL = 37 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_SM_STATUS_FREE = 38 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_SM_STATUS_RESERVED1 = 39 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_SM_STATUS_MRBCP = 40 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_SM_STATUS_MRBCP_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_SM_STATUS_PERF_LSTATE = 44 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_SM_STATUS_PERF_LSTATE_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_SM_STATUS_RESERVED2 = 46 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_SM_STATUS_RESERVED2_LEN = 2 ;
+
+static const uint8_t P9N2_PU_SND_MODE_REG_ENABLE_TRC_GLB_TRIG0 = 0 ;
+static const uint8_t P9N2_PU_SND_MODE_REG_ENABLE_TRC_GLB_TRIG1 = 1 ;
+static const uint8_t P9N2_PU_SND_MODE_REG_ENABLE_GLB_PULSE = 2 ;
+static const uint8_t P9N2_PU_SND_MODE_REG_SINGLE_OUTSTANDING_CMD = 3 ;
+static const uint8_t P9N2_PU_SND_MODE_REG_PROG_REQ_DELAY = 4 ;
+static const uint8_t P9N2_PU_SND_MODE_REG_PROG_REQ_DELAY_LEN = 4 ;
+static const uint8_t P9N2_PU_SND_MODE_REG_DISABLE_ERR_CMD = 8 ;
+static const uint8_t P9N2_PU_SND_MODE_REG_DISABLE_HTM_CMD = 9 ;
+static const uint8_t P9N2_PU_SND_MODE_REG_DISABLE_TRACE_CMD = 10 ;
+static const uint8_t P9N2_PU_SND_MODE_REG_DISABLE_TOD_CMD = 11 ;
+static const uint8_t P9N2_PU_SND_MODE_REG_DISABLE_XSCOM_CMD = 12 ;
+static const uint8_t P9N2_PU_SND_MODE_REG_ENABLE_CLR_ERR_CMD = 13 ;
+static const uint8_t P9N2_PU_SND_MODE_REG_OVERRIDE_PBINIT_ERR_CMD = 14 ;
+static const uint8_t P9N2_PU_SND_MODE_REG_OVERRIDE_PBINIT_HTM_CMD = 15 ;
+static const uint8_t P9N2_PU_SND_MODE_REG_OVERRIDE_PBINIT_TRACE_CMD = 16 ;
+static const uint8_t P9N2_PU_SND_MODE_REG_OVERRIDE_PBINIT_TOD_CMD = 17 ;
+static const uint8_t P9N2_PU_SND_MODE_REG_OVERRIDE_PBINIT_XSCOM_CMD = 18 ;
+static const uint8_t P9N2_PU_SND_MODE_REG_DISABLE_CHECKSTOP = 19 ;
+static const uint8_t P9N2_PU_SND_MODE_REG_MANUAL_SET_PB_STOP = 20 ;
+static const uint8_t P9N2_PU_SND_MODE_REG_MANUAL_CLR_PB_STOP = 21 ;
+static const uint8_t P9N2_PU_SND_MODE_REG_PB_STOP = 22 ;
+static const uint8_t P9N2_PU_SND_MODE_REG_MANUAL_PB_SWITCH_ABCD = 25 ;
+static const uint8_t P9N2_PU_SND_MODE_REG_ENABLE_RECEIVE_OWN_TRIGGER = 26 ;
+static const uint8_t P9N2_PU_SND_MODE_REG_ENABLE_RECEIVE_OWN_TRIGGER_LEN = 2 ;
+static const uint8_t P9N2_PU_SND_MODE_REG_ENABLE_RECEIVE_OWN_TOD = 28 ;
+static const uint8_t P9N2_PU_SND_MODE_REG_RESET_TOD_STATE = 29 ;
+static const uint8_t P9N2_PU_SND_MODE_REG_ENABLE_PB_SWITCH_AB = 30 ;
+static const uint8_t P9N2_PU_SND_MODE_REG_ENABLE_PB_SWITCH_CD = 31 ;
+
+static const uint8_t P9N2_PU_SND_STAT_REG_ERR_CMD_OVERRUN = 0 ;
+static const uint8_t P9N2_PU_SND_STAT_REG_TRC_CMD_OVERRUN = 1 ;
+static const uint8_t P9N2_PU_SND_STAT_REG_XSC_CMD_OVERRUN = 2 ;
+static const uint8_t P9N2_PU_SND_STAT_REG_HTM_CMD_OVERRUN = 3 ;
+static const uint8_t P9N2_PU_SND_STAT_REG_TOD_CMD_OVERRUN = 4 ;
+static const uint8_t P9N2_PU_SND_STAT_REG_CMD_COUNT_ERR = 5 ;
+static const uint8_t P9N2_PU_SND_STAT_REG_PB_OP_HANG_ERR = 6 ;
+static const uint8_t P9N2_PU_SND_STAT_REG_INVALID_CRESP_ERR = 16 ;
+static const uint8_t P9N2_PU_SND_STAT_REG_RCV_TTAG_PARITY_ERR = 32 ;
+static const uint8_t P9N2_PU_SND_STAT_REG_RCV_PB_OP_HANG_ERR = 33 ;
+static const uint8_t P9N2_PU_SND_STAT_REG_TOD_HANG_ERR = 34 ;
+static const uint8_t P9N2_PU_SND_STAT_REG_RCV_TOD_STATE = 48 ;
+static const uint8_t P9N2_PU_SND_STAT_REG_RCV_TOD_STATE_LEN = 4 ;
+
+static const uint8_t P9N2_PEC_SPATTN_IN = 0 ;
+static const uint8_t P9N2_PEC_SPATTN_IN_LEN = 10 ;
+
+static const uint8_t P9N2_PEC_SPA_MASK_IN = 0 ;
+static const uint8_t P9N2_PEC_SPA_MASK_IN_LEN = 10 ;
+
+static const uint8_t P9N2_PU_SPIMPSS_ADC_CTRL_REG0_HWCTRL_FRAME_SIZE = 0 ;
+static const uint8_t P9N2_PU_SPIMPSS_ADC_CTRL_REG0_HWCTRL_FRAME_SIZE_LEN = 6 ;
+static const uint8_t P9N2_PU_SPIMPSS_ADC_CTRL_REG0_HWCTRL_OUT_COUNT = 6 ;
+static const uint8_t P9N2_PU_SPIMPSS_ADC_CTRL_REG0_HWCTRL_OUT_COUNT_LEN = 6 ;
+static const uint8_t P9N2_PU_SPIMPSS_ADC_CTRL_REG0_HWCTRL_IN_DELAY = 12 ;
+static const uint8_t P9N2_PU_SPIMPSS_ADC_CTRL_REG0_HWCTRL_IN_DELAY_LEN = 6 ;
+static const uint8_t P9N2_PU_SPIMPSS_ADC_CTRL_REG0_HWCTRL_IN_COUNT = 18 ;
+static const uint8_t P9N2_PU_SPIMPSS_ADC_CTRL_REG0_HWCTRL_IN_COUNT_LEN = 6 ;
+
+static const uint8_t P9N2_PU_SPIPSS_100NS_REG_OUT = 0 ;
+static const uint8_t P9N2_PU_SPIPSS_100NS_REG_OUT_LEN = 32 ;
+
+static const uint8_t P9N2_PU_SPIPSS_ADC_CMD_REG_HWCTRL_START_SAMPLING = 0 ;
+
+static const uint8_t P9N2_PU_SPIPSS_ADC_CTRL_REG1_HWCTRL_FSM_ENABLE = 0 ;
+static const uint8_t P9N2_PU_SPIPSS_ADC_CTRL_REG1_HWCTRL_DEVICE = 1 ;
+static const uint8_t P9N2_PU_SPIPSS_ADC_CTRL_REG1_HWCTRL_CPOL = 2 ;
+static const uint8_t P9N2_PU_SPIPSS_ADC_CTRL_REG1_HWCTRL_CPHA = 3 ;
+static const uint8_t P9N2_PU_SPIPSS_ADC_CTRL_REG1_HWCTRL_CLOCK_DIVIDER = 4 ;
+static const uint8_t P9N2_PU_SPIPSS_ADC_CTRL_REG1_HWCTRL_CLOCK_DIVIDER_LEN = 10 ;
+static const uint8_t P9N2_PU_SPIPSS_ADC_CTRL_REG1_HWCTRL_NR_OF_FRAMES = 14 ;
+static const uint8_t P9N2_PU_SPIPSS_ADC_CTRL_REG1_HWCTRL_NR_OF_FRAMES_LEN = 4 ;
+static const uint8_t P9N2_PU_SPIPSS_ADC_CTRL_REG1_HWCTRL_WRITE_WHILE_BRIDGE_BUSY_SCRESP_EN = 18 ;
+static const uint8_t P9N2_PU_SPIPSS_ADC_CTRL_REG1_BUSY_RESPONSE_CODE = 19 ;
+static const uint8_t P9N2_PU_SPIPSS_ADC_CTRL_REG1_BUSY_RESPONSE_CODE_LEN = 3 ;
+
+static const uint8_t P9N2_PU_SPIPSS_ADC_CTRL_REG2_HWCTRL_INTER_FRAME_DELAY = 0 ;
+static const uint8_t P9N2_PU_SPIPSS_ADC_CTRL_REG2_HWCTRL_INTER_FRAME_DELAY_LEN = 17 ;
+
+static const uint8_t P9N2_PU_SPIPSS_ADC_RDATA_REG0_HWCTRL_RDATA0 = 0 ;
+static const uint8_t P9N2_PU_SPIPSS_ADC_RDATA_REG0_HWCTRL_RDATA0_LEN = 64 ;
+
+static const uint8_t P9N2_PU_SPIPSS_ADC_RDATA_REG1_HWCTRL_RDATA1 = 0 ;
+static const uint8_t P9N2_PU_SPIPSS_ADC_RDATA_REG1_HWCTRL_RDATA1_LEN = 64 ;
+
+static const uint8_t P9N2_PU_SPIPSS_ADC_RDATA_REG2_HWCTRL_RDATA2 = 0 ;
+static const uint8_t P9N2_PU_SPIPSS_ADC_RDATA_REG2_HWCTRL_RDATA2_LEN = 64 ;
+
+static const uint8_t P9N2_PU_SPIPSS_ADC_RDATA_REG3_HWCTRL_RDATA3 = 0 ;
+static const uint8_t P9N2_PU_SPIPSS_ADC_RDATA_REG3_HWCTRL_RDATA3_LEN = 64 ;
+
+static const uint8_t P9N2_PU_SPIPSS_ADC_RESET_REGISTER_HWCTRL = 0 ;
+static const uint8_t P9N2_PU_SPIPSS_ADC_RESET_REGISTER_HWCTRL_LEN = 2 ;
+
+static const uint8_t P9N2_PU_SPIPSS_ADC_STATUS_REG_HWCTRL_ONGOING = 0 ;
+static const uint8_t P9N2_PU_SPIPSS_ADC_STATUS_REG_RESERVED_1 = 1 ;
+static const uint8_t P9N2_PU_SPIPSS_ADC_STATUS_REG_RESERVED_2 = 2 ;
+static const uint8_t P9N2_PU_SPIPSS_ADC_STATUS_REG_RESERVED_3 = 3 ;
+static const uint8_t P9N2_PU_SPIPSS_ADC_STATUS_REG_HWCTRL_INVALID_NUMBER_OF_FRAMES = 4 ;
+static const uint8_t P9N2_PU_SPIPSS_ADC_STATUS_REG_HWCTRL_WRITE_WHILE_FSM_BUSY_ERR = 5 ;
+static const uint8_t P9N2_PU_SPIPSS_ADC_STATUS_REG_RESERVED_6 = 6 ;
+static const uint8_t P9N2_PU_SPIPSS_ADC_STATUS_REG_HWCTRL_FSM_ERR = 7 ;
+
+static const uint8_t P9N2_PU_SPIPSS_ADC_WDATA_REG_HWCTRL = 0 ;
+static const uint8_t P9N2_PU_SPIPSS_ADC_WDATA_REG_HWCTRL_LEN = 16 ;
+
+static const uint8_t P9N2_PU_SPIPSS_P2S_COMMAND_REG_START = 0 ;
+
+static const uint8_t P9N2_PU_SPIPSS_P2S_CTRL_REG0_FRAME_SIZE = 0 ;
+static const uint8_t P9N2_PU_SPIPSS_P2S_CTRL_REG0_FRAME_SIZE_LEN = 6 ;
+static const uint8_t P9N2_PU_SPIPSS_P2S_CTRL_REG0_OUT_COUNT1 = 6 ;
+static const uint8_t P9N2_PU_SPIPSS_P2S_CTRL_REG0_OUT_COUNT1_LEN = 6 ;
+static const uint8_t P9N2_PU_SPIPSS_P2S_CTRL_REG0_IN_DELAY1 = 12 ;
+static const uint8_t P9N2_PU_SPIPSS_P2S_CTRL_REG0_IN_DELAY1_LEN = 6 ;
+static const uint8_t P9N2_PU_SPIPSS_P2S_CTRL_REG0_IN_COUNT1 = 18 ;
+static const uint8_t P9N2_PU_SPIPSS_P2S_CTRL_REG0_IN_COUNT1_LEN = 6 ;
+static const uint8_t P9N2_PU_SPIPSS_P2S_CTRL_REG0_OUT_COUNT2 = 24 ;
+static const uint8_t P9N2_PU_SPIPSS_P2S_CTRL_REG0_OUT_COUNT2_LEN = 6 ;
+static const uint8_t P9N2_PU_SPIPSS_P2S_CTRL_REG0_IN_DELAY2 = 30 ;
+static const uint8_t P9N2_PU_SPIPSS_P2S_CTRL_REG0_IN_DELAY2_LEN = 6 ;
+static const uint8_t P9N2_PU_SPIPSS_P2S_CTRL_REG0_IN_COUNT2 = 36 ;
+static const uint8_t P9N2_PU_SPIPSS_P2S_CTRL_REG0_IN_COUNT2_LEN = 6 ;
+
+static const uint8_t P9N2_PU_SPIPSS_P2S_CTRL_REG1_BRIDGE_ENABLE = 0 ;
+static const uint8_t P9N2_PU_SPIPSS_P2S_CTRL_REG1_DEVICE = 1 ;
+static const uint8_t P9N2_PU_SPIPSS_P2S_CTRL_REG1_CPOL = 2 ;
+static const uint8_t P9N2_PU_SPIPSS_P2S_CTRL_REG1_CPHA = 3 ;
+static const uint8_t P9N2_PU_SPIPSS_P2S_CTRL_REG1_CLOCK_DIVIDER = 4 ;
+static const uint8_t P9N2_PU_SPIPSS_P2S_CTRL_REG1_CLOCK_DIVIDER_LEN = 10 ;
+static const uint8_t P9N2_PU_SPIPSS_P2S_CTRL_REG1_RESERVED = 14 ;
+static const uint8_t P9N2_PU_SPIPSS_P2S_CTRL_REG1_RESERVED_LEN = 3 ;
+static const uint8_t P9N2_PU_SPIPSS_P2S_CTRL_REG1_NR_OF_FRAMES = 17 ;
+static const uint8_t P9N2_PU_SPIPSS_P2S_CTRL_REG1_WRITE_WHILE_BRIDGE_BUSY_SCRESP_EN = 18 ;
+static const uint8_t P9N2_PU_SPIPSS_P2S_CTRL_REG1_BUSY_RESPONSE_CODE_NO_1 = 19 ;
+static const uint8_t P9N2_PU_SPIPSS_P2S_CTRL_REG1_BUSY_RESPONSE_CODE_NO_1_LEN = 3 ;
+
+static const uint8_t P9N2_PU_SPIPSS_P2S_CTRL_REG2_INTER_FRAME_DELAY = 0 ;
+static const uint8_t P9N2_PU_SPIPSS_P2S_CTRL_REG2_INTER_FRAME_DELAY_LEN = 17 ;
+
+static const uint8_t P9N2_PU_SPIPSS_P2S_RDATA_REG_RDATA = 0 ;
+static const uint8_t P9N2_PU_SPIPSS_P2S_RDATA_REG_RDATA_LEN = 32 ;
+
+static const uint8_t P9N2_PU_SPIPSS_P2S_RESET_REGISTER_RESET = 0 ;
+static const uint8_t P9N2_PU_SPIPSS_P2S_RESET_REGISTER_RESET_LEN = 2 ;
+
+static const uint8_t P9N2_PU_SPIPSS_P2S_STATUS_REG_ONGOING = 0 ;
+static const uint8_t P9N2_PU_SPIPSS_P2S_STATUS_REG_RESERVED_1 = 1 ;
+static const uint8_t P9N2_PU_SPIPSS_P2S_STATUS_REG_RESERVED_2 = 2 ;
+static const uint8_t P9N2_PU_SPIPSS_P2S_STATUS_REG_RESERVED_3 = 3 ;
+static const uint8_t P9N2_PU_SPIPSS_P2S_STATUS_REG_RESERVED_4 = 4 ;
+static const uint8_t P9N2_PU_SPIPSS_P2S_STATUS_REG_WRITE_WHILE_BRIDGE_BUSY_ERR = 5 ;
+static const uint8_t P9N2_PU_SPIPSS_P2S_STATUS_REG_RESERVED6 = 6 ;
+static const uint8_t P9N2_PU_SPIPSS_P2S_STATUS_REG_FSM_ERR = 7 ;
+
+static const uint8_t P9N2_PU_SPIPSS_P2S_WDATA_REG_WDATA = 0 ;
+static const uint8_t P9N2_PU_SPIPSS_P2S_WDATA_REG_WDATA_LEN = 32 ;
+
+static const uint8_t P9N2_PU_SRAM_SRBV0_BOOT_VECTOR_WORD0 = 0 ;
+static const uint8_t P9N2_PU_SRAM_SRBV0_BOOT_VECTOR_WORD0_LEN = 32 ;
+
+static const uint8_t P9N2_PU_SRAM_SRBV1_BOOT_VECTOR_WORD1 = 0 ;
+static const uint8_t P9N2_PU_SRAM_SRBV1_BOOT_VECTOR_WORD1_LEN = 32 ;
+
+static const uint8_t P9N2_PU_SRAM_SRBV2_BOOT_VECTOR_WORD2 = 0 ;
+static const uint8_t P9N2_PU_SRAM_SRBV2_BOOT_VECTOR_WORD2_LEN = 32 ;
+
+static const uint8_t P9N2_PU_SRAM_SRBV3_BOOT_VECTOR_WORD3 = 0 ;
+static const uint8_t P9N2_PU_SRAM_SRBV3_BOOT_VECTOR_WORD3_LEN = 32 ;
+
+static const uint8_t P9N2_PU_SRAM_SRCHSW_CHKSW_WRFSM_DLY_DIS = 0 ;
+static const uint8_t P9N2_PU_SRAM_SRCHSW_CHKSW_ALLOW1_RD = 1 ;
+static const uint8_t P9N2_PU_SRAM_SRCHSW_CHKSW_ALLOW1_WR = 2 ;
+static const uint8_t P9N2_PU_SRAM_SRCHSW_CHKSW_ALLOW1_RDWR = 3 ;
+static const uint8_t P9N2_PU_SRAM_SRCHSW_CHKSW_OCI_PARCHK_DIS = 4 ;
+static const uint8_t P9N2_PU_SRAM_SRCHSW_CHKSW_TANK_RDDATA_PARCHK_DIS = 5 ;
+static const uint8_t P9N2_PU_SRAM_SRCHSW_CHKSW_SPARE_6 = 6 ;
+static const uint8_t P9N2_PU_SRAM_SRCHSW_CHKSW_VAL_BE_ADDR_CHK_DIS = 7 ;
+static const uint8_t P9N2_PU_SRAM_SRCHSW_CHKSW_SO_SPARE = 8 ;
+static const uint8_t P9N2_PU_SRAM_SRCHSW_CHKSW_SO_SPARE_LEN = 2 ;
+
+static const uint8_t P9N2_PU_SRAM_SREAR_ERROR_ADDRESS = 0 ;
+static const uint8_t P9N2_PU_SRAM_SREAR_ERROR_ADDRESS_LEN = 17 ;
+
+static const uint8_t P9N2_PU_SRAM_SRMAP_REMAP_SOURCE = 0 ;
+static const uint8_t P9N2_PU_SRAM_SRMAP_REMAP_SOURCE_LEN = 14 ;
+static const uint8_t P9N2_PU_SRAM_SRMAP_REMAP_DEST = 16 ;
+static const uint8_t P9N2_PU_SRAM_SRMAP_REMAP_DEST_LEN = 14 ;
+
+static const uint8_t P9N2_PU_SRAM_SRMR_ENABLE_REMAP = 0 ;
+static const uint8_t P9N2_PU_SRAM_SRMR_ARB_EN_SEND_ALL_WRITES = 1 ;
+static const uint8_t P9N2_PU_SRAM_SRMR_DISABLE_LFSR = 2 ;
+static const uint8_t P9N2_PU_SRAM_SRMR_LFSR_FAIRNESS_MASK = 3 ;
+static const uint8_t P9N2_PU_SRAM_SRMR_LFSR_FAIRNESS_MASK_LEN = 5 ;
+static const uint8_t P9N2_PU_SRAM_SRMR_ERROR_INJECT_ENABLE = 8 ;
+static const uint8_t P9N2_PU_SRAM_SRMR_CTL_TRACE_EN = 9 ;
+static const uint8_t P9N2_PU_SRAM_SRMR_CTL_TRACE_SEL = 10 ;
+static const uint8_t P9N2_PU_SRAM_SRMR_SPARE = 11 ;
+static const uint8_t P9N2_PU_SRAM_SRMR_SPARE_LEN = 5 ;
+
+static const uint8_t P9N2_PU_STATUS_REGISTER_ADDR_NVLD = 0 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_WRITE_NVLD = 1 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_READ_NVLD = 2 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_INVLD_CMD_ERR = 3 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_CORR_ERR = 4 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_UNCORR_ERROR = 5 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_DATA_REG_0_31 = 6 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_DATA_REG_0_31_LEN = 32 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_UNUSED_39_43 = 39 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_UNUSED_39_43_LEN = 5 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_CTRL_BUSY = 44 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_DCOMP_ERR = 45 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_INVLD_PRGM_ERR = 46 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_UNUSED_47_51 = 47 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_UNUSED_47_51_LEN = 5 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_COMMAND_COMPLETE = 52 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_UNUSED_53 = 53 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_RDWR_OP_BUSY = 54 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_DCOMP_ENGINE_BUSY = 55 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_RD_DATA_COUNT = 56 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_RD_DATA_COUNT_LEN = 8 ;
+
+static const uint8_t P9N2_PU_STATUS_REGISTER_B_BUS_ADDR_NVLD_0 = 0 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_B_BUS_WRITE_NVLD_0 = 1 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_B_BUS_READ_NVLD_0 = 2 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_B_BUS_ADDR_P_ERR_0 = 3 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_B_BUS_PAR_ERR_0 = 4 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_B_BUS_LB_PARITY_ERROR_0 = 5 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_B_PIB_DATA0TO7_0 = 6 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_B_PIB_DATA0TO7_0_LEN = 32 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_B_BUS_WAITING_IN_I2C_QUEUE_0 = 40 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_B_ECC_CORRECTED_ERROR_0 = 41 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_B_ECC_UNCORRECTED_ERROR_0 = 42 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_B_ECC_CONFIG_ERROR_0 = 43 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_B_BUS_BUSY_0 = 44 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_B_BUS_INVALID_COMMAND_0 = 45 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_B_BUS_PARITY_ERROR_0 = 46 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_B_BUS_BACK_END_OVERRUN_ERROR_0 = 47 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_B_BUS_BACK_END_ACCESS_ERROR_0 = 48 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_B_BUS_ARBITRATION_LOST_ERROR_0 = 49 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_B_BUS_NACK_RECEIVED_ERROR_0 = 50 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_B_BUS_DATA_REQUEST_0 = 51 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_B_BUS_COMMAND_COMPLETE_0 = 52 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_B_BUS_STOP_ERROR_0 = 53 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_B_BUS_I2C_PORT_BUSY_0 = 54 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_B_BUS_I2C_INTERFACE_BUSY_0 = 55 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_B_BUS_FIFO_ENTRY_COUNT_0 = 56 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_B_BUS_FIFO_ENTRY_COUNT_0_LEN = 4 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_B_PCBIF_ERRS_0 = 60 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_B_PCBIF_ERRS_0_LEN = 4 ;
+
+static const uint8_t P9N2_PU_STATUS_REGISTER_C_BUS_ADDR_NVLD_1 = 0 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_C_BUS_WRITE_NVLD_1 = 1 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_C_BUS_READ_NVLD_1 = 2 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_C_BUS_ADDR_P_ERR_1 = 3 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_C_BUS_PAR_ERR_1 = 4 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_C_BUS_LB_PARITY_ERROR_1 = 5 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_C_PIB_DATA0TO7_1 = 6 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_C_PIB_DATA0TO7_1_LEN = 32 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_C_BUS_WAITING_IN_I2C_QUEUE_1 = 40 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_C_ECC_CORRECTED_ERROR_1 = 41 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_C_ECC_UNCORRECTED_ERROR_1 = 42 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_C_ECC_CONFIG_ERROR_1 = 43 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_C_BUS_BUSY_1 = 44 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_C_BUS_INVALID_COMMAND_1 = 45 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_C_BUS_PARITY_ERROR_1 = 46 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_C_BUS_BACK_END_OVERRUN_ERROR_1 = 47 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_C_BUS_BACK_END_ACCESS_ERROR_1 = 48 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_C_BUS_ARBITRATION_LOST_ERROR_1 = 49 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_C_BUS_NACK_RECEIVED_ERROR_1 = 50 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_C_BUS_DATA_REQUEST_1 = 51 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_C_BUS_COMMAND_COMPLETE_1 = 52 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_C_BUS_STOP_ERROR_1 = 53 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_C_BUS_I2C_PORT_BUSY_1 = 54 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_C_BUS_I2C_INTERFACE_BUSY_1 = 55 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_C_BUS_FIFO_ENTRY_COUNT_1 = 56 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_C_BUS_FIFO_ENTRY_COUNT_1_LEN = 4 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_C_PCBIF_ERRS_1 = 60 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_C_PCBIF_ERRS_1_LEN = 4 ;
+
+static const uint8_t P9N2_PU_STATUS_REGISTER_D_BUS_ADDR_NVLD_2 = 0 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_D_BUS_WRITE_NVLD_2 = 1 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_D_BUS_READ_NVLD_2 = 2 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_D_BUS_ADDR_P_ERR_2 = 3 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_D_BUS_PAR_ERR_2 = 4 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_D_BUS_LB_PARITY_ERROR_2 = 5 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_D_PIB_DATA0TO7_2 = 6 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_D_PIB_DATA0TO7_2_LEN = 32 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_D_BUS_WAITING_IN_I2C_QUEUE_2 = 40 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_D_ECC_CORRECTED_ERROR_2 = 41 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_D_ECC_UNCORRECTED_ERROR_2 = 42 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_D_ECC_CONFIG_ERROR_2 = 43 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_D_BUS_BUSY_2 = 44 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_D_BUS_INVALID_COMMAND_2 = 45 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_D_BUS_PARITY_ERROR_2 = 46 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_D_BUS_BACK_END_OVERRUN_ERROR_2 = 47 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_D_BUS_BACK_END_ACCESS_ERROR_2 = 48 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_D_BUS_ARBITRATION_LOST_ERROR_2 = 49 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_D_BUS_NACK_RECEIVED_ERROR_2 = 50 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_D_BUS_DATA_REQUEST_2 = 51 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_D_BUS_COMMAND_COMPLETE_2 = 52 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_D_BUS_STOP_ERROR_2 = 53 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_D_BUS_I2C_PORT_BUSY_2 = 54 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_D_BUS_I2C_INTERFACE_BUSY_2 = 55 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_D_BUS_FIFO_ENTRY_COUNT_2 = 56 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_D_BUS_FIFO_ENTRY_COUNT_2_LEN = 4 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_D_PCBIF_ERRS_2 = 60 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_D_PCBIF_ERRS_2_LEN = 4 ;
+
+static const uint8_t P9N2_PU_STATUS_REGISTER_E_BUS_ADDR_NVLD_3 = 0 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_E_BUS_WRITE_NVLD_3 = 1 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_E_BUS_READ_NVLD_3 = 2 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_E_BUS_ADDR_P_ERR_3 = 3 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_E_BUS_PAR_ERR_3 = 4 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_E_BUS_LB_PARITY_ERROR_3 = 5 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_E_PIB_DATA0TO7_3 = 6 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_E_PIB_DATA0TO7_3_LEN = 32 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_E_BUS_WAITING_IN_I2C_QUEUE_3 = 40 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_E_ECC_CORRECTED_ERROR_3 = 41 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_E_ECC_UNCORRECTED_ERROR_3 = 42 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_E_ECC_CONFIG_ERROR_3 = 43 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_E_BUS_BUSY_3 = 44 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_E_BUS_INVALID_COMMAND_3 = 45 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_E_BUS_PARITY_ERROR_3 = 46 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_E_BUS_BACK_END_OVERRUN_ERROR_3 = 47 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_E_BUS_BACK_END_ACCESS_ERROR_3 = 48 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_E_BUS_ARBITRATION_LOST_ERROR_3 = 49 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_E_BUS_NACK_RECEIVED_ERROR_3 = 50 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_E_BUS_DATA_REQUEST_3 = 51 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_E_BUS_COMMAND_COMPLETE_3 = 52 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_E_BUS_STOP_ERROR_3 = 53 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_E_BUS_I2C_PORT_BUSY_3 = 54 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_E_BUS_I2C_INTERFACE_BUSY_3 = 55 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_E_BUS_FIFO_ENTRY_COUNT_3 = 56 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_E_BUS_FIFO_ENTRY_COUNT_3_LEN = 4 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_E_PCBIF_ERRS_3 = 60 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_E_PCBIF_ERRS_3_LEN = 4 ;
+
+static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_B_INVALID_CMD_0 = 0 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_B_LBUS_PARITY_ERROR_0 = 1 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_B_BE_OV_ERROR_0 = 2 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_B_BE_ACC_ERROR_0 = 3 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_B_ARBITRATION_LOST_ERROR_0 = 4 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_B_NACK_RECEIVED_ERROR_0 = 5 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_B_DATA_REQUEST_0 = 6 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_B_STOP_ERROR_0 = 8 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_B_BUSY = 22 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_B_SELF_BUSY_0 = 23 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_B_FIFO_ENTRY_COUNT_0 = 28 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_B_FIFO_ENTRY_COUNT_0_LEN = 4 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_B_PEEK_DATA1_0 = 32 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_B_PEEK_DATA1_0_LEN = 8 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_B_LBUS_PARITY_ERR1_0 = 40 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_B_I2CM_STEERED_INTERRUPTS_0 = 44 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_B_I2CM_STEERED_INTERRUPTS_0_LEN = 4 ;
+
+static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_C_INVALID_CMD_1 = 0 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_C_LBUS_PARITY_ERROR_1 = 1 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_C_BE_OV_ERROR_1 = 2 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_C_BE_ACC_ERROR_1 = 3 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_C_ARBITRATION_LOST_ERROR_1 = 4 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_C_NACK_RECEIVED_ERROR_1 = 5 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_C_DATA_REQUEST_1 = 6 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_C_STOP_ERROR_1 = 8 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_C_BUSY = 22 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_C_SELF_BUSY_1 = 23 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_C_FIFO_ENTRY_COUNT_1 = 28 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_C_FIFO_ENTRY_COUNT_1_LEN = 4 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_C_PEEK_DATA1_1 = 32 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_C_PEEK_DATA1_1_LEN = 8 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_C_LBUS_PARITY_ERR1_1 = 40 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_C_I2CM_STEERED_INTERRUPTS_1 = 44 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_C_I2CM_STEERED_INTERRUPTS_1_LEN = 4 ;
+
+static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_D_INVALID_CMD_2 = 0 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_D_LBUS_PARITY_ERROR_2 = 1 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_D_BE_OV_ERROR_2 = 2 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_D_BE_ACC_ERROR_2 = 3 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_D_ARBITRATION_LOST_ERROR_2 = 4 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_D_NACK_RECEIVED_ERROR_2 = 5 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_D_DATA_REQUEST_2 = 6 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_D_STOP_ERROR_2 = 8 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_D_BUSY = 22 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_D_SELF_BUSY_2 = 23 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_D_FIFO_ENTRY_COUNT_2 = 28 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_D_FIFO_ENTRY_COUNT_2_LEN = 4 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_D_PEEK_DATA1_2 = 32 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_D_PEEK_DATA1_2_LEN = 8 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_D_LBUS_PARITY_ERR1_2 = 40 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_D_I2CM_STEERED_INTERRUPTS_2 = 44 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_D_I2CM_STEERED_INTERRUPTS_2_LEN = 4 ;
+
+static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_E_INVALID_CMD_3 = 0 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_E_LBUS_PARITY_ERROR_3 = 1 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_E_BE_OV_ERROR_3 = 2 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_E_BE_ACC_ERROR_3 = 3 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_E_ARBITRATION_LOST_ERROR_3 = 4 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_E_NACK_RECEIVED_ERROR_3 = 5 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_E_DATA_REQUEST_3 = 6 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_E_STOP_ERROR_3 = 8 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_E_BUSY = 22 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_E_SELF_BUSY_3 = 23 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_E_FIFO_ENTRY_COUNT_3 = 28 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_E_FIFO_ENTRY_COUNT_3_LEN = 4 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_E_PEEK_DATA1_3 = 32 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_E_PEEK_DATA1_3_LEN = 8 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_E_LBUS_PARITY_ERR1_3 = 40 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_E_I2CM_STEERED_INTERRUPTS_3 = 44 ;
+static const uint8_t P9N2_PU_STATUS_REGISTER_ENGINE_E_I2CM_STEERED_INTERRUPTS_3_LEN = 4 ;
+
+static const uint8_t P9N2_PEC_SUM_MASK_REG_SMASK_IN0 = 0 ;
+static const uint8_t P9N2_PEC_SUM_MASK_REG_SMASK_IN1 = 1 ;
+static const uint8_t P9N2_PEC_SUM_MASK_REG_SMASK_IN2 = 2 ;
+static const uint8_t P9N2_PEC_SUM_MASK_REG_SMASK_IN3 = 3 ;
+static const uint8_t P9N2_PEC_SUM_MASK_REG_SMASK_IN4 = 4 ;
+
+static const uint8_t P9N2_PU_SU_CRB_KILL_REQ_ENABLE = 0 ;
+static const uint8_t P9N2_PU_SU_CRB_KILL_REQ_DONE = 1 ;
+static const uint8_t P9N2_PU_SU_CRB_KILL_REQ_SUMMARY = 2 ;
+static const uint8_t P9N2_PU_SU_CRB_KILL_REQ_DISPATCH_SLOT_KILLED_CNT = 4 ;
+static const uint8_t P9N2_PU_SU_CRB_KILL_REQ_DISPATCH_SLOT_KILLED_CNT_LEN = 4 ;
+static const uint8_t P9N2_PU_SU_CRB_KILL_REQ_PREFETCH_CHANNEL_CNT = 8 ;
+static const uint8_t P9N2_PU_SU_CRB_KILL_REQ_PREFETCH_CHANNEL_CNT_LEN = 4 ;
+static const uint8_t P9N2_PU_SU_CRB_KILL_REQ_ACTIVE_CHANNEL_CNT = 12 ;
+static const uint8_t P9N2_PU_SU_CRB_KILL_REQ_ACTIVE_CHANNEL_CNT_LEN = 4 ;
+static const uint8_t P9N2_PU_SU_CRB_KILL_REQ_SWC_VALUE = 16 ;
+static const uint8_t P9N2_PU_SU_CRB_KILL_REQ_SWC_VALUE_LEN = 16 ;
+
+static const uint8_t P9N2_PU_SU_DMA_ERROR_REPORT_0_0 = 0 ;
+static const uint8_t P9N2_PU_SU_DMA_ERROR_REPORT_0_0_LEN = 64 ;
+
+static const uint8_t P9N2_PU_SU_DMA_ERROR_REPORT_1_1 = 0 ;
+static const uint8_t P9N2_PU_SU_DMA_ERROR_REPORT_1_1_LEN = 17 ;
+
+static const uint8_t P9N2_PU_SU_ENGINE_ENABLE_ALLOW_CRYPTO = 0 ;
+static const uint8_t P9N2_PU_SU_ENGINE_ENABLE_CH3_SYM = 57 ;
+static const uint8_t P9N2_PU_SU_ENGINE_ENABLE_CH2_SYM = 58 ;
+static const uint8_t P9N2_PU_SU_ENGINE_ENABLE_CH4_GZIP = 61 ;
+static const uint8_t P9N2_PU_SU_ENGINE_ENABLE_CH1_EFT = 62 ;
+static const uint8_t P9N2_PU_SU_ENGINE_ENABLE_CH0_EFT = 63 ;
+
+static const uint8_t P9N2_PU_SU_ERAT_ERROR_RPT_RPT = 0 ;
+static const uint8_t P9N2_PU_SU_ERAT_ERROR_RPT_RPT_LEN = 48 ;
+
+static const uint8_t P9N2_PU_SU_INBOUND_WRITE_CONTROL_GZIPCOMP_MAX_INRD = 8 ;
+static const uint8_t P9N2_PU_SU_INBOUND_WRITE_CONTROL_GZIPCOMP_MAX_INRD_LEN = 4 ;
+static const uint8_t P9N2_PU_SU_INBOUND_WRITE_CONTROL_GZIPDECOMP_MAX_INRD = 12 ;
+static const uint8_t P9N2_PU_SU_INBOUND_WRITE_CONTROL_GZIPDECOMP_MAX_INRD_LEN = 4 ;
+static const uint8_t P9N2_PU_SU_INBOUND_WRITE_CONTROL_GZIP_COMP_PREFETCH_ENABLE = 16 ;
+static const uint8_t P9N2_PU_SU_INBOUND_WRITE_CONTROL_GZIP_DECOMP_PREFETCH_ENABLE = 17 ;
+static const uint8_t P9N2_PU_SU_INBOUND_WRITE_CONTROL_EFT_COMP_PREFETCH_ENABLE = 23 ;
+static const uint8_t P9N2_PU_SU_INBOUND_WRITE_CONTROL_EFT_DECOMP_PREFETCH_ENABLE = 24 ;
+static const uint8_t P9N2_PU_SU_INBOUND_WRITE_CONTROL_SYM_MAX_INRD = 25 ;
+static const uint8_t P9N2_PU_SU_INBOUND_WRITE_CONTROL_SYM_MAX_INRD_LEN = 4 ;
+static const uint8_t P9N2_PU_SU_INBOUND_WRITE_CONTROL_EFTCOMP_MAX_INRD = 33 ;
+static const uint8_t P9N2_PU_SU_INBOUND_WRITE_CONTROL_EFTCOMP_MAX_INRD_LEN = 4 ;
+static const uint8_t P9N2_PU_SU_INBOUND_WRITE_CONTROL_EFTDECOMP_MAX_INRD = 37 ;
+static const uint8_t P9N2_PU_SU_INBOUND_WRITE_CONTROL_EFTDECOMP_MAX_INRD_LEN = 4 ;
+static const uint8_t P9N2_PU_SU_INBOUND_WRITE_CONTROL_SYM_CPB_CHECK_DISABLE = 48 ;
+static const uint8_t P9N2_PU_SU_INBOUND_WRITE_CONTROL_EFT_SPBC_ENABLE = 56 ;
+
+static const uint8_t P9N2_PU_SU_PERFMON_CONTROL_0_LPID = 0 ;
+static const uint8_t P9N2_PU_SU_PERFMON_CONTROL_0_LPID_LEN = 12 ;
+static const uint8_t P9N2_PU_SU_PERFMON_CONTROL_0_LPID_MASK = 12 ;
+static const uint8_t P9N2_PU_SU_PERFMON_CONTROL_0_LPID_MASK_LEN = 12 ;
+static const uint8_t P9N2_PU_SU_PERFMON_CONTROL_0_PID = 24 ;
+static const uint8_t P9N2_PU_SU_PERFMON_CONTROL_0_PID_LEN = 20 ;
+static const uint8_t P9N2_PU_SU_PERFMON_CONTROL_0_PID_MASK = 44 ;
+static const uint8_t P9N2_PU_SU_PERFMON_CONTROL_0_PID_MASK_LEN = 20 ;
+
+static const uint8_t P9N2_PU_SU_PERFMON_CONTROL_1_GZIP_FC_SELECT = 27 ;
+static const uint8_t P9N2_PU_SU_PERFMON_CONTROL_1_GZIP_FC_SELECT_LEN = 2 ;
+static const uint8_t P9N2_PU_SU_PERFMON_CONTROL_1_842_FC_SELECT = 29 ;
+static const uint8_t P9N2_PU_SU_PERFMON_CONTROL_1_842_FC_SELECT_LEN = 2 ;
+static const uint8_t P9N2_PU_SU_PERFMON_CONTROL_1_DMA_MUX_SELECT = 31 ;
+static const uint8_t P9N2_PU_SU_PERFMON_CONTROL_1_DMA_MUX_SELECT_LEN = 4 ;
+static const uint8_t P9N2_PU_SU_PERFMON_CONTROL_1_EFT_MUX_SELECT = 35 ;
+static const uint8_t P9N2_PU_SU_PERFMON_CONTROL_1_EFT_MUX_SELECT_LEN = 3 ;
+static const uint8_t P9N2_PU_SU_PERFMON_CONTROL_1_GZIP_MUX_SELECT = 38 ;
+static const uint8_t P9N2_PU_SU_PERFMON_CONTROL_1_GZIP_MUX_SELECT_LEN = 3 ;
+static const uint8_t P9N2_PU_SU_PERFMON_CONTROL_1_ERAT_MUX_SELECT = 41 ;
+static const uint8_t P9N2_PU_SU_PERFMON_CONTROL_1_ERAT_MUX_SELECT_LEN = 4 ;
+static const uint8_t P9N2_PU_SU_PERFMON_CONTROL_1_UMAC_MUX_SELECT = 45 ;
+static const uint8_t P9N2_PU_SU_PERFMON_CONTROL_1_UMAC_MUX_SELECT_LEN = 3 ;
+static const uint8_t P9N2_PU_SU_PERFMON_CONTROL_1_PBI_MUX_SELECT = 48 ;
+static const uint8_t P9N2_PU_SU_PERFMON_CONTROL_1_PBI_MUX_SELECT_LEN = 4 ;
+static const uint8_t P9N2_PU_SU_PERFMON_CONTROL_1_SHA_LATENCY_CFG = 52 ;
+static const uint8_t P9N2_PU_SU_PERFMON_CONTROL_1_MD5_LATENCY_CFG = 54 ;
+static const uint8_t P9N2_PU_SU_PERFMON_CONTROL_1_AES_LATENCY_CFG = 56 ;
+static const uint8_t P9N2_PU_SU_PERFMON_CONTROL_1_AESSHA_LATENCY_CFG = 58 ;
+static const uint8_t P9N2_PU_SU_PERFMON_CONTROL_1_GZIP_LATENCY_CFG = 60 ;
+static const uint8_t P9N2_PU_SU_PERFMON_CONTROL_1_842_LATENCY_CFG = 62 ;
+
+static const uint8_t P9N2_PU_SU_STATUS_HMI_ACTIVE = 54 ;
+static const uint8_t P9N2_PU_SU_STATUS_PBI_IDLE = 55 ;
+static const uint8_t P9N2_PU_SU_STATUS_DMA_CH0_IDLE = 56 ;
+static const uint8_t P9N2_PU_SU_STATUS_DMA_CH1_IDLE = 57 ;
+static const uint8_t P9N2_PU_SU_STATUS_DMA_CH2_IDLE = 58 ;
+static const uint8_t P9N2_PU_SU_STATUS_DMA_CH3_IDLE = 59 ;
+static const uint8_t P9N2_PU_SU_STATUS_DMA_CH4_IDLE = 60 ;
+
+static const uint8_t P9N2_PU_SU_UMAC_ERROR_RPT_RPT = 0 ;
+static const uint8_t P9N2_PU_SU_UMAC_ERROR_RPT_RPT_LEN = 56 ;
+
+static const uint8_t P9N2_PU_SU_UMAC_ERROR_RPT1_RPT1 = 0 ;
+static const uint8_t P9N2_PU_SU_UMAC_ERROR_RPT1_RPT1_LEN = 6 ;
+
+static const uint8_t P9N2_PU_SYM_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_LPID = 4 ;
+static const uint8_t P9N2_PU_SYM_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_LPID_LEN = 12 ;
+static const uint8_t P9N2_PU_SYM_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_PID = 20 ;
+static const uint8_t P9N2_PU_SYM_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_PID_LEN = 20 ;
+static const uint8_t P9N2_PU_SYM_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_TID = 44 ;
+static const uint8_t P9N2_PU_SYM_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_TID_LEN = 16 ;
+static const uint8_t P9N2_PU_SYM_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_ENABLE = 63 ;
+
+static const uint8_t P9N2_PU_SYM_HI_PRIOR_RCV_FIFO_BAR_PRIORITY = 8 ;
+static const uint8_t P9N2_PU_SYM_HI_PRIOR_RCV_FIFO_BAR_PRIORITY_LEN = 46 ;
+static const uint8_t P9N2_PU_SYM_HI_PRIOR_RCV_FIFO_BAR_PRIORITY_SIZE = 54 ;
+static const uint8_t P9N2_PU_SYM_HI_PRIOR_RCV_FIFO_BAR_PRIORITY_SIZE_LEN = 3 ;
+
+static const uint8_t P9N2_PU_SYM_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_READ_OFFSET = 4 ;
+static const uint8_t P9N2_PU_SYM_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_READ_OFFSET_LEN = 8 ;
+static const uint8_t P9N2_PU_SYM_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_QUEUED = 15 ;
+static const uint8_t P9N2_PU_SYM_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_QUEUED_LEN = 9 ;
+static const uint8_t P9N2_PU_SYM_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_PRIMAX = 27 ;
+static const uint8_t P9N2_PU_SYM_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_PRIMAX_LEN = 9 ;
+
+static const uint8_t P9N2_PU_SYM_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_LPID = 4 ;
+static const uint8_t P9N2_PU_SYM_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_LPID_LEN = 12 ;
+static const uint8_t P9N2_PU_SYM_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_PID = 20 ;
+static const uint8_t P9N2_PU_SYM_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_PID_LEN = 20 ;
+static const uint8_t P9N2_PU_SYM_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_TID = 44 ;
+static const uint8_t P9N2_PU_SYM_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_TID_LEN = 16 ;
+static const uint8_t P9N2_PU_SYM_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_ENABLE = 63 ;
+
+static const uint8_t P9N2_PU_SYM_LO_PRIOR_RCV_FIFO_BAR_PRIORITY = 8 ;
+static const uint8_t P9N2_PU_SYM_LO_PRIOR_RCV_FIFO_BAR_PRIORITY_LEN = 46 ;
+static const uint8_t P9N2_PU_SYM_LO_PRIOR_RCV_FIFO_BAR_PRIORITY_SIZE = 54 ;
+static const uint8_t P9N2_PU_SYM_LO_PRIOR_RCV_FIFO_BAR_PRIORITY_SIZE_LEN = 3 ;
+
+static const uint8_t P9N2_PU_SYM_LO_PRIOR_RCV_FIFO_CNTL_PRIORITY_READ_OFFSET = 4 ;
+static const uint8_t P9N2_PU_SYM_LO_PRIOR_RCV_FIFO_CNTL_PRIORITY_READ_OFFSET_LEN = 8 ;
+static const uint8_t P9N2_PU_SYM_LO_PRIOR_RCV_FIFO_CNTL_PRIORITY_QUEUED = 15 ;
+static const uint8_t P9N2_PU_SYM_LO_PRIOR_RCV_FIFO_CNTL_PRIORITY_QUEUED_LEN = 9 ;
+
+static const uint8_t P9N2_PU_SYM_MAX_BYTE_CNT_LIMIT = 0 ;
+static const uint8_t P9N2_PU_SYM_MAX_BYTE_CNT_LIMIT_LEN = 5 ;
+static const uint8_t P9N2_PU_SYM_MAX_BYTE_CNT_SRC_DDE = 5 ;
+static const uint8_t P9N2_PU_SYM_MAX_BYTE_CNT_SRC_DDE_LEN = 8 ;
+static const uint8_t P9N2_PU_SYM_MAX_BYTE_CNT_TARGET_DDE = 13 ;
+static const uint8_t P9N2_PU_SYM_MAX_BYTE_CNT_TARGET_DDE_LEN = 8 ;
+static const uint8_t P9N2_PU_SYM_MAX_BYTE_CNT_LO_PRIOR_LIMIT = 21 ;
+static const uint8_t P9N2_PU_SYM_MAX_BYTE_CNT_LO_PRIOR_LIMIT_LEN = 5 ;
+
+static const uint8_t P9N2_PEC_SYNC_CONFIG_PULSE_DELAY = 0 ;
+static const uint8_t P9N2_PEC_SYNC_CONFIG_PULSE_DELAY_LEN = 4 ;
+static const uint8_t P9N2_PEC_SYNC_CONFIG_LISTEN_TO_PULSE_DIS = 4 ;
+static const uint8_t P9N2_PEC_SYNC_CONFIG_PULSE_INPUT_SEL = 5 ;
+static const uint8_t P9N2_PEC_SYNC_CONFIG_USE_FOR_SCAN = 6 ;
+static const uint8_t P9N2_PEC_SYNC_CONFIG_CLEAR_CHIPLET_IS_ALIGNED = 7 ;
+static const uint8_t P9N2_PEC_SYNC_CONFIG_UNIT_REGION_CLKCMD_ENABLE = 8 ;
+static const uint8_t P9N2_PEC_SYNC_CONFIG_DISABLE_PCB_ITR = 9 ;
+static const uint8_t P9N2_PEC_SYNC_CONFIG_ENABLE_VITL_ALIGN_CHECK = 10 ;
+static const uint8_t P9N2_PEC_SYNC_CONFIG_PULSE_OUT_DIS = 11 ;
+static const uint8_t P9N2_PEC_SYNC_CONFIG_CHKSW_DD1_MODE = 12 ;
+static const uint8_t P9N2_PEC_SYNC_CONFIG_CHKSW_DD1_E1 = 13 ;
+static const uint8_t P9N2_PEC_SYNC_CONFIG_CHKSW_DD1_E2 = 14 ;
+static const uint8_t P9N2_PEC_SYNC_CONFIG_CHKSW_DD1_E3 = 15 ;
+static const uint8_t P9N2_PEC_SYNC_CONFIG_PHASE_COUNTER_ON_CLKCHANGE = 16 ;
+static const uint8_t P9N2_PEC_SYNC_CONFIG_PHASE_COUNTER_ON_CLKCHANGE_LEN = 8 ;
+
+static const uint8_t P9N2_PU_SYNC_FIR_ACTION0_REG_INVALID_TRANSFER_SIZE = 0 ;
+static const uint8_t P9N2_PU_SYNC_FIR_ACTION0_REG_INVALID_COMMAND = 1 ;
+static const uint8_t P9N2_PU_SYNC_FIR_ACTION0_REG_INVALID_ADDRESS_ALIGNMENT = 2 ;
+static const uint8_t P9N2_PU_SYNC_FIR_ACTION0_REG_OPB_ERROR = 3 ;
+static const uint8_t P9N2_PU_SYNC_FIR_ACTION0_REG_OPB_TIMEOUT = 4 ;
+static const uint8_t P9N2_PU_SYNC_FIR_ACTION0_REG_OPB_MASTER_HANG_TIMEOUT = 5 ;
+static const uint8_t P9N2_PU_SYNC_FIR_ACTION0_REG_CMD_BUFFER_PAR_ERR = 6 ;
+static const uint8_t P9N2_PU_SYNC_FIR_ACTION0_REG_DAT_BUFFER_PAR_ERR = 7 ;
+static const uint8_t P9N2_PU_SYNC_FIR_ACTION0_REG_RETURNQ_ERR = 8 ;
+static const uint8_t P9N2_PU_SYNC_FIR_ACTION0_REG_RESERVED = 9 ;
+static const uint8_t P9N2_PU_SYNC_FIR_ACTION0_REG_SCOM_PARITY_ERR2 = 10 ;
+static const uint8_t P9N2_PU_SYNC_FIR_ACTION0_REG_SCOM_PARITY_ERR = 11 ;
+
+static const uint8_t P9N2_PU_SYNC_FIR_ACTION1_REG_INVALID_TRANSFER_SIZE = 0 ;
+static const uint8_t P9N2_PU_SYNC_FIR_ACTION1_REG_INVALID_COMMAND = 1 ;
+static const uint8_t P9N2_PU_SYNC_FIR_ACTION1_REG_INVALID_ADDRESS_ALIGNMENT = 2 ;
+static const uint8_t P9N2_PU_SYNC_FIR_ACTION1_REG_OPB_ERROR = 3 ;
+static const uint8_t P9N2_PU_SYNC_FIR_ACTION1_REG_OPB_TIMEOUT = 4 ;
+static const uint8_t P9N2_PU_SYNC_FIR_ACTION1_REG_OPB_MASTER_HANG_TIMEOUT = 5 ;
+static const uint8_t P9N2_PU_SYNC_FIR_ACTION1_REG_CMD_BUFFER_PAR_ERR = 6 ;
+static const uint8_t P9N2_PU_SYNC_FIR_ACTION1_REG_DAT_BUFFER_PAR_ERR = 7 ;
+static const uint8_t P9N2_PU_SYNC_FIR_ACTION1_REG_RETURNQ_ERR = 8 ;
+static const uint8_t P9N2_PU_SYNC_FIR_ACTION1_REG_RESERVED = 9 ;
+static const uint8_t P9N2_PU_SYNC_FIR_ACTION1_REG_SCOM_PARITY_ERR2 = 10 ;
+static const uint8_t P9N2_PU_SYNC_FIR_ACTION1_REG_SCOM_PARITY_ERR = 11 ;
+
+static const uint8_t P9N2_PU_SYNC_FIR_MASK_REG_INVALID_TRANSFER_SIZE = 0 ;
+static const uint8_t P9N2_PU_SYNC_FIR_MASK_REG_INVALID_COMMAND = 1 ;
+static const uint8_t P9N2_PU_SYNC_FIR_MASK_REG_INVALID_ADDRESS_ALIGNMENT = 2 ;
+static const uint8_t P9N2_PU_SYNC_FIR_MASK_REG_OPB_ERROR = 3 ;
+static const uint8_t P9N2_PU_SYNC_FIR_MASK_REG_OPB_TIMEOUT = 4 ;
+static const uint8_t P9N2_PU_SYNC_FIR_MASK_REG_OPB_MASTER_HANG_TIMEOUT = 5 ;
+static const uint8_t P9N2_PU_SYNC_FIR_MASK_REG_CMD_BUFFER_PAR_ERR = 6 ;
+static const uint8_t P9N2_PU_SYNC_FIR_MASK_REG_DAT_BUFFER_PAR_ERR = 7 ;
+static const uint8_t P9N2_PU_SYNC_FIR_MASK_REG_RETURNQ_ERR = 8 ;
+static const uint8_t P9N2_PU_SYNC_FIR_MASK_REG_RESERVED = 9 ;
+static const uint8_t P9N2_PU_SYNC_FIR_MASK_REG_SCOM_PARITY_ERR2 = 10 ;
+static const uint8_t P9N2_PU_SYNC_FIR_MASK_REG_SCOM_PARITY_ERR = 11 ;
+
+static const uint8_t P9N2_PU_SYNC_FIR_REG_INVALID_TRANSFER_SIZE = 0 ;
+static const uint8_t P9N2_PU_SYNC_FIR_REG_INVALID_COMMAND = 1 ;
+static const uint8_t P9N2_PU_SYNC_FIR_REG_INVALID_ADDRESS_ALIGNMENT = 2 ;
+static const uint8_t P9N2_PU_SYNC_FIR_REG_OPB_ERROR = 3 ;
+static const uint8_t P9N2_PU_SYNC_FIR_REG_OPB_TIMEOUT = 4 ;
+static const uint8_t P9N2_PU_SYNC_FIR_REG_OPB_MASTER_HANG_TIMEOUT = 5 ;
+static const uint8_t P9N2_PU_SYNC_FIR_REG_CMD_BUFFER_PAR_ERR = 6 ;
+static const uint8_t P9N2_PU_SYNC_FIR_REG_DAT_BUFFER_PAR_ERR = 7 ;
+static const uint8_t P9N2_PU_SYNC_FIR_REG_RETURNQ_ERR = 8 ;
+static const uint8_t P9N2_PU_SYNC_FIR_REG_RESERVED = 9 ;
+static const uint8_t P9N2_PU_SYNC_FIR_REG_PARITY_ERR2 = 10 ;
+static const uint8_t P9N2_PU_SYNC_FIR_REG_PARITY_ERR = 11 ;
+
+static const uint8_t P9N2_PU_SYNC_FIR_WOF_REG_WOF = 0 ;
+static const uint8_t P9N2_PU_SYNC_FIR_WOF_REG_WOF_LEN = 6 ;
+
+static const uint8_t P9N2__SM1_TCE_KILL_INVALIDATE_ALL = 0 ;
+static const uint8_t P9N2__SM1_TCE_KILL_INVALIDATE_ONE = 2 ;
+static const uint8_t P9N2__SM1_TCE_KILL_INVALIDATE_PE_NUMBER = 4 ;
+static const uint8_t P9N2__SM1_TCE_KILL_INVALIDATE_PE_NUMBER_LEN = 4 ;
+static const uint8_t P9N2__SM1_TCE_KILL_INVALIDATE_ADDRESS = 15 ;
+static const uint8_t P9N2__SM1_TCE_KILL_INVALIDATE_ADDRESS_LEN = 37 ;
+
+static const uint8_t P9N2__SM2_TEST_CERR_ATR_ERR_INJ_PEND = 0 ;
+static const uint8_t P9N2__SM2_TEST_CERR_MAP_ERR_INJ_PEND = 1 ;
+static const uint8_t P9N2__SM2_TEST_CERR_REGSEL = 56 ;
+static const uint8_t P9N2__SM2_TEST_CERR_REGSEL_LEN = 2 ;
+static const uint8_t P9N2__SM2_TEST_CERR_BITSEL = 58 ;
+static const uint8_t P9N2__SM2_TEST_CERR_BITSEL_LEN = 6 ;
+
+static const uint8_t P9N2_CAPP_TFMR_MAX_CYC_BET_STEPS = 0 ;
+static const uint8_t P9N2_CAPP_TFMR_MAX_CYC_BET_STEPS_LEN = 8 ;
+static const uint8_t P9N2_CAPP_TFMR_N_CLKS_PER_STEP = 8 ;
+static const uint8_t P9N2_CAPP_TFMR_N_CLKS_PER_STEP_LEN = 2 ;
+static const uint8_t P9N2_CAPP_TFMR_RESERVED_BIT10 = 10 ;
+static const uint8_t P9N2_CAPP_TFMR_SYNC_BIT_SEL = 11 ;
+static const uint8_t P9N2_CAPP_TFMR_SYNC_BIT_SEL_LEN = 3 ;
+static const uint8_t P9N2_CAPP_TFMR_TB_ECLIPZ = 14 ;
+static const uint8_t P9N2_CAPP_TFMR_RESERVED_BIT15 = 15 ;
+static const uint8_t P9N2_CAPP_TFMR_LOAD_TOD_MOD = 16 ;
+static const uint8_t P9N2_CAPP_TFMR_RESERVED_BIT17 = 17 ;
+static const uint8_t P9N2_CAPP_TFMR_MOVE_CHIP_TOD_TO_TB = 18 ;
+static const uint8_t P9N2_CAPP_TFMR_RESERVED_BIT19 = 19 ;
+static const uint8_t P9N2_CAPP_TFMR_RESERVED_BIT20 = 20 ;
+static const uint8_t P9N2_CAPP_TFMR_RESERVED_BIT21 = 21 ;
+static const uint8_t P9N2_CAPP_TFMR_RESERVED_BIT22 = 22 ;
+static const uint8_t P9N2_CAPP_TFMR_RESERVED_BIT23 = 23 ;
+static const uint8_t P9N2_CAPP_TFMR_CLEAR_TB_ERRORS = 24 ;
+static const uint8_t P9N2_CAPP_TFMR_TBST_CORRUPT = 27 ;
+static const uint8_t P9N2_CAPP_TFMR_TBST_ENCODED = 28 ;
+static const uint8_t P9N2_CAPP_TFMR_TBST_ENCODED_LEN = 4 ;
+static const uint8_t P9N2_CAPP_TFMR_TBST_LAST = 32 ;
+static const uint8_t P9N2_CAPP_TFMR_TBST_LAST_LEN = 4 ;
+static const uint8_t P9N2_CAPP_TFMR_TB_ENABLED = 40 ;
+static const uint8_t P9N2_CAPP_TFMR_TB_VALID = 41 ;
+static const uint8_t P9N2_CAPP_TFMR_TB_SYNC_OCCURRED = 42 ;
+static const uint8_t P9N2_CAPP_TFMR_TB_MISSING_SYNC = 43 ;
+static const uint8_t P9N2_CAPP_TFMR_TB_MISSING_STEP = 44 ;
+static const uint8_t P9N2_CAPP_TFMR_TB_RESIDUE_ERR = 45 ;
+static const uint8_t P9N2_CAPP_TFMR_FIRMWARE_CONTROL_ERROR = 46 ;
+static const uint8_t P9N2_CAPP_TFMR_CHIP_TOD_STATUS = 47 ;
+static const uint8_t P9N2_CAPP_TFMR_CHIP_TOD_STATUS_LEN = 4 ;
+static const uint8_t P9N2_CAPP_TFMR_CHIP_TOD_INTERRUPT = 51 ;
+static const uint8_t P9N2_CAPP_TFMR_TFMR_CORRUPT = 60 ;
+
+static const uint8_t P9N2_PEC_THERM_MODE_REG_DIS_CPM_BUBBLE_CORR = 0 ;
+static const uint8_t P9N2_PEC_THERM_MODE_REG_FORCE_THRES_ACT = 1 ;
+static const uint8_t P9N2_PEC_THERM_MODE_REG_THRES_TRIP_ENA = 2 ;
+static const uint8_t P9N2_PEC_THERM_MODE_REG_THRES_TRIP_ENA_LEN = 3 ;
+static const uint8_t P9N2_PEC_THERM_MODE_REG_DTS_SAMPLE_ENA = 5 ;
+static const uint8_t P9N2_PEC_THERM_MODE_REG_SAMPLE_PULSE_CNT = 6 ;
+static const uint8_t P9N2_PEC_THERM_MODE_REG_SAMPLE_PULSE_CNT_LEN = 4 ;
+static const uint8_t P9N2_PEC_THERM_MODE_REG_THRES_ENA = 10 ;
+static const uint8_t P9N2_PEC_THERM_MODE_REG_THRES_ENA_LEN = 2 ;
+static const uint8_t P9N2_PEC_THERM_MODE_REG_DTS_TRIGGER = 12 ;
+static const uint8_t P9N2_PEC_THERM_MODE_REG_DTS_TRIGGER_SEL = 13 ;
+static const uint8_t P9N2_PEC_THERM_MODE_REG_THRES_OVERFLOW_MASK = 14 ;
+static const uint8_t P9N2_PEC_THERM_MODE_REG_UNUSED = 15 ;
+static const uint8_t P9N2_PEC_THERM_MODE_REG_DTS_READ_SEL = 16 ;
+static const uint8_t P9N2_PEC_THERM_MODE_REG_DTS_READ_SEL_LEN = 4 ;
+static const uint8_t P9N2_PEC_THERM_MODE_REG_DTS_ENABLE_L1 = 20 ;
+static const uint8_t P9N2_PEC_THERM_MODE_REG_DTS_ENABLE_L1_LEN = 2 ;
+static const uint8_t P9N2_PEC_THERM_MODE_REG_THERM_CPM_ENABLE_L1 = 35 ;
+static const uint8_t P9N2_PEC_THERM_MODE_REG_THERM_CPM_ENABLE_L1_LEN = 2 ;
+
+static const uint8_t P9N2_PEC_TIMEOUT_REG_INT_TIMEOUT = 0 ;
+static const uint8_t P9N2_PEC_TIMEOUT_REG_INT_TIMEOUT_LEN = 2 ;
+
+static const uint8_t P9N2_PEC_TIMESTAMP_COUNTER_READ_VALUE = 0 ;
+static const uint8_t P9N2_PEC_TIMESTAMP_COUNTER_READ_VALUE_LEN = 44 ;
+static const uint8_t P9N2_PEC_TIMESTAMP_COUNTER_READ_OVERFLOW_ERR = 44 ;
+
+static const uint8_t P9N2_CAPP_TLBI_ERROR_REPORT_IN_TIMEOUT = 0 ;
+static const uint8_t P9N2_CAPP_TLBI_ERROR_REPORT_IN_SEQ_ERR = 1 ;
+static const uint8_t P9N2_CAPP_TLBI_ERROR_REPORT_IN_SEQ_PERR = 2 ;
+static const uint8_t P9N2_CAPP_TLBI_ERROR_REPORT_IN_BAD_OP_ERR = 3 ;
+static const uint8_t P9N2_CAPP_TLBI_ERROR_REPORT_IN_SNP_ADDR_PERR = 4 ;
+static const uint8_t P9N2_CAPP_TLBI_ERROR_REPORT_IN_SNP_TTAG_PERR = 5 ;
+
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG0_LVALID = 0 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG0_PVALID = 1 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG0_PID = 32 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG0_PID_LEN = 20 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG0_LPID = 52 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG0_LPID_LEN = 12 ;
+
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG1_LVALID = 0 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG1_PVALID = 1 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG1_PID = 32 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG1_PID_LEN = 20 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG1_LPID = 52 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG1_LPID_LEN = 12 ;
+
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG10_LVALID = 0 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG10_PVALID = 1 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG10_PID = 32 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG10_PID_LEN = 20 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG10_LPID = 52 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG10_LPID_LEN = 12 ;
+
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG11_LVALID = 0 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG11_PVALID = 1 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG11_PID = 32 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG11_PID_LEN = 20 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG11_LPID = 52 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG11_LPID_LEN = 12 ;
+
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG12_LVALID = 0 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG12_PVALID = 1 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG12_PID = 32 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG12_PID_LEN = 20 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG12_LPID = 52 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG12_LPID_LEN = 12 ;
+
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG13_LVALID = 0 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG13_PVALID = 1 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG13_PID = 32 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG13_PID_LEN = 20 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG13_LPID = 52 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG13_LPID_LEN = 12 ;
+
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG14_LVALID = 0 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG14_PVALID = 1 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG14_PID = 32 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG14_PID_LEN = 20 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG14_LPID = 52 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG14_LPID_LEN = 12 ;
+
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG15_LVALID = 0 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG15_PVALID = 1 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG15_PID = 32 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG15_PID_LEN = 20 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG15_LPID = 52 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG15_LPID_LEN = 12 ;
+
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG2_LVALID = 0 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG2_PVALID = 1 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG2_PID = 32 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG2_PID_LEN = 20 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG2_LPID = 52 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG2_LPID_LEN = 12 ;
+
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG3_LVALID = 0 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG3_PVALID = 1 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG3_PID = 32 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG3_PID_LEN = 20 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG3_LPID = 52 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG3_LPID_LEN = 12 ;
+
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG4_LVALID = 0 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG4_PVALID = 1 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG4_PID = 32 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG4_PID_LEN = 20 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG4_LPID = 52 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG4_LPID_LEN = 12 ;
+
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG5_LVALID = 0 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG5_PVALID = 1 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG5_PID = 32 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG5_PID_LEN = 20 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG5_LPID = 52 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG5_LPID_LEN = 12 ;
+
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG6_LVALID = 0 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG6_PVALID = 1 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG6_PID = 32 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG6_PID_LEN = 20 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG6_LPID = 52 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG6_LPID_LEN = 12 ;
+
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG7_LVALID = 0 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG7_PVALID = 1 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG7_PID = 32 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG7_PID_LEN = 20 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG7_LPID = 52 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG7_LPID_LEN = 12 ;
+
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG8_LVALID = 0 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG8_PVALID = 1 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG8_PID = 32 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG8_PID_LEN = 20 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG8_LPID = 52 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG8_LPID_LEN = 12 ;
+
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG9_LVALID = 0 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG9_PVALID = 1 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG9_PID = 32 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG9_PID_LEN = 20 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG9_LPID = 52 ;
+static const uint8_t P9N2_CAPP_TLBI_FILTER_REG9_LPID_LEN = 12 ;
+
+static const uint8_t P9N2_CAPP_TLBI_QOS_COMPARE = 0 ;
+static const uint8_t P9N2_CAPP_TLBI_QOS_COMPARE_LEN = 8 ;
+static const uint8_t P9N2_CAPP_TLBI_QOS_INC = 8 ;
+static const uint8_t P9N2_CAPP_TLBI_QOS_INC_LEN = 8 ;
+static const uint8_t P9N2_CAPP_TLBI_QOS_DEC = 16 ;
+static const uint8_t P9N2_CAPP_TLBI_QOS_DEC_LEN = 8 ;
+static const uint8_t P9N2_CAPP_TLBI_QOS_EN = 24 ;
+
+static const uint8_t P9N2_PU_NPU_CTL_TLX_CREDIT_STATUS_VC0_COUNT = 0 ;
+static const uint8_t P9N2_PU_NPU_CTL_TLX_CREDIT_STATUS_VC0_COUNT_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_CTL_TLX_CREDIT_STATUS_VC1_COUNT = 8 ;
+static const uint8_t P9N2_PU_NPU_CTL_TLX_CREDIT_STATUS_VC1_COUNT_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_CTL_TLX_CREDIT_STATUS_VC2_COUNT = 16 ;
+static const uint8_t P9N2_PU_NPU_CTL_TLX_CREDIT_STATUS_VC2_COUNT_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_CTL_TLX_CREDIT_STATUS_VC3_COUNT = 24 ;
+static const uint8_t P9N2_PU_NPU_CTL_TLX_CREDIT_STATUS_VC3_COUNT_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_CTL_TLX_CREDIT_STATUS_DCP0_COUNT = 32 ;
+static const uint8_t P9N2_PU_NPU_CTL_TLX_CREDIT_STATUS_DCP0_COUNT_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_CTL_TLX_CREDIT_STATUS_DCP2_COUNT = 40 ;
+static const uint8_t P9N2_PU_NPU_CTL_TLX_CREDIT_STATUS_DCP2_COUNT_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_CTL_TLX_CREDIT_STATUS_DCP3_COUNT = 48 ;
+static const uint8_t P9N2_PU_NPU_CTL_TLX_CREDIT_STATUS_DCP3_COUNT_LEN = 8 ;
+
+static const uint8_t P9N2__CTL_TLX_CREDIT_STATUS_VC0_COUNT = 0 ;
+static const uint8_t P9N2__CTL_TLX_CREDIT_STATUS_VC0_COUNT_LEN = 8 ;
+static const uint8_t P9N2__CTL_TLX_CREDIT_STATUS_VC1_COUNT = 8 ;
+static const uint8_t P9N2__CTL_TLX_CREDIT_STATUS_VC1_COUNT_LEN = 8 ;
+static const uint8_t P9N2__CTL_TLX_CREDIT_STATUS_VC2_COUNT = 16 ;
+static const uint8_t P9N2__CTL_TLX_CREDIT_STATUS_VC2_COUNT_LEN = 8 ;
+static const uint8_t P9N2__CTL_TLX_CREDIT_STATUS_VC3_COUNT = 24 ;
+static const uint8_t P9N2__CTL_TLX_CREDIT_STATUS_VC3_COUNT_LEN = 8 ;
+static const uint8_t P9N2__CTL_TLX_CREDIT_STATUS_DCP0_COUNT = 32 ;
+static const uint8_t P9N2__CTL_TLX_CREDIT_STATUS_DCP0_COUNT_LEN = 8 ;
+static const uint8_t P9N2__CTL_TLX_CREDIT_STATUS_DCP2_COUNT = 40 ;
+static const uint8_t P9N2__CTL_TLX_CREDIT_STATUS_DCP2_COUNT_LEN = 8 ;
+static const uint8_t P9N2__CTL_TLX_CREDIT_STATUS_DCP3_COUNT = 48 ;
+static const uint8_t P9N2__CTL_TLX_CREDIT_STATUS_DCP3_COUNT_LEN = 8 ;
+
+static const uint8_t P9N2__SM3_TLX_CREDIT_STATUS_VC0_COUNT = 0 ;
+static const uint8_t P9N2__SM3_TLX_CREDIT_STATUS_VC0_COUNT_LEN = 8 ;
+static const uint8_t P9N2__SM3_TLX_CREDIT_STATUS_VC1_COUNT = 8 ;
+static const uint8_t P9N2__SM3_TLX_CREDIT_STATUS_VC1_COUNT_LEN = 8 ;
+static const uint8_t P9N2__SM3_TLX_CREDIT_STATUS_VC2_COUNT = 16 ;
+static const uint8_t P9N2__SM3_TLX_CREDIT_STATUS_VC2_COUNT_LEN = 8 ;
+static const uint8_t P9N2__SM3_TLX_CREDIT_STATUS_VC3_COUNT = 24 ;
+static const uint8_t P9N2__SM3_TLX_CREDIT_STATUS_VC3_COUNT_LEN = 8 ;
+static const uint8_t P9N2__SM3_TLX_CREDIT_STATUS_DCP0_COUNT = 32 ;
+static const uint8_t P9N2__SM3_TLX_CREDIT_STATUS_DCP0_COUNT_LEN = 8 ;
+static const uint8_t P9N2__SM3_TLX_CREDIT_STATUS_DCP2_COUNT = 40 ;
+static const uint8_t P9N2__SM3_TLX_CREDIT_STATUS_DCP2_COUNT_LEN = 8 ;
+static const uint8_t P9N2__SM3_TLX_CREDIT_STATUS_DCP3_COUNT = 48 ;
+static const uint8_t P9N2__SM3_TLX_CREDIT_STATUS_DCP3_COUNT_LEN = 8 ;
+
+static const uint8_t P9N2_PU_NPU_SM3_TLX_CREDIT_STATUS_VC0_COUNT = 0 ;
+static const uint8_t P9N2_PU_NPU_SM3_TLX_CREDIT_STATUS_VC0_COUNT_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_SM3_TLX_CREDIT_STATUS_VC1_COUNT = 8 ;
+static const uint8_t P9N2_PU_NPU_SM3_TLX_CREDIT_STATUS_VC1_COUNT_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_SM3_TLX_CREDIT_STATUS_VC2_COUNT = 16 ;
+static const uint8_t P9N2_PU_NPU_SM3_TLX_CREDIT_STATUS_VC2_COUNT_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_SM3_TLX_CREDIT_STATUS_VC3_COUNT = 24 ;
+static const uint8_t P9N2_PU_NPU_SM3_TLX_CREDIT_STATUS_VC3_COUNT_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_SM3_TLX_CREDIT_STATUS_DCP0_COUNT = 32 ;
+static const uint8_t P9N2_PU_NPU_SM3_TLX_CREDIT_STATUS_DCP0_COUNT_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_SM3_TLX_CREDIT_STATUS_DCP2_COUNT = 40 ;
+static const uint8_t P9N2_PU_NPU_SM3_TLX_CREDIT_STATUS_DCP2_COUNT_LEN = 8 ;
+static const uint8_t P9N2_PU_NPU_SM3_TLX_CREDIT_STATUS_DCP3_COUNT = 48 ;
+static const uint8_t P9N2_PU_NPU_SM3_TLX_CREDIT_STATUS_DCP3_COUNT_LEN = 8 ;
+
+static const uint8_t P9N2_PU_NPU_CTL_TL_DCP_CREDIT_STATUS_DCP0_COUNT = 0 ;
+static const uint8_t P9N2_PU_NPU_CTL_TL_DCP_CREDIT_STATUS_DCP0_COUNT_LEN = 16 ;
+static const uint8_t P9N2_PU_NPU_CTL_TL_DCP_CREDIT_STATUS_DCP1_COUNT = 16 ;
+static const uint8_t P9N2_PU_NPU_CTL_TL_DCP_CREDIT_STATUS_DCP1_COUNT_LEN = 16 ;
+
+static const uint8_t P9N2__CTL_TL_DCP_CREDIT_STATUS_DCP0_COUNT = 0 ;
+static const uint8_t P9N2__CTL_TL_DCP_CREDIT_STATUS_DCP0_COUNT_LEN = 16 ;
+static const uint8_t P9N2__CTL_TL_DCP_CREDIT_STATUS_DCP1_COUNT = 16 ;
+static const uint8_t P9N2__CTL_TL_DCP_CREDIT_STATUS_DCP1_COUNT_LEN = 16 ;
+
+static const uint8_t P9N2__SM3_TL_DCP_CREDIT_STATUS_DCP0_COUNT = 0 ;
+static const uint8_t P9N2__SM3_TL_DCP_CREDIT_STATUS_DCP0_COUNT_LEN = 16 ;
+static const uint8_t P9N2__SM3_TL_DCP_CREDIT_STATUS_DCP1_COUNT = 16 ;
+static const uint8_t P9N2__SM3_TL_DCP_CREDIT_STATUS_DCP1_COUNT_LEN = 16 ;
+
+static const uint8_t P9N2_PU_NPU_SM3_TL_DCP_CREDIT_STATUS_DCP0_COUNT = 0 ;
+static const uint8_t P9N2_PU_NPU_SM3_TL_DCP_CREDIT_STATUS_DCP0_COUNT_LEN = 16 ;
+static const uint8_t P9N2_PU_NPU_SM3_TL_DCP_CREDIT_STATUS_DCP1_COUNT = 16 ;
+static const uint8_t P9N2_PU_NPU_SM3_TL_DCP_CREDIT_STATUS_DCP1_COUNT_LEN = 16 ;
+
+static const uint8_t P9N2_PU_NPU_CTL_TL_VC_CREDIT_STATUS_VC0_COUNT = 0 ;
+static const uint8_t P9N2_PU_NPU_CTL_TL_VC_CREDIT_STATUS_VC0_COUNT_LEN = 16 ;
+static const uint8_t P9N2_PU_NPU_CTL_TL_VC_CREDIT_STATUS_VC1_COUNT = 16 ;
+static const uint8_t P9N2_PU_NPU_CTL_TL_VC_CREDIT_STATUS_VC1_COUNT_LEN = 16 ;
+static const uint8_t P9N2_PU_NPU_CTL_TL_VC_CREDIT_STATUS_VC2_COUNT = 32 ;
+static const uint8_t P9N2_PU_NPU_CTL_TL_VC_CREDIT_STATUS_VC2_COUNT_LEN = 16 ;
+
+static const uint8_t P9N2__CTL_TL_VC_CREDIT_STATUS_VC0_COUNT = 0 ;
+static const uint8_t P9N2__CTL_TL_VC_CREDIT_STATUS_VC0_COUNT_LEN = 16 ;
+static const uint8_t P9N2__CTL_TL_VC_CREDIT_STATUS_VC1_COUNT = 16 ;
+static const uint8_t P9N2__CTL_TL_VC_CREDIT_STATUS_VC1_COUNT_LEN = 16 ;
+static const uint8_t P9N2__CTL_TL_VC_CREDIT_STATUS_VC2_COUNT = 32 ;
+static const uint8_t P9N2__CTL_TL_VC_CREDIT_STATUS_VC2_COUNT_LEN = 16 ;
+
+static const uint8_t P9N2__SM3_TL_VC_CREDIT_STATUS_VC0_COUNT = 0 ;
+static const uint8_t P9N2__SM3_TL_VC_CREDIT_STATUS_VC0_COUNT_LEN = 16 ;
+static const uint8_t P9N2__SM3_TL_VC_CREDIT_STATUS_VC1_COUNT = 16 ;
+static const uint8_t P9N2__SM3_TL_VC_CREDIT_STATUS_VC1_COUNT_LEN = 16 ;
+static const uint8_t P9N2__SM3_TL_VC_CREDIT_STATUS_VC2_COUNT = 32 ;
+static const uint8_t P9N2__SM3_TL_VC_CREDIT_STATUS_VC2_COUNT_LEN = 16 ;
+
+static const uint8_t P9N2_PU_NPU_SM3_TL_VC_CREDIT_STATUS_VC0_COUNT = 0 ;
+static const uint8_t P9N2_PU_NPU_SM3_TL_VC_CREDIT_STATUS_VC0_COUNT_LEN = 16 ;
+static const uint8_t P9N2_PU_NPU_SM3_TL_VC_CREDIT_STATUS_VC1_COUNT = 16 ;
+static const uint8_t P9N2_PU_NPU_SM3_TL_VC_CREDIT_STATUS_VC1_COUNT_LEN = 16 ;
+static const uint8_t P9N2_PU_NPU_SM3_TL_VC_CREDIT_STATUS_VC2_COUNT = 32 ;
+static const uint8_t P9N2_PU_NPU_SM3_TL_VC_CREDIT_STATUS_VC2_COUNT_LEN = 16 ;
+
+static const uint8_t P9N2_PU_TOD_CMD_REG_ADR = 30 ;
+static const uint8_t P9N2_PU_TOD_CMD_REG_ADR_LEN = 31 ;
+
+static const uint8_t P9N2_PU_TOD_DATA_RCV_REG_PCB = 0 ;
+static const uint8_t P9N2_PU_TOD_DATA_RCV_REG_PCB_LEN = 64 ;
+
+static const uint8_t P9N2_PU_TOD_DATA_SND_REG_PCB = 0 ;
+static const uint8_t P9N2_PU_TOD_DATA_SND_REG_PCB_LEN = 64 ;
+
+static const uint8_t P9N2_CAPP_TOD_SYNC000_TIMEBASE = 55 ;
+static const uint8_t P9N2_CAPP_TOD_SYNC000_TIMEBASE_LEN = 5 ;
+static const uint8_t P9N2_CAPP_TOD_SYNC000_CHIP_STATUS = 60 ;
+static const uint8_t P9N2_CAPP_TOD_SYNC000_CHIP_STATUS_LEN = 4 ;
+
+static const uint8_t P9N2_PEC_TRACE_HI_DATA_REG_DATA = 0 ;
+static const uint8_t P9N2_PEC_TRACE_HI_DATA_REG_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_PU_TRACE_HI_DATA_REG_DATA = 0 ;
+static const uint8_t P9N2_PU_TRACE_HI_DATA_REG_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_PEC_TRACE_LO_DATA_REG_DATA = 0 ;
+static const uint8_t P9N2_PEC_TRACE_LO_DATA_REG_DATA_LEN = 32 ;
+static const uint8_t P9N2_PEC_TRACE_LO_DATA_REG_ADDRESS = 32 ;
+static const uint8_t P9N2_PEC_TRACE_LO_DATA_REG_ADDRESS_LEN = 10 ;
+static const uint8_t P9N2_PEC_TRACE_LO_DATA_REG_LAST_BANK = 42 ;
+static const uint8_t P9N2_PEC_TRACE_LO_DATA_REG_LAST_BANK_LEN = 9 ;
+static const uint8_t P9N2_PEC_TRACE_LO_DATA_REG_LAST_BANK_VALID = 51 ;
+static const uint8_t P9N2_PEC_TRACE_LO_DATA_REG_WRITE_ON_RUN = 52 ;
+static const uint8_t P9N2_PEC_TRACE_LO_DATA_REG_RUNNING = 53 ;
+static const uint8_t P9N2_PEC_TRACE_LO_DATA_REG_HOLD_ADDRESS = 54 ;
+static const uint8_t P9N2_PEC_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN = 10 ;
+
+static const uint8_t P9N2_PU_TRACE_LO_DATA_REG_DATA = 0 ;
+static const uint8_t P9N2_PU_TRACE_LO_DATA_REG_DATA_LEN = 32 ;
+static const uint8_t P9N2_PU_TRACE_LO_DATA_REG_ADDRESS = 32 ;
+static const uint8_t P9N2_PU_TRACE_LO_DATA_REG_ADDRESS_LEN = 10 ;
+static const uint8_t P9N2_PU_TRACE_LO_DATA_REG_LAST_BANK = 42 ;
+static const uint8_t P9N2_PU_TRACE_LO_DATA_REG_LAST_BANK_LEN = 9 ;
+static const uint8_t P9N2_PU_TRACE_LO_DATA_REG_LAST_BANK_VALID = 51 ;
+static const uint8_t P9N2_PU_TRACE_LO_DATA_REG_WRITE_ON_RUN = 52 ;
+static const uint8_t P9N2_PU_TRACE_LO_DATA_REG_RUNNING = 53 ;
+static const uint8_t P9N2_PU_TRACE_LO_DATA_REG_HOLD_ADDRESS = 54 ;
+static const uint8_t P9N2_PU_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN = 10 ;
+
+static const uint8_t P9N2_PEC_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE = 0 ;
+static const uint8_t P9N2_PEC_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE = 1 ;
+static const uint8_t P9N2_PEC_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE = 2 ;
+static const uint8_t P9N2_PEC_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN = 8 ;
+static const uint8_t P9N2_PEC_TRACE_TRCTRL_CONFIG_BANK_MODE = 10 ;
+static const uint8_t P9N2_PEC_TRACE_TRCTRL_CONFIG_ENH_MODE = 11 ;
+static const uint8_t P9N2_PEC_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL = 12 ;
+static const uint8_t P9N2_PEC_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN = 2 ;
+static const uint8_t P9N2_PEC_TRACE_TRCTRL_CONFIG_SELECT_CONTROL = 14 ;
+static const uint8_t P9N2_PEC_TRACE_TRCTRL_CONFIG_SELECT_CONTROL_LEN = 4 ;
+static const uint8_t P9N2_PEC_TRACE_TRCTRL_CONFIG_RUN_HOLD_OFF = 18 ;
+static const uint8_t P9N2_PEC_TRACE_TRCTRL_CONFIG_RUN_STATUS = 19 ;
+static const uint8_t P9N2_PEC_TRACE_TRCTRL_CONFIG_RUN_STICKY = 20 ;
+static const uint8_t P9N2_PEC_TRACE_TRCTRL_CONFIG_DISABLE_BANK_EDGE_DETECT = 21 ;
+static const uint8_t P9N2_PEC_TRACE_TRCTRL_CONFIG_CONTROL_UNUSED = 22 ;
+static const uint8_t P9N2_PEC_TRACE_TRCTRL_CONFIG_CONTROL_UNUSED_LEN = 6 ;
+
+static const uint8_t P9N2_PU_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE = 0 ;
+static const uint8_t P9N2_PU_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE = 1 ;
+static const uint8_t P9N2_PU_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE = 2 ;
+static const uint8_t P9N2_PU_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN = 8 ;
+static const uint8_t P9N2_PU_TRACE_TRCTRL_CONFIG_BANK_MODE = 10 ;
+static const uint8_t P9N2_PU_TRACE_TRCTRL_CONFIG_ENH_MODE = 11 ;
+static const uint8_t P9N2_PU_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL = 12 ;
+static const uint8_t P9N2_PU_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN = 2 ;
+static const uint8_t P9N2_PU_TRACE_TRCTRL_CONFIG_SELECT_CONTROL = 14 ;
+static const uint8_t P9N2_PU_TRACE_TRCTRL_CONFIG_SELECT_CONTROL_LEN = 4 ;
+static const uint8_t P9N2_PU_TRACE_TRCTRL_CONFIG_RUN_HOLD_OFF = 18 ;
+static const uint8_t P9N2_PU_TRACE_TRCTRL_CONFIG_RUN_STATUS = 19 ;
+static const uint8_t P9N2_PU_TRACE_TRCTRL_CONFIG_RUN_STICKY = 20 ;
+static const uint8_t P9N2_PU_TRACE_TRCTRL_CONFIG_DISABLE_BANK_EDGE_DETECT = 21 ;
+static const uint8_t P9N2_PU_TRACE_TRCTRL_CONFIG_CONTROL_UNUSED = 22 ;
+static const uint8_t P9N2_PU_TRACE_TRCTRL_CONFIG_CONTROL_UNUSED_LEN = 6 ;
+
+static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 = 0 ;
+static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN = 64 ;
+
+static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 = 0 ;
+static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN = 64 ;
+
+static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 = 0 ;
+static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN = 24 ;
+
+static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 = 0 ;
+static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN = 24 ;
+
+static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_2_PATTERNA = 0 ;
+static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN = 24 ;
+static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_2_PATTERNB = 24 ;
+static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN = 24 ;
+
+static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_2_PATTERNA = 0 ;
+static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN = 24 ;
+static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_2_PATTERNB = 24 ;
+static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN = 24 ;
+
+static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_3_PATTERNC = 0 ;
+static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN = 24 ;
+static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_3_PATTERND = 24 ;
+static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_3_PATTERND_LEN = 24 ;
+
+static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_3_PATTERNC = 0 ;
+static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN = 24 ;
+static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_3_PATTERND = 24 ;
+static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_3_PATTERND_LEN = 24 ;
+
+static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_4_MASKA = 0 ;
+static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_4_MASKA_LEN = 24 ;
+static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_4_MASKB = 24 ;
+static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_4_MASKB_LEN = 24 ;
+
+static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_4_MASKA = 0 ;
+static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_4_MASKA_LEN = 24 ;
+static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_4_MASKB = 24 ;
+static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_4_MASKB_LEN = 24 ;
+
+static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_5_MASKC = 0 ;
+static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_5_MASKC_LEN = 24 ;
+static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_5_MASKD = 24 ;
+static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_5_MASKD_LEN = 24 ;
+
+static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_5_MASKC = 0 ;
+static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_5_MASKC_LEN = 24 ;
+static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_5_MASKD = 24 ;
+static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_5_MASKD_LEN = 24 ;
+
+static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION = 0 ;
+static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK = 1 ;
+static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL = 2 ;
+static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN = 2 ;
+static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL = 4 ;
+static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN = 2 ;
+static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL = 6 ;
+static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN = 2 ;
+static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL = 8 ;
+static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN = 2 ;
+static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK = 10 ;
+static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN = 4 ;
+static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK = 14 ;
+static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN = 4 ;
+static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK = 18 ;
+static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN = 4 ;
+static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK = 22 ;
+static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN = 4 ;
+static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE = 26 ;
+static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE = 27 ;
+static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE = 28 ;
+static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN = 4 ;
+static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_9_ERROR_CMP_MASK = 32 ;
+static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_9_ERROR_CMP_PATTERN = 33 ;
+static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_9_TRIG0_ERR_CMP = 34 ;
+static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_9_TRIG1_ERR_CMP = 35 ;
+static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES = 36 ;
+static const uint8_t P9N2_PEC_TRACE_TRDATA_CONFIG_9_SPARE_LT = 37 ;
+
+static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION = 0 ;
+static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK = 1 ;
+static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL = 2 ;
+static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN = 2 ;
+static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL = 4 ;
+static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN = 2 ;
+static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL = 6 ;
+static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN = 2 ;
+static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL = 8 ;
+static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN = 2 ;
+static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK = 10 ;
+static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN = 4 ;
+static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK = 14 ;
+static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN = 4 ;
+static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK = 18 ;
+static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN = 4 ;
+static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK = 22 ;
+static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN = 4 ;
+static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE = 26 ;
+static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE = 27 ;
+static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE = 28 ;
+static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN = 4 ;
+static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_9_ERROR_CMP_MASK = 32 ;
+static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_9_ERROR_CMP_PATTERN = 33 ;
+static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_9_TRIG0_ERR_CMP = 34 ;
+static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_9_TRIG1_ERR_CMP = 35 ;
+static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES = 36 ;
+static const uint8_t P9N2_PU_TRACE_TRDATA_CONFIG_9_SPARE_LT = 37 ;
+
+static const uint8_t P9N2_PU_TRUST_CONTROL_FSP_TCE_ENABLE = 2 ;
+static const uint8_t P9N2_PU_TRUST_CONTROL_SECURE_BOOTH = 3 ;
+
+static const uint8_t P9N2_PHB_TUNNEL_BAR_REG_PE = 0 ;
+static const uint8_t P9N2_PHB_TUNNEL_BAR_REG_PE_LEN = 43 ;
+
+static const uint8_t P9N2_PEC_STACK0_TUNNEL_BAR_REG_PE = 0 ;
+static const uint8_t P9N2_PEC_STACK0_TUNNEL_BAR_REG_PE_LEN = 43 ;
+
+static const uint8_t P9N2_PU_NPU_CTL_TXI_ERR_INJ_CTRL_CE = 0 ;
+static const uint8_t P9N2_PU_NPU_CTL_TXI_ERR_INJ_CTRL_UE = 1 ;
+static const uint8_t P9N2_PU_NPU_CTL_TXI_ERR_INJ_DATA_CE = 2 ;
+static const uint8_t P9N2_PU_NPU_CTL_TXI_ERR_INJ_DATA_UE = 3 ;
+static const uint8_t P9N2_PU_NPU_CTL_TXI_ERR_INJ_CTRL_PEND = 4 ;
+static const uint8_t P9N2_PU_NPU_CTL_TXI_ERR_INJ_DATA_PEND = 5 ;
+
+static const uint8_t P9N2__CTL_TXI_ERR_INJ_CTRL_CE = 0 ;
+static const uint8_t P9N2__CTL_TXI_ERR_INJ_CTRL_UE = 1 ;
+static const uint8_t P9N2__CTL_TXI_ERR_INJ_DATA_CE = 2 ;
+static const uint8_t P9N2__CTL_TXI_ERR_INJ_DATA_UE = 3 ;
+static const uint8_t P9N2__CTL_TXI_ERR_INJ_CTRL_PEND = 4 ;
+static const uint8_t P9N2__CTL_TXI_ERR_INJ_DATA_PEND = 5 ;
+
+static const uint8_t P9N2__SM3_TXI_ERR_INJ_CTRL_CE = 0 ;
+static const uint8_t P9N2__SM3_TXI_ERR_INJ_CTRL_UE = 1 ;
+static const uint8_t P9N2__SM3_TXI_ERR_INJ_DATA_CE = 2 ;
+static const uint8_t P9N2__SM3_TXI_ERR_INJ_DATA_UE = 3 ;
+static const uint8_t P9N2__SM3_TXI_ERR_INJ_CTRL_PEND = 4 ;
+static const uint8_t P9N2__SM3_TXI_ERR_INJ_DATA_PEND = 5 ;
+
+static const uint8_t P9N2_PU_NPU_SM3_TXI_ERR_INJ_CTRL_CE = 0 ;
+static const uint8_t P9N2_PU_NPU_SM3_TXI_ERR_INJ_CTRL_UE = 1 ;
+static const uint8_t P9N2_PU_NPU_SM3_TXI_ERR_INJ_DATA_CE = 2 ;
+static const uint8_t P9N2_PU_NPU_SM3_TXI_ERR_INJ_DATA_UE = 3 ;
+static const uint8_t P9N2_PU_NPU_SM3_TXI_ERR_INJ_CTRL_PEND = 4 ;
+static const uint8_t P9N2_PU_NPU_SM3_TXI_ERR_INJ_DATA_PEND = 5 ;
+
+static const uint8_t P9N2_PU_TX_CH_FSM_REG_TX_CH_FSM = 0 ;
+static const uint8_t P9N2_PU_TX_CH_FSM_REG_TX_CH_FSM_LEN = 3 ;
+
+static const uint8_t P9N2_PU_TX_CH_INTADDR_REG_SCOM_MODE_0 = 0 ;
+static const uint8_t P9N2_PU_TX_CH_INTADDR_REG_SCOM_MODE_1 = 1 ;
+static const uint8_t P9N2_PU_TX_CH_INTADDR_REG_SCOM_MODE_2 = 2 ;
+static const uint8_t P9N2_PU_TX_CH_INTADDR_REG_SCOM_MODE_3 = 3 ;
+static const uint8_t P9N2_PU_TX_CH_INTADDR_REG_SCOM_MODE_4 = 4 ;
+static const uint8_t P9N2_PU_TX_CH_INTADDR_REG_SCOM_MODE_5 = 5 ;
+static const uint8_t P9N2_PU_TX_CH_INTADDR_REG_SCOM_MODE_6 = 6 ;
+static const uint8_t P9N2_PU_TX_CH_INTADDR_REG_SCOM_MODE_7 = 7 ;
+
+static const uint8_t P9N2_PU_TX_CH_MISC_REG_FSM = 0 ;
+static const uint8_t P9N2_PU_TX_CH_MISC_REG_FSM_LEN = 4 ;
+static const uint8_t P9N2_PU_TX_CH_MISC_REG_TFRAMESIZE = 7 ;
+static const uint8_t P9N2_PU_TX_CH_MISC_REG_TFRAMESIZE_LEN = 5 ;
+static const uint8_t P9N2_PU_TX_CH_MISC_REG_WEN0 = 12 ;
+static const uint8_t P9N2_PU_TX_CH_MISC_REG_WEN1 = 13 ;
+static const uint8_t P9N2_PU_TX_CH_MISC_REG_WEN2 = 14 ;
+static const uint8_t P9N2_PU_TX_CH_MISC_REG_DATA_REQ = 15 ;
+static const uint8_t P9N2_PU_TX_CH_MISC_REG_START_TRANS = 16 ;
+static const uint8_t P9N2_PU_TX_CH_MISC_REG_GXDATAAVAIL_Q = 17 ;
+
+static const uint8_t P9N2_PU_TX_CTRL_STAT_REG_ENABLE_SCWR_TO_TXRF = 0 ;
+static const uint8_t P9N2_PU_TX_CTRL_STAT_REG_DISABLE_ECC_COR_GXC_PSI = 1 ;
+static const uint8_t P9N2_PU_TX_CTRL_STAT_REG_DISABLE_ECC_COR_TXRF_PSI = 2 ;
+static const uint8_t P9N2_PU_TX_CTRL_STAT_REG_CRC_MODE = 3 ;
+static const uint8_t P9N2_PU_TX_CTRL_STAT_REG_CHIP_PERSONALISATION = 4 ;
+static const uint8_t P9N2_PU_TX_CTRL_STAT_REG_ENABLE_STREAMING_MODE = 5 ;
+static const uint8_t P9N2_PU_TX_CTRL_STAT_REG_CHIP_INTERFACEMODE = 6 ;
+static const uint8_t P9N2_PU_TX_CTRL_STAT_REG_DISABLE_TIMEOUT_AND_RETRY = 7 ;
+static const uint8_t P9N2_PU_TX_CTRL_STAT_REG_FENCE_IO_INTERFACE = 8 ;
+static const uint8_t P9N2_PU_TX_CTRL_STAT_REG_FENCE_GX_INTERFACE = 9 ;
+static const uint8_t P9N2_PU_TX_CTRL_STAT_REG_GX_ENABLE_OVERWRITE = 10 ;
+static const uint8_t P9N2_PU_TX_CTRL_STAT_REG_TXSC = 11 ;
+
+static const uint8_t P9N2_PU_TX_DBFF_REG0_DATA_BUFF0 = 0 ;
+static const uint8_t P9N2_PU_TX_DBFF_REG0_DATA_BUFF0_LEN = 32 ;
+
+static const uint8_t P9N2_PU_TX_DBFF_REG1_DATA_BUFF1 = 0 ;
+static const uint8_t P9N2_PU_TX_DBFF_REG1_DATA_BUFF1_LEN = 32 ;
+
+static const uint8_t P9N2_PU_TX_DF_FSM_REG_TX_DF_FSM = 0 ;
+static const uint8_t P9N2_PU_TX_DF_FSM_REG_TX_DF_FSM_LEN = 4 ;
+
+static const uint8_t P9N2_PU_NPU_CTL_TX_DL_CREDIT_STATUS_COUNT = 0 ;
+static const uint8_t P9N2_PU_NPU_CTL_TX_DL_CREDIT_STATUS_COUNT_LEN = 12 ;
+
+static const uint8_t P9N2__CTL_TX_DL_CREDIT_STATUS_COUNT = 0 ;
+static const uint8_t P9N2__CTL_TX_DL_CREDIT_STATUS_COUNT_LEN = 12 ;
+
+static const uint8_t P9N2__SM3_TX_DL_CREDIT_STATUS_COUNT = 0 ;
+static const uint8_t P9N2__SM3_TX_DL_CREDIT_STATUS_COUNT_LEN = 12 ;
+
+static const uint8_t P9N2_PU_NPU_SM3_TX_DL_CREDIT_STATUS_COUNT = 0 ;
+static const uint8_t P9N2_PU_NPU_SM3_TX_DL_CREDIT_STATUS_COUNT_LEN = 12 ;
+
+static const uint8_t P9N2_PU_TX_ERROR_REG_C1_PSITXINS_DATA_PCK = 0 ;
+static const uint8_t P9N2_PU_TX_ERROR_REG_C1_PSITXINS_TZRTMP_PCK = 1 ;
+static const uint8_t P9N2_PU_TX_ERROR_REG_C1_PSITXEI_SHIFT_PCK = 2 ;
+static const uint8_t P9N2_PU_TX_ERROR_REG_C1_PSITXEI_TRANSMIT_PCK = 3 ;
+static const uint8_t P9N2_PU_TX_ERROR_REG_C1_PSITXINS_PARITY = 4 ;
+static const uint8_t P9N2_PU_TX_ERROR_REG_C1_PSITXINS_UNDERRUN = 5 ;
+static const uint8_t P9N2_PU_TX_ERROR_REG_C2_PSITXBFF_DATA_PCK = 6 ;
+static const uint8_t P9N2_PU_TX_ERROR_REG_C1_PSITXBFF_TDO_PCK = 7 ;
+static const uint8_t P9N2_PU_TX_ERROR_REG_C2_PSITXBFF_TFC_PCK = 8 ;
+static const uint8_t P9N2_PU_TX_ERROR_REG_C2_PSITXLC_FSM_PCK = 9 ;
+static const uint8_t P9N2_PU_TX_ERROR_REG_C3_PSITXLC_DATA_BUFF_PCK = 10 ;
+static const uint8_t P9N2_PU_TX_ERROR_REG_C2_PSITXLC_TDO_PCK = 11 ;
+static const uint8_t P9N2_PU_TX_ERROR_REG_C2_PSITXLC_TADDR_PCK = 12 ;
+static const uint8_t P9N2_PU_TX_ERROR_REG_C2_PSITXLC_TCTRL_PCK = 13 ;
+static const uint8_t P9N2_PU_TX_ERROR_REG_C2_PSITXLC_UE_RF = 14 ;
+static const uint8_t P9N2_PU_TX_ERROR_REG_C0_PSITXLC_CE_RF = 15 ;
+static const uint8_t P9N2_PU_TX_ERROR_REG_C3_PSITXLC_UE_GX_2N = 16 ;
+static const uint8_t P9N2_PU_TX_ERROR_REG_C0_PSITXLC_CE_GX_2N = 17 ;
+static const uint8_t P9N2_PU_TX_ERROR_REG_C3_PSITXLC_DATA_GXST2_PCK_2N = 18 ;
+static const uint8_t P9N2_PU_TX_ERROR_REG_C3_PSITXLC_DATA_GXST3_PCK_2N = 19 ;
+static const uint8_t P9N2_PU_TX_ERROR_REG_C3_PSIRFACC_TADDR_PCK = 20 ;
+static const uint8_t P9N2_PU_TX_ERROR_REG_C3_PSIRFACC_TCTRL_PCK = 21 ;
+static const uint8_t P9N2_PU_TX_ERROR_REG_C3_PSIRFACC_TDL_CMD_CTRL_PCK = 22 ;
+static const uint8_t P9N2_PU_TX_ERROR_REG_C3_PSIRFACC_TDL_RSP_CTRL_PCK = 23 ;
+static const uint8_t P9N2_PU_TX_ERROR_REG_C3_PSIRFACC_TFSM_PCK = 24 ;
+static const uint8_t P9N2_PU_TX_ERROR_REG_C3_PSIRFACC_TDL_FSM_PCK = 25 ;
+static const uint8_t P9N2_PU_TX_ERROR_REG_C4_PSIRFACC_TXSC_PCK = 26 ;
+static const uint8_t P9N2_PU_TX_ERROR_REG_C3_PSIRFACC_TDL_RETRY_ERR = 27 ;
+
+static const uint8_t P9N2_PU_TX_ERR_MODE_TX_ERR_MODE_0 = 0 ;
+static const uint8_t P9N2_PU_TX_ERR_MODE_TX_ERR_MODE_1 = 1 ;
+
+static const uint8_t P9N2_PU_TX_MASK_REG_PSITXINS_DATA_PCK = 0 ;
+static const uint8_t P9N2_PU_TX_MASK_REG_PSITXINS_TZRTMP_PCK = 1 ;
+static const uint8_t P9N2_PU_TX_MASK_REG_PSITXEI_SHIFT_PCK = 2 ;
+static const uint8_t P9N2_PU_TX_MASK_REG_PSITXEI_TRANSMIT_PCK = 3 ;
+static const uint8_t P9N2_PU_TX_MASK_REG_PSITXINS_PARITY = 4 ;
+static const uint8_t P9N2_PU_TX_MASK_REG_PSITXINS_UNDERRUN = 5 ;
+static const uint8_t P9N2_PU_TX_MASK_REG_PSITXBFF_DATA_PCK = 6 ;
+static const uint8_t P9N2_PU_TX_MASK_REG_PSITXBFF_TDO_PCK = 7 ;
+static const uint8_t P9N2_PU_TX_MASK_REG_PSITXBFF_TFC_PCK = 8 ;
+static const uint8_t P9N2_PU_TX_MASK_REG_PSITXLC_FSM_PCK = 9 ;
+static const uint8_t P9N2_PU_TX_MASK_REG_PSITXLC_DATA_BUFF_PCK = 10 ;
+static const uint8_t P9N2_PU_TX_MASK_REG_PSITXLC_TDO_PCK = 11 ;
+static const uint8_t P9N2_PU_TX_MASK_REG_PSITXLC_TADDR_PCK = 12 ;
+static const uint8_t P9N2_PU_TX_MASK_REG_PSITXLC_TCTRL_PCK = 13 ;
+static const uint8_t P9N2_PU_TX_MASK_REG_PSITXLC_UE_RF = 14 ;
+static const uint8_t P9N2_PU_TX_MASK_REG_PSITXLC_CE_RF = 15 ;
+static const uint8_t P9N2_PU_TX_MASK_REG_PSITXLC_UE_GX_2N = 16 ;
+static const uint8_t P9N2_PU_TX_MASK_REG_PSITXLC_CE_GX_2N = 17 ;
+static const uint8_t P9N2_PU_TX_MASK_REG_PSITXLC_DATA_GXST2_PCK_2N = 18 ;
+static const uint8_t P9N2_PU_TX_MASK_REG_PSITXLC_DATA_GXST3_PCK_2N = 19 ;
+static const uint8_t P9N2_PU_TX_MASK_REG_PSIRFACC_TADDR_PCK = 20 ;
+static const uint8_t P9N2_PU_TX_MASK_REG_PSIRFACC_TCTRL_PCK = 21 ;
+static const uint8_t P9N2_PU_TX_MASK_REG_PSIRFACC_TDL_CMD_CTRL_PCK = 22 ;
+static const uint8_t P9N2_PU_TX_MASK_REG_PSIRFACC_TDL_RSP_CTRL_PCK = 23 ;
+static const uint8_t P9N2_PU_TX_MASK_REG_PSIRFACC_TFSM_PCK = 24 ;
+static const uint8_t P9N2_PU_TX_MASK_REG_PSIRFACC_TDL_FSM_PCK = 25 ;
+static const uint8_t P9N2_PU_TX_MASK_REG_PSIRFACC_TXSC_PCK = 26 ;
+static const uint8_t P9N2_PU_TX_MASK_REG_PSIRFACC_TDL_RETRY_ERR = 27 ;
+
+static const uint8_t P9N2_PU_TX_PSI_CNTL_TX_PSI_IORESET_WO_PULSE_SLOW_SIGNAL = 0 ;
+static const uint8_t P9N2_PU_TX_PSI_CNTL_DRV_PATTERN_EN = 1 ;
+static const uint8_t P9N2_PU_TX_PSI_CNTL_PATTERN_SEL = 2 ;
+static const uint8_t P9N2_PU_TX_PSI_CNTL_PATTERN_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_TX_PSI_CNTL_CLK_QUIESCE_P = 4 ;
+static const uint8_t P9N2_PU_TX_PSI_CNTL_CLK_QUIESCE_P_LEN = 2 ;
+static const uint8_t P9N2_PU_TX_PSI_CNTL_CLK_QUIESCE_N = 6 ;
+static const uint8_t P9N2_PU_TX_PSI_CNTL_CLK_QUIESCE_N_LEN = 2 ;
+static const uint8_t P9N2_PU_TX_PSI_CNTL_LANE_QUIESCE = 8 ;
+static const uint8_t P9N2_PU_TX_PSI_CNTL_LANE_QUIESCE_LEN = 2 ;
+static const uint8_t P9N2_PU_TX_PSI_CNTL_CLK_INVERT = 10 ;
+static const uint8_t P9N2_PU_TX_PSI_CNTL_LANE_INVERT = 11 ;
+static const uint8_t P9N2_PU_TX_PSI_CNTL_PDWN = 12 ;
+static const uint8_t P9N2_PU_TX_PSI_CNTL_BIST_EN = 13 ;
+static const uint8_t P9N2_PU_TX_PSI_CNTL_SPARE = 24 ;
+static const uint8_t P9N2_PU_TX_PSI_CNTL_SPARE_LEN = 8 ;
+
+static const uint8_t P9N2_PU_TX_PSI_MODE_PC_TEST = 0 ;
+static const uint8_t P9N2_PU_TX_PSI_MODE_MAIN_SLICE_EN_ENC = 4 ;
+static const uint8_t P9N2_PU_TX_PSI_MODE_MAIN_SLICE_EN_ENC_LEN = 4 ;
+static const uint8_t P9N2_PU_TX_PSI_MODE_PC_SLICE_EN_ENC = 12 ;
+static const uint8_t P9N2_PU_TX_PSI_MODE_PC_SLICE_EN_ENC_LEN = 4 ;
+static const uint8_t P9N2_PU_TX_PSI_MODE_SLEWCTL = 16 ;
+static const uint8_t P9N2_PU_TX_PSI_MODE_SLEWCTL_LEN = 4 ;
+static const uint8_t P9N2_PU_TX_PSI_MODE_PVTNL_ENC = 24 ;
+static const uint8_t P9N2_PU_TX_PSI_MODE_PVTNL_ENC_LEN = 2 ;
+static const uint8_t P9N2_PU_TX_PSI_MODE_PVTPL_ENC = 28 ;
+static const uint8_t P9N2_PU_TX_PSI_MODE_PVTPL_ENC_LEN = 2 ;
+
+static const uint8_t P9N2_PU_TX_PSI_STATUS_SPARE = 0 ;
+static const uint8_t P9N2_PU_TX_PSI_STATUS_SPARE_LEN = 4 ;
+static const uint8_t P9N2_PU_TX_PSI_STATUS_BIST_ERROR = 4 ;
+static const uint8_t P9N2_PU_TX_PSI_STATUS_BIST_ERROR_LEN = 3 ;
+static const uint8_t P9N2_PU_TX_PSI_STATUS_TX_PSI_BIST_DONE_RO_SIGNAL = 7 ;
+static const uint8_t P9N2_PU_TX_PSI_STATUS_TX_PSI_BIST_DONE_RO_SIGNAL_LEN = 3 ;
+
+static const uint8_t P9N2_PU_TX_TO_RT_REG_TIMEOUT_VALUE = 0 ;
+static const uint8_t P9N2_PU_TX_TO_RT_REG_TIMEOUT_VALUE_LEN = 4 ;
+static const uint8_t P9N2_PU_TX_TO_RT_REG_RETRY_VALUE = 4 ;
+static const uint8_t P9N2_PU_TX_TO_RT_REG_RETRY_VALUE_LEN = 4 ;
+
+static const uint8_t P9N2_PU_UMAC_STATUS_CONTROL_CRB_READS_ENBL = 1 ;
+static const uint8_t P9N2_PU_UMAC_STATUS_CONTROL_CRB_READS_HALTED = 2 ;
+static const uint8_t P9N2_PU_UMAC_STATUS_CONTROL_IDLE = 3 ;
+static const uint8_t P9N2_PU_UMAC_STATUS_CONTROL_QUIESCE_REQUEST = 4 ;
+static const uint8_t P9N2_PU_UMAC_STATUS_CONTROL_QUIESCE_ACHEIVED = 5 ;
+static const uint8_t P9N2_PU_UMAC_STATUS_CONTROL_QUIESCE_FAILED = 6 ;
+static const uint8_t P9N2_PU_UMAC_STATUS_CONTROL_QUIESCED = 7 ;
+static const uint8_t P9N2_PU_UMAC_STATUS_CONTROL_PASTE_ADDR_ALIGN = 8 ;
+
+static const uint8_t P9N2_PU_VAS_BUFCTL_TOTAL_FREE_BUF_COUNT = 49 ;
+static const uint8_t P9N2_PU_VAS_BUFCTL_TOTAL_FREE_BUF_COUNT_LEN = 7 ;
+static const uint8_t P9N2_PU_VAS_BUFCTL_CONSUMED_BUF_COUNT = 57 ;
+static const uint8_t P9N2_PU_VAS_BUFCTL_CONSUMED_BUF_COUNT_LEN = 7 ;
+
+static const uint8_t P9N2_PU_VAS_CAMDATA0_CAM_DISPLAY_REG_0 = 0 ;
+static const uint8_t P9N2_PU_VAS_CAMDATA0_CAM_DISPLAY_REG_0_LEN = 64 ;
+
+static const uint8_t P9N2_PU_VAS_CAMDATA1_CAM_DISPLAY_REG_1 = 0 ;
+static const uint8_t P9N2_PU_VAS_CAMDATA1_CAM_DISPLAY_REG_1_LEN = 64 ;
+
+static const uint8_t P9N2_PU_VAS_CQERRRPT_CQ_CERR_RESET = 0 ;
+static const uint8_t P9N2_PU_VAS_CQERRRPT_CQ_CERR_BIT4 = 4 ;
+static const uint8_t P9N2_PU_VAS_CQERRRPT_CQ_CERR_BIT5 = 5 ;
+static const uint8_t P9N2_PU_VAS_CQERRRPT_CQ_CERR_BIT6 = 6 ;
+static const uint8_t P9N2_PU_VAS_CQERRRPT_CQ_CERR_BIT7 = 7 ;
+static const uint8_t P9N2_PU_VAS_CQERRRPT_CQ_CERR_BIT8 = 8 ;
+static const uint8_t P9N2_PU_VAS_CQERRRPT_CQ_CERR_BIT9 = 9 ;
+static const uint8_t P9N2_PU_VAS_CQERRRPT_CQ_CERR_BIT10 = 10 ;
+static const uint8_t P9N2_PU_VAS_CQERRRPT_CQ_CERR_BIT11 = 11 ;
+static const uint8_t P9N2_PU_VAS_CQERRRPT_CQ_CERR_BIT12 = 12 ;
+static const uint8_t P9N2_PU_VAS_CQERRRPT_CQ_CERR_BIT13 = 13 ;
+static const uint8_t P9N2_PU_VAS_CQERRRPT_CQ_CERR_BIT14 = 14 ;
+static const uint8_t P9N2_PU_VAS_CQERRRPT_CQ_CERR_BIT15 = 15 ;
+static const uint8_t P9N2_PU_VAS_CQERRRPT_CQ_CERR_BIT16 = 16 ;
+static const uint8_t P9N2_PU_VAS_CQERRRPT_CQ_CERR_BIT17 = 17 ;
+static const uint8_t P9N2_PU_VAS_CQERRRPT_CQ_CERR_BIT18 = 18 ;
+static const uint8_t P9N2_PU_VAS_CQERRRPT_CQ_CERR_BIT19 = 19 ;
+static const uint8_t P9N2_PU_VAS_CQERRRPT_CQ_CERR_BIT20 = 20 ;
+static const uint8_t P9N2_PU_VAS_CQERRRPT_CQ_CERR_BIT21 = 21 ;
+static const uint8_t P9N2_PU_VAS_CQERRRPT_CQ_CERR_BIT22 = 22 ;
+static const uint8_t P9N2_PU_VAS_CQERRRPT_CQ_CERR_BIT23 = 23 ;
+static const uint8_t P9N2_PU_VAS_CQERRRPT_CQ_CERR_BIT24 = 24 ;
+static const uint8_t P9N2_PU_VAS_CQERRRPT_CQ_CERR_BIT25 = 25 ;
+static const uint8_t P9N2_PU_VAS_CQERRRPT_CQ_CERR_BIT26 = 26 ;
+static const uint8_t P9N2_PU_VAS_CQERRRPT_CQ_CERR_BIT27 = 27 ;
+static const uint8_t P9N2_PU_VAS_CQERRRPT_CQ_CERR_BIT28 = 28 ;
+static const uint8_t P9N2_PU_VAS_CQERRRPT_CQ_CERR_BIT29 = 29 ;
+static const uint8_t P9N2_PU_VAS_CQERRRPT_CQ_CERR_BIT30 = 30 ;
+static const uint8_t P9N2_PU_VAS_CQERRRPT_CQ_CERR_BIT31 = 31 ;
+static const uint8_t P9N2_PU_VAS_CQERRRPT_CQ_CERR_BIT32 = 32 ;
+static const uint8_t P9N2_PU_VAS_CQERRRPT_CQ_CERR_BIT33 = 33 ;
+static const uint8_t P9N2_PU_VAS_CQERRRPT_CQ_CERR_BIT34 = 34 ;
+static const uint8_t P9N2_PU_VAS_CQERRRPT_CQ_CERR_BIT35 = 35 ;
+static const uint8_t P9N2_PU_VAS_CQERRRPT_CQ_CERR_BIT36 = 36 ;
+static const uint8_t P9N2_PU_VAS_CQERRRPT_CQ_CERR_BIT37 = 37 ;
+static const uint8_t P9N2_PU_VAS_CQERRRPT_CQ_CERR_BIT38 = 38 ;
+static const uint8_t P9N2_PU_VAS_CQERRRPT_CQ_CERR_BIT39 = 39 ;
+
+static const uint8_t P9N2_PU_VAS_DBGCONT_TRACE_BUS_BITS_0_63 = 0 ;
+static const uint8_t P9N2_PU_VAS_DBGCONT_TRACE_BUS_BITS_0_63_LEN = 64 ;
+
+static const uint8_t P9N2_PU_VAS_DBGNORTH_SEL_RG_TRACE_DATA_LO = 0 ;
+static const uint8_t P9N2_PU_VAS_DBGNORTH_SEL_RG_TRACE_DATA_LO_LEN = 2 ;
+static const uint8_t P9N2_PU_VAS_DBGNORTH_SEL_RG_TRACE_DATA_HI = 2 ;
+static const uint8_t P9N2_PU_VAS_DBGNORTH_SEL_RG_TRACE_DATA_HI_LEN = 2 ;
+static const uint8_t P9N2_PU_VAS_DBGNORTH_SEL_RG_TRIGGERS_01 = 4 ;
+static const uint8_t P9N2_PU_VAS_DBGNORTH_SEL_RG_TRIGGERS_01_LEN = 2 ;
+static const uint8_t P9N2_PU_VAS_DBGNORTH_SEL_RG_TRIGGERS_23 = 6 ;
+static const uint8_t P9N2_PU_VAS_DBGNORTH_SEL_RG_TRIGGERS_23_LEN = 2 ;
+static const uint8_t P9N2_PU_VAS_DBGNORTH_IN_TRACE_GROUP_SEL_LO = 8 ;
+static const uint8_t P9N2_PU_VAS_DBGNORTH_IN_TRACE_GROUP_SEL_LO_LEN = 3 ;
+static const uint8_t P9N2_PU_VAS_DBGNORTH_IN_TRACE_GROUP_SEL_HI = 11 ;
+static const uint8_t P9N2_PU_VAS_DBGNORTH_IN_TRACE_GROUP_SEL_HI_LEN = 3 ;
+static const uint8_t P9N2_PU_VAS_DBGNORTH_IN_TRACE_TRIGGER_SEL_01 = 14 ;
+static const uint8_t P9N2_PU_VAS_DBGNORTH_IN_TRACE_TRIGGER_SEL_01_LEN = 3 ;
+static const uint8_t P9N2_PU_VAS_DBGNORTH_IN_TRACE_TRIGGER_SEL_23 = 17 ;
+static const uint8_t P9N2_PU_VAS_DBGNORTH_IN_TRACE_TRIGGER_SEL_23_LEN = 3 ;
+static const uint8_t P9N2_PU_VAS_DBGNORTH_RG_TRACE_GROUP_SEL_LO = 20 ;
+static const uint8_t P9N2_PU_VAS_DBGNORTH_RG_TRACE_GROUP_SEL_LO_LEN = 3 ;
+static const uint8_t P9N2_PU_VAS_DBGNORTH_RG_TRACE_GROUP_SEL_HI = 23 ;
+static const uint8_t P9N2_PU_VAS_DBGNORTH_RG_TRACE_GROUP_SEL_HI_LEN = 3 ;
+static const uint8_t P9N2_PU_VAS_DBGNORTH_RG_TRACE_TRIGGER_SEL_01 = 26 ;
+static const uint8_t P9N2_PU_VAS_DBGNORTH_RG_TRACE_TRIGGER_SEL_01_LEN = 3 ;
+static const uint8_t P9N2_PU_VAS_DBGNORTH_RG_TRACE_TRIGGER_SEL_23 = 29 ;
+static const uint8_t P9N2_PU_VAS_DBGNORTH_RG_TRACE_TRIGGER_SEL_23_LEN = 3 ;
+static const uint8_t P9N2_PU_VAS_DBGNORTH_ENABLE_IN_TRACE = 32 ;
+static const uint8_t P9N2_PU_VAS_DBGNORTH_ENABLE_RG_TRACE = 33 ;
+static const uint8_t P9N2_PU_VAS_DBGNORTH_DBG_NORTH_UNUSED_BITS0 = 34 ;
+static const uint8_t P9N2_PU_VAS_DBGNORTH_DBG_NORTH_UNUSED_BITS0_LEN = 2 ;
+static const uint8_t P9N2_PU_VAS_DBGNORTH_SEL_RG_PMU_DATA = 36 ;
+static const uint8_t P9N2_PU_VAS_DBGNORTH_DBG_NORTH_UNUSED_BITS1 = 37 ;
+static const uint8_t P9N2_PU_VAS_DBGNORTH_DBG_NORTH_UNUSED_BITS1_LEN = 3 ;
+static const uint8_t P9N2_PU_VAS_DBGNORTH_ENABLE_IN_PMU_COUNTING = 40 ;
+static const uint8_t P9N2_PU_VAS_DBGNORTH_ENABLE_RG_PMU_COUNTING = 41 ;
+static const uint8_t P9N2_PU_VAS_DBGNORTH_IN_TRACE_INT_DATA_LO = 42 ;
+static const uint8_t P9N2_PU_VAS_DBGNORTH_IN_TRACE_INT_DATA_HI = 43 ;
+static const uint8_t P9N2_PU_VAS_DBGNORTH_EG_TRACE_INT_DATA_LO = 44 ;
+static const uint8_t P9N2_PU_VAS_DBGNORTH_EG_TRACE_INT_DATA_HI = 45 ;
+static const uint8_t P9N2_PU_VAS_DBGNORTH_RG_TRACE_INT_DATA_LO = 46 ;
+static const uint8_t P9N2_PU_VAS_DBGNORTH_RG_TRACE_INT_DATA_HI = 47 ;
+static const uint8_t P9N2_PU_VAS_DBGNORTH_IN_TRACE_INT_TRIG_01 = 48 ;
+static const uint8_t P9N2_PU_VAS_DBGNORTH_IN_TRACE_INT_TRIG_23 = 49 ;
+static const uint8_t P9N2_PU_VAS_DBGNORTH_EG_TRACE_INT_TRIG_01 = 50 ;
+static const uint8_t P9N2_PU_VAS_DBGNORTH_EG_TRACE_INT_TRIG_23 = 51 ;
+static const uint8_t P9N2_PU_VAS_DBGNORTH_RG_TRACE_INT_TRIG_01 = 52 ;
+static const uint8_t P9N2_PU_VAS_DBGNORTH_RG_TRACE_INT_TRIG_23 = 53 ;
+
+static const uint8_t P9N2_PU_VAS_DBGSOUTH_PASS_WC_INT_TRACE_DATA_LO = 0 ;
+static const uint8_t P9N2_PU_VAS_DBGSOUTH_PASS_WC_INT_TRACE_DATA_HI = 1 ;
+static const uint8_t P9N2_PU_VAS_DBGSOUTH_PASS_CQ_INT_TRACE_DATA_LO = 2 ;
+static const uint8_t P9N2_PU_VAS_DBGSOUTH_PASS_CQ_INT_TRACE_DATA_HI = 3 ;
+static const uint8_t P9N2_PU_VAS_DBGSOUTH_PASS_WC_INT_TRACE_TRIG_01 = 4 ;
+static const uint8_t P9N2_PU_VAS_DBGSOUTH_PASS_WC_INT_TRACE_TRIG_23 = 5 ;
+static const uint8_t P9N2_PU_VAS_DBGSOUTH_PASS_CQ_INT_TRACE_TRIG_01 = 6 ;
+static const uint8_t P9N2_PU_VAS_DBGSOUTH_PASS_CQ_INT_TRACE_TRIG_23 = 7 ;
+static const uint8_t P9N2_PU_VAS_DBGSOUTH_EG_TRACE_GROUP_SEL_LO = 8 ;
+static const uint8_t P9N2_PU_VAS_DBGSOUTH_EG_TRACE_GROUP_SEL_LO_LEN = 4 ;
+static const uint8_t P9N2_PU_VAS_DBGSOUTH_EG_TRACE_GROUP_SEL_HI = 12 ;
+static const uint8_t P9N2_PU_VAS_DBGSOUTH_EG_TRACE_GROUP_SEL_HI_LEN = 4 ;
+static const uint8_t P9N2_PU_VAS_DBGSOUTH_EG_TRACE_TRIGGER_SEL_01 = 16 ;
+static const uint8_t P9N2_PU_VAS_DBGSOUTH_EG_TRACE_TRIGGER_SEL_01_LEN = 2 ;
+static const uint8_t P9N2_PU_VAS_DBGSOUTH_EG_TRACE_TRIGGER_SEL_23 = 18 ;
+static const uint8_t P9N2_PU_VAS_DBGSOUTH_EG_TRACE_TRIGGER_SEL_23_LEN = 2 ;
+static const uint8_t P9N2_PU_VAS_DBGSOUTH_WC_TRACE_GROUP_SEL_LO = 20 ;
+static const uint8_t P9N2_PU_VAS_DBGSOUTH_WC_TRACE_GROUP_SEL_LO_LEN = 3 ;
+static const uint8_t P9N2_PU_VAS_DBGSOUTH_WC_TRACE_GROUP_SEL_HI = 23 ;
+static const uint8_t P9N2_PU_VAS_DBGSOUTH_WC_TRACE_GROUP_SEL_HI_LEN = 3 ;
+static const uint8_t P9N2_PU_VAS_DBGSOUTH_WC_TRACE_TRIGGER_SEL_01 = 26 ;
+static const uint8_t P9N2_PU_VAS_DBGSOUTH_WC_TRACE_TRIGGER_SEL_01_LEN = 3 ;
+static const uint8_t P9N2_PU_VAS_DBGSOUTH_WC_TRACE_TRIGGER_SEL_23 = 29 ;
+static const uint8_t P9N2_PU_VAS_DBGSOUTH_WC_TRACE_TRIGGER_SEL_23_LEN = 3 ;
+static const uint8_t P9N2_PU_VAS_DBGSOUTH_CQ_TRACE_GROUP_SEL_LO = 32 ;
+static const uint8_t P9N2_PU_VAS_DBGSOUTH_CQ_TRACE_GROUP_SEL_LO_LEN = 3 ;
+static const uint8_t P9N2_PU_VAS_DBGSOUTH_CQ_TRACE_GROUP_SEL_HI = 35 ;
+static const uint8_t P9N2_PU_VAS_DBGSOUTH_CQ_TRACE_GROUP_SEL_HI_LEN = 3 ;
+static const uint8_t P9N2_PU_VAS_DBGSOUTH_CQ_TRACE_TRIGGER_SEL_01 = 38 ;
+static const uint8_t P9N2_PU_VAS_DBGSOUTH_CQ_TRACE_TRIGGER_SEL_01_LEN = 3 ;
+static const uint8_t P9N2_PU_VAS_DBGSOUTH_CQ_TRACE_TRIGGER_SEL_23 = 41 ;
+static const uint8_t P9N2_PU_VAS_DBGSOUTH_CQ_TRACE_TRIGGER_SEL_23_LEN = 3 ;
+static const uint8_t P9N2_PU_VAS_DBGSOUTH_ENABLE_EG_TRACE = 44 ;
+static const uint8_t P9N2_PU_VAS_DBGSOUTH_ENABLE_WC_TRACE = 45 ;
+static const uint8_t P9N2_PU_VAS_DBGSOUTH_ENABLE_CQ_TRACE = 46 ;
+static const uint8_t P9N2_PU_VAS_DBGSOUTH_WC_TRACE_INT_DATA_LO = 47 ;
+static const uint8_t P9N2_PU_VAS_DBGSOUTH_WC_TRACE_INT_DATA_HI = 48 ;
+static const uint8_t P9N2_PU_VAS_DBGSOUTH_EG_TRACE_INT_DATA_LO = 49 ;
+static const uint8_t P9N2_PU_VAS_DBGSOUTH_PASS_CQ_INT_PMU_DATA_LO = 50 ;
+static const uint8_t P9N2_PU_VAS_DBGSOUTH_PASS_CQ_INT_PMU_DATA_HI = 51 ;
+static const uint8_t P9N2_PU_VAS_DBGSOUTH_ENABLE_EG_PMU_COUNTING = 52 ;
+static const uint8_t P9N2_PU_VAS_DBGSOUTH_EG_TRACE_INT_DATA_HI = 53 ;
+static const uint8_t P9N2_PU_VAS_DBGSOUTH_ENABLE_CQ_PMU_COUNTING = 54 ;
+static const uint8_t P9N2_PU_VAS_DBGSOUTH_CQ_TRACE_INT_DATA_LO = 55 ;
+static const uint8_t P9N2_PU_VAS_DBGSOUTH_CQ_TRACE_INT_DATA_HI = 56 ;
+static const uint8_t P9N2_PU_VAS_DBGSOUTH_WC_TRACE_INT_TRIG_01 = 57 ;
+static const uint8_t P9N2_PU_VAS_DBGSOUTH_WC_TRACE_INT_TRIG_23 = 58 ;
+static const uint8_t P9N2_PU_VAS_DBGSOUTH_EG_TRACE_INT_TRIG_01 = 59 ;
+static const uint8_t P9N2_PU_VAS_DBGSOUTH_EG_TRACE_INT_TRIG_23 = 60 ;
+static const uint8_t P9N2_PU_VAS_DBGSOUTH_CQ_TRACE_INT_TRIG_01 = 61 ;
+static const uint8_t P9N2_PU_VAS_DBGSOUTH_CQ_TRACE_INT_TRIG_23 = 62 ;
+
+static const uint8_t P9N2_PU_VAS_DBGTRIG_TRACE_BUS_BITS_64_87 = 0 ;
+static const uint8_t P9N2_PU_VAS_DBGTRIG_TRACE_BUS_BITS_64_87_LEN = 24 ;
+static const uint8_t P9N2_PU_VAS_DBGTRIG_TRACE_BUS_TRIGGER_BITS = 24 ;
+static const uint8_t P9N2_PU_VAS_DBGTRIG_TRACE_BUS_TRIGGER_BITS_LEN = 4 ;
+
+static const uint8_t P9N2_PU_VAS_EGERRRPT_EG_CERR_RESET = 0 ;
+static const uint8_t P9N2_PU_VAS_EGERRRPT_EG_CERR_BIT4 = 4 ;
+static const uint8_t P9N2_PU_VAS_EGERRRPT_EG_CERR_BIT5 = 5 ;
+static const uint8_t P9N2_PU_VAS_EGERRRPT_EG_CERR_BIT6 = 6 ;
+static const uint8_t P9N2_PU_VAS_EGERRRPT_EG_CERR_BIT7 = 7 ;
+static const uint8_t P9N2_PU_VAS_EGERRRPT_EG_CERR_BIT8 = 8 ;
+static const uint8_t P9N2_PU_VAS_EGERRRPT_EG_CERR_BIT9 = 9 ;
+static const uint8_t P9N2_PU_VAS_EGERRRPT_EG_CERR_BIT10 = 10 ;
+static const uint8_t P9N2_PU_VAS_EGERRRPT_EG_CERR_BIT11 = 11 ;
+static const uint8_t P9N2_PU_VAS_EGERRRPT_EG_CERR_UNUSEDBITS = 12 ;
+static const uint8_t P9N2_PU_VAS_EGERRRPT_EG_CERR_UNUSEDBITS_LEN = 8 ;
+
+static const uint8_t P9N2_PU_VAS_ERRINJNO_ECC_ERR_INJ_NORTH_WC_ENA = 0 ;
+static const uint8_t P9N2_PU_VAS_ERRINJNO_ECC_ERR_INJ_NORTH_WC_TYP = 1 ;
+static const uint8_t P9N2_PU_VAS_ERRINJNO_ECC_ERR_INJ_NORTH_WC_FRQ = 2 ;
+static const uint8_t P9N2_PU_VAS_ERRINJNO_ECC_ERR_INJ_NORTH_WC_UNUSED = 3 ;
+static const uint8_t P9N2_PU_VAS_ERRINJNO_ECC_ERR_INJ_NORTH_WC_UNUSED_LEN = 5 ;
+
+static const uint8_t P9N2_PU_VAS_ERRINJSO_ECC_ERR_INJ_SOUTH_WC_ENA = 0 ;
+static const uint8_t P9N2_PU_VAS_ERRINJSO_ECC_ERR_INJ_SOUTH_WC_TYP = 1 ;
+static const uint8_t P9N2_PU_VAS_ERRINJSO_ECC_ERR_INJ_SOUTH_WC_FRQ = 2 ;
+static const uint8_t P9N2_PU_VAS_ERRINJSO_ECC_ERR_INJ_SOUTH_WC_SEL = 3 ;
+static const uint8_t P9N2_PU_VAS_ERRINJSO_ECC_ERR_INJ_SOUTH_WC_SEL_LEN = 2 ;
+static const uint8_t P9N2_PU_VAS_ERRINJSO_ECC_ERR_INJ_SOUTH_EG_ENA = 5 ;
+static const uint8_t P9N2_PU_VAS_ERRINJSO_ECC_ERR_INJ_SOUTH_EG_TYP = 6 ;
+static const uint8_t P9N2_PU_VAS_ERRINJSO_ECC_ERR_INJ_SOUTH_EG_FRQ = 7 ;
+static const uint8_t P9N2_PU_VAS_ERRINJSO_ECC_ERR_INJ_SOUTH_EG_SEL = 8 ;
+static const uint8_t P9N2_PU_VAS_ERRINJSO_ECC_ERR_INJ_SOUTH_UNUSED = 9 ;
+static const uint8_t P9N2_PU_VAS_ERRINJSO_ECC_ERR_INJ_SOUTH_UNUSED_LEN = 3 ;
+
+static const uint8_t P9N2_PU_VAS_FIR_ACTION0_REG_ACTION0 = 0 ;
+static const uint8_t P9N2_PU_VAS_FIR_ACTION0_REG_ACTION0_LEN = 54 ;
+
+static const uint8_t P9N2_PU_VAS_FIR_ACTION1_REG_ACTION1 = 0 ;
+static const uint8_t P9N2_PU_VAS_FIR_ACTION1_REG_ACTION1_LEN = 54 ;
+
+static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_EG_LOGIC_HW_ERROR = 0 ;
+static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_IN_LOGIC_HW_ERROR = 1 ;
+static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_CQ_LOGIC_HW_ERROR = 2 ;
+static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_WC_LOGIC_HW_ERROR = 3 ;
+static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_RG_LOGIC_HW_ERROR = 4 ;
+static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_CQ_PB_PARITY_ERROR = 5 ;
+static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_CQ_PB_RD_ADDR_ERROR = 6 ;
+static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_CQ_PB_WR_ADDR_ERROR = 7 ;
+static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_EG_ECC_CE_ERROR = 8 ;
+static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_IN_ECC_CE_ERROR = 9 ;
+static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_CQ_ECC_CE_ERROR = 10 ;
+static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_WC_ECC_CE_ERROR = 11 ;
+static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_RG_ECC_CE_ERROR = 12 ;
+static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_CQ_PB_OB_CE_ERROR = 13 ;
+static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_CQ_PB_OB_UE_ERROR = 14 ;
+static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_CQ_PB_MASTER_FSM_HANG = 15 ;
+static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_EG_ECC_UE_ERROR = 16 ;
+static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_IN_ECC_UE_ERROR = 17 ;
+static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_CQ_ECC_UE_ERROR = 18 ;
+static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_WC_ECC_UE_ERROR = 19 ;
+static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_RG_ECC_UE_ERROR = 20 ;
+static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_IN_PARITY_ERROR = 21 ;
+static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_IN_SW_CAST_ERROR = 22 ;
+static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_CQ_SMF_ACCESS_ERROR = 23 ;
+static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_EG_ECC_SUE_ERROR = 24 ;
+static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_IN_ECC_SUE_ERROR = 25 ;
+static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_CQ_ECC_SUE_ERROR = 26 ;
+static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_WC_ECC_SUE_ERROR = 27 ;
+static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_RG_ECC_SUE_ERROR = 28 ;
+static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_CQ_PB_RD_LINK_ERROR = 29 ;
+static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_CQ_PB_WR_LINK_ERROR = 30 ;
+static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_CQ_PB_LINK_ABORT = 31 ;
+static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_MMIO_HYP_RD_ADDR_ERR = 32 ;
+static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_MMIO_OS_RD_ADDR_ERR = 33 ;
+static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_MMIO_HYP_WR_ADDR_ERR = 34 ;
+static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_MMIO_OS_WR_ADDR_ERR = 35 ;
+static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_MMIO_NON8B_HYP_ERR = 36 ;
+static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_MMIO_NON8B_OS_ERR = 37 ;
+static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_WM_WIN_NOT_OPEN_ERR = 38 ;
+static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_WM_MULTIHIT_ERR = 39 ;
+static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_PG_MIG_DISABLED_ERR = 40 ;
+static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_PG_MIG_SIZE_MISMATCH_ERR = 41 ;
+static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_NOTIFY_FAILED_ERR = 42 ;
+static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_WR_MON_NOT_DISABLED_ERR = 43 ;
+static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_REJECTED_PASTE_CMD = 44 ;
+static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_DATA_HANG_DETECTED = 45 ;
+static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_INCOMING_PB_PARITY_ERR = 46 ;
+static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_SCOM1_SAT_ERR = 47 ;
+static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_NX_LOCAL_XSTOP = 48 ;
+static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_SCOM_MMIO_ADDR_ERR = 49 ;
+static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_UNUSED50 = 50 ;
+static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_UNUSED51 = 51 ;
+static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_SCOMFIR_INT_ERR_0 = 52 ;
+static const uint8_t P9N2_PU_VAS_FIR_MASK_REG_SCOMFIR_INT_ERR_1 = 53 ;
+
+static const uint8_t P9N2_PU_VAS_FIR_REG_EG_LOGIC_HW_ERROR = 0 ;
+static const uint8_t P9N2_PU_VAS_FIR_REG_IN_LOGIC_HW_ERROR = 1 ;
+static const uint8_t P9N2_PU_VAS_FIR_REG_CQ_LOGIC_HW_ERROR = 2 ;
+static const uint8_t P9N2_PU_VAS_FIR_REG_WC_LOGIC_HW_ERROR = 3 ;
+static const uint8_t P9N2_PU_VAS_FIR_REG_RG_LOGIC_HW_ERROR = 4 ;
+static const uint8_t P9N2_PU_VAS_FIR_REG_CQ_PB_PARITY_ERROR = 5 ;
+static const uint8_t P9N2_PU_VAS_FIR_REG_CQ_PB_RD_ADDR_ERROR = 6 ;
+static const uint8_t P9N2_PU_VAS_FIR_REG_CQ_PB_WR_ADDR_ERROR = 7 ;
+static const uint8_t P9N2_PU_VAS_FIR_REG_EG_ECC_CE_ERROR = 8 ;
+static const uint8_t P9N2_PU_VAS_FIR_REG_IN_ECC_CE_ERROR = 9 ;
+static const uint8_t P9N2_PU_VAS_FIR_REG_CQ_ECC_CE_ERROR = 10 ;
+static const uint8_t P9N2_PU_VAS_FIR_REG_WC_ECC_CE_ERROR = 11 ;
+static const uint8_t P9N2_PU_VAS_FIR_REG_RG_ECC_CE_ERROR = 12 ;
+static const uint8_t P9N2_PU_VAS_FIR_REG_CQ_PB_OB_CE_ERROR = 13 ;
+static const uint8_t P9N2_PU_VAS_FIR_REG_CQ_PB_OB_UE_ERROR = 14 ;
+static const uint8_t P9N2_PU_VAS_FIR_REG_CQ_PB_MASTER_FSM_HANG = 15 ;
+static const uint8_t P9N2_PU_VAS_FIR_REG_EG_ECC_UE_ERROR = 16 ;
+static const uint8_t P9N2_PU_VAS_FIR_REG_IN_ECC_UE_ERROR = 17 ;
+static const uint8_t P9N2_PU_VAS_FIR_REG_CQ_ECC_UE_ERROR = 18 ;
+static const uint8_t P9N2_PU_VAS_FIR_REG_WC_ECC_UE_ERROR = 19 ;
+static const uint8_t P9N2_PU_VAS_FIR_REG_RG_ECC_UE_ERROR = 20 ;
+static const uint8_t P9N2_PU_VAS_FIR_REG_IN_PARITY_ERROR = 21 ;
+static const uint8_t P9N2_PU_VAS_FIR_REG_IN_SW_CAST_ERROR = 22 ;
+static const uint8_t P9N2_PU_VAS_FIR_REG_CQ_SMF_ACCESS_ERROR = 23 ;
+static const uint8_t P9N2_PU_VAS_FIR_REG_EG_ECC_SUE_ERROR = 24 ;
+static const uint8_t P9N2_PU_VAS_FIR_REG_IN_ECC_SUE_ERROR = 25 ;
+static const uint8_t P9N2_PU_VAS_FIR_REG_CQ_ECC_SUE_ERROR = 26 ;
+static const uint8_t P9N2_PU_VAS_FIR_REG_WC_ECC_SUE_ERROR = 27 ;
+static const uint8_t P9N2_PU_VAS_FIR_REG_RG_ECC_SUE_ERROR = 28 ;
+static const uint8_t P9N2_PU_VAS_FIR_REG_CQ_PB_RD_LINK_ERROR = 29 ;
+static const uint8_t P9N2_PU_VAS_FIR_REG_CQ_PB_WR_LINK_ERROR = 30 ;
+static const uint8_t P9N2_PU_VAS_FIR_REG_CQ_PB_LINK_ABORT = 31 ;
+static const uint8_t P9N2_PU_VAS_FIR_REG_MMIO_HYP_RD_ADDR_ERR = 32 ;
+static const uint8_t P9N2_PU_VAS_FIR_REG_MMIO_OS_RD_ADDR_ERR = 33 ;
+static const uint8_t P9N2_PU_VAS_FIR_REG_MMIO_HYP_WR_ADDR_ERR = 34 ;
+static const uint8_t P9N2_PU_VAS_FIR_REG_MMIO_OS_WR_ADDR_ERR = 35 ;
+static const uint8_t P9N2_PU_VAS_FIR_REG_MMIO_NON8B_HYP_ERR = 36 ;
+static const uint8_t P9N2_PU_VAS_FIR_REG_MMIO_NON8B_OS_ERR = 37 ;
+static const uint8_t P9N2_PU_VAS_FIR_REG_WM_WIN_NOT_OPEN_ERR = 38 ;
+static const uint8_t P9N2_PU_VAS_FIR_REG_WM_MULTIHIT_ERR = 39 ;
+static const uint8_t P9N2_PU_VAS_FIR_REG_PG_MIG_DISABLED_ERR = 40 ;
+static const uint8_t P9N2_PU_VAS_FIR_REG_PG_MIG_SIZE_MISMATCH_ERR = 41 ;
+static const uint8_t P9N2_PU_VAS_FIR_REG_NOTIFY_FAILED_ERR = 42 ;
+static const uint8_t P9N2_PU_VAS_FIR_REG_WR_MON_NOT_DISABLED_ERR = 43 ;
+static const uint8_t P9N2_PU_VAS_FIR_REG_REJECTED_PASTE_CMD = 44 ;
+static const uint8_t P9N2_PU_VAS_FIR_REG_DATA_HANG_DETECTED = 45 ;
+static const uint8_t P9N2_PU_VAS_FIR_REG_INCOMING_PB_PARITY_ERR = 46 ;
+static const uint8_t P9N2_PU_VAS_FIR_REG_SCOM1_SAT_ERR = 47 ;
+static const uint8_t P9N2_PU_VAS_FIR_REG_NX_LOCAL_XSTOP = 48 ;
+static const uint8_t P9N2_PU_VAS_FIR_REG_SCOM_MMIO_ADDR_ERR = 49 ;
+static const uint8_t P9N2_PU_VAS_FIR_REG_UNUSED50 = 50 ;
+static const uint8_t P9N2_PU_VAS_FIR_REG_UNUSED51 = 51 ;
+static const uint8_t P9N2_PU_VAS_FIR_REG_SCOMFIR_INT_ERR_0 = 52 ;
+static const uint8_t P9N2_PU_VAS_FIR_REG_SCOMFIR_INT_ERR_1 = 53 ;
+
+static const uint8_t P9N2_PU_VAS_FIR_WOF_REG_WOF = 0 ;
+static const uint8_t P9N2_PU_VAS_FIR_WOF_REG_WOF_LEN = 54 ;
+
+static const uint8_t P9N2_PU_VAS_INERRRPT_IN_CERR_RESET = 0 ;
+static const uint8_t P9N2_PU_VAS_INERRRPT_IN_CERR_BIT4 = 4 ;
+static const uint8_t P9N2_PU_VAS_INERRRPT_IN_CERR_BIT5 = 5 ;
+static const uint8_t P9N2_PU_VAS_INERRRPT_IN_CERR_BIT6 = 6 ;
+static const uint8_t P9N2_PU_VAS_INERRRPT_IN_CERR_BIT7 = 7 ;
+static const uint8_t P9N2_PU_VAS_INERRRPT_IN_CERR_BIT8 = 8 ;
+static const uint8_t P9N2_PU_VAS_INERRRPT_IN_CERR_BIT9 = 9 ;
+static const uint8_t P9N2_PU_VAS_INERRRPT_IN_CERR_BIT10 = 10 ;
+static const uint8_t P9N2_PU_VAS_INERRRPT_IN_CERR_BIT11 = 11 ;
+static const uint8_t P9N2_PU_VAS_INERRRPT_IN_CERR_BIT12 = 12 ;
+static const uint8_t P9N2_PU_VAS_INERRRPT_IN_CERR_BIT13 = 13 ;
+static const uint8_t P9N2_PU_VAS_INERRRPT_IN_CERR_BIT14 = 14 ;
+static const uint8_t P9N2_PU_VAS_INERRRPT_IN_CERR_BIT15 = 15 ;
+static const uint8_t P9N2_PU_VAS_INERRRPT_IN_CERR_BIT16 = 16 ;
+static const uint8_t P9N2_PU_VAS_INERRRPT_IN_CERR_BIT17 = 17 ;
+static const uint8_t P9N2_PU_VAS_INERRRPT_IN_CERR_BIT18 = 18 ;
+static const uint8_t P9N2_PU_VAS_INERRRPT_IN_CERR_BIT19 = 19 ;
+static const uint8_t P9N2_PU_VAS_INERRRPT_IN_CERR_BIT20 = 20 ;
+static const uint8_t P9N2_PU_VAS_INERRRPT_IN_CERR_BIT21 = 21 ;
+static const uint8_t P9N2_PU_VAS_INERRRPT_IN_CERR_BIT22 = 22 ;
+static const uint8_t P9N2_PU_VAS_INERRRPT_IN_CERR_BIT23 = 23 ;
+static const uint8_t P9N2_PU_VAS_INERRRPT_IN_CERR_BIT24 = 24 ;
+static const uint8_t P9N2_PU_VAS_INERRRPT_IN_CERR_BIT25 = 25 ;
+static const uint8_t P9N2_PU_VAS_INERRRPT_IN_CERR_BIT26 = 26 ;
+static const uint8_t P9N2_PU_VAS_INERRRPT_IN_CERR_BIT27 = 27 ;
+static const uint8_t P9N2_PU_VAS_INERRRPT_IN_CERR_BIT28 = 28 ;
+static const uint8_t P9N2_PU_VAS_INERRRPT_IN_CERR_BIT29 = 29 ;
+static const uint8_t P9N2_PU_VAS_INERRRPT_IN_CERR_BIT30 = 30 ;
+static const uint8_t P9N2_PU_VAS_INERRRPT_IN_CERR_BIT31 = 31 ;
+
+static const uint8_t P9N2_PU_VAS_MISCCTL_MISC_CTL_4VS64 = 0 ;
+static const uint8_t P9N2_PU_VAS_MISCCTL_MISC_CTL_ACCEPT_PASTE = 1 ;
+static const uint8_t P9N2_PU_VAS_MISCCTL_MISC_CTL_ENABLE_WRMON = 2 ;
+static const uint8_t P9N2_PU_VAS_MISCCTL_MISC_CTL_DISABLE_PUSH2MEM_LIMIT = 3 ;
+static const uint8_t P9N2_PU_VAS_MISCCTL_MISC_CTL_QUIESCE_REQUEST = 4 ;
+static const uint8_t P9N2_PU_VAS_MISCCTL_MISC_CTL_PREFETCH_DISABLE = 5 ;
+static const uint8_t P9N2_PU_VAS_MISCCTL_MISC_CTL_WCMBAR_ENABLE = 6 ;
+static const uint8_t P9N2_PU_VAS_MISCCTL_MISC_CTL_UWCMBAR_ENABLE = 7 ;
+static const uint8_t P9N2_PU_VAS_MISCCTL_MISC_CTL_RMABAR_ENABLE = 8 ;
+static const uint8_t P9N2_PU_VAS_MISCCTL_MISC_CTL_UNUSED_BITS = 9 ;
+static const uint8_t P9N2_PU_VAS_MISCCTL_MISC_CTL_UNUSED_BITS_LEN = 7 ;
+static const uint8_t P9N2_PU_VAS_MISCCTL_MISC_CTL_INVALIDATE_CAM_LOC = 47 ;
+static const uint8_t P9N2_PU_VAS_MISCCTL_MISC_CTL_INVALIDATE_CAM_ALL = 48 ;
+static const uint8_t P9N2_PU_VAS_MISCCTL_MISC_CTL_CAM_LOCATION = 49 ;
+static const uint8_t P9N2_PU_VAS_MISCCTL_MISC_CTL_CAM_LOCATION_LEN = 7 ;
+static const uint8_t P9N2_PU_VAS_MISCCTL_MISC_CTL_CAM_INVAL_DONE = 56 ;
+static const uint8_t P9N2_PU_VAS_MISCCTL_MISC_CTL_UNUSED_BITS2 = 57 ;
+static const uint8_t P9N2_PU_VAS_MISCCTL_MISC_CTL_HMI_ACTIVE = 58 ;
+static const uint8_t P9N2_PU_VAS_MISCCTL_MISC_CTL_RG_IS_IDLE = 59 ;
+
+static const uint8_t P9N2_PU_VAS_MMIOCTL_MMIO_CTL_INIT = 0 ;
+static const uint8_t P9N2_PU_VAS_MMIOCTL_MMIO_CTL_COMP = 1 ;
+static const uint8_t P9N2_PU_VAS_MMIOCTL_MMIO_CTL_OPTYPE = 2 ;
+static const uint8_t P9N2_PU_VAS_MMIOCTL_MMIO_CTL_ACTYPE = 3 ;
+static const uint8_t P9N2_PU_VAS_MMIOCTL_MMIO_CTL_OP_ERR = 4 ;
+static const uint8_t P9N2_PU_VAS_MMIOCTL_MMIO_CTL_UNUSED = 5 ;
+static const uint8_t P9N2_PU_VAS_MMIOCTL_MMIO_CTL_UNUSED_LEN = 3 ;
+static const uint8_t P9N2_PU_VAS_MMIOCTL_MMIO_CTL_OFFSET = 36 ;
+static const uint8_t P9N2_PU_VAS_MMIOCTL_MMIO_CTL_OFFSET_LEN = 12 ;
+static const uint8_t P9N2_PU_VAS_MMIOCTL_MMIO_CTL_WINID = 48 ;
+static const uint8_t P9N2_PU_VAS_MMIOCTL_MMIO_CTL_WINID_LEN = 16 ;
+
+static const uint8_t P9N2_PU_VAS_MMIODATA_MMIO_DATA = 0 ;
+static const uint8_t P9N2_PU_VAS_MMIODATA_MMIO_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_PU_VAS_MMIOECC_MMIO_ECC = 0 ;
+static const uint8_t P9N2_PU_VAS_MMIOECC_MMIO_ECC_LEN = 8 ;
+
+static const uint8_t P9N2_PU_VAS_MMIO_BASE_ADDR_BAR = 8 ;
+static const uint8_t P9N2_PU_VAS_MMIO_BASE_ADDR_BAR_LEN = 31 ;
+
+static const uint8_t P9N2_PU_VAS_PBCFG0_PBCFG_0_ADDR_EXT_MASK = 0 ;
+static const uint8_t P9N2_PU_VAS_PBCFG0_PBCFG_0_ADDR_EXT_MASK_LEN = 7 ;
+static const uint8_t P9N2_PU_VAS_PBCFG0_PBCFG_0_HANG_POLL_MAX_CNT = 7 ;
+static const uint8_t P9N2_PU_VAS_PBCFG0_PBCFG_0_HANG_POLL_MAX_CNT_LEN = 4 ;
+static const uint8_t P9N2_PU_VAS_PBCFG0_PBCFG_0_SMF_CONFIG = 11 ;
+static const uint8_t P9N2_PU_VAS_PBCFG0_PBCFG_0_SMF_CONFIG_LEN = 2 ;
+static const uint8_t P9N2_PU_VAS_PBCFG0_PBCFG_0_UNUSED1 = 13 ;
+static const uint8_t P9N2_PU_VAS_PBCFG0_PBCFG_0_UNUSED1_LEN = 2 ;
+static const uint8_t P9N2_PU_VAS_PBCFG0_PBCFG_0_HANG_NX_MAX_CNT = 15 ;
+static const uint8_t P9N2_PU_VAS_PBCFG0_PBCFG_0_HANG_NX_MAX_CNT_LEN = 4 ;
+static const uint8_t P9N2_PU_VAS_PBCFG0_PBCFG_0_DISABLE_WR_RD_PUSH = 19 ;
+static const uint8_t P9N2_PU_VAS_PBCFG0_PBCFG_0_INJ_CE = 20 ;
+static const uint8_t P9N2_PU_VAS_PBCFG0_PBCFG_0_INJ_UE = 21 ;
+static const uint8_t P9N2_PU_VAS_PBCFG0_PBCFG_0_INJ_SUE = 22 ;
+static const uint8_t P9N2_PU_VAS_PBCFG0_PBCFG_0_INJ_ARRAY_SEL = 23 ;
+static const uint8_t P9N2_PU_VAS_PBCFG0_PBCFG_0_INJ_FREQ = 24 ;
+static const uint8_t P9N2_PU_VAS_PBCFG0_PBCFG_0_QUEUE_TO_TRACE = 25 ;
+static const uint8_t P9N2_PU_VAS_PBCFG0_PBCFG_0_QUEUE_TO_TRACE_LEN = 4 ;
+static const uint8_t P9N2_PU_VAS_PBCFG0_PBCFG_0_QUEUE_DISABLES = 29 ;
+static const uint8_t P9N2_PU_VAS_PBCFG0_PBCFG_0_QUEUE_DISABLES_LEN = 3 ;
+
+static const uint8_t P9N2_PU_VAS_PBCFG1_DISABLE_LN_WR = 0 ;
+static const uint8_t P9N2_PU_VAS_PBCFG1_DISABLE_G_WR = 1 ;
+static const uint8_t P9N2_PU_VAS_PBCFG1_DISABLE_VG_WR = 2 ;
+static const uint8_t P9N2_PU_VAS_PBCFG1_DISABLE_NN_WR = 3 ;
+static const uint8_t P9N2_PU_VAS_PBCFG1_DISABLE_LN_RD = 4 ;
+static const uint8_t P9N2_PU_VAS_PBCFG1_DISABLE_G_RD = 5 ;
+static const uint8_t P9N2_PU_VAS_PBCFG1_DISABLE_VG_RD = 6 ;
+static const uint8_t P9N2_PU_VAS_PBCFG1_DISABLE_NN_RD = 7 ;
+static const uint8_t P9N2_PU_VAS_PBCFG1_PBCFG_1_UNUSED1 = 8 ;
+static const uint8_t P9N2_PU_VAS_PBCFG1_PBCFG_1_UNUSED1_LEN = 4 ;
+static const uint8_t P9N2_PU_VAS_PBCFG1_RD_GO_M_QOS = 12 ;
+static const uint8_t P9N2_PU_VAS_PBCFG1_ADDR_BAR_MODE = 13 ;
+static const uint8_t P9N2_PU_VAS_PBCFG1_SKIP_G = 14 ;
+static const uint8_t P9N2_PU_VAS_PBCFG1_HANG_SM_ON_ARE = 15 ;
+static const uint8_t P9N2_PU_VAS_PBCFG1_HANG_SM_ON_LINK_FAIL = 16 ;
+static const uint8_t P9N2_PU_VAS_PBCFG1_CFG_PUMP_MODE = 17 ;
+static const uint8_t P9N2_PU_VAS_PBCFG1_DMA_WR_NOT_INJ = 18 ;
+static const uint8_t P9N2_PU_VAS_PBCFG1_DMA_PART_WR_NOT_INJ = 19 ;
+static const uint8_t P9N2_PU_VAS_PBCFG1_DMA_RD_VG_RST_TMASK = 20 ;
+static const uint8_t P9N2_PU_VAS_PBCFG1_DMA_RD_VG_RST_TMASK_LEN = 8 ;
+static const uint8_t P9N2_PU_VAS_PBCFG1_DMA_WR_VG_RST_TMASK = 28 ;
+static const uint8_t P9N2_PU_VAS_PBCFG1_DMA_WR_VG_RST_TMASK_LEN = 8 ;
+static const uint8_t P9N2_PU_VAS_PBCFG1_PBCFG_1_UNUSED2 = 36 ;
+static const uint8_t P9N2_PU_VAS_PBCFG1_PBCFG_1_UNUSED2_LEN = 16 ;
+
+static const uint8_t P9N2_PU_VAS_PMCNTL_PU_BIT_ENABLES = 0 ;
+static const uint8_t P9N2_PU_VAS_PMCNTL_PU_BIT_ENABLES_LEN = 32 ;
+static const uint8_t P9N2_PU_VAS_PMCNTL_PU_CNTL_UNUSED = 32 ;
+static const uint8_t P9N2_PU_VAS_PMCNTL_PU_CNTL_UNUSED_LEN = 4 ;
+
+static const uint8_t P9N2_PU_VAS_RGERRRPT_RG_CERR_RESET = 0 ;
+static const uint8_t P9N2_PU_VAS_RGERRRPT_RG_CERR_BIT4 = 4 ;
+static const uint8_t P9N2_PU_VAS_RGERRRPT_RG_CERR_BIT5 = 5 ;
+static const uint8_t P9N2_PU_VAS_RGERRRPT_RG_CERR_BIT6 = 6 ;
+static const uint8_t P9N2_PU_VAS_RGERRRPT_RG_CERR_BIT7 = 7 ;
+static const uint8_t P9N2_PU_VAS_RGERRRPT_RG_CERR_BIT8 = 8 ;
+static const uint8_t P9N2_PU_VAS_RGERRRPT_RG_CERR_BIT9 = 9 ;
+static const uint8_t P9N2_PU_VAS_RGERRRPT_RG_CERR_BIT10 = 10 ;
+static const uint8_t P9N2_PU_VAS_RGERRRPT_RG_CERR_BIT11 = 11 ;
+static const uint8_t P9N2_PU_VAS_RGERRRPT_RG_CERR_BIT12 = 12 ;
+static const uint8_t P9N2_PU_VAS_RGERRRPT_RG_CERR_BIT13 = 13 ;
+static const uint8_t P9N2_PU_VAS_RGERRRPT_RG_CERR_UNUSED_BITS = 14 ;
+static const uint8_t P9N2_PU_VAS_RGERRRPT_RG_CERR_UNUSED_BITS_LEN = 10 ;
+
+static const uint8_t P9N2_PU_VAS_RMABAR_RMA_BAR = 8 ;
+static const uint8_t P9N2_PU_VAS_RMABAR_RMA_BAR_LEN = 44 ;
+
+static const uint8_t P9N2_PU_VAS_RMABARM_RMA_BAR_MASK = 8 ;
+static const uint8_t P9N2_PU_VAS_RMABARM_RMA_BAR_MASK_LEN = 44 ;
+
+static const uint8_t P9N2_PU_VAS_SOUTHCTL_SOUTH_CTL_DISABLE_WC_SCRUB = 0 ;
+static const uint8_t P9N2_PU_VAS_SOUTHCTL_SOUTH_CTL_DISABLE_WC_ECC = 1 ;
+static const uint8_t P9N2_PU_VAS_SOUTHCTL_SOUTH_CTL_EG_SINGLE_THREAD = 2 ;
+static const uint8_t P9N2_PU_VAS_SOUTHCTL_SOUTH_CTL_EG_WM_CTX_UPDATE_MODE = 3 ;
+static const uint8_t P9N2_PU_VAS_SOUTHCTL_SOUTH_CTL_EG_STAMP_DEBUG = 4 ;
+static const uint8_t P9N2_PU_VAS_SOUTHCTL_SOUTH_CTL_EN_FAST_SCRUB = 5 ;
+static const uint8_t P9N2_PU_VAS_SOUTHCTL_SOUTH_CTL_DIS_SIMULT_RD_WR = 6 ;
+static const uint8_t P9N2_PU_VAS_SOUTHCTL_SOUTH_CTL_ENA_NOTIFY_ORDER = 7 ;
+static const uint8_t P9N2_PU_VAS_SOUTHCTL_SOUTH_CTL_WC_IDLE_BIT = 8 ;
+static const uint8_t P9N2_PU_VAS_SOUTHCTL_SOUTH_CTL_CQ_IDLE_BIT = 9 ;
+static const uint8_t P9N2_PU_VAS_SOUTHCTL_SOUTH_CTL_EG_IDLE_BIT = 10 ;
+static const uint8_t P9N2_PU_VAS_SOUTHCTL_SOUTH_CTL_UNUSED = 11 ;
+static const uint8_t P9N2_PU_VAS_SOUTHCTL_SOUTH_CTL_UNUSED_LEN = 5 ;
+
+static const uint8_t P9N2_PU_VAS_UWMBAR_BASE_ADDR = 8 ;
+static const uint8_t P9N2_PU_VAS_UWMBAR_BASE_ADDR_LEN = 28 ;
+
+static const uint8_t P9N2_PU_VAS_WCBSBAR_WC_BS_BAR = 8 ;
+static const uint8_t P9N2_PU_VAS_WCBSBAR_WC_BS_BAR_LEN = 33 ;
+
+static const uint8_t P9N2_PU_VAS_WCERRRPT_WC_CERR_RESET = 0 ;
+static const uint8_t P9N2_PU_VAS_WCERRRPT_WC_CERR_BIT4 = 4 ;
+static const uint8_t P9N2_PU_VAS_WCERRRPT_WC_CERR_BIT5 = 5 ;
+static const uint8_t P9N2_PU_VAS_WCERRRPT_WC_CERR_BIT6 = 6 ;
+static const uint8_t P9N2_PU_VAS_WCERRRPT_WC_CERR_BIT7 = 7 ;
+static const uint8_t P9N2_PU_VAS_WCERRRPT_WC_CERR_BIT8 = 8 ;
+static const uint8_t P9N2_PU_VAS_WCERRRPT_WC_CERR_BIT9 = 9 ;
+static const uint8_t P9N2_PU_VAS_WCERRRPT_WC_CERR_BIT10 = 10 ;
+static const uint8_t P9N2_PU_VAS_WCERRRPT_WC_CERR_BIT11 = 11 ;
+static const uint8_t P9N2_PU_VAS_WCERRRPT_WC_CERR_BIT12 = 12 ;
+static const uint8_t P9N2_PU_VAS_WCERRRPT_WC_CERR_BIT13 = 13 ;
+static const uint8_t P9N2_PU_VAS_WCERRRPT_WC_CERR_BIT14 = 14 ;
+static const uint8_t P9N2_PU_VAS_WCERRRPT_WC_CERR_BIT15 = 15 ;
+static const uint8_t P9N2_PU_VAS_WCERRRPT_WC_CERR_BIT16 = 16 ;
+static const uint8_t P9N2_PU_VAS_WCERRRPT_WC_CERR_BIT17 = 17 ;
+static const uint8_t P9N2_PU_VAS_WCERRRPT_WC_CERR_BIT18 = 18 ;
+static const uint8_t P9N2_PU_VAS_WCERRRPT_WC_CERR_BIT19 = 19 ;
+static const uint8_t P9N2_PU_VAS_WCERRRPT_WC_CERR_BIT20 = 20 ;
+static const uint8_t P9N2_PU_VAS_WCERRRPT_WC_CERR_BIT21 = 21 ;
+static const uint8_t P9N2_PU_VAS_WCERRRPT_WC_CERR_BIT22 = 22 ;
+static const uint8_t P9N2_PU_VAS_WCERRRPT_WC_CERR_BIT23 = 23 ;
+
+static const uint8_t P9N2_PU_VAS_WCMBAR_BASE_ADDR = 8 ;
+static const uint8_t P9N2_PU_VAS_WCMBAR_BASE_ADDR_LEN = 31 ;
+
+static const uint8_t P9N2_PU_WATCHDOG_HANG_TIMERS_CNTL_CH0_TIMER_ENBL = 0 ;
+static const uint8_t P9N2_PU_WATCHDOG_HANG_TIMERS_CNTL_CH0_REF_DIV = 1 ;
+static const uint8_t P9N2_PU_WATCHDOG_HANG_TIMERS_CNTL_CH0_REF_DIV_LEN = 4 ;
+static const uint8_t P9N2_PU_WATCHDOG_HANG_TIMERS_CNTL_CH1_TIMER_ENBL = 5 ;
+static const uint8_t P9N2_PU_WATCHDOG_HANG_TIMERS_CNTL_CH1_REF_DIV = 6 ;
+static const uint8_t P9N2_PU_WATCHDOG_HANG_TIMERS_CNTL_CH1_REF_DIV_LEN = 4 ;
+static const uint8_t P9N2_PU_WATCHDOG_HANG_TIMERS_CNTL_CH2_TIMER_ENBL = 10 ;
+static const uint8_t P9N2_PU_WATCHDOG_HANG_TIMERS_CNTL_CH2_REF_DIV = 11 ;
+static const uint8_t P9N2_PU_WATCHDOG_HANG_TIMERS_CNTL_CH2_REF_DIV_LEN = 4 ;
+static const uint8_t P9N2_PU_WATCHDOG_HANG_TIMERS_CNTL_CH3_TIMER_ENBL = 15 ;
+static const uint8_t P9N2_PU_WATCHDOG_HANG_TIMERS_CNTL_CH3_REF_DIV = 16 ;
+static const uint8_t P9N2_PU_WATCHDOG_HANG_TIMERS_CNTL_CH3_REF_DIV_LEN = 4 ;
+static const uint8_t P9N2_PU_WATCHDOG_HANG_TIMERS_CNTL_CH4_TIMER_ENBL = 20 ;
+static const uint8_t P9N2_PU_WATCHDOG_HANG_TIMERS_CNTL_CH4_REF_DIV = 21 ;
+static const uint8_t P9N2_PU_WATCHDOG_HANG_TIMERS_CNTL_CH4_REF_DIV_LEN = 4 ;
+static const uint8_t P9N2_PU_WATCHDOG_HANG_TIMERS_CNTL_DMA_TIMER_ENBL = 25 ;
+static const uint8_t P9N2_PU_WATCHDOG_HANG_TIMERS_CNTL_DMA_TIMER_REF_DIV = 26 ;
+static const uint8_t P9N2_PU_WATCHDOG_HANG_TIMERS_CNTL_DMA_TIMER_REF_DIV_LEN = 4 ;
+
+static const uint8_t P9N2_PU_WATER_MARK_REGISTER_B_WATERMARK_REG_0 = 16 ;
+static const uint8_t P9N2_PU_WATER_MARK_REGISTER_B_WATERMARK_REG_0_LEN = 16 ;
+static const uint8_t P9N2_PU_WATER_MARK_REGISTER_B_PEEK_DATA1_0 = 32 ;
+static const uint8_t P9N2_PU_WATER_MARK_REGISTER_B_PEEK_DATA1_0_LEN = 8 ;
+static const uint8_t P9N2_PU_WATER_MARK_REGISTER_B_LBUS_PARITY_ERR1_0 = 40 ;
+
+static const uint8_t P9N2_PU_WATER_MARK_REGISTER_C_WATERMARK_REG_1 = 16 ;
+static const uint8_t P9N2_PU_WATER_MARK_REGISTER_C_WATERMARK_REG_1_LEN = 16 ;
+static const uint8_t P9N2_PU_WATER_MARK_REGISTER_C_PEEK_DATA1_1 = 32 ;
+static const uint8_t P9N2_PU_WATER_MARK_REGISTER_C_PEEK_DATA1_1_LEN = 8 ;
+static const uint8_t P9N2_PU_WATER_MARK_REGISTER_C_LBUS_PARITY_ERR1_1 = 40 ;
+
+static const uint8_t P9N2_PU_WATER_MARK_REGISTER_D_WATERMARK_REG_2 = 16 ;
+static const uint8_t P9N2_PU_WATER_MARK_REGISTER_D_WATERMARK_REG_2_LEN = 16 ;
+static const uint8_t P9N2_PU_WATER_MARK_REGISTER_D_PEEK_DATA1_2 = 32 ;
+static const uint8_t P9N2_PU_WATER_MARK_REGISTER_D_PEEK_DATA1_2_LEN = 8 ;
+static const uint8_t P9N2_PU_WATER_MARK_REGISTER_D_LBUS_PARITY_ERR1_2 = 40 ;
+
+static const uint8_t P9N2_PU_WATER_MARK_REGISTER_E_WATERMARK_REG_3 = 16 ;
+static const uint8_t P9N2_PU_WATER_MARK_REGISTER_E_WATERMARK_REG_3_LEN = 16 ;
+static const uint8_t P9N2_PU_WATER_MARK_REGISTER_E_PEEK_DATA1_3 = 32 ;
+static const uint8_t P9N2_PU_WATER_MARK_REGISTER_E_PEEK_DATA1_3_LEN = 8 ;
+static const uint8_t P9N2_PU_WATER_MARK_REGISTER_E_LBUS_PARITY_ERR1_3 = 40 ;
+
+static const uint8_t P9N2_PHB_WOF_REG_AIB_COMMAND_INVALID = 0 ;
+static const uint8_t P9N2_PHB_WOF_REG_AIB_ADDRESSING_ERROR = 1 ;
+static const uint8_t P9N2_PHB_WOF_REG_AIB_ACCESS_ERROR = 2 ;
+static const uint8_t P9N2_PHB_WOF_REG_PAPR_OUTBOUND_INJECTION_ERROR_TRIGGERED = 3 ;
+static const uint8_t P9N2_PHB_WOF_REG_AIB_FATAL_CLASS_ERROR = 4 ;
+static const uint8_t P9N2_PHB_WOF_REG_AIB_INF_CLASS_ERROR = 5 ;
+static const uint8_t P9N2_PHB_WOF_REG_PE_STOP_STATE_ERROR = 6 ;
+static const uint8_t P9N2_PHB_WOF_REG_AIB_DAT_ERR_SIGNALED = 7 ;
+static const uint8_t P9N2_PHB_WOF_REG_OUT_COMMON_ARRAY_FATAL_ERROR = 8 ;
+static const uint8_t P9N2_PHB_WOF_REG_OUT_COMMON_LATCH_FATAL_ERROR = 9 ;
+static const uint8_t P9N2_PHB_WOF_REG_OUT_COMMON_LOGIC_FATAL_ERROR = 10 ;
+static const uint8_t P9N2_PHB_WOF_REG_BLIF_OUT_INTERFACE_PARITY_ERROR = 11 ;
+static const uint8_t P9N2_PHB_WOF_REG_PCIE_CFG_WRITE_CA_OR_UR_RESPONSE = 12 ;
+static const uint8_t P9N2_PHB_WOF_REG_MMIO_REQUEST_TIMEOUT = 13 ;
+static const uint8_t P9N2_PHB_WOF_REG_OUT_RRB_SOURCED_ERROR = 14 ;
+static const uint8_t P9N2_PHB_WOF_REG_CFG_LOGIC_SIGNALED_ERROR = 15 ;
+static const uint8_t P9N2_PHB_WOF_REG_RSB_REG_REQUEST_ADDRESS_ERROR = 16 ;
+static const uint8_t P9N2_PHB_WOF_REG_RSB_FDA_FATAL_ERROR = 17 ;
+static const uint8_t P9N2_PHB_WOF_REG_RSB_FDA_INF_ERROR = 18 ;
+static const uint8_t P9N2_PHB_WOF_REG_RSB_FDB_FATAL_ERROR = 19 ;
+static const uint8_t P9N2_PHB_WOF_REG_RSB_FDB_INF_ERROR = 20 ;
+static const uint8_t P9N2_PHB_WOF_REG_RSB_ERR_FATAL_ERROR = 21 ;
+static const uint8_t P9N2_PHB_WOF_REG_RSB_ERR_INF_ERROR = 22 ;
+static const uint8_t P9N2_PHB_WOF_REG_RSB_DBG_FATAL_ERROR = 23 ;
+static const uint8_t P9N2_PHB_WOF_REG_RSB_DBG_INF_ERROR = 24 ;
+static const uint8_t P9N2_PHB_WOF_REG_RSB_PCIE_REQUEST_ACCESS_ERROR = 25 ;
+static const uint8_t P9N2_PHB_WOF_REG_RSB_BUS_LOGIC_ERROR = 26 ;
+static const uint8_t P9N2_PHB_WOF_REG_RSB_UVI_FATAL_ERROR = 27 ;
+static const uint8_t P9N2_PHB_WOF_REG_RSB_UVI_INF_ERROR = 28 ;
+static const uint8_t P9N2_PHB_WOF_REG_SCOM_FATAL_ERROR = 29 ;
+static const uint8_t P9N2_PHB_WOF_REG_SCOM_INF_ERROR = 30 ;
+static const uint8_t P9N2_PHB_WOF_REG_PCIE_MACRO_ERROR_ACTIVE_STATUS = 31 ;
+static const uint8_t P9N2_PHB_WOF_REG_ARB_IODA_FATAL_ERROR = 32 ;
+static const uint8_t P9N2_PHB_WOF_REG_ARB_MSI_PE_MATCH_ERROR = 33 ;
+static const uint8_t P9N2_PHB_WOF_REG_ARB_MSI_ADDRESS_ERROR = 34 ;
+static const uint8_t P9N2_PHB_WOF_REG_ARB_TVT_ERROR = 35 ;
+static const uint8_t P9N2_PHB_WOF_REG_ARB_RCVD_FATAL_ERROR_MSG = 36 ;
+static const uint8_t P9N2_PHB_WOF_REG_ARB_RCVD_NONFATAL_ERROR_MSG = 37 ;
+static const uint8_t P9N2_PHB_WOF_REG_ARB_RCVD_CORRECTIBLE_ERROR_MSG = 38 ;
+static const uint8_t P9N2_PHB_WOF_REG_PAPR_INBOUND_INJECTION_ERROR_TRIGGERED = 39 ;
+static const uint8_t P9N2_PHB_WOF_REG_ARB_COMMON_FATAL_ERROR = 40 ;
+static const uint8_t P9N2_PHB_WOF_REG_ARB_TABLE_BAR_DISABLED_ERROR = 41 ;
+static const uint8_t P9N2_PHB_WOF_REG_ARB_BLIF_COMPLETION_ERROR = 42 ;
+static const uint8_t P9N2_PHB_WOF_REG_ARB_PCT_TIMEOUT_ERROR = 43 ;
+static const uint8_t P9N2_PHB_WOF_REG_ARB_ECC_CORRECTABLE_ERROR = 44 ;
+static const uint8_t P9N2_PHB_WOF_REG_ARB_ECC_UNCORRECTABLE_ERROR = 45 ;
+static const uint8_t P9N2_PHB_WOF_REG_ARB_TLP_POISON_SIGNALED = 46 ;
+static const uint8_t P9N2_PHB_WOF_REG_ARB_RTT_PENUM_INVALID_ERROR = 47 ;
+static const uint8_t P9N2_PHB_WOF_REG_MRG_COMMON_FATAL_ERROR = 48 ;
+static const uint8_t P9N2_PHB_WOF_REG_MRG_TABLE_BAR_DISABLED_ERROR = 49 ;
+static const uint8_t P9N2_PHB_WOF_REG_MRG_ECC_CORRECTABLE_ERROR = 50 ;
+static const uint8_t P9N2_PHB_WOF_REG_MRG_ECC_UNCORRECTABLE_ERROR = 51 ;
+static const uint8_t P9N2_PHB_WOF_REG_MRG_AIB2_TX_TIMEOUT_ERROR = 52 ;
+static const uint8_t P9N2_PHB_WOF_REG_MRG_MRT_ERROR = 53 ;
+static const uint8_t P9N2_PHB_WOF_REG_MRG_RESERVED01 = 54 ;
+static const uint8_t P9N2_PHB_WOF_REG_MRG_RESERVED02 = 55 ;
+static const uint8_t P9N2_PHB_WOF_REG_TCE_IODA_PAGE_ACCESS_ERROR = 56 ;
+static const uint8_t P9N2_PHB_WOF_REG_TCE_REQUEST_TIMEOUT_ERROR = 57 ;
+static const uint8_t P9N2_PHB_WOF_REG_TCE_UNEXPECTED_RESPONSE_ERROR = 58 ;
+static const uint8_t P9N2_PHB_WOF_REG_TCE_COMMON_FATAL_ERRORS = 59 ;
+static const uint8_t P9N2_PHB_WOF_REG_TCE_ECC_CORRECTABLE_ERROR = 60 ;
+static const uint8_t P9N2_PHB_WOF_REG_TCE_ECC_UNCORRECTABLE_ERROR = 61 ;
+static const uint8_t P9N2_PHB_WOF_REG_TCE_RESERVED01 = 62 ;
+static const uint8_t P9N2_PHB_WOF_REG_LEM_FIR_INTERNAL_PARITY_ERROR = 63 ;
+
+static const uint8_t P9N2_PU_N3_WRITE_PROTECT_ENABLE_REG_RING_LOCKING = 0 ;
+static const uint8_t P9N2_PU_N3_WRITE_PROTECT_ENABLE_REG_RESERVED_RING_LOCKING = 1 ;
+
+static const uint8_t P9N2_PU_N1_WRITE_PROTECT_ENABLE_REG_RING_LOCKING = 0 ;
+static const uint8_t P9N2_PU_N1_WRITE_PROTECT_ENABLE_REG_RESERVED_RING_LOCKING = 1 ;
+
+static const uint8_t P9N2_PU_WRITE_PROTECT_ENABLE_REG_RING_LOCKING = 0 ;
+static const uint8_t P9N2_PU_WRITE_PROTECT_ENABLE_REG_RESERVED_RING_LOCKING = 1 ;
+
+static const uint8_t P9N2_PU_N2_WRITE_PROTECT_ENABLE_REG_RING_LOCKING = 0 ;
+static const uint8_t P9N2_PU_N2_WRITE_PROTECT_ENABLE_REG_RESERVED_RING_LOCKING = 1 ;
+
+static const uint8_t P9N2_PEC_WRITE_PROTECT_ENABLE_REG_RING_LOCKING = 0 ;
+static const uint8_t P9N2_PEC_WRITE_PROTECT_ENABLE_REG_RESERVED_RING_LOCKING = 1 ;
+
+static const uint8_t P9N2_PU_N0_WRITE_PROTECT_ENABLE_REG_RING_LOCKING = 0 ;
+static const uint8_t P9N2_PU_N0_WRITE_PROTECT_ENABLE_REG_RESERVED_RING_LOCKING = 1 ;
+
+static const uint8_t P9N2_PU_N3_WRITE_PROTECT_RINGS_REG_RINGS = 0 ;
+static const uint8_t P9N2_PU_N3_WRITE_PROTECT_RINGS_REG_RINGS_LEN = 16 ;
+
+static const uint8_t P9N2_PU_N1_WRITE_PROTECT_RINGS_REG_RINGS = 0 ;
+static const uint8_t P9N2_PU_N1_WRITE_PROTECT_RINGS_REG_RINGS_LEN = 16 ;
+
+static const uint8_t P9N2_PU_WRITE_PROTECT_RINGS_REG_RINGS = 0 ;
+static const uint8_t P9N2_PU_WRITE_PROTECT_RINGS_REG_RINGS_LEN = 16 ;
+
+static const uint8_t P9N2_PU_N2_WRITE_PROTECT_RINGS_REG_RINGS = 0 ;
+static const uint8_t P9N2_PU_N2_WRITE_PROTECT_RINGS_REG_RINGS_LEN = 16 ;
+
+static const uint8_t P9N2_PEC_WRITE_PROTECT_RINGS_REG_RINGS = 0 ;
+static const uint8_t P9N2_PEC_WRITE_PROTECT_RINGS_REG_RINGS_LEN = 16 ;
+
+static const uint8_t P9N2_PU_N0_WRITE_PROTECT_RINGS_REG_RINGS = 0 ;
+static const uint8_t P9N2_PU_N0_WRITE_PROTECT_RINGS_REG_RINGS_LEN = 16 ;
+
+static const uint8_t P9N2_PEC_XFIR_IN0 = 0 ;
+static const uint8_t P9N2_PEC_XFIR_IN1 = 1 ;
+static const uint8_t P9N2_PEC_XFIR_IN2 = 2 ;
+static const uint8_t P9N2_PEC_XFIR_IN3 = 3 ;
+static const uint8_t P9N2_PEC_XFIR_IN4 = 4 ;
+static const uint8_t P9N2_PEC_XFIR_IN5 = 5 ;
+static const uint8_t P9N2_PEC_XFIR_IN6 = 6 ;
+static const uint8_t P9N2_PEC_XFIR_IN7 = 7 ;
+static const uint8_t P9N2_PEC_XFIR_IN7_LEN = 19 ;
+static const uint8_t P9N2_PEC_XFIR_IN26 = 26 ;
+
+static const uint8_t P9N2_CAPP_XPT_CONTROL_SEND_PACKET_TIMER_VALUE = 0 ;
+static const uint8_t P9N2_CAPP_XPT_CONTROL_SEND_PACKET_TIMER_VALUE_LEN = 10 ;
+static const uint8_t P9N2_CAPP_XPT_CONTROL_CI_STORE_BUFFER_THRESHOLD = 10 ;
+static const uint8_t P9N2_CAPP_XPT_CONTROL_CI_STORE_BUFFER_THRESHOLD_LEN = 4 ;
+static const uint8_t P9N2_CAPP_XPT_CONTROL_MAX_LPC_DATA_PBH0_CI_STORE_BUFFERS = 14 ;
+static const uint8_t P9N2_CAPP_XPT_CONTROL_MAX_LPC_DATA_PBH0_CI_STORE_BUFFERS_LEN = 4 ;
+static const uint8_t P9N2_CAPP_XPT_CONTROL_TLBI_DATA_POLL_PULSE_DIV = 18 ;
+static const uint8_t P9N2_CAPP_XPT_CONTROL_TLBI_DATA_POLL_PULSE_DIV_LEN = 4 ;
+static const uint8_t P9N2_CAPP_XPT_CONTROL_SN_WRT_DBUF_MAX_CREDIT = 22 ;
+static const uint8_t P9N2_CAPP_XPT_CONTROL_SN_WRT_DBUF_MAX_CREDIT_LEN = 4 ;
+static const uint8_t P9N2_CAPP_XPT_CONTROL_RESERVED = 26 ;
+static const uint8_t P9N2_CAPP_XPT_CONTROL_RESERVED_LEN = 2 ;
+static const uint8_t P9N2_CAPP_XPT_CONTROL_SN_MSG_MAX_CREDIT = 28 ;
+static const uint8_t P9N2_CAPP_XPT_CONTROL_SN_MSG_MAX_CREDIT_LEN = 9 ;
+static const uint8_t P9N2_CAPP_XPT_CONTROL_BENIGN_PTR_DATA = 37 ;
+static const uint8_t P9N2_CAPP_XPT_CONTROL_TLBIE_STALL_EN = 38 ;
+static const uint8_t P9N2_CAPP_XPT_CONTROL_TLBIE_STALL_THRESHOLD = 39 ;
+static const uint8_t P9N2_CAPP_XPT_CONTROL_TLBIE_STALL_THRESHOLD_LEN = 3 ;
+static const uint8_t P9N2_CAPP_XPT_CONTROL_TLBIE_STALL_CMPLT_CNT = 42 ;
+static const uint8_t P9N2_CAPP_XPT_CONTROL_TLBIE_STALL_CMPLT_CNT_LEN = 4 ;
+static const uint8_t P9N2_CAPP_XPT_CONTROL_TLBIE_STALL_DELAY_CNT = 46 ;
+static const uint8_t P9N2_CAPP_XPT_CONTROL_TLBIE_STALL_DELAY_CNT_LEN = 8 ;
+static const uint8_t P9N2_CAPP_XPT_CONTROL_CI_BUFF_MIN = 58 ;
+static const uint8_t P9N2_CAPP_XPT_CONTROL_CI_BUFF_MIN_LEN = 4 ;
+static const uint8_t P9N2_CAPP_XPT_CONTROL_CI_BUFF_AVAIL = 62 ;
+static const uint8_t P9N2_CAPP_XPT_CONTROL_LOAD_CI_BUFF = 63 ;
+
+static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_PSL_CMD_UE_ERRHOLD = 0 ;
+static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_PSL_CMD_SUE_ERRHOLD = 1 ;
+static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_SC_RDATA_PARITY_ERRHOLD = 2 ;
+static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_APC_SC_RDATA_PARITY_ERRHOLD = 3 ;
+static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_SN_SC_RDATA_PARITY_ERRHOLD = 4 ;
+static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_NX_DATA_RTAG_PARITY_ERRHOLD = 5 ;
+static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_NXPBXPT_PBRCV_ECC_CE_ERRHOLD = 6 ;
+static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_NXPBXPT_PBRCV_ECC_UE_ERRHOLD = 7 ;
+static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_NXPBXPT_PBRCV_ECC_SUE_ERRHOLD = 8 ;
+static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_DBG_CTL_REG_PARITY_ERRHOLD = 9 ;
+static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_CFG_REG_PARITY_ERRHOLD = 10 ;
+static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_CAPP_ERR_STAT_CTL_REG_PARITY_ERRHOLD = 11 ;
+static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_PMU_CNTRA_CFG_REG_PARITY_ERRHOLD = 12 ;
+static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_PMU_CNTRB_CFG_REG_PARITY_ERRHOLD = 13 ;
+static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_PMU_EVENT_SEL_REG_PARITY_ERRHOLD = 14 ;
+static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_PE0_CXA_LINKDOWN_ERRHOLD = 15 ;
+static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_PE1_CXA_LINKDOWN_ERRHOLD = 16 ;
+static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_SB_SCOM_ERRHOLD = 17 ;
+static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_PBXMIT_MSGQ_SEQ_ERRHOLD = 18 ;
+static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_PBXMIT_DXMIT_SEQ_ERRHOLD = 19 ;
+static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_EPH_REC_TMR_CNTL_REG_PARITY_ERRHOLD = 20 ;
+static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_RCS_RECOVERY_FAILED_ERRHOLD = 21 ;
+static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_RCS_STATE_MACHINE_ERRHOLD = 22 ;
+static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_NXPBXPT_PBRCV_LNK_RSP_ECC_UE_ERRHOLD = 23 ;
+static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_NXPBXPT_PBRCV_LNK_RSP_ECC_SUE_ERRHOLD = 24 ;
+static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_LNK_RSP_PKT_DISCARDED_ERRHOLD = 25 ;
+static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_SECURE_LNK_RSP_PKT_NOT_VALID_ERRHOLD = 26 ;
+static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_SECURE_LNK_SCOM_CONFLICT_ERRHOLD = 27 ;
+static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_UNSOLICITED_DATA_RCV_ERRHOLD = 28 ;
+static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_AS_RCMD0_PARITY_ERR_ERRHOLD = 29 ;
+static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_AS_REGS_PARITY_ERR_ERRHOLD = 30 ;
+static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_AS_SM_ERRHOLD = 31 ;
+static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_AS_REG_RDATA_PERR_ERRHOLD = 32 ;
+static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_DFS_SM_ERRHOLD = 33 ;
+static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_TB_FIR_ERR_ERRHOLD = 34 ;
+static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_TB_CMD_DISCARDED_ERRHOLD = 35 ;
+static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_TB_REG_RDATA_PERR_ERRHOLD = 36 ;
+static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_RNG_WR_ENBL_REG_PERR_ERRHOLD = 37 ;
+static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_SSA_ECC_HI_UE_ERRHOLD = 38 ;
+static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_SSA_ECC_HI_CE_ERRHOLD = 39 ;
+static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_SSA_ECC_HI_SUE_ERRHOLD = 40 ;
+static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_SSA_ECC_LO_SUE_ERRHOLD = 41 ;
+static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_SSA_ECC_LO_CE_ERRHOLD = 42 ;
+static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_SSA_ECC_LO_UE_ERRHOLD = 43 ;
+static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_CXACQPB_MUX_ECC_CE_ERRHOLD = 44 ;
+static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_CXACQPB_MUX_ECC_UE_ERRHOLD = 45 ;
+static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_APC0_SC_RDATA_PARITY_ERRHOLD = 46 ;
+static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_CREDIT_TIMEOUT_ERRHOLD = 47 ;
+static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_TLBI_SC_RDATA_PARITY_ERRHOLD = 48 ;
+static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_TLBI_REGS_PARITY_ERRHOLD = 49 ;
+static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_RCS_RECOVERY_TIMEOUT_ERRHOLD = 50 ;
+static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_TBST0_BADIN_ERRHOLD = 51 ;
+static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_TBST6_BADIN_ERRHOLD = 52 ;
+static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_TBST7_BADIN_ERRHOLD = 53 ;
+static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_TWO_TFMRCMDS_ERR_ERRHOLD = 54 ;
+static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_TB_MISSING_SYNC_ERRHOLD = 55 ;
+static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_TB_MISSING_STEP_ERRHOLD = 56 ;
+static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_TB_RESIDUE_ERR_ERRHOLD = 57 ;
+static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_TX_TFMR_CORRUPT_ERRHOLD = 58 ;
+static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_TBST_CORRUPT_ERRHOLD = 59 ;
+static const uint8_t P9N2_CAPP_XPT_ERROR_REPORT_TBST9_BADIN_ERRHOLD = 60 ;
+
+static const uint8_t P9N2_CAPP_XPT_PMU_EVENTS_SEL_PMON_GROUP_SELECT = 0 ;
+static const uint8_t P9N2_CAPP_XPT_PMU_EVENTS_SEL_PMON_GROUP_SELECT_LEN = 4 ;
+
+static const uint8_t P9N2_PU_XSCOM_BASE_REG_FBC = 8 ;
+static const uint8_t P9N2_PU_XSCOM_BASE_REG_FBC_LEN = 22 ;
+static const uint8_t P9N2_PU_XSCOM_BASE_REG_FBC_RESET = 61 ;
+static const uint8_t P9N2_PU_XSCOM_BASE_REG_FBC_DISABLE = 62 ;
+static const uint8_t P9N2_PU_XSCOM_BASE_REG_FBC_DISABLE_LOCAL_SHORTCUT = 63 ;
+
+static const uint8_t P9N2_PU_XSCOM_DAT0_REG_DAT0 = 0 ;
+static const uint8_t P9N2_PU_XSCOM_DAT0_REG_DAT0_LEN = 64 ;
+
+static const uint8_t P9N2_PU_XSCOM_DAT1_REG_DAT1 = 0 ;
+static const uint8_t P9N2_PU_XSCOM_DAT1_REG_DAT1_LEN = 64 ;
+
+static const uint8_t P9N2_PU_XSCOM_ERR_REG_ADDRESS = 0 ;
+static const uint8_t P9N2_PU_XSCOM_ERR_REG_TSIZE = 1 ;
+static const uint8_t P9N2_PU_XSCOM_ERR_REG_RC_TTAG_PAR = 2 ;
+static const uint8_t P9N2_PU_XSCOM_ERR_REG_CR_TTAG_PAR = 3 ;
+static const uint8_t P9N2_PU_XSCOM_ERR_REG_CR_ATAG_PAR = 4 ;
+static const uint8_t P9N2_PU_XSCOM_ERR_REG_RC_ADDR_PAR = 5 ;
+static const uint8_t P9N2_PU_XSCOM_ERR_REG_PB_ECC_CE = 8 ;
+static const uint8_t P9N2_PU_XSCOM_ERR_REG_PB_ECC_UE = 9 ;
+static const uint8_t P9N2_PU_XSCOM_ERR_REG_PB_ECC_SUE = 10 ;
+static const uint8_t P9N2_PU_XSCOM_ERR_REG_RTAG_PARITY = 11 ;
+static const uint8_t P9N2_PU_XSCOM_ERR_REG_CRESP_HANG = 12 ;
+static const uint8_t P9N2_PU_XSCOM_ERR_REG_PIB_HANG = 13 ;
+static const uint8_t P9N2_PU_XSCOM_ERR_REG_PBDATA_HANG = 14 ;
+static const uint8_t P9N2_PU_XSCOM_ERR_REG_ADS_HANG = 15 ;
+static const uint8_t P9N2_PU_XSCOM_ERR_REG_FSM_PERR = 16 ;
+static const uint8_t P9N2_PU_XSCOM_ERR_REG_SPARE0 = 17 ;
+static const uint8_t P9N2_PU_XSCOM_ERR_REG_SPARE1 = 18 ;
+static const uint8_t P9N2_PU_XSCOM_ERR_REG_UNEXPECT_DATA = 19 ;
+static const uint8_t P9N2_PU_XSCOM_ERR_REG_ILL_CRESP = 20 ;
+
+static const uint8_t P9N2_PU_XSCOM_LOG_REG_CMD_IN_PROG = 0 ;
+static const uint8_t P9N2_PU_XSCOM_LOG_REG_CMD_STATUS = 1 ;
+static const uint8_t P9N2_PU_XSCOM_LOG_REG_CMD_STATUS_LEN = 3 ;
+static const uint8_t P9N2_PU_XSCOM_LOG_REG_WRITE_CMD = 4 ;
+static const uint8_t P9N2_PU_XSCOM_LOG_REG_ADDR_TAG = 5 ;
+static const uint8_t P9N2_PU_XSCOM_LOG_REG_ADDR_TAG_LEN = 22 ;
+static const uint8_t P9N2_PU_XSCOM_LOG_REG_THR_ID = 27 ;
+static const uint8_t P9N2_PU_XSCOM_LOG_REG_THR_ID_LEN = 3 ;
+static const uint8_t P9N2_PU_XSCOM_LOG_REG_PIB_COMPONENT_BUSY = 31 ;
+static const uint8_t P9N2_PU_XSCOM_LOG_REG_PIB_ADDR = 33 ;
+static const uint8_t P9N2_PU_XSCOM_LOG_REG_PIB_ADDR_LEN = 31 ;
+
+static const uint8_t P9N2_PU_XSCOM_MODE_REG_SPARE = 0 ;
+static const uint8_t P9N2_PU_XSCOM_MODE_REG_SPARE_LEN = 4 ;
+static const uint8_t P9N2_PU_XSCOM_MODE_REG_BAR_PIB_ON_ERROR1 = 4 ;
+static const uint8_t P9N2_PU_XSCOM_MODE_REG_BAR_PIB_ON_ERROR2 = 5 ;
+static const uint8_t P9N2_PU_XSCOM_MODE_REG_BAR_PIB_ON_ERROR3 = 6 ;
+static const uint8_t P9N2_PU_XSCOM_MODE_REG_BAR_PIB_ON_ERROR4 = 7 ;
+static const uint8_t P9N2_PU_XSCOM_MODE_REG_BAR_PIB_ON_ERROR5 = 8 ;
+static const uint8_t P9N2_PU_XSCOM_MODE_REG_BAR_PIB_ON_ERROR6 = 9 ;
+static const uint8_t P9N2_PU_XSCOM_MODE_REG_BAR_PIB_ON_ERROR7 = 10 ;
+static const uint8_t P9N2_PU_XSCOM_MODE_REG_HANG_PIB_RESET = 11 ;
+static const uint8_t P9N2_PU_XSCOM_MODE_REG_HANG_RESET = 12 ;
+static const uint8_t P9N2_PU_XSCOM_MODE_REG_RESET_ON_PARITY = 13 ;
+static const uint8_t P9N2_PU_XSCOM_MODE_REG_FREEZE_LOG_ON_ERROR1 = 14 ;
+static const uint8_t P9N2_PU_XSCOM_MODE_REG_FREEZE_LOG_ON_ERROR2 = 15 ;
+static const uint8_t P9N2_PU_XSCOM_MODE_REG_FREEZE_LOG_ON_ERROR3 = 16 ;
+static const uint8_t P9N2_PU_XSCOM_MODE_REG_FREEZE_LOG_ON_ERROR4 = 17 ;
+static const uint8_t P9N2_PU_XSCOM_MODE_REG_FREEZE_LOG_ON_ERROR5 = 18 ;
+static const uint8_t P9N2_PU_XSCOM_MODE_REG_FREEZE_LOG_ON_ERROR6 = 19 ;
+static const uint8_t P9N2_PU_XSCOM_MODE_REG_FREEZE_LOG_ON_ERROR7 = 20 ;
+
+static const uint8_t P9N2_PU_XSCOM_RCVED_STAT_REG_DONE = 0 ;
+static const uint8_t P9N2_PU_XSCOM_RCVED_STAT_REG_RESULT = 1 ;
+static const uint8_t P9N2_PU_XSCOM_RCVED_STAT_REG_RESULT_LEN = 3 ;
+static const uint8_t P9N2_PU_XSCOM_RCVED_STAT_REG_COREID = 4 ;
+static const uint8_t P9N2_PU_XSCOM_RCVED_STAT_REG_COREID_LEN = 6 ;
+static const uint8_t P9N2_PU_XSCOM_RCVED_STAT_REG_THRID = 10 ;
+static const uint8_t P9N2_PU_XSCOM_RCVED_STAT_REG_THRID_LEN = 3 ;
+static const uint8_t P9N2_PU_XSCOM_RCVED_STAT_REG_DEST_GROUPID = 13 ;
+static const uint8_t P9N2_PU_XSCOM_RCVED_STAT_REG_DEST_GROUPID_LEN = 4 ;
+static const uint8_t P9N2_PU_XSCOM_RCVED_STAT_REG_DEST_CHIPID = 17 ;
+static const uint8_t P9N2_PU_XSCOM_RCVED_STAT_REG_DEST_CHIPID_LEN = 3 ;
+
+static const uint8_t P9N2_PU_NPU_DAT_XSL_ATD_DIAL = 53 ;
+static const uint8_t P9N2_PU_NPU_DAT_XSL_ATD_DIAL_LEN = 11 ;
+
+static const uint8_t P9N2__DAT_XSL_ATD_DIAL = 53 ;
+static const uint8_t P9N2__DAT_XSL_ATD_DIAL_LEN = 11 ;
+
+static const uint8_t P9N2_PU_NPU_DAT_XSL_DBG_WR_TO_DIAL = 0 ;
+static const uint8_t P9N2_PU_NPU_DAT_XSL_DBG_WR_TRNSO_DIAL = 1 ;
+static const uint8_t P9N2_PU_NPU_DAT_XSL_DBG_WR_DVS_DIAL = 8 ;
+static const uint8_t P9N2_PU_NPU_DAT_XSL_DBG_WR_DVS_DIAL_LEN = 16 ;
+
+static const uint8_t P9N2__DAT_XSL_DBG_WR_TO_DIAL = 0 ;
+static const uint8_t P9N2__DAT_XSL_DBG_WR_TRNSO_DIAL = 1 ;
+static const uint8_t P9N2__DAT_XSL_DBG_WR_DVS_DIAL = 8 ;
+static const uint8_t P9N2__DAT_XSL_DBG_WR_DVS_DIAL_LEN = 16 ;
+
+static const uint8_t P9N2__NTL0_XSL_DEBUG0_CONFIG_DIAL = 0 ;
+static const uint8_t P9N2__NTL0_XSL_DEBUG0_CONFIG_DIAL_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU_NTL0_XSL_DEBUG0_CONFIG_DIAL = 0 ;
+static const uint8_t P9N2_PU_NPU_NTL0_XSL_DEBUG0_CONFIG_DIAL_LEN = 64 ;
+
+static const uint8_t P9N2__NTL0_XSL_DEBUG1_CONFIG_DIAL = 0 ;
+static const uint8_t P9N2__NTL0_XSL_DEBUG1_CONFIG_DIAL_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU_NTL0_XSL_DEBUG1_CONFIG_DIAL = 0 ;
+static const uint8_t P9N2_PU_NPU_NTL0_XSL_DEBUG1_CONFIG_DIAL_LEN = 64 ;
+
+static const uint8_t P9N2_PU_NPU_DAT_XSL_DEF_MEE_DIAL = 0 ;
+static const uint8_t P9N2_PU_NPU_DAT_XSL_DEF_MEE_DIAL_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_DAT_XSL_DEF_ITL_DIAL = 5 ;
+static const uint8_t P9N2_PU_NPU_DAT_XSL_DEF_ITL_DIAL_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_DAT_XSL_DEF_ITE_DIAL = 8 ;
+static const uint8_t P9N2_PU_NPU_DAT_XSL_DEF_ITE_DIAL_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_DAT_XSL_DEF_CTXM_DIAL = 24 ;
+static const uint8_t P9N2_PU_NPU_DAT_XSL_DEF_CO_RTRY_LIM_DIAL = 61 ;
+static const uint8_t P9N2_PU_NPU_DAT_XSL_DEF_CO_RTRY_LIM_DIAL_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_DAT_XSL_DEF_DEFE_DIAL = 63 ;
+
+static const uint8_t P9N2__DAT_XSL_DEF_MEE_DIAL = 0 ;
+static const uint8_t P9N2__DAT_XSL_DEF_MEE_DIAL_LEN = 4 ;
+static const uint8_t P9N2__DAT_XSL_DEF_ITL_DIAL = 5 ;
+static const uint8_t P9N2__DAT_XSL_DEF_ITL_DIAL_LEN = 3 ;
+static const uint8_t P9N2__DAT_XSL_DEF_ITE_DIAL = 8 ;
+static const uint8_t P9N2__DAT_XSL_DEF_ITE_DIAL_LEN = 5 ;
+static const uint8_t P9N2__DAT_XSL_DEF_CTXM_DIAL = 24 ;
+static const uint8_t P9N2__DAT_XSL_DEF_CO_RTRY_LIM_DIAL = 61 ;
+static const uint8_t P9N2__DAT_XSL_DEF_CO_RTRY_LIM_DIAL_LEN = 2 ;
+static const uint8_t P9N2__DAT_XSL_DEF_DEFE_DIAL = 63 ;
+
+static const uint8_t P9N2_PU_NPU_DAT_XSL_EEI_ECMD_DIAL = 0 ;
+static const uint8_t P9N2_PU_NPU_DAT_XSL_EEI_ETYPE_DIAL = 2 ;
+static const uint8_t P9N2_PU_NPU_DAT_XSL_EEI_ETYPE_DIAL_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_DAT_XSL_EEI_RSPCODE_DIAL = 8 ;
+static const uint8_t P9N2_PU_NPU_DAT_XSL_EEI_RSPCODE_DIAL_LEN = 8 ;
+
+static const uint8_t P9N2__DAT_XSL_EEI_ECMD_DIAL = 0 ;
+static const uint8_t P9N2__DAT_XSL_EEI_ETYPE_DIAL = 2 ;
+static const uint8_t P9N2__DAT_XSL_EEI_ETYPE_DIAL_LEN = 6 ;
+static const uint8_t P9N2__DAT_XSL_EEI_RSPCODE_DIAL = 8 ;
+static const uint8_t P9N2__DAT_XSL_EEI_RSPCODE_DIAL_LEN = 8 ;
+
+static const uint8_t P9N2_PU_NPU_DAT_XSL_FEC_EVT_DIAL = 0 ;
+static const uint8_t P9N2_PU_NPU_DAT_XSL_FEC_ET_DIAL = 1 ;
+static const uint8_t P9N2_PU_NPU_DAT_XSL_FEC_ET_DIAL_LEN = 7 ;
+static const uint8_t P9N2_PU_NPU_DAT_XSL_FEC_EI_DIAL = 8 ;
+static const uint8_t P9N2_PU_NPU_DAT_XSL_FEC_EI_DIAL_LEN = 56 ;
+
+static const uint8_t P9N2__DAT_XSL_FEC_EVT_DIAL = 0 ;
+static const uint8_t P9N2__DAT_XSL_FEC_ET_DIAL = 1 ;
+static const uint8_t P9N2__DAT_XSL_FEC_ET_DIAL_LEN = 7 ;
+static const uint8_t P9N2__DAT_XSL_FEC_EI_DIAL = 8 ;
+static const uint8_t P9N2__DAT_XSL_FEC_EI_DIAL_LEN = 56 ;
+
+static const uint8_t P9N2_PU_NPU_DAT_XSL_GP_BITS_DIAL = 0 ;
+static const uint8_t P9N2_PU_NPU_DAT_XSL_GP_BITS_DIAL_LEN = 19 ;
+
+static const uint8_t P9N2__DAT_XSL_GP_BITS_DIAL = 0 ;
+static const uint8_t P9N2__DAT_XSL_GP_BITS_DIAL_LEN = 19 ;
+
+static const uint8_t P9N2_PU_NPU_DAT_XSL_INV_ERAT_WR_MLPID_DIAL = 0 ;
+static const uint8_t P9N2_PU_NPU_DAT_XSL_INV_ERAT_WR_MPID_DIAL = 1 ;
+static const uint8_t P9N2_PU_NPU_DAT_XSL_INV_ERAT_WR_MADDR_DIAL = 2 ;
+static const uint8_t P9N2_PU_NPU_DAT_XSL_INV_ERAT_WR_INVR_DIAL = 3 ;
+static const uint8_t P9N2_PU_NPU_DAT_XSL_INV_ERAT_WR_PRS_DIAL = 4 ;
+static const uint8_t P9N2_PU_NPU_DAT_XSL_INV_ERAT_WR_PAGESIZE_DIAL = 5 ;
+static const uint8_t P9N2_PU_NPU_DAT_XSL_INV_ERAT_WR_PAGESIZE_DIAL_LEN = 3 ;
+static const uint8_t P9N2_PU_NPU_DAT_XSL_INV_ERAT_WR_INVALL_DIAL = 8 ;
+static const uint8_t P9N2_PU_NPU_DAT_XSL_INV_ERAT_WR_SEGSIZE_DIAL = 10 ;
+static const uint8_t P9N2_PU_NPU_DAT_XSL_INV_ERAT_WR_INVEA_DIAL = 11 ;
+static const uint8_t P9N2_PU_NPU_DAT_XSL_INV_ERAT_WR_INVADDR_DIAL = 12 ;
+static const uint8_t P9N2_PU_NPU_DAT_XSL_INV_ERAT_WR_INVADDR_DIAL_LEN = 52 ;
+
+static const uint8_t P9N2__DAT_XSL_INV_ERAT_WR_MLPID_DIAL = 0 ;
+static const uint8_t P9N2__DAT_XSL_INV_ERAT_WR_MPID_DIAL = 1 ;
+static const uint8_t P9N2__DAT_XSL_INV_ERAT_WR_MADDR_DIAL = 2 ;
+static const uint8_t P9N2__DAT_XSL_INV_ERAT_WR_INVR_DIAL = 3 ;
+static const uint8_t P9N2__DAT_XSL_INV_ERAT_WR_PRS_DIAL = 4 ;
+static const uint8_t P9N2__DAT_XSL_INV_ERAT_WR_PAGESIZE_DIAL = 5 ;
+static const uint8_t P9N2__DAT_XSL_INV_ERAT_WR_PAGESIZE_DIAL_LEN = 3 ;
+static const uint8_t P9N2__DAT_XSL_INV_ERAT_WR_INVALL_DIAL = 8 ;
+static const uint8_t P9N2__DAT_XSL_INV_ERAT_WR_SEGSIZE_DIAL = 10 ;
+static const uint8_t P9N2__DAT_XSL_INV_ERAT_WR_INVEA_DIAL = 11 ;
+static const uint8_t P9N2__DAT_XSL_INV_ERAT_WR_INVADDR_DIAL = 12 ;
+static const uint8_t P9N2__DAT_XSL_INV_ERAT_WR_INVADDR_DIAL_LEN = 52 ;
+
+static const uint8_t P9N2_PU_NPU_DAT_XSL_INV_LPP_PID_DIAL = 12 ;
+static const uint8_t P9N2_PU_NPU_DAT_XSL_INV_LPP_PID_DIAL_LEN = 20 ;
+static const uint8_t P9N2_PU_NPU_DAT_XSL_INV_LPP_LPID_DIAL = 52 ;
+static const uint8_t P9N2_PU_NPU_DAT_XSL_INV_LPP_LPID_DIAL_LEN = 12 ;
+
+static const uint8_t P9N2__DAT_XSL_INV_LPP_PID_DIAL = 12 ;
+static const uint8_t P9N2__DAT_XSL_INV_LPP_PID_DIAL_LEN = 20 ;
+static const uint8_t P9N2__DAT_XSL_INV_LPP_LPID_DIAL = 52 ;
+static const uint8_t P9N2__DAT_XSL_INV_LPP_LPID_DIAL_LEN = 12 ;
+
+static const uint8_t P9N2_PU_NPU_DAT_XSL_PMON_PMONSEL0_DIAL = 3 ;
+static const uint8_t P9N2_PU_NPU_DAT_XSL_PMON_PMONSEL0_DIAL_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_DAT_XSL_PMON_PMONSEL1_DIAL = 11 ;
+static const uint8_t P9N2_PU_NPU_DAT_XSL_PMON_PMONSEL1_DIAL_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_DAT_XSL_PMON_PMONSEL2_DIAL = 19 ;
+static const uint8_t P9N2_PU_NPU_DAT_XSL_PMON_PMONSEL2_DIAL_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_DAT_XSL_PMON_PMONSEL3_DIAL = 27 ;
+static const uint8_t P9N2_PU_NPU_DAT_XSL_PMON_PMONSEL3_DIAL_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_DAT_XSL_PMON_PMONSEL4_DIAL = 35 ;
+static const uint8_t P9N2_PU_NPU_DAT_XSL_PMON_PMONSEL4_DIAL_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_DAT_XSL_PMON_PMONSEL5_DIAL = 43 ;
+static const uint8_t P9N2_PU_NPU_DAT_XSL_PMON_PMONSEL5_DIAL_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_DAT_XSL_PMON_PMONSEL6_DIAL = 51 ;
+static const uint8_t P9N2_PU_NPU_DAT_XSL_PMON_PMONSEL6_DIAL_LEN = 5 ;
+static const uint8_t P9N2_PU_NPU_DAT_XSL_PMON_PMONSEL7_DIAL = 59 ;
+static const uint8_t P9N2_PU_NPU_DAT_XSL_PMON_PMONSEL7_DIAL_LEN = 5 ;
+
+static const uint8_t P9N2__DAT_XSL_PMON_PMONSEL0_DIAL = 3 ;
+static const uint8_t P9N2__DAT_XSL_PMON_PMONSEL0_DIAL_LEN = 5 ;
+static const uint8_t P9N2__DAT_XSL_PMON_PMONSEL1_DIAL = 11 ;
+static const uint8_t P9N2__DAT_XSL_PMON_PMONSEL1_DIAL_LEN = 5 ;
+static const uint8_t P9N2__DAT_XSL_PMON_PMONSEL2_DIAL = 19 ;
+static const uint8_t P9N2__DAT_XSL_PMON_PMONSEL2_DIAL_LEN = 5 ;
+static const uint8_t P9N2__DAT_XSL_PMON_PMONSEL3_DIAL = 27 ;
+static const uint8_t P9N2__DAT_XSL_PMON_PMONSEL3_DIAL_LEN = 5 ;
+static const uint8_t P9N2__DAT_XSL_PMON_PMONSEL4_DIAL = 35 ;
+static const uint8_t P9N2__DAT_XSL_PMON_PMONSEL4_DIAL_LEN = 5 ;
+static const uint8_t P9N2__DAT_XSL_PMON_PMONSEL5_DIAL = 43 ;
+static const uint8_t P9N2__DAT_XSL_PMON_PMONSEL5_DIAL_LEN = 5 ;
+static const uint8_t P9N2__DAT_XSL_PMON_PMONSEL6_DIAL = 51 ;
+static const uint8_t P9N2__DAT_XSL_PMON_PMONSEL6_DIAL_LEN = 5 ;
+static const uint8_t P9N2__DAT_XSL_PMON_PMONSEL7_DIAL = 59 ;
+static const uint8_t P9N2__DAT_XSL_PMON_PMONSEL7_DIAL_LEN = 5 ;
+
+static const uint8_t P9N2_PU_NPU_DAT_XSL_RECOVER_RCVR_DIAL = 0 ;
+static const uint8_t P9N2_PU_NPU_DAT_XSL_RECOVER_MTYPE_DIAL = 4 ;
+static const uint8_t P9N2_PU_NPU_DAT_XSL_RECOVER_MTYPE_DIAL_LEN = 4 ;
+static const uint8_t P9N2_PU_NPU_DAT_XSL_RECOVER_MID_DIAL = 8 ;
+static const uint8_t P9N2_PU_NPU_DAT_XSL_RECOVER_MID_DIAL_LEN = 8 ;
+
+static const uint8_t P9N2__DAT_XSL_RECOVER_RCVR_DIAL = 0 ;
+static const uint8_t P9N2__DAT_XSL_RECOVER_MTYPE_DIAL = 4 ;
+static const uint8_t P9N2__DAT_XSL_RECOVER_MTYPE_DIAL_LEN = 4 ;
+static const uint8_t P9N2__DAT_XSL_RECOVER_MID_DIAL = 8 ;
+static const uint8_t P9N2__DAT_XSL_RECOVER_MID_DIAL_LEN = 8 ;
+
+static const uint8_t P9N2__NTL0_XSL_WRAP_CFG_XSLO_CLOCK_ENABLE = 0 ;
+static const uint8_t P9N2__NTL0_XSL_WRAP_CFG_RESERVED = 1 ;
+static const uint8_t P9N2__NTL0_XSL_WRAP_CFG_RESERVED_LEN = 7 ;
+
+static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_CFG_XSLO_CLOCK_ENABLE = 0 ;
+static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_CFG_RESERVED = 1 ;
+static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_CFG_RESERVED_LEN = 7 ;
+
+static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_MMIO_INVALIDATE_REQ_WHILE_1_INPROG = 0 ;
+static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_UNEXPECTED_ITAG_PORT_0 = 1 ;
+static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_UNEXPECTED_ITAG_PORT_1 = 2 ;
+static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_UNEXPECTED_RD_PEE_COMPLETION = 3 ;
+static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_UNEXPECTED_CO_RESP = 4 ;
+static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_XLAT_REQ_WHILE_SPAP_INVALID = 5 ;
+static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_INVALID_PEE = 6 ;
+static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_BLOOM_FILTER_ARY = 7 ;
+static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_RESERVED_XSLO = 8 ;
+static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_RESERVED_XSLO_LEN = 2 ;
+static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_TRKR0_SBE = 10 ;
+static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_TRKR1_SBE = 11 ;
+static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_IDB0_SBE = 12 ;
+static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_IDB1_SBE = 13 ;
+static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_FITA_SBE = 14 ;
+static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_TRKR0_UE = 15 ;
+static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_TRKR1_UE = 16 ;
+static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_IDB0_UE = 17 ;
+static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_IDB1_UE = 18 ;
+static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_FITA_UE = 19 ;
+static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_RQDB_PE = 20 ;
+static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_RESERVED0 = 21 ;
+static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_RSDB_PE = 22 ;
+static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_MDB0_PE = 23 ;
+static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_MDB1_PE = 24 ;
+static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_RESERVED1 = 25 ;
+static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_CTX0A_PE = 26 ;
+static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_CTX0B_PE = 27 ;
+static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_CTX1A_PE = 28 ;
+static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_CTX1B_PE = 29 ;
+static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_CTX2A_PE = 30 ;
+static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_CTX2B_PE = 31 ;
+static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_CTX3A_PE = 32 ;
+static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_CTX3B_PE = 33 ;
+static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_ERTA0A_PE = 34 ;
+static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_ERTA0B_PE = 35 ;
+static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_ERTA1A_PE = 36 ;
+static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_ERTA1B_PE = 37 ;
+static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_ERTA2A_PE = 38 ;
+static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_ERTA2B_PE = 39 ;
+static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_ERTA3A_PE = 40 ;
+static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_ERTA3B_PE = 41 ;
+static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_ERTAX0A_PE = 42 ;
+static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_ERTAX0B_PE = 43 ;
+static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_ERTAX1A_PE = 44 ;
+static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_ERTAX1B_PE = 45 ;
+static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_ERTAX2A_PE = 46 ;
+static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_ERTAX2B_PE = 47 ;
+static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_ERTAX3A_PE = 48 ;
+static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_ERTAX3B_PE = 49 ;
+static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_STLBI_PE = 50 ;
+static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_STLBI_OVERFLOW_ERR = 51 ;
+static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_CORESP_DATA_CE = 52 ;
+static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_CORESP_DATA_UE = 53 ;
+static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_CORESP_DATA_SUE = 54 ;
+static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_PEE_DATA_CE = 55 ;
+static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_PEE_DATA_UE = 56 ;
+static const uint8_t P9N2__NTL0_XSL_WRAP_ERROR_PEE_DATA_SUE = 57 ;
+
+static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_MMIO_INVALIDATE_REQ_WHILE_1_INPROG = 0 ;
+static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_UNEXPECTED_ITAG_PORT_0 = 1 ;
+static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_UNEXPECTED_ITAG_PORT_1 = 2 ;
+static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_UNEXPECTED_RD_PEE_COMPLETION = 3 ;
+static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_UNEXPECTED_CO_RESP = 4 ;
+static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_XLAT_REQ_WHILE_SPAP_INVALID = 5 ;
+static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_INVALID_PEE = 6 ;
+static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_BLOOM_FILTER_ARY = 7 ;
+static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_RESERVED_XSLO = 8 ;
+static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_RESERVED_XSLO_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_TRKR0_SBE = 10 ;
+static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_TRKR1_SBE = 11 ;
+static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_IDB0_SBE = 12 ;
+static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_IDB1_SBE = 13 ;
+static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_FITA_SBE = 14 ;
+static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_TRKR0_UE = 15 ;
+static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_TRKR1_UE = 16 ;
+static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_IDB0_UE = 17 ;
+static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_IDB1_UE = 18 ;
+static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_FITA_UE = 19 ;
+static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_RQDB_PE = 20 ;
+static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_RESERVED0 = 21 ;
+static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_RSDB_PE = 22 ;
+static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_MDB0_PE = 23 ;
+static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_MDB1_PE = 24 ;
+static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_RESERVED1 = 25 ;
+static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_CTX0A_PE = 26 ;
+static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_CTX0B_PE = 27 ;
+static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_CTX1A_PE = 28 ;
+static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_CTX1B_PE = 29 ;
+static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_CTX2A_PE = 30 ;
+static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_CTX2B_PE = 31 ;
+static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_CTX3A_PE = 32 ;
+static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_CTX3B_PE = 33 ;
+static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_ERTA0A_PE = 34 ;
+static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_ERTA0B_PE = 35 ;
+static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_ERTA1A_PE = 36 ;
+static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_ERTA1B_PE = 37 ;
+static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_ERTA2A_PE = 38 ;
+static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_ERTA2B_PE = 39 ;
+static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_ERTA3A_PE = 40 ;
+static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_ERTA3B_PE = 41 ;
+static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_ERTAX0A_PE = 42 ;
+static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_ERTAX0B_PE = 43 ;
+static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_ERTAX1A_PE = 44 ;
+static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_ERTAX1B_PE = 45 ;
+static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_ERTAX2A_PE = 46 ;
+static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_ERTAX2B_PE = 47 ;
+static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_ERTAX3A_PE = 48 ;
+static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_ERTAX3B_PE = 49 ;
+static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_STLBI_PE = 50 ;
+static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_STLBI_OVERFLOW_ERR = 51 ;
+static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_CORESP_DATA_CE = 52 ;
+static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_CORESP_DATA_UE = 53 ;
+static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_CORESP_DATA_SUE = 54 ;
+static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_PEE_DATA_CE = 55 ;
+static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_PEE_DATA_UE = 56 ;
+static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERROR_PEE_DATA_SUE = 57 ;
+
+static const uint8_t P9N2__NTL0_XSL_WRAP_ERR_MASK_DIAL = 0 ;
+static const uint8_t P9N2__NTL0_XSL_WRAP_ERR_MASK_DIAL_LEN = 58 ;
+
+static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERR_MASK_DIAL = 0 ;
+static const uint8_t P9N2_PU_NPU_NTL0_XSL_WRAP_ERR_MASK_DIAL_LEN = 58 ;
+
+static const uint8_t P9N2_PEC_XSTOP1_MASK_B = 0 ;
+static const uint8_t P9N2_PEC_XSTOP1_ALIGNED = 1 ;
+static const uint8_t P9N2_PEC_XSTOP1_TRIGGER_OPCG_ON = 2 ;
+static const uint8_t P9N2_PEC_XSTOP1_WAIT_ALLWAYS = 3 ;
+static const uint8_t P9N2_PEC_XSTOP1_PERV = 4 ;
+static const uint8_t P9N2_PEC_XSTOP1_UNIT1 = 5 ;
+static const uint8_t P9N2_PEC_XSTOP1_UNIT2 = 6 ;
+static const uint8_t P9N2_PEC_XSTOP1_UNIT3 = 7 ;
+static const uint8_t P9N2_PEC_XSTOP1_UNIT4 = 8 ;
+static const uint8_t P9N2_PEC_XSTOP1_UNIT5 = 9 ;
+static const uint8_t P9N2_PEC_XSTOP1_UNIT6 = 10 ;
+static const uint8_t P9N2_PEC_XSTOP1_UNIT7 = 11 ;
+static const uint8_t P9N2_PEC_XSTOP1_UNIT8 = 12 ;
+static const uint8_t P9N2_PEC_XSTOP1_UNIT9 = 13 ;
+static const uint8_t P9N2_PEC_XSTOP1_UNIT10 = 14 ;
+static const uint8_t P9N2_PEC_XSTOP1_WAIT_CYCLES = 48 ;
+static const uint8_t P9N2_PEC_XSTOP1_WAIT_CYCLES_LEN = 12 ;
+
+static const uint8_t P9N2_PEC_XSTOP2_MASK_B = 0 ;
+static const uint8_t P9N2_PEC_XSTOP2_ALIGNED = 1 ;
+static const uint8_t P9N2_PEC_XSTOP2_TRIGGER_OPCG_ON = 2 ;
+static const uint8_t P9N2_PEC_XSTOP2_WAIT_ALLWAYS = 3 ;
+static const uint8_t P9N2_PEC_XSTOP2_PERV = 4 ;
+static const uint8_t P9N2_PEC_XSTOP2_UNIT1 = 5 ;
+static const uint8_t P9N2_PEC_XSTOP2_UNIT2 = 6 ;
+static const uint8_t P9N2_PEC_XSTOP2_UNIT3 = 7 ;
+static const uint8_t P9N2_PEC_XSTOP2_UNIT4 = 8 ;
+static const uint8_t P9N2_PEC_XSTOP2_UNIT5 = 9 ;
+static const uint8_t P9N2_PEC_XSTOP2_UNIT6 = 10 ;
+static const uint8_t P9N2_PEC_XSTOP2_UNIT7 = 11 ;
+static const uint8_t P9N2_PEC_XSTOP2_UNIT8 = 12 ;
+static const uint8_t P9N2_PEC_XSTOP2_UNIT9 = 13 ;
+static const uint8_t P9N2_PEC_XSTOP2_UNIT10 = 14 ;
+static const uint8_t P9N2_PEC_XSTOP2_WAIT_CYCLES = 48 ;
+static const uint8_t P9N2_PEC_XSTOP2_WAIT_CYCLES_LEN = 12 ;
+
+static const uint8_t P9N2_PEC_XSTOP3_MASK_B = 0 ;
+static const uint8_t P9N2_PEC_XSTOP3_ALIGNED = 1 ;
+static const uint8_t P9N2_PEC_XSTOP3_TRIGGER_OPCG_ON = 2 ;
+static const uint8_t P9N2_PEC_XSTOP3_WAIT_ALLWAYS = 3 ;
+static const uint8_t P9N2_PEC_XSTOP3_PERV = 4 ;
+static const uint8_t P9N2_PEC_XSTOP3_UNIT1 = 5 ;
+static const uint8_t P9N2_PEC_XSTOP3_UNIT2 = 6 ;
+static const uint8_t P9N2_PEC_XSTOP3_UNIT3 = 7 ;
+static const uint8_t P9N2_PEC_XSTOP3_UNIT4 = 8 ;
+static const uint8_t P9N2_PEC_XSTOP3_UNIT5 = 9 ;
+static const uint8_t P9N2_PEC_XSTOP3_UNIT6 = 10 ;
+static const uint8_t P9N2_PEC_XSTOP3_UNIT7 = 11 ;
+static const uint8_t P9N2_PEC_XSTOP3_UNIT8 = 12 ;
+static const uint8_t P9N2_PEC_XSTOP3_UNIT9 = 13 ;
+static const uint8_t P9N2_PEC_XSTOP3_UNIT10 = 14 ;
+static const uint8_t P9N2_PEC_XSTOP3_WAIT_CYCLES = 48 ;
+static const uint8_t P9N2_PEC_XSTOP3_WAIT_CYCLES_LEN = 12 ;
+
+static const uint8_t P9N2_PEC_XSTOP_INTERRUPT_REG_XSTOP = 0 ;
+
+static const uint8_t P9N2_PU_NPU0_SM0_XTIMER_CONFIG_POCKET_LONG_RATE1 = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM0_XTIMER_CONFIG_POCKET_LONG_RATE1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM0_XTIMER_CONFIG_POCKET_LONG_RATE2 = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM0_XTIMER_CONFIG_POCKET_LONG_RATE2_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM0_XTIMER_CONFIG_POCKET_SHORT_RATE2 = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM0_XTIMER_CONFIG_POCKET_SHORT_RATE2_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM0_XTIMER_CONFIG_FWD_PROG_RATE2 = 14 ;
+static const uint8_t P9N2_PU_NPU0_SM0_XTIMER_CONFIG_FWD_PROG_RATE2_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM0_XTIMER_CONFIG_CTL_TICK = 20 ;
+static const uint8_t P9N2_PU_NPU0_SM0_XTIMER_CONFIG_CTL_TICK_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM0_XTIMER_CONFIG_INH0_TICK = 26 ;
+static const uint8_t P9N2_PU_NPU0_SM0_XTIMER_CONFIG_INH0_TICK_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM0_XTIMER_CONFIG_INH1_TICK = 32 ;
+static const uint8_t P9N2_PU_NPU0_SM0_XTIMER_CONFIG_INH1_TICK_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM0_XTIMER_CONFIG_NV_RESP_RATE1 = 38 ;
+static const uint8_t P9N2_PU_NPU0_SM0_XTIMER_CONFIG_NV_RESP_RATE1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM0_XTIMER_CONFIG_NV_RESP_RATE2 = 40 ;
+static const uint8_t P9N2_PU_NPU0_SM0_XTIMER_CONFIG_NV_RESP_RATE2_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM0_XTIMER_CONFIG_POCKET_SHORT_RATE1 = 46 ;
+static const uint8_t P9N2_PU_NPU0_SM0_XTIMER_CONFIG_POCKET_SHORT_RATE1_LEN = 2 ;
+
+static const uint8_t P9N2_PU_NPU2_SM3_XTIMER_CONFIG_POCKET_LONG_RATE1 = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM3_XTIMER_CONFIG_POCKET_LONG_RATE1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM3_XTIMER_CONFIG_POCKET_LONG_RATE2 = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM3_XTIMER_CONFIG_POCKET_LONG_RATE2_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM3_XTIMER_CONFIG_POCKET_SHORT_RATE2 = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM3_XTIMER_CONFIG_POCKET_SHORT_RATE2_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM3_XTIMER_CONFIG_FWD_PROG_RATE2 = 14 ;
+static const uint8_t P9N2_PU_NPU2_SM3_XTIMER_CONFIG_FWD_PROG_RATE2_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM3_XTIMER_CONFIG_CTL_TICK = 20 ;
+static const uint8_t P9N2_PU_NPU2_SM3_XTIMER_CONFIG_CTL_TICK_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM3_XTIMER_CONFIG_INH0_TICK = 26 ;
+static const uint8_t P9N2_PU_NPU2_SM3_XTIMER_CONFIG_INH0_TICK_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM3_XTIMER_CONFIG_INH1_TICK = 32 ;
+static const uint8_t P9N2_PU_NPU2_SM3_XTIMER_CONFIG_INH1_TICK_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM3_XTIMER_CONFIG_NV_RESP_RATE1 = 38 ;
+static const uint8_t P9N2_PU_NPU2_SM3_XTIMER_CONFIG_NV_RESP_RATE1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM3_XTIMER_CONFIG_NV_RESP_RATE2 = 40 ;
+static const uint8_t P9N2_PU_NPU2_SM3_XTIMER_CONFIG_NV_RESP_RATE2_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM3_XTIMER_CONFIG_POCKET_SHORT_RATE1 = 46 ;
+static const uint8_t P9N2_PU_NPU2_SM3_XTIMER_CONFIG_POCKET_SHORT_RATE1_LEN = 2 ;
+
+static const uint8_t P9N2_PU_NPU0_SM3_XTIMER_CONFIG_POCKET_LONG_RATE1 = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM3_XTIMER_CONFIG_POCKET_LONG_RATE1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM3_XTIMER_CONFIG_POCKET_LONG_RATE2 = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM3_XTIMER_CONFIG_POCKET_LONG_RATE2_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM3_XTIMER_CONFIG_POCKET_SHORT_RATE2 = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM3_XTIMER_CONFIG_POCKET_SHORT_RATE2_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM3_XTIMER_CONFIG_FWD_PROG_RATE2 = 14 ;
+static const uint8_t P9N2_PU_NPU0_SM3_XTIMER_CONFIG_FWD_PROG_RATE2_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM3_XTIMER_CONFIG_CTL_TICK = 20 ;
+static const uint8_t P9N2_PU_NPU0_SM3_XTIMER_CONFIG_CTL_TICK_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM3_XTIMER_CONFIG_INH0_TICK = 26 ;
+static const uint8_t P9N2_PU_NPU0_SM3_XTIMER_CONFIG_INH0_TICK_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM3_XTIMER_CONFIG_INH1_TICK = 32 ;
+static const uint8_t P9N2_PU_NPU0_SM3_XTIMER_CONFIG_INH1_TICK_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM3_XTIMER_CONFIG_NV_RESP_RATE1 = 38 ;
+static const uint8_t P9N2_PU_NPU0_SM3_XTIMER_CONFIG_NV_RESP_RATE1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM3_XTIMER_CONFIG_NV_RESP_RATE2 = 40 ;
+static const uint8_t P9N2_PU_NPU0_SM3_XTIMER_CONFIG_NV_RESP_RATE2_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM3_XTIMER_CONFIG_POCKET_SHORT_RATE1 = 46 ;
+static const uint8_t P9N2_PU_NPU0_SM3_XTIMER_CONFIG_POCKET_SHORT_RATE1_LEN = 2 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM0_XTIMER_CONFIG_POCKET_LONG_RATE1 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_XTIMER_CONFIG_POCKET_LONG_RATE1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_XTIMER_CONFIG_POCKET_LONG_RATE2 = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_XTIMER_CONFIG_POCKET_LONG_RATE2_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_XTIMER_CONFIG_POCKET_SHORT_RATE2 = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_XTIMER_CONFIG_POCKET_SHORT_RATE2_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_XTIMER_CONFIG_FWD_PROG_RATE2 = 14 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_XTIMER_CONFIG_FWD_PROG_RATE2_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_XTIMER_CONFIG_CTL_TICK = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_XTIMER_CONFIG_CTL_TICK_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_XTIMER_CONFIG_INH0_TICK = 26 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_XTIMER_CONFIG_INH0_TICK_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_XTIMER_CONFIG_INH1_TICK = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_XTIMER_CONFIG_INH1_TICK_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_XTIMER_CONFIG_NV_RESP_RATE1 = 38 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_XTIMER_CONFIG_NV_RESP_RATE1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_XTIMER_CONFIG_NV_RESP_RATE2 = 40 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_XTIMER_CONFIG_NV_RESP_RATE2_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_XTIMER_CONFIG_POCKET_SHORT_RATE1 = 46 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM0_XTIMER_CONFIG_POCKET_SHORT_RATE1_LEN = 2 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM1_XTIMER_CONFIG_POCKET_LONG_RATE1 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_XTIMER_CONFIG_POCKET_LONG_RATE1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_XTIMER_CONFIG_POCKET_LONG_RATE2 = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_XTIMER_CONFIG_POCKET_LONG_RATE2_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_XTIMER_CONFIG_POCKET_SHORT_RATE2 = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_XTIMER_CONFIG_POCKET_SHORT_RATE2_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_XTIMER_CONFIG_FWD_PROG_RATE2 = 14 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_XTIMER_CONFIG_FWD_PROG_RATE2_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_XTIMER_CONFIG_CTL_TICK = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_XTIMER_CONFIG_CTL_TICK_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_XTIMER_CONFIG_INH0_TICK = 26 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_XTIMER_CONFIG_INH0_TICK_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_XTIMER_CONFIG_INH1_TICK = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_XTIMER_CONFIG_INH1_TICK_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_XTIMER_CONFIG_NV_RESP_RATE1 = 38 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_XTIMER_CONFIG_NV_RESP_RATE1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_XTIMER_CONFIG_NV_RESP_RATE2 = 40 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_XTIMER_CONFIG_NV_RESP_RATE2_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_XTIMER_CONFIG_POCKET_SHORT_RATE1 = 46 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM1_XTIMER_CONFIG_POCKET_SHORT_RATE1_LEN = 2 ;
+
+static const uint8_t P9N2_PU_NPU2_SM1_XTIMER_CONFIG_POCKET_LONG_RATE1 = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM1_XTIMER_CONFIG_POCKET_LONG_RATE1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM1_XTIMER_CONFIG_POCKET_LONG_RATE2 = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM1_XTIMER_CONFIG_POCKET_LONG_RATE2_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM1_XTIMER_CONFIG_POCKET_SHORT_RATE2 = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM1_XTIMER_CONFIG_POCKET_SHORT_RATE2_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM1_XTIMER_CONFIG_FWD_PROG_RATE2 = 14 ;
+static const uint8_t P9N2_PU_NPU2_SM1_XTIMER_CONFIG_FWD_PROG_RATE2_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM1_XTIMER_CONFIG_CTL_TICK = 20 ;
+static const uint8_t P9N2_PU_NPU2_SM1_XTIMER_CONFIG_CTL_TICK_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM1_XTIMER_CONFIG_INH0_TICK = 26 ;
+static const uint8_t P9N2_PU_NPU2_SM1_XTIMER_CONFIG_INH0_TICK_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM1_XTIMER_CONFIG_INH1_TICK = 32 ;
+static const uint8_t P9N2_PU_NPU2_SM1_XTIMER_CONFIG_INH1_TICK_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM1_XTIMER_CONFIG_NV_RESP_RATE1 = 38 ;
+static const uint8_t P9N2_PU_NPU2_SM1_XTIMER_CONFIG_NV_RESP_RATE1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM1_XTIMER_CONFIG_NV_RESP_RATE2 = 40 ;
+static const uint8_t P9N2_PU_NPU2_SM1_XTIMER_CONFIG_NV_RESP_RATE2_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM1_XTIMER_CONFIG_POCKET_SHORT_RATE1 = 46 ;
+static const uint8_t P9N2_PU_NPU2_SM1_XTIMER_CONFIG_POCKET_SHORT_RATE1_LEN = 2 ;
+
+static const uint8_t P9N2_PU_NPU0_CTL_XTIMER_CONFIG_POCKET_LONG_RATE1 = 0 ;
+static const uint8_t P9N2_PU_NPU0_CTL_XTIMER_CONFIG_POCKET_LONG_RATE1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU0_CTL_XTIMER_CONFIG_POCKET_LONG_RATE2 = 2 ;
+static const uint8_t P9N2_PU_NPU0_CTL_XTIMER_CONFIG_POCKET_LONG_RATE2_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_CTL_XTIMER_CONFIG_POCKET_SHORT_RATE2 = 8 ;
+static const uint8_t P9N2_PU_NPU0_CTL_XTIMER_CONFIG_POCKET_SHORT_RATE2_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_CTL_XTIMER_CONFIG_FWD_PROG_RATE2 = 14 ;
+static const uint8_t P9N2_PU_NPU0_CTL_XTIMER_CONFIG_FWD_PROG_RATE2_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_CTL_XTIMER_CONFIG_CTL_TICK = 20 ;
+static const uint8_t P9N2_PU_NPU0_CTL_XTIMER_CONFIG_CTL_TICK_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_CTL_XTIMER_CONFIG_INH0_TICK = 26 ;
+static const uint8_t P9N2_PU_NPU0_CTL_XTIMER_CONFIG_INH0_TICK_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_CTL_XTIMER_CONFIG_INH1_TICK = 32 ;
+static const uint8_t P9N2_PU_NPU0_CTL_XTIMER_CONFIG_INH1_TICK_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_CTL_XTIMER_CONFIG_NV_RESP_RATE1 = 38 ;
+static const uint8_t P9N2_PU_NPU0_CTL_XTIMER_CONFIG_NV_RESP_RATE1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU0_CTL_XTIMER_CONFIG_NV_RESP_RATE2 = 40 ;
+static const uint8_t P9N2_PU_NPU0_CTL_XTIMER_CONFIG_NV_RESP_RATE2_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_CTL_XTIMER_CONFIG_POCKET_SHORT_RATE1 = 46 ;
+static const uint8_t P9N2_PU_NPU0_CTL_XTIMER_CONFIG_POCKET_SHORT_RATE1_LEN = 2 ;
+
+static const uint8_t P9N2_PU_NPU2_SM0_XTIMER_CONFIG_POCKET_LONG_RATE1 = 0 ;
+static const uint8_t P9N2_PU_NPU2_SM0_XTIMER_CONFIG_POCKET_LONG_RATE1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM0_XTIMER_CONFIG_POCKET_LONG_RATE2 = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM0_XTIMER_CONFIG_POCKET_LONG_RATE2_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM0_XTIMER_CONFIG_POCKET_SHORT_RATE2 = 8 ;
+static const uint8_t P9N2_PU_NPU2_SM0_XTIMER_CONFIG_POCKET_SHORT_RATE2_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM0_XTIMER_CONFIG_FWD_PROG_RATE2 = 14 ;
+static const uint8_t P9N2_PU_NPU2_SM0_XTIMER_CONFIG_FWD_PROG_RATE2_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM0_XTIMER_CONFIG_CTL_TICK = 20 ;
+static const uint8_t P9N2_PU_NPU2_SM0_XTIMER_CONFIG_CTL_TICK_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM0_XTIMER_CONFIG_INH0_TICK = 26 ;
+static const uint8_t P9N2_PU_NPU2_SM0_XTIMER_CONFIG_INH0_TICK_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM0_XTIMER_CONFIG_INH1_TICK = 32 ;
+static const uint8_t P9N2_PU_NPU2_SM0_XTIMER_CONFIG_INH1_TICK_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM0_XTIMER_CONFIG_NV_RESP_RATE1 = 38 ;
+static const uint8_t P9N2_PU_NPU2_SM0_XTIMER_CONFIG_NV_RESP_RATE1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_SM0_XTIMER_CONFIG_NV_RESP_RATE2 = 40 ;
+static const uint8_t P9N2_PU_NPU2_SM0_XTIMER_CONFIG_NV_RESP_RATE2_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_SM0_XTIMER_CONFIG_POCKET_SHORT_RATE1 = 46 ;
+static const uint8_t P9N2_PU_NPU2_SM0_XTIMER_CONFIG_POCKET_SHORT_RATE1_LEN = 2 ;
+
+static const uint8_t P9N2_PU_NPU2_CTL_XTIMER_CONFIG_POCKET_LONG_RATE1 = 0 ;
+static const uint8_t P9N2_PU_NPU2_CTL_XTIMER_CONFIG_POCKET_LONG_RATE1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_CTL_XTIMER_CONFIG_POCKET_LONG_RATE2 = 2 ;
+static const uint8_t P9N2_PU_NPU2_CTL_XTIMER_CONFIG_POCKET_LONG_RATE2_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_CTL_XTIMER_CONFIG_POCKET_SHORT_RATE2 = 8 ;
+static const uint8_t P9N2_PU_NPU2_CTL_XTIMER_CONFIG_POCKET_SHORT_RATE2_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_CTL_XTIMER_CONFIG_FWD_PROG_RATE2 = 14 ;
+static const uint8_t P9N2_PU_NPU2_CTL_XTIMER_CONFIG_FWD_PROG_RATE2_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_CTL_XTIMER_CONFIG_CTL_TICK = 20 ;
+static const uint8_t P9N2_PU_NPU2_CTL_XTIMER_CONFIG_CTL_TICK_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_CTL_XTIMER_CONFIG_INH0_TICK = 26 ;
+static const uint8_t P9N2_PU_NPU2_CTL_XTIMER_CONFIG_INH0_TICK_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_CTL_XTIMER_CONFIG_INH1_TICK = 32 ;
+static const uint8_t P9N2_PU_NPU2_CTL_XTIMER_CONFIG_INH1_TICK_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_CTL_XTIMER_CONFIG_NV_RESP_RATE1 = 38 ;
+static const uint8_t P9N2_PU_NPU2_CTL_XTIMER_CONFIG_NV_RESP_RATE1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU2_CTL_XTIMER_CONFIG_NV_RESP_RATE2 = 40 ;
+static const uint8_t P9N2_PU_NPU2_CTL_XTIMER_CONFIG_NV_RESP_RATE2_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU2_CTL_XTIMER_CONFIG_POCKET_SHORT_RATE1 = 46 ;
+static const uint8_t P9N2_PU_NPU2_CTL_XTIMER_CONFIG_POCKET_SHORT_RATE1_LEN = 2 ;
+
+static const uint8_t P9N2_PU_NPU0_SM1_XTIMER_CONFIG_POCKET_LONG_RATE1 = 0 ;
+static const uint8_t P9N2_PU_NPU0_SM1_XTIMER_CONFIG_POCKET_LONG_RATE1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM1_XTIMER_CONFIG_POCKET_LONG_RATE2 = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM1_XTIMER_CONFIG_POCKET_LONG_RATE2_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM1_XTIMER_CONFIG_POCKET_SHORT_RATE2 = 8 ;
+static const uint8_t P9N2_PU_NPU0_SM1_XTIMER_CONFIG_POCKET_SHORT_RATE2_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM1_XTIMER_CONFIG_FWD_PROG_RATE2 = 14 ;
+static const uint8_t P9N2_PU_NPU0_SM1_XTIMER_CONFIG_FWD_PROG_RATE2_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM1_XTIMER_CONFIG_CTL_TICK = 20 ;
+static const uint8_t P9N2_PU_NPU0_SM1_XTIMER_CONFIG_CTL_TICK_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM1_XTIMER_CONFIG_INH0_TICK = 26 ;
+static const uint8_t P9N2_PU_NPU0_SM1_XTIMER_CONFIG_INH0_TICK_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM1_XTIMER_CONFIG_INH1_TICK = 32 ;
+static const uint8_t P9N2_PU_NPU0_SM1_XTIMER_CONFIG_INH1_TICK_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM1_XTIMER_CONFIG_NV_RESP_RATE1 = 38 ;
+static const uint8_t P9N2_PU_NPU0_SM1_XTIMER_CONFIG_NV_RESP_RATE1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU0_SM1_XTIMER_CONFIG_NV_RESP_RATE2 = 40 ;
+static const uint8_t P9N2_PU_NPU0_SM1_XTIMER_CONFIG_NV_RESP_RATE2_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU0_SM1_XTIMER_CONFIG_POCKET_SHORT_RATE1 = 46 ;
+static const uint8_t P9N2_PU_NPU0_SM1_XTIMER_CONFIG_POCKET_SHORT_RATE1_LEN = 2 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_CTL_XTIMER_CONFIG_POCKET_LONG_RATE1 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_XTIMER_CONFIG_POCKET_LONG_RATE1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_XTIMER_CONFIG_POCKET_LONG_RATE2 = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_XTIMER_CONFIG_POCKET_LONG_RATE2_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_XTIMER_CONFIG_POCKET_SHORT_RATE2 = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_XTIMER_CONFIG_POCKET_SHORT_RATE2_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_XTIMER_CONFIG_FWD_PROG_RATE2 = 14 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_XTIMER_CONFIG_FWD_PROG_RATE2_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_XTIMER_CONFIG_CTL_TICK = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_XTIMER_CONFIG_CTL_TICK_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_XTIMER_CONFIG_INH0_TICK = 26 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_XTIMER_CONFIG_INH0_TICK_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_XTIMER_CONFIG_INH1_TICK = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_XTIMER_CONFIG_INH1_TICK_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_XTIMER_CONFIG_NV_RESP_RATE1 = 38 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_XTIMER_CONFIG_NV_RESP_RATE1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_XTIMER_CONFIG_NV_RESP_RATE2 = 40 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_XTIMER_CONFIG_NV_RESP_RATE2_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_XTIMER_CONFIG_POCKET_SHORT_RATE1 = 46 ;
+static const uint8_t P9N2_PU_NPU_MSC_CTL_XTIMER_CONFIG_POCKET_SHORT_RATE1_LEN = 2 ;
+
+static const uint8_t P9N2_PU_NPU_MSC_SM3_XTIMER_CONFIG_POCKET_LONG_RATE1 = 0 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_XTIMER_CONFIG_POCKET_LONG_RATE1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_XTIMER_CONFIG_POCKET_LONG_RATE2 = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_XTIMER_CONFIG_POCKET_LONG_RATE2_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_XTIMER_CONFIG_POCKET_SHORT_RATE2 = 8 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_XTIMER_CONFIG_POCKET_SHORT_RATE2_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_XTIMER_CONFIG_FWD_PROG_RATE2 = 14 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_XTIMER_CONFIG_FWD_PROG_RATE2_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_XTIMER_CONFIG_CTL_TICK = 20 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_XTIMER_CONFIG_CTL_TICK_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_XTIMER_CONFIG_INH0_TICK = 26 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_XTIMER_CONFIG_INH0_TICK_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_XTIMER_CONFIG_INH1_TICK = 32 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_XTIMER_CONFIG_INH1_TICK_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_XTIMER_CONFIG_NV_RESP_RATE1 = 38 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_XTIMER_CONFIG_NV_RESP_RATE1_LEN = 2 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_XTIMER_CONFIG_NV_RESP_RATE2 = 40 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_XTIMER_CONFIG_NV_RESP_RATE2_LEN = 6 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_XTIMER_CONFIG_POCKET_SHORT_RATE1 = 46 ;
+static const uint8_t P9N2_PU_NPU_MSC_SM3_XTIMER_CONFIG_POCKET_SHORT_RATE1_LEN = 2 ;
+
+static const uint8_t P9N2_PEC_XTRA_TRACE_MODE_DATA = 0 ;
+static const uint8_t P9N2_PEC_XTRA_TRACE_MODE_DATA_LEN = 42 ;
+
+static const uint8_t P9N2_PU_XTRA_TRACE_MODE_DATA = 0 ;
+static const uint8_t P9N2_PU_XTRA_TRACE_MODE_DATA_LEN = 42 ;
+
+static const uint8_t P9N2__SM2_XTS_ATRMISS_ADDR = 15 ;
+static const uint8_t P9N2__SM2_XTS_ATRMISS_ADDR_LEN = 37 ;
+static const uint8_t P9N2__SM2_XTS_ATRMISS_FLAG_OTHER = 54 ;
+static const uint8_t P9N2__SM2_XTS_ATRMISS_FLAG_PREF = 55 ;
+static const uint8_t P9N2__SM2_XTS_ATRMISS_FLAG_DMD = 56 ;
+static const uint8_t P9N2__SM2_XTS_ATRMISS_FLAG_MAP = 57 ;
+static const uint8_t P9N2__SM2_XTS_ATRMISS_FLAG_FENCE = 58 ;
+static const uint8_t P9N2__SM2_XTS_ATRMISS_RETIRE = 59 ;
+static const uint8_t P9N2__SM2_XTS_ATRMISS_IRQENA = 60 ;
+static const uint8_t P9N2__SM2_XTS_ATRMISS_SECOND = 61 ;
+static const uint8_t P9N2__SM2_XTS_ATRMISS_TRIGGERED = 62 ;
+static const uint8_t P9N2__SM2_XTS_ATRMISS_ENA = 63 ;
+
+static const uint8_t P9N2__SM2_XTS_ATRMISS2_ATRMISS_GPA = 27 ;
+static const uint8_t P9N2__SM2_XTS_ATRMISS2_ATRMISS_BDF = 28 ;
+static const uint8_t P9N2__SM2_XTS_ATRMISS2_ATRMISS_BDF_LEN = 16 ;
+static const uint8_t P9N2__SM2_XTS_ATRMISS2_ATRMISS_PASID = 44 ;
+static const uint8_t P9N2__SM2_XTS_ATRMISS2_ATRMISS_PASID_LEN = 20 ;
+
+static const uint8_t P9N2__SM2_XTS_ATRMISSCLR_ATRMISS_ADDR = 15 ;
+static const uint8_t P9N2__SM2_XTS_ATRMISSCLR_ATRMISS_ADDR_LEN = 37 ;
+static const uint8_t P9N2__SM2_XTS_ATRMISSCLR_ATRMISS_FLAG_OTHER = 54 ;
+static const uint8_t P9N2__SM2_XTS_ATRMISSCLR_ATRMISS_FLAG_PREF = 55 ;
+static const uint8_t P9N2__SM2_XTS_ATRMISSCLR_ATRMISS_FLAG_DMD = 56 ;
+static const uint8_t P9N2__SM2_XTS_ATRMISSCLR_ATRMISS_FLAG_MAP = 57 ;
+static const uint8_t P9N2__SM2_XTS_ATRMISSCLR_ATRMISS_FLAG_FENCE = 58 ;
+static const uint8_t P9N2__SM2_XTS_ATRMISSCLR_ATRMISS_RETIRE = 59 ;
+static const uint8_t P9N2__SM2_XTS_ATRMISSCLR_ATRMISS_IRQENA = 60 ;
+static const uint8_t P9N2__SM2_XTS_ATRMISSCLR_ATRMISS_SECOND = 61 ;
+static const uint8_t P9N2__SM2_XTS_ATRMISSCLR_ATRMISS_TRIGGERED = 62 ;
+static const uint8_t P9N2__SM2_XTS_ATRMISSCLR_ATRMISS_ENA = 63 ;
+
+static const uint8_t P9N2__SM3_XTS_ATSD_HYP0_MSRHV = 51 ;
+static const uint8_t P9N2__SM3_XTS_ATSD_HYP0_LPARID = 52 ;
+static const uint8_t P9N2__SM3_XTS_ATSD_HYP0_LPARID_LEN = 12 ;
+
+static const uint8_t P9N2__SM3_XTS_ATSD_HYP1_MSRHV = 51 ;
+static const uint8_t P9N2__SM3_XTS_ATSD_HYP1_LPARID = 52 ;
+static const uint8_t P9N2__SM3_XTS_ATSD_HYP1_LPARID_LEN = 12 ;
+
+static const uint8_t P9N2__SM3_XTS_ATSD_HYP2_MSRHV = 51 ;
+static const uint8_t P9N2__SM3_XTS_ATSD_HYP2_LPARID = 52 ;
+static const uint8_t P9N2__SM3_XTS_ATSD_HYP2_LPARID_LEN = 12 ;
+
+static const uint8_t P9N2__SM3_XTS_ATSD_HYP3_MSRHV = 51 ;
+static const uint8_t P9N2__SM3_XTS_ATSD_HYP3_LPARID = 52 ;
+static const uint8_t P9N2__SM3_XTS_ATSD_HYP3_LPARID_LEN = 12 ;
+
+static const uint8_t P9N2__SM3_XTS_ATSD_HYP4_MSRHV = 51 ;
+static const uint8_t P9N2__SM3_XTS_ATSD_HYP4_LPARID = 52 ;
+static const uint8_t P9N2__SM3_XTS_ATSD_HYP4_LPARID_LEN = 12 ;
+
+static const uint8_t P9N2__SM3_XTS_ATSD_HYP5_MSRHV = 51 ;
+static const uint8_t P9N2__SM3_XTS_ATSD_HYP5_LPARID = 52 ;
+static const uint8_t P9N2__SM3_XTS_ATSD_HYP5_LPARID_LEN = 12 ;
+
+static const uint8_t P9N2__SM3_XTS_ATSD_HYP6_MSRHV = 51 ;
+static const uint8_t P9N2__SM3_XTS_ATSD_HYP6_LPARID = 52 ;
+static const uint8_t P9N2__SM3_XTS_ATSD_HYP6_LPARID_LEN = 12 ;
+
+static const uint8_t P9N2__SM3_XTS_ATSD_HYP7_MSRHV = 51 ;
+static const uint8_t P9N2__SM3_XTS_ATSD_HYP7_LPARID = 52 ;
+static const uint8_t P9N2__SM3_XTS_ATSD_HYP7_LPARID_LEN = 12 ;
+
+static const uint8_t P9N2__SM2_XTS_CONFIG_BRAZOS = 0 ;
+static const uint8_t P9N2__SM2_XTS_CONFIG_MMIOSD = 1 ;
+static const uint8_t P9N2__SM2_XTS_CONFIG_BIG_RSP = 2 ;
+static const uint8_t P9N2__SM2_XTS_CONFIG_CHOP1G = 3 ;
+static const uint8_t P9N2__SM2_XTS_CONFIG_DIS_NCNP = 4 ;
+static const uint8_t P9N2__SM2_XTS_CONFIG_OVR_PM = 5 ;
+static const uint8_t P9N2__SM2_XTS_CONFIG_TRY_ATR_RO = 6 ;
+static const uint8_t P9N2__SM2_XTS_CONFIG_SPLURGE = 7 ;
+static const uint8_t P9N2__SM2_XTS_CONFIG_LIM_PS = 8 ;
+static const uint8_t P9N2__SM2_XTS_CONFIG_PREF2DMD = 9 ;
+static const uint8_t P9N2__SM2_XTS_CONFIG_PREFEVOD = 10 ;
+static const uint8_t P9N2__SM2_XTS_CONFIG_EAINJ = 11 ;
+static const uint8_t P9N2__SM2_XTS_CONFIG_SPL_ONLY = 12 ;
+static const uint8_t P9N2__SM2_XTS_CONFIG_BYPASS_CO = 13 ;
+static const uint8_t P9N2__SM2_XTS_CONFIG_UNUSED = 14 ;
+static const uint8_t P9N2__SM2_XTS_CONFIG_OPENCAPI = 15 ;
+static const uint8_t P9N2__SM2_XTS_CONFIG_TLBIE_DEC_RATE = 16 ;
+static const uint8_t P9N2__SM2_XTS_CONFIG_TLBIE_DEC_RATE_LEN = 8 ;
+static const uint8_t P9N2__SM2_XTS_CONFIG_TLBIE_INC_RATE = 24 ;
+static const uint8_t P9N2__SM2_XTS_CONFIG_TLBIE_INC_RATE_LEN = 8 ;
+static const uint8_t P9N2__SM2_XTS_CONFIG_TLBIE_CNT_THRESH = 32 ;
+static const uint8_t P9N2__SM2_XTS_CONFIG_TLBIE_CNT_THRESH_LEN = 8 ;
+static const uint8_t P9N2__SM2_XTS_CONFIG_WAIT_MISS = 40 ;
+static const uint8_t P9N2__SM2_XTS_CONFIG_PREF_TIMEOUT = 41 ;
+static const uint8_t P9N2__SM2_XTS_CONFIG_PREF_TIMEOUT_LEN = 3 ;
+static const uint8_t P9N2__SM2_XTS_CONFIG_PREF_DEPTH = 44 ;
+static const uint8_t P9N2__SM2_XTS_CONFIG_PREF_DEPTH_LEN = 4 ;
+static const uint8_t P9N2__SM2_XTS_CONFIG_PREF_THRSH0 = 48 ;
+static const uint8_t P9N2__SM2_XTS_CONFIG_PREF_THRSH0_LEN = 4 ;
+static const uint8_t P9N2__SM2_XTS_CONFIG_PREF_THRSH1 = 52 ;
+static const uint8_t P9N2__SM2_XTS_CONFIG_PREF_THRSH1_LEN = 4 ;
+static const uint8_t P9N2__SM2_XTS_CONFIG_PREF_THRSH2 = 56 ;
+static const uint8_t P9N2__SM2_XTS_CONFIG_PREF_THRSH2_LEN = 4 ;
+static const uint8_t P9N2__SM2_XTS_CONFIG_PREF_THRSH3 = 60 ;
+static const uint8_t P9N2__SM2_XTS_CONFIG_PREF_THRSH3_LEN = 4 ;
+
+static const uint8_t P9N2__SM2_XTS_CONFIG2_PERF_ENABLE = 0 ;
+static const uint8_t P9N2__SM2_XTS_CONFIG2_PERF_RESETMODE = 1 ;
+static const uint8_t P9N2__SM2_XTS_CONFIG2_PERF_FREEZEMODE = 2 ;
+static const uint8_t P9N2__SM2_XTS_CONFIG2_PERF_DISABLE_PMISC = 3 ;
+static const uint8_t P9N2__SM2_XTS_CONFIG2_PERF_PMISC_MODE = 4 ;
+static const uint8_t P9N2__SM2_XTS_CONFIG2_PERF_CASCADE = 5 ;
+static const uint8_t P9N2__SM2_XTS_CONFIG2_PERF_CASCADE_LEN = 3 ;
+static const uint8_t P9N2__SM2_XTS_CONFIG2_PERF_PRESCALE_C0 = 8 ;
+static const uint8_t P9N2__SM2_XTS_CONFIG2_PERF_PRESCALE_C0_LEN = 2 ;
+static const uint8_t P9N2__SM2_XTS_CONFIG2_PERF_PRESCALE_C1 = 10 ;
+static const uint8_t P9N2__SM2_XTS_CONFIG2_PERF_PRESCALE_C1_LEN = 2 ;
+static const uint8_t P9N2__SM2_XTS_CONFIG2_PERF_PRESCALE_C2 = 12 ;
+static const uint8_t P9N2__SM2_XTS_CONFIG2_PERF_PRESCALE_C2_LEN = 2 ;
+static const uint8_t P9N2__SM2_XTS_CONFIG2_PERF_PRESCALE_C3 = 14 ;
+static const uint8_t P9N2__SM2_XTS_CONFIG2_PERF_PRESCALE_C3_LEN = 2 ;
+static const uint8_t P9N2__SM2_XTS_CONFIG2_PERF_EVENT0 = 16 ;
+static const uint8_t P9N2__SM2_XTS_CONFIG2_PERF_EVENT0_LEN = 8 ;
+static const uint8_t P9N2__SM2_XTS_CONFIG2_PERF_EVENT1 = 24 ;
+static const uint8_t P9N2__SM2_XTS_CONFIG2_PERF_EVENT1_LEN = 8 ;
+static const uint8_t P9N2__SM2_XTS_CONFIG2_PERF_EVENT2 = 32 ;
+static const uint8_t P9N2__SM2_XTS_CONFIG2_PERF_EVENT2_LEN = 8 ;
+static const uint8_t P9N2__SM2_XTS_CONFIG2_PERF_EVENT3 = 40 ;
+static const uint8_t P9N2__SM2_XTS_CONFIG2_PERF_EVENT3_LEN = 8 ;
+static const uint8_t P9N2__SM2_XTS_CONFIG2_RADDR_BND = 48 ;
+static const uint8_t P9N2__SM2_XTS_CONFIG2_NO_FLUSH_ENA = 49 ;
+static const uint8_t P9N2__SM2_XTS_CONFIG2_MAP_ILOCK = 50 ;
+static const uint8_t P9N2__SM2_XTS_CONFIG2_ADJUST_PLS_RATE = 51 ;
+static const uint8_t P9N2__SM2_XTS_CONFIG2_TLBIE_HV_EN = 52 ;
+static const uint8_t P9N2__SM2_XTS_CONFIG2_TLBIE_PACING_CNT_EN = 53 ;
+static const uint8_t P9N2__SM2_XTS_CONFIG2_XSL1_ENA = 54 ;
+static const uint8_t P9N2__SM2_XTS_CONFIG2_XSL2_ENA = 55 ;
+static const uint8_t P9N2__SM2_XTS_CONFIG2_ATSD_TIMEOUT = 56 ;
+static const uint8_t P9N2__SM2_XTS_CONFIG2_ATSD_TIMEOUT_LEN = 4 ;
+static const uint8_t P9N2__SM2_XTS_CONFIG2_ATR_TIMEOUT = 60 ;
+static const uint8_t P9N2__SM2_XTS_CONFIG2_ATR_TIMEOUT_LEN = 4 ;
+
+static const uint8_t P9N2__SM2_XTS_CONFIG3_CAP_RESERVE = 0 ;
+static const uint8_t P9N2__SM2_XTS_CONFIG3_CAP_RESERVE_LEN = 4 ;
+static const uint8_t P9N2__SM2_XTS_CONFIG3_ATSD_ALIGN = 4 ;
+static const uint8_t P9N2__SM2_XTS_CONFIG3_UNUSED = 5 ;
+static const uint8_t P9N2__SM2_XTS_CONFIG3_UNUSED_LEN = 59 ;
+
+static const uint8_t P9N2__SM2_XTS_PMU_CNT_CNT0 = 0 ;
+static const uint8_t P9N2__SM2_XTS_PMU_CNT_CNT0_LEN = 16 ;
+static const uint8_t P9N2__SM2_XTS_PMU_CNT_CNT1 = 16 ;
+static const uint8_t P9N2__SM2_XTS_PMU_CNT_CNT1_LEN = 16 ;
+static const uint8_t P9N2__SM2_XTS_PMU_CNT_CNT2 = 32 ;
+static const uint8_t P9N2__SM2_XTS_PMU_CNT_CNT2_LEN = 16 ;
+static const uint8_t P9N2__SM2_XTS_PMU_CNT_CNT3 = 48 ;
+static const uint8_t P9N2__SM2_XTS_PMU_CNT_CNT3_LEN = 16 ;
+
+#endif
+
diff --git a/src/import/chips/p9/common/include/p9n2_obus_scom_addresses.H b/src/import/chips/p9/common/include/p9n2_obus_scom_addresses.H
new file mode 100644
index 000000000..98037ec37
--- /dev/null
+++ b/src/import/chips/p9/common/include/p9n2_obus_scom_addresses.H
@@ -0,0 +1,12245 @@
+/* IBM_PROLOG_BEGIN_TAG */
+/* This is an automatically generated prolog. */
+/* */
+/* $Source: src/import/chips/p9/common/include/p9n2_obus_scom_addresses.H $ */
+/* */
+/* OpenPOWER HostBoot Project */
+/* */
+/* Contributors Listed Below - COPYRIGHT 2017 */
+/* [+] International Business Machines Corp. */
+/* */
+/* */
+/* Licensed under the Apache License, Version 2.0 (the "License"); */
+/* you may not use this file except in compliance with the License. */
+/* You may obtain a copy of the License at */
+/* */
+/* http://www.apache.org/licenses/LICENSE-2.0 */
+/* */
+/* Unless required by applicable law or agreed to in writing, software */
+/* distributed under the License is distributed on an "AS IS" BASIS, */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */
+/* implied. See the License for the specific language governing */
+/* permissions and limitations under the License. */
+/* */
+/* IBM_PROLOG_END_TAG */
+///
+/// @file p9_obus_scom_addresses.H
+/// @brief Defines constants for scom addresses
+///
+// *HWP HWP Owner: Ben Gass <bgass@us.ibm.com>
+// *HWP FW Owner: Thi Tran <thi@us.ibm.com>
+// *HWP Team: SOA
+// *HWP Level: 1
+// *HWP Consumed by: FSP:HB:HS:OCC:SBE:CME:SGPE:PGPE:FPPE:IPPE
+
+/*---------------------------------------------------------------
+ *
+ *---------------------------------------------------------------
+ *
+ *---------------------------------------------------------------
+ */
+
+#ifndef __P9N2_OBUS_SCOM_ADDRESSES_H
+#define __P9N2_OBUS_SCOM_ADDRESSES_H
+
+#include <stdint.h>
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_FIR_MASK_REG = 0x09010C03ull;
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_FIR_MASK_REG_AND = 0x09010C04ull;
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_FIR_MASK_REG_OR = 0x09010C05ull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_FIR_MASK_REG = 0x09010C03ull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_FIR_MASK_REG_AND = 0x09010C04ull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_FIR_MASK_REG_OR = 0x09010C05ull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_FIR_REG = 0x09010C00ull;
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_FIR_REG_AND = 0x09010C01ull;
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_FIR_REG_OR = 0x09010C02ull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_FIR_REG = 0x09010C00ull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_FIR_REG_AND = 0x09010C01ull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_FIR_REG_OR = 0x09010C02ull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_FIR_ACTION0_REG = 0x09010C06ull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_FIR_ACTION0_REG = 0x09010C06ull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_FIR_ACTION1_REG = 0x09010C07ull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_FIR_ACTION1_REG = 0x09010C07ull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_FIR_WOF_REG = 0x09010C08ull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_FIR_WOF_REG = 0x09010C08ull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL = 0x8002480009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL = 0x8002480009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL = 0x8002500009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL = 0x8002500009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL = 0x8002580009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL = 0x8002580009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL5_EO_PL = 0x8002600009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL5_EO_PL = 0x8002600009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL = 0x8002400009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL = 0x8002400009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL = 0x8002200009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL = 0x8002200009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_MODE2_EO_PL = 0x8002280009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_MODE2_EO_PL = 0x8002280009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL = 0x8002300009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL = 0x8002300009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_MODE4_EO_PL = 0x8002380009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_MODE4_EO_PL = 0x8002380009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_STAT1_EO_PL = 0x8002680009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_STAT1_EO_PL = 0x8002680009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_STAT1_O_PL = 0x8003180009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_STAT1_O_PL = 0x8003180009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL = 0x8002700009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL = 0x8002700009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL = 0x8002780009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL = 0x8002780009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_STAT4_EO_PL = 0x8002800009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_STAT4_EO_PL = 0x8002800009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL10_O_PL = 0x8000C80009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL10_O_PL = 0x8000C80009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL = 0x8000080009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL = 0x8000080009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_O_PL = 0x8000800009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_O_PL = 0x8000800009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL = 0x8000100009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL = 0x8000100009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_O_PL = 0x8000880009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_O_PL = 0x8000880009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_EO_PL = 0x8000180009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_EO_PL = 0x8000180009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_O_PL = 0x8000900009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_O_PL = 0x8000900009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_EO_PL = 0x8000200009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_EO_PL = 0x8000200009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_O_PL = 0x8000980009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_O_PL = 0x8000980009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL = 0x8000280009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL = 0x8000280009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_O_PL = 0x8000A00009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_O_PL = 0x8000A00009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_EO_PL = 0x8000300009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_EO_PL = 0x8000300009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_O_PL = 0x8000A80009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_O_PL = 0x8000A80009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL7_EO_PL = 0x8000380009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL7_EO_PL = 0x8000380009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL7_O_PL = 0x8000B00009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL7_O_PL = 0x8000B00009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL8_EO_PL = 0x8000400009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL8_EO_PL = 0x8000400009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL8_O_PL = 0x8000B80009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL8_O_PL = 0x8000B80009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL9_O_PL = 0x8000C00009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL9_O_PL = 0x8000C00009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL = 0x8000000009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x8000000009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_FIR_ERROR_INJECT_PL = 0x8002180009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_FIR_ERROR_INJECT_PL = 0x8002180009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_FIR_MASK_PL = 0x8002100009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_FIR_MASK_PL = 0x8002100009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_FIR_PL = 0x8002080009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_FIR_PL = 0x8002080009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_SPARE_MODE_PL = 0x8002000009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_SPARE_MODE_PL = 0x8002000009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL = 0x8002480109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL = 0x8002480109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL = 0x8002500109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL = 0x8002500109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL = 0x8002580109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL = 0x8002580109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL5_EO_PL = 0x8002600109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL5_EO_PL = 0x8002600109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL = 0x8002400109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL = 0x8002400109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL = 0x8002200109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL = 0x8002200109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE2_EO_PL = 0x8002280109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE2_EO_PL = 0x8002280109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL = 0x8002300109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL = 0x8002300109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE4_EO_PL = 0x8002380109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE4_EO_PL = 0x8002380109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_STAT1_EO_PL = 0x8002680109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_STAT1_EO_PL = 0x8002680109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_STAT1_O_PL = 0x8003180109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_STAT1_O_PL = 0x8003180109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL = 0x8002700109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL = 0x8002700109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL = 0x8002780109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL = 0x8002780109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_STAT4_EO_PL = 0x8002800109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_STAT4_EO_PL = 0x8002800109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL10_O_PL = 0x8000C80109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL10_O_PL = 0x8000C80109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL = 0x8000080109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL = 0x8000080109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_O_PL = 0x8000800109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_O_PL = 0x8000800109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL = 0x8000100109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL = 0x8000100109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_O_PL = 0x8000880109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_O_PL = 0x8000880109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_EO_PL = 0x8000180109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_EO_PL = 0x8000180109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_O_PL = 0x8000900109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_O_PL = 0x8000900109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_EO_PL = 0x8000200109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_EO_PL = 0x8000200109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_O_PL = 0x8000980109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_O_PL = 0x8000980109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL = 0x8000280109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL = 0x8000280109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_O_PL = 0x8000A00109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_O_PL = 0x8000A00109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_EO_PL = 0x8000300109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_EO_PL = 0x8000300109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_O_PL = 0x8000A80109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_O_PL = 0x8000A80109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL7_EO_PL = 0x8000380109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL7_EO_PL = 0x8000380109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL7_O_PL = 0x8000B00109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL7_O_PL = 0x8000B00109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL8_EO_PL = 0x8000400109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL8_EO_PL = 0x8000400109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL8_O_PL = 0x8000B80109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL8_O_PL = 0x8000B80109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL9_O_PL = 0x8000C00109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL9_O_PL = 0x8000C00109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL = 0x8000000109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x8000000109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_FIR_ERROR_INJECT_PL = 0x8002180109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_FIR_ERROR_INJECT_PL = 0x8002180109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_FIR_MASK_PL = 0x8002100109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_FIR_MASK_PL = 0x8002100109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_FIR_PL = 0x8002080109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_FIR_PL = 0x8002080109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_SPARE_MODE_PL = 0x8002000109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_SPARE_MODE_PL = 0x8002000109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL = 0x8002480209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL = 0x8002480209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL = 0x8002500209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL = 0x8002500209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL = 0x8002580209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL = 0x8002580209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL5_EO_PL = 0x8002600209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL5_EO_PL = 0x8002600209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL = 0x8002400209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL = 0x8002400209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL = 0x8002200209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL = 0x8002200209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_MODE2_EO_PL = 0x8002280209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_MODE2_EO_PL = 0x8002280209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL = 0x8002300209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL = 0x8002300209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_MODE4_EO_PL = 0x8002380209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_MODE4_EO_PL = 0x8002380209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_STAT1_EO_PL = 0x8002680209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_STAT1_EO_PL = 0x8002680209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_STAT1_O_PL = 0x8003180209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_STAT1_O_PL = 0x8003180209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL = 0x8002700209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL = 0x8002700209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL = 0x8002780209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL = 0x8002780209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_STAT4_EO_PL = 0x8002800209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_STAT4_EO_PL = 0x8002800209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL10_O_PL = 0x8000C80209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL10_O_PL = 0x8000C80209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL = 0x8000080209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL = 0x8000080209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_O_PL = 0x8000800209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_O_PL = 0x8000800209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL = 0x8000100209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL = 0x8000100209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_O_PL = 0x8000880209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_O_PL = 0x8000880209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_EO_PL = 0x8000180209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_EO_PL = 0x8000180209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_O_PL = 0x8000900209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_O_PL = 0x8000900209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_EO_PL = 0x8000200209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_EO_PL = 0x8000200209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_O_PL = 0x8000980209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_O_PL = 0x8000980209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL = 0x8000280209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL = 0x8000280209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_O_PL = 0x8000A00209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_O_PL = 0x8000A00209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_EO_PL = 0x8000300209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_EO_PL = 0x8000300209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_O_PL = 0x8000A80209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_O_PL = 0x8000A80209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL7_EO_PL = 0x8000380209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL7_EO_PL = 0x8000380209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL7_O_PL = 0x8000B00209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL7_O_PL = 0x8000B00209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL8_EO_PL = 0x8000400209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL8_EO_PL = 0x8000400209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL8_O_PL = 0x8000B80209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL8_O_PL = 0x8000B80209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL9_O_PL = 0x8000C00209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL9_O_PL = 0x8000C00209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL = 0x8000000209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x8000000209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_FIR_ERROR_INJECT_PL = 0x8002180209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_FIR_ERROR_INJECT_PL = 0x8002180209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_FIR_MASK_PL = 0x8002100209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_FIR_MASK_PL = 0x8002100209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_FIR_PL = 0x8002080209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_FIR_PL = 0x8002080209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_SPARE_MODE_PL = 0x8002000209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_SPARE_MODE_PL = 0x8002000209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL = 0x8002480309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL = 0x8002480309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL = 0x8002500309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL = 0x8002500309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL = 0x8002580309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL = 0x8002580309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL5_EO_PL = 0x8002600309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL5_EO_PL = 0x8002600309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL = 0x8002400309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL = 0x8002400309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL = 0x8002200309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL = 0x8002200309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_MODE2_EO_PL = 0x8002280309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_MODE2_EO_PL = 0x8002280309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL = 0x8002300309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL = 0x8002300309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_MODE4_EO_PL = 0x8002380309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_MODE4_EO_PL = 0x8002380309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_STAT1_EO_PL = 0x8002680309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_STAT1_EO_PL = 0x8002680309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_STAT1_O_PL = 0x8003180309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_STAT1_O_PL = 0x8003180309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL = 0x8002700309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL = 0x8002700309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL = 0x8002780309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL = 0x8002780309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_STAT4_EO_PL = 0x8002800309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_STAT4_EO_PL = 0x8002800309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL10_O_PL = 0x8000C80309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL10_O_PL = 0x8000C80309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL = 0x8000080309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL = 0x8000080309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_O_PL = 0x8000800309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_O_PL = 0x8000800309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL = 0x8000100309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL = 0x8000100309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_O_PL = 0x8000880309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_O_PL = 0x8000880309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL3_EO_PL = 0x8000180309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL3_EO_PL = 0x8000180309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL3_O_PL = 0x8000900309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL3_O_PL = 0x8000900309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_EO_PL = 0x8000200309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_EO_PL = 0x8000200309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_O_PL = 0x8000980309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_O_PL = 0x8000980309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL = 0x8000280309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL = 0x8000280309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_O_PL = 0x8000A00309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_O_PL = 0x8000A00309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL6_EO_PL = 0x8000300309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL6_EO_PL = 0x8000300309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL6_O_PL = 0x8000A80309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL6_O_PL = 0x8000A80309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL7_EO_PL = 0x8000380309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL7_EO_PL = 0x8000380309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL7_O_PL = 0x8000B00309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL7_O_PL = 0x8000B00309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL8_EO_PL = 0x8000400309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL8_EO_PL = 0x8000400309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL8_O_PL = 0x8000B80309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL8_O_PL = 0x8000B80309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL9_O_PL = 0x8000C00309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL9_O_PL = 0x8000C00309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL = 0x8000000309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x8000000309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_FIR_ERROR_INJECT_PL = 0x8002180309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_FIR_ERROR_INJECT_PL = 0x8002180309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_FIR_MASK_PL = 0x8002100309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_FIR_MASK_PL = 0x8002100309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_FIR_PL = 0x8002080309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_FIR_PL = 0x8002080309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_SPARE_MODE_PL = 0x8002000309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_SPARE_MODE_PL = 0x8002000309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL = 0x8002480409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL = 0x8002480409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL = 0x8002500409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL = 0x8002500409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL = 0x8002580409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL = 0x8002580409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL5_EO_PL = 0x8002600409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL5_EO_PL = 0x8002600409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL = 0x8002400409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL = 0x8002400409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL = 0x8002200409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL = 0x8002200409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_MODE2_EO_PL = 0x8002280409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_MODE2_EO_PL = 0x8002280409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL = 0x8002300409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL = 0x8002300409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_MODE4_EO_PL = 0x8002380409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_MODE4_EO_PL = 0x8002380409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_STAT1_EO_PL = 0x8002680409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_STAT1_EO_PL = 0x8002680409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_STAT1_O_PL = 0x8003180409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_STAT1_O_PL = 0x8003180409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL = 0x8002700409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL = 0x8002700409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL = 0x8002780409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL = 0x8002780409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_STAT4_EO_PL = 0x8002800409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_STAT4_EO_PL = 0x8002800409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL10_O_PL = 0x8000C80409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL10_O_PL = 0x8000C80409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL = 0x8000080409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL = 0x8000080409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_O_PL = 0x8000800409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_O_PL = 0x8000800409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_EO_PL = 0x8000100409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_EO_PL = 0x8000100409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_O_PL = 0x8000880409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_O_PL = 0x8000880409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL3_EO_PL = 0x8000180409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL3_EO_PL = 0x8000180409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL3_O_PL = 0x8000900409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL3_O_PL = 0x8000900409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_EO_PL = 0x8000200409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_EO_PL = 0x8000200409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_O_PL = 0x8000980409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_O_PL = 0x8000980409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL = 0x8000280409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL = 0x8000280409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_O_PL = 0x8000A00409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_O_PL = 0x8000A00409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL6_EO_PL = 0x8000300409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL6_EO_PL = 0x8000300409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL6_O_PL = 0x8000A80409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL6_O_PL = 0x8000A80409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL7_EO_PL = 0x8000380409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL7_EO_PL = 0x8000380409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL7_O_PL = 0x8000B00409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL7_O_PL = 0x8000B00409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL8_EO_PL = 0x8000400409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL8_EO_PL = 0x8000400409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL8_O_PL = 0x8000B80409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL8_O_PL = 0x8000B80409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL9_O_PL = 0x8000C00409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL9_O_PL = 0x8000C00409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL = 0x8000000409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x8000000409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_FIR_ERROR_INJECT_PL = 0x8002180409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_FIR_ERROR_INJECT_PL = 0x8002180409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_FIR_MASK_PL = 0x8002100409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_FIR_MASK_PL = 0x8002100409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_FIR_PL = 0x8002080409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_FIR_PL = 0x8002080409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_SPARE_MODE_PL = 0x8002000409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_SPARE_MODE_PL = 0x8002000409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL = 0x8002480509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL = 0x8002480509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL = 0x8002500509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL = 0x8002500509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL = 0x8002580509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL = 0x8002580509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL5_EO_PL = 0x8002600509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL5_EO_PL = 0x8002600509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL = 0x8002400509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL = 0x8002400509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL = 0x8002200509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL = 0x8002200509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_MODE2_EO_PL = 0x8002280509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_MODE2_EO_PL = 0x8002280509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL = 0x8002300509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL = 0x8002300509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_MODE4_EO_PL = 0x8002380509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_MODE4_EO_PL = 0x8002380509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_STAT1_EO_PL = 0x8002680509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_STAT1_EO_PL = 0x8002680509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_STAT1_O_PL = 0x8003180509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_STAT1_O_PL = 0x8003180509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL = 0x8002700509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL = 0x8002700509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL = 0x8002780509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL = 0x8002780509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_STAT4_EO_PL = 0x8002800509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_STAT4_EO_PL = 0x8002800509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL10_O_PL = 0x8000C80509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL10_O_PL = 0x8000C80509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL = 0x8000080509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL = 0x8000080509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_O_PL = 0x8000800509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_O_PL = 0x8000800509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_EO_PL = 0x8000100509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_EO_PL = 0x8000100509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_O_PL = 0x8000880509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_O_PL = 0x8000880509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL3_EO_PL = 0x8000180509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL3_EO_PL = 0x8000180509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL3_O_PL = 0x8000900509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL3_O_PL = 0x8000900509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_EO_PL = 0x8000200509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_EO_PL = 0x8000200509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_O_PL = 0x8000980509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_O_PL = 0x8000980509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL = 0x8000280509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL = 0x8000280509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_O_PL = 0x8000A00509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_O_PL = 0x8000A00509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL6_EO_PL = 0x8000300509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL6_EO_PL = 0x8000300509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL6_O_PL = 0x8000A80509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL6_O_PL = 0x8000A80509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL7_EO_PL = 0x8000380509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL7_EO_PL = 0x8000380509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL7_O_PL = 0x8000B00509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL7_O_PL = 0x8000B00509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL8_EO_PL = 0x8000400509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL8_EO_PL = 0x8000400509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL8_O_PL = 0x8000B80509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL8_O_PL = 0x8000B80509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL9_O_PL = 0x8000C00509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL9_O_PL = 0x8000C00509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL = 0x8000000509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x8000000509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_FIR_ERROR_INJECT_PL = 0x8002180509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_FIR_ERROR_INJECT_PL = 0x8002180509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_FIR_MASK_PL = 0x8002100509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_FIR_MASK_PL = 0x8002100509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_FIR_PL = 0x8002080509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_FIR_PL = 0x8002080509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_SPARE_MODE_PL = 0x8002000509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_SPARE_MODE_PL = 0x8002000509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL = 0x8002480609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL = 0x8002480609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL = 0x8002500609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL = 0x8002500609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL = 0x8002580609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL = 0x8002580609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL5_EO_PL = 0x8002600609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL5_EO_PL = 0x8002600609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL = 0x8002400609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL = 0x8002400609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL = 0x8002200609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL = 0x8002200609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_MODE2_EO_PL = 0x8002280609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_MODE2_EO_PL = 0x8002280609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL = 0x8002300609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL = 0x8002300609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_MODE4_EO_PL = 0x8002380609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_MODE4_EO_PL = 0x8002380609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_STAT1_EO_PL = 0x8002680609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_STAT1_EO_PL = 0x8002680609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_STAT1_O_PL = 0x8003180609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_STAT1_O_PL = 0x8003180609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL = 0x8002700609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL = 0x8002700609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL = 0x8002780609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL = 0x8002780609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_STAT4_EO_PL = 0x8002800609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_STAT4_EO_PL = 0x8002800609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL10_O_PL = 0x8000C80609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL10_O_PL = 0x8000C80609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL = 0x8000080609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL = 0x8000080609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_O_PL = 0x8000800609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_O_PL = 0x8000800609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_EO_PL = 0x8000100609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_EO_PL = 0x8000100609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_O_PL = 0x8000880609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_O_PL = 0x8000880609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL3_EO_PL = 0x8000180609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL3_EO_PL = 0x8000180609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL3_O_PL = 0x8000900609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL3_O_PL = 0x8000900609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_EO_PL = 0x8000200609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_EO_PL = 0x8000200609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_O_PL = 0x8000980609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_O_PL = 0x8000980609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL = 0x8000280609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL = 0x8000280609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_O_PL = 0x8000A00609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_O_PL = 0x8000A00609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL6_EO_PL = 0x8000300609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL6_EO_PL = 0x8000300609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL6_O_PL = 0x8000A80609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL6_O_PL = 0x8000A80609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL7_EO_PL = 0x8000380609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL7_EO_PL = 0x8000380609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL7_O_PL = 0x8000B00609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL7_O_PL = 0x8000B00609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL8_EO_PL = 0x8000400609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL8_EO_PL = 0x8000400609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL8_O_PL = 0x8000B80609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL8_O_PL = 0x8000B80609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL9_O_PL = 0x8000C00609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL9_O_PL = 0x8000C00609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL = 0x8000000609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x8000000609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_FIR_ERROR_INJECT_PL = 0x8002180609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_FIR_ERROR_INJECT_PL = 0x8002180609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_FIR_MASK_PL = 0x8002100609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_FIR_MASK_PL = 0x8002100609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_FIR_PL = 0x8002080609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_FIR_PL = 0x8002080609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_SPARE_MODE_PL = 0x8002000609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_SPARE_MODE_PL = 0x8002000609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL = 0x8002480709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL = 0x8002480709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL = 0x8002500709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL = 0x8002500709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL = 0x8002580709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL = 0x8002580709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL5_EO_PL = 0x8002600709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL5_EO_PL = 0x8002600709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL = 0x8002400709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL = 0x8002400709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL = 0x8002200709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL = 0x8002200709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_MODE2_EO_PL = 0x8002280709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_MODE2_EO_PL = 0x8002280709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL = 0x8002300709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL = 0x8002300709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_MODE4_EO_PL = 0x8002380709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_MODE4_EO_PL = 0x8002380709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_STAT1_EO_PL = 0x8002680709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_STAT1_EO_PL = 0x8002680709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_STAT1_O_PL = 0x8003180709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_STAT1_O_PL = 0x8003180709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL = 0x8002700709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL = 0x8002700709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL = 0x8002780709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL = 0x8002780709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_STAT4_EO_PL = 0x8002800709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_STAT4_EO_PL = 0x8002800709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL10_O_PL = 0x8000C80709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL10_O_PL = 0x8000C80709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL = 0x8000080709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL = 0x8000080709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_O_PL = 0x8000800709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_O_PL = 0x8000800709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_EO_PL = 0x8000100709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_EO_PL = 0x8000100709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_O_PL = 0x8000880709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_O_PL = 0x8000880709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL3_EO_PL = 0x8000180709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL3_EO_PL = 0x8000180709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL3_O_PL = 0x8000900709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL3_O_PL = 0x8000900709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_EO_PL = 0x8000200709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_EO_PL = 0x8000200709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_O_PL = 0x8000980709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_O_PL = 0x8000980709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL = 0x8000280709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL = 0x8000280709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_O_PL = 0x8000A00709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_O_PL = 0x8000A00709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL6_EO_PL = 0x8000300709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL6_EO_PL = 0x8000300709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL6_O_PL = 0x8000A80709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL6_O_PL = 0x8000A80709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL7_EO_PL = 0x8000380709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL7_EO_PL = 0x8000380709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL7_O_PL = 0x8000B00709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL7_O_PL = 0x8000B00709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL8_EO_PL = 0x8000400709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL8_EO_PL = 0x8000400709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL8_O_PL = 0x8000B80709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL8_O_PL = 0x8000B80709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL9_O_PL = 0x8000C00709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL9_O_PL = 0x8000C00709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL = 0x8000000709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x8000000709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_FIR_ERROR_INJECT_PL = 0x8002180709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_FIR_ERROR_INJECT_PL = 0x8002180709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_FIR_MASK_PL = 0x8002100709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_FIR_MASK_PL = 0x8002100709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_FIR_PL = 0x8002080709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_FIR_PL = 0x8002080709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_SPARE_MODE_PL = 0x8002000709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_SPARE_MODE_PL = 0x8002000709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL = 0x8002480809010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL = 0x8002480809010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL = 0x8002500809010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL = 0x8002500809010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL = 0x8002580809010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL = 0x8002580809010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL5_EO_PL = 0x8002600809010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL5_EO_PL = 0x8002600809010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL = 0x8002400809010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL = 0x8002400809010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL = 0x8002200809010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL = 0x8002200809010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_MODE2_EO_PL = 0x8002280809010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_MODE2_EO_PL = 0x8002280809010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL = 0x8002300809010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL = 0x8002300809010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_MODE4_EO_PL = 0x8002380809010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_MODE4_EO_PL = 0x8002380809010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_STAT1_EO_PL = 0x8002680809010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_STAT1_EO_PL = 0x8002680809010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_STAT1_O_PL = 0x8003180809010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_STAT1_O_PL = 0x8003180809010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL = 0x8002700809010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL = 0x8002700809010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL = 0x8002780809010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL = 0x8002780809010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_STAT4_EO_PL = 0x8002800809010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_STAT4_EO_PL = 0x8002800809010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL10_O_PL = 0x8000C80809010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL10_O_PL = 0x8000C80809010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL = 0x8000080809010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL = 0x8000080809010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_O_PL = 0x8000800809010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_O_PL = 0x8000800809010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_EO_PL = 0x8000100809010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_EO_PL = 0x8000100809010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_O_PL = 0x8000880809010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_O_PL = 0x8000880809010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL3_EO_PL = 0x8000180809010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL3_EO_PL = 0x8000180809010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL3_O_PL = 0x8000900809010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL3_O_PL = 0x8000900809010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_EO_PL = 0x8000200809010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_EO_PL = 0x8000200809010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_O_PL = 0x8000980809010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_O_PL = 0x8000980809010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL = 0x8000280809010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL = 0x8000280809010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_O_PL = 0x8000A00809010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_O_PL = 0x8000A00809010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL6_EO_PL = 0x8000300809010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL6_EO_PL = 0x8000300809010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL6_O_PL = 0x8000A80809010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL6_O_PL = 0x8000A80809010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL7_EO_PL = 0x8000380809010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL7_EO_PL = 0x8000380809010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL7_O_PL = 0x8000B00809010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL7_O_PL = 0x8000B00809010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL8_EO_PL = 0x8000400809010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL8_EO_PL = 0x8000400809010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL8_O_PL = 0x8000B80809010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL8_O_PL = 0x8000B80809010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL9_O_PL = 0x8000C00809010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL9_O_PL = 0x8000C00809010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL = 0x8000000809010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x8000000809010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_FIR_ERROR_INJECT_PL = 0x8002180809010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_FIR_ERROR_INJECT_PL = 0x8002180809010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_FIR_MASK_PL = 0x8002100809010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_FIR_MASK_PL = 0x8002100809010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_FIR_PL = 0x8002080809010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_FIR_PL = 0x8002080809010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_SPARE_MODE_PL = 0x8002000809010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_SPARE_MODE_PL = 0x8002000809010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL = 0x8002480909010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL = 0x8002480909010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL = 0x8002500909010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL = 0x8002500909010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL = 0x8002580909010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL = 0x8002580909010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL5_EO_PL = 0x8002600909010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL5_EO_PL = 0x8002600909010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL = 0x8002400909010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL = 0x8002400909010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL = 0x8002200909010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL = 0x8002200909010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_MODE2_EO_PL = 0x8002280909010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_MODE2_EO_PL = 0x8002280909010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL = 0x8002300909010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL = 0x8002300909010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_MODE4_EO_PL = 0x8002380909010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_MODE4_EO_PL = 0x8002380909010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_STAT1_EO_PL = 0x8002680909010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_STAT1_EO_PL = 0x8002680909010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_STAT1_O_PL = 0x8003180909010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_STAT1_O_PL = 0x8003180909010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL = 0x8002700909010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL = 0x8002700909010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL = 0x8002780909010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL = 0x8002780909010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_STAT4_EO_PL = 0x8002800909010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_STAT4_EO_PL = 0x8002800909010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL10_O_PL = 0x8000C80909010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL10_O_PL = 0x8000C80909010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL = 0x8000080909010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL = 0x8000080909010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_O_PL = 0x8000800909010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_O_PL = 0x8000800909010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_EO_PL = 0x8000100909010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_EO_PL = 0x8000100909010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_O_PL = 0x8000880909010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_O_PL = 0x8000880909010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL3_EO_PL = 0x8000180909010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL3_EO_PL = 0x8000180909010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL3_O_PL = 0x8000900909010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL3_O_PL = 0x8000900909010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_EO_PL = 0x8000200909010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_EO_PL = 0x8000200909010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_O_PL = 0x8000980909010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_O_PL = 0x8000980909010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL = 0x8000280909010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL = 0x8000280909010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_O_PL = 0x8000A00909010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_O_PL = 0x8000A00909010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL6_EO_PL = 0x8000300909010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL6_EO_PL = 0x8000300909010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL6_O_PL = 0x8000A80909010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL6_O_PL = 0x8000A80909010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL7_EO_PL = 0x8000380909010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL7_EO_PL = 0x8000380909010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL7_O_PL = 0x8000B00909010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL7_O_PL = 0x8000B00909010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL8_EO_PL = 0x8000400909010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL8_EO_PL = 0x8000400909010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL8_O_PL = 0x8000B80909010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL8_O_PL = 0x8000B80909010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL9_O_PL = 0x8000C00909010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL9_O_PL = 0x8000C00909010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL = 0x8000000909010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x8000000909010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_FIR_ERROR_INJECT_PL = 0x8002180909010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_FIR_ERROR_INJECT_PL = 0x8002180909010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_FIR_MASK_PL = 0x8002100909010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_FIR_MASK_PL = 0x8002100909010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_FIR_PL = 0x8002080909010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_FIR_PL = 0x8002080909010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_SPARE_MODE_PL = 0x8002000909010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_SPARE_MODE_PL = 0x8002000909010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL = 0x8002480A09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL = 0x8002480A09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL = 0x8002500A09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL = 0x8002500A09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL = 0x8002580A09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL = 0x8002580A09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL5_EO_PL = 0x8002600A09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL5_EO_PL = 0x8002600A09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL = 0x8002400A09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL = 0x8002400A09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL = 0x8002200A09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL = 0x8002200A09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_MODE2_EO_PL = 0x8002280A09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_MODE2_EO_PL = 0x8002280A09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL = 0x8002300A09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL = 0x8002300A09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_MODE4_EO_PL = 0x8002380A09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_MODE4_EO_PL = 0x8002380A09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_STAT1_EO_PL = 0x8002680A09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_STAT1_EO_PL = 0x8002680A09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_STAT1_O_PL = 0x8003180A09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_STAT1_O_PL = 0x8003180A09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL = 0x8002700A09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL = 0x8002700A09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL = 0x8002780A09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL = 0x8002780A09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_STAT4_EO_PL = 0x8002800A09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_STAT4_EO_PL = 0x8002800A09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL10_O_PL = 0x8000C80A09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL10_O_PL = 0x8000C80A09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL = 0x8000080A09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL = 0x8000080A09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_O_PL = 0x8000800A09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_O_PL = 0x8000800A09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_EO_PL = 0x8000100A09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_EO_PL = 0x8000100A09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_O_PL = 0x8000880A09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_O_PL = 0x8000880A09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL3_EO_PL = 0x8000180A09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL3_EO_PL = 0x8000180A09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL3_O_PL = 0x8000900A09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL3_O_PL = 0x8000900A09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_EO_PL = 0x8000200A09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_EO_PL = 0x8000200A09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_O_PL = 0x8000980A09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_O_PL = 0x8000980A09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL = 0x8000280A09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL = 0x8000280A09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_O_PL = 0x8000A00A09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_O_PL = 0x8000A00A09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL6_EO_PL = 0x8000300A09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL6_EO_PL = 0x8000300A09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL6_O_PL = 0x8000A80A09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL6_O_PL = 0x8000A80A09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL7_EO_PL = 0x8000380A09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL7_EO_PL = 0x8000380A09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL7_O_PL = 0x8000B00A09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL7_O_PL = 0x8000B00A09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL8_EO_PL = 0x8000400A09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL8_EO_PL = 0x8000400A09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL8_O_PL = 0x8000B80A09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL8_O_PL = 0x8000B80A09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL9_O_PL = 0x8000C00A09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL9_O_PL = 0x8000C00A09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL = 0x8000000A09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x8000000A09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_FIR_ERROR_INJECT_PL = 0x8002180A09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_FIR_ERROR_INJECT_PL = 0x8002180A09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_FIR_MASK_PL = 0x8002100A09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_FIR_MASK_PL = 0x8002100A09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_FIR_PL = 0x8002080A09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_FIR_PL = 0x8002080A09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_SPARE_MODE_PL = 0x8002000A09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_SPARE_MODE_PL = 0x8002000A09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL = 0x8002480B09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL = 0x8002480B09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL = 0x8002500B09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL = 0x8002500B09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL = 0x8002580B09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL = 0x8002580B09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL5_EO_PL = 0x8002600B09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL5_EO_PL = 0x8002600B09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL = 0x8002400B09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL = 0x8002400B09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL = 0x8002200B09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL = 0x8002200B09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_MODE2_EO_PL = 0x8002280B09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_MODE2_EO_PL = 0x8002280B09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL = 0x8002300B09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL = 0x8002300B09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_MODE4_EO_PL = 0x8002380B09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_MODE4_EO_PL = 0x8002380B09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_STAT1_EO_PL = 0x8002680B09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_STAT1_EO_PL = 0x8002680B09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_STAT1_O_PL = 0x8003180B09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_STAT1_O_PL = 0x8003180B09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL = 0x8002700B09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL = 0x8002700B09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL = 0x8002780B09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL = 0x8002780B09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_STAT4_EO_PL = 0x8002800B09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_STAT4_EO_PL = 0x8002800B09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL10_O_PL = 0x8000C80B09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL10_O_PL = 0x8000C80B09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL = 0x8000080B09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL = 0x8000080B09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_O_PL = 0x8000800B09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_O_PL = 0x8000800B09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_EO_PL = 0x8000100B09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_EO_PL = 0x8000100B09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_O_PL = 0x8000880B09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_O_PL = 0x8000880B09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL3_EO_PL = 0x8000180B09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL3_EO_PL = 0x8000180B09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL3_O_PL = 0x8000900B09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL3_O_PL = 0x8000900B09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_EO_PL = 0x8000200B09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_EO_PL = 0x8000200B09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_O_PL = 0x8000980B09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_O_PL = 0x8000980B09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL = 0x8000280B09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL = 0x8000280B09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_O_PL = 0x8000A00B09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_O_PL = 0x8000A00B09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL6_EO_PL = 0x8000300B09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL6_EO_PL = 0x8000300B09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL6_O_PL = 0x8000A80B09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL6_O_PL = 0x8000A80B09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL7_EO_PL = 0x8000380B09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL7_EO_PL = 0x8000380B09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL7_O_PL = 0x8000B00B09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL7_O_PL = 0x8000B00B09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL8_EO_PL = 0x8000400B09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL8_EO_PL = 0x8000400B09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL8_O_PL = 0x8000B80B09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL8_O_PL = 0x8000B80B09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL9_O_PL = 0x8000C00B09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL9_O_PL = 0x8000C00B09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL = 0x8000000B09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x8000000B09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_FIR_ERROR_INJECT_PL = 0x8002180B09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_FIR_ERROR_INJECT_PL = 0x8002180B09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_FIR_MASK_PL = 0x8002100B09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_FIR_MASK_PL = 0x8002100B09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_FIR_PL = 0x8002080B09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_FIR_PL = 0x8002080B09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_SPARE_MODE_PL = 0x8002000B09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_SPARE_MODE_PL = 0x8002000B09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL = 0x8002480C09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL = 0x8002480C09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL = 0x8002500C09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL = 0x8002500C09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL = 0x8002580C09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL = 0x8002580C09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL5_EO_PL = 0x8002600C09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL5_EO_PL = 0x8002600C09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL = 0x8002400C09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL = 0x8002400C09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL = 0x8002200C09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL = 0x8002200C09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_MODE2_EO_PL = 0x8002280C09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_MODE2_EO_PL = 0x8002280C09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL = 0x8002300C09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL = 0x8002300C09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_MODE4_EO_PL = 0x8002380C09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_MODE4_EO_PL = 0x8002380C09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_STAT1_EO_PL = 0x8002680C09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_STAT1_EO_PL = 0x8002680C09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_STAT1_O_PL = 0x8003180C09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_STAT1_O_PL = 0x8003180C09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL = 0x8002700C09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL = 0x8002700C09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL = 0x8002780C09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL = 0x8002780C09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_STAT4_EO_PL = 0x8002800C09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_STAT4_EO_PL = 0x8002800C09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL10_O_PL = 0x8000C80C09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL10_O_PL = 0x8000C80C09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL = 0x8000080C09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL = 0x8000080C09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_O_PL = 0x8000800C09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_O_PL = 0x8000800C09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_EO_PL = 0x8000100C09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_EO_PL = 0x8000100C09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_O_PL = 0x8000880C09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_O_PL = 0x8000880C09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL3_EO_PL = 0x8000180C09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL3_EO_PL = 0x8000180C09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL3_O_PL = 0x8000900C09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL3_O_PL = 0x8000900C09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_EO_PL = 0x8000200C09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_EO_PL = 0x8000200C09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_O_PL = 0x8000980C09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_O_PL = 0x8000980C09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL = 0x8000280C09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL = 0x8000280C09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_O_PL = 0x8000A00C09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_O_PL = 0x8000A00C09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL6_EO_PL = 0x8000300C09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL6_EO_PL = 0x8000300C09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL6_O_PL = 0x8000A80C09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL6_O_PL = 0x8000A80C09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL7_EO_PL = 0x8000380C09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL7_EO_PL = 0x8000380C09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL7_O_PL = 0x8000B00C09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL7_O_PL = 0x8000B00C09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL8_EO_PL = 0x8000400C09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL8_EO_PL = 0x8000400C09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL8_O_PL = 0x8000B80C09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL8_O_PL = 0x8000B80C09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL9_O_PL = 0x8000C00C09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL9_O_PL = 0x8000C00C09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL = 0x8000000C09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x8000000C09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_FIR_ERROR_INJECT_PL = 0x8002180C09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_FIR_ERROR_INJECT_PL = 0x8002180C09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_FIR_MASK_PL = 0x8002100C09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_FIR_MASK_PL = 0x8002100C09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_FIR_PL = 0x8002080C09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_FIR_PL = 0x8002080C09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_SPARE_MODE_PL = 0x8002000C09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_SPARE_MODE_PL = 0x8002000C09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL = 0x8002480D09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL = 0x8002480D09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL = 0x8002500D09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL = 0x8002500D09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL = 0x8002580D09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL = 0x8002580D09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL5_EO_PL = 0x8002600D09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL5_EO_PL = 0x8002600D09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL = 0x8002400D09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL = 0x8002400D09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL = 0x8002200D09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL = 0x8002200D09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_MODE2_EO_PL = 0x8002280D09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_MODE2_EO_PL = 0x8002280D09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL = 0x8002300D09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL = 0x8002300D09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_MODE4_EO_PL = 0x8002380D09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_MODE4_EO_PL = 0x8002380D09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_STAT1_EO_PL = 0x8002680D09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_STAT1_EO_PL = 0x8002680D09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_STAT1_O_PL = 0x8003180D09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_STAT1_O_PL = 0x8003180D09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL = 0x8002700D09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL = 0x8002700D09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL = 0x8002780D09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL = 0x8002780D09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_STAT4_EO_PL = 0x8002800D09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_STAT4_EO_PL = 0x8002800D09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL10_O_PL = 0x8000C80D09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL10_O_PL = 0x8000C80D09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL = 0x8000080D09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL = 0x8000080D09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_O_PL = 0x8000800D09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_O_PL = 0x8000800D09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_EO_PL = 0x8000100D09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_EO_PL = 0x8000100D09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_O_PL = 0x8000880D09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_O_PL = 0x8000880D09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL3_EO_PL = 0x8000180D09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL3_EO_PL = 0x8000180D09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL3_O_PL = 0x8000900D09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL3_O_PL = 0x8000900D09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_EO_PL = 0x8000200D09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_EO_PL = 0x8000200D09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_O_PL = 0x8000980D09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_O_PL = 0x8000980D09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL = 0x8000280D09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL = 0x8000280D09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_O_PL = 0x8000A00D09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_O_PL = 0x8000A00D09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL6_EO_PL = 0x8000300D09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL6_EO_PL = 0x8000300D09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL6_O_PL = 0x8000A80D09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL6_O_PL = 0x8000A80D09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL7_EO_PL = 0x8000380D09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL7_EO_PL = 0x8000380D09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL7_O_PL = 0x8000B00D09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL7_O_PL = 0x8000B00D09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL8_EO_PL = 0x8000400D09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL8_EO_PL = 0x8000400D09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL8_O_PL = 0x8000B80D09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL8_O_PL = 0x8000B80D09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL9_O_PL = 0x8000C00D09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL9_O_PL = 0x8000C00D09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL = 0x8000000D09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x8000000D09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_FIR_ERROR_INJECT_PL = 0x8002180D09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_FIR_ERROR_INJECT_PL = 0x8002180D09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_FIR_MASK_PL = 0x8002100D09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_FIR_MASK_PL = 0x8002100D09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_FIR_PL = 0x8002080D09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_FIR_PL = 0x8002080D09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_SPARE_MODE_PL = 0x8002000D09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_SPARE_MODE_PL = 0x8002000D09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL = 0x8002480E09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL = 0x8002480E09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL = 0x8002500E09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL = 0x8002500E09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL = 0x8002580E09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL = 0x8002580E09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL5_EO_PL = 0x8002600E09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL5_EO_PL = 0x8002600E09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL = 0x8002400E09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL = 0x8002400E09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL = 0x8002200E09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL = 0x8002200E09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_MODE2_EO_PL = 0x8002280E09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_MODE2_EO_PL = 0x8002280E09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL = 0x8002300E09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL = 0x8002300E09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_MODE4_EO_PL = 0x8002380E09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_MODE4_EO_PL = 0x8002380E09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_STAT1_EO_PL = 0x8002680E09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_STAT1_EO_PL = 0x8002680E09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_STAT1_O_PL = 0x8003180E09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_STAT1_O_PL = 0x8003180E09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL = 0x8002700E09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL = 0x8002700E09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL = 0x8002780E09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL = 0x8002780E09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_STAT4_EO_PL = 0x8002800E09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_STAT4_EO_PL = 0x8002800E09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL10_O_PL = 0x8000C80E09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL10_O_PL = 0x8000C80E09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL = 0x8000080E09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL = 0x8000080E09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_O_PL = 0x8000800E09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_O_PL = 0x8000800E09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_EO_PL = 0x8000100E09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_EO_PL = 0x8000100E09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_O_PL = 0x8000880E09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_O_PL = 0x8000880E09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL3_EO_PL = 0x8000180E09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL3_EO_PL = 0x8000180E09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL3_O_PL = 0x8000900E09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL3_O_PL = 0x8000900E09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_EO_PL = 0x8000200E09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_EO_PL = 0x8000200E09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_O_PL = 0x8000980E09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_O_PL = 0x8000980E09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL = 0x8000280E09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL = 0x8000280E09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_O_PL = 0x8000A00E09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_O_PL = 0x8000A00E09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL6_EO_PL = 0x8000300E09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL6_EO_PL = 0x8000300E09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL6_O_PL = 0x8000A80E09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL6_O_PL = 0x8000A80E09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL7_EO_PL = 0x8000380E09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL7_EO_PL = 0x8000380E09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL7_O_PL = 0x8000B00E09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL7_O_PL = 0x8000B00E09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL8_EO_PL = 0x8000400E09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL8_EO_PL = 0x8000400E09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL8_O_PL = 0x8000B80E09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL8_O_PL = 0x8000B80E09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL9_O_PL = 0x8000C00E09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL9_O_PL = 0x8000C00E09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL = 0x8000000E09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x8000000E09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_FIR_ERROR_INJECT_PL = 0x8002180E09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_FIR_ERROR_INJECT_PL = 0x8002180E09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_FIR_MASK_PL = 0x8002100E09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_FIR_MASK_PL = 0x8002100E09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_FIR_PL = 0x8002080E09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_FIR_PL = 0x8002080E09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_SPARE_MODE_PL = 0x8002000E09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_SPARE_MODE_PL = 0x8002000E09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL = 0x8002480F09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL = 0x8002480F09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL = 0x8002500F09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL = 0x8002500F09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL = 0x8002580F09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL = 0x8002580F09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL5_EO_PL = 0x8002600F09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL5_EO_PL = 0x8002600F09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL = 0x8002400F09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL = 0x8002400F09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL = 0x8002200F09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL = 0x8002200F09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_MODE2_EO_PL = 0x8002280F09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_MODE2_EO_PL = 0x8002280F09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL = 0x8002300F09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL = 0x8002300F09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_MODE4_EO_PL = 0x8002380F09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_MODE4_EO_PL = 0x8002380F09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_STAT1_EO_PL = 0x8002680F09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_STAT1_EO_PL = 0x8002680F09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_STAT1_O_PL = 0x8003180F09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_STAT1_O_PL = 0x8003180F09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL = 0x8002700F09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL = 0x8002700F09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL = 0x8002780F09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL = 0x8002780F09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_STAT4_EO_PL = 0x8002800F09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_STAT4_EO_PL = 0x8002800F09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL10_O_PL = 0x8000C80F09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL10_O_PL = 0x8000C80F09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL = 0x8000080F09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL = 0x8000080F09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_O_PL = 0x8000800F09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_O_PL = 0x8000800F09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_EO_PL = 0x8000100F09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_EO_PL = 0x8000100F09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_O_PL = 0x8000880F09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_O_PL = 0x8000880F09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL3_EO_PL = 0x8000180F09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL3_EO_PL = 0x8000180F09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL3_O_PL = 0x8000900F09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL3_O_PL = 0x8000900F09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_EO_PL = 0x8000200F09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_EO_PL = 0x8000200F09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_O_PL = 0x8000980F09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_O_PL = 0x8000980F09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL = 0x8000280F09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL = 0x8000280F09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_O_PL = 0x8000A00F09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_O_PL = 0x8000A00F09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL6_EO_PL = 0x8000300F09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL6_EO_PL = 0x8000300F09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL6_O_PL = 0x8000A80F09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL6_O_PL = 0x8000A80F09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL7_EO_PL = 0x8000380F09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL7_EO_PL = 0x8000380F09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL7_O_PL = 0x8000B00F09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL7_O_PL = 0x8000B00F09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL8_EO_PL = 0x8000400F09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL8_EO_PL = 0x8000400F09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL8_O_PL = 0x8000B80F09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL8_O_PL = 0x8000B80F09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL9_O_PL = 0x8000C00F09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL9_O_PL = 0x8000C00F09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL = 0x8000000F09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x8000000F09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_FIR_ERROR_INJECT_PL = 0x8002180F09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_FIR_ERROR_INJECT_PL = 0x8002180F09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_FIR_MASK_PL = 0x8002100F09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_FIR_MASK_PL = 0x8002100F09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_FIR_PL = 0x8002080F09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_FIR_PL = 0x8002080F09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_SPARE_MODE_PL = 0x8002000F09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_SPARE_MODE_PL = 0x8002000F09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL2_EO_PL = 0x8002481009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL2_EO_PL = 0x8002481009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL3_EO_PL = 0x8002501009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL3_EO_PL = 0x8002501009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL4_EO_PL = 0x8002581009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL4_EO_PL = 0x8002581009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL5_EO_PL = 0x8002601009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL5_EO_PL = 0x8002601009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_CNTLX1_EO_PL = 0x8002401009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_CNTLX1_EO_PL = 0x8002401009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_MODE1_EO_PL = 0x8002201009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_MODE1_EO_PL = 0x8002201009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_MODE2_EO_PL = 0x8002281009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_MODE2_EO_PL = 0x8002281009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_MODE3_EO_PL = 0x8002301009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_MODE3_EO_PL = 0x8002301009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_MODE4_EO_PL = 0x8002381009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_MODE4_EO_PL = 0x8002381009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_STAT1_EO_PL = 0x8002681009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_STAT1_EO_PL = 0x8002681009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_STAT1_O_PL = 0x8003181009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_STAT1_O_PL = 0x8003181009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_STAT2_EO_PL = 0x8002701009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_STAT2_EO_PL = 0x8002701009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_STAT3_EO_PL = 0x8002781009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_STAT3_EO_PL = 0x8002781009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_STAT4_EO_PL = 0x8002801009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_STAT4_EO_PL = 0x8002801009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL10_O_PL = 0x8000C81009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL10_O_PL = 0x8000C81009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL1_EO_PL = 0x8000081009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL1_EO_PL = 0x8000081009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL1_O_PL = 0x8000801009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL1_O_PL = 0x8000801009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL2_EO_PL = 0x8000101009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL2_EO_PL = 0x8000101009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL2_O_PL = 0x8000881009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL2_O_PL = 0x8000881009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL3_EO_PL = 0x8000181009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL3_EO_PL = 0x8000181009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL3_O_PL = 0x8000901009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL3_O_PL = 0x8000901009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL4_EO_PL = 0x8000201009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL4_EO_PL = 0x8000201009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL4_O_PL = 0x8000981009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL4_O_PL = 0x8000981009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL5_EO_PL = 0x8000281009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL5_EO_PL = 0x8000281009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL5_O_PL = 0x8000A01009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL5_O_PL = 0x8000A01009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL6_EO_PL = 0x8000301009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL6_EO_PL = 0x8000301009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL6_O_PL = 0x8000A81009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL6_O_PL = 0x8000A81009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL7_EO_PL = 0x8000381009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL7_EO_PL = 0x8000381009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL7_O_PL = 0x8000B01009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL7_O_PL = 0x8000B01009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL8_EO_PL = 0x8000401009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL8_EO_PL = 0x8000401009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL8_O_PL = 0x8000B81009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL8_O_PL = 0x8000B81009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL9_O_PL = 0x8000C01009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL9_O_PL = 0x8000C01009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DATA_DAC_SPARE_MODE_PL = 0x8000001009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x8000001009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_FIR_ERROR_INJECT_PL = 0x8002181009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_FIR_ERROR_INJECT_PL = 0x8002181009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_FIR_MASK_PL = 0x8002101009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_FIR_MASK_PL = 0x8002101009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_FIR_PL = 0x8002081009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_FIR_PL = 0x8002081009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_SPARE_MODE_PL = 0x8002001009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_SPARE_MODE_PL = 0x8002001009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL2_EO_PL = 0x8002481109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL2_EO_PL = 0x8002481109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL3_EO_PL = 0x8002501109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL3_EO_PL = 0x8002501109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL4_EO_PL = 0x8002581109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL4_EO_PL = 0x8002581109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL5_EO_PL = 0x8002601109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL5_EO_PL = 0x8002601109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_CNTLX1_EO_PL = 0x8002401109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_CNTLX1_EO_PL = 0x8002401109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_MODE1_EO_PL = 0x8002201109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_MODE1_EO_PL = 0x8002201109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_MODE2_EO_PL = 0x8002281109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_MODE2_EO_PL = 0x8002281109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_MODE3_EO_PL = 0x8002301109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_MODE3_EO_PL = 0x8002301109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_MODE4_EO_PL = 0x8002381109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_MODE4_EO_PL = 0x8002381109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_STAT1_EO_PL = 0x8002681109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_STAT1_EO_PL = 0x8002681109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_STAT1_O_PL = 0x8003181109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_STAT1_O_PL = 0x8003181109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_STAT2_EO_PL = 0x8002701109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_STAT2_EO_PL = 0x8002701109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_STAT3_EO_PL = 0x8002781109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_STAT3_EO_PL = 0x8002781109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_STAT4_EO_PL = 0x8002801109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_STAT4_EO_PL = 0x8002801109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL10_O_PL = 0x8000C81109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL10_O_PL = 0x8000C81109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL1_EO_PL = 0x8000081109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL1_EO_PL = 0x8000081109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL1_O_PL = 0x8000801109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL1_O_PL = 0x8000801109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL2_EO_PL = 0x8000101109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL2_EO_PL = 0x8000101109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL2_O_PL = 0x8000881109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL2_O_PL = 0x8000881109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL3_EO_PL = 0x8000181109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL3_EO_PL = 0x8000181109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL3_O_PL = 0x8000901109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL3_O_PL = 0x8000901109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL4_EO_PL = 0x8000201109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL4_EO_PL = 0x8000201109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL4_O_PL = 0x8000981109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL4_O_PL = 0x8000981109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL5_EO_PL = 0x8000281109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL5_EO_PL = 0x8000281109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL5_O_PL = 0x8000A01109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL5_O_PL = 0x8000A01109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL6_EO_PL = 0x8000301109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL6_EO_PL = 0x8000301109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL6_O_PL = 0x8000A81109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL6_O_PL = 0x8000A81109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL7_EO_PL = 0x8000381109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL7_EO_PL = 0x8000381109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL7_O_PL = 0x8000B01109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL7_O_PL = 0x8000B01109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL8_EO_PL = 0x8000401109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL8_EO_PL = 0x8000401109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL8_O_PL = 0x8000B81109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL8_O_PL = 0x8000B81109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL9_O_PL = 0x8000C01109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL9_O_PL = 0x8000C01109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DATA_DAC_SPARE_MODE_PL = 0x8000001109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x8000001109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_FIR_ERROR_INJECT_PL = 0x8002181109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_FIR_ERROR_INJECT_PL = 0x8002181109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_FIR_MASK_PL = 0x8002101109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_FIR_MASK_PL = 0x8002101109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_FIR_PL = 0x8002081109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_FIR_PL = 0x8002081109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_SPARE_MODE_PL = 0x8002001109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_SPARE_MODE_PL = 0x8002001109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL2_EO_PL = 0x8002481209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL2_EO_PL = 0x8002481209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL3_EO_PL = 0x8002501209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL3_EO_PL = 0x8002501209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL4_EO_PL = 0x8002581209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL4_EO_PL = 0x8002581209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL5_EO_PL = 0x8002601209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL5_EO_PL = 0x8002601209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_CNTLX1_EO_PL = 0x8002401209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_CNTLX1_EO_PL = 0x8002401209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_MODE1_EO_PL = 0x8002201209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_MODE1_EO_PL = 0x8002201209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_MODE2_EO_PL = 0x8002281209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_MODE2_EO_PL = 0x8002281209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_MODE3_EO_PL = 0x8002301209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_MODE3_EO_PL = 0x8002301209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_MODE4_EO_PL = 0x8002381209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_MODE4_EO_PL = 0x8002381209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_STAT1_EO_PL = 0x8002681209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_STAT1_EO_PL = 0x8002681209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_STAT1_O_PL = 0x8003181209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_STAT1_O_PL = 0x8003181209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_STAT2_EO_PL = 0x8002701209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_STAT2_EO_PL = 0x8002701209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_STAT3_EO_PL = 0x8002781209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_STAT3_EO_PL = 0x8002781209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_STAT4_EO_PL = 0x8002801209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_STAT4_EO_PL = 0x8002801209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL10_O_PL = 0x8000C81209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL10_O_PL = 0x8000C81209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL1_EO_PL = 0x8000081209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL1_EO_PL = 0x8000081209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL1_O_PL = 0x8000801209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL1_O_PL = 0x8000801209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL2_EO_PL = 0x8000101209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL2_EO_PL = 0x8000101209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL2_O_PL = 0x8000881209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL2_O_PL = 0x8000881209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL3_EO_PL = 0x8000181209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL3_EO_PL = 0x8000181209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL3_O_PL = 0x8000901209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL3_O_PL = 0x8000901209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL4_EO_PL = 0x8000201209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL4_EO_PL = 0x8000201209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL4_O_PL = 0x8000981209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL4_O_PL = 0x8000981209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL5_EO_PL = 0x8000281209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL5_EO_PL = 0x8000281209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL5_O_PL = 0x8000A01209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL5_O_PL = 0x8000A01209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL6_EO_PL = 0x8000301209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL6_EO_PL = 0x8000301209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL6_O_PL = 0x8000A81209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL6_O_PL = 0x8000A81209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL7_EO_PL = 0x8000381209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL7_EO_PL = 0x8000381209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL7_O_PL = 0x8000B01209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL7_O_PL = 0x8000B01209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL8_EO_PL = 0x8000401209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL8_EO_PL = 0x8000401209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL8_O_PL = 0x8000B81209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL8_O_PL = 0x8000B81209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL9_O_PL = 0x8000C01209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL9_O_PL = 0x8000C01209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DATA_DAC_SPARE_MODE_PL = 0x8000001209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x8000001209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_FIR_ERROR_INJECT_PL = 0x8002181209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_FIR_ERROR_INJECT_PL = 0x8002181209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_FIR_MASK_PL = 0x8002101209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_FIR_MASK_PL = 0x8002101209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_FIR_PL = 0x8002081209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_FIR_PL = 0x8002081209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_SPARE_MODE_PL = 0x8002001209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_SPARE_MODE_PL = 0x8002001209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL2_EO_PL = 0x8002481309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL2_EO_PL = 0x8002481309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL3_EO_PL = 0x8002501309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL3_EO_PL = 0x8002501309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL4_EO_PL = 0x8002581309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL4_EO_PL = 0x8002581309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL5_EO_PL = 0x8002601309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL5_EO_PL = 0x8002601309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_CNTLX1_EO_PL = 0x8002401309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_CNTLX1_EO_PL = 0x8002401309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_MODE1_EO_PL = 0x8002201309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_MODE1_EO_PL = 0x8002201309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_MODE2_EO_PL = 0x8002281309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_MODE2_EO_PL = 0x8002281309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_MODE3_EO_PL = 0x8002301309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_MODE3_EO_PL = 0x8002301309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_MODE4_EO_PL = 0x8002381309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_MODE4_EO_PL = 0x8002381309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_STAT1_EO_PL = 0x8002681309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_STAT1_EO_PL = 0x8002681309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_STAT1_O_PL = 0x8003181309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_STAT1_O_PL = 0x8003181309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_STAT2_EO_PL = 0x8002701309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_STAT2_EO_PL = 0x8002701309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_STAT3_EO_PL = 0x8002781309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_STAT3_EO_PL = 0x8002781309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_STAT4_EO_PL = 0x8002801309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_STAT4_EO_PL = 0x8002801309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL10_O_PL = 0x8000C81309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL10_O_PL = 0x8000C81309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL1_EO_PL = 0x8000081309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL1_EO_PL = 0x8000081309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL1_O_PL = 0x8000801309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL1_O_PL = 0x8000801309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL2_EO_PL = 0x8000101309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL2_EO_PL = 0x8000101309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL2_O_PL = 0x8000881309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL2_O_PL = 0x8000881309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL3_EO_PL = 0x8000181309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL3_EO_PL = 0x8000181309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL3_O_PL = 0x8000901309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL3_O_PL = 0x8000901309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL4_EO_PL = 0x8000201309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL4_EO_PL = 0x8000201309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL4_O_PL = 0x8000981309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL4_O_PL = 0x8000981309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL5_EO_PL = 0x8000281309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL5_EO_PL = 0x8000281309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL5_O_PL = 0x8000A01309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL5_O_PL = 0x8000A01309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL6_EO_PL = 0x8000301309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL6_EO_PL = 0x8000301309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL6_O_PL = 0x8000A81309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL6_O_PL = 0x8000A81309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL7_EO_PL = 0x8000381309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL7_EO_PL = 0x8000381309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL7_O_PL = 0x8000B01309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL7_O_PL = 0x8000B01309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL8_EO_PL = 0x8000401309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL8_EO_PL = 0x8000401309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL8_O_PL = 0x8000B81309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL8_O_PL = 0x8000B81309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL9_O_PL = 0x8000C01309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL9_O_PL = 0x8000C01309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DATA_DAC_SPARE_MODE_PL = 0x8000001309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x8000001309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_FIR_ERROR_INJECT_PL = 0x8002181309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_FIR_ERROR_INJECT_PL = 0x8002181309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_FIR_MASK_PL = 0x8002101309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_FIR_MASK_PL = 0x8002101309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_FIR_PL = 0x8002081309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_FIR_PL = 0x8002081309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_SPARE_MODE_PL = 0x8002001309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_SPARE_MODE_PL = 0x8002001309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL2_EO_PL = 0x8002481409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL2_EO_PL = 0x8002481409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL3_EO_PL = 0x8002501409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL3_EO_PL = 0x8002501409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL4_EO_PL = 0x8002581409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL4_EO_PL = 0x8002581409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL5_EO_PL = 0x8002601409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL5_EO_PL = 0x8002601409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_CNTLX1_EO_PL = 0x8002401409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_CNTLX1_EO_PL = 0x8002401409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_MODE1_EO_PL = 0x8002201409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_MODE1_EO_PL = 0x8002201409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_MODE2_EO_PL = 0x8002281409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_MODE2_EO_PL = 0x8002281409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_MODE3_EO_PL = 0x8002301409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_MODE3_EO_PL = 0x8002301409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_MODE4_EO_PL = 0x8002381409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_MODE4_EO_PL = 0x8002381409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_STAT1_EO_PL = 0x8002681409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_STAT1_EO_PL = 0x8002681409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_STAT1_O_PL = 0x8003181409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_STAT1_O_PL = 0x8003181409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_STAT2_EO_PL = 0x8002701409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_STAT2_EO_PL = 0x8002701409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_STAT3_EO_PL = 0x8002781409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_STAT3_EO_PL = 0x8002781409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_STAT4_EO_PL = 0x8002801409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_STAT4_EO_PL = 0x8002801409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL10_O_PL = 0x8000C81409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL10_O_PL = 0x8000C81409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL1_EO_PL = 0x8000081409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL1_EO_PL = 0x8000081409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL1_O_PL = 0x8000801409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL1_O_PL = 0x8000801409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL2_EO_PL = 0x8000101409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL2_EO_PL = 0x8000101409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL2_O_PL = 0x8000881409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL2_O_PL = 0x8000881409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL3_EO_PL = 0x8000181409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL3_EO_PL = 0x8000181409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL3_O_PL = 0x8000901409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL3_O_PL = 0x8000901409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL4_EO_PL = 0x8000201409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL4_EO_PL = 0x8000201409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL4_O_PL = 0x8000981409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL4_O_PL = 0x8000981409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL5_EO_PL = 0x8000281409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL5_EO_PL = 0x8000281409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL5_O_PL = 0x8000A01409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL5_O_PL = 0x8000A01409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL6_EO_PL = 0x8000301409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL6_EO_PL = 0x8000301409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL6_O_PL = 0x8000A81409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL6_O_PL = 0x8000A81409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL7_EO_PL = 0x8000381409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL7_EO_PL = 0x8000381409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL7_O_PL = 0x8000B01409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL7_O_PL = 0x8000B01409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL8_EO_PL = 0x8000401409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL8_EO_PL = 0x8000401409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL8_O_PL = 0x8000B81409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL8_O_PL = 0x8000B81409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL9_O_PL = 0x8000C01409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL9_O_PL = 0x8000C01409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DATA_DAC_SPARE_MODE_PL = 0x8000001409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x8000001409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_FIR_ERROR_INJECT_PL = 0x8002181409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_FIR_ERROR_INJECT_PL = 0x8002181409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_FIR_MASK_PL = 0x8002101409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_FIR_MASK_PL = 0x8002101409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_FIR_PL = 0x8002081409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_FIR_PL = 0x8002081409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_SPARE_MODE_PL = 0x8002001409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_SPARE_MODE_PL = 0x8002001409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL2_EO_PL = 0x8002481509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL2_EO_PL = 0x8002481509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL3_EO_PL = 0x8002501509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL3_EO_PL = 0x8002501509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL4_EO_PL = 0x8002581509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL4_EO_PL = 0x8002581509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL5_EO_PL = 0x8002601509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL5_EO_PL = 0x8002601509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_CNTLX1_EO_PL = 0x8002401509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_CNTLX1_EO_PL = 0x8002401509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_MODE1_EO_PL = 0x8002201509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_MODE1_EO_PL = 0x8002201509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_MODE2_EO_PL = 0x8002281509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_MODE2_EO_PL = 0x8002281509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_MODE3_EO_PL = 0x8002301509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_MODE3_EO_PL = 0x8002301509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_MODE4_EO_PL = 0x8002381509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_MODE4_EO_PL = 0x8002381509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_STAT1_EO_PL = 0x8002681509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_STAT1_EO_PL = 0x8002681509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_STAT1_O_PL = 0x8003181509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_STAT1_O_PL = 0x8003181509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_STAT2_EO_PL = 0x8002701509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_STAT2_EO_PL = 0x8002701509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_STAT3_EO_PL = 0x8002781509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_STAT3_EO_PL = 0x8002781509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_STAT4_EO_PL = 0x8002801509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_STAT4_EO_PL = 0x8002801509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL10_O_PL = 0x8000C81509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL10_O_PL = 0x8000C81509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL1_EO_PL = 0x8000081509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL1_EO_PL = 0x8000081509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL1_O_PL = 0x8000801509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL1_O_PL = 0x8000801509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL2_EO_PL = 0x8000101509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL2_EO_PL = 0x8000101509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL2_O_PL = 0x8000881509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL2_O_PL = 0x8000881509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL3_EO_PL = 0x8000181509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL3_EO_PL = 0x8000181509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL3_O_PL = 0x8000901509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL3_O_PL = 0x8000901509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL4_EO_PL = 0x8000201509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL4_EO_PL = 0x8000201509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL4_O_PL = 0x8000981509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL4_O_PL = 0x8000981509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL5_EO_PL = 0x8000281509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL5_EO_PL = 0x8000281509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL5_O_PL = 0x8000A01509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL5_O_PL = 0x8000A01509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL6_EO_PL = 0x8000301509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL6_EO_PL = 0x8000301509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL6_O_PL = 0x8000A81509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL6_O_PL = 0x8000A81509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL7_EO_PL = 0x8000381509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL7_EO_PL = 0x8000381509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL7_O_PL = 0x8000B01509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL7_O_PL = 0x8000B01509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL8_EO_PL = 0x8000401509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL8_EO_PL = 0x8000401509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL8_O_PL = 0x8000B81509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL8_O_PL = 0x8000B81509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL9_O_PL = 0x8000C01509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL9_O_PL = 0x8000C01509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DATA_DAC_SPARE_MODE_PL = 0x8000001509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x8000001509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_FIR_ERROR_INJECT_PL = 0x8002181509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_FIR_ERROR_INJECT_PL = 0x8002181509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_FIR_MASK_PL = 0x8002101509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_FIR_MASK_PL = 0x8002101509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_FIR_PL = 0x8002081509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_FIR_PL = 0x8002081509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_SPARE_MODE_PL = 0x8002001509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_SPARE_MODE_PL = 0x8002001509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL2_EO_PL = 0x8002481609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL2_EO_PL = 0x8002481609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL3_EO_PL = 0x8002501609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL3_EO_PL = 0x8002501609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL4_EO_PL = 0x8002581609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL4_EO_PL = 0x8002581609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL5_EO_PL = 0x8002601609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL5_EO_PL = 0x8002601609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_CNTLX1_EO_PL = 0x8002401609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_CNTLX1_EO_PL = 0x8002401609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_MODE1_EO_PL = 0x8002201609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_MODE1_EO_PL = 0x8002201609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_MODE2_EO_PL = 0x8002281609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_MODE2_EO_PL = 0x8002281609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_MODE3_EO_PL = 0x8002301609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_MODE3_EO_PL = 0x8002301609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_MODE4_EO_PL = 0x8002381609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_MODE4_EO_PL = 0x8002381609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_STAT1_EO_PL = 0x8002681609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_STAT1_EO_PL = 0x8002681609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_STAT1_O_PL = 0x8003181609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_STAT1_O_PL = 0x8003181609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_STAT2_EO_PL = 0x8002701609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_STAT2_EO_PL = 0x8002701609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_STAT3_EO_PL = 0x8002781609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_STAT3_EO_PL = 0x8002781609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_STAT4_EO_PL = 0x8002801609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_STAT4_EO_PL = 0x8002801609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL10_O_PL = 0x8000C81609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL10_O_PL = 0x8000C81609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL1_EO_PL = 0x8000081609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL1_EO_PL = 0x8000081609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL1_O_PL = 0x8000801609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL1_O_PL = 0x8000801609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL2_EO_PL = 0x8000101609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL2_EO_PL = 0x8000101609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL2_O_PL = 0x8000881609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL2_O_PL = 0x8000881609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL3_EO_PL = 0x8000181609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL3_EO_PL = 0x8000181609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL3_O_PL = 0x8000901609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL3_O_PL = 0x8000901609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL4_EO_PL = 0x8000201609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL4_EO_PL = 0x8000201609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL4_O_PL = 0x8000981609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL4_O_PL = 0x8000981609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL5_EO_PL = 0x8000281609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL5_EO_PL = 0x8000281609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL5_O_PL = 0x8000A01609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL5_O_PL = 0x8000A01609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL6_EO_PL = 0x8000301609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL6_EO_PL = 0x8000301609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL6_O_PL = 0x8000A81609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL6_O_PL = 0x8000A81609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL7_EO_PL = 0x8000381609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL7_EO_PL = 0x8000381609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL7_O_PL = 0x8000B01609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL7_O_PL = 0x8000B01609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL8_EO_PL = 0x8000401609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL8_EO_PL = 0x8000401609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL8_O_PL = 0x8000B81609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL8_O_PL = 0x8000B81609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL9_O_PL = 0x8000C01609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL9_O_PL = 0x8000C01609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DATA_DAC_SPARE_MODE_PL = 0x8000001609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x8000001609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_FIR_ERROR_INJECT_PL = 0x8002181609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_FIR_ERROR_INJECT_PL = 0x8002181609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_FIR_MASK_PL = 0x8002101609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_FIR_MASK_PL = 0x8002101609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_FIR_PL = 0x8002081609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_FIR_PL = 0x8002081609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_SPARE_MODE_PL = 0x8002001609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_SPARE_MODE_PL = 0x8002001609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL2_EO_PL = 0x8002481709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL2_EO_PL = 0x8002481709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL3_EO_PL = 0x8002501709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL3_EO_PL = 0x8002501709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL4_EO_PL = 0x8002581709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL4_EO_PL = 0x8002581709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL5_EO_PL = 0x8002601709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL5_EO_PL = 0x8002601709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_CNTLX1_EO_PL = 0x8002401709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_CNTLX1_EO_PL = 0x8002401709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_MODE1_EO_PL = 0x8002201709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_MODE1_EO_PL = 0x8002201709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_MODE2_EO_PL = 0x8002281709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_MODE2_EO_PL = 0x8002281709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_MODE3_EO_PL = 0x8002301709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_MODE3_EO_PL = 0x8002301709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_MODE4_EO_PL = 0x8002381709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_MODE4_EO_PL = 0x8002381709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_STAT1_EO_PL = 0x8002681709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_STAT1_EO_PL = 0x8002681709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_STAT1_O_PL = 0x8003181709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_STAT1_O_PL = 0x8003181709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_STAT2_EO_PL = 0x8002701709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_STAT2_EO_PL = 0x8002701709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_STAT3_EO_PL = 0x8002781709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_STAT3_EO_PL = 0x8002781709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_STAT4_EO_PL = 0x8002801709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_STAT4_EO_PL = 0x8002801709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL10_O_PL = 0x8000C81709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL10_O_PL = 0x8000C81709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL1_EO_PL = 0x8000081709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL1_EO_PL = 0x8000081709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL1_O_PL = 0x8000801709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL1_O_PL = 0x8000801709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL2_EO_PL = 0x8000101709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL2_EO_PL = 0x8000101709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL2_O_PL = 0x8000881709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL2_O_PL = 0x8000881709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL3_EO_PL = 0x8000181709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL3_EO_PL = 0x8000181709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL3_O_PL = 0x8000901709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL3_O_PL = 0x8000901709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL4_EO_PL = 0x8000201709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL4_EO_PL = 0x8000201709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL4_O_PL = 0x8000981709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL4_O_PL = 0x8000981709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL5_EO_PL = 0x8000281709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL5_EO_PL = 0x8000281709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL5_O_PL = 0x8000A01709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL5_O_PL = 0x8000A01709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL6_EO_PL = 0x8000301709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL6_EO_PL = 0x8000301709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL6_O_PL = 0x8000A81709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL6_O_PL = 0x8000A81709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL7_EO_PL = 0x8000381709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL7_EO_PL = 0x8000381709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL7_O_PL = 0x8000B01709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL7_O_PL = 0x8000B01709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL8_EO_PL = 0x8000401709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL8_EO_PL = 0x8000401709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL8_O_PL = 0x8000B81709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL8_O_PL = 0x8000B81709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL9_O_PL = 0x8000C01709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL9_O_PL = 0x8000C01709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DATA_DAC_SPARE_MODE_PL = 0x8000001709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x8000001709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_FIR_ERROR_INJECT_PL = 0x8002181709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_FIR_ERROR_INJECT_PL = 0x8002181709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_FIR_MASK_PL = 0x8002101709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_FIR_MASK_PL = 0x8002101709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_FIR_PL = 0x8002081709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_FIR_PL = 0x8002081709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_SPARE_MODE_PL = 0x8002001709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_SPARE_MODE_PL = 0x8002001709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL10_EO_PG = 0x8009200009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL10_EO_PG = 0x8009200009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL11_EO_PG = 0x8009280009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL11_EO_PG = 0x8009280009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL12_EO_PG = 0x8009300009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL12_EO_PG = 0x8009300009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL13_EO_PG = 0x8009380009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL13_EO_PG = 0x8009380009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL14_EO_PG = 0x8009400009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL14_EO_PG = 0x8009400009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL1_EO_PG = 0x8008D80009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL1_EO_PG = 0x8008D80009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL2_EO_PG = 0x8008E00009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL2_EO_PG = 0x8008E00009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL3_EO_PG = 0x8008E80009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL3_EO_PG = 0x8008E80009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL4_EO_PG = 0x8008F00009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL4_EO_PG = 0x8008F00009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL5_EO_PG = 0x8008F80009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL5_EO_PG = 0x8008F80009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL6_EO_PG = 0x8009000009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL6_EO_PG = 0x8009000009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL8_EO_PG = 0x8009100009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL8_EO_PG = 0x8009100009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL9_EO_PG = 0x8009180009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL9_EO_PG = 0x8009180009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTLX7_EO_PG = 0x8009080009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTLX7_EO_PG = 0x8009080009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE10_EO_PG = 0x8008580009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE10_EO_PG = 0x8008580009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE11_EO_PG = 0x8008600009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE11_EO_PG = 0x8008600009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE12_EO_PG = 0x8008680009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE12_EO_PG = 0x8008680009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE13_EO_PG = 0x8008700009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE13_EO_PG = 0x8008700009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE14_EO_PG = 0x8008780009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE14_EO_PG = 0x8008780009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE15_EO_PG = 0x8008800009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE15_EO_PG = 0x8008800009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE16_EO_PG = 0x8008880009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE16_EO_PG = 0x8008880009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE17_EO_PG = 0x8008900009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE17_EO_PG = 0x8008900009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE18_EO_PG = 0x8008980009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE18_EO_PG = 0x8008980009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE19_EO_PG = 0x8008A00009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE19_EO_PG = 0x8008A00009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE1_EO_PG = 0x8008100009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE1_EO_PG = 0x8008100009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE1_O_PG = 0x8009B00009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE1_O_PG = 0x8009B00009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE20_EO_PG = 0x8008A80009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE20_EO_PG = 0x8008A80009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE21_EO_PG = 0x8008B00009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE21_EO_PG = 0x8008B00009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE22_EO_PG = 0x8008B80009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE22_EO_PG = 0x8008B80009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE23_EO_PG = 0x8008C00009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE23_EO_PG = 0x8008C00009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE24_EO_PG = 0x8008C80009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE24_EO_PG = 0x8008C80009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE26_EO_PG = 0x8009680009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE26_EO_PG = 0x8009680009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE27_EO_PG = 0x8009700009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE27_EO_PG = 0x8009700009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE28_EO_PG = 0x8009780009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE28_EO_PG = 0x8009780009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE29_EO_PG = 0x8008D00009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE29_EO_PG = 0x8008D00009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE2_EO_PG = 0x8008180009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE2_EO_PG = 0x8008180009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE2_O_PG = 0x8009880009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE2_O_PG = 0x8009880009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE5_EO_PG = 0x8008300009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE5_EO_PG = 0x8008300009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE6_EO_PG = 0x8008380009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE6_EO_PG = 0x8008380009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE7_EO_PG = 0x8008400009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE7_EO_PG = 0x8008400009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE9_EO_PG = 0x8008500009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE9_EO_PG = 0x8008500009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_STAT1_EO_PG = 0x8009500009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RX_CTL_STAT1_EO_PG = 0x8009500009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_STAT2_EO_PG = 0x8009580009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RX_CTL_STAT2_EO_PG = 0x8009580009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_DATASM_CNTLX1_EO_PG = 0x800B880009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RX_DATASM_CNTLX1_EO_PG = 0x800B880009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_DATASM_SPARE_MODE_PG = 0x800B800009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RX_DATASM_SPARE_MODE_PG = 0x800B800009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_DATASM_STAT10_EO_PG = 0x800BD80009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RX_DATASM_STAT10_EO_PG = 0x800BD80009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_DATASM_STAT11_EO_PG = 0x800BE00009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RX_DATASM_STAT11_EO_PG = 0x800BE00009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_DATASM_STAT1_EO_PG = 0x800B900009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RX_DATASM_STAT1_EO_PG = 0x800B900009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_DATASM_STAT2_EO_PG = 0x800B980009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RX_DATASM_STAT2_EO_PG = 0x800B980009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_DATASM_STAT3_EO_PG = 0x800BA00009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RX_DATASM_STAT3_EO_PG = 0x800BA00009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_DATASM_STAT4_EO_PG = 0x800BA80009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RX_DATASM_STAT4_EO_PG = 0x800BA80009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_DATASM_STAT5_EO_PG = 0x800BB00009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RX_DATASM_STAT5_EO_PG = 0x800BB00009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_DATASM_STAT6_EO_PG = 0x800BB80009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RX_DATASM_STAT6_EO_PG = 0x800BB80009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_DATASM_STAT7_EO_PG = 0x800BC00009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RX_DATASM_STAT7_EO_PG = 0x800BC00009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_DATASM_STAT8_EO_PG = 0x800BC80009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RX_DATASM_STAT8_EO_PG = 0x800BC80009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_DATASM_STAT9_EO_PG = 0x800BD00009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RX_DATASM_STAT9_EO_PG = 0x800BD00009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_FIR1_ERROR_INJECT_PG = 0x800A980009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RX_FIR1_ERROR_INJECT_PG = 0x800A980009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_FIR1_MASK_PG = 0x800A900009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RX_FIR1_MASK_PG = 0x800A900009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_FIR1_PG = 0x800A880009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RX_FIR1_PG = 0x800A880009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_GLBSM_CNTL2_EO_PG = 0x800AE00009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RX_GLBSM_CNTL2_EO_PG = 0x800AE00009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_GLBSM_CNTL3_EO_PG = 0x800AE80009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RX_GLBSM_CNTL3_EO_PG = 0x800AE80009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_GLBSM_CNTL4_EO_PG = 0x800AF00009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RX_GLBSM_CNTL4_EO_PG = 0x800AF00009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_GLBSM_CNTLX1_EO_PG = 0x800AB00009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RX_GLBSM_CNTLX1_EO_PG = 0x800AB00009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_GLBSM_MODE1_EO_PG = 0x800AF80009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RX_GLBSM_MODE1_EO_PG = 0x800AF80009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_GLBSM_SPARE_MODE_PG = 0x800A800009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RX_GLBSM_SPARE_MODE_PG = 0x800A800009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_GLBSM_STAT1_EO_PG = 0x800AB80009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RX_GLBSM_STAT1_EO_PG = 0x800AB80009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_GLBSM_STAT2_EO_PG = 0x800AC00009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RX_GLBSM_STAT2_EO_PG = 0x800AC00009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_GLBSM_STAT3_EO_PG = 0x800AC80009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RX_GLBSM_STAT3_EO_PG = 0x800AC80009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_GLBSM_STAT4_EO_PG = 0x800AD00009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RX_GLBSM_STAT4_EO_PG = 0x800AD00009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_GLBSM_STAT5_EO_PG = 0x800AD80009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RX_GLBSM_STAT5_EO_PG = 0x800AD80009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_ID1_PG = 0x8008080009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RX_ID1_PG = 0x8008080009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_SPARE_MODE_PG = 0x8008000009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_RX_SPARE_MODE_PG = 0x8008000009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE0_RX_DATA_WORK_SPARE_MODE_PL = 0x8003800009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE0_RX_DATA_WORK_SPARE_MODE_PL = 0x8003800009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE0_RX_GLBSM_PL_CNTL1X_O_PL = 0x8003300009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE0_RX_GLBSM_PL_CNTL1X_O_PL = 0x8003300009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE0_RX_GLBSM_PL_CNTL1_O_PL = 0x8003200009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE0_RX_GLBSM_PL_CNTL1_O_PL = 0x8003200009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE0_RX_GLBSM_PL_STAT1_O_PL = 0x8003280009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE0_RX_GLBSM_PL_STAT1_O_PL = 0x8003280009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE0_RX_WORK_CNTL1_O_PL = 0x8003A80009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE0_RX_WORK_CNTL1_O_PL = 0x8003A80009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE0_RX_WORK_STAT1_EO_PL = 0x8003880009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE0_RX_WORK_STAT1_EO_PL = 0x8003880009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE0_RX_WORK_STAT2_EO_PL = 0x8003900009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE0_RX_WORK_STAT2_EO_PL = 0x8003900009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE0_RX_WORK_STAT3_EO_PL = 0x8003980009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE0_RX_WORK_STAT3_EO_PL = 0x8003980009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE0_RX_WORK_STAT4_O_PL = 0x8003A00009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE0_RX_WORK_STAT4_O_PL = 0x8003A00009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE10_RX_DATA_WORK_SPARE_MODE_PL = 0x8003800A09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE10_RX_DATA_WORK_SPARE_MODE_PL = 0x8003800A09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE10_RX_GLBSM_PL_CNTL1X_O_PL = 0x8003300A09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE10_RX_GLBSM_PL_CNTL1X_O_PL = 0x8003300A09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE10_RX_GLBSM_PL_CNTL1_O_PL = 0x8003200A09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE10_RX_GLBSM_PL_CNTL1_O_PL = 0x8003200A09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE10_RX_GLBSM_PL_STAT1_O_PL = 0x8003280A09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE10_RX_GLBSM_PL_STAT1_O_PL = 0x8003280A09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE10_RX_WORK_CNTL1_O_PL = 0x8003A80A09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE10_RX_WORK_CNTL1_O_PL = 0x8003A80A09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE10_RX_WORK_STAT1_EO_PL = 0x8003880A09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE10_RX_WORK_STAT1_EO_PL = 0x8003880A09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE10_RX_WORK_STAT2_EO_PL = 0x8003900A09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE10_RX_WORK_STAT2_EO_PL = 0x8003900A09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE10_RX_WORK_STAT3_EO_PL = 0x8003980A09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE10_RX_WORK_STAT3_EO_PL = 0x8003980A09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE10_RX_WORK_STAT4_O_PL = 0x8003A00A09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE10_RX_WORK_STAT4_O_PL = 0x8003A00A09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE11_RX_DATA_WORK_SPARE_MODE_PL = 0x8003800B09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE11_RX_DATA_WORK_SPARE_MODE_PL = 0x8003800B09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE11_RX_GLBSM_PL_CNTL1X_O_PL = 0x8003300B09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE11_RX_GLBSM_PL_CNTL1X_O_PL = 0x8003300B09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE11_RX_GLBSM_PL_CNTL1_O_PL = 0x8003200B09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE11_RX_GLBSM_PL_CNTL1_O_PL = 0x8003200B09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE11_RX_GLBSM_PL_STAT1_O_PL = 0x8003280B09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE11_RX_GLBSM_PL_STAT1_O_PL = 0x8003280B09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE11_RX_WORK_CNTL1_O_PL = 0x8003A80B09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE11_RX_WORK_CNTL1_O_PL = 0x8003A80B09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE11_RX_WORK_STAT1_EO_PL = 0x8003880B09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE11_RX_WORK_STAT1_EO_PL = 0x8003880B09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE11_RX_WORK_STAT2_EO_PL = 0x8003900B09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE11_RX_WORK_STAT2_EO_PL = 0x8003900B09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE11_RX_WORK_STAT3_EO_PL = 0x8003980B09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE11_RX_WORK_STAT3_EO_PL = 0x8003980B09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE11_RX_WORK_STAT4_O_PL = 0x8003A00B09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE11_RX_WORK_STAT4_O_PL = 0x8003A00B09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE12_RX_DATA_WORK_SPARE_MODE_PL = 0x8003800C09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE12_RX_DATA_WORK_SPARE_MODE_PL = 0x8003800C09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE12_RX_GLBSM_PL_CNTL1X_O_PL = 0x8003300C09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE12_RX_GLBSM_PL_CNTL1X_O_PL = 0x8003300C09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE12_RX_GLBSM_PL_CNTL1_O_PL = 0x8003200C09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE12_RX_GLBSM_PL_CNTL1_O_PL = 0x8003200C09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE12_RX_GLBSM_PL_STAT1_O_PL = 0x8003280C09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE12_RX_GLBSM_PL_STAT1_O_PL = 0x8003280C09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE12_RX_WORK_CNTL1_O_PL = 0x8003A80C09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE12_RX_WORK_CNTL1_O_PL = 0x8003A80C09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE12_RX_WORK_STAT1_EO_PL = 0x8003880C09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE12_RX_WORK_STAT1_EO_PL = 0x8003880C09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE12_RX_WORK_STAT2_EO_PL = 0x8003900C09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE12_RX_WORK_STAT2_EO_PL = 0x8003900C09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE12_RX_WORK_STAT3_EO_PL = 0x8003980C09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE12_RX_WORK_STAT3_EO_PL = 0x8003980C09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE12_RX_WORK_STAT4_O_PL = 0x8003A00C09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE12_RX_WORK_STAT4_O_PL = 0x8003A00C09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE13_RX_DATA_WORK_SPARE_MODE_PL = 0x8003800D09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE13_RX_DATA_WORK_SPARE_MODE_PL = 0x8003800D09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE13_RX_GLBSM_PL_CNTL1X_O_PL = 0x8003300D09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE13_RX_GLBSM_PL_CNTL1X_O_PL = 0x8003300D09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE13_RX_GLBSM_PL_CNTL1_O_PL = 0x8003200D09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE13_RX_GLBSM_PL_CNTL1_O_PL = 0x8003200D09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE13_RX_GLBSM_PL_STAT1_O_PL = 0x8003280D09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE13_RX_GLBSM_PL_STAT1_O_PL = 0x8003280D09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE13_RX_WORK_CNTL1_O_PL = 0x8003A80D09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE13_RX_WORK_CNTL1_O_PL = 0x8003A80D09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE13_RX_WORK_STAT1_EO_PL = 0x8003880D09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE13_RX_WORK_STAT1_EO_PL = 0x8003880D09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE13_RX_WORK_STAT2_EO_PL = 0x8003900D09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE13_RX_WORK_STAT2_EO_PL = 0x8003900D09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE13_RX_WORK_STAT3_EO_PL = 0x8003980D09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE13_RX_WORK_STAT3_EO_PL = 0x8003980D09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE13_RX_WORK_STAT4_O_PL = 0x8003A00D09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE13_RX_WORK_STAT4_O_PL = 0x8003A00D09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE14_RX_DATA_WORK_SPARE_MODE_PL = 0x8003800E09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE14_RX_DATA_WORK_SPARE_MODE_PL = 0x8003800E09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE14_RX_GLBSM_PL_CNTL1X_O_PL = 0x8003300E09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE14_RX_GLBSM_PL_CNTL1X_O_PL = 0x8003300E09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE14_RX_GLBSM_PL_CNTL1_O_PL = 0x8003200E09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE14_RX_GLBSM_PL_CNTL1_O_PL = 0x8003200E09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE14_RX_GLBSM_PL_STAT1_O_PL = 0x8003280E09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE14_RX_GLBSM_PL_STAT1_O_PL = 0x8003280E09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE14_RX_WORK_CNTL1_O_PL = 0x8003A80E09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE14_RX_WORK_CNTL1_O_PL = 0x8003A80E09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE14_RX_WORK_STAT1_EO_PL = 0x8003880E09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE14_RX_WORK_STAT1_EO_PL = 0x8003880E09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE14_RX_WORK_STAT2_EO_PL = 0x8003900E09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE14_RX_WORK_STAT2_EO_PL = 0x8003900E09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE14_RX_WORK_STAT3_EO_PL = 0x8003980E09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE14_RX_WORK_STAT3_EO_PL = 0x8003980E09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE14_RX_WORK_STAT4_O_PL = 0x8003A00E09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE14_RX_WORK_STAT4_O_PL = 0x8003A00E09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE15_RX_DATA_WORK_SPARE_MODE_PL = 0x8003800F09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE15_RX_DATA_WORK_SPARE_MODE_PL = 0x8003800F09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE15_RX_GLBSM_PL_CNTL1X_O_PL = 0x8003300F09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE15_RX_GLBSM_PL_CNTL1X_O_PL = 0x8003300F09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE15_RX_GLBSM_PL_CNTL1_O_PL = 0x8003200F09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE15_RX_GLBSM_PL_CNTL1_O_PL = 0x8003200F09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE15_RX_GLBSM_PL_STAT1_O_PL = 0x8003280F09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE15_RX_GLBSM_PL_STAT1_O_PL = 0x8003280F09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE15_RX_WORK_CNTL1_O_PL = 0x8003A80F09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE15_RX_WORK_CNTL1_O_PL = 0x8003A80F09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE15_RX_WORK_STAT1_EO_PL = 0x8003880F09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE15_RX_WORK_STAT1_EO_PL = 0x8003880F09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE15_RX_WORK_STAT2_EO_PL = 0x8003900F09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE15_RX_WORK_STAT2_EO_PL = 0x8003900F09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE15_RX_WORK_STAT3_EO_PL = 0x8003980F09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE15_RX_WORK_STAT3_EO_PL = 0x8003980F09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE15_RX_WORK_STAT4_O_PL = 0x8003A00F09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE15_RX_WORK_STAT4_O_PL = 0x8003A00F09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE16_RX_DATA_WORK_SPARE_MODE_PL = 0x8003801009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE16_RX_DATA_WORK_SPARE_MODE_PL = 0x8003801009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE16_RX_GLBSM_PL_CNTL1X_O_PL = 0x8003301009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE16_RX_GLBSM_PL_CNTL1X_O_PL = 0x8003301009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE16_RX_GLBSM_PL_CNTL1_O_PL = 0x8003201009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE16_RX_GLBSM_PL_CNTL1_O_PL = 0x8003201009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE16_RX_GLBSM_PL_STAT1_O_PL = 0x8003281009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE16_RX_GLBSM_PL_STAT1_O_PL = 0x8003281009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE16_RX_WORK_CNTL1_O_PL = 0x8003A81009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE16_RX_WORK_CNTL1_O_PL = 0x8003A81009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE16_RX_WORK_STAT1_EO_PL = 0x8003881009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE16_RX_WORK_STAT1_EO_PL = 0x8003881009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE16_RX_WORK_STAT2_EO_PL = 0x8003901009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE16_RX_WORK_STAT2_EO_PL = 0x8003901009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE16_RX_WORK_STAT3_EO_PL = 0x8003981009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE16_RX_WORK_STAT3_EO_PL = 0x8003981009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE16_RX_WORK_STAT4_O_PL = 0x8003A01009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE16_RX_WORK_STAT4_O_PL = 0x8003A01009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE17_RX_DATA_WORK_SPARE_MODE_PL = 0x8003801109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE17_RX_DATA_WORK_SPARE_MODE_PL = 0x8003801109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE17_RX_GLBSM_PL_CNTL1X_O_PL = 0x8003301109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE17_RX_GLBSM_PL_CNTL1X_O_PL = 0x8003301109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE17_RX_GLBSM_PL_CNTL1_O_PL = 0x8003201109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE17_RX_GLBSM_PL_CNTL1_O_PL = 0x8003201109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE17_RX_GLBSM_PL_STAT1_O_PL = 0x8003281109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE17_RX_GLBSM_PL_STAT1_O_PL = 0x8003281109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE17_RX_WORK_CNTL1_O_PL = 0x8003A81109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE17_RX_WORK_CNTL1_O_PL = 0x8003A81109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE17_RX_WORK_STAT1_EO_PL = 0x8003881109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE17_RX_WORK_STAT1_EO_PL = 0x8003881109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE17_RX_WORK_STAT2_EO_PL = 0x8003901109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE17_RX_WORK_STAT2_EO_PL = 0x8003901109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE17_RX_WORK_STAT3_EO_PL = 0x8003981109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE17_RX_WORK_STAT3_EO_PL = 0x8003981109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE17_RX_WORK_STAT4_O_PL = 0x8003A01109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE17_RX_WORK_STAT4_O_PL = 0x8003A01109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE18_RX_DATA_WORK_SPARE_MODE_PL = 0x8003801209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE18_RX_DATA_WORK_SPARE_MODE_PL = 0x8003801209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE18_RX_GLBSM_PL_CNTL1X_O_PL = 0x8003301209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE18_RX_GLBSM_PL_CNTL1X_O_PL = 0x8003301209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE18_RX_GLBSM_PL_CNTL1_O_PL = 0x8003201209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE18_RX_GLBSM_PL_CNTL1_O_PL = 0x8003201209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE18_RX_GLBSM_PL_STAT1_O_PL = 0x8003281209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE18_RX_GLBSM_PL_STAT1_O_PL = 0x8003281209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE18_RX_WORK_CNTL1_O_PL = 0x8003A81209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE18_RX_WORK_CNTL1_O_PL = 0x8003A81209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE18_RX_WORK_STAT1_EO_PL = 0x8003881209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE18_RX_WORK_STAT1_EO_PL = 0x8003881209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE18_RX_WORK_STAT2_EO_PL = 0x8003901209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE18_RX_WORK_STAT2_EO_PL = 0x8003901209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE18_RX_WORK_STAT3_EO_PL = 0x8003981209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE18_RX_WORK_STAT3_EO_PL = 0x8003981209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE18_RX_WORK_STAT4_O_PL = 0x8003A01209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE18_RX_WORK_STAT4_O_PL = 0x8003A01209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE19_RX_DATA_WORK_SPARE_MODE_PL = 0x8003801309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE19_RX_DATA_WORK_SPARE_MODE_PL = 0x8003801309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE19_RX_GLBSM_PL_CNTL1X_O_PL = 0x8003301309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE19_RX_GLBSM_PL_CNTL1X_O_PL = 0x8003301309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE19_RX_GLBSM_PL_CNTL1_O_PL = 0x8003201309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE19_RX_GLBSM_PL_CNTL1_O_PL = 0x8003201309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE19_RX_GLBSM_PL_STAT1_O_PL = 0x8003281309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE19_RX_GLBSM_PL_STAT1_O_PL = 0x8003281309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE19_RX_WORK_CNTL1_O_PL = 0x8003A81309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE19_RX_WORK_CNTL1_O_PL = 0x8003A81309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE19_RX_WORK_STAT1_EO_PL = 0x8003881309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE19_RX_WORK_STAT1_EO_PL = 0x8003881309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE19_RX_WORK_STAT2_EO_PL = 0x8003901309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE19_RX_WORK_STAT2_EO_PL = 0x8003901309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE19_RX_WORK_STAT3_EO_PL = 0x8003981309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE19_RX_WORK_STAT3_EO_PL = 0x8003981309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE19_RX_WORK_STAT4_O_PL = 0x8003A01309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE19_RX_WORK_STAT4_O_PL = 0x8003A01309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE1_RX_DATA_WORK_SPARE_MODE_PL = 0x8003800109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE1_RX_DATA_WORK_SPARE_MODE_PL = 0x8003800109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE1_RX_GLBSM_PL_CNTL1X_O_PL = 0x8003300109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE1_RX_GLBSM_PL_CNTL1X_O_PL = 0x8003300109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE1_RX_GLBSM_PL_CNTL1_O_PL = 0x8003200109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE1_RX_GLBSM_PL_CNTL1_O_PL = 0x8003200109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE1_RX_GLBSM_PL_STAT1_O_PL = 0x8003280109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE1_RX_GLBSM_PL_STAT1_O_PL = 0x8003280109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE1_RX_WORK_CNTL1_O_PL = 0x8003A80109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE1_RX_WORK_CNTL1_O_PL = 0x8003A80109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE1_RX_WORK_STAT1_EO_PL = 0x8003880109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE1_RX_WORK_STAT1_EO_PL = 0x8003880109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE1_RX_WORK_STAT2_EO_PL = 0x8003900109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE1_RX_WORK_STAT2_EO_PL = 0x8003900109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE1_RX_WORK_STAT3_EO_PL = 0x8003980109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE1_RX_WORK_STAT3_EO_PL = 0x8003980109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE1_RX_WORK_STAT4_O_PL = 0x8003A00109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE1_RX_WORK_STAT4_O_PL = 0x8003A00109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE20_RX_DATA_WORK_SPARE_MODE_PL = 0x8003801409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE20_RX_DATA_WORK_SPARE_MODE_PL = 0x8003801409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE20_RX_GLBSM_PL_CNTL1X_O_PL = 0x8003301409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE20_RX_GLBSM_PL_CNTL1X_O_PL = 0x8003301409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE20_RX_GLBSM_PL_CNTL1_O_PL = 0x8003201409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE20_RX_GLBSM_PL_CNTL1_O_PL = 0x8003201409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE20_RX_GLBSM_PL_STAT1_O_PL = 0x8003281409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE20_RX_GLBSM_PL_STAT1_O_PL = 0x8003281409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE20_RX_WORK_CNTL1_O_PL = 0x8003A81409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE20_RX_WORK_CNTL1_O_PL = 0x8003A81409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE20_RX_WORK_STAT1_EO_PL = 0x8003881409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE20_RX_WORK_STAT1_EO_PL = 0x8003881409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE20_RX_WORK_STAT2_EO_PL = 0x8003901409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE20_RX_WORK_STAT2_EO_PL = 0x8003901409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE20_RX_WORK_STAT3_EO_PL = 0x8003981409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE20_RX_WORK_STAT3_EO_PL = 0x8003981409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE20_RX_WORK_STAT4_O_PL = 0x8003A01409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE20_RX_WORK_STAT4_O_PL = 0x8003A01409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE21_RX_DATA_WORK_SPARE_MODE_PL = 0x8003801509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE21_RX_DATA_WORK_SPARE_MODE_PL = 0x8003801509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE21_RX_GLBSM_PL_CNTL1X_O_PL = 0x8003301509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE21_RX_GLBSM_PL_CNTL1X_O_PL = 0x8003301509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE21_RX_GLBSM_PL_CNTL1_O_PL = 0x8003201509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE21_RX_GLBSM_PL_CNTL1_O_PL = 0x8003201509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE21_RX_GLBSM_PL_STAT1_O_PL = 0x8003281509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE21_RX_GLBSM_PL_STAT1_O_PL = 0x8003281509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE21_RX_WORK_CNTL1_O_PL = 0x8003A81509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE21_RX_WORK_CNTL1_O_PL = 0x8003A81509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE21_RX_WORK_STAT1_EO_PL = 0x8003881509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE21_RX_WORK_STAT1_EO_PL = 0x8003881509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE21_RX_WORK_STAT2_EO_PL = 0x8003901509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE21_RX_WORK_STAT2_EO_PL = 0x8003901509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE21_RX_WORK_STAT3_EO_PL = 0x8003981509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE21_RX_WORK_STAT3_EO_PL = 0x8003981509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE21_RX_WORK_STAT4_O_PL = 0x8003A01509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE21_RX_WORK_STAT4_O_PL = 0x8003A01509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE22_RX_DATA_WORK_SPARE_MODE_PL = 0x8003801609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE22_RX_DATA_WORK_SPARE_MODE_PL = 0x8003801609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE22_RX_GLBSM_PL_CNTL1X_O_PL = 0x8003301609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE22_RX_GLBSM_PL_CNTL1X_O_PL = 0x8003301609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE22_RX_GLBSM_PL_CNTL1_O_PL = 0x8003201609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE22_RX_GLBSM_PL_CNTL1_O_PL = 0x8003201609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE22_RX_GLBSM_PL_STAT1_O_PL = 0x8003281609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE22_RX_GLBSM_PL_STAT1_O_PL = 0x8003281609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE22_RX_WORK_CNTL1_O_PL = 0x8003A81609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE22_RX_WORK_CNTL1_O_PL = 0x8003A81609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE22_RX_WORK_STAT1_EO_PL = 0x8003881609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE22_RX_WORK_STAT1_EO_PL = 0x8003881609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE22_RX_WORK_STAT2_EO_PL = 0x8003901609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE22_RX_WORK_STAT2_EO_PL = 0x8003901609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE22_RX_WORK_STAT3_EO_PL = 0x8003981609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE22_RX_WORK_STAT3_EO_PL = 0x8003981609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE22_RX_WORK_STAT4_O_PL = 0x8003A01609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE22_RX_WORK_STAT4_O_PL = 0x8003A01609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE23_RX_DATA_WORK_SPARE_MODE_PL = 0x8003801709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE23_RX_DATA_WORK_SPARE_MODE_PL = 0x8003801709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE23_RX_GLBSM_PL_CNTL1X_O_PL = 0x8003301709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE23_RX_GLBSM_PL_CNTL1X_O_PL = 0x8003301709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE23_RX_GLBSM_PL_CNTL1_O_PL = 0x8003201709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE23_RX_GLBSM_PL_CNTL1_O_PL = 0x8003201709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE23_RX_GLBSM_PL_STAT1_O_PL = 0x8003281709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE23_RX_GLBSM_PL_STAT1_O_PL = 0x8003281709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE23_RX_WORK_CNTL1_O_PL = 0x8003A81709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE23_RX_WORK_CNTL1_O_PL = 0x8003A81709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE23_RX_WORK_STAT1_EO_PL = 0x8003881709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE23_RX_WORK_STAT1_EO_PL = 0x8003881709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE23_RX_WORK_STAT2_EO_PL = 0x8003901709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE23_RX_WORK_STAT2_EO_PL = 0x8003901709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE23_RX_WORK_STAT3_EO_PL = 0x8003981709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE23_RX_WORK_STAT3_EO_PL = 0x8003981709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE23_RX_WORK_STAT4_O_PL = 0x8003A01709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE23_RX_WORK_STAT4_O_PL = 0x8003A01709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE2_RX_DATA_WORK_SPARE_MODE_PL = 0x8003800209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE2_RX_DATA_WORK_SPARE_MODE_PL = 0x8003800209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE2_RX_GLBSM_PL_CNTL1X_O_PL = 0x8003300209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE2_RX_GLBSM_PL_CNTL1X_O_PL = 0x8003300209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE2_RX_GLBSM_PL_CNTL1_O_PL = 0x8003200209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE2_RX_GLBSM_PL_CNTL1_O_PL = 0x8003200209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE2_RX_GLBSM_PL_STAT1_O_PL = 0x8003280209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE2_RX_GLBSM_PL_STAT1_O_PL = 0x8003280209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE2_RX_WORK_CNTL1_O_PL = 0x8003A80209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE2_RX_WORK_CNTL1_O_PL = 0x8003A80209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE2_RX_WORK_STAT1_EO_PL = 0x8003880209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE2_RX_WORK_STAT1_EO_PL = 0x8003880209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE2_RX_WORK_STAT2_EO_PL = 0x8003900209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE2_RX_WORK_STAT2_EO_PL = 0x8003900209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE2_RX_WORK_STAT3_EO_PL = 0x8003980209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE2_RX_WORK_STAT3_EO_PL = 0x8003980209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE2_RX_WORK_STAT4_O_PL = 0x8003A00209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE2_RX_WORK_STAT4_O_PL = 0x8003A00209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE3_RX_DATA_WORK_SPARE_MODE_PL = 0x8003800309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE3_RX_DATA_WORK_SPARE_MODE_PL = 0x8003800309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE3_RX_GLBSM_PL_CNTL1X_O_PL = 0x8003300309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE3_RX_GLBSM_PL_CNTL1X_O_PL = 0x8003300309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE3_RX_GLBSM_PL_CNTL1_O_PL = 0x8003200309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE3_RX_GLBSM_PL_CNTL1_O_PL = 0x8003200309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE3_RX_GLBSM_PL_STAT1_O_PL = 0x8003280309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE3_RX_GLBSM_PL_STAT1_O_PL = 0x8003280309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE3_RX_WORK_CNTL1_O_PL = 0x8003A80309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE3_RX_WORK_CNTL1_O_PL = 0x8003A80309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE3_RX_WORK_STAT1_EO_PL = 0x8003880309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE3_RX_WORK_STAT1_EO_PL = 0x8003880309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE3_RX_WORK_STAT2_EO_PL = 0x8003900309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE3_RX_WORK_STAT2_EO_PL = 0x8003900309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE3_RX_WORK_STAT3_EO_PL = 0x8003980309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE3_RX_WORK_STAT3_EO_PL = 0x8003980309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE3_RX_WORK_STAT4_O_PL = 0x8003A00309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE3_RX_WORK_STAT4_O_PL = 0x8003A00309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE4_RX_DATA_WORK_SPARE_MODE_PL = 0x8003800409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE4_RX_DATA_WORK_SPARE_MODE_PL = 0x8003800409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE4_RX_GLBSM_PL_CNTL1X_O_PL = 0x8003300409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE4_RX_GLBSM_PL_CNTL1X_O_PL = 0x8003300409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE4_RX_GLBSM_PL_CNTL1_O_PL = 0x8003200409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE4_RX_GLBSM_PL_CNTL1_O_PL = 0x8003200409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE4_RX_GLBSM_PL_STAT1_O_PL = 0x8003280409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE4_RX_GLBSM_PL_STAT1_O_PL = 0x8003280409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE4_RX_WORK_CNTL1_O_PL = 0x8003A80409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE4_RX_WORK_CNTL1_O_PL = 0x8003A80409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE4_RX_WORK_STAT1_EO_PL = 0x8003880409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE4_RX_WORK_STAT1_EO_PL = 0x8003880409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE4_RX_WORK_STAT2_EO_PL = 0x8003900409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE4_RX_WORK_STAT2_EO_PL = 0x8003900409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE4_RX_WORK_STAT3_EO_PL = 0x8003980409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE4_RX_WORK_STAT3_EO_PL = 0x8003980409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE4_RX_WORK_STAT4_O_PL = 0x8003A00409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE4_RX_WORK_STAT4_O_PL = 0x8003A00409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE5_RX_DATA_WORK_SPARE_MODE_PL = 0x8003800509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE5_RX_DATA_WORK_SPARE_MODE_PL = 0x8003800509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE5_RX_GLBSM_PL_CNTL1X_O_PL = 0x8003300509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE5_RX_GLBSM_PL_CNTL1X_O_PL = 0x8003300509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE5_RX_GLBSM_PL_CNTL1_O_PL = 0x8003200509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE5_RX_GLBSM_PL_CNTL1_O_PL = 0x8003200509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE5_RX_GLBSM_PL_STAT1_O_PL = 0x8003280509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE5_RX_GLBSM_PL_STAT1_O_PL = 0x8003280509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE5_RX_WORK_CNTL1_O_PL = 0x8003A80509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE5_RX_WORK_CNTL1_O_PL = 0x8003A80509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE5_RX_WORK_STAT1_EO_PL = 0x8003880509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE5_RX_WORK_STAT1_EO_PL = 0x8003880509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE5_RX_WORK_STAT2_EO_PL = 0x8003900509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE5_RX_WORK_STAT2_EO_PL = 0x8003900509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE5_RX_WORK_STAT3_EO_PL = 0x8003980509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE5_RX_WORK_STAT3_EO_PL = 0x8003980509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE5_RX_WORK_STAT4_O_PL = 0x8003A00509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE5_RX_WORK_STAT4_O_PL = 0x8003A00509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE6_RX_DATA_WORK_SPARE_MODE_PL = 0x8003800609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE6_RX_DATA_WORK_SPARE_MODE_PL = 0x8003800609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE6_RX_GLBSM_PL_CNTL1X_O_PL = 0x8003300609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE6_RX_GLBSM_PL_CNTL1X_O_PL = 0x8003300609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE6_RX_GLBSM_PL_CNTL1_O_PL = 0x8003200609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE6_RX_GLBSM_PL_CNTL1_O_PL = 0x8003200609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE6_RX_GLBSM_PL_STAT1_O_PL = 0x8003280609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE6_RX_GLBSM_PL_STAT1_O_PL = 0x8003280609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE6_RX_WORK_CNTL1_O_PL = 0x8003A80609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE6_RX_WORK_CNTL1_O_PL = 0x8003A80609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE6_RX_WORK_STAT1_EO_PL = 0x8003880609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE6_RX_WORK_STAT1_EO_PL = 0x8003880609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE6_RX_WORK_STAT2_EO_PL = 0x8003900609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE6_RX_WORK_STAT2_EO_PL = 0x8003900609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE6_RX_WORK_STAT3_EO_PL = 0x8003980609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE6_RX_WORK_STAT3_EO_PL = 0x8003980609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE6_RX_WORK_STAT4_O_PL = 0x8003A00609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE6_RX_WORK_STAT4_O_PL = 0x8003A00609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE7_RX_DATA_WORK_SPARE_MODE_PL = 0x8003800709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE7_RX_DATA_WORK_SPARE_MODE_PL = 0x8003800709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE7_RX_GLBSM_PL_CNTL1X_O_PL = 0x8003300709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE7_RX_GLBSM_PL_CNTL1X_O_PL = 0x8003300709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE7_RX_GLBSM_PL_CNTL1_O_PL = 0x8003200709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE7_RX_GLBSM_PL_CNTL1_O_PL = 0x8003200709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE7_RX_GLBSM_PL_STAT1_O_PL = 0x8003280709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE7_RX_GLBSM_PL_STAT1_O_PL = 0x8003280709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE7_RX_WORK_CNTL1_O_PL = 0x8003A80709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE7_RX_WORK_CNTL1_O_PL = 0x8003A80709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE7_RX_WORK_STAT1_EO_PL = 0x8003880709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE7_RX_WORK_STAT1_EO_PL = 0x8003880709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE7_RX_WORK_STAT2_EO_PL = 0x8003900709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE7_RX_WORK_STAT2_EO_PL = 0x8003900709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE7_RX_WORK_STAT3_EO_PL = 0x8003980709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE7_RX_WORK_STAT3_EO_PL = 0x8003980709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE7_RX_WORK_STAT4_O_PL = 0x8003A00709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE7_RX_WORK_STAT4_O_PL = 0x8003A00709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE8_RX_DATA_WORK_SPARE_MODE_PL = 0x8003800809010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE8_RX_DATA_WORK_SPARE_MODE_PL = 0x8003800809010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE8_RX_GLBSM_PL_CNTL1X_O_PL = 0x8003300809010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE8_RX_GLBSM_PL_CNTL1X_O_PL = 0x8003300809010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE8_RX_GLBSM_PL_CNTL1_O_PL = 0x8003200809010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE8_RX_GLBSM_PL_CNTL1_O_PL = 0x8003200809010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE8_RX_GLBSM_PL_STAT1_O_PL = 0x8003280809010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE8_RX_GLBSM_PL_STAT1_O_PL = 0x8003280809010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE8_RX_WORK_CNTL1_O_PL = 0x8003A80809010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE8_RX_WORK_CNTL1_O_PL = 0x8003A80809010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE8_RX_WORK_STAT1_EO_PL = 0x8003880809010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE8_RX_WORK_STAT1_EO_PL = 0x8003880809010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE8_RX_WORK_STAT2_EO_PL = 0x8003900809010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE8_RX_WORK_STAT2_EO_PL = 0x8003900809010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE8_RX_WORK_STAT3_EO_PL = 0x8003980809010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE8_RX_WORK_STAT3_EO_PL = 0x8003980809010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE8_RX_WORK_STAT4_O_PL = 0x8003A00809010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE8_RX_WORK_STAT4_O_PL = 0x8003A00809010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE9_RX_DATA_WORK_SPARE_MODE_PL = 0x8003800909010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE9_RX_DATA_WORK_SPARE_MODE_PL = 0x8003800909010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE9_RX_GLBSM_PL_CNTL1X_O_PL = 0x8003300909010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE9_RX_GLBSM_PL_CNTL1X_O_PL = 0x8003300909010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE9_RX_GLBSM_PL_CNTL1_O_PL = 0x8003200909010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE9_RX_GLBSM_PL_CNTL1_O_PL = 0x8003200909010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE9_RX_GLBSM_PL_STAT1_O_PL = 0x8003280909010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE9_RX_GLBSM_PL_STAT1_O_PL = 0x8003280909010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE9_RX_WORK_CNTL1_O_PL = 0x8003A80909010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE9_RX_WORK_CNTL1_O_PL = 0x8003A80909010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE9_RX_WORK_STAT1_EO_PL = 0x8003880909010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE9_RX_WORK_STAT1_EO_PL = 0x8003880909010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE9_RX_WORK_STAT2_EO_PL = 0x8003900909010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE9_RX_WORK_STAT2_EO_PL = 0x8003900909010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE9_RX_WORK_STAT3_EO_PL = 0x8003980909010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE9_RX_WORK_STAT3_EO_PL = 0x8003980909010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE9_RX_WORK_STAT4_O_PL = 0x8003A00909010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX0_SLICE9_RX_WORK_STAT4_O_PL = 0x8003A00909010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX_FIR_ERROR_INJECT_PB = 0x800F980009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX_FIR_ERROR_INJECT_PB = 0x800F980009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX_FIR_MASK_PB = 0x800F900009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX_FIR_MASK_PB = 0x800F900009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX_FIR_PB = 0x800F880009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX_FIR_PB = 0x800F880009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX_FIR_RESET_PB = 0x800F800009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_RX_FIR_RESET_PB = 0x800F800009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_SCOM_MODE_PB = 0x09010C20ull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_SCOM_MODE_PB = 0x09010C20ull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_SPARE_MODE_PB = 0x800F340009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_SPARE_MODE_PB = 0x800F340009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE0_TX_CNTL1G_PL = 0x8004140009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE0_TX_CNTL1G_PL = 0x8004140009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE0_TX_CNTL2_O_PL = 0x80044C0009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE0_TX_CNTL2_O_PL = 0x80044C0009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE0_TX_CNTL3_EO_PL = 0x8004540009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE0_TX_CNTL3_EO_PL = 0x8004540009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE0_TX_FIR_ERROR_INJECT_PL = 0x8004340009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE0_TX_FIR_ERROR_INJECT_PL = 0x8004340009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE0_TX_FIR_MASK_PL = 0x80042C0009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE0_TX_FIR_MASK_PL = 0x80042C0009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE0_TX_FIR_PL = 0x8004240009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE0_TX_FIR_PL = 0x8004240009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE0_TX_MODE1_PL = 0x8004040009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE0_TX_MODE1_PL = 0x8004040009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE0_TX_MODE2_PL = 0x80040C0009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE0_TX_MODE2_PL = 0x80040C0009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE0_TX_STAT1_PL = 0x80041C0009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE0_TX_STAT1_PL = 0x80041C0009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE1_TX_CNTL1G_PL = 0x8004140109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE1_TX_CNTL1G_PL = 0x8004140109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE1_TX_CNTL2_O_PL = 0x80044C0109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE1_TX_CNTL2_O_PL = 0x80044C0109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE1_TX_CNTL3_EO_PL = 0x8004540109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE1_TX_CNTL3_EO_PL = 0x8004540109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE1_TX_FIR_ERROR_INJECT_PL = 0x8004340109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE1_TX_FIR_ERROR_INJECT_PL = 0x8004340109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE1_TX_FIR_MASK_PL = 0x80042C0109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE1_TX_FIR_MASK_PL = 0x80042C0109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE1_TX_FIR_PL = 0x8004240109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE1_TX_FIR_PL = 0x8004240109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE1_TX_MODE1_PL = 0x8004040109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE1_TX_MODE1_PL = 0x8004040109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE1_TX_MODE2_PL = 0x80040C0109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE1_TX_MODE2_PL = 0x80040C0109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE1_TX_STAT1_PL = 0x80041C0109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE1_TX_STAT1_PL = 0x80041C0109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE2_TX_CNTL1G_PL = 0x8004140209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE2_TX_CNTL1G_PL = 0x8004140209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE2_TX_CNTL2_O_PL = 0x80044C0209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE2_TX_CNTL2_O_PL = 0x80044C0209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE2_TX_CNTL3_EO_PL = 0x8004540209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE2_TX_CNTL3_EO_PL = 0x8004540209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE2_TX_FIR_ERROR_INJECT_PL = 0x8004340209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE2_TX_FIR_ERROR_INJECT_PL = 0x8004340209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE2_TX_FIR_MASK_PL = 0x80042C0209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE2_TX_FIR_MASK_PL = 0x80042C0209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE2_TX_FIR_PL = 0x8004240209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE2_TX_FIR_PL = 0x8004240209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE2_TX_MODE1_PL = 0x8004040209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE2_TX_MODE1_PL = 0x8004040209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE2_TX_MODE2_PL = 0x80040C0209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE2_TX_MODE2_PL = 0x80040C0209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE2_TX_STAT1_PL = 0x80041C0209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE2_TX_STAT1_PL = 0x80041C0209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE3_TX_CNTL1G_PL = 0x8004140309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE3_TX_CNTL1G_PL = 0x8004140309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE3_TX_CNTL2_O_PL = 0x80044C0309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE3_TX_CNTL2_O_PL = 0x80044C0309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE3_TX_CNTL3_EO_PL = 0x8004540309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE3_TX_CNTL3_EO_PL = 0x8004540309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE3_TX_FIR_ERROR_INJECT_PL = 0x8004340309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE3_TX_FIR_ERROR_INJECT_PL = 0x8004340309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE3_TX_FIR_MASK_PL = 0x80042C0309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE3_TX_FIR_MASK_PL = 0x80042C0309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE3_TX_FIR_PL = 0x8004240309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE3_TX_FIR_PL = 0x8004240309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE3_TX_MODE1_PL = 0x8004040309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE3_TX_MODE1_PL = 0x8004040309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE3_TX_MODE2_PL = 0x80040C0309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE3_TX_MODE2_PL = 0x80040C0309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE3_TX_STAT1_PL = 0x80041C0309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE3_TX_STAT1_PL = 0x80041C0309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE0_TX_CNTL1G_PL = 0x8004140409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE0_TX_CNTL1G_PL = 0x8004140409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE0_TX_CNTL2_O_PL = 0x80044C0409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE0_TX_CNTL2_O_PL = 0x80044C0409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE0_TX_CNTL3_EO_PL = 0x8004540409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE0_TX_CNTL3_EO_PL = 0x8004540409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE0_TX_FIR_ERROR_INJECT_PL = 0x8004340409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE0_TX_FIR_ERROR_INJECT_PL = 0x8004340409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE0_TX_FIR_MASK_PL = 0x80042C0409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE0_TX_FIR_MASK_PL = 0x80042C0409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE0_TX_FIR_PL = 0x8004240409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE0_TX_FIR_PL = 0x8004240409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE0_TX_MODE1_PL = 0x8004040409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE0_TX_MODE1_PL = 0x8004040409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE0_TX_MODE2_PL = 0x80040C0409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE0_TX_MODE2_PL = 0x80040C0409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE0_TX_STAT1_PL = 0x80041C0409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE0_TX_STAT1_PL = 0x80041C0409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE1_TX_CNTL1G_PL = 0x8004140509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE1_TX_CNTL1G_PL = 0x8004140509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE1_TX_CNTL2_O_PL = 0x80044C0509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE1_TX_CNTL2_O_PL = 0x80044C0509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE1_TX_CNTL3_EO_PL = 0x8004540509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE1_TX_CNTL3_EO_PL = 0x8004540509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE1_TX_FIR_ERROR_INJECT_PL = 0x8004340509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE1_TX_FIR_ERROR_INJECT_PL = 0x8004340509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE1_TX_FIR_MASK_PL = 0x80042C0509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE1_TX_FIR_MASK_PL = 0x80042C0509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE1_TX_FIR_PL = 0x8004240509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE1_TX_FIR_PL = 0x8004240509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE1_TX_MODE1_PL = 0x8004040509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE1_TX_MODE1_PL = 0x8004040509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE1_TX_MODE2_PL = 0x80040C0509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE1_TX_MODE2_PL = 0x80040C0509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE1_TX_STAT1_PL = 0x80041C0509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE1_TX_STAT1_PL = 0x80041C0509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE2_TX_CNTL1G_PL = 0x8004140609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE2_TX_CNTL1G_PL = 0x8004140609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE2_TX_CNTL2_O_PL = 0x80044C0609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE2_TX_CNTL2_O_PL = 0x80044C0609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE2_TX_CNTL3_EO_PL = 0x8004540609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE2_TX_CNTL3_EO_PL = 0x8004540609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE2_TX_FIR_ERROR_INJECT_PL = 0x8004340609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE2_TX_FIR_ERROR_INJECT_PL = 0x8004340609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE2_TX_FIR_MASK_PL = 0x80042C0609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE2_TX_FIR_MASK_PL = 0x80042C0609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE2_TX_FIR_PL = 0x8004240609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE2_TX_FIR_PL = 0x8004240609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE2_TX_MODE1_PL = 0x8004040609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE2_TX_MODE1_PL = 0x8004040609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE2_TX_MODE2_PL = 0x80040C0609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE2_TX_MODE2_PL = 0x80040C0609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE2_TX_STAT1_PL = 0x80041C0609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE2_TX_STAT1_PL = 0x80041C0609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE3_TX_CNTL1G_PL = 0x8004140709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE3_TX_CNTL1G_PL = 0x8004140709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE3_TX_CNTL2_O_PL = 0x80044C0709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE3_TX_CNTL2_O_PL = 0x80044C0709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE3_TX_CNTL3_EO_PL = 0x8004540709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE3_TX_CNTL3_EO_PL = 0x8004540709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE3_TX_FIR_ERROR_INJECT_PL = 0x8004340709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE3_TX_FIR_ERROR_INJECT_PL = 0x8004340709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE3_TX_FIR_MASK_PL = 0x80042C0709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE3_TX_FIR_MASK_PL = 0x80042C0709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE3_TX_FIR_PL = 0x8004240709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE3_TX_FIR_PL = 0x8004240709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE3_TX_MODE1_PL = 0x8004040709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE3_TX_MODE1_PL = 0x8004040709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE3_TX_MODE2_PL = 0x80040C0709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE3_TX_MODE2_PL = 0x80040C0709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE3_TX_STAT1_PL = 0x80041C0709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE3_TX_STAT1_PL = 0x80041C0709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE0_TX_CNTL1G_PL = 0x8004140809010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE0_TX_CNTL1G_PL = 0x8004140809010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE0_TX_CNTL2_O_PL = 0x80044C0809010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE0_TX_CNTL2_O_PL = 0x80044C0809010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE0_TX_CNTL3_EO_PL = 0x8004540809010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE0_TX_CNTL3_EO_PL = 0x8004540809010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE0_TX_FIR_ERROR_INJECT_PL = 0x8004340809010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE0_TX_FIR_ERROR_INJECT_PL = 0x8004340809010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE0_TX_FIR_MASK_PL = 0x80042C0809010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE0_TX_FIR_MASK_PL = 0x80042C0809010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE0_TX_FIR_PL = 0x8004240809010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE0_TX_FIR_PL = 0x8004240809010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE0_TX_MODE1_PL = 0x8004040809010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE0_TX_MODE1_PL = 0x8004040809010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE0_TX_MODE2_PL = 0x80040C0809010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE0_TX_MODE2_PL = 0x80040C0809010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE0_TX_STAT1_PL = 0x80041C0809010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE0_TX_STAT1_PL = 0x80041C0809010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE1_TX_CNTL1G_PL = 0x8004140909010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE1_TX_CNTL1G_PL = 0x8004140909010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE1_TX_CNTL2_O_PL = 0x80044C0909010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE1_TX_CNTL2_O_PL = 0x80044C0909010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE1_TX_CNTL3_EO_PL = 0x8004540909010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE1_TX_CNTL3_EO_PL = 0x8004540909010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE1_TX_FIR_ERROR_INJECT_PL = 0x8004340909010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE1_TX_FIR_ERROR_INJECT_PL = 0x8004340909010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE1_TX_FIR_MASK_PL = 0x80042C0909010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE1_TX_FIR_MASK_PL = 0x80042C0909010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE1_TX_FIR_PL = 0x8004240909010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE1_TX_FIR_PL = 0x8004240909010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE1_TX_MODE1_PL = 0x8004040909010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE1_TX_MODE1_PL = 0x8004040909010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE1_TX_MODE2_PL = 0x80040C0909010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE1_TX_MODE2_PL = 0x80040C0909010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE1_TX_STAT1_PL = 0x80041C0909010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE1_TX_STAT1_PL = 0x80041C0909010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE2_TX_CNTL1G_PL = 0x8004140A09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE2_TX_CNTL1G_PL = 0x8004140A09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE2_TX_CNTL2_O_PL = 0x80044C0A09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE2_TX_CNTL2_O_PL = 0x80044C0A09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE2_TX_CNTL3_EO_PL = 0x8004540A09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE2_TX_CNTL3_EO_PL = 0x8004540A09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE2_TX_FIR_ERROR_INJECT_PL = 0x8004340A09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE2_TX_FIR_ERROR_INJECT_PL = 0x8004340A09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE2_TX_FIR_MASK_PL = 0x80042C0A09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE2_TX_FIR_MASK_PL = 0x80042C0A09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE2_TX_FIR_PL = 0x8004240A09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE2_TX_FIR_PL = 0x8004240A09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE2_TX_MODE1_PL = 0x8004040A09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE2_TX_MODE1_PL = 0x8004040A09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE2_TX_MODE2_PL = 0x80040C0A09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE2_TX_MODE2_PL = 0x80040C0A09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE2_TX_STAT1_PL = 0x80041C0A09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE2_TX_STAT1_PL = 0x80041C0A09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE3_TX_CNTL1G_PL = 0x8004140B09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE3_TX_CNTL1G_PL = 0x8004140B09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE3_TX_CNTL2_O_PL = 0x80044C0B09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE3_TX_CNTL2_O_PL = 0x80044C0B09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE3_TX_CNTL3_EO_PL = 0x8004540B09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE3_TX_CNTL3_EO_PL = 0x8004540B09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE3_TX_FIR_ERROR_INJECT_PL = 0x8004340B09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE3_TX_FIR_ERROR_INJECT_PL = 0x8004340B09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE3_TX_FIR_MASK_PL = 0x80042C0B09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE3_TX_FIR_MASK_PL = 0x80042C0B09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE3_TX_FIR_PL = 0x8004240B09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE3_TX_FIR_PL = 0x8004240B09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE3_TX_MODE1_PL = 0x8004040B09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE3_TX_MODE1_PL = 0x8004040B09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE3_TX_MODE2_PL = 0x80040C0B09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE3_TX_MODE2_PL = 0x80040C0B09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE3_TX_STAT1_PL = 0x80041C0B09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE3_TX_STAT1_PL = 0x80041C0B09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE0_TX_CNTL1G_PL = 0x8004140C09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE0_TX_CNTL1G_PL = 0x8004140C09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE0_TX_CNTL2_O_PL = 0x80044C0C09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE0_TX_CNTL2_O_PL = 0x80044C0C09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE0_TX_CNTL3_EO_PL = 0x8004540C09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE0_TX_CNTL3_EO_PL = 0x8004540C09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE0_TX_FIR_ERROR_INJECT_PL = 0x8004340C09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE0_TX_FIR_ERROR_INJECT_PL = 0x8004340C09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE0_TX_FIR_MASK_PL = 0x80042C0C09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE0_TX_FIR_MASK_PL = 0x80042C0C09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE0_TX_FIR_PL = 0x8004240C09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE0_TX_FIR_PL = 0x8004240C09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE0_TX_MODE1_PL = 0x8004040C09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE0_TX_MODE1_PL = 0x8004040C09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE0_TX_MODE2_PL = 0x80040C0C09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE0_TX_MODE2_PL = 0x80040C0C09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE0_TX_STAT1_PL = 0x80041C0C09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE0_TX_STAT1_PL = 0x80041C0C09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE1_TX_CNTL1G_PL = 0x8004140D09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE1_TX_CNTL1G_PL = 0x8004140D09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE1_TX_CNTL2_O_PL = 0x80044C0D09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE1_TX_CNTL2_O_PL = 0x80044C0D09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE1_TX_CNTL3_EO_PL = 0x8004540D09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE1_TX_CNTL3_EO_PL = 0x8004540D09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE1_TX_FIR_ERROR_INJECT_PL = 0x8004340D09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE1_TX_FIR_ERROR_INJECT_PL = 0x8004340D09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE1_TX_FIR_MASK_PL = 0x80042C0D09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE1_TX_FIR_MASK_PL = 0x80042C0D09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE1_TX_FIR_PL = 0x8004240D09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE1_TX_FIR_PL = 0x8004240D09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE1_TX_MODE1_PL = 0x8004040D09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE1_TX_MODE1_PL = 0x8004040D09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE1_TX_MODE2_PL = 0x80040C0D09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE1_TX_MODE2_PL = 0x80040C0D09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE1_TX_STAT1_PL = 0x80041C0D09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE1_TX_STAT1_PL = 0x80041C0D09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE2_TX_CNTL1G_PL = 0x8004140E09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE2_TX_CNTL1G_PL = 0x8004140E09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE2_TX_CNTL2_O_PL = 0x80044C0E09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE2_TX_CNTL2_O_PL = 0x80044C0E09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE2_TX_CNTL3_EO_PL = 0x8004540E09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE2_TX_CNTL3_EO_PL = 0x8004540E09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE2_TX_FIR_ERROR_INJECT_PL = 0x8004340E09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE2_TX_FIR_ERROR_INJECT_PL = 0x8004340E09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE2_TX_FIR_MASK_PL = 0x80042C0E09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE2_TX_FIR_MASK_PL = 0x80042C0E09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE2_TX_FIR_PL = 0x8004240E09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE2_TX_FIR_PL = 0x8004240E09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE2_TX_MODE1_PL = 0x8004040E09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE2_TX_MODE1_PL = 0x8004040E09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE2_TX_MODE2_PL = 0x80040C0E09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE2_TX_MODE2_PL = 0x80040C0E09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE2_TX_STAT1_PL = 0x80041C0E09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE2_TX_STAT1_PL = 0x80041C0E09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE3_TX_CNTL1G_PL = 0x8004140F09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE3_TX_CNTL1G_PL = 0x8004140F09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE3_TX_CNTL2_O_PL = 0x80044C0F09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE3_TX_CNTL2_O_PL = 0x80044C0F09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE3_TX_CNTL3_EO_PL = 0x8004540F09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE3_TX_CNTL3_EO_PL = 0x8004540F09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE3_TX_FIR_ERROR_INJECT_PL = 0x8004340F09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE3_TX_FIR_ERROR_INJECT_PL = 0x8004340F09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE3_TX_FIR_MASK_PL = 0x80042C0F09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE3_TX_FIR_MASK_PL = 0x80042C0F09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE3_TX_FIR_PL = 0x8004240F09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE3_TX_FIR_PL = 0x8004240F09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE3_TX_MODE1_PL = 0x8004040F09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE3_TX_MODE1_PL = 0x8004040F09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE3_TX_MODE2_PL = 0x80040C0F09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE3_TX_MODE2_PL = 0x80040C0F09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE3_TX_STAT1_PL = 0x80041C0F09010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE3_TX_STAT1_PL = 0x80041C0F09010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE0_TX_CNTL1G_PL = 0x8004141009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE0_TX_CNTL1G_PL = 0x8004141009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE0_TX_CNTL2_O_PL = 0x80044C1009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE0_TX_CNTL2_O_PL = 0x80044C1009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE0_TX_CNTL3_EO_PL = 0x8004541009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE0_TX_CNTL3_EO_PL = 0x8004541009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE0_TX_FIR_ERROR_INJECT_PL = 0x8004341009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE0_TX_FIR_ERROR_INJECT_PL = 0x8004341009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE0_TX_FIR_MASK_PL = 0x80042C1009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE0_TX_FIR_MASK_PL = 0x80042C1009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE0_TX_FIR_PL = 0x8004241009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE0_TX_FIR_PL = 0x8004241009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE0_TX_MODE1_PL = 0x8004041009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE0_TX_MODE1_PL = 0x8004041009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE0_TX_MODE2_PL = 0x80040C1009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE0_TX_MODE2_PL = 0x80040C1009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE0_TX_STAT1_PL = 0x80041C1009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE0_TX_STAT1_PL = 0x80041C1009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE1_TX_CNTL1G_PL = 0x8004141109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE1_TX_CNTL1G_PL = 0x8004141109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE1_TX_CNTL2_O_PL = 0x80044C1109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE1_TX_CNTL2_O_PL = 0x80044C1109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE1_TX_CNTL3_EO_PL = 0x8004541109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE1_TX_CNTL3_EO_PL = 0x8004541109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE1_TX_FIR_ERROR_INJECT_PL = 0x8004341109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE1_TX_FIR_ERROR_INJECT_PL = 0x8004341109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE1_TX_FIR_MASK_PL = 0x80042C1109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE1_TX_FIR_MASK_PL = 0x80042C1109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE1_TX_FIR_PL = 0x8004241109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE1_TX_FIR_PL = 0x8004241109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE1_TX_MODE1_PL = 0x8004041109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE1_TX_MODE1_PL = 0x8004041109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE1_TX_MODE2_PL = 0x80040C1109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE1_TX_MODE2_PL = 0x80040C1109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE1_TX_STAT1_PL = 0x80041C1109010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE1_TX_STAT1_PL = 0x80041C1109010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE2_TX_CNTL1G_PL = 0x8004141209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE2_TX_CNTL1G_PL = 0x8004141209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE2_TX_CNTL2_O_PL = 0x80044C1209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE2_TX_CNTL2_O_PL = 0x80044C1209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE2_TX_CNTL3_EO_PL = 0x8004541209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE2_TX_CNTL3_EO_PL = 0x8004541209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE2_TX_FIR_ERROR_INJECT_PL = 0x8004341209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE2_TX_FIR_ERROR_INJECT_PL = 0x8004341209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE2_TX_FIR_MASK_PL = 0x80042C1209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE2_TX_FIR_MASK_PL = 0x80042C1209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE2_TX_FIR_PL = 0x8004241209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE2_TX_FIR_PL = 0x8004241209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE2_TX_MODE1_PL = 0x8004041209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE2_TX_MODE1_PL = 0x8004041209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE2_TX_MODE2_PL = 0x80040C1209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE2_TX_MODE2_PL = 0x80040C1209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE2_TX_STAT1_PL = 0x80041C1209010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE2_TX_STAT1_PL = 0x80041C1209010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE3_TX_CNTL1G_PL = 0x8004141309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE3_TX_CNTL1G_PL = 0x8004141309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE3_TX_CNTL2_O_PL = 0x80044C1309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE3_TX_CNTL2_O_PL = 0x80044C1309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE3_TX_CNTL3_EO_PL = 0x8004541309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE3_TX_CNTL3_EO_PL = 0x8004541309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE3_TX_FIR_ERROR_INJECT_PL = 0x8004341309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE3_TX_FIR_ERROR_INJECT_PL = 0x8004341309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE3_TX_FIR_MASK_PL = 0x80042C1309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE3_TX_FIR_MASK_PL = 0x80042C1309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE3_TX_FIR_PL = 0x8004241309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE3_TX_FIR_PL = 0x8004241309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE3_TX_MODE1_PL = 0x8004041309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE3_TX_MODE1_PL = 0x8004041309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE3_TX_MODE2_PL = 0x80040C1309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE3_TX_MODE2_PL = 0x80040C1309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE3_TX_STAT1_PL = 0x80041C1309010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE3_TX_STAT1_PL = 0x80041C1309010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE0_TX_CNTL1G_PL = 0x8004141409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE0_TX_CNTL1G_PL = 0x8004141409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE0_TX_CNTL2_O_PL = 0x80044C1409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE0_TX_CNTL2_O_PL = 0x80044C1409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE0_TX_CNTL3_EO_PL = 0x8004541409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE0_TX_CNTL3_EO_PL = 0x8004541409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE0_TX_FIR_ERROR_INJECT_PL = 0x8004341409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE0_TX_FIR_ERROR_INJECT_PL = 0x8004341409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE0_TX_FIR_MASK_PL = 0x80042C1409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE0_TX_FIR_MASK_PL = 0x80042C1409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE0_TX_FIR_PL = 0x8004241409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE0_TX_FIR_PL = 0x8004241409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE0_TX_MODE1_PL = 0x8004041409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE0_TX_MODE1_PL = 0x8004041409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE0_TX_MODE2_PL = 0x80040C1409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE0_TX_MODE2_PL = 0x80040C1409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE0_TX_STAT1_PL = 0x80041C1409010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE0_TX_STAT1_PL = 0x80041C1409010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE1_TX_CNTL1G_PL = 0x8004141509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE1_TX_CNTL1G_PL = 0x8004141509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE1_TX_CNTL2_O_PL = 0x80044C1509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE1_TX_CNTL2_O_PL = 0x80044C1509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE1_TX_CNTL3_EO_PL = 0x8004541509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE1_TX_CNTL3_EO_PL = 0x8004541509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE1_TX_FIR_ERROR_INJECT_PL = 0x8004341509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE1_TX_FIR_ERROR_INJECT_PL = 0x8004341509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE1_TX_FIR_MASK_PL = 0x80042C1509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE1_TX_FIR_MASK_PL = 0x80042C1509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE1_TX_FIR_PL = 0x8004241509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE1_TX_FIR_PL = 0x8004241509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE1_TX_MODE1_PL = 0x8004041509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE1_TX_MODE1_PL = 0x8004041509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE1_TX_MODE2_PL = 0x80040C1509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE1_TX_MODE2_PL = 0x80040C1509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE1_TX_STAT1_PL = 0x80041C1509010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE1_TX_STAT1_PL = 0x80041C1509010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE2_TX_CNTL1G_PL = 0x8004141609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE2_TX_CNTL1G_PL = 0x8004141609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE2_TX_CNTL2_O_PL = 0x80044C1609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE2_TX_CNTL2_O_PL = 0x80044C1609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE2_TX_CNTL3_EO_PL = 0x8004541609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE2_TX_CNTL3_EO_PL = 0x8004541609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE2_TX_FIR_ERROR_INJECT_PL = 0x8004341609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE2_TX_FIR_ERROR_INJECT_PL = 0x8004341609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE2_TX_FIR_MASK_PL = 0x80042C1609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE2_TX_FIR_MASK_PL = 0x80042C1609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE2_TX_FIR_PL = 0x8004241609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE2_TX_FIR_PL = 0x8004241609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE2_TX_MODE1_PL = 0x8004041609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE2_TX_MODE1_PL = 0x8004041609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE2_TX_MODE2_PL = 0x80040C1609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE2_TX_MODE2_PL = 0x80040C1609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE2_TX_STAT1_PL = 0x80041C1609010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE2_TX_STAT1_PL = 0x80041C1609010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE3_TX_CNTL1G_PL = 0x8004141709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE3_TX_CNTL1G_PL = 0x8004141709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE3_TX_CNTL2_O_PL = 0x80044C1709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE3_TX_CNTL2_O_PL = 0x80044C1709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE3_TX_CNTL3_EO_PL = 0x8004541709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE3_TX_CNTL3_EO_PL = 0x8004541709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE3_TX_FIR_ERROR_INJECT_PL = 0x8004341709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE3_TX_FIR_ERROR_INJECT_PL = 0x8004341709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE3_TX_FIR_MASK_PL = 0x80042C1709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE3_TX_FIR_MASK_PL = 0x80042C1709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE3_TX_FIR_PL = 0x8004241709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE3_TX_FIR_PL = 0x8004241709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE3_TX_MODE1_PL = 0x8004041709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE3_TX_MODE1_PL = 0x8004041709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE3_TX_MODE2_PL = 0x80040C1709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE3_TX_MODE2_PL = 0x80040C1709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE3_TX_STAT1_PL = 0x80041C1709010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE3_TX_STAT1_PL = 0x80041C1709010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTLSM_CNTL1_EO_PG = 0x800D340009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TX_CTLSM_CNTL1_EO_PG = 0x800D340009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTLSM_CNTL1_O_PG = 0x800D840009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TX_CTLSM_CNTL1_O_PG = 0x800D840009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTLSM_CNTL2_EO_PG = 0x800D3C0009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TX_CTLSM_CNTL2_EO_PG = 0x800D3C0009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTLSM_CNTL2_O_PG = 0x800D8C0009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TX_CTLSM_CNTL2_O_PG = 0x800D8C0009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTLSM_CNTL3_EO_PG = 0x800D440009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TX_CTLSM_CNTL3_EO_PG = 0x800D440009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTLSM_CNTL4_EO_PG = 0x800D4C0009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TX_CTLSM_CNTL4_EO_PG = 0x800D4C0009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTLSM_CNTL5_EO_PG = 0x800D540009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TX_CTLSM_CNTL5_EO_PG = 0x800D540009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTLSM_CNTL6_EO_PG = 0x800D5C0009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TX_CTLSM_CNTL6_EO_PG = 0x800D5C0009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTLSM_CNTL7_EO_PG = 0x800D640009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TX_CTLSM_CNTL7_EO_PG = 0x800D640009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTLSM_MODE1_EO_PG = 0x800D2C0009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TX_CTLSM_MODE1_EO_PG = 0x800D2C0009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTLSM_SPARE_MODE_PG = 0x800D240009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TX_CTLSM_SPARE_MODE_PG = 0x800D240009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTLSM_STAT1_EO_PG = 0x800D6C0009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TX_CTLSM_STAT1_EO_PG = 0x800D6C0009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTL_CNTL10_EO_PG = 0x800CDC0009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TX_CTL_CNTL10_EO_PG = 0x800CDC0009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTL_CNTL2_EO_PG = 0x800C2C0009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TX_CTL_CNTL2_EO_PG = 0x800C2C0009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTL_CNTL3_EO_PG = 0x800C340009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TX_CTL_CNTL3_EO_PG = 0x800C340009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTL_CNTL8_EO_PG = 0x800CCC0009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TX_CTL_CNTL8_EO_PG = 0x800CCC0009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTL_CNTL9_EO_PG = 0x800CD40009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TX_CTL_CNTL9_EO_PG = 0x800CD40009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTL_CNTLG1_EO_PG = 0x800C240009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TX_CTL_CNTLG1_EO_PG = 0x800C240009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTL_MODE1_EO_PG = 0x800C140009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TX_CTL_MODE1_EO_PG = 0x800C140009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_FIR_ERROR_INJECT_PG = 0x800D1C0009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TX_FIR_ERROR_INJECT_PG = 0x800D1C0009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_FIR_MASK_PG = 0x800D0C0009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TX_FIR_MASK_PG = 0x800D0C0009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_FIR_PG = 0x800D040009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TX_FIR_PG = 0x800D040009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_FIR_RESET_PG = 0x800D140009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TX_FIR_RESET_PG = 0x800D140009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_ID1_PG = 0x800C0C0009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TX_ID1_PG = 0x800C0C0009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_SPARE_MODE_PG = 0x800C040009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX0_TX_SPARE_MODE_PG = 0x800C040009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX_IMPCAL2_PB = 0x800F3C0009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX_IMPCAL2_PB = 0x800F3C0009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX_IMPCAL_NVAL_PB = 0x800F0C0009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX_IMPCAL_NVAL_PB = 0x800F0C0009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX_IMPCAL_PB = 0x800F040009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX_IMPCAL_PB = 0x800F040009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX_IMPCAL_PVAL_PB = 0x800F140009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX_IMPCAL_PVAL_PB = 0x800F140009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX_IMPCAL_P_4X_PB = 0x800F1C0009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX_IMPCAL_P_4X_PB = 0x800F1C0009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX_IMPCAL_SWO1_PB = 0x800F240009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX_IMPCAL_SWO1_PB = 0x800F240009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX_IMPCAL_SWO2_PB = 0x800F2C0009010C3Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_IOO0_TX_IMPCAL_SWO2_PB = 0x800F2C0009010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_C0_S0_P0_E9_IOO3_C0_S0_P0_E9_IOO3_FIR_MASK_REG = 0x0C010C03ull;
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_C0_S0_P0_E9_IOO3_C0_S0_P0_E9_IOO3_FIR_MASK_REG_AND = 0x0C010C04ull;
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_C0_S0_P0_E9_IOO3_C0_S0_P0_E9_IOO3_FIR_MASK_REG_OR = 0x0C010C05ull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_C0_S0_P0_E9_IOO3_C0_S0_P0_E9_IOO3_FIR_REG = 0x0C010C00ull;
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_C0_S0_P0_E9_IOO3_C0_S0_P0_E9_IOO3_FIR_REG_AND = 0x0C010C01ull;
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_C0_S0_P0_E9_IOO3_C0_S0_P0_E9_IOO3_FIR_REG_OR = 0x0C010C02ull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_FIR_ACTION0_REG = 0x0C010C06ull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_FIR_ACTION1_REG = 0x0C010C07ull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_FIR_WOF_REG = 0x0C010C08ull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL = 0x800248000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL = 0x800250000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL = 0x800258000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL5_EO_PL = 0x800260000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL = 0x800240000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL = 0x800220000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE0_RX_BIT_MODE2_EO_PL = 0x800228000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL = 0x800230000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE0_RX_BIT_MODE4_EO_PL = 0x800238000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE0_RX_BIT_STAT1_EO_PL = 0x800268000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE0_RX_BIT_STAT1_O_PL = 0x800318000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL = 0x800270000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL = 0x800278000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE0_RX_BIT_STAT4_EO_PL = 0x800280000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL10_O_PL = 0x8000C8000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL = 0x800008000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_O_PL = 0x800080000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL = 0x800010000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_O_PL = 0x800088000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_EO_PL = 0x800018000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_O_PL = 0x800090000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_EO_PL = 0x800020000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_O_PL = 0x800098000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL = 0x800028000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_O_PL = 0x8000A0000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_EO_PL = 0x800030000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_O_PL = 0x8000A8000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL7_EO_PL = 0x800038000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL7_O_PL = 0x8000B0000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL8_EO_PL = 0x800040000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL8_O_PL = 0x8000B8000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL9_O_PL = 0x8000C0000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x800000000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE0_RX_FIR_ERROR_INJECT_PL = 0x800218000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE0_RX_FIR_MASK_PL = 0x800210000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE0_RX_FIR_PL = 0x800208000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE0_RX_SPARE_MODE_PL = 0x800200000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL = 0x800248010C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL = 0x800250010C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL = 0x800258010C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL5_EO_PL = 0x800260010C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL = 0x800240010C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL = 0x800220010C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE1_RX_BIT_MODE2_EO_PL = 0x800228010C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL = 0x800230010C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE1_RX_BIT_MODE4_EO_PL = 0x800238010C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE1_RX_BIT_STAT1_EO_PL = 0x800268010C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE1_RX_BIT_STAT1_O_PL = 0x800318010C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL = 0x800270010C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL = 0x800278010C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE1_RX_BIT_STAT4_EO_PL = 0x800280010C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL10_O_PL = 0x8000C8010C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL = 0x800008010C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_O_PL = 0x800080010C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL = 0x800010010C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_O_PL = 0x800088010C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_EO_PL = 0x800018010C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_O_PL = 0x800090010C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_EO_PL = 0x800020010C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_O_PL = 0x800098010C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL = 0x800028010C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_O_PL = 0x8000A0010C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_EO_PL = 0x800030010C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_O_PL = 0x8000A8010C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL7_EO_PL = 0x800038010C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL7_O_PL = 0x8000B0010C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL8_EO_PL = 0x800040010C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL8_O_PL = 0x8000B8010C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL9_O_PL = 0x8000C0010C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x800000010C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE1_RX_FIR_ERROR_INJECT_PL = 0x800218010C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE1_RX_FIR_MASK_PL = 0x800210010C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE1_RX_FIR_PL = 0x800208010C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE1_RX_SPARE_MODE_PL = 0x800200010C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL = 0x800248020C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL = 0x800250020C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL = 0x800258020C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL5_EO_PL = 0x800260020C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL = 0x800240020C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL = 0x800220020C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE2_RX_BIT_MODE2_EO_PL = 0x800228020C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL = 0x800230020C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE2_RX_BIT_MODE4_EO_PL = 0x800238020C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE2_RX_BIT_STAT1_EO_PL = 0x800268020C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE2_RX_BIT_STAT1_O_PL = 0x800318020C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL = 0x800270020C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL = 0x800278020C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE2_RX_BIT_STAT4_EO_PL = 0x800280020C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL10_O_PL = 0x8000C8020C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL = 0x800008020C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_O_PL = 0x800080020C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL = 0x800010020C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_O_PL = 0x800088020C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_EO_PL = 0x800018020C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_O_PL = 0x800090020C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_EO_PL = 0x800020020C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_O_PL = 0x800098020C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL = 0x800028020C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_O_PL = 0x8000A0020C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_EO_PL = 0x800030020C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_O_PL = 0x8000A8020C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL7_EO_PL = 0x800038020C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL7_O_PL = 0x8000B0020C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL8_EO_PL = 0x800040020C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL8_O_PL = 0x8000B8020C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL9_O_PL = 0x8000C0020C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x800000020C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE2_RX_FIR_ERROR_INJECT_PL = 0x800218020C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE2_RX_FIR_MASK_PL = 0x800210020C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE2_RX_FIR_PL = 0x800208020C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE2_RX_SPARE_MODE_PL = 0x800200020C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL = 0x800248030C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL = 0x800250030C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL = 0x800258030C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL5_EO_PL = 0x800260030C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL = 0x800240030C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL = 0x800220030C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE3_RX_BIT_MODE2_EO_PL = 0x800228030C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL = 0x800230030C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE3_RX_BIT_MODE4_EO_PL = 0x800238030C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE3_RX_BIT_STAT1_EO_PL = 0x800268030C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE3_RX_BIT_STAT1_O_PL = 0x800318030C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL = 0x800270030C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL = 0x800278030C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE3_RX_BIT_STAT4_EO_PL = 0x800280030C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL10_O_PL = 0x8000C8030C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL = 0x800008030C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_O_PL = 0x800080030C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL = 0x800010030C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_O_PL = 0x800088030C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL3_EO_PL = 0x800018030C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL3_O_PL = 0x800090030C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_EO_PL = 0x800020030C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_O_PL = 0x800098030C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL = 0x800028030C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_O_PL = 0x8000A0030C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL6_EO_PL = 0x800030030C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL6_O_PL = 0x8000A8030C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL7_EO_PL = 0x800038030C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL7_O_PL = 0x8000B0030C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL8_EO_PL = 0x800040030C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL8_O_PL = 0x8000B8030C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL9_O_PL = 0x8000C0030C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x800000030C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE3_RX_FIR_ERROR_INJECT_PL = 0x800218030C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE3_RX_FIR_MASK_PL = 0x800210030C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE3_RX_FIR_PL = 0x800208030C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS0_SLICE3_RX_SPARE_MODE_PL = 0x800200030C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL = 0x800248040C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL = 0x800250040C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL = 0x800258040C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL5_EO_PL = 0x800260040C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL = 0x800240040C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL = 0x800220040C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE0_RX_BIT_MODE2_EO_PL = 0x800228040C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL = 0x800230040C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE0_RX_BIT_MODE4_EO_PL = 0x800238040C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE0_RX_BIT_STAT1_EO_PL = 0x800268040C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE0_RX_BIT_STAT1_O_PL = 0x800318040C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL = 0x800270040C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL = 0x800278040C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE0_RX_BIT_STAT4_EO_PL = 0x800280040C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL10_O_PL = 0x8000C8040C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL = 0x800008040C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_O_PL = 0x800080040C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_EO_PL = 0x800010040C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_O_PL = 0x800088040C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL3_EO_PL = 0x800018040C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL3_O_PL = 0x800090040C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_EO_PL = 0x800020040C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_O_PL = 0x800098040C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL = 0x800028040C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_O_PL = 0x8000A0040C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL6_EO_PL = 0x800030040C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL6_O_PL = 0x8000A8040C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL7_EO_PL = 0x800038040C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL7_O_PL = 0x8000B0040C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL8_EO_PL = 0x800040040C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL8_O_PL = 0x8000B8040C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL9_O_PL = 0x8000C0040C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x800000040C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE0_RX_FIR_ERROR_INJECT_PL = 0x800218040C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE0_RX_FIR_MASK_PL = 0x800210040C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE0_RX_FIR_PL = 0x800208040C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE0_RX_SPARE_MODE_PL = 0x800200040C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL = 0x800248050C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL = 0x800250050C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL = 0x800258050C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL5_EO_PL = 0x800260050C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL = 0x800240050C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL = 0x800220050C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE1_RX_BIT_MODE2_EO_PL = 0x800228050C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL = 0x800230050C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE1_RX_BIT_MODE4_EO_PL = 0x800238050C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE1_RX_BIT_STAT1_EO_PL = 0x800268050C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE1_RX_BIT_STAT1_O_PL = 0x800318050C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL = 0x800270050C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL = 0x800278050C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE1_RX_BIT_STAT4_EO_PL = 0x800280050C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL10_O_PL = 0x8000C8050C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL = 0x800008050C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_O_PL = 0x800080050C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_EO_PL = 0x800010050C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_O_PL = 0x800088050C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL3_EO_PL = 0x800018050C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL3_O_PL = 0x800090050C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_EO_PL = 0x800020050C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_O_PL = 0x800098050C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL = 0x800028050C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_O_PL = 0x8000A0050C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL6_EO_PL = 0x800030050C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL6_O_PL = 0x8000A8050C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL7_EO_PL = 0x800038050C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL7_O_PL = 0x8000B0050C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL8_EO_PL = 0x800040050C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL8_O_PL = 0x8000B8050C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL9_O_PL = 0x8000C0050C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x800000050C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE1_RX_FIR_ERROR_INJECT_PL = 0x800218050C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE1_RX_FIR_MASK_PL = 0x800210050C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE1_RX_FIR_PL = 0x800208050C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE1_RX_SPARE_MODE_PL = 0x800200050C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL = 0x800248060C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL = 0x800250060C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL = 0x800258060C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL5_EO_PL = 0x800260060C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL = 0x800240060C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL = 0x800220060C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE2_RX_BIT_MODE2_EO_PL = 0x800228060C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL = 0x800230060C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE2_RX_BIT_MODE4_EO_PL = 0x800238060C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE2_RX_BIT_STAT1_EO_PL = 0x800268060C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE2_RX_BIT_STAT1_O_PL = 0x800318060C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL = 0x800270060C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL = 0x800278060C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE2_RX_BIT_STAT4_EO_PL = 0x800280060C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL10_O_PL = 0x8000C8060C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL = 0x800008060C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_O_PL = 0x800080060C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_EO_PL = 0x800010060C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_O_PL = 0x800088060C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL3_EO_PL = 0x800018060C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL3_O_PL = 0x800090060C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_EO_PL = 0x800020060C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_O_PL = 0x800098060C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL = 0x800028060C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_O_PL = 0x8000A0060C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL6_EO_PL = 0x800030060C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL6_O_PL = 0x8000A8060C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL7_EO_PL = 0x800038060C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL7_O_PL = 0x8000B0060C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL8_EO_PL = 0x800040060C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL8_O_PL = 0x8000B8060C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL9_O_PL = 0x8000C0060C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x800000060C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE2_RX_FIR_ERROR_INJECT_PL = 0x800218060C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE2_RX_FIR_MASK_PL = 0x800210060C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE2_RX_FIR_PL = 0x800208060C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE2_RX_SPARE_MODE_PL = 0x800200060C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL = 0x800248070C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL = 0x800250070C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL = 0x800258070C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL5_EO_PL = 0x800260070C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL = 0x800240070C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL = 0x800220070C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE3_RX_BIT_MODE2_EO_PL = 0x800228070C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL = 0x800230070C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE3_RX_BIT_MODE4_EO_PL = 0x800238070C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE3_RX_BIT_STAT1_EO_PL = 0x800268070C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE3_RX_BIT_STAT1_O_PL = 0x800318070C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL = 0x800270070C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL = 0x800278070C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE3_RX_BIT_STAT4_EO_PL = 0x800280070C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL10_O_PL = 0x8000C8070C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL = 0x800008070C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_O_PL = 0x800080070C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_EO_PL = 0x800010070C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_O_PL = 0x800088070C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL3_EO_PL = 0x800018070C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL3_O_PL = 0x800090070C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_EO_PL = 0x800020070C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_O_PL = 0x800098070C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL = 0x800028070C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_O_PL = 0x8000A0070C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL6_EO_PL = 0x800030070C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL6_O_PL = 0x8000A8070C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL7_EO_PL = 0x800038070C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL7_O_PL = 0x8000B0070C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL8_EO_PL = 0x800040070C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL8_O_PL = 0x8000B8070C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL9_O_PL = 0x8000C0070C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x800000070C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE3_RX_FIR_ERROR_INJECT_PL = 0x800218070C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE3_RX_FIR_MASK_PL = 0x800210070C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE3_RX_FIR_PL = 0x800208070C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS1_SLICE3_RX_SPARE_MODE_PL = 0x800200070C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL = 0x800248080C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL = 0x800250080C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL = 0x800258080C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL5_EO_PL = 0x800260080C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL = 0x800240080C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL = 0x800220080C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE0_RX_BIT_MODE2_EO_PL = 0x800228080C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL = 0x800230080C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE0_RX_BIT_MODE4_EO_PL = 0x800238080C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE0_RX_BIT_STAT1_EO_PL = 0x800268080C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE0_RX_BIT_STAT1_O_PL = 0x800318080C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL = 0x800270080C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL = 0x800278080C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE0_RX_BIT_STAT4_EO_PL = 0x800280080C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL10_O_PL = 0x8000C8080C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL = 0x800008080C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_O_PL = 0x800080080C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_EO_PL = 0x800010080C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_O_PL = 0x800088080C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL3_EO_PL = 0x800018080C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL3_O_PL = 0x800090080C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_EO_PL = 0x800020080C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_O_PL = 0x800098080C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL = 0x800028080C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_O_PL = 0x8000A0080C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL6_EO_PL = 0x800030080C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL6_O_PL = 0x8000A8080C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL7_EO_PL = 0x800038080C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL7_O_PL = 0x8000B0080C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL8_EO_PL = 0x800040080C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL8_O_PL = 0x8000B8080C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL9_O_PL = 0x8000C0080C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x800000080C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE0_RX_FIR_ERROR_INJECT_PL = 0x800218080C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE0_RX_FIR_MASK_PL = 0x800210080C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE0_RX_FIR_PL = 0x800208080C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE0_RX_SPARE_MODE_PL = 0x800200080C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL = 0x800248090C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL = 0x800250090C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL = 0x800258090C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL5_EO_PL = 0x800260090C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL = 0x800240090C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL = 0x800220090C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE1_RX_BIT_MODE2_EO_PL = 0x800228090C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL = 0x800230090C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE1_RX_BIT_MODE4_EO_PL = 0x800238090C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE1_RX_BIT_STAT1_EO_PL = 0x800268090C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE1_RX_BIT_STAT1_O_PL = 0x800318090C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL = 0x800270090C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL = 0x800278090C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE1_RX_BIT_STAT4_EO_PL = 0x800280090C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL10_O_PL = 0x8000C8090C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL = 0x800008090C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_O_PL = 0x800080090C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_EO_PL = 0x800010090C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_O_PL = 0x800088090C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL3_EO_PL = 0x800018090C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL3_O_PL = 0x800090090C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_EO_PL = 0x800020090C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_O_PL = 0x800098090C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL = 0x800028090C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_O_PL = 0x8000A0090C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL6_EO_PL = 0x800030090C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL6_O_PL = 0x8000A8090C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL7_EO_PL = 0x800038090C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL7_O_PL = 0x8000B0090C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL8_EO_PL = 0x800040090C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL8_O_PL = 0x8000B8090C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL9_O_PL = 0x8000C0090C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x800000090C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE1_RX_FIR_ERROR_INJECT_PL = 0x800218090C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE1_RX_FIR_MASK_PL = 0x800210090C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE1_RX_FIR_PL = 0x800208090C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE1_RX_SPARE_MODE_PL = 0x800200090C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL = 0x8002480A0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL = 0x8002500A0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL = 0x8002580A0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL5_EO_PL = 0x8002600A0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL = 0x8002400A0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL = 0x8002200A0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE2_RX_BIT_MODE2_EO_PL = 0x8002280A0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL = 0x8002300A0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE2_RX_BIT_MODE4_EO_PL = 0x8002380A0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE2_RX_BIT_STAT1_EO_PL = 0x8002680A0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE2_RX_BIT_STAT1_O_PL = 0x8003180A0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL = 0x8002700A0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL = 0x8002780A0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE2_RX_BIT_STAT4_EO_PL = 0x8002800A0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL10_O_PL = 0x8000C80A0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL = 0x8000080A0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_O_PL = 0x8000800A0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_EO_PL = 0x8000100A0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_O_PL = 0x8000880A0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL3_EO_PL = 0x8000180A0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL3_O_PL = 0x8000900A0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_EO_PL = 0x8000200A0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_O_PL = 0x8000980A0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL = 0x8000280A0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_O_PL = 0x8000A00A0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL6_EO_PL = 0x8000300A0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL6_O_PL = 0x8000A80A0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL7_EO_PL = 0x8000380A0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL7_O_PL = 0x8000B00A0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL8_EO_PL = 0x8000400A0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL8_O_PL = 0x8000B80A0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL9_O_PL = 0x8000C00A0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x8000000A0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE2_RX_FIR_ERROR_INJECT_PL = 0x8002180A0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE2_RX_FIR_MASK_PL = 0x8002100A0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE2_RX_FIR_PL = 0x8002080A0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE2_RX_SPARE_MODE_PL = 0x8002000A0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL = 0x8002480B0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL = 0x8002500B0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL = 0x8002580B0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL5_EO_PL = 0x8002600B0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL = 0x8002400B0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL = 0x8002200B0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE3_RX_BIT_MODE2_EO_PL = 0x8002280B0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL = 0x8002300B0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE3_RX_BIT_MODE4_EO_PL = 0x8002380B0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE3_RX_BIT_STAT1_EO_PL = 0x8002680B0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE3_RX_BIT_STAT1_O_PL = 0x8003180B0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL = 0x8002700B0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL = 0x8002780B0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE3_RX_BIT_STAT4_EO_PL = 0x8002800B0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL10_O_PL = 0x8000C80B0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL = 0x8000080B0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_O_PL = 0x8000800B0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_EO_PL = 0x8000100B0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_O_PL = 0x8000880B0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL3_EO_PL = 0x8000180B0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL3_O_PL = 0x8000900B0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_EO_PL = 0x8000200B0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_O_PL = 0x8000980B0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL = 0x8000280B0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_O_PL = 0x8000A00B0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL6_EO_PL = 0x8000300B0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL6_O_PL = 0x8000A80B0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL7_EO_PL = 0x8000380B0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL7_O_PL = 0x8000B00B0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL8_EO_PL = 0x8000400B0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL8_O_PL = 0x8000B80B0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL9_O_PL = 0x8000C00B0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x8000000B0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE3_RX_FIR_ERROR_INJECT_PL = 0x8002180B0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE3_RX_FIR_MASK_PL = 0x8002100B0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE3_RX_FIR_PL = 0x8002080B0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS2_SLICE3_RX_SPARE_MODE_PL = 0x8002000B0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL = 0x8002480C0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL = 0x8002500C0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL = 0x8002580C0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL5_EO_PL = 0x8002600C0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL = 0x8002400C0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL = 0x8002200C0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE0_RX_BIT_MODE2_EO_PL = 0x8002280C0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL = 0x8002300C0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE0_RX_BIT_MODE4_EO_PL = 0x8002380C0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE0_RX_BIT_STAT1_EO_PL = 0x8002680C0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE0_RX_BIT_STAT1_O_PL = 0x8003180C0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL = 0x8002700C0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL = 0x8002780C0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE0_RX_BIT_STAT4_EO_PL = 0x8002800C0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL10_O_PL = 0x8000C80C0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL = 0x8000080C0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_O_PL = 0x8000800C0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_EO_PL = 0x8000100C0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_O_PL = 0x8000880C0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL3_EO_PL = 0x8000180C0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL3_O_PL = 0x8000900C0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_EO_PL = 0x8000200C0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_O_PL = 0x8000980C0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL = 0x8000280C0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_O_PL = 0x8000A00C0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL6_EO_PL = 0x8000300C0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL6_O_PL = 0x8000A80C0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL7_EO_PL = 0x8000380C0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL7_O_PL = 0x8000B00C0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL8_EO_PL = 0x8000400C0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL8_O_PL = 0x8000B80C0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL9_O_PL = 0x8000C00C0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x8000000C0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE0_RX_FIR_ERROR_INJECT_PL = 0x8002180C0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE0_RX_FIR_MASK_PL = 0x8002100C0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE0_RX_FIR_PL = 0x8002080C0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE0_RX_SPARE_MODE_PL = 0x8002000C0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL = 0x8002480D0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL = 0x8002500D0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL = 0x8002580D0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL5_EO_PL = 0x8002600D0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL = 0x8002400D0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL = 0x8002200D0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE1_RX_BIT_MODE2_EO_PL = 0x8002280D0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL = 0x8002300D0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE1_RX_BIT_MODE4_EO_PL = 0x8002380D0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE1_RX_BIT_STAT1_EO_PL = 0x8002680D0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE1_RX_BIT_STAT1_O_PL = 0x8003180D0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL = 0x8002700D0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL = 0x8002780D0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE1_RX_BIT_STAT4_EO_PL = 0x8002800D0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL10_O_PL = 0x8000C80D0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL = 0x8000080D0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_O_PL = 0x8000800D0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_EO_PL = 0x8000100D0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_O_PL = 0x8000880D0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL3_EO_PL = 0x8000180D0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL3_O_PL = 0x8000900D0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_EO_PL = 0x8000200D0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_O_PL = 0x8000980D0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL = 0x8000280D0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_O_PL = 0x8000A00D0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL6_EO_PL = 0x8000300D0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL6_O_PL = 0x8000A80D0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL7_EO_PL = 0x8000380D0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL7_O_PL = 0x8000B00D0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL8_EO_PL = 0x8000400D0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL8_O_PL = 0x8000B80D0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL9_O_PL = 0x8000C00D0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x8000000D0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE1_RX_FIR_ERROR_INJECT_PL = 0x8002180D0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE1_RX_FIR_MASK_PL = 0x8002100D0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE1_RX_FIR_PL = 0x8002080D0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE1_RX_SPARE_MODE_PL = 0x8002000D0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL = 0x8002480E0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL = 0x8002500E0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL = 0x8002580E0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL5_EO_PL = 0x8002600E0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL = 0x8002400E0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL = 0x8002200E0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE2_RX_BIT_MODE2_EO_PL = 0x8002280E0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL = 0x8002300E0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE2_RX_BIT_MODE4_EO_PL = 0x8002380E0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE2_RX_BIT_STAT1_EO_PL = 0x8002680E0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE2_RX_BIT_STAT1_O_PL = 0x8003180E0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL = 0x8002700E0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL = 0x8002780E0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE2_RX_BIT_STAT4_EO_PL = 0x8002800E0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL10_O_PL = 0x8000C80E0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL = 0x8000080E0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_O_PL = 0x8000800E0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_EO_PL = 0x8000100E0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_O_PL = 0x8000880E0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL3_EO_PL = 0x8000180E0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL3_O_PL = 0x8000900E0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_EO_PL = 0x8000200E0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_O_PL = 0x8000980E0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL = 0x8000280E0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_O_PL = 0x8000A00E0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL6_EO_PL = 0x8000300E0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL6_O_PL = 0x8000A80E0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL7_EO_PL = 0x8000380E0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL7_O_PL = 0x8000B00E0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL8_EO_PL = 0x8000400E0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL8_O_PL = 0x8000B80E0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL9_O_PL = 0x8000C00E0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x8000000E0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE2_RX_FIR_ERROR_INJECT_PL = 0x8002180E0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE2_RX_FIR_MASK_PL = 0x8002100E0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE2_RX_FIR_PL = 0x8002080E0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE2_RX_SPARE_MODE_PL = 0x8002000E0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL = 0x8002480F0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL = 0x8002500F0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL = 0x8002580F0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL5_EO_PL = 0x8002600F0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL = 0x8002400F0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL = 0x8002200F0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE3_RX_BIT_MODE2_EO_PL = 0x8002280F0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL = 0x8002300F0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE3_RX_BIT_MODE4_EO_PL = 0x8002380F0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE3_RX_BIT_STAT1_EO_PL = 0x8002680F0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE3_RX_BIT_STAT1_O_PL = 0x8003180F0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL = 0x8002700F0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL = 0x8002780F0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE3_RX_BIT_STAT4_EO_PL = 0x8002800F0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL10_O_PL = 0x8000C80F0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL = 0x8000080F0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_O_PL = 0x8000800F0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_EO_PL = 0x8000100F0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_O_PL = 0x8000880F0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL3_EO_PL = 0x8000180F0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL3_O_PL = 0x8000900F0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_EO_PL = 0x8000200F0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_O_PL = 0x8000980F0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL = 0x8000280F0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_O_PL = 0x8000A00F0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL6_EO_PL = 0x8000300F0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL6_O_PL = 0x8000A80F0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL7_EO_PL = 0x8000380F0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL7_O_PL = 0x8000B00F0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL8_EO_PL = 0x8000400F0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL8_O_PL = 0x8000B80F0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL9_O_PL = 0x8000C00F0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x8000000F0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE3_RX_FIR_ERROR_INJECT_PL = 0x8002180F0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE3_RX_FIR_MASK_PL = 0x8002100F0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE3_RX_FIR_PL = 0x8002080F0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS3_SLICE3_RX_SPARE_MODE_PL = 0x8002000F0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL2_EO_PL = 0x800248100C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL3_EO_PL = 0x800250100C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL4_EO_PL = 0x800258100C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL5_EO_PL = 0x800260100C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE0_RX_BIT_CNTLX1_EO_PL = 0x800240100C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE0_RX_BIT_MODE1_EO_PL = 0x800220100C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE0_RX_BIT_MODE2_EO_PL = 0x800228100C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE0_RX_BIT_MODE3_EO_PL = 0x800230100C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE0_RX_BIT_MODE4_EO_PL = 0x800238100C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE0_RX_BIT_STAT1_EO_PL = 0x800268100C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE0_RX_BIT_STAT1_O_PL = 0x800318100C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE0_RX_BIT_STAT2_EO_PL = 0x800270100C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE0_RX_BIT_STAT3_EO_PL = 0x800278100C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE0_RX_BIT_STAT4_EO_PL = 0x800280100C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL10_O_PL = 0x8000C8100C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL1_EO_PL = 0x800008100C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL1_O_PL = 0x800080100C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL2_EO_PL = 0x800010100C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL2_O_PL = 0x800088100C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL3_EO_PL = 0x800018100C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL3_O_PL = 0x800090100C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL4_EO_PL = 0x800020100C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL4_O_PL = 0x800098100C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL5_EO_PL = 0x800028100C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL5_O_PL = 0x8000A0100C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL6_EO_PL = 0x800030100C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL6_O_PL = 0x8000A8100C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL7_EO_PL = 0x800038100C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL7_O_PL = 0x8000B0100C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL8_EO_PL = 0x800040100C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL8_O_PL = 0x8000B8100C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL9_O_PL = 0x8000C0100C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE0_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x800000100C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE0_RX_FIR_ERROR_INJECT_PL = 0x800218100C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE0_RX_FIR_MASK_PL = 0x800210100C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE0_RX_FIR_PL = 0x800208100C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE0_RX_SPARE_MODE_PL = 0x800200100C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL2_EO_PL = 0x800248110C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL3_EO_PL = 0x800250110C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL4_EO_PL = 0x800258110C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL5_EO_PL = 0x800260110C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE1_RX_BIT_CNTLX1_EO_PL = 0x800240110C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE1_RX_BIT_MODE1_EO_PL = 0x800220110C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE1_RX_BIT_MODE2_EO_PL = 0x800228110C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE1_RX_BIT_MODE3_EO_PL = 0x800230110C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE1_RX_BIT_MODE4_EO_PL = 0x800238110C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE1_RX_BIT_STAT1_EO_PL = 0x800268110C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE1_RX_BIT_STAT1_O_PL = 0x800318110C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE1_RX_BIT_STAT2_EO_PL = 0x800270110C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE1_RX_BIT_STAT3_EO_PL = 0x800278110C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE1_RX_BIT_STAT4_EO_PL = 0x800280110C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL10_O_PL = 0x8000C8110C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL1_EO_PL = 0x800008110C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL1_O_PL = 0x800080110C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL2_EO_PL = 0x800010110C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL2_O_PL = 0x800088110C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL3_EO_PL = 0x800018110C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL3_O_PL = 0x800090110C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL4_EO_PL = 0x800020110C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL4_O_PL = 0x800098110C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL5_EO_PL = 0x800028110C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL5_O_PL = 0x8000A0110C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL6_EO_PL = 0x800030110C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL6_O_PL = 0x8000A8110C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL7_EO_PL = 0x800038110C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL7_O_PL = 0x8000B0110C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL8_EO_PL = 0x800040110C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL8_O_PL = 0x8000B8110C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL9_O_PL = 0x8000C0110C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE1_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x800000110C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE1_RX_FIR_ERROR_INJECT_PL = 0x800218110C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE1_RX_FIR_MASK_PL = 0x800210110C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE1_RX_FIR_PL = 0x800208110C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE1_RX_SPARE_MODE_PL = 0x800200110C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL2_EO_PL = 0x800248120C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL3_EO_PL = 0x800250120C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL4_EO_PL = 0x800258120C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL5_EO_PL = 0x800260120C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE2_RX_BIT_CNTLX1_EO_PL = 0x800240120C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE2_RX_BIT_MODE1_EO_PL = 0x800220120C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE2_RX_BIT_MODE2_EO_PL = 0x800228120C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE2_RX_BIT_MODE3_EO_PL = 0x800230120C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE2_RX_BIT_MODE4_EO_PL = 0x800238120C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE2_RX_BIT_STAT1_EO_PL = 0x800268120C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE2_RX_BIT_STAT1_O_PL = 0x800318120C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE2_RX_BIT_STAT2_EO_PL = 0x800270120C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE2_RX_BIT_STAT3_EO_PL = 0x800278120C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE2_RX_BIT_STAT4_EO_PL = 0x800280120C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL10_O_PL = 0x8000C8120C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL1_EO_PL = 0x800008120C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL1_O_PL = 0x800080120C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL2_EO_PL = 0x800010120C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL2_O_PL = 0x800088120C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL3_EO_PL = 0x800018120C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL3_O_PL = 0x800090120C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL4_EO_PL = 0x800020120C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL4_O_PL = 0x800098120C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL5_EO_PL = 0x800028120C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL5_O_PL = 0x8000A0120C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL6_EO_PL = 0x800030120C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL6_O_PL = 0x8000A8120C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL7_EO_PL = 0x800038120C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL7_O_PL = 0x8000B0120C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL8_EO_PL = 0x800040120C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL8_O_PL = 0x8000B8120C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL9_O_PL = 0x8000C0120C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE2_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x800000120C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE2_RX_FIR_ERROR_INJECT_PL = 0x800218120C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE2_RX_FIR_MASK_PL = 0x800210120C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE2_RX_FIR_PL = 0x800208120C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE2_RX_SPARE_MODE_PL = 0x800200120C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL2_EO_PL = 0x800248130C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL3_EO_PL = 0x800250130C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL4_EO_PL = 0x800258130C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL5_EO_PL = 0x800260130C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE3_RX_BIT_CNTLX1_EO_PL = 0x800240130C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE3_RX_BIT_MODE1_EO_PL = 0x800220130C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE3_RX_BIT_MODE2_EO_PL = 0x800228130C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE3_RX_BIT_MODE3_EO_PL = 0x800230130C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE3_RX_BIT_MODE4_EO_PL = 0x800238130C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE3_RX_BIT_STAT1_EO_PL = 0x800268130C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE3_RX_BIT_STAT1_O_PL = 0x800318130C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE3_RX_BIT_STAT2_EO_PL = 0x800270130C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE3_RX_BIT_STAT3_EO_PL = 0x800278130C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE3_RX_BIT_STAT4_EO_PL = 0x800280130C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL10_O_PL = 0x8000C8130C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL1_EO_PL = 0x800008130C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL1_O_PL = 0x800080130C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL2_EO_PL = 0x800010130C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL2_O_PL = 0x800088130C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL3_EO_PL = 0x800018130C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL3_O_PL = 0x800090130C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL4_EO_PL = 0x800020130C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL4_O_PL = 0x800098130C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL5_EO_PL = 0x800028130C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL5_O_PL = 0x8000A0130C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL6_EO_PL = 0x800030130C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL6_O_PL = 0x8000A8130C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL7_EO_PL = 0x800038130C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL7_O_PL = 0x8000B0130C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL8_EO_PL = 0x800040130C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL8_O_PL = 0x8000B8130C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL9_O_PL = 0x8000C0130C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE3_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x800000130C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE3_RX_FIR_ERROR_INJECT_PL = 0x800218130C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE3_RX_FIR_MASK_PL = 0x800210130C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE3_RX_FIR_PL = 0x800208130C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS4_SLICE3_RX_SPARE_MODE_PL = 0x800200130C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL2_EO_PL = 0x800248140C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL3_EO_PL = 0x800250140C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL4_EO_PL = 0x800258140C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL5_EO_PL = 0x800260140C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE0_RX_BIT_CNTLX1_EO_PL = 0x800240140C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE0_RX_BIT_MODE1_EO_PL = 0x800220140C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE0_RX_BIT_MODE2_EO_PL = 0x800228140C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE0_RX_BIT_MODE3_EO_PL = 0x800230140C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE0_RX_BIT_MODE4_EO_PL = 0x800238140C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE0_RX_BIT_STAT1_EO_PL = 0x800268140C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE0_RX_BIT_STAT1_O_PL = 0x800318140C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE0_RX_BIT_STAT2_EO_PL = 0x800270140C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE0_RX_BIT_STAT3_EO_PL = 0x800278140C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE0_RX_BIT_STAT4_EO_PL = 0x800280140C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL10_O_PL = 0x8000C8140C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL1_EO_PL = 0x800008140C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL1_O_PL = 0x800080140C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL2_EO_PL = 0x800010140C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL2_O_PL = 0x800088140C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL3_EO_PL = 0x800018140C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL3_O_PL = 0x800090140C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL4_EO_PL = 0x800020140C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL4_O_PL = 0x800098140C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL5_EO_PL = 0x800028140C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL5_O_PL = 0x8000A0140C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL6_EO_PL = 0x800030140C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL6_O_PL = 0x8000A8140C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL7_EO_PL = 0x800038140C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL7_O_PL = 0x8000B0140C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL8_EO_PL = 0x800040140C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL8_O_PL = 0x8000B8140C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL9_O_PL = 0x8000C0140C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE0_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x800000140C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE0_RX_FIR_ERROR_INJECT_PL = 0x800218140C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE0_RX_FIR_MASK_PL = 0x800210140C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE0_RX_FIR_PL = 0x800208140C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE0_RX_SPARE_MODE_PL = 0x800200140C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL2_EO_PL = 0x800248150C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL3_EO_PL = 0x800250150C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL4_EO_PL = 0x800258150C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL5_EO_PL = 0x800260150C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE1_RX_BIT_CNTLX1_EO_PL = 0x800240150C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE1_RX_BIT_MODE1_EO_PL = 0x800220150C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE1_RX_BIT_MODE2_EO_PL = 0x800228150C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE1_RX_BIT_MODE3_EO_PL = 0x800230150C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE1_RX_BIT_MODE4_EO_PL = 0x800238150C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE1_RX_BIT_STAT1_EO_PL = 0x800268150C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE1_RX_BIT_STAT1_O_PL = 0x800318150C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE1_RX_BIT_STAT2_EO_PL = 0x800270150C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE1_RX_BIT_STAT3_EO_PL = 0x800278150C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE1_RX_BIT_STAT4_EO_PL = 0x800280150C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL10_O_PL = 0x8000C8150C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL1_EO_PL = 0x800008150C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL1_O_PL = 0x800080150C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL2_EO_PL = 0x800010150C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL2_O_PL = 0x800088150C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL3_EO_PL = 0x800018150C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL3_O_PL = 0x800090150C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL4_EO_PL = 0x800020150C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL4_O_PL = 0x800098150C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL5_EO_PL = 0x800028150C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL5_O_PL = 0x8000A0150C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL6_EO_PL = 0x800030150C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL6_O_PL = 0x8000A8150C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL7_EO_PL = 0x800038150C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL7_O_PL = 0x8000B0150C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL8_EO_PL = 0x800040150C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL8_O_PL = 0x8000B8150C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL9_O_PL = 0x8000C0150C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE1_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x800000150C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE1_RX_FIR_ERROR_INJECT_PL = 0x800218150C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE1_RX_FIR_MASK_PL = 0x800210150C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE1_RX_FIR_PL = 0x800208150C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE1_RX_SPARE_MODE_PL = 0x800200150C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL2_EO_PL = 0x800248160C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL3_EO_PL = 0x800250160C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL4_EO_PL = 0x800258160C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL5_EO_PL = 0x800260160C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE2_RX_BIT_CNTLX1_EO_PL = 0x800240160C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE2_RX_BIT_MODE1_EO_PL = 0x800220160C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE2_RX_BIT_MODE2_EO_PL = 0x800228160C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE2_RX_BIT_MODE3_EO_PL = 0x800230160C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE2_RX_BIT_MODE4_EO_PL = 0x800238160C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE2_RX_BIT_STAT1_EO_PL = 0x800268160C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE2_RX_BIT_STAT1_O_PL = 0x800318160C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE2_RX_BIT_STAT2_EO_PL = 0x800270160C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE2_RX_BIT_STAT3_EO_PL = 0x800278160C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE2_RX_BIT_STAT4_EO_PL = 0x800280160C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL10_O_PL = 0x8000C8160C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL1_EO_PL = 0x800008160C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL1_O_PL = 0x800080160C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL2_EO_PL = 0x800010160C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL2_O_PL = 0x800088160C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL3_EO_PL = 0x800018160C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL3_O_PL = 0x800090160C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL4_EO_PL = 0x800020160C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL4_O_PL = 0x800098160C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL5_EO_PL = 0x800028160C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL5_O_PL = 0x8000A0160C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL6_EO_PL = 0x800030160C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL6_O_PL = 0x8000A8160C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL7_EO_PL = 0x800038160C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL7_O_PL = 0x8000B0160C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL8_EO_PL = 0x800040160C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL8_O_PL = 0x8000B8160C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL9_O_PL = 0x8000C0160C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE2_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x800000160C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE2_RX_FIR_ERROR_INJECT_PL = 0x800218160C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE2_RX_FIR_MASK_PL = 0x800210160C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE2_RX_FIR_PL = 0x800208160C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE2_RX_SPARE_MODE_PL = 0x800200160C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL2_EO_PL = 0x800248170C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL3_EO_PL = 0x800250170C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL4_EO_PL = 0x800258170C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL5_EO_PL = 0x800260170C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE3_RX_BIT_CNTLX1_EO_PL = 0x800240170C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE3_RX_BIT_MODE1_EO_PL = 0x800220170C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE3_RX_BIT_MODE2_EO_PL = 0x800228170C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE3_RX_BIT_MODE3_EO_PL = 0x800230170C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE3_RX_BIT_MODE4_EO_PL = 0x800238170C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE3_RX_BIT_STAT1_EO_PL = 0x800268170C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE3_RX_BIT_STAT1_O_PL = 0x800318170C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE3_RX_BIT_STAT2_EO_PL = 0x800270170C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE3_RX_BIT_STAT3_EO_PL = 0x800278170C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE3_RX_BIT_STAT4_EO_PL = 0x800280170C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL10_O_PL = 0x8000C8170C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL1_EO_PL = 0x800008170C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL1_O_PL = 0x800080170C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL2_EO_PL = 0x800010170C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL2_O_PL = 0x800088170C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL3_EO_PL = 0x800018170C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL3_O_PL = 0x800090170C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL4_EO_PL = 0x800020170C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL4_O_PL = 0x800098170C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL5_EO_PL = 0x800028170C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL5_O_PL = 0x8000A0170C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL6_EO_PL = 0x800030170C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL6_O_PL = 0x8000A8170C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL7_EO_PL = 0x800038170C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL7_O_PL = 0x8000B0170C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL8_EO_PL = 0x800040170C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL8_O_PL = 0x8000B8170C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL9_O_PL = 0x8000C0170C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE3_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x800000170C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE3_RX_FIR_ERROR_INJECT_PL = 0x800218170C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE3_RX_FIR_MASK_PL = 0x800210170C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE3_RX_FIR_PL = 0x800208170C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RXPACKS5_SLICE3_RX_SPARE_MODE_PL = 0x800200170C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RX_CTL_CNTL10_EO_PG = 0x800920000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RX_CTL_CNTL11_EO_PG = 0x800928000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RX_CTL_CNTL12_EO_PG = 0x800930000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RX_CTL_CNTL13_EO_PG = 0x800938000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RX_CTL_CNTL14_EO_PG = 0x800940000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RX_CTL_CNTL1_EO_PG = 0x8008D8000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RX_CTL_CNTL2_EO_PG = 0x8008E0000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RX_CTL_CNTL3_EO_PG = 0x8008E8000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RX_CTL_CNTL4_EO_PG = 0x8008F0000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RX_CTL_CNTL5_EO_PG = 0x8008F8000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RX_CTL_CNTL6_EO_PG = 0x800900000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RX_CTL_CNTL8_EO_PG = 0x800910000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RX_CTL_CNTL9_EO_PG = 0x800918000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RX_CTL_CNTLX7_EO_PG = 0x800908000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RX_CTL_MODE10_EO_PG = 0x800858000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RX_CTL_MODE11_EO_PG = 0x800860000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RX_CTL_MODE12_EO_PG = 0x800868000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RX_CTL_MODE13_EO_PG = 0x800870000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RX_CTL_MODE14_EO_PG = 0x800878000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RX_CTL_MODE15_EO_PG = 0x800880000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RX_CTL_MODE16_EO_PG = 0x800888000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RX_CTL_MODE17_EO_PG = 0x800890000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RX_CTL_MODE18_EO_PG = 0x800898000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RX_CTL_MODE19_EO_PG = 0x8008A0000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RX_CTL_MODE1_EO_PG = 0x800810000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RX_CTL_MODE1_O_PG = 0x8009B0000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RX_CTL_MODE20_EO_PG = 0x8008A8000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RX_CTL_MODE21_EO_PG = 0x8008B0000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RX_CTL_MODE22_EO_PG = 0x8008B8000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RX_CTL_MODE23_EO_PG = 0x8008C0000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RX_CTL_MODE24_EO_PG = 0x8008C8000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RX_CTL_MODE26_EO_PG = 0x800968000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RX_CTL_MODE27_EO_PG = 0x800970000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RX_CTL_MODE28_EO_PG = 0x800978000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RX_CTL_MODE29_EO_PG = 0x8008D0000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RX_CTL_MODE2_EO_PG = 0x800818000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RX_CTL_MODE2_O_PG = 0x800988000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RX_CTL_MODE5_EO_PG = 0x800830000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RX_CTL_MODE6_EO_PG = 0x800838000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RX_CTL_MODE7_EO_PG = 0x800840000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RX_CTL_MODE9_EO_PG = 0x800850000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RX_CTL_STAT1_EO_PG = 0x800950000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RX_CTL_STAT2_EO_PG = 0x800958000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RX_DATASM_CNTLX1_EO_PG = 0x800B88000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RX_DATASM_SPARE_MODE_PG = 0x800B80000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RX_DATASM_STAT10_EO_PG = 0x800BD8000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RX_DATASM_STAT11_EO_PG = 0x800BE0000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RX_DATASM_STAT1_EO_PG = 0x800B90000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RX_DATASM_STAT2_EO_PG = 0x800B98000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RX_DATASM_STAT3_EO_PG = 0x800BA0000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RX_DATASM_STAT4_EO_PG = 0x800BA8000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RX_DATASM_STAT5_EO_PG = 0x800BB0000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RX_DATASM_STAT6_EO_PG = 0x800BB8000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RX_DATASM_STAT7_EO_PG = 0x800BC0000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RX_DATASM_STAT8_EO_PG = 0x800BC8000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RX_DATASM_STAT9_EO_PG = 0x800BD0000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RX_FIR1_ERROR_INJECT_PG = 0x800A98000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RX_FIR1_MASK_PG = 0x800A90000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RX_FIR1_PG = 0x800A88000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RX_GLBSM_CNTL2_EO_PG = 0x800AE0000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RX_GLBSM_CNTL3_EO_PG = 0x800AE8000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RX_GLBSM_CNTL4_EO_PG = 0x800AF0000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RX_GLBSM_CNTLX1_EO_PG = 0x800AB0000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RX_GLBSM_MODE1_EO_PG = 0x800AF8000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RX_GLBSM_SPARE_MODE_PG = 0x800A80000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RX_GLBSM_STAT1_EO_PG = 0x800AB8000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RX_GLBSM_STAT2_EO_PG = 0x800AC0000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RX_GLBSM_STAT3_EO_PG = 0x800AC8000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RX_GLBSM_STAT4_EO_PG = 0x800AD0000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RX_GLBSM_STAT5_EO_PG = 0x800AD8000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RX_ID1_PG = 0x800808000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_RX_SPARE_MODE_PG = 0x800800000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE0_RX_DATA_WORK_SPARE_MODE_PL = 0x800380000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE0_RX_GLBSM_PL_CNTL1X_O_PL = 0x800330000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE0_RX_GLBSM_PL_CNTL1_O_PL = 0x800320000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE0_RX_GLBSM_PL_STAT1_O_PL = 0x800328000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE0_RX_WORK_CNTL1_O_PL = 0x8003A8000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE0_RX_WORK_STAT1_EO_PL = 0x800388000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE0_RX_WORK_STAT2_EO_PL = 0x800390000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE0_RX_WORK_STAT3_EO_PL = 0x800398000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE0_RX_WORK_STAT4_O_PL = 0x8003A0000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE10_RX_DATA_WORK_SPARE_MODE_PL = 0x8003800A0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE10_RX_GLBSM_PL_CNTL1X_O_PL = 0x8003300A0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE10_RX_GLBSM_PL_CNTL1_O_PL = 0x8003200A0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE10_RX_GLBSM_PL_STAT1_O_PL = 0x8003280A0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE10_RX_WORK_CNTL1_O_PL = 0x8003A80A0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE10_RX_WORK_STAT1_EO_PL = 0x8003880A0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE10_RX_WORK_STAT2_EO_PL = 0x8003900A0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE10_RX_WORK_STAT3_EO_PL = 0x8003980A0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE10_RX_WORK_STAT4_O_PL = 0x8003A00A0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE11_RX_DATA_WORK_SPARE_MODE_PL = 0x8003800B0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE11_RX_GLBSM_PL_CNTL1X_O_PL = 0x8003300B0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE11_RX_GLBSM_PL_CNTL1_O_PL = 0x8003200B0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE11_RX_GLBSM_PL_STAT1_O_PL = 0x8003280B0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE11_RX_WORK_CNTL1_O_PL = 0x8003A80B0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE11_RX_WORK_STAT1_EO_PL = 0x8003880B0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE11_RX_WORK_STAT2_EO_PL = 0x8003900B0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE11_RX_WORK_STAT3_EO_PL = 0x8003980B0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE11_RX_WORK_STAT4_O_PL = 0x8003A00B0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE12_RX_DATA_WORK_SPARE_MODE_PL = 0x8003800C0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE12_RX_GLBSM_PL_CNTL1X_O_PL = 0x8003300C0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE12_RX_GLBSM_PL_CNTL1_O_PL = 0x8003200C0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE12_RX_GLBSM_PL_STAT1_O_PL = 0x8003280C0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE12_RX_WORK_CNTL1_O_PL = 0x8003A80C0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE12_RX_WORK_STAT1_EO_PL = 0x8003880C0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE12_RX_WORK_STAT2_EO_PL = 0x8003900C0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE12_RX_WORK_STAT3_EO_PL = 0x8003980C0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE12_RX_WORK_STAT4_O_PL = 0x8003A00C0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE13_RX_DATA_WORK_SPARE_MODE_PL = 0x8003800D0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE13_RX_GLBSM_PL_CNTL1X_O_PL = 0x8003300D0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE13_RX_GLBSM_PL_CNTL1_O_PL = 0x8003200D0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE13_RX_GLBSM_PL_STAT1_O_PL = 0x8003280D0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE13_RX_WORK_CNTL1_O_PL = 0x8003A80D0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE13_RX_WORK_STAT1_EO_PL = 0x8003880D0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE13_RX_WORK_STAT2_EO_PL = 0x8003900D0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE13_RX_WORK_STAT3_EO_PL = 0x8003980D0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE13_RX_WORK_STAT4_O_PL = 0x8003A00D0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE14_RX_DATA_WORK_SPARE_MODE_PL = 0x8003800E0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE14_RX_GLBSM_PL_CNTL1X_O_PL = 0x8003300E0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE14_RX_GLBSM_PL_CNTL1_O_PL = 0x8003200E0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE14_RX_GLBSM_PL_STAT1_O_PL = 0x8003280E0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE14_RX_WORK_CNTL1_O_PL = 0x8003A80E0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE14_RX_WORK_STAT1_EO_PL = 0x8003880E0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE14_RX_WORK_STAT2_EO_PL = 0x8003900E0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE14_RX_WORK_STAT3_EO_PL = 0x8003980E0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE14_RX_WORK_STAT4_O_PL = 0x8003A00E0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE15_RX_DATA_WORK_SPARE_MODE_PL = 0x8003800F0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE15_RX_GLBSM_PL_CNTL1X_O_PL = 0x8003300F0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE15_RX_GLBSM_PL_CNTL1_O_PL = 0x8003200F0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE15_RX_GLBSM_PL_STAT1_O_PL = 0x8003280F0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE15_RX_WORK_CNTL1_O_PL = 0x8003A80F0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE15_RX_WORK_STAT1_EO_PL = 0x8003880F0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE15_RX_WORK_STAT2_EO_PL = 0x8003900F0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE15_RX_WORK_STAT3_EO_PL = 0x8003980F0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE15_RX_WORK_STAT4_O_PL = 0x8003A00F0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE16_RX_DATA_WORK_SPARE_MODE_PL = 0x800380100C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE16_RX_GLBSM_PL_CNTL1X_O_PL = 0x800330100C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE16_RX_GLBSM_PL_CNTL1_O_PL = 0x800320100C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE16_RX_GLBSM_PL_STAT1_O_PL = 0x800328100C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE16_RX_WORK_CNTL1_O_PL = 0x8003A8100C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE16_RX_WORK_STAT1_EO_PL = 0x800388100C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE16_RX_WORK_STAT2_EO_PL = 0x800390100C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE16_RX_WORK_STAT3_EO_PL = 0x800398100C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE16_RX_WORK_STAT4_O_PL = 0x8003A0100C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE17_RX_DATA_WORK_SPARE_MODE_PL = 0x800380110C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE17_RX_GLBSM_PL_CNTL1X_O_PL = 0x800330110C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE17_RX_GLBSM_PL_CNTL1_O_PL = 0x800320110C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE17_RX_GLBSM_PL_STAT1_O_PL = 0x800328110C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE17_RX_WORK_CNTL1_O_PL = 0x8003A8110C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE17_RX_WORK_STAT1_EO_PL = 0x800388110C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE17_RX_WORK_STAT2_EO_PL = 0x800390110C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE17_RX_WORK_STAT3_EO_PL = 0x800398110C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE17_RX_WORK_STAT4_O_PL = 0x8003A0110C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE18_RX_DATA_WORK_SPARE_MODE_PL = 0x800380120C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE18_RX_GLBSM_PL_CNTL1X_O_PL = 0x800330120C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE18_RX_GLBSM_PL_CNTL1_O_PL = 0x800320120C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE18_RX_GLBSM_PL_STAT1_O_PL = 0x800328120C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE18_RX_WORK_CNTL1_O_PL = 0x8003A8120C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE18_RX_WORK_STAT1_EO_PL = 0x800388120C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE18_RX_WORK_STAT2_EO_PL = 0x800390120C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE18_RX_WORK_STAT3_EO_PL = 0x800398120C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE18_RX_WORK_STAT4_O_PL = 0x8003A0120C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE19_RX_DATA_WORK_SPARE_MODE_PL = 0x800380130C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE19_RX_GLBSM_PL_CNTL1X_O_PL = 0x800330130C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE19_RX_GLBSM_PL_CNTL1_O_PL = 0x800320130C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE19_RX_GLBSM_PL_STAT1_O_PL = 0x800328130C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE19_RX_WORK_CNTL1_O_PL = 0x8003A8130C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE19_RX_WORK_STAT1_EO_PL = 0x800388130C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE19_RX_WORK_STAT2_EO_PL = 0x800390130C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE19_RX_WORK_STAT3_EO_PL = 0x800398130C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE19_RX_WORK_STAT4_O_PL = 0x8003A0130C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE1_RX_DATA_WORK_SPARE_MODE_PL = 0x800380010C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE1_RX_GLBSM_PL_CNTL1X_O_PL = 0x800330010C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE1_RX_GLBSM_PL_CNTL1_O_PL = 0x800320010C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE1_RX_GLBSM_PL_STAT1_O_PL = 0x800328010C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE1_RX_WORK_CNTL1_O_PL = 0x8003A8010C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE1_RX_WORK_STAT1_EO_PL = 0x800388010C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE1_RX_WORK_STAT2_EO_PL = 0x800390010C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE1_RX_WORK_STAT3_EO_PL = 0x800398010C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE1_RX_WORK_STAT4_O_PL = 0x8003A0010C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE20_RX_DATA_WORK_SPARE_MODE_PL = 0x800380140C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE20_RX_GLBSM_PL_CNTL1X_O_PL = 0x800330140C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE20_RX_GLBSM_PL_CNTL1_O_PL = 0x800320140C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE20_RX_GLBSM_PL_STAT1_O_PL = 0x800328140C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE20_RX_WORK_CNTL1_O_PL = 0x8003A8140C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE20_RX_WORK_STAT1_EO_PL = 0x800388140C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE20_RX_WORK_STAT2_EO_PL = 0x800390140C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE20_RX_WORK_STAT3_EO_PL = 0x800398140C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE20_RX_WORK_STAT4_O_PL = 0x8003A0140C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE21_RX_DATA_WORK_SPARE_MODE_PL = 0x800380150C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE21_RX_GLBSM_PL_CNTL1X_O_PL = 0x800330150C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE21_RX_GLBSM_PL_CNTL1_O_PL = 0x800320150C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE21_RX_GLBSM_PL_STAT1_O_PL = 0x800328150C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE21_RX_WORK_CNTL1_O_PL = 0x8003A8150C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE21_RX_WORK_STAT1_EO_PL = 0x800388150C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE21_RX_WORK_STAT2_EO_PL = 0x800390150C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE21_RX_WORK_STAT3_EO_PL = 0x800398150C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE21_RX_WORK_STAT4_O_PL = 0x8003A0150C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE22_RX_DATA_WORK_SPARE_MODE_PL = 0x800380160C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE22_RX_GLBSM_PL_CNTL1X_O_PL = 0x800330160C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE22_RX_GLBSM_PL_CNTL1_O_PL = 0x800320160C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE22_RX_GLBSM_PL_STAT1_O_PL = 0x800328160C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE22_RX_WORK_CNTL1_O_PL = 0x8003A8160C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE22_RX_WORK_STAT1_EO_PL = 0x800388160C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE22_RX_WORK_STAT2_EO_PL = 0x800390160C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE22_RX_WORK_STAT3_EO_PL = 0x800398160C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE22_RX_WORK_STAT4_O_PL = 0x8003A0160C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE23_RX_DATA_WORK_SPARE_MODE_PL = 0x800380170C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE23_RX_GLBSM_PL_CNTL1X_O_PL = 0x800330170C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE23_RX_GLBSM_PL_CNTL1_O_PL = 0x800320170C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE23_RX_GLBSM_PL_STAT1_O_PL = 0x800328170C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE23_RX_WORK_CNTL1_O_PL = 0x8003A8170C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE23_RX_WORK_STAT1_EO_PL = 0x800388170C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE23_RX_WORK_STAT2_EO_PL = 0x800390170C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE23_RX_WORK_STAT3_EO_PL = 0x800398170C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE23_RX_WORK_STAT4_O_PL = 0x8003A0170C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE2_RX_DATA_WORK_SPARE_MODE_PL = 0x800380020C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE2_RX_GLBSM_PL_CNTL1X_O_PL = 0x800330020C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE2_RX_GLBSM_PL_CNTL1_O_PL = 0x800320020C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE2_RX_GLBSM_PL_STAT1_O_PL = 0x800328020C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE2_RX_WORK_CNTL1_O_PL = 0x8003A8020C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE2_RX_WORK_STAT1_EO_PL = 0x800388020C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE2_RX_WORK_STAT2_EO_PL = 0x800390020C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE2_RX_WORK_STAT3_EO_PL = 0x800398020C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE2_RX_WORK_STAT4_O_PL = 0x8003A0020C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE3_RX_DATA_WORK_SPARE_MODE_PL = 0x800380030C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE3_RX_GLBSM_PL_CNTL1X_O_PL = 0x800330030C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE3_RX_GLBSM_PL_CNTL1_O_PL = 0x800320030C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE3_RX_GLBSM_PL_STAT1_O_PL = 0x800328030C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE3_RX_WORK_CNTL1_O_PL = 0x8003A8030C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE3_RX_WORK_STAT1_EO_PL = 0x800388030C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE3_RX_WORK_STAT2_EO_PL = 0x800390030C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE3_RX_WORK_STAT3_EO_PL = 0x800398030C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE3_RX_WORK_STAT4_O_PL = 0x8003A0030C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE4_RX_DATA_WORK_SPARE_MODE_PL = 0x800380040C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE4_RX_GLBSM_PL_CNTL1X_O_PL = 0x800330040C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE4_RX_GLBSM_PL_CNTL1_O_PL = 0x800320040C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE4_RX_GLBSM_PL_STAT1_O_PL = 0x800328040C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE4_RX_WORK_CNTL1_O_PL = 0x8003A8040C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE4_RX_WORK_STAT1_EO_PL = 0x800388040C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE4_RX_WORK_STAT2_EO_PL = 0x800390040C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE4_RX_WORK_STAT3_EO_PL = 0x800398040C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE4_RX_WORK_STAT4_O_PL = 0x8003A0040C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE5_RX_DATA_WORK_SPARE_MODE_PL = 0x800380050C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE5_RX_GLBSM_PL_CNTL1X_O_PL = 0x800330050C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE5_RX_GLBSM_PL_CNTL1_O_PL = 0x800320050C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE5_RX_GLBSM_PL_STAT1_O_PL = 0x800328050C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE5_RX_WORK_CNTL1_O_PL = 0x8003A8050C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE5_RX_WORK_STAT1_EO_PL = 0x800388050C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE5_RX_WORK_STAT2_EO_PL = 0x800390050C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE5_RX_WORK_STAT3_EO_PL = 0x800398050C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE5_RX_WORK_STAT4_O_PL = 0x8003A0050C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE6_RX_DATA_WORK_SPARE_MODE_PL = 0x800380060C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE6_RX_GLBSM_PL_CNTL1X_O_PL = 0x800330060C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE6_RX_GLBSM_PL_CNTL1_O_PL = 0x800320060C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE6_RX_GLBSM_PL_STAT1_O_PL = 0x800328060C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE6_RX_WORK_CNTL1_O_PL = 0x8003A8060C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE6_RX_WORK_STAT1_EO_PL = 0x800388060C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE6_RX_WORK_STAT2_EO_PL = 0x800390060C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE6_RX_WORK_STAT3_EO_PL = 0x800398060C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE6_RX_WORK_STAT4_O_PL = 0x8003A0060C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE7_RX_DATA_WORK_SPARE_MODE_PL = 0x800380070C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE7_RX_GLBSM_PL_CNTL1X_O_PL = 0x800330070C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE7_RX_GLBSM_PL_CNTL1_O_PL = 0x800320070C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE7_RX_GLBSM_PL_STAT1_O_PL = 0x800328070C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE7_RX_WORK_CNTL1_O_PL = 0x8003A8070C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE7_RX_WORK_STAT1_EO_PL = 0x800388070C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE7_RX_WORK_STAT2_EO_PL = 0x800390070C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE7_RX_WORK_STAT3_EO_PL = 0x800398070C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE7_RX_WORK_STAT4_O_PL = 0x8003A0070C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE8_RX_DATA_WORK_SPARE_MODE_PL = 0x800380080C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE8_RX_GLBSM_PL_CNTL1X_O_PL = 0x800330080C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE8_RX_GLBSM_PL_CNTL1_O_PL = 0x800320080C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE8_RX_GLBSM_PL_STAT1_O_PL = 0x800328080C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE8_RX_WORK_CNTL1_O_PL = 0x8003A8080C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE8_RX_WORK_STAT1_EO_PL = 0x800388080C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE8_RX_WORK_STAT2_EO_PL = 0x800390080C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE8_RX_WORK_STAT3_EO_PL = 0x800398080C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE8_RX_WORK_STAT4_O_PL = 0x8003A0080C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE9_RX_DATA_WORK_SPARE_MODE_PL = 0x800380090C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE9_RX_GLBSM_PL_CNTL1X_O_PL = 0x800330090C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE9_RX_GLBSM_PL_CNTL1_O_PL = 0x800320090C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE9_RX_GLBSM_PL_STAT1_O_PL = 0x800328090C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE9_RX_WORK_CNTL1_O_PL = 0x8003A8090C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE9_RX_WORK_STAT1_EO_PL = 0x800388090C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE9_RX_WORK_STAT2_EO_PL = 0x800390090C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE9_RX_WORK_STAT3_EO_PL = 0x800398090C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX0_SLICE9_RX_WORK_STAT4_O_PL = 0x8003A0090C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX_FIR_ERROR_INJECT_PB = 0x800F98000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX_FIR_MASK_PB = 0x800F90000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX_FIR_PB = 0x800F88000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_RX_FIR_RESET_PB = 0x800F80000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_SCOM_MODE_PB = 0x0C010C20ull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_SPARE_MODE_PB = 0x800F34000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS0_SLICE0_TX_CNTL1G_PL = 0x800414000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS0_SLICE0_TX_CNTL2_O_PL = 0x80044C000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS0_SLICE0_TX_CNTL3_EO_PL = 0x800454000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS0_SLICE0_TX_FIR_ERROR_INJECT_PL = 0x800434000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS0_SLICE0_TX_FIR_MASK_PL = 0x80042C000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS0_SLICE0_TX_FIR_PL = 0x800424000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS0_SLICE0_TX_MODE1_PL = 0x800404000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS0_SLICE0_TX_MODE2_PL = 0x80040C000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS0_SLICE0_TX_STAT1_PL = 0x80041C000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS0_SLICE1_TX_CNTL1G_PL = 0x800414010C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS0_SLICE1_TX_CNTL2_O_PL = 0x80044C010C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS0_SLICE1_TX_CNTL3_EO_PL = 0x800454010C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS0_SLICE1_TX_FIR_ERROR_INJECT_PL = 0x800434010C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS0_SLICE1_TX_FIR_MASK_PL = 0x80042C010C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS0_SLICE1_TX_FIR_PL = 0x800424010C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS0_SLICE1_TX_MODE1_PL = 0x800404010C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS0_SLICE1_TX_MODE2_PL = 0x80040C010C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS0_SLICE1_TX_STAT1_PL = 0x80041C010C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS0_SLICE2_TX_CNTL1G_PL = 0x800414020C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS0_SLICE2_TX_CNTL2_O_PL = 0x80044C020C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS0_SLICE2_TX_CNTL3_EO_PL = 0x800454020C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS0_SLICE2_TX_FIR_ERROR_INJECT_PL = 0x800434020C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS0_SLICE2_TX_FIR_MASK_PL = 0x80042C020C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS0_SLICE2_TX_FIR_PL = 0x800424020C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS0_SLICE2_TX_MODE1_PL = 0x800404020C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS0_SLICE2_TX_MODE2_PL = 0x80040C020C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS0_SLICE2_TX_STAT1_PL = 0x80041C020C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS0_SLICE3_TX_CNTL1G_PL = 0x800414030C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS0_SLICE3_TX_CNTL2_O_PL = 0x80044C030C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS0_SLICE3_TX_CNTL3_EO_PL = 0x800454030C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS0_SLICE3_TX_FIR_ERROR_INJECT_PL = 0x800434030C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS0_SLICE3_TX_FIR_MASK_PL = 0x80042C030C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS0_SLICE3_TX_FIR_PL = 0x800424030C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS0_SLICE3_TX_MODE1_PL = 0x800404030C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS0_SLICE3_TX_MODE2_PL = 0x80040C030C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS0_SLICE3_TX_STAT1_PL = 0x80041C030C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS1_SLICE0_TX_CNTL1G_PL = 0x800414040C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS1_SLICE0_TX_CNTL2_O_PL = 0x80044C040C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS1_SLICE0_TX_CNTL3_EO_PL = 0x800454040C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS1_SLICE0_TX_FIR_ERROR_INJECT_PL = 0x800434040C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS1_SLICE0_TX_FIR_MASK_PL = 0x80042C040C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS1_SLICE0_TX_FIR_PL = 0x800424040C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS1_SLICE0_TX_MODE1_PL = 0x800404040C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS1_SLICE0_TX_MODE2_PL = 0x80040C040C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS1_SLICE0_TX_STAT1_PL = 0x80041C040C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS1_SLICE1_TX_CNTL1G_PL = 0x800414050C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS1_SLICE1_TX_CNTL2_O_PL = 0x80044C050C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS1_SLICE1_TX_CNTL3_EO_PL = 0x800454050C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS1_SLICE1_TX_FIR_ERROR_INJECT_PL = 0x800434050C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS1_SLICE1_TX_FIR_MASK_PL = 0x80042C050C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS1_SLICE1_TX_FIR_PL = 0x800424050C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS1_SLICE1_TX_MODE1_PL = 0x800404050C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS1_SLICE1_TX_MODE2_PL = 0x80040C050C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS1_SLICE1_TX_STAT1_PL = 0x80041C050C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS1_SLICE2_TX_CNTL1G_PL = 0x800414060C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS1_SLICE2_TX_CNTL2_O_PL = 0x80044C060C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS1_SLICE2_TX_CNTL3_EO_PL = 0x800454060C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS1_SLICE2_TX_FIR_ERROR_INJECT_PL = 0x800434060C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS1_SLICE2_TX_FIR_MASK_PL = 0x80042C060C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS1_SLICE2_TX_FIR_PL = 0x800424060C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS1_SLICE2_TX_MODE1_PL = 0x800404060C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS1_SLICE2_TX_MODE2_PL = 0x80040C060C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS1_SLICE2_TX_STAT1_PL = 0x80041C060C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS1_SLICE3_TX_CNTL1G_PL = 0x800414070C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS1_SLICE3_TX_CNTL2_O_PL = 0x80044C070C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS1_SLICE3_TX_CNTL3_EO_PL = 0x800454070C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS1_SLICE3_TX_FIR_ERROR_INJECT_PL = 0x800434070C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS1_SLICE3_TX_FIR_MASK_PL = 0x80042C070C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS1_SLICE3_TX_FIR_PL = 0x800424070C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS1_SLICE3_TX_MODE1_PL = 0x800404070C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS1_SLICE3_TX_MODE2_PL = 0x80040C070C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS1_SLICE3_TX_STAT1_PL = 0x80041C070C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS2_SLICE0_TX_CNTL1G_PL = 0x800414080C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS2_SLICE0_TX_CNTL2_O_PL = 0x80044C080C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS2_SLICE0_TX_CNTL3_EO_PL = 0x800454080C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS2_SLICE0_TX_FIR_ERROR_INJECT_PL = 0x800434080C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS2_SLICE0_TX_FIR_MASK_PL = 0x80042C080C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS2_SLICE0_TX_FIR_PL = 0x800424080C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS2_SLICE0_TX_MODE1_PL = 0x800404080C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS2_SLICE0_TX_MODE2_PL = 0x80040C080C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS2_SLICE0_TX_STAT1_PL = 0x80041C080C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS2_SLICE1_TX_CNTL1G_PL = 0x800414090C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS2_SLICE1_TX_CNTL2_O_PL = 0x80044C090C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS2_SLICE1_TX_CNTL3_EO_PL = 0x800454090C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS2_SLICE1_TX_FIR_ERROR_INJECT_PL = 0x800434090C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS2_SLICE1_TX_FIR_MASK_PL = 0x80042C090C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS2_SLICE1_TX_FIR_PL = 0x800424090C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS2_SLICE1_TX_MODE1_PL = 0x800404090C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS2_SLICE1_TX_MODE2_PL = 0x80040C090C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS2_SLICE1_TX_STAT1_PL = 0x80041C090C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS2_SLICE2_TX_CNTL1G_PL = 0x8004140A0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS2_SLICE2_TX_CNTL2_O_PL = 0x80044C0A0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS2_SLICE2_TX_CNTL3_EO_PL = 0x8004540A0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS2_SLICE2_TX_FIR_ERROR_INJECT_PL = 0x8004340A0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS2_SLICE2_TX_FIR_MASK_PL = 0x80042C0A0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS2_SLICE2_TX_FIR_PL = 0x8004240A0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS2_SLICE2_TX_MODE1_PL = 0x8004040A0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS2_SLICE2_TX_MODE2_PL = 0x80040C0A0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS2_SLICE2_TX_STAT1_PL = 0x80041C0A0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS2_SLICE3_TX_CNTL1G_PL = 0x8004140B0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS2_SLICE3_TX_CNTL2_O_PL = 0x80044C0B0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS2_SLICE3_TX_CNTL3_EO_PL = 0x8004540B0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS2_SLICE3_TX_FIR_ERROR_INJECT_PL = 0x8004340B0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS2_SLICE3_TX_FIR_MASK_PL = 0x80042C0B0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS2_SLICE3_TX_FIR_PL = 0x8004240B0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS2_SLICE3_TX_MODE1_PL = 0x8004040B0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS2_SLICE3_TX_MODE2_PL = 0x80040C0B0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS2_SLICE3_TX_STAT1_PL = 0x80041C0B0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS3_SLICE0_TX_CNTL1G_PL = 0x8004140C0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS3_SLICE0_TX_CNTL2_O_PL = 0x80044C0C0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS3_SLICE0_TX_CNTL3_EO_PL = 0x8004540C0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS3_SLICE0_TX_FIR_ERROR_INJECT_PL = 0x8004340C0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS3_SLICE0_TX_FIR_MASK_PL = 0x80042C0C0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS3_SLICE0_TX_FIR_PL = 0x8004240C0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS3_SLICE0_TX_MODE1_PL = 0x8004040C0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS3_SLICE0_TX_MODE2_PL = 0x80040C0C0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS3_SLICE0_TX_STAT1_PL = 0x80041C0C0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS3_SLICE1_TX_CNTL1G_PL = 0x8004140D0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS3_SLICE1_TX_CNTL2_O_PL = 0x80044C0D0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS3_SLICE1_TX_CNTL3_EO_PL = 0x8004540D0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS3_SLICE1_TX_FIR_ERROR_INJECT_PL = 0x8004340D0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS3_SLICE1_TX_FIR_MASK_PL = 0x80042C0D0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS3_SLICE1_TX_FIR_PL = 0x8004240D0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS3_SLICE1_TX_MODE1_PL = 0x8004040D0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS3_SLICE1_TX_MODE2_PL = 0x80040C0D0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS3_SLICE1_TX_STAT1_PL = 0x80041C0D0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS3_SLICE2_TX_CNTL1G_PL = 0x8004140E0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS3_SLICE2_TX_CNTL2_O_PL = 0x80044C0E0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS3_SLICE2_TX_CNTL3_EO_PL = 0x8004540E0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS3_SLICE2_TX_FIR_ERROR_INJECT_PL = 0x8004340E0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS3_SLICE2_TX_FIR_MASK_PL = 0x80042C0E0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS3_SLICE2_TX_FIR_PL = 0x8004240E0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS3_SLICE2_TX_MODE1_PL = 0x8004040E0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS3_SLICE2_TX_MODE2_PL = 0x80040C0E0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS3_SLICE2_TX_STAT1_PL = 0x80041C0E0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS3_SLICE3_TX_CNTL1G_PL = 0x8004140F0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS3_SLICE3_TX_CNTL2_O_PL = 0x80044C0F0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS3_SLICE3_TX_CNTL3_EO_PL = 0x8004540F0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS3_SLICE3_TX_FIR_ERROR_INJECT_PL = 0x8004340F0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS3_SLICE3_TX_FIR_MASK_PL = 0x80042C0F0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS3_SLICE3_TX_FIR_PL = 0x8004240F0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS3_SLICE3_TX_MODE1_PL = 0x8004040F0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS3_SLICE3_TX_MODE2_PL = 0x80040C0F0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS3_SLICE3_TX_STAT1_PL = 0x80041C0F0C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS4_SLICE0_TX_CNTL1G_PL = 0x800414100C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS4_SLICE0_TX_CNTL2_O_PL = 0x80044C100C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS4_SLICE0_TX_CNTL3_EO_PL = 0x800454100C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS4_SLICE0_TX_FIR_ERROR_INJECT_PL = 0x800434100C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS4_SLICE0_TX_FIR_MASK_PL = 0x80042C100C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS4_SLICE0_TX_FIR_PL = 0x800424100C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS4_SLICE0_TX_MODE1_PL = 0x800404100C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS4_SLICE0_TX_MODE2_PL = 0x80040C100C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS4_SLICE0_TX_STAT1_PL = 0x80041C100C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS4_SLICE1_TX_CNTL1G_PL = 0x800414110C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS4_SLICE1_TX_CNTL2_O_PL = 0x80044C110C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS4_SLICE1_TX_CNTL3_EO_PL = 0x800454110C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS4_SLICE1_TX_FIR_ERROR_INJECT_PL = 0x800434110C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS4_SLICE1_TX_FIR_MASK_PL = 0x80042C110C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS4_SLICE1_TX_FIR_PL = 0x800424110C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS4_SLICE1_TX_MODE1_PL = 0x800404110C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS4_SLICE1_TX_MODE2_PL = 0x80040C110C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS4_SLICE1_TX_STAT1_PL = 0x80041C110C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS4_SLICE2_TX_CNTL1G_PL = 0x800414120C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS4_SLICE2_TX_CNTL2_O_PL = 0x80044C120C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS4_SLICE2_TX_CNTL3_EO_PL = 0x800454120C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS4_SLICE2_TX_FIR_ERROR_INJECT_PL = 0x800434120C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS4_SLICE2_TX_FIR_MASK_PL = 0x80042C120C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS4_SLICE2_TX_FIR_PL = 0x800424120C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS4_SLICE2_TX_MODE1_PL = 0x800404120C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS4_SLICE2_TX_MODE2_PL = 0x80040C120C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS4_SLICE2_TX_STAT1_PL = 0x80041C120C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS4_SLICE3_TX_CNTL1G_PL = 0x800414130C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS4_SLICE3_TX_CNTL2_O_PL = 0x80044C130C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS4_SLICE3_TX_CNTL3_EO_PL = 0x800454130C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS4_SLICE3_TX_FIR_ERROR_INJECT_PL = 0x800434130C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS4_SLICE3_TX_FIR_MASK_PL = 0x80042C130C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS4_SLICE3_TX_FIR_PL = 0x800424130C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS4_SLICE3_TX_MODE1_PL = 0x800404130C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS4_SLICE3_TX_MODE2_PL = 0x80040C130C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS4_SLICE3_TX_STAT1_PL = 0x80041C130C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS5_SLICE0_TX_CNTL1G_PL = 0x800414140C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS5_SLICE0_TX_CNTL2_O_PL = 0x80044C140C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS5_SLICE0_TX_CNTL3_EO_PL = 0x800454140C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS5_SLICE0_TX_FIR_ERROR_INJECT_PL = 0x800434140C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS5_SLICE0_TX_FIR_MASK_PL = 0x80042C140C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS5_SLICE0_TX_FIR_PL = 0x800424140C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS5_SLICE0_TX_MODE1_PL = 0x800404140C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS5_SLICE0_TX_MODE2_PL = 0x80040C140C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS5_SLICE0_TX_STAT1_PL = 0x80041C140C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS5_SLICE1_TX_CNTL1G_PL = 0x800414150C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS5_SLICE1_TX_CNTL2_O_PL = 0x80044C150C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS5_SLICE1_TX_CNTL3_EO_PL = 0x800454150C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS5_SLICE1_TX_FIR_ERROR_INJECT_PL = 0x800434150C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS5_SLICE1_TX_FIR_MASK_PL = 0x80042C150C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS5_SLICE1_TX_FIR_PL = 0x800424150C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS5_SLICE1_TX_MODE1_PL = 0x800404150C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS5_SLICE1_TX_MODE2_PL = 0x80040C150C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS5_SLICE1_TX_STAT1_PL = 0x80041C150C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS5_SLICE2_TX_CNTL1G_PL = 0x800414160C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS5_SLICE2_TX_CNTL2_O_PL = 0x80044C160C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS5_SLICE2_TX_CNTL3_EO_PL = 0x800454160C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS5_SLICE2_TX_FIR_ERROR_INJECT_PL = 0x800434160C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS5_SLICE2_TX_FIR_MASK_PL = 0x80042C160C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS5_SLICE2_TX_FIR_PL = 0x800424160C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS5_SLICE2_TX_MODE1_PL = 0x800404160C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS5_SLICE2_TX_MODE2_PL = 0x80040C160C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS5_SLICE2_TX_STAT1_PL = 0x80041C160C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS5_SLICE3_TX_CNTL1G_PL = 0x800414170C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS5_SLICE3_TX_CNTL2_O_PL = 0x80044C170C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS5_SLICE3_TX_CNTL3_EO_PL = 0x800454170C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS5_SLICE3_TX_FIR_ERROR_INJECT_PL = 0x800434170C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS5_SLICE3_TX_FIR_MASK_PL = 0x80042C170C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS5_SLICE3_TX_FIR_PL = 0x800424170C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS5_SLICE3_TX_MODE1_PL = 0x800404170C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS5_SLICE3_TX_MODE2_PL = 0x80040C170C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TXPACKS5_SLICE3_TX_STAT1_PL = 0x80041C170C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TX_CTLSM_CNTL1_EO_PG = 0x800D34000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TX_CTLSM_CNTL1_O_PG = 0x800D84000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TX_CTLSM_CNTL2_EO_PG = 0x800D3C000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TX_CTLSM_CNTL2_O_PG = 0x800D8C000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TX_CTLSM_CNTL3_EO_PG = 0x800D44000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TX_CTLSM_CNTL4_EO_PG = 0x800D4C000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TX_CTLSM_CNTL5_EO_PG = 0x800D54000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TX_CTLSM_CNTL6_EO_PG = 0x800D5C000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TX_CTLSM_CNTL7_EO_PG = 0x800D64000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TX_CTLSM_MODE1_EO_PG = 0x800D2C000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TX_CTLSM_SPARE_MODE_PG = 0x800D24000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TX_CTLSM_STAT1_EO_PG = 0x800D6C000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TX_CTL_CNTL10_EO_PG = 0x800CDC000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TX_CTL_CNTL2_EO_PG = 0x800C2C000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TX_CTL_CNTL3_EO_PG = 0x800C34000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TX_CTL_CNTL8_EO_PG = 0x800CCC000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TX_CTL_CNTL9_EO_PG = 0x800CD4000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TX_CTL_CNTLG1_EO_PG = 0x800C24000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TX_CTL_MODE1_EO_PG = 0x800C14000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TX_FIR_ERROR_INJECT_PG = 0x800D1C000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TX_FIR_MASK_PG = 0x800D0C000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TX_FIR_PG = 0x800D04000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TX_FIR_RESET_PG = 0x800D14000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TX_ID1_PG = 0x800C0C000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX0_TX_SPARE_MODE_PG = 0x800C04000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX_IMPCAL2_PB = 0x800F3C000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX_IMPCAL_NVAL_PB = 0x800F0C000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX_IMPCAL_PB = 0x800F04000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX_IMPCAL_PVAL_PB = 0x800F14000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX_IMPCAL_P_4X_PB = 0x800F1C000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX_IMPCAL_SWO1_PB = 0x800F24000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_IOO3_TX_IMPCAL_SWO2_PB = 0x800F2C000C010C3Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_MASK_REG = 0x09010803ull;
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_MASK_REG_AND =
+ 0x09010804ull;
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_MASK_REG_OR = 0x09010805ull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_MASK_REG = 0x09010803ull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_MASK_REG_AND =
+ 0x09010804ull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_MASK_REG_OR =
+ 0x09010805ull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_REG = 0x09010800ull;
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_REG_AND = 0x09010801ull;
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_REG_OR = 0x09010802ull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_REG = 0x09010800ull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_REG_AND = 0x09010801ull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_REG_OR = 0x09010802ull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_CONFIG = 0x0901080Aull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_LL0_IOOL_CONFIG = 0x0901080Aull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_CONTROL = 0x0901080Bull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_LL0_IOOL_CONTROL = 0x0901080Bull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_DLL_STATUS = 0x09010828ull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_LL0_IOOL_DLL_STATUS = 0x09010828ull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_ERR_INJ_LFSR = 0x0901081Bull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_LL0_IOOL_ERR_INJ_LFSR = 0x0901081Bull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_FIR_WOF_REG = 0x09010808ull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_LL0_IOOL_FIR_WOF_REG = 0x09010808ull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LAT_MEASURE = 0x0901080Eull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_LL0_IOOL_LAT_MEASURE = 0x0901080Eull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_EDPL_STATUS = 0x09010824ull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_LL0_IOOL_LINK0_EDPL_STATUS = 0x09010824ull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_ERROR_STATUS = 0x09010816ull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_LL0_IOOL_LINK0_ERROR_STATUS = 0x09010816ull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_INFO = 0x09010814ull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_LL0_IOOL_LINK0_INFO = 0x09010814ull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_QUALITY = 0x09010826ull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_LL0_IOOL_LINK0_QUALITY = 0x09010826ull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_RX_LANE_CONTROL = 0x09010812ull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_LL0_IOOL_LINK0_RX_LANE_CONTROL = 0x09010812ull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_SYN_CAPTURE = 0x09010822ull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_LL0_IOOL_LINK0_SYN_CAPTURE = 0x09010822ull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_TX_LANE_CONTROL = 0x09010810ull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_LL0_IOOL_LINK0_TX_LANE_CONTROL = 0x09010810ull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_EDPL_STATUS = 0x09010825ull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_LL0_IOOL_LINK1_EDPL_STATUS = 0x09010825ull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_ERROR_STATUS = 0x09010817ull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_LL0_IOOL_LINK1_ERROR_STATUS = 0x09010817ull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_INFO = 0x09010815ull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_LL0_IOOL_LINK1_INFO = 0x09010815ull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_QUALITY = 0x09010827ull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_LL0_IOOL_LINK1_QUALITY = 0x09010827ull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_RX_LANE_CONTROL = 0x09010813ull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_LL0_IOOL_LINK1_RX_LANE_CONTROL = 0x09010813ull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_SYN_CAPTURE = 0x09010823ull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_LL0_IOOL_LINK1_SYN_CAPTURE = 0x09010823ull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_TX_LANE_CONTROL = 0x09010811ull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_LL0_IOOL_LINK1_TX_LANE_CONTROL = 0x09010811ull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_MISC_ERROR_STATUS = 0x09010829ull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_LL0_IOOL_MISC_ERROR_STATUS = 0x09010829ull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_OPTICAL_CONFIG = 0x0901080Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_LL0_IOOL_OPTICAL_CONFIG = 0x0901080Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_COUNTERS_0 = 0x0901081Eull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_LL0_IOOL_PERF_COUNTERS_0 = 0x0901081Eull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_COUNTERS_1 = 0x0901081Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_LL0_IOOL_PERF_COUNTERS_1 = 0x0901081Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_COUNT_LSB_0 = 0x09010820ull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_LL0_IOOL_PERF_COUNT_LSB_0 = 0x09010820ull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_COUNT_LSB_1 = 0x09010821ull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_LL0_IOOL_PERF_COUNT_LSB_1 = 0x09010821ull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_SEL_CONFIG = 0x0901081Dull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_LL0_IOOL_PERF_SEL_CONFIG = 0x0901081Dull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_TRACE_CONFIG = 0x0901081Cull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_LL0_IOOL_PERF_TRACE_CONFIG = 0x0901081Cull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PHY_CONFIG = 0x0901080Cull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_LL0_IOOL_PHY_CONFIG = 0x0901080Cull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_REPLAY_THRESHOLD = 0x09010818ull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_LL0_IOOL_REPLAY_THRESHOLD = 0x09010818ull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_RETRAIN_THRESHOLD = 0x0901081Aull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_LL0_IOOL_RETRAIN_THRESHOLD = 0x0901081Aull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_SEC_CONFIG = 0x0901080Dull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_LL0_IOOL_SEC_CONFIG = 0x0901080Dull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_SL_ECC_THRESHOLD = 0x09010819ull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_LL0_IOOL_SL_ECC_THRESHOLD = 0x09010819ull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_LL0_ODL0_CONFIG = 0x0901082Aull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_LL0_ODL0_CONFIG = 0x0901082Aull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_LL0_ODL0_DLX_CONFIG = 0x09010830ull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_LL0_ODL0_DLX_CONFIG = 0x09010830ull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_LL0_ODL1_CONFIG = 0x0901082Bull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_LL0_ODL1_CONFIG = 0x0901082Bull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_LL0_ODL1_DLX_CONFIG = 0x09010831ull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_LL0_ODL1_DLX_CONFIG = 0x09010831ull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_LL0_PB_IOOL_FIR_ACTION0_REG = 0x09010806ull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_ACTION0_REG = 0x09010806ull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_LL0_PB_IOOL_FIR_ACTION1_REG = 0x09010807ull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_ACTION1_REG = 0x09010807ull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_LL3_C0_S0_P0_E9_LL3_C0_S0_P0_E9_LL3_PB_IOOL_FIR_MASK_REG = 0x0C010803ull;
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_LL3_C0_S0_P0_E9_LL3_C0_S0_P0_E9_LL3_PB_IOOL_FIR_MASK_REG_AND =
+ 0x0C010804ull;
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_LL3_C0_S0_P0_E9_LL3_C0_S0_P0_E9_LL3_PB_IOOL_FIR_MASK_REG_OR =
+ 0x0C010805ull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_LL3_C0_S0_P0_E9_LL3_C0_S0_P0_E9_LL3_PB_IOOL_FIR_REG = 0x0C010800ull;
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_LL3_C0_S0_P0_E9_LL3_C0_S0_P0_E9_LL3_PB_IOOL_FIR_REG_AND = 0x0C010801ull;
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_LL3_C0_S0_P0_E9_LL3_C0_S0_P0_E9_LL3_PB_IOOL_FIR_REG_OR = 0x0C010802ull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_LL3_IOOL_CONFIG = 0x0C01080Aull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_LL3_IOOL_CONTROL = 0x0C01080Bull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_LL3_IOOL_DLL_STATUS = 0x0C010828ull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_LL3_IOOL_ERR_INJ_LFSR = 0x0C01081Bull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_LL3_IOOL_FIR_WOF_REG = 0x0C010808ull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_LL3_IOOL_LAT_MEASURE = 0x0C01080Eull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_LL3_IOOL_LINK0_EDPL_STATUS = 0x0C010824ull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_LL3_IOOL_LINK0_ERROR_STATUS = 0x0C010816ull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_LL3_IOOL_LINK0_INFO = 0x0C010814ull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_LL3_IOOL_LINK0_QUALITY = 0x0C010826ull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_LL3_IOOL_LINK0_RX_LANE_CONTROL = 0x0C010812ull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_LL3_IOOL_LINK0_SYN_CAPTURE = 0x0C010822ull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_LL3_IOOL_LINK0_TX_LANE_CONTROL = 0x0C010810ull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_LL3_IOOL_LINK1_EDPL_STATUS = 0x0C010825ull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_LL3_IOOL_LINK1_ERROR_STATUS = 0x0C010817ull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_LL3_IOOL_LINK1_INFO = 0x0C010815ull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_LL3_IOOL_LINK1_QUALITY = 0x0C010827ull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_LL3_IOOL_LINK1_RX_LANE_CONTROL = 0x0C010813ull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_LL3_IOOL_LINK1_SYN_CAPTURE = 0x0C010823ull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_LL3_IOOL_LINK1_TX_LANE_CONTROL = 0x0C010811ull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_LL3_IOOL_MISC_ERROR_STATUS = 0x0C010829ull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_LL3_IOOL_OPTICAL_CONFIG = 0x0C01080Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_LL3_IOOL_PERF_COUNTERS_0 = 0x0C01081Eull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_LL3_IOOL_PERF_COUNTERS_1 = 0x0C01081Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_LL3_IOOL_PERF_COUNT_LSB_0 = 0x0C010820ull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_LL3_IOOL_PERF_COUNT_LSB_1 = 0x0C010821ull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_LL3_IOOL_PERF_SEL_CONFIG = 0x0C01081Dull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_LL3_IOOL_PERF_TRACE_CONFIG = 0x0C01081Cull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_LL3_IOOL_PHY_CONFIG = 0x0C01080Cull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_LL3_IOOL_REPLAY_THRESHOLD = 0x0C010818ull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_LL3_IOOL_RETRAIN_THRESHOLD = 0x0C01081Aull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_LL3_IOOL_SEC_CONFIG = 0x0C01080Dull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_LL3_IOOL_SL_ECC_THRESHOLD = 0x0C010819ull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_LL3_ODL0_CONFIG = 0x0C01082Aull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_LL3_ODL0_DLX_CONFIG = 0x0C010830ull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_LL3_ODL1_CONFIG = 0x0C01082Bull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_LL3_ODL1_DLX_CONFIG = 0x0C010831ull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_LL3_PB_IOOL_FIR_ACTION0_REG = 0x0C010806ull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_LL3_PB_IOOL_FIR_ACTION1_REG = 0x0C010807ull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL0_DLX_INFO = 0x09010832ull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_NV0_ODL0_DLX_INFO = 0x09010832ull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL0_STATUS = 0x0901082Cull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_NV0_ODL0_STATUS = 0x0901082Cull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL0_TRAINING_STATUS = 0x0901082Eull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_NV0_ODL0_TRAINING_STATUS = 0x0901082Eull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL1_DLX_INFO = 0x09010833ull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_NV0_ODL1_DLX_INFO = 0x09010833ull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL1_STATUS = 0x0901082Dull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_NV0_ODL1_STATUS = 0x0901082Dull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL1_TRAINING_STATUS = 0x0901082Full;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_NV0_ODL1_TRAINING_STATUS = 0x0901082Full;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_NV1_ODL0_DLX_INFO = 0x0C010832ull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_NV1_ODL0_STATUS = 0x0C01082Cull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_NV1_ODL0_TRAINING_STATUS = 0x0C01082Eull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_NV1_ODL1_DLX_INFO = 0x0C010833ull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_NV1_ODL1_STATUS = 0x0C01082Dull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_NV1_ODL1_TRAINING_STATUS = 0x0C01082Full;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_ADDR_TRAP_REG = 0x09010003ull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_TCOB0_ADDR_TRAP_REG = 0x09010003ull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_ATOMIC_LOCK_MASK_LATCH_REG = 0x09010007ull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_TCOB0_ATOMIC_LOCK_MASK_LATCH_REG = 0x09010007ull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST1_COND_REG_1 = 0x090107C1ull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_TCOB0_DBG_INST1_COND_REG_1 = 0x090107C1ull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST1_COND_REG_2 = 0x090107C2ull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_TCOB0_DBG_INST1_COND_REG_2 = 0x090107C2ull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST1_COND_REG_3 = 0x090107C3ull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_TCOB0_DBG_INST1_COND_REG_3 = 0x090107C3ull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST2_COND_REG_1 = 0x090107C4ull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_TCOB0_DBG_INST2_COND_REG_1 = 0x090107C4ull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST2_COND_REG_2 = 0x090107C5ull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_TCOB0_DBG_INST2_COND_REG_2 = 0x090107C5ull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST2_COND_REG_3 = 0x090107C6ull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_TCOB0_DBG_INST2_COND_REG_3 = 0x090107C6ull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_MODE_REG = 0x090107C0ull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_TCOB0_DBG_MODE_REG = 0x090107C0ull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_TRACE_MODE_REG_2 = 0x090107CFull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_TCOB0_DBG_TRACE_MODE_REG_2 = 0x090107CFull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_TRACE_REG_0 = 0x090107CDull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_TCOB0_DBG_TRACE_REG_0 = 0x090107CDull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_TRACE_REG_1 = 0x090107CEull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_TCOB0_DBG_TRACE_REG_1 = 0x090107CEull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DEBUG_TRACE_CONTROL = 0x090107D0ull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_TCOB0_DEBUG_TRACE_CONTROL = 0x090107D0ull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_PSCOM_ERROR_MASK = 0x09010002ull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_TCOB0_PSCOM_ERROR_MASK = 0x09010002ull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_PSCOM_MODE_REG = 0x09010000ull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_TCOB0_PSCOM_MODE_REG = 0x09010000ull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_PSCOM_STATUS_ERROR_REG = 0x09010001ull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_TCOB0_PSCOM_STATUS_ERROR_REG = 0x09010001ull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_RING_FENCE_MASK_LATCH_REG = 0x09010008ull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_TCOB0_RING_FENCE_MASK_LATCH_REG = 0x09010008ull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_HI_DATA_REG = 0x09010400ull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_HI_DATA_REG = 0x09010400ull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_LO_DATA_REG = 0x09010401ull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_LO_DATA_REG = 0x09010401ull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRCTRL_CONFIG = 0x09010402ull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRCTRL_CONFIG = 0x09010402ull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_0 = 0x09010403ull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_0 = 0x09010403ull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_1 = 0x09010404ull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_1 = 0x09010404ull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_2 = 0x09010405ull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_2 = 0x09010405ull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_3 = 0x09010406ull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_3 = 0x09010406ull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_4 = 0x09010407ull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_4 = 0x09010407ull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_5 = 0x09010408ull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_5 = 0x09010408ull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9 = 0x09010409ull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9 = 0x09010409ull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_WRITE_PROTECT_ENABLE_REG = 0x09010005ull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_TCOB0_WRITE_PROTECT_ENABLE_REG = 0x09010005ull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_WRITE_PROTECT_RINGS_REG = 0x09010006ull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_TCOB0_WRITE_PROTECT_RINGS_REG = 0x09010006ull;
+
+
+static const uint64_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_XTRA_TRACE_MODE = 0x090107D1ull;
+
+static const uint64_t P9N2_OBUS_0_C0_S0_P0_E9_TCOB0_XTRA_TRACE_MODE = 0x090107D1ull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_TCOB3_ADDR_TRAP_REG = 0x0C010003ull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_TCOB3_ATOMIC_LOCK_MASK_LATCH_REG = 0x0C010007ull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_TCOB3_DBG_INST1_COND_REG_1 = 0x0C0107C1ull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_TCOB3_DBG_INST1_COND_REG_2 = 0x0C0107C2ull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_TCOB3_DBG_INST1_COND_REG_3 = 0x0C0107C3ull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_TCOB3_DBG_INST2_COND_REG_1 = 0x0C0107C4ull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_TCOB3_DBG_INST2_COND_REG_2 = 0x0C0107C5ull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_TCOB3_DBG_INST2_COND_REG_3 = 0x0C0107C6ull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_TCOB3_DBG_MODE_REG = 0x0C0107C0ull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_TCOB3_DBG_TRACE_MODE_REG_2 = 0x0C0107CFull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_TCOB3_DBG_TRACE_REG_0 = 0x0C0107CDull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_TCOB3_DBG_TRACE_REG_1 = 0x0C0107CEull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_TCOB3_DEBUG_TRACE_CONTROL = 0x0C0107D0ull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_TCOB3_PSCOM_ERROR_MASK = 0x0C010002ull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_TCOB3_PSCOM_MODE_REG = 0x0C010000ull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_TCOB3_PSCOM_STATUS_ERROR_REG = 0x0C010001ull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_TCOB3_RING_FENCE_MASK_LATCH_REG = 0x0C010008ull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_TCOB3_TRA0_TR0_TRACE_HI_DATA_REG = 0x0C010400ull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_TCOB3_TRA0_TR0_TRACE_LO_DATA_REG = 0x0C010401ull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_TCOB3_TRA0_TR0_TRACE_TRCTRL_CONFIG = 0x0C010402ull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_TCOB3_TRA0_TR0_TRACE_TRDATA_CONFIG_0 = 0x0C010403ull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_TCOB3_TRA0_TR0_TRACE_TRDATA_CONFIG_1 = 0x0C010404ull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_TCOB3_TRA0_TR0_TRACE_TRDATA_CONFIG_2 = 0x0C010405ull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_TCOB3_TRA0_TR0_TRACE_TRDATA_CONFIG_3 = 0x0C010406ull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_TCOB3_TRA0_TR0_TRACE_TRDATA_CONFIG_4 = 0x0C010407ull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_TCOB3_TRA0_TR0_TRACE_TRDATA_CONFIG_5 = 0x0C010408ull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_TCOB3_TRA0_TR0_TRACE_TRDATA_CONFIG_9 = 0x0C010409ull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_TCOB3_WRITE_PROTECT_ENABLE_REG = 0x0C010005ull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_TCOB3_WRITE_PROTECT_RINGS_REG = 0x0C010006ull;
+
+
+static const uint64_t P9N2_OBUS_3_C0_S0_P0_E9_TCOB3_XTRA_TRACE_MODE = 0x0C0107D1ull;
+
+#endif
+
diff --git a/src/import/chips/p9/common/include/p9n2_obus_scom_addresses_fld.H b/src/import/chips/p9/common/include/p9n2_obus_scom_addresses_fld.H
new file mode 100644
index 000000000..a4483cc35
--- /dev/null
+++ b/src/import/chips/p9/common/include/p9n2_obus_scom_addresses_fld.H
@@ -0,0 +1,10693 @@
+/* IBM_PROLOG_BEGIN_TAG */
+/* This is an automatically generated prolog. */
+/* */
+/* $Source: src/import/chips/p9/common/include/p9n2_obus_scom_addresses_fld.H $ */
+/* */
+/* OpenPOWER HostBoot Project */
+/* */
+/* Contributors Listed Below - COPYRIGHT 2017 */
+/* [+] International Business Machines Corp. */
+/* */
+/* */
+/* Licensed under the Apache License, Version 2.0 (the "License"); */
+/* you may not use this file except in compliance with the License. */
+/* You may obtain a copy of the License at */
+/* */
+/* http://www.apache.org/licenses/LICENSE-2.0 */
+/* */
+/* Unless required by applicable law or agreed to in writing, software */
+/* distributed under the License is distributed on an "AS IS" BASIS, */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */
+/* implied. See the License for the specific language governing */
+/* permissions and limitations under the License. */
+/* */
+/* IBM_PROLOG_END_TAG */
+///
+/// @file p9_obus_scom_addresses_fld.H
+/// @brief Defines constants for scom addresses
+///
+// *HWP HWP Owner: Ben Gass <bgass@us.ibm.com>
+// *HWP FW Owner: Thi Tran <thi@us.ibm.com>
+// *HWP Team: SOA
+// *HWP Level: 1
+// *HWP Consumed by: FSP:HB:HS:OCC:SBE:CME:SGPE:PGPE:FPPE:IPPE
+
+
+#ifndef __P9N2_OBUS_SCOM_ADDRESSES_FLD_H
+#define __P9N2_OBUS_SCOM_ADDRESSES_FLD_H
+
+#include <stdint.h>
+
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_FIR_MASK_REG_RX_INVALID_STATE_OR_PARITY_ERROR = 0 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_FIR_MASK_REG_TX_INVALID_STATE_OR_PARITY_ERROR = 1 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_FIR_MASK_REG_GCR_HANG_ERROR = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_FIR_MASK_REG_UNUSED = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_FIR_MASK_REG_UNUSED_LEN = 45 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_FIR_MASK_REG_INTERNAL_SCOM_ERROR = 48
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_FIR_MASK_REG_INTERNAL_SCOM_ERROR_CLONE
+ = 49 ;
+
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_FIR_REG_RX_INVALID_STATE_OR_PARITY_ERROR = 0 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_FIR_REG_TX_INVALID_STATE_OR_PARITY_ERROR = 1 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_FIR_REG_GCR_HANG_ERROR = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_FIR_REG_UNUSED = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_FIR_REG_UNUSED_LEN = 45 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_FIR_REG_SCOMFIR_ERROR = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_FIR_REG_SCOMFIR_ERROR_CLONE = 49 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_FIR_ACTION0_REG_ACTION0 = 0 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_FIR_ACTION0_REG_ACTION0_LEN = 50 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_FIR_ACTION1_REG_ACTION1 = 0 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_FIR_ACTION1_REG_ACTION1_LEN = 50 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_FIR_WOF_REG_WOF = 0 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_FIR_WOF_REG_WOF_LEN = 50 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_B = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_EDGE = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DDC_B = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_B = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_B = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_B = 62 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN = 2
+ ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_PR_RESET = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_IORESET = 63 ;
+
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL
+ = 50 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_SEL_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_BANK_SEL_A = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_MARGIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_BIST_PIPE_DATA_SHIFT = 57 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_A = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_B = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL_PSAVE_DIG_REQ_DIS = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL_PSAVE_ANA_REQ_DIS = 53 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_MODE2_EO_PL_PR_FW_OFF = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_EN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_MODE4_EO_PL_PR_INVALID_LOCK_COARSE_EN = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE_LEN = 3
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN = 2
+ ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL =
+ 56 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL = 48
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN =
+ 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN =
+ 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL = 50
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_B_IP_RO_SIGNAL = 51
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL =
+ 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL
+ = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL
+ = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
+ 58 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL = 48
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN =
+ 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN
+ = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_RO_SIGNAL =
+ 48 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL =
+ 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN
+ = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_O_PL_B_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_O_PL_B_CONTROLS_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_O_PL_B_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_O_PL_B_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_O_PL_B_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_O_PL_B_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_O_PL_B_H1E_VAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_O_PL_B_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_O_PL_B_H1O_VAL = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_O_PL_B_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL7_O_PL_E_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL7_O_PL_E_CONTROLS_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL8_O_PL_E_OFFSET_E = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL8_O_PL_E_OFFSET_E_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL8_O_PL_E_OFFSET = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL8_O_PL_E_OFFSET_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_7 = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_CFG_LTE_MC = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_CFG_LTE_MC_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_FIR_MASK_PL_ERRS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_FIR_MASK_PL_ERRS_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_B = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_EDGE = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DDC_B = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_B = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_B = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_B = 62 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN = 2
+ ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_PR_RESET = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_IORESET = 63 ;
+
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL
+ = 50 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_SEL_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_BANK_SEL_A = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_MARGIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_BIST_PIPE_DATA_SHIFT = 57 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_A = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_B = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL_PSAVE_DIG_REQ_DIS = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL_PSAVE_ANA_REQ_DIS = 53 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE2_EO_PL_PR_FW_OFF = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_EN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE4_EO_PL_PR_INVALID_LOCK_COARSE_EN = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE_LEN = 3
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN = 2
+ ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL =
+ 56 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL = 48
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN =
+ 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN =
+ 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL = 50
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_B_IP_RO_SIGNAL = 51
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL =
+ 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL
+ = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL
+ = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
+ 58 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL = 48
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN =
+ 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN
+ = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_RO_SIGNAL =
+ 48 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL =
+ 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN
+ = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_O_PL_B_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_O_PL_B_CONTROLS_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_O_PL_B_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_O_PL_B_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_O_PL_B_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_O_PL_B_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_O_PL_B_H1E_VAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_O_PL_B_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_O_PL_B_H1O_VAL = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_O_PL_B_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL7_O_PL_E_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL7_O_PL_E_CONTROLS_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL8_O_PL_E_OFFSET_E = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL8_O_PL_E_OFFSET_E_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL8_O_PL_E_OFFSET = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL8_O_PL_E_OFFSET_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_7 = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_CFG_LTE_MC = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_CFG_LTE_MC_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_FIR_MASK_PL_ERRS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_FIR_MASK_PL_ERRS_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_B = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_EDGE = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DDC_B = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_B = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_B = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_B = 62 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN = 2
+ ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_PR_RESET = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_IORESET = 63 ;
+
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL
+ = 50 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_SEL_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_BANK_SEL_A = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_MARGIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_BIST_PIPE_DATA_SHIFT = 57 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_A = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_B = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL_PSAVE_DIG_REQ_DIS = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL_PSAVE_ANA_REQ_DIS = 53 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_MODE2_EO_PL_PR_FW_OFF = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_EN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_MODE4_EO_PL_PR_INVALID_LOCK_COARSE_EN = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE_LEN = 3
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN = 2
+ ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL =
+ 56 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL = 48
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN =
+ 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN =
+ 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL = 50
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_B_IP_RO_SIGNAL = 51
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL =
+ 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL
+ = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL
+ = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
+ 58 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL = 48
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN =
+ 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN
+ = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_RO_SIGNAL =
+ 48 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL =
+ 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN
+ = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_O_PL_B_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_O_PL_B_CONTROLS_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_O_PL_B_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_O_PL_B_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_O_PL_B_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_O_PL_B_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_O_PL_B_H1E_VAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_O_PL_B_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_O_PL_B_H1O_VAL = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_O_PL_B_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL7_O_PL_E_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL7_O_PL_E_CONTROLS_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL8_O_PL_E_OFFSET_E = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL8_O_PL_E_OFFSET_E_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL8_O_PL_E_OFFSET = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL8_O_PL_E_OFFSET_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_7 = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_CFG_LTE_MC = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_CFG_LTE_MC_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_FIR_MASK_PL_ERRS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_FIR_MASK_PL_ERRS_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_B = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_EDGE = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DDC_B = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_B = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_B = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_B = 62 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN = 2
+ ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_PR_RESET = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_IORESET = 63 ;
+
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL
+ = 50 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_SEL_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_BANK_SEL_A = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_MARGIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_BIST_PIPE_DATA_SHIFT = 57 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_A = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_B = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL_PSAVE_DIG_REQ_DIS = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL_PSAVE_ANA_REQ_DIS = 53 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_MODE2_EO_PL_PR_FW_OFF = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_EN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_MODE4_EO_PL_PR_INVALID_LOCK_COARSE_EN = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE_LEN = 3
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN = 2
+ ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL =
+ 56 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL = 48
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN =
+ 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN =
+ 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL = 50
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_B_IP_RO_SIGNAL = 51
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL =
+ 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL
+ = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL
+ = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
+ 58 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL = 48
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN =
+ 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN
+ = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_RO_SIGNAL =
+ 48 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL =
+ 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN
+ = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_O_PL_B_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_O_PL_B_CONTROLS_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL3_O_PL_B_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL3_O_PL_B_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL3_O_PL_B_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL3_O_PL_B_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL6_O_PL_B_H1E_VAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL6_O_PL_B_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL6_O_PL_B_H1O_VAL = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL6_O_PL_B_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL7_O_PL_E_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL7_O_PL_E_CONTROLS_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL8_O_PL_E_OFFSET_E = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL8_O_PL_E_OFFSET_E_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL8_O_PL_E_OFFSET = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL8_O_PL_E_OFFSET_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_7 = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_CFG_LTE_MC = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_CFG_LTE_MC_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_FIR_MASK_PL_ERRS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_FIR_MASK_PL_ERRS_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_B = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_EDGE = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DDC_B = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_B = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_B = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_B = 62 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN = 2
+ ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_PR_RESET = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_IORESET = 63 ;
+
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL
+ = 50 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_SEL_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_BANK_SEL_A = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_MARGIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_BIST_PIPE_DATA_SHIFT = 57 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_A = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_B = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL_PSAVE_DIG_REQ_DIS = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL_PSAVE_ANA_REQ_DIS = 53 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_MODE2_EO_PL_PR_FW_OFF = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_EN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_MODE4_EO_PL_PR_INVALID_LOCK_COARSE_EN = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE_LEN = 3
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN = 2
+ ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL =
+ 56 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL = 48
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN =
+ 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN =
+ 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL = 50
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_B_IP_RO_SIGNAL = 51
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL =
+ 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL
+ = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL
+ = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
+ 58 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL = 48
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN =
+ 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN
+ = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_RO_SIGNAL =
+ 48 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL =
+ 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN
+ = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_O_PL_B_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_O_PL_B_CONTROLS_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL3_O_PL_B_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL3_O_PL_B_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL3_O_PL_B_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL3_O_PL_B_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL6_O_PL_B_H1E_VAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL6_O_PL_B_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL6_O_PL_B_H1O_VAL = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL6_O_PL_B_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL7_O_PL_E_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL7_O_PL_E_CONTROLS_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL8_O_PL_E_OFFSET_E = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL8_O_PL_E_OFFSET_E_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL8_O_PL_E_OFFSET = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL8_O_PL_E_OFFSET_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_7 = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_CFG_LTE_MC = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_CFG_LTE_MC_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_FIR_MASK_PL_ERRS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_FIR_MASK_PL_ERRS_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_B = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_EDGE = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DDC_B = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_B = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_B = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_B = 62 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN = 2
+ ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_PR_RESET = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_IORESET = 63 ;
+
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL
+ = 50 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_SEL_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_BANK_SEL_A = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_MARGIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_BIST_PIPE_DATA_SHIFT = 57 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_A = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_B = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL_PSAVE_DIG_REQ_DIS = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL_PSAVE_ANA_REQ_DIS = 53 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_MODE2_EO_PL_PR_FW_OFF = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_EN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_MODE4_EO_PL_PR_INVALID_LOCK_COARSE_EN = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE_LEN = 3
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN = 2
+ ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL =
+ 56 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL = 48
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN =
+ 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN =
+ 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL = 50
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_B_IP_RO_SIGNAL = 51
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL =
+ 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL
+ = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL
+ = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
+ 58 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL = 48
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN =
+ 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN
+ = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_RO_SIGNAL =
+ 48 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL =
+ 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN
+ = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_O_PL_B_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_O_PL_B_CONTROLS_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL3_O_PL_B_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL3_O_PL_B_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL3_O_PL_B_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL3_O_PL_B_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL6_O_PL_B_H1E_VAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL6_O_PL_B_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL6_O_PL_B_H1O_VAL = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL6_O_PL_B_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL7_O_PL_E_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL7_O_PL_E_CONTROLS_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL8_O_PL_E_OFFSET_E = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL8_O_PL_E_OFFSET_E_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL8_O_PL_E_OFFSET = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL8_O_PL_E_OFFSET_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_7 = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_CFG_LTE_MC = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_CFG_LTE_MC_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_FIR_MASK_PL_ERRS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_FIR_MASK_PL_ERRS_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_B = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_EDGE = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DDC_B = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_B = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_B = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_B = 62 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN = 2
+ ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_PR_RESET = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_IORESET = 63 ;
+
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL
+ = 50 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_SEL_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_BANK_SEL_A = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_MARGIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_BIST_PIPE_DATA_SHIFT = 57 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_A = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_B = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL_PSAVE_DIG_REQ_DIS = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL_PSAVE_ANA_REQ_DIS = 53 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_MODE2_EO_PL_PR_FW_OFF = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_EN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_MODE4_EO_PL_PR_INVALID_LOCK_COARSE_EN = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE_LEN = 3
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN = 2
+ ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL =
+ 56 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL = 48
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN =
+ 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN =
+ 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL = 50
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_B_IP_RO_SIGNAL = 51
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL =
+ 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL
+ = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL
+ = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
+ 58 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL = 48
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN =
+ 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN
+ = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_RO_SIGNAL =
+ 48 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL =
+ 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN
+ = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_O_PL_B_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_O_PL_B_CONTROLS_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL3_O_PL_B_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL3_O_PL_B_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL3_O_PL_B_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL3_O_PL_B_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL6_O_PL_B_H1E_VAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL6_O_PL_B_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL6_O_PL_B_H1O_VAL = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL6_O_PL_B_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL7_O_PL_E_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL7_O_PL_E_CONTROLS_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL8_O_PL_E_OFFSET_E = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL8_O_PL_E_OFFSET_E_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL8_O_PL_E_OFFSET = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL8_O_PL_E_OFFSET_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_7 = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_CFG_LTE_MC = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_CFG_LTE_MC_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_FIR_MASK_PL_ERRS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_FIR_MASK_PL_ERRS_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_B = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_EDGE = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DDC_B = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_B = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_B = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_B = 62 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN = 2
+ ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_PR_RESET = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_IORESET = 63 ;
+
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL
+ = 50 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_SEL_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_BANK_SEL_A = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_MARGIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_BIST_PIPE_DATA_SHIFT = 57 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_A = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_B = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL_PSAVE_DIG_REQ_DIS = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL_PSAVE_ANA_REQ_DIS = 53 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_MODE2_EO_PL_PR_FW_OFF = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_EN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_MODE4_EO_PL_PR_INVALID_LOCK_COARSE_EN = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE_LEN = 3
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN = 2
+ ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL =
+ 56 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL = 48
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN =
+ 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN =
+ 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL = 50
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_B_IP_RO_SIGNAL = 51
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL =
+ 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL
+ = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL
+ = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
+ 58 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL = 48
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN =
+ 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN
+ = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_RO_SIGNAL =
+ 48 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL =
+ 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN
+ = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_O_PL_B_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_O_PL_B_CONTROLS_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL3_O_PL_B_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL3_O_PL_B_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL3_O_PL_B_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL3_O_PL_B_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL6_O_PL_B_H1E_VAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL6_O_PL_B_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL6_O_PL_B_H1O_VAL = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL6_O_PL_B_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL7_O_PL_E_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL7_O_PL_E_CONTROLS_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL8_O_PL_E_OFFSET_E = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL8_O_PL_E_OFFSET_E_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL8_O_PL_E_OFFSET = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL8_O_PL_E_OFFSET_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_7 = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_CFG_LTE_MC = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_CFG_LTE_MC_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_FIR_MASK_PL_ERRS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_FIR_MASK_PL_ERRS_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_B = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_EDGE = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DDC_B = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_B = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_B = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_B = 62 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN = 2
+ ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_PR_RESET = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_IORESET = 63 ;
+
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL
+ = 50 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_SEL_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_BANK_SEL_A = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_MARGIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_BIST_PIPE_DATA_SHIFT = 57 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_A = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_B = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL_PSAVE_DIG_REQ_DIS = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL_PSAVE_ANA_REQ_DIS = 53 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_MODE2_EO_PL_PR_FW_OFF = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_EN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_MODE4_EO_PL_PR_INVALID_LOCK_COARSE_EN = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE_LEN = 3
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN = 2
+ ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL =
+ 56 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL = 48
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN =
+ 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN =
+ 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL = 50
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_B_IP_RO_SIGNAL = 51
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL =
+ 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL
+ = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL
+ = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
+ 58 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL = 48
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN =
+ 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN
+ = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_RO_SIGNAL =
+ 48 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL =
+ 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN
+ = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_O_PL_B_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_O_PL_B_CONTROLS_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL3_O_PL_B_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL3_O_PL_B_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL3_O_PL_B_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL3_O_PL_B_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL6_O_PL_B_H1E_VAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL6_O_PL_B_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL6_O_PL_B_H1O_VAL = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL6_O_PL_B_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL7_O_PL_E_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL7_O_PL_E_CONTROLS_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL8_O_PL_E_OFFSET_E = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL8_O_PL_E_OFFSET_E_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL8_O_PL_E_OFFSET = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL8_O_PL_E_OFFSET_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_7 = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_CFG_LTE_MC = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_CFG_LTE_MC_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_FIR_MASK_PL_ERRS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_FIR_MASK_PL_ERRS_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_B = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_EDGE = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DDC_B = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_B = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_B = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_B = 62 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN = 2
+ ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_PR_RESET = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_IORESET = 63 ;
+
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL
+ = 50 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_SEL_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_BANK_SEL_A = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_MARGIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_BIST_PIPE_DATA_SHIFT = 57 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_A = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_B = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL_PSAVE_DIG_REQ_DIS = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL_PSAVE_ANA_REQ_DIS = 53 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_MODE2_EO_PL_PR_FW_OFF = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_EN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_MODE4_EO_PL_PR_INVALID_LOCK_COARSE_EN = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE_LEN = 3
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN = 2
+ ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL =
+ 56 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL = 48
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN =
+ 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN =
+ 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL = 50
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_B_IP_RO_SIGNAL = 51
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL =
+ 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL
+ = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL
+ = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
+ 58 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL = 48
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN =
+ 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN
+ = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_RO_SIGNAL =
+ 48 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL =
+ 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN
+ = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_O_PL_B_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_O_PL_B_CONTROLS_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL3_O_PL_B_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL3_O_PL_B_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL3_O_PL_B_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL3_O_PL_B_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL6_O_PL_B_H1E_VAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL6_O_PL_B_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL6_O_PL_B_H1O_VAL = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL6_O_PL_B_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL7_O_PL_E_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL7_O_PL_E_CONTROLS_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL8_O_PL_E_OFFSET_E = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL8_O_PL_E_OFFSET_E_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL8_O_PL_E_OFFSET = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL8_O_PL_E_OFFSET_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_7 = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_CFG_LTE_MC = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_CFG_LTE_MC_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_FIR_MASK_PL_ERRS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_FIR_MASK_PL_ERRS_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_B = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_EDGE = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DDC_B = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_B = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_B = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_B = 62 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN = 2
+ ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_PR_RESET = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_IORESET = 63 ;
+
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL
+ = 50 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_SEL_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_BANK_SEL_A = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_MARGIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_BIST_PIPE_DATA_SHIFT = 57 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_A = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_B = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL_PSAVE_DIG_REQ_DIS = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL_PSAVE_ANA_REQ_DIS = 53 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_MODE2_EO_PL_PR_FW_OFF = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_EN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_MODE4_EO_PL_PR_INVALID_LOCK_COARSE_EN = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE_LEN = 3
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN = 2
+ ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL =
+ 56 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL = 48
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN =
+ 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN =
+ 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL = 50
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_B_IP_RO_SIGNAL = 51
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL =
+ 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL
+ = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL
+ = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
+ 58 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL = 48
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN =
+ 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN
+ = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_RO_SIGNAL =
+ 48 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL =
+ 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN
+ = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_O_PL_B_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_O_PL_B_CONTROLS_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL3_O_PL_B_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL3_O_PL_B_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL3_O_PL_B_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL3_O_PL_B_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL6_O_PL_B_H1E_VAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL6_O_PL_B_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL6_O_PL_B_H1O_VAL = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL6_O_PL_B_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL7_O_PL_E_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL7_O_PL_E_CONTROLS_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL8_O_PL_E_OFFSET_E = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL8_O_PL_E_OFFSET_E_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL8_O_PL_E_OFFSET = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL8_O_PL_E_OFFSET_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_7 = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_CFG_LTE_MC = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_CFG_LTE_MC_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_FIR_MASK_PL_ERRS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_FIR_MASK_PL_ERRS_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_B = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_EDGE = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DDC_B = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_B = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_B = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_B = 62 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN = 2
+ ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_PR_RESET = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_IORESET = 63 ;
+
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL
+ = 50 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_SEL_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_BANK_SEL_A = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_MARGIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_BIST_PIPE_DATA_SHIFT = 57 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_A = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_B = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL_PSAVE_DIG_REQ_DIS = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL_PSAVE_ANA_REQ_DIS = 53 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_MODE2_EO_PL_PR_FW_OFF = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_EN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_MODE4_EO_PL_PR_INVALID_LOCK_COARSE_EN = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE_LEN = 3
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN = 2
+ ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL =
+ 56 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL = 48
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN =
+ 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN =
+ 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL = 50
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_B_IP_RO_SIGNAL = 51
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL =
+ 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL
+ = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL
+ = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
+ 58 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL = 48
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN =
+ 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN
+ = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_RO_SIGNAL =
+ 48 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL =
+ 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN
+ = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_O_PL_B_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_O_PL_B_CONTROLS_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL3_O_PL_B_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL3_O_PL_B_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL3_O_PL_B_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL3_O_PL_B_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL6_O_PL_B_H1E_VAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL6_O_PL_B_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL6_O_PL_B_H1O_VAL = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL6_O_PL_B_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL7_O_PL_E_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL7_O_PL_E_CONTROLS_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL8_O_PL_E_OFFSET_E = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL8_O_PL_E_OFFSET_E_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL8_O_PL_E_OFFSET = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL8_O_PL_E_OFFSET_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_7 = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_CFG_LTE_MC = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_CFG_LTE_MC_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_FIR_MASK_PL_ERRS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_FIR_MASK_PL_ERRS_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_B = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_EDGE = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DDC_B = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_B = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_B = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_B = 62 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN = 2
+ ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_PR_RESET = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_IORESET = 63 ;
+
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL
+ = 50 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_SEL_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_BANK_SEL_A = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_MARGIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_BIST_PIPE_DATA_SHIFT = 57 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_A = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_B = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL_PSAVE_DIG_REQ_DIS = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL_PSAVE_ANA_REQ_DIS = 53 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_MODE2_EO_PL_PR_FW_OFF = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_EN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_MODE4_EO_PL_PR_INVALID_LOCK_COARSE_EN = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE_LEN = 3
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN = 2
+ ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL =
+ 56 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL = 48
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN =
+ 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN =
+ 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL = 50
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_B_IP_RO_SIGNAL = 51
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL =
+ 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL
+ = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL
+ = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
+ 58 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL = 48
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN =
+ 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN
+ = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_RO_SIGNAL =
+ 48 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL =
+ 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN
+ = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_O_PL_B_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_O_PL_B_CONTROLS_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL3_O_PL_B_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL3_O_PL_B_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL3_O_PL_B_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL3_O_PL_B_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL6_O_PL_B_H1E_VAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL6_O_PL_B_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL6_O_PL_B_H1O_VAL = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL6_O_PL_B_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL7_O_PL_E_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL7_O_PL_E_CONTROLS_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL8_O_PL_E_OFFSET_E = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL8_O_PL_E_OFFSET_E_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL8_O_PL_E_OFFSET = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL8_O_PL_E_OFFSET_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_7 = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_CFG_LTE_MC = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_CFG_LTE_MC_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_FIR_MASK_PL_ERRS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_FIR_MASK_PL_ERRS_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_B = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_EDGE = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DDC_B = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_B = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_B = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_B = 62 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN = 2
+ ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_PR_RESET = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_IORESET = 63 ;
+
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL
+ = 50 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_SEL_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_BANK_SEL_A = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_MARGIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_BIST_PIPE_DATA_SHIFT = 57 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_A = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_B = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL_PSAVE_DIG_REQ_DIS = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL_PSAVE_ANA_REQ_DIS = 53 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_MODE2_EO_PL_PR_FW_OFF = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_EN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_MODE4_EO_PL_PR_INVALID_LOCK_COARSE_EN = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE_LEN = 3
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN = 2
+ ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL =
+ 56 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL = 48
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN =
+ 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN =
+ 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL = 50
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_B_IP_RO_SIGNAL = 51
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL =
+ 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL
+ = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL
+ = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
+ 58 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL = 48
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN =
+ 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN
+ = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_RO_SIGNAL =
+ 48 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL =
+ 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN
+ = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_O_PL_B_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_O_PL_B_CONTROLS_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL3_O_PL_B_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL3_O_PL_B_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL3_O_PL_B_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL3_O_PL_B_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL6_O_PL_B_H1E_VAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL6_O_PL_B_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL6_O_PL_B_H1O_VAL = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL6_O_PL_B_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL7_O_PL_E_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL7_O_PL_E_CONTROLS_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL8_O_PL_E_OFFSET_E = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL8_O_PL_E_OFFSET_E_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL8_O_PL_E_OFFSET = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL8_O_PL_E_OFFSET_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_7 = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_CFG_LTE_MC = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_CFG_LTE_MC_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_FIR_MASK_PL_ERRS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_FIR_MASK_PL_ERRS_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_B = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_EDGE = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DDC_B = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_B = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_B = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_B = 62 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN = 2
+ ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_PR_RESET = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_IORESET = 63 ;
+
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL
+ = 50 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_SEL_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_BANK_SEL_A = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_MARGIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_BIST_PIPE_DATA_SHIFT = 57 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_A = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_B = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL_PSAVE_DIG_REQ_DIS = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL_PSAVE_ANA_REQ_DIS = 53 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_MODE2_EO_PL_PR_FW_OFF = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_EN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_MODE4_EO_PL_PR_INVALID_LOCK_COARSE_EN = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE_LEN = 3
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN = 2
+ ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL =
+ 56 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL = 48
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN =
+ 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN =
+ 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL = 50
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_B_IP_RO_SIGNAL = 51
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL =
+ 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL
+ = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL
+ = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
+ 58 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL = 48
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN =
+ 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN
+ = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_RO_SIGNAL =
+ 48 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL =
+ 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN
+ = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_O_PL_B_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_O_PL_B_CONTROLS_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL3_O_PL_B_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL3_O_PL_B_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL3_O_PL_B_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL3_O_PL_B_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL6_O_PL_B_H1E_VAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL6_O_PL_B_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL6_O_PL_B_H1O_VAL = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL6_O_PL_B_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL7_O_PL_E_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL7_O_PL_E_CONTROLS_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL8_O_PL_E_OFFSET_E = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL8_O_PL_E_OFFSET_E_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL8_O_PL_E_OFFSET = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL8_O_PL_E_OFFSET_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_7 = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_CFG_LTE_MC = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_CFG_LTE_MC_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_FIR_MASK_PL_ERRS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_FIR_MASK_PL_ERRS_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_B = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_EDGE = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DDC_B = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_B = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_B = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_B = 62 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN = 2
+ ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_PR_RESET = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_IORESET = 63 ;
+
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL
+ = 50 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_SEL_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_BANK_SEL_A = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_MARGIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_BIST_PIPE_DATA_SHIFT = 57 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_A = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_B = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL_PSAVE_DIG_REQ_DIS = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL_PSAVE_ANA_REQ_DIS = 53 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_MODE2_EO_PL_PR_FW_OFF = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_EN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_MODE4_EO_PL_PR_INVALID_LOCK_COARSE_EN = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE_LEN = 3
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN = 2
+ ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL =
+ 56 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL = 48
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN =
+ 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN =
+ 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL = 50
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_B_IP_RO_SIGNAL = 51
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL =
+ 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL
+ = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL
+ = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
+ 58 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL = 48
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN =
+ 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN
+ = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_RO_SIGNAL =
+ 48 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL =
+ 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN
+ = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_O_PL_B_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_O_PL_B_CONTROLS_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL3_O_PL_B_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL3_O_PL_B_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL3_O_PL_B_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL3_O_PL_B_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL6_O_PL_B_H1E_VAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL6_O_PL_B_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL6_O_PL_B_H1O_VAL = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL6_O_PL_B_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL7_O_PL_E_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL7_O_PL_E_CONTROLS_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL8_O_PL_E_OFFSET_E = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL8_O_PL_E_OFFSET_E_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL8_O_PL_E_OFFSET = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL8_O_PL_E_OFFSET_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_7 = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_CFG_LTE_MC = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_CFG_LTE_MC_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_FIR_MASK_PL_ERRS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_FIR_MASK_PL_ERRS_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_B = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_EDGE = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DDC_B = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_B = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_B = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_B = 62 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN = 2
+ ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL4_EO_PL_PR_RESET = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL4_EO_PL_IORESET = 63 ;
+
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL
+ = 50 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_SEL_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_CNTLX1_EO_PL_BANK_SEL_A = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_MARGIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_CNTLX1_EO_PL_BIST_PIPE_DATA_SHIFT = 57 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_A = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_B = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_MODE1_EO_PL_PSAVE_DIG_REQ_DIS = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_MODE1_EO_PL_PSAVE_ANA_REQ_DIS = 53 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_MODE2_EO_PL_PR_FW_OFF = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_EN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_MODE4_EO_PL_PR_INVALID_LOCK_COARSE_EN = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE_LEN = 3
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN = 2
+ ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL =
+ 56 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL = 48
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN =
+ 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN =
+ 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL = 50
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_B_IP_RO_SIGNAL = 51
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL =
+ 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL
+ = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL
+ = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
+ 58 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL = 48
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN =
+ 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN
+ = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_RO_SIGNAL =
+ 48 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL =
+ 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN
+ = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL1_O_PL_B_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL1_O_PL_B_CONTROLS_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL3_O_PL_B_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL3_O_PL_B_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL3_O_PL_B_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL3_O_PL_B_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL6_O_PL_B_H1E_VAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL6_O_PL_B_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL6_O_PL_B_H1O_VAL = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL6_O_PL_B_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL7_O_PL_E_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL7_O_PL_E_CONTROLS_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL8_O_PL_E_OFFSET_E = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL8_O_PL_E_OFFSET_E_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL8_O_PL_E_OFFSET = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL8_O_PL_E_OFFSET_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_7 = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_CFG_LTE_MC = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_CFG_LTE_MC_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_FIR_MASK_PL_ERRS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_FIR_MASK_PL_ERRS_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE0_RX_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_B = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_EDGE = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DDC_B = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_B = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_B = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_B = 62 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN = 2
+ ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL4_EO_PL_PR_RESET = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL4_EO_PL_IORESET = 63 ;
+
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL
+ = 50 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_SEL_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_CNTLX1_EO_PL_BANK_SEL_A = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_MARGIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_CNTLX1_EO_PL_BIST_PIPE_DATA_SHIFT = 57 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_A = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_B = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_MODE1_EO_PL_PSAVE_DIG_REQ_DIS = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_MODE1_EO_PL_PSAVE_ANA_REQ_DIS = 53 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_MODE2_EO_PL_PR_FW_OFF = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_EN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_MODE4_EO_PL_PR_INVALID_LOCK_COARSE_EN = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE_LEN = 3
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN = 2
+ ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL =
+ 56 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL = 48
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN =
+ 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN =
+ 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL = 50
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_B_IP_RO_SIGNAL = 51
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL =
+ 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL
+ = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL
+ = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
+ 58 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL = 48
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN =
+ 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN
+ = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_RO_SIGNAL =
+ 48 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL =
+ 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN
+ = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL1_O_PL_B_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL1_O_PL_B_CONTROLS_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL3_O_PL_B_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL3_O_PL_B_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL3_O_PL_B_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL3_O_PL_B_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL6_O_PL_B_H1E_VAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL6_O_PL_B_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL6_O_PL_B_H1O_VAL = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL6_O_PL_B_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL7_O_PL_E_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL7_O_PL_E_CONTROLS_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL8_O_PL_E_OFFSET_E = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL8_O_PL_E_OFFSET_E_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL8_O_PL_E_OFFSET = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL8_O_PL_E_OFFSET_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_7 = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_CFG_LTE_MC = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_CFG_LTE_MC_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_FIR_MASK_PL_ERRS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_FIR_MASK_PL_ERRS_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE1_RX_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_B = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_EDGE = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DDC_B = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_B = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_B = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_B = 62 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN = 2
+ ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL4_EO_PL_PR_RESET = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL4_EO_PL_IORESET = 63 ;
+
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL
+ = 50 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_SEL_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_CNTLX1_EO_PL_BANK_SEL_A = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_MARGIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_CNTLX1_EO_PL_BIST_PIPE_DATA_SHIFT = 57 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_A = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_B = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_MODE1_EO_PL_PSAVE_DIG_REQ_DIS = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_MODE1_EO_PL_PSAVE_ANA_REQ_DIS = 53 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_MODE2_EO_PL_PR_FW_OFF = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_EN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_MODE4_EO_PL_PR_INVALID_LOCK_COARSE_EN = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE_LEN = 3
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN = 2
+ ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL =
+ 56 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL = 48
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN =
+ 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN =
+ 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL = 50
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_B_IP_RO_SIGNAL = 51
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL =
+ 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL
+ = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL
+ = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
+ 58 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL = 48
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN =
+ 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN
+ = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_RO_SIGNAL =
+ 48 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL =
+ 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN
+ = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL1_O_PL_B_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL1_O_PL_B_CONTROLS_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL3_O_PL_B_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL3_O_PL_B_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL3_O_PL_B_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL3_O_PL_B_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL6_O_PL_B_H1E_VAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL6_O_PL_B_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL6_O_PL_B_H1O_VAL = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL6_O_PL_B_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL7_O_PL_E_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL7_O_PL_E_CONTROLS_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL8_O_PL_E_OFFSET_E = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL8_O_PL_E_OFFSET_E_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL8_O_PL_E_OFFSET = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL8_O_PL_E_OFFSET_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_7 = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_CFG_LTE_MC = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_CFG_LTE_MC_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_FIR_MASK_PL_ERRS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_FIR_MASK_PL_ERRS_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE2_RX_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_B = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_EDGE = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DDC_B = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_B = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_B = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_B = 62 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN = 2
+ ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL4_EO_PL_PR_RESET = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL4_EO_PL_IORESET = 63 ;
+
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL
+ = 50 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_SEL_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_CNTLX1_EO_PL_BANK_SEL_A = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_MARGIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_CNTLX1_EO_PL_BIST_PIPE_DATA_SHIFT = 57 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_A = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_B = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_MODE1_EO_PL_PSAVE_DIG_REQ_DIS = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_MODE1_EO_PL_PSAVE_ANA_REQ_DIS = 53 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_MODE2_EO_PL_PR_FW_OFF = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_EN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_MODE4_EO_PL_PR_INVALID_LOCK_COARSE_EN = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE_LEN = 3
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN = 2
+ ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL =
+ 56 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL = 48
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN =
+ 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN =
+ 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL = 50
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_B_IP_RO_SIGNAL = 51
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL =
+ 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL
+ = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL
+ = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
+ 58 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL = 48
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN =
+ 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN
+ = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_RO_SIGNAL =
+ 48 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL =
+ 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN
+ = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL1_O_PL_B_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL1_O_PL_B_CONTROLS_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL3_O_PL_B_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL3_O_PL_B_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL3_O_PL_B_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL3_O_PL_B_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL6_O_PL_B_H1E_VAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL6_O_PL_B_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL6_O_PL_B_H1O_VAL = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL6_O_PL_B_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL7_O_PL_E_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL7_O_PL_E_CONTROLS_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL8_O_PL_E_OFFSET_E = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL8_O_PL_E_OFFSET_E_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL8_O_PL_E_OFFSET = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL8_O_PL_E_OFFSET_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_7 = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_CFG_LTE_MC = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_CFG_LTE_MC_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_FIR_MASK_PL_ERRS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_FIR_MASK_PL_ERRS_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS4_SLICE3_RX_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_B = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_EDGE = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DDC_B = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_B = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_B = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_B = 62 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN = 2
+ ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL4_EO_PL_PR_RESET = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL4_EO_PL_IORESET = 63 ;
+
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL
+ = 50 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_SEL_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_CNTLX1_EO_PL_BANK_SEL_A = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_MARGIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_CNTLX1_EO_PL_BIST_PIPE_DATA_SHIFT = 57 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_A = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_B = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_MODE1_EO_PL_PSAVE_DIG_REQ_DIS = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_MODE1_EO_PL_PSAVE_ANA_REQ_DIS = 53 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_MODE2_EO_PL_PR_FW_OFF = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_EN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_MODE4_EO_PL_PR_INVALID_LOCK_COARSE_EN = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE_LEN = 3
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN = 2
+ ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL =
+ 56 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL = 48
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN =
+ 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN =
+ 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL = 50
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_B_IP_RO_SIGNAL = 51
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL =
+ 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL
+ = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL
+ = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
+ 58 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL = 48
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN =
+ 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN
+ = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_RO_SIGNAL =
+ 48 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL =
+ 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN
+ = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL1_O_PL_B_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL1_O_PL_B_CONTROLS_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL3_O_PL_B_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL3_O_PL_B_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL3_O_PL_B_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL3_O_PL_B_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL6_O_PL_B_H1E_VAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL6_O_PL_B_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL6_O_PL_B_H1O_VAL = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL6_O_PL_B_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL7_O_PL_E_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL7_O_PL_E_CONTROLS_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL8_O_PL_E_OFFSET_E = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL8_O_PL_E_OFFSET_E_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL8_O_PL_E_OFFSET = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL8_O_PL_E_OFFSET_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_7 = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_CFG_LTE_MC = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_CFG_LTE_MC_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_FIR_MASK_PL_ERRS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_FIR_MASK_PL_ERRS_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE0_RX_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_B = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_EDGE = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DDC_B = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_B = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_B = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_B = 62 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN = 2
+ ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL4_EO_PL_PR_RESET = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL4_EO_PL_IORESET = 63 ;
+
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL
+ = 50 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_SEL_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_CNTLX1_EO_PL_BANK_SEL_A = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_MARGIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_CNTLX1_EO_PL_BIST_PIPE_DATA_SHIFT = 57 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_A = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_B = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_MODE1_EO_PL_PSAVE_DIG_REQ_DIS = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_MODE1_EO_PL_PSAVE_ANA_REQ_DIS = 53 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_MODE2_EO_PL_PR_FW_OFF = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_EN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_MODE4_EO_PL_PR_INVALID_LOCK_COARSE_EN = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE_LEN = 3
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN = 2
+ ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL =
+ 56 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL = 48
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN =
+ 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN =
+ 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL = 50
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_B_IP_RO_SIGNAL = 51
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL =
+ 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL
+ = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL
+ = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
+ 58 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL = 48
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN =
+ 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN
+ = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_RO_SIGNAL =
+ 48 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL =
+ 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN
+ = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL1_O_PL_B_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL1_O_PL_B_CONTROLS_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL3_O_PL_B_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL3_O_PL_B_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL3_O_PL_B_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL3_O_PL_B_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL6_O_PL_B_H1E_VAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL6_O_PL_B_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL6_O_PL_B_H1O_VAL = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL6_O_PL_B_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL7_O_PL_E_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL7_O_PL_E_CONTROLS_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL8_O_PL_E_OFFSET_E = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL8_O_PL_E_OFFSET_E_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL8_O_PL_E_OFFSET = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL8_O_PL_E_OFFSET_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_7 = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_CFG_LTE_MC = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_CFG_LTE_MC_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_FIR_MASK_PL_ERRS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_FIR_MASK_PL_ERRS_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE1_RX_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_B = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_EDGE = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DDC_B = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_B = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_B = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_B = 62 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN = 2
+ ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL4_EO_PL_PR_RESET = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL4_EO_PL_IORESET = 63 ;
+
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL
+ = 50 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_SEL_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_CNTLX1_EO_PL_BANK_SEL_A = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_MARGIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_CNTLX1_EO_PL_BIST_PIPE_DATA_SHIFT = 57 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_A = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_B = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_MODE1_EO_PL_PSAVE_DIG_REQ_DIS = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_MODE1_EO_PL_PSAVE_ANA_REQ_DIS = 53 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_MODE2_EO_PL_PR_FW_OFF = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_EN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_MODE4_EO_PL_PR_INVALID_LOCK_COARSE_EN = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE_LEN = 3
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN = 2
+ ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL =
+ 56 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL = 48
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN =
+ 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN =
+ 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL = 50
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_B_IP_RO_SIGNAL = 51
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL =
+ 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL
+ = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL
+ = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
+ 58 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL = 48
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN =
+ 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN
+ = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_RO_SIGNAL =
+ 48 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL =
+ 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN
+ = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL1_O_PL_B_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL1_O_PL_B_CONTROLS_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL3_O_PL_B_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL3_O_PL_B_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL3_O_PL_B_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL3_O_PL_B_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL6_O_PL_B_H1E_VAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL6_O_PL_B_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL6_O_PL_B_H1O_VAL = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL6_O_PL_B_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL7_O_PL_E_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL7_O_PL_E_CONTROLS_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL8_O_PL_E_OFFSET_E = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL8_O_PL_E_OFFSET_E_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL8_O_PL_E_OFFSET = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL8_O_PL_E_OFFSET_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_7 = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_CFG_LTE_MC = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_CFG_LTE_MC_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_FIR_MASK_PL_ERRS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_FIR_MASK_PL_ERRS_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE2_RX_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_B = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_EDGE = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DDC_B = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_B = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_B = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_B = 62 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN = 2
+ ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL4_EO_PL_PR_RESET = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL4_EO_PL_IORESET = 63 ;
+
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL
+ = 50 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_SEL_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_CNTLX1_EO_PL_BANK_SEL_A = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_MARGIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_CNTLX1_EO_PL_BIST_PIPE_DATA_SHIFT = 57 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_A = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_B = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_MODE1_EO_PL_PSAVE_DIG_REQ_DIS = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_MODE1_EO_PL_PSAVE_ANA_REQ_DIS = 53 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_MODE2_EO_PL_PR_FW_OFF = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_EN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_MODE4_EO_PL_PR_INVALID_LOCK_COARSE_EN = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE_LEN = 3
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN = 2
+ ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL =
+ 56 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL = 48
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN =
+ 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN =
+ 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL = 50
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_B_IP_RO_SIGNAL = 51
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL =
+ 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL
+ = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL
+ = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
+ 58 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL = 48
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN =
+ 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN
+ = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_RO_SIGNAL =
+ 48 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL =
+ 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN
+ = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL1_O_PL_B_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL1_O_PL_B_CONTROLS_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL3_O_PL_B_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL3_O_PL_B_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL3_O_PL_B_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL3_O_PL_B_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL6_O_PL_B_H1E_VAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL6_O_PL_B_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL6_O_PL_B_H1O_VAL = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL6_O_PL_B_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL7_O_PL_E_CONTROLS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL7_O_PL_E_CONTROLS_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL8_O_PL_E_OFFSET_E = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL8_O_PL_E_OFFSET_E_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL8_O_PL_E_OFFSET = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL8_O_PL_E_OFFSET_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_7 = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_CFG_LTE_MC = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_CFG_LTE_MC_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_FIR_MASK_PL_ERRS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_FIR_MASK_PL_ERRS_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS5_SLICE3_RX_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL10_EO_PG_BIST_PRBS_TEST_TIME = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL10_EO_PG_BIST_PRBS_TEST_TIME_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL10_EO_PG_BIST_BUS_DATA_MODE = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL10_EO_PG_BIST_PRBS_PROP_TIME = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL10_EO_PG_BIST_PRBS_PROP_TIME_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL11_EO_PG_DACTEST_LLMT = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL11_EO_PG_DACTEST_LLMT_LEN = 9 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL11_EO_PG_DACTEST_RESET = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL11_EO_PG_DACTEST_START = 58 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL12_EO_PG_DACTEST_HLMT = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL12_EO_PG_DACTEST_HLMT_LEN = 9 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL13_EO_PG_HIST_MIN_EYE_WIDTH_VALID = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL13_EO_PG_HIST_MIN_EYE_WIDTH_LANE = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL13_EO_PG_HIST_MIN_EYE_WIDTH_LANE_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL13_EO_PG_HIST_MIN_EYE_WIDTH = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL13_EO_PG_HIST_MIN_EYE_WIDTH_LEN = 8 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL14_EO_PG_HIST_MIN_EYE_HEIGHT_VALID = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL14_EO_PG_HIST_MIN_EYE_HEIGHT_LANE = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL14_EO_PG_HIST_MIN_EYE_HEIGHT_LANE_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL14_EO_PG_HIST_MIN_EYE_HEIGHT = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL14_EO_PG_HIST_MIN_EYE_HEIGHT_LEN = 8 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL1_EO_PG_BER_EN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL1_EO_PG_BER_TIMER_FREEZE_EN = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL1_EO_PG_BER_COUNT_FREEZE_EN = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL1_EO_PG_BER_COUNT_SEL = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL1_EO_PG_BER_COUNT_SEL_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL1_EO_PG_BER_TIMER_SEL = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL1_EO_PG_BER_TIMER_SEL_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL1_EO_PG_BER_CLR_COUNT_ON_READ_EN = 59 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL1_EO_PG_BER_CLR_TIMER_ON_READ_EN = 60 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL2_EO_PG_TRC_MODE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL2_EO_PG_TRC_MODE_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL3_EO_PG_INT_MODE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL3_EO_PG_INT_MODE_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL3_EO_PG_INT_CURRENT_STATE = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL3_EO_PG_INT_CURRENT_STATE_LEN = 12 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL4_EO_PG_INT_ENABLE_ENC = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL4_EO_PG_INT_ENABLE_ENC_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL4_EO_PG_INT_NEXT_STATE = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL4_EO_PG_INT_NEXT_STATE_LEN = 12 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL5_EO_PG_INT_GOTO_STATE = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL5_EO_PG_INT_GOTO_STATE_LEN = 12 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL6_EO_PG_INT_RETURN_STATE = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL6_EO_PG_INT_RETURN_STATE_LEN = 12 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL8_EO_PG_SERVO_OP = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL8_EO_PG_SERVO_OP_LEN = 15 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL8_EO_PG_SERVO_DONE = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL9_EO_PG_BIST_EN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL9_EO_PG_BIST_EXT_START_MODE = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL9_EO_PG_BIST_INIT_DISABLE = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL9_EO_PG_BIST_INIT_DISABLE_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL9_EO_PG_BIST_CUPLL_LOCK_CHECK_EN = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL9_EO_PG_BIST_STORE_EYES_LANE_SEL = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL9_EO_PG_BIST_STORE_EYES_LANE_SEL_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL9_EO_PG_BIST_STORE_EYES_BANK_SEL = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL9_EO_PG_BIST_STORE_EYES_BANK_SEL_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL9_EO_PG_PERVASIVE_CAPT = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTL9_EO_PG_BIST_LL_TEST_EN = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTLX7_EO_PG_CAL_LANE_PHY_GCRMSG = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_CNTLX7_EO_PG_CAL_LANE_PHY_GCRMSG_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE10_EO_PG_AMP_INIT_CFG = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE10_EO_PG_AMP_INIT_CFG_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE10_EO_PG_AMP_RECAL_CFG = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE10_EO_PG_AMP_RECAL_CFG_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE10_EO_PG_PEAK_INIT_CFG = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE10_EO_PG_PEAK_INIT_CFG_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE10_EO_PG_PEAK_RECAL_CFG = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE10_EO_PG_PEAK_RECAL_CFG_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE10_EO_PG_AMP_CFG = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE10_EO_PG_AMP_CFG_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE11_EO_PG_OFF_INIT_CFG = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE11_EO_PG_OFF_INIT_CFG_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE11_EO_PG_OFF_RECAL_CFG = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE11_EO_PG_OFF_RECAL_CFG_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE11_EO_PG_CM_CFG = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE11_EO_PG_CM_CFG_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE11_EO_PG_AMIN_CFG = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE11_EO_PG_AMIN_CFG_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE11_EO_PG_USERDEF_CFG = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE11_EO_PG_USERDEF_CFG_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE12_EO_PG_SERVO_CHG_CFG = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE12_EO_PG_SERVO_CHG_CFG_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE12_EO_PG_DAC_BO_CFG = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE12_EO_PG_DAC_BO_CFG_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE12_EO_PG_FILTER_MODE = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE12_EO_PG_FILTER_MODE_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE12_EO_PG_MISC_CFG = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE12_EO_PG_MISC_CFG_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE12_EO_PG_DISABLE_H1_CLEAR = 59 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE12_EO_PG_VOFF_CFG = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE12_EO_PG_VOFF_CFG_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE12_EO_PG_LOFF_AMP_EN = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE13_EO_PG_CM_OFFSET_VAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE13_EO_PG_CM_OFFSET_VAL_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE13_EO_PG_SERVO_THRESH1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE13_EO_PG_SERVO_THRESH1_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE13_EO_PG_SERVO_THRESH2 = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE13_EO_PG_SERVO_THRESH2_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE14_EO_PG_AMP_INIT_TIMEOUT = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE14_EO_PG_AMP_INIT_TIMEOUT_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE14_EO_PG_AMP_RECAL_TIMEOUT = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE14_EO_PG_AMP_RECAL_TIMEOUT_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE14_EO_PG_PEAK_INIT_TIMEOUT = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE14_EO_PG_PEAK_INIT_TIMEOUT_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE14_EO_PG_PEAK_RECAL_TIMEOUT = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE14_EO_PG_PEAK_RECAL_TIMEOUT_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE15_EO_PG_OFF_INIT_TIMEOUT = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE15_EO_PG_OFF_INIT_TIMEOUT_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE15_EO_PG_OFF_RECAL_TIMEOUT = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE15_EO_PG_OFF_RECAL_TIMEOUT_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE15_EO_PG_CM_TIMEOUT = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE15_EO_PG_CM_TIMEOUT_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE15_EO_PG_AMIN_TIMEOUT = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE15_EO_PG_AMIN_TIMEOUT_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE16_EO_PG_AMP_TIMEOUT = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE16_EO_PG_AMP_TIMEOUT_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE16_EO_PG_USERDEF_TIMEOUT = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE16_EO_PG_USERDEF_TIMEOUT_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE16_EO_PG_BER_TIMEOUT = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE16_EO_PG_BER_TIMEOUT_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE16_EO_PG_SPARE4_TIMEOUT = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE16_EO_PG_SPARE4_TIMEOUT_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE17_EO_PG_AMAX_HIGH = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE17_EO_PG_AMAX_HIGH_LEN = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE17_EO_PG_AMAX_LOW = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE17_EO_PG_AMAX_LOW_LEN = 8 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE18_EO_PG_AMP0_FILTER_MASK = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE18_EO_PG_AMP0_FILTER_MASK_LEN = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE18_EO_PG_AMP1_FILTER_MASK = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE18_EO_PG_AMP1_FILTER_MASK_LEN = 8 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE19_EO_PG_CTLE_GAIN_MAX = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE19_EO_PG_CTLE_GAIN_MAX_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE19_EO_PG_AMP_START_VAL = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE19_EO_PG_AMP_START_VAL_LEN = 8 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE1_EO_PG_CLKDIST_PDWN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE1_EO_PG_CLKDIST_PDWN_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE1_EO_PG_BIST_MIN_EYE_WIDTH = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE1_EO_PG_BIST_MIN_EYE_WIDTH_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE1_EO_PG_A_BIST_EN = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE1_EO_PG_B_BIST_EN = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE1_EO_PG_E_BIST_EN = 59 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE1_EO_PG_BISTCLK_EN = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE1_EO_PG_BISTCLK_EN_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE1_EO_PG_DISABLE_BANK_PDWN = 62 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE1_O_PG_MINIKERF = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE1_O_PG_MINIKERF_LEN = 16 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE20_EO_PG_DFE_CONVERGED_CNT_MAX = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE20_EO_PG_DFE_CONVERGED_CNT_MAX_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE20_EO_PG_AP110_AP010_DELTA_MAX = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE20_EO_PG_AP110_AP010_DELTA_MAX_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE21_EO_PG_ENABLE_INTEG_LATCH_OFFSET_CAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE21_EO_PG_ENABLE_CTLE_COARSE_CAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE21_EO_PG_ENABLE_DAC_H1_CAL = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE21_EO_PG_ENABLE_VGA_CAL = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE21_EO_PG_ENABLE_DFE_H1_CAL = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE21_EO_PG_ENABLE_H1AP_TWEAK = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE21_EO_PG_ENABLE_DDC = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE21_EO_PG_ENABLE_CM_COARSE_CAL = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE21_EO_PG_ENABLE_CM_FINE_CAL = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE21_EO_PG_ENABLE_VGA_EDGE_OFFSET_CAL = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE21_EO_PG_ENABLE_CTLE_EDGE_OFFSET_CAL = 58 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_INTEG_LATCH_OFFSET_CAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_CTLE_COARSE_CAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_DAC_H1_CAL = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_VGA_CAL = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_DFE_H1_CAL = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_H1AP_TWEAK = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_DDC = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_CM_COARSE_CAL = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_CM_FINE_CAL = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_VGA_EDGE_OFFSET_CAL = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_CTLE_EDGE_OFFSET_CAL = 58 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE23_EO_PG_IREF_RES_DAC = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE23_EO_PG_IREF_RES_DAC_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE23_EO_PG_IREF_BYPASS = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE23_EO_PG_IREF_PDWN_B = 54 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE24_EO_PG_H1AP_CFG = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE24_EO_PG_H1AP_CFG_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE24_EO_PG_CTLE_UPDATE_MODE = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE24_EO_PG_USER_FILTER_MASK = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE24_EO_PG_USER_FILTER_MASK_LEN = 8 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE26_EO_PG_ENABLE_CTLE_1ST_LATCH_OFFSET_CAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE26_EO_PG_ENABLE_CTLE_2ND_LATCH_OFFSET_CAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE26_EO_PG_ENABLE_VGA_AMAX_MODE = 50 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE27_EO_PG_RC_ENABLE_CTLE_1ST_LATCH_OFFSET_CAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE27_EO_PG_RC_ENABLE_CTLE_2ND_LATCH_OFFSET_CAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE27_EO_PG_RC_ENABLE_VGA_AMAX_MODE = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE27_EO_PG_RC_ENABLE_AUTO_RECAL = 51 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE28_EO_PG_DC_ENABLE_CM_COARSE_CAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE28_EO_PG_DC_ENABLE_CM_FINE_CAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE28_EO_PG_DC_ENABLE_CTLE_1ST_LATCH_OFFSET_CAL = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE28_EO_PG_DC_ENABLE_CTLE_2ND_LATCH_OFFSET_CAL = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE28_EO_PG_DC_ENABLE_INTEG_LATCH_OFFSET_CAL = 52 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE29_EO_PG_APX111_HIGH = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE29_EO_PG_APX111_HIGH_LEN = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE29_EO_PG_APX111_LOW = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE29_EO_PG_APX111_LOW_LEN = 8 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE2_EO_PG_DFE_CA_CFG = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE2_EO_PG_DFE_CA_CFG_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE2_EO_PG_SCOPE_CONTROL = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE2_EO_PG_SCOPE_CONTROL_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE2_EO_PG_RECAL_REQ_DL_MASK = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE2_EO_PG_RECAL_DONE_DL_MASK = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE2_EO_PG_RUN_LANE_DL_MASK = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE2_EO_PG_RECAL_ABORT_DL_MASK = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE2_EO_PG_INIT_DONE_DL_MASK = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE2_EO_PG_DATA_PIPE_CLR_ON_READ_MODE = 59 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE2_O_PG_OCTANT_SELECT = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE2_O_PG_OCTANT_SELECT_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE2_O_PG_SPEED_SELECT = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE2_O_PG_SPEED_SELECT_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE2_O_PG_AC_COUPLED = 53 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE5_EO_PG_TRACKING_TIMEOUT_SEL = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE5_EO_PG_TRACKING_TIMEOUT_SEL_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE6_EO_PG_CONVERGED_END_COUNT = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE6_EO_PG_CONVERGED_END_COUNT_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE6_EO_PG_HIST_MIN_EYE_WIDTH_MODE = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE6_EO_PG_HIST_MIN_EYE_WIDTH_MODE_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE6_EO_PG_HIST_MIN_EYE_HEIGHT_MODE = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE6_EO_PG_HIST_MIN_EYE_HEIGHT_MODE_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE6_EO_PG_AMP_GAIN_CNT_MAX = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE6_EO_PG_AMP_GAIN_CNT_MAX_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE7_EO_PG_ABORT_CHECK_TIMEOUT_SEL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE7_EO_PG_ABORT_CHECK_TIMEOUT_SEL_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE7_EO_PG_POLLING_TIMEOUT_SEL = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE7_EO_PG_POLLING_TIMEOUT_SEL_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE9_EO_PG_MIN_EYE_WIDTH = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE9_EO_PG_MIN_EYE_WIDTH_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE9_EO_PG_MIN_EYE_HEIGHT = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_MODE9_EO_PG_MIN_EYE_HEIGHT_LEN = 8 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_STAT1_EO_PG_SERVO_RESULT = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_STAT1_EO_PG_SERVO_RESULT_LEN = 8 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_STAT2_EO_PG_BIST_INIT_DONE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_STAT2_EO_PG_BIST_DONE = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_STAT2_EO_PG_BIST_LL_ERR = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_STAT2_EO_PG_BIST_NO_EDGE_DET = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_STAT2_EO_PG_BIST_EYE_A_WIDTH = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_STAT2_EO_PG_BIST_EYE_A_WIDTH_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_STAT2_EO_PG_BIST_EYE_B_WIDTH = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_CTL_STAT2_EO_PG_BIST_EYE_B_WIDTH_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_DATASM_CNTLX1_EO_PG_RX_BER_COUNT_CLR_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_DATASM_CNTLX1_EO_PG_RX_BER_TIMER_CLR_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_DATASM_CNTLX1_EO_PG_RX_SCOPE_CAPTURE_WO_PULSE_SLOW_SIGNAL = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_DATASM_CNTLX1_EO_PG_RX_DATA_PIPE_CAPTURE_WO_PULSE_SLOW_SIGNAL =
+ 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_DATASM_CNTLX1_EO_PG_RX_RESET_SERVO_STATUS_WO_PULSE_SLOW_SIGNAL =
+ 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_DATASM_CNTLX1_EO_PG_RX_BER_RESET_WO_PULSE_SLOW_SIGNAL = 54 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_DATASM_SPARE_MODE_PG_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_DATASM_SPARE_MODE_PG_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_DATASM_SPARE_MODE_PG_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_DATASM_SPARE_MODE_PG_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_DATASM_SPARE_MODE_PG_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_DATASM_SPARE_MODE_PG_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_DATASM_SPARE_MODE_PG_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_DATASM_SPARE_MODE_PG_7 = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_DATASM_SPARE_MODE_PG_SERVO_CONFIG = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_DATASM_SPARE_MODE_PG_SERVO_CONFIG_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_DATASM_SPARE_MODE_PG_CTL_CLKDIST_PDWN = 60 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_DATASM_STAT10_EO_PG_RX_SCAN_N_16_23_RO_SIGNAL = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_DATASM_STAT10_EO_PG_RX_SCAN_N_16_23_RO_SIGNAL_LEN = 8 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_DATASM_STAT11_EO_PG_RX_SCAN_N_0_15_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_DATASM_STAT11_EO_PG_RX_SCAN_N_0_15_RO_SIGNAL_LEN = 16 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_DATASM_STAT1_EO_PG_RX_BER_COUNT_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_DATASM_STAT1_EO_PG_RX_BER_COUNT_RO_SIGNAL_LEN = 11 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_DATASM_STAT1_EO_PG_RX_BER_COUNT_SATURATED_RO_SIGNAL = 59 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_DATASM_STAT1_EO_PG_RX_BER_COUNT_FROZEN_BY_ERR_CNT_RO_SIGNAL = 60
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_DATASM_STAT1_EO_PG_RX_BER_COUNT_FROZEN_BY_TIMER_RO_SIGNAL = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_DATASM_STAT1_EO_PG_RX_BER_TIMER_SATURATED_RO_SIGNAL = 62 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_DATASM_STAT2_EO_PG_RX_BER_TIMER_VALUE_0_15_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_DATASM_STAT2_EO_PG_RX_BER_TIMER_VALUE_0_15_RO_SIGNAL_LEN = 16 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_DATASM_STAT3_EO_PG_RX_BER_TIMER_VALUE_16_31_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_DATASM_STAT3_EO_PG_RX_BER_TIMER_VALUE_16_31_RO_SIGNAL_LEN = 16 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_DATASM_STAT4_EO_PG_RX_DATA_PIPE_0_15_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_DATASM_STAT4_EO_PG_RX_DATA_PIPE_0_15_RO_SIGNAL_LEN = 16 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_DATASM_STAT5_EO_PG_RX_DATA_PIPE_16_31_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_DATASM_STAT5_EO_PG_RX_DATA_PIPE_16_31_RO_SIGNAL_LEN = 16 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_DATASM_STAT6_EO_PG_RX_SERVO_STATUS_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_DATASM_STAT6_EO_PG_RX_SERVO_STATUS_RO_SIGNAL_LEN = 16 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_DATASM_STAT7_EO_PG_RX_SERVO_CHG_CNT_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_DATASM_STAT7_EO_PG_RX_SERVO_CHG_CNT_RO_SIGNAL_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_DATASM_STAT7_EO_PG_RX_IREF_PARITY_CHK_RO_SIGNAL = 59 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_DATASM_STAT7_EO_PG_RX_IREF_PARITY_CHK_RO_SIGNAL_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_DATASM_STAT7_EO_PG_RX_PRVCPT_CHANGE_DET_RO_SIGNAL = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_DATASM_STAT8_EO_PG_RX_SCAN_P_0_15_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_DATASM_STAT8_EO_PG_RX_SCAN_P_0_15_RO_SIGNAL_LEN = 16 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_DATASM_STAT9_EO_PG_RX_SCAN_P_16_23_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_DATASM_STAT9_EO_PG_RX_SCAN_P_16_23_RO_SIGNAL_LEN = 9 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_FIR1_ERROR_INJECT_PG_ERR_INJ = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_FIR1_ERROR_INJECT_PG_ERR_INJ_LEN = 15 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_FIR1_MASK_PG_ERRS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_FIR1_MASK_PG_ERRS_LEN = 15 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_PG_REGS_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_GCR_BUFF_RO_SIGNAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_GCRS_LD_SM_RO_SIGNAL = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_GCRS_UNLD_SM_RO_SIGNAL = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_GLBSM_REGS_RO_SIGNAL = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_GLBSM_REGRW_RO_SIGNAL = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_DATASM_REGS_RO_SIGNAL = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_DATASM_REGRW_RO_SIGNAL = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_EYEOPT_SM_RO_SIGNAL = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_BIST_MAIN_STATE_RO_SIGNAL = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_BIST_INIT_STATE_RO_SIGNAL = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_RX_SERVO_SM_RO_SIGNAL = 59 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_WORK_REGS_RO_SIGNAL = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_FIR1_PG_RX_PL_FIR_ERR_RO_SIGNAL = 62 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_GLBSM_CNTL2_EO_PG_CNT_SINGLE_LANE_RECAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_GLBSM_CNTL2_EO_PG_RECAL_LANE_TO_MONITOR = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_GLBSM_CNTL2_EO_PG_RECAL_LANE_TO_MONITOR_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_GLBSM_CNTL3_EO_PG_MANUAL_RECAL_REQUEST = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_GLBSM_CNTL3_EO_PG_MANUAL_RECAL_LANE = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_GLBSM_CNTL3_EO_PG_MANUAL_RECAL_LANE_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_GLBSM_CNTL4_EO_PG_RX_CLR_RECAL_CNT_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_GLBSM_CNTL4_EO_PG_RX_INT_RETURN_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_GLBSM_CNTL4_EO_PG_RX_MANUAL_RECAL_ABORT_WO_PULSE_SLOW_SIGNAL = 50
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_GLBSM_CNTL4_EO_PG_RX_MANUAL_RECAL_CONTINUE_WO_PULSE_SLOW_SIGNAL =
+ 51 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_GLBSM_CNTLX1_EO_PG_CLR_PAR_ERRS = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_GLBSM_CNTLX1_EO_PG_FIR_RESET = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_GLBSM_MODE1_EO_PG_RC_ENABLE_PU_EDGE_TRACK = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_GLBSM_SPARE_MODE_PG_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_GLBSM_SPARE_MODE_PG_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_GLBSM_SPARE_MODE_PG_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_GLBSM_SPARE_MODE_PG_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_GLBSM_SPARE_MODE_PG_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_GLBSM_SPARE_MODE_PG_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_GLBSM_SPARE_MODE_PG_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_GLBSM_SPARE_MODE_PG_7 = 55 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_GLBSM_STAT1_EO_PG_RX_EYE_OPT_STATE_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_GLBSM_STAT1_EO_PG_RX_EYE_OPT_STATE_RO_SIGNAL_LEN = 12 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_GLBSM_STAT2_EO_PG_RX_RECAL_CNT_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_GLBSM_STAT2_EO_PG_RX_RECAL_CNT_RO_SIGNAL_LEN = 16 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_GLBSM_STAT3_EO_PG_RX_DACTEST_ISGT_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_GLBSM_STAT3_EO_PG_RX_DACTEST_ISLT_RO_SIGNAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_GLBSM_STAT3_EO_PG_RX_DACTEST_ISEQ_RO_SIGNAL = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_GLBSM_STAT3_EO_PG_RX_DACTEST_DIFF_RO_SIGNAL = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_GLBSM_STAT3_EO_PG_RX_DACTEST_DIFF_RO_SIGNAL_LEN = 9 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_GLBSM_STAT4_EO_PG_RX_INT_REQ_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_GLBSM_STAT4_EO_PG_RX_INT_REQ_RO_SIGNAL_LEN = 16 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_GLBSM_STAT5_EO_PG_RX_LANE_CURRENTLY_INITIALIZING_RO_SIGNAL = 48
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_GLBSM_STAT5_EO_PG_RX_LANE_CURRENTLY_RECALIBRATING_RO_SIGNAL = 49
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_GLBSM_STAT5_EO_PG_RX_CURRENT_RECAL_INIT_LANE_RO_SIGNAL = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_GLBSM_STAT5_EO_PG_RX_CURRENT_RECAL_INIT_LANE_RO_SIGNAL_LEN = 5
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_GLBSM_STAT5_EO_PG_RX_MANUAL_RECAL_DONE_RO_SIGNAL = 55 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_ID1_PG_BUS_ID = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_ID1_PG_BUS_ID_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_SPARE_MODE_PG_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_SPARE_MODE_PG_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_SPARE_MODE_PG_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_SPARE_MODE_PG_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RX_SPARE_MODE_PG_4 = 52 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE0_RX_DATA_WORK_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE0_RX_DATA_WORK_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE0_RX_DATA_WORK_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE0_RX_DATA_WORK_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE0_RX_DATA_WORK_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE0_RX_DATA_WORK_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE0_RX_DATA_WORK_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE0_RX_DATA_WORK_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE0_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL
+ = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE0_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL
+ = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE0_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL
+ = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE0_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL
+ = 51 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE0_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE0_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE0_RX_GLBSM_PL_CNTL1_O_PL_RECAL_REQ = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE0_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE0_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE0_RX_GLBSM_PL_CNTL1_O_PL_FORCE_INIT_DONE = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE0_RX_GLBSM_PL_CNTL1_O_PL_FORCE_RECAL_DONE = 54 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE0_RX_GLBSM_PL_STAT1_O_PL_RX_INIT_DONE_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE0_RX_GLBSM_PL_STAT1_O_PL_RX_DCCAL_DONE_RO_SIGNAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE0_RX_GLBSM_PL_STAT1_O_PL_RX_LANE_BUSY_RO_SIGNAL = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE0_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_DONE_RO_SIGNAL = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE0_RX_GLBSM_PL_STAT1_O_PL_RX_RUN_LANE_ACTIVE_RO_SIGNAL = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE0_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_REQ_ACTIVE_RO_SIGNAL = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE0_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_ABORT_ACTIVE_RO_SIGNAL = 54
+ ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE0_RX_WORK_CNTL1_O_PL_REGS_IORESET = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE0_RX_WORK_STAT1_EO_PL_BIST_ERR_A = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE0_RX_WORK_STAT1_EO_PL_BIST_ERR_B = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE0_RX_WORK_STAT1_EO_PL_BIST_ERR_E = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE0_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE0_RX_WORK_STAT2_EO_PL_B_BAD_DFE_CONV = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE0_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE0_RX_WORK_STAT2_EO_PL_B_H1AP_AT_LIMIT = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE0_RX_WORK_STAT2_EO_PL_A_AP = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE0_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE0_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE0_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE0_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE0_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE0_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE0_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE0_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE0_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE10_RX_DATA_WORK_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE10_RX_DATA_WORK_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE10_RX_DATA_WORK_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE10_RX_DATA_WORK_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE10_RX_DATA_WORK_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE10_RX_DATA_WORK_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE10_RX_DATA_WORK_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE10_RX_DATA_WORK_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE10_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL
+ = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE10_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL
+ = 49 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE10_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE10_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL = 51 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE10_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE10_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE10_RX_GLBSM_PL_CNTL1_O_PL_RECAL_REQ = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE10_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE10_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE10_RX_GLBSM_PL_CNTL1_O_PL_FORCE_INIT_DONE = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE10_RX_GLBSM_PL_CNTL1_O_PL_FORCE_RECAL_DONE = 54 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE10_RX_GLBSM_PL_STAT1_O_PL_RX_INIT_DONE_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE10_RX_GLBSM_PL_STAT1_O_PL_RX_DCCAL_DONE_RO_SIGNAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE10_RX_GLBSM_PL_STAT1_O_PL_RX_LANE_BUSY_RO_SIGNAL = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE10_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_DONE_RO_SIGNAL = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE10_RX_GLBSM_PL_STAT1_O_PL_RX_RUN_LANE_ACTIVE_RO_SIGNAL = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE10_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_REQ_ACTIVE_RO_SIGNAL = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE10_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_ABORT_ACTIVE_RO_SIGNAL = 54
+ ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE10_RX_WORK_CNTL1_O_PL_REGS_IORESET = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE10_RX_WORK_STAT1_EO_PL_BIST_ERR_A = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE10_RX_WORK_STAT1_EO_PL_BIST_ERR_B = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE10_RX_WORK_STAT1_EO_PL_BIST_ERR_E = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE10_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE10_RX_WORK_STAT2_EO_PL_B_BAD_DFE_CONV = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE10_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE10_RX_WORK_STAT2_EO_PL_B_H1AP_AT_LIMIT = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE10_RX_WORK_STAT2_EO_PL_A_AP = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE10_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE10_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE10_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE10_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE10_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE10_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE10_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE10_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE10_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE11_RX_DATA_WORK_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE11_RX_DATA_WORK_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE11_RX_DATA_WORK_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE11_RX_DATA_WORK_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE11_RX_DATA_WORK_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE11_RX_DATA_WORK_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE11_RX_DATA_WORK_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE11_RX_DATA_WORK_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE11_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL
+ = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE11_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL
+ = 49 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE11_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE11_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL = 51 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE11_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE11_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE11_RX_GLBSM_PL_CNTL1_O_PL_RECAL_REQ = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE11_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE11_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE11_RX_GLBSM_PL_CNTL1_O_PL_FORCE_INIT_DONE = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE11_RX_GLBSM_PL_CNTL1_O_PL_FORCE_RECAL_DONE = 54 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE11_RX_GLBSM_PL_STAT1_O_PL_RX_INIT_DONE_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE11_RX_GLBSM_PL_STAT1_O_PL_RX_DCCAL_DONE_RO_SIGNAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE11_RX_GLBSM_PL_STAT1_O_PL_RX_LANE_BUSY_RO_SIGNAL = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE11_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_DONE_RO_SIGNAL = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE11_RX_GLBSM_PL_STAT1_O_PL_RX_RUN_LANE_ACTIVE_RO_SIGNAL = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE11_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_REQ_ACTIVE_RO_SIGNAL = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE11_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_ABORT_ACTIVE_RO_SIGNAL = 54
+ ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE11_RX_WORK_CNTL1_O_PL_REGS_IORESET = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE11_RX_WORK_STAT1_EO_PL_BIST_ERR_A = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE11_RX_WORK_STAT1_EO_PL_BIST_ERR_B = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE11_RX_WORK_STAT1_EO_PL_BIST_ERR_E = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE11_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE11_RX_WORK_STAT2_EO_PL_B_BAD_DFE_CONV = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE11_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE11_RX_WORK_STAT2_EO_PL_B_H1AP_AT_LIMIT = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE11_RX_WORK_STAT2_EO_PL_A_AP = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE11_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE11_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE11_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE11_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE11_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE11_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE11_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE11_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE11_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE12_RX_DATA_WORK_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE12_RX_DATA_WORK_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE12_RX_DATA_WORK_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE12_RX_DATA_WORK_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE12_RX_DATA_WORK_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE12_RX_DATA_WORK_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE12_RX_DATA_WORK_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE12_RX_DATA_WORK_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE12_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL
+ = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE12_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL
+ = 49 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE12_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE12_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL = 51 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE12_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE12_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE12_RX_GLBSM_PL_CNTL1_O_PL_RECAL_REQ = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE12_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE12_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE12_RX_GLBSM_PL_CNTL1_O_PL_FORCE_INIT_DONE = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE12_RX_GLBSM_PL_CNTL1_O_PL_FORCE_RECAL_DONE = 54 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE12_RX_GLBSM_PL_STAT1_O_PL_RX_INIT_DONE_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE12_RX_GLBSM_PL_STAT1_O_PL_RX_DCCAL_DONE_RO_SIGNAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE12_RX_GLBSM_PL_STAT1_O_PL_RX_LANE_BUSY_RO_SIGNAL = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE12_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_DONE_RO_SIGNAL = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE12_RX_GLBSM_PL_STAT1_O_PL_RX_RUN_LANE_ACTIVE_RO_SIGNAL = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE12_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_REQ_ACTIVE_RO_SIGNAL = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE12_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_ABORT_ACTIVE_RO_SIGNAL = 54
+ ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE12_RX_WORK_CNTL1_O_PL_REGS_IORESET = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE12_RX_WORK_STAT1_EO_PL_BIST_ERR_A = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE12_RX_WORK_STAT1_EO_PL_BIST_ERR_B = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE12_RX_WORK_STAT1_EO_PL_BIST_ERR_E = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE12_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE12_RX_WORK_STAT2_EO_PL_B_BAD_DFE_CONV = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE12_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE12_RX_WORK_STAT2_EO_PL_B_H1AP_AT_LIMIT = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE12_RX_WORK_STAT2_EO_PL_A_AP = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE12_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE12_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE12_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE12_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE12_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE12_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE12_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE12_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE12_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE13_RX_DATA_WORK_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE13_RX_DATA_WORK_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE13_RX_DATA_WORK_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE13_RX_DATA_WORK_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE13_RX_DATA_WORK_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE13_RX_DATA_WORK_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE13_RX_DATA_WORK_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE13_RX_DATA_WORK_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE13_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL
+ = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE13_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL
+ = 49 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE13_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE13_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL = 51 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE13_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE13_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE13_RX_GLBSM_PL_CNTL1_O_PL_RECAL_REQ = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE13_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE13_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE13_RX_GLBSM_PL_CNTL1_O_PL_FORCE_INIT_DONE = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE13_RX_GLBSM_PL_CNTL1_O_PL_FORCE_RECAL_DONE = 54 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE13_RX_GLBSM_PL_STAT1_O_PL_RX_INIT_DONE_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE13_RX_GLBSM_PL_STAT1_O_PL_RX_DCCAL_DONE_RO_SIGNAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE13_RX_GLBSM_PL_STAT1_O_PL_RX_LANE_BUSY_RO_SIGNAL = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE13_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_DONE_RO_SIGNAL = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE13_RX_GLBSM_PL_STAT1_O_PL_RX_RUN_LANE_ACTIVE_RO_SIGNAL = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE13_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_REQ_ACTIVE_RO_SIGNAL = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE13_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_ABORT_ACTIVE_RO_SIGNAL = 54
+ ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE13_RX_WORK_CNTL1_O_PL_REGS_IORESET = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE13_RX_WORK_STAT1_EO_PL_BIST_ERR_A = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE13_RX_WORK_STAT1_EO_PL_BIST_ERR_B = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE13_RX_WORK_STAT1_EO_PL_BIST_ERR_E = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE13_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE13_RX_WORK_STAT2_EO_PL_B_BAD_DFE_CONV = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE13_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE13_RX_WORK_STAT2_EO_PL_B_H1AP_AT_LIMIT = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE13_RX_WORK_STAT2_EO_PL_A_AP = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE13_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE13_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE13_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE13_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE13_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE13_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE13_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE13_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE13_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE14_RX_DATA_WORK_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE14_RX_DATA_WORK_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE14_RX_DATA_WORK_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE14_RX_DATA_WORK_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE14_RX_DATA_WORK_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE14_RX_DATA_WORK_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE14_RX_DATA_WORK_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE14_RX_DATA_WORK_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE14_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL
+ = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE14_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL
+ = 49 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE14_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE14_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL = 51 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE14_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE14_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE14_RX_GLBSM_PL_CNTL1_O_PL_RECAL_REQ = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE14_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE14_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE14_RX_GLBSM_PL_CNTL1_O_PL_FORCE_INIT_DONE = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE14_RX_GLBSM_PL_CNTL1_O_PL_FORCE_RECAL_DONE = 54 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE14_RX_GLBSM_PL_STAT1_O_PL_RX_INIT_DONE_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE14_RX_GLBSM_PL_STAT1_O_PL_RX_DCCAL_DONE_RO_SIGNAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE14_RX_GLBSM_PL_STAT1_O_PL_RX_LANE_BUSY_RO_SIGNAL = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE14_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_DONE_RO_SIGNAL = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE14_RX_GLBSM_PL_STAT1_O_PL_RX_RUN_LANE_ACTIVE_RO_SIGNAL = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE14_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_REQ_ACTIVE_RO_SIGNAL = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE14_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_ABORT_ACTIVE_RO_SIGNAL = 54
+ ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE14_RX_WORK_CNTL1_O_PL_REGS_IORESET = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE14_RX_WORK_STAT1_EO_PL_BIST_ERR_A = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE14_RX_WORK_STAT1_EO_PL_BIST_ERR_B = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE14_RX_WORK_STAT1_EO_PL_BIST_ERR_E = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE14_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE14_RX_WORK_STAT2_EO_PL_B_BAD_DFE_CONV = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE14_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE14_RX_WORK_STAT2_EO_PL_B_H1AP_AT_LIMIT = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE14_RX_WORK_STAT2_EO_PL_A_AP = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE14_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE14_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE14_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE14_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE14_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE14_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE14_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE14_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE14_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE15_RX_DATA_WORK_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE15_RX_DATA_WORK_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE15_RX_DATA_WORK_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE15_RX_DATA_WORK_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE15_RX_DATA_WORK_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE15_RX_DATA_WORK_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE15_RX_DATA_WORK_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE15_RX_DATA_WORK_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE15_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL
+ = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE15_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL
+ = 49 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE15_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE15_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL = 51 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE15_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE15_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE15_RX_GLBSM_PL_CNTL1_O_PL_RECAL_REQ = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE15_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE15_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE15_RX_GLBSM_PL_CNTL1_O_PL_FORCE_INIT_DONE = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE15_RX_GLBSM_PL_CNTL1_O_PL_FORCE_RECAL_DONE = 54 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE15_RX_GLBSM_PL_STAT1_O_PL_RX_INIT_DONE_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE15_RX_GLBSM_PL_STAT1_O_PL_RX_DCCAL_DONE_RO_SIGNAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE15_RX_GLBSM_PL_STAT1_O_PL_RX_LANE_BUSY_RO_SIGNAL = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE15_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_DONE_RO_SIGNAL = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE15_RX_GLBSM_PL_STAT1_O_PL_RX_RUN_LANE_ACTIVE_RO_SIGNAL = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE15_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_REQ_ACTIVE_RO_SIGNAL = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE15_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_ABORT_ACTIVE_RO_SIGNAL = 54
+ ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE15_RX_WORK_CNTL1_O_PL_REGS_IORESET = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE15_RX_WORK_STAT1_EO_PL_BIST_ERR_A = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE15_RX_WORK_STAT1_EO_PL_BIST_ERR_B = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE15_RX_WORK_STAT1_EO_PL_BIST_ERR_E = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE15_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE15_RX_WORK_STAT2_EO_PL_B_BAD_DFE_CONV = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE15_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE15_RX_WORK_STAT2_EO_PL_B_H1AP_AT_LIMIT = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE15_RX_WORK_STAT2_EO_PL_A_AP = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE15_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE15_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE15_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE15_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE15_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE15_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE15_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE15_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE15_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE16_RX_DATA_WORK_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE16_RX_DATA_WORK_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE16_RX_DATA_WORK_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE16_RX_DATA_WORK_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE16_RX_DATA_WORK_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE16_RX_DATA_WORK_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE16_RX_DATA_WORK_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE16_RX_DATA_WORK_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE16_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL
+ = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE16_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL
+ = 49 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE16_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE16_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL = 51 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE16_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE16_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE16_RX_GLBSM_PL_CNTL1_O_PL_RECAL_REQ = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE16_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE16_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE16_RX_GLBSM_PL_CNTL1_O_PL_FORCE_INIT_DONE = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE16_RX_GLBSM_PL_CNTL1_O_PL_FORCE_RECAL_DONE = 54 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE16_RX_GLBSM_PL_STAT1_O_PL_RX_INIT_DONE_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE16_RX_GLBSM_PL_STAT1_O_PL_RX_DCCAL_DONE_RO_SIGNAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE16_RX_GLBSM_PL_STAT1_O_PL_RX_LANE_BUSY_RO_SIGNAL = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE16_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_DONE_RO_SIGNAL = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE16_RX_GLBSM_PL_STAT1_O_PL_RX_RUN_LANE_ACTIVE_RO_SIGNAL = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE16_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_REQ_ACTIVE_RO_SIGNAL = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE16_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_ABORT_ACTIVE_RO_SIGNAL = 54
+ ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE16_RX_WORK_CNTL1_O_PL_REGS_IORESET = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE16_RX_WORK_STAT1_EO_PL_BIST_ERR_A = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE16_RX_WORK_STAT1_EO_PL_BIST_ERR_B = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE16_RX_WORK_STAT1_EO_PL_BIST_ERR_E = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE16_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE16_RX_WORK_STAT2_EO_PL_B_BAD_DFE_CONV = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE16_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE16_RX_WORK_STAT2_EO_PL_B_H1AP_AT_LIMIT = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE16_RX_WORK_STAT2_EO_PL_A_AP = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE16_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE16_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE16_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE16_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE16_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE16_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE16_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE16_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE16_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE17_RX_DATA_WORK_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE17_RX_DATA_WORK_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE17_RX_DATA_WORK_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE17_RX_DATA_WORK_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE17_RX_DATA_WORK_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE17_RX_DATA_WORK_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE17_RX_DATA_WORK_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE17_RX_DATA_WORK_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE17_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL
+ = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE17_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL
+ = 49 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE17_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE17_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL = 51 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE17_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE17_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE17_RX_GLBSM_PL_CNTL1_O_PL_RECAL_REQ = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE17_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE17_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE17_RX_GLBSM_PL_CNTL1_O_PL_FORCE_INIT_DONE = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE17_RX_GLBSM_PL_CNTL1_O_PL_FORCE_RECAL_DONE = 54 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE17_RX_GLBSM_PL_STAT1_O_PL_RX_INIT_DONE_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE17_RX_GLBSM_PL_STAT1_O_PL_RX_DCCAL_DONE_RO_SIGNAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE17_RX_GLBSM_PL_STAT1_O_PL_RX_LANE_BUSY_RO_SIGNAL = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE17_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_DONE_RO_SIGNAL = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE17_RX_GLBSM_PL_STAT1_O_PL_RX_RUN_LANE_ACTIVE_RO_SIGNAL = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE17_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_REQ_ACTIVE_RO_SIGNAL = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE17_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_ABORT_ACTIVE_RO_SIGNAL = 54
+ ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE17_RX_WORK_CNTL1_O_PL_REGS_IORESET = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE17_RX_WORK_STAT1_EO_PL_BIST_ERR_A = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE17_RX_WORK_STAT1_EO_PL_BIST_ERR_B = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE17_RX_WORK_STAT1_EO_PL_BIST_ERR_E = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE17_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE17_RX_WORK_STAT2_EO_PL_B_BAD_DFE_CONV = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE17_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE17_RX_WORK_STAT2_EO_PL_B_H1AP_AT_LIMIT = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE17_RX_WORK_STAT2_EO_PL_A_AP = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE17_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE17_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE17_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE17_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE17_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE17_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE17_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE17_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE17_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE18_RX_DATA_WORK_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE18_RX_DATA_WORK_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE18_RX_DATA_WORK_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE18_RX_DATA_WORK_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE18_RX_DATA_WORK_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE18_RX_DATA_WORK_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE18_RX_DATA_WORK_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE18_RX_DATA_WORK_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE18_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL
+ = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE18_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL
+ = 49 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE18_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE18_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL = 51 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE18_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE18_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE18_RX_GLBSM_PL_CNTL1_O_PL_RECAL_REQ = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE18_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE18_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE18_RX_GLBSM_PL_CNTL1_O_PL_FORCE_INIT_DONE = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE18_RX_GLBSM_PL_CNTL1_O_PL_FORCE_RECAL_DONE = 54 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE18_RX_GLBSM_PL_STAT1_O_PL_RX_INIT_DONE_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE18_RX_GLBSM_PL_STAT1_O_PL_RX_DCCAL_DONE_RO_SIGNAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE18_RX_GLBSM_PL_STAT1_O_PL_RX_LANE_BUSY_RO_SIGNAL = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE18_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_DONE_RO_SIGNAL = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE18_RX_GLBSM_PL_STAT1_O_PL_RX_RUN_LANE_ACTIVE_RO_SIGNAL = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE18_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_REQ_ACTIVE_RO_SIGNAL = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE18_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_ABORT_ACTIVE_RO_SIGNAL = 54
+ ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE18_RX_WORK_CNTL1_O_PL_REGS_IORESET = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE18_RX_WORK_STAT1_EO_PL_BIST_ERR_A = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE18_RX_WORK_STAT1_EO_PL_BIST_ERR_B = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE18_RX_WORK_STAT1_EO_PL_BIST_ERR_E = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE18_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE18_RX_WORK_STAT2_EO_PL_B_BAD_DFE_CONV = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE18_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE18_RX_WORK_STAT2_EO_PL_B_H1AP_AT_LIMIT = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE18_RX_WORK_STAT2_EO_PL_A_AP = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE18_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE18_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE18_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE18_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE18_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE18_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE18_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE18_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE18_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE19_RX_DATA_WORK_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE19_RX_DATA_WORK_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE19_RX_DATA_WORK_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE19_RX_DATA_WORK_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE19_RX_DATA_WORK_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE19_RX_DATA_WORK_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE19_RX_DATA_WORK_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE19_RX_DATA_WORK_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE19_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL
+ = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE19_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL
+ = 49 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE19_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE19_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL = 51 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE19_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE19_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE19_RX_GLBSM_PL_CNTL1_O_PL_RECAL_REQ = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE19_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE19_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE19_RX_GLBSM_PL_CNTL1_O_PL_FORCE_INIT_DONE = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE19_RX_GLBSM_PL_CNTL1_O_PL_FORCE_RECAL_DONE = 54 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE19_RX_GLBSM_PL_STAT1_O_PL_RX_INIT_DONE_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE19_RX_GLBSM_PL_STAT1_O_PL_RX_DCCAL_DONE_RO_SIGNAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE19_RX_GLBSM_PL_STAT1_O_PL_RX_LANE_BUSY_RO_SIGNAL = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE19_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_DONE_RO_SIGNAL = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE19_RX_GLBSM_PL_STAT1_O_PL_RX_RUN_LANE_ACTIVE_RO_SIGNAL = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE19_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_REQ_ACTIVE_RO_SIGNAL = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE19_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_ABORT_ACTIVE_RO_SIGNAL = 54
+ ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE19_RX_WORK_CNTL1_O_PL_REGS_IORESET = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE19_RX_WORK_STAT1_EO_PL_BIST_ERR_A = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE19_RX_WORK_STAT1_EO_PL_BIST_ERR_B = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE19_RX_WORK_STAT1_EO_PL_BIST_ERR_E = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE19_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE19_RX_WORK_STAT2_EO_PL_B_BAD_DFE_CONV = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE19_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE19_RX_WORK_STAT2_EO_PL_B_H1AP_AT_LIMIT = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE19_RX_WORK_STAT2_EO_PL_A_AP = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE19_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE19_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE19_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE19_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE19_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE19_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE19_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE19_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE19_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE1_RX_DATA_WORK_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE1_RX_DATA_WORK_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE1_RX_DATA_WORK_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE1_RX_DATA_WORK_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE1_RX_DATA_WORK_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE1_RX_DATA_WORK_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE1_RX_DATA_WORK_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE1_RX_DATA_WORK_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE1_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL
+ = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE1_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL
+ = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE1_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL
+ = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE1_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL
+ = 51 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE1_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE1_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE1_RX_GLBSM_PL_CNTL1_O_PL_RECAL_REQ = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE1_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE1_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE1_RX_GLBSM_PL_CNTL1_O_PL_FORCE_INIT_DONE = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE1_RX_GLBSM_PL_CNTL1_O_PL_FORCE_RECAL_DONE = 54 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE1_RX_GLBSM_PL_STAT1_O_PL_RX_INIT_DONE_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE1_RX_GLBSM_PL_STAT1_O_PL_RX_DCCAL_DONE_RO_SIGNAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE1_RX_GLBSM_PL_STAT1_O_PL_RX_LANE_BUSY_RO_SIGNAL = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE1_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_DONE_RO_SIGNAL = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE1_RX_GLBSM_PL_STAT1_O_PL_RX_RUN_LANE_ACTIVE_RO_SIGNAL = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE1_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_REQ_ACTIVE_RO_SIGNAL = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE1_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_ABORT_ACTIVE_RO_SIGNAL = 54
+ ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE1_RX_WORK_CNTL1_O_PL_REGS_IORESET = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE1_RX_WORK_STAT1_EO_PL_BIST_ERR_A = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE1_RX_WORK_STAT1_EO_PL_BIST_ERR_B = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE1_RX_WORK_STAT1_EO_PL_BIST_ERR_E = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE1_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE1_RX_WORK_STAT2_EO_PL_B_BAD_DFE_CONV = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE1_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE1_RX_WORK_STAT2_EO_PL_B_H1AP_AT_LIMIT = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE1_RX_WORK_STAT2_EO_PL_A_AP = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE1_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE1_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE1_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE1_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE1_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE1_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE1_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE1_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE1_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE20_RX_DATA_WORK_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE20_RX_DATA_WORK_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE20_RX_DATA_WORK_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE20_RX_DATA_WORK_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE20_RX_DATA_WORK_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE20_RX_DATA_WORK_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE20_RX_DATA_WORK_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE20_RX_DATA_WORK_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE20_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL
+ = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE20_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL
+ = 49 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE20_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE20_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL = 51 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE20_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE20_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE20_RX_GLBSM_PL_CNTL1_O_PL_RECAL_REQ = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE20_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE20_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE20_RX_GLBSM_PL_CNTL1_O_PL_FORCE_INIT_DONE = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE20_RX_GLBSM_PL_CNTL1_O_PL_FORCE_RECAL_DONE = 54 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE20_RX_GLBSM_PL_STAT1_O_PL_RX_INIT_DONE_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE20_RX_GLBSM_PL_STAT1_O_PL_RX_DCCAL_DONE_RO_SIGNAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE20_RX_GLBSM_PL_STAT1_O_PL_RX_LANE_BUSY_RO_SIGNAL = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE20_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_DONE_RO_SIGNAL = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE20_RX_GLBSM_PL_STAT1_O_PL_RX_RUN_LANE_ACTIVE_RO_SIGNAL = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE20_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_REQ_ACTIVE_RO_SIGNAL = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE20_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_ABORT_ACTIVE_RO_SIGNAL = 54
+ ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE20_RX_WORK_CNTL1_O_PL_REGS_IORESET = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE20_RX_WORK_STAT1_EO_PL_BIST_ERR_A = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE20_RX_WORK_STAT1_EO_PL_BIST_ERR_B = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE20_RX_WORK_STAT1_EO_PL_BIST_ERR_E = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE20_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE20_RX_WORK_STAT2_EO_PL_B_BAD_DFE_CONV = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE20_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE20_RX_WORK_STAT2_EO_PL_B_H1AP_AT_LIMIT = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE20_RX_WORK_STAT2_EO_PL_A_AP = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE20_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE20_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE20_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE20_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE20_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE20_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE20_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE20_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE20_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE21_RX_DATA_WORK_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE21_RX_DATA_WORK_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE21_RX_DATA_WORK_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE21_RX_DATA_WORK_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE21_RX_DATA_WORK_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE21_RX_DATA_WORK_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE21_RX_DATA_WORK_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE21_RX_DATA_WORK_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE21_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL
+ = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE21_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL
+ = 49 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE21_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE21_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL = 51 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE21_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE21_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE21_RX_GLBSM_PL_CNTL1_O_PL_RECAL_REQ = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE21_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE21_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE21_RX_GLBSM_PL_CNTL1_O_PL_FORCE_INIT_DONE = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE21_RX_GLBSM_PL_CNTL1_O_PL_FORCE_RECAL_DONE = 54 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE21_RX_GLBSM_PL_STAT1_O_PL_RX_INIT_DONE_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE21_RX_GLBSM_PL_STAT1_O_PL_RX_DCCAL_DONE_RO_SIGNAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE21_RX_GLBSM_PL_STAT1_O_PL_RX_LANE_BUSY_RO_SIGNAL = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE21_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_DONE_RO_SIGNAL = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE21_RX_GLBSM_PL_STAT1_O_PL_RX_RUN_LANE_ACTIVE_RO_SIGNAL = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE21_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_REQ_ACTIVE_RO_SIGNAL = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE21_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_ABORT_ACTIVE_RO_SIGNAL = 54
+ ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE21_RX_WORK_CNTL1_O_PL_REGS_IORESET = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE21_RX_WORK_STAT1_EO_PL_BIST_ERR_A = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE21_RX_WORK_STAT1_EO_PL_BIST_ERR_B = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE21_RX_WORK_STAT1_EO_PL_BIST_ERR_E = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE21_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE21_RX_WORK_STAT2_EO_PL_B_BAD_DFE_CONV = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE21_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE21_RX_WORK_STAT2_EO_PL_B_H1AP_AT_LIMIT = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE21_RX_WORK_STAT2_EO_PL_A_AP = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE21_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE21_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE21_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE21_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE21_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE21_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE21_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE21_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE21_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE22_RX_DATA_WORK_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE22_RX_DATA_WORK_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE22_RX_DATA_WORK_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE22_RX_DATA_WORK_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE22_RX_DATA_WORK_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE22_RX_DATA_WORK_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE22_RX_DATA_WORK_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE22_RX_DATA_WORK_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE22_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL
+ = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE22_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL
+ = 49 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE22_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE22_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL = 51 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE22_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE22_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE22_RX_GLBSM_PL_CNTL1_O_PL_RECAL_REQ = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE22_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE22_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE22_RX_GLBSM_PL_CNTL1_O_PL_FORCE_INIT_DONE = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE22_RX_GLBSM_PL_CNTL1_O_PL_FORCE_RECAL_DONE = 54 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE22_RX_GLBSM_PL_STAT1_O_PL_RX_INIT_DONE_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE22_RX_GLBSM_PL_STAT1_O_PL_RX_DCCAL_DONE_RO_SIGNAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE22_RX_GLBSM_PL_STAT1_O_PL_RX_LANE_BUSY_RO_SIGNAL = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE22_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_DONE_RO_SIGNAL = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE22_RX_GLBSM_PL_STAT1_O_PL_RX_RUN_LANE_ACTIVE_RO_SIGNAL = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE22_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_REQ_ACTIVE_RO_SIGNAL = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE22_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_ABORT_ACTIVE_RO_SIGNAL = 54
+ ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE22_RX_WORK_CNTL1_O_PL_REGS_IORESET = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE22_RX_WORK_STAT1_EO_PL_BIST_ERR_A = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE22_RX_WORK_STAT1_EO_PL_BIST_ERR_B = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE22_RX_WORK_STAT1_EO_PL_BIST_ERR_E = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE22_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE22_RX_WORK_STAT2_EO_PL_B_BAD_DFE_CONV = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE22_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE22_RX_WORK_STAT2_EO_PL_B_H1AP_AT_LIMIT = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE22_RX_WORK_STAT2_EO_PL_A_AP = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE22_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE22_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE22_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE22_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE22_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE22_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE22_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE22_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE22_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE23_RX_DATA_WORK_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE23_RX_DATA_WORK_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE23_RX_DATA_WORK_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE23_RX_DATA_WORK_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE23_RX_DATA_WORK_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE23_RX_DATA_WORK_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE23_RX_DATA_WORK_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE23_RX_DATA_WORK_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE23_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL
+ = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE23_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL
+ = 49 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE23_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE23_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL = 51 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE23_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE23_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE23_RX_GLBSM_PL_CNTL1_O_PL_RECAL_REQ = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE23_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE23_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE23_RX_GLBSM_PL_CNTL1_O_PL_FORCE_INIT_DONE = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE23_RX_GLBSM_PL_CNTL1_O_PL_FORCE_RECAL_DONE = 54 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE23_RX_GLBSM_PL_STAT1_O_PL_RX_INIT_DONE_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE23_RX_GLBSM_PL_STAT1_O_PL_RX_DCCAL_DONE_RO_SIGNAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE23_RX_GLBSM_PL_STAT1_O_PL_RX_LANE_BUSY_RO_SIGNAL = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE23_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_DONE_RO_SIGNAL = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE23_RX_GLBSM_PL_STAT1_O_PL_RX_RUN_LANE_ACTIVE_RO_SIGNAL = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE23_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_REQ_ACTIVE_RO_SIGNAL = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE23_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_ABORT_ACTIVE_RO_SIGNAL = 54
+ ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE23_RX_WORK_CNTL1_O_PL_REGS_IORESET = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE23_RX_WORK_STAT1_EO_PL_BIST_ERR_A = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE23_RX_WORK_STAT1_EO_PL_BIST_ERR_B = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE23_RX_WORK_STAT1_EO_PL_BIST_ERR_E = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE23_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE23_RX_WORK_STAT2_EO_PL_B_BAD_DFE_CONV = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE23_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE23_RX_WORK_STAT2_EO_PL_B_H1AP_AT_LIMIT = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE23_RX_WORK_STAT2_EO_PL_A_AP = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE23_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE23_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE23_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE23_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE23_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE23_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE23_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE23_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE23_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE2_RX_DATA_WORK_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE2_RX_DATA_WORK_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE2_RX_DATA_WORK_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE2_RX_DATA_WORK_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE2_RX_DATA_WORK_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE2_RX_DATA_WORK_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE2_RX_DATA_WORK_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE2_RX_DATA_WORK_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE2_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL
+ = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE2_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL
+ = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE2_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL
+ = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE2_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL
+ = 51 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE2_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE2_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE2_RX_GLBSM_PL_CNTL1_O_PL_RECAL_REQ = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE2_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE2_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE2_RX_GLBSM_PL_CNTL1_O_PL_FORCE_INIT_DONE = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE2_RX_GLBSM_PL_CNTL1_O_PL_FORCE_RECAL_DONE = 54 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE2_RX_GLBSM_PL_STAT1_O_PL_RX_INIT_DONE_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE2_RX_GLBSM_PL_STAT1_O_PL_RX_DCCAL_DONE_RO_SIGNAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE2_RX_GLBSM_PL_STAT1_O_PL_RX_LANE_BUSY_RO_SIGNAL = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE2_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_DONE_RO_SIGNAL = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE2_RX_GLBSM_PL_STAT1_O_PL_RX_RUN_LANE_ACTIVE_RO_SIGNAL = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE2_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_REQ_ACTIVE_RO_SIGNAL = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE2_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_ABORT_ACTIVE_RO_SIGNAL = 54
+ ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE2_RX_WORK_CNTL1_O_PL_REGS_IORESET = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE2_RX_WORK_STAT1_EO_PL_BIST_ERR_A = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE2_RX_WORK_STAT1_EO_PL_BIST_ERR_B = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE2_RX_WORK_STAT1_EO_PL_BIST_ERR_E = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE2_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE2_RX_WORK_STAT2_EO_PL_B_BAD_DFE_CONV = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE2_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE2_RX_WORK_STAT2_EO_PL_B_H1AP_AT_LIMIT = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE2_RX_WORK_STAT2_EO_PL_A_AP = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE2_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE2_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE2_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE2_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE2_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE2_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE2_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE2_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE2_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE3_RX_DATA_WORK_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE3_RX_DATA_WORK_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE3_RX_DATA_WORK_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE3_RX_DATA_WORK_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE3_RX_DATA_WORK_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE3_RX_DATA_WORK_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE3_RX_DATA_WORK_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE3_RX_DATA_WORK_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE3_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL
+ = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE3_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL
+ = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE3_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL
+ = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE3_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL
+ = 51 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE3_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE3_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE3_RX_GLBSM_PL_CNTL1_O_PL_RECAL_REQ = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE3_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE3_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE3_RX_GLBSM_PL_CNTL1_O_PL_FORCE_INIT_DONE = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE3_RX_GLBSM_PL_CNTL1_O_PL_FORCE_RECAL_DONE = 54 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE3_RX_GLBSM_PL_STAT1_O_PL_RX_INIT_DONE_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE3_RX_GLBSM_PL_STAT1_O_PL_RX_DCCAL_DONE_RO_SIGNAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE3_RX_GLBSM_PL_STAT1_O_PL_RX_LANE_BUSY_RO_SIGNAL = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE3_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_DONE_RO_SIGNAL = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE3_RX_GLBSM_PL_STAT1_O_PL_RX_RUN_LANE_ACTIVE_RO_SIGNAL = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE3_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_REQ_ACTIVE_RO_SIGNAL = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE3_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_ABORT_ACTIVE_RO_SIGNAL = 54
+ ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE3_RX_WORK_CNTL1_O_PL_REGS_IORESET = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE3_RX_WORK_STAT1_EO_PL_BIST_ERR_A = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE3_RX_WORK_STAT1_EO_PL_BIST_ERR_B = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE3_RX_WORK_STAT1_EO_PL_BIST_ERR_E = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE3_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE3_RX_WORK_STAT2_EO_PL_B_BAD_DFE_CONV = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE3_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE3_RX_WORK_STAT2_EO_PL_B_H1AP_AT_LIMIT = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE3_RX_WORK_STAT2_EO_PL_A_AP = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE3_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE3_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE3_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE3_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE3_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE3_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE3_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE3_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE3_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE4_RX_DATA_WORK_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE4_RX_DATA_WORK_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE4_RX_DATA_WORK_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE4_RX_DATA_WORK_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE4_RX_DATA_WORK_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE4_RX_DATA_WORK_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE4_RX_DATA_WORK_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE4_RX_DATA_WORK_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE4_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL
+ = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE4_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL
+ = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE4_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL
+ = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE4_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL
+ = 51 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE4_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE4_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE4_RX_GLBSM_PL_CNTL1_O_PL_RECAL_REQ = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE4_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE4_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE4_RX_GLBSM_PL_CNTL1_O_PL_FORCE_INIT_DONE = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE4_RX_GLBSM_PL_CNTL1_O_PL_FORCE_RECAL_DONE = 54 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE4_RX_GLBSM_PL_STAT1_O_PL_RX_INIT_DONE_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE4_RX_GLBSM_PL_STAT1_O_PL_RX_DCCAL_DONE_RO_SIGNAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE4_RX_GLBSM_PL_STAT1_O_PL_RX_LANE_BUSY_RO_SIGNAL = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE4_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_DONE_RO_SIGNAL = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE4_RX_GLBSM_PL_STAT1_O_PL_RX_RUN_LANE_ACTIVE_RO_SIGNAL = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE4_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_REQ_ACTIVE_RO_SIGNAL = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE4_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_ABORT_ACTIVE_RO_SIGNAL = 54
+ ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE4_RX_WORK_CNTL1_O_PL_REGS_IORESET = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE4_RX_WORK_STAT1_EO_PL_BIST_ERR_A = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE4_RX_WORK_STAT1_EO_PL_BIST_ERR_B = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE4_RX_WORK_STAT1_EO_PL_BIST_ERR_E = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE4_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE4_RX_WORK_STAT2_EO_PL_B_BAD_DFE_CONV = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE4_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE4_RX_WORK_STAT2_EO_PL_B_H1AP_AT_LIMIT = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE4_RX_WORK_STAT2_EO_PL_A_AP = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE4_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE4_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE4_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE4_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE4_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE4_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE4_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE4_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE4_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE5_RX_DATA_WORK_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE5_RX_DATA_WORK_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE5_RX_DATA_WORK_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE5_RX_DATA_WORK_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE5_RX_DATA_WORK_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE5_RX_DATA_WORK_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE5_RX_DATA_WORK_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE5_RX_DATA_WORK_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE5_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL
+ = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE5_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL
+ = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE5_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL
+ = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE5_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL
+ = 51 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE5_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE5_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE5_RX_GLBSM_PL_CNTL1_O_PL_RECAL_REQ = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE5_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE5_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE5_RX_GLBSM_PL_CNTL1_O_PL_FORCE_INIT_DONE = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE5_RX_GLBSM_PL_CNTL1_O_PL_FORCE_RECAL_DONE = 54 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE5_RX_GLBSM_PL_STAT1_O_PL_RX_INIT_DONE_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE5_RX_GLBSM_PL_STAT1_O_PL_RX_DCCAL_DONE_RO_SIGNAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE5_RX_GLBSM_PL_STAT1_O_PL_RX_LANE_BUSY_RO_SIGNAL = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE5_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_DONE_RO_SIGNAL = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE5_RX_GLBSM_PL_STAT1_O_PL_RX_RUN_LANE_ACTIVE_RO_SIGNAL = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE5_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_REQ_ACTIVE_RO_SIGNAL = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE5_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_ABORT_ACTIVE_RO_SIGNAL = 54
+ ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE5_RX_WORK_CNTL1_O_PL_REGS_IORESET = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE5_RX_WORK_STAT1_EO_PL_BIST_ERR_A = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE5_RX_WORK_STAT1_EO_PL_BIST_ERR_B = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE5_RX_WORK_STAT1_EO_PL_BIST_ERR_E = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE5_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE5_RX_WORK_STAT2_EO_PL_B_BAD_DFE_CONV = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE5_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE5_RX_WORK_STAT2_EO_PL_B_H1AP_AT_LIMIT = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE5_RX_WORK_STAT2_EO_PL_A_AP = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE5_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE5_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE5_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE5_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE5_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE5_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE5_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE5_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE5_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE6_RX_DATA_WORK_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE6_RX_DATA_WORK_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE6_RX_DATA_WORK_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE6_RX_DATA_WORK_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE6_RX_DATA_WORK_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE6_RX_DATA_WORK_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE6_RX_DATA_WORK_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE6_RX_DATA_WORK_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE6_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL
+ = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE6_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL
+ = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE6_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL
+ = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE6_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL
+ = 51 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE6_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE6_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE6_RX_GLBSM_PL_CNTL1_O_PL_RECAL_REQ = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE6_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE6_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE6_RX_GLBSM_PL_CNTL1_O_PL_FORCE_INIT_DONE = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE6_RX_GLBSM_PL_CNTL1_O_PL_FORCE_RECAL_DONE = 54 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE6_RX_GLBSM_PL_STAT1_O_PL_RX_INIT_DONE_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE6_RX_GLBSM_PL_STAT1_O_PL_RX_DCCAL_DONE_RO_SIGNAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE6_RX_GLBSM_PL_STAT1_O_PL_RX_LANE_BUSY_RO_SIGNAL = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE6_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_DONE_RO_SIGNAL = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE6_RX_GLBSM_PL_STAT1_O_PL_RX_RUN_LANE_ACTIVE_RO_SIGNAL = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE6_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_REQ_ACTIVE_RO_SIGNAL = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE6_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_ABORT_ACTIVE_RO_SIGNAL = 54
+ ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE6_RX_WORK_CNTL1_O_PL_REGS_IORESET = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE6_RX_WORK_STAT1_EO_PL_BIST_ERR_A = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE6_RX_WORK_STAT1_EO_PL_BIST_ERR_B = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE6_RX_WORK_STAT1_EO_PL_BIST_ERR_E = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE6_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE6_RX_WORK_STAT2_EO_PL_B_BAD_DFE_CONV = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE6_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE6_RX_WORK_STAT2_EO_PL_B_H1AP_AT_LIMIT = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE6_RX_WORK_STAT2_EO_PL_A_AP = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE6_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE6_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE6_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE6_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE6_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE6_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE6_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE6_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE6_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE7_RX_DATA_WORK_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE7_RX_DATA_WORK_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE7_RX_DATA_WORK_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE7_RX_DATA_WORK_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE7_RX_DATA_WORK_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE7_RX_DATA_WORK_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE7_RX_DATA_WORK_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE7_RX_DATA_WORK_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE7_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL
+ = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE7_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL
+ = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE7_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL
+ = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE7_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL
+ = 51 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE7_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE7_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE7_RX_GLBSM_PL_CNTL1_O_PL_RECAL_REQ = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE7_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE7_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE7_RX_GLBSM_PL_CNTL1_O_PL_FORCE_INIT_DONE = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE7_RX_GLBSM_PL_CNTL1_O_PL_FORCE_RECAL_DONE = 54 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE7_RX_GLBSM_PL_STAT1_O_PL_RX_INIT_DONE_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE7_RX_GLBSM_PL_STAT1_O_PL_RX_DCCAL_DONE_RO_SIGNAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE7_RX_GLBSM_PL_STAT1_O_PL_RX_LANE_BUSY_RO_SIGNAL = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE7_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_DONE_RO_SIGNAL = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE7_RX_GLBSM_PL_STAT1_O_PL_RX_RUN_LANE_ACTIVE_RO_SIGNAL = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE7_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_REQ_ACTIVE_RO_SIGNAL = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE7_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_ABORT_ACTIVE_RO_SIGNAL = 54
+ ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE7_RX_WORK_CNTL1_O_PL_REGS_IORESET = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE7_RX_WORK_STAT1_EO_PL_BIST_ERR_A = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE7_RX_WORK_STAT1_EO_PL_BIST_ERR_B = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE7_RX_WORK_STAT1_EO_PL_BIST_ERR_E = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE7_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE7_RX_WORK_STAT2_EO_PL_B_BAD_DFE_CONV = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE7_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE7_RX_WORK_STAT2_EO_PL_B_H1AP_AT_LIMIT = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE7_RX_WORK_STAT2_EO_PL_A_AP = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE7_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE7_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE7_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE7_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE7_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE7_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE7_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE7_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE7_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE8_RX_DATA_WORK_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE8_RX_DATA_WORK_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE8_RX_DATA_WORK_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE8_RX_DATA_WORK_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE8_RX_DATA_WORK_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE8_RX_DATA_WORK_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE8_RX_DATA_WORK_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE8_RX_DATA_WORK_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE8_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL
+ = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE8_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL
+ = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE8_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL
+ = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE8_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL
+ = 51 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE8_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE8_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE8_RX_GLBSM_PL_CNTL1_O_PL_RECAL_REQ = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE8_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE8_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE8_RX_GLBSM_PL_CNTL1_O_PL_FORCE_INIT_DONE = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE8_RX_GLBSM_PL_CNTL1_O_PL_FORCE_RECAL_DONE = 54 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE8_RX_GLBSM_PL_STAT1_O_PL_RX_INIT_DONE_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE8_RX_GLBSM_PL_STAT1_O_PL_RX_DCCAL_DONE_RO_SIGNAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE8_RX_GLBSM_PL_STAT1_O_PL_RX_LANE_BUSY_RO_SIGNAL = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE8_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_DONE_RO_SIGNAL = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE8_RX_GLBSM_PL_STAT1_O_PL_RX_RUN_LANE_ACTIVE_RO_SIGNAL = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE8_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_REQ_ACTIVE_RO_SIGNAL = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE8_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_ABORT_ACTIVE_RO_SIGNAL = 54
+ ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE8_RX_WORK_CNTL1_O_PL_REGS_IORESET = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE8_RX_WORK_STAT1_EO_PL_BIST_ERR_A = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE8_RX_WORK_STAT1_EO_PL_BIST_ERR_B = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE8_RX_WORK_STAT1_EO_PL_BIST_ERR_E = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE8_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE8_RX_WORK_STAT2_EO_PL_B_BAD_DFE_CONV = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE8_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE8_RX_WORK_STAT2_EO_PL_B_H1AP_AT_LIMIT = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE8_RX_WORK_STAT2_EO_PL_A_AP = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE8_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE8_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE8_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE8_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE8_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE8_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE8_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE8_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE8_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE9_RX_DATA_WORK_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE9_RX_DATA_WORK_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE9_RX_DATA_WORK_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE9_RX_DATA_WORK_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE9_RX_DATA_WORK_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE9_RX_DATA_WORK_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE9_RX_DATA_WORK_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE9_RX_DATA_WORK_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE9_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_LANE_WO_PULSE_SLOW_SIGNAL
+ = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE9_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_LANE_WO_PULSE_SLOW_SIGNAL
+ = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE9_RX_GLBSM_PL_CNTL1X_O_PL_RX_SET_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL
+ = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE9_RX_GLBSM_PL_CNTL1X_O_PL_RX_CLR_RUN_DCCAL_WO_PULSE_SLOW_SIGNAL
+ = 51 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE9_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE9_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE9_RX_GLBSM_PL_CNTL1_O_PL_RECAL_REQ = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE9_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE9_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE9_RX_GLBSM_PL_CNTL1_O_PL_FORCE_INIT_DONE = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE9_RX_GLBSM_PL_CNTL1_O_PL_FORCE_RECAL_DONE = 54 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE9_RX_GLBSM_PL_STAT1_O_PL_RX_INIT_DONE_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE9_RX_GLBSM_PL_STAT1_O_PL_RX_DCCAL_DONE_RO_SIGNAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE9_RX_GLBSM_PL_STAT1_O_PL_RX_LANE_BUSY_RO_SIGNAL = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE9_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_DONE_RO_SIGNAL = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE9_RX_GLBSM_PL_STAT1_O_PL_RX_RUN_LANE_ACTIVE_RO_SIGNAL = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE9_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_REQ_ACTIVE_RO_SIGNAL = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE9_RX_GLBSM_PL_STAT1_O_PL_RX_RECAL_ABORT_ACTIVE_RO_SIGNAL = 54
+ ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE9_RX_WORK_CNTL1_O_PL_REGS_IORESET = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE9_RX_WORK_STAT1_EO_PL_BIST_ERR_A = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE9_RX_WORK_STAT1_EO_PL_BIST_ERR_B = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE9_RX_WORK_STAT1_EO_PL_BIST_ERR_E = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE9_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE9_RX_WORK_STAT2_EO_PL_B_BAD_DFE_CONV = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE9_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE9_RX_WORK_STAT2_EO_PL_B_H1AP_AT_LIMIT = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE9_RX_WORK_STAT2_EO_PL_A_AP = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE9_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE9_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE9_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE9_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE9_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE9_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE9_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE9_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_SLICE9_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX_FIR_ERROR_INJECT_PB_ERRS_INJ = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX_FIR_ERROR_INJECT_PB_ERRS_INJ_LEN = 10 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX_FIR_MASK_PB_ERRS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX_FIR_MASK_PB_ERRS_LEN = 10 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX_FIR_PB_RX_PB_FIR_ERRS_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX_FIR_PB_RX_PB_FIR_ERRS_RO_SIGNAL_LEN = 10 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX_FIR_RESET_PB_CLR_PAR_ERRS = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX_FIR_RESET_PB_RESET = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_SCOM_MODE_PB_GCR_TEST = 0 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_SCOM_MODE_PB_ENABLE_GCR_OFL_BUFF = 1 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_SCOM_MODE_PB_IORESET_HARD_BUS0 = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_SCOM_MODE_PB_MMIO_PG_REG_ACCESS = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_SCOM_MODE_PB_SPARES1 = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_SCOM_MODE_PB_SPARES1_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_SCOM_MODE_PB_GCR_HANG_DET_SEL = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_SCOM_MODE_PB_GCR_HANG_DET_SEL_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_SCOM_MODE_PB_GCR_BUFFER_ENABLED_RO_SIGNAL = 11 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_SCOM_MODE_PB_GCR_HANG_ERROR_MASK = 12 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_SCOM_MODE_PB_GCR_HANG_ERROR_INJ = 13 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_SCOM_MODE_PB_PPE_GCR = 14 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_SCOM_MODE_PB_CHAN_FAIL_MASK = 15 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_SCOM_MODE_PB_CHAN_FAIL_MASK_LEN = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_SCOM_MODE_PB_SPARES2 = 23 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_SCOM_MODE_PB_SPARES2_LEN = 8 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_SPARE_MODE_PB_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_SPARE_MODE_PB_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_SPARE_MODE_PB_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_SPARE_MODE_PB_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_SPARE_MODE_PB_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_SPARE_MODE_PB_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_SPARE_MODE_PB_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_SPARE_MODE_PB_7 = 55 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL = 48
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN
+ = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE0_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 53
+ ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE0_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE0_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE0_TX_CNTL2_O_PL_IORESET = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE0_TX_CNTL3_EO_PL_TDR_ENABLE = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE0_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE0_TX_FIR_MASK_PL_ERRS = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE0_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE0_TX_MODE1_PL_LANE_PDWN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE0_TX_MODE1_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE0_TX_MODE1_PL_LANE_QUIESCE = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE0_TX_MODE1_PL_LANE_QUIESCE_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE0_TX_MODE1_PL_PSAVE_REQ_DIS = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE0_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE0_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE0_TX_MODE1_PL_SPARE_MODE_0 = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE0_TX_MODE1_PL_SPARE_MODE_1 = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE0_TX_MODE1_PL_SPARE_MODE_2 = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE0_TX_MODE1_PL_SPARE_MODE_3 = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE0_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE0_TX_MODE2_PL_RXCAL = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE0_TX_MODE2_PL_UNLOAD_SEL = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE0_TX_MODE2_PL_UNLOAD_SEL_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE0_TX_STAT1_PL_LANE_BIST_ERR = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE0_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE0_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL = 48
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN
+ = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE1_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 53
+ ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE1_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE1_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE1_TX_CNTL2_O_PL_IORESET = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE1_TX_CNTL3_EO_PL_TDR_ENABLE = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE1_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE1_TX_FIR_MASK_PL_ERRS = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE1_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE1_TX_MODE1_PL_LANE_PDWN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE1_TX_MODE1_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE1_TX_MODE1_PL_LANE_QUIESCE = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE1_TX_MODE1_PL_LANE_QUIESCE_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE1_TX_MODE1_PL_PSAVE_REQ_DIS = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE1_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE1_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE1_TX_MODE1_PL_SPARE_MODE_0 = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE1_TX_MODE1_PL_SPARE_MODE_1 = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE1_TX_MODE1_PL_SPARE_MODE_2 = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE1_TX_MODE1_PL_SPARE_MODE_3 = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE1_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE1_TX_MODE2_PL_RXCAL = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE1_TX_MODE2_PL_UNLOAD_SEL = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE1_TX_MODE2_PL_UNLOAD_SEL_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE1_TX_STAT1_PL_LANE_BIST_ERR = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE1_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE1_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL = 48
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN
+ = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE2_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 53
+ ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE2_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE2_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE2_TX_CNTL2_O_PL_IORESET = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE2_TX_CNTL3_EO_PL_TDR_ENABLE = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE2_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE2_TX_FIR_MASK_PL_ERRS = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE2_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE2_TX_MODE1_PL_LANE_PDWN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE2_TX_MODE1_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE2_TX_MODE1_PL_LANE_QUIESCE = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE2_TX_MODE1_PL_LANE_QUIESCE_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE2_TX_MODE1_PL_PSAVE_REQ_DIS = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE2_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE2_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE2_TX_MODE1_PL_SPARE_MODE_0 = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE2_TX_MODE1_PL_SPARE_MODE_1 = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE2_TX_MODE1_PL_SPARE_MODE_2 = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE2_TX_MODE1_PL_SPARE_MODE_3 = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE2_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE2_TX_MODE2_PL_RXCAL = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE2_TX_MODE2_PL_UNLOAD_SEL = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE2_TX_MODE2_PL_UNLOAD_SEL_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE2_TX_STAT1_PL_LANE_BIST_ERR = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE2_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE2_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL = 48
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN
+ = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE3_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 53
+ ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE3_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE3_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE3_TX_CNTL2_O_PL_IORESET = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE3_TX_CNTL3_EO_PL_TDR_ENABLE = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE3_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE3_TX_FIR_MASK_PL_ERRS = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE3_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE3_TX_MODE1_PL_LANE_PDWN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE3_TX_MODE1_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE3_TX_MODE1_PL_LANE_QUIESCE = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE3_TX_MODE1_PL_LANE_QUIESCE_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE3_TX_MODE1_PL_PSAVE_REQ_DIS = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE3_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE3_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE3_TX_MODE1_PL_SPARE_MODE_0 = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE3_TX_MODE1_PL_SPARE_MODE_1 = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE3_TX_MODE1_PL_SPARE_MODE_2 = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE3_TX_MODE1_PL_SPARE_MODE_3 = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE3_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE3_TX_MODE2_PL_RXCAL = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE3_TX_MODE2_PL_UNLOAD_SEL = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE3_TX_MODE2_PL_UNLOAD_SEL_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE3_TX_STAT1_PL_LANE_BIST_ERR = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE3_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS0_SLICE3_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL = 48
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN
+ = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE0_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 53
+ ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE0_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE0_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE0_TX_CNTL2_O_PL_IORESET = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE0_TX_CNTL3_EO_PL_TDR_ENABLE = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE0_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE0_TX_FIR_MASK_PL_ERRS = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE0_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE0_TX_MODE1_PL_LANE_PDWN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE0_TX_MODE1_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE0_TX_MODE1_PL_LANE_QUIESCE = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE0_TX_MODE1_PL_LANE_QUIESCE_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE0_TX_MODE1_PL_PSAVE_REQ_DIS = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE0_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE0_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE0_TX_MODE1_PL_SPARE_MODE_0 = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE0_TX_MODE1_PL_SPARE_MODE_1 = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE0_TX_MODE1_PL_SPARE_MODE_2 = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE0_TX_MODE1_PL_SPARE_MODE_3 = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE0_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE0_TX_MODE2_PL_RXCAL = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE0_TX_MODE2_PL_UNLOAD_SEL = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE0_TX_MODE2_PL_UNLOAD_SEL_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE0_TX_STAT1_PL_LANE_BIST_ERR = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE0_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE0_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL = 48
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN
+ = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE1_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 53
+ ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE1_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE1_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE1_TX_CNTL2_O_PL_IORESET = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE1_TX_CNTL3_EO_PL_TDR_ENABLE = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE1_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE1_TX_FIR_MASK_PL_ERRS = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE1_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE1_TX_MODE1_PL_LANE_PDWN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE1_TX_MODE1_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE1_TX_MODE1_PL_LANE_QUIESCE = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE1_TX_MODE1_PL_LANE_QUIESCE_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE1_TX_MODE1_PL_PSAVE_REQ_DIS = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE1_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE1_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE1_TX_MODE1_PL_SPARE_MODE_0 = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE1_TX_MODE1_PL_SPARE_MODE_1 = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE1_TX_MODE1_PL_SPARE_MODE_2 = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE1_TX_MODE1_PL_SPARE_MODE_3 = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE1_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE1_TX_MODE2_PL_RXCAL = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE1_TX_MODE2_PL_UNLOAD_SEL = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE1_TX_MODE2_PL_UNLOAD_SEL_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE1_TX_STAT1_PL_LANE_BIST_ERR = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE1_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE1_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL = 48
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN
+ = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE2_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 53
+ ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE2_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE2_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE2_TX_CNTL2_O_PL_IORESET = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE2_TX_CNTL3_EO_PL_TDR_ENABLE = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE2_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE2_TX_FIR_MASK_PL_ERRS = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE2_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE2_TX_MODE1_PL_LANE_PDWN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE2_TX_MODE1_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE2_TX_MODE1_PL_LANE_QUIESCE = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE2_TX_MODE1_PL_LANE_QUIESCE_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE2_TX_MODE1_PL_PSAVE_REQ_DIS = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE2_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE2_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE2_TX_MODE1_PL_SPARE_MODE_0 = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE2_TX_MODE1_PL_SPARE_MODE_1 = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE2_TX_MODE1_PL_SPARE_MODE_2 = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE2_TX_MODE1_PL_SPARE_MODE_3 = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE2_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE2_TX_MODE2_PL_RXCAL = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE2_TX_MODE2_PL_UNLOAD_SEL = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE2_TX_MODE2_PL_UNLOAD_SEL_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE2_TX_STAT1_PL_LANE_BIST_ERR = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE2_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE2_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL = 48
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN
+ = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE3_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 53
+ ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE3_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE3_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE3_TX_CNTL2_O_PL_IORESET = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE3_TX_CNTL3_EO_PL_TDR_ENABLE = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE3_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE3_TX_FIR_MASK_PL_ERRS = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE3_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE3_TX_MODE1_PL_LANE_PDWN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE3_TX_MODE1_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE3_TX_MODE1_PL_LANE_QUIESCE = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE3_TX_MODE1_PL_LANE_QUIESCE_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE3_TX_MODE1_PL_PSAVE_REQ_DIS = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE3_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE3_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE3_TX_MODE1_PL_SPARE_MODE_0 = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE3_TX_MODE1_PL_SPARE_MODE_1 = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE3_TX_MODE1_PL_SPARE_MODE_2 = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE3_TX_MODE1_PL_SPARE_MODE_3 = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE3_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE3_TX_MODE2_PL_RXCAL = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE3_TX_MODE2_PL_UNLOAD_SEL = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE3_TX_MODE2_PL_UNLOAD_SEL_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE3_TX_STAT1_PL_LANE_BIST_ERR = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE3_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS1_SLICE3_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL = 48
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN
+ = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE0_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 53
+ ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE0_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE0_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE0_TX_CNTL2_O_PL_IORESET = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE0_TX_CNTL3_EO_PL_TDR_ENABLE = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE0_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE0_TX_FIR_MASK_PL_ERRS = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE0_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE0_TX_MODE1_PL_LANE_PDWN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE0_TX_MODE1_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE0_TX_MODE1_PL_LANE_QUIESCE = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE0_TX_MODE1_PL_LANE_QUIESCE_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE0_TX_MODE1_PL_PSAVE_REQ_DIS = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE0_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE0_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE0_TX_MODE1_PL_SPARE_MODE_0 = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE0_TX_MODE1_PL_SPARE_MODE_1 = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE0_TX_MODE1_PL_SPARE_MODE_2 = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE0_TX_MODE1_PL_SPARE_MODE_3 = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE0_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE0_TX_MODE2_PL_RXCAL = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE0_TX_MODE2_PL_UNLOAD_SEL = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE0_TX_MODE2_PL_UNLOAD_SEL_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE0_TX_STAT1_PL_LANE_BIST_ERR = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE0_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE0_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL = 48
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN
+ = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE1_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 53
+ ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE1_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE1_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE1_TX_CNTL2_O_PL_IORESET = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE1_TX_CNTL3_EO_PL_TDR_ENABLE = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE1_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE1_TX_FIR_MASK_PL_ERRS = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE1_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE1_TX_MODE1_PL_LANE_PDWN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE1_TX_MODE1_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE1_TX_MODE1_PL_LANE_QUIESCE = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE1_TX_MODE1_PL_LANE_QUIESCE_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE1_TX_MODE1_PL_PSAVE_REQ_DIS = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE1_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE1_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE1_TX_MODE1_PL_SPARE_MODE_0 = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE1_TX_MODE1_PL_SPARE_MODE_1 = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE1_TX_MODE1_PL_SPARE_MODE_2 = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE1_TX_MODE1_PL_SPARE_MODE_3 = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE1_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE1_TX_MODE2_PL_RXCAL = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE1_TX_MODE2_PL_UNLOAD_SEL = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE1_TX_MODE2_PL_UNLOAD_SEL_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE1_TX_STAT1_PL_LANE_BIST_ERR = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE1_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE1_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL = 48
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN
+ = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE2_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 53
+ ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE2_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE2_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE2_TX_CNTL2_O_PL_IORESET = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE2_TX_CNTL3_EO_PL_TDR_ENABLE = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE2_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE2_TX_FIR_MASK_PL_ERRS = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE2_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE2_TX_MODE1_PL_LANE_PDWN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE2_TX_MODE1_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE2_TX_MODE1_PL_LANE_QUIESCE = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE2_TX_MODE1_PL_LANE_QUIESCE_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE2_TX_MODE1_PL_PSAVE_REQ_DIS = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE2_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE2_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE2_TX_MODE1_PL_SPARE_MODE_0 = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE2_TX_MODE1_PL_SPARE_MODE_1 = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE2_TX_MODE1_PL_SPARE_MODE_2 = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE2_TX_MODE1_PL_SPARE_MODE_3 = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE2_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE2_TX_MODE2_PL_RXCAL = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE2_TX_MODE2_PL_UNLOAD_SEL = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE2_TX_MODE2_PL_UNLOAD_SEL_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE2_TX_STAT1_PL_LANE_BIST_ERR = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE2_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE2_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL = 48
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN
+ = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE3_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 53
+ ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE3_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE3_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE3_TX_CNTL2_O_PL_IORESET = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE3_TX_CNTL3_EO_PL_TDR_ENABLE = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE3_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE3_TX_FIR_MASK_PL_ERRS = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE3_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE3_TX_MODE1_PL_LANE_PDWN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE3_TX_MODE1_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE3_TX_MODE1_PL_LANE_QUIESCE = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE3_TX_MODE1_PL_LANE_QUIESCE_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE3_TX_MODE1_PL_PSAVE_REQ_DIS = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE3_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE3_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE3_TX_MODE1_PL_SPARE_MODE_0 = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE3_TX_MODE1_PL_SPARE_MODE_1 = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE3_TX_MODE1_PL_SPARE_MODE_2 = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE3_TX_MODE1_PL_SPARE_MODE_3 = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE3_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE3_TX_MODE2_PL_RXCAL = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE3_TX_MODE2_PL_UNLOAD_SEL = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE3_TX_MODE2_PL_UNLOAD_SEL_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE3_TX_STAT1_PL_LANE_BIST_ERR = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE3_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS2_SLICE3_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL = 48
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN
+ = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE0_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 53
+ ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE0_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE0_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE0_TX_CNTL2_O_PL_IORESET = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE0_TX_CNTL3_EO_PL_TDR_ENABLE = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE0_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE0_TX_FIR_MASK_PL_ERRS = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE0_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE0_TX_MODE1_PL_LANE_PDWN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE0_TX_MODE1_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE0_TX_MODE1_PL_LANE_QUIESCE = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE0_TX_MODE1_PL_LANE_QUIESCE_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE0_TX_MODE1_PL_PSAVE_REQ_DIS = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE0_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE0_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE0_TX_MODE1_PL_SPARE_MODE_0 = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE0_TX_MODE1_PL_SPARE_MODE_1 = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE0_TX_MODE1_PL_SPARE_MODE_2 = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE0_TX_MODE1_PL_SPARE_MODE_3 = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE0_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE0_TX_MODE2_PL_RXCAL = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE0_TX_MODE2_PL_UNLOAD_SEL = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE0_TX_MODE2_PL_UNLOAD_SEL_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE0_TX_STAT1_PL_LANE_BIST_ERR = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE0_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE0_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL = 48
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN
+ = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE1_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 53
+ ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE1_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE1_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE1_TX_CNTL2_O_PL_IORESET = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE1_TX_CNTL3_EO_PL_TDR_ENABLE = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE1_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE1_TX_FIR_MASK_PL_ERRS = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE1_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE1_TX_MODE1_PL_LANE_PDWN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE1_TX_MODE1_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE1_TX_MODE1_PL_LANE_QUIESCE = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE1_TX_MODE1_PL_LANE_QUIESCE_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE1_TX_MODE1_PL_PSAVE_REQ_DIS = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE1_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE1_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE1_TX_MODE1_PL_SPARE_MODE_0 = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE1_TX_MODE1_PL_SPARE_MODE_1 = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE1_TX_MODE1_PL_SPARE_MODE_2 = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE1_TX_MODE1_PL_SPARE_MODE_3 = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE1_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE1_TX_MODE2_PL_RXCAL = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE1_TX_MODE2_PL_UNLOAD_SEL = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE1_TX_MODE2_PL_UNLOAD_SEL_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE1_TX_STAT1_PL_LANE_BIST_ERR = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE1_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE1_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL = 48
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN
+ = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE2_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 53
+ ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE2_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE2_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE2_TX_CNTL2_O_PL_IORESET = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE2_TX_CNTL3_EO_PL_TDR_ENABLE = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE2_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE2_TX_FIR_MASK_PL_ERRS = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE2_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE2_TX_MODE1_PL_LANE_PDWN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE2_TX_MODE1_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE2_TX_MODE1_PL_LANE_QUIESCE = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE2_TX_MODE1_PL_LANE_QUIESCE_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE2_TX_MODE1_PL_PSAVE_REQ_DIS = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE2_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE2_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE2_TX_MODE1_PL_SPARE_MODE_0 = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE2_TX_MODE1_PL_SPARE_MODE_1 = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE2_TX_MODE1_PL_SPARE_MODE_2 = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE2_TX_MODE1_PL_SPARE_MODE_3 = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE2_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE2_TX_MODE2_PL_RXCAL = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE2_TX_MODE2_PL_UNLOAD_SEL = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE2_TX_MODE2_PL_UNLOAD_SEL_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE2_TX_STAT1_PL_LANE_BIST_ERR = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE2_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE2_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL = 48
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN
+ = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE3_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 53
+ ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE3_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE3_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE3_TX_CNTL2_O_PL_IORESET = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE3_TX_CNTL3_EO_PL_TDR_ENABLE = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE3_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE3_TX_FIR_MASK_PL_ERRS = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE3_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE3_TX_MODE1_PL_LANE_PDWN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE3_TX_MODE1_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE3_TX_MODE1_PL_LANE_QUIESCE = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE3_TX_MODE1_PL_LANE_QUIESCE_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE3_TX_MODE1_PL_PSAVE_REQ_DIS = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE3_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE3_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE3_TX_MODE1_PL_SPARE_MODE_0 = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE3_TX_MODE1_PL_SPARE_MODE_1 = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE3_TX_MODE1_PL_SPARE_MODE_2 = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE3_TX_MODE1_PL_SPARE_MODE_3 = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE3_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE3_TX_MODE2_PL_RXCAL = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE3_TX_MODE2_PL_UNLOAD_SEL = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE3_TX_MODE2_PL_UNLOAD_SEL_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE3_TX_STAT1_PL_LANE_BIST_ERR = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE3_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS3_SLICE3_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL = 48
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN
+ = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE0_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 53
+ ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE0_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE0_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE0_TX_CNTL2_O_PL_IORESET = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE0_TX_CNTL3_EO_PL_TDR_ENABLE = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE0_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE0_TX_FIR_MASK_PL_ERRS = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE0_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE0_TX_MODE1_PL_LANE_PDWN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE0_TX_MODE1_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE0_TX_MODE1_PL_LANE_QUIESCE = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE0_TX_MODE1_PL_LANE_QUIESCE_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE0_TX_MODE1_PL_PSAVE_REQ_DIS = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE0_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE0_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE0_TX_MODE1_PL_SPARE_MODE_0 = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE0_TX_MODE1_PL_SPARE_MODE_1 = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE0_TX_MODE1_PL_SPARE_MODE_2 = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE0_TX_MODE1_PL_SPARE_MODE_3 = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE0_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE0_TX_MODE2_PL_RXCAL = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE0_TX_MODE2_PL_UNLOAD_SEL = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE0_TX_MODE2_PL_UNLOAD_SEL_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE0_TX_STAT1_PL_LANE_BIST_ERR = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE0_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE0_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL = 48
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN
+ = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE1_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 53
+ ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE1_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE1_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE1_TX_CNTL2_O_PL_IORESET = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE1_TX_CNTL3_EO_PL_TDR_ENABLE = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE1_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE1_TX_FIR_MASK_PL_ERRS = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE1_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE1_TX_MODE1_PL_LANE_PDWN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE1_TX_MODE1_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE1_TX_MODE1_PL_LANE_QUIESCE = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE1_TX_MODE1_PL_LANE_QUIESCE_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE1_TX_MODE1_PL_PSAVE_REQ_DIS = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE1_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE1_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE1_TX_MODE1_PL_SPARE_MODE_0 = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE1_TX_MODE1_PL_SPARE_MODE_1 = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE1_TX_MODE1_PL_SPARE_MODE_2 = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE1_TX_MODE1_PL_SPARE_MODE_3 = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE1_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE1_TX_MODE2_PL_RXCAL = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE1_TX_MODE2_PL_UNLOAD_SEL = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE1_TX_MODE2_PL_UNLOAD_SEL_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE1_TX_STAT1_PL_LANE_BIST_ERR = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE1_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE1_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL = 48
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN
+ = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE2_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 53
+ ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE2_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE2_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE2_TX_CNTL2_O_PL_IORESET = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE2_TX_CNTL3_EO_PL_TDR_ENABLE = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE2_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE2_TX_FIR_MASK_PL_ERRS = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE2_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE2_TX_MODE1_PL_LANE_PDWN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE2_TX_MODE1_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE2_TX_MODE1_PL_LANE_QUIESCE = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE2_TX_MODE1_PL_LANE_QUIESCE_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE2_TX_MODE1_PL_PSAVE_REQ_DIS = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE2_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE2_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE2_TX_MODE1_PL_SPARE_MODE_0 = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE2_TX_MODE1_PL_SPARE_MODE_1 = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE2_TX_MODE1_PL_SPARE_MODE_2 = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE2_TX_MODE1_PL_SPARE_MODE_3 = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE2_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE2_TX_MODE2_PL_RXCAL = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE2_TX_MODE2_PL_UNLOAD_SEL = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE2_TX_MODE2_PL_UNLOAD_SEL_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE2_TX_STAT1_PL_LANE_BIST_ERR = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE2_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE2_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL = 48
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN
+ = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE3_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 53
+ ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE3_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE3_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE3_TX_CNTL2_O_PL_IORESET = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE3_TX_CNTL3_EO_PL_TDR_ENABLE = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE3_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE3_TX_FIR_MASK_PL_ERRS = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE3_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE3_TX_MODE1_PL_LANE_PDWN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE3_TX_MODE1_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE3_TX_MODE1_PL_LANE_QUIESCE = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE3_TX_MODE1_PL_LANE_QUIESCE_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE3_TX_MODE1_PL_PSAVE_REQ_DIS = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE3_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE3_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE3_TX_MODE1_PL_SPARE_MODE_0 = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE3_TX_MODE1_PL_SPARE_MODE_1 = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE3_TX_MODE1_PL_SPARE_MODE_2 = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE3_TX_MODE1_PL_SPARE_MODE_3 = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE3_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE3_TX_MODE2_PL_RXCAL = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE3_TX_MODE2_PL_UNLOAD_SEL = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE3_TX_MODE2_PL_UNLOAD_SEL_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE3_TX_STAT1_PL_LANE_BIST_ERR = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE3_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS4_SLICE3_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL = 48
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN
+ = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE0_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 53
+ ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE0_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE0_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE0_TX_CNTL2_O_PL_IORESET = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE0_TX_CNTL3_EO_PL_TDR_ENABLE = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE0_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE0_TX_FIR_MASK_PL_ERRS = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE0_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE0_TX_MODE1_PL_LANE_PDWN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE0_TX_MODE1_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE0_TX_MODE1_PL_LANE_QUIESCE = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE0_TX_MODE1_PL_LANE_QUIESCE_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE0_TX_MODE1_PL_PSAVE_REQ_DIS = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE0_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE0_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE0_TX_MODE1_PL_SPARE_MODE_0 = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE0_TX_MODE1_PL_SPARE_MODE_1 = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE0_TX_MODE1_PL_SPARE_MODE_2 = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE0_TX_MODE1_PL_SPARE_MODE_3 = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE0_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE0_TX_MODE2_PL_RXCAL = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE0_TX_MODE2_PL_UNLOAD_SEL = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE0_TX_MODE2_PL_UNLOAD_SEL_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE0_TX_STAT1_PL_LANE_BIST_ERR = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE0_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE0_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL = 48
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN
+ = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE1_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 53
+ ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE1_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE1_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE1_TX_CNTL2_O_PL_IORESET = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE1_TX_CNTL3_EO_PL_TDR_ENABLE = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE1_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE1_TX_FIR_MASK_PL_ERRS = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE1_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE1_TX_MODE1_PL_LANE_PDWN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE1_TX_MODE1_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE1_TX_MODE1_PL_LANE_QUIESCE = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE1_TX_MODE1_PL_LANE_QUIESCE_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE1_TX_MODE1_PL_PSAVE_REQ_DIS = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE1_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE1_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE1_TX_MODE1_PL_SPARE_MODE_0 = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE1_TX_MODE1_PL_SPARE_MODE_1 = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE1_TX_MODE1_PL_SPARE_MODE_2 = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE1_TX_MODE1_PL_SPARE_MODE_3 = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE1_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE1_TX_MODE2_PL_RXCAL = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE1_TX_MODE2_PL_UNLOAD_SEL = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE1_TX_MODE2_PL_UNLOAD_SEL_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE1_TX_STAT1_PL_LANE_BIST_ERR = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE1_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE1_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL = 48
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN
+ = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE2_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 53
+ ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE2_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE2_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE2_TX_CNTL2_O_PL_IORESET = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE2_TX_CNTL3_EO_PL_TDR_ENABLE = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE2_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE2_TX_FIR_MASK_PL_ERRS = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE2_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE2_TX_MODE1_PL_LANE_PDWN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE2_TX_MODE1_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE2_TX_MODE1_PL_LANE_QUIESCE = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE2_TX_MODE1_PL_LANE_QUIESCE_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE2_TX_MODE1_PL_PSAVE_REQ_DIS = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE2_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE2_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE2_TX_MODE1_PL_SPARE_MODE_0 = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE2_TX_MODE1_PL_SPARE_MODE_1 = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE2_TX_MODE1_PL_SPARE_MODE_2 = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE2_TX_MODE1_PL_SPARE_MODE_3 = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE2_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE2_TX_MODE2_PL_RXCAL = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE2_TX_MODE2_PL_UNLOAD_SEL = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE2_TX_MODE2_PL_UNLOAD_SEL_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE2_TX_STAT1_PL_LANE_BIST_ERR = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE2_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE2_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL = 48
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN
+ = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE3_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 53
+ ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE3_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE3_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE3_TX_CNTL2_O_PL_IORESET = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE3_TX_CNTL3_EO_PL_TDR_ENABLE = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE3_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE3_TX_FIR_MASK_PL_ERRS = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE3_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE3_TX_MODE1_PL_LANE_PDWN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE3_TX_MODE1_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE3_TX_MODE1_PL_LANE_QUIESCE = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE3_TX_MODE1_PL_LANE_QUIESCE_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE3_TX_MODE1_PL_PSAVE_REQ_DIS = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE3_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE3_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE3_TX_MODE1_PL_SPARE_MODE_0 = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE3_TX_MODE1_PL_SPARE_MODE_1 = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE3_TX_MODE1_PL_SPARE_MODE_2 = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE3_TX_MODE1_PL_SPARE_MODE_3 = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE3_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE3_TX_MODE2_PL_RXCAL = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE3_TX_MODE2_PL_UNLOAD_SEL = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE3_TX_MODE2_PL_UNLOAD_SEL_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE3_TX_STAT1_PL_LANE_BIST_ERR = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE3_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TXPACKS5_SLICE3_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTLSM_CNTL1_EO_PG_PSEG_PRE_EN = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTLSM_CNTL1_EO_PG_PSEG_PRE_EN_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTLSM_CNTL1_EO_PG_PSEG_PRE_SEL = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTLSM_CNTL1_EO_PG_PSEG_PRE_SEL_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTLSM_CNTL1_O_PG_PSEG_POST_EN = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTLSM_CNTL1_O_PG_PSEG_POST_EN_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTLSM_CNTL1_O_PG_PSEG_POST_SEL = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTLSM_CNTL1_O_PG_PSEG_POST_SEL_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTLSM_CNTL2_EO_PG_NSEG_PRE_EN = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTLSM_CNTL2_EO_PG_NSEG_PRE_EN_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTLSM_CNTL2_EO_PG_NSEG_PRE_SEL = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTLSM_CNTL2_EO_PG_NSEG_PRE_SEL_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTLSM_CNTL2_O_PG_NSEG_POST_EN = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTLSM_CNTL2_O_PG_NSEG_POST_EN_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTLSM_CNTL2_O_PG_NSEG_POST_SEL = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTLSM_CNTL2_O_PG_NSEG_POST_SEL_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTLSM_CNTL3_EO_PG_PSEG_MARGINPU_EN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTLSM_CNTL3_EO_PG_PSEG_MARGINPU_EN_LEN = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTLSM_CNTL3_EO_PG_PSEG_MARGINPD_EN = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTLSM_CNTL3_EO_PG_PSEG_MARGINPD_EN_LEN = 8 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTLSM_CNTL4_EO_PG_NSEG_MARGINPU_EN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTLSM_CNTL4_EO_PG_NSEG_MARGINPU_EN_LEN = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTLSM_CNTL4_EO_PG_NSEG_MARGINPD_EN = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTLSM_CNTL4_EO_PG_NSEG_MARGINPD_EN_LEN = 8 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTLSM_CNTL5_EO_PG_MARGINPU_SEL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTLSM_CNTL5_EO_PG_MARGINPU_SEL_LEN = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTLSM_CNTL5_EO_PG_MARGINPD_SEL = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTLSM_CNTL5_EO_PG_MARGINPD_SEL_LEN = 8 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTLSM_CNTL6_EO_PG_PSEG_MAIN_EN = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTLSM_CNTL6_EO_PG_PSEG_MAIN_EN_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTLSM_CNTL7_EO_PG_NSEG_MAIN_EN = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTLSM_CNTL7_EO_PG_NSEG_MAIN_EN_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTLSM_MODE1_EO_PG_SEG_TEST_MODE = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTLSM_MODE1_EO_PG_SEG_TEST_MODE_LEN = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTLSM_MODE1_EO_PG_FFE_BOOST_EN = 59 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTLSM_MODE1_EO_PG_SEG_TEST_LEAKAGE_CTRL = 61 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTLSM_SPARE_MODE_PG_CTL_SM_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTLSM_SPARE_MODE_PG_CTL_SM_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTLSM_SPARE_MODE_PG_CTL_SM_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTLSM_SPARE_MODE_PG_CTL_SM_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTLSM_SPARE_MODE_PG_CTL_SM_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTLSM_SPARE_MODE_PG_CTL_SM_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTLSM_SPARE_MODE_PG_CTL_SM_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTLSM_SPARE_MODE_PG_CTL_SM_7 = 55 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTLSM_STAT1_EO_PG_TX_BIST_DONE_RO_SIGNAL = 50 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTL_CNTL10_EO_PG_TDR_PULSE_WIDTH = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTL_CNTL10_EO_PG_TDR_PULSE_WIDTH_LEN = 8 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTL_CNTL2_EO_PG_ERR_INJ_A_FINE_SEL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTL_CNTL2_EO_PG_ERR_INJ_A_FINE_SEL_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTL_CNTL2_EO_PG_ERR_INJ_A_COARSE_SEL = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTL_CNTL2_EO_PG_ERR_INJ_A_COARSE_SEL_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTL_CNTL2_EO_PG_ERR_INJ_A_BER_SEL = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTL_CNTL2_EO_PG_ERR_INJ_A_BER_SEL_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTL_CNTL2_EO_PG_ERR_INJ_ENABLE = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTL_CNTL2_EO_PG_ERR_INJ_CLOCK_ENABLE = 62 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTL_CNTL3_EO_PG_ERR_INJ_B_FINE_SEL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTL_CNTL3_EO_PG_ERR_INJ_B_FINE_SEL_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTL_CNTL3_EO_PG_ERR_INJ_B_COARSE_SEL = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTL_CNTL3_EO_PG_ERR_INJ_B_COARSE_SEL_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTL_CNTL3_EO_PG_ERR_INJ_B_BER_SEL = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTL_CNTL3_EO_PG_ERR_INJ_B_BER_SEL_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTL_CNTL8_EO_PG_TDR_DAC_CNTL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTL_CNTL8_EO_PG_TDR_DAC_CNTL_LEN = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTL_CNTL8_EO_PG_TDR_PHASE_SEL = 57 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTL_CNTL9_EO_PG_TDR_PULSE_OFFSET = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTL_CNTL9_EO_PG_TDR_PULSE_OFFSET_LEN = 14 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTL_CNTLG1_EO_PG_DRV_DATA_PATTERN_GCRMSG = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTL_CNTLG1_EO_PG_DRV_DATA_PATTERN_GCRMSG_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTL_MODE1_EO_PG_CLKDIST_PDWN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTL_MODE1_EO_PG_CLKDIST_PDWN_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTL_MODE1_EO_PG_BIST_EN = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_CTL_MODE1_EO_PG_EXBIST_MODE = 52 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_FIR_ERROR_INJECT_PG_ERR_INJ = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_FIR_ERROR_INJECT_PG_ERR_INJ_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_FIR_MASK_PG_ERRS = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_FIR_MASK_PG_ERRS_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_FIR_MASK_PG_PL_ERR = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_FIR_PG_TX_PG_FIR_ERR_TX_SM_REGS_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_FIR_PG_TX_PG_FIR_ERR_GCR_BUFF_RO_SIGNAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_FIR_PG_TX_PG_FIR_ERR_GCRS_LD_SM_RO_SIGNAL = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_FIR_PG_TX_PG_FIR_ERR_GCRS_UNLD_SM_RO_SIGNAL = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_FIR_PG_TX_PG_FIR_ERR_CTL_REGS_RO_SIGNAL = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_FIR_PG_TX_PL_FIR_ERR_RO_SIGNAL = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_FIR_RESET_PG_CLR_PAR_ERRS = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_FIR_RESET_PG_RESET = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_ID1_PG_BUS_ID = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_ID1_PG_BUS_ID_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_SPARE_MODE_PG_0 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_SPARE_MODE_PG_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_SPARE_MODE_PG_2 = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_SPARE_MODE_PG_3 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_SPARE_MODE_PG_4 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_SPARE_MODE_PG_5 = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_SPARE_MODE_PG_6 = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_SPARE_MODE_PG_7 = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_SPARE_MODE_PG_8_9 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX0_TX_SPARE_MODE_PG_8_9_LEN = 2 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX_IMPCAL2_PB_TX_ZCAL_ANS_NOT_FOUND_ERROR_RO_SIGNAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX_IMPCAL2_PB_TX_ZCAL_ANS_RANGE_ERROR_RO_SIGNAL = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX_IMPCAL2_PB_TX_ZCAL_TEST_ENABLE_WO_PULSE_SLOW_SIGNAL = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX_IMPCAL2_PB_TX_ZCAL_TEST_STATUS_RO_SIGNAL = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX_IMPCAL2_PB_TX_ZCAL_TEST_DONE_RO_SIGNAL = 55 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX_IMPCAL_NVAL_PB_ZCAL_N = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX_IMPCAL_NVAL_PB_ZCAL_N_LEN = 9 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX_IMPCAL_PB_TX_ZCAL_REQ_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX_IMPCAL_PB_TX_ZCAL_DONE_RO_SIGNAL = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX_IMPCAL_PB_TX_ZCAL_ERROR_RO_SIGNAL = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX_IMPCAL_PB_TX_ZCAL_BUSY_RO_SIGNAL = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX_IMPCAL_PB_TX_ZCAL_FORCE_SAMPLE_WO_PULSE_SLOW_SIGNAL = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX_IMPCAL_PB_TX_ZCAL_CMP_OUT_RO_SIGNAL = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX_IMPCAL_PB_TX_ZCAL_SAMPLE_CNT_RO_SIGNAL = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX_IMPCAL_PB_TX_ZCAL_SAMPLE_CNT_RO_SIGNAL_LEN = 9 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX_IMPCAL_PVAL_PB_ZCAL_P = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX_IMPCAL_PVAL_PB_ZCAL_P_LEN = 9 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX_IMPCAL_P_4X_PB_ZCAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX_IMPCAL_P_4X_PB_ZCAL_LEN = 5 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX_IMPCAL_SWO1_PB_ZCAL_SWO_EN = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX_IMPCAL_SWO1_PB_ZCAL_SWO_CAL_SEGS = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX_IMPCAL_SWO1_PB_ZCAL_SWO_CMP_INV = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX_IMPCAL_SWO1_PB_ZCAL_SWO_CMP_OFFSET = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX_IMPCAL_SWO1_PB_ZCAL_SWO_CMP_RESET = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX_IMPCAL_SWO1_PB_ZCAL_SWO_POWERDOWN = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX_IMPCAL_SWO1_PB_ZCAL_SWO_TCOIL = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX_IMPCAL_SWO1_PB_ZCAL_RANGE_CHECK = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX_IMPCAL_SWO1_PB_ZCAL_CYA_DATA_INV = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX_IMPCAL_SWO1_PB_ZCAL_TEST_OVR_2R = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX_IMPCAL_SWO1_PB_ZCAL_TEST_OVR_1R = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX_IMPCAL_SWO1_PB_ZCAL_TEST_OVR_4X_SEG = 59 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX_IMPCAL_SWO1_PB_ZCAL_TEST_CLK_DIV = 60 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX_IMPCAL_SWO2_PB_ZCAL_SM_MIN_VAL = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX_IMPCAL_SWO2_PB_ZCAL_SM_MIN_VAL_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX_IMPCAL_SWO2_PB_ZCAL_SM_MAX_VAL = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_TX_IMPCAL_SWO2_PB_ZCAL_SM_MAX_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_MASK_REG_LINK0_TRAINED = 0
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_MASK_REG_LINK1_TRAINED = 1
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_MASK_REG_LINK0_OP_IRQ = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_MASK_REG_LINK1_OP_IRQ = 3 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_MASK_REG_LINK0_REPLAY_THRESHOLD = 4 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_MASK_REG_LINK1_REPLAY_THRESHOLD = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_MASK_REG_LINK0_CRC_ERROR = 6
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_MASK_REG_LINK1_CRC_ERROR = 7
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_MASK_REG_LINK0_NAK_RECEIVED =
+ 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_MASK_REG_LINK1_NAK_RECEIVED =
+ 9 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_MASK_REG_LINK0_REPLAY_BUFFER_FULL = 10 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_MASK_REG_LINK1_REPLAY_BUFFER_FULL = 11 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_MASK_REG_LINK0_SL_ECC_THRESHOLD = 12 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_MASK_REG_LINK1_SL_ECC_THRESHOLD = 13 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_MASK_REG_LINK0_SL_ECC_CORRECTABLE = 14 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_MASK_REG_LINK1_SL_ECC_CORRECTABLE = 15 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_MASK_REG_LINK0_SL_ECC_UE = 16
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_MASK_REG_LINK1_SL_ECC_UE = 17
+ ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_MASK_REG_LINK0_RETRAIN_THRESHOLD = 18 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_MASK_REG_LINK1_RETRAIN_THRESHOLD = 19 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_MASK_REG_LINK0_LOSS_BLOCK_ALIGN = 20 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_MASK_REG_LINK1_LOSS_BLOCK_ALIGN = 21 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_MASK_REG_LINK0_INVALID_BLOCK
+ = 22 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_MASK_REG_LINK1_INVALID_BLOCK
+ = 23 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_MASK_REG_LINK0_DESKEW_ERROR =
+ 24 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_MASK_REG_LINK1_DESKEW_ERROR =
+ 25 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_MASK_REG_LINK0_DESKEW_OVERFLOW = 26 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_MASK_REG_LINK1_DESKEW_OVERFLOW = 27 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_MASK_REG_LINK0_SW_RETRAIN =
+ 28 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_MASK_REG_LINK1_SW_RETRAIN =
+ 29 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_MASK_REG_LINK0_ACK_QUEUE_OVERFLOW = 30 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_MASK_REG_LINK1_ACK_QUEUE_OVERFLOW = 31 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_MASK_REG_LINK0_ACK_QUEUE_UNDERFLOW = 32 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_MASK_REG_LINK1_ACK_QUEUE_UNDERFLOW = 33 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_MASK_REG_LINK0_NUM_REPLAY =
+ 34 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_MASK_REG_LINK1_NUM_REPLAY =
+ 35 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_MASK_REG_LINK0_TRAINING_SET_RECEIVED = 36 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_MASK_REG_LINK1_TRAINING_SET_RECEIVED = 37 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_MASK_REG_LINK0_PRBS_SELECT_ERROR = 38 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_MASK_REG_LINK1_PRBS_SELECT_ERROR = 39 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_MASK_REG_LINK0_TCOMPLETE_BAD
+ = 40 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_MASK_REG_LINK1_TCOMPLETE_BAD
+ = 41 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_MASK_REG_LINK0_NO_SPARE = 42
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_MASK_REG_LINK1_NO_SPARE = 43
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_MASK_REG_LINK0_SPARE_DONE =
+ 44 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_MASK_REG_LINK1_SPARE_DONE =
+ 45 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_MASK_REG_LINK0_TOO_MANY_CRC_ERRORS = 46 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_MASK_REG_LINK1_TOO_MANY_CRC_ERRORS = 47 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_MASK_REG_LINK0_NPU_DLX_ERROR
+ = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_MASK_REG_LINK1_NPU_DLX_ERROR
+ = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_MASK_REG_LINKX_NPU_ERROR = 50
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_MASK_REG_OSC_SWITCH = 51 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_MASK_REG_LINK0_CORRECTABLE_ARRAY_ERROR = 52 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_MASK_REG_LINK1_CORRECTABLE_ARRAY_ERROR = 53 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_MASK_REG_LINK0_UNCORRECTABLE_ARRAY_ERROR = 54 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_MASK_REG_LINK1_UNCORRECTABLE_ARRAY_ERROR = 55 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_MASK_REG_LINK0_TRAINING_FAILED = 56 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_MASK_REG_LINK1_TRAINING_FAILED = 57 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_MASK_REG_LINK0_UNRECOVERABLE_ERROR = 58 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_MASK_REG_LINK1_UNRECOVERABLE_ERROR = 59 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_MASK_REG_LINK0_INTERNAL_ERROR
+ = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_MASK_REG_LINK1_INTERNAL_ERROR
+ = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_MASK_REG_SCOM_ERR_DUP = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_MASK_REG_SCOM_ERR = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_REG_LINK0_TRAINED = 0 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_REG_LINK1_TRAINED = 1 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_REG_LINK0_OP_IRQ = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_REG_LINK1_OP_IRQ = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_REG_LINK0_REPLAY_THRESHOLD =
+ 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_REG_LINK1_REPLAY_THRESHOLD =
+ 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_REG_LINK0_CRC_ERROR = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_REG_LINK1_CRC_ERROR = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_REG_LINK0_NAK_RECEIVED = 8
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_REG_LINK1_NAK_RECEIVED = 9
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_REG_LINK0_REPLAY_BUFFER_FULL
+ = 10 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_REG_LINK1_REPLAY_BUFFER_FULL
+ = 11 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_REG_LINK0_SL_ECC_THRESHOLD =
+ 12 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_REG_LINK1_SL_ECC_THRESHOLD =
+ 13 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_REG_LINK0_SL_ECC_CORRECTABLE
+ = 14 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_REG_LINK1_SL_ECC_CORRECTABLE
+ = 15 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_REG_LINK0_SL_ECC_UE = 16 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_REG_LINK1_SL_ECC_UE = 17 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_REG_LINK0_RETRAIN_THRESHOLD =
+ 18 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_REG_LINK1_RETRAIN_THRESHOLD =
+ 19 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_REG_LINK0_LOSS_BLOCK_ALIGN =
+ 20 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_REG_LINK1_LOSS_BLOCK_ALIGN =
+ 21 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_REG_LINK0_INVALID_BLOCK = 22
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_REG_LINK1_INVALID_BLOCK = 23
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_REG_LINK0_DESKEW_ERROR = 24
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_REG_LINK1_DESKEW_ERROR = 25
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_REG_LINK0_DESKEW_OVERFLOW =
+ 26 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_REG_LINK1_DESKEW_OVERFLOW =
+ 27 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_REG_LINK0_SW_RETRAIN = 28 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_REG_LINK1_SW_RETRAIN = 29 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_REG_LINK0_ACK_QUEUE_OVERFLOW
+ = 30 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_REG_LINK1_ACK_QUEUE_OVERFLOW
+ = 31 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_REG_LINK0_ACK_QUEUE_UNDERFLOW
+ = 32 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_REG_LINK1_ACK_QUEUE_UNDERFLOW
+ = 33 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_REG_LINK0_NUM_REPLAY = 34 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_REG_LINK1_NUM_REPLAY = 35 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_REG_LINK0_TRAINING_SET_RECEIVED = 36 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_REG_LINK1_TRAINING_SET_RECEIVED = 37 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_REG_LINK0_PRBS_SELECT_ERROR =
+ 38 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_REG_LINK1_PRBS_SELECT_ERROR =
+ 39 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_REG_LINK0_TCOMPLETE_BAD = 40
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_REG_LINK1_TCOMPLETE_BAD = 41
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_REG_LINK0_NO_SPARE = 42 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_REG_LINK1_NO_SPARE = 43 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_REG_LINK0_SPARE_DONE = 44 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_REG_LINK1_SPARE_DONE = 45 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_REG_LINK0_TOO_MANY_CRC_ERRORS
+ = 46 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_REG_LINK1_TOO_MANY_CRC_ERRORS
+ = 47 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_REG_LINK0_NPU_DLX_ERROR = 48
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_REG_LINK1_NPU_DLX_ERROR = 49
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_REG_LINKX_NPU_ERROR = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_REG_OSC_SWITCH = 51 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_REG_LINK0_CORRECTABLE_ARRAY_ERROR = 52 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_REG_LINK1_CORRECTABLE_ARRAY_ERROR = 53 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_REG_LINK0_UNCORRECTABLE_ARRAY_ERROR = 54 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_REG_LINK1_UNCORRECTABLE_ARRAY_ERROR = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_REG_LINK0_TRAINING_FAILED =
+ 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_REG_LINK1_TRAINING_FAILED =
+ 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_REG_LINK0_UNRECOVERABLE_ERROR
+ = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_REG_LINK1_UNRECOVERABLE_ERROR
+ = 59 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_REG_LINK0_INTERNAL_ERROR = 60
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_REG_LINK1_INTERNAL_ERROR = 61
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_REG_SCOM_ERR_DUP = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_PB_IOOL_FIR_REG_SCOM_ERR = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_CONFIG_LINK_PAIR = 0 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_CONFIG_DISABLE_SL_ECC = 1 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_CONFIG_CRC_LANE_ID = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_CONFIG_EDPL_LANE_ID = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_CONFIG_SL_UE_CRC_ERR = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_CONFIG_REPORT_SL_CHKBIT_ERR = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_CONFIG_BW_SAMPLE_SIZE = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_CONFIG_BW_WINDOW_SIZE = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_CONFIG_UNUSED1 = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_CONFIG_UNUSED1_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_CONFIG_PACKET_DELAY_LIMIT = 11 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_CONFIG_PACKET_DELAY_LIMIT_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_CONFIG_TDM_DELAY = 16 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_CONFIG_TDM_DELAY_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_CONFIG_AUTO_TDM_TX = 20 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_CONFIG_AUTO_TDM_RX = 21 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_CONFIG_AUTO_TDM_AND_NOT_OR = 22 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_CONFIG_UNUSED2 = 23 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_CONFIG_AUTO_TDM_BW_DIFF = 24 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_CONFIG_AUTO_TDM_BW_DIFF_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_CONFIG_AUTO_TDM_ERROR_RATE = 28 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_CONFIG_AUTO_TDM_ERROR_RATE_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_CONFIG_AUTO_TDM_EXIT_RATE = 32 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_CONFIG_AUTO_TDM_EXIT_RATE_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_CONFIG_UNUSED3 = 36 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_CONFIG_UNUSED3_LEN = 12 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_CONFIG_TIMEOUT = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_CONFIG_TIMEOUT_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_CONFIG_TIMER_1US = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_CONFIG_TIMER_1US_LEN = 12 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_CONTROL_LINK0_PHY_TRAINING = 0 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_CONTROL_LINK0_STARTUP = 1 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_CONTROL_LINK0_HOLD_PATT_A = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_CONTROL_LINK0_HOLD_PATT_B = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_CONTROL_LINK0_RUN_LANE_DISABLE = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_CONTROL_LINK0_RUN_LANE_OVERRIDE = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_CONTROL_LINK0_IGNORE_PHY = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_CONTROL_LINK0_IGNORE_FENCE = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_CONTROL_LINK0_ERR_INJ_COMMAND = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_CONTROL_LINK0_ERR_INJ_COMMAND_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_CONTROL_LINK0_ERR_INJ_COMMAND_LANES = 12 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_CONTROL_LINK0_ERR_INJ_COMMAND_LANES_LEN = 12 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_CONTROL_UNUSED0 = 24 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_CONTROL_UNUSED0_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_CONTROL_LINK0_COMMAND = 28 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_CONTROL_LINK0_COMMAND_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_CONTROL_LINK1_PHY_TRAINING = 32 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_CONTROL_LINK1_STARTUP = 33 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_CONTROL_LINK1_HOLD_PATT_A = 34 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_CONTROL_LINK1_HOLD_PATT_B = 35 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_CONTROL_LINK1_RUN_LANE_DISABLE = 36 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_CONTROL_LINK1_RUN_LANE_OVERRIDE = 37 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_CONTROL_LINK1_IGNORE_PHY = 38 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_CONTROL_LINK1_IGNORE_FENCE = 39 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_CONTROL_LINK1_ERR_INJ_COMMAND = 40 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_CONTROL_LINK1_ERR_INJ_COMMAND_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_CONTROL_LINK1_ERR_INJ_COMMAND_LANES = 44 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_CONTROL_LINK1_ERR_INJ_COMMAND_LANES_LEN = 12 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_CONTROL_UNUSED1 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_CONTROL_UNUSED1_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_CONTROL_LINK1_COMMAND = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_CONTROL_LINK1_COMMAND_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_DLL_STATUS_LINK0_CURRENT_STATE = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_DLL_STATUS_LINK0_CURRENT_STATE_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_DLL_STATUS_LINK0_PRIOR_STATE = 12 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_DLL_STATUS_LINK0_PRIOR_STATE_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_DLL_STATUS_LINK0_OPTICS_RST_B = 16 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_DLL_STATUS_LINK0_OPTICS_IRQ = 17 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_DLL_STATUS_LINK0_TRAINING = 18 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_DLL_STATUS_LINK0_MAX_PKT_TIMER = 19 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_DLL_STATUS_LINK0_MAX_PKT_TIMER_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_DLL_STATUS_LINK1_CURRENT_STATE = 28 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_DLL_STATUS_LINK1_CURRENT_STATE_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_DLL_STATUS_LINK1_PRIOR_STATE = 36 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_DLL_STATUS_LINK1_PRIOR_STATE_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_DLL_STATUS_LINK1_OPTICS_RST_B = 40 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_DLL_STATUS_LINK1_OPTICS_IRQ = 41 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_DLL_STATUS_LINK1_TRAINING = 42 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_DLL_STATUS_LINK1_MAX_PKT_TIMER = 43 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_DLL_STATUS_LINK1_MAX_PKT_TIMER_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_DLL_STATUS_LINK0_LINK_CAP_VALID = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_DLL_STATUS_LINK1_LINK_CAP_VALID = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_ERR_INJ_LFSR_LFSR = 0 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_ERR_INJ_LFSR_LFSR_LEN = 61 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_FIR_WOF_REG_WOF = 0 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_FIR_WOF_REG_WOF_LEN = 64 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LAT_MEASURE_LINK0_ROUND_TRIP_VALID = 0 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LAT_MEASURE_LINK0_ROUND_TRIP = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LAT_MEASURE_LINK0_ROUND_TRIP_LEN = 10 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LAT_MEASURE_LINK1_ROUND_TRIP_VALID = 12 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LAT_MEASURE_LINK1_ROUND_TRIP = 14 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LAT_MEASURE_LINK1_ROUND_TRIP_LEN = 10 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LAT_MEASURE_LOCAL_LATENCY_DIFFERENCE_VALID = 24 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LAT_MEASURE_LOCAL_LATENCY_LONGER_LINK = 25 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LAT_MEASURE_LOCAL_LATENCY_DIFFERENCE = 29 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LAT_MEASURE_LOCAL_LATENCY_DIFFERENCE_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LAT_MEASURE_REMOTE_LATENCY_DIFFERENCE_VALID = 36 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LAT_MEASURE_REMOTE_LATENCY_LONGER_LINK = 37 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LAT_MEASURE_REMOTE_LATENCY_DIFFERENCE = 41 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LAT_MEASURE_REMOTE_LATENCY_DIFFERENCE_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LAT_MEASURE_LINK0_TOD_LATENCY = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LAT_MEASURE_LINK0_TOD_LATENCY_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LAT_MEASURE_LINK1_TOD_LATENCY = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LAT_MEASURE_LINK1_TOD_LATENCY_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_EDPL_STATUS_ERROR_COUNT_0 = 0 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_EDPL_STATUS_ERROR_COUNT_0_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_EDPL_STATUS_ERROR_COUNT_1 = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_EDPL_STATUS_ERROR_COUNT_1_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_EDPL_STATUS_ERROR_COUNT_2 = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_EDPL_STATUS_ERROR_COUNT_2_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_EDPL_STATUS_ERROR_COUNT_3 = 12 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_EDPL_STATUS_ERROR_COUNT_3_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_EDPL_STATUS_ERROR_COUNT_4 = 16 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_EDPL_STATUS_ERROR_COUNT_4_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_EDPL_STATUS_ERROR_COUNT_5 = 20 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_EDPL_STATUS_ERROR_COUNT_5_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_EDPL_STATUS_ERROR_COUNT_6 = 24 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_EDPL_STATUS_ERROR_COUNT_6_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_EDPL_STATUS_ERROR_COUNT_7 = 28 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_EDPL_STATUS_ERROR_COUNT_7_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_EDPL_STATUS_ERROR_COUNT_8 = 32 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_EDPL_STATUS_ERROR_COUNT_8_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_EDPL_STATUS_ERROR_COUNT_9 = 36 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_EDPL_STATUS_ERROR_COUNT_9_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_EDPL_STATUS_ERROR_COUNT_10 = 40 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_EDPL_STATUS_ERROR_COUNT_10_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_EDPL_STATUS_ERROR_COUNT_11 = 44 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_EDPL_STATUS_ERROR_COUNT_11_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_ERROR_STATUS_RESET_KEEPER = 0 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_ERROR_STATUS_CE = 1 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_ERROR_STATUS_CE_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_ERROR_STATUS_UE = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_ERROR_STATUS_UE_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_ERROR_STATUS_OSC = 12 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_ERROR_STATUS_OSC_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_ERROR_STATUS_TRAIN = 16 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_ERROR_STATUS_TRAIN_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_ERROR_STATUS_UNRECOV = 24 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_ERROR_STATUS_UNRECOV_LEN = 13 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_ERROR_STATUS_INTERNAL = 40 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_ERROR_STATUS_INTERNAL_LEN = 22 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_INFO_MAX_TIMEOUT = 0 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_INFO_MAX_TIMEOUT_LEN = 16 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_INFO_FRAME_CAP_VALID = 16 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_INFO_FRAME_CAP_INST = 17 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_INFO_FRAME_CAP_ADDR = 18 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_INFO_FRAME_CAP_ADDR_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_INFO_FRAME_CAP_SYN = 24 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_INFO_FRAME_CAP_SYN_LEN = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_INFO_REPLAY_CAP_VALID = 32 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_INFO_REPLAY_CAP_INST = 33 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_INFO_REPLAY_CAP_INST_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_INFO_REPLAY_CAP_ADDR = 35 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_INFO_REPLAY_CAP_ADDR_LEN = 9 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_INFO_REPLAY_CAP_SYN = 44 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_INFO_REPLAY_CAP_SYN_LEN = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_INFO_ACK_FIFO_CAP_VALID = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_INFO_ACK_FIFO_CAP_ADDR = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_INFO_ACK_FIFO_CAP_ADDR_LEN = 9 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_QUALITY_TX_BW = 1 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_QUALITY_TX_BW_LEN = 11 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_QUALITY_RX_BW = 13 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_QUALITY_RX_BW_LEN = 11 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_QUALITY_ERROR_RATE = 25 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_QUALITY_ERROR_RATE_LEN = 23 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_QUALITY_SPARE_COUNTER_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_QUALITY_SPARE_COUNTER_1_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_QUALITY_SPARE_COUNTER_2 = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_QUALITY_SPARE_COUNTER_2_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_RX_LANE_CONTROL_DISABLED = 0 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_RX_LANE_CONTROL_DISABLED_LEN = 12 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_RX_LANE_CONTROL_BRINGUP = 12 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_RX_LANE_CONTROL_BRINGUP_LEN = 12 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_RX_LANE_CONTROL_SPARED = 24 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_RX_LANE_CONTROL_SPARED_LEN = 12 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_RX_LANE_CONTROL_LOCKED = 36 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_RX_LANE_CONTROL_LOCKED_LEN = 12 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_RX_LANE_CONTROL_FAILED = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_RX_LANE_CONTROL_FAILED_LEN = 12 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_SYN_CAPTURE_LINK_CAP_CRC = 0 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_SYN_CAPTURE_LINK_CAP_CRC_LEN = 36 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_SYN_CAPTURE_LINK_CAP_SLECC_SYN0 = 36 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_SYN_CAPTURE_LINK_CAP_SLECC_SYN0_LEN = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_SYN_CAPTURE_LINK_CAP_SLECC_SYN1 = 44 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_SYN_CAPTURE_LINK_CAP_SLECC_SYN1_LEN = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_SYN_CAPTURE_LINK_CAP_SLECC_SYN2 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_SYN_CAPTURE_LINK_CAP_SLECC_SYN2_LEN = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_SYN_CAPTURE_LINK_CAP_CRC_LANE = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_SYN_CAPTURE_LINK_CAP_CRC_LANE_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_TX_LANE_CONTROL_LANE00 = 0 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_TX_LANE_CONTROL_LANE00_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_TX_LANE_CONTROL_LANE01 = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_TX_LANE_CONTROL_LANE01_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_TX_LANE_CONTROL_LANE02 = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_TX_LANE_CONTROL_LANE02_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_TX_LANE_CONTROL_LANE03 = 12 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_TX_LANE_CONTROL_LANE03_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_TX_LANE_CONTROL_LANE04 = 16 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_TX_LANE_CONTROL_LANE04_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_TX_LANE_CONTROL_LANE05 = 20 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_TX_LANE_CONTROL_LANE05_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_TX_LANE_CONTROL_LANE06 = 24 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_TX_LANE_CONTROL_LANE06_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_TX_LANE_CONTROL_LANE07 = 28 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_TX_LANE_CONTROL_LANE07_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_TX_LANE_CONTROL_LANE08 = 32 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_TX_LANE_CONTROL_LANE08_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_TX_LANE_CONTROL_LANE09 = 36 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_TX_LANE_CONTROL_LANE09_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_TX_LANE_CONTROL_LANE10 = 40 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_TX_LANE_CONTROL_LANE10_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_TX_LANE_CONTROL_LANE11 = 44 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_TX_LANE_CONTROL_LANE11_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_TX_LANE_CONTROL_FAILED = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK0_TX_LANE_CONTROL_FAILED_LEN = 12 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_EDPL_STATUS_ERROR_COUNT_0 = 0 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_EDPL_STATUS_ERROR_COUNT_0_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_EDPL_STATUS_ERROR_COUNT_1 = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_EDPL_STATUS_ERROR_COUNT_1_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_EDPL_STATUS_ERROR_COUNT_2 = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_EDPL_STATUS_ERROR_COUNT_2_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_EDPL_STATUS_ERROR_COUNT_3 = 12 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_EDPL_STATUS_ERROR_COUNT_3_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_EDPL_STATUS_ERROR_COUNT_4 = 16 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_EDPL_STATUS_ERROR_COUNT_4_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_EDPL_STATUS_ERROR_COUNT_5 = 20 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_EDPL_STATUS_ERROR_COUNT_5_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_EDPL_STATUS_ERROR_COUNT_6 = 24 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_EDPL_STATUS_ERROR_COUNT_6_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_EDPL_STATUS_ERROR_COUNT_7 = 28 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_EDPL_STATUS_ERROR_COUNT_7_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_EDPL_STATUS_ERROR_COUNT_8 = 32 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_EDPL_STATUS_ERROR_COUNT_8_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_EDPL_STATUS_ERROR_COUNT_9 = 36 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_EDPL_STATUS_ERROR_COUNT_9_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_EDPL_STATUS_ERROR_COUNT_10 = 40 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_EDPL_STATUS_ERROR_COUNT_10_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_EDPL_STATUS_ERROR_COUNT_11 = 44 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_EDPL_STATUS_ERROR_COUNT_11_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_ERROR_STATUS_RESET_KEEPER = 0 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_ERROR_STATUS_CE = 1 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_ERROR_STATUS_CE_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_ERROR_STATUS_UE = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_ERROR_STATUS_UE_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_ERROR_STATUS_OSC = 12 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_ERROR_STATUS_OSC_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_ERROR_STATUS_TRAIN = 16 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_ERROR_STATUS_TRAIN_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_ERROR_STATUS_UNRECOV = 24 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_ERROR_STATUS_UNRECOV_LEN = 13 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_ERROR_STATUS_INTERNAL = 40 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_ERROR_STATUS_INTERNAL_LEN = 22 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_INFO_MAX_TIMEOUT = 0 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_INFO_MAX_TIMEOUT_LEN = 16 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_INFO_FRAME_CAP_VALID = 16 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_INFO_FRAME_CAP_INST = 17 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_INFO_FRAME_CAP_ADDR = 18 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_INFO_FRAME_CAP_ADDR_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_INFO_FRAME_CAP_SYN = 24 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_INFO_FRAME_CAP_SYN_LEN = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_INFO_REPLAY_CAP_VALID = 32 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_INFO_REPLAY_CAP_INST = 33 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_INFO_REPLAY_CAP_INST_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_INFO_REPLAY_CAP_ADDR = 35 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_INFO_REPLAY_CAP_ADDR_LEN = 9 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_INFO_REPLAY_CAP_SYN = 44 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_INFO_REPLAY_CAP_SYN_LEN = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_INFO_ACK_FIFO_CAP_VALID = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_INFO_ACK_FIFO_CAP_ADDR = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_INFO_ACK_FIFO_CAP_ADDR_LEN = 9 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_QUALITY_TX_BW = 1 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_QUALITY_TX_BW_LEN = 11 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_QUALITY_RX_BW = 13 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_QUALITY_RX_BW_LEN = 11 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_QUALITY_ERROR_RATE = 25 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_QUALITY_ERROR_RATE_LEN = 23 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_QUALITY_SPARE_COUNTER_1 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_QUALITY_SPARE_COUNTER_1_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_QUALITY_SPARE_COUNTER_2 = 57 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_QUALITY_SPARE_COUNTER_2_LEN = 7 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_RX_LANE_CONTROL_DISABLED = 0 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_RX_LANE_CONTROL_DISABLED_LEN = 12 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_RX_LANE_CONTROL_BRINGUP = 12 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_RX_LANE_CONTROL_BRINGUP_LEN = 12 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_RX_LANE_CONTROL_SPARED = 24 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_RX_LANE_CONTROL_SPARED_LEN = 12 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_RX_LANE_CONTROL_LOCKED = 36 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_RX_LANE_CONTROL_LOCKED_LEN = 12 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_RX_LANE_CONTROL_FAILED = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_RX_LANE_CONTROL_FAILED_LEN = 12 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_SYN_CAPTURE_LINK_CAP_CRC = 0 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_SYN_CAPTURE_LINK_CAP_CRC_LEN = 36 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_SYN_CAPTURE_LINK_CAP_SLECC_SYN0 = 36 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_SYN_CAPTURE_LINK_CAP_SLECC_SYN0_LEN = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_SYN_CAPTURE_LINK_CAP_SLECC_SYN1 = 44 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_SYN_CAPTURE_LINK_CAP_SLECC_SYN1_LEN = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_SYN_CAPTURE_LINK_CAP_SLECC_SYN2 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_SYN_CAPTURE_LINK_CAP_SLECC_SYN2_LEN = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_SYN_CAPTURE_LINK_CAP_CRC_LANE = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_SYN_CAPTURE_LINK_CAP_CRC_LANE_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_TX_LANE_CONTROL_LANE00 = 0 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_TX_LANE_CONTROL_LANE00_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_TX_LANE_CONTROL_LANE01 = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_TX_LANE_CONTROL_LANE01_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_TX_LANE_CONTROL_LANE02 = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_TX_LANE_CONTROL_LANE02_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_TX_LANE_CONTROL_LANE03 = 12 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_TX_LANE_CONTROL_LANE03_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_TX_LANE_CONTROL_LANE04 = 16 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_TX_LANE_CONTROL_LANE04_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_TX_LANE_CONTROL_LANE05 = 20 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_TX_LANE_CONTROL_LANE05_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_TX_LANE_CONTROL_LANE06 = 24 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_TX_LANE_CONTROL_LANE06_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_TX_LANE_CONTROL_LANE07 = 28 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_TX_LANE_CONTROL_LANE07_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_TX_LANE_CONTROL_LANE08 = 32 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_TX_LANE_CONTROL_LANE08_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_TX_LANE_CONTROL_LANE09 = 36 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_TX_LANE_CONTROL_LANE09_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_TX_LANE_CONTROL_LANE10 = 40 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_TX_LANE_CONTROL_LANE10_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_TX_LANE_CONTROL_LANE11 = 44 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_TX_LANE_CONTROL_LANE11_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_TX_LANE_CONTROL_FAILED = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_LINK1_TX_LANE_CONTROL_FAILED_LEN = 12 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_MISC_ERROR_STATUS_RESET_KEEPER = 0 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_MISC_ERROR_STATUS_LINKX = 1 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_MISC_ERROR_STATUS_LINKX_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_MISC_ERROR_STATUS_DLX0 = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_MISC_ERROR_STATUS_DLX0_LEN = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_MISC_ERROR_STATUS_DLX1 = 16 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_MISC_ERROR_STATUS_DLX1_LEN = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_MISC_ERROR_STATUS_OLL = 24 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_MISC_ERROR_STATUS_OLL_LEN = 16 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_MISC_ERROR_STATUS_ODL = 44 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_MISC_ERROR_STATUS_ODL_LEN = 16 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_OPTICAL_CONFIG_DISABLE_BAD_LANE_COUNT = 0 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_OPTICAL_CONFIG_DISABLE_CLEAR_BAD_LANE_COUNT = 1 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_OPTICAL_CONFIG_LINK_FAIL_NO_SPARE = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_OPTICAL_CONFIG_LINK_FAIL_CRC_ERROR = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_OPTICAL_CONFIG_BAD_LANE_DURATION = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_OPTICAL_CONFIG_BAD_LANE_DURATION_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_OPTICAL_CONFIG_OPT_UNUSED2 = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_OPTICAL_CONFIG_BAD_LANE_MAX = 9 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_OPTICAL_CONFIG_BAD_LANE_MAX_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_OPTICAL_CONFIG_DISABLE_LINK_FAIL_COUNT = 16 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_OPTICAL_CONFIG_OPT_UNUSED3 = 17 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_OPTICAL_CONFIG_OPT_UNUSED3_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_OPTICAL_CONFIG_LINK_FAIL_DURATION = 20 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_OPTICAL_CONFIG_LINK_FAIL_DURATION_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_OPTICAL_CONFIG_OPT_UNUSED4 = 24 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_OPTICAL_CONFIG_LINK_FAIL_MAX = 25 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_OPTICAL_CONFIG_LINK_FAIL_MAX_LEN = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_OPTICAL_CONFIG_CLEAR_LINK_FAIL_COUNTER = 32 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_OPTICAL_CONFIG_CLEAR_BAD_LANE_COUNTER = 33 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_OPTICAL_CONFIG_OPT_UNUSED5 = 34 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_OPTICAL_CONFIG_OPT_UNUSED5_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_OPTICAL_CONFIG_ELEVEN_LANE_MODE = 37 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_OPTICAL_CONFIG_LINK0_ELEVEN_LANE_SHIFT = 38 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_OPTICAL_CONFIG_LINK1_ELEVEN_LANE_SHIFT = 39 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_OPTICAL_CONFIG_LINK0_RX_LANE_SWAP = 40 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_OPTICAL_CONFIG_LINK0_TX_LANE_SWAP = 41 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_OPTICAL_CONFIG_LINK1_RX_LANE_SWAP = 42 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_OPTICAL_CONFIG_LINK1_TX_LANE_SWAP = 43 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_OPTICAL_CONFIG_ACK_QUEUE_LOW = 44 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_OPTICAL_CONFIG_ACK_QUEUE_LOW_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_OPTICAL_CONFIG_ACK_QUEUE_START = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_OPTICAL_CONFIG_ACK_QUEUE_START_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_OPTICAL_CONFIG_ACK_QUEUE_HIGH = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_OPTICAL_CONFIG_ACK_QUEUE_HIGH_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_OPTICAL_CONFIG_REPLAY_BUFFER_SIZE = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_OPTICAL_CONFIG_REPLAY_BUFFER_SIZE_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_OPTICAL_CONFIG_OPT_UNUSED6 = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_OPTICAL_CONFIG_FAST_ASYNC_CROSS = 59 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_OPTICAL_CONFIG_RECAL_ABORT_TIMEOUT = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_OPTICAL_CONFIG_RECAL_ABORT_TIMEOUT_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_COUNTERS_0_PERFMON_COUNTER = 0 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_COUNTERS_0_PERFMON_COUNTER_LEN = 16 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_COUNTERS_0_PERFMON_COUNTER_1 = 16 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_COUNTERS_0_PERFMON_COUNTER_1_LEN = 16 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_COUNTERS_0_PERFMON_COUNTER_2 = 32 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_COUNTERS_0_PERFMON_COUNTER_2_LEN = 16 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_COUNTERS_0_PERFMON_COUNTER_3 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_COUNTERS_0_PERFMON_COUNTER_3_LEN = 16 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_COUNTERS_1_PERFMON_COUNTER_4 = 0 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_COUNTERS_1_PERFMON_COUNTER_4_LEN = 16 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_COUNTERS_1_PERFMON_COUNTER_5 = 16 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_COUNTERS_1_PERFMON_COUNTER_5_LEN = 16 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_COUNTERS_1_PERFMON_COUNTER_6 = 32 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_COUNTERS_1_PERFMON_COUNTER_6_LEN = 16 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_COUNTERS_1_PERFMON_COUNTER_7 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_COUNTERS_1_PERFMON_COUNTER_7_LEN = 16 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_SEL_CONFIG_SELECT_0 = 0 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_SEL_CONFIG_SELECT_0_LEN = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_SEL_CONFIG_SELECT_1 = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_SEL_CONFIG_SELECT_1_LEN = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_SEL_CONFIG_SELECT_2 = 16 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_SEL_CONFIG_SELECT_2_LEN = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_SEL_CONFIG_SELECT_3 = 24 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_SEL_CONFIG_SELECT_3_LEN = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_SEL_CONFIG_SELECT_4 = 32 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_SEL_CONFIG_SELECT_4_LEN = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_SEL_CONFIG_SELECT_5 = 40 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_SEL_CONFIG_SELECT_5_LEN = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_SEL_CONFIG_SELECT_6 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_SEL_CONFIG_SELECT_6_LEN = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_SEL_CONFIG_SELECT_7 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_SEL_CONFIG_SELECT_7_LEN = 8 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_TRACE_CONFIG_ENABLE_0 = 0 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_TRACE_CONFIG_ENABLE_0_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_TRACE_CONFIG_ENABLE_1 = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_TRACE_CONFIG_ENABLE_1_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_TRACE_CONFIG_ENABLE_2 = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_TRACE_CONFIG_ENABLE_2_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_TRACE_CONFIG_ENABLE_3 = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_TRACE_CONFIG_ENABLE_3_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_TRACE_CONFIG_ENABLE_4 = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_TRACE_CONFIG_ENABLE_4_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_TRACE_CONFIG_ENABLE_5 = 10 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_TRACE_CONFIG_ENABLE_5_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_TRACE_CONFIG_ENABLE_6 = 12 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_TRACE_CONFIG_ENABLE_6_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_TRACE_CONFIG_ENABLE_7 = 14 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_TRACE_CONFIG_ENABLE_7_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_TRACE_CONFIG_SIZE_0 = 16 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_TRACE_CONFIG_SIZE_0_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_TRACE_CONFIG_SIZE_1 = 18 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_TRACE_CONFIG_SIZE_1_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_TRACE_CONFIG_SIZE_2 = 20 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_TRACE_CONFIG_SIZE_2_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_TRACE_CONFIG_SIZE_3 = 22 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_TRACE_CONFIG_SIZE_3_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_TRACE_CONFIG_SIZE_4 = 24 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_TRACE_CONFIG_SIZE_4_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_TRACE_CONFIG_SIZE_5 = 26 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_TRACE_CONFIG_SIZE_5_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_TRACE_CONFIG_SIZE_6 = 28 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_TRACE_CONFIG_SIZE_6_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_TRACE_CONFIG_SIZE_7 = 30 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_TRACE_CONFIG_SIZE_7_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_TRACE_CONFIG_PMULET_FREEZE_MODE = 32 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_TRACE_CONFIG_COMMON_FREEZE_MODE = 33 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_TRACE_CONFIG_RESET_MODE = 34 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_TRACE_CONFIG_PERFTRACE_ENABLE = 35 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_TRACE_CONFIG_PERFTRACE_FIXED_WINDOW = 36 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_TRACE_CONFIG_PERFTRACE_PRESCALE = 37 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_TRACE_CONFIG_PERFTRACE_MODE = 38 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_TRACE_CONFIG_PERFTRACE_MODE_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_TRACE_CONFIG_CONFIG_0 = 40 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_TRACE_CONFIG_CONFIG_0_LEN = 12 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_TRACE_CONFIG_CONFIG_1 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PERF_TRACE_CONFIG_CONFIG_1_LEN = 12 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PHY_CONFIG_TRAIN_A_ADJ = 0 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PHY_CONFIG_TRAIN_A_ADJ_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PHY_CONFIG_TRAIN_B_ADJ = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PHY_CONFIG_TRAIN_B_ADJ_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PHY_CONFIG_TRAIN_TIME = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PHY_CONFIG_TRAIN_TIME_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PHY_CONFIG_TRAIN_A_HYST = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PHY_CONFIG_TRAIN_A_HYST_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PHY_CONFIG_TRAIN_B_HYST = 12 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PHY_CONFIG_TRAIN_B_HYST_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PHY_CONFIG_PRBS_PHASE_SELECT = 16 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PHY_CONFIG_PRBS_PHASE_SELECT_LEN = 24 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PHY_CONFIG_PRBS = 40 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PHY_CONFIG_PRBS_LEN = 10 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PHY_CONFIG_PRBS_INVERT = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PHY_CONFIG_UNUSED1 = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PHY_CONFIG_ODL0_ENABLED = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PHY_CONFIG_ODL1_ENABLED = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PHY_CONFIG_ODL_SWAP = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PHY_CONFIG_UNUSED2 = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PHY_CONFIG_UNUSED2_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PHY_CONFIG_LINK0_OLL_ENABLED = 58 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PHY_CONFIG_LINK1_OLL_ENABLED = 59 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PHY_CONFIG_NPU_TRANSPORT_SWAP = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PHY_CONFIG_NV0_NPU_ENABLED = 61 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PHY_CONFIG_NV1_NPU_ENABLED = 62 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_PHY_CONFIG_NV2_NPU_ENABLED = 63 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_REPLAY_THRESHOLD_THRESH_TB_SEL = 0 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_REPLAY_THRESHOLD_THRESH_TB_SEL_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_REPLAY_THRESHOLD_THRESH_TAP_SEL = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_REPLAY_THRESHOLD_THRESH_TAP_SEL_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_REPLAY_THRESHOLD_THRESH_ENABLE = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_REPLAY_THRESHOLD_THRESH_ENABLE_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_REPLAY_THRESHOLD_THRESH_UNUSED1 = 11 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_REPLAY_THRESHOLD_THRESH_UNUSED1_LEN = 15 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_REPLAY_THRESHOLD_THRESH_LINK0_CLEAR = 26 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_REPLAY_THRESHOLD_THRESH_LINK1_CLEAR = 27 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_REPLAY_THRESHOLD_THRESH_DIS_TB_CLEAR = 28 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_REPLAY_THRESHOLD_THRESH_DIS_TAP_CLEAR = 29 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_REPLAY_THRESHOLD_THRESH_DIS_TAP_STOP = 30 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_REPLAY_THRESHOLD_THRESH_UNUSED2 = 31 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_REPLAY_THRESHOLD_THRESH_LINK0_COUNT = 32 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_REPLAY_THRESHOLD_THRESH_LINK0_COUNT_LEN = 16 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_REPLAY_THRESHOLD_THRESH_LINK1_COUNT = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_REPLAY_THRESHOLD_THRESH_LINK1_COUNT_LEN = 16 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_RETRAIN_THRESHOLD_THRESH_TB_SEL = 0 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_RETRAIN_THRESHOLD_THRESH_TB_SEL_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_RETRAIN_THRESHOLD_THRESH_TAP_SEL = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_RETRAIN_THRESHOLD_THRESH_TAP_SEL_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_RETRAIN_THRESHOLD_THRESH_ENABLE = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_RETRAIN_THRESHOLD_THRESH_ENABLE_LEN = 9 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_RETRAIN_THRESHOLD_THRESH_UNUSED1 = 17 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_RETRAIN_THRESHOLD_THRESH_UNUSED1_LEN = 9 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_RETRAIN_THRESHOLD_THRESH_LINK0_CLEAR = 26 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_RETRAIN_THRESHOLD_THRESH_LINK1_CLEAR = 27 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_RETRAIN_THRESHOLD_THRESH_DIS_TB_CLEAR = 28 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_RETRAIN_THRESHOLD_THRESH_DIS_TAP_CLEAR = 29 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_RETRAIN_THRESHOLD_THRESH_DIS_TAP_STOP = 30 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_RETRAIN_THRESHOLD_THRESH_UNUSED2 = 31 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_RETRAIN_THRESHOLD_THRESH_LINK0_COUNT = 32 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_RETRAIN_THRESHOLD_THRESH_LINK0_COUNT_LEN = 16 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_RETRAIN_THRESHOLD_THRESH_LINK1_COUNT = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_RETRAIN_THRESHOLD_THRESH_LINK1_COUNT_LEN = 16 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_SEC_CONFIG_ENABLE_ERR_INJ = 0 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_SEC_CONFIG_ENABLE_TRACE = 1 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_SEC_CONFIG_RESET_INJ = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_SEC_CONFIG_UNUSED4 = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_SEC_CONFIG_UNUSED4_LEN = 13 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_SEC_CONFIG_SBE_ERROR_RATE = 16 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_SEC_CONFIG_SBE_ERROR_RATE_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_SEC_CONFIG_RAND_ERROR_RATE = 18 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_SEC_CONFIG_RAND_ERROR_RATE_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_SEC_CONFIG_INV_SH_ERROR_RATE = 24 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_SEC_CONFIG_INV_SH_ERROR_RATE_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_SEC_CONFIG_SYNC_HEADER_ERROR_RATE = 26 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_SEC_CONFIG_SYNC_HEADER_ERROR_RATE_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_SEC_CONFIG_UNUSED5 = 32 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_SEC_CONFIG_UNUSED5_LEN = 16 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_SEC_CONFIG_EDPL_RATE = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_SEC_CONFIG_EDPL_RATE_LEN = 16 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_SL_ECC_THRESHOLD_THRESH_TB_SEL = 0 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_SL_ECC_THRESHOLD_THRESH_TB_SEL_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_SL_ECC_THRESHOLD_THRESH_TAP_SEL = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_SL_ECC_THRESHOLD_THRESH_TAP_SEL_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_SL_ECC_THRESHOLD_THRESH_ENABLE = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_SL_ECC_THRESHOLD_THRESH_ENABLE_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_SL_ECC_THRESHOLD_THRESH_UNUSED1 = 10 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_SL_ECC_THRESHOLD_THRESH_UNUSED1_LEN = 16 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_SL_ECC_THRESHOLD_THRESH_LINK0_CLEAR = 26 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_SL_ECC_THRESHOLD_THRESH_LINK1_CLEAR = 27 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_SL_ECC_THRESHOLD_THRESH_DIS_TB_CLEAR = 28 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_SL_ECC_THRESHOLD_THRESH_DIS_TAP_CLEAR = 29 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_SL_ECC_THRESHOLD_THRESH_DIS_TAP_STOP = 30 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_SL_ECC_THRESHOLD_THRESH_UNUSED2 = 31 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_SL_ECC_THRESHOLD_THRESH_LINK0_COUNT = 32 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_SL_ECC_THRESHOLD_THRESH_LINK0_COUNT_LEN = 16 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_SL_ECC_THRESHOLD_THRESH_LINK1_COUNT = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_IOOL_SL_ECC_THRESHOLD_THRESH_LINK1_COUNT_LEN = 16 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_ODL0_CONFIG_CFG_RESET = 0 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_ODL0_CONFIG_CFG_RETRAIN = 1 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_ODL0_CONFIG_CFG_VERSION = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_ODL0_CONFIG_CFG_VERSION_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_ODL0_CONFIG_CFG_TRAIN_MODE = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_ODL0_CONFIG_CFG_TRAIN_MODE_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_ODL0_CONFIG_CFG_SUPPORTED_MODES = 12 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_ODL0_CONFIG_CFG_SUPPORTED_MODES_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_ODL0_CONFIG_CFG_X4_BACKOFF_ENABLE = 16 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_ODL0_CONFIG_CFG_X1_BACKOFF_ENABLE = 17 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_ODL0_CONFIG_CFG_PWRMGT_ENABLE = 18 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_ODL0_CONFIG_CFG_TX_EP_MODE = 19 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_ODL0_CONFIG_CFG_PHY_CNTR_LIMIT = 20 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_ODL0_CONFIG_CFG_PHY_CNTR_LIMIT_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_ODL0_CONFIG_CFG_128_130_ENCODING_ENABLED = 24 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_ODL0_CONFIG_CFG_TRAINING_STATUS_REGISTER_SELECT = 25 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_ODL0_CONFIG_CFG_UNUSED2 = 26 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_ODL0_CONFIG_CFG_CRC_TX_INJECTION = 27 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_ODL0_CONFIG_CFG_ECC_CE_INJECTION = 28 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_ODL0_CONFIG_CFG_ECC_UE_INJECTION = 29 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_ODL0_CONFIG_CFG_DL2TL_CONTROL_PARITY_INJECT = 30 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_ODL0_CONFIG_CFG_DL2TL_DATA_PARITY_INJECT = 31 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_ODL0_CONFIG_CFG_UNUSED1 = 32 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_ODL0_CONFIG_CFG_DEBUG_ENABLE = 33 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_ODL0_CONFIG_CFG_DEBUG_SELECT = 34 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_ODL0_CONFIG_CFG_DEBUG_SELECT_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_ODL0_CONFIG_CFG_REPLAY_RSVD_ENTRIES = 36 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_ODL0_CONFIG_CFG_REPLAY_RSVD_ENTRIES_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_ODL0_CONFIG_CFG_FWD_PROGRESS_TIMER = 40 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_ODL0_CONFIG_CFG_FWD_PROGRESS_TIMER_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_ODL0_CONFIG_CFG_CFG_SPARE = 44 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_ODL0_CONFIG_CFG_CFG_SPARE_LEN = 20 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_ODL0_DLX_CONFIG_CFG_DLX0 = 0 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_ODL0_DLX_CONFIG_CFG_DLX0_LEN = 32 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_ODL1_CONFIG_CFG_RESET = 0 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_ODL1_CONFIG_CFG_RETRAIN = 1 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_ODL1_CONFIG_CFG_VERSION = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_ODL1_CONFIG_CFG_VERSION_LEN = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_ODL1_CONFIG_CFG_TRAIN_MODE = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_ODL1_CONFIG_CFG_TRAIN_MODE_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_ODL1_CONFIG_CFG_SUPPORTED_MODES = 12 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_ODL1_CONFIG_CFG_SUPPORTED_MODES_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_ODL1_CONFIG_CFG_X4_BACKOFF_ENABLE = 16 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_ODL1_CONFIG_CFG_X1_BACKOFF_ENABLE = 17 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_ODL1_CONFIG_CFG_PWRMGT_ENABLE = 18 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_ODL1_CONFIG_CFG_TX_EP_MODE = 19 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_ODL1_CONFIG_CFG_PHY_CNTR_LIMIT = 20 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_ODL1_CONFIG_CFG_PHY_CNTR_LIMIT_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_ODL1_CONFIG_CFG_128_130_ENCODING_ENABLED = 24 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_ODL1_CONFIG_CFG_TRAINING_STATUS_REGISTER_SELECT = 25 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_ODL1_CONFIG_CFG_UNUSED2 = 26 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_ODL1_CONFIG_CFG_CRC_TX_INJECTION = 27 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_ODL1_CONFIG_CFG_ECC_CE_INJECTION = 28 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_ODL1_CONFIG_CFG_ECC_UE_INJECTION = 29 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_ODL1_CONFIG_CFG_DL2TL_CONTROL_PARITY_INJECT = 30 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_ODL1_CONFIG_CFG_DL2TL_DATA_PARITY_INJECT = 31 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_ODL1_CONFIG_CFG_UNUSED1 = 32 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_ODL1_CONFIG_CFG_DEBUG_ENABLE = 33 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_ODL1_CONFIG_CFG_DEBUG_SELECT = 34 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_ODL1_CONFIG_CFG_DEBUG_SELECT_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_ODL1_CONFIG_CFG_REPLAY_RSVD_ENTRIES = 36 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_ODL1_CONFIG_CFG_REPLAY_RSVD_ENTRIES_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_ODL1_CONFIG_CFG_FWD_PROGRESS_TIMER = 40 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_ODL1_CONFIG_CFG_FWD_PROGRESS_TIMER_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_ODL1_CONFIG_CFG_CFG_SPARE = 44 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_ODL1_CONFIG_CFG_CFG_SPARE_LEN = 20 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_ODL1_DLX_CONFIG_CFG_DLX1 = 0 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_ODL1_DLX_CONFIG_CFG_DLX1_LEN = 32 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_PB_IOOL_FIR_ACTION0_REG_ACTION0 = 0 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_PB_IOOL_FIR_ACTION0_REG_ACTION0_LEN = 64 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_PB_IOOL_FIR_ACTION1_REG_ACTION1 = 0 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_LL0_PB_IOOL_FIR_ACTION1_REG_ACTION1_LEN = 64 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL0_DLX_INFO_STS = 0 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL0_DLX_INFO_STS_LEN = 64 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL0_STATUS_STS_TRAINED_MODE = 0 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL0_STATUS_STS_TRAINED_MODE_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL0_STATUS_STS_RX_LANE_REVERSED = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL0_STATUS_STS_TX_LANE_REVERSED = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL0_STATUS_STS_RSVD0 = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL0_STATUS_STS_ACK_PTRS_EQUAL = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL0_STATUS_STS_RSVD1 = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL0_STATUS_STS_RSVD1_LEN = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL0_STATUS_STS_RX_TRAINED_LANES = 16 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL0_STATUS_STS_RX_TRAINED_LANES_LEN = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL0_STATUS_STS_TX_TRAINED_LANES = 24 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL0_STATUS_STS_TX_TRAINED_LANES_LEN = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL0_STATUS_STS_ENDPOINT_INFO = 32 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL0_STATUS_STS_ENDPOINT_INFO_LEN = 16 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL0_STATUS_STS_RSVD2 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL0_STATUS_STS_TRAINING_STATE_MACHINE = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL0_STATUS_STS_TRAINING_STATE_MACHINE_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL0_STATUS_STS_RSVD3 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL0_STATUS_STS_RSVD3_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL0_STATUS_STS_DESKEW_DONE = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL0_STATUS_STS_LANES_DISABLED = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL0_STATUS_STS_LANES_DISABLED_LEN = 8 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL0_TRAINING_STATUS_STS_RX_PATTERN_A = 0 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL0_TRAINING_STATUS_STS_RX_PATTERN_A_LEN = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL0_TRAINING_STATUS_STS_RX_PATTERN_B = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL0_TRAINING_STATUS_STS_RX_PATTERN_B_LEN = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL0_TRAINING_STATUS_STS_SYNC_PATTERN = 16 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL0_TRAINING_STATUS_STS_SYNC_PATTERN_LEN = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL0_TRAINING_STATUS_STS_PHY_INIT_DONE = 24 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL0_TRAINING_STATUS_STS_PHY_INIT_DONE_LEN = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL0_TRAINING_STATUS_STS_BLOCK_LOCKED = 32 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL0_TRAINING_STATUS_STS_BLOCK_LOCKED_LEN = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL0_TRAINING_STATUS_STS_RX_TS1 = 40 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL0_TRAINING_STATUS_STS_RX_TS1_LEN = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL0_TRAINING_STATUS_STS_RX_TS2 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL0_TRAINING_STATUS_STS_RX_TS2_LEN = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL0_TRAINING_STATUS_STS_RX_TS3 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL0_TRAINING_STATUS_STS_RX_TS3_LEN = 8 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL1_DLX_INFO_STS = 0 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL1_DLX_INFO_STS_LEN = 64 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL1_STATUS_STS_TRAINED_MODE = 0 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL1_STATUS_STS_TRAINED_MODE_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL1_STATUS_STS_RX_LANE_REVERSED = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL1_STATUS_STS_TX_LANE_REVERSED = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL1_STATUS_STS_RSVD0 = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL1_STATUS_STS_ACK_PTRS_EQUAL = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL1_STATUS_STS_RSVD1 = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL1_STATUS_STS_RSVD1_LEN = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL1_STATUS_STS_RX_TRAINED_LANES = 16 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL1_STATUS_STS_RX_TRAINED_LANES_LEN = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL1_STATUS_STS_TX_TRAINED_LANES = 24 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL1_STATUS_STS_TX_TRAINED_LANES_LEN = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL1_STATUS_STS_ENDPOINT_INFO = 32 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL1_STATUS_STS_ENDPOINT_INFO_LEN = 16 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL1_STATUS_STS_RSVD2 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL1_STATUS_STS_TRAINING_STATE_MACHINE = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL1_STATUS_STS_TRAINING_STATE_MACHINE_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL1_STATUS_STS_RSVD3 = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL1_STATUS_STS_RSVD3_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL1_STATUS_STS_DESKEW_DONE = 55 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL1_STATUS_STS_LANES_DISABLED = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL1_STATUS_STS_LANES_DISABLED_LEN = 8 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL1_TRAINING_STATUS_STS_RX_PATTERN_A = 0 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL1_TRAINING_STATUS_STS_RX_PATTERN_A_LEN = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL1_TRAINING_STATUS_STS_RX_PATTERN_B = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL1_TRAINING_STATUS_STS_RX_PATTERN_B_LEN = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL1_TRAINING_STATUS_STS_SYNC_PATTERN = 16 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL1_TRAINING_STATUS_STS_SYNC_PATTERN_LEN = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL1_TRAINING_STATUS_STS_PHY_INIT_DONE = 24 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL1_TRAINING_STATUS_STS_PHY_INIT_DONE_LEN = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL1_TRAINING_STATUS_STS_BLOCK_LOCKED = 32 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL1_TRAINING_STATUS_STS_BLOCK_LOCKED_LEN = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL1_TRAINING_STATUS_STS_RX_TS1 = 40 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL1_TRAINING_STATUS_STS_RX_TS1_LEN = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL1_TRAINING_STATUS_STS_RX_TS2 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL1_TRAINING_STATUS_STS_RX_TS2_LEN = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL1_TRAINING_STATUS_STS_RX_TS3 = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_NV0_ODL1_TRAINING_STATUS_STS_RX_TS3_LEN = 8 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR = 0 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN = 16 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_ADDR_TRAP_REG_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR = 16 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_ADDR_TRAP_REG_RESERVED_LAST_LT = 17 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR = 18 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN = 13
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY = 31 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR = 32 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION = 33 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER = 34 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_ATOMIC_LOCK_MASK_LATCH_REG_MASK = 0 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_ATOMIC_LOCK_MASK_LATCH_REG_MASK_LEN = 16 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST1_COND_REG_1_COND1_SEL_A = 0 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST1_COND_REG_1_COND1_SEL_A_LEN = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST1_COND_REG_1_COND1_SEL_B = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST1_COND_REG_1_COND1_SEL_B_LEN = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST1_COND_REG_1_COND2_SEL_A = 16 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST1_COND_REG_1_COND2_SEL_A_LEN = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST1_COND_REG_1_COND2_SEL_B = 24 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST1_COND_REG_1_COND2_SEL_B_LEN = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST1_COND_REG_1_C1_INAROW_MODE = 32 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE1 = 33 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE1 = 34 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE1 = 35 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST1_COND_REG_1_UNUSED = 36 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST1_COND_REG_1_UNUSED_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST1_COND_REG_1_C2_INAROW_MODE = 39 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE2 = 40 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE2 = 41 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE2 = 42 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST1_COND_REG_1_UNUSED_2 = 43 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST1_COND_REG_1_UNUSED_2_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST1_COND_REG_1_COND3_ENABLE_RESET = 46 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST1_COND_REG_1_EXACT_TO_MODE = 47 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST1_COND_REG_1_RESET_C2TIMER_ON_C1 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST1_COND_REG_1_RESET_C3_ON_C0 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST1_COND_REG_1_SLOW_TO_MODE = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST1_COND_REG_1_EXACT_RESET_C3_ON_TO = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST1_COND_REG_1_C1_COUNT_LT = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST1_COND_REG_1_C1_COUNT_LT_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST1_COND_REG_1_C2_COUNT_LT = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST1_COND_REG_1_C2_COUNT_LT_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST1_COND_REG_1_RESET_C3_SELECT = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST1_COND_REG_1_RESET_C3_SELECT_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A = 0 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A = 10 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B = 15 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST1_COND_REG_2_TO_CMP_LT = 20 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST1_COND_REG_2_TO_CMP_LT_LEN = 24 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST2_COND_REG_1_COND1_SEL_A = 0 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST2_COND_REG_1_COND1_SEL_A_LEN = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST2_COND_REG_1_COND1_SEL_B = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST2_COND_REG_1_COND1_SEL_B_LEN = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST2_COND_REG_1_COND2_SEL_A = 16 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST2_COND_REG_1_COND2_SEL_A_LEN = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST2_COND_REG_1_COND2_SEL_B = 24 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST2_COND_REG_1_COND2_SEL_B_LEN = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST2_COND_REG_1_C1_INAROW_MODE = 32 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE1 = 33 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE1 = 34 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE1 = 35 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST2_COND_REG_1_UNUSED = 36 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST2_COND_REG_1_UNUSED_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST2_COND_REG_1_C2_INAROW_MODE = 39 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE2 = 40 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE2 = 41 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE2 = 42 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST2_COND_REG_1_UNUSED_2 = 43 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST2_COND_REG_1_UNUSED_2_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST2_COND_REG_1_COND3_ENABLE_RESET = 46 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST2_COND_REG_1_EXACT_TO_MODE = 47 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST2_COND_REG_1_RESET_C2TIMER_ON_C1 = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST2_COND_REG_1_RESET_C3_ON_C0 = 49 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST2_COND_REG_1_SLOW_TO_MODE = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST2_COND_REG_1_EXACT_RESET_C3_ON_TO = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST2_COND_REG_1_C1_COUNT_LT = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST2_COND_REG_1_C1_COUNT_LT_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST2_COND_REG_1_C2_COUNT_LT = 56 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST2_COND_REG_1_C2_COUNT_LT_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST2_COND_REG_1_RESET_C3_SELECT = 60 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST2_COND_REG_1_RESET_C3_SELECT_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A = 0 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A = 10 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B = 15 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST2_COND_REG_2_TO_CMP_LT = 20 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_INST2_COND_REG_2_TO_CMP_LT_LEN = 24 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_MODE_REG_GLB_BRCST = 0 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_MODE_REG_GLB_BRCST_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_MODE_REG_TRACE_SEL = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_MODE_REG_TRACE_SEL_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_MODE_REG_TRIG_SEL = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_MODE_REG_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_MODE_REG_STOP_ON_XSTOP_SELECTION = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_MODE_REG_STOP_ON_RECOV_ERR_SELECTION = 9 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_MODE_REG_STOP_ON_SPATTN_SELECTION = 10 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_MODE_REG_FREEZE_SEL = 11 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_MODE_REG_SYNC_BRCST = 12 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_MODE_REG_SYNC_BRCST_LEN = 2 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE = 0 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE_LEN = 16 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_TRACE_MODE_REG_2_IMM_FREEZE = 16 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_TRACE_MODE_REG_2_STOP_ON_ERR = 17 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_TRACE_MODE_REG_2_BANK_ON_RUNN_MATCH = 18 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_TRACE_MODE_REG_2_FORCE_TEST = 19 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_TRACE_MODE_REG_2_ACCUM_HIST = 20 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_TRACE_MODE_REG_2_FRZ_COUNT_ON_FRZ = 21 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_TRACE_REG_0_INST1_COND3_ENABLE = 0 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_TRACE_REG_0_INST2_COND3_ENABLE = 1 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_TRACE_REG_0_INST3_COND3_ENABLE = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_TRACE_REG_0_INST4_COND3_ENABLE = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_TRACE_REG_0_INST1_SLOW_LFSR_MODE = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_TRACE_REG_0_INST2_SLOW_LFSR_MODE = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_TRACE_REG_0_INST3_SLOW_LFSR_MODE = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_TRACE_REG_0_INST4_SLOW_LFSR_MODE = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL = 10 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL = 12 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL = 14 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL = 16 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL = 18 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_TRACE_REG_0_EXT_TRIG_ON_STOP = 32 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_TRACE_REG_0_EXT_TRIG_ON_FREEZE = 33 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL = 34 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL = 39 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL_LEN = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_TRACE_REG_0_PC_TP_TRIG_SEL = 44 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_TRACE_REG_0_PC_TP_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_TRACE_REG_0_ARM_SEL = 46 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_TRACE_REG_0_ARM_SEL_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL = 50 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL_LEN = 4 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO = 0 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO = 10 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_WAITN = 24 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_WAITN = 25 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_WAITN = 26 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_WAITN = 27 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_WAITN = 28 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_WAITN = 29 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_BANK = 36 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_BANK = 37 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_BANK = 38 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_BANK = 39 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_BANK = 40 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_BANK = 41 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT = 48 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_SELECTOR = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT_LEN = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_SELECTOR = 55 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DEBUG_TRACE_CONTROL_SCOM_TRACE_START = 0 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DEBUG_TRACE_CONTROL_SCOM_TRACE_STOP = 1 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_DEBUG_TRACE_CONTROL_SCOM_TRACE_RESET = 2 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_PSCOM_ERROR_MASK_PCB_WDATA_PARITY = 0 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_PSCOM_ERROR_MASK_PCB_ADDRESS_PARITY = 1 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_PSCOM_ERROR_MASK_DL_RETURN_WDATA_PARITY = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_PSCOM_ERROR_MASK_DL_RETURN_P0 = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_PSCOM_ERROR_MASK_UL_RDATA_PARITY = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_PSCOM_ERROR_MASK_UL_P0 = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_PSCOM_ERROR_MASK_PARITY_ON_INTERFACE_MACHINE = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_PSCOM_ERROR_MASK_PARITY_ON_P2S_MACHINE = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 9 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 10 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_PSCOM_ERROR_MASK_PARALLEL_WRITE_NVLD = 11 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_PSCOM_ERROR_MASK_PARALLEL_READ_NVLD = 12 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_PSCOM_ERROR_MASK_PARALLEL_ADDR_INVALID = 13 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_PSCOM_ERROR_MASK_PCB_COMMAND_PARITY = 14 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_PSCOM_ERROR_MASK_GENERAL_TIMEOUT = 15 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 16 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 17 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_PSCOM_MODE_REG_ABORT_ON_PCB_ADDR_PARITY_ERROR = 0 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_PSCOM_MODE_REG_ABORT_ON_PCB_WDATA_PARITY_ERROR = 1 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_PSCOM_MODE_REG_UNUSED_BIT_2 = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_PSCOM_MODE_REG_WATCHDOG_ENABLE = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_PSCOM_MODE_REG_SCOM_HANG_LIMIT = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_PSCOM_MODE_REG_SCOM_HANG_LIMIT_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_PSCOM_MODE_REG_FORCE_ALL_RINGS = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_PSCOM_MODE_REG_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_PSCOM_MODE_REG_RESERVED_LT = 9 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_PSCOM_MODE_REG_RESERVED_LT_LEN = 3 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_WDATA_PARITY = 0 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_ADDRESS_PARITY = 1 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_WDATA_PARITY = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_P0 = 3 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_RDATA_PARITY = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_P0 = 5 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_P2S_MACHINE = 7 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 8
+ ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_TCOB0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 9 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 10
+ ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_WRITE_NVLD = 11 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_READ_NVLD = 12 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_ADDR_INVALID = 13 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_COMMAND_PARITY = 14 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_GENERAL_TIMEOUT = 15 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_TCOB0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 16 ;
+static const uint8_t
+P9N2_OBUS_C0_S0_P0_E9_TCOB0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 17 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_WDATA_PARITY = 18 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_ADDRESS_PARITY = 19 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_WDATA_PARITY = 20 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_P0 = 21 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_RDATA_PARITY = 22 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_P0 = 23 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_INTERFACE_MACHINE = 24 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_P2S_MACHINE = 25 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 26 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN =
+ 27 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 28 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_WRITE_NVLD = 29 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_READ_NVLD = 30 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_ADDR_INVALID = 31 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_COMMAND_PARITY = 32 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_PSCOM_STATUS_ERROR_REG_TRAPPED_GENERAL_TIMEOUT = 33 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION =
+ 34 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER =
+ 35 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_RING_FENCE_MASK_LATCH_REG_ENABLE = 1 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN = 15 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_HI_DATA_REG_DATA = 0 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_HI_DATA_REG_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_LO_DATA_REG_DATA = 0 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_LO_DATA_REG_DATA_LEN = 32 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_LO_DATA_REG_ADDRESS = 32 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN = 10 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK = 42 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN = 9 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID = 51 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN = 52 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_LO_DATA_REG_RUNNING = 53 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS = 54 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN = 10 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE = 0 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE = 1 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRCTRL_CONFIG_BANK_MODE = 10 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRCTRL_CONFIG_ENH_MODE = 11 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL = 12 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRCTRL_CONFIG_SELECT_CONTROL = 14 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRCTRL_CONFIG_SELECT_CONTROL_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRCTRL_CONFIG_RUN_HOLD_OFF = 18 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRCTRL_CONFIG_RUN_STATUS = 19 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRCTRL_CONFIG_RUN_STICKY = 20 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRCTRL_CONFIG_DISABLE_BANK_EDGE_DETECT = 21 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRCTRL_CONFIG_CONTROL_UNUSED = 22 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRCTRL_CONFIG_CONTROL_UNUSED_LEN = 6 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 = 0 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN = 64 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 = 0 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN = 24 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA = 0 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN = 24 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB = 24 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN = 24 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC = 0 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN = 24 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERND = 24 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN = 24 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKA = 0 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN = 24 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKB = 24 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN = 24 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKC = 0 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN = 24 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKD = 24 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN = 24 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION = 0 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK = 1 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL = 6 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL = 8 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN = 2 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK = 10 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK = 14 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK = 18 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK = 22 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE = 26 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE = 27 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE = 28 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN = 4 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_ERROR_CMP_MASK = 32 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_ERROR_CMP_PATTERN = 33 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_ERR_CMP = 34 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_ERR_CMP = 35 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES = 36 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_SPARE_LT = 37 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_WRITE_PROTECT_ENABLE_REG_RING_LOCKING = 0 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_WRITE_PROTECT_ENABLE_REG_RESERVED_RING_LOCKING = 1 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_WRITE_PROTECT_RINGS_REG_RINGS = 0 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_WRITE_PROTECT_RINGS_REG_RINGS_LEN = 16 ;
+
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_XTRA_TRACE_MODE_DATA = 0 ;
+static const uint8_t P9N2_OBUS_C0_S0_P0_E9_TCOB0_XTRA_TRACE_MODE_DATA_LEN = 42 ;
+
+#endif
+
diff --git a/src/import/chips/p9/common/include/p9n2_perv_scom_addresses.H b/src/import/chips/p9/common/include/p9n2_perv_scom_addresses.H
new file mode 100644
index 000000000..6d768893c
--- /dev/null
+++ b/src/import/chips/p9/common/include/p9n2_perv_scom_addresses.H
@@ -0,0 +1,18252 @@
+/* IBM_PROLOG_BEGIN_TAG */
+/* This is an automatically generated prolog. */
+/* */
+/* $Source: src/import/chips/p9/common/include/p9n2_perv_scom_addresses.H $ */
+/* */
+/* OpenPOWER HostBoot Project */
+/* */
+/* Contributors Listed Below - COPYRIGHT 2017 */
+/* [+] International Business Machines Corp. */
+/* */
+/* */
+/* Licensed under the Apache License, Version 2.0 (the "License"); */
+/* you may not use this file except in compliance with the License. */
+/* You may obtain a copy of the License at */
+/* */
+/* http://www.apache.org/licenses/LICENSE-2.0 */
+/* */
+/* Unless required by applicable law or agreed to in writing, software */
+/* distributed under the License is distributed on an "AS IS" BASIS, */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */
+/* implied. See the License for the specific language governing */
+/* permissions and limitations under the License. */
+/* */
+/* IBM_PROLOG_END_TAG */
+///
+/// @file p9_perv_scom_addresses.H
+/// @brief Defines constants for scom addresses
+///
+// *HWP HWP Owner: Ben Gass <bgass@us.ibm.com>
+// *HWP FW Owner: Thi Tran <thi@us.ibm.com>
+// *HWP Team: SOA
+// *HWP Level: 1
+// *HWP Consumed by: FSP:HB:HS:OCC:SBE:CME:SGPE:PGPE:FPPE:IPPE
+
+/*---------------------------------------------------------------
+ *
+ *---------------------------------------------------------------
+ *
+ *---------------------------------------------------------------
+ */
+
+#ifndef __P9N2_PERV_SCOM_ADDRESSES_H
+#define __P9N2_PERV_SCOM_ADDRESSES_H
+
+#include <stdint.h>
+
+static const uint64_t P9N2_PERV_ADDR_TRAP_REG = 0x00010003ull;
+
+static const uint64_t P9N2_PERV_TP_ADDR_TRAP_REG = 0x01010003ull;
+
+
+static const uint64_t P9N2_PERV_ASSIST_INTERRUPT_REG = 0x000F0011ull;
+
+static const uint64_t P9N2_PERV_TP_ASSIST_INTERRUPT_REG = 0x010F0011ull;
+
+static const uint64_t P9N2_PERV_N0_ASSIST_INTERRUPT_REG = 0x020F0011ull;
+
+static const uint64_t P9N2_PERV_N1_ASSIST_INTERRUPT_REG = 0x030F0011ull;
+
+static const uint64_t P9N2_PERV_N2_ASSIST_INTERRUPT_REG = 0x040F0011ull;
+
+static const uint64_t P9N2_PERV_N3_ASSIST_INTERRUPT_REG = 0x050F0011ull;
+
+static const uint64_t P9N2_PERV_XB_ASSIST_INTERRUPT_REG = 0x060F0011ull;
+
+static const uint64_t P9N2_PERV_MC01_ASSIST_INTERRUPT_REG = 0x070F0011ull;
+
+static const uint64_t P9N2_PERV_MC23_ASSIST_INTERRUPT_REG = 0x080F0011ull;
+
+static const uint64_t P9N2_PERV_OB0_ASSIST_INTERRUPT_REG = 0x090F0011ull;
+
+static const uint64_t P9N2_PERV_OB3_ASSIST_INTERRUPT_REG = 0x0C0F0011ull;
+
+static const uint64_t P9N2_PERV_PCI0_ASSIST_INTERRUPT_REG = 0x0D0F0011ull;
+
+static const uint64_t P9N2_PERV_PCI1_ASSIST_INTERRUPT_REG = 0x0E0F0011ull;
+
+static const uint64_t P9N2_PERV_PCI2_ASSIST_INTERRUPT_REG = 0x0F0F0011ull;
+
+static const uint64_t P9N2_PERV_EP00_ASSIST_INTERRUPT_REG = 0x100F0011ull;
+
+static const uint64_t P9N2_PERV_EP01_ASSIST_INTERRUPT_REG = 0x110F0011ull;
+
+static const uint64_t P9N2_PERV_EP02_ASSIST_INTERRUPT_REG = 0x120F0011ull;
+
+static const uint64_t P9N2_PERV_EP03_ASSIST_INTERRUPT_REG = 0x130F0011ull;
+
+static const uint64_t P9N2_PERV_EP04_ASSIST_INTERRUPT_REG = 0x140F0011ull;
+
+static const uint64_t P9N2_PERV_EP05_ASSIST_INTERRUPT_REG = 0x150F0011ull;
+
+static const uint64_t P9N2_PERV_EC00_ASSIST_INTERRUPT_REG = 0x200F0011ull;
+
+static const uint64_t P9N2_PERV_EC01_ASSIST_INTERRUPT_REG = 0x210F0011ull;
+
+static const uint64_t P9N2_PERV_EC02_ASSIST_INTERRUPT_REG = 0x220F0011ull;
+
+static const uint64_t P9N2_PERV_EC03_ASSIST_INTERRUPT_REG = 0x230F0011ull;
+
+static const uint64_t P9N2_PERV_EC04_ASSIST_INTERRUPT_REG = 0x240F0011ull;
+
+static const uint64_t P9N2_PERV_EC05_ASSIST_INTERRUPT_REG = 0x250F0011ull;
+
+static const uint64_t P9N2_PERV_EC06_ASSIST_INTERRUPT_REG = 0x260F0011ull;
+
+static const uint64_t P9N2_PERV_EC07_ASSIST_INTERRUPT_REG = 0x270F0011ull;
+
+static const uint64_t P9N2_PERV_EC08_ASSIST_INTERRUPT_REG = 0x280F0011ull;
+
+static const uint64_t P9N2_PERV_EC09_ASSIST_INTERRUPT_REG = 0x290F0011ull;
+
+static const uint64_t P9N2_PERV_EC10_ASSIST_INTERRUPT_REG = 0x2A0F0011ull;
+
+static const uint64_t P9N2_PERV_EC11_ASSIST_INTERRUPT_REG = 0x2B0F0011ull;
+
+static const uint64_t P9N2_PERV_EC12_ASSIST_INTERRUPT_REG = 0x2C0F0011ull;
+
+static const uint64_t P9N2_PERV_EC13_ASSIST_INTERRUPT_REG = 0x2D0F0011ull;
+
+static const uint64_t P9N2_PERV_EC14_ASSIST_INTERRUPT_REG = 0x2E0F0011ull;
+
+static const uint64_t P9N2_PERV_EC15_ASSIST_INTERRUPT_REG = 0x2F0F0011ull;
+
+static const uint64_t P9N2_PERV_EC16_ASSIST_INTERRUPT_REG = 0x300F0011ull;
+
+static const uint64_t P9N2_PERV_EC17_ASSIST_INTERRUPT_REG = 0x310F0011ull;
+
+static const uint64_t P9N2_PERV_EC18_ASSIST_INTERRUPT_REG = 0x320F0011ull;
+
+static const uint64_t P9N2_PERV_EC19_ASSIST_INTERRUPT_REG = 0x330F0011ull;
+
+static const uint64_t P9N2_PERV_EC20_ASSIST_INTERRUPT_REG = 0x340F0011ull;
+
+static const uint64_t P9N2_PERV_EC21_ASSIST_INTERRUPT_REG = 0x350F0011ull;
+
+static const uint64_t P9N2_PERV_EC22_ASSIST_INTERRUPT_REG = 0x360F0011ull;
+
+static const uint64_t P9N2_PERV_EC23_ASSIST_INTERRUPT_REG = 0x370F0011ull;
+
+
+static const uint64_t P9N2_PERV_ATOMIC_LOCK_MASK_LATCH_REG = 0x00010007ull;
+
+static const uint64_t P9N2_PERV_TP_ATOMIC_LOCK_MASK_LATCH_REG = 0x01010007ull;
+
+
+static const uint64_t P9N2_PERV_ATOMIC_LOCK_REG = 0x000F03FFull;
+
+static const uint64_t P9N2_PERV_TP_ATOMIC_LOCK_REG = 0x010F03FFull;
+
+static const uint64_t P9N2_PERV_N0_ATOMIC_LOCK_REG = 0x020F03FFull;
+
+static const uint64_t P9N2_PERV_N1_ATOMIC_LOCK_REG = 0x030F03FFull;
+
+static const uint64_t P9N2_PERV_N2_ATOMIC_LOCK_REG = 0x040F03FFull;
+
+static const uint64_t P9N2_PERV_N3_ATOMIC_LOCK_REG = 0x050F03FFull;
+
+static const uint64_t P9N2_PERV_XB_ATOMIC_LOCK_REG = 0x060F03FFull;
+
+static const uint64_t P9N2_PERV_MC01_ATOMIC_LOCK_REG = 0x070F03FFull;
+
+static const uint64_t P9N2_PERV_MC23_ATOMIC_LOCK_REG = 0x080F03FFull;
+
+static const uint64_t P9N2_PERV_OB0_ATOMIC_LOCK_REG = 0x090F03FFull;
+
+static const uint64_t P9N2_PERV_OB3_ATOMIC_LOCK_REG = 0x0C0F03FFull;
+
+static const uint64_t P9N2_PERV_PCI0_ATOMIC_LOCK_REG = 0x0D0F03FFull;
+
+static const uint64_t P9N2_PERV_PCI1_ATOMIC_LOCK_REG = 0x0E0F03FFull;
+
+static const uint64_t P9N2_PERV_PCI2_ATOMIC_LOCK_REG = 0x0F0F03FFull;
+
+static const uint64_t P9N2_PERV_EP00_ATOMIC_LOCK_REG = 0x100F03FFull;
+
+static const uint64_t P9N2_PERV_EP01_ATOMIC_LOCK_REG = 0x110F03FFull;
+
+static const uint64_t P9N2_PERV_EP02_ATOMIC_LOCK_REG = 0x120F03FFull;
+
+static const uint64_t P9N2_PERV_EP03_ATOMIC_LOCK_REG = 0x130F03FFull;
+
+static const uint64_t P9N2_PERV_EP04_ATOMIC_LOCK_REG = 0x140F03FFull;
+
+static const uint64_t P9N2_PERV_EP05_ATOMIC_LOCK_REG = 0x150F03FFull;
+
+static const uint64_t P9N2_PERV_EC00_ATOMIC_LOCK_REG = 0x200F03FFull;
+
+static const uint64_t P9N2_PERV_EC01_ATOMIC_LOCK_REG = 0x210F03FFull;
+
+static const uint64_t P9N2_PERV_EC02_ATOMIC_LOCK_REG = 0x220F03FFull;
+
+static const uint64_t P9N2_PERV_EC03_ATOMIC_LOCK_REG = 0x230F03FFull;
+
+static const uint64_t P9N2_PERV_EC04_ATOMIC_LOCK_REG = 0x240F03FFull;
+
+static const uint64_t P9N2_PERV_EC05_ATOMIC_LOCK_REG = 0x250F03FFull;
+
+static const uint64_t P9N2_PERV_EC06_ATOMIC_LOCK_REG = 0x260F03FFull;
+
+static const uint64_t P9N2_PERV_EC07_ATOMIC_LOCK_REG = 0x270F03FFull;
+
+static const uint64_t P9N2_PERV_EC08_ATOMIC_LOCK_REG = 0x280F03FFull;
+
+static const uint64_t P9N2_PERV_EC09_ATOMIC_LOCK_REG = 0x290F03FFull;
+
+static const uint64_t P9N2_PERV_EC10_ATOMIC_LOCK_REG = 0x2A0F03FFull;
+
+static const uint64_t P9N2_PERV_EC11_ATOMIC_LOCK_REG = 0x2B0F03FFull;
+
+static const uint64_t P9N2_PERV_EC12_ATOMIC_LOCK_REG = 0x2C0F03FFull;
+
+static const uint64_t P9N2_PERV_EC13_ATOMIC_LOCK_REG = 0x2D0F03FFull;
+
+static const uint64_t P9N2_PERV_EC14_ATOMIC_LOCK_REG = 0x2E0F03FFull;
+
+static const uint64_t P9N2_PERV_EC15_ATOMIC_LOCK_REG = 0x2F0F03FFull;
+
+static const uint64_t P9N2_PERV_EC16_ATOMIC_LOCK_REG = 0x300F03FFull;
+
+static const uint64_t P9N2_PERV_EC17_ATOMIC_LOCK_REG = 0x310F03FFull;
+
+static const uint64_t P9N2_PERV_EC18_ATOMIC_LOCK_REG = 0x320F03FFull;
+
+static const uint64_t P9N2_PERV_EC19_ATOMIC_LOCK_REG = 0x330F03FFull;
+
+static const uint64_t P9N2_PERV_EC20_ATOMIC_LOCK_REG = 0x340F03FFull;
+
+static const uint64_t P9N2_PERV_EC21_ATOMIC_LOCK_REG = 0x350F03FFull;
+
+static const uint64_t P9N2_PERV_EC22_ATOMIC_LOCK_REG = 0x360F03FFull;
+
+static const uint64_t P9N2_PERV_EC23_ATOMIC_LOCK_REG = 0x370F03FFull;
+
+
+static const uint64_t P9N2_PERV_ATTN_INTERRUPT_REG = 0x000F001Aull;
+
+static const uint64_t P9N2_PERV_TP_ATTN_INTERRUPT_REG = 0x010F001Aull;
+
+static const uint64_t P9N2_PERV_N0_ATTN_INTERRUPT_REG = 0x020F001Aull;
+
+static const uint64_t P9N2_PERV_N1_ATTN_INTERRUPT_REG = 0x030F001Aull;
+
+static const uint64_t P9N2_PERV_N2_ATTN_INTERRUPT_REG = 0x040F001Aull;
+
+static const uint64_t P9N2_PERV_N3_ATTN_INTERRUPT_REG = 0x050F001Aull;
+
+static const uint64_t P9N2_PERV_XB_ATTN_INTERRUPT_REG = 0x060F001Aull;
+
+static const uint64_t P9N2_PERV_MC01_ATTN_INTERRUPT_REG = 0x070F001Aull;
+
+static const uint64_t P9N2_PERV_MC23_ATTN_INTERRUPT_REG = 0x080F001Aull;
+
+static const uint64_t P9N2_PERV_OB0_ATTN_INTERRUPT_REG = 0x090F001Aull;
+
+static const uint64_t P9N2_PERV_OB3_ATTN_INTERRUPT_REG = 0x0C0F001Aull;
+
+static const uint64_t P9N2_PERV_PCI0_ATTN_INTERRUPT_REG = 0x0D0F001Aull;
+
+static const uint64_t P9N2_PERV_PCI1_ATTN_INTERRUPT_REG = 0x0E0F001Aull;
+
+static const uint64_t P9N2_PERV_PCI2_ATTN_INTERRUPT_REG = 0x0F0F001Aull;
+
+static const uint64_t P9N2_PERV_EP00_ATTN_INTERRUPT_REG = 0x100F001Aull;
+
+static const uint64_t P9N2_PERV_EP01_ATTN_INTERRUPT_REG = 0x110F001Aull;
+
+static const uint64_t P9N2_PERV_EP02_ATTN_INTERRUPT_REG = 0x120F001Aull;
+
+static const uint64_t P9N2_PERV_EP03_ATTN_INTERRUPT_REG = 0x130F001Aull;
+
+static const uint64_t P9N2_PERV_EP04_ATTN_INTERRUPT_REG = 0x140F001Aull;
+
+static const uint64_t P9N2_PERV_EP05_ATTN_INTERRUPT_REG = 0x150F001Aull;
+
+static const uint64_t P9N2_PERV_EC00_ATTN_INTERRUPT_REG = 0x200F001Aull;
+
+static const uint64_t P9N2_PERV_EC01_ATTN_INTERRUPT_REG = 0x210F001Aull;
+
+static const uint64_t P9N2_PERV_EC02_ATTN_INTERRUPT_REG = 0x220F001Aull;
+
+static const uint64_t P9N2_PERV_EC03_ATTN_INTERRUPT_REG = 0x230F001Aull;
+
+static const uint64_t P9N2_PERV_EC04_ATTN_INTERRUPT_REG = 0x240F001Aull;
+
+static const uint64_t P9N2_PERV_EC05_ATTN_INTERRUPT_REG = 0x250F001Aull;
+
+static const uint64_t P9N2_PERV_EC06_ATTN_INTERRUPT_REG = 0x260F001Aull;
+
+static const uint64_t P9N2_PERV_EC07_ATTN_INTERRUPT_REG = 0x270F001Aull;
+
+static const uint64_t P9N2_PERV_EC08_ATTN_INTERRUPT_REG = 0x280F001Aull;
+
+static const uint64_t P9N2_PERV_EC09_ATTN_INTERRUPT_REG = 0x290F001Aull;
+
+static const uint64_t P9N2_PERV_EC10_ATTN_INTERRUPT_REG = 0x2A0F001Aull;
+
+static const uint64_t P9N2_PERV_EC11_ATTN_INTERRUPT_REG = 0x2B0F001Aull;
+
+static const uint64_t P9N2_PERV_EC12_ATTN_INTERRUPT_REG = 0x2C0F001Aull;
+
+static const uint64_t P9N2_PERV_EC13_ATTN_INTERRUPT_REG = 0x2D0F001Aull;
+
+static const uint64_t P9N2_PERV_EC14_ATTN_INTERRUPT_REG = 0x2E0F001Aull;
+
+static const uint64_t P9N2_PERV_EC15_ATTN_INTERRUPT_REG = 0x2F0F001Aull;
+
+static const uint64_t P9N2_PERV_EC16_ATTN_INTERRUPT_REG = 0x300F001Aull;
+
+static const uint64_t P9N2_PERV_EC17_ATTN_INTERRUPT_REG = 0x310F001Aull;
+
+static const uint64_t P9N2_PERV_EC18_ATTN_INTERRUPT_REG = 0x320F001Aull;
+
+static const uint64_t P9N2_PERV_EC19_ATTN_INTERRUPT_REG = 0x330F001Aull;
+
+static const uint64_t P9N2_PERV_EC20_ATTN_INTERRUPT_REG = 0x340F001Aull;
+
+static const uint64_t P9N2_PERV_EC21_ATTN_INTERRUPT_REG = 0x350F001Aull;
+
+static const uint64_t P9N2_PERV_EC22_ATTN_INTERRUPT_REG = 0x360F001Aull;
+
+static const uint64_t P9N2_PERV_EC23_ATTN_INTERRUPT_REG = 0x370F001Aull;
+
+
+static const uint64_t P9N2_PERV_BIST = 0x0003000Bull;
+
+static const uint64_t P9N2_PERV_TP_BIST = 0x0103000Bull;
+
+static const uint64_t P9N2_PERV_N0_BIST = 0x0203000Bull;
+
+static const uint64_t P9N2_PERV_N1_BIST = 0x0303000Bull;
+
+static const uint64_t P9N2_PERV_N2_BIST = 0x0403000Bull;
+
+static const uint64_t P9N2_PERV_N3_BIST = 0x0503000Bull;
+
+static const uint64_t P9N2_PERV_XB_BIST = 0x0603000Bull;
+
+static const uint64_t P9N2_PERV_MC01_BIST = 0x0703000Bull;
+
+static const uint64_t P9N2_PERV_MC23_BIST = 0x0803000Bull;
+
+static const uint64_t P9N2_PERV_OB0_BIST = 0x0903000Bull;
+
+static const uint64_t P9N2_PERV_OB3_BIST = 0x0C03000Bull;
+
+static const uint64_t P9N2_PERV_PCI0_BIST = 0x0D03000Bull;
+
+static const uint64_t P9N2_PERV_PCI1_BIST = 0x0E03000Bull;
+
+static const uint64_t P9N2_PERV_PCI2_BIST = 0x0F03000Bull;
+
+static const uint64_t P9N2_PERV_EP00_BIST = 0x1003000Bull;
+
+static const uint64_t P9N2_PERV_EP01_BIST = 0x1103000Bull;
+
+static const uint64_t P9N2_PERV_EP02_BIST = 0x1203000Bull;
+
+static const uint64_t P9N2_PERV_EP03_BIST = 0x1303000Bull;
+
+static const uint64_t P9N2_PERV_EP04_BIST = 0x1403000Bull;
+
+static const uint64_t P9N2_PERV_EP05_BIST = 0x1503000Bull;
+
+static const uint64_t P9N2_PERV_EC00_BIST = 0x2003000Bull;
+
+static const uint64_t P9N2_PERV_EC01_BIST = 0x2103000Bull;
+
+static const uint64_t P9N2_PERV_EC02_BIST = 0x2203000Bull;
+
+static const uint64_t P9N2_PERV_EC03_BIST = 0x2303000Bull;
+
+static const uint64_t P9N2_PERV_EC04_BIST = 0x2403000Bull;
+
+static const uint64_t P9N2_PERV_EC05_BIST = 0x2503000Bull;
+
+static const uint64_t P9N2_PERV_EC06_BIST = 0x2603000Bull;
+
+static const uint64_t P9N2_PERV_EC07_BIST = 0x2703000Bull;
+
+static const uint64_t P9N2_PERV_EC08_BIST = 0x2803000Bull;
+
+static const uint64_t P9N2_PERV_EC09_BIST = 0x2903000Bull;
+
+static const uint64_t P9N2_PERV_EC10_BIST = 0x2A03000Bull;
+
+static const uint64_t P9N2_PERV_EC11_BIST = 0x2B03000Bull;
+
+static const uint64_t P9N2_PERV_EC12_BIST = 0x2C03000Bull;
+
+static const uint64_t P9N2_PERV_EC13_BIST = 0x2D03000Bull;
+
+static const uint64_t P9N2_PERV_EC14_BIST = 0x2E03000Bull;
+
+static const uint64_t P9N2_PERV_EC15_BIST = 0x2F03000Bull;
+
+static const uint64_t P9N2_PERV_EC16_BIST = 0x3003000Bull;
+
+static const uint64_t P9N2_PERV_EC17_BIST = 0x3103000Bull;
+
+static const uint64_t P9N2_PERV_EC18_BIST = 0x3203000Bull;
+
+static const uint64_t P9N2_PERV_EC19_BIST = 0x3303000Bull;
+
+static const uint64_t P9N2_PERV_EC20_BIST = 0x3403000Bull;
+
+static const uint64_t P9N2_PERV_EC21_BIST = 0x3503000Bull;
+
+static const uint64_t P9N2_PERV_EC22_BIST = 0x3603000Bull;
+
+static const uint64_t P9N2_PERV_EC23_BIST = 0x3703000Bull;
+
+
+static const uint64_t P9N2_PERV_BIT_SEL_REG_2 = 0x000F0008ull;
+
+static const uint64_t P9N2_PERV_PIB_BIT_SEL_REG_2 = 0x000F0008ull;
+
+
+static const uint32_t P9N2_PERV_CBS_CS_FSI = 0x00002801ull;
+
+static const uint32_t P9N2_PERV_CBS_CS_FSI_BYTE = 0x00002804ull;
+
+static const uint64_t P9N2_PERV_CBS_CS_SCOM = 0x00050001ull;
+
+static const uint64_t P9N2_PERV_PIB_CBS_CS = 0x00050001ull;
+
+
+static const uint32_t P9N2_PERV_CBS_EL_FSI = 0x00002803ull;
+
+static const uint32_t P9N2_PERV_CBS_EL_FSI_BYTE = 0x0000280Cull;
+
+static const uint64_t P9N2_PERV_CBS_EL_SCOM = 0x00050003ull;
+
+static const uint64_t P9N2_PERV_PIB_CBS_EL = 0x00050003ull;
+
+
+static const uint32_t P9N2_PERV_CBS_EL_HIST_FSI = 0x00002806ull;
+
+static const uint32_t P9N2_PERV_CBS_EL_HIST_FSI_BYTE = 0x00002818ull;
+
+static const uint64_t P9N2_PERV_CBS_EL_HIST_SCOM = 0x00050006ull;
+
+static const uint64_t P9N2_PERV_PIB_CBS_EL_HIST = 0x00050006ull;
+
+
+static const uint32_t P9N2_PERV_CBS_ENVSTAT_FSI = 0x00002804ull;
+
+static const uint32_t P9N2_PERV_CBS_ENVSTAT_FSI_BYTE = 0x00002810ull;
+
+static const uint64_t P9N2_PERV_CBS_ENVSTAT_SCOM = 0x00050004ull;
+
+static const uint64_t P9N2_PERV_PIB_CBS_ENVSTAT = 0x00050004ull;
+
+
+static const uint32_t P9N2_PERV_CBS_STAT_FSI = 0x0000280Bull;
+
+static const uint32_t P9N2_PERV_CBS_STAT_FSI_BYTE = 0x0000282Cull;
+
+static const uint64_t P9N2_PERV_CBS_STAT_SCOM = 0x0005000Bull;
+
+static const uint64_t P9N2_PERV_PIB_CBS_STAT = 0x0005000Bull;
+
+
+static const uint32_t P9N2_PERV_CBS_TR_FSI = 0x00002802ull;
+
+static const uint32_t P9N2_PERV_CBS_TR_FSI_BYTE = 0x00002808ull;
+
+static const uint64_t P9N2_PERV_CBS_TR_SCOM = 0x00050002ull;
+
+static const uint64_t P9N2_PERV_PIB_CBS_TR = 0x00050002ull;
+
+
+static const uint32_t P9N2_PERV_CBS_TR_HIST_FSI = 0x00002805ull;
+
+static const uint32_t P9N2_PERV_CBS_TR_HIST_FSI_BYTE = 0x00002814ull;
+
+static const uint64_t P9N2_PERV_CBS_TR_HIST_SCOM = 0x00050005ull;
+
+static const uint64_t P9N2_PERV_PIB_CBS_TR_HIST = 0x00050005ull;
+
+
+static const uint64_t P9N2_PERV_CC_ATOMIC_LOCK_REG = 0x000303FFull;
+
+static const uint64_t P9N2_PERV_TP_CC_ATOMIC_LOCK_REG = 0x010303FFull;
+
+static const uint64_t P9N2_PERV_N0_CC_ATOMIC_LOCK_REG = 0x020303FFull;
+
+static const uint64_t P9N2_PERV_N1_CC_ATOMIC_LOCK_REG = 0x030303FFull;
+
+static const uint64_t P9N2_PERV_N2_CC_ATOMIC_LOCK_REG = 0x040303FFull;
+
+static const uint64_t P9N2_PERV_N3_CC_ATOMIC_LOCK_REG = 0x050303FFull;
+
+static const uint64_t P9N2_PERV_XB_CC_ATOMIC_LOCK_REG = 0x060303FFull;
+
+static const uint64_t P9N2_PERV_MC01_CC_ATOMIC_LOCK_REG = 0x070303FFull;
+
+static const uint64_t P9N2_PERV_MC23_CC_ATOMIC_LOCK_REG = 0x080303FFull;
+
+static const uint64_t P9N2_PERV_OB0_CC_ATOMIC_LOCK_REG = 0x090303FFull;
+
+static const uint64_t P9N2_PERV_OB3_CC_ATOMIC_LOCK_REG = 0x0C0303FFull;
+
+static const uint64_t P9N2_PERV_PCI0_CC_ATOMIC_LOCK_REG = 0x0D0303FFull;
+
+static const uint64_t P9N2_PERV_PCI1_CC_ATOMIC_LOCK_REG = 0x0E0303FFull;
+
+static const uint64_t P9N2_PERV_PCI2_CC_ATOMIC_LOCK_REG = 0x0F0303FFull;
+
+static const uint64_t P9N2_PERV_EP00_CC_ATOMIC_LOCK_REG = 0x100303FFull;
+
+static const uint64_t P9N2_PERV_EP01_CC_ATOMIC_LOCK_REG = 0x110303FFull;
+
+static const uint64_t P9N2_PERV_EP02_CC_ATOMIC_LOCK_REG = 0x120303FFull;
+
+static const uint64_t P9N2_PERV_EP03_CC_ATOMIC_LOCK_REG = 0x130303FFull;
+
+static const uint64_t P9N2_PERV_EP04_CC_ATOMIC_LOCK_REG = 0x140303FFull;
+
+static const uint64_t P9N2_PERV_EP05_CC_ATOMIC_LOCK_REG = 0x150303FFull;
+
+static const uint64_t P9N2_PERV_EC00_CC_ATOMIC_LOCK_REG = 0x200303FFull;
+
+static const uint64_t P9N2_PERV_EC01_CC_ATOMIC_LOCK_REG = 0x210303FFull;
+
+static const uint64_t P9N2_PERV_EC02_CC_ATOMIC_LOCK_REG = 0x220303FFull;
+
+static const uint64_t P9N2_PERV_EC03_CC_ATOMIC_LOCK_REG = 0x230303FFull;
+
+static const uint64_t P9N2_PERV_EC04_CC_ATOMIC_LOCK_REG = 0x240303FFull;
+
+static const uint64_t P9N2_PERV_EC05_CC_ATOMIC_LOCK_REG = 0x250303FFull;
+
+static const uint64_t P9N2_PERV_EC06_CC_ATOMIC_LOCK_REG = 0x260303FFull;
+
+static const uint64_t P9N2_PERV_EC07_CC_ATOMIC_LOCK_REG = 0x270303FFull;
+
+static const uint64_t P9N2_PERV_EC08_CC_ATOMIC_LOCK_REG = 0x280303FFull;
+
+static const uint64_t P9N2_PERV_EC09_CC_ATOMIC_LOCK_REG = 0x290303FFull;
+
+static const uint64_t P9N2_PERV_EC10_CC_ATOMIC_LOCK_REG = 0x2A0303FFull;
+
+static const uint64_t P9N2_PERV_EC11_CC_ATOMIC_LOCK_REG = 0x2B0303FFull;
+
+static const uint64_t P9N2_PERV_EC12_CC_ATOMIC_LOCK_REG = 0x2C0303FFull;
+
+static const uint64_t P9N2_PERV_EC13_CC_ATOMIC_LOCK_REG = 0x2D0303FFull;
+
+static const uint64_t P9N2_PERV_EC14_CC_ATOMIC_LOCK_REG = 0x2E0303FFull;
+
+static const uint64_t P9N2_PERV_EC15_CC_ATOMIC_LOCK_REG = 0x2F0303FFull;
+
+static const uint64_t P9N2_PERV_EC16_CC_ATOMIC_LOCK_REG = 0x300303FFull;
+
+static const uint64_t P9N2_PERV_EC17_CC_ATOMIC_LOCK_REG = 0x310303FFull;
+
+static const uint64_t P9N2_PERV_EC18_CC_ATOMIC_LOCK_REG = 0x320303FFull;
+
+static const uint64_t P9N2_PERV_EC19_CC_ATOMIC_LOCK_REG = 0x330303FFull;
+
+static const uint64_t P9N2_PERV_EC20_CC_ATOMIC_LOCK_REG = 0x340303FFull;
+
+static const uint64_t P9N2_PERV_EC21_CC_ATOMIC_LOCK_REG = 0x350303FFull;
+
+static const uint64_t P9N2_PERV_EC22_CC_ATOMIC_LOCK_REG = 0x360303FFull;
+
+static const uint64_t P9N2_PERV_EC23_CC_ATOMIC_LOCK_REG = 0x370303FFull;
+
+
+static const uint64_t P9N2_PERV_CC_PROTECT_MODE_REG = 0x000303FEull;
+
+static const uint64_t P9N2_PERV_TP_CC_PROTECT_MODE_REG = 0x010303FEull;
+
+static const uint64_t P9N2_PERV_N0_CC_PROTECT_MODE_REG = 0x020303FEull;
+
+static const uint64_t P9N2_PERV_N1_CC_PROTECT_MODE_REG = 0x030303FEull;
+
+static const uint64_t P9N2_PERV_N2_CC_PROTECT_MODE_REG = 0x040303FEull;
+
+static const uint64_t P9N2_PERV_N3_CC_PROTECT_MODE_REG = 0x050303FEull;
+
+static const uint64_t P9N2_PERV_XB_CC_PROTECT_MODE_REG = 0x060303FEull;
+
+static const uint64_t P9N2_PERV_MC01_CC_PROTECT_MODE_REG = 0x070303FEull;
+
+static const uint64_t P9N2_PERV_MC23_CC_PROTECT_MODE_REG = 0x080303FEull;
+
+static const uint64_t P9N2_PERV_OB0_CC_PROTECT_MODE_REG = 0x090303FEull;
+
+static const uint64_t P9N2_PERV_OB3_CC_PROTECT_MODE_REG = 0x0C0303FEull;
+
+static const uint64_t P9N2_PERV_PCI0_CC_PROTECT_MODE_REG = 0x0D0303FEull;
+
+static const uint64_t P9N2_PERV_PCI1_CC_PROTECT_MODE_REG = 0x0E0303FEull;
+
+static const uint64_t P9N2_PERV_PCI2_CC_PROTECT_MODE_REG = 0x0F0303FEull;
+
+static const uint64_t P9N2_PERV_EP00_CC_PROTECT_MODE_REG = 0x100303FEull;
+
+static const uint64_t P9N2_PERV_EP01_CC_PROTECT_MODE_REG = 0x110303FEull;
+
+static const uint64_t P9N2_PERV_EP02_CC_PROTECT_MODE_REG = 0x120303FEull;
+
+static const uint64_t P9N2_PERV_EP03_CC_PROTECT_MODE_REG = 0x130303FEull;
+
+static const uint64_t P9N2_PERV_EP04_CC_PROTECT_MODE_REG = 0x140303FEull;
+
+static const uint64_t P9N2_PERV_EP05_CC_PROTECT_MODE_REG = 0x150303FEull;
+
+static const uint64_t P9N2_PERV_EC00_CC_PROTECT_MODE_REG = 0x200303FEull;
+
+static const uint64_t P9N2_PERV_EC01_CC_PROTECT_MODE_REG = 0x210303FEull;
+
+static const uint64_t P9N2_PERV_EC02_CC_PROTECT_MODE_REG = 0x220303FEull;
+
+static const uint64_t P9N2_PERV_EC03_CC_PROTECT_MODE_REG = 0x230303FEull;
+
+static const uint64_t P9N2_PERV_EC04_CC_PROTECT_MODE_REG = 0x240303FEull;
+
+static const uint64_t P9N2_PERV_EC05_CC_PROTECT_MODE_REG = 0x250303FEull;
+
+static const uint64_t P9N2_PERV_EC06_CC_PROTECT_MODE_REG = 0x260303FEull;
+
+static const uint64_t P9N2_PERV_EC07_CC_PROTECT_MODE_REG = 0x270303FEull;
+
+static const uint64_t P9N2_PERV_EC08_CC_PROTECT_MODE_REG = 0x280303FEull;
+
+static const uint64_t P9N2_PERV_EC09_CC_PROTECT_MODE_REG = 0x290303FEull;
+
+static const uint64_t P9N2_PERV_EC10_CC_PROTECT_MODE_REG = 0x2A0303FEull;
+
+static const uint64_t P9N2_PERV_EC11_CC_PROTECT_MODE_REG = 0x2B0303FEull;
+
+static const uint64_t P9N2_PERV_EC12_CC_PROTECT_MODE_REG = 0x2C0303FEull;
+
+static const uint64_t P9N2_PERV_EC13_CC_PROTECT_MODE_REG = 0x2D0303FEull;
+
+static const uint64_t P9N2_PERV_EC14_CC_PROTECT_MODE_REG = 0x2E0303FEull;
+
+static const uint64_t P9N2_PERV_EC15_CC_PROTECT_MODE_REG = 0x2F0303FEull;
+
+static const uint64_t P9N2_PERV_EC16_CC_PROTECT_MODE_REG = 0x300303FEull;
+
+static const uint64_t P9N2_PERV_EC17_CC_PROTECT_MODE_REG = 0x310303FEull;
+
+static const uint64_t P9N2_PERV_EC18_CC_PROTECT_MODE_REG = 0x320303FEull;
+
+static const uint64_t P9N2_PERV_EC19_CC_PROTECT_MODE_REG = 0x330303FEull;
+
+static const uint64_t P9N2_PERV_EC20_CC_PROTECT_MODE_REG = 0x340303FEull;
+
+static const uint64_t P9N2_PERV_EC21_CC_PROTECT_MODE_REG = 0x350303FEull;
+
+static const uint64_t P9N2_PERV_EC22_CC_PROTECT_MODE_REG = 0x360303FEull;
+
+static const uint64_t P9N2_PERV_EC23_CC_PROTECT_MODE_REG = 0x370303FEull;
+
+
+static const uint32_t P9N2_PERV_FSI2PIB_CHIPID_FSI = 0x0000100Aull;
+
+static const uint32_t P9N2_PERV_FSI2PIB_CHIPID_FSI_BYTE = 0x00001028ull;
+
+
+static const uint32_t P9N2_PERV_FSISHIFT_CHIP_ID_FSI = 0x00000C09ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_CHIP_ID_FSI_BYTE = 0x00000C24ull;
+
+
+static const uint64_t P9N2_PERV_CLK_REGION = 0x00030006ull;
+
+static const uint64_t P9N2_PERV_TP_CLK_REGION = 0x01030006ull;
+
+static const uint64_t P9N2_PERV_N0_CLK_REGION = 0x02030006ull;
+
+static const uint64_t P9N2_PERV_N1_CLK_REGION = 0x03030006ull;
+
+static const uint64_t P9N2_PERV_N2_CLK_REGION = 0x04030006ull;
+
+static const uint64_t P9N2_PERV_N3_CLK_REGION = 0x05030006ull;
+
+static const uint64_t P9N2_PERV_XB_CLK_REGION = 0x06030006ull;
+
+static const uint64_t P9N2_PERV_MC01_CLK_REGION = 0x07030006ull;
+
+static const uint64_t P9N2_PERV_MC23_CLK_REGION = 0x08030006ull;
+
+static const uint64_t P9N2_PERV_OB0_CLK_REGION = 0x09030006ull;
+
+static const uint64_t P9N2_PERV_OB3_CLK_REGION = 0x0C030006ull;
+
+static const uint64_t P9N2_PERV_PCI0_CLK_REGION = 0x0D030006ull;
+
+static const uint64_t P9N2_PERV_PCI1_CLK_REGION = 0x0E030006ull;
+
+static const uint64_t P9N2_PERV_PCI2_CLK_REGION = 0x0F030006ull;
+
+static const uint64_t P9N2_PERV_EP00_CLK_REGION = 0x10030006ull;
+
+static const uint64_t P9N2_PERV_EP01_CLK_REGION = 0x11030006ull;
+
+static const uint64_t P9N2_PERV_EP02_CLK_REGION = 0x12030006ull;
+
+static const uint64_t P9N2_PERV_EP03_CLK_REGION = 0x13030006ull;
+
+static const uint64_t P9N2_PERV_EP04_CLK_REGION = 0x14030006ull;
+
+static const uint64_t P9N2_PERV_EP05_CLK_REGION = 0x15030006ull;
+
+static const uint64_t P9N2_PERV_EC00_CLK_REGION = 0x20030006ull;
+
+static const uint64_t P9N2_PERV_EC01_CLK_REGION = 0x21030006ull;
+
+static const uint64_t P9N2_PERV_EC02_CLK_REGION = 0x22030006ull;
+
+static const uint64_t P9N2_PERV_EC03_CLK_REGION = 0x23030006ull;
+
+static const uint64_t P9N2_PERV_EC04_CLK_REGION = 0x24030006ull;
+
+static const uint64_t P9N2_PERV_EC05_CLK_REGION = 0x25030006ull;
+
+static const uint64_t P9N2_PERV_EC06_CLK_REGION = 0x26030006ull;
+
+static const uint64_t P9N2_PERV_EC07_CLK_REGION = 0x27030006ull;
+
+static const uint64_t P9N2_PERV_EC08_CLK_REGION = 0x28030006ull;
+
+static const uint64_t P9N2_PERV_EC09_CLK_REGION = 0x29030006ull;
+
+static const uint64_t P9N2_PERV_EC10_CLK_REGION = 0x2A030006ull;
+
+static const uint64_t P9N2_PERV_EC11_CLK_REGION = 0x2B030006ull;
+
+static const uint64_t P9N2_PERV_EC12_CLK_REGION = 0x2C030006ull;
+
+static const uint64_t P9N2_PERV_EC13_CLK_REGION = 0x2D030006ull;
+
+static const uint64_t P9N2_PERV_EC14_CLK_REGION = 0x2E030006ull;
+
+static const uint64_t P9N2_PERV_EC15_CLK_REGION = 0x2F030006ull;
+
+static const uint64_t P9N2_PERV_EC16_CLK_REGION = 0x30030006ull;
+
+static const uint64_t P9N2_PERV_EC17_CLK_REGION = 0x31030006ull;
+
+static const uint64_t P9N2_PERV_EC18_CLK_REGION = 0x32030006ull;
+
+static const uint64_t P9N2_PERV_EC19_CLK_REGION = 0x33030006ull;
+
+static const uint64_t P9N2_PERV_EC20_CLK_REGION = 0x34030006ull;
+
+static const uint64_t P9N2_PERV_EC21_CLK_REGION = 0x35030006ull;
+
+static const uint64_t P9N2_PERV_EC22_CLK_REGION = 0x36030006ull;
+
+static const uint64_t P9N2_PERV_EC23_CLK_REGION = 0x37030006ull;
+
+
+static const uint64_t P9N2_PERV_CLOCK_STAT_ARY = 0x0003000Aull;
+
+static const uint64_t P9N2_PERV_TP_CLOCK_STAT_ARY = 0x0103000Aull;
+
+static const uint64_t P9N2_PERV_N0_CLOCK_STAT_ARY = 0x0203000Aull;
+
+static const uint64_t P9N2_PERV_N1_CLOCK_STAT_ARY = 0x0303000Aull;
+
+static const uint64_t P9N2_PERV_N2_CLOCK_STAT_ARY = 0x0403000Aull;
+
+static const uint64_t P9N2_PERV_N3_CLOCK_STAT_ARY = 0x0503000Aull;
+
+static const uint64_t P9N2_PERV_XB_CLOCK_STAT_ARY = 0x0603000Aull;
+
+static const uint64_t P9N2_PERV_MC01_CLOCK_STAT_ARY = 0x0703000Aull;
+
+static const uint64_t P9N2_PERV_MC23_CLOCK_STAT_ARY = 0x0803000Aull;
+
+static const uint64_t P9N2_PERV_OB0_CLOCK_STAT_ARY = 0x0903000Aull;
+
+static const uint64_t P9N2_PERV_OB3_CLOCK_STAT_ARY = 0x0C03000Aull;
+
+static const uint64_t P9N2_PERV_PCI0_CLOCK_STAT_ARY = 0x0D03000Aull;
+
+static const uint64_t P9N2_PERV_PCI1_CLOCK_STAT_ARY = 0x0E03000Aull;
+
+static const uint64_t P9N2_PERV_PCI2_CLOCK_STAT_ARY = 0x0F03000Aull;
+
+static const uint64_t P9N2_PERV_EP00_CLOCK_STAT_ARY = 0x1003000Aull;
+
+static const uint64_t P9N2_PERV_EP01_CLOCK_STAT_ARY = 0x1103000Aull;
+
+static const uint64_t P9N2_PERV_EP02_CLOCK_STAT_ARY = 0x1203000Aull;
+
+static const uint64_t P9N2_PERV_EP03_CLOCK_STAT_ARY = 0x1303000Aull;
+
+static const uint64_t P9N2_PERV_EP04_CLOCK_STAT_ARY = 0x1403000Aull;
+
+static const uint64_t P9N2_PERV_EP05_CLOCK_STAT_ARY = 0x1503000Aull;
+
+static const uint64_t P9N2_PERV_EC00_CLOCK_STAT_ARY = 0x2003000Aull;
+
+static const uint64_t P9N2_PERV_EC01_CLOCK_STAT_ARY = 0x2103000Aull;
+
+static const uint64_t P9N2_PERV_EC02_CLOCK_STAT_ARY = 0x2203000Aull;
+
+static const uint64_t P9N2_PERV_EC03_CLOCK_STAT_ARY = 0x2303000Aull;
+
+static const uint64_t P9N2_PERV_EC04_CLOCK_STAT_ARY = 0x2403000Aull;
+
+static const uint64_t P9N2_PERV_EC05_CLOCK_STAT_ARY = 0x2503000Aull;
+
+static const uint64_t P9N2_PERV_EC06_CLOCK_STAT_ARY = 0x2603000Aull;
+
+static const uint64_t P9N2_PERV_EC07_CLOCK_STAT_ARY = 0x2703000Aull;
+
+static const uint64_t P9N2_PERV_EC08_CLOCK_STAT_ARY = 0x2803000Aull;
+
+static const uint64_t P9N2_PERV_EC09_CLOCK_STAT_ARY = 0x2903000Aull;
+
+static const uint64_t P9N2_PERV_EC10_CLOCK_STAT_ARY = 0x2A03000Aull;
+
+static const uint64_t P9N2_PERV_EC11_CLOCK_STAT_ARY = 0x2B03000Aull;
+
+static const uint64_t P9N2_PERV_EC12_CLOCK_STAT_ARY = 0x2C03000Aull;
+
+static const uint64_t P9N2_PERV_EC13_CLOCK_STAT_ARY = 0x2D03000Aull;
+
+static const uint64_t P9N2_PERV_EC14_CLOCK_STAT_ARY = 0x2E03000Aull;
+
+static const uint64_t P9N2_PERV_EC15_CLOCK_STAT_ARY = 0x2F03000Aull;
+
+static const uint64_t P9N2_PERV_EC16_CLOCK_STAT_ARY = 0x3003000Aull;
+
+static const uint64_t P9N2_PERV_EC17_CLOCK_STAT_ARY = 0x3103000Aull;
+
+static const uint64_t P9N2_PERV_EC18_CLOCK_STAT_ARY = 0x3203000Aull;
+
+static const uint64_t P9N2_PERV_EC19_CLOCK_STAT_ARY = 0x3303000Aull;
+
+static const uint64_t P9N2_PERV_EC20_CLOCK_STAT_ARY = 0x3403000Aull;
+
+static const uint64_t P9N2_PERV_EC21_CLOCK_STAT_ARY = 0x3503000Aull;
+
+static const uint64_t P9N2_PERV_EC22_CLOCK_STAT_ARY = 0x3603000Aull;
+
+static const uint64_t P9N2_PERV_EC23_CLOCK_STAT_ARY = 0x3703000Aull;
+
+
+static const uint64_t P9N2_PERV_CLOCK_STAT_NSL = 0x00030009ull;
+
+static const uint64_t P9N2_PERV_TP_CLOCK_STAT_NSL = 0x01030009ull;
+
+static const uint64_t P9N2_PERV_N0_CLOCK_STAT_NSL = 0x02030009ull;
+
+static const uint64_t P9N2_PERV_N1_CLOCK_STAT_NSL = 0x03030009ull;
+
+static const uint64_t P9N2_PERV_N2_CLOCK_STAT_NSL = 0x04030009ull;
+
+static const uint64_t P9N2_PERV_N3_CLOCK_STAT_NSL = 0x05030009ull;
+
+static const uint64_t P9N2_PERV_XB_CLOCK_STAT_NSL = 0x06030009ull;
+
+static const uint64_t P9N2_PERV_MC01_CLOCK_STAT_NSL = 0x07030009ull;
+
+static const uint64_t P9N2_PERV_MC23_CLOCK_STAT_NSL = 0x08030009ull;
+
+static const uint64_t P9N2_PERV_OB0_CLOCK_STAT_NSL = 0x09030009ull;
+
+static const uint64_t P9N2_PERV_OB3_CLOCK_STAT_NSL = 0x0C030009ull;
+
+static const uint64_t P9N2_PERV_PCI0_CLOCK_STAT_NSL = 0x0D030009ull;
+
+static const uint64_t P9N2_PERV_PCI1_CLOCK_STAT_NSL = 0x0E030009ull;
+
+static const uint64_t P9N2_PERV_PCI2_CLOCK_STAT_NSL = 0x0F030009ull;
+
+static const uint64_t P9N2_PERV_EP00_CLOCK_STAT_NSL = 0x10030009ull;
+
+static const uint64_t P9N2_PERV_EP01_CLOCK_STAT_NSL = 0x11030009ull;
+
+static const uint64_t P9N2_PERV_EP02_CLOCK_STAT_NSL = 0x12030009ull;
+
+static const uint64_t P9N2_PERV_EP03_CLOCK_STAT_NSL = 0x13030009ull;
+
+static const uint64_t P9N2_PERV_EP04_CLOCK_STAT_NSL = 0x14030009ull;
+
+static const uint64_t P9N2_PERV_EP05_CLOCK_STAT_NSL = 0x15030009ull;
+
+static const uint64_t P9N2_PERV_EC00_CLOCK_STAT_NSL = 0x20030009ull;
+
+static const uint64_t P9N2_PERV_EC01_CLOCK_STAT_NSL = 0x21030009ull;
+
+static const uint64_t P9N2_PERV_EC02_CLOCK_STAT_NSL = 0x22030009ull;
+
+static const uint64_t P9N2_PERV_EC03_CLOCK_STAT_NSL = 0x23030009ull;
+
+static const uint64_t P9N2_PERV_EC04_CLOCK_STAT_NSL = 0x24030009ull;
+
+static const uint64_t P9N2_PERV_EC05_CLOCK_STAT_NSL = 0x25030009ull;
+
+static const uint64_t P9N2_PERV_EC06_CLOCK_STAT_NSL = 0x26030009ull;
+
+static const uint64_t P9N2_PERV_EC07_CLOCK_STAT_NSL = 0x27030009ull;
+
+static const uint64_t P9N2_PERV_EC08_CLOCK_STAT_NSL = 0x28030009ull;
+
+static const uint64_t P9N2_PERV_EC09_CLOCK_STAT_NSL = 0x29030009ull;
+
+static const uint64_t P9N2_PERV_EC10_CLOCK_STAT_NSL = 0x2A030009ull;
+
+static const uint64_t P9N2_PERV_EC11_CLOCK_STAT_NSL = 0x2B030009ull;
+
+static const uint64_t P9N2_PERV_EC12_CLOCK_STAT_NSL = 0x2C030009ull;
+
+static const uint64_t P9N2_PERV_EC13_CLOCK_STAT_NSL = 0x2D030009ull;
+
+static const uint64_t P9N2_PERV_EC14_CLOCK_STAT_NSL = 0x2E030009ull;
+
+static const uint64_t P9N2_PERV_EC15_CLOCK_STAT_NSL = 0x2F030009ull;
+
+static const uint64_t P9N2_PERV_EC16_CLOCK_STAT_NSL = 0x30030009ull;
+
+static const uint64_t P9N2_PERV_EC17_CLOCK_STAT_NSL = 0x31030009ull;
+
+static const uint64_t P9N2_PERV_EC18_CLOCK_STAT_NSL = 0x32030009ull;
+
+static const uint64_t P9N2_PERV_EC19_CLOCK_STAT_NSL = 0x33030009ull;
+
+static const uint64_t P9N2_PERV_EC20_CLOCK_STAT_NSL = 0x34030009ull;
+
+static const uint64_t P9N2_PERV_EC21_CLOCK_STAT_NSL = 0x35030009ull;
+
+static const uint64_t P9N2_PERV_EC22_CLOCK_STAT_NSL = 0x36030009ull;
+
+static const uint64_t P9N2_PERV_EC23_CLOCK_STAT_NSL = 0x37030009ull;
+
+
+static const uint64_t P9N2_PERV_CLOCK_STAT_SL = 0x00030008ull;
+
+static const uint64_t P9N2_PERV_TP_CLOCK_STAT_SL = 0x01030008ull;
+
+static const uint64_t P9N2_PERV_N0_CLOCK_STAT_SL = 0x02030008ull;
+
+static const uint64_t P9N2_PERV_N1_CLOCK_STAT_SL = 0x03030008ull;
+
+static const uint64_t P9N2_PERV_N2_CLOCK_STAT_SL = 0x04030008ull;
+
+static const uint64_t P9N2_PERV_N3_CLOCK_STAT_SL = 0x05030008ull;
+
+static const uint64_t P9N2_PERV_XB_CLOCK_STAT_SL = 0x06030008ull;
+
+static const uint64_t P9N2_PERV_MC01_CLOCK_STAT_SL = 0x07030008ull;
+
+static const uint64_t P9N2_PERV_MC23_CLOCK_STAT_SL = 0x08030008ull;
+
+static const uint64_t P9N2_PERV_OB0_CLOCK_STAT_SL = 0x09030008ull;
+
+static const uint64_t P9N2_PERV_OB3_CLOCK_STAT_SL = 0x0C030008ull;
+
+static const uint64_t P9N2_PERV_PCI0_CLOCK_STAT_SL = 0x0D030008ull;
+
+static const uint64_t P9N2_PERV_PCI1_CLOCK_STAT_SL = 0x0E030008ull;
+
+static const uint64_t P9N2_PERV_PCI2_CLOCK_STAT_SL = 0x0F030008ull;
+
+static const uint64_t P9N2_PERV_EP00_CLOCK_STAT_SL = 0x10030008ull;
+
+static const uint64_t P9N2_PERV_EP01_CLOCK_STAT_SL = 0x11030008ull;
+
+static const uint64_t P9N2_PERV_EP02_CLOCK_STAT_SL = 0x12030008ull;
+
+static const uint64_t P9N2_PERV_EP03_CLOCK_STAT_SL = 0x13030008ull;
+
+static const uint64_t P9N2_PERV_EP04_CLOCK_STAT_SL = 0x14030008ull;
+
+static const uint64_t P9N2_PERV_EP05_CLOCK_STAT_SL = 0x15030008ull;
+
+static const uint64_t P9N2_PERV_EC00_CLOCK_STAT_SL = 0x20030008ull;
+
+static const uint64_t P9N2_PERV_EC01_CLOCK_STAT_SL = 0x21030008ull;
+
+static const uint64_t P9N2_PERV_EC02_CLOCK_STAT_SL = 0x22030008ull;
+
+static const uint64_t P9N2_PERV_EC03_CLOCK_STAT_SL = 0x23030008ull;
+
+static const uint64_t P9N2_PERV_EC04_CLOCK_STAT_SL = 0x24030008ull;
+
+static const uint64_t P9N2_PERV_EC05_CLOCK_STAT_SL = 0x25030008ull;
+
+static const uint64_t P9N2_PERV_EC06_CLOCK_STAT_SL = 0x26030008ull;
+
+static const uint64_t P9N2_PERV_EC07_CLOCK_STAT_SL = 0x27030008ull;
+
+static const uint64_t P9N2_PERV_EC08_CLOCK_STAT_SL = 0x28030008ull;
+
+static const uint64_t P9N2_PERV_EC09_CLOCK_STAT_SL = 0x29030008ull;
+
+static const uint64_t P9N2_PERV_EC10_CLOCK_STAT_SL = 0x2A030008ull;
+
+static const uint64_t P9N2_PERV_EC11_CLOCK_STAT_SL = 0x2B030008ull;
+
+static const uint64_t P9N2_PERV_EC12_CLOCK_STAT_SL = 0x2C030008ull;
+
+static const uint64_t P9N2_PERV_EC13_CLOCK_STAT_SL = 0x2D030008ull;
+
+static const uint64_t P9N2_PERV_EC14_CLOCK_STAT_SL = 0x2E030008ull;
+
+static const uint64_t P9N2_PERV_EC15_CLOCK_STAT_SL = 0x2F030008ull;
+
+static const uint64_t P9N2_PERV_EC16_CLOCK_STAT_SL = 0x30030008ull;
+
+static const uint64_t P9N2_PERV_EC17_CLOCK_STAT_SL = 0x31030008ull;
+
+static const uint64_t P9N2_PERV_EC18_CLOCK_STAT_SL = 0x32030008ull;
+
+static const uint64_t P9N2_PERV_EC19_CLOCK_STAT_SL = 0x33030008ull;
+
+static const uint64_t P9N2_PERV_EC20_CLOCK_STAT_SL = 0x34030008ull;
+
+static const uint64_t P9N2_PERV_EC21_CLOCK_STAT_SL = 0x35030008ull;
+
+static const uint64_t P9N2_PERV_EC22_CLOCK_STAT_SL = 0x36030008ull;
+
+static const uint64_t P9N2_PERV_EC23_CLOCK_STAT_SL = 0x37030008ull;
+
+
+static const uint64_t P9N2_PERV_CMD_WRDAT = 0x00030000ull;
+
+static const uint64_t P9N2_PERV_PIB_CMD_WRDAT = 0x00030000ull;
+
+static const uint64_t P9N2_PERV_0_PIB2OPB0_CMD_WRDAT = 0x00020000ull;
+
+static const uint64_t P9N2_PERV_0_PIB2OPB1_CMD_WRDAT = 0x00020010ull;
+
+static const uint64_t P9N2_PERV_PIB2OPB0_CMD_WRDAT = 0x00020000ull;
+
+static const uint64_t P9N2_PERV_PIB2OPB1_CMD_WRDAT = 0x00020010ull;
+
+
+static const uint32_t P9N2_PERV_FSI2PIB_COMMAND_REGISTER_FSI = 0x00001002ull;
+
+static const uint32_t P9N2_PERV_FSI2PIB_COMMAND_REGISTER_FSI_BYTE = 0x00001008ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_COMMAND_REGISTER_FSI = 0x00000C01ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_COMMAND_REGISTER_FSI_BYTE = 0x00000C04ull;
+
+
+static const uint64_t P9N2_PERV_0_FSII2C_COMMAND_REGISTER_A = 0x00001801ull;
+
+static const uint32_t P9N2_PERV_FSII2C_COMMAND_REGISTER_A = 0x00001801ull;
+
+
+static const uint32_t P9N2_PERV_FSI2PIB_COMPLEMENT_MASK_FSI = 0x0000100Cull;
+
+static const uint32_t P9N2_PERV_FSI2PIB_COMPLEMENT_MASK_FSI_BYTE = 0x00001030ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_COMPLEMENT_MASK_FSI = 0x00000C0Cull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_COMPLEMENT_MASK_FSI_BYTE = 0x00000C30ull;
+
+
+static const uint64_t P9N2_PERV_CONTROL_REG = 0x00050012ull;
+
+static const uint64_t P9N2_PERV_TP_CONTROL_REG = 0x01050012ull;
+
+static const uint64_t P9N2_PERV_N0_CONTROL_REG = 0x02050012ull;
+
+static const uint64_t P9N2_PERV_N1_CONTROL_REG = 0x03050012ull;
+
+static const uint64_t P9N2_PERV_N2_CONTROL_REG = 0x04050012ull;
+
+static const uint64_t P9N2_PERV_N3_CONTROL_REG = 0x05050012ull;
+
+static const uint64_t P9N2_PERV_XB_CONTROL_REG = 0x06050012ull;
+
+static const uint64_t P9N2_PERV_MC01_CONTROL_REG = 0x07050012ull;
+
+static const uint64_t P9N2_PERV_MC23_CONTROL_REG = 0x08050012ull;
+
+static const uint64_t P9N2_PERV_OB0_CONTROL_REG = 0x09050012ull;
+
+static const uint64_t P9N2_PERV_OB3_CONTROL_REG = 0x0C050012ull;
+
+static const uint64_t P9N2_PERV_PCI0_CONTROL_REG = 0x0D050012ull;
+
+static const uint64_t P9N2_PERV_PCI1_CONTROL_REG = 0x0E050012ull;
+
+static const uint64_t P9N2_PERV_PCI2_CONTROL_REG = 0x0F050012ull;
+
+static const uint64_t P9N2_PERV_EP00_CONTROL_REG = 0x10050012ull;
+
+static const uint64_t P9N2_PERV_EP01_CONTROL_REG = 0x11050012ull;
+
+static const uint64_t P9N2_PERV_EP02_CONTROL_REG = 0x12050012ull;
+
+static const uint64_t P9N2_PERV_EP03_CONTROL_REG = 0x13050012ull;
+
+static const uint64_t P9N2_PERV_EP04_CONTROL_REG = 0x14050012ull;
+
+static const uint64_t P9N2_PERV_EP05_CONTROL_REG = 0x15050012ull;
+
+static const uint64_t P9N2_PERV_EC00_CONTROL_REG = 0x20050012ull;
+
+static const uint64_t P9N2_PERV_EC01_CONTROL_REG = 0x21050012ull;
+
+static const uint64_t P9N2_PERV_EC02_CONTROL_REG = 0x22050012ull;
+
+static const uint64_t P9N2_PERV_EC03_CONTROL_REG = 0x23050012ull;
+
+static const uint64_t P9N2_PERV_EC04_CONTROL_REG = 0x24050012ull;
+
+static const uint64_t P9N2_PERV_EC05_CONTROL_REG = 0x25050012ull;
+
+static const uint64_t P9N2_PERV_EC06_CONTROL_REG = 0x26050012ull;
+
+static const uint64_t P9N2_PERV_EC07_CONTROL_REG = 0x27050012ull;
+
+static const uint64_t P9N2_PERV_EC08_CONTROL_REG = 0x28050012ull;
+
+static const uint64_t P9N2_PERV_EC09_CONTROL_REG = 0x29050012ull;
+
+static const uint64_t P9N2_PERV_EC10_CONTROL_REG = 0x2A050012ull;
+
+static const uint64_t P9N2_PERV_EC11_CONTROL_REG = 0x2B050012ull;
+
+static const uint64_t P9N2_PERV_EC12_CONTROL_REG = 0x2C050012ull;
+
+static const uint64_t P9N2_PERV_EC13_CONTROL_REG = 0x2D050012ull;
+
+static const uint64_t P9N2_PERV_EC14_CONTROL_REG = 0x2E050012ull;
+
+static const uint64_t P9N2_PERV_EC15_CONTROL_REG = 0x2F050012ull;
+
+static const uint64_t P9N2_PERV_EC16_CONTROL_REG = 0x30050012ull;
+
+static const uint64_t P9N2_PERV_EC17_CONTROL_REG = 0x31050012ull;
+
+static const uint64_t P9N2_PERV_EC18_CONTROL_REG = 0x32050012ull;
+
+static const uint64_t P9N2_PERV_EC19_CONTROL_REG = 0x33050012ull;
+
+static const uint64_t P9N2_PERV_EC20_CONTROL_REG = 0x34050012ull;
+
+static const uint64_t P9N2_PERV_EC21_CONTROL_REG = 0x35050012ull;
+
+static const uint64_t P9N2_PERV_EC22_CONTROL_REG = 0x36050012ull;
+
+static const uint64_t P9N2_PERV_EC23_CONTROL_REG = 0x37050012ull;
+
+
+static const uint64_t P9N2_PERV_CPLT_CONF0 = 0x00000008ull;
+
+static const uint64_t P9N2_PERV_TP_CPLT_CONF0 = 0x01000008ull;
+
+static const uint64_t P9N2_PERV_CPLT_CONF0_OR = 0x00000018ull;
+
+static const uint64_t P9N2_PERV_TP_CPLT_CONF0_OR = 0x01000018ull;
+
+static const uint64_t P9N2_PERV_CPLT_CONF0_CLEAR = 0x00000028ull;
+
+static const uint64_t P9N2_PERV_TP_CPLT_CONF0_CLEAR = 0x01000028ull;
+
+static const uint64_t P9N2_PERV_N0_CPLT_CONF0 = 0x02000008ull;
+
+static const uint64_t P9N2_PERV_N0_CPLT_CONF0_OR = 0x02000018ull;
+
+static const uint64_t P9N2_PERV_N0_CPLT_CONF0_CLEAR = 0x02000028ull;
+
+static const uint64_t P9N2_PERV_N1_CPLT_CONF0 = 0x03000008ull;
+
+static const uint64_t P9N2_PERV_N1_CPLT_CONF0_OR = 0x03000018ull;
+
+static const uint64_t P9N2_PERV_N1_CPLT_CONF0_CLEAR = 0x03000028ull;
+
+static const uint64_t P9N2_PERV_N2_CPLT_CONF0 = 0x04000008ull;
+
+static const uint64_t P9N2_PERV_N2_CPLT_CONF0_OR = 0x04000018ull;
+
+static const uint64_t P9N2_PERV_N2_CPLT_CONF0_CLEAR = 0x04000028ull;
+
+static const uint64_t P9N2_PERV_N3_CPLT_CONF0 = 0x05000008ull;
+
+static const uint64_t P9N2_PERV_N3_CPLT_CONF0_OR = 0x05000018ull;
+
+static const uint64_t P9N2_PERV_N3_CPLT_CONF0_CLEAR = 0x05000028ull;
+
+static const uint64_t P9N2_PERV_XB_CPLT_CONF0 = 0x06000008ull;
+
+static const uint64_t P9N2_PERV_XB_CPLT_CONF0_OR = 0x06000018ull;
+
+static const uint64_t P9N2_PERV_XB_CPLT_CONF0_CLEAR = 0x06000028ull;
+
+static const uint64_t P9N2_PERV_MC01_CPLT_CONF0 = 0x07000008ull;
+
+static const uint64_t P9N2_PERV_MC01_CPLT_CONF0_OR = 0x07000018ull;
+
+static const uint64_t P9N2_PERV_MC01_CPLT_CONF0_CLEAR = 0x07000028ull;
+
+static const uint64_t P9N2_PERV_MC23_CPLT_CONF0 = 0x08000008ull;
+
+static const uint64_t P9N2_PERV_MC23_CPLT_CONF0_OR = 0x08000018ull;
+
+static const uint64_t P9N2_PERV_MC23_CPLT_CONF0_CLEAR = 0x08000028ull;
+
+static const uint64_t P9N2_PERV_OB0_CPLT_CONF0 = 0x09000008ull;
+
+static const uint64_t P9N2_PERV_OB0_CPLT_CONF0_OR = 0x09000018ull;
+
+static const uint64_t P9N2_PERV_OB0_CPLT_CONF0_CLEAR = 0x09000028ull;
+
+static const uint64_t P9N2_PERV_OB3_CPLT_CONF0 = 0x0C000008ull;
+
+static const uint64_t P9N2_PERV_OB3_CPLT_CONF0_OR = 0x0C000018ull;
+
+static const uint64_t P9N2_PERV_OB3_CPLT_CONF0_CLEAR = 0x0C000028ull;
+
+static const uint64_t P9N2_PERV_PCI0_CPLT_CONF0 = 0x0D000008ull;
+
+static const uint64_t P9N2_PERV_PCI0_CPLT_CONF0_OR = 0x0D000018ull;
+
+static const uint64_t P9N2_PERV_PCI0_CPLT_CONF0_CLEAR = 0x0D000028ull;
+
+static const uint64_t P9N2_PERV_PCI1_CPLT_CONF0 = 0x0E000008ull;
+
+static const uint64_t P9N2_PERV_PCI1_CPLT_CONF0_OR = 0x0E000018ull;
+
+static const uint64_t P9N2_PERV_PCI1_CPLT_CONF0_CLEAR = 0x0E000028ull;
+
+static const uint64_t P9N2_PERV_PCI2_CPLT_CONF0 = 0x0F000008ull;
+
+static const uint64_t P9N2_PERV_PCI2_CPLT_CONF0_OR = 0x0F000018ull;
+
+static const uint64_t P9N2_PERV_PCI2_CPLT_CONF0_CLEAR = 0x0F000028ull;
+
+static const uint64_t P9N2_PERV_EP00_CPLT_CONF0 = 0x10000008ull;
+
+static const uint64_t P9N2_PERV_EP00_CPLT_CONF0_OR = 0x10000018ull;
+
+static const uint64_t P9N2_PERV_EP00_CPLT_CONF0_CLEAR = 0x10000028ull;
+
+static const uint64_t P9N2_PERV_EP01_CPLT_CONF0 = 0x11000008ull;
+
+static const uint64_t P9N2_PERV_EP01_CPLT_CONF0_OR = 0x11000018ull;
+
+static const uint64_t P9N2_PERV_EP01_CPLT_CONF0_CLEAR = 0x11000028ull;
+
+static const uint64_t P9N2_PERV_EP02_CPLT_CONF0 = 0x12000008ull;
+
+static const uint64_t P9N2_PERV_EP02_CPLT_CONF0_OR = 0x12000018ull;
+
+static const uint64_t P9N2_PERV_EP02_CPLT_CONF0_CLEAR = 0x12000028ull;
+
+static const uint64_t P9N2_PERV_EP03_CPLT_CONF0 = 0x13000008ull;
+
+static const uint64_t P9N2_PERV_EP03_CPLT_CONF0_OR = 0x13000018ull;
+
+static const uint64_t P9N2_PERV_EP03_CPLT_CONF0_CLEAR = 0x13000028ull;
+
+static const uint64_t P9N2_PERV_EP04_CPLT_CONF0 = 0x14000008ull;
+
+static const uint64_t P9N2_PERV_EP04_CPLT_CONF0_OR = 0x14000018ull;
+
+static const uint64_t P9N2_PERV_EP04_CPLT_CONF0_CLEAR = 0x14000028ull;
+
+static const uint64_t P9N2_PERV_EP05_CPLT_CONF0 = 0x15000008ull;
+
+static const uint64_t P9N2_PERV_EP05_CPLT_CONF0_OR = 0x15000018ull;
+
+static const uint64_t P9N2_PERV_EP05_CPLT_CONF0_CLEAR = 0x15000028ull;
+
+static const uint64_t P9N2_PERV_EC00_CPLT_CONF0 = 0x20000008ull;
+
+static const uint64_t P9N2_PERV_EC00_CPLT_CONF0_OR = 0x20000018ull;
+
+static const uint64_t P9N2_PERV_EC00_CPLT_CONF0_CLEAR = 0x20000028ull;
+
+static const uint64_t P9N2_PERV_EC01_CPLT_CONF0 = 0x21000008ull;
+
+static const uint64_t P9N2_PERV_EC01_CPLT_CONF0_OR = 0x21000018ull;
+
+static const uint64_t P9N2_PERV_EC01_CPLT_CONF0_CLEAR = 0x21000028ull;
+
+static const uint64_t P9N2_PERV_EC02_CPLT_CONF0 = 0x22000008ull;
+
+static const uint64_t P9N2_PERV_EC02_CPLT_CONF0_OR = 0x22000018ull;
+
+static const uint64_t P9N2_PERV_EC02_CPLT_CONF0_CLEAR = 0x22000028ull;
+
+static const uint64_t P9N2_PERV_EC03_CPLT_CONF0 = 0x23000008ull;
+
+static const uint64_t P9N2_PERV_EC03_CPLT_CONF0_OR = 0x23000018ull;
+
+static const uint64_t P9N2_PERV_EC03_CPLT_CONF0_CLEAR = 0x23000028ull;
+
+static const uint64_t P9N2_PERV_EC04_CPLT_CONF0 = 0x24000008ull;
+
+static const uint64_t P9N2_PERV_EC04_CPLT_CONF0_OR = 0x24000018ull;
+
+static const uint64_t P9N2_PERV_EC04_CPLT_CONF0_CLEAR = 0x24000028ull;
+
+static const uint64_t P9N2_PERV_EC05_CPLT_CONF0 = 0x25000008ull;
+
+static const uint64_t P9N2_PERV_EC05_CPLT_CONF0_OR = 0x25000018ull;
+
+static const uint64_t P9N2_PERV_EC05_CPLT_CONF0_CLEAR = 0x25000028ull;
+
+static const uint64_t P9N2_PERV_EC06_CPLT_CONF0 = 0x26000008ull;
+
+static const uint64_t P9N2_PERV_EC06_CPLT_CONF0_OR = 0x26000018ull;
+
+static const uint64_t P9N2_PERV_EC06_CPLT_CONF0_CLEAR = 0x26000028ull;
+
+static const uint64_t P9N2_PERV_EC07_CPLT_CONF0 = 0x27000008ull;
+
+static const uint64_t P9N2_PERV_EC07_CPLT_CONF0_OR = 0x27000018ull;
+
+static const uint64_t P9N2_PERV_EC07_CPLT_CONF0_CLEAR = 0x27000028ull;
+
+static const uint64_t P9N2_PERV_EC08_CPLT_CONF0 = 0x28000008ull;
+
+static const uint64_t P9N2_PERV_EC08_CPLT_CONF0_OR = 0x28000018ull;
+
+static const uint64_t P9N2_PERV_EC08_CPLT_CONF0_CLEAR = 0x28000028ull;
+
+static const uint64_t P9N2_PERV_EC09_CPLT_CONF0 = 0x29000008ull;
+
+static const uint64_t P9N2_PERV_EC09_CPLT_CONF0_OR = 0x29000018ull;
+
+static const uint64_t P9N2_PERV_EC09_CPLT_CONF0_CLEAR = 0x29000028ull;
+
+static const uint64_t P9N2_PERV_EC10_CPLT_CONF0 = 0x2A000008ull;
+
+static const uint64_t P9N2_PERV_EC10_CPLT_CONF0_OR = 0x2A000018ull;
+
+static const uint64_t P9N2_PERV_EC10_CPLT_CONF0_CLEAR = 0x2A000028ull;
+
+static const uint64_t P9N2_PERV_EC11_CPLT_CONF0 = 0x2B000008ull;
+
+static const uint64_t P9N2_PERV_EC11_CPLT_CONF0_OR = 0x2B000018ull;
+
+static const uint64_t P9N2_PERV_EC11_CPLT_CONF0_CLEAR = 0x2B000028ull;
+
+static const uint64_t P9N2_PERV_EC12_CPLT_CONF0 = 0x2C000008ull;
+
+static const uint64_t P9N2_PERV_EC12_CPLT_CONF0_OR = 0x2C000018ull;
+
+static const uint64_t P9N2_PERV_EC12_CPLT_CONF0_CLEAR = 0x2C000028ull;
+
+static const uint64_t P9N2_PERV_EC13_CPLT_CONF0 = 0x2D000008ull;
+
+static const uint64_t P9N2_PERV_EC13_CPLT_CONF0_OR = 0x2D000018ull;
+
+static const uint64_t P9N2_PERV_EC13_CPLT_CONF0_CLEAR = 0x2D000028ull;
+
+static const uint64_t P9N2_PERV_EC14_CPLT_CONF0 = 0x2E000008ull;
+
+static const uint64_t P9N2_PERV_EC14_CPLT_CONF0_OR = 0x2E000018ull;
+
+static const uint64_t P9N2_PERV_EC14_CPLT_CONF0_CLEAR = 0x2E000028ull;
+
+static const uint64_t P9N2_PERV_EC15_CPLT_CONF0 = 0x2F000008ull;
+
+static const uint64_t P9N2_PERV_EC15_CPLT_CONF0_OR = 0x2F000018ull;
+
+static const uint64_t P9N2_PERV_EC15_CPLT_CONF0_CLEAR = 0x2F000028ull;
+
+static const uint64_t P9N2_PERV_EC16_CPLT_CONF0 = 0x30000008ull;
+
+static const uint64_t P9N2_PERV_EC16_CPLT_CONF0_OR = 0x30000018ull;
+
+static const uint64_t P9N2_PERV_EC16_CPLT_CONF0_CLEAR = 0x30000028ull;
+
+static const uint64_t P9N2_PERV_EC17_CPLT_CONF0 = 0x31000008ull;
+
+static const uint64_t P9N2_PERV_EC17_CPLT_CONF0_OR = 0x31000018ull;
+
+static const uint64_t P9N2_PERV_EC17_CPLT_CONF0_CLEAR = 0x31000028ull;
+
+static const uint64_t P9N2_PERV_EC18_CPLT_CONF0 = 0x32000008ull;
+
+static const uint64_t P9N2_PERV_EC18_CPLT_CONF0_OR = 0x32000018ull;
+
+static const uint64_t P9N2_PERV_EC18_CPLT_CONF0_CLEAR = 0x32000028ull;
+
+static const uint64_t P9N2_PERV_EC19_CPLT_CONF0 = 0x33000008ull;
+
+static const uint64_t P9N2_PERV_EC19_CPLT_CONF0_OR = 0x33000018ull;
+
+static const uint64_t P9N2_PERV_EC19_CPLT_CONF0_CLEAR = 0x33000028ull;
+
+static const uint64_t P9N2_PERV_EC20_CPLT_CONF0 = 0x34000008ull;
+
+static const uint64_t P9N2_PERV_EC20_CPLT_CONF0_OR = 0x34000018ull;
+
+static const uint64_t P9N2_PERV_EC20_CPLT_CONF0_CLEAR = 0x34000028ull;
+
+static const uint64_t P9N2_PERV_EC21_CPLT_CONF0 = 0x35000008ull;
+
+static const uint64_t P9N2_PERV_EC21_CPLT_CONF0_OR = 0x35000018ull;
+
+static const uint64_t P9N2_PERV_EC21_CPLT_CONF0_CLEAR = 0x35000028ull;
+
+static const uint64_t P9N2_PERV_EC22_CPLT_CONF0 = 0x36000008ull;
+
+static const uint64_t P9N2_PERV_EC22_CPLT_CONF0_OR = 0x36000018ull;
+
+static const uint64_t P9N2_PERV_EC22_CPLT_CONF0_CLEAR = 0x36000028ull;
+
+static const uint64_t P9N2_PERV_EC23_CPLT_CONF0 = 0x37000008ull;
+
+static const uint64_t P9N2_PERV_EC23_CPLT_CONF0_OR = 0x37000018ull;
+
+static const uint64_t P9N2_PERV_EC23_CPLT_CONF0_CLEAR = 0x37000028ull;
+
+
+static const uint64_t P9N2_PERV_CPLT_CONF1 = 0x00000009ull;
+
+static const uint64_t P9N2_PERV_TP_CPLT_CONF1 = 0x01000009ull;
+
+static const uint64_t P9N2_PERV_CPLT_CONF1_OR = 0x00000019ull;
+
+static const uint64_t P9N2_PERV_TP_CPLT_CONF1_OR = 0x01000019ull;
+
+static const uint64_t P9N2_PERV_CPLT_CONF1_CLEAR = 0x00000029ull;
+
+static const uint64_t P9N2_PERV_TP_CPLT_CONF1_CLEAR = 0x01000029ull;
+
+static const uint64_t P9N2_PERV_N0_CPLT_CONF1 = 0x02000009ull;
+
+static const uint64_t P9N2_PERV_N0_CPLT_CONF1_OR = 0x02000019ull;
+
+static const uint64_t P9N2_PERV_N0_CPLT_CONF1_CLEAR = 0x02000029ull;
+
+static const uint64_t P9N2_PERV_N1_CPLT_CONF1 = 0x03000009ull;
+
+static const uint64_t P9N2_PERV_N1_CPLT_CONF1_OR = 0x03000019ull;
+
+static const uint64_t P9N2_PERV_N1_CPLT_CONF1_CLEAR = 0x03000029ull;
+
+static const uint64_t P9N2_PERV_N2_CPLT_CONF1 = 0x04000009ull;
+
+static const uint64_t P9N2_PERV_N2_CPLT_CONF1_OR = 0x04000019ull;
+
+static const uint64_t P9N2_PERV_N2_CPLT_CONF1_CLEAR = 0x04000029ull;
+
+static const uint64_t P9N2_PERV_N3_CPLT_CONF1 = 0x05000009ull;
+
+static const uint64_t P9N2_PERV_N3_CPLT_CONF1_OR = 0x05000019ull;
+
+static const uint64_t P9N2_PERV_N3_CPLT_CONF1_CLEAR = 0x05000029ull;
+
+static const uint64_t P9N2_PERV_XB_CPLT_CONF1 = 0x06000009ull;
+
+static const uint64_t P9N2_PERV_XB_CPLT_CONF1_OR = 0x06000019ull;
+
+static const uint64_t P9N2_PERV_XB_CPLT_CONF1_CLEAR = 0x06000029ull;
+
+static const uint64_t P9N2_PERV_MC01_CPLT_CONF1 = 0x07000009ull;
+
+static const uint64_t P9N2_PERV_MC01_CPLT_CONF1_OR = 0x07000019ull;
+
+static const uint64_t P9N2_PERV_MC01_CPLT_CONF1_CLEAR = 0x07000029ull;
+
+static const uint64_t P9N2_PERV_MC23_CPLT_CONF1 = 0x08000009ull;
+
+static const uint64_t P9N2_PERV_MC23_CPLT_CONF1_OR = 0x08000019ull;
+
+static const uint64_t P9N2_PERV_MC23_CPLT_CONF1_CLEAR = 0x08000029ull;
+
+static const uint64_t P9N2_PERV_OB0_CPLT_CONF1 = 0x09000009ull;
+
+static const uint64_t P9N2_PERV_OB0_CPLT_CONF1_OR = 0x09000019ull;
+
+static const uint64_t P9N2_PERV_OB0_CPLT_CONF1_CLEAR = 0x09000029ull;
+
+static const uint64_t P9N2_PERV_OB3_CPLT_CONF1 = 0x0C000009ull;
+
+static const uint64_t P9N2_PERV_OB3_CPLT_CONF1_OR = 0x0C000019ull;
+
+static const uint64_t P9N2_PERV_OB3_CPLT_CONF1_CLEAR = 0x0C000029ull;
+
+static const uint64_t P9N2_PERV_PCI0_CPLT_CONF1 = 0x0D000009ull;
+
+static const uint64_t P9N2_PERV_PCI0_CPLT_CONF1_OR = 0x0D000019ull;
+
+static const uint64_t P9N2_PERV_PCI0_CPLT_CONF1_CLEAR = 0x0D000029ull;
+
+static const uint64_t P9N2_PERV_PCI1_CPLT_CONF1 = 0x0E000009ull;
+
+static const uint64_t P9N2_PERV_PCI1_CPLT_CONF1_OR = 0x0E000019ull;
+
+static const uint64_t P9N2_PERV_PCI1_CPLT_CONF1_CLEAR = 0x0E000029ull;
+
+static const uint64_t P9N2_PERV_PCI2_CPLT_CONF1 = 0x0F000009ull;
+
+static const uint64_t P9N2_PERV_PCI2_CPLT_CONF1_OR = 0x0F000019ull;
+
+static const uint64_t P9N2_PERV_PCI2_CPLT_CONF1_CLEAR = 0x0F000029ull;
+
+static const uint64_t P9N2_PERV_EP00_CPLT_CONF1 = 0x10000009ull;
+
+static const uint64_t P9N2_PERV_EP00_CPLT_CONF1_OR = 0x10000019ull;
+
+static const uint64_t P9N2_PERV_EP00_CPLT_CONF1_CLEAR = 0x10000029ull;
+
+static const uint64_t P9N2_PERV_EP01_CPLT_CONF1 = 0x11000009ull;
+
+static const uint64_t P9N2_PERV_EP01_CPLT_CONF1_OR = 0x11000019ull;
+
+static const uint64_t P9N2_PERV_EP01_CPLT_CONF1_CLEAR = 0x11000029ull;
+
+static const uint64_t P9N2_PERV_EP02_CPLT_CONF1 = 0x12000009ull;
+
+static const uint64_t P9N2_PERV_EP02_CPLT_CONF1_OR = 0x12000019ull;
+
+static const uint64_t P9N2_PERV_EP02_CPLT_CONF1_CLEAR = 0x12000029ull;
+
+static const uint64_t P9N2_PERV_EP03_CPLT_CONF1 = 0x13000009ull;
+
+static const uint64_t P9N2_PERV_EP03_CPLT_CONF1_OR = 0x13000019ull;
+
+static const uint64_t P9N2_PERV_EP03_CPLT_CONF1_CLEAR = 0x13000029ull;
+
+static const uint64_t P9N2_PERV_EP04_CPLT_CONF1 = 0x14000009ull;
+
+static const uint64_t P9N2_PERV_EP04_CPLT_CONF1_OR = 0x14000019ull;
+
+static const uint64_t P9N2_PERV_EP04_CPLT_CONF1_CLEAR = 0x14000029ull;
+
+static const uint64_t P9N2_PERV_EP05_CPLT_CONF1 = 0x15000009ull;
+
+static const uint64_t P9N2_PERV_EP05_CPLT_CONF1_OR = 0x15000019ull;
+
+static const uint64_t P9N2_PERV_EP05_CPLT_CONF1_CLEAR = 0x15000029ull;
+
+static const uint64_t P9N2_PERV_EC00_CPLT_CONF1 = 0x20000009ull;
+
+static const uint64_t P9N2_PERV_EC00_CPLT_CONF1_OR = 0x20000019ull;
+
+static const uint64_t P9N2_PERV_EC00_CPLT_CONF1_CLEAR = 0x20000029ull;
+
+static const uint64_t P9N2_PERV_EC01_CPLT_CONF1 = 0x21000009ull;
+
+static const uint64_t P9N2_PERV_EC01_CPLT_CONF1_OR = 0x21000019ull;
+
+static const uint64_t P9N2_PERV_EC01_CPLT_CONF1_CLEAR = 0x21000029ull;
+
+static const uint64_t P9N2_PERV_EC02_CPLT_CONF1 = 0x22000009ull;
+
+static const uint64_t P9N2_PERV_EC02_CPLT_CONF1_OR = 0x22000019ull;
+
+static const uint64_t P9N2_PERV_EC02_CPLT_CONF1_CLEAR = 0x22000029ull;
+
+static const uint64_t P9N2_PERV_EC03_CPLT_CONF1 = 0x23000009ull;
+
+static const uint64_t P9N2_PERV_EC03_CPLT_CONF1_OR = 0x23000019ull;
+
+static const uint64_t P9N2_PERV_EC03_CPLT_CONF1_CLEAR = 0x23000029ull;
+
+static const uint64_t P9N2_PERV_EC04_CPLT_CONF1 = 0x24000009ull;
+
+static const uint64_t P9N2_PERV_EC04_CPLT_CONF1_OR = 0x24000019ull;
+
+static const uint64_t P9N2_PERV_EC04_CPLT_CONF1_CLEAR = 0x24000029ull;
+
+static const uint64_t P9N2_PERV_EC05_CPLT_CONF1 = 0x25000009ull;
+
+static const uint64_t P9N2_PERV_EC05_CPLT_CONF1_OR = 0x25000019ull;
+
+static const uint64_t P9N2_PERV_EC05_CPLT_CONF1_CLEAR = 0x25000029ull;
+
+static const uint64_t P9N2_PERV_EC06_CPLT_CONF1 = 0x26000009ull;
+
+static const uint64_t P9N2_PERV_EC06_CPLT_CONF1_OR = 0x26000019ull;
+
+static const uint64_t P9N2_PERV_EC06_CPLT_CONF1_CLEAR = 0x26000029ull;
+
+static const uint64_t P9N2_PERV_EC07_CPLT_CONF1 = 0x27000009ull;
+
+static const uint64_t P9N2_PERV_EC07_CPLT_CONF1_OR = 0x27000019ull;
+
+static const uint64_t P9N2_PERV_EC07_CPLT_CONF1_CLEAR = 0x27000029ull;
+
+static const uint64_t P9N2_PERV_EC08_CPLT_CONF1 = 0x28000009ull;
+
+static const uint64_t P9N2_PERV_EC08_CPLT_CONF1_OR = 0x28000019ull;
+
+static const uint64_t P9N2_PERV_EC08_CPLT_CONF1_CLEAR = 0x28000029ull;
+
+static const uint64_t P9N2_PERV_EC09_CPLT_CONF1 = 0x29000009ull;
+
+static const uint64_t P9N2_PERV_EC09_CPLT_CONF1_OR = 0x29000019ull;
+
+static const uint64_t P9N2_PERV_EC09_CPLT_CONF1_CLEAR = 0x29000029ull;
+
+static const uint64_t P9N2_PERV_EC10_CPLT_CONF1 = 0x2A000009ull;
+
+static const uint64_t P9N2_PERV_EC10_CPLT_CONF1_OR = 0x2A000019ull;
+
+static const uint64_t P9N2_PERV_EC10_CPLT_CONF1_CLEAR = 0x2A000029ull;
+
+static const uint64_t P9N2_PERV_EC11_CPLT_CONF1 = 0x2B000009ull;
+
+static const uint64_t P9N2_PERV_EC11_CPLT_CONF1_OR = 0x2B000019ull;
+
+static const uint64_t P9N2_PERV_EC11_CPLT_CONF1_CLEAR = 0x2B000029ull;
+
+static const uint64_t P9N2_PERV_EC12_CPLT_CONF1 = 0x2C000009ull;
+
+static const uint64_t P9N2_PERV_EC12_CPLT_CONF1_OR = 0x2C000019ull;
+
+static const uint64_t P9N2_PERV_EC12_CPLT_CONF1_CLEAR = 0x2C000029ull;
+
+static const uint64_t P9N2_PERV_EC13_CPLT_CONF1 = 0x2D000009ull;
+
+static const uint64_t P9N2_PERV_EC13_CPLT_CONF1_OR = 0x2D000019ull;
+
+static const uint64_t P9N2_PERV_EC13_CPLT_CONF1_CLEAR = 0x2D000029ull;
+
+static const uint64_t P9N2_PERV_EC14_CPLT_CONF1 = 0x2E000009ull;
+
+static const uint64_t P9N2_PERV_EC14_CPLT_CONF1_OR = 0x2E000019ull;
+
+static const uint64_t P9N2_PERV_EC14_CPLT_CONF1_CLEAR = 0x2E000029ull;
+
+static const uint64_t P9N2_PERV_EC15_CPLT_CONF1 = 0x2F000009ull;
+
+static const uint64_t P9N2_PERV_EC15_CPLT_CONF1_OR = 0x2F000019ull;
+
+static const uint64_t P9N2_PERV_EC15_CPLT_CONF1_CLEAR = 0x2F000029ull;
+
+static const uint64_t P9N2_PERV_EC16_CPLT_CONF1 = 0x30000009ull;
+
+static const uint64_t P9N2_PERV_EC16_CPLT_CONF1_OR = 0x30000019ull;
+
+static const uint64_t P9N2_PERV_EC16_CPLT_CONF1_CLEAR = 0x30000029ull;
+
+static const uint64_t P9N2_PERV_EC17_CPLT_CONF1 = 0x31000009ull;
+
+static const uint64_t P9N2_PERV_EC17_CPLT_CONF1_OR = 0x31000019ull;
+
+static const uint64_t P9N2_PERV_EC17_CPLT_CONF1_CLEAR = 0x31000029ull;
+
+static const uint64_t P9N2_PERV_EC18_CPLT_CONF1 = 0x32000009ull;
+
+static const uint64_t P9N2_PERV_EC18_CPLT_CONF1_OR = 0x32000019ull;
+
+static const uint64_t P9N2_PERV_EC18_CPLT_CONF1_CLEAR = 0x32000029ull;
+
+static const uint64_t P9N2_PERV_EC19_CPLT_CONF1 = 0x33000009ull;
+
+static const uint64_t P9N2_PERV_EC19_CPLT_CONF1_OR = 0x33000019ull;
+
+static const uint64_t P9N2_PERV_EC19_CPLT_CONF1_CLEAR = 0x33000029ull;
+
+static const uint64_t P9N2_PERV_EC20_CPLT_CONF1 = 0x34000009ull;
+
+static const uint64_t P9N2_PERV_EC20_CPLT_CONF1_OR = 0x34000019ull;
+
+static const uint64_t P9N2_PERV_EC20_CPLT_CONF1_CLEAR = 0x34000029ull;
+
+static const uint64_t P9N2_PERV_EC21_CPLT_CONF1 = 0x35000009ull;
+
+static const uint64_t P9N2_PERV_EC21_CPLT_CONF1_OR = 0x35000019ull;
+
+static const uint64_t P9N2_PERV_EC21_CPLT_CONF1_CLEAR = 0x35000029ull;
+
+static const uint64_t P9N2_PERV_EC22_CPLT_CONF1 = 0x36000009ull;
+
+static const uint64_t P9N2_PERV_EC22_CPLT_CONF1_OR = 0x36000019ull;
+
+static const uint64_t P9N2_PERV_EC22_CPLT_CONF1_CLEAR = 0x36000029ull;
+
+static const uint64_t P9N2_PERV_EC23_CPLT_CONF1 = 0x37000009ull;
+
+static const uint64_t P9N2_PERV_EC23_CPLT_CONF1_OR = 0x37000019ull;
+
+static const uint64_t P9N2_PERV_EC23_CPLT_CONF1_CLEAR = 0x37000029ull;
+
+
+static const uint64_t P9N2_PERV_CPLT_CTRL0 = 0x00000000ull;
+
+static const uint64_t P9N2_PERV_TP_CPLT_CTRL0 = 0x01000000ull;
+
+static const uint64_t P9N2_PERV_CPLT_CTRL0_OR = 0x00000010ull;
+
+static const uint64_t P9N2_PERV_TP_CPLT_CTRL0_OR = 0x01000010ull;
+
+static const uint64_t P9N2_PERV_CPLT_CTRL0_CLEAR = 0x00000020ull;
+
+static const uint64_t P9N2_PERV_TP_CPLT_CTRL0_CLEAR = 0x01000020ull;
+
+static const uint64_t P9N2_PERV_N0_CPLT_CTRL0 = 0x02000000ull;
+
+static const uint64_t P9N2_PERV_N0_CPLT_CTRL0_OR = 0x02000010ull;
+
+static const uint64_t P9N2_PERV_N0_CPLT_CTRL0_CLEAR = 0x02000020ull;
+
+static const uint64_t P9N2_PERV_N1_CPLT_CTRL0 = 0x03000000ull;
+
+static const uint64_t P9N2_PERV_N1_CPLT_CTRL0_OR = 0x03000010ull;
+
+static const uint64_t P9N2_PERV_N1_CPLT_CTRL0_CLEAR = 0x03000020ull;
+
+static const uint64_t P9N2_PERV_N2_CPLT_CTRL0 = 0x04000000ull;
+
+static const uint64_t P9N2_PERV_N2_CPLT_CTRL0_OR = 0x04000010ull;
+
+static const uint64_t P9N2_PERV_N2_CPLT_CTRL0_CLEAR = 0x04000020ull;
+
+static const uint64_t P9N2_PERV_N3_CPLT_CTRL0 = 0x05000000ull;
+
+static const uint64_t P9N2_PERV_N3_CPLT_CTRL0_OR = 0x05000010ull;
+
+static const uint64_t P9N2_PERV_N3_CPLT_CTRL0_CLEAR = 0x05000020ull;
+
+static const uint64_t P9N2_PERV_XB_CPLT_CTRL0 = 0x06000000ull;
+
+static const uint64_t P9N2_PERV_XB_CPLT_CTRL0_OR = 0x06000010ull;
+
+static const uint64_t P9N2_PERV_XB_CPLT_CTRL0_CLEAR = 0x06000020ull;
+
+static const uint64_t P9N2_PERV_MC01_CPLT_CTRL0 = 0x07000000ull;
+
+static const uint64_t P9N2_PERV_MC01_CPLT_CTRL0_OR = 0x07000010ull;
+
+static const uint64_t P9N2_PERV_MC01_CPLT_CTRL0_CLEAR = 0x07000020ull;
+
+static const uint64_t P9N2_PERV_MC23_CPLT_CTRL0 = 0x08000000ull;
+
+static const uint64_t P9N2_PERV_MC23_CPLT_CTRL0_OR = 0x08000010ull;
+
+static const uint64_t P9N2_PERV_MC23_CPLT_CTRL0_CLEAR = 0x08000020ull;
+
+static const uint64_t P9N2_PERV_OB0_CPLT_CTRL0 = 0x09000000ull;
+
+static const uint64_t P9N2_PERV_OB0_CPLT_CTRL0_OR = 0x09000010ull;
+
+static const uint64_t P9N2_PERV_OB0_CPLT_CTRL0_CLEAR = 0x09000020ull;
+
+static const uint64_t P9N2_PERV_OB3_CPLT_CTRL0 = 0x0C000000ull;
+
+static const uint64_t P9N2_PERV_OB3_CPLT_CTRL0_OR = 0x0C000010ull;
+
+static const uint64_t P9N2_PERV_OB3_CPLT_CTRL0_CLEAR = 0x0C000020ull;
+
+static const uint64_t P9N2_PERV_PCI0_CPLT_CTRL0 = 0x0D000000ull;
+
+static const uint64_t P9N2_PERV_PCI0_CPLT_CTRL0_OR = 0x0D000010ull;
+
+static const uint64_t P9N2_PERV_PCI0_CPLT_CTRL0_CLEAR = 0x0D000020ull;
+
+static const uint64_t P9N2_PERV_PCI1_CPLT_CTRL0 = 0x0E000000ull;
+
+static const uint64_t P9N2_PERV_PCI1_CPLT_CTRL0_OR = 0x0E000010ull;
+
+static const uint64_t P9N2_PERV_PCI1_CPLT_CTRL0_CLEAR = 0x0E000020ull;
+
+static const uint64_t P9N2_PERV_PCI2_CPLT_CTRL0 = 0x0F000000ull;
+
+static const uint64_t P9N2_PERV_PCI2_CPLT_CTRL0_OR = 0x0F000010ull;
+
+static const uint64_t P9N2_PERV_PCI2_CPLT_CTRL0_CLEAR = 0x0F000020ull;
+
+static const uint64_t P9N2_PERV_EP00_CPLT_CTRL0 = 0x10000000ull;
+
+static const uint64_t P9N2_PERV_EP00_CPLT_CTRL0_OR = 0x10000010ull;
+
+static const uint64_t P9N2_PERV_EP00_CPLT_CTRL0_CLEAR = 0x10000020ull;
+
+static const uint64_t P9N2_PERV_EP01_CPLT_CTRL0 = 0x11000000ull;
+
+static const uint64_t P9N2_PERV_EP01_CPLT_CTRL0_OR = 0x11000010ull;
+
+static const uint64_t P9N2_PERV_EP01_CPLT_CTRL0_CLEAR = 0x11000020ull;
+
+static const uint64_t P9N2_PERV_EP02_CPLT_CTRL0 = 0x12000000ull;
+
+static const uint64_t P9N2_PERV_EP02_CPLT_CTRL0_OR = 0x12000010ull;
+
+static const uint64_t P9N2_PERV_EP02_CPLT_CTRL0_CLEAR = 0x12000020ull;
+
+static const uint64_t P9N2_PERV_EP03_CPLT_CTRL0 = 0x13000000ull;
+
+static const uint64_t P9N2_PERV_EP03_CPLT_CTRL0_OR = 0x13000010ull;
+
+static const uint64_t P9N2_PERV_EP03_CPLT_CTRL0_CLEAR = 0x13000020ull;
+
+static const uint64_t P9N2_PERV_EP04_CPLT_CTRL0 = 0x14000000ull;
+
+static const uint64_t P9N2_PERV_EP04_CPLT_CTRL0_OR = 0x14000010ull;
+
+static const uint64_t P9N2_PERV_EP04_CPLT_CTRL0_CLEAR = 0x14000020ull;
+
+static const uint64_t P9N2_PERV_EP05_CPLT_CTRL0 = 0x15000000ull;
+
+static const uint64_t P9N2_PERV_EP05_CPLT_CTRL0_OR = 0x15000010ull;
+
+static const uint64_t P9N2_PERV_EP05_CPLT_CTRL0_CLEAR = 0x15000020ull;
+
+static const uint64_t P9N2_PERV_EC00_CPLT_CTRL0 = 0x20000000ull;
+
+static const uint64_t P9N2_PERV_EC00_CPLT_CTRL0_OR = 0x20000010ull;
+
+static const uint64_t P9N2_PERV_EC00_CPLT_CTRL0_CLEAR = 0x20000020ull;
+
+static const uint64_t P9N2_PERV_EC01_CPLT_CTRL0 = 0x21000000ull;
+
+static const uint64_t P9N2_PERV_EC01_CPLT_CTRL0_OR = 0x21000010ull;
+
+static const uint64_t P9N2_PERV_EC01_CPLT_CTRL0_CLEAR = 0x21000020ull;
+
+static const uint64_t P9N2_PERV_EC02_CPLT_CTRL0 = 0x22000000ull;
+
+static const uint64_t P9N2_PERV_EC02_CPLT_CTRL0_OR = 0x22000010ull;
+
+static const uint64_t P9N2_PERV_EC02_CPLT_CTRL0_CLEAR = 0x22000020ull;
+
+static const uint64_t P9N2_PERV_EC03_CPLT_CTRL0 = 0x23000000ull;
+
+static const uint64_t P9N2_PERV_EC03_CPLT_CTRL0_OR = 0x23000010ull;
+
+static const uint64_t P9N2_PERV_EC03_CPLT_CTRL0_CLEAR = 0x23000020ull;
+
+static const uint64_t P9N2_PERV_EC04_CPLT_CTRL0 = 0x24000000ull;
+
+static const uint64_t P9N2_PERV_EC04_CPLT_CTRL0_OR = 0x24000010ull;
+
+static const uint64_t P9N2_PERV_EC04_CPLT_CTRL0_CLEAR = 0x24000020ull;
+
+static const uint64_t P9N2_PERV_EC05_CPLT_CTRL0 = 0x25000000ull;
+
+static const uint64_t P9N2_PERV_EC05_CPLT_CTRL0_OR = 0x25000010ull;
+
+static const uint64_t P9N2_PERV_EC05_CPLT_CTRL0_CLEAR = 0x25000020ull;
+
+static const uint64_t P9N2_PERV_EC06_CPLT_CTRL0 = 0x26000000ull;
+
+static const uint64_t P9N2_PERV_EC06_CPLT_CTRL0_OR = 0x26000010ull;
+
+static const uint64_t P9N2_PERV_EC06_CPLT_CTRL0_CLEAR = 0x26000020ull;
+
+static const uint64_t P9N2_PERV_EC07_CPLT_CTRL0 = 0x27000000ull;
+
+static const uint64_t P9N2_PERV_EC07_CPLT_CTRL0_OR = 0x27000010ull;
+
+static const uint64_t P9N2_PERV_EC07_CPLT_CTRL0_CLEAR = 0x27000020ull;
+
+static const uint64_t P9N2_PERV_EC08_CPLT_CTRL0 = 0x28000000ull;
+
+static const uint64_t P9N2_PERV_EC08_CPLT_CTRL0_OR = 0x28000010ull;
+
+static const uint64_t P9N2_PERV_EC08_CPLT_CTRL0_CLEAR = 0x28000020ull;
+
+static const uint64_t P9N2_PERV_EC09_CPLT_CTRL0 = 0x29000000ull;
+
+static const uint64_t P9N2_PERV_EC09_CPLT_CTRL0_OR = 0x29000010ull;
+
+static const uint64_t P9N2_PERV_EC09_CPLT_CTRL0_CLEAR = 0x29000020ull;
+
+static const uint64_t P9N2_PERV_EC10_CPLT_CTRL0 = 0x2A000000ull;
+
+static const uint64_t P9N2_PERV_EC10_CPLT_CTRL0_OR = 0x2A000010ull;
+
+static const uint64_t P9N2_PERV_EC10_CPLT_CTRL0_CLEAR = 0x2A000020ull;
+
+static const uint64_t P9N2_PERV_EC11_CPLT_CTRL0 = 0x2B000000ull;
+
+static const uint64_t P9N2_PERV_EC11_CPLT_CTRL0_OR = 0x2B000010ull;
+
+static const uint64_t P9N2_PERV_EC11_CPLT_CTRL0_CLEAR = 0x2B000020ull;
+
+static const uint64_t P9N2_PERV_EC12_CPLT_CTRL0 = 0x2C000000ull;
+
+static const uint64_t P9N2_PERV_EC12_CPLT_CTRL0_OR = 0x2C000010ull;
+
+static const uint64_t P9N2_PERV_EC12_CPLT_CTRL0_CLEAR = 0x2C000020ull;
+
+static const uint64_t P9N2_PERV_EC13_CPLT_CTRL0 = 0x2D000000ull;
+
+static const uint64_t P9N2_PERV_EC13_CPLT_CTRL0_OR = 0x2D000010ull;
+
+static const uint64_t P9N2_PERV_EC13_CPLT_CTRL0_CLEAR = 0x2D000020ull;
+
+static const uint64_t P9N2_PERV_EC14_CPLT_CTRL0 = 0x2E000000ull;
+
+static const uint64_t P9N2_PERV_EC14_CPLT_CTRL0_OR = 0x2E000010ull;
+
+static const uint64_t P9N2_PERV_EC14_CPLT_CTRL0_CLEAR = 0x2E000020ull;
+
+static const uint64_t P9N2_PERV_EC15_CPLT_CTRL0 = 0x2F000000ull;
+
+static const uint64_t P9N2_PERV_EC15_CPLT_CTRL0_OR = 0x2F000010ull;
+
+static const uint64_t P9N2_PERV_EC15_CPLT_CTRL0_CLEAR = 0x2F000020ull;
+
+static const uint64_t P9N2_PERV_EC16_CPLT_CTRL0 = 0x30000000ull;
+
+static const uint64_t P9N2_PERV_EC16_CPLT_CTRL0_OR = 0x30000010ull;
+
+static const uint64_t P9N2_PERV_EC16_CPLT_CTRL0_CLEAR = 0x30000020ull;
+
+static const uint64_t P9N2_PERV_EC17_CPLT_CTRL0 = 0x31000000ull;
+
+static const uint64_t P9N2_PERV_EC17_CPLT_CTRL0_OR = 0x31000010ull;
+
+static const uint64_t P9N2_PERV_EC17_CPLT_CTRL0_CLEAR = 0x31000020ull;
+
+static const uint64_t P9N2_PERV_EC18_CPLT_CTRL0 = 0x32000000ull;
+
+static const uint64_t P9N2_PERV_EC18_CPLT_CTRL0_OR = 0x32000010ull;
+
+static const uint64_t P9N2_PERV_EC18_CPLT_CTRL0_CLEAR = 0x32000020ull;
+
+static const uint64_t P9N2_PERV_EC19_CPLT_CTRL0 = 0x33000000ull;
+
+static const uint64_t P9N2_PERV_EC19_CPLT_CTRL0_OR = 0x33000010ull;
+
+static const uint64_t P9N2_PERV_EC19_CPLT_CTRL0_CLEAR = 0x33000020ull;
+
+static const uint64_t P9N2_PERV_EC20_CPLT_CTRL0 = 0x34000000ull;
+
+static const uint64_t P9N2_PERV_EC20_CPLT_CTRL0_OR = 0x34000010ull;
+
+static const uint64_t P9N2_PERV_EC20_CPLT_CTRL0_CLEAR = 0x34000020ull;
+
+static const uint64_t P9N2_PERV_EC21_CPLT_CTRL0 = 0x35000000ull;
+
+static const uint64_t P9N2_PERV_EC21_CPLT_CTRL0_OR = 0x35000010ull;
+
+static const uint64_t P9N2_PERV_EC21_CPLT_CTRL0_CLEAR = 0x35000020ull;
+
+static const uint64_t P9N2_PERV_EC22_CPLT_CTRL0 = 0x36000000ull;
+
+static const uint64_t P9N2_PERV_EC22_CPLT_CTRL0_OR = 0x36000010ull;
+
+static const uint64_t P9N2_PERV_EC22_CPLT_CTRL0_CLEAR = 0x36000020ull;
+
+static const uint64_t P9N2_PERV_EC23_CPLT_CTRL0 = 0x37000000ull;
+
+static const uint64_t P9N2_PERV_EC23_CPLT_CTRL0_OR = 0x37000010ull;
+
+static const uint64_t P9N2_PERV_EC23_CPLT_CTRL0_CLEAR = 0x37000020ull;
+
+
+static const uint64_t P9N2_PERV_CPLT_CTRL1 = 0x00000001ull;
+
+static const uint64_t P9N2_PERV_TP_CPLT_CTRL1 = 0x01000001ull;
+
+static const uint64_t P9N2_PERV_CPLT_CTRL1_OR = 0x00000011ull;
+
+static const uint64_t P9N2_PERV_TP_CPLT_CTRL1_OR = 0x01000011ull;
+
+static const uint64_t P9N2_PERV_CPLT_CTRL1_CLEAR = 0x00000021ull;
+
+static const uint64_t P9N2_PERV_TP_CPLT_CTRL1_CLEAR = 0x01000021ull;
+
+static const uint64_t P9N2_PERV_N0_CPLT_CTRL1 = 0x02000001ull;
+
+static const uint64_t P9N2_PERV_N0_CPLT_CTRL1_OR = 0x02000011ull;
+
+static const uint64_t P9N2_PERV_N0_CPLT_CTRL1_CLEAR = 0x02000021ull;
+
+static const uint64_t P9N2_PERV_N1_CPLT_CTRL1 = 0x03000001ull;
+
+static const uint64_t P9N2_PERV_N1_CPLT_CTRL1_OR = 0x03000011ull;
+
+static const uint64_t P9N2_PERV_N1_CPLT_CTRL1_CLEAR = 0x03000021ull;
+
+static const uint64_t P9N2_PERV_N2_CPLT_CTRL1 = 0x04000001ull;
+
+static const uint64_t P9N2_PERV_N2_CPLT_CTRL1_OR = 0x04000011ull;
+
+static const uint64_t P9N2_PERV_N2_CPLT_CTRL1_CLEAR = 0x04000021ull;
+
+static const uint64_t P9N2_PERV_N3_CPLT_CTRL1 = 0x05000001ull;
+
+static const uint64_t P9N2_PERV_N3_CPLT_CTRL1_OR = 0x05000011ull;
+
+static const uint64_t P9N2_PERV_N3_CPLT_CTRL1_CLEAR = 0x05000021ull;
+
+static const uint64_t P9N2_PERV_XB_CPLT_CTRL1 = 0x06000001ull;
+
+static const uint64_t P9N2_PERV_XB_CPLT_CTRL1_OR = 0x06000011ull;
+
+static const uint64_t P9N2_PERV_XB_CPLT_CTRL1_CLEAR = 0x06000021ull;
+
+static const uint64_t P9N2_PERV_MC01_CPLT_CTRL1 = 0x07000001ull;
+
+static const uint64_t P9N2_PERV_MC01_CPLT_CTRL1_OR = 0x07000011ull;
+
+static const uint64_t P9N2_PERV_MC01_CPLT_CTRL1_CLEAR = 0x07000021ull;
+
+static const uint64_t P9N2_PERV_MC23_CPLT_CTRL1 = 0x08000001ull;
+
+static const uint64_t P9N2_PERV_MC23_CPLT_CTRL1_OR = 0x08000011ull;
+
+static const uint64_t P9N2_PERV_MC23_CPLT_CTRL1_CLEAR = 0x08000021ull;
+
+static const uint64_t P9N2_PERV_OB0_CPLT_CTRL1 = 0x09000001ull;
+
+static const uint64_t P9N2_PERV_OB0_CPLT_CTRL1_OR = 0x09000011ull;
+
+static const uint64_t P9N2_PERV_OB0_CPLT_CTRL1_CLEAR = 0x09000021ull;
+
+static const uint64_t P9N2_PERV_OB3_CPLT_CTRL1 = 0x0C000001ull;
+
+static const uint64_t P9N2_PERV_OB3_CPLT_CTRL1_OR = 0x0C000011ull;
+
+static const uint64_t P9N2_PERV_OB3_CPLT_CTRL1_CLEAR = 0x0C000021ull;
+
+static const uint64_t P9N2_PERV_PCI0_CPLT_CTRL1 = 0x0D000001ull;
+
+static const uint64_t P9N2_PERV_PCI0_CPLT_CTRL1_OR = 0x0D000011ull;
+
+static const uint64_t P9N2_PERV_PCI0_CPLT_CTRL1_CLEAR = 0x0D000021ull;
+
+static const uint64_t P9N2_PERV_PCI1_CPLT_CTRL1 = 0x0E000001ull;
+
+static const uint64_t P9N2_PERV_PCI1_CPLT_CTRL1_OR = 0x0E000011ull;
+
+static const uint64_t P9N2_PERV_PCI1_CPLT_CTRL1_CLEAR = 0x0E000021ull;
+
+static const uint64_t P9N2_PERV_PCI2_CPLT_CTRL1 = 0x0F000001ull;
+
+static const uint64_t P9N2_PERV_PCI2_CPLT_CTRL1_OR = 0x0F000011ull;
+
+static const uint64_t P9N2_PERV_PCI2_CPLT_CTRL1_CLEAR = 0x0F000021ull;
+
+static const uint64_t P9N2_PERV_EP00_CPLT_CTRL1 = 0x10000001ull;
+
+static const uint64_t P9N2_PERV_EP00_CPLT_CTRL1_OR = 0x10000011ull;
+
+static const uint64_t P9N2_PERV_EP00_CPLT_CTRL1_CLEAR = 0x10000021ull;
+
+static const uint64_t P9N2_PERV_EP01_CPLT_CTRL1 = 0x11000001ull;
+
+static const uint64_t P9N2_PERV_EP01_CPLT_CTRL1_OR = 0x11000011ull;
+
+static const uint64_t P9N2_PERV_EP01_CPLT_CTRL1_CLEAR = 0x11000021ull;
+
+static const uint64_t P9N2_PERV_EP02_CPLT_CTRL1 = 0x12000001ull;
+
+static const uint64_t P9N2_PERV_EP02_CPLT_CTRL1_OR = 0x12000011ull;
+
+static const uint64_t P9N2_PERV_EP02_CPLT_CTRL1_CLEAR = 0x12000021ull;
+
+static const uint64_t P9N2_PERV_EP03_CPLT_CTRL1 = 0x13000001ull;
+
+static const uint64_t P9N2_PERV_EP03_CPLT_CTRL1_OR = 0x13000011ull;
+
+static const uint64_t P9N2_PERV_EP03_CPLT_CTRL1_CLEAR = 0x13000021ull;
+
+static const uint64_t P9N2_PERV_EP04_CPLT_CTRL1 = 0x14000001ull;
+
+static const uint64_t P9N2_PERV_EP04_CPLT_CTRL1_OR = 0x14000011ull;
+
+static const uint64_t P9N2_PERV_EP04_CPLT_CTRL1_CLEAR = 0x14000021ull;
+
+static const uint64_t P9N2_PERV_EP05_CPLT_CTRL1 = 0x15000001ull;
+
+static const uint64_t P9N2_PERV_EP05_CPLT_CTRL1_OR = 0x15000011ull;
+
+static const uint64_t P9N2_PERV_EP05_CPLT_CTRL1_CLEAR = 0x15000021ull;
+
+static const uint64_t P9N2_PERV_EC00_CPLT_CTRL1 = 0x20000001ull;
+
+static const uint64_t P9N2_PERV_EC00_CPLT_CTRL1_OR = 0x20000011ull;
+
+static const uint64_t P9N2_PERV_EC00_CPLT_CTRL1_CLEAR = 0x20000021ull;
+
+static const uint64_t P9N2_PERV_EC01_CPLT_CTRL1 = 0x21000001ull;
+
+static const uint64_t P9N2_PERV_EC01_CPLT_CTRL1_OR = 0x21000011ull;
+
+static const uint64_t P9N2_PERV_EC01_CPLT_CTRL1_CLEAR = 0x21000021ull;
+
+static const uint64_t P9N2_PERV_EC02_CPLT_CTRL1 = 0x22000001ull;
+
+static const uint64_t P9N2_PERV_EC02_CPLT_CTRL1_OR = 0x22000011ull;
+
+static const uint64_t P9N2_PERV_EC02_CPLT_CTRL1_CLEAR = 0x22000021ull;
+
+static const uint64_t P9N2_PERV_EC03_CPLT_CTRL1 = 0x23000001ull;
+
+static const uint64_t P9N2_PERV_EC03_CPLT_CTRL1_OR = 0x23000011ull;
+
+static const uint64_t P9N2_PERV_EC03_CPLT_CTRL1_CLEAR = 0x23000021ull;
+
+static const uint64_t P9N2_PERV_EC04_CPLT_CTRL1 = 0x24000001ull;
+
+static const uint64_t P9N2_PERV_EC04_CPLT_CTRL1_OR = 0x24000011ull;
+
+static const uint64_t P9N2_PERV_EC04_CPLT_CTRL1_CLEAR = 0x24000021ull;
+
+static const uint64_t P9N2_PERV_EC05_CPLT_CTRL1 = 0x25000001ull;
+
+static const uint64_t P9N2_PERV_EC05_CPLT_CTRL1_OR = 0x25000011ull;
+
+static const uint64_t P9N2_PERV_EC05_CPLT_CTRL1_CLEAR = 0x25000021ull;
+
+static const uint64_t P9N2_PERV_EC06_CPLT_CTRL1 = 0x26000001ull;
+
+static const uint64_t P9N2_PERV_EC06_CPLT_CTRL1_OR = 0x26000011ull;
+
+static const uint64_t P9N2_PERV_EC06_CPLT_CTRL1_CLEAR = 0x26000021ull;
+
+static const uint64_t P9N2_PERV_EC07_CPLT_CTRL1 = 0x27000001ull;
+
+static const uint64_t P9N2_PERV_EC07_CPLT_CTRL1_OR = 0x27000011ull;
+
+static const uint64_t P9N2_PERV_EC07_CPLT_CTRL1_CLEAR = 0x27000021ull;
+
+static const uint64_t P9N2_PERV_EC08_CPLT_CTRL1 = 0x28000001ull;
+
+static const uint64_t P9N2_PERV_EC08_CPLT_CTRL1_OR = 0x28000011ull;
+
+static const uint64_t P9N2_PERV_EC08_CPLT_CTRL1_CLEAR = 0x28000021ull;
+
+static const uint64_t P9N2_PERV_EC09_CPLT_CTRL1 = 0x29000001ull;
+
+static const uint64_t P9N2_PERV_EC09_CPLT_CTRL1_OR = 0x29000011ull;
+
+static const uint64_t P9N2_PERV_EC09_CPLT_CTRL1_CLEAR = 0x29000021ull;
+
+static const uint64_t P9N2_PERV_EC10_CPLT_CTRL1 = 0x2A000001ull;
+
+static const uint64_t P9N2_PERV_EC10_CPLT_CTRL1_OR = 0x2A000011ull;
+
+static const uint64_t P9N2_PERV_EC10_CPLT_CTRL1_CLEAR = 0x2A000021ull;
+
+static const uint64_t P9N2_PERV_EC11_CPLT_CTRL1 = 0x2B000001ull;
+
+static const uint64_t P9N2_PERV_EC11_CPLT_CTRL1_OR = 0x2B000011ull;
+
+static const uint64_t P9N2_PERV_EC11_CPLT_CTRL1_CLEAR = 0x2B000021ull;
+
+static const uint64_t P9N2_PERV_EC12_CPLT_CTRL1 = 0x2C000001ull;
+
+static const uint64_t P9N2_PERV_EC12_CPLT_CTRL1_OR = 0x2C000011ull;
+
+static const uint64_t P9N2_PERV_EC12_CPLT_CTRL1_CLEAR = 0x2C000021ull;
+
+static const uint64_t P9N2_PERV_EC13_CPLT_CTRL1 = 0x2D000001ull;
+
+static const uint64_t P9N2_PERV_EC13_CPLT_CTRL1_OR = 0x2D000011ull;
+
+static const uint64_t P9N2_PERV_EC13_CPLT_CTRL1_CLEAR = 0x2D000021ull;
+
+static const uint64_t P9N2_PERV_EC14_CPLT_CTRL1 = 0x2E000001ull;
+
+static const uint64_t P9N2_PERV_EC14_CPLT_CTRL1_OR = 0x2E000011ull;
+
+static const uint64_t P9N2_PERV_EC14_CPLT_CTRL1_CLEAR = 0x2E000021ull;
+
+static const uint64_t P9N2_PERV_EC15_CPLT_CTRL1 = 0x2F000001ull;
+
+static const uint64_t P9N2_PERV_EC15_CPLT_CTRL1_OR = 0x2F000011ull;
+
+static const uint64_t P9N2_PERV_EC15_CPLT_CTRL1_CLEAR = 0x2F000021ull;
+
+static const uint64_t P9N2_PERV_EC16_CPLT_CTRL1 = 0x30000001ull;
+
+static const uint64_t P9N2_PERV_EC16_CPLT_CTRL1_OR = 0x30000011ull;
+
+static const uint64_t P9N2_PERV_EC16_CPLT_CTRL1_CLEAR = 0x30000021ull;
+
+static const uint64_t P9N2_PERV_EC17_CPLT_CTRL1 = 0x31000001ull;
+
+static const uint64_t P9N2_PERV_EC17_CPLT_CTRL1_OR = 0x31000011ull;
+
+static const uint64_t P9N2_PERV_EC17_CPLT_CTRL1_CLEAR = 0x31000021ull;
+
+static const uint64_t P9N2_PERV_EC18_CPLT_CTRL1 = 0x32000001ull;
+
+static const uint64_t P9N2_PERV_EC18_CPLT_CTRL1_OR = 0x32000011ull;
+
+static const uint64_t P9N2_PERV_EC18_CPLT_CTRL1_CLEAR = 0x32000021ull;
+
+static const uint64_t P9N2_PERV_EC19_CPLT_CTRL1 = 0x33000001ull;
+
+static const uint64_t P9N2_PERV_EC19_CPLT_CTRL1_OR = 0x33000011ull;
+
+static const uint64_t P9N2_PERV_EC19_CPLT_CTRL1_CLEAR = 0x33000021ull;
+
+static const uint64_t P9N2_PERV_EC20_CPLT_CTRL1 = 0x34000001ull;
+
+static const uint64_t P9N2_PERV_EC20_CPLT_CTRL1_OR = 0x34000011ull;
+
+static const uint64_t P9N2_PERV_EC20_CPLT_CTRL1_CLEAR = 0x34000021ull;
+
+static const uint64_t P9N2_PERV_EC21_CPLT_CTRL1 = 0x35000001ull;
+
+static const uint64_t P9N2_PERV_EC21_CPLT_CTRL1_OR = 0x35000011ull;
+
+static const uint64_t P9N2_PERV_EC21_CPLT_CTRL1_CLEAR = 0x35000021ull;
+
+static const uint64_t P9N2_PERV_EC22_CPLT_CTRL1 = 0x36000001ull;
+
+static const uint64_t P9N2_PERV_EC22_CPLT_CTRL1_OR = 0x36000011ull;
+
+static const uint64_t P9N2_PERV_EC22_CPLT_CTRL1_CLEAR = 0x36000021ull;
+
+static const uint64_t P9N2_PERV_EC23_CPLT_CTRL1 = 0x37000001ull;
+
+static const uint64_t P9N2_PERV_EC23_CPLT_CTRL1_OR = 0x37000011ull;
+
+static const uint64_t P9N2_PERV_EC23_CPLT_CTRL1_CLEAR = 0x37000021ull;
+
+
+static const uint64_t P9N2_PERV_CPLT_MASK0 = 0x00000101ull;
+
+static const uint64_t P9N2_PERV_TP_CPLT_MASK0 = 0x01000101ull;
+
+static const uint64_t P9N2_PERV_N0_CPLT_MASK0 = 0x02000101ull;
+
+static const uint64_t P9N2_PERV_N1_CPLT_MASK0 = 0x03000101ull;
+
+static const uint64_t P9N2_PERV_N2_CPLT_MASK0 = 0x04000101ull;
+
+static const uint64_t P9N2_PERV_N3_CPLT_MASK0 = 0x05000101ull;
+
+static const uint64_t P9N2_PERV_XB_CPLT_MASK0 = 0x06000101ull;
+
+static const uint64_t P9N2_PERV_MC01_CPLT_MASK0 = 0x07000101ull;
+
+static const uint64_t P9N2_PERV_MC23_CPLT_MASK0 = 0x08000101ull;
+
+static const uint64_t P9N2_PERV_OB0_CPLT_MASK0 = 0x09000101ull;
+
+static const uint64_t P9N2_PERV_OB3_CPLT_MASK0 = 0x0C000101ull;
+
+static const uint64_t P9N2_PERV_PCI0_CPLT_MASK0 = 0x0D000101ull;
+
+static const uint64_t P9N2_PERV_PCI1_CPLT_MASK0 = 0x0E000101ull;
+
+static const uint64_t P9N2_PERV_PCI2_CPLT_MASK0 = 0x0F000101ull;
+
+static const uint64_t P9N2_PERV_EP00_CPLT_MASK0 = 0x10000101ull;
+
+static const uint64_t P9N2_PERV_EP01_CPLT_MASK0 = 0x11000101ull;
+
+static const uint64_t P9N2_PERV_EP02_CPLT_MASK0 = 0x12000101ull;
+
+static const uint64_t P9N2_PERV_EP03_CPLT_MASK0 = 0x13000101ull;
+
+static const uint64_t P9N2_PERV_EP04_CPLT_MASK0 = 0x14000101ull;
+
+static const uint64_t P9N2_PERV_EP05_CPLT_MASK0 = 0x15000101ull;
+
+static const uint64_t P9N2_PERV_EC00_CPLT_MASK0 = 0x20000101ull;
+
+static const uint64_t P9N2_PERV_EC01_CPLT_MASK0 = 0x21000101ull;
+
+static const uint64_t P9N2_PERV_EC02_CPLT_MASK0 = 0x22000101ull;
+
+static const uint64_t P9N2_PERV_EC03_CPLT_MASK0 = 0x23000101ull;
+
+static const uint64_t P9N2_PERV_EC04_CPLT_MASK0 = 0x24000101ull;
+
+static const uint64_t P9N2_PERV_EC05_CPLT_MASK0 = 0x25000101ull;
+
+static const uint64_t P9N2_PERV_EC06_CPLT_MASK0 = 0x26000101ull;
+
+static const uint64_t P9N2_PERV_EC07_CPLT_MASK0 = 0x27000101ull;
+
+static const uint64_t P9N2_PERV_EC08_CPLT_MASK0 = 0x28000101ull;
+
+static const uint64_t P9N2_PERV_EC09_CPLT_MASK0 = 0x29000101ull;
+
+static const uint64_t P9N2_PERV_EC10_CPLT_MASK0 = 0x2A000101ull;
+
+static const uint64_t P9N2_PERV_EC11_CPLT_MASK0 = 0x2B000101ull;
+
+static const uint64_t P9N2_PERV_EC12_CPLT_MASK0 = 0x2C000101ull;
+
+static const uint64_t P9N2_PERV_EC13_CPLT_MASK0 = 0x2D000101ull;
+
+static const uint64_t P9N2_PERV_EC14_CPLT_MASK0 = 0x2E000101ull;
+
+static const uint64_t P9N2_PERV_EC15_CPLT_MASK0 = 0x2F000101ull;
+
+static const uint64_t P9N2_PERV_EC16_CPLT_MASK0 = 0x30000101ull;
+
+static const uint64_t P9N2_PERV_EC17_CPLT_MASK0 = 0x31000101ull;
+
+static const uint64_t P9N2_PERV_EC18_CPLT_MASK0 = 0x32000101ull;
+
+static const uint64_t P9N2_PERV_EC19_CPLT_MASK0 = 0x33000101ull;
+
+static const uint64_t P9N2_PERV_EC20_CPLT_MASK0 = 0x34000101ull;
+
+static const uint64_t P9N2_PERV_EC21_CPLT_MASK0 = 0x35000101ull;
+
+static const uint64_t P9N2_PERV_EC22_CPLT_MASK0 = 0x36000101ull;
+
+static const uint64_t P9N2_PERV_EC23_CPLT_MASK0 = 0x37000101ull;
+
+
+static const uint64_t P9N2_PERV_CPLT_STAT0 = 0x00000100ull;
+
+static const uint64_t P9N2_PERV_TP_CPLT_STAT0 = 0x01000100ull;
+
+static const uint64_t P9N2_PERV_N0_CPLT_STAT0 = 0x02000100ull;
+
+static const uint64_t P9N2_PERV_N1_CPLT_STAT0 = 0x03000100ull;
+
+static const uint64_t P9N2_PERV_N2_CPLT_STAT0 = 0x04000100ull;
+
+static const uint64_t P9N2_PERV_N3_CPLT_STAT0 = 0x05000100ull;
+
+static const uint64_t P9N2_PERV_XB_CPLT_STAT0 = 0x06000100ull;
+
+static const uint64_t P9N2_PERV_MC01_CPLT_STAT0 = 0x07000100ull;
+
+static const uint64_t P9N2_PERV_MC23_CPLT_STAT0 = 0x08000100ull;
+
+static const uint64_t P9N2_PERV_OB0_CPLT_STAT0 = 0x09000100ull;
+
+static const uint64_t P9N2_PERV_OB3_CPLT_STAT0 = 0x0C000100ull;
+
+static const uint64_t P9N2_PERV_PCI0_CPLT_STAT0 = 0x0D000100ull;
+
+static const uint64_t P9N2_PERV_PCI1_CPLT_STAT0 = 0x0E000100ull;
+
+static const uint64_t P9N2_PERV_PCI2_CPLT_STAT0 = 0x0F000100ull;
+
+static const uint64_t P9N2_PERV_EP00_CPLT_STAT0 = 0x10000100ull;
+
+static const uint64_t P9N2_PERV_EP01_CPLT_STAT0 = 0x11000100ull;
+
+static const uint64_t P9N2_PERV_EP02_CPLT_STAT0 = 0x12000100ull;
+
+static const uint64_t P9N2_PERV_EP03_CPLT_STAT0 = 0x13000100ull;
+
+static const uint64_t P9N2_PERV_EP04_CPLT_STAT0 = 0x14000100ull;
+
+static const uint64_t P9N2_PERV_EP05_CPLT_STAT0 = 0x15000100ull;
+
+static const uint64_t P9N2_PERV_EC00_CPLT_STAT0 = 0x20000100ull;
+
+static const uint64_t P9N2_PERV_EC01_CPLT_STAT0 = 0x21000100ull;
+
+static const uint64_t P9N2_PERV_EC02_CPLT_STAT0 = 0x22000100ull;
+
+static const uint64_t P9N2_PERV_EC03_CPLT_STAT0 = 0x23000100ull;
+
+static const uint64_t P9N2_PERV_EC04_CPLT_STAT0 = 0x24000100ull;
+
+static const uint64_t P9N2_PERV_EC05_CPLT_STAT0 = 0x25000100ull;
+
+static const uint64_t P9N2_PERV_EC06_CPLT_STAT0 = 0x26000100ull;
+
+static const uint64_t P9N2_PERV_EC07_CPLT_STAT0 = 0x27000100ull;
+
+static const uint64_t P9N2_PERV_EC08_CPLT_STAT0 = 0x28000100ull;
+
+static const uint64_t P9N2_PERV_EC09_CPLT_STAT0 = 0x29000100ull;
+
+static const uint64_t P9N2_PERV_EC10_CPLT_STAT0 = 0x2A000100ull;
+
+static const uint64_t P9N2_PERV_EC11_CPLT_STAT0 = 0x2B000100ull;
+
+static const uint64_t P9N2_PERV_EC12_CPLT_STAT0 = 0x2C000100ull;
+
+static const uint64_t P9N2_PERV_EC13_CPLT_STAT0 = 0x2D000100ull;
+
+static const uint64_t P9N2_PERV_EC14_CPLT_STAT0 = 0x2E000100ull;
+
+static const uint64_t P9N2_PERV_EC15_CPLT_STAT0 = 0x2F000100ull;
+
+static const uint64_t P9N2_PERV_EC16_CPLT_STAT0 = 0x30000100ull;
+
+static const uint64_t P9N2_PERV_EC17_CPLT_STAT0 = 0x31000100ull;
+
+static const uint64_t P9N2_PERV_EC18_CPLT_STAT0 = 0x32000100ull;
+
+static const uint64_t P9N2_PERV_EC19_CPLT_STAT0 = 0x33000100ull;
+
+static const uint64_t P9N2_PERV_EC20_CPLT_STAT0 = 0x34000100ull;
+
+static const uint64_t P9N2_PERV_EC21_CPLT_STAT0 = 0x35000100ull;
+
+static const uint64_t P9N2_PERV_EC22_CPLT_STAT0 = 0x36000100ull;
+
+static const uint64_t P9N2_PERV_EC23_CPLT_STAT0 = 0x37000100ull;
+
+
+static const uint64_t P9N2_PERV_EC00_CPPM_CACCR = 0x200F0168ull;
+
+static const uint64_t P9N2_PERV_EC00_CPPM_CACCR_CLEAR = 0x200F0169ull;
+
+static const uint64_t P9N2_PERV_EC00_CPPM_CACCR_OR = 0x200F016Aull;
+
+static const uint64_t P9N2_PERV_EC01_CPPM_CACCR = 0x210F0168ull;
+
+static const uint64_t P9N2_PERV_EC01_CPPM_CACCR_CLEAR = 0x210F0169ull;
+
+static const uint64_t P9N2_PERV_EC01_CPPM_CACCR_OR = 0x210F016Aull;
+
+static const uint64_t P9N2_PERV_EC02_CPPM_CACCR = 0x220F0168ull;
+
+static const uint64_t P9N2_PERV_EC02_CPPM_CACCR_CLEAR = 0x220F0169ull;
+
+static const uint64_t P9N2_PERV_EC02_CPPM_CACCR_OR = 0x220F016Aull;
+
+static const uint64_t P9N2_PERV_EC03_CPPM_CACCR = 0x230F0168ull;
+
+static const uint64_t P9N2_PERV_EC03_CPPM_CACCR_CLEAR = 0x230F0169ull;
+
+static const uint64_t P9N2_PERV_EC03_CPPM_CACCR_OR = 0x230F016Aull;
+
+static const uint64_t P9N2_PERV_EC04_CPPM_CACCR = 0x240F0168ull;
+
+static const uint64_t P9N2_PERV_EC04_CPPM_CACCR_CLEAR = 0x240F0169ull;
+
+static const uint64_t P9N2_PERV_EC04_CPPM_CACCR_OR = 0x240F016Aull;
+
+static const uint64_t P9N2_PERV_EC05_CPPM_CACCR = 0x250F0168ull;
+
+static const uint64_t P9N2_PERV_EC05_CPPM_CACCR_CLEAR = 0x250F0169ull;
+
+static const uint64_t P9N2_PERV_EC05_CPPM_CACCR_OR = 0x250F016Aull;
+
+static const uint64_t P9N2_PERV_EC06_CPPM_CACCR = 0x260F0168ull;
+
+static const uint64_t P9N2_PERV_EC06_CPPM_CACCR_CLEAR = 0x260F0169ull;
+
+static const uint64_t P9N2_PERV_EC06_CPPM_CACCR_OR = 0x260F016Aull;
+
+static const uint64_t P9N2_PERV_EC07_CPPM_CACCR = 0x270F0168ull;
+
+static const uint64_t P9N2_PERV_EC07_CPPM_CACCR_CLEAR = 0x270F0169ull;
+
+static const uint64_t P9N2_PERV_EC07_CPPM_CACCR_OR = 0x270F016Aull;
+
+static const uint64_t P9N2_PERV_EC08_CPPM_CACCR = 0x280F0168ull;
+
+static const uint64_t P9N2_PERV_EC08_CPPM_CACCR_CLEAR = 0x280F0169ull;
+
+static const uint64_t P9N2_PERV_EC08_CPPM_CACCR_OR = 0x280F016Aull;
+
+static const uint64_t P9N2_PERV_EC09_CPPM_CACCR = 0x290F0168ull;
+
+static const uint64_t P9N2_PERV_EC09_CPPM_CACCR_CLEAR = 0x290F0169ull;
+
+static const uint64_t P9N2_PERV_EC09_CPPM_CACCR_OR = 0x290F016Aull;
+
+static const uint64_t P9N2_PERV_EC10_CPPM_CACCR = 0x2A0F0168ull;
+
+static const uint64_t P9N2_PERV_EC10_CPPM_CACCR_CLEAR = 0x2A0F0169ull;
+
+static const uint64_t P9N2_PERV_EC10_CPPM_CACCR_OR = 0x2A0F016Aull;
+
+static const uint64_t P9N2_PERV_EC11_CPPM_CACCR = 0x2B0F0168ull;
+
+static const uint64_t P9N2_PERV_EC11_CPPM_CACCR_CLEAR = 0x2B0F0169ull;
+
+static const uint64_t P9N2_PERV_EC11_CPPM_CACCR_OR = 0x2B0F016Aull;
+
+static const uint64_t P9N2_PERV_EC12_CPPM_CACCR = 0x2C0F0168ull;
+
+static const uint64_t P9N2_PERV_EC12_CPPM_CACCR_CLEAR = 0x2C0F0169ull;
+
+static const uint64_t P9N2_PERV_EC12_CPPM_CACCR_OR = 0x2C0F016Aull;
+
+static const uint64_t P9N2_PERV_EC13_CPPM_CACCR = 0x2D0F0168ull;
+
+static const uint64_t P9N2_PERV_EC13_CPPM_CACCR_CLEAR = 0x2D0F0169ull;
+
+static const uint64_t P9N2_PERV_EC13_CPPM_CACCR_OR = 0x2D0F016Aull;
+
+static const uint64_t P9N2_PERV_EC14_CPPM_CACCR = 0x2E0F0168ull;
+
+static const uint64_t P9N2_PERV_EC14_CPPM_CACCR_CLEAR = 0x2E0F0169ull;
+
+static const uint64_t P9N2_PERV_EC14_CPPM_CACCR_OR = 0x2E0F016Aull;
+
+static const uint64_t P9N2_PERV_EC15_CPPM_CACCR = 0x2F0F0168ull;
+
+static const uint64_t P9N2_PERV_EC15_CPPM_CACCR_CLEAR = 0x2F0F0169ull;
+
+static const uint64_t P9N2_PERV_EC15_CPPM_CACCR_OR = 0x2F0F016Aull;
+
+static const uint64_t P9N2_PERV_EC16_CPPM_CACCR = 0x300F0168ull;
+
+static const uint64_t P9N2_PERV_EC16_CPPM_CACCR_CLEAR = 0x300F0169ull;
+
+static const uint64_t P9N2_PERV_EC16_CPPM_CACCR_OR = 0x300F016Aull;
+
+static const uint64_t P9N2_PERV_EC17_CPPM_CACCR = 0x310F0168ull;
+
+static const uint64_t P9N2_PERV_EC17_CPPM_CACCR_CLEAR = 0x310F0169ull;
+
+static const uint64_t P9N2_PERV_EC17_CPPM_CACCR_OR = 0x310F016Aull;
+
+static const uint64_t P9N2_PERV_EC18_CPPM_CACCR = 0x320F0168ull;
+
+static const uint64_t P9N2_PERV_EC18_CPPM_CACCR_CLEAR = 0x320F0169ull;
+
+static const uint64_t P9N2_PERV_EC18_CPPM_CACCR_OR = 0x320F016Aull;
+
+static const uint64_t P9N2_PERV_EC19_CPPM_CACCR = 0x330F0168ull;
+
+static const uint64_t P9N2_PERV_EC19_CPPM_CACCR_CLEAR = 0x330F0169ull;
+
+static const uint64_t P9N2_PERV_EC19_CPPM_CACCR_OR = 0x330F016Aull;
+
+static const uint64_t P9N2_PERV_EC20_CPPM_CACCR = 0x340F0168ull;
+
+static const uint64_t P9N2_PERV_EC20_CPPM_CACCR_CLEAR = 0x340F0169ull;
+
+static const uint64_t P9N2_PERV_EC20_CPPM_CACCR_OR = 0x340F016Aull;
+
+static const uint64_t P9N2_PERV_EC21_CPPM_CACCR = 0x350F0168ull;
+
+static const uint64_t P9N2_PERV_EC21_CPPM_CACCR_CLEAR = 0x350F0169ull;
+
+static const uint64_t P9N2_PERV_EC21_CPPM_CACCR_OR = 0x350F016Aull;
+
+static const uint64_t P9N2_PERV_EC22_CPPM_CACCR = 0x360F0168ull;
+
+static const uint64_t P9N2_PERV_EC22_CPPM_CACCR_CLEAR = 0x360F0169ull;
+
+static const uint64_t P9N2_PERV_EC22_CPPM_CACCR_OR = 0x360F016Aull;
+
+static const uint64_t P9N2_PERV_EC23_CPPM_CACCR = 0x370F0168ull;
+
+static const uint64_t P9N2_PERV_EC23_CPPM_CACCR_CLEAR = 0x370F0169ull;
+
+static const uint64_t P9N2_PERV_EC23_CPPM_CACCR_OR = 0x370F016Aull;
+
+
+static const uint64_t P9N2_PERV_EC00_CPPM_CACSR = 0x200F016Bull;
+
+static const uint64_t P9N2_PERV_EC01_CPPM_CACSR = 0x210F016Bull;
+
+static const uint64_t P9N2_PERV_EC02_CPPM_CACSR = 0x220F016Bull;
+
+static const uint64_t P9N2_PERV_EC03_CPPM_CACSR = 0x230F016Bull;
+
+static const uint64_t P9N2_PERV_EC04_CPPM_CACSR = 0x240F016Bull;
+
+static const uint64_t P9N2_PERV_EC05_CPPM_CACSR = 0x250F016Bull;
+
+static const uint64_t P9N2_PERV_EC06_CPPM_CACSR = 0x260F016Bull;
+
+static const uint64_t P9N2_PERV_EC07_CPPM_CACSR = 0x270F016Bull;
+
+static const uint64_t P9N2_PERV_EC08_CPPM_CACSR = 0x280F016Bull;
+
+static const uint64_t P9N2_PERV_EC09_CPPM_CACSR = 0x290F016Bull;
+
+static const uint64_t P9N2_PERV_EC10_CPPM_CACSR = 0x2A0F016Bull;
+
+static const uint64_t P9N2_PERV_EC11_CPPM_CACSR = 0x2B0F016Bull;
+
+static const uint64_t P9N2_PERV_EC12_CPPM_CACSR = 0x2C0F016Bull;
+
+static const uint64_t P9N2_PERV_EC13_CPPM_CACSR = 0x2D0F016Bull;
+
+static const uint64_t P9N2_PERV_EC14_CPPM_CACSR = 0x2E0F016Bull;
+
+static const uint64_t P9N2_PERV_EC15_CPPM_CACSR = 0x2F0F016Bull;
+
+static const uint64_t P9N2_PERV_EC16_CPPM_CACSR = 0x300F016Bull;
+
+static const uint64_t P9N2_PERV_EC17_CPPM_CACSR = 0x310F016Bull;
+
+static const uint64_t P9N2_PERV_EC18_CPPM_CACSR = 0x320F016Bull;
+
+static const uint64_t P9N2_PERV_EC19_CPPM_CACSR = 0x330F016Bull;
+
+static const uint64_t P9N2_PERV_EC20_CPPM_CACSR = 0x340F016Bull;
+
+static const uint64_t P9N2_PERV_EC21_CPPM_CACSR = 0x350F016Bull;
+
+static const uint64_t P9N2_PERV_EC22_CPPM_CACSR = 0x360F016Bull;
+
+static const uint64_t P9N2_PERV_EC23_CPPM_CACSR = 0x370F016Bull;
+
+
+static const uint64_t P9N2_PERV_EC00_CPPM_CIIR = 0x200F01ADull;
+
+static const uint64_t P9N2_PERV_EC01_CPPM_CIIR = 0x210F01ADull;
+
+static const uint64_t P9N2_PERV_EC02_CPPM_CIIR = 0x220F01ADull;
+
+static const uint64_t P9N2_PERV_EC03_CPPM_CIIR = 0x230F01ADull;
+
+static const uint64_t P9N2_PERV_EC04_CPPM_CIIR = 0x240F01ADull;
+
+static const uint64_t P9N2_PERV_EC05_CPPM_CIIR = 0x250F01ADull;
+
+static const uint64_t P9N2_PERV_EC06_CPPM_CIIR = 0x260F01ADull;
+
+static const uint64_t P9N2_PERV_EC07_CPPM_CIIR = 0x270F01ADull;
+
+static const uint64_t P9N2_PERV_EC08_CPPM_CIIR = 0x280F01ADull;
+
+static const uint64_t P9N2_PERV_EC09_CPPM_CIIR = 0x290F01ADull;
+
+static const uint64_t P9N2_PERV_EC10_CPPM_CIIR = 0x2A0F01ADull;
+
+static const uint64_t P9N2_PERV_EC11_CPPM_CIIR = 0x2B0F01ADull;
+
+static const uint64_t P9N2_PERV_EC12_CPPM_CIIR = 0x2C0F01ADull;
+
+static const uint64_t P9N2_PERV_EC13_CPPM_CIIR = 0x2D0F01ADull;
+
+static const uint64_t P9N2_PERV_EC14_CPPM_CIIR = 0x2E0F01ADull;
+
+static const uint64_t P9N2_PERV_EC15_CPPM_CIIR = 0x2F0F01ADull;
+
+static const uint64_t P9N2_PERV_EC16_CPPM_CIIR = 0x300F01ADull;
+
+static const uint64_t P9N2_PERV_EC17_CPPM_CIIR = 0x310F01ADull;
+
+static const uint64_t P9N2_PERV_EC18_CPPM_CIIR = 0x320F01ADull;
+
+static const uint64_t P9N2_PERV_EC19_CPPM_CIIR = 0x330F01ADull;
+
+static const uint64_t P9N2_PERV_EC20_CPPM_CIIR = 0x340F01ADull;
+
+static const uint64_t P9N2_PERV_EC21_CPPM_CIIR = 0x350F01ADull;
+
+static const uint64_t P9N2_PERV_EC22_CPPM_CIIR = 0x360F01ADull;
+
+static const uint64_t P9N2_PERV_EC23_CPPM_CIIR = 0x370F01ADull;
+
+
+static const uint64_t P9N2_PERV_EC00_CPPM_CISR = 0x200F01AEull;
+
+static const uint64_t P9N2_PERV_EC01_CPPM_CISR = 0x210F01AEull;
+
+static const uint64_t P9N2_PERV_EC02_CPPM_CISR = 0x220F01AEull;
+
+static const uint64_t P9N2_PERV_EC03_CPPM_CISR = 0x230F01AEull;
+
+static const uint64_t P9N2_PERV_EC04_CPPM_CISR = 0x240F01AEull;
+
+static const uint64_t P9N2_PERV_EC05_CPPM_CISR = 0x250F01AEull;
+
+static const uint64_t P9N2_PERV_EC06_CPPM_CISR = 0x260F01AEull;
+
+static const uint64_t P9N2_PERV_EC07_CPPM_CISR = 0x270F01AEull;
+
+static const uint64_t P9N2_PERV_EC08_CPPM_CISR = 0x280F01AEull;
+
+static const uint64_t P9N2_PERV_EC09_CPPM_CISR = 0x290F01AEull;
+
+static const uint64_t P9N2_PERV_EC10_CPPM_CISR = 0x2A0F01AEull;
+
+static const uint64_t P9N2_PERV_EC11_CPPM_CISR = 0x2B0F01AEull;
+
+static const uint64_t P9N2_PERV_EC12_CPPM_CISR = 0x2C0F01AEull;
+
+static const uint64_t P9N2_PERV_EC13_CPPM_CISR = 0x2D0F01AEull;
+
+static const uint64_t P9N2_PERV_EC14_CPPM_CISR = 0x2E0F01AEull;
+
+static const uint64_t P9N2_PERV_EC15_CPPM_CISR = 0x2F0F01AEull;
+
+static const uint64_t P9N2_PERV_EC16_CPPM_CISR = 0x300F01AEull;
+
+static const uint64_t P9N2_PERV_EC17_CPPM_CISR = 0x310F01AEull;
+
+static const uint64_t P9N2_PERV_EC18_CPPM_CISR = 0x320F01AEull;
+
+static const uint64_t P9N2_PERV_EC19_CPPM_CISR = 0x330F01AEull;
+
+static const uint64_t P9N2_PERV_EC20_CPPM_CISR = 0x340F01AEull;
+
+static const uint64_t P9N2_PERV_EC21_CPPM_CISR = 0x350F01AEull;
+
+static const uint64_t P9N2_PERV_EC22_CPPM_CISR = 0x360F01AEull;
+
+static const uint64_t P9N2_PERV_EC23_CPPM_CISR = 0x370F01AEull;
+
+
+static const uint64_t P9N2_PERV_EC00_CPPM_CIVRMLCR = 0x200F01B7ull;
+
+static const uint64_t P9N2_PERV_EC01_CPPM_CIVRMLCR = 0x210F01B7ull;
+
+static const uint64_t P9N2_PERV_EC02_CPPM_CIVRMLCR = 0x220F01B7ull;
+
+static const uint64_t P9N2_PERV_EC03_CPPM_CIVRMLCR = 0x230F01B7ull;
+
+static const uint64_t P9N2_PERV_EC04_CPPM_CIVRMLCR = 0x240F01B7ull;
+
+static const uint64_t P9N2_PERV_EC05_CPPM_CIVRMLCR = 0x250F01B7ull;
+
+static const uint64_t P9N2_PERV_EC06_CPPM_CIVRMLCR = 0x260F01B7ull;
+
+static const uint64_t P9N2_PERV_EC07_CPPM_CIVRMLCR = 0x270F01B7ull;
+
+static const uint64_t P9N2_PERV_EC08_CPPM_CIVRMLCR = 0x280F01B7ull;
+
+static const uint64_t P9N2_PERV_EC09_CPPM_CIVRMLCR = 0x290F01B7ull;
+
+static const uint64_t P9N2_PERV_EC10_CPPM_CIVRMLCR = 0x2A0F01B7ull;
+
+static const uint64_t P9N2_PERV_EC11_CPPM_CIVRMLCR = 0x2B0F01B7ull;
+
+static const uint64_t P9N2_PERV_EC12_CPPM_CIVRMLCR = 0x2C0F01B7ull;
+
+static const uint64_t P9N2_PERV_EC13_CPPM_CIVRMLCR = 0x2D0F01B7ull;
+
+static const uint64_t P9N2_PERV_EC14_CPPM_CIVRMLCR = 0x2E0F01B7ull;
+
+static const uint64_t P9N2_PERV_EC15_CPPM_CIVRMLCR = 0x2F0F01B7ull;
+
+static const uint64_t P9N2_PERV_EC16_CPPM_CIVRMLCR = 0x300F01B7ull;
+
+static const uint64_t P9N2_PERV_EC17_CPPM_CIVRMLCR = 0x310F01B7ull;
+
+static const uint64_t P9N2_PERV_EC18_CPPM_CIVRMLCR = 0x320F01B7ull;
+
+static const uint64_t P9N2_PERV_EC19_CPPM_CIVRMLCR = 0x330F01B7ull;
+
+static const uint64_t P9N2_PERV_EC20_CPPM_CIVRMLCR = 0x340F01B7ull;
+
+static const uint64_t P9N2_PERV_EC21_CPPM_CIVRMLCR = 0x350F01B7ull;
+
+static const uint64_t P9N2_PERV_EC22_CPPM_CIVRMLCR = 0x360F01B7ull;
+
+static const uint64_t P9N2_PERV_EC23_CPPM_CIVRMLCR = 0x370F01B7ull;
+
+
+static const uint64_t P9N2_PERV_EC00_CPPM_CMEDATA = 0x200F01A8ull;
+
+static const uint64_t P9N2_PERV_EC00_CPPM_CMEDATA_CLEAR = 0x200F01A9ull;
+
+static const uint64_t P9N2_PERV_EC00_CPPM_CMEDATA_OR = 0x200F01AAull;
+
+static const uint64_t P9N2_PERV_EC01_CPPM_CMEDATA = 0x210F01A8ull;
+
+static const uint64_t P9N2_PERV_EC01_CPPM_CMEDATA_CLEAR = 0x210F01A9ull;
+
+static const uint64_t P9N2_PERV_EC01_CPPM_CMEDATA_OR = 0x210F01AAull;
+
+static const uint64_t P9N2_PERV_EC02_CPPM_CMEDATA = 0x220F01A8ull;
+
+static const uint64_t P9N2_PERV_EC02_CPPM_CMEDATA_CLEAR = 0x220F01A9ull;
+
+static const uint64_t P9N2_PERV_EC02_CPPM_CMEDATA_OR = 0x220F01AAull;
+
+static const uint64_t P9N2_PERV_EC03_CPPM_CMEDATA = 0x230F01A8ull;
+
+static const uint64_t P9N2_PERV_EC03_CPPM_CMEDATA_CLEAR = 0x230F01A9ull;
+
+static const uint64_t P9N2_PERV_EC03_CPPM_CMEDATA_OR = 0x230F01AAull;
+
+static const uint64_t P9N2_PERV_EC04_CPPM_CMEDATA = 0x240F01A8ull;
+
+static const uint64_t P9N2_PERV_EC04_CPPM_CMEDATA_CLEAR = 0x240F01A9ull;
+
+static const uint64_t P9N2_PERV_EC04_CPPM_CMEDATA_OR = 0x240F01AAull;
+
+static const uint64_t P9N2_PERV_EC05_CPPM_CMEDATA = 0x250F01A8ull;
+
+static const uint64_t P9N2_PERV_EC05_CPPM_CMEDATA_CLEAR = 0x250F01A9ull;
+
+static const uint64_t P9N2_PERV_EC05_CPPM_CMEDATA_OR = 0x250F01AAull;
+
+static const uint64_t P9N2_PERV_EC06_CPPM_CMEDATA = 0x260F01A8ull;
+
+static const uint64_t P9N2_PERV_EC06_CPPM_CMEDATA_CLEAR = 0x260F01A9ull;
+
+static const uint64_t P9N2_PERV_EC06_CPPM_CMEDATA_OR = 0x260F01AAull;
+
+static const uint64_t P9N2_PERV_EC07_CPPM_CMEDATA = 0x270F01A8ull;
+
+static const uint64_t P9N2_PERV_EC07_CPPM_CMEDATA_CLEAR = 0x270F01A9ull;
+
+static const uint64_t P9N2_PERV_EC07_CPPM_CMEDATA_OR = 0x270F01AAull;
+
+static const uint64_t P9N2_PERV_EC08_CPPM_CMEDATA = 0x280F01A8ull;
+
+static const uint64_t P9N2_PERV_EC08_CPPM_CMEDATA_CLEAR = 0x280F01A9ull;
+
+static const uint64_t P9N2_PERV_EC08_CPPM_CMEDATA_OR = 0x280F01AAull;
+
+static const uint64_t P9N2_PERV_EC09_CPPM_CMEDATA = 0x290F01A8ull;
+
+static const uint64_t P9N2_PERV_EC09_CPPM_CMEDATA_CLEAR = 0x290F01A9ull;
+
+static const uint64_t P9N2_PERV_EC09_CPPM_CMEDATA_OR = 0x290F01AAull;
+
+static const uint64_t P9N2_PERV_EC10_CPPM_CMEDATA = 0x2A0F01A8ull;
+
+static const uint64_t P9N2_PERV_EC10_CPPM_CMEDATA_CLEAR = 0x2A0F01A9ull;
+
+static const uint64_t P9N2_PERV_EC10_CPPM_CMEDATA_OR = 0x2A0F01AAull;
+
+static const uint64_t P9N2_PERV_EC11_CPPM_CMEDATA = 0x2B0F01A8ull;
+
+static const uint64_t P9N2_PERV_EC11_CPPM_CMEDATA_CLEAR = 0x2B0F01A9ull;
+
+static const uint64_t P9N2_PERV_EC11_CPPM_CMEDATA_OR = 0x2B0F01AAull;
+
+static const uint64_t P9N2_PERV_EC12_CPPM_CMEDATA = 0x2C0F01A8ull;
+
+static const uint64_t P9N2_PERV_EC12_CPPM_CMEDATA_CLEAR = 0x2C0F01A9ull;
+
+static const uint64_t P9N2_PERV_EC12_CPPM_CMEDATA_OR = 0x2C0F01AAull;
+
+static const uint64_t P9N2_PERV_EC13_CPPM_CMEDATA = 0x2D0F01A8ull;
+
+static const uint64_t P9N2_PERV_EC13_CPPM_CMEDATA_CLEAR = 0x2D0F01A9ull;
+
+static const uint64_t P9N2_PERV_EC13_CPPM_CMEDATA_OR = 0x2D0F01AAull;
+
+static const uint64_t P9N2_PERV_EC14_CPPM_CMEDATA = 0x2E0F01A8ull;
+
+static const uint64_t P9N2_PERV_EC14_CPPM_CMEDATA_CLEAR = 0x2E0F01A9ull;
+
+static const uint64_t P9N2_PERV_EC14_CPPM_CMEDATA_OR = 0x2E0F01AAull;
+
+static const uint64_t P9N2_PERV_EC15_CPPM_CMEDATA = 0x2F0F01A8ull;
+
+static const uint64_t P9N2_PERV_EC15_CPPM_CMEDATA_CLEAR = 0x2F0F01A9ull;
+
+static const uint64_t P9N2_PERV_EC15_CPPM_CMEDATA_OR = 0x2F0F01AAull;
+
+static const uint64_t P9N2_PERV_EC16_CPPM_CMEDATA = 0x300F01A8ull;
+
+static const uint64_t P9N2_PERV_EC16_CPPM_CMEDATA_CLEAR = 0x300F01A9ull;
+
+static const uint64_t P9N2_PERV_EC16_CPPM_CMEDATA_OR = 0x300F01AAull;
+
+static const uint64_t P9N2_PERV_EC17_CPPM_CMEDATA = 0x310F01A8ull;
+
+static const uint64_t P9N2_PERV_EC17_CPPM_CMEDATA_CLEAR = 0x310F01A9ull;
+
+static const uint64_t P9N2_PERV_EC17_CPPM_CMEDATA_OR = 0x310F01AAull;
+
+static const uint64_t P9N2_PERV_EC18_CPPM_CMEDATA = 0x320F01A8ull;
+
+static const uint64_t P9N2_PERV_EC18_CPPM_CMEDATA_CLEAR = 0x320F01A9ull;
+
+static const uint64_t P9N2_PERV_EC18_CPPM_CMEDATA_OR = 0x320F01AAull;
+
+static const uint64_t P9N2_PERV_EC19_CPPM_CMEDATA = 0x330F01A8ull;
+
+static const uint64_t P9N2_PERV_EC19_CPPM_CMEDATA_CLEAR = 0x330F01A9ull;
+
+static const uint64_t P9N2_PERV_EC19_CPPM_CMEDATA_OR = 0x330F01AAull;
+
+static const uint64_t P9N2_PERV_EC20_CPPM_CMEDATA = 0x340F01A8ull;
+
+static const uint64_t P9N2_PERV_EC20_CPPM_CMEDATA_CLEAR = 0x340F01A9ull;
+
+static const uint64_t P9N2_PERV_EC20_CPPM_CMEDATA_OR = 0x340F01AAull;
+
+static const uint64_t P9N2_PERV_EC21_CPPM_CMEDATA = 0x350F01A8ull;
+
+static const uint64_t P9N2_PERV_EC21_CPPM_CMEDATA_CLEAR = 0x350F01A9ull;
+
+static const uint64_t P9N2_PERV_EC21_CPPM_CMEDATA_OR = 0x350F01AAull;
+
+static const uint64_t P9N2_PERV_EC22_CPPM_CMEDATA = 0x360F01A8ull;
+
+static const uint64_t P9N2_PERV_EC22_CPPM_CMEDATA_CLEAR = 0x360F01A9ull;
+
+static const uint64_t P9N2_PERV_EC22_CPPM_CMEDATA_OR = 0x360F01AAull;
+
+static const uint64_t P9N2_PERV_EC23_CPPM_CMEDATA = 0x370F01A8ull;
+
+static const uint64_t P9N2_PERV_EC23_CPPM_CMEDATA_CLEAR = 0x370F01A9ull;
+
+static const uint64_t P9N2_PERV_EC23_CPPM_CMEDATA_OR = 0x370F01AAull;
+
+
+static const uint64_t P9N2_PERV_EC00_CPPM_CMEDB0 = 0x200F0190ull;
+
+static const uint64_t P9N2_PERV_EC00_CPPM_CMEDB0_CLEAR = 0x200F0191ull;
+
+static const uint64_t P9N2_PERV_EC00_CPPM_CMEDB0_OR = 0x200F0192ull;
+
+static const uint64_t P9N2_PERV_EC01_CPPM_CMEDB0 = 0x210F0190ull;
+
+static const uint64_t P9N2_PERV_EC01_CPPM_CMEDB0_CLEAR = 0x210F0191ull;
+
+static const uint64_t P9N2_PERV_EC01_CPPM_CMEDB0_OR = 0x210F0192ull;
+
+static const uint64_t P9N2_PERV_EC02_CPPM_CMEDB0 = 0x220F0190ull;
+
+static const uint64_t P9N2_PERV_EC02_CPPM_CMEDB0_CLEAR = 0x220F0191ull;
+
+static const uint64_t P9N2_PERV_EC02_CPPM_CMEDB0_OR = 0x220F0192ull;
+
+static const uint64_t P9N2_PERV_EC03_CPPM_CMEDB0 = 0x230F0190ull;
+
+static const uint64_t P9N2_PERV_EC03_CPPM_CMEDB0_CLEAR = 0x230F0191ull;
+
+static const uint64_t P9N2_PERV_EC03_CPPM_CMEDB0_OR = 0x230F0192ull;
+
+static const uint64_t P9N2_PERV_EC04_CPPM_CMEDB0 = 0x240F0190ull;
+
+static const uint64_t P9N2_PERV_EC04_CPPM_CMEDB0_CLEAR = 0x240F0191ull;
+
+static const uint64_t P9N2_PERV_EC04_CPPM_CMEDB0_OR = 0x240F0192ull;
+
+static const uint64_t P9N2_PERV_EC05_CPPM_CMEDB0 = 0x250F0190ull;
+
+static const uint64_t P9N2_PERV_EC05_CPPM_CMEDB0_CLEAR = 0x250F0191ull;
+
+static const uint64_t P9N2_PERV_EC05_CPPM_CMEDB0_OR = 0x250F0192ull;
+
+static const uint64_t P9N2_PERV_EC06_CPPM_CMEDB0 = 0x260F0190ull;
+
+static const uint64_t P9N2_PERV_EC06_CPPM_CMEDB0_CLEAR = 0x260F0191ull;
+
+static const uint64_t P9N2_PERV_EC06_CPPM_CMEDB0_OR = 0x260F0192ull;
+
+static const uint64_t P9N2_PERV_EC07_CPPM_CMEDB0 = 0x270F0190ull;
+
+static const uint64_t P9N2_PERV_EC07_CPPM_CMEDB0_CLEAR = 0x270F0191ull;
+
+static const uint64_t P9N2_PERV_EC07_CPPM_CMEDB0_OR = 0x270F0192ull;
+
+static const uint64_t P9N2_PERV_EC08_CPPM_CMEDB0 = 0x280F0190ull;
+
+static const uint64_t P9N2_PERV_EC08_CPPM_CMEDB0_CLEAR = 0x280F0191ull;
+
+static const uint64_t P9N2_PERV_EC08_CPPM_CMEDB0_OR = 0x280F0192ull;
+
+static const uint64_t P9N2_PERV_EC09_CPPM_CMEDB0 = 0x290F0190ull;
+
+static const uint64_t P9N2_PERV_EC09_CPPM_CMEDB0_CLEAR = 0x290F0191ull;
+
+static const uint64_t P9N2_PERV_EC09_CPPM_CMEDB0_OR = 0x290F0192ull;
+
+static const uint64_t P9N2_PERV_EC10_CPPM_CMEDB0 = 0x2A0F0190ull;
+
+static const uint64_t P9N2_PERV_EC10_CPPM_CMEDB0_CLEAR = 0x2A0F0191ull;
+
+static const uint64_t P9N2_PERV_EC10_CPPM_CMEDB0_OR = 0x2A0F0192ull;
+
+static const uint64_t P9N2_PERV_EC11_CPPM_CMEDB0 = 0x2B0F0190ull;
+
+static const uint64_t P9N2_PERV_EC11_CPPM_CMEDB0_CLEAR = 0x2B0F0191ull;
+
+static const uint64_t P9N2_PERV_EC11_CPPM_CMEDB0_OR = 0x2B0F0192ull;
+
+static const uint64_t P9N2_PERV_EC12_CPPM_CMEDB0 = 0x2C0F0190ull;
+
+static const uint64_t P9N2_PERV_EC12_CPPM_CMEDB0_CLEAR = 0x2C0F0191ull;
+
+static const uint64_t P9N2_PERV_EC12_CPPM_CMEDB0_OR = 0x2C0F0192ull;
+
+static const uint64_t P9N2_PERV_EC13_CPPM_CMEDB0 = 0x2D0F0190ull;
+
+static const uint64_t P9N2_PERV_EC13_CPPM_CMEDB0_CLEAR = 0x2D0F0191ull;
+
+static const uint64_t P9N2_PERV_EC13_CPPM_CMEDB0_OR = 0x2D0F0192ull;
+
+static const uint64_t P9N2_PERV_EC14_CPPM_CMEDB0 = 0x2E0F0190ull;
+
+static const uint64_t P9N2_PERV_EC14_CPPM_CMEDB0_CLEAR = 0x2E0F0191ull;
+
+static const uint64_t P9N2_PERV_EC14_CPPM_CMEDB0_OR = 0x2E0F0192ull;
+
+static const uint64_t P9N2_PERV_EC15_CPPM_CMEDB0 = 0x2F0F0190ull;
+
+static const uint64_t P9N2_PERV_EC15_CPPM_CMEDB0_CLEAR = 0x2F0F0191ull;
+
+static const uint64_t P9N2_PERV_EC15_CPPM_CMEDB0_OR = 0x2F0F0192ull;
+
+static const uint64_t P9N2_PERV_EC16_CPPM_CMEDB0 = 0x300F0190ull;
+
+static const uint64_t P9N2_PERV_EC16_CPPM_CMEDB0_CLEAR = 0x300F0191ull;
+
+static const uint64_t P9N2_PERV_EC16_CPPM_CMEDB0_OR = 0x300F0192ull;
+
+static const uint64_t P9N2_PERV_EC17_CPPM_CMEDB0 = 0x310F0190ull;
+
+static const uint64_t P9N2_PERV_EC17_CPPM_CMEDB0_CLEAR = 0x310F0191ull;
+
+static const uint64_t P9N2_PERV_EC17_CPPM_CMEDB0_OR = 0x310F0192ull;
+
+static const uint64_t P9N2_PERV_EC18_CPPM_CMEDB0 = 0x320F0190ull;
+
+static const uint64_t P9N2_PERV_EC18_CPPM_CMEDB0_CLEAR = 0x320F0191ull;
+
+static const uint64_t P9N2_PERV_EC18_CPPM_CMEDB0_OR = 0x320F0192ull;
+
+static const uint64_t P9N2_PERV_EC19_CPPM_CMEDB0 = 0x330F0190ull;
+
+static const uint64_t P9N2_PERV_EC19_CPPM_CMEDB0_CLEAR = 0x330F0191ull;
+
+static const uint64_t P9N2_PERV_EC19_CPPM_CMEDB0_OR = 0x330F0192ull;
+
+static const uint64_t P9N2_PERV_EC20_CPPM_CMEDB0 = 0x340F0190ull;
+
+static const uint64_t P9N2_PERV_EC20_CPPM_CMEDB0_CLEAR = 0x340F0191ull;
+
+static const uint64_t P9N2_PERV_EC20_CPPM_CMEDB0_OR = 0x340F0192ull;
+
+static const uint64_t P9N2_PERV_EC21_CPPM_CMEDB0 = 0x350F0190ull;
+
+static const uint64_t P9N2_PERV_EC21_CPPM_CMEDB0_CLEAR = 0x350F0191ull;
+
+static const uint64_t P9N2_PERV_EC21_CPPM_CMEDB0_OR = 0x350F0192ull;
+
+static const uint64_t P9N2_PERV_EC22_CPPM_CMEDB0 = 0x360F0190ull;
+
+static const uint64_t P9N2_PERV_EC22_CPPM_CMEDB0_CLEAR = 0x360F0191ull;
+
+static const uint64_t P9N2_PERV_EC22_CPPM_CMEDB0_OR = 0x360F0192ull;
+
+static const uint64_t P9N2_PERV_EC23_CPPM_CMEDB0 = 0x370F0190ull;
+
+static const uint64_t P9N2_PERV_EC23_CPPM_CMEDB0_CLEAR = 0x370F0191ull;
+
+static const uint64_t P9N2_PERV_EC23_CPPM_CMEDB0_OR = 0x370F0192ull;
+
+
+static const uint64_t P9N2_PERV_EC00_CPPM_CMEDB1 = 0x200F0194ull;
+
+static const uint64_t P9N2_PERV_EC00_CPPM_CMEDB1_CLEAR = 0x200F0195ull;
+
+static const uint64_t P9N2_PERV_EC00_CPPM_CMEDB1_OR = 0x200F0196ull;
+
+static const uint64_t P9N2_PERV_EC01_CPPM_CMEDB1 = 0x210F0194ull;
+
+static const uint64_t P9N2_PERV_EC01_CPPM_CMEDB1_CLEAR = 0x210F0195ull;
+
+static const uint64_t P9N2_PERV_EC01_CPPM_CMEDB1_OR = 0x210F0196ull;
+
+static const uint64_t P9N2_PERV_EC02_CPPM_CMEDB1 = 0x220F0194ull;
+
+static const uint64_t P9N2_PERV_EC02_CPPM_CMEDB1_CLEAR = 0x220F0195ull;
+
+static const uint64_t P9N2_PERV_EC02_CPPM_CMEDB1_OR = 0x220F0196ull;
+
+static const uint64_t P9N2_PERV_EC03_CPPM_CMEDB1 = 0x230F0194ull;
+
+static const uint64_t P9N2_PERV_EC03_CPPM_CMEDB1_CLEAR = 0x230F0195ull;
+
+static const uint64_t P9N2_PERV_EC03_CPPM_CMEDB1_OR = 0x230F0196ull;
+
+static const uint64_t P9N2_PERV_EC04_CPPM_CMEDB1 = 0x240F0194ull;
+
+static const uint64_t P9N2_PERV_EC04_CPPM_CMEDB1_CLEAR = 0x240F0195ull;
+
+static const uint64_t P9N2_PERV_EC04_CPPM_CMEDB1_OR = 0x240F0196ull;
+
+static const uint64_t P9N2_PERV_EC05_CPPM_CMEDB1 = 0x250F0194ull;
+
+static const uint64_t P9N2_PERV_EC05_CPPM_CMEDB1_CLEAR = 0x250F0195ull;
+
+static const uint64_t P9N2_PERV_EC05_CPPM_CMEDB1_OR = 0x250F0196ull;
+
+static const uint64_t P9N2_PERV_EC06_CPPM_CMEDB1 = 0x260F0194ull;
+
+static const uint64_t P9N2_PERV_EC06_CPPM_CMEDB1_CLEAR = 0x260F0195ull;
+
+static const uint64_t P9N2_PERV_EC06_CPPM_CMEDB1_OR = 0x260F0196ull;
+
+static const uint64_t P9N2_PERV_EC07_CPPM_CMEDB1 = 0x270F0194ull;
+
+static const uint64_t P9N2_PERV_EC07_CPPM_CMEDB1_CLEAR = 0x270F0195ull;
+
+static const uint64_t P9N2_PERV_EC07_CPPM_CMEDB1_OR = 0x270F0196ull;
+
+static const uint64_t P9N2_PERV_EC08_CPPM_CMEDB1 = 0x280F0194ull;
+
+static const uint64_t P9N2_PERV_EC08_CPPM_CMEDB1_CLEAR = 0x280F0195ull;
+
+static const uint64_t P9N2_PERV_EC08_CPPM_CMEDB1_OR = 0x280F0196ull;
+
+static const uint64_t P9N2_PERV_EC09_CPPM_CMEDB1 = 0x290F0194ull;
+
+static const uint64_t P9N2_PERV_EC09_CPPM_CMEDB1_CLEAR = 0x290F0195ull;
+
+static const uint64_t P9N2_PERV_EC09_CPPM_CMEDB1_OR = 0x290F0196ull;
+
+static const uint64_t P9N2_PERV_EC10_CPPM_CMEDB1 = 0x2A0F0194ull;
+
+static const uint64_t P9N2_PERV_EC10_CPPM_CMEDB1_CLEAR = 0x2A0F0195ull;
+
+static const uint64_t P9N2_PERV_EC10_CPPM_CMEDB1_OR = 0x2A0F0196ull;
+
+static const uint64_t P9N2_PERV_EC11_CPPM_CMEDB1 = 0x2B0F0194ull;
+
+static const uint64_t P9N2_PERV_EC11_CPPM_CMEDB1_CLEAR = 0x2B0F0195ull;
+
+static const uint64_t P9N2_PERV_EC11_CPPM_CMEDB1_OR = 0x2B0F0196ull;
+
+static const uint64_t P9N2_PERV_EC12_CPPM_CMEDB1 = 0x2C0F0194ull;
+
+static const uint64_t P9N2_PERV_EC12_CPPM_CMEDB1_CLEAR = 0x2C0F0195ull;
+
+static const uint64_t P9N2_PERV_EC12_CPPM_CMEDB1_OR = 0x2C0F0196ull;
+
+static const uint64_t P9N2_PERV_EC13_CPPM_CMEDB1 = 0x2D0F0194ull;
+
+static const uint64_t P9N2_PERV_EC13_CPPM_CMEDB1_CLEAR = 0x2D0F0195ull;
+
+static const uint64_t P9N2_PERV_EC13_CPPM_CMEDB1_OR = 0x2D0F0196ull;
+
+static const uint64_t P9N2_PERV_EC14_CPPM_CMEDB1 = 0x2E0F0194ull;
+
+static const uint64_t P9N2_PERV_EC14_CPPM_CMEDB1_CLEAR = 0x2E0F0195ull;
+
+static const uint64_t P9N2_PERV_EC14_CPPM_CMEDB1_OR = 0x2E0F0196ull;
+
+static const uint64_t P9N2_PERV_EC15_CPPM_CMEDB1 = 0x2F0F0194ull;
+
+static const uint64_t P9N2_PERV_EC15_CPPM_CMEDB1_CLEAR = 0x2F0F0195ull;
+
+static const uint64_t P9N2_PERV_EC15_CPPM_CMEDB1_OR = 0x2F0F0196ull;
+
+static const uint64_t P9N2_PERV_EC16_CPPM_CMEDB1 = 0x300F0194ull;
+
+static const uint64_t P9N2_PERV_EC16_CPPM_CMEDB1_CLEAR = 0x300F0195ull;
+
+static const uint64_t P9N2_PERV_EC16_CPPM_CMEDB1_OR = 0x300F0196ull;
+
+static const uint64_t P9N2_PERV_EC17_CPPM_CMEDB1 = 0x310F0194ull;
+
+static const uint64_t P9N2_PERV_EC17_CPPM_CMEDB1_CLEAR = 0x310F0195ull;
+
+static const uint64_t P9N2_PERV_EC17_CPPM_CMEDB1_OR = 0x310F0196ull;
+
+static const uint64_t P9N2_PERV_EC18_CPPM_CMEDB1 = 0x320F0194ull;
+
+static const uint64_t P9N2_PERV_EC18_CPPM_CMEDB1_CLEAR = 0x320F0195ull;
+
+static const uint64_t P9N2_PERV_EC18_CPPM_CMEDB1_OR = 0x320F0196ull;
+
+static const uint64_t P9N2_PERV_EC19_CPPM_CMEDB1 = 0x330F0194ull;
+
+static const uint64_t P9N2_PERV_EC19_CPPM_CMEDB1_CLEAR = 0x330F0195ull;
+
+static const uint64_t P9N2_PERV_EC19_CPPM_CMEDB1_OR = 0x330F0196ull;
+
+static const uint64_t P9N2_PERV_EC20_CPPM_CMEDB1 = 0x340F0194ull;
+
+static const uint64_t P9N2_PERV_EC20_CPPM_CMEDB1_CLEAR = 0x340F0195ull;
+
+static const uint64_t P9N2_PERV_EC20_CPPM_CMEDB1_OR = 0x340F0196ull;
+
+static const uint64_t P9N2_PERV_EC21_CPPM_CMEDB1 = 0x350F0194ull;
+
+static const uint64_t P9N2_PERV_EC21_CPPM_CMEDB1_CLEAR = 0x350F0195ull;
+
+static const uint64_t P9N2_PERV_EC21_CPPM_CMEDB1_OR = 0x350F0196ull;
+
+static const uint64_t P9N2_PERV_EC22_CPPM_CMEDB1 = 0x360F0194ull;
+
+static const uint64_t P9N2_PERV_EC22_CPPM_CMEDB1_CLEAR = 0x360F0195ull;
+
+static const uint64_t P9N2_PERV_EC22_CPPM_CMEDB1_OR = 0x360F0196ull;
+
+static const uint64_t P9N2_PERV_EC23_CPPM_CMEDB1 = 0x370F0194ull;
+
+static const uint64_t P9N2_PERV_EC23_CPPM_CMEDB1_CLEAR = 0x370F0195ull;
+
+static const uint64_t P9N2_PERV_EC23_CPPM_CMEDB1_OR = 0x370F0196ull;
+
+
+static const uint64_t P9N2_PERV_EC00_CPPM_CMEDB2 = 0x200F0198ull;
+
+static const uint64_t P9N2_PERV_EC00_CPPM_CMEDB2_CLEAR = 0x200F0199ull;
+
+static const uint64_t P9N2_PERV_EC00_CPPM_CMEDB2_OR = 0x200F019Aull;
+
+static const uint64_t P9N2_PERV_EC01_CPPM_CMEDB2 = 0x210F0198ull;
+
+static const uint64_t P9N2_PERV_EC01_CPPM_CMEDB2_CLEAR = 0x210F0199ull;
+
+static const uint64_t P9N2_PERV_EC01_CPPM_CMEDB2_OR = 0x210F019Aull;
+
+static const uint64_t P9N2_PERV_EC02_CPPM_CMEDB2 = 0x220F0198ull;
+
+static const uint64_t P9N2_PERV_EC02_CPPM_CMEDB2_CLEAR = 0x220F0199ull;
+
+static const uint64_t P9N2_PERV_EC02_CPPM_CMEDB2_OR = 0x220F019Aull;
+
+static const uint64_t P9N2_PERV_EC03_CPPM_CMEDB2 = 0x230F0198ull;
+
+static const uint64_t P9N2_PERV_EC03_CPPM_CMEDB2_CLEAR = 0x230F0199ull;
+
+static const uint64_t P9N2_PERV_EC03_CPPM_CMEDB2_OR = 0x230F019Aull;
+
+static const uint64_t P9N2_PERV_EC04_CPPM_CMEDB2 = 0x240F0198ull;
+
+static const uint64_t P9N2_PERV_EC04_CPPM_CMEDB2_CLEAR = 0x240F0199ull;
+
+static const uint64_t P9N2_PERV_EC04_CPPM_CMEDB2_OR = 0x240F019Aull;
+
+static const uint64_t P9N2_PERV_EC05_CPPM_CMEDB2 = 0x250F0198ull;
+
+static const uint64_t P9N2_PERV_EC05_CPPM_CMEDB2_CLEAR = 0x250F0199ull;
+
+static const uint64_t P9N2_PERV_EC05_CPPM_CMEDB2_OR = 0x250F019Aull;
+
+static const uint64_t P9N2_PERV_EC06_CPPM_CMEDB2 = 0x260F0198ull;
+
+static const uint64_t P9N2_PERV_EC06_CPPM_CMEDB2_CLEAR = 0x260F0199ull;
+
+static const uint64_t P9N2_PERV_EC06_CPPM_CMEDB2_OR = 0x260F019Aull;
+
+static const uint64_t P9N2_PERV_EC07_CPPM_CMEDB2 = 0x270F0198ull;
+
+static const uint64_t P9N2_PERV_EC07_CPPM_CMEDB2_CLEAR = 0x270F0199ull;
+
+static const uint64_t P9N2_PERV_EC07_CPPM_CMEDB2_OR = 0x270F019Aull;
+
+static const uint64_t P9N2_PERV_EC08_CPPM_CMEDB2 = 0x280F0198ull;
+
+static const uint64_t P9N2_PERV_EC08_CPPM_CMEDB2_CLEAR = 0x280F0199ull;
+
+static const uint64_t P9N2_PERV_EC08_CPPM_CMEDB2_OR = 0x280F019Aull;
+
+static const uint64_t P9N2_PERV_EC09_CPPM_CMEDB2 = 0x290F0198ull;
+
+static const uint64_t P9N2_PERV_EC09_CPPM_CMEDB2_CLEAR = 0x290F0199ull;
+
+static const uint64_t P9N2_PERV_EC09_CPPM_CMEDB2_OR = 0x290F019Aull;
+
+static const uint64_t P9N2_PERV_EC10_CPPM_CMEDB2 = 0x2A0F0198ull;
+
+static const uint64_t P9N2_PERV_EC10_CPPM_CMEDB2_CLEAR = 0x2A0F0199ull;
+
+static const uint64_t P9N2_PERV_EC10_CPPM_CMEDB2_OR = 0x2A0F019Aull;
+
+static const uint64_t P9N2_PERV_EC11_CPPM_CMEDB2 = 0x2B0F0198ull;
+
+static const uint64_t P9N2_PERV_EC11_CPPM_CMEDB2_CLEAR = 0x2B0F0199ull;
+
+static const uint64_t P9N2_PERV_EC11_CPPM_CMEDB2_OR = 0x2B0F019Aull;
+
+static const uint64_t P9N2_PERV_EC12_CPPM_CMEDB2 = 0x2C0F0198ull;
+
+static const uint64_t P9N2_PERV_EC12_CPPM_CMEDB2_CLEAR = 0x2C0F0199ull;
+
+static const uint64_t P9N2_PERV_EC12_CPPM_CMEDB2_OR = 0x2C0F019Aull;
+
+static const uint64_t P9N2_PERV_EC13_CPPM_CMEDB2 = 0x2D0F0198ull;
+
+static const uint64_t P9N2_PERV_EC13_CPPM_CMEDB2_CLEAR = 0x2D0F0199ull;
+
+static const uint64_t P9N2_PERV_EC13_CPPM_CMEDB2_OR = 0x2D0F019Aull;
+
+static const uint64_t P9N2_PERV_EC14_CPPM_CMEDB2 = 0x2E0F0198ull;
+
+static const uint64_t P9N2_PERV_EC14_CPPM_CMEDB2_CLEAR = 0x2E0F0199ull;
+
+static const uint64_t P9N2_PERV_EC14_CPPM_CMEDB2_OR = 0x2E0F019Aull;
+
+static const uint64_t P9N2_PERV_EC15_CPPM_CMEDB2 = 0x2F0F0198ull;
+
+static const uint64_t P9N2_PERV_EC15_CPPM_CMEDB2_CLEAR = 0x2F0F0199ull;
+
+static const uint64_t P9N2_PERV_EC15_CPPM_CMEDB2_OR = 0x2F0F019Aull;
+
+static const uint64_t P9N2_PERV_EC16_CPPM_CMEDB2 = 0x300F0198ull;
+
+static const uint64_t P9N2_PERV_EC16_CPPM_CMEDB2_CLEAR = 0x300F0199ull;
+
+static const uint64_t P9N2_PERV_EC16_CPPM_CMEDB2_OR = 0x300F019Aull;
+
+static const uint64_t P9N2_PERV_EC17_CPPM_CMEDB2 = 0x310F0198ull;
+
+static const uint64_t P9N2_PERV_EC17_CPPM_CMEDB2_CLEAR = 0x310F0199ull;
+
+static const uint64_t P9N2_PERV_EC17_CPPM_CMEDB2_OR = 0x310F019Aull;
+
+static const uint64_t P9N2_PERV_EC18_CPPM_CMEDB2 = 0x320F0198ull;
+
+static const uint64_t P9N2_PERV_EC18_CPPM_CMEDB2_CLEAR = 0x320F0199ull;
+
+static const uint64_t P9N2_PERV_EC18_CPPM_CMEDB2_OR = 0x320F019Aull;
+
+static const uint64_t P9N2_PERV_EC19_CPPM_CMEDB2 = 0x330F0198ull;
+
+static const uint64_t P9N2_PERV_EC19_CPPM_CMEDB2_CLEAR = 0x330F0199ull;
+
+static const uint64_t P9N2_PERV_EC19_CPPM_CMEDB2_OR = 0x330F019Aull;
+
+static const uint64_t P9N2_PERV_EC20_CPPM_CMEDB2 = 0x340F0198ull;
+
+static const uint64_t P9N2_PERV_EC20_CPPM_CMEDB2_CLEAR = 0x340F0199ull;
+
+static const uint64_t P9N2_PERV_EC20_CPPM_CMEDB2_OR = 0x340F019Aull;
+
+static const uint64_t P9N2_PERV_EC21_CPPM_CMEDB2 = 0x350F0198ull;
+
+static const uint64_t P9N2_PERV_EC21_CPPM_CMEDB2_CLEAR = 0x350F0199ull;
+
+static const uint64_t P9N2_PERV_EC21_CPPM_CMEDB2_OR = 0x350F019Aull;
+
+static const uint64_t P9N2_PERV_EC22_CPPM_CMEDB2 = 0x360F0198ull;
+
+static const uint64_t P9N2_PERV_EC22_CPPM_CMEDB2_CLEAR = 0x360F0199ull;
+
+static const uint64_t P9N2_PERV_EC22_CPPM_CMEDB2_OR = 0x360F019Aull;
+
+static const uint64_t P9N2_PERV_EC23_CPPM_CMEDB2 = 0x370F0198ull;
+
+static const uint64_t P9N2_PERV_EC23_CPPM_CMEDB2_CLEAR = 0x370F0199ull;
+
+static const uint64_t P9N2_PERV_EC23_CPPM_CMEDB2_OR = 0x370F019Aull;
+
+
+static const uint64_t P9N2_PERV_EC00_CPPM_CMEDB3 = 0x200F019Cull;
+
+static const uint64_t P9N2_PERV_EC00_CPPM_CMEDB3_CLEAR = 0x200F019Dull;
+
+static const uint64_t P9N2_PERV_EC00_CPPM_CMEDB3_OR = 0x200F019Eull;
+
+static const uint64_t P9N2_PERV_EC01_CPPM_CMEDB3 = 0x210F019Cull;
+
+static const uint64_t P9N2_PERV_EC01_CPPM_CMEDB3_CLEAR = 0x210F019Dull;
+
+static const uint64_t P9N2_PERV_EC01_CPPM_CMEDB3_OR = 0x210F019Eull;
+
+static const uint64_t P9N2_PERV_EC02_CPPM_CMEDB3 = 0x220F019Cull;
+
+static const uint64_t P9N2_PERV_EC02_CPPM_CMEDB3_CLEAR = 0x220F019Dull;
+
+static const uint64_t P9N2_PERV_EC02_CPPM_CMEDB3_OR = 0x220F019Eull;
+
+static const uint64_t P9N2_PERV_EC03_CPPM_CMEDB3 = 0x230F019Cull;
+
+static const uint64_t P9N2_PERV_EC03_CPPM_CMEDB3_CLEAR = 0x230F019Dull;
+
+static const uint64_t P9N2_PERV_EC03_CPPM_CMEDB3_OR = 0x230F019Eull;
+
+static const uint64_t P9N2_PERV_EC04_CPPM_CMEDB3 = 0x240F019Cull;
+
+static const uint64_t P9N2_PERV_EC04_CPPM_CMEDB3_CLEAR = 0x240F019Dull;
+
+static const uint64_t P9N2_PERV_EC04_CPPM_CMEDB3_OR = 0x240F019Eull;
+
+static const uint64_t P9N2_PERV_EC05_CPPM_CMEDB3 = 0x250F019Cull;
+
+static const uint64_t P9N2_PERV_EC05_CPPM_CMEDB3_CLEAR = 0x250F019Dull;
+
+static const uint64_t P9N2_PERV_EC05_CPPM_CMEDB3_OR = 0x250F019Eull;
+
+static const uint64_t P9N2_PERV_EC06_CPPM_CMEDB3 = 0x260F019Cull;
+
+static const uint64_t P9N2_PERV_EC06_CPPM_CMEDB3_CLEAR = 0x260F019Dull;
+
+static const uint64_t P9N2_PERV_EC06_CPPM_CMEDB3_OR = 0x260F019Eull;
+
+static const uint64_t P9N2_PERV_EC07_CPPM_CMEDB3 = 0x270F019Cull;
+
+static const uint64_t P9N2_PERV_EC07_CPPM_CMEDB3_CLEAR = 0x270F019Dull;
+
+static const uint64_t P9N2_PERV_EC07_CPPM_CMEDB3_OR = 0x270F019Eull;
+
+static const uint64_t P9N2_PERV_EC08_CPPM_CMEDB3 = 0x280F019Cull;
+
+static const uint64_t P9N2_PERV_EC08_CPPM_CMEDB3_CLEAR = 0x280F019Dull;
+
+static const uint64_t P9N2_PERV_EC08_CPPM_CMEDB3_OR = 0x280F019Eull;
+
+static const uint64_t P9N2_PERV_EC09_CPPM_CMEDB3 = 0x290F019Cull;
+
+static const uint64_t P9N2_PERV_EC09_CPPM_CMEDB3_CLEAR = 0x290F019Dull;
+
+static const uint64_t P9N2_PERV_EC09_CPPM_CMEDB3_OR = 0x290F019Eull;
+
+static const uint64_t P9N2_PERV_EC10_CPPM_CMEDB3 = 0x2A0F019Cull;
+
+static const uint64_t P9N2_PERV_EC10_CPPM_CMEDB3_CLEAR = 0x2A0F019Dull;
+
+static const uint64_t P9N2_PERV_EC10_CPPM_CMEDB3_OR = 0x2A0F019Eull;
+
+static const uint64_t P9N2_PERV_EC11_CPPM_CMEDB3 = 0x2B0F019Cull;
+
+static const uint64_t P9N2_PERV_EC11_CPPM_CMEDB3_CLEAR = 0x2B0F019Dull;
+
+static const uint64_t P9N2_PERV_EC11_CPPM_CMEDB3_OR = 0x2B0F019Eull;
+
+static const uint64_t P9N2_PERV_EC12_CPPM_CMEDB3 = 0x2C0F019Cull;
+
+static const uint64_t P9N2_PERV_EC12_CPPM_CMEDB3_CLEAR = 0x2C0F019Dull;
+
+static const uint64_t P9N2_PERV_EC12_CPPM_CMEDB3_OR = 0x2C0F019Eull;
+
+static const uint64_t P9N2_PERV_EC13_CPPM_CMEDB3 = 0x2D0F019Cull;
+
+static const uint64_t P9N2_PERV_EC13_CPPM_CMEDB3_CLEAR = 0x2D0F019Dull;
+
+static const uint64_t P9N2_PERV_EC13_CPPM_CMEDB3_OR = 0x2D0F019Eull;
+
+static const uint64_t P9N2_PERV_EC14_CPPM_CMEDB3 = 0x2E0F019Cull;
+
+static const uint64_t P9N2_PERV_EC14_CPPM_CMEDB3_CLEAR = 0x2E0F019Dull;
+
+static const uint64_t P9N2_PERV_EC14_CPPM_CMEDB3_OR = 0x2E0F019Eull;
+
+static const uint64_t P9N2_PERV_EC15_CPPM_CMEDB3 = 0x2F0F019Cull;
+
+static const uint64_t P9N2_PERV_EC15_CPPM_CMEDB3_CLEAR = 0x2F0F019Dull;
+
+static const uint64_t P9N2_PERV_EC15_CPPM_CMEDB3_OR = 0x2F0F019Eull;
+
+static const uint64_t P9N2_PERV_EC16_CPPM_CMEDB3 = 0x300F019Cull;
+
+static const uint64_t P9N2_PERV_EC16_CPPM_CMEDB3_CLEAR = 0x300F019Dull;
+
+static const uint64_t P9N2_PERV_EC16_CPPM_CMEDB3_OR = 0x300F019Eull;
+
+static const uint64_t P9N2_PERV_EC17_CPPM_CMEDB3 = 0x310F019Cull;
+
+static const uint64_t P9N2_PERV_EC17_CPPM_CMEDB3_CLEAR = 0x310F019Dull;
+
+static const uint64_t P9N2_PERV_EC17_CPPM_CMEDB3_OR = 0x310F019Eull;
+
+static const uint64_t P9N2_PERV_EC18_CPPM_CMEDB3 = 0x320F019Cull;
+
+static const uint64_t P9N2_PERV_EC18_CPPM_CMEDB3_CLEAR = 0x320F019Dull;
+
+static const uint64_t P9N2_PERV_EC18_CPPM_CMEDB3_OR = 0x320F019Eull;
+
+static const uint64_t P9N2_PERV_EC19_CPPM_CMEDB3 = 0x330F019Cull;
+
+static const uint64_t P9N2_PERV_EC19_CPPM_CMEDB3_CLEAR = 0x330F019Dull;
+
+static const uint64_t P9N2_PERV_EC19_CPPM_CMEDB3_OR = 0x330F019Eull;
+
+static const uint64_t P9N2_PERV_EC20_CPPM_CMEDB3 = 0x340F019Cull;
+
+static const uint64_t P9N2_PERV_EC20_CPPM_CMEDB3_CLEAR = 0x340F019Dull;
+
+static const uint64_t P9N2_PERV_EC20_CPPM_CMEDB3_OR = 0x340F019Eull;
+
+static const uint64_t P9N2_PERV_EC21_CPPM_CMEDB3 = 0x350F019Cull;
+
+static const uint64_t P9N2_PERV_EC21_CPPM_CMEDB3_CLEAR = 0x350F019Dull;
+
+static const uint64_t P9N2_PERV_EC21_CPPM_CMEDB3_OR = 0x350F019Eull;
+
+static const uint64_t P9N2_PERV_EC22_CPPM_CMEDB3 = 0x360F019Cull;
+
+static const uint64_t P9N2_PERV_EC22_CPPM_CMEDB3_CLEAR = 0x360F019Dull;
+
+static const uint64_t P9N2_PERV_EC22_CPPM_CMEDB3_OR = 0x360F019Eull;
+
+static const uint64_t P9N2_PERV_EC23_CPPM_CMEDB3 = 0x370F019Cull;
+
+static const uint64_t P9N2_PERV_EC23_CPPM_CMEDB3_CLEAR = 0x370F019Dull;
+
+static const uint64_t P9N2_PERV_EC23_CPPM_CMEDB3_OR = 0x370F019Eull;
+
+
+static const uint64_t P9N2_PERV_EC00_CPPM_CMEMSG = 0x200F01ABull;
+
+static const uint64_t P9N2_PERV_EC01_CPPM_CMEMSG = 0x210F01ABull;
+
+static const uint64_t P9N2_PERV_EC02_CPPM_CMEMSG = 0x220F01ABull;
+
+static const uint64_t P9N2_PERV_EC03_CPPM_CMEMSG = 0x230F01ABull;
+
+static const uint64_t P9N2_PERV_EC04_CPPM_CMEMSG = 0x240F01ABull;
+
+static const uint64_t P9N2_PERV_EC05_CPPM_CMEMSG = 0x250F01ABull;
+
+static const uint64_t P9N2_PERV_EC06_CPPM_CMEMSG = 0x260F01ABull;
+
+static const uint64_t P9N2_PERV_EC07_CPPM_CMEMSG = 0x270F01ABull;
+
+static const uint64_t P9N2_PERV_EC08_CPPM_CMEMSG = 0x280F01ABull;
+
+static const uint64_t P9N2_PERV_EC09_CPPM_CMEMSG = 0x290F01ABull;
+
+static const uint64_t P9N2_PERV_EC10_CPPM_CMEMSG = 0x2A0F01ABull;
+
+static const uint64_t P9N2_PERV_EC11_CPPM_CMEMSG = 0x2B0F01ABull;
+
+static const uint64_t P9N2_PERV_EC12_CPPM_CMEMSG = 0x2C0F01ABull;
+
+static const uint64_t P9N2_PERV_EC13_CPPM_CMEMSG = 0x2D0F01ABull;
+
+static const uint64_t P9N2_PERV_EC14_CPPM_CMEMSG = 0x2E0F01ABull;
+
+static const uint64_t P9N2_PERV_EC15_CPPM_CMEMSG = 0x2F0F01ABull;
+
+static const uint64_t P9N2_PERV_EC16_CPPM_CMEMSG = 0x300F01ABull;
+
+static const uint64_t P9N2_PERV_EC17_CPPM_CMEMSG = 0x310F01ABull;
+
+static const uint64_t P9N2_PERV_EC18_CPPM_CMEMSG = 0x320F01ABull;
+
+static const uint64_t P9N2_PERV_EC19_CPPM_CMEMSG = 0x330F01ABull;
+
+static const uint64_t P9N2_PERV_EC20_CPPM_CMEMSG = 0x340F01ABull;
+
+static const uint64_t P9N2_PERV_EC21_CPPM_CMEMSG = 0x350F01ABull;
+
+static const uint64_t P9N2_PERV_EC22_CPPM_CMEMSG = 0x360F01ABull;
+
+static const uint64_t P9N2_PERV_EC23_CPPM_CMEMSG = 0x370F01ABull;
+
+
+static const uint64_t P9N2_PERV_EC00_CPPM_CPMMR_SCOM = 0x200F0106ull;
+
+static const uint64_t P9N2_PERV_EC00_CPPM_CPMMR_SCOM1 = 0x200F0107ull;
+
+static const uint64_t P9N2_PERV_EC00_CPPM_CPMMR_SCOM2 = 0x200F0108ull;
+
+static const uint64_t P9N2_PERV_EC01_CPPM_CPMMR_SCOM = 0x210F0106ull;
+
+static const uint64_t P9N2_PERV_EC01_CPPM_CPMMR_SCOM1 = 0x210F0107ull;
+
+static const uint64_t P9N2_PERV_EC01_CPPM_CPMMR_SCOM2 = 0x210F0108ull;
+
+static const uint64_t P9N2_PERV_EC02_CPPM_CPMMR_SCOM = 0x220F0106ull;
+
+static const uint64_t P9N2_PERV_EC02_CPPM_CPMMR_SCOM1 = 0x220F0107ull;
+
+static const uint64_t P9N2_PERV_EC02_CPPM_CPMMR_SCOM2 = 0x220F0108ull;
+
+static const uint64_t P9N2_PERV_EC03_CPPM_CPMMR_SCOM = 0x230F0106ull;
+
+static const uint64_t P9N2_PERV_EC03_CPPM_CPMMR_SCOM1 = 0x230F0107ull;
+
+static const uint64_t P9N2_PERV_EC03_CPPM_CPMMR_SCOM2 = 0x230F0108ull;
+
+static const uint64_t P9N2_PERV_EC04_CPPM_CPMMR_SCOM = 0x240F0106ull;
+
+static const uint64_t P9N2_PERV_EC04_CPPM_CPMMR_SCOM1 = 0x240F0107ull;
+
+static const uint64_t P9N2_PERV_EC04_CPPM_CPMMR_SCOM2 = 0x240F0108ull;
+
+static const uint64_t P9N2_PERV_EC05_CPPM_CPMMR_SCOM = 0x250F0106ull;
+
+static const uint64_t P9N2_PERV_EC05_CPPM_CPMMR_SCOM1 = 0x250F0107ull;
+
+static const uint64_t P9N2_PERV_EC05_CPPM_CPMMR_SCOM2 = 0x250F0108ull;
+
+static const uint64_t P9N2_PERV_EC06_CPPM_CPMMR_SCOM = 0x260F0106ull;
+
+static const uint64_t P9N2_PERV_EC06_CPPM_CPMMR_SCOM1 = 0x260F0107ull;
+
+static const uint64_t P9N2_PERV_EC06_CPPM_CPMMR_SCOM2 = 0x260F0108ull;
+
+static const uint64_t P9N2_PERV_EC07_CPPM_CPMMR_SCOM = 0x270F0106ull;
+
+static const uint64_t P9N2_PERV_EC07_CPPM_CPMMR_SCOM1 = 0x270F0107ull;
+
+static const uint64_t P9N2_PERV_EC07_CPPM_CPMMR_SCOM2 = 0x270F0108ull;
+
+static const uint64_t P9N2_PERV_EC08_CPPM_CPMMR_SCOM = 0x280F0106ull;
+
+static const uint64_t P9N2_PERV_EC08_CPPM_CPMMR_SCOM1 = 0x280F0107ull;
+
+static const uint64_t P9N2_PERV_EC08_CPPM_CPMMR_SCOM2 = 0x280F0108ull;
+
+static const uint64_t P9N2_PERV_EC09_CPPM_CPMMR_SCOM = 0x290F0106ull;
+
+static const uint64_t P9N2_PERV_EC09_CPPM_CPMMR_SCOM1 = 0x290F0107ull;
+
+static const uint64_t P9N2_PERV_EC09_CPPM_CPMMR_SCOM2 = 0x290F0108ull;
+
+static const uint64_t P9N2_PERV_EC10_CPPM_CPMMR_SCOM = 0x2A0F0106ull;
+
+static const uint64_t P9N2_PERV_EC10_CPPM_CPMMR_SCOM1 = 0x2A0F0107ull;
+
+static const uint64_t P9N2_PERV_EC10_CPPM_CPMMR_SCOM2 = 0x2A0F0108ull;
+
+static const uint64_t P9N2_PERV_EC11_CPPM_CPMMR_SCOM = 0x2B0F0106ull;
+
+static const uint64_t P9N2_PERV_EC11_CPPM_CPMMR_SCOM1 = 0x2B0F0107ull;
+
+static const uint64_t P9N2_PERV_EC11_CPPM_CPMMR_SCOM2 = 0x2B0F0108ull;
+
+static const uint64_t P9N2_PERV_EC12_CPPM_CPMMR_SCOM = 0x2C0F0106ull;
+
+static const uint64_t P9N2_PERV_EC12_CPPM_CPMMR_SCOM1 = 0x2C0F0107ull;
+
+static const uint64_t P9N2_PERV_EC12_CPPM_CPMMR_SCOM2 = 0x2C0F0108ull;
+
+static const uint64_t P9N2_PERV_EC13_CPPM_CPMMR_SCOM = 0x2D0F0106ull;
+
+static const uint64_t P9N2_PERV_EC13_CPPM_CPMMR_SCOM1 = 0x2D0F0107ull;
+
+static const uint64_t P9N2_PERV_EC13_CPPM_CPMMR_SCOM2 = 0x2D0F0108ull;
+
+static const uint64_t P9N2_PERV_EC14_CPPM_CPMMR_SCOM = 0x2E0F0106ull;
+
+static const uint64_t P9N2_PERV_EC14_CPPM_CPMMR_SCOM1 = 0x2E0F0107ull;
+
+static const uint64_t P9N2_PERV_EC14_CPPM_CPMMR_SCOM2 = 0x2E0F0108ull;
+
+static const uint64_t P9N2_PERV_EC15_CPPM_CPMMR_SCOM = 0x2F0F0106ull;
+
+static const uint64_t P9N2_PERV_EC15_CPPM_CPMMR_SCOM1 = 0x2F0F0107ull;
+
+static const uint64_t P9N2_PERV_EC15_CPPM_CPMMR_SCOM2 = 0x2F0F0108ull;
+
+static const uint64_t P9N2_PERV_EC16_CPPM_CPMMR_SCOM = 0x300F0106ull;
+
+static const uint64_t P9N2_PERV_EC16_CPPM_CPMMR_SCOM1 = 0x300F0107ull;
+
+static const uint64_t P9N2_PERV_EC16_CPPM_CPMMR_SCOM2 = 0x300F0108ull;
+
+static const uint64_t P9N2_PERV_EC17_CPPM_CPMMR_SCOM = 0x310F0106ull;
+
+static const uint64_t P9N2_PERV_EC17_CPPM_CPMMR_SCOM1 = 0x310F0107ull;
+
+static const uint64_t P9N2_PERV_EC17_CPPM_CPMMR_SCOM2 = 0x310F0108ull;
+
+static const uint64_t P9N2_PERV_EC18_CPPM_CPMMR_SCOM = 0x320F0106ull;
+
+static const uint64_t P9N2_PERV_EC18_CPPM_CPMMR_SCOM1 = 0x320F0107ull;
+
+static const uint64_t P9N2_PERV_EC18_CPPM_CPMMR_SCOM2 = 0x320F0108ull;
+
+static const uint64_t P9N2_PERV_EC19_CPPM_CPMMR_SCOM = 0x330F0106ull;
+
+static const uint64_t P9N2_PERV_EC19_CPPM_CPMMR_SCOM1 = 0x330F0107ull;
+
+static const uint64_t P9N2_PERV_EC19_CPPM_CPMMR_SCOM2 = 0x330F0108ull;
+
+static const uint64_t P9N2_PERV_EC20_CPPM_CPMMR_SCOM = 0x340F0106ull;
+
+static const uint64_t P9N2_PERV_EC20_CPPM_CPMMR_SCOM1 = 0x340F0107ull;
+
+static const uint64_t P9N2_PERV_EC20_CPPM_CPMMR_SCOM2 = 0x340F0108ull;
+
+static const uint64_t P9N2_PERV_EC21_CPPM_CPMMR_SCOM = 0x350F0106ull;
+
+static const uint64_t P9N2_PERV_EC21_CPPM_CPMMR_SCOM1 = 0x350F0107ull;
+
+static const uint64_t P9N2_PERV_EC21_CPPM_CPMMR_SCOM2 = 0x350F0108ull;
+
+static const uint64_t P9N2_PERV_EC22_CPPM_CPMMR_SCOM = 0x360F0106ull;
+
+static const uint64_t P9N2_PERV_EC22_CPPM_CPMMR_SCOM1 = 0x360F0107ull;
+
+static const uint64_t P9N2_PERV_EC22_CPPM_CPMMR_SCOM2 = 0x360F0108ull;
+
+static const uint64_t P9N2_PERV_EC23_CPPM_CPMMR_SCOM = 0x370F0106ull;
+
+static const uint64_t P9N2_PERV_EC23_CPPM_CPMMR_SCOM1 = 0x370F0107ull;
+
+static const uint64_t P9N2_PERV_EC23_CPPM_CPMMR_SCOM2 = 0x370F0108ull;
+
+
+static const uint64_t P9N2_PERV_EC00_CPPM_CSAR = 0x200F0138ull;
+
+static const uint64_t P9N2_PERV_EC00_CPPM_CSAR_CLEAR = 0x200F0139ull;
+
+static const uint64_t P9N2_PERV_EC00_CPPM_CSAR_OR = 0x200F013Aull;
+
+static const uint64_t P9N2_PERV_EC01_CPPM_CSAR = 0x210F0138ull;
+
+static const uint64_t P9N2_PERV_EC01_CPPM_CSAR_CLEAR = 0x210F0139ull;
+
+static const uint64_t P9N2_PERV_EC01_CPPM_CSAR_OR = 0x210F013Aull;
+
+static const uint64_t P9N2_PERV_EC02_CPPM_CSAR = 0x220F0138ull;
+
+static const uint64_t P9N2_PERV_EC02_CPPM_CSAR_CLEAR = 0x220F0139ull;
+
+static const uint64_t P9N2_PERV_EC02_CPPM_CSAR_OR = 0x220F013Aull;
+
+static const uint64_t P9N2_PERV_EC03_CPPM_CSAR = 0x230F0138ull;
+
+static const uint64_t P9N2_PERV_EC03_CPPM_CSAR_CLEAR = 0x230F0139ull;
+
+static const uint64_t P9N2_PERV_EC03_CPPM_CSAR_OR = 0x230F013Aull;
+
+static const uint64_t P9N2_PERV_EC04_CPPM_CSAR = 0x240F0138ull;
+
+static const uint64_t P9N2_PERV_EC04_CPPM_CSAR_CLEAR = 0x240F0139ull;
+
+static const uint64_t P9N2_PERV_EC04_CPPM_CSAR_OR = 0x240F013Aull;
+
+static const uint64_t P9N2_PERV_EC05_CPPM_CSAR = 0x250F0138ull;
+
+static const uint64_t P9N2_PERV_EC05_CPPM_CSAR_CLEAR = 0x250F0139ull;
+
+static const uint64_t P9N2_PERV_EC05_CPPM_CSAR_OR = 0x250F013Aull;
+
+static const uint64_t P9N2_PERV_EC06_CPPM_CSAR = 0x260F0138ull;
+
+static const uint64_t P9N2_PERV_EC06_CPPM_CSAR_CLEAR = 0x260F0139ull;
+
+static const uint64_t P9N2_PERV_EC06_CPPM_CSAR_OR = 0x260F013Aull;
+
+static const uint64_t P9N2_PERV_EC07_CPPM_CSAR = 0x270F0138ull;
+
+static const uint64_t P9N2_PERV_EC07_CPPM_CSAR_CLEAR = 0x270F0139ull;
+
+static const uint64_t P9N2_PERV_EC07_CPPM_CSAR_OR = 0x270F013Aull;
+
+static const uint64_t P9N2_PERV_EC08_CPPM_CSAR = 0x280F0138ull;
+
+static const uint64_t P9N2_PERV_EC08_CPPM_CSAR_CLEAR = 0x280F0139ull;
+
+static const uint64_t P9N2_PERV_EC08_CPPM_CSAR_OR = 0x280F013Aull;
+
+static const uint64_t P9N2_PERV_EC09_CPPM_CSAR = 0x290F0138ull;
+
+static const uint64_t P9N2_PERV_EC09_CPPM_CSAR_CLEAR = 0x290F0139ull;
+
+static const uint64_t P9N2_PERV_EC09_CPPM_CSAR_OR = 0x290F013Aull;
+
+static const uint64_t P9N2_PERV_EC10_CPPM_CSAR = 0x2A0F0138ull;
+
+static const uint64_t P9N2_PERV_EC10_CPPM_CSAR_CLEAR = 0x2A0F0139ull;
+
+static const uint64_t P9N2_PERV_EC10_CPPM_CSAR_OR = 0x2A0F013Aull;
+
+static const uint64_t P9N2_PERV_EC11_CPPM_CSAR = 0x2B0F0138ull;
+
+static const uint64_t P9N2_PERV_EC11_CPPM_CSAR_CLEAR = 0x2B0F0139ull;
+
+static const uint64_t P9N2_PERV_EC11_CPPM_CSAR_OR = 0x2B0F013Aull;
+
+static const uint64_t P9N2_PERV_EC12_CPPM_CSAR = 0x2C0F0138ull;
+
+static const uint64_t P9N2_PERV_EC12_CPPM_CSAR_CLEAR = 0x2C0F0139ull;
+
+static const uint64_t P9N2_PERV_EC12_CPPM_CSAR_OR = 0x2C0F013Aull;
+
+static const uint64_t P9N2_PERV_EC13_CPPM_CSAR = 0x2D0F0138ull;
+
+static const uint64_t P9N2_PERV_EC13_CPPM_CSAR_CLEAR = 0x2D0F0139ull;
+
+static const uint64_t P9N2_PERV_EC13_CPPM_CSAR_OR = 0x2D0F013Aull;
+
+static const uint64_t P9N2_PERV_EC14_CPPM_CSAR = 0x2E0F0138ull;
+
+static const uint64_t P9N2_PERV_EC14_CPPM_CSAR_CLEAR = 0x2E0F0139ull;
+
+static const uint64_t P9N2_PERV_EC14_CPPM_CSAR_OR = 0x2E0F013Aull;
+
+static const uint64_t P9N2_PERV_EC15_CPPM_CSAR = 0x2F0F0138ull;
+
+static const uint64_t P9N2_PERV_EC15_CPPM_CSAR_CLEAR = 0x2F0F0139ull;
+
+static const uint64_t P9N2_PERV_EC15_CPPM_CSAR_OR = 0x2F0F013Aull;
+
+static const uint64_t P9N2_PERV_EC16_CPPM_CSAR = 0x300F0138ull;
+
+static const uint64_t P9N2_PERV_EC16_CPPM_CSAR_CLEAR = 0x300F0139ull;
+
+static const uint64_t P9N2_PERV_EC16_CPPM_CSAR_OR = 0x300F013Aull;
+
+static const uint64_t P9N2_PERV_EC17_CPPM_CSAR = 0x310F0138ull;
+
+static const uint64_t P9N2_PERV_EC17_CPPM_CSAR_CLEAR = 0x310F0139ull;
+
+static const uint64_t P9N2_PERV_EC17_CPPM_CSAR_OR = 0x310F013Aull;
+
+static const uint64_t P9N2_PERV_EC18_CPPM_CSAR = 0x320F0138ull;
+
+static const uint64_t P9N2_PERV_EC18_CPPM_CSAR_CLEAR = 0x320F0139ull;
+
+static const uint64_t P9N2_PERV_EC18_CPPM_CSAR_OR = 0x320F013Aull;
+
+static const uint64_t P9N2_PERV_EC19_CPPM_CSAR = 0x330F0138ull;
+
+static const uint64_t P9N2_PERV_EC19_CPPM_CSAR_CLEAR = 0x330F0139ull;
+
+static const uint64_t P9N2_PERV_EC19_CPPM_CSAR_OR = 0x330F013Aull;
+
+static const uint64_t P9N2_PERV_EC20_CPPM_CSAR = 0x340F0138ull;
+
+static const uint64_t P9N2_PERV_EC20_CPPM_CSAR_CLEAR = 0x340F0139ull;
+
+static const uint64_t P9N2_PERV_EC20_CPPM_CSAR_OR = 0x340F013Aull;
+
+static const uint64_t P9N2_PERV_EC21_CPPM_CSAR = 0x350F0138ull;
+
+static const uint64_t P9N2_PERV_EC21_CPPM_CSAR_CLEAR = 0x350F0139ull;
+
+static const uint64_t P9N2_PERV_EC21_CPPM_CSAR_OR = 0x350F013Aull;
+
+static const uint64_t P9N2_PERV_EC22_CPPM_CSAR = 0x360F0138ull;
+
+static const uint64_t P9N2_PERV_EC22_CPPM_CSAR_CLEAR = 0x360F0139ull;
+
+static const uint64_t P9N2_PERV_EC22_CPPM_CSAR_OR = 0x360F013Aull;
+
+static const uint64_t P9N2_PERV_EC23_CPPM_CSAR = 0x370F0138ull;
+
+static const uint64_t P9N2_PERV_EC23_CPPM_CSAR_CLEAR = 0x370F0139ull;
+
+static const uint64_t P9N2_PERV_EC23_CPPM_CSAR_OR = 0x370F013Aull;
+
+
+static const uint64_t P9N2_PERV_EC00_CPPM_ERR = 0x200F0121ull;
+
+static const uint64_t P9N2_PERV_EC01_CPPM_ERR = 0x210F0121ull;
+
+static const uint64_t P9N2_PERV_EC02_CPPM_ERR = 0x220F0121ull;
+
+static const uint64_t P9N2_PERV_EC03_CPPM_ERR = 0x230F0121ull;
+
+static const uint64_t P9N2_PERV_EC04_CPPM_ERR = 0x240F0121ull;
+
+static const uint64_t P9N2_PERV_EC05_CPPM_ERR = 0x250F0121ull;
+
+static const uint64_t P9N2_PERV_EC06_CPPM_ERR = 0x260F0121ull;
+
+static const uint64_t P9N2_PERV_EC07_CPPM_ERR = 0x270F0121ull;
+
+static const uint64_t P9N2_PERV_EC08_CPPM_ERR = 0x280F0121ull;
+
+static const uint64_t P9N2_PERV_EC09_CPPM_ERR = 0x290F0121ull;
+
+static const uint64_t P9N2_PERV_EC10_CPPM_ERR = 0x2A0F0121ull;
+
+static const uint64_t P9N2_PERV_EC11_CPPM_ERR = 0x2B0F0121ull;
+
+static const uint64_t P9N2_PERV_EC12_CPPM_ERR = 0x2C0F0121ull;
+
+static const uint64_t P9N2_PERV_EC13_CPPM_ERR = 0x2D0F0121ull;
+
+static const uint64_t P9N2_PERV_EC14_CPPM_ERR = 0x2E0F0121ull;
+
+static const uint64_t P9N2_PERV_EC15_CPPM_ERR = 0x2F0F0121ull;
+
+static const uint64_t P9N2_PERV_EC16_CPPM_ERR = 0x300F0121ull;
+
+static const uint64_t P9N2_PERV_EC17_CPPM_ERR = 0x310F0121ull;
+
+static const uint64_t P9N2_PERV_EC18_CPPM_ERR = 0x320F0121ull;
+
+static const uint64_t P9N2_PERV_EC19_CPPM_ERR = 0x330F0121ull;
+
+static const uint64_t P9N2_PERV_EC20_CPPM_ERR = 0x340F0121ull;
+
+static const uint64_t P9N2_PERV_EC21_CPPM_ERR = 0x350F0121ull;
+
+static const uint64_t P9N2_PERV_EC22_CPPM_ERR = 0x360F0121ull;
+
+static const uint64_t P9N2_PERV_EC23_CPPM_ERR = 0x370F0121ull;
+
+
+static const uint64_t P9N2_PERV_EC00_CPPM_ERRMSK = 0x200F0122ull;
+
+static const uint64_t P9N2_PERV_EC01_CPPM_ERRMSK = 0x210F0122ull;
+
+static const uint64_t P9N2_PERV_EC02_CPPM_ERRMSK = 0x220F0122ull;
+
+static const uint64_t P9N2_PERV_EC03_CPPM_ERRMSK = 0x230F0122ull;
+
+static const uint64_t P9N2_PERV_EC04_CPPM_ERRMSK = 0x240F0122ull;
+
+static const uint64_t P9N2_PERV_EC05_CPPM_ERRMSK = 0x250F0122ull;
+
+static const uint64_t P9N2_PERV_EC06_CPPM_ERRMSK = 0x260F0122ull;
+
+static const uint64_t P9N2_PERV_EC07_CPPM_ERRMSK = 0x270F0122ull;
+
+static const uint64_t P9N2_PERV_EC08_CPPM_ERRMSK = 0x280F0122ull;
+
+static const uint64_t P9N2_PERV_EC09_CPPM_ERRMSK = 0x290F0122ull;
+
+static const uint64_t P9N2_PERV_EC10_CPPM_ERRMSK = 0x2A0F0122ull;
+
+static const uint64_t P9N2_PERV_EC11_CPPM_ERRMSK = 0x2B0F0122ull;
+
+static const uint64_t P9N2_PERV_EC12_CPPM_ERRMSK = 0x2C0F0122ull;
+
+static const uint64_t P9N2_PERV_EC13_CPPM_ERRMSK = 0x2D0F0122ull;
+
+static const uint64_t P9N2_PERV_EC14_CPPM_ERRMSK = 0x2E0F0122ull;
+
+static const uint64_t P9N2_PERV_EC15_CPPM_ERRMSK = 0x2F0F0122ull;
+
+static const uint64_t P9N2_PERV_EC16_CPPM_ERRMSK = 0x300F0122ull;
+
+static const uint64_t P9N2_PERV_EC17_CPPM_ERRMSK = 0x310F0122ull;
+
+static const uint64_t P9N2_PERV_EC18_CPPM_ERRMSK = 0x320F0122ull;
+
+static const uint64_t P9N2_PERV_EC19_CPPM_ERRMSK = 0x330F0122ull;
+
+static const uint64_t P9N2_PERV_EC20_CPPM_ERRMSK = 0x340F0122ull;
+
+static const uint64_t P9N2_PERV_EC21_CPPM_ERRMSK = 0x350F0122ull;
+
+static const uint64_t P9N2_PERV_EC22_CPPM_ERRMSK = 0x360F0122ull;
+
+static const uint64_t P9N2_PERV_EC23_CPPM_ERRMSK = 0x370F0122ull;
+
+
+static const uint64_t P9N2_PERV_EC00_CPPM_IPPMCMD = 0x200F01C0ull;
+
+static const uint64_t P9N2_PERV_EC01_CPPM_IPPMCMD = 0x210F01C0ull;
+
+static const uint64_t P9N2_PERV_EC02_CPPM_IPPMCMD = 0x220F01C0ull;
+
+static const uint64_t P9N2_PERV_EC03_CPPM_IPPMCMD = 0x230F01C0ull;
+
+static const uint64_t P9N2_PERV_EC04_CPPM_IPPMCMD = 0x240F01C0ull;
+
+static const uint64_t P9N2_PERV_EC05_CPPM_IPPMCMD = 0x250F01C0ull;
+
+static const uint64_t P9N2_PERV_EC06_CPPM_IPPMCMD = 0x260F01C0ull;
+
+static const uint64_t P9N2_PERV_EC07_CPPM_IPPMCMD = 0x270F01C0ull;
+
+static const uint64_t P9N2_PERV_EC08_CPPM_IPPMCMD = 0x280F01C0ull;
+
+static const uint64_t P9N2_PERV_EC09_CPPM_IPPMCMD = 0x290F01C0ull;
+
+static const uint64_t P9N2_PERV_EC10_CPPM_IPPMCMD = 0x2A0F01C0ull;
+
+static const uint64_t P9N2_PERV_EC11_CPPM_IPPMCMD = 0x2B0F01C0ull;
+
+static const uint64_t P9N2_PERV_EC12_CPPM_IPPMCMD = 0x2C0F01C0ull;
+
+static const uint64_t P9N2_PERV_EC13_CPPM_IPPMCMD = 0x2D0F01C0ull;
+
+static const uint64_t P9N2_PERV_EC14_CPPM_IPPMCMD = 0x2E0F01C0ull;
+
+static const uint64_t P9N2_PERV_EC15_CPPM_IPPMCMD = 0x2F0F01C0ull;
+
+static const uint64_t P9N2_PERV_EC16_CPPM_IPPMCMD = 0x300F01C0ull;
+
+static const uint64_t P9N2_PERV_EC17_CPPM_IPPMCMD = 0x310F01C0ull;
+
+static const uint64_t P9N2_PERV_EC18_CPPM_IPPMCMD = 0x320F01C0ull;
+
+static const uint64_t P9N2_PERV_EC19_CPPM_IPPMCMD = 0x330F01C0ull;
+
+static const uint64_t P9N2_PERV_EC20_CPPM_IPPMCMD = 0x340F01C0ull;
+
+static const uint64_t P9N2_PERV_EC21_CPPM_IPPMCMD = 0x350F01C0ull;
+
+static const uint64_t P9N2_PERV_EC22_CPPM_IPPMCMD = 0x360F01C0ull;
+
+static const uint64_t P9N2_PERV_EC23_CPPM_IPPMCMD = 0x370F01C0ull;
+
+
+static const uint64_t P9N2_PERV_EC00_CPPM_IPPMRDATA = 0x200F01C3ull;
+
+static const uint64_t P9N2_PERV_EC01_CPPM_IPPMRDATA = 0x210F01C3ull;
+
+static const uint64_t P9N2_PERV_EC02_CPPM_IPPMRDATA = 0x220F01C3ull;
+
+static const uint64_t P9N2_PERV_EC03_CPPM_IPPMRDATA = 0x230F01C3ull;
+
+static const uint64_t P9N2_PERV_EC04_CPPM_IPPMRDATA = 0x240F01C3ull;
+
+static const uint64_t P9N2_PERV_EC05_CPPM_IPPMRDATA = 0x250F01C3ull;
+
+static const uint64_t P9N2_PERV_EC06_CPPM_IPPMRDATA = 0x260F01C3ull;
+
+static const uint64_t P9N2_PERV_EC07_CPPM_IPPMRDATA = 0x270F01C3ull;
+
+static const uint64_t P9N2_PERV_EC08_CPPM_IPPMRDATA = 0x280F01C3ull;
+
+static const uint64_t P9N2_PERV_EC09_CPPM_IPPMRDATA = 0x290F01C3ull;
+
+static const uint64_t P9N2_PERV_EC10_CPPM_IPPMRDATA = 0x2A0F01C3ull;
+
+static const uint64_t P9N2_PERV_EC11_CPPM_IPPMRDATA = 0x2B0F01C3ull;
+
+static const uint64_t P9N2_PERV_EC12_CPPM_IPPMRDATA = 0x2C0F01C3ull;
+
+static const uint64_t P9N2_PERV_EC13_CPPM_IPPMRDATA = 0x2D0F01C3ull;
+
+static const uint64_t P9N2_PERV_EC14_CPPM_IPPMRDATA = 0x2E0F01C3ull;
+
+static const uint64_t P9N2_PERV_EC15_CPPM_IPPMRDATA = 0x2F0F01C3ull;
+
+static const uint64_t P9N2_PERV_EC16_CPPM_IPPMRDATA = 0x300F01C3ull;
+
+static const uint64_t P9N2_PERV_EC17_CPPM_IPPMRDATA = 0x310F01C3ull;
+
+static const uint64_t P9N2_PERV_EC18_CPPM_IPPMRDATA = 0x320F01C3ull;
+
+static const uint64_t P9N2_PERV_EC19_CPPM_IPPMRDATA = 0x330F01C3ull;
+
+static const uint64_t P9N2_PERV_EC20_CPPM_IPPMRDATA = 0x340F01C3ull;
+
+static const uint64_t P9N2_PERV_EC21_CPPM_IPPMRDATA = 0x350F01C3ull;
+
+static const uint64_t P9N2_PERV_EC22_CPPM_IPPMRDATA = 0x360F01C3ull;
+
+static const uint64_t P9N2_PERV_EC23_CPPM_IPPMRDATA = 0x370F01C3ull;
+
+
+static const uint64_t P9N2_PERV_EC00_CPPM_IPPMSTAT = 0x200F01C1ull;
+
+static const uint64_t P9N2_PERV_EC01_CPPM_IPPMSTAT = 0x210F01C1ull;
+
+static const uint64_t P9N2_PERV_EC02_CPPM_IPPMSTAT = 0x220F01C1ull;
+
+static const uint64_t P9N2_PERV_EC03_CPPM_IPPMSTAT = 0x230F01C1ull;
+
+static const uint64_t P9N2_PERV_EC04_CPPM_IPPMSTAT = 0x240F01C1ull;
+
+static const uint64_t P9N2_PERV_EC05_CPPM_IPPMSTAT = 0x250F01C1ull;
+
+static const uint64_t P9N2_PERV_EC06_CPPM_IPPMSTAT = 0x260F01C1ull;
+
+static const uint64_t P9N2_PERV_EC07_CPPM_IPPMSTAT = 0x270F01C1ull;
+
+static const uint64_t P9N2_PERV_EC08_CPPM_IPPMSTAT = 0x280F01C1ull;
+
+static const uint64_t P9N2_PERV_EC09_CPPM_IPPMSTAT = 0x290F01C1ull;
+
+static const uint64_t P9N2_PERV_EC10_CPPM_IPPMSTAT = 0x2A0F01C1ull;
+
+static const uint64_t P9N2_PERV_EC11_CPPM_IPPMSTAT = 0x2B0F01C1ull;
+
+static const uint64_t P9N2_PERV_EC12_CPPM_IPPMSTAT = 0x2C0F01C1ull;
+
+static const uint64_t P9N2_PERV_EC13_CPPM_IPPMSTAT = 0x2D0F01C1ull;
+
+static const uint64_t P9N2_PERV_EC14_CPPM_IPPMSTAT = 0x2E0F01C1ull;
+
+static const uint64_t P9N2_PERV_EC15_CPPM_IPPMSTAT = 0x2F0F01C1ull;
+
+static const uint64_t P9N2_PERV_EC16_CPPM_IPPMSTAT = 0x300F01C1ull;
+
+static const uint64_t P9N2_PERV_EC17_CPPM_IPPMSTAT = 0x310F01C1ull;
+
+static const uint64_t P9N2_PERV_EC18_CPPM_IPPMSTAT = 0x320F01C1ull;
+
+static const uint64_t P9N2_PERV_EC19_CPPM_IPPMSTAT = 0x330F01C1ull;
+
+static const uint64_t P9N2_PERV_EC20_CPPM_IPPMSTAT = 0x340F01C1ull;
+
+static const uint64_t P9N2_PERV_EC21_CPPM_IPPMSTAT = 0x350F01C1ull;
+
+static const uint64_t P9N2_PERV_EC22_CPPM_IPPMSTAT = 0x360F01C1ull;
+
+static const uint64_t P9N2_PERV_EC23_CPPM_IPPMSTAT = 0x370F01C1ull;
+
+
+static const uint64_t P9N2_PERV_EC00_CPPM_IPPMWDATA = 0x200F01C2ull;
+
+static const uint64_t P9N2_PERV_EC01_CPPM_IPPMWDATA = 0x210F01C2ull;
+
+static const uint64_t P9N2_PERV_EC02_CPPM_IPPMWDATA = 0x220F01C2ull;
+
+static const uint64_t P9N2_PERV_EC03_CPPM_IPPMWDATA = 0x230F01C2ull;
+
+static const uint64_t P9N2_PERV_EC04_CPPM_IPPMWDATA = 0x240F01C2ull;
+
+static const uint64_t P9N2_PERV_EC05_CPPM_IPPMWDATA = 0x250F01C2ull;
+
+static const uint64_t P9N2_PERV_EC06_CPPM_IPPMWDATA = 0x260F01C2ull;
+
+static const uint64_t P9N2_PERV_EC07_CPPM_IPPMWDATA = 0x270F01C2ull;
+
+static const uint64_t P9N2_PERV_EC08_CPPM_IPPMWDATA = 0x280F01C2ull;
+
+static const uint64_t P9N2_PERV_EC09_CPPM_IPPMWDATA = 0x290F01C2ull;
+
+static const uint64_t P9N2_PERV_EC10_CPPM_IPPMWDATA = 0x2A0F01C2ull;
+
+static const uint64_t P9N2_PERV_EC11_CPPM_IPPMWDATA = 0x2B0F01C2ull;
+
+static const uint64_t P9N2_PERV_EC12_CPPM_IPPMWDATA = 0x2C0F01C2ull;
+
+static const uint64_t P9N2_PERV_EC13_CPPM_IPPMWDATA = 0x2D0F01C2ull;
+
+static const uint64_t P9N2_PERV_EC14_CPPM_IPPMWDATA = 0x2E0F01C2ull;
+
+static const uint64_t P9N2_PERV_EC15_CPPM_IPPMWDATA = 0x2F0F01C2ull;
+
+static const uint64_t P9N2_PERV_EC16_CPPM_IPPMWDATA = 0x300F01C2ull;
+
+static const uint64_t P9N2_PERV_EC17_CPPM_IPPMWDATA = 0x310F01C2ull;
+
+static const uint64_t P9N2_PERV_EC18_CPPM_IPPMWDATA = 0x320F01C2ull;
+
+static const uint64_t P9N2_PERV_EC19_CPPM_IPPMWDATA = 0x330F01C2ull;
+
+static const uint64_t P9N2_PERV_EC20_CPPM_IPPMWDATA = 0x340F01C2ull;
+
+static const uint64_t P9N2_PERV_EC21_CPPM_IPPMWDATA = 0x350F01C2ull;
+
+static const uint64_t P9N2_PERV_EC22_CPPM_IPPMWDATA = 0x360F01C2ull;
+
+static const uint64_t P9N2_PERV_EC23_CPPM_IPPMWDATA = 0x370F01C2ull;
+
+
+static const uint64_t P9N2_PERV_EC00_CPPM_NC0INDIR_SCOM = 0x200F0130ull;
+
+static const uint64_t P9N2_PERV_EC00_CPPM_NC0INDIR_SCOM1 = 0x200F0131ull;
+
+static const uint64_t P9N2_PERV_EC00_CPPM_NC0INDIR_SCOM2 = 0x200F0132ull;
+
+static const uint64_t P9N2_PERV_EC01_CPPM_NC0INDIR_SCOM = 0x210F0130ull;
+
+static const uint64_t P9N2_PERV_EC01_CPPM_NC0INDIR_SCOM1 = 0x210F0131ull;
+
+static const uint64_t P9N2_PERV_EC01_CPPM_NC0INDIR_SCOM2 = 0x210F0132ull;
+
+static const uint64_t P9N2_PERV_EC02_CPPM_NC0INDIR_SCOM = 0x220F0130ull;
+
+static const uint64_t P9N2_PERV_EC02_CPPM_NC0INDIR_SCOM1 = 0x220F0131ull;
+
+static const uint64_t P9N2_PERV_EC02_CPPM_NC0INDIR_SCOM2 = 0x220F0132ull;
+
+static const uint64_t P9N2_PERV_EC03_CPPM_NC0INDIR_SCOM = 0x230F0130ull;
+
+static const uint64_t P9N2_PERV_EC03_CPPM_NC0INDIR_SCOM1 = 0x230F0131ull;
+
+static const uint64_t P9N2_PERV_EC03_CPPM_NC0INDIR_SCOM2 = 0x230F0132ull;
+
+static const uint64_t P9N2_PERV_EC04_CPPM_NC0INDIR_SCOM = 0x240F0130ull;
+
+static const uint64_t P9N2_PERV_EC04_CPPM_NC0INDIR_SCOM1 = 0x240F0131ull;
+
+static const uint64_t P9N2_PERV_EC04_CPPM_NC0INDIR_SCOM2 = 0x240F0132ull;
+
+static const uint64_t P9N2_PERV_EC05_CPPM_NC0INDIR_SCOM = 0x250F0130ull;
+
+static const uint64_t P9N2_PERV_EC05_CPPM_NC0INDIR_SCOM1 = 0x250F0131ull;
+
+static const uint64_t P9N2_PERV_EC05_CPPM_NC0INDIR_SCOM2 = 0x250F0132ull;
+
+static const uint64_t P9N2_PERV_EC06_CPPM_NC0INDIR_SCOM = 0x260F0130ull;
+
+static const uint64_t P9N2_PERV_EC06_CPPM_NC0INDIR_SCOM1 = 0x260F0131ull;
+
+static const uint64_t P9N2_PERV_EC06_CPPM_NC0INDIR_SCOM2 = 0x260F0132ull;
+
+static const uint64_t P9N2_PERV_EC07_CPPM_NC0INDIR_SCOM = 0x270F0130ull;
+
+static const uint64_t P9N2_PERV_EC07_CPPM_NC0INDIR_SCOM1 = 0x270F0131ull;
+
+static const uint64_t P9N2_PERV_EC07_CPPM_NC0INDIR_SCOM2 = 0x270F0132ull;
+
+static const uint64_t P9N2_PERV_EC08_CPPM_NC0INDIR_SCOM = 0x280F0130ull;
+
+static const uint64_t P9N2_PERV_EC08_CPPM_NC0INDIR_SCOM1 = 0x280F0131ull;
+
+static const uint64_t P9N2_PERV_EC08_CPPM_NC0INDIR_SCOM2 = 0x280F0132ull;
+
+static const uint64_t P9N2_PERV_EC09_CPPM_NC0INDIR_SCOM = 0x290F0130ull;
+
+static const uint64_t P9N2_PERV_EC09_CPPM_NC0INDIR_SCOM1 = 0x290F0131ull;
+
+static const uint64_t P9N2_PERV_EC09_CPPM_NC0INDIR_SCOM2 = 0x290F0132ull;
+
+static const uint64_t P9N2_PERV_EC10_CPPM_NC0INDIR_SCOM = 0x2A0F0130ull;
+
+static const uint64_t P9N2_PERV_EC10_CPPM_NC0INDIR_SCOM1 = 0x2A0F0131ull;
+
+static const uint64_t P9N2_PERV_EC10_CPPM_NC0INDIR_SCOM2 = 0x2A0F0132ull;
+
+static const uint64_t P9N2_PERV_EC11_CPPM_NC0INDIR_SCOM = 0x2B0F0130ull;
+
+static const uint64_t P9N2_PERV_EC11_CPPM_NC0INDIR_SCOM1 = 0x2B0F0131ull;
+
+static const uint64_t P9N2_PERV_EC11_CPPM_NC0INDIR_SCOM2 = 0x2B0F0132ull;
+
+static const uint64_t P9N2_PERV_EC12_CPPM_NC0INDIR_SCOM = 0x2C0F0130ull;
+
+static const uint64_t P9N2_PERV_EC12_CPPM_NC0INDIR_SCOM1 = 0x2C0F0131ull;
+
+static const uint64_t P9N2_PERV_EC12_CPPM_NC0INDIR_SCOM2 = 0x2C0F0132ull;
+
+static const uint64_t P9N2_PERV_EC13_CPPM_NC0INDIR_SCOM = 0x2D0F0130ull;
+
+static const uint64_t P9N2_PERV_EC13_CPPM_NC0INDIR_SCOM1 = 0x2D0F0131ull;
+
+static const uint64_t P9N2_PERV_EC13_CPPM_NC0INDIR_SCOM2 = 0x2D0F0132ull;
+
+static const uint64_t P9N2_PERV_EC14_CPPM_NC0INDIR_SCOM = 0x2E0F0130ull;
+
+static const uint64_t P9N2_PERV_EC14_CPPM_NC0INDIR_SCOM1 = 0x2E0F0131ull;
+
+static const uint64_t P9N2_PERV_EC14_CPPM_NC0INDIR_SCOM2 = 0x2E0F0132ull;
+
+static const uint64_t P9N2_PERV_EC15_CPPM_NC0INDIR_SCOM = 0x2F0F0130ull;
+
+static const uint64_t P9N2_PERV_EC15_CPPM_NC0INDIR_SCOM1 = 0x2F0F0131ull;
+
+static const uint64_t P9N2_PERV_EC15_CPPM_NC0INDIR_SCOM2 = 0x2F0F0132ull;
+
+static const uint64_t P9N2_PERV_EC16_CPPM_NC0INDIR_SCOM = 0x300F0130ull;
+
+static const uint64_t P9N2_PERV_EC16_CPPM_NC0INDIR_SCOM1 = 0x300F0131ull;
+
+static const uint64_t P9N2_PERV_EC16_CPPM_NC0INDIR_SCOM2 = 0x300F0132ull;
+
+static const uint64_t P9N2_PERV_EC17_CPPM_NC0INDIR_SCOM = 0x310F0130ull;
+
+static const uint64_t P9N2_PERV_EC17_CPPM_NC0INDIR_SCOM1 = 0x310F0131ull;
+
+static const uint64_t P9N2_PERV_EC17_CPPM_NC0INDIR_SCOM2 = 0x310F0132ull;
+
+static const uint64_t P9N2_PERV_EC18_CPPM_NC0INDIR_SCOM = 0x320F0130ull;
+
+static const uint64_t P9N2_PERV_EC18_CPPM_NC0INDIR_SCOM1 = 0x320F0131ull;
+
+static const uint64_t P9N2_PERV_EC18_CPPM_NC0INDIR_SCOM2 = 0x320F0132ull;
+
+static const uint64_t P9N2_PERV_EC19_CPPM_NC0INDIR_SCOM = 0x330F0130ull;
+
+static const uint64_t P9N2_PERV_EC19_CPPM_NC0INDIR_SCOM1 = 0x330F0131ull;
+
+static const uint64_t P9N2_PERV_EC19_CPPM_NC0INDIR_SCOM2 = 0x330F0132ull;
+
+static const uint64_t P9N2_PERV_EC20_CPPM_NC0INDIR_SCOM = 0x340F0130ull;
+
+static const uint64_t P9N2_PERV_EC20_CPPM_NC0INDIR_SCOM1 = 0x340F0131ull;
+
+static const uint64_t P9N2_PERV_EC20_CPPM_NC0INDIR_SCOM2 = 0x340F0132ull;
+
+static const uint64_t P9N2_PERV_EC21_CPPM_NC0INDIR_SCOM = 0x350F0130ull;
+
+static const uint64_t P9N2_PERV_EC21_CPPM_NC0INDIR_SCOM1 = 0x350F0131ull;
+
+static const uint64_t P9N2_PERV_EC21_CPPM_NC0INDIR_SCOM2 = 0x350F0132ull;
+
+static const uint64_t P9N2_PERV_EC22_CPPM_NC0INDIR_SCOM = 0x360F0130ull;
+
+static const uint64_t P9N2_PERV_EC22_CPPM_NC0INDIR_SCOM1 = 0x360F0131ull;
+
+static const uint64_t P9N2_PERV_EC22_CPPM_NC0INDIR_SCOM2 = 0x360F0132ull;
+
+static const uint64_t P9N2_PERV_EC23_CPPM_NC0INDIR_SCOM = 0x370F0130ull;
+
+static const uint64_t P9N2_PERV_EC23_CPPM_NC0INDIR_SCOM1 = 0x370F0131ull;
+
+static const uint64_t P9N2_PERV_EC23_CPPM_NC0INDIR_SCOM2 = 0x370F0132ull;
+
+
+static const uint64_t P9N2_PERV_EC00_CPPM_NC1INDIR_SCOM = 0x200F0133ull;
+
+static const uint64_t P9N2_PERV_EC00_CPPM_NC1INDIR_SCOM1 = 0x200F0134ull;
+
+static const uint64_t P9N2_PERV_EC00_CPPM_NC1INDIR_SCOM2 = 0x200F0135ull;
+
+static const uint64_t P9N2_PERV_EC01_CPPM_NC1INDIR_SCOM = 0x210F0133ull;
+
+static const uint64_t P9N2_PERV_EC01_CPPM_NC1INDIR_SCOM1 = 0x210F0134ull;
+
+static const uint64_t P9N2_PERV_EC01_CPPM_NC1INDIR_SCOM2 = 0x210F0135ull;
+
+static const uint64_t P9N2_PERV_EC02_CPPM_NC1INDIR_SCOM = 0x220F0133ull;
+
+static const uint64_t P9N2_PERV_EC02_CPPM_NC1INDIR_SCOM1 = 0x220F0134ull;
+
+static const uint64_t P9N2_PERV_EC02_CPPM_NC1INDIR_SCOM2 = 0x220F0135ull;
+
+static const uint64_t P9N2_PERV_EC03_CPPM_NC1INDIR_SCOM = 0x230F0133ull;
+
+static const uint64_t P9N2_PERV_EC03_CPPM_NC1INDIR_SCOM1 = 0x230F0134ull;
+
+static const uint64_t P9N2_PERV_EC03_CPPM_NC1INDIR_SCOM2 = 0x230F0135ull;
+
+static const uint64_t P9N2_PERV_EC04_CPPM_NC1INDIR_SCOM = 0x240F0133ull;
+
+static const uint64_t P9N2_PERV_EC04_CPPM_NC1INDIR_SCOM1 = 0x240F0134ull;
+
+static const uint64_t P9N2_PERV_EC04_CPPM_NC1INDIR_SCOM2 = 0x240F0135ull;
+
+static const uint64_t P9N2_PERV_EC05_CPPM_NC1INDIR_SCOM = 0x250F0133ull;
+
+static const uint64_t P9N2_PERV_EC05_CPPM_NC1INDIR_SCOM1 = 0x250F0134ull;
+
+static const uint64_t P9N2_PERV_EC05_CPPM_NC1INDIR_SCOM2 = 0x250F0135ull;
+
+static const uint64_t P9N2_PERV_EC06_CPPM_NC1INDIR_SCOM = 0x260F0133ull;
+
+static const uint64_t P9N2_PERV_EC06_CPPM_NC1INDIR_SCOM1 = 0x260F0134ull;
+
+static const uint64_t P9N2_PERV_EC06_CPPM_NC1INDIR_SCOM2 = 0x260F0135ull;
+
+static const uint64_t P9N2_PERV_EC07_CPPM_NC1INDIR_SCOM = 0x270F0133ull;
+
+static const uint64_t P9N2_PERV_EC07_CPPM_NC1INDIR_SCOM1 = 0x270F0134ull;
+
+static const uint64_t P9N2_PERV_EC07_CPPM_NC1INDIR_SCOM2 = 0x270F0135ull;
+
+static const uint64_t P9N2_PERV_EC08_CPPM_NC1INDIR_SCOM = 0x280F0133ull;
+
+static const uint64_t P9N2_PERV_EC08_CPPM_NC1INDIR_SCOM1 = 0x280F0134ull;
+
+static const uint64_t P9N2_PERV_EC08_CPPM_NC1INDIR_SCOM2 = 0x280F0135ull;
+
+static const uint64_t P9N2_PERV_EC09_CPPM_NC1INDIR_SCOM = 0x290F0133ull;
+
+static const uint64_t P9N2_PERV_EC09_CPPM_NC1INDIR_SCOM1 = 0x290F0134ull;
+
+static const uint64_t P9N2_PERV_EC09_CPPM_NC1INDIR_SCOM2 = 0x290F0135ull;
+
+static const uint64_t P9N2_PERV_EC10_CPPM_NC1INDIR_SCOM = 0x2A0F0133ull;
+
+static const uint64_t P9N2_PERV_EC10_CPPM_NC1INDIR_SCOM1 = 0x2A0F0134ull;
+
+static const uint64_t P9N2_PERV_EC10_CPPM_NC1INDIR_SCOM2 = 0x2A0F0135ull;
+
+static const uint64_t P9N2_PERV_EC11_CPPM_NC1INDIR_SCOM = 0x2B0F0133ull;
+
+static const uint64_t P9N2_PERV_EC11_CPPM_NC1INDIR_SCOM1 = 0x2B0F0134ull;
+
+static const uint64_t P9N2_PERV_EC11_CPPM_NC1INDIR_SCOM2 = 0x2B0F0135ull;
+
+static const uint64_t P9N2_PERV_EC12_CPPM_NC1INDIR_SCOM = 0x2C0F0133ull;
+
+static const uint64_t P9N2_PERV_EC12_CPPM_NC1INDIR_SCOM1 = 0x2C0F0134ull;
+
+static const uint64_t P9N2_PERV_EC12_CPPM_NC1INDIR_SCOM2 = 0x2C0F0135ull;
+
+static const uint64_t P9N2_PERV_EC13_CPPM_NC1INDIR_SCOM = 0x2D0F0133ull;
+
+static const uint64_t P9N2_PERV_EC13_CPPM_NC1INDIR_SCOM1 = 0x2D0F0134ull;
+
+static const uint64_t P9N2_PERV_EC13_CPPM_NC1INDIR_SCOM2 = 0x2D0F0135ull;
+
+static const uint64_t P9N2_PERV_EC14_CPPM_NC1INDIR_SCOM = 0x2E0F0133ull;
+
+static const uint64_t P9N2_PERV_EC14_CPPM_NC1INDIR_SCOM1 = 0x2E0F0134ull;
+
+static const uint64_t P9N2_PERV_EC14_CPPM_NC1INDIR_SCOM2 = 0x2E0F0135ull;
+
+static const uint64_t P9N2_PERV_EC15_CPPM_NC1INDIR_SCOM = 0x2F0F0133ull;
+
+static const uint64_t P9N2_PERV_EC15_CPPM_NC1INDIR_SCOM1 = 0x2F0F0134ull;
+
+static const uint64_t P9N2_PERV_EC15_CPPM_NC1INDIR_SCOM2 = 0x2F0F0135ull;
+
+static const uint64_t P9N2_PERV_EC16_CPPM_NC1INDIR_SCOM = 0x300F0133ull;
+
+static const uint64_t P9N2_PERV_EC16_CPPM_NC1INDIR_SCOM1 = 0x300F0134ull;
+
+static const uint64_t P9N2_PERV_EC16_CPPM_NC1INDIR_SCOM2 = 0x300F0135ull;
+
+static const uint64_t P9N2_PERV_EC17_CPPM_NC1INDIR_SCOM = 0x310F0133ull;
+
+static const uint64_t P9N2_PERV_EC17_CPPM_NC1INDIR_SCOM1 = 0x310F0134ull;
+
+static const uint64_t P9N2_PERV_EC17_CPPM_NC1INDIR_SCOM2 = 0x310F0135ull;
+
+static const uint64_t P9N2_PERV_EC18_CPPM_NC1INDIR_SCOM = 0x320F0133ull;
+
+static const uint64_t P9N2_PERV_EC18_CPPM_NC1INDIR_SCOM1 = 0x320F0134ull;
+
+static const uint64_t P9N2_PERV_EC18_CPPM_NC1INDIR_SCOM2 = 0x320F0135ull;
+
+static const uint64_t P9N2_PERV_EC19_CPPM_NC1INDIR_SCOM = 0x330F0133ull;
+
+static const uint64_t P9N2_PERV_EC19_CPPM_NC1INDIR_SCOM1 = 0x330F0134ull;
+
+static const uint64_t P9N2_PERV_EC19_CPPM_NC1INDIR_SCOM2 = 0x330F0135ull;
+
+static const uint64_t P9N2_PERV_EC20_CPPM_NC1INDIR_SCOM = 0x340F0133ull;
+
+static const uint64_t P9N2_PERV_EC20_CPPM_NC1INDIR_SCOM1 = 0x340F0134ull;
+
+static const uint64_t P9N2_PERV_EC20_CPPM_NC1INDIR_SCOM2 = 0x340F0135ull;
+
+static const uint64_t P9N2_PERV_EC21_CPPM_NC1INDIR_SCOM = 0x350F0133ull;
+
+static const uint64_t P9N2_PERV_EC21_CPPM_NC1INDIR_SCOM1 = 0x350F0134ull;
+
+static const uint64_t P9N2_PERV_EC21_CPPM_NC1INDIR_SCOM2 = 0x350F0135ull;
+
+static const uint64_t P9N2_PERV_EC22_CPPM_NC1INDIR_SCOM = 0x360F0133ull;
+
+static const uint64_t P9N2_PERV_EC22_CPPM_NC1INDIR_SCOM1 = 0x360F0134ull;
+
+static const uint64_t P9N2_PERV_EC22_CPPM_NC1INDIR_SCOM2 = 0x360F0135ull;
+
+static const uint64_t P9N2_PERV_EC23_CPPM_NC1INDIR_SCOM = 0x370F0133ull;
+
+static const uint64_t P9N2_PERV_EC23_CPPM_NC1INDIR_SCOM1 = 0x370F0134ull;
+
+static const uint64_t P9N2_PERV_EC23_CPPM_NC1INDIR_SCOM2 = 0x370F0135ull;
+
+
+static const uint64_t P9N2_PERV_EC00_CPPM_PECES = 0x200F01AFull;
+
+static const uint64_t P9N2_PERV_EC01_CPPM_PECES = 0x210F01AFull;
+
+static const uint64_t P9N2_PERV_EC02_CPPM_PECES = 0x220F01AFull;
+
+static const uint64_t P9N2_PERV_EC03_CPPM_PECES = 0x230F01AFull;
+
+static const uint64_t P9N2_PERV_EC04_CPPM_PECES = 0x240F01AFull;
+
+static const uint64_t P9N2_PERV_EC05_CPPM_PECES = 0x250F01AFull;
+
+static const uint64_t P9N2_PERV_EC06_CPPM_PECES = 0x260F01AFull;
+
+static const uint64_t P9N2_PERV_EC07_CPPM_PECES = 0x270F01AFull;
+
+static const uint64_t P9N2_PERV_EC08_CPPM_PECES = 0x280F01AFull;
+
+static const uint64_t P9N2_PERV_EC09_CPPM_PECES = 0x290F01AFull;
+
+static const uint64_t P9N2_PERV_EC10_CPPM_PECES = 0x2A0F01AFull;
+
+static const uint64_t P9N2_PERV_EC11_CPPM_PECES = 0x2B0F01AFull;
+
+static const uint64_t P9N2_PERV_EC12_CPPM_PECES = 0x2C0F01AFull;
+
+static const uint64_t P9N2_PERV_EC13_CPPM_PECES = 0x2D0F01AFull;
+
+static const uint64_t P9N2_PERV_EC14_CPPM_PECES = 0x2E0F01AFull;
+
+static const uint64_t P9N2_PERV_EC15_CPPM_PECES = 0x2F0F01AFull;
+
+static const uint64_t P9N2_PERV_EC16_CPPM_PECES = 0x300F01AFull;
+
+static const uint64_t P9N2_PERV_EC17_CPPM_PECES = 0x310F01AFull;
+
+static const uint64_t P9N2_PERV_EC18_CPPM_PECES = 0x320F01AFull;
+
+static const uint64_t P9N2_PERV_EC19_CPPM_PECES = 0x330F01AFull;
+
+static const uint64_t P9N2_PERV_EC20_CPPM_PECES = 0x340F01AFull;
+
+static const uint64_t P9N2_PERV_EC21_CPPM_PECES = 0x350F01AFull;
+
+static const uint64_t P9N2_PERV_EC22_CPPM_PECES = 0x360F01AFull;
+
+static const uint64_t P9N2_PERV_EC23_CPPM_PECES = 0x370F01AFull;
+
+
+static const uint64_t P9N2_PERV_EC00_CPPM_PERRSUM = 0x200F0120ull;
+
+static const uint64_t P9N2_PERV_EC01_CPPM_PERRSUM = 0x210F0120ull;
+
+static const uint64_t P9N2_PERV_EC02_CPPM_PERRSUM = 0x220F0120ull;
+
+static const uint64_t P9N2_PERV_EC03_CPPM_PERRSUM = 0x230F0120ull;
+
+static const uint64_t P9N2_PERV_EC04_CPPM_PERRSUM = 0x240F0120ull;
+
+static const uint64_t P9N2_PERV_EC05_CPPM_PERRSUM = 0x250F0120ull;
+
+static const uint64_t P9N2_PERV_EC06_CPPM_PERRSUM = 0x260F0120ull;
+
+static const uint64_t P9N2_PERV_EC07_CPPM_PERRSUM = 0x270F0120ull;
+
+static const uint64_t P9N2_PERV_EC08_CPPM_PERRSUM = 0x280F0120ull;
+
+static const uint64_t P9N2_PERV_EC09_CPPM_PERRSUM = 0x290F0120ull;
+
+static const uint64_t P9N2_PERV_EC10_CPPM_PERRSUM = 0x2A0F0120ull;
+
+static const uint64_t P9N2_PERV_EC11_CPPM_PERRSUM = 0x2B0F0120ull;
+
+static const uint64_t P9N2_PERV_EC12_CPPM_PERRSUM = 0x2C0F0120ull;
+
+static const uint64_t P9N2_PERV_EC13_CPPM_PERRSUM = 0x2D0F0120ull;
+
+static const uint64_t P9N2_PERV_EC14_CPPM_PERRSUM = 0x2E0F0120ull;
+
+static const uint64_t P9N2_PERV_EC15_CPPM_PERRSUM = 0x2F0F0120ull;
+
+static const uint64_t P9N2_PERV_EC16_CPPM_PERRSUM = 0x300F0120ull;
+
+static const uint64_t P9N2_PERV_EC17_CPPM_PERRSUM = 0x310F0120ull;
+
+static const uint64_t P9N2_PERV_EC18_CPPM_PERRSUM = 0x320F0120ull;
+
+static const uint64_t P9N2_PERV_EC19_CPPM_PERRSUM = 0x330F0120ull;
+
+static const uint64_t P9N2_PERV_EC20_CPPM_PERRSUM = 0x340F0120ull;
+
+static const uint64_t P9N2_PERV_EC21_CPPM_PERRSUM = 0x350F0120ull;
+
+static const uint64_t P9N2_PERV_EC22_CPPM_PERRSUM = 0x360F0120ull;
+
+static const uint64_t P9N2_PERV_EC23_CPPM_PERRSUM = 0x370F0120ull;
+
+
+static const uint64_t P9N2_PERV_CRSIC = 0x00030005ull;
+
+static const uint64_t P9N2_PERV_PIB_CRSIC = 0x00030005ull;
+
+static const uint64_t P9N2_PERV_0_PIB2OPB0_CRSIC = 0x00020005ull;
+
+static const uint64_t P9N2_PERV_0_PIB2OPB1_CRSIC = 0x00020015ull;
+
+static const uint64_t P9N2_PERV_PIB2OPB0_CRSIC = 0x00020005ull;
+
+static const uint64_t P9N2_PERV_PIB2OPB1_CRSIC = 0x00020015ull;
+
+
+static const uint64_t P9N2_PERV_CRSIM = 0x00030006ull;
+
+static const uint64_t P9N2_PERV_PIB_CRSIM = 0x00030006ull;
+
+static const uint64_t P9N2_PERV_0_PIB2OPB0_CRSIM = 0x00020006ull;
+
+static const uint64_t P9N2_PERV_0_PIB2OPB1_CRSIM = 0x00020016ull;
+
+static const uint64_t P9N2_PERV_PIB2OPB0_CRSIM = 0x00020006ull;
+
+static const uint64_t P9N2_PERV_PIB2OPB1_CRSIM = 0x00020016ull;
+
+
+static const uint64_t P9N2_PERV_CRSIS = 0x00030007ull;
+
+static const uint64_t P9N2_PERV_PIB_CRSIS = 0x00030007ull;
+
+static const uint64_t P9N2_PERV_0_PIB2OPB0_CRSIS = 0x00020007ull;
+
+static const uint64_t P9N2_PERV_0_PIB2OPB1_CRSIS = 0x00020017ull;
+
+static const uint64_t P9N2_PERV_PIB2OPB0_CRSIS = 0x00020007ull;
+
+static const uint64_t P9N2_PERV_PIB2OPB1_CRSIS = 0x00020017ull;
+
+
+static const uint64_t P9N2_PERV_CTRL_ATOMIC_LOCK_REG = 0x000003FFull;
+
+static const uint64_t P9N2_PERV_TP_CTRL_ATOMIC_LOCK_REG = 0x010003FFull;
+
+static const uint64_t P9N2_PERV_N0_CTRL_ATOMIC_LOCK_REG = 0x020003FFull;
+
+static const uint64_t P9N2_PERV_N1_CTRL_ATOMIC_LOCK_REG = 0x030003FFull;
+
+static const uint64_t P9N2_PERV_N2_CTRL_ATOMIC_LOCK_REG = 0x040003FFull;
+
+static const uint64_t P9N2_PERV_N3_CTRL_ATOMIC_LOCK_REG = 0x050003FFull;
+
+static const uint64_t P9N2_PERV_XB_CTRL_ATOMIC_LOCK_REG = 0x060003FFull;
+
+static const uint64_t P9N2_PERV_MC01_CTRL_ATOMIC_LOCK_REG = 0x070003FFull;
+
+static const uint64_t P9N2_PERV_MC23_CTRL_ATOMIC_LOCK_REG = 0x080003FFull;
+
+static const uint64_t P9N2_PERV_OB0_CTRL_ATOMIC_LOCK_REG = 0x090003FFull;
+
+static const uint64_t P9N2_PERV_OB3_CTRL_ATOMIC_LOCK_REG = 0x0C0003FFull;
+
+static const uint64_t P9N2_PERV_PCI0_CTRL_ATOMIC_LOCK_REG = 0x0D0003FFull;
+
+static const uint64_t P9N2_PERV_PCI1_CTRL_ATOMIC_LOCK_REG = 0x0E0003FFull;
+
+static const uint64_t P9N2_PERV_PCI2_CTRL_ATOMIC_LOCK_REG = 0x0F0003FFull;
+
+static const uint64_t P9N2_PERV_EP00_CTRL_ATOMIC_LOCK_REG = 0x100003FFull;
+
+static const uint64_t P9N2_PERV_EP01_CTRL_ATOMIC_LOCK_REG = 0x110003FFull;
+
+static const uint64_t P9N2_PERV_EP02_CTRL_ATOMIC_LOCK_REG = 0x120003FFull;
+
+static const uint64_t P9N2_PERV_EP03_CTRL_ATOMIC_LOCK_REG = 0x130003FFull;
+
+static const uint64_t P9N2_PERV_EP04_CTRL_ATOMIC_LOCK_REG = 0x140003FFull;
+
+static const uint64_t P9N2_PERV_EP05_CTRL_ATOMIC_LOCK_REG = 0x150003FFull;
+
+static const uint64_t P9N2_PERV_EC00_CTRL_ATOMIC_LOCK_REG = 0x200003FFull;
+
+static const uint64_t P9N2_PERV_EC01_CTRL_ATOMIC_LOCK_REG = 0x210003FFull;
+
+static const uint64_t P9N2_PERV_EC02_CTRL_ATOMIC_LOCK_REG = 0x220003FFull;
+
+static const uint64_t P9N2_PERV_EC03_CTRL_ATOMIC_LOCK_REG = 0x230003FFull;
+
+static const uint64_t P9N2_PERV_EC04_CTRL_ATOMIC_LOCK_REG = 0x240003FFull;
+
+static const uint64_t P9N2_PERV_EC05_CTRL_ATOMIC_LOCK_REG = 0x250003FFull;
+
+static const uint64_t P9N2_PERV_EC06_CTRL_ATOMIC_LOCK_REG = 0x260003FFull;
+
+static const uint64_t P9N2_PERV_EC07_CTRL_ATOMIC_LOCK_REG = 0x270003FFull;
+
+static const uint64_t P9N2_PERV_EC08_CTRL_ATOMIC_LOCK_REG = 0x280003FFull;
+
+static const uint64_t P9N2_PERV_EC09_CTRL_ATOMIC_LOCK_REG = 0x290003FFull;
+
+static const uint64_t P9N2_PERV_EC10_CTRL_ATOMIC_LOCK_REG = 0x2A0003FFull;
+
+static const uint64_t P9N2_PERV_EC11_CTRL_ATOMIC_LOCK_REG = 0x2B0003FFull;
+
+static const uint64_t P9N2_PERV_EC12_CTRL_ATOMIC_LOCK_REG = 0x2C0003FFull;
+
+static const uint64_t P9N2_PERV_EC13_CTRL_ATOMIC_LOCK_REG = 0x2D0003FFull;
+
+static const uint64_t P9N2_PERV_EC14_CTRL_ATOMIC_LOCK_REG = 0x2E0003FFull;
+
+static const uint64_t P9N2_PERV_EC15_CTRL_ATOMIC_LOCK_REG = 0x2F0003FFull;
+
+static const uint64_t P9N2_PERV_EC16_CTRL_ATOMIC_LOCK_REG = 0x300003FFull;
+
+static const uint64_t P9N2_PERV_EC17_CTRL_ATOMIC_LOCK_REG = 0x310003FFull;
+
+static const uint64_t P9N2_PERV_EC18_CTRL_ATOMIC_LOCK_REG = 0x320003FFull;
+
+static const uint64_t P9N2_PERV_EC19_CTRL_ATOMIC_LOCK_REG = 0x330003FFull;
+
+static const uint64_t P9N2_PERV_EC20_CTRL_ATOMIC_LOCK_REG = 0x340003FFull;
+
+static const uint64_t P9N2_PERV_EC21_CTRL_ATOMIC_LOCK_REG = 0x350003FFull;
+
+static const uint64_t P9N2_PERV_EC22_CTRL_ATOMIC_LOCK_REG = 0x360003FFull;
+
+static const uint64_t P9N2_PERV_EC23_CTRL_ATOMIC_LOCK_REG = 0x370003FFull;
+
+
+static const uint64_t P9N2_PERV_CTRL_PROTECT_MODE_REG = 0x000003FEull;
+
+static const uint64_t P9N2_PERV_TP_CTRL_PROTECT_MODE_REG = 0x010003FEull;
+
+static const uint64_t P9N2_PERV_N0_CTRL_PROTECT_MODE_REG = 0x020003FEull;
+
+static const uint64_t P9N2_PERV_N1_CTRL_PROTECT_MODE_REG = 0x030003FEull;
+
+static const uint64_t P9N2_PERV_N2_CTRL_PROTECT_MODE_REG = 0x040003FEull;
+
+static const uint64_t P9N2_PERV_N3_CTRL_PROTECT_MODE_REG = 0x050003FEull;
+
+static const uint64_t P9N2_PERV_XB_CTRL_PROTECT_MODE_REG = 0x060003FEull;
+
+static const uint64_t P9N2_PERV_MC01_CTRL_PROTECT_MODE_REG = 0x070003FEull;
+
+static const uint64_t P9N2_PERV_MC23_CTRL_PROTECT_MODE_REG = 0x080003FEull;
+
+static const uint64_t P9N2_PERV_OB0_CTRL_PROTECT_MODE_REG = 0x090003FEull;
+
+static const uint64_t P9N2_PERV_OB3_CTRL_PROTECT_MODE_REG = 0x0C0003FEull;
+
+static const uint64_t P9N2_PERV_PCI0_CTRL_PROTECT_MODE_REG = 0x0D0003FEull;
+
+static const uint64_t P9N2_PERV_PCI1_CTRL_PROTECT_MODE_REG = 0x0E0003FEull;
+
+static const uint64_t P9N2_PERV_PCI2_CTRL_PROTECT_MODE_REG = 0x0F0003FEull;
+
+static const uint64_t P9N2_PERV_EP00_CTRL_PROTECT_MODE_REG = 0x100003FEull;
+
+static const uint64_t P9N2_PERV_EP01_CTRL_PROTECT_MODE_REG = 0x110003FEull;
+
+static const uint64_t P9N2_PERV_EP02_CTRL_PROTECT_MODE_REG = 0x120003FEull;
+
+static const uint64_t P9N2_PERV_EP03_CTRL_PROTECT_MODE_REG = 0x130003FEull;
+
+static const uint64_t P9N2_PERV_EP04_CTRL_PROTECT_MODE_REG = 0x140003FEull;
+
+static const uint64_t P9N2_PERV_EP05_CTRL_PROTECT_MODE_REG = 0x150003FEull;
+
+static const uint64_t P9N2_PERV_EC00_CTRL_PROTECT_MODE_REG = 0x200003FEull;
+
+static const uint64_t P9N2_PERV_EC01_CTRL_PROTECT_MODE_REG = 0x210003FEull;
+
+static const uint64_t P9N2_PERV_EC02_CTRL_PROTECT_MODE_REG = 0x220003FEull;
+
+static const uint64_t P9N2_PERV_EC03_CTRL_PROTECT_MODE_REG = 0x230003FEull;
+
+static const uint64_t P9N2_PERV_EC04_CTRL_PROTECT_MODE_REG = 0x240003FEull;
+
+static const uint64_t P9N2_PERV_EC05_CTRL_PROTECT_MODE_REG = 0x250003FEull;
+
+static const uint64_t P9N2_PERV_EC06_CTRL_PROTECT_MODE_REG = 0x260003FEull;
+
+static const uint64_t P9N2_PERV_EC07_CTRL_PROTECT_MODE_REG = 0x270003FEull;
+
+static const uint64_t P9N2_PERV_EC08_CTRL_PROTECT_MODE_REG = 0x280003FEull;
+
+static const uint64_t P9N2_PERV_EC09_CTRL_PROTECT_MODE_REG = 0x290003FEull;
+
+static const uint64_t P9N2_PERV_EC10_CTRL_PROTECT_MODE_REG = 0x2A0003FEull;
+
+static const uint64_t P9N2_PERV_EC11_CTRL_PROTECT_MODE_REG = 0x2B0003FEull;
+
+static const uint64_t P9N2_PERV_EC12_CTRL_PROTECT_MODE_REG = 0x2C0003FEull;
+
+static const uint64_t P9N2_PERV_EC13_CTRL_PROTECT_MODE_REG = 0x2D0003FEull;
+
+static const uint64_t P9N2_PERV_EC14_CTRL_PROTECT_MODE_REG = 0x2E0003FEull;
+
+static const uint64_t P9N2_PERV_EC15_CTRL_PROTECT_MODE_REG = 0x2F0003FEull;
+
+static const uint64_t P9N2_PERV_EC16_CTRL_PROTECT_MODE_REG = 0x300003FEull;
+
+static const uint64_t P9N2_PERV_EC17_CTRL_PROTECT_MODE_REG = 0x310003FEull;
+
+static const uint64_t P9N2_PERV_EC18_CTRL_PROTECT_MODE_REG = 0x320003FEull;
+
+static const uint64_t P9N2_PERV_EC19_CTRL_PROTECT_MODE_REG = 0x330003FEull;
+
+static const uint64_t P9N2_PERV_EC20_CTRL_PROTECT_MODE_REG = 0x340003FEull;
+
+static const uint64_t P9N2_PERV_EC21_CTRL_PROTECT_MODE_REG = 0x350003FEull;
+
+static const uint64_t P9N2_PERV_EC22_CTRL_PROTECT_MODE_REG = 0x360003FEull;
+
+static const uint64_t P9N2_PERV_EC23_CTRL_PROTECT_MODE_REG = 0x370003FEull;
+
+
+static const uint32_t P9N2_PERV_FSI2PIB_DATA_REGISTER_0_FSI = 0x00001000ull;
+
+
+static const uint32_t P9N2_PERV_FSI2PIB_DATA_REGISTER_1_FSI = 0x00001001ull;
+
+static const uint32_t P9N2_PERV_FSI2PIB_DATA_REGISTER_1_FSI_BYTE = 0x00001004ull;
+
+
+static const uint64_t P9N2_PERV_DBG_CBS_CC = 0x00030013ull;
+
+static const uint64_t P9N2_PERV_TP_DBG_CBS_CC = 0x01030013ull;
+
+static const uint64_t P9N2_PERV_N0_DBG_CBS_CC = 0x02030013ull;
+
+static const uint64_t P9N2_PERV_N1_DBG_CBS_CC = 0x03030013ull;
+
+static const uint64_t P9N2_PERV_N2_DBG_CBS_CC = 0x04030013ull;
+
+static const uint64_t P9N2_PERV_N3_DBG_CBS_CC = 0x05030013ull;
+
+static const uint64_t P9N2_PERV_XB_DBG_CBS_CC = 0x06030013ull;
+
+static const uint64_t P9N2_PERV_MC01_DBG_CBS_CC = 0x07030013ull;
+
+static const uint64_t P9N2_PERV_MC23_DBG_CBS_CC = 0x08030013ull;
+
+static const uint64_t P9N2_PERV_OB0_DBG_CBS_CC = 0x09030013ull;
+
+static const uint64_t P9N2_PERV_OB3_DBG_CBS_CC = 0x0C030013ull;
+
+static const uint64_t P9N2_PERV_PCI0_DBG_CBS_CC = 0x0D030013ull;
+
+static const uint64_t P9N2_PERV_PCI1_DBG_CBS_CC = 0x0E030013ull;
+
+static const uint64_t P9N2_PERV_PCI2_DBG_CBS_CC = 0x0F030013ull;
+
+static const uint64_t P9N2_PERV_EP00_DBG_CBS_CC = 0x10030013ull;
+
+static const uint64_t P9N2_PERV_EP01_DBG_CBS_CC = 0x11030013ull;
+
+static const uint64_t P9N2_PERV_EP02_DBG_CBS_CC = 0x12030013ull;
+
+static const uint64_t P9N2_PERV_EP03_DBG_CBS_CC = 0x13030013ull;
+
+static const uint64_t P9N2_PERV_EP04_DBG_CBS_CC = 0x14030013ull;
+
+static const uint64_t P9N2_PERV_EP05_DBG_CBS_CC = 0x15030013ull;
+
+static const uint64_t P9N2_PERV_EC00_DBG_CBS_CC = 0x20030013ull;
+
+static const uint64_t P9N2_PERV_EC01_DBG_CBS_CC = 0x21030013ull;
+
+static const uint64_t P9N2_PERV_EC02_DBG_CBS_CC = 0x22030013ull;
+
+static const uint64_t P9N2_PERV_EC03_DBG_CBS_CC = 0x23030013ull;
+
+static const uint64_t P9N2_PERV_EC04_DBG_CBS_CC = 0x24030013ull;
+
+static const uint64_t P9N2_PERV_EC05_DBG_CBS_CC = 0x25030013ull;
+
+static const uint64_t P9N2_PERV_EC06_DBG_CBS_CC = 0x26030013ull;
+
+static const uint64_t P9N2_PERV_EC07_DBG_CBS_CC = 0x27030013ull;
+
+static const uint64_t P9N2_PERV_EC08_DBG_CBS_CC = 0x28030013ull;
+
+static const uint64_t P9N2_PERV_EC09_DBG_CBS_CC = 0x29030013ull;
+
+static const uint64_t P9N2_PERV_EC10_DBG_CBS_CC = 0x2A030013ull;
+
+static const uint64_t P9N2_PERV_EC11_DBG_CBS_CC = 0x2B030013ull;
+
+static const uint64_t P9N2_PERV_EC12_DBG_CBS_CC = 0x2C030013ull;
+
+static const uint64_t P9N2_PERV_EC13_DBG_CBS_CC = 0x2D030013ull;
+
+static const uint64_t P9N2_PERV_EC14_DBG_CBS_CC = 0x2E030013ull;
+
+static const uint64_t P9N2_PERV_EC15_DBG_CBS_CC = 0x2F030013ull;
+
+static const uint64_t P9N2_PERV_EC16_DBG_CBS_CC = 0x30030013ull;
+
+static const uint64_t P9N2_PERV_EC17_DBG_CBS_CC = 0x31030013ull;
+
+static const uint64_t P9N2_PERV_EC18_DBG_CBS_CC = 0x32030013ull;
+
+static const uint64_t P9N2_PERV_EC19_DBG_CBS_CC = 0x33030013ull;
+
+static const uint64_t P9N2_PERV_EC20_DBG_CBS_CC = 0x34030013ull;
+
+static const uint64_t P9N2_PERV_EC21_DBG_CBS_CC = 0x35030013ull;
+
+static const uint64_t P9N2_PERV_EC22_DBG_CBS_CC = 0x36030013ull;
+
+static const uint64_t P9N2_PERV_EC23_DBG_CBS_CC = 0x37030013ull;
+
+
+static const uint64_t P9N2_PERV_DBG_INST1_COND_REG_1 = 0x000107C1ull;
+
+static const uint64_t P9N2_PERV_TP_DBG_INST1_COND_REG_1 = 0x010107C1ull;
+
+
+static const uint64_t P9N2_PERV_DBG_INST1_COND_REG_2 = 0x000107C2ull;
+
+static const uint64_t P9N2_PERV_TP_DBG_INST1_COND_REG_2 = 0x010107C2ull;
+
+
+static const uint64_t P9N2_PERV_DBG_INST1_COND_REG_3 = 0x000107C3ull;
+
+static const uint64_t P9N2_PERV_TP_DBG_INST1_COND_REG_3 = 0x010107C3ull;
+
+
+static const uint64_t P9N2_PERV_DBG_INST2_COND_REG_1 = 0x000107C4ull;
+
+static const uint64_t P9N2_PERV_TP_DBG_INST2_COND_REG_1 = 0x010107C4ull;
+
+
+static const uint64_t P9N2_PERV_DBG_INST2_COND_REG_2 = 0x000107C5ull;
+
+static const uint64_t P9N2_PERV_TP_DBG_INST2_COND_REG_2 = 0x010107C5ull;
+
+
+static const uint64_t P9N2_PERV_DBG_INST2_COND_REG_3 = 0x000107C6ull;
+
+static const uint64_t P9N2_PERV_TP_DBG_INST2_COND_REG_3 = 0x010107C6ull;
+
+
+static const uint64_t P9N2_PERV_DBG_MODE_REG = 0x000107C0ull;
+
+static const uint64_t P9N2_PERV_TP_DBG_MODE_REG = 0x010107C0ull;
+
+
+static const uint64_t P9N2_PERV_DBG_TRACE_MODE_REG_2 = 0x000107CFull;
+
+static const uint64_t P9N2_PERV_TP_DBG_TRACE_MODE_REG_2 = 0x010107CFull;
+
+
+static const uint64_t P9N2_PERV_DBG_TRACE_REG_0 = 0x000107CDull;
+
+static const uint64_t P9N2_PERV_TP_DBG_TRACE_REG_0 = 0x010107CDull;
+
+
+static const uint64_t P9N2_PERV_DBG_TRACE_REG_1 = 0x000107CEull;
+
+static const uint64_t P9N2_PERV_TP_DBG_TRACE_REG_1 = 0x010107CEull;
+
+
+static const uint64_t P9N2_PERV_DEBUG_TRACE_CONTROL = 0x000107D0ull;
+
+static const uint64_t P9N2_PERV_TP_DEBUG_TRACE_CONTROL = 0x010107D0ull;
+
+
+static const uint64_t P9N2_PERV_DEVICE_ID_REG = 0x000F000Full;
+
+static const uint64_t P9N2_PERV_PIB_DEVICE_ID_REG = 0x000F000Full;
+
+
+static const uint32_t P9N2_PERV_FSISHIFT_DMA_ERROR_PTR_REGISTER_FSI = 0x00000C21ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_DMA_ERROR_PTR_REGISTER_FSI_BYTE = 0x00000C84ull;
+
+
+static const uint32_t P9N2_PERV_FSISHIFT_DMA_MODE_REGISTER_FSI = 0x00000C19ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_DMA_MODE_REGISTER_FSI_BYTE = 0x00000C64ull;
+
+
+static const uint32_t P9N2_PERV_FSISHIFT_DMA_OP_BLOCKSIZE_REGISTER_FSI = 0x00000C1Bull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_DMA_OP_BLOCKSIZE_REGISTER_FSI_BYTE = 0x00000C6Cull;
+
+
+static const uint32_t P9N2_PERV_FSISHIFT_DMA_PIB_RCV_BUFFER0_REGISTER_FSI = 0x00000C1Full;
+
+static const uint32_t P9N2_PERV_FSISHIFT_DMA_PIB_RCV_BUFFER0_REGISTER_FSI_BYTE = 0x00000C7Cull;
+
+
+static const uint32_t P9N2_PERV_FSISHIFT_DMA_PIB_RCV_BUFFER1_REGISTER_FSI = 0x00000C20ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_DMA_PIB_RCV_BUFFER1_REGISTER_FSI_BYTE = 0x00000C80ull;
+
+
+static const uint32_t P9N2_PERV_FSISHIFT_DMA_PIB_SND_BUFFER0_REGISTER_FSI = 0x00000C1Dull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_DMA_PIB_SND_BUFFER0_REGISTER_FSI_BYTE = 0x00000C74ull;
+
+
+static const uint32_t P9N2_PERV_FSISHIFT_DMA_PIB_SND_BUFFER1_REGISTER_FSI = 0x00000C1Eull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_DMA_PIB_SND_BUFFER1_REGISTER_FSI_BYTE = 0x00000C78ull;
+
+
+static const uint32_t P9N2_PERV_FSISHIFT_DMA_REM_SIZE_REGISTER_FSI = 0x00000C1Cull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_DMA_REM_SIZE_REGISTER_FSI_BYTE = 0x00000C70ull;
+
+
+static const uint32_t P9N2_PERV_FSISHIFT_DMA_SCOM_CMD_REGISTER_FSI = 0x00000C22ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_DMA_SCOM_CMD_REGISTER_FSI_BYTE = 0x00000C88ull;
+
+
+static const uint32_t P9N2_PERV_FSISHIFT_DMA_STAT_COMP_MASK_REGISTER_FSI = 0x00000C1Aull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_DMA_STAT_COMP_MASK_REGISTER_FSI_BYTE = 0x00000C68ull;
+
+
+static const uint32_t P9N2_PERV_DOORBELL_STATUS_CONTROL_1A_FSI = 0x00002824ull;
+
+static const uint32_t P9N2_PERV_DOORBELL_STATUS_CONTROL_1A_FSI_BYTE = 0x00002890ull;
+
+static const uint64_t P9N2_PERV_DOORBELL_STATUS_CONTROL_1A_SCOM = 0x00050020ull;
+
+static const uint64_t P9N2_PERV_PIB_DOORBELL_STATUS_CONTROL_1A = 0x00050020ull;
+
+
+static const uint32_t P9N2_PERV_DOORBELL_STATUS_CONTROL_2A_FSI = 0x0000282Cull;
+
+static const uint32_t P9N2_PERV_DOORBELL_STATUS_CONTROL_2A_FSI_BYTE = 0x000028B0ull;
+
+static const uint64_t P9N2_PERV_DOORBELL_STATUS_CONTROL_2A_SCOM = 0x00050028ull;
+
+static const uint64_t P9N2_PERV_PIB_DOORBELL_STATUS_CONTROL_2A = 0x00050028ull;
+
+
+static const uint64_t P9N2_PERV_DTS_RESULT0 = 0x00050000ull;
+
+static const uint64_t P9N2_PERV_TP_DTS_RESULT0 = 0x01050000ull;
+
+static const uint64_t P9N2_PERV_N0_DTS_RESULT0 = 0x02050000ull;
+
+static const uint64_t P9N2_PERV_N1_DTS_RESULT0 = 0x03050000ull;
+
+static const uint64_t P9N2_PERV_N2_DTS_RESULT0 = 0x04050000ull;
+
+static const uint64_t P9N2_PERV_N3_DTS_RESULT0 = 0x05050000ull;
+
+static const uint64_t P9N2_PERV_XB_DTS_RESULT0 = 0x06050000ull;
+
+static const uint64_t P9N2_PERV_MC01_DTS_RESULT0 = 0x07050000ull;
+
+static const uint64_t P9N2_PERV_MC23_DTS_RESULT0 = 0x08050000ull;
+
+static const uint64_t P9N2_PERV_OB0_DTS_RESULT0 = 0x09050000ull;
+
+static const uint64_t P9N2_PERV_OB3_DTS_RESULT0 = 0x0C050000ull;
+
+static const uint64_t P9N2_PERV_PCI0_DTS_RESULT0 = 0x0D050000ull;
+
+static const uint64_t P9N2_PERV_PCI1_DTS_RESULT0 = 0x0E050000ull;
+
+static const uint64_t P9N2_PERV_PCI2_DTS_RESULT0 = 0x0F050000ull;
+
+static const uint64_t P9N2_PERV_EP00_DTS_RESULT0 = 0x10050000ull;
+
+static const uint64_t P9N2_PERV_EP01_DTS_RESULT0 = 0x11050000ull;
+
+static const uint64_t P9N2_PERV_EP02_DTS_RESULT0 = 0x12050000ull;
+
+static const uint64_t P9N2_PERV_EP03_DTS_RESULT0 = 0x13050000ull;
+
+static const uint64_t P9N2_PERV_EP04_DTS_RESULT0 = 0x14050000ull;
+
+static const uint64_t P9N2_PERV_EP05_DTS_RESULT0 = 0x15050000ull;
+
+static const uint64_t P9N2_PERV_EC00_DTS_RESULT0 = 0x20050000ull;
+
+static const uint64_t P9N2_PERV_EC01_DTS_RESULT0 = 0x21050000ull;
+
+static const uint64_t P9N2_PERV_EC02_DTS_RESULT0 = 0x22050000ull;
+
+static const uint64_t P9N2_PERV_EC03_DTS_RESULT0 = 0x23050000ull;
+
+static const uint64_t P9N2_PERV_EC04_DTS_RESULT0 = 0x24050000ull;
+
+static const uint64_t P9N2_PERV_EC05_DTS_RESULT0 = 0x25050000ull;
+
+static const uint64_t P9N2_PERV_EC06_DTS_RESULT0 = 0x26050000ull;
+
+static const uint64_t P9N2_PERV_EC07_DTS_RESULT0 = 0x27050000ull;
+
+static const uint64_t P9N2_PERV_EC08_DTS_RESULT0 = 0x28050000ull;
+
+static const uint64_t P9N2_PERV_EC09_DTS_RESULT0 = 0x29050000ull;
+
+static const uint64_t P9N2_PERV_EC10_DTS_RESULT0 = 0x2A050000ull;
+
+static const uint64_t P9N2_PERV_EC11_DTS_RESULT0 = 0x2B050000ull;
+
+static const uint64_t P9N2_PERV_EC12_DTS_RESULT0 = 0x2C050000ull;
+
+static const uint64_t P9N2_PERV_EC13_DTS_RESULT0 = 0x2D050000ull;
+
+static const uint64_t P9N2_PERV_EC14_DTS_RESULT0 = 0x2E050000ull;
+
+static const uint64_t P9N2_PERV_EC15_DTS_RESULT0 = 0x2F050000ull;
+
+static const uint64_t P9N2_PERV_EC16_DTS_RESULT0 = 0x30050000ull;
+
+static const uint64_t P9N2_PERV_EC17_DTS_RESULT0 = 0x31050000ull;
+
+static const uint64_t P9N2_PERV_EC18_DTS_RESULT0 = 0x32050000ull;
+
+static const uint64_t P9N2_PERV_EC19_DTS_RESULT0 = 0x33050000ull;
+
+static const uint64_t P9N2_PERV_EC20_DTS_RESULT0 = 0x34050000ull;
+
+static const uint64_t P9N2_PERV_EC21_DTS_RESULT0 = 0x35050000ull;
+
+static const uint64_t P9N2_PERV_EC22_DTS_RESULT0 = 0x36050000ull;
+
+static const uint64_t P9N2_PERV_EC23_DTS_RESULT0 = 0x37050000ull;
+
+
+static const uint64_t P9N2_PERV_DTS_TRC_RESULT = 0x00050003ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_PERV_TP_DTS_TRC_RESULT = 0x01050003ull;
+
+static const uint64_t P9N2_PERV_N0_DTS_TRC_RESULT = 0x02050003ull;
+
+static const uint64_t P9N2_PERV_N1_DTS_TRC_RESULT = 0x03050003ull;
+
+static const uint64_t P9N2_PERV_N2_DTS_TRC_RESULT = 0x04050003ull;
+
+static const uint64_t P9N2_PERV_N3_DTS_TRC_RESULT = 0x05050003ull;
+
+static const uint64_t P9N2_PERV_XB_DTS_TRC_RESULT = 0x06050003ull;
+
+static const uint64_t P9N2_PERV_MC01_DTS_TRC_RESULT = 0x07050003ull;
+
+static const uint64_t P9N2_PERV_MC23_DTS_TRC_RESULT = 0x08050003ull;
+
+static const uint64_t P9N2_PERV_OB0_DTS_TRC_RESULT = 0x09050003ull;
+
+static const uint64_t P9N2_PERV_OB3_DTS_TRC_RESULT = 0x0C050003ull;
+
+static const uint64_t P9N2_PERV_PCI0_DTS_TRC_RESULT = 0x0D050003ull;
+
+static const uint64_t P9N2_PERV_PCI1_DTS_TRC_RESULT = 0x0E050003ull;
+
+static const uint64_t P9N2_PERV_PCI2_DTS_TRC_RESULT = 0x0F050003ull;
+
+static const uint64_t P9N2_PERV_EP00_DTS_TRC_RESULT = 0x10050003ull;
+
+static const uint64_t P9N2_PERV_EP01_DTS_TRC_RESULT = 0x11050003ull;
+
+static const uint64_t P9N2_PERV_EP02_DTS_TRC_RESULT = 0x12050003ull;
+
+static const uint64_t P9N2_PERV_EP03_DTS_TRC_RESULT = 0x13050003ull;
+
+static const uint64_t P9N2_PERV_EP04_DTS_TRC_RESULT = 0x14050003ull;
+
+static const uint64_t P9N2_PERV_EP05_DTS_TRC_RESULT = 0x15050003ull;
+
+static const uint64_t P9N2_PERV_EC00_DTS_TRC_RESULT = 0x20050003ull;
+
+static const uint64_t P9N2_PERV_EC01_DTS_TRC_RESULT = 0x21050003ull;
+
+static const uint64_t P9N2_PERV_EC02_DTS_TRC_RESULT = 0x22050003ull;
+
+static const uint64_t P9N2_PERV_EC03_DTS_TRC_RESULT = 0x23050003ull;
+
+static const uint64_t P9N2_PERV_EC04_DTS_TRC_RESULT = 0x24050003ull;
+
+static const uint64_t P9N2_PERV_EC05_DTS_TRC_RESULT = 0x25050003ull;
+
+static const uint64_t P9N2_PERV_EC06_DTS_TRC_RESULT = 0x26050003ull;
+
+static const uint64_t P9N2_PERV_EC07_DTS_TRC_RESULT = 0x27050003ull;
+
+static const uint64_t P9N2_PERV_EC08_DTS_TRC_RESULT = 0x28050003ull;
+
+static const uint64_t P9N2_PERV_EC09_DTS_TRC_RESULT = 0x29050003ull;
+
+static const uint64_t P9N2_PERV_EC10_DTS_TRC_RESULT = 0x2A050003ull;
+
+static const uint64_t P9N2_PERV_EC11_DTS_TRC_RESULT = 0x2B050003ull;
+
+static const uint64_t P9N2_PERV_EC12_DTS_TRC_RESULT = 0x2C050003ull;
+
+static const uint64_t P9N2_PERV_EC13_DTS_TRC_RESULT = 0x2D050003ull;
+
+static const uint64_t P9N2_PERV_EC14_DTS_TRC_RESULT = 0x2E050003ull;
+
+static const uint64_t P9N2_PERV_EC15_DTS_TRC_RESULT = 0x2F050003ull;
+
+static const uint64_t P9N2_PERV_EC16_DTS_TRC_RESULT = 0x30050003ull;
+
+static const uint64_t P9N2_PERV_EC17_DTS_TRC_RESULT = 0x31050003ull;
+
+static const uint64_t P9N2_PERV_EC18_DTS_TRC_RESULT = 0x32050003ull;
+
+static const uint64_t P9N2_PERV_EC19_DTS_TRC_RESULT = 0x33050003ull;
+
+static const uint64_t P9N2_PERV_EC20_DTS_TRC_RESULT = 0x34050003ull;
+
+static const uint64_t P9N2_PERV_EC21_DTS_TRC_RESULT = 0x35050003ull;
+
+static const uint64_t P9N2_PERV_EC22_DTS_TRC_RESULT = 0x36050003ull;
+
+static const uint64_t P9N2_PERV_EC23_DTS_TRC_RESULT = 0x37050003ull;
+
+
+static const uint64_t P9N2_PERV_EDRAM_STATUS = 0x000F0029ull;
+
+static const uint64_t P9N2_PERV_TP_EDRAM_STATUS = 0x010F0029ull;
+
+static const uint64_t P9N2_PERV_N0_EDRAM_STATUS = 0x020F0029ull;
+
+static const uint64_t P9N2_PERV_N1_EDRAM_STATUS = 0x030F0029ull;
+
+static const uint64_t P9N2_PERV_N2_EDRAM_STATUS = 0x040F0029ull;
+
+static const uint64_t P9N2_PERV_N3_EDRAM_STATUS = 0x050F0029ull;
+
+static const uint64_t P9N2_PERV_XB_EDRAM_STATUS = 0x060F0029ull;
+
+static const uint64_t P9N2_PERV_MC01_EDRAM_STATUS = 0x070F0029ull;
+
+static const uint64_t P9N2_PERV_MC23_EDRAM_STATUS = 0x080F0029ull;
+
+static const uint64_t P9N2_PERV_OB0_EDRAM_STATUS = 0x090F0029ull;
+
+static const uint64_t P9N2_PERV_OB3_EDRAM_STATUS = 0x0C0F0029ull;
+
+static const uint64_t P9N2_PERV_PCI0_EDRAM_STATUS = 0x0D0F0029ull;
+
+static const uint64_t P9N2_PERV_PCI1_EDRAM_STATUS = 0x0E0F0029ull;
+
+static const uint64_t P9N2_PERV_PCI2_EDRAM_STATUS = 0x0F0F0029ull;
+
+static const uint64_t P9N2_PERV_EP00_EDRAM_STATUS = 0x100F0029ull;
+
+static const uint64_t P9N2_PERV_EP01_EDRAM_STATUS = 0x110F0029ull;
+
+static const uint64_t P9N2_PERV_EP02_EDRAM_STATUS = 0x120F0029ull;
+
+static const uint64_t P9N2_PERV_EP03_EDRAM_STATUS = 0x130F0029ull;
+
+static const uint64_t P9N2_PERV_EP04_EDRAM_STATUS = 0x140F0029ull;
+
+static const uint64_t P9N2_PERV_EP05_EDRAM_STATUS = 0x150F0029ull;
+
+static const uint64_t P9N2_PERV_EC00_EDRAM_STATUS = 0x200F0029ull;
+
+static const uint64_t P9N2_PERV_EC01_EDRAM_STATUS = 0x210F0029ull;
+
+static const uint64_t P9N2_PERV_EC02_EDRAM_STATUS = 0x220F0029ull;
+
+static const uint64_t P9N2_PERV_EC03_EDRAM_STATUS = 0x230F0029ull;
+
+static const uint64_t P9N2_PERV_EC04_EDRAM_STATUS = 0x240F0029ull;
+
+static const uint64_t P9N2_PERV_EC05_EDRAM_STATUS = 0x250F0029ull;
+
+static const uint64_t P9N2_PERV_EC06_EDRAM_STATUS = 0x260F0029ull;
+
+static const uint64_t P9N2_PERV_EC07_EDRAM_STATUS = 0x270F0029ull;
+
+static const uint64_t P9N2_PERV_EC08_EDRAM_STATUS = 0x280F0029ull;
+
+static const uint64_t P9N2_PERV_EC09_EDRAM_STATUS = 0x290F0029ull;
+
+static const uint64_t P9N2_PERV_EC10_EDRAM_STATUS = 0x2A0F0029ull;
+
+static const uint64_t P9N2_PERV_EC11_EDRAM_STATUS = 0x2B0F0029ull;
+
+static const uint64_t P9N2_PERV_EC12_EDRAM_STATUS = 0x2C0F0029ull;
+
+static const uint64_t P9N2_PERV_EC13_EDRAM_STATUS = 0x2D0F0029ull;
+
+static const uint64_t P9N2_PERV_EC14_EDRAM_STATUS = 0x2E0F0029ull;
+
+static const uint64_t P9N2_PERV_EC15_EDRAM_STATUS = 0x2F0F0029ull;
+
+static const uint64_t P9N2_PERV_EC16_EDRAM_STATUS = 0x300F0029ull;
+
+static const uint64_t P9N2_PERV_EC17_EDRAM_STATUS = 0x310F0029ull;
+
+static const uint64_t P9N2_PERV_EC18_EDRAM_STATUS = 0x320F0029ull;
+
+static const uint64_t P9N2_PERV_EC19_EDRAM_STATUS = 0x330F0029ull;
+
+static const uint64_t P9N2_PERV_EC20_EDRAM_STATUS = 0x340F0029ull;
+
+static const uint64_t P9N2_PERV_EC21_EDRAM_STATUS = 0x350F0029ull;
+
+static const uint64_t P9N2_PERV_EC22_EDRAM_STATUS = 0x360F0029ull;
+
+static const uint64_t P9N2_PERV_EC23_EDRAM_STATUS = 0x370F0029ull;
+
+
+static const uint64_t P9N2_PERV_ERROR_REG = 0x000F001Full;
+
+static const uint64_t P9N2_PERV_PIB_ERROR_REG = 0x000F001Full;
+
+static const uint64_t P9N2_PERV_TP_ERROR_REG = 0x010F001Full;
+
+static const uint64_t P9N2_PERV_N0_ERROR_REG = 0x020F001Full;
+
+static const uint64_t P9N2_PERV_N1_ERROR_REG = 0x030F001Full;
+
+static const uint64_t P9N2_PERV_N2_ERROR_REG = 0x040F001Full;
+
+static const uint64_t P9N2_PERV_N3_ERROR_REG = 0x050F001Full;
+
+static const uint64_t P9N2_PERV_XB_ERROR_REG = 0x060F001Full;
+
+static const uint64_t P9N2_PERV_MC01_ERROR_REG = 0x070F001Full;
+
+static const uint64_t P9N2_PERV_MC23_ERROR_REG = 0x080F001Full;
+
+static const uint64_t P9N2_PERV_OB0_ERROR_REG = 0x090F001Full;
+
+static const uint64_t P9N2_PERV_OB3_ERROR_REG = 0x0C0F001Full;
+
+static const uint64_t P9N2_PERV_PCI0_ERROR_REG = 0x0D0F001Full;
+
+static const uint64_t P9N2_PERV_PCI1_ERROR_REG = 0x0E0F001Full;
+
+static const uint64_t P9N2_PERV_PCI2_ERROR_REG = 0x0F0F001Full;
+
+static const uint64_t P9N2_PERV_EP00_ERROR_REG = 0x100F001Full;
+
+static const uint64_t P9N2_PERV_EP01_ERROR_REG = 0x110F001Full;
+
+static const uint64_t P9N2_PERV_EP02_ERROR_REG = 0x120F001Full;
+
+static const uint64_t P9N2_PERV_EP03_ERROR_REG = 0x130F001Full;
+
+static const uint64_t P9N2_PERV_EP04_ERROR_REG = 0x140F001Full;
+
+static const uint64_t P9N2_PERV_EP05_ERROR_REG = 0x150F001Full;
+
+static const uint64_t P9N2_PERV_EC00_ERROR_REG = 0x200F001Full;
+
+static const uint64_t P9N2_PERV_EC01_ERROR_REG = 0x210F001Full;
+
+static const uint64_t P9N2_PERV_EC02_ERROR_REG = 0x220F001Full;
+
+static const uint64_t P9N2_PERV_EC03_ERROR_REG = 0x230F001Full;
+
+static const uint64_t P9N2_PERV_EC04_ERROR_REG = 0x240F001Full;
+
+static const uint64_t P9N2_PERV_EC05_ERROR_REG = 0x250F001Full;
+
+static const uint64_t P9N2_PERV_EC06_ERROR_REG = 0x260F001Full;
+
+static const uint64_t P9N2_PERV_EC07_ERROR_REG = 0x270F001Full;
+
+static const uint64_t P9N2_PERV_EC08_ERROR_REG = 0x280F001Full;
+
+static const uint64_t P9N2_PERV_EC09_ERROR_REG = 0x290F001Full;
+
+static const uint64_t P9N2_PERV_EC10_ERROR_REG = 0x2A0F001Full;
+
+static const uint64_t P9N2_PERV_EC11_ERROR_REG = 0x2B0F001Full;
+
+static const uint64_t P9N2_PERV_EC12_ERROR_REG = 0x2C0F001Full;
+
+static const uint64_t P9N2_PERV_EC13_ERROR_REG = 0x2D0F001Full;
+
+static const uint64_t P9N2_PERV_EC14_ERROR_REG = 0x2E0F001Full;
+
+static const uint64_t P9N2_PERV_EC15_ERROR_REG = 0x2F0F001Full;
+
+static const uint64_t P9N2_PERV_EC16_ERROR_REG = 0x300F001Full;
+
+static const uint64_t P9N2_PERV_EC17_ERROR_REG = 0x310F001Full;
+
+static const uint64_t P9N2_PERV_EC18_ERROR_REG = 0x320F001Full;
+
+static const uint64_t P9N2_PERV_EC19_ERROR_REG = 0x330F001Full;
+
+static const uint64_t P9N2_PERV_EC20_ERROR_REG = 0x340F001Full;
+
+static const uint64_t P9N2_PERV_EC21_ERROR_REG = 0x350F001Full;
+
+static const uint64_t P9N2_PERV_EC22_ERROR_REG = 0x360F001Full;
+
+static const uint64_t P9N2_PERV_EC23_ERROR_REG = 0x370F001Full;
+
+
+static const uint64_t P9N2_PERV_ERROR_STATUS = 0x0003000Full;
+
+static const uint64_t P9N2_PERV_TP_ERROR_STATUS = 0x0103000Full;
+
+static const uint64_t P9N2_PERV_N0_ERROR_STATUS = 0x0203000Full;
+
+static const uint64_t P9N2_PERV_N1_ERROR_STATUS = 0x0303000Full;
+
+static const uint64_t P9N2_PERV_N2_ERROR_STATUS = 0x0403000Full;
+
+static const uint64_t P9N2_PERV_N3_ERROR_STATUS = 0x0503000Full;
+
+static const uint64_t P9N2_PERV_XB_ERROR_STATUS = 0x0603000Full;
+
+static const uint64_t P9N2_PERV_MC01_ERROR_STATUS = 0x0703000Full;
+
+static const uint64_t P9N2_PERV_MC23_ERROR_STATUS = 0x0803000Full;
+
+static const uint64_t P9N2_PERV_OB0_ERROR_STATUS = 0x0903000Full;
+
+static const uint64_t P9N2_PERV_OB3_ERROR_STATUS = 0x0C03000Full;
+
+static const uint64_t P9N2_PERV_PCI0_ERROR_STATUS = 0x0D03000Full;
+
+static const uint64_t P9N2_PERV_PCI1_ERROR_STATUS = 0x0E03000Full;
+
+static const uint64_t P9N2_PERV_PCI2_ERROR_STATUS = 0x0F03000Full;
+
+static const uint64_t P9N2_PERV_EP00_ERROR_STATUS = 0x1003000Full;
+
+static const uint64_t P9N2_PERV_EP01_ERROR_STATUS = 0x1103000Full;
+
+static const uint64_t P9N2_PERV_EP02_ERROR_STATUS = 0x1203000Full;
+
+static const uint64_t P9N2_PERV_EP03_ERROR_STATUS = 0x1303000Full;
+
+static const uint64_t P9N2_PERV_EP04_ERROR_STATUS = 0x1403000Full;
+
+static const uint64_t P9N2_PERV_EP05_ERROR_STATUS = 0x1503000Full;
+
+static const uint64_t P9N2_PERV_EC00_ERROR_STATUS = 0x2003000Full;
+
+static const uint64_t P9N2_PERV_EC01_ERROR_STATUS = 0x2103000Full;
+
+static const uint64_t P9N2_PERV_EC02_ERROR_STATUS = 0x2203000Full;
+
+static const uint64_t P9N2_PERV_EC03_ERROR_STATUS = 0x2303000Full;
+
+static const uint64_t P9N2_PERV_EC04_ERROR_STATUS = 0x2403000Full;
+
+static const uint64_t P9N2_PERV_EC05_ERROR_STATUS = 0x2503000Full;
+
+static const uint64_t P9N2_PERV_EC06_ERROR_STATUS = 0x2603000Full;
+
+static const uint64_t P9N2_PERV_EC07_ERROR_STATUS = 0x2703000Full;
+
+static const uint64_t P9N2_PERV_EC08_ERROR_STATUS = 0x2803000Full;
+
+static const uint64_t P9N2_PERV_EC09_ERROR_STATUS = 0x2903000Full;
+
+static const uint64_t P9N2_PERV_EC10_ERROR_STATUS = 0x2A03000Full;
+
+static const uint64_t P9N2_PERV_EC11_ERROR_STATUS = 0x2B03000Full;
+
+static const uint64_t P9N2_PERV_EC12_ERROR_STATUS = 0x2C03000Full;
+
+static const uint64_t P9N2_PERV_EC13_ERROR_STATUS = 0x2D03000Full;
+
+static const uint64_t P9N2_PERV_EC14_ERROR_STATUS = 0x2E03000Full;
+
+static const uint64_t P9N2_PERV_EC15_ERROR_STATUS = 0x2F03000Full;
+
+static const uint64_t P9N2_PERV_EC16_ERROR_STATUS = 0x3003000Full;
+
+static const uint64_t P9N2_PERV_EC17_ERROR_STATUS = 0x3103000Full;
+
+static const uint64_t P9N2_PERV_EC18_ERROR_STATUS = 0x3203000Full;
+
+static const uint64_t P9N2_PERV_EC19_ERROR_STATUS = 0x3303000Full;
+
+static const uint64_t P9N2_PERV_EC20_ERROR_STATUS = 0x3403000Full;
+
+static const uint64_t P9N2_PERV_EC21_ERROR_STATUS = 0x3503000Full;
+
+static const uint64_t P9N2_PERV_EC22_ERROR_STATUS = 0x3603000Full;
+
+static const uint64_t P9N2_PERV_EC23_ERROR_STATUS = 0x3703000Full;
+
+
+static const uint64_t P9N2_PERV_ERROR_STATUS_REG = 0x000F0034ull;
+
+static const uint64_t P9N2_PERV_PIB_ERROR_STATUS_REG = 0x000F0034ull;
+
+
+static const uint64_t P9N2_PERV_ERR_STATUS_REG = 0x00050013ull;
+
+static const uint64_t P9N2_PERV_TP_ERR_STATUS_REG = 0x01050013ull;
+
+static const uint64_t P9N2_PERV_N0_ERR_STATUS_REG = 0x02050013ull;
+
+static const uint64_t P9N2_PERV_N1_ERR_STATUS_REG = 0x03050013ull;
+
+static const uint64_t P9N2_PERV_N2_ERR_STATUS_REG = 0x04050013ull;
+
+static const uint64_t P9N2_PERV_N3_ERR_STATUS_REG = 0x05050013ull;
+
+static const uint64_t P9N2_PERV_XB_ERR_STATUS_REG = 0x06050013ull;
+
+static const uint64_t P9N2_PERV_MC01_ERR_STATUS_REG = 0x07050013ull;
+
+static const uint64_t P9N2_PERV_MC23_ERR_STATUS_REG = 0x08050013ull;
+
+static const uint64_t P9N2_PERV_OB0_ERR_STATUS_REG = 0x09050013ull;
+
+static const uint64_t P9N2_PERV_OB3_ERR_STATUS_REG = 0x0C050013ull;
+
+static const uint64_t P9N2_PERV_PCI0_ERR_STATUS_REG = 0x0D050013ull;
+
+static const uint64_t P9N2_PERV_PCI1_ERR_STATUS_REG = 0x0E050013ull;
+
+static const uint64_t P9N2_PERV_PCI2_ERR_STATUS_REG = 0x0F050013ull;
+
+static const uint64_t P9N2_PERV_EP00_ERR_STATUS_REG = 0x10050013ull;
+
+static const uint64_t P9N2_PERV_EP01_ERR_STATUS_REG = 0x11050013ull;
+
+static const uint64_t P9N2_PERV_EP02_ERR_STATUS_REG = 0x12050013ull;
+
+static const uint64_t P9N2_PERV_EP03_ERR_STATUS_REG = 0x13050013ull;
+
+static const uint64_t P9N2_PERV_EP04_ERR_STATUS_REG = 0x14050013ull;
+
+static const uint64_t P9N2_PERV_EP05_ERR_STATUS_REG = 0x15050013ull;
+
+static const uint64_t P9N2_PERV_EC00_ERR_STATUS_REG = 0x20050013ull;
+
+static const uint64_t P9N2_PERV_EC01_ERR_STATUS_REG = 0x21050013ull;
+
+static const uint64_t P9N2_PERV_EC02_ERR_STATUS_REG = 0x22050013ull;
+
+static const uint64_t P9N2_PERV_EC03_ERR_STATUS_REG = 0x23050013ull;
+
+static const uint64_t P9N2_PERV_EC04_ERR_STATUS_REG = 0x24050013ull;
+
+static const uint64_t P9N2_PERV_EC05_ERR_STATUS_REG = 0x25050013ull;
+
+static const uint64_t P9N2_PERV_EC06_ERR_STATUS_REG = 0x26050013ull;
+
+static const uint64_t P9N2_PERV_EC07_ERR_STATUS_REG = 0x27050013ull;
+
+static const uint64_t P9N2_PERV_EC08_ERR_STATUS_REG = 0x28050013ull;
+
+static const uint64_t P9N2_PERV_EC09_ERR_STATUS_REG = 0x29050013ull;
+
+static const uint64_t P9N2_PERV_EC10_ERR_STATUS_REG = 0x2A050013ull;
+
+static const uint64_t P9N2_PERV_EC11_ERR_STATUS_REG = 0x2B050013ull;
+
+static const uint64_t P9N2_PERV_EC12_ERR_STATUS_REG = 0x2C050013ull;
+
+static const uint64_t P9N2_PERV_EC13_ERR_STATUS_REG = 0x2D050013ull;
+
+static const uint64_t P9N2_PERV_EC14_ERR_STATUS_REG = 0x2E050013ull;
+
+static const uint64_t P9N2_PERV_EC15_ERR_STATUS_REG = 0x2F050013ull;
+
+static const uint64_t P9N2_PERV_EC16_ERR_STATUS_REG = 0x30050013ull;
+
+static const uint64_t P9N2_PERV_EC17_ERR_STATUS_REG = 0x31050013ull;
+
+static const uint64_t P9N2_PERV_EC18_ERR_STATUS_REG = 0x32050013ull;
+
+static const uint64_t P9N2_PERV_EC19_ERR_STATUS_REG = 0x33050013ull;
+
+static const uint64_t P9N2_PERV_EC20_ERR_STATUS_REG = 0x34050013ull;
+
+static const uint64_t P9N2_PERV_EC21_ERR_STATUS_REG = 0x35050013ull;
+
+static const uint64_t P9N2_PERV_EC22_ERR_STATUS_REG = 0x36050013ull;
+
+static const uint64_t P9N2_PERV_EC23_ERR_STATUS_REG = 0x37050013ull;
+
+
+static const uint32_t P9N2_PERV_FSISHIFT_EXTENDED_STATUS_FSI = 0x00000C08ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_EXTENDED_STATUS_FSI_BYTE = 0x00000C20ull;
+
+
+static const uint64_t P9N2_PERV_0_FSII2C_EXTENDED_STATUS_A = 0x00001808ull;
+
+static const uint32_t P9N2_PERV_FSII2C_EXTENDED_STATUS_A = 0x00001808ull;
+
+
+static const uint64_t P9N2_PERV_0_FSII2C_FIFO1_REGISTER_READ_A = 0x00001800ull;
+
+static const uint32_t P9N2_PERV_FSII2C_FIFO1_REGISTER_READ_A = 0x00001800ull;
+
+
+static const uint64_t P9N2_PERV_FIRST_ERR_REG = 0x000F001Eull;
+
+static const uint64_t P9N2_PERV_PIB_FIRST_ERR_REG = 0x000F001Eull;
+
+
+static const uint64_t P9N2_PERV_FIRST_REPLY_REG = 0x000F0018ull;
+
+static const uint64_t P9N2_PERV_PIB_FIRST_REPLY_REG = 0x000F0018ull;
+
+
+static const uint64_t P9N2_PERV_FIR_MASK = 0x00040002ull;
+
+static const uint64_t P9N2_PERV_TP_FIR_MASK = 0x01040002ull;
+
+static const uint64_t P9N2_PERV_N0_FIR_MASK = 0x02040002ull;
+
+static const uint64_t P9N2_PERV_N1_FIR_MASK = 0x03040002ull;
+
+static const uint64_t P9N2_PERV_N2_FIR_MASK = 0x04040002ull;
+
+static const uint64_t P9N2_PERV_N3_FIR_MASK = 0x05040002ull;
+
+static const uint64_t P9N2_PERV_XB_FIR_MASK = 0x06040002ull;
+
+static const uint64_t P9N2_PERV_MC01_FIR_MASK = 0x07040002ull;
+
+static const uint64_t P9N2_PERV_MC23_FIR_MASK = 0x08040002ull;
+
+static const uint64_t P9N2_PERV_OB0_FIR_MASK = 0x09040002ull;
+
+static const uint64_t P9N2_PERV_OB3_FIR_MASK = 0x0C040002ull;
+
+static const uint64_t P9N2_PERV_PCI0_FIR_MASK = 0x0D040002ull;
+
+static const uint64_t P9N2_PERV_PCI1_FIR_MASK = 0x0E040002ull;
+
+static const uint64_t P9N2_PERV_PCI2_FIR_MASK = 0x0F040002ull;
+
+static const uint64_t P9N2_PERV_EP00_FIR_MASK = 0x10040002ull;
+
+static const uint64_t P9N2_PERV_EP01_FIR_MASK = 0x11040002ull;
+
+static const uint64_t P9N2_PERV_EP02_FIR_MASK = 0x12040002ull;
+
+static const uint64_t P9N2_PERV_EP03_FIR_MASK = 0x13040002ull;
+
+static const uint64_t P9N2_PERV_EP04_FIR_MASK = 0x14040002ull;
+
+static const uint64_t P9N2_PERV_EP05_FIR_MASK = 0x15040002ull;
+
+static const uint64_t P9N2_PERV_EC00_FIR_MASK = 0x20040002ull;
+
+static const uint64_t P9N2_PERV_EC01_FIR_MASK = 0x21040002ull;
+
+static const uint64_t P9N2_PERV_EC02_FIR_MASK = 0x22040002ull;
+
+static const uint64_t P9N2_PERV_EC03_FIR_MASK = 0x23040002ull;
+
+static const uint64_t P9N2_PERV_EC04_FIR_MASK = 0x24040002ull;
+
+static const uint64_t P9N2_PERV_EC05_FIR_MASK = 0x25040002ull;
+
+static const uint64_t P9N2_PERV_EC06_FIR_MASK = 0x26040002ull;
+
+static const uint64_t P9N2_PERV_EC07_FIR_MASK = 0x27040002ull;
+
+static const uint64_t P9N2_PERV_EC08_FIR_MASK = 0x28040002ull;
+
+static const uint64_t P9N2_PERV_EC09_FIR_MASK = 0x29040002ull;
+
+static const uint64_t P9N2_PERV_EC10_FIR_MASK = 0x2A040002ull;
+
+static const uint64_t P9N2_PERV_EC11_FIR_MASK = 0x2B040002ull;
+
+static const uint64_t P9N2_PERV_EC12_FIR_MASK = 0x2C040002ull;
+
+static const uint64_t P9N2_PERV_EC13_FIR_MASK = 0x2D040002ull;
+
+static const uint64_t P9N2_PERV_EC14_FIR_MASK = 0x2E040002ull;
+
+static const uint64_t P9N2_PERV_EC15_FIR_MASK = 0x2F040002ull;
+
+static const uint64_t P9N2_PERV_EC16_FIR_MASK = 0x30040002ull;
+
+static const uint64_t P9N2_PERV_EC17_FIR_MASK = 0x31040002ull;
+
+static const uint64_t P9N2_PERV_EC18_FIR_MASK = 0x32040002ull;
+
+static const uint64_t P9N2_PERV_EC19_FIR_MASK = 0x33040002ull;
+
+static const uint64_t P9N2_PERV_EC20_FIR_MASK = 0x34040002ull;
+
+static const uint64_t P9N2_PERV_EC21_FIR_MASK = 0x35040002ull;
+
+static const uint64_t P9N2_PERV_EC22_FIR_MASK = 0x36040002ull;
+
+static const uint64_t P9N2_PERV_EC23_FIR_MASK = 0x37040002ull;
+
+
+static const uint64_t P9N2_PERV_FMU_FORCE_OP_REG = 0x00020003ull;
+
+static const uint64_t P9N2_PERV_TP_FMU_FORCE_OP_REG = 0x01020003ull;
+
+
+static const uint64_t P9N2_PERV_FMU_KVREF_DATAREG = 0x00020004ull;
+
+static const uint64_t P9N2_PERV_TP_FMU_KVREF_DATAREG = 0x01020004ull;
+
+
+static const uint64_t P9N2_PERV_FMU_MODE_REG = 0x00020000ull;
+
+static const uint64_t P9N2_PERV_TP_FMU_MODE_REG = 0x01020000ull;
+
+
+static const uint64_t P9N2_PERV_FMU_OSC_CNTR1_REG = 0x00020001ull;
+
+static const uint64_t P9N2_PERV_TP_FMU_OSC_CNTR1_REG = 0x01020001ull;
+
+
+static const uint64_t P9N2_PERV_FMU_OSC_CNTR2_REG = 0x00020002ull;
+
+static const uint64_t P9N2_PERV_TP_FMU_OSC_CNTR2_REG = 0x01020002ull;
+
+
+static const uint64_t P9N2_PERV_FMU_PULSE_GEN_REG = 0x00020001ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_PERV_TP_FMU_PULSE_GEN_REG = 0x01020001ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+
+static const uint64_t P9N2_PERV_FMU_VMEAS_MAX_RESULT = 0x00020008ull;
+
+static const uint64_t P9N2_PERV_TP_FMU_VMEAS_MAX_RESULT = 0x01020008ull;
+
+
+static const uint64_t P9N2_PERV_FMU_VMEAS_MIN_RESULT = 0x00020009ull;
+
+static const uint64_t P9N2_PERV_TP_FMU_VMEAS_MIN_RESULT = 0x01020009ull;
+
+
+static const uint32_t P9N2_PERV_FSISHIFT_FRONT_END_LENGTH_REGISTER_FSI = 0x00000C02ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FRONT_END_LENGTH_REGISTER_FSI_BYTE = 0x00000C08ull;
+
+
+static const uint32_t P9N2_PERV_FSB_FSB_DNFIFO_DATA_OUT_FSI = 0x00002410ull;
+
+static const uint32_t P9N2_PERV_FSB_FSB_DNFIFO_DATA_OUT_FSI_BYTE = 0x00002440ull;
+
+
+static const uint32_t P9N2_PERV_FSB_FSB_DOWNFIFO_ACK_EOT_FSI = 0x00002415ull;
+
+static const uint32_t P9N2_PERV_FSB_FSB_DOWNFIFO_ACK_EOT_FSI_BYTE = 0x00002454ull;
+
+
+static const uint32_t P9N2_PERV_FSB_FSB_DOWNFIFO_MTC_FSI = 0x00002416ull;
+
+static const uint32_t P9N2_PERV_FSB_FSB_DOWNFIFO_MTC_FSI_BYTE = 0x00002458ull;
+
+
+static const uint32_t P9N2_PERV_FSB_FSB_DOWNFIFO_RESET_FSI = 0x00002414ull;
+
+static const uint32_t P9N2_PERV_FSB_FSB_DOWNFIFO_RESET_FSI_BYTE = 0x00002450ull;
+
+
+static const uint32_t P9N2_PERV_FSB_FSB_DOWNFIFO_STATUS_FSI = 0x00002411ull;
+
+static const uint32_t P9N2_PERV_FSB_FSB_DOWNFIFO_STATUS_FSI_BYTE = 0x00002444ull;
+
+
+static const uint32_t P9N2_PERV_FSB_FSB_UPFIFO_DATA_IN_FSI = 0x00002400ull;
+
+
+static const uint32_t P9N2_PERV_FSB_FSB_UPFIFO_REQ_RESET_FSI = 0x00002403ull;
+
+static const uint32_t P9N2_PERV_FSB_FSB_UPFIFO_REQ_RESET_FSI_BYTE = 0x0000240Cull;
+
+
+static const uint32_t P9N2_PERV_FSB_FSB_UPFIFO_SIG_EOT_FSI = 0x00002402ull;
+
+static const uint32_t P9N2_PERV_FSB_FSB_UPFIFO_SIG_EOT_FSI_BYTE = 0x00002408ull;
+
+
+static const uint32_t P9N2_PERV_FSB_FSB_UPFIFO_STATUS_FSI = 0x00002401ull;
+
+static const uint32_t P9N2_PERV_FSB_FSB_UPFIFO_STATUS_FSI_BYTE = 0x00002404ull;
+
+
+static const uint32_t P9N2_PERV_FSISCRPD1_FSI = 0x00001401ull;
+
+static const uint32_t P9N2_PERV_FSISCRPD1_FSI_BYTE = 0x00001404ull;
+
+
+static const uint32_t P9N2_PERV_FSISCRPD2_FSI = 0x00001402ull;
+
+static const uint32_t P9N2_PERV_FSISCRPD2_FSI_BYTE = 0x00001408ull;
+
+
+static const uint32_t P9N2_PERV_FSISCRPD3_FSI = 0x00001403ull;
+
+static const uint32_t P9N2_PERV_FSISCRPD3_FSI_BYTE = 0x0000140Cull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_LLMOD_FSI0 = 0x00000900ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_LLSTAT_FSI0 = 0x00000904ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_0_MAEB_FSI0 = 0x00003070ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MAEB = 0x00000C1Cull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_0_MAESP0_FSI0 = 0x00003050ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MAESP0 = 0x00000C14ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_0_MAESP1_FSI0 = 0x00003054ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MAESP1 = 0x00000C15ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_0_MAESP2_FSI0 = 0x00003058ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MAESP2 = 0x00000C16ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_0_MAESP3_FSI0 = 0x0000305Cull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MAESP3 = 0x00000C17ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_0_MAESP4_FSI0 = 0x00003060ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MAESP4 = 0x00000C18ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_0_MAESP5_FSI0 = 0x00003064ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MAESP5 = 0x00000C19ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_0_MAESP6_FSI0 = 0x00003068ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MAESP6 = 0x00000C1Aull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_0_MAESP7_FSI0 = 0x0000306Cull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MAESP7 = 0x00000C1Bull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_0_MATRB0_FSI0 = 0x000031D8ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MATRB0 = 0x00000C76ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_0_MCENP0_FSI0 = 0x00003020ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MCENP0 = 0x00000C08ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_0_MCRSP0_FSI0 = 0x00003008ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MCRSP0 = 0x00000C02ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_0_MCRSP1_FSI0 = 0x0000300Cull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MCRSP1 = 0x00000C03ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_0_MCSIEP0_FSI0 = 0x00003070ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MCSIEP0 = 0x00000C1Cull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_0_MDLYR_FSI0 = 0x00003004ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MDLYR = 0x00000C01ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_0_MDTRB0_FSI0 = 0x000031DCull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MDTRB0 = 0x00000C77ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_0_MECTRL_FSI0 = 0x000032E0ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MECTRL = 0x00000CB8ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_0_MENP0_FSI0 = 0x00003010ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MENP0 = 0x00000C04ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_0_MENP1_FSI0 = 0x00003014ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MENP1 = 0x00000C05ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_0_MESRB0_FSI0 = 0x000031D0ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MESRB0 = 0x00000C74ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_0_MLEVP0_FSI0 = 0x00003018ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MLEVP0 = 0x00000C06ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_0_MLEVP1_FSI0 = 0x0000301Cull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MLEVP1 = 0x00000C07ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_0_MMODE_FSI0 = 0x00003000ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MMODE = 0x00000C00ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_0_MREFP0_FSI0 = 0x00003020ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MREFP0 = 0x00000C08ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_0_MREFP1_FSI0 = 0x00003024ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MREFP1 = 0x00000C09ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_0_MRESB0_FSI0 = 0x000031D0ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MRESB0 = 0x00000C74ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+
+static const uint32_t P9N2_PERV_FSI_A_MST_0_MRESP0_FSI0 = 0x000030D0ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MRESP0 = 0x00000C34ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_0_MRESP1_FSI0 = 0x000030D4ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MRESP1 = 0x00000C35ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_0_MRESP2_FSI0 = 0x000030D8ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MRESP2 = 0x00000C36ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_0_MRESP3_FSI0 = 0x000030DCull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MRESP3 = 0x00000C37ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_0_MRESP4_FSI0 = 0x000030E0ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MRESP4 = 0x00000C38ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_0_MRESP5_FSI0 = 0x000030E4ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MRESP5 = 0x00000C39ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_0_MRESP6_FSI0 = 0x000030E8ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MRESP6 = 0x00000C3Aull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_0_MRESP7_FSI0 = 0x000030ECull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MRESP7 = 0x00000C3Bull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_0_MSCSB0_FSI0 = 0x000031D4ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSCSB0 = 0x00000C75ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_0_MSENP0_FSI0 = 0x00003018ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSENP0 = 0x00000C06ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_0_MSIEP0_FSI0 = 0x00003030ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSIEP0 = 0x00000C0Cull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_0_MSIEP1_FSI0 = 0x00003034ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSIEP1 = 0x00000C0Dull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_0_MSIEP2_FSI0 = 0x00003038ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSIEP2 = 0x00000C0Eull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_0_MSIEP3_FSI0 = 0x0000303Cull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSIEP3 = 0x00000C0Full;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_0_MSIEP4_FSI0 = 0x00003040ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSIEP4 = 0x00000C10ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_0_MSIEP5_FSI0 = 0x00003044ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSIEP5 = 0x00000C11ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_0_MSIEP6_FSI0 = 0x00003048ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSIEP6 = 0x00000C12ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_0_MSIEP7_FSI0 = 0x0000304Cull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSIEP7 = 0x00000C13ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_0_MSSIEP0_FSI0 = 0x00003050ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSSIEP0 = 0x00000C14ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_0_MSTAP0_FSI0 = 0x000030D0ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP0 = 0x00000C34ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+
+static const uint32_t P9N2_PERV_FSI_A_MST_0_MSTAP1_FSI0 = 0x000030D4ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP1 = 0x00000C35ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+
+static const uint32_t P9N2_PERV_FSI_A_MST_0_MSTAP2_FSI0 = 0x000030D8ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP2 = 0x00000C36ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+
+static const uint32_t P9N2_PERV_FSI_A_MST_0_MSTAP3_FSI0 = 0x000030DCull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP3 = 0x00000C37ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+
+static const uint32_t P9N2_PERV_FSI_A_MST_0_MSTAP4_FSI0 = 0x000030E0ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP4 = 0x00000C38ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+
+static const uint32_t P9N2_PERV_FSI_A_MST_0_MSTAP5_FSI0 = 0x000030E4ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP5 = 0x00000C39ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+
+static const uint32_t P9N2_PERV_FSI_A_MST_0_MSTAP6_FSI0 = 0x000030E8ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP6 = 0x00000C3Aull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+
+static const uint32_t P9N2_PERV_FSI_A_MST_0_MSTAP7_FSI0 = 0x000030ECull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP7 = 0x00000C3Bull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+
+static const uint32_t P9N2_PERV_FSI_A_MST_0_MVER_FSI0 = 0x00003074ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MVER = 0x00000C1Dull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MAEB_FSI0 = 0x00003470ull;
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MAEB_SCOMFSI0 = 0x00000D1Cull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MAESP0_FSI0 = 0x00003450ull;
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MAESP0_SCOMFSI0 = 0x00000D14ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MAESP1_FSI0 = 0x00003454ull;
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MAESP1_SCOMFSI0 = 0x00000D15ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MAESP2_FSI0 = 0x00003458ull;
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MAESP2_SCOMFSI0 = 0x00000D16ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MAESP3_FSI0 = 0x0000345Cull;
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MAESP3_SCOMFSI0 = 0x00000D17ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MAESP4_FSI0 = 0x00003460ull;
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MAESP4_SCOMFSI0 = 0x00000D18ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MAESP5_FSI0 = 0x00003464ull;
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MAESP5_SCOMFSI0 = 0x00000D19ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MAESP6_FSI0 = 0x00003468ull;
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MAESP6_SCOMFSI0 = 0x00000D1Aull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MAESP7_FSI0 = 0x0000346Cull;
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MAESP7_SCOMFSI0 = 0x00000D1Bull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MATRB0_FSI0 = 0x000035D8ull;
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MATRB0_SCOMFSI0 = 0x00000D76ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MCENP0_FSI0 = 0x00003420ull;
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MCENP0_SCOMFSI0 = 0x00000D08ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MCRSP0_FSI0 = 0x00003408ull;
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MCRSP0_SCOMFSI0 = 0x00000D02ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MCRSP1_FSI0 = 0x0000340Cull;
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MCRSP1_SCOMFSI0 = 0x00000D03ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MCSIEP0_FSI0 = 0x00003470ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MCSIEP0_SCOMFSI0 = 0x00000D1Cull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MDLYR_FSI0 = 0x00003404ull;
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MDLYR_SCOMFSI0 = 0x00000D01ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MDTRB0_FSI0 = 0x000035DCull;
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MDTRB0_SCOMFSI0 = 0x00000D77ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MECTRL_FSI0 = 0x000036E0ull;
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MECTRL_SCOMFSI0 = 0x00000DB8ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MENP0_FSI0 = 0x00003410ull;
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MENP0_SCOMFSI0 = 0x00000D04ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MENP1_FSI0 = 0x00003414ull;
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MENP1_SCOMFSI0 = 0x00000D05ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MESRB0_FSI0 = 0x000035D0ull;
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MESRB0_SCOMFSI0 = 0x00000D74ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MLEVP0_FSI0 = 0x00003418ull;
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MLEVP0_SCOMFSI0 = 0x00000D06ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MLEVP1_FSI0 = 0x0000341Cull;
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MLEVP1_SCOMFSI0 = 0x00000D07ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MMODE_FSI0 = 0x00003400ull;
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MMODE_SCOMFSI0 = 0x00000D00ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MREFP0_FSI0 = 0x00003420ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MREFP0_SCOMFSI0 = 0x00000D08ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MREFP1_FSI0 = 0x00003424ull;
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MREFP1_SCOMFSI0 = 0x00000D09ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MRESB0_FSI0 = 0x000035D0ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MRESB0_SCOMFSI0 = 0x00000D74ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MRESP0_FSI0 = 0x000034D0ull;
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MRESP0_SCOMFSI0 = 0x00000D34ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MRESP1_FSI0 = 0x000034D4ull;
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MRESP1_SCOMFSI0 = 0x00000D35ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MRESP2_FSI0 = 0x000034D8ull;
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MRESP2_SCOMFSI0 = 0x00000D36ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MRESP3_FSI0 = 0x000034DCull;
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MRESP3_SCOMFSI0 = 0x00000D37ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MRESP4_FSI0 = 0x000034E0ull;
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MRESP4_SCOMFSI0 = 0x00000D38ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MRESP5_FSI0 = 0x000034E4ull;
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MRESP5_SCOMFSI0 = 0x00000D39ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MRESP6_FSI0 = 0x000034E8ull;
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MRESP6_SCOMFSI0 = 0x00000D3Aull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MRESP7_FSI0 = 0x000034ECull;
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MRESP7_SCOMFSI0 = 0x00000D3Bull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MSCSB0_FSI0 = 0x000035D4ull;
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MSCSB0_SCOMFSI0 = 0x00000D75ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MSENP0_FSI0 = 0x00003418ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MSENP0_SCOMFSI0 = 0x00000D06ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MSIEP0_FSI0 = 0x00003430ull;
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MSIEP0_SCOMFSI0 = 0x00000D0Cull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MSIEP1_FSI0 = 0x00003434ull;
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MSIEP1_SCOMFSI0 = 0x00000D0Dull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MSIEP2_FSI0 = 0x00003438ull;
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MSIEP2_SCOMFSI0 = 0x00000D0Eull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MSIEP3_FSI0 = 0x0000343Cull;
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MSIEP3_SCOMFSI0 = 0x00000D0Full;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MSIEP4_FSI0 = 0x00003440ull;
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MSIEP4_SCOMFSI0 = 0x00000D10ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MSIEP5_FSI0 = 0x00003444ull;
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MSIEP5_SCOMFSI0 = 0x00000D11ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MSIEP6_FSI0 = 0x00003448ull;
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MSIEP6_SCOMFSI0 = 0x00000D12ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MSIEP7_FSI0 = 0x0000344Cull;
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MSIEP7_SCOMFSI0 = 0x00000D13ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MSSIEP0_FSI0 = 0x00003450ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MSSIEP0_SCOMFSI0 = 0x00000D14ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MSTAP0_FSI0 = 0x000034D0ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MSTAP0_SCOMFSI0 = 0x00000D34ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MSTAP1_FSI0 = 0x000034D4ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MSTAP1_SCOMFSI0 = 0x00000D35ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MSTAP2_FSI0 = 0x000034D8ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MSTAP2_SCOMFSI0 = 0x00000D36ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MSTAP3_FSI0 = 0x000034DCull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MSTAP3_SCOMFSI0 = 0x00000D37ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MSTAP4_FSI0 = 0x000034E0ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MSTAP4_SCOMFSI0 = 0x00000D38ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MSTAP5_FSI0 = 0x000034E4ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MSTAP5_SCOMFSI0 = 0x00000D39ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MSTAP6_FSI0 = 0x000034E8ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MSTAP6_SCOMFSI0 = 0x00000D3Aull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MSTAP7_FSI0 = 0x000034ECull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MSTAP7_SCOMFSI0 = 0x00000D3Bull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MVER_FSI0 = 0x00003474ull;
+
+static const uint32_t P9N2_PERV_FSI_A_MST_1_MVER_SCOMFSI0 = 0x00000D1Dull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_SCI1M_FSI0 = 0x00000820ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_SCI2CM_FSI0 = 0x0000082Cull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_SCISC_FSI0 = 0x00000808ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_SCISM_FSI0 = 0x00000814ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_SCMBL_FSI0 = 0x00000840ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_SCMBR_FSI0 = 0x0000084Cull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_SCMDT_FSI0 = 0x0000082Cull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+
+static const uint32_t P9N2_PERV_FSI_A_SCRSIC0_FSI0 = 0x00000850ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_SCRSIC4_FSI0 = 0x00000854ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_SCRSIM0_FSI0 = 0x00000858ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_SCRSIM4_FSI0 = 0x0000085Cull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_SCRSIS0_FSI0 = 0x00000860ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_SCRSIS4_FSI0 = 0x00000864ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_SDATA_FSI0 = 0x00000830ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_SDMA_FSI0 = 0x00000804ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_SI1M_FSI0 = 0x00000818ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_SI1S_FSI0 = 0x0000081Cull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_SI2M_FSI0 = 0x00000824ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_SI2S_FSI0 = 0x00000828ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_SIC_FSI0 = 0x00000820ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+
+static const uint32_t P9N2_PERV_FSI_A_SISC_FSI0 = 0x00000808ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+
+static const uint32_t P9N2_PERV_FSI_A_SISM_FSI0 = 0x0000080Cull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_SISS_FSI0 = 0x00000810ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_SLASTD_SRES_FSI0 = 0x00000834ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_SLBUS_FSI0 = 0x00000830ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+
+static const uint32_t P9N2_PERV_FSI_A_SMBL_FSI0 = 0x00000838ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_SMBR_FSI0 = 0x00000844ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_SMODE_FSI0 = 0x00000800ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_SNML_FSI0 = 0x00000840ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+
+static const uint32_t P9N2_PERV_FSI_A_SNMR_FSI0 = 0x0000084Cull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+
+static const uint32_t P9N2_PERV_FSI_A_SOML_FSI0 = 0x0000083Cull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_SOMR_FSI0 = 0x00000848ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_SRSIC0_FSI0 = 0x00000868ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_SRSIC4_FSI0 = 0x0000086Cull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_SRSIM0_FSI0 = 0x00000870ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_SRSIM4_FSI0 = 0x00000874ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_SRSIS0_FSI0 = 0x00000878ull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_SRSIS4_FSI0 = 0x0000087Cull;
+
+
+static const uint32_t P9N2_PERV_FSI_A_SSI1M_FSI0 = 0x0000081Cull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+
+static const uint32_t P9N2_PERV_FSI_A_SSI2M_FSI0 = 0x00000828ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+
+static const uint32_t P9N2_PERV_FSI_A_SSISM_FSI0 = 0x00000810ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+
+static const uint32_t P9N2_PERV_FSI_A_SSMBL_FSI0 = 0x0000083Cull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+
+static const uint32_t P9N2_PERV_FSI_A_SSMBR_FSI0 = 0x00000848ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+
+static const uint32_t P9N2_PERV_FSI_A_SSTAT_FSI0 = 0x00000814ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+
+static const uint32_t P9N2_PERV_FSI_B_LLMOD_FSI1 = 0x00000900ull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_LLSTAT_FSI1 = 0x00000904ull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_MST_0_MAEB_FSI1 = 0x00003070ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MAEB = 0x00000C1Cull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_MST_0_MAESP0_FSI1 = 0x00003050ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MAESP0 = 0x00000C14ull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_MST_0_MAESP1_FSI1 = 0x00003054ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MAESP1 = 0x00000C15ull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_MST_0_MAESP2_FSI1 = 0x00003058ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MAESP2 = 0x00000C16ull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_MST_0_MAESP3_FSI1 = 0x0000305Cull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MAESP3 = 0x00000C17ull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_MST_0_MAESP4_FSI1 = 0x00003060ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MAESP4 = 0x00000C18ull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_MST_0_MAESP5_FSI1 = 0x00003064ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MAESP5 = 0x00000C19ull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_MST_0_MAESP6_FSI1 = 0x00003068ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MAESP6 = 0x00000C1Aull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_MST_0_MAESP7_FSI1 = 0x0000306Cull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MAESP7 = 0x00000C1Bull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_MST_0_MATRB0_FSI1 = 0x000031D8ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MATRB0 = 0x00000C76ull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_MST_0_MCENP0_FSI1 = 0x00003020ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MCENP0 = 0x00000C08ull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_MST_0_MCRSP0_FSI1 = 0x00003008ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MCRSP0 = 0x00000C02ull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_MST_0_MCRSP1_FSI1 = 0x0000300Cull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MCRSP1 = 0x00000C03ull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_MST_0_MCSIEP0_FSI1 = 0x00003070ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MCSIEP0 = 0x00000C1Cull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_MST_0_MDLYR_FSI1 = 0x00003004ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MDLYR = 0x00000C01ull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_MST_0_MDTRB0_FSI1 = 0x000031DCull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MDTRB0 = 0x00000C77ull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_MST_0_MECTRL_FSI1 = 0x000032E0ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MECTRL = 0x00000CB8ull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_MST_0_MENP0_FSI1 = 0x00003010ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MENP0 = 0x00000C04ull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_MST_0_MENP1_FSI1 = 0x00003014ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MENP1 = 0x00000C05ull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_MST_0_MESRB0_FSI1 = 0x000031D0ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MESRB0 = 0x00000C74ull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_MST_0_MLEVP0_FSI1 = 0x00003018ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MLEVP0 = 0x00000C06ull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_MST_0_MLEVP1_FSI1 = 0x0000301Cull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MLEVP1 = 0x00000C07ull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_MST_0_MMODE_FSI1 = 0x00003000ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MMODE = 0x00000C00ull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_MST_0_MREFP0_FSI1 = 0x00003020ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MREFP0 = 0x00000C08ull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_MST_0_MREFP1_FSI1 = 0x00003024ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MREFP1 = 0x00000C09ull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_MST_0_MRESB0_FSI1 = 0x000031D0ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MRESB0 = 0x00000C74ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+
+static const uint32_t P9N2_PERV_FSI_B_MST_0_MRESP0_FSI1 = 0x000030D0ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MRESP0 = 0x00000C34ull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_MST_0_MRESP1_FSI1 = 0x000030D4ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MRESP1 = 0x00000C35ull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_MST_0_MRESP2_FSI1 = 0x000030D8ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MRESP2 = 0x00000C36ull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_MST_0_MRESP3_FSI1 = 0x000030DCull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MRESP3 = 0x00000C37ull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_MST_0_MRESP4_FSI1 = 0x000030E0ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MRESP4 = 0x00000C38ull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_MST_0_MRESP5_FSI1 = 0x000030E4ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MRESP5 = 0x00000C39ull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_MST_0_MRESP6_FSI1 = 0x000030E8ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MRESP6 = 0x00000C3Aull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_MST_0_MRESP7_FSI1 = 0x000030ECull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MRESP7 = 0x00000C3Bull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_MST_0_MSCSB0_FSI1 = 0x000031D4ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSCSB0 = 0x00000C75ull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_MST_0_MSENP0_FSI1 = 0x00003018ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSENP0 = 0x00000C06ull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_MST_0_MSIEP0_FSI1 = 0x00003030ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSIEP0 = 0x00000C0Cull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_MST_0_MSIEP1_FSI1 = 0x00003034ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSIEP1 = 0x00000C0Dull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_MST_0_MSIEP2_FSI1 = 0x00003038ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSIEP2 = 0x00000C0Eull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_MST_0_MSIEP3_FSI1 = 0x0000303Cull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSIEP3 = 0x00000C0Full;
+
+
+static const uint32_t P9N2_PERV_FSI_B_MST_0_MSIEP4_FSI1 = 0x00003040ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSIEP4 = 0x00000C10ull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_MST_0_MSIEP5_FSI1 = 0x00003044ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSIEP5 = 0x00000C11ull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_MST_0_MSIEP6_FSI1 = 0x00003048ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSIEP6 = 0x00000C12ull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_MST_0_MSIEP7_FSI1 = 0x0000304Cull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSIEP7 = 0x00000C13ull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_MST_0_MSSIEP0_FSI1 = 0x00003050ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSSIEP0 = 0x00000C14ull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_MST_0_MSTAP0_FSI1 = 0x000030D0ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP0 = 0x00000C34ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+
+static const uint32_t P9N2_PERV_FSI_B_MST_0_MSTAP1_FSI1 = 0x000030D4ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP1 = 0x00000C35ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+
+static const uint32_t P9N2_PERV_FSI_B_MST_0_MSTAP2_FSI1 = 0x000030D8ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP2 = 0x00000C36ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+
+static const uint32_t P9N2_PERV_FSI_B_MST_0_MSTAP3_FSI1 = 0x000030DCull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP3 = 0x00000C37ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+
+static const uint32_t P9N2_PERV_FSI_B_MST_0_MSTAP4_FSI1 = 0x000030E0ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP4 = 0x00000C38ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+
+static const uint32_t P9N2_PERV_FSI_B_MST_0_MSTAP5_FSI1 = 0x000030E4ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP5 = 0x00000C39ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+
+static const uint32_t P9N2_PERV_FSI_B_MST_0_MSTAP6_FSI1 = 0x000030E8ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP6 = 0x00000C3Aull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+
+static const uint32_t P9N2_PERV_FSI_B_MST_0_MSTAP7_FSI1 = 0x000030ECull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP7 = 0x00000C3Bull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+
+static const uint32_t P9N2_PERV_FSI_B_MST_0_MVER_FSI1 = 0x00003074ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MVER = 0x00000C1Dull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_SCI1M_FSI1 = 0x00000820ull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_SCI2CM_FSI1 = 0x0000082Cull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_SCISC_FSI1 = 0x00000808ull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_SCISM_FSI1 = 0x00000814ull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_SCMBL_FSI1 = 0x00000840ull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_SCMBR_FSI1 = 0x0000084Cull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_SCMDT_FSI1 = 0x0000082Cull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+
+static const uint32_t P9N2_PERV_FSI_B_SCRSIC0_FSI1 = 0x00000850ull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_SCRSIC4_FSI1 = 0x00000854ull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_SCRSIM0_FSI1 = 0x00000858ull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_SCRSIM4_FSI1 = 0x0000085Cull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_SCRSIS0_FSI1 = 0x00000860ull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_SCRSIS4_FSI1 = 0x00000864ull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_SDATA_FSI1 = 0x00000830ull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_SDMA_FSI1 = 0x00000804ull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_SI1M_FSI1 = 0x00000818ull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_SI1S_FSI1 = 0x0000081Cull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_SI2M_FSI1 = 0x00000824ull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_SI2S_FSI1 = 0x00000828ull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_SIC_FSI1 = 0x00000820ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+
+static const uint32_t P9N2_PERV_FSI_B_SISC_FSI1 = 0x00000808ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+
+static const uint32_t P9N2_PERV_FSI_B_SISM_FSI1 = 0x0000080Cull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_SISS_FSI1 = 0x00000810ull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_SLASTD_SRES_FSI1 = 0x00000834ull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_SLBUS_FSI1 = 0x00000830ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+
+static const uint32_t P9N2_PERV_FSI_B_SMBL_FSI1 = 0x00000838ull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_SMBR_FSI1 = 0x00000844ull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_SMODE_FSI1 = 0x00000800ull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_SNML_FSI1 = 0x00000840ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+
+static const uint32_t P9N2_PERV_FSI_B_SNMR_FSI1 = 0x0000084Cull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+
+static const uint32_t P9N2_PERV_FSI_B_SOML_FSI1 = 0x0000083Cull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_SOMR_FSI1 = 0x00000848ull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_SRSIC0_FSI1 = 0x00000868ull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_SRSIC4_FSI1 = 0x0000086Cull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_SRSIM0_FSI1 = 0x00000870ull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_SRSIM4_FSI1 = 0x00000874ull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_SRSIS0_FSI1 = 0x00000878ull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_SRSIS4_FSI1 = 0x0000087Cull;
+
+
+static const uint32_t P9N2_PERV_FSI_B_SSI1M_FSI1 = 0x0000081Cull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+
+static const uint32_t P9N2_PERV_FSI_B_SSI2M_FSI1 = 0x00000828ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+
+static const uint32_t P9N2_PERV_FSI_B_SSISM_FSI1 = 0x00000810ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+
+static const uint32_t P9N2_PERV_FSI_B_SSMBL_FSI1 = 0x0000083Cull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+
+static const uint32_t P9N2_PERV_FSI_B_SSMBR_FSI1 = 0x00000848ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+
+static const uint32_t P9N2_PERV_FSI_B_SSTAT_FSI1 = 0x00000814ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+
+static const uint32_t P9N2_PERV_GPWRP_FSI = 0x0000281Full;
+
+static const uint32_t P9N2_PERV_GPWRP_FSI_BYTE = 0x0000287Cull;
+
+static const uint64_t P9N2_PERV_GPWRP_SCOM = 0x0005001Full;
+
+static const uint64_t P9N2_PERV_PIB_GPWRP = 0x0005001Full;
+
+
+static const uint64_t P9N2_PERV_GXSTOP0_MASK_REG = 0x00040014ull;
+
+static const uint64_t P9N2_PERV_TP_GXSTOP0_MASK_REG = 0x01040014ull;
+
+static const uint64_t P9N2_PERV_N0_GXSTOP0_MASK_REG = 0x02040014ull;
+
+static const uint64_t P9N2_PERV_N1_GXSTOP0_MASK_REG = 0x03040014ull;
+
+static const uint64_t P9N2_PERV_N2_GXSTOP0_MASK_REG = 0x04040014ull;
+
+static const uint64_t P9N2_PERV_N3_GXSTOP0_MASK_REG = 0x05040014ull;
+
+static const uint64_t P9N2_PERV_XB_GXSTOP0_MASK_REG = 0x06040014ull;
+
+static const uint64_t P9N2_PERV_MC01_GXSTOP0_MASK_REG = 0x07040014ull;
+
+static const uint64_t P9N2_PERV_MC23_GXSTOP0_MASK_REG = 0x08040014ull;
+
+static const uint64_t P9N2_PERV_OB0_GXSTOP0_MASK_REG = 0x09040014ull;
+
+static const uint64_t P9N2_PERV_OB3_GXSTOP0_MASK_REG = 0x0C040014ull;
+
+static const uint64_t P9N2_PERV_PCI0_GXSTOP0_MASK_REG = 0x0D040014ull;
+
+static const uint64_t P9N2_PERV_PCI1_GXSTOP0_MASK_REG = 0x0E040014ull;
+
+static const uint64_t P9N2_PERV_PCI2_GXSTOP0_MASK_REG = 0x0F040014ull;
+
+static const uint64_t P9N2_PERV_EP00_GXSTOP0_MASK_REG = 0x10040014ull;
+
+static const uint64_t P9N2_PERV_EP01_GXSTOP0_MASK_REG = 0x11040014ull;
+
+static const uint64_t P9N2_PERV_EP02_GXSTOP0_MASK_REG = 0x12040014ull;
+
+static const uint64_t P9N2_PERV_EP03_GXSTOP0_MASK_REG = 0x13040014ull;
+
+static const uint64_t P9N2_PERV_EP04_GXSTOP0_MASK_REG = 0x14040014ull;
+
+static const uint64_t P9N2_PERV_EP05_GXSTOP0_MASK_REG = 0x15040014ull;
+
+static const uint64_t P9N2_PERV_EC00_GXSTOP0_MASK_REG = 0x20040014ull;
+
+static const uint64_t P9N2_PERV_EC01_GXSTOP0_MASK_REG = 0x21040014ull;
+
+static const uint64_t P9N2_PERV_EC02_GXSTOP0_MASK_REG = 0x22040014ull;
+
+static const uint64_t P9N2_PERV_EC03_GXSTOP0_MASK_REG = 0x23040014ull;
+
+static const uint64_t P9N2_PERV_EC04_GXSTOP0_MASK_REG = 0x24040014ull;
+
+static const uint64_t P9N2_PERV_EC05_GXSTOP0_MASK_REG = 0x25040014ull;
+
+static const uint64_t P9N2_PERV_EC06_GXSTOP0_MASK_REG = 0x26040014ull;
+
+static const uint64_t P9N2_PERV_EC07_GXSTOP0_MASK_REG = 0x27040014ull;
+
+static const uint64_t P9N2_PERV_EC08_GXSTOP0_MASK_REG = 0x28040014ull;
+
+static const uint64_t P9N2_PERV_EC09_GXSTOP0_MASK_REG = 0x29040014ull;
+
+static const uint64_t P9N2_PERV_EC10_GXSTOP0_MASK_REG = 0x2A040014ull;
+
+static const uint64_t P9N2_PERV_EC11_GXSTOP0_MASK_REG = 0x2B040014ull;
+
+static const uint64_t P9N2_PERV_EC12_GXSTOP0_MASK_REG = 0x2C040014ull;
+
+static const uint64_t P9N2_PERV_EC13_GXSTOP0_MASK_REG = 0x2D040014ull;
+
+static const uint64_t P9N2_PERV_EC14_GXSTOP0_MASK_REG = 0x2E040014ull;
+
+static const uint64_t P9N2_PERV_EC15_GXSTOP0_MASK_REG = 0x2F040014ull;
+
+static const uint64_t P9N2_PERV_EC16_GXSTOP0_MASK_REG = 0x30040014ull;
+
+static const uint64_t P9N2_PERV_EC17_GXSTOP0_MASK_REG = 0x31040014ull;
+
+static const uint64_t P9N2_PERV_EC18_GXSTOP0_MASK_REG = 0x32040014ull;
+
+static const uint64_t P9N2_PERV_EC19_GXSTOP0_MASK_REG = 0x33040014ull;
+
+static const uint64_t P9N2_PERV_EC20_GXSTOP0_MASK_REG = 0x34040014ull;
+
+static const uint64_t P9N2_PERV_EC21_GXSTOP0_MASK_REG = 0x35040014ull;
+
+static const uint64_t P9N2_PERV_EC22_GXSTOP0_MASK_REG = 0x36040014ull;
+
+static const uint64_t P9N2_PERV_EC23_GXSTOP0_MASK_REG = 0x37040014ull;
+
+
+static const uint64_t P9N2_PERV_GXSTOP1_MASK_REG = 0x00040015ull;
+
+static const uint64_t P9N2_PERV_TP_GXSTOP1_MASK_REG = 0x01040015ull;
+
+static const uint64_t P9N2_PERV_N0_GXSTOP1_MASK_REG = 0x02040015ull;
+
+static const uint64_t P9N2_PERV_N1_GXSTOP1_MASK_REG = 0x03040015ull;
+
+static const uint64_t P9N2_PERV_N2_GXSTOP1_MASK_REG = 0x04040015ull;
+
+static const uint64_t P9N2_PERV_N3_GXSTOP1_MASK_REG = 0x05040015ull;
+
+static const uint64_t P9N2_PERV_XB_GXSTOP1_MASK_REG = 0x06040015ull;
+
+static const uint64_t P9N2_PERV_MC01_GXSTOP1_MASK_REG = 0x07040015ull;
+
+static const uint64_t P9N2_PERV_MC23_GXSTOP1_MASK_REG = 0x08040015ull;
+
+static const uint64_t P9N2_PERV_OB0_GXSTOP1_MASK_REG = 0x09040015ull;
+
+static const uint64_t P9N2_PERV_OB3_GXSTOP1_MASK_REG = 0x0C040015ull;
+
+static const uint64_t P9N2_PERV_PCI0_GXSTOP1_MASK_REG = 0x0D040015ull;
+
+static const uint64_t P9N2_PERV_PCI1_GXSTOP1_MASK_REG = 0x0E040015ull;
+
+static const uint64_t P9N2_PERV_PCI2_GXSTOP1_MASK_REG = 0x0F040015ull;
+
+static const uint64_t P9N2_PERV_EP00_GXSTOP1_MASK_REG = 0x10040015ull;
+
+static const uint64_t P9N2_PERV_EP01_GXSTOP1_MASK_REG = 0x11040015ull;
+
+static const uint64_t P9N2_PERV_EP02_GXSTOP1_MASK_REG = 0x12040015ull;
+
+static const uint64_t P9N2_PERV_EP03_GXSTOP1_MASK_REG = 0x13040015ull;
+
+static const uint64_t P9N2_PERV_EP04_GXSTOP1_MASK_REG = 0x14040015ull;
+
+static const uint64_t P9N2_PERV_EP05_GXSTOP1_MASK_REG = 0x15040015ull;
+
+static const uint64_t P9N2_PERV_EC00_GXSTOP1_MASK_REG = 0x20040015ull;
+
+static const uint64_t P9N2_PERV_EC01_GXSTOP1_MASK_REG = 0x21040015ull;
+
+static const uint64_t P9N2_PERV_EC02_GXSTOP1_MASK_REG = 0x22040015ull;
+
+static const uint64_t P9N2_PERV_EC03_GXSTOP1_MASK_REG = 0x23040015ull;
+
+static const uint64_t P9N2_PERV_EC04_GXSTOP1_MASK_REG = 0x24040015ull;
+
+static const uint64_t P9N2_PERV_EC05_GXSTOP1_MASK_REG = 0x25040015ull;
+
+static const uint64_t P9N2_PERV_EC06_GXSTOP1_MASK_REG = 0x26040015ull;
+
+static const uint64_t P9N2_PERV_EC07_GXSTOP1_MASK_REG = 0x27040015ull;
+
+static const uint64_t P9N2_PERV_EC08_GXSTOP1_MASK_REG = 0x28040015ull;
+
+static const uint64_t P9N2_PERV_EC09_GXSTOP1_MASK_REG = 0x29040015ull;
+
+static const uint64_t P9N2_PERV_EC10_GXSTOP1_MASK_REG = 0x2A040015ull;
+
+static const uint64_t P9N2_PERV_EC11_GXSTOP1_MASK_REG = 0x2B040015ull;
+
+static const uint64_t P9N2_PERV_EC12_GXSTOP1_MASK_REG = 0x2C040015ull;
+
+static const uint64_t P9N2_PERV_EC13_GXSTOP1_MASK_REG = 0x2D040015ull;
+
+static const uint64_t P9N2_PERV_EC14_GXSTOP1_MASK_REG = 0x2E040015ull;
+
+static const uint64_t P9N2_PERV_EC15_GXSTOP1_MASK_REG = 0x2F040015ull;
+
+static const uint64_t P9N2_PERV_EC16_GXSTOP1_MASK_REG = 0x30040015ull;
+
+static const uint64_t P9N2_PERV_EC17_GXSTOP1_MASK_REG = 0x31040015ull;
+
+static const uint64_t P9N2_PERV_EC18_GXSTOP1_MASK_REG = 0x32040015ull;
+
+static const uint64_t P9N2_PERV_EC19_GXSTOP1_MASK_REG = 0x33040015ull;
+
+static const uint64_t P9N2_PERV_EC20_GXSTOP1_MASK_REG = 0x34040015ull;
+
+static const uint64_t P9N2_PERV_EC21_GXSTOP1_MASK_REG = 0x35040015ull;
+
+static const uint64_t P9N2_PERV_EC22_GXSTOP1_MASK_REG = 0x36040015ull;
+
+static const uint64_t P9N2_PERV_EC23_GXSTOP1_MASK_REG = 0x37040015ull;
+
+
+static const uint64_t P9N2_PERV_GXSTOP2_MASK_REG = 0x00040016ull;
+
+static const uint64_t P9N2_PERV_TP_GXSTOP2_MASK_REG = 0x01040016ull;
+
+static const uint64_t P9N2_PERV_N0_GXSTOP2_MASK_REG = 0x02040016ull;
+
+static const uint64_t P9N2_PERV_N1_GXSTOP2_MASK_REG = 0x03040016ull;
+
+static const uint64_t P9N2_PERV_N2_GXSTOP2_MASK_REG = 0x04040016ull;
+
+static const uint64_t P9N2_PERV_N3_GXSTOP2_MASK_REG = 0x05040016ull;
+
+static const uint64_t P9N2_PERV_XB_GXSTOP2_MASK_REG = 0x06040016ull;
+
+static const uint64_t P9N2_PERV_MC01_GXSTOP2_MASK_REG = 0x07040016ull;
+
+static const uint64_t P9N2_PERV_MC23_GXSTOP2_MASK_REG = 0x08040016ull;
+
+static const uint64_t P9N2_PERV_OB0_GXSTOP2_MASK_REG = 0x09040016ull;
+
+static const uint64_t P9N2_PERV_OB3_GXSTOP2_MASK_REG = 0x0C040016ull;
+
+static const uint64_t P9N2_PERV_PCI0_GXSTOP2_MASK_REG = 0x0D040016ull;
+
+static const uint64_t P9N2_PERV_PCI1_GXSTOP2_MASK_REG = 0x0E040016ull;
+
+static const uint64_t P9N2_PERV_PCI2_GXSTOP2_MASK_REG = 0x0F040016ull;
+
+static const uint64_t P9N2_PERV_EP00_GXSTOP2_MASK_REG = 0x10040016ull;
+
+static const uint64_t P9N2_PERV_EP01_GXSTOP2_MASK_REG = 0x11040016ull;
+
+static const uint64_t P9N2_PERV_EP02_GXSTOP2_MASK_REG = 0x12040016ull;
+
+static const uint64_t P9N2_PERV_EP03_GXSTOP2_MASK_REG = 0x13040016ull;
+
+static const uint64_t P9N2_PERV_EP04_GXSTOP2_MASK_REG = 0x14040016ull;
+
+static const uint64_t P9N2_PERV_EP05_GXSTOP2_MASK_REG = 0x15040016ull;
+
+static const uint64_t P9N2_PERV_EC00_GXSTOP2_MASK_REG = 0x20040016ull;
+
+static const uint64_t P9N2_PERV_EC01_GXSTOP2_MASK_REG = 0x21040016ull;
+
+static const uint64_t P9N2_PERV_EC02_GXSTOP2_MASK_REG = 0x22040016ull;
+
+static const uint64_t P9N2_PERV_EC03_GXSTOP2_MASK_REG = 0x23040016ull;
+
+static const uint64_t P9N2_PERV_EC04_GXSTOP2_MASK_REG = 0x24040016ull;
+
+static const uint64_t P9N2_PERV_EC05_GXSTOP2_MASK_REG = 0x25040016ull;
+
+static const uint64_t P9N2_PERV_EC06_GXSTOP2_MASK_REG = 0x26040016ull;
+
+static const uint64_t P9N2_PERV_EC07_GXSTOP2_MASK_REG = 0x27040016ull;
+
+static const uint64_t P9N2_PERV_EC08_GXSTOP2_MASK_REG = 0x28040016ull;
+
+static const uint64_t P9N2_PERV_EC09_GXSTOP2_MASK_REG = 0x29040016ull;
+
+static const uint64_t P9N2_PERV_EC10_GXSTOP2_MASK_REG = 0x2A040016ull;
+
+static const uint64_t P9N2_PERV_EC11_GXSTOP2_MASK_REG = 0x2B040016ull;
+
+static const uint64_t P9N2_PERV_EC12_GXSTOP2_MASK_REG = 0x2C040016ull;
+
+static const uint64_t P9N2_PERV_EC13_GXSTOP2_MASK_REG = 0x2D040016ull;
+
+static const uint64_t P9N2_PERV_EC14_GXSTOP2_MASK_REG = 0x2E040016ull;
+
+static const uint64_t P9N2_PERV_EC15_GXSTOP2_MASK_REG = 0x2F040016ull;
+
+static const uint64_t P9N2_PERV_EC16_GXSTOP2_MASK_REG = 0x30040016ull;
+
+static const uint64_t P9N2_PERV_EC17_GXSTOP2_MASK_REG = 0x31040016ull;
+
+static const uint64_t P9N2_PERV_EC18_GXSTOP2_MASK_REG = 0x32040016ull;
+
+static const uint64_t P9N2_PERV_EC19_GXSTOP2_MASK_REG = 0x33040016ull;
+
+static const uint64_t P9N2_PERV_EC20_GXSTOP2_MASK_REG = 0x34040016ull;
+
+static const uint64_t P9N2_PERV_EC21_GXSTOP2_MASK_REG = 0x35040016ull;
+
+static const uint64_t P9N2_PERV_EC22_GXSTOP2_MASK_REG = 0x36040016ull;
+
+static const uint64_t P9N2_PERV_EC23_GXSTOP2_MASK_REG = 0x37040016ull;
+
+
+static const uint64_t P9N2_PERV_GXSTOP_TRIG_REG = 0x00040013ull;
+
+static const uint64_t P9N2_PERV_TP_GXSTOP_TRIG_REG = 0x01040013ull;
+
+static const uint64_t P9N2_PERV_N0_GXSTOP_TRIG_REG = 0x02040013ull;
+
+static const uint64_t P9N2_PERV_N1_GXSTOP_TRIG_REG = 0x03040013ull;
+
+static const uint64_t P9N2_PERV_N2_GXSTOP_TRIG_REG = 0x04040013ull;
+
+static const uint64_t P9N2_PERV_N3_GXSTOP_TRIG_REG = 0x05040013ull;
+
+static const uint64_t P9N2_PERV_XB_GXSTOP_TRIG_REG = 0x06040013ull;
+
+static const uint64_t P9N2_PERV_MC01_GXSTOP_TRIG_REG = 0x07040013ull;
+
+static const uint64_t P9N2_PERV_MC23_GXSTOP_TRIG_REG = 0x08040013ull;
+
+static const uint64_t P9N2_PERV_OB0_GXSTOP_TRIG_REG = 0x09040013ull;
+
+static const uint64_t P9N2_PERV_OB3_GXSTOP_TRIG_REG = 0x0C040013ull;
+
+static const uint64_t P9N2_PERV_PCI0_GXSTOP_TRIG_REG = 0x0D040013ull;
+
+static const uint64_t P9N2_PERV_PCI1_GXSTOP_TRIG_REG = 0x0E040013ull;
+
+static const uint64_t P9N2_PERV_PCI2_GXSTOP_TRIG_REG = 0x0F040013ull;
+
+static const uint64_t P9N2_PERV_EP00_GXSTOP_TRIG_REG = 0x10040013ull;
+
+static const uint64_t P9N2_PERV_EP01_GXSTOP_TRIG_REG = 0x11040013ull;
+
+static const uint64_t P9N2_PERV_EP02_GXSTOP_TRIG_REG = 0x12040013ull;
+
+static const uint64_t P9N2_PERV_EP03_GXSTOP_TRIG_REG = 0x13040013ull;
+
+static const uint64_t P9N2_PERV_EP04_GXSTOP_TRIG_REG = 0x14040013ull;
+
+static const uint64_t P9N2_PERV_EP05_GXSTOP_TRIG_REG = 0x15040013ull;
+
+static const uint64_t P9N2_PERV_EC00_GXSTOP_TRIG_REG = 0x20040013ull;
+
+static const uint64_t P9N2_PERV_EC01_GXSTOP_TRIG_REG = 0x21040013ull;
+
+static const uint64_t P9N2_PERV_EC02_GXSTOP_TRIG_REG = 0x22040013ull;
+
+static const uint64_t P9N2_PERV_EC03_GXSTOP_TRIG_REG = 0x23040013ull;
+
+static const uint64_t P9N2_PERV_EC04_GXSTOP_TRIG_REG = 0x24040013ull;
+
+static const uint64_t P9N2_PERV_EC05_GXSTOP_TRIG_REG = 0x25040013ull;
+
+static const uint64_t P9N2_PERV_EC06_GXSTOP_TRIG_REG = 0x26040013ull;
+
+static const uint64_t P9N2_PERV_EC07_GXSTOP_TRIG_REG = 0x27040013ull;
+
+static const uint64_t P9N2_PERV_EC08_GXSTOP_TRIG_REG = 0x28040013ull;
+
+static const uint64_t P9N2_PERV_EC09_GXSTOP_TRIG_REG = 0x29040013ull;
+
+static const uint64_t P9N2_PERV_EC10_GXSTOP_TRIG_REG = 0x2A040013ull;
+
+static const uint64_t P9N2_PERV_EC11_GXSTOP_TRIG_REG = 0x2B040013ull;
+
+static const uint64_t P9N2_PERV_EC12_GXSTOP_TRIG_REG = 0x2C040013ull;
+
+static const uint64_t P9N2_PERV_EC13_GXSTOP_TRIG_REG = 0x2D040013ull;
+
+static const uint64_t P9N2_PERV_EC14_GXSTOP_TRIG_REG = 0x2E040013ull;
+
+static const uint64_t P9N2_PERV_EC15_GXSTOP_TRIG_REG = 0x2F040013ull;
+
+static const uint64_t P9N2_PERV_EC16_GXSTOP_TRIG_REG = 0x30040013ull;
+
+static const uint64_t P9N2_PERV_EC17_GXSTOP_TRIG_REG = 0x31040013ull;
+
+static const uint64_t P9N2_PERV_EC18_GXSTOP_TRIG_REG = 0x32040013ull;
+
+static const uint64_t P9N2_PERV_EC19_GXSTOP_TRIG_REG = 0x33040013ull;
+
+static const uint64_t P9N2_PERV_EC20_GXSTOP_TRIG_REG = 0x34040013ull;
+
+static const uint64_t P9N2_PERV_EC21_GXSTOP_TRIG_REG = 0x35040013ull;
+
+static const uint64_t P9N2_PERV_EC22_GXSTOP_TRIG_REG = 0x36040013ull;
+
+static const uint64_t P9N2_PERV_EC23_GXSTOP_TRIG_REG = 0x37040013ull;
+
+
+static const uint64_t P9N2_PERV_HANG_PULSE_0_REG = 0x000F0020ull;
+
+static const uint64_t P9N2_PERV_TP_HANG_PULSE_0_REG = 0x010F0020ull;
+
+static const uint64_t P9N2_PERV_N0_HANG_PULSE_0_REG = 0x020F0020ull;
+
+static const uint64_t P9N2_PERV_N1_HANG_PULSE_0_REG = 0x030F0020ull;
+
+static const uint64_t P9N2_PERV_N2_HANG_PULSE_0_REG = 0x040F0020ull;
+
+static const uint64_t P9N2_PERV_N3_HANG_PULSE_0_REG = 0x050F0020ull;
+
+static const uint64_t P9N2_PERV_XB_HANG_PULSE_0_REG = 0x060F0020ull;
+
+static const uint64_t P9N2_PERV_MC01_HANG_PULSE_0_REG = 0x070F0020ull;
+
+static const uint64_t P9N2_PERV_MC23_HANG_PULSE_0_REG = 0x080F0020ull;
+
+static const uint64_t P9N2_PERV_OB0_HANG_PULSE_0_REG = 0x090F0020ull;
+
+static const uint64_t P9N2_PERV_OB3_HANG_PULSE_0_REG = 0x0C0F0020ull;
+
+static const uint64_t P9N2_PERV_PCI0_HANG_PULSE_0_REG = 0x0D0F0020ull;
+
+static const uint64_t P9N2_PERV_PCI1_HANG_PULSE_0_REG = 0x0E0F0020ull;
+
+static const uint64_t P9N2_PERV_PCI2_HANG_PULSE_0_REG = 0x0F0F0020ull;
+
+static const uint64_t P9N2_PERV_EP00_HANG_PULSE_0_REG = 0x100F0020ull;
+
+static const uint64_t P9N2_PERV_EP01_HANG_PULSE_0_REG = 0x110F0020ull;
+
+static const uint64_t P9N2_PERV_EP02_HANG_PULSE_0_REG = 0x120F0020ull;
+
+static const uint64_t P9N2_PERV_EP03_HANG_PULSE_0_REG = 0x130F0020ull;
+
+static const uint64_t P9N2_PERV_EP04_HANG_PULSE_0_REG = 0x140F0020ull;
+
+static const uint64_t P9N2_PERV_EP05_HANG_PULSE_0_REG = 0x150F0020ull;
+
+static const uint64_t P9N2_PERV_EC00_HANG_PULSE_0_REG = 0x200F0020ull;
+
+static const uint64_t P9N2_PERV_EC01_HANG_PULSE_0_REG = 0x210F0020ull;
+
+static const uint64_t P9N2_PERV_EC02_HANG_PULSE_0_REG = 0x220F0020ull;
+
+static const uint64_t P9N2_PERV_EC03_HANG_PULSE_0_REG = 0x230F0020ull;
+
+static const uint64_t P9N2_PERV_EC04_HANG_PULSE_0_REG = 0x240F0020ull;
+
+static const uint64_t P9N2_PERV_EC05_HANG_PULSE_0_REG = 0x250F0020ull;
+
+static const uint64_t P9N2_PERV_EC06_HANG_PULSE_0_REG = 0x260F0020ull;
+
+static const uint64_t P9N2_PERV_EC07_HANG_PULSE_0_REG = 0x270F0020ull;
+
+static const uint64_t P9N2_PERV_EC08_HANG_PULSE_0_REG = 0x280F0020ull;
+
+static const uint64_t P9N2_PERV_EC09_HANG_PULSE_0_REG = 0x290F0020ull;
+
+static const uint64_t P9N2_PERV_EC10_HANG_PULSE_0_REG = 0x2A0F0020ull;
+
+static const uint64_t P9N2_PERV_EC11_HANG_PULSE_0_REG = 0x2B0F0020ull;
+
+static const uint64_t P9N2_PERV_EC12_HANG_PULSE_0_REG = 0x2C0F0020ull;
+
+static const uint64_t P9N2_PERV_EC13_HANG_PULSE_0_REG = 0x2D0F0020ull;
+
+static const uint64_t P9N2_PERV_EC14_HANG_PULSE_0_REG = 0x2E0F0020ull;
+
+static const uint64_t P9N2_PERV_EC15_HANG_PULSE_0_REG = 0x2F0F0020ull;
+
+static const uint64_t P9N2_PERV_EC16_HANG_PULSE_0_REG = 0x300F0020ull;
+
+static const uint64_t P9N2_PERV_EC17_HANG_PULSE_0_REG = 0x310F0020ull;
+
+static const uint64_t P9N2_PERV_EC18_HANG_PULSE_0_REG = 0x320F0020ull;
+
+static const uint64_t P9N2_PERV_EC19_HANG_PULSE_0_REG = 0x330F0020ull;
+
+static const uint64_t P9N2_PERV_EC20_HANG_PULSE_0_REG = 0x340F0020ull;
+
+static const uint64_t P9N2_PERV_EC21_HANG_PULSE_0_REG = 0x350F0020ull;
+
+static const uint64_t P9N2_PERV_EC22_HANG_PULSE_0_REG = 0x360F0020ull;
+
+static const uint64_t P9N2_PERV_EC23_HANG_PULSE_0_REG = 0x370F0020ull;
+
+
+static const uint64_t P9N2_PERV_HANG_PULSE_1_REG = 0x000F0021ull;
+
+static const uint64_t P9N2_PERV_TP_HANG_PULSE_1_REG = 0x010F0021ull;
+
+static const uint64_t P9N2_PERV_N0_HANG_PULSE_1_REG = 0x020F0021ull;
+
+static const uint64_t P9N2_PERV_N1_HANG_PULSE_1_REG = 0x030F0021ull;
+
+static const uint64_t P9N2_PERV_N2_HANG_PULSE_1_REG = 0x040F0021ull;
+
+static const uint64_t P9N2_PERV_N3_HANG_PULSE_1_REG = 0x050F0021ull;
+
+static const uint64_t P9N2_PERV_XB_HANG_PULSE_1_REG = 0x060F0021ull;
+
+static const uint64_t P9N2_PERV_MC01_HANG_PULSE_1_REG = 0x070F0021ull;
+
+static const uint64_t P9N2_PERV_MC23_HANG_PULSE_1_REG = 0x080F0021ull;
+
+static const uint64_t P9N2_PERV_OB0_HANG_PULSE_1_REG = 0x090F0021ull;
+
+static const uint64_t P9N2_PERV_OB3_HANG_PULSE_1_REG = 0x0C0F0021ull;
+
+static const uint64_t P9N2_PERV_PCI0_HANG_PULSE_1_REG = 0x0D0F0021ull;
+
+static const uint64_t P9N2_PERV_PCI1_HANG_PULSE_1_REG = 0x0E0F0021ull;
+
+static const uint64_t P9N2_PERV_PCI2_HANG_PULSE_1_REG = 0x0F0F0021ull;
+
+static const uint64_t P9N2_PERV_EP00_HANG_PULSE_1_REG = 0x100F0021ull;
+
+static const uint64_t P9N2_PERV_EP01_HANG_PULSE_1_REG = 0x110F0021ull;
+
+static const uint64_t P9N2_PERV_EP02_HANG_PULSE_1_REG = 0x120F0021ull;
+
+static const uint64_t P9N2_PERV_EP03_HANG_PULSE_1_REG = 0x130F0021ull;
+
+static const uint64_t P9N2_PERV_EP04_HANG_PULSE_1_REG = 0x140F0021ull;
+
+static const uint64_t P9N2_PERV_EP05_HANG_PULSE_1_REG = 0x150F0021ull;
+
+static const uint64_t P9N2_PERV_EC00_HANG_PULSE_1_REG = 0x200F0021ull;
+
+static const uint64_t P9N2_PERV_EC01_HANG_PULSE_1_REG = 0x210F0021ull;
+
+static const uint64_t P9N2_PERV_EC02_HANG_PULSE_1_REG = 0x220F0021ull;
+
+static const uint64_t P9N2_PERV_EC03_HANG_PULSE_1_REG = 0x230F0021ull;
+
+static const uint64_t P9N2_PERV_EC04_HANG_PULSE_1_REG = 0x240F0021ull;
+
+static const uint64_t P9N2_PERV_EC05_HANG_PULSE_1_REG = 0x250F0021ull;
+
+static const uint64_t P9N2_PERV_EC06_HANG_PULSE_1_REG = 0x260F0021ull;
+
+static const uint64_t P9N2_PERV_EC07_HANG_PULSE_1_REG = 0x270F0021ull;
+
+static const uint64_t P9N2_PERV_EC08_HANG_PULSE_1_REG = 0x280F0021ull;
+
+static const uint64_t P9N2_PERV_EC09_HANG_PULSE_1_REG = 0x290F0021ull;
+
+static const uint64_t P9N2_PERV_EC10_HANG_PULSE_1_REG = 0x2A0F0021ull;
+
+static const uint64_t P9N2_PERV_EC11_HANG_PULSE_1_REG = 0x2B0F0021ull;
+
+static const uint64_t P9N2_PERV_EC12_HANG_PULSE_1_REG = 0x2C0F0021ull;
+
+static const uint64_t P9N2_PERV_EC13_HANG_PULSE_1_REG = 0x2D0F0021ull;
+
+static const uint64_t P9N2_PERV_EC14_HANG_PULSE_1_REG = 0x2E0F0021ull;
+
+static const uint64_t P9N2_PERV_EC15_HANG_PULSE_1_REG = 0x2F0F0021ull;
+
+static const uint64_t P9N2_PERV_EC16_HANG_PULSE_1_REG = 0x300F0021ull;
+
+static const uint64_t P9N2_PERV_EC17_HANG_PULSE_1_REG = 0x310F0021ull;
+
+static const uint64_t P9N2_PERV_EC18_HANG_PULSE_1_REG = 0x320F0021ull;
+
+static const uint64_t P9N2_PERV_EC19_HANG_PULSE_1_REG = 0x330F0021ull;
+
+static const uint64_t P9N2_PERV_EC20_HANG_PULSE_1_REG = 0x340F0021ull;
+
+static const uint64_t P9N2_PERV_EC21_HANG_PULSE_1_REG = 0x350F0021ull;
+
+static const uint64_t P9N2_PERV_EC22_HANG_PULSE_1_REG = 0x360F0021ull;
+
+static const uint64_t P9N2_PERV_EC23_HANG_PULSE_1_REG = 0x370F0021ull;
+
+
+static const uint64_t P9N2_PERV_HANG_PULSE_2_REG = 0x000F0022ull;
+
+static const uint64_t P9N2_PERV_TP_HANG_PULSE_2_REG = 0x010F0022ull;
+
+static const uint64_t P9N2_PERV_N0_HANG_PULSE_2_REG = 0x020F0022ull;
+
+static const uint64_t P9N2_PERV_N1_HANG_PULSE_2_REG = 0x030F0022ull;
+
+static const uint64_t P9N2_PERV_N2_HANG_PULSE_2_REG = 0x040F0022ull;
+
+static const uint64_t P9N2_PERV_N3_HANG_PULSE_2_REG = 0x050F0022ull;
+
+static const uint64_t P9N2_PERV_XB_HANG_PULSE_2_REG = 0x060F0022ull;
+
+static const uint64_t P9N2_PERV_MC01_HANG_PULSE_2_REG = 0x070F0022ull;
+
+static const uint64_t P9N2_PERV_MC23_HANG_PULSE_2_REG = 0x080F0022ull;
+
+static const uint64_t P9N2_PERV_OB0_HANG_PULSE_2_REG = 0x090F0022ull;
+
+static const uint64_t P9N2_PERV_OB3_HANG_PULSE_2_REG = 0x0C0F0022ull;
+
+static const uint64_t P9N2_PERV_PCI0_HANG_PULSE_2_REG = 0x0D0F0022ull;
+
+static const uint64_t P9N2_PERV_PCI1_HANG_PULSE_2_REG = 0x0E0F0022ull;
+
+static const uint64_t P9N2_PERV_PCI2_HANG_PULSE_2_REG = 0x0F0F0022ull;
+
+static const uint64_t P9N2_PERV_EP00_HANG_PULSE_2_REG = 0x100F0022ull;
+
+static const uint64_t P9N2_PERV_EP01_HANG_PULSE_2_REG = 0x110F0022ull;
+
+static const uint64_t P9N2_PERV_EP02_HANG_PULSE_2_REG = 0x120F0022ull;
+
+static const uint64_t P9N2_PERV_EP03_HANG_PULSE_2_REG = 0x130F0022ull;
+
+static const uint64_t P9N2_PERV_EP04_HANG_PULSE_2_REG = 0x140F0022ull;
+
+static const uint64_t P9N2_PERV_EP05_HANG_PULSE_2_REG = 0x150F0022ull;
+
+static const uint64_t P9N2_PERV_EC00_HANG_PULSE_2_REG = 0x200F0022ull;
+
+static const uint64_t P9N2_PERV_EC01_HANG_PULSE_2_REG = 0x210F0022ull;
+
+static const uint64_t P9N2_PERV_EC02_HANG_PULSE_2_REG = 0x220F0022ull;
+
+static const uint64_t P9N2_PERV_EC03_HANG_PULSE_2_REG = 0x230F0022ull;
+
+static const uint64_t P9N2_PERV_EC04_HANG_PULSE_2_REG = 0x240F0022ull;
+
+static const uint64_t P9N2_PERV_EC05_HANG_PULSE_2_REG = 0x250F0022ull;
+
+static const uint64_t P9N2_PERV_EC06_HANG_PULSE_2_REG = 0x260F0022ull;
+
+static const uint64_t P9N2_PERV_EC07_HANG_PULSE_2_REG = 0x270F0022ull;
+
+static const uint64_t P9N2_PERV_EC08_HANG_PULSE_2_REG = 0x280F0022ull;
+
+static const uint64_t P9N2_PERV_EC09_HANG_PULSE_2_REG = 0x290F0022ull;
+
+static const uint64_t P9N2_PERV_EC10_HANG_PULSE_2_REG = 0x2A0F0022ull;
+
+static const uint64_t P9N2_PERV_EC11_HANG_PULSE_2_REG = 0x2B0F0022ull;
+
+static const uint64_t P9N2_PERV_EC12_HANG_PULSE_2_REG = 0x2C0F0022ull;
+
+static const uint64_t P9N2_PERV_EC13_HANG_PULSE_2_REG = 0x2D0F0022ull;
+
+static const uint64_t P9N2_PERV_EC14_HANG_PULSE_2_REG = 0x2E0F0022ull;
+
+static const uint64_t P9N2_PERV_EC15_HANG_PULSE_2_REG = 0x2F0F0022ull;
+
+static const uint64_t P9N2_PERV_EC16_HANG_PULSE_2_REG = 0x300F0022ull;
+
+static const uint64_t P9N2_PERV_EC17_HANG_PULSE_2_REG = 0x310F0022ull;
+
+static const uint64_t P9N2_PERV_EC18_HANG_PULSE_2_REG = 0x320F0022ull;
+
+static const uint64_t P9N2_PERV_EC19_HANG_PULSE_2_REG = 0x330F0022ull;
+
+static const uint64_t P9N2_PERV_EC20_HANG_PULSE_2_REG = 0x340F0022ull;
+
+static const uint64_t P9N2_PERV_EC21_HANG_PULSE_2_REG = 0x350F0022ull;
+
+static const uint64_t P9N2_PERV_EC22_HANG_PULSE_2_REG = 0x360F0022ull;
+
+static const uint64_t P9N2_PERV_EC23_HANG_PULSE_2_REG = 0x370F0022ull;
+
+
+static const uint64_t P9N2_PERV_HANG_PULSE_3_REG = 0x000F0023ull;
+
+static const uint64_t P9N2_PERV_TP_HANG_PULSE_3_REG = 0x010F0023ull;
+
+static const uint64_t P9N2_PERV_N0_HANG_PULSE_3_REG = 0x020F0023ull;
+
+static const uint64_t P9N2_PERV_N1_HANG_PULSE_3_REG = 0x030F0023ull;
+
+static const uint64_t P9N2_PERV_N2_HANG_PULSE_3_REG = 0x040F0023ull;
+
+static const uint64_t P9N2_PERV_N3_HANG_PULSE_3_REG = 0x050F0023ull;
+
+static const uint64_t P9N2_PERV_XB_HANG_PULSE_3_REG = 0x060F0023ull;
+
+static const uint64_t P9N2_PERV_MC01_HANG_PULSE_3_REG = 0x070F0023ull;
+
+static const uint64_t P9N2_PERV_MC23_HANG_PULSE_3_REG = 0x080F0023ull;
+
+static const uint64_t P9N2_PERV_OB0_HANG_PULSE_3_REG = 0x090F0023ull;
+
+static const uint64_t P9N2_PERV_OB3_HANG_PULSE_3_REG = 0x0C0F0023ull;
+
+static const uint64_t P9N2_PERV_PCI0_HANG_PULSE_3_REG = 0x0D0F0023ull;
+
+static const uint64_t P9N2_PERV_PCI1_HANG_PULSE_3_REG = 0x0E0F0023ull;
+
+static const uint64_t P9N2_PERV_PCI2_HANG_PULSE_3_REG = 0x0F0F0023ull;
+
+static const uint64_t P9N2_PERV_EP00_HANG_PULSE_3_REG = 0x100F0023ull;
+
+static const uint64_t P9N2_PERV_EP01_HANG_PULSE_3_REG = 0x110F0023ull;
+
+static const uint64_t P9N2_PERV_EP02_HANG_PULSE_3_REG = 0x120F0023ull;
+
+static const uint64_t P9N2_PERV_EP03_HANG_PULSE_3_REG = 0x130F0023ull;
+
+static const uint64_t P9N2_PERV_EP04_HANG_PULSE_3_REG = 0x140F0023ull;
+
+static const uint64_t P9N2_PERV_EP05_HANG_PULSE_3_REG = 0x150F0023ull;
+
+static const uint64_t P9N2_PERV_EC00_HANG_PULSE_3_REG = 0x200F0023ull;
+
+static const uint64_t P9N2_PERV_EC01_HANG_PULSE_3_REG = 0x210F0023ull;
+
+static const uint64_t P9N2_PERV_EC02_HANG_PULSE_3_REG = 0x220F0023ull;
+
+static const uint64_t P9N2_PERV_EC03_HANG_PULSE_3_REG = 0x230F0023ull;
+
+static const uint64_t P9N2_PERV_EC04_HANG_PULSE_3_REG = 0x240F0023ull;
+
+static const uint64_t P9N2_PERV_EC05_HANG_PULSE_3_REG = 0x250F0023ull;
+
+static const uint64_t P9N2_PERV_EC06_HANG_PULSE_3_REG = 0x260F0023ull;
+
+static const uint64_t P9N2_PERV_EC07_HANG_PULSE_3_REG = 0x270F0023ull;
+
+static const uint64_t P9N2_PERV_EC08_HANG_PULSE_3_REG = 0x280F0023ull;
+
+static const uint64_t P9N2_PERV_EC09_HANG_PULSE_3_REG = 0x290F0023ull;
+
+static const uint64_t P9N2_PERV_EC10_HANG_PULSE_3_REG = 0x2A0F0023ull;
+
+static const uint64_t P9N2_PERV_EC11_HANG_PULSE_3_REG = 0x2B0F0023ull;
+
+static const uint64_t P9N2_PERV_EC12_HANG_PULSE_3_REG = 0x2C0F0023ull;
+
+static const uint64_t P9N2_PERV_EC13_HANG_PULSE_3_REG = 0x2D0F0023ull;
+
+static const uint64_t P9N2_PERV_EC14_HANG_PULSE_3_REG = 0x2E0F0023ull;
+
+static const uint64_t P9N2_PERV_EC15_HANG_PULSE_3_REG = 0x2F0F0023ull;
+
+static const uint64_t P9N2_PERV_EC16_HANG_PULSE_3_REG = 0x300F0023ull;
+
+static const uint64_t P9N2_PERV_EC17_HANG_PULSE_3_REG = 0x310F0023ull;
+
+static const uint64_t P9N2_PERV_EC18_HANG_PULSE_3_REG = 0x320F0023ull;
+
+static const uint64_t P9N2_PERV_EC19_HANG_PULSE_3_REG = 0x330F0023ull;
+
+static const uint64_t P9N2_PERV_EC20_HANG_PULSE_3_REG = 0x340F0023ull;
+
+static const uint64_t P9N2_PERV_EC21_HANG_PULSE_3_REG = 0x350F0023ull;
+
+static const uint64_t P9N2_PERV_EC22_HANG_PULSE_3_REG = 0x360F0023ull;
+
+static const uint64_t P9N2_PERV_EC23_HANG_PULSE_3_REG = 0x370F0023ull;
+
+
+static const uint64_t P9N2_PERV_HANG_PULSE_4_REG = 0x000F0024ull;
+
+static const uint64_t P9N2_PERV_TP_HANG_PULSE_4_REG = 0x010F0024ull;
+
+static const uint64_t P9N2_PERV_N0_HANG_PULSE_4_REG = 0x020F0024ull;
+
+static const uint64_t P9N2_PERV_N1_HANG_PULSE_4_REG = 0x030F0024ull;
+
+static const uint64_t P9N2_PERV_N2_HANG_PULSE_4_REG = 0x040F0024ull;
+
+static const uint64_t P9N2_PERV_N3_HANG_PULSE_4_REG = 0x050F0024ull;
+
+static const uint64_t P9N2_PERV_XB_HANG_PULSE_4_REG = 0x060F0024ull;
+
+static const uint64_t P9N2_PERV_MC01_HANG_PULSE_4_REG = 0x070F0024ull;
+
+static const uint64_t P9N2_PERV_MC23_HANG_PULSE_4_REG = 0x080F0024ull;
+
+static const uint64_t P9N2_PERV_OB0_HANG_PULSE_4_REG = 0x090F0024ull;
+
+static const uint64_t P9N2_PERV_OB3_HANG_PULSE_4_REG = 0x0C0F0024ull;
+
+static const uint64_t P9N2_PERV_PCI0_HANG_PULSE_4_REG = 0x0D0F0024ull;
+
+static const uint64_t P9N2_PERV_PCI1_HANG_PULSE_4_REG = 0x0E0F0024ull;
+
+static const uint64_t P9N2_PERV_PCI2_HANG_PULSE_4_REG = 0x0F0F0024ull;
+
+static const uint64_t P9N2_PERV_EP00_HANG_PULSE_4_REG = 0x100F0024ull;
+
+static const uint64_t P9N2_PERV_EP01_HANG_PULSE_4_REG = 0x110F0024ull;
+
+static const uint64_t P9N2_PERV_EP02_HANG_PULSE_4_REG = 0x120F0024ull;
+
+static const uint64_t P9N2_PERV_EP03_HANG_PULSE_4_REG = 0x130F0024ull;
+
+static const uint64_t P9N2_PERV_EP04_HANG_PULSE_4_REG = 0x140F0024ull;
+
+static const uint64_t P9N2_PERV_EP05_HANG_PULSE_4_REG = 0x150F0024ull;
+
+static const uint64_t P9N2_PERV_EC00_HANG_PULSE_4_REG = 0x200F0024ull;
+
+static const uint64_t P9N2_PERV_EC01_HANG_PULSE_4_REG = 0x210F0024ull;
+
+static const uint64_t P9N2_PERV_EC02_HANG_PULSE_4_REG = 0x220F0024ull;
+
+static const uint64_t P9N2_PERV_EC03_HANG_PULSE_4_REG = 0x230F0024ull;
+
+static const uint64_t P9N2_PERV_EC04_HANG_PULSE_4_REG = 0x240F0024ull;
+
+static const uint64_t P9N2_PERV_EC05_HANG_PULSE_4_REG = 0x250F0024ull;
+
+static const uint64_t P9N2_PERV_EC06_HANG_PULSE_4_REG = 0x260F0024ull;
+
+static const uint64_t P9N2_PERV_EC07_HANG_PULSE_4_REG = 0x270F0024ull;
+
+static const uint64_t P9N2_PERV_EC08_HANG_PULSE_4_REG = 0x280F0024ull;
+
+static const uint64_t P9N2_PERV_EC09_HANG_PULSE_4_REG = 0x290F0024ull;
+
+static const uint64_t P9N2_PERV_EC10_HANG_PULSE_4_REG = 0x2A0F0024ull;
+
+static const uint64_t P9N2_PERV_EC11_HANG_PULSE_4_REG = 0x2B0F0024ull;
+
+static const uint64_t P9N2_PERV_EC12_HANG_PULSE_4_REG = 0x2C0F0024ull;
+
+static const uint64_t P9N2_PERV_EC13_HANG_PULSE_4_REG = 0x2D0F0024ull;
+
+static const uint64_t P9N2_PERV_EC14_HANG_PULSE_4_REG = 0x2E0F0024ull;
+
+static const uint64_t P9N2_PERV_EC15_HANG_PULSE_4_REG = 0x2F0F0024ull;
+
+static const uint64_t P9N2_PERV_EC16_HANG_PULSE_4_REG = 0x300F0024ull;
+
+static const uint64_t P9N2_PERV_EC17_HANG_PULSE_4_REG = 0x310F0024ull;
+
+static const uint64_t P9N2_PERV_EC18_HANG_PULSE_4_REG = 0x320F0024ull;
+
+static const uint64_t P9N2_PERV_EC19_HANG_PULSE_4_REG = 0x330F0024ull;
+
+static const uint64_t P9N2_PERV_EC20_HANG_PULSE_4_REG = 0x340F0024ull;
+
+static const uint64_t P9N2_PERV_EC21_HANG_PULSE_4_REG = 0x350F0024ull;
+
+static const uint64_t P9N2_PERV_EC22_HANG_PULSE_4_REG = 0x360F0024ull;
+
+static const uint64_t P9N2_PERV_EC23_HANG_PULSE_4_REG = 0x370F0024ull;
+
+
+static const uint64_t P9N2_PERV_HANG_PULSE_5_REG = 0x000F0025ull;
+
+static const uint64_t P9N2_PERV_TP_HANG_PULSE_5_REG = 0x010F0025ull;
+
+static const uint64_t P9N2_PERV_N0_HANG_PULSE_5_REG = 0x020F0025ull;
+
+static const uint64_t P9N2_PERV_N1_HANG_PULSE_5_REG = 0x030F0025ull;
+
+static const uint64_t P9N2_PERV_N2_HANG_PULSE_5_REG = 0x040F0025ull;
+
+static const uint64_t P9N2_PERV_N3_HANG_PULSE_5_REG = 0x050F0025ull;
+
+static const uint64_t P9N2_PERV_XB_HANG_PULSE_5_REG = 0x060F0025ull;
+
+static const uint64_t P9N2_PERV_MC01_HANG_PULSE_5_REG = 0x070F0025ull;
+
+static const uint64_t P9N2_PERV_MC23_HANG_PULSE_5_REG = 0x080F0025ull;
+
+static const uint64_t P9N2_PERV_OB0_HANG_PULSE_5_REG = 0x090F0025ull;
+
+static const uint64_t P9N2_PERV_OB3_HANG_PULSE_5_REG = 0x0C0F0025ull;
+
+static const uint64_t P9N2_PERV_PCI0_HANG_PULSE_5_REG = 0x0D0F0025ull;
+
+static const uint64_t P9N2_PERV_PCI1_HANG_PULSE_5_REG = 0x0E0F0025ull;
+
+static const uint64_t P9N2_PERV_PCI2_HANG_PULSE_5_REG = 0x0F0F0025ull;
+
+static const uint64_t P9N2_PERV_EP00_HANG_PULSE_5_REG = 0x100F0025ull;
+
+static const uint64_t P9N2_PERV_EP01_HANG_PULSE_5_REG = 0x110F0025ull;
+
+static const uint64_t P9N2_PERV_EP02_HANG_PULSE_5_REG = 0x120F0025ull;
+
+static const uint64_t P9N2_PERV_EP03_HANG_PULSE_5_REG = 0x130F0025ull;
+
+static const uint64_t P9N2_PERV_EP04_HANG_PULSE_5_REG = 0x140F0025ull;
+
+static const uint64_t P9N2_PERV_EP05_HANG_PULSE_5_REG = 0x150F0025ull;
+
+static const uint64_t P9N2_PERV_EC00_HANG_PULSE_5_REG = 0x200F0025ull;
+
+static const uint64_t P9N2_PERV_EC01_HANG_PULSE_5_REG = 0x210F0025ull;
+
+static const uint64_t P9N2_PERV_EC02_HANG_PULSE_5_REG = 0x220F0025ull;
+
+static const uint64_t P9N2_PERV_EC03_HANG_PULSE_5_REG = 0x230F0025ull;
+
+static const uint64_t P9N2_PERV_EC04_HANG_PULSE_5_REG = 0x240F0025ull;
+
+static const uint64_t P9N2_PERV_EC05_HANG_PULSE_5_REG = 0x250F0025ull;
+
+static const uint64_t P9N2_PERV_EC06_HANG_PULSE_5_REG = 0x260F0025ull;
+
+static const uint64_t P9N2_PERV_EC07_HANG_PULSE_5_REG = 0x270F0025ull;
+
+static const uint64_t P9N2_PERV_EC08_HANG_PULSE_5_REG = 0x280F0025ull;
+
+static const uint64_t P9N2_PERV_EC09_HANG_PULSE_5_REG = 0x290F0025ull;
+
+static const uint64_t P9N2_PERV_EC10_HANG_PULSE_5_REG = 0x2A0F0025ull;
+
+static const uint64_t P9N2_PERV_EC11_HANG_PULSE_5_REG = 0x2B0F0025ull;
+
+static const uint64_t P9N2_PERV_EC12_HANG_PULSE_5_REG = 0x2C0F0025ull;
+
+static const uint64_t P9N2_PERV_EC13_HANG_PULSE_5_REG = 0x2D0F0025ull;
+
+static const uint64_t P9N2_PERV_EC14_HANG_PULSE_5_REG = 0x2E0F0025ull;
+
+static const uint64_t P9N2_PERV_EC15_HANG_PULSE_5_REG = 0x2F0F0025ull;
+
+static const uint64_t P9N2_PERV_EC16_HANG_PULSE_5_REG = 0x300F0025ull;
+
+static const uint64_t P9N2_PERV_EC17_HANG_PULSE_5_REG = 0x310F0025ull;
+
+static const uint64_t P9N2_PERV_EC18_HANG_PULSE_5_REG = 0x320F0025ull;
+
+static const uint64_t P9N2_PERV_EC19_HANG_PULSE_5_REG = 0x330F0025ull;
+
+static const uint64_t P9N2_PERV_EC20_HANG_PULSE_5_REG = 0x340F0025ull;
+
+static const uint64_t P9N2_PERV_EC21_HANG_PULSE_5_REG = 0x350F0025ull;
+
+static const uint64_t P9N2_PERV_EC22_HANG_PULSE_5_REG = 0x360F0025ull;
+
+static const uint64_t P9N2_PERV_EC23_HANG_PULSE_5_REG = 0x370F0025ull;
+
+
+static const uint64_t P9N2_PERV_HANG_PULSE_6_REG = 0x000F0026ull;
+
+static const uint64_t P9N2_PERV_TP_HANG_PULSE_6_REG = 0x010F0026ull;
+
+static const uint64_t P9N2_PERV_N0_HANG_PULSE_6_REG = 0x020F0026ull;
+
+static const uint64_t P9N2_PERV_N1_HANG_PULSE_6_REG = 0x030F0026ull;
+
+static const uint64_t P9N2_PERV_N2_HANG_PULSE_6_REG = 0x040F0026ull;
+
+static const uint64_t P9N2_PERV_N3_HANG_PULSE_6_REG = 0x050F0026ull;
+
+static const uint64_t P9N2_PERV_XB_HANG_PULSE_6_REG = 0x060F0026ull;
+
+static const uint64_t P9N2_PERV_MC01_HANG_PULSE_6_REG = 0x070F0026ull;
+
+static const uint64_t P9N2_PERV_MC23_HANG_PULSE_6_REG = 0x080F0026ull;
+
+static const uint64_t P9N2_PERV_OB0_HANG_PULSE_6_REG = 0x090F0026ull;
+
+static const uint64_t P9N2_PERV_OB3_HANG_PULSE_6_REG = 0x0C0F0026ull;
+
+static const uint64_t P9N2_PERV_PCI0_HANG_PULSE_6_REG = 0x0D0F0026ull;
+
+static const uint64_t P9N2_PERV_PCI1_HANG_PULSE_6_REG = 0x0E0F0026ull;
+
+static const uint64_t P9N2_PERV_PCI2_HANG_PULSE_6_REG = 0x0F0F0026ull;
+
+static const uint64_t P9N2_PERV_EP00_HANG_PULSE_6_REG = 0x100F0026ull;
+
+static const uint64_t P9N2_PERV_EP01_HANG_PULSE_6_REG = 0x110F0026ull;
+
+static const uint64_t P9N2_PERV_EP02_HANG_PULSE_6_REG = 0x120F0026ull;
+
+static const uint64_t P9N2_PERV_EP03_HANG_PULSE_6_REG = 0x130F0026ull;
+
+static const uint64_t P9N2_PERV_EP04_HANG_PULSE_6_REG = 0x140F0026ull;
+
+static const uint64_t P9N2_PERV_EP05_HANG_PULSE_6_REG = 0x150F0026ull;
+
+static const uint64_t P9N2_PERV_EC00_HANG_PULSE_6_REG = 0x200F0026ull;
+
+static const uint64_t P9N2_PERV_EC01_HANG_PULSE_6_REG = 0x210F0026ull;
+
+static const uint64_t P9N2_PERV_EC02_HANG_PULSE_6_REG = 0x220F0026ull;
+
+static const uint64_t P9N2_PERV_EC03_HANG_PULSE_6_REG = 0x230F0026ull;
+
+static const uint64_t P9N2_PERV_EC04_HANG_PULSE_6_REG = 0x240F0026ull;
+
+static const uint64_t P9N2_PERV_EC05_HANG_PULSE_6_REG = 0x250F0026ull;
+
+static const uint64_t P9N2_PERV_EC06_HANG_PULSE_6_REG = 0x260F0026ull;
+
+static const uint64_t P9N2_PERV_EC07_HANG_PULSE_6_REG = 0x270F0026ull;
+
+static const uint64_t P9N2_PERV_EC08_HANG_PULSE_6_REG = 0x280F0026ull;
+
+static const uint64_t P9N2_PERV_EC09_HANG_PULSE_6_REG = 0x290F0026ull;
+
+static const uint64_t P9N2_PERV_EC10_HANG_PULSE_6_REG = 0x2A0F0026ull;
+
+static const uint64_t P9N2_PERV_EC11_HANG_PULSE_6_REG = 0x2B0F0026ull;
+
+static const uint64_t P9N2_PERV_EC12_HANG_PULSE_6_REG = 0x2C0F0026ull;
+
+static const uint64_t P9N2_PERV_EC13_HANG_PULSE_6_REG = 0x2D0F0026ull;
+
+static const uint64_t P9N2_PERV_EC14_HANG_PULSE_6_REG = 0x2E0F0026ull;
+
+static const uint64_t P9N2_PERV_EC15_HANG_PULSE_6_REG = 0x2F0F0026ull;
+
+static const uint64_t P9N2_PERV_EC16_HANG_PULSE_6_REG = 0x300F0026ull;
+
+static const uint64_t P9N2_PERV_EC17_HANG_PULSE_6_REG = 0x310F0026ull;
+
+static const uint64_t P9N2_PERV_EC18_HANG_PULSE_6_REG = 0x320F0026ull;
+
+static const uint64_t P9N2_PERV_EC19_HANG_PULSE_6_REG = 0x330F0026ull;
+
+static const uint64_t P9N2_PERV_EC20_HANG_PULSE_6_REG = 0x340F0026ull;
+
+static const uint64_t P9N2_PERV_EC21_HANG_PULSE_6_REG = 0x350F0026ull;
+
+static const uint64_t P9N2_PERV_EC22_HANG_PULSE_6_REG = 0x360F0026ull;
+
+static const uint64_t P9N2_PERV_EC23_HANG_PULSE_6_REG = 0x370F0026ull;
+
+
+static const uint64_t P9N2_PERV_HEARTBEAT_REG = 0x000F0018ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_PERV_TP_HEARTBEAT_REG = 0x010F0018ull;
+
+static const uint64_t P9N2_PERV_N0_HEARTBEAT_REG = 0x020F0018ull;
+
+static const uint64_t P9N2_PERV_N1_HEARTBEAT_REG = 0x030F0018ull;
+
+static const uint64_t P9N2_PERV_N2_HEARTBEAT_REG = 0x040F0018ull;
+
+static const uint64_t P9N2_PERV_N3_HEARTBEAT_REG = 0x050F0018ull;
+
+static const uint64_t P9N2_PERV_XB_HEARTBEAT_REG = 0x060F0018ull;
+
+static const uint64_t P9N2_PERV_MC01_HEARTBEAT_REG = 0x070F0018ull;
+
+static const uint64_t P9N2_PERV_MC23_HEARTBEAT_REG = 0x080F0018ull;
+
+static const uint64_t P9N2_PERV_OB0_HEARTBEAT_REG = 0x090F0018ull;
+
+static const uint64_t P9N2_PERV_OB3_HEARTBEAT_REG = 0x0C0F0018ull;
+
+static const uint64_t P9N2_PERV_PCI0_HEARTBEAT_REG = 0x0D0F0018ull;
+
+static const uint64_t P9N2_PERV_PCI1_HEARTBEAT_REG = 0x0E0F0018ull;
+
+static const uint64_t P9N2_PERV_PCI2_HEARTBEAT_REG = 0x0F0F0018ull;
+
+static const uint64_t P9N2_PERV_EP00_HEARTBEAT_REG = 0x100F0018ull;
+
+static const uint64_t P9N2_PERV_EP01_HEARTBEAT_REG = 0x110F0018ull;
+
+static const uint64_t P9N2_PERV_EP02_HEARTBEAT_REG = 0x120F0018ull;
+
+static const uint64_t P9N2_PERV_EP03_HEARTBEAT_REG = 0x130F0018ull;
+
+static const uint64_t P9N2_PERV_EP04_HEARTBEAT_REG = 0x140F0018ull;
+
+static const uint64_t P9N2_PERV_EP05_HEARTBEAT_REG = 0x150F0018ull;
+
+static const uint64_t P9N2_PERV_EC00_HEARTBEAT_REG = 0x200F0018ull;
+
+static const uint64_t P9N2_PERV_EC01_HEARTBEAT_REG = 0x210F0018ull;
+
+static const uint64_t P9N2_PERV_EC02_HEARTBEAT_REG = 0x220F0018ull;
+
+static const uint64_t P9N2_PERV_EC03_HEARTBEAT_REG = 0x230F0018ull;
+
+static const uint64_t P9N2_PERV_EC04_HEARTBEAT_REG = 0x240F0018ull;
+
+static const uint64_t P9N2_PERV_EC05_HEARTBEAT_REG = 0x250F0018ull;
+
+static const uint64_t P9N2_PERV_EC06_HEARTBEAT_REG = 0x260F0018ull;
+
+static const uint64_t P9N2_PERV_EC07_HEARTBEAT_REG = 0x270F0018ull;
+
+static const uint64_t P9N2_PERV_EC08_HEARTBEAT_REG = 0x280F0018ull;
+
+static const uint64_t P9N2_PERV_EC09_HEARTBEAT_REG = 0x290F0018ull;
+
+static const uint64_t P9N2_PERV_EC10_HEARTBEAT_REG = 0x2A0F0018ull;
+
+static const uint64_t P9N2_PERV_EC11_HEARTBEAT_REG = 0x2B0F0018ull;
+
+static const uint64_t P9N2_PERV_EC12_HEARTBEAT_REG = 0x2C0F0018ull;
+
+static const uint64_t P9N2_PERV_EC13_HEARTBEAT_REG = 0x2D0F0018ull;
+
+static const uint64_t P9N2_PERV_EC14_HEARTBEAT_REG = 0x2E0F0018ull;
+
+static const uint64_t P9N2_PERV_EC15_HEARTBEAT_REG = 0x2F0F0018ull;
+
+static const uint64_t P9N2_PERV_EC16_HEARTBEAT_REG = 0x300F0018ull;
+
+static const uint64_t P9N2_PERV_EC17_HEARTBEAT_REG = 0x310F0018ull;
+
+static const uint64_t P9N2_PERV_EC18_HEARTBEAT_REG = 0x320F0018ull;
+
+static const uint64_t P9N2_PERV_EC19_HEARTBEAT_REG = 0x330F0018ull;
+
+static const uint64_t P9N2_PERV_EC20_HEARTBEAT_REG = 0x340F0018ull;
+
+static const uint64_t P9N2_PERV_EC21_HEARTBEAT_REG = 0x350F0018ull;
+
+static const uint64_t P9N2_PERV_EC22_HEARTBEAT_REG = 0x360F0018ull;
+
+static const uint64_t P9N2_PERV_EC23_HEARTBEAT_REG = 0x370F0018ull;
+
+
+static const uint64_t P9N2_PERV_HOSTATTN = 0x00040009ull;
+
+static const uint64_t P9N2_PERV_TP_HOSTATTN = 0x01040009ull;
+
+static const uint64_t P9N2_PERV_N0_HOSTATTN = 0x02040009ull;
+
+static const uint64_t P9N2_PERV_N1_HOSTATTN = 0x03040009ull;
+
+static const uint64_t P9N2_PERV_N2_HOSTATTN = 0x04040009ull;
+
+static const uint64_t P9N2_PERV_N3_HOSTATTN = 0x05040009ull;
+
+static const uint64_t P9N2_PERV_XB_HOSTATTN = 0x06040009ull;
+
+static const uint64_t P9N2_PERV_MC01_HOSTATTN = 0x07040009ull;
+
+static const uint64_t P9N2_PERV_MC23_HOSTATTN = 0x08040009ull;
+
+static const uint64_t P9N2_PERV_OB0_HOSTATTN = 0x09040009ull;
+
+static const uint64_t P9N2_PERV_OB3_HOSTATTN = 0x0C040009ull;
+
+static const uint64_t P9N2_PERV_PCI0_HOSTATTN = 0x0D040009ull;
+
+static const uint64_t P9N2_PERV_PCI1_HOSTATTN = 0x0E040009ull;
+
+static const uint64_t P9N2_PERV_PCI2_HOSTATTN = 0x0F040009ull;
+
+static const uint64_t P9N2_PERV_EP00_HOSTATTN = 0x10040009ull;
+
+static const uint64_t P9N2_PERV_EP01_HOSTATTN = 0x11040009ull;
+
+static const uint64_t P9N2_PERV_EP02_HOSTATTN = 0x12040009ull;
+
+static const uint64_t P9N2_PERV_EP03_HOSTATTN = 0x13040009ull;
+
+static const uint64_t P9N2_PERV_EP04_HOSTATTN = 0x14040009ull;
+
+static const uint64_t P9N2_PERV_EP05_HOSTATTN = 0x15040009ull;
+
+static const uint64_t P9N2_PERV_EC00_HOSTATTN = 0x20040009ull;
+
+static const uint64_t P9N2_PERV_EC01_HOSTATTN = 0x21040009ull;
+
+static const uint64_t P9N2_PERV_EC02_HOSTATTN = 0x22040009ull;
+
+static const uint64_t P9N2_PERV_EC03_HOSTATTN = 0x23040009ull;
+
+static const uint64_t P9N2_PERV_EC04_HOSTATTN = 0x24040009ull;
+
+static const uint64_t P9N2_PERV_EC05_HOSTATTN = 0x25040009ull;
+
+static const uint64_t P9N2_PERV_EC06_HOSTATTN = 0x26040009ull;
+
+static const uint64_t P9N2_PERV_EC07_HOSTATTN = 0x27040009ull;
+
+static const uint64_t P9N2_PERV_EC08_HOSTATTN = 0x28040009ull;
+
+static const uint64_t P9N2_PERV_EC09_HOSTATTN = 0x29040009ull;
+
+static const uint64_t P9N2_PERV_EC10_HOSTATTN = 0x2A040009ull;
+
+static const uint64_t P9N2_PERV_EC11_HOSTATTN = 0x2B040009ull;
+
+static const uint64_t P9N2_PERV_EC12_HOSTATTN = 0x2C040009ull;
+
+static const uint64_t P9N2_PERV_EC13_HOSTATTN = 0x2D040009ull;
+
+static const uint64_t P9N2_PERV_EC14_HOSTATTN = 0x2E040009ull;
+
+static const uint64_t P9N2_PERV_EC15_HOSTATTN = 0x2F040009ull;
+
+static const uint64_t P9N2_PERV_EC16_HOSTATTN = 0x30040009ull;
+
+static const uint64_t P9N2_PERV_EC17_HOSTATTN = 0x31040009ull;
+
+static const uint64_t P9N2_PERV_EC18_HOSTATTN = 0x32040009ull;
+
+static const uint64_t P9N2_PERV_EC19_HOSTATTN = 0x33040009ull;
+
+static const uint64_t P9N2_PERV_EC20_HOSTATTN = 0x34040009ull;
+
+static const uint64_t P9N2_PERV_EC21_HOSTATTN = 0x35040009ull;
+
+static const uint64_t P9N2_PERV_EC22_HOSTATTN = 0x36040009ull;
+
+static const uint64_t P9N2_PERV_EC23_HOSTATTN = 0x37040009ull;
+
+
+static const uint64_t P9N2_PERV_HOSTATTN_MASK = 0x0004001Aull;
+
+static const uint64_t P9N2_PERV_TP_HOSTATTN_MASK = 0x0104001Aull;
+
+static const uint64_t P9N2_PERV_N0_HOSTATTN_MASK = 0x0204001Aull;
+
+static const uint64_t P9N2_PERV_N1_HOSTATTN_MASK = 0x0304001Aull;
+
+static const uint64_t P9N2_PERV_N2_HOSTATTN_MASK = 0x0404001Aull;
+
+static const uint64_t P9N2_PERV_N3_HOSTATTN_MASK = 0x0504001Aull;
+
+static const uint64_t P9N2_PERV_XB_HOSTATTN_MASK = 0x0604001Aull;
+
+static const uint64_t P9N2_PERV_MC01_HOSTATTN_MASK = 0x0704001Aull;
+
+static const uint64_t P9N2_PERV_MC23_HOSTATTN_MASK = 0x0804001Aull;
+
+static const uint64_t P9N2_PERV_OB0_HOSTATTN_MASK = 0x0904001Aull;
+
+static const uint64_t P9N2_PERV_OB3_HOSTATTN_MASK = 0x0C04001Aull;
+
+static const uint64_t P9N2_PERV_PCI0_HOSTATTN_MASK = 0x0D04001Aull;
+
+static const uint64_t P9N2_PERV_PCI1_HOSTATTN_MASK = 0x0E04001Aull;
+
+static const uint64_t P9N2_PERV_PCI2_HOSTATTN_MASK = 0x0F04001Aull;
+
+static const uint64_t P9N2_PERV_EP00_HOSTATTN_MASK = 0x1004001Aull;
+
+static const uint64_t P9N2_PERV_EP01_HOSTATTN_MASK = 0x1104001Aull;
+
+static const uint64_t P9N2_PERV_EP02_HOSTATTN_MASK = 0x1204001Aull;
+
+static const uint64_t P9N2_PERV_EP03_HOSTATTN_MASK = 0x1304001Aull;
+
+static const uint64_t P9N2_PERV_EP04_HOSTATTN_MASK = 0x1404001Aull;
+
+static const uint64_t P9N2_PERV_EP05_HOSTATTN_MASK = 0x1504001Aull;
+
+static const uint64_t P9N2_PERV_EC00_HOSTATTN_MASK = 0x2004001Aull;
+
+static const uint64_t P9N2_PERV_EC01_HOSTATTN_MASK = 0x2104001Aull;
+
+static const uint64_t P9N2_PERV_EC02_HOSTATTN_MASK = 0x2204001Aull;
+
+static const uint64_t P9N2_PERV_EC03_HOSTATTN_MASK = 0x2304001Aull;
+
+static const uint64_t P9N2_PERV_EC04_HOSTATTN_MASK = 0x2404001Aull;
+
+static const uint64_t P9N2_PERV_EC05_HOSTATTN_MASK = 0x2504001Aull;
+
+static const uint64_t P9N2_PERV_EC06_HOSTATTN_MASK = 0x2604001Aull;
+
+static const uint64_t P9N2_PERV_EC07_HOSTATTN_MASK = 0x2704001Aull;
+
+static const uint64_t P9N2_PERV_EC08_HOSTATTN_MASK = 0x2804001Aull;
+
+static const uint64_t P9N2_PERV_EC09_HOSTATTN_MASK = 0x2904001Aull;
+
+static const uint64_t P9N2_PERV_EC10_HOSTATTN_MASK = 0x2A04001Aull;
+
+static const uint64_t P9N2_PERV_EC11_HOSTATTN_MASK = 0x2B04001Aull;
+
+static const uint64_t P9N2_PERV_EC12_HOSTATTN_MASK = 0x2C04001Aull;
+
+static const uint64_t P9N2_PERV_EC13_HOSTATTN_MASK = 0x2D04001Aull;
+
+static const uint64_t P9N2_PERV_EC14_HOSTATTN_MASK = 0x2E04001Aull;
+
+static const uint64_t P9N2_PERV_EC15_HOSTATTN_MASK = 0x2F04001Aull;
+
+static const uint64_t P9N2_PERV_EC16_HOSTATTN_MASK = 0x3004001Aull;
+
+static const uint64_t P9N2_PERV_EC17_HOSTATTN_MASK = 0x3104001Aull;
+
+static const uint64_t P9N2_PERV_EC18_HOSTATTN_MASK = 0x3204001Aull;
+
+static const uint64_t P9N2_PERV_EC19_HOSTATTN_MASK = 0x3304001Aull;
+
+static const uint64_t P9N2_PERV_EC20_HOSTATTN_MASK = 0x3404001Aull;
+
+static const uint64_t P9N2_PERV_EC21_HOSTATTN_MASK = 0x3504001Aull;
+
+static const uint64_t P9N2_PERV_EC22_HOSTATTN_MASK = 0x3604001Aull;
+
+static const uint64_t P9N2_PERV_EC23_HOSTATTN_MASK = 0x3704001Aull;
+
+
+static const uint64_t P9N2_PERV_HOST_MASK_REG = 0x000F0033ull;
+
+static const uint64_t P9N2_PERV_PIB_HOST_MASK_REG = 0x000F0033ull;
+
+
+static const uint64_t P9N2_PERV_0_FSII2C_I2C_BUSY_REGISTER_A = 0x0000180Aull;
+
+static const uint32_t P9N2_PERV_FSII2C_I2C_BUSY_REGISTER_A = 0x0000180Aull;
+
+
+static const uint64_t P9N2_PERV_IGNORE_PAR_REG = 0x000F001Cull;
+
+static const uint64_t P9N2_PERV_PIB_IGNORE_PAR_REG = 0x000F001Cull;
+
+
+static const uint64_t P9N2_PERV_0_FSII2C_IMM_RESET_ERR_A = 0x00001808ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint32_t P9N2_PERV_FSII2C_IMM_RESET_ERR_A = 0x00001808ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+
+static const uint64_t P9N2_PERV_0_FSII2C_IMM_RESET_I2C_A = 0x00001807ull;
+
+static const uint32_t P9N2_PERV_FSII2C_IMM_RESET_I2C_A = 0x00001807ull;
+
+
+static const uint64_t P9N2_PERV_0_FSII2C_IMM_RESET_S_SCL_A = 0x0000180Bull;
+
+static const uint32_t P9N2_PERV_FSII2C_IMM_RESET_S_SCL_A = 0x0000180Bull;
+
+
+static const uint64_t P9N2_PERV_0_FSII2C_IMM_RESET_S_SDA_A = 0x0000180Dull;
+
+static const uint32_t P9N2_PERV_FSII2C_IMM_RESET_S_SDA_A = 0x0000180Dull;
+
+
+static const uint64_t P9N2_PERV_0_FSII2C_IMM_SET_S_SCL_A = 0x00001809ull;
+
+static const uint32_t P9N2_PERV_FSII2C_IMM_SET_S_SCL_A = 0x00001809ull;
+
+
+static const uint64_t P9N2_PERV_0_FSII2C_IMM_SET_S_SDA_A = 0x0000180Cull;
+
+static const uint32_t P9N2_PERV_FSII2C_IMM_SET_S_SDA_A = 0x0000180Cull;
+
+
+static const uint64_t P9N2_PERV_INJECT_REG = 0x00050011ull;
+
+static const uint64_t P9N2_PERV_TP_INJECT_REG = 0x01050011ull;
+
+static const uint64_t P9N2_PERV_N0_INJECT_REG = 0x02050011ull;
+
+static const uint64_t P9N2_PERV_N1_INJECT_REG = 0x03050011ull;
+
+static const uint64_t P9N2_PERV_N2_INJECT_REG = 0x04050011ull;
+
+static const uint64_t P9N2_PERV_N3_INJECT_REG = 0x05050011ull;
+
+static const uint64_t P9N2_PERV_XB_INJECT_REG = 0x06050011ull;
+
+static const uint64_t P9N2_PERV_MC01_INJECT_REG = 0x07050011ull;
+
+static const uint64_t P9N2_PERV_MC23_INJECT_REG = 0x08050011ull;
+
+static const uint64_t P9N2_PERV_OB0_INJECT_REG = 0x09050011ull;
+
+static const uint64_t P9N2_PERV_OB3_INJECT_REG = 0x0C050011ull;
+
+static const uint64_t P9N2_PERV_PCI0_INJECT_REG = 0x0D050011ull;
+
+static const uint64_t P9N2_PERV_PCI1_INJECT_REG = 0x0E050011ull;
+
+static const uint64_t P9N2_PERV_PCI2_INJECT_REG = 0x0F050011ull;
+
+static const uint64_t P9N2_PERV_EP00_INJECT_REG = 0x10050011ull;
+
+static const uint64_t P9N2_PERV_EP01_INJECT_REG = 0x11050011ull;
+
+static const uint64_t P9N2_PERV_EP02_INJECT_REG = 0x12050011ull;
+
+static const uint64_t P9N2_PERV_EP03_INJECT_REG = 0x13050011ull;
+
+static const uint64_t P9N2_PERV_EP04_INJECT_REG = 0x14050011ull;
+
+static const uint64_t P9N2_PERV_EP05_INJECT_REG = 0x15050011ull;
+
+static const uint64_t P9N2_PERV_EC00_INJECT_REG = 0x20050011ull;
+
+static const uint64_t P9N2_PERV_EC01_INJECT_REG = 0x21050011ull;
+
+static const uint64_t P9N2_PERV_EC02_INJECT_REG = 0x22050011ull;
+
+static const uint64_t P9N2_PERV_EC03_INJECT_REG = 0x23050011ull;
+
+static const uint64_t P9N2_PERV_EC04_INJECT_REG = 0x24050011ull;
+
+static const uint64_t P9N2_PERV_EC05_INJECT_REG = 0x25050011ull;
+
+static const uint64_t P9N2_PERV_EC06_INJECT_REG = 0x26050011ull;
+
+static const uint64_t P9N2_PERV_EC07_INJECT_REG = 0x27050011ull;
+
+static const uint64_t P9N2_PERV_EC08_INJECT_REG = 0x28050011ull;
+
+static const uint64_t P9N2_PERV_EC09_INJECT_REG = 0x29050011ull;
+
+static const uint64_t P9N2_PERV_EC10_INJECT_REG = 0x2A050011ull;
+
+static const uint64_t P9N2_PERV_EC11_INJECT_REG = 0x2B050011ull;
+
+static const uint64_t P9N2_PERV_EC12_INJECT_REG = 0x2C050011ull;
+
+static const uint64_t P9N2_PERV_EC13_INJECT_REG = 0x2D050011ull;
+
+static const uint64_t P9N2_PERV_EC14_INJECT_REG = 0x2E050011ull;
+
+static const uint64_t P9N2_PERV_EC15_INJECT_REG = 0x2F050011ull;
+
+static const uint64_t P9N2_PERV_EC16_INJECT_REG = 0x30050011ull;
+
+static const uint64_t P9N2_PERV_EC17_INJECT_REG = 0x31050011ull;
+
+static const uint64_t P9N2_PERV_EC18_INJECT_REG = 0x32050011ull;
+
+static const uint64_t P9N2_PERV_EC19_INJECT_REG = 0x33050011ull;
+
+static const uint64_t P9N2_PERV_EC20_INJECT_REG = 0x34050011ull;
+
+static const uint64_t P9N2_PERV_EC21_INJECT_REG = 0x35050011ull;
+
+static const uint64_t P9N2_PERV_EC22_INJECT_REG = 0x36050011ull;
+
+static const uint64_t P9N2_PERV_EC23_INJECT_REG = 0x37050011ull;
+
+
+static const uint32_t P9N2_PERV_FSI2PIB_INTERRUPT_FSI = 0x0000100Bull;
+
+static const uint32_t P9N2_PERV_FSI2PIB_INTERRUPT_FSI_BYTE = 0x0000102Cull;
+
+
+static const uint64_t P9N2_PERV_INTERRUPT1_REG = 0x000F0020ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_PERV_INTERRUPT1_REG_OR = 0x000F0021ull;
+
+static const uint64_t P9N2_PERV_INTERRUPT1_REG_AND = 0x000F0022ull;
+
+static const uint64_t P9N2_PERV_PIB_INTERRUPT1_REG = 0x000F0020ull;
+
+static const uint64_t P9N2_PERV_PIB_INTERRUPT1_REG_OR = 0x000F0021ull;
+
+static const uint64_t P9N2_PERV_PIB_INTERRUPT1_REG_AND = 0x000F0022ull;
+
+
+static const uint64_t P9N2_PERV_INTERRUPT2_REG = 0x000F0023ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_PERV_INTERRUPT2_REG_OR = 0x000F0024ull;
+
+static const uint64_t P9N2_PERV_INTERRUPT2_REG_AND = 0x000F0025ull;
+
+static const uint64_t P9N2_PERV_PIB_INTERRUPT2_REG = 0x000F0023ull;
+
+static const uint64_t P9N2_PERV_PIB_INTERRUPT2_REG_OR = 0x000F0024ull;
+
+static const uint64_t P9N2_PERV_PIB_INTERRUPT2_REG_AND = 0x000F0025ull;
+
+
+static const uint64_t P9N2_PERV_INTERRUPT3_REG = 0x000F0026ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_PERV_INTERRUPT3_REG_OR = 0x000F0027ull;
+
+static const uint64_t P9N2_PERV_INTERRUPT3_REG_AND = 0x000F0028ull;
+
+static const uint64_t P9N2_PERV_PIB_INTERRUPT3_REG = 0x000F0026ull;
+
+static const uint64_t P9N2_PERV_PIB_INTERRUPT3_REG_OR = 0x000F0027ull;
+
+static const uint64_t P9N2_PERV_PIB_INTERRUPT3_REG_AND = 0x000F0028ull;
+
+
+static const uint64_t P9N2_PERV_INTERRUPT4_REG = 0x000F0029ull;
+
+static const uint64_t P9N2_PERV_INTERRUPT4_REG_OR = 0x000F002Aull;
+
+static const uint64_t P9N2_PERV_INTERRUPT4_REG_AND = 0x000F002Bull;
+
+static const uint64_t P9N2_PERV_PIB_INTERRUPT4_REG = 0x000F0029ull;
+
+static const uint64_t P9N2_PERV_PIB_INTERRUPT4_REG_OR = 0x000F002Aull;
+
+static const uint64_t P9N2_PERV_PIB_INTERRUPT4_REG_AND = 0x000F002Bull;
+
+
+static const uint64_t P9N2_PERV_0_FSII2C_INTERRUPTS_A = 0x00001806ull;
+
+static const uint32_t P9N2_PERV_FSII2C_INTERRUPTS_A = 0x00001806ull;
+
+
+static const uint64_t P9N2_PERV_0_FSII2C_INTERRUPT_COND_A = 0x00001805ull;
+
+static const uint32_t P9N2_PERV_FSII2C_INTERRUPT_COND_A = 0x00001805ull;
+
+
+static const uint64_t P9N2_PERV_INTERRUPT_CONF_REG = 0x000F002Full;
+
+static const uint64_t P9N2_PERV_INTERRUPT_CONF_REG_WOR = 0x000F0030ull;
+
+static const uint64_t P9N2_PERV_INTERRUPT_CONF_REG_WAND = 0x000F0031ull;
+
+static const uint64_t P9N2_PERV_PIB_INTERRUPT_CONF_REG = 0x000F002Full;
+
+static const uint64_t P9N2_PERV_PIB_INTERRUPT_CONF_REG_WOR = 0x000F0030ull;
+
+static const uint64_t P9N2_PERV_PIB_INTERRUPT_CONF_REG_WAND = 0x000F0031ull;
+
+
+static const uint64_t P9N2_PERV_INTERRUPT_HOLD_REG = 0x000F0032ull;
+
+static const uint64_t P9N2_PERV_PIB_INTERRUPT_HOLD_REG = 0x000F0032ull;
+
+
+static const uint64_t P9N2_PERV_0_FSII2C_INTERRUPT_MASK_REGISTER_A_WO = 0x00001804ull;
+
+static const uint64_t P9N2_PERV_0_FSII2C_INTERRUPT_MASK_REGISTER_A_OR = 0x00001805ull;
+
+static const uint64_t P9N2_PERV_0_FSII2C_INTERRUPT_MASK_REGISTER_A_AND = 0x00001806ull;
+
+static const uint32_t P9N2_PERV_FSII2C_INTERRUPT_MASK_REGISTER_A_WO = 0x00001804ull;
+
+static const uint32_t P9N2_PERV_FSII2C_INTERRUPT_MASK_REGISTER_A_OR = 0x00001805ull;
+
+static const uint32_t P9N2_PERV_FSII2C_INTERRUPT_MASK_REGISTER_A_AND = 0x00001806ull;
+
+
+static const uint64_t P9N2_PERV_0_FSII2C_INTERRUPT_MASK_REGISTER_READ_A = 0x00001804ull;
+
+static const uint32_t P9N2_PERV_FSII2C_INTERRUPT_MASK_REGISTER_READ_A = 0x00001804ull;
+
+
+static const uint64_t P9N2_PERV_INTERRUPT_TYPE_MASK_REG = 0x000F002Cull;
+
+static const uint64_t P9N2_PERV_INTERRUPT_TYPE_MASK_REG_WOR = 0x000F002Dull;
+
+static const uint64_t P9N2_PERV_INTERRUPT_TYPE_MASK_REG_WAND = 0x000F002Eull;
+
+static const uint64_t P9N2_PERV_PIB_INTERRUPT_TYPE_MASK_REG = 0x000F002Cull;
+
+static const uint64_t P9N2_PERV_PIB_INTERRUPT_TYPE_MASK_REG_WOR = 0x000F002Dull;
+
+static const uint64_t P9N2_PERV_PIB_INTERRUPT_TYPE_MASK_REG_WAND = 0x000F002Eull;
+
+
+static const uint64_t P9N2_PERV_INTERRUPT_TYPE_REG = 0x000F001Aull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_PERV_PIB_INTERRUPT_TYPE_REG = 0x000F001Aull;
+
+
+static const uint64_t P9N2_PERV_IODA_TCD_IODA = 0x00002800ull;
+
+
+static const uint64_t P9N2_PERV_IODA_TDR_IODA = 0x00002C00ull;
+
+
+static const uint64_t P9N2_PERV_IODA_TDR_MEM_IODA = 0x00003000ull;
+
+
+static const uint64_t P9N2_PERV_FSB_IODA_TVT_IODA = 0x00002400ull;
+
+
+static const uint64_t P9N2_PERV_IODA_XLT_EA_IODA = 0x00004000ull;
+
+
+static const uint64_t P9N2_PERV_KVREF_AND_VMEAS_MODE_STATUS_REG = 0x00020007ull;
+
+static const uint64_t P9N2_PERV_TP_KVREF_AND_VMEAS_MODE_STATUS_REG = 0x01020007ull;
+
+
+static const uint64_t P9N2_PERV_KVREF_TUNE_DATA = 0x00020005ull;
+
+static const uint64_t P9N2_PERV_TP_KVREF_TUNE_DATA = 0x01020005ull;
+
+
+static const uint64_t P9N2_PERV_LOCAL_FIR = 0x0004000Aull;
+
+static const uint64_t P9N2_PERV_TP_LOCAL_FIR = 0x0104000Aull;
+
+static const uint64_t P9N2_PERV_LOCAL_FIR_AND = 0x0004000Bull;
+
+static const uint64_t P9N2_PERV_TP_LOCAL_FIR_AND = 0x0104000Bull;
+
+static const uint64_t P9N2_PERV_LOCAL_FIR_OR = 0x0004000Cull;
+
+static const uint64_t P9N2_PERV_TP_LOCAL_FIR_OR = 0x0104000Cull;
+
+static const uint64_t P9N2_PERV_N0_LOCAL_FIR = 0x0204000Aull;
+
+static const uint64_t P9N2_PERV_N0_LOCAL_FIR_AND = 0x0204000Bull;
+
+static const uint64_t P9N2_PERV_N0_LOCAL_FIR_OR = 0x0204000Cull;
+
+static const uint64_t P9N2_PERV_N1_LOCAL_FIR = 0x0304000Aull;
+
+static const uint64_t P9N2_PERV_N1_LOCAL_FIR_AND = 0x0304000Bull;
+
+static const uint64_t P9N2_PERV_N1_LOCAL_FIR_OR = 0x0304000Cull;
+
+static const uint64_t P9N2_PERV_N2_LOCAL_FIR = 0x0404000Aull;
+
+static const uint64_t P9N2_PERV_N2_LOCAL_FIR_AND = 0x0404000Bull;
+
+static const uint64_t P9N2_PERV_N2_LOCAL_FIR_OR = 0x0404000Cull;
+
+static const uint64_t P9N2_PERV_N3_LOCAL_FIR = 0x0504000Aull;
+
+static const uint64_t P9N2_PERV_N3_LOCAL_FIR_AND = 0x0504000Bull;
+
+static const uint64_t P9N2_PERV_N3_LOCAL_FIR_OR = 0x0504000Cull;
+
+static const uint64_t P9N2_PERV_XB_LOCAL_FIR = 0x0604000Aull;
+
+static const uint64_t P9N2_PERV_XB_LOCAL_FIR_AND = 0x0604000Bull;
+
+static const uint64_t P9N2_PERV_XB_LOCAL_FIR_OR = 0x0604000Cull;
+
+static const uint64_t P9N2_PERV_MC01_LOCAL_FIR = 0x0704000Aull;
+
+static const uint64_t P9N2_PERV_MC01_LOCAL_FIR_AND = 0x0704000Bull;
+
+static const uint64_t P9N2_PERV_MC01_LOCAL_FIR_OR = 0x0704000Cull;
+
+static const uint64_t P9N2_PERV_MC23_LOCAL_FIR = 0x0804000Aull;
+
+static const uint64_t P9N2_PERV_MC23_LOCAL_FIR_AND = 0x0804000Bull;
+
+static const uint64_t P9N2_PERV_MC23_LOCAL_FIR_OR = 0x0804000Cull;
+
+static const uint64_t P9N2_PERV_OB0_LOCAL_FIR = 0x0904000Aull;
+
+static const uint64_t P9N2_PERV_OB0_LOCAL_FIR_AND = 0x0904000Bull;
+
+static const uint64_t P9N2_PERV_OB0_LOCAL_FIR_OR = 0x0904000Cull;
+
+static const uint64_t P9N2_PERV_OB3_LOCAL_FIR = 0x0C04000Aull;
+
+static const uint64_t P9N2_PERV_OB3_LOCAL_FIR_AND = 0x0C04000Bull;
+
+static const uint64_t P9N2_PERV_OB3_LOCAL_FIR_OR = 0x0C04000Cull;
+
+static const uint64_t P9N2_PERV_PCI0_LOCAL_FIR = 0x0D04000Aull;
+
+static const uint64_t P9N2_PERV_PCI0_LOCAL_FIR_AND = 0x0D04000Bull;
+
+static const uint64_t P9N2_PERV_PCI0_LOCAL_FIR_OR = 0x0D04000Cull;
+
+static const uint64_t P9N2_PERV_PCI1_LOCAL_FIR = 0x0E04000Aull;
+
+static const uint64_t P9N2_PERV_PCI1_LOCAL_FIR_AND = 0x0E04000Bull;
+
+static const uint64_t P9N2_PERV_PCI1_LOCAL_FIR_OR = 0x0E04000Cull;
+
+static const uint64_t P9N2_PERV_PCI2_LOCAL_FIR = 0x0F04000Aull;
+
+static const uint64_t P9N2_PERV_PCI2_LOCAL_FIR_AND = 0x0F04000Bull;
+
+static const uint64_t P9N2_PERV_PCI2_LOCAL_FIR_OR = 0x0F04000Cull;
+
+static const uint64_t P9N2_PERV_EP00_LOCAL_FIR = 0x1004000Aull;
+
+static const uint64_t P9N2_PERV_EP00_LOCAL_FIR_AND = 0x1004000Bull;
+
+static const uint64_t P9N2_PERV_EP00_LOCAL_FIR_OR = 0x1004000Cull;
+
+static const uint64_t P9N2_PERV_EP01_LOCAL_FIR = 0x1104000Aull;
+
+static const uint64_t P9N2_PERV_EP01_LOCAL_FIR_AND = 0x1104000Bull;
+
+static const uint64_t P9N2_PERV_EP01_LOCAL_FIR_OR = 0x1104000Cull;
+
+static const uint64_t P9N2_PERV_EP02_LOCAL_FIR = 0x1204000Aull;
+
+static const uint64_t P9N2_PERV_EP02_LOCAL_FIR_AND = 0x1204000Bull;
+
+static const uint64_t P9N2_PERV_EP02_LOCAL_FIR_OR = 0x1204000Cull;
+
+static const uint64_t P9N2_PERV_EP03_LOCAL_FIR = 0x1304000Aull;
+
+static const uint64_t P9N2_PERV_EP03_LOCAL_FIR_AND = 0x1304000Bull;
+
+static const uint64_t P9N2_PERV_EP03_LOCAL_FIR_OR = 0x1304000Cull;
+
+static const uint64_t P9N2_PERV_EP04_LOCAL_FIR = 0x1404000Aull;
+
+static const uint64_t P9N2_PERV_EP04_LOCAL_FIR_AND = 0x1404000Bull;
+
+static const uint64_t P9N2_PERV_EP04_LOCAL_FIR_OR = 0x1404000Cull;
+
+static const uint64_t P9N2_PERV_EP05_LOCAL_FIR = 0x1504000Aull;
+
+static const uint64_t P9N2_PERV_EP05_LOCAL_FIR_AND = 0x1504000Bull;
+
+static const uint64_t P9N2_PERV_EP05_LOCAL_FIR_OR = 0x1504000Cull;
+
+static const uint64_t P9N2_PERV_EC00_LOCAL_FIR = 0x2004000Aull;
+
+static const uint64_t P9N2_PERV_EC00_LOCAL_FIR_AND = 0x2004000Bull;
+
+static const uint64_t P9N2_PERV_EC00_LOCAL_FIR_OR = 0x2004000Cull;
+
+static const uint64_t P9N2_PERV_EC01_LOCAL_FIR = 0x2104000Aull;
+
+static const uint64_t P9N2_PERV_EC01_LOCAL_FIR_AND = 0x2104000Bull;
+
+static const uint64_t P9N2_PERV_EC01_LOCAL_FIR_OR = 0x2104000Cull;
+
+static const uint64_t P9N2_PERV_EC02_LOCAL_FIR = 0x2204000Aull;
+
+static const uint64_t P9N2_PERV_EC02_LOCAL_FIR_AND = 0x2204000Bull;
+
+static const uint64_t P9N2_PERV_EC02_LOCAL_FIR_OR = 0x2204000Cull;
+
+static const uint64_t P9N2_PERV_EC03_LOCAL_FIR = 0x2304000Aull;
+
+static const uint64_t P9N2_PERV_EC03_LOCAL_FIR_AND = 0x2304000Bull;
+
+static const uint64_t P9N2_PERV_EC03_LOCAL_FIR_OR = 0x2304000Cull;
+
+static const uint64_t P9N2_PERV_EC04_LOCAL_FIR = 0x2404000Aull;
+
+static const uint64_t P9N2_PERV_EC04_LOCAL_FIR_AND = 0x2404000Bull;
+
+static const uint64_t P9N2_PERV_EC04_LOCAL_FIR_OR = 0x2404000Cull;
+
+static const uint64_t P9N2_PERV_EC05_LOCAL_FIR = 0x2504000Aull;
+
+static const uint64_t P9N2_PERV_EC05_LOCAL_FIR_AND = 0x2504000Bull;
+
+static const uint64_t P9N2_PERV_EC05_LOCAL_FIR_OR = 0x2504000Cull;
+
+static const uint64_t P9N2_PERV_EC06_LOCAL_FIR = 0x2604000Aull;
+
+static const uint64_t P9N2_PERV_EC06_LOCAL_FIR_AND = 0x2604000Bull;
+
+static const uint64_t P9N2_PERV_EC06_LOCAL_FIR_OR = 0x2604000Cull;
+
+static const uint64_t P9N2_PERV_EC07_LOCAL_FIR = 0x2704000Aull;
+
+static const uint64_t P9N2_PERV_EC07_LOCAL_FIR_AND = 0x2704000Bull;
+
+static const uint64_t P9N2_PERV_EC07_LOCAL_FIR_OR = 0x2704000Cull;
+
+static const uint64_t P9N2_PERV_EC08_LOCAL_FIR = 0x2804000Aull;
+
+static const uint64_t P9N2_PERV_EC08_LOCAL_FIR_AND = 0x2804000Bull;
+
+static const uint64_t P9N2_PERV_EC08_LOCAL_FIR_OR = 0x2804000Cull;
+
+static const uint64_t P9N2_PERV_EC09_LOCAL_FIR = 0x2904000Aull;
+
+static const uint64_t P9N2_PERV_EC09_LOCAL_FIR_AND = 0x2904000Bull;
+
+static const uint64_t P9N2_PERV_EC09_LOCAL_FIR_OR = 0x2904000Cull;
+
+static const uint64_t P9N2_PERV_EC10_LOCAL_FIR = 0x2A04000Aull;
+
+static const uint64_t P9N2_PERV_EC10_LOCAL_FIR_AND = 0x2A04000Bull;
+
+static const uint64_t P9N2_PERV_EC10_LOCAL_FIR_OR = 0x2A04000Cull;
+
+static const uint64_t P9N2_PERV_EC11_LOCAL_FIR = 0x2B04000Aull;
+
+static const uint64_t P9N2_PERV_EC11_LOCAL_FIR_AND = 0x2B04000Bull;
+
+static const uint64_t P9N2_PERV_EC11_LOCAL_FIR_OR = 0x2B04000Cull;
+
+static const uint64_t P9N2_PERV_EC12_LOCAL_FIR = 0x2C04000Aull;
+
+static const uint64_t P9N2_PERV_EC12_LOCAL_FIR_AND = 0x2C04000Bull;
+
+static const uint64_t P9N2_PERV_EC12_LOCAL_FIR_OR = 0x2C04000Cull;
+
+static const uint64_t P9N2_PERV_EC13_LOCAL_FIR = 0x2D04000Aull;
+
+static const uint64_t P9N2_PERV_EC13_LOCAL_FIR_AND = 0x2D04000Bull;
+
+static const uint64_t P9N2_PERV_EC13_LOCAL_FIR_OR = 0x2D04000Cull;
+
+static const uint64_t P9N2_PERV_EC14_LOCAL_FIR = 0x2E04000Aull;
+
+static const uint64_t P9N2_PERV_EC14_LOCAL_FIR_AND = 0x2E04000Bull;
+
+static const uint64_t P9N2_PERV_EC14_LOCAL_FIR_OR = 0x2E04000Cull;
+
+static const uint64_t P9N2_PERV_EC15_LOCAL_FIR = 0x2F04000Aull;
+
+static const uint64_t P9N2_PERV_EC15_LOCAL_FIR_AND = 0x2F04000Bull;
+
+static const uint64_t P9N2_PERV_EC15_LOCAL_FIR_OR = 0x2F04000Cull;
+
+static const uint64_t P9N2_PERV_EC16_LOCAL_FIR = 0x3004000Aull;
+
+static const uint64_t P9N2_PERV_EC16_LOCAL_FIR_AND = 0x3004000Bull;
+
+static const uint64_t P9N2_PERV_EC16_LOCAL_FIR_OR = 0x3004000Cull;
+
+static const uint64_t P9N2_PERV_EC17_LOCAL_FIR = 0x3104000Aull;
+
+static const uint64_t P9N2_PERV_EC17_LOCAL_FIR_AND = 0x3104000Bull;
+
+static const uint64_t P9N2_PERV_EC17_LOCAL_FIR_OR = 0x3104000Cull;
+
+static const uint64_t P9N2_PERV_EC18_LOCAL_FIR = 0x3204000Aull;
+
+static const uint64_t P9N2_PERV_EC18_LOCAL_FIR_AND = 0x3204000Bull;
+
+static const uint64_t P9N2_PERV_EC18_LOCAL_FIR_OR = 0x3204000Cull;
+
+static const uint64_t P9N2_PERV_EC19_LOCAL_FIR = 0x3304000Aull;
+
+static const uint64_t P9N2_PERV_EC19_LOCAL_FIR_AND = 0x3304000Bull;
+
+static const uint64_t P9N2_PERV_EC19_LOCAL_FIR_OR = 0x3304000Cull;
+
+static const uint64_t P9N2_PERV_EC20_LOCAL_FIR = 0x3404000Aull;
+
+static const uint64_t P9N2_PERV_EC20_LOCAL_FIR_AND = 0x3404000Bull;
+
+static const uint64_t P9N2_PERV_EC20_LOCAL_FIR_OR = 0x3404000Cull;
+
+static const uint64_t P9N2_PERV_EC21_LOCAL_FIR = 0x3504000Aull;
+
+static const uint64_t P9N2_PERV_EC21_LOCAL_FIR_AND = 0x3504000Bull;
+
+static const uint64_t P9N2_PERV_EC21_LOCAL_FIR_OR = 0x3504000Cull;
+
+static const uint64_t P9N2_PERV_EC22_LOCAL_FIR = 0x3604000Aull;
+
+static const uint64_t P9N2_PERV_EC22_LOCAL_FIR_AND = 0x3604000Bull;
+
+static const uint64_t P9N2_PERV_EC22_LOCAL_FIR_OR = 0x3604000Cull;
+
+static const uint64_t P9N2_PERV_EC23_LOCAL_FIR = 0x3704000Aull;
+
+static const uint64_t P9N2_PERV_EC23_LOCAL_FIR_AND = 0x3704000Bull;
+
+static const uint64_t P9N2_PERV_EC23_LOCAL_FIR_OR = 0x3704000Cull;
+
+
+static const uint64_t P9N2_PERV_LOCAL_FIR_ACTION0 = 0x00040010ull;
+
+static const uint64_t P9N2_PERV_TP_LOCAL_FIR_ACTION0 = 0x01040010ull;
+
+static const uint64_t P9N2_PERV_N0_LOCAL_FIR_ACTION0 = 0x02040010ull;
+
+static const uint64_t P9N2_PERV_N1_LOCAL_FIR_ACTION0 = 0x03040010ull;
+
+static const uint64_t P9N2_PERV_N2_LOCAL_FIR_ACTION0 = 0x04040010ull;
+
+static const uint64_t P9N2_PERV_N3_LOCAL_FIR_ACTION0 = 0x05040010ull;
+
+static const uint64_t P9N2_PERV_XB_LOCAL_FIR_ACTION0 = 0x06040010ull;
+
+static const uint64_t P9N2_PERV_MC01_LOCAL_FIR_ACTION0 = 0x07040010ull;
+
+static const uint64_t P9N2_PERV_MC23_LOCAL_FIR_ACTION0 = 0x08040010ull;
+
+static const uint64_t P9N2_PERV_OB0_LOCAL_FIR_ACTION0 = 0x09040010ull;
+
+static const uint64_t P9N2_PERV_OB3_LOCAL_FIR_ACTION0 = 0x0C040010ull;
+
+static const uint64_t P9N2_PERV_PCI0_LOCAL_FIR_ACTION0 = 0x0D040010ull;
+
+static const uint64_t P9N2_PERV_PCI1_LOCAL_FIR_ACTION0 = 0x0E040010ull;
+
+static const uint64_t P9N2_PERV_PCI2_LOCAL_FIR_ACTION0 = 0x0F040010ull;
+
+static const uint64_t P9N2_PERV_EP00_LOCAL_FIR_ACTION0 = 0x10040010ull;
+
+static const uint64_t P9N2_PERV_EP01_LOCAL_FIR_ACTION0 = 0x11040010ull;
+
+static const uint64_t P9N2_PERV_EP02_LOCAL_FIR_ACTION0 = 0x12040010ull;
+
+static const uint64_t P9N2_PERV_EP03_LOCAL_FIR_ACTION0 = 0x13040010ull;
+
+static const uint64_t P9N2_PERV_EP04_LOCAL_FIR_ACTION0 = 0x14040010ull;
+
+static const uint64_t P9N2_PERV_EP05_LOCAL_FIR_ACTION0 = 0x15040010ull;
+
+static const uint64_t P9N2_PERV_EC00_LOCAL_FIR_ACTION0 = 0x20040010ull;
+
+static const uint64_t P9N2_PERV_EC01_LOCAL_FIR_ACTION0 = 0x21040010ull;
+
+static const uint64_t P9N2_PERV_EC02_LOCAL_FIR_ACTION0 = 0x22040010ull;
+
+static const uint64_t P9N2_PERV_EC03_LOCAL_FIR_ACTION0 = 0x23040010ull;
+
+static const uint64_t P9N2_PERV_EC04_LOCAL_FIR_ACTION0 = 0x24040010ull;
+
+static const uint64_t P9N2_PERV_EC05_LOCAL_FIR_ACTION0 = 0x25040010ull;
+
+static const uint64_t P9N2_PERV_EC06_LOCAL_FIR_ACTION0 = 0x26040010ull;
+
+static const uint64_t P9N2_PERV_EC07_LOCAL_FIR_ACTION0 = 0x27040010ull;
+
+static const uint64_t P9N2_PERV_EC08_LOCAL_FIR_ACTION0 = 0x28040010ull;
+
+static const uint64_t P9N2_PERV_EC09_LOCAL_FIR_ACTION0 = 0x29040010ull;
+
+static const uint64_t P9N2_PERV_EC10_LOCAL_FIR_ACTION0 = 0x2A040010ull;
+
+static const uint64_t P9N2_PERV_EC11_LOCAL_FIR_ACTION0 = 0x2B040010ull;
+
+static const uint64_t P9N2_PERV_EC12_LOCAL_FIR_ACTION0 = 0x2C040010ull;
+
+static const uint64_t P9N2_PERV_EC13_LOCAL_FIR_ACTION0 = 0x2D040010ull;
+
+static const uint64_t P9N2_PERV_EC14_LOCAL_FIR_ACTION0 = 0x2E040010ull;
+
+static const uint64_t P9N2_PERV_EC15_LOCAL_FIR_ACTION0 = 0x2F040010ull;
+
+static const uint64_t P9N2_PERV_EC16_LOCAL_FIR_ACTION0 = 0x30040010ull;
+
+static const uint64_t P9N2_PERV_EC17_LOCAL_FIR_ACTION0 = 0x31040010ull;
+
+static const uint64_t P9N2_PERV_EC18_LOCAL_FIR_ACTION0 = 0x32040010ull;
+
+static const uint64_t P9N2_PERV_EC19_LOCAL_FIR_ACTION0 = 0x33040010ull;
+
+static const uint64_t P9N2_PERV_EC20_LOCAL_FIR_ACTION0 = 0x34040010ull;
+
+static const uint64_t P9N2_PERV_EC21_LOCAL_FIR_ACTION0 = 0x35040010ull;
+
+static const uint64_t P9N2_PERV_EC22_LOCAL_FIR_ACTION0 = 0x36040010ull;
+
+static const uint64_t P9N2_PERV_EC23_LOCAL_FIR_ACTION0 = 0x37040010ull;
+
+
+static const uint64_t P9N2_PERV_LOCAL_FIR_ACTION1 = 0x00040011ull;
+
+static const uint64_t P9N2_PERV_TP_LOCAL_FIR_ACTION1 = 0x01040011ull;
+
+static const uint64_t P9N2_PERV_N0_LOCAL_FIR_ACTION1 = 0x02040011ull;
+
+static const uint64_t P9N2_PERV_N1_LOCAL_FIR_ACTION1 = 0x03040011ull;
+
+static const uint64_t P9N2_PERV_N2_LOCAL_FIR_ACTION1 = 0x04040011ull;
+
+static const uint64_t P9N2_PERV_N3_LOCAL_FIR_ACTION1 = 0x05040011ull;
+
+static const uint64_t P9N2_PERV_XB_LOCAL_FIR_ACTION1 = 0x06040011ull;
+
+static const uint64_t P9N2_PERV_MC01_LOCAL_FIR_ACTION1 = 0x07040011ull;
+
+static const uint64_t P9N2_PERV_MC23_LOCAL_FIR_ACTION1 = 0x08040011ull;
+
+static const uint64_t P9N2_PERV_OB0_LOCAL_FIR_ACTION1 = 0x09040011ull;
+
+static const uint64_t P9N2_PERV_OB3_LOCAL_FIR_ACTION1 = 0x0C040011ull;
+
+static const uint64_t P9N2_PERV_PCI0_LOCAL_FIR_ACTION1 = 0x0D040011ull;
+
+static const uint64_t P9N2_PERV_PCI1_LOCAL_FIR_ACTION1 = 0x0E040011ull;
+
+static const uint64_t P9N2_PERV_PCI2_LOCAL_FIR_ACTION1 = 0x0F040011ull;
+
+static const uint64_t P9N2_PERV_EP00_LOCAL_FIR_ACTION1 = 0x10040011ull;
+
+static const uint64_t P9N2_PERV_EP01_LOCAL_FIR_ACTION1 = 0x11040011ull;
+
+static const uint64_t P9N2_PERV_EP02_LOCAL_FIR_ACTION1 = 0x12040011ull;
+
+static const uint64_t P9N2_PERV_EP03_LOCAL_FIR_ACTION1 = 0x13040011ull;
+
+static const uint64_t P9N2_PERV_EP04_LOCAL_FIR_ACTION1 = 0x14040011ull;
+
+static const uint64_t P9N2_PERV_EP05_LOCAL_FIR_ACTION1 = 0x15040011ull;
+
+static const uint64_t P9N2_PERV_EC00_LOCAL_FIR_ACTION1 = 0x20040011ull;
+
+static const uint64_t P9N2_PERV_EC01_LOCAL_FIR_ACTION1 = 0x21040011ull;
+
+static const uint64_t P9N2_PERV_EC02_LOCAL_FIR_ACTION1 = 0x22040011ull;
+
+static const uint64_t P9N2_PERV_EC03_LOCAL_FIR_ACTION1 = 0x23040011ull;
+
+static const uint64_t P9N2_PERV_EC04_LOCAL_FIR_ACTION1 = 0x24040011ull;
+
+static const uint64_t P9N2_PERV_EC05_LOCAL_FIR_ACTION1 = 0x25040011ull;
+
+static const uint64_t P9N2_PERV_EC06_LOCAL_FIR_ACTION1 = 0x26040011ull;
+
+static const uint64_t P9N2_PERV_EC07_LOCAL_FIR_ACTION1 = 0x27040011ull;
+
+static const uint64_t P9N2_PERV_EC08_LOCAL_FIR_ACTION1 = 0x28040011ull;
+
+static const uint64_t P9N2_PERV_EC09_LOCAL_FIR_ACTION1 = 0x29040011ull;
+
+static const uint64_t P9N2_PERV_EC10_LOCAL_FIR_ACTION1 = 0x2A040011ull;
+
+static const uint64_t P9N2_PERV_EC11_LOCAL_FIR_ACTION1 = 0x2B040011ull;
+
+static const uint64_t P9N2_PERV_EC12_LOCAL_FIR_ACTION1 = 0x2C040011ull;
+
+static const uint64_t P9N2_PERV_EC13_LOCAL_FIR_ACTION1 = 0x2D040011ull;
+
+static const uint64_t P9N2_PERV_EC14_LOCAL_FIR_ACTION1 = 0x2E040011ull;
+
+static const uint64_t P9N2_PERV_EC15_LOCAL_FIR_ACTION1 = 0x2F040011ull;
+
+static const uint64_t P9N2_PERV_EC16_LOCAL_FIR_ACTION1 = 0x30040011ull;
+
+static const uint64_t P9N2_PERV_EC17_LOCAL_FIR_ACTION1 = 0x31040011ull;
+
+static const uint64_t P9N2_PERV_EC18_LOCAL_FIR_ACTION1 = 0x32040011ull;
+
+static const uint64_t P9N2_PERV_EC19_LOCAL_FIR_ACTION1 = 0x33040011ull;
+
+static const uint64_t P9N2_PERV_EC20_LOCAL_FIR_ACTION1 = 0x34040011ull;
+
+static const uint64_t P9N2_PERV_EC21_LOCAL_FIR_ACTION1 = 0x35040011ull;
+
+static const uint64_t P9N2_PERV_EC22_LOCAL_FIR_ACTION1 = 0x36040011ull;
+
+static const uint64_t P9N2_PERV_EC23_LOCAL_FIR_ACTION1 = 0x37040011ull;
+
+
+static const uint64_t P9N2_PERV_LOCAL_FIR_MASK = 0x0004000Dull;
+
+static const uint64_t P9N2_PERV_TP_LOCAL_FIR_MASK = 0x0104000Dull;
+
+static const uint64_t P9N2_PERV_LOCAL_FIR_MASK_AND = 0x0004000Eull;
+
+static const uint64_t P9N2_PERV_TP_LOCAL_FIR_MASK_AND = 0x0104000Eull;
+
+static const uint64_t P9N2_PERV_LOCAL_FIR_MASK_OR = 0x0004000Full;
+
+static const uint64_t P9N2_PERV_TP_LOCAL_FIR_MASK_OR = 0x0104000Full;
+
+static const uint64_t P9N2_PERV_N0_LOCAL_FIR_MASK = 0x0204000Dull;
+
+static const uint64_t P9N2_PERV_N0_LOCAL_FIR_MASK_AND = 0x0204000Eull;
+
+static const uint64_t P9N2_PERV_N0_LOCAL_FIR_MASK_OR = 0x0204000Full;
+
+static const uint64_t P9N2_PERV_N1_LOCAL_FIR_MASK = 0x0304000Dull;
+
+static const uint64_t P9N2_PERV_N1_LOCAL_FIR_MASK_AND = 0x0304000Eull;
+
+static const uint64_t P9N2_PERV_N1_LOCAL_FIR_MASK_OR = 0x0304000Full;
+
+static const uint64_t P9N2_PERV_N2_LOCAL_FIR_MASK = 0x0404000Dull;
+
+static const uint64_t P9N2_PERV_N2_LOCAL_FIR_MASK_AND = 0x0404000Eull;
+
+static const uint64_t P9N2_PERV_N2_LOCAL_FIR_MASK_OR = 0x0404000Full;
+
+static const uint64_t P9N2_PERV_N3_LOCAL_FIR_MASK = 0x0504000Dull;
+
+static const uint64_t P9N2_PERV_N3_LOCAL_FIR_MASK_AND = 0x0504000Eull;
+
+static const uint64_t P9N2_PERV_N3_LOCAL_FIR_MASK_OR = 0x0504000Full;
+
+static const uint64_t P9N2_PERV_XB_LOCAL_FIR_MASK = 0x0604000Dull;
+
+static const uint64_t P9N2_PERV_XB_LOCAL_FIR_MASK_AND = 0x0604000Eull;
+
+static const uint64_t P9N2_PERV_XB_LOCAL_FIR_MASK_OR = 0x0604000Full;
+
+static const uint64_t P9N2_PERV_MC01_LOCAL_FIR_MASK = 0x0704000Dull;
+
+static const uint64_t P9N2_PERV_MC01_LOCAL_FIR_MASK_AND = 0x0704000Eull;
+
+static const uint64_t P9N2_PERV_MC01_LOCAL_FIR_MASK_OR = 0x0704000Full;
+
+static const uint64_t P9N2_PERV_MC23_LOCAL_FIR_MASK = 0x0804000Dull;
+
+static const uint64_t P9N2_PERV_MC23_LOCAL_FIR_MASK_AND = 0x0804000Eull;
+
+static const uint64_t P9N2_PERV_MC23_LOCAL_FIR_MASK_OR = 0x0804000Full;
+
+static const uint64_t P9N2_PERV_OB0_LOCAL_FIR_MASK = 0x0904000Dull;
+
+static const uint64_t P9N2_PERV_OB0_LOCAL_FIR_MASK_AND = 0x0904000Eull;
+
+static const uint64_t P9N2_PERV_OB0_LOCAL_FIR_MASK_OR = 0x0904000Full;
+
+static const uint64_t P9N2_PERV_OB3_LOCAL_FIR_MASK = 0x0C04000Dull;
+
+static const uint64_t P9N2_PERV_OB3_LOCAL_FIR_MASK_AND = 0x0C04000Eull;
+
+static const uint64_t P9N2_PERV_OB3_LOCAL_FIR_MASK_OR = 0x0C04000Full;
+
+static const uint64_t P9N2_PERV_PCI0_LOCAL_FIR_MASK = 0x0D04000Dull;
+
+static const uint64_t P9N2_PERV_PCI0_LOCAL_FIR_MASK_AND = 0x0D04000Eull;
+
+static const uint64_t P9N2_PERV_PCI0_LOCAL_FIR_MASK_OR = 0x0D04000Full;
+
+static const uint64_t P9N2_PERV_PCI1_LOCAL_FIR_MASK = 0x0E04000Dull;
+
+static const uint64_t P9N2_PERV_PCI1_LOCAL_FIR_MASK_AND = 0x0E04000Eull;
+
+static const uint64_t P9N2_PERV_PCI1_LOCAL_FIR_MASK_OR = 0x0E04000Full;
+
+static const uint64_t P9N2_PERV_PCI2_LOCAL_FIR_MASK = 0x0F04000Dull;
+
+static const uint64_t P9N2_PERV_PCI2_LOCAL_FIR_MASK_AND = 0x0F04000Eull;
+
+static const uint64_t P9N2_PERV_PCI2_LOCAL_FIR_MASK_OR = 0x0F04000Full;
+
+static const uint64_t P9N2_PERV_EP00_LOCAL_FIR_MASK = 0x1004000Dull;
+
+static const uint64_t P9N2_PERV_EP00_LOCAL_FIR_MASK_AND = 0x1004000Eull;
+
+static const uint64_t P9N2_PERV_EP00_LOCAL_FIR_MASK_OR = 0x1004000Full;
+
+static const uint64_t P9N2_PERV_EP01_LOCAL_FIR_MASK = 0x1104000Dull;
+
+static const uint64_t P9N2_PERV_EP01_LOCAL_FIR_MASK_AND = 0x1104000Eull;
+
+static const uint64_t P9N2_PERV_EP01_LOCAL_FIR_MASK_OR = 0x1104000Full;
+
+static const uint64_t P9N2_PERV_EP02_LOCAL_FIR_MASK = 0x1204000Dull;
+
+static const uint64_t P9N2_PERV_EP02_LOCAL_FIR_MASK_AND = 0x1204000Eull;
+
+static const uint64_t P9N2_PERV_EP02_LOCAL_FIR_MASK_OR = 0x1204000Full;
+
+static const uint64_t P9N2_PERV_EP03_LOCAL_FIR_MASK = 0x1304000Dull;
+
+static const uint64_t P9N2_PERV_EP03_LOCAL_FIR_MASK_AND = 0x1304000Eull;
+
+static const uint64_t P9N2_PERV_EP03_LOCAL_FIR_MASK_OR = 0x1304000Full;
+
+static const uint64_t P9N2_PERV_EP04_LOCAL_FIR_MASK = 0x1404000Dull;
+
+static const uint64_t P9N2_PERV_EP04_LOCAL_FIR_MASK_AND = 0x1404000Eull;
+
+static const uint64_t P9N2_PERV_EP04_LOCAL_FIR_MASK_OR = 0x1404000Full;
+
+static const uint64_t P9N2_PERV_EP05_LOCAL_FIR_MASK = 0x1504000Dull;
+
+static const uint64_t P9N2_PERV_EP05_LOCAL_FIR_MASK_AND = 0x1504000Eull;
+
+static const uint64_t P9N2_PERV_EP05_LOCAL_FIR_MASK_OR = 0x1504000Full;
+
+static const uint64_t P9N2_PERV_EC00_LOCAL_FIR_MASK = 0x2004000Dull;
+
+static const uint64_t P9N2_PERV_EC00_LOCAL_FIR_MASK_AND = 0x2004000Eull;
+
+static const uint64_t P9N2_PERV_EC00_LOCAL_FIR_MASK_OR = 0x2004000Full;
+
+static const uint64_t P9N2_PERV_EC01_LOCAL_FIR_MASK = 0x2104000Dull;
+
+static const uint64_t P9N2_PERV_EC01_LOCAL_FIR_MASK_AND = 0x2104000Eull;
+
+static const uint64_t P9N2_PERV_EC01_LOCAL_FIR_MASK_OR = 0x2104000Full;
+
+static const uint64_t P9N2_PERV_EC02_LOCAL_FIR_MASK = 0x2204000Dull;
+
+static const uint64_t P9N2_PERV_EC02_LOCAL_FIR_MASK_AND = 0x2204000Eull;
+
+static const uint64_t P9N2_PERV_EC02_LOCAL_FIR_MASK_OR = 0x2204000Full;
+
+static const uint64_t P9N2_PERV_EC03_LOCAL_FIR_MASK = 0x2304000Dull;
+
+static const uint64_t P9N2_PERV_EC03_LOCAL_FIR_MASK_AND = 0x2304000Eull;
+
+static const uint64_t P9N2_PERV_EC03_LOCAL_FIR_MASK_OR = 0x2304000Full;
+
+static const uint64_t P9N2_PERV_EC04_LOCAL_FIR_MASK = 0x2404000Dull;
+
+static const uint64_t P9N2_PERV_EC04_LOCAL_FIR_MASK_AND = 0x2404000Eull;
+
+static const uint64_t P9N2_PERV_EC04_LOCAL_FIR_MASK_OR = 0x2404000Full;
+
+static const uint64_t P9N2_PERV_EC05_LOCAL_FIR_MASK = 0x2504000Dull;
+
+static const uint64_t P9N2_PERV_EC05_LOCAL_FIR_MASK_AND = 0x2504000Eull;
+
+static const uint64_t P9N2_PERV_EC05_LOCAL_FIR_MASK_OR = 0x2504000Full;
+
+static const uint64_t P9N2_PERV_EC06_LOCAL_FIR_MASK = 0x2604000Dull;
+
+static const uint64_t P9N2_PERV_EC06_LOCAL_FIR_MASK_AND = 0x2604000Eull;
+
+static const uint64_t P9N2_PERV_EC06_LOCAL_FIR_MASK_OR = 0x2604000Full;
+
+static const uint64_t P9N2_PERV_EC07_LOCAL_FIR_MASK = 0x2704000Dull;
+
+static const uint64_t P9N2_PERV_EC07_LOCAL_FIR_MASK_AND = 0x2704000Eull;
+
+static const uint64_t P9N2_PERV_EC07_LOCAL_FIR_MASK_OR = 0x2704000Full;
+
+static const uint64_t P9N2_PERV_EC08_LOCAL_FIR_MASK = 0x2804000Dull;
+
+static const uint64_t P9N2_PERV_EC08_LOCAL_FIR_MASK_AND = 0x2804000Eull;
+
+static const uint64_t P9N2_PERV_EC08_LOCAL_FIR_MASK_OR = 0x2804000Full;
+
+static const uint64_t P9N2_PERV_EC09_LOCAL_FIR_MASK = 0x2904000Dull;
+
+static const uint64_t P9N2_PERV_EC09_LOCAL_FIR_MASK_AND = 0x2904000Eull;
+
+static const uint64_t P9N2_PERV_EC09_LOCAL_FIR_MASK_OR = 0x2904000Full;
+
+static const uint64_t P9N2_PERV_EC10_LOCAL_FIR_MASK = 0x2A04000Dull;
+
+static const uint64_t P9N2_PERV_EC10_LOCAL_FIR_MASK_AND = 0x2A04000Eull;
+
+static const uint64_t P9N2_PERV_EC10_LOCAL_FIR_MASK_OR = 0x2A04000Full;
+
+static const uint64_t P9N2_PERV_EC11_LOCAL_FIR_MASK = 0x2B04000Dull;
+
+static const uint64_t P9N2_PERV_EC11_LOCAL_FIR_MASK_AND = 0x2B04000Eull;
+
+static const uint64_t P9N2_PERV_EC11_LOCAL_FIR_MASK_OR = 0x2B04000Full;
+
+static const uint64_t P9N2_PERV_EC12_LOCAL_FIR_MASK = 0x2C04000Dull;
+
+static const uint64_t P9N2_PERV_EC12_LOCAL_FIR_MASK_AND = 0x2C04000Eull;
+
+static const uint64_t P9N2_PERV_EC12_LOCAL_FIR_MASK_OR = 0x2C04000Full;
+
+static const uint64_t P9N2_PERV_EC13_LOCAL_FIR_MASK = 0x2D04000Dull;
+
+static const uint64_t P9N2_PERV_EC13_LOCAL_FIR_MASK_AND = 0x2D04000Eull;
+
+static const uint64_t P9N2_PERV_EC13_LOCAL_FIR_MASK_OR = 0x2D04000Full;
+
+static const uint64_t P9N2_PERV_EC14_LOCAL_FIR_MASK = 0x2E04000Dull;
+
+static const uint64_t P9N2_PERV_EC14_LOCAL_FIR_MASK_AND = 0x2E04000Eull;
+
+static const uint64_t P9N2_PERV_EC14_LOCAL_FIR_MASK_OR = 0x2E04000Full;
+
+static const uint64_t P9N2_PERV_EC15_LOCAL_FIR_MASK = 0x2F04000Dull;
+
+static const uint64_t P9N2_PERV_EC15_LOCAL_FIR_MASK_AND = 0x2F04000Eull;
+
+static const uint64_t P9N2_PERV_EC15_LOCAL_FIR_MASK_OR = 0x2F04000Full;
+
+static const uint64_t P9N2_PERV_EC16_LOCAL_FIR_MASK = 0x3004000Dull;
+
+static const uint64_t P9N2_PERV_EC16_LOCAL_FIR_MASK_AND = 0x3004000Eull;
+
+static const uint64_t P9N2_PERV_EC16_LOCAL_FIR_MASK_OR = 0x3004000Full;
+
+static const uint64_t P9N2_PERV_EC17_LOCAL_FIR_MASK = 0x3104000Dull;
+
+static const uint64_t P9N2_PERV_EC17_LOCAL_FIR_MASK_AND = 0x3104000Eull;
+
+static const uint64_t P9N2_PERV_EC17_LOCAL_FIR_MASK_OR = 0x3104000Full;
+
+static const uint64_t P9N2_PERV_EC18_LOCAL_FIR_MASK = 0x3204000Dull;
+
+static const uint64_t P9N2_PERV_EC18_LOCAL_FIR_MASK_AND = 0x3204000Eull;
+
+static const uint64_t P9N2_PERV_EC18_LOCAL_FIR_MASK_OR = 0x3204000Full;
+
+static const uint64_t P9N2_PERV_EC19_LOCAL_FIR_MASK = 0x3304000Dull;
+
+static const uint64_t P9N2_PERV_EC19_LOCAL_FIR_MASK_AND = 0x3304000Eull;
+
+static const uint64_t P9N2_PERV_EC19_LOCAL_FIR_MASK_OR = 0x3304000Full;
+
+static const uint64_t P9N2_PERV_EC20_LOCAL_FIR_MASK = 0x3404000Dull;
+
+static const uint64_t P9N2_PERV_EC20_LOCAL_FIR_MASK_AND = 0x3404000Eull;
+
+static const uint64_t P9N2_PERV_EC20_LOCAL_FIR_MASK_OR = 0x3404000Full;
+
+static const uint64_t P9N2_PERV_EC21_LOCAL_FIR_MASK = 0x3504000Dull;
+
+static const uint64_t P9N2_PERV_EC21_LOCAL_FIR_MASK_AND = 0x3504000Eull;
+
+static const uint64_t P9N2_PERV_EC21_LOCAL_FIR_MASK_OR = 0x3504000Full;
+
+static const uint64_t P9N2_PERV_EC22_LOCAL_FIR_MASK = 0x3604000Dull;
+
+static const uint64_t P9N2_PERV_EC22_LOCAL_FIR_MASK_AND = 0x3604000Eull;
+
+static const uint64_t P9N2_PERV_EC22_LOCAL_FIR_MASK_OR = 0x3604000Full;
+
+static const uint64_t P9N2_PERV_EC23_LOCAL_FIR_MASK = 0x3704000Dull;
+
+static const uint64_t P9N2_PERV_EC23_LOCAL_FIR_MASK_AND = 0x3704000Eull;
+
+static const uint64_t P9N2_PERV_EC23_LOCAL_FIR_MASK_OR = 0x3704000Full;
+
+
+static const uint64_t P9N2_PERV_LOCAL_XSTOP_ERR = 0x00040018ull;
+
+static const uint64_t P9N2_PERV_TP_LOCAL_XSTOP_ERR = 0x01040018ull;
+
+static const uint64_t P9N2_PERV_N0_LOCAL_XSTOP_ERR = 0x02040018ull;
+
+static const uint64_t P9N2_PERV_N1_LOCAL_XSTOP_ERR = 0x03040018ull;
+
+static const uint64_t P9N2_PERV_N2_LOCAL_XSTOP_ERR = 0x04040018ull;
+
+static const uint64_t P9N2_PERV_N3_LOCAL_XSTOP_ERR = 0x05040018ull;
+
+static const uint64_t P9N2_PERV_XB_LOCAL_XSTOP_ERR = 0x06040018ull;
+
+static const uint64_t P9N2_PERV_MC01_LOCAL_XSTOP_ERR = 0x07040018ull;
+
+static const uint64_t P9N2_PERV_MC23_LOCAL_XSTOP_ERR = 0x08040018ull;
+
+static const uint64_t P9N2_PERV_OB0_LOCAL_XSTOP_ERR = 0x09040018ull;
+
+static const uint64_t P9N2_PERV_OB3_LOCAL_XSTOP_ERR = 0x0C040018ull;
+
+static const uint64_t P9N2_PERV_PCI0_LOCAL_XSTOP_ERR = 0x0D040018ull;
+
+static const uint64_t P9N2_PERV_PCI1_LOCAL_XSTOP_ERR = 0x0E040018ull;
+
+static const uint64_t P9N2_PERV_PCI2_LOCAL_XSTOP_ERR = 0x0F040018ull;
+
+static const uint64_t P9N2_PERV_EP00_LOCAL_XSTOP_ERR = 0x10040018ull;
+
+static const uint64_t P9N2_PERV_EP01_LOCAL_XSTOP_ERR = 0x11040018ull;
+
+static const uint64_t P9N2_PERV_EP02_LOCAL_XSTOP_ERR = 0x12040018ull;
+
+static const uint64_t P9N2_PERV_EP03_LOCAL_XSTOP_ERR = 0x13040018ull;
+
+static const uint64_t P9N2_PERV_EP04_LOCAL_XSTOP_ERR = 0x14040018ull;
+
+static const uint64_t P9N2_PERV_EP05_LOCAL_XSTOP_ERR = 0x15040018ull;
+
+static const uint64_t P9N2_PERV_EC00_LOCAL_XSTOP_ERR = 0x20040018ull;
+
+static const uint64_t P9N2_PERV_EC01_LOCAL_XSTOP_ERR = 0x21040018ull;
+
+static const uint64_t P9N2_PERV_EC02_LOCAL_XSTOP_ERR = 0x22040018ull;
+
+static const uint64_t P9N2_PERV_EC03_LOCAL_XSTOP_ERR = 0x23040018ull;
+
+static const uint64_t P9N2_PERV_EC04_LOCAL_XSTOP_ERR = 0x24040018ull;
+
+static const uint64_t P9N2_PERV_EC05_LOCAL_XSTOP_ERR = 0x25040018ull;
+
+static const uint64_t P9N2_PERV_EC06_LOCAL_XSTOP_ERR = 0x26040018ull;
+
+static const uint64_t P9N2_PERV_EC07_LOCAL_XSTOP_ERR = 0x27040018ull;
+
+static const uint64_t P9N2_PERV_EC08_LOCAL_XSTOP_ERR = 0x28040018ull;
+
+static const uint64_t P9N2_PERV_EC09_LOCAL_XSTOP_ERR = 0x29040018ull;
+
+static const uint64_t P9N2_PERV_EC10_LOCAL_XSTOP_ERR = 0x2A040018ull;
+
+static const uint64_t P9N2_PERV_EC11_LOCAL_XSTOP_ERR = 0x2B040018ull;
+
+static const uint64_t P9N2_PERV_EC12_LOCAL_XSTOP_ERR = 0x2C040018ull;
+
+static const uint64_t P9N2_PERV_EC13_LOCAL_XSTOP_ERR = 0x2D040018ull;
+
+static const uint64_t P9N2_PERV_EC14_LOCAL_XSTOP_ERR = 0x2E040018ull;
+
+static const uint64_t P9N2_PERV_EC15_LOCAL_XSTOP_ERR = 0x2F040018ull;
+
+static const uint64_t P9N2_PERV_EC16_LOCAL_XSTOP_ERR = 0x30040018ull;
+
+static const uint64_t P9N2_PERV_EC17_LOCAL_XSTOP_ERR = 0x31040018ull;
+
+static const uint64_t P9N2_PERV_EC18_LOCAL_XSTOP_ERR = 0x32040018ull;
+
+static const uint64_t P9N2_PERV_EC19_LOCAL_XSTOP_ERR = 0x33040018ull;
+
+static const uint64_t P9N2_PERV_EC20_LOCAL_XSTOP_ERR = 0x34040018ull;
+
+static const uint64_t P9N2_PERV_EC21_LOCAL_XSTOP_ERR = 0x35040018ull;
+
+static const uint64_t P9N2_PERV_EC22_LOCAL_XSTOP_ERR = 0x36040018ull;
+
+static const uint64_t P9N2_PERV_EC23_LOCAL_XSTOP_ERR = 0x37040018ull;
+
+
+static const uint64_t P9N2_PERV_LOCAL_XSTOP_MASK = 0x00040019ull;
+
+static const uint64_t P9N2_PERV_TP_LOCAL_XSTOP_MASK = 0x01040019ull;
+
+static const uint64_t P9N2_PERV_N0_LOCAL_XSTOP_MASK = 0x02040019ull;
+
+static const uint64_t P9N2_PERV_N1_LOCAL_XSTOP_MASK = 0x03040019ull;
+
+static const uint64_t P9N2_PERV_N2_LOCAL_XSTOP_MASK = 0x04040019ull;
+
+static const uint64_t P9N2_PERV_N3_LOCAL_XSTOP_MASK = 0x05040019ull;
+
+static const uint64_t P9N2_PERV_XB_LOCAL_XSTOP_MASK = 0x06040019ull;
+
+static const uint64_t P9N2_PERV_MC01_LOCAL_XSTOP_MASK = 0x07040019ull;
+
+static const uint64_t P9N2_PERV_MC23_LOCAL_XSTOP_MASK = 0x08040019ull;
+
+static const uint64_t P9N2_PERV_OB0_LOCAL_XSTOP_MASK = 0x09040019ull;
+
+static const uint64_t P9N2_PERV_OB3_LOCAL_XSTOP_MASK = 0x0C040019ull;
+
+static const uint64_t P9N2_PERV_PCI0_LOCAL_XSTOP_MASK = 0x0D040019ull;
+
+static const uint64_t P9N2_PERV_PCI1_LOCAL_XSTOP_MASK = 0x0E040019ull;
+
+static const uint64_t P9N2_PERV_PCI2_LOCAL_XSTOP_MASK = 0x0F040019ull;
+
+static const uint64_t P9N2_PERV_EP00_LOCAL_XSTOP_MASK = 0x10040019ull;
+
+static const uint64_t P9N2_PERV_EP01_LOCAL_XSTOP_MASK = 0x11040019ull;
+
+static const uint64_t P9N2_PERV_EP02_LOCAL_XSTOP_MASK = 0x12040019ull;
+
+static const uint64_t P9N2_PERV_EP03_LOCAL_XSTOP_MASK = 0x13040019ull;
+
+static const uint64_t P9N2_PERV_EP04_LOCAL_XSTOP_MASK = 0x14040019ull;
+
+static const uint64_t P9N2_PERV_EP05_LOCAL_XSTOP_MASK = 0x15040019ull;
+
+static const uint64_t P9N2_PERV_EC00_LOCAL_XSTOP_MASK = 0x20040019ull;
+
+static const uint64_t P9N2_PERV_EC01_LOCAL_XSTOP_MASK = 0x21040019ull;
+
+static const uint64_t P9N2_PERV_EC02_LOCAL_XSTOP_MASK = 0x22040019ull;
+
+static const uint64_t P9N2_PERV_EC03_LOCAL_XSTOP_MASK = 0x23040019ull;
+
+static const uint64_t P9N2_PERV_EC04_LOCAL_XSTOP_MASK = 0x24040019ull;
+
+static const uint64_t P9N2_PERV_EC05_LOCAL_XSTOP_MASK = 0x25040019ull;
+
+static const uint64_t P9N2_PERV_EC06_LOCAL_XSTOP_MASK = 0x26040019ull;
+
+static const uint64_t P9N2_PERV_EC07_LOCAL_XSTOP_MASK = 0x27040019ull;
+
+static const uint64_t P9N2_PERV_EC08_LOCAL_XSTOP_MASK = 0x28040019ull;
+
+static const uint64_t P9N2_PERV_EC09_LOCAL_XSTOP_MASK = 0x29040019ull;
+
+static const uint64_t P9N2_PERV_EC10_LOCAL_XSTOP_MASK = 0x2A040019ull;
+
+static const uint64_t P9N2_PERV_EC11_LOCAL_XSTOP_MASK = 0x2B040019ull;
+
+static const uint64_t P9N2_PERV_EC12_LOCAL_XSTOP_MASK = 0x2C040019ull;
+
+static const uint64_t P9N2_PERV_EC13_LOCAL_XSTOP_MASK = 0x2D040019ull;
+
+static const uint64_t P9N2_PERV_EC14_LOCAL_XSTOP_MASK = 0x2E040019ull;
+
+static const uint64_t P9N2_PERV_EC15_LOCAL_XSTOP_MASK = 0x2F040019ull;
+
+static const uint64_t P9N2_PERV_EC16_LOCAL_XSTOP_MASK = 0x30040019ull;
+
+static const uint64_t P9N2_PERV_EC17_LOCAL_XSTOP_MASK = 0x31040019ull;
+
+static const uint64_t P9N2_PERV_EC18_LOCAL_XSTOP_MASK = 0x32040019ull;
+
+static const uint64_t P9N2_PERV_EC19_LOCAL_XSTOP_MASK = 0x33040019ull;
+
+static const uint64_t P9N2_PERV_EC20_LOCAL_XSTOP_MASK = 0x34040019ull;
+
+static const uint64_t P9N2_PERV_EC21_LOCAL_XSTOP_MASK = 0x35040019ull;
+
+static const uint64_t P9N2_PERV_EC22_LOCAL_XSTOP_MASK = 0x36040019ull;
+
+static const uint64_t P9N2_PERV_EC23_LOCAL_XSTOP_MASK = 0x37040019ull;
+
+
+static const uint64_t P9N2_PERV_LSTAT = 0x00030002ull;
+
+static const uint64_t P9N2_PERV_PIB_LSTAT = 0x00030002ull;
+
+static const uint64_t P9N2_PERV_0_PIB2OPB0_LSTAT = 0x00020002ull;
+
+static const uint64_t P9N2_PERV_0_PIB2OPB1_LSTAT = 0x00020012ull;
+
+static const uint64_t P9N2_PERV_PIB2OPB0_LSTAT = 0x00020002ull;
+
+static const uint64_t P9N2_PERV_PIB2OPB1_LSTAT = 0x00020012ull;
+
+
+static const uint32_t P9N2_PERV_M1A_DATA_AREA_0_FSI = 0x00002840ull;
+
+static const uint32_t P9N2_PERV_M1A_DATA_AREA_0_FSI_BYTE = 0x00002900ull;
+
+static const uint64_t P9N2_PERV_M1A_DATA_AREA_0_SCOM = 0x00050040ull;
+
+static const uint64_t P9N2_PERV_PIB_M1A_DATA_AREA_0 = 0x00050040ull;
+
+
+static const uint32_t P9N2_PERV_M1A_DATA_AREA_1_FSI = 0x00002841ull;
+
+static const uint32_t P9N2_PERV_M1A_DATA_AREA_1_FSI_BYTE = 0x00002904ull;
+
+static const uint64_t P9N2_PERV_M1A_DATA_AREA_1_SCOM = 0x00050041ull;
+
+static const uint64_t P9N2_PERV_PIB_M1A_DATA_AREA_1 = 0x00050041ull;
+
+
+static const uint32_t P9N2_PERV_M1A_DATA_AREA_10_FSI = 0x0000284Aull;
+
+static const uint32_t P9N2_PERV_M1A_DATA_AREA_10_FSI_BYTE = 0x00002928ull;
+
+static const uint64_t P9N2_PERV_M1A_DATA_AREA_10_SCOM = 0x0005004Aull;
+
+static const uint64_t P9N2_PERV_PIB_M1A_DATA_AREA_10 = 0x0005004Aull;
+
+
+static const uint32_t P9N2_PERV_M1A_DATA_AREA_11_FSI = 0x0000284Bull;
+
+static const uint32_t P9N2_PERV_M1A_DATA_AREA_11_FSI_BYTE = 0x0000292Cull;
+
+static const uint64_t P9N2_PERV_M1A_DATA_AREA_11_SCOM = 0x0005004Bull;
+
+static const uint64_t P9N2_PERV_PIB_M1A_DATA_AREA_11 = 0x0005004Bull;
+
+
+static const uint32_t P9N2_PERV_M1A_DATA_AREA_12_FSI = 0x0000284Cull;
+
+static const uint32_t P9N2_PERV_M1A_DATA_AREA_12_FSI_BYTE = 0x00002930ull;
+
+static const uint64_t P9N2_PERV_M1A_DATA_AREA_12_SCOM = 0x0005004Cull;
+
+static const uint64_t P9N2_PERV_PIB_M1A_DATA_AREA_12 = 0x0005004Cull;
+
+
+static const uint32_t P9N2_PERV_M1A_DATA_AREA_13_FSI = 0x0000284Dull;
+
+static const uint32_t P9N2_PERV_M1A_DATA_AREA_13_FSI_BYTE = 0x00002934ull;
+
+static const uint64_t P9N2_PERV_M1A_DATA_AREA_13_SCOM = 0x0005004Dull;
+
+static const uint64_t P9N2_PERV_PIB_M1A_DATA_AREA_13 = 0x0005004Dull;
+
+
+static const uint32_t P9N2_PERV_M1A_DATA_AREA_14_FSI = 0x0000284Eull;
+
+static const uint32_t P9N2_PERV_M1A_DATA_AREA_14_FSI_BYTE = 0x00002938ull;
+
+static const uint64_t P9N2_PERV_M1A_DATA_AREA_14_SCOM = 0x0005004Eull;
+
+static const uint64_t P9N2_PERV_PIB_M1A_DATA_AREA_14 = 0x0005004Eull;
+
+
+static const uint32_t P9N2_PERV_M1A_DATA_AREA_15_FSI = 0x0000284Full;
+
+static const uint32_t P9N2_PERV_M1A_DATA_AREA_15_FSI_BYTE = 0x0000293Cull;
+
+static const uint64_t P9N2_PERV_M1A_DATA_AREA_15_SCOM = 0x0005004Full;
+
+static const uint64_t P9N2_PERV_PIB_M1A_DATA_AREA_15 = 0x0005004Full;
+
+
+static const uint32_t P9N2_PERV_M1A_DATA_AREA_2_FSI = 0x00002842ull;
+
+static const uint32_t P9N2_PERV_M1A_DATA_AREA_2_FSI_BYTE = 0x00002908ull;
+
+static const uint64_t P9N2_PERV_M1A_DATA_AREA_2_SCOM = 0x00050042ull;
+
+static const uint64_t P9N2_PERV_PIB_M1A_DATA_AREA_2 = 0x00050042ull;
+
+
+static const uint32_t P9N2_PERV_M1A_DATA_AREA_3_FSI = 0x00002843ull;
+
+static const uint32_t P9N2_PERV_M1A_DATA_AREA_3_FSI_BYTE = 0x0000290Cull;
+
+static const uint64_t P9N2_PERV_M1A_DATA_AREA_3_SCOM = 0x00050043ull;
+
+static const uint64_t P9N2_PERV_PIB_M1A_DATA_AREA_3 = 0x00050043ull;
+
+
+static const uint32_t P9N2_PERV_M1A_DATA_AREA_4_FSI = 0x00002844ull;
+
+static const uint32_t P9N2_PERV_M1A_DATA_AREA_4_FSI_BYTE = 0x00002910ull;
+
+static const uint64_t P9N2_PERV_M1A_DATA_AREA_4_SCOM = 0x00050044ull;
+
+static const uint64_t P9N2_PERV_PIB_M1A_DATA_AREA_4 = 0x00050044ull;
+
+
+static const uint32_t P9N2_PERV_M1A_DATA_AREA_5_FSI = 0x00002845ull;
+
+static const uint32_t P9N2_PERV_M1A_DATA_AREA_5_FSI_BYTE = 0x00002914ull;
+
+static const uint64_t P9N2_PERV_M1A_DATA_AREA_5_SCOM = 0x00050045ull;
+
+static const uint64_t P9N2_PERV_PIB_M1A_DATA_AREA_5 = 0x00050045ull;
+
+
+static const uint32_t P9N2_PERV_M1A_DATA_AREA_6_FSI = 0x00002846ull;
+
+static const uint32_t P9N2_PERV_M1A_DATA_AREA_6_FSI_BYTE = 0x00002918ull;
+
+static const uint64_t P9N2_PERV_M1A_DATA_AREA_6_SCOM = 0x00050046ull;
+
+static const uint64_t P9N2_PERV_PIB_M1A_DATA_AREA_6 = 0x00050046ull;
+
+
+static const uint32_t P9N2_PERV_M1A_DATA_AREA_7_FSI = 0x00002847ull;
+
+static const uint32_t P9N2_PERV_M1A_DATA_AREA_7_FSI_BYTE = 0x0000291Cull;
+
+static const uint64_t P9N2_PERV_M1A_DATA_AREA_7_SCOM = 0x00050047ull;
+
+static const uint64_t P9N2_PERV_PIB_M1A_DATA_AREA_7 = 0x00050047ull;
+
+
+static const uint32_t P9N2_PERV_M1A_DATA_AREA_8_FSI = 0x00002848ull;
+
+static const uint32_t P9N2_PERV_M1A_DATA_AREA_8_FSI_BYTE = 0x00002920ull;
+
+static const uint64_t P9N2_PERV_M1A_DATA_AREA_8_SCOM = 0x00050048ull;
+
+static const uint64_t P9N2_PERV_PIB_M1A_DATA_AREA_8 = 0x00050048ull;
+
+
+static const uint32_t P9N2_PERV_M1A_DATA_AREA_9_FSI = 0x00002849ull;
+
+static const uint32_t P9N2_PERV_M1A_DATA_AREA_9_FSI_BYTE = 0x00002924ull;
+
+static const uint64_t P9N2_PERV_M1A_DATA_AREA_9_SCOM = 0x00050049ull;
+
+static const uint64_t P9N2_PERV_PIB_M1A_DATA_AREA_9 = 0x00050049ull;
+
+
+static const uint32_t P9N2_PERV_M1B_DATA_AREA_0_FSI = 0x00002880ull;
+
+static const uint32_t P9N2_PERV_M1B_DATA_AREA_0_FSI_BYTE = 0x00002A00ull;
+
+static const uint64_t P9N2_PERV_M1B_DATA_AREA_0_SCOM = 0x00050080ull;
+
+static const uint64_t P9N2_PERV_PIB_M1B_DATA_AREA_0 = 0x00050080ull;
+
+
+static const uint32_t P9N2_PERV_M1B_DATA_AREA_1_FSI = 0x00002881ull;
+
+static const uint32_t P9N2_PERV_M1B_DATA_AREA_1_FSI_BYTE = 0x00002A04ull;
+
+static const uint64_t P9N2_PERV_M1B_DATA_AREA_1_SCOM = 0x00050081ull;
+
+static const uint64_t P9N2_PERV_PIB_M1B_DATA_AREA_1 = 0x00050081ull;
+
+
+static const uint32_t P9N2_PERV_M1B_DATA_AREA_10_FSI = 0x0000288Aull;
+
+static const uint32_t P9N2_PERV_M1B_DATA_AREA_10_FSI_BYTE = 0x00002A28ull;
+
+static const uint64_t P9N2_PERV_M1B_DATA_AREA_10_SCOM = 0x0005008Aull;
+
+static const uint64_t P9N2_PERV_PIB_M1B_DATA_AREA_10 = 0x0005008Aull;
+
+
+static const uint32_t P9N2_PERV_M1B_DATA_AREA_11_FSI = 0x0000288Bull;
+
+static const uint32_t P9N2_PERV_M1B_DATA_AREA_11_FSI_BYTE = 0x00002A2Cull;
+
+static const uint64_t P9N2_PERV_M1B_DATA_AREA_11_SCOM = 0x0005008Bull;
+
+static const uint64_t P9N2_PERV_PIB_M1B_DATA_AREA_11 = 0x0005008Bull;
+
+
+static const uint32_t P9N2_PERV_M1B_DATA_AREA_12_FSI = 0x0000288Cull;
+
+static const uint32_t P9N2_PERV_M1B_DATA_AREA_12_FSI_BYTE = 0x00002A30ull;
+
+static const uint64_t P9N2_PERV_M1B_DATA_AREA_12_SCOM = 0x0005008Cull;
+
+static const uint64_t P9N2_PERV_PIB_M1B_DATA_AREA_12 = 0x0005008Cull;
+
+
+static const uint32_t P9N2_PERV_M1B_DATA_AREA_13_FSI = 0x0000288Dull;
+
+static const uint32_t P9N2_PERV_M1B_DATA_AREA_13_FSI_BYTE = 0x00002A34ull;
+
+static const uint64_t P9N2_PERV_M1B_DATA_AREA_13_SCOM = 0x0005008Dull;
+
+static const uint64_t P9N2_PERV_PIB_M1B_DATA_AREA_13 = 0x0005008Dull;
+
+
+static const uint32_t P9N2_PERV_M1B_DATA_AREA_14_FSI = 0x0000288Eull;
+
+static const uint32_t P9N2_PERV_M1B_DATA_AREA_14_FSI_BYTE = 0x00002A38ull;
+
+static const uint64_t P9N2_PERV_M1B_DATA_AREA_14_SCOM = 0x0005008Eull;
+
+static const uint64_t P9N2_PERV_PIB_M1B_DATA_AREA_14 = 0x0005008Eull;
+
+
+static const uint32_t P9N2_PERV_M1B_DATA_AREA_15_FSI = 0x0000288Full;
+
+static const uint32_t P9N2_PERV_M1B_DATA_AREA_15_FSI_BYTE = 0x00002A3Cull;
+
+static const uint64_t P9N2_PERV_M1B_DATA_AREA_15_SCOM = 0x0005008Full;
+
+static const uint64_t P9N2_PERV_PIB_M1B_DATA_AREA_15 = 0x0005008Full;
+
+
+static const uint32_t P9N2_PERV_M1B_DATA_AREA_2_FSI = 0x00002882ull;
+
+static const uint32_t P9N2_PERV_M1B_DATA_AREA_2_FSI_BYTE = 0x00002A08ull;
+
+static const uint64_t P9N2_PERV_M1B_DATA_AREA_2_SCOM = 0x00050082ull;
+
+static const uint64_t P9N2_PERV_PIB_M1B_DATA_AREA_2 = 0x00050082ull;
+
+
+static const uint32_t P9N2_PERV_M1B_DATA_AREA_3_FSI = 0x00002883ull;
+
+static const uint32_t P9N2_PERV_M1B_DATA_AREA_3_FSI_BYTE = 0x00002A0Cull;
+
+static const uint64_t P9N2_PERV_M1B_DATA_AREA_3_SCOM = 0x00050083ull;
+
+static const uint64_t P9N2_PERV_PIB_M1B_DATA_AREA_3 = 0x00050083ull;
+
+
+static const uint32_t P9N2_PERV_M1B_DATA_AREA_4_FSI = 0x00002884ull;
+
+static const uint32_t P9N2_PERV_M1B_DATA_AREA_4_FSI_BYTE = 0x00002A10ull;
+
+static const uint64_t P9N2_PERV_M1B_DATA_AREA_4_SCOM = 0x00050084ull;
+
+static const uint64_t P9N2_PERV_PIB_M1B_DATA_AREA_4 = 0x00050084ull;
+
+
+static const uint32_t P9N2_PERV_M1B_DATA_AREA_5_FSI = 0x00002885ull;
+
+static const uint32_t P9N2_PERV_M1B_DATA_AREA_5_FSI_BYTE = 0x00002A14ull;
+
+static const uint64_t P9N2_PERV_M1B_DATA_AREA_5_SCOM = 0x00050085ull;
+
+static const uint64_t P9N2_PERV_PIB_M1B_DATA_AREA_5 = 0x00050085ull;
+
+
+static const uint32_t P9N2_PERV_M1B_DATA_AREA_6_FSI = 0x00002886ull;
+
+static const uint32_t P9N2_PERV_M1B_DATA_AREA_6_FSI_BYTE = 0x00002A18ull;
+
+static const uint64_t P9N2_PERV_M1B_DATA_AREA_6_SCOM = 0x00050086ull;
+
+static const uint64_t P9N2_PERV_PIB_M1B_DATA_AREA_6 = 0x00050086ull;
+
+
+static const uint32_t P9N2_PERV_M1B_DATA_AREA_7_FSI = 0x00002887ull;
+
+static const uint32_t P9N2_PERV_M1B_DATA_AREA_7_FSI_BYTE = 0x00002A1Cull;
+
+static const uint64_t P9N2_PERV_M1B_DATA_AREA_7_SCOM = 0x00050087ull;
+
+static const uint64_t P9N2_PERV_PIB_M1B_DATA_AREA_7 = 0x00050087ull;
+
+
+static const uint32_t P9N2_PERV_M1B_DATA_AREA_8_FSI = 0x00002888ull;
+
+static const uint32_t P9N2_PERV_M1B_DATA_AREA_8_FSI_BYTE = 0x00002A20ull;
+
+static const uint64_t P9N2_PERV_M1B_DATA_AREA_8_SCOM = 0x00050088ull;
+
+static const uint64_t P9N2_PERV_PIB_M1B_DATA_AREA_8 = 0x00050088ull;
+
+
+static const uint32_t P9N2_PERV_M1B_DATA_AREA_9_FSI = 0x00002889ull;
+
+static const uint32_t P9N2_PERV_M1B_DATA_AREA_9_FSI_BYTE = 0x00002A24ull;
+
+static const uint64_t P9N2_PERV_M1B_DATA_AREA_9_SCOM = 0x00050089ull;
+
+static const uint64_t P9N2_PERV_PIB_M1B_DATA_AREA_9 = 0x00050089ull;
+
+
+static const uint32_t P9N2_PERV_M2A_DATA_AREA_0_FSI = 0x000028C0ull;
+
+static const uint32_t P9N2_PERV_M2A_DATA_AREA_0_FSI_BYTE = 0x00002B00ull;
+
+static const uint64_t P9N2_PERV_M2A_DATA_AREA_0_SCOM = 0x000500C0ull;
+
+static const uint64_t P9N2_PERV_PIB_M2A_DATA_AREA_0 = 0x000500C0ull;
+
+
+static const uint32_t P9N2_PERV_M2A_DATA_AREA_1_FSI = 0x000028C1ull;
+
+static const uint32_t P9N2_PERV_M2A_DATA_AREA_1_FSI_BYTE = 0x00002B04ull;
+
+static const uint64_t P9N2_PERV_M2A_DATA_AREA_1_SCOM = 0x000500C1ull;
+
+static const uint64_t P9N2_PERV_PIB_M2A_DATA_AREA_1 = 0x000500C1ull;
+
+
+static const uint32_t P9N2_PERV_M2A_DATA_AREA_10_FSI = 0x000028CAull;
+
+static const uint32_t P9N2_PERV_M2A_DATA_AREA_10_FSI_BYTE = 0x00002B28ull;
+
+static const uint64_t P9N2_PERV_M2A_DATA_AREA_10_SCOM = 0x000500CAull;
+
+static const uint64_t P9N2_PERV_PIB_M2A_DATA_AREA_10 = 0x000500CAull;
+
+
+static const uint32_t P9N2_PERV_M2A_DATA_AREA_11_FSI = 0x000028CBull;
+
+static const uint32_t P9N2_PERV_M2A_DATA_AREA_11_FSI_BYTE = 0x00002B2Cull;
+
+static const uint64_t P9N2_PERV_M2A_DATA_AREA_11_SCOM = 0x000500CBull;
+
+static const uint64_t P9N2_PERV_PIB_M2A_DATA_AREA_11 = 0x000500CBull;
+
+
+static const uint32_t P9N2_PERV_M2A_DATA_AREA_12_FSI = 0x000028CCull;
+
+static const uint32_t P9N2_PERV_M2A_DATA_AREA_12_FSI_BYTE = 0x00002B30ull;
+
+static const uint64_t P9N2_PERV_M2A_DATA_AREA_12_SCOM = 0x000500CCull;
+
+static const uint64_t P9N2_PERV_PIB_M2A_DATA_AREA_12 = 0x000500CCull;
+
+
+static const uint32_t P9N2_PERV_M2A_DATA_AREA_13_FSI = 0x000028CDull;
+
+static const uint32_t P9N2_PERV_M2A_DATA_AREA_13_FSI_BYTE = 0x00002B34ull;
+
+static const uint64_t P9N2_PERV_M2A_DATA_AREA_13_SCOM = 0x000500CDull;
+
+static const uint64_t P9N2_PERV_PIB_M2A_DATA_AREA_13 = 0x000500CDull;
+
+
+static const uint32_t P9N2_PERV_M2A_DATA_AREA_14_FSI = 0x000028CEull;
+
+static const uint32_t P9N2_PERV_M2A_DATA_AREA_14_FSI_BYTE = 0x00002B38ull;
+
+static const uint64_t P9N2_PERV_M2A_DATA_AREA_14_SCOM = 0x000500CEull;
+
+static const uint64_t P9N2_PERV_PIB_M2A_DATA_AREA_14 = 0x000500CEull;
+
+
+static const uint32_t P9N2_PERV_M2A_DATA_AREA_15_FSI = 0x000028CFull;
+
+static const uint32_t P9N2_PERV_M2A_DATA_AREA_15_FSI_BYTE = 0x00002B3Cull;
+
+static const uint64_t P9N2_PERV_M2A_DATA_AREA_15_SCOM = 0x000500CFull;
+
+static const uint64_t P9N2_PERV_PIB_M2A_DATA_AREA_15 = 0x000500CFull;
+
+
+static const uint32_t P9N2_PERV_M2A_DATA_AREA_2_FSI = 0x000028C2ull;
+
+static const uint32_t P9N2_PERV_M2A_DATA_AREA_2_FSI_BYTE = 0x00002B08ull;
+
+static const uint64_t P9N2_PERV_M2A_DATA_AREA_2_SCOM = 0x000500C2ull;
+
+static const uint64_t P9N2_PERV_PIB_M2A_DATA_AREA_2 = 0x000500C2ull;
+
+
+static const uint32_t P9N2_PERV_M2A_DATA_AREA_3_FSI = 0x000028C3ull;
+
+static const uint32_t P9N2_PERV_M2A_DATA_AREA_3_FSI_BYTE = 0x00002B0Cull;
+
+static const uint64_t P9N2_PERV_M2A_DATA_AREA_3_SCOM = 0x000500C3ull;
+
+static const uint64_t P9N2_PERV_PIB_M2A_DATA_AREA_3 = 0x000500C3ull;
+
+
+static const uint32_t P9N2_PERV_M2A_DATA_AREA_4_FSI = 0x000028C4ull;
+
+static const uint32_t P9N2_PERV_M2A_DATA_AREA_4_FSI_BYTE = 0x00002B10ull;
+
+static const uint64_t P9N2_PERV_M2A_DATA_AREA_4_SCOM = 0x000500C4ull;
+
+static const uint64_t P9N2_PERV_PIB_M2A_DATA_AREA_4 = 0x000500C4ull;
+
+
+static const uint32_t P9N2_PERV_M2A_DATA_AREA_5_FSI = 0x000028C5ull;
+
+static const uint32_t P9N2_PERV_M2A_DATA_AREA_5_FSI_BYTE = 0x00002B14ull;
+
+static const uint64_t P9N2_PERV_M2A_DATA_AREA_5_SCOM = 0x000500C5ull;
+
+static const uint64_t P9N2_PERV_PIB_M2A_DATA_AREA_5 = 0x000500C5ull;
+
+
+static const uint32_t P9N2_PERV_M2A_DATA_AREA_6_FSI = 0x000028C6ull;
+
+static const uint32_t P9N2_PERV_M2A_DATA_AREA_6_FSI_BYTE = 0x00002B18ull;
+
+static const uint64_t P9N2_PERV_M2A_DATA_AREA_6_SCOM = 0x000500C6ull;
+
+static const uint64_t P9N2_PERV_PIB_M2A_DATA_AREA_6 = 0x000500C6ull;
+
+
+static const uint32_t P9N2_PERV_M2A_DATA_AREA_7_FSI = 0x000028C7ull;
+
+static const uint32_t P9N2_PERV_M2A_DATA_AREA_7_FSI_BYTE = 0x00002B1Cull;
+
+static const uint64_t P9N2_PERV_M2A_DATA_AREA_7_SCOM = 0x000500C7ull;
+
+static const uint64_t P9N2_PERV_PIB_M2A_DATA_AREA_7 = 0x000500C7ull;
+
+
+static const uint32_t P9N2_PERV_M2A_DATA_AREA_8_FSI = 0x000028C8ull;
+
+static const uint32_t P9N2_PERV_M2A_DATA_AREA_8_FSI_BYTE = 0x00002B20ull;
+
+static const uint64_t P9N2_PERV_M2A_DATA_AREA_8_SCOM = 0x000500C8ull;
+
+static const uint64_t P9N2_PERV_PIB_M2A_DATA_AREA_8 = 0x000500C8ull;
+
+
+static const uint32_t P9N2_PERV_M2A_DATA_AREA_9_FSI = 0x000028C9ull;
+
+static const uint32_t P9N2_PERV_M2A_DATA_AREA_9_FSI_BYTE = 0x00002B24ull;
+
+static const uint64_t P9N2_PERV_M2A_DATA_AREA_9_SCOM = 0x000500C9ull;
+
+static const uint64_t P9N2_PERV_PIB_M2A_DATA_AREA_9 = 0x000500C9ull;
+
+
+static const uint32_t P9N2_PERV_M2B_DATA_AREA_0_FSI = 0x00002900ull;
+
+static const uint32_t P9N2_PERV_M2B_DATA_AREA_0_FSI_BYTE = 0x00002C00ull;
+
+static const uint64_t P9N2_PERV_M2B_DATA_AREA_0_SCOM = 0x00050100ull;
+
+static const uint64_t P9N2_PERV_PIB_M2B_DATA_AREA_0 = 0x00050100ull;
+
+
+static const uint32_t P9N2_PERV_M2B_DATA_AREA_1_FSI = 0x00002901ull;
+
+static const uint32_t P9N2_PERV_M2B_DATA_AREA_1_FSI_BYTE = 0x00002C04ull;
+
+static const uint64_t P9N2_PERV_M2B_DATA_AREA_1_SCOM = 0x00050101ull;
+
+static const uint64_t P9N2_PERV_PIB_M2B_DATA_AREA_1 = 0x00050101ull;
+
+
+static const uint32_t P9N2_PERV_M2B_DATA_AREA_10_FSI = 0x0000290Aull;
+
+static const uint32_t P9N2_PERV_M2B_DATA_AREA_10_FSI_BYTE = 0x00002C28ull;
+
+static const uint64_t P9N2_PERV_M2B_DATA_AREA_10_SCOM = 0x0005010Aull;
+
+static const uint64_t P9N2_PERV_PIB_M2B_DATA_AREA_10 = 0x0005010Aull;
+
+
+static const uint32_t P9N2_PERV_M2B_DATA_AREA_11_FSI = 0x0000290Bull;
+
+static const uint32_t P9N2_PERV_M2B_DATA_AREA_11_FSI_BYTE = 0x00002C2Cull;
+
+static const uint64_t P9N2_PERV_M2B_DATA_AREA_11_SCOM = 0x0005010Bull;
+
+static const uint64_t P9N2_PERV_PIB_M2B_DATA_AREA_11 = 0x0005010Bull;
+
+
+static const uint32_t P9N2_PERV_M2B_DATA_AREA_12_FSI = 0x0000290Cull;
+
+static const uint32_t P9N2_PERV_M2B_DATA_AREA_12_FSI_BYTE = 0x00002C30ull;
+
+static const uint64_t P9N2_PERV_M2B_DATA_AREA_12_SCOM = 0x0005010Cull;
+
+static const uint64_t P9N2_PERV_PIB_M2B_DATA_AREA_12 = 0x0005010Cull;
+
+
+static const uint32_t P9N2_PERV_M2B_DATA_AREA_13_FSI = 0x0000290Dull;
+
+static const uint32_t P9N2_PERV_M2B_DATA_AREA_13_FSI_BYTE = 0x00002C34ull;
+
+static const uint64_t P9N2_PERV_M2B_DATA_AREA_13_SCOM = 0x0005010Dull;
+
+static const uint64_t P9N2_PERV_PIB_M2B_DATA_AREA_13 = 0x0005010Dull;
+
+
+static const uint32_t P9N2_PERV_M2B_DATA_AREA_14_FSI = 0x0000290Eull;
+
+static const uint32_t P9N2_PERV_M2B_DATA_AREA_14_FSI_BYTE = 0x00002C38ull;
+
+static const uint64_t P9N2_PERV_M2B_DATA_AREA_14_SCOM = 0x0005010Eull;
+
+static const uint64_t P9N2_PERV_PIB_M2B_DATA_AREA_14 = 0x0005010Eull;
+
+
+static const uint32_t P9N2_PERV_M2B_DATA_AREA_15_FSI = 0x0000290Full;
+
+static const uint32_t P9N2_PERV_M2B_DATA_AREA_15_FSI_BYTE = 0x00002C3Cull;
+
+static const uint64_t P9N2_PERV_M2B_DATA_AREA_15_SCOM = 0x0005010Full;
+
+static const uint64_t P9N2_PERV_PIB_M2B_DATA_AREA_15 = 0x0005010Full;
+
+
+static const uint32_t P9N2_PERV_M2B_DATA_AREA_2_FSI = 0x00002902ull;
+
+static const uint32_t P9N2_PERV_M2B_DATA_AREA_2_FSI_BYTE = 0x00002C08ull;
+
+static const uint64_t P9N2_PERV_M2B_DATA_AREA_2_SCOM = 0x00050102ull;
+
+static const uint64_t P9N2_PERV_PIB_M2B_DATA_AREA_2 = 0x00050102ull;
+
+
+static const uint32_t P9N2_PERV_M2B_DATA_AREA_3_FSI = 0x00002903ull;
+
+static const uint32_t P9N2_PERV_M2B_DATA_AREA_3_FSI_BYTE = 0x00002C0Cull;
+
+static const uint64_t P9N2_PERV_M2B_DATA_AREA_3_SCOM = 0x00050103ull;
+
+static const uint64_t P9N2_PERV_PIB_M2B_DATA_AREA_3 = 0x00050103ull;
+
+
+static const uint32_t P9N2_PERV_M2B_DATA_AREA_4_FSI = 0x00002904ull;
+
+static const uint32_t P9N2_PERV_M2B_DATA_AREA_4_FSI_BYTE = 0x00002C10ull;
+
+static const uint64_t P9N2_PERV_M2B_DATA_AREA_4_SCOM = 0x00050104ull;
+
+static const uint64_t P9N2_PERV_PIB_M2B_DATA_AREA_4 = 0x00050104ull;
+
+
+static const uint32_t P9N2_PERV_M2B_DATA_AREA_5_FSI = 0x00002905ull;
+
+static const uint32_t P9N2_PERV_M2B_DATA_AREA_5_FSI_BYTE = 0x00002C14ull;
+
+static const uint64_t P9N2_PERV_M2B_DATA_AREA_5_SCOM = 0x00050105ull;
+
+static const uint64_t P9N2_PERV_PIB_M2B_DATA_AREA_5 = 0x00050105ull;
+
+
+static const uint32_t P9N2_PERV_M2B_DATA_AREA_6_FSI = 0x00002906ull;
+
+static const uint32_t P9N2_PERV_M2B_DATA_AREA_6_FSI_BYTE = 0x00002C18ull;
+
+static const uint64_t P9N2_PERV_M2B_DATA_AREA_6_SCOM = 0x00050106ull;
+
+static const uint64_t P9N2_PERV_PIB_M2B_DATA_AREA_6 = 0x00050106ull;
+
+
+static const uint32_t P9N2_PERV_M2B_DATA_AREA_7_FSI = 0x00002907ull;
+
+static const uint32_t P9N2_PERV_M2B_DATA_AREA_7_FSI_BYTE = 0x00002C1Cull;
+
+static const uint64_t P9N2_PERV_M2B_DATA_AREA_7_SCOM = 0x00050107ull;
+
+static const uint64_t P9N2_PERV_PIB_M2B_DATA_AREA_7 = 0x00050107ull;
+
+
+static const uint32_t P9N2_PERV_M2B_DATA_AREA_8_FSI = 0x00002908ull;
+
+static const uint32_t P9N2_PERV_M2B_DATA_AREA_8_FSI_BYTE = 0x00002C20ull;
+
+static const uint64_t P9N2_PERV_M2B_DATA_AREA_8_SCOM = 0x00050108ull;
+
+static const uint64_t P9N2_PERV_PIB_M2B_DATA_AREA_8 = 0x00050108ull;
+
+
+static const uint32_t P9N2_PERV_M2B_DATA_AREA_9_FSI = 0x00002909ull;
+
+static const uint32_t P9N2_PERV_M2B_DATA_AREA_9_FSI_BYTE = 0x00002C24ull;
+
+static const uint64_t P9N2_PERV_M2B_DATA_AREA_9_SCOM = 0x00050109ull;
+
+static const uint64_t P9N2_PERV_PIB_M2B_DATA_AREA_9 = 0x00050109ull;
+
+
+static const uint32_t P9N2_PERV_MAILBOX_1_HEADER_COMMAND_0_A_FSI = 0x00002821ull;
+
+static const uint32_t P9N2_PERV_MAILBOX_1_HEADER_COMMAND_0_A_FSI_BYTE = 0x00002884ull;
+
+static const uint64_t P9N2_PERV_MAILBOX_1_HEADER_COMMAND_0_A_SCOM = 0x00050021ull;
+
+static const uint64_t P9N2_PERV_PIB_MAILBOX_1_HEADER_COMMAND_0_A = 0x00050021ull;
+
+
+static const uint32_t P9N2_PERV_MAILBOX_1_HEADER_COMMAND_0_B_FSI = 0x00002825ull;
+
+static const uint32_t P9N2_PERV_MAILBOX_1_HEADER_COMMAND_0_B_FSI_BYTE = 0x00002894ull;
+
+static const uint64_t P9N2_PERV_MAILBOX_1_HEADER_COMMAND_0_B_SCOM = 0x00050025ull;
+
+static const uint64_t P9N2_PERV_PIB_MAILBOX_1_HEADER_COMMAND_0_B = 0x00050025ull;
+
+
+static const uint32_t P9N2_PERV_MAILBOX_1_HEADER_COMMAND_1_A_FSI = 0x00002822ull;
+
+static const uint32_t P9N2_PERV_MAILBOX_1_HEADER_COMMAND_1_A_FSI_BYTE = 0x00002888ull;
+
+static const uint64_t P9N2_PERV_MAILBOX_1_HEADER_COMMAND_1_A_SCOM = 0x00050022ull;
+
+static const uint64_t P9N2_PERV_PIB_MAILBOX_1_HEADER_COMMAND_1_A = 0x00050022ull;
+
+
+static const uint32_t P9N2_PERV_MAILBOX_1_HEADER_COMMAND_1_B_FSI = 0x00002826ull;
+
+static const uint32_t P9N2_PERV_MAILBOX_1_HEADER_COMMAND_1_B_FSI_BYTE = 0x00002898ull;
+
+static const uint64_t P9N2_PERV_MAILBOX_1_HEADER_COMMAND_1_B_SCOM = 0x00050026ull;
+
+static const uint64_t P9N2_PERV_PIB_MAILBOX_1_HEADER_COMMAND_1_B = 0x00050026ull;
+
+
+static const uint32_t P9N2_PERV_MAILBOX_1_HEADER_COMMAND_2_A_FSI = 0x00002823ull;
+
+static const uint32_t P9N2_PERV_MAILBOX_1_HEADER_COMMAND_2_A_FSI_BYTE = 0x0000288Cull;
+
+static const uint64_t P9N2_PERV_MAILBOX_1_HEADER_COMMAND_2_A_SCOM = 0x00050023ull;
+
+static const uint64_t P9N2_PERV_PIB_MAILBOX_1_HEADER_COMMAND_2_A = 0x00050023ull;
+
+
+static const uint32_t P9N2_PERV_MAILBOX_1_HEADER_COMMAND_2_B_FSI = 0x00002827ull;
+
+static const uint32_t P9N2_PERV_MAILBOX_1_HEADER_COMMAND_2_B_FSI_BYTE = 0x0000289Cull;
+
+static const uint64_t P9N2_PERV_MAILBOX_1_HEADER_COMMAND_2_B_SCOM = 0x00050027ull;
+
+static const uint64_t P9N2_PERV_PIB_MAILBOX_1_HEADER_COMMAND_2_B = 0x00050027ull;
+
+
+static const uint32_t P9N2_PERV_MAILBOX_1_SLAVE_A_DOORBELL_INTERRUPT_MASK_1_FSI = 0x00002833ull;
+
+static const uint32_t P9N2_PERV_MAILBOX_1_SLAVE_A_DOORBELL_INTERRUPT_MASK_1_FSI_BYTE = 0x000028CCull;
+
+static const uint64_t P9N2_PERV_MAILBOX_1_SLAVE_A_DOORBELL_INTERRUPT_MASK_1_SCOM = 0x00050033ull;
+
+static const uint64_t P9N2_PERV_MAILBOX_1_SLAVE_A_DOORBELL_INTERRUPT_MASK_1_SCOM1 = 0x00050034ull;
+
+static const uint64_t P9N2_PERV_PIB_MAILBOX_1_SLAVE_A_DOORBELL_INTERRUPT_MASK_1_WOR = 0x00050033ull;
+
+static const uint64_t P9N2_PERV_PIB_MAILBOX_1_SLAVE_A_DOORBELL_INTERRUPT_MASK_1_CLEAR = 0x00050034ull;
+
+
+static const uint32_t P9N2_PERV_MAILBOX_2_HEADER_COMMAND_0_A_FSI = 0x00002829ull;
+
+static const uint32_t P9N2_PERV_MAILBOX_2_HEADER_COMMAND_0_A_FSI_BYTE = 0x000028A4ull;
+
+static const uint64_t P9N2_PERV_MAILBOX_2_HEADER_COMMAND_0_A_SCOM = 0x00050029ull;
+
+static const uint64_t P9N2_PERV_PIB_MAILBOX_2_HEADER_COMMAND_0_A = 0x00050029ull;
+
+
+static const uint32_t P9N2_PERV_MAILBOX_2_HEADER_COMMAND_0_B_FSI = 0x0000282Dull;
+
+static const uint32_t P9N2_PERV_MAILBOX_2_HEADER_COMMAND_0_B_FSI_BYTE = 0x000028B4ull;
+
+static const uint64_t P9N2_PERV_MAILBOX_2_HEADER_COMMAND_0_B_SCOM = 0x0005002Dull;
+
+static const uint64_t P9N2_PERV_PIB_MAILBOX_2_HEADER_COMMAND_0_B = 0x0005002Dull;
+
+
+static const uint32_t P9N2_PERV_MAILBOX_2_HEADER_COMMAND_1_A_FSI = 0x0000282Aull;
+
+static const uint32_t P9N2_PERV_MAILBOX_2_HEADER_COMMAND_1_A_FSI_BYTE = 0x000028A8ull;
+
+static const uint64_t P9N2_PERV_MAILBOX_2_HEADER_COMMAND_1_A_SCOM = 0x0005002Aull;
+
+static const uint64_t P9N2_PERV_PIB_MAILBOX_2_HEADER_COMMAND_1_A = 0x0005002Aull;
+
+
+static const uint32_t P9N2_PERV_MAILBOX_2_HEADER_COMMAND_1_B_FSI = 0x0000282Eull;
+
+static const uint32_t P9N2_PERV_MAILBOX_2_HEADER_COMMAND_1_B_FSI_BYTE = 0x000028B8ull;
+
+static const uint64_t P9N2_PERV_MAILBOX_2_HEADER_COMMAND_1_B_SCOM = 0x0005002Eull;
+
+static const uint64_t P9N2_PERV_PIB_MAILBOX_2_HEADER_COMMAND_1_B = 0x0005002Eull;
+
+
+static const uint32_t P9N2_PERV_MAILBOX_2_HEADER_COMMAND_2_A_FSI = 0x0000282Bull;
+
+static const uint32_t P9N2_PERV_MAILBOX_2_HEADER_COMMAND_2_A_FSI_BYTE = 0x000028ACull;
+
+static const uint64_t P9N2_PERV_MAILBOX_2_HEADER_COMMAND_2_A_SCOM = 0x0005002Bull;
+
+static const uint64_t P9N2_PERV_PIB_MAILBOX_2_HEADER_COMMAND_2_A = 0x0005002Bull;
+
+
+static const uint32_t P9N2_PERV_MAILBOX_2_HEADER_COMMAND_2_B_FSI = 0x0000282Full;
+
+static const uint32_t P9N2_PERV_MAILBOX_2_HEADER_COMMAND_2_B_FSI_BYTE = 0x000028BCull;
+
+static const uint64_t P9N2_PERV_MAILBOX_2_HEADER_COMMAND_2_B_SCOM = 0x0005002Full;
+
+static const uint64_t P9N2_PERV_PIB_MAILBOX_2_HEADER_COMMAND_2_B = 0x0005002Full;
+
+
+static const uint32_t P9N2_PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_FSI = 0x00002831ull;
+
+static const uint32_t P9N2_PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_FSI_BYTE = 0x000028C4ull;
+
+static const uint64_t P9N2_PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_SCOM = 0x00050031ull;
+
+static const uint64_t P9N2_PERV_PIB_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS = 0x00050031ull;
+
+
+static const uint32_t P9N2_PERV_MAILBOX_SLAVE_A_DOORBELL_INTERRUPT_FSI = 0x00002832ull;
+
+static const uint32_t P9N2_PERV_MAILBOX_SLAVE_A_DOORBELL_INTERRUPT_FSI_BYTE = 0x000028C8ull;
+
+static const uint64_t P9N2_PERV_MAILBOX_SLAVE_A_DOORBELL_INTERRUPT_SCOM = 0x00050032ull;
+
+static const uint64_t P9N2_PERV_PIB_MAILBOX_SLAVE_A_DOORBELL_INTERRUPT = 0x00050032ull;
+
+
+static const uint32_t P9N2_PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_FSI = 0x00002830ull;
+
+static const uint32_t P9N2_PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_FSI_BYTE = 0x000028C0ull;
+
+static const uint64_t P9N2_PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_SCOM = 0x00050030ull;
+
+static const uint64_t P9N2_PERV_PIB_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS = 0x00050030ull;
+
+
+static const uint32_t P9N2_PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_FSI = 0x00002835ull;
+
+static const uint32_t P9N2_PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_FSI_BYTE = 0x000028D4ull;
+
+static const uint64_t P9N2_PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_SCOM = 0x00050035ull;
+
+static const uint64_t P9N2_PERV_PIB_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT = 0x00050035ull;
+
+
+static const uint32_t P9N2_PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MASK_1_FSI = 0x00002836ull;
+
+static const uint64_t P9N2_PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MASK_1_FSI0 = 0x00002837ull;
+
+static const uint32_t P9N2_PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MASK_1_FSI_BYTE = 0x000028D8ull;
+
+static const uint64_t P9N2_PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MASK_1_SCOM = 0x00050036ull;
+
+static const uint64_t P9N2_PERV_PIB_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MASK_1 = 0x00050036ull;
+
+
+static const uint64_t P9N2_PERV_MCAST_COMP_MASK_REG = 0x000F0017ull;
+
+static const uint64_t P9N2_PERV_PIB_MCAST_COMP_MASK_REG = 0x000F0017ull;
+
+
+static const uint64_t P9N2_PERV_MCAST_COMP_REG = 0x000F0015ull;
+
+static const uint64_t P9N2_PERV_PIB_MCAST_COMP_REG = 0x000F0015ull;
+
+
+static const uint64_t P9N2_PERV_MCAST_COMP_VAL_REG = 0x000F0016ull;
+
+static const uint64_t P9N2_PERV_PIB_MCAST_COMP_VAL_REG = 0x000F0016ull;
+
+
+static const uint64_t P9N2_PERV_MCAST_GRP_0_SLAVES_REG = 0x000F0000ull;
+
+static const uint64_t P9N2_PERV_PIB_MCAST_GRP_0_SLAVES_REG = 0x000F0000ull;
+
+
+static const uint64_t P9N2_PERV_MCAST_GRP_1_SLAVES_REG = 0x000F0001ull;
+
+static const uint64_t P9N2_PERV_PIB_MCAST_GRP_1_SLAVES_REG = 0x000F0001ull;
+
+
+static const uint64_t P9N2_PERV_MCAST_GRP_2_SLAVES_REG = 0x000F0002ull;
+
+static const uint64_t P9N2_PERV_PIB_MCAST_GRP_2_SLAVES_REG = 0x000F0002ull;
+
+
+static const uint64_t P9N2_PERV_MCAST_GRP_3_SLAVES_REG = 0x000F0003ull;
+
+static const uint64_t P9N2_PERV_PIB_MCAST_GRP_3_SLAVES_REG = 0x000F0003ull;
+
+
+static const uint64_t P9N2_PERV_MCAST_GRP_4_SLAVES_REG = 0x000F0004ull;
+
+static const uint64_t P9N2_PERV_PIB_MCAST_GRP_4_SLAVES_REG = 0x000F0004ull;
+
+
+static const uint64_t P9N2_PERV_MCAST_GRP_5_SLAVES_REG = 0x000F0005ull;
+
+static const uint64_t P9N2_PERV_PIB_MCAST_GRP_5_SLAVES_REG = 0x000F0005ull;
+
+
+static const uint64_t P9N2_PERV_MCAST_GRP_6_SLAVES_REG = 0x000F0006ull;
+
+static const uint64_t P9N2_PERV_PIB_MCAST_GRP_6_SLAVES_REG = 0x000F0006ull;
+
+
+static const uint64_t P9N2_PERV_MODE_REG = 0x00040008ull;
+
+static const uint64_t P9N2_PERV_TP_MODE_REG = 0x01040008ull;
+
+static const uint64_t P9N2_PERV_N0_MODE_REG = 0x02040008ull;
+
+static const uint64_t P9N2_PERV_N1_MODE_REG = 0x03040008ull;
+
+static const uint64_t P9N2_PERV_N2_MODE_REG = 0x04040008ull;
+
+static const uint64_t P9N2_PERV_N3_MODE_REG = 0x05040008ull;
+
+static const uint64_t P9N2_PERV_XB_MODE_REG = 0x06040008ull;
+
+static const uint64_t P9N2_PERV_MC01_MODE_REG = 0x07040008ull;
+
+static const uint64_t P9N2_PERV_MC23_MODE_REG = 0x08040008ull;
+
+static const uint64_t P9N2_PERV_OB0_MODE_REG = 0x09040008ull;
+
+static const uint64_t P9N2_PERV_OB3_MODE_REG = 0x0C040008ull;
+
+static const uint64_t P9N2_PERV_PCI0_MODE_REG = 0x0D040008ull;
+
+static const uint64_t P9N2_PERV_PCI1_MODE_REG = 0x0E040008ull;
+
+static const uint64_t P9N2_PERV_PCI2_MODE_REG = 0x0F040008ull;
+
+static const uint64_t P9N2_PERV_EP00_MODE_REG = 0x10040008ull;
+
+static const uint64_t P9N2_PERV_EP01_MODE_REG = 0x11040008ull;
+
+static const uint64_t P9N2_PERV_EP02_MODE_REG = 0x12040008ull;
+
+static const uint64_t P9N2_PERV_EP03_MODE_REG = 0x13040008ull;
+
+static const uint64_t P9N2_PERV_EP04_MODE_REG = 0x14040008ull;
+
+static const uint64_t P9N2_PERV_EP05_MODE_REG = 0x15040008ull;
+
+static const uint64_t P9N2_PERV_EC00_MODE_REG = 0x20040008ull;
+
+static const uint64_t P9N2_PERV_EC01_MODE_REG = 0x21040008ull;
+
+static const uint64_t P9N2_PERV_EC02_MODE_REG = 0x22040008ull;
+
+static const uint64_t P9N2_PERV_EC03_MODE_REG = 0x23040008ull;
+
+static const uint64_t P9N2_PERV_EC04_MODE_REG = 0x24040008ull;
+
+static const uint64_t P9N2_PERV_EC05_MODE_REG = 0x25040008ull;
+
+static const uint64_t P9N2_PERV_EC06_MODE_REG = 0x26040008ull;
+
+static const uint64_t P9N2_PERV_EC07_MODE_REG = 0x27040008ull;
+
+static const uint64_t P9N2_PERV_EC08_MODE_REG = 0x28040008ull;
+
+static const uint64_t P9N2_PERV_EC09_MODE_REG = 0x29040008ull;
+
+static const uint64_t P9N2_PERV_EC10_MODE_REG = 0x2A040008ull;
+
+static const uint64_t P9N2_PERV_EC11_MODE_REG = 0x2B040008ull;
+
+static const uint64_t P9N2_PERV_EC12_MODE_REG = 0x2C040008ull;
+
+static const uint64_t P9N2_PERV_EC13_MODE_REG = 0x2D040008ull;
+
+static const uint64_t P9N2_PERV_EC14_MODE_REG = 0x2E040008ull;
+
+static const uint64_t P9N2_PERV_EC15_MODE_REG = 0x2F040008ull;
+
+static const uint64_t P9N2_PERV_EC16_MODE_REG = 0x30040008ull;
+
+static const uint64_t P9N2_PERV_EC17_MODE_REG = 0x31040008ull;
+
+static const uint64_t P9N2_PERV_EC18_MODE_REG = 0x32040008ull;
+
+static const uint64_t P9N2_PERV_EC19_MODE_REG = 0x33040008ull;
+
+static const uint64_t P9N2_PERV_EC20_MODE_REG = 0x34040008ull;
+
+static const uint64_t P9N2_PERV_EC21_MODE_REG = 0x35040008ull;
+
+static const uint64_t P9N2_PERV_EC22_MODE_REG = 0x36040008ull;
+
+static const uint64_t P9N2_PERV_EC23_MODE_REG = 0x37040008ull;
+
+
+static const uint64_t P9N2_PERV_0_FSII2C_MODE_REGISTER_A = 0x00001802ull;
+
+static const uint32_t P9N2_PERV_FSII2C_MODE_REGISTER_A = 0x00001802ull;
+
+
+static const uint64_t P9N2_PERV_MULTICAST_GROUP_1 = 0x000F0001ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_PERV_TP_MULTICAST_GROUP_1 = 0x010F0001ull;
+
+static const uint64_t P9N2_PERV_N0_MULTICAST_GROUP_1 = 0x020F0001ull;
+
+static const uint64_t P9N2_PERV_N1_MULTICAST_GROUP_1 = 0x030F0001ull;
+
+static const uint64_t P9N2_PERV_N2_MULTICAST_GROUP_1 = 0x040F0001ull;
+
+static const uint64_t P9N2_PERV_N3_MULTICAST_GROUP_1 = 0x050F0001ull;
+
+static const uint64_t P9N2_PERV_XB_MULTICAST_GROUP_1 = 0x060F0001ull;
+
+static const uint64_t P9N2_PERV_MC01_MULTICAST_GROUP_1 = 0x070F0001ull;
+
+static const uint64_t P9N2_PERV_MC23_MULTICAST_GROUP_1 = 0x080F0001ull;
+
+static const uint64_t P9N2_PERV_OB0_MULTICAST_GROUP_1 = 0x090F0001ull;
+
+static const uint64_t P9N2_PERV_OB3_MULTICAST_GROUP_1 = 0x0C0F0001ull;
+
+static const uint64_t P9N2_PERV_PCI0_MULTICAST_GROUP_1 = 0x0D0F0001ull;
+
+static const uint64_t P9N2_PERV_PCI1_MULTICAST_GROUP_1 = 0x0E0F0001ull;
+
+static const uint64_t P9N2_PERV_PCI2_MULTICAST_GROUP_1 = 0x0F0F0001ull;
+
+static const uint64_t P9N2_PERV_EP00_MULTICAST_GROUP_1 = 0x100F0001ull;
+
+static const uint64_t P9N2_PERV_EP01_MULTICAST_GROUP_1 = 0x110F0001ull;
+
+static const uint64_t P9N2_PERV_EP02_MULTICAST_GROUP_1 = 0x120F0001ull;
+
+static const uint64_t P9N2_PERV_EP03_MULTICAST_GROUP_1 = 0x130F0001ull;
+
+static const uint64_t P9N2_PERV_EP04_MULTICAST_GROUP_1 = 0x140F0001ull;
+
+static const uint64_t P9N2_PERV_EP05_MULTICAST_GROUP_1 = 0x150F0001ull;
+
+static const uint64_t P9N2_PERV_EC00_MULTICAST_GROUP_1 = 0x200F0001ull;
+
+static const uint64_t P9N2_PERV_EC01_MULTICAST_GROUP_1 = 0x210F0001ull;
+
+static const uint64_t P9N2_PERV_EC02_MULTICAST_GROUP_1 = 0x220F0001ull;
+
+static const uint64_t P9N2_PERV_EC03_MULTICAST_GROUP_1 = 0x230F0001ull;
+
+static const uint64_t P9N2_PERV_EC04_MULTICAST_GROUP_1 = 0x240F0001ull;
+
+static const uint64_t P9N2_PERV_EC05_MULTICAST_GROUP_1 = 0x250F0001ull;
+
+static const uint64_t P9N2_PERV_EC06_MULTICAST_GROUP_1 = 0x260F0001ull;
+
+static const uint64_t P9N2_PERV_EC07_MULTICAST_GROUP_1 = 0x270F0001ull;
+
+static const uint64_t P9N2_PERV_EC08_MULTICAST_GROUP_1 = 0x280F0001ull;
+
+static const uint64_t P9N2_PERV_EC09_MULTICAST_GROUP_1 = 0x290F0001ull;
+
+static const uint64_t P9N2_PERV_EC10_MULTICAST_GROUP_1 = 0x2A0F0001ull;
+
+static const uint64_t P9N2_PERV_EC11_MULTICAST_GROUP_1 = 0x2B0F0001ull;
+
+static const uint64_t P9N2_PERV_EC12_MULTICAST_GROUP_1 = 0x2C0F0001ull;
+
+static const uint64_t P9N2_PERV_EC13_MULTICAST_GROUP_1 = 0x2D0F0001ull;
+
+static const uint64_t P9N2_PERV_EC14_MULTICAST_GROUP_1 = 0x2E0F0001ull;
+
+static const uint64_t P9N2_PERV_EC15_MULTICAST_GROUP_1 = 0x2F0F0001ull;
+
+static const uint64_t P9N2_PERV_EC16_MULTICAST_GROUP_1 = 0x300F0001ull;
+
+static const uint64_t P9N2_PERV_EC17_MULTICAST_GROUP_1 = 0x310F0001ull;
+
+static const uint64_t P9N2_PERV_EC18_MULTICAST_GROUP_1 = 0x320F0001ull;
+
+static const uint64_t P9N2_PERV_EC19_MULTICAST_GROUP_1 = 0x330F0001ull;
+
+static const uint64_t P9N2_PERV_EC20_MULTICAST_GROUP_1 = 0x340F0001ull;
+
+static const uint64_t P9N2_PERV_EC21_MULTICAST_GROUP_1 = 0x350F0001ull;
+
+static const uint64_t P9N2_PERV_EC22_MULTICAST_GROUP_1 = 0x360F0001ull;
+
+static const uint64_t P9N2_PERV_EC23_MULTICAST_GROUP_1 = 0x370F0001ull;
+
+
+static const uint64_t P9N2_PERV_MULTICAST_GROUP_2 = 0x000F0002ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_PERV_TP_MULTICAST_GROUP_2 = 0x010F0002ull;
+
+static const uint64_t P9N2_PERV_N0_MULTICAST_GROUP_2 = 0x020F0002ull;
+
+static const uint64_t P9N2_PERV_N1_MULTICAST_GROUP_2 = 0x030F0002ull;
+
+static const uint64_t P9N2_PERV_N2_MULTICAST_GROUP_2 = 0x040F0002ull;
+
+static const uint64_t P9N2_PERV_N3_MULTICAST_GROUP_2 = 0x050F0002ull;
+
+static const uint64_t P9N2_PERV_XB_MULTICAST_GROUP_2 = 0x060F0002ull;
+
+static const uint64_t P9N2_PERV_MC01_MULTICAST_GROUP_2 = 0x070F0002ull;
+
+static const uint64_t P9N2_PERV_MC23_MULTICAST_GROUP_2 = 0x080F0002ull;
+
+static const uint64_t P9N2_PERV_OB0_MULTICAST_GROUP_2 = 0x090F0002ull;
+
+static const uint64_t P9N2_PERV_OB3_MULTICAST_GROUP_2 = 0x0C0F0002ull;
+
+static const uint64_t P9N2_PERV_PCI0_MULTICAST_GROUP_2 = 0x0D0F0002ull;
+
+static const uint64_t P9N2_PERV_PCI1_MULTICAST_GROUP_2 = 0x0E0F0002ull;
+
+static const uint64_t P9N2_PERV_PCI2_MULTICAST_GROUP_2 = 0x0F0F0002ull;
+
+static const uint64_t P9N2_PERV_EP00_MULTICAST_GROUP_2 = 0x100F0002ull;
+
+static const uint64_t P9N2_PERV_EP01_MULTICAST_GROUP_2 = 0x110F0002ull;
+
+static const uint64_t P9N2_PERV_EP02_MULTICAST_GROUP_2 = 0x120F0002ull;
+
+static const uint64_t P9N2_PERV_EP03_MULTICAST_GROUP_2 = 0x130F0002ull;
+
+static const uint64_t P9N2_PERV_EP04_MULTICAST_GROUP_2 = 0x140F0002ull;
+
+static const uint64_t P9N2_PERV_EP05_MULTICAST_GROUP_2 = 0x150F0002ull;
+
+static const uint64_t P9N2_PERV_EC00_MULTICAST_GROUP_2 = 0x200F0002ull;
+
+static const uint64_t P9N2_PERV_EC01_MULTICAST_GROUP_2 = 0x210F0002ull;
+
+static const uint64_t P9N2_PERV_EC02_MULTICAST_GROUP_2 = 0x220F0002ull;
+
+static const uint64_t P9N2_PERV_EC03_MULTICAST_GROUP_2 = 0x230F0002ull;
+
+static const uint64_t P9N2_PERV_EC04_MULTICAST_GROUP_2 = 0x240F0002ull;
+
+static const uint64_t P9N2_PERV_EC05_MULTICAST_GROUP_2 = 0x250F0002ull;
+
+static const uint64_t P9N2_PERV_EC06_MULTICAST_GROUP_2 = 0x260F0002ull;
+
+static const uint64_t P9N2_PERV_EC07_MULTICAST_GROUP_2 = 0x270F0002ull;
+
+static const uint64_t P9N2_PERV_EC08_MULTICAST_GROUP_2 = 0x280F0002ull;
+
+static const uint64_t P9N2_PERV_EC09_MULTICAST_GROUP_2 = 0x290F0002ull;
+
+static const uint64_t P9N2_PERV_EC10_MULTICAST_GROUP_2 = 0x2A0F0002ull;
+
+static const uint64_t P9N2_PERV_EC11_MULTICAST_GROUP_2 = 0x2B0F0002ull;
+
+static const uint64_t P9N2_PERV_EC12_MULTICAST_GROUP_2 = 0x2C0F0002ull;
+
+static const uint64_t P9N2_PERV_EC13_MULTICAST_GROUP_2 = 0x2D0F0002ull;
+
+static const uint64_t P9N2_PERV_EC14_MULTICAST_GROUP_2 = 0x2E0F0002ull;
+
+static const uint64_t P9N2_PERV_EC15_MULTICAST_GROUP_2 = 0x2F0F0002ull;
+
+static const uint64_t P9N2_PERV_EC16_MULTICAST_GROUP_2 = 0x300F0002ull;
+
+static const uint64_t P9N2_PERV_EC17_MULTICAST_GROUP_2 = 0x310F0002ull;
+
+static const uint64_t P9N2_PERV_EC18_MULTICAST_GROUP_2 = 0x320F0002ull;
+
+static const uint64_t P9N2_PERV_EC19_MULTICAST_GROUP_2 = 0x330F0002ull;
+
+static const uint64_t P9N2_PERV_EC20_MULTICAST_GROUP_2 = 0x340F0002ull;
+
+static const uint64_t P9N2_PERV_EC21_MULTICAST_GROUP_2 = 0x350F0002ull;
+
+static const uint64_t P9N2_PERV_EC22_MULTICAST_GROUP_2 = 0x360F0002ull;
+
+static const uint64_t P9N2_PERV_EC23_MULTICAST_GROUP_2 = 0x370F0002ull;
+
+
+static const uint64_t P9N2_PERV_MULTICAST_GROUP_3 = 0x000F0003ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_PERV_TP_MULTICAST_GROUP_3 = 0x010F0003ull;
+
+static const uint64_t P9N2_PERV_N0_MULTICAST_GROUP_3 = 0x020F0003ull;
+
+static const uint64_t P9N2_PERV_N1_MULTICAST_GROUP_3 = 0x030F0003ull;
+
+static const uint64_t P9N2_PERV_N2_MULTICAST_GROUP_3 = 0x040F0003ull;
+
+static const uint64_t P9N2_PERV_N3_MULTICAST_GROUP_3 = 0x050F0003ull;
+
+static const uint64_t P9N2_PERV_XB_MULTICAST_GROUP_3 = 0x060F0003ull;
+
+static const uint64_t P9N2_PERV_MC01_MULTICAST_GROUP_3 = 0x070F0003ull;
+
+static const uint64_t P9N2_PERV_MC23_MULTICAST_GROUP_3 = 0x080F0003ull;
+
+static const uint64_t P9N2_PERV_OB0_MULTICAST_GROUP_3 = 0x090F0003ull;
+
+static const uint64_t P9N2_PERV_OB3_MULTICAST_GROUP_3 = 0x0C0F0003ull;
+
+static const uint64_t P9N2_PERV_PCI0_MULTICAST_GROUP_3 = 0x0D0F0003ull;
+
+static const uint64_t P9N2_PERV_PCI1_MULTICAST_GROUP_3 = 0x0E0F0003ull;
+
+static const uint64_t P9N2_PERV_PCI2_MULTICAST_GROUP_3 = 0x0F0F0003ull;
+
+static const uint64_t P9N2_PERV_EP00_MULTICAST_GROUP_3 = 0x100F0003ull;
+
+static const uint64_t P9N2_PERV_EP01_MULTICAST_GROUP_3 = 0x110F0003ull;
+
+static const uint64_t P9N2_PERV_EP02_MULTICAST_GROUP_3 = 0x120F0003ull;
+
+static const uint64_t P9N2_PERV_EP03_MULTICAST_GROUP_3 = 0x130F0003ull;
+
+static const uint64_t P9N2_PERV_EP04_MULTICAST_GROUP_3 = 0x140F0003ull;
+
+static const uint64_t P9N2_PERV_EP05_MULTICAST_GROUP_3 = 0x150F0003ull;
+
+static const uint64_t P9N2_PERV_EC00_MULTICAST_GROUP_3 = 0x200F0003ull;
+
+static const uint64_t P9N2_PERV_EC01_MULTICAST_GROUP_3 = 0x210F0003ull;
+
+static const uint64_t P9N2_PERV_EC02_MULTICAST_GROUP_3 = 0x220F0003ull;
+
+static const uint64_t P9N2_PERV_EC03_MULTICAST_GROUP_3 = 0x230F0003ull;
+
+static const uint64_t P9N2_PERV_EC04_MULTICAST_GROUP_3 = 0x240F0003ull;
+
+static const uint64_t P9N2_PERV_EC05_MULTICAST_GROUP_3 = 0x250F0003ull;
+
+static const uint64_t P9N2_PERV_EC06_MULTICAST_GROUP_3 = 0x260F0003ull;
+
+static const uint64_t P9N2_PERV_EC07_MULTICAST_GROUP_3 = 0x270F0003ull;
+
+static const uint64_t P9N2_PERV_EC08_MULTICAST_GROUP_3 = 0x280F0003ull;
+
+static const uint64_t P9N2_PERV_EC09_MULTICAST_GROUP_3 = 0x290F0003ull;
+
+static const uint64_t P9N2_PERV_EC10_MULTICAST_GROUP_3 = 0x2A0F0003ull;
+
+static const uint64_t P9N2_PERV_EC11_MULTICAST_GROUP_3 = 0x2B0F0003ull;
+
+static const uint64_t P9N2_PERV_EC12_MULTICAST_GROUP_3 = 0x2C0F0003ull;
+
+static const uint64_t P9N2_PERV_EC13_MULTICAST_GROUP_3 = 0x2D0F0003ull;
+
+static const uint64_t P9N2_PERV_EC14_MULTICAST_GROUP_3 = 0x2E0F0003ull;
+
+static const uint64_t P9N2_PERV_EC15_MULTICAST_GROUP_3 = 0x2F0F0003ull;
+
+static const uint64_t P9N2_PERV_EC16_MULTICAST_GROUP_3 = 0x300F0003ull;
+
+static const uint64_t P9N2_PERV_EC17_MULTICAST_GROUP_3 = 0x310F0003ull;
+
+static const uint64_t P9N2_PERV_EC18_MULTICAST_GROUP_3 = 0x320F0003ull;
+
+static const uint64_t P9N2_PERV_EC19_MULTICAST_GROUP_3 = 0x330F0003ull;
+
+static const uint64_t P9N2_PERV_EC20_MULTICAST_GROUP_3 = 0x340F0003ull;
+
+static const uint64_t P9N2_PERV_EC21_MULTICAST_GROUP_3 = 0x350F0003ull;
+
+static const uint64_t P9N2_PERV_EC22_MULTICAST_GROUP_3 = 0x360F0003ull;
+
+static const uint64_t P9N2_PERV_EC23_MULTICAST_GROUP_3 = 0x370F0003ull;
+
+
+static const uint64_t P9N2_PERV_MULTICAST_GROUP_4 = 0x000F0004ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_PERV_TP_MULTICAST_GROUP_4 = 0x010F0004ull;
+
+static const uint64_t P9N2_PERV_N0_MULTICAST_GROUP_4 = 0x020F0004ull;
+
+static const uint64_t P9N2_PERV_N1_MULTICAST_GROUP_4 = 0x030F0004ull;
+
+static const uint64_t P9N2_PERV_N2_MULTICAST_GROUP_4 = 0x040F0004ull;
+
+static const uint64_t P9N2_PERV_N3_MULTICAST_GROUP_4 = 0x050F0004ull;
+
+static const uint64_t P9N2_PERV_XB_MULTICAST_GROUP_4 = 0x060F0004ull;
+
+static const uint64_t P9N2_PERV_MC01_MULTICAST_GROUP_4 = 0x070F0004ull;
+
+static const uint64_t P9N2_PERV_MC23_MULTICAST_GROUP_4 = 0x080F0004ull;
+
+static const uint64_t P9N2_PERV_OB0_MULTICAST_GROUP_4 = 0x090F0004ull;
+
+static const uint64_t P9N2_PERV_OB3_MULTICAST_GROUP_4 = 0x0C0F0004ull;
+
+static const uint64_t P9N2_PERV_PCI0_MULTICAST_GROUP_4 = 0x0D0F0004ull;
+
+static const uint64_t P9N2_PERV_PCI1_MULTICAST_GROUP_4 = 0x0E0F0004ull;
+
+static const uint64_t P9N2_PERV_PCI2_MULTICAST_GROUP_4 = 0x0F0F0004ull;
+
+static const uint64_t P9N2_PERV_EP00_MULTICAST_GROUP_4 = 0x100F0004ull;
+
+static const uint64_t P9N2_PERV_EP01_MULTICAST_GROUP_4 = 0x110F0004ull;
+
+static const uint64_t P9N2_PERV_EP02_MULTICAST_GROUP_4 = 0x120F0004ull;
+
+static const uint64_t P9N2_PERV_EP03_MULTICAST_GROUP_4 = 0x130F0004ull;
+
+static const uint64_t P9N2_PERV_EP04_MULTICAST_GROUP_4 = 0x140F0004ull;
+
+static const uint64_t P9N2_PERV_EP05_MULTICAST_GROUP_4 = 0x150F0004ull;
+
+static const uint64_t P9N2_PERV_EC00_MULTICAST_GROUP_4 = 0x200F0004ull;
+
+static const uint64_t P9N2_PERV_EC01_MULTICAST_GROUP_4 = 0x210F0004ull;
+
+static const uint64_t P9N2_PERV_EC02_MULTICAST_GROUP_4 = 0x220F0004ull;
+
+static const uint64_t P9N2_PERV_EC03_MULTICAST_GROUP_4 = 0x230F0004ull;
+
+static const uint64_t P9N2_PERV_EC04_MULTICAST_GROUP_4 = 0x240F0004ull;
+
+static const uint64_t P9N2_PERV_EC05_MULTICAST_GROUP_4 = 0x250F0004ull;
+
+static const uint64_t P9N2_PERV_EC06_MULTICAST_GROUP_4 = 0x260F0004ull;
+
+static const uint64_t P9N2_PERV_EC07_MULTICAST_GROUP_4 = 0x270F0004ull;
+
+static const uint64_t P9N2_PERV_EC08_MULTICAST_GROUP_4 = 0x280F0004ull;
+
+static const uint64_t P9N2_PERV_EC09_MULTICAST_GROUP_4 = 0x290F0004ull;
+
+static const uint64_t P9N2_PERV_EC10_MULTICAST_GROUP_4 = 0x2A0F0004ull;
+
+static const uint64_t P9N2_PERV_EC11_MULTICAST_GROUP_4 = 0x2B0F0004ull;
+
+static const uint64_t P9N2_PERV_EC12_MULTICAST_GROUP_4 = 0x2C0F0004ull;
+
+static const uint64_t P9N2_PERV_EC13_MULTICAST_GROUP_4 = 0x2D0F0004ull;
+
+static const uint64_t P9N2_PERV_EC14_MULTICAST_GROUP_4 = 0x2E0F0004ull;
+
+static const uint64_t P9N2_PERV_EC15_MULTICAST_GROUP_4 = 0x2F0F0004ull;
+
+static const uint64_t P9N2_PERV_EC16_MULTICAST_GROUP_4 = 0x300F0004ull;
+
+static const uint64_t P9N2_PERV_EC17_MULTICAST_GROUP_4 = 0x310F0004ull;
+
+static const uint64_t P9N2_PERV_EC18_MULTICAST_GROUP_4 = 0x320F0004ull;
+
+static const uint64_t P9N2_PERV_EC19_MULTICAST_GROUP_4 = 0x330F0004ull;
+
+static const uint64_t P9N2_PERV_EC20_MULTICAST_GROUP_4 = 0x340F0004ull;
+
+static const uint64_t P9N2_PERV_EC21_MULTICAST_GROUP_4 = 0x350F0004ull;
+
+static const uint64_t P9N2_PERV_EC22_MULTICAST_GROUP_4 = 0x360F0004ull;
+
+static const uint64_t P9N2_PERV_EC23_MULTICAST_GROUP_4 = 0x370F0004ull;
+
+
+static const uint64_t P9N2_PERV_NET_CTRL0 = 0x000F0040ull;
+
+static const uint64_t P9N2_PERV_TP_NET_CTRL0 = 0x010F0040ull;
+
+static const uint64_t P9N2_PERV_NET_CTRL0_WAND = 0x000F0041ull;
+
+static const uint64_t P9N2_PERV_TP_NET_CTRL0_WAND = 0x010F0041ull;
+
+static const uint64_t P9N2_PERV_NET_CTRL0_WOR = 0x000F0042ull;
+
+static const uint64_t P9N2_PERV_TP_NET_CTRL0_WOR = 0x010F0042ull;
+
+static const uint64_t P9N2_PERV_N0_NET_CTRL0 = 0x020F0040ull;
+
+static const uint64_t P9N2_PERV_N0_NET_CTRL0_WAND = 0x020F0041ull;
+
+static const uint64_t P9N2_PERV_N0_NET_CTRL0_WOR = 0x020F0042ull;
+
+static const uint64_t P9N2_PERV_N1_NET_CTRL0 = 0x030F0040ull;
+
+static const uint64_t P9N2_PERV_N1_NET_CTRL0_WAND = 0x030F0041ull;
+
+static const uint64_t P9N2_PERV_N1_NET_CTRL0_WOR = 0x030F0042ull;
+
+static const uint64_t P9N2_PERV_N2_NET_CTRL0 = 0x040F0040ull;
+
+static const uint64_t P9N2_PERV_N2_NET_CTRL0_WAND = 0x040F0041ull;
+
+static const uint64_t P9N2_PERV_N2_NET_CTRL0_WOR = 0x040F0042ull;
+
+static const uint64_t P9N2_PERV_N3_NET_CTRL0 = 0x050F0040ull;
+
+static const uint64_t P9N2_PERV_N3_NET_CTRL0_WAND = 0x050F0041ull;
+
+static const uint64_t P9N2_PERV_N3_NET_CTRL0_WOR = 0x050F0042ull;
+
+static const uint64_t P9N2_PERV_XB_NET_CTRL0 = 0x060F0040ull;
+
+static const uint64_t P9N2_PERV_XB_NET_CTRL0_WAND = 0x060F0041ull;
+
+static const uint64_t P9N2_PERV_XB_NET_CTRL0_WOR = 0x060F0042ull;
+
+static const uint64_t P9N2_PERV_MC01_NET_CTRL0 = 0x070F0040ull;
+
+static const uint64_t P9N2_PERV_MC01_NET_CTRL0_WAND = 0x070F0041ull;
+
+static const uint64_t P9N2_PERV_MC01_NET_CTRL0_WOR = 0x070F0042ull;
+
+static const uint64_t P9N2_PERV_MC23_NET_CTRL0 = 0x080F0040ull;
+
+static const uint64_t P9N2_PERV_MC23_NET_CTRL0_WAND = 0x080F0041ull;
+
+static const uint64_t P9N2_PERV_MC23_NET_CTRL0_WOR = 0x080F0042ull;
+
+static const uint64_t P9N2_PERV_OB0_NET_CTRL0 = 0x090F0040ull;
+
+static const uint64_t P9N2_PERV_OB0_NET_CTRL0_WAND = 0x090F0041ull;
+
+static const uint64_t P9N2_PERV_OB0_NET_CTRL0_WOR = 0x090F0042ull;
+
+static const uint64_t P9N2_PERV_OB3_NET_CTRL0 = 0x0C0F0040ull;
+
+static const uint64_t P9N2_PERV_OB3_NET_CTRL0_WAND = 0x0C0F0041ull;
+
+static const uint64_t P9N2_PERV_OB3_NET_CTRL0_WOR = 0x0C0F0042ull;
+
+static const uint64_t P9N2_PERV_PCI0_NET_CTRL0 = 0x0D0F0040ull;
+
+static const uint64_t P9N2_PERV_PCI0_NET_CTRL0_WAND = 0x0D0F0041ull;
+
+static const uint64_t P9N2_PERV_PCI0_NET_CTRL0_WOR = 0x0D0F0042ull;
+
+static const uint64_t P9N2_PERV_PCI1_NET_CTRL0 = 0x0E0F0040ull;
+
+static const uint64_t P9N2_PERV_PCI1_NET_CTRL0_WAND = 0x0E0F0041ull;
+
+static const uint64_t P9N2_PERV_PCI1_NET_CTRL0_WOR = 0x0E0F0042ull;
+
+static const uint64_t P9N2_PERV_PCI2_NET_CTRL0 = 0x0F0F0040ull;
+
+static const uint64_t P9N2_PERV_PCI2_NET_CTRL0_WAND = 0x0F0F0041ull;
+
+static const uint64_t P9N2_PERV_PCI2_NET_CTRL0_WOR = 0x0F0F0042ull;
+
+static const uint64_t P9N2_PERV_EP00_NET_CTRL0 = 0x100F0040ull;
+
+static const uint64_t P9N2_PERV_EP00_NET_CTRL0_WAND = 0x100F0041ull;
+
+static const uint64_t P9N2_PERV_EP00_NET_CTRL0_WOR = 0x100F0042ull;
+
+static const uint64_t P9N2_PERV_EP01_NET_CTRL0 = 0x110F0040ull;
+
+static const uint64_t P9N2_PERV_EP01_NET_CTRL0_WAND = 0x110F0041ull;
+
+static const uint64_t P9N2_PERV_EP01_NET_CTRL0_WOR = 0x110F0042ull;
+
+static const uint64_t P9N2_PERV_EP02_NET_CTRL0 = 0x120F0040ull;
+
+static const uint64_t P9N2_PERV_EP02_NET_CTRL0_WAND = 0x120F0041ull;
+
+static const uint64_t P9N2_PERV_EP02_NET_CTRL0_WOR = 0x120F0042ull;
+
+static const uint64_t P9N2_PERV_EP03_NET_CTRL0 = 0x130F0040ull;
+
+static const uint64_t P9N2_PERV_EP03_NET_CTRL0_WAND = 0x130F0041ull;
+
+static const uint64_t P9N2_PERV_EP03_NET_CTRL0_WOR = 0x130F0042ull;
+
+static const uint64_t P9N2_PERV_EP04_NET_CTRL0 = 0x140F0040ull;
+
+static const uint64_t P9N2_PERV_EP04_NET_CTRL0_WAND = 0x140F0041ull;
+
+static const uint64_t P9N2_PERV_EP04_NET_CTRL0_WOR = 0x140F0042ull;
+
+static const uint64_t P9N2_PERV_EP05_NET_CTRL0 = 0x150F0040ull;
+
+static const uint64_t P9N2_PERV_EP05_NET_CTRL0_WAND = 0x150F0041ull;
+
+static const uint64_t P9N2_PERV_EP05_NET_CTRL0_WOR = 0x150F0042ull;
+
+static const uint64_t P9N2_PERV_EC00_NET_CTRL0 = 0x200F0040ull;
+
+static const uint64_t P9N2_PERV_EC00_NET_CTRL0_WAND = 0x200F0041ull;
+
+static const uint64_t P9N2_PERV_EC00_NET_CTRL0_WOR = 0x200F0042ull;
+
+static const uint64_t P9N2_PERV_EC01_NET_CTRL0 = 0x210F0040ull;
+
+static const uint64_t P9N2_PERV_EC01_NET_CTRL0_WAND = 0x210F0041ull;
+
+static const uint64_t P9N2_PERV_EC01_NET_CTRL0_WOR = 0x210F0042ull;
+
+static const uint64_t P9N2_PERV_EC02_NET_CTRL0 = 0x220F0040ull;
+
+static const uint64_t P9N2_PERV_EC02_NET_CTRL0_WAND = 0x220F0041ull;
+
+static const uint64_t P9N2_PERV_EC02_NET_CTRL0_WOR = 0x220F0042ull;
+
+static const uint64_t P9N2_PERV_EC03_NET_CTRL0 = 0x230F0040ull;
+
+static const uint64_t P9N2_PERV_EC03_NET_CTRL0_WAND = 0x230F0041ull;
+
+static const uint64_t P9N2_PERV_EC03_NET_CTRL0_WOR = 0x230F0042ull;
+
+static const uint64_t P9N2_PERV_EC04_NET_CTRL0 = 0x240F0040ull;
+
+static const uint64_t P9N2_PERV_EC04_NET_CTRL0_WAND = 0x240F0041ull;
+
+static const uint64_t P9N2_PERV_EC04_NET_CTRL0_WOR = 0x240F0042ull;
+
+static const uint64_t P9N2_PERV_EC05_NET_CTRL0 = 0x250F0040ull;
+
+static const uint64_t P9N2_PERV_EC05_NET_CTRL0_WAND = 0x250F0041ull;
+
+static const uint64_t P9N2_PERV_EC05_NET_CTRL0_WOR = 0x250F0042ull;
+
+static const uint64_t P9N2_PERV_EC06_NET_CTRL0 = 0x260F0040ull;
+
+static const uint64_t P9N2_PERV_EC06_NET_CTRL0_WAND = 0x260F0041ull;
+
+static const uint64_t P9N2_PERV_EC06_NET_CTRL0_WOR = 0x260F0042ull;
+
+static const uint64_t P9N2_PERV_EC07_NET_CTRL0 = 0x270F0040ull;
+
+static const uint64_t P9N2_PERV_EC07_NET_CTRL0_WAND = 0x270F0041ull;
+
+static const uint64_t P9N2_PERV_EC07_NET_CTRL0_WOR = 0x270F0042ull;
+
+static const uint64_t P9N2_PERV_EC08_NET_CTRL0 = 0x280F0040ull;
+
+static const uint64_t P9N2_PERV_EC08_NET_CTRL0_WAND = 0x280F0041ull;
+
+static const uint64_t P9N2_PERV_EC08_NET_CTRL0_WOR = 0x280F0042ull;
+
+static const uint64_t P9N2_PERV_EC09_NET_CTRL0 = 0x290F0040ull;
+
+static const uint64_t P9N2_PERV_EC09_NET_CTRL0_WAND = 0x290F0041ull;
+
+static const uint64_t P9N2_PERV_EC09_NET_CTRL0_WOR = 0x290F0042ull;
+
+static const uint64_t P9N2_PERV_EC10_NET_CTRL0 = 0x2A0F0040ull;
+
+static const uint64_t P9N2_PERV_EC10_NET_CTRL0_WAND = 0x2A0F0041ull;
+
+static const uint64_t P9N2_PERV_EC10_NET_CTRL0_WOR = 0x2A0F0042ull;
+
+static const uint64_t P9N2_PERV_EC11_NET_CTRL0 = 0x2B0F0040ull;
+
+static const uint64_t P9N2_PERV_EC11_NET_CTRL0_WAND = 0x2B0F0041ull;
+
+static const uint64_t P9N2_PERV_EC11_NET_CTRL0_WOR = 0x2B0F0042ull;
+
+static const uint64_t P9N2_PERV_EC12_NET_CTRL0 = 0x2C0F0040ull;
+
+static const uint64_t P9N2_PERV_EC12_NET_CTRL0_WAND = 0x2C0F0041ull;
+
+static const uint64_t P9N2_PERV_EC12_NET_CTRL0_WOR = 0x2C0F0042ull;
+
+static const uint64_t P9N2_PERV_EC13_NET_CTRL0 = 0x2D0F0040ull;
+
+static const uint64_t P9N2_PERV_EC13_NET_CTRL0_WAND = 0x2D0F0041ull;
+
+static const uint64_t P9N2_PERV_EC13_NET_CTRL0_WOR = 0x2D0F0042ull;
+
+static const uint64_t P9N2_PERV_EC14_NET_CTRL0 = 0x2E0F0040ull;
+
+static const uint64_t P9N2_PERV_EC14_NET_CTRL0_WAND = 0x2E0F0041ull;
+
+static const uint64_t P9N2_PERV_EC14_NET_CTRL0_WOR = 0x2E0F0042ull;
+
+static const uint64_t P9N2_PERV_EC15_NET_CTRL0 = 0x2F0F0040ull;
+
+static const uint64_t P9N2_PERV_EC15_NET_CTRL0_WAND = 0x2F0F0041ull;
+
+static const uint64_t P9N2_PERV_EC15_NET_CTRL0_WOR = 0x2F0F0042ull;
+
+static const uint64_t P9N2_PERV_EC16_NET_CTRL0 = 0x300F0040ull;
+
+static const uint64_t P9N2_PERV_EC16_NET_CTRL0_WAND = 0x300F0041ull;
+
+static const uint64_t P9N2_PERV_EC16_NET_CTRL0_WOR = 0x300F0042ull;
+
+static const uint64_t P9N2_PERV_EC17_NET_CTRL0 = 0x310F0040ull;
+
+static const uint64_t P9N2_PERV_EC17_NET_CTRL0_WAND = 0x310F0041ull;
+
+static const uint64_t P9N2_PERV_EC17_NET_CTRL0_WOR = 0x310F0042ull;
+
+static const uint64_t P9N2_PERV_EC18_NET_CTRL0 = 0x320F0040ull;
+
+static const uint64_t P9N2_PERV_EC18_NET_CTRL0_WAND = 0x320F0041ull;
+
+static const uint64_t P9N2_PERV_EC18_NET_CTRL0_WOR = 0x320F0042ull;
+
+static const uint64_t P9N2_PERV_EC19_NET_CTRL0 = 0x330F0040ull;
+
+static const uint64_t P9N2_PERV_EC19_NET_CTRL0_WAND = 0x330F0041ull;
+
+static const uint64_t P9N2_PERV_EC19_NET_CTRL0_WOR = 0x330F0042ull;
+
+static const uint64_t P9N2_PERV_EC20_NET_CTRL0 = 0x340F0040ull;
+
+static const uint64_t P9N2_PERV_EC20_NET_CTRL0_WAND = 0x340F0041ull;
+
+static const uint64_t P9N2_PERV_EC20_NET_CTRL0_WOR = 0x340F0042ull;
+
+static const uint64_t P9N2_PERV_EC21_NET_CTRL0 = 0x350F0040ull;
+
+static const uint64_t P9N2_PERV_EC21_NET_CTRL0_WAND = 0x350F0041ull;
+
+static const uint64_t P9N2_PERV_EC21_NET_CTRL0_WOR = 0x350F0042ull;
+
+static const uint64_t P9N2_PERV_EC22_NET_CTRL0 = 0x360F0040ull;
+
+static const uint64_t P9N2_PERV_EC22_NET_CTRL0_WAND = 0x360F0041ull;
+
+static const uint64_t P9N2_PERV_EC22_NET_CTRL0_WOR = 0x360F0042ull;
+
+static const uint64_t P9N2_PERV_EC23_NET_CTRL0 = 0x370F0040ull;
+
+static const uint64_t P9N2_PERV_EC23_NET_CTRL0_WAND = 0x370F0041ull;
+
+static const uint64_t P9N2_PERV_EC23_NET_CTRL0_WOR = 0x370F0042ull;
+
+
+static const uint64_t P9N2_PERV_NET_CTRL1 = 0x000F0044ull;
+
+static const uint64_t P9N2_PERV_TP_NET_CTRL1 = 0x010F0044ull;
+
+static const uint64_t P9N2_PERV_NET_CTRL1_WAND = 0x000F0045ull;
+
+static const uint64_t P9N2_PERV_TP_NET_CTRL1_WAND = 0x010F0045ull;
+
+static const uint64_t P9N2_PERV_NET_CTRL1_WOR = 0x000F0046ull;
+
+static const uint64_t P9N2_PERV_TP_NET_CTRL1_WOR = 0x010F0046ull;
+
+static const uint64_t P9N2_PERV_N0_NET_CTRL1 = 0x020F0044ull;
+
+static const uint64_t P9N2_PERV_N0_NET_CTRL1_WAND = 0x020F0045ull;
+
+static const uint64_t P9N2_PERV_N0_NET_CTRL1_WOR = 0x020F0046ull;
+
+static const uint64_t P9N2_PERV_N1_NET_CTRL1 = 0x030F0044ull;
+
+static const uint64_t P9N2_PERV_N1_NET_CTRL1_WAND = 0x030F0045ull;
+
+static const uint64_t P9N2_PERV_N1_NET_CTRL1_WOR = 0x030F0046ull;
+
+static const uint64_t P9N2_PERV_N2_NET_CTRL1 = 0x040F0044ull;
+
+static const uint64_t P9N2_PERV_N2_NET_CTRL1_WAND = 0x040F0045ull;
+
+static const uint64_t P9N2_PERV_N2_NET_CTRL1_WOR = 0x040F0046ull;
+
+static const uint64_t P9N2_PERV_N3_NET_CTRL1 = 0x050F0044ull;
+
+static const uint64_t P9N2_PERV_N3_NET_CTRL1_WAND = 0x050F0045ull;
+
+static const uint64_t P9N2_PERV_N3_NET_CTRL1_WOR = 0x050F0046ull;
+
+static const uint64_t P9N2_PERV_XB_NET_CTRL1 = 0x060F0044ull;
+
+static const uint64_t P9N2_PERV_XB_NET_CTRL1_WAND = 0x060F0045ull;
+
+static const uint64_t P9N2_PERV_XB_NET_CTRL1_WOR = 0x060F0046ull;
+
+static const uint64_t P9N2_PERV_MC01_NET_CTRL1 = 0x070F0044ull;
+
+static const uint64_t P9N2_PERV_MC01_NET_CTRL1_WAND = 0x070F0045ull;
+
+static const uint64_t P9N2_PERV_MC01_NET_CTRL1_WOR = 0x070F0046ull;
+
+static const uint64_t P9N2_PERV_MC23_NET_CTRL1 = 0x080F0044ull;
+
+static const uint64_t P9N2_PERV_MC23_NET_CTRL1_WAND = 0x080F0045ull;
+
+static const uint64_t P9N2_PERV_MC23_NET_CTRL1_WOR = 0x080F0046ull;
+
+static const uint64_t P9N2_PERV_OB0_NET_CTRL1 = 0x090F0044ull;
+
+static const uint64_t P9N2_PERV_OB0_NET_CTRL1_WAND = 0x090F0045ull;
+
+static const uint64_t P9N2_PERV_OB0_NET_CTRL1_WOR = 0x090F0046ull;
+
+static const uint64_t P9N2_PERV_OB3_NET_CTRL1 = 0x0C0F0044ull;
+
+static const uint64_t P9N2_PERV_OB3_NET_CTRL1_WAND = 0x0C0F0045ull;
+
+static const uint64_t P9N2_PERV_OB3_NET_CTRL1_WOR = 0x0C0F0046ull;
+
+static const uint64_t P9N2_PERV_PCI0_NET_CTRL1 = 0x0D0F0044ull;
+
+static const uint64_t P9N2_PERV_PCI0_NET_CTRL1_WAND = 0x0D0F0045ull;
+
+static const uint64_t P9N2_PERV_PCI0_NET_CTRL1_WOR = 0x0D0F0046ull;
+
+static const uint64_t P9N2_PERV_PCI1_NET_CTRL1 = 0x0E0F0044ull;
+
+static const uint64_t P9N2_PERV_PCI1_NET_CTRL1_WAND = 0x0E0F0045ull;
+
+static const uint64_t P9N2_PERV_PCI1_NET_CTRL1_WOR = 0x0E0F0046ull;
+
+static const uint64_t P9N2_PERV_PCI2_NET_CTRL1 = 0x0F0F0044ull;
+
+static const uint64_t P9N2_PERV_PCI2_NET_CTRL1_WAND = 0x0F0F0045ull;
+
+static const uint64_t P9N2_PERV_PCI2_NET_CTRL1_WOR = 0x0F0F0046ull;
+
+static const uint64_t P9N2_PERV_EP00_NET_CTRL1 = 0x100F0044ull;
+
+static const uint64_t P9N2_PERV_EP00_NET_CTRL1_WAND = 0x100F0045ull;
+
+static const uint64_t P9N2_PERV_EP00_NET_CTRL1_WOR = 0x100F0046ull;
+
+static const uint64_t P9N2_PERV_EP01_NET_CTRL1 = 0x110F0044ull;
+
+static const uint64_t P9N2_PERV_EP01_NET_CTRL1_WAND = 0x110F0045ull;
+
+static const uint64_t P9N2_PERV_EP01_NET_CTRL1_WOR = 0x110F0046ull;
+
+static const uint64_t P9N2_PERV_EP02_NET_CTRL1 = 0x120F0044ull;
+
+static const uint64_t P9N2_PERV_EP02_NET_CTRL1_WAND = 0x120F0045ull;
+
+static const uint64_t P9N2_PERV_EP02_NET_CTRL1_WOR = 0x120F0046ull;
+
+static const uint64_t P9N2_PERV_EP03_NET_CTRL1 = 0x130F0044ull;
+
+static const uint64_t P9N2_PERV_EP03_NET_CTRL1_WAND = 0x130F0045ull;
+
+static const uint64_t P9N2_PERV_EP03_NET_CTRL1_WOR = 0x130F0046ull;
+
+static const uint64_t P9N2_PERV_EP04_NET_CTRL1 = 0x140F0044ull;
+
+static const uint64_t P9N2_PERV_EP04_NET_CTRL1_WAND = 0x140F0045ull;
+
+static const uint64_t P9N2_PERV_EP04_NET_CTRL1_WOR = 0x140F0046ull;
+
+static const uint64_t P9N2_PERV_EP05_NET_CTRL1 = 0x150F0044ull;
+
+static const uint64_t P9N2_PERV_EP05_NET_CTRL1_WAND = 0x150F0045ull;
+
+static const uint64_t P9N2_PERV_EP05_NET_CTRL1_WOR = 0x150F0046ull;
+
+static const uint64_t P9N2_PERV_EC00_NET_CTRL1 = 0x200F0044ull;
+
+static const uint64_t P9N2_PERV_EC00_NET_CTRL1_WAND = 0x200F0045ull;
+
+static const uint64_t P9N2_PERV_EC00_NET_CTRL1_WOR = 0x200F0046ull;
+
+static const uint64_t P9N2_PERV_EC01_NET_CTRL1 = 0x210F0044ull;
+
+static const uint64_t P9N2_PERV_EC01_NET_CTRL1_WAND = 0x210F0045ull;
+
+static const uint64_t P9N2_PERV_EC01_NET_CTRL1_WOR = 0x210F0046ull;
+
+static const uint64_t P9N2_PERV_EC02_NET_CTRL1 = 0x220F0044ull;
+
+static const uint64_t P9N2_PERV_EC02_NET_CTRL1_WAND = 0x220F0045ull;
+
+static const uint64_t P9N2_PERV_EC02_NET_CTRL1_WOR = 0x220F0046ull;
+
+static const uint64_t P9N2_PERV_EC03_NET_CTRL1 = 0x230F0044ull;
+
+static const uint64_t P9N2_PERV_EC03_NET_CTRL1_WAND = 0x230F0045ull;
+
+static const uint64_t P9N2_PERV_EC03_NET_CTRL1_WOR = 0x230F0046ull;
+
+static const uint64_t P9N2_PERV_EC04_NET_CTRL1 = 0x240F0044ull;
+
+static const uint64_t P9N2_PERV_EC04_NET_CTRL1_WAND = 0x240F0045ull;
+
+static const uint64_t P9N2_PERV_EC04_NET_CTRL1_WOR = 0x240F0046ull;
+
+static const uint64_t P9N2_PERV_EC05_NET_CTRL1 = 0x250F0044ull;
+
+static const uint64_t P9N2_PERV_EC05_NET_CTRL1_WAND = 0x250F0045ull;
+
+static const uint64_t P9N2_PERV_EC05_NET_CTRL1_WOR = 0x250F0046ull;
+
+static const uint64_t P9N2_PERV_EC06_NET_CTRL1 = 0x260F0044ull;
+
+static const uint64_t P9N2_PERV_EC06_NET_CTRL1_WAND = 0x260F0045ull;
+
+static const uint64_t P9N2_PERV_EC06_NET_CTRL1_WOR = 0x260F0046ull;
+
+static const uint64_t P9N2_PERV_EC07_NET_CTRL1 = 0x270F0044ull;
+
+static const uint64_t P9N2_PERV_EC07_NET_CTRL1_WAND = 0x270F0045ull;
+
+static const uint64_t P9N2_PERV_EC07_NET_CTRL1_WOR = 0x270F0046ull;
+
+static const uint64_t P9N2_PERV_EC08_NET_CTRL1 = 0x280F0044ull;
+
+static const uint64_t P9N2_PERV_EC08_NET_CTRL1_WAND = 0x280F0045ull;
+
+static const uint64_t P9N2_PERV_EC08_NET_CTRL1_WOR = 0x280F0046ull;
+
+static const uint64_t P9N2_PERV_EC09_NET_CTRL1 = 0x290F0044ull;
+
+static const uint64_t P9N2_PERV_EC09_NET_CTRL1_WAND = 0x290F0045ull;
+
+static const uint64_t P9N2_PERV_EC09_NET_CTRL1_WOR = 0x290F0046ull;
+
+static const uint64_t P9N2_PERV_EC10_NET_CTRL1 = 0x2A0F0044ull;
+
+static const uint64_t P9N2_PERV_EC10_NET_CTRL1_WAND = 0x2A0F0045ull;
+
+static const uint64_t P9N2_PERV_EC10_NET_CTRL1_WOR = 0x2A0F0046ull;
+
+static const uint64_t P9N2_PERV_EC11_NET_CTRL1 = 0x2B0F0044ull;
+
+static const uint64_t P9N2_PERV_EC11_NET_CTRL1_WAND = 0x2B0F0045ull;
+
+static const uint64_t P9N2_PERV_EC11_NET_CTRL1_WOR = 0x2B0F0046ull;
+
+static const uint64_t P9N2_PERV_EC12_NET_CTRL1 = 0x2C0F0044ull;
+
+static const uint64_t P9N2_PERV_EC12_NET_CTRL1_WAND = 0x2C0F0045ull;
+
+static const uint64_t P9N2_PERV_EC12_NET_CTRL1_WOR = 0x2C0F0046ull;
+
+static const uint64_t P9N2_PERV_EC13_NET_CTRL1 = 0x2D0F0044ull;
+
+static const uint64_t P9N2_PERV_EC13_NET_CTRL1_WAND = 0x2D0F0045ull;
+
+static const uint64_t P9N2_PERV_EC13_NET_CTRL1_WOR = 0x2D0F0046ull;
+
+static const uint64_t P9N2_PERV_EC14_NET_CTRL1 = 0x2E0F0044ull;
+
+static const uint64_t P9N2_PERV_EC14_NET_CTRL1_WAND = 0x2E0F0045ull;
+
+static const uint64_t P9N2_PERV_EC14_NET_CTRL1_WOR = 0x2E0F0046ull;
+
+static const uint64_t P9N2_PERV_EC15_NET_CTRL1 = 0x2F0F0044ull;
+
+static const uint64_t P9N2_PERV_EC15_NET_CTRL1_WAND = 0x2F0F0045ull;
+
+static const uint64_t P9N2_PERV_EC15_NET_CTRL1_WOR = 0x2F0F0046ull;
+
+static const uint64_t P9N2_PERV_EC16_NET_CTRL1 = 0x300F0044ull;
+
+static const uint64_t P9N2_PERV_EC16_NET_CTRL1_WAND = 0x300F0045ull;
+
+static const uint64_t P9N2_PERV_EC16_NET_CTRL1_WOR = 0x300F0046ull;
+
+static const uint64_t P9N2_PERV_EC17_NET_CTRL1 = 0x310F0044ull;
+
+static const uint64_t P9N2_PERV_EC17_NET_CTRL1_WAND = 0x310F0045ull;
+
+static const uint64_t P9N2_PERV_EC17_NET_CTRL1_WOR = 0x310F0046ull;
+
+static const uint64_t P9N2_PERV_EC18_NET_CTRL1 = 0x320F0044ull;
+
+static const uint64_t P9N2_PERV_EC18_NET_CTRL1_WAND = 0x320F0045ull;
+
+static const uint64_t P9N2_PERV_EC18_NET_CTRL1_WOR = 0x320F0046ull;
+
+static const uint64_t P9N2_PERV_EC19_NET_CTRL1 = 0x330F0044ull;
+
+static const uint64_t P9N2_PERV_EC19_NET_CTRL1_WAND = 0x330F0045ull;
+
+static const uint64_t P9N2_PERV_EC19_NET_CTRL1_WOR = 0x330F0046ull;
+
+static const uint64_t P9N2_PERV_EC20_NET_CTRL1 = 0x340F0044ull;
+
+static const uint64_t P9N2_PERV_EC20_NET_CTRL1_WAND = 0x340F0045ull;
+
+static const uint64_t P9N2_PERV_EC20_NET_CTRL1_WOR = 0x340F0046ull;
+
+static const uint64_t P9N2_PERV_EC21_NET_CTRL1 = 0x350F0044ull;
+
+static const uint64_t P9N2_PERV_EC21_NET_CTRL1_WAND = 0x350F0045ull;
+
+static const uint64_t P9N2_PERV_EC21_NET_CTRL1_WOR = 0x350F0046ull;
+
+static const uint64_t P9N2_PERV_EC22_NET_CTRL1 = 0x360F0044ull;
+
+static const uint64_t P9N2_PERV_EC22_NET_CTRL1_WAND = 0x360F0045ull;
+
+static const uint64_t P9N2_PERV_EC22_NET_CTRL1_WOR = 0x360F0046ull;
+
+static const uint64_t P9N2_PERV_EC23_NET_CTRL1 = 0x370F0044ull;
+
+static const uint64_t P9N2_PERV_EC23_NET_CTRL1_WAND = 0x370F0045ull;
+
+static const uint64_t P9N2_PERV_EC23_NET_CTRL1_WOR = 0x370F0046ull;
+
+
+static const uint64_t P9N2_PERV_OCC_SCOM_OCCERRRPT = 0x0001080Aull;
+
+static const uint64_t P9N2_PERV_TP_OCC_SCOM_OCCERRRPT = 0x0101080Aull;
+
+
+static const uint64_t P9N2_PERV_OCC_SCOM_OCCLFIR = 0x00010800ull;
+
+static const uint64_t P9N2_PERV_TP_OCC_SCOM_OCCLFIR = 0x01010800ull;
+
+static const uint64_t P9N2_PERV_OCC_SCOM_OCCLFIR_AND = 0x00010801ull;
+
+static const uint64_t P9N2_PERV_TP_OCC_SCOM_OCCLFIR_AND = 0x01010801ull;
+
+static const uint64_t P9N2_PERV_OCC_SCOM_OCCLFIR_OR = 0x00010802ull;
+
+static const uint64_t P9N2_PERV_TP_OCC_SCOM_OCCLFIR_OR = 0x01010802ull;
+
+
+static const uint64_t P9N2_PERV_OCC_SCOM_OCCLFIRACT0 = 0x00010806ull;
+
+static const uint64_t P9N2_PERV_TP_OCC_SCOM_OCCLFIRACT0 = 0x01010806ull;
+
+
+static const uint64_t P9N2_PERV_OCC_SCOM_OCCLFIRACT1 = 0x00010807ull;
+
+static const uint64_t P9N2_PERV_TP_OCC_SCOM_OCCLFIRACT1 = 0x01010807ull;
+
+
+static const uint64_t P9N2_PERV_OCC_SCOM_OCCLFIRMASK = 0x00010803ull;
+
+static const uint64_t P9N2_PERV_TP_OCC_SCOM_OCCLFIRMASK = 0x01010803ull;
+
+static const uint64_t P9N2_PERV_OCC_SCOM_OCCLFIRMASK_AND = 0x00010804ull;
+
+static const uint64_t P9N2_PERV_TP_OCC_SCOM_OCCLFIRMASK_AND = 0x01010804ull;
+
+static const uint64_t P9N2_PERV_OCC_SCOM_OCCLFIRMASK_OR = 0x00010805ull;
+
+static const uint64_t P9N2_PERV_TP_OCC_SCOM_OCCLFIRMASK_OR = 0x01010805ull;
+
+
+static const uint64_t P9N2_PERV_OPCG_ALIGN = 0x00030001ull;
+
+static const uint64_t P9N2_PERV_TP_OPCG_ALIGN = 0x01030001ull;
+
+static const uint64_t P9N2_PERV_N0_OPCG_ALIGN = 0x02030001ull;
+
+static const uint64_t P9N2_PERV_N1_OPCG_ALIGN = 0x03030001ull;
+
+static const uint64_t P9N2_PERV_N2_OPCG_ALIGN = 0x04030001ull;
+
+static const uint64_t P9N2_PERV_N3_OPCG_ALIGN = 0x05030001ull;
+
+static const uint64_t P9N2_PERV_XB_OPCG_ALIGN = 0x06030001ull;
+
+static const uint64_t P9N2_PERV_MC01_OPCG_ALIGN = 0x07030001ull;
+
+static const uint64_t P9N2_PERV_MC23_OPCG_ALIGN = 0x08030001ull;
+
+static const uint64_t P9N2_PERV_OB0_OPCG_ALIGN = 0x09030001ull;
+
+static const uint64_t P9N2_PERV_OB3_OPCG_ALIGN = 0x0C030001ull;
+
+static const uint64_t P9N2_PERV_PCI0_OPCG_ALIGN = 0x0D030001ull;
+
+static const uint64_t P9N2_PERV_PCI1_OPCG_ALIGN = 0x0E030001ull;
+
+static const uint64_t P9N2_PERV_PCI2_OPCG_ALIGN = 0x0F030001ull;
+
+static const uint64_t P9N2_PERV_EP00_OPCG_ALIGN = 0x10030001ull;
+
+static const uint64_t P9N2_PERV_EP01_OPCG_ALIGN = 0x11030001ull;
+
+static const uint64_t P9N2_PERV_EP02_OPCG_ALIGN = 0x12030001ull;
+
+static const uint64_t P9N2_PERV_EP03_OPCG_ALIGN = 0x13030001ull;
+
+static const uint64_t P9N2_PERV_EP04_OPCG_ALIGN = 0x14030001ull;
+
+static const uint64_t P9N2_PERV_EP05_OPCG_ALIGN = 0x15030001ull;
+
+static const uint64_t P9N2_PERV_EC00_OPCG_ALIGN = 0x20030001ull;
+
+static const uint64_t P9N2_PERV_EC01_OPCG_ALIGN = 0x21030001ull;
+
+static const uint64_t P9N2_PERV_EC02_OPCG_ALIGN = 0x22030001ull;
+
+static const uint64_t P9N2_PERV_EC03_OPCG_ALIGN = 0x23030001ull;
+
+static const uint64_t P9N2_PERV_EC04_OPCG_ALIGN = 0x24030001ull;
+
+static const uint64_t P9N2_PERV_EC05_OPCG_ALIGN = 0x25030001ull;
+
+static const uint64_t P9N2_PERV_EC06_OPCG_ALIGN = 0x26030001ull;
+
+static const uint64_t P9N2_PERV_EC07_OPCG_ALIGN = 0x27030001ull;
+
+static const uint64_t P9N2_PERV_EC08_OPCG_ALIGN = 0x28030001ull;
+
+static const uint64_t P9N2_PERV_EC09_OPCG_ALIGN = 0x29030001ull;
+
+static const uint64_t P9N2_PERV_EC10_OPCG_ALIGN = 0x2A030001ull;
+
+static const uint64_t P9N2_PERV_EC11_OPCG_ALIGN = 0x2B030001ull;
+
+static const uint64_t P9N2_PERV_EC12_OPCG_ALIGN = 0x2C030001ull;
+
+static const uint64_t P9N2_PERV_EC13_OPCG_ALIGN = 0x2D030001ull;
+
+static const uint64_t P9N2_PERV_EC14_OPCG_ALIGN = 0x2E030001ull;
+
+static const uint64_t P9N2_PERV_EC15_OPCG_ALIGN = 0x2F030001ull;
+
+static const uint64_t P9N2_PERV_EC16_OPCG_ALIGN = 0x30030001ull;
+
+static const uint64_t P9N2_PERV_EC17_OPCG_ALIGN = 0x31030001ull;
+
+static const uint64_t P9N2_PERV_EC18_OPCG_ALIGN = 0x32030001ull;
+
+static const uint64_t P9N2_PERV_EC19_OPCG_ALIGN = 0x33030001ull;
+
+static const uint64_t P9N2_PERV_EC20_OPCG_ALIGN = 0x34030001ull;
+
+static const uint64_t P9N2_PERV_EC21_OPCG_ALIGN = 0x35030001ull;
+
+static const uint64_t P9N2_PERV_EC22_OPCG_ALIGN = 0x36030001ull;
+
+static const uint64_t P9N2_PERV_EC23_OPCG_ALIGN = 0x37030001ull;
+
+
+static const uint64_t P9N2_PERV_OPCG_CAPT1 = 0x00030010ull;
+
+static const uint64_t P9N2_PERV_TP_OPCG_CAPT1 = 0x01030010ull;
+
+static const uint64_t P9N2_PERV_N0_OPCG_CAPT1 = 0x02030010ull;
+
+static const uint64_t P9N2_PERV_N1_OPCG_CAPT1 = 0x03030010ull;
+
+static const uint64_t P9N2_PERV_N2_OPCG_CAPT1 = 0x04030010ull;
+
+static const uint64_t P9N2_PERV_N3_OPCG_CAPT1 = 0x05030010ull;
+
+static const uint64_t P9N2_PERV_XB_OPCG_CAPT1 = 0x06030010ull;
+
+static const uint64_t P9N2_PERV_MC01_OPCG_CAPT1 = 0x07030010ull;
+
+static const uint64_t P9N2_PERV_MC23_OPCG_CAPT1 = 0x08030010ull;
+
+static const uint64_t P9N2_PERV_OB0_OPCG_CAPT1 = 0x09030010ull;
+
+static const uint64_t P9N2_PERV_OB3_OPCG_CAPT1 = 0x0C030010ull;
+
+static const uint64_t P9N2_PERV_PCI0_OPCG_CAPT1 = 0x0D030010ull;
+
+static const uint64_t P9N2_PERV_PCI1_OPCG_CAPT1 = 0x0E030010ull;
+
+static const uint64_t P9N2_PERV_PCI2_OPCG_CAPT1 = 0x0F030010ull;
+
+static const uint64_t P9N2_PERV_EP00_OPCG_CAPT1 = 0x10030010ull;
+
+static const uint64_t P9N2_PERV_EP01_OPCG_CAPT1 = 0x11030010ull;
+
+static const uint64_t P9N2_PERV_EP02_OPCG_CAPT1 = 0x12030010ull;
+
+static const uint64_t P9N2_PERV_EP03_OPCG_CAPT1 = 0x13030010ull;
+
+static const uint64_t P9N2_PERV_EP04_OPCG_CAPT1 = 0x14030010ull;
+
+static const uint64_t P9N2_PERV_EP05_OPCG_CAPT1 = 0x15030010ull;
+
+static const uint64_t P9N2_PERV_EC00_OPCG_CAPT1 = 0x20030010ull;
+
+static const uint64_t P9N2_PERV_EC01_OPCG_CAPT1 = 0x21030010ull;
+
+static const uint64_t P9N2_PERV_EC02_OPCG_CAPT1 = 0x22030010ull;
+
+static const uint64_t P9N2_PERV_EC03_OPCG_CAPT1 = 0x23030010ull;
+
+static const uint64_t P9N2_PERV_EC04_OPCG_CAPT1 = 0x24030010ull;
+
+static const uint64_t P9N2_PERV_EC05_OPCG_CAPT1 = 0x25030010ull;
+
+static const uint64_t P9N2_PERV_EC06_OPCG_CAPT1 = 0x26030010ull;
+
+static const uint64_t P9N2_PERV_EC07_OPCG_CAPT1 = 0x27030010ull;
+
+static const uint64_t P9N2_PERV_EC08_OPCG_CAPT1 = 0x28030010ull;
+
+static const uint64_t P9N2_PERV_EC09_OPCG_CAPT1 = 0x29030010ull;
+
+static const uint64_t P9N2_PERV_EC10_OPCG_CAPT1 = 0x2A030010ull;
+
+static const uint64_t P9N2_PERV_EC11_OPCG_CAPT1 = 0x2B030010ull;
+
+static const uint64_t P9N2_PERV_EC12_OPCG_CAPT1 = 0x2C030010ull;
+
+static const uint64_t P9N2_PERV_EC13_OPCG_CAPT1 = 0x2D030010ull;
+
+static const uint64_t P9N2_PERV_EC14_OPCG_CAPT1 = 0x2E030010ull;
+
+static const uint64_t P9N2_PERV_EC15_OPCG_CAPT1 = 0x2F030010ull;
+
+static const uint64_t P9N2_PERV_EC16_OPCG_CAPT1 = 0x30030010ull;
+
+static const uint64_t P9N2_PERV_EC17_OPCG_CAPT1 = 0x31030010ull;
+
+static const uint64_t P9N2_PERV_EC18_OPCG_CAPT1 = 0x32030010ull;
+
+static const uint64_t P9N2_PERV_EC19_OPCG_CAPT1 = 0x33030010ull;
+
+static const uint64_t P9N2_PERV_EC20_OPCG_CAPT1 = 0x34030010ull;
+
+static const uint64_t P9N2_PERV_EC21_OPCG_CAPT1 = 0x35030010ull;
+
+static const uint64_t P9N2_PERV_EC22_OPCG_CAPT1 = 0x36030010ull;
+
+static const uint64_t P9N2_PERV_EC23_OPCG_CAPT1 = 0x37030010ull;
+
+
+static const uint64_t P9N2_PERV_OPCG_CAPT2 = 0x00030011ull;
+
+static const uint64_t P9N2_PERV_TP_OPCG_CAPT2 = 0x01030011ull;
+
+static const uint64_t P9N2_PERV_N0_OPCG_CAPT2 = 0x02030011ull;
+
+static const uint64_t P9N2_PERV_N1_OPCG_CAPT2 = 0x03030011ull;
+
+static const uint64_t P9N2_PERV_N2_OPCG_CAPT2 = 0x04030011ull;
+
+static const uint64_t P9N2_PERV_N3_OPCG_CAPT2 = 0x05030011ull;
+
+static const uint64_t P9N2_PERV_XB_OPCG_CAPT2 = 0x06030011ull;
+
+static const uint64_t P9N2_PERV_MC01_OPCG_CAPT2 = 0x07030011ull;
+
+static const uint64_t P9N2_PERV_MC23_OPCG_CAPT2 = 0x08030011ull;
+
+static const uint64_t P9N2_PERV_OB0_OPCG_CAPT2 = 0x09030011ull;
+
+static const uint64_t P9N2_PERV_OB3_OPCG_CAPT2 = 0x0C030011ull;
+
+static const uint64_t P9N2_PERV_PCI0_OPCG_CAPT2 = 0x0D030011ull;
+
+static const uint64_t P9N2_PERV_PCI1_OPCG_CAPT2 = 0x0E030011ull;
+
+static const uint64_t P9N2_PERV_PCI2_OPCG_CAPT2 = 0x0F030011ull;
+
+static const uint64_t P9N2_PERV_EP00_OPCG_CAPT2 = 0x10030011ull;
+
+static const uint64_t P9N2_PERV_EP01_OPCG_CAPT2 = 0x11030011ull;
+
+static const uint64_t P9N2_PERV_EP02_OPCG_CAPT2 = 0x12030011ull;
+
+static const uint64_t P9N2_PERV_EP03_OPCG_CAPT2 = 0x13030011ull;
+
+static const uint64_t P9N2_PERV_EP04_OPCG_CAPT2 = 0x14030011ull;
+
+static const uint64_t P9N2_PERV_EP05_OPCG_CAPT2 = 0x15030011ull;
+
+static const uint64_t P9N2_PERV_EC00_OPCG_CAPT2 = 0x20030011ull;
+
+static const uint64_t P9N2_PERV_EC01_OPCG_CAPT2 = 0x21030011ull;
+
+static const uint64_t P9N2_PERV_EC02_OPCG_CAPT2 = 0x22030011ull;
+
+static const uint64_t P9N2_PERV_EC03_OPCG_CAPT2 = 0x23030011ull;
+
+static const uint64_t P9N2_PERV_EC04_OPCG_CAPT2 = 0x24030011ull;
+
+static const uint64_t P9N2_PERV_EC05_OPCG_CAPT2 = 0x25030011ull;
+
+static const uint64_t P9N2_PERV_EC06_OPCG_CAPT2 = 0x26030011ull;
+
+static const uint64_t P9N2_PERV_EC07_OPCG_CAPT2 = 0x27030011ull;
+
+static const uint64_t P9N2_PERV_EC08_OPCG_CAPT2 = 0x28030011ull;
+
+static const uint64_t P9N2_PERV_EC09_OPCG_CAPT2 = 0x29030011ull;
+
+static const uint64_t P9N2_PERV_EC10_OPCG_CAPT2 = 0x2A030011ull;
+
+static const uint64_t P9N2_PERV_EC11_OPCG_CAPT2 = 0x2B030011ull;
+
+static const uint64_t P9N2_PERV_EC12_OPCG_CAPT2 = 0x2C030011ull;
+
+static const uint64_t P9N2_PERV_EC13_OPCG_CAPT2 = 0x2D030011ull;
+
+static const uint64_t P9N2_PERV_EC14_OPCG_CAPT2 = 0x2E030011ull;
+
+static const uint64_t P9N2_PERV_EC15_OPCG_CAPT2 = 0x2F030011ull;
+
+static const uint64_t P9N2_PERV_EC16_OPCG_CAPT2 = 0x30030011ull;
+
+static const uint64_t P9N2_PERV_EC17_OPCG_CAPT2 = 0x31030011ull;
+
+static const uint64_t P9N2_PERV_EC18_OPCG_CAPT2 = 0x32030011ull;
+
+static const uint64_t P9N2_PERV_EC19_OPCG_CAPT2 = 0x33030011ull;
+
+static const uint64_t P9N2_PERV_EC20_OPCG_CAPT2 = 0x34030011ull;
+
+static const uint64_t P9N2_PERV_EC21_OPCG_CAPT2 = 0x35030011ull;
+
+static const uint64_t P9N2_PERV_EC22_OPCG_CAPT2 = 0x36030011ull;
+
+static const uint64_t P9N2_PERV_EC23_OPCG_CAPT2 = 0x37030011ull;
+
+
+static const uint64_t P9N2_PERV_OPCG_CAPT3 = 0x00030012ull;
+
+static const uint64_t P9N2_PERV_TP_OPCG_CAPT3 = 0x01030012ull;
+
+static const uint64_t P9N2_PERV_N0_OPCG_CAPT3 = 0x02030012ull;
+
+static const uint64_t P9N2_PERV_N1_OPCG_CAPT3 = 0x03030012ull;
+
+static const uint64_t P9N2_PERV_N2_OPCG_CAPT3 = 0x04030012ull;
+
+static const uint64_t P9N2_PERV_N3_OPCG_CAPT3 = 0x05030012ull;
+
+static const uint64_t P9N2_PERV_XB_OPCG_CAPT3 = 0x06030012ull;
+
+static const uint64_t P9N2_PERV_MC01_OPCG_CAPT3 = 0x07030012ull;
+
+static const uint64_t P9N2_PERV_MC23_OPCG_CAPT3 = 0x08030012ull;
+
+static const uint64_t P9N2_PERV_OB0_OPCG_CAPT3 = 0x09030012ull;
+
+static const uint64_t P9N2_PERV_OB3_OPCG_CAPT3 = 0x0C030012ull;
+
+static const uint64_t P9N2_PERV_PCI0_OPCG_CAPT3 = 0x0D030012ull;
+
+static const uint64_t P9N2_PERV_PCI1_OPCG_CAPT3 = 0x0E030012ull;
+
+static const uint64_t P9N2_PERV_PCI2_OPCG_CAPT3 = 0x0F030012ull;
+
+static const uint64_t P9N2_PERV_EP00_OPCG_CAPT3 = 0x10030012ull;
+
+static const uint64_t P9N2_PERV_EP01_OPCG_CAPT3 = 0x11030012ull;
+
+static const uint64_t P9N2_PERV_EP02_OPCG_CAPT3 = 0x12030012ull;
+
+static const uint64_t P9N2_PERV_EP03_OPCG_CAPT3 = 0x13030012ull;
+
+static const uint64_t P9N2_PERV_EP04_OPCG_CAPT3 = 0x14030012ull;
+
+static const uint64_t P9N2_PERV_EP05_OPCG_CAPT3 = 0x15030012ull;
+
+static const uint64_t P9N2_PERV_EC00_OPCG_CAPT3 = 0x20030012ull;
+
+static const uint64_t P9N2_PERV_EC01_OPCG_CAPT3 = 0x21030012ull;
+
+static const uint64_t P9N2_PERV_EC02_OPCG_CAPT3 = 0x22030012ull;
+
+static const uint64_t P9N2_PERV_EC03_OPCG_CAPT3 = 0x23030012ull;
+
+static const uint64_t P9N2_PERV_EC04_OPCG_CAPT3 = 0x24030012ull;
+
+static const uint64_t P9N2_PERV_EC05_OPCG_CAPT3 = 0x25030012ull;
+
+static const uint64_t P9N2_PERV_EC06_OPCG_CAPT3 = 0x26030012ull;
+
+static const uint64_t P9N2_PERV_EC07_OPCG_CAPT3 = 0x27030012ull;
+
+static const uint64_t P9N2_PERV_EC08_OPCG_CAPT3 = 0x28030012ull;
+
+static const uint64_t P9N2_PERV_EC09_OPCG_CAPT3 = 0x29030012ull;
+
+static const uint64_t P9N2_PERV_EC10_OPCG_CAPT3 = 0x2A030012ull;
+
+static const uint64_t P9N2_PERV_EC11_OPCG_CAPT3 = 0x2B030012ull;
+
+static const uint64_t P9N2_PERV_EC12_OPCG_CAPT3 = 0x2C030012ull;
+
+static const uint64_t P9N2_PERV_EC13_OPCG_CAPT3 = 0x2D030012ull;
+
+static const uint64_t P9N2_PERV_EC14_OPCG_CAPT3 = 0x2E030012ull;
+
+static const uint64_t P9N2_PERV_EC15_OPCG_CAPT3 = 0x2F030012ull;
+
+static const uint64_t P9N2_PERV_EC16_OPCG_CAPT3 = 0x30030012ull;
+
+static const uint64_t P9N2_PERV_EC17_OPCG_CAPT3 = 0x31030012ull;
+
+static const uint64_t P9N2_PERV_EC18_OPCG_CAPT3 = 0x32030012ull;
+
+static const uint64_t P9N2_PERV_EC19_OPCG_CAPT3 = 0x33030012ull;
+
+static const uint64_t P9N2_PERV_EC20_OPCG_CAPT3 = 0x34030012ull;
+
+static const uint64_t P9N2_PERV_EC21_OPCG_CAPT3 = 0x35030012ull;
+
+static const uint64_t P9N2_PERV_EC22_OPCG_CAPT3 = 0x36030012ull;
+
+static const uint64_t P9N2_PERV_EC23_OPCG_CAPT3 = 0x37030012ull;
+
+
+static const uint64_t P9N2_PERV_OPCG_REG0 = 0x00030002ull;
+
+static const uint64_t P9N2_PERV_TP_OPCG_REG0 = 0x01030002ull;
+
+static const uint64_t P9N2_PERV_N0_OPCG_REG0 = 0x02030002ull;
+
+static const uint64_t P9N2_PERV_N1_OPCG_REG0 = 0x03030002ull;
+
+static const uint64_t P9N2_PERV_N2_OPCG_REG0 = 0x04030002ull;
+
+static const uint64_t P9N2_PERV_N3_OPCG_REG0 = 0x05030002ull;
+
+static const uint64_t P9N2_PERV_XB_OPCG_REG0 = 0x06030002ull;
+
+static const uint64_t P9N2_PERV_MC01_OPCG_REG0 = 0x07030002ull;
+
+static const uint64_t P9N2_PERV_MC23_OPCG_REG0 = 0x08030002ull;
+
+static const uint64_t P9N2_PERV_OB0_OPCG_REG0 = 0x09030002ull;
+
+static const uint64_t P9N2_PERV_OB3_OPCG_REG0 = 0x0C030002ull;
+
+static const uint64_t P9N2_PERV_PCI0_OPCG_REG0 = 0x0D030002ull;
+
+static const uint64_t P9N2_PERV_PCI1_OPCG_REG0 = 0x0E030002ull;
+
+static const uint64_t P9N2_PERV_PCI2_OPCG_REG0 = 0x0F030002ull;
+
+static const uint64_t P9N2_PERV_EP00_OPCG_REG0 = 0x10030002ull;
+
+static const uint64_t P9N2_PERV_EP01_OPCG_REG0 = 0x11030002ull;
+
+static const uint64_t P9N2_PERV_EP02_OPCG_REG0 = 0x12030002ull;
+
+static const uint64_t P9N2_PERV_EP03_OPCG_REG0 = 0x13030002ull;
+
+static const uint64_t P9N2_PERV_EP04_OPCG_REG0 = 0x14030002ull;
+
+static const uint64_t P9N2_PERV_EP05_OPCG_REG0 = 0x15030002ull;
+
+static const uint64_t P9N2_PERV_EC00_OPCG_REG0 = 0x20030002ull;
+
+static const uint64_t P9N2_PERV_EC01_OPCG_REG0 = 0x21030002ull;
+
+static const uint64_t P9N2_PERV_EC02_OPCG_REG0 = 0x22030002ull;
+
+static const uint64_t P9N2_PERV_EC03_OPCG_REG0 = 0x23030002ull;
+
+static const uint64_t P9N2_PERV_EC04_OPCG_REG0 = 0x24030002ull;
+
+static const uint64_t P9N2_PERV_EC05_OPCG_REG0 = 0x25030002ull;
+
+static const uint64_t P9N2_PERV_EC06_OPCG_REG0 = 0x26030002ull;
+
+static const uint64_t P9N2_PERV_EC07_OPCG_REG0 = 0x27030002ull;
+
+static const uint64_t P9N2_PERV_EC08_OPCG_REG0 = 0x28030002ull;
+
+static const uint64_t P9N2_PERV_EC09_OPCG_REG0 = 0x29030002ull;
+
+static const uint64_t P9N2_PERV_EC10_OPCG_REG0 = 0x2A030002ull;
+
+static const uint64_t P9N2_PERV_EC11_OPCG_REG0 = 0x2B030002ull;
+
+static const uint64_t P9N2_PERV_EC12_OPCG_REG0 = 0x2C030002ull;
+
+static const uint64_t P9N2_PERV_EC13_OPCG_REG0 = 0x2D030002ull;
+
+static const uint64_t P9N2_PERV_EC14_OPCG_REG0 = 0x2E030002ull;
+
+static const uint64_t P9N2_PERV_EC15_OPCG_REG0 = 0x2F030002ull;
+
+static const uint64_t P9N2_PERV_EC16_OPCG_REG0 = 0x30030002ull;
+
+static const uint64_t P9N2_PERV_EC17_OPCG_REG0 = 0x31030002ull;
+
+static const uint64_t P9N2_PERV_EC18_OPCG_REG0 = 0x32030002ull;
+
+static const uint64_t P9N2_PERV_EC19_OPCG_REG0 = 0x33030002ull;
+
+static const uint64_t P9N2_PERV_EC20_OPCG_REG0 = 0x34030002ull;
+
+static const uint64_t P9N2_PERV_EC21_OPCG_REG0 = 0x35030002ull;
+
+static const uint64_t P9N2_PERV_EC22_OPCG_REG0 = 0x36030002ull;
+
+static const uint64_t P9N2_PERV_EC23_OPCG_REG0 = 0x37030002ull;
+
+
+static const uint64_t P9N2_PERV_OPCG_REG1 = 0x00030003ull;
+
+static const uint64_t P9N2_PERV_TP_OPCG_REG1 = 0x01030003ull;
+
+static const uint64_t P9N2_PERV_N0_OPCG_REG1 = 0x02030003ull;
+
+static const uint64_t P9N2_PERV_N1_OPCG_REG1 = 0x03030003ull;
+
+static const uint64_t P9N2_PERV_N2_OPCG_REG1 = 0x04030003ull;
+
+static const uint64_t P9N2_PERV_N3_OPCG_REG1 = 0x05030003ull;
+
+static const uint64_t P9N2_PERV_XB_OPCG_REG1 = 0x06030003ull;
+
+static const uint64_t P9N2_PERV_MC01_OPCG_REG1 = 0x07030003ull;
+
+static const uint64_t P9N2_PERV_MC23_OPCG_REG1 = 0x08030003ull;
+
+static const uint64_t P9N2_PERV_OB0_OPCG_REG1 = 0x09030003ull;
+
+static const uint64_t P9N2_PERV_OB3_OPCG_REG1 = 0x0C030003ull;
+
+static const uint64_t P9N2_PERV_PCI0_OPCG_REG1 = 0x0D030003ull;
+
+static const uint64_t P9N2_PERV_PCI1_OPCG_REG1 = 0x0E030003ull;
+
+static const uint64_t P9N2_PERV_PCI2_OPCG_REG1 = 0x0F030003ull;
+
+static const uint64_t P9N2_PERV_EP00_OPCG_REG1 = 0x10030003ull;
+
+static const uint64_t P9N2_PERV_EP01_OPCG_REG1 = 0x11030003ull;
+
+static const uint64_t P9N2_PERV_EP02_OPCG_REG1 = 0x12030003ull;
+
+static const uint64_t P9N2_PERV_EP03_OPCG_REG1 = 0x13030003ull;
+
+static const uint64_t P9N2_PERV_EP04_OPCG_REG1 = 0x14030003ull;
+
+static const uint64_t P9N2_PERV_EP05_OPCG_REG1 = 0x15030003ull;
+
+static const uint64_t P9N2_PERV_EC00_OPCG_REG1 = 0x20030003ull;
+
+static const uint64_t P9N2_PERV_EC01_OPCG_REG1 = 0x21030003ull;
+
+static const uint64_t P9N2_PERV_EC02_OPCG_REG1 = 0x22030003ull;
+
+static const uint64_t P9N2_PERV_EC03_OPCG_REG1 = 0x23030003ull;
+
+static const uint64_t P9N2_PERV_EC04_OPCG_REG1 = 0x24030003ull;
+
+static const uint64_t P9N2_PERV_EC05_OPCG_REG1 = 0x25030003ull;
+
+static const uint64_t P9N2_PERV_EC06_OPCG_REG1 = 0x26030003ull;
+
+static const uint64_t P9N2_PERV_EC07_OPCG_REG1 = 0x27030003ull;
+
+static const uint64_t P9N2_PERV_EC08_OPCG_REG1 = 0x28030003ull;
+
+static const uint64_t P9N2_PERV_EC09_OPCG_REG1 = 0x29030003ull;
+
+static const uint64_t P9N2_PERV_EC10_OPCG_REG1 = 0x2A030003ull;
+
+static const uint64_t P9N2_PERV_EC11_OPCG_REG1 = 0x2B030003ull;
+
+static const uint64_t P9N2_PERV_EC12_OPCG_REG1 = 0x2C030003ull;
+
+static const uint64_t P9N2_PERV_EC13_OPCG_REG1 = 0x2D030003ull;
+
+static const uint64_t P9N2_PERV_EC14_OPCG_REG1 = 0x2E030003ull;
+
+static const uint64_t P9N2_PERV_EC15_OPCG_REG1 = 0x2F030003ull;
+
+static const uint64_t P9N2_PERV_EC16_OPCG_REG1 = 0x30030003ull;
+
+static const uint64_t P9N2_PERV_EC17_OPCG_REG1 = 0x31030003ull;
+
+static const uint64_t P9N2_PERV_EC18_OPCG_REG1 = 0x32030003ull;
+
+static const uint64_t P9N2_PERV_EC19_OPCG_REG1 = 0x33030003ull;
+
+static const uint64_t P9N2_PERV_EC20_OPCG_REG1 = 0x34030003ull;
+
+static const uint64_t P9N2_PERV_EC21_OPCG_REG1 = 0x35030003ull;
+
+static const uint64_t P9N2_PERV_EC22_OPCG_REG1 = 0x36030003ull;
+
+static const uint64_t P9N2_PERV_EC23_OPCG_REG1 = 0x37030003ull;
+
+
+static const uint64_t P9N2_PERV_OPCG_REG2 = 0x00030004ull;
+
+static const uint64_t P9N2_PERV_TP_OPCG_REG2 = 0x01030004ull;
+
+static const uint64_t P9N2_PERV_N0_OPCG_REG2 = 0x02030004ull;
+
+static const uint64_t P9N2_PERV_N1_OPCG_REG2 = 0x03030004ull;
+
+static const uint64_t P9N2_PERV_N2_OPCG_REG2 = 0x04030004ull;
+
+static const uint64_t P9N2_PERV_N3_OPCG_REG2 = 0x05030004ull;
+
+static const uint64_t P9N2_PERV_XB_OPCG_REG2 = 0x06030004ull;
+
+static const uint64_t P9N2_PERV_MC01_OPCG_REG2 = 0x07030004ull;
+
+static const uint64_t P9N2_PERV_MC23_OPCG_REG2 = 0x08030004ull;
+
+static const uint64_t P9N2_PERV_OB0_OPCG_REG2 = 0x09030004ull;
+
+static const uint64_t P9N2_PERV_OB3_OPCG_REG2 = 0x0C030004ull;
+
+static const uint64_t P9N2_PERV_PCI0_OPCG_REG2 = 0x0D030004ull;
+
+static const uint64_t P9N2_PERV_PCI1_OPCG_REG2 = 0x0E030004ull;
+
+static const uint64_t P9N2_PERV_PCI2_OPCG_REG2 = 0x0F030004ull;
+
+static const uint64_t P9N2_PERV_EP00_OPCG_REG2 = 0x10030004ull;
+
+static const uint64_t P9N2_PERV_EP01_OPCG_REG2 = 0x11030004ull;
+
+static const uint64_t P9N2_PERV_EP02_OPCG_REG2 = 0x12030004ull;
+
+static const uint64_t P9N2_PERV_EP03_OPCG_REG2 = 0x13030004ull;
+
+static const uint64_t P9N2_PERV_EP04_OPCG_REG2 = 0x14030004ull;
+
+static const uint64_t P9N2_PERV_EP05_OPCG_REG2 = 0x15030004ull;
+
+static const uint64_t P9N2_PERV_EC00_OPCG_REG2 = 0x20030004ull;
+
+static const uint64_t P9N2_PERV_EC01_OPCG_REG2 = 0x21030004ull;
+
+static const uint64_t P9N2_PERV_EC02_OPCG_REG2 = 0x22030004ull;
+
+static const uint64_t P9N2_PERV_EC03_OPCG_REG2 = 0x23030004ull;
+
+static const uint64_t P9N2_PERV_EC04_OPCG_REG2 = 0x24030004ull;
+
+static const uint64_t P9N2_PERV_EC05_OPCG_REG2 = 0x25030004ull;
+
+static const uint64_t P9N2_PERV_EC06_OPCG_REG2 = 0x26030004ull;
+
+static const uint64_t P9N2_PERV_EC07_OPCG_REG2 = 0x27030004ull;
+
+static const uint64_t P9N2_PERV_EC08_OPCG_REG2 = 0x28030004ull;
+
+static const uint64_t P9N2_PERV_EC09_OPCG_REG2 = 0x29030004ull;
+
+static const uint64_t P9N2_PERV_EC10_OPCG_REG2 = 0x2A030004ull;
+
+static const uint64_t P9N2_PERV_EC11_OPCG_REG2 = 0x2B030004ull;
+
+static const uint64_t P9N2_PERV_EC12_OPCG_REG2 = 0x2C030004ull;
+
+static const uint64_t P9N2_PERV_EC13_OPCG_REG2 = 0x2D030004ull;
+
+static const uint64_t P9N2_PERV_EC14_OPCG_REG2 = 0x2E030004ull;
+
+static const uint64_t P9N2_PERV_EC15_OPCG_REG2 = 0x2F030004ull;
+
+static const uint64_t P9N2_PERV_EC16_OPCG_REG2 = 0x30030004ull;
+
+static const uint64_t P9N2_PERV_EC17_OPCG_REG2 = 0x31030004ull;
+
+static const uint64_t P9N2_PERV_EC18_OPCG_REG2 = 0x32030004ull;
+
+static const uint64_t P9N2_PERV_EC19_OPCG_REG2 = 0x33030004ull;
+
+static const uint64_t P9N2_PERV_EC20_OPCG_REG2 = 0x34030004ull;
+
+static const uint64_t P9N2_PERV_EC21_OPCG_REG2 = 0x35030004ull;
+
+static const uint64_t P9N2_PERV_EC22_OPCG_REG2 = 0x36030004ull;
+
+static const uint64_t P9N2_PERV_EC23_OPCG_REG2 = 0x37030004ull;
+
+
+static const uint64_t P9N2_PERV_OSCERR_HOLD = 0x00020019ull;
+
+static const uint64_t P9N2_PERV_TP_OSCERR_HOLD = 0x01020019ull;
+
+
+static const uint64_t P9N2_PERV_OSCERR_MASK = 0x0002001Aull;
+
+static const uint64_t P9N2_PERV_TP_OSCERR_MASK = 0x0102001Aull;
+
+
+static const uint64_t P9N2_PERV_OSCERR_MCODE = 0x0002001Bull;
+
+static const uint64_t P9N2_PERV_TP_OSCERR_MCODE = 0x0102001Bull;
+
+
+static const uint64_t P9N2_PERV_PCB_OPCG_GO = 0x00030020ull;
+
+static const uint64_t P9N2_PERV_TP_PCB_OPCG_GO = 0x01030020ull;
+
+static const uint64_t P9N2_PERV_N0_PCB_OPCG_GO = 0x02030020ull;
+
+static const uint64_t P9N2_PERV_N1_PCB_OPCG_GO = 0x03030020ull;
+
+static const uint64_t P9N2_PERV_N2_PCB_OPCG_GO = 0x04030020ull;
+
+static const uint64_t P9N2_PERV_N3_PCB_OPCG_GO = 0x05030020ull;
+
+static const uint64_t P9N2_PERV_XB_PCB_OPCG_GO = 0x06030020ull;
+
+static const uint64_t P9N2_PERV_MC01_PCB_OPCG_GO = 0x07030020ull;
+
+static const uint64_t P9N2_PERV_MC23_PCB_OPCG_GO = 0x08030020ull;
+
+static const uint64_t P9N2_PERV_OB0_PCB_OPCG_GO = 0x09030020ull;
+
+static const uint64_t P9N2_PERV_OB3_PCB_OPCG_GO = 0x0C030020ull;
+
+static const uint64_t P9N2_PERV_PCI0_PCB_OPCG_GO = 0x0D030020ull;
+
+static const uint64_t P9N2_PERV_PCI1_PCB_OPCG_GO = 0x0E030020ull;
+
+static const uint64_t P9N2_PERV_PCI2_PCB_OPCG_GO = 0x0F030020ull;
+
+static const uint64_t P9N2_PERV_EP00_PCB_OPCG_GO = 0x10030020ull;
+
+static const uint64_t P9N2_PERV_EP01_PCB_OPCG_GO = 0x11030020ull;
+
+static const uint64_t P9N2_PERV_EP02_PCB_OPCG_GO = 0x12030020ull;
+
+static const uint64_t P9N2_PERV_EP03_PCB_OPCG_GO = 0x13030020ull;
+
+static const uint64_t P9N2_PERV_EP04_PCB_OPCG_GO = 0x14030020ull;
+
+static const uint64_t P9N2_PERV_EP05_PCB_OPCG_GO = 0x15030020ull;
+
+static const uint64_t P9N2_PERV_EC00_PCB_OPCG_GO = 0x20030020ull;
+
+static const uint64_t P9N2_PERV_EC01_PCB_OPCG_GO = 0x21030020ull;
+
+static const uint64_t P9N2_PERV_EC02_PCB_OPCG_GO = 0x22030020ull;
+
+static const uint64_t P9N2_PERV_EC03_PCB_OPCG_GO = 0x23030020ull;
+
+static const uint64_t P9N2_PERV_EC04_PCB_OPCG_GO = 0x24030020ull;
+
+static const uint64_t P9N2_PERV_EC05_PCB_OPCG_GO = 0x25030020ull;
+
+static const uint64_t P9N2_PERV_EC06_PCB_OPCG_GO = 0x26030020ull;
+
+static const uint64_t P9N2_PERV_EC07_PCB_OPCG_GO = 0x27030020ull;
+
+static const uint64_t P9N2_PERV_EC08_PCB_OPCG_GO = 0x28030020ull;
+
+static const uint64_t P9N2_PERV_EC09_PCB_OPCG_GO = 0x29030020ull;
+
+static const uint64_t P9N2_PERV_EC10_PCB_OPCG_GO = 0x2A030020ull;
+
+static const uint64_t P9N2_PERV_EC11_PCB_OPCG_GO = 0x2B030020ull;
+
+static const uint64_t P9N2_PERV_EC12_PCB_OPCG_GO = 0x2C030020ull;
+
+static const uint64_t P9N2_PERV_EC13_PCB_OPCG_GO = 0x2D030020ull;
+
+static const uint64_t P9N2_PERV_EC14_PCB_OPCG_GO = 0x2E030020ull;
+
+static const uint64_t P9N2_PERV_EC15_PCB_OPCG_GO = 0x2F030020ull;
+
+static const uint64_t P9N2_PERV_EC16_PCB_OPCG_GO = 0x30030020ull;
+
+static const uint64_t P9N2_PERV_EC17_PCB_OPCG_GO = 0x31030020ull;
+
+static const uint64_t P9N2_PERV_EC18_PCB_OPCG_GO = 0x32030020ull;
+
+static const uint64_t P9N2_PERV_EC19_PCB_OPCG_GO = 0x33030020ull;
+
+static const uint64_t P9N2_PERV_EC20_PCB_OPCG_GO = 0x34030020ull;
+
+static const uint64_t P9N2_PERV_EC21_PCB_OPCG_GO = 0x35030020ull;
+
+static const uint64_t P9N2_PERV_EC22_PCB_OPCG_GO = 0x36030020ull;
+
+static const uint64_t P9N2_PERV_EC23_PCB_OPCG_GO = 0x37030020ull;
+
+
+static const uint64_t P9N2_PERV_PCB_OPCG_STOP = 0x00030030ull;
+
+static const uint64_t P9N2_PERV_TP_PCB_OPCG_STOP = 0x01030030ull;
+
+static const uint64_t P9N2_PERV_N0_PCB_OPCG_STOP = 0x02030030ull;
+
+static const uint64_t P9N2_PERV_N1_PCB_OPCG_STOP = 0x03030030ull;
+
+static const uint64_t P9N2_PERV_N2_PCB_OPCG_STOP = 0x04030030ull;
+
+static const uint64_t P9N2_PERV_N3_PCB_OPCG_STOP = 0x05030030ull;
+
+static const uint64_t P9N2_PERV_XB_PCB_OPCG_STOP = 0x06030030ull;
+
+static const uint64_t P9N2_PERV_MC01_PCB_OPCG_STOP = 0x07030030ull;
+
+static const uint64_t P9N2_PERV_MC23_PCB_OPCG_STOP = 0x08030030ull;
+
+static const uint64_t P9N2_PERV_OB0_PCB_OPCG_STOP = 0x09030030ull;
+
+static const uint64_t P9N2_PERV_OB3_PCB_OPCG_STOP = 0x0C030030ull;
+
+static const uint64_t P9N2_PERV_PCI0_PCB_OPCG_STOP = 0x0D030030ull;
+
+static const uint64_t P9N2_PERV_PCI1_PCB_OPCG_STOP = 0x0E030030ull;
+
+static const uint64_t P9N2_PERV_PCI2_PCB_OPCG_STOP = 0x0F030030ull;
+
+static const uint64_t P9N2_PERV_EP00_PCB_OPCG_STOP = 0x10030030ull;
+
+static const uint64_t P9N2_PERV_EP01_PCB_OPCG_STOP = 0x11030030ull;
+
+static const uint64_t P9N2_PERV_EP02_PCB_OPCG_STOP = 0x12030030ull;
+
+static const uint64_t P9N2_PERV_EP03_PCB_OPCG_STOP = 0x13030030ull;
+
+static const uint64_t P9N2_PERV_EP04_PCB_OPCG_STOP = 0x14030030ull;
+
+static const uint64_t P9N2_PERV_EP05_PCB_OPCG_STOP = 0x15030030ull;
+
+static const uint64_t P9N2_PERV_EC00_PCB_OPCG_STOP = 0x20030030ull;
+
+static const uint64_t P9N2_PERV_EC01_PCB_OPCG_STOP = 0x21030030ull;
+
+static const uint64_t P9N2_PERV_EC02_PCB_OPCG_STOP = 0x22030030ull;
+
+static const uint64_t P9N2_PERV_EC03_PCB_OPCG_STOP = 0x23030030ull;
+
+static const uint64_t P9N2_PERV_EC04_PCB_OPCG_STOP = 0x24030030ull;
+
+static const uint64_t P9N2_PERV_EC05_PCB_OPCG_STOP = 0x25030030ull;
+
+static const uint64_t P9N2_PERV_EC06_PCB_OPCG_STOP = 0x26030030ull;
+
+static const uint64_t P9N2_PERV_EC07_PCB_OPCG_STOP = 0x27030030ull;
+
+static const uint64_t P9N2_PERV_EC08_PCB_OPCG_STOP = 0x28030030ull;
+
+static const uint64_t P9N2_PERV_EC09_PCB_OPCG_STOP = 0x29030030ull;
+
+static const uint64_t P9N2_PERV_EC10_PCB_OPCG_STOP = 0x2A030030ull;
+
+static const uint64_t P9N2_PERV_EC11_PCB_OPCG_STOP = 0x2B030030ull;
+
+static const uint64_t P9N2_PERV_EC12_PCB_OPCG_STOP = 0x2C030030ull;
+
+static const uint64_t P9N2_PERV_EC13_PCB_OPCG_STOP = 0x2D030030ull;
+
+static const uint64_t P9N2_PERV_EC14_PCB_OPCG_STOP = 0x2E030030ull;
+
+static const uint64_t P9N2_PERV_EC15_PCB_OPCG_STOP = 0x2F030030ull;
+
+static const uint64_t P9N2_PERV_EC16_PCB_OPCG_STOP = 0x30030030ull;
+
+static const uint64_t P9N2_PERV_EC17_PCB_OPCG_STOP = 0x31030030ull;
+
+static const uint64_t P9N2_PERV_EC18_PCB_OPCG_STOP = 0x32030030ull;
+
+static const uint64_t P9N2_PERV_EC19_PCB_OPCG_STOP = 0x33030030ull;
+
+static const uint64_t P9N2_PERV_EC20_PCB_OPCG_STOP = 0x34030030ull;
+
+static const uint64_t P9N2_PERV_EC21_PCB_OPCG_STOP = 0x35030030ull;
+
+static const uint64_t P9N2_PERV_EC22_PCB_OPCG_STOP = 0x36030030ull;
+
+static const uint64_t P9N2_PERV_EC23_PCB_OPCG_STOP = 0x37030030ull;
+
+
+static const uint32_t P9N2_PERV_PEEK4A0_FSI = 0x000004A0ull;
+
+
+static const uint32_t P9N2_PERV_PEEK4A4_FSI = 0x000004A4ull;
+
+
+static const uint32_t P9N2_PERV_PEEK4A8_FSI = 0x000004A8ull;
+
+
+static const uint32_t P9N2_PERV_PEEK4AC_FSI = 0x000004ACull;
+
+
+static const uint32_t P9N2_PERV_PEEK4B0_FSI = 0x000004B0ull;
+
+
+static const uint32_t P9N2_PERV_PEEK4B4_FSI = 0x000004B4ull;
+
+
+static const uint32_t P9N2_PERV_PEEK4B8_FSI = 0x000004B8ull;
+
+
+static const uint32_t P9N2_PERV_PERV_CTRL0_FSI = 0x0000281Aull;
+
+static const uint32_t P9N2_PERV_PERV_CTRL0_FSI_BYTE = 0x00002868ull;
+
+static const uint64_t P9N2_PERV_PERV_CTRL0_SCOM = 0x0005001Aull;
+
+static const uint64_t P9N2_PERV_PIB_PERV_CTRL0 = 0x0005001Aull;
+
+
+static const uint32_t P9N2_PERV_PERV_CTRL0_CLEAR_FSI = 0x0000293Aull;
+
+static const uint32_t P9N2_PERV_PERV_CTRL0_CLEAR_FSI_BYTE = 0x00002CE8ull;
+
+static const uint64_t P9N2_PERV_PERV_CTRL0_CLEAR_SCOM = 0x0005013Aull;
+
+static const uint64_t P9N2_PERV_PIB_PERV_CTRL0_CLEAR = 0x0005013Aull;
+
+
+static const uint32_t P9N2_PERV_PERV_CTRL0_COPY_FSI = 0x0000291Aull;
+
+static const uint32_t P9N2_PERV_PERV_CTRL0_COPY_FSI_BYTE = 0x00002C68ull;
+
+static const uint64_t P9N2_PERV_PERV_CTRL0_COPY_SCOM = 0x0005011Aull;
+
+static const uint64_t P9N2_PERV_PIB_PERV_CTRL0_COPY = 0x0005011Aull;
+
+
+static const uint32_t P9N2_PERV_PERV_CTRL0_SET_FSI = 0x0000292Aull;
+
+static const uint32_t P9N2_PERV_PERV_CTRL0_SET_FSI_BYTE = 0x00002CA8ull;
+
+static const uint64_t P9N2_PERV_PERV_CTRL0_SET_SCOM = 0x0005012Aull;
+
+static const uint64_t P9N2_PERV_PIB_PERV_CTRL0_SET = 0x0005012Aull;
+
+
+static const uint32_t P9N2_PERV_PERV_CTRL1_FSI = 0x0000281Bull;
+
+static const uint32_t P9N2_PERV_PERV_CTRL1_FSI_BYTE = 0x0000286Cull;
+
+static const uint64_t P9N2_PERV_PERV_CTRL1_SCOM = 0x0005001Bull;
+
+static const uint64_t P9N2_PERV_PIB_PERV_CTRL1 = 0x0005001Bull;
+
+
+static const uint32_t P9N2_PERV_PERV_CTRL1_CLEAR_FSI = 0x0000293Bull;
+
+static const uint32_t P9N2_PERV_PERV_CTRL1_CLEAR_FSI_BYTE = 0x00002CECull;
+
+static const uint64_t P9N2_PERV_PERV_CTRL1_CLEAR_SCOM = 0x0005013Bull;
+
+static const uint64_t P9N2_PERV_PIB_PERV_CTRL1_CLEAR = 0x0005013Bull;
+
+
+static const uint32_t P9N2_PERV_PERV_CTRL1_COPY_FSI = 0x0000291Bull;
+
+static const uint32_t P9N2_PERV_PERV_CTRL1_COPY_FSI_BYTE = 0x00002C6Cull;
+
+static const uint64_t P9N2_PERV_PERV_CTRL1_COPY_SCOM = 0x0005011Bull;
+
+static const uint64_t P9N2_PERV_PIB_PERV_CTRL1_COPY = 0x0005011Bull;
+
+
+static const uint32_t P9N2_PERV_PERV_CTRL1_SET_FSI = 0x0000292Bull;
+
+static const uint32_t P9N2_PERV_PERV_CTRL1_SET_FSI_BYTE = 0x00002CACull;
+
+static const uint64_t P9N2_PERV_PERV_CTRL1_SET_SCOM = 0x0005012Bull;
+
+static const uint64_t P9N2_PERV_PIB_PERV_CTRL1_SET = 0x0005012Bull;
+
+
+static const uint64_t P9N2_PERV_PLL_LOCK_REG = 0x000F0019ull;
+
+static const uint64_t P9N2_PERV_TP_PLL_LOCK_REG = 0x010F0019ull;
+
+static const uint64_t P9N2_PERV_N0_PLL_LOCK_REG = 0x020F0019ull;
+
+static const uint64_t P9N2_PERV_N1_PLL_LOCK_REG = 0x030F0019ull;
+
+static const uint64_t P9N2_PERV_N2_PLL_LOCK_REG = 0x040F0019ull;
+
+static const uint64_t P9N2_PERV_N3_PLL_LOCK_REG = 0x050F0019ull;
+
+static const uint64_t P9N2_PERV_XB_PLL_LOCK_REG = 0x060F0019ull;
+
+static const uint64_t P9N2_PERV_MC01_PLL_LOCK_REG = 0x070F0019ull;
+
+static const uint64_t P9N2_PERV_MC23_PLL_LOCK_REG = 0x080F0019ull;
+
+static const uint64_t P9N2_PERV_OB0_PLL_LOCK_REG = 0x090F0019ull;
+
+static const uint64_t P9N2_PERV_OB3_PLL_LOCK_REG = 0x0C0F0019ull;
+
+static const uint64_t P9N2_PERV_PCI0_PLL_LOCK_REG = 0x0D0F0019ull;
+
+static const uint64_t P9N2_PERV_PCI1_PLL_LOCK_REG = 0x0E0F0019ull;
+
+static const uint64_t P9N2_PERV_PCI2_PLL_LOCK_REG = 0x0F0F0019ull;
+
+static const uint64_t P9N2_PERV_EP00_PLL_LOCK_REG = 0x100F0019ull;
+
+static const uint64_t P9N2_PERV_EP01_PLL_LOCK_REG = 0x110F0019ull;
+
+static const uint64_t P9N2_PERV_EP02_PLL_LOCK_REG = 0x120F0019ull;
+
+static const uint64_t P9N2_PERV_EP03_PLL_LOCK_REG = 0x130F0019ull;
+
+static const uint64_t P9N2_PERV_EP04_PLL_LOCK_REG = 0x140F0019ull;
+
+static const uint64_t P9N2_PERV_EP05_PLL_LOCK_REG = 0x150F0019ull;
+
+static const uint64_t P9N2_PERV_EC00_PLL_LOCK_REG = 0x200F0019ull;
+
+static const uint64_t P9N2_PERV_EC01_PLL_LOCK_REG = 0x210F0019ull;
+
+static const uint64_t P9N2_PERV_EC02_PLL_LOCK_REG = 0x220F0019ull;
+
+static const uint64_t P9N2_PERV_EC03_PLL_LOCK_REG = 0x230F0019ull;
+
+static const uint64_t P9N2_PERV_EC04_PLL_LOCK_REG = 0x240F0019ull;
+
+static const uint64_t P9N2_PERV_EC05_PLL_LOCK_REG = 0x250F0019ull;
+
+static const uint64_t P9N2_PERV_EC06_PLL_LOCK_REG = 0x260F0019ull;
+
+static const uint64_t P9N2_PERV_EC07_PLL_LOCK_REG = 0x270F0019ull;
+
+static const uint64_t P9N2_PERV_EC08_PLL_LOCK_REG = 0x280F0019ull;
+
+static const uint64_t P9N2_PERV_EC09_PLL_LOCK_REG = 0x290F0019ull;
+
+static const uint64_t P9N2_PERV_EC10_PLL_LOCK_REG = 0x2A0F0019ull;
+
+static const uint64_t P9N2_PERV_EC11_PLL_LOCK_REG = 0x2B0F0019ull;
+
+static const uint64_t P9N2_PERV_EC12_PLL_LOCK_REG = 0x2C0F0019ull;
+
+static const uint64_t P9N2_PERV_EC13_PLL_LOCK_REG = 0x2D0F0019ull;
+
+static const uint64_t P9N2_PERV_EC14_PLL_LOCK_REG = 0x2E0F0019ull;
+
+static const uint64_t P9N2_PERV_EC15_PLL_LOCK_REG = 0x2F0F0019ull;
+
+static const uint64_t P9N2_PERV_EC16_PLL_LOCK_REG = 0x300F0019ull;
+
+static const uint64_t P9N2_PERV_EC17_PLL_LOCK_REG = 0x310F0019ull;
+
+static const uint64_t P9N2_PERV_EC18_PLL_LOCK_REG = 0x320F0019ull;
+
+static const uint64_t P9N2_PERV_EC19_PLL_LOCK_REG = 0x330F0019ull;
+
+static const uint64_t P9N2_PERV_EC20_PLL_LOCK_REG = 0x340F0019ull;
+
+static const uint64_t P9N2_PERV_EC21_PLL_LOCK_REG = 0x350F0019ull;
+
+static const uint64_t P9N2_PERV_EC22_PLL_LOCK_REG = 0x360F0019ull;
+
+static const uint64_t P9N2_PERV_EC23_PLL_LOCK_REG = 0x370F0019ull;
+
+
+static const uint64_t P9N2_PERV_EP00_PPM_CGCR = 0x100F0164ull;
+
+static const uint64_t P9N2_PERV_EP01_PPM_CGCR = 0x110F0164ull;
+
+static const uint64_t P9N2_PERV_EP02_PPM_CGCR = 0x120F0164ull;
+
+static const uint64_t P9N2_PERV_EP03_PPM_CGCR = 0x130F0164ull;
+
+static const uint64_t P9N2_PERV_EP04_PPM_CGCR = 0x140F0164ull;
+
+static const uint64_t P9N2_PERV_EP05_PPM_CGCR = 0x150F0164ull;
+
+static const uint64_t P9N2_PERV_EC00_PPM_CGCR = 0x200F0164ull;
+
+static const uint64_t P9N2_PERV_EC01_PPM_CGCR = 0x210F0164ull;
+
+static const uint64_t P9N2_PERV_EC02_PPM_CGCR = 0x220F0164ull;
+
+static const uint64_t P9N2_PERV_EC03_PPM_CGCR = 0x230F0164ull;
+
+static const uint64_t P9N2_PERV_EC04_PPM_CGCR = 0x240F0164ull;
+
+static const uint64_t P9N2_PERV_EC05_PPM_CGCR = 0x250F0164ull;
+
+static const uint64_t P9N2_PERV_EC06_PPM_CGCR = 0x260F0164ull;
+
+static const uint64_t P9N2_PERV_EC07_PPM_CGCR = 0x270F0164ull;
+
+static const uint64_t P9N2_PERV_EC08_PPM_CGCR = 0x280F0164ull;
+
+static const uint64_t P9N2_PERV_EC09_PPM_CGCR = 0x290F0164ull;
+
+static const uint64_t P9N2_PERV_EC10_PPM_CGCR = 0x2A0F0164ull;
+
+static const uint64_t P9N2_PERV_EC11_PPM_CGCR = 0x2B0F0164ull;
+
+static const uint64_t P9N2_PERV_EC12_PPM_CGCR = 0x2C0F0164ull;
+
+static const uint64_t P9N2_PERV_EC13_PPM_CGCR = 0x2D0F0164ull;
+
+static const uint64_t P9N2_PERV_EC14_PPM_CGCR = 0x2E0F0164ull;
+
+static const uint64_t P9N2_PERV_EC15_PPM_CGCR = 0x2F0F0164ull;
+
+static const uint64_t P9N2_PERV_EC16_PPM_CGCR = 0x300F0164ull;
+
+static const uint64_t P9N2_PERV_EC17_PPM_CGCR = 0x310F0164ull;
+
+static const uint64_t P9N2_PERV_EC18_PPM_CGCR = 0x320F0164ull;
+
+static const uint64_t P9N2_PERV_EC19_PPM_CGCR = 0x330F0164ull;
+
+static const uint64_t P9N2_PERV_EC20_PPM_CGCR = 0x340F0164ull;
+
+static const uint64_t P9N2_PERV_EC21_PPM_CGCR = 0x350F0164ull;
+
+static const uint64_t P9N2_PERV_EC22_PPM_CGCR = 0x360F0164ull;
+
+static const uint64_t P9N2_PERV_EC23_PPM_CGCR = 0x370F0164ull;
+
+
+static const uint64_t P9N2_PERV_EP00_PPM_GPMMR_SCOM = 0x100F0100ull;
+
+static const uint64_t P9N2_PERV_EP00_PPM_GPMMR_SCOM1 = 0x100F0101ull;
+
+static const uint64_t P9N2_PERV_EP00_PPM_GPMMR_SCOM2 = 0x100F0102ull;
+
+static const uint64_t P9N2_PERV_EP01_PPM_GPMMR_SCOM = 0x110F0100ull;
+
+static const uint64_t P9N2_PERV_EP01_PPM_GPMMR_SCOM1 = 0x110F0101ull;
+
+static const uint64_t P9N2_PERV_EP01_PPM_GPMMR_SCOM2 = 0x110F0102ull;
+
+static const uint64_t P9N2_PERV_EP02_PPM_GPMMR_SCOM = 0x120F0100ull;
+
+static const uint64_t P9N2_PERV_EP02_PPM_GPMMR_SCOM1 = 0x120F0101ull;
+
+static const uint64_t P9N2_PERV_EP02_PPM_GPMMR_SCOM2 = 0x120F0102ull;
+
+static const uint64_t P9N2_PERV_EP03_PPM_GPMMR_SCOM = 0x130F0100ull;
+
+static const uint64_t P9N2_PERV_EP03_PPM_GPMMR_SCOM1 = 0x130F0101ull;
+
+static const uint64_t P9N2_PERV_EP03_PPM_GPMMR_SCOM2 = 0x130F0102ull;
+
+static const uint64_t P9N2_PERV_EP04_PPM_GPMMR_SCOM = 0x140F0100ull;
+
+static const uint64_t P9N2_PERV_EP04_PPM_GPMMR_SCOM1 = 0x140F0101ull;
+
+static const uint64_t P9N2_PERV_EP04_PPM_GPMMR_SCOM2 = 0x140F0102ull;
+
+static const uint64_t P9N2_PERV_EP05_PPM_GPMMR_SCOM = 0x150F0100ull;
+
+static const uint64_t P9N2_PERV_EP05_PPM_GPMMR_SCOM1 = 0x150F0101ull;
+
+static const uint64_t P9N2_PERV_EP05_PPM_GPMMR_SCOM2 = 0x150F0102ull;
+
+static const uint64_t P9N2_PERV_EC00_PPM_GPMMR_SCOM = 0x200F0100ull;
+
+static const uint64_t P9N2_PERV_EC00_PPM_GPMMR_SCOM1 = 0x200F0101ull;
+
+static const uint64_t P9N2_PERV_EC00_PPM_GPMMR_SCOM2 = 0x200F0102ull;
+
+static const uint64_t P9N2_PERV_EC01_PPM_GPMMR_SCOM = 0x210F0100ull;
+
+static const uint64_t P9N2_PERV_EC01_PPM_GPMMR_SCOM1 = 0x210F0101ull;
+
+static const uint64_t P9N2_PERV_EC01_PPM_GPMMR_SCOM2 = 0x210F0102ull;
+
+static const uint64_t P9N2_PERV_EC02_PPM_GPMMR_SCOM = 0x220F0100ull;
+
+static const uint64_t P9N2_PERV_EC02_PPM_GPMMR_SCOM1 = 0x220F0101ull;
+
+static const uint64_t P9N2_PERV_EC02_PPM_GPMMR_SCOM2 = 0x220F0102ull;
+
+static const uint64_t P9N2_PERV_EC03_PPM_GPMMR_SCOM = 0x230F0100ull;
+
+static const uint64_t P9N2_PERV_EC03_PPM_GPMMR_SCOM1 = 0x230F0101ull;
+
+static const uint64_t P9N2_PERV_EC03_PPM_GPMMR_SCOM2 = 0x230F0102ull;
+
+static const uint64_t P9N2_PERV_EC04_PPM_GPMMR_SCOM = 0x240F0100ull;
+
+static const uint64_t P9N2_PERV_EC04_PPM_GPMMR_SCOM1 = 0x240F0101ull;
+
+static const uint64_t P9N2_PERV_EC04_PPM_GPMMR_SCOM2 = 0x240F0102ull;
+
+static const uint64_t P9N2_PERV_EC05_PPM_GPMMR_SCOM = 0x250F0100ull;
+
+static const uint64_t P9N2_PERV_EC05_PPM_GPMMR_SCOM1 = 0x250F0101ull;
+
+static const uint64_t P9N2_PERV_EC05_PPM_GPMMR_SCOM2 = 0x250F0102ull;
+
+static const uint64_t P9N2_PERV_EC06_PPM_GPMMR_SCOM = 0x260F0100ull;
+
+static const uint64_t P9N2_PERV_EC06_PPM_GPMMR_SCOM1 = 0x260F0101ull;
+
+static const uint64_t P9N2_PERV_EC06_PPM_GPMMR_SCOM2 = 0x260F0102ull;
+
+static const uint64_t P9N2_PERV_EC07_PPM_GPMMR_SCOM = 0x270F0100ull;
+
+static const uint64_t P9N2_PERV_EC07_PPM_GPMMR_SCOM1 = 0x270F0101ull;
+
+static const uint64_t P9N2_PERV_EC07_PPM_GPMMR_SCOM2 = 0x270F0102ull;
+
+static const uint64_t P9N2_PERV_EC08_PPM_GPMMR_SCOM = 0x280F0100ull;
+
+static const uint64_t P9N2_PERV_EC08_PPM_GPMMR_SCOM1 = 0x280F0101ull;
+
+static const uint64_t P9N2_PERV_EC08_PPM_GPMMR_SCOM2 = 0x280F0102ull;
+
+static const uint64_t P9N2_PERV_EC09_PPM_GPMMR_SCOM = 0x290F0100ull;
+
+static const uint64_t P9N2_PERV_EC09_PPM_GPMMR_SCOM1 = 0x290F0101ull;
+
+static const uint64_t P9N2_PERV_EC09_PPM_GPMMR_SCOM2 = 0x290F0102ull;
+
+static const uint64_t P9N2_PERV_EC10_PPM_GPMMR_SCOM = 0x2A0F0100ull;
+
+static const uint64_t P9N2_PERV_EC10_PPM_GPMMR_SCOM1 = 0x2A0F0101ull;
+
+static const uint64_t P9N2_PERV_EC10_PPM_GPMMR_SCOM2 = 0x2A0F0102ull;
+
+static const uint64_t P9N2_PERV_EC11_PPM_GPMMR_SCOM = 0x2B0F0100ull;
+
+static const uint64_t P9N2_PERV_EC11_PPM_GPMMR_SCOM1 = 0x2B0F0101ull;
+
+static const uint64_t P9N2_PERV_EC11_PPM_GPMMR_SCOM2 = 0x2B0F0102ull;
+
+static const uint64_t P9N2_PERV_EC12_PPM_GPMMR_SCOM = 0x2C0F0100ull;
+
+static const uint64_t P9N2_PERV_EC12_PPM_GPMMR_SCOM1 = 0x2C0F0101ull;
+
+static const uint64_t P9N2_PERV_EC12_PPM_GPMMR_SCOM2 = 0x2C0F0102ull;
+
+static const uint64_t P9N2_PERV_EC13_PPM_GPMMR_SCOM = 0x2D0F0100ull;
+
+static const uint64_t P9N2_PERV_EC13_PPM_GPMMR_SCOM1 = 0x2D0F0101ull;
+
+static const uint64_t P9N2_PERV_EC13_PPM_GPMMR_SCOM2 = 0x2D0F0102ull;
+
+static const uint64_t P9N2_PERV_EC14_PPM_GPMMR_SCOM = 0x2E0F0100ull;
+
+static const uint64_t P9N2_PERV_EC14_PPM_GPMMR_SCOM1 = 0x2E0F0101ull;
+
+static const uint64_t P9N2_PERV_EC14_PPM_GPMMR_SCOM2 = 0x2E0F0102ull;
+
+static const uint64_t P9N2_PERV_EC15_PPM_GPMMR_SCOM = 0x2F0F0100ull;
+
+static const uint64_t P9N2_PERV_EC15_PPM_GPMMR_SCOM1 = 0x2F0F0101ull;
+
+static const uint64_t P9N2_PERV_EC15_PPM_GPMMR_SCOM2 = 0x2F0F0102ull;
+
+static const uint64_t P9N2_PERV_EC16_PPM_GPMMR_SCOM = 0x300F0100ull;
+
+static const uint64_t P9N2_PERV_EC16_PPM_GPMMR_SCOM1 = 0x300F0101ull;
+
+static const uint64_t P9N2_PERV_EC16_PPM_GPMMR_SCOM2 = 0x300F0102ull;
+
+static const uint64_t P9N2_PERV_EC17_PPM_GPMMR_SCOM = 0x310F0100ull;
+
+static const uint64_t P9N2_PERV_EC17_PPM_GPMMR_SCOM1 = 0x310F0101ull;
+
+static const uint64_t P9N2_PERV_EC17_PPM_GPMMR_SCOM2 = 0x310F0102ull;
+
+static const uint64_t P9N2_PERV_EC18_PPM_GPMMR_SCOM = 0x320F0100ull;
+
+static const uint64_t P9N2_PERV_EC18_PPM_GPMMR_SCOM1 = 0x320F0101ull;
+
+static const uint64_t P9N2_PERV_EC18_PPM_GPMMR_SCOM2 = 0x320F0102ull;
+
+static const uint64_t P9N2_PERV_EC19_PPM_GPMMR_SCOM = 0x330F0100ull;
+
+static const uint64_t P9N2_PERV_EC19_PPM_GPMMR_SCOM1 = 0x330F0101ull;
+
+static const uint64_t P9N2_PERV_EC19_PPM_GPMMR_SCOM2 = 0x330F0102ull;
+
+static const uint64_t P9N2_PERV_EC20_PPM_GPMMR_SCOM = 0x340F0100ull;
+
+static const uint64_t P9N2_PERV_EC20_PPM_GPMMR_SCOM1 = 0x340F0101ull;
+
+static const uint64_t P9N2_PERV_EC20_PPM_GPMMR_SCOM2 = 0x340F0102ull;
+
+static const uint64_t P9N2_PERV_EC21_PPM_GPMMR_SCOM = 0x350F0100ull;
+
+static const uint64_t P9N2_PERV_EC21_PPM_GPMMR_SCOM1 = 0x350F0101ull;
+
+static const uint64_t P9N2_PERV_EC21_PPM_GPMMR_SCOM2 = 0x350F0102ull;
+
+static const uint64_t P9N2_PERV_EC22_PPM_GPMMR_SCOM = 0x360F0100ull;
+
+static const uint64_t P9N2_PERV_EC22_PPM_GPMMR_SCOM1 = 0x360F0101ull;
+
+static const uint64_t P9N2_PERV_EC22_PPM_GPMMR_SCOM2 = 0x360F0102ull;
+
+static const uint64_t P9N2_PERV_EC23_PPM_GPMMR_SCOM = 0x370F0100ull;
+
+static const uint64_t P9N2_PERV_EC23_PPM_GPMMR_SCOM1 = 0x370F0101ull;
+
+static const uint64_t P9N2_PERV_EC23_PPM_GPMMR_SCOM2 = 0x370F0102ull;
+
+
+static const uint64_t P9N2_PERV_EP00_PPM_IVRMAVR = 0x100F01B5ull;
+
+static const uint64_t P9N2_PERV_EP01_PPM_IVRMAVR = 0x110F01B5ull;
+
+static const uint64_t P9N2_PERV_EP02_PPM_IVRMAVR = 0x120F01B5ull;
+
+static const uint64_t P9N2_PERV_EP03_PPM_IVRMAVR = 0x130F01B5ull;
+
+static const uint64_t P9N2_PERV_EP04_PPM_IVRMAVR = 0x140F01B5ull;
+
+static const uint64_t P9N2_PERV_EP05_PPM_IVRMAVR = 0x150F01B5ull;
+
+static const uint64_t P9N2_PERV_EC00_PPM_IVRMAVR = 0x200F01B5ull;
+
+static const uint64_t P9N2_PERV_EC01_PPM_IVRMAVR = 0x210F01B5ull;
+
+static const uint64_t P9N2_PERV_EC02_PPM_IVRMAVR = 0x220F01B5ull;
+
+static const uint64_t P9N2_PERV_EC03_PPM_IVRMAVR = 0x230F01B5ull;
+
+static const uint64_t P9N2_PERV_EC04_PPM_IVRMAVR = 0x240F01B5ull;
+
+static const uint64_t P9N2_PERV_EC05_PPM_IVRMAVR = 0x250F01B5ull;
+
+static const uint64_t P9N2_PERV_EC06_PPM_IVRMAVR = 0x260F01B5ull;
+
+static const uint64_t P9N2_PERV_EC07_PPM_IVRMAVR = 0x270F01B5ull;
+
+static const uint64_t P9N2_PERV_EC08_PPM_IVRMAVR = 0x280F01B5ull;
+
+static const uint64_t P9N2_PERV_EC09_PPM_IVRMAVR = 0x290F01B5ull;
+
+static const uint64_t P9N2_PERV_EC10_PPM_IVRMAVR = 0x2A0F01B5ull;
+
+static const uint64_t P9N2_PERV_EC11_PPM_IVRMAVR = 0x2B0F01B5ull;
+
+static const uint64_t P9N2_PERV_EC12_PPM_IVRMAVR = 0x2C0F01B5ull;
+
+static const uint64_t P9N2_PERV_EC13_PPM_IVRMAVR = 0x2D0F01B5ull;
+
+static const uint64_t P9N2_PERV_EC14_PPM_IVRMAVR = 0x2E0F01B5ull;
+
+static const uint64_t P9N2_PERV_EC15_PPM_IVRMAVR = 0x2F0F01B5ull;
+
+static const uint64_t P9N2_PERV_EC16_PPM_IVRMAVR = 0x300F01B5ull;
+
+static const uint64_t P9N2_PERV_EC17_PPM_IVRMAVR = 0x310F01B5ull;
+
+static const uint64_t P9N2_PERV_EC18_PPM_IVRMAVR = 0x320F01B5ull;
+
+static const uint64_t P9N2_PERV_EC19_PPM_IVRMAVR = 0x330F01B5ull;
+
+static const uint64_t P9N2_PERV_EC20_PPM_IVRMAVR = 0x340F01B5ull;
+
+static const uint64_t P9N2_PERV_EC21_PPM_IVRMAVR = 0x350F01B5ull;
+
+static const uint64_t P9N2_PERV_EC22_PPM_IVRMAVR = 0x360F01B5ull;
+
+static const uint64_t P9N2_PERV_EC23_PPM_IVRMAVR = 0x370F01B5ull;
+
+
+static const uint64_t P9N2_PERV_EP00_PPM_IVRMCR = 0x100F01B0ull;
+
+static const uint64_t P9N2_PERV_EP00_PPM_IVRMCR_CLEAR = 0x100F01B1ull;
+
+static const uint64_t P9N2_PERV_EP00_PPM_IVRMCR_OR = 0x100F01B2ull;
+
+static const uint64_t P9N2_PERV_EP01_PPM_IVRMCR = 0x110F01B0ull;
+
+static const uint64_t P9N2_PERV_EP01_PPM_IVRMCR_CLEAR = 0x110F01B1ull;
+
+static const uint64_t P9N2_PERV_EP01_PPM_IVRMCR_OR = 0x110F01B2ull;
+
+static const uint64_t P9N2_PERV_EP02_PPM_IVRMCR = 0x120F01B0ull;
+
+static const uint64_t P9N2_PERV_EP02_PPM_IVRMCR_CLEAR = 0x120F01B1ull;
+
+static const uint64_t P9N2_PERV_EP02_PPM_IVRMCR_OR = 0x120F01B2ull;
+
+static const uint64_t P9N2_PERV_EP03_PPM_IVRMCR = 0x130F01B0ull;
+
+static const uint64_t P9N2_PERV_EP03_PPM_IVRMCR_CLEAR = 0x130F01B1ull;
+
+static const uint64_t P9N2_PERV_EP03_PPM_IVRMCR_OR = 0x130F01B2ull;
+
+static const uint64_t P9N2_PERV_EP04_PPM_IVRMCR = 0x140F01B0ull;
+
+static const uint64_t P9N2_PERV_EP04_PPM_IVRMCR_CLEAR = 0x140F01B1ull;
+
+static const uint64_t P9N2_PERV_EP04_PPM_IVRMCR_OR = 0x140F01B2ull;
+
+static const uint64_t P9N2_PERV_EP05_PPM_IVRMCR = 0x150F01B0ull;
+
+static const uint64_t P9N2_PERV_EP05_PPM_IVRMCR_CLEAR = 0x150F01B1ull;
+
+static const uint64_t P9N2_PERV_EP05_PPM_IVRMCR_OR = 0x150F01B2ull;
+
+static const uint64_t P9N2_PERV_EC00_PPM_IVRMCR = 0x200F01B0ull;
+
+static const uint64_t P9N2_PERV_EC00_PPM_IVRMCR_CLEAR = 0x200F01B1ull;
+
+static const uint64_t P9N2_PERV_EC00_PPM_IVRMCR_OR = 0x200F01B2ull;
+
+static const uint64_t P9N2_PERV_EC01_PPM_IVRMCR = 0x210F01B0ull;
+
+static const uint64_t P9N2_PERV_EC01_PPM_IVRMCR_CLEAR = 0x210F01B1ull;
+
+static const uint64_t P9N2_PERV_EC01_PPM_IVRMCR_OR = 0x210F01B2ull;
+
+static const uint64_t P9N2_PERV_EC02_PPM_IVRMCR = 0x220F01B0ull;
+
+static const uint64_t P9N2_PERV_EC02_PPM_IVRMCR_CLEAR = 0x220F01B1ull;
+
+static const uint64_t P9N2_PERV_EC02_PPM_IVRMCR_OR = 0x220F01B2ull;
+
+static const uint64_t P9N2_PERV_EC03_PPM_IVRMCR = 0x230F01B0ull;
+
+static const uint64_t P9N2_PERV_EC03_PPM_IVRMCR_CLEAR = 0x230F01B1ull;
+
+static const uint64_t P9N2_PERV_EC03_PPM_IVRMCR_OR = 0x230F01B2ull;
+
+static const uint64_t P9N2_PERV_EC04_PPM_IVRMCR = 0x240F01B0ull;
+
+static const uint64_t P9N2_PERV_EC04_PPM_IVRMCR_CLEAR = 0x240F01B1ull;
+
+static const uint64_t P9N2_PERV_EC04_PPM_IVRMCR_OR = 0x240F01B2ull;
+
+static const uint64_t P9N2_PERV_EC05_PPM_IVRMCR = 0x250F01B0ull;
+
+static const uint64_t P9N2_PERV_EC05_PPM_IVRMCR_CLEAR = 0x250F01B1ull;
+
+static const uint64_t P9N2_PERV_EC05_PPM_IVRMCR_OR = 0x250F01B2ull;
+
+static const uint64_t P9N2_PERV_EC06_PPM_IVRMCR = 0x260F01B0ull;
+
+static const uint64_t P9N2_PERV_EC06_PPM_IVRMCR_CLEAR = 0x260F01B1ull;
+
+static const uint64_t P9N2_PERV_EC06_PPM_IVRMCR_OR = 0x260F01B2ull;
+
+static const uint64_t P9N2_PERV_EC07_PPM_IVRMCR = 0x270F01B0ull;
+
+static const uint64_t P9N2_PERV_EC07_PPM_IVRMCR_CLEAR = 0x270F01B1ull;
+
+static const uint64_t P9N2_PERV_EC07_PPM_IVRMCR_OR = 0x270F01B2ull;
+
+static const uint64_t P9N2_PERV_EC08_PPM_IVRMCR = 0x280F01B0ull;
+
+static const uint64_t P9N2_PERV_EC08_PPM_IVRMCR_CLEAR = 0x280F01B1ull;
+
+static const uint64_t P9N2_PERV_EC08_PPM_IVRMCR_OR = 0x280F01B2ull;
+
+static const uint64_t P9N2_PERV_EC09_PPM_IVRMCR = 0x290F01B0ull;
+
+static const uint64_t P9N2_PERV_EC09_PPM_IVRMCR_CLEAR = 0x290F01B1ull;
+
+static const uint64_t P9N2_PERV_EC09_PPM_IVRMCR_OR = 0x290F01B2ull;
+
+static const uint64_t P9N2_PERV_EC10_PPM_IVRMCR = 0x2A0F01B0ull;
+
+static const uint64_t P9N2_PERV_EC10_PPM_IVRMCR_CLEAR = 0x2A0F01B1ull;
+
+static const uint64_t P9N2_PERV_EC10_PPM_IVRMCR_OR = 0x2A0F01B2ull;
+
+static const uint64_t P9N2_PERV_EC11_PPM_IVRMCR = 0x2B0F01B0ull;
+
+static const uint64_t P9N2_PERV_EC11_PPM_IVRMCR_CLEAR = 0x2B0F01B1ull;
+
+static const uint64_t P9N2_PERV_EC11_PPM_IVRMCR_OR = 0x2B0F01B2ull;
+
+static const uint64_t P9N2_PERV_EC12_PPM_IVRMCR = 0x2C0F01B0ull;
+
+static const uint64_t P9N2_PERV_EC12_PPM_IVRMCR_CLEAR = 0x2C0F01B1ull;
+
+static const uint64_t P9N2_PERV_EC12_PPM_IVRMCR_OR = 0x2C0F01B2ull;
+
+static const uint64_t P9N2_PERV_EC13_PPM_IVRMCR = 0x2D0F01B0ull;
+
+static const uint64_t P9N2_PERV_EC13_PPM_IVRMCR_CLEAR = 0x2D0F01B1ull;
+
+static const uint64_t P9N2_PERV_EC13_PPM_IVRMCR_OR = 0x2D0F01B2ull;
+
+static const uint64_t P9N2_PERV_EC14_PPM_IVRMCR = 0x2E0F01B0ull;
+
+static const uint64_t P9N2_PERV_EC14_PPM_IVRMCR_CLEAR = 0x2E0F01B1ull;
+
+static const uint64_t P9N2_PERV_EC14_PPM_IVRMCR_OR = 0x2E0F01B2ull;
+
+static const uint64_t P9N2_PERV_EC15_PPM_IVRMCR = 0x2F0F01B0ull;
+
+static const uint64_t P9N2_PERV_EC15_PPM_IVRMCR_CLEAR = 0x2F0F01B1ull;
+
+static const uint64_t P9N2_PERV_EC15_PPM_IVRMCR_OR = 0x2F0F01B2ull;
+
+static const uint64_t P9N2_PERV_EC16_PPM_IVRMCR = 0x300F01B0ull;
+
+static const uint64_t P9N2_PERV_EC16_PPM_IVRMCR_CLEAR = 0x300F01B1ull;
+
+static const uint64_t P9N2_PERV_EC16_PPM_IVRMCR_OR = 0x300F01B2ull;
+
+static const uint64_t P9N2_PERV_EC17_PPM_IVRMCR = 0x310F01B0ull;
+
+static const uint64_t P9N2_PERV_EC17_PPM_IVRMCR_CLEAR = 0x310F01B1ull;
+
+static const uint64_t P9N2_PERV_EC17_PPM_IVRMCR_OR = 0x310F01B2ull;
+
+static const uint64_t P9N2_PERV_EC18_PPM_IVRMCR = 0x320F01B0ull;
+
+static const uint64_t P9N2_PERV_EC18_PPM_IVRMCR_CLEAR = 0x320F01B1ull;
+
+static const uint64_t P9N2_PERV_EC18_PPM_IVRMCR_OR = 0x320F01B2ull;
+
+static const uint64_t P9N2_PERV_EC19_PPM_IVRMCR = 0x330F01B0ull;
+
+static const uint64_t P9N2_PERV_EC19_PPM_IVRMCR_CLEAR = 0x330F01B1ull;
+
+static const uint64_t P9N2_PERV_EC19_PPM_IVRMCR_OR = 0x330F01B2ull;
+
+static const uint64_t P9N2_PERV_EC20_PPM_IVRMCR = 0x340F01B0ull;
+
+static const uint64_t P9N2_PERV_EC20_PPM_IVRMCR_CLEAR = 0x340F01B1ull;
+
+static const uint64_t P9N2_PERV_EC20_PPM_IVRMCR_OR = 0x340F01B2ull;
+
+static const uint64_t P9N2_PERV_EC21_PPM_IVRMCR = 0x350F01B0ull;
+
+static const uint64_t P9N2_PERV_EC21_PPM_IVRMCR_CLEAR = 0x350F01B1ull;
+
+static const uint64_t P9N2_PERV_EC21_PPM_IVRMCR_OR = 0x350F01B2ull;
+
+static const uint64_t P9N2_PERV_EC22_PPM_IVRMCR = 0x360F01B0ull;
+
+static const uint64_t P9N2_PERV_EC22_PPM_IVRMCR_CLEAR = 0x360F01B1ull;
+
+static const uint64_t P9N2_PERV_EC22_PPM_IVRMCR_OR = 0x360F01B2ull;
+
+static const uint64_t P9N2_PERV_EC23_PPM_IVRMCR = 0x370F01B0ull;
+
+static const uint64_t P9N2_PERV_EC23_PPM_IVRMCR_CLEAR = 0x370F01B1ull;
+
+static const uint64_t P9N2_PERV_EC23_PPM_IVRMCR_OR = 0x370F01B2ull;
+
+
+static const uint64_t P9N2_PERV_EP00_PPM_IVRMDVR = 0x100F01B4ull;
+
+static const uint64_t P9N2_PERV_EP01_PPM_IVRMDVR = 0x110F01B4ull;
+
+static const uint64_t P9N2_PERV_EP02_PPM_IVRMDVR = 0x120F01B4ull;
+
+static const uint64_t P9N2_PERV_EP03_PPM_IVRMDVR = 0x130F01B4ull;
+
+static const uint64_t P9N2_PERV_EP04_PPM_IVRMDVR = 0x140F01B4ull;
+
+static const uint64_t P9N2_PERV_EP05_PPM_IVRMDVR = 0x150F01B4ull;
+
+static const uint64_t P9N2_PERV_EC00_PPM_IVRMDVR = 0x200F01B4ull;
+
+static const uint64_t P9N2_PERV_EC01_PPM_IVRMDVR = 0x210F01B4ull;
+
+static const uint64_t P9N2_PERV_EC02_PPM_IVRMDVR = 0x220F01B4ull;
+
+static const uint64_t P9N2_PERV_EC03_PPM_IVRMDVR = 0x230F01B4ull;
+
+static const uint64_t P9N2_PERV_EC04_PPM_IVRMDVR = 0x240F01B4ull;
+
+static const uint64_t P9N2_PERV_EC05_PPM_IVRMDVR = 0x250F01B4ull;
+
+static const uint64_t P9N2_PERV_EC06_PPM_IVRMDVR = 0x260F01B4ull;
+
+static const uint64_t P9N2_PERV_EC07_PPM_IVRMDVR = 0x270F01B4ull;
+
+static const uint64_t P9N2_PERV_EC08_PPM_IVRMDVR = 0x280F01B4ull;
+
+static const uint64_t P9N2_PERV_EC09_PPM_IVRMDVR = 0x290F01B4ull;
+
+static const uint64_t P9N2_PERV_EC10_PPM_IVRMDVR = 0x2A0F01B4ull;
+
+static const uint64_t P9N2_PERV_EC11_PPM_IVRMDVR = 0x2B0F01B4ull;
+
+static const uint64_t P9N2_PERV_EC12_PPM_IVRMDVR = 0x2C0F01B4ull;
+
+static const uint64_t P9N2_PERV_EC13_PPM_IVRMDVR = 0x2D0F01B4ull;
+
+static const uint64_t P9N2_PERV_EC14_PPM_IVRMDVR = 0x2E0F01B4ull;
+
+static const uint64_t P9N2_PERV_EC15_PPM_IVRMDVR = 0x2F0F01B4ull;
+
+static const uint64_t P9N2_PERV_EC16_PPM_IVRMDVR = 0x300F01B4ull;
+
+static const uint64_t P9N2_PERV_EC17_PPM_IVRMDVR = 0x310F01B4ull;
+
+static const uint64_t P9N2_PERV_EC18_PPM_IVRMDVR = 0x320F01B4ull;
+
+static const uint64_t P9N2_PERV_EC19_PPM_IVRMDVR = 0x330F01B4ull;
+
+static const uint64_t P9N2_PERV_EC20_PPM_IVRMDVR = 0x340F01B4ull;
+
+static const uint64_t P9N2_PERV_EC21_PPM_IVRMDVR = 0x350F01B4ull;
+
+static const uint64_t P9N2_PERV_EC22_PPM_IVRMDVR = 0x360F01B4ull;
+
+static const uint64_t P9N2_PERV_EC23_PPM_IVRMDVR = 0x370F01B4ull;
+
+
+static const uint64_t P9N2_PERV_EP00_PPM_IVRMST = 0x100F01B3ull;
+
+static const uint64_t P9N2_PERV_EP01_PPM_IVRMST = 0x110F01B3ull;
+
+static const uint64_t P9N2_PERV_EP02_PPM_IVRMST = 0x120F01B3ull;
+
+static const uint64_t P9N2_PERV_EP03_PPM_IVRMST = 0x130F01B3ull;
+
+static const uint64_t P9N2_PERV_EP04_PPM_IVRMST = 0x140F01B3ull;
+
+static const uint64_t P9N2_PERV_EP05_PPM_IVRMST = 0x150F01B3ull;
+
+static const uint64_t P9N2_PERV_EC00_PPM_IVRMST = 0x200F01B3ull;
+
+static const uint64_t P9N2_PERV_EC01_PPM_IVRMST = 0x210F01B3ull;
+
+static const uint64_t P9N2_PERV_EC02_PPM_IVRMST = 0x220F01B3ull;
+
+static const uint64_t P9N2_PERV_EC03_PPM_IVRMST = 0x230F01B3ull;
+
+static const uint64_t P9N2_PERV_EC04_PPM_IVRMST = 0x240F01B3ull;
+
+static const uint64_t P9N2_PERV_EC05_PPM_IVRMST = 0x250F01B3ull;
+
+static const uint64_t P9N2_PERV_EC06_PPM_IVRMST = 0x260F01B3ull;
+
+static const uint64_t P9N2_PERV_EC07_PPM_IVRMST = 0x270F01B3ull;
+
+static const uint64_t P9N2_PERV_EC08_PPM_IVRMST = 0x280F01B3ull;
+
+static const uint64_t P9N2_PERV_EC09_PPM_IVRMST = 0x290F01B3ull;
+
+static const uint64_t P9N2_PERV_EC10_PPM_IVRMST = 0x2A0F01B3ull;
+
+static const uint64_t P9N2_PERV_EC11_PPM_IVRMST = 0x2B0F01B3ull;
+
+static const uint64_t P9N2_PERV_EC12_PPM_IVRMST = 0x2C0F01B3ull;
+
+static const uint64_t P9N2_PERV_EC13_PPM_IVRMST = 0x2D0F01B3ull;
+
+static const uint64_t P9N2_PERV_EC14_PPM_IVRMST = 0x2E0F01B3ull;
+
+static const uint64_t P9N2_PERV_EC15_PPM_IVRMST = 0x2F0F01B3ull;
+
+static const uint64_t P9N2_PERV_EC16_PPM_IVRMST = 0x300F01B3ull;
+
+static const uint64_t P9N2_PERV_EC17_PPM_IVRMST = 0x310F01B3ull;
+
+static const uint64_t P9N2_PERV_EC18_PPM_IVRMST = 0x320F01B3ull;
+
+static const uint64_t P9N2_PERV_EC19_PPM_IVRMST = 0x330F01B3ull;
+
+static const uint64_t P9N2_PERV_EC20_PPM_IVRMST = 0x340F01B3ull;
+
+static const uint64_t P9N2_PERV_EC21_PPM_IVRMST = 0x350F01B3ull;
+
+static const uint64_t P9N2_PERV_EC22_PPM_IVRMST = 0x360F01B3ull;
+
+static const uint64_t P9N2_PERV_EC23_PPM_IVRMST = 0x370F01B3ull;
+
+
+static const uint64_t P9N2_PERV_EP00_PPM_PFCS_SCOM = 0x100F0118ull;
+
+static const uint64_t P9N2_PERV_EP00_PPM_PFCS_SCOM1 = 0x100F0119ull;
+
+static const uint64_t P9N2_PERV_EP00_PPM_PFCS_SCOM2 = 0x100F011Aull;
+
+static const uint64_t P9N2_PERV_EP01_PPM_PFCS_SCOM = 0x110F0118ull;
+
+static const uint64_t P9N2_PERV_EP01_PPM_PFCS_SCOM1 = 0x110F0119ull;
+
+static const uint64_t P9N2_PERV_EP01_PPM_PFCS_SCOM2 = 0x110F011Aull;
+
+static const uint64_t P9N2_PERV_EP02_PPM_PFCS_SCOM = 0x120F0118ull;
+
+static const uint64_t P9N2_PERV_EP02_PPM_PFCS_SCOM1 = 0x120F0119ull;
+
+static const uint64_t P9N2_PERV_EP02_PPM_PFCS_SCOM2 = 0x120F011Aull;
+
+static const uint64_t P9N2_PERV_EP03_PPM_PFCS_SCOM = 0x130F0118ull;
+
+static const uint64_t P9N2_PERV_EP03_PPM_PFCS_SCOM1 = 0x130F0119ull;
+
+static const uint64_t P9N2_PERV_EP03_PPM_PFCS_SCOM2 = 0x130F011Aull;
+
+static const uint64_t P9N2_PERV_EP04_PPM_PFCS_SCOM = 0x140F0118ull;
+
+static const uint64_t P9N2_PERV_EP04_PPM_PFCS_SCOM1 = 0x140F0119ull;
+
+static const uint64_t P9N2_PERV_EP04_PPM_PFCS_SCOM2 = 0x140F011Aull;
+
+static const uint64_t P9N2_PERV_EP05_PPM_PFCS_SCOM = 0x150F0118ull;
+
+static const uint64_t P9N2_PERV_EP05_PPM_PFCS_SCOM1 = 0x150F0119ull;
+
+static const uint64_t P9N2_PERV_EP05_PPM_PFCS_SCOM2 = 0x150F011Aull;
+
+static const uint64_t P9N2_PERV_EC00_PPM_PFCS_SCOM = 0x200F0118ull;
+
+static const uint64_t P9N2_PERV_EC00_PPM_PFCS_SCOM1 = 0x200F0119ull;
+
+static const uint64_t P9N2_PERV_EC00_PPM_PFCS_SCOM2 = 0x200F011Aull;
+
+static const uint64_t P9N2_PERV_EC01_PPM_PFCS_SCOM = 0x210F0118ull;
+
+static const uint64_t P9N2_PERV_EC01_PPM_PFCS_SCOM1 = 0x210F0119ull;
+
+static const uint64_t P9N2_PERV_EC01_PPM_PFCS_SCOM2 = 0x210F011Aull;
+
+static const uint64_t P9N2_PERV_EC02_PPM_PFCS_SCOM = 0x220F0118ull;
+
+static const uint64_t P9N2_PERV_EC02_PPM_PFCS_SCOM1 = 0x220F0119ull;
+
+static const uint64_t P9N2_PERV_EC02_PPM_PFCS_SCOM2 = 0x220F011Aull;
+
+static const uint64_t P9N2_PERV_EC03_PPM_PFCS_SCOM = 0x230F0118ull;
+
+static const uint64_t P9N2_PERV_EC03_PPM_PFCS_SCOM1 = 0x230F0119ull;
+
+static const uint64_t P9N2_PERV_EC03_PPM_PFCS_SCOM2 = 0x230F011Aull;
+
+static const uint64_t P9N2_PERV_EC04_PPM_PFCS_SCOM = 0x240F0118ull;
+
+static const uint64_t P9N2_PERV_EC04_PPM_PFCS_SCOM1 = 0x240F0119ull;
+
+static const uint64_t P9N2_PERV_EC04_PPM_PFCS_SCOM2 = 0x240F011Aull;
+
+static const uint64_t P9N2_PERV_EC05_PPM_PFCS_SCOM = 0x250F0118ull;
+
+static const uint64_t P9N2_PERV_EC05_PPM_PFCS_SCOM1 = 0x250F0119ull;
+
+static const uint64_t P9N2_PERV_EC05_PPM_PFCS_SCOM2 = 0x250F011Aull;
+
+static const uint64_t P9N2_PERV_EC06_PPM_PFCS_SCOM = 0x260F0118ull;
+
+static const uint64_t P9N2_PERV_EC06_PPM_PFCS_SCOM1 = 0x260F0119ull;
+
+static const uint64_t P9N2_PERV_EC06_PPM_PFCS_SCOM2 = 0x260F011Aull;
+
+static const uint64_t P9N2_PERV_EC07_PPM_PFCS_SCOM = 0x270F0118ull;
+
+static const uint64_t P9N2_PERV_EC07_PPM_PFCS_SCOM1 = 0x270F0119ull;
+
+static const uint64_t P9N2_PERV_EC07_PPM_PFCS_SCOM2 = 0x270F011Aull;
+
+static const uint64_t P9N2_PERV_EC08_PPM_PFCS_SCOM = 0x280F0118ull;
+
+static const uint64_t P9N2_PERV_EC08_PPM_PFCS_SCOM1 = 0x280F0119ull;
+
+static const uint64_t P9N2_PERV_EC08_PPM_PFCS_SCOM2 = 0x280F011Aull;
+
+static const uint64_t P9N2_PERV_EC09_PPM_PFCS_SCOM = 0x290F0118ull;
+
+static const uint64_t P9N2_PERV_EC09_PPM_PFCS_SCOM1 = 0x290F0119ull;
+
+static const uint64_t P9N2_PERV_EC09_PPM_PFCS_SCOM2 = 0x290F011Aull;
+
+static const uint64_t P9N2_PERV_EC10_PPM_PFCS_SCOM = 0x2A0F0118ull;
+
+static const uint64_t P9N2_PERV_EC10_PPM_PFCS_SCOM1 = 0x2A0F0119ull;
+
+static const uint64_t P9N2_PERV_EC10_PPM_PFCS_SCOM2 = 0x2A0F011Aull;
+
+static const uint64_t P9N2_PERV_EC11_PPM_PFCS_SCOM = 0x2B0F0118ull;
+
+static const uint64_t P9N2_PERV_EC11_PPM_PFCS_SCOM1 = 0x2B0F0119ull;
+
+static const uint64_t P9N2_PERV_EC11_PPM_PFCS_SCOM2 = 0x2B0F011Aull;
+
+static const uint64_t P9N2_PERV_EC12_PPM_PFCS_SCOM = 0x2C0F0118ull;
+
+static const uint64_t P9N2_PERV_EC12_PPM_PFCS_SCOM1 = 0x2C0F0119ull;
+
+static const uint64_t P9N2_PERV_EC12_PPM_PFCS_SCOM2 = 0x2C0F011Aull;
+
+static const uint64_t P9N2_PERV_EC13_PPM_PFCS_SCOM = 0x2D0F0118ull;
+
+static const uint64_t P9N2_PERV_EC13_PPM_PFCS_SCOM1 = 0x2D0F0119ull;
+
+static const uint64_t P9N2_PERV_EC13_PPM_PFCS_SCOM2 = 0x2D0F011Aull;
+
+static const uint64_t P9N2_PERV_EC14_PPM_PFCS_SCOM = 0x2E0F0118ull;
+
+static const uint64_t P9N2_PERV_EC14_PPM_PFCS_SCOM1 = 0x2E0F0119ull;
+
+static const uint64_t P9N2_PERV_EC14_PPM_PFCS_SCOM2 = 0x2E0F011Aull;
+
+static const uint64_t P9N2_PERV_EC15_PPM_PFCS_SCOM = 0x2F0F0118ull;
+
+static const uint64_t P9N2_PERV_EC15_PPM_PFCS_SCOM1 = 0x2F0F0119ull;
+
+static const uint64_t P9N2_PERV_EC15_PPM_PFCS_SCOM2 = 0x2F0F011Aull;
+
+static const uint64_t P9N2_PERV_EC16_PPM_PFCS_SCOM = 0x300F0118ull;
+
+static const uint64_t P9N2_PERV_EC16_PPM_PFCS_SCOM1 = 0x300F0119ull;
+
+static const uint64_t P9N2_PERV_EC16_PPM_PFCS_SCOM2 = 0x300F011Aull;
+
+static const uint64_t P9N2_PERV_EC17_PPM_PFCS_SCOM = 0x310F0118ull;
+
+static const uint64_t P9N2_PERV_EC17_PPM_PFCS_SCOM1 = 0x310F0119ull;
+
+static const uint64_t P9N2_PERV_EC17_PPM_PFCS_SCOM2 = 0x310F011Aull;
+
+static const uint64_t P9N2_PERV_EC18_PPM_PFCS_SCOM = 0x320F0118ull;
+
+static const uint64_t P9N2_PERV_EC18_PPM_PFCS_SCOM1 = 0x320F0119ull;
+
+static const uint64_t P9N2_PERV_EC18_PPM_PFCS_SCOM2 = 0x320F011Aull;
+
+static const uint64_t P9N2_PERV_EC19_PPM_PFCS_SCOM = 0x330F0118ull;
+
+static const uint64_t P9N2_PERV_EC19_PPM_PFCS_SCOM1 = 0x330F0119ull;
+
+static const uint64_t P9N2_PERV_EC19_PPM_PFCS_SCOM2 = 0x330F011Aull;
+
+static const uint64_t P9N2_PERV_EC20_PPM_PFCS_SCOM = 0x340F0118ull;
+
+static const uint64_t P9N2_PERV_EC20_PPM_PFCS_SCOM1 = 0x340F0119ull;
+
+static const uint64_t P9N2_PERV_EC20_PPM_PFCS_SCOM2 = 0x340F011Aull;
+
+static const uint64_t P9N2_PERV_EC21_PPM_PFCS_SCOM = 0x350F0118ull;
+
+static const uint64_t P9N2_PERV_EC21_PPM_PFCS_SCOM1 = 0x350F0119ull;
+
+static const uint64_t P9N2_PERV_EC21_PPM_PFCS_SCOM2 = 0x350F011Aull;
+
+static const uint64_t P9N2_PERV_EC22_PPM_PFCS_SCOM = 0x360F0118ull;
+
+static const uint64_t P9N2_PERV_EC22_PPM_PFCS_SCOM1 = 0x360F0119ull;
+
+static const uint64_t P9N2_PERV_EC22_PPM_PFCS_SCOM2 = 0x360F011Aull;
+
+static const uint64_t P9N2_PERV_EC23_PPM_PFCS_SCOM = 0x370F0118ull;
+
+static const uint64_t P9N2_PERV_EC23_PPM_PFCS_SCOM1 = 0x370F0119ull;
+
+static const uint64_t P9N2_PERV_EC23_PPM_PFCS_SCOM2 = 0x370F011Aull;
+
+
+static const uint64_t P9N2_PERV_EP00_PPM_PFDLY = 0x100F011Bull;
+
+static const uint64_t P9N2_PERV_EP01_PPM_PFDLY = 0x110F011Bull;
+
+static const uint64_t P9N2_PERV_EP02_PPM_PFDLY = 0x120F011Bull;
+
+static const uint64_t P9N2_PERV_EP03_PPM_PFDLY = 0x130F011Bull;
+
+static const uint64_t P9N2_PERV_EP04_PPM_PFDLY = 0x140F011Bull;
+
+static const uint64_t P9N2_PERV_EP05_PPM_PFDLY = 0x150F011Bull;
+
+static const uint64_t P9N2_PERV_EC00_PPM_PFDLY = 0x200F011Bull;
+
+static const uint64_t P9N2_PERV_EC01_PPM_PFDLY = 0x210F011Bull;
+
+static const uint64_t P9N2_PERV_EC02_PPM_PFDLY = 0x220F011Bull;
+
+static const uint64_t P9N2_PERV_EC03_PPM_PFDLY = 0x230F011Bull;
+
+static const uint64_t P9N2_PERV_EC04_PPM_PFDLY = 0x240F011Bull;
+
+static const uint64_t P9N2_PERV_EC05_PPM_PFDLY = 0x250F011Bull;
+
+static const uint64_t P9N2_PERV_EC06_PPM_PFDLY = 0x260F011Bull;
+
+static const uint64_t P9N2_PERV_EC07_PPM_PFDLY = 0x270F011Bull;
+
+static const uint64_t P9N2_PERV_EC08_PPM_PFDLY = 0x280F011Bull;
+
+static const uint64_t P9N2_PERV_EC09_PPM_PFDLY = 0x290F011Bull;
+
+static const uint64_t P9N2_PERV_EC10_PPM_PFDLY = 0x2A0F011Bull;
+
+static const uint64_t P9N2_PERV_EC11_PPM_PFDLY = 0x2B0F011Bull;
+
+static const uint64_t P9N2_PERV_EC12_PPM_PFDLY = 0x2C0F011Bull;
+
+static const uint64_t P9N2_PERV_EC13_PPM_PFDLY = 0x2D0F011Bull;
+
+static const uint64_t P9N2_PERV_EC14_PPM_PFDLY = 0x2E0F011Bull;
+
+static const uint64_t P9N2_PERV_EC15_PPM_PFDLY = 0x2F0F011Bull;
+
+static const uint64_t P9N2_PERV_EC16_PPM_PFDLY = 0x300F011Bull;
+
+static const uint64_t P9N2_PERV_EC17_PPM_PFDLY = 0x310F011Bull;
+
+static const uint64_t P9N2_PERV_EC18_PPM_PFDLY = 0x320F011Bull;
+
+static const uint64_t P9N2_PERV_EC19_PPM_PFDLY = 0x330F011Bull;
+
+static const uint64_t P9N2_PERV_EC20_PPM_PFDLY = 0x340F011Bull;
+
+static const uint64_t P9N2_PERV_EC21_PPM_PFDLY = 0x350F011Bull;
+
+static const uint64_t P9N2_PERV_EC22_PPM_PFDLY = 0x360F011Bull;
+
+static const uint64_t P9N2_PERV_EC23_PPM_PFDLY = 0x370F011Bull;
+
+
+static const uint64_t P9N2_PERV_EP00_PPM_PFOFF = 0x100F011Dull;
+
+static const uint64_t P9N2_PERV_EP01_PPM_PFOFF = 0x110F011Dull;
+
+static const uint64_t P9N2_PERV_EP02_PPM_PFOFF = 0x120F011Dull;
+
+static const uint64_t P9N2_PERV_EP03_PPM_PFOFF = 0x130F011Dull;
+
+static const uint64_t P9N2_PERV_EP04_PPM_PFOFF = 0x140F011Dull;
+
+static const uint64_t P9N2_PERV_EP05_PPM_PFOFF = 0x150F011Dull;
+
+static const uint64_t P9N2_PERV_EC00_PPM_PFOFF = 0x200F011Dull;
+
+static const uint64_t P9N2_PERV_EC01_PPM_PFOFF = 0x210F011Dull;
+
+static const uint64_t P9N2_PERV_EC02_PPM_PFOFF = 0x220F011Dull;
+
+static const uint64_t P9N2_PERV_EC03_PPM_PFOFF = 0x230F011Dull;
+
+static const uint64_t P9N2_PERV_EC04_PPM_PFOFF = 0x240F011Dull;
+
+static const uint64_t P9N2_PERV_EC05_PPM_PFOFF = 0x250F011Dull;
+
+static const uint64_t P9N2_PERV_EC06_PPM_PFOFF = 0x260F011Dull;
+
+static const uint64_t P9N2_PERV_EC07_PPM_PFOFF = 0x270F011Dull;
+
+static const uint64_t P9N2_PERV_EC08_PPM_PFOFF = 0x280F011Dull;
+
+static const uint64_t P9N2_PERV_EC09_PPM_PFOFF = 0x290F011Dull;
+
+static const uint64_t P9N2_PERV_EC10_PPM_PFOFF = 0x2A0F011Dull;
+
+static const uint64_t P9N2_PERV_EC11_PPM_PFOFF = 0x2B0F011Dull;
+
+static const uint64_t P9N2_PERV_EC12_PPM_PFOFF = 0x2C0F011Dull;
+
+static const uint64_t P9N2_PERV_EC13_PPM_PFOFF = 0x2D0F011Dull;
+
+static const uint64_t P9N2_PERV_EC14_PPM_PFOFF = 0x2E0F011Dull;
+
+static const uint64_t P9N2_PERV_EC15_PPM_PFOFF = 0x2F0F011Dull;
+
+static const uint64_t P9N2_PERV_EC16_PPM_PFOFF = 0x300F011Dull;
+
+static const uint64_t P9N2_PERV_EC17_PPM_PFOFF = 0x310F011Dull;
+
+static const uint64_t P9N2_PERV_EC18_PPM_PFOFF = 0x320F011Dull;
+
+static const uint64_t P9N2_PERV_EC19_PPM_PFOFF = 0x330F011Dull;
+
+static const uint64_t P9N2_PERV_EC20_PPM_PFOFF = 0x340F011Dull;
+
+static const uint64_t P9N2_PERV_EC21_PPM_PFOFF = 0x350F011Dull;
+
+static const uint64_t P9N2_PERV_EC22_PPM_PFOFF = 0x360F011Dull;
+
+static const uint64_t P9N2_PERV_EC23_PPM_PFOFF = 0x370F011Dull;
+
+
+static const uint64_t P9N2_PERV_EP00_PPM_PFSNS = 0x100F011Cull;
+
+static const uint64_t P9N2_PERV_EP01_PPM_PFSNS = 0x110F011Cull;
+
+static const uint64_t P9N2_PERV_EP02_PPM_PFSNS = 0x120F011Cull;
+
+static const uint64_t P9N2_PERV_EP03_PPM_PFSNS = 0x130F011Cull;
+
+static const uint64_t P9N2_PERV_EP04_PPM_PFSNS = 0x140F011Cull;
+
+static const uint64_t P9N2_PERV_EP05_PPM_PFSNS = 0x150F011Cull;
+
+static const uint64_t P9N2_PERV_EC00_PPM_PFSNS = 0x200F011Cull;
+
+static const uint64_t P9N2_PERV_EC01_PPM_PFSNS = 0x210F011Cull;
+
+static const uint64_t P9N2_PERV_EC02_PPM_PFSNS = 0x220F011Cull;
+
+static const uint64_t P9N2_PERV_EC03_PPM_PFSNS = 0x230F011Cull;
+
+static const uint64_t P9N2_PERV_EC04_PPM_PFSNS = 0x240F011Cull;
+
+static const uint64_t P9N2_PERV_EC05_PPM_PFSNS = 0x250F011Cull;
+
+static const uint64_t P9N2_PERV_EC06_PPM_PFSNS = 0x260F011Cull;
+
+static const uint64_t P9N2_PERV_EC07_PPM_PFSNS = 0x270F011Cull;
+
+static const uint64_t P9N2_PERV_EC08_PPM_PFSNS = 0x280F011Cull;
+
+static const uint64_t P9N2_PERV_EC09_PPM_PFSNS = 0x290F011Cull;
+
+static const uint64_t P9N2_PERV_EC10_PPM_PFSNS = 0x2A0F011Cull;
+
+static const uint64_t P9N2_PERV_EC11_PPM_PFSNS = 0x2B0F011Cull;
+
+static const uint64_t P9N2_PERV_EC12_PPM_PFSNS = 0x2C0F011Cull;
+
+static const uint64_t P9N2_PERV_EC13_PPM_PFSNS = 0x2D0F011Cull;
+
+static const uint64_t P9N2_PERV_EC14_PPM_PFSNS = 0x2E0F011Cull;
+
+static const uint64_t P9N2_PERV_EC15_PPM_PFSNS = 0x2F0F011Cull;
+
+static const uint64_t P9N2_PERV_EC16_PPM_PFSNS = 0x300F011Cull;
+
+static const uint64_t P9N2_PERV_EC17_PPM_PFSNS = 0x310F011Cull;
+
+static const uint64_t P9N2_PERV_EC18_PPM_PFSNS = 0x320F011Cull;
+
+static const uint64_t P9N2_PERV_EC19_PPM_PFSNS = 0x330F011Cull;
+
+static const uint64_t P9N2_PERV_EC20_PPM_PFSNS = 0x340F011Cull;
+
+static const uint64_t P9N2_PERV_EC21_PPM_PFSNS = 0x350F011Cull;
+
+static const uint64_t P9N2_PERV_EC22_PPM_PFSNS = 0x360F011Cull;
+
+static const uint64_t P9N2_PERV_EC23_PPM_PFSNS = 0x370F011Cull;
+
+
+static const uint64_t P9N2_PERV_EP00_PPM_PIG = 0x100F0180ull;
+
+static const uint64_t P9N2_PERV_EP01_PPM_PIG = 0x110F0180ull;
+
+static const uint64_t P9N2_PERV_EP02_PPM_PIG = 0x120F0180ull;
+
+static const uint64_t P9N2_PERV_EP03_PPM_PIG = 0x130F0180ull;
+
+static const uint64_t P9N2_PERV_EP04_PPM_PIG = 0x140F0180ull;
+
+static const uint64_t P9N2_PERV_EP05_PPM_PIG = 0x150F0180ull;
+
+static const uint64_t P9N2_PERV_EC00_PPM_PIG = 0x200F0180ull;
+
+static const uint64_t P9N2_PERV_EC01_PPM_PIG = 0x210F0180ull;
+
+static const uint64_t P9N2_PERV_EC02_PPM_PIG = 0x220F0180ull;
+
+static const uint64_t P9N2_PERV_EC03_PPM_PIG = 0x230F0180ull;
+
+static const uint64_t P9N2_PERV_EC04_PPM_PIG = 0x240F0180ull;
+
+static const uint64_t P9N2_PERV_EC05_PPM_PIG = 0x250F0180ull;
+
+static const uint64_t P9N2_PERV_EC06_PPM_PIG = 0x260F0180ull;
+
+static const uint64_t P9N2_PERV_EC07_PPM_PIG = 0x270F0180ull;
+
+static const uint64_t P9N2_PERV_EC08_PPM_PIG = 0x280F0180ull;
+
+static const uint64_t P9N2_PERV_EC09_PPM_PIG = 0x290F0180ull;
+
+static const uint64_t P9N2_PERV_EC10_PPM_PIG = 0x2A0F0180ull;
+
+static const uint64_t P9N2_PERV_EC11_PPM_PIG = 0x2B0F0180ull;
+
+static const uint64_t P9N2_PERV_EC12_PPM_PIG = 0x2C0F0180ull;
+
+static const uint64_t P9N2_PERV_EC13_PPM_PIG = 0x2D0F0180ull;
+
+static const uint64_t P9N2_PERV_EC14_PPM_PIG = 0x2E0F0180ull;
+
+static const uint64_t P9N2_PERV_EC15_PPM_PIG = 0x2F0F0180ull;
+
+static const uint64_t P9N2_PERV_EC16_PPM_PIG = 0x300F0180ull;
+
+static const uint64_t P9N2_PERV_EC17_PPM_PIG = 0x310F0180ull;
+
+static const uint64_t P9N2_PERV_EC18_PPM_PIG = 0x320F0180ull;
+
+static const uint64_t P9N2_PERV_EC19_PPM_PIG = 0x330F0180ull;
+
+static const uint64_t P9N2_PERV_EC20_PPM_PIG = 0x340F0180ull;
+
+static const uint64_t P9N2_PERV_EC21_PPM_PIG = 0x350F0180ull;
+
+static const uint64_t P9N2_PERV_EC22_PPM_PIG = 0x360F0180ull;
+
+static const uint64_t P9N2_PERV_EC23_PPM_PIG = 0x370F0180ull;
+
+
+static const uint64_t P9N2_PERV_EP00_PPM_SCRATCH0 = 0x100F011Eull;
+
+static const uint64_t P9N2_PERV_EP01_PPM_SCRATCH0 = 0x110F011Eull;
+
+static const uint64_t P9N2_PERV_EP02_PPM_SCRATCH0 = 0x120F011Eull;
+
+static const uint64_t P9N2_PERV_EP03_PPM_SCRATCH0 = 0x130F011Eull;
+
+static const uint64_t P9N2_PERV_EP04_PPM_SCRATCH0 = 0x140F011Eull;
+
+static const uint64_t P9N2_PERV_EP05_PPM_SCRATCH0 = 0x150F011Eull;
+
+static const uint64_t P9N2_PERV_EC00_PPM_SCRATCH0 = 0x200F011Eull;
+
+static const uint64_t P9N2_PERV_EC01_PPM_SCRATCH0 = 0x210F011Eull;
+
+static const uint64_t P9N2_PERV_EC02_PPM_SCRATCH0 = 0x220F011Eull;
+
+static const uint64_t P9N2_PERV_EC03_PPM_SCRATCH0 = 0x230F011Eull;
+
+static const uint64_t P9N2_PERV_EC04_PPM_SCRATCH0 = 0x240F011Eull;
+
+static const uint64_t P9N2_PERV_EC05_PPM_SCRATCH0 = 0x250F011Eull;
+
+static const uint64_t P9N2_PERV_EC06_PPM_SCRATCH0 = 0x260F011Eull;
+
+static const uint64_t P9N2_PERV_EC07_PPM_SCRATCH0 = 0x270F011Eull;
+
+static const uint64_t P9N2_PERV_EC08_PPM_SCRATCH0 = 0x280F011Eull;
+
+static const uint64_t P9N2_PERV_EC09_PPM_SCRATCH0 = 0x290F011Eull;
+
+static const uint64_t P9N2_PERV_EC10_PPM_SCRATCH0 = 0x2A0F011Eull;
+
+static const uint64_t P9N2_PERV_EC11_PPM_SCRATCH0 = 0x2B0F011Eull;
+
+static const uint64_t P9N2_PERV_EC12_PPM_SCRATCH0 = 0x2C0F011Eull;
+
+static const uint64_t P9N2_PERV_EC13_PPM_SCRATCH0 = 0x2D0F011Eull;
+
+static const uint64_t P9N2_PERV_EC14_PPM_SCRATCH0 = 0x2E0F011Eull;
+
+static const uint64_t P9N2_PERV_EC15_PPM_SCRATCH0 = 0x2F0F011Eull;
+
+static const uint64_t P9N2_PERV_EC16_PPM_SCRATCH0 = 0x300F011Eull;
+
+static const uint64_t P9N2_PERV_EC17_PPM_SCRATCH0 = 0x310F011Eull;
+
+static const uint64_t P9N2_PERV_EC18_PPM_SCRATCH0 = 0x320F011Eull;
+
+static const uint64_t P9N2_PERV_EC19_PPM_SCRATCH0 = 0x330F011Eull;
+
+static const uint64_t P9N2_PERV_EC20_PPM_SCRATCH0 = 0x340F011Eull;
+
+static const uint64_t P9N2_PERV_EC21_PPM_SCRATCH0 = 0x350F011Eull;
+
+static const uint64_t P9N2_PERV_EC22_PPM_SCRATCH0 = 0x360F011Eull;
+
+static const uint64_t P9N2_PERV_EC23_PPM_SCRATCH0 = 0x370F011Eull;
+
+
+static const uint64_t P9N2_PERV_EP00_PPM_SCRATCH1 = 0x100F011Full;
+
+static const uint64_t P9N2_PERV_EP01_PPM_SCRATCH1 = 0x110F011Full;
+
+static const uint64_t P9N2_PERV_EP02_PPM_SCRATCH1 = 0x120F011Full;
+
+static const uint64_t P9N2_PERV_EP03_PPM_SCRATCH1 = 0x130F011Full;
+
+static const uint64_t P9N2_PERV_EP04_PPM_SCRATCH1 = 0x140F011Full;
+
+static const uint64_t P9N2_PERV_EP05_PPM_SCRATCH1 = 0x150F011Full;
+
+static const uint64_t P9N2_PERV_EC00_PPM_SCRATCH1 = 0x200F011Full;
+
+static const uint64_t P9N2_PERV_EC01_PPM_SCRATCH1 = 0x210F011Full;
+
+static const uint64_t P9N2_PERV_EC02_PPM_SCRATCH1 = 0x220F011Full;
+
+static const uint64_t P9N2_PERV_EC03_PPM_SCRATCH1 = 0x230F011Full;
+
+static const uint64_t P9N2_PERV_EC04_PPM_SCRATCH1 = 0x240F011Full;
+
+static const uint64_t P9N2_PERV_EC05_PPM_SCRATCH1 = 0x250F011Full;
+
+static const uint64_t P9N2_PERV_EC06_PPM_SCRATCH1 = 0x260F011Full;
+
+static const uint64_t P9N2_PERV_EC07_PPM_SCRATCH1 = 0x270F011Full;
+
+static const uint64_t P9N2_PERV_EC08_PPM_SCRATCH1 = 0x280F011Full;
+
+static const uint64_t P9N2_PERV_EC09_PPM_SCRATCH1 = 0x290F011Full;
+
+static const uint64_t P9N2_PERV_EC10_PPM_SCRATCH1 = 0x2A0F011Full;
+
+static const uint64_t P9N2_PERV_EC11_PPM_SCRATCH1 = 0x2B0F011Full;
+
+static const uint64_t P9N2_PERV_EC12_PPM_SCRATCH1 = 0x2C0F011Full;
+
+static const uint64_t P9N2_PERV_EC13_PPM_SCRATCH1 = 0x2D0F011Full;
+
+static const uint64_t P9N2_PERV_EC14_PPM_SCRATCH1 = 0x2E0F011Full;
+
+static const uint64_t P9N2_PERV_EC15_PPM_SCRATCH1 = 0x2F0F011Full;
+
+static const uint64_t P9N2_PERV_EC16_PPM_SCRATCH1 = 0x300F011Full;
+
+static const uint64_t P9N2_PERV_EC17_PPM_SCRATCH1 = 0x310F011Full;
+
+static const uint64_t P9N2_PERV_EC18_PPM_SCRATCH1 = 0x320F011Full;
+
+static const uint64_t P9N2_PERV_EC19_PPM_SCRATCH1 = 0x330F011Full;
+
+static const uint64_t P9N2_PERV_EC20_PPM_SCRATCH1 = 0x340F011Full;
+
+static const uint64_t P9N2_PERV_EC21_PPM_SCRATCH1 = 0x350F011Full;
+
+static const uint64_t P9N2_PERV_EC22_PPM_SCRATCH1 = 0x360F011Full;
+
+static const uint64_t P9N2_PERV_EC23_PPM_SCRATCH1 = 0x370F011Full;
+
+
+static const uint64_t P9N2_PERV_EP00_PPM_SPWKUP_FSP = 0x100F010Bull;
+
+static const uint64_t P9N2_PERV_EP01_PPM_SPWKUP_FSP = 0x110F010Bull;
+
+static const uint64_t P9N2_PERV_EP02_PPM_SPWKUP_FSP = 0x120F010Bull;
+
+static const uint64_t P9N2_PERV_EP03_PPM_SPWKUP_FSP = 0x130F010Bull;
+
+static const uint64_t P9N2_PERV_EP04_PPM_SPWKUP_FSP = 0x140F010Bull;
+
+static const uint64_t P9N2_PERV_EP05_PPM_SPWKUP_FSP = 0x150F010Bull;
+
+static const uint64_t P9N2_PERV_EC00_PPM_SPWKUP_FSP = 0x200F010Bull;
+
+static const uint64_t P9N2_PERV_EC01_PPM_SPWKUP_FSP = 0x210F010Bull;
+
+static const uint64_t P9N2_PERV_EC02_PPM_SPWKUP_FSP = 0x220F010Bull;
+
+static const uint64_t P9N2_PERV_EC03_PPM_SPWKUP_FSP = 0x230F010Bull;
+
+static const uint64_t P9N2_PERV_EC04_PPM_SPWKUP_FSP = 0x240F010Bull;
+
+static const uint64_t P9N2_PERV_EC05_PPM_SPWKUP_FSP = 0x250F010Bull;
+
+static const uint64_t P9N2_PERV_EC06_PPM_SPWKUP_FSP = 0x260F010Bull;
+
+static const uint64_t P9N2_PERV_EC07_PPM_SPWKUP_FSP = 0x270F010Bull;
+
+static const uint64_t P9N2_PERV_EC08_PPM_SPWKUP_FSP = 0x280F010Bull;
+
+static const uint64_t P9N2_PERV_EC09_PPM_SPWKUP_FSP = 0x290F010Bull;
+
+static const uint64_t P9N2_PERV_EC10_PPM_SPWKUP_FSP = 0x2A0F010Bull;
+
+static const uint64_t P9N2_PERV_EC11_PPM_SPWKUP_FSP = 0x2B0F010Bull;
+
+static const uint64_t P9N2_PERV_EC12_PPM_SPWKUP_FSP = 0x2C0F010Bull;
+
+static const uint64_t P9N2_PERV_EC13_PPM_SPWKUP_FSP = 0x2D0F010Bull;
+
+static const uint64_t P9N2_PERV_EC14_PPM_SPWKUP_FSP = 0x2E0F010Bull;
+
+static const uint64_t P9N2_PERV_EC15_PPM_SPWKUP_FSP = 0x2F0F010Bull;
+
+static const uint64_t P9N2_PERV_EC16_PPM_SPWKUP_FSP = 0x300F010Bull;
+
+static const uint64_t P9N2_PERV_EC17_PPM_SPWKUP_FSP = 0x310F010Bull;
+
+static const uint64_t P9N2_PERV_EC18_PPM_SPWKUP_FSP = 0x320F010Bull;
+
+static const uint64_t P9N2_PERV_EC19_PPM_SPWKUP_FSP = 0x330F010Bull;
+
+static const uint64_t P9N2_PERV_EC20_PPM_SPWKUP_FSP = 0x340F010Bull;
+
+static const uint64_t P9N2_PERV_EC21_PPM_SPWKUP_FSP = 0x350F010Bull;
+
+static const uint64_t P9N2_PERV_EC22_PPM_SPWKUP_FSP = 0x360F010Bull;
+
+static const uint64_t P9N2_PERV_EC23_PPM_SPWKUP_FSP = 0x370F010Bull;
+
+
+static const uint64_t P9N2_PERV_EP00_PPM_SPWKUP_HYP = 0x100F010Dull;
+
+static const uint64_t P9N2_PERV_EP01_PPM_SPWKUP_HYP = 0x110F010Dull;
+
+static const uint64_t P9N2_PERV_EP02_PPM_SPWKUP_HYP = 0x120F010Dull;
+
+static const uint64_t P9N2_PERV_EP03_PPM_SPWKUP_HYP = 0x130F010Dull;
+
+static const uint64_t P9N2_PERV_EP04_PPM_SPWKUP_HYP = 0x140F010Dull;
+
+static const uint64_t P9N2_PERV_EP05_PPM_SPWKUP_HYP = 0x150F010Dull;
+
+static const uint64_t P9N2_PERV_EC00_PPM_SPWKUP_HYP = 0x200F010Dull;
+
+static const uint64_t P9N2_PERV_EC01_PPM_SPWKUP_HYP = 0x210F010Dull;
+
+static const uint64_t P9N2_PERV_EC02_PPM_SPWKUP_HYP = 0x220F010Dull;
+
+static const uint64_t P9N2_PERV_EC03_PPM_SPWKUP_HYP = 0x230F010Dull;
+
+static const uint64_t P9N2_PERV_EC04_PPM_SPWKUP_HYP = 0x240F010Dull;
+
+static const uint64_t P9N2_PERV_EC05_PPM_SPWKUP_HYP = 0x250F010Dull;
+
+static const uint64_t P9N2_PERV_EC06_PPM_SPWKUP_HYP = 0x260F010Dull;
+
+static const uint64_t P9N2_PERV_EC07_PPM_SPWKUP_HYP = 0x270F010Dull;
+
+static const uint64_t P9N2_PERV_EC08_PPM_SPWKUP_HYP = 0x280F010Dull;
+
+static const uint64_t P9N2_PERV_EC09_PPM_SPWKUP_HYP = 0x290F010Dull;
+
+static const uint64_t P9N2_PERV_EC10_PPM_SPWKUP_HYP = 0x2A0F010Dull;
+
+static const uint64_t P9N2_PERV_EC11_PPM_SPWKUP_HYP = 0x2B0F010Dull;
+
+static const uint64_t P9N2_PERV_EC12_PPM_SPWKUP_HYP = 0x2C0F010Dull;
+
+static const uint64_t P9N2_PERV_EC13_PPM_SPWKUP_HYP = 0x2D0F010Dull;
+
+static const uint64_t P9N2_PERV_EC14_PPM_SPWKUP_HYP = 0x2E0F010Dull;
+
+static const uint64_t P9N2_PERV_EC15_PPM_SPWKUP_HYP = 0x2F0F010Dull;
+
+static const uint64_t P9N2_PERV_EC16_PPM_SPWKUP_HYP = 0x300F010Dull;
+
+static const uint64_t P9N2_PERV_EC17_PPM_SPWKUP_HYP = 0x310F010Dull;
+
+static const uint64_t P9N2_PERV_EC18_PPM_SPWKUP_HYP = 0x320F010Dull;
+
+static const uint64_t P9N2_PERV_EC19_PPM_SPWKUP_HYP = 0x330F010Dull;
+
+static const uint64_t P9N2_PERV_EC20_PPM_SPWKUP_HYP = 0x340F010Dull;
+
+static const uint64_t P9N2_PERV_EC21_PPM_SPWKUP_HYP = 0x350F010Dull;
+
+static const uint64_t P9N2_PERV_EC22_PPM_SPWKUP_HYP = 0x360F010Dull;
+
+static const uint64_t P9N2_PERV_EC23_PPM_SPWKUP_HYP = 0x370F010Dull;
+
+
+static const uint64_t P9N2_PERV_EP00_PPM_SPWKUP_OCC = 0x100F010Cull;
+
+static const uint64_t P9N2_PERV_EP01_PPM_SPWKUP_OCC = 0x110F010Cull;
+
+static const uint64_t P9N2_PERV_EP02_PPM_SPWKUP_OCC = 0x120F010Cull;
+
+static const uint64_t P9N2_PERV_EP03_PPM_SPWKUP_OCC = 0x130F010Cull;
+
+static const uint64_t P9N2_PERV_EP04_PPM_SPWKUP_OCC = 0x140F010Cull;
+
+static const uint64_t P9N2_PERV_EP05_PPM_SPWKUP_OCC = 0x150F010Cull;
+
+static const uint64_t P9N2_PERV_EC00_PPM_SPWKUP_OCC = 0x200F010Cull;
+
+static const uint64_t P9N2_PERV_EC01_PPM_SPWKUP_OCC = 0x210F010Cull;
+
+static const uint64_t P9N2_PERV_EC02_PPM_SPWKUP_OCC = 0x220F010Cull;
+
+static const uint64_t P9N2_PERV_EC03_PPM_SPWKUP_OCC = 0x230F010Cull;
+
+static const uint64_t P9N2_PERV_EC04_PPM_SPWKUP_OCC = 0x240F010Cull;
+
+static const uint64_t P9N2_PERV_EC05_PPM_SPWKUP_OCC = 0x250F010Cull;
+
+static const uint64_t P9N2_PERV_EC06_PPM_SPWKUP_OCC = 0x260F010Cull;
+
+static const uint64_t P9N2_PERV_EC07_PPM_SPWKUP_OCC = 0x270F010Cull;
+
+static const uint64_t P9N2_PERV_EC08_PPM_SPWKUP_OCC = 0x280F010Cull;
+
+static const uint64_t P9N2_PERV_EC09_PPM_SPWKUP_OCC = 0x290F010Cull;
+
+static const uint64_t P9N2_PERV_EC10_PPM_SPWKUP_OCC = 0x2A0F010Cull;
+
+static const uint64_t P9N2_PERV_EC11_PPM_SPWKUP_OCC = 0x2B0F010Cull;
+
+static const uint64_t P9N2_PERV_EC12_PPM_SPWKUP_OCC = 0x2C0F010Cull;
+
+static const uint64_t P9N2_PERV_EC13_PPM_SPWKUP_OCC = 0x2D0F010Cull;
+
+static const uint64_t P9N2_PERV_EC14_PPM_SPWKUP_OCC = 0x2E0F010Cull;
+
+static const uint64_t P9N2_PERV_EC15_PPM_SPWKUP_OCC = 0x2F0F010Cull;
+
+static const uint64_t P9N2_PERV_EC16_PPM_SPWKUP_OCC = 0x300F010Cull;
+
+static const uint64_t P9N2_PERV_EC17_PPM_SPWKUP_OCC = 0x310F010Cull;
+
+static const uint64_t P9N2_PERV_EC18_PPM_SPWKUP_OCC = 0x320F010Cull;
+
+static const uint64_t P9N2_PERV_EC19_PPM_SPWKUP_OCC = 0x330F010Cull;
+
+static const uint64_t P9N2_PERV_EC20_PPM_SPWKUP_OCC = 0x340F010Cull;
+
+static const uint64_t P9N2_PERV_EC21_PPM_SPWKUP_OCC = 0x350F010Cull;
+
+static const uint64_t P9N2_PERV_EC22_PPM_SPWKUP_OCC = 0x360F010Cull;
+
+static const uint64_t P9N2_PERV_EC23_PPM_SPWKUP_OCC = 0x370F010Cull;
+
+
+static const uint64_t P9N2_PERV_EP00_PPM_SPWKUP_OTR = 0x100F010Aull;
+
+static const uint64_t P9N2_PERV_EP01_PPM_SPWKUP_OTR = 0x110F010Aull;
+
+static const uint64_t P9N2_PERV_EP02_PPM_SPWKUP_OTR = 0x120F010Aull;
+
+static const uint64_t P9N2_PERV_EP03_PPM_SPWKUP_OTR = 0x130F010Aull;
+
+static const uint64_t P9N2_PERV_EP04_PPM_SPWKUP_OTR = 0x140F010Aull;
+
+static const uint64_t P9N2_PERV_EP05_PPM_SPWKUP_OTR = 0x150F010Aull;
+
+static const uint64_t P9N2_PERV_EC00_PPM_SPWKUP_OTR = 0x200F010Aull;
+
+static const uint64_t P9N2_PERV_EC01_PPM_SPWKUP_OTR = 0x210F010Aull;
+
+static const uint64_t P9N2_PERV_EC02_PPM_SPWKUP_OTR = 0x220F010Aull;
+
+static const uint64_t P9N2_PERV_EC03_PPM_SPWKUP_OTR = 0x230F010Aull;
+
+static const uint64_t P9N2_PERV_EC04_PPM_SPWKUP_OTR = 0x240F010Aull;
+
+static const uint64_t P9N2_PERV_EC05_PPM_SPWKUP_OTR = 0x250F010Aull;
+
+static const uint64_t P9N2_PERV_EC06_PPM_SPWKUP_OTR = 0x260F010Aull;
+
+static const uint64_t P9N2_PERV_EC07_PPM_SPWKUP_OTR = 0x270F010Aull;
+
+static const uint64_t P9N2_PERV_EC08_PPM_SPWKUP_OTR = 0x280F010Aull;
+
+static const uint64_t P9N2_PERV_EC09_PPM_SPWKUP_OTR = 0x290F010Aull;
+
+static const uint64_t P9N2_PERV_EC10_PPM_SPWKUP_OTR = 0x2A0F010Aull;
+
+static const uint64_t P9N2_PERV_EC11_PPM_SPWKUP_OTR = 0x2B0F010Aull;
+
+static const uint64_t P9N2_PERV_EC12_PPM_SPWKUP_OTR = 0x2C0F010Aull;
+
+static const uint64_t P9N2_PERV_EC13_PPM_SPWKUP_OTR = 0x2D0F010Aull;
+
+static const uint64_t P9N2_PERV_EC14_PPM_SPWKUP_OTR = 0x2E0F010Aull;
+
+static const uint64_t P9N2_PERV_EC15_PPM_SPWKUP_OTR = 0x2F0F010Aull;
+
+static const uint64_t P9N2_PERV_EC16_PPM_SPWKUP_OTR = 0x300F010Aull;
+
+static const uint64_t P9N2_PERV_EC17_PPM_SPWKUP_OTR = 0x310F010Aull;
+
+static const uint64_t P9N2_PERV_EC18_PPM_SPWKUP_OTR = 0x320F010Aull;
+
+static const uint64_t P9N2_PERV_EC19_PPM_SPWKUP_OTR = 0x330F010Aull;
+
+static const uint64_t P9N2_PERV_EC20_PPM_SPWKUP_OTR = 0x340F010Aull;
+
+static const uint64_t P9N2_PERV_EC21_PPM_SPWKUP_OTR = 0x350F010Aull;
+
+static const uint64_t P9N2_PERV_EC22_PPM_SPWKUP_OTR = 0x360F010Aull;
+
+static const uint64_t P9N2_PERV_EC23_PPM_SPWKUP_OTR = 0x370F010Aull;
+
+
+static const uint64_t P9N2_PERV_EP00_PPM_SSHFSP = 0x100F0111ull;
+
+static const uint64_t P9N2_PERV_EP01_PPM_SSHFSP = 0x110F0111ull;
+
+static const uint64_t P9N2_PERV_EP02_PPM_SSHFSP = 0x120F0111ull;
+
+static const uint64_t P9N2_PERV_EP03_PPM_SSHFSP = 0x130F0111ull;
+
+static const uint64_t P9N2_PERV_EP04_PPM_SSHFSP = 0x140F0111ull;
+
+static const uint64_t P9N2_PERV_EP05_PPM_SSHFSP = 0x150F0111ull;
+
+static const uint64_t P9N2_PERV_EC00_PPM_SSHFSP = 0x200F0111ull;
+
+static const uint64_t P9N2_PERV_EC01_PPM_SSHFSP = 0x210F0111ull;
+
+static const uint64_t P9N2_PERV_EC02_PPM_SSHFSP = 0x220F0111ull;
+
+static const uint64_t P9N2_PERV_EC03_PPM_SSHFSP = 0x230F0111ull;
+
+static const uint64_t P9N2_PERV_EC04_PPM_SSHFSP = 0x240F0111ull;
+
+static const uint64_t P9N2_PERV_EC05_PPM_SSHFSP = 0x250F0111ull;
+
+static const uint64_t P9N2_PERV_EC06_PPM_SSHFSP = 0x260F0111ull;
+
+static const uint64_t P9N2_PERV_EC07_PPM_SSHFSP = 0x270F0111ull;
+
+static const uint64_t P9N2_PERV_EC08_PPM_SSHFSP = 0x280F0111ull;
+
+static const uint64_t P9N2_PERV_EC09_PPM_SSHFSP = 0x290F0111ull;
+
+static const uint64_t P9N2_PERV_EC10_PPM_SSHFSP = 0x2A0F0111ull;
+
+static const uint64_t P9N2_PERV_EC11_PPM_SSHFSP = 0x2B0F0111ull;
+
+static const uint64_t P9N2_PERV_EC12_PPM_SSHFSP = 0x2C0F0111ull;
+
+static const uint64_t P9N2_PERV_EC13_PPM_SSHFSP = 0x2D0F0111ull;
+
+static const uint64_t P9N2_PERV_EC14_PPM_SSHFSP = 0x2E0F0111ull;
+
+static const uint64_t P9N2_PERV_EC15_PPM_SSHFSP = 0x2F0F0111ull;
+
+static const uint64_t P9N2_PERV_EC16_PPM_SSHFSP = 0x300F0111ull;
+
+static const uint64_t P9N2_PERV_EC17_PPM_SSHFSP = 0x310F0111ull;
+
+static const uint64_t P9N2_PERV_EC18_PPM_SSHFSP = 0x320F0111ull;
+
+static const uint64_t P9N2_PERV_EC19_PPM_SSHFSP = 0x330F0111ull;
+
+static const uint64_t P9N2_PERV_EC20_PPM_SSHFSP = 0x340F0111ull;
+
+static const uint64_t P9N2_PERV_EC21_PPM_SSHFSP = 0x350F0111ull;
+
+static const uint64_t P9N2_PERV_EC22_PPM_SSHFSP = 0x360F0111ull;
+
+static const uint64_t P9N2_PERV_EC23_PPM_SSHFSP = 0x370F0111ull;
+
+
+static const uint64_t P9N2_PERV_EP00_PPM_SSHHYP = 0x100F0114ull;
+
+static const uint64_t P9N2_PERV_EP01_PPM_SSHHYP = 0x110F0114ull;
+
+static const uint64_t P9N2_PERV_EP02_PPM_SSHHYP = 0x120F0114ull;
+
+static const uint64_t P9N2_PERV_EP03_PPM_SSHHYP = 0x130F0114ull;
+
+static const uint64_t P9N2_PERV_EP04_PPM_SSHHYP = 0x140F0114ull;
+
+static const uint64_t P9N2_PERV_EP05_PPM_SSHHYP = 0x150F0114ull;
+
+static const uint64_t P9N2_PERV_EC00_PPM_SSHHYP = 0x200F0114ull;
+
+static const uint64_t P9N2_PERV_EC01_PPM_SSHHYP = 0x210F0114ull;
+
+static const uint64_t P9N2_PERV_EC02_PPM_SSHHYP = 0x220F0114ull;
+
+static const uint64_t P9N2_PERV_EC03_PPM_SSHHYP = 0x230F0114ull;
+
+static const uint64_t P9N2_PERV_EC04_PPM_SSHHYP = 0x240F0114ull;
+
+static const uint64_t P9N2_PERV_EC05_PPM_SSHHYP = 0x250F0114ull;
+
+static const uint64_t P9N2_PERV_EC06_PPM_SSHHYP = 0x260F0114ull;
+
+static const uint64_t P9N2_PERV_EC07_PPM_SSHHYP = 0x270F0114ull;
+
+static const uint64_t P9N2_PERV_EC08_PPM_SSHHYP = 0x280F0114ull;
+
+static const uint64_t P9N2_PERV_EC09_PPM_SSHHYP = 0x290F0114ull;
+
+static const uint64_t P9N2_PERV_EC10_PPM_SSHHYP = 0x2A0F0114ull;
+
+static const uint64_t P9N2_PERV_EC11_PPM_SSHHYP = 0x2B0F0114ull;
+
+static const uint64_t P9N2_PERV_EC12_PPM_SSHHYP = 0x2C0F0114ull;
+
+static const uint64_t P9N2_PERV_EC13_PPM_SSHHYP = 0x2D0F0114ull;
+
+static const uint64_t P9N2_PERV_EC14_PPM_SSHHYP = 0x2E0F0114ull;
+
+static const uint64_t P9N2_PERV_EC15_PPM_SSHHYP = 0x2F0F0114ull;
+
+static const uint64_t P9N2_PERV_EC16_PPM_SSHHYP = 0x300F0114ull;
+
+static const uint64_t P9N2_PERV_EC17_PPM_SSHHYP = 0x310F0114ull;
+
+static const uint64_t P9N2_PERV_EC18_PPM_SSHHYP = 0x320F0114ull;
+
+static const uint64_t P9N2_PERV_EC19_PPM_SSHHYP = 0x330F0114ull;
+
+static const uint64_t P9N2_PERV_EC20_PPM_SSHHYP = 0x340F0114ull;
+
+static const uint64_t P9N2_PERV_EC21_PPM_SSHHYP = 0x350F0114ull;
+
+static const uint64_t P9N2_PERV_EC22_PPM_SSHHYP = 0x360F0114ull;
+
+static const uint64_t P9N2_PERV_EC23_PPM_SSHHYP = 0x370F0114ull;
+
+
+static const uint64_t P9N2_PERV_EP00_PPM_SSHOCC = 0x100F0112ull;
+
+static const uint64_t P9N2_PERV_EP01_PPM_SSHOCC = 0x110F0112ull;
+
+static const uint64_t P9N2_PERV_EP02_PPM_SSHOCC = 0x120F0112ull;
+
+static const uint64_t P9N2_PERV_EP03_PPM_SSHOCC = 0x130F0112ull;
+
+static const uint64_t P9N2_PERV_EP04_PPM_SSHOCC = 0x140F0112ull;
+
+static const uint64_t P9N2_PERV_EP05_PPM_SSHOCC = 0x150F0112ull;
+
+static const uint64_t P9N2_PERV_EC00_PPM_SSHOCC = 0x200F0112ull;
+
+static const uint64_t P9N2_PERV_EC01_PPM_SSHOCC = 0x210F0112ull;
+
+static const uint64_t P9N2_PERV_EC02_PPM_SSHOCC = 0x220F0112ull;
+
+static const uint64_t P9N2_PERV_EC03_PPM_SSHOCC = 0x230F0112ull;
+
+static const uint64_t P9N2_PERV_EC04_PPM_SSHOCC = 0x240F0112ull;
+
+static const uint64_t P9N2_PERV_EC05_PPM_SSHOCC = 0x250F0112ull;
+
+static const uint64_t P9N2_PERV_EC06_PPM_SSHOCC = 0x260F0112ull;
+
+static const uint64_t P9N2_PERV_EC07_PPM_SSHOCC = 0x270F0112ull;
+
+static const uint64_t P9N2_PERV_EC08_PPM_SSHOCC = 0x280F0112ull;
+
+static const uint64_t P9N2_PERV_EC09_PPM_SSHOCC = 0x290F0112ull;
+
+static const uint64_t P9N2_PERV_EC10_PPM_SSHOCC = 0x2A0F0112ull;
+
+static const uint64_t P9N2_PERV_EC11_PPM_SSHOCC = 0x2B0F0112ull;
+
+static const uint64_t P9N2_PERV_EC12_PPM_SSHOCC = 0x2C0F0112ull;
+
+static const uint64_t P9N2_PERV_EC13_PPM_SSHOCC = 0x2D0F0112ull;
+
+static const uint64_t P9N2_PERV_EC14_PPM_SSHOCC = 0x2E0F0112ull;
+
+static const uint64_t P9N2_PERV_EC15_PPM_SSHOCC = 0x2F0F0112ull;
+
+static const uint64_t P9N2_PERV_EC16_PPM_SSHOCC = 0x300F0112ull;
+
+static const uint64_t P9N2_PERV_EC17_PPM_SSHOCC = 0x310F0112ull;
+
+static const uint64_t P9N2_PERV_EC18_PPM_SSHOCC = 0x320F0112ull;
+
+static const uint64_t P9N2_PERV_EC19_PPM_SSHOCC = 0x330F0112ull;
+
+static const uint64_t P9N2_PERV_EC20_PPM_SSHOCC = 0x340F0112ull;
+
+static const uint64_t P9N2_PERV_EC21_PPM_SSHOCC = 0x350F0112ull;
+
+static const uint64_t P9N2_PERV_EC22_PPM_SSHOCC = 0x360F0112ull;
+
+static const uint64_t P9N2_PERV_EC23_PPM_SSHOCC = 0x370F0112ull;
+
+
+static const uint64_t P9N2_PERV_EP00_PPM_SSHOTR = 0x100F0113ull;
+
+static const uint64_t P9N2_PERV_EP01_PPM_SSHOTR = 0x110F0113ull;
+
+static const uint64_t P9N2_PERV_EP02_PPM_SSHOTR = 0x120F0113ull;
+
+static const uint64_t P9N2_PERV_EP03_PPM_SSHOTR = 0x130F0113ull;
+
+static const uint64_t P9N2_PERV_EP04_PPM_SSHOTR = 0x140F0113ull;
+
+static const uint64_t P9N2_PERV_EP05_PPM_SSHOTR = 0x150F0113ull;
+
+static const uint64_t P9N2_PERV_EC00_PPM_SSHOTR = 0x200F0113ull;
+
+static const uint64_t P9N2_PERV_EC01_PPM_SSHOTR = 0x210F0113ull;
+
+static const uint64_t P9N2_PERV_EC02_PPM_SSHOTR = 0x220F0113ull;
+
+static const uint64_t P9N2_PERV_EC03_PPM_SSHOTR = 0x230F0113ull;
+
+static const uint64_t P9N2_PERV_EC04_PPM_SSHOTR = 0x240F0113ull;
+
+static const uint64_t P9N2_PERV_EC05_PPM_SSHOTR = 0x250F0113ull;
+
+static const uint64_t P9N2_PERV_EC06_PPM_SSHOTR = 0x260F0113ull;
+
+static const uint64_t P9N2_PERV_EC07_PPM_SSHOTR = 0x270F0113ull;
+
+static const uint64_t P9N2_PERV_EC08_PPM_SSHOTR = 0x280F0113ull;
+
+static const uint64_t P9N2_PERV_EC09_PPM_SSHOTR = 0x290F0113ull;
+
+static const uint64_t P9N2_PERV_EC10_PPM_SSHOTR = 0x2A0F0113ull;
+
+static const uint64_t P9N2_PERV_EC11_PPM_SSHOTR = 0x2B0F0113ull;
+
+static const uint64_t P9N2_PERV_EC12_PPM_SSHOTR = 0x2C0F0113ull;
+
+static const uint64_t P9N2_PERV_EC13_PPM_SSHOTR = 0x2D0F0113ull;
+
+static const uint64_t P9N2_PERV_EC14_PPM_SSHOTR = 0x2E0F0113ull;
+
+static const uint64_t P9N2_PERV_EC15_PPM_SSHOTR = 0x2F0F0113ull;
+
+static const uint64_t P9N2_PERV_EC16_PPM_SSHOTR = 0x300F0113ull;
+
+static const uint64_t P9N2_PERV_EC17_PPM_SSHOTR = 0x310F0113ull;
+
+static const uint64_t P9N2_PERV_EC18_PPM_SSHOTR = 0x320F0113ull;
+
+static const uint64_t P9N2_PERV_EC19_PPM_SSHOTR = 0x330F0113ull;
+
+static const uint64_t P9N2_PERV_EC20_PPM_SSHOTR = 0x340F0113ull;
+
+static const uint64_t P9N2_PERV_EC21_PPM_SSHOTR = 0x350F0113ull;
+
+static const uint64_t P9N2_PERV_EC22_PPM_SSHOTR = 0x360F0113ull;
+
+static const uint64_t P9N2_PERV_EC23_PPM_SSHOTR = 0x370F0113ull;
+
+
+static const uint64_t P9N2_PERV_EP00_PPM_SSHSRC = 0x100F0110ull;
+
+static const uint64_t P9N2_PERV_EP01_PPM_SSHSRC = 0x110F0110ull;
+
+static const uint64_t P9N2_PERV_EP02_PPM_SSHSRC = 0x120F0110ull;
+
+static const uint64_t P9N2_PERV_EP03_PPM_SSHSRC = 0x130F0110ull;
+
+static const uint64_t P9N2_PERV_EP04_PPM_SSHSRC = 0x140F0110ull;
+
+static const uint64_t P9N2_PERV_EP05_PPM_SSHSRC = 0x150F0110ull;
+
+static const uint64_t P9N2_PERV_EC00_PPM_SSHSRC = 0x200F0110ull;
+
+static const uint64_t P9N2_PERV_EC01_PPM_SSHSRC = 0x210F0110ull;
+
+static const uint64_t P9N2_PERV_EC02_PPM_SSHSRC = 0x220F0110ull;
+
+static const uint64_t P9N2_PERV_EC03_PPM_SSHSRC = 0x230F0110ull;
+
+static const uint64_t P9N2_PERV_EC04_PPM_SSHSRC = 0x240F0110ull;
+
+static const uint64_t P9N2_PERV_EC05_PPM_SSHSRC = 0x250F0110ull;
+
+static const uint64_t P9N2_PERV_EC06_PPM_SSHSRC = 0x260F0110ull;
+
+static const uint64_t P9N2_PERV_EC07_PPM_SSHSRC = 0x270F0110ull;
+
+static const uint64_t P9N2_PERV_EC08_PPM_SSHSRC = 0x280F0110ull;
+
+static const uint64_t P9N2_PERV_EC09_PPM_SSHSRC = 0x290F0110ull;
+
+static const uint64_t P9N2_PERV_EC10_PPM_SSHSRC = 0x2A0F0110ull;
+
+static const uint64_t P9N2_PERV_EC11_PPM_SSHSRC = 0x2B0F0110ull;
+
+static const uint64_t P9N2_PERV_EC12_PPM_SSHSRC = 0x2C0F0110ull;
+
+static const uint64_t P9N2_PERV_EC13_PPM_SSHSRC = 0x2D0F0110ull;
+
+static const uint64_t P9N2_PERV_EC14_PPM_SSHSRC = 0x2E0F0110ull;
+
+static const uint64_t P9N2_PERV_EC15_PPM_SSHSRC = 0x2F0F0110ull;
+
+static const uint64_t P9N2_PERV_EC16_PPM_SSHSRC = 0x300F0110ull;
+
+static const uint64_t P9N2_PERV_EC17_PPM_SSHSRC = 0x310F0110ull;
+
+static const uint64_t P9N2_PERV_EC18_PPM_SSHSRC = 0x320F0110ull;
+
+static const uint64_t P9N2_PERV_EC19_PPM_SSHSRC = 0x330F0110ull;
+
+static const uint64_t P9N2_PERV_EC20_PPM_SSHSRC = 0x340F0110ull;
+
+static const uint64_t P9N2_PERV_EC21_PPM_SSHSRC = 0x350F0110ull;
+
+static const uint64_t P9N2_PERV_EC22_PPM_SSHSRC = 0x360F0110ull;
+
+static const uint64_t P9N2_PERV_EC23_PPM_SSHSRC = 0x370F0110ull;
+
+
+static const uint64_t P9N2_PERV_EP00_PPM_VDMCR = 0x100F01B8ull;
+
+static const uint64_t P9N2_PERV_EP00_PPM_VDMCR_CLEAR = 0x100F01B9ull;
+
+static const uint64_t P9N2_PERV_EP00_PPM_VDMCR_OR = 0x100F01BAull;
+
+static const uint64_t P9N2_PERV_EP01_PPM_VDMCR = 0x110F01B8ull;
+
+static const uint64_t P9N2_PERV_EP01_PPM_VDMCR_CLEAR = 0x110F01B9ull;
+
+static const uint64_t P9N2_PERV_EP01_PPM_VDMCR_OR = 0x110F01BAull;
+
+static const uint64_t P9N2_PERV_EP02_PPM_VDMCR = 0x120F01B8ull;
+
+static const uint64_t P9N2_PERV_EP02_PPM_VDMCR_CLEAR = 0x120F01B9ull;
+
+static const uint64_t P9N2_PERV_EP02_PPM_VDMCR_OR = 0x120F01BAull;
+
+static const uint64_t P9N2_PERV_EP03_PPM_VDMCR = 0x130F01B8ull;
+
+static const uint64_t P9N2_PERV_EP03_PPM_VDMCR_CLEAR = 0x130F01B9ull;
+
+static const uint64_t P9N2_PERV_EP03_PPM_VDMCR_OR = 0x130F01BAull;
+
+static const uint64_t P9N2_PERV_EP04_PPM_VDMCR = 0x140F01B8ull;
+
+static const uint64_t P9N2_PERV_EP04_PPM_VDMCR_CLEAR = 0x140F01B9ull;
+
+static const uint64_t P9N2_PERV_EP04_PPM_VDMCR_OR = 0x140F01BAull;
+
+static const uint64_t P9N2_PERV_EP05_PPM_VDMCR = 0x150F01B8ull;
+
+static const uint64_t P9N2_PERV_EP05_PPM_VDMCR_CLEAR = 0x150F01B9ull;
+
+static const uint64_t P9N2_PERV_EP05_PPM_VDMCR_OR = 0x150F01BAull;
+
+static const uint64_t P9N2_PERV_EC00_PPM_VDMCR = 0x200F01B8ull;
+
+static const uint64_t P9N2_PERV_EC00_PPM_VDMCR_CLEAR = 0x200F01B9ull;
+
+static const uint64_t P9N2_PERV_EC00_PPM_VDMCR_OR = 0x200F01BAull;
+
+static const uint64_t P9N2_PERV_EC01_PPM_VDMCR = 0x210F01B8ull;
+
+static const uint64_t P9N2_PERV_EC01_PPM_VDMCR_CLEAR = 0x210F01B9ull;
+
+static const uint64_t P9N2_PERV_EC01_PPM_VDMCR_OR = 0x210F01BAull;
+
+static const uint64_t P9N2_PERV_EC02_PPM_VDMCR = 0x220F01B8ull;
+
+static const uint64_t P9N2_PERV_EC02_PPM_VDMCR_CLEAR = 0x220F01B9ull;
+
+static const uint64_t P9N2_PERV_EC02_PPM_VDMCR_OR = 0x220F01BAull;
+
+static const uint64_t P9N2_PERV_EC03_PPM_VDMCR = 0x230F01B8ull;
+
+static const uint64_t P9N2_PERV_EC03_PPM_VDMCR_CLEAR = 0x230F01B9ull;
+
+static const uint64_t P9N2_PERV_EC03_PPM_VDMCR_OR = 0x230F01BAull;
+
+static const uint64_t P9N2_PERV_EC04_PPM_VDMCR = 0x240F01B8ull;
+
+static const uint64_t P9N2_PERV_EC04_PPM_VDMCR_CLEAR = 0x240F01B9ull;
+
+static const uint64_t P9N2_PERV_EC04_PPM_VDMCR_OR = 0x240F01BAull;
+
+static const uint64_t P9N2_PERV_EC05_PPM_VDMCR = 0x250F01B8ull;
+
+static const uint64_t P9N2_PERV_EC05_PPM_VDMCR_CLEAR = 0x250F01B9ull;
+
+static const uint64_t P9N2_PERV_EC05_PPM_VDMCR_OR = 0x250F01BAull;
+
+static const uint64_t P9N2_PERV_EC06_PPM_VDMCR = 0x260F01B8ull;
+
+static const uint64_t P9N2_PERV_EC06_PPM_VDMCR_CLEAR = 0x260F01B9ull;
+
+static const uint64_t P9N2_PERV_EC06_PPM_VDMCR_OR = 0x260F01BAull;
+
+static const uint64_t P9N2_PERV_EC07_PPM_VDMCR = 0x270F01B8ull;
+
+static const uint64_t P9N2_PERV_EC07_PPM_VDMCR_CLEAR = 0x270F01B9ull;
+
+static const uint64_t P9N2_PERV_EC07_PPM_VDMCR_OR = 0x270F01BAull;
+
+static const uint64_t P9N2_PERV_EC08_PPM_VDMCR = 0x280F01B8ull;
+
+static const uint64_t P9N2_PERV_EC08_PPM_VDMCR_CLEAR = 0x280F01B9ull;
+
+static const uint64_t P9N2_PERV_EC08_PPM_VDMCR_OR = 0x280F01BAull;
+
+static const uint64_t P9N2_PERV_EC09_PPM_VDMCR = 0x290F01B8ull;
+
+static const uint64_t P9N2_PERV_EC09_PPM_VDMCR_CLEAR = 0x290F01B9ull;
+
+static const uint64_t P9N2_PERV_EC09_PPM_VDMCR_OR = 0x290F01BAull;
+
+static const uint64_t P9N2_PERV_EC10_PPM_VDMCR = 0x2A0F01B8ull;
+
+static const uint64_t P9N2_PERV_EC10_PPM_VDMCR_CLEAR = 0x2A0F01B9ull;
+
+static const uint64_t P9N2_PERV_EC10_PPM_VDMCR_OR = 0x2A0F01BAull;
+
+static const uint64_t P9N2_PERV_EC11_PPM_VDMCR = 0x2B0F01B8ull;
+
+static const uint64_t P9N2_PERV_EC11_PPM_VDMCR_CLEAR = 0x2B0F01B9ull;
+
+static const uint64_t P9N2_PERV_EC11_PPM_VDMCR_OR = 0x2B0F01BAull;
+
+static const uint64_t P9N2_PERV_EC12_PPM_VDMCR = 0x2C0F01B8ull;
+
+static const uint64_t P9N2_PERV_EC12_PPM_VDMCR_CLEAR = 0x2C0F01B9ull;
+
+static const uint64_t P9N2_PERV_EC12_PPM_VDMCR_OR = 0x2C0F01BAull;
+
+static const uint64_t P9N2_PERV_EC13_PPM_VDMCR = 0x2D0F01B8ull;
+
+static const uint64_t P9N2_PERV_EC13_PPM_VDMCR_CLEAR = 0x2D0F01B9ull;
+
+static const uint64_t P9N2_PERV_EC13_PPM_VDMCR_OR = 0x2D0F01BAull;
+
+static const uint64_t P9N2_PERV_EC14_PPM_VDMCR = 0x2E0F01B8ull;
+
+static const uint64_t P9N2_PERV_EC14_PPM_VDMCR_CLEAR = 0x2E0F01B9ull;
+
+static const uint64_t P9N2_PERV_EC14_PPM_VDMCR_OR = 0x2E0F01BAull;
+
+static const uint64_t P9N2_PERV_EC15_PPM_VDMCR = 0x2F0F01B8ull;
+
+static const uint64_t P9N2_PERV_EC15_PPM_VDMCR_CLEAR = 0x2F0F01B9ull;
+
+static const uint64_t P9N2_PERV_EC15_PPM_VDMCR_OR = 0x2F0F01BAull;
+
+static const uint64_t P9N2_PERV_EC16_PPM_VDMCR = 0x300F01B8ull;
+
+static const uint64_t P9N2_PERV_EC16_PPM_VDMCR_CLEAR = 0x300F01B9ull;
+
+static const uint64_t P9N2_PERV_EC16_PPM_VDMCR_OR = 0x300F01BAull;
+
+static const uint64_t P9N2_PERV_EC17_PPM_VDMCR = 0x310F01B8ull;
+
+static const uint64_t P9N2_PERV_EC17_PPM_VDMCR_CLEAR = 0x310F01B9ull;
+
+static const uint64_t P9N2_PERV_EC17_PPM_VDMCR_OR = 0x310F01BAull;
+
+static const uint64_t P9N2_PERV_EC18_PPM_VDMCR = 0x320F01B8ull;
+
+static const uint64_t P9N2_PERV_EC18_PPM_VDMCR_CLEAR = 0x320F01B9ull;
+
+static const uint64_t P9N2_PERV_EC18_PPM_VDMCR_OR = 0x320F01BAull;
+
+static const uint64_t P9N2_PERV_EC19_PPM_VDMCR = 0x330F01B8ull;
+
+static const uint64_t P9N2_PERV_EC19_PPM_VDMCR_CLEAR = 0x330F01B9ull;
+
+static const uint64_t P9N2_PERV_EC19_PPM_VDMCR_OR = 0x330F01BAull;
+
+static const uint64_t P9N2_PERV_EC20_PPM_VDMCR = 0x340F01B8ull;
+
+static const uint64_t P9N2_PERV_EC20_PPM_VDMCR_CLEAR = 0x340F01B9ull;
+
+static const uint64_t P9N2_PERV_EC20_PPM_VDMCR_OR = 0x340F01BAull;
+
+static const uint64_t P9N2_PERV_EC21_PPM_VDMCR = 0x350F01B8ull;
+
+static const uint64_t P9N2_PERV_EC21_PPM_VDMCR_CLEAR = 0x350F01B9ull;
+
+static const uint64_t P9N2_PERV_EC21_PPM_VDMCR_OR = 0x350F01BAull;
+
+static const uint64_t P9N2_PERV_EC22_PPM_VDMCR = 0x360F01B8ull;
+
+static const uint64_t P9N2_PERV_EC22_PPM_VDMCR_CLEAR = 0x360F01B9ull;
+
+static const uint64_t P9N2_PERV_EC22_PPM_VDMCR_OR = 0x360F01BAull;
+
+static const uint64_t P9N2_PERV_EC23_PPM_VDMCR = 0x370F01B8ull;
+
+static const uint64_t P9N2_PERV_EC23_PPM_VDMCR_CLEAR = 0x370F01B9ull;
+
+static const uint64_t P9N2_PERV_EC23_PPM_VDMCR_OR = 0x370F01BAull;
+
+
+static const uint64_t P9N2_PERV_PRE_COUNTER_REG = 0x000F0028ull;
+
+static const uint64_t P9N2_PERV_TP_PRE_COUNTER_REG = 0x010F0028ull;
+
+static const uint64_t P9N2_PERV_N0_PRE_COUNTER_REG = 0x020F0028ull;
+
+static const uint64_t P9N2_PERV_N1_PRE_COUNTER_REG = 0x030F0028ull;
+
+static const uint64_t P9N2_PERV_N2_PRE_COUNTER_REG = 0x040F0028ull;
+
+static const uint64_t P9N2_PERV_N3_PRE_COUNTER_REG = 0x050F0028ull;
+
+static const uint64_t P9N2_PERV_XB_PRE_COUNTER_REG = 0x060F0028ull;
+
+static const uint64_t P9N2_PERV_MC01_PRE_COUNTER_REG = 0x070F0028ull;
+
+static const uint64_t P9N2_PERV_MC23_PRE_COUNTER_REG = 0x080F0028ull;
+
+static const uint64_t P9N2_PERV_OB0_PRE_COUNTER_REG = 0x090F0028ull;
+
+static const uint64_t P9N2_PERV_OB3_PRE_COUNTER_REG = 0x0C0F0028ull;
+
+static const uint64_t P9N2_PERV_PCI0_PRE_COUNTER_REG = 0x0D0F0028ull;
+
+static const uint64_t P9N2_PERV_PCI1_PRE_COUNTER_REG = 0x0E0F0028ull;
+
+static const uint64_t P9N2_PERV_PCI2_PRE_COUNTER_REG = 0x0F0F0028ull;
+
+static const uint64_t P9N2_PERV_EP00_PRE_COUNTER_REG = 0x100F0028ull;
+
+static const uint64_t P9N2_PERV_EP01_PRE_COUNTER_REG = 0x110F0028ull;
+
+static const uint64_t P9N2_PERV_EP02_PRE_COUNTER_REG = 0x120F0028ull;
+
+static const uint64_t P9N2_PERV_EP03_PRE_COUNTER_REG = 0x130F0028ull;
+
+static const uint64_t P9N2_PERV_EP04_PRE_COUNTER_REG = 0x140F0028ull;
+
+static const uint64_t P9N2_PERV_EP05_PRE_COUNTER_REG = 0x150F0028ull;
+
+static const uint64_t P9N2_PERV_EC00_PRE_COUNTER_REG = 0x200F0028ull;
+
+static const uint64_t P9N2_PERV_EC01_PRE_COUNTER_REG = 0x210F0028ull;
+
+static const uint64_t P9N2_PERV_EC02_PRE_COUNTER_REG = 0x220F0028ull;
+
+static const uint64_t P9N2_PERV_EC03_PRE_COUNTER_REG = 0x230F0028ull;
+
+static const uint64_t P9N2_PERV_EC04_PRE_COUNTER_REG = 0x240F0028ull;
+
+static const uint64_t P9N2_PERV_EC05_PRE_COUNTER_REG = 0x250F0028ull;
+
+static const uint64_t P9N2_PERV_EC06_PRE_COUNTER_REG = 0x260F0028ull;
+
+static const uint64_t P9N2_PERV_EC07_PRE_COUNTER_REG = 0x270F0028ull;
+
+static const uint64_t P9N2_PERV_EC08_PRE_COUNTER_REG = 0x280F0028ull;
+
+static const uint64_t P9N2_PERV_EC09_PRE_COUNTER_REG = 0x290F0028ull;
+
+static const uint64_t P9N2_PERV_EC10_PRE_COUNTER_REG = 0x2A0F0028ull;
+
+static const uint64_t P9N2_PERV_EC11_PRE_COUNTER_REG = 0x2B0F0028ull;
+
+static const uint64_t P9N2_PERV_EC12_PRE_COUNTER_REG = 0x2C0F0028ull;
+
+static const uint64_t P9N2_PERV_EC13_PRE_COUNTER_REG = 0x2D0F0028ull;
+
+static const uint64_t P9N2_PERV_EC14_PRE_COUNTER_REG = 0x2E0F0028ull;
+
+static const uint64_t P9N2_PERV_EC15_PRE_COUNTER_REG = 0x2F0F0028ull;
+
+static const uint64_t P9N2_PERV_EC16_PRE_COUNTER_REG = 0x300F0028ull;
+
+static const uint64_t P9N2_PERV_EC17_PRE_COUNTER_REG = 0x310F0028ull;
+
+static const uint64_t P9N2_PERV_EC18_PRE_COUNTER_REG = 0x320F0028ull;
+
+static const uint64_t P9N2_PERV_EC19_PRE_COUNTER_REG = 0x330F0028ull;
+
+static const uint64_t P9N2_PERV_EC20_PRE_COUNTER_REG = 0x340F0028ull;
+
+static const uint64_t P9N2_PERV_EC21_PRE_COUNTER_REG = 0x350F0028ull;
+
+static const uint64_t P9N2_PERV_EC22_PRE_COUNTER_REG = 0x360F0028ull;
+
+static const uint64_t P9N2_PERV_EC23_PRE_COUNTER_REG = 0x370F0028ull;
+
+
+static const uint64_t P9N2_PERV_PRIMARY_ADDRESS_REG = 0x000F0000ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_PERV_TP_PRIMARY_ADDRESS_REG = 0x010F0000ull;
+
+static const uint64_t P9N2_PERV_N0_PRIMARY_ADDRESS_REG = 0x020F0000ull;
+
+static const uint64_t P9N2_PERV_N1_PRIMARY_ADDRESS_REG = 0x030F0000ull;
+
+static const uint64_t P9N2_PERV_N2_PRIMARY_ADDRESS_REG = 0x040F0000ull;
+
+static const uint64_t P9N2_PERV_N3_PRIMARY_ADDRESS_REG = 0x050F0000ull;
+
+static const uint64_t P9N2_PERV_XB_PRIMARY_ADDRESS_REG = 0x060F0000ull;
+
+static const uint64_t P9N2_PERV_MC01_PRIMARY_ADDRESS_REG = 0x070F0000ull;
+
+static const uint64_t P9N2_PERV_MC23_PRIMARY_ADDRESS_REG = 0x080F0000ull;
+
+static const uint64_t P9N2_PERV_OB0_PRIMARY_ADDRESS_REG = 0x090F0000ull;
+
+static const uint64_t P9N2_PERV_OB3_PRIMARY_ADDRESS_REG = 0x0C0F0000ull;
+
+static const uint64_t P9N2_PERV_PCI0_PRIMARY_ADDRESS_REG = 0x0D0F0000ull;
+
+static const uint64_t P9N2_PERV_PCI1_PRIMARY_ADDRESS_REG = 0x0E0F0000ull;
+
+static const uint64_t P9N2_PERV_PCI2_PRIMARY_ADDRESS_REG = 0x0F0F0000ull;
+
+static const uint64_t P9N2_PERV_EP00_PRIMARY_ADDRESS_REG = 0x100F0000ull;
+
+static const uint64_t P9N2_PERV_EP01_PRIMARY_ADDRESS_REG = 0x110F0000ull;
+
+static const uint64_t P9N2_PERV_EP02_PRIMARY_ADDRESS_REG = 0x120F0000ull;
+
+static const uint64_t P9N2_PERV_EP03_PRIMARY_ADDRESS_REG = 0x130F0000ull;
+
+static const uint64_t P9N2_PERV_EP04_PRIMARY_ADDRESS_REG = 0x140F0000ull;
+
+static const uint64_t P9N2_PERV_EP05_PRIMARY_ADDRESS_REG = 0x150F0000ull;
+
+static const uint64_t P9N2_PERV_EC00_PRIMARY_ADDRESS_REG = 0x200F0000ull;
+
+static const uint64_t P9N2_PERV_EC01_PRIMARY_ADDRESS_REG = 0x210F0000ull;
+
+static const uint64_t P9N2_PERV_EC02_PRIMARY_ADDRESS_REG = 0x220F0000ull;
+
+static const uint64_t P9N2_PERV_EC03_PRIMARY_ADDRESS_REG = 0x230F0000ull;
+
+static const uint64_t P9N2_PERV_EC04_PRIMARY_ADDRESS_REG = 0x240F0000ull;
+
+static const uint64_t P9N2_PERV_EC05_PRIMARY_ADDRESS_REG = 0x250F0000ull;
+
+static const uint64_t P9N2_PERV_EC06_PRIMARY_ADDRESS_REG = 0x260F0000ull;
+
+static const uint64_t P9N2_PERV_EC07_PRIMARY_ADDRESS_REG = 0x270F0000ull;
+
+static const uint64_t P9N2_PERV_EC08_PRIMARY_ADDRESS_REG = 0x280F0000ull;
+
+static const uint64_t P9N2_PERV_EC09_PRIMARY_ADDRESS_REG = 0x290F0000ull;
+
+static const uint64_t P9N2_PERV_EC10_PRIMARY_ADDRESS_REG = 0x2A0F0000ull;
+
+static const uint64_t P9N2_PERV_EC11_PRIMARY_ADDRESS_REG = 0x2B0F0000ull;
+
+static const uint64_t P9N2_PERV_EC12_PRIMARY_ADDRESS_REG = 0x2C0F0000ull;
+
+static const uint64_t P9N2_PERV_EC13_PRIMARY_ADDRESS_REG = 0x2D0F0000ull;
+
+static const uint64_t P9N2_PERV_EC14_PRIMARY_ADDRESS_REG = 0x2E0F0000ull;
+
+static const uint64_t P9N2_PERV_EC15_PRIMARY_ADDRESS_REG = 0x2F0F0000ull;
+
+static const uint64_t P9N2_PERV_EC16_PRIMARY_ADDRESS_REG = 0x300F0000ull;
+
+static const uint64_t P9N2_PERV_EC17_PRIMARY_ADDRESS_REG = 0x310F0000ull;
+
+static const uint64_t P9N2_PERV_EC18_PRIMARY_ADDRESS_REG = 0x320F0000ull;
+
+static const uint64_t P9N2_PERV_EC19_PRIMARY_ADDRESS_REG = 0x330F0000ull;
+
+static const uint64_t P9N2_PERV_EC20_PRIMARY_ADDRESS_REG = 0x340F0000ull;
+
+static const uint64_t P9N2_PERV_EC21_PRIMARY_ADDRESS_REG = 0x350F0000ull;
+
+static const uint64_t P9N2_PERV_EC22_PRIMARY_ADDRESS_REG = 0x360F0000ull;
+
+static const uint64_t P9N2_PERV_EC23_PRIMARY_ADDRESS_REG = 0x370F0000ull;
+
+
+static const uint64_t P9N2_PERV_PROTECT_MODE_REG = 0x000F03FEull;
+
+static const uint64_t P9N2_PERV_TP_PROTECT_MODE_REG = 0x010F03FEull;
+
+static const uint64_t P9N2_PERV_N0_PROTECT_MODE_REG = 0x020F03FEull;
+
+static const uint64_t P9N2_PERV_N1_PROTECT_MODE_REG = 0x030F03FEull;
+
+static const uint64_t P9N2_PERV_N2_PROTECT_MODE_REG = 0x040F03FEull;
+
+static const uint64_t P9N2_PERV_N3_PROTECT_MODE_REG = 0x050F03FEull;
+
+static const uint64_t P9N2_PERV_XB_PROTECT_MODE_REG = 0x060F03FEull;
+
+static const uint64_t P9N2_PERV_MC01_PROTECT_MODE_REG = 0x070F03FEull;
+
+static const uint64_t P9N2_PERV_MC23_PROTECT_MODE_REG = 0x080F03FEull;
+
+static const uint64_t P9N2_PERV_OB0_PROTECT_MODE_REG = 0x090F03FEull;
+
+static const uint64_t P9N2_PERV_OB3_PROTECT_MODE_REG = 0x0C0F03FEull;
+
+static const uint64_t P9N2_PERV_PCI0_PROTECT_MODE_REG = 0x0D0F03FEull;
+
+static const uint64_t P9N2_PERV_PCI1_PROTECT_MODE_REG = 0x0E0F03FEull;
+
+static const uint64_t P9N2_PERV_PCI2_PROTECT_MODE_REG = 0x0F0F03FEull;
+
+static const uint64_t P9N2_PERV_EP00_PROTECT_MODE_REG = 0x100F03FEull;
+
+static const uint64_t P9N2_PERV_EP01_PROTECT_MODE_REG = 0x110F03FEull;
+
+static const uint64_t P9N2_PERV_EP02_PROTECT_MODE_REG = 0x120F03FEull;
+
+static const uint64_t P9N2_PERV_EP03_PROTECT_MODE_REG = 0x130F03FEull;
+
+static const uint64_t P9N2_PERV_EP04_PROTECT_MODE_REG = 0x140F03FEull;
+
+static const uint64_t P9N2_PERV_EP05_PROTECT_MODE_REG = 0x150F03FEull;
+
+static const uint64_t P9N2_PERV_EC00_PROTECT_MODE_REG = 0x200F03FEull;
+
+static const uint64_t P9N2_PERV_EC01_PROTECT_MODE_REG = 0x210F03FEull;
+
+static const uint64_t P9N2_PERV_EC02_PROTECT_MODE_REG = 0x220F03FEull;
+
+static const uint64_t P9N2_PERV_EC03_PROTECT_MODE_REG = 0x230F03FEull;
+
+static const uint64_t P9N2_PERV_EC04_PROTECT_MODE_REG = 0x240F03FEull;
+
+static const uint64_t P9N2_PERV_EC05_PROTECT_MODE_REG = 0x250F03FEull;
+
+static const uint64_t P9N2_PERV_EC06_PROTECT_MODE_REG = 0x260F03FEull;
+
+static const uint64_t P9N2_PERV_EC07_PROTECT_MODE_REG = 0x270F03FEull;
+
+static const uint64_t P9N2_PERV_EC08_PROTECT_MODE_REG = 0x280F03FEull;
+
+static const uint64_t P9N2_PERV_EC09_PROTECT_MODE_REG = 0x290F03FEull;
+
+static const uint64_t P9N2_PERV_EC10_PROTECT_MODE_REG = 0x2A0F03FEull;
+
+static const uint64_t P9N2_PERV_EC11_PROTECT_MODE_REG = 0x2B0F03FEull;
+
+static const uint64_t P9N2_PERV_EC12_PROTECT_MODE_REG = 0x2C0F03FEull;
+
+static const uint64_t P9N2_PERV_EC13_PROTECT_MODE_REG = 0x2D0F03FEull;
+
+static const uint64_t P9N2_PERV_EC14_PROTECT_MODE_REG = 0x2E0F03FEull;
+
+static const uint64_t P9N2_PERV_EC15_PROTECT_MODE_REG = 0x2F0F03FEull;
+
+static const uint64_t P9N2_PERV_EC16_PROTECT_MODE_REG = 0x300F03FEull;
+
+static const uint64_t P9N2_PERV_EC17_PROTECT_MODE_REG = 0x310F03FEull;
+
+static const uint64_t P9N2_PERV_EC18_PROTECT_MODE_REG = 0x320F03FEull;
+
+static const uint64_t P9N2_PERV_EC19_PROTECT_MODE_REG = 0x330F03FEull;
+
+static const uint64_t P9N2_PERV_EC20_PROTECT_MODE_REG = 0x340F03FEull;
+
+static const uint64_t P9N2_PERV_EC21_PROTECT_MODE_REG = 0x350F03FEull;
+
+static const uint64_t P9N2_PERV_EC22_PROTECT_MODE_REG = 0x360F03FEull;
+
+static const uint64_t P9N2_PERV_EC23_PROTECT_MODE_REG = 0x370F03FEull;
+
+
+static const uint64_t P9N2_PERV_PSCOM_ERROR_MASK = 0x00010002ull;
+
+static const uint64_t P9N2_PERV_TP_PSCOM_ERROR_MASK = 0x01010002ull;
+
+
+static const uint64_t P9N2_PERV_PSCOM_MODE_REG = 0x00010000ull;
+
+static const uint64_t P9N2_PERV_TP_PSCOM_MODE_REG = 0x01010000ull;
+
+
+static const uint64_t P9N2_PERV_PSCOM_STATUS_ERROR_REG = 0x00010001ull;
+
+static const uint64_t P9N2_PERV_TP_PSCOM_STATUS_ERROR_REG = 0x01010001ull;
+
+
+static const uint64_t P9N2_PERV_EP00_QPPM_DPLL_CTRL = 0x100F0152ull;
+
+static const uint64_t P9N2_PERV_EP00_QPPM_DPLL_CTRL_CLEAR = 0x100F0153ull;
+
+static const uint64_t P9N2_PERV_EP00_QPPM_DPLL_CTRL_OR = 0x100F0154ull;
+
+static const uint64_t P9N2_PERV_EP01_QPPM_DPLL_CTRL = 0x110F0152ull;
+
+static const uint64_t P9N2_PERV_EP01_QPPM_DPLL_CTRL_CLEAR = 0x110F0153ull;
+
+static const uint64_t P9N2_PERV_EP01_QPPM_DPLL_CTRL_OR = 0x110F0154ull;
+
+static const uint64_t P9N2_PERV_EP02_QPPM_DPLL_CTRL = 0x120F0152ull;
+
+static const uint64_t P9N2_PERV_EP02_QPPM_DPLL_CTRL_CLEAR = 0x120F0153ull;
+
+static const uint64_t P9N2_PERV_EP02_QPPM_DPLL_CTRL_OR = 0x120F0154ull;
+
+static const uint64_t P9N2_PERV_EP03_QPPM_DPLL_CTRL = 0x130F0152ull;
+
+static const uint64_t P9N2_PERV_EP03_QPPM_DPLL_CTRL_CLEAR = 0x130F0153ull;
+
+static const uint64_t P9N2_PERV_EP03_QPPM_DPLL_CTRL_OR = 0x130F0154ull;
+
+static const uint64_t P9N2_PERV_EP04_QPPM_DPLL_CTRL = 0x140F0152ull;
+
+static const uint64_t P9N2_PERV_EP04_QPPM_DPLL_CTRL_CLEAR = 0x140F0153ull;
+
+static const uint64_t P9N2_PERV_EP04_QPPM_DPLL_CTRL_OR = 0x140F0154ull;
+
+static const uint64_t P9N2_PERV_EP05_QPPM_DPLL_CTRL = 0x150F0152ull;
+
+static const uint64_t P9N2_PERV_EP05_QPPM_DPLL_CTRL_CLEAR = 0x150F0153ull;
+
+static const uint64_t P9N2_PERV_EP05_QPPM_DPLL_CTRL_OR = 0x150F0154ull;
+
+
+static const uint64_t P9N2_PERV_EP00_QPPM_DPLL_FREQ = 0x100F0151ull;
+
+static const uint64_t P9N2_PERV_EP01_QPPM_DPLL_FREQ = 0x110F0151ull;
+
+static const uint64_t P9N2_PERV_EP02_QPPM_DPLL_FREQ = 0x120F0151ull;
+
+static const uint64_t P9N2_PERV_EP03_QPPM_DPLL_FREQ = 0x130F0151ull;
+
+static const uint64_t P9N2_PERV_EP04_QPPM_DPLL_FREQ = 0x140F0151ull;
+
+static const uint64_t P9N2_PERV_EP05_QPPM_DPLL_FREQ = 0x150F0151ull;
+
+
+static const uint64_t P9N2_PERV_EP00_QPPM_DPLL_ICHAR = 0x100F0157ull;
+
+static const uint64_t P9N2_PERV_EP01_QPPM_DPLL_ICHAR = 0x110F0157ull;
+
+static const uint64_t P9N2_PERV_EP02_QPPM_DPLL_ICHAR = 0x120F0157ull;
+
+static const uint64_t P9N2_PERV_EP03_QPPM_DPLL_ICHAR = 0x130F0157ull;
+
+static const uint64_t P9N2_PERV_EP04_QPPM_DPLL_ICHAR = 0x140F0157ull;
+
+static const uint64_t P9N2_PERV_EP05_QPPM_DPLL_ICHAR = 0x150F0157ull;
+
+
+static const uint64_t P9N2_PERV_EP00_QPPM_DPLL_OCHAR = 0x100F0156ull;
+
+static const uint64_t P9N2_PERV_EP01_QPPM_DPLL_OCHAR = 0x110F0156ull;
+
+static const uint64_t P9N2_PERV_EP02_QPPM_DPLL_OCHAR = 0x120F0156ull;
+
+static const uint64_t P9N2_PERV_EP03_QPPM_DPLL_OCHAR = 0x130F0156ull;
+
+static const uint64_t P9N2_PERV_EP04_QPPM_DPLL_OCHAR = 0x140F0156ull;
+
+static const uint64_t P9N2_PERV_EP05_QPPM_DPLL_OCHAR = 0x150F0156ull;
+
+
+static const uint64_t P9N2_PERV_EP00_QPPM_DPLL_STAT = 0x100F0155ull;
+
+static const uint64_t P9N2_PERV_EP01_QPPM_DPLL_STAT = 0x110F0155ull;
+
+static const uint64_t P9N2_PERV_EP02_QPPM_DPLL_STAT = 0x120F0155ull;
+
+static const uint64_t P9N2_PERV_EP03_QPPM_DPLL_STAT = 0x130F0155ull;
+
+static const uint64_t P9N2_PERV_EP04_QPPM_DPLL_STAT = 0x140F0155ull;
+
+static const uint64_t P9N2_PERV_EP05_QPPM_DPLL_STAT = 0x150F0155ull;
+
+
+static const uint64_t P9N2_PERV_EP00_QPPM_ERR = 0x100F0121ull;
+
+static const uint64_t P9N2_PERV_EP01_QPPM_ERR = 0x110F0121ull;
+
+static const uint64_t P9N2_PERV_EP02_QPPM_ERR = 0x120F0121ull;
+
+static const uint64_t P9N2_PERV_EP03_QPPM_ERR = 0x130F0121ull;
+
+static const uint64_t P9N2_PERV_EP04_QPPM_ERR = 0x140F0121ull;
+
+static const uint64_t P9N2_PERV_EP05_QPPM_ERR = 0x150F0121ull;
+
+
+static const uint64_t P9N2_PERV_EP00_QPPM_ERRMSK = 0x100F0122ull;
+
+static const uint64_t P9N2_PERV_EP01_QPPM_ERRMSK = 0x110F0122ull;
+
+static const uint64_t P9N2_PERV_EP02_QPPM_ERRMSK = 0x120F0122ull;
+
+static const uint64_t P9N2_PERV_EP03_QPPM_ERRMSK = 0x130F0122ull;
+
+static const uint64_t P9N2_PERV_EP04_QPPM_ERRMSK = 0x140F0122ull;
+
+static const uint64_t P9N2_PERV_EP05_QPPM_ERRMSK = 0x150F0122ull;
+
+
+static const uint64_t P9N2_PERV_EP00_QPPM_ERRSUM = 0x100F0120ull;
+
+static const uint64_t P9N2_PERV_EP01_QPPM_ERRSUM = 0x110F0120ull;
+
+static const uint64_t P9N2_PERV_EP02_QPPM_ERRSUM = 0x120F0120ull;
+
+static const uint64_t P9N2_PERV_EP03_QPPM_ERRSUM = 0x130F0120ull;
+
+static const uint64_t P9N2_PERV_EP04_QPPM_ERRSUM = 0x140F0120ull;
+
+static const uint64_t P9N2_PERV_EP05_QPPM_ERRSUM = 0x150F0120ull;
+
+
+static const uint64_t P9N2_PERV_EP00_QPPM_EXCGCR = 0x100F0165ull;
+
+static const uint64_t P9N2_PERV_EP00_QPPM_EXCGCR_CLEAR = 0x100F0166ull;
+
+static const uint64_t P9N2_PERV_EP00_QPPM_EXCGCR_OR = 0x100F0167ull;
+
+static const uint64_t P9N2_PERV_EP01_QPPM_EXCGCR = 0x110F0165ull;
+
+static const uint64_t P9N2_PERV_EP01_QPPM_EXCGCR_CLEAR = 0x110F0166ull;
+
+static const uint64_t P9N2_PERV_EP01_QPPM_EXCGCR_OR = 0x110F0167ull;
+
+static const uint64_t P9N2_PERV_EP02_QPPM_EXCGCR = 0x120F0165ull;
+
+static const uint64_t P9N2_PERV_EP02_QPPM_EXCGCR_CLEAR = 0x120F0166ull;
+
+static const uint64_t P9N2_PERV_EP02_QPPM_EXCGCR_OR = 0x120F0167ull;
+
+static const uint64_t P9N2_PERV_EP03_QPPM_EXCGCR = 0x130F0165ull;
+
+static const uint64_t P9N2_PERV_EP03_QPPM_EXCGCR_CLEAR = 0x130F0166ull;
+
+static const uint64_t P9N2_PERV_EP03_QPPM_EXCGCR_OR = 0x130F0167ull;
+
+static const uint64_t P9N2_PERV_EP04_QPPM_EXCGCR = 0x140F0165ull;
+
+static const uint64_t P9N2_PERV_EP04_QPPM_EXCGCR_CLEAR = 0x140F0166ull;
+
+static const uint64_t P9N2_PERV_EP04_QPPM_EXCGCR_OR = 0x140F0167ull;
+
+static const uint64_t P9N2_PERV_EP05_QPPM_EXCGCR = 0x150F0165ull;
+
+static const uint64_t P9N2_PERV_EP05_QPPM_EXCGCR_CLEAR = 0x150F0166ull;
+
+static const uint64_t P9N2_PERV_EP05_QPPM_EXCGCR_OR = 0x150F0167ull;
+
+
+static const uint64_t P9N2_PERV_EP00_QPPM_OCCHB = 0x100F015Full;
+
+static const uint64_t P9N2_PERV_EP01_QPPM_OCCHB = 0x110F015Full;
+
+static const uint64_t P9N2_PERV_EP02_QPPM_OCCHB = 0x120F015Full;
+
+static const uint64_t P9N2_PERV_EP03_QPPM_OCCHB = 0x130F015Full;
+
+static const uint64_t P9N2_PERV_EP04_QPPM_OCCHB = 0x140F015Full;
+
+static const uint64_t P9N2_PERV_EP05_QPPM_OCCHB = 0x150F015Full;
+
+
+static const uint64_t P9N2_PERV_EP00_QPPM_QACCR = 0x100F0160ull;
+
+static const uint64_t P9N2_PERV_EP00_QPPM_QACCR_CLEAR = 0x100F0161ull;
+
+static const uint64_t P9N2_PERV_EP00_QPPM_QACCR_OR = 0x100F0162ull;
+
+static const uint64_t P9N2_PERV_EP01_QPPM_QACCR = 0x110F0160ull;
+
+static const uint64_t P9N2_PERV_EP01_QPPM_QACCR_CLEAR = 0x110F0161ull;
+
+static const uint64_t P9N2_PERV_EP01_QPPM_QACCR_OR = 0x110F0162ull;
+
+static const uint64_t P9N2_PERV_EP02_QPPM_QACCR = 0x120F0160ull;
+
+static const uint64_t P9N2_PERV_EP02_QPPM_QACCR_CLEAR = 0x120F0161ull;
+
+static const uint64_t P9N2_PERV_EP02_QPPM_QACCR_OR = 0x120F0162ull;
+
+static const uint64_t P9N2_PERV_EP03_QPPM_QACCR = 0x130F0160ull;
+
+static const uint64_t P9N2_PERV_EP03_QPPM_QACCR_CLEAR = 0x130F0161ull;
+
+static const uint64_t P9N2_PERV_EP03_QPPM_QACCR_OR = 0x130F0162ull;
+
+static const uint64_t P9N2_PERV_EP04_QPPM_QACCR = 0x140F0160ull;
+
+static const uint64_t P9N2_PERV_EP04_QPPM_QACCR_CLEAR = 0x140F0161ull;
+
+static const uint64_t P9N2_PERV_EP04_QPPM_QACCR_OR = 0x140F0162ull;
+
+static const uint64_t P9N2_PERV_EP05_QPPM_QACCR = 0x150F0160ull;
+
+static const uint64_t P9N2_PERV_EP05_QPPM_QACCR_CLEAR = 0x150F0161ull;
+
+static const uint64_t P9N2_PERV_EP05_QPPM_QACCR_OR = 0x150F0162ull;
+
+
+static const uint64_t P9N2_PERV_EP00_QPPM_QACSR = 0x100F0163ull;
+
+static const uint64_t P9N2_PERV_EP01_QPPM_QACSR = 0x110F0163ull;
+
+static const uint64_t P9N2_PERV_EP02_QPPM_QACSR = 0x120F0163ull;
+
+static const uint64_t P9N2_PERV_EP03_QPPM_QACSR = 0x130F0163ull;
+
+static const uint64_t P9N2_PERV_EP04_QPPM_QACSR = 0x140F0163ull;
+
+static const uint64_t P9N2_PERV_EP05_QPPM_QACSR = 0x150F0163ull;
+
+
+static const uint64_t P9N2_PERV_EP00_QPPM_QCCR_SCOM = 0x100F01BDull;
+
+static const uint64_t P9N2_PERV_EP00_QPPM_QCCR_SCOM1 = 0x100F01BEull;
+
+static const uint64_t P9N2_PERV_EP00_QPPM_QCCR_SCOM2 = 0x100F01BFull;
+
+static const uint64_t P9N2_PERV_EP01_QPPM_QCCR_SCOM = 0x110F01BDull;
+
+static const uint64_t P9N2_PERV_EP01_QPPM_QCCR_SCOM1 = 0x110F01BEull;
+
+static const uint64_t P9N2_PERV_EP01_QPPM_QCCR_SCOM2 = 0x110F01BFull;
+
+static const uint64_t P9N2_PERV_EP02_QPPM_QCCR_SCOM = 0x120F01BDull;
+
+static const uint64_t P9N2_PERV_EP02_QPPM_QCCR_SCOM1 = 0x120F01BEull;
+
+static const uint64_t P9N2_PERV_EP02_QPPM_QCCR_SCOM2 = 0x120F01BFull;
+
+static const uint64_t P9N2_PERV_EP03_QPPM_QCCR_SCOM = 0x130F01BDull;
+
+static const uint64_t P9N2_PERV_EP03_QPPM_QCCR_SCOM1 = 0x130F01BEull;
+
+static const uint64_t P9N2_PERV_EP03_QPPM_QCCR_SCOM2 = 0x130F01BFull;
+
+static const uint64_t P9N2_PERV_EP04_QPPM_QCCR_SCOM = 0x140F01BDull;
+
+static const uint64_t P9N2_PERV_EP04_QPPM_QCCR_SCOM1 = 0x140F01BEull;
+
+static const uint64_t P9N2_PERV_EP04_QPPM_QCCR_SCOM2 = 0x140F01BFull;
+
+static const uint64_t P9N2_PERV_EP05_QPPM_QCCR_SCOM = 0x150F01BDull;
+
+static const uint64_t P9N2_PERV_EP05_QPPM_QCCR_SCOM1 = 0x150F01BEull;
+
+static const uint64_t P9N2_PERV_EP05_QPPM_QCCR_SCOM2 = 0x150F01BFull;
+
+
+static const uint64_t P9N2_PERV_EP00_QPPM_QPMMR = 0x100F0103ull;
+
+static const uint64_t P9N2_PERV_EP00_QPPM_QPMMR_CLEAR = 0x100F0104ull;
+
+static const uint64_t P9N2_PERV_EP00_QPPM_QPMMR_OR = 0x100F0105ull;
+
+static const uint64_t P9N2_PERV_EP01_QPPM_QPMMR = 0x110F0103ull;
+
+static const uint64_t P9N2_PERV_EP01_QPPM_QPMMR_CLEAR = 0x110F0104ull;
+
+static const uint64_t P9N2_PERV_EP01_QPPM_QPMMR_OR = 0x110F0105ull;
+
+static const uint64_t P9N2_PERV_EP02_QPPM_QPMMR = 0x120F0103ull;
+
+static const uint64_t P9N2_PERV_EP02_QPPM_QPMMR_CLEAR = 0x120F0104ull;
+
+static const uint64_t P9N2_PERV_EP02_QPPM_QPMMR_OR = 0x120F0105ull;
+
+static const uint64_t P9N2_PERV_EP03_QPPM_QPMMR = 0x130F0103ull;
+
+static const uint64_t P9N2_PERV_EP03_QPPM_QPMMR_CLEAR = 0x130F0104ull;
+
+static const uint64_t P9N2_PERV_EP03_QPPM_QPMMR_OR = 0x130F0105ull;
+
+static const uint64_t P9N2_PERV_EP04_QPPM_QPMMR = 0x140F0103ull;
+
+static const uint64_t P9N2_PERV_EP04_QPPM_QPMMR_CLEAR = 0x140F0104ull;
+
+static const uint64_t P9N2_PERV_EP04_QPPM_QPMMR_OR = 0x140F0105ull;
+
+static const uint64_t P9N2_PERV_EP05_QPPM_QPMMR = 0x150F0103ull;
+
+static const uint64_t P9N2_PERV_EP05_QPPM_QPMMR_CLEAR = 0x150F0104ull;
+
+static const uint64_t P9N2_PERV_EP05_QPPM_QPMMR_OR = 0x150F0105ull;
+
+
+static const uint64_t P9N2_PERV_EP00_QPPM_VDMCFGR = 0x100F01B6ull;
+
+static const uint64_t P9N2_PERV_EP01_QPPM_VDMCFGR = 0x110F01B6ull;
+
+static const uint64_t P9N2_PERV_EP02_QPPM_VDMCFGR = 0x120F01B6ull;
+
+static const uint64_t P9N2_PERV_EP03_QPPM_VDMCFGR = 0x130F01B6ull;
+
+static const uint64_t P9N2_PERV_EP04_QPPM_VDMCFGR = 0x140F01B6ull;
+
+static const uint64_t P9N2_PERV_EP05_QPPM_VDMCFGR = 0x150F01B6ull;
+
+
+static const uint64_t P9N2_PERV_EP00_QPPM_VOLT_CHAR = 0x100F01BBull;
+
+static const uint64_t P9N2_PERV_EP01_QPPM_VOLT_CHAR = 0x110F01BBull;
+
+static const uint64_t P9N2_PERV_EP02_QPPM_VOLT_CHAR = 0x120F01BBull;
+
+static const uint64_t P9N2_PERV_EP03_QPPM_VOLT_CHAR = 0x130F01BBull;
+
+static const uint64_t P9N2_PERV_EP04_QPPM_VOLT_CHAR = 0x140F01BBull;
+
+static const uint64_t P9N2_PERV_EP05_QPPM_VOLT_CHAR = 0x150F01BBull;
+
+
+static const uint32_t P9N2_PERV_FSISHIFT_READ_BUFFER_FSI = 0x00000C03ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_READ_BUFFER_FSI_BYTE = 0x00000C0Cull;
+
+
+static const uint64_t P9N2_PERV_RECOV_INTERRUPT_REG = 0x000F001Bull;
+
+static const uint64_t P9N2_PERV_TP_RECOV_INTERRUPT_REG = 0x010F001Bull;
+
+static const uint64_t P9N2_PERV_N0_RECOV_INTERRUPT_REG = 0x020F001Bull;
+
+static const uint64_t P9N2_PERV_N1_RECOV_INTERRUPT_REG = 0x030F001Bull;
+
+static const uint64_t P9N2_PERV_N2_RECOV_INTERRUPT_REG = 0x040F001Bull;
+
+static const uint64_t P9N2_PERV_N3_RECOV_INTERRUPT_REG = 0x050F001Bull;
+
+static const uint64_t P9N2_PERV_XB_RECOV_INTERRUPT_REG = 0x060F001Bull;
+
+static const uint64_t P9N2_PERV_MC01_RECOV_INTERRUPT_REG = 0x070F001Bull;
+
+static const uint64_t P9N2_PERV_MC23_RECOV_INTERRUPT_REG = 0x080F001Bull;
+
+static const uint64_t P9N2_PERV_OB0_RECOV_INTERRUPT_REG = 0x090F001Bull;
+
+static const uint64_t P9N2_PERV_OB3_RECOV_INTERRUPT_REG = 0x0C0F001Bull;
+
+static const uint64_t P9N2_PERV_PCI0_RECOV_INTERRUPT_REG = 0x0D0F001Bull;
+
+static const uint64_t P9N2_PERV_PCI1_RECOV_INTERRUPT_REG = 0x0E0F001Bull;
+
+static const uint64_t P9N2_PERV_PCI2_RECOV_INTERRUPT_REG = 0x0F0F001Bull;
+
+static const uint64_t P9N2_PERV_EP00_RECOV_INTERRUPT_REG = 0x100F001Bull;
+
+static const uint64_t P9N2_PERV_EP01_RECOV_INTERRUPT_REG = 0x110F001Bull;
+
+static const uint64_t P9N2_PERV_EP02_RECOV_INTERRUPT_REG = 0x120F001Bull;
+
+static const uint64_t P9N2_PERV_EP03_RECOV_INTERRUPT_REG = 0x130F001Bull;
+
+static const uint64_t P9N2_PERV_EP04_RECOV_INTERRUPT_REG = 0x140F001Bull;
+
+static const uint64_t P9N2_PERV_EP05_RECOV_INTERRUPT_REG = 0x150F001Bull;
+
+static const uint64_t P9N2_PERV_EC00_RECOV_INTERRUPT_REG = 0x200F001Bull;
+
+static const uint64_t P9N2_PERV_EC01_RECOV_INTERRUPT_REG = 0x210F001Bull;
+
+static const uint64_t P9N2_PERV_EC02_RECOV_INTERRUPT_REG = 0x220F001Bull;
+
+static const uint64_t P9N2_PERV_EC03_RECOV_INTERRUPT_REG = 0x230F001Bull;
+
+static const uint64_t P9N2_PERV_EC04_RECOV_INTERRUPT_REG = 0x240F001Bull;
+
+static const uint64_t P9N2_PERV_EC05_RECOV_INTERRUPT_REG = 0x250F001Bull;
+
+static const uint64_t P9N2_PERV_EC06_RECOV_INTERRUPT_REG = 0x260F001Bull;
+
+static const uint64_t P9N2_PERV_EC07_RECOV_INTERRUPT_REG = 0x270F001Bull;
+
+static const uint64_t P9N2_PERV_EC08_RECOV_INTERRUPT_REG = 0x280F001Bull;
+
+static const uint64_t P9N2_PERV_EC09_RECOV_INTERRUPT_REG = 0x290F001Bull;
+
+static const uint64_t P9N2_PERV_EC10_RECOV_INTERRUPT_REG = 0x2A0F001Bull;
+
+static const uint64_t P9N2_PERV_EC11_RECOV_INTERRUPT_REG = 0x2B0F001Bull;
+
+static const uint64_t P9N2_PERV_EC12_RECOV_INTERRUPT_REG = 0x2C0F001Bull;
+
+static const uint64_t P9N2_PERV_EC13_RECOV_INTERRUPT_REG = 0x2D0F001Bull;
+
+static const uint64_t P9N2_PERV_EC14_RECOV_INTERRUPT_REG = 0x2E0F001Bull;
+
+static const uint64_t P9N2_PERV_EC15_RECOV_INTERRUPT_REG = 0x2F0F001Bull;
+
+static const uint64_t P9N2_PERV_EC16_RECOV_INTERRUPT_REG = 0x300F001Bull;
+
+static const uint64_t P9N2_PERV_EC17_RECOV_INTERRUPT_REG = 0x310F001Bull;
+
+static const uint64_t P9N2_PERV_EC18_RECOV_INTERRUPT_REG = 0x320F001Bull;
+
+static const uint64_t P9N2_PERV_EC19_RECOV_INTERRUPT_REG = 0x330F001Bull;
+
+static const uint64_t P9N2_PERV_EC20_RECOV_INTERRUPT_REG = 0x340F001Bull;
+
+static const uint64_t P9N2_PERV_EC21_RECOV_INTERRUPT_REG = 0x350F001Bull;
+
+static const uint64_t P9N2_PERV_EC22_RECOV_INTERRUPT_REG = 0x360F001Bull;
+
+static const uint64_t P9N2_PERV_EC23_RECOV_INTERRUPT_REG = 0x370F001Bull;
+
+
+static const uint64_t P9N2_PERV_REC_ACK_REG = 0x000F0010ull;
+
+static const uint64_t P9N2_PERV_PIB_REC_ACK_REG = 0x000F0010ull;
+
+
+static const uint64_t P9N2_PERV_REC_ERR_REG0 = 0x000F0011ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_PERV_PIB_REC_ERR_REG0 = 0x000F0011ull;
+
+
+static const uint64_t P9N2_PERV_REC_ERR_REG1 = 0x000F0012ull;
+
+static const uint64_t P9N2_PERV_PIB_REC_ERR_REG1 = 0x000F0012ull;
+
+
+static const uint64_t P9N2_PERV_REC_ERR_REG2 = 0x000F0013ull;
+
+static const uint64_t P9N2_PERV_PIB_REC_ERR_REG2 = 0x000F0013ull;
+
+
+static const uint64_t P9N2_PERV_REC_ERR_REG3 = 0x000F0014ull;
+
+static const uint64_t P9N2_PERV_PIB_REC_ERR_REG3 = 0x000F0014ull;
+
+
+static const uint64_t P9N2_PERV_RESET = 0x00030004ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_PERV_PIB_RESET = 0x00030004ull;
+
+static const uint64_t P9N2_PERV_0_PIB2OPB0_RESET = 0x00020004ull;
+
+static const uint64_t P9N2_PERV_0_PIB2OPB1_RESET = 0x00020014ull;
+
+static const uint32_t P9N2_PERV_FSI2PIB_RESET_FSI = 0x00001006ull;
+
+static const uint32_t P9N2_PERV_FSI2PIB_RESET_FSI_BYTE = 0x00001018ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_RESET_FSI = 0x00000C06ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_RESET_FSI_BYTE = 0x00000C18ull;
+
+static const uint64_t P9N2_PERV_PIB2OPB0_RESET = 0x00020004ull;
+
+static const uint64_t P9N2_PERV_PIB2OPB1_RESET = 0x00020014ull;
+
+
+static const uint32_t P9N2_PERV_FSISHIFT_RESET_ERRORS_FSI = 0x00000C07ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_RESET_ERRORS_FSI_BYTE = 0x00000C1Cull;
+
+
+static const uint64_t P9N2_PERV_RESET_REG = 0x000F001Dull;
+
+static const uint64_t P9N2_PERV_PIB_RESET_REG = 0x000F001Dull;
+
+
+static const uint64_t P9N2_PERV_0_FSII2C_RESIDUAL_FRONT_END_BACK_END_LENGTH_A = 0x00001809ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint32_t P9N2_PERV_FSII2C_RESIDUAL_FRONT_END_BACK_END_LENGTH_A = 0x00001809ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+
+static const uint64_t P9N2_PERV_RFIR = 0x00040001ull;
+
+static const uint64_t P9N2_PERV_TP_RFIR = 0x01040001ull;
+
+static const uint64_t P9N2_PERV_N0_RFIR = 0x02040001ull;
+
+static const uint64_t P9N2_PERV_N1_RFIR = 0x03040001ull;
+
+static const uint64_t P9N2_PERV_N2_RFIR = 0x04040001ull;
+
+static const uint64_t P9N2_PERV_N3_RFIR = 0x05040001ull;
+
+static const uint64_t P9N2_PERV_XB_RFIR = 0x06040001ull;
+
+static const uint64_t P9N2_PERV_MC01_RFIR = 0x07040001ull;
+
+static const uint64_t P9N2_PERV_MC23_RFIR = 0x08040001ull;
+
+static const uint64_t P9N2_PERV_OB0_RFIR = 0x09040001ull;
+
+static const uint64_t P9N2_PERV_OB3_RFIR = 0x0C040001ull;
+
+static const uint64_t P9N2_PERV_PCI0_RFIR = 0x0D040001ull;
+
+static const uint64_t P9N2_PERV_PCI1_RFIR = 0x0E040001ull;
+
+static const uint64_t P9N2_PERV_PCI2_RFIR = 0x0F040001ull;
+
+static const uint64_t P9N2_PERV_EP00_RFIR = 0x10040001ull;
+
+static const uint64_t P9N2_PERV_EP01_RFIR = 0x11040001ull;
+
+static const uint64_t P9N2_PERV_EP02_RFIR = 0x12040001ull;
+
+static const uint64_t P9N2_PERV_EP03_RFIR = 0x13040001ull;
+
+static const uint64_t P9N2_PERV_EP04_RFIR = 0x14040001ull;
+
+static const uint64_t P9N2_PERV_EP05_RFIR = 0x15040001ull;
+
+static const uint64_t P9N2_PERV_EC00_RFIR = 0x20040001ull;
+
+static const uint64_t P9N2_PERV_EC01_RFIR = 0x21040001ull;
+
+static const uint64_t P9N2_PERV_EC02_RFIR = 0x22040001ull;
+
+static const uint64_t P9N2_PERV_EC03_RFIR = 0x23040001ull;
+
+static const uint64_t P9N2_PERV_EC04_RFIR = 0x24040001ull;
+
+static const uint64_t P9N2_PERV_EC05_RFIR = 0x25040001ull;
+
+static const uint64_t P9N2_PERV_EC06_RFIR = 0x26040001ull;
+
+static const uint64_t P9N2_PERV_EC07_RFIR = 0x27040001ull;
+
+static const uint64_t P9N2_PERV_EC08_RFIR = 0x28040001ull;
+
+static const uint64_t P9N2_PERV_EC09_RFIR = 0x29040001ull;
+
+static const uint64_t P9N2_PERV_EC10_RFIR = 0x2A040001ull;
+
+static const uint64_t P9N2_PERV_EC11_RFIR = 0x2B040001ull;
+
+static const uint64_t P9N2_PERV_EC12_RFIR = 0x2C040001ull;
+
+static const uint64_t P9N2_PERV_EC13_RFIR = 0x2D040001ull;
+
+static const uint64_t P9N2_PERV_EC14_RFIR = 0x2E040001ull;
+
+static const uint64_t P9N2_PERV_EC15_RFIR = 0x2F040001ull;
+
+static const uint64_t P9N2_PERV_EC16_RFIR = 0x30040001ull;
+
+static const uint64_t P9N2_PERV_EC17_RFIR = 0x31040001ull;
+
+static const uint64_t P9N2_PERV_EC18_RFIR = 0x32040001ull;
+
+static const uint64_t P9N2_PERV_EC19_RFIR = 0x33040001ull;
+
+static const uint64_t P9N2_PERV_EC20_RFIR = 0x34040001ull;
+
+static const uint64_t P9N2_PERV_EC21_RFIR = 0x35040001ull;
+
+static const uint64_t P9N2_PERV_EC22_RFIR = 0x36040001ull;
+
+static const uint64_t P9N2_PERV_EC23_RFIR = 0x37040001ull;
+
+
+static const uint64_t P9N2_PERV_RING_FENCE_MASK_LATCH_REG = 0x00010008ull;
+
+static const uint64_t P9N2_PERV_TP_RING_FENCE_MASK_LATCH_REG = 0x01010008ull;
+
+
+static const uint32_t P9N2_PERV_ROOT_CTRL0_FSI = 0x00002810ull;
+
+static const uint32_t P9N2_PERV_ROOT_CTRL0_FSI_BYTE = 0x00002840ull;
+
+static const uint64_t P9N2_PERV_ROOT_CTRL0_SCOM = 0x00050010ull;
+
+static const uint64_t P9N2_PERV_PIB_ROOT_CTRL0 = 0x00050010ull;
+
+
+static const uint32_t P9N2_PERV_ROOT_CTRL0_CLEAR_FSI = 0x00002930ull;
+
+static const uint32_t P9N2_PERV_ROOT_CTRL0_CLEAR_FSI_BYTE = 0x00002CC0ull;
+
+static const uint64_t P9N2_PERV_ROOT_CTRL0_CLEAR_SCOM = 0x00050130ull;
+
+static const uint64_t P9N2_PERV_PIB_ROOT_CTRL0_CLEAR = 0x00050130ull;
+
+
+static const uint32_t P9N2_PERV_ROOT_CTRL0_COPY_FSI = 0x00002910ull;
+
+static const uint32_t P9N2_PERV_ROOT_CTRL0_COPY_FSI_BYTE = 0x00002C40ull;
+
+static const uint64_t P9N2_PERV_ROOT_CTRL0_COPY_SCOM = 0x00050110ull;
+
+static const uint64_t P9N2_PERV_PIB_ROOT_CTRL0_COPY = 0x00050110ull;
+
+
+static const uint32_t P9N2_PERV_ROOT_CTRL0_SET_FSI = 0x00002920ull;
+
+static const uint32_t P9N2_PERV_ROOT_CTRL0_SET_FSI_BYTE = 0x00002C80ull;
+
+static const uint64_t P9N2_PERV_ROOT_CTRL0_SET_SCOM = 0x00050120ull;
+
+static const uint64_t P9N2_PERV_PIB_ROOT_CTRL0_SET = 0x00050120ull;
+
+
+static const uint32_t P9N2_PERV_ROOT_CTRL1_FSI = 0x00002811ull;
+
+static const uint32_t P9N2_PERV_ROOT_CTRL1_FSI_BYTE = 0x00002844ull;
+
+static const uint64_t P9N2_PERV_ROOT_CTRL1_SCOM = 0x00050011ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_PERV_PIB_ROOT_CTRL1 = 0x00050011ull;
+
+
+static const uint32_t P9N2_PERV_ROOT_CTRL1_CLEAR_FSI = 0x00002931ull;
+
+static const uint32_t P9N2_PERV_ROOT_CTRL1_CLEAR_FSI_BYTE = 0x00002CC4ull;
+
+static const uint64_t P9N2_PERV_ROOT_CTRL1_CLEAR_SCOM = 0x00050131ull;
+
+static const uint64_t P9N2_PERV_PIB_ROOT_CTRL1_CLEAR = 0x00050131ull;
+
+
+static const uint32_t P9N2_PERV_ROOT_CTRL1_COPY_FSI = 0x00002911ull;
+
+static const uint32_t P9N2_PERV_ROOT_CTRL1_COPY_FSI_BYTE = 0x00002C44ull;
+
+static const uint64_t P9N2_PERV_ROOT_CTRL1_COPY_SCOM = 0x00050111ull;
+
+static const uint64_t P9N2_PERV_PIB_ROOT_CTRL1_COPY = 0x00050111ull;
+
+
+static const uint32_t P9N2_PERV_ROOT_CTRL1_SET_FSI = 0x00002921ull;
+
+static const uint32_t P9N2_PERV_ROOT_CTRL1_SET_FSI_BYTE = 0x00002C84ull;
+
+static const uint64_t P9N2_PERV_ROOT_CTRL1_SET_SCOM = 0x00050121ull;
+
+static const uint64_t P9N2_PERV_PIB_ROOT_CTRL1_SET = 0x00050121ull;
+
+
+static const uint32_t P9N2_PERV_ROOT_CTRL2_FSI = 0x00002812ull;
+
+static const uint32_t P9N2_PERV_ROOT_CTRL2_FSI_BYTE = 0x00002848ull;
+
+static const uint64_t P9N2_PERV_ROOT_CTRL2_SCOM = 0x00050012ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_PERV_PIB_ROOT_CTRL2 = 0x00050012ull;
+
+
+static const uint32_t P9N2_PERV_ROOT_CTRL2_CLEAR_FSI = 0x00002932ull;
+
+static const uint32_t P9N2_PERV_ROOT_CTRL2_CLEAR_FSI_BYTE = 0x00002CC8ull;
+
+static const uint64_t P9N2_PERV_ROOT_CTRL2_CLEAR_SCOM = 0x00050132ull;
+
+static const uint64_t P9N2_PERV_PIB_ROOT_CTRL2_CLEAR = 0x00050132ull;
+
+
+static const uint32_t P9N2_PERV_ROOT_CTRL2_COPY_FSI = 0x00002912ull;
+
+static const uint32_t P9N2_PERV_ROOT_CTRL2_COPY_FSI_BYTE = 0x00002C48ull;
+
+static const uint64_t P9N2_PERV_ROOT_CTRL2_COPY_SCOM = 0x00050112ull;
+
+static const uint64_t P9N2_PERV_PIB_ROOT_CTRL2_COPY = 0x00050112ull;
+
+
+static const uint32_t P9N2_PERV_ROOT_CTRL2_SET_FSI = 0x00002922ull;
+
+static const uint32_t P9N2_PERV_ROOT_CTRL2_SET_FSI_BYTE = 0x00002C88ull;
+
+static const uint64_t P9N2_PERV_ROOT_CTRL2_SET_SCOM = 0x00050122ull;
+
+static const uint64_t P9N2_PERV_PIB_ROOT_CTRL2_SET = 0x00050122ull;
+
+
+static const uint32_t P9N2_PERV_ROOT_CTRL3_FSI = 0x00002813ull;
+
+static const uint32_t P9N2_PERV_ROOT_CTRL3_FSI_BYTE = 0x0000284Cull;
+
+static const uint64_t P9N2_PERV_ROOT_CTRL3_SCOM = 0x00050013ull;
+
+static const uint64_t P9N2_PERV_PIB_ROOT_CTRL3 = 0x00050013ull;
+
+
+static const uint32_t P9N2_PERV_ROOT_CTRL3_CLEAR_FSI = 0x00002933ull;
+
+static const uint32_t P9N2_PERV_ROOT_CTRL3_CLEAR_FSI_BYTE = 0x00002CCCull;
+
+static const uint64_t P9N2_PERV_ROOT_CTRL3_CLEAR_SCOM = 0x00050133ull;
+
+static const uint64_t P9N2_PERV_PIB_ROOT_CTRL3_CLEAR = 0x00050133ull;
+
+
+static const uint32_t P9N2_PERV_ROOT_CTRL3_COPY_FSI = 0x00002913ull;
+
+static const uint32_t P9N2_PERV_ROOT_CTRL3_COPY_FSI_BYTE = 0x00002C4Cull;
+
+static const uint64_t P9N2_PERV_ROOT_CTRL3_COPY_SCOM = 0x00050113ull;
+
+static const uint64_t P9N2_PERV_PIB_ROOT_CTRL3_COPY = 0x00050113ull;
+
+
+static const uint32_t P9N2_PERV_ROOT_CTRL3_SET_FSI = 0x00002923ull;
+
+static const uint32_t P9N2_PERV_ROOT_CTRL3_SET_FSI_BYTE = 0x00002C8Cull;
+
+static const uint64_t P9N2_PERV_ROOT_CTRL3_SET_SCOM = 0x00050123ull;
+
+static const uint64_t P9N2_PERV_PIB_ROOT_CTRL3_SET = 0x00050123ull;
+
+
+static const uint32_t P9N2_PERV_ROOT_CTRL4_FSI = 0x00002814ull;
+
+static const uint32_t P9N2_PERV_ROOT_CTRL4_FSI_BYTE = 0x00002850ull;
+
+static const uint64_t P9N2_PERV_ROOT_CTRL4_SCOM = 0x00050014ull;
+
+static const uint64_t P9N2_PERV_PIB_ROOT_CTRL4 = 0x00050014ull;
+
+
+static const uint32_t P9N2_PERV_ROOT_CTRL4_CLEAR_FSI = 0x00002934ull;
+
+static const uint32_t P9N2_PERV_ROOT_CTRL4_CLEAR_FSI_BYTE = 0x00002CD0ull;
+
+static const uint64_t P9N2_PERV_ROOT_CTRL4_CLEAR_SCOM = 0x00050134ull;
+
+static const uint64_t P9N2_PERV_PIB_ROOT_CTRL4_CLEAR = 0x00050134ull;
+
+
+static const uint32_t P9N2_PERV_ROOT_CTRL4_COPY_FSI = 0x00002914ull;
+
+static const uint32_t P9N2_PERV_ROOT_CTRL4_COPY_FSI_BYTE = 0x00002C50ull;
+
+static const uint64_t P9N2_PERV_ROOT_CTRL4_COPY_SCOM = 0x00050114ull;
+
+static const uint64_t P9N2_PERV_PIB_ROOT_CTRL4_COPY = 0x00050114ull;
+
+
+static const uint32_t P9N2_PERV_ROOT_CTRL4_SET_FSI = 0x00002924ull;
+
+static const uint32_t P9N2_PERV_ROOT_CTRL4_SET_FSI_BYTE = 0x00002C90ull;
+
+static const uint64_t P9N2_PERV_ROOT_CTRL4_SET_SCOM = 0x00050124ull;
+
+static const uint64_t P9N2_PERV_PIB_ROOT_CTRL4_SET = 0x00050124ull;
+
+
+static const uint32_t P9N2_PERV_ROOT_CTRL5_FSI = 0x00002815ull;
+
+static const uint32_t P9N2_PERV_ROOT_CTRL5_FSI_BYTE = 0x00002854ull;
+
+static const uint64_t P9N2_PERV_ROOT_CTRL5_SCOM = 0x00050015ull;
+
+static const uint64_t P9N2_PERV_PIB_ROOT_CTRL5 = 0x00050015ull;
+
+
+static const uint32_t P9N2_PERV_ROOT_CTRL5_CLEAR_FSI = 0x00002935ull;
+
+static const uint32_t P9N2_PERV_ROOT_CTRL5_CLEAR_FSI_BYTE = 0x00002CD4ull;
+
+static const uint64_t P9N2_PERV_ROOT_CTRL5_CLEAR_SCOM = 0x00050135ull;
+
+static const uint64_t P9N2_PERV_PIB_ROOT_CTRL5_CLEAR = 0x00050135ull;
+
+
+static const uint32_t P9N2_PERV_ROOT_CTRL5_COPY_FSI = 0x00002915ull;
+
+static const uint32_t P9N2_PERV_ROOT_CTRL5_COPY_FSI_BYTE = 0x00002C54ull;
+
+static const uint64_t P9N2_PERV_ROOT_CTRL5_COPY_SCOM = 0x00050115ull;
+
+static const uint64_t P9N2_PERV_PIB_ROOT_CTRL5_COPY = 0x00050115ull;
+
+
+static const uint32_t P9N2_PERV_ROOT_CTRL5_SET_FSI = 0x00002925ull;
+
+static const uint32_t P9N2_PERV_ROOT_CTRL5_SET_FSI_BYTE = 0x00002C94ull;
+
+static const uint64_t P9N2_PERV_ROOT_CTRL5_SET_SCOM = 0x00050125ull;
+
+static const uint64_t P9N2_PERV_PIB_ROOT_CTRL5_SET = 0x00050125ull;
+
+
+static const uint32_t P9N2_PERV_ROOT_CTRL6_FSI = 0x00002816ull;
+
+static const uint32_t P9N2_PERV_ROOT_CTRL6_FSI_BYTE = 0x00002858ull;
+
+static const uint64_t P9N2_PERV_ROOT_CTRL6_SCOM = 0x00050016ull;
+
+static const uint64_t P9N2_PERV_PIB_ROOT_CTRL6 = 0x00050016ull;
+
+
+static const uint32_t P9N2_PERV_ROOT_CTRL6_CLEAR_FSI = 0x00002936ull;
+
+static const uint32_t P9N2_PERV_ROOT_CTRL6_CLEAR_FSI_BYTE = 0x00002CD8ull;
+
+static const uint64_t P9N2_PERV_ROOT_CTRL6_CLEAR_SCOM = 0x00050136ull;
+
+static const uint64_t P9N2_PERV_PIB_ROOT_CTRL6_CLEAR = 0x00050136ull;
+
+
+static const uint32_t P9N2_PERV_ROOT_CTRL6_COPY_FSI = 0x00002916ull;
+
+static const uint32_t P9N2_PERV_ROOT_CTRL6_COPY_FSI_BYTE = 0x00002C58ull;
+
+static const uint64_t P9N2_PERV_ROOT_CTRL6_COPY_SCOM = 0x00050116ull;
+
+static const uint64_t P9N2_PERV_PIB_ROOT_CTRL6_COPY = 0x00050116ull;
+
+
+static const uint32_t P9N2_PERV_ROOT_CTRL6_SET_FSI = 0x00002926ull;
+
+static const uint32_t P9N2_PERV_ROOT_CTRL6_SET_FSI_BYTE = 0x00002C98ull;
+
+static const uint64_t P9N2_PERV_ROOT_CTRL6_SET_SCOM = 0x00050126ull;
+
+static const uint64_t P9N2_PERV_PIB_ROOT_CTRL6_SET = 0x00050126ull;
+
+
+static const uint32_t P9N2_PERV_ROOT_CTRL7_FSI = 0x00002817ull;
+
+static const uint32_t P9N2_PERV_ROOT_CTRL7_FSI_BYTE = 0x0000285Cull;
+
+static const uint64_t P9N2_PERV_ROOT_CTRL7_SCOM = 0x00050017ull;
+
+static const uint64_t P9N2_PERV_PIB_ROOT_CTRL7 = 0x00050017ull;
+
+
+static const uint32_t P9N2_PERV_ROOT_CTRL7_CLEAR_FSI = 0x00002937ull;
+
+static const uint32_t P9N2_PERV_ROOT_CTRL7_CLEAR_FSI_BYTE = 0x00002CDCull;
+
+static const uint64_t P9N2_PERV_ROOT_CTRL7_CLEAR_SCOM = 0x00050137ull;
+
+static const uint64_t P9N2_PERV_PIB_ROOT_CTRL7_CLEAR = 0x00050137ull;
+
+
+static const uint32_t P9N2_PERV_ROOT_CTRL7_COPY_FSI = 0x00002917ull;
+
+static const uint32_t P9N2_PERV_ROOT_CTRL7_COPY_FSI_BYTE = 0x00002C5Cull;
+
+static const uint64_t P9N2_PERV_ROOT_CTRL7_COPY_SCOM = 0x00050117ull;
+
+static const uint64_t P9N2_PERV_PIB_ROOT_CTRL7_COPY = 0x00050117ull;
+
+
+static const uint32_t P9N2_PERV_ROOT_CTRL7_SET_FSI = 0x00002927ull;
+
+static const uint32_t P9N2_PERV_ROOT_CTRL7_SET_FSI_BYTE = 0x00002C9Cull;
+
+static const uint64_t P9N2_PERV_ROOT_CTRL7_SET_SCOM = 0x00050127ull;
+
+static const uint64_t P9N2_PERV_PIB_ROOT_CTRL7_SET = 0x00050127ull;
+
+
+static const uint32_t P9N2_PERV_ROOT_CTRL8_FSI = 0x00002818ull;
+
+static const uint32_t P9N2_PERV_ROOT_CTRL8_FSI_BYTE = 0x00002860ull;
+
+static const uint64_t P9N2_PERV_ROOT_CTRL8_SCOM = 0x00050018ull;
+
+static const uint64_t P9N2_PERV_PIB_ROOT_CTRL8 = 0x00050018ull;
+
+
+static const uint32_t P9N2_PERV_ROOT_CTRL8_CLEAR_FSI = 0x00002938ull;
+
+static const uint32_t P9N2_PERV_ROOT_CTRL8_CLEAR_FSI_BYTE = 0x00002CE0ull;
+
+static const uint64_t P9N2_PERV_ROOT_CTRL8_CLEAR_SCOM = 0x00050138ull;
+
+static const uint64_t P9N2_PERV_PIB_ROOT_CTRL8_CLEAR = 0x00050138ull;
+
+
+static const uint32_t P9N2_PERV_ROOT_CTRL8_COPY_FSI = 0x00002918ull;
+
+static const uint32_t P9N2_PERV_ROOT_CTRL8_COPY_FSI_BYTE = 0x00002C60ull;
+
+static const uint64_t P9N2_PERV_ROOT_CTRL8_COPY_SCOM = 0x00050118ull;
+
+static const uint64_t P9N2_PERV_PIB_ROOT_CTRL8_COPY = 0x00050118ull;
+
+
+static const uint32_t P9N2_PERV_ROOT_CTRL8_SET_FSI = 0x00002928ull;
+
+static const uint32_t P9N2_PERV_ROOT_CTRL8_SET_FSI_BYTE = 0x00002CA0ull;
+
+static const uint64_t P9N2_PERV_ROOT_CTRL8_SET_SCOM = 0x00050128ull;
+
+static const uint64_t P9N2_PERV_PIB_ROOT_CTRL8_SET = 0x00050128ull;
+
+
+static const uint64_t P9N2_PERV_RSIC = 0x00030008ull;
+
+static const uint64_t P9N2_PERV_PIB_RSIC = 0x00030008ull;
+
+static const uint64_t P9N2_PERV_0_PIB2OPB0_RSIC = 0x00020008ull;
+
+static const uint64_t P9N2_PERV_0_PIB2OPB1_RSIC = 0x00020018ull;
+
+static const uint64_t P9N2_PERV_PIB2OPB0_RSIC = 0x00020008ull;
+
+static const uint64_t P9N2_PERV_PIB2OPB1_RSIC = 0x00020018ull;
+
+
+static const uint64_t P9N2_PERV_RSIM = 0x00030009ull;
+
+static const uint64_t P9N2_PERV_PIB_RSIM = 0x00030009ull;
+
+static const uint64_t P9N2_PERV_0_PIB2OPB0_RSIM = 0x00020009ull;
+
+static const uint64_t P9N2_PERV_0_PIB2OPB1_RSIM = 0x00020019ull;
+
+static const uint64_t P9N2_PERV_PIB2OPB0_RSIM = 0x00020009ull;
+
+static const uint64_t P9N2_PERV_PIB2OPB1_RSIM = 0x00020019ull;
+
+
+static const uint64_t P9N2_PERV_RSIS = 0x0003000Aull;
+
+static const uint64_t P9N2_PERV_PIB_RSIS = 0x0003000Aull;
+
+static const uint64_t P9N2_PERV_0_PIB2OPB0_RSIS = 0x0002000Aull;
+
+static const uint64_t P9N2_PERV_0_PIB2OPB1_RSIS = 0x0002001Aull;
+
+static const uint64_t P9N2_PERV_PIB2OPB0_RSIS = 0x0002000Aull;
+
+static const uint64_t P9N2_PERV_PIB2OPB1_RSIS = 0x0002001Aull;
+
+
+static const uint64_t P9N2_PERV_SBE_LCL_DBG_PPE = 0x00000120ull;
+
+
+static const uint64_t P9N2_PERV_SBE_LCL_EIMR_PPE = 0x00000020ull;
+
+static const uint64_t P9N2_PERV_SBE_LCL_EIMR_PPE1 = 0x00000030ull;
+
+static const uint64_t P9N2_PERV_SBE_LCL_EIMR_PPE2 = 0x00000038ull;
+
+
+static const uint64_t P9N2_PERV_SBE_LCL_EINR_PPE = 0x000000A0ull;
+
+
+static const uint64_t P9N2_PERV_SBE_LCL_EIPR_PPE = 0x00000040ull;
+
+static const uint64_t P9N2_PERV_SBE_LCL_EIPR_PPE1 = 0x00000050ull;
+
+static const uint64_t P9N2_PERV_SBE_LCL_EIPR_PPE2 = 0x00000058ull;
+
+
+static const uint64_t P9N2_PERV_SBE_LCL_EISR_PPE = 0x00000000ull;
+
+static const uint64_t P9N2_PERV_SBE_LCL_EISR_PPE1 = 0x00000010ull;
+
+static const uint64_t P9N2_PERV_SBE_LCL_EISR_PPE2 = 0x00000018ull;
+
+
+static const uint64_t P9N2_PERV_SBE_LCL_EISTR_PPE = 0x00000080ull;
+
+
+static const uint64_t P9N2_PERV_SBE_LCL_EITR_PPE = 0x00000060ull;
+
+static const uint64_t P9N2_PERV_SBE_LCL_EITR_PPE1 = 0x00000070ull;
+
+static const uint64_t P9N2_PERV_SBE_LCL_EITR_PPE2 = 0x00000078ull;
+
+
+static const uint64_t P9N2_PERV_SBE_LCL_IVPR_PPE = 0x00000160ull;
+
+
+static const uint64_t P9N2_PERV_SBE_LCL_TBR_PPE = 0x00000140ull;
+
+
+static const uint64_t P9N2_PERV_SBE_LCL_TSEL_PPE = 0x00000100ull;
+
+
+static const uint32_t P9N2_PERV_SB_CS_FSI = 0x00002808ull;
+
+static const uint32_t P9N2_PERV_SB_CS_FSI_BYTE = 0x00002820ull;
+
+static const uint64_t P9N2_PERV_SB_CS_SCOM = 0x00050008ull;
+
+static const uint64_t P9N2_PERV_PIB_SB_CS = 0x00050008ull;
+
+
+static const uint32_t P9N2_PERV_SB_MSG_FSI = 0x00002809ull;
+
+static const uint32_t P9N2_PERV_SB_MSG_FSI_BYTE = 0x00002824ull;
+
+static const uint64_t P9N2_PERV_SB_MSG_SCOM = 0x00050009ull;
+
+static const uint64_t P9N2_PERV_PIB_SB_MSG = 0x00050009ull;
+
+
+static const uint64_t P9N2_PERV_SCAN32 = 0x00038000ull;
+
+static const uint64_t P9N2_PERV_TP_SCAN32 = 0x01038000ull;
+
+static const uint64_t P9N2_PERV_N0_SCAN32 = 0x02038000ull;
+
+static const uint64_t P9N2_PERV_N1_SCAN32 = 0x03038000ull;
+
+static const uint64_t P9N2_PERV_N2_SCAN32 = 0x04038000ull;
+
+static const uint64_t P9N2_PERV_N3_SCAN32 = 0x05038000ull;
+
+static const uint64_t P9N2_PERV_XB_SCAN32 = 0x06038000ull;
+
+static const uint64_t P9N2_PERV_MC01_SCAN32 = 0x07038000ull;
+
+static const uint64_t P9N2_PERV_MC23_SCAN32 = 0x08038000ull;
+
+static const uint64_t P9N2_PERV_OB0_SCAN32 = 0x09038000ull;
+
+static const uint64_t P9N2_PERV_OB3_SCAN32 = 0x0C038000ull;
+
+static const uint64_t P9N2_PERV_PCI0_SCAN32 = 0x0D038000ull;
+
+static const uint64_t P9N2_PERV_PCI1_SCAN32 = 0x0E038000ull;
+
+static const uint64_t P9N2_PERV_PCI2_SCAN32 = 0x0F038000ull;
+
+static const uint64_t P9N2_PERV_EP00_SCAN32 = 0x10038000ull;
+
+static const uint64_t P9N2_PERV_EP01_SCAN32 = 0x11038000ull;
+
+static const uint64_t P9N2_PERV_EP02_SCAN32 = 0x12038000ull;
+
+static const uint64_t P9N2_PERV_EP03_SCAN32 = 0x13038000ull;
+
+static const uint64_t P9N2_PERV_EP04_SCAN32 = 0x14038000ull;
+
+static const uint64_t P9N2_PERV_EP05_SCAN32 = 0x15038000ull;
+
+static const uint64_t P9N2_PERV_EC00_SCAN32 = 0x20038000ull;
+
+static const uint64_t P9N2_PERV_EC01_SCAN32 = 0x21038000ull;
+
+static const uint64_t P9N2_PERV_EC02_SCAN32 = 0x22038000ull;
+
+static const uint64_t P9N2_PERV_EC03_SCAN32 = 0x23038000ull;
+
+static const uint64_t P9N2_PERV_EC04_SCAN32 = 0x24038000ull;
+
+static const uint64_t P9N2_PERV_EC05_SCAN32 = 0x25038000ull;
+
+static const uint64_t P9N2_PERV_EC06_SCAN32 = 0x26038000ull;
+
+static const uint64_t P9N2_PERV_EC07_SCAN32 = 0x27038000ull;
+
+static const uint64_t P9N2_PERV_EC08_SCAN32 = 0x28038000ull;
+
+static const uint64_t P9N2_PERV_EC09_SCAN32 = 0x29038000ull;
+
+static const uint64_t P9N2_PERV_EC10_SCAN32 = 0x2A038000ull;
+
+static const uint64_t P9N2_PERV_EC11_SCAN32 = 0x2B038000ull;
+
+static const uint64_t P9N2_PERV_EC12_SCAN32 = 0x2C038000ull;
+
+static const uint64_t P9N2_PERV_EC13_SCAN32 = 0x2D038000ull;
+
+static const uint64_t P9N2_PERV_EC14_SCAN32 = 0x2E038000ull;
+
+static const uint64_t P9N2_PERV_EC15_SCAN32 = 0x2F038000ull;
+
+static const uint64_t P9N2_PERV_EC16_SCAN32 = 0x30038000ull;
+
+static const uint64_t P9N2_PERV_EC17_SCAN32 = 0x31038000ull;
+
+static const uint64_t P9N2_PERV_EC18_SCAN32 = 0x32038000ull;
+
+static const uint64_t P9N2_PERV_EC19_SCAN32 = 0x33038000ull;
+
+static const uint64_t P9N2_PERV_EC20_SCAN32 = 0x34038000ull;
+
+static const uint64_t P9N2_PERV_EC21_SCAN32 = 0x35038000ull;
+
+static const uint64_t P9N2_PERV_EC22_SCAN32 = 0x36038000ull;
+
+static const uint64_t P9N2_PERV_EC23_SCAN32 = 0x37038000ull;
+
+
+static const uint64_t P9N2_PERV_SCAN64 = 0x0003E000ull;
+
+static const uint64_t P9N2_PERV_TP_SCAN64 = 0x0103E000ull;
+
+static const uint64_t P9N2_PERV_N0_SCAN64 = 0x0203E000ull;
+
+static const uint64_t P9N2_PERV_N1_SCAN64 = 0x0303E000ull;
+
+static const uint64_t P9N2_PERV_N2_SCAN64 = 0x0403E000ull;
+
+static const uint64_t P9N2_PERV_N3_SCAN64 = 0x0503E000ull;
+
+static const uint64_t P9N2_PERV_XB_SCAN64 = 0x0603E000ull;
+
+static const uint64_t P9N2_PERV_MC01_SCAN64 = 0x0703E000ull;
+
+static const uint64_t P9N2_PERV_MC23_SCAN64 = 0x0803E000ull;
+
+static const uint64_t P9N2_PERV_OB0_SCAN64 = 0x0903E000ull;
+
+static const uint64_t P9N2_PERV_OB3_SCAN64 = 0x0C03E000ull;
+
+static const uint64_t P9N2_PERV_PCI0_SCAN64 = 0x0D03E000ull;
+
+static const uint64_t P9N2_PERV_PCI1_SCAN64 = 0x0E03E000ull;
+
+static const uint64_t P9N2_PERV_PCI2_SCAN64 = 0x0F03E000ull;
+
+static const uint64_t P9N2_PERV_EP00_SCAN64 = 0x1003E000ull;
+
+static const uint64_t P9N2_PERV_EP01_SCAN64 = 0x1103E000ull;
+
+static const uint64_t P9N2_PERV_EP02_SCAN64 = 0x1203E000ull;
+
+static const uint64_t P9N2_PERV_EP03_SCAN64 = 0x1303E000ull;
+
+static const uint64_t P9N2_PERV_EP04_SCAN64 = 0x1403E000ull;
+
+static const uint64_t P9N2_PERV_EP05_SCAN64 = 0x1503E000ull;
+
+static const uint64_t P9N2_PERV_EC00_SCAN64 = 0x2003E000ull;
+
+static const uint64_t P9N2_PERV_EC01_SCAN64 = 0x2103E000ull;
+
+static const uint64_t P9N2_PERV_EC02_SCAN64 = 0x2203E000ull;
+
+static const uint64_t P9N2_PERV_EC03_SCAN64 = 0x2303E000ull;
+
+static const uint64_t P9N2_PERV_EC04_SCAN64 = 0x2403E000ull;
+
+static const uint64_t P9N2_PERV_EC05_SCAN64 = 0x2503E000ull;
+
+static const uint64_t P9N2_PERV_EC06_SCAN64 = 0x2603E000ull;
+
+static const uint64_t P9N2_PERV_EC07_SCAN64 = 0x2703E000ull;
+
+static const uint64_t P9N2_PERV_EC08_SCAN64 = 0x2803E000ull;
+
+static const uint64_t P9N2_PERV_EC09_SCAN64 = 0x2903E000ull;
+
+static const uint64_t P9N2_PERV_EC10_SCAN64 = 0x2A03E000ull;
+
+static const uint64_t P9N2_PERV_EC11_SCAN64 = 0x2B03E000ull;
+
+static const uint64_t P9N2_PERV_EC12_SCAN64 = 0x2C03E000ull;
+
+static const uint64_t P9N2_PERV_EC13_SCAN64 = 0x2D03E000ull;
+
+static const uint64_t P9N2_PERV_EC14_SCAN64 = 0x2E03E000ull;
+
+static const uint64_t P9N2_PERV_EC15_SCAN64 = 0x2F03E000ull;
+
+static const uint64_t P9N2_PERV_EC16_SCAN64 = 0x3003E000ull;
+
+static const uint64_t P9N2_PERV_EC17_SCAN64 = 0x3103E000ull;
+
+static const uint64_t P9N2_PERV_EC18_SCAN64 = 0x3203E000ull;
+
+static const uint64_t P9N2_PERV_EC19_SCAN64 = 0x3303E000ull;
+
+static const uint64_t P9N2_PERV_EC20_SCAN64 = 0x3403E000ull;
+
+static const uint64_t P9N2_PERV_EC21_SCAN64 = 0x3503E000ull;
+
+static const uint64_t P9N2_PERV_EC22_SCAN64 = 0x3603E000ull;
+
+static const uint64_t P9N2_PERV_EC23_SCAN64 = 0x3703E000ull;
+
+
+static const uint64_t P9N2_PERV_SCAN_CAPTUREDR = 0x0003C000ull;
+
+static const uint64_t P9N2_PERV_TP_SCAN_CAPTUREDR = 0x0103C000ull;
+
+static const uint64_t P9N2_PERV_N0_SCAN_CAPTUREDR = 0x0203C000ull;
+
+static const uint64_t P9N2_PERV_N1_SCAN_CAPTUREDR = 0x0303C000ull;
+
+static const uint64_t P9N2_PERV_N2_SCAN_CAPTUREDR = 0x0403C000ull;
+
+static const uint64_t P9N2_PERV_N3_SCAN_CAPTUREDR = 0x0503C000ull;
+
+static const uint64_t P9N2_PERV_XB_SCAN_CAPTUREDR = 0x0603C000ull;
+
+static const uint64_t P9N2_PERV_MC01_SCAN_CAPTUREDR = 0x0703C000ull;
+
+static const uint64_t P9N2_PERV_MC23_SCAN_CAPTUREDR = 0x0803C000ull;
+
+static const uint64_t P9N2_PERV_OB0_SCAN_CAPTUREDR = 0x0903C000ull;
+
+static const uint64_t P9N2_PERV_OB3_SCAN_CAPTUREDR = 0x0C03C000ull;
+
+static const uint64_t P9N2_PERV_PCI0_SCAN_CAPTUREDR = 0x0D03C000ull;
+
+static const uint64_t P9N2_PERV_PCI1_SCAN_CAPTUREDR = 0x0E03C000ull;
+
+static const uint64_t P9N2_PERV_PCI2_SCAN_CAPTUREDR = 0x0F03C000ull;
+
+static const uint64_t P9N2_PERV_EP00_SCAN_CAPTUREDR = 0x1003C000ull;
+
+static const uint64_t P9N2_PERV_EP01_SCAN_CAPTUREDR = 0x1103C000ull;
+
+static const uint64_t P9N2_PERV_EP02_SCAN_CAPTUREDR = 0x1203C000ull;
+
+static const uint64_t P9N2_PERV_EP03_SCAN_CAPTUREDR = 0x1303C000ull;
+
+static const uint64_t P9N2_PERV_EP04_SCAN_CAPTUREDR = 0x1403C000ull;
+
+static const uint64_t P9N2_PERV_EP05_SCAN_CAPTUREDR = 0x1503C000ull;
+
+static const uint64_t P9N2_PERV_EC00_SCAN_CAPTUREDR = 0x2003C000ull;
+
+static const uint64_t P9N2_PERV_EC01_SCAN_CAPTUREDR = 0x2103C000ull;
+
+static const uint64_t P9N2_PERV_EC02_SCAN_CAPTUREDR = 0x2203C000ull;
+
+static const uint64_t P9N2_PERV_EC03_SCAN_CAPTUREDR = 0x2303C000ull;
+
+static const uint64_t P9N2_PERV_EC04_SCAN_CAPTUREDR = 0x2403C000ull;
+
+static const uint64_t P9N2_PERV_EC05_SCAN_CAPTUREDR = 0x2503C000ull;
+
+static const uint64_t P9N2_PERV_EC06_SCAN_CAPTUREDR = 0x2603C000ull;
+
+static const uint64_t P9N2_PERV_EC07_SCAN_CAPTUREDR = 0x2703C000ull;
+
+static const uint64_t P9N2_PERV_EC08_SCAN_CAPTUREDR = 0x2803C000ull;
+
+static const uint64_t P9N2_PERV_EC09_SCAN_CAPTUREDR = 0x2903C000ull;
+
+static const uint64_t P9N2_PERV_EC10_SCAN_CAPTUREDR = 0x2A03C000ull;
+
+static const uint64_t P9N2_PERV_EC11_SCAN_CAPTUREDR = 0x2B03C000ull;
+
+static const uint64_t P9N2_PERV_EC12_SCAN_CAPTUREDR = 0x2C03C000ull;
+
+static const uint64_t P9N2_PERV_EC13_SCAN_CAPTUREDR = 0x2D03C000ull;
+
+static const uint64_t P9N2_PERV_EC14_SCAN_CAPTUREDR = 0x2E03C000ull;
+
+static const uint64_t P9N2_PERV_EC15_SCAN_CAPTUREDR = 0x2F03C000ull;
+
+static const uint64_t P9N2_PERV_EC16_SCAN_CAPTUREDR = 0x3003C000ull;
+
+static const uint64_t P9N2_PERV_EC17_SCAN_CAPTUREDR = 0x3103C000ull;
+
+static const uint64_t P9N2_PERV_EC18_SCAN_CAPTUREDR = 0x3203C000ull;
+
+static const uint64_t P9N2_PERV_EC19_SCAN_CAPTUREDR = 0x3303C000ull;
+
+static const uint64_t P9N2_PERV_EC20_SCAN_CAPTUREDR = 0x3403C000ull;
+
+static const uint64_t P9N2_PERV_EC21_SCAN_CAPTUREDR = 0x3503C000ull;
+
+static const uint64_t P9N2_PERV_EC22_SCAN_CAPTUREDR = 0x3603C000ull;
+
+static const uint64_t P9N2_PERV_EC23_SCAN_CAPTUREDR = 0x3703C000ull;
+
+
+static const uint64_t P9N2_PERV_12_FSI2PIB_SCAN_CAPTUREDR_LONG = 0x0C03D000ull;
+
+static const uint64_t P9N2_PERV_13_FSI2PIB_SCAN_CAPTUREDR_LONG = 0x0D03D000ull;
+
+static const uint64_t P9N2_PERV_14_FSI2PIB_SCAN_CAPTUREDR_LONG = 0x0E03D000ull;
+
+static const uint64_t P9N2_PERV_15_FSI2PIB_SCAN_CAPTUREDR_LONG = 0x0F03D000ull;
+
+static const uint64_t P9N2_PERV_16_FSI2PIB_SCAN_CAPTUREDR_LONG = 0x1003D000ull;
+
+static const uint64_t P9N2_PERV_17_FSI2PIB_SCAN_CAPTUREDR_LONG = 0x1103D000ull;
+
+static const uint64_t P9N2_PERV_18_FSI2PIB_SCAN_CAPTUREDR_LONG = 0x1203D000ull;
+
+static const uint64_t P9N2_PERV_19_FSI2PIB_SCAN_CAPTUREDR_LONG = 0x1303D000ull;
+
+static const uint64_t P9N2_PERV_1_FSI2PIB_SCAN_CAPTUREDR_LONG = 0x0103D000ull;
+
+static const uint64_t P9N2_PERV_20_FSI2PIB_SCAN_CAPTUREDR_LONG = 0x1403D000ull;
+
+static const uint64_t P9N2_PERV_21_FSI2PIB_SCAN_CAPTUREDR_LONG = 0x1503D000ull;
+
+static const uint64_t P9N2_PERV_2_FSI2PIB_SCAN_CAPTUREDR_LONG = 0x0203D000ull;
+
+static const uint64_t P9N2_PERV_32_FSI2PIB_SCAN_CAPTUREDR_LONG = 0x2003D000ull;
+
+static const uint64_t P9N2_PERV_33_FSI2PIB_SCAN_CAPTUREDR_LONG = 0x2103D000ull;
+
+static const uint64_t P9N2_PERV_34_FSI2PIB_SCAN_CAPTUREDR_LONG = 0x2203D000ull;
+
+static const uint64_t P9N2_PERV_35_FSI2PIB_SCAN_CAPTUREDR_LONG = 0x2303D000ull;
+
+static const uint64_t P9N2_PERV_36_FSI2PIB_SCAN_CAPTUREDR_LONG = 0x2403D000ull;
+
+static const uint64_t P9N2_PERV_37_FSI2PIB_SCAN_CAPTUREDR_LONG = 0x2503D000ull;
+
+static const uint64_t P9N2_PERV_38_FSI2PIB_SCAN_CAPTUREDR_LONG = 0x2603D000ull;
+
+static const uint64_t P9N2_PERV_39_FSI2PIB_SCAN_CAPTUREDR_LONG = 0x2703D000ull;
+
+static const uint64_t P9N2_PERV_3_FSI2PIB_SCAN_CAPTUREDR_LONG = 0x0303D000ull;
+
+static const uint64_t P9N2_PERV_40_FSI2PIB_SCAN_CAPTUREDR_LONG = 0x2803D000ull;
+
+static const uint64_t P9N2_PERV_41_FSI2PIB_SCAN_CAPTUREDR_LONG = 0x2903D000ull;
+
+static const uint64_t P9N2_PERV_42_FSI2PIB_SCAN_CAPTUREDR_LONG = 0x2A03D000ull;
+
+static const uint64_t P9N2_PERV_43_FSI2PIB_SCAN_CAPTUREDR_LONG = 0x2B03D000ull;
+
+static const uint64_t P9N2_PERV_44_FSI2PIB_SCAN_CAPTUREDR_LONG = 0x2C03D000ull;
+
+static const uint64_t P9N2_PERV_45_FSI2PIB_SCAN_CAPTUREDR_LONG = 0x2D03D000ull;
+
+static const uint64_t P9N2_PERV_46_FSI2PIB_SCAN_CAPTUREDR_LONG = 0x2E03D000ull;
+
+static const uint64_t P9N2_PERV_47_FSI2PIB_SCAN_CAPTUREDR_LONG = 0x2F03D000ull;
+
+static const uint64_t P9N2_PERV_48_FSI2PIB_SCAN_CAPTUREDR_LONG = 0x3003D000ull;
+
+static const uint64_t P9N2_PERV_49_FSI2PIB_SCAN_CAPTUREDR_LONG = 0x3103D000ull;
+
+static const uint64_t P9N2_PERV_4_FSI2PIB_SCAN_CAPTUREDR_LONG = 0x0403D000ull;
+
+static const uint64_t P9N2_PERV_50_FSI2PIB_SCAN_CAPTUREDR_LONG = 0x3203D000ull;
+
+static const uint64_t P9N2_PERV_51_FSI2PIB_SCAN_CAPTUREDR_LONG = 0x3303D000ull;
+
+static const uint64_t P9N2_PERV_52_FSI2PIB_SCAN_CAPTUREDR_LONG = 0x3403D000ull;
+
+static const uint64_t P9N2_PERV_53_FSI2PIB_SCAN_CAPTUREDR_LONG = 0x3503D000ull;
+
+static const uint64_t P9N2_PERV_54_FSI2PIB_SCAN_CAPTUREDR_LONG = 0x3603D000ull;
+
+static const uint64_t P9N2_PERV_55_FSI2PIB_SCAN_CAPTUREDR_LONG = 0x3703D000ull;
+
+static const uint64_t P9N2_PERV_5_FSI2PIB_SCAN_CAPTUREDR_LONG = 0x0503D000ull;
+
+static const uint64_t P9N2_PERV_6_FSI2PIB_SCAN_CAPTUREDR_LONG = 0x0603D000ull;
+
+static const uint64_t P9N2_PERV_7_FSI2PIB_SCAN_CAPTUREDR_LONG = 0x0703D000ull;
+
+static const uint64_t P9N2_PERV_8_FSI2PIB_SCAN_CAPTUREDR_LONG = 0x0803D000ull;
+
+static const uint64_t P9N2_PERV_9_FSI2PIB_SCAN_CAPTUREDR_LONG = 0x0903D000ull;
+
+
+static const uint64_t P9N2_PERV_12_FSI2PIB_SCAN_LONG_ROTATE = 0x0C039000ull;
+
+static const uint64_t P9N2_PERV_13_FSI2PIB_SCAN_LONG_ROTATE = 0x0D039000ull;
+
+static const uint64_t P9N2_PERV_14_FSI2PIB_SCAN_LONG_ROTATE = 0x0E039000ull;
+
+static const uint64_t P9N2_PERV_15_FSI2PIB_SCAN_LONG_ROTATE = 0x0F039000ull;
+
+static const uint64_t P9N2_PERV_16_FSI2PIB_SCAN_LONG_ROTATE = 0x10039000ull;
+
+static const uint64_t P9N2_PERV_17_FSI2PIB_SCAN_LONG_ROTATE = 0x11039000ull;
+
+static const uint64_t P9N2_PERV_18_FSI2PIB_SCAN_LONG_ROTATE = 0x12039000ull;
+
+static const uint64_t P9N2_PERV_19_FSI2PIB_SCAN_LONG_ROTATE = 0x13039000ull;
+
+static const uint64_t P9N2_PERV_1_FSI2PIB_SCAN_LONG_ROTATE = 0x01039000ull;
+
+static const uint64_t P9N2_PERV_20_FSI2PIB_SCAN_LONG_ROTATE = 0x14039000ull;
+
+static const uint64_t P9N2_PERV_21_FSI2PIB_SCAN_LONG_ROTATE = 0x15039000ull;
+
+static const uint64_t P9N2_PERV_2_FSI2PIB_SCAN_LONG_ROTATE = 0x02039000ull;
+
+static const uint64_t P9N2_PERV_32_FSI2PIB_SCAN_LONG_ROTATE = 0x20039000ull;
+
+static const uint64_t P9N2_PERV_33_FSI2PIB_SCAN_LONG_ROTATE = 0x21039000ull;
+
+static const uint64_t P9N2_PERV_34_FSI2PIB_SCAN_LONG_ROTATE = 0x22039000ull;
+
+static const uint64_t P9N2_PERV_35_FSI2PIB_SCAN_LONG_ROTATE = 0x23039000ull;
+
+static const uint64_t P9N2_PERV_36_FSI2PIB_SCAN_LONG_ROTATE = 0x24039000ull;
+
+static const uint64_t P9N2_PERV_37_FSI2PIB_SCAN_LONG_ROTATE = 0x25039000ull;
+
+static const uint64_t P9N2_PERV_38_FSI2PIB_SCAN_LONG_ROTATE = 0x26039000ull;
+
+static const uint64_t P9N2_PERV_39_FSI2PIB_SCAN_LONG_ROTATE = 0x27039000ull;
+
+static const uint64_t P9N2_PERV_3_FSI2PIB_SCAN_LONG_ROTATE = 0x03039000ull;
+
+static const uint64_t P9N2_PERV_40_FSI2PIB_SCAN_LONG_ROTATE = 0x28039000ull;
+
+static const uint64_t P9N2_PERV_41_FSI2PIB_SCAN_LONG_ROTATE = 0x29039000ull;
+
+static const uint64_t P9N2_PERV_42_FSI2PIB_SCAN_LONG_ROTATE = 0x2A039000ull;
+
+static const uint64_t P9N2_PERV_43_FSI2PIB_SCAN_LONG_ROTATE = 0x2B039000ull;
+
+static const uint64_t P9N2_PERV_44_FSI2PIB_SCAN_LONG_ROTATE = 0x2C039000ull;
+
+static const uint64_t P9N2_PERV_45_FSI2PIB_SCAN_LONG_ROTATE = 0x2D039000ull;
+
+static const uint64_t P9N2_PERV_46_FSI2PIB_SCAN_LONG_ROTATE = 0x2E039000ull;
+
+static const uint64_t P9N2_PERV_47_FSI2PIB_SCAN_LONG_ROTATE = 0x2F039000ull;
+
+static const uint64_t P9N2_PERV_48_FSI2PIB_SCAN_LONG_ROTATE = 0x30039000ull;
+
+static const uint64_t P9N2_PERV_49_FSI2PIB_SCAN_LONG_ROTATE = 0x31039000ull;
+
+static const uint64_t P9N2_PERV_4_FSI2PIB_SCAN_LONG_ROTATE = 0x04039000ull;
+
+static const uint64_t P9N2_PERV_50_FSI2PIB_SCAN_LONG_ROTATE = 0x32039000ull;
+
+static const uint64_t P9N2_PERV_51_FSI2PIB_SCAN_LONG_ROTATE = 0x33039000ull;
+
+static const uint64_t P9N2_PERV_52_FSI2PIB_SCAN_LONG_ROTATE = 0x34039000ull;
+
+static const uint64_t P9N2_PERV_53_FSI2PIB_SCAN_LONG_ROTATE = 0x35039000ull;
+
+static const uint64_t P9N2_PERV_54_FSI2PIB_SCAN_LONG_ROTATE = 0x36039000ull;
+
+static const uint64_t P9N2_PERV_55_FSI2PIB_SCAN_LONG_ROTATE = 0x37039000ull;
+
+static const uint64_t P9N2_PERV_5_FSI2PIB_SCAN_LONG_ROTATE = 0x05039000ull;
+
+static const uint64_t P9N2_PERV_6_FSI2PIB_SCAN_LONG_ROTATE = 0x06039000ull;
+
+static const uint64_t P9N2_PERV_7_FSI2PIB_SCAN_LONG_ROTATE = 0x07039000ull;
+
+static const uint64_t P9N2_PERV_8_FSI2PIB_SCAN_LONG_ROTATE = 0x08039000ull;
+
+static const uint64_t P9N2_PERV_9_FSI2PIB_SCAN_LONG_ROTATE = 0x09039000ull;
+
+
+static const uint64_t P9N2_PERV_SCAN_REGION_TYPE = 0x00030005ull;
+
+static const uint64_t P9N2_PERV_TP_SCAN_REGION_TYPE = 0x01030005ull;
+
+static const uint64_t P9N2_PERV_N0_SCAN_REGION_TYPE = 0x02030005ull;
+
+static const uint64_t P9N2_PERV_N1_SCAN_REGION_TYPE = 0x03030005ull;
+
+static const uint64_t P9N2_PERV_N2_SCAN_REGION_TYPE = 0x04030005ull;
+
+static const uint64_t P9N2_PERV_N3_SCAN_REGION_TYPE = 0x05030005ull;
+
+static const uint64_t P9N2_PERV_XB_SCAN_REGION_TYPE = 0x06030005ull;
+
+static const uint64_t P9N2_PERV_MC01_SCAN_REGION_TYPE = 0x07030005ull;
+
+static const uint64_t P9N2_PERV_MC23_SCAN_REGION_TYPE = 0x08030005ull;
+
+static const uint64_t P9N2_PERV_OB0_SCAN_REGION_TYPE = 0x09030005ull;
+
+static const uint64_t P9N2_PERV_OB3_SCAN_REGION_TYPE = 0x0C030005ull;
+
+static const uint64_t P9N2_PERV_PCI0_SCAN_REGION_TYPE = 0x0D030005ull;
+
+static const uint64_t P9N2_PERV_PCI1_SCAN_REGION_TYPE = 0x0E030005ull;
+
+static const uint64_t P9N2_PERV_PCI2_SCAN_REGION_TYPE = 0x0F030005ull;
+
+static const uint64_t P9N2_PERV_EP00_SCAN_REGION_TYPE = 0x10030005ull;
+
+static const uint64_t P9N2_PERV_EP01_SCAN_REGION_TYPE = 0x11030005ull;
+
+static const uint64_t P9N2_PERV_EP02_SCAN_REGION_TYPE = 0x12030005ull;
+
+static const uint64_t P9N2_PERV_EP03_SCAN_REGION_TYPE = 0x13030005ull;
+
+static const uint64_t P9N2_PERV_EP04_SCAN_REGION_TYPE = 0x14030005ull;
+
+static const uint64_t P9N2_PERV_EP05_SCAN_REGION_TYPE = 0x15030005ull;
+
+static const uint64_t P9N2_PERV_EC00_SCAN_REGION_TYPE = 0x20030005ull;
+
+static const uint64_t P9N2_PERV_EC01_SCAN_REGION_TYPE = 0x21030005ull;
+
+static const uint64_t P9N2_PERV_EC02_SCAN_REGION_TYPE = 0x22030005ull;
+
+static const uint64_t P9N2_PERV_EC03_SCAN_REGION_TYPE = 0x23030005ull;
+
+static const uint64_t P9N2_PERV_EC04_SCAN_REGION_TYPE = 0x24030005ull;
+
+static const uint64_t P9N2_PERV_EC05_SCAN_REGION_TYPE = 0x25030005ull;
+
+static const uint64_t P9N2_PERV_EC06_SCAN_REGION_TYPE = 0x26030005ull;
+
+static const uint64_t P9N2_PERV_EC07_SCAN_REGION_TYPE = 0x27030005ull;
+
+static const uint64_t P9N2_PERV_EC08_SCAN_REGION_TYPE = 0x28030005ull;
+
+static const uint64_t P9N2_PERV_EC09_SCAN_REGION_TYPE = 0x29030005ull;
+
+static const uint64_t P9N2_PERV_EC10_SCAN_REGION_TYPE = 0x2A030005ull;
+
+static const uint64_t P9N2_PERV_EC11_SCAN_REGION_TYPE = 0x2B030005ull;
+
+static const uint64_t P9N2_PERV_EC12_SCAN_REGION_TYPE = 0x2C030005ull;
+
+static const uint64_t P9N2_PERV_EC13_SCAN_REGION_TYPE = 0x2D030005ull;
+
+static const uint64_t P9N2_PERV_EC14_SCAN_REGION_TYPE = 0x2E030005ull;
+
+static const uint64_t P9N2_PERV_EC15_SCAN_REGION_TYPE = 0x2F030005ull;
+
+static const uint64_t P9N2_PERV_EC16_SCAN_REGION_TYPE = 0x30030005ull;
+
+static const uint64_t P9N2_PERV_EC17_SCAN_REGION_TYPE = 0x31030005ull;
+
+static const uint64_t P9N2_PERV_EC18_SCAN_REGION_TYPE = 0x32030005ull;
+
+static const uint64_t P9N2_PERV_EC19_SCAN_REGION_TYPE = 0x33030005ull;
+
+static const uint64_t P9N2_PERV_EC20_SCAN_REGION_TYPE = 0x34030005ull;
+
+static const uint64_t P9N2_PERV_EC21_SCAN_REGION_TYPE = 0x35030005ull;
+
+static const uint64_t P9N2_PERV_EC22_SCAN_REGION_TYPE = 0x36030005ull;
+
+static const uint64_t P9N2_PERV_EC23_SCAN_REGION_TYPE = 0x37030005ull;
+
+
+static const uint64_t P9N2_PERV_SCAN_UPDATEDR = 0x0003A000ull;
+
+static const uint64_t P9N2_PERV_TP_SCAN_UPDATEDR = 0x0103A000ull;
+
+static const uint64_t P9N2_PERV_N0_SCAN_UPDATEDR = 0x0203A000ull;
+
+static const uint64_t P9N2_PERV_N1_SCAN_UPDATEDR = 0x0303A000ull;
+
+static const uint64_t P9N2_PERV_N2_SCAN_UPDATEDR = 0x0403A000ull;
+
+static const uint64_t P9N2_PERV_N3_SCAN_UPDATEDR = 0x0503A000ull;
+
+static const uint64_t P9N2_PERV_XB_SCAN_UPDATEDR = 0x0603A000ull;
+
+static const uint64_t P9N2_PERV_MC01_SCAN_UPDATEDR = 0x0703A000ull;
+
+static const uint64_t P9N2_PERV_MC23_SCAN_UPDATEDR = 0x0803A000ull;
+
+static const uint64_t P9N2_PERV_OB0_SCAN_UPDATEDR = 0x0903A000ull;
+
+static const uint64_t P9N2_PERV_OB3_SCAN_UPDATEDR = 0x0C03A000ull;
+
+static const uint64_t P9N2_PERV_PCI0_SCAN_UPDATEDR = 0x0D03A000ull;
+
+static const uint64_t P9N2_PERV_PCI1_SCAN_UPDATEDR = 0x0E03A000ull;
+
+static const uint64_t P9N2_PERV_PCI2_SCAN_UPDATEDR = 0x0F03A000ull;
+
+static const uint64_t P9N2_PERV_EP00_SCAN_UPDATEDR = 0x1003A000ull;
+
+static const uint64_t P9N2_PERV_EP01_SCAN_UPDATEDR = 0x1103A000ull;
+
+static const uint64_t P9N2_PERV_EP02_SCAN_UPDATEDR = 0x1203A000ull;
+
+static const uint64_t P9N2_PERV_EP03_SCAN_UPDATEDR = 0x1303A000ull;
+
+static const uint64_t P9N2_PERV_EP04_SCAN_UPDATEDR = 0x1403A000ull;
+
+static const uint64_t P9N2_PERV_EP05_SCAN_UPDATEDR = 0x1503A000ull;
+
+static const uint64_t P9N2_PERV_EC00_SCAN_UPDATEDR = 0x2003A000ull;
+
+static const uint64_t P9N2_PERV_EC01_SCAN_UPDATEDR = 0x2103A000ull;
+
+static const uint64_t P9N2_PERV_EC02_SCAN_UPDATEDR = 0x2203A000ull;
+
+static const uint64_t P9N2_PERV_EC03_SCAN_UPDATEDR = 0x2303A000ull;
+
+static const uint64_t P9N2_PERV_EC04_SCAN_UPDATEDR = 0x2403A000ull;
+
+static const uint64_t P9N2_PERV_EC05_SCAN_UPDATEDR = 0x2503A000ull;
+
+static const uint64_t P9N2_PERV_EC06_SCAN_UPDATEDR = 0x2603A000ull;
+
+static const uint64_t P9N2_PERV_EC07_SCAN_UPDATEDR = 0x2703A000ull;
+
+static const uint64_t P9N2_PERV_EC08_SCAN_UPDATEDR = 0x2803A000ull;
+
+static const uint64_t P9N2_PERV_EC09_SCAN_UPDATEDR = 0x2903A000ull;
+
+static const uint64_t P9N2_PERV_EC10_SCAN_UPDATEDR = 0x2A03A000ull;
+
+static const uint64_t P9N2_PERV_EC11_SCAN_UPDATEDR = 0x2B03A000ull;
+
+static const uint64_t P9N2_PERV_EC12_SCAN_UPDATEDR = 0x2C03A000ull;
+
+static const uint64_t P9N2_PERV_EC13_SCAN_UPDATEDR = 0x2D03A000ull;
+
+static const uint64_t P9N2_PERV_EC14_SCAN_UPDATEDR = 0x2E03A000ull;
+
+static const uint64_t P9N2_PERV_EC15_SCAN_UPDATEDR = 0x2F03A000ull;
+
+static const uint64_t P9N2_PERV_EC16_SCAN_UPDATEDR = 0x3003A000ull;
+
+static const uint64_t P9N2_PERV_EC17_SCAN_UPDATEDR = 0x3103A000ull;
+
+static const uint64_t P9N2_PERV_EC18_SCAN_UPDATEDR = 0x3203A000ull;
+
+static const uint64_t P9N2_PERV_EC19_SCAN_UPDATEDR = 0x3303A000ull;
+
+static const uint64_t P9N2_PERV_EC20_SCAN_UPDATEDR = 0x3403A000ull;
+
+static const uint64_t P9N2_PERV_EC21_SCAN_UPDATEDR = 0x3503A000ull;
+
+static const uint64_t P9N2_PERV_EC22_SCAN_UPDATEDR = 0x3603A000ull;
+
+static const uint64_t P9N2_PERV_EC23_SCAN_UPDATEDR = 0x3703A000ull;
+
+
+static const uint64_t P9N2_PERV_SCAN_UPDATEDR_LONG = 0x0003B000ull;
+
+static const uint64_t P9N2_PERV_TP_SCAN_UPDATEDR_LONG = 0x0103B000ull;
+
+static const uint64_t P9N2_PERV_N0_SCAN_UPDATEDR_LONG = 0x0203B000ull;
+
+static const uint64_t P9N2_PERV_N1_SCAN_UPDATEDR_LONG = 0x0303B000ull;
+
+static const uint64_t P9N2_PERV_N2_SCAN_UPDATEDR_LONG = 0x0403B000ull;
+
+static const uint64_t P9N2_PERV_N3_SCAN_UPDATEDR_LONG = 0x0503B000ull;
+
+static const uint64_t P9N2_PERV_XB_SCAN_UPDATEDR_LONG = 0x0603B000ull;
+
+static const uint64_t P9N2_PERV_MC01_SCAN_UPDATEDR_LONG = 0x0703B000ull;
+
+static const uint64_t P9N2_PERV_MC23_SCAN_UPDATEDR_LONG = 0x0803B000ull;
+
+static const uint64_t P9N2_PERV_OB0_SCAN_UPDATEDR_LONG = 0x0903B000ull;
+
+static const uint64_t P9N2_PERV_OB3_SCAN_UPDATEDR_LONG = 0x0C03B000ull;
+
+static const uint64_t P9N2_PERV_PCI0_SCAN_UPDATEDR_LONG = 0x0D03B000ull;
+
+static const uint64_t P9N2_PERV_PCI1_SCAN_UPDATEDR_LONG = 0x0E03B000ull;
+
+static const uint64_t P9N2_PERV_PCI2_SCAN_UPDATEDR_LONG = 0x0F03B000ull;
+
+static const uint64_t P9N2_PERV_EP00_SCAN_UPDATEDR_LONG = 0x1003B000ull;
+
+static const uint64_t P9N2_PERV_EP01_SCAN_UPDATEDR_LONG = 0x1103B000ull;
+
+static const uint64_t P9N2_PERV_EP02_SCAN_UPDATEDR_LONG = 0x1203B000ull;
+
+static const uint64_t P9N2_PERV_EP03_SCAN_UPDATEDR_LONG = 0x1303B000ull;
+
+static const uint64_t P9N2_PERV_EP04_SCAN_UPDATEDR_LONG = 0x1403B000ull;
+
+static const uint64_t P9N2_PERV_EP05_SCAN_UPDATEDR_LONG = 0x1503B000ull;
+
+static const uint64_t P9N2_PERV_EC00_SCAN_UPDATEDR_LONG = 0x2003B000ull;
+
+static const uint64_t P9N2_PERV_EC01_SCAN_UPDATEDR_LONG = 0x2103B000ull;
+
+static const uint64_t P9N2_PERV_EC02_SCAN_UPDATEDR_LONG = 0x2203B000ull;
+
+static const uint64_t P9N2_PERV_EC03_SCAN_UPDATEDR_LONG = 0x2303B000ull;
+
+static const uint64_t P9N2_PERV_EC04_SCAN_UPDATEDR_LONG = 0x2403B000ull;
+
+static const uint64_t P9N2_PERV_EC05_SCAN_UPDATEDR_LONG = 0x2503B000ull;
+
+static const uint64_t P9N2_PERV_EC06_SCAN_UPDATEDR_LONG = 0x2603B000ull;
+
+static const uint64_t P9N2_PERV_EC07_SCAN_UPDATEDR_LONG = 0x2703B000ull;
+
+static const uint64_t P9N2_PERV_EC08_SCAN_UPDATEDR_LONG = 0x2803B000ull;
+
+static const uint64_t P9N2_PERV_EC09_SCAN_UPDATEDR_LONG = 0x2903B000ull;
+
+static const uint64_t P9N2_PERV_EC10_SCAN_UPDATEDR_LONG = 0x2A03B000ull;
+
+static const uint64_t P9N2_PERV_EC11_SCAN_UPDATEDR_LONG = 0x2B03B000ull;
+
+static const uint64_t P9N2_PERV_EC12_SCAN_UPDATEDR_LONG = 0x2C03B000ull;
+
+static const uint64_t P9N2_PERV_EC13_SCAN_UPDATEDR_LONG = 0x2D03B000ull;
+
+static const uint64_t P9N2_PERV_EC14_SCAN_UPDATEDR_LONG = 0x2E03B000ull;
+
+static const uint64_t P9N2_PERV_EC15_SCAN_UPDATEDR_LONG = 0x2F03B000ull;
+
+static const uint64_t P9N2_PERV_EC16_SCAN_UPDATEDR_LONG = 0x3003B000ull;
+
+static const uint64_t P9N2_PERV_EC17_SCAN_UPDATEDR_LONG = 0x3103B000ull;
+
+static const uint64_t P9N2_PERV_EC18_SCAN_UPDATEDR_LONG = 0x3203B000ull;
+
+static const uint64_t P9N2_PERV_EC19_SCAN_UPDATEDR_LONG = 0x3303B000ull;
+
+static const uint64_t P9N2_PERV_EC20_SCAN_UPDATEDR_LONG = 0x3403B000ull;
+
+static const uint64_t P9N2_PERV_EC21_SCAN_UPDATEDR_LONG = 0x3503B000ull;
+
+static const uint64_t P9N2_PERV_EC22_SCAN_UPDATEDR_LONG = 0x3603B000ull;
+
+static const uint64_t P9N2_PERV_EC23_SCAN_UPDATEDR_LONG = 0x3703B000ull;
+
+
+static const uint32_t P9N2_PERV_SCPSIZE_FSI = 0x00001400ull;
+
+
+static const uint32_t P9N2_PERV_SCRATCH_REGISTER_1_FSI = 0x00002838ull;
+
+static const uint32_t P9N2_PERV_SCRATCH_REGISTER_1_FSI_BYTE = 0x000028E0ull;
+
+static const uint64_t P9N2_PERV_SCRATCH_REGISTER_1_SCOM = 0x00050038ull;
+
+static const uint64_t P9N2_PERV_PIB_SCRATCH_REGISTER_1 = 0x00050038ull;
+
+
+static const uint32_t P9N2_PERV_SCRATCH_REGISTER_2_FSI = 0x00002839ull;
+
+static const uint32_t P9N2_PERV_SCRATCH_REGISTER_2_FSI_BYTE = 0x000028E4ull;
+
+static const uint64_t P9N2_PERV_SCRATCH_REGISTER_2_SCOM = 0x00050039ull;
+
+static const uint64_t P9N2_PERV_PIB_SCRATCH_REGISTER_2 = 0x00050039ull;
+
+
+static const uint32_t P9N2_PERV_SCRATCH_REGISTER_3_FSI = 0x0000283Aull;
+
+static const uint32_t P9N2_PERV_SCRATCH_REGISTER_3_FSI_BYTE = 0x000028E8ull;
+
+static const uint64_t P9N2_PERV_SCRATCH_REGISTER_3_SCOM = 0x0005003Aull;
+
+static const uint64_t P9N2_PERV_PIB_SCRATCH_REGISTER_3 = 0x0005003Aull;
+
+
+static const uint32_t P9N2_PERV_SCRATCH_REGISTER_4_FSI = 0x0000283Bull;
+
+static const uint32_t P9N2_PERV_SCRATCH_REGISTER_4_FSI_BYTE = 0x000028ECull;
+
+static const uint64_t P9N2_PERV_SCRATCH_REGISTER_4_SCOM = 0x0005003Bull;
+
+static const uint64_t P9N2_PERV_PIB_SCRATCH_REGISTER_4 = 0x0005003Bull;
+
+
+static const uint32_t P9N2_PERV_SCRATCH_REGISTER_5_FSI = 0x0000283Cull;
+
+static const uint32_t P9N2_PERV_SCRATCH_REGISTER_5_FSI_BYTE = 0x000028F0ull;
+
+static const uint64_t P9N2_PERV_SCRATCH_REGISTER_5_SCOM = 0x0005003Cull;
+
+static const uint64_t P9N2_PERV_PIB_SCRATCH_REGISTER_5 = 0x0005003Cull;
+
+
+static const uint32_t P9N2_PERV_SCRATCH_REGISTER_6_FSI = 0x0000283Dull;
+
+static const uint32_t P9N2_PERV_SCRATCH_REGISTER_6_FSI_BYTE = 0x000028F4ull;
+
+static const uint64_t P9N2_PERV_SCRATCH_REGISTER_6_SCOM = 0x0005003Dull;
+
+static const uint64_t P9N2_PERV_PIB_SCRATCH_REGISTER_6 = 0x0005003Dull;
+
+
+static const uint32_t P9N2_PERV_SCRATCH_REGISTER_7_FSI = 0x0000283Eull;
+
+static const uint32_t P9N2_PERV_SCRATCH_REGISTER_7_FSI_BYTE = 0x000028F8ull;
+
+static const uint64_t P9N2_PERV_SCRATCH_REGISTER_7_SCOM = 0x0005003Eull;
+
+static const uint64_t P9N2_PERV_PIB_SCRATCH_REGISTER_7 = 0x0005003Eull;
+
+
+static const uint32_t P9N2_PERV_SCRATCH_REGISTER_8_FSI = 0x0000283Full;
+
+static const uint32_t P9N2_PERV_SCRATCH_REGISTER_8_FSI_BYTE = 0x000028FCull;
+
+static const uint64_t P9N2_PERV_SCRATCH_REGISTER_8_SCOM = 0x0005003Full;
+
+static const uint64_t P9N2_PERV_PIB_SCRATCH_REGISTER_8 = 0x0005003Full;
+
+
+static const uint32_t P9N2_PERV_FSI2PIB_SET_PIB_RESET_FSI = 0x00001007ull;
+
+static const uint32_t P9N2_PERV_FSI2PIB_SET_PIB_RESET_FSI_BYTE = 0x0000101Cull;
+
+
+static const uint32_t P9N2_PERV_FSISHIFT_SHIFT_CONTROL_REGISTER_2_FSI = 0x00000C10ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_SHIFT_CONTROL_REGISTER_2_FSI_BYTE = 0x00000C40ull;
+
+
+static const uint64_t P9N2_PERV_SKITTER_CLKSRC_REG = 0x00050016ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_PERV_TP_SKITTER_CLKSRC_REG = 0x01050016ull;
+
+static const uint64_t P9N2_PERV_N0_SKITTER_CLKSRC_REG = 0x02050016ull;
+
+static const uint64_t P9N2_PERV_N1_SKITTER_CLKSRC_REG = 0x03050016ull;
+
+static const uint64_t P9N2_PERV_N2_SKITTER_CLKSRC_REG = 0x04050016ull;
+
+static const uint64_t P9N2_PERV_N3_SKITTER_CLKSRC_REG = 0x05050016ull;
+
+static const uint64_t P9N2_PERV_XB_SKITTER_CLKSRC_REG = 0x06050016ull;
+
+static const uint64_t P9N2_PERV_MC01_SKITTER_CLKSRC_REG = 0x07050016ull;
+
+static const uint64_t P9N2_PERV_MC23_SKITTER_CLKSRC_REG = 0x08050016ull;
+
+static const uint64_t P9N2_PERV_OB0_SKITTER_CLKSRC_REG = 0x09050016ull;
+
+static const uint64_t P9N2_PERV_OB3_SKITTER_CLKSRC_REG = 0x0C050016ull;
+
+static const uint64_t P9N2_PERV_PCI0_SKITTER_CLKSRC_REG = 0x0D050016ull;
+
+static const uint64_t P9N2_PERV_PCI1_SKITTER_CLKSRC_REG = 0x0E050016ull;
+
+static const uint64_t P9N2_PERV_PCI2_SKITTER_CLKSRC_REG = 0x0F050016ull;
+
+static const uint64_t P9N2_PERV_EP00_SKITTER_CLKSRC_REG = 0x10050016ull;
+
+static const uint64_t P9N2_PERV_EP01_SKITTER_CLKSRC_REG = 0x11050016ull;
+
+static const uint64_t P9N2_PERV_EP02_SKITTER_CLKSRC_REG = 0x12050016ull;
+
+static const uint64_t P9N2_PERV_EP03_SKITTER_CLKSRC_REG = 0x13050016ull;
+
+static const uint64_t P9N2_PERV_EP04_SKITTER_CLKSRC_REG = 0x14050016ull;
+
+static const uint64_t P9N2_PERV_EP05_SKITTER_CLKSRC_REG = 0x15050016ull;
+
+static const uint64_t P9N2_PERV_EC00_SKITTER_CLKSRC_REG = 0x20050016ull;
+
+static const uint64_t P9N2_PERV_EC01_SKITTER_CLKSRC_REG = 0x21050016ull;
+
+static const uint64_t P9N2_PERV_EC02_SKITTER_CLKSRC_REG = 0x22050016ull;
+
+static const uint64_t P9N2_PERV_EC03_SKITTER_CLKSRC_REG = 0x23050016ull;
+
+static const uint64_t P9N2_PERV_EC04_SKITTER_CLKSRC_REG = 0x24050016ull;
+
+static const uint64_t P9N2_PERV_EC05_SKITTER_CLKSRC_REG = 0x25050016ull;
+
+static const uint64_t P9N2_PERV_EC06_SKITTER_CLKSRC_REG = 0x26050016ull;
+
+static const uint64_t P9N2_PERV_EC07_SKITTER_CLKSRC_REG = 0x27050016ull;
+
+static const uint64_t P9N2_PERV_EC08_SKITTER_CLKSRC_REG = 0x28050016ull;
+
+static const uint64_t P9N2_PERV_EC09_SKITTER_CLKSRC_REG = 0x29050016ull;
+
+static const uint64_t P9N2_PERV_EC10_SKITTER_CLKSRC_REG = 0x2A050016ull;
+
+static const uint64_t P9N2_PERV_EC11_SKITTER_CLKSRC_REG = 0x2B050016ull;
+
+static const uint64_t P9N2_PERV_EC12_SKITTER_CLKSRC_REG = 0x2C050016ull;
+
+static const uint64_t P9N2_PERV_EC13_SKITTER_CLKSRC_REG = 0x2D050016ull;
+
+static const uint64_t P9N2_PERV_EC14_SKITTER_CLKSRC_REG = 0x2E050016ull;
+
+static const uint64_t P9N2_PERV_EC15_SKITTER_CLKSRC_REG = 0x2F050016ull;
+
+static const uint64_t P9N2_PERV_EC16_SKITTER_CLKSRC_REG = 0x30050016ull;
+
+static const uint64_t P9N2_PERV_EC17_SKITTER_CLKSRC_REG = 0x31050016ull;
+
+static const uint64_t P9N2_PERV_EC18_SKITTER_CLKSRC_REG = 0x32050016ull;
+
+static const uint64_t P9N2_PERV_EC19_SKITTER_CLKSRC_REG = 0x33050016ull;
+
+static const uint64_t P9N2_PERV_EC20_SKITTER_CLKSRC_REG = 0x34050016ull;
+
+static const uint64_t P9N2_PERV_EC21_SKITTER_CLKSRC_REG = 0x35050016ull;
+
+static const uint64_t P9N2_PERV_EC22_SKITTER_CLKSRC_REG = 0x36050016ull;
+
+static const uint64_t P9N2_PERV_EC23_SKITTER_CLKSRC_REG = 0x37050016ull;
+
+
+static const uint64_t P9N2_PERV_SKITTER_DATA0 = 0x00050019ull;
+
+static const uint64_t P9N2_PERV_TP_SKITTER_DATA0 = 0x01050019ull;
+
+static const uint64_t P9N2_PERV_N0_SKITTER_DATA0 = 0x02050019ull;
+
+static const uint64_t P9N2_PERV_N1_SKITTER_DATA0 = 0x03050019ull;
+
+static const uint64_t P9N2_PERV_N2_SKITTER_DATA0 = 0x04050019ull;
+
+static const uint64_t P9N2_PERV_N3_SKITTER_DATA0 = 0x05050019ull;
+
+static const uint64_t P9N2_PERV_XB_SKITTER_DATA0 = 0x06050019ull;
+
+static const uint64_t P9N2_PERV_MC01_SKITTER_DATA0 = 0x07050019ull;
+
+static const uint64_t P9N2_PERV_MC23_SKITTER_DATA0 = 0x08050019ull;
+
+static const uint64_t P9N2_PERV_OB0_SKITTER_DATA0 = 0x09050019ull;
+
+static const uint64_t P9N2_PERV_OB3_SKITTER_DATA0 = 0x0C050019ull;
+
+static const uint64_t P9N2_PERV_PCI0_SKITTER_DATA0 = 0x0D050019ull;
+
+static const uint64_t P9N2_PERV_PCI1_SKITTER_DATA0 = 0x0E050019ull;
+
+static const uint64_t P9N2_PERV_PCI2_SKITTER_DATA0 = 0x0F050019ull;
+
+static const uint64_t P9N2_PERV_EP00_SKITTER_DATA0 = 0x10050019ull;
+
+static const uint64_t P9N2_PERV_EP01_SKITTER_DATA0 = 0x11050019ull;
+
+static const uint64_t P9N2_PERV_EP02_SKITTER_DATA0 = 0x12050019ull;
+
+static const uint64_t P9N2_PERV_EP03_SKITTER_DATA0 = 0x13050019ull;
+
+static const uint64_t P9N2_PERV_EP04_SKITTER_DATA0 = 0x14050019ull;
+
+static const uint64_t P9N2_PERV_EP05_SKITTER_DATA0 = 0x15050019ull;
+
+static const uint64_t P9N2_PERV_EC00_SKITTER_DATA0 = 0x20050019ull;
+
+static const uint64_t P9N2_PERV_EC01_SKITTER_DATA0 = 0x21050019ull;
+
+static const uint64_t P9N2_PERV_EC02_SKITTER_DATA0 = 0x22050019ull;
+
+static const uint64_t P9N2_PERV_EC03_SKITTER_DATA0 = 0x23050019ull;
+
+static const uint64_t P9N2_PERV_EC04_SKITTER_DATA0 = 0x24050019ull;
+
+static const uint64_t P9N2_PERV_EC05_SKITTER_DATA0 = 0x25050019ull;
+
+static const uint64_t P9N2_PERV_EC06_SKITTER_DATA0 = 0x26050019ull;
+
+static const uint64_t P9N2_PERV_EC07_SKITTER_DATA0 = 0x27050019ull;
+
+static const uint64_t P9N2_PERV_EC08_SKITTER_DATA0 = 0x28050019ull;
+
+static const uint64_t P9N2_PERV_EC09_SKITTER_DATA0 = 0x29050019ull;
+
+static const uint64_t P9N2_PERV_EC10_SKITTER_DATA0 = 0x2A050019ull;
+
+static const uint64_t P9N2_PERV_EC11_SKITTER_DATA0 = 0x2B050019ull;
+
+static const uint64_t P9N2_PERV_EC12_SKITTER_DATA0 = 0x2C050019ull;
+
+static const uint64_t P9N2_PERV_EC13_SKITTER_DATA0 = 0x2D050019ull;
+
+static const uint64_t P9N2_PERV_EC14_SKITTER_DATA0 = 0x2E050019ull;
+
+static const uint64_t P9N2_PERV_EC15_SKITTER_DATA0 = 0x2F050019ull;
+
+static const uint64_t P9N2_PERV_EC16_SKITTER_DATA0 = 0x30050019ull;
+
+static const uint64_t P9N2_PERV_EC17_SKITTER_DATA0 = 0x31050019ull;
+
+static const uint64_t P9N2_PERV_EC18_SKITTER_DATA0 = 0x32050019ull;
+
+static const uint64_t P9N2_PERV_EC19_SKITTER_DATA0 = 0x33050019ull;
+
+static const uint64_t P9N2_PERV_EC20_SKITTER_DATA0 = 0x34050019ull;
+
+static const uint64_t P9N2_PERV_EC21_SKITTER_DATA0 = 0x35050019ull;
+
+static const uint64_t P9N2_PERV_EC22_SKITTER_DATA0 = 0x36050019ull;
+
+static const uint64_t P9N2_PERV_EC23_SKITTER_DATA0 = 0x37050019ull;
+
+
+static const uint64_t P9N2_PERV_SKITTER_DATA1 = 0x0005001Aull;
+
+static const uint64_t P9N2_PERV_TP_SKITTER_DATA1 = 0x0105001Aull;
+
+static const uint64_t P9N2_PERV_N0_SKITTER_DATA1 = 0x0205001Aull;
+
+static const uint64_t P9N2_PERV_N1_SKITTER_DATA1 = 0x0305001Aull;
+
+static const uint64_t P9N2_PERV_N2_SKITTER_DATA1 = 0x0405001Aull;
+
+static const uint64_t P9N2_PERV_N3_SKITTER_DATA1 = 0x0505001Aull;
+
+static const uint64_t P9N2_PERV_XB_SKITTER_DATA1 = 0x0605001Aull;
+
+static const uint64_t P9N2_PERV_MC01_SKITTER_DATA1 = 0x0705001Aull;
+
+static const uint64_t P9N2_PERV_MC23_SKITTER_DATA1 = 0x0805001Aull;
+
+static const uint64_t P9N2_PERV_OB0_SKITTER_DATA1 = 0x0905001Aull;
+
+static const uint64_t P9N2_PERV_OB3_SKITTER_DATA1 = 0x0C05001Aull;
+
+static const uint64_t P9N2_PERV_PCI0_SKITTER_DATA1 = 0x0D05001Aull;
+
+static const uint64_t P9N2_PERV_PCI1_SKITTER_DATA1 = 0x0E05001Aull;
+
+static const uint64_t P9N2_PERV_PCI2_SKITTER_DATA1 = 0x0F05001Aull;
+
+static const uint64_t P9N2_PERV_EP00_SKITTER_DATA1 = 0x1005001Aull;
+
+static const uint64_t P9N2_PERV_EP01_SKITTER_DATA1 = 0x1105001Aull;
+
+static const uint64_t P9N2_PERV_EP02_SKITTER_DATA1 = 0x1205001Aull;
+
+static const uint64_t P9N2_PERV_EP03_SKITTER_DATA1 = 0x1305001Aull;
+
+static const uint64_t P9N2_PERV_EP04_SKITTER_DATA1 = 0x1405001Aull;
+
+static const uint64_t P9N2_PERV_EP05_SKITTER_DATA1 = 0x1505001Aull;
+
+static const uint64_t P9N2_PERV_EC00_SKITTER_DATA1 = 0x2005001Aull;
+
+static const uint64_t P9N2_PERV_EC01_SKITTER_DATA1 = 0x2105001Aull;
+
+static const uint64_t P9N2_PERV_EC02_SKITTER_DATA1 = 0x2205001Aull;
+
+static const uint64_t P9N2_PERV_EC03_SKITTER_DATA1 = 0x2305001Aull;
+
+static const uint64_t P9N2_PERV_EC04_SKITTER_DATA1 = 0x2405001Aull;
+
+static const uint64_t P9N2_PERV_EC05_SKITTER_DATA1 = 0x2505001Aull;
+
+static const uint64_t P9N2_PERV_EC06_SKITTER_DATA1 = 0x2605001Aull;
+
+static const uint64_t P9N2_PERV_EC07_SKITTER_DATA1 = 0x2705001Aull;
+
+static const uint64_t P9N2_PERV_EC08_SKITTER_DATA1 = 0x2805001Aull;
+
+static const uint64_t P9N2_PERV_EC09_SKITTER_DATA1 = 0x2905001Aull;
+
+static const uint64_t P9N2_PERV_EC10_SKITTER_DATA1 = 0x2A05001Aull;
+
+static const uint64_t P9N2_PERV_EC11_SKITTER_DATA1 = 0x2B05001Aull;
+
+static const uint64_t P9N2_PERV_EC12_SKITTER_DATA1 = 0x2C05001Aull;
+
+static const uint64_t P9N2_PERV_EC13_SKITTER_DATA1 = 0x2D05001Aull;
+
+static const uint64_t P9N2_PERV_EC14_SKITTER_DATA1 = 0x2E05001Aull;
+
+static const uint64_t P9N2_PERV_EC15_SKITTER_DATA1 = 0x2F05001Aull;
+
+static const uint64_t P9N2_PERV_EC16_SKITTER_DATA1 = 0x3005001Aull;
+
+static const uint64_t P9N2_PERV_EC17_SKITTER_DATA1 = 0x3105001Aull;
+
+static const uint64_t P9N2_PERV_EC18_SKITTER_DATA1 = 0x3205001Aull;
+
+static const uint64_t P9N2_PERV_EC19_SKITTER_DATA1 = 0x3305001Aull;
+
+static const uint64_t P9N2_PERV_EC20_SKITTER_DATA1 = 0x3405001Aull;
+
+static const uint64_t P9N2_PERV_EC21_SKITTER_DATA1 = 0x3505001Aull;
+
+static const uint64_t P9N2_PERV_EC22_SKITTER_DATA1 = 0x3605001Aull;
+
+static const uint64_t P9N2_PERV_EC23_SKITTER_DATA1 = 0x3705001Aull;
+
+
+static const uint64_t P9N2_PERV_SKITTER_DATA2 = 0x0005001Bull;
+
+static const uint64_t P9N2_PERV_TP_SKITTER_DATA2 = 0x0105001Bull;
+
+static const uint64_t P9N2_PERV_N0_SKITTER_DATA2 = 0x0205001Bull;
+
+static const uint64_t P9N2_PERV_N1_SKITTER_DATA2 = 0x0305001Bull;
+
+static const uint64_t P9N2_PERV_N2_SKITTER_DATA2 = 0x0405001Bull;
+
+static const uint64_t P9N2_PERV_N3_SKITTER_DATA2 = 0x0505001Bull;
+
+static const uint64_t P9N2_PERV_XB_SKITTER_DATA2 = 0x0605001Bull;
+
+static const uint64_t P9N2_PERV_MC01_SKITTER_DATA2 = 0x0705001Bull;
+
+static const uint64_t P9N2_PERV_MC23_SKITTER_DATA2 = 0x0805001Bull;
+
+static const uint64_t P9N2_PERV_OB0_SKITTER_DATA2 = 0x0905001Bull;
+
+static const uint64_t P9N2_PERV_OB3_SKITTER_DATA2 = 0x0C05001Bull;
+
+static const uint64_t P9N2_PERV_PCI0_SKITTER_DATA2 = 0x0D05001Bull;
+
+static const uint64_t P9N2_PERV_PCI1_SKITTER_DATA2 = 0x0E05001Bull;
+
+static const uint64_t P9N2_PERV_PCI2_SKITTER_DATA2 = 0x0F05001Bull;
+
+static const uint64_t P9N2_PERV_EP00_SKITTER_DATA2 = 0x1005001Bull;
+
+static const uint64_t P9N2_PERV_EP01_SKITTER_DATA2 = 0x1105001Bull;
+
+static const uint64_t P9N2_PERV_EP02_SKITTER_DATA2 = 0x1205001Bull;
+
+static const uint64_t P9N2_PERV_EP03_SKITTER_DATA2 = 0x1305001Bull;
+
+static const uint64_t P9N2_PERV_EP04_SKITTER_DATA2 = 0x1405001Bull;
+
+static const uint64_t P9N2_PERV_EP05_SKITTER_DATA2 = 0x1505001Bull;
+
+static const uint64_t P9N2_PERV_EC00_SKITTER_DATA2 = 0x2005001Bull;
+
+static const uint64_t P9N2_PERV_EC01_SKITTER_DATA2 = 0x2105001Bull;
+
+static const uint64_t P9N2_PERV_EC02_SKITTER_DATA2 = 0x2205001Bull;
+
+static const uint64_t P9N2_PERV_EC03_SKITTER_DATA2 = 0x2305001Bull;
+
+static const uint64_t P9N2_PERV_EC04_SKITTER_DATA2 = 0x2405001Bull;
+
+static const uint64_t P9N2_PERV_EC05_SKITTER_DATA2 = 0x2505001Bull;
+
+static const uint64_t P9N2_PERV_EC06_SKITTER_DATA2 = 0x2605001Bull;
+
+static const uint64_t P9N2_PERV_EC07_SKITTER_DATA2 = 0x2705001Bull;
+
+static const uint64_t P9N2_PERV_EC08_SKITTER_DATA2 = 0x2805001Bull;
+
+static const uint64_t P9N2_PERV_EC09_SKITTER_DATA2 = 0x2905001Bull;
+
+static const uint64_t P9N2_PERV_EC10_SKITTER_DATA2 = 0x2A05001Bull;
+
+static const uint64_t P9N2_PERV_EC11_SKITTER_DATA2 = 0x2B05001Bull;
+
+static const uint64_t P9N2_PERV_EC12_SKITTER_DATA2 = 0x2C05001Bull;
+
+static const uint64_t P9N2_PERV_EC13_SKITTER_DATA2 = 0x2D05001Bull;
+
+static const uint64_t P9N2_PERV_EC14_SKITTER_DATA2 = 0x2E05001Bull;
+
+static const uint64_t P9N2_PERV_EC15_SKITTER_DATA2 = 0x2F05001Bull;
+
+static const uint64_t P9N2_PERV_EC16_SKITTER_DATA2 = 0x3005001Bull;
+
+static const uint64_t P9N2_PERV_EC17_SKITTER_DATA2 = 0x3105001Bull;
+
+static const uint64_t P9N2_PERV_EC18_SKITTER_DATA2 = 0x3205001Bull;
+
+static const uint64_t P9N2_PERV_EC19_SKITTER_DATA2 = 0x3305001Bull;
+
+static const uint64_t P9N2_PERV_EC20_SKITTER_DATA2 = 0x3405001Bull;
+
+static const uint64_t P9N2_PERV_EC21_SKITTER_DATA2 = 0x3505001Bull;
+
+static const uint64_t P9N2_PERV_EC22_SKITTER_DATA2 = 0x3605001Bull;
+
+static const uint64_t P9N2_PERV_EC23_SKITTER_DATA2 = 0x3705001Bull;
+
+
+static const uint64_t P9N2_PERV_SKITTER_FORCE_REG = 0x00050014ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_PERV_TP_SKITTER_FORCE_REG = 0x01050014ull;
+
+static const uint64_t P9N2_PERV_N0_SKITTER_FORCE_REG = 0x02050014ull;
+
+static const uint64_t P9N2_PERV_N1_SKITTER_FORCE_REG = 0x03050014ull;
+
+static const uint64_t P9N2_PERV_N2_SKITTER_FORCE_REG = 0x04050014ull;
+
+static const uint64_t P9N2_PERV_N3_SKITTER_FORCE_REG = 0x05050014ull;
+
+static const uint64_t P9N2_PERV_XB_SKITTER_FORCE_REG = 0x06050014ull;
+
+static const uint64_t P9N2_PERV_MC01_SKITTER_FORCE_REG = 0x07050014ull;
+
+static const uint64_t P9N2_PERV_MC23_SKITTER_FORCE_REG = 0x08050014ull;
+
+static const uint64_t P9N2_PERV_OB0_SKITTER_FORCE_REG = 0x09050014ull;
+
+static const uint64_t P9N2_PERV_OB3_SKITTER_FORCE_REG = 0x0C050014ull;
+
+static const uint64_t P9N2_PERV_PCI0_SKITTER_FORCE_REG = 0x0D050014ull;
+
+static const uint64_t P9N2_PERV_PCI1_SKITTER_FORCE_REG = 0x0E050014ull;
+
+static const uint64_t P9N2_PERV_PCI2_SKITTER_FORCE_REG = 0x0F050014ull;
+
+static const uint64_t P9N2_PERV_EP00_SKITTER_FORCE_REG = 0x10050014ull;
+
+static const uint64_t P9N2_PERV_EP01_SKITTER_FORCE_REG = 0x11050014ull;
+
+static const uint64_t P9N2_PERV_EP02_SKITTER_FORCE_REG = 0x12050014ull;
+
+static const uint64_t P9N2_PERV_EP03_SKITTER_FORCE_REG = 0x13050014ull;
+
+static const uint64_t P9N2_PERV_EP04_SKITTER_FORCE_REG = 0x14050014ull;
+
+static const uint64_t P9N2_PERV_EP05_SKITTER_FORCE_REG = 0x15050014ull;
+
+static const uint64_t P9N2_PERV_EC00_SKITTER_FORCE_REG = 0x20050014ull;
+
+static const uint64_t P9N2_PERV_EC01_SKITTER_FORCE_REG = 0x21050014ull;
+
+static const uint64_t P9N2_PERV_EC02_SKITTER_FORCE_REG = 0x22050014ull;
+
+static const uint64_t P9N2_PERV_EC03_SKITTER_FORCE_REG = 0x23050014ull;
+
+static const uint64_t P9N2_PERV_EC04_SKITTER_FORCE_REG = 0x24050014ull;
+
+static const uint64_t P9N2_PERV_EC05_SKITTER_FORCE_REG = 0x25050014ull;
+
+static const uint64_t P9N2_PERV_EC06_SKITTER_FORCE_REG = 0x26050014ull;
+
+static const uint64_t P9N2_PERV_EC07_SKITTER_FORCE_REG = 0x27050014ull;
+
+static const uint64_t P9N2_PERV_EC08_SKITTER_FORCE_REG = 0x28050014ull;
+
+static const uint64_t P9N2_PERV_EC09_SKITTER_FORCE_REG = 0x29050014ull;
+
+static const uint64_t P9N2_PERV_EC10_SKITTER_FORCE_REG = 0x2A050014ull;
+
+static const uint64_t P9N2_PERV_EC11_SKITTER_FORCE_REG = 0x2B050014ull;
+
+static const uint64_t P9N2_PERV_EC12_SKITTER_FORCE_REG = 0x2C050014ull;
+
+static const uint64_t P9N2_PERV_EC13_SKITTER_FORCE_REG = 0x2D050014ull;
+
+static const uint64_t P9N2_PERV_EC14_SKITTER_FORCE_REG = 0x2E050014ull;
+
+static const uint64_t P9N2_PERV_EC15_SKITTER_FORCE_REG = 0x2F050014ull;
+
+static const uint64_t P9N2_PERV_EC16_SKITTER_FORCE_REG = 0x30050014ull;
+
+static const uint64_t P9N2_PERV_EC17_SKITTER_FORCE_REG = 0x31050014ull;
+
+static const uint64_t P9N2_PERV_EC18_SKITTER_FORCE_REG = 0x32050014ull;
+
+static const uint64_t P9N2_PERV_EC19_SKITTER_FORCE_REG = 0x33050014ull;
+
+static const uint64_t P9N2_PERV_EC20_SKITTER_FORCE_REG = 0x34050014ull;
+
+static const uint64_t P9N2_PERV_EC21_SKITTER_FORCE_REG = 0x35050014ull;
+
+static const uint64_t P9N2_PERV_EC22_SKITTER_FORCE_REG = 0x36050014ull;
+
+static const uint64_t P9N2_PERV_EC23_SKITTER_FORCE_REG = 0x37050014ull;
+
+
+static const uint64_t P9N2_PERV_SKITTER_MODE_REG = 0x00050010ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_PERV_TP_SKITTER_MODE_REG = 0x01050010ull;
+
+static const uint64_t P9N2_PERV_N0_SKITTER_MODE_REG = 0x02050010ull;
+
+static const uint64_t P9N2_PERV_N1_SKITTER_MODE_REG = 0x03050010ull;
+
+static const uint64_t P9N2_PERV_N2_SKITTER_MODE_REG = 0x04050010ull;
+
+static const uint64_t P9N2_PERV_N3_SKITTER_MODE_REG = 0x05050010ull;
+
+static const uint64_t P9N2_PERV_XB_SKITTER_MODE_REG = 0x06050010ull;
+
+static const uint64_t P9N2_PERV_MC01_SKITTER_MODE_REG = 0x07050010ull;
+
+static const uint64_t P9N2_PERV_MC23_SKITTER_MODE_REG = 0x08050010ull;
+
+static const uint64_t P9N2_PERV_OB0_SKITTER_MODE_REG = 0x09050010ull;
+
+static const uint64_t P9N2_PERV_OB3_SKITTER_MODE_REG = 0x0C050010ull;
+
+static const uint64_t P9N2_PERV_PCI0_SKITTER_MODE_REG = 0x0D050010ull;
+
+static const uint64_t P9N2_PERV_PCI1_SKITTER_MODE_REG = 0x0E050010ull;
+
+static const uint64_t P9N2_PERV_PCI2_SKITTER_MODE_REG = 0x0F050010ull;
+
+static const uint64_t P9N2_PERV_EP00_SKITTER_MODE_REG = 0x10050010ull;
+
+static const uint64_t P9N2_PERV_EP01_SKITTER_MODE_REG = 0x11050010ull;
+
+static const uint64_t P9N2_PERV_EP02_SKITTER_MODE_REG = 0x12050010ull;
+
+static const uint64_t P9N2_PERV_EP03_SKITTER_MODE_REG = 0x13050010ull;
+
+static const uint64_t P9N2_PERV_EP04_SKITTER_MODE_REG = 0x14050010ull;
+
+static const uint64_t P9N2_PERV_EP05_SKITTER_MODE_REG = 0x15050010ull;
+
+static const uint64_t P9N2_PERV_EC00_SKITTER_MODE_REG = 0x20050010ull;
+
+static const uint64_t P9N2_PERV_EC01_SKITTER_MODE_REG = 0x21050010ull;
+
+static const uint64_t P9N2_PERV_EC02_SKITTER_MODE_REG = 0x22050010ull;
+
+static const uint64_t P9N2_PERV_EC03_SKITTER_MODE_REG = 0x23050010ull;
+
+static const uint64_t P9N2_PERV_EC04_SKITTER_MODE_REG = 0x24050010ull;
+
+static const uint64_t P9N2_PERV_EC05_SKITTER_MODE_REG = 0x25050010ull;
+
+static const uint64_t P9N2_PERV_EC06_SKITTER_MODE_REG = 0x26050010ull;
+
+static const uint64_t P9N2_PERV_EC07_SKITTER_MODE_REG = 0x27050010ull;
+
+static const uint64_t P9N2_PERV_EC08_SKITTER_MODE_REG = 0x28050010ull;
+
+static const uint64_t P9N2_PERV_EC09_SKITTER_MODE_REG = 0x29050010ull;
+
+static const uint64_t P9N2_PERV_EC10_SKITTER_MODE_REG = 0x2A050010ull;
+
+static const uint64_t P9N2_PERV_EC11_SKITTER_MODE_REG = 0x2B050010ull;
+
+static const uint64_t P9N2_PERV_EC12_SKITTER_MODE_REG = 0x2C050010ull;
+
+static const uint64_t P9N2_PERV_EC13_SKITTER_MODE_REG = 0x2D050010ull;
+
+static const uint64_t P9N2_PERV_EC14_SKITTER_MODE_REG = 0x2E050010ull;
+
+static const uint64_t P9N2_PERV_EC15_SKITTER_MODE_REG = 0x2F050010ull;
+
+static const uint64_t P9N2_PERV_EC16_SKITTER_MODE_REG = 0x30050010ull;
+
+static const uint64_t P9N2_PERV_EC17_SKITTER_MODE_REG = 0x31050010ull;
+
+static const uint64_t P9N2_PERV_EC18_SKITTER_MODE_REG = 0x32050010ull;
+
+static const uint64_t P9N2_PERV_EC19_SKITTER_MODE_REG = 0x33050010ull;
+
+static const uint64_t P9N2_PERV_EC20_SKITTER_MODE_REG = 0x34050010ull;
+
+static const uint64_t P9N2_PERV_EC21_SKITTER_MODE_REG = 0x35050010ull;
+
+static const uint64_t P9N2_PERV_EC22_SKITTER_MODE_REG = 0x36050010ull;
+
+static const uint64_t P9N2_PERV_EC23_SKITTER_MODE_REG = 0x37050010ull;
+
+
+static const uint64_t P9N2_PERV_SLAVE_CONFIG_REG = 0x000F001Eull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_PERV_TP_SLAVE_CONFIG_REG = 0x010F001Eull;
+
+static const uint64_t P9N2_PERV_N0_SLAVE_CONFIG_REG = 0x020F001Eull;
+
+static const uint64_t P9N2_PERV_N1_SLAVE_CONFIG_REG = 0x030F001Eull;
+
+static const uint64_t P9N2_PERV_N2_SLAVE_CONFIG_REG = 0x040F001Eull;
+
+static const uint64_t P9N2_PERV_N3_SLAVE_CONFIG_REG = 0x050F001Eull;
+
+static const uint64_t P9N2_PERV_XB_SLAVE_CONFIG_REG = 0x060F001Eull;
+
+static const uint64_t P9N2_PERV_MC01_SLAVE_CONFIG_REG = 0x070F001Eull;
+
+static const uint64_t P9N2_PERV_MC23_SLAVE_CONFIG_REG = 0x080F001Eull;
+
+static const uint64_t P9N2_PERV_OB0_SLAVE_CONFIG_REG = 0x090F001Eull;
+
+static const uint64_t P9N2_PERV_OB3_SLAVE_CONFIG_REG = 0x0C0F001Eull;
+
+static const uint64_t P9N2_PERV_PCI0_SLAVE_CONFIG_REG = 0x0D0F001Eull;
+
+static const uint64_t P9N2_PERV_PCI1_SLAVE_CONFIG_REG = 0x0E0F001Eull;
+
+static const uint64_t P9N2_PERV_PCI2_SLAVE_CONFIG_REG = 0x0F0F001Eull;
+
+static const uint64_t P9N2_PERV_EP00_SLAVE_CONFIG_REG = 0x100F001Eull;
+
+static const uint64_t P9N2_PERV_EP01_SLAVE_CONFIG_REG = 0x110F001Eull;
+
+static const uint64_t P9N2_PERV_EP02_SLAVE_CONFIG_REG = 0x120F001Eull;
+
+static const uint64_t P9N2_PERV_EP03_SLAVE_CONFIG_REG = 0x130F001Eull;
+
+static const uint64_t P9N2_PERV_EP04_SLAVE_CONFIG_REG = 0x140F001Eull;
+
+static const uint64_t P9N2_PERV_EP05_SLAVE_CONFIG_REG = 0x150F001Eull;
+
+static const uint64_t P9N2_PERV_EC00_SLAVE_CONFIG_REG = 0x200F001Eull;
+
+static const uint64_t P9N2_PERV_EC01_SLAVE_CONFIG_REG = 0x210F001Eull;
+
+static const uint64_t P9N2_PERV_EC02_SLAVE_CONFIG_REG = 0x220F001Eull;
+
+static const uint64_t P9N2_PERV_EC03_SLAVE_CONFIG_REG = 0x230F001Eull;
+
+static const uint64_t P9N2_PERV_EC04_SLAVE_CONFIG_REG = 0x240F001Eull;
+
+static const uint64_t P9N2_PERV_EC05_SLAVE_CONFIG_REG = 0x250F001Eull;
+
+static const uint64_t P9N2_PERV_EC06_SLAVE_CONFIG_REG = 0x260F001Eull;
+
+static const uint64_t P9N2_PERV_EC07_SLAVE_CONFIG_REG = 0x270F001Eull;
+
+static const uint64_t P9N2_PERV_EC08_SLAVE_CONFIG_REG = 0x280F001Eull;
+
+static const uint64_t P9N2_PERV_EC09_SLAVE_CONFIG_REG = 0x290F001Eull;
+
+static const uint64_t P9N2_PERV_EC10_SLAVE_CONFIG_REG = 0x2A0F001Eull;
+
+static const uint64_t P9N2_PERV_EC11_SLAVE_CONFIG_REG = 0x2B0F001Eull;
+
+static const uint64_t P9N2_PERV_EC12_SLAVE_CONFIG_REG = 0x2C0F001Eull;
+
+static const uint64_t P9N2_PERV_EC13_SLAVE_CONFIG_REG = 0x2D0F001Eull;
+
+static const uint64_t P9N2_PERV_EC14_SLAVE_CONFIG_REG = 0x2E0F001Eull;
+
+static const uint64_t P9N2_PERV_EC15_SLAVE_CONFIG_REG = 0x2F0F001Eull;
+
+static const uint64_t P9N2_PERV_EC16_SLAVE_CONFIG_REG = 0x300F001Eull;
+
+static const uint64_t P9N2_PERV_EC17_SLAVE_CONFIG_REG = 0x310F001Eull;
+
+static const uint64_t P9N2_PERV_EC18_SLAVE_CONFIG_REG = 0x320F001Eull;
+
+static const uint64_t P9N2_PERV_EC19_SLAVE_CONFIG_REG = 0x330F001Eull;
+
+static const uint64_t P9N2_PERV_EC20_SLAVE_CONFIG_REG = 0x340F001Eull;
+
+static const uint64_t P9N2_PERV_EC21_SLAVE_CONFIG_REG = 0x350F001Eull;
+
+static const uint64_t P9N2_PERV_EC22_SLAVE_CONFIG_REG = 0x360F001Eull;
+
+static const uint64_t P9N2_PERV_EC23_SLAVE_CONFIG_REG = 0x370F001Eull;
+
+
+static const uint32_t P9N2_PERV_SNS1LTH_FSI = 0x0000281Dull;
+
+static const uint32_t P9N2_PERV_SNS1LTH_FSI_BYTE = 0x00002874ull;
+
+static const uint64_t P9N2_PERV_SNS1LTH_SCOM = 0x0005001Dull;
+
+static const uint64_t P9N2_PERV_PIB_SNS1LTH = 0x0005001Dull;
+
+
+static const uint32_t P9N2_PERV_SNS2LTH_FSI = 0x0000281Eull;
+
+static const uint32_t P9N2_PERV_SNS2LTH_FSI_BYTE = 0x00002878ull;
+
+static const uint64_t P9N2_PERV_SNS2LTH_SCOM = 0x0005001Eull;
+
+static const uint64_t P9N2_PERV_PIB_SNS2LTH = 0x0005001Eull;
+
+
+static const uint64_t P9N2_PERV_SPATTN_SCOM = 0x00040004ull;
+
+static const uint64_t P9N2_PERV_TP_SPATTN_SCOM = 0x01040004ull;
+
+static const uint64_t P9N2_PERV_SPATTN_SCOM1 = 0x00040005ull;
+
+static const uint64_t P9N2_PERV_TP_SPATTN_SCOM1 = 0x01040005ull;
+
+static const uint64_t P9N2_PERV_SPATTN_SCOM2 = 0x00040006ull;
+
+static const uint64_t P9N2_PERV_TP_SPATTN_SCOM2 = 0x01040006ull;
+
+static const uint64_t P9N2_PERV_N0_SPATTN_SCOM = 0x02040004ull;
+
+static const uint64_t P9N2_PERV_N0_SPATTN_SCOM1 = 0x02040005ull;
+
+static const uint64_t P9N2_PERV_N0_SPATTN_SCOM2 = 0x02040006ull;
+
+static const uint64_t P9N2_PERV_N1_SPATTN_SCOM = 0x03040004ull;
+
+static const uint64_t P9N2_PERV_N1_SPATTN_SCOM1 = 0x03040005ull;
+
+static const uint64_t P9N2_PERV_N1_SPATTN_SCOM2 = 0x03040006ull;
+
+static const uint64_t P9N2_PERV_N2_SPATTN_SCOM = 0x04040004ull;
+
+static const uint64_t P9N2_PERV_N2_SPATTN_SCOM1 = 0x04040005ull;
+
+static const uint64_t P9N2_PERV_N2_SPATTN_SCOM2 = 0x04040006ull;
+
+static const uint64_t P9N2_PERV_N3_SPATTN_SCOM = 0x05040004ull;
+
+static const uint64_t P9N2_PERV_N3_SPATTN_SCOM1 = 0x05040005ull;
+
+static const uint64_t P9N2_PERV_N3_SPATTN_SCOM2 = 0x05040006ull;
+
+static const uint64_t P9N2_PERV_XB_SPATTN_SCOM = 0x06040004ull;
+
+static const uint64_t P9N2_PERV_XB_SPATTN_SCOM1 = 0x06040005ull;
+
+static const uint64_t P9N2_PERV_XB_SPATTN_SCOM2 = 0x06040006ull;
+
+static const uint64_t P9N2_PERV_MC01_SPATTN_SCOM = 0x07040004ull;
+
+static const uint64_t P9N2_PERV_MC01_SPATTN_SCOM1 = 0x07040005ull;
+
+static const uint64_t P9N2_PERV_MC01_SPATTN_SCOM2 = 0x07040006ull;
+
+static const uint64_t P9N2_PERV_MC23_SPATTN_SCOM = 0x08040004ull;
+
+static const uint64_t P9N2_PERV_MC23_SPATTN_SCOM1 = 0x08040005ull;
+
+static const uint64_t P9N2_PERV_MC23_SPATTN_SCOM2 = 0x08040006ull;
+
+static const uint64_t P9N2_PERV_OB0_SPATTN_SCOM = 0x09040004ull;
+
+static const uint64_t P9N2_PERV_OB0_SPATTN_SCOM1 = 0x09040005ull;
+
+static const uint64_t P9N2_PERV_OB0_SPATTN_SCOM2 = 0x09040006ull;
+
+static const uint64_t P9N2_PERV_OB3_SPATTN_SCOM = 0x0C040004ull;
+
+static const uint64_t P9N2_PERV_OB3_SPATTN_SCOM1 = 0x0C040005ull;
+
+static const uint64_t P9N2_PERV_OB3_SPATTN_SCOM2 = 0x0C040006ull;
+
+static const uint64_t P9N2_PERV_PCI0_SPATTN_SCOM = 0x0D040004ull;
+
+static const uint64_t P9N2_PERV_PCI0_SPATTN_SCOM1 = 0x0D040005ull;
+
+static const uint64_t P9N2_PERV_PCI0_SPATTN_SCOM2 = 0x0D040006ull;
+
+static const uint64_t P9N2_PERV_PCI1_SPATTN_SCOM = 0x0E040004ull;
+
+static const uint64_t P9N2_PERV_PCI1_SPATTN_SCOM1 = 0x0E040005ull;
+
+static const uint64_t P9N2_PERV_PCI1_SPATTN_SCOM2 = 0x0E040006ull;
+
+static const uint64_t P9N2_PERV_PCI2_SPATTN_SCOM = 0x0F040004ull;
+
+static const uint64_t P9N2_PERV_PCI2_SPATTN_SCOM1 = 0x0F040005ull;
+
+static const uint64_t P9N2_PERV_PCI2_SPATTN_SCOM2 = 0x0F040006ull;
+
+static const uint64_t P9N2_PERV_EP00_SPATTN_SCOM = 0x10040004ull;
+
+static const uint64_t P9N2_PERV_EP00_SPATTN_SCOM1 = 0x10040005ull;
+
+static const uint64_t P9N2_PERV_EP00_SPATTN_SCOM2 = 0x10040006ull;
+
+static const uint64_t P9N2_PERV_EP01_SPATTN_SCOM = 0x11040004ull;
+
+static const uint64_t P9N2_PERV_EP01_SPATTN_SCOM1 = 0x11040005ull;
+
+static const uint64_t P9N2_PERV_EP01_SPATTN_SCOM2 = 0x11040006ull;
+
+static const uint64_t P9N2_PERV_EP02_SPATTN_SCOM = 0x12040004ull;
+
+static const uint64_t P9N2_PERV_EP02_SPATTN_SCOM1 = 0x12040005ull;
+
+static const uint64_t P9N2_PERV_EP02_SPATTN_SCOM2 = 0x12040006ull;
+
+static const uint64_t P9N2_PERV_EP03_SPATTN_SCOM = 0x13040004ull;
+
+static const uint64_t P9N2_PERV_EP03_SPATTN_SCOM1 = 0x13040005ull;
+
+static const uint64_t P9N2_PERV_EP03_SPATTN_SCOM2 = 0x13040006ull;
+
+static const uint64_t P9N2_PERV_EP04_SPATTN_SCOM = 0x14040004ull;
+
+static const uint64_t P9N2_PERV_EP04_SPATTN_SCOM1 = 0x14040005ull;
+
+static const uint64_t P9N2_PERV_EP04_SPATTN_SCOM2 = 0x14040006ull;
+
+static const uint64_t P9N2_PERV_EP05_SPATTN_SCOM = 0x15040004ull;
+
+static const uint64_t P9N2_PERV_EP05_SPATTN_SCOM1 = 0x15040005ull;
+
+static const uint64_t P9N2_PERV_EP05_SPATTN_SCOM2 = 0x15040006ull;
+
+static const uint64_t P9N2_PERV_EC00_SPATTN_SCOM = 0x20040004ull;
+
+static const uint64_t P9N2_PERV_EC00_SPATTN_SCOM1 = 0x20040005ull;
+
+static const uint64_t P9N2_PERV_EC00_SPATTN_SCOM2 = 0x20040006ull;
+
+static const uint64_t P9N2_PERV_EC01_SPATTN_SCOM = 0x21040004ull;
+
+static const uint64_t P9N2_PERV_EC01_SPATTN_SCOM1 = 0x21040005ull;
+
+static const uint64_t P9N2_PERV_EC01_SPATTN_SCOM2 = 0x21040006ull;
+
+static const uint64_t P9N2_PERV_EC02_SPATTN_SCOM = 0x22040004ull;
+
+static const uint64_t P9N2_PERV_EC02_SPATTN_SCOM1 = 0x22040005ull;
+
+static const uint64_t P9N2_PERV_EC02_SPATTN_SCOM2 = 0x22040006ull;
+
+static const uint64_t P9N2_PERV_EC03_SPATTN_SCOM = 0x23040004ull;
+
+static const uint64_t P9N2_PERV_EC03_SPATTN_SCOM1 = 0x23040005ull;
+
+static const uint64_t P9N2_PERV_EC03_SPATTN_SCOM2 = 0x23040006ull;
+
+static const uint64_t P9N2_PERV_EC04_SPATTN_SCOM = 0x24040004ull;
+
+static const uint64_t P9N2_PERV_EC04_SPATTN_SCOM1 = 0x24040005ull;
+
+static const uint64_t P9N2_PERV_EC04_SPATTN_SCOM2 = 0x24040006ull;
+
+static const uint64_t P9N2_PERV_EC05_SPATTN_SCOM = 0x25040004ull;
+
+static const uint64_t P9N2_PERV_EC05_SPATTN_SCOM1 = 0x25040005ull;
+
+static const uint64_t P9N2_PERV_EC05_SPATTN_SCOM2 = 0x25040006ull;
+
+static const uint64_t P9N2_PERV_EC06_SPATTN_SCOM = 0x26040004ull;
+
+static const uint64_t P9N2_PERV_EC06_SPATTN_SCOM1 = 0x26040005ull;
+
+static const uint64_t P9N2_PERV_EC06_SPATTN_SCOM2 = 0x26040006ull;
+
+static const uint64_t P9N2_PERV_EC07_SPATTN_SCOM = 0x27040004ull;
+
+static const uint64_t P9N2_PERV_EC07_SPATTN_SCOM1 = 0x27040005ull;
+
+static const uint64_t P9N2_PERV_EC07_SPATTN_SCOM2 = 0x27040006ull;
+
+static const uint64_t P9N2_PERV_EC08_SPATTN_SCOM = 0x28040004ull;
+
+static const uint64_t P9N2_PERV_EC08_SPATTN_SCOM1 = 0x28040005ull;
+
+static const uint64_t P9N2_PERV_EC08_SPATTN_SCOM2 = 0x28040006ull;
+
+static const uint64_t P9N2_PERV_EC09_SPATTN_SCOM = 0x29040004ull;
+
+static const uint64_t P9N2_PERV_EC09_SPATTN_SCOM1 = 0x29040005ull;
+
+static const uint64_t P9N2_PERV_EC09_SPATTN_SCOM2 = 0x29040006ull;
+
+static const uint64_t P9N2_PERV_EC10_SPATTN_SCOM = 0x2A040004ull;
+
+static const uint64_t P9N2_PERV_EC10_SPATTN_SCOM1 = 0x2A040005ull;
+
+static const uint64_t P9N2_PERV_EC10_SPATTN_SCOM2 = 0x2A040006ull;
+
+static const uint64_t P9N2_PERV_EC11_SPATTN_SCOM = 0x2B040004ull;
+
+static const uint64_t P9N2_PERV_EC11_SPATTN_SCOM1 = 0x2B040005ull;
+
+static const uint64_t P9N2_PERV_EC11_SPATTN_SCOM2 = 0x2B040006ull;
+
+static const uint64_t P9N2_PERV_EC12_SPATTN_SCOM = 0x2C040004ull;
+
+static const uint64_t P9N2_PERV_EC12_SPATTN_SCOM1 = 0x2C040005ull;
+
+static const uint64_t P9N2_PERV_EC12_SPATTN_SCOM2 = 0x2C040006ull;
+
+static const uint64_t P9N2_PERV_EC13_SPATTN_SCOM = 0x2D040004ull;
+
+static const uint64_t P9N2_PERV_EC13_SPATTN_SCOM1 = 0x2D040005ull;
+
+static const uint64_t P9N2_PERV_EC13_SPATTN_SCOM2 = 0x2D040006ull;
+
+static const uint64_t P9N2_PERV_EC14_SPATTN_SCOM = 0x2E040004ull;
+
+static const uint64_t P9N2_PERV_EC14_SPATTN_SCOM1 = 0x2E040005ull;
+
+static const uint64_t P9N2_PERV_EC14_SPATTN_SCOM2 = 0x2E040006ull;
+
+static const uint64_t P9N2_PERV_EC15_SPATTN_SCOM = 0x2F040004ull;
+
+static const uint64_t P9N2_PERV_EC15_SPATTN_SCOM1 = 0x2F040005ull;
+
+static const uint64_t P9N2_PERV_EC15_SPATTN_SCOM2 = 0x2F040006ull;
+
+static const uint64_t P9N2_PERV_EC16_SPATTN_SCOM = 0x30040004ull;
+
+static const uint64_t P9N2_PERV_EC16_SPATTN_SCOM1 = 0x30040005ull;
+
+static const uint64_t P9N2_PERV_EC16_SPATTN_SCOM2 = 0x30040006ull;
+
+static const uint64_t P9N2_PERV_EC17_SPATTN_SCOM = 0x31040004ull;
+
+static const uint64_t P9N2_PERV_EC17_SPATTN_SCOM1 = 0x31040005ull;
+
+static const uint64_t P9N2_PERV_EC17_SPATTN_SCOM2 = 0x31040006ull;
+
+static const uint64_t P9N2_PERV_EC18_SPATTN_SCOM = 0x32040004ull;
+
+static const uint64_t P9N2_PERV_EC18_SPATTN_SCOM1 = 0x32040005ull;
+
+static const uint64_t P9N2_PERV_EC18_SPATTN_SCOM2 = 0x32040006ull;
+
+static const uint64_t P9N2_PERV_EC19_SPATTN_SCOM = 0x33040004ull;
+
+static const uint64_t P9N2_PERV_EC19_SPATTN_SCOM1 = 0x33040005ull;
+
+static const uint64_t P9N2_PERV_EC19_SPATTN_SCOM2 = 0x33040006ull;
+
+static const uint64_t P9N2_PERV_EC20_SPATTN_SCOM = 0x34040004ull;
+
+static const uint64_t P9N2_PERV_EC20_SPATTN_SCOM1 = 0x34040005ull;
+
+static const uint64_t P9N2_PERV_EC20_SPATTN_SCOM2 = 0x34040006ull;
+
+static const uint64_t P9N2_PERV_EC21_SPATTN_SCOM = 0x35040004ull;
+
+static const uint64_t P9N2_PERV_EC21_SPATTN_SCOM1 = 0x35040005ull;
+
+static const uint64_t P9N2_PERV_EC21_SPATTN_SCOM2 = 0x35040006ull;
+
+static const uint64_t P9N2_PERV_EC22_SPATTN_SCOM = 0x36040004ull;
+
+static const uint64_t P9N2_PERV_EC22_SPATTN_SCOM1 = 0x36040005ull;
+
+static const uint64_t P9N2_PERV_EC22_SPATTN_SCOM2 = 0x36040006ull;
+
+static const uint64_t P9N2_PERV_EC23_SPATTN_SCOM = 0x37040004ull;
+
+static const uint64_t P9N2_PERV_EC23_SPATTN_SCOM1 = 0x37040005ull;
+
+static const uint64_t P9N2_PERV_EC23_SPATTN_SCOM2 = 0x37040006ull;
+
+
+static const uint64_t P9N2_PERV_SPA_MASK = 0x00040007ull;
+
+static const uint64_t P9N2_PERV_TP_SPA_MASK = 0x01040007ull;
+
+static const uint64_t P9N2_PERV_N0_SPA_MASK = 0x02040007ull;
+
+static const uint64_t P9N2_PERV_N1_SPA_MASK = 0x03040007ull;
+
+static const uint64_t P9N2_PERV_N2_SPA_MASK = 0x04040007ull;
+
+static const uint64_t P9N2_PERV_N3_SPA_MASK = 0x05040007ull;
+
+static const uint64_t P9N2_PERV_XB_SPA_MASK = 0x06040007ull;
+
+static const uint64_t P9N2_PERV_MC01_SPA_MASK = 0x07040007ull;
+
+static const uint64_t P9N2_PERV_MC23_SPA_MASK = 0x08040007ull;
+
+static const uint64_t P9N2_PERV_OB0_SPA_MASK = 0x09040007ull;
+
+static const uint64_t P9N2_PERV_OB3_SPA_MASK = 0x0C040007ull;
+
+static const uint64_t P9N2_PERV_PCI0_SPA_MASK = 0x0D040007ull;
+
+static const uint64_t P9N2_PERV_PCI1_SPA_MASK = 0x0E040007ull;
+
+static const uint64_t P9N2_PERV_PCI2_SPA_MASK = 0x0F040007ull;
+
+static const uint64_t P9N2_PERV_EP00_SPA_MASK = 0x10040007ull;
+
+static const uint64_t P9N2_PERV_EP01_SPA_MASK = 0x11040007ull;
+
+static const uint64_t P9N2_PERV_EP02_SPA_MASK = 0x12040007ull;
+
+static const uint64_t P9N2_PERV_EP03_SPA_MASK = 0x13040007ull;
+
+static const uint64_t P9N2_PERV_EP04_SPA_MASK = 0x14040007ull;
+
+static const uint64_t P9N2_PERV_EP05_SPA_MASK = 0x15040007ull;
+
+static const uint64_t P9N2_PERV_EC00_SPA_MASK = 0x20040007ull;
+
+static const uint64_t P9N2_PERV_EC01_SPA_MASK = 0x21040007ull;
+
+static const uint64_t P9N2_PERV_EC02_SPA_MASK = 0x22040007ull;
+
+static const uint64_t P9N2_PERV_EC03_SPA_MASK = 0x23040007ull;
+
+static const uint64_t P9N2_PERV_EC04_SPA_MASK = 0x24040007ull;
+
+static const uint64_t P9N2_PERV_EC05_SPA_MASK = 0x25040007ull;
+
+static const uint64_t P9N2_PERV_EC06_SPA_MASK = 0x26040007ull;
+
+static const uint64_t P9N2_PERV_EC07_SPA_MASK = 0x27040007ull;
+
+static const uint64_t P9N2_PERV_EC08_SPA_MASK = 0x28040007ull;
+
+static const uint64_t P9N2_PERV_EC09_SPA_MASK = 0x29040007ull;
+
+static const uint64_t P9N2_PERV_EC10_SPA_MASK = 0x2A040007ull;
+
+static const uint64_t P9N2_PERV_EC11_SPA_MASK = 0x2B040007ull;
+
+static const uint64_t P9N2_PERV_EC12_SPA_MASK = 0x2C040007ull;
+
+static const uint64_t P9N2_PERV_EC13_SPA_MASK = 0x2D040007ull;
+
+static const uint64_t P9N2_PERV_EC14_SPA_MASK = 0x2E040007ull;
+
+static const uint64_t P9N2_PERV_EC15_SPA_MASK = 0x2F040007ull;
+
+static const uint64_t P9N2_PERV_EC16_SPA_MASK = 0x30040007ull;
+
+static const uint64_t P9N2_PERV_EC17_SPA_MASK = 0x31040007ull;
+
+static const uint64_t P9N2_PERV_EC18_SPA_MASK = 0x32040007ull;
+
+static const uint64_t P9N2_PERV_EC19_SPA_MASK = 0x33040007ull;
+
+static const uint64_t P9N2_PERV_EC20_SPA_MASK = 0x34040007ull;
+
+static const uint64_t P9N2_PERV_EC21_SPA_MASK = 0x35040007ull;
+
+static const uint64_t P9N2_PERV_EC22_SPA_MASK = 0x36040007ull;
+
+static const uint64_t P9N2_PERV_EC23_SPA_MASK = 0x37040007ull;
+
+
+static const uint32_t P9N2_PERV_FSI2PIB_STATUS_FSI = 0x00001007ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint32_t P9N2_PERV_FSI2PIB_STATUS_FSI_BYTE = 0x0000101Cull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint32_t P9N2_PERV_FSISHIFT_STATUS_FSI = 0x00000C07ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint32_t P9N2_PERV_FSISHIFT_STATUS_FSI_BYTE = 0x00000C1Cull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+
+static const uint64_t P9N2_PERV_0_FSII2C_STATUS_REGISTER_ENGINE_A = 0x00001807ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint32_t P9N2_PERV_FSII2C_STATUS_REGISTER_ENGINE_A = 0x00001807ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+
+static const uint64_t P9N2_PERV_STAT_RDDAT_ERRES = 0x00030001ull;
+
+static const uint64_t P9N2_PERV_PIB_STAT_RDDAT_ERRES = 0x00030001ull;
+
+static const uint64_t P9N2_PERV_0_PIB2OPB0_STAT_RDDAT_ERRES = 0x00020001ull;
+
+static const uint64_t P9N2_PERV_0_PIB2OPB1_STAT_RDDAT_ERRES = 0x00020011ull;
+
+static const uint64_t P9N2_PERV_PIB2OPB0_STAT_RDDAT_ERRES = 0x00020001ull;
+
+static const uint64_t P9N2_PERV_PIB2OPB1_STAT_RDDAT_ERRES = 0x00020011ull;
+
+
+static const uint64_t P9N2_PERV_SUM_MASK_REG = 0x00040017ull;
+
+static const uint64_t P9N2_PERV_TP_SUM_MASK_REG = 0x01040017ull;
+
+static const uint64_t P9N2_PERV_N0_SUM_MASK_REG = 0x02040017ull;
+
+static const uint64_t P9N2_PERV_N1_SUM_MASK_REG = 0x03040017ull;
+
+static const uint64_t P9N2_PERV_N2_SUM_MASK_REG = 0x04040017ull;
+
+static const uint64_t P9N2_PERV_N3_SUM_MASK_REG = 0x05040017ull;
+
+static const uint64_t P9N2_PERV_XB_SUM_MASK_REG = 0x06040017ull;
+
+static const uint64_t P9N2_PERV_MC01_SUM_MASK_REG = 0x07040017ull;
+
+static const uint64_t P9N2_PERV_MC23_SUM_MASK_REG = 0x08040017ull;
+
+static const uint64_t P9N2_PERV_OB0_SUM_MASK_REG = 0x09040017ull;
+
+static const uint64_t P9N2_PERV_OB3_SUM_MASK_REG = 0x0C040017ull;
+
+static const uint64_t P9N2_PERV_PCI0_SUM_MASK_REG = 0x0D040017ull;
+
+static const uint64_t P9N2_PERV_PCI1_SUM_MASK_REG = 0x0E040017ull;
+
+static const uint64_t P9N2_PERV_PCI2_SUM_MASK_REG = 0x0F040017ull;
+
+static const uint64_t P9N2_PERV_EP00_SUM_MASK_REG = 0x10040017ull;
+
+static const uint64_t P9N2_PERV_EP01_SUM_MASK_REG = 0x11040017ull;
+
+static const uint64_t P9N2_PERV_EP02_SUM_MASK_REG = 0x12040017ull;
+
+static const uint64_t P9N2_PERV_EP03_SUM_MASK_REG = 0x13040017ull;
+
+static const uint64_t P9N2_PERV_EP04_SUM_MASK_REG = 0x14040017ull;
+
+static const uint64_t P9N2_PERV_EP05_SUM_MASK_REG = 0x15040017ull;
+
+static const uint64_t P9N2_PERV_EC00_SUM_MASK_REG = 0x20040017ull;
+
+static const uint64_t P9N2_PERV_EC01_SUM_MASK_REG = 0x21040017ull;
+
+static const uint64_t P9N2_PERV_EC02_SUM_MASK_REG = 0x22040017ull;
+
+static const uint64_t P9N2_PERV_EC03_SUM_MASK_REG = 0x23040017ull;
+
+static const uint64_t P9N2_PERV_EC04_SUM_MASK_REG = 0x24040017ull;
+
+static const uint64_t P9N2_PERV_EC05_SUM_MASK_REG = 0x25040017ull;
+
+static const uint64_t P9N2_PERV_EC06_SUM_MASK_REG = 0x26040017ull;
+
+static const uint64_t P9N2_PERV_EC07_SUM_MASK_REG = 0x27040017ull;
+
+static const uint64_t P9N2_PERV_EC08_SUM_MASK_REG = 0x28040017ull;
+
+static const uint64_t P9N2_PERV_EC09_SUM_MASK_REG = 0x29040017ull;
+
+static const uint64_t P9N2_PERV_EC10_SUM_MASK_REG = 0x2A040017ull;
+
+static const uint64_t P9N2_PERV_EC11_SUM_MASK_REG = 0x2B040017ull;
+
+static const uint64_t P9N2_PERV_EC12_SUM_MASK_REG = 0x2C040017ull;
+
+static const uint64_t P9N2_PERV_EC13_SUM_MASK_REG = 0x2D040017ull;
+
+static const uint64_t P9N2_PERV_EC14_SUM_MASK_REG = 0x2E040017ull;
+
+static const uint64_t P9N2_PERV_EC15_SUM_MASK_REG = 0x2F040017ull;
+
+static const uint64_t P9N2_PERV_EC16_SUM_MASK_REG = 0x30040017ull;
+
+static const uint64_t P9N2_PERV_EC17_SUM_MASK_REG = 0x31040017ull;
+
+static const uint64_t P9N2_PERV_EC18_SUM_MASK_REG = 0x32040017ull;
+
+static const uint64_t P9N2_PERV_EC19_SUM_MASK_REG = 0x33040017ull;
+
+static const uint64_t P9N2_PERV_EC20_SUM_MASK_REG = 0x34040017ull;
+
+static const uint64_t P9N2_PERV_EC21_SUM_MASK_REG = 0x35040017ull;
+
+static const uint64_t P9N2_PERV_EC22_SUM_MASK_REG = 0x36040017ull;
+
+static const uint64_t P9N2_PERV_EC23_SUM_MASK_REG = 0x37040017ull;
+
+
+static const uint64_t P9N2_PERV_SYNC_CONFIG = 0x00030000ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_PERV_TP_SYNC_CONFIG = 0x01030000ull;
+
+static const uint64_t P9N2_PERV_N0_SYNC_CONFIG = 0x02030000ull;
+
+static const uint64_t P9N2_PERV_N1_SYNC_CONFIG = 0x03030000ull;
+
+static const uint64_t P9N2_PERV_N2_SYNC_CONFIG = 0x04030000ull;
+
+static const uint64_t P9N2_PERV_N3_SYNC_CONFIG = 0x05030000ull;
+
+static const uint64_t P9N2_PERV_XB_SYNC_CONFIG = 0x06030000ull;
+
+static const uint64_t P9N2_PERV_MC01_SYNC_CONFIG = 0x07030000ull;
+
+static const uint64_t P9N2_PERV_MC23_SYNC_CONFIG = 0x08030000ull;
+
+static const uint64_t P9N2_PERV_OB0_SYNC_CONFIG = 0x09030000ull;
+
+static const uint64_t P9N2_PERV_OB3_SYNC_CONFIG = 0x0C030000ull;
+
+static const uint64_t P9N2_PERV_PCI0_SYNC_CONFIG = 0x0D030000ull;
+
+static const uint64_t P9N2_PERV_PCI1_SYNC_CONFIG = 0x0E030000ull;
+
+static const uint64_t P9N2_PERV_PCI2_SYNC_CONFIG = 0x0F030000ull;
+
+static const uint64_t P9N2_PERV_EP00_SYNC_CONFIG = 0x10030000ull;
+
+static const uint64_t P9N2_PERV_EP01_SYNC_CONFIG = 0x11030000ull;
+
+static const uint64_t P9N2_PERV_EP02_SYNC_CONFIG = 0x12030000ull;
+
+static const uint64_t P9N2_PERV_EP03_SYNC_CONFIG = 0x13030000ull;
+
+static const uint64_t P9N2_PERV_EP04_SYNC_CONFIG = 0x14030000ull;
+
+static const uint64_t P9N2_PERV_EP05_SYNC_CONFIG = 0x15030000ull;
+
+static const uint64_t P9N2_PERV_EC00_SYNC_CONFIG = 0x20030000ull;
+
+static const uint64_t P9N2_PERV_EC01_SYNC_CONFIG = 0x21030000ull;
+
+static const uint64_t P9N2_PERV_EC02_SYNC_CONFIG = 0x22030000ull;
+
+static const uint64_t P9N2_PERV_EC03_SYNC_CONFIG = 0x23030000ull;
+
+static const uint64_t P9N2_PERV_EC04_SYNC_CONFIG = 0x24030000ull;
+
+static const uint64_t P9N2_PERV_EC05_SYNC_CONFIG = 0x25030000ull;
+
+static const uint64_t P9N2_PERV_EC06_SYNC_CONFIG = 0x26030000ull;
+
+static const uint64_t P9N2_PERV_EC07_SYNC_CONFIG = 0x27030000ull;
+
+static const uint64_t P9N2_PERV_EC08_SYNC_CONFIG = 0x28030000ull;
+
+static const uint64_t P9N2_PERV_EC09_SYNC_CONFIG = 0x29030000ull;
+
+static const uint64_t P9N2_PERV_EC10_SYNC_CONFIG = 0x2A030000ull;
+
+static const uint64_t P9N2_PERV_EC11_SYNC_CONFIG = 0x2B030000ull;
+
+static const uint64_t P9N2_PERV_EC12_SYNC_CONFIG = 0x2C030000ull;
+
+static const uint64_t P9N2_PERV_EC13_SYNC_CONFIG = 0x2D030000ull;
+
+static const uint64_t P9N2_PERV_EC14_SYNC_CONFIG = 0x2E030000ull;
+
+static const uint64_t P9N2_PERV_EC15_SYNC_CONFIG = 0x2F030000ull;
+
+static const uint64_t P9N2_PERV_EC16_SYNC_CONFIG = 0x30030000ull;
+
+static const uint64_t P9N2_PERV_EC17_SYNC_CONFIG = 0x31030000ull;
+
+static const uint64_t P9N2_PERV_EC18_SYNC_CONFIG = 0x32030000ull;
+
+static const uint64_t P9N2_PERV_EC19_SYNC_CONFIG = 0x33030000ull;
+
+static const uint64_t P9N2_PERV_EC20_SYNC_CONFIG = 0x34030000ull;
+
+static const uint64_t P9N2_PERV_EC21_SYNC_CONFIG = 0x35030000ull;
+
+static const uint64_t P9N2_PERV_EC22_SYNC_CONFIG = 0x36030000ull;
+
+static const uint64_t P9N2_PERV_EC23_SYNC_CONFIG = 0x37030000ull;
+
+
+static const uint64_t P9N2_PERV_THERM_MODE_REG = 0x0005000Full;
+
+static const uint64_t P9N2_PERV_TP_THERM_MODE_REG = 0x0105000Full;
+
+static const uint64_t P9N2_PERV_N0_THERM_MODE_REG = 0x0205000Full;
+
+static const uint64_t P9N2_PERV_N1_THERM_MODE_REG = 0x0305000Full;
+
+static const uint64_t P9N2_PERV_N2_THERM_MODE_REG = 0x0405000Full;
+
+static const uint64_t P9N2_PERV_N3_THERM_MODE_REG = 0x0505000Full;
+
+static const uint64_t P9N2_PERV_XB_THERM_MODE_REG = 0x0605000Full;
+
+static const uint64_t P9N2_PERV_MC01_THERM_MODE_REG = 0x0705000Full;
+
+static const uint64_t P9N2_PERV_MC23_THERM_MODE_REG = 0x0805000Full;
+
+static const uint64_t P9N2_PERV_OB0_THERM_MODE_REG = 0x0905000Full;
+
+static const uint64_t P9N2_PERV_OB3_THERM_MODE_REG = 0x0C05000Full;
+
+static const uint64_t P9N2_PERV_PCI0_THERM_MODE_REG = 0x0D05000Full;
+
+static const uint64_t P9N2_PERV_PCI1_THERM_MODE_REG = 0x0E05000Full;
+
+static const uint64_t P9N2_PERV_PCI2_THERM_MODE_REG = 0x0F05000Full;
+
+static const uint64_t P9N2_PERV_EP00_THERM_MODE_REG = 0x1005000Full;
+
+static const uint64_t P9N2_PERV_EP01_THERM_MODE_REG = 0x1105000Full;
+
+static const uint64_t P9N2_PERV_EP02_THERM_MODE_REG = 0x1205000Full;
+
+static const uint64_t P9N2_PERV_EP03_THERM_MODE_REG = 0x1305000Full;
+
+static const uint64_t P9N2_PERV_EP04_THERM_MODE_REG = 0x1405000Full;
+
+static const uint64_t P9N2_PERV_EP05_THERM_MODE_REG = 0x1505000Full;
+
+static const uint64_t P9N2_PERV_EC00_THERM_MODE_REG = 0x2005000Full;
+
+static const uint64_t P9N2_PERV_EC01_THERM_MODE_REG = 0x2105000Full;
+
+static const uint64_t P9N2_PERV_EC02_THERM_MODE_REG = 0x2205000Full;
+
+static const uint64_t P9N2_PERV_EC03_THERM_MODE_REG = 0x2305000Full;
+
+static const uint64_t P9N2_PERV_EC04_THERM_MODE_REG = 0x2405000Full;
+
+static const uint64_t P9N2_PERV_EC05_THERM_MODE_REG = 0x2505000Full;
+
+static const uint64_t P9N2_PERV_EC06_THERM_MODE_REG = 0x2605000Full;
+
+static const uint64_t P9N2_PERV_EC07_THERM_MODE_REG = 0x2705000Full;
+
+static const uint64_t P9N2_PERV_EC08_THERM_MODE_REG = 0x2805000Full;
+
+static const uint64_t P9N2_PERV_EC09_THERM_MODE_REG = 0x2905000Full;
+
+static const uint64_t P9N2_PERV_EC10_THERM_MODE_REG = 0x2A05000Full;
+
+static const uint64_t P9N2_PERV_EC11_THERM_MODE_REG = 0x2B05000Full;
+
+static const uint64_t P9N2_PERV_EC12_THERM_MODE_REG = 0x2C05000Full;
+
+static const uint64_t P9N2_PERV_EC13_THERM_MODE_REG = 0x2D05000Full;
+
+static const uint64_t P9N2_PERV_EC14_THERM_MODE_REG = 0x2E05000Full;
+
+static const uint64_t P9N2_PERV_EC15_THERM_MODE_REG = 0x2F05000Full;
+
+static const uint64_t P9N2_PERV_EC16_THERM_MODE_REG = 0x3005000Full;
+
+static const uint64_t P9N2_PERV_EC17_THERM_MODE_REG = 0x3105000Full;
+
+static const uint64_t P9N2_PERV_EC18_THERM_MODE_REG = 0x3205000Full;
+
+static const uint64_t P9N2_PERV_EC19_THERM_MODE_REG = 0x3305000Full;
+
+static const uint64_t P9N2_PERV_EC20_THERM_MODE_REG = 0x3405000Full;
+
+static const uint64_t P9N2_PERV_EC21_THERM_MODE_REG = 0x3505000Full;
+
+static const uint64_t P9N2_PERV_EC22_THERM_MODE_REG = 0x3605000Full;
+
+static const uint64_t P9N2_PERV_EC23_THERM_MODE_REG = 0x3705000Full;
+
+
+static const uint64_t P9N2_PERV_TIMEOUT_REG = 0x000F0019ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_PERV_PIB_TIMEOUT_REG = 0x000F0019ull;
+
+static const uint64_t P9N2_PERV_TP_TIMEOUT_REG = 0x010F0010ull;
+
+static const uint64_t P9N2_PERV_N0_TIMEOUT_REG = 0x020F0010ull;
+
+static const uint64_t P9N2_PERV_N1_TIMEOUT_REG = 0x030F0010ull;
+
+static const uint64_t P9N2_PERV_N2_TIMEOUT_REG = 0x040F0010ull;
+
+static const uint64_t P9N2_PERV_N3_TIMEOUT_REG = 0x050F0010ull;
+
+static const uint64_t P9N2_PERV_XB_TIMEOUT_REG = 0x060F0010ull;
+
+static const uint64_t P9N2_PERV_MC01_TIMEOUT_REG = 0x070F0010ull;
+
+static const uint64_t P9N2_PERV_MC23_TIMEOUT_REG = 0x080F0010ull;
+
+static const uint64_t P9N2_PERV_OB0_TIMEOUT_REG = 0x090F0010ull;
+
+static const uint64_t P9N2_PERV_OB3_TIMEOUT_REG = 0x0C0F0010ull;
+
+static const uint64_t P9N2_PERV_PCI0_TIMEOUT_REG = 0x0D0F0010ull;
+
+static const uint64_t P9N2_PERV_PCI1_TIMEOUT_REG = 0x0E0F0010ull;
+
+static const uint64_t P9N2_PERV_PCI2_TIMEOUT_REG = 0x0F0F0010ull;
+
+static const uint64_t P9N2_PERV_EP00_TIMEOUT_REG = 0x100F0010ull;
+
+static const uint64_t P9N2_PERV_EP01_TIMEOUT_REG = 0x110F0010ull;
+
+static const uint64_t P9N2_PERV_EP02_TIMEOUT_REG = 0x120F0010ull;
+
+static const uint64_t P9N2_PERV_EP03_TIMEOUT_REG = 0x130F0010ull;
+
+static const uint64_t P9N2_PERV_EP04_TIMEOUT_REG = 0x140F0010ull;
+
+static const uint64_t P9N2_PERV_EP05_TIMEOUT_REG = 0x150F0010ull;
+
+static const uint64_t P9N2_PERV_EC00_TIMEOUT_REG = 0x200F0010ull;
+
+static const uint64_t P9N2_PERV_EC01_TIMEOUT_REG = 0x210F0010ull;
+
+static const uint64_t P9N2_PERV_EC02_TIMEOUT_REG = 0x220F0010ull;
+
+static const uint64_t P9N2_PERV_EC03_TIMEOUT_REG = 0x230F0010ull;
+
+static const uint64_t P9N2_PERV_EC04_TIMEOUT_REG = 0x240F0010ull;
+
+static const uint64_t P9N2_PERV_EC05_TIMEOUT_REG = 0x250F0010ull;
+
+static const uint64_t P9N2_PERV_EC06_TIMEOUT_REG = 0x260F0010ull;
+
+static const uint64_t P9N2_PERV_EC07_TIMEOUT_REG = 0x270F0010ull;
+
+static const uint64_t P9N2_PERV_EC08_TIMEOUT_REG = 0x280F0010ull;
+
+static const uint64_t P9N2_PERV_EC09_TIMEOUT_REG = 0x290F0010ull;
+
+static const uint64_t P9N2_PERV_EC10_TIMEOUT_REG = 0x2A0F0010ull;
+
+static const uint64_t P9N2_PERV_EC11_TIMEOUT_REG = 0x2B0F0010ull;
+
+static const uint64_t P9N2_PERV_EC12_TIMEOUT_REG = 0x2C0F0010ull;
+
+static const uint64_t P9N2_PERV_EC13_TIMEOUT_REG = 0x2D0F0010ull;
+
+static const uint64_t P9N2_PERV_EC14_TIMEOUT_REG = 0x2E0F0010ull;
+
+static const uint64_t P9N2_PERV_EC15_TIMEOUT_REG = 0x2F0F0010ull;
+
+static const uint64_t P9N2_PERV_EC16_TIMEOUT_REG = 0x300F0010ull;
+
+static const uint64_t P9N2_PERV_EC17_TIMEOUT_REG = 0x310F0010ull;
+
+static const uint64_t P9N2_PERV_EC18_TIMEOUT_REG = 0x320F0010ull;
+
+static const uint64_t P9N2_PERV_EC19_TIMEOUT_REG = 0x330F0010ull;
+
+static const uint64_t P9N2_PERV_EC20_TIMEOUT_REG = 0x340F0010ull;
+
+static const uint64_t P9N2_PERV_EC21_TIMEOUT_REG = 0x350F0010ull;
+
+static const uint64_t P9N2_PERV_EC22_TIMEOUT_REG = 0x360F0010ull;
+
+static const uint64_t P9N2_PERV_EC23_TIMEOUT_REG = 0x370F0010ull;
+
+
+static const uint64_t P9N2_PERV_TIMESTAMP_COUNTER_READ = 0x0005001Cull;
+
+static const uint64_t P9N2_PERV_TP_TIMESTAMP_COUNTER_READ = 0x0105001Cull;
+
+static const uint64_t P9N2_PERV_N0_TIMESTAMP_COUNTER_READ = 0x0205001Cull;
+
+static const uint64_t P9N2_PERV_N1_TIMESTAMP_COUNTER_READ = 0x0305001Cull;
+
+static const uint64_t P9N2_PERV_N2_TIMESTAMP_COUNTER_READ = 0x0405001Cull;
+
+static const uint64_t P9N2_PERV_N3_TIMESTAMP_COUNTER_READ = 0x0505001Cull;
+
+static const uint64_t P9N2_PERV_XB_TIMESTAMP_COUNTER_READ = 0x0605001Cull;
+
+static const uint64_t P9N2_PERV_MC01_TIMESTAMP_COUNTER_READ = 0x0705001Cull;
+
+static const uint64_t P9N2_PERV_MC23_TIMESTAMP_COUNTER_READ = 0x0805001Cull;
+
+static const uint64_t P9N2_PERV_OB0_TIMESTAMP_COUNTER_READ = 0x0905001Cull;
+
+static const uint64_t P9N2_PERV_OB3_TIMESTAMP_COUNTER_READ = 0x0C05001Cull;
+
+static const uint64_t P9N2_PERV_PCI0_TIMESTAMP_COUNTER_READ = 0x0D05001Cull;
+
+static const uint64_t P9N2_PERV_PCI1_TIMESTAMP_COUNTER_READ = 0x0E05001Cull;
+
+static const uint64_t P9N2_PERV_PCI2_TIMESTAMP_COUNTER_READ = 0x0F05001Cull;
+
+static const uint64_t P9N2_PERV_EP00_TIMESTAMP_COUNTER_READ = 0x1005001Cull;
+
+static const uint64_t P9N2_PERV_EP01_TIMESTAMP_COUNTER_READ = 0x1105001Cull;
+
+static const uint64_t P9N2_PERV_EP02_TIMESTAMP_COUNTER_READ = 0x1205001Cull;
+
+static const uint64_t P9N2_PERV_EP03_TIMESTAMP_COUNTER_READ = 0x1305001Cull;
+
+static const uint64_t P9N2_PERV_EP04_TIMESTAMP_COUNTER_READ = 0x1405001Cull;
+
+static const uint64_t P9N2_PERV_EP05_TIMESTAMP_COUNTER_READ = 0x1505001Cull;
+
+static const uint64_t P9N2_PERV_EC00_TIMESTAMP_COUNTER_READ = 0x2005001Cull;
+
+static const uint64_t P9N2_PERV_EC01_TIMESTAMP_COUNTER_READ = 0x2105001Cull;
+
+static const uint64_t P9N2_PERV_EC02_TIMESTAMP_COUNTER_READ = 0x2205001Cull;
+
+static const uint64_t P9N2_PERV_EC03_TIMESTAMP_COUNTER_READ = 0x2305001Cull;
+
+static const uint64_t P9N2_PERV_EC04_TIMESTAMP_COUNTER_READ = 0x2405001Cull;
+
+static const uint64_t P9N2_PERV_EC05_TIMESTAMP_COUNTER_READ = 0x2505001Cull;
+
+static const uint64_t P9N2_PERV_EC06_TIMESTAMP_COUNTER_READ = 0x2605001Cull;
+
+static const uint64_t P9N2_PERV_EC07_TIMESTAMP_COUNTER_READ = 0x2705001Cull;
+
+static const uint64_t P9N2_PERV_EC08_TIMESTAMP_COUNTER_READ = 0x2805001Cull;
+
+static const uint64_t P9N2_PERV_EC09_TIMESTAMP_COUNTER_READ = 0x2905001Cull;
+
+static const uint64_t P9N2_PERV_EC10_TIMESTAMP_COUNTER_READ = 0x2A05001Cull;
+
+static const uint64_t P9N2_PERV_EC11_TIMESTAMP_COUNTER_READ = 0x2B05001Cull;
+
+static const uint64_t P9N2_PERV_EC12_TIMESTAMP_COUNTER_READ = 0x2C05001Cull;
+
+static const uint64_t P9N2_PERV_EC13_TIMESTAMP_COUNTER_READ = 0x2D05001Cull;
+
+static const uint64_t P9N2_PERV_EC14_TIMESTAMP_COUNTER_READ = 0x2E05001Cull;
+
+static const uint64_t P9N2_PERV_EC15_TIMESTAMP_COUNTER_READ = 0x2F05001Cull;
+
+static const uint64_t P9N2_PERV_EC16_TIMESTAMP_COUNTER_READ = 0x3005001Cull;
+
+static const uint64_t P9N2_PERV_EC17_TIMESTAMP_COUNTER_READ = 0x3105001Cull;
+
+static const uint64_t P9N2_PERV_EC18_TIMESTAMP_COUNTER_READ = 0x3205001Cull;
+
+static const uint64_t P9N2_PERV_EC19_TIMESTAMP_COUNTER_READ = 0x3305001Cull;
+
+static const uint64_t P9N2_PERV_EC20_TIMESTAMP_COUNTER_READ = 0x3405001Cull;
+
+static const uint64_t P9N2_PERV_EC21_TIMESTAMP_COUNTER_READ = 0x3505001Cull;
+
+static const uint64_t P9N2_PERV_EC22_TIMESTAMP_COUNTER_READ = 0x3605001Cull;
+
+static const uint64_t P9N2_PERV_EC23_TIMESTAMP_COUNTER_READ = 0x3705001Cull;
+
+
+static const uint64_t P9N2_PERV_TOD_CHIP_CTRL_REG = 0x00040010ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_PERV_PIB_TOD_CHIP_CTRL_REG = 0x00040010ull;
+
+
+static const uint64_t P9N2_PERV_TOD_ERROR_INJECT_REG = 0x00040031ull;
+
+static const uint64_t P9N2_PERV_PIB_TOD_ERROR_INJECT_REG = 0x00040031ull;
+
+
+static const uint64_t P9N2_PERV_TOD_ERROR_MASK_REG = 0x00040032ull;
+
+static const uint64_t P9N2_PERV_PIB_TOD_ERROR_MASK_REG = 0x00040032ull;
+
+
+static const uint64_t P9N2_PERV_TOD_ERROR_REG = 0x00040030ull;
+
+static const uint64_t P9N2_PERV_PIB_TOD_ERROR_REG = 0x00040030ull;
+
+
+static const uint64_t P9N2_PERV_TOD_ERROR_ROUTING_REG = 0x00040033ull;
+
+static const uint64_t P9N2_PERV_PIB_TOD_ERROR_ROUTING_REG = 0x00040033ull;
+
+
+static const uint64_t P9N2_PERV_TOD_FSM_REG = 0x00040024ull;
+
+static const uint64_t P9N2_PERV_PIB_TOD_FSM_REG = 0x00040024ull;
+
+
+static const uint64_t P9N2_PERV_TOD_I_PATH_CTRL_REG = 0x00040006ull;
+
+static const uint64_t P9N2_PERV_PIB_TOD_I_PATH_CTRL_REG = 0x00040006ull;
+
+
+static const uint64_t P9N2_PERV_TOD_LOAD_TOD_MOD_REG = 0x00040018ull;
+
+static const uint64_t P9N2_PERV_PIB_TOD_LOAD_TOD_MOD_REG = 0x00040018ull;
+
+
+static const uint64_t P9N2_PERV_TOD_LOAD_TOD_REG = 0x00040021ull;
+
+static const uint64_t P9N2_PERV_PIB_TOD_LOAD_TOD_REG = 0x00040021ull;
+
+
+static const uint64_t P9N2_PERV_TOD_LOW_ORDER_STEP_REG = 0x00040023ull;
+
+static const uint64_t P9N2_PERV_PIB_TOD_LOW_ORDER_STEP_REG = 0x00040023ull;
+
+
+static const uint64_t P9N2_PERV_TOD_MISC_RESET_REG = 0x0004000Bull;
+
+static const uint64_t P9N2_PERV_PIB_TOD_MISC_RESET_REG = 0x0004000Bull;
+
+
+static const uint64_t P9N2_PERV_TOD_MOVE_TOD_TO_TB_REG = 0x00040017ull;
+
+static const uint64_t P9N2_PERV_PIB_TOD_MOVE_TOD_TO_TB_REG = 0x00040017ull;
+
+
+static const uint64_t P9N2_PERV_TOD_M_PATH_0_STEP_STEER_REG = 0x0004000Eull;
+
+static const uint64_t P9N2_PERV_PIB_TOD_M_PATH_0_STEP_STEER_REG = 0x0004000Eull;
+
+
+static const uint64_t P9N2_PERV_TOD_M_PATH_1_STEP_STEER_REG = 0x0004000Full;
+
+static const uint64_t P9N2_PERV_PIB_TOD_M_PATH_1_STEP_STEER_REG = 0x0004000Full;
+
+
+static const uint64_t P9N2_PERV_TOD_M_PATH_CTRL_REG = 0x00040000ull;
+
+static const uint64_t P9N2_PERV_PIB_TOD_M_PATH_CTRL_REG = 0x00040000ull;
+
+
+static const uint64_t P9N2_PERV_TOD_M_PATH_STATUS_REG = 0x00040009ull;
+
+static const uint64_t P9N2_PERV_PIB_TOD_M_PATH_STATUS_REG = 0x00040009ull;
+
+
+static const uint64_t P9N2_PERV_TOD_PRI_PORT_0_CTRL_REG = 0x00040001ull;
+
+static const uint64_t P9N2_PERV_PIB_TOD_PRI_PORT_0_CTRL_REG = 0x00040001ull;
+
+
+static const uint64_t P9N2_PERV_TOD_PRI_PORT_1_CTRL_REG = 0x00040002ull;
+
+static const uint64_t P9N2_PERV_PIB_TOD_PRI_PORT_1_CTRL_REG = 0x00040002ull;
+
+
+static const uint64_t P9N2_PERV_TOD_PROBE_SELECT_REG = 0x0004000Cull;
+
+static const uint64_t P9N2_PERV_PIB_TOD_PROBE_SELECT_REG = 0x0004000Cull;
+
+
+static const uint64_t P9N2_PERV_TOD_PSS_MSS_CTRL_REG = 0x00040007ull;
+
+static const uint64_t P9N2_PERV_PIB_TOD_PSS_MSS_CTRL_REG = 0x00040007ull;
+
+
+static const uint64_t P9N2_PERV_TOD_PSS_MSS_STATUS_REG = 0x00040008ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_PERV_PIB_TOD_PSS_MSS_STATUS_REG = 0x00040008ull;
+
+
+static const uint64_t P9N2_PERV_TOD_RX_TTYPE_CTRL_REG = 0x00040029ull;
+
+static const uint64_t P9N2_PERV_PIB_TOD_RX_TTYPE_CTRL_REG = 0x00040029ull;
+
+
+static const uint64_t P9N2_PERV_TOD_SEC_PORT_0_CTRL_REG = 0x00040003ull;
+
+static const uint64_t P9N2_PERV_PIB_TOD_SEC_PORT_0_CTRL_REG = 0x00040003ull;
+
+
+static const uint64_t P9N2_PERV_TOD_SEC_PORT_1_CTRL_REG = 0x00040004ull;
+
+static const uint64_t P9N2_PERV_PIB_TOD_SEC_PORT_1_CTRL_REG = 0x00040004ull;
+
+
+static const uint64_t P9N2_PERV_TOD_START_TOD_REG = 0x00040022ull;
+
+static const uint64_t P9N2_PERV_PIB_TOD_START_TOD_REG = 0x00040022ull;
+
+
+static const uint64_t P9N2_PERV_TOD_S_PATH_CTRL_REG = 0x00040005ull;
+
+static const uint64_t P9N2_PERV_PIB_TOD_S_PATH_CTRL_REG = 0x00040005ull;
+
+
+static const uint64_t P9N2_PERV_TOD_S_PATH_STATUS_REG = 0x0004000Aull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_PERV_PIB_TOD_S_PATH_STATUS_REG = 0x0004000Aull;
+
+
+static const uint64_t P9N2_PERV_TOD_TIMER_REG = 0x0004000Dull;
+
+static const uint64_t P9N2_PERV_PIB_TOD_TIMER_REG = 0x0004000Dull;
+
+
+static const uint64_t P9N2_PERV_TOD_TRACE_DATA_1_REG = 0x0004001Dull;
+
+static const uint64_t P9N2_PERV_PIB_TOD_TRACE_DATA_1_REG = 0x0004001Dull;
+
+
+static const uint64_t P9N2_PERV_TOD_TRACE_DATA_2_REG = 0x0004001Eull;
+
+static const uint64_t P9N2_PERV_PIB_TOD_TRACE_DATA_2_REG = 0x0004001Eull;
+
+
+static const uint64_t P9N2_PERV_TOD_TRACE_DATA_3_REG = 0x0004001Full;
+
+static const uint64_t P9N2_PERV_PIB_TOD_TRACE_DATA_3_REG = 0x0004001Full;
+
+
+static const uint64_t P9N2_PERV_TOD_TX_TTYPE_0_REG = 0x00040011ull;
+
+static const uint64_t P9N2_PERV_PIB_TOD_TX_TTYPE_0_REG = 0x00040011ull;
+
+
+static const uint64_t P9N2_PERV_TOD_TX_TTYPE_1_REG = 0x00040012ull;
+
+static const uint64_t P9N2_PERV_PIB_TOD_TX_TTYPE_1_REG = 0x00040012ull;
+
+
+static const uint64_t P9N2_PERV_TOD_TX_TTYPE_2_REG = 0x00040013ull;
+
+static const uint64_t P9N2_PERV_PIB_TOD_TX_TTYPE_2_REG = 0x00040013ull;
+
+
+static const uint64_t P9N2_PERV_TOD_TX_TTYPE_3_REG = 0x00040014ull;
+
+static const uint64_t P9N2_PERV_PIB_TOD_TX_TTYPE_3_REG = 0x00040014ull;
+
+
+static const uint64_t P9N2_PERV_TOD_TX_TTYPE_4_REG = 0x00040015ull;
+
+static const uint64_t P9N2_PERV_PIB_TOD_TX_TTYPE_4_REG = 0x00040015ull;
+
+
+static const uint64_t P9N2_PERV_TOD_TX_TTYPE_5_REG = 0x00040016ull;
+
+static const uint64_t P9N2_PERV_PIB_TOD_TX_TTYPE_5_REG = 0x00040016ull;
+
+
+static const uint64_t P9N2_PERV_TOD_TX_TTYPE_CTRL_REG = 0x00040027ull;
+
+static const uint64_t P9N2_PERV_PIB_TOD_TX_TTYPE_CTRL_REG = 0x00040027ull;
+
+
+static const uint64_t P9N2_PERV_TOD_VALUE_REG = 0x00040020ull;
+
+static const uint64_t P9N2_PERV_PIB_TOD_VALUE_REG = 0x00040020ull;
+
+
+static const uint64_t P9N2_PERV_TRACE_HI_DATA_REG = 0x00010440ull;
+
+static const uint64_t P9N2_PERV_TP_TRACE_HI_DATA_REG = 0x01010400ull;
+//DUPS: 01010400,
+
+static const uint64_t P9N2_PERV_TRACE_LO_DATA_REG = 0x00010441ull;
+
+static const uint64_t P9N2_PERV_TP_TRACE_LO_DATA_REG = 0x01010401ull;
+//DUPS: 01010401,
+
+static const uint64_t P9N2_PERV_TRACE_TRCTRL_CONFIG = 0x00010442ull;
+
+static const uint64_t P9N2_PERV_TP_TRACE_TRCTRL_CONFIG = 0x01010402ull;
+//DUPS: 01010402,
+
+static const uint64_t P9N2_PERV_TRACE_TRDATA_CONFIG_0 = 0x00010443ull;
+
+static const uint64_t P9N2_PERV_TP_TRACE_TRDATA_CONFIG_0 = 0x01010403ull;
+//DUPS: 01010403,
+
+static const uint64_t P9N2_PERV_TRACE_TRDATA_CONFIG_1 = 0x00010444ull;
+
+static const uint64_t P9N2_PERV_TP_TRACE_TRDATA_CONFIG_1 = 0x01010404ull;
+//DUPS: 01010404,
+
+static const uint64_t P9N2_PERV_TRACE_TRDATA_CONFIG_2 = 0x00010445ull;
+
+static const uint64_t P9N2_PERV_TP_TRACE_TRDATA_CONFIG_2 = 0x01010405ull;
+//DUPS: 01010405,
+
+static const uint64_t P9N2_PERV_TRACE_TRDATA_CONFIG_3 = 0x00010446ull;
+
+static const uint64_t P9N2_PERV_TP_TRACE_TRDATA_CONFIG_3 = 0x01010406ull;
+//DUPS: 01010406,
+
+static const uint64_t P9N2_PERV_TRACE_TRDATA_CONFIG_4 = 0x00010447ull;
+
+static const uint64_t P9N2_PERV_TP_TRACE_TRDATA_CONFIG_4 = 0x01010407ull;
+//DUPS: 01010407,
+
+static const uint64_t P9N2_PERV_TRACE_TRDATA_CONFIG_5 = 0x00010448ull;
+
+static const uint64_t P9N2_PERV_TP_TRACE_TRDATA_CONFIG_5 = 0x01010408ull;
+//DUPS: 01010408,
+
+static const uint64_t P9N2_PERV_TRACE_TRDATA_CONFIG_9 = 0x00010449ull;
+
+static const uint64_t P9N2_PERV_TP_TRACE_TRDATA_CONFIG_9 = 0x01010409ull;
+//DUPS: 01010409,
+
+static const uint32_t P9N2_PERV_FSI2PIB_TRUE_MASK_FSI = 0x0000100Dull;
+
+static const uint32_t P9N2_PERV_FSI2PIB_TRUE_MASK_FSI_BYTE = 0x00001034ull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_TRUE_MASK_FSI = 0x00000C0Dull;
+
+static const uint32_t P9N2_PERV_FSISHIFT_TRUE_MASK_FSI_BYTE = 0x00000C34ull;
+
+
+static const uint64_t P9N2_PERV_VITAL_SCAN_OUT = 0x000F0017ull;
+
+static const uint64_t P9N2_PERV_TP_VITAL_SCAN_OUT = 0x010F0017ull;
+
+static const uint64_t P9N2_PERV_N0_VITAL_SCAN_OUT = 0x020F0017ull;
+
+static const uint64_t P9N2_PERV_N1_VITAL_SCAN_OUT = 0x030F0017ull;
+
+static const uint64_t P9N2_PERV_N2_VITAL_SCAN_OUT = 0x040F0017ull;
+
+static const uint64_t P9N2_PERV_N3_VITAL_SCAN_OUT = 0x050F0017ull;
+
+static const uint64_t P9N2_PERV_XB_VITAL_SCAN_OUT = 0x060F0017ull;
+
+static const uint64_t P9N2_PERV_MC01_VITAL_SCAN_OUT = 0x070F0017ull;
+
+static const uint64_t P9N2_PERV_MC23_VITAL_SCAN_OUT = 0x080F0017ull;
+
+static const uint64_t P9N2_PERV_OB0_VITAL_SCAN_OUT = 0x090F0017ull;
+
+static const uint64_t P9N2_PERV_OB3_VITAL_SCAN_OUT = 0x0C0F0017ull;
+
+static const uint64_t P9N2_PERV_PCI0_VITAL_SCAN_OUT = 0x0D0F0017ull;
+
+static const uint64_t P9N2_PERV_PCI1_VITAL_SCAN_OUT = 0x0E0F0017ull;
+
+static const uint64_t P9N2_PERV_PCI2_VITAL_SCAN_OUT = 0x0F0F0017ull;
+
+static const uint64_t P9N2_PERV_EP00_VITAL_SCAN_OUT = 0x100F0017ull;
+
+static const uint64_t P9N2_PERV_EP01_VITAL_SCAN_OUT = 0x110F0017ull;
+
+static const uint64_t P9N2_PERV_EP02_VITAL_SCAN_OUT = 0x120F0017ull;
+
+static const uint64_t P9N2_PERV_EP03_VITAL_SCAN_OUT = 0x130F0017ull;
+
+static const uint64_t P9N2_PERV_EP04_VITAL_SCAN_OUT = 0x140F0017ull;
+
+static const uint64_t P9N2_PERV_EP05_VITAL_SCAN_OUT = 0x150F0017ull;
+
+static const uint64_t P9N2_PERV_EC00_VITAL_SCAN_OUT = 0x200F0017ull;
+
+static const uint64_t P9N2_PERV_EC01_VITAL_SCAN_OUT = 0x210F0017ull;
+
+static const uint64_t P9N2_PERV_EC02_VITAL_SCAN_OUT = 0x220F0017ull;
+
+static const uint64_t P9N2_PERV_EC03_VITAL_SCAN_OUT = 0x230F0017ull;
+
+static const uint64_t P9N2_PERV_EC04_VITAL_SCAN_OUT = 0x240F0017ull;
+
+static const uint64_t P9N2_PERV_EC05_VITAL_SCAN_OUT = 0x250F0017ull;
+
+static const uint64_t P9N2_PERV_EC06_VITAL_SCAN_OUT = 0x260F0017ull;
+
+static const uint64_t P9N2_PERV_EC07_VITAL_SCAN_OUT = 0x270F0017ull;
+
+static const uint64_t P9N2_PERV_EC08_VITAL_SCAN_OUT = 0x280F0017ull;
+
+static const uint64_t P9N2_PERV_EC09_VITAL_SCAN_OUT = 0x290F0017ull;
+
+static const uint64_t P9N2_PERV_EC10_VITAL_SCAN_OUT = 0x2A0F0017ull;
+
+static const uint64_t P9N2_PERV_EC11_VITAL_SCAN_OUT = 0x2B0F0017ull;
+
+static const uint64_t P9N2_PERV_EC12_VITAL_SCAN_OUT = 0x2C0F0017ull;
+
+static const uint64_t P9N2_PERV_EC13_VITAL_SCAN_OUT = 0x2D0F0017ull;
+
+static const uint64_t P9N2_PERV_EC14_VITAL_SCAN_OUT = 0x2E0F0017ull;
+
+static const uint64_t P9N2_PERV_EC15_VITAL_SCAN_OUT = 0x2F0F0017ull;
+
+static const uint64_t P9N2_PERV_EC16_VITAL_SCAN_OUT = 0x300F0017ull;
+
+static const uint64_t P9N2_PERV_EC17_VITAL_SCAN_OUT = 0x310F0017ull;
+
+static const uint64_t P9N2_PERV_EC18_VITAL_SCAN_OUT = 0x320F0017ull;
+
+static const uint64_t P9N2_PERV_EC19_VITAL_SCAN_OUT = 0x330F0017ull;
+
+static const uint64_t P9N2_PERV_EC20_VITAL_SCAN_OUT = 0x340F0017ull;
+
+static const uint64_t P9N2_PERV_EC21_VITAL_SCAN_OUT = 0x350F0017ull;
+
+static const uint64_t P9N2_PERV_EC22_VITAL_SCAN_OUT = 0x360F0017ull;
+
+static const uint64_t P9N2_PERV_EC23_VITAL_SCAN_OUT = 0x370F0017ull;
+
+
+static const uint64_t P9N2_PERV_VMEAS_RESULT_REG = 0x00020006ull;
+
+static const uint64_t P9N2_PERV_TP_VMEAS_RESULT_REG = 0x01020006ull;
+
+
+static const uint64_t P9N2_PERV_0_FSII2C_WATER_MARK_REGISTER_A = 0x00001803ull;
+
+static const uint32_t P9N2_PERV_FSII2C_WATER_MARK_REGISTER_A = 0x00001803ull;
+
+
+static const uint64_t P9N2_PERV_WRITE_PROTECT_ENABLE_REG = 0x00010005ull;
+
+static const uint64_t P9N2_PERV_TP_WRITE_PROTECT_ENABLE_REG = 0x01010005ull;
+
+
+static const uint64_t P9N2_PERV_WRITE_PROTECT_RINGS_REG = 0x00010006ull;
+
+static const uint64_t P9N2_PERV_TP_WRITE_PROTECT_RINGS_REG = 0x01010006ull;
+
+
+static const uint64_t P9N2_PERV_XFIR = 0x00040000ull;
+
+static const uint64_t P9N2_PERV_TP_XFIR = 0x01040000ull;
+
+static const uint64_t P9N2_PERV_N0_XFIR = 0x02040000ull;
+
+static const uint64_t P9N2_PERV_N1_XFIR = 0x03040000ull;
+
+static const uint64_t P9N2_PERV_N2_XFIR = 0x04040000ull;
+
+static const uint64_t P9N2_PERV_N3_XFIR = 0x05040000ull;
+
+static const uint64_t P9N2_PERV_XB_XFIR = 0x06040000ull;
+
+static const uint64_t P9N2_PERV_MC01_XFIR = 0x07040000ull;
+
+static const uint64_t P9N2_PERV_MC23_XFIR = 0x08040000ull;
+
+static const uint64_t P9N2_PERV_OB0_XFIR = 0x09040000ull;
+
+static const uint64_t P9N2_PERV_OB3_XFIR = 0x0C040000ull;
+
+static const uint64_t P9N2_PERV_PCI0_XFIR = 0x0D040000ull;
+
+static const uint64_t P9N2_PERV_PCI1_XFIR = 0x0E040000ull;
+
+static const uint64_t P9N2_PERV_PCI2_XFIR = 0x0F040000ull;
+
+static const uint64_t P9N2_PERV_EP00_XFIR = 0x10040000ull;
+
+static const uint64_t P9N2_PERV_EP01_XFIR = 0x11040000ull;
+
+static const uint64_t P9N2_PERV_EP02_XFIR = 0x12040000ull;
+
+static const uint64_t P9N2_PERV_EP03_XFIR = 0x13040000ull;
+
+static const uint64_t P9N2_PERV_EP04_XFIR = 0x14040000ull;
+
+static const uint64_t P9N2_PERV_EP05_XFIR = 0x15040000ull;
+
+static const uint64_t P9N2_PERV_EC00_XFIR = 0x20040000ull;
+
+static const uint64_t P9N2_PERV_EC01_XFIR = 0x21040000ull;
+
+static const uint64_t P9N2_PERV_EC02_XFIR = 0x22040000ull;
+
+static const uint64_t P9N2_PERV_EC03_XFIR = 0x23040000ull;
+
+static const uint64_t P9N2_PERV_EC04_XFIR = 0x24040000ull;
+
+static const uint64_t P9N2_PERV_EC05_XFIR = 0x25040000ull;
+
+static const uint64_t P9N2_PERV_EC06_XFIR = 0x26040000ull;
+
+static const uint64_t P9N2_PERV_EC07_XFIR = 0x27040000ull;
+
+static const uint64_t P9N2_PERV_EC08_XFIR = 0x28040000ull;
+
+static const uint64_t P9N2_PERV_EC09_XFIR = 0x29040000ull;
+
+static const uint64_t P9N2_PERV_EC10_XFIR = 0x2A040000ull;
+
+static const uint64_t P9N2_PERV_EC11_XFIR = 0x2B040000ull;
+
+static const uint64_t P9N2_PERV_EC12_XFIR = 0x2C040000ull;
+
+static const uint64_t P9N2_PERV_EC13_XFIR = 0x2D040000ull;
+
+static const uint64_t P9N2_PERV_EC14_XFIR = 0x2E040000ull;
+
+static const uint64_t P9N2_PERV_EC15_XFIR = 0x2F040000ull;
+
+static const uint64_t P9N2_PERV_EC16_XFIR = 0x30040000ull;
+
+static const uint64_t P9N2_PERV_EC17_XFIR = 0x31040000ull;
+
+static const uint64_t P9N2_PERV_EC18_XFIR = 0x32040000ull;
+
+static const uint64_t P9N2_PERV_EC19_XFIR = 0x33040000ull;
+
+static const uint64_t P9N2_PERV_EC20_XFIR = 0x34040000ull;
+
+static const uint64_t P9N2_PERV_EC21_XFIR = 0x35040000ull;
+
+static const uint64_t P9N2_PERV_EC22_XFIR = 0x36040000ull;
+
+static const uint64_t P9N2_PERV_EC23_XFIR = 0x37040000ull;
+
+
+static const uint64_t P9N2_PERV_XSTOP1 = 0x0003000Cull;
+
+static const uint64_t P9N2_PERV_TP_XSTOP1 = 0x0103000Cull;
+
+static const uint64_t P9N2_PERV_N0_XSTOP1 = 0x0203000Cull;
+
+static const uint64_t P9N2_PERV_N1_XSTOP1 = 0x0303000Cull;
+
+static const uint64_t P9N2_PERV_N2_XSTOP1 = 0x0403000Cull;
+
+static const uint64_t P9N2_PERV_N3_XSTOP1 = 0x0503000Cull;
+
+static const uint64_t P9N2_PERV_XB_XSTOP1 = 0x0603000Cull;
+
+static const uint64_t P9N2_PERV_MC01_XSTOP1 = 0x0703000Cull;
+
+static const uint64_t P9N2_PERV_MC23_XSTOP1 = 0x0803000Cull;
+
+static const uint64_t P9N2_PERV_OB0_XSTOP1 = 0x0903000Cull;
+
+static const uint64_t P9N2_PERV_OB3_XSTOP1 = 0x0C03000Cull;
+
+static const uint64_t P9N2_PERV_PCI0_XSTOP1 = 0x0D03000Cull;
+
+static const uint64_t P9N2_PERV_PCI1_XSTOP1 = 0x0E03000Cull;
+
+static const uint64_t P9N2_PERV_PCI2_XSTOP1 = 0x0F03000Cull;
+
+static const uint64_t P9N2_PERV_EP00_XSTOP1 = 0x1003000Cull;
+
+static const uint64_t P9N2_PERV_EP01_XSTOP1 = 0x1103000Cull;
+
+static const uint64_t P9N2_PERV_EP02_XSTOP1 = 0x1203000Cull;
+
+static const uint64_t P9N2_PERV_EP03_XSTOP1 = 0x1303000Cull;
+
+static const uint64_t P9N2_PERV_EP04_XSTOP1 = 0x1403000Cull;
+
+static const uint64_t P9N2_PERV_EP05_XSTOP1 = 0x1503000Cull;
+
+static const uint64_t P9N2_PERV_EC00_XSTOP1 = 0x2003000Cull;
+
+static const uint64_t P9N2_PERV_EC01_XSTOP1 = 0x2103000Cull;
+
+static const uint64_t P9N2_PERV_EC02_XSTOP1 = 0x2203000Cull;
+
+static const uint64_t P9N2_PERV_EC03_XSTOP1 = 0x2303000Cull;
+
+static const uint64_t P9N2_PERV_EC04_XSTOP1 = 0x2403000Cull;
+
+static const uint64_t P9N2_PERV_EC05_XSTOP1 = 0x2503000Cull;
+
+static const uint64_t P9N2_PERV_EC06_XSTOP1 = 0x2603000Cull;
+
+static const uint64_t P9N2_PERV_EC07_XSTOP1 = 0x2703000Cull;
+
+static const uint64_t P9N2_PERV_EC08_XSTOP1 = 0x2803000Cull;
+
+static const uint64_t P9N2_PERV_EC09_XSTOP1 = 0x2903000Cull;
+
+static const uint64_t P9N2_PERV_EC10_XSTOP1 = 0x2A03000Cull;
+
+static const uint64_t P9N2_PERV_EC11_XSTOP1 = 0x2B03000Cull;
+
+static const uint64_t P9N2_PERV_EC12_XSTOP1 = 0x2C03000Cull;
+
+static const uint64_t P9N2_PERV_EC13_XSTOP1 = 0x2D03000Cull;
+
+static const uint64_t P9N2_PERV_EC14_XSTOP1 = 0x2E03000Cull;
+
+static const uint64_t P9N2_PERV_EC15_XSTOP1 = 0x2F03000Cull;
+
+static const uint64_t P9N2_PERV_EC16_XSTOP1 = 0x3003000Cull;
+
+static const uint64_t P9N2_PERV_EC17_XSTOP1 = 0x3103000Cull;
+
+static const uint64_t P9N2_PERV_EC18_XSTOP1 = 0x3203000Cull;
+
+static const uint64_t P9N2_PERV_EC19_XSTOP1 = 0x3303000Cull;
+
+static const uint64_t P9N2_PERV_EC20_XSTOP1 = 0x3403000Cull;
+
+static const uint64_t P9N2_PERV_EC21_XSTOP1 = 0x3503000Cull;
+
+static const uint64_t P9N2_PERV_EC22_XSTOP1 = 0x3603000Cull;
+
+static const uint64_t P9N2_PERV_EC23_XSTOP1 = 0x3703000Cull;
+
+
+static const uint64_t P9N2_PERV_XSTOP2 = 0x0003000Dull;
+
+static const uint64_t P9N2_PERV_TP_XSTOP2 = 0x0103000Dull;
+
+static const uint64_t P9N2_PERV_N0_XSTOP2 = 0x0203000Dull;
+
+static const uint64_t P9N2_PERV_N1_XSTOP2 = 0x0303000Dull;
+
+static const uint64_t P9N2_PERV_N2_XSTOP2 = 0x0403000Dull;
+
+static const uint64_t P9N2_PERV_N3_XSTOP2 = 0x0503000Dull;
+
+static const uint64_t P9N2_PERV_XB_XSTOP2 = 0x0603000Dull;
+
+static const uint64_t P9N2_PERV_MC01_XSTOP2 = 0x0703000Dull;
+
+static const uint64_t P9N2_PERV_MC23_XSTOP2 = 0x0803000Dull;
+
+static const uint64_t P9N2_PERV_OB0_XSTOP2 = 0x0903000Dull;
+
+static const uint64_t P9N2_PERV_OB3_XSTOP2 = 0x0C03000Dull;
+
+static const uint64_t P9N2_PERV_PCI0_XSTOP2 = 0x0D03000Dull;
+
+static const uint64_t P9N2_PERV_PCI1_XSTOP2 = 0x0E03000Dull;
+
+static const uint64_t P9N2_PERV_PCI2_XSTOP2 = 0x0F03000Dull;
+
+static const uint64_t P9N2_PERV_EP00_XSTOP2 = 0x1003000Dull;
+
+static const uint64_t P9N2_PERV_EP01_XSTOP2 = 0x1103000Dull;
+
+static const uint64_t P9N2_PERV_EP02_XSTOP2 = 0x1203000Dull;
+
+static const uint64_t P9N2_PERV_EP03_XSTOP2 = 0x1303000Dull;
+
+static const uint64_t P9N2_PERV_EP04_XSTOP2 = 0x1403000Dull;
+
+static const uint64_t P9N2_PERV_EP05_XSTOP2 = 0x1503000Dull;
+
+static const uint64_t P9N2_PERV_EC00_XSTOP2 = 0x2003000Dull;
+
+static const uint64_t P9N2_PERV_EC01_XSTOP2 = 0x2103000Dull;
+
+static const uint64_t P9N2_PERV_EC02_XSTOP2 = 0x2203000Dull;
+
+static const uint64_t P9N2_PERV_EC03_XSTOP2 = 0x2303000Dull;
+
+static const uint64_t P9N2_PERV_EC04_XSTOP2 = 0x2403000Dull;
+
+static const uint64_t P9N2_PERV_EC05_XSTOP2 = 0x2503000Dull;
+
+static const uint64_t P9N2_PERV_EC06_XSTOP2 = 0x2603000Dull;
+
+static const uint64_t P9N2_PERV_EC07_XSTOP2 = 0x2703000Dull;
+
+static const uint64_t P9N2_PERV_EC08_XSTOP2 = 0x2803000Dull;
+
+static const uint64_t P9N2_PERV_EC09_XSTOP2 = 0x2903000Dull;
+
+static const uint64_t P9N2_PERV_EC10_XSTOP2 = 0x2A03000Dull;
+
+static const uint64_t P9N2_PERV_EC11_XSTOP2 = 0x2B03000Dull;
+
+static const uint64_t P9N2_PERV_EC12_XSTOP2 = 0x2C03000Dull;
+
+static const uint64_t P9N2_PERV_EC13_XSTOP2 = 0x2D03000Dull;
+
+static const uint64_t P9N2_PERV_EC14_XSTOP2 = 0x2E03000Dull;
+
+static const uint64_t P9N2_PERV_EC15_XSTOP2 = 0x2F03000Dull;
+
+static const uint64_t P9N2_PERV_EC16_XSTOP2 = 0x3003000Dull;
+
+static const uint64_t P9N2_PERV_EC17_XSTOP2 = 0x3103000Dull;
+
+static const uint64_t P9N2_PERV_EC18_XSTOP2 = 0x3203000Dull;
+
+static const uint64_t P9N2_PERV_EC19_XSTOP2 = 0x3303000Dull;
+
+static const uint64_t P9N2_PERV_EC20_XSTOP2 = 0x3403000Dull;
+
+static const uint64_t P9N2_PERV_EC21_XSTOP2 = 0x3503000Dull;
+
+static const uint64_t P9N2_PERV_EC22_XSTOP2 = 0x3603000Dull;
+
+static const uint64_t P9N2_PERV_EC23_XSTOP2 = 0x3703000Dull;
+
+
+static const uint64_t P9N2_PERV_XSTOP3 = 0x0003000Eull;
+
+static const uint64_t P9N2_PERV_TP_XSTOP3 = 0x0103000Eull;
+
+static const uint64_t P9N2_PERV_N0_XSTOP3 = 0x0203000Eull;
+
+static const uint64_t P9N2_PERV_N1_XSTOP3 = 0x0303000Eull;
+
+static const uint64_t P9N2_PERV_N2_XSTOP3 = 0x0403000Eull;
+
+static const uint64_t P9N2_PERV_N3_XSTOP3 = 0x0503000Eull;
+
+static const uint64_t P9N2_PERV_XB_XSTOP3 = 0x0603000Eull;
+
+static const uint64_t P9N2_PERV_MC01_XSTOP3 = 0x0703000Eull;
+
+static const uint64_t P9N2_PERV_MC23_XSTOP3 = 0x0803000Eull;
+
+static const uint64_t P9N2_PERV_OB0_XSTOP3 = 0x0903000Eull;
+
+static const uint64_t P9N2_PERV_OB3_XSTOP3 = 0x0C03000Eull;
+
+static const uint64_t P9N2_PERV_PCI0_XSTOP3 = 0x0D03000Eull;
+
+static const uint64_t P9N2_PERV_PCI1_XSTOP3 = 0x0E03000Eull;
+
+static const uint64_t P9N2_PERV_PCI2_XSTOP3 = 0x0F03000Eull;
+
+static const uint64_t P9N2_PERV_EP00_XSTOP3 = 0x1003000Eull;
+
+static const uint64_t P9N2_PERV_EP01_XSTOP3 = 0x1103000Eull;
+
+static const uint64_t P9N2_PERV_EP02_XSTOP3 = 0x1203000Eull;
+
+static const uint64_t P9N2_PERV_EP03_XSTOP3 = 0x1303000Eull;
+
+static const uint64_t P9N2_PERV_EP04_XSTOP3 = 0x1403000Eull;
+
+static const uint64_t P9N2_PERV_EP05_XSTOP3 = 0x1503000Eull;
+
+static const uint64_t P9N2_PERV_EC00_XSTOP3 = 0x2003000Eull;
+
+static const uint64_t P9N2_PERV_EC01_XSTOP3 = 0x2103000Eull;
+
+static const uint64_t P9N2_PERV_EC02_XSTOP3 = 0x2203000Eull;
+
+static const uint64_t P9N2_PERV_EC03_XSTOP3 = 0x2303000Eull;
+
+static const uint64_t P9N2_PERV_EC04_XSTOP3 = 0x2403000Eull;
+
+static const uint64_t P9N2_PERV_EC05_XSTOP3 = 0x2503000Eull;
+
+static const uint64_t P9N2_PERV_EC06_XSTOP3 = 0x2603000Eull;
+
+static const uint64_t P9N2_PERV_EC07_XSTOP3 = 0x2703000Eull;
+
+static const uint64_t P9N2_PERV_EC08_XSTOP3 = 0x2803000Eull;
+
+static const uint64_t P9N2_PERV_EC09_XSTOP3 = 0x2903000Eull;
+
+static const uint64_t P9N2_PERV_EC10_XSTOP3 = 0x2A03000Eull;
+
+static const uint64_t P9N2_PERV_EC11_XSTOP3 = 0x2B03000Eull;
+
+static const uint64_t P9N2_PERV_EC12_XSTOP3 = 0x2C03000Eull;
+
+static const uint64_t P9N2_PERV_EC13_XSTOP3 = 0x2D03000Eull;
+
+static const uint64_t P9N2_PERV_EC14_XSTOP3 = 0x2E03000Eull;
+
+static const uint64_t P9N2_PERV_EC15_XSTOP3 = 0x2F03000Eull;
+
+static const uint64_t P9N2_PERV_EC16_XSTOP3 = 0x3003000Eull;
+
+static const uint64_t P9N2_PERV_EC17_XSTOP3 = 0x3103000Eull;
+
+static const uint64_t P9N2_PERV_EC18_XSTOP3 = 0x3203000Eull;
+
+static const uint64_t P9N2_PERV_EC19_XSTOP3 = 0x3303000Eull;
+
+static const uint64_t P9N2_PERV_EC20_XSTOP3 = 0x3403000Eull;
+
+static const uint64_t P9N2_PERV_EC21_XSTOP3 = 0x3503000Eull;
+
+static const uint64_t P9N2_PERV_EC22_XSTOP3 = 0x3603000Eull;
+
+static const uint64_t P9N2_PERV_EC23_XSTOP3 = 0x3703000Eull;
+
+
+static const uint64_t P9N2_PERV_XSTOP_INTERRUPT_REG = 0x000F001Cull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_PERV_TP_XSTOP_INTERRUPT_REG = 0x010F001Cull;
+
+static const uint64_t P9N2_PERV_N0_XSTOP_INTERRUPT_REG = 0x020F001Cull;
+
+static const uint64_t P9N2_PERV_N1_XSTOP_INTERRUPT_REG = 0x030F001Cull;
+
+static const uint64_t P9N2_PERV_N2_XSTOP_INTERRUPT_REG = 0x040F001Cull;
+
+static const uint64_t P9N2_PERV_N3_XSTOP_INTERRUPT_REG = 0x050F001Cull;
+
+static const uint64_t P9N2_PERV_XB_XSTOP_INTERRUPT_REG = 0x060F001Cull;
+
+static const uint64_t P9N2_PERV_MC01_XSTOP_INTERRUPT_REG = 0x070F001Cull;
+
+static const uint64_t P9N2_PERV_MC23_XSTOP_INTERRUPT_REG = 0x080F001Cull;
+
+static const uint64_t P9N2_PERV_OB0_XSTOP_INTERRUPT_REG = 0x090F001Cull;
+
+static const uint64_t P9N2_PERV_OB3_XSTOP_INTERRUPT_REG = 0x0C0F001Cull;
+
+static const uint64_t P9N2_PERV_PCI0_XSTOP_INTERRUPT_REG = 0x0D0F001Cull;
+
+static const uint64_t P9N2_PERV_PCI1_XSTOP_INTERRUPT_REG = 0x0E0F001Cull;
+
+static const uint64_t P9N2_PERV_PCI2_XSTOP_INTERRUPT_REG = 0x0F0F001Cull;
+
+static const uint64_t P9N2_PERV_EP00_XSTOP_INTERRUPT_REG = 0x100F001Cull;
+
+static const uint64_t P9N2_PERV_EP01_XSTOP_INTERRUPT_REG = 0x110F001Cull;
+
+static const uint64_t P9N2_PERV_EP02_XSTOP_INTERRUPT_REG = 0x120F001Cull;
+
+static const uint64_t P9N2_PERV_EP03_XSTOP_INTERRUPT_REG = 0x130F001Cull;
+
+static const uint64_t P9N2_PERV_EP04_XSTOP_INTERRUPT_REG = 0x140F001Cull;
+
+static const uint64_t P9N2_PERV_EP05_XSTOP_INTERRUPT_REG = 0x150F001Cull;
+
+static const uint64_t P9N2_PERV_EC00_XSTOP_INTERRUPT_REG = 0x200F001Cull;
+
+static const uint64_t P9N2_PERV_EC01_XSTOP_INTERRUPT_REG = 0x210F001Cull;
+
+static const uint64_t P9N2_PERV_EC02_XSTOP_INTERRUPT_REG = 0x220F001Cull;
+
+static const uint64_t P9N2_PERV_EC03_XSTOP_INTERRUPT_REG = 0x230F001Cull;
+
+static const uint64_t P9N2_PERV_EC04_XSTOP_INTERRUPT_REG = 0x240F001Cull;
+
+static const uint64_t P9N2_PERV_EC05_XSTOP_INTERRUPT_REG = 0x250F001Cull;
+
+static const uint64_t P9N2_PERV_EC06_XSTOP_INTERRUPT_REG = 0x260F001Cull;
+
+static const uint64_t P9N2_PERV_EC07_XSTOP_INTERRUPT_REG = 0x270F001Cull;
+
+static const uint64_t P9N2_PERV_EC08_XSTOP_INTERRUPT_REG = 0x280F001Cull;
+
+static const uint64_t P9N2_PERV_EC09_XSTOP_INTERRUPT_REG = 0x290F001Cull;
+
+static const uint64_t P9N2_PERV_EC10_XSTOP_INTERRUPT_REG = 0x2A0F001Cull;
+
+static const uint64_t P9N2_PERV_EC11_XSTOP_INTERRUPT_REG = 0x2B0F001Cull;
+
+static const uint64_t P9N2_PERV_EC12_XSTOP_INTERRUPT_REG = 0x2C0F001Cull;
+
+static const uint64_t P9N2_PERV_EC13_XSTOP_INTERRUPT_REG = 0x2D0F001Cull;
+
+static const uint64_t P9N2_PERV_EC14_XSTOP_INTERRUPT_REG = 0x2E0F001Cull;
+
+static const uint64_t P9N2_PERV_EC15_XSTOP_INTERRUPT_REG = 0x2F0F001Cull;
+
+static const uint64_t P9N2_PERV_EC16_XSTOP_INTERRUPT_REG = 0x300F001Cull;
+
+static const uint64_t P9N2_PERV_EC17_XSTOP_INTERRUPT_REG = 0x310F001Cull;
+
+static const uint64_t P9N2_PERV_EC18_XSTOP_INTERRUPT_REG = 0x320F001Cull;
+
+static const uint64_t P9N2_PERV_EC19_XSTOP_INTERRUPT_REG = 0x330F001Cull;
+
+static const uint64_t P9N2_PERV_EC20_XSTOP_INTERRUPT_REG = 0x340F001Cull;
+
+static const uint64_t P9N2_PERV_EC21_XSTOP_INTERRUPT_REG = 0x350F001Cull;
+
+static const uint64_t P9N2_PERV_EC22_XSTOP_INTERRUPT_REG = 0x360F001Cull;
+
+static const uint64_t P9N2_PERV_EC23_XSTOP_INTERRUPT_REG = 0x370F001Cull;
+
+
+static const uint64_t P9N2_PERV_XTRA_TRACE_MODE = 0x000107D1ull;
+
+static const uint64_t P9N2_PERV_TP_XTRA_TRACE_MODE = 0x010107D1ull;
+
+#endif
+
diff --git a/src/import/chips/p9/common/include/p9n2_perv_scom_addresses_fld.H b/src/import/chips/p9/common/include/p9n2_perv_scom_addresses_fld.H
new file mode 100644
index 000000000..7f0ba8663
--- /dev/null
+++ b/src/import/chips/p9/common/include/p9n2_perv_scom_addresses_fld.H
@@ -0,0 +1,5855 @@
+/* IBM_PROLOG_BEGIN_TAG */
+/* This is an automatically generated prolog. */
+/* */
+/* $Source: src/import/chips/p9/common/include/p9n2_perv_scom_addresses_fld.H $ */
+/* */
+/* OpenPOWER HostBoot Project */
+/* */
+/* Contributors Listed Below - COPYRIGHT 2017 */
+/* [+] International Business Machines Corp. */
+/* */
+/* */
+/* Licensed under the Apache License, Version 2.0 (the "License"); */
+/* you may not use this file except in compliance with the License. */
+/* You may obtain a copy of the License at */
+/* */
+/* http://www.apache.org/licenses/LICENSE-2.0 */
+/* */
+/* Unless required by applicable law or agreed to in writing, software */
+/* distributed under the License is distributed on an "AS IS" BASIS, */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */
+/* implied. See the License for the specific language governing */
+/* permissions and limitations under the License. */
+/* */
+/* IBM_PROLOG_END_TAG */
+///
+/// @file p9_perv_scom_addresses_fld.H
+/// @brief Defines constants for scom addresses
+///
+// *HWP HWP Owner: Ben Gass <bgass@us.ibm.com>
+// *HWP FW Owner: Thi Tran <thi@us.ibm.com>
+// *HWP Team: SOA
+// *HWP Level: 1
+// *HWP Consumed by: FSP:HB:HS:OCC:SBE:CME:SGPE:PGPE:FPPE:IPPE
+
+#ifndef __P9N2_PERV_SCOM_ADDRESSES_FLD_H
+#define __P9N2_PERV_SCOM_ADDRESSES_FLD_H
+
+#include <stdint.h>
+
+static const uint8_t P9N2_PERV_1_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR = 0 ;
+static const uint8_t P9N2_PERV_1_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN = 16 ;
+static const uint8_t P9N2_PERV_1_ADDR_TRAP_REG_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR = 16 ;
+static const uint8_t P9N2_PERV_1_ADDR_TRAP_REG_RESERVED_LAST_LT = 17 ;
+static const uint8_t P9N2_PERV_1_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR = 18 ;
+static const uint8_t P9N2_PERV_1_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN = 13 ;
+static const uint8_t P9N2_PERV_1_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY = 31 ;
+static const uint8_t P9N2_PERV_1_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR = 32 ;
+static const uint8_t P9N2_PERV_1_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION = 33 ;
+static const uint8_t P9N2_PERV_1_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER = 34 ;
+
+static const uint8_t P9N2_PERV_1_ASSIST_INTERRUPT_REG_ATTN = 0 ;
+static const uint8_t P9N2_PERV_1_ASSIST_INTERRUPT_REG_RECOV = 1 ;
+static const uint8_t P9N2_PERV_1_ASSIST_INTERRUPT_REG_XSTOP = 2 ;
+
+static const uint8_t P9N2_PERV_1_ATOMIC_LOCK_MASK_LATCH_REG_MASK = 0 ;
+static const uint8_t P9N2_PERV_1_ATOMIC_LOCK_MASK_LATCH_REG_MASK_LEN = 16 ;
+
+static const uint8_t P9N2_PERV_1_ATOMIC_LOCK_REG_ENABLE = 0 ;
+static const uint8_t P9N2_PERV_1_ATOMIC_LOCK_REG_ID = 1 ;
+static const uint8_t P9N2_PERV_1_ATOMIC_LOCK_REG_ID_LEN = 4 ;
+static const uint8_t P9N2_PERV_1_ATOMIC_LOCK_REG_ACTIVITY = 8 ;
+static const uint8_t P9N2_PERV_1_ATOMIC_LOCK_REG_ACTIVITY_LEN = 8 ;
+
+static const uint8_t P9N2_PERV_1_ATTN_INTERRUPT_REG_ATTN = 0 ;
+
+static const uint8_t P9N2_PERV_1_BIST_TC_START_TEST_DC = 0 ;
+static const uint8_t P9N2_PERV_1_BIST_TC_SRAM_ABIST_MODE_DC = 1 ;
+static const uint8_t P9N2_PERV_1_BIST_TC_EDRAM_ABIST_MODE_DC = 2 ;
+static const uint8_t P9N2_PERV_1_BIST_TC_IOBIST_MODE_DC = 3 ;
+static const uint8_t P9N2_PERV_1_BIST_PERV = 4 ;
+static const uint8_t P9N2_PERV_1_BIST_UNIT1 = 5 ;
+static const uint8_t P9N2_PERV_1_BIST_UNIT2 = 6 ;
+static const uint8_t P9N2_PERV_1_BIST_UNIT3 = 7 ;
+static const uint8_t P9N2_PERV_1_BIST_UNIT4 = 8 ;
+static const uint8_t P9N2_PERV_1_BIST_UNIT5 = 9 ;
+static const uint8_t P9N2_PERV_1_BIST_UNIT6 = 10 ;
+static const uint8_t P9N2_PERV_1_BIST_UNIT7 = 11 ;
+static const uint8_t P9N2_PERV_1_BIST_UNIT8 = 12 ;
+static const uint8_t P9N2_PERV_1_BIST_UNIT9 = 13 ;
+static const uint8_t P9N2_PERV_1_BIST_UNIT10 = 14 ;
+static const uint8_t P9N2_PERV_1_BIST_STROBE_WINDOW_EN = 48 ;
+
+static const uint8_t P9N2_PERV_BIT_SEL_REG_2_SELECT_REGISTER_FSP2PIB = 0 ;
+static const uint8_t P9N2_PERV_BIT_SEL_REG_2_SELECT_REGISTER_FSP2PIB_LEN = 6 ;
+
+static const uint8_t P9N2_PERV_CBS_CS_START_BOOT_SEQUENCER = 0 ;
+static const uint8_t P9N2_PERV_CBS_CS_1_UNUSED = 1 ;
+static const uint8_t P9N2_PERV_CBS_CS_OPTION_SKIP_SCAN0_CLOCKSTART = 2 ;
+static const uint8_t P9N2_PERV_CBS_CS_OPTION_PREVENT_SBE_START = 3 ;
+static const uint8_t P9N2_PERV_CBS_CS_SECURE_ACCESS_BIT = 4 ;
+static const uint8_t P9N2_PERV_CBS_CS_SAMPLED_SMD_PIN = 5 ;
+static const uint8_t P9N2_PERV_CBS_CS_STATE_MACHINE_TRANSITION_DELAY = 6 ;
+static const uint8_t P9N2_PERV_CBS_CS_STATE_MACHINE_TRANSITION_DELAY_LEN = 10 ;
+static const uint8_t P9N2_PERV_CBS_CS_INTERNAL_STATE_VECTOR = 16 ;
+static const uint8_t P9N2_PERV_CBS_CS_INTERNAL_STATE_VECTOR_LEN = 16 ;
+
+static const uint8_t P9N2_PERV_CBS_ENVSTAT_C4_TEST_ENABLE = 0 ;
+static const uint8_t P9N2_PERV_CBS_ENVSTAT_C4_CARD_TEST_BSC = 1 ;
+static const uint8_t P9N2_PERV_CBS_ENVSTAT_C4_VDN_GPOOD = 2 ;
+static const uint8_t P9N2_PERV_CBS_ENVSTAT_C4_FSI_IN_ENA = 3 ;
+static const uint8_t P9N2_PERV_CBS_ENVSTAT_C4_CHIP_MASTER = 4 ;
+static const uint8_t P9N2_PERV_CBS_ENVSTAT_C4_SMD = 5 ;
+static const uint8_t P9N2_PERV_CBS_ENVSTAT_C4_JTAG_TMS = 6 ;
+static const uint8_t P9N2_PERV_CBS_ENVSTAT_CBS_ENVSTAT_REMAINDER = 7 ;
+static const uint8_t P9N2_PERV_CBS_ENVSTAT_CBS_ENVSTAT_REMAINDER_LEN = 25 ;
+
+static const uint8_t P9N2_PERV_CBS_STAT_DBG_RESET_EP = 0 ;
+static const uint8_t P9N2_PERV_CBS_STAT_DBG_OPCG_IP = 1 ;
+static const uint8_t P9N2_PERV_CBS_STAT_DBG_VITL_CLKOFF = 2 ;
+static const uint8_t P9N2_PERV_CBS_STAT_DBG_TEST_ENABLE = 3 ;
+static const uint8_t P9N2_PERV_CBS_STAT_DBG_REQ = 4 ;
+static const uint8_t P9N2_PERV_CBS_STAT_DBG_CMD = 5 ;
+static const uint8_t P9N2_PERV_CBS_STAT_DBG_CMD_LEN = 3 ;
+static const uint8_t P9N2_PERV_CBS_STAT_DBG_STATE = 8 ;
+static const uint8_t P9N2_PERV_CBS_STAT_DBG_STATE_LEN = 5 ;
+static const uint8_t P9N2_PERV_CBS_STAT_DBG_SECURITY_DEBUG_MODE = 13 ;
+static const uint8_t P9N2_PERV_CBS_STAT_DBG_PROTOCOL_ERROR = 14 ;
+static const uint8_t P9N2_PERV_CBS_STAT_DBG_PCB_IDLE = 15 ;
+static const uint8_t P9N2_PERV_CBS_STAT_DBG_CURRENT_OPCG_MODE = 16 ;
+static const uint8_t P9N2_PERV_CBS_STAT_DBG_CURRENT_OPCG_MODE_LEN = 4 ;
+static const uint8_t P9N2_PERV_CBS_STAT_DBG_LAST_OPCG_MODE = 20 ;
+static const uint8_t P9N2_PERV_CBS_STAT_DBG_LAST_OPCG_MODE_LEN = 4 ;
+static const uint8_t P9N2_PERV_CBS_STAT_DBG_PCB_ERROR = 24 ;
+static const uint8_t P9N2_PERV_CBS_STAT_DBG_PARITY_ERROR = 25 ;
+static const uint8_t P9N2_PERV_CBS_STAT_DBG_CC_ERROR = 26 ;
+static const uint8_t P9N2_PERV_CBS_STAT_DBG_CHIPLET_IS_ALIGNED = 27 ;
+static const uint8_t P9N2_PERV_CBS_STAT_DBG_PCB_REQUEST_SINCE_RESET = 28 ;
+static const uint8_t P9N2_PERV_CBS_STAT_DBG_PARANOIA_TEST_ENABLE_CHANGE = 29 ;
+static const uint8_t P9N2_PERV_CBS_STAT_DBG_PARANOIA_VITL_CLKOFF_CHANGE = 30 ;
+static const uint8_t P9N2_PERV_CBS_STAT_DBG_TP_TPFSI_ACK = 31 ;
+
+static const uint8_t P9N2_PERV_CBS_TR_SIGNATURE = 0 ;
+static const uint8_t P9N2_PERV_CBS_TR_SIGNATURE_LEN = 16 ;
+static const uint8_t P9N2_PERV_CBS_TR_UNUSED = 16 ;
+static const uint8_t P9N2_PERV_CBS_TR_UNUSED_LEN = 6 ;
+static const uint8_t P9N2_PERV_CBS_TR_TRANS_DELAY = 22 ;
+static const uint8_t P9N2_PERV_CBS_TR_TRANS_DELAY_LEN = 10 ;
+
+static const uint8_t P9N2_PERV_1_CC_ATOMIC_LOCK_REG_ENABLE = 0 ;
+static const uint8_t P9N2_PERV_1_CC_ATOMIC_LOCK_REG_ID = 1 ;
+static const uint8_t P9N2_PERV_1_CC_ATOMIC_LOCK_REG_ID_LEN = 4 ;
+static const uint8_t P9N2_PERV_1_CC_ATOMIC_LOCK_REG_ACTIVITY = 8 ;
+static const uint8_t P9N2_PERV_1_CC_ATOMIC_LOCK_REG_ACTIVITY_LEN = 8 ;
+
+static const uint8_t P9N2_PERV_1_CC_PROTECT_MODE_REG_READ_ENABLE = 0 ;
+static const uint8_t P9N2_PERV_1_CC_PROTECT_MODE_REG_WRITE_ENABLE = 1 ;
+
+static const uint8_t P9N2_PERV_1_CLK_REGION_CLOCK_CMD = 0 ;
+static const uint8_t P9N2_PERV_1_CLK_REGION_CLOCK_CMD_LEN = 2 ;
+static const uint8_t P9N2_PERV_1_CLK_REGION_SLAVE_MODE = 2 ;
+static const uint8_t P9N2_PERV_1_CLK_REGION_MASTER_MODE = 3 ;
+static const uint8_t P9N2_PERV_1_CLK_REGION_CLOCK_PERV = 4 ;
+static const uint8_t P9N2_PERV_1_CLK_REGION_CLOCK_UNIT1 = 5 ;
+static const uint8_t P9N2_PERV_1_CLK_REGION_CLOCK_UNIT2 = 6 ;
+static const uint8_t P9N2_PERV_1_CLK_REGION_CLOCK_UNIT3 = 7 ;
+static const uint8_t P9N2_PERV_1_CLK_REGION_CLOCK_UNIT4 = 8 ;
+static const uint8_t P9N2_PERV_1_CLK_REGION_CLOCK_UNIT5 = 9 ;
+static const uint8_t P9N2_PERV_1_CLK_REGION_CLOCK_UNIT6 = 10 ;
+static const uint8_t P9N2_PERV_1_CLK_REGION_CLOCK_UNIT7 = 11 ;
+static const uint8_t P9N2_PERV_1_CLK_REGION_CLOCK_UNIT8 = 12 ;
+static const uint8_t P9N2_PERV_1_CLK_REGION_CLOCK_UNIT9 = 13 ;
+static const uint8_t P9N2_PERV_1_CLK_REGION_CLOCK_UNIT10 = 14 ;
+static const uint8_t P9N2_PERV_1_CLK_REGION_SEL_THOLD_SL = 48 ;
+static const uint8_t P9N2_PERV_1_CLK_REGION_SEL_THOLD_NSL = 49 ;
+static const uint8_t P9N2_PERV_1_CLK_REGION_SEL_THOLD_ARY = 50 ;
+static const uint8_t P9N2_PERV_1_CLK_REGION_CLOCK_PULSE_USE_EVEN = 52 ;
+
+static const uint8_t P9N2_PERV_1_CLOCK_STAT_ARY_STATUS_PERV = 4 ;
+static const uint8_t P9N2_PERV_1_CLOCK_STAT_ARY_STATUS_UNIT1 = 5 ;
+static const uint8_t P9N2_PERV_1_CLOCK_STAT_ARY_STATUS_UNIT2 = 6 ;
+static const uint8_t P9N2_PERV_1_CLOCK_STAT_ARY_STATUS_UNIT3 = 7 ;
+static const uint8_t P9N2_PERV_1_CLOCK_STAT_ARY_STATUS_UNIT4 = 8 ;
+static const uint8_t P9N2_PERV_1_CLOCK_STAT_ARY_STATUS_UNIT5 = 9 ;
+static const uint8_t P9N2_PERV_1_CLOCK_STAT_ARY_STATUS_UNIT6 = 10 ;
+static const uint8_t P9N2_PERV_1_CLOCK_STAT_ARY_STATUS_UNIT7 = 11 ;
+static const uint8_t P9N2_PERV_1_CLOCK_STAT_ARY_STATUS_UNIT8 = 12 ;
+static const uint8_t P9N2_PERV_1_CLOCK_STAT_ARY_STATUS_UNIT9 = 13 ;
+static const uint8_t P9N2_PERV_1_CLOCK_STAT_ARY_STATUS_UNIT10 = 14 ;
+
+static const uint8_t P9N2_PERV_1_CLOCK_STAT_NSL_STATUS_PERV = 4 ;
+static const uint8_t P9N2_PERV_1_CLOCK_STAT_NSL_STATUS_UNIT1 = 5 ;
+static const uint8_t P9N2_PERV_1_CLOCK_STAT_NSL_STATUS_UNIT2 = 6 ;
+static const uint8_t P9N2_PERV_1_CLOCK_STAT_NSL_STATUS_UNIT3 = 7 ;
+static const uint8_t P9N2_PERV_1_CLOCK_STAT_NSL_STATUS_UNIT4 = 8 ;
+static const uint8_t P9N2_PERV_1_CLOCK_STAT_NSL_STATUS_UNIT5 = 9 ;
+static const uint8_t P9N2_PERV_1_CLOCK_STAT_NSL_STATUS_UNIT6 = 10 ;
+static const uint8_t P9N2_PERV_1_CLOCK_STAT_NSL_STATUS_UNIT7 = 11 ;
+static const uint8_t P9N2_PERV_1_CLOCK_STAT_NSL_STATUS_UNIT8 = 12 ;
+static const uint8_t P9N2_PERV_1_CLOCK_STAT_NSL_STATUS_UNIT9 = 13 ;
+static const uint8_t P9N2_PERV_1_CLOCK_STAT_NSL_STATUS_UNIT10 = 14 ;
+
+static const uint8_t P9N2_PERV_1_CLOCK_STAT_SL_STATUS_PERV = 4 ;
+static const uint8_t P9N2_PERV_1_CLOCK_STAT_SL_STATUS_UNIT1 = 5 ;
+static const uint8_t P9N2_PERV_1_CLOCK_STAT_SL_STATUS_UNIT2 = 6 ;
+static const uint8_t P9N2_PERV_1_CLOCK_STAT_SL_STATUS_UNIT3 = 7 ;
+static const uint8_t P9N2_PERV_1_CLOCK_STAT_SL_STATUS_UNIT4 = 8 ;
+static const uint8_t P9N2_PERV_1_CLOCK_STAT_SL_STATUS_UNIT5 = 9 ;
+static const uint8_t P9N2_PERV_1_CLOCK_STAT_SL_STATUS_UNIT6 = 10 ;
+static const uint8_t P9N2_PERV_1_CLOCK_STAT_SL_STATUS_UNIT7 = 11 ;
+static const uint8_t P9N2_PERV_1_CLOCK_STAT_SL_STATUS_UNIT8 = 12 ;
+static const uint8_t P9N2_PERV_1_CLOCK_STAT_SL_STATUS_UNIT9 = 13 ;
+static const uint8_t P9N2_PERV_1_CLOCK_STAT_SL_STATUS_UNIT10 = 14 ;
+
+static const uint8_t P9N2_PERV_PIB2OPB1_CMD_WRDAT_WRITE_NOT_READ = 0 ;
+static const uint8_t P9N2_PERV_PIB2OPB1_CMD_WRDAT_CMD = 1 ;
+static const uint8_t P9N2_PERV_PIB2OPB1_CMD_WRDAT_CMD_LEN = 31 ;
+static const uint8_t P9N2_PERV_PIB2OPB1_CMD_WRDAT_WDATA = 32 ;
+static const uint8_t P9N2_PERV_PIB2OPB1_CMD_WRDAT_WDATA_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_CMD_WRDAT_WRITE_NOT_READ = 0 ;
+static const uint8_t P9N2_PERV_CMD_WRDAT_CMD = 1 ;
+static const uint8_t P9N2_PERV_CMD_WRDAT_CMD_LEN = 31 ;
+static const uint8_t P9N2_PERV_CMD_WRDAT_WDATA = 32 ;
+static const uint8_t P9N2_PERV_CMD_WRDAT_WDATA_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_PIB2OPB0_CMD_WRDAT_WRITE_NOT_READ = 0 ;
+static const uint8_t P9N2_PERV_PIB2OPB0_CMD_WRDAT_CMD = 1 ;
+static const uint8_t P9N2_PERV_PIB2OPB0_CMD_WRDAT_CMD_LEN = 31 ;
+static const uint8_t P9N2_PERV_PIB2OPB0_CMD_WRDAT_WDATA = 32 ;
+static const uint8_t P9N2_PERV_PIB2OPB0_CMD_WRDAT_WDATA_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_FSI2PIB_COMMAND_REGISTER_CMD_REG = 0 ;
+static const uint8_t P9N2_PERV_FSI2PIB_COMMAND_REGISTER_CMD_REG_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_FSISHIFT_COMMAND_REGISTER_CMDREG_WRITE_FLAG = 0 ;
+static const uint8_t P9N2_PERV_FSISHIFT_COMMAND_REGISTER_CMDREG_BROADCAST_FLAG = 1 ;
+static const uint8_t P9N2_PERV_FSISHIFT_COMMAND_REGISTER_CMDREG_SCAN_ADDRESS = 2 ;
+static const uint8_t P9N2_PERV_FSISHIFT_COMMAND_REGISTER_CMDREG_SCAN_ADDRESS_LEN = 14 ;
+static const uint8_t P9N2_PERV_FSISHIFT_COMMAND_REGISTER_CMDREG_SCAN_REGION = 16 ;
+static const uint8_t P9N2_PERV_FSISHIFT_COMMAND_REGISTER_CMDREG_SCAN_REGION_LEN = 12 ;
+static const uint8_t P9N2_PERV_FSISHIFT_COMMAND_REGISTER_CMDREG_SCAN_TYPE = 28 ;
+static const uint8_t P9N2_PERV_FSISHIFT_COMMAND_REGISTER_CMDREG_SCAN_TYPE_LEN = 4 ;
+
+static const uint8_t P9N2_PERV_FSII2C_COMMAND_REGISTER_A_WITH_START_0 = 0 ;
+static const uint8_t P9N2_PERV_FSII2C_COMMAND_REGISTER_A_WITH_ADDRESS_0 = 1 ;
+static const uint8_t P9N2_PERV_FSII2C_COMMAND_REGISTER_A_READ_CONTINUE_0 = 2 ;
+static const uint8_t P9N2_PERV_FSII2C_COMMAND_REGISTER_A_WITH_STOP_0 = 3 ;
+static const uint8_t P9N2_PERV_FSII2C_COMMAND_REGISTER_A_NOT_USED_0 = 4 ;
+static const uint8_t P9N2_PERV_FSII2C_COMMAND_REGISTER_A_NOT_USED_0_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSII2C_COMMAND_REGISTER_A_DEVICE_ADDRESS_0 = 8 ;
+static const uint8_t P9N2_PERV_FSII2C_COMMAND_REGISTER_A_DEVICE_ADDRESS_0_LEN = 7 ;
+static const uint8_t P9N2_PERV_FSII2C_COMMAND_REGISTER_A_READ_NOT_WRITE_0 = 15 ;
+static const uint8_t P9N2_PERV_FSII2C_COMMAND_REGISTER_A_LENGTH_IN_BYTES_0 = 16 ;
+static const uint8_t P9N2_PERV_FSII2C_COMMAND_REGISTER_A_LENGTH_IN_BYTES_0_LEN = 16 ;
+
+static const uint8_t P9N2_PERV_FSI2PIB_COMPLEMENT_MASK_REG = 0 ;
+static const uint8_t P9N2_PERV_FSI2PIB_COMPLEMENT_MASK_REG_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_FSISHIFT_COMPLEMENT_MASK_REG = 0 ;
+static const uint8_t P9N2_PERV_FSISHIFT_COMPLEMENT_MASK_REG_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_1_CONTROL_REG_RESET_TRIP_HISTORY = 0 ;
+static const uint8_t P9N2_PERV_1_CONTROL_REG_RESET_SAMPLE_PULSE_CNT = 1 ;
+static const uint8_t P9N2_PERV_1_CONTROL_REG_F_RESET_CPM_RD = 2 ;
+static const uint8_t P9N2_PERV_1_CONTROL_REG_F_RESET_CPM_WR = 3 ;
+static const uint8_t P9N2_PERV_1_CONTROL_REG_RESET_SAMPLE_DTS = 4 ;
+static const uint8_t P9N2_PERV_1_CONTROL_REG_FORCE_SAMPLE_DTS = 5 ;
+static const uint8_t P9N2_PERV_1_CONTROL_REG_FORCE_SAMPLE_DTS_INTERRUPTIBLE = 6 ;
+static const uint8_t P9N2_PERV_1_CONTROL_REG_FORCE_RESET_THRES_L1RESULTS = 7 ;
+static const uint8_t P9N2_PERV_1_CONTROL_REG_FORCE_RESET_THRES_L2RESULTS = 8 ;
+static const uint8_t P9N2_PERV_1_CONTROL_REG_FORCE_RESET_THRES_L3RESULTS = 9 ;
+static const uint8_t P9N2_PERV_1_CONTROL_REG_FORCE_MEASURE_VOLT_INTERRUPTIBLE = 10 ;
+static const uint8_t P9N2_PERV_1_CONTROL_REG_FORCE_RESET_MEASURE_VOLT = 11 ;
+static const uint8_t P9N2_PERV_1_CONTROL_REG_FORCE_SHIFT_SENSOR = 12 ;
+
+static const uint8_t P9N2_PERV_1_CPLT_CONF0_CTRL_MISC_PROBE0_SEL_DC = 0 ;
+static const uint8_t P9N2_PERV_1_CPLT_CONF0_CTRL_MISC_PROBE0_SEL_DC_LEN = 6 ;
+static const uint8_t P9N2_PERV_1_CPLT_CONF0_RESERVED_6C = 6 ;
+static const uint8_t P9N2_PERV_1_CPLT_CONF0_RESERVED_7C = 7 ;
+static const uint8_t P9N2_PERV_1_CPLT_CONF0_CTRL_MISC_PROBE1_SEL_DC = 8 ;
+static const uint8_t P9N2_PERV_1_CPLT_CONF0_CTRL_MISC_PROBE1_SEL_DC_LEN = 6 ;
+static const uint8_t P9N2_PERV_1_CPLT_CONF0_RESERVED_14C = 14 ;
+static const uint8_t P9N2_PERV_1_CPLT_CONF0_RESERVED_15C = 15 ;
+static const uint8_t P9N2_PERV_1_CPLT_CONF0_CTRL_MISC_PROBE2_SEL_DC = 16 ;
+static const uint8_t P9N2_PERV_1_CPLT_CONF0_CTRL_MISC_PROBE2_SEL_DC_LEN = 6 ;
+static const uint8_t P9N2_PERV_1_CPLT_CONF0_RESERVED_22C = 22 ;
+static const uint8_t P9N2_PERV_1_CPLT_CONF0_RESERVED_23C = 23 ;
+static const uint8_t P9N2_PERV_1_CPLT_CONF0_CTRL_MISC_PROBE3_SEL_DC = 24 ;
+static const uint8_t P9N2_PERV_1_CPLT_CONF0_CTRL_MISC_PROBE3_SEL_DC_LEN = 6 ;
+static const uint8_t P9N2_PERV_1_CPLT_CONF0_RESERVED_30C = 30 ;
+static const uint8_t P9N2_PERV_1_CPLT_CONF0_RESERVED_31C = 31 ;
+static const uint8_t P9N2_PERV_1_CPLT_CONF0_CTRL_CC_OFLOW_FEH_SEL_DC = 32 ;
+static const uint8_t P9N2_PERV_1_CPLT_CONF0_CTRL_CC_SCAN_PROTECT_DC = 33 ;
+static const uint8_t P9N2_PERV_1_CPLT_CONF0_CTRL_CC_SDIS_DC_N = 34 ;
+static const uint8_t P9N2_PERV_1_CPLT_CONF0_CTRL_CC_SCAN_DIAG = 35 ;
+static const uint8_t P9N2_PERV_1_CPLT_CONF0_RESERVED_TEST_CONTROL_36C = 36 ;
+static const uint8_t P9N2_PERV_1_CPLT_CONF0_RESERVED_TEST_CONTROL_37C = 37 ;
+static const uint8_t P9N2_PERV_1_CPLT_CONF0_RESERVED_TEST_CONTROL_38C = 38 ;
+static const uint8_t P9N2_PERV_1_CPLT_CONF0_RESERVED_TEST_CONTROL_39C = 39 ;
+static const uint8_t P9N2_PERV_1_CPLT_CONF0_CTRL_EPS_MASK_VITL_PCB_ERR_DC = 40 ;
+static const uint8_t P9N2_PERV_1_CPLT_CONF0_CTRL_CC_MASK_VITL_SCAN_OPCG_ERR_DC = 41 ;
+static const uint8_t P9N2_PERV_1_CPLT_CONF0_RESERVED_42C = 42 ;
+static const uint8_t P9N2_PERV_1_CPLT_CONF0_RESERVED_43C = 43 ;
+static const uint8_t P9N2_PERV_1_CPLT_CONF0_TC_PCB_DBG_GLB_BRCST_EN = 44 ;
+static const uint8_t P9N2_PERV_1_CPLT_CONF0_FREE_USAGE_45C = 45 ;
+static const uint8_t P9N2_PERV_1_CPLT_CONF0_FREE_USAGE_46C = 46 ;
+static const uint8_t P9N2_PERV_1_CPLT_CONF0_FREE_USAGE_47C = 47 ;
+static const uint8_t P9N2_PERV_1_CPLT_CONF0_UNUSED_48C = 48 ;
+static const uint8_t P9N2_PERV_1_CPLT_CONF0_UNUSED_49C = 49 ;
+static const uint8_t P9N2_PERV_1_CPLT_CONF0_UNUSED_50C = 50 ;
+static const uint8_t P9N2_PERV_1_CPLT_CONF0_UNUSED_51C = 51 ;
+static const uint8_t P9N2_PERV_1_CPLT_CONF0_TC_UNIT_CHIP_ID_DC = 52 ;
+static const uint8_t P9N2_PERV_1_CPLT_CONF0_TC_UNIT_CHIP_ID_DC_LEN = 3 ;
+static const uint8_t P9N2_PERV_1_CPLT_CONF0_RESERVED_ID_55C = 55 ;
+static const uint8_t P9N2_PERV_1_CPLT_CONF0_UNUSED_56C = 56 ;
+static const uint8_t P9N2_PERV_1_CPLT_CONF0_UNUSED_57C = 57 ;
+static const uint8_t P9N2_PERV_1_CPLT_CONF0_UNUSED_58C = 58 ;
+static const uint8_t P9N2_PERV_1_CPLT_CONF0_UNUSED_59C = 59 ;
+static const uint8_t P9N2_PERV_1_CPLT_CONF0_UNUSED_60C = 60 ;
+static const uint8_t P9N2_PERV_1_CPLT_CONF0_RESERVED_ID_61C = 61 ;
+static const uint8_t P9N2_PERV_1_CPLT_CONF0_RESERVED_ID_62C = 62 ;
+static const uint8_t P9N2_PERV_1_CPLT_CONF0_RESERVED_ID_63C = 63 ;
+
+static const uint8_t P9N2_PERV_1_CPLT_CONF1_TCPERV_AMUX_VSELECT_CHIP = 0 ;
+static const uint8_t P9N2_PERV_1_CPLT_CONF1_TCPERV_AMUX_VSELECT_CHIP_LEN = 3 ;
+static const uint8_t P9N2_PERV_1_CPLT_CONF1_UNUSED_3D = 3 ;
+static const uint8_t P9N2_PERV_1_CPLT_CONF1_UNUSED_4D = 4 ;
+static const uint8_t P9N2_PERV_1_CPLT_CONF1_UNUSED_5D = 5 ;
+static const uint8_t P9N2_PERV_1_CPLT_CONF1_UNUSED_6D = 6 ;
+static const uint8_t P9N2_PERV_1_CPLT_CONF1_UNUSED_7D = 7 ;
+static const uint8_t P9N2_PERV_1_CPLT_CONF1_UNUSED_8D = 8 ;
+static const uint8_t P9N2_PERV_1_CPLT_CONF1_UNUSED_9D = 9 ;
+static const uint8_t P9N2_PERV_1_CPLT_CONF1_UNUSED_10D = 10 ;
+static const uint8_t P9N2_PERV_1_CPLT_CONF1_UNUSED_11D = 11 ;
+static const uint8_t P9N2_PERV_1_CPLT_CONF1_TP_IO_SPI_APSS_MCPRECOMP = 12 ;
+static const uint8_t P9N2_PERV_1_CPLT_CONF1_TP_IO_SPI_APSS_MCPRECOMP_LEN = 2 ;
+static const uint8_t P9N2_PERV_1_CPLT_CONF1_TP_IO_SPARE2_MCPRECOMP = 14 ;
+static const uint8_t P9N2_PERV_1_CPLT_CONF1_TP_IO_SPARE2_MCPRECOMP_LEN = 2 ;
+static const uint8_t P9N2_PERV_1_CPLT_CONF1_TP_IO_SPARE3_MCPRECOMP = 16 ;
+static const uint8_t P9N2_PERV_1_CPLT_CONF1_TP_IO_SPARE3_MCPRECOMP_LEN = 2 ;
+static const uint8_t P9N2_PERV_1_CPLT_CONF1_UNUSED_18D = 18 ;
+static const uint8_t P9N2_PERV_1_CPLT_CONF1_UNUSED_19D = 19 ;
+static const uint8_t P9N2_PERV_1_CPLT_CONF1_UNUSED_20D = 20 ;
+static const uint8_t P9N2_PERV_1_CPLT_CONF1_UNUSED_21D = 21 ;
+static const uint8_t P9N2_PERV_1_CPLT_CONF1_UNUSED_22D = 22 ;
+static const uint8_t P9N2_PERV_1_CPLT_CONF1_UNUSED_23D = 23 ;
+static const uint8_t P9N2_PERV_1_CPLT_CONF1_UNUSED_24D = 24 ;
+static const uint8_t P9N2_PERV_1_CPLT_CONF1_UNUSED_25D = 25 ;
+static const uint8_t P9N2_PERV_1_CPLT_CONF1_UNUSED_26D = 26 ;
+static const uint8_t P9N2_PERV_1_CPLT_CONF1_UNUSED_27D = 27 ;
+static const uint8_t P9N2_PERV_1_CPLT_CONF1_UNUSED_28D = 28 ;
+static const uint8_t P9N2_PERV_1_CPLT_CONF1_UNUSED_29D = 29 ;
+static const uint8_t P9N2_PERV_1_CPLT_CONF1_UNUSED_30D = 30 ;
+static const uint8_t P9N2_PERV_1_CPLT_CONF1_UNUSED_31D = 31 ;
+
+static const uint8_t P9N2_PERV_1_CPLT_CTRL0_CTRL_CC_ABSTCLK_MUXSEL_DC = 0 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL0_TC_UNIT_SYNCCLK_MUXSEL_DC = 1 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL0_CTRL_CC_FLUSHMODE_INH_DC = 2 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL0_CTRL_CC_FORCE_ALIGN_DC = 3 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL0_TC_UNIT_ARY_WRT_THRU_DC = 4 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL0_UNUSED_5A = 5 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL0_UNUSED_6A = 6 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL0_UNUSED_7A = 7 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL0_CTRL_CC_ABIST_RECOV_DISABLE_DC = 8 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL0_UNUSED_9A = 9 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL0_UNUSED_10A = 10 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL0_RESERVED_11A = 11 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL0_UNUSED_12A = 12 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL0_TC_UNIT_DETERMINISTIC_TEST_ENABLE_DC = 13 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL0_TC_UNIT_CONSTRAIN_SAFESCAN_DC = 14 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL0_TC_UNIT_RRFA_TEST_ENABLE_DC = 15 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL0_UNUSED_16A = 16 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL0_UNUSED_17A = 17 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL0_RESERVED_18A = 18 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL0_RESERVED_19A = 19 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL0_UNUSED_20A = 20 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL0_UNUSED_21A = 21 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL0_UNUSED_22A = 22 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL0_UNUSED_23A = 23 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL0_UNUSED_24A = 24 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL0_UNUSED_25A = 25 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL0_UNUSED_26A = 26 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL0_UNUSED_27A = 27 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL0_UNUSED_28A = 28 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL0_UNUSED_29A = 29 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL0_UNUSED_30A = 30 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL0_UNUSED_31A = 31 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL0_UNUSED_32A = 32 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL0_RESERVED_33A = 33 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL0_RESERVED_34A = 34 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL0_RESERVED_35A = 35 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL0_UNUSED_36A = 36 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL0_UNUSED_37A = 37 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL0_RESERVED_38A = 38 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL0_RESERVED_39A = 39 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL0_CTRL_MISC_CLKDIV_SEL_DC = 40 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL0_CTRL_MISC_CLKDIV_SEL_DC_LEN = 2 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL0_RESERVED_42A = 42 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL0_RESERVED_43A = 43 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL0_UNUSED_44A = 44 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL0_CTRL_CC_OTP_PRGMODE_DC = 45 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL0_CTRL_CC_SSS_CALIBRATE_DC = 46 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL0_CTRL_CC_PIN_LBIST_DC = 47 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL0_FREE_USAGE_48A = 48 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL0_FREE_USAGE_49A = 49 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL0_FREE_USAGE_50A = 50 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL0_FREE_USAGE_51A = 51 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL0_FREE_USAGE_52A = 52 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL0_FREE_USAGE_53A = 53 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL0_FREE_USAGE_54A = 54 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL0_FREE_USAGE_55A = 55 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL0_FREE_USAGE_56A = 56 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL0_FREE_USAGE_57A = 57 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL0_FREE_USAGE_58A = 58 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL0_FREE_USAGE_59A = 59 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL0_FREE_USAGE_60A = 60 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL0_FREE_USAGE_61A = 61 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL0_FREE_USAGE_62A = 62 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL0_FREE_USAGE_63A = 63 ;
+
+static const uint8_t P9N2_PERV_1_CPLT_CTRL1_UNUSED_0B = 0 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL1_UNUSED_1B = 1 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL1_UNUSED_2B = 2 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL1_TC_VITL_REGION_FENCE = 3 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL1_TC_PERV_REGION_FENCE = 4 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL1_TC_REGION1_FENCE = 5 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL1_TC_REGION2_FENCE = 6 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL1_TC_REGION3_FENCE = 7 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL1_UNUSED_8B = 8 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL1_UNUSED_9B = 9 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL1_UNUSED_10B = 10 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL1_UNUSED_11B = 11 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL1_UNUSED_12B = 12 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL1_UNUSED_13B = 13 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL1_UNUSED_14B = 14 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL1_RESERVED = 15 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL1_TC_UNIT_MULTICYCLE_TEST_FENCE = 16 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL1_UNUSED_17B = 17 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL1_UNUSED_18B = 18 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL1_UNUSED_19B = 19 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL1_TC_PERV_EXPORT_FREEZE = 20 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL1_UNUSED_21B = 21 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL1_UNUSED_22B = 22 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL1_UNUSED_23B = 23 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL1_UNUSED_24B = 24 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL1_UNUSED_25B = 25 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL1_UNUSED_26B = 26 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL1_UNUSED_27B = 27 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL1_UNUSED_28B = 28 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL1_UNUSED_29B = 29 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL1_UNUSED_30B = 30 ;
+static const uint8_t P9N2_PERV_1_CPLT_CTRL1_UNUSED_31B = 31 ;
+
+static const uint8_t P9N2_PERV_1_CPLT_MASK0_CPLTMASK0 = 0 ;
+static const uint8_t P9N2_PERV_1_CPLT_MASK0_CPLTMASK0_LEN = 24 ;
+
+static const uint8_t P9N2_PERV_1_CPLT_STAT0_ABIST_DONE_DC = 0 ;
+static const uint8_t P9N2_PERV_1_CPLT_STAT0_EBIST_DONE_DC = 1 ;
+static const uint8_t P9N2_PERV_1_CPLT_STAT0_RESERVED_2E = 2 ;
+static const uint8_t P9N2_PERV_1_CPLT_STAT0_RESERVED_3E = 3 ;
+static const uint8_t P9N2_PERV_1_CPLT_STAT0_TC_DIAG_PORT0_OUT = 4 ;
+static const uint8_t P9N2_PERV_1_CPLT_STAT0_TC_DIAG_PORT1_OUT = 5 ;
+static const uint8_t P9N2_PERV_1_CPLT_STAT0_RESERVED_6E = 6 ;
+static const uint8_t P9N2_PERV_1_CPLT_STAT0_PLL_DESTOUT = 7 ;
+static const uint8_t P9N2_PERV_1_CPLT_STAT0_CC_CTRL_OPCG_DONE_DC = 8 ;
+static const uint8_t P9N2_PERV_1_CPLT_STAT0_CC_CTRL_CHIPLET_IS_ALIGNED_DC = 9 ;
+static const uint8_t P9N2_PERV_1_CPLT_STAT0_FREE_USAGE_10E = 10 ;
+static const uint8_t P9N2_PERV_1_CPLT_STAT0_FREE_USAGE_11E = 11 ;
+static const uint8_t P9N2_PERV_1_CPLT_STAT0_FREE_USAGE_12E = 12 ;
+static const uint8_t P9N2_PERV_1_CPLT_STAT0_FREE_USAGE_13E = 13 ;
+static const uint8_t P9N2_PERV_1_CPLT_STAT0_FREE_USAGE_14E = 14 ;
+static const uint8_t P9N2_PERV_1_CPLT_STAT0_FREE_USAGE_15E = 15 ;
+static const uint8_t P9N2_PERV_1_CPLT_STAT0_FREE_USAGE_16E = 16 ;
+static const uint8_t P9N2_PERV_1_CPLT_STAT0_FREE_USAGE_17E = 17 ;
+static const uint8_t P9N2_PERV_1_CPLT_STAT0_FREE_USAGE_18E = 18 ;
+static const uint8_t P9N2_PERV_1_CPLT_STAT0_FREE_USAGE_19E = 19 ;
+static const uint8_t P9N2_PERV_1_CPLT_STAT0_FREE_USAGE_20E = 20 ;
+static const uint8_t P9N2_PERV_1_CPLT_STAT0_FREE_USAGE_21E = 21 ;
+static const uint8_t P9N2_PERV_1_CPLT_STAT0_FREE_USAGE_22E = 22 ;
+static const uint8_t P9N2_PERV_1_CPLT_STAT0_FREE_USAGE_23E = 23 ;
+
+static const uint8_t P9N2_PERV_1_CTRL_ATOMIC_LOCK_REG_ENABLE = 0 ;
+static const uint8_t P9N2_PERV_1_CTRL_ATOMIC_LOCK_REG_ID = 1 ;
+static const uint8_t P9N2_PERV_1_CTRL_ATOMIC_LOCK_REG_ID_LEN = 4 ;
+static const uint8_t P9N2_PERV_1_CTRL_ATOMIC_LOCK_REG_ACTIVITY = 8 ;
+static const uint8_t P9N2_PERV_1_CTRL_ATOMIC_LOCK_REG_ACTIVITY_LEN = 8 ;
+
+static const uint8_t P9N2_PERV_1_CTRL_PROTECT_MODE_REG_READ_ENABLE = 0 ;
+static const uint8_t P9N2_PERV_1_CTRL_PROTECT_MODE_REG_WRITE_ENABLE = 1 ;
+
+static const uint8_t P9N2_PERV_FSI2PIB_DATA_REGISTER_0_REG = 0 ;
+static const uint8_t P9N2_PERV_FSI2PIB_DATA_REGISTER_0_REG_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_FSI2PIB_DATA_REGISTER_1_REG = 0 ;
+static const uint8_t P9N2_PERV_FSI2PIB_DATA_REGISTER_1_REG_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_1_DBG_CBS_CC_RESET_EP = 0 ;
+static const uint8_t P9N2_PERV_1_DBG_CBS_CC_OPCG_IP = 1 ;
+static const uint8_t P9N2_PERV_1_DBG_CBS_CC_VITL_CLKOFF = 2 ;
+static const uint8_t P9N2_PERV_1_DBG_CBS_CC_TEST_ENABLE = 3 ;
+static const uint8_t P9N2_PERV_1_DBG_CBS_CC_REQ = 4 ;
+static const uint8_t P9N2_PERV_1_DBG_CBS_CC_CMD = 5 ;
+static const uint8_t P9N2_PERV_1_DBG_CBS_CC_CMD_LEN = 3 ;
+static const uint8_t P9N2_PERV_1_DBG_CBS_CC_STATE = 8 ;
+static const uint8_t P9N2_PERV_1_DBG_CBS_CC_STATE_LEN = 5 ;
+static const uint8_t P9N2_PERV_1_DBG_CBS_CC_SECURITY_DEBUG_MODE = 13 ;
+static const uint8_t P9N2_PERV_1_DBG_CBS_CC_PROTOCOL_ERROR = 14 ;
+static const uint8_t P9N2_PERV_1_DBG_CBS_CC_PCB_IDLE = 15 ;
+static const uint8_t P9N2_PERV_1_DBG_CBS_CC_CURRENT_OPCG_MODE = 16 ;
+static const uint8_t P9N2_PERV_1_DBG_CBS_CC_CURRENT_OPCG_MODE_LEN = 4 ;
+static const uint8_t P9N2_PERV_1_DBG_CBS_CC_LAST_OPCG_MODE = 20 ;
+static const uint8_t P9N2_PERV_1_DBG_CBS_CC_LAST_OPCG_MODE_LEN = 4 ;
+static const uint8_t P9N2_PERV_1_DBG_CBS_CC_PCB_ERROR = 24 ;
+static const uint8_t P9N2_PERV_1_DBG_CBS_CC_PARITY_ERROR = 25 ;
+static const uint8_t P9N2_PERV_1_DBG_CBS_CC_ERROR = 26 ;
+static const uint8_t P9N2_PERV_1_DBG_CBS_CC_CHIPLET_IS_ALIGNED = 27 ;
+static const uint8_t P9N2_PERV_1_DBG_CBS_CC_PCB_REQUEST_SINCE_RESET = 28 ;
+static const uint8_t P9N2_PERV_1_DBG_CBS_CC_PARANOIA_TEST_ENABLE_CHANGE = 29 ;
+static const uint8_t P9N2_PERV_1_DBG_CBS_CC_PARANOIA_VITL_CLKOFF_CHANGE = 30 ;
+static const uint8_t P9N2_PERV_1_DBG_CBS_CC_TP_TPFSI_ACK = 31 ;
+
+static const uint8_t P9N2_PERV_1_DBG_INST1_COND_REG_1_COND1_SEL_A = 0 ;
+static const uint8_t P9N2_PERV_1_DBG_INST1_COND_REG_1_COND1_SEL_A_LEN = 8 ;
+static const uint8_t P9N2_PERV_1_DBG_INST1_COND_REG_1_COND1_SEL_B = 8 ;
+static const uint8_t P9N2_PERV_1_DBG_INST1_COND_REG_1_COND1_SEL_B_LEN = 8 ;
+static const uint8_t P9N2_PERV_1_DBG_INST1_COND_REG_1_COND2_SEL_A = 16 ;
+static const uint8_t P9N2_PERV_1_DBG_INST1_COND_REG_1_COND2_SEL_A_LEN = 8 ;
+static const uint8_t P9N2_PERV_1_DBG_INST1_COND_REG_1_COND2_SEL_B = 24 ;
+static const uint8_t P9N2_PERV_1_DBG_INST1_COND_REG_1_COND2_SEL_B_LEN = 8 ;
+static const uint8_t P9N2_PERV_1_DBG_INST1_COND_REG_1_C1_INAROW_MODE = 32 ;
+static const uint8_t P9N2_PERV_1_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE1 = 33 ;
+static const uint8_t P9N2_PERV_1_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE1 = 34 ;
+static const uint8_t P9N2_PERV_1_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE1 = 35 ;
+static const uint8_t P9N2_PERV_1_DBG_INST1_COND_REG_1_UNUSED = 36 ;
+static const uint8_t P9N2_PERV_1_DBG_INST1_COND_REG_1_UNUSED_LEN = 3 ;
+static const uint8_t P9N2_PERV_1_DBG_INST1_COND_REG_1_C2_INAROW_MODE = 39 ;
+static const uint8_t P9N2_PERV_1_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE2 = 40 ;
+static const uint8_t P9N2_PERV_1_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE2 = 41 ;
+static const uint8_t P9N2_PERV_1_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE2 = 42 ;
+static const uint8_t P9N2_PERV_1_DBG_INST1_COND_REG_1_UNUSED_2 = 43 ;
+static const uint8_t P9N2_PERV_1_DBG_INST1_COND_REG_1_UNUSED_2_LEN = 3 ;
+static const uint8_t P9N2_PERV_1_DBG_INST1_COND_REG_1_COND3_ENABLE_RESET = 46 ;
+static const uint8_t P9N2_PERV_1_DBG_INST1_COND_REG_1_EXACT_TO_MODE = 47 ;
+static const uint8_t P9N2_PERV_1_DBG_INST1_COND_REG_1_RESET_C2TIMER_ON_C1 = 48 ;
+static const uint8_t P9N2_PERV_1_DBG_INST1_COND_REG_1_RESET_C3_ON_C0 = 49 ;
+static const uint8_t P9N2_PERV_1_DBG_INST1_COND_REG_1_SLOW_TO_MODE = 50 ;
+static const uint8_t P9N2_PERV_1_DBG_INST1_COND_REG_1_EXACT_RESET_C3_ON_TO = 51 ;
+static const uint8_t P9N2_PERV_1_DBG_INST1_COND_REG_1_C1_COUNT_LT = 52 ;
+static const uint8_t P9N2_PERV_1_DBG_INST1_COND_REG_1_C1_COUNT_LT_LEN = 4 ;
+static const uint8_t P9N2_PERV_1_DBG_INST1_COND_REG_1_C2_COUNT_LT = 56 ;
+static const uint8_t P9N2_PERV_1_DBG_INST1_COND_REG_1_C2_COUNT_LT_LEN = 4 ;
+static const uint8_t P9N2_PERV_1_DBG_INST1_COND_REG_1_RESET_C3_SELECT = 60 ;
+static const uint8_t P9N2_PERV_1_DBG_INST1_COND_REG_1_RESET_C3_SELECT_LEN = 3 ;
+
+static const uint8_t P9N2_PERV_1_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A = 0 ;
+static const uint8_t P9N2_PERV_1_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN = 5 ;
+static const uint8_t P9N2_PERV_1_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B = 5 ;
+static const uint8_t P9N2_PERV_1_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN = 5 ;
+static const uint8_t P9N2_PERV_1_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A = 10 ;
+static const uint8_t P9N2_PERV_1_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN = 5 ;
+static const uint8_t P9N2_PERV_1_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B = 15 ;
+static const uint8_t P9N2_PERV_1_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN = 5 ;
+static const uint8_t P9N2_PERV_1_DBG_INST1_COND_REG_2_TO_CMP_LT = 20 ;
+static const uint8_t P9N2_PERV_1_DBG_INST1_COND_REG_2_TO_CMP_LT_LEN = 24 ;
+
+static const uint8_t P9N2_PERV_1_DBG_INST2_COND_REG_1_COND1_SEL_A = 0 ;
+static const uint8_t P9N2_PERV_1_DBG_INST2_COND_REG_1_COND1_SEL_A_LEN = 8 ;
+static const uint8_t P9N2_PERV_1_DBG_INST2_COND_REG_1_COND1_SEL_B = 8 ;
+static const uint8_t P9N2_PERV_1_DBG_INST2_COND_REG_1_COND1_SEL_B_LEN = 8 ;
+static const uint8_t P9N2_PERV_1_DBG_INST2_COND_REG_1_COND2_SEL_A = 16 ;
+static const uint8_t P9N2_PERV_1_DBG_INST2_COND_REG_1_COND2_SEL_A_LEN = 8 ;
+static const uint8_t P9N2_PERV_1_DBG_INST2_COND_REG_1_COND2_SEL_B = 24 ;
+static const uint8_t P9N2_PERV_1_DBG_INST2_COND_REG_1_COND2_SEL_B_LEN = 8 ;
+static const uint8_t P9N2_PERV_1_DBG_INST2_COND_REG_1_C1_INAROW_MODE = 32 ;
+static const uint8_t P9N2_PERV_1_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE1 = 33 ;
+static const uint8_t P9N2_PERV_1_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE1 = 34 ;
+static const uint8_t P9N2_PERV_1_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE1 = 35 ;
+static const uint8_t P9N2_PERV_1_DBG_INST2_COND_REG_1_UNUSED = 36 ;
+static const uint8_t P9N2_PERV_1_DBG_INST2_COND_REG_1_UNUSED_LEN = 3 ;
+static const uint8_t P9N2_PERV_1_DBG_INST2_COND_REG_1_C2_INAROW_MODE = 39 ;
+static const uint8_t P9N2_PERV_1_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE2 = 40 ;
+static const uint8_t P9N2_PERV_1_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE2 = 41 ;
+static const uint8_t P9N2_PERV_1_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE2 = 42 ;
+static const uint8_t P9N2_PERV_1_DBG_INST2_COND_REG_1_UNUSED_2 = 43 ;
+static const uint8_t P9N2_PERV_1_DBG_INST2_COND_REG_1_UNUSED_2_LEN = 3 ;
+static const uint8_t P9N2_PERV_1_DBG_INST2_COND_REG_1_COND3_ENABLE_RESET = 46 ;
+static const uint8_t P9N2_PERV_1_DBG_INST2_COND_REG_1_EXACT_TO_MODE = 47 ;
+static const uint8_t P9N2_PERV_1_DBG_INST2_COND_REG_1_RESET_C2TIMER_ON_C1 = 48 ;
+static const uint8_t P9N2_PERV_1_DBG_INST2_COND_REG_1_RESET_C3_ON_C0 = 49 ;
+static const uint8_t P9N2_PERV_1_DBG_INST2_COND_REG_1_SLOW_TO_MODE = 50 ;
+static const uint8_t P9N2_PERV_1_DBG_INST2_COND_REG_1_EXACT_RESET_C3_ON_TO = 51 ;
+static const uint8_t P9N2_PERV_1_DBG_INST2_COND_REG_1_C1_COUNT_LT = 52 ;
+static const uint8_t P9N2_PERV_1_DBG_INST2_COND_REG_1_C1_COUNT_LT_LEN = 4 ;
+static const uint8_t P9N2_PERV_1_DBG_INST2_COND_REG_1_C2_COUNT_LT = 56 ;
+static const uint8_t P9N2_PERV_1_DBG_INST2_COND_REG_1_C2_COUNT_LT_LEN = 4 ;
+static const uint8_t P9N2_PERV_1_DBG_INST2_COND_REG_1_RESET_C3_SELECT = 60 ;
+static const uint8_t P9N2_PERV_1_DBG_INST2_COND_REG_1_RESET_C3_SELECT_LEN = 3 ;
+
+static const uint8_t P9N2_PERV_1_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A = 0 ;
+static const uint8_t P9N2_PERV_1_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN = 5 ;
+static const uint8_t P9N2_PERV_1_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B = 5 ;
+static const uint8_t P9N2_PERV_1_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN = 5 ;
+static const uint8_t P9N2_PERV_1_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A = 10 ;
+static const uint8_t P9N2_PERV_1_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN = 5 ;
+static const uint8_t P9N2_PERV_1_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B = 15 ;
+static const uint8_t P9N2_PERV_1_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN = 5 ;
+static const uint8_t P9N2_PERV_1_DBG_INST2_COND_REG_2_TO_CMP_LT = 20 ;
+static const uint8_t P9N2_PERV_1_DBG_INST2_COND_REG_2_TO_CMP_LT_LEN = 24 ;
+
+static const uint8_t P9N2_PERV_1_DBG_MODE_REG_GLB_BRCST = 0 ;
+static const uint8_t P9N2_PERV_1_DBG_MODE_REG_GLB_BRCST_LEN = 3 ;
+static const uint8_t P9N2_PERV_1_DBG_MODE_REG_TRACE_SEL = 3 ;
+static const uint8_t P9N2_PERV_1_DBG_MODE_REG_TRACE_SEL_LEN = 3 ;
+static const uint8_t P9N2_PERV_1_DBG_MODE_REG_TRIG_SEL = 6 ;
+static const uint8_t P9N2_PERV_1_DBG_MODE_REG_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_PERV_1_DBG_MODE_REG_STOP_ON_XSTOP_SELECTION = 8 ;
+static const uint8_t P9N2_PERV_1_DBG_MODE_REG_STOP_ON_RECOV_ERR_SELECTION = 9 ;
+static const uint8_t P9N2_PERV_1_DBG_MODE_REG_STOP_ON_SPATTN_SELECTION = 10 ;
+static const uint8_t P9N2_PERV_1_DBG_MODE_REG_FREEZE_SEL = 11 ;
+static const uint8_t P9N2_PERV_1_DBG_MODE_REG_SYNC_BRCST = 12 ;
+static const uint8_t P9N2_PERV_1_DBG_MODE_REG_SYNC_BRCST_LEN = 2 ;
+
+static const uint8_t P9N2_PERV_1_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE = 0 ;
+static const uint8_t P9N2_PERV_1_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE_LEN = 16 ;
+static const uint8_t P9N2_PERV_1_DBG_TRACE_MODE_REG_2_IMM_FREEZE = 16 ;
+static const uint8_t P9N2_PERV_1_DBG_TRACE_MODE_REG_2_STOP_ON_ERR = 17 ;
+static const uint8_t P9N2_PERV_1_DBG_TRACE_MODE_REG_2_BANK_ON_RUNN_MATCH = 18 ;
+static const uint8_t P9N2_PERV_1_DBG_TRACE_MODE_REG_2_FORCE_TEST = 19 ;
+static const uint8_t P9N2_PERV_1_DBG_TRACE_MODE_REG_2_ACCUM_HIST = 20 ;
+static const uint8_t P9N2_PERV_1_DBG_TRACE_MODE_REG_2_FRZ_COUNT_ON_FRZ = 21 ;
+
+static const uint8_t P9N2_PERV_1_DBG_TRACE_REG_0_INST1_COND3_ENABLE = 0 ;
+static const uint8_t P9N2_PERV_1_DBG_TRACE_REG_0_INST2_COND3_ENABLE = 1 ;
+static const uint8_t P9N2_PERV_1_DBG_TRACE_REG_0_INST3_COND3_ENABLE = 2 ;
+static const uint8_t P9N2_PERV_1_DBG_TRACE_REG_0_INST4_COND3_ENABLE = 3 ;
+static const uint8_t P9N2_PERV_1_DBG_TRACE_REG_0_INST1_SLOW_LFSR_MODE = 4 ;
+static const uint8_t P9N2_PERV_1_DBG_TRACE_REG_0_INST2_SLOW_LFSR_MODE = 5 ;
+static const uint8_t P9N2_PERV_1_DBG_TRACE_REG_0_INST3_SLOW_LFSR_MODE = 6 ;
+static const uint8_t P9N2_PERV_1_DBG_TRACE_REG_0_INST4_SLOW_LFSR_MODE = 7 ;
+static const uint8_t P9N2_PERV_1_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL = 8 ;
+static const uint8_t P9N2_PERV_1_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_PERV_1_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL = 10 ;
+static const uint8_t P9N2_PERV_1_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_PERV_1_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL = 12 ;
+static const uint8_t P9N2_PERV_1_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_PERV_1_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL = 14 ;
+static const uint8_t P9N2_PERV_1_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_PERV_1_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL = 16 ;
+static const uint8_t P9N2_PERV_1_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_PERV_1_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL = 18 ;
+static const uint8_t P9N2_PERV_1_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_PERV_1_DBG_TRACE_REG_0_EXT_TRIG_ON_STOP = 32 ;
+static const uint8_t P9N2_PERV_1_DBG_TRACE_REG_0_EXT_TRIG_ON_FREEZE = 33 ;
+static const uint8_t P9N2_PERV_1_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL = 34 ;
+static const uint8_t P9N2_PERV_1_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL_LEN = 5 ;
+static const uint8_t P9N2_PERV_1_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL = 39 ;
+static const uint8_t P9N2_PERV_1_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL_LEN = 5 ;
+static const uint8_t P9N2_PERV_1_DBG_TRACE_REG_0_PC_TP_TRIG_SEL = 44 ;
+static const uint8_t P9N2_PERV_1_DBG_TRACE_REG_0_PC_TP_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_PERV_1_DBG_TRACE_REG_0_ARM_SEL = 46 ;
+static const uint8_t P9N2_PERV_1_DBG_TRACE_REG_0_ARM_SEL_LEN = 4 ;
+static const uint8_t P9N2_PERV_1_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL = 50 ;
+static const uint8_t P9N2_PERV_1_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL_LEN = 4 ;
+static const uint8_t P9N2_PERV_1_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL = 54 ;
+static const uint8_t P9N2_PERV_1_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL_LEN = 4 ;
+
+static const uint8_t P9N2_PERV_1_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO = 0 ;
+static const uint8_t P9N2_PERV_1_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO_LEN = 2 ;
+static const uint8_t P9N2_PERV_1_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO = 2 ;
+static const uint8_t P9N2_PERV_1_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO_LEN = 2 ;
+static const uint8_t P9N2_PERV_1_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO = 4 ;
+static const uint8_t P9N2_PERV_1_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO_LEN = 2 ;
+static const uint8_t P9N2_PERV_1_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO = 6 ;
+static const uint8_t P9N2_PERV_1_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO_LEN = 2 ;
+static const uint8_t P9N2_PERV_1_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO = 8 ;
+static const uint8_t P9N2_PERV_1_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO_LEN = 2 ;
+static const uint8_t P9N2_PERV_1_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO = 10 ;
+static const uint8_t P9N2_PERV_1_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO_LEN = 2 ;
+static const uint8_t P9N2_PERV_1_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_WAITN = 24 ;
+static const uint8_t P9N2_PERV_1_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_WAITN = 25 ;
+static const uint8_t P9N2_PERV_1_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_WAITN = 26 ;
+static const uint8_t P9N2_PERV_1_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_WAITN = 27 ;
+static const uint8_t P9N2_PERV_1_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_WAITN = 28 ;
+static const uint8_t P9N2_PERV_1_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_WAITN = 29 ;
+static const uint8_t P9N2_PERV_1_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_BANK = 36 ;
+static const uint8_t P9N2_PERV_1_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_BANK = 37 ;
+static const uint8_t P9N2_PERV_1_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_BANK = 38 ;
+static const uint8_t P9N2_PERV_1_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_BANK = 39 ;
+static const uint8_t P9N2_PERV_1_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_BANK = 40 ;
+static const uint8_t P9N2_PERV_1_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_BANK = 41 ;
+static const uint8_t P9N2_PERV_1_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT = 48 ;
+static const uint8_t P9N2_PERV_1_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT_LEN = 3 ;
+static const uint8_t P9N2_PERV_1_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_SELECTOR = 51 ;
+static const uint8_t P9N2_PERV_1_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT = 52 ;
+static const uint8_t P9N2_PERV_1_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT_LEN = 3 ;
+static const uint8_t P9N2_PERV_1_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_SELECTOR = 55 ;
+
+static const uint8_t P9N2_PERV_1_DEBUG_TRACE_CONTROL_SCOM_TRACE_START = 0 ;
+static const uint8_t P9N2_PERV_1_DEBUG_TRACE_CONTROL_SCOM_TRACE_STOP = 1 ;
+static const uint8_t P9N2_PERV_1_DEBUG_TRACE_CONTROL_SCOM_TRACE_RESET = 2 ;
+
+static const uint8_t P9N2_PERV_DEVICE_ID_REG_SOCKET = 36 ;
+static const uint8_t P9N2_PERV_DEVICE_ID_REG_SOCKET_LEN = 3 ;
+static const uint8_t P9N2_PERV_DEVICE_ID_REG_CHIPPOS = 39 ;
+static const uint8_t P9N2_PERV_DEVICE_ID_REG_FUSED_CORE_MODE_SEL0 = 55 ;
+static const uint8_t P9N2_PERV_DEVICE_ID_REG_FUSED_CORE_MODE_SEL1 = 56 ;
+static const uint8_t P9N2_PERV_DEVICE_ID_REG_HW_MODE_SEL = 57 ;
+static const uint8_t P9N2_PERV_DEVICE_ID_REG_TP_EX_FUSE_SMT8_CTYPE_EN = 58 ;
+
+static const uint8_t P9N2_PERV_FSISHIFT_DMA_ERROR_PTR_REGISTER_REG = 0 ;
+static const uint8_t P9N2_PERV_FSISHIFT_DMA_ERROR_PTR_REGISTER_REG_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_FSISHIFT_DMA_MODE_REGISTER_REG_ENABLE = 0 ;
+static const uint8_t P9N2_PERV_FSISHIFT_DMA_MODE_REGISTER_REG_FIFO_SIZE_EQ_1 = 1 ;
+static const uint8_t P9N2_PERV_FSISHIFT_DMA_MODE_REGISTER_REG_UNUSED = 2 ;
+static const uint8_t P9N2_PERV_FSISHIFT_DMA_MODE_REGISTER_REG_UNUSED_LEN = 30 ;
+
+static const uint8_t P9N2_PERV_FSISHIFT_DMA_OP_BLOCKSIZE_REGISTER_OPCODE = 0 ;
+static const uint8_t P9N2_PERV_FSISHIFT_DMA_OP_BLOCKSIZE_REGISTER_OPCODE_LEN = 8 ;
+static const uint8_t P9N2_PERV_FSISHIFT_DMA_OP_BLOCKSIZE_REGISTER_SIZE = 8 ;
+static const uint8_t P9N2_PERV_FSISHIFT_DMA_OP_BLOCKSIZE_REGISTER_SIZE_LEN = 24 ;
+
+static const uint8_t P9N2_PERV_FSISHIFT_DMA_PIB_RCV_BUFFER0_REGISTER_BUF0_REG_DATA0 = 0 ;
+static const uint8_t P9N2_PERV_FSISHIFT_DMA_PIB_RCV_BUFFER0_REGISTER_BUF0_REG_DATA0_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_FSISHIFT_DMA_PIB_RCV_BUFFER1_REGISTER_BUF1_REG_DATA1 = 0 ;
+static const uint8_t P9N2_PERV_FSISHIFT_DMA_PIB_RCV_BUFFER1_REGISTER_BUF1_REG_DATA1_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_FSISHIFT_DMA_PIB_SND_BUFFER0_REGISTER_BUF0_REG_DATA0 = 0 ;
+static const uint8_t P9N2_PERV_FSISHIFT_DMA_PIB_SND_BUFFER0_REGISTER_BUF0_REG_DATA0_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_FSISHIFT_DMA_PIB_SND_BUFFER1_REGISTER_BUF1_REG_DATA0 = 0 ;
+static const uint8_t P9N2_PERV_FSISHIFT_DMA_PIB_SND_BUFFER1_REGISTER_BUF1_REG_DATA0_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_FSISHIFT_DMA_REM_SIZE_REGISTER_REMAINING_WORDS = 8 ;
+static const uint8_t P9N2_PERV_FSISHIFT_DMA_REM_SIZE_REGISTER_REMAINING_WORDS_LEN = 24 ;
+
+static const uint8_t P9N2_PERV_FSISHIFT_DMA_SCOM_CMD_REGISTER_REG = 0 ;
+static const uint8_t P9N2_PERV_FSISHIFT_DMA_SCOM_CMD_REGISTER_REG_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_FSISHIFT_DMA_STAT_COMP_MASK_REGISTER_REG = 0 ;
+static const uint8_t P9N2_PERV_FSISHIFT_DMA_STAT_COMP_MASK_REGISTER_REG_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_DOORBELL_STATUS_CONTROL_1A_DSC1_PERMISSION_TO_SEND_1 = 0 ;
+static const uint8_t P9N2_PERV_DOORBELL_STATUS_CONTROL_1A_DSC1_ABORT_1 = 1 ;
+static const uint8_t P9N2_PERV_DOORBELL_STATUS_CONTROL_1A_DSC1_LBUS_SLAVE_1B_PENDING = 2 ;
+static const uint8_t P9N2_PERV_DOORBELL_STATUS_CONTROL_1A_DSC1_PIB_SLAVE_PENDING = 3 ;
+static const uint8_t P9N2_PERV_DOORBELL_STATUS_CONTROL_1A_DSC1_UNUSED_27 = 4 ;
+static const uint8_t P9N2_PERV_DOORBELL_STATUS_CONTROL_1A_DSC1_XDN_1 = 5 ;
+static const uint8_t P9N2_PERV_DOORBELL_STATUS_CONTROL_1A_DSC1_XUP_1 = 6 ;
+static const uint8_t P9N2_PERV_DOORBELL_STATUS_CONTROL_1A_DSC1_UNUSED_24 = 7 ;
+static const uint8_t P9N2_PERV_DOORBELL_STATUS_CONTROL_1A_DSC1_HEADER_COUNT = 8 ;
+static const uint8_t P9N2_PERV_DOORBELL_STATUS_CONTROL_1A_DSC1_HEADER_COUNT_LEN = 4 ;
+static const uint8_t P9N2_PERV_DOORBELL_STATUS_CONTROL_1A_DSC1_DATA_COUNT = 12 ;
+static const uint8_t P9N2_PERV_DOORBELL_STATUS_CONTROL_1A_DSC1_DATA_COUNT_LEN = 8 ;
+static const uint8_t P9N2_PERV_DOORBELL_STATUS_CONTROL_1A_DSC1_HEADER_COUNT_1B = 20 ;
+static const uint8_t P9N2_PERV_DOORBELL_STATUS_CONTROL_1A_DSC1_HEADER_COUNT_1B_LEN = 4 ;
+static const uint8_t P9N2_PERV_DOORBELL_STATUS_CONTROL_1A_DSC1_DATA_COUNT_1B = 24 ;
+static const uint8_t P9N2_PERV_DOORBELL_STATUS_CONTROL_1A_DSC1_DATA_COUNT_1B_LEN = 8 ;
+
+static const uint8_t P9N2_PERV_DOORBELL_STATUS_CONTROL_2A_DSC2_PERMISSION_TO_SEND_2 = 0 ;
+static const uint8_t P9N2_PERV_DOORBELL_STATUS_CONTROL_2A_DSC2_ABORT_2 = 1 ;
+static const uint8_t P9N2_PERV_DOORBELL_STATUS_CONTROL_2A_DSC2_LBUS_SLAVE_2B_PENDING = 2 ;
+static const uint8_t P9N2_PERV_DOORBELL_STATUS_CONTROL_2A_DSC2_PIB_SLAVE_PENDING = 3 ;
+static const uint8_t P9N2_PERV_DOORBELL_STATUS_CONTROL_2A_DSC2_UNUSED_27 = 4 ;
+static const uint8_t P9N2_PERV_DOORBELL_STATUS_CONTROL_2A_DSC2_XDN_2 = 5 ;
+static const uint8_t P9N2_PERV_DOORBELL_STATUS_CONTROL_2A_DSC2_XUP_2 = 6 ;
+static const uint8_t P9N2_PERV_DOORBELL_STATUS_CONTROL_2A_DSC2_UNUSED_24 = 7 ;
+static const uint8_t P9N2_PERV_DOORBELL_STATUS_CONTROL_2A_DSC2_HEADER_COUNT = 8 ;
+static const uint8_t P9N2_PERV_DOORBELL_STATUS_CONTROL_2A_DSC2_HEADER_COUNT_LEN = 4 ;
+static const uint8_t P9N2_PERV_DOORBELL_STATUS_CONTROL_2A_DSC2_DATA_COUNT = 12 ;
+static const uint8_t P9N2_PERV_DOORBELL_STATUS_CONTROL_2A_DSC2_DATA_COUNT_LEN = 8 ;
+static const uint8_t P9N2_PERV_DOORBELL_STATUS_CONTROL_2A_DSC2_HEADER_COUNT_2B = 20 ;
+static const uint8_t P9N2_PERV_DOORBELL_STATUS_CONTROL_2A_DSC2_HEADER_COUNT_2B_LEN = 4 ;
+static const uint8_t P9N2_PERV_DOORBELL_STATUS_CONTROL_2A_DSC2_DATA_COUNT_2B = 24 ;
+static const uint8_t P9N2_PERV_DOORBELL_STATUS_CONTROL_2A_DSC2_DATA_COUNT_2B_LEN = 8 ;
+
+static const uint8_t P9N2_PERV_1_DTS_RESULT0_0_RESULT = 0 ;
+static const uint8_t P9N2_PERV_1_DTS_RESULT0_0_RESULT_LEN = 16 ;
+static const uint8_t P9N2_PERV_1_DTS_RESULT0_1_RESULT = 16 ;
+static const uint8_t P9N2_PERV_1_DTS_RESULT0_1_RESULT_LEN = 16 ;
+
+static const uint8_t P9N2_PERV_1_DTS_TRC_RESULT_TIMESTAMP_COUNTER_VALUE = 0 ;
+static const uint8_t P9N2_PERV_1_DTS_TRC_RESULT_TIMESTAMP_COUNTER_VALUE_LEN = 44 ;
+static const uint8_t P9N2_PERV_1_DTS_TRC_RESULT_TIMESTAMP_COUNTER_OVERFLOW_ERR = 44 ;
+static const uint8_t P9N2_PERV_1_DTS_TRC_RESULT_1 = 48 ;
+static const uint8_t P9N2_PERV_1_DTS_TRC_RESULT_1_LEN = 16 ;
+
+static const uint8_t P9N2_PERV_1_EDRAM_STATUS_STAT = 0 ;
+static const uint8_t P9N2_PERV_1_EDRAM_STATUS_STAT_LEN = 4 ;
+
+static const uint8_t P9N2_PERV_ERROR_REG_TIMEOUT_ACTIVE = 0 ;
+static const uint8_t P9N2_PERV_ERROR_REG_PARITY_ERR = 1 ;
+static const uint8_t P9N2_PERV_ERROR_REG_BEAT_NUM_ERR = 2 ;
+static const uint8_t P9N2_PERV_ERROR_REG_BEAT_REC_ERR = 3 ;
+static const uint8_t P9N2_PERV_ERROR_REG_RECEIVED = 4 ;
+static const uint8_t P9N2_PERV_ERROR_REG_RX_PCB_DATA_P_ERR = 5 ;
+static const uint8_t P9N2_PERV_ERROR_REG_PIB_ADDR_P_ERR = 6 ;
+static const uint8_t P9N2_PERV_ERROR_REG_PIB_DATA_P_ERR = 7 ;
+
+static const uint8_t P9N2_PERV_1_ERROR_STATUS_PCB_WRITE_NOT_ALLOWED_ERR = 0 ;
+static const uint8_t P9N2_PERV_1_ERROR_STATUS_PCB_READ_NOT_ALLOWED_ERR = 1 ;
+static const uint8_t P9N2_PERV_1_ERROR_STATUS_PCB_PARITY_ON_CMD_ERR = 2 ;
+static const uint8_t P9N2_PERV_1_ERROR_STATUS_PCB_ADDRESS_NOT_VALID_ERR = 3 ;
+static const uint8_t P9N2_PERV_1_ERROR_STATUS_PCB_PARITY_ON_ADDR_ERR = 4 ;
+static const uint8_t P9N2_PERV_1_ERROR_STATUS_PCB_PARITY_ON_DATA_ERR = 5 ;
+static const uint8_t P9N2_PERV_1_ERROR_STATUS_PCB_PROTECTED_ACCESS_INVALID_ERR = 6 ;
+static const uint8_t P9N2_PERV_1_ERROR_STATUS_PCB_PARITY_ON_SPCIF_ERR = 7 ;
+static const uint8_t P9N2_PERV_1_ERROR_STATUS_PCB_WRITE_AND_OPCG_IP_ERR = 8 ;
+static const uint8_t P9N2_PERV_1_ERROR_STATUS_SCAN_READ_AND_OPCG_IP_ERR = 9 ;
+static const uint8_t P9N2_PERV_1_ERROR_STATUS_CLOCK_CMD_CONFLICT_ERR = 10 ;
+static const uint8_t P9N2_PERV_1_ERROR_STATUS_SCAN_COLLISION_ERR = 11 ;
+static const uint8_t P9N2_PERV_1_ERROR_STATUS_PREVENTED_SCAN_COLLISION_ERR = 12 ;
+static const uint8_t P9N2_PERV_1_ERROR_STATUS_OPCG_TRIGGER_ERR = 13 ;
+static const uint8_t P9N2_PERV_1_ERROR_STATUS_PHASE_CNT_CORRUPTION_ERR = 14 ;
+static const uint8_t P9N2_PERV_1_ERROR_STATUS_CLOCK_CMD_PREVENTED_ERR = 15 ;
+static const uint8_t P9N2_PERV_1_ERROR_STATUS_PARITY_ON_OPCG_SM_ERR = 16 ;
+static const uint8_t P9N2_PERV_1_ERROR_STATUS_PARITY_ON_CLOCK_MUX_REG_ERR = 17 ;
+static const uint8_t P9N2_PERV_1_ERROR_STATUS_PARITY_ON_OPCG_REG_ERR = 18 ;
+static const uint8_t P9N2_PERV_1_ERROR_STATUS_PARITY_ON_SYNC_CONFIG_REG_ERR = 19 ;
+static const uint8_t P9N2_PERV_1_ERROR_STATUS_PARITY_ON_XSTOP_REG_ERR = 20 ;
+static const uint8_t P9N2_PERV_1_ERROR_STATUS_PARITY_ON_GPIO_REG_ERR = 21 ;
+static const uint8_t P9N2_PERV_1_ERROR_STATUS_CLKCMD_REQUEST_ERR = 22 ;
+static const uint8_t P9N2_PERV_1_ERROR_STATUS_CBS_PROTOCOL_ERR = 23 ;
+static const uint8_t P9N2_PERV_1_ERROR_STATUS_VITL_ALIGN_ERR = 24 ;
+static const uint8_t P9N2_PERV_1_ERROR_STATUS_UNIT_SYNC_LVL_ERR = 25 ;
+static const uint8_t P9N2_PERV_1_ERROR_STATUS_PARITY_ON_SELFBOOT_CMD_STATE_ERR = 26 ;
+static const uint8_t P9N2_PERV_1_ERROR_STATUS_OPCG_STOPPED_BY_PCB_ERR = 27 ;
+static const uint8_t P9N2_PERV_1_ERROR_STATUS_EDRAM_SCAN_PREVENTED_ERR = 28 ;
+static const uint8_t P9N2_PERV_1_ERROR_STATUS_UNUSED_ERROR29 = 29 ;
+static const uint8_t P9N2_PERV_1_ERROR_STATUS_UNUSED_ERROR30 = 30 ;
+static const uint8_t P9N2_PERV_1_ERROR_STATUS_UNUSED_ERROR31 = 31 ;
+
+static const uint8_t P9N2_PERV_1_ERR_STATUS_REG_SERIAL_SHIFTCNT_MODEREG_PARITY_ERR_HOLD = 0 ;
+static const uint8_t P9N2_PERV_1_ERR_STATUS_REG_THERM_MODEREG_PARITY_ERR_HOLD = 1 ;
+static const uint8_t P9N2_PERV_1_ERR_STATUS_REG_SKITTER_MODEREG_PARITY_ERR_HOLD = 2 ;
+static const uint8_t P9N2_PERV_1_ERR_STATUS_REG_SKITTER_FORCEREG_PARITY_ERR_HOLD = 3 ;
+static const uint8_t P9N2_PERV_1_ERR_STATUS_REG_SCAN_INIT_VERSION_REG_PARITY_ERR_HOLD = 4 ;
+static const uint8_t P9N2_PERV_1_ERR_STATUS_REG_VOLT_MODEREG_PARITY_ERR_HOLD = 5 ;
+static const uint8_t P9N2_PERV_1_ERR_STATUS_REG_SKITTER_CLKSRCREG_PARITY_ERR_HOLD = 6 ;
+static const uint8_t P9N2_PERV_1_ERR_STATUS_REG_COUNT_STATE_ERR_HOLD = 7 ;
+static const uint8_t P9N2_PERV_1_ERR_STATUS_REG_RUN_STATE_ERR_HOLD = 8 ;
+static const uint8_t P9N2_PERV_1_ERR_STATUS_REG_THRES_THERM_STATE_ERR_HOLD = 9 ;
+static const uint8_t P9N2_PERV_1_ERR_STATUS_REG_THRES_THERM_OVERFLOW_ERR_HOLD = 10 ;
+static const uint8_t P9N2_PERV_1_ERR_STATUS_REG_SHIFTER_PARITY_ERR_HOLD = 11 ;
+static const uint8_t P9N2_PERV_1_ERR_STATUS_REG_SHIFTER_VALID_ERR_HOLD = 12 ;
+static const uint8_t P9N2_PERV_1_ERR_STATUS_REG_TIMEOUT_ERR_HOLD = 13 ;
+static const uint8_t P9N2_PERV_1_ERR_STATUS_REG_F_SKITTER_ERR_HOLD = 14 ;
+static const uint8_t P9N2_PERV_1_ERR_STATUS_REG_PCB_ERR_HOLD_OUT = 15 ;
+static const uint8_t P9N2_PERV_1_ERR_STATUS_REG_SERIAL_SHIFTCNT_MODEREG_PARITY_MASK = 16 ;
+static const uint8_t P9N2_PERV_1_ERR_STATUS_REG_THERM_MODEREG_PARITY_MASK = 17 ;
+static const uint8_t P9N2_PERV_1_ERR_STATUS_REG_SKITTER_MODEREG_PARITY_MASK = 18 ;
+static const uint8_t P9N2_PERV_1_ERR_STATUS_REG_SKITTER_FORCEREG_PARITY_MASK = 19 ;
+static const uint8_t P9N2_PERV_1_ERR_STATUS_REG_SCAN_INIT_VERSION_PARITY_MASK = 20 ;
+static const uint8_t P9N2_PERV_1_ERR_STATUS_REG_VOLT_MODEREG_PARITY_MASK = 21 ;
+static const uint8_t P9N2_PERV_1_ERR_STATUS_REG_COUNT_STATE_MASK = 23 ;
+static const uint8_t P9N2_PERV_1_ERR_STATUS_REG_RUN_STATE_MASK = 24 ;
+static const uint8_t P9N2_PERV_1_ERR_STATUS_REG_THRES_STATE_MASK = 25 ;
+static const uint8_t P9N2_PERV_1_ERR_STATUS_REG_OVERFLOW_MASK = 26 ;
+static const uint8_t P9N2_PERV_1_ERR_STATUS_REG_SHIFTER_PARITY_MASK = 27 ;
+static const uint8_t P9N2_PERV_1_ERR_STATUS_REG_SHIFTER_VALID_MASK = 28 ;
+static const uint8_t P9N2_PERV_1_ERR_STATUS_REG_TIMEOUT_MASK = 29 ;
+static const uint8_t P9N2_PERV_1_ERR_STATUS_REG_F_SKITTER_READ_MASK = 30 ;
+static const uint8_t P9N2_PERV_1_ERR_STATUS_REG_PCB_MASK = 31 ;
+static const uint8_t P9N2_PERV_1_ERR_STATUS_REG_COUNT_STATE_LT = 40 ;
+static const uint8_t P9N2_PERV_1_ERR_STATUS_REG_COUNT_STATE_LT_LEN = 4 ;
+static const uint8_t P9N2_PERV_1_ERR_STATUS_REG_RUN_STATE_LT = 44 ;
+static const uint8_t P9N2_PERV_1_ERR_STATUS_REG_RUN_STATE_LT_LEN = 3 ;
+static const uint8_t P9N2_PERV_1_ERR_STATUS_REG_SHIFT_DTS_LT = 47 ;
+static const uint8_t P9N2_PERV_1_ERR_STATUS_REG_SHIFT_VOLT_LT = 48 ;
+static const uint8_t P9N2_PERV_1_ERR_STATUS_REG_READ_STATE_LT = 49 ;
+static const uint8_t P9N2_PERV_1_ERR_STATUS_REG_READ_STATE_LT_LEN = 2 ;
+static const uint8_t P9N2_PERV_1_ERR_STATUS_REG_WRITE_STATE_LT = 51 ;
+static const uint8_t P9N2_PERV_1_ERR_STATUS_REG_WRITE_STATE_LT_LEN = 4 ;
+static const uint8_t P9N2_PERV_1_ERR_STATUS_REG_SAMPLE_DTS_LT = 55 ;
+static const uint8_t P9N2_PERV_1_ERR_STATUS_REG_MEASURE_VOLT_LT = 56 ;
+static const uint8_t P9N2_PERV_1_ERR_STATUS_REG_READ_CPM_LT = 57 ;
+static const uint8_t P9N2_PERV_1_ERR_STATUS_REG_WRITE_CPM_LT = 58 ;
+static const uint8_t P9N2_PERV_1_ERR_STATUS_REG_UNUSED = 59 ;
+
+static const uint8_t P9N2_PERV_FSII2C_EXTENDED_STATUS_A_MSM_CURR_STATE_0 = 11 ;
+static const uint8_t P9N2_PERV_FSII2C_EXTENDED_STATUS_A_MSM_CURR_STATE_0_LEN = 5 ;
+static const uint8_t P9N2_PERV_FSII2C_EXTENDED_STATUS_A_SELF_BUSY_0 = 25 ;
+
+static const uint8_t P9N2_PERV_FSII2C_FIFO1_REGISTER_READ_A_FIFO_BITS_READ0_0 = 0 ;
+static const uint8_t P9N2_PERV_FSII2C_FIFO1_REGISTER_READ_A_FIFO_BITS_READ0_0_LEN = 8 ;
+
+static const uint8_t P9N2_PERV_FIRST_ERR_REG_TIMEOUT_ACTIVE = 0 ;
+static const uint8_t P9N2_PERV_FIRST_ERR_REG_PARITY = 1 ;
+static const uint8_t P9N2_PERV_FIRST_ERR_REG_BEAT_NUM = 2 ;
+static const uint8_t P9N2_PERV_FIRST_ERR_REG_BEAT_REC = 3 ;
+static const uint8_t P9N2_PERV_FIRST_ERR_REG_RECEIVED_ERROR = 4 ;
+static const uint8_t P9N2_PERV_FIRST_ERR_REG_RX_PCB_DATA_P = 5 ;
+static const uint8_t P9N2_PERV_FIRST_ERR_REG_PIB_ADDR_P = 6 ;
+static const uint8_t P9N2_PERV_FIRST_ERR_REG_PIB_DATA_P = 7 ;
+
+static const uint8_t P9N2_PERV_FIRST_REPLY_REG_REGISTER = 0 ;
+static const uint8_t P9N2_PERV_FIRST_REPLY_REG_REGISTER_LEN = 6 ;
+
+static const uint8_t P9N2_PERV_1_FIR_MASK_IN0 = 0 ;
+static const uint8_t P9N2_PERV_1_FIR_MASK_IN1 = 1 ;
+static const uint8_t P9N2_PERV_1_FIR_MASK_IN2 = 2 ;
+static const uint8_t P9N2_PERV_1_FIR_MASK_IN3 = 3 ;
+static const uint8_t P9N2_PERV_1_FIR_MASK_IN4 = 4 ;
+static const uint8_t P9N2_PERV_1_FIR_MASK_IN5 = 5 ;
+static const uint8_t P9N2_PERV_1_FIR_MASK_IN6 = 6 ;
+static const uint8_t P9N2_PERV_1_FIR_MASK_IN7 = 7 ;
+static const uint8_t P9N2_PERV_1_FIR_MASK_IN8 = 8 ;
+static const uint8_t P9N2_PERV_1_FIR_MASK_IN9 = 9 ;
+static const uint8_t P9N2_PERV_1_FIR_MASK_IN10 = 10 ;
+static const uint8_t P9N2_PERV_1_FIR_MASK_IN11 = 11 ;
+static const uint8_t P9N2_PERV_1_FIR_MASK_IN12 = 12 ;
+static const uint8_t P9N2_PERV_1_FIR_MASK_IN13 = 13 ;
+static const uint8_t P9N2_PERV_1_FIR_MASK_IN14 = 14 ;
+static const uint8_t P9N2_PERV_1_FIR_MASK_IN15 = 15 ;
+static const uint8_t P9N2_PERV_1_FIR_MASK_IN16 = 16 ;
+static const uint8_t P9N2_PERV_1_FIR_MASK_IN17 = 17 ;
+static const uint8_t P9N2_PERV_1_FIR_MASK_IN18 = 18 ;
+static const uint8_t P9N2_PERV_1_FIR_MASK_IN19 = 19 ;
+static const uint8_t P9N2_PERV_1_FIR_MASK_IN20 = 20 ;
+static const uint8_t P9N2_PERV_1_FIR_MASK_IN21 = 21 ;
+static const uint8_t P9N2_PERV_1_FIR_MASK_IN21_LEN = 5 ;
+static const uint8_t P9N2_PERV_1_FIR_MASK_IN26 = 26 ;
+
+static const uint8_t P9N2_PERV_1_FMU_FORCE_OP_REG_FORCE_MEASURE = 0 ;
+static const uint8_t P9N2_PERV_1_FMU_FORCE_OP_REG_FORCE_FMU_SM_RESET = 1 ;
+
+static const uint8_t P9N2_PERV_1_FMU_KVREF_DATAREG_FMU_KVREF_DATAREG = 0 ;
+static const uint8_t P9N2_PERV_1_FMU_KVREF_DATAREG_FMU_KVREF_DATAREG_LEN = 64 ;
+
+static const uint8_t P9N2_PERV_1_FMU_MODE_REG_TOD_CNTR_REF = 12 ;
+static const uint8_t P9N2_PERV_1_FMU_MODE_REG_TOD_CNTR_REF_LEN = 4 ;
+static const uint8_t P9N2_PERV_1_FMU_MODE_REG_UNUSED1 = 16 ;
+static const uint8_t P9N2_PERV_1_FMU_MODE_REG_POWER_UP_CNTR_REF = 17 ;
+static const uint8_t P9N2_PERV_1_FMU_MODE_REG_POWER_UP_CNTR_REF_LEN = 3 ;
+static const uint8_t P9N2_PERV_1_FMU_MODE_REG_UNUSED2 = 20 ;
+static const uint8_t P9N2_PERV_1_FMU_MODE_REG_UNUSED2_LEN = 4 ;
+
+static const uint8_t P9N2_PERV_1_FMU_OSC_CNTR1_REG_FMU_PULSE_GEN_REG_ERR = 1 ;
+static const uint8_t P9N2_PERV_1_FMU_OSC_CNTR1_REG_FMU_MODEREG_P_ERR = 2 ;
+static const uint8_t P9N2_PERV_1_FMU_OSC_CNTR1_REG_RESULT_AVAILABLE = 3 ;
+static const uint8_t P9N2_PERV_1_FMU_OSC_CNTR1_REG_PULSE1_CNTR = 4 ;
+static const uint8_t P9N2_PERV_1_FMU_OSC_CNTR1_REG_PULSE1_CNTR_LEN = 24 ;
+
+static const uint8_t P9N2_PERV_1_FMU_OSC_CNTR2_REG_FMU_PULSE_GEN_REG_ERR = 1 ;
+static const uint8_t P9N2_PERV_1_FMU_OSC_CNTR2_REG_FMU_MODEREG_P_ERR = 2 ;
+static const uint8_t P9N2_PERV_1_FMU_OSC_CNTR2_REG_RESULT_AVAILABLE = 3 ;
+static const uint8_t P9N2_PERV_1_FMU_OSC_CNTR2_REG_PULSE2_CNTR = 4 ;
+static const uint8_t P9N2_PERV_1_FMU_OSC_CNTR2_REG_PULSE2_CNTR_LEN = 24 ;
+
+static const uint8_t P9N2_PERV_1_FMU_PULSE_GEN_REG_INT_ENA = 0 ;
+static const uint8_t P9N2_PERV_1_FMU_PULSE_GEN_REG_UNUSED3 = 1 ;
+static const uint8_t P9N2_PERV_1_FMU_PULSE_GEN_REG_INT_CNTR_REF = 2 ;
+static const uint8_t P9N2_PERV_1_FMU_PULSE_GEN_REG_INT_CNTR_REF_LEN = 10 ;
+
+static const uint8_t P9N2_PERV_1_FMU_VMEAS_MAX_RESULT_VMEAS_MAX_RESULT = 0 ;
+static const uint8_t P9N2_PERV_1_FMU_VMEAS_MAX_RESULT_VMEAS_MAX_RESULT_LEN = 8 ;
+
+static const uint8_t P9N2_PERV_1_FMU_VMEAS_MIN_RESULT_VMEAS_MIN_RESULT = 0 ;
+static const uint8_t P9N2_PERV_1_FMU_VMEAS_MIN_RESULT_VMEAS_MIN_RESULT_LEN = 8 ;
+
+static const uint8_t P9N2_PERV_FSB_FSB_DNFIFO_DATA_OUT_DNFIFO_DATA_OUT_PORT = 0 ;
+static const uint8_t P9N2_PERV_FSB_FSB_DNFIFO_DATA_OUT_DNFIFO_DATA_OUT_PORT_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_FSB_FSB_DOWNFIFO_ACK_EOT_DNFIFO_ACK = 0 ;
+
+static const uint8_t P9N2_PERV_FSB_FSB_DOWNFIFO_MTC_DNFIFO_MCT = 0 ;
+static const uint8_t P9N2_PERV_FSB_FSB_DOWNFIFO_MTC_DNFIFO_MCT_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_FSB_FSB_DOWNFIFO_RESET_DNFIFO_RESET = 0 ;
+
+static const uint8_t P9N2_PERV_FSB_FSB_DOWNFIFO_STATUS_DNFIFO_REQ_RESET_FR_SBE = 6 ;
+static const uint8_t P9N2_PERV_FSB_FSB_DOWNFIFO_STATUS_DNFIFO_REQ_RESET_FR_SP = 7 ;
+static const uint8_t P9N2_PERV_FSB_FSB_DOWNFIFO_STATUS_DNFIFO_DEQUEUED_EOT_FLAG = 8 ;
+static const uint8_t P9N2_PERV_FSB_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_FULL = 10 ;
+static const uint8_t P9N2_PERV_FSB_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_EMPTY = 11 ;
+static const uint8_t P9N2_PERV_FSB_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_ENTRY_COUNT = 12 ;
+static const uint8_t P9N2_PERV_FSB_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_ENTRY_COUNT_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSB_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_VALID_FLAGS = 16 ;
+static const uint8_t P9N2_PERV_FSB_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_VALID_FLAGS_LEN = 8 ;
+static const uint8_t P9N2_PERV_FSB_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_EOT_FLAGS = 24 ;
+static const uint8_t P9N2_PERV_FSB_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_EOT_FLAGS_LEN = 8 ;
+
+static const uint8_t P9N2_PERV_FSB_FSB_UPFIFO_DATA_IN_UPFIFO_DATA_IN_PORT = 0 ;
+static const uint8_t P9N2_PERV_FSB_FSB_UPFIFO_DATA_IN_UPFIFO_DATA_IN_PORT_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_FSB_FSB_UPFIFO_REQ_RESET_UPFIFO_REQ_RESET = 0 ;
+
+static const uint8_t P9N2_PERV_FSB_FSB_UPFIFO_SIG_EOT_UPFIFO_SIGNAL = 0 ;
+
+static const uint8_t P9N2_PERV_FSB_FSB_UPFIFO_STATUS_REQ_RESET_FR_SP = 6 ;
+static const uint8_t P9N2_PERV_FSB_FSB_UPFIFO_STATUS_REQ_RESET_FR_SBE = 7 ;
+static const uint8_t P9N2_PERV_FSB_FSB_UPFIFO_STATUS_DEQUEUED_EOT_FLAG = 8 ;
+static const uint8_t P9N2_PERV_FSB_FSB_UPFIFO_STATUS_FIFO_FULL = 10 ;
+static const uint8_t P9N2_PERV_FSB_FSB_UPFIFO_STATUS_FIFO_EMPTY = 11 ;
+static const uint8_t P9N2_PERV_FSB_FSB_UPFIFO_STATUS_FIFO_ENTRY_COUNT = 12 ;
+static const uint8_t P9N2_PERV_FSB_FSB_UPFIFO_STATUS_FIFO_ENTRY_COUNT_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSB_FSB_UPFIFO_STATUS_FIFO_VALID_FLAGS = 16 ;
+static const uint8_t P9N2_PERV_FSB_FSB_UPFIFO_STATUS_FIFO_VALID_FLAGS_LEN = 8 ;
+static const uint8_t P9N2_PERV_FSB_FSB_UPFIFO_STATUS_FIFO_EOT_FLAGS = 24 ;
+static const uint8_t P9N2_PERV_FSB_FSB_UPFIFO_STATUS_FIFO_EOT_FLAGS_LEN = 8 ;
+
+static const uint8_t P9N2_PERV_FSISCRPD1_FSI_SCRATCH_PAD1 = 0 ;
+static const uint8_t P9N2_PERV_FSISCRPD1_FSI_SCRATCH_PAD1_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_FSISCRPD2_FSI_SCRATCH_PAD2 = 0 ;
+static const uint8_t P9N2_PERV_FSISCRPD2_FSI_SCRATCH_PAD2_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_FSISCRPD3_FSI_SCRATCH_PAD3 = 0 ;
+static const uint8_t P9N2_PERV_FSISCRPD3_FSI_SCRATCH_PAD3_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_FSI_A_LLMOD_EXTEND_TIMO = 29 ;
+static const uint8_t P9N2_PERV_FSI_A_LLMOD_DISABLE_GAP = 30 ;
+static const uint8_t P9N2_PERV_FSI_A_LLMOD_ASYNC_MODE = 31 ;
+
+static const uint8_t P9N2_PERV_FSI_A_LLSTAT_RESERVED_0 = 0 ;
+static const uint8_t P9N2_PERV_FSI_A_LLSTAT_RESERVED_0_LEN = 7 ;
+static const uint8_t P9N2_PERV_FSI_A_LLSTAT_NO_CLK = 7 ;
+static const uint8_t P9N2_PERV_FSI_A_LLSTAT_RESERVED_2 = 8 ;
+static const uint8_t P9N2_PERV_FSI_A_LLSTAT_RESERVED_2_LEN = 2 ;
+static const uint8_t P9N2_PERV_FSI_A_LLSTAT_BAD_HANDSHAKE_AT_START = 10 ;
+static const uint8_t P9N2_PERV_FSI_A_LLSTAT_TIMEOUT = 11 ;
+static const uint8_t P9N2_PERV_FSI_A_LLSTAT_LBUS_BUSY = 12 ;
+static const uint8_t P9N2_PERV_FSI_A_LLSTAT_OPB_BUSY = 13 ;
+static const uint8_t P9N2_PERV_FSI_A_LLSTAT_RESERVED_3 = 14 ;
+static const uint8_t P9N2_PERV_FSI_A_LLSTAT_BREAK_PENDING = 15 ;
+static const uint8_t P9N2_PERV_FSI_A_LLSTAT_RESERVED_4 = 16 ;
+static const uint8_t P9N2_PERV_FSI_A_LLSTAT_RESERVED_4_LEN = 2 ;
+static const uint8_t P9N2_PERV_FSI_A_LLSTAT_HANDSHAKE_STATE = 18 ;
+static const uint8_t P9N2_PERV_FSI_A_LLSTAT_HANDSHAKE_STATE_LEN = 2 ;
+static const uint8_t P9N2_PERV_FSI_A_LLSTAT_CFAM_CYCLE_TIME = 20 ;
+static const uint8_t P9N2_PERV_FSI_A_LLSTAT_CFAM_CYCLE_TIME_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSI_A_LLSTAT_REFCLOCK_STATUS = 24 ;
+static const uint8_t P9N2_PERV_FSI_A_LLSTAT_REFCLOCK_STATUS_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSI_A_LLSTAT_RESERVED_5 = 28 ;
+static const uint8_t P9N2_PERV_FSI_A_LLSTAT_RESERVED_5_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_LLSTAT_ASYNC_MODE = 31 ;
+
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MAEB_BRIDGE_ERROR = 0 ;
+
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MAEB_BRIDGE_ERROR = 0 ;
+
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MCENP0_CLR_PORT_ENABLE = 0 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MCENP0_CLR_PORT_ENABLE_LEN = 8 ;
+
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MCENP0_CLR_PORT_ENABLE = 0 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MCENP0_CLR_PORT_ENABLE_LEN = 8 ;
+
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MENP0_PORT_ENABLE = 0 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MENP0_PORT_1_ENABLE = 1 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MENP0_PORT_2_ENABLE = 2 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MENP0_PORT_3_ENABLE = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MENP0_PORT_4_ENABLE = 4 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MENP0_PORT_5_ENABLE = 5 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MENP0_PORT_6_ENABLE = 6 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MENP0_PORT_7_ENABLE = 7 ;
+
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MENP0_PORT_ENABLE = 0 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MENP0_PORT_1_ENABLE = 1 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MENP0_PORT_2_ENABLE = 2 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MENP0_PORT_3_ENABLE = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MENP0_PORT_4_ENABLE = 4 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MENP0_PORT_5_ENABLE = 5 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MENP0_PORT_6_ENABLE = 6 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MENP0_PORT_7_ENABLE = 7 ;
+
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MESRB0_FIRST_ERROR = 0 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MESRB0_FIRST_ERROR_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MESRB0_CRC_ERROR_COUNT = 4 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MESRB0_CRC_ERROR_COUNT_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MESRB0_MMODE_PARITY_CHECK = 8 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MESRB0_MDLYR_PARITY_CHECK = 9 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MESRB0_MCRSP0_PARITY_CHECK = 10 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MESRB0_MENP0_PARITY_CHECK = 11 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MESRB0_MSIEP0_PARITY_CHECK = 12 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MESRB0_MSSIEP0_PARITY_CHECK = 13 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MESRB0_REGISTER_ACCESS_FSM_CHECK = 14 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MESRB0_OPB_BUS_ACCESS_FSM_CHECK = 15 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MESRB0_REGISTER_ACCESS_ERROR = 16 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MESRB0_FAILING_OPB_MASTER_FRST = 17 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MESRB0_FAILING_OPB_MASTER_FRST_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MESRB0_ACTUAL_ERROR = 20 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MESRB0_ACTUAL_ERROR_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MESRB0_SELECTED_ERROR = 24 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MESRB0_SELECTED_ERROR_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MESRB0_FAILING_OPB_MASTER_ACT = 29 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MESRB0_FAILING_OPB_MASTER_ACT_LEN = 3 ;
+
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MESRB0_FIRST_ERROR = 0 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MESRB0_FIRST_ERROR_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MESRB0_CRC_ERROR_COUNT = 4 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MESRB0_CRC_ERROR_COUNT_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MESRB0_MMODE_PARITY_CHECK = 8 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MESRB0_MDLYR_PARITY_CHECK = 9 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MESRB0_MCRSP0_PARITY_CHECK = 10 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MESRB0_MENP0_PARITY_CHECK = 11 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MESRB0_MSIEP0_PARITY_CHECK = 12 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MESRB0_MSSIEP0_PARITY_CHECK = 13 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MESRB0_REGISTER_ACCESS_FSM_CHECK = 14 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MESRB0_OPB_BUS_ACCESS_FSM_CHECK = 15 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MESRB0_REGISTER_ACCESS_ERROR = 16 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MESRB0_FAILING_OPB_MASTER_FRST = 17 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MESRB0_FAILING_OPB_MASTER_FRST_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MESRB0_ACTUAL_ERROR = 20 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MESRB0_ACTUAL_ERROR_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MESRB0_SELECTED_ERROR = 24 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MESRB0_SELECTED_ERROR_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MESRB0_FAILING_OPB_MASTER_ACT = 29 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MESRB0_FAILING_OPB_MASTER_ACT_LEN = 3 ;
+
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MLEVP0_PORT_LEVEL = 0 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MLEVP0_PORT_LEVEL_1 = 1 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MLEVP0_PORT_LEVEL_2 = 2 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MLEVP0_PORT_LEVEL_3 = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MLEVP0_PORT_LEVEL_4 = 4 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MLEVP0_PORT_LEVEL_5 = 5 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MLEVP0_PORT_LEVEL_6 = 6 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MLEVP0_PORT_LEVEL_7 = 7 ;
+
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MLEVP0_PORT_LEVEL = 0 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MLEVP0_PORT_LEVEL_1 = 1 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MLEVP0_PORT_LEVEL_2 = 2 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MLEVP0_PORT_LEVEL_3 = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MLEVP0_PORT_LEVEL_4 = 4 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MLEVP0_PORT_LEVEL_5 = 5 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MLEVP0_PORT_LEVEL_6 = 6 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MLEVP0_PORT_LEVEL_7 = 7 ;
+
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MLEVP1_PORT_LEVEL = 0 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MLEVP1_PORT_LEVEL_1 = 1 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MLEVP1_PORT_LEVEL_2 = 2 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MLEVP1_PORT_LEVEL_3 = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MLEVP1_PORT_LEVEL_4 = 4 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MLEVP1_PORT_LEVEL_5 = 5 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MLEVP1_PORT_LEVEL_6 = 6 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MLEVP1_PORT_LEVEL_7 = 7 ;
+
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MLEVP1_PORT_LEVEL = 0 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MLEVP1_PORT_LEVEL_1 = 1 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MLEVP1_PORT_LEVEL_2 = 2 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MLEVP1_PORT_LEVEL_3 = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MLEVP1_PORT_LEVEL_4 = 4 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MLEVP1_PORT_LEVEL_5 = 5 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MLEVP1_PORT_LEVEL_6 = 6 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MLEVP1_PORT_LEVEL_7 = 7 ;
+
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MMODE_ENABLE_IPOLL_AND_DMA = 0 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MMODE_ENABLE_HW_ERROR_RECOVERY = 1 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MMODE_ENABLE_RELATIVE_ADDRESS_CMDS = 2 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MMODE_ENABLE_PARITY_CHECK = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MMODE_CLOCK_RATE_SELECTION = 4 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MMODE_CLOCK_RATE_SELECTION_LEN = 10 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MMODE_CLOCK_RATE_SELECTION_1 = 14 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MMODE_CLOCK_RATE_SELECTION_1_LEN = 10 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MMODE_CLOCK_DIV_4 = 25 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MMODE_TIMEOUT_SEL = 26 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MMODE_TIMEOUT_SEL_LEN = 2 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MMODE_RECEIVER_MODE = 29 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MMODE_RECEIVER_MODE_LEN = 3 ;
+
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MMODE_ENABLE_IPOLL_AND_DMA = 0 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MMODE_ENABLE_HW_ERROR_RECOVERY = 1 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MMODE_ENABLE_RELATIVE_ADDRESS_CMDS = 2 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MMODE_ENABLE_PARITY_CHECK = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MMODE_CLOCK_RATE_SELECTION = 4 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MMODE_CLOCK_RATE_SELECTION_LEN = 10 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MMODE_CLOCK_RATE_SELECTION_1 = 14 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MMODE_CLOCK_RATE_SELECTION_1_LEN = 10 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MMODE_CLOCK_DIV_4 = 25 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MMODE_TIMEOUT_SEL = 26 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MMODE_TIMEOUT_SEL_LEN = 2 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MMODE_RECEIVER_MODE = 29 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MMODE_RECEIVER_MODE_LEN = 3 ;
+
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MREFP0_PORT_HOT_PLUG = 0 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MREFP0_PORT_HOT_PLUG_1 = 1 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MREFP0_PORT_HOT_PLUG_2 = 2 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MREFP0_PORT_HOT_PLUG_3 = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MREFP0_PORT_HOT_PLUG_4 = 4 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MREFP0_PORT_HOT_PLUG_5 = 5 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MREFP0_PORT_HOT_PLUG_6 = 6 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MREFP0_PORT_HOT_PLUG_7 = 7 ;
+
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MREFP0_PORT_HOT_PLUG = 0 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MREFP0_PORT_HOT_PLUG_1 = 1 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MREFP0_PORT_HOT_PLUG_2 = 2 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MREFP0_PORT_HOT_PLUG_3 = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MREFP0_PORT_HOT_PLUG_4 = 4 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MREFP0_PORT_HOT_PLUG_5 = 5 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MREFP0_PORT_HOT_PLUG_6 = 6 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MREFP0_PORT_HOT_PLUG_7 = 7 ;
+
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MREFP1_PORT_HOT_PLUG = 0 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MREFP1_PORT_HOT_PLUG_1 = 1 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MREFP1_PORT_HOT_PLUG_2 = 2 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MREFP1_PORT_HOT_PLUG_3 = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MREFP1_PORT_HOT_PLUG_4 = 4 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MREFP1_PORT_HOT_PLUG_5 = 5 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MREFP1_PORT_HOT_PLUG_6 = 6 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MREFP1_PORT_HOT_PLUG_7 = 7 ;
+
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MREFP1_PORT_HOT_PLUG = 0 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MREFP1_PORT_HOT_PLUG_1 = 1 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MREFP1_PORT_HOT_PLUG_2 = 2 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MREFP1_PORT_HOT_PLUG_3 = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MREFP1_PORT_HOT_PLUG_4 = 4 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MREFP1_PORT_HOT_PLUG_5 = 5 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MREFP1_PORT_HOT_PLUG_6 = 6 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MREFP1_PORT_HOT_PLUG_7 = 7 ;
+
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MRESB0_BRIDGE_GENERAL_RESET = 0 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MRESB0_BRIDGE_ERROR_RESET = 1 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MRESB0_SET_DMA_IRQ_SUSPEND_MODE = 5 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MRESB0_CLEAR_DMA_IRQ_SUSPEND_MODE = 6 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MRESB0_SET_DLY_MEASUREMENT = 7 ;
+
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MRESB0_BRIDGE_GENERAL_RESET = 0 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MRESB0_BRIDGE_ERROR_RESET = 1 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MRESB0_SET_DMA_IRQ_SUSPEND_MODE = 5 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MRESB0_CLEAR_DMA_IRQ_SUSPEND_MODE = 6 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MRESB0_SET_DLY_MEASUREMENT = 7 ;
+
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MRESP0_PORT_GENERAL_RESET = 0 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MRESP0_PORT_ERROR_RESET = 1 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MRESP0_ALL_BRIDGE_GENERAL_RESET = 2 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MRESP0_ALL_PORT_GENERAL_RESET = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MRESP0_CONTROL_REGISTER_RESET = 4 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MRESP0_PARITY_ERROR_RESET = 5 ;
+
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MRESP0_PORT_GENERAL_RESET = 0 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MRESP0_PORT_ERROR_RESET = 1 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MRESP0_ALL_BRIDGE_GENERAL_RESET = 2 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MRESP0_ALL_PORT_GENERAL_RESET = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MRESP0_CONTROL_REGISTER_RESET = 4 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MRESP0_PARITY_ERROR_RESET = 5 ;
+
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MRESP1_PORT_GENERAL_RESET_1 = 0 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MRESP1_PORT_ERROR_RESET_1 = 1 ;
+
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MRESP1_PORT_GENERAL_RESET_1 = 0 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MRESP1_PORT_ERROR_RESET_1 = 1 ;
+
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MRESP2_PORT_GENERAL_RESET_2 = 0 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MRESP2_PORT_ERROR_RESET_2 = 1 ;
+
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MRESP2_PORT_GENERAL_RESET_2 = 0 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MRESP2_PORT_ERROR_RESET_2 = 1 ;
+
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MRESP3_PORT_GENERAL_RESET_3 = 0 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MRESP3_PORT_ERROR_RESET_3 = 1 ;
+
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MRESP3_PORT_GENERAL_RESET_3 = 0 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MRESP3_PORT_ERROR_RESET_3 = 1 ;
+
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MRESP4_PORT_GENERAL_RESET_4 = 0 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MRESP4_PORT_ERROR_RESET_4 = 1 ;
+
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MRESP4_PORT_GENERAL_RESET_4 = 0 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MRESP4_PORT_ERROR_RESET_4 = 1 ;
+
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MRESP5_PORT_GENERAL_RESET_5 = 0 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MRESP5_PORT_ERROR_RESET_5 = 1 ;
+
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MRESP5_PORT_GENERAL_RESET_5 = 0 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MRESP5_PORT_ERROR_RESET_5 = 1 ;
+
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MRESP6_PORT_GENERAL_RESET_6 = 0 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MRESP6_PORT_ERROR_RESET_6 = 1 ;
+
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MRESP6_PORT_GENERAL_RESET_6 = 0 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MRESP6_PORT_ERROR_RESET_6 = 1 ;
+
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MRESP7_PORT_GENERAL_RESET_7 = 0 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MRESP7_PORT_ERROR_RESET_7 = 1 ;
+
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MRESP7_PORT_GENERAL_RESET_7 = 0 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MRESP7_PORT_ERROR_RESET_7 = 1 ;
+
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSENP0_SET_PORT_ENABLE = 0 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSENP0_SET_PORT_ENABLE_LEN = 8 ;
+
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSENP0_SET_PORT_ENABLE = 0 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSENP0_SET_PORT_ENABLE_LEN = 8 ;
+
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP0_PORT0_ERROR_CODE = 1 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP0_PORT0_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP0_PORT0_ERROR_CODE_1 = 5 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP0_PORT0_ERROR_CODE_1_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP0_PORT0_ERROR_CODE_2 = 9 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP0_PORT0_ERROR_CODE_2_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP0_FOURTH_ERROR = 13 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP0_FOURTH_ERROR_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP0_CRC_ERROR_COUNT = 16 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP0_CRC_ERROR_COUNT_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP0_HOT_PLUG_FLAG = 20 ;
+
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP0_PORT0_ERROR_CODE = 1 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP0_PORT0_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP0_PORT0_ERROR_CODE_1 = 5 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP0_PORT0_ERROR_CODE_1_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP0_PORT0_ERROR_CODE_2 = 9 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP0_PORT0_ERROR_CODE_2_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP0_FOURTH_ERROR = 13 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP0_FOURTH_ERROR_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP0_CRC_ERROR_COUNT = 16 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP0_CRC_ERROR_COUNT_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP0_HOT_PLUG_FLAG = 20 ;
+
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP1_PORT1_ERROR_CODE = 1 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP1_PORT1_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP1_PORT1_ERROR_CODE_1 = 5 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP1_PORT1_ERROR_CODE_1_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP1_PORT1_ERROR_CODE_2 = 9 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP1_PORT1_ERROR_CODE_2_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP1_FOURTH_ERROR = 13 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP1_FOURTH_ERROR_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP1_CRC_ERROR_COUNT = 16 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP1_CRC_ERROR_COUNT_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP1_HOT_PLUG_FLAG = 20 ;
+
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP1_PORT1_ERROR_CODE = 1 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP1_PORT1_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP1_PORT1_ERROR_CODE_1 = 5 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP1_PORT1_ERROR_CODE_1_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP1_PORT1_ERROR_CODE_2 = 9 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP1_PORT1_ERROR_CODE_2_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP1_FOURTH_ERROR = 13 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP1_FOURTH_ERROR_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP1_CRC_ERROR_COUNT = 16 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP1_CRC_ERROR_COUNT_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP1_HOT_PLUG_FLAG = 20 ;
+
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP2_PORT2_ERROR_CODE = 1 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP2_PORT2_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP2_PORT2_ERROR_CODE_1 = 5 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP2_PORT2_ERROR_CODE_1_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP2_PORT2_ERROR_CODE_2 = 9 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP2_PORT2_ERROR_CODE_2_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP2_FOURTH_ERROR = 13 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP2_FOURTH_ERROR_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP2_CRC_ERROR_COUNT = 16 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP2_CRC_ERROR_COUNT_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP2_HOT_PLUG_FLAG = 20 ;
+
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP2_PORT2_ERROR_CODE = 1 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP2_PORT2_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP2_PORT2_ERROR_CODE_1 = 5 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP2_PORT2_ERROR_CODE_1_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP2_PORT2_ERROR_CODE_2 = 9 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP2_PORT2_ERROR_CODE_2_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP2_FOURTH_ERROR = 13 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP2_FOURTH_ERROR_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP2_CRC_ERROR_COUNT = 16 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP2_CRC_ERROR_COUNT_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP2_HOT_PLUG_FLAG = 20 ;
+
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP3_PORT3_ERROR_CODE = 1 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP3_PORT3_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP3_PORT3_ERROR_CODE_1 = 5 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP3_PORT3_ERROR_CODE_1_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP3_PORT3_ERROR_CODE_2 = 9 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP3_PORT3_ERROR_CODE_2_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP3_FOURTH_ERROR = 13 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP3_FOURTH_ERROR_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP3_CRC_ERROR_COUNT = 16 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP3_CRC_ERROR_COUNT_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP3_HOT_PLUG_FLAG = 20 ;
+
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP3_PORT3_ERROR_CODE = 1 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP3_PORT3_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP3_PORT3_ERROR_CODE_1 = 5 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP3_PORT3_ERROR_CODE_1_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP3_PORT3_ERROR_CODE_2 = 9 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP3_PORT3_ERROR_CODE_2_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP3_FOURTH_ERROR = 13 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP3_FOURTH_ERROR_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP3_CRC_ERROR_COUNT = 16 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP3_CRC_ERROR_COUNT_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP3_HOT_PLUG_FLAG = 20 ;
+
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP4_PORT4_ERROR_CODE = 1 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP4_PORT4_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP4_PORT4_ERROR_CODE_1 = 5 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP4_PORT4_ERROR_CODE_1_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP4_PORT4_ERROR_CODE_2 = 9 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP4_PORT4_ERROR_CODE_2_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP4_FOURTH_ERROR = 13 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP4_FOURTH_ERROR_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP4_CRC_ERROR_COUNT = 16 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP4_CRC_ERROR_COUNT_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP4_HOT_PLUG_FLAG = 20 ;
+
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP4_PORT4_ERROR_CODE = 1 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP4_PORT4_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP4_PORT4_ERROR_CODE_1 = 5 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP4_PORT4_ERROR_CODE_1_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP4_PORT4_ERROR_CODE_2 = 9 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP4_PORT4_ERROR_CODE_2_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP4_FOURTH_ERROR = 13 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP4_FOURTH_ERROR_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP4_CRC_ERROR_COUNT = 16 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP4_CRC_ERROR_COUNT_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP4_HOT_PLUG_FLAG = 20 ;
+
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP5_PORT5_ERROR_CODE = 1 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP5_PORT5_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP5_PORT5_ERROR_CODE_1 = 5 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP5_PORT5_ERROR_CODE_1_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP5_PORT5_ERROR_CODE_2 = 9 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP5_PORT5_ERROR_CODE_2_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP5_FOURTH_ERROR = 13 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP5_FOURTH_ERROR_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP5_CRC_ERROR_COUNT = 16 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP5_CRC_ERROR_COUNT_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP5_HOT_PLUG_FLAG = 20 ;
+
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP5_PORT5_ERROR_CODE = 1 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP5_PORT5_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP5_PORT5_ERROR_CODE_1 = 5 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP5_PORT5_ERROR_CODE_1_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP5_PORT5_ERROR_CODE_2 = 9 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP5_PORT5_ERROR_CODE_2_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP5_FOURTH_ERROR = 13 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP5_FOURTH_ERROR_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP5_CRC_ERROR_COUNT = 16 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP5_CRC_ERROR_COUNT_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP5_HOT_PLUG_FLAG = 20 ;
+
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP6_PORT6_ERROR_CODE = 1 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP6_PORT6_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP6_PORT6_ERROR_CODE_1 = 5 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP6_PORT6_ERROR_CODE_1_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP6_PORT6_ERROR_CODE_2 = 9 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP6_PORT6_ERROR_CODE_2_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP6_FOURTH_ERROR = 13 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP6_FOURTH_ERROR_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP6_CRC_ERROR_COUNT = 16 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP6_CRC_ERROR_COUNT_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP6_HOT_PLUG_FLAG = 20 ;
+
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP6_PORT6_ERROR_CODE = 1 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP6_PORT6_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP6_PORT6_ERROR_CODE_1 = 5 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP6_PORT6_ERROR_CODE_1_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP6_PORT6_ERROR_CODE_2 = 9 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP6_PORT6_ERROR_CODE_2_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP6_FOURTH_ERROR = 13 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP6_FOURTH_ERROR_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP6_CRC_ERROR_COUNT = 16 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP6_CRC_ERROR_COUNT_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP6_HOT_PLUG_FLAG = 20 ;
+
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP7_PORT7_ERROR_CODE = 1 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP7_PORT7_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP7_PORT7_ERROR_CODE_1 = 5 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP7_PORT7_ERROR_CODE_1_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP7_PORT7_ERROR_CODE_2 = 9 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP7_PORT7_ERROR_CODE_2_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP7_FOURTH_ERROR = 13 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP7_FOURTH_ERROR_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP7_CRC_ERROR_COUNT = 16 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP7_CRC_ERROR_COUNT_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_0_MSTAP7_HOT_PLUG_FLAG = 20 ;
+
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP7_PORT7_ERROR_CODE = 1 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP7_PORT7_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP7_PORT7_ERROR_CODE_1 = 5 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP7_PORT7_ERROR_CODE_1_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP7_PORT7_ERROR_CODE_2 = 9 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP7_PORT7_ERROR_CODE_2_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP7_FOURTH_ERROR = 13 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP7_FOURTH_ERROR_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP7_CRC_ERROR_COUNT = 16 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP7_CRC_ERROR_COUNT_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_A_MST_0_MSTAP7_HOT_PLUG_FLAG = 20 ;
+
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MAEB_BRIDGE_ERROR = 0 ;
+
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MCENP0_CLR_PORT_ENABLE = 0 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MCENP0_CLR_PORT_ENABLE_LEN = 8 ;
+
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MENP0_PORT_0_ENABLE = 0 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MENP0_PORT_ENABLE = 1 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MENP0_PORT_2_ENABLE = 2 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MENP0_PORT_3_ENABLE = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MENP0_PORT_4_ENABLE = 4 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MENP0_PORT_5_ENABLE = 5 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MENP0_PORT_6_ENABLE = 6 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MENP0_PORT_7_ENABLE = 7 ;
+
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MESRB0_FIRST_ERROR = 0 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MESRB0_FIRST_ERROR_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MESRB0_CRC_ERROR_COUNT = 4 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MESRB0_CRC_ERROR_COUNT_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MESRB0_MMODE_PARITY_CHECK = 8 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MESRB0_MDLYR_PARITY_CHECK = 9 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MESRB0_MCRSP0_PARITY_CHECK = 10 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MESRB0_MENP0_PARITY_CHECK = 11 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MESRB0_MSIEP0_PARITY_CHECK = 12 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MESRB0_MSSIEP0_PARITY_CHECK = 13 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MESRB0_REGISTER_ACCESS_FSM_CHECK = 14 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MESRB0_OPB_BUS_ACCESS_FSM_CHECK = 15 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MESRB0_REGISTER_ACCESS_ERROR = 16 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MESRB0_FAILING_OPB_MASTER_FRST = 17 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MESRB0_FAILING_OPB_MASTER_FRST_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MESRB0_ACTUAL_ERROR = 20 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MESRB0_ACTUAL_ERROR_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MESRB0_SELECTED_ERROR = 24 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MESRB0_SELECTED_ERROR_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MESRB0_FAILING_OPB_MASTER_ACT = 29 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MESRB0_FAILING_OPB_MASTER_ACT_LEN = 3 ;
+
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MLEVP0_PORT_LEVEL_0 = 0 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MLEVP0_PORT_LEVEL = 1 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MLEVP0_PORT_LEVEL_2 = 2 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MLEVP0_PORT_LEVEL_3 = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MLEVP0_PORT_LEVEL_4 = 4 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MLEVP0_PORT_LEVEL_5 = 5 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MLEVP0_PORT_LEVEL_6 = 6 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MLEVP0_PORT_LEVEL_7 = 7 ;
+
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MLEVP1_PORT_LEVEL_0 = 0 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MLEVP1_PORT_LEVEL = 1 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MLEVP1_PORT_LEVEL_2 = 2 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MLEVP1_PORT_LEVEL_3 = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MLEVP1_PORT_LEVEL_4 = 4 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MLEVP1_PORT_LEVEL_5 = 5 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MLEVP1_PORT_LEVEL_6 = 6 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MLEVP1_PORT_LEVEL_7 = 7 ;
+
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MMODE_ENABLE_IPOLL_AND_DMA = 0 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MMODE_ENABLE_HW_ERROR_RECOVERY = 1 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MMODE_ENABLE_RELATIVE_ADDRESS_CMDS = 2 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MMODE_ENABLE_PARITY_CHECK = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MMODE_CLOCK_RATE_SELECTION_0 = 4 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MMODE_CLOCK_RATE_SELECTION_0_LEN = 10 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MMODE_CLOCK_RATE_SELECTION = 14 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MMODE_CLOCK_RATE_SELECTION_LEN = 10 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MMODE_CLOCK_DIV_4 = 25 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MMODE_TIMEOUT_SEL = 26 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MMODE_TIMEOUT_SEL_LEN = 2 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MMODE_RECEIVER_MODE = 29 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MMODE_RECEIVER_MODE_LEN = 3 ;
+
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MREFP0_PORT_HOT_PLUG_0 = 0 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MREFP0_PORT_HOT_PLUG = 1 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MREFP0_PORT_HOT_PLUG_2 = 2 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MREFP0_PORT_HOT_PLUG_3 = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MREFP0_PORT_HOT_PLUG_4 = 4 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MREFP0_PORT_HOT_PLUG_5 = 5 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MREFP0_PORT_HOT_PLUG_6 = 6 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MREFP0_PORT_HOT_PLUG_7 = 7 ;
+
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MREFP1_PORT_HOT_PLUG_0 = 0 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MREFP1_PORT_HOT_PLUG = 1 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MREFP1_PORT_HOT_PLUG_2 = 2 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MREFP1_PORT_HOT_PLUG_3 = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MREFP1_PORT_HOT_PLUG_4 = 4 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MREFP1_PORT_HOT_PLUG_5 = 5 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MREFP1_PORT_HOT_PLUG_6 = 6 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MREFP1_PORT_HOT_PLUG_7 = 7 ;
+
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MRESB0_BRIDGE_GENERAL_RESET = 0 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MRESB0_BRIDGE_ERROR_RESET = 1 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MRESB0_SET_DMA_IRQ_SUSPEND_MODE = 5 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MRESB0_CLEAR_DMA_IRQ_SUSPEND_MODE = 6 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MRESB0_SET_DLY_MEASUREMENT = 7 ;
+
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MRESP0_PORT_GENERAL_RESET = 0 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MRESP0_PORT_ERROR_RESET = 1 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MRESP0_ALL_BRIDGE_GENERAL_RESET = 2 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MRESP0_ALL_PORT_GENERAL_RESET = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MRESP0_CONTROL_REGISTER_RESET = 4 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MRESP0_PARITY_ERROR_RESET = 5 ;
+
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MRESP1_PORT_GENERAL_RESET = 0 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MRESP1_PORT_ERROR_RESET = 1 ;
+
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MRESP2_PORT_GENERAL_RESET_2 = 0 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MRESP2_PORT_ERROR_RESET_2 = 1 ;
+
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MRESP3_PORT_GENERAL_RESET_3 = 0 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MRESP3_PORT_ERROR_RESET_3 = 1 ;
+
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MRESP4_PORT_GENERAL_RESET_4 = 0 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MRESP4_PORT_ERROR_RESET_4 = 1 ;
+
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MRESP5_PORT_GENERAL_RESET_5 = 0 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MRESP5_PORT_ERROR_RESET_5 = 1 ;
+
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MRESP6_PORT_GENERAL_RESET_6 = 0 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MRESP6_PORT_ERROR_RESET_6 = 1 ;
+
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MRESP7_PORT_GENERAL_RESET_7 = 0 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MRESP7_PORT_ERROR_RESET_7 = 1 ;
+
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSENP0_SET_PORT_ENABLE = 0 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSENP0_SET_PORT_ENABLE_LEN = 8 ;
+
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP0_PORT0_ERROR_CODE_0 = 1 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP0_PORT0_ERROR_CODE_0_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP0_PORT0_ERROR_CODE = 5 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP0_PORT0_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP0_PORT0_ERROR_CODE_2 = 9 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP0_PORT0_ERROR_CODE_2_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP0_FOURTH_ERROR = 13 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP0_FOURTH_ERROR_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP0_CRC_ERROR_COUNT = 16 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP0_CRC_ERROR_COUNT_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP0_HOT_PLUG_FLAG = 20 ;
+
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP1_PORT1_ERROR_CODE_0 = 1 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP1_PORT1_ERROR_CODE_0_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP1_PORT1_ERROR_CODE = 5 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP1_PORT1_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP1_PORT1_ERROR_CODE_2 = 9 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP1_PORT1_ERROR_CODE_2_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP1_FOURTH_ERROR = 13 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP1_FOURTH_ERROR_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP1_CRC_ERROR_COUNT = 16 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP1_CRC_ERROR_COUNT_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP1_HOT_PLUG_FLAG = 20 ;
+
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP2_PORT2_ERROR_CODE_0 = 1 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP2_PORT2_ERROR_CODE_0_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP2_PORT2_ERROR_CODE = 5 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP2_PORT2_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP2_PORT2_ERROR_CODE_2 = 9 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP2_PORT2_ERROR_CODE_2_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP2_FOURTH_ERROR = 13 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP2_FOURTH_ERROR_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP2_CRC_ERROR_COUNT = 16 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP2_CRC_ERROR_COUNT_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP2_HOT_PLUG_FLAG = 20 ;
+
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP3_PORT3_ERROR_CODE_0 = 1 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP3_PORT3_ERROR_CODE_0_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP3_PORT3_ERROR_CODE = 5 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP3_PORT3_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP3_PORT3_ERROR_CODE_2 = 9 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP3_PORT3_ERROR_CODE_2_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP3_FOURTH_ERROR = 13 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP3_FOURTH_ERROR_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP3_CRC_ERROR_COUNT = 16 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP3_CRC_ERROR_COUNT_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP3_HOT_PLUG_FLAG = 20 ;
+
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP4_PORT4_ERROR_CODE_0 = 1 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP4_PORT4_ERROR_CODE_0_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP4_PORT4_ERROR_CODE = 5 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP4_PORT4_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP4_PORT4_ERROR_CODE_2 = 9 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP4_PORT4_ERROR_CODE_2_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP4_FOURTH_ERROR = 13 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP4_FOURTH_ERROR_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP4_CRC_ERROR_COUNT = 16 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP4_CRC_ERROR_COUNT_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP4_HOT_PLUG_FLAG = 20 ;
+
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP5_PORT5_ERROR_CODE_0 = 1 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP5_PORT5_ERROR_CODE_0_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP5_PORT5_ERROR_CODE = 5 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP5_PORT5_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP5_PORT5_ERROR_CODE_2 = 9 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP5_PORT5_ERROR_CODE_2_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP5_FOURTH_ERROR = 13 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP5_FOURTH_ERROR_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP5_CRC_ERROR_COUNT = 16 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP5_CRC_ERROR_COUNT_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP5_HOT_PLUG_FLAG = 20 ;
+
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP6_PORT6_ERROR_CODE_0 = 1 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP6_PORT6_ERROR_CODE_0_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP6_PORT6_ERROR_CODE = 5 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP6_PORT6_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP6_PORT6_ERROR_CODE_2 = 9 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP6_PORT6_ERROR_CODE_2_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP6_FOURTH_ERROR = 13 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP6_FOURTH_ERROR_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP6_CRC_ERROR_COUNT = 16 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP6_CRC_ERROR_COUNT_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP6_HOT_PLUG_FLAG = 20 ;
+
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP7_PORT7_ERROR_CODE_0 = 1 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP7_PORT7_ERROR_CODE_0_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP7_PORT7_ERROR_CODE = 5 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP7_PORT7_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP7_PORT7_ERROR_CODE_2 = 9 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP7_PORT7_ERROR_CODE_2_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP7_FOURTH_ERROR = 13 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP7_FOURTH_ERROR_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP7_CRC_ERROR_COUNT = 16 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP7_CRC_ERROR_COUNT_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSI_A_MST_1_MSTAP7_HOT_PLUG_FLAG = 20 ;
+
+static const uint8_t P9N2_PERV_FSI_A_SDMA_DMA_REQUEST_1_SELECT = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_SDMA_DMA_REQUEST_1_SELECT_LEN = 5 ;
+static const uint8_t P9N2_PERV_FSI_A_SDMA_DMA_REQUEST_2_SELECT = 11 ;
+static const uint8_t P9N2_PERV_FSI_A_SDMA_DMA_REQUEST_2_SELECT_LEN = 5 ;
+static const uint8_t P9N2_PERV_FSI_A_SDMA_CMFSI_PORT_ID_SELECT = 19 ;
+static const uint8_t P9N2_PERV_FSI_A_SDMA_CMFSI_PORT_ID_SELECT_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_SDMA_CMFSI_SLAVE_ID_SELECT = 22 ;
+static const uint8_t P9N2_PERV_FSI_A_SDMA_CMFSI_SLAVE_ID_SELECT_LEN = 2 ;
+static const uint8_t P9N2_PERV_FSI_A_SDMA_MFSI_PORT_ID_SELECT = 27 ;
+static const uint8_t P9N2_PERV_FSI_A_SDMA_MFSI_PORT_ID_SELECT_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_SDMA_MFSI_SLAVE_ID_SELECT = 30 ;
+static const uint8_t P9N2_PERV_FSI_A_SDMA_MFSI_SLAVE_ID_SELECT_LEN = 2 ;
+
+static const uint8_t P9N2_PERV_FSI_A_SLBUS_FORCE_LBUS_OWNERSHIP = 0 ;
+static const uint8_t P9N2_PERV_FSI_A_SLBUS_REQUEST_LBUS_OWNERSHIP = 1 ;
+static const uint8_t P9N2_PERV_FSI_A_SLBUS_RELEASE_LBUS_OWNERSHIP = 2 ;
+static const uint8_t P9N2_PERV_FSI_A_SLBUS_RELEASE_LBUS_OWNERSHIP_LEN = 2 ;
+static const uint8_t P9N2_PERV_FSI_A_SLBUS_RESET_LBUS_REQUEST = 4 ;
+static const uint8_t P9N2_PERV_FSI_A_SLBUS_LOCK_LBUS_ACCESS = 8 ;
+static const uint8_t P9N2_PERV_FSI_A_SLBUS_LOCK_LBUS_ACCESS_LEN = 8 ;
+
+static const uint8_t P9N2_PERV_FSI_A_SMODE_WARM_START_COMPLETED = 0 ;
+static const uint8_t P9N2_PERV_FSI_A_SMODE_ENABLE_AUX_PORT_UNUSED = 1 ;
+static const uint8_t P9N2_PERV_FSI_A_SMODE_ENABLE_HW_ERROR_RECOVERY = 2 ;
+static const uint8_t P9N2_PERV_FSI_A_SMODE_OWN_ID_THIS_SLAVE = 6 ;
+static const uint8_t P9N2_PERV_FSI_A_SMODE_OWN_ID_THIS_SLAVE_LEN = 2 ;
+static const uint8_t P9N2_PERV_FSI_A_SMODE_ECHO_DELAY_CYCLES = 8 ;
+static const uint8_t P9N2_PERV_FSI_A_SMODE_ECHO_DELAY_CYCLES_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSI_A_SMODE_SEND_DELAY_CYCLES = 12 ;
+static const uint8_t P9N2_PERV_FSI_A_SMODE_SEND_DELAY_CYCLES_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSI_A_SMODE_LBUS_CLOCK_DIVIDER = 20 ;
+static const uint8_t P9N2_PERV_FSI_A_SMODE_LBUS_CLOCK_DIVIDER_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSI_A_SMODE_BRIEFING_DATA_TO_SLAVE_SIDE_1 = 28 ;
+static const uint8_t P9N2_PERV_FSI_A_SMODE_BRIEFING_DATA_TO_SLAVE_SIDE_1_LEN = 4 ;
+
+static const uint8_t P9N2_PERV_FSI_A_SSTAT_ANY_SLV_ERROR = 0 ;
+static const uint8_t P9N2_PERV_FSI_A_SSTAT_ID_DIRTY = 1 ;
+static const uint8_t P9N2_PERV_FSI_A_SSTAT_WARM_START_SYNC_FR_LEFT = 2 ;
+static const uint8_t P9N2_PERV_FSI_A_SSTAT_WARM_START_SYNC_FR_RIGHT = 3 ;
+static const uint8_t P9N2_PERV_FSI_A_SSTAT_MAIL_DELIVERED_TO_LEFT = 4 ;
+static const uint8_t P9N2_PERV_FSI_A_SSTAT_MAIL_DELIVERED_TO_RIGHT = 5 ;
+static const uint8_t P9N2_PERV_FSI_A_SSTAT_MAIL_RECEIVED_FR_LEFT = 6 ;
+static const uint8_t P9N2_PERV_FSI_A_SSTAT_MAIL_RECEIVED_FR_RIGHT = 7 ;
+static const uint8_t P9N2_PERV_FSI_A_SSTAT_BRIEFING_DATA_SYNC_FR_LEFT = 8 ;
+static const uint8_t P9N2_PERV_FSI_A_SSTAT_BRIEFING_DATA_SYNC_FR_LEFT_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSI_A_SSTAT_BRIEFING_DATA_SYNC_FR_RIGHT = 12 ;
+static const uint8_t P9N2_PERV_FSI_A_SSTAT_BRIEFING_DATA_SYNC_FR_RIGHT_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSI_A_SSTAT_LBUS_REQ_SYNC_FR_LEFT = 16 ;
+static const uint8_t P9N2_PERV_FSI_A_SSTAT_LBUS_REQ_SYNC_FR_RIGHT = 17 ;
+static const uint8_t P9N2_PERV_FSI_A_SSTAT_THIS_LBUS_REQ = 18 ;
+static const uint8_t P9N2_PERV_FSI_A_SSTAT_LBUS_LOCK = 19 ;
+static const uint8_t P9N2_PERV_FSI_A_SSTAT_LBUS_GNT = 20 ;
+static const uint8_t P9N2_PERV_FSI_A_SSTAT_LBUS_GNT_LEN = 2 ;
+static const uint8_t P9N2_PERV_FSI_A_SSTAT_THIS_SIDE = 22 ;
+static const uint8_t P9N2_PERV_FSI_A_SSTAT_THIS_SIDE_LEN = 2 ;
+static const uint8_t P9N2_PERV_FSI_A_SSTAT_OWNERSHIP_FF1 = 24 ;
+static const uint8_t P9N2_PERV_FSI_A_SSTAT_OWNERSHIP_FF2 = 25 ;
+static const uint8_t P9N2_PERV_FSI_A_SSTAT_AUX_DI_LEVEL = 26 ;
+static const uint8_t P9N2_PERV_FSI_A_SSTAT_AUX_DI_REFERENCE = 27 ;
+static const uint8_t P9N2_PERV_FSI_A_SSTAT_CRC_ERR_CTR = 28 ;
+static const uint8_t P9N2_PERV_FSI_A_SSTAT_CRC_ERR_CTR_LEN = 4 ;
+
+static const uint8_t P9N2_PERV_FSI_B_LLMOD_EXTEND_TIMO = 29 ;
+static const uint8_t P9N2_PERV_FSI_B_LLMOD_DISABLE_GAP = 30 ;
+static const uint8_t P9N2_PERV_FSI_B_LLMOD_ASYNC_MODE = 31 ;
+
+static const uint8_t P9N2_PERV_FSI_B_LLSTAT_RESERVED_0 = 0 ;
+static const uint8_t P9N2_PERV_FSI_B_LLSTAT_RESERVED_0_LEN = 7 ;
+static const uint8_t P9N2_PERV_FSI_B_LLSTAT_NO_CLK = 7 ;
+static const uint8_t P9N2_PERV_FSI_B_LLSTAT_RESERVED_2 = 8 ;
+static const uint8_t P9N2_PERV_FSI_B_LLSTAT_RESERVED_2_LEN = 2 ;
+static const uint8_t P9N2_PERV_FSI_B_LLSTAT_BAD_HANDSHAKE_AT_START = 10 ;
+static const uint8_t P9N2_PERV_FSI_B_LLSTAT_TIMEOUT = 11 ;
+static const uint8_t P9N2_PERV_FSI_B_LLSTAT_LBUS_BUSY = 12 ;
+static const uint8_t P9N2_PERV_FSI_B_LLSTAT_OPB_BUSY = 13 ;
+static const uint8_t P9N2_PERV_FSI_B_LLSTAT_RESERVED_3 = 14 ;
+static const uint8_t P9N2_PERV_FSI_B_LLSTAT_BREAK_PENDING = 15 ;
+static const uint8_t P9N2_PERV_FSI_B_LLSTAT_RESERVED_4 = 16 ;
+static const uint8_t P9N2_PERV_FSI_B_LLSTAT_RESERVED_4_LEN = 2 ;
+static const uint8_t P9N2_PERV_FSI_B_LLSTAT_HANDSHAKE_STATE = 18 ;
+static const uint8_t P9N2_PERV_FSI_B_LLSTAT_HANDSHAKE_STATE_LEN = 2 ;
+static const uint8_t P9N2_PERV_FSI_B_LLSTAT_CFAM_CYCLE_TIME = 20 ;
+static const uint8_t P9N2_PERV_FSI_B_LLSTAT_CFAM_CYCLE_TIME_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSI_B_LLSTAT_REFCLOCK_STATUS = 24 ;
+static const uint8_t P9N2_PERV_FSI_B_LLSTAT_REFCLOCK_STATUS_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSI_B_LLSTAT_RESERVED_5 = 28 ;
+static const uint8_t P9N2_PERV_FSI_B_LLSTAT_RESERVED_5_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_B_LLSTAT_ASYNC_MODE = 31 ;
+
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MAEB_BRIDGE_ERROR = 0 ;
+
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MAEB_BRIDGE_ERROR = 0 ;
+
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MCENP0_CLR_PORT_ENABLE = 0 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MCENP0_CLR_PORT_ENABLE_LEN = 8 ;
+
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MCENP0_CLR_PORT_ENABLE = 0 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MCENP0_CLR_PORT_ENABLE_LEN = 8 ;
+
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MENP0_PORT_ENABLE = 0 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MENP0_PORT_1_ENABLE = 1 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MENP0_PORT_2_ENABLE = 2 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MENP0_PORT_3_ENABLE = 3 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MENP0_PORT_4_ENABLE = 4 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MENP0_PORT_5_ENABLE = 5 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MENP0_PORT_6_ENABLE = 6 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MENP0_PORT_7_ENABLE = 7 ;
+
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MENP0_PORT_ENABLE = 0 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MENP0_PORT_1_ENABLE = 1 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MENP0_PORT_2_ENABLE = 2 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MENP0_PORT_3_ENABLE = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MENP0_PORT_4_ENABLE = 4 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MENP0_PORT_5_ENABLE = 5 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MENP0_PORT_6_ENABLE = 6 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MENP0_PORT_7_ENABLE = 7 ;
+
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MESRB0_FIRST_ERROR = 0 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MESRB0_FIRST_ERROR_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MESRB0_CRC_ERROR_COUNT = 4 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MESRB0_CRC_ERROR_COUNT_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MESRB0_MMODE_PARITY_CHECK = 8 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MESRB0_MDLYR_PARITY_CHECK = 9 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MESRB0_MCRSP0_PARITY_CHECK = 10 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MESRB0_MENP0_PARITY_CHECK = 11 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MESRB0_MSIEP0_PARITY_CHECK = 12 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MESRB0_MSSIEP0_PARITY_CHECK = 13 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MESRB0_REGISTER_ACCESS_FSM_CHECK = 14 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MESRB0_OPB_BUS_ACCESS_FSM_CHECK = 15 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MESRB0_REGISTER_ACCESS_ERROR = 16 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MESRB0_FAILING_OPB_MASTER_FRST = 17 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MESRB0_FAILING_OPB_MASTER_FRST_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MESRB0_ACTUAL_ERROR = 20 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MESRB0_ACTUAL_ERROR_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MESRB0_SELECTED_ERROR = 24 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MESRB0_SELECTED_ERROR_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MESRB0_FAILING_OPB_MASTER_ACT = 29 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MESRB0_FAILING_OPB_MASTER_ACT_LEN = 3 ;
+
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MESRB0_FIRST_ERROR = 0 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MESRB0_FIRST_ERROR_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MESRB0_CRC_ERROR_COUNT = 4 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MESRB0_CRC_ERROR_COUNT_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MESRB0_MMODE_PARITY_CHECK = 8 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MESRB0_MDLYR_PARITY_CHECK = 9 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MESRB0_MCRSP0_PARITY_CHECK = 10 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MESRB0_MENP0_PARITY_CHECK = 11 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MESRB0_MSIEP0_PARITY_CHECK = 12 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MESRB0_MSSIEP0_PARITY_CHECK = 13 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MESRB0_REGISTER_ACCESS_FSM_CHECK = 14 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MESRB0_OPB_BUS_ACCESS_FSM_CHECK = 15 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MESRB0_REGISTER_ACCESS_ERROR = 16 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MESRB0_FAILING_OPB_MASTER_FRST = 17 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MESRB0_FAILING_OPB_MASTER_FRST_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MESRB0_ACTUAL_ERROR = 20 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MESRB0_ACTUAL_ERROR_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MESRB0_SELECTED_ERROR = 24 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MESRB0_SELECTED_ERROR_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MESRB0_FAILING_OPB_MASTER_ACT = 29 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MESRB0_FAILING_OPB_MASTER_ACT_LEN = 3 ;
+
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MLEVP0_PORT_LEVEL = 0 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MLEVP0_PORT_LEVEL_1 = 1 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MLEVP0_PORT_LEVEL_2 = 2 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MLEVP0_PORT_LEVEL_3 = 3 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MLEVP0_PORT_LEVEL_4 = 4 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MLEVP0_PORT_LEVEL_5 = 5 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MLEVP0_PORT_LEVEL_6 = 6 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MLEVP0_PORT_LEVEL_7 = 7 ;
+
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MLEVP0_PORT_LEVEL = 0 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MLEVP0_PORT_LEVEL_1 = 1 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MLEVP0_PORT_LEVEL_2 = 2 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MLEVP0_PORT_LEVEL_3 = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MLEVP0_PORT_LEVEL_4 = 4 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MLEVP0_PORT_LEVEL_5 = 5 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MLEVP0_PORT_LEVEL_6 = 6 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MLEVP0_PORT_LEVEL_7 = 7 ;
+
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MLEVP1_PORT_LEVEL = 0 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MLEVP1_PORT_LEVEL_1 = 1 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MLEVP1_PORT_LEVEL_2 = 2 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MLEVP1_PORT_LEVEL_3 = 3 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MLEVP1_PORT_LEVEL_4 = 4 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MLEVP1_PORT_LEVEL_5 = 5 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MLEVP1_PORT_LEVEL_6 = 6 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MLEVP1_PORT_LEVEL_7 = 7 ;
+
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MLEVP1_PORT_LEVEL = 0 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MLEVP1_PORT_LEVEL_1 = 1 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MLEVP1_PORT_LEVEL_2 = 2 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MLEVP1_PORT_LEVEL_3 = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MLEVP1_PORT_LEVEL_4 = 4 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MLEVP1_PORT_LEVEL_5 = 5 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MLEVP1_PORT_LEVEL_6 = 6 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MLEVP1_PORT_LEVEL_7 = 7 ;
+
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MMODE_ENABLE_IPOLL_AND_DMA = 0 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MMODE_ENABLE_HW_ERROR_RECOVERY = 1 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MMODE_ENABLE_RELATIVE_ADDRESS_CMDS = 2 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MMODE_ENABLE_PARITY_CHECK = 3 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MMODE_CLOCK_RATE_SELECTION = 4 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MMODE_CLOCK_RATE_SELECTION_LEN = 10 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MMODE_CLOCK_RATE_SELECTION_1 = 14 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MMODE_CLOCK_RATE_SELECTION_1_LEN = 10 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MMODE_CLOCK_DIV_4 = 25 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MMODE_TIMEOUT_SEL = 26 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MMODE_TIMEOUT_SEL_LEN = 2 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MMODE_RECEIVER_MODE = 29 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MMODE_RECEIVER_MODE_LEN = 3 ;
+
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MMODE_ENABLE_IPOLL_AND_DMA = 0 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MMODE_ENABLE_HW_ERROR_RECOVERY = 1 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MMODE_ENABLE_RELATIVE_ADDRESS_CMDS = 2 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MMODE_ENABLE_PARITY_CHECK = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MMODE_CLOCK_RATE_SELECTION = 4 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MMODE_CLOCK_RATE_SELECTION_LEN = 10 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MMODE_CLOCK_RATE_SELECTION_1 = 14 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MMODE_CLOCK_RATE_SELECTION_1_LEN = 10 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MMODE_CLOCK_DIV_4 = 25 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MMODE_TIMEOUT_SEL = 26 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MMODE_TIMEOUT_SEL_LEN = 2 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MMODE_RECEIVER_MODE = 29 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MMODE_RECEIVER_MODE_LEN = 3 ;
+
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MREFP0_PORT_HOT_PLUG = 0 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MREFP0_PORT_HOT_PLUG_1 = 1 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MREFP0_PORT_HOT_PLUG_2 = 2 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MREFP0_PORT_HOT_PLUG_3 = 3 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MREFP0_PORT_HOT_PLUG_4 = 4 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MREFP0_PORT_HOT_PLUG_5 = 5 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MREFP0_PORT_HOT_PLUG_6 = 6 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MREFP0_PORT_HOT_PLUG_7 = 7 ;
+
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MREFP0_PORT_HOT_PLUG = 0 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MREFP0_PORT_HOT_PLUG_1 = 1 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MREFP0_PORT_HOT_PLUG_2 = 2 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MREFP0_PORT_HOT_PLUG_3 = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MREFP0_PORT_HOT_PLUG_4 = 4 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MREFP0_PORT_HOT_PLUG_5 = 5 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MREFP0_PORT_HOT_PLUG_6 = 6 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MREFP0_PORT_HOT_PLUG_7 = 7 ;
+
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MREFP1_PORT_HOT_PLUG = 0 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MREFP1_PORT_HOT_PLUG_1 = 1 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MREFP1_PORT_HOT_PLUG_2 = 2 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MREFP1_PORT_HOT_PLUG_3 = 3 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MREFP1_PORT_HOT_PLUG_4 = 4 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MREFP1_PORT_HOT_PLUG_5 = 5 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MREFP1_PORT_HOT_PLUG_6 = 6 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MREFP1_PORT_HOT_PLUG_7 = 7 ;
+
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MREFP1_PORT_HOT_PLUG = 0 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MREFP1_PORT_HOT_PLUG_1 = 1 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MREFP1_PORT_HOT_PLUG_2 = 2 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MREFP1_PORT_HOT_PLUG_3 = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MREFP1_PORT_HOT_PLUG_4 = 4 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MREFP1_PORT_HOT_PLUG_5 = 5 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MREFP1_PORT_HOT_PLUG_6 = 6 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MREFP1_PORT_HOT_PLUG_7 = 7 ;
+
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MRESB0_BRIDGE_GENERAL_RESET = 0 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MRESB0_BRIDGE_ERROR_RESET = 1 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MRESB0_SET_DMA_IRQ_SUSPEND_MODE = 5 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MRESB0_CLEAR_DMA_IRQ_SUSPEND_MODE = 6 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MRESB0_SET_DLY_MEASUREMENT = 7 ;
+
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MRESB0_BRIDGE_GENERAL_RESET = 0 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MRESB0_BRIDGE_ERROR_RESET = 1 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MRESB0_SET_DMA_IRQ_SUSPEND_MODE = 5 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MRESB0_CLEAR_DMA_IRQ_SUSPEND_MODE = 6 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MRESB0_SET_DLY_MEASUREMENT = 7 ;
+
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MRESP0_PORT_GENERAL_RESET = 0 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MRESP0_PORT_ERROR_RESET = 1 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MRESP0_ALL_BRIDGE_GENERAL_RESET = 2 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MRESP0_ALL_PORT_GENERAL_RESET = 3 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MRESP0_CONTROL_REGISTER_RESET = 4 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MRESP0_PARITY_ERROR_RESET = 5 ;
+
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MRESP0_PORT_GENERAL_RESET = 0 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MRESP0_PORT_ERROR_RESET = 1 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MRESP0_ALL_BRIDGE_GENERAL_RESET = 2 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MRESP0_ALL_PORT_GENERAL_RESET = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MRESP0_CONTROL_REGISTER_RESET = 4 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MRESP0_PARITY_ERROR_RESET = 5 ;
+
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MRESP1_PORT_GENERAL_RESET_1 = 0 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MRESP1_PORT_ERROR_RESET_1 = 1 ;
+
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MRESP1_PORT_GENERAL_RESET_1 = 0 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MRESP1_PORT_ERROR_RESET_1 = 1 ;
+
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MRESP2_PORT_GENERAL_RESET_2 = 0 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MRESP2_PORT_ERROR_RESET_2 = 1 ;
+
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MRESP2_PORT_GENERAL_RESET_2 = 0 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MRESP2_PORT_ERROR_RESET_2 = 1 ;
+
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MRESP3_PORT_GENERAL_RESET_3 = 0 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MRESP3_PORT_ERROR_RESET_3 = 1 ;
+
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MRESP3_PORT_GENERAL_RESET_3 = 0 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MRESP3_PORT_ERROR_RESET_3 = 1 ;
+
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MRESP4_PORT_GENERAL_RESET_4 = 0 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MRESP4_PORT_ERROR_RESET_4 = 1 ;
+
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MRESP4_PORT_GENERAL_RESET_4 = 0 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MRESP4_PORT_ERROR_RESET_4 = 1 ;
+
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MRESP5_PORT_GENERAL_RESET_5 = 0 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MRESP5_PORT_ERROR_RESET_5 = 1 ;
+
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MRESP5_PORT_GENERAL_RESET_5 = 0 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MRESP5_PORT_ERROR_RESET_5 = 1 ;
+
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MRESP6_PORT_GENERAL_RESET_6 = 0 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MRESP6_PORT_ERROR_RESET_6 = 1 ;
+
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MRESP6_PORT_GENERAL_RESET_6 = 0 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MRESP6_PORT_ERROR_RESET_6 = 1 ;
+
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MRESP7_PORT_GENERAL_RESET_7 = 0 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MRESP7_PORT_ERROR_RESET_7 = 1 ;
+
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MRESP7_PORT_GENERAL_RESET_7 = 0 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MRESP7_PORT_ERROR_RESET_7 = 1 ;
+
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSENP0_SET_PORT_ENABLE = 0 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSENP0_SET_PORT_ENABLE_LEN = 8 ;
+
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSENP0_SET_PORT_ENABLE = 0 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSENP0_SET_PORT_ENABLE_LEN = 8 ;
+
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP0_PORT0_ERROR_CODE = 1 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP0_PORT0_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP0_PORT0_ERROR_CODE_1 = 5 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP0_PORT0_ERROR_CODE_1_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP0_PORT0_ERROR_CODE_2 = 9 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP0_PORT0_ERROR_CODE_2_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP0_FOURTH_ERROR = 13 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP0_FOURTH_ERROR_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP0_CRC_ERROR_COUNT = 16 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP0_CRC_ERROR_COUNT_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP0_HOT_PLUG_FLAG = 20 ;
+
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP0_PORT0_ERROR_CODE = 1 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP0_PORT0_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP0_PORT0_ERROR_CODE_1 = 5 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP0_PORT0_ERROR_CODE_1_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP0_PORT0_ERROR_CODE_2 = 9 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP0_PORT0_ERROR_CODE_2_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP0_FOURTH_ERROR = 13 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP0_FOURTH_ERROR_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP0_CRC_ERROR_COUNT = 16 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP0_CRC_ERROR_COUNT_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP0_HOT_PLUG_FLAG = 20 ;
+
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP1_PORT1_ERROR_CODE = 1 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP1_PORT1_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP1_PORT1_ERROR_CODE_1 = 5 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP1_PORT1_ERROR_CODE_1_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP1_PORT1_ERROR_CODE_2 = 9 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP1_PORT1_ERROR_CODE_2_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP1_FOURTH_ERROR = 13 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP1_FOURTH_ERROR_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP1_CRC_ERROR_COUNT = 16 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP1_CRC_ERROR_COUNT_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP1_HOT_PLUG_FLAG = 20 ;
+
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP1_PORT1_ERROR_CODE = 1 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP1_PORT1_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP1_PORT1_ERROR_CODE_1 = 5 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP1_PORT1_ERROR_CODE_1_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP1_PORT1_ERROR_CODE_2 = 9 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP1_PORT1_ERROR_CODE_2_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP1_FOURTH_ERROR = 13 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP1_FOURTH_ERROR_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP1_CRC_ERROR_COUNT = 16 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP1_CRC_ERROR_COUNT_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP1_HOT_PLUG_FLAG = 20 ;
+
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP2_PORT2_ERROR_CODE = 1 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP2_PORT2_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP2_PORT2_ERROR_CODE_1 = 5 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP2_PORT2_ERROR_CODE_1_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP2_PORT2_ERROR_CODE_2 = 9 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP2_PORT2_ERROR_CODE_2_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP2_FOURTH_ERROR = 13 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP2_FOURTH_ERROR_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP2_CRC_ERROR_COUNT = 16 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP2_CRC_ERROR_COUNT_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP2_HOT_PLUG_FLAG = 20 ;
+
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP2_PORT2_ERROR_CODE = 1 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP2_PORT2_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP2_PORT2_ERROR_CODE_1 = 5 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP2_PORT2_ERROR_CODE_1_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP2_PORT2_ERROR_CODE_2 = 9 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP2_PORT2_ERROR_CODE_2_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP2_FOURTH_ERROR = 13 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP2_FOURTH_ERROR_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP2_CRC_ERROR_COUNT = 16 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP2_CRC_ERROR_COUNT_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP2_HOT_PLUG_FLAG = 20 ;
+
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP3_PORT3_ERROR_CODE = 1 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP3_PORT3_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP3_PORT3_ERROR_CODE_1 = 5 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP3_PORT3_ERROR_CODE_1_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP3_PORT3_ERROR_CODE_2 = 9 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP3_PORT3_ERROR_CODE_2_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP3_FOURTH_ERROR = 13 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP3_FOURTH_ERROR_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP3_CRC_ERROR_COUNT = 16 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP3_CRC_ERROR_COUNT_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP3_HOT_PLUG_FLAG = 20 ;
+
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP3_PORT3_ERROR_CODE = 1 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP3_PORT3_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP3_PORT3_ERROR_CODE_1 = 5 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP3_PORT3_ERROR_CODE_1_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP3_PORT3_ERROR_CODE_2 = 9 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP3_PORT3_ERROR_CODE_2_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP3_FOURTH_ERROR = 13 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP3_FOURTH_ERROR_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP3_CRC_ERROR_COUNT = 16 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP3_CRC_ERROR_COUNT_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP3_HOT_PLUG_FLAG = 20 ;
+
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP4_PORT4_ERROR_CODE = 1 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP4_PORT4_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP4_PORT4_ERROR_CODE_1 = 5 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP4_PORT4_ERROR_CODE_1_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP4_PORT4_ERROR_CODE_2 = 9 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP4_PORT4_ERROR_CODE_2_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP4_FOURTH_ERROR = 13 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP4_FOURTH_ERROR_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP4_CRC_ERROR_COUNT = 16 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP4_CRC_ERROR_COUNT_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP4_HOT_PLUG_FLAG = 20 ;
+
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP4_PORT4_ERROR_CODE = 1 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP4_PORT4_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP4_PORT4_ERROR_CODE_1 = 5 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP4_PORT4_ERROR_CODE_1_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP4_PORT4_ERROR_CODE_2 = 9 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP4_PORT4_ERROR_CODE_2_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP4_FOURTH_ERROR = 13 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP4_FOURTH_ERROR_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP4_CRC_ERROR_COUNT = 16 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP4_CRC_ERROR_COUNT_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP4_HOT_PLUG_FLAG = 20 ;
+
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP5_PORT5_ERROR_CODE = 1 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP5_PORT5_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP5_PORT5_ERROR_CODE_1 = 5 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP5_PORT5_ERROR_CODE_1_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP5_PORT5_ERROR_CODE_2 = 9 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP5_PORT5_ERROR_CODE_2_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP5_FOURTH_ERROR = 13 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP5_FOURTH_ERROR_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP5_CRC_ERROR_COUNT = 16 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP5_CRC_ERROR_COUNT_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP5_HOT_PLUG_FLAG = 20 ;
+
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP5_PORT5_ERROR_CODE = 1 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP5_PORT5_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP5_PORT5_ERROR_CODE_1 = 5 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP5_PORT5_ERROR_CODE_1_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP5_PORT5_ERROR_CODE_2 = 9 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP5_PORT5_ERROR_CODE_2_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP5_FOURTH_ERROR = 13 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP5_FOURTH_ERROR_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP5_CRC_ERROR_COUNT = 16 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP5_CRC_ERROR_COUNT_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP5_HOT_PLUG_FLAG = 20 ;
+
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP6_PORT6_ERROR_CODE = 1 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP6_PORT6_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP6_PORT6_ERROR_CODE_1 = 5 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP6_PORT6_ERROR_CODE_1_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP6_PORT6_ERROR_CODE_2 = 9 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP6_PORT6_ERROR_CODE_2_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP6_FOURTH_ERROR = 13 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP6_FOURTH_ERROR_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP6_CRC_ERROR_COUNT = 16 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP6_CRC_ERROR_COUNT_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP6_HOT_PLUG_FLAG = 20 ;
+
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP6_PORT6_ERROR_CODE = 1 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP6_PORT6_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP6_PORT6_ERROR_CODE_1 = 5 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP6_PORT6_ERROR_CODE_1_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP6_PORT6_ERROR_CODE_2 = 9 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP6_PORT6_ERROR_CODE_2_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP6_FOURTH_ERROR = 13 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP6_FOURTH_ERROR_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP6_CRC_ERROR_COUNT = 16 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP6_CRC_ERROR_COUNT_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP6_HOT_PLUG_FLAG = 20 ;
+
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP7_PORT7_ERROR_CODE = 1 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP7_PORT7_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP7_PORT7_ERROR_CODE_1 = 5 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP7_PORT7_ERROR_CODE_1_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP7_PORT7_ERROR_CODE_2 = 9 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP7_PORT7_ERROR_CODE_2_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP7_FOURTH_ERROR = 13 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP7_FOURTH_ERROR_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP7_CRC_ERROR_COUNT = 16 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP7_CRC_ERROR_COUNT_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSI_B_MST_0_MSTAP7_HOT_PLUG_FLAG = 20 ;
+
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP7_PORT7_ERROR_CODE = 1 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP7_PORT7_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP7_PORT7_ERROR_CODE_1 = 5 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP7_PORT7_ERROR_CODE_1_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP7_PORT7_ERROR_CODE_2 = 9 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP7_PORT7_ERROR_CODE_2_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP7_FOURTH_ERROR = 13 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP7_FOURTH_ERROR_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP7_CRC_ERROR_COUNT = 16 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP7_CRC_ERROR_COUNT_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSISHIFT_FSI_B_MST_0_MSTAP7_HOT_PLUG_FLAG = 20 ;
+
+static const uint8_t P9N2_PERV_FSI_B_SDMA_DMA_REQUEST_1_SELECT = 3 ;
+static const uint8_t P9N2_PERV_FSI_B_SDMA_DMA_REQUEST_1_SELECT_LEN = 5 ;
+static const uint8_t P9N2_PERV_FSI_B_SDMA_DMA_REQUEST_2_SELECT = 11 ;
+static const uint8_t P9N2_PERV_FSI_B_SDMA_DMA_REQUEST_2_SELECT_LEN = 5 ;
+static const uint8_t P9N2_PERV_FSI_B_SDMA_CMFSI_PORT_ID_SELECT = 19 ;
+static const uint8_t P9N2_PERV_FSI_B_SDMA_CMFSI_PORT_ID_SELECT_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_B_SDMA_CMFSI_SLAVE_ID_SELECT = 22 ;
+static const uint8_t P9N2_PERV_FSI_B_SDMA_CMFSI_SLAVE_ID_SELECT_LEN = 2 ;
+static const uint8_t P9N2_PERV_FSI_B_SDMA_MFSI_PORT_ID_SELECT = 27 ;
+static const uint8_t P9N2_PERV_FSI_B_SDMA_MFSI_PORT_ID_SELECT_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI_B_SDMA_MFSI_SLAVE_ID_SELECT = 30 ;
+static const uint8_t P9N2_PERV_FSI_B_SDMA_MFSI_SLAVE_ID_SELECT_LEN = 2 ;
+
+static const uint8_t P9N2_PERV_FSI_B_SLBUS_FORCE_LBUS_OWNERSHIP = 0 ;
+static const uint8_t P9N2_PERV_FSI_B_SLBUS_REQUEST_LBUS_OWNERSHIP = 1 ;
+static const uint8_t P9N2_PERV_FSI_B_SLBUS_RELEASE_LBUS_OWNERSHIP = 2 ;
+static const uint8_t P9N2_PERV_FSI_B_SLBUS_RELEASE_LBUS_OWNERSHIP_LEN = 2 ;
+static const uint8_t P9N2_PERV_FSI_B_SLBUS_RESET_LBUS_REQUEST = 4 ;
+static const uint8_t P9N2_PERV_FSI_B_SLBUS_LOCK_LBUS_ACCESS = 8 ;
+static const uint8_t P9N2_PERV_FSI_B_SLBUS_LOCK_LBUS_ACCESS_LEN = 8 ;
+
+static const uint8_t P9N2_PERV_FSI_B_SMODE_WARM_START_COMPLETED = 0 ;
+static const uint8_t P9N2_PERV_FSI_B_SMODE_ENABLE_AUX_PORT_UNUSED = 1 ;
+static const uint8_t P9N2_PERV_FSI_B_SMODE_ENABLE_HW_ERROR_RECOVERY = 2 ;
+static const uint8_t P9N2_PERV_FSI_B_SMODE_OWN_ID_THIS_SLAVE = 6 ;
+static const uint8_t P9N2_PERV_FSI_B_SMODE_OWN_ID_THIS_SLAVE_LEN = 2 ;
+static const uint8_t P9N2_PERV_FSI_B_SMODE_ECHO_DELAY_CYCLES = 8 ;
+static const uint8_t P9N2_PERV_FSI_B_SMODE_ECHO_DELAY_CYCLES_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSI_B_SMODE_SEND_DELAY_CYCLES = 12 ;
+static const uint8_t P9N2_PERV_FSI_B_SMODE_SEND_DELAY_CYCLES_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSI_B_SMODE_LBUS_CLOCK_DIVIDER = 20 ;
+static const uint8_t P9N2_PERV_FSI_B_SMODE_LBUS_CLOCK_DIVIDER_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSI_B_SMODE_BRIEFING_DATA_TO_SLAVE_SIDE_0 = 24 ;
+static const uint8_t P9N2_PERV_FSI_B_SMODE_BRIEFING_DATA_TO_SLAVE_SIDE_0_LEN = 4 ;
+
+static const uint8_t P9N2_PERV_FSI_B_SSTAT_ANY_SLV_ERROR = 0 ;
+static const uint8_t P9N2_PERV_FSI_B_SSTAT_ID_DIRTY = 1 ;
+static const uint8_t P9N2_PERV_FSI_B_SSTAT_WARM_START_SYNC_FR_LEFT = 2 ;
+static const uint8_t P9N2_PERV_FSI_B_SSTAT_WARM_START_SYNC_FR_RIGHT = 3 ;
+static const uint8_t P9N2_PERV_FSI_B_SSTAT_MAIL_DELIVERED_TO_LEFT = 4 ;
+static const uint8_t P9N2_PERV_FSI_B_SSTAT_MAIL_DELIVERED_TO_RIGHT = 5 ;
+static const uint8_t P9N2_PERV_FSI_B_SSTAT_MAIL_RECEIVED_FR_LEFT = 6 ;
+static const uint8_t P9N2_PERV_FSI_B_SSTAT_MAIL_RECEIVED_FR_RIGHT = 7 ;
+static const uint8_t P9N2_PERV_FSI_B_SSTAT_BRIEFING_DATA_SYNC_FR_LEFT = 8 ;
+static const uint8_t P9N2_PERV_FSI_B_SSTAT_BRIEFING_DATA_SYNC_FR_LEFT_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSI_B_SSTAT_BRIEFING_DATA_SYNC_FR_RIGHT = 12 ;
+static const uint8_t P9N2_PERV_FSI_B_SSTAT_BRIEFING_DATA_SYNC_FR_RIGHT_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSI_B_SSTAT_LBUS_REQ_SYNC_FR_LEFT = 16 ;
+static const uint8_t P9N2_PERV_FSI_B_SSTAT_LBUS_REQ_SYNC_FR_RIGHT = 17 ;
+static const uint8_t P9N2_PERV_FSI_B_SSTAT_THIS_LBUS_REQ = 18 ;
+static const uint8_t P9N2_PERV_FSI_B_SSTAT_LBUS_LOCK = 19 ;
+static const uint8_t P9N2_PERV_FSI_B_SSTAT_LBUS_GNT = 20 ;
+static const uint8_t P9N2_PERV_FSI_B_SSTAT_LBUS_GNT_LEN = 2 ;
+static const uint8_t P9N2_PERV_FSI_B_SSTAT_THIS_SIDE = 22 ;
+static const uint8_t P9N2_PERV_FSI_B_SSTAT_THIS_SIDE_LEN = 2 ;
+static const uint8_t P9N2_PERV_FSI_B_SSTAT_OWNERSHIP_FF1 = 24 ;
+static const uint8_t P9N2_PERV_FSI_B_SSTAT_OWNERSHIP_FF2 = 25 ;
+static const uint8_t P9N2_PERV_FSI_B_SSTAT_AUX_DI_LEVEL = 26 ;
+static const uint8_t P9N2_PERV_FSI_B_SSTAT_AUX_DI_REFERENCE = 27 ;
+static const uint8_t P9N2_PERV_FSI_B_SSTAT_CRC_ERR_CTR = 28 ;
+static const uint8_t P9N2_PERV_FSI_B_SSTAT_CRC_ERR_CTR_LEN = 4 ;
+
+static const uint8_t P9N2_PERV_GPWRP_MAGIC_COOKIE = 0 ;
+static const uint8_t P9N2_PERV_GPWRP_MAGIC_COOKIE_LEN = 16 ;
+static const uint8_t P9N2_PERV_GPWRP_EN_OR_DIS_WRITE_PROTECTION = 16 ;
+static const uint8_t P9N2_PERV_GPWRP_EN_OR_DIS_WRITE_PROTECTION_LEN = 16 ;
+
+static const uint8_t P9N2_PERV_1_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN0 = 0 ;
+static const uint8_t P9N2_PERV_1_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN1 = 1 ;
+static const uint8_t P9N2_PERV_1_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN2 = 2 ;
+static const uint8_t P9N2_PERV_1_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN3 = 3 ;
+static const uint8_t P9N2_PERV_1_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN4 = 4 ;
+static const uint8_t P9N2_PERV_1_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN5 = 5 ;
+static const uint8_t P9N2_PERV_1_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN6 = 6 ;
+static const uint8_t P9N2_PERV_1_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN7 = 7 ;
+static const uint8_t P9N2_PERV_1_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN8 = 8 ;
+static const uint8_t P9N2_PERV_1_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN9 = 9 ;
+static const uint8_t P9N2_PERV_1_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN10 = 10 ;
+static const uint8_t P9N2_PERV_1_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN11 = 11 ;
+
+static const uint8_t P9N2_PERV_1_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN0 = 0 ;
+static const uint8_t P9N2_PERV_1_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN1 = 1 ;
+static const uint8_t P9N2_PERV_1_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN2 = 2 ;
+static const uint8_t P9N2_PERV_1_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN3 = 3 ;
+static const uint8_t P9N2_PERV_1_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN4 = 4 ;
+static const uint8_t P9N2_PERV_1_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN5 = 5 ;
+static const uint8_t P9N2_PERV_1_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN6 = 6 ;
+static const uint8_t P9N2_PERV_1_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN7 = 7 ;
+static const uint8_t P9N2_PERV_1_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN8 = 8 ;
+static const uint8_t P9N2_PERV_1_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN9 = 9 ;
+static const uint8_t P9N2_PERV_1_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN10 = 10 ;
+static const uint8_t P9N2_PERV_1_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN11 = 11 ;
+
+static const uint8_t P9N2_PERV_1_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN0 = 0 ;
+static const uint8_t P9N2_PERV_1_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN1 = 1 ;
+static const uint8_t P9N2_PERV_1_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN2 = 2 ;
+static const uint8_t P9N2_PERV_1_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN3 = 3 ;
+static const uint8_t P9N2_PERV_1_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN4 = 4 ;
+static const uint8_t P9N2_PERV_1_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN5 = 5 ;
+static const uint8_t P9N2_PERV_1_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN6 = 6 ;
+static const uint8_t P9N2_PERV_1_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN7 = 7 ;
+static const uint8_t P9N2_PERV_1_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN8 = 8 ;
+static const uint8_t P9N2_PERV_1_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN9 = 9 ;
+static const uint8_t P9N2_PERV_1_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN10 = 10 ;
+static const uint8_t P9N2_PERV_1_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN11 = 11 ;
+
+static const uint8_t P9N2_PERV_1_GXSTOP_TRIG_REG_GXSTP_IN0 = 0 ;
+static const uint8_t P9N2_PERV_1_GXSTOP_TRIG_REG_GXSTP_IN1 = 1 ;
+static const uint8_t P9N2_PERV_1_GXSTOP_TRIG_REG_GXSTP_IN2 = 2 ;
+static const uint8_t P9N2_PERV_1_GXSTOP_TRIG_REG_GXSTP_IN3 = 3 ;
+static const uint8_t P9N2_PERV_1_GXSTOP_TRIG_REG_GXSTP_IN4 = 4 ;
+static const uint8_t P9N2_PERV_1_GXSTOP_TRIG_REG_GXSTP_IN5 = 5 ;
+static const uint8_t P9N2_PERV_1_GXSTOP_TRIG_REG_GXSTP_IN6 = 6 ;
+static const uint8_t P9N2_PERV_1_GXSTOP_TRIG_REG_GXSTP_IN7 = 7 ;
+static const uint8_t P9N2_PERV_1_GXSTOP_TRIG_REG_GXSTP_IN8 = 8 ;
+static const uint8_t P9N2_PERV_1_GXSTOP_TRIG_REG_GXSTP_IN9 = 9 ;
+static const uint8_t P9N2_PERV_1_GXSTOP_TRIG_REG_GXSTP_IN10 = 10 ;
+static const uint8_t P9N2_PERV_1_GXSTOP_TRIG_REG_GXSTP_IN11 = 11 ;
+
+static const uint8_t P9N2_PERV_1_HANG_PULSE_0_REG_0 = 0 ;
+static const uint8_t P9N2_PERV_1_HANG_PULSE_0_REG_0_LEN = 6 ;
+static const uint8_t P9N2_PERV_1_HANG_PULSE_0_REG_SUPPRESS = 6 ;
+
+static const uint8_t P9N2_PERV_1_HANG_PULSE_1_REG_1 = 0 ;
+static const uint8_t P9N2_PERV_1_HANG_PULSE_1_REG_1_LEN = 6 ;
+static const uint8_t P9N2_PERV_1_HANG_PULSE_1_REG_SUPPRESS = 6 ;
+
+static const uint8_t P9N2_PERV_1_HANG_PULSE_2_REG_2 = 0 ;
+static const uint8_t P9N2_PERV_1_HANG_PULSE_2_REG_2_LEN = 6 ;
+static const uint8_t P9N2_PERV_1_HANG_PULSE_2_REG_SUPPRESS = 6 ;
+
+static const uint8_t P9N2_PERV_1_HANG_PULSE_3_REG_3 = 0 ;
+static const uint8_t P9N2_PERV_1_HANG_PULSE_3_REG_3_LEN = 6 ;
+static const uint8_t P9N2_PERV_1_HANG_PULSE_3_REG_SUPPRESS = 6 ;
+
+static const uint8_t P9N2_PERV_1_HANG_PULSE_4_REG_4 = 0 ;
+static const uint8_t P9N2_PERV_1_HANG_PULSE_4_REG_4_LEN = 6 ;
+static const uint8_t P9N2_PERV_1_HANG_PULSE_4_REG_SUPPRESS = 6 ;
+
+static const uint8_t P9N2_PERV_1_HANG_PULSE_5_REG_5 = 0 ;
+static const uint8_t P9N2_PERV_1_HANG_PULSE_5_REG_5_LEN = 6 ;
+static const uint8_t P9N2_PERV_1_HANG_PULSE_5_REG_SUPPRESS = 6 ;
+
+static const uint8_t P9N2_PERV_1_HANG_PULSE_6_REG_6 = 0 ;
+static const uint8_t P9N2_PERV_1_HANG_PULSE_6_REG_6_LEN = 6 ;
+static const uint8_t P9N2_PERV_1_HANG_PULSE_6_REG_SUPPRESS = 6 ;
+
+static const uint8_t P9N2_PERV_1_HEARTBEAT_REG_DEAD = 0 ;
+
+static const uint8_t P9N2_PERV_1_HOSTATTN_IN0 = 0 ;
+static const uint8_t P9N2_PERV_1_HOSTATTN_IN1 = 1 ;
+static const uint8_t P9N2_PERV_1_HOSTATTN_IN2 = 2 ;
+static const uint8_t P9N2_PERV_1_HOSTATTN_IN3 = 3 ;
+static const uint8_t P9N2_PERV_1_HOSTATTN_IN4 = 4 ;
+static const uint8_t P9N2_PERV_1_HOSTATTN_IN5 = 5 ;
+static const uint8_t P9N2_PERV_1_HOSTATTN_IN6 = 6 ;
+static const uint8_t P9N2_PERV_1_HOSTATTN_IN7 = 7 ;
+static const uint8_t P9N2_PERV_1_HOSTATTN_IN8 = 8 ;
+static const uint8_t P9N2_PERV_1_HOSTATTN_IN9 = 9 ;
+static const uint8_t P9N2_PERV_1_HOSTATTN_IN10 = 10 ;
+static const uint8_t P9N2_PERV_1_HOSTATTN_IN11 = 11 ;
+static const uint8_t P9N2_PERV_1_HOSTATTN_IN12 = 12 ;
+static const uint8_t P9N2_PERV_1_HOSTATTN_IN13 = 13 ;
+static const uint8_t P9N2_PERV_1_HOSTATTN_IN14 = 14 ;
+static const uint8_t P9N2_PERV_1_HOSTATTN_IN15 = 15 ;
+static const uint8_t P9N2_PERV_1_HOSTATTN_IN16 = 16 ;
+static const uint8_t P9N2_PERV_1_HOSTATTN_IN17 = 17 ;
+static const uint8_t P9N2_PERV_1_HOSTATTN_IN18 = 18 ;
+static const uint8_t P9N2_PERV_1_HOSTATTN_IN19 = 19 ;
+static const uint8_t P9N2_PERV_1_HOSTATTN_IN20 = 20 ;
+static const uint8_t P9N2_PERV_1_HOSTATTN_IN21 = 21 ;
+static const uint8_t P9N2_PERV_1_HOSTATTN_IN22 = 22 ;
+
+static const uint8_t P9N2_PERV_1_HOSTATTN_MASK_IN = 0 ;
+static const uint8_t P9N2_PERV_1_HOSTATTN_MASK_IN_LEN = 22 ;
+
+static const uint8_t P9N2_PERV_HOST_MASK_REG_IPOLL_0 = 0 ;
+static const uint8_t P9N2_PERV_HOST_MASK_REG_IPOLL_1 = 1 ;
+static const uint8_t P9N2_PERV_HOST_MASK_REG_IPOLL_2 = 2 ;
+static const uint8_t P9N2_PERV_HOST_MASK_REG_IPOLL_3 = 3 ;
+static const uint8_t P9N2_PERV_HOST_MASK_REG_IPOLL_4 = 4 ;
+static const uint8_t P9N2_PERV_HOST_MASK_REG_IPOLL_5 = 5 ;
+static const uint8_t P9N2_PERV_HOST_MASK_REG_ERROR_0 = 6 ;
+static const uint8_t P9N2_PERV_HOST_MASK_REG_ERROR_1 = 7 ;
+static const uint8_t P9N2_PERV_HOST_MASK_REG_ERROR_2 = 8 ;
+static const uint8_t P9N2_PERV_HOST_MASK_REG_ERROR_3 = 9 ;
+static const uint8_t P9N2_PERV_HOST_MASK_REG_ERROR_4 = 10 ;
+static const uint8_t P9N2_PERV_HOST_MASK_REG_ERROR_5 = 11 ;
+
+static const uint8_t P9N2_PERV_IGNORE_PAR_REG_PARITY = 0 ;
+static const uint8_t P9N2_PERV_IGNORE_PAR_REG_DISABLE_ECC_CORRECTION = 1 ;
+static const uint8_t P9N2_PERV_IGNORE_PAR_REG_ECC_S_BIT_ERROR = 2 ;
+static const uint8_t P9N2_PERV_IGNORE_PAR_REG_CHKSW_AR012 = 3 ;
+
+static const uint8_t P9N2_PERV_1_INJECT_REG_THERM_TRIP = 0 ;
+static const uint8_t P9N2_PERV_1_INJECT_REG_THERM_TRIP_LEN = 2 ;
+static const uint8_t P9N2_PERV_1_INJECT_REG_THERM_MODE = 2 ;
+static const uint8_t P9N2_PERV_1_INJECT_REG_THERM_MODE_LEN = 2 ;
+
+static const uint8_t P9N2_PERV_FSI2PIB_INTERRUPT_STATUS_REG = 0 ;
+static const uint8_t P9N2_PERV_FSI2PIB_INTERRUPT_STATUS_REG_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_INTERRUPT1_REG_INTERRUPT1 = 0 ;
+static const uint8_t P9N2_PERV_INTERRUPT1_REG_INTERRUPT1_LEN = 56 ;
+
+static const uint8_t P9N2_PERV_INTERRUPT2_REG_INTERRUPT2 = 0 ;
+static const uint8_t P9N2_PERV_INTERRUPT2_REG_INTERRUPT2_LEN = 56 ;
+
+static const uint8_t P9N2_PERV_INTERRUPT3_REG_INTERRUPT3 = 0 ;
+static const uint8_t P9N2_PERV_INTERRUPT3_REG_INTERRUPT3_LEN = 56 ;
+
+static const uint8_t P9N2_PERV_INTERRUPT4_REG_INTERRUPT4 = 0 ;
+static const uint8_t P9N2_PERV_INTERRUPT4_REG_INTERRUPT4_LEN = 56 ;
+
+static const uint8_t P9N2_PERV_FSII2C_INTERRUPT_COND_A_INVALID_CMD_0 = 16 ;
+static const uint8_t P9N2_PERV_FSII2C_INTERRUPT_COND_A_LBUS_PARITY_ERROR_0 = 17 ;
+static const uint8_t P9N2_PERV_FSII2C_INTERRUPT_COND_A_BE_OV_ERROR_0 = 18 ;
+static const uint8_t P9N2_PERV_FSII2C_INTERRUPT_COND_A_BE_ACC_ERROR_0 = 19 ;
+static const uint8_t P9N2_PERV_FSII2C_INTERRUPT_COND_A_ARBITRATION_LOST_ERROR_0 = 20 ;
+static const uint8_t P9N2_PERV_FSII2C_INTERRUPT_COND_A_NACK_RECEIVED_ERROR_0 = 21 ;
+static const uint8_t P9N2_PERV_FSII2C_INTERRUPT_COND_A_DATA_REQUEST_0 = 22 ;
+static const uint8_t P9N2_PERV_FSII2C_INTERRUPT_COND_A_STOP_ERROR_0 = 24 ;
+
+static const uint8_t P9N2_PERV_INTERRUPT_CONF_REG_UNUSED0 = 0 ;
+static const uint8_t P9N2_PERV_INTERRUPT_CONF_REG_SEL0 = 1 ;
+static const uint8_t P9N2_PERV_INTERRUPT_CONF_REG_SEL0_LEN = 3 ;
+static const uint8_t P9N2_PERV_INTERRUPT_CONF_REG_UNUSED4 = 4 ;
+static const uint8_t P9N2_PERV_INTERRUPT_CONF_REG_SEL1 = 5 ;
+static const uint8_t P9N2_PERV_INTERRUPT_CONF_REG_SEL1_LEN = 3 ;
+static const uint8_t P9N2_PERV_INTERRUPT_CONF_REG_GP = 8 ;
+static const uint8_t P9N2_PERV_INTERRUPT_CONF_REG_CC = 9 ;
+static const uint8_t P9N2_PERV_INTERRUPT_CONF_REG_UNUSED2 = 10 ;
+static const uint8_t P9N2_PERV_INTERRUPT_CONF_REG_UNUSED3 = 11 ;
+
+static const uint8_t P9N2_PERV_INTERRUPT_HOLD_REG_HOLD = 0 ;
+static const uint8_t P9N2_PERV_INTERRUPT_HOLD_REG_HOLD_LEN = 26 ;
+
+static const uint8_t P9N2_PERV_FSII2C_INTERRUPT_MASK_REGISTER_A_INT_0 = 16 ;
+static const uint8_t P9N2_PERV_FSII2C_INTERRUPT_MASK_REGISTER_A_INT_0_LEN = 16 ;
+
+static const uint8_t P9N2_PERV_FSII2C_INTERRUPT_MASK_REGISTER_READ_A_INT_0 = 16 ;
+static const uint8_t P9N2_PERV_FSII2C_INTERRUPT_MASK_REGISTER_READ_A_INT_0_LEN = 16 ;
+
+static const uint8_t P9N2_PERV_INTERRUPT_TYPE_MASK_REG_GP = 0 ;
+static const uint8_t P9N2_PERV_INTERRUPT_TYPE_MASK_REG_CC = 1 ;
+static const uint8_t P9N2_PERV_INTERRUPT_TYPE_MASK_REG_UNUSED2 = 2 ;
+static const uint8_t P9N2_PERV_INTERRUPT_TYPE_MASK_REG_UNUSED3 = 3 ;
+
+static const uint8_t P9N2_PERV_INTERRUPT_TYPE_REG_ATTENTION = 0 ;
+static const uint8_t P9N2_PERV_INTERRUPT_TYPE_REG_RECOVERABLE_ERROR = 1 ;
+static const uint8_t P9N2_PERV_INTERRUPT_TYPE_REG_CHECKSTOP = 2 ;
+
+static const uint8_t P9N2_PERV_IODA_TCD_IDIAL_VLD = 0 ;
+static const uint8_t P9N2_PERV_IODA_TCD_IDIAL_RSVD0 = 1 ;
+static const uint8_t P9N2_PERV_IODA_TCD_IDIAL_RSVD0_LEN = 5 ;
+static const uint8_t P9N2_PERV_IODA_TCD_IDIAL_PC = 6 ;
+static const uint8_t P9N2_PERV_IODA_TCD_IDIAL_PC_LEN = 2 ;
+static const uint8_t P9N2_PERV_IODA_TCD_IDIAL_PE = 8 ;
+static const uint8_t P9N2_PERV_IODA_TCD_IDIAL_PE_LEN = 4 ;
+static const uint8_t P9N2_PERV_IODA_TCD_IDIAL_EA = 12 ;
+static const uint8_t P9N2_PERV_IODA_TCD_IDIAL_EA_LEN = 37 ;
+static const uint8_t P9N2_PERV_IODA_TCD_IDIAL_RSVD1 = 49 ;
+static const uint8_t P9N2_PERV_IODA_TCD_IDIAL_RSVD1_LEN = 15 ;
+
+static const uint8_t P9N2_PERV_IODA_TDR_IDIAL_RA = 0 ;
+static const uint8_t P9N2_PERV_IODA_TDR_IDIAL_RA_LEN = 39 ;
+static const uint8_t P9N2_PERV_IODA_TDR_IDIAL_RSVD0 = 39 ;
+static const uint8_t P9N2_PERV_IODA_TDR_IDIAL_RSVD0_LEN = 2 ;
+static const uint8_t P9N2_PERV_IODA_TDR_IDIAL_PAR = 41 ;
+static const uint8_t P9N2_PERV_IODA_TDR_IDIAL_PAR_LEN = 5 ;
+
+static const uint8_t P9N2_PERV_IODA_TDR_MEM_IDIAL_RSVD0 = 0 ;
+static const uint8_t P9N2_PERV_IODA_TDR_MEM_IDIAL_RSVD0_LEN = 13 ;
+static const uint8_t P9N2_PERV_IODA_TDR_MEM_IDIAL_RA = 13 ;
+static const uint8_t P9N2_PERV_IODA_TDR_MEM_IDIAL_RA_LEN = 39 ;
+static const uint8_t P9N2_PERV_IODA_TDR_MEM_IDIAL_RSVD1 = 52 ;
+static const uint8_t P9N2_PERV_IODA_TDR_MEM_IDIAL_RSVD1_LEN = 10 ;
+static const uint8_t P9N2_PERV_IODA_TDR_MEM_IDIAL_PC = 62 ;
+static const uint8_t P9N2_PERV_IODA_TDR_MEM_IDIAL_PC_LEN = 2 ;
+
+static const uint8_t P9N2_PERV_FSB_IODA_TVT_TVT0_XLAT_ADDR = 0 ;
+static const uint8_t P9N2_PERV_FSB_IODA_TVT_TVT0_XLAT_ADDR_LEN = 48 ;
+static const uint8_t P9N2_PERV_FSB_IODA_TVT_TVT0_TABLE_LEVEL = 48 ;
+static const uint8_t P9N2_PERV_FSB_IODA_TVT_TVT0_TABLE_LEVEL_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSB_IODA_TVT_TVT0_TABLE_SIZE = 51 ;
+static const uint8_t P9N2_PERV_FSB_IODA_TVT_TVT0_TABLE_SIZE_LEN = 5 ;
+static const uint8_t P9N2_PERV_FSB_IODA_TVT_TVT0_SPARE = 56 ;
+static const uint8_t P9N2_PERV_FSB_IODA_TVT_TVT0_SPARE_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSB_IODA_TVT_TVT0_PAGE_SIZE = 59 ;
+static const uint8_t P9N2_PERV_FSB_IODA_TVT_TVT0_PAGE_SIZE_LEN = 5 ;
+
+static const uint8_t P9N2_PERV_IODA_XLT_EA_IDIAL_EA = 0 ;
+static const uint8_t P9N2_PERV_IODA_XLT_EA_IDIAL_EA_LEN = 37 ;
+static const uint8_t P9N2_PERV_IODA_XLT_EA_IDIAL_PE = 37 ;
+static const uint8_t P9N2_PERV_IODA_XLT_EA_IDIAL_PE_LEN = 4 ;
+static const uint8_t P9N2_PERV_IODA_XLT_EA_IDIAL_RNW = 41 ;
+static const uint8_t P9N2_PERV_IODA_XLT_EA_IDIAL_TAG = 42 ;
+static const uint8_t P9N2_PERV_IODA_XLT_EA_IDIAL_TAG_LEN = 8 ;
+static const uint8_t P9N2_PERV_IODA_XLT_EA_IDIAL_RSVD0 = 50 ;
+static const uint8_t P9N2_PERV_IODA_XLT_EA_IDIAL_RSVD0_LEN = 14 ;
+
+static const uint8_t P9N2_PERV_1_KVREF_AND_VMEAS_MODE_STATUS_REG_START_CAL = 0 ;
+static const uint8_t P9N2_PERV_1_KVREF_AND_VMEAS_MODE_STATUS_REG_DATA_SEL = 1 ;
+static const uint8_t P9N2_PERV_1_KVREF_AND_VMEAS_MODE_STATUS_REG_BYPASS = 2 ;
+static const uint8_t P9N2_PERV_1_KVREF_AND_VMEAS_MODE_STATUS_REG_MEASURE = 8 ;
+static const uint8_t P9N2_PERV_1_KVREF_AND_VMEAS_MODE_STATUS_REG_MAX = 9 ;
+static const uint8_t P9N2_PERV_1_KVREF_AND_VMEAS_MODE_STATUS_REG_MIN = 10 ;
+static const uint8_t P9N2_PERV_1_KVREF_AND_VMEAS_MODE_STATUS_REG_CAL_DONE = 16 ;
+static const uint8_t P9N2_PERV_1_KVREF_AND_VMEAS_MODE_STATUS_REG_TIMEOUT = 18 ;
+static const uint8_t P9N2_PERV_1_KVREF_AND_VMEAS_MODE_STATUS_REG_RESULT_VALID = 19 ;
+
+static const uint8_t P9N2_PERV_1_KVREF_TUNE_DATA_FMU_KVREF_TUNE_DATA = 0 ;
+static const uint8_t P9N2_PERV_1_KVREF_TUNE_DATA_FMU_KVREF_TUNE_DATA_LEN = 12 ;
+
+static const uint8_t P9N2_PERV_1_LOCAL_FIR_IN0 = 0 ;
+static const uint8_t P9N2_PERV_1_LOCAL_FIR_IN1 = 1 ;
+static const uint8_t P9N2_PERV_1_LOCAL_FIR_IN2 = 2 ;
+static const uint8_t P9N2_PERV_1_LOCAL_FIR_IN3 = 3 ;
+static const uint8_t P9N2_PERV_1_LOCAL_FIR_IN4 = 4 ;
+static const uint8_t P9N2_PERV_1_LOCAL_FIR_IN5 = 5 ;
+static const uint8_t P9N2_PERV_1_LOCAL_FIR_IN6 = 6 ;
+static const uint8_t P9N2_PERV_1_LOCAL_FIR_IN7 = 7 ;
+static const uint8_t P9N2_PERV_1_LOCAL_FIR_IN8 = 8 ;
+static const uint8_t P9N2_PERV_1_LOCAL_FIR_IN9 = 9 ;
+static const uint8_t P9N2_PERV_1_LOCAL_FIR_IN10 = 10 ;
+static const uint8_t P9N2_PERV_1_LOCAL_FIR_IN11 = 11 ;
+static const uint8_t P9N2_PERV_1_LOCAL_FIR_IN12 = 12 ;
+static const uint8_t P9N2_PERV_1_LOCAL_FIR_IN13 = 13 ;
+static const uint8_t P9N2_PERV_1_LOCAL_FIR_IN14 = 14 ;
+static const uint8_t P9N2_PERV_1_LOCAL_FIR_IN15 = 15 ;
+static const uint8_t P9N2_PERV_1_LOCAL_FIR_IN16 = 16 ;
+static const uint8_t P9N2_PERV_1_LOCAL_FIR_IN17 = 17 ;
+static const uint8_t P9N2_PERV_1_LOCAL_FIR_IN18 = 18 ;
+static const uint8_t P9N2_PERV_1_LOCAL_FIR_IN19 = 19 ;
+static const uint8_t P9N2_PERV_1_LOCAL_FIR_IN20 = 20 ;
+static const uint8_t P9N2_PERV_1_LOCAL_FIR_IN21 = 21 ;
+static const uint8_t P9N2_PERV_1_LOCAL_FIR_IN22 = 22 ;
+static const uint8_t P9N2_PERV_1_LOCAL_FIR_IN23 = 23 ;
+static const uint8_t P9N2_PERV_1_LOCAL_FIR_IN24 = 24 ;
+static const uint8_t P9N2_PERV_1_LOCAL_FIR_IN25 = 25 ;
+static const uint8_t P9N2_PERV_1_LOCAL_FIR_IN26 = 26 ;
+static const uint8_t P9N2_PERV_1_LOCAL_FIR_IN27 = 27 ;
+static const uint8_t P9N2_PERV_1_LOCAL_FIR_IN28 = 28 ;
+static const uint8_t P9N2_PERV_1_LOCAL_FIR_IN29 = 29 ;
+static const uint8_t P9N2_PERV_1_LOCAL_FIR_IN30 = 30 ;
+static const uint8_t P9N2_PERV_1_LOCAL_FIR_IN31 = 31 ;
+static const uint8_t P9N2_PERV_1_LOCAL_FIR_IN32 = 32 ;
+static const uint8_t P9N2_PERV_1_LOCAL_FIR_IN33 = 33 ;
+static const uint8_t P9N2_PERV_1_LOCAL_FIR_IN34 = 34 ;
+static const uint8_t P9N2_PERV_1_LOCAL_FIR_IN35 = 35 ;
+static const uint8_t P9N2_PERV_1_LOCAL_FIR_IN36 = 36 ;
+static const uint8_t P9N2_PERV_1_LOCAL_FIR_IN37 = 37 ;
+static const uint8_t P9N2_PERV_1_LOCAL_FIR_IN38 = 38 ;
+static const uint8_t P9N2_PERV_1_LOCAL_FIR_IN39 = 39 ;
+static const uint8_t P9N2_PERV_1_LOCAL_FIR_IN40 = 40 ;
+static const uint8_t P9N2_PERV_1_LOCAL_FIR_IN41 = 41 ;
+
+static const uint8_t P9N2_PERV_1_LOCAL_FIR_ACTION0_IN = 0 ;
+static const uint8_t P9N2_PERV_1_LOCAL_FIR_ACTION0_IN_LEN = 42 ;
+
+static const uint8_t P9N2_PERV_1_LOCAL_FIR_ACTION1_IN = 0 ;
+static const uint8_t P9N2_PERV_1_LOCAL_FIR_ACTION1_IN_LEN = 42 ;
+
+static const uint8_t P9N2_PERV_1_LOCAL_FIR_MASK_LFIR_IN = 0 ;
+static const uint8_t P9N2_PERV_1_LOCAL_FIR_MASK_LFIR_IN_LEN = 42 ;
+
+static const uint8_t P9N2_PERV_1_LOCAL_XSTOP_ERR_IN0 = 0 ;
+static const uint8_t P9N2_PERV_1_LOCAL_XSTOP_ERR_IN1 = 1 ;
+static const uint8_t P9N2_PERV_1_LOCAL_XSTOP_ERR_IN2 = 2 ;
+static const uint8_t P9N2_PERV_1_LOCAL_XSTOP_ERR_IN3 = 3 ;
+static const uint8_t P9N2_PERV_1_LOCAL_XSTOP_ERR_IN4 = 4 ;
+static const uint8_t P9N2_PERV_1_LOCAL_XSTOP_ERR_IN5 = 5 ;
+static const uint8_t P9N2_PERV_1_LOCAL_XSTOP_ERR_IN6 = 6 ;
+static const uint8_t P9N2_PERV_1_LOCAL_XSTOP_ERR_IN7 = 7 ;
+static const uint8_t P9N2_PERV_1_LOCAL_XSTOP_ERR_IN8 = 8 ;
+static const uint8_t P9N2_PERV_1_LOCAL_XSTOP_ERR_IN9 = 9 ;
+static const uint8_t P9N2_PERV_1_LOCAL_XSTOP_ERR_IN10 = 10 ;
+static const uint8_t P9N2_PERV_1_LOCAL_XSTOP_ERR_IN11 = 11 ;
+static const uint8_t P9N2_PERV_1_LOCAL_XSTOP_ERR_IN12 = 12 ;
+static const uint8_t P9N2_PERV_1_LOCAL_XSTOP_ERR_IN13 = 13 ;
+static const uint8_t P9N2_PERV_1_LOCAL_XSTOP_ERR_IN14 = 14 ;
+static const uint8_t P9N2_PERV_1_LOCAL_XSTOP_ERR_IN15 = 15 ;
+static const uint8_t P9N2_PERV_1_LOCAL_XSTOP_ERR_IN16 = 16 ;
+static const uint8_t P9N2_PERV_1_LOCAL_XSTOP_ERR_IN17 = 17 ;
+static const uint8_t P9N2_PERV_1_LOCAL_XSTOP_ERR_IN18 = 18 ;
+static const uint8_t P9N2_PERV_1_LOCAL_XSTOP_ERR_IN19 = 19 ;
+static const uint8_t P9N2_PERV_1_LOCAL_XSTOP_ERR_IN20 = 20 ;
+static const uint8_t P9N2_PERV_1_LOCAL_XSTOP_ERR_IN21 = 21 ;
+static const uint8_t P9N2_PERV_1_LOCAL_XSTOP_ERR_IN22 = 22 ;
+
+static const uint8_t P9N2_PERV_1_LOCAL_XSTOP_MASK_IN = 0 ;
+static const uint8_t P9N2_PERV_1_LOCAL_XSTOP_MASK_IN_LEN = 22 ;
+
+static const uint8_t P9N2_PERV_M1A_DATA_AREA_0_MDA_M1A_DATA_AREA = 0 ;
+static const uint8_t P9N2_PERV_M1A_DATA_AREA_0_MDA_M1A_DATA_AREA_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_M1A_DATA_AREA_1_MDA_M1A_DATA_AREA = 0 ;
+static const uint8_t P9N2_PERV_M1A_DATA_AREA_1_MDA_M1A_DATA_AREA_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_M1A_DATA_AREA_10_MDA_M1A_DATA_AREA = 0 ;
+static const uint8_t P9N2_PERV_M1A_DATA_AREA_10_MDA_M1A_DATA_AREA_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_M1A_DATA_AREA_11_MDA_M1A_DATA_AREA = 0 ;
+static const uint8_t P9N2_PERV_M1A_DATA_AREA_11_MDA_M1A_DATA_AREA_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_M1A_DATA_AREA_12_MDA_M1A_DATA_AREA = 0 ;
+static const uint8_t P9N2_PERV_M1A_DATA_AREA_12_MDA_M1A_DATA_AREA_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_M1A_DATA_AREA_13_MDA_M1A_DATA_AREA = 0 ;
+static const uint8_t P9N2_PERV_M1A_DATA_AREA_13_MDA_M1A_DATA_AREA_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_M1A_DATA_AREA_14_MDA_M1A_DATA_AREA = 0 ;
+static const uint8_t P9N2_PERV_M1A_DATA_AREA_14_MDA_M1A_DATA_AREA_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_M1A_DATA_AREA_15_MDA_M1A_DATA_AREA = 0 ;
+static const uint8_t P9N2_PERV_M1A_DATA_AREA_15_MDA_M1A_DATA_AREA_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_M1A_DATA_AREA_2_MDA_M1A_DATA_AREA = 0 ;
+static const uint8_t P9N2_PERV_M1A_DATA_AREA_2_MDA_M1A_DATA_AREA_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_M1A_DATA_AREA_3_MDA_M1A_DATA_AREA = 0 ;
+static const uint8_t P9N2_PERV_M1A_DATA_AREA_3_MDA_M1A_DATA_AREA_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_M1A_DATA_AREA_4_MDA_M1A_DATA_AREA = 0 ;
+static const uint8_t P9N2_PERV_M1A_DATA_AREA_4_MDA_M1A_DATA_AREA_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_M1A_DATA_AREA_5_MDA_M1A_DATA_AREA = 0 ;
+static const uint8_t P9N2_PERV_M1A_DATA_AREA_5_MDA_M1A_DATA_AREA_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_M1A_DATA_AREA_6_MDA_M1A_DATA_AREA = 0 ;
+static const uint8_t P9N2_PERV_M1A_DATA_AREA_6_MDA_M1A_DATA_AREA_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_M1A_DATA_AREA_7_MDA_M1A_DATA_AREA = 0 ;
+static const uint8_t P9N2_PERV_M1A_DATA_AREA_7_MDA_M1A_DATA_AREA_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_M1A_DATA_AREA_8_MDA_M1A_DATA_AREA = 0 ;
+static const uint8_t P9N2_PERV_M1A_DATA_AREA_8_MDA_M1A_DATA_AREA_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_M1A_DATA_AREA_9_MDA_M1A_DATA_AREA = 0 ;
+static const uint8_t P9N2_PERV_M1A_DATA_AREA_9_MDA_M1A_DATA_AREA_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_M1B_DATA_AREA_0_MDA_M1B_DATA_AREA = 0 ;
+static const uint8_t P9N2_PERV_M1B_DATA_AREA_0_MDA_M1B_DATA_AREA_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_M1B_DATA_AREA_1_MDA_M1B_DATA_AREA = 0 ;
+static const uint8_t P9N2_PERV_M1B_DATA_AREA_1_MDA_M1B_DATA_AREA_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_M1B_DATA_AREA_10_MDA_M1B_DATA_AREA = 0 ;
+static const uint8_t P9N2_PERV_M1B_DATA_AREA_10_MDA_M1B_DATA_AREA_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_M1B_DATA_AREA_11_MDA_M1B_DATA_AREA = 0 ;
+static const uint8_t P9N2_PERV_M1B_DATA_AREA_11_MDA_M1B_DATA_AREA_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_M1B_DATA_AREA_12_MDA_M1B_DATA_AREA = 0 ;
+static const uint8_t P9N2_PERV_M1B_DATA_AREA_12_MDA_M1B_DATA_AREA_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_M1B_DATA_AREA_13_MDA_M1B_DATA_AREA = 0 ;
+static const uint8_t P9N2_PERV_M1B_DATA_AREA_13_MDA_M1B_DATA_AREA_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_M1B_DATA_AREA_14_MDA_M1B_DATA_AREA = 0 ;
+static const uint8_t P9N2_PERV_M1B_DATA_AREA_14_MDA_M1B_DATA_AREA_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_M1B_DATA_AREA_15_MDA_M1B_DATA_AREA = 0 ;
+static const uint8_t P9N2_PERV_M1B_DATA_AREA_15_MDA_M1B_DATA_AREA_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_M1B_DATA_AREA_2_MDA_M1B_DATA_AREA = 0 ;
+static const uint8_t P9N2_PERV_M1B_DATA_AREA_2_MDA_M1B_DATA_AREA_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_M1B_DATA_AREA_3_MDA_M1B_DATA_AREA = 0 ;
+static const uint8_t P9N2_PERV_M1B_DATA_AREA_3_MDA_M1B_DATA_AREA_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_M1B_DATA_AREA_4_MDA_M1B_DATA_AREA = 0 ;
+static const uint8_t P9N2_PERV_M1B_DATA_AREA_4_MDA_M1B_DATA_AREA_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_M1B_DATA_AREA_5_MDA_M1B_DATA_AREA = 0 ;
+static const uint8_t P9N2_PERV_M1B_DATA_AREA_5_MDA_M1B_DATA_AREA_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_M1B_DATA_AREA_6_MDA_M1B_DATA_AREA = 0 ;
+static const uint8_t P9N2_PERV_M1B_DATA_AREA_6_MDA_M1B_DATA_AREA_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_M1B_DATA_AREA_7_MDA_M1B_DATA_AREA = 0 ;
+static const uint8_t P9N2_PERV_M1B_DATA_AREA_7_MDA_M1B_DATA_AREA_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_M1B_DATA_AREA_8_MDA_M1B_DATA_AREA = 0 ;
+static const uint8_t P9N2_PERV_M1B_DATA_AREA_8_MDA_M1B_DATA_AREA_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_M1B_DATA_AREA_9_MDA_M1B_DATA_AREA = 0 ;
+static const uint8_t P9N2_PERV_M1B_DATA_AREA_9_MDA_M1B_DATA_AREA_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_M2A_DATA_AREA_0_MDA_M2A_DATA_AREA = 0 ;
+static const uint8_t P9N2_PERV_M2A_DATA_AREA_0_MDA_M2A_DATA_AREA_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_M2A_DATA_AREA_1_MDA_M2A_DATA_AREA = 0 ;
+static const uint8_t P9N2_PERV_M2A_DATA_AREA_1_MDA_M2A_DATA_AREA_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_M2A_DATA_AREA_10_MDA_M2A_DATA_AREA = 0 ;
+static const uint8_t P9N2_PERV_M2A_DATA_AREA_10_MDA_M2A_DATA_AREA_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_M2A_DATA_AREA_11_MDA_M2A_DATA_AREA = 0 ;
+static const uint8_t P9N2_PERV_M2A_DATA_AREA_11_MDA_M2A_DATA_AREA_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_M2A_DATA_AREA_12_MDA_M2A_DATA_AREA = 0 ;
+static const uint8_t P9N2_PERV_M2A_DATA_AREA_12_MDA_M2A_DATA_AREA_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_M2A_DATA_AREA_13_MDA_M2A_DATA_AREA = 0 ;
+static const uint8_t P9N2_PERV_M2A_DATA_AREA_13_MDA_M2A_DATA_AREA_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_M2A_DATA_AREA_14_MDA_M2A_DATA_AREA = 0 ;
+static const uint8_t P9N2_PERV_M2A_DATA_AREA_14_MDA_M2A_DATA_AREA_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_M2A_DATA_AREA_15_MDA_M2A_DATA_AREA = 0 ;
+static const uint8_t P9N2_PERV_M2A_DATA_AREA_15_MDA_M2A_DATA_AREA_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_M2A_DATA_AREA_2_MDA_M2A_DATA_AREA = 0 ;
+static const uint8_t P9N2_PERV_M2A_DATA_AREA_2_MDA_M2A_DATA_AREA_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_M2A_DATA_AREA_3_MDA_M2A_DATA_AREA = 0 ;
+static const uint8_t P9N2_PERV_M2A_DATA_AREA_3_MDA_M2A_DATA_AREA_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_M2A_DATA_AREA_4_MDA_M2A_DATA_AREA = 0 ;
+static const uint8_t P9N2_PERV_M2A_DATA_AREA_4_MDA_M2A_DATA_AREA_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_M2A_DATA_AREA_5_MDA_M2A_DATA_AREA = 0 ;
+static const uint8_t P9N2_PERV_M2A_DATA_AREA_5_MDA_M2A_DATA_AREA_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_M2A_DATA_AREA_6_MDA_M2A_DATA_AREA = 0 ;
+static const uint8_t P9N2_PERV_M2A_DATA_AREA_6_MDA_M2A_DATA_AREA_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_M2A_DATA_AREA_7_MDA_M2A_DATA_AREA = 0 ;
+static const uint8_t P9N2_PERV_M2A_DATA_AREA_7_MDA_M2A_DATA_AREA_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_M2A_DATA_AREA_8_MDA_M2A_DATA_AREA = 0 ;
+static const uint8_t P9N2_PERV_M2A_DATA_AREA_8_MDA_M2A_DATA_AREA_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_M2A_DATA_AREA_9_MDA_M2A_DATA_AREA = 0 ;
+static const uint8_t P9N2_PERV_M2A_DATA_AREA_9_MDA_M2A_DATA_AREA_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_M2B_DATA_AREA_0_MDA_M2B_DATA_AREA = 0 ;
+static const uint8_t P9N2_PERV_M2B_DATA_AREA_0_MDA_M2B_DATA_AREA_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_M2B_DATA_AREA_1_MDA_M2B_DATA_AREA = 0 ;
+static const uint8_t P9N2_PERV_M2B_DATA_AREA_1_MDA_M2B_DATA_AREA_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_M2B_DATA_AREA_10_MDA_M2B_DATA_AREA = 0 ;
+static const uint8_t P9N2_PERV_M2B_DATA_AREA_10_MDA_M2B_DATA_AREA_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_M2B_DATA_AREA_11_MDA_M2B_DATA_AREA = 0 ;
+static const uint8_t P9N2_PERV_M2B_DATA_AREA_11_MDA_M2B_DATA_AREA_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_M2B_DATA_AREA_12_MDA_M2B_DATA_AREA = 0 ;
+static const uint8_t P9N2_PERV_M2B_DATA_AREA_12_MDA_M2B_DATA_AREA_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_M2B_DATA_AREA_13_MDA_M2B_DATA_AREA = 0 ;
+static const uint8_t P9N2_PERV_M2B_DATA_AREA_13_MDA_M2B_DATA_AREA_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_M2B_DATA_AREA_14_MDA_M2B_DATA_AREA = 0 ;
+static const uint8_t P9N2_PERV_M2B_DATA_AREA_14_MDA_M2B_DATA_AREA_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_M2B_DATA_AREA_15_MDA_M2B_DATA_AREA = 0 ;
+static const uint8_t P9N2_PERV_M2B_DATA_AREA_15_MDA_M2B_DATA_AREA_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_M2B_DATA_AREA_2_MDA_M2B_DATA_AREA = 0 ;
+static const uint8_t P9N2_PERV_M2B_DATA_AREA_2_MDA_M2B_DATA_AREA_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_M2B_DATA_AREA_3_MDA_M2B_DATA_AREA = 0 ;
+static const uint8_t P9N2_PERV_M2B_DATA_AREA_3_MDA_M2B_DATA_AREA_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_M2B_DATA_AREA_4_MDA_M2B_DATA_AREA = 0 ;
+static const uint8_t P9N2_PERV_M2B_DATA_AREA_4_MDA_M2B_DATA_AREA_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_M2B_DATA_AREA_5_MDA_M2B_DATA_AREA = 0 ;
+static const uint8_t P9N2_PERV_M2B_DATA_AREA_5_MDA_M2B_DATA_AREA_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_M2B_DATA_AREA_6_MDA_M2B_DATA_AREA = 0 ;
+static const uint8_t P9N2_PERV_M2B_DATA_AREA_6_MDA_M2B_DATA_AREA_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_M2B_DATA_AREA_7_MDA_M2B_DATA_AREA = 0 ;
+static const uint8_t P9N2_PERV_M2B_DATA_AREA_7_MDA_M2B_DATA_AREA_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_M2B_DATA_AREA_8_MDA_M2B_DATA_AREA = 0 ;
+static const uint8_t P9N2_PERV_M2B_DATA_AREA_8_MDA_M2B_DATA_AREA_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_M2B_DATA_AREA_9_MDA_M2B_DATA_AREA = 0 ;
+static const uint8_t P9N2_PERV_M2B_DATA_AREA_9_MDA_M2B_DATA_AREA_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_MAILBOX_1_HEADER_COMMAND_0_A_M1HC0A = 0 ;
+static const uint8_t P9N2_PERV_MAILBOX_1_HEADER_COMMAND_0_A_M1HC0A_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_MAILBOX_1_HEADER_COMMAND_0_B_M1HC0B = 0 ;
+static const uint8_t P9N2_PERV_MAILBOX_1_HEADER_COMMAND_0_B_M1HC0B_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_MAILBOX_1_HEADER_COMMAND_1_A_M1HC1A = 0 ;
+static const uint8_t P9N2_PERV_MAILBOX_1_HEADER_COMMAND_1_A_M1HC1A_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_MAILBOX_1_HEADER_COMMAND_1_B_M1HC1B = 0 ;
+static const uint8_t P9N2_PERV_MAILBOX_1_HEADER_COMMAND_1_B_M1HC1B_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_MAILBOX_1_HEADER_COMMAND_2_A_M1HC2A = 0 ;
+static const uint8_t P9N2_PERV_MAILBOX_1_HEADER_COMMAND_2_A_M1HC2A_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_MAILBOX_1_HEADER_COMMAND_2_B_M1HC2B = 0 ;
+static const uint8_t P9N2_PERV_MAILBOX_1_HEADER_COMMAND_2_B_M1HC2B_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_MAILBOX_1_SLAVE_A_DOORBELL_INTERRUPT_MASK_1_M1SASIM1_ENABLE_PIB_ERROR = 29 ;
+static const uint8_t P9N2_PERV_MAILBOX_1_SLAVE_A_DOORBELL_INTERRUPT_MASK_1_M1SASIM1_ENABLE_XUP = 30 ;
+static const uint8_t P9N2_PERV_MAILBOX_1_SLAVE_A_DOORBELL_INTERRUPT_MASK_1_M1SASIM1_ENABLE_PIB_PENDING = 31 ;
+
+static const uint8_t P9N2_PERV_MAILBOX_2_HEADER_COMMAND_0_A_M2HC0A = 0 ;
+static const uint8_t P9N2_PERV_MAILBOX_2_HEADER_COMMAND_0_A_M2HC0A_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_MAILBOX_2_HEADER_COMMAND_0_B_M2HC0B = 0 ;
+static const uint8_t P9N2_PERV_MAILBOX_2_HEADER_COMMAND_0_B_M2HC0B_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_MAILBOX_2_HEADER_COMMAND_1_A_M2HC1A = 0 ;
+static const uint8_t P9N2_PERV_MAILBOX_2_HEADER_COMMAND_1_A_M2HC1A_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_MAILBOX_2_HEADER_COMMAND_1_B_M2HC1B = 0 ;
+static const uint8_t P9N2_PERV_MAILBOX_2_HEADER_COMMAND_1_B_M2HC1B_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_MAILBOX_2_HEADER_COMMAND_2_A_M2HC2A = 0 ;
+static const uint8_t P9N2_PERV_MAILBOX_2_HEADER_COMMAND_2_A_M2HC2A_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_MAILBOX_2_HEADER_COMMAND_2_B_M2HC2B = 0 ;
+static const uint8_t P9N2_PERV_MAILBOX_2_HEADER_COMMAND_2_B_M2HC2B_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_MSADES_UNUSED_31_28 = 0 ;
+static const uint8_t P9N2_PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_MSADES_UNUSED_31_28_LEN = 4 ;
+static const uint8_t P9N2_PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_MSADES_ILLEGAL_OPERATION_ATTEMPTED_1 = 4 ;
+static const uint8_t P9N2_PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_MSADES_WRITE_FULL_PIB_1 = 5 ;
+static const uint8_t P9N2_PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_MSADES_READ_EMPTY_PIB_1 = 6 ;
+static const uint8_t P9N2_PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_MSADES_LBUS_B_RAM_PARITY_DETECTED_1 = 7 ;
+static const uint8_t P9N2_PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_MSADES_ADDRESS_OF_LBUS_PARITY_1 = 8 ;
+static const uint8_t P9N2_PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_MSADES_ADDRESS_OF_LBUS_PARITY_1_LEN = 7 ;
+static const uint8_t P9N2_PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_MSADES_CLEAR_1 = 15 ;
+static const uint8_t P9N2_PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_MSADES_UNUSED_15_12 = 16 ;
+static const uint8_t P9N2_PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_MSADES_UNUSED_15_12_LEN = 4 ;
+static const uint8_t P9N2_PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_MSADES_ILLEGAL_OPERATION_ATTEMPTED_2 = 20 ;
+static const uint8_t P9N2_PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_MSADES_WRITE_FULL_PIB_2 = 21 ;
+static const uint8_t P9N2_PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_MSADES_READ_EMPTY_PIB_2 = 22 ;
+static const uint8_t P9N2_PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_MSADES_LBUS_B_RAM_PARITY_DETECTED_2 = 23 ;
+static const uint8_t P9N2_PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_MSADES_ADDRESS_OF_LBUS_PARITY_2 = 24 ;
+static const uint8_t P9N2_PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_MSADES_ADDRESS_OF_LBUS_PARITY_2_LEN = 7 ;
+static const uint8_t P9N2_PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_MSADES_CLEAR_2 = 31 ;
+
+static const uint8_t P9N2_PERV_MAILBOX_SLAVE_A_DOORBELL_INTERRUPT_MSADI_UNUSED_31_11 = 11 ;
+static const uint8_t P9N2_PERV_MAILBOX_SLAVE_A_DOORBELL_INTERRUPT_MSADI_UNUSED_31_11_LEN = 10 ;
+static const uint8_t P9N2_PERV_MAILBOX_SLAVE_A_DOORBELL_INTERRUPT_MSADI_PIB_ERROR_2 = 21 ;
+static const uint8_t P9N2_PERV_MAILBOX_SLAVE_A_DOORBELL_INTERRUPT_MSADI_XUP_2 = 22 ;
+static const uint8_t P9N2_PERV_MAILBOX_SLAVE_A_DOORBELL_INTERRUPT_MSADI_PIB_PENDING_2 = 23 ;
+static const uint8_t P9N2_PERV_MAILBOX_SLAVE_A_DOORBELL_INTERRUPT_MSADI_UNUSED_7_3 = 24 ;
+static const uint8_t P9N2_PERV_MAILBOX_SLAVE_A_DOORBELL_INTERRUPT_MSADI_UNUSED_7_3_LEN = 5 ;
+static const uint8_t P9N2_PERV_MAILBOX_SLAVE_A_DOORBELL_INTERRUPT_MSADI_PIB_ERROR_1 = 29 ;
+static const uint8_t P9N2_PERV_MAILBOX_SLAVE_A_DOORBELL_INTERRUPT_MSADI_XUP_1 = 30 ;
+static const uint8_t P9N2_PERV_MAILBOX_SLAVE_A_DOORBELL_INTERRUPT_MSADI_PIB_PENDING_1 = 31 ;
+
+static const uint8_t P9N2_PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_MSBDES_UNUSED_31_28 = 0 ;
+static const uint8_t P9N2_PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_MSBDES_UNUSED_31_28_LEN = 4 ;
+static const uint8_t P9N2_PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_MSBDES_ILLEGAL_OPERATION_ATTEMPTED_1 = 4 ;
+static const uint8_t P9N2_PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_MSBDES_WRITE_FULL_PIB_A_1 = 5 ;
+static const uint8_t P9N2_PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_MSBDES_READ_EMPTY_PIB_A_1 = 6 ;
+static const uint8_t P9N2_PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_MSBDES_PIB_A_RAM_PARITY_DETECTED_1 = 7 ;
+static const uint8_t P9N2_PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_MSBDES_ADDRESS_OF_PIB_PARITY_1 = 8 ;
+static const uint8_t P9N2_PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_MSBDES_ADDRESS_OF_PIB_PARITY_1_LEN = 7 ;
+static const uint8_t P9N2_PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_MSBDES_CLEAR_1 = 15 ;
+static const uint8_t P9N2_PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_MSBDES_UNUSED_15_12 = 16 ;
+static const uint8_t P9N2_PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_MSBDES_UNUSED_15_12_LEN = 4 ;
+static const uint8_t P9N2_PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_MSBDES_ILLEGAL_OPERATION_ATTEMPTED_2 = 20 ;
+static const uint8_t P9N2_PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_MSBDES_WRITE_FULL_PIB_A_2 = 21 ;
+static const uint8_t P9N2_PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_MSBDES_READ_EMPTY_PIB_A_2 = 22 ;
+static const uint8_t P9N2_PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_MSBDES_PIB_A_RAM_PARITY_DETECTED_2 = 23 ;
+static const uint8_t P9N2_PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_MSBDES_ADDRESS_OF_PIB_PARITY_2 = 24 ;
+static const uint8_t P9N2_PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_MSBDES_ADDRESS_OF_PIB_PARITY_2_LEN = 7 ;
+static const uint8_t P9N2_PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_MSBDES_CLEAR_2 = 31 ;
+
+static const uint8_t P9N2_PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MSBDI_ABORT_MAILBOX_2 = 24 ;
+static const uint8_t P9N2_PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MSBDI_ABORT_MAILBOX_1 = 25 ;
+static const uint8_t P9N2_PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MSBDI_LBUS_ERROR_2 = 26 ;
+static const uint8_t P9N2_PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MSBDI_LBUS_ERROR_1 = 27 ;
+static const uint8_t P9N2_PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MSBDI_XDN_2 = 28 ;
+static const uint8_t P9N2_PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MSBDI_XDN_1 = 29 ;
+static const uint8_t P9N2_PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MSBDI_LBUS_PENDING_2 = 30 ;
+static const uint8_t P9N2_PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MSBDI_LBUS_PENDING_1 = 31 ;
+
+static const uint8_t P9N2_PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MASK_1_MSBDIM1_ENABLE_LBUS_PENDING = 24 ;
+static const uint8_t P9N2_PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MASK_1_MSBDIM1_ENABLE_LBUS_PENDING_2 = 25 ;
+static const uint8_t P9N2_PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MASK_1_MSBDIM1_ENABLE_XDN = 26 ;
+static const uint8_t P9N2_PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MASK_1_MSBDIM1_ENABLE_XDN_2 = 27 ;
+static const uint8_t P9N2_PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MASK_1_MSBDIM1_ENABLE_LBUS_ERROR = 28 ;
+static const uint8_t P9N2_PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MASK_1_MSBDIM1_ENABLE_LBUS_ERROR_2 = 29 ;
+static const uint8_t P9N2_PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MASK_1_MSBDIM1_ENABLE_ABORT = 30 ;
+static const uint8_t P9N2_PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MASK_1_MSBDIM1_ENABLE_ABORT_2 = 31 ;
+
+static const uint8_t P9N2_PERV_MCAST_COMP_MASK_REG_MULTICAST_COMPARE_REGISTER = 0 ;
+static const uint8_t P9N2_PERV_MCAST_COMP_MASK_REG_MULTICAST_COMPARE_REGISTER_LEN = 64 ;
+
+static const uint8_t P9N2_PERV_MCAST_COMP_REG_MULTICAST_COMPARE_REGISTER = 0 ;
+static const uint8_t P9N2_PERV_MCAST_COMP_REG_MULTICAST_COMPARE_REGISTER_LEN = 2 ;
+
+static const uint8_t P9N2_PERV_MCAST_COMP_VAL_REG_MULTICAST_COMPARE_VALUE_REGISTER = 0 ;
+static const uint8_t P9N2_PERV_MCAST_COMP_VAL_REG_MULTICAST_COMPARE_VALUE_REGISTER_LEN = 64 ;
+
+static const uint8_t P9N2_PERV_MCAST_GRP_0_SLAVES_REG_GROUP = 0 ;
+static const uint8_t P9N2_PERV_MCAST_GRP_0_SLAVES_REG_GROUP_LEN = 6 ;
+
+static const uint8_t P9N2_PERV_MCAST_GRP_1_SLAVES_REG_GROUP = 0 ;
+static const uint8_t P9N2_PERV_MCAST_GRP_1_SLAVES_REG_GROUP_LEN = 6 ;
+
+static const uint8_t P9N2_PERV_MCAST_GRP_2_SLAVES_REG_GROUP = 0 ;
+static const uint8_t P9N2_PERV_MCAST_GRP_2_SLAVES_REG_GROUP_LEN = 6 ;
+
+static const uint8_t P9N2_PERV_MCAST_GRP_3_SLAVES_REG_GROUP = 0 ;
+static const uint8_t P9N2_PERV_MCAST_GRP_3_SLAVES_REG_GROUP_LEN = 6 ;
+
+static const uint8_t P9N2_PERV_MCAST_GRP_4_SLAVES_REG_GROUP = 0 ;
+static const uint8_t P9N2_PERV_MCAST_GRP_4_SLAVES_REG_GROUP_LEN = 6 ;
+
+static const uint8_t P9N2_PERV_MCAST_GRP_5_SLAVES_REG_GROUP = 0 ;
+static const uint8_t P9N2_PERV_MCAST_GRP_5_SLAVES_REG_GROUP_LEN = 6 ;
+
+static const uint8_t P9N2_PERV_MCAST_GRP_6_SLAVES_REG_GROUP = 0 ;
+static const uint8_t P9N2_PERV_MCAST_GRP_6_SLAVES_REG_GROUP_LEN = 6 ;
+
+static const uint8_t P9N2_PERV_1_MODE_REG_IN0 = 0 ;
+static const uint8_t P9N2_PERV_1_MODE_REG_IN1 = 1 ;
+static const uint8_t P9N2_PERV_1_MODE_REG_IN2 = 2 ;
+static const uint8_t P9N2_PERV_1_MODE_REG_IN3 = 3 ;
+static const uint8_t P9N2_PERV_1_MODE_REG_IN4 = 4 ;
+static const uint8_t P9N2_PERV_1_MODE_REG_IN5 = 5 ;
+static const uint8_t P9N2_PERV_1_MODE_REG_IN6 = 6 ;
+static const uint8_t P9N2_PERV_1_MODE_REG_IN7 = 7 ;
+static const uint8_t P9N2_PERV_1_MODE_REG_IN8 = 8 ;
+static const uint8_t P9N2_PERV_1_MODE_REG_IN9 = 9 ;
+static const uint8_t P9N2_PERV_1_MODE_REG_IN10 = 10 ;
+static const uint8_t P9N2_PERV_1_MODE_REG_IN11 = 11 ;
+static const uint8_t P9N2_PERV_1_MODE_REG_IN = 12 ;
+static const uint8_t P9N2_PERV_1_MODE_REG_IN_LEN = 4 ;
+
+static const uint8_t P9N2_PERV_FSII2C_MODE_REGISTER_A_BIT_RATE_DIVISOR_0 = 0 ;
+static const uint8_t P9N2_PERV_FSII2C_MODE_REGISTER_A_BIT_RATE_DIVISOR_0_LEN = 16 ;
+static const uint8_t P9N2_PERV_FSII2C_MODE_REGISTER_A_PORT_NUMBER_0 = 16 ;
+static const uint8_t P9N2_PERV_FSII2C_MODE_REGISTER_A_PORT_NUMBER_0_LEN = 6 ;
+static const uint8_t P9N2_PERV_FSII2C_MODE_REGISTER_A_FGAT_0 = 28 ;
+static const uint8_t P9N2_PERV_FSII2C_MODE_REGISTER_A_DIAG_0 = 29 ;
+static const uint8_t P9N2_PERV_FSII2C_MODE_REGISTER_A_PACING_ALLOW_0 = 30 ;
+static const uint8_t P9N2_PERV_FSII2C_MODE_REGISTER_A_WRAP_0 = 31 ;
+
+static const uint8_t P9N2_PERV_1_MULTICAST_GROUP_1_MULTICAST1 = 3 ;
+static const uint8_t P9N2_PERV_1_MULTICAST_GROUP_1_MULTICAST1_LEN = 3 ;
+
+static const uint8_t P9N2_PERV_1_MULTICAST_GROUP_2_MULTICAST2 = 3 ;
+static const uint8_t P9N2_PERV_1_MULTICAST_GROUP_2_MULTICAST2_LEN = 3 ;
+
+static const uint8_t P9N2_PERV_1_MULTICAST_GROUP_3_MULTICAST3 = 3 ;
+static const uint8_t P9N2_PERV_1_MULTICAST_GROUP_3_MULTICAST3_LEN = 3 ;
+
+static const uint8_t P9N2_PERV_1_MULTICAST_GROUP_4_MULTICAST4 = 3 ;
+static const uint8_t P9N2_PERV_1_MULTICAST_GROUP_4_MULTICAST4_LEN = 3 ;
+
+static const uint8_t P9N2_PERV_1_NET_CTRL0_CHIPLET_ENABLE = 0 ;
+static const uint8_t P9N2_PERV_1_NET_CTRL0_PCB_EP_RESET = 1 ;
+static const uint8_t P9N2_PERV_1_NET_CTRL0_CLK_ASYNC_RESET = 2 ;
+static const uint8_t P9N2_PERV_1_NET_CTRL0_PLL_TEST_EN = 3 ;
+static const uint8_t P9N2_PERV_1_NET_CTRL0_PLL_RESET = 4 ;
+static const uint8_t P9N2_PERV_1_NET_CTRL0_PLL_BYPASS = 5 ;
+static const uint8_t P9N2_PERV_1_NET_CTRL0_VITAL_SCAN = 6 ;
+static const uint8_t P9N2_PERV_1_NET_CTRL0_VITAL_SCAN_IN = 7 ;
+static const uint8_t P9N2_PERV_1_NET_CTRL0_VITAL_PHASE = 8 ;
+static const uint8_t P9N2_PERV_1_NET_CTRL0_FLUSH_ALIGN_OVR = 9 ;
+static const uint8_t P9N2_PERV_1_NET_CTRL0_VITAL_AL = 10 ;
+static const uint8_t P9N2_PERV_1_NET_CTRL0_ACT_DIS = 11 ;
+static const uint8_t P9N2_PERV_1_NET_CTRL0_MPW1 = 12 ;
+static const uint8_t P9N2_PERV_1_NET_CTRL0_MPW2 = 13 ;
+static const uint8_t P9N2_PERV_1_NET_CTRL0_MPW3 = 14 ;
+static const uint8_t P9N2_PERV_1_NET_CTRL0_DELAY_LCLKR = 15 ;
+static const uint8_t P9N2_PERV_1_NET_CTRL0_VITAL_THOLD = 16 ;
+static const uint8_t P9N2_PERV_1_NET_CTRL0_FLUSH_SCAN_N = 17 ;
+static const uint8_t P9N2_PERV_1_NET_CTRL0_FENCE_EN = 18 ;
+static const uint8_t P9N2_PERV_1_NET_CTRL0_CPLT_RCTRL = 19 ;
+static const uint8_t P9N2_PERV_1_NET_CTRL0_CPLT_DCTRL = 20 ;
+static const uint8_t P9N2_PERV_1_NET_CTRL0_ADJ_FUNC_CLKSEL = 22 ;
+static const uint8_t P9N2_PERV_1_NET_CTRL0_TP_FENCE_PCB = 25 ;
+static const uint8_t P9N2_PERV_1_NET_CTRL0_LVLTRANS_FENCE = 26 ;
+static const uint8_t P9N2_PERV_1_NET_CTRL0_ARRAY_WRITE_ASSIST_EN = 27 ;
+static const uint8_t P9N2_PERV_1_NET_CTRL0_HTB_INTEST = 28 ;
+static const uint8_t P9N2_PERV_1_NET_CTRL0_HTB_EXTEST = 29 ;
+static const uint8_t P9N2_PERV_1_NET_CTRL0_PM_ACCESS = 30 ;
+static const uint8_t P9N2_PERV_1_NET_CTRL0_PLLFORCE_OUT_EN = 31 ;
+
+static const uint8_t P9N2_PERV_1_NET_CTRL1_PLL_CLKIN_SEL = 0 ;
+static const uint8_t P9N2_PERV_1_NET_CTRL1_CLK_DCC_BYPASS_EN = 1 ;
+static const uint8_t P9N2_PERV_1_NET_CTRL1_CLK_PDLY_BYPASS_EN = 2 ;
+static const uint8_t P9N2_PERV_1_NET_CTRL1_CLK_DIV_BYPASS_EN = 3 ;
+static const uint8_t P9N2_PERV_1_NET_CTRL1_REFCLK_CLKMUX0_SEL = 4 ;
+static const uint8_t P9N2_PERV_1_NET_CTRL1_REFCLK_CLKMUX1_SEL = 5 ;
+static const uint8_t P9N2_PERV_1_NET_CTRL1_PLL_BNDY_BYPASS_EN = 6 ;
+static const uint8_t P9N2_PERV_1_NET_CTRL1_DPLL_TEST_SEL = 8 ;
+static const uint8_t P9N2_PERV_1_NET_CTRL1_DPLL_TEST_SEL_LEN = 8 ;
+static const uint8_t P9N2_PERV_1_NET_CTRL1_SB_STRENGTH = 16 ;
+static const uint8_t P9N2_PERV_1_NET_CTRL1_SB_STRENGTH_LEN = 4 ;
+static const uint8_t P9N2_PERV_1_NET_CTRL1_ASYNC_TYPE = 20 ;
+static const uint8_t P9N2_PERV_1_NET_CTRL1_ASYNC_OBS = 21 ;
+static const uint8_t P9N2_PERV_1_NET_CTRL1_CPM_CAL_SET = 22 ;
+static const uint8_t P9N2_PERV_1_NET_CTRL1_SENSEADJ_RESET0 = 23 ;
+static const uint8_t P9N2_PERV_1_NET_CTRL1_SENSEADJ_RESET1 = 24 ;
+static const uint8_t P9N2_PERV_1_NET_CTRL1_CLK_PULSE_EN = 25 ;
+static const uint8_t P9N2_PERV_1_NET_CTRL1_CLK_PULSE_MODE = 26 ;
+static const uint8_t P9N2_PERV_1_NET_CTRL1_CLK_PULSE_MODE_LEN = 2 ;
+static const uint8_t P9N2_PERV_1_NET_CTRL1_PCB_ACCESS = 28 ;
+static const uint8_t P9N2_PERV_1_NET_CTRL1_PCB_ACCESS_LEN = 4 ;
+
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCERRRPT_SRAM_CERRRPT = 0 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCERRRPT_SRAM_CERRRPT_LEN = 10 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCERRRPT_JTAGACC_CERRPT = 10 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCERRRPT_JTAGACC_CERRPT_LEN = 6 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCERRRPT_C405_DCU_ECC_UE = 16 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCERRRPT_C405_DCU_ECC_CE = 17 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCERRRPT_C405_ICU_ECC_UE = 18 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCERRRPT_C405_ICU_ECC_CE = 19 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCERRRPT_GPE0_OCISLV_ERR = 20 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCERRRPT_GPE0_OCISLV_ERR_LEN = 7 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCERRRPT_GPE1_OCISLV_ERR = 28 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCERRRPT_GPE1_OCISLV_ERR_LEN = 7 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCERRRPT_GPE2_OCISLV_ERR = 36 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCERRRPT_GPE2_OCISLV_ERR_LEN = 7 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCERRRPT_GPE3_OCISLV_ERR = 44 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCERRRPT_GPE3_OCISLV_ERR_LEN = 7 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCERRRPT_OCB_OCISLV_ERR = 52 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCERRRPT_OCB_OCISLV_ERR_LEN = 6 ;
+
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIR_FW0 = 0 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIR_FW1 = 1 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIR_CME_ERROR_NOTIFY = 2 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIR_STOP_RECOVERY_NOTIFY_PRD = 3 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIR_HB_ERROR = 4 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIR_GPE0_WATCHDOG_TIMEOUT = 5 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIR_GPE1_WATCHDOG_TIMEOUT = 6 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIR_GPE2_WATCHDOG_TIMEOUT = 7 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIR_GPE3_WATCHDOG_TIMEOUT = 8 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIR_GPE0_ERROR = 9 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIR_GPE1_ERROR = 10 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIR_GPE2_ERROR = 11 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIR_GPE3_ERROR = 12 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIR_OCB_ERROR = 13 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIR_SRT_UE = 14 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIR_SRT_CE = 15 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIR_SRT_READ_ERROR = 16 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIR_SRT_WRITE_ERROR = 17 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIR_SRT_DATAOUT_PERR = 18 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIR_SRT_OCI_WRITE_DATA_PARITY = 19 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIR_SRT_OCI_BE_PARITY_ERR = 20 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIR_SRT_OCI_ADDR_PARITY_ERR = 21 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIR_GPE0_HALTED = 22 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIR_GPE1_HALTED = 23 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIR_GPE2_HALTED = 24 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIR_GPE3_HALTED = 25 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIR_EXTERNAL_TRAP = 26 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIR_PPC405_CORE_RESET = 27 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIR_PPC405_CHIP_RESET = 28 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIR_PPC405_SYSTEM_RESET = 29 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIR_PPC405_DBGMSRWE = 30 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIR_PPC405_DBGSTOPACK = 31 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIR_OCB_DB_OCI_TIMEOUT = 32 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIR_OCB_DB_OCI_READ_DATA_PARITY = 33 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIR_OCB_DB_OCI_SLAVE_ERROR = 34 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIR_OCB_PIB_ADDR_PARITY_ERR = 35 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIR_OCB_DB_PIB_DATA_PARITY_ERR = 36 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIR_OCB_IDC0_ERROR = 37 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIR_OCB_IDC1_ERROR = 38 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIR_OCB_IDC2_ERROR = 39 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIR_OCB_IDC3_ERROR = 40 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIR_SRT_FSM_ERR = 41 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIR_JTAGACC_ERR = 42 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIR_SPARE_ERR_38 = 43 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIR_C405_ECC_UE = 44 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIR_C405_ECC_CE = 45 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIR_C405_OCI_MACHINECHECK = 46 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIR_SRAM_SPARE_DIRECT_ERROR0 = 47 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIR_SRAM_SPARE_DIRECT_ERROR1 = 48 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIR_SRAM_SPARE_DIRECT_ERROR2 = 49 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIR_SRAM_SPARE_DIRECT_ERROR3 = 50 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIR_GPE0_OCISLV_ERR = 51 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIR_GPE1_OCISLV_ERR = 52 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIR_GPE2_OCISLV_ERR = 53 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIR_GPE3_OCISLV_ERR = 54 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIR_C405ICU_M_TIMEOUT = 55 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIR_C405DCU_M_TIMEOUT = 56 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIR_COMPLEX_FAULT = 57 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIR_COMPLEX_NOTIFY = 58 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIR_SPARE_59_61 = 59 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIR_SPARE_59_61_LEN = 3 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIR_FIR_PARITY_ERR_DUP = 62 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIR_FIR_PARITY_ERR = 63 ;
+
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIRACT0_FIR_ACTION0 = 0 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIRACT0_FIR_ACTION0_LEN = 64 ;
+
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIRACT1_FIR_ACTION1 = 0 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIRACT1_FIR_ACTION1_LEN = 64 ;
+
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIRMASK_FW0_MASK = 0 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIRMASK_FW1_MASK = 1 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIRMASK_SPARE_2_MASK = 2 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIRMASK_SPARE_3_MASK = 3 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIRMASK_HB_MALF_MASK = 4 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIRMASK_GPE0_WATCHDOG_TIMEOUT_MASK = 5 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIRMASK_GPE1_WATCHDOG_TIMEOUT_MASK = 6 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIRMASK_GPE2_WATCHDOG_TIMEOUT_MASK = 7 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIRMASK_GPE3_WATCHDOG_TIMEOUT_MASK = 8 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIRMASK_GPE0_ERROR_MASK = 9 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIRMASK_GPE1_ERROR_MASK = 10 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIRMASK_GPE2_ERROR_MASK = 11 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIRMASK_GPE3_ERROR_MASK = 12 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIRMASK_OCB_ERROR_MASK = 13 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIRMASK_SRT_UE_MASK = 14 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIRMASK_SRT_CE_MASK = 15 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIRMASK_SRT_READ_ERROR_MASK = 16 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIRMASK_SRT_WRITE_ERROR_MASK = 17 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIRMASK_SRT_DATAOUT_PERR_MASK = 18 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIRMASK_SRT_OCI_WRITE_DATA_PARITY_MASK = 19 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIRMASK_SRT_OCI_BE_PARITY_ERR_MASK = 20 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIRMASK_SRT_OCI_ADDR_PARITY_ERR_MASK = 21 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIRMASK_GPE0_HALTED_MASK = 22 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIRMASK_GPE1_HALTED_MASK = 23 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIRMASK_GPE2_HALTED_MASK = 24 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIRMASK_GPE3_HALTED_MASK = 25 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIRMASK_EXTERNAL_TRAP_MASK = 26 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIRMASK_PPC405_CORE_RESET_MASK = 27 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIRMASK_PPC405_CHIP_RESET_MASK = 28 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIRMASK_PPC405_SYSTEM_RESET_MASK = 29 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIRMASK_PPC405_DBGMSRWE_MASK = 30 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIRMASK_PPC405_DBGSTOPACK_MASK = 31 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIRMASK_OCB_DB_OCI_TIMEOUT_MASK = 32 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIRMASK_OCB_DB_OCI_READ_DATA_PARITY_MASK = 33 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIRMASK_OCB_DB_OCI_SLAVE_ERROR_MASK = 34 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIRMASK_OCB_PIB_ADDR_PARITY_ERR_MASK = 35 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIRMASK_OCB_DB_PIB_DATA_PARITY_ERR_MASK = 36 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIRMASK_OCB_IDC0_ERROR_MASK = 37 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIRMASK_OCB_IDC1_ERROR_MASK = 38 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIRMASK_OCB_IDC2_ERROR_MASK = 39 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIRMASK_OCB_IDC3_ERROR_MASK = 40 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIRMASK_SRT_FSM_ERR_MASK = 41 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIRMASK_JTAGACC_ERR_MASK = 42 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIRMASK_SPARE_ERR_38_MASK = 43 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIRMASK_C405_ECC_UE_MASK = 44 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIRMASK_C405_ECC_CE_MASK = 45 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIRMASK_C405_OCI_MACHINECHECK_MASK = 46 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIRMASK_SRAM_SPARE_DIRECT_ERROR0_MASK = 47 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIRMASK_SRAM_SPARE_DIRECT_ERROR1_MASK = 48 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIRMASK_SRAM_SPARE_DIRECT_ERROR2_MASK = 49 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIRMASK_SRAM_SPARE_DIRECT_ERROR3_MASK = 50 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIRMASK_GPE0_OCISLV_ERR_MASK = 51 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIRMASK_GPE1_OCISLV_ERR_MASK = 52 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIRMASK_GPE2_OCISLV_ERR_MASK = 53 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIRMASK_GPE3_OCISLV_ERR_MASK = 54 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIRMASK_C405ICU_M_TIMEOUT_MASK = 55 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIRMASK_C405DCU_M_TIMEOUT_MASK = 56 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIRMASK_COMPLEX_FAULT_MASK = 57 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIRMASK_COMPLEX_NOTIFY_MASK = 58 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIRMASK_SPARE_59_61 = 59 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIRMASK_SPARE_59_61_LEN = 3 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIRMASK_FIR_PARITY_ERR_DUP_MASK = 62 ;
+static const uint8_t P9N2_PERV_1_OCC_SCOM_OCCLFIRMASK_FIR_PARITY_ERR_MASK = 63 ;
+
+static const uint8_t P9N2_PERV_1_OPCG_ALIGN_INOP = 0 ;
+static const uint8_t P9N2_PERV_1_OPCG_ALIGN_INOP_LEN = 4 ;
+static const uint8_t P9N2_PERV_1_OPCG_ALIGN_SNOP = 4 ;
+static const uint8_t P9N2_PERV_1_OPCG_ALIGN_SNOP_LEN = 4 ;
+static const uint8_t P9N2_PERV_1_OPCG_ALIGN_ENOP = 8 ;
+static const uint8_t P9N2_PERV_1_OPCG_ALIGN_ENOP_LEN = 4 ;
+static const uint8_t P9N2_PERV_1_OPCG_ALIGN_INOP_WAIT = 12 ;
+static const uint8_t P9N2_PERV_1_OPCG_ALIGN_INOP_WAIT_LEN = 8 ;
+static const uint8_t P9N2_PERV_1_OPCG_ALIGN_SNOP_WAIT = 20 ;
+static const uint8_t P9N2_PERV_1_OPCG_ALIGN_SNOP_WAIT_LEN = 12 ;
+static const uint8_t P9N2_PERV_1_OPCG_ALIGN_ENOP_WAIT = 32 ;
+static const uint8_t P9N2_PERV_1_OPCG_ALIGN_ENOP_WAIT_LEN = 8 ;
+static const uint8_t P9N2_PERV_1_OPCG_ALIGN_INOP_FORCE_SG = 40 ;
+static const uint8_t P9N2_PERV_1_OPCG_ALIGN_SNOP_FORCE_SG = 41 ;
+static const uint8_t P9N2_PERV_1_OPCG_ALIGN_ENOP_FORCE_SG = 42 ;
+static const uint8_t P9N2_PERV_1_OPCG_ALIGN_NO_WAIT_ON_CLK_CMD = 43 ;
+static const uint8_t P9N2_PERV_1_OPCG_ALIGN_SOURCE_SELECT = 44 ;
+static const uint8_t P9N2_PERV_1_OPCG_ALIGN_SOURCE_SELECT_LEN = 2 ;
+static const uint8_t P9N2_PERV_1_OPCG_ALIGN_UNUSED46 = 46 ;
+static const uint8_t P9N2_PERV_1_OPCG_ALIGN_SCAN_RATIO = 47 ;
+static const uint8_t P9N2_PERV_1_OPCG_ALIGN_SCAN_RATIO_LEN = 5 ;
+static const uint8_t P9N2_PERV_1_OPCG_ALIGN_WAIT_CYCLES = 52 ;
+static const uint8_t P9N2_PERV_1_OPCG_ALIGN_WAIT_CYCLES_LEN = 12 ;
+
+static const uint8_t P9N2_PERV_1_OPCG_CAPT1_COUNT = 0 ;
+static const uint8_t P9N2_PERV_1_OPCG_CAPT1_COUNT_LEN = 4 ;
+static const uint8_t P9N2_PERV_1_OPCG_CAPT1_SEQ_01 = 4 ;
+static const uint8_t P9N2_PERV_1_OPCG_CAPT1_SEQ_01_LEN = 5 ;
+static const uint8_t P9N2_PERV_1_OPCG_CAPT1_SEQ_02 = 9 ;
+static const uint8_t P9N2_PERV_1_OPCG_CAPT1_SEQ_02_LEN = 5 ;
+static const uint8_t P9N2_PERV_1_OPCG_CAPT1_SEQ_03 = 14 ;
+static const uint8_t P9N2_PERV_1_OPCG_CAPT1_SEQ_03_LEN = 5 ;
+static const uint8_t P9N2_PERV_1_OPCG_CAPT1_SEQ_04 = 19 ;
+static const uint8_t P9N2_PERV_1_OPCG_CAPT1_SEQ_04_LEN = 5 ;
+static const uint8_t P9N2_PERV_1_OPCG_CAPT1_SEQ_05 = 24 ;
+static const uint8_t P9N2_PERV_1_OPCG_CAPT1_SEQ_05_LEN = 5 ;
+static const uint8_t P9N2_PERV_1_OPCG_CAPT1_SEQ_06 = 29 ;
+static const uint8_t P9N2_PERV_1_OPCG_CAPT1_SEQ_06_LEN = 5 ;
+static const uint8_t P9N2_PERV_1_OPCG_CAPT1_SEQ_07 = 34 ;
+static const uint8_t P9N2_PERV_1_OPCG_CAPT1_SEQ_07_LEN = 5 ;
+static const uint8_t P9N2_PERV_1_OPCG_CAPT1_SEQ_08 = 39 ;
+static const uint8_t P9N2_PERV_1_OPCG_CAPT1_SEQ_08_LEN = 5 ;
+static const uint8_t P9N2_PERV_1_OPCG_CAPT1_SEQ_09 = 44 ;
+static const uint8_t P9N2_PERV_1_OPCG_CAPT1_SEQ_09_LEN = 5 ;
+static const uint8_t P9N2_PERV_1_OPCG_CAPT1_SEQ_10 = 49 ;
+static const uint8_t P9N2_PERV_1_OPCG_CAPT1_SEQ_10_LEN = 5 ;
+static const uint8_t P9N2_PERV_1_OPCG_CAPT1_SEQ_11 = 54 ;
+static const uint8_t P9N2_PERV_1_OPCG_CAPT1_SEQ_11_LEN = 5 ;
+static const uint8_t P9N2_PERV_1_OPCG_CAPT1_SEQ_12 = 59 ;
+static const uint8_t P9N2_PERV_1_OPCG_CAPT1_SEQ_12_LEN = 5 ;
+
+static const uint8_t P9N2_PERV_1_OPCG_CAPT2_UNUSED = 0 ;
+static const uint8_t P9N2_PERV_1_OPCG_CAPT2_UNUSED_LEN = 4 ;
+static const uint8_t P9N2_PERV_1_OPCG_CAPT2_SEQ_13_01EVEN = 4 ;
+static const uint8_t P9N2_PERV_1_OPCG_CAPT2_SEQ_13_01EVEN_LEN = 5 ;
+static const uint8_t P9N2_PERV_1_OPCG_CAPT2_SEQ_14_01ODD = 9 ;
+static const uint8_t P9N2_PERV_1_OPCG_CAPT2_SEQ_14_01ODD_LEN = 5 ;
+static const uint8_t P9N2_PERV_1_OPCG_CAPT2_SEQ_15_02EVEN = 14 ;
+static const uint8_t P9N2_PERV_1_OPCG_CAPT2_SEQ_15_02EVEN_LEN = 5 ;
+static const uint8_t P9N2_PERV_1_OPCG_CAPT2_SEQ_16_02ODD = 19 ;
+static const uint8_t P9N2_PERV_1_OPCG_CAPT2_SEQ_16_02ODD_LEN = 5 ;
+static const uint8_t P9N2_PERV_1_OPCG_CAPT2_SEQ_17_03EVEN = 24 ;
+static const uint8_t P9N2_PERV_1_OPCG_CAPT2_SEQ_17_03EVEN_LEN = 5 ;
+static const uint8_t P9N2_PERV_1_OPCG_CAPT2_SEQ_18_03ODD = 29 ;
+static const uint8_t P9N2_PERV_1_OPCG_CAPT2_SEQ_18_03ODD_LEN = 5 ;
+static const uint8_t P9N2_PERV_1_OPCG_CAPT2_SEQ_19_04EVEN = 34 ;
+static const uint8_t P9N2_PERV_1_OPCG_CAPT2_SEQ_19_04EVEN_LEN = 5 ;
+static const uint8_t P9N2_PERV_1_OPCG_CAPT2_SEQ_20_04ODD = 39 ;
+static const uint8_t P9N2_PERV_1_OPCG_CAPT2_SEQ_20_04ODD_LEN = 5 ;
+static const uint8_t P9N2_PERV_1_OPCG_CAPT2_SEQ_21_05EVEN = 44 ;
+static const uint8_t P9N2_PERV_1_OPCG_CAPT2_SEQ_21_05EVEN_LEN = 5 ;
+static const uint8_t P9N2_PERV_1_OPCG_CAPT2_SEQ_22_05ODD = 49 ;
+static const uint8_t P9N2_PERV_1_OPCG_CAPT2_SEQ_22_05ODD_LEN = 5 ;
+static const uint8_t P9N2_PERV_1_OPCG_CAPT2_SEQ_23_06EVEN = 54 ;
+static const uint8_t P9N2_PERV_1_OPCG_CAPT2_SEQ_23_06EVEN_LEN = 5 ;
+static const uint8_t P9N2_PERV_1_OPCG_CAPT2_SEQ_24_06ODD = 59 ;
+static const uint8_t P9N2_PERV_1_OPCG_CAPT2_SEQ_24_06ODD_LEN = 5 ;
+
+static const uint8_t P9N2_PERV_1_OPCG_CAPT3_UNUSED = 0 ;
+static const uint8_t P9N2_PERV_1_OPCG_CAPT3_UNUSED_LEN = 4 ;
+static const uint8_t P9N2_PERV_1_OPCG_CAPT3_SEQ_07EVEN = 4 ;
+static const uint8_t P9N2_PERV_1_OPCG_CAPT3_SEQ_07EVEN_LEN = 5 ;
+static const uint8_t P9N2_PERV_1_OPCG_CAPT3_SEQ_07ODD = 9 ;
+static const uint8_t P9N2_PERV_1_OPCG_CAPT3_SEQ_07ODD_LEN = 5 ;
+static const uint8_t P9N2_PERV_1_OPCG_CAPT3_SEQ_08EVEN = 14 ;
+static const uint8_t P9N2_PERV_1_OPCG_CAPT3_SEQ_08EVEN_LEN = 5 ;
+static const uint8_t P9N2_PERV_1_OPCG_CAPT3_SEQ_08ODD = 19 ;
+static const uint8_t P9N2_PERV_1_OPCG_CAPT3_SEQ_08ODD_LEN = 5 ;
+static const uint8_t P9N2_PERV_1_OPCG_CAPT3_SEQ_09EVEN = 24 ;
+static const uint8_t P9N2_PERV_1_OPCG_CAPT3_SEQ_09EVEN_LEN = 5 ;
+static const uint8_t P9N2_PERV_1_OPCG_CAPT3_SEQ_09ODD = 29 ;
+static const uint8_t P9N2_PERV_1_OPCG_CAPT3_SEQ_09ODD_LEN = 5 ;
+static const uint8_t P9N2_PERV_1_OPCG_CAPT3_SEQ_10EVEN = 34 ;
+static const uint8_t P9N2_PERV_1_OPCG_CAPT3_SEQ_10EVEN_LEN = 5 ;
+static const uint8_t P9N2_PERV_1_OPCG_CAPT3_SEQ_10ODD = 39 ;
+static const uint8_t P9N2_PERV_1_OPCG_CAPT3_SEQ_10ODD_LEN = 5 ;
+static const uint8_t P9N2_PERV_1_OPCG_CAPT3_SEQ_11EVEN = 44 ;
+static const uint8_t P9N2_PERV_1_OPCG_CAPT3_SEQ_11EVEN_LEN = 5 ;
+static const uint8_t P9N2_PERV_1_OPCG_CAPT3_SEQ_11ODD = 49 ;
+static const uint8_t P9N2_PERV_1_OPCG_CAPT3_SEQ_11ODD_LEN = 5 ;
+static const uint8_t P9N2_PERV_1_OPCG_CAPT3_SEQ_12EVEN = 54 ;
+static const uint8_t P9N2_PERV_1_OPCG_CAPT3_SEQ_12EVEN_LEN = 5 ;
+static const uint8_t P9N2_PERV_1_OPCG_CAPT3_SEQ_12ODD = 59 ;
+static const uint8_t P9N2_PERV_1_OPCG_CAPT3_SEQ_12ODD_LEN = 5 ;
+
+static const uint8_t P9N2_PERV_1_OPCG_REG0_RUNN_MODE = 0 ;
+static const uint8_t P9N2_PERV_1_OPCG_REG0_GO = 1 ;
+static const uint8_t P9N2_PERV_1_OPCG_REG0_RUN_SCAN0 = 2 ;
+static const uint8_t P9N2_PERV_1_OPCG_REG0_SCAN0_MODE = 3 ;
+static const uint8_t P9N2_PERV_1_OPCG_REG0_IN_SLAVE_MODE = 4 ;
+static const uint8_t P9N2_PERV_1_OPCG_REG0_IN_MASTER_MODE = 5 ;
+static const uint8_t P9N2_PERV_1_OPCG_REG0_KEEP_MS_MODE = 6 ;
+static const uint8_t P9N2_PERV_1_OPCG_REG0_TRIGGER_ON_UNIT0_SYNC_LVL = 7 ;
+static const uint8_t P9N2_PERV_1_OPCG_REG0_TRIGGER_ON_UNIT1_SYNC_LVL = 8 ;
+static const uint8_t P9N2_PERV_1_OPCG_REG0_RUN_CHIPLET_SCAN0 = 9 ;
+static const uint8_t P9N2_PERV_1_OPCG_REG0_RUN_CHIPLET_SCAN0_NO_PLL = 10 ;
+static const uint8_t P9N2_PERV_1_OPCG_REG0_RUN_ON_UPDATE_DR = 11 ;
+static const uint8_t P9N2_PERV_1_OPCG_REG0_RUN_ON_CAPTURE_DR = 12 ;
+static const uint8_t P9N2_PERV_1_OPCG_REG0_STOP_RUNN_ON_XSTOP = 13 ;
+static const uint8_t P9N2_PERV_1_OPCG_REG0_STARTS_BIST = 14 ;
+static const uint8_t P9N2_PERV_1_OPCG_REG0_UNUSED1520 = 15 ;
+static const uint8_t P9N2_PERV_1_OPCG_REG0_UNUSED1520_LEN = 6 ;
+static const uint8_t P9N2_PERV_1_OPCG_REG0_LOOP_COUNT = 21 ;
+static const uint8_t P9N2_PERV_1_OPCG_REG0_LOOP_COUNT_LEN = 43 ;
+
+static const uint8_t P9N2_PERV_1_OPCG_REG1_SCAN_COUNT = 0 ;
+static const uint8_t P9N2_PERV_1_OPCG_REG1_SCAN_COUNT_LEN = 12 ;
+static const uint8_t P9N2_PERV_1_OPCG_REG1_MISR_A_VAL = 12 ;
+static const uint8_t P9N2_PERV_1_OPCG_REG1_MISR_A_VAL_LEN = 12 ;
+static const uint8_t P9N2_PERV_1_OPCG_REG1_MISR_B_VAL = 24 ;
+static const uint8_t P9N2_PERV_1_OPCG_REG1_MISR_B_VAL_LEN = 12 ;
+static const uint8_t P9N2_PERV_1_OPCG_REG1_MISR_INIT_WAIT = 36 ;
+static const uint8_t P9N2_PERV_1_OPCG_REG1_MISR_INIT_WAIT_LEN = 12 ;
+static const uint8_t P9N2_PERV_1_OPCG_REG1_SUPPRESS_LAST_RUNN_CLK = 48 ;
+static const uint8_t P9N2_PERV_1_OPCG_REG1_SCAN_CLK_USE_EVEN = 49 ;
+static const uint8_t P9N2_PERV_1_OPCG_REG1_UNUSED2 = 50 ;
+static const uint8_t P9N2_PERV_1_OPCG_REG1_UNUSED2_LEN = 2 ;
+static const uint8_t P9N2_PERV_1_OPCG_REG1_RTIM_THOLD_FORCE = 52 ;
+static const uint8_t P9N2_PERV_1_OPCG_REG1_DISABLE_ARY_CLK_DURING_FILL = 53 ;
+static const uint8_t P9N2_PERV_1_OPCG_REG1_SG_HIGH_DURING_FILL = 54 ;
+static const uint8_t P9N2_PERV_1_OPCG_REG1_LBIST_SKITTER_CTL = 55 ;
+static const uint8_t P9N2_PERV_1_OPCG_REG1_LBIST_SKITTER_CTL_LEN = 2 ;
+static const uint8_t P9N2_PERV_1_OPCG_REG1_MISR_MODE = 57 ;
+static const uint8_t P9N2_PERV_1_OPCG_REG1_INFINITE_MODE = 58 ;
+static const uint8_t P9N2_PERV_1_OPCG_REG1_NSL_FILL_COUNT = 59 ;
+static const uint8_t P9N2_PERV_1_OPCG_REG1_NSL_FILL_COUNT_LEN = 5 ;
+
+static const uint8_t P9N2_PERV_1_OPCG_REG2_GO2 = 0 ;
+static const uint8_t P9N2_PERV_1_OPCG_REG2_PRPG_WEIGHTING = 1 ;
+static const uint8_t P9N2_PERV_1_OPCG_REG2_PRPG_WEIGHTING_LEN = 3 ;
+static const uint8_t P9N2_PERV_1_OPCG_REG2_PRPG_VALUE = 4 ;
+static const uint8_t P9N2_PERV_1_OPCG_REG2_PRPG_VALUE_LEN = 12 ;
+static const uint8_t P9N2_PERV_1_OPCG_REG2_PRPG_A_VAL = 16 ;
+static const uint8_t P9N2_PERV_1_OPCG_REG2_PRPG_A_VAL_LEN = 12 ;
+static const uint8_t P9N2_PERV_1_OPCG_REG2_PRPG_B_VAL = 28 ;
+static const uint8_t P9N2_PERV_1_OPCG_REG2_PRPG_B_VAL_LEN = 12 ;
+static const uint8_t P9N2_PERV_1_OPCG_REG2_PRPG_MODE = 40 ;
+static const uint8_t P9N2_PERV_1_OPCG_REG2_UNUSED41_63 = 41 ;
+static const uint8_t P9N2_PERV_1_OPCG_REG2_UNUSED41_63_LEN = 23 ;
+
+static const uint8_t P9N2_PERV_1_OSCERR_HOLD_CP = 0 ;
+static const uint8_t P9N2_PERV_1_OSCERR_HOLD_CP_LEN = 4 ;
+static const uint8_t P9N2_PERV_1_OSCERR_HOLD_MEM = 4 ;
+static const uint8_t P9N2_PERV_1_OSCERR_HOLD_MEM_LEN = 4 ;
+static const uint8_t P9N2_PERV_1_OSCERR_HOLD_GX = 8 ;
+static const uint8_t P9N2_PERV_1_OSCERR_HOLD_GX_LEN = 4 ;
+static const uint8_t P9N2_PERV_1_OSCERR_HOLD_CPLITE = 12 ;
+static const uint8_t P9N2_PERV_1_OSCERR_HOLD_CPLITE_LEN = 4 ;
+
+static const uint8_t P9N2_PERV_1_OSCERR_MASK_CP = 0 ;
+static const uint8_t P9N2_PERV_1_OSCERR_MASK_CP_LEN = 4 ;
+static const uint8_t P9N2_PERV_1_OSCERR_MASK_MEM = 4 ;
+static const uint8_t P9N2_PERV_1_OSCERR_MASK_MEM_LEN = 4 ;
+static const uint8_t P9N2_PERV_1_OSCERR_MASK_GX = 8 ;
+static const uint8_t P9N2_PERV_1_OSCERR_MASK_GX_LEN = 4 ;
+static const uint8_t P9N2_PERV_1_OSCERR_MASK_CPLITE = 12 ;
+static const uint8_t P9N2_PERV_1_OSCERR_MASK_CPLITE_LEN = 4 ;
+
+static const uint8_t P9N2_PERV_1_OSCERR_MCODE_IN = 0 ;
+static const uint8_t P9N2_PERV_1_OSCERR_MCODE_IN_LEN = 4 ;
+
+static const uint8_t P9N2_PERV_1_PCB_OPCG_GO_OPCGGO = 0 ;
+
+static const uint8_t P9N2_PERV_1_PCB_OPCG_STOP_OPCGSTOP = 0 ;
+
+static const uint8_t P9N2_PERV_PEEK4A0_FSI_A_MST_0_ACTUAL_ERROR = 4 ;
+static const uint8_t P9N2_PERV_PEEK4A0_FSI_A_MST_0_ACTUAL_ERROR_LEN = 4 ;
+static const uint8_t P9N2_PERV_PEEK4A0_FSI_A_MST_0_PORT_0_ENABLE = 8 ;
+static const uint8_t P9N2_PERV_PEEK4A0_FSI_A_MST_0_PORT_1_ENABLE = 12 ;
+static const uint8_t P9N2_PERV_PEEK4A0_FSI_A_MST_0_PORT_2_ENABLE = 16 ;
+static const uint8_t P9N2_PERV_PEEK4A0_FSI_A_MST_0_PORT_3_ENABLE = 20 ;
+static const uint8_t P9N2_PERV_PEEK4A0_FSI_A_MST_0_PORT_4_ENABLE = 24 ;
+static const uint8_t P9N2_PERV_PEEK4A0_FSI_A_MST_0_PORT_5_ENABLE = 28 ;
+
+static const uint8_t P9N2_PERV_PEEK4A4_FSI_A_MST_0_PORT_6_ENABLE = 0 ;
+static const uint8_t P9N2_PERV_PEEK4A4_FSI_A_MST_0_PORT_7_ENABLE = 4 ;
+static const uint8_t P9N2_PERV_PEEK4A4_FSI_A_MST_1_ACTUAL_ERROR = 8 ;
+static const uint8_t P9N2_PERV_PEEK4A4_FSI_A_MST_1_ACTUAL_ERROR_LEN = 4 ;
+static const uint8_t P9N2_PERV_PEEK4A4_FSI_A_MST_1_PORT_0_ENABLE = 12 ;
+static const uint8_t P9N2_PERV_PEEK4A4_FSI_A_MST_1_PORT_1_ENABLE = 16 ;
+static const uint8_t P9N2_PERV_PEEK4A4_FSI_A_MST_1_PORT_2_ENABLE = 20 ;
+static const uint8_t P9N2_PERV_PEEK4A4_FSI_A_MST_1_PORT_3_ENABLE = 24 ;
+static const uint8_t P9N2_PERV_PEEK4A4_FSI_A_MST_1_PORT_4_ENABLE = 28 ;
+
+static const uint8_t P9N2_PERV_PEEK4A8_FSI_B_MST_0_ACTUAL_ERROR = 4 ;
+static const uint8_t P9N2_PERV_PEEK4A8_FSI_B_MST_0_ACTUAL_ERROR_LEN = 4 ;
+static const uint8_t P9N2_PERV_PEEK4A8_FSI_B_MST_0_PORT_0_ENABLE = 8 ;
+static const uint8_t P9N2_PERV_PEEK4A8_FSI_B_MST_0_PORT_1_ENABLE = 12 ;
+static const uint8_t P9N2_PERV_PEEK4A8_FSI_B_MST_0_PORT_2_ENABLE = 16 ;
+static const uint8_t P9N2_PERV_PEEK4A8_FSI_B_MST_0_PORT_3_ENABLE = 20 ;
+static const uint8_t P9N2_PERV_PEEK4A8_FSI_B_MST_0_PORT_4_ENABLE = 24 ;
+static const uint8_t P9N2_PERV_PEEK4A8_FSI_B_MST_0_PORT_5_ENABLE = 28 ;
+
+static const uint8_t P9N2_PERV_PEEK4AC_FSI_B_MST_0_PORT_6_ENABLE = 0 ;
+static const uint8_t P9N2_PERV_PEEK4AC_FSI_B_MST_0_PORT_7_ENABLE = 4 ;
+
+static const uint8_t P9N2_PERV_PERV_CTRL0_TP_CHIPLET_EN_DC = 0 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_TP_PCB_EP_RESET_DC = 1 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_2_RESERVED = 2 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_TP_PLL_TEST_EN_DC = 3 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_TP_PLLRST_DC = 4 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_TP_PLLBYP_DC = 5 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_TP_VITL_SCAN_CLK_DC = 6 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_TP_VITL_SCIN_DC = 7 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_8_RESERVED = 8 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_TP_FLUSH_ALIGN_OVERWRITE = 9 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_TP_ARRAY_WRITE_ASSIST_EN_DC = 10 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_TP_VITL_ACT_DIS_DC = 11 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_TP_VITL_MPW1_DC_N = 12 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_TP_VITL_MPW2_DC_N = 13 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_TP_VITL_MPW3_DC_N = 14 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_TP_VITL_DELAY_LCLKR_DC = 15 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_TP_VITL_CLKOFF_DC = 16 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_TP_FLUSH_SCAN_DC_N = 17 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_TP_FENCE_EN_DC = 18 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_TP_RI_DC_N = 19 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_TP_DI1_DC_N = 20 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_TP_DI2_DC_N = 21 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_22_RESERVED = 22 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_TP_OTP_SCOM_FUSED_CORE_MODE = 23 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_TP_TCPERV_SRAM_ENABLE_DC = 24 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_TP_FENCE_PCB_DC = 25 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_TP_LVLTRANS_FENCE_DC = 26 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_TP_EDRAM_ENABLE_DC = 27 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_TP_I2CM_MVPD0_PROTECT = 28 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_TP_I2CM_MVPD1_PROTECT = 29 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_TP_EX_SINGLE_LPAR_EN_DC = 30 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_TP_PLLCHIPLET_FORCE_OUT_EN_DC = 31 ;
+
+static const uint8_t P9N2_PERV_PERV_CTRL0_CLEAR_TP_CHIPLET_EN_DC = 0 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_CLEAR_TP_PCB_EP_RESET_DC = 1 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_CLEAR_2_RESERVED = 2 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_CLEAR_TP_PLL_TEST_EN_DC = 3 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_CLEAR_TP_PLLRST_DC = 4 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_CLEAR_TP_PLLBYP_DC = 5 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_CLEAR_TP_VITL_SCAN_CLK_DC = 6 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_CLEAR_TP_VITL_SCIN_DC = 7 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_CLEAR_8_RESERVED = 8 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_CLEAR_TP_FLUSH_ALIGN_OVERWRITE = 9 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_CLEAR_TP_ARRAY_WRITE_ASSIST_EN_DC = 10 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_CLEAR_TP_VITL_ACT_DIS_DC = 11 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_CLEAR_TP_VITL_MPW1_DC_N = 12 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_CLEAR_TP_VITL_MPW2_DC_N = 13 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_CLEAR_TP_VITL_MPW3_DC_N = 14 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_CLEAR_TP_VITL_DELAY_LCLKR_DC = 15 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_CLEAR_TP_VITL_CLKOFF_DC = 16 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_CLEAR_TP_FLUSH_SCAN_DC_N = 17 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_CLEAR_TP_FENCE_EN_DC = 18 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_CLEAR_TP_RI_DC_N = 19 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_CLEAR_TP_DI1_DC_N = 20 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_CLEAR_TP_DI2_DC_N = 21 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_CLEAR_22_RESERVED = 22 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_CLEAR_TP_OTP_SCOM_FUSED_CORE_MODE = 23 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_CLEAR_TP_TCPERV_SRAM_ENABLE_DC = 24 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_CLEAR_TP_FENCE_PCB_DC = 25 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_CLEAR_TP_LVLTRANS_FENCE_DC = 26 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_CLEAR_TP_EDRAM_ENABLE_DC = 27 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_CLEAR_TP_I2CM_MVPD0_PROTECT = 28 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_CLEAR_TP_I2CM_MVPD1_PROTECT = 29 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_CLEAR_TP_EX_SINGLE_LPAR_EN_DC = 30 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_CLEAR_TP_PLLCHIPLET_FORCE_OUT_EN_DC = 31 ;
+
+static const uint8_t P9N2_PERV_PERV_CTRL0_COPY_PERV_CTRL0_COPY_REG = 0 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_COPY_PERV_CTRL0_COPY_REG_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_PERV_CTRL0_SET_TP_CHIPLET_EN_DC = 0 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_SET_TP_PCB_EP_RESET_DC = 1 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_SET_2_RESERVED = 2 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_SET_TP_PLL_TEST_EN_DC = 3 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_SET_TP_PLLRST_DC = 4 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_SET_TP_PLLBYP_DC = 5 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_SET_TP_VITL_SCAN_CLK_DC = 6 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_SET_TP_VITL_SCIN_DC = 7 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_SET_8_RESERVED = 8 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_SET_TP_FLUSH_ALIGN_OVERWRITE = 9 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_SET_TP_ARRAY_WRITE_ASSIST_EN_DC = 10 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_SET_TP_VITL_ACT_DIS_DC = 11 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_SET_TP_VITL_MPW1_DC_N = 12 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_SET_TP_VITL_MPW2_DC_N = 13 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_SET_TP_VITL_MPW3_DC_N = 14 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_SET_TP_VITL_DELAY_LCLKR_DC = 15 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_SET_TP_VITL_CLKOFF_DC = 16 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_SET_TP_FLUSH_SCAN_DC_N = 17 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_SET_TP_FENCE_EN_DC = 18 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_SET_TP_RI_DC_N = 19 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_SET_TP_DI1_DC_N = 20 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_SET_TP_DI2_DC_N = 21 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_SET_22_RESERVED = 22 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_SET_TP_OTP_SCOM_FUSED_CORE_MODE = 23 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_SET_TP_TCPERV_SRAM_ENABLE_DC = 24 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_SET_TP_FENCE_PCB_DC = 25 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_SET_TP_LVLTRANS_FENCE_DC = 26 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_SET_TP_EDRAM_ENABLE_DC = 27 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_SET_TP_I2CM_MVPD0_PROTECT = 28 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_SET_TP_I2CM_MVPD1_PROTECT = 29 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_SET_TP_EX_SINGLE_LPAR_EN_DC = 30 ;
+static const uint8_t P9N2_PERV_PERV_CTRL0_SET_TP_PLLCHIPLET_FORCE_OUT_EN_DC = 31 ;
+
+static const uint8_t P9N2_PERV_PERV_CTRL1_TP_CHIPLET_PLL_CLKIN_SEL_DC = 0 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_TP_CHIPLET_CLK_DCCDIV_BYPASS_EN_DC = 1 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_TP_CHIPLET_CLK_PROGDLY_BYPASS_EN_DC = 2 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_3_RESERVED = 3 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_4_RESERVED = 4 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_5_RESERVED = 5 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_6_RESERVED = 6 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_7_RESERVED = 7 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_8_RESERVED = 8 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_9_RESERVED = 9 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_10_RESERVED = 10 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_11_RESERVED = 11 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_12_RESERVED = 12 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_13_RESERVED = 13 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_14_RESERVED = 14 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_15_RESERVED = 15 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_TP_SEC_BUF_DRV_STRENGTH_DC = 16 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_TP_SEC_BUF_DRV_STRENGTH_DC_LEN = 4 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_20_RESERVED = 20 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_21_RESERVED = 21 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_22_RESERVED = 22 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_23_RESERVED = 23 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_24_RESERVED = 24 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_TP_CLK_PULSE_ENABLE_DC = 25 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_TP_CLK_PULSE_MODE_DC = 26 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_TP_CLK_PULSE_MODE_DC_LEN = 2 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_TP_RESCLK_DIS_DC = 28 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_TP_CPM_CAL_SET = 29 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_30_RESERVED = 30 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_TP_PCB_PM_MUX_SEL_DC = 31 ;
+
+static const uint8_t P9N2_PERV_PERV_CTRL1_CLEAR_TP_CHIPLET_PLL_CLKIN_SEL_DC = 0 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_CLEAR_TP_CHIPLET_CLK_DCCDIV_BYPASS_EN_DC = 1 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_CLEAR_TP_CHIPLET_CLK_PROGDLY_BYPASS_EN_DC = 2 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_CLEAR_3_RESERVED = 3 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_CLEAR_4_RESERVED = 4 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_CLEAR_5_RESERVED = 5 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_CLEAR_6_RESERVED = 6 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_CLEAR_7_RESERVED = 7 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_CLEAR_8_RESERVED = 8 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_CLEAR_9_RESERVED = 9 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_CLEAR_10_RESERVED = 10 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_CLEAR_11_RESERVED = 11 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_CLEAR_12_RESERVED = 12 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_CLEAR_13_RESERVED = 13 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_CLEAR_14_RESERVED = 14 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_CLEAR_15_RESERVED = 15 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_CLEAR_TP_SEC_BUF_DRV_STRENGTH_DC = 16 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_CLEAR_TP_SEC_BUF_DRV_STRENGTH_DC_LEN = 4 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_CLEAR_20_RESERVED = 20 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_CLEAR_21_RESERVED = 21 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_CLEAR_22_RESERVED = 22 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_CLEAR_23_RESERVED = 23 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_CLEAR_24_RESERVED = 24 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_CLEAR_TP_CLK_PULSE_ENABLE_DC = 25 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_CLEAR_TP_CLK_PULSE_MODE_DC = 26 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_CLEAR_TP_CLK_PULSE_MODE_DC_LEN = 2 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_CLEAR_TP_RESCLK_DIS_DC = 28 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_CLEAR_TP_CPM_CAL_SET = 29 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_CLEAR_30_RESERVED = 30 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_CLEAR_TP_PCB_PM_MUX_SEL_DC = 31 ;
+
+static const uint8_t P9N2_PERV_PERV_CTRL1_COPY_PERV_CTRL1_COPY_REG = 0 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_COPY_PERV_CTRL1_COPY_REG_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_PERV_CTRL1_SET_TP_CHIPLET_PLL_CLKIN_SEL_DC = 0 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_SET_TP_CHIPLET_CLK_DCCDIV_BYPASS_EN_DC = 1 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_SET_TP_CHIPLET_CLK_PROGDLY_BYPASS_EN_DC = 2 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_SET_3_RESERVED = 3 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_SET_4_RESERVED = 4 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_SET_5_RESERVED = 5 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_SET_6_RESERVED = 6 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_SET_7_RESERVED = 7 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_SET_8_RESERVED = 8 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_SET_9_RESERVED = 9 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_SET_10_RESERVED = 10 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_SET_11_RESERVED = 11 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_SET_12_RESERVED = 12 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_SET_13_RESERVED = 13 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_SET_14_RESERVED = 14 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_SET_15_RESERVED = 15 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_SET_TP_SEC_BUF_DRV_STRENGTH_DC = 16 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_SET_TP_SEC_BUF_DRV_STRENGTH_DC_LEN = 4 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_SET_20_RESERVED = 20 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_SET_21_RESERVED = 21 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_SET_22_RESERVED = 22 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_SET_23_RESERVED = 23 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_SET_24_RESERVED = 24 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_SET_TP_CLK_PULSE_ENABLE_DC = 25 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_SET_TP_CLK_PULSE_MODE_DC = 26 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_SET_TP_CLK_PULSE_MODE_DC_LEN = 2 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_SET_TP_RESCLK_DIS_DC = 28 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_SET_TP_CPM_CAL = 29 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_SET_30_RESERVED = 30 ;
+static const uint8_t P9N2_PERV_PERV_CTRL1_SET_TP_PCB_PM_MUX_SEL_DC = 31 ;
+
+static const uint8_t P9N2_PERV_1_PLL_LOCK_REG_LOCK = 0 ;
+static const uint8_t P9N2_PERV_1_PLL_LOCK_REG_LOCK_LEN = 4 ;
+
+static const uint8_t P9N2_PERV_1_PRE_COUNTER_REG_COUNTER = 0 ;
+static const uint8_t P9N2_PERV_1_PRE_COUNTER_REG_COUNTER_LEN = 8 ;
+
+static const uint8_t P9N2_PERV_1_PRIMARY_ADDRESS_REG_PRIMARY_ADDRESS = 0 ;
+static const uint8_t P9N2_PERV_1_PRIMARY_ADDRESS_REG_PRIMARY_ADDRESS_LEN = 6 ;
+
+static const uint8_t P9N2_PERV_1_PROTECT_MODE_REG_READ_ENABLE = 0 ;
+static const uint8_t P9N2_PERV_1_PROTECT_MODE_REG_WRITE_ENABLE = 1 ;
+
+static const uint8_t P9N2_PERV_1_PSCOM_ERROR_MASK_PCB_WDATA_PARITY = 0 ;
+static const uint8_t P9N2_PERV_1_PSCOM_ERROR_MASK_PCB_ADDRESS_PARITY = 1 ;
+static const uint8_t P9N2_PERV_1_PSCOM_ERROR_MASK_DL_RETURN_WDATA_PARITY = 2 ;
+static const uint8_t P9N2_PERV_1_PSCOM_ERROR_MASK_DL_RETURN_P0 = 3 ;
+static const uint8_t P9N2_PERV_1_PSCOM_ERROR_MASK_UL_RDATA_PARITY = 4 ;
+static const uint8_t P9N2_PERV_1_PSCOM_ERROR_MASK_UL_P0 = 5 ;
+static const uint8_t P9N2_PERV_1_PSCOM_ERROR_MASK_PARITY_ON_INTERFACE_MACHINE = 6 ;
+static const uint8_t P9N2_PERV_1_PSCOM_ERROR_MASK_PARITY_ON_P2S_MACHINE = 7 ;
+static const uint8_t P9N2_PERV_1_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 8 ;
+static const uint8_t P9N2_PERV_1_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 9 ;
+static const uint8_t P9N2_PERV_1_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 10 ;
+static const uint8_t P9N2_PERV_1_PSCOM_ERROR_MASK_PARALLEL_WRITE_NVLD = 11 ;
+static const uint8_t P9N2_PERV_1_PSCOM_ERROR_MASK_PARALLEL_READ_NVLD = 12 ;
+static const uint8_t P9N2_PERV_1_PSCOM_ERROR_MASK_PARALLEL_ADDR_INVALID = 13 ;
+static const uint8_t P9N2_PERV_1_PSCOM_ERROR_MASK_PCB_COMMAND_PARITY = 14 ;
+static const uint8_t P9N2_PERV_1_PSCOM_ERROR_MASK_GENERAL_TIMEOUT = 15 ;
+static const uint8_t P9N2_PERV_1_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 16 ;
+static const uint8_t P9N2_PERV_1_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 17 ;
+
+static const uint8_t P9N2_PERV_1_PSCOM_MODE_REG_ABORT_ON_PCB_ADDR_PARITY_ERROR = 0 ;
+static const uint8_t P9N2_PERV_1_PSCOM_MODE_REG_ABORT_ON_PCB_WDATA_PARITY_ERROR = 1 ;
+static const uint8_t P9N2_PERV_1_PSCOM_MODE_REG_UNUSED_BIT_2 = 2 ;
+static const uint8_t P9N2_PERV_1_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR = 3 ;
+static const uint8_t P9N2_PERV_1_PSCOM_MODE_REG_WATCHDOG_ENABLE = 4 ;
+static const uint8_t P9N2_PERV_1_PSCOM_MODE_REG_SCOM_HANG_LIMIT = 5 ;
+static const uint8_t P9N2_PERV_1_PSCOM_MODE_REG_SCOM_HANG_LIMIT_LEN = 2 ;
+static const uint8_t P9N2_PERV_1_PSCOM_MODE_REG_FORCE_ALL_RINGS = 7 ;
+static const uint8_t P9N2_PERV_1_PSCOM_MODE_REG_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE = 8 ;
+static const uint8_t P9N2_PERV_1_PSCOM_MODE_REG_RESERVED_LT = 9 ;
+static const uint8_t P9N2_PERV_1_PSCOM_MODE_REG_RESERVED_LT_LEN = 3 ;
+
+static const uint8_t P9N2_PERV_1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_WDATA_PARITY = 0 ;
+static const uint8_t P9N2_PERV_1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_ADDRESS_PARITY = 1 ;
+static const uint8_t P9N2_PERV_1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_WDATA_PARITY = 2 ;
+static const uint8_t P9N2_PERV_1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_P0 = 3 ;
+static const uint8_t P9N2_PERV_1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_RDATA_PARITY = 4 ;
+static const uint8_t P9N2_PERV_1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_P0 = 5 ;
+static const uint8_t P9N2_PERV_1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE = 6 ;
+static const uint8_t P9N2_PERV_1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_P2S_MACHINE = 7 ;
+static const uint8_t P9N2_PERV_1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 8 ;
+static const uint8_t P9N2_PERV_1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 9 ;
+static const uint8_t P9N2_PERV_1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 10 ;
+static const uint8_t P9N2_PERV_1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_WRITE_NVLD = 11 ;
+static const uint8_t P9N2_PERV_1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_READ_NVLD = 12 ;
+static const uint8_t P9N2_PERV_1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_ADDR_INVALID = 13 ;
+static const uint8_t P9N2_PERV_1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_COMMAND_PARITY = 14 ;
+static const uint8_t P9N2_PERV_1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_GENERAL_TIMEOUT = 15 ;
+static const uint8_t P9N2_PERV_1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 16 ;
+static const uint8_t P9N2_PERV_1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 17 ;
+static const uint8_t P9N2_PERV_1_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_WDATA_PARITY = 18 ;
+static const uint8_t P9N2_PERV_1_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_ADDRESS_PARITY = 19 ;
+static const uint8_t P9N2_PERV_1_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_WDATA_PARITY = 20 ;
+static const uint8_t P9N2_PERV_1_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_P0 = 21 ;
+static const uint8_t P9N2_PERV_1_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_RDATA_PARITY = 22 ;
+static const uint8_t P9N2_PERV_1_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_P0 = 23 ;
+static const uint8_t P9N2_PERV_1_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_INTERFACE_MACHINE = 24 ;
+static const uint8_t P9N2_PERV_1_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_P2S_MACHINE = 25 ;
+static const uint8_t P9N2_PERV_1_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 26 ;
+static const uint8_t P9N2_PERV_1_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 27 ;
+static const uint8_t P9N2_PERV_1_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 28 ;
+static const uint8_t P9N2_PERV_1_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_WRITE_NVLD = 29 ;
+static const uint8_t P9N2_PERV_1_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_READ_NVLD = 30 ;
+static const uint8_t P9N2_PERV_1_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_ADDR_INVALID = 31 ;
+static const uint8_t P9N2_PERV_1_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_COMMAND_PARITY = 32 ;
+static const uint8_t P9N2_PERV_1_PSCOM_STATUS_ERROR_REG_TRAPPED_GENERAL_TIMEOUT = 33 ;
+static const uint8_t P9N2_PERV_1_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 34 ;
+static const uint8_t P9N2_PERV_1_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 35 ;
+
+static const uint8_t P9N2_PERV_FSISHIFT_READ_BUFFER_REG = 0 ;
+static const uint8_t P9N2_PERV_FSISHIFT_READ_BUFFER_REG_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_1_RECOV_INTERRUPT_REG_RECOV = 0 ;
+
+static const uint8_t P9N2_PERV_REC_ACK_REG_RECEIVE_ACKNOWLEDGE_REGISTER = 0 ;
+static const uint8_t P9N2_PERV_REC_ACK_REG_RECEIVE_ACKNOWLEDGE_REGISTER_LEN = 64 ;
+
+static const uint8_t P9N2_PERV_REC_ERR_REG0_MASTER_RESPONSE_BIT = 0 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG0_MASTER_ERROR_CODE = 1 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG0_MASTER_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG0_SLAVE1_RESPONSE_BIT = 4 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG0_SLAVE1_ERROR_CODE = 5 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG0_SLAVE1_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG0_SLAVE2_RESPONSE_BIT = 8 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG0_SLAVE2_ERROR_CODE = 9 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG0_SLAVE2_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG0_SLAVE3_RESPONSE_BIT = 12 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG0_SLAVE3_ERROR_CODE = 13 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG0_SLAVE3_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG0_SLAVE4_RESPONSE_BIT = 16 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG0_SLAVE4_ERROR_CODE = 17 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG0_SLAVE4_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG0_SLAVE5_RESPONSE_BIT = 20 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG0_SLAVE5_ERROR_CODE = 21 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG0_SLAVE5_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG0_SLAVE6_RESPONSE_BIT = 24 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG0_SLAVE6_ERROR_CODE = 25 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG0_SLAVE6_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG0_SLAVE7_RESPONSE_BIT = 28 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG0_SLAVE7_ERROR_CODE = 29 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG0_SLAVE7_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG0_SLAVE8_RESPONSE_BIT = 32 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG0_SLAVE8_ERROR_CODE = 33 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG0_SLAVE8_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG0_SLAVE9_RESPONSE_BIT = 36 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG0_SLAVE9_ERROR_CODE = 37 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG0_SLAVE9_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG0_SLAVE10_RESPONSE_BIT = 40 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG0_SLAVE10_ERROR_CODE = 41 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG0_SLAVE10_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG0_SLAVE11_RESPONSE_BIT = 44 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG0_SLAVE11_ERROR_CODE = 45 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG0_SLAVE11_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG0_SLAVE12_RESPONSE_BIT = 48 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG0_SLAVE12_ERROR_CODE = 49 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG0_SLAVE12_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG0_SLAVE13_RESPONSE_BIT = 52 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG0_SLAVE13_ERROR_CODE = 53 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG0_SLAVE13_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG0_SLAVE14_RESPONSE_BIT = 56 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG0_SLAVE14_ERROR_CODE = 57 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG0_SLAVE14_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG0_SLAVE15_RESPONSE_BIT = 60 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG0_SLAVE15_ERROR_CODE = 61 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG0_SLAVE15_ERROR_CODE_LEN = 3 ;
+
+static const uint8_t P9N2_PERV_REC_ERR_REG1_SLAVE16_RESPONSE_BIT = 0 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG1_SLAVE16_ERROR_CODE = 1 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG1_SLAVE16_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG1_SLAVE17_RESPONSE_BIT = 4 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG1_SLAVE17_ERROR_CODE = 5 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG1_SLAVE17_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG1_SLAVE18_RESPONSE_BIT = 8 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG1_SLAVE18_ERROR_CODE = 9 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG1_SLAVE18_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG1_SLAVE19_RESPONSE_BIT = 12 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG1_SLAVE19_ERROR_CODE = 13 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG1_SLAVE19_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG1_SLAVE20_RESPONSE_BIT = 16 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG1_SLAVE20_ERROR_CODE = 17 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG1_SLAVE20_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG1_SLAVE21_RESPONSE_BIT = 20 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG1_SLAVE21_ERROR_CODE = 21 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG1_SLAVE21_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG1_SLAVE22_RESPONSE_BIT = 24 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG1_SLAVE22_ERROR_CODE = 25 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG1_SLAVE22_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG1_SLAVE23_RESPONSE_BIT = 28 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG1_SLAVE23_ERROR_CODE = 29 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG1_SLAVE23_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG1_SLAVE24_RESPONSE_BIT = 32 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG1_SLAVE24_ERROR_CODE = 33 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG1_SLAVE24_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG1_SLAVE25_RESPONSE_BIT = 36 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG1_SLAVE25_ERROR_CODE = 37 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG1_SLAVE25_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG1_SLAVE26_RESPONSE_BIT = 40 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG1_SLAVE26_ERROR_CODE = 41 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG1_SLAVE26_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG1_SLAVE27_RESPONSE_BIT = 44 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG1_SLAVE27_ERROR_CODE = 45 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG1_SLAVE27_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG1_SLAVE28_RESPONSE_BIT = 48 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG1_SLAVE28_ERROR_CODE = 49 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG1_SLAVE28_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG1_SLAVE29_RESPONSE_BIT = 52 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG1_SLAVE29_ERROR_CODE = 53 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG1_SLAVE29_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG1_SLAVE30_RESPONSE_BIT = 56 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG1_SLAVE30_ERROR_CODE = 57 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG1_SLAVE30_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG1_SLAVE31_RESPONSE_BIT = 60 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG1_SLAVE31_ERROR_CODE = 61 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG1_SLAVE31_ERROR_CODE_LEN = 3 ;
+
+static const uint8_t P9N2_PERV_REC_ERR_REG2_SLAVE32_RESPONSE_BIT = 0 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG2_SLAVE32_ERROR_CODE = 1 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG2_SLAVE32_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG2_SLAVE33_RESPONSE_BIT = 4 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG2_SLAVE33_ERROR_CODE = 5 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG2_SLAVE33_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG2_SLAVE34_RESPONSE_BIT = 8 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG2_SLAVE34_ERROR_CODE = 9 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG2_SLAVE34_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG2_SLAVE35_RESPONSE_BIT = 12 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG2_SLAVE35_ERROR_CODE = 13 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG2_SLAVE35_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG2_SLAVE36_RESPONSE_BIT = 16 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG2_SLAVE36_ERROR_CODE = 17 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG2_SLAVE36_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG2_SLAVE37_RESPONSE_BIT = 20 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG2_SLAVE37_ERROR_CODE = 21 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG2_SLAVE37_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG2_SLAVE38_RESPONSE_BIT = 24 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG2_SLAVE38_ERROR_CODE = 25 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG2_SLAVE38_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG2_SLAVE39_RESPONSE_BIT = 28 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG2_SLAVE39_ERROR_CODE = 29 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG2_SLAVE39_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG2_SLAVE40_RESPONSE_BIT = 32 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG2_SLAVE40_ERROR_CODE = 33 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG2_SLAVE40_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG2_SLAVE41_RESPONSE_BIT = 36 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG2_SLAVE41_ERROR_CODE = 37 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG2_SLAVE41_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG2_SLAVE42_RESPONSE_BIT = 40 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG2_SLAVE42_ERROR_CODE = 41 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG2_SLAVE42_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG2_SLAVE43_RESPONSE_BIT = 44 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG2_SLAVE43_ERROR_CODE = 45 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG2_SLAVE43_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG2_SLAVE44_RESPONSE_BIT = 48 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG2_SLAVE44_ERROR_CODE = 49 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG2_SLAVE44_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG2_SLAVE45_RESPONSE_BIT = 52 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG2_SLAVE45_ERROR_CODE = 53 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG2_SLAVE45_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG2_SLAVE46_RESPONSE_BIT = 56 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG2_SLAVE46_ERROR_CODE = 57 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG2_SLAVE46_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG2_SLAVE47_RESPONSE_BIT = 60 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG2_SLAVE47_ERROR_CODE = 61 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG2_SLAVE47_ERROR_CODE_LEN = 3 ;
+
+static const uint8_t P9N2_PERV_REC_ERR_REG3_SLAVE48_RESPONSE_BIT = 0 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG3_SLAVE48_ERROR_CODE = 1 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG3_SLAVE48_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG3_SLAVE49_RESPONSE_BIT = 4 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG3_SLAVE49_ERROR_CODE = 5 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG3_SLAVE49_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG3_SLAVE50_RESPONSE_BIT = 8 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG3_SLAVE50_ERROR_CODE = 9 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG3_SLAVE50_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG3_SLAVE51_RESPONSE_BIT = 12 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG3_SLAVE51_ERROR_CODE = 13 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG3_SLAVE51_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG3_SLAVE52_RESPONSE_BIT = 16 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG3_SLAVE52_ERROR_CODE = 17 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG3_SLAVE52_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG3_SLAVE53_RESPONSE_BIT = 20 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG3_SLAVE53_ERROR_CODE = 21 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG3_SLAVE53_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG3_SLAVE54_RESPONSE_BIT = 24 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG3_SLAVE54_ERROR_CODE = 25 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG3_SLAVE54_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG3_SLAVE55_RESPONSE_BIT = 28 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG3_SLAVE55_ERROR_CODE = 29 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG3_SLAVE55_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG3_SLAVE56_RESPONSE_BIT = 32 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG3_SLAVE56_ERROR_CODE = 33 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG3_SLAVE56_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG3_SLAVE57_RESPONSE_BIT = 36 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG3_SLAVE57_ERROR_CODE = 37 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG3_SLAVE57_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG3_SLAVE58_RESPONSE_BIT = 40 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG3_SLAVE58_ERROR_CODE = 41 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG3_SLAVE58_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG3_SLAVE59_RESPONSE_BIT = 44 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG3_SLAVE59_ERROR_CODE = 45 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG3_SLAVE59_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG3_SLAVE60_RESPONSE_BIT = 48 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG3_SLAVE60_ERROR_CODE = 49 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG3_SLAVE60_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG3_SLAVE61_RESPONSE_BIT = 52 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG3_SLAVE61_ERROR_CODE = 53 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG3_SLAVE61_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG3_SLAVE62_RESPONSE_BIT = 56 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG3_SLAVE62_ERROR_CODE = 57 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG3_SLAVE62_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG3_SLAVE63_RESPONSE_BIT = 60 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG3_SLAVE63_ERROR_CODE = 61 ;
+static const uint8_t P9N2_PERV_REC_ERR_REG3_SLAVE63_ERROR_CODE_LEN = 3 ;
+
+static const uint8_t P9N2_PERV_RESET_REG_PCB = 0 ;
+static const uint8_t P9N2_PERV_RESET_REG_ENDPOINTS = 1 ;
+static const uint8_t P9N2_PERV_RESET_REG_TIMEOUT_EN = 2 ;
+
+static const uint8_t P9N2_PERV_FSII2C_RESIDUAL_FRONT_END_BACK_END_LENGTH_A_RESID_FE_LEN_0 = 0 ;
+static const uint8_t P9N2_PERV_FSII2C_RESIDUAL_FRONT_END_BACK_END_LENGTH_A_RESID_FE_LEN_0_LEN = 16 ;
+
+static const uint8_t P9N2_PERV_1_RFIR_IN0 = 0 ;
+static const uint8_t P9N2_PERV_1_RFIR_LFIR_RECOV_ERR = 1 ;
+static const uint8_t P9N2_PERV_1_RFIR_IN4 = 2 ;
+static const uint8_t P9N2_PERV_1_RFIR_IN5 = 3 ;
+static const uint8_t P9N2_PERV_1_RFIR_IN6 = 4 ;
+static const uint8_t P9N2_PERV_1_RFIR_IN7 = 5 ;
+static const uint8_t P9N2_PERV_1_RFIR_IN8 = 6 ;
+static const uint8_t P9N2_PERV_1_RFIR_IN9 = 7 ;
+static const uint8_t P9N2_PERV_1_RFIR_IN10 = 8 ;
+static const uint8_t P9N2_PERV_1_RFIR_IN11 = 9 ;
+static const uint8_t P9N2_PERV_1_RFIR_IN12 = 10 ;
+static const uint8_t P9N2_PERV_1_RFIR_IN13 = 11 ;
+static const uint8_t P9N2_PERV_1_RFIR_IN14 = 12 ;
+static const uint8_t P9N2_PERV_1_RFIR_IN15 = 13 ;
+static const uint8_t P9N2_PERV_1_RFIR_IN16 = 14 ;
+static const uint8_t P9N2_PERV_1_RFIR_IN17 = 15 ;
+static const uint8_t P9N2_PERV_1_RFIR_IN18 = 16 ;
+static const uint8_t P9N2_PERV_1_RFIR_IN19 = 17 ;
+static const uint8_t P9N2_PERV_1_RFIR_IN20 = 18 ;
+static const uint8_t P9N2_PERV_1_RFIR_IN21 = 19 ;
+static const uint8_t P9N2_PERV_1_RFIR_IN21_LEN = 5 ;
+
+static const uint8_t P9N2_PERV_1_RING_FENCE_MASK_LATCH_REG_ENABLE = 1 ;
+static const uint8_t P9N2_PERV_1_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN = 15 ;
+
+static const uint8_t P9N2_PERV_ROOT_CTRL0_FENCE0_DC = 0 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_TPFSI_TP_FENCE_VTLIO_DC = 1 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_TPFSI_TPI2C_BUS_FENCE_DC = 2 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_TPCFSI_OPB_SW0_FENCE_DC = 3 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_TPCFSI_OPB_SW0_FENCE_DC_LEN = 3 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_TPCFSI_OPB_SW1_FENCE_DC = 6 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_TPCFSI_OPB_SW1_FENCE_DC_LEN = 2 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_FENCE1_DC = 8 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_FENCE2_DC = 9 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_FENCE3_DC = 10 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_FENCE4_DC = 11 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_FENCE5_DC = 12 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_FENCE6_DC = 13 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_SPARE_FENCE_CONTROL = 14 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_VDD2VIO_LVL_FENCE_DC = 15 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_PIB2PCB_DC = 16 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_OOB_MUX = 17 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_18_SPARE_MUX_CONTROL = 18 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_19_SPARE_MUX_CONTROL = 19 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_FSI_CC_VSB_CBS_REQ = 20 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_FSI_CC_VSB_CBS_CMD = 21 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_FSI_CC_VSB_CBS_CMD_LEN = 3 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_24_SPARE_CBS_CONTROL = 24 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_25_SPARE_CBS_CONTROL = 25 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_26_SPARE_CBS_CONTROL = 26 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_27_SPARE_CBS_CONTROL = 27 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_28_SPARE_RESET = 28 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_29_SPARE_RESET = 29 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_PCB_RESET_DC = 30 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_GLOBAL_EP_RESET_DC = 31 ;
+
+static const uint8_t P9N2_PERV_ROOT_CTRL0_CLEAR_FENCE0_DC = 0 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_CLEAR_TPFSI_TP_FENCE_VTLIO_DC = 1 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_CLEAR_TPFSI_TPI2C_BUS_FENCE_DC = 2 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_CLEAR_TPCFSI_OPB_SW0_FENCE_DC = 3 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_CLEAR_TPCFSI_OPB_SW0_FENCE_DC_LEN = 3 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_CLEAR_TPCFSI_OPB_SW1_FENCE_DC = 6 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_CLEAR_TPCFSI_OPB_SW1_FENCE_DC_LEN = 2 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_CLEAR_FENCE1_DC = 8 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_CLEAR_FENCE2_DC = 9 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_CLEAR_FENCE3_DC = 10 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_CLEAR_FENCE4_DC = 11 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_CLEAR_FENCE5_DC = 12 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_CLEAR_FENCE6_DC = 13 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_CLEAR_SPARE_FENCE_CONTROL = 14 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_CLEAR_VDD2VIO_LVL_FENCE_DC = 15 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_CLEAR_PIB2PCB_DC = 16 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_CLEAR_OOB_MUX = 17 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_CLEAR_18_SPARE_MUX_CONTROL = 18 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_CLEAR_19_SPARE_MUX_CONTROL = 19 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_CLEAR_FSI_CC_VSB_CBS_REQ = 20 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_CLEAR_FSI_CC_VSB_CBS_CMD = 21 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_CLEAR_FSI_CC_VSB_CBS_CMD_LEN = 3 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_CLEAR_24_SPARE_CBS_CONTROL = 24 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_CLEAR_25_SPARE_CBS_CONTROL = 25 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_CLEAR_26_SPARE_CBS_CONTROL = 26 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_CLEAR_27_SPARE_CBS_CONTROL = 27 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_CLEAR_28_SPARE_RESET = 28 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_CLEAR_29_SPARE_RESET = 29 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_CLEAR_PCB_RESET_DC = 30 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_CLEAR_GLOBAL_EP_RESET_DC = 31 ;
+
+static const uint8_t P9N2_PERV_ROOT_CTRL0_COPY_ROOT_CTRL0_COPY_REG = 0 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_COPY_ROOT_CTRL0_COPY_REG_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_ROOT_CTRL0_SET_FENCE0_DC = 0 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_SET_TPFSI_TP_FENCE_VTLIO_DC = 1 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_SET_TPFSI_TPI2C_BUS_FENCE_DC = 2 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_SET_TPCFSI_OPB_SW0_FENCE_DC = 3 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_SET_TPCFSI_OPB_SW0_FENCE_DC_LEN = 3 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_SET_TPCFSI_OPB_SW1_FENCE_DC = 6 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_SET_TPCFSI_OPB_SW1_FENCE_DC_LEN = 2 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_SET_FENCE1_DC = 8 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_SET_FENCE2_DC = 9 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_SET_FENCE3_DC = 10 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_SET_FENCE4_DC = 11 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_SET_FENCE5_DC = 12 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_SET_FENCE6_DC = 13 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_SET_SPARE_FENCE_CONTROL = 14 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_SET_VDD2VIO_LVL_FENCE_DC = 15 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_SET_PIB2PCB_DC = 16 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_SET_OOB_MUX = 17 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_SET_18_SPARE_MUX_CONTROL = 18 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_SET_19_SPARE_MUX_CONTROL = 19 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_SET_FSI_CC_VSB_CBS_REQ = 20 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_SET_FSI_CC_VSB_CBS_CMD = 21 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_SET_FSI_CC_VSB_CBS_CMD_LEN = 3 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_SET_24_SPARE_CBS_CONTROL = 24 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_SET_25_SPARE_CBS_CONTROL = 25 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_SET_26_SPARE_CBS_CONTROL = 26 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_SET_27_SPARE_CBS_CONTROL = 27 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_SET_28_SPARE_RESET = 28 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_SET_29_SPARE_RESET = 29 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_SET_PCB_RESET_DC = 30 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL0_SET_GLOBAL_EP_RESET_DC = 31 ;
+
+static const uint8_t P9N2_PERV_ROOT_CTRL1_TP_PROBE0_SEL_DC = 0 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_TP_PROBE0_SEL_DC_LEN = 4 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_TP_PROBE1_SEL_DC = 4 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_TP_PROBE1_SEL_DC_LEN = 4 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_TP_PROBE_MESH_SEL_DC = 8 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_TP_PROBE_DRV_EN_DC = 9 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_TP_PROBE_HIGHDRIVE_DC = 10 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_TP_FSI_PROBE_SEL_DC = 11 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_TP_FSI_PROBE_SEL_DC_LEN = 2 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_13_SPARE_PROBE = 13 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_14_SPARE_PROBE = 14 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_15_SPARE_PROBE = 15 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_TP_IDDQ_DC = 16 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_SPARE_RI_CONTROL = 17 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_SPARE_DI_CONTROL = 18 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_TP_RI_DC_B = 19 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_TP_DI1_DC_B = 20 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_TP_DI2_DC_B = 21 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_22_SPARE_TEST = 22 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_23_SPARE_TEST = 23 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_TP_TEST_BURNIN_MODE_DC = 24 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_TPFSI_ARRAY_SET_VBL_TO_VDD_DC = 25 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_TPFSI_TP_LOWFREQTEST_REFCLK_DC_UNUSED = 26 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_TP_GLBCK_MEM_TESTCLK_SEL_DC = 27 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_28_SPARE_TEST_CONTROL = 28 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_29_SPARE_TEST_CONTROL = 29 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_30_SPARE_TEST_CONTROL = 30 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_31_SPARE_TEST_CONTROL = 31 ;
+
+static const uint8_t P9N2_PERV_ROOT_CTRL1_CLEAR_TP_PROBE0_SEL_DC = 0 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_CLEAR_TP_PROBE0_SEL_DC_LEN = 4 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_CLEAR_TP_PROBE1_SEL_DC = 4 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_CLEAR_TP_PROBE1_SEL_DC_LEN = 4 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_CLEAR_TP_PROBE_MESH_SEL_DC = 8 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_CLEAR_TP_PROBE_DRV_EN_DC = 9 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_CLEAR_TP_PROBE_HIGHDRIVE_DC = 10 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_CLEAR_TP_FSI_PROBE_SEL_DC = 11 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_CLEAR_TP_FSI_PROBE_SEL_DC_LEN = 2 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_CLEAR_13_SPARE_PROBE = 13 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_CLEAR_14_SPARE_PROBE = 14 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_CLEAR_15_SPARE_PROBE = 15 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_CLEAR_TP_IDDQ_DC = 16 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_CLEAR_SPARE_RI_CONTROL = 17 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_CLEAR_SPARE_DI_CONTROL = 18 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_CLEAR_TP_RI_DC_B = 19 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_CLEAR_TP_DI1_DC_B = 20 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_CLEAR_TP_DI2_DC_B = 21 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_CLEAR_22_SPARE_TEST = 22 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_CLEAR_23_SPARE_TEST = 23 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_CLEAR_TP_TEST_BURNIN_MODE_DC = 24 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_CLEAR_TPFSI_ARRAY_SET_VBL_TO_VDD_DC = 25 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_CLEAR_TPFSI_TP_LOWFREQTEST_REFCLK_DC_UNUSED = 26 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_CLEAR_TP_GLBCK_MEM_TESTCLK_SEL_DC = 27 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_CLEAR_28_SPARE_TEST_CONTROL = 28 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_CLEAR_29_SPARE_TEST_CONTROL = 29 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_CLEAR_30_SPARE_TEST_CONTROL = 30 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_CLEAR_31_SPARE_TEST_CONTROL = 31 ;
+
+static const uint8_t P9N2_PERV_ROOT_CTRL1_COPY_ROOT_CTRL1_COPY_REG = 0 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_COPY_ROOT_CTRL1_COPY_REG_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_ROOT_CTRL1_SET_TP_PROBE0_SEL_DC = 0 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_SET_TP_PROBE0_SEL_DC_LEN = 4 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_SET_TP_PROBE1_SEL_DC = 4 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_SET_TP_PROBE1_SEL_DC_LEN = 4 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_SET_TP_PROBE_MESH_SEL_DC = 8 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_SET_TP_PROBE_DRV_EN_DC = 9 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_SET_TP_PROBE_HIGHDRIVE_DC = 10 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_SET_TP_FSI_PROBE_SEL_DC = 11 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_SET_TP_FSI_PROBE_SEL_DC_LEN = 2 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_SET_13_SPARE_PROBE = 13 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_SET_14_SPARE_PROBE = 14 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_SET_15_SPARE_PROBE = 15 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_SET_TP_IDDQ_DC = 16 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_SET_SPARE_RI_CONTROL = 17 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_SET_SPARE_DI_CONTROL = 18 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_SET_TP_RI_DC_B = 19 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_SET_TP_DI1_DC_B = 20 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_SET_TP_DI2_DC_B = 21 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_SET_22_SPARE_TEST = 22 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_SET_23_SPARE_TEST = 23 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_SET_TP_TEST_BURNIN_MODE_DC = 24 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_SET_TPFSI_ARRAY_VBL_TO_VDD_DC = 25 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_SET_TPFSI_TP_LOWFREQTEST_REFCLK_DC_UNUSED = 26 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_SET_TP_GLBCK_MEM_TESTCLK_SEL_DC = 27 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_SET_28_SPARE_TEST_CONTROL = 28 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_SET_29_SPARE_TEST_CONTROL = 29 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_SET_30_SPARE_TEST_CONTROL = 30 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL1_SET_31_SPARE_TEST_CONTROL = 31 ;
+
+static const uint8_t P9N2_PERV_ROOT_CTRL2_TPFSI_TP_VSB_DBG_PCB_ASYNC_EN_DC = 0 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_TPFSI_TP_VSB_DBG_PCB_DATA_PAR_DIS_DC = 1 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_TPFSI_TP_VSB_DBG_PCB_TYPE_PAR_DIS_DC = 2 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_TPFSI_TP_VSB_PCB_GSD_LATCHED_MODE_DC = 3 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_TP_PIB_VSB_DISABLE_PARITY_DC = 4 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_TP_PIB_TRACE_MODE_DATA_DC = 5 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_TP_PIB_VSB_SBE_TRACE_MODE = 6 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_TP_TPCPERV_VSB_TRACE_STOP = 7 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_TP_GPIO_PIB_TIMEOUT = 8 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_TP_GPIO_PIB_TIMEOUT_LEN = 3 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_SPARE_PIB_CONTROL = 11 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_TPCFSI_OPB_SW_RESET_DC = 12 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_13_SPARE_OPB_CONTROL = 13 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_14_SPARE_OPB_CONTROL = 14 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_15_SPARE_OPB_CONTROL = 15 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_TPFSI_TP_EDRAM_CTRL_GATE = 16 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_TP_GLBCK_VSB_NEST_VREGDLY_SHUTOFF_DC = 17 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_TPFSI_TP_PFET_FORCE_OFF_DC = 18 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_TPFSI_TP_PFET_OVERRIDE_ON_DC_N = 19 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_TPFSI_TC_HSSPORWREN_ALLOW = 20 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_21_FREE_USAGE = 21 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_22_FREE_USAGE = 22 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_23_FREE_USAGE = 23 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_TP_IO_VSB_OP0A_V1P8_EN = 24 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_TP_IO_VSB_OP0B_V1P8_EN = 25 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_26_FREE_USAGE = 26 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_27_FREE_USAGE = 27 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_28_FREE_USAGE = 28 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_29_FREE_USAGE = 29 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_TP_IO_VSB_OP3A_V1P8_EN = 30 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_TP_IO_VSB_OP3B_V1P8_EN = 31 ;
+
+static const uint8_t P9N2_PERV_ROOT_CTRL2_CLEAR_TPFSI_TP_VSB_DBG_PCB_ASYNC_EN_DC = 0 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_CLEAR_TPFSI_TP_VSB_DBG_PCB_DATA_PAR_DIS_DC = 1 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_CLEAR_TPFSI_TP_VSB_DBG_PCB_TYPE_PAR_DIS_DC = 2 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_CLEAR_TPFSI_TP_VSB_PCB_GSD_LATCHED_MODE_DC = 3 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_CLEAR_TP_PIB_VSB_DISABLE_PARITY_DC = 4 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_CLEAR_TP_PIB_TRACE_MODE_DATA_DC = 5 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_CLEAR_TP_PIB_VSB_SBE_TRACE_MODE = 6 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_CLEAR_TP_TPCPERV_VSB_TRACE_STOP = 7 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_CLEAR_TP_GPIO_PIB_TIMEOUT = 8 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_CLEAR_TP_GPIO_PIB_TIMEOUT_LEN = 3 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_CLEAR_SPARE_PIB_CONTROL = 11 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_CLEAR_TPCFSI_OPB_SW_RESET_DC = 12 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_CLEAR_13_SPARE_OPB_CONTROL = 13 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_CLEAR_14_SPARE_OPB_CONTROL = 14 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_CLEAR_15_SPARE_OPB_CONTROL = 15 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_CLEAR_TPFSI_TP_EDRAM_CTRL_GATE = 16 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_CLEAR_TP_GLBCK_VSB_NEST_VREGDLY_SHUTOFF_DC = 17 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_CLEAR_TPFSI_TP_PFET_FORCE_OFF_DC = 18 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_CLEAR_TPFSI_TP_PFET_OVERRIDE_ON_DC_N = 19 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_CLEAR_TPFSI_TC_HSSPORWREN_ALLOW = 20 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_CLEAR_21_FREE_USAGE = 21 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_CLEAR_22_FREE_USAGE = 22 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_CLEAR_23_FREE_USAGE = 23 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_CLEAR_TP_IO_VSB_OP0A_V1P8_EN = 24 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_CLEAR_TP_IO_VSB_OP0B_V1P8_EN = 25 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_CLEAR_26_FREE_USAGE = 26 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_CLEAR_27_FREE_USAGE = 27 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_CLEAR_28_FREE_USAGE = 28 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_CLEAR_29_FREE_USAGE = 29 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_CLEAR_TP_IO_VSB_OP3A_V1P8_EN = 30 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_CLEAR_TP_IO_VSB_OP3B_V1P8_EN = 31 ;
+
+static const uint8_t P9N2_PERV_ROOT_CTRL2_COPY_ROOT_CTRL2_COPY_REG = 0 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_COPY_ROOT_CTRL2_COPY_REG_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_ROOT_CTRL2_SET_TPFSI_TP_VSB_DBG_PCB_ASYNC_EN_DC = 0 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_SET_TPFSI_TP_VSB_DBG_PCB_DATA_PAR_DIS_DC = 1 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_SET_TPFSI_TP_VSB_DBG_PCB_TYPE_PAR_DIS_DC = 2 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_SET_TPFSI_TP_VSB_PCB_GSD_LATCHED_MODE_DC = 3 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_SET_TP_PIB_VSB_DISABLE_PARITY_DC = 4 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_SET_TP_PIB_TRACE_MODE_DATA_DC = 5 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_SET_TP_PIB_VSB_SBE_TRACE_MODE = 6 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_SET_TP_TPCPERV_VSB_TRACE_STOP = 7 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_SET_TP_GPIO_PIB_TIMEOUT = 8 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_SET_TP_GPIO_PIB_TIMEOUT_LEN = 3 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_SET_SPARE_PIB_CONTROL = 11 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_SET_TPCFSI_OPB_SW_RESET_DC = 12 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_SET_13_SPARE_OPB_CONTROL = 13 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_SET_14_SPARE_OPB_CONTROL = 14 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_SET_15_SPARE_OPB_CONTROL = 15 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_SET_TPFSI_TP_EDRAM_CTRL_GATE = 16 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_SET_TP_GLBCK_VSB_NEST_VREGDLY_SHUTOFF_DC = 17 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_SET_TPFSI_TP_PFET_FORCE_OFF_DC = 18 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_SET_TPFSI_TP_PFET_OVERRIDE_ON_DC_N = 19 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_SET_TPFSI_TC_HSSPORWREN_ALLOW = 20 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_SET_21_FREE_USAGE = 21 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_SET_22_FREE_USAGE = 22 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_SET_23_FREE_USAGE = 23 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_SET_TP_IO_VSB_OP0A_V1P8_EN = 24 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_SET_TP_IO_VSB_OP0B_V1P8_EN = 25 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_SET_26_FREE_USAGE = 26 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_SET_27_FREE_USAGE = 27 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_SET_28_FREE_USAGE = 28 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_SET_29_FREE_USAGE = 29 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_SET_TP_IO_VSB_OP3A_V1P8_EN = 30 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL2_SET_TP_IO_VSB_OP3B_V1P8_EN = 31 ;
+
+static const uint8_t P9N2_PERV_ROOT_CTRL3_OSCSWITCH_CNTL0_DC = 0 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL3_OSCSWITCH_CNTL0_DC_LEN = 16 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL3_TP_GLBCK_VSB_PCIESW_USEOSC_DC = 16 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL3_TP_GLBCK_VSB_PCIESW_USEOSC_DC_LEN = 4 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL3_TP_GLBCK_VSB_PCIESW_TWEAK_DC = 20 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL3_TP_GLBCK_VSB_PCIESW_TWEAK_DC_LEN = 4 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL3_OSCSWITCH_CNTL1_DC = 24 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL3_OSCSWITCH_CNTL1_DC_LEN = 8 ;
+
+static const uint8_t P9N2_PERV_ROOT_CTRL3_CLEAR_OSCSWITCH_CNTL0_DC = 0 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL3_CLEAR_OSCSWITCH_CNTL0_DC_LEN = 16 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL3_CLEAR_TP_GLBCK_VSB_PCIESW_USEOSC_DC = 16 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL3_CLEAR_TP_GLBCK_VSB_PCIESW_USEOSC_DC_LEN = 4 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL3_CLEAR_TP_GLBCK_VSB_PCIESW_TWEAK_DC = 20 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL3_CLEAR_TP_GLBCK_VSB_PCIESW_TWEAK_DC_LEN = 4 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL3_CLEAR_OSCSWITCH_CNTL1_DC = 24 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL3_CLEAR_OSCSWITCH_CNTL1_DC_LEN = 8 ;
+
+static const uint8_t P9N2_PERV_ROOT_CTRL3_COPY_ROOT_CTRL3_COPY_REG = 0 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL3_COPY_ROOT_CTRL3_COPY_REG_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_ROOT_CTRL3_SET_OSCSWITCH_CNTL0_DC = 0 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL3_SET_OSCSWITCH_CNTL0_DC_LEN = 16 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL3_SET_TP_GLBCK_VSB_PCIESW_USEOSC_DC = 16 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL3_SET_TP_GLBCK_VSB_PCIESW_USEOSC_DC_LEN = 4 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL3_SET_TP_GLBCK_VSB_PCIESW_TWEAK_DC = 20 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL3_SET_TP_GLBCK_VSB_PCIESW_TWEAK_DC_LEN = 4 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL3_SET_OSCSWITCH_CNTL1_DC = 24 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL3_SET_OSCSWITCH_CNTL1_DC_LEN = 8 ;
+
+static const uint8_t P9N2_PERV_ROOT_CTRL4_TP_OSCSWITCH_VSB = 0 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL4_TP_OSCSWITCH_VSB_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_ROOT_CTRL4_CLEAR_TP_OSCSWITCH_VSB = 0 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL4_CLEAR_TP_OSCSWITCH_VSB_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_ROOT_CTRL4_COPY_ROOT_CTRL4_COPY_REG = 0 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL4_COPY_ROOT_CTRL4_COPY_REG_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_ROOT_CTRL4_SET_TP_OSCSWITCH_VSB = 0 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL4_SET_TP_OSCSWITCH_VSB_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_ROOT_CTRL5_TPFSI_OSCSW_ERRINJ0_DC = 0 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL5_TPFSI_OSCSW_ERRINJ0_DC_LEN = 3 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL5_TPFSI_OSCSW_ERRINJ1_DC = 3 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL5_TPFSI_OSCSW_ERRINJ1_DC_LEN = 3 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL5_TPFSI_OSCSW_TWEAK_DC = 6 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL5_TPFSI_OSCSW_TWEAK_DC_LEN = 2 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL5_TPFSI_OSCSW_SKEW_ADJUST_DC = 8 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL5_TPFSI_OSCSW_SKEW_ADJUST_DC_LEN = 4 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL5_TPFSI_OSCSW_SNS_CONTENT_SEL_DC = 12 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL5_TPFSI_OSCSW_SNS_CONTENT_SEL_DC_LEN = 3 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL5_15_SPARE_OSC = 15 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL5_TPFSI_TP_CHKSW_DD1_DC = 16 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL5_TPFSI_TP_CHKSW_DD1_DC_LEN = 8 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL5_24_SPARE_OSC = 24 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL5_25_SPARE_OSC = 25 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL5_26_SPARE_OSC = 26 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL5_27_SPARE_OSC = 27 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL5_28_SPARE_OSC = 28 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL5_29_SPARE_OSC = 29 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL5_30_SPARE_OSC = 30 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL5_31_SPARE_OSC = 31 ;
+
+static const uint8_t P9N2_PERV_ROOT_CTRL5_CLEAR_TPFSI_OSCSW_ERRINJ0_DC = 0 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL5_CLEAR_TPFSI_OSCSW_ERRINJ0_DC_LEN = 3 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL5_CLEAR_TPFSI_OSCSW_ERRINJ1_DC = 3 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL5_CLEAR_TPFSI_OSCSW_ERRINJ1_DC_LEN = 3 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL5_CLEAR_TPFSI_OSCSW_TWEAK_DC = 6 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL5_CLEAR_TPFSI_OSCSW_TWEAK_DC_LEN = 2 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL5_CLEAR_TPFSI_OSCSW_SKEW_ADJUST_DC = 8 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL5_CLEAR_TPFSI_OSCSW_SKEW_ADJUST_DC_LEN = 4 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL5_CLEAR_TPFSI_OSCSW_SNS_CONTENT_SEL_DC = 12 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL5_CLEAR_TPFSI_OSCSW_SNS_CONTENT_SEL_DC_LEN = 3 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL5_CLEAR_15_SPARE_OSC = 15 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL5_CLEAR_TPFSI_TP_CHKSW_DD1_DC = 16 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL5_CLEAR_TPFSI_TP_CHKSW_DD1_DC_LEN = 8 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL5_CLEAR_24_SPARE_OSC = 24 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL5_CLEAR_25_SPARE_OSC = 25 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL5_CLEAR_26_SPARE_OSC = 26 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL5_CLEAR_27_SPARE_OSC = 27 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL5_CLEAR_28_SPARE_OSC = 28 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL5_CLEAR_29_SPARE_OSC = 29 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL5_CLEAR_30_SPARE_OSC = 30 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL5_CLEAR_31_SPARE_OSC = 31 ;
+
+static const uint8_t P9N2_PERV_ROOT_CTRL5_COPY_ROOT_CTRL5_COPY_REG = 0 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL5_COPY_ROOT_CTRL5_COPY_REG_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_ROOT_CTRL5_SET_TPFSI_OSCSW_ERRINJ0_DC = 0 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL5_SET_TPFSI_OSCSW_ERRINJ0_DC_LEN = 3 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL5_SET_TPFSI_OSCSW_ERRINJ1_DC = 3 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL5_SET_TPFSI_OSCSW_ERRINJ1_DC_LEN = 3 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL5_SET_TPFSI_OSCSW_TWEAK_DC = 6 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL5_SET_TPFSI_OSCSW_TWEAK_DC_LEN = 2 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL5_SET_TPFSI_OSCSW_SKEW_ADJUST_DC = 8 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL5_SET_TPFSI_OSCSW_SKEW_ADJUST_DC_LEN = 4 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL5_SET_TPFSI_OSCSW_SNS_CONTENT_SEL_DC = 12 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL5_SET_TPFSI_OSCSW_SNS_CONTENT_SEL_DC_LEN = 3 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL5_SET_15_SPARE_OSC = 15 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL5_SET_TPFSI_TP_CHKSW_DD1_DC = 16 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL5_SET_TPFSI_TP_CHKSW_DD1_DC_LEN = 8 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL5_SET_24_SPARE_OSC = 24 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL5_SET_25_SPARE_OSC = 25 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL5_SET_26_SPARE_OSC = 26 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL5_SET_27_SPARE_OSC = 27 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL5_SET_28_SPARE_OSC = 28 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL5_SET_29_SPARE_OSC = 29 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL5_SET_30_SPARE_OSC = 30 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL5_SET_31_SPARE_OSC = 31 ;
+
+static const uint8_t P9N2_PERV_ROOT_CTRL6_TP_PLLREFCLK_RCVR_TERM_DC = 0 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL6_TP_PLLREFCLK_RCVR_TERM_DC_LEN = 2 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL6_TP_PCIREFCLK_RCVR_TERM_DC = 2 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL6_TP_PCIREFCLK_RCVR_TERM_DC_LEN = 2 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL6_REFCLK_0_TERM_DIS_DC = 4 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL6_REFCLK_1_TERM_DIS_DC = 5 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL6_6_SPARE_TERM_DIS = 6 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL6_7_SPARE_TERM_DIS = 7 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL6_TPFSI_OSCSW0_PGOOD_N = 8 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL6_TPFSI_OSCSW1_PGOOD = 9 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL6_10_SPARE_REFCLOCK = 10 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL6_11_SPARE_REFCLOCK = 11 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL6_TPFSI_OFFCHIP_REFCLK_EN_DC = 12 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL6_TPFSI_OFFCHIP_REFCLK_EN_DC_LEN = 12 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL6_GP_TP_GLBCK_VSB_NEST_MESH_SEL_DC = 24 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL6_25_SPARE_REFCLOCK_CONTROL = 25 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL6_26_SPARE_REFCLOCK_CONTROL = 26 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL6_TPFSI_ALTREFCLK_SEL = 27 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL6_TPFSI_ALTREFCLK_SE1 = 28 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL6_29_SPARE_REFCLOCK_CONTROL = 29 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL6_30_SPARE_REFCLOCK_CONTROL = 30 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL6_31_SPARE_REFCLOCK_CONTROL = 31 ;
+
+static const uint8_t P9N2_PERV_ROOT_CTRL6_CLEAR_TP_PLLREFCLK_RCVR_TERM_DC = 0 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL6_CLEAR_TP_PLLREFCLK_RCVR_TERM_DC_LEN = 2 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL6_CLEAR_TP_PCIREFCLK_RCVR_TERM_DC = 2 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL6_CLEAR_TP_PCIREFCLK_RCVR_TERM_DC_LEN = 2 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL6_CLEAR_REFCLK_0_TERM_DIS_DC = 4 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL6_CLEAR_REFCLK_1_TERM_DIS_DC = 5 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL6_CLEAR_6_SPARE_TERM_DIS = 6 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL6_CLEAR_7_SPARE_TERM_DIS = 7 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL6_CLEAR_TPFSI_OSCSW0_PGOOD_N = 8 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL6_CLEAR_TPFSI_OSCSW1_PGOOD = 9 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL6_CLEAR_10_SPARE_REFCLOCK = 10 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL6_CLEAR_11_SPARE_REFCLOCK = 11 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL6_CLEAR_TPFSI_OFFCHIP_REFCLK_EN_DC = 12 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL6_CLEAR_TPFSI_OFFCHIP_REFCLK_EN_DC_LEN = 12 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL6_CLEAR_GP_TP_GLBCK_VSB_NEST_MESH_SEL_DC = 24 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL6_CLEAR_25_SPARE_REFCLOCK_CONTROL = 25 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL6_CLEAR_26_SPARE_REFCLOCK_CONTROL = 26 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL6_CLEAR_TPFSI_ALTREFCLK_SEL = 27 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL6_CLEAR_TPFSI_ALTREFCLK_SE1 = 28 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL6_CLEAR_29_SPARE_REFCLOCK_CONTROL = 29 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL6_CLEAR_30_SPARE_REFCLOCK_CONTROL = 30 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL6_CLEAR_31_SPARE_REFCLOCK_CONTROL = 31 ;
+
+static const uint8_t P9N2_PERV_ROOT_CTRL6_COPY_ROOT_CTRL6_COPY_REG = 0 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL6_COPY_ROOT_CTRL6_COPY_REG_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_ROOT_CTRL6_SET_TP_PLLREFCLK_RCVR_TERM_DC = 0 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL6_SET_TP_PLLREFCLK_RCVR_TERM_DC_LEN = 2 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL6_SET_TP_PCIREFCLK_RCVR_TERM_DC = 2 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL6_SET_TP_PCIREFCLK_RCVR_TERM_DC_LEN = 2 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL6_SET_REFCLK_0_TERM_DIS_DC = 4 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL6_SET_REFCLK_1_TERM_DIS_DC = 5 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL6_SET_6_SPARE_TERM_DIS = 6 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL6_SET_7_SPARE_TERM_DIS = 7 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL6_SET_TPFSI_OSCSW0_PGOOD_N = 8 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL6_SET_TPFSI_OSCSW1_PGOOD = 9 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL6_SET_10_SPARE_REFCLOCK = 10 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL6_SET_11_SPARE_REFCLOCK = 11 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL6_SET_TPFSI_OFFCHIP_REFCLK_EN_DC = 12 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL6_SET_TPFSI_OFFCHIP_REFCLK_EN_DC_LEN = 12 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL6_SET_GP_TP_GLBCK_VSB_NEST_MESH_SEL_DC = 24 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL6_SET_25_SPARE_REFCLOCK_CONTROL = 25 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL6_SET_26_SPARE_REFCLOCK_CONTROL = 26 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL6_SET_TPFSI_ALTREFCLK_SEL = 27 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL6_SET_TPFSI_ALTREFCLK_SE1 = 28 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL6_SET_29_SPARE_REFCLOCK_CONTROL = 29 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL6_SET_30_SPARE_REFCLOCK_CONTROL = 30 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL6_SET_31_SPARE_REFCLOCK_CONTROL = 31 ;
+
+static const uint8_t P9N2_PERV_ROOT_CTRL7_0_SPARE_SECTOR_BUFFER_CONTROL = 0 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_1_SPARE_SECTOR_BUFFER_CONTROL = 1 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_2_SPARE_SECTOR_BUFFER_CONTROL = 2 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_3_SPARE_SECTOR_BUFFER_CONTROL = 3 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_4_SPARE_SECTOR_BUFFER_CONTROL = 4 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_5_SPARE_SECTOR_BUFFER_CONTROL = 5 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_6_SPARE_SECTOR_BUFFER_CONTROL = 6 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_7_SPARE_SECTOR_BUFFER_CONTROL = 7 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_8_SPARE_SECTOR_BUFFER_CONTROL = 8 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_9_SPARE_SECTOR_BUFFER_CONTROL = 9 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_10_SPARE_SECTOR_BUFFER_CONTROL = 10 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_11_SPARE_SECTOR_BUFFER_CONTROL = 11 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_12_SPARE_SECTOR_BUFFER_CONTROL = 12 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_13_SPARE_SECTOR_BUFFER_CONTROL = 13 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_14_SPARE_SECTOR_BUFFER_CONTROL = 14 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_15_SPARE_SECTOR_BUFFER_CONTROL = 15 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_16_SPARE_RESONANT_CLOCKING_CONTROL = 16 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_17_SPARE_RESONANT_CLOCKING_CONTROL = 17 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_18_SPARE_RESONANT_CLOCKING_CONTROL = 18 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_19_SPARE_RESONANT_CLOCKING_CONTROL = 19 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_20_SPARE_RESONANT_CLOCKING_CONTROL = 20 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_21_SPARE_RESONANT_CLOCKING_CONTROL = 21 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_22_SPARE_RESONANT_CLOCKING_CONTROL = 22 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_23_SPARE_RESONANT_CLOCKING_CONTROL = 23 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_24_SPARE_RESONANT_CLOCKING_CONTROL = 24 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_25_SPARE_RESONANT_CLOCKING_CONTROL = 25 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_26_SPARE_RESONANT_CLOCKING_CONTROL = 26 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_27_SPARE_RESONANT_CLOCKING_CONTROL = 27 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_28_SPARE_RESONANT_CLOCKING_CONTROL = 28 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_29_SPARE_RESONANT_CLOCKING_CONTROL = 29 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_30_SPARE_RESONANT_CLOCKING_CONTROL = 30 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_31_SPARE_RESONANT_CLOCKING_CONTROL = 31 ;
+
+static const uint8_t P9N2_PERV_ROOT_CTRL7_CLEAR_0_SPARE_SECTOR_BUFFER_CONTROL = 0 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_CLEAR_1_SPARE_SECTOR_BUFFER_CONTROL = 1 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_CLEAR_2_SPARE_SECTOR_BUFFER_CONTROL = 2 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_CLEAR_3_SPARE_SECTOR_BUFFER_CONTROL = 3 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_CLEAR_4_SPARE_SECTOR_BUFFER_CONTROL = 4 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_CLEAR_5_SPARE_SECTOR_BUFFER_CONTROL = 5 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_CLEAR_6_SPARE_SECTOR_BUFFER_CONTROL = 6 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_CLEAR_7_SPARE_SECTOR_BUFFER_CONTROL = 7 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_CLEAR_8_SPARE_SECTOR_BUFFER_CONTROL = 8 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_CLEAR_9_SPARE_SECTOR_BUFFER_CONTROL = 9 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_CLEAR_10_SPARE_SECTOR_BUFFER_CONTROL = 10 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_CLEAR_11_SPARE_SECTOR_BUFFER_CONTROL = 11 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_CLEAR_12_SPARE_SECTOR_BUFFER_CONTROL = 12 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_CLEAR_13_SPARE_SECTOR_BUFFER_CONTROL = 13 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_CLEAR_14_SPARE_SECTOR_BUFFER_CONTROL = 14 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_CLEAR_15_SPARE_SECTOR_BUFFER_CONTROL = 15 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_CLEAR_16_SPARE_RESONANT_CLOCKING_CONTROL = 16 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_CLEAR_17_SPARE_RESONANT_CLOCKING_CONTROL = 17 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_CLEAR_18_SPARE_RESONANT_CLOCKING_CONTROL = 18 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_CLEAR_19_SPARE_RESONANT_CLOCKING_CONTROL = 19 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_CLEAR_20_SPARE_RESONANT_CLOCKING_CONTROL = 20 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_CLEAR_21_SPARE_RESONANT_CLOCKING_CONTROL = 21 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_CLEAR_22_SPARE_RESONANT_CLOCKING_CONTROL = 22 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_CLEAR_23_SPARE_RESONANT_CLOCKING_CONTROL = 23 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_CLEAR_24_SPARE_RESONANT_CLOCKING_CONTROL = 24 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_CLEAR_25_SPARE_RESONANT_CLOCKING_CONTROL = 25 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_CLEAR_26_SPARE_RESONANT_CLOCKING_CONTROL = 26 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_CLEAR_27_SPARE_RESONANT_CLOCKING_CONTROL = 27 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_CLEAR_28_SPARE_RESONANT_CLOCKING_CONTROL = 28 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_CLEAR_29_SPARE_RESONANT_CLOCKING_CONTROL = 29 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_CLEAR_30_SPARE_RESONANT_CLOCKING_CONTROL = 30 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_CLEAR_31_SPARE_RESONANT_CLOCKING_CONTROL = 31 ;
+
+static const uint8_t P9N2_PERV_ROOT_CTRL7_COPY_ROOT_CTRL7_COPY_REG = 0 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_COPY_ROOT_CTRL7_COPY_REG_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_ROOT_CTRL7_SET_0_SPARE_SECTOR_BUFFER_CONTROL = 0 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_SET_1_SPARE_SECTOR_BUFFER_CONTROL = 1 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_SET_2_SPARE_SECTOR_BUFFER_CONTROL = 2 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_SET_3_SPARE_SECTOR_BUFFER_CONTROL = 3 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_SET_4_SPARE_SECTOR_BUFFER_CONTROL = 4 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_SET_5_SPARE_SECTOR_BUFFER_CONTROL = 5 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_SET_6_SPARE_SECTOR_BUFFER_CONTROL = 6 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_SET_7_SPARE_SECTOR_BUFFER_CONTROL = 7 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_SET_8_SPARE_SECTOR_BUFFER_CONTROL = 8 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_SET_9_SPARE_SECTOR_BUFFER_CONTROL = 9 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_SET_10_SPARE_SECTOR_BUFFER_CONTROL = 10 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_SET_11_SPARE_SECTOR_BUFFER_CONTROL = 11 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_SET_12_SPARE_SECTOR_BUFFER_CONTROL = 12 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_SET_13_SPARE_SECTOR_BUFFER_CONTROL = 13 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_SET_14_SPARE_SECTOR_BUFFER_CONTROL = 14 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_SET_15_SPARE_SECTOR_BUFFER_CONTROL = 15 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_SET_16_SPARE_RESONANT_CLOCKING_CONTROL = 16 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_SET_17_SPARE_RESONANT_CLOCKING_CONTROL = 17 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_SET_18_SPARE_RESONANT_CLOCKING_CONTROL = 18 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_SET_19_SPARE_RESONANT_CLOCKING_CONTROL = 19 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_SET_20_SPARE_RESONANT_CLOCKING_CONTROL = 20 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_SET_21_SPARE_RESONANT_CLOCKING_CONTROL = 21 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_SET_22_SPARE_RESONANT_CLOCKING_CONTROL = 22 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_SET_23_SPARE_RESONANT_CLOCKING_CONTROL = 23 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_SET_24_SPARE_RESONANT_CLOCKING_CONTROL = 24 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_SET_25_SPARE_RESONANT_CLOCKING_CONTROL = 25 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_SET_26_SPARE_RESONANT_CLOCKING_CONTROL = 26 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_SET_27_SPARE_RESONANT_CLOCKING_CONTROL = 27 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_SET_28_SPARE_RESONANT_CLOCKING_CONTROL = 28 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_SET_29_SPARE_RESONANT_CLOCKING_CONTROL = 29 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_SET_30_SPARE_RESONANT_CLOCKING_CONTROL = 30 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL7_SET_31_SPARE_RESONANT_CLOCKING_CONTROL = 31 ;
+
+static const uint8_t P9N2_PERV_ROOT_CTRL8_TP_SS0_PLL_RESET = 0 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_TP_SS0_PLL_BYPASS = 1 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_TP_SS0_PLL_TEST_EN = 2 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_3_SPARE_SS_PLL_CONTROL = 3 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_TP_FILT0_PLL_RESET = 4 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_TP_FILT0_PLL_BYPASS = 5 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_TP_FILT0_PLL_TEST_EN = 6 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_SPARE_FILT0_PLL = 7 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_TP_FILT1_PLL_RESET = 8 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_TP_FILT1_PLL_BYPASS = 9 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_TP_FILT1_PLL_TEST_EN = 10 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_SPARE_FILT1_PLL = 11 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_TP_PLL_TEST_EN = 12 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_TP_PLL_FORCE_OUT_EN_DC = 13 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_14_SPARE_PLL = 14 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_15_SPARE_PLL = 15 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_TP_CLK_ASYNC_RESET_DC = 16 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_TP_CLK_DIV_BYPASS_EN_DC = 17 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_TP_CLK_PDLY_BYPASS1_EN_DC = 18 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_TP_CLK_PDLY_BYPASS2_EN_DC = 19 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_20_SPARE_PLL_CONTROL = 20 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_21_SPARE_PLL_CONTROL = 21 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_22_SPARE_PLL_CONTROL = 22 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_23_SPARE_PLL_CONTROL = 23 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_TP_FSI_CLKIN_SEL_DC = 24 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_25_SPARE_CLKIN_CONTROL = 25 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_26_SPARE_CLKIN_CONTROL = 26 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_27_SPARE_CLKIN_CONTROL = 27 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_TP_PLL_CLKIN_SEL1_DC = 28 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_TP_PLL_CLKIN_SEL2_DC = 29 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_TP_PLL_CLKIN_SEL3_DC = 30 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_TP_PLL_CLKIN_SEL4_DC = 31 ;
+
+static const uint8_t P9N2_PERV_ROOT_CTRL8_CLEAR_TP_SS0_PLL_RESET = 0 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_CLEAR_TP_SS0_PLL_BYPASS = 1 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_CLEAR_TP_SS0_PLL_TEST_EN = 2 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_CLEAR_3_SPARE_SS_PLL_CONTROL = 3 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_CLEAR_TP_FILT0_PLL_RESET = 4 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_CLEAR_TP_FILT0_PLL_BYPASS = 5 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_CLEAR_TP_FILT0_PLL_TEST_EN = 6 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_CLEAR_SPARE_FILT0_PLL = 7 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_CLEAR_TP_FILT1_PLL_RESET = 8 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_CLEAR_TP_FILT1_PLL_BYPASS = 9 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_CLEAR_TP_FILT1_PLL_TEST_EN = 10 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_CLEAR_SPARE_FILT1_PLL = 11 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_CLEAR_TP_PLL_TEST_EN = 12 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_CLEAR_TP_PLL_FORCE_OUT_EN_DC = 13 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_CLEAR_14_SPARE_PLL = 14 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_CLEAR_15_SPARE_PLL = 15 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_CLEAR_TP_CLK_ASYNC_RESET_DC = 16 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_CLEAR_TP_CLK_DIV_BYPASS_EN_DC = 17 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_CLEAR_TP_CLK_PDLY_BYPASS1_EN_DC = 18 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_CLEAR_TP_CLK_PDLY_BYPASS2_EN_DC = 19 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_CLEAR_20_SPARE_PLL_CONTROL = 20 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_CLEAR_21_SPARE_PLL_CONTROL = 21 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_CLEAR_22_SPARE_PLL_CONTROL = 22 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_CLEAR_23_SPARE_PLL_CONTROL = 23 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_CLEAR_TP_FSI_CLKIN_SEL_DC = 24 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_CLEAR_25_SPARE_CLKIN_CONTROL = 25 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_CLEAR_26_SPARE_CLKIN_CONTROL = 26 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_CLEAR_27_SPARE_CLKIN_CONTROL = 27 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_CLEAR_TP_PLL_CLKIN_SEL1_DC = 28 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_CLEAR_TP_PLL_CLKIN_SEL2_DC = 29 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_CLEAR_TP_PLL_CLKIN_SEL3_DC = 30 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_CLEAR_TP_PLL_CLKIN_SEL4_DC = 31 ;
+
+static const uint8_t P9N2_PERV_ROOT_CTRL8_COPY_ROOT_CTRL8_COPY_REG = 0 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_COPY_ROOT_CTRL8_COPY_REG_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_ROOT_CTRL8_SET_TP_SS0_PLL_RESET = 0 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_SET_TP_SS0_PLL_BYPASS = 1 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_SET_TP_SS0_PLL_TEST_EN = 2 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_SET_3_SPARE_SS_PLL_CONTROL = 3 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_SET_TP_FILT0_PLL_RESET = 4 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_SET_TP_FILT0_PLL_BYPASS = 5 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_SET_TP_FILT0_PLL_TEST_EN = 6 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_SET_SPARE_FILT0_PLL = 7 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_SET_TP_FILT1_PLL_RESET = 8 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_SET_TP_FILT1_PLL_BYPASS = 9 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_SET_TP_FILT1_PLL_TEST_EN = 10 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_SET_SPARE_FILT1_PLL = 11 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_SET_TP_PLL_TEST_EN = 12 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_SET_TP_PLL_FORCE_OUT_EN_DC = 13 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_SET_14_SPARE_PLL = 14 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_SET_15_SPARE_PLL = 15 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_SET_TP_CLK_ASYNC_RESET_DC = 16 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_SET_TP_CLK_DIV_BYPASS_EN_DC = 17 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_SET_TP_CLK_PDLY_BYPASS1_EN_DC = 18 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_SET_TP_CLK_PDLY_BYPASS2_EN_DC = 19 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_SET_20_SPARE_PLL_CONTROL = 20 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_SET_21_SPARE_PLL_CONTROL = 21 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_SET_22_SPARE_PLL_CONTROL = 22 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_SET_23_SPARE_PLL_CONTROL = 23 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_SET_TP_FSI_CLKIN_SEL_DC = 24 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_SET_25_SPARE_CLKIN_CONTROL = 25 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_SET_26_SPARE_CLKIN_CONTROL = 26 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_SET_27_SPARE_CLKIN_CONTROL = 27 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_SET_TP_PLL_CLKIN_SEL1_DC = 28 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_SET_TP_PLL_CLKIN_SEL2_DC = 29 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_SET_TP_PLL_CLKIN_SEL3_DC = 30 ;
+static const uint8_t P9N2_PERV_ROOT_CTRL8_SET_TP_PLL_CLKIN_SEL4_DC = 31 ;
+
+static const uint8_t P9N2_PERV_SBE_LCL_DBG_EN = 0 ;
+static const uint8_t P9N2_PERV_SBE_LCL_DBG_HALT_ON_XSTOP = 1 ;
+static const uint8_t P9N2_PERV_SBE_LCL_DBG_HALT_ON_TRIG = 2 ;
+static const uint8_t P9N2_PERV_SBE_LCL_DBG_RESERVED3 = 3 ;
+static const uint8_t P9N2_PERV_SBE_LCL_DBG_EN_INTR_ADDR = 4 ;
+static const uint8_t P9N2_PERV_SBE_LCL_DBG_EN_TRACE_EXTRA = 5 ;
+static const uint8_t P9N2_PERV_SBE_LCL_DBG_EN_TRACE_STALL = 6 ;
+static const uint8_t P9N2_PERV_SBE_LCL_DBG_EN_WAIT_CYCLES = 7 ;
+static const uint8_t P9N2_PERV_SBE_LCL_DBG_EN_FULL_SPEED = 8 ;
+static const uint8_t P9N2_PERV_SBE_LCL_DBG_RESERVED9 = 9 ;
+static const uint8_t P9N2_PERV_SBE_LCL_DBG_TRACE_MODE_SEL = 10 ;
+static const uint8_t P9N2_PERV_SBE_LCL_DBG_TRACE_MODE_SEL_LEN = 2 ;
+static const uint8_t P9N2_PERV_SBE_LCL_DBG_FIR_TRIGGER = 16 ;
+static const uint8_t P9N2_PERV_SBE_LCL_DBG_MIB_GPIO = 17 ;
+static const uint8_t P9N2_PERV_SBE_LCL_DBG_MIB_GPIO_LEN = 3 ;
+static const uint8_t P9N2_PERV_SBE_LCL_DBG_TRACE_DATA_SEL = 20 ;
+static const uint8_t P9N2_PERV_SBE_LCL_DBG_TRACE_DATA_SEL_LEN = 4 ;
+static const uint8_t P9N2_PERV_SBE_LCL_DBG_HALT_INPUT = 24 ;
+
+static const uint8_t P9N2_PERV_SBE_LCL_EIMR_START0 = 0 ;
+static const uint8_t P9N2_PERV_SBE_LCL_EIMR_START1 = 1 ;
+static const uint8_t P9N2_PERV_SBE_LCL_EIMR_INTR0 = 2 ;
+static const uint8_t P9N2_PERV_SBE_LCL_EIMR_INTR1 = 3 ;
+static const uint8_t P9N2_PERV_SBE_LCL_EIMR_DRTM_REQ = 4 ;
+static const uint8_t P9N2_PERV_SBE_LCL_EIMR_SBEFIFO_RESET = 5 ;
+static const uint8_t P9N2_PERV_SBE_LCL_EIMR_SBEFIFO_DATA = 6 ;
+static const uint8_t P9N2_PERV_SBE_LCL_EIMR_SPARE = 7 ;
+static const uint8_t P9N2_PERV_SBE_LCL_EIMR_TRIG = 8 ;
+static const uint8_t P9N2_PERV_SBE_LCL_EIMR_XSTOP = 9 ;
+
+static const uint8_t P9N2_PERV_SBE_LCL_EINR_START0 = 0 ;
+static const uint8_t P9N2_PERV_SBE_LCL_EINR_START1 = 1 ;
+static const uint8_t P9N2_PERV_SBE_LCL_EINR_INTR0 = 2 ;
+static const uint8_t P9N2_PERV_SBE_LCL_EINR_INTR1 = 3 ;
+static const uint8_t P9N2_PERV_SBE_LCL_EINR_DRTM_REQ = 4 ;
+static const uint8_t P9N2_PERV_SBE_LCL_EINR_SBEFIFO_RESET = 5 ;
+static const uint8_t P9N2_PERV_SBE_LCL_EINR_SBEFIFO_DATA = 6 ;
+static const uint8_t P9N2_PERV_SBE_LCL_EINR_SPARE = 7 ;
+static const uint8_t P9N2_PERV_SBE_LCL_EINR_TRIG = 8 ;
+static const uint8_t P9N2_PERV_SBE_LCL_EINR_XSTOP = 9 ;
+
+static const uint8_t P9N2_PERV_SBE_LCL_EIPR_START0 = 0 ;
+static const uint8_t P9N2_PERV_SBE_LCL_EIPR_START1 = 1 ;
+static const uint8_t P9N2_PERV_SBE_LCL_EIPR_INTR0 = 2 ;
+static const uint8_t P9N2_PERV_SBE_LCL_EIPR_INTR1 = 3 ;
+static const uint8_t P9N2_PERV_SBE_LCL_EIPR_DRTM_REQ = 4 ;
+static const uint8_t P9N2_PERV_SBE_LCL_EIPR_SBEFIFO_RESET = 5 ;
+static const uint8_t P9N2_PERV_SBE_LCL_EIPR_SBEFIFO_DATA = 6 ;
+static const uint8_t P9N2_PERV_SBE_LCL_EIPR_SPARE = 7 ;
+static const uint8_t P9N2_PERV_SBE_LCL_EIPR_TRIG = 8 ;
+static const uint8_t P9N2_PERV_SBE_LCL_EIPR_XSTOP = 9 ;
+
+static const uint8_t P9N2_PERV_SBE_LCL_EISR_START0 = 0 ;
+static const uint8_t P9N2_PERV_SBE_LCL_EISR_START1 = 1 ;
+static const uint8_t P9N2_PERV_SBE_LCL_EISR_INTR0 = 2 ;
+static const uint8_t P9N2_PERV_SBE_LCL_EISR_INTR1 = 3 ;
+static const uint8_t P9N2_PERV_SBE_LCL_EISR_DRTM_REQ = 4 ;
+static const uint8_t P9N2_PERV_SBE_LCL_EISR_SBEFIFO_RESET = 5 ;
+static const uint8_t P9N2_PERV_SBE_LCL_EISR_SBEFIFO_DATA = 6 ;
+static const uint8_t P9N2_PERV_SBE_LCL_EISR_SPARE = 7 ;
+static const uint8_t P9N2_PERV_SBE_LCL_EISR_TRIG = 8 ;
+static const uint8_t P9N2_PERV_SBE_LCL_EISR_XSTOP = 9 ;
+
+static const uint8_t P9N2_PERV_SBE_LCL_EISTR_INTERRUPT_STATUS = 0 ;
+static const uint8_t P9N2_PERV_SBE_LCL_EISTR_INTERRUPT_STATUS_LEN = 10 ;
+
+static const uint8_t P9N2_PERV_SBE_LCL_EITR_START0 = 0 ;
+static const uint8_t P9N2_PERV_SBE_LCL_EITR_START1 = 1 ;
+static const uint8_t P9N2_PERV_SBE_LCL_EITR_INTR0 = 2 ;
+static const uint8_t P9N2_PERV_SBE_LCL_EITR_INTR1 = 3 ;
+static const uint8_t P9N2_PERV_SBE_LCL_EITR_DRTM_REQ = 4 ;
+static const uint8_t P9N2_PERV_SBE_LCL_EITR_SBEFIFO_RESET = 5 ;
+static const uint8_t P9N2_PERV_SBE_LCL_EITR_SBEFIFO_DATA = 6 ;
+static const uint8_t P9N2_PERV_SBE_LCL_EITR_SPARE = 7 ;
+static const uint8_t P9N2_PERV_SBE_LCL_EITR_TRIG = 8 ;
+static const uint8_t P9N2_PERV_SBE_LCL_EITR_XSTOP = 9 ;
+
+static const uint8_t P9N2_PERV_SBE_LCL_IVPR_IVPR = 0 ;
+static const uint8_t P9N2_PERV_SBE_LCL_IVPR_IVPR_LEN = 23 ;
+
+static const uint8_t P9N2_PERV_SBE_LCL_TBR_TIMEBASE = 0 ;
+static const uint8_t P9N2_PERV_SBE_LCL_TBR_TIMEBASE_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_SBE_LCL_TSEL_FIT_SEL = 0 ;
+static const uint8_t P9N2_PERV_SBE_LCL_TSEL_FIT_SEL_LEN = 4 ;
+static const uint8_t P9N2_PERV_SBE_LCL_TSEL_WATCHDOG_SEL = 4 ;
+static const uint8_t P9N2_PERV_SBE_LCL_TSEL_WATCHDOG_SEL_LEN = 4 ;
+
+static const uint8_t P9N2_PERV_SB_CS_SECURE_DEBUG_MODE = 0 ;
+static const uint8_t P9N2_PERV_SB_CS_START_RESTART_VECTOR0 = 12 ;
+static const uint8_t P9N2_PERV_SB_CS_START_RESTART_VECTOR1 = 13 ;
+static const uint8_t P9N2_PERV_SB_CS_INTERRUPT_S0 = 14 ;
+static const uint8_t P9N2_PERV_SB_CS_INTERRUPT_S1 = 15 ;
+static const uint8_t P9N2_PERV_SB_CS_BYPASSING_RESET_SEQUENCE_PIB_I2CM = 16 ;
+static const uint8_t P9N2_PERV_SB_CS_SELECT_SECONDARY_SEEPROM = 17 ;
+static const uint8_t P9N2_PERV_SB_CS_DEBUG_BOLT_ON_CONTROL_BITS = 25 ;
+static const uint8_t P9N2_PERV_SB_CS_DEBUG_BOLT_ON_CONTROL_BITS_LEN = 7 ;
+
+static const uint8_t P9N2_PERV_1_SCAN32_SCAN32_REG = 0 ;
+static const uint8_t P9N2_PERV_1_SCAN32_SCAN32_REG_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_1_SCAN64_SCAN64_REG = 0 ;
+static const uint8_t P9N2_PERV_1_SCAN64_SCAN64_REG_LEN = 64 ;
+
+static const uint8_t P9N2_PERV_1_SCAN_CAPTUREDR_SCAN_CAPTUREDR_REG = 0 ;
+static const uint8_t P9N2_PERV_1_SCAN_CAPTUREDR_SCAN_CAPTUREDR_REG_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_1_SCAN_REGION_TYPE_SYSTEM_FAST_INIT = 0 ;
+static const uint8_t P9N2_PERV_1_SCAN_REGION_TYPE_VITL = 3 ;
+static const uint8_t P9N2_PERV_1_SCAN_REGION_TYPE_PERV = 4 ;
+static const uint8_t P9N2_PERV_1_SCAN_REGION_TYPE_UNIT1 = 5 ;
+static const uint8_t P9N2_PERV_1_SCAN_REGION_TYPE_UNIT2 = 6 ;
+static const uint8_t P9N2_PERV_1_SCAN_REGION_TYPE_UNIT3 = 7 ;
+static const uint8_t P9N2_PERV_1_SCAN_REGION_TYPE_UNIT4 = 8 ;
+static const uint8_t P9N2_PERV_1_SCAN_REGION_TYPE_UNIT5 = 9 ;
+static const uint8_t P9N2_PERV_1_SCAN_REGION_TYPE_UNIT6 = 10 ;
+static const uint8_t P9N2_PERV_1_SCAN_REGION_TYPE_UNIT7 = 11 ;
+static const uint8_t P9N2_PERV_1_SCAN_REGION_TYPE_UNIT8 = 12 ;
+static const uint8_t P9N2_PERV_1_SCAN_REGION_TYPE_UNIT9 = 13 ;
+static const uint8_t P9N2_PERV_1_SCAN_REGION_TYPE_UNIT10 = 14 ;
+static const uint8_t P9N2_PERV_1_SCAN_REGION_TYPE_FUNC = 48 ;
+static const uint8_t P9N2_PERV_1_SCAN_REGION_TYPE_CFG = 49 ;
+static const uint8_t P9N2_PERV_1_SCAN_REGION_TYPE_CCFG_GPTR = 50 ;
+static const uint8_t P9N2_PERV_1_SCAN_REGION_TYPE_REGF = 51 ;
+static const uint8_t P9N2_PERV_1_SCAN_REGION_TYPE_LBIST = 52 ;
+static const uint8_t P9N2_PERV_1_SCAN_REGION_TYPE_ABIST = 53 ;
+static const uint8_t P9N2_PERV_1_SCAN_REGION_TYPE_REPR = 54 ;
+static const uint8_t P9N2_PERV_1_SCAN_REGION_TYPE_TIME = 55 ;
+static const uint8_t P9N2_PERV_1_SCAN_REGION_TYPE_BNDY = 56 ;
+static const uint8_t P9N2_PERV_1_SCAN_REGION_TYPE_FARR = 57 ;
+static const uint8_t P9N2_PERV_1_SCAN_REGION_TYPE_CMSK = 58 ;
+static const uint8_t P9N2_PERV_1_SCAN_REGION_TYPE_INEX = 59 ;
+
+static const uint8_t P9N2_PERV_1_SCAN_UPDATEDR_SCAN_UPDATEDR_REG = 0 ;
+static const uint8_t P9N2_PERV_1_SCAN_UPDATEDR_SCAN_UPDATEDR_REG_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_1_SCAN_UPDATEDR_LONG_SCAN_UPDATEDR_LONG_REG = 0 ;
+static const uint8_t P9N2_PERV_1_SCAN_UPDATEDR_LONG_SCAN_UPDATEDR_LONG_REG_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_SCRATCH_REGISTER_1_SR = 0 ;
+static const uint8_t P9N2_PERV_SCRATCH_REGISTER_1_SR_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_SCRATCH_REGISTER_2_SR = 0 ;
+static const uint8_t P9N2_PERV_SCRATCH_REGISTER_2_SR_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_SCRATCH_REGISTER_3_SR = 0 ;
+static const uint8_t P9N2_PERV_SCRATCH_REGISTER_3_SR_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_SCRATCH_REGISTER_4_SR = 0 ;
+static const uint8_t P9N2_PERV_SCRATCH_REGISTER_4_SR_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_SCRATCH_REGISTER_5_SR = 0 ;
+static const uint8_t P9N2_PERV_SCRATCH_REGISTER_5_SR_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_SCRATCH_REGISTER_6_SR = 0 ;
+static const uint8_t P9N2_PERV_SCRATCH_REGISTER_6_SR_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_SCRATCH_REGISTER_7_SR = 0 ;
+static const uint8_t P9N2_PERV_SCRATCH_REGISTER_7_SR_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_SCRATCH_REGISTER_8_SR = 0 ;
+static const uint8_t P9N2_PERV_SCRATCH_REGISTER_8_SR_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_FSISHIFT_SHIFT_CONTROL_REGISTER_2_REGISTER = 0 ;
+static const uint8_t P9N2_PERV_FSISHIFT_SHIFT_CONTROL_REGISTER_2_REGISTER_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_1_SKITTER_CLKSRC_REG_SKITTER0 = 0 ;
+static const uint8_t P9N2_PERV_1_SKITTER_CLKSRC_REG_SKITTER0_LEN = 3 ;
+static const uint8_t P9N2_PERV_1_SKITTER_CLKSRC_REG_SKITTER0_DELAY_SELECT = 36 ;
+static const uint8_t P9N2_PERV_1_SKITTER_CLKSRC_REG_SKITTER0_DELAY_SELECT_LEN = 2 ;
+
+static const uint8_t P9N2_PERV_1_SKITTER_FORCE_REG_F_READ = 0 ;
+
+static const uint8_t P9N2_PERV_1_SKITTER_MODE_REG_HOLD_SAMPLE = 0 ;
+static const uint8_t P9N2_PERV_1_SKITTER_MODE_REG_DISABLE_STICKINESS = 1 ;
+static const uint8_t P9N2_PERV_1_SKITTER_MODE_REG_UNUSED1 = 2 ;
+static const uint8_t P9N2_PERV_1_SKITTER_MODE_REG_UNUSED1_LEN = 2 ;
+static const uint8_t P9N2_PERV_1_SKITTER_MODE_REG_HOLD_DBGTRIG_SEL = 4 ;
+static const uint8_t P9N2_PERV_1_SKITTER_MODE_REG_HOLD_DBGTRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_PERV_1_SKITTER_MODE_REG_RESET_TRIG_SEL = 6 ;
+static const uint8_t P9N2_PERV_1_SKITTER_MODE_REG_RESET_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_PERV_1_SKITTER_MODE_REG_SAMPLE_GUTS = 8 ;
+static const uint8_t P9N2_PERV_1_SKITTER_MODE_REG_SAMPLE_GUTS_LEN = 2 ;
+static const uint8_t P9N2_PERV_1_SKITTER_MODE_REG_HOLD_SAMPLE_WITH_TRIGGER = 44 ;
+static const uint8_t P9N2_PERV_1_SKITTER_MODE_REG_DATA_V_LT = 45 ;
+
+static const uint8_t P9N2_PERV_1_SLAVE_CONFIG_REG_CFG_DISABLE_PERV_THOLD_CHECK = 0 ;
+static const uint8_t P9N2_PERV_1_SLAVE_CONFIG_REG_CFG_DISABLE_MALF_PULSE_GEN = 1 ;
+static const uint8_t P9N2_PERV_1_SLAVE_CONFIG_REG_CFG_STOP_HANG_CNT_SYS_XSTP = 2 ;
+static const uint8_t P9N2_PERV_1_SLAVE_CONFIG_REG_CFG_DISABLE_CL_ATOMIC_LOCK = 3 ;
+static const uint8_t P9N2_PERV_1_SLAVE_CONFIG_REG_CFG_DISABLE_HEARTBEAT = 4 ;
+static const uint8_t P9N2_PERV_1_SLAVE_CONFIG_REG_CFG_DISABLE_FORCE_TO_ZERO = 5 ;
+static const uint8_t P9N2_PERV_1_SLAVE_CONFIG_REG_CFG_PM_DISABLE = 6 ;
+static const uint8_t P9N2_PERV_1_SLAVE_CONFIG_REG_CFG_PM_MUX_DISABLE = 7 ;
+static const uint8_t P9N2_PERV_1_SLAVE_CONFIG_REG_ERROR_MASK = 8 ;
+static const uint8_t P9N2_PERV_1_SLAVE_CONFIG_REG_ERROR_MASK_LEN = 6 ;
+
+static const uint8_t P9N2_PERV_SNS1LTH_SNS1_0_31 = 0 ;
+static const uint8_t P9N2_PERV_SNS1LTH_SNS1_0_31_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_SNS2LTH_SNS2_UNUSED_0_31 = 0 ;
+static const uint8_t P9N2_PERV_SNS2LTH_SNS2_UNUSED_0_31_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_1_SPATTN_IN0 = 0 ;
+static const uint8_t P9N2_PERV_1_SPATTN_IN1 = 1 ;
+static const uint8_t P9N2_PERV_1_SPATTN_IN2 = 2 ;
+static const uint8_t P9N2_PERV_1_SPATTN_IN3 = 3 ;
+static const uint8_t P9N2_PERV_1_SPATTN_IN4 = 4 ;
+static const uint8_t P9N2_PERV_1_SPATTN_IN5 = 5 ;
+static const uint8_t P9N2_PERV_1_SPATTN_IN6 = 6 ;
+static const uint8_t P9N2_PERV_1_SPATTN_IN7 = 7 ;
+static const uint8_t P9N2_PERV_1_SPATTN_IN8 = 8 ;
+static const uint8_t P9N2_PERV_1_SPATTN_IN9 = 9 ;
+
+static const uint8_t P9N2_PERV_1_SPA_MASK_IN = 0 ;
+static const uint8_t P9N2_PERV_1_SPA_MASK_IN_LEN = 10 ;
+
+static const uint8_t P9N2_PERV_FSI2PIB_STATUS_ANY_ERROR = 0 ;
+static const uint8_t P9N2_PERV_FSI2PIB_STATUS_SYSTEM_CHECKSTOP = 1 ;
+static const uint8_t P9N2_PERV_FSI2PIB_STATUS_SPECIAL_ATTENTION = 2 ;
+static const uint8_t P9N2_PERV_FSI2PIB_STATUS_RECOVERABLE_ERROR = 3 ;
+static const uint8_t P9N2_PERV_FSI2PIB_STATUS_CHIPLET_INTERRUPT_FROM_HOST = 4 ;
+static const uint8_t P9N2_PERV_FSI2PIB_STATUS_PARITY_CHECK = 5 ;
+static const uint8_t P9N2_PERV_FSI2PIB_STATUS_POWER_MANAGEMENT_INTERRUPT = 6 ;
+static const uint8_t P9N2_PERV_FSI2PIB_STATUS_PROTECTION_CHECK = 7 ;
+static const uint8_t P9N2_PERV_FSI2PIB_STATUS_SELFBOOT_DONE = 8 ;
+static const uint8_t P9N2_PERV_FSI2PIB_STATUS_RESERVED_9 = 9 ;
+static const uint8_t P9N2_PERV_FSI2PIB_STATUS_IDLE_INDICATION = 10 ;
+static const uint8_t P9N2_PERV_FSI2PIB_STATUS_PIB_ABORT = 11 ;
+static const uint8_t P9N2_PERV_FSI2PIB_STATUS_USE_OSC_OBSERVATION = 12 ;
+static const uint8_t P9N2_PERV_FSI2PIB_STATUS_USE_OSC_OBSERVATION_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSI2PIB_STATUS_VDD_NEST_OBSERVE = 16 ;
+static const uint8_t P9N2_PERV_FSI2PIB_STATUS_PIB_ERROR_CODE = 17 ;
+static const uint8_t P9N2_PERV_FSI2PIB_STATUS_PIB_ERROR_CODE_LEN = 3 ;
+static const uint8_t P9N2_PERV_FSI2PIB_STATUS_OSCILLATOR = 20 ;
+static const uint8_t P9N2_PERV_FSI2PIB_STATUS_OSCILLATOR_LEN = 4 ;
+static const uint8_t P9N2_PERV_FSI2PIB_STATUS_PLLLOCK_0_FILTER_PLL_NEST = 24 ;
+static const uint8_t P9N2_PERV_FSI2PIB_STATUS_PLLLOCK_1_FILTER_PLL_MC = 25 ;
+static const uint8_t P9N2_PERV_FSI2PIB_STATUS_PLLLOCK_2_XBUS = 26 ;
+static const uint8_t P9N2_PERV_FSI2PIB_STATUS_PLLLOCK_3_NEST = 27 ;
+static const uint8_t P9N2_PERV_FSI2PIB_STATUS_INTERRUPT_CONDITION_PENDING = 28 ;
+static const uint8_t P9N2_PERV_FSI2PIB_STATUS_INTERRUPT_ENABLED = 29 ;
+static const uint8_t P9N2_PERV_FSI2PIB_STATUS_SELFBOOT_ENGINE_ATTENTION = 30 ;
+static const uint8_t P9N2_PERV_FSI2PIB_STATUS_RESERVED_31 = 31 ;
+
+static const uint8_t P9N2_PERV_FSISHIFT_STATUS_4 = 0 ;
+static const uint8_t P9N2_PERV_FSISHIFT_STATUS_4_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_FSII2C_STATUS_REGISTER_ENGINE_A_INVALID_CMD_0 = 0 ;
+static const uint8_t P9N2_PERV_FSII2C_STATUS_REGISTER_ENGINE_A_LBUS_PARITY_ERROR_0 = 1 ;
+static const uint8_t P9N2_PERV_FSII2C_STATUS_REGISTER_ENGINE_A_BE_OV_ERROR_0 = 2 ;
+static const uint8_t P9N2_PERV_FSII2C_STATUS_REGISTER_ENGINE_A_BE_ACC_ERROR_0 = 3 ;
+static const uint8_t P9N2_PERV_FSII2C_STATUS_REGISTER_ENGINE_A_ARBITRATION_LOST_ERROR_0 = 4 ;
+static const uint8_t P9N2_PERV_FSII2C_STATUS_REGISTER_ENGINE_A_NACK_RECEIVED_ERROR_0 = 5 ;
+static const uint8_t P9N2_PERV_FSII2C_STATUS_REGISTER_ENGINE_A_DATA_REQUEST_0 = 6 ;
+static const uint8_t P9N2_PERV_FSII2C_STATUS_REGISTER_ENGINE_A_STOP_ERROR_0 = 8 ;
+static const uint8_t P9N2_PERV_FSII2C_STATUS_REGISTER_ENGINE_A_BUSY = 22 ;
+static const uint8_t P9N2_PERV_FSII2C_STATUS_REGISTER_ENGINE_A_SELF_BUSY_0 = 23 ;
+static const uint8_t P9N2_PERV_FSII2C_STATUS_REGISTER_ENGINE_A_FIFO_ENTRY_COUNT_0 = 28 ;
+static const uint8_t P9N2_PERV_FSII2C_STATUS_REGISTER_ENGINE_A_FIFO_ENTRY_COUNT_0_LEN = 4 ;
+
+static const uint8_t P9N2_PERV_PIB2OPB1_STAT_RDDAT_ERRES_ANY_ERROR = 0 ;
+static const uint8_t P9N2_PERV_PIB2OPB1_STAT_RDDAT_ERRES_CMD_PARITY_ERROR = 1 ;
+static const uint8_t P9N2_PERV_PIB2OPB1_STAT_RDDAT_ERRES_WR_DATA_PARITY_ERROR = 2 ;
+static const uint8_t P9N2_PERV_PIB2OPB1_STAT_RDDAT_ERRES_RD_DATA_PARITY_ERROR = 3 ;
+static const uint8_t P9N2_PERV_PIB2OPB1_STAT_RDDAT_ERRES_LCK_STATUS_PARITY_ERROR = 4 ;
+static const uint8_t P9N2_PERV_PIB2OPB1_STAT_RDDAT_ERRES_FSM_PARITY_ERROR = 5 ;
+static const uint8_t P9N2_PERV_PIB2OPB1_STAT_RDDAT_ERRES_OPB_COMMAND_OVERRUN_ERROR = 7 ;
+static const uint8_t P9N2_PERV_PIB2OPB1_STAT_RDDAT_ERRES_OPB_PARITY_ERROR = 8 ;
+static const uint8_t P9N2_PERV_PIB2OPB1_STAT_RDDAT_ERRES_OPB_PROTOCOL_ERROR = 9 ;
+static const uint8_t P9N2_PERV_PIB2OPB1_STAT_RDDAT_ERRES_OPB_TIMEOUT_BIT = 10 ;
+static const uint8_t P9N2_PERV_PIB2OPB1_STAT_RDDAT_ERRES_OPB_ERRACK = 11 ;
+static const uint8_t P9N2_PERV_PIB2OPB1_STAT_RDDAT_ERRES_INVALID_ADDRESS = 12 ;
+static const uint8_t P9N2_PERV_PIB2OPB1_STAT_RDDAT_ERRES_PORT_IS_FENCED = 13 ;
+static const uint8_t P9N2_PERV_PIB2OPB1_STAT_RDDAT_ERRES_READ_DATA_VALID = 14 ;
+static const uint8_t P9N2_PERV_PIB2OPB1_STAT_RDDAT_ERRES_OPB_BUSY_FLAG = 15 ;
+static const uint8_t P9N2_PERV_PIB2OPB1_STAT_RDDAT_ERRES_CM_ANY_MASTER_ERROR = 16 ;
+static const uint8_t P9N2_PERV_PIB2OPB1_STAT_RDDAT_ERRES_CM_ANY_PORT_INTERRUPT = 17 ;
+static const uint8_t P9N2_PERV_PIB2OPB1_STAT_RDDAT_ERRES_CM_HOT_PLUG_EVENT = 18 ;
+static const uint8_t P9N2_PERV_PIB2OPB1_STAT_RDDAT_ERRES_CM_CONTROL_REGISTER_PARITY_INTERRUPT = 19 ;
+static const uint8_t P9N2_PERV_PIB2OPB1_STAT_RDDAT_ERRES_CM_ANY_INTR_1_REMOTE_SLAVE_INTERRUPT = 20 ;
+static const uint8_t P9N2_PERV_PIB2OPB1_STAT_RDDAT_ERRES_CM_ANY_INTR_2_REMOTE_SLAVE_INTERRUPT = 21 ;
+static const uint8_t P9N2_PERV_PIB2OPB1_STAT_RDDAT_ERRES_M_ANY_MASTER_ERROR = 24 ;
+static const uint8_t P9N2_PERV_PIB2OPB1_STAT_RDDAT_ERRES_M_ANY_PORT_INTERRUPT = 25 ;
+static const uint8_t P9N2_PERV_PIB2OPB1_STAT_RDDAT_ERRES_M_HOT_PLUG_EVENT = 26 ;
+static const uint8_t P9N2_PERV_PIB2OPB1_STAT_RDDAT_ERRES_M_CONTROL_REGISTER_PARITY_INTERRUPT = 27 ;
+static const uint8_t P9N2_PERV_PIB2OPB1_STAT_RDDAT_ERRES_M_ANY_INTR_1_REMOTE_SLAVE_INTERRUPT = 28 ;
+static const uint8_t P9N2_PERV_PIB2OPB1_STAT_RDDAT_ERRES_M_ANY_INTR_2_REMOTE_SLAVE_INTERRUPT = 29 ;
+static const uint8_t P9N2_PERV_PIB2OPB1_STAT_RDDAT_ERRES_READ_DATA = 32 ;
+static const uint8_t P9N2_PERV_PIB2OPB1_STAT_RDDAT_ERRES_READ_DATA_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_STAT_RDDAT_ERRES_ANY_ERROR = 0 ;
+static const uint8_t P9N2_PERV_STAT_RDDAT_ERRES_CMD_PARITY_ERROR = 1 ;
+static const uint8_t P9N2_PERV_STAT_RDDAT_ERRES_WR_DATA_PARITY_ERROR = 2 ;
+static const uint8_t P9N2_PERV_STAT_RDDAT_ERRES_RD_DATA_PARITY_ERROR = 3 ;
+static const uint8_t P9N2_PERV_STAT_RDDAT_ERRES_LCK_STATUS_PARITY_ERROR = 4 ;
+static const uint8_t P9N2_PERV_STAT_RDDAT_ERRES_FSM_PARITY_ERROR = 5 ;
+static const uint8_t P9N2_PERV_STAT_RDDAT_ERRES_OPB_COMMAND_OVERRUN_ERROR = 7 ;
+static const uint8_t P9N2_PERV_STAT_RDDAT_ERRES_OPB_PARITY_ERROR = 8 ;
+static const uint8_t P9N2_PERV_STAT_RDDAT_ERRES_OPB_PROTOCOL_ERROR = 9 ;
+static const uint8_t P9N2_PERV_STAT_RDDAT_ERRES_OPB_TIMEOUT_BIT = 10 ;
+static const uint8_t P9N2_PERV_STAT_RDDAT_ERRES_OPB_ERRACK = 11 ;
+static const uint8_t P9N2_PERV_STAT_RDDAT_ERRES_INVALID_ADDRESS = 12 ;
+static const uint8_t P9N2_PERV_STAT_RDDAT_ERRES_PORT_IS_FENCED = 13 ;
+static const uint8_t P9N2_PERV_STAT_RDDAT_ERRES_READ_DATA_VALID = 14 ;
+static const uint8_t P9N2_PERV_STAT_RDDAT_ERRES_OPB_BUSY_FLAG = 15 ;
+static const uint8_t P9N2_PERV_STAT_RDDAT_ERRES_CM_ANY_MASTER_ERROR = 16 ;
+static const uint8_t P9N2_PERV_STAT_RDDAT_ERRES_CM_ANY_PORT_INTERRUPT = 17 ;
+static const uint8_t P9N2_PERV_STAT_RDDAT_ERRES_CM_HOT_PLUG_EVENT = 18 ;
+static const uint8_t P9N2_PERV_STAT_RDDAT_ERRES_CM_CONTROL_REGISTER_PARITY_INTERRUPT = 19 ;
+static const uint8_t P9N2_PERV_STAT_RDDAT_ERRES_CM_ANY_INTR_1_REMOTE_SLAVE_INTERRUPT = 20 ;
+static const uint8_t P9N2_PERV_STAT_RDDAT_ERRES_CM_ANY_INTR_2_REMOTE_SLAVE_INTERRUPT = 21 ;
+static const uint8_t P9N2_PERV_STAT_RDDAT_ERRES_M_ANY_MASTER_ERROR = 24 ;
+static const uint8_t P9N2_PERV_STAT_RDDAT_ERRES_M_ANY_PORT_INTERRUPT = 25 ;
+static const uint8_t P9N2_PERV_STAT_RDDAT_ERRES_M_HOT_PLUG_EVENT = 26 ;
+static const uint8_t P9N2_PERV_STAT_RDDAT_ERRES_M_CONTROL_REGISTER_PARITY_INTERRUPT = 27 ;
+static const uint8_t P9N2_PERV_STAT_RDDAT_ERRES_M_ANY_INTR_1_REMOTE_SLAVE_INTERRUPT = 28 ;
+static const uint8_t P9N2_PERV_STAT_RDDAT_ERRES_M_ANY_INTR_2_REMOTE_SLAVE_INTERRUPT = 29 ;
+static const uint8_t P9N2_PERV_STAT_RDDAT_ERRES_READ_DATA = 32 ;
+static const uint8_t P9N2_PERV_STAT_RDDAT_ERRES_READ_DATA_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_PIB2OPB0_STAT_RDDAT_ERRES_ANY_ERROR = 0 ;
+static const uint8_t P9N2_PERV_PIB2OPB0_STAT_RDDAT_ERRES_CMD_PARITY_ERROR = 1 ;
+static const uint8_t P9N2_PERV_PIB2OPB0_STAT_RDDAT_ERRES_WR_DATA_PARITY_ERROR = 2 ;
+static const uint8_t P9N2_PERV_PIB2OPB0_STAT_RDDAT_ERRES_RD_DATA_PARITY_ERROR = 3 ;
+static const uint8_t P9N2_PERV_PIB2OPB0_STAT_RDDAT_ERRES_LCK_STATUS_PARITY_ERROR = 4 ;
+static const uint8_t P9N2_PERV_PIB2OPB0_STAT_RDDAT_ERRES_FSM_PARITY_ERROR = 5 ;
+static const uint8_t P9N2_PERV_PIB2OPB0_STAT_RDDAT_ERRES_OPB_COMMAND_OVERRUN_ERROR = 7 ;
+static const uint8_t P9N2_PERV_PIB2OPB0_STAT_RDDAT_ERRES_OPB_PARITY_ERROR = 8 ;
+static const uint8_t P9N2_PERV_PIB2OPB0_STAT_RDDAT_ERRES_OPB_PROTOCOL_ERROR = 9 ;
+static const uint8_t P9N2_PERV_PIB2OPB0_STAT_RDDAT_ERRES_OPB_TIMEOUT_BIT = 10 ;
+static const uint8_t P9N2_PERV_PIB2OPB0_STAT_RDDAT_ERRES_OPB_ERRACK = 11 ;
+static const uint8_t P9N2_PERV_PIB2OPB0_STAT_RDDAT_ERRES_INVALID_ADDRESS = 12 ;
+static const uint8_t P9N2_PERV_PIB2OPB0_STAT_RDDAT_ERRES_PORT_IS_FENCED = 13 ;
+static const uint8_t P9N2_PERV_PIB2OPB0_STAT_RDDAT_ERRES_READ_DATA_VALID = 14 ;
+static const uint8_t P9N2_PERV_PIB2OPB0_STAT_RDDAT_ERRES_OPB_BUSY_FLAG = 15 ;
+static const uint8_t P9N2_PERV_PIB2OPB0_STAT_RDDAT_ERRES_CM_ANY_MASTER_ERROR = 16 ;
+static const uint8_t P9N2_PERV_PIB2OPB0_STAT_RDDAT_ERRES_CM_ANY_PORT_INTERRUPT = 17 ;
+static const uint8_t P9N2_PERV_PIB2OPB0_STAT_RDDAT_ERRES_CM_HOT_PLUG_EVENT = 18 ;
+static const uint8_t P9N2_PERV_PIB2OPB0_STAT_RDDAT_ERRES_CM_CONTROL_REGISTER_PARITY_INTERRUPT = 19 ;
+static const uint8_t P9N2_PERV_PIB2OPB0_STAT_RDDAT_ERRES_CM_ANY_INTR_1_REMOTE_SLAVE_INTERRUPT = 20 ;
+static const uint8_t P9N2_PERV_PIB2OPB0_STAT_RDDAT_ERRES_CM_ANY_INTR_2_REMOTE_SLAVE_INTERRUPT = 21 ;
+static const uint8_t P9N2_PERV_PIB2OPB0_STAT_RDDAT_ERRES_M_ANY_MASTER_ERROR = 24 ;
+static const uint8_t P9N2_PERV_PIB2OPB0_STAT_RDDAT_ERRES_M_ANY_PORT_INTERRUPT = 25 ;
+static const uint8_t P9N2_PERV_PIB2OPB0_STAT_RDDAT_ERRES_M_HOT_PLUG_EVENT = 26 ;
+static const uint8_t P9N2_PERV_PIB2OPB0_STAT_RDDAT_ERRES_M_CONTROL_REGISTER_PARITY_INTERRUPT = 27 ;
+static const uint8_t P9N2_PERV_PIB2OPB0_STAT_RDDAT_ERRES_M_ANY_INTR_1_REMOTE_SLAVE_INTERRUPT = 28 ;
+static const uint8_t P9N2_PERV_PIB2OPB0_STAT_RDDAT_ERRES_M_ANY_INTR_2_REMOTE_SLAVE_INTERRUPT = 29 ;
+static const uint8_t P9N2_PERV_PIB2OPB0_STAT_RDDAT_ERRES_READ_DATA = 32 ;
+static const uint8_t P9N2_PERV_PIB2OPB0_STAT_RDDAT_ERRES_READ_DATA_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_1_SUM_MASK_REG_SMASK_IN0 = 0 ;
+static const uint8_t P9N2_PERV_1_SUM_MASK_REG_SMASK_IN1 = 1 ;
+static const uint8_t P9N2_PERV_1_SUM_MASK_REG_SMASK_IN2 = 2 ;
+static const uint8_t P9N2_PERV_1_SUM_MASK_REG_SMASK_IN3 = 3 ;
+static const uint8_t P9N2_PERV_1_SUM_MASK_REG_SMASK_IN4 = 4 ;
+
+static const uint8_t P9N2_PERV_1_SYNC_CONFIG_PULSE_DELAY = 0 ;
+static const uint8_t P9N2_PERV_1_SYNC_CONFIG_PULSE_DELAY_LEN = 4 ;
+static const uint8_t P9N2_PERV_1_SYNC_CONFIG_LISTEN_TO_PULSE_DIS = 4 ;
+static const uint8_t P9N2_PERV_1_SYNC_CONFIG_PULSE_INPUT_SEL = 5 ;
+static const uint8_t P9N2_PERV_1_SYNC_CONFIG_USE_FOR_SCAN = 6 ;
+static const uint8_t P9N2_PERV_1_SYNC_CONFIG_CLEAR_CHIPLET_IS_ALIGNED = 7 ;
+static const uint8_t P9N2_PERV_1_SYNC_CONFIG_UNIT_REGION_CLKCMD_ENABLE = 8 ;
+static const uint8_t P9N2_PERV_1_SYNC_CONFIG_DISABLE_PCB_ITR = 9 ;
+static const uint8_t P9N2_PERV_1_SYNC_CONFIG_ENABLE_VITL_ALIGN_CHECK = 10 ;
+static const uint8_t P9N2_PERV_1_SYNC_CONFIG_PULSE_OUT_DIS = 11 ;
+static const uint8_t P9N2_PERV_1_SYNC_CONFIG_CHKSW_DD1_MODE = 12 ;
+static const uint8_t P9N2_PERV_1_SYNC_CONFIG_CHKSW_DD1_E1 = 13 ;
+static const uint8_t P9N2_PERV_1_SYNC_CONFIG_CHKSW_DD1_E2 = 14 ;
+static const uint8_t P9N2_PERV_1_SYNC_CONFIG_CHKSW_DD1_E3 = 15 ;
+static const uint8_t P9N2_PERV_1_SYNC_CONFIG_PHASE_COUNTER_ON_CLKCHANGE = 16 ;
+static const uint8_t P9N2_PERV_1_SYNC_CONFIG_PHASE_COUNTER_ON_CLKCHANGE_LEN = 8 ;
+
+static const uint8_t P9N2_PERV_1_THERM_MODE_REG_DIS_CPM_BUBBLE_CORR = 0 ;
+static const uint8_t P9N2_PERV_1_THERM_MODE_REG_FORCE_THRES_ACT = 1 ;
+static const uint8_t P9N2_PERV_1_THERM_MODE_REG_THRES_TRIP_ENA = 2 ;
+static const uint8_t P9N2_PERV_1_THERM_MODE_REG_THRES_TRIP_ENA_LEN = 3 ;
+static const uint8_t P9N2_PERV_1_THERM_MODE_REG_DTS_SAMPLE_ENA = 5 ;
+static const uint8_t P9N2_PERV_1_THERM_MODE_REG_SAMPLE_PULSE_CNT = 6 ;
+static const uint8_t P9N2_PERV_1_THERM_MODE_REG_SAMPLE_PULSE_CNT_LEN = 4 ;
+static const uint8_t P9N2_PERV_1_THERM_MODE_REG_THRES_ENA = 10 ;
+static const uint8_t P9N2_PERV_1_THERM_MODE_REG_THRES_ENA_LEN = 2 ;
+static const uint8_t P9N2_PERV_1_THERM_MODE_REG_DTS_TRIGGER = 12 ;
+static const uint8_t P9N2_PERV_1_THERM_MODE_REG_DTS_TRIGGER_SEL = 13 ;
+static const uint8_t P9N2_PERV_1_THERM_MODE_REG_THRES_OVERFLOW_MASK = 14 ;
+static const uint8_t P9N2_PERV_1_THERM_MODE_REG_UNUSED = 15 ;
+static const uint8_t P9N2_PERV_1_THERM_MODE_REG_DTS_READ_SEL = 16 ;
+static const uint8_t P9N2_PERV_1_THERM_MODE_REG_DTS_READ_SEL_LEN = 4 ;
+static const uint8_t P9N2_PERV_1_THERM_MODE_REG_DTS_ENABLE_L1 = 20 ;
+static const uint8_t P9N2_PERV_1_THERM_MODE_REG_DTS_ENABLE_L1_LEN = 2 ;
+static const uint8_t P9N2_PERV_1_THERM_MODE_REG_THERM_CPM_ENABLE_L1 = 35 ;
+static const uint8_t P9N2_PERV_1_THERM_MODE_REG_THERM_CPM_ENABLE_L1_LEN = 2 ;
+
+static const uint8_t P9N2_PERV_TIMEOUT_REG_REGISTER = 0 ;
+static const uint8_t P9N2_PERV_TIMEOUT_REG_REGISTER_LEN = 8 ;
+
+static const uint8_t P9N2_PERV_1_TIMESTAMP_COUNTER_READ_VALUE = 0 ;
+static const uint8_t P9N2_PERV_1_TIMESTAMP_COUNTER_READ_VALUE_LEN = 44 ;
+static const uint8_t P9N2_PERV_1_TIMESTAMP_COUNTER_READ_OVERFLOW_ERR = 44 ;
+
+static const uint8_t P9N2_PERV_TOD_CHIP_CTRL_REG_TIMEBASE_ENABLE = 0 ;
+static const uint8_t P9N2_PERV_TOD_CHIP_CTRL_REG_I_PATH_CORE_SYNC_PERIOD_SELECT = 1 ;
+static const uint8_t P9N2_PERV_TOD_CHIP_CTRL_REG_I_PATH_CORE_SYNC_PERIOD_SELECT_LEN = 3 ;
+static const uint8_t P9N2_PERV_TOD_CHIP_CTRL_REG_I_PATH_SYNC_CHECK_DISABLE = 4 ;
+static const uint8_t P9N2_PERV_TOD_CHIP_CTRL_REG_TX_TTYPE_PIB_MST_FSM_STATE_DISABLE = 5 ;
+static const uint8_t P9N2_PERV_TOD_CHIP_CTRL_REG_RX_TTYPE_1_ON_STEP_ENABLE = 6 ;
+static const uint8_t P9N2_PERV_TOD_CHIP_CTRL_REG_MOVE_TO_TB_ON_2X_SYNC_ENABLE = 7 ;
+static const uint8_t P9N2_PERV_TOD_CHIP_CTRL_REG_USE_TB_SYNC_MECHANISM = 8 ;
+static const uint8_t P9N2_PERV_TOD_CHIP_CTRL_REG_USE_TB_STEP_SYNC = 9 ;
+static const uint8_t P9N2_PERV_TOD_CHIP_CTRL_REG_LOW_ORDER_STEP_VALUE = 10 ;
+static const uint8_t P9N2_PERV_TOD_CHIP_CTRL_REG_LOW_ORDER_STEP_VALUE_LEN = 6 ;
+static const uint8_t P9N2_PERV_TOD_CHIP_CTRL_REG_DISTRIBUTION_BROADCAST_MODE_ENABLE = 16 ;
+static const uint8_t P9N2_PERV_TOD_CHIP_CTRL_REG_0X10_SPARE_17_18 = 17 ;
+static const uint8_t P9N2_PERV_TOD_CHIP_CTRL_REG_0X10_SPARE_17_18_LEN = 2 ;
+static const uint8_t P9N2_PERV_TOD_CHIP_CTRL_REG_0X10_SPARE_19_23 = 19 ;
+static const uint8_t P9N2_PERV_TOD_CHIP_CTRL_REG_0X10_SPARE_19_23_LEN = 5 ;
+static const uint8_t P9N2_PERV_TOD_CHIP_CTRL_REG_0X10_SPARE_24_25 = 24 ;
+static const uint8_t P9N2_PERV_TOD_CHIP_CTRL_REG_0X10_SPARE_24_25_LEN = 2 ;
+static const uint8_t P9N2_PERV_TOD_CHIP_CTRL_REG_TX_TTYPE_PIB_MST_IF_RESET = 26 ;
+static const uint8_t P9N2_PERV_TOD_CHIP_CTRL_REG_0X10_SPARE_27 = 27 ;
+static const uint8_t P9N2_PERV_TOD_CHIP_CTRL_REG_M_PATH_CLOCK_OFF_ENABLE = 28 ;
+static const uint8_t P9N2_PERV_TOD_CHIP_CTRL_REG_0X10_SPARE_29 = 29 ;
+static const uint8_t P9N2_PERV_TOD_CHIP_CTRL_REG_XSTOP_GATE = 30 ;
+static const uint8_t P9N2_PERV_TOD_CHIP_CTRL_REG_STICKY_ERROR_INJECT_ENABLE = 31 ;
+
+static const uint8_t P9N2_PERV_TOD_ERROR_INJECT_REG_0X00_DATA_PARITY = 0 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_INJECT_REG_M_PATH_0_PARITY = 1 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_INJECT_REG_M_PATH_1_PARITY = 2 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_INJECT_REG_0X01_DATA_PARITY = 3 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_INJECT_REG_0X02_DATA_PARITY = 4 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_INJECT_REG_0X03_DATA_PARITY = 5 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_INJECT_REG_0X04_DATA_PARITY = 6 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_INJECT_REG_0X05_DATA_PARITY = 7 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_INJECT_REG_0X06_DATA_PARITY = 8 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_INJECT_REG_0X07_DATA_PARITY = 9 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_INJECT_REG_S_PATH_0_PARITY = 10 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_INJECT_REG_0X08_DATA_PARITY = 11 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_INJECT_REG_0X09_DATA_PARITY = 12 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_INJECT_REG_0X0A_DATA_PARITY = 13 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_INJECT_REG_M_PATH_0_STEP_CHECK = 14 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_INJECT_REG_M_PATH_1_STEP_CHECK = 15 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_INJECT_REG_S_PATH_0_STEP_CHECK = 16 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_INJECT_REG_I_PATH_STEP_CHECK = 17 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_INJECT_REG_PSS_HAM = 18 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_INJECT_REG_0X0B_DATA_PARITY = 19 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_INJECT_REG_S_PATH_1_PARITY = 20 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_INJECT_REG_S_PATH_1_STEP_CHECK = 21 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_INJECT_REG_I_PATH_DELAY_STEP_CHECK_PARITY = 22 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_INJECT_REG_0X0C_DATA_PARITY = 23 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_INJECT_REG_0X11_0X12_0X13_0X14_0X15_0X16_DATA_PARITY = 24 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_INJECT_REG_0X17_0X18_0X21_0X22_DATA_PARITY = 25 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_INJECT_REG_0X1D_0X1E_0X1F_DATA_PARITY = 26 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_INJECT_REG_0X20_DATA_PARITY = 27 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_INJECT_REG_0X23_DATA_PARITY = 28 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_INJECT_REG_0X24_DATA_PARITY = 29 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_INJECT_REG_0X29_DATA_PARITY = 30 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_INJECT_REG_0X30_0X31_0X32_0X33_DATA_PARITY = 31 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_INJECT_REG_0X10_DATA_PARITY = 32 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_INJECT_REG_I_PATH_SYNC_CHECK = 33 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_INJECT_REG_I_PATH_FSM_STATE_PARITY = 34 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_INJECT_REG_I_PATH_TIME_PARITY = 35 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_INJECT_REG_I_PATH_TIME_OVERFLOW = 36 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_INJECT_REG_WOF_LOW_ORDER_STEP_COUNTER_PARITY = 37 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_INJECT_REG_RX_TTYPE_0 = 38 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_INJECT_REG_RX_TTYPE_1 = 39 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_INJECT_REG_RX_TTYPE_2 = 40 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_INJECT_REG_RX_TTYPE_3 = 41 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_INJECT_REG_RX_TTYPE_4 = 42 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_INJECT_REG_RX_TTYPE_5 = 43 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_INJECT_REG_PIB_SLAVE_ADDR_INVALID = 44 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_INJECT_REG_PIB_SLAVE_WRITE_INVALID = 45 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_INJECT_REG_PIB_SLAVE_READ_INVALID = 46 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_INJECT_REG_PIB_SLAVE_ADDR_PARITY = 47 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_INJECT_REG_PIB_SLAVE_DATA_PARITY = 48 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_INJECT_REG_0X27_DATA_PARITY = 49 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_INJECT_REG_PIB_MASTER_RSP_INFO = 50 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_INJECT_REG_PIB_MASTER_RSP_INFO_LEN = 3 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_INJECT_REG_RX_TTYPE_INVALID = 53 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_INJECT_REG_RX_TTYPE_4_DATA_PARITY = 54 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_INJECT_REG_PIB_MASTER_REQUEST = 55 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_INJECT_REG_PIB_RESET_DURING_PIB_ACCESS = 56 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_INJECT_REG_EXTERNAL_XSTOP = 57 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_INJECT_REG_SPARE_58 = 58 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_INJECT_REG_SPARE_59 = 59 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_INJECT_REG_SPARE_60 = 60 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_INJECT_REG_SPARE_61 = 61 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_INJECT_REG_OSCSWITCH_INTERRUPT = 62 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_INJECT_REG_CORE_STEP = 63 ;
+
+static const uint8_t P9N2_PERV_TOD_ERROR_MASK_REG_0X00_DATA_PARITY = 0 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_MASK_REG_M_PATH_0_PARITY = 1 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_MASK_REG_M_PATH_1_PARITY = 2 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_MASK_REG_0X01_DATA_PARITY = 3 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_MASK_REG_0X02_DATA_PARITY = 4 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_MASK_REG_0X03_DATA_PARITY = 5 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_MASK_REG_0X04_DATA_PARITY = 6 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_MASK_REG_0X05_DATA_PARITY = 7 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_MASK_REG_0X06_DATA_PARITY = 8 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_MASK_REG_0X07_DATA_PARITY = 9 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_MASK_REG_S_PATH_0_PARITY = 10 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_MASK_REG_0X08_DATA_PARITY = 11 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_MASK_REG_0X09_DATA_PARITY = 12 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_MASK_REG_0X0A_DATA_PARITY = 13 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_MASK_REG_M_PATH_0_STEP_CHECK = 14 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_MASK_REG_M_PATH_1_STEP_CHECK = 15 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_MASK_REG_S_PATH_0_STEP_CHECK = 16 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_MASK_REG_I_PATH_STEP_CHECK = 17 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_MASK_REG_PSS_HAM = 18 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_MASK_REG_0X0B_DATA_PARITY = 19 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_MASK_REG_S_PATH_1_PARITY = 20 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_MASK_REG_S_PATH_1_STEP_CHECK = 21 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_MASK_REG_I_PATH_DELAY_STEP_CHECK_PARITY = 22 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_MASK_REG_0X0C_DATA_PARITY = 23 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_MASK_REG_0X11_0X12_0X13_0X14_0X15_0X16_DATA_PARITY = 24 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_MASK_REG_0X17_0X18_0X21_0X22_DATA_PARITY = 25 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_MASK_REG_0X1D_0X1E_0X1F_DATA_PARITY = 26 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_MASK_REG_0X20_DATA_PARITY = 27 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_MASK_REG_0X23_DATA_PARITY = 28 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_MASK_REG_0X24_DATA_PARITY = 29 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_MASK_REG_0X29_DATA_PARITY = 30 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_MASK_REG_0X30_0X31_0X32_0X33_DATA_PARITY = 31 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_MASK_REG_0X10_DATA_PARITY = 32 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_MASK_REG_I_PATH_SYNC_CHECK = 33 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_MASK_REG_I_PATH_FSM_STATE_PARITY = 34 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_MASK_REG_I_PATH_TIME_PARITY = 35 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_MASK_REG_I_PATH_TIME_OVERFLOW = 36 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_MASK_REG_WOF_LOW_ORDER_STEP_COUNTER_PARITY = 37 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_MASK_REG_RX_TTYPE_0 = 38 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_MASK_REG_RX_TTYPE_1 = 39 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_MASK_REG_RX_TTYPE_2 = 40 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_MASK_REG_RX_TTYPE_3 = 41 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_MASK_REG_RX_TTYPE_4 = 42 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_MASK_REG_RX_TTYPE_5 = 43 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_MASK_REG_PIB_SLAVE_ADDR_INVALID = 44 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_MASK_REG_PIB_SLAVE_WRITE_INVALID = 45 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_MASK_REG_PIB_SLAVE_READ_INVALID = 46 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_MASK_REG_PIB_SLAVE_ADDR_PARITY = 47 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_MASK_REG_PIB_SLAVE_DATA_PARITY = 48 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_MASK_REG_0X27_DATA_PARITY = 49 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_MASK_REG_PIB_MASTER_RSP_INFO = 50 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_MASK_REG_PIB_MASTER_RSP_INFO_LEN = 3 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_MASK_REG_RX_TTYPE_INVALID = 53 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_MASK_REG_RX_TTYPE_4_DATA_PARITY = 54 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_MASK_REG_PIB_MASTER_REQUEST = 55 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_MASK_REG_PIB_RESET_DURING_PIB_ACCESS = 56 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_MASK_REG_EXTERNAL_XSTOP = 57 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_MASK_REG_SPARE_58 = 58 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_MASK_REG_SPARE_59 = 59 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_MASK_REG_SPARE_60 = 60 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_MASK_REG_SPARE_61 = 61 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_MASK_REG_OSCSWITCH_INTERRUPT = 62 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_MASK_REG_SPARE_63 = 63 ;
+
+static const uint8_t P9N2_PERV_TOD_ERROR_REG_0X00_DATA_PARITY = 0 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_REG_M_PATH_0_PARITY = 1 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_REG_M_PATH_1_PARITY = 2 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_REG_0X01_DATA_PARITY = 3 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_REG_0X02_DATA_PARITY = 4 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_REG_0X03_DATA_PARITY = 5 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_REG_0X04_DATA_PARITY = 6 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_REG_0X05_DATA_PARITY = 7 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_REG_0X06_DATA_PARITY = 8 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_REG_0X07_DATA_PARITY = 9 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_REG_S_PATH_0_PARITY = 10 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_REG_0X08_DATA_PARITY = 11 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_REG_0X09_DATA_PARITY = 12 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_REG_0X0A_DATA_PARITY = 13 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_REG_M_PATH_0_STEP_CHECK = 14 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_REG_M_PATH_1_STEP_CHECK = 15 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_REG_S_PATH_0_STEP_CHECK = 16 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_REG_I_PATH_STEP_CHECK = 17 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_REG_PSS_HAM = 18 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_REG_0X0B_DATA_PARITY = 19 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_REG_S_PATH_1_PARITY = 20 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_REG_S_PATH_1_STEP_CHECK = 21 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_REG_I_PATH_DELAY_STEP_CHECK_PARITY = 22 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_REG_0X0C_DATA_PARITY = 23 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_REG_0X11_0X12_0X13_0X14_0X15_0X16_DATA_PARITY = 24 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_REG_0X17_0X18_0X21_0X22_DATA_PARITY = 25 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_REG_0X1D_0X1E_0X1F_DATA_PARITY = 26 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_REG_0X20_DATA_PARITY = 27 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_REG_0X23_DATA_PARITY = 28 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_REG_0X24_DATA_PARITY = 29 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_REG_0X29_DATA_PARITY = 30 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_REG_0X30_0X31_0X32_0X33_DATA_PARITY = 31 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_REG_0X10_DATA_PARITY = 32 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_REG_I_PATH_SYNC_CHECK = 33 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_REG_I_PATH_FSM_STATE_PARITY = 34 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_REG_I_PATH_TIME_PARITY = 35 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_REG_I_PATH_TIME_OVERFLOW = 36 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_REG_WOF_LOW_ORDER_STEP_COUNTER_PARITY = 37 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_REG_RX_TTYPE_0 = 38 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_REG_RX_TTYPE_1 = 39 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_REG_RX_TTYPE_2 = 40 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_REG_RX_TTYPE_3 = 41 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_REG_RX_TTYPE_4 = 42 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_REG_RX_TTYPE_5 = 43 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_REG_PIB_SLAVE_ADDR_INVALID = 44 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_REG_PIB_SLAVE_WRITE_INVALID = 45 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_REG_PIB_SLAVE_READ_INVALID = 46 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_REG_PIB_SLAVE_ADDR_PARITY = 47 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_REG_PIB_SLAVE_DATA_PARITY = 48 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_REG_0X27_DATA_PARITY = 49 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_REG_PIB_MASTER_RSP_INFO = 50 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_REG_PIB_MASTER_RSP_INFO_LEN = 3 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_REG_RX_TTYPE_INVALID = 53 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_REG_RX_TTYPE_4_DATA_PARITY = 54 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_REG_PIB_MASTER_REQUEST = 55 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_REG_PIB_RESET_DURING_PIB_ACCESS = 56 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_REG_EXTERNAL_XSTOP = 57 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_REG_SPARE_58 = 58 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_REG_SPARE_59 = 59 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_REG_SPARE_60 = 60 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_REG_SPARE_61 = 61 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_REG_OSCSWITCH_INTERRUPT = 62 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_REG_SPARE_63 = 63 ;
+
+static const uint8_t P9N2_PERV_TOD_ERROR_ROUTING_REG_0X00_DATA_PARITY = 0 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_ROUTING_REG_M_PATH_0_PARITY = 1 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_ROUTING_REG_M_PATH_1_PARITY = 2 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_ROUTING_REG_0X01_DATA_PARITY = 3 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_ROUTING_REG_0X02_DATA_PARITY = 4 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_ROUTING_REG_0X03_DATA_PARITY = 5 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_ROUTING_REG_0X04_DATA_PARITY = 6 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_ROUTING_REG_0X05_DATA_PARITY = 7 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_ROUTING_REG_0X06_DATA_PARITY = 8 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_ROUTING_REG_0X07_DATA_PARITY = 9 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_ROUTING_REG_S_PATH_0_PARITY = 10 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_ROUTING_REG_0X08_DATA_PARITY = 11 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_ROUTING_REG_0X09_DATA_PARITY = 12 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_ROUTING_REG_0X0A_DATA_PARITY = 13 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_ROUTING_REG_M_PATH_0_STEP_CHECK = 14 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_ROUTING_REG_M_PATH_1_STEP_CHECK = 15 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_ROUTING_REG_S_PATH_0_STEP_CHECK = 16 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_ROUTING_REG_I_PATH_STEP_CHECK = 17 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_ROUTING_REG_PSS_HAM_CORE_INTERRUPT_MASK = 18 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_ROUTING_REG_0X0B_DATA_PARITY = 19 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_ROUTING_REG_S_PATH_1_PARITY = 20 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_ROUTING_REG_S_PATH_1_STEP_CHECK = 21 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_ROUTING_REG_I_PATH_DELAY_STEP_CHECK_PARITY = 22 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_ROUTING_REG_0X0C_DATA_PARITY = 23 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_ROUTING_REG_0X11_0X12_0X13_0X14_0X15_0X16_DATA_PARITY = 24 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_ROUTING_REG_0X17_0X18_0X21_0X22_DATA_PARITY = 25 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_ROUTING_REG_0X1D_0X1E_0X1F_DATA_PARITY = 26 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_ROUTING_REG_0X20_DATA_PARITY = 27 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_ROUTING_REG_0X23_DATA_PARITY = 28 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_ROUTING_REG_0X24_DATA_PARITY = 29 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_ROUTING_REG_0X29_DATA_PARITY = 30 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_ROUTING_REG_0X30_0X31_0X32_0X33_DATA_PARITY = 31 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_ROUTING_REG_0X10_DATA_PARITY = 32 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_ROUTING_REG_I_PATH_SYNC_CHECK = 33 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_ROUTING_REG_I_PATH_FSM_STATE_PARITY = 34 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_ROUTING_REG_I_PATH_TIME_PARITY = 35 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_ROUTING_REG_I_PATH_TIME_OVERFLOW_CORE_INTERRUPT = 36 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_ROUTING_REG_WOF_LOW_ORDER_STEP_COUNTER_PARITY = 37 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_ROUTING_REG_RX_TTYPE_0 = 38 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_ROUTING_REG_RX_TTYPE_1 = 39 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_ROUTING_REG_RX_TTYPE_2 = 40 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_ROUTING_REG_RX_TTYPE_3 = 41 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_ROUTING_REG_RX_TTYPE_4 = 42 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_ROUTING_REG_RX_TTYPE_5 = 43 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_ROUTING_REG_PIB_SLAVE_ADDR_INVALID = 44 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_ROUTING_REG_PIB_SLAVE_WRITE_INVALID = 45 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_ROUTING_REG_PIB_SLAVE_READ_INVALID = 46 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_ROUTING_REG_PIB_SLAVE_ADDR_PARITY = 47 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_ROUTING_REG_PIB_SLAVE_DATA_PARITY = 48 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_ROUTING_REG_0X27_DATA_PARITY = 49 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_ROUTING_REG_PIB_MASTER_RSP_INFO = 50 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_ROUTING_REG_PIB_MASTER_RSP_INFO_LEN = 3 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_ROUTING_REG_RX_TTYPE_INVALID = 53 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_ROUTING_REG_RX_TTYPE_4_DATA_PARITY = 54 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_ROUTING_REG_PIB_MASTER_REQUEST = 55 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_ROUTING_REG_PIB_RESET_DURING_PIB_ACCESS = 56 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_ROUTING_REG_EXTERNAL_XSTOP = 57 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_ROUTING_REG_SPARE_58 = 58 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_ROUTING_REG_SPARE_59 = 59 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_ROUTING_REG_SPARE_60 = 60 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_ROUTING_REG_SPARE_61 = 61 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_ROUTING_REG_OSCSWITCH_INTERRUPT = 62 ;
+static const uint8_t P9N2_PERV_TOD_ERROR_ROUTING_REG_SPARE_63 = 63 ;
+
+static const uint8_t P9N2_PERV_TOD_FSM_REG_I_PATH_STATE = 0 ;
+static const uint8_t P9N2_PERV_TOD_FSM_REG_I_PATH_STATE_LEN = 4 ;
+static const uint8_t P9N2_PERV_TOD_FSM_REG_IS_RUNNING = 4 ;
+static const uint8_t P9N2_PERV_TOD_FSM_REG_0X24_SPARE_05_07 = 5 ;
+static const uint8_t P9N2_PERV_TOD_FSM_REG_0X24_SPARE_05_07_LEN = 3 ;
+
+static const uint8_t P9N2_PERV_TOD_I_PATH_CTRL_REG_DELAY_DISABLE = 0 ;
+static const uint8_t P9N2_PERV_TOD_I_PATH_CTRL_REG_DELAY_ADJUST_DISABLE = 1 ;
+static const uint8_t P9N2_PERV_TOD_I_PATH_CTRL_REG_0X06_SPARE_02_04 = 2 ;
+static const uint8_t P9N2_PERV_TOD_I_PATH_CTRL_REG_0X06_SPARE_02_04_LEN = 3 ;
+static const uint8_t P9N2_PERV_TOD_I_PATH_CTRL_REG_STEP_CHECK_STEP_SELECT = 5 ;
+static const uint8_t P9N2_PERV_TOD_I_PATH_CTRL_REG_STEP_CHECK_CPS_DEVIATION_FACTOR = 6 ;
+static const uint8_t P9N2_PERV_TOD_I_PATH_CTRL_REG_STEP_CHECK_CPS_DEVIATION_FACTOR_LEN = 2 ;
+static const uint8_t P9N2_PERV_TOD_I_PATH_CTRL_REG_STEP_CHECK_CPS_DEVIATION = 8 ;
+static const uint8_t P9N2_PERV_TOD_I_PATH_CTRL_REG_STEP_CHECK_CPS_DEVIATION_LEN = 4 ;
+static const uint8_t P9N2_PERV_TOD_I_PATH_CTRL_REG_STEP_CHECK_CONSTANT_CPS_ENABLE = 12 ;
+static const uint8_t P9N2_PERV_TOD_I_PATH_CTRL_REG_STEP_CHECK_VALIDITY_COUNT = 13 ;
+static const uint8_t P9N2_PERV_TOD_I_PATH_CTRL_REG_STEP_CHECK_VALIDITY_COUNT_LEN = 3 ;
+static const uint8_t P9N2_PERV_TOD_I_PATH_CTRL_REG_0X06_SPARE_16_21 = 16 ;
+static const uint8_t P9N2_PERV_TOD_I_PATH_CTRL_REG_0X06_SPARE_16_21_LEN = 6 ;
+static const uint8_t P9N2_PERV_TOD_I_PATH_CTRL_REG_DELAY_ADJUST_VALUE = 22 ;
+static const uint8_t P9N2_PERV_TOD_I_PATH_CTRL_REG_DELAY_ADJUST_VALUE_LEN = 10 ;
+static const uint8_t P9N2_PERV_TOD_I_PATH_CTRL_REG_CPS = 32 ;
+static const uint8_t P9N2_PERV_TOD_I_PATH_CTRL_REG_CPS_LEN = 8 ;
+
+static const uint8_t P9N2_PERV_TOD_LOAD_TOD_MOD_REG_FSM_TRIGGER = 0 ;
+static const uint8_t P9N2_PERV_TOD_LOAD_TOD_MOD_REG_FSM_SYNC_ENABLE = 1 ;
+
+static const uint8_t P9N2_PERV_TOD_LOAD_TOD_REG_VALUE = 0 ;
+static const uint8_t P9N2_PERV_TOD_LOAD_TOD_REG_VALUE_LEN = 60 ;
+static const uint8_t P9N2_PERV_TOD_LOAD_TOD_REG_WOF = 60 ;
+static const uint8_t P9N2_PERV_TOD_LOAD_TOD_REG_WOF_LEN = 4 ;
+
+static const uint8_t P9N2_PERV_TOD_LOW_ORDER_STEP_REG_COUNTER_VALUE = 0 ;
+static const uint8_t P9N2_PERV_TOD_LOW_ORDER_STEP_REG_COUNTER_VALUE_LEN = 6 ;
+static const uint8_t P9N2_PERV_TOD_LOW_ORDER_STEP_REG_0X23_SPARE_06_07 = 6 ;
+static const uint8_t P9N2_PERV_TOD_LOW_ORDER_STEP_REG_0X23_SPARE_06_07_LEN = 2 ;
+
+static const uint8_t P9N2_PERV_TOD_MISC_RESET_REG_M_PATH_0_STEP_CREATE_THRESHOLD_ENABLE = 0 ;
+static const uint8_t P9N2_PERV_TOD_MISC_RESET_REG_M_PATH_0_STEP_ALIGN_THRESHOLD_ENABLE = 1 ;
+static const uint8_t P9N2_PERV_TOD_MISC_RESET_REG_M_PATH_1_STEP_CREATE_THRESHOLD_ENABLE = 2 ;
+static const uint8_t P9N2_PERV_TOD_MISC_RESET_REG_M_PATH_1_STEP_ALIGN_THRESHOLD_ENABLE = 3 ;
+static const uint8_t P9N2_PERV_TOD_MISC_RESET_REG_0X0B_SPARE_04_05 = 4 ;
+static const uint8_t P9N2_PERV_TOD_MISC_RESET_REG_0X0B_SPARE_04_05_LEN = 2 ;
+static const uint8_t P9N2_PERV_TOD_MISC_RESET_REG_DISTR_STEP_SYNC_TX_SYNC_DISABLE = 6 ;
+static const uint8_t P9N2_PERV_TOD_MISC_RESET_REG_CORE_STEP_SYNC_TX_SYNC_DISABLE = 7 ;
+static const uint8_t P9N2_PERV_TOD_MISC_RESET_REG_PROBE_0_TOGGLE_ENABLE = 8 ;
+static const uint8_t P9N2_PERV_TOD_MISC_RESET_REG_PROBE_1_TOGGLE_ENABLE = 9 ;
+static const uint8_t P9N2_PERV_TOD_MISC_RESET_REG_PROBE_2_TOGGLE_ENABLE = 10 ;
+static const uint8_t P9N2_PERV_TOD_MISC_RESET_REG_PROBE_3_TOGGLE_ENABLE = 11 ;
+static const uint8_t P9N2_PERV_TOD_MISC_RESET_REG_DISTR_STEP_SYNC_TX_DISABLE = 12 ;
+static const uint8_t P9N2_PERV_TOD_MISC_RESET_REG_DISTR_STEP_SYNC_TX_TRIGGER = 13 ;
+static const uint8_t P9N2_PERV_TOD_MISC_RESET_REG_CORE_STEP_SYNC_TX_ENABLE = 14 ;
+static const uint8_t P9N2_PERV_TOD_MISC_RESET_REG_CORE_STEP_SYNC_TX_TRIGGER = 15 ;
+static const uint8_t P9N2_PERV_TOD_MISC_RESET_REG_TRACE_ENABLE = 16 ;
+static const uint8_t P9N2_PERV_TOD_MISC_RESET_REG_0X0B_SPARE_17 = 17 ;
+static const uint8_t P9N2_PERV_TOD_MISC_RESET_REG_TRACE_DATA_SELECT = 18 ;
+static const uint8_t P9N2_PERV_TOD_MISC_RESET_REG_TRACE_DATA_SELECT_LEN = 2 ;
+static const uint8_t P9N2_PERV_TOD_MISC_RESET_REG_M_PATH_0_SYNC_CREATE_COUNTER_ENABLE = 20 ;
+static const uint8_t P9N2_PERV_TOD_MISC_RESET_REG_M_PATH_1_SYNC_CREATE_COUNTER_ENABLE = 21 ;
+static const uint8_t P9N2_PERV_TOD_MISC_RESET_REG_I_PATH_DELAY_TWOS_COMPL_LOAD = 22 ;
+static const uint8_t P9N2_PERV_TOD_MISC_RESET_REG_I_PATH_DELAY_ADJUST = 23 ;
+static const uint8_t P9N2_PERV_TOD_MISC_RESET_REG_I_PATH_DELAY_TWOS_COMPL_LOAD_VALUE = 24 ;
+static const uint8_t P9N2_PERV_TOD_MISC_RESET_REG_I_PATH_DELAY_TWOS_COMPL_LOAD_VALUE_LEN = 9 ;
+static const uint8_t P9N2_PERV_TOD_MISC_RESET_REG_0X0B_SPARE_33_39 = 33 ;
+static const uint8_t P9N2_PERV_TOD_MISC_RESET_REG_0X0B_SPARE_33_39_LEN = 7 ;
+
+static const uint8_t P9N2_PERV_TOD_MOVE_TOD_TO_TB_REG_TRIGGER = 0 ;
+
+static const uint8_t P9N2_PERV_TOD_M_PATH_0_STEP_STEER_REG_MODE = 0 ;
+static const uint8_t P9N2_PERV_TOD_M_PATH_0_STEP_STEER_REG_RATE = 1 ;
+static const uint8_t P9N2_PERV_TOD_M_PATH_0_STEP_STEER_REG_RATE_LEN = 31 ;
+static const uint8_t P9N2_PERV_TOD_M_PATH_0_STEP_STEER_REG_COUNTER_LOAD_FLAG = 32 ;
+static const uint8_t P9N2_PERV_TOD_M_PATH_0_STEP_STEER_REG_COUNTER_LOAD_VALUE = 33 ;
+static const uint8_t P9N2_PERV_TOD_M_PATH_0_STEP_STEER_REG_COUNTER_LOAD_VALUE_LEN = 31 ;
+
+static const uint8_t P9N2_PERV_TOD_M_PATH_1_STEP_STEER_REG_MODE = 0 ;
+static const uint8_t P9N2_PERV_TOD_M_PATH_1_STEP_STEER_REG_RATE = 1 ;
+static const uint8_t P9N2_PERV_TOD_M_PATH_1_STEP_STEER_REG_RATE_LEN = 31 ;
+static const uint8_t P9N2_PERV_TOD_M_PATH_1_STEP_STEER_REG_COUNTER_LOAD_FLAG = 32 ;
+static const uint8_t P9N2_PERV_TOD_M_PATH_1_STEP_STEER_REG_COUNTER_LOAD_VALUE = 33 ;
+static const uint8_t P9N2_PERV_TOD_M_PATH_1_STEP_STEER_REG_COUNTER_LOAD_VALUE_LEN = 31 ;
+
+static const uint8_t P9N2_PERV_TOD_M_PATH_CTRL_REG_0_OSC_NOT_VALID = 0 ;
+static const uint8_t P9N2_PERV_TOD_M_PATH_CTRL_REG_1_OSC_NOT_VALID = 1 ;
+static const uint8_t P9N2_PERV_TOD_M_PATH_CTRL_REG_0_STEP_ALIGN_DISABLE = 2 ;
+static const uint8_t P9N2_PERV_TOD_M_PATH_CTRL_REG_1_STEP_ALIGN_DISABLE = 3 ;
+static const uint8_t P9N2_PERV_TOD_M_PATH_CTRL_REG_STEP_CREATE_DUAL_EDGE_DISABLE = 4 ;
+static const uint8_t P9N2_PERV_TOD_M_PATH_CTRL_REG_SYNC_CREATE_SPS_SELECT = 5 ;
+static const uint8_t P9N2_PERV_TOD_M_PATH_CTRL_REG_SYNC_CREATE_SPS_SELECT_LEN = 3 ;
+static const uint8_t P9N2_PERV_TOD_M_PATH_CTRL_REG_0_STEP_CHECK_CPS_DEVIATION = 8 ;
+static const uint8_t P9N2_PERV_TOD_M_PATH_CTRL_REG_0_STEP_CHECK_CPS_DEVIATION_LEN = 4 ;
+static const uint8_t P9N2_PERV_TOD_M_PATH_CTRL_REG_0_STEP_CHECK_CONSTANT_CPS_ENABLE = 12 ;
+static const uint8_t P9N2_PERV_TOD_M_PATH_CTRL_REG_0_STEP_CHECK_VALIDITY_COUNT = 13 ;
+static const uint8_t P9N2_PERV_TOD_M_PATH_CTRL_REG_0_STEP_CHECK_VALIDITY_COUNT_LEN = 3 ;
+static const uint8_t P9N2_PERV_TOD_M_PATH_CTRL_REG_1_STEP_CHECK_CPS_DEVIATION = 16 ;
+static const uint8_t P9N2_PERV_TOD_M_PATH_CTRL_REG_1_STEP_CHECK_CPS_DEVIATION_LEN = 4 ;
+static const uint8_t P9N2_PERV_TOD_M_PATH_CTRL_REG_1_STEP_CHECK_CONSTANT_CPS_ENABLE = 20 ;
+static const uint8_t P9N2_PERV_TOD_M_PATH_CTRL_REG_1_STEP_CHECK_VALIDITY_COUNT = 21 ;
+static const uint8_t P9N2_PERV_TOD_M_PATH_CTRL_REG_1_STEP_CHECK_VALIDITY_COUNT_LEN = 3 ;
+static const uint8_t P9N2_PERV_TOD_M_PATH_CTRL_REG_STEP_CHECK_CPS_DEVIATION_FACTOR = 24 ;
+static const uint8_t P9N2_PERV_TOD_M_PATH_CTRL_REG_STEP_CHECK_CPS_DEVIATION_FACTOR_LEN = 2 ;
+static const uint8_t P9N2_PERV_TOD_M_PATH_CTRL_REG_0_LOCAL_STEP_MODE_ENABLE = 26 ;
+static const uint8_t P9N2_PERV_TOD_M_PATH_CTRL_REG_1_LOCAL_STEP_MODE_ENABLE = 27 ;
+static const uint8_t P9N2_PERV_TOD_M_PATH_CTRL_REG_0_STEP_STEER_ENABLE = 28 ;
+static const uint8_t P9N2_PERV_TOD_M_PATH_CTRL_REG_1_STEP_STEER_ENABLE = 29 ;
+static const uint8_t P9N2_PERV_TOD_M_PATH_CTRL_REG_0_STEP_ALIGN_CLKGATE_DISABLE = 30 ;
+static const uint8_t P9N2_PERV_TOD_M_PATH_CTRL_REG_1_STEP_ALIGN_CLKGATE_DISABLE = 31 ;
+
+static const uint8_t P9N2_PERV_TOD_M_PATH_STATUS_REG_0_STEP_ALIGN_THRESHOLD = 0 ;
+static const uint8_t P9N2_PERV_TOD_M_PATH_STATUS_REG_0_STEP_ALIGN_THRESHOLD_LEN = 8 ;
+static const uint8_t P9N2_PERV_TOD_M_PATH_STATUS_REG_0_CPS = 8 ;
+static const uint8_t P9N2_PERV_TOD_M_PATH_STATUS_REG_0_CPS_LEN = 8 ;
+static const uint8_t P9N2_PERV_TOD_M_PATH_STATUS_REG_1_STEP_ALIGN_THRESHOLD = 16 ;
+static const uint8_t P9N2_PERV_TOD_M_PATH_STATUS_REG_1_STEP_ALIGN_THRESHOLD_LEN = 8 ;
+static const uint8_t P9N2_PERV_TOD_M_PATH_STATUS_REG_1_CPS = 24 ;
+static const uint8_t P9N2_PERV_TOD_M_PATH_STATUS_REG_1_CPS_LEN = 8 ;
+
+static const uint8_t P9N2_PERV_TOD_PRI_PORT_0_CTRL_REG_RX_SELECT = 0 ;
+static const uint8_t P9N2_PERV_TOD_PRI_PORT_0_CTRL_REG_RX_SELECT_LEN = 3 ;
+static const uint8_t P9N2_PERV_TOD_PRI_PORT_0_CTRL_REG_0X01_SPARE_03 = 3 ;
+static const uint8_t P9N2_PERV_TOD_PRI_PORT_0_CTRL_REG_X0_TX_SELECT = 4 ;
+static const uint8_t P9N2_PERV_TOD_PRI_PORT_0_CTRL_REG_X0_TX_SELECT_LEN = 2 ;
+static const uint8_t P9N2_PERV_TOD_PRI_PORT_0_CTRL_REG_X1_TX_SELECT = 6 ;
+static const uint8_t P9N2_PERV_TOD_PRI_PORT_0_CTRL_REG_X1_TX_SELECT_LEN = 2 ;
+static const uint8_t P9N2_PERV_TOD_PRI_PORT_0_CTRL_REG_X2_TX_SELECT = 8 ;
+static const uint8_t P9N2_PERV_TOD_PRI_PORT_0_CTRL_REG_X2_TX_SELECT_LEN = 2 ;
+static const uint8_t P9N2_PERV_TOD_PRI_PORT_0_CTRL_REG_X3_TX_SELECT = 10 ;
+static const uint8_t P9N2_PERV_TOD_PRI_PORT_0_CTRL_REG_X3_TX_SELECT_LEN = 2 ;
+static const uint8_t P9N2_PERV_TOD_PRI_PORT_0_CTRL_REG_X4_TX_SELECT = 12 ;
+static const uint8_t P9N2_PERV_TOD_PRI_PORT_0_CTRL_REG_X4_TX_SELECT_LEN = 2 ;
+static const uint8_t P9N2_PERV_TOD_PRI_PORT_0_CTRL_REG_X5_TX_SELECT = 14 ;
+static const uint8_t P9N2_PERV_TOD_PRI_PORT_0_CTRL_REG_X5_TX_SELECT_LEN = 2 ;
+static const uint8_t P9N2_PERV_TOD_PRI_PORT_0_CTRL_REG_X6_TX_SELECT = 16 ;
+static const uint8_t P9N2_PERV_TOD_PRI_PORT_0_CTRL_REG_X6_TX_SELECT_LEN = 2 ;
+static const uint8_t P9N2_PERV_TOD_PRI_PORT_0_CTRL_REG_X7_TX_SELECT = 18 ;
+static const uint8_t P9N2_PERV_TOD_PRI_PORT_0_CTRL_REG_X7_TX_SELECT_LEN = 2 ;
+static const uint8_t P9N2_PERV_TOD_PRI_PORT_0_CTRL_REG_X0_TX_ENABLE = 20 ;
+static const uint8_t P9N2_PERV_TOD_PRI_PORT_0_CTRL_REG_X1_TX_ENABLE = 21 ;
+static const uint8_t P9N2_PERV_TOD_PRI_PORT_0_CTRL_REG_X2_TX_ENABLE = 22 ;
+static const uint8_t P9N2_PERV_TOD_PRI_PORT_0_CTRL_REG_X3_TX_ENABLE = 23 ;
+static const uint8_t P9N2_PERV_TOD_PRI_PORT_0_CTRL_REG_X4_TX_ENABLE = 24 ;
+static const uint8_t P9N2_PERV_TOD_PRI_PORT_0_CTRL_REG_X5_TX_ENABLE = 25 ;
+static const uint8_t P9N2_PERV_TOD_PRI_PORT_0_CTRL_REG_X6_TX_ENABLE = 26 ;
+static const uint8_t P9N2_PERV_TOD_PRI_PORT_0_CTRL_REG_X7_TX_ENABLE = 27 ;
+static const uint8_t P9N2_PERV_TOD_PRI_PORT_0_CTRL_REG_0X01_SPARE_28_31 = 28 ;
+static const uint8_t P9N2_PERV_TOD_PRI_PORT_0_CTRL_REG_0X01_SPARE_28_31_LEN = 4 ;
+static const uint8_t P9N2_PERV_TOD_PRI_PORT_0_CTRL_REG_I_PATH_DELAY_VALUE = 32 ;
+static const uint8_t P9N2_PERV_TOD_PRI_PORT_0_CTRL_REG_I_PATH_DELAY_VALUE_LEN = 8 ;
+
+static const uint8_t P9N2_PERV_TOD_PRI_PORT_1_CTRL_REG_RX_SELECT = 0 ;
+static const uint8_t P9N2_PERV_TOD_PRI_PORT_1_CTRL_REG_RX_SELECT_LEN = 3 ;
+static const uint8_t P9N2_PERV_TOD_PRI_PORT_1_CTRL_REG_0X02_SPARE_03 = 3 ;
+static const uint8_t P9N2_PERV_TOD_PRI_PORT_1_CTRL_REG_X0_TX_SELECT = 4 ;
+static const uint8_t P9N2_PERV_TOD_PRI_PORT_1_CTRL_REG_X0_TX_SELECT_LEN = 2 ;
+static const uint8_t P9N2_PERV_TOD_PRI_PORT_1_CTRL_REG_X1_TX_SELECT = 6 ;
+static const uint8_t P9N2_PERV_TOD_PRI_PORT_1_CTRL_REG_X1_TX_SELECT_LEN = 2 ;
+static const uint8_t P9N2_PERV_TOD_PRI_PORT_1_CTRL_REG_X2_TX_SELECT = 8 ;
+static const uint8_t P9N2_PERV_TOD_PRI_PORT_1_CTRL_REG_X2_TX_SELECT_LEN = 2 ;
+static const uint8_t P9N2_PERV_TOD_PRI_PORT_1_CTRL_REG_X3_TX_SELECT = 10 ;
+static const uint8_t P9N2_PERV_TOD_PRI_PORT_1_CTRL_REG_X3_TX_SELECT_LEN = 2 ;
+static const uint8_t P9N2_PERV_TOD_PRI_PORT_1_CTRL_REG_X4_TX_SELECT = 12 ;
+static const uint8_t P9N2_PERV_TOD_PRI_PORT_1_CTRL_REG_X4_TX_SELECT_LEN = 2 ;
+static const uint8_t P9N2_PERV_TOD_PRI_PORT_1_CTRL_REG_X5_TX_SELECT = 14 ;
+static const uint8_t P9N2_PERV_TOD_PRI_PORT_1_CTRL_REG_X5_TX_SELECT_LEN = 2 ;
+static const uint8_t P9N2_PERV_TOD_PRI_PORT_1_CTRL_REG_X6_TX_SELECT = 16 ;
+static const uint8_t P9N2_PERV_TOD_PRI_PORT_1_CTRL_REG_X6_TX_SELECT_LEN = 2 ;
+static const uint8_t P9N2_PERV_TOD_PRI_PORT_1_CTRL_REG_X7_TX_SELECT = 18 ;
+static const uint8_t P9N2_PERV_TOD_PRI_PORT_1_CTRL_REG_X7_TX_SELECT_LEN = 2 ;
+static const uint8_t P9N2_PERV_TOD_PRI_PORT_1_CTRL_REG_X0_TX_ENABLE = 20 ;
+static const uint8_t P9N2_PERV_TOD_PRI_PORT_1_CTRL_REG_X1_TX_ENABLE = 21 ;
+static const uint8_t P9N2_PERV_TOD_PRI_PORT_1_CTRL_REG_X2_TX_ENABLE = 22 ;
+static const uint8_t P9N2_PERV_TOD_PRI_PORT_1_CTRL_REG_X3_TX_ENABLE = 23 ;
+static const uint8_t P9N2_PERV_TOD_PRI_PORT_1_CTRL_REG_X4_TX_ENABLE = 24 ;
+static const uint8_t P9N2_PERV_TOD_PRI_PORT_1_CTRL_REG_X5_TX_ENABLE = 25 ;
+static const uint8_t P9N2_PERV_TOD_PRI_PORT_1_CTRL_REG_X6_TX_ENABLE = 26 ;
+static const uint8_t P9N2_PERV_TOD_PRI_PORT_1_CTRL_REG_X7_TX_ENABLE = 27 ;
+static const uint8_t P9N2_PERV_TOD_PRI_PORT_1_CTRL_REG_0X02_SPARE_28_31 = 28 ;
+static const uint8_t P9N2_PERV_TOD_PRI_PORT_1_CTRL_REG_0X02_SPARE_28_31_LEN = 4 ;
+
+static const uint8_t P9N2_PERV_TOD_PROBE_SELECT_REG_0_DATA = 0 ;
+static const uint8_t P9N2_PERV_TOD_PROBE_SELECT_REG_0_DATA_LEN = 8 ;
+static const uint8_t P9N2_PERV_TOD_PROBE_SELECT_REG_1_DATA = 8 ;
+static const uint8_t P9N2_PERV_TOD_PROBE_SELECT_REG_1_DATA_LEN = 8 ;
+static const uint8_t P9N2_PERV_TOD_PROBE_SELECT_REG_2_DATA = 16 ;
+static const uint8_t P9N2_PERV_TOD_PROBE_SELECT_REG_2_DATA_LEN = 8 ;
+static const uint8_t P9N2_PERV_TOD_PROBE_SELECT_REG_3_DATA = 24 ;
+static const uint8_t P9N2_PERV_TOD_PROBE_SELECT_REG_3_DATA_LEN = 8 ;
+
+static const uint8_t P9N2_PERV_TOD_PSS_MSS_CTRL_REG_PRI_M_PATH_SELECT = 0 ;
+static const uint8_t P9N2_PERV_TOD_PSS_MSS_CTRL_REG_PRI_M_S_SELECT = 1 ;
+static const uint8_t P9N2_PERV_TOD_PSS_MSS_CTRL_REG_PRI_M_S_DRAWER_SELECT = 2 ;
+static const uint8_t P9N2_PERV_TOD_PSS_MSS_CTRL_REG_PRI_S_PATH_1_STEP_CHECK_ENABLE = 3 ;
+static const uint8_t P9N2_PERV_TOD_PSS_MSS_CTRL_REG_PRI_M_PATH_0_STEP_CHECK_ENABLE = 4 ;
+static const uint8_t P9N2_PERV_TOD_PSS_MSS_CTRL_REG_PRI_M_PATH_1_STEP_CHECK_ENABLE = 5 ;
+static const uint8_t P9N2_PERV_TOD_PSS_MSS_CTRL_REG_PRI_S_PATH_0_STEP_CHECK_ENABLE = 6 ;
+static const uint8_t P9N2_PERV_TOD_PSS_MSS_CTRL_REG_PRI_I_PATH_STEP_CHECK_ENABLE = 7 ;
+static const uint8_t P9N2_PERV_TOD_PSS_MSS_CTRL_REG_SEC_M_PATH_SELECT = 8 ;
+static const uint8_t P9N2_PERV_TOD_PSS_MSS_CTRL_REG_SEC_M_S_SELECT = 9 ;
+static const uint8_t P9N2_PERV_TOD_PSS_MSS_CTRL_REG_SEC_M_S_DRAWER_SELECT = 10 ;
+static const uint8_t P9N2_PERV_TOD_PSS_MSS_CTRL_REG_SEC_S_PATH_1_STEP_CHECK_ENABLE = 11 ;
+static const uint8_t P9N2_PERV_TOD_PSS_MSS_CTRL_REG_SEC_M_PATH_0_STEP_CHECK_ENABLE = 12 ;
+static const uint8_t P9N2_PERV_TOD_PSS_MSS_CTRL_REG_SEC_M_PATH_1_STEP_CHECK_ENABLE = 13 ;
+static const uint8_t P9N2_PERV_TOD_PSS_MSS_CTRL_REG_SEC_S_PATH_0_STEP_CHECK_ENABLE = 14 ;
+static const uint8_t P9N2_PERV_TOD_PSS_MSS_CTRL_REG_SEC_I_PATH_STEP_CHECK_ENABLE = 15 ;
+static const uint8_t P9N2_PERV_TOD_PSS_MSS_CTRL_REG_SWITCH_SYNC_ERROR_DISABLE = 16 ;
+static const uint8_t P9N2_PERV_TOD_PSS_MSS_CTRL_REG_I_PATH_STEP_CHECK_CPS_DEVIATION_X_DISABLE = 17 ;
+static const uint8_t P9N2_PERV_TOD_PSS_MSS_CTRL_REG_STEP_CHECK_ENABLE_CHICKEN_SWITCH = 18 ;
+static const uint8_t P9N2_PERV_TOD_PSS_MSS_CTRL_REG_0X07_SPARE_19 = 19 ;
+static const uint8_t P9N2_PERV_TOD_PSS_MSS_CTRL_REG_0X07_SPARE_20 = 20 ;
+static const uint8_t P9N2_PERV_TOD_PSS_MSS_CTRL_REG_MISC_RESYNC_OSC_FROM = 21 ;
+static const uint8_t P9N2_PERV_TOD_PSS_MSS_CTRL_REG_0X07_SPARE_22_31 = 22 ;
+static const uint8_t P9N2_PERV_TOD_PSS_MSS_CTRL_REG_0X07_SPARE_22_31_LEN = 10 ;
+
+static const uint8_t P9N2_PERV_TOD_PSS_MSS_STATUS_REG_PRI_SEC_SELECT = 0 ;
+static const uint8_t P9N2_PERV_TOD_PSS_MSS_STATUS_REG_PRI_SEC_SELECT_LEN = 3 ;
+static const uint8_t P9N2_PERV_TOD_PSS_MSS_STATUS_REG_0X08_SPARE_03 = 3 ;
+static const uint8_t P9N2_PERV_TOD_PSS_MSS_STATUS_REG_M_PATH_0_OSC_NOT_VALID = 4 ;
+static const uint8_t P9N2_PERV_TOD_PSS_MSS_STATUS_REG_M_PATH_1_OSC_NOT_VALID = 5 ;
+static const uint8_t P9N2_PERV_TOD_PSS_MSS_STATUS_REG_M_PATH_0_STEP_CHECK_VALID = 6 ;
+static const uint8_t P9N2_PERV_TOD_PSS_MSS_STATUS_REG_M_PATH_1_STEP_CHECK_VALID = 7 ;
+static const uint8_t P9N2_PERV_TOD_PSS_MSS_STATUS_REG_S_PATH_0_STEP_CHECK_VALID = 8 ;
+static const uint8_t P9N2_PERV_TOD_PSS_MSS_STATUS_REG_I_PATH_STEP_CHECK_VALID = 9 ;
+static const uint8_t P9N2_PERV_TOD_PSS_MSS_STATUS_REG_S_PATH_1_STEP_CHECK_VALID = 10 ;
+static const uint8_t P9N2_PERV_TOD_PSS_MSS_STATUS_REG_IS_SPECIAL = 11 ;
+static const uint8_t P9N2_PERV_TOD_PSS_MSS_STATUS_REG_PRI_M_PATH_SELECT = 12 ;
+static const uint8_t P9N2_PERV_TOD_PSS_MSS_STATUS_REG_PRI_M_S_SELECT = 13 ;
+static const uint8_t P9N2_PERV_TOD_PSS_MSS_STATUS_REG_PRI_M_S_DRAWER_SELECT = 14 ;
+static const uint8_t P9N2_PERV_TOD_PSS_MSS_STATUS_REG_PRI_S_PATH_SELECT = 15 ;
+static const uint8_t P9N2_PERV_TOD_PSS_MSS_STATUS_REG_SEC_M_PATH_SELECT = 16 ;
+static const uint8_t P9N2_PERV_TOD_PSS_MSS_STATUS_REG_SEC_M_S_SELECT = 17 ;
+static const uint8_t P9N2_PERV_TOD_PSS_MSS_STATUS_REG_SEC_M_S_DRAWER_SELECT = 18 ;
+static const uint8_t P9N2_PERV_TOD_PSS_MSS_STATUS_REG_SEC_S_PATH_SELECT = 19 ;
+static const uint8_t P9N2_PERV_TOD_PSS_MSS_STATUS_REG_IS_RUNNING = 20 ;
+static const uint8_t P9N2_PERV_TOD_PSS_MSS_STATUS_REG_IS_PRIMARY = 21 ;
+static const uint8_t P9N2_PERV_TOD_PSS_MSS_STATUS_REG_IS_SECONDARY = 22 ;
+static const uint8_t P9N2_PERV_TOD_PSS_MSS_STATUS_REG_IS_ACTIVE_MASTER = 23 ;
+static const uint8_t P9N2_PERV_TOD_PSS_MSS_STATUS_REG_IS_BACKUP_MASTER = 24 ;
+static const uint8_t P9N2_PERV_TOD_PSS_MSS_STATUS_REG_IS_SLAVE = 25 ;
+static const uint8_t P9N2_PERV_TOD_PSS_MSS_STATUS_REG_M_PATH_SELECT = 26 ;
+static const uint8_t P9N2_PERV_TOD_PSS_MSS_STATUS_REG_S_PATH_SELECT = 27 ;
+static const uint8_t P9N2_PERV_TOD_PSS_MSS_STATUS_REG_M_PATH_0_STEP_ALIGN_VALID_SWITCH = 28 ;
+static const uint8_t P9N2_PERV_TOD_PSS_MSS_STATUS_REG_M_PATH_1_STEP_ALIGN_VALID_SWITCH = 29 ;
+static const uint8_t P9N2_PERV_TOD_PSS_MSS_STATUS_REG_0X08_SPARE_30 = 30 ;
+static const uint8_t P9N2_PERV_TOD_PSS_MSS_STATUS_REG_M_PATH_SWITCH_TRIGGER = 31 ;
+
+static const uint8_t P9N2_PERV_TOD_RX_TTYPE_CTRL_REG_DATA = 0 ;
+static const uint8_t P9N2_PERV_TOD_RX_TTYPE_CTRL_REG_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_PERV_TOD_SEC_PORT_0_CTRL_REG_RX_SELECT = 0 ;
+static const uint8_t P9N2_PERV_TOD_SEC_PORT_0_CTRL_REG_RX_SELECT_LEN = 3 ;
+static const uint8_t P9N2_PERV_TOD_SEC_PORT_0_CTRL_REG_0X03_SPARE_03 = 3 ;
+static const uint8_t P9N2_PERV_TOD_SEC_PORT_0_CTRL_REG_X0_TX_SELECT = 4 ;
+static const uint8_t P9N2_PERV_TOD_SEC_PORT_0_CTRL_REG_X0_TX_SELECT_LEN = 2 ;
+static const uint8_t P9N2_PERV_TOD_SEC_PORT_0_CTRL_REG_X1_TX_SELECT = 6 ;
+static const uint8_t P9N2_PERV_TOD_SEC_PORT_0_CTRL_REG_X1_TX_SELECT_LEN = 2 ;
+static const uint8_t P9N2_PERV_TOD_SEC_PORT_0_CTRL_REG_X2_TX_SELECT = 8 ;
+static const uint8_t P9N2_PERV_TOD_SEC_PORT_0_CTRL_REG_X2_TX_SELECT_LEN = 2 ;
+static const uint8_t P9N2_PERV_TOD_SEC_PORT_0_CTRL_REG_X3_TX_SELECT = 10 ;
+static const uint8_t P9N2_PERV_TOD_SEC_PORT_0_CTRL_REG_X3_TX_SELECT_LEN = 2 ;
+static const uint8_t P9N2_PERV_TOD_SEC_PORT_0_CTRL_REG_X4_TX_SELECT = 12 ;
+static const uint8_t P9N2_PERV_TOD_SEC_PORT_0_CTRL_REG_X4_TX_SELECT_LEN = 2 ;
+static const uint8_t P9N2_PERV_TOD_SEC_PORT_0_CTRL_REG_X5_TX_SELECT = 14 ;
+static const uint8_t P9N2_PERV_TOD_SEC_PORT_0_CTRL_REG_X5_TX_SELECT_LEN = 2 ;
+static const uint8_t P9N2_PERV_TOD_SEC_PORT_0_CTRL_REG_X6_TX_SELECT = 16 ;
+static const uint8_t P9N2_PERV_TOD_SEC_PORT_0_CTRL_REG_X6_TX_SELECT_LEN = 2 ;
+static const uint8_t P9N2_PERV_TOD_SEC_PORT_0_CTRL_REG_X7_TX_SELECT = 18 ;
+static const uint8_t P9N2_PERV_TOD_SEC_PORT_0_CTRL_REG_X7_TX_SELECT_LEN = 2 ;
+static const uint8_t P9N2_PERV_TOD_SEC_PORT_0_CTRL_REG_X0_TX_ENABLE = 20 ;
+static const uint8_t P9N2_PERV_TOD_SEC_PORT_0_CTRL_REG_X1_TX_ENABLE = 21 ;
+static const uint8_t P9N2_PERV_TOD_SEC_PORT_0_CTRL_REG_X2_TX_ENABLE = 22 ;
+static const uint8_t P9N2_PERV_TOD_SEC_PORT_0_CTRL_REG_X3_TX_ENABLE = 23 ;
+static const uint8_t P9N2_PERV_TOD_SEC_PORT_0_CTRL_REG_X4_TX_ENABLE = 24 ;
+static const uint8_t P9N2_PERV_TOD_SEC_PORT_0_CTRL_REG_X5_TX_ENABLE = 25 ;
+static const uint8_t P9N2_PERV_TOD_SEC_PORT_0_CTRL_REG_X6_TX_ENABLE = 26 ;
+static const uint8_t P9N2_PERV_TOD_SEC_PORT_0_CTRL_REG_X7_TX_ENABLE = 27 ;
+static const uint8_t P9N2_PERV_TOD_SEC_PORT_0_CTRL_REG_0X03_SPARE_28_31 = 28 ;
+static const uint8_t P9N2_PERV_TOD_SEC_PORT_0_CTRL_REG_0X03_SPARE_28_31_LEN = 4 ;
+static const uint8_t P9N2_PERV_TOD_SEC_PORT_0_CTRL_REG_I_PATH_DELAY_VALUE = 32 ;
+static const uint8_t P9N2_PERV_TOD_SEC_PORT_0_CTRL_REG_I_PATH_DELAY_VALUE_LEN = 8 ;
+
+static const uint8_t P9N2_PERV_TOD_SEC_PORT_1_CTRL_REG_RX_SELECT = 0 ;
+static const uint8_t P9N2_PERV_TOD_SEC_PORT_1_CTRL_REG_RX_SELECT_LEN = 3 ;
+static const uint8_t P9N2_PERV_TOD_SEC_PORT_1_CTRL_REG_0X04_SPARE_03 = 3 ;
+static const uint8_t P9N2_PERV_TOD_SEC_PORT_1_CTRL_REG_X0_TX_SELECT = 4 ;
+static const uint8_t P9N2_PERV_TOD_SEC_PORT_1_CTRL_REG_X0_TX_SELECT_LEN = 2 ;
+static const uint8_t P9N2_PERV_TOD_SEC_PORT_1_CTRL_REG_X1_TX_SELECT = 6 ;
+static const uint8_t P9N2_PERV_TOD_SEC_PORT_1_CTRL_REG_X1_TX_SELECT_LEN = 2 ;
+static const uint8_t P9N2_PERV_TOD_SEC_PORT_1_CTRL_REG_X2_TX_SELECT = 8 ;
+static const uint8_t P9N2_PERV_TOD_SEC_PORT_1_CTRL_REG_X2_TX_SELECT_LEN = 2 ;
+static const uint8_t P9N2_PERV_TOD_SEC_PORT_1_CTRL_REG_X3_TX_SELECT = 10 ;
+static const uint8_t P9N2_PERV_TOD_SEC_PORT_1_CTRL_REG_X3_TX_SELECT_LEN = 2 ;
+static const uint8_t P9N2_PERV_TOD_SEC_PORT_1_CTRL_REG_X4_TX_SELECT = 12 ;
+static const uint8_t P9N2_PERV_TOD_SEC_PORT_1_CTRL_REG_X4_TX_SELECT_LEN = 2 ;
+static const uint8_t P9N2_PERV_TOD_SEC_PORT_1_CTRL_REG_X5_TX_SELECT = 14 ;
+static const uint8_t P9N2_PERV_TOD_SEC_PORT_1_CTRL_REG_X5_TX_SELECT_LEN = 2 ;
+static const uint8_t P9N2_PERV_TOD_SEC_PORT_1_CTRL_REG_X6_TX_SELECT = 16 ;
+static const uint8_t P9N2_PERV_TOD_SEC_PORT_1_CTRL_REG_X6_TX_SELECT_LEN = 2 ;
+static const uint8_t P9N2_PERV_TOD_SEC_PORT_1_CTRL_REG_X7_TX_SELECT = 18 ;
+static const uint8_t P9N2_PERV_TOD_SEC_PORT_1_CTRL_REG_X7_TX_SELECT_LEN = 2 ;
+static const uint8_t P9N2_PERV_TOD_SEC_PORT_1_CTRL_REG_X0_TX_ENABLE = 20 ;
+static const uint8_t P9N2_PERV_TOD_SEC_PORT_1_CTRL_REG_X1_TX_ENABLE = 21 ;
+static const uint8_t P9N2_PERV_TOD_SEC_PORT_1_CTRL_REG_X2_TX_ENABLE = 22 ;
+static const uint8_t P9N2_PERV_TOD_SEC_PORT_1_CTRL_REG_X3_TX_ENABLE = 23 ;
+static const uint8_t P9N2_PERV_TOD_SEC_PORT_1_CTRL_REG_X4_TX_ENABLE = 24 ;
+static const uint8_t P9N2_PERV_TOD_SEC_PORT_1_CTRL_REG_X5_TX_ENABLE = 25 ;
+static const uint8_t P9N2_PERV_TOD_SEC_PORT_1_CTRL_REG_X6_TX_ENABLE = 26 ;
+static const uint8_t P9N2_PERV_TOD_SEC_PORT_1_CTRL_REG_X7_TX_ENABLE = 27 ;
+static const uint8_t P9N2_PERV_TOD_SEC_PORT_1_CTRL_REG_0X04_SPARE_28_31 = 28 ;
+static const uint8_t P9N2_PERV_TOD_SEC_PORT_1_CTRL_REG_0X04_SPARE_28_31_LEN = 4 ;
+
+static const uint8_t P9N2_PERV_TOD_START_TOD_REG_FSM_TRIGGER = 0 ;
+static const uint8_t P9N2_PERV_TOD_START_TOD_REG_0X22_SPARE_01 = 1 ;
+static const uint8_t P9N2_PERV_TOD_START_TOD_REG_FSM_DATA02 = 2 ;
+static const uint8_t P9N2_PERV_TOD_START_TOD_REG_0X22_SPARE_03_07 = 3 ;
+static const uint8_t P9N2_PERV_TOD_START_TOD_REG_0X22_SPARE_03_07_LEN = 5 ;
+
+static const uint8_t P9N2_PERV_TOD_S_PATH_CTRL_REG_PRI_SELECT = 0 ;
+static const uint8_t P9N2_PERV_TOD_S_PATH_CTRL_REG_0X05_SPARE_01 = 1 ;
+static const uint8_t P9N2_PERV_TOD_S_PATH_CTRL_REG_M_CPS_ENABLE = 2 ;
+static const uint8_t P9N2_PERV_TOD_S_PATH_CTRL_REG_REMOTE_SYNC_DISABLE = 3 ;
+static const uint8_t P9N2_PERV_TOD_S_PATH_CTRL_REG_SEC_SELECT = 4 ;
+static const uint8_t P9N2_PERV_TOD_S_PATH_CTRL_REG_0X05_SPARE_05 = 5 ;
+static const uint8_t P9N2_PERV_TOD_S_PATH_CTRL_REG_STEP_CHECK_CPS_DEVIATION_FACTOR = 6 ;
+static const uint8_t P9N2_PERV_TOD_S_PATH_CTRL_REG_STEP_CHECK_CPS_DEVIATION_FACTOR_LEN = 2 ;
+static const uint8_t P9N2_PERV_TOD_S_PATH_CTRL_REG_0_STEP_CHECK_CPS_DEVIATION = 8 ;
+static const uint8_t P9N2_PERV_TOD_S_PATH_CTRL_REG_0_STEP_CHECK_CPS_DEVIATION_LEN = 4 ;
+static const uint8_t P9N2_PERV_TOD_S_PATH_CTRL_REG_0_STEP_CHECK_CONSTANT_CPS_ENABLE = 12 ;
+static const uint8_t P9N2_PERV_TOD_S_PATH_CTRL_REG_0_STEP_CHECK_VALIDITY_COUNT = 13 ;
+static const uint8_t P9N2_PERV_TOD_S_PATH_CTRL_REG_0_STEP_CHECK_VALIDITY_COUNT_LEN = 3 ;
+static const uint8_t P9N2_PERV_TOD_S_PATH_CTRL_REG_1_STEP_CHECK_CPS_DEVIATION = 16 ;
+static const uint8_t P9N2_PERV_TOD_S_PATH_CTRL_REG_1_STEP_CHECK_CPS_DEVIATION_LEN = 4 ;
+static const uint8_t P9N2_PERV_TOD_S_PATH_CTRL_REG_1_STEP_CHECK_CONSTANT_CPS_ENABLE = 20 ;
+static const uint8_t P9N2_PERV_TOD_S_PATH_CTRL_REG_1_STEP_CHECK_VALIDITY_COUNT = 21 ;
+static const uint8_t P9N2_PERV_TOD_S_PATH_CTRL_REG_1_STEP_CHECK_VALIDITY_COUNT_LEN = 3 ;
+static const uint8_t P9N2_PERV_TOD_S_PATH_CTRL_REG_REMOTE_SYNC_ERROR_DISABLE = 24 ;
+static const uint8_t P9N2_PERV_TOD_S_PATH_CTRL_REG_REMOTE_SYNC_CHECK_M_CPS_DISABLE = 25 ;
+static const uint8_t P9N2_PERV_TOD_S_PATH_CTRL_REG_REMOTE_SYNC_CHECK_CPS_DEVIATION_FACTOR = 26 ;
+static const uint8_t P9N2_PERV_TOD_S_PATH_CTRL_REG_REMOTE_SYNC_CHECK_CPS_DEVIATION_FACTOR_LEN = 2 ;
+static const uint8_t P9N2_PERV_TOD_S_PATH_CTRL_REG_REMOTE_SYNC_CHECK_CPS_DEVIATION = 28 ;
+static const uint8_t P9N2_PERV_TOD_S_PATH_CTRL_REG_REMOTE_SYNC_CHECK_CPS_DEVIATION_LEN = 4 ;
+static const uint8_t P9N2_PERV_TOD_S_PATH_CTRL_REG_REMOTE_SYNC_MISS_COUNT_MAX = 32 ;
+static const uint8_t P9N2_PERV_TOD_S_PATH_CTRL_REG_REMOTE_SYNC_MISS_COUNT_MAX_LEN = 8 ;
+
+static const uint8_t P9N2_PERV_TOD_S_PATH_STATUS_REG_M_0_STEP_ALIGN_FSM_STATE = 0 ;
+static const uint8_t P9N2_PERV_TOD_S_PATH_STATUS_REG_M_0_STEP_ALIGN_FSM_STATE_LEN = 4 ;
+static const uint8_t P9N2_PERV_TOD_S_PATH_STATUS_REG_M_1_STEP_ALIGN_FSM_STATE = 4 ;
+static const uint8_t P9N2_PERV_TOD_S_PATH_STATUS_REG_M_1_STEP_ALIGN_FSM_STATE_LEN = 4 ;
+static const uint8_t P9N2_PERV_TOD_S_PATH_STATUS_REG_I_DELAY_ADJUST_RATIO = 8 ;
+static const uint8_t P9N2_PERV_TOD_S_PATH_STATUS_REG_I_DELAY_ADJUST_RATIO_LEN = 5 ;
+static const uint8_t P9N2_PERV_TOD_S_PATH_STATUS_REG_0X0A_SPARE_13_15 = 13 ;
+static const uint8_t P9N2_PERV_TOD_S_PATH_STATUS_REG_0X0A_SPARE_13_15_LEN = 3 ;
+static const uint8_t P9N2_PERV_TOD_S_PATH_STATUS_REG_0_CPS = 16 ;
+static const uint8_t P9N2_PERV_TOD_S_PATH_STATUS_REG_0_CPS_LEN = 8 ;
+static const uint8_t P9N2_PERV_TOD_S_PATH_STATUS_REG_1_CPS = 24 ;
+static const uint8_t P9N2_PERV_TOD_S_PATH_STATUS_REG_1_CPS_LEN = 8 ;
+static const uint8_t P9N2_PERV_TOD_S_PATH_STATUS_REG_0_REMOTE_SYNC_LATE_SYNC_COUNT = 32 ;
+static const uint8_t P9N2_PERV_TOD_S_PATH_STATUS_REG_0_REMOTE_SYNC_LATE_SYNC_COUNT_LEN = 8 ;
+static const uint8_t P9N2_PERV_TOD_S_PATH_STATUS_REG_1_REMOTE_SYNC_LATE_SYNC_COUNT = 40 ;
+static const uint8_t P9N2_PERV_TOD_S_PATH_STATUS_REG_1_REMOTE_SYNC_LATE_SYNC_COUNT_LEN = 8 ;
+
+static const uint8_t P9N2_PERV_TOD_TIMER_REG_VALUE = 0 ;
+static const uint8_t P9N2_PERV_TOD_TIMER_REG_VALUE_LEN = 60 ;
+static const uint8_t P9N2_PERV_TOD_TIMER_REG_0X0D_SPARE_60_62 = 60 ;
+static const uint8_t P9N2_PERV_TOD_TIMER_REG_0X0D_SPARE_60_62_LEN = 3 ;
+static const uint8_t P9N2_PERV_TOD_TIMER_REG_STATUS = 63 ;
+
+static const uint8_t P9N2_PERV_TOD_TRACE_DATA_1_REG_SET = 0 ;
+static const uint8_t P9N2_PERV_TOD_TRACE_DATA_1_REG_SET_LEN = 64 ;
+
+static const uint8_t P9N2_PERV_TOD_TRACE_DATA_2_REG_SET = 0 ;
+static const uint8_t P9N2_PERV_TOD_TRACE_DATA_2_REG_SET_LEN = 64 ;
+
+static const uint8_t P9N2_PERV_TOD_TRACE_DATA_3_REG_SET = 0 ;
+static const uint8_t P9N2_PERV_TOD_TRACE_DATA_3_REG_SET_LEN = 64 ;
+
+static const uint8_t P9N2_PERV_TOD_TX_TTYPE_0_REG_TRIGGER = 0 ;
+
+static const uint8_t P9N2_PERV_TOD_TX_TTYPE_1_REG_TRIGGER = 0 ;
+
+static const uint8_t P9N2_PERV_TOD_TX_TTYPE_2_REG_TRIGGER = 0 ;
+
+static const uint8_t P9N2_PERV_TOD_TX_TTYPE_3_REG_TRIGGER = 0 ;
+
+static const uint8_t P9N2_PERV_TOD_TX_TTYPE_4_REG_TRIGGER = 0 ;
+
+static const uint8_t P9N2_PERV_TOD_TX_TTYPE_5_REG_TRIGGER = 0 ;
+
+static const uint8_t P9N2_PERV_TOD_TX_TTYPE_CTRL_REG_MOVE_TO_TB_CORE_ADDRESS = 0 ;
+static const uint8_t P9N2_PERV_TOD_TX_TTYPE_CTRL_REG_MOVE_TO_TB_CORE_ADDRESS_LEN = 24 ;
+static const uint8_t P9N2_PERV_TOD_TX_TTYPE_CTRL_REG_MOVE_TO_TB_CORE_ID = 24 ;
+static const uint8_t P9N2_PERV_TOD_TX_TTYPE_CTRL_REG_MOVE_TO_TB_CORE_ID_LEN = 8 ;
+static const uint8_t P9N2_PERV_TOD_TX_TTYPE_CTRL_REG_4_SEND_MODE = 32 ;
+static const uint8_t P9N2_PERV_TOD_TX_TTYPE_CTRL_REG_4_SEND_ENABLE = 33 ;
+static const uint8_t P9N2_PERV_TOD_TX_TTYPE_CTRL_REG_0X27_SPARE_34 = 34 ;
+static const uint8_t P9N2_PERV_TOD_TX_TTYPE_CTRL_REG_MOVE_TO_TB_CORE_ADDRESS_ENABLE = 35 ;
+static const uint8_t P9N2_PERV_TOD_TX_TTYPE_CTRL_REG_0X27_SPARE_36 = 36 ;
+static const uint8_t P9N2_PERV_TOD_TX_TTYPE_CTRL_REG_PIB_FSM_STATE = 37 ;
+static const uint8_t P9N2_PERV_TOD_TX_TTYPE_CTRL_REG_PIB_FSM_STATE_LEN = 3 ;
+
+static const uint8_t P9N2_PERV_TOD_VALUE_REG_VALUE = 0 ;
+static const uint8_t P9N2_PERV_TOD_VALUE_REG_VALUE_LEN = 60 ;
+static const uint8_t P9N2_PERV_TOD_VALUE_REG_WOF_COUNTER = 60 ;
+static const uint8_t P9N2_PERV_TOD_VALUE_REG_WOF_COUNTER_LEN = 4 ;
+
+static const uint8_t P9N2_PERV_1_TRACE_HI_DATA_REG_DATA = 0 ;
+static const uint8_t P9N2_PERV_1_TRACE_HI_DATA_REG_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_PERV_1_TRACE_LO_DATA_REG_DATA = 0 ;
+static const uint8_t P9N2_PERV_1_TRACE_LO_DATA_REG_DATA_LEN = 32 ;
+static const uint8_t P9N2_PERV_1_TRACE_LO_DATA_REG_ADDRESS = 32 ;
+static const uint8_t P9N2_PERV_1_TRACE_LO_DATA_REG_ADDRESS_LEN = 10 ;
+static const uint8_t P9N2_PERV_1_TRACE_LO_DATA_REG_LAST_BANK = 42 ;
+static const uint8_t P9N2_PERV_1_TRACE_LO_DATA_REG_LAST_BANK_LEN = 9 ;
+static const uint8_t P9N2_PERV_1_TRACE_LO_DATA_REG_LAST_BANK_VALID = 51 ;
+static const uint8_t P9N2_PERV_1_TRACE_LO_DATA_REG_WRITE_ON_RUN = 52 ;
+static const uint8_t P9N2_PERV_1_TRACE_LO_DATA_REG_RUNNING = 53 ;
+static const uint8_t P9N2_PERV_1_TRACE_LO_DATA_REG_HOLD_ADDRESS = 54 ;
+static const uint8_t P9N2_PERV_1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN = 10 ;
+
+static const uint8_t P9N2_PERV_1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE = 0 ;
+static const uint8_t P9N2_PERV_1_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE = 1 ;
+static const uint8_t P9N2_PERV_1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE = 2 ;
+static const uint8_t P9N2_PERV_1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN = 8 ;
+static const uint8_t P9N2_PERV_1_TRACE_TRCTRL_CONFIG_BANK_MODE = 10 ;
+static const uint8_t P9N2_PERV_1_TRACE_TRCTRL_CONFIG_ENH_MODE = 11 ;
+static const uint8_t P9N2_PERV_1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL = 12 ;
+static const uint8_t P9N2_PERV_1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN = 2 ;
+static const uint8_t P9N2_PERV_1_TRACE_TRCTRL_CONFIG_SELECT_CONTROL = 14 ;
+static const uint8_t P9N2_PERV_1_TRACE_TRCTRL_CONFIG_SELECT_CONTROL_LEN = 4 ;
+static const uint8_t P9N2_PERV_1_TRACE_TRCTRL_CONFIG_RUN_HOLD_OFF = 18 ;
+static const uint8_t P9N2_PERV_1_TRACE_TRCTRL_CONFIG_RUN_STATUS = 19 ;
+static const uint8_t P9N2_PERV_1_TRACE_TRCTRL_CONFIG_RUN_STICKY = 20 ;
+static const uint8_t P9N2_PERV_1_TRACE_TRCTRL_CONFIG_DISABLE_BANK_EDGE_DETECT = 21 ;
+static const uint8_t P9N2_PERV_1_TRACE_TRCTRL_CONFIG_CONTROL_UNUSED = 22 ;
+static const uint8_t P9N2_PERV_1_TRACE_TRCTRL_CONFIG_CONTROL_UNUSED_LEN = 6 ;
+
+static const uint8_t P9N2_PERV_1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 = 0 ;
+static const uint8_t P9N2_PERV_1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN = 64 ;
+
+static const uint8_t P9N2_PERV_1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 = 0 ;
+static const uint8_t P9N2_PERV_1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN = 24 ;
+
+static const uint8_t P9N2_PERV_1_TRACE_TRDATA_CONFIG_2_PATTERNA = 0 ;
+static const uint8_t P9N2_PERV_1_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN = 24 ;
+static const uint8_t P9N2_PERV_1_TRACE_TRDATA_CONFIG_2_PATTERNB = 24 ;
+static const uint8_t P9N2_PERV_1_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN = 24 ;
+
+static const uint8_t P9N2_PERV_1_TRACE_TRDATA_CONFIG_3_PATTERNC = 0 ;
+static const uint8_t P9N2_PERV_1_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN = 24 ;
+static const uint8_t P9N2_PERV_1_TRACE_TRDATA_CONFIG_3_PATTERND = 24 ;
+static const uint8_t P9N2_PERV_1_TRACE_TRDATA_CONFIG_3_PATTERND_LEN = 24 ;
+
+static const uint8_t P9N2_PERV_1_TRACE_TRDATA_CONFIG_4_MASKA = 0 ;
+static const uint8_t P9N2_PERV_1_TRACE_TRDATA_CONFIG_4_MASKA_LEN = 24 ;
+static const uint8_t P9N2_PERV_1_TRACE_TRDATA_CONFIG_4_MASKB = 24 ;
+static const uint8_t P9N2_PERV_1_TRACE_TRDATA_CONFIG_4_MASKB_LEN = 24 ;
+
+static const uint8_t P9N2_PERV_1_TRACE_TRDATA_CONFIG_5_MASKC = 0 ;
+static const uint8_t P9N2_PERV_1_TRACE_TRDATA_CONFIG_5_MASKC_LEN = 24 ;
+static const uint8_t P9N2_PERV_1_TRACE_TRDATA_CONFIG_5_MASKD = 24 ;
+static const uint8_t P9N2_PERV_1_TRACE_TRDATA_CONFIG_5_MASKD_LEN = 24 ;
+
+static const uint8_t P9N2_PERV_1_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION = 0 ;
+static const uint8_t P9N2_PERV_1_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK = 1 ;
+static const uint8_t P9N2_PERV_1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL = 2 ;
+static const uint8_t P9N2_PERV_1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN = 2 ;
+static const uint8_t P9N2_PERV_1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL = 4 ;
+static const uint8_t P9N2_PERV_1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN = 2 ;
+static const uint8_t P9N2_PERV_1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL = 6 ;
+static const uint8_t P9N2_PERV_1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN = 2 ;
+static const uint8_t P9N2_PERV_1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL = 8 ;
+static const uint8_t P9N2_PERV_1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN = 2 ;
+static const uint8_t P9N2_PERV_1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK = 10 ;
+static const uint8_t P9N2_PERV_1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN = 4 ;
+static const uint8_t P9N2_PERV_1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK = 14 ;
+static const uint8_t P9N2_PERV_1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN = 4 ;
+static const uint8_t P9N2_PERV_1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK = 18 ;
+static const uint8_t P9N2_PERV_1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN = 4 ;
+static const uint8_t P9N2_PERV_1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK = 22 ;
+static const uint8_t P9N2_PERV_1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN = 4 ;
+static const uint8_t P9N2_PERV_1_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE = 26 ;
+static const uint8_t P9N2_PERV_1_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE = 27 ;
+static const uint8_t P9N2_PERV_1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE = 28 ;
+static const uint8_t P9N2_PERV_1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN = 4 ;
+static const uint8_t P9N2_PERV_1_TRACE_TRDATA_CONFIG_9_ERROR_CMP_MASK = 32 ;
+static const uint8_t P9N2_PERV_1_TRACE_TRDATA_CONFIG_9_ERROR_CMP_PATTERN = 33 ;
+static const uint8_t P9N2_PERV_1_TRACE_TRDATA_CONFIG_9_TRIG0_ERR_CMP = 34 ;
+static const uint8_t P9N2_PERV_1_TRACE_TRDATA_CONFIG_9_TRIG1_ERR_CMP = 35 ;
+static const uint8_t P9N2_PERV_1_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES = 36 ;
+static const uint8_t P9N2_PERV_1_TRACE_TRDATA_CONFIG_9_SPARE_LT = 37 ;
+
+static const uint8_t P9N2_PERV_FSI2PIB_TRUE_MASK_REG = 0 ;
+static const uint8_t P9N2_PERV_FSI2PIB_TRUE_MASK_REG_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_FSISHIFT_TRUE_MASK_REG = 0 ;
+static const uint8_t P9N2_PERV_FSISHIFT_TRUE_MASK_REG_LEN = 32 ;
+
+static const uint8_t P9N2_PERV_1_VMEAS_RESULT_REG_RESULT = 0 ;
+static const uint8_t P9N2_PERV_1_VMEAS_RESULT_REG_RESULT_LEN = 8 ;
+
+static const uint8_t P9N2_PERV_FSII2C_WATER_MARK_REGISTER_A_WATERMARK_REG_0 = 16 ;
+static const uint8_t P9N2_PERV_FSII2C_WATER_MARK_REGISTER_A_WATERMARK_REG_0_LEN = 16 ;
+
+static const uint8_t P9N2_PERV_1_WRITE_PROTECT_ENABLE_REG_RING_LOCKING = 0 ;
+static const uint8_t P9N2_PERV_1_WRITE_PROTECT_ENABLE_REG_RESERVED_RING_LOCKING = 1 ;
+
+static const uint8_t P9N2_PERV_1_WRITE_PROTECT_RINGS_REG_RINGS = 0 ;
+static const uint8_t P9N2_PERV_1_WRITE_PROTECT_RINGS_REG_RINGS_LEN = 16 ;
+
+static const uint8_t P9N2_PERV_1_XFIR_IN0 = 0 ;
+static const uint8_t P9N2_PERV_1_XFIR_IN1 = 1 ;
+static const uint8_t P9N2_PERV_1_XFIR_IN2 = 2 ;
+static const uint8_t P9N2_PERV_1_XFIR_IN3 = 3 ;
+static const uint8_t P9N2_PERV_1_XFIR_IN4 = 4 ;
+static const uint8_t P9N2_PERV_1_XFIR_IN5 = 5 ;
+static const uint8_t P9N2_PERV_1_XFIR_IN6 = 6 ;
+static const uint8_t P9N2_PERV_1_XFIR_IN7 = 7 ;
+static const uint8_t P9N2_PERV_1_XFIR_IN8 = 8 ;
+static const uint8_t P9N2_PERV_1_XFIR_IN9 = 9 ;
+static const uint8_t P9N2_PERV_1_XFIR_IN10 = 10 ;
+static const uint8_t P9N2_PERV_1_XFIR_IN11 = 11 ;
+static const uint8_t P9N2_PERV_1_XFIR_IN12 = 12 ;
+static const uint8_t P9N2_PERV_1_XFIR_IN13 = 13 ;
+static const uint8_t P9N2_PERV_1_XFIR_IN14 = 14 ;
+static const uint8_t P9N2_PERV_1_XFIR_IN15 = 15 ;
+static const uint8_t P9N2_PERV_1_XFIR_IN16 = 16 ;
+static const uint8_t P9N2_PERV_1_XFIR_IN17 = 17 ;
+static const uint8_t P9N2_PERV_1_XFIR_IN18 = 18 ;
+static const uint8_t P9N2_PERV_1_XFIR_IN19 = 19 ;
+static const uint8_t P9N2_PERV_1_XFIR_IN20 = 20 ;
+static const uint8_t P9N2_PERV_1_XFIR_IN21 = 21 ;
+static const uint8_t P9N2_PERV_1_XFIR_IN21_LEN = 5 ;
+static const uint8_t P9N2_PERV_1_XFIR_IN26 = 26 ;
+
+static const uint8_t P9N2_PERV_1_XSTOP1_MASK_B = 0 ;
+static const uint8_t P9N2_PERV_1_XSTOP1_ALIGNED = 1 ;
+static const uint8_t P9N2_PERV_1_XSTOP1_TRIGGER_OPCG_ON = 2 ;
+static const uint8_t P9N2_PERV_1_XSTOP1_WAIT_ALLWAYS = 3 ;
+static const uint8_t P9N2_PERV_1_XSTOP1_PERV = 4 ;
+static const uint8_t P9N2_PERV_1_XSTOP1_UNIT1 = 5 ;
+static const uint8_t P9N2_PERV_1_XSTOP1_UNIT2 = 6 ;
+static const uint8_t P9N2_PERV_1_XSTOP1_UNIT3 = 7 ;
+static const uint8_t P9N2_PERV_1_XSTOP1_UNIT4 = 8 ;
+static const uint8_t P9N2_PERV_1_XSTOP1_UNIT5 = 9 ;
+static const uint8_t P9N2_PERV_1_XSTOP1_UNIT6 = 10 ;
+static const uint8_t P9N2_PERV_1_XSTOP1_UNIT7 = 11 ;
+static const uint8_t P9N2_PERV_1_XSTOP1_UNIT8 = 12 ;
+static const uint8_t P9N2_PERV_1_XSTOP1_UNIT9 = 13 ;
+static const uint8_t P9N2_PERV_1_XSTOP1_UNIT10 = 14 ;
+static const uint8_t P9N2_PERV_1_XSTOP1_WAIT_CYCLES = 48 ;
+static const uint8_t P9N2_PERV_1_XSTOP1_WAIT_CYCLES_LEN = 12 ;
+
+static const uint8_t P9N2_PERV_1_XSTOP2_MASK_B = 0 ;
+static const uint8_t P9N2_PERV_1_XSTOP2_ALIGNED = 1 ;
+static const uint8_t P9N2_PERV_1_XSTOP2_TRIGGER_OPCG_ON = 2 ;
+static const uint8_t P9N2_PERV_1_XSTOP2_WAIT_ALLWAYS = 3 ;
+static const uint8_t P9N2_PERV_1_XSTOP2_PERV = 4 ;
+static const uint8_t P9N2_PERV_1_XSTOP2_UNIT1 = 5 ;
+static const uint8_t P9N2_PERV_1_XSTOP2_UNIT2 = 6 ;
+static const uint8_t P9N2_PERV_1_XSTOP2_UNIT3 = 7 ;
+static const uint8_t P9N2_PERV_1_XSTOP2_UNIT4 = 8 ;
+static const uint8_t P9N2_PERV_1_XSTOP2_UNIT5 = 9 ;
+static const uint8_t P9N2_PERV_1_XSTOP2_UNIT6 = 10 ;
+static const uint8_t P9N2_PERV_1_XSTOP2_UNIT7 = 11 ;
+static const uint8_t P9N2_PERV_1_XSTOP2_UNIT8 = 12 ;
+static const uint8_t P9N2_PERV_1_XSTOP2_UNIT9 = 13 ;
+static const uint8_t P9N2_PERV_1_XSTOP2_UNIT10 = 14 ;
+static const uint8_t P9N2_PERV_1_XSTOP2_WAIT_CYCLES = 48 ;
+static const uint8_t P9N2_PERV_1_XSTOP2_WAIT_CYCLES_LEN = 12 ;
+
+static const uint8_t P9N2_PERV_1_XSTOP3_MASK_B = 0 ;
+static const uint8_t P9N2_PERV_1_XSTOP3_ALIGNED = 1 ;
+static const uint8_t P9N2_PERV_1_XSTOP3_TRIGGER_OPCG_ON = 2 ;
+static const uint8_t P9N2_PERV_1_XSTOP3_WAIT_ALLWAYS = 3 ;
+static const uint8_t P9N2_PERV_1_XSTOP3_PERV = 4 ;
+static const uint8_t P9N2_PERV_1_XSTOP3_UNIT1 = 5 ;
+static const uint8_t P9N2_PERV_1_XSTOP3_UNIT2 = 6 ;
+static const uint8_t P9N2_PERV_1_XSTOP3_UNIT3 = 7 ;
+static const uint8_t P9N2_PERV_1_XSTOP3_UNIT4 = 8 ;
+static const uint8_t P9N2_PERV_1_XSTOP3_UNIT5 = 9 ;
+static const uint8_t P9N2_PERV_1_XSTOP3_UNIT6 = 10 ;
+static const uint8_t P9N2_PERV_1_XSTOP3_UNIT7 = 11 ;
+static const uint8_t P9N2_PERV_1_XSTOP3_UNIT8 = 12 ;
+static const uint8_t P9N2_PERV_1_XSTOP3_UNIT9 = 13 ;
+static const uint8_t P9N2_PERV_1_XSTOP3_UNIT10 = 14 ;
+static const uint8_t P9N2_PERV_1_XSTOP3_WAIT_CYCLES = 48 ;
+static const uint8_t P9N2_PERV_1_XSTOP3_WAIT_CYCLES_LEN = 12 ;
+
+static const uint8_t P9N2_PERV_1_XSTOP_INTERRUPT_REG_XSTOP = 0 ;
+
+static const uint8_t P9N2_PERV_1_XTRA_TRACE_MODE_DATA = 0 ;
+static const uint8_t P9N2_PERV_1_XTRA_TRACE_MODE_DATA_LEN = 42 ;
+
+#endif
+
diff --git a/src/import/chips/p9/common/include/p9n2_quad_scom_addresses.H b/src/import/chips/p9/common/include/p9n2_quad_scom_addresses.H
new file mode 100644
index 000000000..3e6a4a992
--- /dev/null
+++ b/src/import/chips/p9/common/include/p9n2_quad_scom_addresses.H
@@ -0,0 +1,34970 @@
+/* IBM_PROLOG_BEGIN_TAG */
+/* This is an automatically generated prolog. */
+/* */
+/* $Source: src/import/chips/p9/common/include/p9n2_quad_scom_addresses.H $ */
+/* */
+/* OpenPOWER HostBoot Project */
+/* */
+/* Contributors Listed Below - COPYRIGHT 2017 */
+/* [+] International Business Machines Corp. */
+/* */
+/* */
+/* Licensed under the Apache License, Version 2.0 (the "License"); */
+/* you may not use this file except in compliance with the License. */
+/* You may obtain a copy of the License at */
+/* */
+/* http://www.apache.org/licenses/LICENSE-2.0 */
+/* */
+/* Unless required by applicable law or agreed to in writing, software */
+/* distributed under the License is distributed on an "AS IS" BASIS, */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */
+/* implied. See the License for the specific language governing */
+/* permissions and limitations under the License. */
+/* */
+/* IBM_PROLOG_END_TAG */
+///
+/// @file p9_quad_scom_addresses.H
+/// @brief Defines constants for scom addresses
+///
+// *HWP HWP Owner: Ben Gass <bgass@us.ibm.com>
+// *HWP FW Owner: Thi Tran <thi@us.ibm.com>
+// *HWP Team: SOA
+// *HWP Level: 1
+// *HWP Consumed by: FSP:HB:HS:OCC:SBE:CME:SGPE:PGPE:FPPE:IPPE
+
+/*---------------------------------------------------------------
+ *
+ *---------------------------------------------------------------
+ *
+ *---------------------------------------------------------------
+ */
+
+
+#ifndef __P9N2_QUAD_SCOM_ADDRESSES_H
+#define __P9N2_QUAD_SCOM_ADDRESSES_H
+
+#include <stdint.h>
+
+
+static const uint64_t P9N2_C_ADDR_TRAP_REG = 0x20010003ull;
+
+static const uint64_t P9N2_C_0_ADDR_TRAP_REG = 0x20010003ull;
+
+static const uint64_t P9N2_C_1_ADDR_TRAP_REG = 0x21010003ull;
+
+static const uint64_t P9N2_C_2_ADDR_TRAP_REG = 0x22010003ull;
+
+static const uint64_t P9N2_C_3_ADDR_TRAP_REG = 0x23010003ull;
+
+static const uint64_t P9N2_C_4_ADDR_TRAP_REG = 0x24010003ull;
+
+static const uint64_t P9N2_C_5_ADDR_TRAP_REG = 0x25010003ull;
+
+static const uint64_t P9N2_C_6_ADDR_TRAP_REG = 0x26010003ull;
+
+static const uint64_t P9N2_C_7_ADDR_TRAP_REG = 0x27010003ull;
+
+static const uint64_t P9N2_C_8_ADDR_TRAP_REG = 0x28010003ull;
+
+static const uint64_t P9N2_C_9_ADDR_TRAP_REG = 0x29010003ull;
+
+static const uint64_t P9N2_C_10_ADDR_TRAP_REG = 0x2A010003ull;
+
+static const uint64_t P9N2_C_11_ADDR_TRAP_REG = 0x2B010003ull;
+
+static const uint64_t P9N2_C_12_ADDR_TRAP_REG = 0x2C010003ull;
+
+static const uint64_t P9N2_C_13_ADDR_TRAP_REG = 0x2D010003ull;
+
+static const uint64_t P9N2_C_14_ADDR_TRAP_REG = 0x2E010003ull;
+
+static const uint64_t P9N2_C_15_ADDR_TRAP_REG = 0x2F010003ull;
+
+static const uint64_t P9N2_C_16_ADDR_TRAP_REG = 0x30010003ull;
+
+static const uint64_t P9N2_C_17_ADDR_TRAP_REG = 0x31010003ull;
+
+static const uint64_t P9N2_C_18_ADDR_TRAP_REG = 0x32010003ull;
+
+static const uint64_t P9N2_C_19_ADDR_TRAP_REG = 0x33010003ull;
+
+static const uint64_t P9N2_C_20_ADDR_TRAP_REG = 0x34010003ull;
+
+static const uint64_t P9N2_C_21_ADDR_TRAP_REG = 0x35010003ull;
+
+static const uint64_t P9N2_C_22_ADDR_TRAP_REG = 0x36010003ull;
+
+static const uint64_t P9N2_C_23_ADDR_TRAP_REG = 0x37010003ull;
+
+static const uint64_t P9N2_EQ_ADDR_TRAP_REG = 0x10010003ull;
+
+static const uint64_t P9N2_EQ_0_ADDR_TRAP_REG = 0x10010003ull;
+
+static const uint64_t P9N2_EQ_1_ADDR_TRAP_REG = 0x11010003ull;
+
+static const uint64_t P9N2_EQ_2_ADDR_TRAP_REG = 0x12010003ull;
+
+static const uint64_t P9N2_EQ_3_ADDR_TRAP_REG = 0x13010003ull;
+
+static const uint64_t P9N2_EQ_4_ADDR_TRAP_REG = 0x14010003ull;
+
+static const uint64_t P9N2_EQ_5_ADDR_TRAP_REG = 0x15010003ull;
+
+static const uint64_t P9N2_EX_ADDR_TRAP_REG = 0x20010003ull;
+//DUPS: 21010003,
+static const uint64_t P9N2_EX_0_ADDR_TRAP_REG = 0x20010003ull;
+//DUPS: 21010003,
+static const uint64_t P9N2_EX_1_ADDR_TRAP_REG = 0x22010003ull;
+//DUPS: 23010003,
+static const uint64_t P9N2_EX_2_ADDR_TRAP_REG = 0x24010003ull;
+//DUPS: 25010003,
+static const uint64_t P9N2_EX_3_ADDR_TRAP_REG = 0x26010003ull;
+//DUPS: 27010003,
+static const uint64_t P9N2_EX_4_ADDR_TRAP_REG = 0x28010003ull;
+//DUPS: 29010003,
+static const uint64_t P9N2_EX_5_ADDR_TRAP_REG = 0x2A010003ull;
+//DUPS: 2B010003,
+static const uint64_t P9N2_EX_6_ADDR_TRAP_REG = 0x2C010003ull;
+//DUPS: 2D010003,
+static const uint64_t P9N2_EX_7_ADDR_TRAP_REG = 0x2F010003ull;
+//DUPS: 2F010003,
+static const uint64_t P9N2_EX_8_ADDR_TRAP_REG = 0x30010003ull;
+//DUPS: 31010003,
+static const uint64_t P9N2_EX_9_ADDR_TRAP_REG = 0x32010003ull;
+//DUPS: 33010003,
+static const uint64_t P9N2_EX_10_ADDR_TRAP_REG = 0x34010003ull;
+//DUPS: 35010003,
+static const uint64_t P9N2_EX_11_ADDR_TRAP_REG = 0x36010003ull;
+//DUPS: 37010003,
+
+static const uint64_t P9N2_C_ASSIST_INTERRUPT_REG = 0x200F0011ull;
+
+static const uint64_t P9N2_C_0_ASSIST_INTERRUPT_REG = 0x200F0011ull;
+
+static const uint64_t P9N2_C_1_ASSIST_INTERRUPT_REG = 0x210F0011ull;
+
+static const uint64_t P9N2_C_2_ASSIST_INTERRUPT_REG = 0x220F0011ull;
+
+static const uint64_t P9N2_C_3_ASSIST_INTERRUPT_REG = 0x230F0011ull;
+
+static const uint64_t P9N2_C_4_ASSIST_INTERRUPT_REG = 0x240F0011ull;
+
+static const uint64_t P9N2_C_5_ASSIST_INTERRUPT_REG = 0x250F0011ull;
+
+static const uint64_t P9N2_C_6_ASSIST_INTERRUPT_REG = 0x260F0011ull;
+
+static const uint64_t P9N2_C_7_ASSIST_INTERRUPT_REG = 0x270F0011ull;
+
+static const uint64_t P9N2_C_8_ASSIST_INTERRUPT_REG = 0x280F0011ull;
+
+static const uint64_t P9N2_C_9_ASSIST_INTERRUPT_REG = 0x290F0011ull;
+
+static const uint64_t P9N2_C_10_ASSIST_INTERRUPT_REG = 0x2A0F0011ull;
+
+static const uint64_t P9N2_C_11_ASSIST_INTERRUPT_REG = 0x2B0F0011ull;
+
+static const uint64_t P9N2_C_12_ASSIST_INTERRUPT_REG = 0x2C0F0011ull;
+
+static const uint64_t P9N2_C_13_ASSIST_INTERRUPT_REG = 0x2D0F0011ull;
+
+static const uint64_t P9N2_C_14_ASSIST_INTERRUPT_REG = 0x2E0F0011ull;
+
+static const uint64_t P9N2_C_15_ASSIST_INTERRUPT_REG = 0x2F0F0011ull;
+
+static const uint64_t P9N2_C_16_ASSIST_INTERRUPT_REG = 0x300F0011ull;
+
+static const uint64_t P9N2_C_17_ASSIST_INTERRUPT_REG = 0x310F0011ull;
+
+static const uint64_t P9N2_C_18_ASSIST_INTERRUPT_REG = 0x320F0011ull;
+
+static const uint64_t P9N2_C_19_ASSIST_INTERRUPT_REG = 0x330F0011ull;
+
+static const uint64_t P9N2_C_20_ASSIST_INTERRUPT_REG = 0x340F0011ull;
+
+static const uint64_t P9N2_C_21_ASSIST_INTERRUPT_REG = 0x350F0011ull;
+
+static const uint64_t P9N2_C_22_ASSIST_INTERRUPT_REG = 0x360F0011ull;
+
+static const uint64_t P9N2_C_23_ASSIST_INTERRUPT_REG = 0x370F0011ull;
+
+static const uint64_t P9N2_EQ_ASSIST_INTERRUPT_REG = 0x100F0011ull;
+
+static const uint64_t P9N2_EQ_0_ASSIST_INTERRUPT_REG = 0x100F0011ull;
+
+static const uint64_t P9N2_EQ_1_ASSIST_INTERRUPT_REG = 0x110F0011ull;
+
+static const uint64_t P9N2_EQ_2_ASSIST_INTERRUPT_REG = 0x120F0011ull;
+
+static const uint64_t P9N2_EQ_3_ASSIST_INTERRUPT_REG = 0x130F0011ull;
+
+static const uint64_t P9N2_EQ_4_ASSIST_INTERRUPT_REG = 0x140F0011ull;
+
+static const uint64_t P9N2_EQ_5_ASSIST_INTERRUPT_REG = 0x150F0011ull;
+
+static const uint64_t P9N2_EX_ASSIST_INTERRUPT_REG = 0x200F0011ull;
+//DUPS: 210F0011,
+static const uint64_t P9N2_EX_0_ASSIST_INTERRUPT_REG = 0x200F0011ull;
+//DUPS: 210F0011,
+static const uint64_t P9N2_EX_1_ASSIST_INTERRUPT_REG = 0x220F0011ull;
+//DUPS: 220F0011,
+static const uint64_t P9N2_EX_2_ASSIST_INTERRUPT_REG = 0x240F0011ull;
+//DUPS: 250F0011,
+static const uint64_t P9N2_EX_3_ASSIST_INTERRUPT_REG = 0x260F0011ull;
+//DUPS: 270F0011,
+static const uint64_t P9N2_EX_4_ASSIST_INTERRUPT_REG = 0x280F0011ull;
+//DUPS: 290F0011,
+static const uint64_t P9N2_EX_5_ASSIST_INTERRUPT_REG = 0x2A0F0011ull;
+//DUPS: 2B0F0011,
+static const uint64_t P9N2_EX_6_ASSIST_INTERRUPT_REG = 0x2C0F0011ull;
+//DUPS: 2D0F0011,
+static const uint64_t P9N2_EX_7_ASSIST_INTERRUPT_REG = 0x2E0F0011ull;
+//DUPS: 2F0F0011,
+static const uint64_t P9N2_EX_8_ASSIST_INTERRUPT_REG = 0x300F0011ull;
+//DUPS: 310F0011,
+static const uint64_t P9N2_EX_9_ASSIST_INTERRUPT_REG = 0x320F0011ull;
+//DUPS: 330F0011,
+static const uint64_t P9N2_EX_10_ASSIST_INTERRUPT_REG = 0x340F0011ull;
+//DUPS: 350F0011,
+static const uint64_t P9N2_EX_11_ASSIST_INTERRUPT_REG = 0x360F0011ull;
+//DUPS: 370F0011,
+
+static const uint64_t P9N2_C_ATOMIC_LOCK_MASK_LATCH_REG = 0x20010007ull;
+
+static const uint64_t P9N2_C_0_ATOMIC_LOCK_MASK_LATCH_REG = 0x20010007ull;
+
+static const uint64_t P9N2_C_1_ATOMIC_LOCK_MASK_LATCH_REG = 0x21010007ull;
+
+static const uint64_t P9N2_C_2_ATOMIC_LOCK_MASK_LATCH_REG = 0x22010007ull;
+
+static const uint64_t P9N2_C_3_ATOMIC_LOCK_MASK_LATCH_REG = 0x23010007ull;
+
+static const uint64_t P9N2_C_4_ATOMIC_LOCK_MASK_LATCH_REG = 0x24010007ull;
+
+static const uint64_t P9N2_C_5_ATOMIC_LOCK_MASK_LATCH_REG = 0x25010007ull;
+
+static const uint64_t P9N2_C_6_ATOMIC_LOCK_MASK_LATCH_REG = 0x26010007ull;
+
+static const uint64_t P9N2_C_7_ATOMIC_LOCK_MASK_LATCH_REG = 0x27010007ull;
+
+static const uint64_t P9N2_C_8_ATOMIC_LOCK_MASK_LATCH_REG = 0x28010007ull;
+
+static const uint64_t P9N2_C_9_ATOMIC_LOCK_MASK_LATCH_REG = 0x29010007ull;
+
+static const uint64_t P9N2_C_10_ATOMIC_LOCK_MASK_LATCH_REG = 0x2A010007ull;
+
+static const uint64_t P9N2_C_11_ATOMIC_LOCK_MASK_LATCH_REG = 0x2B010007ull;
+
+static const uint64_t P9N2_C_12_ATOMIC_LOCK_MASK_LATCH_REG = 0x2C010007ull;
+
+static const uint64_t P9N2_C_13_ATOMIC_LOCK_MASK_LATCH_REG = 0x2D010007ull;
+
+static const uint64_t P9N2_C_14_ATOMIC_LOCK_MASK_LATCH_REG = 0x2E010007ull;
+
+static const uint64_t P9N2_C_15_ATOMIC_LOCK_MASK_LATCH_REG = 0x2F010007ull;
+
+static const uint64_t P9N2_C_16_ATOMIC_LOCK_MASK_LATCH_REG = 0x30010007ull;
+
+static const uint64_t P9N2_C_17_ATOMIC_LOCK_MASK_LATCH_REG = 0x31010007ull;
+
+static const uint64_t P9N2_C_18_ATOMIC_LOCK_MASK_LATCH_REG = 0x32010007ull;
+
+static const uint64_t P9N2_C_19_ATOMIC_LOCK_MASK_LATCH_REG = 0x33010007ull;
+
+static const uint64_t P9N2_C_20_ATOMIC_LOCK_MASK_LATCH_REG = 0x34010007ull;
+
+static const uint64_t P9N2_C_21_ATOMIC_LOCK_MASK_LATCH_REG = 0x35010007ull;
+
+static const uint64_t P9N2_C_22_ATOMIC_LOCK_MASK_LATCH_REG = 0x36010007ull;
+
+static const uint64_t P9N2_C_23_ATOMIC_LOCK_MASK_LATCH_REG = 0x37010007ull;
+
+static const uint64_t P9N2_EQ_ATOMIC_LOCK_MASK_LATCH_REG = 0x10010007ull;
+
+static const uint64_t P9N2_EQ_0_ATOMIC_LOCK_MASK_LATCH_REG = 0x10010007ull;
+
+static const uint64_t P9N2_EQ_1_ATOMIC_LOCK_MASK_LATCH_REG = 0x11010007ull;
+
+static const uint64_t P9N2_EQ_2_ATOMIC_LOCK_MASK_LATCH_REG = 0x12010007ull;
+
+static const uint64_t P9N2_EQ_3_ATOMIC_LOCK_MASK_LATCH_REG = 0x13010007ull;
+
+static const uint64_t P9N2_EQ_4_ATOMIC_LOCK_MASK_LATCH_REG = 0x14010007ull;
+
+static const uint64_t P9N2_EQ_5_ATOMIC_LOCK_MASK_LATCH_REG = 0x15010007ull;
+
+static const uint64_t P9N2_EX_ATOMIC_LOCK_MASK_LATCH_REG = 0x20010007ull;
+//DUPS: 21010007,
+static const uint64_t P9N2_EX_0_ATOMIC_LOCK_MASK_LATCH_REG = 0x20010007ull;
+//DUPS: 21010007,
+static const uint64_t P9N2_EX_1_ATOMIC_LOCK_MASK_LATCH_REG = 0x22010007ull;
+//DUPS: 23010007,
+static const uint64_t P9N2_EX_2_ATOMIC_LOCK_MASK_LATCH_REG = 0x24010007ull;
+//DUPS: 25010007,
+static const uint64_t P9N2_EX_3_ATOMIC_LOCK_MASK_LATCH_REG = 0x26010007ull;
+//DUPS: 27010007,
+static const uint64_t P9N2_EX_4_ATOMIC_LOCK_MASK_LATCH_REG = 0x28010007ull;
+//DUPS: 29010007,
+static const uint64_t P9N2_EX_5_ATOMIC_LOCK_MASK_LATCH_REG = 0x2A010007ull;
+//DUPS: 2B010007,
+static const uint64_t P9N2_EX_6_ATOMIC_LOCK_MASK_LATCH_REG = 0x2C010007ull;
+//DUPS: 2D010007,
+static const uint64_t P9N2_EX_7_ATOMIC_LOCK_MASK_LATCH_REG = 0x2F010007ull;
+//DUPS: 2F010007,
+static const uint64_t P9N2_EX_8_ATOMIC_LOCK_MASK_LATCH_REG = 0x30010007ull;
+//DUPS: 31010007,
+static const uint64_t P9N2_EX_9_ATOMIC_LOCK_MASK_LATCH_REG = 0x32010007ull;
+//DUPS: 33010007,
+static const uint64_t P9N2_EX_10_ATOMIC_LOCK_MASK_LATCH_REG = 0x34010007ull;
+//DUPS: 35010007,
+static const uint64_t P9N2_EX_11_ATOMIC_LOCK_MASK_LATCH_REG = 0x36010007ull;
+//DUPS: 37010007,
+
+static const uint64_t P9N2_C_ATOMIC_LOCK_REG = 0x200F03FFull;
+
+static const uint64_t P9N2_C_0_ATOMIC_LOCK_REG = 0x200F03FFull;
+
+static const uint64_t P9N2_C_1_ATOMIC_LOCK_REG = 0x210F03FFull;
+
+static const uint64_t P9N2_C_2_ATOMIC_LOCK_REG = 0x220F03FFull;
+
+static const uint64_t P9N2_C_3_ATOMIC_LOCK_REG = 0x230F03FFull;
+
+static const uint64_t P9N2_C_4_ATOMIC_LOCK_REG = 0x240F03FFull;
+
+static const uint64_t P9N2_C_5_ATOMIC_LOCK_REG = 0x250F03FFull;
+
+static const uint64_t P9N2_C_6_ATOMIC_LOCK_REG = 0x260F03FFull;
+
+static const uint64_t P9N2_C_7_ATOMIC_LOCK_REG = 0x270F03FFull;
+
+static const uint64_t P9N2_C_8_ATOMIC_LOCK_REG = 0x280F03FFull;
+
+static const uint64_t P9N2_C_9_ATOMIC_LOCK_REG = 0x290F03FFull;
+
+static const uint64_t P9N2_C_10_ATOMIC_LOCK_REG = 0x2A0F03FFull;
+
+static const uint64_t P9N2_C_11_ATOMIC_LOCK_REG = 0x2B0F03FFull;
+
+static const uint64_t P9N2_C_12_ATOMIC_LOCK_REG = 0x2C0F03FFull;
+
+static const uint64_t P9N2_C_13_ATOMIC_LOCK_REG = 0x2D0F03FFull;
+
+static const uint64_t P9N2_C_14_ATOMIC_LOCK_REG = 0x2E0F03FFull;
+
+static const uint64_t P9N2_C_15_ATOMIC_LOCK_REG = 0x2F0F03FFull;
+
+static const uint64_t P9N2_C_16_ATOMIC_LOCK_REG = 0x300F03FFull;
+
+static const uint64_t P9N2_C_17_ATOMIC_LOCK_REG = 0x310F03FFull;
+
+static const uint64_t P9N2_C_18_ATOMIC_LOCK_REG = 0x320F03FFull;
+
+static const uint64_t P9N2_C_19_ATOMIC_LOCK_REG = 0x330F03FFull;
+
+static const uint64_t P9N2_C_20_ATOMIC_LOCK_REG = 0x340F03FFull;
+
+static const uint64_t P9N2_C_21_ATOMIC_LOCK_REG = 0x350F03FFull;
+
+static const uint64_t P9N2_C_22_ATOMIC_LOCK_REG = 0x360F03FFull;
+
+static const uint64_t P9N2_C_23_ATOMIC_LOCK_REG = 0x370F03FFull;
+
+static const uint64_t P9N2_EQ_ATOMIC_LOCK_REG = 0x100F03FFull;
+
+static const uint64_t P9N2_EQ_0_ATOMIC_LOCK_REG = 0x100F03FFull;
+
+static const uint64_t P9N2_EQ_1_ATOMIC_LOCK_REG = 0x110F03FFull;
+
+static const uint64_t P9N2_EQ_2_ATOMIC_LOCK_REG = 0x120F03FFull;
+
+static const uint64_t P9N2_EQ_3_ATOMIC_LOCK_REG = 0x130F03FFull;
+
+static const uint64_t P9N2_EQ_4_ATOMIC_LOCK_REG = 0x140F03FFull;
+
+static const uint64_t P9N2_EQ_5_ATOMIC_LOCK_REG = 0x150F03FFull;
+
+static const uint64_t P9N2_EX_ATOMIC_LOCK_REG = 0x200F03FFull;
+//DUPS: 210F03FF,
+static const uint64_t P9N2_EX_0_ATOMIC_LOCK_REG = 0x200F03FFull;
+//DUPS: 210F03FF,
+static const uint64_t P9N2_EX_1_ATOMIC_LOCK_REG = 0x220F03FFull;
+//DUPS: 220F03FF,
+static const uint64_t P9N2_EX_2_ATOMIC_LOCK_REG = 0x240F03FFull;
+//DUPS: 250F03FF,
+static const uint64_t P9N2_EX_3_ATOMIC_LOCK_REG = 0x260F03FFull;
+//DUPS: 270F03FF,
+static const uint64_t P9N2_EX_4_ATOMIC_LOCK_REG = 0x280F03FFull;
+//DUPS: 290F03FF,
+static const uint64_t P9N2_EX_5_ATOMIC_LOCK_REG = 0x2A0F03FFull;
+//DUPS: 2B0F03FF,
+static const uint64_t P9N2_EX_6_ATOMIC_LOCK_REG = 0x2C0F03FFull;
+//DUPS: 2D0F03FF,
+static const uint64_t P9N2_EX_7_ATOMIC_LOCK_REG = 0x2E0F03FFull;
+//DUPS: 2F0F03FF,
+static const uint64_t P9N2_EX_8_ATOMIC_LOCK_REG = 0x300F03FFull;
+//DUPS: 310F03FF,
+static const uint64_t P9N2_EX_9_ATOMIC_LOCK_REG = 0x320F03FFull;
+//DUPS: 330F03FF,
+static const uint64_t P9N2_EX_10_ATOMIC_LOCK_REG = 0x340F03FFull;
+//DUPS: 350F03FF,
+static const uint64_t P9N2_EX_11_ATOMIC_LOCK_REG = 0x360F03FFull;
+//DUPS: 370F03FF,
+
+static const uint64_t P9N2_C_ATTN_INTERRUPT_REG = 0x200F001Aull;
+
+static const uint64_t P9N2_C_0_ATTN_INTERRUPT_REG = 0x200F001Aull;
+
+static const uint64_t P9N2_C_1_ATTN_INTERRUPT_REG = 0x210F001Aull;
+
+static const uint64_t P9N2_C_2_ATTN_INTERRUPT_REG = 0x220F001Aull;
+
+static const uint64_t P9N2_C_3_ATTN_INTERRUPT_REG = 0x230F001Aull;
+
+static const uint64_t P9N2_C_4_ATTN_INTERRUPT_REG = 0x240F001Aull;
+
+static const uint64_t P9N2_C_5_ATTN_INTERRUPT_REG = 0x250F001Aull;
+
+static const uint64_t P9N2_C_6_ATTN_INTERRUPT_REG = 0x260F001Aull;
+
+static const uint64_t P9N2_C_7_ATTN_INTERRUPT_REG = 0x270F001Aull;
+
+static const uint64_t P9N2_C_8_ATTN_INTERRUPT_REG = 0x280F001Aull;
+
+static const uint64_t P9N2_C_9_ATTN_INTERRUPT_REG = 0x290F001Aull;
+
+static const uint64_t P9N2_C_10_ATTN_INTERRUPT_REG = 0x2A0F001Aull;
+
+static const uint64_t P9N2_C_11_ATTN_INTERRUPT_REG = 0x2B0F001Aull;
+
+static const uint64_t P9N2_C_12_ATTN_INTERRUPT_REG = 0x2C0F001Aull;
+
+static const uint64_t P9N2_C_13_ATTN_INTERRUPT_REG = 0x2D0F001Aull;
+
+static const uint64_t P9N2_C_14_ATTN_INTERRUPT_REG = 0x2E0F001Aull;
+
+static const uint64_t P9N2_C_15_ATTN_INTERRUPT_REG = 0x2F0F001Aull;
+
+static const uint64_t P9N2_C_16_ATTN_INTERRUPT_REG = 0x300F001Aull;
+
+static const uint64_t P9N2_C_17_ATTN_INTERRUPT_REG = 0x310F001Aull;
+
+static const uint64_t P9N2_C_18_ATTN_INTERRUPT_REG = 0x320F001Aull;
+
+static const uint64_t P9N2_C_19_ATTN_INTERRUPT_REG = 0x330F001Aull;
+
+static const uint64_t P9N2_C_20_ATTN_INTERRUPT_REG = 0x340F001Aull;
+
+static const uint64_t P9N2_C_21_ATTN_INTERRUPT_REG = 0x350F001Aull;
+
+static const uint64_t P9N2_C_22_ATTN_INTERRUPT_REG = 0x360F001Aull;
+
+static const uint64_t P9N2_C_23_ATTN_INTERRUPT_REG = 0x370F001Aull;
+
+static const uint64_t P9N2_EQ_ATTN_INTERRUPT_REG = 0x100F001Aull;
+
+static const uint64_t P9N2_EQ_0_ATTN_INTERRUPT_REG = 0x100F001Aull;
+
+static const uint64_t P9N2_EQ_1_ATTN_INTERRUPT_REG = 0x110F001Aull;
+
+static const uint64_t P9N2_EQ_2_ATTN_INTERRUPT_REG = 0x120F001Aull;
+
+static const uint64_t P9N2_EQ_3_ATTN_INTERRUPT_REG = 0x130F001Aull;
+
+static const uint64_t P9N2_EQ_4_ATTN_INTERRUPT_REG = 0x140F001Aull;
+
+static const uint64_t P9N2_EQ_5_ATTN_INTERRUPT_REG = 0x150F001Aull;
+
+static const uint64_t P9N2_EX_ATTN_INTERRUPT_REG = 0x200F001Aull;
+//DUPS: 210F001A,
+static const uint64_t P9N2_EX_0_ATTN_INTERRUPT_REG = 0x200F001Aull;
+//DUPS: 210F001A,
+static const uint64_t P9N2_EX_1_ATTN_INTERRUPT_REG = 0x220F001Aull;
+//DUPS: 220F001A,
+static const uint64_t P9N2_EX_2_ATTN_INTERRUPT_REG = 0x240F001Aull;
+//DUPS: 250F001A,
+static const uint64_t P9N2_EX_3_ATTN_INTERRUPT_REG = 0x260F001Aull;
+//DUPS: 270F001A,
+static const uint64_t P9N2_EX_4_ATTN_INTERRUPT_REG = 0x280F001Aull;
+//DUPS: 290F001A,
+static const uint64_t P9N2_EX_5_ATTN_INTERRUPT_REG = 0x2A0F001Aull;
+//DUPS: 2B0F001A,
+static const uint64_t P9N2_EX_6_ATTN_INTERRUPT_REG = 0x2C0F001Aull;
+//DUPS: 2D0F001A,
+static const uint64_t P9N2_EX_7_ATTN_INTERRUPT_REG = 0x2E0F001Aull;
+//DUPS: 2F0F001A,
+static const uint64_t P9N2_EX_8_ATTN_INTERRUPT_REG = 0x300F001Aull;
+//DUPS: 310F001A,
+static const uint64_t P9N2_EX_9_ATTN_INTERRUPT_REG = 0x320F001Aull;
+//DUPS: 330F001A,
+static const uint64_t P9N2_EX_10_ATTN_INTERRUPT_REG = 0x340F001Aull;
+//DUPS: 350F001A,
+static const uint64_t P9N2_EX_11_ATTN_INTERRUPT_REG = 0x360F001Aull;
+//DUPS: 370F001A,
+
+static const uint64_t P9N2_C_BIST = 0x2003000Bull;
+
+static const uint64_t P9N2_C_0_BIST = 0x2003000Bull;
+
+static const uint64_t P9N2_C_1_BIST = 0x2103000Bull;
+
+static const uint64_t P9N2_C_2_BIST = 0x2203000Bull;
+
+static const uint64_t P9N2_C_3_BIST = 0x2303000Bull;
+
+static const uint64_t P9N2_C_4_BIST = 0x2403000Bull;
+
+static const uint64_t P9N2_C_5_BIST = 0x2503000Bull;
+
+static const uint64_t P9N2_C_6_BIST = 0x2603000Bull;
+
+static const uint64_t P9N2_C_7_BIST = 0x2703000Bull;
+
+static const uint64_t P9N2_C_8_BIST = 0x2803000Bull;
+
+static const uint64_t P9N2_C_9_BIST = 0x2903000Bull;
+
+static const uint64_t P9N2_C_10_BIST = 0x2A03000Bull;
+
+static const uint64_t P9N2_C_11_BIST = 0x2B03000Bull;
+
+static const uint64_t P9N2_C_12_BIST = 0x2C03000Bull;
+
+static const uint64_t P9N2_C_13_BIST = 0x2D03000Bull;
+
+static const uint64_t P9N2_C_14_BIST = 0x2E03000Bull;
+
+static const uint64_t P9N2_C_15_BIST = 0x2F03000Bull;
+
+static const uint64_t P9N2_C_16_BIST = 0x3003000Bull;
+
+static const uint64_t P9N2_C_17_BIST = 0x3103000Bull;
+
+static const uint64_t P9N2_C_18_BIST = 0x3203000Bull;
+
+static const uint64_t P9N2_C_19_BIST = 0x3303000Bull;
+
+static const uint64_t P9N2_C_20_BIST = 0x3403000Bull;
+
+static const uint64_t P9N2_C_21_BIST = 0x3503000Bull;
+
+static const uint64_t P9N2_C_22_BIST = 0x3603000Bull;
+
+static const uint64_t P9N2_C_23_BIST = 0x3703000Bull;
+
+static const uint64_t P9N2_EQ_BIST = 0x1003000Bull;
+
+static const uint64_t P9N2_EQ_0_BIST = 0x1003000Bull;
+
+static const uint64_t P9N2_EQ_1_BIST = 0x1103000Bull;
+
+static const uint64_t P9N2_EQ_2_BIST = 0x1203000Bull;
+
+static const uint64_t P9N2_EQ_3_BIST = 0x1303000Bull;
+
+static const uint64_t P9N2_EQ_4_BIST = 0x1403000Bull;
+
+static const uint64_t P9N2_EQ_5_BIST = 0x1503000Bull;
+
+static const uint64_t P9N2_EX_BIST = 0x2003000Bull;
+//DUPS: 2103000B,
+static const uint64_t P9N2_EX_0_BIST = 0x2003000Bull;
+//DUPS: 2103000B,
+static const uint64_t P9N2_EX_1_BIST = 0x2203000Bull;
+//DUPS: 2303000B,
+static const uint64_t P9N2_EX_2_BIST = 0x2403000Bull;
+//DUPS: 2503000B,
+static const uint64_t P9N2_EX_3_BIST = 0x2603000Bull;
+//DUPS: 2703000B,
+static const uint64_t P9N2_EX_4_BIST = 0x2803000Bull;
+//DUPS: 2903000B,
+static const uint64_t P9N2_EX_5_BIST = 0x2A03000Bull;
+//DUPS: 2B03000B,
+static const uint64_t P9N2_EX_6_BIST = 0x2C03000Bull;
+//DUPS: 2D03000B,
+static const uint64_t P9N2_EX_7_BIST = 0x2F03000Bull;
+//DUPS: 2F03000B,
+static const uint64_t P9N2_EX_8_BIST = 0x3003000Bull;
+//DUPS: 3103000B,
+static const uint64_t P9N2_EX_9_BIST = 0x3203000Bull;
+//DUPS: 3303000B,
+static const uint64_t P9N2_EX_10_BIST = 0x3403000Bull;
+//DUPS: 3503000B,
+static const uint64_t P9N2_EX_11_BIST = 0x3603000Bull;
+//DUPS: 3703000B,
+
+static const uint64_t P9N2_C_CC_ATOMIC_LOCK_REG = 0x200303FFull;
+
+static const uint64_t P9N2_C_0_CC_ATOMIC_LOCK_REG = 0x200303FFull;
+
+static const uint64_t P9N2_C_1_CC_ATOMIC_LOCK_REG = 0x210303FFull;
+
+static const uint64_t P9N2_C_2_CC_ATOMIC_LOCK_REG = 0x220303FFull;
+
+static const uint64_t P9N2_C_3_CC_ATOMIC_LOCK_REG = 0x230303FFull;
+
+static const uint64_t P9N2_C_4_CC_ATOMIC_LOCK_REG = 0x240303FFull;
+
+static const uint64_t P9N2_C_5_CC_ATOMIC_LOCK_REG = 0x250303FFull;
+
+static const uint64_t P9N2_C_6_CC_ATOMIC_LOCK_REG = 0x260303FFull;
+
+static const uint64_t P9N2_C_7_CC_ATOMIC_LOCK_REG = 0x270303FFull;
+
+static const uint64_t P9N2_C_8_CC_ATOMIC_LOCK_REG = 0x280303FFull;
+
+static const uint64_t P9N2_C_9_CC_ATOMIC_LOCK_REG = 0x290303FFull;
+
+static const uint64_t P9N2_C_10_CC_ATOMIC_LOCK_REG = 0x2A0303FFull;
+
+static const uint64_t P9N2_C_11_CC_ATOMIC_LOCK_REG = 0x2B0303FFull;
+
+static const uint64_t P9N2_C_12_CC_ATOMIC_LOCK_REG = 0x2C0303FFull;
+
+static const uint64_t P9N2_C_13_CC_ATOMIC_LOCK_REG = 0x2D0303FFull;
+
+static const uint64_t P9N2_C_14_CC_ATOMIC_LOCK_REG = 0x2E0303FFull;
+
+static const uint64_t P9N2_C_15_CC_ATOMIC_LOCK_REG = 0x2F0303FFull;
+
+static const uint64_t P9N2_C_16_CC_ATOMIC_LOCK_REG = 0x300303FFull;
+
+static const uint64_t P9N2_C_17_CC_ATOMIC_LOCK_REG = 0x310303FFull;
+
+static const uint64_t P9N2_C_18_CC_ATOMIC_LOCK_REG = 0x320303FFull;
+
+static const uint64_t P9N2_C_19_CC_ATOMIC_LOCK_REG = 0x330303FFull;
+
+static const uint64_t P9N2_C_20_CC_ATOMIC_LOCK_REG = 0x340303FFull;
+
+static const uint64_t P9N2_C_21_CC_ATOMIC_LOCK_REG = 0x350303FFull;
+
+static const uint64_t P9N2_C_22_CC_ATOMIC_LOCK_REG = 0x360303FFull;
+
+static const uint64_t P9N2_C_23_CC_ATOMIC_LOCK_REG = 0x370303FFull;
+
+static const uint64_t P9N2_EQ_CC_ATOMIC_LOCK_REG = 0x100303FFull;
+
+static const uint64_t P9N2_EQ_0_CC_ATOMIC_LOCK_REG = 0x100303FFull;
+
+static const uint64_t P9N2_EQ_1_CC_ATOMIC_LOCK_REG = 0x110303FFull;
+
+static const uint64_t P9N2_EQ_2_CC_ATOMIC_LOCK_REG = 0x120303FFull;
+
+static const uint64_t P9N2_EQ_3_CC_ATOMIC_LOCK_REG = 0x130303FFull;
+
+static const uint64_t P9N2_EQ_4_CC_ATOMIC_LOCK_REG = 0x140303FFull;
+
+static const uint64_t P9N2_EQ_5_CC_ATOMIC_LOCK_REG = 0x150303FFull;
+
+static const uint64_t P9N2_EX_CC_ATOMIC_LOCK_REG = 0x200303FFull;
+//DUPS: 210303FF,
+static const uint64_t P9N2_EX_0_CC_ATOMIC_LOCK_REG = 0x200303FFull;
+//DUPS: 210303FF,
+static const uint64_t P9N2_EX_1_CC_ATOMIC_LOCK_REG = 0x220303FFull;
+//DUPS: 230303FF,
+static const uint64_t P9N2_EX_2_CC_ATOMIC_LOCK_REG = 0x240303FFull;
+//DUPS: 250303FF,
+static const uint64_t P9N2_EX_3_CC_ATOMIC_LOCK_REG = 0x260303FFull;
+//DUPS: 270303FF,
+static const uint64_t P9N2_EX_4_CC_ATOMIC_LOCK_REG = 0x280303FFull;
+//DUPS: 290303FF,
+static const uint64_t P9N2_EX_5_CC_ATOMIC_LOCK_REG = 0x2A0303FFull;
+//DUPS: 2B0303FF,
+static const uint64_t P9N2_EX_6_CC_ATOMIC_LOCK_REG = 0x2C0303FFull;
+//DUPS: 2D0303FF,
+static const uint64_t P9N2_EX_7_CC_ATOMIC_LOCK_REG = 0x2F0303FFull;
+//DUPS: 2F0303FF,
+static const uint64_t P9N2_EX_8_CC_ATOMIC_LOCK_REG = 0x300303FFull;
+//DUPS: 310303FF,
+static const uint64_t P9N2_EX_9_CC_ATOMIC_LOCK_REG = 0x320303FFull;
+//DUPS: 330303FF,
+static const uint64_t P9N2_EX_10_CC_ATOMIC_LOCK_REG = 0x340303FFull;
+//DUPS: 350303FF,
+static const uint64_t P9N2_EX_11_CC_ATOMIC_LOCK_REG = 0x360303FFull;
+//DUPS: 370303FF,
+
+static const uint64_t P9N2_C_CC_PROTECT_MODE_REG = 0x200303FEull;
+
+static const uint64_t P9N2_C_0_CC_PROTECT_MODE_REG = 0x200303FEull;
+
+static const uint64_t P9N2_C_1_CC_PROTECT_MODE_REG = 0x210303FEull;
+
+static const uint64_t P9N2_C_2_CC_PROTECT_MODE_REG = 0x220303FEull;
+
+static const uint64_t P9N2_C_3_CC_PROTECT_MODE_REG = 0x230303FEull;
+
+static const uint64_t P9N2_C_4_CC_PROTECT_MODE_REG = 0x240303FEull;
+
+static const uint64_t P9N2_C_5_CC_PROTECT_MODE_REG = 0x250303FEull;
+
+static const uint64_t P9N2_C_6_CC_PROTECT_MODE_REG = 0x260303FEull;
+
+static const uint64_t P9N2_C_7_CC_PROTECT_MODE_REG = 0x270303FEull;
+
+static const uint64_t P9N2_C_8_CC_PROTECT_MODE_REG = 0x280303FEull;
+
+static const uint64_t P9N2_C_9_CC_PROTECT_MODE_REG = 0x290303FEull;
+
+static const uint64_t P9N2_C_10_CC_PROTECT_MODE_REG = 0x2A0303FEull;
+
+static const uint64_t P9N2_C_11_CC_PROTECT_MODE_REG = 0x2B0303FEull;
+
+static const uint64_t P9N2_C_12_CC_PROTECT_MODE_REG = 0x2C0303FEull;
+
+static const uint64_t P9N2_C_13_CC_PROTECT_MODE_REG = 0x2D0303FEull;
+
+static const uint64_t P9N2_C_14_CC_PROTECT_MODE_REG = 0x2E0303FEull;
+
+static const uint64_t P9N2_C_15_CC_PROTECT_MODE_REG = 0x2F0303FEull;
+
+static const uint64_t P9N2_C_16_CC_PROTECT_MODE_REG = 0x300303FEull;
+
+static const uint64_t P9N2_C_17_CC_PROTECT_MODE_REG = 0x310303FEull;
+
+static const uint64_t P9N2_C_18_CC_PROTECT_MODE_REG = 0x320303FEull;
+
+static const uint64_t P9N2_C_19_CC_PROTECT_MODE_REG = 0x330303FEull;
+
+static const uint64_t P9N2_C_20_CC_PROTECT_MODE_REG = 0x340303FEull;
+
+static const uint64_t P9N2_C_21_CC_PROTECT_MODE_REG = 0x350303FEull;
+
+static const uint64_t P9N2_C_22_CC_PROTECT_MODE_REG = 0x360303FEull;
+
+static const uint64_t P9N2_C_23_CC_PROTECT_MODE_REG = 0x370303FEull;
+
+static const uint64_t P9N2_EQ_CC_PROTECT_MODE_REG = 0x100303FEull;
+
+static const uint64_t P9N2_EQ_0_CC_PROTECT_MODE_REG = 0x100303FEull;
+
+static const uint64_t P9N2_EQ_1_CC_PROTECT_MODE_REG = 0x110303FEull;
+
+static const uint64_t P9N2_EQ_2_CC_PROTECT_MODE_REG = 0x120303FEull;
+
+static const uint64_t P9N2_EQ_3_CC_PROTECT_MODE_REG = 0x130303FEull;
+
+static const uint64_t P9N2_EQ_4_CC_PROTECT_MODE_REG = 0x140303FEull;
+
+static const uint64_t P9N2_EQ_5_CC_PROTECT_MODE_REG = 0x150303FEull;
+
+static const uint64_t P9N2_EX_CC_PROTECT_MODE_REG = 0x200303FEull;
+//DUPS: 210303FE,
+static const uint64_t P9N2_EX_0_CC_PROTECT_MODE_REG = 0x200303FEull;
+//DUPS: 210303FE,
+static const uint64_t P9N2_EX_1_CC_PROTECT_MODE_REG = 0x220303FEull;
+//DUPS: 230303FE,
+static const uint64_t P9N2_EX_2_CC_PROTECT_MODE_REG = 0x240303FEull;
+//DUPS: 250303FE,
+static const uint64_t P9N2_EX_3_CC_PROTECT_MODE_REG = 0x260303FEull;
+//DUPS: 270303FE,
+static const uint64_t P9N2_EX_4_CC_PROTECT_MODE_REG = 0x280303FEull;
+//DUPS: 290303FE,
+static const uint64_t P9N2_EX_5_CC_PROTECT_MODE_REG = 0x2A0303FEull;
+//DUPS: 2B0303FE,
+static const uint64_t P9N2_EX_6_CC_PROTECT_MODE_REG = 0x2C0303FEull;
+//DUPS: 2D0303FE,
+static const uint64_t P9N2_EX_7_CC_PROTECT_MODE_REG = 0x2F0303FEull;
+//DUPS: 2F0303FE,
+static const uint64_t P9N2_EX_8_CC_PROTECT_MODE_REG = 0x300303FEull;
+//DUPS: 310303FE,
+static const uint64_t P9N2_EX_9_CC_PROTECT_MODE_REG = 0x320303FEull;
+//DUPS: 330303FE,
+static const uint64_t P9N2_EX_10_CC_PROTECT_MODE_REG = 0x340303FEull;
+//DUPS: 350303FE,
+static const uint64_t P9N2_EX_11_CC_PROTECT_MODE_REG = 0x360303FEull;
+//DUPS: 370303FE,
+
+static const uint64_t P9N2_C_CLK_REGION = 0x20030006ull;
+
+static const uint64_t P9N2_C_0_CLK_REGION = 0x20030006ull;
+
+static const uint64_t P9N2_C_1_CLK_REGION = 0x21030006ull;
+
+static const uint64_t P9N2_C_2_CLK_REGION = 0x22030006ull;
+
+static const uint64_t P9N2_C_3_CLK_REGION = 0x23030006ull;
+
+static const uint64_t P9N2_C_4_CLK_REGION = 0x24030006ull;
+
+static const uint64_t P9N2_C_5_CLK_REGION = 0x25030006ull;
+
+static const uint64_t P9N2_C_6_CLK_REGION = 0x26030006ull;
+
+static const uint64_t P9N2_C_7_CLK_REGION = 0x27030006ull;
+
+static const uint64_t P9N2_C_8_CLK_REGION = 0x28030006ull;
+
+static const uint64_t P9N2_C_9_CLK_REGION = 0x29030006ull;
+
+static const uint64_t P9N2_C_10_CLK_REGION = 0x2A030006ull;
+
+static const uint64_t P9N2_C_11_CLK_REGION = 0x2B030006ull;
+
+static const uint64_t P9N2_C_12_CLK_REGION = 0x2C030006ull;
+
+static const uint64_t P9N2_C_13_CLK_REGION = 0x2D030006ull;
+
+static const uint64_t P9N2_C_14_CLK_REGION = 0x2E030006ull;
+
+static const uint64_t P9N2_C_15_CLK_REGION = 0x2F030006ull;
+
+static const uint64_t P9N2_C_16_CLK_REGION = 0x30030006ull;
+
+static const uint64_t P9N2_C_17_CLK_REGION = 0x31030006ull;
+
+static const uint64_t P9N2_C_18_CLK_REGION = 0x32030006ull;
+
+static const uint64_t P9N2_C_19_CLK_REGION = 0x33030006ull;
+
+static const uint64_t P9N2_C_20_CLK_REGION = 0x34030006ull;
+
+static const uint64_t P9N2_C_21_CLK_REGION = 0x35030006ull;
+
+static const uint64_t P9N2_C_22_CLK_REGION = 0x36030006ull;
+
+static const uint64_t P9N2_C_23_CLK_REGION = 0x37030006ull;
+
+static const uint64_t P9N2_EQ_CLK_REGION = 0x10030006ull;
+
+static const uint64_t P9N2_EQ_0_CLK_REGION = 0x10030006ull;
+
+static const uint64_t P9N2_EQ_1_CLK_REGION = 0x11030006ull;
+
+static const uint64_t P9N2_EQ_2_CLK_REGION = 0x12030006ull;
+
+static const uint64_t P9N2_EQ_3_CLK_REGION = 0x13030006ull;
+
+static const uint64_t P9N2_EQ_4_CLK_REGION = 0x14030006ull;
+
+static const uint64_t P9N2_EQ_5_CLK_REGION = 0x15030006ull;
+
+static const uint64_t P9N2_EX_CLK_REGION = 0x20030006ull;
+//DUPS: 21030006,
+static const uint64_t P9N2_EX_0_CLK_REGION = 0x20030006ull;
+//DUPS: 21030006,
+static const uint64_t P9N2_EX_1_CLK_REGION = 0x22030006ull;
+//DUPS: 23030006,
+static const uint64_t P9N2_EX_2_CLK_REGION = 0x24030006ull;
+//DUPS: 25030006,
+static const uint64_t P9N2_EX_3_CLK_REGION = 0x26030006ull;
+//DUPS: 27030006,
+static const uint64_t P9N2_EX_4_CLK_REGION = 0x28030006ull;
+//DUPS: 29030006,
+static const uint64_t P9N2_EX_5_CLK_REGION = 0x2A030006ull;
+//DUPS: 2B030006,
+static const uint64_t P9N2_EX_6_CLK_REGION = 0x2C030006ull;
+//DUPS: 2D030006,
+static const uint64_t P9N2_EX_7_CLK_REGION = 0x2F030006ull;
+//DUPS: 2F030006,
+static const uint64_t P9N2_EX_8_CLK_REGION = 0x30030006ull;
+//DUPS: 31030006,
+static const uint64_t P9N2_EX_9_CLK_REGION = 0x32030006ull;
+//DUPS: 33030006,
+static const uint64_t P9N2_EX_10_CLK_REGION = 0x34030006ull;
+//DUPS: 35030006,
+static const uint64_t P9N2_EX_11_CLK_REGION = 0x36030006ull;
+//DUPS: 37030006,
+
+static const uint64_t P9N2_C_CLOCK_STAT_ARY = 0x2003000Aull;
+
+static const uint64_t P9N2_C_0_CLOCK_STAT_ARY = 0x2003000Aull;
+
+static const uint64_t P9N2_C_1_CLOCK_STAT_ARY = 0x2103000Aull;
+
+static const uint64_t P9N2_C_2_CLOCK_STAT_ARY = 0x2203000Aull;
+
+static const uint64_t P9N2_C_3_CLOCK_STAT_ARY = 0x2303000Aull;
+
+static const uint64_t P9N2_C_4_CLOCK_STAT_ARY = 0x2403000Aull;
+
+static const uint64_t P9N2_C_5_CLOCK_STAT_ARY = 0x2503000Aull;
+
+static const uint64_t P9N2_C_6_CLOCK_STAT_ARY = 0x2603000Aull;
+
+static const uint64_t P9N2_C_7_CLOCK_STAT_ARY = 0x2703000Aull;
+
+static const uint64_t P9N2_C_8_CLOCK_STAT_ARY = 0x2803000Aull;
+
+static const uint64_t P9N2_C_9_CLOCK_STAT_ARY = 0x2903000Aull;
+
+static const uint64_t P9N2_C_10_CLOCK_STAT_ARY = 0x2A03000Aull;
+
+static const uint64_t P9N2_C_11_CLOCK_STAT_ARY = 0x2B03000Aull;
+
+static const uint64_t P9N2_C_12_CLOCK_STAT_ARY = 0x2C03000Aull;
+
+static const uint64_t P9N2_C_13_CLOCK_STAT_ARY = 0x2D03000Aull;
+
+static const uint64_t P9N2_C_14_CLOCK_STAT_ARY = 0x2E03000Aull;
+
+static const uint64_t P9N2_C_15_CLOCK_STAT_ARY = 0x2F03000Aull;
+
+static const uint64_t P9N2_C_16_CLOCK_STAT_ARY = 0x3003000Aull;
+
+static const uint64_t P9N2_C_17_CLOCK_STAT_ARY = 0x3103000Aull;
+
+static const uint64_t P9N2_C_18_CLOCK_STAT_ARY = 0x3203000Aull;
+
+static const uint64_t P9N2_C_19_CLOCK_STAT_ARY = 0x3303000Aull;
+
+static const uint64_t P9N2_C_20_CLOCK_STAT_ARY = 0x3403000Aull;
+
+static const uint64_t P9N2_C_21_CLOCK_STAT_ARY = 0x3503000Aull;
+
+static const uint64_t P9N2_C_22_CLOCK_STAT_ARY = 0x3603000Aull;
+
+static const uint64_t P9N2_C_23_CLOCK_STAT_ARY = 0x3703000Aull;
+
+static const uint64_t P9N2_EQ_CLOCK_STAT_ARY = 0x1003000Aull;
+
+static const uint64_t P9N2_EQ_0_CLOCK_STAT_ARY = 0x1003000Aull;
+
+static const uint64_t P9N2_EQ_1_CLOCK_STAT_ARY = 0x1103000Aull;
+
+static const uint64_t P9N2_EQ_2_CLOCK_STAT_ARY = 0x1203000Aull;
+
+static const uint64_t P9N2_EQ_3_CLOCK_STAT_ARY = 0x1303000Aull;
+
+static const uint64_t P9N2_EQ_4_CLOCK_STAT_ARY = 0x1403000Aull;
+
+static const uint64_t P9N2_EQ_5_CLOCK_STAT_ARY = 0x1503000Aull;
+
+static const uint64_t P9N2_EX_CLOCK_STAT_ARY = 0x2003000Aull;
+//DUPS: 2103000A,
+static const uint64_t P9N2_EX_0_CLOCK_STAT_ARY = 0x2003000Aull;
+//DUPS: 2103000A,
+static const uint64_t P9N2_EX_1_CLOCK_STAT_ARY = 0x2203000Aull;
+//DUPS: 2303000A,
+static const uint64_t P9N2_EX_2_CLOCK_STAT_ARY = 0x2403000Aull;
+//DUPS: 2503000A,
+static const uint64_t P9N2_EX_3_CLOCK_STAT_ARY = 0x2603000Aull;
+//DUPS: 2703000A,
+static const uint64_t P9N2_EX_4_CLOCK_STAT_ARY = 0x2803000Aull;
+//DUPS: 2903000A,
+static const uint64_t P9N2_EX_5_CLOCK_STAT_ARY = 0x2A03000Aull;
+//DUPS: 2B03000A,
+static const uint64_t P9N2_EX_6_CLOCK_STAT_ARY = 0x2C03000Aull;
+//DUPS: 2D03000A,
+static const uint64_t P9N2_EX_7_CLOCK_STAT_ARY = 0x2F03000Aull;
+//DUPS: 2F03000A,
+static const uint64_t P9N2_EX_8_CLOCK_STAT_ARY = 0x3003000Aull;
+//DUPS: 3103000A,
+static const uint64_t P9N2_EX_9_CLOCK_STAT_ARY = 0x3203000Aull;
+//DUPS: 3303000A,
+static const uint64_t P9N2_EX_10_CLOCK_STAT_ARY = 0x3403000Aull;
+//DUPS: 3503000A,
+static const uint64_t P9N2_EX_11_CLOCK_STAT_ARY = 0x3603000Aull;
+//DUPS: 3703000A,
+
+static const uint64_t P9N2_C_CLOCK_STAT_NSL = 0x20030009ull;
+
+static const uint64_t P9N2_C_0_CLOCK_STAT_NSL = 0x20030009ull;
+
+static const uint64_t P9N2_C_1_CLOCK_STAT_NSL = 0x21030009ull;
+
+static const uint64_t P9N2_C_2_CLOCK_STAT_NSL = 0x22030009ull;
+
+static const uint64_t P9N2_C_3_CLOCK_STAT_NSL = 0x23030009ull;
+
+static const uint64_t P9N2_C_4_CLOCK_STAT_NSL = 0x24030009ull;
+
+static const uint64_t P9N2_C_5_CLOCK_STAT_NSL = 0x25030009ull;
+
+static const uint64_t P9N2_C_6_CLOCK_STAT_NSL = 0x26030009ull;
+
+static const uint64_t P9N2_C_7_CLOCK_STAT_NSL = 0x27030009ull;
+
+static const uint64_t P9N2_C_8_CLOCK_STAT_NSL = 0x28030009ull;
+
+static const uint64_t P9N2_C_9_CLOCK_STAT_NSL = 0x29030009ull;
+
+static const uint64_t P9N2_C_10_CLOCK_STAT_NSL = 0x2A030009ull;
+
+static const uint64_t P9N2_C_11_CLOCK_STAT_NSL = 0x2B030009ull;
+
+static const uint64_t P9N2_C_12_CLOCK_STAT_NSL = 0x2C030009ull;
+
+static const uint64_t P9N2_C_13_CLOCK_STAT_NSL = 0x2D030009ull;
+
+static const uint64_t P9N2_C_14_CLOCK_STAT_NSL = 0x2E030009ull;
+
+static const uint64_t P9N2_C_15_CLOCK_STAT_NSL = 0x2F030009ull;
+
+static const uint64_t P9N2_C_16_CLOCK_STAT_NSL = 0x30030009ull;
+
+static const uint64_t P9N2_C_17_CLOCK_STAT_NSL = 0x31030009ull;
+
+static const uint64_t P9N2_C_18_CLOCK_STAT_NSL = 0x32030009ull;
+
+static const uint64_t P9N2_C_19_CLOCK_STAT_NSL = 0x33030009ull;
+
+static const uint64_t P9N2_C_20_CLOCK_STAT_NSL = 0x34030009ull;
+
+static const uint64_t P9N2_C_21_CLOCK_STAT_NSL = 0x35030009ull;
+
+static const uint64_t P9N2_C_22_CLOCK_STAT_NSL = 0x36030009ull;
+
+static const uint64_t P9N2_C_23_CLOCK_STAT_NSL = 0x37030009ull;
+
+static const uint64_t P9N2_EQ_CLOCK_STAT_NSL = 0x10030009ull;
+
+static const uint64_t P9N2_EQ_0_CLOCK_STAT_NSL = 0x10030009ull;
+
+static const uint64_t P9N2_EQ_1_CLOCK_STAT_NSL = 0x11030009ull;
+
+static const uint64_t P9N2_EQ_2_CLOCK_STAT_NSL = 0x12030009ull;
+
+static const uint64_t P9N2_EQ_3_CLOCK_STAT_NSL = 0x13030009ull;
+
+static const uint64_t P9N2_EQ_4_CLOCK_STAT_NSL = 0x14030009ull;
+
+static const uint64_t P9N2_EQ_5_CLOCK_STAT_NSL = 0x15030009ull;
+
+static const uint64_t P9N2_EX_CLOCK_STAT_NSL = 0x20030009ull;
+//DUPS: 21030009,
+static const uint64_t P9N2_EX_0_CLOCK_STAT_NSL = 0x20030009ull;
+//DUPS: 21030009,
+static const uint64_t P9N2_EX_1_CLOCK_STAT_NSL = 0x22030009ull;
+//DUPS: 23030009,
+static const uint64_t P9N2_EX_2_CLOCK_STAT_NSL = 0x24030009ull;
+//DUPS: 25030009,
+static const uint64_t P9N2_EX_3_CLOCK_STAT_NSL = 0x26030009ull;
+//DUPS: 27030009,
+static const uint64_t P9N2_EX_4_CLOCK_STAT_NSL = 0x28030009ull;
+//DUPS: 29030009,
+static const uint64_t P9N2_EX_5_CLOCK_STAT_NSL = 0x2A030009ull;
+//DUPS: 2B030009,
+static const uint64_t P9N2_EX_6_CLOCK_STAT_NSL = 0x2C030009ull;
+//DUPS: 2D030009,
+static const uint64_t P9N2_EX_7_CLOCK_STAT_NSL = 0x2F030009ull;
+//DUPS: 2F030009,
+static const uint64_t P9N2_EX_8_CLOCK_STAT_NSL = 0x30030009ull;
+//DUPS: 31030009,
+static const uint64_t P9N2_EX_9_CLOCK_STAT_NSL = 0x32030009ull;
+//DUPS: 33030009,
+static const uint64_t P9N2_EX_10_CLOCK_STAT_NSL = 0x34030009ull;
+//DUPS: 35030009,
+static const uint64_t P9N2_EX_11_CLOCK_STAT_NSL = 0x36030009ull;
+//DUPS: 37030009,
+
+static const uint64_t P9N2_C_CLOCK_STAT_SL = 0x20030008ull;
+
+static const uint64_t P9N2_C_0_CLOCK_STAT_SL = 0x20030008ull;
+
+static const uint64_t P9N2_C_1_CLOCK_STAT_SL = 0x21030008ull;
+
+static const uint64_t P9N2_C_2_CLOCK_STAT_SL = 0x22030008ull;
+
+static const uint64_t P9N2_C_3_CLOCK_STAT_SL = 0x23030008ull;
+
+static const uint64_t P9N2_C_4_CLOCK_STAT_SL = 0x24030008ull;
+
+static const uint64_t P9N2_C_5_CLOCK_STAT_SL = 0x25030008ull;
+
+static const uint64_t P9N2_C_6_CLOCK_STAT_SL = 0x26030008ull;
+
+static const uint64_t P9N2_C_7_CLOCK_STAT_SL = 0x27030008ull;
+
+static const uint64_t P9N2_C_8_CLOCK_STAT_SL = 0x28030008ull;
+
+static const uint64_t P9N2_C_9_CLOCK_STAT_SL = 0x29030008ull;
+
+static const uint64_t P9N2_C_10_CLOCK_STAT_SL = 0x2A030008ull;
+
+static const uint64_t P9N2_C_11_CLOCK_STAT_SL = 0x2B030008ull;
+
+static const uint64_t P9N2_C_12_CLOCK_STAT_SL = 0x2C030008ull;
+
+static const uint64_t P9N2_C_13_CLOCK_STAT_SL = 0x2D030008ull;
+
+static const uint64_t P9N2_C_14_CLOCK_STAT_SL = 0x2E030008ull;
+
+static const uint64_t P9N2_C_15_CLOCK_STAT_SL = 0x2F030008ull;
+
+static const uint64_t P9N2_C_16_CLOCK_STAT_SL = 0x30030008ull;
+
+static const uint64_t P9N2_C_17_CLOCK_STAT_SL = 0x31030008ull;
+
+static const uint64_t P9N2_C_18_CLOCK_STAT_SL = 0x32030008ull;
+
+static const uint64_t P9N2_C_19_CLOCK_STAT_SL = 0x33030008ull;
+
+static const uint64_t P9N2_C_20_CLOCK_STAT_SL = 0x34030008ull;
+
+static const uint64_t P9N2_C_21_CLOCK_STAT_SL = 0x35030008ull;
+
+static const uint64_t P9N2_C_22_CLOCK_STAT_SL = 0x36030008ull;
+
+static const uint64_t P9N2_C_23_CLOCK_STAT_SL = 0x37030008ull;
+
+static const uint64_t P9N2_EQ_CLOCK_STAT_SL = 0x10030008ull;
+
+static const uint64_t P9N2_EQ_0_CLOCK_STAT_SL = 0x10030008ull;
+
+static const uint64_t P9N2_EQ_1_CLOCK_STAT_SL = 0x11030008ull;
+
+static const uint64_t P9N2_EQ_2_CLOCK_STAT_SL = 0x12030008ull;
+
+static const uint64_t P9N2_EQ_3_CLOCK_STAT_SL = 0x13030008ull;
+
+static const uint64_t P9N2_EQ_4_CLOCK_STAT_SL = 0x14030008ull;
+
+static const uint64_t P9N2_EQ_5_CLOCK_STAT_SL = 0x15030008ull;
+
+static const uint64_t P9N2_EX_CLOCK_STAT_SL = 0x20030008ull;
+//DUPS: 21030008,
+static const uint64_t P9N2_EX_0_CLOCK_STAT_SL = 0x20030008ull;
+//DUPS: 21030008,
+static const uint64_t P9N2_EX_1_CLOCK_STAT_SL = 0x22030008ull;
+//DUPS: 23030008,
+static const uint64_t P9N2_EX_2_CLOCK_STAT_SL = 0x24030008ull;
+//DUPS: 25030008,
+static const uint64_t P9N2_EX_3_CLOCK_STAT_SL = 0x26030008ull;
+//DUPS: 27030008,
+static const uint64_t P9N2_EX_4_CLOCK_STAT_SL = 0x28030008ull;
+//DUPS: 29030008,
+static const uint64_t P9N2_EX_5_CLOCK_STAT_SL = 0x2A030008ull;
+//DUPS: 2B030008,
+static const uint64_t P9N2_EX_6_CLOCK_STAT_SL = 0x2C030008ull;
+//DUPS: 2D030008,
+static const uint64_t P9N2_EX_7_CLOCK_STAT_SL = 0x2F030008ull;
+//DUPS: 2F030008,
+static const uint64_t P9N2_EX_8_CLOCK_STAT_SL = 0x30030008ull;
+//DUPS: 31030008,
+static const uint64_t P9N2_EX_9_CLOCK_STAT_SL = 0x32030008ull;
+//DUPS: 33030008,
+static const uint64_t P9N2_EX_10_CLOCK_STAT_SL = 0x34030008ull;
+//DUPS: 35030008,
+static const uint64_t P9N2_EX_11_CLOCK_STAT_SL = 0x36030008ull;
+//DUPS: 37030008,
+
+static const uint64_t P9N2_EX_CME_LCL_DBG_PPE = 0x109010120ull;
+
+static const uint64_t P9N2_EX_CME_LCL_DBG_PPE1 = 0x109010138ull;
+
+static const uint64_t P9N2_EX_CME_LCL_DBG_PPE2 = 0x109010130ull;
+
+static const uint64_t P9N2_EX_0_CME_LCL_DBG_PPE = 0x109010120ull;
+
+static const uint64_t P9N2_EX_0_CME_LCL_DBG_PPE1 = 0x109010138ull;
+
+static const uint64_t P9N2_EX_0_CME_LCL_DBG_PPE2 = 0x109010130ull;
+
+static const uint64_t P9N2_EX_1_CME_LCL_DBG_PPE = 0x109020120ull;
+
+static const uint64_t P9N2_EX_1_CME_LCL_DBG_PPE1 = 0x109020138ull;
+
+static const uint64_t P9N2_EX_1_CME_LCL_DBG_PPE2 = 0x109020130ull;
+
+static const uint64_t P9N2_EX_2_CME_LCL_DBG_PPE = 0x10A010120ull;
+
+static const uint64_t P9N2_EX_2_CME_LCL_DBG_PPE1 = 0x10A010138ull;
+
+static const uint64_t P9N2_EX_2_CME_LCL_DBG_PPE2 = 0x10A010130ull;
+
+static const uint64_t P9N2_EX_3_CME_LCL_DBG_PPE = 0x10A020120ull;
+
+static const uint64_t P9N2_EX_3_CME_LCL_DBG_PPE1 = 0x10A020138ull;
+
+static const uint64_t P9N2_EX_3_CME_LCL_DBG_PPE2 = 0x10A020130ull;
+
+static const uint64_t P9N2_EX_4_CME_LCL_DBG_PPE = 0x10B010120ull;
+
+static const uint64_t P9N2_EX_4_CME_LCL_DBG_PPE1 = 0x10B010138ull;
+
+static const uint64_t P9N2_EX_4_CME_LCL_DBG_PPE2 = 0x10B010130ull;
+
+static const uint64_t P9N2_EX_5_CME_LCL_DBG_PPE = 0x10B020120ull;
+
+static const uint64_t P9N2_EX_5_CME_LCL_DBG_PPE1 = 0x10B020138ull;
+
+static const uint64_t P9N2_EX_5_CME_LCL_DBG_PPE2 = 0x10B020130ull;
+
+static const uint64_t P9N2_EX_6_CME_LCL_DBG_PPE = 0x10C010120ull;
+
+static const uint64_t P9N2_EX_6_CME_LCL_DBG_PPE1 = 0x10C010138ull;
+
+static const uint64_t P9N2_EX_6_CME_LCL_DBG_PPE2 = 0x10C010130ull;
+
+static const uint64_t P9N2_EX_7_CME_LCL_DBG_PPE = 0x10C020120ull;
+
+static const uint64_t P9N2_EX_7_CME_LCL_DBG_PPE1 = 0x10C020138ull;
+
+static const uint64_t P9N2_EX_7_CME_LCL_DBG_PPE2 = 0x10C020130ull;
+
+static const uint64_t P9N2_EX_8_CME_LCL_DBG_PPE = 0x10D010120ull;
+
+static const uint64_t P9N2_EX_8_CME_LCL_DBG_PPE1 = 0x10D010138ull;
+
+static const uint64_t P9N2_EX_8_CME_LCL_DBG_PPE2 = 0x10D010130ull;
+
+static const uint64_t P9N2_EX_9_CME_LCL_DBG_PPE = 0x10D020120ull;
+
+static const uint64_t P9N2_EX_9_CME_LCL_DBG_PPE1 = 0x10D020138ull;
+
+static const uint64_t P9N2_EX_9_CME_LCL_DBG_PPE2 = 0x10D020130ull;
+
+static const uint64_t P9N2_EX_10_CME_LCL_DBG_PPE = 0x10E010120ull;
+
+static const uint64_t P9N2_EX_10_CME_LCL_DBG_PPE1 = 0x10E010138ull;
+
+static const uint64_t P9N2_EX_10_CME_LCL_DBG_PPE2 = 0x10E010130ull;
+
+static const uint64_t P9N2_EX_11_CME_LCL_DBG_PPE = 0x10E020120ull;
+
+static const uint64_t P9N2_EX_11_CME_LCL_DBG_PPE1 = 0x10E020138ull;
+
+static const uint64_t P9N2_EX_11_CME_LCL_DBG_PPE2 = 0x10E020130ull;
+
+
+static const uint64_t P9N2_EQ_CME_LCL_EIMR = 0x10012026ull;
+//DUPS: 10012026,
+static const uint64_t P9N2_EQ_0_CME_LCL_EIMR = 0x10012026ull;
+//DUPS: 10012026,
+static const uint64_t P9N2_EQ_1_CME_LCL_EIMR = 0x11012026ull;
+//DUPS: 11012026,
+static const uint64_t P9N2_EQ_2_CME_LCL_EIMR = 0x12012026ull;
+//DUPS: 12012026,
+static const uint64_t P9N2_EQ_3_CME_LCL_EIMR = 0x13012026ull;
+//DUPS: 13012026,
+static const uint64_t P9N2_EQ_4_CME_LCL_EIMR = 0x14012026ull;
+//DUPS: 14012026,
+static const uint64_t P9N2_EQ_5_CME_LCL_EIMR = 0x15012026ull;
+//DUPS: 15012026,
+static const uint64_t P9N2_EX_CME_LCL_EIMR_PPE = 0x109010020ull;
+
+static const uint64_t P9N2_EX_CME_LCL_EIMR_PPE1 = 0x109010038ull;
+
+static const uint64_t P9N2_EX_CME_LCL_EIMR_PPE2 = 0x109010030ull;
+
+static const uint64_t P9N2_EX_CME_LCL_EIMR_SCOM = 0x10012026ull;
+
+static const uint64_t P9N2_EX_0_CME_LCL_EIMR_PPE = 0x109010020ull;
+
+static const uint64_t P9N2_EX_0_CME_LCL_EIMR_PPE1 = 0x109010038ull;
+
+static const uint64_t P9N2_EX_0_CME_LCL_EIMR_PPE2 = 0x109010030ull;
+
+static const uint64_t P9N2_EX_0_CME_LCL_EIMR_SCOM = 0x10012026ull;
+
+static const uint64_t P9N2_EX_1_CME_LCL_EIMR_PPE = 0x109020020ull;
+
+static const uint64_t P9N2_EX_1_CME_LCL_EIMR_PPE1 = 0x109020038ull;
+
+static const uint64_t P9N2_EX_1_CME_LCL_EIMR_PPE2 = 0x109020030ull;
+
+static const uint64_t P9N2_EX_1_CME_LCL_EIMR_SCOM = 0x10012426ull;
+
+static const uint64_t P9N2_EX_2_CME_LCL_EIMR_PPE = 0x10A010020ull;
+
+static const uint64_t P9N2_EX_2_CME_LCL_EIMR_PPE1 = 0x10A010038ull;
+
+static const uint64_t P9N2_EX_2_CME_LCL_EIMR_PPE2 = 0x10A010030ull;
+
+static const uint64_t P9N2_EX_2_CME_LCL_EIMR_SCOM = 0x11012026ull;
+
+static const uint64_t P9N2_EX_3_CME_LCL_EIMR_PPE = 0x10A020020ull;
+
+static const uint64_t P9N2_EX_3_CME_LCL_EIMR_PPE1 = 0x10A020038ull;
+
+static const uint64_t P9N2_EX_3_CME_LCL_EIMR_PPE2 = 0x10A020030ull;
+
+static const uint64_t P9N2_EX_3_CME_LCL_EIMR_SCOM = 0x11012426ull;
+
+static const uint64_t P9N2_EX_4_CME_LCL_EIMR_PPE = 0x10B010020ull;
+
+static const uint64_t P9N2_EX_4_CME_LCL_EIMR_PPE1 = 0x10B010038ull;
+
+static const uint64_t P9N2_EX_4_CME_LCL_EIMR_PPE2 = 0x10B010030ull;
+
+static const uint64_t P9N2_EX_4_CME_LCL_EIMR_SCOM = 0x12012026ull;
+
+static const uint64_t P9N2_EX_5_CME_LCL_EIMR_PPE = 0x10B020020ull;
+
+static const uint64_t P9N2_EX_5_CME_LCL_EIMR_PPE1 = 0x10B020038ull;
+
+static const uint64_t P9N2_EX_5_CME_LCL_EIMR_PPE2 = 0x10B020030ull;
+
+static const uint64_t P9N2_EX_5_CME_LCL_EIMR_SCOM = 0x12012426ull;
+
+static const uint64_t P9N2_EX_6_CME_LCL_EIMR_PPE = 0x10C010020ull;
+
+static const uint64_t P9N2_EX_6_CME_LCL_EIMR_PPE1 = 0x10C010038ull;
+
+static const uint64_t P9N2_EX_6_CME_LCL_EIMR_PPE2 = 0x10C010030ull;
+
+static const uint64_t P9N2_EX_6_CME_LCL_EIMR_SCOM = 0x13012026ull;
+
+static const uint64_t P9N2_EX_7_CME_LCL_EIMR_PPE = 0x10C020020ull;
+
+static const uint64_t P9N2_EX_7_CME_LCL_EIMR_PPE1 = 0x10C020038ull;
+
+static const uint64_t P9N2_EX_7_CME_LCL_EIMR_PPE2 = 0x10C020030ull;
+
+static const uint64_t P9N2_EX_7_CME_LCL_EIMR_SCOM = 0x13012426ull;
+
+static const uint64_t P9N2_EX_8_CME_LCL_EIMR_PPE = 0x10D010020ull;
+
+static const uint64_t P9N2_EX_8_CME_LCL_EIMR_PPE1 = 0x10D010038ull;
+
+static const uint64_t P9N2_EX_8_CME_LCL_EIMR_PPE2 = 0x10D010030ull;
+
+static const uint64_t P9N2_EX_8_CME_LCL_EIMR_SCOM = 0x14012026ull;
+
+static const uint64_t P9N2_EX_9_CME_LCL_EIMR_PPE = 0x10D020020ull;
+
+static const uint64_t P9N2_EX_9_CME_LCL_EIMR_PPE1 = 0x10D020038ull;
+
+static const uint64_t P9N2_EX_9_CME_LCL_EIMR_PPE2 = 0x10D020030ull;
+
+static const uint64_t P9N2_EX_9_CME_LCL_EIMR_SCOM = 0x14012426ull;
+
+static const uint64_t P9N2_EX_10_CME_LCL_EIMR_PPE = 0x10E010020ull;
+
+static const uint64_t P9N2_EX_10_CME_LCL_EIMR_PPE1 = 0x10E010038ull;
+
+static const uint64_t P9N2_EX_10_CME_LCL_EIMR_PPE2 = 0x10E010030ull;
+
+static const uint64_t P9N2_EX_10_CME_LCL_EIMR_SCOM = 0x15012026ull;
+
+static const uint64_t P9N2_EX_11_CME_LCL_EIMR_PPE = 0x10E020020ull;
+
+static const uint64_t P9N2_EX_11_CME_LCL_EIMR_PPE1 = 0x10E020038ull;
+
+static const uint64_t P9N2_EX_11_CME_LCL_EIMR_PPE2 = 0x10E020030ull;
+
+static const uint64_t P9N2_EX_11_CME_LCL_EIMR_SCOM = 0x15012426ull;
+
+
+static const uint64_t P9N2_EQ_CME_LCL_EINR = 0x1001202Aull;
+//DUPS: 1001202A,
+static const uint64_t P9N2_EQ_0_CME_LCL_EINR = 0x1001202Aull;
+//DUPS: 1001202A,
+static const uint64_t P9N2_EQ_1_CME_LCL_EINR = 0x1101202Aull;
+//DUPS: 1101202A,
+static const uint64_t P9N2_EQ_2_CME_LCL_EINR = 0x1201202Aull;
+//DUPS: 1201202A,
+static const uint64_t P9N2_EQ_3_CME_LCL_EINR = 0x1301202Aull;
+//DUPS: 1301202A,
+static const uint64_t P9N2_EQ_4_CME_LCL_EINR = 0x1401202Aull;
+//DUPS: 1401202A,
+static const uint64_t P9N2_EQ_5_CME_LCL_EINR = 0x1501202Aull;
+//DUPS: 1501202A,
+static const uint64_t P9N2_EX_CME_LCL_EINR_PPE = 0x1090100A0ull;
+
+static const uint64_t P9N2_EX_CME_LCL_EINR_SCOM = 0x1001202Aull;
+
+static const uint64_t P9N2_EX_0_CME_LCL_EINR_PPE = 0x1090100A0ull;
+
+static const uint64_t P9N2_EX_0_CME_LCL_EINR_SCOM = 0x1001202Aull;
+
+static const uint64_t P9N2_EX_1_CME_LCL_EINR_PPE = 0x1090200A0ull;
+
+static const uint64_t P9N2_EX_1_CME_LCL_EINR_SCOM = 0x1001242Aull;
+
+static const uint64_t P9N2_EX_2_CME_LCL_EINR_PPE = 0x10A0100A0ull;
+
+static const uint64_t P9N2_EX_2_CME_LCL_EINR_SCOM = 0x1101202Aull;
+
+static const uint64_t P9N2_EX_3_CME_LCL_EINR_PPE = 0x10A0200A0ull;
+
+static const uint64_t P9N2_EX_3_CME_LCL_EINR_SCOM = 0x1101242Aull;
+
+static const uint64_t P9N2_EX_4_CME_LCL_EINR_PPE = 0x10B0100A0ull;
+
+static const uint64_t P9N2_EX_4_CME_LCL_EINR_SCOM = 0x1201202Aull;
+
+static const uint64_t P9N2_EX_5_CME_LCL_EINR_PPE = 0x10B0200A0ull;
+
+static const uint64_t P9N2_EX_5_CME_LCL_EINR_SCOM = 0x1201242Aull;
+
+static const uint64_t P9N2_EX_6_CME_LCL_EINR_PPE = 0x10C0100A0ull;
+
+static const uint64_t P9N2_EX_6_CME_LCL_EINR_SCOM = 0x1301202Aull;
+
+static const uint64_t P9N2_EX_7_CME_LCL_EINR_PPE = 0x10C0200A0ull;
+
+static const uint64_t P9N2_EX_7_CME_LCL_EINR_SCOM = 0x1301242Aull;
+
+static const uint64_t P9N2_EX_8_CME_LCL_EINR_PPE = 0x10D0100A0ull;
+
+static const uint64_t P9N2_EX_8_CME_LCL_EINR_SCOM = 0x1401202Aull;
+
+static const uint64_t P9N2_EX_9_CME_LCL_EINR_PPE = 0x10D0200A0ull;
+
+static const uint64_t P9N2_EX_9_CME_LCL_EINR_SCOM = 0x1401242Aull;
+
+static const uint64_t P9N2_EX_10_CME_LCL_EINR_PPE = 0x10E0100A0ull;
+
+static const uint64_t P9N2_EX_10_CME_LCL_EINR_SCOM = 0x1501202Aull;
+
+static const uint64_t P9N2_EX_11_CME_LCL_EINR_PPE = 0x10E0200A0ull;
+
+static const uint64_t P9N2_EX_11_CME_LCL_EINR_SCOM = 0x1501242Aull;
+
+
+static const uint64_t P9N2_EQ_CME_LCL_EIPR = 0x10012027ull;
+//DUPS: 10012027,
+static const uint64_t P9N2_EQ_0_CME_LCL_EIPR = 0x10012027ull;
+//DUPS: 10012027,
+static const uint64_t P9N2_EQ_1_CME_LCL_EIPR = 0x11012027ull;
+//DUPS: 11012027,
+static const uint64_t P9N2_EQ_2_CME_LCL_EIPR = 0x12012027ull;
+//DUPS: 12012027,
+static const uint64_t P9N2_EQ_3_CME_LCL_EIPR = 0x13012027ull;
+//DUPS: 13012027,
+static const uint64_t P9N2_EQ_4_CME_LCL_EIPR = 0x14012027ull;
+//DUPS: 14012027,
+static const uint64_t P9N2_EQ_5_CME_LCL_EIPR = 0x15012027ull;
+//DUPS: 15012027,
+static const uint64_t P9N2_EX_CME_LCL_EIPR_PPE = 0x109010040ull;
+
+static const uint64_t P9N2_EX_CME_LCL_EIPR_PPE1 = 0x109010058ull;
+
+static const uint64_t P9N2_EX_CME_LCL_EIPR_PPE2 = 0x109010050ull;
+
+static const uint64_t P9N2_EX_CME_LCL_EIPR_SCOM = 0x10012027ull;
+
+static const uint64_t P9N2_EX_0_CME_LCL_EIPR_PPE = 0x109010040ull;
+
+static const uint64_t P9N2_EX_0_CME_LCL_EIPR_PPE1 = 0x109010058ull;
+
+static const uint64_t P9N2_EX_0_CME_LCL_EIPR_PPE2 = 0x109010050ull;
+
+static const uint64_t P9N2_EX_0_CME_LCL_EIPR_SCOM = 0x10012027ull;
+
+static const uint64_t P9N2_EX_1_CME_LCL_EIPR_PPE = 0x109020040ull;
+
+static const uint64_t P9N2_EX_1_CME_LCL_EIPR_PPE1 = 0x109020058ull;
+
+static const uint64_t P9N2_EX_1_CME_LCL_EIPR_PPE2 = 0x109020050ull;
+
+static const uint64_t P9N2_EX_1_CME_LCL_EIPR_SCOM = 0x10012427ull;
+
+static const uint64_t P9N2_EX_2_CME_LCL_EIPR_PPE = 0x10A010040ull;
+
+static const uint64_t P9N2_EX_2_CME_LCL_EIPR_PPE1 = 0x10A010058ull;
+
+static const uint64_t P9N2_EX_2_CME_LCL_EIPR_PPE2 = 0x10A010050ull;
+
+static const uint64_t P9N2_EX_2_CME_LCL_EIPR_SCOM = 0x11012027ull;
+
+static const uint64_t P9N2_EX_3_CME_LCL_EIPR_PPE = 0x10A020040ull;
+
+static const uint64_t P9N2_EX_3_CME_LCL_EIPR_PPE1 = 0x10A020058ull;
+
+static const uint64_t P9N2_EX_3_CME_LCL_EIPR_PPE2 = 0x10A020050ull;
+
+static const uint64_t P9N2_EX_3_CME_LCL_EIPR_SCOM = 0x11012427ull;
+
+static const uint64_t P9N2_EX_4_CME_LCL_EIPR_PPE = 0x10B010040ull;
+
+static const uint64_t P9N2_EX_4_CME_LCL_EIPR_PPE1 = 0x10B010058ull;
+
+static const uint64_t P9N2_EX_4_CME_LCL_EIPR_PPE2 = 0x10B010050ull;
+
+static const uint64_t P9N2_EX_4_CME_LCL_EIPR_SCOM = 0x12012027ull;
+
+static const uint64_t P9N2_EX_5_CME_LCL_EIPR_PPE = 0x10B020040ull;
+
+static const uint64_t P9N2_EX_5_CME_LCL_EIPR_PPE1 = 0x10B020058ull;
+
+static const uint64_t P9N2_EX_5_CME_LCL_EIPR_PPE2 = 0x10B020050ull;
+
+static const uint64_t P9N2_EX_5_CME_LCL_EIPR_SCOM = 0x12012427ull;
+
+static const uint64_t P9N2_EX_6_CME_LCL_EIPR_PPE = 0x10C010040ull;
+
+static const uint64_t P9N2_EX_6_CME_LCL_EIPR_PPE1 = 0x10C010058ull;
+
+static const uint64_t P9N2_EX_6_CME_LCL_EIPR_PPE2 = 0x10C010050ull;
+
+static const uint64_t P9N2_EX_6_CME_LCL_EIPR_SCOM = 0x13012027ull;
+
+static const uint64_t P9N2_EX_7_CME_LCL_EIPR_PPE = 0x10C020040ull;
+
+static const uint64_t P9N2_EX_7_CME_LCL_EIPR_PPE1 = 0x10C020058ull;
+
+static const uint64_t P9N2_EX_7_CME_LCL_EIPR_PPE2 = 0x10C020050ull;
+
+static const uint64_t P9N2_EX_7_CME_LCL_EIPR_SCOM = 0x13012427ull;
+
+static const uint64_t P9N2_EX_8_CME_LCL_EIPR_PPE = 0x10D010040ull;
+
+static const uint64_t P9N2_EX_8_CME_LCL_EIPR_PPE1 = 0x10D010058ull;
+
+static const uint64_t P9N2_EX_8_CME_LCL_EIPR_PPE2 = 0x10D010050ull;
+
+static const uint64_t P9N2_EX_8_CME_LCL_EIPR_SCOM = 0x14012027ull;
+
+static const uint64_t P9N2_EX_9_CME_LCL_EIPR_PPE = 0x10D020040ull;
+
+static const uint64_t P9N2_EX_9_CME_LCL_EIPR_PPE1 = 0x10D020058ull;
+
+static const uint64_t P9N2_EX_9_CME_LCL_EIPR_PPE2 = 0x10D020050ull;
+
+static const uint64_t P9N2_EX_9_CME_LCL_EIPR_SCOM = 0x14012427ull;
+
+static const uint64_t P9N2_EX_10_CME_LCL_EIPR_PPE = 0x10E010040ull;
+
+static const uint64_t P9N2_EX_10_CME_LCL_EIPR_PPE1 = 0x10E010058ull;
+
+static const uint64_t P9N2_EX_10_CME_LCL_EIPR_PPE2 = 0x10E010050ull;
+
+static const uint64_t P9N2_EX_10_CME_LCL_EIPR_SCOM = 0x15012027ull;
+
+static const uint64_t P9N2_EX_11_CME_LCL_EIPR_PPE = 0x10E020040ull;
+
+static const uint64_t P9N2_EX_11_CME_LCL_EIPR_PPE1 = 0x10E020058ull;
+
+static const uint64_t P9N2_EX_11_CME_LCL_EIPR_PPE2 = 0x10E020050ull;
+
+static const uint64_t P9N2_EX_11_CME_LCL_EIPR_SCOM = 0x15012427ull;
+
+
+static const uint64_t P9N2_EQ_CME_LCL_EISR = 0x10012025ull;
+//DUPS: 10012025,
+static const uint64_t P9N2_EQ_0_CME_LCL_EISR = 0x10012025ull;
+//DUPS: 10012025,
+static const uint64_t P9N2_EQ_1_CME_LCL_EISR = 0x11012025ull;
+//DUPS: 11012025,
+static const uint64_t P9N2_EQ_2_CME_LCL_EISR = 0x12012025ull;
+//DUPS: 12012025,
+static const uint64_t P9N2_EQ_3_CME_LCL_EISR = 0x13012025ull;
+//DUPS: 13012025,
+static const uint64_t P9N2_EQ_4_CME_LCL_EISR = 0x14012025ull;
+//DUPS: 14012025,
+static const uint64_t P9N2_EQ_5_CME_LCL_EISR = 0x15012025ull;
+//DUPS: 15012025,
+static const uint64_t P9N2_EX_CME_LCL_EISR_PPE = 0x109010000ull;
+
+static const uint64_t P9N2_EX_CME_LCL_EISR_PPE1 = 0x109010018ull;
+
+static const uint64_t P9N2_EX_CME_LCL_EISR_PPE2 = 0x109010010ull;
+
+static const uint64_t P9N2_EX_CME_LCL_EISR_SCOM = 0x10012025ull;
+
+static const uint64_t P9N2_EX_0_CME_LCL_EISR_PPE = 0x109010000ull;
+
+static const uint64_t P9N2_EX_0_CME_LCL_EISR_PPE1 = 0x109010018ull;
+
+static const uint64_t P9N2_EX_0_CME_LCL_EISR_PPE2 = 0x109010010ull;
+
+static const uint64_t P9N2_EX_0_CME_LCL_EISR_SCOM = 0x10012025ull;
+
+static const uint64_t P9N2_EX_1_CME_LCL_EISR_PPE = 0x109020000ull;
+
+static const uint64_t P9N2_EX_1_CME_LCL_EISR_PPE1 = 0x109020018ull;
+
+static const uint64_t P9N2_EX_1_CME_LCL_EISR_PPE2 = 0x109020010ull;
+
+static const uint64_t P9N2_EX_1_CME_LCL_EISR_SCOM = 0x10012425ull;
+
+static const uint64_t P9N2_EX_2_CME_LCL_EISR_PPE = 0x10A010000ull;
+
+static const uint64_t P9N2_EX_2_CME_LCL_EISR_PPE1 = 0x10A010018ull;
+
+static const uint64_t P9N2_EX_2_CME_LCL_EISR_PPE2 = 0x10A010010ull;
+
+static const uint64_t P9N2_EX_2_CME_LCL_EISR_SCOM = 0x11012025ull;
+
+static const uint64_t P9N2_EX_3_CME_LCL_EISR_PPE = 0x10A020000ull;
+
+static const uint64_t P9N2_EX_3_CME_LCL_EISR_PPE1 = 0x10A020018ull;
+
+static const uint64_t P9N2_EX_3_CME_LCL_EISR_PPE2 = 0x10A020010ull;
+
+static const uint64_t P9N2_EX_3_CME_LCL_EISR_SCOM = 0x11012425ull;
+
+static const uint64_t P9N2_EX_4_CME_LCL_EISR_PPE = 0x10B010000ull;
+
+static const uint64_t P9N2_EX_4_CME_LCL_EISR_PPE1 = 0x10B010018ull;
+
+static const uint64_t P9N2_EX_4_CME_LCL_EISR_PPE2 = 0x10B010010ull;
+
+static const uint64_t P9N2_EX_4_CME_LCL_EISR_SCOM = 0x12012025ull;
+
+static const uint64_t P9N2_EX_5_CME_LCL_EISR_PPE = 0x10B020000ull;
+
+static const uint64_t P9N2_EX_5_CME_LCL_EISR_PPE1 = 0x10B020018ull;
+
+static const uint64_t P9N2_EX_5_CME_LCL_EISR_PPE2 = 0x10B020010ull;
+
+static const uint64_t P9N2_EX_5_CME_LCL_EISR_SCOM = 0x12012425ull;
+
+static const uint64_t P9N2_EX_6_CME_LCL_EISR_PPE = 0x10C010000ull;
+
+static const uint64_t P9N2_EX_6_CME_LCL_EISR_PPE1 = 0x10C010018ull;
+
+static const uint64_t P9N2_EX_6_CME_LCL_EISR_PPE2 = 0x10C010010ull;
+
+static const uint64_t P9N2_EX_6_CME_LCL_EISR_SCOM = 0x13012025ull;
+
+static const uint64_t P9N2_EX_7_CME_LCL_EISR_PPE = 0x10C020000ull;
+
+static const uint64_t P9N2_EX_7_CME_LCL_EISR_PPE1 = 0x10C020018ull;
+
+static const uint64_t P9N2_EX_7_CME_LCL_EISR_PPE2 = 0x10C020010ull;
+
+static const uint64_t P9N2_EX_7_CME_LCL_EISR_SCOM = 0x13012425ull;
+
+static const uint64_t P9N2_EX_8_CME_LCL_EISR_PPE = 0x10D010000ull;
+
+static const uint64_t P9N2_EX_8_CME_LCL_EISR_PPE1 = 0x10D010018ull;
+
+static const uint64_t P9N2_EX_8_CME_LCL_EISR_PPE2 = 0x10D010010ull;
+
+static const uint64_t P9N2_EX_8_CME_LCL_EISR_SCOM = 0x14012025ull;
+
+static const uint64_t P9N2_EX_9_CME_LCL_EISR_PPE = 0x10D020000ull;
+
+static const uint64_t P9N2_EX_9_CME_LCL_EISR_PPE1 = 0x10D020018ull;
+
+static const uint64_t P9N2_EX_9_CME_LCL_EISR_PPE2 = 0x10D020010ull;
+
+static const uint64_t P9N2_EX_9_CME_LCL_EISR_SCOM = 0x14012425ull;
+
+static const uint64_t P9N2_EX_10_CME_LCL_EISR_PPE = 0x10E010000ull;
+
+static const uint64_t P9N2_EX_10_CME_LCL_EISR_PPE1 = 0x10E010018ull;
+
+static const uint64_t P9N2_EX_10_CME_LCL_EISR_PPE2 = 0x10E010010ull;
+
+static const uint64_t P9N2_EX_10_CME_LCL_EISR_SCOM = 0x15012025ull;
+
+static const uint64_t P9N2_EX_11_CME_LCL_EISR_PPE = 0x10E020000ull;
+
+static const uint64_t P9N2_EX_11_CME_LCL_EISR_PPE1 = 0x10E020018ull;
+
+static const uint64_t P9N2_EX_11_CME_LCL_EISR_PPE2 = 0x10E020010ull;
+
+static const uint64_t P9N2_EX_11_CME_LCL_EISR_SCOM = 0x15012425ull;
+
+
+static const uint64_t P9N2_EQ_CME_LCL_EISTR = 0x10012029ull;
+//DUPS: 10012029,
+static const uint64_t P9N2_EQ_0_CME_LCL_EISTR = 0x10012029ull;
+//DUPS: 10012029,
+static const uint64_t P9N2_EQ_1_CME_LCL_EISTR = 0x11012029ull;
+//DUPS: 11012029,
+static const uint64_t P9N2_EQ_2_CME_LCL_EISTR = 0x12012029ull;
+//DUPS: 12012029,
+static const uint64_t P9N2_EQ_3_CME_LCL_EISTR = 0x13012029ull;
+//DUPS: 13012029,
+static const uint64_t P9N2_EQ_4_CME_LCL_EISTR = 0x14012029ull;
+//DUPS: 14012029,
+static const uint64_t P9N2_EQ_5_CME_LCL_EISTR = 0x15012029ull;
+//DUPS: 15012029,
+static const uint64_t P9N2_EX_CME_LCL_EISTR_PPE = 0x109010080ull;
+
+static const uint64_t P9N2_EX_CME_LCL_EISTR_SCOM = 0x10012029ull;
+
+static const uint64_t P9N2_EX_0_CME_LCL_EISTR_PPE = 0x109010080ull;
+
+static const uint64_t P9N2_EX_0_CME_LCL_EISTR_SCOM = 0x10012029ull;
+
+static const uint64_t P9N2_EX_1_CME_LCL_EISTR_PPE = 0x109020080ull;
+
+static const uint64_t P9N2_EX_1_CME_LCL_EISTR_SCOM = 0x10012429ull;
+
+static const uint64_t P9N2_EX_2_CME_LCL_EISTR_PPE = 0x10A010080ull;
+
+static const uint64_t P9N2_EX_2_CME_LCL_EISTR_SCOM = 0x11012029ull;
+
+static const uint64_t P9N2_EX_3_CME_LCL_EISTR_PPE = 0x10A020080ull;
+
+static const uint64_t P9N2_EX_3_CME_LCL_EISTR_SCOM = 0x11012429ull;
+
+static const uint64_t P9N2_EX_4_CME_LCL_EISTR_PPE = 0x10B010080ull;
+
+static const uint64_t P9N2_EX_4_CME_LCL_EISTR_SCOM = 0x12012029ull;
+
+static const uint64_t P9N2_EX_5_CME_LCL_EISTR_PPE = 0x10B020080ull;
+
+static const uint64_t P9N2_EX_5_CME_LCL_EISTR_SCOM = 0x12012429ull;
+
+static const uint64_t P9N2_EX_6_CME_LCL_EISTR_PPE = 0x10C010080ull;
+
+static const uint64_t P9N2_EX_6_CME_LCL_EISTR_SCOM = 0x13012029ull;
+
+static const uint64_t P9N2_EX_7_CME_LCL_EISTR_PPE = 0x10C020080ull;
+
+static const uint64_t P9N2_EX_7_CME_LCL_EISTR_SCOM = 0x13012429ull;
+
+static const uint64_t P9N2_EX_8_CME_LCL_EISTR_PPE = 0x10D010080ull;
+
+static const uint64_t P9N2_EX_8_CME_LCL_EISTR_SCOM = 0x14012029ull;
+
+static const uint64_t P9N2_EX_9_CME_LCL_EISTR_PPE = 0x10D020080ull;
+
+static const uint64_t P9N2_EX_9_CME_LCL_EISTR_SCOM = 0x14012429ull;
+
+static const uint64_t P9N2_EX_10_CME_LCL_EISTR_PPE = 0x10E010080ull;
+
+static const uint64_t P9N2_EX_10_CME_LCL_EISTR_SCOM = 0x15012029ull;
+
+static const uint64_t P9N2_EX_11_CME_LCL_EISTR_PPE = 0x10E020080ull;
+
+static const uint64_t P9N2_EX_11_CME_LCL_EISTR_SCOM = 0x15012429ull;
+
+
+static const uint64_t P9N2_EQ_CME_LCL_EITR = 0x10012028ull;
+//DUPS: 10012028,
+static const uint64_t P9N2_EQ_0_CME_LCL_EITR = 0x10012028ull;
+//DUPS: 10012028,
+static const uint64_t P9N2_EQ_1_CME_LCL_EITR = 0x11012028ull;
+//DUPS: 11012028,
+static const uint64_t P9N2_EQ_2_CME_LCL_EITR = 0x12012028ull;
+//DUPS: 12012028,
+static const uint64_t P9N2_EQ_3_CME_LCL_EITR = 0x13012028ull;
+//DUPS: 13012028,
+static const uint64_t P9N2_EQ_4_CME_LCL_EITR = 0x14012028ull;
+//DUPS: 14012028,
+static const uint64_t P9N2_EQ_5_CME_LCL_EITR = 0x15012028ull;
+//DUPS: 15012028,
+static const uint64_t P9N2_EX_CME_LCL_EITR_PPE = 0x109010060ull;
+
+static const uint64_t P9N2_EX_CME_LCL_EITR_PPE1 = 0x109010078ull;
+
+static const uint64_t P9N2_EX_CME_LCL_EITR_PPE2 = 0x109010070ull;
+
+static const uint64_t P9N2_EX_CME_LCL_EITR_SCOM = 0x10012028ull;
+
+static const uint64_t P9N2_EX_0_CME_LCL_EITR_PPE = 0x109010060ull;
+
+static const uint64_t P9N2_EX_0_CME_LCL_EITR_PPE1 = 0x109010078ull;
+
+static const uint64_t P9N2_EX_0_CME_LCL_EITR_PPE2 = 0x109010070ull;
+
+static const uint64_t P9N2_EX_0_CME_LCL_EITR_SCOM = 0x10012028ull;
+
+static const uint64_t P9N2_EX_1_CME_LCL_EITR_PPE = 0x109020060ull;
+
+static const uint64_t P9N2_EX_1_CME_LCL_EITR_PPE1 = 0x109020078ull;
+
+static const uint64_t P9N2_EX_1_CME_LCL_EITR_PPE2 = 0x109020070ull;
+
+static const uint64_t P9N2_EX_1_CME_LCL_EITR_SCOM = 0x10012428ull;
+
+static const uint64_t P9N2_EX_2_CME_LCL_EITR_PPE = 0x10A010060ull;
+
+static const uint64_t P9N2_EX_2_CME_LCL_EITR_PPE1 = 0x10A010078ull;
+
+static const uint64_t P9N2_EX_2_CME_LCL_EITR_PPE2 = 0x10A010070ull;
+
+static const uint64_t P9N2_EX_2_CME_LCL_EITR_SCOM = 0x11012028ull;
+
+static const uint64_t P9N2_EX_3_CME_LCL_EITR_PPE = 0x10A020060ull;
+
+static const uint64_t P9N2_EX_3_CME_LCL_EITR_PPE1 = 0x10A020078ull;
+
+static const uint64_t P9N2_EX_3_CME_LCL_EITR_PPE2 = 0x10A020070ull;
+
+static const uint64_t P9N2_EX_3_CME_LCL_EITR_SCOM = 0x11012428ull;
+
+static const uint64_t P9N2_EX_4_CME_LCL_EITR_PPE = 0x10B010060ull;
+
+static const uint64_t P9N2_EX_4_CME_LCL_EITR_PPE1 = 0x10B010078ull;
+
+static const uint64_t P9N2_EX_4_CME_LCL_EITR_PPE2 = 0x10B010070ull;
+
+static const uint64_t P9N2_EX_4_CME_LCL_EITR_SCOM = 0x12012028ull;
+
+static const uint64_t P9N2_EX_5_CME_LCL_EITR_PPE = 0x10B020060ull;
+
+static const uint64_t P9N2_EX_5_CME_LCL_EITR_PPE1 = 0x10B020078ull;
+
+static const uint64_t P9N2_EX_5_CME_LCL_EITR_PPE2 = 0x10B020070ull;
+
+static const uint64_t P9N2_EX_5_CME_LCL_EITR_SCOM = 0x12012428ull;
+
+static const uint64_t P9N2_EX_6_CME_LCL_EITR_PPE = 0x10C010060ull;
+
+static const uint64_t P9N2_EX_6_CME_LCL_EITR_PPE1 = 0x10C010078ull;
+
+static const uint64_t P9N2_EX_6_CME_LCL_EITR_PPE2 = 0x10C010070ull;
+
+static const uint64_t P9N2_EX_6_CME_LCL_EITR_SCOM = 0x13012028ull;
+
+static const uint64_t P9N2_EX_7_CME_LCL_EITR_PPE = 0x10C020060ull;
+
+static const uint64_t P9N2_EX_7_CME_LCL_EITR_PPE1 = 0x10C020078ull;
+
+static const uint64_t P9N2_EX_7_CME_LCL_EITR_PPE2 = 0x10C020070ull;
+
+static const uint64_t P9N2_EX_7_CME_LCL_EITR_SCOM = 0x13012428ull;
+
+static const uint64_t P9N2_EX_8_CME_LCL_EITR_PPE = 0x10D010060ull;
+
+static const uint64_t P9N2_EX_8_CME_LCL_EITR_PPE1 = 0x10D010078ull;
+
+static const uint64_t P9N2_EX_8_CME_LCL_EITR_PPE2 = 0x10D010070ull;
+
+static const uint64_t P9N2_EX_8_CME_LCL_EITR_SCOM = 0x14012028ull;
+
+static const uint64_t P9N2_EX_9_CME_LCL_EITR_PPE = 0x10D020060ull;
+
+static const uint64_t P9N2_EX_9_CME_LCL_EITR_PPE1 = 0x10D020078ull;
+
+static const uint64_t P9N2_EX_9_CME_LCL_EITR_PPE2 = 0x10D020070ull;
+
+static const uint64_t P9N2_EX_9_CME_LCL_EITR_SCOM = 0x14012428ull;
+
+static const uint64_t P9N2_EX_10_CME_LCL_EITR_PPE = 0x10E010060ull;
+
+static const uint64_t P9N2_EX_10_CME_LCL_EITR_PPE1 = 0x10E010078ull;
+
+static const uint64_t P9N2_EX_10_CME_LCL_EITR_PPE2 = 0x10E010070ull;
+
+static const uint64_t P9N2_EX_10_CME_LCL_EITR_SCOM = 0x15012028ull;
+
+static const uint64_t P9N2_EX_11_CME_LCL_EITR_PPE = 0x10E020060ull;
+
+static const uint64_t P9N2_EX_11_CME_LCL_EITR_PPE1 = 0x10E020078ull;
+
+static const uint64_t P9N2_EX_11_CME_LCL_EITR_PPE2 = 0x10E020070ull;
+
+static const uint64_t P9N2_EX_11_CME_LCL_EITR_SCOM = 0x15012428ull;
+
+
+static const uint64_t P9N2_EX_CME_LCL_ICCR_PPE = 0x109010700ull;
+
+static const uint64_t P9N2_EX_CME_LCL_ICCR_PPE1 = 0x109010718ull;
+
+static const uint64_t P9N2_EX_CME_LCL_ICCR_PPE2 = 0x109010710ull;
+
+static const uint64_t P9N2_EX_0_CME_LCL_ICCR_PPE = 0x109010700ull;
+
+static const uint64_t P9N2_EX_0_CME_LCL_ICCR_PPE1 = 0x109010718ull;
+
+static const uint64_t P9N2_EX_0_CME_LCL_ICCR_PPE2 = 0x109010710ull;
+
+static const uint64_t P9N2_EX_1_CME_LCL_ICCR_PPE = 0x109020700ull;
+
+static const uint64_t P9N2_EX_1_CME_LCL_ICCR_PPE1 = 0x109020718ull;
+
+static const uint64_t P9N2_EX_1_CME_LCL_ICCR_PPE2 = 0x109020710ull;
+
+static const uint64_t P9N2_EX_2_CME_LCL_ICCR_PPE = 0x10A010700ull;
+
+static const uint64_t P9N2_EX_2_CME_LCL_ICCR_PPE1 = 0x10A010718ull;
+
+static const uint64_t P9N2_EX_2_CME_LCL_ICCR_PPE2 = 0x10A010710ull;
+
+static const uint64_t P9N2_EX_3_CME_LCL_ICCR_PPE = 0x10A020700ull;
+
+static const uint64_t P9N2_EX_3_CME_LCL_ICCR_PPE1 = 0x10A020718ull;
+
+static const uint64_t P9N2_EX_3_CME_LCL_ICCR_PPE2 = 0x10A020710ull;
+
+static const uint64_t P9N2_EX_4_CME_LCL_ICCR_PPE = 0x10B010700ull;
+
+static const uint64_t P9N2_EX_4_CME_LCL_ICCR_PPE1 = 0x10B010718ull;
+
+static const uint64_t P9N2_EX_4_CME_LCL_ICCR_PPE2 = 0x10B010710ull;
+
+static const uint64_t P9N2_EX_5_CME_LCL_ICCR_PPE = 0x10B020700ull;
+
+static const uint64_t P9N2_EX_5_CME_LCL_ICCR_PPE1 = 0x10B020718ull;
+
+static const uint64_t P9N2_EX_5_CME_LCL_ICCR_PPE2 = 0x10B020710ull;
+
+static const uint64_t P9N2_EX_6_CME_LCL_ICCR_PPE = 0x10C010700ull;
+
+static const uint64_t P9N2_EX_6_CME_LCL_ICCR_PPE1 = 0x10C010718ull;
+
+static const uint64_t P9N2_EX_6_CME_LCL_ICCR_PPE2 = 0x10C010710ull;
+
+static const uint64_t P9N2_EX_7_CME_LCL_ICCR_PPE = 0x10C020700ull;
+
+static const uint64_t P9N2_EX_7_CME_LCL_ICCR_PPE1 = 0x10C020718ull;
+
+static const uint64_t P9N2_EX_7_CME_LCL_ICCR_PPE2 = 0x10C020710ull;
+
+static const uint64_t P9N2_EX_8_CME_LCL_ICCR_PPE = 0x10D010700ull;
+
+static const uint64_t P9N2_EX_8_CME_LCL_ICCR_PPE1 = 0x10D010718ull;
+
+static const uint64_t P9N2_EX_8_CME_LCL_ICCR_PPE2 = 0x10D010710ull;
+
+static const uint64_t P9N2_EX_9_CME_LCL_ICCR_PPE = 0x10D020700ull;
+
+static const uint64_t P9N2_EX_9_CME_LCL_ICCR_PPE1 = 0x10D020718ull;
+
+static const uint64_t P9N2_EX_9_CME_LCL_ICCR_PPE2 = 0x10D020710ull;
+
+static const uint64_t P9N2_EX_10_CME_LCL_ICCR_PPE = 0x10E010700ull;
+
+static const uint64_t P9N2_EX_10_CME_LCL_ICCR_PPE1 = 0x10E010718ull;
+
+static const uint64_t P9N2_EX_10_CME_LCL_ICCR_PPE2 = 0x10E010710ull;
+
+static const uint64_t P9N2_EX_11_CME_LCL_ICCR_PPE = 0x10E020700ull;
+
+static const uint64_t P9N2_EX_11_CME_LCL_ICCR_PPE1 = 0x10E020718ull;
+
+static const uint64_t P9N2_EX_11_CME_LCL_ICCR_PPE2 = 0x10E020710ull;
+
+
+static const uint64_t P9N2_EQ_CME_LCL_ICRR = 0x1001204Dull;
+//DUPS: 1001204D,
+static const uint64_t P9N2_EQ_0_CME_LCL_ICRR = 0x1001204Dull;
+//DUPS: 1001204D,
+static const uint64_t P9N2_EQ_1_CME_LCL_ICRR = 0x1101204Dull;
+//DUPS: 1101204D,
+static const uint64_t P9N2_EQ_2_CME_LCL_ICRR = 0x1201204Dull;
+//DUPS: 1201204D,
+static const uint64_t P9N2_EQ_3_CME_LCL_ICRR = 0x1301204Dull;
+//DUPS: 1301204D,
+static const uint64_t P9N2_EQ_4_CME_LCL_ICRR = 0x1401204Dull;
+//DUPS: 1401204D,
+static const uint64_t P9N2_EQ_5_CME_LCL_ICRR = 0x1501204Dull;
+//DUPS: 1501204D,
+static const uint64_t P9N2_EX_CME_LCL_ICRR_PPE = 0x109010740ull;
+
+static const uint64_t P9N2_EX_CME_LCL_ICRR_SCOM = 0x1001204Dull;
+
+static const uint64_t P9N2_EX_0_CME_LCL_ICRR_PPE = 0x109010740ull;
+
+static const uint64_t P9N2_EX_0_CME_LCL_ICRR_SCOM = 0x1001204Dull;
+
+static const uint64_t P9N2_EX_1_CME_LCL_ICRR_PPE = 0x109020740ull;
+
+static const uint64_t P9N2_EX_1_CME_LCL_ICRR_SCOM = 0x1001244Dull;
+
+static const uint64_t P9N2_EX_2_CME_LCL_ICRR_PPE = 0x10A010740ull;
+
+static const uint64_t P9N2_EX_2_CME_LCL_ICRR_SCOM = 0x1101204Dull;
+
+static const uint64_t P9N2_EX_3_CME_LCL_ICRR_PPE = 0x10A020740ull;
+
+static const uint64_t P9N2_EX_3_CME_LCL_ICRR_SCOM = 0x1101244Dull;
+
+static const uint64_t P9N2_EX_4_CME_LCL_ICRR_PPE = 0x10B010740ull;
+
+static const uint64_t P9N2_EX_4_CME_LCL_ICRR_SCOM = 0x1201204Dull;
+
+static const uint64_t P9N2_EX_5_CME_LCL_ICRR_PPE = 0x10B020740ull;
+
+static const uint64_t P9N2_EX_5_CME_LCL_ICRR_SCOM = 0x1201244Dull;
+
+static const uint64_t P9N2_EX_6_CME_LCL_ICRR_PPE = 0x10C010740ull;
+
+static const uint64_t P9N2_EX_6_CME_LCL_ICRR_SCOM = 0x1301204Dull;
+
+static const uint64_t P9N2_EX_7_CME_LCL_ICRR_PPE = 0x10C020740ull;
+
+static const uint64_t P9N2_EX_7_CME_LCL_ICRR_SCOM = 0x1301244Dull;
+
+static const uint64_t P9N2_EX_8_CME_LCL_ICRR_PPE = 0x10D010740ull;
+
+static const uint64_t P9N2_EX_8_CME_LCL_ICRR_SCOM = 0x1401204Dull;
+
+static const uint64_t P9N2_EX_9_CME_LCL_ICRR_PPE = 0x10D020740ull;
+
+static const uint64_t P9N2_EX_9_CME_LCL_ICRR_SCOM = 0x1401244Dull;
+
+static const uint64_t P9N2_EX_10_CME_LCL_ICRR_PPE = 0x10E010740ull;
+
+static const uint64_t P9N2_EX_10_CME_LCL_ICRR_SCOM = 0x1501204Dull;
+
+static const uint64_t P9N2_EX_11_CME_LCL_ICRR_PPE = 0x10E020740ull;
+
+static const uint64_t P9N2_EX_11_CME_LCL_ICRR_SCOM = 0x1501244Dull;
+
+
+static const uint64_t P9N2_EX_CME_LCL_ICSR_PPE = 0x109010720ull;
+
+static const uint64_t P9N2_EX_0_CME_LCL_ICSR_PPE = 0x109010720ull;
+
+static const uint64_t P9N2_EX_1_CME_LCL_ICSR_PPE = 0x109020720ull;
+
+static const uint64_t P9N2_EX_2_CME_LCL_ICSR_PPE = 0x10A010720ull;
+
+static const uint64_t P9N2_EX_3_CME_LCL_ICSR_PPE = 0x10A020720ull;
+
+static const uint64_t P9N2_EX_4_CME_LCL_ICSR_PPE = 0x10B010720ull;
+
+static const uint64_t P9N2_EX_5_CME_LCL_ICSR_PPE = 0x10B020720ull;
+
+static const uint64_t P9N2_EX_6_CME_LCL_ICSR_PPE = 0x10C010720ull;
+
+static const uint64_t P9N2_EX_7_CME_LCL_ICSR_PPE = 0x10C020720ull;
+
+static const uint64_t P9N2_EX_8_CME_LCL_ICSR_PPE = 0x10D010720ull;
+
+static const uint64_t P9N2_EX_9_CME_LCL_ICSR_PPE = 0x10D020720ull;
+
+static const uint64_t P9N2_EX_10_CME_LCL_ICSR_PPE = 0x10E010720ull;
+
+static const uint64_t P9N2_EX_11_CME_LCL_ICSR_PPE = 0x10E020720ull;
+
+
+static const uint64_t P9N2_EX_CME_LCL_PECESR0_PPE = 0x109010280ull;
+
+static const uint64_t P9N2_EX_0_CME_LCL_PECESR0_PPE = 0x109010280ull;
+
+static const uint64_t P9N2_EX_1_CME_LCL_PECESR0_PPE = 0x109020280ull;
+
+static const uint64_t P9N2_EX_2_CME_LCL_PECESR0_PPE = 0x10A010280ull;
+
+static const uint64_t P9N2_EX_3_CME_LCL_PECESR0_PPE = 0x10A020280ull;
+
+static const uint64_t P9N2_EX_4_CME_LCL_PECESR0_PPE = 0x10B010280ull;
+
+static const uint64_t P9N2_EX_5_CME_LCL_PECESR0_PPE = 0x10B020280ull;
+
+static const uint64_t P9N2_EX_6_CME_LCL_PECESR0_PPE = 0x10C010280ull;
+
+static const uint64_t P9N2_EX_7_CME_LCL_PECESR0_PPE = 0x10C020280ull;
+
+static const uint64_t P9N2_EX_8_CME_LCL_PECESR0_PPE = 0x10D010280ull;
+
+static const uint64_t P9N2_EX_9_CME_LCL_PECESR0_PPE = 0x10D020280ull;
+
+static const uint64_t P9N2_EX_10_CME_LCL_PECESR0_PPE = 0x10E010280ull;
+
+static const uint64_t P9N2_EX_11_CME_LCL_PECESR0_PPE = 0x10E020280ull;
+
+
+static const uint64_t P9N2_EX_CME_LCL_PECESR1_PPE = 0x1090102A0ull;
+
+static const uint64_t P9N2_EX_0_CME_LCL_PECESR1_PPE = 0x1090102A0ull;
+
+static const uint64_t P9N2_EX_1_CME_LCL_PECESR1_PPE = 0x1090202A0ull;
+
+static const uint64_t P9N2_EX_2_CME_LCL_PECESR1_PPE = 0x10A0102A0ull;
+
+static const uint64_t P9N2_EX_3_CME_LCL_PECESR1_PPE = 0x10A0202A0ull;
+
+static const uint64_t P9N2_EX_4_CME_LCL_PECESR1_PPE = 0x10B0102A0ull;
+
+static const uint64_t P9N2_EX_5_CME_LCL_PECESR1_PPE = 0x10B0202A0ull;
+
+static const uint64_t P9N2_EX_6_CME_LCL_PECESR1_PPE = 0x10C0102A0ull;
+
+static const uint64_t P9N2_EX_7_CME_LCL_PECESR1_PPE = 0x10C0202A0ull;
+
+static const uint64_t P9N2_EX_8_CME_LCL_PECESR1_PPE = 0x10D0102A0ull;
+
+static const uint64_t P9N2_EX_9_CME_LCL_PECESR1_PPE = 0x10D0202A0ull;
+
+static const uint64_t P9N2_EX_10_CME_LCL_PECESR1_PPE = 0x10E0102A0ull;
+
+static const uint64_t P9N2_EX_11_CME_LCL_PECESR1_PPE = 0x10E0202A0ull;
+
+
+static const uint64_t P9N2_EQ_CME_LCL_SISR = 0x1001204Cull;
+//DUPS: 1001204C,
+static const uint64_t P9N2_EQ_0_CME_LCL_SISR = 0x1001204Cull;
+//DUPS: 1001204C,
+static const uint64_t P9N2_EQ_1_CME_LCL_SISR = 0x1101204Cull;
+//DUPS: 1101204C,
+static const uint64_t P9N2_EQ_2_CME_LCL_SISR = 0x1201204Cull;
+//DUPS: 1201204C,
+static const uint64_t P9N2_EQ_3_CME_LCL_SISR = 0x1301204Cull;
+//DUPS: 1301204C,
+static const uint64_t P9N2_EQ_4_CME_LCL_SISR = 0x1401204Cull;
+//DUPS: 1401204C,
+static const uint64_t P9N2_EQ_5_CME_LCL_SISR = 0x1501204Cull;
+//DUPS: 1501204C,
+static const uint64_t P9N2_EX_CME_LCL_SISR_PPE = 0x109010520ull;
+
+static const uint64_t P9N2_EX_CME_LCL_SISR_SCOM = 0x1001204Cull;
+
+static const uint64_t P9N2_EX_0_CME_LCL_SISR_PPE = 0x109010520ull;
+
+static const uint64_t P9N2_EX_0_CME_LCL_SISR_SCOM = 0x1001204Cull;
+
+static const uint64_t P9N2_EX_1_CME_LCL_SISR_PPE = 0x109020520ull;
+
+static const uint64_t P9N2_EX_1_CME_LCL_SISR_SCOM = 0x1001244Cull;
+
+static const uint64_t P9N2_EX_2_CME_LCL_SISR_PPE = 0x10A010520ull;
+
+static const uint64_t P9N2_EX_2_CME_LCL_SISR_SCOM = 0x1101204Cull;
+
+static const uint64_t P9N2_EX_3_CME_LCL_SISR_PPE = 0x10A020520ull;
+
+static const uint64_t P9N2_EX_3_CME_LCL_SISR_SCOM = 0x1101244Cull;
+
+static const uint64_t P9N2_EX_4_CME_LCL_SISR_PPE = 0x10B010520ull;
+
+static const uint64_t P9N2_EX_4_CME_LCL_SISR_SCOM = 0x1201204Cull;
+
+static const uint64_t P9N2_EX_5_CME_LCL_SISR_PPE = 0x10B020520ull;
+
+static const uint64_t P9N2_EX_5_CME_LCL_SISR_SCOM = 0x1201244Cull;
+
+static const uint64_t P9N2_EX_6_CME_LCL_SISR_PPE = 0x10C010520ull;
+
+static const uint64_t P9N2_EX_6_CME_LCL_SISR_SCOM = 0x1301204Cull;
+
+static const uint64_t P9N2_EX_7_CME_LCL_SISR_PPE = 0x10C020520ull;
+
+static const uint64_t P9N2_EX_7_CME_LCL_SISR_SCOM = 0x1301244Cull;
+
+static const uint64_t P9N2_EX_8_CME_LCL_SISR_PPE = 0x10D010520ull;
+
+static const uint64_t P9N2_EX_8_CME_LCL_SISR_SCOM = 0x1401204Cull;
+
+static const uint64_t P9N2_EX_9_CME_LCL_SISR_PPE = 0x10D020520ull;
+
+static const uint64_t P9N2_EX_9_CME_LCL_SISR_SCOM = 0x1401244Cull;
+
+static const uint64_t P9N2_EX_10_CME_LCL_SISR_PPE = 0x10E010520ull;
+
+static const uint64_t P9N2_EX_10_CME_LCL_SISR_SCOM = 0x1501204Cull;
+
+static const uint64_t P9N2_EX_11_CME_LCL_SISR_PPE = 0x10E020520ull;
+
+static const uint64_t P9N2_EX_11_CME_LCL_SISR_SCOM = 0x1501244Cull;
+
+
+static const uint64_t P9N2_EX_CME_LCL_TSEL_PPE = 0x109010100ull;
+
+static const uint64_t P9N2_EX_0_CME_LCL_TSEL_PPE = 0x109010100ull;
+
+static const uint64_t P9N2_EX_1_CME_LCL_TSEL_PPE = 0x109020100ull;
+
+static const uint64_t P9N2_EX_2_CME_LCL_TSEL_PPE = 0x10A010100ull;
+
+static const uint64_t P9N2_EX_3_CME_LCL_TSEL_PPE = 0x10A020100ull;
+
+static const uint64_t P9N2_EX_4_CME_LCL_TSEL_PPE = 0x10B010100ull;
+
+static const uint64_t P9N2_EX_5_CME_LCL_TSEL_PPE = 0x10B020100ull;
+
+static const uint64_t P9N2_EX_6_CME_LCL_TSEL_PPE = 0x10C010100ull;
+
+static const uint64_t P9N2_EX_7_CME_LCL_TSEL_PPE = 0x10C020100ull;
+
+static const uint64_t P9N2_EX_8_CME_LCL_TSEL_PPE = 0x10D010100ull;
+
+static const uint64_t P9N2_EX_9_CME_LCL_TSEL_PPE = 0x10D020100ull;
+
+static const uint64_t P9N2_EX_10_CME_LCL_TSEL_PPE = 0x10E010100ull;
+
+static const uint64_t P9N2_EX_11_CME_LCL_TSEL_PPE = 0x10E020100ull;
+
+
+static const uint64_t P9N2_EQ_CME_SCOM_AFSR = 0x10012033ull;
+//DUPS: 10012033,
+static const uint64_t P9N2_EQ_0_CME_SCOM_AFSR = 0x10012033ull;
+//DUPS: 10012033,
+static const uint64_t P9N2_EQ_1_CME_SCOM_AFSR = 0x11012033ull;
+//DUPS: 11012033,
+static const uint64_t P9N2_EQ_2_CME_SCOM_AFSR = 0x12012033ull;
+//DUPS: 12012033,
+static const uint64_t P9N2_EQ_3_CME_SCOM_AFSR = 0x13012033ull;
+//DUPS: 13012033,
+static const uint64_t P9N2_EQ_4_CME_SCOM_AFSR = 0x14012033ull;
+//DUPS: 14012033,
+static const uint64_t P9N2_EQ_5_CME_SCOM_AFSR = 0x15012033ull;
+//DUPS: 15012033,
+static const uint64_t P9N2_EX_CME_SCOM_AFSR_PPE = 0x109010160ull;
+
+static const uint64_t P9N2_EX_CME_SCOM_AFSR_SCOM = 0x10012033ull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_AFSR_PPE = 0x109010160ull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_AFSR_SCOM = 0x10012033ull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_AFSR_PPE = 0x109020160ull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_AFSR_SCOM = 0x10012433ull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_AFSR_PPE = 0x10A010160ull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_AFSR_SCOM = 0x11012033ull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_AFSR_PPE = 0x10A020160ull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_AFSR_SCOM = 0x11012433ull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_AFSR_PPE = 0x10B010160ull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_AFSR_SCOM = 0x12012033ull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_AFSR_PPE = 0x10B020160ull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_AFSR_SCOM = 0x12012433ull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_AFSR_PPE = 0x10C010160ull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_AFSR_SCOM = 0x13012033ull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_AFSR_PPE = 0x10C020160ull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_AFSR_SCOM = 0x13012433ull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_AFSR_PPE = 0x10D010160ull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_AFSR_SCOM = 0x14012033ull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_AFSR_PPE = 0x10D020160ull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_AFSR_SCOM = 0x14012433ull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_AFSR_PPE = 0x10E010160ull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_AFSR_SCOM = 0x15012033ull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_AFSR_PPE = 0x10E020160ull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_AFSR_SCOM = 0x15012433ull;
+
+
+static const uint64_t P9N2_EQ_CME_SCOM_AFTR = 0x10012034ull;
+//DUPS: 10012034,
+static const uint64_t P9N2_EQ_0_CME_SCOM_AFTR = 0x10012034ull;
+//DUPS: 10012034,
+static const uint64_t P9N2_EQ_1_CME_SCOM_AFTR = 0x11012034ull;
+//DUPS: 11012034,
+static const uint64_t P9N2_EQ_2_CME_SCOM_AFTR = 0x12012034ull;
+//DUPS: 12012034,
+static const uint64_t P9N2_EQ_3_CME_SCOM_AFTR = 0x13012034ull;
+//DUPS: 13012034,
+static const uint64_t P9N2_EQ_4_CME_SCOM_AFTR = 0x14012034ull;
+//DUPS: 14012034,
+static const uint64_t P9N2_EQ_5_CME_SCOM_AFTR = 0x15012034ull;
+//DUPS: 15012034,
+static const uint64_t P9N2_EX_CME_SCOM_AFTR_PPE = 0x109010180ull;
+
+static const uint64_t P9N2_EX_CME_SCOM_AFTR_SCOM = 0x10012034ull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_AFTR_PPE = 0x109010180ull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_AFTR_SCOM = 0x10012034ull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_AFTR_PPE = 0x109020180ull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_AFTR_SCOM = 0x10012434ull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_AFTR_PPE = 0x10A010180ull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_AFTR_SCOM = 0x11012034ull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_AFTR_PPE = 0x10A020180ull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_AFTR_SCOM = 0x11012434ull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_AFTR_PPE = 0x10B010180ull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_AFTR_SCOM = 0x12012034ull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_AFTR_PPE = 0x10B020180ull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_AFTR_SCOM = 0x12012434ull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_AFTR_PPE = 0x10C010180ull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_AFTR_SCOM = 0x13012034ull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_AFTR_PPE = 0x10C020180ull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_AFTR_SCOM = 0x13012434ull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_AFTR_PPE = 0x10D010180ull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_AFTR_SCOM = 0x14012034ull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_AFTR_PPE = 0x10D020180ull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_AFTR_SCOM = 0x14012434ull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_AFTR_PPE = 0x10E010180ull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_AFTR_SCOM = 0x15012034ull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_AFTR_PPE = 0x10E020180ull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_AFTR_SCOM = 0x15012434ull;
+
+
+static const uint64_t P9N2_EQ_CME_SCOM_BCEBAR0 = 0x10012030ull;
+//DUPS: 10012030,
+static const uint64_t P9N2_EQ_0_CME_SCOM_BCEBAR0 = 0x10012030ull;
+//DUPS: 10012030,
+static const uint64_t P9N2_EQ_1_CME_SCOM_BCEBAR0 = 0x11012030ull;
+//DUPS: 11012030,
+static const uint64_t P9N2_EQ_2_CME_SCOM_BCEBAR0 = 0x12012030ull;
+//DUPS: 12012030,
+static const uint64_t P9N2_EQ_3_CME_SCOM_BCEBAR0 = 0x13012030ull;
+//DUPS: 13012030,
+static const uint64_t P9N2_EQ_4_CME_SCOM_BCEBAR0 = 0x14012030ull;
+//DUPS: 14012030,
+static const uint64_t P9N2_EQ_5_CME_SCOM_BCEBAR0 = 0x15012030ull;
+//DUPS: 15012030,
+static const uint64_t P9N2_EX_CME_SCOM_BCEBAR0 = 0x10012030ull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_BCEBAR0 = 0x10012030ull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_BCEBAR0 = 0x10012430ull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_BCEBAR0 = 0x11012030ull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_BCEBAR0 = 0x11012430ull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_BCEBAR0 = 0x12012030ull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_BCEBAR0 = 0x12012430ull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_BCEBAR0 = 0x13012030ull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_BCEBAR0 = 0x13012430ull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_BCEBAR0 = 0x14012030ull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_BCEBAR0 = 0x14012430ull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_BCEBAR0 = 0x15012030ull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_BCEBAR0 = 0x15012430ull;
+
+
+static const uint64_t P9N2_EQ_CME_SCOM_BCEBAR1 = 0x10012031ull;
+//DUPS: 10012031,
+static const uint64_t P9N2_EQ_0_CME_SCOM_BCEBAR1 = 0x10012031ull;
+//DUPS: 10012031,
+static const uint64_t P9N2_EQ_1_CME_SCOM_BCEBAR1 = 0x11012031ull;
+//DUPS: 11012031,
+static const uint64_t P9N2_EQ_2_CME_SCOM_BCEBAR1 = 0x12012031ull;
+//DUPS: 12012031,
+static const uint64_t P9N2_EQ_3_CME_SCOM_BCEBAR1 = 0x13012031ull;
+//DUPS: 13012031,
+static const uint64_t P9N2_EQ_4_CME_SCOM_BCEBAR1 = 0x14012031ull;
+//DUPS: 14012031,
+static const uint64_t P9N2_EQ_5_CME_SCOM_BCEBAR1 = 0x15012031ull;
+//DUPS: 15012031,
+static const uint64_t P9N2_EX_CME_SCOM_BCEBAR1 = 0x10012031ull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_BCEBAR1 = 0x10012031ull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_BCEBAR1 = 0x10012431ull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_BCEBAR1 = 0x11012031ull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_BCEBAR1 = 0x11012431ull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_BCEBAR1 = 0x12012031ull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_BCEBAR1 = 0x12012431ull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_BCEBAR1 = 0x13012031ull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_BCEBAR1 = 0x13012431ull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_BCEBAR1 = 0x14012031ull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_BCEBAR1 = 0x14012431ull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_BCEBAR1 = 0x15012031ull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_BCEBAR1 = 0x15012431ull;
+
+
+static const uint64_t P9N2_EQ_CME_SCOM_BCECSR = 0x1001200Full;
+//DUPS: 1001200F,
+static const uint64_t P9N2_EQ_0_CME_SCOM_BCECSR = 0x1001200Full;
+//DUPS: 1001200F,
+static const uint64_t P9N2_EQ_1_CME_SCOM_BCECSR = 0x1101200Full;
+//DUPS: 1101200F,
+static const uint64_t P9N2_EQ_2_CME_SCOM_BCECSR = 0x1201200Full;
+//DUPS: 1201200F,
+static const uint64_t P9N2_EQ_3_CME_SCOM_BCECSR = 0x1301200Full;
+//DUPS: 1301200F,
+static const uint64_t P9N2_EQ_4_CME_SCOM_BCECSR = 0x1401200Full;
+//DUPS: 1401200F,
+static const uint64_t P9N2_EQ_5_CME_SCOM_BCECSR = 0x1501200Full;
+//DUPS: 1501200F,
+static const uint64_t P9N2_EX_CME_SCOM_BCECSR_PPE = 0x1090101E0ull;
+
+static const uint64_t P9N2_EX_CME_SCOM_BCECSR_SCOM = 0x1001200Full;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_BCECSR_PPE = 0x1090101E0ull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_BCECSR_SCOM = 0x1001200Full;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_BCECSR_PPE = 0x1090201E0ull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_BCECSR_SCOM = 0x1001240Full;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_BCECSR_PPE = 0x10A0101E0ull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_BCECSR_SCOM = 0x1101200Full;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_BCECSR_PPE = 0x10A0201E0ull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_BCECSR_SCOM = 0x1101240Full;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_BCECSR_PPE = 0x10B0101E0ull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_BCECSR_SCOM = 0x1201200Full;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_BCECSR_PPE = 0x10B0201E0ull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_BCECSR_SCOM = 0x1201240Full;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_BCECSR_PPE = 0x10C0101E0ull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_BCECSR_SCOM = 0x1301200Full;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_BCECSR_PPE = 0x10C0201E0ull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_BCECSR_SCOM = 0x1301240Full;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_BCECSR_PPE = 0x10D0101E0ull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_BCECSR_SCOM = 0x1401200Full;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_BCECSR_PPE = 0x10D0201E0ull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_BCECSR_SCOM = 0x1401240Full;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_BCECSR_PPE = 0x10E0101E0ull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_BCECSR_SCOM = 0x1501200Full;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_BCECSR_PPE = 0x10E0201E0ull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_BCECSR_SCOM = 0x1501240Full;
+
+
+static const uint64_t P9N2_EQ_CME_SCOM_CIDSR = 0x1001202Eull;
+//DUPS: 1001202E,
+static const uint64_t P9N2_EQ_0_CME_SCOM_CIDSR = 0x1001202Eull;
+//DUPS: 1001202E,
+static const uint64_t P9N2_EQ_1_CME_SCOM_CIDSR = 0x1101202Eull;
+//DUPS: 1101202E,
+static const uint64_t P9N2_EQ_2_CME_SCOM_CIDSR = 0x1201202Eull;
+//DUPS: 1201202E,
+static const uint64_t P9N2_EQ_3_CME_SCOM_CIDSR = 0x1301202Eull;
+//DUPS: 1301202E,
+static const uint64_t P9N2_EQ_4_CME_SCOM_CIDSR = 0x1401202Eull;
+//DUPS: 1401202E,
+static const uint64_t P9N2_EQ_5_CME_SCOM_CIDSR = 0x1501202Eull;
+//DUPS: 1501202E,
+static const uint64_t P9N2_EX_CME_SCOM_CIDSR_PPE = 0x1090106C0ull;
+
+static const uint64_t P9N2_EX_CME_SCOM_CIDSR_SCOM = 0x1001202Eull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_CIDSR_PPE = 0x1090106C0ull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_CIDSR_SCOM = 0x1001202Eull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_CIDSR_PPE = 0x1090206C0ull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_CIDSR_SCOM = 0x1001242Eull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_CIDSR_PPE = 0x10A0106C0ull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_CIDSR_SCOM = 0x1101202Eull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_CIDSR_PPE = 0x10A0206C0ull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_CIDSR_SCOM = 0x1101242Eull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_CIDSR_PPE = 0x10B0106C0ull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_CIDSR_SCOM = 0x1201202Eull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_CIDSR_PPE = 0x10B0206C0ull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_CIDSR_SCOM = 0x1201242Eull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_CIDSR_PPE = 0x10C0106C0ull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_CIDSR_SCOM = 0x1301202Eull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_CIDSR_PPE = 0x10C0206C0ull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_CIDSR_SCOM = 0x1301242Eull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_CIDSR_PPE = 0x10D0106C0ull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_CIDSR_SCOM = 0x1401202Eull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_CIDSR_PPE = 0x10D0206C0ull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_CIDSR_SCOM = 0x1401242Eull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_CIDSR_PPE = 0x10E0106C0ull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_CIDSR_SCOM = 0x1501202Eull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_CIDSR_PPE = 0x10E0206C0ull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_CIDSR_SCOM = 0x1501242Eull;
+
+
+static const uint64_t P9N2_EQ_CME_SCOM_EIIR = 0x1001202Bull;
+//DUPS: 1001202B,
+static const uint64_t P9N2_EQ_0_CME_SCOM_EIIR = 0x1001202Bull;
+//DUPS: 1001202B,
+static const uint64_t P9N2_EQ_1_CME_SCOM_EIIR = 0x1101202Bull;
+//DUPS: 1101202B,
+static const uint64_t P9N2_EQ_2_CME_SCOM_EIIR = 0x1201202Bull;
+//DUPS: 1201202B,
+static const uint64_t P9N2_EQ_3_CME_SCOM_EIIR = 0x1301202Bull;
+//DUPS: 1301202B,
+static const uint64_t P9N2_EQ_4_CME_SCOM_EIIR = 0x1401202Bull;
+//DUPS: 1401202B,
+static const uint64_t P9N2_EQ_5_CME_SCOM_EIIR = 0x1501202Bull;
+//DUPS: 1501202B,
+static const uint64_t P9N2_EX_CME_SCOM_EIIR = 0x1001202Bull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_EIIR = 0x1001202Bull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_EIIR = 0x1001242Bull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_EIIR = 0x1101202Bull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_EIIR = 0x1101242Bull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_EIIR = 0x1201202Bull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_EIIR = 0x1201242Bull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_EIIR = 0x1301202Bull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_EIIR = 0x1301242Bull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_EIIR = 0x1401202Bull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_EIIR = 0x1401242Bull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_EIIR = 0x1501202Bull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_EIIR = 0x1501242Bull;
+
+
+static const uint64_t P9N2_EQ_CME_SCOM_FLAGS = 0x10012020ull;
+//DUPS: 10012020,
+static const uint64_t P9N2_EQ_CME_SCOM_FLAGS_CLEAR = 0x10012021ull;
+//DUPS: 10012021,
+static const uint64_t P9N2_EQ_CME_SCOM_FLAGS_OR = 0x10012022ull;
+//DUPS: 10012022,
+static const uint64_t P9N2_EQ_0_CME_SCOM_FLAGS = 0x10012020ull;
+//DUPS: 10012020,
+static const uint64_t P9N2_EQ_0_CME_SCOM_FLAGS_CLEAR = 0x10012021ull;
+//DUPS: 10012021,
+static const uint64_t P9N2_EQ_0_CME_SCOM_FLAGS_OR = 0x10012022ull;
+//DUPS: 10012022,
+static const uint64_t P9N2_EQ_1_CME_SCOM_FLAGS = 0x11012020ull;
+//DUPS: 11012020,
+static const uint64_t P9N2_EQ_1_CME_SCOM_FLAGS_CLEAR = 0x11012021ull;
+//DUPS: 11012021,
+static const uint64_t P9N2_EQ_1_CME_SCOM_FLAGS_OR = 0x11012022ull;
+//DUPS: 11012022,
+static const uint64_t P9N2_EQ_2_CME_SCOM_FLAGS = 0x12012020ull;
+//DUPS: 12012020,
+static const uint64_t P9N2_EQ_2_CME_SCOM_FLAGS_CLEAR = 0x12012021ull;
+//DUPS: 12012021,
+static const uint64_t P9N2_EQ_2_CME_SCOM_FLAGS_OR = 0x12012022ull;
+//DUPS: 12012022,
+static const uint64_t P9N2_EQ_3_CME_SCOM_FLAGS = 0x13012020ull;
+//DUPS: 13012020,
+static const uint64_t P9N2_EQ_3_CME_SCOM_FLAGS_CLEAR = 0x13012021ull;
+//DUPS: 13012021,
+static const uint64_t P9N2_EQ_3_CME_SCOM_FLAGS_OR = 0x13012022ull;
+//DUPS: 13012022,
+static const uint64_t P9N2_EQ_4_CME_SCOM_FLAGS = 0x14012020ull;
+//DUPS: 14012020,
+static const uint64_t P9N2_EQ_4_CME_SCOM_FLAGS_CLEAR = 0x14012021ull;
+//DUPS: 14012021,
+static const uint64_t P9N2_EQ_4_CME_SCOM_FLAGS_OR = 0x14012022ull;
+//DUPS: 14012022,
+static const uint64_t P9N2_EQ_5_CME_SCOM_FLAGS = 0x15012020ull;
+//DUPS: 15012020,
+static const uint64_t P9N2_EQ_5_CME_SCOM_FLAGS_CLEAR = 0x15012021ull;
+//DUPS: 15012021,
+static const uint64_t P9N2_EQ_5_CME_SCOM_FLAGS_OR = 0x15012022ull;
+//DUPS: 15012022,
+static const uint64_t P9N2_EX_CME_SCOM_FLAGS_PPE = 0x109010400ull;
+
+static const uint64_t P9N2_EX_CME_SCOM_FLAGS_PPE1 = 0x109010418ull;
+
+static const uint64_t P9N2_EX_CME_SCOM_FLAGS_PPE2 = 0x109010410ull;
+
+static const uint64_t P9N2_EX_CME_SCOM_FLAGS_SCOM = 0x10012020ull;
+
+static const uint64_t P9N2_EX_CME_SCOM_FLAGS_SCOM1 = 0x10012021ull;
+
+static const uint64_t P9N2_EX_CME_SCOM_FLAGS_SCOM2 = 0x10012022ull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_FLAGS_PPE = 0x109010400ull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_FLAGS_PPE1 = 0x109010418ull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_FLAGS_PPE2 = 0x109010410ull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_FLAGS_SCOM = 0x10012020ull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_FLAGS_SCOM1 = 0x10012021ull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_FLAGS_SCOM2 = 0x10012022ull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_FLAGS_PPE = 0x109020400ull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_FLAGS_PPE1 = 0x109020418ull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_FLAGS_PPE2 = 0x109020410ull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_FLAGS_SCOM = 0x10012420ull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_FLAGS_SCOM1 = 0x10012421ull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_FLAGS_SCOM2 = 0x10012422ull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_FLAGS_PPE = 0x10A010400ull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_FLAGS_PPE1 = 0x10A010418ull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_FLAGS_PPE2 = 0x10A010410ull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_FLAGS_SCOM = 0x11012020ull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_FLAGS_SCOM1 = 0x11012021ull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_FLAGS_SCOM2 = 0x11012022ull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_FLAGS_PPE = 0x10A020400ull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_FLAGS_PPE1 = 0x10A020418ull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_FLAGS_PPE2 = 0x10A020410ull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_FLAGS_SCOM = 0x11012420ull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_FLAGS_SCOM1 = 0x11012421ull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_FLAGS_SCOM2 = 0x11012422ull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_FLAGS_PPE = 0x10B010400ull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_FLAGS_PPE1 = 0x10B010418ull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_FLAGS_PPE2 = 0x10B010410ull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_FLAGS_SCOM = 0x12012020ull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_FLAGS_SCOM1 = 0x12012021ull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_FLAGS_SCOM2 = 0x12012022ull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_FLAGS_PPE = 0x10B020400ull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_FLAGS_PPE1 = 0x10B020418ull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_FLAGS_PPE2 = 0x10B020410ull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_FLAGS_SCOM = 0x12012420ull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_FLAGS_SCOM1 = 0x12012421ull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_FLAGS_SCOM2 = 0x12012422ull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_FLAGS_PPE = 0x10C010400ull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_FLAGS_PPE1 = 0x10C010418ull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_FLAGS_PPE2 = 0x10C010410ull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_FLAGS_SCOM = 0x13012020ull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_FLAGS_SCOM1 = 0x13012021ull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_FLAGS_SCOM2 = 0x13012022ull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_FLAGS_PPE = 0x10C020400ull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_FLAGS_PPE1 = 0x10C020418ull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_FLAGS_PPE2 = 0x10C020410ull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_FLAGS_SCOM = 0x13012420ull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_FLAGS_SCOM1 = 0x13012421ull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_FLAGS_SCOM2 = 0x13012422ull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_FLAGS_PPE = 0x10D010400ull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_FLAGS_PPE1 = 0x10D010418ull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_FLAGS_PPE2 = 0x10D010410ull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_FLAGS_SCOM = 0x14012020ull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_FLAGS_SCOM1 = 0x14012021ull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_FLAGS_SCOM2 = 0x14012022ull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_FLAGS_PPE = 0x10D020400ull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_FLAGS_PPE1 = 0x10D020418ull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_FLAGS_PPE2 = 0x10D020410ull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_FLAGS_SCOM = 0x14012420ull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_FLAGS_SCOM1 = 0x14012421ull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_FLAGS_SCOM2 = 0x14012422ull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_FLAGS_PPE = 0x10E010400ull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_FLAGS_PPE1 = 0x10E010418ull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_FLAGS_PPE2 = 0x10E010410ull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_FLAGS_SCOM = 0x15012020ull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_FLAGS_SCOM1 = 0x15012021ull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_FLAGS_SCOM2 = 0x15012022ull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_FLAGS_PPE = 0x10E020400ull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_FLAGS_PPE1 = 0x10E020418ull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_FLAGS_PPE2 = 0x10E020410ull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_FLAGS_SCOM = 0x15012420ull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_FLAGS_SCOM1 = 0x15012421ull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_FLAGS_SCOM2 = 0x15012422ull;
+
+
+static const uint64_t P9N2_EQ_CME_SCOM_IDCR = 0x1001202Dull;
+//DUPS: 1001202D,
+static const uint64_t P9N2_EQ_0_CME_SCOM_IDCR = 0x1001202Dull;
+//DUPS: 1001202D,
+static const uint64_t P9N2_EQ_1_CME_SCOM_IDCR = 0x1101202Dull;
+//DUPS: 1101202D,
+static const uint64_t P9N2_EQ_2_CME_SCOM_IDCR = 0x1201202Dull;
+//DUPS: 1201202D,
+static const uint64_t P9N2_EQ_3_CME_SCOM_IDCR = 0x1301202Dull;
+//DUPS: 1301202D,
+static const uint64_t P9N2_EQ_4_CME_SCOM_IDCR = 0x1401202Dull;
+//DUPS: 1401202D,
+static const uint64_t P9N2_EQ_5_CME_SCOM_IDCR = 0x1501202Dull;
+//DUPS: 1501202D,
+static const uint64_t P9N2_EX_CME_SCOM_IDCR_PPE = 0x1090106A0ull;
+
+static const uint64_t P9N2_EX_CME_SCOM_IDCR_SCOM = 0x1001202Dull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_IDCR_PPE = 0x1090106A0ull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_IDCR_SCOM = 0x1001202Dull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_IDCR_PPE = 0x1090206A0ull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_IDCR_SCOM = 0x1001242Dull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_IDCR_PPE = 0x10A0106A0ull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_IDCR_SCOM = 0x1101202Dull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_IDCR_PPE = 0x10A0206A0ull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_IDCR_SCOM = 0x1101242Dull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_IDCR_PPE = 0x10B0106A0ull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_IDCR_SCOM = 0x1201202Dull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_IDCR_PPE = 0x10B0206A0ull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_IDCR_SCOM = 0x1201242Dull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_IDCR_PPE = 0x10C0106A0ull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_IDCR_SCOM = 0x1301202Dull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_IDCR_PPE = 0x10C0206A0ull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_IDCR_SCOM = 0x1301242Dull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_IDCR_PPE = 0x10D0106A0ull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_IDCR_SCOM = 0x1401202Dull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_IDCR_PPE = 0x10D0206A0ull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_IDCR_SCOM = 0x1401242Dull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_IDCR_PPE = 0x10E0106A0ull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_IDCR_SCOM = 0x1501202Dull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_IDCR_PPE = 0x10E0206A0ull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_IDCR_SCOM = 0x1501242Dull;
+
+
+static const uint64_t P9N2_EQ_CME_SCOM_LFIR = 0x10012000ull;
+//DUPS: 10012000,
+static const uint64_t P9N2_EQ_CME_SCOM_LFIR_AND = 0x10012001ull;
+//DUPS: 10012001,
+static const uint64_t P9N2_EQ_CME_SCOM_LFIR_OR = 0x10012002ull;
+//DUPS: 10012002,
+static const uint64_t P9N2_EQ_0_CME_SCOM_LFIR = 0x10012000ull;
+//DUPS: 10012000,
+static const uint64_t P9N2_EQ_0_CME_SCOM_LFIR_AND = 0x10012001ull;
+//DUPS: 10012001,
+static const uint64_t P9N2_EQ_0_CME_SCOM_LFIR_OR = 0x10012002ull;
+//DUPS: 10012002,
+static const uint64_t P9N2_EQ_1_CME_SCOM_LFIR = 0x11012000ull;
+//DUPS: 11012000,
+static const uint64_t P9N2_EQ_1_CME_SCOM_LFIR_AND = 0x11012001ull;
+//DUPS: 11012001,
+static const uint64_t P9N2_EQ_1_CME_SCOM_LFIR_OR = 0x11012002ull;
+//DUPS: 11012002,
+static const uint64_t P9N2_EQ_2_CME_SCOM_LFIR = 0x12012000ull;
+//DUPS: 12012000,
+static const uint64_t P9N2_EQ_2_CME_SCOM_LFIR_AND = 0x12012001ull;
+//DUPS: 12012001,
+static const uint64_t P9N2_EQ_2_CME_SCOM_LFIR_OR = 0x12012002ull;
+//DUPS: 12012002,
+static const uint64_t P9N2_EQ_3_CME_SCOM_LFIR = 0x13012000ull;
+//DUPS: 13012000,
+static const uint64_t P9N2_EQ_3_CME_SCOM_LFIR_AND = 0x13012001ull;
+//DUPS: 13012001,
+static const uint64_t P9N2_EQ_3_CME_SCOM_LFIR_OR = 0x13012002ull;
+//DUPS: 13012002,
+static const uint64_t P9N2_EQ_4_CME_SCOM_LFIR = 0x14012000ull;
+//DUPS: 14012000,
+static const uint64_t P9N2_EQ_4_CME_SCOM_LFIR_AND = 0x14012001ull;
+//DUPS: 14012001,
+static const uint64_t P9N2_EQ_4_CME_SCOM_LFIR_OR = 0x14012002ull;
+//DUPS: 14012002,
+static const uint64_t P9N2_EQ_5_CME_SCOM_LFIR = 0x15012000ull;
+//DUPS: 15012000,
+static const uint64_t P9N2_EQ_5_CME_SCOM_LFIR_AND = 0x15012001ull;
+//DUPS: 15012001,
+static const uint64_t P9N2_EQ_5_CME_SCOM_LFIR_OR = 0x15012002ull;
+//DUPS: 15012002,
+static const uint64_t P9N2_EX_CME_SCOM_LFIR = 0x10012000ull;
+
+static const uint64_t P9N2_EX_CME_SCOM_LFIR_AND = 0x10012001ull;
+
+static const uint64_t P9N2_EX_CME_SCOM_LFIR_OR = 0x10012002ull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_LFIR = 0x10012000ull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_LFIR_AND = 0x10012001ull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_LFIR_OR = 0x10012002ull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_LFIR = 0x10012400ull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_LFIR_AND = 0x10012401ull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_LFIR_OR = 0x10012402ull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_LFIR = 0x11012000ull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_LFIR_AND = 0x11012001ull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_LFIR_OR = 0x11012002ull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_LFIR = 0x11012400ull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_LFIR_AND = 0x11012401ull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_LFIR_OR = 0x11012402ull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_LFIR = 0x12012000ull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_LFIR_AND = 0x12012001ull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_LFIR_OR = 0x12012002ull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_LFIR = 0x12012400ull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_LFIR_AND = 0x12012401ull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_LFIR_OR = 0x12012402ull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_LFIR = 0x13012000ull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_LFIR_AND = 0x13012001ull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_LFIR_OR = 0x13012002ull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_LFIR = 0x13012400ull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_LFIR_AND = 0x13012401ull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_LFIR_OR = 0x13012402ull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_LFIR = 0x14012000ull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_LFIR_AND = 0x14012001ull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_LFIR_OR = 0x14012002ull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_LFIR = 0x14012400ull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_LFIR_AND = 0x14012401ull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_LFIR_OR = 0x14012402ull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_LFIR = 0x15012000ull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_LFIR_AND = 0x15012001ull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_LFIR_OR = 0x15012002ull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_LFIR = 0x15012400ull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_LFIR_AND = 0x15012401ull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_LFIR_OR = 0x15012402ull;
+
+
+static const uint64_t P9N2_EQ_CME_SCOM_LFIRACT0 = 0x10012006ull;
+//DUPS: 10012006,
+static const uint64_t P9N2_EQ_0_CME_SCOM_LFIRACT0 = 0x10012006ull;
+//DUPS: 10012006,
+static const uint64_t P9N2_EQ_1_CME_SCOM_LFIRACT0 = 0x11012006ull;
+//DUPS: 11012006,
+static const uint64_t P9N2_EQ_2_CME_SCOM_LFIRACT0 = 0x12012006ull;
+//DUPS: 12012006,
+static const uint64_t P9N2_EQ_3_CME_SCOM_LFIRACT0 = 0x13012006ull;
+//DUPS: 13012006,
+static const uint64_t P9N2_EQ_4_CME_SCOM_LFIRACT0 = 0x14012006ull;
+//DUPS: 14012006,
+static const uint64_t P9N2_EQ_5_CME_SCOM_LFIRACT0 = 0x15012006ull;
+//DUPS: 15012006,
+static const uint64_t P9N2_EX_CME_SCOM_LFIRACT0 = 0x10012006ull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_LFIRACT0 = 0x10012006ull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_LFIRACT0 = 0x10012406ull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_LFIRACT0 = 0x11012006ull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_LFIRACT0 = 0x11012406ull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_LFIRACT0 = 0x12012006ull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_LFIRACT0 = 0x12012406ull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_LFIRACT0 = 0x13012006ull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_LFIRACT0 = 0x13012406ull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_LFIRACT0 = 0x14012006ull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_LFIRACT0 = 0x14012406ull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_LFIRACT0 = 0x15012006ull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_LFIRACT0 = 0x15012406ull;
+
+
+static const uint64_t P9N2_EQ_CME_SCOM_LFIRACT1 = 0x10012007ull;
+//DUPS: 10012007,
+static const uint64_t P9N2_EQ_0_CME_SCOM_LFIRACT1 = 0x10012007ull;
+//DUPS: 10012007,
+static const uint64_t P9N2_EQ_1_CME_SCOM_LFIRACT1 = 0x11012007ull;
+//DUPS: 11012007,
+static const uint64_t P9N2_EQ_2_CME_SCOM_LFIRACT1 = 0x12012007ull;
+//DUPS: 12012007,
+static const uint64_t P9N2_EQ_3_CME_SCOM_LFIRACT1 = 0x13012007ull;
+//DUPS: 13012007,
+static const uint64_t P9N2_EQ_4_CME_SCOM_LFIRACT1 = 0x14012007ull;
+//DUPS: 14012007,
+static const uint64_t P9N2_EQ_5_CME_SCOM_LFIRACT1 = 0x15012007ull;
+//DUPS: 15012007,
+static const uint64_t P9N2_EX_CME_SCOM_LFIRACT1 = 0x10012007ull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_LFIRACT1 = 0x10012007ull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_LFIRACT1 = 0x10012407ull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_LFIRACT1 = 0x11012007ull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_LFIRACT1 = 0x11012407ull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_LFIRACT1 = 0x12012007ull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_LFIRACT1 = 0x12012407ull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_LFIRACT1 = 0x13012007ull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_LFIRACT1 = 0x13012407ull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_LFIRACT1 = 0x14012007ull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_LFIRACT1 = 0x14012407ull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_LFIRACT1 = 0x15012007ull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_LFIRACT1 = 0x15012407ull;
+
+
+static const uint64_t P9N2_EQ_CME_SCOM_LFIRMASK = 0x10012003ull;
+//DUPS: 10012003,
+static const uint64_t P9N2_EQ_CME_SCOM_LFIRMASK_AND = 0x10012004ull;
+//DUPS: 10012004,
+static const uint64_t P9N2_EQ_CME_SCOM_LFIRMASK_OR = 0x10012005ull;
+//DUPS: 10012005,
+static const uint64_t P9N2_EQ_0_CME_SCOM_LFIRMASK = 0x10012003ull;
+//DUPS: 10012003,
+static const uint64_t P9N2_EQ_0_CME_SCOM_LFIRMASK_AND = 0x10012004ull;
+//DUPS: 10012004,
+static const uint64_t P9N2_EQ_0_CME_SCOM_LFIRMASK_OR = 0x10012005ull;
+//DUPS: 10012005,
+static const uint64_t P9N2_EQ_1_CME_SCOM_LFIRMASK = 0x11012003ull;
+//DUPS: 11012003,
+static const uint64_t P9N2_EQ_1_CME_SCOM_LFIRMASK_AND = 0x11012004ull;
+//DUPS: 11012004,
+static const uint64_t P9N2_EQ_1_CME_SCOM_LFIRMASK_OR = 0x11012005ull;
+//DUPS: 11012005,
+static const uint64_t P9N2_EQ_2_CME_SCOM_LFIRMASK = 0x12012003ull;
+//DUPS: 12012003,
+static const uint64_t P9N2_EQ_2_CME_SCOM_LFIRMASK_AND = 0x12012004ull;
+//DUPS: 12012004,
+static const uint64_t P9N2_EQ_2_CME_SCOM_LFIRMASK_OR = 0x12012005ull;
+//DUPS: 12012005,
+static const uint64_t P9N2_EQ_3_CME_SCOM_LFIRMASK = 0x13012003ull;
+//DUPS: 13012003,
+static const uint64_t P9N2_EQ_3_CME_SCOM_LFIRMASK_AND = 0x13012004ull;
+//DUPS: 13012004,
+static const uint64_t P9N2_EQ_3_CME_SCOM_LFIRMASK_OR = 0x13012005ull;
+//DUPS: 13012005,
+static const uint64_t P9N2_EQ_4_CME_SCOM_LFIRMASK = 0x14012003ull;
+//DUPS: 14012003,
+static const uint64_t P9N2_EQ_4_CME_SCOM_LFIRMASK_AND = 0x14012004ull;
+//DUPS: 14012004,
+static const uint64_t P9N2_EQ_4_CME_SCOM_LFIRMASK_OR = 0x14012005ull;
+//DUPS: 14012005,
+static const uint64_t P9N2_EQ_5_CME_SCOM_LFIRMASK = 0x15012003ull;
+//DUPS: 15012003,
+static const uint64_t P9N2_EQ_5_CME_SCOM_LFIRMASK_AND = 0x15012004ull;
+//DUPS: 15012004,
+static const uint64_t P9N2_EQ_5_CME_SCOM_LFIRMASK_OR = 0x15012005ull;
+//DUPS: 15012005,
+static const uint64_t P9N2_EX_CME_SCOM_LFIRMASK = 0x10012003ull;
+
+static const uint64_t P9N2_EX_CME_SCOM_LFIRMASK_AND = 0x10012004ull;
+
+static const uint64_t P9N2_EX_CME_SCOM_LFIRMASK_OR = 0x10012005ull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_LFIRMASK = 0x10012003ull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_LFIRMASK_AND = 0x10012004ull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_LFIRMASK_OR = 0x10012005ull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_LFIRMASK = 0x10012403ull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_LFIRMASK_AND = 0x10012404ull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_LFIRMASK_OR = 0x10012405ull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_LFIRMASK = 0x11012003ull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_LFIRMASK_AND = 0x11012004ull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_LFIRMASK_OR = 0x11012005ull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_LFIRMASK = 0x11012403ull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_LFIRMASK_AND = 0x11012404ull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_LFIRMASK_OR = 0x11012405ull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_LFIRMASK = 0x12012003ull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_LFIRMASK_AND = 0x12012004ull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_LFIRMASK_OR = 0x12012005ull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_LFIRMASK = 0x12012403ull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_LFIRMASK_AND = 0x12012404ull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_LFIRMASK_OR = 0x12012405ull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_LFIRMASK = 0x13012003ull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_LFIRMASK_AND = 0x13012004ull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_LFIRMASK_OR = 0x13012005ull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_LFIRMASK = 0x13012403ull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_LFIRMASK_AND = 0x13012404ull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_LFIRMASK_OR = 0x13012405ull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_LFIRMASK = 0x14012003ull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_LFIRMASK_AND = 0x14012004ull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_LFIRMASK_OR = 0x14012005ull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_LFIRMASK = 0x14012403ull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_LFIRMASK_AND = 0x14012404ull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_LFIRMASK_OR = 0x14012405ull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_LFIRMASK = 0x15012003ull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_LFIRMASK_AND = 0x15012004ull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_LFIRMASK_OR = 0x15012005ull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_LFIRMASK = 0x15012403ull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_LFIRMASK_AND = 0x15012404ull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_LFIRMASK_OR = 0x15012405ull;
+
+
+static const uint64_t P9N2_EQ_CME_SCOM_LMCR_SCOM = 0x1001203Aull;
+//DUPS: 1001203A,
+static const uint64_t P9N2_EQ_CME_SCOM_LMCR_SCOM1 = 0x1001203Bull;
+//DUPS: 1001203B,
+static const uint64_t P9N2_EQ_CME_SCOM_LMCR_SCOM2 = 0x1001203Cull;
+//DUPS: 1001203C,
+static const uint64_t P9N2_EQ_0_CME_SCOM_LMCR_SCOM = 0x1001203Aull;
+//DUPS: 1001203A,
+static const uint64_t P9N2_EQ_0_CME_SCOM_LMCR_SCOM1 = 0x1001203Bull;
+//DUPS: 1001203B,
+static const uint64_t P9N2_EQ_0_CME_SCOM_LMCR_SCOM2 = 0x1001203Cull;
+//DUPS: 1001203C,
+static const uint64_t P9N2_EQ_1_CME_SCOM_LMCR_SCOM = 0x1101203Aull;
+//DUPS: 1101203A,
+static const uint64_t P9N2_EQ_1_CME_SCOM_LMCR_SCOM1 = 0x1101203Bull;
+//DUPS: 1101203B,
+static const uint64_t P9N2_EQ_1_CME_SCOM_LMCR_SCOM2 = 0x1101203Cull;
+//DUPS: 1101203C,
+static const uint64_t P9N2_EQ_2_CME_SCOM_LMCR_SCOM = 0x1201203Aull;
+//DUPS: 1201203A,
+static const uint64_t P9N2_EQ_2_CME_SCOM_LMCR_SCOM1 = 0x1201203Bull;
+//DUPS: 1201203B,
+static const uint64_t P9N2_EQ_2_CME_SCOM_LMCR_SCOM2 = 0x1201203Cull;
+//DUPS: 1201203C,
+static const uint64_t P9N2_EQ_3_CME_SCOM_LMCR_SCOM = 0x1301203Aull;
+//DUPS: 1301203A,
+static const uint64_t P9N2_EQ_3_CME_SCOM_LMCR_SCOM1 = 0x1301203Bull;
+//DUPS: 1301203B,
+static const uint64_t P9N2_EQ_3_CME_SCOM_LMCR_SCOM2 = 0x1301203Cull;
+//DUPS: 1301203C,
+static const uint64_t P9N2_EQ_4_CME_SCOM_LMCR_SCOM = 0x1401203Aull;
+//DUPS: 1401203A,
+static const uint64_t P9N2_EQ_4_CME_SCOM_LMCR_SCOM1 = 0x1401203Bull;
+//DUPS: 1401203B,
+static const uint64_t P9N2_EQ_4_CME_SCOM_LMCR_SCOM2 = 0x1401203Cull;
+//DUPS: 1401203C,
+static const uint64_t P9N2_EQ_5_CME_SCOM_LMCR_SCOM = 0x1501203Aull;
+//DUPS: 1501203A,
+static const uint64_t P9N2_EQ_5_CME_SCOM_LMCR_SCOM1 = 0x1501203Bull;
+//DUPS: 1501203B,
+static const uint64_t P9N2_EQ_5_CME_SCOM_LMCR_SCOM2 = 0x1501203Cull;
+//DUPS: 1501203C,
+static const uint64_t P9N2_EX_CME_SCOM_LMCR_PPE = 0x1090101A0ull;
+
+static const uint64_t P9N2_EX_CME_SCOM_LMCR_PPE1 = 0x1090101B8ull;
+
+static const uint64_t P9N2_EX_CME_SCOM_LMCR_PPE2 = 0x1090101B0ull;
+
+static const uint64_t P9N2_EX_CME_SCOM_LMCR_SCOM = 0x1001203Aull;
+
+static const uint64_t P9N2_EX_CME_SCOM_LMCR_SCOM1 = 0x1001203Bull;
+
+static const uint64_t P9N2_EX_CME_SCOM_LMCR_SCOM2 = 0x1001203Cull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_LMCR_PPE = 0x1090101A0ull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_LMCR_PPE1 = 0x1090101B8ull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_LMCR_PPE2 = 0x1090101B0ull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_LMCR_SCOM = 0x1001203Aull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_LMCR_SCOM1 = 0x1001203Bull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_LMCR_SCOM2 = 0x1001203Cull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_LMCR_PPE = 0x1090201A0ull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_LMCR_PPE1 = 0x1090201B8ull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_LMCR_PPE2 = 0x1090201B0ull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_LMCR_SCOM = 0x1001243Aull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_LMCR_SCOM1 = 0x1001243Bull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_LMCR_SCOM2 = 0x1001243Cull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_LMCR_PPE = 0x10A0101A0ull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_LMCR_PPE1 = 0x10A0101B8ull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_LMCR_PPE2 = 0x10A0101B0ull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_LMCR_SCOM = 0x1101203Aull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_LMCR_SCOM1 = 0x1101203Bull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_LMCR_SCOM2 = 0x1101203Cull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_LMCR_PPE = 0x10A0201A0ull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_LMCR_PPE1 = 0x10A0201B8ull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_LMCR_PPE2 = 0x10A0201B0ull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_LMCR_SCOM = 0x1101243Aull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_LMCR_SCOM1 = 0x1101243Bull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_LMCR_SCOM2 = 0x1101243Cull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_LMCR_PPE = 0x10B0101A0ull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_LMCR_PPE1 = 0x10B0101B8ull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_LMCR_PPE2 = 0x10B0101B0ull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_LMCR_SCOM = 0x1201203Aull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_LMCR_SCOM1 = 0x1201203Bull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_LMCR_SCOM2 = 0x1201203Cull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_LMCR_PPE = 0x10B0201A0ull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_LMCR_PPE1 = 0x10B0201B8ull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_LMCR_PPE2 = 0x10B0201B0ull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_LMCR_SCOM = 0x1201243Aull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_LMCR_SCOM1 = 0x1201243Bull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_LMCR_SCOM2 = 0x1201243Cull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_LMCR_PPE = 0x10C0101A0ull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_LMCR_PPE1 = 0x10C0101B8ull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_LMCR_PPE2 = 0x10C0101B0ull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_LMCR_SCOM = 0x1301203Aull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_LMCR_SCOM1 = 0x1301203Bull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_LMCR_SCOM2 = 0x1301203Cull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_LMCR_PPE = 0x10C0201A0ull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_LMCR_PPE1 = 0x10C0201B8ull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_LMCR_PPE2 = 0x10C0201B0ull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_LMCR_SCOM = 0x1301243Aull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_LMCR_SCOM1 = 0x1301243Bull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_LMCR_SCOM2 = 0x1301243Cull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_LMCR_PPE = 0x10D0101A0ull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_LMCR_PPE1 = 0x10D0101B8ull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_LMCR_PPE2 = 0x10D0101B0ull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_LMCR_SCOM = 0x1401203Aull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_LMCR_SCOM1 = 0x1401203Bull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_LMCR_SCOM2 = 0x1401203Cull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_LMCR_PPE = 0x10D0201A0ull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_LMCR_PPE1 = 0x10D0201B8ull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_LMCR_PPE2 = 0x10D0201B0ull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_LMCR_SCOM = 0x1401243Aull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_LMCR_SCOM1 = 0x1401243Bull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_LMCR_SCOM2 = 0x1401243Cull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_LMCR_PPE = 0x10E0101A0ull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_LMCR_PPE1 = 0x10E0101B8ull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_LMCR_PPE2 = 0x10E0101B0ull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_LMCR_SCOM = 0x1501203Aull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_LMCR_SCOM1 = 0x1501203Bull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_LMCR_SCOM2 = 0x1501203Cull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_LMCR_PPE = 0x10E0201A0ull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_LMCR_PPE1 = 0x10E0201B8ull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_LMCR_PPE2 = 0x10E0201B0ull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_LMCR_SCOM = 0x1501243Aull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_LMCR_SCOM1 = 0x1501243Bull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_LMCR_SCOM2 = 0x1501243Cull;
+
+
+static const uint64_t P9N2_EQ_CME_SCOM_PMCRS0 = 0x10012042ull;
+//DUPS: 10012042,
+static const uint64_t P9N2_EQ_0_CME_SCOM_PMCRS0 = 0x10012042ull;
+//DUPS: 10012042,
+static const uint64_t P9N2_EQ_1_CME_SCOM_PMCRS0 = 0x11012042ull;
+//DUPS: 11012042,
+static const uint64_t P9N2_EQ_2_CME_SCOM_PMCRS0 = 0x12012042ull;
+//DUPS: 12012042,
+static const uint64_t P9N2_EQ_3_CME_SCOM_PMCRS0 = 0x13012042ull;
+//DUPS: 13012042,
+static const uint64_t P9N2_EQ_4_CME_SCOM_PMCRS0 = 0x14012042ull;
+//DUPS: 14012042,
+static const uint64_t P9N2_EQ_5_CME_SCOM_PMCRS0 = 0x15012042ull;
+//DUPS: 15012042,
+static const uint64_t P9N2_EX_CME_SCOM_PMCRS0_PPE = 0x109010240ull;
+
+static const uint64_t P9N2_EX_CME_SCOM_PMCRS0_SCOM = 0x10012042ull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_PMCRS0_PPE = 0x109010240ull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_PMCRS0_SCOM = 0x10012042ull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_PMCRS0_PPE = 0x109020240ull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_PMCRS0_SCOM = 0x10012442ull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_PMCRS0_PPE = 0x10A010240ull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_PMCRS0_SCOM = 0x11012042ull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_PMCRS0_PPE = 0x10A020240ull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_PMCRS0_SCOM = 0x11012442ull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_PMCRS0_PPE = 0x10B010240ull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_PMCRS0_SCOM = 0x12012042ull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_PMCRS0_PPE = 0x10B020240ull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_PMCRS0_SCOM = 0x12012442ull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_PMCRS0_PPE = 0x10C010240ull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_PMCRS0_SCOM = 0x13012042ull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_PMCRS0_PPE = 0x10C020240ull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_PMCRS0_SCOM = 0x13012442ull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_PMCRS0_PPE = 0x10D010240ull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_PMCRS0_SCOM = 0x14012042ull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_PMCRS0_PPE = 0x10D020240ull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_PMCRS0_SCOM = 0x14012442ull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_PMCRS0_PPE = 0x10E010240ull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_PMCRS0_SCOM = 0x15012042ull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_PMCRS0_PPE = 0x10E020240ull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_PMCRS0_SCOM = 0x15012442ull;
+
+
+static const uint64_t P9N2_EQ_CME_SCOM_PMCRS1 = 0x10012043ull;
+//DUPS: 10012043,
+static const uint64_t P9N2_EQ_0_CME_SCOM_PMCRS1 = 0x10012043ull;
+//DUPS: 10012043,
+static const uint64_t P9N2_EQ_1_CME_SCOM_PMCRS1 = 0x11012043ull;
+//DUPS: 11012043,
+static const uint64_t P9N2_EQ_2_CME_SCOM_PMCRS1 = 0x12012043ull;
+//DUPS: 12012043,
+static const uint64_t P9N2_EQ_3_CME_SCOM_PMCRS1 = 0x13012043ull;
+//DUPS: 13012043,
+static const uint64_t P9N2_EQ_4_CME_SCOM_PMCRS1 = 0x14012043ull;
+//DUPS: 14012043,
+static const uint64_t P9N2_EQ_5_CME_SCOM_PMCRS1 = 0x15012043ull;
+//DUPS: 15012043,
+static const uint64_t P9N2_EX_CME_SCOM_PMCRS1_PPE = 0x109010260ull;
+
+static const uint64_t P9N2_EX_CME_SCOM_PMCRS1_SCOM = 0x10012043ull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_PMCRS1_PPE = 0x109010260ull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_PMCRS1_SCOM = 0x10012043ull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_PMCRS1_PPE = 0x109020260ull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_PMCRS1_SCOM = 0x10012443ull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_PMCRS1_PPE = 0x10A010260ull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_PMCRS1_SCOM = 0x11012043ull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_PMCRS1_PPE = 0x10A020260ull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_PMCRS1_SCOM = 0x11012443ull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_PMCRS1_PPE = 0x10B010260ull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_PMCRS1_SCOM = 0x12012043ull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_PMCRS1_PPE = 0x10B020260ull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_PMCRS1_SCOM = 0x12012443ull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_PMCRS1_PPE = 0x10C010260ull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_PMCRS1_SCOM = 0x13012043ull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_PMCRS1_PPE = 0x10C020260ull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_PMCRS1_SCOM = 0x13012443ull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_PMCRS1_PPE = 0x10D010260ull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_PMCRS1_SCOM = 0x14012043ull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_PMCRS1_PPE = 0x10D020260ull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_PMCRS1_SCOM = 0x14012443ull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_PMCRS1_PPE = 0x10E010260ull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_PMCRS1_SCOM = 0x15012043ull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_PMCRS1_PPE = 0x10E020260ull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_PMCRS1_SCOM = 0x15012443ull;
+
+
+static const uint64_t P9N2_EQ_CME_SCOM_PMSRS0 = 0x10012040ull;
+//DUPS: 10012040,
+static const uint64_t P9N2_EQ_0_CME_SCOM_PMSRS0 = 0x10012040ull;
+//DUPS: 10012040,
+static const uint64_t P9N2_EQ_1_CME_SCOM_PMSRS0 = 0x11012040ull;
+//DUPS: 11012040,
+static const uint64_t P9N2_EQ_2_CME_SCOM_PMSRS0 = 0x12012040ull;
+//DUPS: 12012040,
+static const uint64_t P9N2_EQ_3_CME_SCOM_PMSRS0 = 0x13012040ull;
+//DUPS: 13012040,
+static const uint64_t P9N2_EQ_4_CME_SCOM_PMSRS0 = 0x14012040ull;
+//DUPS: 14012040,
+static const uint64_t P9N2_EQ_5_CME_SCOM_PMSRS0 = 0x15012040ull;
+//DUPS: 15012040,
+static const uint64_t P9N2_EX_CME_SCOM_PMSRS0_PPE = 0x109010200ull;
+
+static const uint64_t P9N2_EX_CME_SCOM_PMSRS0_SCOM = 0x10012040ull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_PMSRS0_PPE = 0x109010200ull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_PMSRS0_SCOM = 0x10012040ull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_PMSRS0_PPE = 0x109020200ull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_PMSRS0_SCOM = 0x10012440ull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_PMSRS0_PPE = 0x10A010200ull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_PMSRS0_SCOM = 0x11012040ull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_PMSRS0_PPE = 0x10A020200ull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_PMSRS0_SCOM = 0x11012440ull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_PMSRS0_PPE = 0x10B010200ull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_PMSRS0_SCOM = 0x12012040ull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_PMSRS0_PPE = 0x10B020200ull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_PMSRS0_SCOM = 0x12012440ull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_PMSRS0_PPE = 0x10C010200ull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_PMSRS0_SCOM = 0x13012040ull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_PMSRS0_PPE = 0x10C020200ull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_PMSRS0_SCOM = 0x13012440ull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_PMSRS0_PPE = 0x10D010200ull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_PMSRS0_SCOM = 0x14012040ull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_PMSRS0_PPE = 0x10D020200ull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_PMSRS0_SCOM = 0x14012440ull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_PMSRS0_PPE = 0x10E010200ull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_PMSRS0_SCOM = 0x15012040ull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_PMSRS0_PPE = 0x10E020200ull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_PMSRS0_SCOM = 0x15012440ull;
+
+
+static const uint64_t P9N2_EQ_CME_SCOM_PMSRS1 = 0x10012041ull;
+//DUPS: 10012041,
+static const uint64_t P9N2_EQ_0_CME_SCOM_PMSRS1 = 0x10012041ull;
+//DUPS: 10012041,
+static const uint64_t P9N2_EQ_1_CME_SCOM_PMSRS1 = 0x11012041ull;
+//DUPS: 11012041,
+static const uint64_t P9N2_EQ_2_CME_SCOM_PMSRS1 = 0x12012041ull;
+//DUPS: 12012041,
+static const uint64_t P9N2_EQ_3_CME_SCOM_PMSRS1 = 0x13012041ull;
+//DUPS: 13012041,
+static const uint64_t P9N2_EQ_4_CME_SCOM_PMSRS1 = 0x14012041ull;
+//DUPS: 14012041,
+static const uint64_t P9N2_EQ_5_CME_SCOM_PMSRS1 = 0x15012041ull;
+//DUPS: 15012041,
+static const uint64_t P9N2_EX_CME_SCOM_PMSRS1_PPE = 0x109010220ull;
+
+static const uint64_t P9N2_EX_CME_SCOM_PMSRS1_SCOM = 0x10012041ull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_PMSRS1_PPE = 0x109010220ull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_PMSRS1_SCOM = 0x10012041ull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_PMSRS1_PPE = 0x109020220ull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_PMSRS1_SCOM = 0x10012441ull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_PMSRS1_PPE = 0x10A010220ull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_PMSRS1_SCOM = 0x11012041ull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_PMSRS1_PPE = 0x10A020220ull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_PMSRS1_SCOM = 0x11012441ull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_PMSRS1_PPE = 0x10B010220ull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_PMSRS1_SCOM = 0x12012041ull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_PMSRS1_PPE = 0x10B020220ull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_PMSRS1_SCOM = 0x12012441ull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_PMSRS1_PPE = 0x10C010220ull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_PMSRS1_SCOM = 0x13012041ull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_PMSRS1_PPE = 0x10C020220ull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_PMSRS1_SCOM = 0x13012441ull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_PMSRS1_PPE = 0x10D010220ull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_PMSRS1_SCOM = 0x14012041ull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_PMSRS1_PPE = 0x10D020220ull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_PMSRS1_SCOM = 0x14012441ull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_PMSRS1_PPE = 0x10E010220ull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_PMSRS1_SCOM = 0x15012041ull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_PMSRS1_PPE = 0x10E020220ull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_PMSRS1_SCOM = 0x15012441ull;
+
+
+static const uint64_t P9N2_EQ_CME_SCOM_PSCRS00 = 0x10012044ull;
+//DUPS: 10012044,
+static const uint64_t P9N2_EQ_0_CME_SCOM_PSCRS00 = 0x10012044ull;
+//DUPS: 10012044,
+static const uint64_t P9N2_EQ_1_CME_SCOM_PSCRS00 = 0x11012044ull;
+//DUPS: 11012044,
+static const uint64_t P9N2_EQ_2_CME_SCOM_PSCRS00 = 0x12012044ull;
+//DUPS: 12012044,
+static const uint64_t P9N2_EQ_3_CME_SCOM_PSCRS00 = 0x13012044ull;
+//DUPS: 13012044,
+static const uint64_t P9N2_EQ_4_CME_SCOM_PSCRS00 = 0x14012044ull;
+//DUPS: 14012044,
+static const uint64_t P9N2_EQ_5_CME_SCOM_PSCRS00 = 0x15012044ull;
+//DUPS: 15012044,
+static const uint64_t P9N2_EX_CME_SCOM_PSCRS00_PPE = 0x109010300ull;
+
+static const uint64_t P9N2_EX_CME_SCOM_PSCRS00_SCOM = 0x10012044ull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_PSCRS00_PPE = 0x109010300ull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_PSCRS00_SCOM = 0x10012044ull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_PSCRS00_PPE = 0x109020300ull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_PSCRS00_SCOM = 0x10012444ull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_PSCRS00_PPE = 0x10A010300ull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_PSCRS00_SCOM = 0x11012044ull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_PSCRS00_PPE = 0x10A020300ull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_PSCRS00_SCOM = 0x11012444ull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_PSCRS00_PPE = 0x10B010300ull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_PSCRS00_SCOM = 0x12012044ull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_PSCRS00_PPE = 0x10B020300ull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_PSCRS00_SCOM = 0x12012444ull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_PSCRS00_PPE = 0x10C010300ull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_PSCRS00_SCOM = 0x13012044ull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_PSCRS00_PPE = 0x10C020300ull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_PSCRS00_SCOM = 0x13012444ull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_PSCRS00_PPE = 0x10D010300ull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_PSCRS00_SCOM = 0x14012044ull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_PSCRS00_PPE = 0x10D020300ull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_PSCRS00_SCOM = 0x14012444ull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_PSCRS00_PPE = 0x10E010300ull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_PSCRS00_SCOM = 0x15012044ull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_PSCRS00_PPE = 0x10E020300ull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_PSCRS00_SCOM = 0x15012444ull;
+
+
+static const uint64_t P9N2_EQ_CME_SCOM_PSCRS01 = 0x10012045ull;
+//DUPS: 10012045,
+static const uint64_t P9N2_EQ_0_CME_SCOM_PSCRS01 = 0x10012045ull;
+//DUPS: 10012045,
+static const uint64_t P9N2_EQ_1_CME_SCOM_PSCRS01 = 0x11012045ull;
+//DUPS: 11012045,
+static const uint64_t P9N2_EQ_2_CME_SCOM_PSCRS01 = 0x12012045ull;
+//DUPS: 12012045,
+static const uint64_t P9N2_EQ_3_CME_SCOM_PSCRS01 = 0x13012045ull;
+//DUPS: 13012045,
+static const uint64_t P9N2_EQ_4_CME_SCOM_PSCRS01 = 0x14012045ull;
+//DUPS: 14012045,
+static const uint64_t P9N2_EQ_5_CME_SCOM_PSCRS01 = 0x15012045ull;
+//DUPS: 15012045,
+static const uint64_t P9N2_EX_CME_SCOM_PSCRS01_PPE = 0x109010320ull;
+
+static const uint64_t P9N2_EX_CME_SCOM_PSCRS01_SCOM = 0x10012045ull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_PSCRS01_PPE = 0x109010320ull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_PSCRS01_SCOM = 0x10012045ull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_PSCRS01_PPE = 0x109020320ull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_PSCRS01_SCOM = 0x10012445ull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_PSCRS01_PPE = 0x10A010320ull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_PSCRS01_SCOM = 0x11012045ull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_PSCRS01_PPE = 0x10A020320ull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_PSCRS01_SCOM = 0x11012445ull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_PSCRS01_PPE = 0x10B010320ull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_PSCRS01_SCOM = 0x12012045ull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_PSCRS01_PPE = 0x10B020320ull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_PSCRS01_SCOM = 0x12012445ull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_PSCRS01_PPE = 0x10C010320ull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_PSCRS01_SCOM = 0x13012045ull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_PSCRS01_PPE = 0x10C020320ull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_PSCRS01_SCOM = 0x13012445ull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_PSCRS01_PPE = 0x10D010320ull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_PSCRS01_SCOM = 0x14012045ull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_PSCRS01_PPE = 0x10D020320ull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_PSCRS01_SCOM = 0x14012445ull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_PSCRS01_PPE = 0x10E010320ull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_PSCRS01_SCOM = 0x15012045ull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_PSCRS01_PPE = 0x10E020320ull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_PSCRS01_SCOM = 0x15012445ull;
+
+
+static const uint64_t P9N2_EQ_CME_SCOM_PSCRS02 = 0x10012046ull;
+//DUPS: 10012046,
+static const uint64_t P9N2_EQ_0_CME_SCOM_PSCRS02 = 0x10012046ull;
+//DUPS: 10012046,
+static const uint64_t P9N2_EQ_1_CME_SCOM_PSCRS02 = 0x11012046ull;
+//DUPS: 11012046,
+static const uint64_t P9N2_EQ_2_CME_SCOM_PSCRS02 = 0x12012046ull;
+//DUPS: 12012046,
+static const uint64_t P9N2_EQ_3_CME_SCOM_PSCRS02 = 0x13012046ull;
+//DUPS: 13012046,
+static const uint64_t P9N2_EQ_4_CME_SCOM_PSCRS02 = 0x14012046ull;
+//DUPS: 14012046,
+static const uint64_t P9N2_EQ_5_CME_SCOM_PSCRS02 = 0x15012046ull;
+//DUPS: 15012046,
+static const uint64_t P9N2_EX_CME_SCOM_PSCRS02_PPE = 0x109010340ull;
+
+static const uint64_t P9N2_EX_CME_SCOM_PSCRS02_SCOM = 0x10012046ull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_PSCRS02_PPE = 0x109010340ull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_PSCRS02_SCOM = 0x10012046ull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_PSCRS02_PPE = 0x109020340ull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_PSCRS02_SCOM = 0x10012446ull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_PSCRS02_PPE = 0x10A010340ull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_PSCRS02_SCOM = 0x11012046ull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_PSCRS02_PPE = 0x10A020340ull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_PSCRS02_SCOM = 0x11012446ull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_PSCRS02_PPE = 0x10B010340ull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_PSCRS02_SCOM = 0x12012046ull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_PSCRS02_PPE = 0x10B020340ull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_PSCRS02_SCOM = 0x12012446ull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_PSCRS02_PPE = 0x10C010340ull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_PSCRS02_SCOM = 0x13012046ull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_PSCRS02_PPE = 0x10C020340ull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_PSCRS02_SCOM = 0x13012446ull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_PSCRS02_PPE = 0x10D010340ull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_PSCRS02_SCOM = 0x14012046ull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_PSCRS02_PPE = 0x10D020340ull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_PSCRS02_SCOM = 0x14012446ull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_PSCRS02_PPE = 0x10E010340ull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_PSCRS02_SCOM = 0x15012046ull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_PSCRS02_PPE = 0x10E020340ull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_PSCRS02_SCOM = 0x15012446ull;
+
+
+static const uint64_t P9N2_EQ_CME_SCOM_PSCRS03 = 0x10012047ull;
+//DUPS: 10012047,
+static const uint64_t P9N2_EQ_0_CME_SCOM_PSCRS03 = 0x10012047ull;
+//DUPS: 10012047,
+static const uint64_t P9N2_EQ_1_CME_SCOM_PSCRS03 = 0x11012047ull;
+//DUPS: 11012047,
+static const uint64_t P9N2_EQ_2_CME_SCOM_PSCRS03 = 0x12012047ull;
+//DUPS: 12012047,
+static const uint64_t P9N2_EQ_3_CME_SCOM_PSCRS03 = 0x13012047ull;
+//DUPS: 13012047,
+static const uint64_t P9N2_EQ_4_CME_SCOM_PSCRS03 = 0x14012047ull;
+//DUPS: 14012047,
+static const uint64_t P9N2_EQ_5_CME_SCOM_PSCRS03 = 0x15012047ull;
+//DUPS: 15012047,
+static const uint64_t P9N2_EX_CME_SCOM_PSCRS03_PPE = 0x109010360ull;
+
+static const uint64_t P9N2_EX_CME_SCOM_PSCRS03_SCOM = 0x10012047ull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_PSCRS03_PPE = 0x109010360ull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_PSCRS03_SCOM = 0x10012047ull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_PSCRS03_PPE = 0x109020360ull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_PSCRS03_SCOM = 0x10012447ull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_PSCRS03_PPE = 0x10A010360ull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_PSCRS03_SCOM = 0x11012047ull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_PSCRS03_PPE = 0x10A020360ull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_PSCRS03_SCOM = 0x11012447ull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_PSCRS03_PPE = 0x10B010360ull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_PSCRS03_SCOM = 0x12012047ull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_PSCRS03_PPE = 0x10B020360ull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_PSCRS03_SCOM = 0x12012447ull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_PSCRS03_PPE = 0x10C010360ull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_PSCRS03_SCOM = 0x13012047ull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_PSCRS03_PPE = 0x10C020360ull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_PSCRS03_SCOM = 0x13012447ull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_PSCRS03_PPE = 0x10D010360ull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_PSCRS03_SCOM = 0x14012047ull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_PSCRS03_PPE = 0x10D020360ull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_PSCRS03_SCOM = 0x14012447ull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_PSCRS03_PPE = 0x10E010360ull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_PSCRS03_SCOM = 0x15012047ull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_PSCRS03_PPE = 0x10E020360ull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_PSCRS03_SCOM = 0x15012447ull;
+
+
+static const uint64_t P9N2_EQ_CME_SCOM_PSCRS10 = 0x10012048ull;
+//DUPS: 10012048,
+static const uint64_t P9N2_EQ_0_CME_SCOM_PSCRS10 = 0x10012048ull;
+//DUPS: 10012048,
+static const uint64_t P9N2_EQ_1_CME_SCOM_PSCRS10 = 0x11012048ull;
+//DUPS: 11012048,
+static const uint64_t P9N2_EQ_2_CME_SCOM_PSCRS10 = 0x12012048ull;
+//DUPS: 12012048,
+static const uint64_t P9N2_EQ_3_CME_SCOM_PSCRS10 = 0x13012048ull;
+//DUPS: 13012048,
+static const uint64_t P9N2_EQ_4_CME_SCOM_PSCRS10 = 0x14012048ull;
+//DUPS: 14012048,
+static const uint64_t P9N2_EQ_5_CME_SCOM_PSCRS10 = 0x15012048ull;
+//DUPS: 15012048,
+static const uint64_t P9N2_EX_CME_SCOM_PSCRS10_PPE = 0x109010380ull;
+
+static const uint64_t P9N2_EX_CME_SCOM_PSCRS10_SCOM = 0x10012048ull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_PSCRS10_PPE = 0x109010380ull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_PSCRS10_SCOM = 0x10012048ull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_PSCRS10_PPE = 0x109020380ull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_PSCRS10_SCOM = 0x10012448ull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_PSCRS10_PPE = 0x10A010380ull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_PSCRS10_SCOM = 0x11012048ull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_PSCRS10_PPE = 0x10A020380ull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_PSCRS10_SCOM = 0x11012448ull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_PSCRS10_PPE = 0x10B010380ull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_PSCRS10_SCOM = 0x12012048ull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_PSCRS10_PPE = 0x10B020380ull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_PSCRS10_SCOM = 0x12012448ull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_PSCRS10_PPE = 0x10C010380ull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_PSCRS10_SCOM = 0x13012048ull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_PSCRS10_PPE = 0x10C020380ull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_PSCRS10_SCOM = 0x13012448ull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_PSCRS10_PPE = 0x10D010380ull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_PSCRS10_SCOM = 0x14012048ull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_PSCRS10_PPE = 0x10D020380ull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_PSCRS10_SCOM = 0x14012448ull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_PSCRS10_PPE = 0x10E010380ull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_PSCRS10_SCOM = 0x15012048ull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_PSCRS10_PPE = 0x10E020380ull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_PSCRS10_SCOM = 0x15012448ull;
+
+
+static const uint64_t P9N2_EQ_CME_SCOM_PSCRS11 = 0x10012049ull;
+//DUPS: 10012049,
+static const uint64_t P9N2_EQ_0_CME_SCOM_PSCRS11 = 0x10012049ull;
+//DUPS: 10012049,
+static const uint64_t P9N2_EQ_1_CME_SCOM_PSCRS11 = 0x11012049ull;
+//DUPS: 11012049,
+static const uint64_t P9N2_EQ_2_CME_SCOM_PSCRS11 = 0x12012049ull;
+//DUPS: 12012049,
+static const uint64_t P9N2_EQ_3_CME_SCOM_PSCRS11 = 0x13012049ull;
+//DUPS: 13012049,
+static const uint64_t P9N2_EQ_4_CME_SCOM_PSCRS11 = 0x14012049ull;
+//DUPS: 14012049,
+static const uint64_t P9N2_EQ_5_CME_SCOM_PSCRS11 = 0x15012049ull;
+//DUPS: 15012049,
+static const uint64_t P9N2_EX_CME_SCOM_PSCRS11_PPE = 0x1090103A0ull;
+
+static const uint64_t P9N2_EX_CME_SCOM_PSCRS11_SCOM = 0x10012049ull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_PSCRS11_PPE = 0x1090103A0ull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_PSCRS11_SCOM = 0x10012049ull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_PSCRS11_PPE = 0x1090203A0ull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_PSCRS11_SCOM = 0x10012449ull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_PSCRS11_PPE = 0x10A0103A0ull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_PSCRS11_SCOM = 0x11012049ull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_PSCRS11_PPE = 0x10A0203A0ull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_PSCRS11_SCOM = 0x11012449ull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_PSCRS11_PPE = 0x10B0103A0ull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_PSCRS11_SCOM = 0x12012049ull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_PSCRS11_PPE = 0x10B0203A0ull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_PSCRS11_SCOM = 0x12012449ull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_PSCRS11_PPE = 0x10C0103A0ull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_PSCRS11_SCOM = 0x13012049ull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_PSCRS11_PPE = 0x10C0203A0ull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_PSCRS11_SCOM = 0x13012449ull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_PSCRS11_PPE = 0x10D0103A0ull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_PSCRS11_SCOM = 0x14012049ull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_PSCRS11_PPE = 0x10D0203A0ull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_PSCRS11_SCOM = 0x14012449ull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_PSCRS11_PPE = 0x10E0103A0ull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_PSCRS11_SCOM = 0x15012049ull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_PSCRS11_PPE = 0x10E0203A0ull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_PSCRS11_SCOM = 0x15012449ull;
+
+
+static const uint64_t P9N2_EQ_CME_SCOM_PSCRS12 = 0x1001204Aull;
+//DUPS: 1001204A,
+static const uint64_t P9N2_EQ_0_CME_SCOM_PSCRS12 = 0x1001204Aull;
+//DUPS: 1001204A,
+static const uint64_t P9N2_EQ_1_CME_SCOM_PSCRS12 = 0x1101204Aull;
+//DUPS: 1101204A,
+static const uint64_t P9N2_EQ_2_CME_SCOM_PSCRS12 = 0x1201204Aull;
+//DUPS: 1201204A,
+static const uint64_t P9N2_EQ_3_CME_SCOM_PSCRS12 = 0x1301204Aull;
+//DUPS: 1301204A,
+static const uint64_t P9N2_EQ_4_CME_SCOM_PSCRS12 = 0x1401204Aull;
+//DUPS: 1401204A,
+static const uint64_t P9N2_EQ_5_CME_SCOM_PSCRS12 = 0x1501204Aull;
+//DUPS: 1501204A,
+static const uint64_t P9N2_EX_CME_SCOM_PSCRS12_PPE = 0x1090103C0ull;
+
+static const uint64_t P9N2_EX_CME_SCOM_PSCRS12_SCOM = 0x1001204Aull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_PSCRS12_PPE = 0x1090103C0ull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_PSCRS12_SCOM = 0x1001204Aull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_PSCRS12_PPE = 0x1090203C0ull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_PSCRS12_SCOM = 0x1001244Aull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_PSCRS12_PPE = 0x10A0103C0ull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_PSCRS12_SCOM = 0x1101204Aull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_PSCRS12_PPE = 0x10A0203C0ull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_PSCRS12_SCOM = 0x1101244Aull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_PSCRS12_PPE = 0x10B0103C0ull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_PSCRS12_SCOM = 0x1201204Aull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_PSCRS12_PPE = 0x10B0203C0ull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_PSCRS12_SCOM = 0x1201244Aull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_PSCRS12_PPE = 0x10C0103C0ull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_PSCRS12_SCOM = 0x1301204Aull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_PSCRS12_PPE = 0x10C0203C0ull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_PSCRS12_SCOM = 0x1301244Aull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_PSCRS12_PPE = 0x10D0103C0ull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_PSCRS12_SCOM = 0x1401204Aull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_PSCRS12_PPE = 0x10D0203C0ull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_PSCRS12_SCOM = 0x1401244Aull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_PSCRS12_PPE = 0x10E0103C0ull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_PSCRS12_SCOM = 0x1501204Aull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_PSCRS12_PPE = 0x10E0203C0ull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_PSCRS12_SCOM = 0x1501244Aull;
+
+
+static const uint64_t P9N2_EQ_CME_SCOM_PSCRS13 = 0x1001204Bull;
+//DUPS: 1001204B,
+static const uint64_t P9N2_EQ_0_CME_SCOM_PSCRS13 = 0x1001204Bull;
+//DUPS: 1001204B,
+static const uint64_t P9N2_EQ_1_CME_SCOM_PSCRS13 = 0x1101204Bull;
+//DUPS: 1101204B,
+static const uint64_t P9N2_EQ_2_CME_SCOM_PSCRS13 = 0x1201204Bull;
+//DUPS: 1201204B,
+static const uint64_t P9N2_EQ_3_CME_SCOM_PSCRS13 = 0x1301204Bull;
+//DUPS: 1301204B,
+static const uint64_t P9N2_EQ_4_CME_SCOM_PSCRS13 = 0x1401204Bull;
+//DUPS: 1401204B,
+static const uint64_t P9N2_EQ_5_CME_SCOM_PSCRS13 = 0x1501204Bull;
+//DUPS: 1501204B,
+static const uint64_t P9N2_EX_CME_SCOM_PSCRS13_PPE = 0x1090103E0ull;
+
+static const uint64_t P9N2_EX_CME_SCOM_PSCRS13_SCOM = 0x1001204Bull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_PSCRS13_PPE = 0x1090103E0ull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_PSCRS13_SCOM = 0x1001204Bull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_PSCRS13_PPE = 0x1090203E0ull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_PSCRS13_SCOM = 0x1001244Bull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_PSCRS13_PPE = 0x10A0103E0ull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_PSCRS13_SCOM = 0x1101204Bull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_PSCRS13_PPE = 0x10A0203E0ull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_PSCRS13_SCOM = 0x1101244Bull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_PSCRS13_PPE = 0x10B0103E0ull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_PSCRS13_SCOM = 0x1201204Bull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_PSCRS13_PPE = 0x10B0203E0ull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_PSCRS13_SCOM = 0x1201244Bull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_PSCRS13_PPE = 0x10C0103E0ull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_PSCRS13_SCOM = 0x1301204Bull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_PSCRS13_PPE = 0x10C0203E0ull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_PSCRS13_SCOM = 0x1301244Bull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_PSCRS13_PPE = 0x10D0103E0ull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_PSCRS13_SCOM = 0x1401204Bull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_PSCRS13_PPE = 0x10D0203E0ull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_PSCRS13_SCOM = 0x1401244Bull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_PSCRS13_PPE = 0x10E0103E0ull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_PSCRS13_SCOM = 0x1501204Bull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_PSCRS13_PPE = 0x10E0203E0ull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_PSCRS13_SCOM = 0x1501244Bull;
+
+
+static const uint64_t P9N2_EQ_CME_SCOM_QFMR = 0x10012032ull;
+//DUPS: 10012032,
+static const uint64_t P9N2_EQ_0_CME_SCOM_QFMR = 0x10012032ull;
+//DUPS: 10012032,
+static const uint64_t P9N2_EQ_1_CME_SCOM_QFMR = 0x11012032ull;
+//DUPS: 11012032,
+static const uint64_t P9N2_EQ_2_CME_SCOM_QFMR = 0x12012032ull;
+//DUPS: 12012032,
+static const uint64_t P9N2_EQ_3_CME_SCOM_QFMR = 0x13012032ull;
+//DUPS: 13012032,
+static const uint64_t P9N2_EQ_4_CME_SCOM_QFMR = 0x14012032ull;
+//DUPS: 14012032,
+static const uint64_t P9N2_EQ_5_CME_SCOM_QFMR = 0x15012032ull;
+//DUPS: 15012032,
+static const uint64_t P9N2_EX_CME_SCOM_QFMR_PPE = 0x109010140ull;
+
+static const uint64_t P9N2_EX_CME_SCOM_QFMR_SCOM = 0x10012032ull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_QFMR_PPE = 0x109010140ull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_QFMR_SCOM = 0x10012032ull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_QFMR_PPE = 0x109020140ull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_QFMR_SCOM = 0x10012432ull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_QFMR_PPE = 0x10A010140ull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_QFMR_SCOM = 0x11012032ull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_QFMR_PPE = 0x10A020140ull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_QFMR_SCOM = 0x11012432ull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_QFMR_PPE = 0x10B010140ull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_QFMR_SCOM = 0x12012032ull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_QFMR_PPE = 0x10B020140ull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_QFMR_SCOM = 0x12012432ull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_QFMR_PPE = 0x10C010140ull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_QFMR_SCOM = 0x13012032ull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_QFMR_PPE = 0x10C020140ull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_QFMR_SCOM = 0x13012432ull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_QFMR_PPE = 0x10D010140ull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_QFMR_SCOM = 0x14012032ull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_QFMR_PPE = 0x10D020140ull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_QFMR_SCOM = 0x14012432ull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_QFMR_PPE = 0x10E010140ull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_QFMR_SCOM = 0x15012032ull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_QFMR_PPE = 0x10E020140ull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_QFMR_SCOM = 0x15012432ull;
+
+
+static const uint64_t P9N2_EQ_CME_SCOM_QIDSR = 0x1001202Full;
+//DUPS: 1001202F,
+static const uint64_t P9N2_EQ_0_CME_SCOM_QIDSR = 0x1001202Full;
+//DUPS: 1001202F,
+static const uint64_t P9N2_EQ_1_CME_SCOM_QIDSR = 0x1101202Full;
+//DUPS: 1101202F,
+static const uint64_t P9N2_EQ_2_CME_SCOM_QIDSR = 0x1201202Full;
+//DUPS: 1201202F,
+static const uint64_t P9N2_EQ_3_CME_SCOM_QIDSR = 0x1301202Full;
+//DUPS: 1301202F,
+static const uint64_t P9N2_EQ_4_CME_SCOM_QIDSR = 0x1401202Full;
+//DUPS: 1401202F,
+static const uint64_t P9N2_EQ_5_CME_SCOM_QIDSR = 0x1501202Full;
+//DUPS: 1501202F,
+static const uint64_t P9N2_EX_CME_SCOM_QIDSR_PPE = 0x1090106E0ull;
+
+static const uint64_t P9N2_EX_CME_SCOM_QIDSR_SCOM = 0x1001202Full;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_QIDSR_PPE = 0x1090106E0ull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_QIDSR_SCOM = 0x1001202Full;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_QIDSR_PPE = 0x1090206E0ull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_QIDSR_SCOM = 0x1001242Full;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_QIDSR_PPE = 0x10A0106E0ull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_QIDSR_SCOM = 0x1101202Full;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_QIDSR_PPE = 0x10A0206E0ull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_QIDSR_SCOM = 0x1101242Full;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_QIDSR_PPE = 0x10B0106E0ull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_QIDSR_SCOM = 0x1201202Full;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_QIDSR_PPE = 0x10B0206E0ull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_QIDSR_SCOM = 0x1201242Full;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_QIDSR_PPE = 0x10C0106E0ull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_QIDSR_SCOM = 0x1301202Full;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_QIDSR_PPE = 0x10C0206E0ull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_QIDSR_SCOM = 0x1301242Full;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_QIDSR_PPE = 0x10D0106E0ull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_QIDSR_SCOM = 0x1401202Full;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_QIDSR_PPE = 0x10D0206E0ull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_QIDSR_SCOM = 0x1401242Full;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_QIDSR_PPE = 0x10E0106E0ull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_QIDSR_SCOM = 0x1501202Full;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_QIDSR_PPE = 0x10E0206E0ull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_QIDSR_SCOM = 0x1501242Full;
+
+
+static const uint64_t P9N2_EQ_CME_SCOM_SICR_SCOM = 0x1001203Dull;
+//DUPS: 1001203D,
+static const uint64_t P9N2_EQ_CME_SCOM_SICR_SCOM1 = 0x1001203Eull;
+//DUPS: 1001203E,
+static const uint64_t P9N2_EQ_CME_SCOM_SICR_SCOM2 = 0x1001203Full;
+//DUPS: 1001203F,
+static const uint64_t P9N2_EQ_0_CME_SCOM_SICR_SCOM = 0x1001203Dull;
+//DUPS: 1001203D,
+static const uint64_t P9N2_EQ_0_CME_SCOM_SICR_SCOM1 = 0x1001203Eull;
+//DUPS: 1001203E,
+static const uint64_t P9N2_EQ_0_CME_SCOM_SICR_SCOM2 = 0x1001203Full;
+//DUPS: 1001203F,
+static const uint64_t P9N2_EQ_1_CME_SCOM_SICR_SCOM = 0x1101203Dull;
+//DUPS: 1101203D,
+static const uint64_t P9N2_EQ_1_CME_SCOM_SICR_SCOM1 = 0x1101203Eull;
+//DUPS: 1101203E,
+static const uint64_t P9N2_EQ_1_CME_SCOM_SICR_SCOM2 = 0x1101203Full;
+//DUPS: 1101203F,
+static const uint64_t P9N2_EQ_2_CME_SCOM_SICR_SCOM = 0x1201203Dull;
+//DUPS: 1201203D,
+static const uint64_t P9N2_EQ_2_CME_SCOM_SICR_SCOM1 = 0x1201203Eull;
+//DUPS: 1201203E,
+static const uint64_t P9N2_EQ_2_CME_SCOM_SICR_SCOM2 = 0x1201203Full;
+//DUPS: 1201203F,
+static const uint64_t P9N2_EQ_3_CME_SCOM_SICR_SCOM = 0x1301203Dull;
+//DUPS: 1301203D,
+static const uint64_t P9N2_EQ_3_CME_SCOM_SICR_SCOM1 = 0x1301203Eull;
+//DUPS: 1301203E,
+static const uint64_t P9N2_EQ_3_CME_SCOM_SICR_SCOM2 = 0x1301203Full;
+//DUPS: 1301203F,
+static const uint64_t P9N2_EQ_4_CME_SCOM_SICR_SCOM = 0x1401203Dull;
+//DUPS: 1401203D,
+static const uint64_t P9N2_EQ_4_CME_SCOM_SICR_SCOM1 = 0x1401203Eull;
+//DUPS: 1401203E,
+static const uint64_t P9N2_EQ_4_CME_SCOM_SICR_SCOM2 = 0x1401203Full;
+//DUPS: 1401203F,
+static const uint64_t P9N2_EQ_5_CME_SCOM_SICR_SCOM = 0x1501203Dull;
+//DUPS: 1501203D,
+static const uint64_t P9N2_EQ_5_CME_SCOM_SICR_SCOM1 = 0x1501203Eull;
+//DUPS: 1501203E,
+static const uint64_t P9N2_EQ_5_CME_SCOM_SICR_SCOM2 = 0x1501203Full;
+//DUPS: 1501203F,
+static const uint64_t P9N2_EX_CME_SCOM_SICR_PPE = 0x109010500ull;
+
+static const uint64_t P9N2_EX_CME_SCOM_SICR_PPE1 = 0x109010518ull;
+
+static const uint64_t P9N2_EX_CME_SCOM_SICR_PPE2 = 0x109010510ull;
+
+static const uint64_t P9N2_EX_CME_SCOM_SICR_SCOM = 0x1001203Dull;
+
+static const uint64_t P9N2_EX_CME_SCOM_SICR_SCOM1 = 0x1001203Eull;
+
+static const uint64_t P9N2_EX_CME_SCOM_SICR_SCOM2 = 0x1001203Full;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_SICR_PPE = 0x109010500ull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_SICR_PPE1 = 0x109010518ull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_SICR_PPE2 = 0x109010510ull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_SICR_SCOM = 0x1001203Dull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_SICR_SCOM1 = 0x1001203Eull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_SICR_SCOM2 = 0x1001203Full;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_SICR_PPE = 0x109020500ull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_SICR_PPE1 = 0x109020518ull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_SICR_PPE2 = 0x109020510ull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_SICR_SCOM = 0x1001243Dull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_SICR_SCOM1 = 0x1001243Eull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_SICR_SCOM2 = 0x1001243Full;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_SICR_PPE = 0x10A010500ull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_SICR_PPE1 = 0x10A010518ull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_SICR_PPE2 = 0x10A010510ull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_SICR_SCOM = 0x1101203Dull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_SICR_SCOM1 = 0x1101203Eull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_SICR_SCOM2 = 0x1101203Full;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_SICR_PPE = 0x10A020500ull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_SICR_PPE1 = 0x10A020518ull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_SICR_PPE2 = 0x10A020510ull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_SICR_SCOM = 0x1101243Dull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_SICR_SCOM1 = 0x1101243Eull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_SICR_SCOM2 = 0x1101243Full;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_SICR_PPE = 0x10B010500ull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_SICR_PPE1 = 0x10B010518ull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_SICR_PPE2 = 0x10B010510ull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_SICR_SCOM = 0x1201203Dull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_SICR_SCOM1 = 0x1201203Eull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_SICR_SCOM2 = 0x1201203Full;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_SICR_PPE = 0x10B020500ull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_SICR_PPE1 = 0x10B020518ull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_SICR_PPE2 = 0x10B020510ull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_SICR_SCOM = 0x1201243Dull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_SICR_SCOM1 = 0x1201243Eull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_SICR_SCOM2 = 0x1201243Full;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_SICR_PPE = 0x10C010500ull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_SICR_PPE1 = 0x10C010518ull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_SICR_PPE2 = 0x10C010510ull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_SICR_SCOM = 0x1301203Dull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_SICR_SCOM1 = 0x1301203Eull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_SICR_SCOM2 = 0x1301203Full;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_SICR_PPE = 0x10C020500ull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_SICR_PPE1 = 0x10C020518ull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_SICR_PPE2 = 0x10C020510ull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_SICR_SCOM = 0x1301243Dull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_SICR_SCOM1 = 0x1301243Eull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_SICR_SCOM2 = 0x1301243Full;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_SICR_PPE = 0x10D010500ull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_SICR_PPE1 = 0x10D010518ull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_SICR_PPE2 = 0x10D010510ull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_SICR_SCOM = 0x1401203Dull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_SICR_SCOM1 = 0x1401203Eull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_SICR_SCOM2 = 0x1401203Full;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_SICR_PPE = 0x10D020500ull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_SICR_PPE1 = 0x10D020518ull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_SICR_PPE2 = 0x10D020510ull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_SICR_SCOM = 0x1401243Dull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_SICR_SCOM1 = 0x1401243Eull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_SICR_SCOM2 = 0x1401243Full;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_SICR_PPE = 0x10E010500ull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_SICR_PPE1 = 0x10E010518ull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_SICR_PPE2 = 0x10E010510ull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_SICR_SCOM = 0x1501203Dull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_SICR_SCOM1 = 0x1501203Eull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_SICR_SCOM2 = 0x1501203Full;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_SICR_PPE = 0x10E020500ull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_SICR_PPE1 = 0x10E020518ull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_SICR_PPE2 = 0x10E020510ull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_SICR_SCOM = 0x1501243Dull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_SICR_SCOM1 = 0x1501243Eull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_SICR_SCOM2 = 0x1501243Full;
+
+
+static const uint64_t P9N2_EQ_CME_SCOM_SRTCH0 = 0x10012023ull;
+//DUPS: 10012023,
+static const uint64_t P9N2_EQ_0_CME_SCOM_SRTCH0 = 0x10012023ull;
+//DUPS: 10012023,
+static const uint64_t P9N2_EQ_1_CME_SCOM_SRTCH0 = 0x11012023ull;
+//DUPS: 11012023,
+static const uint64_t P9N2_EQ_2_CME_SCOM_SRTCH0 = 0x12012023ull;
+//DUPS: 12012023,
+static const uint64_t P9N2_EQ_3_CME_SCOM_SRTCH0 = 0x13012023ull;
+//DUPS: 13012023,
+static const uint64_t P9N2_EQ_4_CME_SCOM_SRTCH0 = 0x14012023ull;
+//DUPS: 14012023,
+static const uint64_t P9N2_EQ_5_CME_SCOM_SRTCH0 = 0x15012023ull;
+//DUPS: 15012023,
+static const uint64_t P9N2_EX_CME_SCOM_SRTCH0_PPE = 0x109010420ull;
+
+static const uint64_t P9N2_EX_CME_SCOM_SRTCH0_SCOM = 0x10012023ull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_SRTCH0_PPE = 0x109010420ull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_SRTCH0_SCOM = 0x10012023ull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_SRTCH0_PPE = 0x109020420ull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_SRTCH0_SCOM = 0x10012423ull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_SRTCH0_PPE = 0x10A010420ull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_SRTCH0_SCOM = 0x11012023ull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_SRTCH0_PPE = 0x10A020420ull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_SRTCH0_SCOM = 0x11012423ull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_SRTCH0_PPE = 0x10B010420ull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_SRTCH0_SCOM = 0x12012023ull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_SRTCH0_PPE = 0x10B020420ull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_SRTCH0_SCOM = 0x12012423ull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_SRTCH0_PPE = 0x10C010420ull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_SRTCH0_SCOM = 0x13012023ull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_SRTCH0_PPE = 0x10C020420ull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_SRTCH0_SCOM = 0x13012423ull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_SRTCH0_PPE = 0x10D010420ull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_SRTCH0_SCOM = 0x14012023ull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_SRTCH0_PPE = 0x10D020420ull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_SRTCH0_SCOM = 0x14012423ull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_SRTCH0_PPE = 0x10E010420ull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_SRTCH0_SCOM = 0x15012023ull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_SRTCH0_PPE = 0x10E020420ull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_SRTCH0_SCOM = 0x15012423ull;
+
+
+static const uint64_t P9N2_EQ_CME_SCOM_SRTCH1 = 0x10012024ull;
+//DUPS: 10012024,
+static const uint64_t P9N2_EQ_0_CME_SCOM_SRTCH1 = 0x10012024ull;
+//DUPS: 10012024,
+static const uint64_t P9N2_EQ_1_CME_SCOM_SRTCH1 = 0x11012024ull;
+//DUPS: 11012024,
+static const uint64_t P9N2_EQ_2_CME_SCOM_SRTCH1 = 0x12012024ull;
+//DUPS: 12012024,
+static const uint64_t P9N2_EQ_3_CME_SCOM_SRTCH1 = 0x13012024ull;
+//DUPS: 13012024,
+static const uint64_t P9N2_EQ_4_CME_SCOM_SRTCH1 = 0x14012024ull;
+//DUPS: 14012024,
+static const uint64_t P9N2_EQ_5_CME_SCOM_SRTCH1 = 0x15012024ull;
+//DUPS: 15012024,
+static const uint64_t P9N2_EX_CME_SCOM_SRTCH1_PPE = 0x109010440ull;
+
+static const uint64_t P9N2_EX_CME_SCOM_SRTCH1_SCOM = 0x10012024ull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_SRTCH1_PPE = 0x109010440ull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_SRTCH1_SCOM = 0x10012024ull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_SRTCH1_PPE = 0x109020440ull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_SRTCH1_SCOM = 0x10012424ull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_SRTCH1_PPE = 0x10A010440ull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_SRTCH1_SCOM = 0x11012024ull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_SRTCH1_PPE = 0x10A020440ull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_SRTCH1_SCOM = 0x11012424ull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_SRTCH1_PPE = 0x10B010440ull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_SRTCH1_SCOM = 0x12012024ull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_SRTCH1_PPE = 0x10B020440ull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_SRTCH1_SCOM = 0x12012424ull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_SRTCH1_PPE = 0x10C010440ull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_SRTCH1_SCOM = 0x13012024ull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_SRTCH1_PPE = 0x10C020440ull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_SRTCH1_SCOM = 0x13012424ull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_SRTCH1_PPE = 0x10D010440ull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_SRTCH1_SCOM = 0x14012024ull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_SRTCH1_PPE = 0x10D020440ull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_SRTCH1_SCOM = 0x14012424ull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_SRTCH1_PPE = 0x10E010440ull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_SRTCH1_SCOM = 0x15012024ull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_SRTCH1_PPE = 0x10E020440ull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_SRTCH1_SCOM = 0x15012424ull;
+
+
+static const uint64_t P9N2_EQ_CME_SCOM_VCCR = 0x1001202Cull;
+//DUPS: 1001202C,
+static const uint64_t P9N2_EQ_0_CME_SCOM_VCCR = 0x1001202Cull;
+//DUPS: 1001202C,
+static const uint64_t P9N2_EQ_1_CME_SCOM_VCCR = 0x1101202Cull;
+//DUPS: 1101202C,
+static const uint64_t P9N2_EQ_2_CME_SCOM_VCCR = 0x1201202Cull;
+//DUPS: 1201202C,
+static const uint64_t P9N2_EQ_3_CME_SCOM_VCCR = 0x1301202Cull;
+//DUPS: 1301202C,
+static const uint64_t P9N2_EQ_4_CME_SCOM_VCCR = 0x1401202Cull;
+//DUPS: 1401202C,
+static const uint64_t P9N2_EQ_5_CME_SCOM_VCCR = 0x1501202Cull;
+//DUPS: 1501202C,
+static const uint64_t P9N2_EX_CME_SCOM_VCCR_PPE = 0x109010680ull;
+
+static const uint64_t P9N2_EX_CME_SCOM_VCCR_SCOM = 0x1001202Cull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_VCCR_PPE = 0x109010680ull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_VCCR_SCOM = 0x1001202Cull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_VCCR_PPE = 0x109020680ull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_VCCR_SCOM = 0x1001242Cull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_VCCR_PPE = 0x10A010680ull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_VCCR_SCOM = 0x1101202Cull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_VCCR_PPE = 0x10A020680ull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_VCCR_SCOM = 0x1101242Cull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_VCCR_PPE = 0x10B010680ull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_VCCR_SCOM = 0x1201202Cull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_VCCR_PPE = 0x10B020680ull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_VCCR_SCOM = 0x1201242Cull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_VCCR_PPE = 0x10C010680ull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_VCCR_SCOM = 0x1301202Cull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_VCCR_PPE = 0x10C020680ull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_VCCR_SCOM = 0x1301242Cull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_VCCR_PPE = 0x10D010680ull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_VCCR_SCOM = 0x1401202Cull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_VCCR_PPE = 0x10D020680ull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_VCCR_SCOM = 0x1401242Cull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_VCCR_PPE = 0x10E010680ull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_VCCR_SCOM = 0x1501202Cull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_VCCR_PPE = 0x10E020680ull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_VCCR_SCOM = 0x1501242Cull;
+
+
+static const uint64_t P9N2_EQ_CME_SCOM_VCTR = 0x10012039ull;
+//DUPS: 10012039,
+static const uint64_t P9N2_EQ_0_CME_SCOM_VCTR = 0x10012039ull;
+//DUPS: 10012039,
+static const uint64_t P9N2_EQ_1_CME_SCOM_VCTR = 0x11012039ull;
+//DUPS: 11012039,
+static const uint64_t P9N2_EQ_2_CME_SCOM_VCTR = 0x12012039ull;
+//DUPS: 12012039,
+static const uint64_t P9N2_EQ_3_CME_SCOM_VCTR = 0x13012039ull;
+//DUPS: 13012039,
+static const uint64_t P9N2_EQ_4_CME_SCOM_VCTR = 0x14012039ull;
+//DUPS: 14012039,
+static const uint64_t P9N2_EQ_5_CME_SCOM_VCTR = 0x15012039ull;
+//DUPS: 15012039,
+static const uint64_t P9N2_EX_CME_SCOM_VCTR = 0x10012039ull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_VCTR = 0x10012039ull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_VCTR = 0x10012439ull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_VCTR = 0x11012039ull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_VCTR = 0x11012439ull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_VCTR = 0x12012039ull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_VCTR = 0x12012439ull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_VCTR = 0x13012039ull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_VCTR = 0x13012439ull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_VCTR = 0x14012039ull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_VCTR = 0x14012439ull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_VCTR = 0x15012039ull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_VCTR = 0x15012439ull;
+
+
+static const uint64_t P9N2_EQ_CME_SCOM_VDCR = 0x10012035ull;
+//DUPS: 10012035,
+static const uint64_t P9N2_EQ_0_CME_SCOM_VDCR = 0x10012035ull;
+//DUPS: 10012035,
+static const uint64_t P9N2_EQ_1_CME_SCOM_VDCR = 0x11012035ull;
+//DUPS: 11012035,
+static const uint64_t P9N2_EQ_2_CME_SCOM_VDCR = 0x12012035ull;
+//DUPS: 12012035,
+static const uint64_t P9N2_EQ_3_CME_SCOM_VDCR = 0x13012035ull;
+//DUPS: 13012035,
+static const uint64_t P9N2_EQ_4_CME_SCOM_VDCR = 0x14012035ull;
+//DUPS: 14012035,
+static const uint64_t P9N2_EQ_5_CME_SCOM_VDCR = 0x15012035ull;
+//DUPS: 15012035,
+static const uint64_t P9N2_EX_CME_SCOM_VDCR_PPE = 0x109010600ull;
+
+static const uint64_t P9N2_EX_CME_SCOM_VDCR_SCOM = 0x10012035ull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_VDCR_PPE = 0x109010600ull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_VDCR_SCOM = 0x10012035ull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_VDCR_PPE = 0x109020600ull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_VDCR_SCOM = 0x10012435ull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_VDCR_PPE = 0x10A010600ull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_VDCR_SCOM = 0x11012035ull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_VDCR_PPE = 0x10A020600ull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_VDCR_SCOM = 0x11012435ull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_VDCR_PPE = 0x10B010600ull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_VDCR_SCOM = 0x12012035ull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_VDCR_PPE = 0x10B020600ull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_VDCR_SCOM = 0x12012435ull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_VDCR_PPE = 0x10C010600ull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_VDCR_SCOM = 0x13012035ull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_VDCR_PPE = 0x10C020600ull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_VDCR_SCOM = 0x13012435ull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_VDCR_PPE = 0x10D010600ull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_VDCR_SCOM = 0x14012035ull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_VDCR_PPE = 0x10D020600ull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_VDCR_SCOM = 0x14012435ull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_VDCR_PPE = 0x10E010600ull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_VDCR_SCOM = 0x15012035ull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_VDCR_PPE = 0x10E020600ull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_VDCR_SCOM = 0x15012435ull;
+
+
+static const uint64_t P9N2_EQ_CME_SCOM_VDSR = 0x10012037ull;
+//DUPS: 10012037,
+static const uint64_t P9N2_EQ_0_CME_SCOM_VDSR = 0x10012037ull;
+//DUPS: 10012037,
+static const uint64_t P9N2_EQ_1_CME_SCOM_VDSR = 0x11012037ull;
+//DUPS: 11012037,
+static const uint64_t P9N2_EQ_2_CME_SCOM_VDSR = 0x12012037ull;
+//DUPS: 12012037,
+static const uint64_t P9N2_EQ_3_CME_SCOM_VDSR = 0x13012037ull;
+//DUPS: 13012037,
+static const uint64_t P9N2_EQ_4_CME_SCOM_VDSR = 0x14012037ull;
+//DUPS: 14012037,
+static const uint64_t P9N2_EQ_5_CME_SCOM_VDSR = 0x15012037ull;
+//DUPS: 15012037,
+static const uint64_t P9N2_EX_CME_SCOM_VDSR_PPE = 0x109010640ull;
+
+static const uint64_t P9N2_EX_CME_SCOM_VDSR_SCOM = 0x10012037ull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_VDSR_PPE = 0x109010640ull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_VDSR_SCOM = 0x10012037ull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_VDSR_PPE = 0x109020640ull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_VDSR_SCOM = 0x10012437ull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_VDSR_PPE = 0x10A010640ull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_VDSR_SCOM = 0x11012037ull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_VDSR_PPE = 0x10A020640ull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_VDSR_SCOM = 0x11012437ull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_VDSR_PPE = 0x10B010640ull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_VDSR_SCOM = 0x12012037ull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_VDSR_PPE = 0x10B020640ull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_VDSR_SCOM = 0x12012437ull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_VDSR_PPE = 0x10C010640ull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_VDSR_SCOM = 0x13012037ull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_VDSR_PPE = 0x10C020640ull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_VDSR_SCOM = 0x13012437ull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_VDSR_PPE = 0x10D010640ull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_VDSR_SCOM = 0x14012037ull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_VDSR_PPE = 0x10D020640ull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_VDSR_SCOM = 0x14012437ull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_VDSR_PPE = 0x10E010640ull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_VDSR_SCOM = 0x15012037ull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_VDSR_PPE = 0x10E020640ull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_VDSR_SCOM = 0x15012437ull;
+
+
+static const uint64_t P9N2_EQ_CME_SCOM_VECR = 0x10012038ull;
+//DUPS: 10012038,
+static const uint64_t P9N2_EQ_0_CME_SCOM_VECR = 0x10012038ull;
+//DUPS: 10012038,
+static const uint64_t P9N2_EQ_1_CME_SCOM_VECR = 0x11012038ull;
+//DUPS: 11012038,
+static const uint64_t P9N2_EQ_2_CME_SCOM_VECR = 0x12012038ull;
+//DUPS: 12012038,
+static const uint64_t P9N2_EQ_3_CME_SCOM_VECR = 0x13012038ull;
+//DUPS: 13012038,
+static const uint64_t P9N2_EQ_4_CME_SCOM_VECR = 0x14012038ull;
+//DUPS: 14012038,
+static const uint64_t P9N2_EQ_5_CME_SCOM_VECR = 0x15012038ull;
+//DUPS: 15012038,
+static const uint64_t P9N2_EX_CME_SCOM_VECR_PPE = 0x109010660ull;
+
+static const uint64_t P9N2_EX_CME_SCOM_VECR_SCOM = 0x10012038ull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_VECR_PPE = 0x109010660ull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_VECR_SCOM = 0x10012038ull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_VECR_PPE = 0x109020660ull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_VECR_SCOM = 0x10012438ull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_VECR_PPE = 0x10A010660ull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_VECR_SCOM = 0x11012038ull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_VECR_PPE = 0x10A020660ull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_VECR_SCOM = 0x11012438ull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_VECR_PPE = 0x10B010660ull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_VECR_SCOM = 0x12012038ull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_VECR_PPE = 0x10B020660ull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_VECR_SCOM = 0x12012438ull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_VECR_PPE = 0x10C010660ull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_VECR_SCOM = 0x13012038ull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_VECR_PPE = 0x10C020660ull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_VECR_SCOM = 0x13012438ull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_VECR_PPE = 0x10D010660ull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_VECR_SCOM = 0x14012038ull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_VECR_PPE = 0x10D020660ull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_VECR_SCOM = 0x14012438ull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_VECR_PPE = 0x10E010660ull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_VECR_SCOM = 0x15012038ull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_VECR_PPE = 0x10E020660ull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_VECR_SCOM = 0x15012438ull;
+
+
+static const uint64_t P9N2_EQ_CME_SCOM_VNCR = 0x10012036ull;
+//DUPS: 10012036,
+static const uint64_t P9N2_EQ_0_CME_SCOM_VNCR = 0x10012036ull;
+//DUPS: 10012036,
+static const uint64_t P9N2_EQ_1_CME_SCOM_VNCR = 0x11012036ull;
+//DUPS: 11012036,
+static const uint64_t P9N2_EQ_2_CME_SCOM_VNCR = 0x12012036ull;
+//DUPS: 12012036,
+static const uint64_t P9N2_EQ_3_CME_SCOM_VNCR = 0x13012036ull;
+//DUPS: 13012036,
+static const uint64_t P9N2_EQ_4_CME_SCOM_VNCR = 0x14012036ull;
+//DUPS: 14012036,
+static const uint64_t P9N2_EQ_5_CME_SCOM_VNCR = 0x15012036ull;
+//DUPS: 15012036,
+static const uint64_t P9N2_EX_CME_SCOM_VNCR_PPE = 0x109010620ull;
+
+static const uint64_t P9N2_EX_CME_SCOM_VNCR_SCOM = 0x10012036ull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_VNCR_PPE = 0x109010620ull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_VNCR_SCOM = 0x10012036ull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_VNCR_PPE = 0x109020620ull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_VNCR_SCOM = 0x10012436ull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_VNCR_PPE = 0x10A010620ull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_VNCR_SCOM = 0x11012036ull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_VNCR_PPE = 0x10A020620ull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_VNCR_SCOM = 0x11012436ull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_VNCR_PPE = 0x10B010620ull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_VNCR_SCOM = 0x12012036ull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_VNCR_PPE = 0x10B020620ull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_VNCR_SCOM = 0x12012436ull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_VNCR_PPE = 0x10C010620ull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_VNCR_SCOM = 0x13012036ull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_VNCR_PPE = 0x10C020620ull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_VNCR_SCOM = 0x13012436ull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_VNCR_PPE = 0x10D010620ull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_VNCR_SCOM = 0x14012036ull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_VNCR_PPE = 0x10D020620ull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_VNCR_SCOM = 0x14012436ull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_VNCR_PPE = 0x10E010620ull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_VNCR_SCOM = 0x15012036ull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_VNCR_PPE = 0x10E020620ull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_VNCR_SCOM = 0x15012436ull;
+
+
+static const uint64_t P9N2_EQ_CME_SCOM_XIPCBMD0 = 0x1001201Cull;
+//DUPS: 1001201C,
+static const uint64_t P9N2_EQ_0_CME_SCOM_XIPCBMD0 = 0x1001201Cull;
+//DUPS: 1001201C,
+static const uint64_t P9N2_EQ_1_CME_SCOM_XIPCBMD0 = 0x1101201Cull;
+//DUPS: 1101201C,
+static const uint64_t P9N2_EQ_2_CME_SCOM_XIPCBMD0 = 0x1201201Cull;
+//DUPS: 1201201C,
+static const uint64_t P9N2_EQ_3_CME_SCOM_XIPCBMD0 = 0x1301201Cull;
+//DUPS: 1301201C,
+static const uint64_t P9N2_EQ_4_CME_SCOM_XIPCBMD0 = 0x1401201Cull;
+//DUPS: 1401201C,
+static const uint64_t P9N2_EQ_5_CME_SCOM_XIPCBMD0 = 0x1501201Cull;
+//DUPS: 1501201C,
+static const uint64_t P9N2_EX_CME_SCOM_XIPCBMD0_PPE = 0x109010580ull;
+
+static const uint64_t P9N2_EX_CME_SCOM_XIPCBMD0_SCOM = 0x1001201Cull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_XIPCBMD0_PPE = 0x109010580ull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_XIPCBMD0_SCOM = 0x1001201Cull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_XIPCBMD0_PPE = 0x109020580ull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_XIPCBMD0_SCOM = 0x1001241Cull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_XIPCBMD0_PPE = 0x10A010580ull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_XIPCBMD0_SCOM = 0x1101201Cull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_XIPCBMD0_PPE = 0x10A020580ull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_XIPCBMD0_SCOM = 0x1101241Cull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_XIPCBMD0_PPE = 0x10B010580ull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_XIPCBMD0_SCOM = 0x1201201Cull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_XIPCBMD0_PPE = 0x10B020580ull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_XIPCBMD0_SCOM = 0x1201241Cull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_XIPCBMD0_PPE = 0x10C010580ull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_XIPCBMD0_SCOM = 0x1301201Cull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_XIPCBMD0_PPE = 0x10C020580ull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_XIPCBMD0_SCOM = 0x1301241Cull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_XIPCBMD0_PPE = 0x10D010580ull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_XIPCBMD0_SCOM = 0x1401201Cull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_XIPCBMD0_PPE = 0x10D020580ull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_XIPCBMD0_SCOM = 0x1401241Cull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_XIPCBMD0_PPE = 0x10E010580ull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_XIPCBMD0_SCOM = 0x1501201Cull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_XIPCBMD0_PPE = 0x10E020580ull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_XIPCBMD0_SCOM = 0x1501241Cull;
+
+
+static const uint64_t P9N2_EQ_CME_SCOM_XIPCBMD1 = 0x1001201Dull;
+//DUPS: 1001201D,
+static const uint64_t P9N2_EQ_0_CME_SCOM_XIPCBMD1 = 0x1001201Dull;
+//DUPS: 1001201D,
+static const uint64_t P9N2_EQ_1_CME_SCOM_XIPCBMD1 = 0x1101201Dull;
+//DUPS: 1101201D,
+static const uint64_t P9N2_EQ_2_CME_SCOM_XIPCBMD1 = 0x1201201Dull;
+//DUPS: 1201201D,
+static const uint64_t P9N2_EQ_3_CME_SCOM_XIPCBMD1 = 0x1301201Dull;
+//DUPS: 1301201D,
+static const uint64_t P9N2_EQ_4_CME_SCOM_XIPCBMD1 = 0x1401201Dull;
+//DUPS: 1401201D,
+static const uint64_t P9N2_EQ_5_CME_SCOM_XIPCBMD1 = 0x1501201Dull;
+//DUPS: 1501201D,
+static const uint64_t P9N2_EX_CME_SCOM_XIPCBMD1_PPE = 0x1090105A0ull;
+
+static const uint64_t P9N2_EX_CME_SCOM_XIPCBMD1_SCOM = 0x1001201Dull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_XIPCBMD1_PPE = 0x1090105A0ull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_XIPCBMD1_SCOM = 0x1001201Dull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_XIPCBMD1_PPE = 0x1090205A0ull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_XIPCBMD1_SCOM = 0x1001241Dull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_XIPCBMD1_PPE = 0x10A0105A0ull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_XIPCBMD1_SCOM = 0x1101201Dull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_XIPCBMD1_PPE = 0x10A0205A0ull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_XIPCBMD1_SCOM = 0x1101241Dull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_XIPCBMD1_PPE = 0x10B0105A0ull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_XIPCBMD1_SCOM = 0x1201201Dull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_XIPCBMD1_PPE = 0x10B0205A0ull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_XIPCBMD1_SCOM = 0x1201241Dull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_XIPCBMD1_PPE = 0x10C0105A0ull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_XIPCBMD1_SCOM = 0x1301201Dull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_XIPCBMD1_PPE = 0x10C0205A0ull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_XIPCBMD1_SCOM = 0x1301241Dull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_XIPCBMD1_PPE = 0x10D0105A0ull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_XIPCBMD1_SCOM = 0x1401201Dull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_XIPCBMD1_PPE = 0x10D0205A0ull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_XIPCBMD1_SCOM = 0x1401241Dull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_XIPCBMD1_PPE = 0x10E0105A0ull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_XIPCBMD1_SCOM = 0x1501201Dull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_XIPCBMD1_PPE = 0x10E0205A0ull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_XIPCBMD1_SCOM = 0x1501241Dull;
+
+
+static const uint64_t P9N2_EQ_CME_SCOM_XIPCBMI0 = 0x1001201Eull;
+//DUPS: 1001201E,
+static const uint64_t P9N2_EQ_0_CME_SCOM_XIPCBMI0 = 0x1001201Eull;
+//DUPS: 1001201E,
+static const uint64_t P9N2_EQ_1_CME_SCOM_XIPCBMI0 = 0x1101201Eull;
+//DUPS: 1101201E,
+static const uint64_t P9N2_EQ_2_CME_SCOM_XIPCBMI0 = 0x1201201Eull;
+//DUPS: 1201201E,
+static const uint64_t P9N2_EQ_3_CME_SCOM_XIPCBMI0 = 0x1301201Eull;
+//DUPS: 1301201E,
+static const uint64_t P9N2_EQ_4_CME_SCOM_XIPCBMI0 = 0x1401201Eull;
+//DUPS: 1401201E,
+static const uint64_t P9N2_EQ_5_CME_SCOM_XIPCBMI0 = 0x1501201Eull;
+//DUPS: 1501201E,
+static const uint64_t P9N2_EX_CME_SCOM_XIPCBMI0_PPE = 0x1090105C0ull;
+
+static const uint64_t P9N2_EX_CME_SCOM_XIPCBMI0_SCOM = 0x1001201Eull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_XIPCBMI0_PPE = 0x1090105C0ull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_XIPCBMI0_SCOM = 0x1001201Eull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_XIPCBMI0_PPE = 0x1090205C0ull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_XIPCBMI0_SCOM = 0x1001241Eull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_XIPCBMI0_PPE = 0x10A0105C0ull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_XIPCBMI0_SCOM = 0x1101201Eull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_XIPCBMI0_PPE = 0x10A0205C0ull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_XIPCBMI0_SCOM = 0x1101241Eull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_XIPCBMI0_PPE = 0x10B0105C0ull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_XIPCBMI0_SCOM = 0x1201201Eull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_XIPCBMI0_PPE = 0x10B0205C0ull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_XIPCBMI0_SCOM = 0x1201241Eull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_XIPCBMI0_PPE = 0x10C0105C0ull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_XIPCBMI0_SCOM = 0x1301201Eull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_XIPCBMI0_PPE = 0x10C0205C0ull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_XIPCBMI0_SCOM = 0x1301241Eull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_XIPCBMI0_PPE = 0x10D0105C0ull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_XIPCBMI0_SCOM = 0x1401201Eull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_XIPCBMI0_PPE = 0x10D0205C0ull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_XIPCBMI0_SCOM = 0x1401241Eull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_XIPCBMI0_PPE = 0x10E0105C0ull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_XIPCBMI0_SCOM = 0x1501201Eull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_XIPCBMI0_PPE = 0x10E0205C0ull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_XIPCBMI0_SCOM = 0x1501241Eull;
+
+
+static const uint64_t P9N2_EQ_CME_SCOM_XIPCBMI1 = 0x1001201Full;
+//DUPS: 1001201F,
+static const uint64_t P9N2_EQ_0_CME_SCOM_XIPCBMI1 = 0x1001201Full;
+//DUPS: 1001201F,
+static const uint64_t P9N2_EQ_1_CME_SCOM_XIPCBMI1 = 0x1101201Full;
+//DUPS: 1101201F,
+static const uint64_t P9N2_EQ_2_CME_SCOM_XIPCBMI1 = 0x1201201Full;
+//DUPS: 1201201F,
+static const uint64_t P9N2_EQ_3_CME_SCOM_XIPCBMI1 = 0x1301201Full;
+//DUPS: 1301201F,
+static const uint64_t P9N2_EQ_4_CME_SCOM_XIPCBMI1 = 0x1401201Full;
+//DUPS: 1401201F,
+static const uint64_t P9N2_EQ_5_CME_SCOM_XIPCBMI1 = 0x1501201Full;
+//DUPS: 1501201F,
+static const uint64_t P9N2_EX_CME_SCOM_XIPCBMI1_PPE = 0x1090105E0ull;
+
+static const uint64_t P9N2_EX_CME_SCOM_XIPCBMI1_SCOM = 0x1001201Full;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_XIPCBMI1_PPE = 0x1090105E0ull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_XIPCBMI1_SCOM = 0x1001201Full;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_XIPCBMI1_PPE = 0x1090205E0ull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_XIPCBMI1_SCOM = 0x1001241Full;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_XIPCBMI1_PPE = 0x10A0105E0ull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_XIPCBMI1_SCOM = 0x1101201Full;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_XIPCBMI1_PPE = 0x10A0205E0ull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_XIPCBMI1_SCOM = 0x1101241Full;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_XIPCBMI1_PPE = 0x10B0105E0ull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_XIPCBMI1_SCOM = 0x1201201Full;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_XIPCBMI1_PPE = 0x10B0205E0ull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_XIPCBMI1_SCOM = 0x1201241Full;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_XIPCBMI1_PPE = 0x10C0105E0ull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_XIPCBMI1_SCOM = 0x1301201Full;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_XIPCBMI1_PPE = 0x10C0205E0ull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_XIPCBMI1_SCOM = 0x1301241Full;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_XIPCBMI1_PPE = 0x10D0105E0ull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_XIPCBMI1_SCOM = 0x1401201Full;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_XIPCBMI1_PPE = 0x10D0205E0ull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_XIPCBMI1_SCOM = 0x1401241Full;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_XIPCBMI1_PPE = 0x10E0105E0ull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_XIPCBMI1_SCOM = 0x1501201Full;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_XIPCBMI1_PPE = 0x10E0205E0ull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_XIPCBMI1_SCOM = 0x1501241Full;
+
+
+static const uint64_t P9N2_EQ_CME_SCOM_XIPCBQ0 = 0x1001201Aull;
+//DUPS: 1001201A,
+static const uint64_t P9N2_EQ_0_CME_SCOM_XIPCBQ0 = 0x1001201Aull;
+//DUPS: 1001201A,
+static const uint64_t P9N2_EQ_1_CME_SCOM_XIPCBQ0 = 0x1101201Aull;
+//DUPS: 1101201A,
+static const uint64_t P9N2_EQ_2_CME_SCOM_XIPCBQ0 = 0x1201201Aull;
+//DUPS: 1201201A,
+static const uint64_t P9N2_EQ_3_CME_SCOM_XIPCBQ0 = 0x1301201Aull;
+//DUPS: 1301201A,
+static const uint64_t P9N2_EQ_4_CME_SCOM_XIPCBQ0 = 0x1401201Aull;
+//DUPS: 1401201A,
+static const uint64_t P9N2_EQ_5_CME_SCOM_XIPCBQ0 = 0x1501201Aull;
+//DUPS: 1501201A,
+static const uint64_t P9N2_EX_CME_SCOM_XIPCBQ0 = 0x1001201Aull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_XIPCBQ0 = 0x1001201Aull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_XIPCBQ0 = 0x1001241Aull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_XIPCBQ0 = 0x1101201Aull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_XIPCBQ0 = 0x1101241Aull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_XIPCBQ0 = 0x1201201Aull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_XIPCBQ0 = 0x1201241Aull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_XIPCBQ0 = 0x1301201Aull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_XIPCBQ0 = 0x1301241Aull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_XIPCBQ0 = 0x1401201Aull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_XIPCBQ0 = 0x1401241Aull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_XIPCBQ0 = 0x1501201Aull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_XIPCBQ0 = 0x1501241Aull;
+
+
+static const uint64_t P9N2_EQ_CME_SCOM_XIPCBQ1 = 0x1001201Bull;
+//DUPS: 1001201B,
+static const uint64_t P9N2_EQ_0_CME_SCOM_XIPCBQ1 = 0x1001201Bull;
+//DUPS: 1001201B,
+static const uint64_t P9N2_EQ_1_CME_SCOM_XIPCBQ1 = 0x1101201Bull;
+//DUPS: 1101201B,
+static const uint64_t P9N2_EQ_2_CME_SCOM_XIPCBQ1 = 0x1201201Bull;
+//DUPS: 1201201B,
+static const uint64_t P9N2_EQ_3_CME_SCOM_XIPCBQ1 = 0x1301201Bull;
+//DUPS: 1301201B,
+static const uint64_t P9N2_EQ_4_CME_SCOM_XIPCBQ1 = 0x1401201Bull;
+//DUPS: 1401201B,
+static const uint64_t P9N2_EQ_5_CME_SCOM_XIPCBQ1 = 0x1501201Bull;
+//DUPS: 1501201B,
+static const uint64_t P9N2_EX_CME_SCOM_XIPCBQ1 = 0x1001201Bull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_XIPCBQ1 = 0x1001201Bull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_XIPCBQ1 = 0x1001241Bull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_XIPCBQ1 = 0x1101201Bull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_XIPCBQ1 = 0x1101241Bull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_XIPCBQ1 = 0x1201201Bull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_XIPCBQ1 = 0x1201241Bull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_XIPCBQ1 = 0x1301201Bull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_XIPCBQ1 = 0x1301241Bull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_XIPCBQ1 = 0x1401201Bull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_XIPCBQ1 = 0x1401241Bull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_XIPCBQ1 = 0x1501201Bull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_XIPCBQ1 = 0x1501241Bull;
+
+
+static const uint64_t P9N2_EQ_CME_SCOM_XISIB = 0x10012016ull;
+//DUPS: 10012016,
+static const uint64_t P9N2_EQ_0_CME_SCOM_XISIB = 0x10012016ull;
+//DUPS: 10012016,
+static const uint64_t P9N2_EQ_1_CME_SCOM_XISIB = 0x11012016ull;
+//DUPS: 11012016,
+static const uint64_t P9N2_EQ_2_CME_SCOM_XISIB = 0x12012016ull;
+//DUPS: 12012016,
+static const uint64_t P9N2_EQ_3_CME_SCOM_XISIB = 0x13012016ull;
+//DUPS: 13012016,
+static const uint64_t P9N2_EQ_4_CME_SCOM_XISIB = 0x14012016ull;
+//DUPS: 14012016,
+static const uint64_t P9N2_EQ_5_CME_SCOM_XISIB = 0x15012016ull;
+//DUPS: 15012016,
+static const uint64_t P9N2_EX_CME_SCOM_XISIB = 0x10012016ull;
+
+static const uint64_t P9N2_EX_0_CME_SCOM_XISIB = 0x10012016ull;
+
+static const uint64_t P9N2_EX_1_CME_SCOM_XISIB = 0x10012416ull;
+
+static const uint64_t P9N2_EX_2_CME_SCOM_XISIB = 0x11012016ull;
+
+static const uint64_t P9N2_EX_3_CME_SCOM_XISIB = 0x11012416ull;
+
+static const uint64_t P9N2_EX_4_CME_SCOM_XISIB = 0x12012016ull;
+
+static const uint64_t P9N2_EX_5_CME_SCOM_XISIB = 0x12012416ull;
+
+static const uint64_t P9N2_EX_6_CME_SCOM_XISIB = 0x13012016ull;
+
+static const uint64_t P9N2_EX_7_CME_SCOM_XISIB = 0x13012416ull;
+
+static const uint64_t P9N2_EX_8_CME_SCOM_XISIB = 0x14012016ull;
+
+static const uint64_t P9N2_EX_9_CME_SCOM_XISIB = 0x14012416ull;
+
+static const uint64_t P9N2_EX_10_CME_SCOM_XISIB = 0x15012016ull;
+
+static const uint64_t P9N2_EX_11_CME_SCOM_XISIB = 0x15012416ull;
+
+
+static const uint64_t P9N2_C_CONTROL_REG = 0x20050012ull;
+
+static const uint64_t P9N2_C_0_CONTROL_REG = 0x20050012ull;
+
+static const uint64_t P9N2_C_1_CONTROL_REG = 0x21050012ull;
+
+static const uint64_t P9N2_C_2_CONTROL_REG = 0x22050012ull;
+
+static const uint64_t P9N2_C_3_CONTROL_REG = 0x23050012ull;
+
+static const uint64_t P9N2_C_4_CONTROL_REG = 0x24050012ull;
+
+static const uint64_t P9N2_C_5_CONTROL_REG = 0x25050012ull;
+
+static const uint64_t P9N2_C_6_CONTROL_REG = 0x26050012ull;
+
+static const uint64_t P9N2_C_7_CONTROL_REG = 0x27050012ull;
+
+static const uint64_t P9N2_C_8_CONTROL_REG = 0x28050012ull;
+
+static const uint64_t P9N2_C_9_CONTROL_REG = 0x29050012ull;
+
+static const uint64_t P9N2_C_10_CONTROL_REG = 0x2A050012ull;
+
+static const uint64_t P9N2_C_11_CONTROL_REG = 0x2B050012ull;
+
+static const uint64_t P9N2_C_12_CONTROL_REG = 0x2C050012ull;
+
+static const uint64_t P9N2_C_13_CONTROL_REG = 0x2D050012ull;
+
+static const uint64_t P9N2_C_14_CONTROL_REG = 0x2E050012ull;
+
+static const uint64_t P9N2_C_15_CONTROL_REG = 0x2F050012ull;
+
+static const uint64_t P9N2_C_16_CONTROL_REG = 0x30050012ull;
+
+static const uint64_t P9N2_C_17_CONTROL_REG = 0x31050012ull;
+
+static const uint64_t P9N2_C_18_CONTROL_REG = 0x32050012ull;
+
+static const uint64_t P9N2_C_19_CONTROL_REG = 0x33050012ull;
+
+static const uint64_t P9N2_C_20_CONTROL_REG = 0x34050012ull;
+
+static const uint64_t P9N2_C_21_CONTROL_REG = 0x35050012ull;
+
+static const uint64_t P9N2_C_22_CONTROL_REG = 0x36050012ull;
+
+static const uint64_t P9N2_C_23_CONTROL_REG = 0x37050012ull;
+
+static const uint64_t P9N2_EQ_CONTROL_REG = 0x10050012ull;
+
+static const uint64_t P9N2_EQ_0_CONTROL_REG = 0x10050012ull;
+
+static const uint64_t P9N2_EQ_1_CONTROL_REG = 0x11050012ull;
+
+static const uint64_t P9N2_EQ_2_CONTROL_REG = 0x12050012ull;
+
+static const uint64_t P9N2_EQ_3_CONTROL_REG = 0x13050012ull;
+
+static const uint64_t P9N2_EQ_4_CONTROL_REG = 0x14050012ull;
+
+static const uint64_t P9N2_EQ_5_CONTROL_REG = 0x15050012ull;
+
+static const uint64_t P9N2_EX_CONTROL_REG = 0x20050012ull;
+//DUPS: 21050012,
+static const uint64_t P9N2_EX_0_CONTROL_REG = 0x20050012ull;
+//DUPS: 21050012,
+static const uint64_t P9N2_EX_1_CONTROL_REG = 0x22050012ull;
+//DUPS: 23050012,
+static const uint64_t P9N2_EX_2_CONTROL_REG = 0x24050012ull;
+//DUPS: 25050012,
+static const uint64_t P9N2_EX_3_CONTROL_REG = 0x26050012ull;
+//DUPS: 27050012,
+static const uint64_t P9N2_EX_4_CONTROL_REG = 0x28050012ull;
+//DUPS: 29050012,
+static const uint64_t P9N2_EX_5_CONTROL_REG = 0x2A050012ull;
+//DUPS: 2B050012,
+static const uint64_t P9N2_EX_6_CONTROL_REG = 0x2C050012ull;
+//DUPS: 2D050012,
+static const uint64_t P9N2_EX_7_CONTROL_REG = 0x2F050012ull;
+//DUPS: 2F050012,
+static const uint64_t P9N2_EX_8_CONTROL_REG = 0x30050012ull;
+//DUPS: 31050012,
+static const uint64_t P9N2_EX_9_CONTROL_REG = 0x32050012ull;
+//DUPS: 33050012,
+static const uint64_t P9N2_EX_10_CONTROL_REG = 0x34050012ull;
+//DUPS: 35050012,
+static const uint64_t P9N2_EX_11_CONTROL_REG = 0x36050012ull;
+//DUPS: 37050012,
+
+static const uint64_t P9N2_C_CORE_ACTION0 = 0x20010A46ull;
+
+static const uint64_t P9N2_C_0_CORE_ACTION0 = 0x20010A46ull;
+
+static const uint64_t P9N2_C_1_CORE_ACTION0 = 0x21010A46ull;
+
+static const uint64_t P9N2_C_2_CORE_ACTION0 = 0x22010A46ull;
+
+static const uint64_t P9N2_C_3_CORE_ACTION0 = 0x23010A46ull;
+
+static const uint64_t P9N2_C_4_CORE_ACTION0 = 0x24010A46ull;
+
+static const uint64_t P9N2_C_5_CORE_ACTION0 = 0x25010A46ull;
+
+static const uint64_t P9N2_C_6_CORE_ACTION0 = 0x26010A46ull;
+
+static const uint64_t P9N2_C_7_CORE_ACTION0 = 0x27010A46ull;
+
+static const uint64_t P9N2_C_8_CORE_ACTION0 = 0x28010A46ull;
+
+static const uint64_t P9N2_C_9_CORE_ACTION0 = 0x29010A46ull;
+
+static const uint64_t P9N2_C_10_CORE_ACTION0 = 0x2A010A46ull;
+
+static const uint64_t P9N2_C_11_CORE_ACTION0 = 0x2B010A46ull;
+
+static const uint64_t P9N2_C_12_CORE_ACTION0 = 0x2C010A46ull;
+
+static const uint64_t P9N2_C_13_CORE_ACTION0 = 0x2D010A46ull;
+
+static const uint64_t P9N2_C_14_CORE_ACTION0 = 0x2E010A46ull;
+
+static const uint64_t P9N2_C_15_CORE_ACTION0 = 0x2F010A46ull;
+
+static const uint64_t P9N2_C_16_CORE_ACTION0 = 0x30010A46ull;
+
+static const uint64_t P9N2_C_17_CORE_ACTION0 = 0x31010A46ull;
+
+static const uint64_t P9N2_C_18_CORE_ACTION0 = 0x32010A46ull;
+
+static const uint64_t P9N2_C_19_CORE_ACTION0 = 0x33010A46ull;
+
+static const uint64_t P9N2_C_20_CORE_ACTION0 = 0x34010A46ull;
+
+static const uint64_t P9N2_C_21_CORE_ACTION0 = 0x35010A46ull;
+
+static const uint64_t P9N2_C_22_CORE_ACTION0 = 0x36010A46ull;
+
+static const uint64_t P9N2_C_23_CORE_ACTION0 = 0x37010A46ull;
+
+static const uint64_t P9N2_EX_0_L2_CORE_ACTION0 = 0x20010A46ull;
+//DUPS: 21010A46,
+static const uint64_t P9N2_EX_10_L2_CORE_ACTION0 = 0x34010A46ull;
+//DUPS: 35010A46,
+static const uint64_t P9N2_EX_11_L2_CORE_ACTION0 = 0x36010A46ull;
+//DUPS: 37010A46,
+static const uint64_t P9N2_EX_1_L2_CORE_ACTION0 = 0x22010A46ull;
+//DUPS: 23010A46,
+static const uint64_t P9N2_EX_2_L2_CORE_ACTION0 = 0x24010A46ull;
+//DUPS: 25010A46,
+static const uint64_t P9N2_EX_3_L2_CORE_ACTION0 = 0x26010A46ull;
+//DUPS: 27010A46,
+static const uint64_t P9N2_EX_4_L2_CORE_ACTION0 = 0x28010A46ull;
+//DUPS: 29010A46,
+static const uint64_t P9N2_EX_5_L2_CORE_ACTION0 = 0x2A010A46ull;
+//DUPS: 2B010A46,
+static const uint64_t P9N2_EX_6_L2_CORE_ACTION0 = 0x2C010A46ull;
+//DUPS: 2D010A46,
+static const uint64_t P9N2_EX_7_L2_CORE_ACTION0 = 0x2F010A46ull;
+//DUPS: 2F010A46,
+static const uint64_t P9N2_EX_8_L2_CORE_ACTION0 = 0x30010A46ull;
+//DUPS: 31010A46,
+static const uint64_t P9N2_EX_9_L2_CORE_ACTION0 = 0x32010A46ull;
+//DUPS: 33010A46,
+static const uint64_t P9N2_EX_L2_CORE_ACTION0 = 0x20010A46ull;
+//DUPS: 21010A46,
+
+static const uint64_t P9N2_C_CORE_ACTION1 = 0x20010A47ull;
+
+static const uint64_t P9N2_C_0_CORE_ACTION1 = 0x20010A47ull;
+
+static const uint64_t P9N2_C_1_CORE_ACTION1 = 0x21010A47ull;
+
+static const uint64_t P9N2_C_2_CORE_ACTION1 = 0x22010A47ull;
+
+static const uint64_t P9N2_C_3_CORE_ACTION1 = 0x23010A47ull;
+
+static const uint64_t P9N2_C_4_CORE_ACTION1 = 0x24010A47ull;
+
+static const uint64_t P9N2_C_5_CORE_ACTION1 = 0x25010A47ull;
+
+static const uint64_t P9N2_C_6_CORE_ACTION1 = 0x26010A47ull;
+
+static const uint64_t P9N2_C_7_CORE_ACTION1 = 0x27010A47ull;
+
+static const uint64_t P9N2_C_8_CORE_ACTION1 = 0x28010A47ull;
+
+static const uint64_t P9N2_C_9_CORE_ACTION1 = 0x29010A47ull;
+
+static const uint64_t P9N2_C_10_CORE_ACTION1 = 0x2A010A47ull;
+
+static const uint64_t P9N2_C_11_CORE_ACTION1 = 0x2B010A47ull;
+
+static const uint64_t P9N2_C_12_CORE_ACTION1 = 0x2C010A47ull;
+
+static const uint64_t P9N2_C_13_CORE_ACTION1 = 0x2D010A47ull;
+
+static const uint64_t P9N2_C_14_CORE_ACTION1 = 0x2E010A47ull;
+
+static const uint64_t P9N2_C_15_CORE_ACTION1 = 0x2F010A47ull;
+
+static const uint64_t P9N2_C_16_CORE_ACTION1 = 0x30010A47ull;
+
+static const uint64_t P9N2_C_17_CORE_ACTION1 = 0x31010A47ull;
+
+static const uint64_t P9N2_C_18_CORE_ACTION1 = 0x32010A47ull;
+
+static const uint64_t P9N2_C_19_CORE_ACTION1 = 0x33010A47ull;
+
+static const uint64_t P9N2_C_20_CORE_ACTION1 = 0x34010A47ull;
+
+static const uint64_t P9N2_C_21_CORE_ACTION1 = 0x35010A47ull;
+
+static const uint64_t P9N2_C_22_CORE_ACTION1 = 0x36010A47ull;
+
+static const uint64_t P9N2_C_23_CORE_ACTION1 = 0x37010A47ull;
+
+static const uint64_t P9N2_EX_0_L2_CORE_ACTION1 = 0x20010A47ull;
+//DUPS: 21010A47,
+static const uint64_t P9N2_EX_10_L2_CORE_ACTION1 = 0x34010A47ull;
+//DUPS: 35010A47,
+static const uint64_t P9N2_EX_11_L2_CORE_ACTION1 = 0x36010A47ull;
+//DUPS: 37010A47,
+static const uint64_t P9N2_EX_1_L2_CORE_ACTION1 = 0x22010A47ull;
+//DUPS: 23010A47,
+static const uint64_t P9N2_EX_2_L2_CORE_ACTION1 = 0x24010A47ull;
+//DUPS: 25010A47,
+static const uint64_t P9N2_EX_3_L2_CORE_ACTION1 = 0x26010A47ull;
+//DUPS: 27010A47,
+static const uint64_t P9N2_EX_4_L2_CORE_ACTION1 = 0x28010A47ull;
+//DUPS: 29010A47,
+static const uint64_t P9N2_EX_5_L2_CORE_ACTION1 = 0x2A010A47ull;
+//DUPS: 2B010A47,
+static const uint64_t P9N2_EX_6_L2_CORE_ACTION1 = 0x2C010A47ull;
+//DUPS: 2D010A47,
+static const uint64_t P9N2_EX_7_L2_CORE_ACTION1 = 0x2F010A47ull;
+//DUPS: 2F010A47,
+static const uint64_t P9N2_EX_8_L2_CORE_ACTION1 = 0x30010A47ull;
+//DUPS: 31010A47,
+static const uint64_t P9N2_EX_9_L2_CORE_ACTION1 = 0x32010A47ull;
+//DUPS: 33010A47,
+static const uint64_t P9N2_EX_L2_CORE_ACTION1 = 0x20010A47ull;
+//DUPS: 21010A47,
+
+static const uint64_t P9N2_C_CORE_FIR = 0x20010A40ull;
+
+static const uint64_t P9N2_C_CORE_FIR_AND = 0x20010A41ull;
+
+static const uint64_t P9N2_C_CORE_FIR_OR = 0x20010A42ull;
+
+static const uint64_t P9N2_C_0_CORE_FIR = 0x20010A40ull;
+
+static const uint64_t P9N2_C_0_CORE_FIR_AND = 0x20010A41ull;
+
+static const uint64_t P9N2_C_0_CORE_FIR_OR = 0x20010A42ull;
+
+static const uint64_t P9N2_C_1_CORE_FIR = 0x21010A40ull;
+
+static const uint64_t P9N2_C_1_CORE_FIR_AND = 0x21010A41ull;
+
+static const uint64_t P9N2_C_1_CORE_FIR_OR = 0x21010A42ull;
+
+static const uint64_t P9N2_C_2_CORE_FIR = 0x22010A40ull;
+
+static const uint64_t P9N2_C_2_CORE_FIR_AND = 0x22010A41ull;
+
+static const uint64_t P9N2_C_2_CORE_FIR_OR = 0x22010A42ull;
+
+static const uint64_t P9N2_C_3_CORE_FIR = 0x23010A40ull;
+
+static const uint64_t P9N2_C_3_CORE_FIR_AND = 0x23010A41ull;
+
+static const uint64_t P9N2_C_3_CORE_FIR_OR = 0x23010A42ull;
+
+static const uint64_t P9N2_C_4_CORE_FIR = 0x24010A40ull;
+
+static const uint64_t P9N2_C_4_CORE_FIR_AND = 0x24010A41ull;
+
+static const uint64_t P9N2_C_4_CORE_FIR_OR = 0x24010A42ull;
+
+static const uint64_t P9N2_C_5_CORE_FIR = 0x25010A40ull;
+
+static const uint64_t P9N2_C_5_CORE_FIR_AND = 0x25010A41ull;
+
+static const uint64_t P9N2_C_5_CORE_FIR_OR = 0x25010A42ull;
+
+static const uint64_t P9N2_C_6_CORE_FIR = 0x26010A40ull;
+
+static const uint64_t P9N2_C_6_CORE_FIR_AND = 0x26010A41ull;
+
+static const uint64_t P9N2_C_6_CORE_FIR_OR = 0x26010A42ull;
+
+static const uint64_t P9N2_C_7_CORE_FIR = 0x27010A40ull;
+
+static const uint64_t P9N2_C_7_CORE_FIR_AND = 0x27010A41ull;
+
+static const uint64_t P9N2_C_7_CORE_FIR_OR = 0x27010A42ull;
+
+static const uint64_t P9N2_C_8_CORE_FIR = 0x28010A40ull;
+
+static const uint64_t P9N2_C_8_CORE_FIR_AND = 0x28010A41ull;
+
+static const uint64_t P9N2_C_8_CORE_FIR_OR = 0x28010A42ull;
+
+static const uint64_t P9N2_C_9_CORE_FIR = 0x29010A40ull;
+
+static const uint64_t P9N2_C_9_CORE_FIR_AND = 0x29010A41ull;
+
+static const uint64_t P9N2_C_9_CORE_FIR_OR = 0x29010A42ull;
+
+static const uint64_t P9N2_C_10_CORE_FIR = 0x2A010A40ull;
+
+static const uint64_t P9N2_C_10_CORE_FIR_AND = 0x2A010A41ull;
+
+static const uint64_t P9N2_C_10_CORE_FIR_OR = 0x2A010A42ull;
+
+static const uint64_t P9N2_C_11_CORE_FIR = 0x2B010A40ull;
+
+static const uint64_t P9N2_C_11_CORE_FIR_AND = 0x2B010A41ull;
+
+static const uint64_t P9N2_C_11_CORE_FIR_OR = 0x2B010A42ull;
+
+static const uint64_t P9N2_C_12_CORE_FIR = 0x2C010A40ull;
+
+static const uint64_t P9N2_C_12_CORE_FIR_AND = 0x2C010A41ull;
+
+static const uint64_t P9N2_C_12_CORE_FIR_OR = 0x2C010A42ull;
+
+static const uint64_t P9N2_C_13_CORE_FIR = 0x2D010A40ull;
+
+static const uint64_t P9N2_C_13_CORE_FIR_AND = 0x2D010A41ull;
+
+static const uint64_t P9N2_C_13_CORE_FIR_OR = 0x2D010A42ull;
+
+static const uint64_t P9N2_C_14_CORE_FIR = 0x2E010A40ull;
+
+static const uint64_t P9N2_C_14_CORE_FIR_AND = 0x2E010A41ull;
+
+static const uint64_t P9N2_C_14_CORE_FIR_OR = 0x2E010A42ull;
+
+static const uint64_t P9N2_C_15_CORE_FIR = 0x2F010A40ull;
+
+static const uint64_t P9N2_C_15_CORE_FIR_AND = 0x2F010A41ull;
+
+static const uint64_t P9N2_C_15_CORE_FIR_OR = 0x2F010A42ull;
+
+static const uint64_t P9N2_C_16_CORE_FIR = 0x30010A40ull;
+
+static const uint64_t P9N2_C_16_CORE_FIR_AND = 0x30010A41ull;
+
+static const uint64_t P9N2_C_16_CORE_FIR_OR = 0x30010A42ull;
+
+static const uint64_t P9N2_C_17_CORE_FIR = 0x31010A40ull;
+
+static const uint64_t P9N2_C_17_CORE_FIR_AND = 0x31010A41ull;
+
+static const uint64_t P9N2_C_17_CORE_FIR_OR = 0x31010A42ull;
+
+static const uint64_t P9N2_C_18_CORE_FIR = 0x32010A40ull;
+
+static const uint64_t P9N2_C_18_CORE_FIR_AND = 0x32010A41ull;
+
+static const uint64_t P9N2_C_18_CORE_FIR_OR = 0x32010A42ull;
+
+static const uint64_t P9N2_C_19_CORE_FIR = 0x33010A40ull;
+
+static const uint64_t P9N2_C_19_CORE_FIR_AND = 0x33010A41ull;
+
+static const uint64_t P9N2_C_19_CORE_FIR_OR = 0x33010A42ull;
+
+static const uint64_t P9N2_C_20_CORE_FIR = 0x34010A40ull;
+
+static const uint64_t P9N2_C_20_CORE_FIR_AND = 0x34010A41ull;
+
+static const uint64_t P9N2_C_20_CORE_FIR_OR = 0x34010A42ull;
+
+static const uint64_t P9N2_C_21_CORE_FIR = 0x35010A40ull;
+
+static const uint64_t P9N2_C_21_CORE_FIR_AND = 0x35010A41ull;
+
+static const uint64_t P9N2_C_21_CORE_FIR_OR = 0x35010A42ull;
+
+static const uint64_t P9N2_C_22_CORE_FIR = 0x36010A40ull;
+
+static const uint64_t P9N2_C_22_CORE_FIR_AND = 0x36010A41ull;
+
+static const uint64_t P9N2_C_22_CORE_FIR_OR = 0x36010A42ull;
+
+static const uint64_t P9N2_C_23_CORE_FIR = 0x37010A40ull;
+
+static const uint64_t P9N2_C_23_CORE_FIR_AND = 0x37010A41ull;
+
+static const uint64_t P9N2_C_23_CORE_FIR_OR = 0x37010A42ull;
+
+static const uint64_t P9N2_EX_0_L2_CORE_FIR = 0x20010A40ull;
+//DUPS: 21010A40,
+static const uint64_t P9N2_EX_0_L2_CORE_FIR_AND = 0x20010A41ull;
+//DUPS: 21010A41,
+static const uint64_t P9N2_EX_0_L2_CORE_FIR_OR = 0x20010A42ull;
+//DUPS: 21010A42,
+static const uint64_t P9N2_EX_10_L2_CORE_FIR = 0x34010A40ull;
+//DUPS: 35010A40,
+static const uint64_t P9N2_EX_10_L2_CORE_FIR_AND = 0x34010A41ull;
+//DUPS: 35010A41,
+static const uint64_t P9N2_EX_10_L2_CORE_FIR_OR = 0x34010A42ull;
+//DUPS: 35010A42,
+static const uint64_t P9N2_EX_11_L2_CORE_FIR = 0x36010A40ull;
+//DUPS: 37010A40,
+static const uint64_t P9N2_EX_11_L2_CORE_FIR_AND = 0x36010A41ull;
+//DUPS: 37010A41,
+static const uint64_t P9N2_EX_11_L2_CORE_FIR_OR = 0x36010A42ull;
+//DUPS: 37010A42,
+static const uint64_t P9N2_EX_1_L2_CORE_FIR = 0x22010A40ull;
+//DUPS: 23010A40,
+static const uint64_t P9N2_EX_1_L2_CORE_FIR_AND = 0x22010A41ull;
+//DUPS: 23010A41,
+static const uint64_t P9N2_EX_1_L2_CORE_FIR_OR = 0x22010A42ull;
+//DUPS: 23010A42,
+static const uint64_t P9N2_EX_2_L2_CORE_FIR = 0x24010A40ull;
+//DUPS: 25010A40,
+static const uint64_t P9N2_EX_2_L2_CORE_FIR_AND = 0x24010A41ull;
+//DUPS: 25010A41,
+static const uint64_t P9N2_EX_2_L2_CORE_FIR_OR = 0x24010A42ull;
+//DUPS: 25010A42,
+static const uint64_t P9N2_EX_3_L2_CORE_FIR = 0x26010A40ull;
+//DUPS: 27010A40,
+static const uint64_t P9N2_EX_3_L2_CORE_FIR_AND = 0x26010A41ull;
+//DUPS: 27010A41,
+static const uint64_t P9N2_EX_3_L2_CORE_FIR_OR = 0x26010A42ull;
+//DUPS: 27010A42,
+static const uint64_t P9N2_EX_4_L2_CORE_FIR = 0x28010A40ull;
+//DUPS: 29010A40,
+static const uint64_t P9N2_EX_4_L2_CORE_FIR_AND = 0x28010A41ull;
+//DUPS: 29010A41,
+static const uint64_t P9N2_EX_4_L2_CORE_FIR_OR = 0x28010A42ull;
+//DUPS: 29010A42,
+static const uint64_t P9N2_EX_5_L2_CORE_FIR = 0x2A010A40ull;
+//DUPS: 2B010A40,
+static const uint64_t P9N2_EX_5_L2_CORE_FIR_AND = 0x2A010A41ull;
+//DUPS: 2B010A41,
+static const uint64_t P9N2_EX_5_L2_CORE_FIR_OR = 0x2A010A42ull;
+//DUPS: 2B010A42,
+static const uint64_t P9N2_EX_6_L2_CORE_FIR = 0x2C010A40ull;
+//DUPS: 2D010A40,
+static const uint64_t P9N2_EX_6_L2_CORE_FIR_AND = 0x2C010A41ull;
+//DUPS: 2D010A41,
+static const uint64_t P9N2_EX_6_L2_CORE_FIR_OR = 0x2C010A42ull;
+//DUPS: 2D010A42,
+static const uint64_t P9N2_EX_7_L2_CORE_FIR = 0x2F010A40ull;
+//DUPS: 2F010A40,
+static const uint64_t P9N2_EX_7_L2_CORE_FIR_AND = 0x2F010A41ull;
+//DUPS: 2F010A41,
+static const uint64_t P9N2_EX_7_L2_CORE_FIR_OR = 0x2F010A42ull;
+//DUPS: 2F010A42,
+static const uint64_t P9N2_EX_8_L2_CORE_FIR = 0x30010A40ull;
+//DUPS: 31010A40,
+static const uint64_t P9N2_EX_8_L2_CORE_FIR_AND = 0x30010A41ull;
+//DUPS: 31010A41,
+static const uint64_t P9N2_EX_8_L2_CORE_FIR_OR = 0x30010A42ull;
+//DUPS: 31010A42,
+static const uint64_t P9N2_EX_9_L2_CORE_FIR = 0x32010A40ull;
+//DUPS: 33010A40,
+static const uint64_t P9N2_EX_9_L2_CORE_FIR_AND = 0x32010A41ull;
+//DUPS: 33010A41,
+static const uint64_t P9N2_EX_9_L2_CORE_FIR_OR = 0x32010A42ull;
+//DUPS: 33010A42,
+static const uint64_t P9N2_EX_L2_CORE_FIR = 0x20010A40ull;
+//DUPS: 21010A40,
+static const uint64_t P9N2_EX_L2_CORE_FIR_AND = 0x20010A41ull;
+//DUPS: 21010A41,
+static const uint64_t P9N2_EX_L2_CORE_FIR_OR = 0x20010A42ull;
+//DUPS: 21010A42,
+
+static const uint64_t P9N2_C_CORE_FIRMASK = 0x20010A43ull;
+
+static const uint64_t P9N2_C_CORE_FIRMASK_AND = 0x20010A44ull;
+
+static const uint64_t P9N2_C_CORE_FIRMASK_OR = 0x20010A45ull;
+
+static const uint64_t P9N2_C_0_CORE_FIRMASK = 0x20010A43ull;
+
+static const uint64_t P9N2_C_0_CORE_FIRMASK_AND = 0x20010A44ull;
+
+static const uint64_t P9N2_C_0_CORE_FIRMASK_OR = 0x20010A45ull;
+
+static const uint64_t P9N2_C_1_CORE_FIRMASK = 0x21010A43ull;
+
+static const uint64_t P9N2_C_1_CORE_FIRMASK_AND = 0x21010A44ull;
+
+static const uint64_t P9N2_C_1_CORE_FIRMASK_OR = 0x21010A45ull;
+
+static const uint64_t P9N2_C_2_CORE_FIRMASK = 0x22010A43ull;
+
+static const uint64_t P9N2_C_2_CORE_FIRMASK_AND = 0x22010A44ull;
+
+static const uint64_t P9N2_C_2_CORE_FIRMASK_OR = 0x22010A45ull;
+
+static const uint64_t P9N2_C_3_CORE_FIRMASK = 0x23010A43ull;
+
+static const uint64_t P9N2_C_3_CORE_FIRMASK_AND = 0x23010A44ull;
+
+static const uint64_t P9N2_C_3_CORE_FIRMASK_OR = 0x23010A45ull;
+
+static const uint64_t P9N2_C_4_CORE_FIRMASK = 0x24010A43ull;
+
+static const uint64_t P9N2_C_4_CORE_FIRMASK_AND = 0x24010A44ull;
+
+static const uint64_t P9N2_C_4_CORE_FIRMASK_OR = 0x24010A45ull;
+
+static const uint64_t P9N2_C_5_CORE_FIRMASK = 0x25010A43ull;
+
+static const uint64_t P9N2_C_5_CORE_FIRMASK_AND = 0x25010A44ull;
+
+static const uint64_t P9N2_C_5_CORE_FIRMASK_OR = 0x25010A45ull;
+
+static const uint64_t P9N2_C_6_CORE_FIRMASK = 0x26010A43ull;
+
+static const uint64_t P9N2_C_6_CORE_FIRMASK_AND = 0x26010A44ull;
+
+static const uint64_t P9N2_C_6_CORE_FIRMASK_OR = 0x26010A45ull;
+
+static const uint64_t P9N2_C_7_CORE_FIRMASK = 0x27010A43ull;
+
+static const uint64_t P9N2_C_7_CORE_FIRMASK_AND = 0x27010A44ull;
+
+static const uint64_t P9N2_C_7_CORE_FIRMASK_OR = 0x27010A45ull;
+
+static const uint64_t P9N2_C_8_CORE_FIRMASK = 0x28010A43ull;
+
+static const uint64_t P9N2_C_8_CORE_FIRMASK_AND = 0x28010A44ull;
+
+static const uint64_t P9N2_C_8_CORE_FIRMASK_OR = 0x28010A45ull;
+
+static const uint64_t P9N2_C_9_CORE_FIRMASK = 0x29010A43ull;
+
+static const uint64_t P9N2_C_9_CORE_FIRMASK_AND = 0x29010A44ull;
+
+static const uint64_t P9N2_C_9_CORE_FIRMASK_OR = 0x29010A45ull;
+
+static const uint64_t P9N2_C_10_CORE_FIRMASK = 0x2A010A43ull;
+
+static const uint64_t P9N2_C_10_CORE_FIRMASK_AND = 0x2A010A44ull;
+
+static const uint64_t P9N2_C_10_CORE_FIRMASK_OR = 0x2A010A45ull;
+
+static const uint64_t P9N2_C_11_CORE_FIRMASK = 0x2B010A43ull;
+
+static const uint64_t P9N2_C_11_CORE_FIRMASK_AND = 0x2B010A44ull;
+
+static const uint64_t P9N2_C_11_CORE_FIRMASK_OR = 0x2B010A45ull;
+
+static const uint64_t P9N2_C_12_CORE_FIRMASK = 0x2C010A43ull;
+
+static const uint64_t P9N2_C_12_CORE_FIRMASK_AND = 0x2C010A44ull;
+
+static const uint64_t P9N2_C_12_CORE_FIRMASK_OR = 0x2C010A45ull;
+
+static const uint64_t P9N2_C_13_CORE_FIRMASK = 0x2D010A43ull;
+
+static const uint64_t P9N2_C_13_CORE_FIRMASK_AND = 0x2D010A44ull;
+
+static const uint64_t P9N2_C_13_CORE_FIRMASK_OR = 0x2D010A45ull;
+
+static const uint64_t P9N2_C_14_CORE_FIRMASK = 0x2E010A43ull;
+
+static const uint64_t P9N2_C_14_CORE_FIRMASK_AND = 0x2E010A44ull;
+
+static const uint64_t P9N2_C_14_CORE_FIRMASK_OR = 0x2E010A45ull;
+
+static const uint64_t P9N2_C_15_CORE_FIRMASK = 0x2F010A43ull;
+
+static const uint64_t P9N2_C_15_CORE_FIRMASK_AND = 0x2F010A44ull;
+
+static const uint64_t P9N2_C_15_CORE_FIRMASK_OR = 0x2F010A45ull;
+
+static const uint64_t P9N2_C_16_CORE_FIRMASK = 0x30010A43ull;
+
+static const uint64_t P9N2_C_16_CORE_FIRMASK_AND = 0x30010A44ull;
+
+static const uint64_t P9N2_C_16_CORE_FIRMASK_OR = 0x30010A45ull;
+
+static const uint64_t P9N2_C_17_CORE_FIRMASK = 0x31010A43ull;
+
+static const uint64_t P9N2_C_17_CORE_FIRMASK_AND = 0x31010A44ull;
+
+static const uint64_t P9N2_C_17_CORE_FIRMASK_OR = 0x31010A45ull;
+
+static const uint64_t P9N2_C_18_CORE_FIRMASK = 0x32010A43ull;
+
+static const uint64_t P9N2_C_18_CORE_FIRMASK_AND = 0x32010A44ull;
+
+static const uint64_t P9N2_C_18_CORE_FIRMASK_OR = 0x32010A45ull;
+
+static const uint64_t P9N2_C_19_CORE_FIRMASK = 0x33010A43ull;
+
+static const uint64_t P9N2_C_19_CORE_FIRMASK_AND = 0x33010A44ull;
+
+static const uint64_t P9N2_C_19_CORE_FIRMASK_OR = 0x33010A45ull;
+
+static const uint64_t P9N2_C_20_CORE_FIRMASK = 0x34010A43ull;
+
+static const uint64_t P9N2_C_20_CORE_FIRMASK_AND = 0x34010A44ull;
+
+static const uint64_t P9N2_C_20_CORE_FIRMASK_OR = 0x34010A45ull;
+
+static const uint64_t P9N2_C_21_CORE_FIRMASK = 0x35010A43ull;
+
+static const uint64_t P9N2_C_21_CORE_FIRMASK_AND = 0x35010A44ull;
+
+static const uint64_t P9N2_C_21_CORE_FIRMASK_OR = 0x35010A45ull;
+
+static const uint64_t P9N2_C_22_CORE_FIRMASK = 0x36010A43ull;
+
+static const uint64_t P9N2_C_22_CORE_FIRMASK_AND = 0x36010A44ull;
+
+static const uint64_t P9N2_C_22_CORE_FIRMASK_OR = 0x36010A45ull;
+
+static const uint64_t P9N2_C_23_CORE_FIRMASK = 0x37010A43ull;
+
+static const uint64_t P9N2_C_23_CORE_FIRMASK_AND = 0x37010A44ull;
+
+static const uint64_t P9N2_C_23_CORE_FIRMASK_OR = 0x37010A45ull;
+
+static const uint64_t P9N2_EX_0_L2_CORE_FIRMASK = 0x20010A43ull;
+//DUPS: 21010A43,
+static const uint64_t P9N2_EX_0_L2_CORE_FIRMASK_AND = 0x20010A44ull;
+//DUPS: 21010A44,
+static const uint64_t P9N2_EX_0_L2_CORE_FIRMASK_OR = 0x20010A45ull;
+//DUPS: 21010A45,
+static const uint64_t P9N2_EX_10_L2_CORE_FIRMASK = 0x34010A43ull;
+//DUPS: 35010A43,
+static const uint64_t P9N2_EX_10_L2_CORE_FIRMASK_AND = 0x34010A44ull;
+//DUPS: 35010A44,
+static const uint64_t P9N2_EX_10_L2_CORE_FIRMASK_OR = 0x34010A45ull;
+//DUPS: 35010A45,
+static const uint64_t P9N2_EX_11_L2_CORE_FIRMASK = 0x36010A43ull;
+//DUPS: 37010A43,
+static const uint64_t P9N2_EX_11_L2_CORE_FIRMASK_AND = 0x36010A44ull;
+//DUPS: 37010A44,
+static const uint64_t P9N2_EX_11_L2_CORE_FIRMASK_OR = 0x36010A45ull;
+//DUPS: 37010A45,
+static const uint64_t P9N2_EX_1_L2_CORE_FIRMASK = 0x22010A43ull;
+//DUPS: 23010A43,
+static const uint64_t P9N2_EX_1_L2_CORE_FIRMASK_AND = 0x22010A44ull;
+//DUPS: 23010A44,
+static const uint64_t P9N2_EX_1_L2_CORE_FIRMASK_OR = 0x22010A45ull;
+//DUPS: 23010A45,
+static const uint64_t P9N2_EX_2_L2_CORE_FIRMASK = 0x24010A43ull;
+//DUPS: 25010A43,
+static const uint64_t P9N2_EX_2_L2_CORE_FIRMASK_AND = 0x24010A44ull;
+//DUPS: 25010A44,
+static const uint64_t P9N2_EX_2_L2_CORE_FIRMASK_OR = 0x24010A45ull;
+//DUPS: 25010A45,
+static const uint64_t P9N2_EX_3_L2_CORE_FIRMASK = 0x26010A43ull;
+//DUPS: 27010A43,
+static const uint64_t P9N2_EX_3_L2_CORE_FIRMASK_AND = 0x26010A44ull;
+//DUPS: 27010A44,
+static const uint64_t P9N2_EX_3_L2_CORE_FIRMASK_OR = 0x26010A45ull;
+//DUPS: 27010A45,
+static const uint64_t P9N2_EX_4_L2_CORE_FIRMASK = 0x28010A43ull;
+//DUPS: 29010A43,
+static const uint64_t P9N2_EX_4_L2_CORE_FIRMASK_AND = 0x28010A44ull;
+//DUPS: 29010A44,
+static const uint64_t P9N2_EX_4_L2_CORE_FIRMASK_OR = 0x28010A45ull;
+//DUPS: 29010A45,
+static const uint64_t P9N2_EX_5_L2_CORE_FIRMASK = 0x2A010A43ull;
+//DUPS: 2B010A43,
+static const uint64_t P9N2_EX_5_L2_CORE_FIRMASK_AND = 0x2A010A44ull;
+//DUPS: 2B010A44,
+static const uint64_t P9N2_EX_5_L2_CORE_FIRMASK_OR = 0x2A010A45ull;
+//DUPS: 2B010A45,
+static const uint64_t P9N2_EX_6_L2_CORE_FIRMASK = 0x2C010A43ull;
+//DUPS: 2D010A43,
+static const uint64_t P9N2_EX_6_L2_CORE_FIRMASK_AND = 0x2C010A44ull;
+//DUPS: 2D010A44,
+static const uint64_t P9N2_EX_6_L2_CORE_FIRMASK_OR = 0x2C010A45ull;
+//DUPS: 2D010A45,
+static const uint64_t P9N2_EX_7_L2_CORE_FIRMASK = 0x2F010A43ull;
+//DUPS: 2F010A43,
+static const uint64_t P9N2_EX_7_L2_CORE_FIRMASK_AND = 0x2F010A44ull;
+//DUPS: 2F010A44,
+static const uint64_t P9N2_EX_7_L2_CORE_FIRMASK_OR = 0x2F010A45ull;
+//DUPS: 2F010A45,
+static const uint64_t P9N2_EX_8_L2_CORE_FIRMASK = 0x30010A43ull;
+//DUPS: 31010A43,
+static const uint64_t P9N2_EX_8_L2_CORE_FIRMASK_AND = 0x30010A44ull;
+//DUPS: 31010A44,
+static const uint64_t P9N2_EX_8_L2_CORE_FIRMASK_OR = 0x30010A45ull;
+//DUPS: 31010A45,
+static const uint64_t P9N2_EX_9_L2_CORE_FIRMASK = 0x32010A43ull;
+//DUPS: 33010A43,
+static const uint64_t P9N2_EX_9_L2_CORE_FIRMASK_AND = 0x32010A44ull;
+//DUPS: 33010A44,
+static const uint64_t P9N2_EX_9_L2_CORE_FIRMASK_OR = 0x32010A45ull;
+//DUPS: 33010A45,
+static const uint64_t P9N2_EX_L2_CORE_FIRMASK = 0x20010A43ull;
+//DUPS: 21010A43,
+static const uint64_t P9N2_EX_L2_CORE_FIRMASK_AND = 0x20010A44ull;
+//DUPS: 21010A44,
+static const uint64_t P9N2_EX_L2_CORE_FIRMASK_OR = 0x20010A45ull;
+//DUPS: 21010A45,
+
+static const uint64_t P9N2_C_CORE_FUSES = 0x20010AA7ull;
+
+static const uint64_t P9N2_C_0_CORE_FUSES = 0x20010AA7ull;
+
+static const uint64_t P9N2_C_1_CORE_FUSES = 0x21010AA7ull;
+
+static const uint64_t P9N2_C_2_CORE_FUSES = 0x22010AA7ull;
+
+static const uint64_t P9N2_C_3_CORE_FUSES = 0x23010AA7ull;
+
+static const uint64_t P9N2_C_4_CORE_FUSES = 0x24010AA7ull;
+
+static const uint64_t P9N2_C_5_CORE_FUSES = 0x25010AA7ull;
+
+static const uint64_t P9N2_C_6_CORE_FUSES = 0x26010AA7ull;
+
+static const uint64_t P9N2_C_7_CORE_FUSES = 0x27010AA7ull;
+
+static const uint64_t P9N2_C_8_CORE_FUSES = 0x28010AA7ull;
+
+static const uint64_t P9N2_C_9_CORE_FUSES = 0x29010AA7ull;
+
+static const uint64_t P9N2_C_10_CORE_FUSES = 0x2A010AA7ull;
+
+static const uint64_t P9N2_C_11_CORE_FUSES = 0x2B010AA7ull;
+
+static const uint64_t P9N2_C_12_CORE_FUSES = 0x2C010AA7ull;
+
+static const uint64_t P9N2_C_13_CORE_FUSES = 0x2D010AA7ull;
+
+static const uint64_t P9N2_C_14_CORE_FUSES = 0x2E010AA7ull;
+
+static const uint64_t P9N2_C_15_CORE_FUSES = 0x2F010AA7ull;
+
+static const uint64_t P9N2_C_16_CORE_FUSES = 0x30010AA7ull;
+
+static const uint64_t P9N2_C_17_CORE_FUSES = 0x31010AA7ull;
+
+static const uint64_t P9N2_C_18_CORE_FUSES = 0x32010AA7ull;
+
+static const uint64_t P9N2_C_19_CORE_FUSES = 0x33010AA7ull;
+
+static const uint64_t P9N2_C_20_CORE_FUSES = 0x34010AA7ull;
+
+static const uint64_t P9N2_C_21_CORE_FUSES = 0x35010AA7ull;
+
+static const uint64_t P9N2_C_22_CORE_FUSES = 0x36010AA7ull;
+
+static const uint64_t P9N2_C_23_CORE_FUSES = 0x37010AA7ull;
+
+static const uint64_t P9N2_EX_0_L2_CORE_FUSES = 0x20010AA7ull;
+//DUPS: 21010AA7,
+static const uint64_t P9N2_EX_10_L2_CORE_FUSES = 0x34010AA7ull;
+//DUPS: 35010AA7,
+static const uint64_t P9N2_EX_11_L2_CORE_FUSES = 0x36010AA7ull;
+//DUPS: 37010AA7,
+static const uint64_t P9N2_EX_1_L2_CORE_FUSES = 0x22010AA7ull;
+//DUPS: 23010AA7,
+static const uint64_t P9N2_EX_2_L2_CORE_FUSES = 0x24010AA7ull;
+//DUPS: 25010AA7,
+static const uint64_t P9N2_EX_3_L2_CORE_FUSES = 0x26010AA7ull;
+//DUPS: 27010AA7,
+static const uint64_t P9N2_EX_4_L2_CORE_FUSES = 0x28010AA7ull;
+//DUPS: 29010AA7,
+static const uint64_t P9N2_EX_5_L2_CORE_FUSES = 0x2A010AA7ull;
+//DUPS: 2B010AA7,
+static const uint64_t P9N2_EX_6_L2_CORE_FUSES = 0x2C010AA7ull;
+//DUPS: 2D010AA7,
+static const uint64_t P9N2_EX_7_L2_CORE_FUSES = 0x2F010AA7ull;
+//DUPS: 2F010AA7,
+static const uint64_t P9N2_EX_8_L2_CORE_FUSES = 0x30010AA7ull;
+//DUPS: 31010AA7,
+static const uint64_t P9N2_EX_9_L2_CORE_FUSES = 0x32010AA7ull;
+//DUPS: 33010AA7,
+static const uint64_t P9N2_EX_L2_CORE_FUSES = 0x20010AA7ull;
+//DUPS: 21010AA7,
+
+static const uint64_t P9N2_C_CORE_THREAD_STATE = 0x20010AB3ull;
+
+static const uint64_t P9N2_C_0_CORE_THREAD_STATE = 0x20010AB3ull;
+
+static const uint64_t P9N2_C_1_CORE_THREAD_STATE = 0x21010AB3ull;
+
+static const uint64_t P9N2_C_2_CORE_THREAD_STATE = 0x22010AB3ull;
+
+static const uint64_t P9N2_C_3_CORE_THREAD_STATE = 0x23010AB3ull;
+
+static const uint64_t P9N2_C_4_CORE_THREAD_STATE = 0x24010AB3ull;
+
+static const uint64_t P9N2_C_5_CORE_THREAD_STATE = 0x25010AB3ull;
+
+static const uint64_t P9N2_C_6_CORE_THREAD_STATE = 0x26010AB3ull;
+
+static const uint64_t P9N2_C_7_CORE_THREAD_STATE = 0x27010AB3ull;
+
+static const uint64_t P9N2_C_8_CORE_THREAD_STATE = 0x28010AB3ull;
+
+static const uint64_t P9N2_C_9_CORE_THREAD_STATE = 0x29010AB3ull;
+
+static const uint64_t P9N2_C_10_CORE_THREAD_STATE = 0x2A010AB3ull;
+
+static const uint64_t P9N2_C_11_CORE_THREAD_STATE = 0x2B010AB3ull;
+
+static const uint64_t P9N2_C_12_CORE_THREAD_STATE = 0x2C010AB3ull;
+
+static const uint64_t P9N2_C_13_CORE_THREAD_STATE = 0x2D010AB3ull;
+
+static const uint64_t P9N2_C_14_CORE_THREAD_STATE = 0x2E010AB3ull;
+
+static const uint64_t P9N2_C_15_CORE_THREAD_STATE = 0x2F010AB3ull;
+
+static const uint64_t P9N2_C_16_CORE_THREAD_STATE = 0x30010AB3ull;
+
+static const uint64_t P9N2_C_17_CORE_THREAD_STATE = 0x31010AB3ull;
+
+static const uint64_t P9N2_C_18_CORE_THREAD_STATE = 0x32010AB3ull;
+
+static const uint64_t P9N2_C_19_CORE_THREAD_STATE = 0x33010AB3ull;
+
+static const uint64_t P9N2_C_20_CORE_THREAD_STATE = 0x34010AB3ull;
+
+static const uint64_t P9N2_C_21_CORE_THREAD_STATE = 0x35010AB3ull;
+
+static const uint64_t P9N2_C_22_CORE_THREAD_STATE = 0x36010AB3ull;
+
+static const uint64_t P9N2_C_23_CORE_THREAD_STATE = 0x37010AB3ull;
+
+static const uint64_t P9N2_EX_0_L2_CORE_THREAD_STATE = 0x20010AB3ull;
+//DUPS: 20010AB3,
+static const uint64_t P9N2_EX_10_L2_CORE_THREAD_STATE = 0x34010AB3ull;
+//DUPS: 34010AB3,
+static const uint64_t P9N2_EX_11_L2_CORE_THREAD_STATE = 0x36010AB3ull;
+//DUPS: 36010AB3,
+static const uint64_t P9N2_EX_1_L2_CORE_THREAD_STATE = 0x22010AB3ull;
+//DUPS: 22010AB3,
+static const uint64_t P9N2_EX_2_L2_CORE_THREAD_STATE = 0x24010AB3ull;
+//DUPS: 24010AB3,
+static const uint64_t P9N2_EX_3_L2_CORE_THREAD_STATE = 0x26010AB3ull;
+//DUPS: 26010AB3,
+static const uint64_t P9N2_EX_4_L2_CORE_THREAD_STATE = 0x28010AB3ull;
+//DUPS: 28010AB3,
+static const uint64_t P9N2_EX_5_L2_CORE_THREAD_STATE = 0x2B010AB3ull;
+//DUPS: 2A010AB3,
+static const uint64_t P9N2_EX_6_L2_CORE_THREAD_STATE = 0x2D010AB3ull;
+//DUPS: 2C010AB3,
+static const uint64_t P9N2_EX_7_L2_CORE_THREAD_STATE = 0x2F010AB3ull;
+//DUPS: 2E010AB3,
+static const uint64_t P9N2_EX_8_L2_CORE_THREAD_STATE = 0x30010AB3ull;
+//DUPS: 30010AB3,
+static const uint64_t P9N2_EX_9_L2_CORE_THREAD_STATE = 0x32010AB3ull;
+//DUPS: 32010AB3,
+static const uint64_t P9N2_EX_L2_CORE_THREAD_STATE = 0x20010AB3ull;
+//DUPS: 20010AB3,
+
+static const uint64_t P9N2_C_CORE_WOF = 0x20010A48ull;
+
+static const uint64_t P9N2_C_0_CORE_WOF = 0x20010A48ull;
+
+static const uint64_t P9N2_C_1_CORE_WOF = 0x21010A48ull;
+
+static const uint64_t P9N2_C_2_CORE_WOF = 0x22010A48ull;
+
+static const uint64_t P9N2_C_3_CORE_WOF = 0x23010A48ull;
+
+static const uint64_t P9N2_C_4_CORE_WOF = 0x24010A48ull;
+
+static const uint64_t P9N2_C_5_CORE_WOF = 0x25010A48ull;
+
+static const uint64_t P9N2_C_6_CORE_WOF = 0x26010A48ull;
+
+static const uint64_t P9N2_C_7_CORE_WOF = 0x27010A48ull;
+
+static const uint64_t P9N2_C_8_CORE_WOF = 0x28010A48ull;
+
+static const uint64_t P9N2_C_9_CORE_WOF = 0x29010A48ull;
+
+static const uint64_t P9N2_C_10_CORE_WOF = 0x2A010A48ull;
+
+static const uint64_t P9N2_C_11_CORE_WOF = 0x2B010A48ull;
+
+static const uint64_t P9N2_C_12_CORE_WOF = 0x2C010A48ull;
+
+static const uint64_t P9N2_C_13_CORE_WOF = 0x2D010A48ull;
+
+static const uint64_t P9N2_C_14_CORE_WOF = 0x2E010A48ull;
+
+static const uint64_t P9N2_C_15_CORE_WOF = 0x2F010A48ull;
+
+static const uint64_t P9N2_C_16_CORE_WOF = 0x30010A48ull;
+
+static const uint64_t P9N2_C_17_CORE_WOF = 0x31010A48ull;
+
+static const uint64_t P9N2_C_18_CORE_WOF = 0x32010A48ull;
+
+static const uint64_t P9N2_C_19_CORE_WOF = 0x33010A48ull;
+
+static const uint64_t P9N2_C_20_CORE_WOF = 0x34010A48ull;
+
+static const uint64_t P9N2_C_21_CORE_WOF = 0x35010A48ull;
+
+static const uint64_t P9N2_C_22_CORE_WOF = 0x36010A48ull;
+
+static const uint64_t P9N2_C_23_CORE_WOF = 0x37010A48ull;
+
+static const uint64_t P9N2_EX_CORE_WOF = 0x20010A48ull;
+//DUPS: 21010A48,
+static const uint64_t P9N2_EX_0_CORE_WOF = 0x20010A48ull;
+//DUPS: 21010A48,
+static const uint64_t P9N2_EX_1_CORE_WOF = 0x22010A48ull;
+//DUPS: 23010A48,
+static const uint64_t P9N2_EX_2_CORE_WOF = 0x24010A48ull;
+//DUPS: 25010A48,
+static const uint64_t P9N2_EX_3_CORE_WOF = 0x26010A48ull;
+//DUPS: 27010A48,
+static const uint64_t P9N2_EX_4_CORE_WOF = 0x28010A48ull;
+//DUPS: 29010A48,
+static const uint64_t P9N2_EX_5_CORE_WOF = 0x2A010A48ull;
+//DUPS: 2B010A48,
+static const uint64_t P9N2_EX_6_CORE_WOF = 0x2C010A48ull;
+//DUPS: 2D010A48,
+static const uint64_t P9N2_EX_7_CORE_WOF = 0x2F010A48ull;
+//DUPS: 2F010A48,
+static const uint64_t P9N2_EX_8_CORE_WOF = 0x30010A48ull;
+//DUPS: 31010A48,
+static const uint64_t P9N2_EX_9_CORE_WOF = 0x32010A48ull;
+//DUPS: 33010A48,
+static const uint64_t P9N2_EX_10_CORE_WOF = 0x34010A48ull;
+//DUPS: 35010A48,
+static const uint64_t P9N2_EX_11_CORE_WOF = 0x36010A48ull;
+//DUPS: 37010A48,
+
+static const uint64_t P9N2_C_CPLT_CONF0 = 0x20000008ull;
+
+static const uint64_t P9N2_C_CPLT_CONF0_OR = 0x20000018ull;
+
+static const uint64_t P9N2_C_CPLT_CONF0_CLEAR = 0x20000028ull;
+
+static const uint64_t P9N2_C_0_CPLT_CONF0 = 0x20000008ull;
+
+static const uint64_t P9N2_C_0_CPLT_CONF0_OR = 0x20000018ull;
+
+static const uint64_t P9N2_C_0_CPLT_CONF0_CLEAR = 0x20000028ull;
+
+static const uint64_t P9N2_C_1_CPLT_CONF0 = 0x21000008ull;
+
+static const uint64_t P9N2_C_1_CPLT_CONF0_OR = 0x21000018ull;
+
+static const uint64_t P9N2_C_1_CPLT_CONF0_CLEAR = 0x21000028ull;
+
+static const uint64_t P9N2_C_2_CPLT_CONF0 = 0x22000008ull;
+
+static const uint64_t P9N2_C_2_CPLT_CONF0_OR = 0x22000018ull;
+
+static const uint64_t P9N2_C_2_CPLT_CONF0_CLEAR = 0x22000028ull;
+
+static const uint64_t P9N2_C_3_CPLT_CONF0 = 0x23000008ull;
+
+static const uint64_t P9N2_C_3_CPLT_CONF0_OR = 0x23000018ull;
+
+static const uint64_t P9N2_C_3_CPLT_CONF0_CLEAR = 0x23000028ull;
+
+static const uint64_t P9N2_C_4_CPLT_CONF0 = 0x24000008ull;
+
+static const uint64_t P9N2_C_4_CPLT_CONF0_OR = 0x24000018ull;
+
+static const uint64_t P9N2_C_4_CPLT_CONF0_CLEAR = 0x24000028ull;
+
+static const uint64_t P9N2_C_5_CPLT_CONF0 = 0x25000008ull;
+
+static const uint64_t P9N2_C_5_CPLT_CONF0_OR = 0x25000018ull;
+
+static const uint64_t P9N2_C_5_CPLT_CONF0_CLEAR = 0x25000028ull;
+
+static const uint64_t P9N2_C_6_CPLT_CONF0 = 0x26000008ull;
+
+static const uint64_t P9N2_C_6_CPLT_CONF0_OR = 0x26000018ull;
+
+static const uint64_t P9N2_C_6_CPLT_CONF0_CLEAR = 0x26000028ull;
+
+static const uint64_t P9N2_C_7_CPLT_CONF0 = 0x27000008ull;
+
+static const uint64_t P9N2_C_7_CPLT_CONF0_OR = 0x27000018ull;
+
+static const uint64_t P9N2_C_7_CPLT_CONF0_CLEAR = 0x27000028ull;
+
+static const uint64_t P9N2_C_8_CPLT_CONF0 = 0x28000008ull;
+
+static const uint64_t P9N2_C_8_CPLT_CONF0_OR = 0x28000018ull;
+
+static const uint64_t P9N2_C_8_CPLT_CONF0_CLEAR = 0x28000028ull;
+
+static const uint64_t P9N2_C_9_CPLT_CONF0 = 0x29000008ull;
+
+static const uint64_t P9N2_C_9_CPLT_CONF0_OR = 0x29000018ull;
+
+static const uint64_t P9N2_C_9_CPLT_CONF0_CLEAR = 0x29000028ull;
+
+static const uint64_t P9N2_C_10_CPLT_CONF0 = 0x2A000008ull;
+
+static const uint64_t P9N2_C_10_CPLT_CONF0_OR = 0x2A000018ull;
+
+static const uint64_t P9N2_C_10_CPLT_CONF0_CLEAR = 0x2A000028ull;
+
+static const uint64_t P9N2_C_11_CPLT_CONF0 = 0x2B000008ull;
+
+static const uint64_t P9N2_C_11_CPLT_CONF0_OR = 0x2B000018ull;
+
+static const uint64_t P9N2_C_11_CPLT_CONF0_CLEAR = 0x2B000028ull;
+
+static const uint64_t P9N2_C_12_CPLT_CONF0 = 0x2C000008ull;
+
+static const uint64_t P9N2_C_12_CPLT_CONF0_OR = 0x2C000018ull;
+
+static const uint64_t P9N2_C_12_CPLT_CONF0_CLEAR = 0x2C000028ull;
+
+static const uint64_t P9N2_C_13_CPLT_CONF0 = 0x2D000008ull;
+
+static const uint64_t P9N2_C_13_CPLT_CONF0_OR = 0x2D000018ull;
+
+static const uint64_t P9N2_C_13_CPLT_CONF0_CLEAR = 0x2D000028ull;
+
+static const uint64_t P9N2_C_14_CPLT_CONF0 = 0x2E000008ull;
+
+static const uint64_t P9N2_C_14_CPLT_CONF0_OR = 0x2E000018ull;
+
+static const uint64_t P9N2_C_14_CPLT_CONF0_CLEAR = 0x2E000028ull;
+
+static const uint64_t P9N2_C_15_CPLT_CONF0 = 0x2F000008ull;
+
+static const uint64_t P9N2_C_15_CPLT_CONF0_OR = 0x2F000018ull;
+
+static const uint64_t P9N2_C_15_CPLT_CONF0_CLEAR = 0x2F000028ull;
+
+static const uint64_t P9N2_C_16_CPLT_CONF0 = 0x30000008ull;
+
+static const uint64_t P9N2_C_16_CPLT_CONF0_OR = 0x30000018ull;
+
+static const uint64_t P9N2_C_16_CPLT_CONF0_CLEAR = 0x30000028ull;
+
+static const uint64_t P9N2_C_17_CPLT_CONF0 = 0x31000008ull;
+
+static const uint64_t P9N2_C_17_CPLT_CONF0_OR = 0x31000018ull;
+
+static const uint64_t P9N2_C_17_CPLT_CONF0_CLEAR = 0x31000028ull;
+
+static const uint64_t P9N2_C_18_CPLT_CONF0 = 0x32000008ull;
+
+static const uint64_t P9N2_C_18_CPLT_CONF0_OR = 0x32000018ull;
+
+static const uint64_t P9N2_C_18_CPLT_CONF0_CLEAR = 0x32000028ull;
+
+static const uint64_t P9N2_C_19_CPLT_CONF0 = 0x33000008ull;
+
+static const uint64_t P9N2_C_19_CPLT_CONF0_OR = 0x33000018ull;
+
+static const uint64_t P9N2_C_19_CPLT_CONF0_CLEAR = 0x33000028ull;
+
+static const uint64_t P9N2_C_20_CPLT_CONF0 = 0x34000008ull;
+
+static const uint64_t P9N2_C_20_CPLT_CONF0_OR = 0x34000018ull;
+
+static const uint64_t P9N2_C_20_CPLT_CONF0_CLEAR = 0x34000028ull;
+
+static const uint64_t P9N2_C_21_CPLT_CONF0 = 0x35000008ull;
+
+static const uint64_t P9N2_C_21_CPLT_CONF0_OR = 0x35000018ull;
+
+static const uint64_t P9N2_C_21_CPLT_CONF0_CLEAR = 0x35000028ull;
+
+static const uint64_t P9N2_C_22_CPLT_CONF0 = 0x36000008ull;
+
+static const uint64_t P9N2_C_22_CPLT_CONF0_OR = 0x36000018ull;
+
+static const uint64_t P9N2_C_22_CPLT_CONF0_CLEAR = 0x36000028ull;
+
+static const uint64_t P9N2_C_23_CPLT_CONF0 = 0x37000008ull;
+
+static const uint64_t P9N2_C_23_CPLT_CONF0_OR = 0x37000018ull;
+
+static const uint64_t P9N2_C_23_CPLT_CONF0_CLEAR = 0x37000028ull;
+
+static const uint64_t P9N2_EQ_CPLT_CONF0 = 0x10000008ull;
+
+static const uint64_t P9N2_EQ_CPLT_CONF0_OR = 0x10000018ull;
+
+static const uint64_t P9N2_EQ_CPLT_CONF0_CLEAR = 0x10000028ull;
+
+static const uint64_t P9N2_EQ_0_CPLT_CONF0 = 0x10000008ull;
+
+static const uint64_t P9N2_EQ_0_CPLT_CONF0_OR = 0x10000018ull;
+
+static const uint64_t P9N2_EQ_0_CPLT_CONF0_CLEAR = 0x10000028ull;
+
+static const uint64_t P9N2_EQ_1_CPLT_CONF0 = 0x11000008ull;
+
+static const uint64_t P9N2_EQ_1_CPLT_CONF0_OR = 0x11000018ull;
+
+static const uint64_t P9N2_EQ_1_CPLT_CONF0_CLEAR = 0x11000028ull;
+
+static const uint64_t P9N2_EQ_2_CPLT_CONF0 = 0x12000008ull;
+
+static const uint64_t P9N2_EQ_2_CPLT_CONF0_OR = 0x12000018ull;
+
+static const uint64_t P9N2_EQ_2_CPLT_CONF0_CLEAR = 0x12000028ull;
+
+static const uint64_t P9N2_EQ_3_CPLT_CONF0 = 0x13000008ull;
+
+static const uint64_t P9N2_EQ_3_CPLT_CONF0_OR = 0x13000018ull;
+
+static const uint64_t P9N2_EQ_3_CPLT_CONF0_CLEAR = 0x13000028ull;
+
+static const uint64_t P9N2_EQ_4_CPLT_CONF0 = 0x14000008ull;
+
+static const uint64_t P9N2_EQ_4_CPLT_CONF0_OR = 0x14000018ull;
+
+static const uint64_t P9N2_EQ_4_CPLT_CONF0_CLEAR = 0x14000028ull;
+
+static const uint64_t P9N2_EQ_5_CPLT_CONF0 = 0x15000008ull;
+
+static const uint64_t P9N2_EQ_5_CPLT_CONF0_OR = 0x15000018ull;
+
+static const uint64_t P9N2_EQ_5_CPLT_CONF0_CLEAR = 0x15000028ull;
+
+static const uint64_t P9N2_EX_CPLT_CONF0 = 0x20000008ull;
+//DUPS: 21000008,
+static const uint64_t P9N2_EX_CPLT_CONF0_OR = 0x20000018ull;
+//DUPS: 21000018,
+static const uint64_t P9N2_EX_CPLT_CONF0_CLEAR = 0x20000028ull;
+//DUPS: 21000028,
+static const uint64_t P9N2_EX_0_CPLT_CONF0 = 0x20000008ull;
+//DUPS: 21000008,
+static const uint64_t P9N2_EX_0_CPLT_CONF0_OR = 0x20000018ull;
+//DUPS: 21000018,
+static const uint64_t P9N2_EX_0_CPLT_CONF0_CLEAR = 0x20000028ull;
+//DUPS: 21000028,
+static const uint64_t P9N2_EX_1_CPLT_CONF0 = 0x22000008ull;
+//DUPS: 23000008,
+static const uint64_t P9N2_EX_1_CPLT_CONF0_OR = 0x22000018ull;
+//DUPS: 23000018,
+static const uint64_t P9N2_EX_1_CPLT_CONF0_CLEAR = 0x22000028ull;
+//DUPS: 23000028,
+static const uint64_t P9N2_EX_2_CPLT_CONF0 = 0x24000008ull;
+//DUPS: 25000008,
+static const uint64_t P9N2_EX_2_CPLT_CONF0_OR = 0x24000018ull;
+//DUPS: 25000018,
+static const uint64_t P9N2_EX_2_CPLT_CONF0_CLEAR = 0x24000028ull;
+//DUPS: 25000028,
+static const uint64_t P9N2_EX_3_CPLT_CONF0 = 0x26000008ull;
+//DUPS: 27000008,
+static const uint64_t P9N2_EX_3_CPLT_CONF0_OR = 0x26000018ull;
+//DUPS: 27000018,
+static const uint64_t P9N2_EX_3_CPLT_CONF0_CLEAR = 0x26000028ull;
+//DUPS: 27000028,
+static const uint64_t P9N2_EX_4_CPLT_CONF0 = 0x28000008ull;
+//DUPS: 29000008,
+static const uint64_t P9N2_EX_4_CPLT_CONF0_OR = 0x28000018ull;
+//DUPS: 29000018,
+static const uint64_t P9N2_EX_4_CPLT_CONF0_CLEAR = 0x28000028ull;
+//DUPS: 29000028,
+static const uint64_t P9N2_EX_5_CPLT_CONF0 = 0x2A000008ull;
+//DUPS: 2B000008,
+static const uint64_t P9N2_EX_5_CPLT_CONF0_OR = 0x2A000018ull;
+//DUPS: 2B000018,
+static const uint64_t P9N2_EX_5_CPLT_CONF0_CLEAR = 0x2A000028ull;
+//DUPS: 2B000028,
+static const uint64_t P9N2_EX_6_CPLT_CONF0 = 0x2C000008ull;
+//DUPS: 2D000008,
+static const uint64_t P9N2_EX_6_CPLT_CONF0_OR = 0x2C000018ull;
+//DUPS: 2D000018,
+static const uint64_t P9N2_EX_6_CPLT_CONF0_CLEAR = 0x2C000028ull;
+//DUPS: 2D000028,
+static const uint64_t P9N2_EX_7_CPLT_CONF0 = 0x2F000008ull;
+//DUPS: 2F000008,
+static const uint64_t P9N2_EX_7_CPLT_CONF0_OR = 0x2F000018ull;
+//DUPS: 2F000018,
+static const uint64_t P9N2_EX_7_CPLT_CONF0_CLEAR = 0x2F000028ull;
+//DUPS: 2F000028,
+static const uint64_t P9N2_EX_8_CPLT_CONF0 = 0x30000008ull;
+//DUPS: 31000008,
+static const uint64_t P9N2_EX_8_CPLT_CONF0_OR = 0x30000018ull;
+//DUPS: 31000018,
+static const uint64_t P9N2_EX_8_CPLT_CONF0_CLEAR = 0x30000028ull;
+//DUPS: 31000028,
+static const uint64_t P9N2_EX_9_CPLT_CONF0 = 0x32000008ull;
+//DUPS: 33000008,
+static const uint64_t P9N2_EX_9_CPLT_CONF0_OR = 0x32000018ull;
+//DUPS: 33000018,
+static const uint64_t P9N2_EX_9_CPLT_CONF0_CLEAR = 0x32000028ull;
+//DUPS: 33000028,
+static const uint64_t P9N2_EX_10_CPLT_CONF0 = 0x34000008ull;
+//DUPS: 35000008,
+static const uint64_t P9N2_EX_10_CPLT_CONF0_OR = 0x34000018ull;
+//DUPS: 35000018,
+static const uint64_t P9N2_EX_10_CPLT_CONF0_CLEAR = 0x34000028ull;
+//DUPS: 35000028,
+static const uint64_t P9N2_EX_11_CPLT_CONF0 = 0x36000008ull;
+//DUPS: 37000008,
+static const uint64_t P9N2_EX_11_CPLT_CONF0_OR = 0x36000018ull;
+//DUPS: 37000018,
+static const uint64_t P9N2_EX_11_CPLT_CONF0_CLEAR = 0x36000028ull;
+//DUPS: 37000028,
+
+static const uint64_t P9N2_C_CPLT_CONF1 = 0x20000009ull;
+
+static const uint64_t P9N2_C_CPLT_CONF1_OR = 0x20000019ull;
+
+static const uint64_t P9N2_C_CPLT_CONF1_CLEAR = 0x20000029ull;
+
+static const uint64_t P9N2_C_0_CPLT_CONF1 = 0x20000009ull;
+
+static const uint64_t P9N2_C_0_CPLT_CONF1_OR = 0x20000019ull;
+
+static const uint64_t P9N2_C_0_CPLT_CONF1_CLEAR = 0x20000029ull;
+
+static const uint64_t P9N2_C_1_CPLT_CONF1 = 0x21000009ull;
+
+static const uint64_t P9N2_C_1_CPLT_CONF1_OR = 0x21000019ull;
+
+static const uint64_t P9N2_C_1_CPLT_CONF1_CLEAR = 0x21000029ull;
+
+static const uint64_t P9N2_C_2_CPLT_CONF1 = 0x22000009ull;
+
+static const uint64_t P9N2_C_2_CPLT_CONF1_OR = 0x22000019ull;
+
+static const uint64_t P9N2_C_2_CPLT_CONF1_CLEAR = 0x22000029ull;
+
+static const uint64_t P9N2_C_3_CPLT_CONF1 = 0x23000009ull;
+
+static const uint64_t P9N2_C_3_CPLT_CONF1_OR = 0x23000019ull;
+
+static const uint64_t P9N2_C_3_CPLT_CONF1_CLEAR = 0x23000029ull;
+
+static const uint64_t P9N2_C_4_CPLT_CONF1 = 0x24000009ull;
+
+static const uint64_t P9N2_C_4_CPLT_CONF1_OR = 0x24000019ull;
+
+static const uint64_t P9N2_C_4_CPLT_CONF1_CLEAR = 0x24000029ull;
+
+static const uint64_t P9N2_C_5_CPLT_CONF1 = 0x25000009ull;
+
+static const uint64_t P9N2_C_5_CPLT_CONF1_OR = 0x25000019ull;
+
+static const uint64_t P9N2_C_5_CPLT_CONF1_CLEAR = 0x25000029ull;
+
+static const uint64_t P9N2_C_6_CPLT_CONF1 = 0x26000009ull;
+
+static const uint64_t P9N2_C_6_CPLT_CONF1_OR = 0x26000019ull;
+
+static const uint64_t P9N2_C_6_CPLT_CONF1_CLEAR = 0x26000029ull;
+
+static const uint64_t P9N2_C_7_CPLT_CONF1 = 0x27000009ull;
+
+static const uint64_t P9N2_C_7_CPLT_CONF1_OR = 0x27000019ull;
+
+static const uint64_t P9N2_C_7_CPLT_CONF1_CLEAR = 0x27000029ull;
+
+static const uint64_t P9N2_C_8_CPLT_CONF1 = 0x28000009ull;
+
+static const uint64_t P9N2_C_8_CPLT_CONF1_OR = 0x28000019ull;
+
+static const uint64_t P9N2_C_8_CPLT_CONF1_CLEAR = 0x28000029ull;
+
+static const uint64_t P9N2_C_9_CPLT_CONF1 = 0x29000009ull;
+
+static const uint64_t P9N2_C_9_CPLT_CONF1_OR = 0x29000019ull;
+
+static const uint64_t P9N2_C_9_CPLT_CONF1_CLEAR = 0x29000029ull;
+
+static const uint64_t P9N2_C_10_CPLT_CONF1 = 0x2A000009ull;
+
+static const uint64_t P9N2_C_10_CPLT_CONF1_OR = 0x2A000019ull;
+
+static const uint64_t P9N2_C_10_CPLT_CONF1_CLEAR = 0x2A000029ull;
+
+static const uint64_t P9N2_C_11_CPLT_CONF1 = 0x2B000009ull;
+
+static const uint64_t P9N2_C_11_CPLT_CONF1_OR = 0x2B000019ull;
+
+static const uint64_t P9N2_C_11_CPLT_CONF1_CLEAR = 0x2B000029ull;
+
+static const uint64_t P9N2_C_12_CPLT_CONF1 = 0x2C000009ull;
+
+static const uint64_t P9N2_C_12_CPLT_CONF1_OR = 0x2C000019ull;
+
+static const uint64_t P9N2_C_12_CPLT_CONF1_CLEAR = 0x2C000029ull;
+
+static const uint64_t P9N2_C_13_CPLT_CONF1 = 0x2D000009ull;
+
+static const uint64_t P9N2_C_13_CPLT_CONF1_OR = 0x2D000019ull;
+
+static const uint64_t P9N2_C_13_CPLT_CONF1_CLEAR = 0x2D000029ull;
+
+static const uint64_t P9N2_C_14_CPLT_CONF1 = 0x2E000009ull;
+
+static const uint64_t P9N2_C_14_CPLT_CONF1_OR = 0x2E000019ull;
+
+static const uint64_t P9N2_C_14_CPLT_CONF1_CLEAR = 0x2E000029ull;
+
+static const uint64_t P9N2_C_15_CPLT_CONF1 = 0x2F000009ull;
+
+static const uint64_t P9N2_C_15_CPLT_CONF1_OR = 0x2F000019ull;
+
+static const uint64_t P9N2_C_15_CPLT_CONF1_CLEAR = 0x2F000029ull;
+
+static const uint64_t P9N2_C_16_CPLT_CONF1 = 0x30000009ull;
+
+static const uint64_t P9N2_C_16_CPLT_CONF1_OR = 0x30000019ull;
+
+static const uint64_t P9N2_C_16_CPLT_CONF1_CLEAR = 0x30000029ull;
+
+static const uint64_t P9N2_C_17_CPLT_CONF1 = 0x31000009ull;
+
+static const uint64_t P9N2_C_17_CPLT_CONF1_OR = 0x31000019ull;
+
+static const uint64_t P9N2_C_17_CPLT_CONF1_CLEAR = 0x31000029ull;
+
+static const uint64_t P9N2_C_18_CPLT_CONF1 = 0x32000009ull;
+
+static const uint64_t P9N2_C_18_CPLT_CONF1_OR = 0x32000019ull;
+
+static const uint64_t P9N2_C_18_CPLT_CONF1_CLEAR = 0x32000029ull;
+
+static const uint64_t P9N2_C_19_CPLT_CONF1 = 0x33000009ull;
+
+static const uint64_t P9N2_C_19_CPLT_CONF1_OR = 0x33000019ull;
+
+static const uint64_t P9N2_C_19_CPLT_CONF1_CLEAR = 0x33000029ull;
+
+static const uint64_t P9N2_C_20_CPLT_CONF1 = 0x34000009ull;
+
+static const uint64_t P9N2_C_20_CPLT_CONF1_OR = 0x34000019ull;
+
+static const uint64_t P9N2_C_20_CPLT_CONF1_CLEAR = 0x34000029ull;
+
+static const uint64_t P9N2_C_21_CPLT_CONF1 = 0x35000009ull;
+
+static const uint64_t P9N2_C_21_CPLT_CONF1_OR = 0x35000019ull;
+
+static const uint64_t P9N2_C_21_CPLT_CONF1_CLEAR = 0x35000029ull;
+
+static const uint64_t P9N2_C_22_CPLT_CONF1 = 0x36000009ull;
+
+static const uint64_t P9N2_C_22_CPLT_CONF1_OR = 0x36000019ull;
+
+static const uint64_t P9N2_C_22_CPLT_CONF1_CLEAR = 0x36000029ull;
+
+static const uint64_t P9N2_C_23_CPLT_CONF1 = 0x37000009ull;
+
+static const uint64_t P9N2_C_23_CPLT_CONF1_OR = 0x37000019ull;
+
+static const uint64_t P9N2_C_23_CPLT_CONF1_CLEAR = 0x37000029ull;
+
+static const uint64_t P9N2_EQ_CPLT_CONF1 = 0x10000009ull;
+
+static const uint64_t P9N2_EQ_CPLT_CONF1_OR = 0x10000019ull;
+
+static const uint64_t P9N2_EQ_CPLT_CONF1_CLEAR = 0x10000029ull;
+
+static const uint64_t P9N2_EQ_0_CPLT_CONF1 = 0x10000009ull;
+
+static const uint64_t P9N2_EQ_0_CPLT_CONF1_OR = 0x10000019ull;
+
+static const uint64_t P9N2_EQ_0_CPLT_CONF1_CLEAR = 0x10000029ull;
+
+static const uint64_t P9N2_EQ_1_CPLT_CONF1 = 0x11000009ull;
+
+static const uint64_t P9N2_EQ_1_CPLT_CONF1_OR = 0x11000019ull;
+
+static const uint64_t P9N2_EQ_1_CPLT_CONF1_CLEAR = 0x11000029ull;
+
+static const uint64_t P9N2_EQ_2_CPLT_CONF1 = 0x12000009ull;
+
+static const uint64_t P9N2_EQ_2_CPLT_CONF1_OR = 0x12000019ull;
+
+static const uint64_t P9N2_EQ_2_CPLT_CONF1_CLEAR = 0x12000029ull;
+
+static const uint64_t P9N2_EQ_3_CPLT_CONF1 = 0x13000009ull;
+
+static const uint64_t P9N2_EQ_3_CPLT_CONF1_OR = 0x13000019ull;
+
+static const uint64_t P9N2_EQ_3_CPLT_CONF1_CLEAR = 0x13000029ull;
+
+static const uint64_t P9N2_EQ_4_CPLT_CONF1 = 0x14000009ull;
+
+static const uint64_t P9N2_EQ_4_CPLT_CONF1_OR = 0x14000019ull;
+
+static const uint64_t P9N2_EQ_4_CPLT_CONF1_CLEAR = 0x14000029ull;
+
+static const uint64_t P9N2_EQ_5_CPLT_CONF1 = 0x15000009ull;
+
+static const uint64_t P9N2_EQ_5_CPLT_CONF1_OR = 0x15000019ull;
+
+static const uint64_t P9N2_EQ_5_CPLT_CONF1_CLEAR = 0x15000029ull;
+
+static const uint64_t P9N2_EX_CPLT_CONF1 = 0x20000009ull;
+//DUPS: 21000009,
+static const uint64_t P9N2_EX_CPLT_CONF1_OR = 0x20000019ull;
+//DUPS: 21000019,
+static const uint64_t P9N2_EX_CPLT_CONF1_CLEAR = 0x20000029ull;
+//DUPS: 21000029,
+static const uint64_t P9N2_EX_0_CPLT_CONF1 = 0x20000009ull;
+//DUPS: 21000009,
+static const uint64_t P9N2_EX_0_CPLT_CONF1_OR = 0x20000019ull;
+//DUPS: 21000019,
+static const uint64_t P9N2_EX_0_CPLT_CONF1_CLEAR = 0x20000029ull;
+//DUPS: 21000029,
+static const uint64_t P9N2_EX_1_CPLT_CONF1 = 0x22000009ull;
+//DUPS: 23000009,
+static const uint64_t P9N2_EX_1_CPLT_CONF1_OR = 0x22000019ull;
+//DUPS: 23000019,
+static const uint64_t P9N2_EX_1_CPLT_CONF1_CLEAR = 0x22000029ull;
+//DUPS: 23000029,
+static const uint64_t P9N2_EX_2_CPLT_CONF1 = 0x24000009ull;
+//DUPS: 25000009,
+static const uint64_t P9N2_EX_2_CPLT_CONF1_OR = 0x24000019ull;
+//DUPS: 25000019,
+static const uint64_t P9N2_EX_2_CPLT_CONF1_CLEAR = 0x24000029ull;
+//DUPS: 25000029,
+static const uint64_t P9N2_EX_3_CPLT_CONF1 = 0x26000009ull;
+//DUPS: 27000009,
+static const uint64_t P9N2_EX_3_CPLT_CONF1_OR = 0x26000019ull;
+//DUPS: 27000019,
+static const uint64_t P9N2_EX_3_CPLT_CONF1_CLEAR = 0x26000029ull;
+//DUPS: 27000029,
+static const uint64_t P9N2_EX_4_CPLT_CONF1 = 0x28000009ull;
+//DUPS: 29000009,
+static const uint64_t P9N2_EX_4_CPLT_CONF1_OR = 0x28000019ull;
+//DUPS: 29000019,
+static const uint64_t P9N2_EX_4_CPLT_CONF1_CLEAR = 0x28000029ull;
+//DUPS: 29000029,
+static const uint64_t P9N2_EX_5_CPLT_CONF1 = 0x2A000009ull;
+//DUPS: 2B000009,
+static const uint64_t P9N2_EX_5_CPLT_CONF1_OR = 0x2A000019ull;
+//DUPS: 2B000019,
+static const uint64_t P9N2_EX_5_CPLT_CONF1_CLEAR = 0x2A000029ull;
+//DUPS: 2B000029,
+static const uint64_t P9N2_EX_6_CPLT_CONF1 = 0x2C000009ull;
+//DUPS: 2D000009,
+static const uint64_t P9N2_EX_6_CPLT_CONF1_OR = 0x2C000019ull;
+//DUPS: 2D000019,
+static const uint64_t P9N2_EX_6_CPLT_CONF1_CLEAR = 0x2C000029ull;
+//DUPS: 2D000029,
+static const uint64_t P9N2_EX_7_CPLT_CONF1 = 0x2F000009ull;
+//DUPS: 2F000009,
+static const uint64_t P9N2_EX_7_CPLT_CONF1_OR = 0x2F000019ull;
+//DUPS: 2F000019,
+static const uint64_t P9N2_EX_7_CPLT_CONF1_CLEAR = 0x2F000029ull;
+//DUPS: 2F000029,
+static const uint64_t P9N2_EX_8_CPLT_CONF1 = 0x30000009ull;
+//DUPS: 31000009,
+static const uint64_t P9N2_EX_8_CPLT_CONF1_OR = 0x30000019ull;
+//DUPS: 31000019,
+static const uint64_t P9N2_EX_8_CPLT_CONF1_CLEAR = 0x30000029ull;
+//DUPS: 31000029,
+static const uint64_t P9N2_EX_9_CPLT_CONF1 = 0x32000009ull;
+//DUPS: 33000009,
+static const uint64_t P9N2_EX_9_CPLT_CONF1_OR = 0x32000019ull;
+//DUPS: 33000019,
+static const uint64_t P9N2_EX_9_CPLT_CONF1_CLEAR = 0x32000029ull;
+//DUPS: 33000029,
+static const uint64_t P9N2_EX_10_CPLT_CONF1 = 0x34000009ull;
+//DUPS: 35000009,
+static const uint64_t P9N2_EX_10_CPLT_CONF1_OR = 0x34000019ull;
+//DUPS: 35000019,
+static const uint64_t P9N2_EX_10_CPLT_CONF1_CLEAR = 0x34000029ull;
+//DUPS: 35000029,
+static const uint64_t P9N2_EX_11_CPLT_CONF1 = 0x36000009ull;
+//DUPS: 37000009,
+static const uint64_t P9N2_EX_11_CPLT_CONF1_OR = 0x36000019ull;
+//DUPS: 37000019,
+static const uint64_t P9N2_EX_11_CPLT_CONF1_CLEAR = 0x36000029ull;
+//DUPS: 37000029,
+
+static const uint64_t P9N2_C_CPLT_CTRL0 = 0x20000000ull;
+
+static const uint64_t P9N2_C_CPLT_CTRL0_OR = 0x20000010ull;
+
+static const uint64_t P9N2_C_CPLT_CTRL0_CLEAR = 0x20000020ull;
+
+static const uint64_t P9N2_C_0_CPLT_CTRL0 = 0x20000000ull;
+
+static const uint64_t P9N2_C_0_CPLT_CTRL0_OR = 0x20000010ull;
+
+static const uint64_t P9N2_C_0_CPLT_CTRL0_CLEAR = 0x20000020ull;
+
+static const uint64_t P9N2_C_1_CPLT_CTRL0 = 0x21000000ull;
+
+static const uint64_t P9N2_C_1_CPLT_CTRL0_OR = 0x21000010ull;
+
+static const uint64_t P9N2_C_1_CPLT_CTRL0_CLEAR = 0x21000020ull;
+
+static const uint64_t P9N2_C_2_CPLT_CTRL0 = 0x22000000ull;
+
+static const uint64_t P9N2_C_2_CPLT_CTRL0_OR = 0x22000010ull;
+
+static const uint64_t P9N2_C_2_CPLT_CTRL0_CLEAR = 0x22000020ull;
+
+static const uint64_t P9N2_C_3_CPLT_CTRL0 = 0x23000000ull;
+
+static const uint64_t P9N2_C_3_CPLT_CTRL0_OR = 0x23000010ull;
+
+static const uint64_t P9N2_C_3_CPLT_CTRL0_CLEAR = 0x23000020ull;
+
+static const uint64_t P9N2_C_4_CPLT_CTRL0 = 0x24000000ull;
+
+static const uint64_t P9N2_C_4_CPLT_CTRL0_OR = 0x24000010ull;
+
+static const uint64_t P9N2_C_4_CPLT_CTRL0_CLEAR = 0x24000020ull;
+
+static const uint64_t P9N2_C_5_CPLT_CTRL0 = 0x25000000ull;
+
+static const uint64_t P9N2_C_5_CPLT_CTRL0_OR = 0x25000010ull;
+
+static const uint64_t P9N2_C_5_CPLT_CTRL0_CLEAR = 0x25000020ull;
+
+static const uint64_t P9N2_C_6_CPLT_CTRL0 = 0x26000000ull;
+
+static const uint64_t P9N2_C_6_CPLT_CTRL0_OR = 0x26000010ull;
+
+static const uint64_t P9N2_C_6_CPLT_CTRL0_CLEAR = 0x26000020ull;
+
+static const uint64_t P9N2_C_7_CPLT_CTRL0 = 0x27000000ull;
+
+static const uint64_t P9N2_C_7_CPLT_CTRL0_OR = 0x27000010ull;
+
+static const uint64_t P9N2_C_7_CPLT_CTRL0_CLEAR = 0x27000020ull;
+
+static const uint64_t P9N2_C_8_CPLT_CTRL0 = 0x28000000ull;
+
+static const uint64_t P9N2_C_8_CPLT_CTRL0_OR = 0x28000010ull;
+
+static const uint64_t P9N2_C_8_CPLT_CTRL0_CLEAR = 0x28000020ull;
+
+static const uint64_t P9N2_C_9_CPLT_CTRL0 = 0x29000000ull;
+
+static const uint64_t P9N2_C_9_CPLT_CTRL0_OR = 0x29000010ull;
+
+static const uint64_t P9N2_C_9_CPLT_CTRL0_CLEAR = 0x29000020ull;
+
+static const uint64_t P9N2_C_10_CPLT_CTRL0 = 0x2A000000ull;
+
+static const uint64_t P9N2_C_10_CPLT_CTRL0_OR = 0x2A000010ull;
+
+static const uint64_t P9N2_C_10_CPLT_CTRL0_CLEAR = 0x2A000020ull;
+
+static const uint64_t P9N2_C_11_CPLT_CTRL0 = 0x2B000000ull;
+
+static const uint64_t P9N2_C_11_CPLT_CTRL0_OR = 0x2B000010ull;
+
+static const uint64_t P9N2_C_11_CPLT_CTRL0_CLEAR = 0x2B000020ull;
+
+static const uint64_t P9N2_C_12_CPLT_CTRL0 = 0x2C000000ull;
+
+static const uint64_t P9N2_C_12_CPLT_CTRL0_OR = 0x2C000010ull;
+
+static const uint64_t P9N2_C_12_CPLT_CTRL0_CLEAR = 0x2C000020ull;
+
+static const uint64_t P9N2_C_13_CPLT_CTRL0 = 0x2D000000ull;
+
+static const uint64_t P9N2_C_13_CPLT_CTRL0_OR = 0x2D000010ull;
+
+static const uint64_t P9N2_C_13_CPLT_CTRL0_CLEAR = 0x2D000020ull;
+
+static const uint64_t P9N2_C_14_CPLT_CTRL0 = 0x2E000000ull;
+
+static const uint64_t P9N2_C_14_CPLT_CTRL0_OR = 0x2E000010ull;
+
+static const uint64_t P9N2_C_14_CPLT_CTRL0_CLEAR = 0x2E000020ull;
+
+static const uint64_t P9N2_C_15_CPLT_CTRL0 = 0x2F000000ull;
+
+static const uint64_t P9N2_C_15_CPLT_CTRL0_OR = 0x2F000010ull;
+
+static const uint64_t P9N2_C_15_CPLT_CTRL0_CLEAR = 0x2F000020ull;
+
+static const uint64_t P9N2_C_16_CPLT_CTRL0 = 0x30000000ull;
+
+static const uint64_t P9N2_C_16_CPLT_CTRL0_OR = 0x30000010ull;
+
+static const uint64_t P9N2_C_16_CPLT_CTRL0_CLEAR = 0x30000020ull;
+
+static const uint64_t P9N2_C_17_CPLT_CTRL0 = 0x31000000ull;
+
+static const uint64_t P9N2_C_17_CPLT_CTRL0_OR = 0x31000010ull;
+
+static const uint64_t P9N2_C_17_CPLT_CTRL0_CLEAR = 0x31000020ull;
+
+static const uint64_t P9N2_C_18_CPLT_CTRL0 = 0x32000000ull;
+
+static const uint64_t P9N2_C_18_CPLT_CTRL0_OR = 0x32000010ull;
+
+static const uint64_t P9N2_C_18_CPLT_CTRL0_CLEAR = 0x32000020ull;
+
+static const uint64_t P9N2_C_19_CPLT_CTRL0 = 0x33000000ull;
+
+static const uint64_t P9N2_C_19_CPLT_CTRL0_OR = 0x33000010ull;
+
+static const uint64_t P9N2_C_19_CPLT_CTRL0_CLEAR = 0x33000020ull;
+
+static const uint64_t P9N2_C_20_CPLT_CTRL0 = 0x34000000ull;
+
+static const uint64_t P9N2_C_20_CPLT_CTRL0_OR = 0x34000010ull;
+
+static const uint64_t P9N2_C_20_CPLT_CTRL0_CLEAR = 0x34000020ull;
+
+static const uint64_t P9N2_C_21_CPLT_CTRL0 = 0x35000000ull;
+
+static const uint64_t P9N2_C_21_CPLT_CTRL0_OR = 0x35000010ull;
+
+static const uint64_t P9N2_C_21_CPLT_CTRL0_CLEAR = 0x35000020ull;
+
+static const uint64_t P9N2_C_22_CPLT_CTRL0 = 0x36000000ull;
+
+static const uint64_t P9N2_C_22_CPLT_CTRL0_OR = 0x36000010ull;
+
+static const uint64_t P9N2_C_22_CPLT_CTRL0_CLEAR = 0x36000020ull;
+
+static const uint64_t P9N2_C_23_CPLT_CTRL0 = 0x37000000ull;
+
+static const uint64_t P9N2_C_23_CPLT_CTRL0_OR = 0x37000010ull;
+
+static const uint64_t P9N2_C_23_CPLT_CTRL0_CLEAR = 0x37000020ull;
+
+static const uint64_t P9N2_EQ_CPLT_CTRL0 = 0x10000000ull;
+
+static const uint64_t P9N2_EQ_CPLT_CTRL0_OR = 0x10000010ull;
+
+static const uint64_t P9N2_EQ_CPLT_CTRL0_CLEAR = 0x10000020ull;
+
+static const uint64_t P9N2_EQ_0_CPLT_CTRL0 = 0x10000000ull;
+
+static const uint64_t P9N2_EQ_0_CPLT_CTRL0_OR = 0x10000010ull;
+
+static const uint64_t P9N2_EQ_0_CPLT_CTRL0_CLEAR = 0x10000020ull;
+
+static const uint64_t P9N2_EQ_1_CPLT_CTRL0 = 0x11000000ull;
+
+static const uint64_t P9N2_EQ_1_CPLT_CTRL0_OR = 0x11000010ull;
+
+static const uint64_t P9N2_EQ_1_CPLT_CTRL0_CLEAR = 0x11000020ull;
+
+static const uint64_t P9N2_EQ_2_CPLT_CTRL0 = 0x12000000ull;
+
+static const uint64_t P9N2_EQ_2_CPLT_CTRL0_OR = 0x12000010ull;
+
+static const uint64_t P9N2_EQ_2_CPLT_CTRL0_CLEAR = 0x12000020ull;
+
+static const uint64_t P9N2_EQ_3_CPLT_CTRL0 = 0x13000000ull;
+
+static const uint64_t P9N2_EQ_3_CPLT_CTRL0_OR = 0x13000010ull;
+
+static const uint64_t P9N2_EQ_3_CPLT_CTRL0_CLEAR = 0x13000020ull;
+
+static const uint64_t P9N2_EQ_4_CPLT_CTRL0 = 0x14000000ull;
+
+static const uint64_t P9N2_EQ_4_CPLT_CTRL0_OR = 0x14000010ull;
+
+static const uint64_t P9N2_EQ_4_CPLT_CTRL0_CLEAR = 0x14000020ull;
+
+static const uint64_t P9N2_EQ_5_CPLT_CTRL0 = 0x15000000ull;
+
+static const uint64_t P9N2_EQ_5_CPLT_CTRL0_OR = 0x15000010ull;
+
+static const uint64_t P9N2_EQ_5_CPLT_CTRL0_CLEAR = 0x15000020ull;
+
+static const uint64_t P9N2_EX_CPLT_CTRL0 = 0x20000000ull;
+//DUPS: 21000000,
+static const uint64_t P9N2_EX_CPLT_CTRL0_OR = 0x20000010ull;
+//DUPS: 21000010,
+static const uint64_t P9N2_EX_CPLT_CTRL0_CLEAR = 0x20000020ull;
+//DUPS: 21000020,
+static const uint64_t P9N2_EX_0_CPLT_CTRL0 = 0x20000000ull;
+//DUPS: 21000000,
+static const uint64_t P9N2_EX_0_CPLT_CTRL0_OR = 0x20000010ull;
+//DUPS: 21000010,
+static const uint64_t P9N2_EX_0_CPLT_CTRL0_CLEAR = 0x20000020ull;
+//DUPS: 21000020,
+static const uint64_t P9N2_EX_1_CPLT_CTRL0 = 0x22000000ull;
+//DUPS: 23000000,
+static const uint64_t P9N2_EX_1_CPLT_CTRL0_OR = 0x22000010ull;
+//DUPS: 23000010,
+static const uint64_t P9N2_EX_1_CPLT_CTRL0_CLEAR = 0x22000020ull;
+//DUPS: 23000020,
+static const uint64_t P9N2_EX_2_CPLT_CTRL0 = 0x24000000ull;
+//DUPS: 25000000,
+static const uint64_t P9N2_EX_2_CPLT_CTRL0_OR = 0x24000010ull;
+//DUPS: 25000010,
+static const uint64_t P9N2_EX_2_CPLT_CTRL0_CLEAR = 0x24000020ull;
+//DUPS: 25000020,
+static const uint64_t P9N2_EX_3_CPLT_CTRL0 = 0x26000000ull;
+//DUPS: 27000000,
+static const uint64_t P9N2_EX_3_CPLT_CTRL0_OR = 0x26000010ull;
+//DUPS: 27000010,
+static const uint64_t P9N2_EX_3_CPLT_CTRL0_CLEAR = 0x26000020ull;
+//DUPS: 27000020,
+static const uint64_t P9N2_EX_4_CPLT_CTRL0 = 0x28000000ull;
+//DUPS: 29000000,
+static const uint64_t P9N2_EX_4_CPLT_CTRL0_OR = 0x28000010ull;
+//DUPS: 29000010,
+static const uint64_t P9N2_EX_4_CPLT_CTRL0_CLEAR = 0x28000020ull;
+//DUPS: 29000020,
+static const uint64_t P9N2_EX_5_CPLT_CTRL0 = 0x2A000000ull;
+//DUPS: 2B000000,
+static const uint64_t P9N2_EX_5_CPLT_CTRL0_OR = 0x2A000010ull;
+//DUPS: 2B000010,
+static const uint64_t P9N2_EX_5_CPLT_CTRL0_CLEAR = 0x2A000020ull;
+//DUPS: 2B000020,
+static const uint64_t P9N2_EX_6_CPLT_CTRL0 = 0x2C000000ull;
+//DUPS: 2D000000,
+static const uint64_t P9N2_EX_6_CPLT_CTRL0_OR = 0x2C000010ull;
+//DUPS: 2D000010,
+static const uint64_t P9N2_EX_6_CPLT_CTRL0_CLEAR = 0x2C000020ull;
+//DUPS: 2D000020,
+static const uint64_t P9N2_EX_7_CPLT_CTRL0 = 0x2E000000ull;
+//DUPS: 2F000000,
+static const uint64_t P9N2_EX_7_CPLT_CTRL0_OR = 0x2F000010ull;
+//DUPS: 2F000010,
+static const uint64_t P9N2_EX_7_CPLT_CTRL0_CLEAR = 0x2F000020ull;
+//DUPS: 2F000020,
+static const uint64_t P9N2_EX_8_CPLT_CTRL0 = 0x30000000ull;
+//DUPS: 31000000,
+static const uint64_t P9N2_EX_8_CPLT_CTRL0_OR = 0x30000010ull;
+//DUPS: 31000010,
+static const uint64_t P9N2_EX_8_CPLT_CTRL0_CLEAR = 0x30000020ull;
+//DUPS: 31000020,
+static const uint64_t P9N2_EX_9_CPLT_CTRL0 = 0x32000000ull;
+//DUPS: 33000000,
+static const uint64_t P9N2_EX_9_CPLT_CTRL0_OR = 0x32000010ull;
+//DUPS: 33000010,
+static const uint64_t P9N2_EX_9_CPLT_CTRL0_CLEAR = 0x32000020ull;
+//DUPS: 33000020,
+static const uint64_t P9N2_EX_10_CPLT_CTRL0 = 0x34000000ull;
+//DUPS: 35000000,
+static const uint64_t P9N2_EX_10_CPLT_CTRL0_OR = 0x34000010ull;
+//DUPS: 35000010,
+static const uint64_t P9N2_EX_10_CPLT_CTRL0_CLEAR = 0x34000020ull;
+//DUPS: 35000020,
+static const uint64_t P9N2_EX_11_CPLT_CTRL0 = 0x36000000ull;
+//DUPS: 37000000,
+static const uint64_t P9N2_EX_11_CPLT_CTRL0_OR = 0x36000010ull;
+//DUPS: 37000010,
+static const uint64_t P9N2_EX_11_CPLT_CTRL0_CLEAR = 0x36000020ull;
+//DUPS: 37000020,
+
+static const uint64_t P9N2_C_CPLT_CTRL1 = 0x20000001ull;
+
+static const uint64_t P9N2_C_CPLT_CTRL1_OR = 0x20000011ull;
+
+static const uint64_t P9N2_C_CPLT_CTRL1_CLEAR = 0x20000021ull;
+
+static const uint64_t P9N2_C_0_CPLT_CTRL1 = 0x20000001ull;
+
+static const uint64_t P9N2_C_0_CPLT_CTRL1_OR = 0x20000011ull;
+
+static const uint64_t P9N2_C_0_CPLT_CTRL1_CLEAR = 0x20000021ull;
+
+static const uint64_t P9N2_C_1_CPLT_CTRL1 = 0x21000001ull;
+
+static const uint64_t P9N2_C_1_CPLT_CTRL1_OR = 0x21000011ull;
+
+static const uint64_t P9N2_C_1_CPLT_CTRL1_CLEAR = 0x21000021ull;
+
+static const uint64_t P9N2_C_2_CPLT_CTRL1 = 0x22000001ull;
+
+static const uint64_t P9N2_C_2_CPLT_CTRL1_OR = 0x22000011ull;
+
+static const uint64_t P9N2_C_2_CPLT_CTRL1_CLEAR = 0x22000021ull;
+
+static const uint64_t P9N2_C_3_CPLT_CTRL1 = 0x23000001ull;
+
+static const uint64_t P9N2_C_3_CPLT_CTRL1_OR = 0x23000011ull;
+
+static const uint64_t P9N2_C_3_CPLT_CTRL1_CLEAR = 0x23000021ull;
+
+static const uint64_t P9N2_C_4_CPLT_CTRL1 = 0x24000001ull;
+
+static const uint64_t P9N2_C_4_CPLT_CTRL1_OR = 0x24000011ull;
+
+static const uint64_t P9N2_C_4_CPLT_CTRL1_CLEAR = 0x24000021ull;
+
+static const uint64_t P9N2_C_5_CPLT_CTRL1 = 0x25000001ull;
+
+static const uint64_t P9N2_C_5_CPLT_CTRL1_OR = 0x25000011ull;
+
+static const uint64_t P9N2_C_5_CPLT_CTRL1_CLEAR = 0x25000021ull;
+
+static const uint64_t P9N2_C_6_CPLT_CTRL1 = 0x26000001ull;
+
+static const uint64_t P9N2_C_6_CPLT_CTRL1_OR = 0x26000011ull;
+
+static const uint64_t P9N2_C_6_CPLT_CTRL1_CLEAR = 0x26000021ull;
+
+static const uint64_t P9N2_C_7_CPLT_CTRL1 = 0x27000001ull;
+
+static const uint64_t P9N2_C_7_CPLT_CTRL1_OR = 0x27000011ull;
+
+static const uint64_t P9N2_C_7_CPLT_CTRL1_CLEAR = 0x27000021ull;
+
+static const uint64_t P9N2_C_8_CPLT_CTRL1 = 0x28000001ull;
+
+static const uint64_t P9N2_C_8_CPLT_CTRL1_OR = 0x28000011ull;
+
+static const uint64_t P9N2_C_8_CPLT_CTRL1_CLEAR = 0x28000021ull;
+
+static const uint64_t P9N2_C_9_CPLT_CTRL1 = 0x29000001ull;
+
+static const uint64_t P9N2_C_9_CPLT_CTRL1_OR = 0x29000011ull;
+
+static const uint64_t P9N2_C_9_CPLT_CTRL1_CLEAR = 0x29000021ull;
+
+static const uint64_t P9N2_C_10_CPLT_CTRL1 = 0x2A000001ull;
+
+static const uint64_t P9N2_C_10_CPLT_CTRL1_OR = 0x2A000011ull;
+
+static const uint64_t P9N2_C_10_CPLT_CTRL1_CLEAR = 0x2A000021ull;
+
+static const uint64_t P9N2_C_11_CPLT_CTRL1 = 0x2B000001ull;
+
+static const uint64_t P9N2_C_11_CPLT_CTRL1_OR = 0x2B000011ull;
+
+static const uint64_t P9N2_C_11_CPLT_CTRL1_CLEAR = 0x2B000021ull;
+
+static const uint64_t P9N2_C_12_CPLT_CTRL1 = 0x2C000001ull;
+
+static const uint64_t P9N2_C_12_CPLT_CTRL1_OR = 0x2C000011ull;
+
+static const uint64_t P9N2_C_12_CPLT_CTRL1_CLEAR = 0x2C000021ull;
+
+static const uint64_t P9N2_C_13_CPLT_CTRL1 = 0x2D000001ull;
+
+static const uint64_t P9N2_C_13_CPLT_CTRL1_OR = 0x2D000011ull;
+
+static const uint64_t P9N2_C_13_CPLT_CTRL1_CLEAR = 0x2D000021ull;
+
+static const uint64_t P9N2_C_14_CPLT_CTRL1 = 0x2E000001ull;
+
+static const uint64_t P9N2_C_14_CPLT_CTRL1_OR = 0x2E000011ull;
+
+static const uint64_t P9N2_C_14_CPLT_CTRL1_CLEAR = 0x2E000021ull;
+
+static const uint64_t P9N2_C_15_CPLT_CTRL1 = 0x2F000001ull;
+
+static const uint64_t P9N2_C_15_CPLT_CTRL1_OR = 0x2F000011ull;
+
+static const uint64_t P9N2_C_15_CPLT_CTRL1_CLEAR = 0x2F000021ull;
+
+static const uint64_t P9N2_C_16_CPLT_CTRL1 = 0x30000001ull;
+
+static const uint64_t P9N2_C_16_CPLT_CTRL1_OR = 0x30000011ull;
+
+static const uint64_t P9N2_C_16_CPLT_CTRL1_CLEAR = 0x30000021ull;
+
+static const uint64_t P9N2_C_17_CPLT_CTRL1 = 0x31000001ull;
+
+static const uint64_t P9N2_C_17_CPLT_CTRL1_OR = 0x31000011ull;
+
+static const uint64_t P9N2_C_17_CPLT_CTRL1_CLEAR = 0x31000021ull;
+
+static const uint64_t P9N2_C_18_CPLT_CTRL1 = 0x32000001ull;
+
+static const uint64_t P9N2_C_18_CPLT_CTRL1_OR = 0x32000011ull;
+
+static const uint64_t P9N2_C_18_CPLT_CTRL1_CLEAR = 0x32000021ull;
+
+static const uint64_t P9N2_C_19_CPLT_CTRL1 = 0x33000001ull;
+
+static const uint64_t P9N2_C_19_CPLT_CTRL1_OR = 0x33000011ull;
+
+static const uint64_t P9N2_C_19_CPLT_CTRL1_CLEAR = 0x33000021ull;
+
+static const uint64_t P9N2_C_20_CPLT_CTRL1 = 0x34000001ull;
+
+static const uint64_t P9N2_C_20_CPLT_CTRL1_OR = 0x34000011ull;
+
+static const uint64_t P9N2_C_20_CPLT_CTRL1_CLEAR = 0x34000021ull;
+
+static const uint64_t P9N2_C_21_CPLT_CTRL1 = 0x35000001ull;
+
+static const uint64_t P9N2_C_21_CPLT_CTRL1_OR = 0x35000011ull;
+
+static const uint64_t P9N2_C_21_CPLT_CTRL1_CLEAR = 0x35000021ull;
+
+static const uint64_t P9N2_C_22_CPLT_CTRL1 = 0x36000001ull;
+
+static const uint64_t P9N2_C_22_CPLT_CTRL1_OR = 0x36000011ull;
+
+static const uint64_t P9N2_C_22_CPLT_CTRL1_CLEAR = 0x36000021ull;
+
+static const uint64_t P9N2_C_23_CPLT_CTRL1 = 0x37000001ull;
+
+static const uint64_t P9N2_C_23_CPLT_CTRL1_OR = 0x37000011ull;
+
+static const uint64_t P9N2_C_23_CPLT_CTRL1_CLEAR = 0x37000021ull;
+
+static const uint64_t P9N2_EQ_CPLT_CTRL1 = 0x10000001ull;
+
+static const uint64_t P9N2_EQ_CPLT_CTRL1_OR = 0x10000011ull;
+
+static const uint64_t P9N2_EQ_CPLT_CTRL1_CLEAR = 0x10000021ull;
+
+static const uint64_t P9N2_EQ_0_CPLT_CTRL1 = 0x10000001ull;
+
+static const uint64_t P9N2_EQ_0_CPLT_CTRL1_OR = 0x10000011ull;
+
+static const uint64_t P9N2_EQ_0_CPLT_CTRL1_CLEAR = 0x10000021ull;
+
+static const uint64_t P9N2_EQ_1_CPLT_CTRL1 = 0x11000001ull;
+
+static const uint64_t P9N2_EQ_1_CPLT_CTRL1_OR = 0x11000011ull;
+
+static const uint64_t P9N2_EQ_1_CPLT_CTRL1_CLEAR = 0x11000021ull;
+
+static const uint64_t P9N2_EQ_2_CPLT_CTRL1 = 0x12000001ull;
+
+static const uint64_t P9N2_EQ_2_CPLT_CTRL1_OR = 0x12000011ull;
+
+static const uint64_t P9N2_EQ_2_CPLT_CTRL1_CLEAR = 0x12000021ull;
+
+static const uint64_t P9N2_EQ_3_CPLT_CTRL1 = 0x13000001ull;
+
+static const uint64_t P9N2_EQ_3_CPLT_CTRL1_OR = 0x13000011ull;
+
+static const uint64_t P9N2_EQ_3_CPLT_CTRL1_CLEAR = 0x13000021ull;
+
+static const uint64_t P9N2_EQ_4_CPLT_CTRL1 = 0x14000001ull;
+
+static const uint64_t P9N2_EQ_4_CPLT_CTRL1_OR = 0x14000011ull;
+
+static const uint64_t P9N2_EQ_4_CPLT_CTRL1_CLEAR = 0x14000021ull;
+
+static const uint64_t P9N2_EQ_5_CPLT_CTRL1 = 0x15000001ull;
+
+static const uint64_t P9N2_EQ_5_CPLT_CTRL1_OR = 0x15000011ull;
+
+static const uint64_t P9N2_EQ_5_CPLT_CTRL1_CLEAR = 0x15000021ull;
+
+static const uint64_t P9N2_EX_CPLT_CTRL1 = 0x20000001ull;
+//DUPS: 21000001,
+static const uint64_t P9N2_EX_CPLT_CTRL1_OR = 0x20000011ull;
+//DUPS: 21000011,
+static const uint64_t P9N2_EX_CPLT_CTRL1_CLEAR = 0x20000021ull;
+//DUPS: 21000021,
+static const uint64_t P9N2_EX_0_CPLT_CTRL1 = 0x20000001ull;
+//DUPS: 21000001,
+static const uint64_t P9N2_EX_0_CPLT_CTRL1_OR = 0x20000011ull;
+//DUPS: 21000011,
+static const uint64_t P9N2_EX_0_CPLT_CTRL1_CLEAR = 0x20000021ull;
+//DUPS: 21000021,
+static const uint64_t P9N2_EX_1_CPLT_CTRL1 = 0x22000001ull;
+//DUPS: 23000001,
+static const uint64_t P9N2_EX_1_CPLT_CTRL1_OR = 0x22000011ull;
+//DUPS: 23000011,
+static const uint64_t P9N2_EX_1_CPLT_CTRL1_CLEAR = 0x22000021ull;
+//DUPS: 23000021,
+static const uint64_t P9N2_EX_2_CPLT_CTRL1 = 0x24000001ull;
+//DUPS: 25000001,
+static const uint64_t P9N2_EX_2_CPLT_CTRL1_OR = 0x24000011ull;
+//DUPS: 25000011,
+static const uint64_t P9N2_EX_2_CPLT_CTRL1_CLEAR = 0x24000021ull;
+//DUPS: 25000021,
+static const uint64_t P9N2_EX_3_CPLT_CTRL1 = 0x26000001ull;
+//DUPS: 27000001,
+static const uint64_t P9N2_EX_3_CPLT_CTRL1_OR = 0x26000011ull;
+//DUPS: 27000011,
+static const uint64_t P9N2_EX_3_CPLT_CTRL1_CLEAR = 0x26000021ull;
+//DUPS: 27000021,
+static const uint64_t P9N2_EX_4_CPLT_CTRL1 = 0x28000001ull;
+//DUPS: 29000001,
+static const uint64_t P9N2_EX_4_CPLT_CTRL1_OR = 0x28000011ull;
+//DUPS: 29000011,
+static const uint64_t P9N2_EX_4_CPLT_CTRL1_CLEAR = 0x28000021ull;
+//DUPS: 29000021,
+static const uint64_t P9N2_EX_5_CPLT_CTRL1 = 0x2A000001ull;
+//DUPS: 2B000001,
+static const uint64_t P9N2_EX_5_CPLT_CTRL1_OR = 0x2A000011ull;
+//DUPS: 2B000011,
+static const uint64_t P9N2_EX_5_CPLT_CTRL1_CLEAR = 0x2A000021ull;
+//DUPS: 2B000021,
+static const uint64_t P9N2_EX_6_CPLT_CTRL1 = 0x2C000001ull;
+//DUPS: 2D000001,
+static const uint64_t P9N2_EX_6_CPLT_CTRL1_OR = 0x2C000011ull;
+//DUPS: 2D000011,
+static const uint64_t P9N2_EX_6_CPLT_CTRL1_CLEAR = 0x2C000021ull;
+//DUPS: 2D000021,
+static const uint64_t P9N2_EX_7_CPLT_CTRL1 = 0x2F000001ull;
+//DUPS: 2F000001,
+static const uint64_t P9N2_EX_7_CPLT_CTRL1_OR = 0x2F000011ull;
+//DUPS: 2F000011,
+static const uint64_t P9N2_EX_7_CPLT_CTRL1_CLEAR = 0x2F000021ull;
+//DUPS: 2F000021,
+static const uint64_t P9N2_EX_8_CPLT_CTRL1 = 0x30000001ull;
+//DUPS: 31000001,
+static const uint64_t P9N2_EX_8_CPLT_CTRL1_OR = 0x30000011ull;
+//DUPS: 31000011,
+static const uint64_t P9N2_EX_8_CPLT_CTRL1_CLEAR = 0x30000021ull;
+//DUPS: 31000021,
+static const uint64_t P9N2_EX_9_CPLT_CTRL1 = 0x32000001ull;
+//DUPS: 33000001,
+static const uint64_t P9N2_EX_9_CPLT_CTRL1_OR = 0x32000011ull;
+//DUPS: 33000011,
+static const uint64_t P9N2_EX_9_CPLT_CTRL1_CLEAR = 0x32000021ull;
+//DUPS: 33000021,
+static const uint64_t P9N2_EX_10_CPLT_CTRL1 = 0x34000001ull;
+//DUPS: 35000001,
+static const uint64_t P9N2_EX_10_CPLT_CTRL1_OR = 0x34000011ull;
+//DUPS: 35000011,
+static const uint64_t P9N2_EX_10_CPLT_CTRL1_CLEAR = 0x34000021ull;
+//DUPS: 35000021,
+static const uint64_t P9N2_EX_11_CPLT_CTRL1 = 0x36000001ull;
+//DUPS: 37000001,
+static const uint64_t P9N2_EX_11_CPLT_CTRL1_OR = 0x36000011ull;
+//DUPS: 37000011,
+static const uint64_t P9N2_EX_11_CPLT_CTRL1_CLEAR = 0x36000021ull;
+//DUPS: 37000021,
+
+static const uint64_t P9N2_C_CPLT_MASK0 = 0x20000101ull;
+
+static const uint64_t P9N2_C_0_CPLT_MASK0 = 0x20000101ull;
+
+static const uint64_t P9N2_C_1_CPLT_MASK0 = 0x21000101ull;
+
+static const uint64_t P9N2_C_2_CPLT_MASK0 = 0x22000101ull;
+
+static const uint64_t P9N2_C_3_CPLT_MASK0 = 0x23000101ull;
+
+static const uint64_t P9N2_C_4_CPLT_MASK0 = 0x24000101ull;
+
+static const uint64_t P9N2_C_5_CPLT_MASK0 = 0x25000101ull;
+
+static const uint64_t P9N2_C_6_CPLT_MASK0 = 0x26000101ull;
+
+static const uint64_t P9N2_C_7_CPLT_MASK0 = 0x27000101ull;
+
+static const uint64_t P9N2_C_8_CPLT_MASK0 = 0x28000101ull;
+
+static const uint64_t P9N2_C_9_CPLT_MASK0 = 0x29000101ull;
+
+static const uint64_t P9N2_C_10_CPLT_MASK0 = 0x2A000101ull;
+
+static const uint64_t P9N2_C_11_CPLT_MASK0 = 0x2B000101ull;
+
+static const uint64_t P9N2_C_12_CPLT_MASK0 = 0x2C000101ull;
+
+static const uint64_t P9N2_C_13_CPLT_MASK0 = 0x2D000101ull;
+
+static const uint64_t P9N2_C_14_CPLT_MASK0 = 0x2E000101ull;
+
+static const uint64_t P9N2_C_15_CPLT_MASK0 = 0x2F000101ull;
+
+static const uint64_t P9N2_C_16_CPLT_MASK0 = 0x30000101ull;
+
+static const uint64_t P9N2_C_17_CPLT_MASK0 = 0x31000101ull;
+
+static const uint64_t P9N2_C_18_CPLT_MASK0 = 0x32000101ull;
+
+static const uint64_t P9N2_C_19_CPLT_MASK0 = 0x33000101ull;
+
+static const uint64_t P9N2_C_20_CPLT_MASK0 = 0x34000101ull;
+
+static const uint64_t P9N2_C_21_CPLT_MASK0 = 0x35000101ull;
+
+static const uint64_t P9N2_C_22_CPLT_MASK0 = 0x36000101ull;
+
+static const uint64_t P9N2_C_23_CPLT_MASK0 = 0x37000101ull;
+
+static const uint64_t P9N2_EQ_CPLT_MASK0 = 0x10000101ull;
+
+static const uint64_t P9N2_EQ_0_CPLT_MASK0 = 0x10000101ull;
+
+static const uint64_t P9N2_EQ_1_CPLT_MASK0 = 0x11000101ull;
+
+static const uint64_t P9N2_EQ_2_CPLT_MASK0 = 0x12000101ull;
+
+static const uint64_t P9N2_EQ_3_CPLT_MASK0 = 0x13000101ull;
+
+static const uint64_t P9N2_EQ_4_CPLT_MASK0 = 0x14000101ull;
+
+static const uint64_t P9N2_EQ_5_CPLT_MASK0 = 0x15000101ull;
+
+static const uint64_t P9N2_EX_CPLT_MASK0 = 0x20000101ull;
+//DUPS: 21000101,
+static const uint64_t P9N2_EX_0_CPLT_MASK0 = 0x20000101ull;
+//DUPS: 21000101,
+static const uint64_t P9N2_EX_1_CPLT_MASK0 = 0x22000101ull;
+//DUPS: 23000101,
+static const uint64_t P9N2_EX_2_CPLT_MASK0 = 0x24000101ull;
+//DUPS: 25000101,
+static const uint64_t P9N2_EX_3_CPLT_MASK0 = 0x26000101ull;
+//DUPS: 27000101,
+static const uint64_t P9N2_EX_4_CPLT_MASK0 = 0x28000101ull;
+//DUPS: 29000101,
+static const uint64_t P9N2_EX_5_CPLT_MASK0 = 0x2A000101ull;
+//DUPS: 2B000101,
+static const uint64_t P9N2_EX_6_CPLT_MASK0 = 0x2C000101ull;
+//DUPS: 2D000101,
+static const uint64_t P9N2_EX_7_CPLT_MASK0 = 0x2F000101ull;
+//DUPS: 2F000101,
+static const uint64_t P9N2_EX_8_CPLT_MASK0 = 0x30000101ull;
+//DUPS: 31000101,
+static const uint64_t P9N2_EX_9_CPLT_MASK0 = 0x32000101ull;
+//DUPS: 33000101,
+static const uint64_t P9N2_EX_10_CPLT_MASK0 = 0x34000101ull;
+//DUPS: 35000101,
+static const uint64_t P9N2_EX_11_CPLT_MASK0 = 0x36000101ull;
+//DUPS: 37000101,
+
+static const uint64_t P9N2_C_CPLT_STAT0 = 0x20000100ull;
+
+static const uint64_t P9N2_C_0_CPLT_STAT0 = 0x20000100ull;
+
+static const uint64_t P9N2_C_1_CPLT_STAT0 = 0x21000100ull;
+
+static const uint64_t P9N2_C_2_CPLT_STAT0 = 0x22000100ull;
+
+static const uint64_t P9N2_C_3_CPLT_STAT0 = 0x23000100ull;
+
+static const uint64_t P9N2_C_4_CPLT_STAT0 = 0x24000100ull;
+
+static const uint64_t P9N2_C_5_CPLT_STAT0 = 0x25000100ull;
+
+static const uint64_t P9N2_C_6_CPLT_STAT0 = 0x26000100ull;
+
+static const uint64_t P9N2_C_7_CPLT_STAT0 = 0x27000100ull;
+
+static const uint64_t P9N2_C_8_CPLT_STAT0 = 0x28000100ull;
+
+static const uint64_t P9N2_C_9_CPLT_STAT0 = 0x29000100ull;
+
+static const uint64_t P9N2_C_10_CPLT_STAT0 = 0x2A000100ull;
+
+static const uint64_t P9N2_C_11_CPLT_STAT0 = 0x2B000100ull;
+
+static const uint64_t P9N2_C_12_CPLT_STAT0 = 0x2C000100ull;
+
+static const uint64_t P9N2_C_13_CPLT_STAT0 = 0x2D000100ull;
+
+static const uint64_t P9N2_C_14_CPLT_STAT0 = 0x2E000100ull;
+
+static const uint64_t P9N2_C_15_CPLT_STAT0 = 0x2F000100ull;
+
+static const uint64_t P9N2_C_16_CPLT_STAT0 = 0x30000100ull;
+
+static const uint64_t P9N2_C_17_CPLT_STAT0 = 0x31000100ull;
+
+static const uint64_t P9N2_C_18_CPLT_STAT0 = 0x32000100ull;
+
+static const uint64_t P9N2_C_19_CPLT_STAT0 = 0x33000100ull;
+
+static const uint64_t P9N2_C_20_CPLT_STAT0 = 0x34000100ull;
+
+static const uint64_t P9N2_C_21_CPLT_STAT0 = 0x35000100ull;
+
+static const uint64_t P9N2_C_22_CPLT_STAT0 = 0x36000100ull;
+
+static const uint64_t P9N2_C_23_CPLT_STAT0 = 0x37000100ull;
+
+static const uint64_t P9N2_EQ_CPLT_STAT0 = 0x10000100ull;
+
+static const uint64_t P9N2_EQ_0_CPLT_STAT0 = 0x10000100ull;
+
+static const uint64_t P9N2_EQ_1_CPLT_STAT0 = 0x11000100ull;
+
+static const uint64_t P9N2_EQ_2_CPLT_STAT0 = 0x12000100ull;
+
+static const uint64_t P9N2_EQ_3_CPLT_STAT0 = 0x13000100ull;
+
+static const uint64_t P9N2_EQ_4_CPLT_STAT0 = 0x14000100ull;
+
+static const uint64_t P9N2_EQ_5_CPLT_STAT0 = 0x15000100ull;
+
+static const uint64_t P9N2_EX_CPLT_STAT0 = 0x20000100ull;
+//DUPS: 21000100,
+static const uint64_t P9N2_EX_0_CPLT_STAT0 = 0x20000100ull;
+//DUPS: 21000100,
+static const uint64_t P9N2_EX_1_CPLT_STAT0 = 0x22000100ull;
+//DUPS: 23000100,
+static const uint64_t P9N2_EX_2_CPLT_STAT0 = 0x24000100ull;
+//DUPS: 25000100,
+static const uint64_t P9N2_EX_3_CPLT_STAT0 = 0x26000100ull;
+//DUPS: 27000100,
+static const uint64_t P9N2_EX_4_CPLT_STAT0 = 0x28000100ull;
+//DUPS: 29000100,
+static const uint64_t P9N2_EX_5_CPLT_STAT0 = 0x2A000100ull;
+//DUPS: 2B000100,
+static const uint64_t P9N2_EX_6_CPLT_STAT0 = 0x2C000100ull;
+//DUPS: 2D000100,
+static const uint64_t P9N2_EX_7_CPLT_STAT0 = 0x2F000100ull;
+//DUPS: 2F000100,
+static const uint64_t P9N2_EX_8_CPLT_STAT0 = 0x30000100ull;
+//DUPS: 31000100,
+static const uint64_t P9N2_EX_9_CPLT_STAT0 = 0x32000100ull;
+//DUPS: 33000100,
+static const uint64_t P9N2_EX_10_CPLT_STAT0 = 0x34000100ull;
+//DUPS: 35000100,
+static const uint64_t P9N2_EX_11_CPLT_STAT0 = 0x36000100ull;
+//DUPS: 37000100,
+
+static const uint64_t P9N2_C_CPPM_CACCR = 0x200F0168ull;
+
+static const uint64_t P9N2_C_CPPM_CACCR_CLEAR = 0x200F0169ull;
+
+static const uint64_t P9N2_C_CPPM_CACCR_OR = 0x200F016Aull;
+
+static const uint64_t P9N2_C_0_CPPM_CACCR = 0x200F0168ull;
+
+static const uint64_t P9N2_C_0_CPPM_CACCR_CLEAR = 0x200F0169ull;
+
+static const uint64_t P9N2_C_0_CPPM_CACCR_OR = 0x200F016Aull;
+
+static const uint64_t P9N2_C_1_CPPM_CACCR = 0x210F0168ull;
+
+static const uint64_t P9N2_C_1_CPPM_CACCR_CLEAR = 0x210F0169ull;
+
+static const uint64_t P9N2_C_1_CPPM_CACCR_OR = 0x210F016Aull;
+
+static const uint64_t P9N2_C_2_CPPM_CACCR = 0x220F0168ull;
+
+static const uint64_t P9N2_C_2_CPPM_CACCR_CLEAR = 0x220F0169ull;
+
+static const uint64_t P9N2_C_2_CPPM_CACCR_OR = 0x220F016Aull;
+
+static const uint64_t P9N2_C_3_CPPM_CACCR = 0x230F0168ull;
+
+static const uint64_t P9N2_C_3_CPPM_CACCR_CLEAR = 0x230F0169ull;
+
+static const uint64_t P9N2_C_3_CPPM_CACCR_OR = 0x230F016Aull;
+
+static const uint64_t P9N2_C_4_CPPM_CACCR = 0x240F0168ull;
+
+static const uint64_t P9N2_C_4_CPPM_CACCR_CLEAR = 0x240F0169ull;
+
+static const uint64_t P9N2_C_4_CPPM_CACCR_OR = 0x240F016Aull;
+
+static const uint64_t P9N2_C_5_CPPM_CACCR = 0x250F0168ull;
+
+static const uint64_t P9N2_C_5_CPPM_CACCR_CLEAR = 0x250F0169ull;
+
+static const uint64_t P9N2_C_5_CPPM_CACCR_OR = 0x250F016Aull;
+
+static const uint64_t P9N2_C_6_CPPM_CACCR = 0x260F0168ull;
+
+static const uint64_t P9N2_C_6_CPPM_CACCR_CLEAR = 0x260F0169ull;
+
+static const uint64_t P9N2_C_6_CPPM_CACCR_OR = 0x260F016Aull;
+
+static const uint64_t P9N2_C_7_CPPM_CACCR = 0x270F0168ull;
+
+static const uint64_t P9N2_C_7_CPPM_CACCR_CLEAR = 0x270F0169ull;
+
+static const uint64_t P9N2_C_7_CPPM_CACCR_OR = 0x270F016Aull;
+
+static const uint64_t P9N2_C_8_CPPM_CACCR = 0x280F0168ull;
+
+static const uint64_t P9N2_C_8_CPPM_CACCR_CLEAR = 0x280F0169ull;
+
+static const uint64_t P9N2_C_8_CPPM_CACCR_OR = 0x280F016Aull;
+
+static const uint64_t P9N2_C_9_CPPM_CACCR = 0x290F0168ull;
+
+static const uint64_t P9N2_C_9_CPPM_CACCR_CLEAR = 0x290F0169ull;
+
+static const uint64_t P9N2_C_9_CPPM_CACCR_OR = 0x290F016Aull;
+
+static const uint64_t P9N2_C_10_CPPM_CACCR = 0x2A0F0168ull;
+
+static const uint64_t P9N2_C_10_CPPM_CACCR_CLEAR = 0x2A0F0169ull;
+
+static const uint64_t P9N2_C_10_CPPM_CACCR_OR = 0x2A0F016Aull;
+
+static const uint64_t P9N2_C_11_CPPM_CACCR = 0x2B0F0168ull;
+
+static const uint64_t P9N2_C_11_CPPM_CACCR_CLEAR = 0x2B0F0169ull;
+
+static const uint64_t P9N2_C_11_CPPM_CACCR_OR = 0x2B0F016Aull;
+
+static const uint64_t P9N2_C_12_CPPM_CACCR = 0x2C0F0168ull;
+
+static const uint64_t P9N2_C_12_CPPM_CACCR_CLEAR = 0x2C0F0169ull;
+
+static const uint64_t P9N2_C_12_CPPM_CACCR_OR = 0x2C0F016Aull;
+
+static const uint64_t P9N2_C_13_CPPM_CACCR = 0x2D0F0168ull;
+
+static const uint64_t P9N2_C_13_CPPM_CACCR_CLEAR = 0x2D0F0169ull;
+
+static const uint64_t P9N2_C_13_CPPM_CACCR_OR = 0x2D0F016Aull;
+
+static const uint64_t P9N2_C_14_CPPM_CACCR = 0x2E0F0168ull;
+
+static const uint64_t P9N2_C_14_CPPM_CACCR_CLEAR = 0x2E0F0169ull;
+
+static const uint64_t P9N2_C_14_CPPM_CACCR_OR = 0x2E0F016Aull;
+
+static const uint64_t P9N2_C_15_CPPM_CACCR = 0x2F0F0168ull;
+
+static const uint64_t P9N2_C_15_CPPM_CACCR_CLEAR = 0x2F0F0169ull;
+
+static const uint64_t P9N2_C_15_CPPM_CACCR_OR = 0x2F0F016Aull;
+
+static const uint64_t P9N2_C_16_CPPM_CACCR = 0x300F0168ull;
+
+static const uint64_t P9N2_C_16_CPPM_CACCR_CLEAR = 0x300F0169ull;
+
+static const uint64_t P9N2_C_16_CPPM_CACCR_OR = 0x300F016Aull;
+
+static const uint64_t P9N2_C_17_CPPM_CACCR = 0x310F0168ull;
+
+static const uint64_t P9N2_C_17_CPPM_CACCR_CLEAR = 0x310F0169ull;
+
+static const uint64_t P9N2_C_17_CPPM_CACCR_OR = 0x310F016Aull;
+
+static const uint64_t P9N2_C_18_CPPM_CACCR = 0x320F0168ull;
+
+static const uint64_t P9N2_C_18_CPPM_CACCR_CLEAR = 0x320F0169ull;
+
+static const uint64_t P9N2_C_18_CPPM_CACCR_OR = 0x320F016Aull;
+
+static const uint64_t P9N2_C_19_CPPM_CACCR = 0x330F0168ull;
+
+static const uint64_t P9N2_C_19_CPPM_CACCR_CLEAR = 0x330F0169ull;
+
+static const uint64_t P9N2_C_19_CPPM_CACCR_OR = 0x330F016Aull;
+
+static const uint64_t P9N2_C_20_CPPM_CACCR = 0x340F0168ull;
+
+static const uint64_t P9N2_C_20_CPPM_CACCR_CLEAR = 0x340F0169ull;
+
+static const uint64_t P9N2_C_20_CPPM_CACCR_OR = 0x340F016Aull;
+
+static const uint64_t P9N2_C_21_CPPM_CACCR = 0x350F0168ull;
+
+static const uint64_t P9N2_C_21_CPPM_CACCR_CLEAR = 0x350F0169ull;
+
+static const uint64_t P9N2_C_21_CPPM_CACCR_OR = 0x350F016Aull;
+
+static const uint64_t P9N2_C_22_CPPM_CACCR = 0x360F0168ull;
+
+static const uint64_t P9N2_C_22_CPPM_CACCR_CLEAR = 0x360F0169ull;
+
+static const uint64_t P9N2_C_22_CPPM_CACCR_OR = 0x360F016Aull;
+
+static const uint64_t P9N2_C_23_CPPM_CACCR = 0x370F0168ull;
+
+static const uint64_t P9N2_C_23_CPPM_CACCR_CLEAR = 0x370F0169ull;
+
+static const uint64_t P9N2_C_23_CPPM_CACCR_OR = 0x370F016Aull;
+
+static const uint64_t P9N2_EX_CPPM_CACCR = 0x200F0168ull;
+//DUPS: 210F0168,
+static const uint64_t P9N2_EX_CPPM_CACCR_CLEAR = 0x200F0169ull;
+//DUPS: 210F0169,
+static const uint64_t P9N2_EX_CPPM_CACCR_OR = 0x200F016Aull;
+//DUPS: 210F016A,
+static const uint64_t P9N2_EX_0_CPPM_CACCR = 0x200F0168ull;
+//DUPS: 210F0168,
+static const uint64_t P9N2_EX_0_CPPM_CACCR_CLEAR = 0x200F0169ull;
+//DUPS: 210F0169,
+static const uint64_t P9N2_EX_0_CPPM_CACCR_OR = 0x200F016Aull;
+//DUPS: 210F016A,
+static const uint64_t P9N2_EX_1_CPPM_CACCR = 0x220F0168ull;
+//DUPS: 220F0168,
+static const uint64_t P9N2_EX_1_CPPM_CACCR_CLEAR = 0x220F0169ull;
+//DUPS: 220F0169,
+static const uint64_t P9N2_EX_1_CPPM_CACCR_OR = 0x220F016Aull;
+//DUPS: 220F016A,
+static const uint64_t P9N2_EX_2_CPPM_CACCR = 0x240F0168ull;
+//DUPS: 250F0168,
+static const uint64_t P9N2_EX_2_CPPM_CACCR_CLEAR = 0x240F0169ull;
+//DUPS: 250F0169,
+static const uint64_t P9N2_EX_2_CPPM_CACCR_OR = 0x240F016Aull;
+//DUPS: 250F016A,
+static const uint64_t P9N2_EX_3_CPPM_CACCR = 0x260F0168ull;
+//DUPS: 270F0168,
+static const uint64_t P9N2_EX_3_CPPM_CACCR_CLEAR = 0x260F0169ull;
+//DUPS: 270F0169,
+static const uint64_t P9N2_EX_3_CPPM_CACCR_OR = 0x260F016Aull;
+//DUPS: 270F016A,
+static const uint64_t P9N2_EX_4_CPPM_CACCR = 0x280F0168ull;
+//DUPS: 290F0168,
+static const uint64_t P9N2_EX_4_CPPM_CACCR_CLEAR = 0x280F0169ull;
+//DUPS: 290F0169,
+static const uint64_t P9N2_EX_4_CPPM_CACCR_OR = 0x280F016Aull;
+//DUPS: 290F016A,
+static const uint64_t P9N2_EX_5_CPPM_CACCR = 0x2A0F0168ull;
+//DUPS: 2B0F0168,
+static const uint64_t P9N2_EX_5_CPPM_CACCR_CLEAR = 0x2A0F0169ull;
+//DUPS: 2B0F0169,
+static const uint64_t P9N2_EX_5_CPPM_CACCR_OR = 0x2A0F016Aull;
+//DUPS: 2B0F016A,
+static const uint64_t P9N2_EX_6_CPPM_CACCR = 0x2C0F0168ull;
+//DUPS: 2D0F0168,
+static const uint64_t P9N2_EX_6_CPPM_CACCR_CLEAR = 0x2C0F0169ull;
+//DUPS: 2D0F0169,
+static const uint64_t P9N2_EX_6_CPPM_CACCR_OR = 0x2C0F016Aull;
+//DUPS: 2D0F016A,
+static const uint64_t P9N2_EX_7_CPPM_CACCR = 0x2E0F0168ull;
+//DUPS: 2F0F0168,
+static const uint64_t P9N2_EX_7_CPPM_CACCR_CLEAR = 0x2E0F0169ull;
+//DUPS: 2F0F0169,
+static const uint64_t P9N2_EX_7_CPPM_CACCR_OR = 0x2E0F016Aull;
+//DUPS: 2F0F016A,
+static const uint64_t P9N2_EX_8_CPPM_CACCR = 0x300F0168ull;
+//DUPS: 310F0168,
+static const uint64_t P9N2_EX_8_CPPM_CACCR_CLEAR = 0x300F0169ull;
+//DUPS: 310F0169,
+static const uint64_t P9N2_EX_8_CPPM_CACCR_OR = 0x300F016Aull;
+//DUPS: 310F016A,
+static const uint64_t P9N2_EX_9_CPPM_CACCR = 0x320F0168ull;
+//DUPS: 330F0168,
+static const uint64_t P9N2_EX_9_CPPM_CACCR_CLEAR = 0x320F0169ull;
+//DUPS: 330F0169,
+static const uint64_t P9N2_EX_9_CPPM_CACCR_OR = 0x320F016Aull;
+//DUPS: 330F016A,
+static const uint64_t P9N2_EX_10_CPPM_CACCR = 0x340F0168ull;
+//DUPS: 350F0168,
+static const uint64_t P9N2_EX_10_CPPM_CACCR_CLEAR = 0x340F0169ull;
+//DUPS: 350F0169,
+static const uint64_t P9N2_EX_10_CPPM_CACCR_OR = 0x340F016Aull;
+//DUPS: 350F016A,
+static const uint64_t P9N2_EX_11_CPPM_CACCR = 0x360F0168ull;
+//DUPS: 370F0168,
+static const uint64_t P9N2_EX_11_CPPM_CACCR_CLEAR = 0x360F0169ull;
+//DUPS: 370F0169,
+static const uint64_t P9N2_EX_11_CPPM_CACCR_OR = 0x360F016Aull;
+//DUPS: 370F016A,
+
+static const uint64_t P9N2_C_CPPM_CACSR = 0x200F016Bull;
+
+static const uint64_t P9N2_C_0_CPPM_CACSR = 0x200F016Bull;
+
+static const uint64_t P9N2_C_1_CPPM_CACSR = 0x210F016Bull;
+
+static const uint64_t P9N2_C_2_CPPM_CACSR = 0x220F016Bull;
+
+static const uint64_t P9N2_C_3_CPPM_CACSR = 0x230F016Bull;
+
+static const uint64_t P9N2_C_4_CPPM_CACSR = 0x240F016Bull;
+
+static const uint64_t P9N2_C_5_CPPM_CACSR = 0x250F016Bull;
+
+static const uint64_t P9N2_C_6_CPPM_CACSR = 0x260F016Bull;
+
+static const uint64_t P9N2_C_7_CPPM_CACSR = 0x270F016Bull;
+
+static const uint64_t P9N2_C_8_CPPM_CACSR = 0x280F016Bull;
+
+static const uint64_t P9N2_C_9_CPPM_CACSR = 0x290F016Bull;
+
+static const uint64_t P9N2_C_10_CPPM_CACSR = 0x2A0F016Bull;
+
+static const uint64_t P9N2_C_11_CPPM_CACSR = 0x2B0F016Bull;
+
+static const uint64_t P9N2_C_12_CPPM_CACSR = 0x2C0F016Bull;
+
+static const uint64_t P9N2_C_13_CPPM_CACSR = 0x2D0F016Bull;
+
+static const uint64_t P9N2_C_14_CPPM_CACSR = 0x2E0F016Bull;
+
+static const uint64_t P9N2_C_15_CPPM_CACSR = 0x2F0F016Bull;
+
+static const uint64_t P9N2_C_16_CPPM_CACSR = 0x300F016Bull;
+
+static const uint64_t P9N2_C_17_CPPM_CACSR = 0x310F016Bull;
+
+static const uint64_t P9N2_C_18_CPPM_CACSR = 0x320F016Bull;
+
+static const uint64_t P9N2_C_19_CPPM_CACSR = 0x330F016Bull;
+
+static const uint64_t P9N2_C_20_CPPM_CACSR = 0x340F016Bull;
+
+static const uint64_t P9N2_C_21_CPPM_CACSR = 0x350F016Bull;
+
+static const uint64_t P9N2_C_22_CPPM_CACSR = 0x360F016Bull;
+
+static const uint64_t P9N2_C_23_CPPM_CACSR = 0x370F016Bull;
+
+static const uint64_t P9N2_EX_CPPM_CACSR = 0x200F016Bull;
+//DUPS: 210F016B,
+static const uint64_t P9N2_EX_0_CPPM_CACSR = 0x200F016Bull;
+//DUPS: 210F016B,
+static const uint64_t P9N2_EX_1_CPPM_CACSR = 0x220F016Bull;
+//DUPS: 220F016B,
+static const uint64_t P9N2_EX_2_CPPM_CACSR = 0x240F016Bull;
+//DUPS: 250F016B,
+static const uint64_t P9N2_EX_3_CPPM_CACSR = 0x260F016Bull;
+//DUPS: 270F016B,
+static const uint64_t P9N2_EX_4_CPPM_CACSR = 0x280F016Bull;
+//DUPS: 290F016B,
+static const uint64_t P9N2_EX_5_CPPM_CACSR = 0x2A0F016Bull;
+//DUPS: 2B0F016B,
+static const uint64_t P9N2_EX_6_CPPM_CACSR = 0x2C0F016Bull;
+//DUPS: 2D0F016B,
+static const uint64_t P9N2_EX_7_CPPM_CACSR = 0x2E0F016Bull;
+//DUPS: 2F0F016B,
+static const uint64_t P9N2_EX_8_CPPM_CACSR = 0x300F016Bull;
+//DUPS: 310F016B,
+static const uint64_t P9N2_EX_9_CPPM_CACSR = 0x320F016Bull;
+//DUPS: 330F016B,
+static const uint64_t P9N2_EX_10_CPPM_CACSR = 0x340F016Bull;
+//DUPS: 350F016B,
+static const uint64_t P9N2_EX_11_CPPM_CACSR = 0x360F016Bull;
+//DUPS: 370F016B,
+
+static const uint64_t P9N2_C_CPPM_CIIR = 0x200F01ADull;
+
+static const uint64_t P9N2_C_0_CPPM_CIIR = 0x200F01ADull;
+
+static const uint64_t P9N2_C_1_CPPM_CIIR = 0x210F01ADull;
+
+static const uint64_t P9N2_C_2_CPPM_CIIR = 0x220F01ADull;
+
+static const uint64_t P9N2_C_3_CPPM_CIIR = 0x230F01ADull;
+
+static const uint64_t P9N2_C_4_CPPM_CIIR = 0x240F01ADull;
+
+static const uint64_t P9N2_C_5_CPPM_CIIR = 0x250F01ADull;
+
+static const uint64_t P9N2_C_6_CPPM_CIIR = 0x260F01ADull;
+
+static const uint64_t P9N2_C_7_CPPM_CIIR = 0x270F01ADull;
+
+static const uint64_t P9N2_C_8_CPPM_CIIR = 0x280F01ADull;
+
+static const uint64_t P9N2_C_9_CPPM_CIIR = 0x290F01ADull;
+
+static const uint64_t P9N2_C_10_CPPM_CIIR = 0x2A0F01ADull;
+
+static const uint64_t P9N2_C_11_CPPM_CIIR = 0x2B0F01ADull;
+
+static const uint64_t P9N2_C_12_CPPM_CIIR = 0x2C0F01ADull;
+
+static const uint64_t P9N2_C_13_CPPM_CIIR = 0x2D0F01ADull;
+
+static const uint64_t P9N2_C_14_CPPM_CIIR = 0x2E0F01ADull;
+
+static const uint64_t P9N2_C_15_CPPM_CIIR = 0x2F0F01ADull;
+
+static const uint64_t P9N2_C_16_CPPM_CIIR = 0x300F01ADull;
+
+static const uint64_t P9N2_C_17_CPPM_CIIR = 0x310F01ADull;
+
+static const uint64_t P9N2_C_18_CPPM_CIIR = 0x320F01ADull;
+
+static const uint64_t P9N2_C_19_CPPM_CIIR = 0x330F01ADull;
+
+static const uint64_t P9N2_C_20_CPPM_CIIR = 0x340F01ADull;
+
+static const uint64_t P9N2_C_21_CPPM_CIIR = 0x350F01ADull;
+
+static const uint64_t P9N2_C_22_CPPM_CIIR = 0x360F01ADull;
+
+static const uint64_t P9N2_C_23_CPPM_CIIR = 0x370F01ADull;
+
+static const uint64_t P9N2_EX_CPPM_CIIR = 0x200F01ADull;
+//DUPS: 210F01AD,
+static const uint64_t P9N2_EX_0_CPPM_CIIR = 0x200F01ADull;
+//DUPS: 210F01AD,
+static const uint64_t P9N2_EX_1_CPPM_CIIR = 0x220F01ADull;
+//DUPS: 220F01AD,
+static const uint64_t P9N2_EX_2_CPPM_CIIR = 0x240F01ADull;
+//DUPS: 250F01AD,
+static const uint64_t P9N2_EX_3_CPPM_CIIR = 0x260F01ADull;
+//DUPS: 270F01AD,
+static const uint64_t P9N2_EX_4_CPPM_CIIR = 0x280F01ADull;
+//DUPS: 290F01AD,
+static const uint64_t P9N2_EX_5_CPPM_CIIR = 0x2A0F01ADull;
+//DUPS: 2B0F01AD,
+static const uint64_t P9N2_EX_6_CPPM_CIIR = 0x2C0F01ADull;
+//DUPS: 2D0F01AD,
+static const uint64_t P9N2_EX_7_CPPM_CIIR = 0x2E0F01ADull;
+//DUPS: 2F0F01AD,
+static const uint64_t P9N2_EX_8_CPPM_CIIR = 0x300F01ADull;
+//DUPS: 310F01AD,
+static const uint64_t P9N2_EX_9_CPPM_CIIR = 0x320F01ADull;
+//DUPS: 330F01AD,
+static const uint64_t P9N2_EX_10_CPPM_CIIR = 0x340F01ADull;
+//DUPS: 350F01AD,
+static const uint64_t P9N2_EX_11_CPPM_CIIR = 0x360F01ADull;
+//DUPS: 370F01AD,
+
+static const uint64_t P9N2_C_CPPM_CISR = 0x200F01AEull;
+
+static const uint64_t P9N2_C_0_CPPM_CISR = 0x200F01AEull;
+
+static const uint64_t P9N2_C_1_CPPM_CISR = 0x210F01AEull;
+
+static const uint64_t P9N2_C_2_CPPM_CISR = 0x220F01AEull;
+
+static const uint64_t P9N2_C_3_CPPM_CISR = 0x230F01AEull;
+
+static const uint64_t P9N2_C_4_CPPM_CISR = 0x240F01AEull;
+
+static const uint64_t P9N2_C_5_CPPM_CISR = 0x250F01AEull;
+
+static const uint64_t P9N2_C_6_CPPM_CISR = 0x260F01AEull;
+
+static const uint64_t P9N2_C_7_CPPM_CISR = 0x270F01AEull;
+
+static const uint64_t P9N2_C_8_CPPM_CISR = 0x280F01AEull;
+
+static const uint64_t P9N2_C_9_CPPM_CISR = 0x290F01AEull;
+
+static const uint64_t P9N2_C_10_CPPM_CISR = 0x2A0F01AEull;
+
+static const uint64_t P9N2_C_11_CPPM_CISR = 0x2B0F01AEull;
+
+static const uint64_t P9N2_C_12_CPPM_CISR = 0x2C0F01AEull;
+
+static const uint64_t P9N2_C_13_CPPM_CISR = 0x2D0F01AEull;
+
+static const uint64_t P9N2_C_14_CPPM_CISR = 0x2E0F01AEull;
+
+static const uint64_t P9N2_C_15_CPPM_CISR = 0x2F0F01AEull;
+
+static const uint64_t P9N2_C_16_CPPM_CISR = 0x300F01AEull;
+
+static const uint64_t P9N2_C_17_CPPM_CISR = 0x310F01AEull;
+
+static const uint64_t P9N2_C_18_CPPM_CISR = 0x320F01AEull;
+
+static const uint64_t P9N2_C_19_CPPM_CISR = 0x330F01AEull;
+
+static const uint64_t P9N2_C_20_CPPM_CISR = 0x340F01AEull;
+
+static const uint64_t P9N2_C_21_CPPM_CISR = 0x350F01AEull;
+
+static const uint64_t P9N2_C_22_CPPM_CISR = 0x360F01AEull;
+
+static const uint64_t P9N2_C_23_CPPM_CISR = 0x370F01AEull;
+
+static const uint64_t P9N2_EX_CPPM_CISR = 0x200F01AEull;
+//DUPS: 210F01AE,
+static const uint64_t P9N2_EX_0_CPPM_CISR = 0x200F01AEull;
+//DUPS: 210F01AE,
+static const uint64_t P9N2_EX_1_CPPM_CISR = 0x220F01AEull;
+//DUPS: 220F01AE,
+static const uint64_t P9N2_EX_2_CPPM_CISR = 0x240F01AEull;
+//DUPS: 250F01AE,
+static const uint64_t P9N2_EX_3_CPPM_CISR = 0x260F01AEull;
+//DUPS: 270F01AE,
+static const uint64_t P9N2_EX_4_CPPM_CISR = 0x280F01AEull;
+//DUPS: 290F01AE,
+static const uint64_t P9N2_EX_5_CPPM_CISR = 0x2A0F01AEull;
+//DUPS: 2B0F01AE,
+static const uint64_t P9N2_EX_6_CPPM_CISR = 0x2C0F01AEull;
+//DUPS: 2D0F01AE,
+static const uint64_t P9N2_EX_7_CPPM_CISR = 0x2E0F01AEull;
+//DUPS: 2F0F01AE,
+static const uint64_t P9N2_EX_8_CPPM_CISR = 0x300F01AEull;
+//DUPS: 310F01AE,
+static const uint64_t P9N2_EX_9_CPPM_CISR = 0x320F01AEull;
+//DUPS: 330F01AE,
+static const uint64_t P9N2_EX_10_CPPM_CISR = 0x340F01AEull;
+//DUPS: 350F01AE,
+static const uint64_t P9N2_EX_11_CPPM_CISR = 0x360F01AEull;
+//DUPS: 370F01AE,
+
+static const uint64_t P9N2_C_CPPM_CIVRMLCR = 0x200F01B7ull;
+
+static const uint64_t P9N2_C_0_CPPM_CIVRMLCR = 0x200F01B7ull;
+
+static const uint64_t P9N2_C_1_CPPM_CIVRMLCR = 0x210F01B7ull;
+
+static const uint64_t P9N2_C_2_CPPM_CIVRMLCR = 0x220F01B7ull;
+
+static const uint64_t P9N2_C_3_CPPM_CIVRMLCR = 0x230F01B7ull;
+
+static const uint64_t P9N2_C_4_CPPM_CIVRMLCR = 0x240F01B7ull;
+
+static const uint64_t P9N2_C_5_CPPM_CIVRMLCR = 0x250F01B7ull;
+
+static const uint64_t P9N2_C_6_CPPM_CIVRMLCR = 0x260F01B7ull;
+
+static const uint64_t P9N2_C_7_CPPM_CIVRMLCR = 0x270F01B7ull;
+
+static const uint64_t P9N2_C_8_CPPM_CIVRMLCR = 0x280F01B7ull;
+
+static const uint64_t P9N2_C_9_CPPM_CIVRMLCR = 0x290F01B7ull;
+
+static const uint64_t P9N2_C_10_CPPM_CIVRMLCR = 0x2A0F01B7ull;
+
+static const uint64_t P9N2_C_11_CPPM_CIVRMLCR = 0x2B0F01B7ull;
+
+static const uint64_t P9N2_C_12_CPPM_CIVRMLCR = 0x2C0F01B7ull;
+
+static const uint64_t P9N2_C_13_CPPM_CIVRMLCR = 0x2D0F01B7ull;
+
+static const uint64_t P9N2_C_14_CPPM_CIVRMLCR = 0x2E0F01B7ull;
+
+static const uint64_t P9N2_C_15_CPPM_CIVRMLCR = 0x2F0F01B7ull;
+
+static const uint64_t P9N2_C_16_CPPM_CIVRMLCR = 0x300F01B7ull;
+
+static const uint64_t P9N2_C_17_CPPM_CIVRMLCR = 0x310F01B7ull;
+
+static const uint64_t P9N2_C_18_CPPM_CIVRMLCR = 0x320F01B7ull;
+
+static const uint64_t P9N2_C_19_CPPM_CIVRMLCR = 0x330F01B7ull;
+
+static const uint64_t P9N2_C_20_CPPM_CIVRMLCR = 0x340F01B7ull;
+
+static const uint64_t P9N2_C_21_CPPM_CIVRMLCR = 0x350F01B7ull;
+
+static const uint64_t P9N2_C_22_CPPM_CIVRMLCR = 0x360F01B7ull;
+
+static const uint64_t P9N2_C_23_CPPM_CIVRMLCR = 0x370F01B7ull;
+
+static const uint64_t P9N2_EX_CPPM_CIVRMLCR = 0x200F01B7ull;
+//DUPS: 210F01B7,
+static const uint64_t P9N2_EX_0_CPPM_CIVRMLCR = 0x200F01B7ull;
+//DUPS: 210F01B7,
+static const uint64_t P9N2_EX_1_CPPM_CIVRMLCR = 0x220F01B7ull;
+//DUPS: 220F01B7,
+static const uint64_t P9N2_EX_2_CPPM_CIVRMLCR = 0x240F01B7ull;
+//DUPS: 250F01B7,
+static const uint64_t P9N2_EX_3_CPPM_CIVRMLCR = 0x260F01B7ull;
+//DUPS: 270F01B7,
+static const uint64_t P9N2_EX_4_CPPM_CIVRMLCR = 0x280F01B7ull;
+//DUPS: 290F01B7,
+static const uint64_t P9N2_EX_5_CPPM_CIVRMLCR = 0x2A0F01B7ull;
+//DUPS: 2B0F01B7,
+static const uint64_t P9N2_EX_6_CPPM_CIVRMLCR = 0x2C0F01B7ull;
+//DUPS: 2D0F01B7,
+static const uint64_t P9N2_EX_7_CPPM_CIVRMLCR = 0x2E0F01B7ull;
+//DUPS: 2F0F01B7,
+static const uint64_t P9N2_EX_8_CPPM_CIVRMLCR = 0x300F01B7ull;
+//DUPS: 310F01B7,
+static const uint64_t P9N2_EX_9_CPPM_CIVRMLCR = 0x320F01B7ull;
+//DUPS: 330F01B7,
+static const uint64_t P9N2_EX_10_CPPM_CIVRMLCR = 0x340F01B7ull;
+//DUPS: 350F01B7,
+static const uint64_t P9N2_EX_11_CPPM_CIVRMLCR = 0x360F01B7ull;
+//DUPS: 370F01B7,
+
+static const uint64_t P9N2_C_CPPM_CMEDATA = 0x200F01A8ull;
+
+static const uint64_t P9N2_C_CPPM_CMEDATA_CLEAR = 0x200F01A9ull;
+
+static const uint64_t P9N2_C_CPPM_CMEDATA_OR = 0x200F01AAull;
+
+static const uint64_t P9N2_C_0_CPPM_CMEDATA = 0x200F01A8ull;
+
+static const uint64_t P9N2_C_0_CPPM_CMEDATA_CLEAR = 0x200F01A9ull;
+
+static const uint64_t P9N2_C_0_CPPM_CMEDATA_OR = 0x200F01AAull;
+
+static const uint64_t P9N2_C_1_CPPM_CMEDATA = 0x210F01A8ull;
+
+static const uint64_t P9N2_C_1_CPPM_CMEDATA_CLEAR = 0x210F01A9ull;
+
+static const uint64_t P9N2_C_1_CPPM_CMEDATA_OR = 0x210F01AAull;
+
+static const uint64_t P9N2_C_2_CPPM_CMEDATA = 0x220F01A8ull;
+
+static const uint64_t P9N2_C_2_CPPM_CMEDATA_CLEAR = 0x220F01A9ull;
+
+static const uint64_t P9N2_C_2_CPPM_CMEDATA_OR = 0x220F01AAull;
+
+static const uint64_t P9N2_C_3_CPPM_CMEDATA = 0x230F01A8ull;
+
+static const uint64_t P9N2_C_3_CPPM_CMEDATA_CLEAR = 0x230F01A9ull;
+
+static const uint64_t P9N2_C_3_CPPM_CMEDATA_OR = 0x230F01AAull;
+
+static const uint64_t P9N2_C_4_CPPM_CMEDATA = 0x240F01A8ull;
+
+static const uint64_t P9N2_C_4_CPPM_CMEDATA_CLEAR = 0x240F01A9ull;
+
+static const uint64_t P9N2_C_4_CPPM_CMEDATA_OR = 0x240F01AAull;
+
+static const uint64_t P9N2_C_5_CPPM_CMEDATA = 0x250F01A8ull;
+
+static const uint64_t P9N2_C_5_CPPM_CMEDATA_CLEAR = 0x250F01A9ull;
+
+static const uint64_t P9N2_C_5_CPPM_CMEDATA_OR = 0x250F01AAull;
+
+static const uint64_t P9N2_C_6_CPPM_CMEDATA = 0x260F01A8ull;
+
+static const uint64_t P9N2_C_6_CPPM_CMEDATA_CLEAR = 0x260F01A9ull;
+
+static const uint64_t P9N2_C_6_CPPM_CMEDATA_OR = 0x260F01AAull;
+
+static const uint64_t P9N2_C_7_CPPM_CMEDATA = 0x270F01A8ull;
+
+static const uint64_t P9N2_C_7_CPPM_CMEDATA_CLEAR = 0x270F01A9ull;
+
+static const uint64_t P9N2_C_7_CPPM_CMEDATA_OR = 0x270F01AAull;
+
+static const uint64_t P9N2_C_8_CPPM_CMEDATA = 0x280F01A8ull;
+
+static const uint64_t P9N2_C_8_CPPM_CMEDATA_CLEAR = 0x280F01A9ull;
+
+static const uint64_t P9N2_C_8_CPPM_CMEDATA_OR = 0x280F01AAull;
+
+static const uint64_t P9N2_C_9_CPPM_CMEDATA = 0x290F01A8ull;
+
+static const uint64_t P9N2_C_9_CPPM_CMEDATA_CLEAR = 0x290F01A9ull;
+
+static const uint64_t P9N2_C_9_CPPM_CMEDATA_OR = 0x290F01AAull;
+
+static const uint64_t P9N2_C_10_CPPM_CMEDATA = 0x2A0F01A8ull;
+
+static const uint64_t P9N2_C_10_CPPM_CMEDATA_CLEAR = 0x2A0F01A9ull;
+
+static const uint64_t P9N2_C_10_CPPM_CMEDATA_OR = 0x2A0F01AAull;
+
+static const uint64_t P9N2_C_11_CPPM_CMEDATA = 0x2B0F01A8ull;
+
+static const uint64_t P9N2_C_11_CPPM_CMEDATA_CLEAR = 0x2B0F01A9ull;
+
+static const uint64_t P9N2_C_11_CPPM_CMEDATA_OR = 0x2B0F01AAull;
+
+static const uint64_t P9N2_C_12_CPPM_CMEDATA = 0x2C0F01A8ull;
+
+static const uint64_t P9N2_C_12_CPPM_CMEDATA_CLEAR = 0x2C0F01A9ull;
+
+static const uint64_t P9N2_C_12_CPPM_CMEDATA_OR = 0x2C0F01AAull;
+
+static const uint64_t P9N2_C_13_CPPM_CMEDATA = 0x2D0F01A8ull;
+
+static const uint64_t P9N2_C_13_CPPM_CMEDATA_CLEAR = 0x2D0F01A9ull;
+
+static const uint64_t P9N2_C_13_CPPM_CMEDATA_OR = 0x2D0F01AAull;
+
+static const uint64_t P9N2_C_14_CPPM_CMEDATA = 0x2E0F01A8ull;
+
+static const uint64_t P9N2_C_14_CPPM_CMEDATA_CLEAR = 0x2E0F01A9ull;
+
+static const uint64_t P9N2_C_14_CPPM_CMEDATA_OR = 0x2E0F01AAull;
+
+static const uint64_t P9N2_C_15_CPPM_CMEDATA = 0x2F0F01A8ull;
+
+static const uint64_t P9N2_C_15_CPPM_CMEDATA_CLEAR = 0x2F0F01A9ull;
+
+static const uint64_t P9N2_C_15_CPPM_CMEDATA_OR = 0x2F0F01AAull;
+
+static const uint64_t P9N2_C_16_CPPM_CMEDATA = 0x300F01A8ull;
+
+static const uint64_t P9N2_C_16_CPPM_CMEDATA_CLEAR = 0x300F01A9ull;
+
+static const uint64_t P9N2_C_16_CPPM_CMEDATA_OR = 0x300F01AAull;
+
+static const uint64_t P9N2_C_17_CPPM_CMEDATA = 0x310F01A8ull;
+
+static const uint64_t P9N2_C_17_CPPM_CMEDATA_CLEAR = 0x310F01A9ull;
+
+static const uint64_t P9N2_C_17_CPPM_CMEDATA_OR = 0x310F01AAull;
+
+static const uint64_t P9N2_C_18_CPPM_CMEDATA = 0x320F01A8ull;
+
+static const uint64_t P9N2_C_18_CPPM_CMEDATA_CLEAR = 0x320F01A9ull;
+
+static const uint64_t P9N2_C_18_CPPM_CMEDATA_OR = 0x320F01AAull;
+
+static const uint64_t P9N2_C_19_CPPM_CMEDATA = 0x330F01A8ull;
+
+static const uint64_t P9N2_C_19_CPPM_CMEDATA_CLEAR = 0x330F01A9ull;
+
+static const uint64_t P9N2_C_19_CPPM_CMEDATA_OR = 0x330F01AAull;
+
+static const uint64_t P9N2_C_20_CPPM_CMEDATA = 0x340F01A8ull;
+
+static const uint64_t P9N2_C_20_CPPM_CMEDATA_CLEAR = 0x340F01A9ull;
+
+static const uint64_t P9N2_C_20_CPPM_CMEDATA_OR = 0x340F01AAull;
+
+static const uint64_t P9N2_C_21_CPPM_CMEDATA = 0x350F01A8ull;
+
+static const uint64_t P9N2_C_21_CPPM_CMEDATA_CLEAR = 0x350F01A9ull;
+
+static const uint64_t P9N2_C_21_CPPM_CMEDATA_OR = 0x350F01AAull;
+
+static const uint64_t P9N2_C_22_CPPM_CMEDATA = 0x360F01A8ull;
+
+static const uint64_t P9N2_C_22_CPPM_CMEDATA_CLEAR = 0x360F01A9ull;
+
+static const uint64_t P9N2_C_22_CPPM_CMEDATA_OR = 0x360F01AAull;
+
+static const uint64_t P9N2_C_23_CPPM_CMEDATA = 0x370F01A8ull;
+
+static const uint64_t P9N2_C_23_CPPM_CMEDATA_CLEAR = 0x370F01A9ull;
+
+static const uint64_t P9N2_C_23_CPPM_CMEDATA_OR = 0x370F01AAull;
+
+static const uint64_t P9N2_EX_CPPM_CMEDATA = 0x200F01A8ull;
+//DUPS: 210F01A8,
+static const uint64_t P9N2_EX_CPPM_CMEDATA_CLEAR = 0x200F01A9ull;
+//DUPS: 210F01A9,
+static const uint64_t P9N2_EX_CPPM_CMEDATA_OR = 0x200F01AAull;
+//DUPS: 210F01AA,
+static const uint64_t P9N2_EX_0_CPPM_CMEDATA = 0x200F01A8ull;
+//DUPS: 210F01A8,
+static const uint64_t P9N2_EX_0_CPPM_CMEDATA_CLEAR = 0x200F01A9ull;
+//DUPS: 210F01A9,
+static const uint64_t P9N2_EX_0_CPPM_CMEDATA_OR = 0x200F01AAull;
+//DUPS: 210F01AA,
+static const uint64_t P9N2_EX_1_CPPM_CMEDATA = 0x220F01A8ull;
+//DUPS: 220F01A8,
+static const uint64_t P9N2_EX_1_CPPM_CMEDATA_CLEAR = 0x220F01A9ull;
+//DUPS: 220F01A9,
+static const uint64_t P9N2_EX_1_CPPM_CMEDATA_OR = 0x220F01AAull;
+//DUPS: 220F01AA,
+static const uint64_t P9N2_EX_2_CPPM_CMEDATA = 0x240F01A8ull;
+//DUPS: 250F01A8,
+static const uint64_t P9N2_EX_2_CPPM_CMEDATA_CLEAR = 0x240F01A9ull;
+//DUPS: 250F01A9,
+static const uint64_t P9N2_EX_2_CPPM_CMEDATA_OR = 0x240F01AAull;
+//DUPS: 250F01AA,
+static const uint64_t P9N2_EX_3_CPPM_CMEDATA = 0x260F01A8ull;
+//DUPS: 270F01A8,
+static const uint64_t P9N2_EX_3_CPPM_CMEDATA_CLEAR = 0x260F01A9ull;
+//DUPS: 270F01A9,
+static const uint64_t P9N2_EX_3_CPPM_CMEDATA_OR = 0x260F01AAull;
+//DUPS: 270F01AA,
+static const uint64_t P9N2_EX_4_CPPM_CMEDATA = 0x280F01A8ull;
+//DUPS: 290F01A8,
+static const uint64_t P9N2_EX_4_CPPM_CMEDATA_CLEAR = 0x280F01A9ull;
+//DUPS: 290F01A9,
+static const uint64_t P9N2_EX_4_CPPM_CMEDATA_OR = 0x280F01AAull;
+//DUPS: 290F01AA,
+static const uint64_t P9N2_EX_5_CPPM_CMEDATA = 0x2A0F01A8ull;
+//DUPS: 2B0F01A8,
+static const uint64_t P9N2_EX_5_CPPM_CMEDATA_CLEAR = 0x2A0F01A9ull;
+//DUPS: 2B0F01A9,
+static const uint64_t P9N2_EX_5_CPPM_CMEDATA_OR = 0x2A0F01AAull;
+//DUPS: 2B0F01AA,
+static const uint64_t P9N2_EX_6_CPPM_CMEDATA = 0x2C0F01A8ull;
+//DUPS: 2D0F01A8,
+static const uint64_t P9N2_EX_6_CPPM_CMEDATA_CLEAR = 0x2C0F01A9ull;
+//DUPS: 2D0F01A9,
+static const uint64_t P9N2_EX_6_CPPM_CMEDATA_OR = 0x2C0F01AAull;
+//DUPS: 2D0F01AA,
+static const uint64_t P9N2_EX_7_CPPM_CMEDATA = 0x2E0F01A8ull;
+//DUPS: 2F0F01A8,
+static const uint64_t P9N2_EX_7_CPPM_CMEDATA_CLEAR = 0x2E0F01A9ull;
+//DUPS: 2F0F01A9,
+static const uint64_t P9N2_EX_7_CPPM_CMEDATA_OR = 0x2E0F01AAull;
+//DUPS: 2F0F01AA,
+static const uint64_t P9N2_EX_8_CPPM_CMEDATA = 0x300F01A8ull;
+//DUPS: 310F01A8,
+static const uint64_t P9N2_EX_8_CPPM_CMEDATA_CLEAR = 0x300F01A9ull;
+//DUPS: 310F01A9,
+static const uint64_t P9N2_EX_8_CPPM_CMEDATA_OR = 0x300F01AAull;
+//DUPS: 310F01AA,
+static const uint64_t P9N2_EX_9_CPPM_CMEDATA = 0x320F01A8ull;
+//DUPS: 330F01A8,
+static const uint64_t P9N2_EX_9_CPPM_CMEDATA_CLEAR = 0x320F01A9ull;
+//DUPS: 330F01A9,
+static const uint64_t P9N2_EX_9_CPPM_CMEDATA_OR = 0x320F01AAull;
+//DUPS: 330F01AA,
+static const uint64_t P9N2_EX_10_CPPM_CMEDATA = 0x340F01A8ull;
+//DUPS: 350F01A8,
+static const uint64_t P9N2_EX_10_CPPM_CMEDATA_CLEAR = 0x340F01A9ull;
+//DUPS: 350F01A9,
+static const uint64_t P9N2_EX_10_CPPM_CMEDATA_OR = 0x340F01AAull;
+//DUPS: 350F01AA,
+static const uint64_t P9N2_EX_11_CPPM_CMEDATA = 0x360F01A8ull;
+//DUPS: 370F01A8,
+static const uint64_t P9N2_EX_11_CPPM_CMEDATA_CLEAR = 0x360F01A9ull;
+//DUPS: 370F01A9,
+static const uint64_t P9N2_EX_11_CPPM_CMEDATA_OR = 0x360F01AAull;
+//DUPS: 370F01AA,
+
+static const uint64_t P9N2_C_CPPM_CMEDB0 = 0x200F0190ull;
+
+static const uint64_t P9N2_C_CPPM_CMEDB0_CLEAR = 0x200F0191ull;
+
+static const uint64_t P9N2_C_CPPM_CMEDB0_OR = 0x200F0192ull;
+
+static const uint64_t P9N2_C_0_CPPM_CMEDB0 = 0x200F0190ull;
+
+static const uint64_t P9N2_C_0_CPPM_CMEDB0_CLEAR = 0x200F0191ull;
+
+static const uint64_t P9N2_C_0_CPPM_CMEDB0_OR = 0x200F0192ull;
+
+static const uint64_t P9N2_C_1_CPPM_CMEDB0 = 0x210F0190ull;
+
+static const uint64_t P9N2_C_1_CPPM_CMEDB0_CLEAR = 0x210F0191ull;
+
+static const uint64_t P9N2_C_1_CPPM_CMEDB0_OR = 0x210F0192ull;
+
+static const uint64_t P9N2_C_2_CPPM_CMEDB0 = 0x220F0190ull;
+
+static const uint64_t P9N2_C_2_CPPM_CMEDB0_CLEAR = 0x220F0191ull;
+
+static const uint64_t P9N2_C_2_CPPM_CMEDB0_OR = 0x220F0192ull;
+
+static const uint64_t P9N2_C_3_CPPM_CMEDB0 = 0x230F0190ull;
+
+static const uint64_t P9N2_C_3_CPPM_CMEDB0_CLEAR = 0x230F0191ull;
+
+static const uint64_t P9N2_C_3_CPPM_CMEDB0_OR = 0x230F0192ull;
+
+static const uint64_t P9N2_C_4_CPPM_CMEDB0 = 0x240F0190ull;
+
+static const uint64_t P9N2_C_4_CPPM_CMEDB0_CLEAR = 0x240F0191ull;
+
+static const uint64_t P9N2_C_4_CPPM_CMEDB0_OR = 0x240F0192ull;
+
+static const uint64_t P9N2_C_5_CPPM_CMEDB0 = 0x250F0190ull;
+
+static const uint64_t P9N2_C_5_CPPM_CMEDB0_CLEAR = 0x250F0191ull;
+
+static const uint64_t P9N2_C_5_CPPM_CMEDB0_OR = 0x250F0192ull;
+
+static const uint64_t P9N2_C_6_CPPM_CMEDB0 = 0x260F0190ull;
+
+static const uint64_t P9N2_C_6_CPPM_CMEDB0_CLEAR = 0x260F0191ull;
+
+static const uint64_t P9N2_C_6_CPPM_CMEDB0_OR = 0x260F0192ull;
+
+static const uint64_t P9N2_C_7_CPPM_CMEDB0 = 0x270F0190ull;
+
+static const uint64_t P9N2_C_7_CPPM_CMEDB0_CLEAR = 0x270F0191ull;
+
+static const uint64_t P9N2_C_7_CPPM_CMEDB0_OR = 0x270F0192ull;
+
+static const uint64_t P9N2_C_8_CPPM_CMEDB0 = 0x280F0190ull;
+
+static const uint64_t P9N2_C_8_CPPM_CMEDB0_CLEAR = 0x280F0191ull;
+
+static const uint64_t P9N2_C_8_CPPM_CMEDB0_OR = 0x280F0192ull;
+
+static const uint64_t P9N2_C_9_CPPM_CMEDB0 = 0x290F0190ull;
+
+static const uint64_t P9N2_C_9_CPPM_CMEDB0_CLEAR = 0x290F0191ull;
+
+static const uint64_t P9N2_C_9_CPPM_CMEDB0_OR = 0x290F0192ull;
+
+static const uint64_t P9N2_C_10_CPPM_CMEDB0 = 0x2A0F0190ull;
+
+static const uint64_t P9N2_C_10_CPPM_CMEDB0_CLEAR = 0x2A0F0191ull;
+
+static const uint64_t P9N2_C_10_CPPM_CMEDB0_OR = 0x2A0F0192ull;
+
+static const uint64_t P9N2_C_11_CPPM_CMEDB0 = 0x2B0F0190ull;
+
+static const uint64_t P9N2_C_11_CPPM_CMEDB0_CLEAR = 0x2B0F0191ull;
+
+static const uint64_t P9N2_C_11_CPPM_CMEDB0_OR = 0x2B0F0192ull;
+
+static const uint64_t P9N2_C_12_CPPM_CMEDB0 = 0x2C0F0190ull;
+
+static const uint64_t P9N2_C_12_CPPM_CMEDB0_CLEAR = 0x2C0F0191ull;
+
+static const uint64_t P9N2_C_12_CPPM_CMEDB0_OR = 0x2C0F0192ull;
+
+static const uint64_t P9N2_C_13_CPPM_CMEDB0 = 0x2D0F0190ull;
+
+static const uint64_t P9N2_C_13_CPPM_CMEDB0_CLEAR = 0x2D0F0191ull;
+
+static const uint64_t P9N2_C_13_CPPM_CMEDB0_OR = 0x2D0F0192ull;
+
+static const uint64_t P9N2_C_14_CPPM_CMEDB0 = 0x2E0F0190ull;
+
+static const uint64_t P9N2_C_14_CPPM_CMEDB0_CLEAR = 0x2E0F0191ull;
+
+static const uint64_t P9N2_C_14_CPPM_CMEDB0_OR = 0x2E0F0192ull;
+
+static const uint64_t P9N2_C_15_CPPM_CMEDB0 = 0x2F0F0190ull;
+
+static const uint64_t P9N2_C_15_CPPM_CMEDB0_CLEAR = 0x2F0F0191ull;
+
+static const uint64_t P9N2_C_15_CPPM_CMEDB0_OR = 0x2F0F0192ull;
+
+static const uint64_t P9N2_C_16_CPPM_CMEDB0 = 0x300F0190ull;
+
+static const uint64_t P9N2_C_16_CPPM_CMEDB0_CLEAR = 0x300F0191ull;
+
+static const uint64_t P9N2_C_16_CPPM_CMEDB0_OR = 0x300F0192ull;
+
+static const uint64_t P9N2_C_17_CPPM_CMEDB0 = 0x310F0190ull;
+
+static const uint64_t P9N2_C_17_CPPM_CMEDB0_CLEAR = 0x310F0191ull;
+
+static const uint64_t P9N2_C_17_CPPM_CMEDB0_OR = 0x310F0192ull;
+
+static const uint64_t P9N2_C_18_CPPM_CMEDB0 = 0x320F0190ull;
+
+static const uint64_t P9N2_C_18_CPPM_CMEDB0_CLEAR = 0x320F0191ull;
+
+static const uint64_t P9N2_C_18_CPPM_CMEDB0_OR = 0x320F0192ull;
+
+static const uint64_t P9N2_C_19_CPPM_CMEDB0 = 0x330F0190ull;
+
+static const uint64_t P9N2_C_19_CPPM_CMEDB0_CLEAR = 0x330F0191ull;
+
+static const uint64_t P9N2_C_19_CPPM_CMEDB0_OR = 0x330F0192ull;
+
+static const uint64_t P9N2_C_20_CPPM_CMEDB0 = 0x340F0190ull;
+
+static const uint64_t P9N2_C_20_CPPM_CMEDB0_CLEAR = 0x340F0191ull;
+
+static const uint64_t P9N2_C_20_CPPM_CMEDB0_OR = 0x340F0192ull;
+
+static const uint64_t P9N2_C_21_CPPM_CMEDB0 = 0x350F0190ull;
+
+static const uint64_t P9N2_C_21_CPPM_CMEDB0_CLEAR = 0x350F0191ull;
+
+static const uint64_t P9N2_C_21_CPPM_CMEDB0_OR = 0x350F0192ull;
+
+static const uint64_t P9N2_C_22_CPPM_CMEDB0 = 0x360F0190ull;
+
+static const uint64_t P9N2_C_22_CPPM_CMEDB0_CLEAR = 0x360F0191ull;
+
+static const uint64_t P9N2_C_22_CPPM_CMEDB0_OR = 0x360F0192ull;
+
+static const uint64_t P9N2_C_23_CPPM_CMEDB0 = 0x370F0190ull;
+
+static const uint64_t P9N2_C_23_CPPM_CMEDB0_CLEAR = 0x370F0191ull;
+
+static const uint64_t P9N2_C_23_CPPM_CMEDB0_OR = 0x370F0192ull;
+
+static const uint64_t P9N2_EX_CPPM_CMEDB0 = 0x200F0190ull;
+//DUPS: 210F0190,
+static const uint64_t P9N2_EX_CPPM_CMEDB0_CLEAR = 0x200F0191ull;
+//DUPS: 210F0191,
+static const uint64_t P9N2_EX_CPPM_CMEDB0_OR = 0x200F0192ull;
+//DUPS: 210F0192,
+static const uint64_t P9N2_EX_0_CPPM_CMEDB0 = 0x200F0190ull;
+//DUPS: 210F0190,
+static const uint64_t P9N2_EX_0_CPPM_CMEDB0_CLEAR = 0x200F0191ull;
+//DUPS: 210F0191,
+static const uint64_t P9N2_EX_0_CPPM_CMEDB0_OR = 0x200F0192ull;
+//DUPS: 210F0192,
+static const uint64_t P9N2_EX_1_CPPM_CMEDB0 = 0x220F0190ull;
+//DUPS: 220F0190,
+static const uint64_t P9N2_EX_1_CPPM_CMEDB0_CLEAR = 0x220F0191ull;
+//DUPS: 220F0191,
+static const uint64_t P9N2_EX_1_CPPM_CMEDB0_OR = 0x220F0192ull;
+//DUPS: 220F0192,
+static const uint64_t P9N2_EX_2_CPPM_CMEDB0 = 0x240F0190ull;
+//DUPS: 250F0190,
+static const uint64_t P9N2_EX_2_CPPM_CMEDB0_CLEAR = 0x240F0191ull;
+//DUPS: 250F0191,
+static const uint64_t P9N2_EX_2_CPPM_CMEDB0_OR = 0x240F0192ull;
+//DUPS: 250F0192,
+static const uint64_t P9N2_EX_3_CPPM_CMEDB0 = 0x260F0190ull;
+//DUPS: 270F0190,
+static const uint64_t P9N2_EX_3_CPPM_CMEDB0_CLEAR = 0x260F0191ull;
+//DUPS: 270F0191,
+static const uint64_t P9N2_EX_3_CPPM_CMEDB0_OR = 0x260F0192ull;
+//DUPS: 270F0192,
+static const uint64_t P9N2_EX_4_CPPM_CMEDB0 = 0x280F0190ull;
+//DUPS: 290F0190,
+static const uint64_t P9N2_EX_4_CPPM_CMEDB0_CLEAR = 0x280F0191ull;
+//DUPS: 290F0191,
+static const uint64_t P9N2_EX_4_CPPM_CMEDB0_OR = 0x280F0192ull;
+//DUPS: 290F0192,
+static const uint64_t P9N2_EX_5_CPPM_CMEDB0 = 0x2A0F0190ull;
+//DUPS: 2B0F0190,
+static const uint64_t P9N2_EX_5_CPPM_CMEDB0_CLEAR = 0x2A0F0191ull;
+//DUPS: 2B0F0191,
+static const uint64_t P9N2_EX_5_CPPM_CMEDB0_OR = 0x2A0F0192ull;
+//DUPS: 2B0F0192,
+static const uint64_t P9N2_EX_6_CPPM_CMEDB0 = 0x2C0F0190ull;
+//DUPS: 2D0F0190,
+static const uint64_t P9N2_EX_6_CPPM_CMEDB0_CLEAR = 0x2C0F0191ull;
+//DUPS: 2D0F0191,
+static const uint64_t P9N2_EX_6_CPPM_CMEDB0_OR = 0x2C0F0192ull;
+//DUPS: 2D0F0192,
+static const uint64_t P9N2_EX_7_CPPM_CMEDB0 = 0x2E0F0190ull;
+//DUPS: 2F0F0190,
+static const uint64_t P9N2_EX_7_CPPM_CMEDB0_CLEAR = 0x2E0F0191ull;
+//DUPS: 2F0F0191,
+static const uint64_t P9N2_EX_7_CPPM_CMEDB0_OR = 0x2E0F0192ull;
+//DUPS: 2F0F0192,
+static const uint64_t P9N2_EX_8_CPPM_CMEDB0 = 0x300F0190ull;
+//DUPS: 310F0190,
+static const uint64_t P9N2_EX_8_CPPM_CMEDB0_CLEAR = 0x300F0191ull;
+//DUPS: 310F0191,
+static const uint64_t P9N2_EX_8_CPPM_CMEDB0_OR = 0x300F0192ull;
+//DUPS: 310F0192,
+static const uint64_t P9N2_EX_9_CPPM_CMEDB0 = 0x320F0190ull;
+//DUPS: 330F0190,
+static const uint64_t P9N2_EX_9_CPPM_CMEDB0_CLEAR = 0x320F0191ull;
+//DUPS: 330F0191,
+static const uint64_t P9N2_EX_9_CPPM_CMEDB0_OR = 0x320F0192ull;
+//DUPS: 330F0192,
+static const uint64_t P9N2_EX_10_CPPM_CMEDB0 = 0x340F0190ull;
+//DUPS: 350F0190,
+static const uint64_t P9N2_EX_10_CPPM_CMEDB0_CLEAR = 0x340F0191ull;
+//DUPS: 350F0191,
+static const uint64_t P9N2_EX_10_CPPM_CMEDB0_OR = 0x340F0192ull;
+//DUPS: 350F0192,
+static const uint64_t P9N2_EX_11_CPPM_CMEDB0 = 0x360F0190ull;
+//DUPS: 370F0190,
+static const uint64_t P9N2_EX_11_CPPM_CMEDB0_CLEAR = 0x360F0191ull;
+//DUPS: 370F0191,
+static const uint64_t P9N2_EX_11_CPPM_CMEDB0_OR = 0x360F0192ull;
+//DUPS: 370F0192,
+
+static const uint64_t P9N2_C_CPPM_CMEDB1 = 0x200F0194ull;
+
+static const uint64_t P9N2_C_CPPM_CMEDB1_CLEAR = 0x200F0195ull;
+
+static const uint64_t P9N2_C_CPPM_CMEDB1_OR = 0x200F0196ull;
+
+static const uint64_t P9N2_C_0_CPPM_CMEDB1 = 0x200F0194ull;
+
+static const uint64_t P9N2_C_0_CPPM_CMEDB1_CLEAR = 0x200F0195ull;
+
+static const uint64_t P9N2_C_0_CPPM_CMEDB1_OR = 0x200F0196ull;
+
+static const uint64_t P9N2_C_1_CPPM_CMEDB1 = 0x210F0194ull;
+
+static const uint64_t P9N2_C_1_CPPM_CMEDB1_CLEAR = 0x210F0195ull;
+
+static const uint64_t P9N2_C_1_CPPM_CMEDB1_OR = 0x210F0196ull;
+
+static const uint64_t P9N2_C_2_CPPM_CMEDB1 = 0x220F0194ull;
+
+static const uint64_t P9N2_C_2_CPPM_CMEDB1_CLEAR = 0x220F0195ull;
+
+static const uint64_t P9N2_C_2_CPPM_CMEDB1_OR = 0x220F0196ull;
+
+static const uint64_t P9N2_C_3_CPPM_CMEDB1 = 0x230F0194ull;
+
+static const uint64_t P9N2_C_3_CPPM_CMEDB1_CLEAR = 0x230F0195ull;
+
+static const uint64_t P9N2_C_3_CPPM_CMEDB1_OR = 0x230F0196ull;
+
+static const uint64_t P9N2_C_4_CPPM_CMEDB1 = 0x240F0194ull;
+
+static const uint64_t P9N2_C_4_CPPM_CMEDB1_CLEAR = 0x240F0195ull;
+
+static const uint64_t P9N2_C_4_CPPM_CMEDB1_OR = 0x240F0196ull;
+
+static const uint64_t P9N2_C_5_CPPM_CMEDB1 = 0x250F0194ull;
+
+static const uint64_t P9N2_C_5_CPPM_CMEDB1_CLEAR = 0x250F0195ull;
+
+static const uint64_t P9N2_C_5_CPPM_CMEDB1_OR = 0x250F0196ull;
+
+static const uint64_t P9N2_C_6_CPPM_CMEDB1 = 0x260F0194ull;
+
+static const uint64_t P9N2_C_6_CPPM_CMEDB1_CLEAR = 0x260F0195ull;
+
+static const uint64_t P9N2_C_6_CPPM_CMEDB1_OR = 0x260F0196ull;
+
+static const uint64_t P9N2_C_7_CPPM_CMEDB1 = 0x270F0194ull;
+
+static const uint64_t P9N2_C_7_CPPM_CMEDB1_CLEAR = 0x270F0195ull;
+
+static const uint64_t P9N2_C_7_CPPM_CMEDB1_OR = 0x270F0196ull;
+
+static const uint64_t P9N2_C_8_CPPM_CMEDB1 = 0x280F0194ull;
+
+static const uint64_t P9N2_C_8_CPPM_CMEDB1_CLEAR = 0x280F0195ull;
+
+static const uint64_t P9N2_C_8_CPPM_CMEDB1_OR = 0x280F0196ull;
+
+static const uint64_t P9N2_C_9_CPPM_CMEDB1 = 0x290F0194ull;
+
+static const uint64_t P9N2_C_9_CPPM_CMEDB1_CLEAR = 0x290F0195ull;
+
+static const uint64_t P9N2_C_9_CPPM_CMEDB1_OR = 0x290F0196ull;
+
+static const uint64_t P9N2_C_10_CPPM_CMEDB1 = 0x2A0F0194ull;
+
+static const uint64_t P9N2_C_10_CPPM_CMEDB1_CLEAR = 0x2A0F0195ull;
+
+static const uint64_t P9N2_C_10_CPPM_CMEDB1_OR = 0x2A0F0196ull;
+
+static const uint64_t P9N2_C_11_CPPM_CMEDB1 = 0x2B0F0194ull;
+
+static const uint64_t P9N2_C_11_CPPM_CMEDB1_CLEAR = 0x2B0F0195ull;
+
+static const uint64_t P9N2_C_11_CPPM_CMEDB1_OR = 0x2B0F0196ull;
+
+static const uint64_t P9N2_C_12_CPPM_CMEDB1 = 0x2C0F0194ull;
+
+static const uint64_t P9N2_C_12_CPPM_CMEDB1_CLEAR = 0x2C0F0195ull;
+
+static const uint64_t P9N2_C_12_CPPM_CMEDB1_OR = 0x2C0F0196ull;
+
+static const uint64_t P9N2_C_13_CPPM_CMEDB1 = 0x2D0F0194ull;
+
+static const uint64_t P9N2_C_13_CPPM_CMEDB1_CLEAR = 0x2D0F0195ull;
+
+static const uint64_t P9N2_C_13_CPPM_CMEDB1_OR = 0x2D0F0196ull;
+
+static const uint64_t P9N2_C_14_CPPM_CMEDB1 = 0x2E0F0194ull;
+
+static const uint64_t P9N2_C_14_CPPM_CMEDB1_CLEAR = 0x2E0F0195ull;
+
+static const uint64_t P9N2_C_14_CPPM_CMEDB1_OR = 0x2E0F0196ull;
+
+static const uint64_t P9N2_C_15_CPPM_CMEDB1 = 0x2F0F0194ull;
+
+static const uint64_t P9N2_C_15_CPPM_CMEDB1_CLEAR = 0x2F0F0195ull;
+
+static const uint64_t P9N2_C_15_CPPM_CMEDB1_OR = 0x2F0F0196ull;
+
+static const uint64_t P9N2_C_16_CPPM_CMEDB1 = 0x300F0194ull;
+
+static const uint64_t P9N2_C_16_CPPM_CMEDB1_CLEAR = 0x300F0195ull;
+
+static const uint64_t P9N2_C_16_CPPM_CMEDB1_OR = 0x300F0196ull;
+
+static const uint64_t P9N2_C_17_CPPM_CMEDB1 = 0x310F0194ull;
+
+static const uint64_t P9N2_C_17_CPPM_CMEDB1_CLEAR = 0x310F0195ull;
+
+static const uint64_t P9N2_C_17_CPPM_CMEDB1_OR = 0x310F0196ull;
+
+static const uint64_t P9N2_C_18_CPPM_CMEDB1 = 0x320F0194ull;
+
+static const uint64_t P9N2_C_18_CPPM_CMEDB1_CLEAR = 0x320F0195ull;
+
+static const uint64_t P9N2_C_18_CPPM_CMEDB1_OR = 0x320F0196ull;
+
+static const uint64_t P9N2_C_19_CPPM_CMEDB1 = 0x330F0194ull;
+
+static const uint64_t P9N2_C_19_CPPM_CMEDB1_CLEAR = 0x330F0195ull;
+
+static const uint64_t P9N2_C_19_CPPM_CMEDB1_OR = 0x330F0196ull;
+
+static const uint64_t P9N2_C_20_CPPM_CMEDB1 = 0x340F0194ull;
+
+static const uint64_t P9N2_C_20_CPPM_CMEDB1_CLEAR = 0x340F0195ull;
+
+static const uint64_t P9N2_C_20_CPPM_CMEDB1_OR = 0x340F0196ull;
+
+static const uint64_t P9N2_C_21_CPPM_CMEDB1 = 0x350F0194ull;
+
+static const uint64_t P9N2_C_21_CPPM_CMEDB1_CLEAR = 0x350F0195ull;
+
+static const uint64_t P9N2_C_21_CPPM_CMEDB1_OR = 0x350F0196ull;
+
+static const uint64_t P9N2_C_22_CPPM_CMEDB1 = 0x360F0194ull;
+
+static const uint64_t P9N2_C_22_CPPM_CMEDB1_CLEAR = 0x360F0195ull;
+
+static const uint64_t P9N2_C_22_CPPM_CMEDB1_OR = 0x360F0196ull;
+
+static const uint64_t P9N2_C_23_CPPM_CMEDB1 = 0x370F0194ull;
+
+static const uint64_t P9N2_C_23_CPPM_CMEDB1_CLEAR = 0x370F0195ull;
+
+static const uint64_t P9N2_C_23_CPPM_CMEDB1_OR = 0x370F0196ull;
+
+static const uint64_t P9N2_EX_CPPM_CMEDB1 = 0x200F0194ull;
+//DUPS: 210F0194,
+static const uint64_t P9N2_EX_CPPM_CMEDB1_CLEAR = 0x200F0195ull;
+//DUPS: 210F0195,
+static const uint64_t P9N2_EX_CPPM_CMEDB1_OR = 0x200F0196ull;
+//DUPS: 210F0196,
+static const uint64_t P9N2_EX_0_CPPM_CMEDB1 = 0x200F0194ull;
+//DUPS: 210F0194,
+static const uint64_t P9N2_EX_0_CPPM_CMEDB1_CLEAR = 0x200F0195ull;
+//DUPS: 210F0195,
+static const uint64_t P9N2_EX_0_CPPM_CMEDB1_OR = 0x200F0196ull;
+//DUPS: 210F0196,
+static const uint64_t P9N2_EX_1_CPPM_CMEDB1 = 0x220F0194ull;
+//DUPS: 220F0194,
+static const uint64_t P9N2_EX_1_CPPM_CMEDB1_CLEAR = 0x220F0195ull;
+//DUPS: 220F0195,
+static const uint64_t P9N2_EX_1_CPPM_CMEDB1_OR = 0x220F0196ull;
+//DUPS: 220F0196,
+static const uint64_t P9N2_EX_2_CPPM_CMEDB1 = 0x240F0194ull;
+//DUPS: 250F0194,
+static const uint64_t P9N2_EX_2_CPPM_CMEDB1_CLEAR = 0x240F0195ull;
+//DUPS: 250F0195,
+static const uint64_t P9N2_EX_2_CPPM_CMEDB1_OR = 0x240F0196ull;
+//DUPS: 250F0196,
+static const uint64_t P9N2_EX_3_CPPM_CMEDB1 = 0x260F0194ull;
+//DUPS: 270F0194,
+static const uint64_t P9N2_EX_3_CPPM_CMEDB1_CLEAR = 0x260F0195ull;
+//DUPS: 270F0195,
+static const uint64_t P9N2_EX_3_CPPM_CMEDB1_OR = 0x260F0196ull;
+//DUPS: 270F0196,
+static const uint64_t P9N2_EX_4_CPPM_CMEDB1 = 0x280F0194ull;
+//DUPS: 290F0194,
+static const uint64_t P9N2_EX_4_CPPM_CMEDB1_CLEAR = 0x280F0195ull;
+//DUPS: 290F0195,
+static const uint64_t P9N2_EX_4_CPPM_CMEDB1_OR = 0x280F0196ull;
+//DUPS: 290F0196,
+static const uint64_t P9N2_EX_5_CPPM_CMEDB1 = 0x2A0F0194ull;
+//DUPS: 2B0F0194,
+static const uint64_t P9N2_EX_5_CPPM_CMEDB1_CLEAR = 0x2A0F0195ull;
+//DUPS: 2B0F0195,
+static const uint64_t P9N2_EX_5_CPPM_CMEDB1_OR = 0x2A0F0196ull;
+//DUPS: 2B0F0196,
+static const uint64_t P9N2_EX_6_CPPM_CMEDB1 = 0x2C0F0194ull;
+//DUPS: 2D0F0194,
+static const uint64_t P9N2_EX_6_CPPM_CMEDB1_CLEAR = 0x2C0F0195ull;
+//DUPS: 2D0F0195,
+static const uint64_t P9N2_EX_6_CPPM_CMEDB1_OR = 0x2C0F0196ull;
+//DUPS: 2D0F0196,
+static const uint64_t P9N2_EX_7_CPPM_CMEDB1 = 0x2E0F0194ull;
+//DUPS: 2F0F0194,
+static const uint64_t P9N2_EX_7_CPPM_CMEDB1_CLEAR = 0x2E0F0195ull;
+//DUPS: 2F0F0195,
+static const uint64_t P9N2_EX_7_CPPM_CMEDB1_OR = 0x2E0F0196ull;
+//DUPS: 2F0F0196,
+static const uint64_t P9N2_EX_8_CPPM_CMEDB1 = 0x300F0194ull;
+//DUPS: 310F0194,
+static const uint64_t P9N2_EX_8_CPPM_CMEDB1_CLEAR = 0x300F0195ull;
+//DUPS: 310F0195,
+static const uint64_t P9N2_EX_8_CPPM_CMEDB1_OR = 0x300F0196ull;
+//DUPS: 310F0196,
+static const uint64_t P9N2_EX_9_CPPM_CMEDB1 = 0x320F0194ull;
+//DUPS: 330F0194,
+static const uint64_t P9N2_EX_9_CPPM_CMEDB1_CLEAR = 0x320F0195ull;
+//DUPS: 330F0195,
+static const uint64_t P9N2_EX_9_CPPM_CMEDB1_OR = 0x320F0196ull;
+//DUPS: 330F0196,
+static const uint64_t P9N2_EX_10_CPPM_CMEDB1 = 0x340F0194ull;
+//DUPS: 350F0194,
+static const uint64_t P9N2_EX_10_CPPM_CMEDB1_CLEAR = 0x340F0195ull;
+//DUPS: 350F0195,
+static const uint64_t P9N2_EX_10_CPPM_CMEDB1_OR = 0x340F0196ull;
+//DUPS: 350F0196,
+static const uint64_t P9N2_EX_11_CPPM_CMEDB1 = 0x360F0194ull;
+//DUPS: 370F0194,
+static const uint64_t P9N2_EX_11_CPPM_CMEDB1_CLEAR = 0x360F0195ull;
+//DUPS: 370F0195,
+static const uint64_t P9N2_EX_11_CPPM_CMEDB1_OR = 0x360F0196ull;
+//DUPS: 370F0196,
+
+static const uint64_t P9N2_C_CPPM_CMEDB2 = 0x200F0198ull;
+
+static const uint64_t P9N2_C_CPPM_CMEDB2_CLEAR = 0x200F0199ull;
+
+static const uint64_t P9N2_C_CPPM_CMEDB2_OR = 0x200F019Aull;
+
+static const uint64_t P9N2_C_0_CPPM_CMEDB2 = 0x200F0198ull;
+
+static const uint64_t P9N2_C_0_CPPM_CMEDB2_CLEAR = 0x200F0199ull;
+
+static const uint64_t P9N2_C_0_CPPM_CMEDB2_OR = 0x200F019Aull;
+
+static const uint64_t P9N2_C_1_CPPM_CMEDB2 = 0x210F0198ull;
+
+static const uint64_t P9N2_C_1_CPPM_CMEDB2_CLEAR = 0x210F0199ull;
+
+static const uint64_t P9N2_C_1_CPPM_CMEDB2_OR = 0x210F019Aull;
+
+static const uint64_t P9N2_C_2_CPPM_CMEDB2 = 0x220F0198ull;
+
+static const uint64_t P9N2_C_2_CPPM_CMEDB2_CLEAR = 0x220F0199ull;
+
+static const uint64_t P9N2_C_2_CPPM_CMEDB2_OR = 0x220F019Aull;
+
+static const uint64_t P9N2_C_3_CPPM_CMEDB2 = 0x230F0198ull;
+
+static const uint64_t P9N2_C_3_CPPM_CMEDB2_CLEAR = 0x230F0199ull;
+
+static const uint64_t P9N2_C_3_CPPM_CMEDB2_OR = 0x230F019Aull;
+
+static const uint64_t P9N2_C_4_CPPM_CMEDB2 = 0x240F0198ull;
+
+static const uint64_t P9N2_C_4_CPPM_CMEDB2_CLEAR = 0x240F0199ull;
+
+static const uint64_t P9N2_C_4_CPPM_CMEDB2_OR = 0x240F019Aull;
+
+static const uint64_t P9N2_C_5_CPPM_CMEDB2 = 0x250F0198ull;
+
+static const uint64_t P9N2_C_5_CPPM_CMEDB2_CLEAR = 0x250F0199ull;
+
+static const uint64_t P9N2_C_5_CPPM_CMEDB2_OR = 0x250F019Aull;
+
+static const uint64_t P9N2_C_6_CPPM_CMEDB2 = 0x260F0198ull;
+
+static const uint64_t P9N2_C_6_CPPM_CMEDB2_CLEAR = 0x260F0199ull;
+
+static const uint64_t P9N2_C_6_CPPM_CMEDB2_OR = 0x260F019Aull;
+
+static const uint64_t P9N2_C_7_CPPM_CMEDB2 = 0x270F0198ull;
+
+static const uint64_t P9N2_C_7_CPPM_CMEDB2_CLEAR = 0x270F0199ull;
+
+static const uint64_t P9N2_C_7_CPPM_CMEDB2_OR = 0x270F019Aull;
+
+static const uint64_t P9N2_C_8_CPPM_CMEDB2 = 0x280F0198ull;
+
+static const uint64_t P9N2_C_8_CPPM_CMEDB2_CLEAR = 0x280F0199ull;
+
+static const uint64_t P9N2_C_8_CPPM_CMEDB2_OR = 0x280F019Aull;
+
+static const uint64_t P9N2_C_9_CPPM_CMEDB2 = 0x290F0198ull;
+
+static const uint64_t P9N2_C_9_CPPM_CMEDB2_CLEAR = 0x290F0199ull;
+
+static const uint64_t P9N2_C_9_CPPM_CMEDB2_OR = 0x290F019Aull;
+
+static const uint64_t P9N2_C_10_CPPM_CMEDB2 = 0x2A0F0198ull;
+
+static const uint64_t P9N2_C_10_CPPM_CMEDB2_CLEAR = 0x2A0F0199ull;
+
+static const uint64_t P9N2_C_10_CPPM_CMEDB2_OR = 0x2A0F019Aull;
+
+static const uint64_t P9N2_C_11_CPPM_CMEDB2 = 0x2B0F0198ull;
+
+static const uint64_t P9N2_C_11_CPPM_CMEDB2_CLEAR = 0x2B0F0199ull;
+
+static const uint64_t P9N2_C_11_CPPM_CMEDB2_OR = 0x2B0F019Aull;
+
+static const uint64_t P9N2_C_12_CPPM_CMEDB2 = 0x2C0F0198ull;
+
+static const uint64_t P9N2_C_12_CPPM_CMEDB2_CLEAR = 0x2C0F0199ull;
+
+static const uint64_t P9N2_C_12_CPPM_CMEDB2_OR = 0x2C0F019Aull;
+
+static const uint64_t P9N2_C_13_CPPM_CMEDB2 = 0x2D0F0198ull;
+
+static const uint64_t P9N2_C_13_CPPM_CMEDB2_CLEAR = 0x2D0F0199ull;
+
+static const uint64_t P9N2_C_13_CPPM_CMEDB2_OR = 0x2D0F019Aull;
+
+static const uint64_t P9N2_C_14_CPPM_CMEDB2 = 0x2E0F0198ull;
+
+static const uint64_t P9N2_C_14_CPPM_CMEDB2_CLEAR = 0x2E0F0199ull;
+
+static const uint64_t P9N2_C_14_CPPM_CMEDB2_OR = 0x2E0F019Aull;
+
+static const uint64_t P9N2_C_15_CPPM_CMEDB2 = 0x2F0F0198ull;
+
+static const uint64_t P9N2_C_15_CPPM_CMEDB2_CLEAR = 0x2F0F0199ull;
+
+static const uint64_t P9N2_C_15_CPPM_CMEDB2_OR = 0x2F0F019Aull;
+
+static const uint64_t P9N2_C_16_CPPM_CMEDB2 = 0x300F0198ull;
+
+static const uint64_t P9N2_C_16_CPPM_CMEDB2_CLEAR = 0x300F0199ull;
+
+static const uint64_t P9N2_C_16_CPPM_CMEDB2_OR = 0x300F019Aull;
+
+static const uint64_t P9N2_C_17_CPPM_CMEDB2 = 0x310F0198ull;
+
+static const uint64_t P9N2_C_17_CPPM_CMEDB2_CLEAR = 0x310F0199ull;
+
+static const uint64_t P9N2_C_17_CPPM_CMEDB2_OR = 0x310F019Aull;
+
+static const uint64_t P9N2_C_18_CPPM_CMEDB2 = 0x320F0198ull;
+
+static const uint64_t P9N2_C_18_CPPM_CMEDB2_CLEAR = 0x320F0199ull;
+
+static const uint64_t P9N2_C_18_CPPM_CMEDB2_OR = 0x320F019Aull;
+
+static const uint64_t P9N2_C_19_CPPM_CMEDB2 = 0x330F0198ull;
+
+static const uint64_t P9N2_C_19_CPPM_CMEDB2_CLEAR = 0x330F0199ull;
+
+static const uint64_t P9N2_C_19_CPPM_CMEDB2_OR = 0x330F019Aull;
+
+static const uint64_t P9N2_C_20_CPPM_CMEDB2 = 0x340F0198ull;
+
+static const uint64_t P9N2_C_20_CPPM_CMEDB2_CLEAR = 0x340F0199ull;
+
+static const uint64_t P9N2_C_20_CPPM_CMEDB2_OR = 0x340F019Aull;
+
+static const uint64_t P9N2_C_21_CPPM_CMEDB2 = 0x350F0198ull;
+
+static const uint64_t P9N2_C_21_CPPM_CMEDB2_CLEAR = 0x350F0199ull;
+
+static const uint64_t P9N2_C_21_CPPM_CMEDB2_OR = 0x350F019Aull;
+
+static const uint64_t P9N2_C_22_CPPM_CMEDB2 = 0x360F0198ull;
+
+static const uint64_t P9N2_C_22_CPPM_CMEDB2_CLEAR = 0x360F0199ull;
+
+static const uint64_t P9N2_C_22_CPPM_CMEDB2_OR = 0x360F019Aull;
+
+static const uint64_t P9N2_C_23_CPPM_CMEDB2 = 0x370F0198ull;
+
+static const uint64_t P9N2_C_23_CPPM_CMEDB2_CLEAR = 0x370F0199ull;
+
+static const uint64_t P9N2_C_23_CPPM_CMEDB2_OR = 0x370F019Aull;
+
+static const uint64_t P9N2_EX_CPPM_CMEDB2 = 0x200F0198ull;
+//DUPS: 210F0198,
+static const uint64_t P9N2_EX_CPPM_CMEDB2_CLEAR = 0x200F0199ull;
+//DUPS: 210F0199,
+static const uint64_t P9N2_EX_CPPM_CMEDB2_OR = 0x200F019Aull;
+//DUPS: 210F019A,
+static const uint64_t P9N2_EX_0_CPPM_CMEDB2 = 0x200F0198ull;
+//DUPS: 210F0198,
+static const uint64_t P9N2_EX_0_CPPM_CMEDB2_CLEAR = 0x200F0199ull;
+//DUPS: 210F0199,
+static const uint64_t P9N2_EX_0_CPPM_CMEDB2_OR = 0x200F019Aull;
+//DUPS: 210F019A,
+static const uint64_t P9N2_EX_1_CPPM_CMEDB2 = 0x220F0198ull;
+//DUPS: 220F0198,
+static const uint64_t P9N2_EX_1_CPPM_CMEDB2_CLEAR = 0x220F0199ull;
+//DUPS: 220F0199,
+static const uint64_t P9N2_EX_1_CPPM_CMEDB2_OR = 0x220F019Aull;
+//DUPS: 220F019A,
+static const uint64_t P9N2_EX_2_CPPM_CMEDB2 = 0x240F0198ull;
+//DUPS: 250F0198,
+static const uint64_t P9N2_EX_2_CPPM_CMEDB2_CLEAR = 0x240F0199ull;
+//DUPS: 250F0199,
+static const uint64_t P9N2_EX_2_CPPM_CMEDB2_OR = 0x240F019Aull;
+//DUPS: 250F019A,
+static const uint64_t P9N2_EX_3_CPPM_CMEDB2 = 0x260F0198ull;
+//DUPS: 270F0198,
+static const uint64_t P9N2_EX_3_CPPM_CMEDB2_CLEAR = 0x260F0199ull;
+//DUPS: 270F0199,
+static const uint64_t P9N2_EX_3_CPPM_CMEDB2_OR = 0x260F019Aull;
+//DUPS: 270F019A,
+static const uint64_t P9N2_EX_4_CPPM_CMEDB2 = 0x280F0198ull;
+//DUPS: 290F0198,
+static const uint64_t P9N2_EX_4_CPPM_CMEDB2_CLEAR = 0x280F0199ull;
+//DUPS: 290F0199,
+static const uint64_t P9N2_EX_4_CPPM_CMEDB2_OR = 0x280F019Aull;
+//DUPS: 290F019A,
+static const uint64_t P9N2_EX_5_CPPM_CMEDB2 = 0x2A0F0198ull;
+//DUPS: 2B0F0198,
+static const uint64_t P9N2_EX_5_CPPM_CMEDB2_CLEAR = 0x2A0F0199ull;
+//DUPS: 2B0F0199,
+static const uint64_t P9N2_EX_5_CPPM_CMEDB2_OR = 0x2A0F019Aull;
+//DUPS: 2B0F019A,
+static const uint64_t P9N2_EX_6_CPPM_CMEDB2 = 0x2C0F0198ull;
+//DUPS: 2D0F0198,
+static const uint64_t P9N2_EX_6_CPPM_CMEDB2_CLEAR = 0x2C0F0199ull;
+//DUPS: 2D0F0199,
+static const uint64_t P9N2_EX_6_CPPM_CMEDB2_OR = 0x2C0F019Aull;
+//DUPS: 2D0F019A,
+static const uint64_t P9N2_EX_7_CPPM_CMEDB2 = 0x2E0F0198ull;
+//DUPS: 2F0F0198,
+static const uint64_t P9N2_EX_7_CPPM_CMEDB2_CLEAR = 0x2E0F0199ull;
+//DUPS: 2F0F0199,
+static const uint64_t P9N2_EX_7_CPPM_CMEDB2_OR = 0x2E0F019Aull;
+//DUPS: 2F0F019A,
+static const uint64_t P9N2_EX_8_CPPM_CMEDB2 = 0x300F0198ull;
+//DUPS: 310F0198,
+static const uint64_t P9N2_EX_8_CPPM_CMEDB2_CLEAR = 0x300F0199ull;
+//DUPS: 310F0199,
+static const uint64_t P9N2_EX_8_CPPM_CMEDB2_OR = 0x300F019Aull;
+//DUPS: 310F019A,
+static const uint64_t P9N2_EX_9_CPPM_CMEDB2 = 0x320F0198ull;
+//DUPS: 330F0198,
+static const uint64_t P9N2_EX_9_CPPM_CMEDB2_CLEAR = 0x320F0199ull;
+//DUPS: 330F0199,
+static const uint64_t P9N2_EX_9_CPPM_CMEDB2_OR = 0x320F019Aull;
+//DUPS: 330F019A,
+static const uint64_t P9N2_EX_10_CPPM_CMEDB2 = 0x340F0198ull;
+//DUPS: 350F0198,
+static const uint64_t P9N2_EX_10_CPPM_CMEDB2_CLEAR = 0x340F0199ull;
+//DUPS: 350F0199,
+static const uint64_t P9N2_EX_10_CPPM_CMEDB2_OR = 0x340F019Aull;
+//DUPS: 350F019A,
+static const uint64_t P9N2_EX_11_CPPM_CMEDB2 = 0x360F0198ull;
+//DUPS: 370F0198,
+static const uint64_t P9N2_EX_11_CPPM_CMEDB2_CLEAR = 0x360F0199ull;
+//DUPS: 370F0199,
+static const uint64_t P9N2_EX_11_CPPM_CMEDB2_OR = 0x360F019Aull;
+//DUPS: 370F019A,
+
+static const uint64_t P9N2_C_CPPM_CMEDB3 = 0x200F019Cull;
+
+static const uint64_t P9N2_C_CPPM_CMEDB3_CLEAR = 0x200F019Dull;
+
+static const uint64_t P9N2_C_CPPM_CMEDB3_OR = 0x200F019Eull;
+
+static const uint64_t P9N2_C_0_CPPM_CMEDB3 = 0x200F019Cull;
+
+static const uint64_t P9N2_C_0_CPPM_CMEDB3_CLEAR = 0x200F019Dull;
+
+static const uint64_t P9N2_C_0_CPPM_CMEDB3_OR = 0x200F019Eull;
+
+static const uint64_t P9N2_C_1_CPPM_CMEDB3 = 0x210F019Cull;
+
+static const uint64_t P9N2_C_1_CPPM_CMEDB3_CLEAR = 0x210F019Dull;
+
+static const uint64_t P9N2_C_1_CPPM_CMEDB3_OR = 0x210F019Eull;
+
+static const uint64_t P9N2_C_2_CPPM_CMEDB3 = 0x220F019Cull;
+
+static const uint64_t P9N2_C_2_CPPM_CMEDB3_CLEAR = 0x220F019Dull;
+
+static const uint64_t P9N2_C_2_CPPM_CMEDB3_OR = 0x220F019Eull;
+
+static const uint64_t P9N2_C_3_CPPM_CMEDB3 = 0x230F019Cull;
+
+static const uint64_t P9N2_C_3_CPPM_CMEDB3_CLEAR = 0x230F019Dull;
+
+static const uint64_t P9N2_C_3_CPPM_CMEDB3_OR = 0x230F019Eull;
+
+static const uint64_t P9N2_C_4_CPPM_CMEDB3 = 0x240F019Cull;
+
+static const uint64_t P9N2_C_4_CPPM_CMEDB3_CLEAR = 0x240F019Dull;
+
+static const uint64_t P9N2_C_4_CPPM_CMEDB3_OR = 0x240F019Eull;
+
+static const uint64_t P9N2_C_5_CPPM_CMEDB3 = 0x250F019Cull;
+
+static const uint64_t P9N2_C_5_CPPM_CMEDB3_CLEAR = 0x250F019Dull;
+
+static const uint64_t P9N2_C_5_CPPM_CMEDB3_OR = 0x250F019Eull;
+
+static const uint64_t P9N2_C_6_CPPM_CMEDB3 = 0x260F019Cull;
+
+static const uint64_t P9N2_C_6_CPPM_CMEDB3_CLEAR = 0x260F019Dull;
+
+static const uint64_t P9N2_C_6_CPPM_CMEDB3_OR = 0x260F019Eull;
+
+static const uint64_t P9N2_C_7_CPPM_CMEDB3 = 0x270F019Cull;
+
+static const uint64_t P9N2_C_7_CPPM_CMEDB3_CLEAR = 0x270F019Dull;
+
+static const uint64_t P9N2_C_7_CPPM_CMEDB3_OR = 0x270F019Eull;
+
+static const uint64_t P9N2_C_8_CPPM_CMEDB3 = 0x280F019Cull;
+
+static const uint64_t P9N2_C_8_CPPM_CMEDB3_CLEAR = 0x280F019Dull;
+
+static const uint64_t P9N2_C_8_CPPM_CMEDB3_OR = 0x280F019Eull;
+
+static const uint64_t P9N2_C_9_CPPM_CMEDB3 = 0x290F019Cull;
+
+static const uint64_t P9N2_C_9_CPPM_CMEDB3_CLEAR = 0x290F019Dull;
+
+static const uint64_t P9N2_C_9_CPPM_CMEDB3_OR = 0x290F019Eull;
+
+static const uint64_t P9N2_C_10_CPPM_CMEDB3 = 0x2A0F019Cull;
+
+static const uint64_t P9N2_C_10_CPPM_CMEDB3_CLEAR = 0x2A0F019Dull;
+
+static const uint64_t P9N2_C_10_CPPM_CMEDB3_OR = 0x2A0F019Eull;
+
+static const uint64_t P9N2_C_11_CPPM_CMEDB3 = 0x2B0F019Cull;
+
+static const uint64_t P9N2_C_11_CPPM_CMEDB3_CLEAR = 0x2B0F019Dull;
+
+static const uint64_t P9N2_C_11_CPPM_CMEDB3_OR = 0x2B0F019Eull;
+
+static const uint64_t P9N2_C_12_CPPM_CMEDB3 = 0x2C0F019Cull;
+
+static const uint64_t P9N2_C_12_CPPM_CMEDB3_CLEAR = 0x2C0F019Dull;
+
+static const uint64_t P9N2_C_12_CPPM_CMEDB3_OR = 0x2C0F019Eull;
+
+static const uint64_t P9N2_C_13_CPPM_CMEDB3 = 0x2D0F019Cull;
+
+static const uint64_t P9N2_C_13_CPPM_CMEDB3_CLEAR = 0x2D0F019Dull;
+
+static const uint64_t P9N2_C_13_CPPM_CMEDB3_OR = 0x2D0F019Eull;
+
+static const uint64_t P9N2_C_14_CPPM_CMEDB3 = 0x2E0F019Cull;
+
+static const uint64_t P9N2_C_14_CPPM_CMEDB3_CLEAR = 0x2E0F019Dull;
+
+static const uint64_t P9N2_C_14_CPPM_CMEDB3_OR = 0x2E0F019Eull;
+
+static const uint64_t P9N2_C_15_CPPM_CMEDB3 = 0x2F0F019Cull;
+
+static const uint64_t P9N2_C_15_CPPM_CMEDB3_CLEAR = 0x2F0F019Dull;
+
+static const uint64_t P9N2_C_15_CPPM_CMEDB3_OR = 0x2F0F019Eull;
+
+static const uint64_t P9N2_C_16_CPPM_CMEDB3 = 0x300F019Cull;
+
+static const uint64_t P9N2_C_16_CPPM_CMEDB3_CLEAR = 0x300F019Dull;
+
+static const uint64_t P9N2_C_16_CPPM_CMEDB3_OR = 0x300F019Eull;
+
+static const uint64_t P9N2_C_17_CPPM_CMEDB3 = 0x310F019Cull;
+
+static const uint64_t P9N2_C_17_CPPM_CMEDB3_CLEAR = 0x310F019Dull;
+
+static const uint64_t P9N2_C_17_CPPM_CMEDB3_OR = 0x310F019Eull;
+
+static const uint64_t P9N2_C_18_CPPM_CMEDB3 = 0x320F019Cull;
+
+static const uint64_t P9N2_C_18_CPPM_CMEDB3_CLEAR = 0x320F019Dull;
+
+static const uint64_t P9N2_C_18_CPPM_CMEDB3_OR = 0x320F019Eull;
+
+static const uint64_t P9N2_C_19_CPPM_CMEDB3 = 0x330F019Cull;
+
+static const uint64_t P9N2_C_19_CPPM_CMEDB3_CLEAR = 0x330F019Dull;
+
+static const uint64_t P9N2_C_19_CPPM_CMEDB3_OR = 0x330F019Eull;
+
+static const uint64_t P9N2_C_20_CPPM_CMEDB3 = 0x340F019Cull;
+
+static const uint64_t P9N2_C_20_CPPM_CMEDB3_CLEAR = 0x340F019Dull;
+
+static const uint64_t P9N2_C_20_CPPM_CMEDB3_OR = 0x340F019Eull;
+
+static const uint64_t P9N2_C_21_CPPM_CMEDB3 = 0x350F019Cull;
+
+static const uint64_t P9N2_C_21_CPPM_CMEDB3_CLEAR = 0x350F019Dull;
+
+static const uint64_t P9N2_C_21_CPPM_CMEDB3_OR = 0x350F019Eull;
+
+static const uint64_t P9N2_C_22_CPPM_CMEDB3 = 0x360F019Cull;
+
+static const uint64_t P9N2_C_22_CPPM_CMEDB3_CLEAR = 0x360F019Dull;
+
+static const uint64_t P9N2_C_22_CPPM_CMEDB3_OR = 0x360F019Eull;
+
+static const uint64_t P9N2_C_23_CPPM_CMEDB3 = 0x370F019Cull;
+
+static const uint64_t P9N2_C_23_CPPM_CMEDB3_CLEAR = 0x370F019Dull;
+
+static const uint64_t P9N2_C_23_CPPM_CMEDB3_OR = 0x370F019Eull;
+
+static const uint64_t P9N2_EX_CPPM_CMEDB3 = 0x200F019Cull;
+//DUPS: 210F019C,
+static const uint64_t P9N2_EX_CPPM_CMEDB3_CLEAR = 0x200F019Dull;
+//DUPS: 210F019D,
+static const uint64_t P9N2_EX_CPPM_CMEDB3_OR = 0x200F019Eull;
+//DUPS: 210F019E,
+static const uint64_t P9N2_EX_0_CPPM_CMEDB3 = 0x200F019Cull;
+//DUPS: 210F019C,
+static const uint64_t P9N2_EX_0_CPPM_CMEDB3_CLEAR = 0x200F019Dull;
+//DUPS: 210F019D,
+static const uint64_t P9N2_EX_0_CPPM_CMEDB3_OR = 0x200F019Eull;
+//DUPS: 210F019E,
+static const uint64_t P9N2_EX_1_CPPM_CMEDB3 = 0x220F019Cull;
+//DUPS: 220F019C,
+static const uint64_t P9N2_EX_1_CPPM_CMEDB3_CLEAR = 0x220F019Dull;
+//DUPS: 220F019D,
+static const uint64_t P9N2_EX_1_CPPM_CMEDB3_OR = 0x220F019Eull;
+//DUPS: 220F019E,
+static const uint64_t P9N2_EX_2_CPPM_CMEDB3 = 0x240F019Cull;
+//DUPS: 250F019C,
+static const uint64_t P9N2_EX_2_CPPM_CMEDB3_CLEAR = 0x240F019Dull;
+//DUPS: 250F019D,
+static const uint64_t P9N2_EX_2_CPPM_CMEDB3_OR = 0x240F019Eull;
+//DUPS: 250F019E,
+static const uint64_t P9N2_EX_3_CPPM_CMEDB3 = 0x260F019Cull;
+//DUPS: 270F019C,
+static const uint64_t P9N2_EX_3_CPPM_CMEDB3_CLEAR = 0x260F019Dull;
+//DUPS: 270F019D,
+static const uint64_t P9N2_EX_3_CPPM_CMEDB3_OR = 0x260F019Eull;
+//DUPS: 270F019E,
+static const uint64_t P9N2_EX_4_CPPM_CMEDB3 = 0x280F019Cull;
+//DUPS: 290F019C,
+static const uint64_t P9N2_EX_4_CPPM_CMEDB3_CLEAR = 0x280F019Dull;
+//DUPS: 290F019D,
+static const uint64_t P9N2_EX_4_CPPM_CMEDB3_OR = 0x280F019Eull;
+//DUPS: 290F019E,
+static const uint64_t P9N2_EX_5_CPPM_CMEDB3 = 0x2A0F019Cull;
+//DUPS: 2B0F019C,
+static const uint64_t P9N2_EX_5_CPPM_CMEDB3_CLEAR = 0x2A0F019Dull;
+//DUPS: 2B0F019D,
+static const uint64_t P9N2_EX_5_CPPM_CMEDB3_OR = 0x2A0F019Eull;
+//DUPS: 2B0F019E,
+static const uint64_t P9N2_EX_6_CPPM_CMEDB3 = 0x2C0F019Cull;
+//DUPS: 2D0F019C,
+static const uint64_t P9N2_EX_6_CPPM_CMEDB3_CLEAR = 0x2C0F019Dull;
+//DUPS: 2D0F019D,
+static const uint64_t P9N2_EX_6_CPPM_CMEDB3_OR = 0x2C0F019Eull;
+//DUPS: 2D0F019E,
+static const uint64_t P9N2_EX_7_CPPM_CMEDB3 = 0x2E0F019Cull;
+//DUPS: 2F0F019C,
+static const uint64_t P9N2_EX_7_CPPM_CMEDB3_CLEAR = 0x2E0F019Dull;
+//DUPS: 2F0F019D,
+static const uint64_t P9N2_EX_7_CPPM_CMEDB3_OR = 0x2E0F019Eull;
+//DUPS: 2F0F019E,
+static const uint64_t P9N2_EX_8_CPPM_CMEDB3 = 0x300F019Cull;
+//DUPS: 310F019C,
+static const uint64_t P9N2_EX_8_CPPM_CMEDB3_CLEAR = 0x300F019Dull;
+//DUPS: 310F019D,
+static const uint64_t P9N2_EX_8_CPPM_CMEDB3_OR = 0x300F019Eull;
+//DUPS: 310F019E,
+static const uint64_t P9N2_EX_9_CPPM_CMEDB3 = 0x320F019Cull;
+//DUPS: 330F019C,
+static const uint64_t P9N2_EX_9_CPPM_CMEDB3_CLEAR = 0x320F019Dull;
+//DUPS: 330F019D,
+static const uint64_t P9N2_EX_9_CPPM_CMEDB3_OR = 0x320F019Eull;
+//DUPS: 330F019E,
+static const uint64_t P9N2_EX_10_CPPM_CMEDB3 = 0x340F019Cull;
+//DUPS: 350F019C,
+static const uint64_t P9N2_EX_10_CPPM_CMEDB3_CLEAR = 0x340F019Dull;
+//DUPS: 350F019D,
+static const uint64_t P9N2_EX_10_CPPM_CMEDB3_OR = 0x340F019Eull;
+//DUPS: 350F019E,
+static const uint64_t P9N2_EX_11_CPPM_CMEDB3 = 0x360F019Cull;
+//DUPS: 370F019C,
+static const uint64_t P9N2_EX_11_CPPM_CMEDB3_CLEAR = 0x360F019Dull;
+//DUPS: 370F019D,
+static const uint64_t P9N2_EX_11_CPPM_CMEDB3_OR = 0x360F019Eull;
+//DUPS: 370F019E,
+
+static const uint64_t P9N2_C_CPPM_CMEMSG = 0x200F01ABull;
+
+static const uint64_t P9N2_C_0_CPPM_CMEMSG = 0x200F01ABull;
+
+static const uint64_t P9N2_C_1_CPPM_CMEMSG = 0x210F01ABull;
+
+static const uint64_t P9N2_C_2_CPPM_CMEMSG = 0x220F01ABull;
+
+static const uint64_t P9N2_C_3_CPPM_CMEMSG = 0x230F01ABull;
+
+static const uint64_t P9N2_C_4_CPPM_CMEMSG = 0x240F01ABull;
+
+static const uint64_t P9N2_C_5_CPPM_CMEMSG = 0x250F01ABull;
+
+static const uint64_t P9N2_C_6_CPPM_CMEMSG = 0x260F01ABull;
+
+static const uint64_t P9N2_C_7_CPPM_CMEMSG = 0x270F01ABull;
+
+static const uint64_t P9N2_C_8_CPPM_CMEMSG = 0x280F01ABull;
+
+static const uint64_t P9N2_C_9_CPPM_CMEMSG = 0x290F01ABull;
+
+static const uint64_t P9N2_C_10_CPPM_CMEMSG = 0x2A0F01ABull;
+
+static const uint64_t P9N2_C_11_CPPM_CMEMSG = 0x2B0F01ABull;
+
+static const uint64_t P9N2_C_12_CPPM_CMEMSG = 0x2C0F01ABull;
+
+static const uint64_t P9N2_C_13_CPPM_CMEMSG = 0x2D0F01ABull;
+
+static const uint64_t P9N2_C_14_CPPM_CMEMSG = 0x2E0F01ABull;
+
+static const uint64_t P9N2_C_15_CPPM_CMEMSG = 0x2F0F01ABull;
+
+static const uint64_t P9N2_C_16_CPPM_CMEMSG = 0x300F01ABull;
+
+static const uint64_t P9N2_C_17_CPPM_CMEMSG = 0x310F01ABull;
+
+static const uint64_t P9N2_C_18_CPPM_CMEMSG = 0x320F01ABull;
+
+static const uint64_t P9N2_C_19_CPPM_CMEMSG = 0x330F01ABull;
+
+static const uint64_t P9N2_C_20_CPPM_CMEMSG = 0x340F01ABull;
+
+static const uint64_t P9N2_C_21_CPPM_CMEMSG = 0x350F01ABull;
+
+static const uint64_t P9N2_C_22_CPPM_CMEMSG = 0x360F01ABull;
+
+static const uint64_t P9N2_C_23_CPPM_CMEMSG = 0x370F01ABull;
+
+static const uint64_t P9N2_EX_CPPM_CMEMSG = 0x200F01ABull;
+//DUPS: 210F01AB,
+static const uint64_t P9N2_EX_0_CPPM_CMEMSG = 0x200F01ABull;
+//DUPS: 210F01AB,
+static const uint64_t P9N2_EX_1_CPPM_CMEMSG = 0x220F01ABull;
+//DUPS: 220F01AB,
+static const uint64_t P9N2_EX_2_CPPM_CMEMSG = 0x240F01ABull;
+//DUPS: 250F01AB,
+static const uint64_t P9N2_EX_3_CPPM_CMEMSG = 0x260F01ABull;
+//DUPS: 270F01AB,
+static const uint64_t P9N2_EX_4_CPPM_CMEMSG = 0x280F01ABull;
+//DUPS: 290F01AB,
+static const uint64_t P9N2_EX_5_CPPM_CMEMSG = 0x2A0F01ABull;
+//DUPS: 2B0F01AB,
+static const uint64_t P9N2_EX_6_CPPM_CMEMSG = 0x2C0F01ABull;
+//DUPS: 2D0F01AB,
+static const uint64_t P9N2_EX_7_CPPM_CMEMSG = 0x2E0F01ABull;
+//DUPS: 2F0F01AB,
+static const uint64_t P9N2_EX_8_CPPM_CMEMSG = 0x300F01ABull;
+//DUPS: 310F01AB,
+static const uint64_t P9N2_EX_9_CPPM_CMEMSG = 0x320F01ABull;
+//DUPS: 330F01AB,
+static const uint64_t P9N2_EX_10_CPPM_CMEMSG = 0x340F01ABull;
+//DUPS: 350F01AB,
+static const uint64_t P9N2_EX_11_CPPM_CMEMSG = 0x360F01ABull;
+//DUPS: 370F01AB,
+
+static const uint64_t P9N2_C_CPPM_CPMMR_SCOM = 0x200F0106ull;
+
+static const uint64_t P9N2_C_CPPM_CPMMR_SCOM1 = 0x200F0107ull;
+
+static const uint64_t P9N2_C_CPPM_CPMMR_SCOM2 = 0x200F0108ull;
+
+static const uint64_t P9N2_C_0_CPPM_CPMMR_SCOM = 0x200F0106ull;
+
+static const uint64_t P9N2_C_0_CPPM_CPMMR_SCOM1 = 0x200F0107ull;
+
+static const uint64_t P9N2_C_0_CPPM_CPMMR_SCOM2 = 0x200F0108ull;
+
+static const uint64_t P9N2_C_1_CPPM_CPMMR_SCOM = 0x210F0106ull;
+
+static const uint64_t P9N2_C_1_CPPM_CPMMR_SCOM1 = 0x210F0107ull;
+
+static const uint64_t P9N2_C_1_CPPM_CPMMR_SCOM2 = 0x210F0108ull;
+
+static const uint64_t P9N2_C_2_CPPM_CPMMR_SCOM = 0x220F0106ull;
+
+static const uint64_t P9N2_C_2_CPPM_CPMMR_SCOM1 = 0x220F0107ull;
+
+static const uint64_t P9N2_C_2_CPPM_CPMMR_SCOM2 = 0x220F0108ull;
+
+static const uint64_t P9N2_C_3_CPPM_CPMMR_SCOM = 0x230F0106ull;
+
+static const uint64_t P9N2_C_3_CPPM_CPMMR_SCOM1 = 0x230F0107ull;
+
+static const uint64_t P9N2_C_3_CPPM_CPMMR_SCOM2 = 0x230F0108ull;
+
+static const uint64_t P9N2_C_4_CPPM_CPMMR_SCOM = 0x240F0106ull;
+
+static const uint64_t P9N2_C_4_CPPM_CPMMR_SCOM1 = 0x240F0107ull;
+
+static const uint64_t P9N2_C_4_CPPM_CPMMR_SCOM2 = 0x240F0108ull;
+
+static const uint64_t P9N2_C_5_CPPM_CPMMR_SCOM = 0x250F0106ull;
+
+static const uint64_t P9N2_C_5_CPPM_CPMMR_SCOM1 = 0x250F0107ull;
+
+static const uint64_t P9N2_C_5_CPPM_CPMMR_SCOM2 = 0x250F0108ull;
+
+static const uint64_t P9N2_C_6_CPPM_CPMMR_SCOM = 0x260F0106ull;
+
+static const uint64_t P9N2_C_6_CPPM_CPMMR_SCOM1 = 0x260F0107ull;
+
+static const uint64_t P9N2_C_6_CPPM_CPMMR_SCOM2 = 0x260F0108ull;
+
+static const uint64_t P9N2_C_7_CPPM_CPMMR_SCOM = 0x270F0106ull;
+
+static const uint64_t P9N2_C_7_CPPM_CPMMR_SCOM1 = 0x270F0107ull;
+
+static const uint64_t P9N2_C_7_CPPM_CPMMR_SCOM2 = 0x270F0108ull;
+
+static const uint64_t P9N2_C_8_CPPM_CPMMR_SCOM = 0x280F0106ull;
+
+static const uint64_t P9N2_C_8_CPPM_CPMMR_SCOM1 = 0x280F0107ull;
+
+static const uint64_t P9N2_C_8_CPPM_CPMMR_SCOM2 = 0x280F0108ull;
+
+static const uint64_t P9N2_C_9_CPPM_CPMMR_SCOM = 0x290F0106ull;
+
+static const uint64_t P9N2_C_9_CPPM_CPMMR_SCOM1 = 0x290F0107ull;
+
+static const uint64_t P9N2_C_9_CPPM_CPMMR_SCOM2 = 0x290F0108ull;
+
+static const uint64_t P9N2_C_10_CPPM_CPMMR_SCOM = 0x2A0F0106ull;
+
+static const uint64_t P9N2_C_10_CPPM_CPMMR_SCOM1 = 0x2A0F0107ull;
+
+static const uint64_t P9N2_C_10_CPPM_CPMMR_SCOM2 = 0x2A0F0108ull;
+
+static const uint64_t P9N2_C_11_CPPM_CPMMR_SCOM = 0x2B0F0106ull;
+
+static const uint64_t P9N2_C_11_CPPM_CPMMR_SCOM1 = 0x2B0F0107ull;
+
+static const uint64_t P9N2_C_11_CPPM_CPMMR_SCOM2 = 0x2B0F0108ull;
+
+static const uint64_t P9N2_C_12_CPPM_CPMMR_SCOM = 0x2C0F0106ull;
+
+static const uint64_t P9N2_C_12_CPPM_CPMMR_SCOM1 = 0x2C0F0107ull;
+
+static const uint64_t P9N2_C_12_CPPM_CPMMR_SCOM2 = 0x2C0F0108ull;
+
+static const uint64_t P9N2_C_13_CPPM_CPMMR_SCOM = 0x2D0F0106ull;
+
+static const uint64_t P9N2_C_13_CPPM_CPMMR_SCOM1 = 0x2D0F0107ull;
+
+static const uint64_t P9N2_C_13_CPPM_CPMMR_SCOM2 = 0x2D0F0108ull;
+
+static const uint64_t P9N2_C_14_CPPM_CPMMR_SCOM = 0x2E0F0106ull;
+
+static const uint64_t P9N2_C_14_CPPM_CPMMR_SCOM1 = 0x2E0F0107ull;
+
+static const uint64_t P9N2_C_14_CPPM_CPMMR_SCOM2 = 0x2E0F0108ull;
+
+static const uint64_t P9N2_C_15_CPPM_CPMMR_SCOM = 0x2F0F0106ull;
+
+static const uint64_t P9N2_C_15_CPPM_CPMMR_SCOM1 = 0x2F0F0107ull;
+
+static const uint64_t P9N2_C_15_CPPM_CPMMR_SCOM2 = 0x2F0F0108ull;
+
+static const uint64_t P9N2_C_16_CPPM_CPMMR_SCOM = 0x300F0106ull;
+
+static const uint64_t P9N2_C_16_CPPM_CPMMR_SCOM1 = 0x300F0107ull;
+
+static const uint64_t P9N2_C_16_CPPM_CPMMR_SCOM2 = 0x300F0108ull;
+
+static const uint64_t P9N2_C_17_CPPM_CPMMR_SCOM = 0x310F0106ull;
+
+static const uint64_t P9N2_C_17_CPPM_CPMMR_SCOM1 = 0x310F0107ull;
+
+static const uint64_t P9N2_C_17_CPPM_CPMMR_SCOM2 = 0x310F0108ull;
+
+static const uint64_t P9N2_C_18_CPPM_CPMMR_SCOM = 0x320F0106ull;
+
+static const uint64_t P9N2_C_18_CPPM_CPMMR_SCOM1 = 0x320F0107ull;
+
+static const uint64_t P9N2_C_18_CPPM_CPMMR_SCOM2 = 0x320F0108ull;
+
+static const uint64_t P9N2_C_19_CPPM_CPMMR_SCOM = 0x330F0106ull;
+
+static const uint64_t P9N2_C_19_CPPM_CPMMR_SCOM1 = 0x330F0107ull;
+
+static const uint64_t P9N2_C_19_CPPM_CPMMR_SCOM2 = 0x330F0108ull;
+
+static const uint64_t P9N2_C_20_CPPM_CPMMR_SCOM = 0x340F0106ull;
+
+static const uint64_t P9N2_C_20_CPPM_CPMMR_SCOM1 = 0x340F0107ull;
+
+static const uint64_t P9N2_C_20_CPPM_CPMMR_SCOM2 = 0x340F0108ull;
+
+static const uint64_t P9N2_C_21_CPPM_CPMMR_SCOM = 0x350F0106ull;
+
+static const uint64_t P9N2_C_21_CPPM_CPMMR_SCOM1 = 0x350F0107ull;
+
+static const uint64_t P9N2_C_21_CPPM_CPMMR_SCOM2 = 0x350F0108ull;
+
+static const uint64_t P9N2_C_22_CPPM_CPMMR_SCOM = 0x360F0106ull;
+
+static const uint64_t P9N2_C_22_CPPM_CPMMR_SCOM1 = 0x360F0107ull;
+
+static const uint64_t P9N2_C_22_CPPM_CPMMR_SCOM2 = 0x360F0108ull;
+
+static const uint64_t P9N2_C_23_CPPM_CPMMR_SCOM = 0x370F0106ull;
+
+static const uint64_t P9N2_C_23_CPPM_CPMMR_SCOM1 = 0x370F0107ull;
+
+static const uint64_t P9N2_C_23_CPPM_CPMMR_SCOM2 = 0x370F0108ull;
+
+static const uint64_t P9N2_EX_CPPM_CPMMR_SCOM = 0x200F0106ull;
+//DUPS: 210F0106,
+static const uint64_t P9N2_EX_CPPM_CPMMR_SCOM1 = 0x200F0107ull;
+//DUPS: 210F0107,
+static const uint64_t P9N2_EX_CPPM_CPMMR_SCOM2 = 0x200F0108ull;
+//DUPS: 210F0108,
+static const uint64_t P9N2_EX_0_CPPM_CPMMR_SCOM = 0x200F0106ull;
+//DUPS: 210F0106,
+static const uint64_t P9N2_EX_0_CPPM_CPMMR_SCOM1 = 0x200F0107ull;
+//DUPS: 210F0107,
+static const uint64_t P9N2_EX_0_CPPM_CPMMR_SCOM2 = 0x200F0108ull;
+//DUPS: 210F0108,
+static const uint64_t P9N2_EX_1_CPPM_CPMMR_SCOM = 0x220F0106ull;
+//DUPS: 220F0106,
+static const uint64_t P9N2_EX_1_CPPM_CPMMR_SCOM1 = 0x220F0107ull;
+//DUPS: 220F0107,
+static const uint64_t P9N2_EX_1_CPPM_CPMMR_SCOM2 = 0x220F0108ull;
+//DUPS: 220F0108,
+static const uint64_t P9N2_EX_2_CPPM_CPMMR_SCOM = 0x240F0106ull;
+//DUPS: 250F0106,
+static const uint64_t P9N2_EX_2_CPPM_CPMMR_SCOM1 = 0x240F0107ull;
+//DUPS: 250F0107,
+static const uint64_t P9N2_EX_2_CPPM_CPMMR_SCOM2 = 0x240F0108ull;
+//DUPS: 250F0108,
+static const uint64_t P9N2_EX_3_CPPM_CPMMR_SCOM = 0x260F0106ull;
+//DUPS: 270F0106,
+static const uint64_t P9N2_EX_3_CPPM_CPMMR_SCOM1 = 0x260F0107ull;
+//DUPS: 270F0107,
+static const uint64_t P9N2_EX_3_CPPM_CPMMR_SCOM2 = 0x260F0108ull;
+//DUPS: 270F0108,
+static const uint64_t P9N2_EX_4_CPPM_CPMMR_SCOM = 0x280F0106ull;
+//DUPS: 290F0106,
+static const uint64_t P9N2_EX_4_CPPM_CPMMR_SCOM1 = 0x280F0107ull;
+//DUPS: 290F0107,
+static const uint64_t P9N2_EX_4_CPPM_CPMMR_SCOM2 = 0x280F0108ull;
+//DUPS: 290F0108,
+static const uint64_t P9N2_EX_5_CPPM_CPMMR_SCOM = 0x2A0F0106ull;
+//DUPS: 2B0F0106,
+static const uint64_t P9N2_EX_5_CPPM_CPMMR_SCOM1 = 0x2A0F0107ull;
+//DUPS: 2B0F0107,
+static const uint64_t P9N2_EX_5_CPPM_CPMMR_SCOM2 = 0x2A0F0108ull;
+//DUPS: 2B0F0108,
+static const uint64_t P9N2_EX_6_CPPM_CPMMR_SCOM = 0x2C0F0106ull;
+//DUPS: 2D0F0106,
+static const uint64_t P9N2_EX_6_CPPM_CPMMR_SCOM1 = 0x2C0F0107ull;
+//DUPS: 2D0F0107,
+static const uint64_t P9N2_EX_6_CPPM_CPMMR_SCOM2 = 0x2C0F0108ull;
+//DUPS: 2D0F0108,
+static const uint64_t P9N2_EX_7_CPPM_CPMMR_SCOM = 0x2E0F0106ull;
+//DUPS: 2F0F0106,
+static const uint64_t P9N2_EX_7_CPPM_CPMMR_SCOM1 = 0x2E0F0107ull;
+//DUPS: 2F0F0107,
+static const uint64_t P9N2_EX_7_CPPM_CPMMR_SCOM2 = 0x2E0F0108ull;
+//DUPS: 2F0F0108,
+static const uint64_t P9N2_EX_8_CPPM_CPMMR_SCOM = 0x300F0106ull;
+//DUPS: 310F0106,
+static const uint64_t P9N2_EX_8_CPPM_CPMMR_SCOM1 = 0x300F0107ull;
+//DUPS: 310F0107,
+static const uint64_t P9N2_EX_8_CPPM_CPMMR_SCOM2 = 0x300F0108ull;
+//DUPS: 310F0108,
+static const uint64_t P9N2_EX_9_CPPM_CPMMR_SCOM = 0x320F0106ull;
+//DUPS: 330F0106,
+static const uint64_t P9N2_EX_9_CPPM_CPMMR_SCOM1 = 0x320F0107ull;
+//DUPS: 330F0107,
+static const uint64_t P9N2_EX_9_CPPM_CPMMR_SCOM2 = 0x320F0108ull;
+//DUPS: 330F0108,
+static const uint64_t P9N2_EX_10_CPPM_CPMMR_SCOM = 0x340F0106ull;
+//DUPS: 350F0106,
+static const uint64_t P9N2_EX_10_CPPM_CPMMR_SCOM1 = 0x340F0107ull;
+//DUPS: 350F0107,
+static const uint64_t P9N2_EX_10_CPPM_CPMMR_SCOM2 = 0x340F0108ull;
+//DUPS: 350F0108,
+static const uint64_t P9N2_EX_11_CPPM_CPMMR_SCOM = 0x360F0106ull;
+//DUPS: 370F0106,
+static const uint64_t P9N2_EX_11_CPPM_CPMMR_SCOM1 = 0x360F0107ull;
+//DUPS: 370F0107,
+static const uint64_t P9N2_EX_11_CPPM_CPMMR_SCOM2 = 0x360F0108ull;
+//DUPS: 370F0108,
+
+static const uint64_t P9N2_C_CPPM_CSAR = 0x200F0138ull;
+
+static const uint64_t P9N2_C_CPPM_CSAR_CLEAR = 0x200F0139ull;
+
+static const uint64_t P9N2_C_CPPM_CSAR_OR = 0x200F013Aull;
+
+static const uint64_t P9N2_C_0_CPPM_CSAR = 0x200F0138ull;
+
+static const uint64_t P9N2_C_0_CPPM_CSAR_CLEAR = 0x200F0139ull;
+
+static const uint64_t P9N2_C_0_CPPM_CSAR_OR = 0x200F013Aull;
+
+static const uint64_t P9N2_C_1_CPPM_CSAR = 0x210F0138ull;
+
+static const uint64_t P9N2_C_1_CPPM_CSAR_CLEAR = 0x210F0139ull;
+
+static const uint64_t P9N2_C_1_CPPM_CSAR_OR = 0x210F013Aull;
+
+static const uint64_t P9N2_C_2_CPPM_CSAR = 0x220F0138ull;
+
+static const uint64_t P9N2_C_2_CPPM_CSAR_CLEAR = 0x220F0139ull;
+
+static const uint64_t P9N2_C_2_CPPM_CSAR_OR = 0x220F013Aull;
+
+static const uint64_t P9N2_C_3_CPPM_CSAR = 0x230F0138ull;
+
+static const uint64_t P9N2_C_3_CPPM_CSAR_CLEAR = 0x230F0139ull;
+
+static const uint64_t P9N2_C_3_CPPM_CSAR_OR = 0x230F013Aull;
+
+static const uint64_t P9N2_C_4_CPPM_CSAR = 0x240F0138ull;
+
+static const uint64_t P9N2_C_4_CPPM_CSAR_CLEAR = 0x240F0139ull;
+
+static const uint64_t P9N2_C_4_CPPM_CSAR_OR = 0x240F013Aull;
+
+static const uint64_t P9N2_C_5_CPPM_CSAR = 0x250F0138ull;
+
+static const uint64_t P9N2_C_5_CPPM_CSAR_CLEAR = 0x250F0139ull;
+
+static const uint64_t P9N2_C_5_CPPM_CSAR_OR = 0x250F013Aull;
+
+static const uint64_t P9N2_C_6_CPPM_CSAR = 0x260F0138ull;
+
+static const uint64_t P9N2_C_6_CPPM_CSAR_CLEAR = 0x260F0139ull;
+
+static const uint64_t P9N2_C_6_CPPM_CSAR_OR = 0x260F013Aull;
+
+static const uint64_t P9N2_C_7_CPPM_CSAR = 0x270F0138ull;
+
+static const uint64_t P9N2_C_7_CPPM_CSAR_CLEAR = 0x270F0139ull;
+
+static const uint64_t P9N2_C_7_CPPM_CSAR_OR = 0x270F013Aull;
+
+static const uint64_t P9N2_C_8_CPPM_CSAR = 0x280F0138ull;
+
+static const uint64_t P9N2_C_8_CPPM_CSAR_CLEAR = 0x280F0139ull;
+
+static const uint64_t P9N2_C_8_CPPM_CSAR_OR = 0x280F013Aull;
+
+static const uint64_t P9N2_C_9_CPPM_CSAR = 0x290F0138ull;
+
+static const uint64_t P9N2_C_9_CPPM_CSAR_CLEAR = 0x290F0139ull;
+
+static const uint64_t P9N2_C_9_CPPM_CSAR_OR = 0x290F013Aull;
+
+static const uint64_t P9N2_C_10_CPPM_CSAR = 0x2A0F0138ull;
+
+static const uint64_t P9N2_C_10_CPPM_CSAR_CLEAR = 0x2A0F0139ull;
+
+static const uint64_t P9N2_C_10_CPPM_CSAR_OR = 0x2A0F013Aull;
+
+static const uint64_t P9N2_C_11_CPPM_CSAR = 0x2B0F0138ull;
+
+static const uint64_t P9N2_C_11_CPPM_CSAR_CLEAR = 0x2B0F0139ull;
+
+static const uint64_t P9N2_C_11_CPPM_CSAR_OR = 0x2B0F013Aull;
+
+static const uint64_t P9N2_C_12_CPPM_CSAR = 0x2C0F0138ull;
+
+static const uint64_t P9N2_C_12_CPPM_CSAR_CLEAR = 0x2C0F0139ull;
+
+static const uint64_t P9N2_C_12_CPPM_CSAR_OR = 0x2C0F013Aull;
+
+static const uint64_t P9N2_C_13_CPPM_CSAR = 0x2D0F0138ull;
+
+static const uint64_t P9N2_C_13_CPPM_CSAR_CLEAR = 0x2D0F0139ull;
+
+static const uint64_t P9N2_C_13_CPPM_CSAR_OR = 0x2D0F013Aull;
+
+static const uint64_t P9N2_C_14_CPPM_CSAR = 0x2E0F0138ull;
+
+static const uint64_t P9N2_C_14_CPPM_CSAR_CLEAR = 0x2E0F0139ull;
+
+static const uint64_t P9N2_C_14_CPPM_CSAR_OR = 0x2E0F013Aull;
+
+static const uint64_t P9N2_C_15_CPPM_CSAR = 0x2F0F0138ull;
+
+static const uint64_t P9N2_C_15_CPPM_CSAR_CLEAR = 0x2F0F0139ull;
+
+static const uint64_t P9N2_C_15_CPPM_CSAR_OR = 0x2F0F013Aull;
+
+static const uint64_t P9N2_C_16_CPPM_CSAR = 0x300F0138ull;
+
+static const uint64_t P9N2_C_16_CPPM_CSAR_CLEAR = 0x300F0139ull;
+
+static const uint64_t P9N2_C_16_CPPM_CSAR_OR = 0x300F013Aull;
+
+static const uint64_t P9N2_C_17_CPPM_CSAR = 0x310F0138ull;
+
+static const uint64_t P9N2_C_17_CPPM_CSAR_CLEAR = 0x310F0139ull;
+
+static const uint64_t P9N2_C_17_CPPM_CSAR_OR = 0x310F013Aull;
+
+static const uint64_t P9N2_C_18_CPPM_CSAR = 0x320F0138ull;
+
+static const uint64_t P9N2_C_18_CPPM_CSAR_CLEAR = 0x320F0139ull;
+
+static const uint64_t P9N2_C_18_CPPM_CSAR_OR = 0x320F013Aull;
+
+static const uint64_t P9N2_C_19_CPPM_CSAR = 0x330F0138ull;
+
+static const uint64_t P9N2_C_19_CPPM_CSAR_CLEAR = 0x330F0139ull;
+
+static const uint64_t P9N2_C_19_CPPM_CSAR_OR = 0x330F013Aull;
+
+static const uint64_t P9N2_C_20_CPPM_CSAR = 0x340F0138ull;
+
+static const uint64_t P9N2_C_20_CPPM_CSAR_CLEAR = 0x340F0139ull;
+
+static const uint64_t P9N2_C_20_CPPM_CSAR_OR = 0x340F013Aull;
+
+static const uint64_t P9N2_C_21_CPPM_CSAR = 0x350F0138ull;
+
+static const uint64_t P9N2_C_21_CPPM_CSAR_CLEAR = 0x350F0139ull;
+
+static const uint64_t P9N2_C_21_CPPM_CSAR_OR = 0x350F013Aull;
+
+static const uint64_t P9N2_C_22_CPPM_CSAR = 0x360F0138ull;
+
+static const uint64_t P9N2_C_22_CPPM_CSAR_CLEAR = 0x360F0139ull;
+
+static const uint64_t P9N2_C_22_CPPM_CSAR_OR = 0x360F013Aull;
+
+static const uint64_t P9N2_C_23_CPPM_CSAR = 0x370F0138ull;
+
+static const uint64_t P9N2_C_23_CPPM_CSAR_CLEAR = 0x370F0139ull;
+
+static const uint64_t P9N2_C_23_CPPM_CSAR_OR = 0x370F013Aull;
+
+static const uint64_t P9N2_EX_CPPM_CSAR = 0x200F0138ull;
+//DUPS: 210F0138,
+static const uint64_t P9N2_EX_CPPM_CSAR_CLEAR = 0x200F0139ull;
+//DUPS: 210F0139,
+static const uint64_t P9N2_EX_CPPM_CSAR_OR = 0x200F013Aull;
+//DUPS: 210F013A,
+static const uint64_t P9N2_EX_0_CPPM_CSAR = 0x200F0138ull;
+//DUPS: 210F0138,
+static const uint64_t P9N2_EX_0_CPPM_CSAR_CLEAR = 0x200F0139ull;
+//DUPS: 210F0139,
+static const uint64_t P9N2_EX_0_CPPM_CSAR_OR = 0x200F013Aull;
+//DUPS: 210F013A,
+static const uint64_t P9N2_EX_1_CPPM_CSAR = 0x220F0138ull;
+//DUPS: 220F0138,
+static const uint64_t P9N2_EX_1_CPPM_CSAR_CLEAR = 0x220F0139ull;
+//DUPS: 220F0139,
+static const uint64_t P9N2_EX_1_CPPM_CSAR_OR = 0x220F013Aull;
+//DUPS: 220F013A,
+static const uint64_t P9N2_EX_2_CPPM_CSAR = 0x240F0138ull;
+//DUPS: 250F0138,
+static const uint64_t P9N2_EX_2_CPPM_CSAR_CLEAR = 0x240F0139ull;
+//DUPS: 250F0139,
+static const uint64_t P9N2_EX_2_CPPM_CSAR_OR = 0x240F013Aull;
+//DUPS: 250F013A,
+static const uint64_t P9N2_EX_3_CPPM_CSAR = 0x260F0138ull;
+//DUPS: 270F0138,
+static const uint64_t P9N2_EX_3_CPPM_CSAR_CLEAR = 0x260F0139ull;
+//DUPS: 270F0139,
+static const uint64_t P9N2_EX_3_CPPM_CSAR_OR = 0x260F013Aull;
+//DUPS: 270F013A,
+static const uint64_t P9N2_EX_4_CPPM_CSAR = 0x280F0138ull;
+//DUPS: 290F0138,
+static const uint64_t P9N2_EX_4_CPPM_CSAR_CLEAR = 0x280F0139ull;
+//DUPS: 290F0139,
+static const uint64_t P9N2_EX_4_CPPM_CSAR_OR = 0x280F013Aull;
+//DUPS: 290F013A,
+static const uint64_t P9N2_EX_5_CPPM_CSAR = 0x2A0F0138ull;
+//DUPS: 2B0F0138,
+static const uint64_t P9N2_EX_5_CPPM_CSAR_CLEAR = 0x2A0F0139ull;
+//DUPS: 2B0F0139,
+static const uint64_t P9N2_EX_5_CPPM_CSAR_OR = 0x2A0F013Aull;
+//DUPS: 2B0F013A,
+static const uint64_t P9N2_EX_6_CPPM_CSAR = 0x2C0F0138ull;
+//DUPS: 2D0F0138,
+static const uint64_t P9N2_EX_6_CPPM_CSAR_CLEAR = 0x2C0F0139ull;
+//DUPS: 2D0F0139,
+static const uint64_t P9N2_EX_6_CPPM_CSAR_OR = 0x2C0F013Aull;
+//DUPS: 2D0F013A,
+static const uint64_t P9N2_EX_7_CPPM_CSAR = 0x2E0F0138ull;
+//DUPS: 2F0F0138,
+static const uint64_t P9N2_EX_7_CPPM_CSAR_CLEAR = 0x2E0F0139ull;
+//DUPS: 2F0F0139,
+static const uint64_t P9N2_EX_7_CPPM_CSAR_OR = 0x2E0F013Aull;
+//DUPS: 2F0F013A,
+static const uint64_t P9N2_EX_8_CPPM_CSAR = 0x300F0138ull;
+//DUPS: 310F0138,
+static const uint64_t P9N2_EX_8_CPPM_CSAR_CLEAR = 0x300F0139ull;
+//DUPS: 310F0139,
+static const uint64_t P9N2_EX_8_CPPM_CSAR_OR = 0x300F013Aull;
+//DUPS: 310F013A,
+static const uint64_t P9N2_EX_9_CPPM_CSAR = 0x320F0138ull;
+//DUPS: 330F0138,
+static const uint64_t P9N2_EX_9_CPPM_CSAR_CLEAR = 0x320F0139ull;
+//DUPS: 330F0139,
+static const uint64_t P9N2_EX_9_CPPM_CSAR_OR = 0x320F013Aull;
+//DUPS: 330F013A,
+static const uint64_t P9N2_EX_10_CPPM_CSAR = 0x340F0138ull;
+//DUPS: 350F0138,
+static const uint64_t P9N2_EX_10_CPPM_CSAR_CLEAR = 0x340F0139ull;
+//DUPS: 350F0139,
+static const uint64_t P9N2_EX_10_CPPM_CSAR_OR = 0x340F013Aull;
+//DUPS: 350F013A,
+static const uint64_t P9N2_EX_11_CPPM_CSAR = 0x360F0138ull;
+//DUPS: 370F0138,
+static const uint64_t P9N2_EX_11_CPPM_CSAR_CLEAR = 0x360F0139ull;
+//DUPS: 370F0139,
+static const uint64_t P9N2_EX_11_CPPM_CSAR_OR = 0x360F013Aull;
+//DUPS: 370F013A,
+
+static const uint64_t P9N2_C_CPPM_ERR = 0x200F0121ull;
+
+static const uint64_t P9N2_C_0_CPPM_ERR = 0x200F0121ull;
+
+static const uint64_t P9N2_C_1_CPPM_ERR = 0x210F0121ull;
+
+static const uint64_t P9N2_C_2_CPPM_ERR = 0x220F0121ull;
+
+static const uint64_t P9N2_C_3_CPPM_ERR = 0x230F0121ull;
+
+static const uint64_t P9N2_C_4_CPPM_ERR = 0x240F0121ull;
+
+static const uint64_t P9N2_C_5_CPPM_ERR = 0x250F0121ull;
+
+static const uint64_t P9N2_C_6_CPPM_ERR = 0x260F0121ull;
+
+static const uint64_t P9N2_C_7_CPPM_ERR = 0x270F0121ull;
+
+static const uint64_t P9N2_C_8_CPPM_ERR = 0x280F0121ull;
+
+static const uint64_t P9N2_C_9_CPPM_ERR = 0x290F0121ull;
+
+static const uint64_t P9N2_C_10_CPPM_ERR = 0x2A0F0121ull;
+
+static const uint64_t P9N2_C_11_CPPM_ERR = 0x2B0F0121ull;
+
+static const uint64_t P9N2_C_12_CPPM_ERR = 0x2C0F0121ull;
+
+static const uint64_t P9N2_C_13_CPPM_ERR = 0x2D0F0121ull;
+
+static const uint64_t P9N2_C_14_CPPM_ERR = 0x2E0F0121ull;
+
+static const uint64_t P9N2_C_15_CPPM_ERR = 0x2F0F0121ull;
+
+static const uint64_t P9N2_C_16_CPPM_ERR = 0x300F0121ull;
+
+static const uint64_t P9N2_C_17_CPPM_ERR = 0x310F0121ull;
+
+static const uint64_t P9N2_C_18_CPPM_ERR = 0x320F0121ull;
+
+static const uint64_t P9N2_C_19_CPPM_ERR = 0x330F0121ull;
+
+static const uint64_t P9N2_C_20_CPPM_ERR = 0x340F0121ull;
+
+static const uint64_t P9N2_C_21_CPPM_ERR = 0x350F0121ull;
+
+static const uint64_t P9N2_C_22_CPPM_ERR = 0x360F0121ull;
+
+static const uint64_t P9N2_C_23_CPPM_ERR = 0x370F0121ull;
+
+static const uint64_t P9N2_EX_CPPM_ERR = 0x200F0121ull;
+//DUPS: 210F0121,
+static const uint64_t P9N2_EX_0_CPPM_ERR = 0x200F0121ull;
+//DUPS: 210F0121,
+static const uint64_t P9N2_EX_1_CPPM_ERR = 0x220F0121ull;
+//DUPS: 220F0121,
+static const uint64_t P9N2_EX_2_CPPM_ERR = 0x240F0121ull;
+//DUPS: 250F0121,
+static const uint64_t P9N2_EX_3_CPPM_ERR = 0x260F0121ull;
+//DUPS: 270F0121,
+static const uint64_t P9N2_EX_4_CPPM_ERR = 0x280F0121ull;
+//DUPS: 290F0121,
+static const uint64_t P9N2_EX_5_CPPM_ERR = 0x2A0F0121ull;
+//DUPS: 2B0F0121,
+static const uint64_t P9N2_EX_6_CPPM_ERR = 0x2C0F0121ull;
+//DUPS: 2D0F0121,
+static const uint64_t P9N2_EX_7_CPPM_ERR = 0x2E0F0121ull;
+//DUPS: 2F0F0121,
+static const uint64_t P9N2_EX_8_CPPM_ERR = 0x300F0121ull;
+//DUPS: 310F0121,
+static const uint64_t P9N2_EX_9_CPPM_ERR = 0x320F0121ull;
+//DUPS: 330F0121,
+static const uint64_t P9N2_EX_10_CPPM_ERR = 0x340F0121ull;
+//DUPS: 350F0121,
+static const uint64_t P9N2_EX_11_CPPM_ERR = 0x360F0121ull;
+//DUPS: 370F0121,
+
+static const uint64_t P9N2_C_CPPM_ERRMSK = 0x200F0122ull;
+
+static const uint64_t P9N2_C_0_CPPM_ERRMSK = 0x200F0122ull;
+
+static const uint64_t P9N2_C_1_CPPM_ERRMSK = 0x210F0122ull;
+
+static const uint64_t P9N2_C_2_CPPM_ERRMSK = 0x220F0122ull;
+
+static const uint64_t P9N2_C_3_CPPM_ERRMSK = 0x230F0122ull;
+
+static const uint64_t P9N2_C_4_CPPM_ERRMSK = 0x240F0122ull;
+
+static const uint64_t P9N2_C_5_CPPM_ERRMSK = 0x250F0122ull;
+
+static const uint64_t P9N2_C_6_CPPM_ERRMSK = 0x260F0122ull;
+
+static const uint64_t P9N2_C_7_CPPM_ERRMSK = 0x270F0122ull;
+
+static const uint64_t P9N2_C_8_CPPM_ERRMSK = 0x280F0122ull;
+
+static const uint64_t P9N2_C_9_CPPM_ERRMSK = 0x290F0122ull;
+
+static const uint64_t P9N2_C_10_CPPM_ERRMSK = 0x2A0F0122ull;
+
+static const uint64_t P9N2_C_11_CPPM_ERRMSK = 0x2B0F0122ull;
+
+static const uint64_t P9N2_C_12_CPPM_ERRMSK = 0x2C0F0122ull;
+
+static const uint64_t P9N2_C_13_CPPM_ERRMSK = 0x2D0F0122ull;
+
+static const uint64_t P9N2_C_14_CPPM_ERRMSK = 0x2E0F0122ull;
+
+static const uint64_t P9N2_C_15_CPPM_ERRMSK = 0x2F0F0122ull;
+
+static const uint64_t P9N2_C_16_CPPM_ERRMSK = 0x300F0122ull;
+
+static const uint64_t P9N2_C_17_CPPM_ERRMSK = 0x310F0122ull;
+
+static const uint64_t P9N2_C_18_CPPM_ERRMSK = 0x320F0122ull;
+
+static const uint64_t P9N2_C_19_CPPM_ERRMSK = 0x330F0122ull;
+
+static const uint64_t P9N2_C_20_CPPM_ERRMSK = 0x340F0122ull;
+
+static const uint64_t P9N2_C_21_CPPM_ERRMSK = 0x350F0122ull;
+
+static const uint64_t P9N2_C_22_CPPM_ERRMSK = 0x360F0122ull;
+
+static const uint64_t P9N2_C_23_CPPM_ERRMSK = 0x370F0122ull;
+
+static const uint64_t P9N2_EX_CPPM_ERRMSK = 0x200F0122ull;
+//DUPS: 210F0122,
+static const uint64_t P9N2_EX_0_CPPM_ERRMSK = 0x200F0122ull;
+//DUPS: 210F0122,
+static const uint64_t P9N2_EX_1_CPPM_ERRMSK = 0x220F0122ull;
+//DUPS: 220F0122,
+static const uint64_t P9N2_EX_2_CPPM_ERRMSK = 0x240F0122ull;
+//DUPS: 250F0122,
+static const uint64_t P9N2_EX_3_CPPM_ERRMSK = 0x260F0122ull;
+//DUPS: 270F0122,
+static const uint64_t P9N2_EX_4_CPPM_ERRMSK = 0x280F0122ull;
+//DUPS: 290F0122,
+static const uint64_t P9N2_EX_5_CPPM_ERRMSK = 0x2A0F0122ull;
+//DUPS: 2B0F0122,
+static const uint64_t P9N2_EX_6_CPPM_ERRMSK = 0x2C0F0122ull;
+//DUPS: 2D0F0122,
+static const uint64_t P9N2_EX_7_CPPM_ERRMSK = 0x2E0F0122ull;
+//DUPS: 2F0F0122,
+static const uint64_t P9N2_EX_8_CPPM_ERRMSK = 0x300F0122ull;
+//DUPS: 310F0122,
+static const uint64_t P9N2_EX_9_CPPM_ERRMSK = 0x320F0122ull;
+//DUPS: 330F0122,
+static const uint64_t P9N2_EX_10_CPPM_ERRMSK = 0x340F0122ull;
+//DUPS: 350F0122,
+static const uint64_t P9N2_EX_11_CPPM_ERRMSK = 0x360F0122ull;
+//DUPS: 370F0122,
+
+static const uint64_t P9N2_C_CPPM_IPPMCMD = 0x200F01C0ull;
+
+static const uint64_t P9N2_C_0_CPPM_IPPMCMD = 0x200F01C0ull;
+
+static const uint64_t P9N2_C_1_CPPM_IPPMCMD = 0x210F01C0ull;
+
+static const uint64_t P9N2_C_2_CPPM_IPPMCMD = 0x220F01C0ull;
+
+static const uint64_t P9N2_C_3_CPPM_IPPMCMD = 0x230F01C0ull;
+
+static const uint64_t P9N2_C_4_CPPM_IPPMCMD = 0x240F01C0ull;
+
+static const uint64_t P9N2_C_5_CPPM_IPPMCMD = 0x250F01C0ull;
+
+static const uint64_t P9N2_C_6_CPPM_IPPMCMD = 0x260F01C0ull;
+
+static const uint64_t P9N2_C_7_CPPM_IPPMCMD = 0x270F01C0ull;
+
+static const uint64_t P9N2_C_8_CPPM_IPPMCMD = 0x280F01C0ull;
+
+static const uint64_t P9N2_C_9_CPPM_IPPMCMD = 0x290F01C0ull;
+
+static const uint64_t P9N2_C_10_CPPM_IPPMCMD = 0x2A0F01C0ull;
+
+static const uint64_t P9N2_C_11_CPPM_IPPMCMD = 0x2B0F01C0ull;
+
+static const uint64_t P9N2_C_12_CPPM_IPPMCMD = 0x2C0F01C0ull;
+
+static const uint64_t P9N2_C_13_CPPM_IPPMCMD = 0x2D0F01C0ull;
+
+static const uint64_t P9N2_C_14_CPPM_IPPMCMD = 0x2E0F01C0ull;
+
+static const uint64_t P9N2_C_15_CPPM_IPPMCMD = 0x2F0F01C0ull;
+
+static const uint64_t P9N2_C_16_CPPM_IPPMCMD = 0x300F01C0ull;
+
+static const uint64_t P9N2_C_17_CPPM_IPPMCMD = 0x310F01C0ull;
+
+static const uint64_t P9N2_C_18_CPPM_IPPMCMD = 0x320F01C0ull;
+
+static const uint64_t P9N2_C_19_CPPM_IPPMCMD = 0x330F01C0ull;
+
+static const uint64_t P9N2_C_20_CPPM_IPPMCMD = 0x340F01C0ull;
+
+static const uint64_t P9N2_C_21_CPPM_IPPMCMD = 0x350F01C0ull;
+
+static const uint64_t P9N2_C_22_CPPM_IPPMCMD = 0x360F01C0ull;
+
+static const uint64_t P9N2_C_23_CPPM_IPPMCMD = 0x370F01C0ull;
+
+static const uint64_t P9N2_EX_CPPM_IPPMCMD = 0x200F01C0ull;
+//DUPS: 210F01C0,
+static const uint64_t P9N2_EX_0_CPPM_IPPMCMD = 0x200F01C0ull;
+//DUPS: 210F01C0,
+static const uint64_t P9N2_EX_1_CPPM_IPPMCMD = 0x220F01C0ull;
+//DUPS: 220F01C0,
+static const uint64_t P9N2_EX_2_CPPM_IPPMCMD = 0x240F01C0ull;
+//DUPS: 250F01C0,
+static const uint64_t P9N2_EX_3_CPPM_IPPMCMD = 0x260F01C0ull;
+//DUPS: 270F01C0,
+static const uint64_t P9N2_EX_4_CPPM_IPPMCMD = 0x280F01C0ull;
+//DUPS: 290F01C0,
+static const uint64_t P9N2_EX_5_CPPM_IPPMCMD = 0x2A0F01C0ull;
+//DUPS: 2B0F01C0,
+static const uint64_t P9N2_EX_6_CPPM_IPPMCMD = 0x2C0F01C0ull;
+//DUPS: 2D0F01C0,
+static const uint64_t P9N2_EX_7_CPPM_IPPMCMD = 0x2E0F01C0ull;
+//DUPS: 2F0F01C0,
+static const uint64_t P9N2_EX_8_CPPM_IPPMCMD = 0x300F01C0ull;
+//DUPS: 310F01C0,
+static const uint64_t P9N2_EX_9_CPPM_IPPMCMD = 0x320F01C0ull;
+//DUPS: 330F01C0,
+static const uint64_t P9N2_EX_10_CPPM_IPPMCMD = 0x340F01C0ull;
+//DUPS: 350F01C0,
+static const uint64_t P9N2_EX_11_CPPM_IPPMCMD = 0x360F01C0ull;
+//DUPS: 370F01C0,
+
+static const uint64_t P9N2_C_CPPM_IPPMRDATA = 0x200F01C3ull;
+
+static const uint64_t P9N2_C_0_CPPM_IPPMRDATA = 0x200F01C3ull;
+
+static const uint64_t P9N2_C_1_CPPM_IPPMRDATA = 0x210F01C3ull;
+
+static const uint64_t P9N2_C_2_CPPM_IPPMRDATA = 0x220F01C3ull;
+
+static const uint64_t P9N2_C_3_CPPM_IPPMRDATA = 0x230F01C3ull;
+
+static const uint64_t P9N2_C_4_CPPM_IPPMRDATA = 0x240F01C3ull;
+
+static const uint64_t P9N2_C_5_CPPM_IPPMRDATA = 0x250F01C3ull;
+
+static const uint64_t P9N2_C_6_CPPM_IPPMRDATA = 0x260F01C3ull;
+
+static const uint64_t P9N2_C_7_CPPM_IPPMRDATA = 0x270F01C3ull;
+
+static const uint64_t P9N2_C_8_CPPM_IPPMRDATA = 0x280F01C3ull;
+
+static const uint64_t P9N2_C_9_CPPM_IPPMRDATA = 0x290F01C3ull;
+
+static const uint64_t P9N2_C_10_CPPM_IPPMRDATA = 0x2A0F01C3ull;
+
+static const uint64_t P9N2_C_11_CPPM_IPPMRDATA = 0x2B0F01C3ull;
+
+static const uint64_t P9N2_C_12_CPPM_IPPMRDATA = 0x2C0F01C3ull;
+
+static const uint64_t P9N2_C_13_CPPM_IPPMRDATA = 0x2D0F01C3ull;
+
+static const uint64_t P9N2_C_14_CPPM_IPPMRDATA = 0x2E0F01C3ull;
+
+static const uint64_t P9N2_C_15_CPPM_IPPMRDATA = 0x2F0F01C3ull;
+
+static const uint64_t P9N2_C_16_CPPM_IPPMRDATA = 0x300F01C3ull;
+
+static const uint64_t P9N2_C_17_CPPM_IPPMRDATA = 0x310F01C3ull;
+
+static const uint64_t P9N2_C_18_CPPM_IPPMRDATA = 0x320F01C3ull;
+
+static const uint64_t P9N2_C_19_CPPM_IPPMRDATA = 0x330F01C3ull;
+
+static const uint64_t P9N2_C_20_CPPM_IPPMRDATA = 0x340F01C3ull;
+
+static const uint64_t P9N2_C_21_CPPM_IPPMRDATA = 0x350F01C3ull;
+
+static const uint64_t P9N2_C_22_CPPM_IPPMRDATA = 0x360F01C3ull;
+
+static const uint64_t P9N2_C_23_CPPM_IPPMRDATA = 0x370F01C3ull;
+
+static const uint64_t P9N2_EX_CPPM_IPPMRDATA = 0x200F01C3ull;
+//DUPS: 210F01C3,
+static const uint64_t P9N2_EX_0_CPPM_IPPMRDATA = 0x200F01C3ull;
+//DUPS: 210F01C3,
+static const uint64_t P9N2_EX_1_CPPM_IPPMRDATA = 0x220F01C3ull;
+//DUPS: 220F01C3,
+static const uint64_t P9N2_EX_2_CPPM_IPPMRDATA = 0x240F01C3ull;
+//DUPS: 250F01C3,
+static const uint64_t P9N2_EX_3_CPPM_IPPMRDATA = 0x260F01C3ull;
+//DUPS: 270F01C3,
+static const uint64_t P9N2_EX_4_CPPM_IPPMRDATA = 0x280F01C3ull;
+//DUPS: 290F01C3,
+static const uint64_t P9N2_EX_5_CPPM_IPPMRDATA = 0x2A0F01C3ull;
+//DUPS: 2B0F01C3,
+static const uint64_t P9N2_EX_6_CPPM_IPPMRDATA = 0x2C0F01C3ull;
+//DUPS: 2D0F01C3,
+static const uint64_t P9N2_EX_7_CPPM_IPPMRDATA = 0x2E0F01C3ull;
+//DUPS: 2F0F01C3,
+static const uint64_t P9N2_EX_8_CPPM_IPPMRDATA = 0x300F01C3ull;
+//DUPS: 310F01C3,
+static const uint64_t P9N2_EX_9_CPPM_IPPMRDATA = 0x320F01C3ull;
+//DUPS: 330F01C3,
+static const uint64_t P9N2_EX_10_CPPM_IPPMRDATA = 0x340F01C3ull;
+//DUPS: 350F01C3,
+static const uint64_t P9N2_EX_11_CPPM_IPPMRDATA = 0x360F01C3ull;
+//DUPS: 370F01C3,
+
+static const uint64_t P9N2_C_CPPM_IPPMSTAT = 0x200F01C1ull;
+
+static const uint64_t P9N2_C_0_CPPM_IPPMSTAT = 0x200F01C1ull;
+
+static const uint64_t P9N2_C_1_CPPM_IPPMSTAT = 0x210F01C1ull;
+
+static const uint64_t P9N2_C_2_CPPM_IPPMSTAT = 0x220F01C1ull;
+
+static const uint64_t P9N2_C_3_CPPM_IPPMSTAT = 0x230F01C1ull;
+
+static const uint64_t P9N2_C_4_CPPM_IPPMSTAT = 0x240F01C1ull;
+
+static const uint64_t P9N2_C_5_CPPM_IPPMSTAT = 0x250F01C1ull;
+
+static const uint64_t P9N2_C_6_CPPM_IPPMSTAT = 0x260F01C1ull;
+
+static const uint64_t P9N2_C_7_CPPM_IPPMSTAT = 0x270F01C1ull;
+
+static const uint64_t P9N2_C_8_CPPM_IPPMSTAT = 0x280F01C1ull;
+
+static const uint64_t P9N2_C_9_CPPM_IPPMSTAT = 0x290F01C1ull;
+
+static const uint64_t P9N2_C_10_CPPM_IPPMSTAT = 0x2A0F01C1ull;
+
+static const uint64_t P9N2_C_11_CPPM_IPPMSTAT = 0x2B0F01C1ull;
+
+static const uint64_t P9N2_C_12_CPPM_IPPMSTAT = 0x2C0F01C1ull;
+
+static const uint64_t P9N2_C_13_CPPM_IPPMSTAT = 0x2D0F01C1ull;
+
+static const uint64_t P9N2_C_14_CPPM_IPPMSTAT = 0x2E0F01C1ull;
+
+static const uint64_t P9N2_C_15_CPPM_IPPMSTAT = 0x2F0F01C1ull;
+
+static const uint64_t P9N2_C_16_CPPM_IPPMSTAT = 0x300F01C1ull;
+
+static const uint64_t P9N2_C_17_CPPM_IPPMSTAT = 0x310F01C1ull;
+
+static const uint64_t P9N2_C_18_CPPM_IPPMSTAT = 0x320F01C1ull;
+
+static const uint64_t P9N2_C_19_CPPM_IPPMSTAT = 0x330F01C1ull;
+
+static const uint64_t P9N2_C_20_CPPM_IPPMSTAT = 0x340F01C1ull;
+
+static const uint64_t P9N2_C_21_CPPM_IPPMSTAT = 0x350F01C1ull;
+
+static const uint64_t P9N2_C_22_CPPM_IPPMSTAT = 0x360F01C1ull;
+
+static const uint64_t P9N2_C_23_CPPM_IPPMSTAT = 0x370F01C1ull;
+
+static const uint64_t P9N2_EX_CPPM_IPPMSTAT = 0x200F01C1ull;
+//DUPS: 210F01C1,
+static const uint64_t P9N2_EX_0_CPPM_IPPMSTAT = 0x200F01C1ull;
+//DUPS: 210F01C1,
+static const uint64_t P9N2_EX_1_CPPM_IPPMSTAT = 0x220F01C1ull;
+//DUPS: 220F01C1,
+static const uint64_t P9N2_EX_2_CPPM_IPPMSTAT = 0x240F01C1ull;
+//DUPS: 250F01C1,
+static const uint64_t P9N2_EX_3_CPPM_IPPMSTAT = 0x260F01C1ull;
+//DUPS: 270F01C1,
+static const uint64_t P9N2_EX_4_CPPM_IPPMSTAT = 0x280F01C1ull;
+//DUPS: 290F01C1,
+static const uint64_t P9N2_EX_5_CPPM_IPPMSTAT = 0x2A0F01C1ull;
+//DUPS: 2B0F01C1,
+static const uint64_t P9N2_EX_6_CPPM_IPPMSTAT = 0x2C0F01C1ull;
+//DUPS: 2D0F01C1,
+static const uint64_t P9N2_EX_7_CPPM_IPPMSTAT = 0x2E0F01C1ull;
+//DUPS: 2F0F01C1,
+static const uint64_t P9N2_EX_8_CPPM_IPPMSTAT = 0x300F01C1ull;
+//DUPS: 310F01C1,
+static const uint64_t P9N2_EX_9_CPPM_IPPMSTAT = 0x320F01C1ull;
+//DUPS: 330F01C1,
+static const uint64_t P9N2_EX_10_CPPM_IPPMSTAT = 0x340F01C1ull;
+//DUPS: 350F01C1,
+static const uint64_t P9N2_EX_11_CPPM_IPPMSTAT = 0x360F01C1ull;
+//DUPS: 370F01C1,
+
+static const uint64_t P9N2_C_CPPM_IPPMWDATA = 0x200F01C2ull;
+
+static const uint64_t P9N2_C_0_CPPM_IPPMWDATA = 0x200F01C2ull;
+
+static const uint64_t P9N2_C_1_CPPM_IPPMWDATA = 0x210F01C2ull;
+
+static const uint64_t P9N2_C_2_CPPM_IPPMWDATA = 0x220F01C2ull;
+
+static const uint64_t P9N2_C_3_CPPM_IPPMWDATA = 0x230F01C2ull;
+
+static const uint64_t P9N2_C_4_CPPM_IPPMWDATA = 0x240F01C2ull;
+
+static const uint64_t P9N2_C_5_CPPM_IPPMWDATA = 0x250F01C2ull;
+
+static const uint64_t P9N2_C_6_CPPM_IPPMWDATA = 0x260F01C2ull;
+
+static const uint64_t P9N2_C_7_CPPM_IPPMWDATA = 0x270F01C2ull;
+
+static const uint64_t P9N2_C_8_CPPM_IPPMWDATA = 0x280F01C2ull;
+
+static const uint64_t P9N2_C_9_CPPM_IPPMWDATA = 0x290F01C2ull;
+
+static const uint64_t P9N2_C_10_CPPM_IPPMWDATA = 0x2A0F01C2ull;
+
+static const uint64_t P9N2_C_11_CPPM_IPPMWDATA = 0x2B0F01C2ull;
+
+static const uint64_t P9N2_C_12_CPPM_IPPMWDATA = 0x2C0F01C2ull;
+
+static const uint64_t P9N2_C_13_CPPM_IPPMWDATA = 0x2D0F01C2ull;
+
+static const uint64_t P9N2_C_14_CPPM_IPPMWDATA = 0x2E0F01C2ull;
+
+static const uint64_t P9N2_C_15_CPPM_IPPMWDATA = 0x2F0F01C2ull;
+
+static const uint64_t P9N2_C_16_CPPM_IPPMWDATA = 0x300F01C2ull;
+
+static const uint64_t P9N2_C_17_CPPM_IPPMWDATA = 0x310F01C2ull;
+
+static const uint64_t P9N2_C_18_CPPM_IPPMWDATA = 0x320F01C2ull;
+
+static const uint64_t P9N2_C_19_CPPM_IPPMWDATA = 0x330F01C2ull;
+
+static const uint64_t P9N2_C_20_CPPM_IPPMWDATA = 0x340F01C2ull;
+
+static const uint64_t P9N2_C_21_CPPM_IPPMWDATA = 0x350F01C2ull;
+
+static const uint64_t P9N2_C_22_CPPM_IPPMWDATA = 0x360F01C2ull;
+
+static const uint64_t P9N2_C_23_CPPM_IPPMWDATA = 0x370F01C2ull;
+
+static const uint64_t P9N2_EX_CPPM_IPPMWDATA = 0x200F01C2ull;
+//DUPS: 210F01C2,
+static const uint64_t P9N2_EX_0_CPPM_IPPMWDATA = 0x200F01C2ull;
+//DUPS: 210F01C2,
+static const uint64_t P9N2_EX_1_CPPM_IPPMWDATA = 0x220F01C2ull;
+//DUPS: 220F01C2,
+static const uint64_t P9N2_EX_2_CPPM_IPPMWDATA = 0x240F01C2ull;
+//DUPS: 250F01C2,
+static const uint64_t P9N2_EX_3_CPPM_IPPMWDATA = 0x260F01C2ull;
+//DUPS: 270F01C2,
+static const uint64_t P9N2_EX_4_CPPM_IPPMWDATA = 0x280F01C2ull;
+//DUPS: 290F01C2,
+static const uint64_t P9N2_EX_5_CPPM_IPPMWDATA = 0x2A0F01C2ull;
+//DUPS: 2B0F01C2,
+static const uint64_t P9N2_EX_6_CPPM_IPPMWDATA = 0x2C0F01C2ull;
+//DUPS: 2D0F01C2,
+static const uint64_t P9N2_EX_7_CPPM_IPPMWDATA = 0x2E0F01C2ull;
+//DUPS: 2F0F01C2,
+static const uint64_t P9N2_EX_8_CPPM_IPPMWDATA = 0x300F01C2ull;
+//DUPS: 310F01C2,
+static const uint64_t P9N2_EX_9_CPPM_IPPMWDATA = 0x320F01C2ull;
+//DUPS: 330F01C2,
+static const uint64_t P9N2_EX_10_CPPM_IPPMWDATA = 0x340F01C2ull;
+//DUPS: 350F01C2,
+static const uint64_t P9N2_EX_11_CPPM_IPPMWDATA = 0x360F01C2ull;
+//DUPS: 370F01C2,
+
+static const uint64_t P9N2_C_CPPM_NC0INDIR_SCOM = 0x200F0130ull;
+
+static const uint64_t P9N2_C_CPPM_NC0INDIR_SCOM1 = 0x200F0131ull;
+
+static const uint64_t P9N2_C_CPPM_NC0INDIR_SCOM2 = 0x200F0132ull;
+
+static const uint64_t P9N2_C_0_CPPM_NC0INDIR_SCOM = 0x200F0130ull;
+
+static const uint64_t P9N2_C_0_CPPM_NC0INDIR_SCOM1 = 0x200F0131ull;
+
+static const uint64_t P9N2_C_0_CPPM_NC0INDIR_SCOM2 = 0x200F0132ull;
+
+static const uint64_t P9N2_C_1_CPPM_NC0INDIR_SCOM = 0x210F0130ull;
+
+static const uint64_t P9N2_C_1_CPPM_NC0INDIR_SCOM1 = 0x210F0131ull;
+
+static const uint64_t P9N2_C_1_CPPM_NC0INDIR_SCOM2 = 0x210F0132ull;
+
+static const uint64_t P9N2_C_2_CPPM_NC0INDIR_SCOM = 0x220F0130ull;
+
+static const uint64_t P9N2_C_2_CPPM_NC0INDIR_SCOM1 = 0x220F0131ull;
+
+static const uint64_t P9N2_C_2_CPPM_NC0INDIR_SCOM2 = 0x220F0132ull;
+
+static const uint64_t P9N2_C_3_CPPM_NC0INDIR_SCOM = 0x230F0130ull;
+
+static const uint64_t P9N2_C_3_CPPM_NC0INDIR_SCOM1 = 0x230F0131ull;
+
+static const uint64_t P9N2_C_3_CPPM_NC0INDIR_SCOM2 = 0x230F0132ull;
+
+static const uint64_t P9N2_C_4_CPPM_NC0INDIR_SCOM = 0x240F0130ull;
+
+static const uint64_t P9N2_C_4_CPPM_NC0INDIR_SCOM1 = 0x240F0131ull;
+
+static const uint64_t P9N2_C_4_CPPM_NC0INDIR_SCOM2 = 0x240F0132ull;
+
+static const uint64_t P9N2_C_5_CPPM_NC0INDIR_SCOM = 0x250F0130ull;
+
+static const uint64_t P9N2_C_5_CPPM_NC0INDIR_SCOM1 = 0x250F0131ull;
+
+static const uint64_t P9N2_C_5_CPPM_NC0INDIR_SCOM2 = 0x250F0132ull;
+
+static const uint64_t P9N2_C_6_CPPM_NC0INDIR_SCOM = 0x260F0130ull;
+
+static const uint64_t P9N2_C_6_CPPM_NC0INDIR_SCOM1 = 0x260F0131ull;
+
+static const uint64_t P9N2_C_6_CPPM_NC0INDIR_SCOM2 = 0x260F0132ull;
+
+static const uint64_t P9N2_C_7_CPPM_NC0INDIR_SCOM = 0x270F0130ull;
+
+static const uint64_t P9N2_C_7_CPPM_NC0INDIR_SCOM1 = 0x270F0131ull;
+
+static const uint64_t P9N2_C_7_CPPM_NC0INDIR_SCOM2 = 0x270F0132ull;
+
+static const uint64_t P9N2_C_8_CPPM_NC0INDIR_SCOM = 0x280F0130ull;
+
+static const uint64_t P9N2_C_8_CPPM_NC0INDIR_SCOM1 = 0x280F0131ull;
+
+static const uint64_t P9N2_C_8_CPPM_NC0INDIR_SCOM2 = 0x280F0132ull;
+
+static const uint64_t P9N2_C_9_CPPM_NC0INDIR_SCOM = 0x290F0130ull;
+
+static const uint64_t P9N2_C_9_CPPM_NC0INDIR_SCOM1 = 0x290F0131ull;
+
+static const uint64_t P9N2_C_9_CPPM_NC0INDIR_SCOM2 = 0x290F0132ull;
+
+static const uint64_t P9N2_C_10_CPPM_NC0INDIR_SCOM = 0x2A0F0130ull;
+
+static const uint64_t P9N2_C_10_CPPM_NC0INDIR_SCOM1 = 0x2A0F0131ull;
+
+static const uint64_t P9N2_C_10_CPPM_NC0INDIR_SCOM2 = 0x2A0F0132ull;
+
+static const uint64_t P9N2_C_11_CPPM_NC0INDIR_SCOM = 0x2B0F0130ull;
+
+static const uint64_t P9N2_C_11_CPPM_NC0INDIR_SCOM1 = 0x2B0F0131ull;
+
+static const uint64_t P9N2_C_11_CPPM_NC0INDIR_SCOM2 = 0x2B0F0132ull;
+
+static const uint64_t P9N2_C_12_CPPM_NC0INDIR_SCOM = 0x2C0F0130ull;
+
+static const uint64_t P9N2_C_12_CPPM_NC0INDIR_SCOM1 = 0x2C0F0131ull;
+
+static const uint64_t P9N2_C_12_CPPM_NC0INDIR_SCOM2 = 0x2C0F0132ull;
+
+static const uint64_t P9N2_C_13_CPPM_NC0INDIR_SCOM = 0x2D0F0130ull;
+
+static const uint64_t P9N2_C_13_CPPM_NC0INDIR_SCOM1 = 0x2D0F0131ull;
+
+static const uint64_t P9N2_C_13_CPPM_NC0INDIR_SCOM2 = 0x2D0F0132ull;
+
+static const uint64_t P9N2_C_14_CPPM_NC0INDIR_SCOM = 0x2E0F0130ull;
+
+static const uint64_t P9N2_C_14_CPPM_NC0INDIR_SCOM1 = 0x2E0F0131ull;
+
+static const uint64_t P9N2_C_14_CPPM_NC0INDIR_SCOM2 = 0x2E0F0132ull;
+
+static const uint64_t P9N2_C_15_CPPM_NC0INDIR_SCOM = 0x2F0F0130ull;
+
+static const uint64_t P9N2_C_15_CPPM_NC0INDIR_SCOM1 = 0x2F0F0131ull;
+
+static const uint64_t P9N2_C_15_CPPM_NC0INDIR_SCOM2 = 0x2F0F0132ull;
+
+static const uint64_t P9N2_C_16_CPPM_NC0INDIR_SCOM = 0x300F0130ull;
+
+static const uint64_t P9N2_C_16_CPPM_NC0INDIR_SCOM1 = 0x300F0131ull;
+
+static const uint64_t P9N2_C_16_CPPM_NC0INDIR_SCOM2 = 0x300F0132ull;
+
+static const uint64_t P9N2_C_17_CPPM_NC0INDIR_SCOM = 0x310F0130ull;
+
+static const uint64_t P9N2_C_17_CPPM_NC0INDIR_SCOM1 = 0x310F0131ull;
+
+static const uint64_t P9N2_C_17_CPPM_NC0INDIR_SCOM2 = 0x310F0132ull;
+
+static const uint64_t P9N2_C_18_CPPM_NC0INDIR_SCOM = 0x320F0130ull;
+
+static const uint64_t P9N2_C_18_CPPM_NC0INDIR_SCOM1 = 0x320F0131ull;
+
+static const uint64_t P9N2_C_18_CPPM_NC0INDIR_SCOM2 = 0x320F0132ull;
+
+static const uint64_t P9N2_C_19_CPPM_NC0INDIR_SCOM = 0x330F0130ull;
+
+static const uint64_t P9N2_C_19_CPPM_NC0INDIR_SCOM1 = 0x330F0131ull;
+
+static const uint64_t P9N2_C_19_CPPM_NC0INDIR_SCOM2 = 0x330F0132ull;
+
+static const uint64_t P9N2_C_20_CPPM_NC0INDIR_SCOM = 0x340F0130ull;
+
+static const uint64_t P9N2_C_20_CPPM_NC0INDIR_SCOM1 = 0x340F0131ull;
+
+static const uint64_t P9N2_C_20_CPPM_NC0INDIR_SCOM2 = 0x340F0132ull;
+
+static const uint64_t P9N2_C_21_CPPM_NC0INDIR_SCOM = 0x350F0130ull;
+
+static const uint64_t P9N2_C_21_CPPM_NC0INDIR_SCOM1 = 0x350F0131ull;
+
+static const uint64_t P9N2_C_21_CPPM_NC0INDIR_SCOM2 = 0x350F0132ull;
+
+static const uint64_t P9N2_C_22_CPPM_NC0INDIR_SCOM = 0x360F0130ull;
+
+static const uint64_t P9N2_C_22_CPPM_NC0INDIR_SCOM1 = 0x360F0131ull;
+
+static const uint64_t P9N2_C_22_CPPM_NC0INDIR_SCOM2 = 0x360F0132ull;
+
+static const uint64_t P9N2_C_23_CPPM_NC0INDIR_SCOM = 0x370F0130ull;
+
+static const uint64_t P9N2_C_23_CPPM_NC0INDIR_SCOM1 = 0x370F0131ull;
+
+static const uint64_t P9N2_C_23_CPPM_NC0INDIR_SCOM2 = 0x370F0132ull;
+
+static const uint64_t P9N2_EX_CPPM_NC0INDIR_SCOM = 0x200F0130ull;
+//DUPS: 210F0130,
+static const uint64_t P9N2_EX_CPPM_NC0INDIR_SCOM1 = 0x200F0131ull;
+//DUPS: 210F0131,
+static const uint64_t P9N2_EX_CPPM_NC0INDIR_SCOM2 = 0x200F0132ull;
+//DUPS: 210F0132,
+static const uint64_t P9N2_EX_0_CPPM_NC0INDIR_SCOM = 0x200F0130ull;
+//DUPS: 210F0130,
+static const uint64_t P9N2_EX_0_CPPM_NC0INDIR_SCOM1 = 0x200F0131ull;
+//DUPS: 210F0131,
+static const uint64_t P9N2_EX_0_CPPM_NC0INDIR_SCOM2 = 0x200F0132ull;
+//DUPS: 210F0132,
+static const uint64_t P9N2_EX_1_CPPM_NC0INDIR_SCOM = 0x220F0130ull;
+//DUPS: 220F0130,
+static const uint64_t P9N2_EX_1_CPPM_NC0INDIR_SCOM1 = 0x220F0131ull;
+//DUPS: 220F0131,
+static const uint64_t P9N2_EX_1_CPPM_NC0INDIR_SCOM2 = 0x220F0132ull;
+//DUPS: 220F0132,
+static const uint64_t P9N2_EX_2_CPPM_NC0INDIR_SCOM = 0x240F0130ull;
+//DUPS: 250F0130,
+static const uint64_t P9N2_EX_2_CPPM_NC0INDIR_SCOM1 = 0x240F0131ull;
+//DUPS: 250F0131,
+static const uint64_t P9N2_EX_2_CPPM_NC0INDIR_SCOM2 = 0x240F0132ull;
+//DUPS: 250F0132,
+static const uint64_t P9N2_EX_3_CPPM_NC0INDIR_SCOM = 0x260F0130ull;
+//DUPS: 270F0130,
+static const uint64_t P9N2_EX_3_CPPM_NC0INDIR_SCOM1 = 0x260F0131ull;
+//DUPS: 270F0131,
+static const uint64_t P9N2_EX_3_CPPM_NC0INDIR_SCOM2 = 0x260F0132ull;
+//DUPS: 270F0132,
+static const uint64_t P9N2_EX_4_CPPM_NC0INDIR_SCOM = 0x280F0130ull;
+//DUPS: 290F0130,
+static const uint64_t P9N2_EX_4_CPPM_NC0INDIR_SCOM1 = 0x280F0131ull;
+//DUPS: 290F0131,
+static const uint64_t P9N2_EX_4_CPPM_NC0INDIR_SCOM2 = 0x280F0132ull;
+//DUPS: 290F0132,
+static const uint64_t P9N2_EX_5_CPPM_NC0INDIR_SCOM = 0x2A0F0130ull;
+//DUPS: 2B0F0130,
+static const uint64_t P9N2_EX_5_CPPM_NC0INDIR_SCOM1 = 0x2A0F0131ull;
+//DUPS: 2B0F0131,
+static const uint64_t P9N2_EX_5_CPPM_NC0INDIR_SCOM2 = 0x2A0F0132ull;
+//DUPS: 2B0F0132,
+static const uint64_t P9N2_EX_6_CPPM_NC0INDIR_SCOM = 0x2C0F0130ull;
+//DUPS: 2D0F0130,
+static const uint64_t P9N2_EX_6_CPPM_NC0INDIR_SCOM1 = 0x2C0F0131ull;
+//DUPS: 2D0F0131,
+static const uint64_t P9N2_EX_6_CPPM_NC0INDIR_SCOM2 = 0x2C0F0132ull;
+//DUPS: 2D0F0132,
+static const uint64_t P9N2_EX_7_CPPM_NC0INDIR_SCOM = 0x2E0F0130ull;
+//DUPS: 2F0F0130,
+static const uint64_t P9N2_EX_7_CPPM_NC0INDIR_SCOM1 = 0x2E0F0131ull;
+//DUPS: 2F0F0131,
+static const uint64_t P9N2_EX_7_CPPM_NC0INDIR_SCOM2 = 0x2E0F0132ull;
+//DUPS: 2F0F0132,
+static const uint64_t P9N2_EX_8_CPPM_NC0INDIR_SCOM = 0x300F0130ull;
+//DUPS: 310F0130,
+static const uint64_t P9N2_EX_8_CPPM_NC0INDIR_SCOM1 = 0x300F0131ull;
+//DUPS: 310F0131,
+static const uint64_t P9N2_EX_8_CPPM_NC0INDIR_SCOM2 = 0x300F0132ull;
+//DUPS: 310F0132,
+static const uint64_t P9N2_EX_9_CPPM_NC0INDIR_SCOM = 0x320F0130ull;
+//DUPS: 330F0130,
+static const uint64_t P9N2_EX_9_CPPM_NC0INDIR_SCOM1 = 0x320F0131ull;
+//DUPS: 330F0131,
+static const uint64_t P9N2_EX_9_CPPM_NC0INDIR_SCOM2 = 0x320F0132ull;
+//DUPS: 330F0132,
+static const uint64_t P9N2_EX_10_CPPM_NC0INDIR_SCOM = 0x340F0130ull;
+//DUPS: 350F0130,
+static const uint64_t P9N2_EX_10_CPPM_NC0INDIR_SCOM1 = 0x340F0131ull;
+//DUPS: 350F0131,
+static const uint64_t P9N2_EX_10_CPPM_NC0INDIR_SCOM2 = 0x340F0132ull;
+//DUPS: 350F0132,
+static const uint64_t P9N2_EX_11_CPPM_NC0INDIR_SCOM = 0x360F0130ull;
+//DUPS: 370F0130,
+static const uint64_t P9N2_EX_11_CPPM_NC0INDIR_SCOM1 = 0x360F0131ull;
+//DUPS: 370F0131,
+static const uint64_t P9N2_EX_11_CPPM_NC0INDIR_SCOM2 = 0x360F0132ull;
+//DUPS: 370F0132,
+
+static const uint64_t P9N2_C_CPPM_NC1INDIR_SCOM = 0x200F0133ull;
+
+static const uint64_t P9N2_C_CPPM_NC1INDIR_SCOM1 = 0x200F0134ull;
+
+static const uint64_t P9N2_C_CPPM_NC1INDIR_SCOM2 = 0x200F0135ull;
+
+static const uint64_t P9N2_C_0_CPPM_NC1INDIR_SCOM = 0x200F0133ull;
+
+static const uint64_t P9N2_C_0_CPPM_NC1INDIR_SCOM1 = 0x200F0134ull;
+
+static const uint64_t P9N2_C_0_CPPM_NC1INDIR_SCOM2 = 0x200F0135ull;
+
+static const uint64_t P9N2_C_1_CPPM_NC1INDIR_SCOM = 0x210F0133ull;
+
+static const uint64_t P9N2_C_1_CPPM_NC1INDIR_SCOM1 = 0x210F0134ull;
+
+static const uint64_t P9N2_C_1_CPPM_NC1INDIR_SCOM2 = 0x210F0135ull;
+
+static const uint64_t P9N2_C_2_CPPM_NC1INDIR_SCOM = 0x220F0133ull;
+
+static const uint64_t P9N2_C_2_CPPM_NC1INDIR_SCOM1 = 0x220F0134ull;
+
+static const uint64_t P9N2_C_2_CPPM_NC1INDIR_SCOM2 = 0x220F0135ull;
+
+static const uint64_t P9N2_C_3_CPPM_NC1INDIR_SCOM = 0x230F0133ull;
+
+static const uint64_t P9N2_C_3_CPPM_NC1INDIR_SCOM1 = 0x230F0134ull;
+
+static const uint64_t P9N2_C_3_CPPM_NC1INDIR_SCOM2 = 0x230F0135ull;
+
+static const uint64_t P9N2_C_4_CPPM_NC1INDIR_SCOM = 0x240F0133ull;
+
+static const uint64_t P9N2_C_4_CPPM_NC1INDIR_SCOM1 = 0x240F0134ull;
+
+static const uint64_t P9N2_C_4_CPPM_NC1INDIR_SCOM2 = 0x240F0135ull;
+
+static const uint64_t P9N2_C_5_CPPM_NC1INDIR_SCOM = 0x250F0133ull;
+
+static const uint64_t P9N2_C_5_CPPM_NC1INDIR_SCOM1 = 0x250F0134ull;
+
+static const uint64_t P9N2_C_5_CPPM_NC1INDIR_SCOM2 = 0x250F0135ull;
+
+static const uint64_t P9N2_C_6_CPPM_NC1INDIR_SCOM = 0x260F0133ull;
+
+static const uint64_t P9N2_C_6_CPPM_NC1INDIR_SCOM1 = 0x260F0134ull;
+
+static const uint64_t P9N2_C_6_CPPM_NC1INDIR_SCOM2 = 0x260F0135ull;
+
+static const uint64_t P9N2_C_7_CPPM_NC1INDIR_SCOM = 0x270F0133ull;
+
+static const uint64_t P9N2_C_7_CPPM_NC1INDIR_SCOM1 = 0x270F0134ull;
+
+static const uint64_t P9N2_C_7_CPPM_NC1INDIR_SCOM2 = 0x270F0135ull;
+
+static const uint64_t P9N2_C_8_CPPM_NC1INDIR_SCOM = 0x280F0133ull;
+
+static const uint64_t P9N2_C_8_CPPM_NC1INDIR_SCOM1 = 0x280F0134ull;
+
+static const uint64_t P9N2_C_8_CPPM_NC1INDIR_SCOM2 = 0x280F0135ull;
+
+static const uint64_t P9N2_C_9_CPPM_NC1INDIR_SCOM = 0x290F0133ull;
+
+static const uint64_t P9N2_C_9_CPPM_NC1INDIR_SCOM1 = 0x290F0134ull;
+
+static const uint64_t P9N2_C_9_CPPM_NC1INDIR_SCOM2 = 0x290F0135ull;
+
+static const uint64_t P9N2_C_10_CPPM_NC1INDIR_SCOM = 0x2A0F0133ull;
+
+static const uint64_t P9N2_C_10_CPPM_NC1INDIR_SCOM1 = 0x2A0F0134ull;
+
+static const uint64_t P9N2_C_10_CPPM_NC1INDIR_SCOM2 = 0x2A0F0135ull;
+
+static const uint64_t P9N2_C_11_CPPM_NC1INDIR_SCOM = 0x2B0F0133ull;
+
+static const uint64_t P9N2_C_11_CPPM_NC1INDIR_SCOM1 = 0x2B0F0134ull;
+
+static const uint64_t P9N2_C_11_CPPM_NC1INDIR_SCOM2 = 0x2B0F0135ull;
+
+static const uint64_t P9N2_C_12_CPPM_NC1INDIR_SCOM = 0x2C0F0133ull;
+
+static const uint64_t P9N2_C_12_CPPM_NC1INDIR_SCOM1 = 0x2C0F0134ull;
+
+static const uint64_t P9N2_C_12_CPPM_NC1INDIR_SCOM2 = 0x2C0F0135ull;
+
+static const uint64_t P9N2_C_13_CPPM_NC1INDIR_SCOM = 0x2D0F0133ull;
+
+static const uint64_t P9N2_C_13_CPPM_NC1INDIR_SCOM1 = 0x2D0F0134ull;
+
+static const uint64_t P9N2_C_13_CPPM_NC1INDIR_SCOM2 = 0x2D0F0135ull;
+
+static const uint64_t P9N2_C_14_CPPM_NC1INDIR_SCOM = 0x2E0F0133ull;
+
+static const uint64_t P9N2_C_14_CPPM_NC1INDIR_SCOM1 = 0x2E0F0134ull;
+
+static const uint64_t P9N2_C_14_CPPM_NC1INDIR_SCOM2 = 0x2E0F0135ull;
+
+static const uint64_t P9N2_C_15_CPPM_NC1INDIR_SCOM = 0x2F0F0133ull;
+
+static const uint64_t P9N2_C_15_CPPM_NC1INDIR_SCOM1 = 0x2F0F0134ull;
+
+static const uint64_t P9N2_C_15_CPPM_NC1INDIR_SCOM2 = 0x2F0F0135ull;
+
+static const uint64_t P9N2_C_16_CPPM_NC1INDIR_SCOM = 0x300F0133ull;
+
+static const uint64_t P9N2_C_16_CPPM_NC1INDIR_SCOM1 = 0x300F0134ull;
+
+static const uint64_t P9N2_C_16_CPPM_NC1INDIR_SCOM2 = 0x300F0135ull;
+
+static const uint64_t P9N2_C_17_CPPM_NC1INDIR_SCOM = 0x310F0133ull;
+
+static const uint64_t P9N2_C_17_CPPM_NC1INDIR_SCOM1 = 0x310F0134ull;
+
+static const uint64_t P9N2_C_17_CPPM_NC1INDIR_SCOM2 = 0x310F0135ull;
+
+static const uint64_t P9N2_C_18_CPPM_NC1INDIR_SCOM = 0x320F0133ull;
+
+static const uint64_t P9N2_C_18_CPPM_NC1INDIR_SCOM1 = 0x320F0134ull;
+
+static const uint64_t P9N2_C_18_CPPM_NC1INDIR_SCOM2 = 0x320F0135ull;
+
+static const uint64_t P9N2_C_19_CPPM_NC1INDIR_SCOM = 0x330F0133ull;
+
+static const uint64_t P9N2_C_19_CPPM_NC1INDIR_SCOM1 = 0x330F0134ull;
+
+static const uint64_t P9N2_C_19_CPPM_NC1INDIR_SCOM2 = 0x330F0135ull;
+
+static const uint64_t P9N2_C_20_CPPM_NC1INDIR_SCOM = 0x340F0133ull;
+
+static const uint64_t P9N2_C_20_CPPM_NC1INDIR_SCOM1 = 0x340F0134ull;
+
+static const uint64_t P9N2_C_20_CPPM_NC1INDIR_SCOM2 = 0x340F0135ull;
+
+static const uint64_t P9N2_C_21_CPPM_NC1INDIR_SCOM = 0x350F0133ull;
+
+static const uint64_t P9N2_C_21_CPPM_NC1INDIR_SCOM1 = 0x350F0134ull;
+
+static const uint64_t P9N2_C_21_CPPM_NC1INDIR_SCOM2 = 0x350F0135ull;
+
+static const uint64_t P9N2_C_22_CPPM_NC1INDIR_SCOM = 0x360F0133ull;
+
+static const uint64_t P9N2_C_22_CPPM_NC1INDIR_SCOM1 = 0x360F0134ull;
+
+static const uint64_t P9N2_C_22_CPPM_NC1INDIR_SCOM2 = 0x360F0135ull;
+
+static const uint64_t P9N2_C_23_CPPM_NC1INDIR_SCOM = 0x370F0133ull;
+
+static const uint64_t P9N2_C_23_CPPM_NC1INDIR_SCOM1 = 0x370F0134ull;
+
+static const uint64_t P9N2_C_23_CPPM_NC1INDIR_SCOM2 = 0x370F0135ull;
+
+static const uint64_t P9N2_EX_CPPM_NC1INDIR_SCOM = 0x200F0133ull;
+//DUPS: 210F0133,
+static const uint64_t P9N2_EX_CPPM_NC1INDIR_SCOM1 = 0x200F0134ull;
+//DUPS: 210F0134,
+static const uint64_t P9N2_EX_CPPM_NC1INDIR_SCOM2 = 0x200F0135ull;
+//DUPS: 210F0135,
+static const uint64_t P9N2_EX_0_CPPM_NC1INDIR_SCOM = 0x200F0133ull;
+//DUPS: 210F0133,
+static const uint64_t P9N2_EX_0_CPPM_NC1INDIR_SCOM1 = 0x200F0134ull;
+//DUPS: 210F0134,
+static const uint64_t P9N2_EX_0_CPPM_NC1INDIR_SCOM2 = 0x200F0135ull;
+//DUPS: 210F0135,
+static const uint64_t P9N2_EX_1_CPPM_NC1INDIR_SCOM = 0x220F0133ull;
+//DUPS: 220F0133,
+static const uint64_t P9N2_EX_1_CPPM_NC1INDIR_SCOM1 = 0x220F0134ull;
+//DUPS: 220F0134,
+static const uint64_t P9N2_EX_1_CPPM_NC1INDIR_SCOM2 = 0x220F0135ull;
+//DUPS: 220F0135,
+static const uint64_t P9N2_EX_2_CPPM_NC1INDIR_SCOM = 0x240F0133ull;
+//DUPS: 250F0133,
+static const uint64_t P9N2_EX_2_CPPM_NC1INDIR_SCOM1 = 0x240F0134ull;
+//DUPS: 250F0134,
+static const uint64_t P9N2_EX_2_CPPM_NC1INDIR_SCOM2 = 0x240F0135ull;
+//DUPS: 250F0135,
+static const uint64_t P9N2_EX_3_CPPM_NC1INDIR_SCOM = 0x260F0133ull;
+//DUPS: 270F0133,
+static const uint64_t P9N2_EX_3_CPPM_NC1INDIR_SCOM1 = 0x260F0134ull;
+//DUPS: 270F0134,
+static const uint64_t P9N2_EX_3_CPPM_NC1INDIR_SCOM2 = 0x260F0135ull;
+//DUPS: 270F0135,
+static const uint64_t P9N2_EX_4_CPPM_NC1INDIR_SCOM = 0x280F0133ull;
+//DUPS: 290F0133,
+static const uint64_t P9N2_EX_4_CPPM_NC1INDIR_SCOM1 = 0x280F0134ull;
+//DUPS: 290F0134,
+static const uint64_t P9N2_EX_4_CPPM_NC1INDIR_SCOM2 = 0x280F0135ull;
+//DUPS: 290F0135,
+static const uint64_t P9N2_EX_5_CPPM_NC1INDIR_SCOM = 0x2A0F0133ull;
+//DUPS: 2B0F0133,
+static const uint64_t P9N2_EX_5_CPPM_NC1INDIR_SCOM1 = 0x2A0F0134ull;
+//DUPS: 2B0F0134,
+static const uint64_t P9N2_EX_5_CPPM_NC1INDIR_SCOM2 = 0x2A0F0135ull;
+//DUPS: 2B0F0135,
+static const uint64_t P9N2_EX_6_CPPM_NC1INDIR_SCOM = 0x2C0F0133ull;
+//DUPS: 2D0F0133,
+static const uint64_t P9N2_EX_6_CPPM_NC1INDIR_SCOM1 = 0x2C0F0134ull;
+//DUPS: 2D0F0134,
+static const uint64_t P9N2_EX_6_CPPM_NC1INDIR_SCOM2 = 0x2C0F0135ull;
+//DUPS: 2D0F0135,
+static const uint64_t P9N2_EX_7_CPPM_NC1INDIR_SCOM = 0x2E0F0133ull;
+//DUPS: 2F0F0133,
+static const uint64_t P9N2_EX_7_CPPM_NC1INDIR_SCOM1 = 0x2E0F0134ull;
+//DUPS: 2F0F0134,
+static const uint64_t P9N2_EX_7_CPPM_NC1INDIR_SCOM2 = 0x2E0F0135ull;
+//DUPS: 2F0F0135,
+static const uint64_t P9N2_EX_8_CPPM_NC1INDIR_SCOM = 0x300F0133ull;
+//DUPS: 310F0133,
+static const uint64_t P9N2_EX_8_CPPM_NC1INDIR_SCOM1 = 0x300F0134ull;
+//DUPS: 310F0134,
+static const uint64_t P9N2_EX_8_CPPM_NC1INDIR_SCOM2 = 0x300F0135ull;
+//DUPS: 310F0135,
+static const uint64_t P9N2_EX_9_CPPM_NC1INDIR_SCOM = 0x320F0133ull;
+//DUPS: 330F0133,
+static const uint64_t P9N2_EX_9_CPPM_NC1INDIR_SCOM1 = 0x320F0134ull;
+//DUPS: 330F0134,
+static const uint64_t P9N2_EX_9_CPPM_NC1INDIR_SCOM2 = 0x320F0135ull;
+//DUPS: 330F0135,
+static const uint64_t P9N2_EX_10_CPPM_NC1INDIR_SCOM = 0x340F0133ull;
+//DUPS: 350F0133,
+static const uint64_t P9N2_EX_10_CPPM_NC1INDIR_SCOM1 = 0x340F0134ull;
+//DUPS: 350F0134,
+static const uint64_t P9N2_EX_10_CPPM_NC1INDIR_SCOM2 = 0x340F0135ull;
+//DUPS: 350F0135,
+static const uint64_t P9N2_EX_11_CPPM_NC1INDIR_SCOM = 0x360F0133ull;
+//DUPS: 370F0133,
+static const uint64_t P9N2_EX_11_CPPM_NC1INDIR_SCOM1 = 0x360F0134ull;
+//DUPS: 370F0134,
+static const uint64_t P9N2_EX_11_CPPM_NC1INDIR_SCOM2 = 0x360F0135ull;
+//DUPS: 370F0135,
+
+static const uint64_t P9N2_C_CPPM_PECES = 0x200F01AFull;
+
+static const uint64_t P9N2_C_0_CPPM_PECES = 0x200F01AFull;
+
+static const uint64_t P9N2_C_1_CPPM_PECES = 0x210F01AFull;
+
+static const uint64_t P9N2_C_2_CPPM_PECES = 0x220F01AFull;
+
+static const uint64_t P9N2_C_3_CPPM_PECES = 0x230F01AFull;
+
+static const uint64_t P9N2_C_4_CPPM_PECES = 0x240F01AFull;
+
+static const uint64_t P9N2_C_5_CPPM_PECES = 0x250F01AFull;
+
+static const uint64_t P9N2_C_6_CPPM_PECES = 0x260F01AFull;
+
+static const uint64_t P9N2_C_7_CPPM_PECES = 0x270F01AFull;
+
+static const uint64_t P9N2_C_8_CPPM_PECES = 0x280F01AFull;
+
+static const uint64_t P9N2_C_9_CPPM_PECES = 0x290F01AFull;
+
+static const uint64_t P9N2_C_10_CPPM_PECES = 0x2A0F01AFull;
+
+static const uint64_t P9N2_C_11_CPPM_PECES = 0x2B0F01AFull;
+
+static const uint64_t P9N2_C_12_CPPM_PECES = 0x2C0F01AFull;
+
+static const uint64_t P9N2_C_13_CPPM_PECES = 0x2D0F01AFull;
+
+static const uint64_t P9N2_C_14_CPPM_PECES = 0x2E0F01AFull;
+
+static const uint64_t P9N2_C_15_CPPM_PECES = 0x2F0F01AFull;
+
+static const uint64_t P9N2_C_16_CPPM_PECES = 0x300F01AFull;
+
+static const uint64_t P9N2_C_17_CPPM_PECES = 0x310F01AFull;
+
+static const uint64_t P9N2_C_18_CPPM_PECES = 0x320F01AFull;
+
+static const uint64_t P9N2_C_19_CPPM_PECES = 0x330F01AFull;
+
+static const uint64_t P9N2_C_20_CPPM_PECES = 0x340F01AFull;
+
+static const uint64_t P9N2_C_21_CPPM_PECES = 0x350F01AFull;
+
+static const uint64_t P9N2_C_22_CPPM_PECES = 0x360F01AFull;
+
+static const uint64_t P9N2_C_23_CPPM_PECES = 0x370F01AFull;
+
+static const uint64_t P9N2_EX_CPPM_PECES = 0x200F01AFull;
+//DUPS: 210F01AF,
+static const uint64_t P9N2_EX_0_CPPM_PECES = 0x200F01AFull;
+//DUPS: 210F01AF,
+static const uint64_t P9N2_EX_1_CPPM_PECES = 0x220F01AFull;
+//DUPS: 220F01AF,
+static const uint64_t P9N2_EX_2_CPPM_PECES = 0x240F01AFull;
+//DUPS: 250F01AF,
+static const uint64_t P9N2_EX_3_CPPM_PECES = 0x260F01AFull;
+//DUPS: 270F01AF,
+static const uint64_t P9N2_EX_4_CPPM_PECES = 0x280F01AFull;
+//DUPS: 290F01AF,
+static const uint64_t P9N2_EX_5_CPPM_PECES = 0x2A0F01AFull;
+//DUPS: 2B0F01AF,
+static const uint64_t P9N2_EX_6_CPPM_PECES = 0x2C0F01AFull;
+//DUPS: 2D0F01AF,
+static const uint64_t P9N2_EX_7_CPPM_PECES = 0x2E0F01AFull;
+//DUPS: 2F0F01AF,
+static const uint64_t P9N2_EX_8_CPPM_PECES = 0x300F01AFull;
+//DUPS: 310F01AF,
+static const uint64_t P9N2_EX_9_CPPM_PECES = 0x320F01AFull;
+//DUPS: 330F01AF,
+static const uint64_t P9N2_EX_10_CPPM_PECES = 0x340F01AFull;
+//DUPS: 350F01AF,
+static const uint64_t P9N2_EX_11_CPPM_PECES = 0x360F01AFull;
+//DUPS: 370F01AF,
+
+static const uint64_t P9N2_C_CPPM_PERRSUM = 0x200F0120ull;
+
+static const uint64_t P9N2_C_0_CPPM_PERRSUM = 0x200F0120ull;
+
+static const uint64_t P9N2_C_1_CPPM_PERRSUM = 0x210F0120ull;
+
+static const uint64_t P9N2_C_2_CPPM_PERRSUM = 0x220F0120ull;
+
+static const uint64_t P9N2_C_3_CPPM_PERRSUM = 0x230F0120ull;
+
+static const uint64_t P9N2_C_4_CPPM_PERRSUM = 0x240F0120ull;
+
+static const uint64_t P9N2_C_5_CPPM_PERRSUM = 0x250F0120ull;
+
+static const uint64_t P9N2_C_6_CPPM_PERRSUM = 0x260F0120ull;
+
+static const uint64_t P9N2_C_7_CPPM_PERRSUM = 0x270F0120ull;
+
+static const uint64_t P9N2_C_8_CPPM_PERRSUM = 0x280F0120ull;
+
+static const uint64_t P9N2_C_9_CPPM_PERRSUM = 0x290F0120ull;
+
+static const uint64_t P9N2_C_10_CPPM_PERRSUM = 0x2A0F0120ull;
+
+static const uint64_t P9N2_C_11_CPPM_PERRSUM = 0x2B0F0120ull;
+
+static const uint64_t P9N2_C_12_CPPM_PERRSUM = 0x2C0F0120ull;
+
+static const uint64_t P9N2_C_13_CPPM_PERRSUM = 0x2D0F0120ull;
+
+static const uint64_t P9N2_C_14_CPPM_PERRSUM = 0x2E0F0120ull;
+
+static const uint64_t P9N2_C_15_CPPM_PERRSUM = 0x2F0F0120ull;
+
+static const uint64_t P9N2_C_16_CPPM_PERRSUM = 0x300F0120ull;
+
+static const uint64_t P9N2_C_17_CPPM_PERRSUM = 0x310F0120ull;
+
+static const uint64_t P9N2_C_18_CPPM_PERRSUM = 0x320F0120ull;
+
+static const uint64_t P9N2_C_19_CPPM_PERRSUM = 0x330F0120ull;
+
+static const uint64_t P9N2_C_20_CPPM_PERRSUM = 0x340F0120ull;
+
+static const uint64_t P9N2_C_21_CPPM_PERRSUM = 0x350F0120ull;
+
+static const uint64_t P9N2_C_22_CPPM_PERRSUM = 0x360F0120ull;
+
+static const uint64_t P9N2_C_23_CPPM_PERRSUM = 0x370F0120ull;
+
+static const uint64_t P9N2_EX_CPPM_PERRSUM = 0x200F0120ull;
+//DUPS: 210F0120,
+static const uint64_t P9N2_EX_0_CPPM_PERRSUM = 0x200F0120ull;
+//DUPS: 210F0120,
+static const uint64_t P9N2_EX_1_CPPM_PERRSUM = 0x220F0120ull;
+//DUPS: 220F0120,
+static const uint64_t P9N2_EX_2_CPPM_PERRSUM = 0x240F0120ull;
+//DUPS: 250F0120,
+static const uint64_t P9N2_EX_3_CPPM_PERRSUM = 0x260F0120ull;
+//DUPS: 270F0120,
+static const uint64_t P9N2_EX_4_CPPM_PERRSUM = 0x280F0120ull;
+//DUPS: 290F0120,
+static const uint64_t P9N2_EX_5_CPPM_PERRSUM = 0x2A0F0120ull;
+//DUPS: 2B0F0120,
+static const uint64_t P9N2_EX_6_CPPM_PERRSUM = 0x2C0F0120ull;
+//DUPS: 2D0F0120,
+static const uint64_t P9N2_EX_7_CPPM_PERRSUM = 0x2E0F0120ull;
+//DUPS: 2F0F0120,
+static const uint64_t P9N2_EX_8_CPPM_PERRSUM = 0x300F0120ull;
+//DUPS: 310F0120,
+static const uint64_t P9N2_EX_9_CPPM_PERRSUM = 0x320F0120ull;
+//DUPS: 330F0120,
+static const uint64_t P9N2_EX_10_CPPM_PERRSUM = 0x340F0120ull;
+//DUPS: 350F0120,
+static const uint64_t P9N2_EX_11_CPPM_PERRSUM = 0x360F0120ull;
+//DUPS: 370F0120,
+
+static const uint64_t P9N2_EQ_CSAR = 0x1001200Dull;
+//DUPS: 1001200D,
+static const uint64_t P9N2_EQ_0_CSAR = 0x1001200Dull;
+//DUPS: 1001200D,
+static const uint64_t P9N2_EQ_1_CSAR = 0x1101200Dull;
+//DUPS: 1101200D,
+static const uint64_t P9N2_EQ_2_CSAR = 0x1201200Dull;
+//DUPS: 1201200D,
+static const uint64_t P9N2_EQ_3_CSAR = 0x1301200Dull;
+//DUPS: 1301200D,
+static const uint64_t P9N2_EQ_4_CSAR = 0x1401200Dull;
+//DUPS: 1401200D,
+static const uint64_t P9N2_EQ_5_CSAR = 0x1501200Dull;
+//DUPS: 1501200D,
+static const uint64_t P9N2_EX_CSAR = 0x1001200Dull;
+
+static const uint64_t P9N2_EX_0_CSAR = 0x1001200Dull;
+
+static const uint64_t P9N2_EX_1_CSAR = 0x1001240Dull;
+
+static const uint64_t P9N2_EX_2_CSAR = 0x1101200Dull;
+
+static const uint64_t P9N2_EX_3_CSAR = 0x1101240Dull;
+
+static const uint64_t P9N2_EX_4_CSAR = 0x1201200Dull;
+
+static const uint64_t P9N2_EX_5_CSAR = 0x1201240Dull;
+
+static const uint64_t P9N2_EX_6_CSAR = 0x1301200Dull;
+
+static const uint64_t P9N2_EX_7_CSAR = 0x1301240Dull;
+
+static const uint64_t P9N2_EX_8_CSAR = 0x1401200Dull;
+
+static const uint64_t P9N2_EX_9_CSAR = 0x1401240Dull;
+
+static const uint64_t P9N2_EX_10_CSAR = 0x1501200Dull;
+
+static const uint64_t P9N2_EX_11_CSAR = 0x1501240Dull;
+
+
+static const uint64_t P9N2_EQ_CSCR = 0x1001200Aull;
+//DUPS: 1001200A,
+static const uint64_t P9N2_EQ_CSCR_CLEAR = 0x1001200Bull;
+//DUPS: 1001200B,
+static const uint64_t P9N2_EQ_CSCR_OR = 0x1001200Cull;
+//DUPS: 1001200C,
+static const uint64_t P9N2_EQ_0_CSCR = 0x1001200Aull;
+//DUPS: 1001200A,
+static const uint64_t P9N2_EQ_0_CSCR_CLEAR = 0x1001200Bull;
+//DUPS: 1001200B,
+static const uint64_t P9N2_EQ_0_CSCR_OR = 0x1001200Cull;
+//DUPS: 1001200C,
+static const uint64_t P9N2_EQ_1_CSCR = 0x1101200Aull;
+//DUPS: 1101200A,
+static const uint64_t P9N2_EQ_1_CSCR_CLEAR = 0x1101200Bull;
+//DUPS: 1101200B,
+static const uint64_t P9N2_EQ_1_CSCR_OR = 0x1101200Cull;
+//DUPS: 1101200C,
+static const uint64_t P9N2_EQ_2_CSCR = 0x1201200Aull;
+//DUPS: 1201200A,
+static const uint64_t P9N2_EQ_2_CSCR_CLEAR = 0x1201200Bull;
+//DUPS: 1201200B,
+static const uint64_t P9N2_EQ_2_CSCR_OR = 0x1201200Cull;
+//DUPS: 1201200C,
+static const uint64_t P9N2_EQ_3_CSCR = 0x1301200Aull;
+//DUPS: 1301200A,
+static const uint64_t P9N2_EQ_3_CSCR_CLEAR = 0x1301200Bull;
+//DUPS: 1301200B,
+static const uint64_t P9N2_EQ_3_CSCR_OR = 0x1301200Cull;
+//DUPS: 1301200C,
+static const uint64_t P9N2_EQ_4_CSCR = 0x1401200Aull;
+//DUPS: 1401200A,
+static const uint64_t P9N2_EQ_4_CSCR_CLEAR = 0x1401200Bull;
+//DUPS: 1401200B,
+static const uint64_t P9N2_EQ_4_CSCR_OR = 0x1401200Cull;
+//DUPS: 1401200C,
+static const uint64_t P9N2_EQ_5_CSCR = 0x1501200Aull;
+//DUPS: 1501200A,
+static const uint64_t P9N2_EQ_5_CSCR_CLEAR = 0x1501200Bull;
+//DUPS: 1501200B,
+static const uint64_t P9N2_EQ_5_CSCR_OR = 0x1501200Cull;
+//DUPS: 1501200C,
+static const uint64_t P9N2_EX_CSCR = 0x1001200Aull;
+
+static const uint64_t P9N2_EX_CSCR_CLEAR = 0x1001200Bull;
+
+static const uint64_t P9N2_EX_CSCR_OR = 0x1001200Cull;
+
+static const uint64_t P9N2_EX_0_CSCR = 0x1001200Aull;
+
+static const uint64_t P9N2_EX_0_CSCR_CLEAR = 0x1001200Bull;
+
+static const uint64_t P9N2_EX_0_CSCR_OR = 0x1001200Cull;
+
+static const uint64_t P9N2_EX_1_CSCR = 0x1001240Aull;
+
+static const uint64_t P9N2_EX_1_CSCR_CLEAR = 0x1001240Bull;
+
+static const uint64_t P9N2_EX_1_CSCR_OR = 0x1001240Cull;
+
+static const uint64_t P9N2_EX_2_CSCR = 0x1101200Aull;
+
+static const uint64_t P9N2_EX_2_CSCR_CLEAR = 0x1101200Bull;
+
+static const uint64_t P9N2_EX_2_CSCR_OR = 0x1101200Cull;
+
+static const uint64_t P9N2_EX_3_CSCR = 0x1101240Aull;
+
+static const uint64_t P9N2_EX_3_CSCR_CLEAR = 0x1101240Bull;
+
+static const uint64_t P9N2_EX_3_CSCR_OR = 0x1101240Cull;
+
+static const uint64_t P9N2_EX_4_CSCR = 0x1201200Aull;
+
+static const uint64_t P9N2_EX_4_CSCR_CLEAR = 0x1201200Bull;
+
+static const uint64_t P9N2_EX_4_CSCR_OR = 0x1201200Cull;
+
+static const uint64_t P9N2_EX_5_CSCR = 0x1201240Aull;
+
+static const uint64_t P9N2_EX_5_CSCR_CLEAR = 0x1201240Bull;
+
+static const uint64_t P9N2_EX_5_CSCR_OR = 0x1201240Cull;
+
+static const uint64_t P9N2_EX_6_CSCR = 0x1301200Aull;
+
+static const uint64_t P9N2_EX_6_CSCR_CLEAR = 0x1301200Bull;
+
+static const uint64_t P9N2_EX_6_CSCR_OR = 0x1301200Cull;
+
+static const uint64_t P9N2_EX_7_CSCR = 0x1301240Aull;
+
+static const uint64_t P9N2_EX_7_CSCR_CLEAR = 0x1301240Bull;
+
+static const uint64_t P9N2_EX_7_CSCR_OR = 0x1301240Cull;
+
+static const uint64_t P9N2_EX_8_CSCR = 0x1401200Aull;
+
+static const uint64_t P9N2_EX_8_CSCR_CLEAR = 0x1401200Bull;
+
+static const uint64_t P9N2_EX_8_CSCR_OR = 0x1401200Cull;
+
+static const uint64_t P9N2_EX_9_CSCR = 0x1401240Aull;
+
+static const uint64_t P9N2_EX_9_CSCR_CLEAR = 0x1401240Bull;
+
+static const uint64_t P9N2_EX_9_CSCR_OR = 0x1401240Cull;
+
+static const uint64_t P9N2_EX_10_CSCR = 0x1501200Aull;
+
+static const uint64_t P9N2_EX_10_CSCR_CLEAR = 0x1501200Bull;
+
+static const uint64_t P9N2_EX_10_CSCR_OR = 0x1501200Cull;
+
+static const uint64_t P9N2_EX_11_CSCR = 0x1501240Aull;
+
+static const uint64_t P9N2_EX_11_CSCR_CLEAR = 0x1501240Bull;
+
+static const uint64_t P9N2_EX_11_CSCR_OR = 0x1501240Cull;
+
+
+static const uint64_t P9N2_EQ_CSDR = 0x1001200Eull;
+//DUPS: 1001200E,
+static const uint64_t P9N2_EQ_0_CSDR = 0x1001200Eull;
+//DUPS: 1001200E,
+static const uint64_t P9N2_EQ_1_CSDR = 0x1101200Eull;
+//DUPS: 1101200E,
+static const uint64_t P9N2_EQ_2_CSDR = 0x1201200Eull;
+//DUPS: 1201200E,
+static const uint64_t P9N2_EQ_3_CSDR = 0x1301200Eull;
+//DUPS: 1301200E,
+static const uint64_t P9N2_EQ_4_CSDR = 0x1401200Eull;
+//DUPS: 1401200E,
+static const uint64_t P9N2_EQ_5_CSDR = 0x1501200Eull;
+//DUPS: 1501200E,
+static const uint64_t P9N2_EX_CSDR = 0x1001200Eull;
+
+static const uint64_t P9N2_EX_0_CSDR = 0x1001200Eull;
+
+static const uint64_t P9N2_EX_1_CSDR = 0x1001240Eull;
+
+static const uint64_t P9N2_EX_2_CSDR = 0x1101200Eull;
+
+static const uint64_t P9N2_EX_3_CSDR = 0x1101240Eull;
+
+static const uint64_t P9N2_EX_4_CSDR = 0x1201200Eull;
+
+static const uint64_t P9N2_EX_5_CSDR = 0x1201240Eull;
+
+static const uint64_t P9N2_EX_6_CSDR = 0x1301200Eull;
+
+static const uint64_t P9N2_EX_7_CSDR = 0x1301240Eull;
+
+static const uint64_t P9N2_EX_8_CSDR = 0x1401200Eull;
+
+static const uint64_t P9N2_EX_9_CSDR = 0x1401240Eull;
+
+static const uint64_t P9N2_EX_10_CSDR = 0x1501200Eull;
+
+static const uint64_t P9N2_EX_11_CSDR = 0x1501240Eull;
+
+
+static const uint64_t P9N2_C_CTRL = 0x20010A85ull;
+
+static const uint64_t P9N2_C_0_CTRL = 0x20010A85ull;
+
+static const uint64_t P9N2_C_1_CTRL = 0x21010A85ull;
+
+static const uint64_t P9N2_C_2_CTRL = 0x22010A85ull;
+
+static const uint64_t P9N2_C_3_CTRL = 0x23010A85ull;
+
+static const uint64_t P9N2_C_4_CTRL = 0x24010A85ull;
+
+static const uint64_t P9N2_C_5_CTRL = 0x25010A85ull;
+
+static const uint64_t P9N2_C_6_CTRL = 0x26010A85ull;
+
+static const uint64_t P9N2_C_7_CTRL = 0x27010A85ull;
+
+static const uint64_t P9N2_C_8_CTRL = 0x28010A85ull;
+
+static const uint64_t P9N2_C_9_CTRL = 0x29010A85ull;
+
+static const uint64_t P9N2_C_10_CTRL = 0x2A010A85ull;
+
+static const uint64_t P9N2_C_11_CTRL = 0x2B010A85ull;
+
+static const uint64_t P9N2_C_12_CTRL = 0x2C010A85ull;
+
+static const uint64_t P9N2_C_13_CTRL = 0x2D010A85ull;
+
+static const uint64_t P9N2_C_14_CTRL = 0x2E010A85ull;
+
+static const uint64_t P9N2_C_15_CTRL = 0x2F010A85ull;
+
+static const uint64_t P9N2_C_16_CTRL = 0x30010A85ull;
+
+static const uint64_t P9N2_C_17_CTRL = 0x31010A85ull;
+
+static const uint64_t P9N2_C_18_CTRL = 0x32010A85ull;
+
+static const uint64_t P9N2_C_19_CTRL = 0x33010A85ull;
+
+static const uint64_t P9N2_C_20_CTRL = 0x34010A85ull;
+
+static const uint64_t P9N2_C_21_CTRL = 0x35010A85ull;
+
+static const uint64_t P9N2_C_22_CTRL = 0x36010A85ull;
+
+static const uint64_t P9N2_C_23_CTRL = 0x37010A85ull;
+
+static const uint64_t P9N2_EX_0_L2_CTRL = 0x20010A85ull;
+//DUPS: 20010A85,
+static const uint64_t P9N2_EX_10_L2_CTRL = 0x34010A85ull;
+//DUPS: 34010A85,
+static const uint64_t P9N2_EX_11_L2_CTRL = 0x36010A85ull;
+//DUPS: 36010A85,
+static const uint64_t P9N2_EX_1_L2_CTRL = 0x22010A85ull;
+//DUPS: 22010A85,
+static const uint64_t P9N2_EX_2_L2_CTRL = 0x24010A85ull;
+//DUPS: 24010A85,
+static const uint64_t P9N2_EX_3_L2_CTRL = 0x26010A85ull;
+//DUPS: 26010A85,
+static const uint64_t P9N2_EX_4_L2_CTRL = 0x28010A85ull;
+//DUPS: 28010A85,
+static const uint64_t P9N2_EX_5_L2_CTRL = 0x2B010A85ull;
+//DUPS: 2A010A85,
+static const uint64_t P9N2_EX_6_L2_CTRL = 0x2D010A85ull;
+//DUPS: 2C010A85,
+static const uint64_t P9N2_EX_7_L2_CTRL = 0x2F010A85ull;
+//DUPS: 2E010A85,
+static const uint64_t P9N2_EX_8_L2_CTRL = 0x30010A85ull;
+//DUPS: 30010A85,
+static const uint64_t P9N2_EX_9_L2_CTRL = 0x32010A85ull;
+//DUPS: 32010A85,
+static const uint64_t P9N2_EX_L2_CTRL = 0x20010A85ull;
+//DUPS: 20010A85,
+
+static const uint64_t P9N2_C_CTRL_ATOMIC_LOCK_REG = 0x200003FFull;
+
+static const uint64_t P9N2_C_0_CTRL_ATOMIC_LOCK_REG = 0x200003FFull;
+
+static const uint64_t P9N2_C_1_CTRL_ATOMIC_LOCK_REG = 0x210003FFull;
+
+static const uint64_t P9N2_C_2_CTRL_ATOMIC_LOCK_REG = 0x220003FFull;
+
+static const uint64_t P9N2_C_3_CTRL_ATOMIC_LOCK_REG = 0x230003FFull;
+
+static const uint64_t P9N2_C_4_CTRL_ATOMIC_LOCK_REG = 0x240003FFull;
+
+static const uint64_t P9N2_C_5_CTRL_ATOMIC_LOCK_REG = 0x250003FFull;
+
+static const uint64_t P9N2_C_6_CTRL_ATOMIC_LOCK_REG = 0x260003FFull;
+
+static const uint64_t P9N2_C_7_CTRL_ATOMIC_LOCK_REG = 0x270003FFull;
+
+static const uint64_t P9N2_C_8_CTRL_ATOMIC_LOCK_REG = 0x280003FFull;
+
+static const uint64_t P9N2_C_9_CTRL_ATOMIC_LOCK_REG = 0x290003FFull;
+
+static const uint64_t P9N2_C_10_CTRL_ATOMIC_LOCK_REG = 0x2A0003FFull;
+
+static const uint64_t P9N2_C_11_CTRL_ATOMIC_LOCK_REG = 0x2B0003FFull;
+
+static const uint64_t P9N2_C_12_CTRL_ATOMIC_LOCK_REG = 0x2C0003FFull;
+
+static const uint64_t P9N2_C_13_CTRL_ATOMIC_LOCK_REG = 0x2D0003FFull;
+
+static const uint64_t P9N2_C_14_CTRL_ATOMIC_LOCK_REG = 0x2E0003FFull;
+
+static const uint64_t P9N2_C_15_CTRL_ATOMIC_LOCK_REG = 0x2F0003FFull;
+
+static const uint64_t P9N2_C_16_CTRL_ATOMIC_LOCK_REG = 0x300003FFull;
+
+static const uint64_t P9N2_C_17_CTRL_ATOMIC_LOCK_REG = 0x310003FFull;
+
+static const uint64_t P9N2_C_18_CTRL_ATOMIC_LOCK_REG = 0x320003FFull;
+
+static const uint64_t P9N2_C_19_CTRL_ATOMIC_LOCK_REG = 0x330003FFull;
+
+static const uint64_t P9N2_C_20_CTRL_ATOMIC_LOCK_REG = 0x340003FFull;
+
+static const uint64_t P9N2_C_21_CTRL_ATOMIC_LOCK_REG = 0x350003FFull;
+
+static const uint64_t P9N2_C_22_CTRL_ATOMIC_LOCK_REG = 0x360003FFull;
+
+static const uint64_t P9N2_C_23_CTRL_ATOMIC_LOCK_REG = 0x370003FFull;
+
+static const uint64_t P9N2_EQ_CTRL_ATOMIC_LOCK_REG = 0x100003FFull;
+
+static const uint64_t P9N2_EQ_0_CTRL_ATOMIC_LOCK_REG = 0x100003FFull;
+
+static const uint64_t P9N2_EQ_1_CTRL_ATOMIC_LOCK_REG = 0x110003FFull;
+
+static const uint64_t P9N2_EQ_2_CTRL_ATOMIC_LOCK_REG = 0x120003FFull;
+
+static const uint64_t P9N2_EQ_3_CTRL_ATOMIC_LOCK_REG = 0x130003FFull;
+
+static const uint64_t P9N2_EQ_4_CTRL_ATOMIC_LOCK_REG = 0x140003FFull;
+
+static const uint64_t P9N2_EQ_5_CTRL_ATOMIC_LOCK_REG = 0x150003FFull;
+
+static const uint64_t P9N2_EX_CTRL_ATOMIC_LOCK_REG = 0x200003FFull;
+//DUPS: 210003FF,
+static const uint64_t P9N2_EX_0_CTRL_ATOMIC_LOCK_REG = 0x200003FFull;
+//DUPS: 210003FF,
+static const uint64_t P9N2_EX_1_CTRL_ATOMIC_LOCK_REG = 0x220003FFull;
+//DUPS: 230003FF,
+static const uint64_t P9N2_EX_2_CTRL_ATOMIC_LOCK_REG = 0x240003FFull;
+//DUPS: 250003FF,
+static const uint64_t P9N2_EX_3_CTRL_ATOMIC_LOCK_REG = 0x260003FFull;
+//DUPS: 270003FF,
+static const uint64_t P9N2_EX_4_CTRL_ATOMIC_LOCK_REG = 0x280003FFull;
+//DUPS: 290003FF,
+static const uint64_t P9N2_EX_5_CTRL_ATOMIC_LOCK_REG = 0x2A0003FFull;
+//DUPS: 2B0003FF,
+static const uint64_t P9N2_EX_6_CTRL_ATOMIC_LOCK_REG = 0x2C0003FFull;
+//DUPS: 2D0003FF,
+static const uint64_t P9N2_EX_7_CTRL_ATOMIC_LOCK_REG = 0x2F0003FFull;
+//DUPS: 2F0003FF,
+static const uint64_t P9N2_EX_8_CTRL_ATOMIC_LOCK_REG = 0x300003FFull;
+//DUPS: 310003FF,
+static const uint64_t P9N2_EX_9_CTRL_ATOMIC_LOCK_REG = 0x320003FFull;
+//DUPS: 330003FF,
+static const uint64_t P9N2_EX_10_CTRL_ATOMIC_LOCK_REG = 0x340003FFull;
+//DUPS: 350003FF,
+static const uint64_t P9N2_EX_11_CTRL_ATOMIC_LOCK_REG = 0x360003FFull;
+//DUPS: 370003FF,
+
+static const uint64_t P9N2_C_CTRL_PROTECT_MODE_REG = 0x200003FEull;
+
+static const uint64_t P9N2_C_0_CTRL_PROTECT_MODE_REG = 0x200003FEull;
+
+static const uint64_t P9N2_C_1_CTRL_PROTECT_MODE_REG = 0x210003FEull;
+
+static const uint64_t P9N2_C_2_CTRL_PROTECT_MODE_REG = 0x220003FEull;
+
+static const uint64_t P9N2_C_3_CTRL_PROTECT_MODE_REG = 0x230003FEull;
+
+static const uint64_t P9N2_C_4_CTRL_PROTECT_MODE_REG = 0x240003FEull;
+
+static const uint64_t P9N2_C_5_CTRL_PROTECT_MODE_REG = 0x250003FEull;
+
+static const uint64_t P9N2_C_6_CTRL_PROTECT_MODE_REG = 0x260003FEull;
+
+static const uint64_t P9N2_C_7_CTRL_PROTECT_MODE_REG = 0x270003FEull;
+
+static const uint64_t P9N2_C_8_CTRL_PROTECT_MODE_REG = 0x280003FEull;
+
+static const uint64_t P9N2_C_9_CTRL_PROTECT_MODE_REG = 0x290003FEull;
+
+static const uint64_t P9N2_C_10_CTRL_PROTECT_MODE_REG = 0x2A0003FEull;
+
+static const uint64_t P9N2_C_11_CTRL_PROTECT_MODE_REG = 0x2B0003FEull;
+
+static const uint64_t P9N2_C_12_CTRL_PROTECT_MODE_REG = 0x2C0003FEull;
+
+static const uint64_t P9N2_C_13_CTRL_PROTECT_MODE_REG = 0x2D0003FEull;
+
+static const uint64_t P9N2_C_14_CTRL_PROTECT_MODE_REG = 0x2E0003FEull;
+
+static const uint64_t P9N2_C_15_CTRL_PROTECT_MODE_REG = 0x2F0003FEull;
+
+static const uint64_t P9N2_C_16_CTRL_PROTECT_MODE_REG = 0x300003FEull;
+
+static const uint64_t P9N2_C_17_CTRL_PROTECT_MODE_REG = 0x310003FEull;
+
+static const uint64_t P9N2_C_18_CTRL_PROTECT_MODE_REG = 0x320003FEull;
+
+static const uint64_t P9N2_C_19_CTRL_PROTECT_MODE_REG = 0x330003FEull;
+
+static const uint64_t P9N2_C_20_CTRL_PROTECT_MODE_REG = 0x340003FEull;
+
+static const uint64_t P9N2_C_21_CTRL_PROTECT_MODE_REG = 0x350003FEull;
+
+static const uint64_t P9N2_C_22_CTRL_PROTECT_MODE_REG = 0x360003FEull;
+
+static const uint64_t P9N2_C_23_CTRL_PROTECT_MODE_REG = 0x370003FEull;
+
+static const uint64_t P9N2_EQ_CTRL_PROTECT_MODE_REG = 0x100003FEull;
+
+static const uint64_t P9N2_EQ_0_CTRL_PROTECT_MODE_REG = 0x100003FEull;
+
+static const uint64_t P9N2_EQ_1_CTRL_PROTECT_MODE_REG = 0x110003FEull;
+
+static const uint64_t P9N2_EQ_2_CTRL_PROTECT_MODE_REG = 0x120003FEull;
+
+static const uint64_t P9N2_EQ_3_CTRL_PROTECT_MODE_REG = 0x130003FEull;
+
+static const uint64_t P9N2_EQ_4_CTRL_PROTECT_MODE_REG = 0x140003FEull;
+
+static const uint64_t P9N2_EQ_5_CTRL_PROTECT_MODE_REG = 0x150003FEull;
+
+static const uint64_t P9N2_EX_CTRL_PROTECT_MODE_REG = 0x200003FEull;
+//DUPS: 210003FE,
+static const uint64_t P9N2_EX_0_CTRL_PROTECT_MODE_REG = 0x200003FEull;
+//DUPS: 210003FE,
+static const uint64_t P9N2_EX_1_CTRL_PROTECT_MODE_REG = 0x220003FEull;
+//DUPS: 230003FE,
+static const uint64_t P9N2_EX_2_CTRL_PROTECT_MODE_REG = 0x240003FEull;
+//DUPS: 250003FE,
+static const uint64_t P9N2_EX_3_CTRL_PROTECT_MODE_REG = 0x260003FEull;
+//DUPS: 270003FE,
+static const uint64_t P9N2_EX_4_CTRL_PROTECT_MODE_REG = 0x280003FEull;
+//DUPS: 290003FE,
+static const uint64_t P9N2_EX_5_CTRL_PROTECT_MODE_REG = 0x2A0003FEull;
+//DUPS: 2B0003FE,
+static const uint64_t P9N2_EX_6_CTRL_PROTECT_MODE_REG = 0x2C0003FEull;
+//DUPS: 2D0003FE,
+static const uint64_t P9N2_EX_7_CTRL_PROTECT_MODE_REG = 0x2F0003FEull;
+//DUPS: 2F0003FE,
+static const uint64_t P9N2_EX_8_CTRL_PROTECT_MODE_REG = 0x300003FEull;
+//DUPS: 310003FE,
+static const uint64_t P9N2_EX_9_CTRL_PROTECT_MODE_REG = 0x320003FEull;
+//DUPS: 330003FE,
+static const uint64_t P9N2_EX_10_CTRL_PROTECT_MODE_REG = 0x340003FEull;
+//DUPS: 350003FE,
+static const uint64_t P9N2_EX_11_CTRL_PROTECT_MODE_REG = 0x360003FEull;
+//DUPS: 370003FE,
+
+static const uint64_t P9N2_C_DBG_CBS_CC = 0x20030013ull;
+
+static const uint64_t P9N2_C_0_DBG_CBS_CC = 0x20030013ull;
+
+static const uint64_t P9N2_C_1_DBG_CBS_CC = 0x21030013ull;
+
+static const uint64_t P9N2_C_2_DBG_CBS_CC = 0x22030013ull;
+
+static const uint64_t P9N2_C_3_DBG_CBS_CC = 0x23030013ull;
+
+static const uint64_t P9N2_C_4_DBG_CBS_CC = 0x24030013ull;
+
+static const uint64_t P9N2_C_5_DBG_CBS_CC = 0x25030013ull;
+
+static const uint64_t P9N2_C_6_DBG_CBS_CC = 0x26030013ull;
+
+static const uint64_t P9N2_C_7_DBG_CBS_CC = 0x27030013ull;
+
+static const uint64_t P9N2_C_8_DBG_CBS_CC = 0x28030013ull;
+
+static const uint64_t P9N2_C_9_DBG_CBS_CC = 0x29030013ull;
+
+static const uint64_t P9N2_C_10_DBG_CBS_CC = 0x2A030013ull;
+
+static const uint64_t P9N2_C_11_DBG_CBS_CC = 0x2B030013ull;
+
+static const uint64_t P9N2_C_12_DBG_CBS_CC = 0x2C030013ull;
+
+static const uint64_t P9N2_C_13_DBG_CBS_CC = 0x2D030013ull;
+
+static const uint64_t P9N2_C_14_DBG_CBS_CC = 0x2E030013ull;
+
+static const uint64_t P9N2_C_15_DBG_CBS_CC = 0x2F030013ull;
+
+static const uint64_t P9N2_C_16_DBG_CBS_CC = 0x30030013ull;
+
+static const uint64_t P9N2_C_17_DBG_CBS_CC = 0x31030013ull;
+
+static const uint64_t P9N2_C_18_DBG_CBS_CC = 0x32030013ull;
+
+static const uint64_t P9N2_C_19_DBG_CBS_CC = 0x33030013ull;
+
+static const uint64_t P9N2_C_20_DBG_CBS_CC = 0x34030013ull;
+
+static const uint64_t P9N2_C_21_DBG_CBS_CC = 0x35030013ull;
+
+static const uint64_t P9N2_C_22_DBG_CBS_CC = 0x36030013ull;
+
+static const uint64_t P9N2_C_23_DBG_CBS_CC = 0x37030013ull;
+
+static const uint64_t P9N2_EQ_DBG_CBS_CC = 0x10030013ull;
+
+static const uint64_t P9N2_EQ_0_DBG_CBS_CC = 0x10030013ull;
+
+static const uint64_t P9N2_EQ_1_DBG_CBS_CC = 0x11030013ull;
+
+static const uint64_t P9N2_EQ_2_DBG_CBS_CC = 0x12030013ull;
+
+static const uint64_t P9N2_EQ_3_DBG_CBS_CC = 0x13030013ull;
+
+static const uint64_t P9N2_EQ_4_DBG_CBS_CC = 0x14030013ull;
+
+static const uint64_t P9N2_EQ_5_DBG_CBS_CC = 0x15030013ull;
+
+static const uint64_t P9N2_EX_DBG_CBS_CC = 0x20030013ull;
+//DUPS: 21030013,
+static const uint64_t P9N2_EX_0_DBG_CBS_CC = 0x20030013ull;
+//DUPS: 21030013,
+static const uint64_t P9N2_EX_1_DBG_CBS_CC = 0x22030013ull;
+//DUPS: 23030013,
+static const uint64_t P9N2_EX_2_DBG_CBS_CC = 0x24030013ull;
+//DUPS: 25030013,
+static const uint64_t P9N2_EX_3_DBG_CBS_CC = 0x26030013ull;
+//DUPS: 27030013,
+static const uint64_t P9N2_EX_4_DBG_CBS_CC = 0x28030013ull;
+//DUPS: 29030013,
+static const uint64_t P9N2_EX_5_DBG_CBS_CC = 0x2A030013ull;
+//DUPS: 2B030013,
+static const uint64_t P9N2_EX_6_DBG_CBS_CC = 0x2C030013ull;
+//DUPS: 2D030013,
+static const uint64_t P9N2_EX_7_DBG_CBS_CC = 0x2F030013ull;
+//DUPS: 2F030013,
+static const uint64_t P9N2_EX_8_DBG_CBS_CC = 0x30030013ull;
+//DUPS: 31030013,
+static const uint64_t P9N2_EX_9_DBG_CBS_CC = 0x32030013ull;
+//DUPS: 33030013,
+static const uint64_t P9N2_EX_10_DBG_CBS_CC = 0x34030013ull;
+//DUPS: 35030013,
+static const uint64_t P9N2_EX_11_DBG_CBS_CC = 0x36030013ull;
+//DUPS: 37030013,
+
+static const uint64_t P9N2_C_DBG_INST1_COND_REG_1 = 0x200107C1ull;
+
+static const uint64_t P9N2_C_0_DBG_INST1_COND_REG_1 = 0x200107C1ull;
+
+static const uint64_t P9N2_C_1_DBG_INST1_COND_REG_1 = 0x210107C1ull;
+
+static const uint64_t P9N2_C_2_DBG_INST1_COND_REG_1 = 0x220107C1ull;
+
+static const uint64_t P9N2_C_3_DBG_INST1_COND_REG_1 = 0x230107C1ull;
+
+static const uint64_t P9N2_C_4_DBG_INST1_COND_REG_1 = 0x240107C1ull;
+
+static const uint64_t P9N2_C_5_DBG_INST1_COND_REG_1 = 0x250107C1ull;
+
+static const uint64_t P9N2_C_6_DBG_INST1_COND_REG_1 = 0x260107C1ull;
+
+static const uint64_t P9N2_C_7_DBG_INST1_COND_REG_1 = 0x270107C1ull;
+
+static const uint64_t P9N2_C_8_DBG_INST1_COND_REG_1 = 0x280107C1ull;
+
+static const uint64_t P9N2_C_9_DBG_INST1_COND_REG_1 = 0x290107C1ull;
+
+static const uint64_t P9N2_C_10_DBG_INST1_COND_REG_1 = 0x2A0107C1ull;
+
+static const uint64_t P9N2_C_11_DBG_INST1_COND_REG_1 = 0x2B0107C1ull;
+
+static const uint64_t P9N2_C_12_DBG_INST1_COND_REG_1 = 0x2C0107C1ull;
+
+static const uint64_t P9N2_C_13_DBG_INST1_COND_REG_1 = 0x2D0107C1ull;
+
+static const uint64_t P9N2_C_14_DBG_INST1_COND_REG_1 = 0x2E0107C1ull;
+
+static const uint64_t P9N2_C_15_DBG_INST1_COND_REG_1 = 0x2F0107C1ull;
+
+static const uint64_t P9N2_C_16_DBG_INST1_COND_REG_1 = 0x300107C1ull;
+
+static const uint64_t P9N2_C_17_DBG_INST1_COND_REG_1 = 0x310107C1ull;
+
+static const uint64_t P9N2_C_18_DBG_INST1_COND_REG_1 = 0x320107C1ull;
+
+static const uint64_t P9N2_C_19_DBG_INST1_COND_REG_1 = 0x330107C1ull;
+
+static const uint64_t P9N2_C_20_DBG_INST1_COND_REG_1 = 0x340107C1ull;
+
+static const uint64_t P9N2_C_21_DBG_INST1_COND_REG_1 = 0x350107C1ull;
+
+static const uint64_t P9N2_C_22_DBG_INST1_COND_REG_1 = 0x360107C1ull;
+
+static const uint64_t P9N2_C_23_DBG_INST1_COND_REG_1 = 0x370107C1ull;
+
+static const uint64_t P9N2_EQ_DBG_INST1_COND_REG_1 = 0x100107C1ull;
+
+static const uint64_t P9N2_EQ_0_DBG_INST1_COND_REG_1 = 0x100107C1ull;
+
+static const uint64_t P9N2_EQ_1_DBG_INST1_COND_REG_1 = 0x110107C1ull;
+
+static const uint64_t P9N2_EQ_2_DBG_INST1_COND_REG_1 = 0x120107C1ull;
+
+static const uint64_t P9N2_EQ_3_DBG_INST1_COND_REG_1 = 0x130107C1ull;
+
+static const uint64_t P9N2_EQ_4_DBG_INST1_COND_REG_1 = 0x140107C1ull;
+
+static const uint64_t P9N2_EQ_5_DBG_INST1_COND_REG_1 = 0x150107C1ull;
+
+static const uint64_t P9N2_EX_DBG_INST1_COND_REG_1 = 0x200107C1ull;
+//DUPS: 210107C1,
+static const uint64_t P9N2_EX_0_DBG_INST1_COND_REG_1 = 0x200107C1ull;
+//DUPS: 210107C1,
+static const uint64_t P9N2_EX_1_DBG_INST1_COND_REG_1 = 0x220107C1ull;
+//DUPS: 230107C1,
+static const uint64_t P9N2_EX_2_DBG_INST1_COND_REG_1 = 0x240107C1ull;
+//DUPS: 250107C1,
+static const uint64_t P9N2_EX_3_DBG_INST1_COND_REG_1 = 0x260107C1ull;
+//DUPS: 270107C1,
+static const uint64_t P9N2_EX_4_DBG_INST1_COND_REG_1 = 0x280107C1ull;
+//DUPS: 290107C1,
+static const uint64_t P9N2_EX_5_DBG_INST1_COND_REG_1 = 0x2A0107C1ull;
+//DUPS: 2B0107C1,
+static const uint64_t P9N2_EX_6_DBG_INST1_COND_REG_1 = 0x2C0107C1ull;
+//DUPS: 2D0107C1,
+static const uint64_t P9N2_EX_7_DBG_INST1_COND_REG_1 = 0x2F0107C1ull;
+//DUPS: 2F0107C1,
+static const uint64_t P9N2_EX_8_DBG_INST1_COND_REG_1 = 0x300107C1ull;
+//DUPS: 310107C1,
+static const uint64_t P9N2_EX_9_DBG_INST1_COND_REG_1 = 0x320107C1ull;
+//DUPS: 330107C1,
+static const uint64_t P9N2_EX_10_DBG_INST1_COND_REG_1 = 0x340107C1ull;
+//DUPS: 350107C1,
+static const uint64_t P9N2_EX_11_DBG_INST1_COND_REG_1 = 0x360107C1ull;
+//DUPS: 370107C1,
+
+static const uint64_t P9N2_C_DBG_INST1_COND_REG_2 = 0x200107C2ull;
+
+static const uint64_t P9N2_C_0_DBG_INST1_COND_REG_2 = 0x200107C2ull;
+
+static const uint64_t P9N2_C_1_DBG_INST1_COND_REG_2 = 0x210107C2ull;
+
+static const uint64_t P9N2_C_2_DBG_INST1_COND_REG_2 = 0x220107C2ull;
+
+static const uint64_t P9N2_C_3_DBG_INST1_COND_REG_2 = 0x230107C2ull;
+
+static const uint64_t P9N2_C_4_DBG_INST1_COND_REG_2 = 0x240107C2ull;
+
+static const uint64_t P9N2_C_5_DBG_INST1_COND_REG_2 = 0x250107C2ull;
+
+static const uint64_t P9N2_C_6_DBG_INST1_COND_REG_2 = 0x260107C2ull;
+
+static const uint64_t P9N2_C_7_DBG_INST1_COND_REG_2 = 0x270107C2ull;
+
+static const uint64_t P9N2_C_8_DBG_INST1_COND_REG_2 = 0x280107C2ull;
+
+static const uint64_t P9N2_C_9_DBG_INST1_COND_REG_2 = 0x290107C2ull;
+
+static const uint64_t P9N2_C_10_DBG_INST1_COND_REG_2 = 0x2A0107C2ull;
+
+static const uint64_t P9N2_C_11_DBG_INST1_COND_REG_2 = 0x2B0107C2ull;
+
+static const uint64_t P9N2_C_12_DBG_INST1_COND_REG_2 = 0x2C0107C2ull;
+
+static const uint64_t P9N2_C_13_DBG_INST1_COND_REG_2 = 0x2D0107C2ull;
+
+static const uint64_t P9N2_C_14_DBG_INST1_COND_REG_2 = 0x2E0107C2ull;
+
+static const uint64_t P9N2_C_15_DBG_INST1_COND_REG_2 = 0x2F0107C2ull;
+
+static const uint64_t P9N2_C_16_DBG_INST1_COND_REG_2 = 0x300107C2ull;
+
+static const uint64_t P9N2_C_17_DBG_INST1_COND_REG_2 = 0x310107C2ull;
+
+static const uint64_t P9N2_C_18_DBG_INST1_COND_REG_2 = 0x320107C2ull;
+
+static const uint64_t P9N2_C_19_DBG_INST1_COND_REG_2 = 0x330107C2ull;
+
+static const uint64_t P9N2_C_20_DBG_INST1_COND_REG_2 = 0x340107C2ull;
+
+static const uint64_t P9N2_C_21_DBG_INST1_COND_REG_2 = 0x350107C2ull;
+
+static const uint64_t P9N2_C_22_DBG_INST1_COND_REG_2 = 0x360107C2ull;
+
+static const uint64_t P9N2_C_23_DBG_INST1_COND_REG_2 = 0x370107C2ull;
+
+static const uint64_t P9N2_EQ_DBG_INST1_COND_REG_2 = 0x100107C2ull;
+
+static const uint64_t P9N2_EQ_0_DBG_INST1_COND_REG_2 = 0x100107C2ull;
+
+static const uint64_t P9N2_EQ_1_DBG_INST1_COND_REG_2 = 0x110107C2ull;
+
+static const uint64_t P9N2_EQ_2_DBG_INST1_COND_REG_2 = 0x120107C2ull;
+
+static const uint64_t P9N2_EQ_3_DBG_INST1_COND_REG_2 = 0x130107C2ull;
+
+static const uint64_t P9N2_EQ_4_DBG_INST1_COND_REG_2 = 0x140107C2ull;
+
+static const uint64_t P9N2_EQ_5_DBG_INST1_COND_REG_2 = 0x150107C2ull;
+
+static const uint64_t P9N2_EX_DBG_INST1_COND_REG_2 = 0x200107C2ull;
+//DUPS: 210107C2,
+static const uint64_t P9N2_EX_0_DBG_INST1_COND_REG_2 = 0x200107C2ull;
+//DUPS: 210107C2,
+static const uint64_t P9N2_EX_1_DBG_INST1_COND_REG_2 = 0x220107C2ull;
+//DUPS: 230107C2,
+static const uint64_t P9N2_EX_2_DBG_INST1_COND_REG_2 = 0x240107C2ull;
+//DUPS: 250107C2,
+static const uint64_t P9N2_EX_3_DBG_INST1_COND_REG_2 = 0x260107C2ull;
+//DUPS: 270107C2,
+static const uint64_t P9N2_EX_4_DBG_INST1_COND_REG_2 = 0x280107C2ull;
+//DUPS: 290107C2,
+static const uint64_t P9N2_EX_5_DBG_INST1_COND_REG_2 = 0x2A0107C2ull;
+//DUPS: 2B0107C2,
+static const uint64_t P9N2_EX_6_DBG_INST1_COND_REG_2 = 0x2C0107C2ull;
+//DUPS: 2D0107C2,
+static const uint64_t P9N2_EX_7_DBG_INST1_COND_REG_2 = 0x2F0107C2ull;
+//DUPS: 2F0107C2,
+static const uint64_t P9N2_EX_8_DBG_INST1_COND_REG_2 = 0x300107C2ull;
+//DUPS: 310107C2,
+static const uint64_t P9N2_EX_9_DBG_INST1_COND_REG_2 = 0x320107C2ull;
+//DUPS: 330107C2,
+static const uint64_t P9N2_EX_10_DBG_INST1_COND_REG_2 = 0x340107C2ull;
+//DUPS: 350107C2,
+static const uint64_t P9N2_EX_11_DBG_INST1_COND_REG_2 = 0x360107C2ull;
+//DUPS: 370107C2,
+
+static const uint64_t P9N2_C_DBG_INST1_COND_REG_3 = 0x200107C3ull;
+
+static const uint64_t P9N2_C_0_DBG_INST1_COND_REG_3 = 0x200107C3ull;
+
+static const uint64_t P9N2_C_1_DBG_INST1_COND_REG_3 = 0x210107C3ull;
+
+static const uint64_t P9N2_C_2_DBG_INST1_COND_REG_3 = 0x220107C3ull;
+
+static const uint64_t P9N2_C_3_DBG_INST1_COND_REG_3 = 0x230107C3ull;
+
+static const uint64_t P9N2_C_4_DBG_INST1_COND_REG_3 = 0x240107C3ull;
+
+static const uint64_t P9N2_C_5_DBG_INST1_COND_REG_3 = 0x250107C3ull;
+
+static const uint64_t P9N2_C_6_DBG_INST1_COND_REG_3 = 0x260107C3ull;
+
+static const uint64_t P9N2_C_7_DBG_INST1_COND_REG_3 = 0x270107C3ull;
+
+static const uint64_t P9N2_C_8_DBG_INST1_COND_REG_3 = 0x280107C3ull;
+
+static const uint64_t P9N2_C_9_DBG_INST1_COND_REG_3 = 0x290107C3ull;
+
+static const uint64_t P9N2_C_10_DBG_INST1_COND_REG_3 = 0x2A0107C3ull;
+
+static const uint64_t P9N2_C_11_DBG_INST1_COND_REG_3 = 0x2B0107C3ull;
+
+static const uint64_t P9N2_C_12_DBG_INST1_COND_REG_3 = 0x2C0107C3ull;
+
+static const uint64_t P9N2_C_13_DBG_INST1_COND_REG_3 = 0x2D0107C3ull;
+
+static const uint64_t P9N2_C_14_DBG_INST1_COND_REG_3 = 0x2E0107C3ull;
+
+static const uint64_t P9N2_C_15_DBG_INST1_COND_REG_3 = 0x2F0107C3ull;
+
+static const uint64_t P9N2_C_16_DBG_INST1_COND_REG_3 = 0x300107C3ull;
+
+static const uint64_t P9N2_C_17_DBG_INST1_COND_REG_3 = 0x310107C3ull;
+
+static const uint64_t P9N2_C_18_DBG_INST1_COND_REG_3 = 0x320107C3ull;
+
+static const uint64_t P9N2_C_19_DBG_INST1_COND_REG_3 = 0x330107C3ull;
+
+static const uint64_t P9N2_C_20_DBG_INST1_COND_REG_3 = 0x340107C3ull;
+
+static const uint64_t P9N2_C_21_DBG_INST1_COND_REG_3 = 0x350107C3ull;
+
+static const uint64_t P9N2_C_22_DBG_INST1_COND_REG_3 = 0x360107C3ull;
+
+static const uint64_t P9N2_C_23_DBG_INST1_COND_REG_3 = 0x370107C3ull;
+
+static const uint64_t P9N2_EQ_DBG_INST1_COND_REG_3 = 0x100107C3ull;
+
+static const uint64_t P9N2_EQ_0_DBG_INST1_COND_REG_3 = 0x100107C3ull;
+
+static const uint64_t P9N2_EQ_1_DBG_INST1_COND_REG_3 = 0x110107C3ull;
+
+static const uint64_t P9N2_EQ_2_DBG_INST1_COND_REG_3 = 0x120107C3ull;
+
+static const uint64_t P9N2_EQ_3_DBG_INST1_COND_REG_3 = 0x130107C3ull;
+
+static const uint64_t P9N2_EQ_4_DBG_INST1_COND_REG_3 = 0x140107C3ull;
+
+static const uint64_t P9N2_EQ_5_DBG_INST1_COND_REG_3 = 0x150107C3ull;
+
+static const uint64_t P9N2_EX_DBG_INST1_COND_REG_3 = 0x200107C3ull;
+//DUPS: 210107C3,
+static const uint64_t P9N2_EX_0_DBG_INST1_COND_REG_3 = 0x200107C3ull;
+//DUPS: 210107C3,
+static const uint64_t P9N2_EX_1_DBG_INST1_COND_REG_3 = 0x220107C3ull;
+//DUPS: 230107C3,
+static const uint64_t P9N2_EX_2_DBG_INST1_COND_REG_3 = 0x240107C3ull;
+//DUPS: 250107C3,
+static const uint64_t P9N2_EX_3_DBG_INST1_COND_REG_3 = 0x260107C3ull;
+//DUPS: 270107C3,
+static const uint64_t P9N2_EX_4_DBG_INST1_COND_REG_3 = 0x280107C3ull;
+//DUPS: 290107C3,
+static const uint64_t P9N2_EX_5_DBG_INST1_COND_REG_3 = 0x2A0107C3ull;
+//DUPS: 2B0107C3,
+static const uint64_t P9N2_EX_6_DBG_INST1_COND_REG_3 = 0x2C0107C3ull;
+//DUPS: 2D0107C3,
+static const uint64_t P9N2_EX_7_DBG_INST1_COND_REG_3 = 0x2F0107C3ull;
+//DUPS: 2F0107C3,
+static const uint64_t P9N2_EX_8_DBG_INST1_COND_REG_3 = 0x300107C3ull;
+//DUPS: 310107C3,
+static const uint64_t P9N2_EX_9_DBG_INST1_COND_REG_3 = 0x320107C3ull;
+//DUPS: 330107C3,
+static const uint64_t P9N2_EX_10_DBG_INST1_COND_REG_3 = 0x340107C3ull;
+//DUPS: 350107C3,
+static const uint64_t P9N2_EX_11_DBG_INST1_COND_REG_3 = 0x360107C3ull;
+//DUPS: 370107C3,
+
+static const uint64_t P9N2_C_DBG_INST2_COND_REG_1 = 0x200107C4ull;
+
+static const uint64_t P9N2_C_0_DBG_INST2_COND_REG_1 = 0x200107C4ull;
+
+static const uint64_t P9N2_C_1_DBG_INST2_COND_REG_1 = 0x210107C4ull;
+
+static const uint64_t P9N2_C_2_DBG_INST2_COND_REG_1 = 0x220107C4ull;
+
+static const uint64_t P9N2_C_3_DBG_INST2_COND_REG_1 = 0x230107C4ull;
+
+static const uint64_t P9N2_C_4_DBG_INST2_COND_REG_1 = 0x240107C4ull;
+
+static const uint64_t P9N2_C_5_DBG_INST2_COND_REG_1 = 0x250107C4ull;
+
+static const uint64_t P9N2_C_6_DBG_INST2_COND_REG_1 = 0x260107C4ull;
+
+static const uint64_t P9N2_C_7_DBG_INST2_COND_REG_1 = 0x270107C4ull;
+
+static const uint64_t P9N2_C_8_DBG_INST2_COND_REG_1 = 0x280107C4ull;
+
+static const uint64_t P9N2_C_9_DBG_INST2_COND_REG_1 = 0x290107C4ull;
+
+static const uint64_t P9N2_C_10_DBG_INST2_COND_REG_1 = 0x2A0107C4ull;
+
+static const uint64_t P9N2_C_11_DBG_INST2_COND_REG_1 = 0x2B0107C4ull;
+
+static const uint64_t P9N2_C_12_DBG_INST2_COND_REG_1 = 0x2C0107C4ull;
+
+static const uint64_t P9N2_C_13_DBG_INST2_COND_REG_1 = 0x2D0107C4ull;
+
+static const uint64_t P9N2_C_14_DBG_INST2_COND_REG_1 = 0x2E0107C4ull;
+
+static const uint64_t P9N2_C_15_DBG_INST2_COND_REG_1 = 0x2F0107C4ull;
+
+static const uint64_t P9N2_C_16_DBG_INST2_COND_REG_1 = 0x300107C4ull;
+
+static const uint64_t P9N2_C_17_DBG_INST2_COND_REG_1 = 0x310107C4ull;
+
+static const uint64_t P9N2_C_18_DBG_INST2_COND_REG_1 = 0x320107C4ull;
+
+static const uint64_t P9N2_C_19_DBG_INST2_COND_REG_1 = 0x330107C4ull;
+
+static const uint64_t P9N2_C_20_DBG_INST2_COND_REG_1 = 0x340107C4ull;
+
+static const uint64_t P9N2_C_21_DBG_INST2_COND_REG_1 = 0x350107C4ull;
+
+static const uint64_t P9N2_C_22_DBG_INST2_COND_REG_1 = 0x360107C4ull;
+
+static const uint64_t P9N2_C_23_DBG_INST2_COND_REG_1 = 0x370107C4ull;
+
+static const uint64_t P9N2_EQ_DBG_INST2_COND_REG_1 = 0x100107C4ull;
+
+static const uint64_t P9N2_EQ_0_DBG_INST2_COND_REG_1 = 0x100107C4ull;
+
+static const uint64_t P9N2_EQ_1_DBG_INST2_COND_REG_1 = 0x110107C4ull;
+
+static const uint64_t P9N2_EQ_2_DBG_INST2_COND_REG_1 = 0x120107C4ull;
+
+static const uint64_t P9N2_EQ_3_DBG_INST2_COND_REG_1 = 0x130107C4ull;
+
+static const uint64_t P9N2_EQ_4_DBG_INST2_COND_REG_1 = 0x140107C4ull;
+
+static const uint64_t P9N2_EQ_5_DBG_INST2_COND_REG_1 = 0x150107C4ull;
+
+static const uint64_t P9N2_EX_DBG_INST2_COND_REG_1 = 0x200107C4ull;
+//DUPS: 210107C4,
+static const uint64_t P9N2_EX_0_DBG_INST2_COND_REG_1 = 0x200107C4ull;
+//DUPS: 210107C4,
+static const uint64_t P9N2_EX_1_DBG_INST2_COND_REG_1 = 0x220107C4ull;
+//DUPS: 230107C4,
+static const uint64_t P9N2_EX_2_DBG_INST2_COND_REG_1 = 0x240107C4ull;
+//DUPS: 250107C4,
+static const uint64_t P9N2_EX_3_DBG_INST2_COND_REG_1 = 0x260107C4ull;
+//DUPS: 270107C4,
+static const uint64_t P9N2_EX_4_DBG_INST2_COND_REG_1 = 0x280107C4ull;
+//DUPS: 290107C4,
+static const uint64_t P9N2_EX_5_DBG_INST2_COND_REG_1 = 0x2A0107C4ull;
+//DUPS: 2B0107C4,
+static const uint64_t P9N2_EX_6_DBG_INST2_COND_REG_1 = 0x2C0107C4ull;
+//DUPS: 2D0107C4,
+static const uint64_t P9N2_EX_7_DBG_INST2_COND_REG_1 = 0x2F0107C4ull;
+//DUPS: 2F0107C4,
+static const uint64_t P9N2_EX_8_DBG_INST2_COND_REG_1 = 0x300107C4ull;
+//DUPS: 310107C4,
+static const uint64_t P9N2_EX_9_DBG_INST2_COND_REG_1 = 0x320107C4ull;
+//DUPS: 330107C4,
+static const uint64_t P9N2_EX_10_DBG_INST2_COND_REG_1 = 0x340107C4ull;
+//DUPS: 350107C4,
+static const uint64_t P9N2_EX_11_DBG_INST2_COND_REG_1 = 0x360107C4ull;
+//DUPS: 370107C4,
+
+static const uint64_t P9N2_C_DBG_INST2_COND_REG_2 = 0x200107C5ull;
+
+static const uint64_t P9N2_C_0_DBG_INST2_COND_REG_2 = 0x200107C5ull;
+
+static const uint64_t P9N2_C_1_DBG_INST2_COND_REG_2 = 0x210107C5ull;
+
+static const uint64_t P9N2_C_2_DBG_INST2_COND_REG_2 = 0x220107C5ull;
+
+static const uint64_t P9N2_C_3_DBG_INST2_COND_REG_2 = 0x230107C5ull;
+
+static const uint64_t P9N2_C_4_DBG_INST2_COND_REG_2 = 0x240107C5ull;
+
+static const uint64_t P9N2_C_5_DBG_INST2_COND_REG_2 = 0x250107C5ull;
+
+static const uint64_t P9N2_C_6_DBG_INST2_COND_REG_2 = 0x260107C5ull;
+
+static const uint64_t P9N2_C_7_DBG_INST2_COND_REG_2 = 0x270107C5ull;
+
+static const uint64_t P9N2_C_8_DBG_INST2_COND_REG_2 = 0x280107C5ull;
+
+static const uint64_t P9N2_C_9_DBG_INST2_COND_REG_2 = 0x290107C5ull;
+
+static const uint64_t P9N2_C_10_DBG_INST2_COND_REG_2 = 0x2A0107C5ull;
+
+static const uint64_t P9N2_C_11_DBG_INST2_COND_REG_2 = 0x2B0107C5ull;
+
+static const uint64_t P9N2_C_12_DBG_INST2_COND_REG_2 = 0x2C0107C5ull;
+
+static const uint64_t P9N2_C_13_DBG_INST2_COND_REG_2 = 0x2D0107C5ull;
+
+static const uint64_t P9N2_C_14_DBG_INST2_COND_REG_2 = 0x2E0107C5ull;
+
+static const uint64_t P9N2_C_15_DBG_INST2_COND_REG_2 = 0x2F0107C5ull;
+
+static const uint64_t P9N2_C_16_DBG_INST2_COND_REG_2 = 0x300107C5ull;
+
+static const uint64_t P9N2_C_17_DBG_INST2_COND_REG_2 = 0x310107C5ull;
+
+static const uint64_t P9N2_C_18_DBG_INST2_COND_REG_2 = 0x320107C5ull;
+
+static const uint64_t P9N2_C_19_DBG_INST2_COND_REG_2 = 0x330107C5ull;
+
+static const uint64_t P9N2_C_20_DBG_INST2_COND_REG_2 = 0x340107C5ull;
+
+static const uint64_t P9N2_C_21_DBG_INST2_COND_REG_2 = 0x350107C5ull;
+
+static const uint64_t P9N2_C_22_DBG_INST2_COND_REG_2 = 0x360107C5ull;
+
+static const uint64_t P9N2_C_23_DBG_INST2_COND_REG_2 = 0x370107C5ull;
+
+static const uint64_t P9N2_EQ_DBG_INST2_COND_REG_2 = 0x100107C5ull;
+
+static const uint64_t P9N2_EQ_0_DBG_INST2_COND_REG_2 = 0x100107C5ull;
+
+static const uint64_t P9N2_EQ_1_DBG_INST2_COND_REG_2 = 0x110107C5ull;
+
+static const uint64_t P9N2_EQ_2_DBG_INST2_COND_REG_2 = 0x120107C5ull;
+
+static const uint64_t P9N2_EQ_3_DBG_INST2_COND_REG_2 = 0x130107C5ull;
+
+static const uint64_t P9N2_EQ_4_DBG_INST2_COND_REG_2 = 0x140107C5ull;
+
+static const uint64_t P9N2_EQ_5_DBG_INST2_COND_REG_2 = 0x150107C5ull;
+
+static const uint64_t P9N2_EX_DBG_INST2_COND_REG_2 = 0x200107C5ull;
+//DUPS: 210107C5,
+static const uint64_t P9N2_EX_0_DBG_INST2_COND_REG_2 = 0x200107C5ull;
+//DUPS: 210107C5,
+static const uint64_t P9N2_EX_1_DBG_INST2_COND_REG_2 = 0x220107C5ull;
+//DUPS: 230107C5,
+static const uint64_t P9N2_EX_2_DBG_INST2_COND_REG_2 = 0x240107C5ull;
+//DUPS: 250107C5,
+static const uint64_t P9N2_EX_3_DBG_INST2_COND_REG_2 = 0x260107C5ull;
+//DUPS: 270107C5,
+static const uint64_t P9N2_EX_4_DBG_INST2_COND_REG_2 = 0x280107C5ull;
+//DUPS: 290107C5,
+static const uint64_t P9N2_EX_5_DBG_INST2_COND_REG_2 = 0x2A0107C5ull;
+//DUPS: 2B0107C5,
+static const uint64_t P9N2_EX_6_DBG_INST2_COND_REG_2 = 0x2C0107C5ull;
+//DUPS: 2D0107C5,
+static const uint64_t P9N2_EX_7_DBG_INST2_COND_REG_2 = 0x2F0107C5ull;
+//DUPS: 2F0107C5,
+static const uint64_t P9N2_EX_8_DBG_INST2_COND_REG_2 = 0x300107C5ull;
+//DUPS: 310107C5,
+static const uint64_t P9N2_EX_9_DBG_INST2_COND_REG_2 = 0x320107C5ull;
+//DUPS: 330107C5,
+static const uint64_t P9N2_EX_10_DBG_INST2_COND_REG_2 = 0x340107C5ull;
+//DUPS: 350107C5,
+static const uint64_t P9N2_EX_11_DBG_INST2_COND_REG_2 = 0x360107C5ull;
+//DUPS: 370107C5,
+
+static const uint64_t P9N2_C_DBG_INST2_COND_REG_3 = 0x200107C6ull;
+
+static const uint64_t P9N2_C_0_DBG_INST2_COND_REG_3 = 0x200107C6ull;
+
+static const uint64_t P9N2_C_1_DBG_INST2_COND_REG_3 = 0x210107C6ull;
+
+static const uint64_t P9N2_C_2_DBG_INST2_COND_REG_3 = 0x220107C6ull;
+
+static const uint64_t P9N2_C_3_DBG_INST2_COND_REG_3 = 0x230107C6ull;
+
+static const uint64_t P9N2_C_4_DBG_INST2_COND_REG_3 = 0x240107C6ull;
+
+static const uint64_t P9N2_C_5_DBG_INST2_COND_REG_3 = 0x250107C6ull;
+
+static const uint64_t P9N2_C_6_DBG_INST2_COND_REG_3 = 0x260107C6ull;
+
+static const uint64_t P9N2_C_7_DBG_INST2_COND_REG_3 = 0x270107C6ull;
+
+static const uint64_t P9N2_C_8_DBG_INST2_COND_REG_3 = 0x280107C6ull;
+
+static const uint64_t P9N2_C_9_DBG_INST2_COND_REG_3 = 0x290107C6ull;
+
+static const uint64_t P9N2_C_10_DBG_INST2_COND_REG_3 = 0x2A0107C6ull;
+
+static const uint64_t P9N2_C_11_DBG_INST2_COND_REG_3 = 0x2B0107C6ull;
+
+static const uint64_t P9N2_C_12_DBG_INST2_COND_REG_3 = 0x2C0107C6ull;
+
+static const uint64_t P9N2_C_13_DBG_INST2_COND_REG_3 = 0x2D0107C6ull;
+
+static const uint64_t P9N2_C_14_DBG_INST2_COND_REG_3 = 0x2E0107C6ull;
+
+static const uint64_t P9N2_C_15_DBG_INST2_COND_REG_3 = 0x2F0107C6ull;
+
+static const uint64_t P9N2_C_16_DBG_INST2_COND_REG_3 = 0x300107C6ull;
+
+static const uint64_t P9N2_C_17_DBG_INST2_COND_REG_3 = 0x310107C6ull;
+
+static const uint64_t P9N2_C_18_DBG_INST2_COND_REG_3 = 0x320107C6ull;
+
+static const uint64_t P9N2_C_19_DBG_INST2_COND_REG_3 = 0x330107C6ull;
+
+static const uint64_t P9N2_C_20_DBG_INST2_COND_REG_3 = 0x340107C6ull;
+
+static const uint64_t P9N2_C_21_DBG_INST2_COND_REG_3 = 0x350107C6ull;
+
+static const uint64_t P9N2_C_22_DBG_INST2_COND_REG_3 = 0x360107C6ull;
+
+static const uint64_t P9N2_C_23_DBG_INST2_COND_REG_3 = 0x370107C6ull;
+
+static const uint64_t P9N2_EQ_DBG_INST2_COND_REG_3 = 0x100107C6ull;
+
+static const uint64_t P9N2_EQ_0_DBG_INST2_COND_REG_3 = 0x100107C6ull;
+
+static const uint64_t P9N2_EQ_1_DBG_INST2_COND_REG_3 = 0x110107C6ull;
+
+static const uint64_t P9N2_EQ_2_DBG_INST2_COND_REG_3 = 0x120107C6ull;
+
+static const uint64_t P9N2_EQ_3_DBG_INST2_COND_REG_3 = 0x130107C6ull;
+
+static const uint64_t P9N2_EQ_4_DBG_INST2_COND_REG_3 = 0x140107C6ull;
+
+static const uint64_t P9N2_EQ_5_DBG_INST2_COND_REG_3 = 0x150107C6ull;
+
+static const uint64_t P9N2_EX_DBG_INST2_COND_REG_3 = 0x200107C6ull;
+//DUPS: 210107C6,
+static const uint64_t P9N2_EX_0_DBG_INST2_COND_REG_3 = 0x200107C6ull;
+//DUPS: 210107C6,
+static const uint64_t P9N2_EX_1_DBG_INST2_COND_REG_3 = 0x220107C6ull;
+//DUPS: 230107C6,
+static const uint64_t P9N2_EX_2_DBG_INST2_COND_REG_3 = 0x240107C6ull;
+//DUPS: 250107C6,
+static const uint64_t P9N2_EX_3_DBG_INST2_COND_REG_3 = 0x260107C6ull;
+//DUPS: 270107C6,
+static const uint64_t P9N2_EX_4_DBG_INST2_COND_REG_3 = 0x280107C6ull;
+//DUPS: 290107C6,
+static const uint64_t P9N2_EX_5_DBG_INST2_COND_REG_3 = 0x2A0107C6ull;
+//DUPS: 2B0107C6,
+static const uint64_t P9N2_EX_6_DBG_INST2_COND_REG_3 = 0x2C0107C6ull;
+//DUPS: 2D0107C6,
+static const uint64_t P9N2_EX_7_DBG_INST2_COND_REG_3 = 0x2F0107C6ull;
+//DUPS: 2F0107C6,
+static const uint64_t P9N2_EX_8_DBG_INST2_COND_REG_3 = 0x300107C6ull;
+//DUPS: 310107C6,
+static const uint64_t P9N2_EX_9_DBG_INST2_COND_REG_3 = 0x320107C6ull;
+//DUPS: 330107C6,
+static const uint64_t P9N2_EX_10_DBG_INST2_COND_REG_3 = 0x340107C6ull;
+//DUPS: 350107C6,
+static const uint64_t P9N2_EX_11_DBG_INST2_COND_REG_3 = 0x360107C6ull;
+//DUPS: 370107C6,
+
+static const uint64_t P9N2_C_DBG_MODE_REG = 0x200107C0ull;
+
+static const uint64_t P9N2_C_0_DBG_MODE_REG = 0x200107C0ull;
+
+static const uint64_t P9N2_C_1_DBG_MODE_REG = 0x210107C0ull;
+
+static const uint64_t P9N2_C_2_DBG_MODE_REG = 0x220107C0ull;
+
+static const uint64_t P9N2_C_3_DBG_MODE_REG = 0x230107C0ull;
+
+static const uint64_t P9N2_C_4_DBG_MODE_REG = 0x240107C0ull;
+
+static const uint64_t P9N2_C_5_DBG_MODE_REG = 0x250107C0ull;
+
+static const uint64_t P9N2_C_6_DBG_MODE_REG = 0x260107C0ull;
+
+static const uint64_t P9N2_C_7_DBG_MODE_REG = 0x270107C0ull;
+
+static const uint64_t P9N2_C_8_DBG_MODE_REG = 0x280107C0ull;
+
+static const uint64_t P9N2_C_9_DBG_MODE_REG = 0x290107C0ull;
+
+static const uint64_t P9N2_C_10_DBG_MODE_REG = 0x2A0107C0ull;
+
+static const uint64_t P9N2_C_11_DBG_MODE_REG = 0x2B0107C0ull;
+
+static const uint64_t P9N2_C_12_DBG_MODE_REG = 0x2C0107C0ull;
+
+static const uint64_t P9N2_C_13_DBG_MODE_REG = 0x2D0107C0ull;
+
+static const uint64_t P9N2_C_14_DBG_MODE_REG = 0x2E0107C0ull;
+
+static const uint64_t P9N2_C_15_DBG_MODE_REG = 0x2F0107C0ull;
+
+static const uint64_t P9N2_C_16_DBG_MODE_REG = 0x300107C0ull;
+
+static const uint64_t P9N2_C_17_DBG_MODE_REG = 0x310107C0ull;
+
+static const uint64_t P9N2_C_18_DBG_MODE_REG = 0x320107C0ull;
+
+static const uint64_t P9N2_C_19_DBG_MODE_REG = 0x330107C0ull;
+
+static const uint64_t P9N2_C_20_DBG_MODE_REG = 0x340107C0ull;
+
+static const uint64_t P9N2_C_21_DBG_MODE_REG = 0x350107C0ull;
+
+static const uint64_t P9N2_C_22_DBG_MODE_REG = 0x360107C0ull;
+
+static const uint64_t P9N2_C_23_DBG_MODE_REG = 0x370107C0ull;
+
+static const uint64_t P9N2_EQ_DBG_MODE_REG = 0x100107C0ull;
+
+static const uint64_t P9N2_EQ_0_DBG_MODE_REG = 0x100107C0ull;
+
+static const uint64_t P9N2_EQ_1_DBG_MODE_REG = 0x110107C0ull;
+
+static const uint64_t P9N2_EQ_2_DBG_MODE_REG = 0x120107C0ull;
+
+static const uint64_t P9N2_EQ_3_DBG_MODE_REG = 0x130107C0ull;
+
+static const uint64_t P9N2_EQ_4_DBG_MODE_REG = 0x140107C0ull;
+
+static const uint64_t P9N2_EQ_5_DBG_MODE_REG = 0x150107C0ull;
+
+static const uint64_t P9N2_EX_DBG_MODE_REG = 0x200107C0ull;
+//DUPS: 210107C0,
+static const uint64_t P9N2_EX_0_DBG_MODE_REG = 0x200107C0ull;
+//DUPS: 210107C0,
+static const uint64_t P9N2_EX_1_DBG_MODE_REG = 0x220107C0ull;
+//DUPS: 230107C0,
+static const uint64_t P9N2_EX_2_DBG_MODE_REG = 0x240107C0ull;
+//DUPS: 250107C0,
+static const uint64_t P9N2_EX_3_DBG_MODE_REG = 0x260107C0ull;
+//DUPS: 270107C0,
+static const uint64_t P9N2_EX_4_DBG_MODE_REG = 0x280107C0ull;
+//DUPS: 290107C0,
+static const uint64_t P9N2_EX_5_DBG_MODE_REG = 0x2A0107C0ull;
+//DUPS: 2B0107C0,
+static const uint64_t P9N2_EX_6_DBG_MODE_REG = 0x2C0107C0ull;
+//DUPS: 2D0107C0,
+static const uint64_t P9N2_EX_7_DBG_MODE_REG = 0x2F0107C0ull;
+//DUPS: 2F0107C0,
+static const uint64_t P9N2_EX_8_DBG_MODE_REG = 0x300107C0ull;
+//DUPS: 310107C0,
+static const uint64_t P9N2_EX_9_DBG_MODE_REG = 0x320107C0ull;
+//DUPS: 330107C0,
+static const uint64_t P9N2_EX_10_DBG_MODE_REG = 0x340107C0ull;
+//DUPS: 350107C0,
+static const uint64_t P9N2_EX_11_DBG_MODE_REG = 0x360107C0ull;
+//DUPS: 370107C0,
+
+static const uint64_t P9N2_C_DBG_TRACE_MODE_REG_2 = 0x200107CFull;
+
+static const uint64_t P9N2_C_0_DBG_TRACE_MODE_REG_2 = 0x200107CFull;
+
+static const uint64_t P9N2_C_1_DBG_TRACE_MODE_REG_2 = 0x210107CFull;
+
+static const uint64_t P9N2_C_2_DBG_TRACE_MODE_REG_2 = 0x220107CFull;
+
+static const uint64_t P9N2_C_3_DBG_TRACE_MODE_REG_2 = 0x230107CFull;
+
+static const uint64_t P9N2_C_4_DBG_TRACE_MODE_REG_2 = 0x240107CFull;
+
+static const uint64_t P9N2_C_5_DBG_TRACE_MODE_REG_2 = 0x250107CFull;
+
+static const uint64_t P9N2_C_6_DBG_TRACE_MODE_REG_2 = 0x260107CFull;
+
+static const uint64_t P9N2_C_7_DBG_TRACE_MODE_REG_2 = 0x270107CFull;
+
+static const uint64_t P9N2_C_8_DBG_TRACE_MODE_REG_2 = 0x280107CFull;
+
+static const uint64_t P9N2_C_9_DBG_TRACE_MODE_REG_2 = 0x290107CFull;
+
+static const uint64_t P9N2_C_10_DBG_TRACE_MODE_REG_2 = 0x2A0107CFull;
+
+static const uint64_t P9N2_C_11_DBG_TRACE_MODE_REG_2 = 0x2B0107CFull;
+
+static const uint64_t P9N2_C_12_DBG_TRACE_MODE_REG_2 = 0x2C0107CFull;
+
+static const uint64_t P9N2_C_13_DBG_TRACE_MODE_REG_2 = 0x2D0107CFull;
+
+static const uint64_t P9N2_C_14_DBG_TRACE_MODE_REG_2 = 0x2E0107CFull;
+
+static const uint64_t P9N2_C_15_DBG_TRACE_MODE_REG_2 = 0x2F0107CFull;
+
+static const uint64_t P9N2_C_16_DBG_TRACE_MODE_REG_2 = 0x300107CFull;
+
+static const uint64_t P9N2_C_17_DBG_TRACE_MODE_REG_2 = 0x310107CFull;
+
+static const uint64_t P9N2_C_18_DBG_TRACE_MODE_REG_2 = 0x320107CFull;
+
+static const uint64_t P9N2_C_19_DBG_TRACE_MODE_REG_2 = 0x330107CFull;
+
+static const uint64_t P9N2_C_20_DBG_TRACE_MODE_REG_2 = 0x340107CFull;
+
+static const uint64_t P9N2_C_21_DBG_TRACE_MODE_REG_2 = 0x350107CFull;
+
+static const uint64_t P9N2_C_22_DBG_TRACE_MODE_REG_2 = 0x360107CFull;
+
+static const uint64_t P9N2_C_23_DBG_TRACE_MODE_REG_2 = 0x370107CFull;
+
+static const uint64_t P9N2_EQ_DBG_TRACE_MODE_REG_2 = 0x100107CFull;
+
+static const uint64_t P9N2_EQ_0_DBG_TRACE_MODE_REG_2 = 0x100107CFull;
+
+static const uint64_t P9N2_EQ_1_DBG_TRACE_MODE_REG_2 = 0x110107CFull;
+
+static const uint64_t P9N2_EQ_2_DBG_TRACE_MODE_REG_2 = 0x120107CFull;
+
+static const uint64_t P9N2_EQ_3_DBG_TRACE_MODE_REG_2 = 0x130107CFull;
+
+static const uint64_t P9N2_EQ_4_DBG_TRACE_MODE_REG_2 = 0x140107CFull;
+
+static const uint64_t P9N2_EQ_5_DBG_TRACE_MODE_REG_2 = 0x150107CFull;
+
+static const uint64_t P9N2_EX_DBG_TRACE_MODE_REG_2 = 0x200107CFull;
+//DUPS: 210107CF,
+static const uint64_t P9N2_EX_0_DBG_TRACE_MODE_REG_2 = 0x200107CFull;
+//DUPS: 210107CF,
+static const uint64_t P9N2_EX_1_DBG_TRACE_MODE_REG_2 = 0x220107CFull;
+//DUPS: 230107CF,
+static const uint64_t P9N2_EX_2_DBG_TRACE_MODE_REG_2 = 0x240107CFull;
+//DUPS: 250107CF,
+static const uint64_t P9N2_EX_3_DBG_TRACE_MODE_REG_2 = 0x260107CFull;
+//DUPS: 270107CF,
+static const uint64_t P9N2_EX_4_DBG_TRACE_MODE_REG_2 = 0x280107CFull;
+//DUPS: 290107CF,
+static const uint64_t P9N2_EX_5_DBG_TRACE_MODE_REG_2 = 0x2A0107CFull;
+//DUPS: 2B0107CF,
+static const uint64_t P9N2_EX_6_DBG_TRACE_MODE_REG_2 = 0x2C0107CFull;
+//DUPS: 2D0107CF,
+static const uint64_t P9N2_EX_7_DBG_TRACE_MODE_REG_2 = 0x2F0107CFull;
+//DUPS: 2F0107CF,
+static const uint64_t P9N2_EX_8_DBG_TRACE_MODE_REG_2 = 0x300107CFull;
+//DUPS: 310107CF,
+static const uint64_t P9N2_EX_9_DBG_TRACE_MODE_REG_2 = 0x320107CFull;
+//DUPS: 330107CF,
+static const uint64_t P9N2_EX_10_DBG_TRACE_MODE_REG_2 = 0x340107CFull;
+//DUPS: 350107CF,
+static const uint64_t P9N2_EX_11_DBG_TRACE_MODE_REG_2 = 0x360107CFull;
+//DUPS: 370107CF,
+
+static const uint64_t P9N2_C_DBG_TRACE_REG_0 = 0x200107CDull;
+
+static const uint64_t P9N2_C_0_DBG_TRACE_REG_0 = 0x200107CDull;
+
+static const uint64_t P9N2_C_1_DBG_TRACE_REG_0 = 0x210107CDull;
+
+static const uint64_t P9N2_C_2_DBG_TRACE_REG_0 = 0x220107CDull;
+
+static const uint64_t P9N2_C_3_DBG_TRACE_REG_0 = 0x230107CDull;
+
+static const uint64_t P9N2_C_4_DBG_TRACE_REG_0 = 0x240107CDull;
+
+static const uint64_t P9N2_C_5_DBG_TRACE_REG_0 = 0x250107CDull;
+
+static const uint64_t P9N2_C_6_DBG_TRACE_REG_0 = 0x260107CDull;
+
+static const uint64_t P9N2_C_7_DBG_TRACE_REG_0 = 0x270107CDull;
+
+static const uint64_t P9N2_C_8_DBG_TRACE_REG_0 = 0x280107CDull;
+
+static const uint64_t P9N2_C_9_DBG_TRACE_REG_0 = 0x290107CDull;
+
+static const uint64_t P9N2_C_10_DBG_TRACE_REG_0 = 0x2A0107CDull;
+
+static const uint64_t P9N2_C_11_DBG_TRACE_REG_0 = 0x2B0107CDull;
+
+static const uint64_t P9N2_C_12_DBG_TRACE_REG_0 = 0x2C0107CDull;
+
+static const uint64_t P9N2_C_13_DBG_TRACE_REG_0 = 0x2D0107CDull;
+
+static const uint64_t P9N2_C_14_DBG_TRACE_REG_0 = 0x2E0107CDull;
+
+static const uint64_t P9N2_C_15_DBG_TRACE_REG_0 = 0x2F0107CDull;
+
+static const uint64_t P9N2_C_16_DBG_TRACE_REG_0 = 0x300107CDull;
+
+static const uint64_t P9N2_C_17_DBG_TRACE_REG_0 = 0x310107CDull;
+
+static const uint64_t P9N2_C_18_DBG_TRACE_REG_0 = 0x320107CDull;
+
+static const uint64_t P9N2_C_19_DBG_TRACE_REG_0 = 0x330107CDull;
+
+static const uint64_t P9N2_C_20_DBG_TRACE_REG_0 = 0x340107CDull;
+
+static const uint64_t P9N2_C_21_DBG_TRACE_REG_0 = 0x350107CDull;
+
+static const uint64_t P9N2_C_22_DBG_TRACE_REG_0 = 0x360107CDull;
+
+static const uint64_t P9N2_C_23_DBG_TRACE_REG_0 = 0x370107CDull;
+
+static const uint64_t P9N2_EQ_DBG_TRACE_REG_0 = 0x100107CDull;
+
+static const uint64_t P9N2_EQ_0_DBG_TRACE_REG_0 = 0x100107CDull;
+
+static const uint64_t P9N2_EQ_1_DBG_TRACE_REG_0 = 0x110107CDull;
+
+static const uint64_t P9N2_EQ_2_DBG_TRACE_REG_0 = 0x120107CDull;
+
+static const uint64_t P9N2_EQ_3_DBG_TRACE_REG_0 = 0x130107CDull;
+
+static const uint64_t P9N2_EQ_4_DBG_TRACE_REG_0 = 0x140107CDull;
+
+static const uint64_t P9N2_EQ_5_DBG_TRACE_REG_0 = 0x150107CDull;
+
+static const uint64_t P9N2_EX_DBG_TRACE_REG_0 = 0x200107CDull;
+//DUPS: 210107CD,
+static const uint64_t P9N2_EX_0_DBG_TRACE_REG_0 = 0x200107CDull;
+//DUPS: 210107CD,
+static const uint64_t P9N2_EX_1_DBG_TRACE_REG_0 = 0x220107CDull;
+//DUPS: 230107CD,
+static const uint64_t P9N2_EX_2_DBG_TRACE_REG_0 = 0x240107CDull;
+//DUPS: 250107CD,
+static const uint64_t P9N2_EX_3_DBG_TRACE_REG_0 = 0x260107CDull;
+//DUPS: 270107CD,
+static const uint64_t P9N2_EX_4_DBG_TRACE_REG_0 = 0x280107CDull;
+//DUPS: 290107CD,
+static const uint64_t P9N2_EX_5_DBG_TRACE_REG_0 = 0x2A0107CDull;
+//DUPS: 2B0107CD,
+static const uint64_t P9N2_EX_6_DBG_TRACE_REG_0 = 0x2C0107CDull;
+//DUPS: 2D0107CD,
+static const uint64_t P9N2_EX_7_DBG_TRACE_REG_0 = 0x2F0107CDull;
+//DUPS: 2F0107CD,
+static const uint64_t P9N2_EX_8_DBG_TRACE_REG_0 = 0x300107CDull;
+//DUPS: 310107CD,
+static const uint64_t P9N2_EX_9_DBG_TRACE_REG_0 = 0x320107CDull;
+//DUPS: 330107CD,
+static const uint64_t P9N2_EX_10_DBG_TRACE_REG_0 = 0x340107CDull;
+//DUPS: 350107CD,
+static const uint64_t P9N2_EX_11_DBG_TRACE_REG_0 = 0x360107CDull;
+//DUPS: 370107CD,
+
+static const uint64_t P9N2_C_DBG_TRACE_REG_1 = 0x200107CEull;
+
+static const uint64_t P9N2_C_0_DBG_TRACE_REG_1 = 0x200107CEull;
+
+static const uint64_t P9N2_C_1_DBG_TRACE_REG_1 = 0x210107CEull;
+
+static const uint64_t P9N2_C_2_DBG_TRACE_REG_1 = 0x220107CEull;
+
+static const uint64_t P9N2_C_3_DBG_TRACE_REG_1 = 0x230107CEull;
+
+static const uint64_t P9N2_C_4_DBG_TRACE_REG_1 = 0x240107CEull;
+
+static const uint64_t P9N2_C_5_DBG_TRACE_REG_1 = 0x250107CEull;
+
+static const uint64_t P9N2_C_6_DBG_TRACE_REG_1 = 0x260107CEull;
+
+static const uint64_t P9N2_C_7_DBG_TRACE_REG_1 = 0x270107CEull;
+
+static const uint64_t P9N2_C_8_DBG_TRACE_REG_1 = 0x280107CEull;
+
+static const uint64_t P9N2_C_9_DBG_TRACE_REG_1 = 0x290107CEull;
+
+static const uint64_t P9N2_C_10_DBG_TRACE_REG_1 = 0x2A0107CEull;
+
+static const uint64_t P9N2_C_11_DBG_TRACE_REG_1 = 0x2B0107CEull;
+
+static const uint64_t P9N2_C_12_DBG_TRACE_REG_1 = 0x2C0107CEull;
+
+static const uint64_t P9N2_C_13_DBG_TRACE_REG_1 = 0x2D0107CEull;
+
+static const uint64_t P9N2_C_14_DBG_TRACE_REG_1 = 0x2E0107CEull;
+
+static const uint64_t P9N2_C_15_DBG_TRACE_REG_1 = 0x2F0107CEull;
+
+static const uint64_t P9N2_C_16_DBG_TRACE_REG_1 = 0x300107CEull;
+
+static const uint64_t P9N2_C_17_DBG_TRACE_REG_1 = 0x310107CEull;
+
+static const uint64_t P9N2_C_18_DBG_TRACE_REG_1 = 0x320107CEull;
+
+static const uint64_t P9N2_C_19_DBG_TRACE_REG_1 = 0x330107CEull;
+
+static const uint64_t P9N2_C_20_DBG_TRACE_REG_1 = 0x340107CEull;
+
+static const uint64_t P9N2_C_21_DBG_TRACE_REG_1 = 0x350107CEull;
+
+static const uint64_t P9N2_C_22_DBG_TRACE_REG_1 = 0x360107CEull;
+
+static const uint64_t P9N2_C_23_DBG_TRACE_REG_1 = 0x370107CEull;
+
+static const uint64_t P9N2_EQ_DBG_TRACE_REG_1 = 0x100107CEull;
+
+static const uint64_t P9N2_EQ_0_DBG_TRACE_REG_1 = 0x100107CEull;
+
+static const uint64_t P9N2_EQ_1_DBG_TRACE_REG_1 = 0x110107CEull;
+
+static const uint64_t P9N2_EQ_2_DBG_TRACE_REG_1 = 0x120107CEull;
+
+static const uint64_t P9N2_EQ_3_DBG_TRACE_REG_1 = 0x130107CEull;
+
+static const uint64_t P9N2_EQ_4_DBG_TRACE_REG_1 = 0x140107CEull;
+
+static const uint64_t P9N2_EQ_5_DBG_TRACE_REG_1 = 0x150107CEull;
+
+static const uint64_t P9N2_EX_DBG_TRACE_REG_1 = 0x200107CEull;
+//DUPS: 210107CE,
+static const uint64_t P9N2_EX_0_DBG_TRACE_REG_1 = 0x200107CEull;
+//DUPS: 210107CE,
+static const uint64_t P9N2_EX_1_DBG_TRACE_REG_1 = 0x220107CEull;
+//DUPS: 230107CE,
+static const uint64_t P9N2_EX_2_DBG_TRACE_REG_1 = 0x240107CEull;
+//DUPS: 250107CE,
+static const uint64_t P9N2_EX_3_DBG_TRACE_REG_1 = 0x260107CEull;
+//DUPS: 270107CE,
+static const uint64_t P9N2_EX_4_DBG_TRACE_REG_1 = 0x280107CEull;
+//DUPS: 290107CE,
+static const uint64_t P9N2_EX_5_DBG_TRACE_REG_1 = 0x2A0107CEull;
+//DUPS: 2B0107CE,
+static const uint64_t P9N2_EX_6_DBG_TRACE_REG_1 = 0x2C0107CEull;
+//DUPS: 2D0107CE,
+static const uint64_t P9N2_EX_7_DBG_TRACE_REG_1 = 0x2F0107CEull;
+//DUPS: 2F0107CE,
+static const uint64_t P9N2_EX_8_DBG_TRACE_REG_1 = 0x300107CEull;
+//DUPS: 310107CE,
+static const uint64_t P9N2_EX_9_DBG_TRACE_REG_1 = 0x320107CEull;
+//DUPS: 330107CE,
+static const uint64_t P9N2_EX_10_DBG_TRACE_REG_1 = 0x340107CEull;
+//DUPS: 350107CE,
+static const uint64_t P9N2_EX_11_DBG_TRACE_REG_1 = 0x360107CEull;
+//DUPS: 370107CE,
+
+static const uint64_t P9N2_C_DEBUG_TRACE_CONTROL = 0x200107D0ull;
+
+static const uint64_t P9N2_C_0_DEBUG_TRACE_CONTROL = 0x200107D0ull;
+
+static const uint64_t P9N2_C_1_DEBUG_TRACE_CONTROL = 0x210107D0ull;
+
+static const uint64_t P9N2_C_2_DEBUG_TRACE_CONTROL = 0x220107D0ull;
+
+static const uint64_t P9N2_C_3_DEBUG_TRACE_CONTROL = 0x230107D0ull;
+
+static const uint64_t P9N2_C_4_DEBUG_TRACE_CONTROL = 0x240107D0ull;
+
+static const uint64_t P9N2_C_5_DEBUG_TRACE_CONTROL = 0x250107D0ull;
+
+static const uint64_t P9N2_C_6_DEBUG_TRACE_CONTROL = 0x260107D0ull;
+
+static const uint64_t P9N2_C_7_DEBUG_TRACE_CONTROL = 0x270107D0ull;
+
+static const uint64_t P9N2_C_8_DEBUG_TRACE_CONTROL = 0x280107D0ull;
+
+static const uint64_t P9N2_C_9_DEBUG_TRACE_CONTROL = 0x290107D0ull;
+
+static const uint64_t P9N2_C_10_DEBUG_TRACE_CONTROL = 0x2A0107D0ull;
+
+static const uint64_t P9N2_C_11_DEBUG_TRACE_CONTROL = 0x2B0107D0ull;
+
+static const uint64_t P9N2_C_12_DEBUG_TRACE_CONTROL = 0x2C0107D0ull;
+
+static const uint64_t P9N2_C_13_DEBUG_TRACE_CONTROL = 0x2D0107D0ull;
+
+static const uint64_t P9N2_C_14_DEBUG_TRACE_CONTROL = 0x2E0107D0ull;
+
+static const uint64_t P9N2_C_15_DEBUG_TRACE_CONTROL = 0x2F0107D0ull;
+
+static const uint64_t P9N2_C_16_DEBUG_TRACE_CONTROL = 0x300107D0ull;
+
+static const uint64_t P9N2_C_17_DEBUG_TRACE_CONTROL = 0x310107D0ull;
+
+static const uint64_t P9N2_C_18_DEBUG_TRACE_CONTROL = 0x320107D0ull;
+
+static const uint64_t P9N2_C_19_DEBUG_TRACE_CONTROL = 0x330107D0ull;
+
+static const uint64_t P9N2_C_20_DEBUG_TRACE_CONTROL = 0x340107D0ull;
+
+static const uint64_t P9N2_C_21_DEBUG_TRACE_CONTROL = 0x350107D0ull;
+
+static const uint64_t P9N2_C_22_DEBUG_TRACE_CONTROL = 0x360107D0ull;
+
+static const uint64_t P9N2_C_23_DEBUG_TRACE_CONTROL = 0x370107D0ull;
+
+static const uint64_t P9N2_EQ_DEBUG_TRACE_CONTROL = 0x100107D0ull;
+
+static const uint64_t P9N2_EQ_0_DEBUG_TRACE_CONTROL = 0x100107D0ull;
+
+static const uint64_t P9N2_EQ_1_DEBUG_TRACE_CONTROL = 0x110107D0ull;
+
+static const uint64_t P9N2_EQ_2_DEBUG_TRACE_CONTROL = 0x120107D0ull;
+
+static const uint64_t P9N2_EQ_3_DEBUG_TRACE_CONTROL = 0x130107D0ull;
+
+static const uint64_t P9N2_EQ_4_DEBUG_TRACE_CONTROL = 0x140107D0ull;
+
+static const uint64_t P9N2_EQ_5_DEBUG_TRACE_CONTROL = 0x150107D0ull;
+
+static const uint64_t P9N2_EX_DEBUG_TRACE_CONTROL = 0x200107D0ull;
+//DUPS: 210107D0,
+static const uint64_t P9N2_EX_0_DEBUG_TRACE_CONTROL = 0x200107D0ull;
+//DUPS: 210107D0,
+static const uint64_t P9N2_EX_1_DEBUG_TRACE_CONTROL = 0x220107D0ull;
+//DUPS: 230107D0,
+static const uint64_t P9N2_EX_2_DEBUG_TRACE_CONTROL = 0x240107D0ull;
+//DUPS: 250107D0,
+static const uint64_t P9N2_EX_3_DEBUG_TRACE_CONTROL = 0x260107D0ull;
+//DUPS: 270107D0,
+static const uint64_t P9N2_EX_4_DEBUG_TRACE_CONTROL = 0x280107D0ull;
+//DUPS: 290107D0,
+static const uint64_t P9N2_EX_5_DEBUG_TRACE_CONTROL = 0x2A0107D0ull;
+//DUPS: 2B0107D0,
+static const uint64_t P9N2_EX_6_DEBUG_TRACE_CONTROL = 0x2C0107D0ull;
+//DUPS: 2D0107D0,
+static const uint64_t P9N2_EX_7_DEBUG_TRACE_CONTROL = 0x2F0107D0ull;
+//DUPS: 2F0107D0,
+static const uint64_t P9N2_EX_8_DEBUG_TRACE_CONTROL = 0x300107D0ull;
+//DUPS: 310107D0,
+static const uint64_t P9N2_EX_9_DEBUG_TRACE_CONTROL = 0x320107D0ull;
+//DUPS: 330107D0,
+static const uint64_t P9N2_EX_10_DEBUG_TRACE_CONTROL = 0x340107D0ull;
+//DUPS: 350107D0,
+static const uint64_t P9N2_EX_11_DEBUG_TRACE_CONTROL = 0x360107D0ull;
+//DUPS: 370107D0,
+
+static const uint64_t P9N2_C_DIRECT_CONTROLS = 0x20010A9Cull;
+
+static const uint64_t P9N2_C_0_DIRECT_CONTROLS = 0x20010A9Cull;
+
+static const uint64_t P9N2_C_1_DIRECT_CONTROLS = 0x21010A9Cull;
+
+static const uint64_t P9N2_C_2_DIRECT_CONTROLS = 0x22010A9Cull;
+
+static const uint64_t P9N2_C_3_DIRECT_CONTROLS = 0x23010A9Cull;
+
+static const uint64_t P9N2_C_4_DIRECT_CONTROLS = 0x24010A9Cull;
+
+static const uint64_t P9N2_C_5_DIRECT_CONTROLS = 0x25010A9Cull;
+
+static const uint64_t P9N2_C_6_DIRECT_CONTROLS = 0x26010A9Cull;
+
+static const uint64_t P9N2_C_7_DIRECT_CONTROLS = 0x27010A9Cull;
+
+static const uint64_t P9N2_C_8_DIRECT_CONTROLS = 0x28010A9Cull;
+
+static const uint64_t P9N2_C_9_DIRECT_CONTROLS = 0x29010A9Cull;
+
+static const uint64_t P9N2_C_10_DIRECT_CONTROLS = 0x2A010A9Cull;
+
+static const uint64_t P9N2_C_11_DIRECT_CONTROLS = 0x2B010A9Cull;
+
+static const uint64_t P9N2_C_12_DIRECT_CONTROLS = 0x2C010A9Cull;
+
+static const uint64_t P9N2_C_13_DIRECT_CONTROLS = 0x2D010A9Cull;
+
+static const uint64_t P9N2_C_14_DIRECT_CONTROLS = 0x2E010A9Cull;
+
+static const uint64_t P9N2_C_15_DIRECT_CONTROLS = 0x2F010A9Cull;
+
+static const uint64_t P9N2_C_16_DIRECT_CONTROLS = 0x30010A9Cull;
+
+static const uint64_t P9N2_C_17_DIRECT_CONTROLS = 0x31010A9Cull;
+
+static const uint64_t P9N2_C_18_DIRECT_CONTROLS = 0x32010A9Cull;
+
+static const uint64_t P9N2_C_19_DIRECT_CONTROLS = 0x33010A9Cull;
+
+static const uint64_t P9N2_C_20_DIRECT_CONTROLS = 0x34010A9Cull;
+
+static const uint64_t P9N2_C_21_DIRECT_CONTROLS = 0x35010A9Cull;
+
+static const uint64_t P9N2_C_22_DIRECT_CONTROLS = 0x36010A9Cull;
+
+static const uint64_t P9N2_C_23_DIRECT_CONTROLS = 0x37010A9Cull;
+
+static const uint64_t P9N2_EX_0_L2_DIRECT_CONTROLS = 0x20010A9Cull;
+//DUPS: 20010A9C,
+static const uint64_t P9N2_EX_10_L2_DIRECT_CONTROLS = 0x34010A9Cull;
+//DUPS: 34010A9C,
+static const uint64_t P9N2_EX_11_L2_DIRECT_CONTROLS = 0x36010A9Cull;
+//DUPS: 36010A9C,
+static const uint64_t P9N2_EX_1_L2_DIRECT_CONTROLS = 0x22010A9Cull;
+//DUPS: 22010A9C,
+static const uint64_t P9N2_EX_2_L2_DIRECT_CONTROLS = 0x24010A9Cull;
+//DUPS: 24010A9C,
+static const uint64_t P9N2_EX_3_L2_DIRECT_CONTROLS = 0x26010A9Cull;
+//DUPS: 26010A9C,
+static const uint64_t P9N2_EX_4_L2_DIRECT_CONTROLS = 0x28010A9Cull;
+//DUPS: 28010A9C,
+static const uint64_t P9N2_EX_5_L2_DIRECT_CONTROLS = 0x2B010A9Cull;
+//DUPS: 2A010A9C,
+static const uint64_t P9N2_EX_6_L2_DIRECT_CONTROLS = 0x2D010A9Cull;
+//DUPS: 2C010A9C,
+static const uint64_t P9N2_EX_7_L2_DIRECT_CONTROLS = 0x2F010A9Cull;
+//DUPS: 2E010A9C,
+static const uint64_t P9N2_EX_8_L2_DIRECT_CONTROLS = 0x30010A9Cull;
+//DUPS: 30010A9C,
+static const uint64_t P9N2_EX_9_L2_DIRECT_CONTROLS = 0x32010A9Cull;
+//DUPS: 32010A9C,
+static const uint64_t P9N2_EX_L2_DIRECT_CONTROLS = 0x20010A9Cull;
+//DUPS: 20010A9C,
+
+static const uint64_t P9N2_EQ_DRAM_REF_REG = 0x10011C0Full;
+//DUPS: 10011C0F,
+static const uint64_t P9N2_EQ_0_DRAM_REF_REG = 0x10011C0Full;
+//DUPS: 10011C0F,
+static const uint64_t P9N2_EQ_1_DRAM_REF_REG = 0x11011C0Full;
+//DUPS: 11011C0F,
+static const uint64_t P9N2_EQ_2_DRAM_REF_REG = 0x12011C0Full;
+//DUPS: 12011C0F,
+static const uint64_t P9N2_EQ_3_DRAM_REF_REG = 0x13011C0Full;
+//DUPS: 13011C0F,
+static const uint64_t P9N2_EQ_4_DRAM_REF_REG = 0x14011C0Full;
+//DUPS: 14011C0F,
+static const uint64_t P9N2_EQ_5_DRAM_REF_REG = 0x15011C0Full;
+//DUPS: 15011C0F,
+static const uint64_t P9N2_EX_DRAM_REF_REG = 0x1001180Full;
+
+static const uint64_t P9N2_EX_0_DRAM_REF_REG = 0x1001180Full;
+
+static const uint64_t P9N2_EX_1_DRAM_REF_REG = 0x10011C0Full;
+
+static const uint64_t P9N2_EX_2_DRAM_REF_REG = 0x1101180Full;
+
+static const uint64_t P9N2_EX_3_DRAM_REF_REG = 0x11011C0Full;
+
+static const uint64_t P9N2_EX_4_DRAM_REF_REG = 0x1201180Full;
+
+static const uint64_t P9N2_EX_5_DRAM_REF_REG = 0x12011C0Full;
+
+static const uint64_t P9N2_EX_6_DRAM_REF_REG = 0x1301180Full;
+
+static const uint64_t P9N2_EX_7_DRAM_REF_REG = 0x13011C0Full;
+
+static const uint64_t P9N2_EX_8_DRAM_REF_REG = 0x1401180Full;
+
+static const uint64_t P9N2_EX_9_DRAM_REF_REG = 0x14011C0Full;
+
+static const uint64_t P9N2_EX_10_DRAM_REF_REG = 0x1501180Full;
+
+static const uint64_t P9N2_EX_11_DRAM_REF_REG = 0x15011C0Full;
+
+
+static const uint64_t P9N2_C_DTS_RESULT0 = 0x20050000ull;
+
+static const uint64_t P9N2_C_0_DTS_RESULT0 = 0x20050000ull;
+
+static const uint64_t P9N2_C_1_DTS_RESULT0 = 0x21050000ull;
+
+static const uint64_t P9N2_C_2_DTS_RESULT0 = 0x22050000ull;
+
+static const uint64_t P9N2_C_3_DTS_RESULT0 = 0x23050000ull;
+
+static const uint64_t P9N2_C_4_DTS_RESULT0 = 0x24050000ull;
+
+static const uint64_t P9N2_C_5_DTS_RESULT0 = 0x25050000ull;
+
+static const uint64_t P9N2_C_6_DTS_RESULT0 = 0x26050000ull;
+
+static const uint64_t P9N2_C_7_DTS_RESULT0 = 0x27050000ull;
+
+static const uint64_t P9N2_C_8_DTS_RESULT0 = 0x28050000ull;
+
+static const uint64_t P9N2_C_9_DTS_RESULT0 = 0x29050000ull;
+
+static const uint64_t P9N2_C_10_DTS_RESULT0 = 0x2A050000ull;
+
+static const uint64_t P9N2_C_11_DTS_RESULT0 = 0x2B050000ull;
+
+static const uint64_t P9N2_C_12_DTS_RESULT0 = 0x2C050000ull;
+
+static const uint64_t P9N2_C_13_DTS_RESULT0 = 0x2D050000ull;
+
+static const uint64_t P9N2_C_14_DTS_RESULT0 = 0x2E050000ull;
+
+static const uint64_t P9N2_C_15_DTS_RESULT0 = 0x2F050000ull;
+
+static const uint64_t P9N2_C_16_DTS_RESULT0 = 0x30050000ull;
+
+static const uint64_t P9N2_C_17_DTS_RESULT0 = 0x31050000ull;
+
+static const uint64_t P9N2_C_18_DTS_RESULT0 = 0x32050000ull;
+
+static const uint64_t P9N2_C_19_DTS_RESULT0 = 0x33050000ull;
+
+static const uint64_t P9N2_C_20_DTS_RESULT0 = 0x34050000ull;
+
+static const uint64_t P9N2_C_21_DTS_RESULT0 = 0x35050000ull;
+
+static const uint64_t P9N2_C_22_DTS_RESULT0 = 0x36050000ull;
+
+static const uint64_t P9N2_C_23_DTS_RESULT0 = 0x37050000ull;
+
+static const uint64_t P9N2_EQ_DTS_RESULT0 = 0x10050000ull;
+
+static const uint64_t P9N2_EQ_0_DTS_RESULT0 = 0x10050000ull;
+
+static const uint64_t P9N2_EQ_1_DTS_RESULT0 = 0x11050000ull;
+
+static const uint64_t P9N2_EQ_2_DTS_RESULT0 = 0x12050000ull;
+
+static const uint64_t P9N2_EQ_3_DTS_RESULT0 = 0x13050000ull;
+
+static const uint64_t P9N2_EQ_4_DTS_RESULT0 = 0x14050000ull;
+
+static const uint64_t P9N2_EQ_5_DTS_RESULT0 = 0x15050000ull;
+
+static const uint64_t P9N2_EX_DTS_RESULT0 = 0x20050000ull;
+//DUPS: 21050000,
+static const uint64_t P9N2_EX_0_DTS_RESULT0 = 0x20050000ull;
+//DUPS: 21050000,
+static const uint64_t P9N2_EX_1_DTS_RESULT0 = 0x22050000ull;
+//DUPS: 23050000,
+static const uint64_t P9N2_EX_2_DTS_RESULT0 = 0x24050000ull;
+//DUPS: 25050000,
+static const uint64_t P9N2_EX_3_DTS_RESULT0 = 0x26050000ull;
+//DUPS: 27050000,
+static const uint64_t P9N2_EX_4_DTS_RESULT0 = 0x28050000ull;
+//DUPS: 29050000,
+static const uint64_t P9N2_EX_5_DTS_RESULT0 = 0x2A050000ull;
+//DUPS: 2B050000,
+static const uint64_t P9N2_EX_6_DTS_RESULT0 = 0x2C050000ull;
+//DUPS: 2D050000,
+static const uint64_t P9N2_EX_7_DTS_RESULT0 = 0x2F050000ull;
+//DUPS: 2F050000,
+static const uint64_t P9N2_EX_8_DTS_RESULT0 = 0x30050000ull;
+//DUPS: 31050000,
+static const uint64_t P9N2_EX_9_DTS_RESULT0 = 0x32050000ull;
+//DUPS: 33050000,
+static const uint64_t P9N2_EX_10_DTS_RESULT0 = 0x34050000ull;
+//DUPS: 35050000,
+static const uint64_t P9N2_EX_11_DTS_RESULT0 = 0x36050000ull;
+//DUPS: 37050000,
+
+static const uint64_t P9N2_C_DTS_TRC_RESULT = 0x20050003ull;
+
+static const uint64_t P9N2_C_0_DTS_TRC_RESULT = 0x20050003ull;
+
+static const uint64_t P9N2_C_1_DTS_TRC_RESULT = 0x21050003ull;
+
+static const uint64_t P9N2_C_2_DTS_TRC_RESULT = 0x22050003ull;
+
+static const uint64_t P9N2_C_3_DTS_TRC_RESULT = 0x23050003ull;
+
+static const uint64_t P9N2_C_4_DTS_TRC_RESULT = 0x24050003ull;
+
+static const uint64_t P9N2_C_5_DTS_TRC_RESULT = 0x25050003ull;
+
+static const uint64_t P9N2_C_6_DTS_TRC_RESULT = 0x26050003ull;
+
+static const uint64_t P9N2_C_7_DTS_TRC_RESULT = 0x27050003ull;
+
+static const uint64_t P9N2_C_8_DTS_TRC_RESULT = 0x28050003ull;
+
+static const uint64_t P9N2_C_9_DTS_TRC_RESULT = 0x29050003ull;
+
+static const uint64_t P9N2_C_10_DTS_TRC_RESULT = 0x2A050003ull;
+
+static const uint64_t P9N2_C_11_DTS_TRC_RESULT = 0x2B050003ull;
+
+static const uint64_t P9N2_C_12_DTS_TRC_RESULT = 0x2C050003ull;
+
+static const uint64_t P9N2_C_13_DTS_TRC_RESULT = 0x2D050003ull;
+
+static const uint64_t P9N2_C_14_DTS_TRC_RESULT = 0x2E050003ull;
+
+static const uint64_t P9N2_C_15_DTS_TRC_RESULT = 0x2F050003ull;
+
+static const uint64_t P9N2_C_16_DTS_TRC_RESULT = 0x30050003ull;
+
+static const uint64_t P9N2_C_17_DTS_TRC_RESULT = 0x31050003ull;
+
+static const uint64_t P9N2_C_18_DTS_TRC_RESULT = 0x32050003ull;
+
+static const uint64_t P9N2_C_19_DTS_TRC_RESULT = 0x33050003ull;
+
+static const uint64_t P9N2_C_20_DTS_TRC_RESULT = 0x34050003ull;
+
+static const uint64_t P9N2_C_21_DTS_TRC_RESULT = 0x35050003ull;
+
+static const uint64_t P9N2_C_22_DTS_TRC_RESULT = 0x36050003ull;
+
+static const uint64_t P9N2_C_23_DTS_TRC_RESULT = 0x37050003ull;
+
+static const uint64_t P9N2_EQ_DTS_TRC_RESULT = 0x10050003ull;
+
+static const uint64_t P9N2_EQ_0_DTS_TRC_RESULT = 0x10050003ull;
+
+static const uint64_t P9N2_EQ_1_DTS_TRC_RESULT = 0x11050003ull;
+
+static const uint64_t P9N2_EQ_2_DTS_TRC_RESULT = 0x12050003ull;
+
+static const uint64_t P9N2_EQ_3_DTS_TRC_RESULT = 0x13050003ull;
+
+static const uint64_t P9N2_EQ_4_DTS_TRC_RESULT = 0x14050003ull;
+
+static const uint64_t P9N2_EQ_5_DTS_TRC_RESULT = 0x15050003ull;
+
+static const uint64_t P9N2_EX_DTS_TRC_RESULT = 0x20050003ull;
+//DUPS: 21050003,
+static const uint64_t P9N2_EX_0_DTS_TRC_RESULT = 0x20050003ull;
+//DUPS: 21050003,
+static const uint64_t P9N2_EX_1_DTS_TRC_RESULT = 0x22050003ull;
+//DUPS: 23050003,
+static const uint64_t P9N2_EX_2_DTS_TRC_RESULT = 0x24050003ull;
+//DUPS: 25050003,
+static const uint64_t P9N2_EX_3_DTS_TRC_RESULT = 0x26050003ull;
+//DUPS: 27050003,
+static const uint64_t P9N2_EX_4_DTS_TRC_RESULT = 0x28050003ull;
+//DUPS: 29050003,
+static const uint64_t P9N2_EX_5_DTS_TRC_RESULT = 0x2A050003ull;
+//DUPS: 2B050003,
+static const uint64_t P9N2_EX_6_DTS_TRC_RESULT = 0x2C050003ull;
+//DUPS: 2D050003,
+static const uint64_t P9N2_EX_7_DTS_TRC_RESULT = 0x2F050003ull;
+//DUPS: 2F050003,
+static const uint64_t P9N2_EX_8_DTS_TRC_RESULT = 0x30050003ull;
+//DUPS: 31050003,
+static const uint64_t P9N2_EX_9_DTS_TRC_RESULT = 0x32050003ull;
+//DUPS: 33050003,
+static const uint64_t P9N2_EX_10_DTS_TRC_RESULT = 0x34050003ull;
+//DUPS: 35050003,
+static const uint64_t P9N2_EX_11_DTS_TRC_RESULT = 0x36050003ull;
+//DUPS: 37050003,
+
+static const uint64_t P9N2_EQ_EDRAM_BANK_FAIL_SCOM_RD = 0x10011C1Bull;
+//DUPS: 10011C1B,
+static const uint64_t P9N2_EQ_0_EDRAM_BANK_FAIL_SCOM_RD = 0x10011C1Bull;
+//DUPS: 10011C1B,
+static const uint64_t P9N2_EQ_1_EDRAM_BANK_FAIL_SCOM_RD = 0x11011C1Bull;
+//DUPS: 11011C1B,
+static const uint64_t P9N2_EQ_2_EDRAM_BANK_FAIL_SCOM_RD = 0x12011C1Bull;
+//DUPS: 12011C1B,
+static const uint64_t P9N2_EQ_3_EDRAM_BANK_FAIL_SCOM_RD = 0x13011C1Bull;
+//DUPS: 13011C1B,
+static const uint64_t P9N2_EQ_4_EDRAM_BANK_FAIL_SCOM_RD = 0x14011C1Bull;
+//DUPS: 14011C1B,
+static const uint64_t P9N2_EQ_5_EDRAM_BANK_FAIL_SCOM_RD = 0x15011C1Bull;
+//DUPS: 15011C1B,
+static const uint64_t P9N2_EX_0_L3_EDRAM_BANK_FAIL_SCOM_RD = 0x1001181Bull;
+
+static const uint64_t P9N2_EX_10_L3_EDRAM_BANK_FAIL_SCOM_RD = 0x1501181Bull;
+
+static const uint64_t P9N2_EX_11_L3_EDRAM_BANK_FAIL_SCOM_RD = 0x15011C1Bull;
+
+static const uint64_t P9N2_EX_1_L3_EDRAM_BANK_FAIL_SCOM_RD = 0x10011C1Bull;
+
+static const uint64_t P9N2_EX_2_L3_EDRAM_BANK_FAIL_SCOM_RD = 0x1101181Bull;
+
+static const uint64_t P9N2_EX_3_L3_EDRAM_BANK_FAIL_SCOM_RD = 0x11011C1Bull;
+
+static const uint64_t P9N2_EX_4_L3_EDRAM_BANK_FAIL_SCOM_RD = 0x1201181Bull;
+
+static const uint64_t P9N2_EX_5_L3_EDRAM_BANK_FAIL_SCOM_RD = 0x12011C1Bull;
+
+static const uint64_t P9N2_EX_6_L3_EDRAM_BANK_FAIL_SCOM_RD = 0x1301181Bull;
+
+static const uint64_t P9N2_EX_7_L3_EDRAM_BANK_FAIL_SCOM_RD = 0x13011C1Bull;
+
+static const uint64_t P9N2_EX_8_L3_EDRAM_BANK_FAIL_SCOM_RD = 0x1401181Bull;
+
+static const uint64_t P9N2_EX_9_L3_EDRAM_BANK_FAIL_SCOM_RD = 0x14011C1Bull;
+
+static const uint64_t P9N2_EX_L3_EDRAM_BANK_FAIL_SCOM_RD = 0x1001181Bull;
+
+
+static const uint64_t P9N2_EQ_EDRAM_BANK_SOFT_DIS = 0x10011C0Bull;
+//DUPS: 10011C0B,
+static const uint64_t P9N2_EQ_0_EDRAM_BANK_SOFT_DIS = 0x10011C0Bull;
+//DUPS: 10011C0B,
+static const uint64_t P9N2_EQ_1_EDRAM_BANK_SOFT_DIS = 0x11011C0Bull;
+//DUPS: 11011C0B,
+static const uint64_t P9N2_EQ_2_EDRAM_BANK_SOFT_DIS = 0x12011C0Bull;
+//DUPS: 12011C0B,
+static const uint64_t P9N2_EQ_3_EDRAM_BANK_SOFT_DIS = 0x13011C0Bull;
+//DUPS: 13011C0B,
+static const uint64_t P9N2_EQ_4_EDRAM_BANK_SOFT_DIS = 0x14011C0Bull;
+//DUPS: 14011C0B,
+static const uint64_t P9N2_EQ_5_EDRAM_BANK_SOFT_DIS = 0x15011C0Bull;
+//DUPS: 15011C0B,
+static const uint64_t P9N2_EX_0_L3_EDRAM_BANK_SOFT_DIS = 0x1001180Bull;
+
+static const uint64_t P9N2_EX_10_L3_EDRAM_BANK_SOFT_DIS = 0x1501180Bull;
+
+static const uint64_t P9N2_EX_11_L3_EDRAM_BANK_SOFT_DIS = 0x15011C0Bull;
+
+static const uint64_t P9N2_EX_1_L3_EDRAM_BANK_SOFT_DIS = 0x10011C0Bull;
+
+static const uint64_t P9N2_EX_2_L3_EDRAM_BANK_SOFT_DIS = 0x1101180Bull;
+
+static const uint64_t P9N2_EX_3_L3_EDRAM_BANK_SOFT_DIS = 0x11011C0Bull;
+
+static const uint64_t P9N2_EX_4_L3_EDRAM_BANK_SOFT_DIS = 0x1201180Bull;
+
+static const uint64_t P9N2_EX_5_L3_EDRAM_BANK_SOFT_DIS = 0x12011C0Bull;
+
+static const uint64_t P9N2_EX_6_L3_EDRAM_BANK_SOFT_DIS = 0x1301180Bull;
+
+static const uint64_t P9N2_EX_7_L3_EDRAM_BANK_SOFT_DIS = 0x13011C0Bull;
+
+static const uint64_t P9N2_EX_8_L3_EDRAM_BANK_SOFT_DIS = 0x1401180Bull;
+
+static const uint64_t P9N2_EX_9_L3_EDRAM_BANK_SOFT_DIS = 0x14011C0Bull;
+
+static const uint64_t P9N2_EX_L3_EDRAM_BANK_SOFT_DIS = 0x1001180Bull;
+
+
+static const uint64_t P9N2_EQ_EDRAM_REG = 0x10011C0Cull;
+//DUPS: 10011C0C,
+static const uint64_t P9N2_EQ_0_EDRAM_REG = 0x10011C0Cull;
+//DUPS: 10011C0C,
+static const uint64_t P9N2_EQ_1_EDRAM_REG = 0x11011C0Cull;
+//DUPS: 11011C0C,
+static const uint64_t P9N2_EQ_2_EDRAM_REG = 0x12011C0Cull;
+//DUPS: 12011C0C,
+static const uint64_t P9N2_EQ_3_EDRAM_REG = 0x13011C0Cull;
+//DUPS: 13011C0C,
+static const uint64_t P9N2_EQ_4_EDRAM_REG = 0x14011C0Cull;
+//DUPS: 14011C0C,
+static const uint64_t P9N2_EQ_5_EDRAM_REG = 0x15011C0Cull;
+//DUPS: 15011C0C,
+static const uint64_t P9N2_EX_0_L3_EDRAM_REG = 0x1001180Cull;
+
+static const uint64_t P9N2_EX_10_L3_EDRAM_REG = 0x1501180Cull;
+
+static const uint64_t P9N2_EX_11_L3_EDRAM_REG = 0x15011C0Cull;
+
+static const uint64_t P9N2_EX_1_L3_EDRAM_REG = 0x10011C0Cull;
+
+static const uint64_t P9N2_EX_2_L3_EDRAM_REG = 0x1101180Cull;
+
+static const uint64_t P9N2_EX_3_L3_EDRAM_REG = 0x11011C0Cull;
+
+static const uint64_t P9N2_EX_4_L3_EDRAM_REG = 0x1201180Cull;
+
+static const uint64_t P9N2_EX_5_L3_EDRAM_REG = 0x12011C0Cull;
+
+static const uint64_t P9N2_EX_6_L3_EDRAM_REG = 0x1301180Cull;
+
+static const uint64_t P9N2_EX_7_L3_EDRAM_REG = 0x13011C0Cull;
+
+static const uint64_t P9N2_EX_8_L3_EDRAM_REG = 0x1401180Cull;
+
+static const uint64_t P9N2_EX_9_L3_EDRAM_REG = 0x14011C0Cull;
+
+static const uint64_t P9N2_EX_L3_EDRAM_REG = 0x1001180Cull;
+
+
+static const uint64_t P9N2_C_EDRAM_STATUS = 0x200F0029ull;
+
+static const uint64_t P9N2_C_0_EDRAM_STATUS = 0x200F0029ull;
+
+static const uint64_t P9N2_C_1_EDRAM_STATUS = 0x210F0029ull;
+
+static const uint64_t P9N2_C_2_EDRAM_STATUS = 0x220F0029ull;
+
+static const uint64_t P9N2_C_3_EDRAM_STATUS = 0x230F0029ull;
+
+static const uint64_t P9N2_C_4_EDRAM_STATUS = 0x240F0029ull;
+
+static const uint64_t P9N2_C_5_EDRAM_STATUS = 0x250F0029ull;
+
+static const uint64_t P9N2_C_6_EDRAM_STATUS = 0x260F0029ull;
+
+static const uint64_t P9N2_C_7_EDRAM_STATUS = 0x270F0029ull;
+
+static const uint64_t P9N2_C_8_EDRAM_STATUS = 0x280F0029ull;
+
+static const uint64_t P9N2_C_9_EDRAM_STATUS = 0x290F0029ull;
+
+static const uint64_t P9N2_C_10_EDRAM_STATUS = 0x2A0F0029ull;
+
+static const uint64_t P9N2_C_11_EDRAM_STATUS = 0x2B0F0029ull;
+
+static const uint64_t P9N2_C_12_EDRAM_STATUS = 0x2C0F0029ull;
+
+static const uint64_t P9N2_C_13_EDRAM_STATUS = 0x2D0F0029ull;
+
+static const uint64_t P9N2_C_14_EDRAM_STATUS = 0x2E0F0029ull;
+
+static const uint64_t P9N2_C_15_EDRAM_STATUS = 0x2F0F0029ull;
+
+static const uint64_t P9N2_C_16_EDRAM_STATUS = 0x300F0029ull;
+
+static const uint64_t P9N2_C_17_EDRAM_STATUS = 0x310F0029ull;
+
+static const uint64_t P9N2_C_18_EDRAM_STATUS = 0x320F0029ull;
+
+static const uint64_t P9N2_C_19_EDRAM_STATUS = 0x330F0029ull;
+
+static const uint64_t P9N2_C_20_EDRAM_STATUS = 0x340F0029ull;
+
+static const uint64_t P9N2_C_21_EDRAM_STATUS = 0x350F0029ull;
+
+static const uint64_t P9N2_C_22_EDRAM_STATUS = 0x360F0029ull;
+
+static const uint64_t P9N2_C_23_EDRAM_STATUS = 0x370F0029ull;
+
+static const uint64_t P9N2_EQ_EDRAM_STATUS = 0x100F0029ull;
+
+static const uint64_t P9N2_EQ_0_EDRAM_STATUS = 0x100F0029ull;
+
+static const uint64_t P9N2_EQ_1_EDRAM_STATUS = 0x110F0029ull;
+
+static const uint64_t P9N2_EQ_2_EDRAM_STATUS = 0x120F0029ull;
+
+static const uint64_t P9N2_EQ_3_EDRAM_STATUS = 0x130F0029ull;
+
+static const uint64_t P9N2_EQ_4_EDRAM_STATUS = 0x140F0029ull;
+
+static const uint64_t P9N2_EQ_5_EDRAM_STATUS = 0x150F0029ull;
+
+static const uint64_t P9N2_EX_EDRAM_STATUS = 0x200F0029ull;
+//DUPS: 210F0029,
+static const uint64_t P9N2_EX_0_EDRAM_STATUS = 0x200F0029ull;
+//DUPS: 210F0029,
+static const uint64_t P9N2_EX_1_EDRAM_STATUS = 0x220F0029ull;
+//DUPS: 220F0029,
+static const uint64_t P9N2_EX_2_EDRAM_STATUS = 0x240F0029ull;
+//DUPS: 250F0029,
+static const uint64_t P9N2_EX_3_EDRAM_STATUS = 0x260F0029ull;
+//DUPS: 270F0029,
+static const uint64_t P9N2_EX_4_EDRAM_STATUS = 0x280F0029ull;
+//DUPS: 290F0029,
+static const uint64_t P9N2_EX_5_EDRAM_STATUS = 0x2A0F0029ull;
+//DUPS: 2B0F0029,
+static const uint64_t P9N2_EX_6_EDRAM_STATUS = 0x2C0F0029ull;
+//DUPS: 2D0F0029,
+static const uint64_t P9N2_EX_7_EDRAM_STATUS = 0x2E0F0029ull;
+//DUPS: 2F0F0029,
+static const uint64_t P9N2_EX_8_EDRAM_STATUS = 0x300F0029ull;
+//DUPS: 310F0029,
+static const uint64_t P9N2_EX_9_EDRAM_STATUS = 0x320F0029ull;
+//DUPS: 330F0029,
+static const uint64_t P9N2_EX_10_EDRAM_STATUS = 0x340F0029ull;
+//DUPS: 350F0029,
+static const uint64_t P9N2_EX_11_EDRAM_STATUS = 0x360F0029ull;
+//DUPS: 370F0029,
+
+static const uint64_t P9N2_EQ_ED_RD_ERR_STAT_REG0 = 0x10011C19ull;
+//DUPS: 10011C19,
+static const uint64_t P9N2_EQ_0_ED_RD_ERR_STAT_REG0 = 0x10011C19ull;
+//DUPS: 10011C19,
+static const uint64_t P9N2_EQ_1_ED_RD_ERR_STAT_REG0 = 0x11011C19ull;
+//DUPS: 11011C19,
+static const uint64_t P9N2_EQ_2_ED_RD_ERR_STAT_REG0 = 0x12011C19ull;
+//DUPS: 12011C19,
+static const uint64_t P9N2_EQ_3_ED_RD_ERR_STAT_REG0 = 0x13011C19ull;
+//DUPS: 13011C19,
+static const uint64_t P9N2_EQ_4_ED_RD_ERR_STAT_REG0 = 0x14011C19ull;
+//DUPS: 14011C19,
+static const uint64_t P9N2_EQ_5_ED_RD_ERR_STAT_REG0 = 0x15011C19ull;
+//DUPS: 15011C19,
+static const uint64_t P9N2_EX_ED_RD_ERR_STAT_REG0 = 0x10011819ull;
+
+static const uint64_t P9N2_EX_0_ED_RD_ERR_STAT_REG0 = 0x10011819ull;
+
+static const uint64_t P9N2_EX_1_ED_RD_ERR_STAT_REG0 = 0x10011C19ull;
+
+static const uint64_t P9N2_EX_2_ED_RD_ERR_STAT_REG0 = 0x11011819ull;
+
+static const uint64_t P9N2_EX_3_ED_RD_ERR_STAT_REG0 = 0x11011C19ull;
+
+static const uint64_t P9N2_EX_4_ED_RD_ERR_STAT_REG0 = 0x12011819ull;
+
+static const uint64_t P9N2_EX_5_ED_RD_ERR_STAT_REG0 = 0x12011C19ull;
+
+static const uint64_t P9N2_EX_6_ED_RD_ERR_STAT_REG0 = 0x13011819ull;
+
+static const uint64_t P9N2_EX_7_ED_RD_ERR_STAT_REG0 = 0x13011C19ull;
+
+static const uint64_t P9N2_EX_8_ED_RD_ERR_STAT_REG0 = 0x14011819ull;
+
+static const uint64_t P9N2_EX_9_ED_RD_ERR_STAT_REG0 = 0x14011C19ull;
+
+static const uint64_t P9N2_EX_10_ED_RD_ERR_STAT_REG0 = 0x15011819ull;
+
+static const uint64_t P9N2_EX_11_ED_RD_ERR_STAT_REG0 = 0x15011C19ull;
+
+
+static const uint64_t P9N2_EQ_ED_RD_ERR_STAT_REG1 = 0x10011C1Aull;
+//DUPS: 10011C1A,
+static const uint64_t P9N2_EQ_0_ED_RD_ERR_STAT_REG1 = 0x10011C1Aull;
+//DUPS: 10011C1A,
+static const uint64_t P9N2_EQ_1_ED_RD_ERR_STAT_REG1 = 0x11011C1Aull;
+//DUPS: 11011C1A,
+static const uint64_t P9N2_EQ_2_ED_RD_ERR_STAT_REG1 = 0x12011C1Aull;
+//DUPS: 12011C1A,
+static const uint64_t P9N2_EQ_3_ED_RD_ERR_STAT_REG1 = 0x13011C1Aull;
+//DUPS: 13011C1A,
+static const uint64_t P9N2_EQ_4_ED_RD_ERR_STAT_REG1 = 0x14011C1Aull;
+//DUPS: 14011C1A,
+static const uint64_t P9N2_EQ_5_ED_RD_ERR_STAT_REG1 = 0x15011C1Aull;
+//DUPS: 15011C1A,
+static const uint64_t P9N2_EX_0_L3_ED_RD_ERR_STAT_REG1 = 0x1001181Aull;
+
+static const uint64_t P9N2_EX_10_L3_ED_RD_ERR_STAT_REG1 = 0x1501181Aull;
+
+static const uint64_t P9N2_EX_11_L3_ED_RD_ERR_STAT_REG1 = 0x15011C1Aull;
+
+static const uint64_t P9N2_EX_1_L3_ED_RD_ERR_STAT_REG1 = 0x10011C1Aull;
+
+static const uint64_t P9N2_EX_2_L3_ED_RD_ERR_STAT_REG1 = 0x1101181Aull;
+
+static const uint64_t P9N2_EX_3_L3_ED_RD_ERR_STAT_REG1 = 0x11011C1Aull;
+
+static const uint64_t P9N2_EX_4_L3_ED_RD_ERR_STAT_REG1 = 0x1201181Aull;
+
+static const uint64_t P9N2_EX_5_L3_ED_RD_ERR_STAT_REG1 = 0x12011C1Aull;
+
+static const uint64_t P9N2_EX_6_L3_ED_RD_ERR_STAT_REG1 = 0x1301181Aull;
+
+static const uint64_t P9N2_EX_7_L3_ED_RD_ERR_STAT_REG1 = 0x13011C1Aull;
+
+static const uint64_t P9N2_EX_8_L3_ED_RD_ERR_STAT_REG1 = 0x1401181Aull;
+
+static const uint64_t P9N2_EX_9_L3_ED_RD_ERR_STAT_REG1 = 0x14011C1Aull;
+
+static const uint64_t P9N2_EX_L3_ED_RD_ERR_STAT_REG1 = 0x1001181Aull;
+
+
+static const uint64_t P9N2_C_ERROR_REG = 0x200F001Full;
+
+static const uint64_t P9N2_C_0_ERROR_REG = 0x200F001Full;
+
+static const uint64_t P9N2_C_1_ERROR_REG = 0x210F001Full;
+
+static const uint64_t P9N2_C_2_ERROR_REG = 0x220F001Full;
+
+static const uint64_t P9N2_C_3_ERROR_REG = 0x230F001Full;
+
+static const uint64_t P9N2_C_4_ERROR_REG = 0x240F001Full;
+
+static const uint64_t P9N2_C_5_ERROR_REG = 0x250F001Full;
+
+static const uint64_t P9N2_C_6_ERROR_REG = 0x260F001Full;
+
+static const uint64_t P9N2_C_7_ERROR_REG = 0x270F001Full;
+
+static const uint64_t P9N2_C_8_ERROR_REG = 0x280F001Full;
+
+static const uint64_t P9N2_C_9_ERROR_REG = 0x290F001Full;
+
+static const uint64_t P9N2_C_10_ERROR_REG = 0x2A0F001Full;
+
+static const uint64_t P9N2_C_11_ERROR_REG = 0x2B0F001Full;
+
+static const uint64_t P9N2_C_12_ERROR_REG = 0x2C0F001Full;
+
+static const uint64_t P9N2_C_13_ERROR_REG = 0x2D0F001Full;
+
+static const uint64_t P9N2_C_14_ERROR_REG = 0x2E0F001Full;
+
+static const uint64_t P9N2_C_15_ERROR_REG = 0x2F0F001Full;
+
+static const uint64_t P9N2_C_16_ERROR_REG = 0x300F001Full;
+
+static const uint64_t P9N2_C_17_ERROR_REG = 0x310F001Full;
+
+static const uint64_t P9N2_C_18_ERROR_REG = 0x320F001Full;
+
+static const uint64_t P9N2_C_19_ERROR_REG = 0x330F001Full;
+
+static const uint64_t P9N2_C_20_ERROR_REG = 0x340F001Full;
+
+static const uint64_t P9N2_C_21_ERROR_REG = 0x350F001Full;
+
+static const uint64_t P9N2_C_22_ERROR_REG = 0x360F001Full;
+
+static const uint64_t P9N2_C_23_ERROR_REG = 0x370F001Full;
+
+static const uint64_t P9N2_EQ_ERROR_REG = 0x100F001Full;
+
+static const uint64_t P9N2_EQ_0_ERROR_REG = 0x100F001Full;
+
+static const uint64_t P9N2_EQ_1_ERROR_REG = 0x110F001Full;
+
+static const uint64_t P9N2_EQ_2_ERROR_REG = 0x120F001Full;
+
+static const uint64_t P9N2_EQ_3_ERROR_REG = 0x130F001Full;
+
+static const uint64_t P9N2_EQ_4_ERROR_REG = 0x140F001Full;
+
+static const uint64_t P9N2_EQ_5_ERROR_REG = 0x150F001Full;
+
+static const uint64_t P9N2_EX_ERROR_REG = 0x200F001Full;
+//DUPS: 210F001F,
+static const uint64_t P9N2_EX_0_ERROR_REG = 0x200F001Full;
+//DUPS: 210F001F,
+static const uint64_t P9N2_EX_1_ERROR_REG = 0x220F001Full;
+//DUPS: 220F001F,
+static const uint64_t P9N2_EX_2_ERROR_REG = 0x240F001Full;
+//DUPS: 250F001F,
+static const uint64_t P9N2_EX_3_ERROR_REG = 0x260F001Full;
+//DUPS: 270F001F,
+static const uint64_t P9N2_EX_4_ERROR_REG = 0x280F001Full;
+//DUPS: 290F001F,
+static const uint64_t P9N2_EX_5_ERROR_REG = 0x2A0F001Full;
+//DUPS: 2B0F001F,
+static const uint64_t P9N2_EX_6_ERROR_REG = 0x2C0F001Full;
+//DUPS: 2D0F001F,
+static const uint64_t P9N2_EX_7_ERROR_REG = 0x2E0F001Full;
+//DUPS: 2F0F001F,
+static const uint64_t P9N2_EX_8_ERROR_REG = 0x300F001Full;
+//DUPS: 310F001F,
+static const uint64_t P9N2_EX_9_ERROR_REG = 0x320F001Full;
+//DUPS: 330F001F,
+static const uint64_t P9N2_EX_10_ERROR_REG = 0x340F001Full;
+//DUPS: 350F001F,
+static const uint64_t P9N2_EX_11_ERROR_REG = 0x360F001Full;
+//DUPS: 370F001F,
+
+static const uint64_t P9N2_C_ERROR_STATUS = 0x2003000Full;
+
+static const uint64_t P9N2_C_0_ERROR_STATUS = 0x2003000Full;
+
+static const uint64_t P9N2_C_1_ERROR_STATUS = 0x2103000Full;
+
+static const uint64_t P9N2_C_2_ERROR_STATUS = 0x2203000Full;
+
+static const uint64_t P9N2_C_3_ERROR_STATUS = 0x2303000Full;
+
+static const uint64_t P9N2_C_4_ERROR_STATUS = 0x2403000Full;
+
+static const uint64_t P9N2_C_5_ERROR_STATUS = 0x2503000Full;
+
+static const uint64_t P9N2_C_6_ERROR_STATUS = 0x2603000Full;
+
+static const uint64_t P9N2_C_7_ERROR_STATUS = 0x2703000Full;
+
+static const uint64_t P9N2_C_8_ERROR_STATUS = 0x2803000Full;
+
+static const uint64_t P9N2_C_9_ERROR_STATUS = 0x2903000Full;
+
+static const uint64_t P9N2_C_10_ERROR_STATUS = 0x2A03000Full;
+
+static const uint64_t P9N2_C_11_ERROR_STATUS = 0x2B03000Full;
+
+static const uint64_t P9N2_C_12_ERROR_STATUS = 0x2C03000Full;
+
+static const uint64_t P9N2_C_13_ERROR_STATUS = 0x2D03000Full;
+
+static const uint64_t P9N2_C_14_ERROR_STATUS = 0x2E03000Full;
+
+static const uint64_t P9N2_C_15_ERROR_STATUS = 0x2F03000Full;
+
+static const uint64_t P9N2_C_16_ERROR_STATUS = 0x3003000Full;
+
+static const uint64_t P9N2_C_17_ERROR_STATUS = 0x3103000Full;
+
+static const uint64_t P9N2_C_18_ERROR_STATUS = 0x3203000Full;
+
+static const uint64_t P9N2_C_19_ERROR_STATUS = 0x3303000Full;
+
+static const uint64_t P9N2_C_20_ERROR_STATUS = 0x3403000Full;
+
+static const uint64_t P9N2_C_21_ERROR_STATUS = 0x3503000Full;
+
+static const uint64_t P9N2_C_22_ERROR_STATUS = 0x3603000Full;
+
+static const uint64_t P9N2_C_23_ERROR_STATUS = 0x3703000Full;
+
+static const uint64_t P9N2_EQ_ERROR_STATUS = 0x1003000Full;
+
+static const uint64_t P9N2_EQ_0_ERROR_STATUS = 0x1003000Full;
+
+static const uint64_t P9N2_EQ_1_ERROR_STATUS = 0x1103000Full;
+
+static const uint64_t P9N2_EQ_2_ERROR_STATUS = 0x1203000Full;
+
+static const uint64_t P9N2_EQ_3_ERROR_STATUS = 0x1303000Full;
+
+static const uint64_t P9N2_EQ_4_ERROR_STATUS = 0x1403000Full;
+
+static const uint64_t P9N2_EQ_5_ERROR_STATUS = 0x1503000Full;
+
+static const uint64_t P9N2_EX_ERROR_STATUS = 0x2003000Full;
+//DUPS: 2103000F,
+static const uint64_t P9N2_EX_0_ERROR_STATUS = 0x2003000Full;
+//DUPS: 2103000F,
+static const uint64_t P9N2_EX_1_ERROR_STATUS = 0x2203000Full;
+//DUPS: 2303000F,
+static const uint64_t P9N2_EX_2_ERROR_STATUS = 0x2403000Full;
+//DUPS: 2503000F,
+static const uint64_t P9N2_EX_3_ERROR_STATUS = 0x2603000Full;
+//DUPS: 2703000F,
+static const uint64_t P9N2_EX_4_ERROR_STATUS = 0x2803000Full;
+//DUPS: 2903000F,
+static const uint64_t P9N2_EX_5_ERROR_STATUS = 0x2A03000Full;
+//DUPS: 2B03000F,
+static const uint64_t P9N2_EX_6_ERROR_STATUS = 0x2C03000Full;
+//DUPS: 2D03000F,
+static const uint64_t P9N2_EX_7_ERROR_STATUS = 0x2F03000Full;
+//DUPS: 2F03000F,
+static const uint64_t P9N2_EX_8_ERROR_STATUS = 0x3003000Full;
+//DUPS: 3103000F,
+static const uint64_t P9N2_EX_9_ERROR_STATUS = 0x3203000Full;
+//DUPS: 3303000F,
+static const uint64_t P9N2_EX_10_ERROR_STATUS = 0x3403000Full;
+//DUPS: 3503000F,
+static const uint64_t P9N2_EX_11_ERROR_STATUS = 0x3603000Full;
+//DUPS: 3703000F,
+
+static const uint64_t P9N2_C_ERR_INJ_REG = 0x20010C04ull;
+//DUPS: 20010CBF,
+static const uint64_t P9N2_C_0_ERR_INJ_REG = 0x20010C04ull;
+//DUPS: 20010CBF,
+static const uint64_t P9N2_C_1_ERR_INJ_REG = 0x21010C04ull;
+//DUPS: 21010CBF,
+static const uint64_t P9N2_C_2_ERR_INJ_REG = 0x22010C04ull;
+//DUPS: 22010CBF,
+static const uint64_t P9N2_C_3_ERR_INJ_REG = 0x23010C04ull;
+//DUPS: 23010CBF,
+static const uint64_t P9N2_C_4_ERR_INJ_REG = 0x24010C04ull;
+//DUPS: 24010CBF,
+static const uint64_t P9N2_C_5_ERR_INJ_REG = 0x25010C04ull;
+//DUPS: 25010CBF,
+static const uint64_t P9N2_C_6_ERR_INJ_REG = 0x26010C04ull;
+//DUPS: 26010CBF,
+static const uint64_t P9N2_C_7_ERR_INJ_REG = 0x27010C04ull;
+//DUPS: 27010CBF,
+static const uint64_t P9N2_C_8_ERR_INJ_REG = 0x28010C04ull;
+//DUPS: 28010CBF,
+static const uint64_t P9N2_C_9_ERR_INJ_REG = 0x29010C04ull;
+//DUPS: 29010CBF,
+static const uint64_t P9N2_C_10_ERR_INJ_REG = 0x2A010C04ull;
+//DUPS: 2A010CBF,
+static const uint64_t P9N2_C_11_ERR_INJ_REG = 0x2B010C04ull;
+//DUPS: 2B010CBF,
+static const uint64_t P9N2_C_12_ERR_INJ_REG = 0x2C010C04ull;
+//DUPS: 2C010CBF,
+static const uint64_t P9N2_C_13_ERR_INJ_REG = 0x2D010C04ull;
+//DUPS: 2D010CBF,
+static const uint64_t P9N2_C_14_ERR_INJ_REG = 0x2E010C04ull;
+//DUPS: 2E010CBF,
+static const uint64_t P9N2_C_15_ERR_INJ_REG = 0x2F010C04ull;
+//DUPS: 2F010CBF,
+static const uint64_t P9N2_C_16_ERR_INJ_REG = 0x30010C04ull;
+//DUPS: 30010CBF,
+static const uint64_t P9N2_C_17_ERR_INJ_REG = 0x31010C04ull;
+//DUPS: 31010CBF,
+static const uint64_t P9N2_C_18_ERR_INJ_REG = 0x32010C04ull;
+//DUPS: 32010CBF,
+static const uint64_t P9N2_C_19_ERR_INJ_REG = 0x33010C04ull;
+//DUPS: 33010CBF,
+static const uint64_t P9N2_C_20_ERR_INJ_REG = 0x34010C04ull;
+//DUPS: 34010CBF,
+static const uint64_t P9N2_C_21_ERR_INJ_REG = 0x35010C04ull;
+//DUPS: 35010CBF,
+static const uint64_t P9N2_C_22_ERR_INJ_REG = 0x36010C04ull;
+//DUPS: 36010CBF,
+static const uint64_t P9N2_C_23_ERR_INJ_REG = 0x37010C04ull;
+//DUPS: 37010CBF,
+static const uint64_t P9N2_EQ_ERR_INJ_REG = 0x10010C0Cull;
+//DUPS: 1001180D, 10010C0C, 10011C0D,
+static const uint64_t P9N2_EQ_0_ERR_INJ_REG = 0x10010C0Cull;
+//DUPS: 1001180D, 10010C0C, 10011C0D,
+static const uint64_t P9N2_EQ_1_ERR_INJ_REG = 0x11010C0Cull;
+//DUPS: 1101180D, 11010C0C, 11011C0D,
+static const uint64_t P9N2_EQ_2_ERR_INJ_REG = 0x12010C0Cull;
+//DUPS: 1201180D, 12010C0C, 12011C0D,
+static const uint64_t P9N2_EQ_3_ERR_INJ_REG = 0x13010C0Cull;
+//DUPS: 1301180D, 13010C0C, 13011C0D,
+static const uint64_t P9N2_EQ_4_ERR_INJ_REG = 0x14010C0Cull;
+//DUPS: 1401180D, 14010C0C, 14011C0D,
+static const uint64_t P9N2_EQ_5_ERR_INJ_REG = 0x15010C0Cull;
+//DUPS: 1501180D, 15010C0C, 15011C0D,
+static const uint64_t P9N2_EX_ERR_INJ_REG = 0x20010CBFull;
+//DUPS: 21010CBF,
+static const uint64_t P9N2_EX_0_ERR_INJ_REG = 0x20010CBFull;
+//DUPS: 21010CBF,
+static const uint64_t P9N2_EX_1_ERR_INJ_REG = 0x22010CBFull;
+//DUPS: 23010CBF,
+static const uint64_t P9N2_EX_2_ERR_INJ_REG = 0x24010CBFull;
+//DUPS: 25010CBF,
+static const uint64_t P9N2_EX_3_ERR_INJ_REG = 0x26010CBFull;
+//DUPS: 27010CBF,
+static const uint64_t P9N2_EX_4_ERR_INJ_REG = 0x28010CBFull;
+//DUPS: 29010CBF,
+static const uint64_t P9N2_EX_5_ERR_INJ_REG = 0x2A010CBFull;
+//DUPS: 2B010CBF,
+static const uint64_t P9N2_EX_6_ERR_INJ_REG = 0x2C010CBFull;
+//DUPS: 2D010CBF,
+static const uint64_t P9N2_EX_7_ERR_INJ_REG = 0x2F010CBFull;
+//DUPS: 2F010CBF,
+static const uint64_t P9N2_EX_8_ERR_INJ_REG = 0x30010CBFull;
+//DUPS: 31010CBF,
+static const uint64_t P9N2_EX_9_ERR_INJ_REG = 0x32010CBFull;
+//DUPS: 33010CBF,
+static const uint64_t P9N2_EX_0_L2_ERR_INJ_REG = 0x20010C04ull;
+//DUPS: 21010C04, 1001080C,
+static const uint64_t P9N2_EX_0_L3_ERR_INJ_REG = 0x1001180Dull;
+
+static const uint64_t P9N2_EX_10_ERR_INJ_REG = 0x34010CBFull;
+//DUPS: 35010CBF,
+static const uint64_t P9N2_EX_11_ERR_INJ_REG = 0x36010CBFull;
+//DUPS: 37010CBF,
+static const uint64_t P9N2_EX_10_L2_ERR_INJ_REG = 0x34010C04ull;
+//DUPS: 35010C04, 1501080C,
+static const uint64_t P9N2_EX_10_L3_ERR_INJ_REG = 0x1501180Dull;
+
+static const uint64_t P9N2_EX_11_L2_ERR_INJ_REG = 0x15010C0Cull;
+//DUPS: 37010C04, 15010C0C,
+static const uint64_t P9N2_EX_11_L3_ERR_INJ_REG = 0x15011C0Dull;
+
+static const uint64_t P9N2_EX_1_L2_ERR_INJ_REG = 0x10010C0Cull;
+//DUPS: 23010C04, 10010C0C,
+static const uint64_t P9N2_EX_1_L3_ERR_INJ_REG = 0x10011C0Dull;
+
+static const uint64_t P9N2_EX_2_L2_ERR_INJ_REG = 0x24010C04ull;
+//DUPS: 25010C04, 1101080C,
+static const uint64_t P9N2_EX_2_L3_ERR_INJ_REG = 0x1101180Dull;
+
+static const uint64_t P9N2_EX_3_L2_ERR_INJ_REG = 0x11010C0Cull;
+//DUPS: 27010C04, 11010C0C,
+static const uint64_t P9N2_EX_3_L3_ERR_INJ_REG = 0x11011C0Dull;
+
+static const uint64_t P9N2_EX_4_L2_ERR_INJ_REG = 0x28010C04ull;
+//DUPS: 29010C04, 1201080C,
+static const uint64_t P9N2_EX_4_L3_ERR_INJ_REG = 0x1201180Dull;
+
+static const uint64_t P9N2_EX_5_L2_ERR_INJ_REG = 0x2A010C04ull;
+//DUPS: 2B010C04, 12010C0C,
+static const uint64_t P9N2_EX_5_L3_ERR_INJ_REG = 0x12011C0Dull;
+
+static const uint64_t P9N2_EX_6_L2_ERR_INJ_REG = 0x2C010C04ull;
+//DUPS: 2D010C04, 1301080C,
+static const uint64_t P9N2_EX_6_L3_ERR_INJ_REG = 0x1301180Dull;
+
+static const uint64_t P9N2_EX_7_L2_ERR_INJ_REG = 0x2F010C04ull;
+//DUPS: 2F010C04, 13010C0C,
+static const uint64_t P9N2_EX_7_L3_ERR_INJ_REG = 0x13011C0Dull;
+
+static const uint64_t P9N2_EX_8_L2_ERR_INJ_REG = 0x30010C04ull;
+//DUPS: 31010C04, 1401080C,
+static const uint64_t P9N2_EX_8_L3_ERR_INJ_REG = 0x1401180Dull;
+
+static const uint64_t P9N2_EX_9_L2_ERR_INJ_REG = 0x14010C0Cull;
+//DUPS: 33010C04, 14010C0C,
+static const uint64_t P9N2_EX_9_L3_ERR_INJ_REG = 0x14011C0Dull;
+
+static const uint64_t P9N2_EX_L2_ERR_INJ_REG = 0x20010C04ull;
+//DUPS: 21010C04, 1001080C,
+static const uint64_t P9N2_EX_L3_ERR_INJ_REG = 0x1001180Dull;
+
+
+static const uint64_t P9N2_EQ_ERR_RPT0 = 0x10010C12ull;
+//DUPS: 10010C12,
+static const uint64_t P9N2_EQ_0_ERR_RPT0 = 0x10010C12ull;
+//DUPS: 10010C12,
+static const uint64_t P9N2_EQ_1_ERR_RPT0 = 0x11010C12ull;
+//DUPS: 11010C12,
+static const uint64_t P9N2_EQ_2_ERR_RPT0 = 0x12010C12ull;
+//DUPS: 12010C12,
+static const uint64_t P9N2_EQ_3_ERR_RPT0 = 0x13010C12ull;
+//DUPS: 13010C12,
+static const uint64_t P9N2_EQ_4_ERR_RPT0 = 0x14010C12ull;
+//DUPS: 14010C12,
+static const uint64_t P9N2_EQ_5_ERR_RPT0 = 0x15010C12ull;
+//DUPS: 15010C12,
+static const uint64_t P9N2_EX_0_L2_ERR_RPT0 = 0x10010812ull;
+
+static const uint64_t P9N2_EX_10_L2_ERR_RPT0 = 0x15010812ull;
+
+static const uint64_t P9N2_EX_11_L2_ERR_RPT0 = 0x15010C12ull;
+
+static const uint64_t P9N2_EX_1_L2_ERR_RPT0 = 0x10010C12ull;
+
+static const uint64_t P9N2_EX_2_L2_ERR_RPT0 = 0x11010812ull;
+
+static const uint64_t P9N2_EX_3_L2_ERR_RPT0 = 0x11010C12ull;
+
+static const uint64_t P9N2_EX_4_L2_ERR_RPT0 = 0x12010812ull;
+
+static const uint64_t P9N2_EX_5_L2_ERR_RPT0 = 0x12010C12ull;
+
+static const uint64_t P9N2_EX_6_L2_ERR_RPT0 = 0x13010812ull;
+
+static const uint64_t P9N2_EX_7_L2_ERR_RPT0 = 0x13010C12ull;
+
+static const uint64_t P9N2_EX_8_L2_ERR_RPT0 = 0x14010812ull;
+
+static const uint64_t P9N2_EX_9_L2_ERR_RPT0 = 0x14010C12ull;
+
+static const uint64_t P9N2_EX_L2_ERR_RPT0 = 0x10010812ull;
+
+
+static const uint64_t P9N2_EQ_ERR_RPT1 = 0x10010C13ull;
+//DUPS: 10010C13,
+static const uint64_t P9N2_EQ_0_ERR_RPT1 = 0x10010C13ull;
+//DUPS: 10010C13,
+static const uint64_t P9N2_EQ_1_ERR_RPT1 = 0x11010C13ull;
+//DUPS: 11010C13,
+static const uint64_t P9N2_EQ_2_ERR_RPT1 = 0x12010C13ull;
+//DUPS: 12010C13,
+static const uint64_t P9N2_EQ_3_ERR_RPT1 = 0x13010C13ull;
+//DUPS: 13010C13,
+static const uint64_t P9N2_EQ_4_ERR_RPT1 = 0x14010C13ull;
+//DUPS: 14010C13,
+static const uint64_t P9N2_EQ_5_ERR_RPT1 = 0x15010C13ull;
+//DUPS: 15010C13,
+static const uint64_t P9N2_EX_0_L2_ERR_RPT1 = 0x10010813ull;
+
+static const uint64_t P9N2_EX_10_L2_ERR_RPT1 = 0x15010813ull;
+
+static const uint64_t P9N2_EX_11_L2_ERR_RPT1 = 0x15010C13ull;
+
+static const uint64_t P9N2_EX_1_L2_ERR_RPT1 = 0x10010C13ull;
+
+static const uint64_t P9N2_EX_2_L2_ERR_RPT1 = 0x11010813ull;
+
+static const uint64_t P9N2_EX_3_L2_ERR_RPT1 = 0x11010C13ull;
+
+static const uint64_t P9N2_EX_4_L2_ERR_RPT1 = 0x12010813ull;
+
+static const uint64_t P9N2_EX_5_L2_ERR_RPT1 = 0x12010C13ull;
+
+static const uint64_t P9N2_EX_6_L2_ERR_RPT1 = 0x13010813ull;
+
+static const uint64_t P9N2_EX_7_L2_ERR_RPT1 = 0x13010C13ull;
+
+static const uint64_t P9N2_EX_8_L2_ERR_RPT1 = 0x14010813ull;
+
+static const uint64_t P9N2_EX_9_L2_ERR_RPT1 = 0x14010C13ull;
+
+static const uint64_t P9N2_EX_L2_ERR_RPT1 = 0x10010813ull;
+
+
+static const uint64_t P9N2_EQ_ERR_RPT_REG = 0x1001100Eull;
+//DUPS: 1001140E,
+static const uint64_t P9N2_EQ_0_ERR_RPT_REG = 0x1001100Eull;
+//DUPS: 1001140E,
+static const uint64_t P9N2_EQ_1_ERR_RPT_REG = 0x1101100Eull;
+//DUPS: 1101140E,
+static const uint64_t P9N2_EQ_2_ERR_RPT_REG = 0x1201100Eull;
+//DUPS: 1201140E,
+static const uint64_t P9N2_EQ_3_ERR_RPT_REG = 0x1301100Eull;
+//DUPS: 1301140E,
+static const uint64_t P9N2_EQ_4_ERR_RPT_REG = 0x1401100Eull;
+//DUPS: 1401140E,
+static const uint64_t P9N2_EQ_5_ERR_RPT_REG = 0x1501100Eull;
+//DUPS: 1501140E,
+static const uint64_t P9N2_EX_ERR_RPT_REG = 0x1001100Eull;
+
+static const uint64_t P9N2_EX_0_ERR_RPT_REG = 0x1001100Eull;
+
+static const uint64_t P9N2_EX_1_ERR_RPT_REG = 0x1001140Eull;
+
+static const uint64_t P9N2_EX_2_ERR_RPT_REG = 0x1101100Eull;
+
+static const uint64_t P9N2_EX_3_ERR_RPT_REG = 0x1101140Eull;
+
+static const uint64_t P9N2_EX_4_ERR_RPT_REG = 0x1201100Eull;
+
+static const uint64_t P9N2_EX_5_ERR_RPT_REG = 0x1201140Eull;
+
+static const uint64_t P9N2_EX_6_ERR_RPT_REG = 0x1301100Eull;
+
+static const uint64_t P9N2_EX_7_ERR_RPT_REG = 0x1301140Eull;
+
+static const uint64_t P9N2_EX_8_ERR_RPT_REG = 0x1401100Eull;
+
+static const uint64_t P9N2_EX_9_ERR_RPT_REG = 0x1401140Eull;
+
+static const uint64_t P9N2_EX_10_ERR_RPT_REG = 0x1501100Eull;
+
+static const uint64_t P9N2_EX_11_ERR_RPT_REG = 0x1501140Eull;
+
+
+static const uint64_t P9N2_C_ERR_STATUS_REG = 0x20050013ull;
+
+static const uint64_t P9N2_C_0_ERR_STATUS_REG = 0x20050013ull;
+
+static const uint64_t P9N2_C_1_ERR_STATUS_REG = 0x21050013ull;
+
+static const uint64_t P9N2_C_2_ERR_STATUS_REG = 0x22050013ull;
+
+static const uint64_t P9N2_C_3_ERR_STATUS_REG = 0x23050013ull;
+
+static const uint64_t P9N2_C_4_ERR_STATUS_REG = 0x24050013ull;
+
+static const uint64_t P9N2_C_5_ERR_STATUS_REG = 0x25050013ull;
+
+static const uint64_t P9N2_C_6_ERR_STATUS_REG = 0x26050013ull;
+
+static const uint64_t P9N2_C_7_ERR_STATUS_REG = 0x27050013ull;
+
+static const uint64_t P9N2_C_8_ERR_STATUS_REG = 0x28050013ull;
+
+static const uint64_t P9N2_C_9_ERR_STATUS_REG = 0x29050013ull;
+
+static const uint64_t P9N2_C_10_ERR_STATUS_REG = 0x2A050013ull;
+
+static const uint64_t P9N2_C_11_ERR_STATUS_REG = 0x2B050013ull;
+
+static const uint64_t P9N2_C_12_ERR_STATUS_REG = 0x2C050013ull;
+
+static const uint64_t P9N2_C_13_ERR_STATUS_REG = 0x2D050013ull;
+
+static const uint64_t P9N2_C_14_ERR_STATUS_REG = 0x2E050013ull;
+
+static const uint64_t P9N2_C_15_ERR_STATUS_REG = 0x2F050013ull;
+
+static const uint64_t P9N2_C_16_ERR_STATUS_REG = 0x30050013ull;
+
+static const uint64_t P9N2_C_17_ERR_STATUS_REG = 0x31050013ull;
+
+static const uint64_t P9N2_C_18_ERR_STATUS_REG = 0x32050013ull;
+
+static const uint64_t P9N2_C_19_ERR_STATUS_REG = 0x33050013ull;
+
+static const uint64_t P9N2_C_20_ERR_STATUS_REG = 0x34050013ull;
+
+static const uint64_t P9N2_C_21_ERR_STATUS_REG = 0x35050013ull;
+
+static const uint64_t P9N2_C_22_ERR_STATUS_REG = 0x36050013ull;
+
+static const uint64_t P9N2_C_23_ERR_STATUS_REG = 0x37050013ull;
+
+static const uint64_t P9N2_EQ_ERR_STATUS_REG = 0x10050013ull;
+
+static const uint64_t P9N2_EQ_0_ERR_STATUS_REG = 0x10050013ull;
+
+static const uint64_t P9N2_EQ_1_ERR_STATUS_REG = 0x11050013ull;
+
+static const uint64_t P9N2_EQ_2_ERR_STATUS_REG = 0x12050013ull;
+
+static const uint64_t P9N2_EQ_3_ERR_STATUS_REG = 0x13050013ull;
+
+static const uint64_t P9N2_EQ_4_ERR_STATUS_REG = 0x14050013ull;
+
+static const uint64_t P9N2_EQ_5_ERR_STATUS_REG = 0x15050013ull;
+
+static const uint64_t P9N2_EX_ERR_STATUS_REG = 0x20050013ull;
+//DUPS: 21050013,
+static const uint64_t P9N2_EX_0_ERR_STATUS_REG = 0x20050013ull;
+//DUPS: 21050013,
+static const uint64_t P9N2_EX_1_ERR_STATUS_REG = 0x22050013ull;
+//DUPS: 23050013,
+static const uint64_t P9N2_EX_2_ERR_STATUS_REG = 0x24050013ull;
+//DUPS: 25050013,
+static const uint64_t P9N2_EX_3_ERR_STATUS_REG = 0x26050013ull;
+//DUPS: 27050013,
+static const uint64_t P9N2_EX_4_ERR_STATUS_REG = 0x28050013ull;
+//DUPS: 29050013,
+static const uint64_t P9N2_EX_5_ERR_STATUS_REG = 0x2A050013ull;
+//DUPS: 2B050013,
+static const uint64_t P9N2_EX_6_ERR_STATUS_REG = 0x2C050013ull;
+//DUPS: 2D050013,
+static const uint64_t P9N2_EX_7_ERR_STATUS_REG = 0x2F050013ull;
+//DUPS: 2F050013,
+static const uint64_t P9N2_EX_8_ERR_STATUS_REG = 0x30050013ull;
+//DUPS: 31050013,
+static const uint64_t P9N2_EX_9_ERR_STATUS_REG = 0x32050013ull;
+//DUPS: 33050013,
+static const uint64_t P9N2_EX_10_ERR_STATUS_REG = 0x34050013ull;
+//DUPS: 35050013,
+static const uint64_t P9N2_EX_11_ERR_STATUS_REG = 0x36050013ull;
+//DUPS: 37050013,
+
+static const uint64_t P9N2_EQ_FIR_ACTION0_REG = 0x10010C06ull;
+//DUPS: 10011806, 10011006, 10010C06, 10011C06, 10011406,
+static const uint64_t P9N2_EQ_0_FIR_ACTION0_REG = 0x10010C06ull;
+//DUPS: 10011806, 10011006, 10010C06, 10011C06, 10011406,
+static const uint64_t P9N2_EQ_1_FIR_ACTION0_REG = 0x11010C06ull;
+//DUPS: 11011806, 11011006, 11010C06, 11011C06, 11011406,
+static const uint64_t P9N2_EQ_2_FIR_ACTION0_REG = 0x12010C06ull;
+//DUPS: 12011806, 12011006, 12010C06, 12011C06, 12011406,
+static const uint64_t P9N2_EQ_3_FIR_ACTION0_REG = 0x13010C06ull;
+//DUPS: 13011806, 13011006, 13010C06, 13011C06, 13011406,
+static const uint64_t P9N2_EQ_4_FIR_ACTION0_REG = 0x14010C06ull;
+//DUPS: 14011806, 14011006, 14010C06, 14011C06, 14011406,
+static const uint64_t P9N2_EQ_5_FIR_ACTION0_REG = 0x15010C06ull;
+//DUPS: 15011806, 15011006, 15010C06, 15011C06, 15011406,
+static const uint64_t P9N2_EX_FIR_ACTION0_REG = 0x10011006ull;
+
+static const uint64_t P9N2_EX_0_FIR_ACTION0_REG = 0x10011006ull;
+
+static const uint64_t P9N2_EX_1_FIR_ACTION0_REG = 0x10011406ull;
+
+static const uint64_t P9N2_EX_2_FIR_ACTION0_REG = 0x11011006ull;
+
+static const uint64_t P9N2_EX_3_FIR_ACTION0_REG = 0x11011406ull;
+
+static const uint64_t P9N2_EX_4_FIR_ACTION0_REG = 0x12011006ull;
+
+static const uint64_t P9N2_EX_5_FIR_ACTION0_REG = 0x12011406ull;
+
+static const uint64_t P9N2_EX_6_FIR_ACTION0_REG = 0x13011006ull;
+
+static const uint64_t P9N2_EX_7_FIR_ACTION0_REG = 0x13011406ull;
+
+static const uint64_t P9N2_EX_8_FIR_ACTION0_REG = 0x14011006ull;
+
+static const uint64_t P9N2_EX_9_FIR_ACTION0_REG = 0x14011406ull;
+
+static const uint64_t P9N2_EX_0_L2_FIR_ACTION0_REG = 0x10010806ull;
+
+static const uint64_t P9N2_EX_0_L3_FIR_ACTION0_REG = 0x10011806ull;
+
+static const uint64_t P9N2_EX_10_FIR_ACTION0_REG = 0x15011006ull;
+
+static const uint64_t P9N2_EX_11_FIR_ACTION0_REG = 0x15011406ull;
+
+static const uint64_t P9N2_EX_10_L2_FIR_ACTION0_REG = 0x15010806ull;
+
+static const uint64_t P9N2_EX_10_L3_FIR_ACTION0_REG = 0x15011806ull;
+
+static const uint64_t P9N2_EX_11_L2_FIR_ACTION0_REG = 0x15010C06ull;
+
+static const uint64_t P9N2_EX_11_L3_FIR_ACTION0_REG = 0x15011C06ull;
+
+static const uint64_t P9N2_EX_1_L2_FIR_ACTION0_REG = 0x10010C06ull;
+
+static const uint64_t P9N2_EX_1_L3_FIR_ACTION0_REG = 0x10011C06ull;
+
+static const uint64_t P9N2_EX_2_L2_FIR_ACTION0_REG = 0x11010806ull;
+
+static const uint64_t P9N2_EX_2_L3_FIR_ACTION0_REG = 0x11011806ull;
+
+static const uint64_t P9N2_EX_3_L2_FIR_ACTION0_REG = 0x11010C06ull;
+
+static const uint64_t P9N2_EX_3_L3_FIR_ACTION0_REG = 0x11011C06ull;
+
+static const uint64_t P9N2_EX_4_L2_FIR_ACTION0_REG = 0x12010806ull;
+
+static const uint64_t P9N2_EX_4_L3_FIR_ACTION0_REG = 0x12011806ull;
+
+static const uint64_t P9N2_EX_5_L2_FIR_ACTION0_REG = 0x12010C06ull;
+
+static const uint64_t P9N2_EX_5_L3_FIR_ACTION0_REG = 0x12011C06ull;
+
+static const uint64_t P9N2_EX_6_L2_FIR_ACTION0_REG = 0x13010806ull;
+
+static const uint64_t P9N2_EX_6_L3_FIR_ACTION0_REG = 0x13011806ull;
+
+static const uint64_t P9N2_EX_7_L2_FIR_ACTION0_REG = 0x13010C06ull;
+
+static const uint64_t P9N2_EX_7_L3_FIR_ACTION0_REG = 0x13011C06ull;
+
+static const uint64_t P9N2_EX_8_L2_FIR_ACTION0_REG = 0x14010806ull;
+
+static const uint64_t P9N2_EX_8_L3_FIR_ACTION0_REG = 0x14011806ull;
+
+static const uint64_t P9N2_EX_9_L2_FIR_ACTION0_REG = 0x14010C06ull;
+
+static const uint64_t P9N2_EX_9_L3_FIR_ACTION0_REG = 0x14011C06ull;
+
+static const uint64_t P9N2_EX_L2_FIR_ACTION0_REG = 0x10010806ull;
+
+static const uint64_t P9N2_EX_L3_FIR_ACTION0_REG = 0x10011806ull;
+
+
+static const uint64_t P9N2_EQ_FIR_ACTION1_REG = 0x10010C07ull;
+//DUPS: 10011807, 10011007, 10010C07, 10011C07, 10011407,
+static const uint64_t P9N2_EQ_0_FIR_ACTION1_REG = 0x10010C07ull;
+//DUPS: 10011807, 10011007, 10010C07, 10011C07, 10011407,
+static const uint64_t P9N2_EQ_1_FIR_ACTION1_REG = 0x11010C07ull;
+//DUPS: 11011807, 11011007, 11010C07, 11011C07, 11011407,
+static const uint64_t P9N2_EQ_2_FIR_ACTION1_REG = 0x12010C07ull;
+//DUPS: 12011807, 12011007, 12010C07, 12011C07, 12011407,
+static const uint64_t P9N2_EQ_3_FIR_ACTION1_REG = 0x13010C07ull;
+//DUPS: 13011807, 13011007, 13010C07, 13011C07, 13011407,
+static const uint64_t P9N2_EQ_4_FIR_ACTION1_REG = 0x14010C07ull;
+//DUPS: 14011807, 14011007, 14010C07, 14011C07, 14011407,
+static const uint64_t P9N2_EQ_5_FIR_ACTION1_REG = 0x15010C07ull;
+//DUPS: 15011807, 15011007, 15010C07, 15011C07, 15011407,
+static const uint64_t P9N2_EX_FIR_ACTION1_REG = 0x10011007ull;
+
+static const uint64_t P9N2_EX_0_FIR_ACTION1_REG = 0x10011007ull;
+
+static const uint64_t P9N2_EX_1_FIR_ACTION1_REG = 0x10011407ull;
+
+static const uint64_t P9N2_EX_2_FIR_ACTION1_REG = 0x11011007ull;
+
+static const uint64_t P9N2_EX_3_FIR_ACTION1_REG = 0x11011407ull;
+
+static const uint64_t P9N2_EX_4_FIR_ACTION1_REG = 0x12011007ull;
+
+static const uint64_t P9N2_EX_5_FIR_ACTION1_REG = 0x12011407ull;
+
+static const uint64_t P9N2_EX_6_FIR_ACTION1_REG = 0x13011007ull;
+
+static const uint64_t P9N2_EX_7_FIR_ACTION1_REG = 0x13011407ull;
+
+static const uint64_t P9N2_EX_8_FIR_ACTION1_REG = 0x14011007ull;
+
+static const uint64_t P9N2_EX_9_FIR_ACTION1_REG = 0x14011407ull;
+
+static const uint64_t P9N2_EX_0_L2_FIR_ACTION1_REG = 0x10010807ull;
+
+static const uint64_t P9N2_EX_0_L3_FIR_ACTION1_REG = 0x10011807ull;
+
+static const uint64_t P9N2_EX_10_FIR_ACTION1_REG = 0x15011007ull;
+
+static const uint64_t P9N2_EX_11_FIR_ACTION1_REG = 0x15011407ull;
+
+static const uint64_t P9N2_EX_10_L2_FIR_ACTION1_REG = 0x15010807ull;
+
+static const uint64_t P9N2_EX_10_L3_FIR_ACTION1_REG = 0x15011807ull;
+
+static const uint64_t P9N2_EX_11_L2_FIR_ACTION1_REG = 0x15010C07ull;
+
+static const uint64_t P9N2_EX_11_L3_FIR_ACTION1_REG = 0x15011C07ull;
+
+static const uint64_t P9N2_EX_1_L2_FIR_ACTION1_REG = 0x10010C07ull;
+
+static const uint64_t P9N2_EX_1_L3_FIR_ACTION1_REG = 0x10011C07ull;
+
+static const uint64_t P9N2_EX_2_L2_FIR_ACTION1_REG = 0x11010807ull;
+
+static const uint64_t P9N2_EX_2_L3_FIR_ACTION1_REG = 0x11011807ull;
+
+static const uint64_t P9N2_EX_3_L2_FIR_ACTION1_REG = 0x11010C07ull;
+
+static const uint64_t P9N2_EX_3_L3_FIR_ACTION1_REG = 0x11011C07ull;
+
+static const uint64_t P9N2_EX_4_L2_FIR_ACTION1_REG = 0x12010807ull;
+
+static const uint64_t P9N2_EX_4_L3_FIR_ACTION1_REG = 0x12011807ull;
+
+static const uint64_t P9N2_EX_5_L2_FIR_ACTION1_REG = 0x12010C07ull;
+
+static const uint64_t P9N2_EX_5_L3_FIR_ACTION1_REG = 0x12011C07ull;
+
+static const uint64_t P9N2_EX_6_L2_FIR_ACTION1_REG = 0x13010807ull;
+
+static const uint64_t P9N2_EX_6_L3_FIR_ACTION1_REG = 0x13011807ull;
+
+static const uint64_t P9N2_EX_7_L2_FIR_ACTION1_REG = 0x13010C07ull;
+
+static const uint64_t P9N2_EX_7_L3_FIR_ACTION1_REG = 0x13011C07ull;
+
+static const uint64_t P9N2_EX_8_L2_FIR_ACTION1_REG = 0x14010807ull;
+
+static const uint64_t P9N2_EX_8_L3_FIR_ACTION1_REG = 0x14011807ull;
+
+static const uint64_t P9N2_EX_9_L2_FIR_ACTION1_REG = 0x14010C07ull;
+
+static const uint64_t P9N2_EX_9_L3_FIR_ACTION1_REG = 0x14011C07ull;
+
+static const uint64_t P9N2_EX_L2_FIR_ACTION1_REG = 0x10010807ull;
+
+static const uint64_t P9N2_EX_L3_FIR_ACTION1_REG = 0x10011807ull;
+
+
+static const uint64_t P9N2_C_FIR_ERR_INJ = 0x20010A4Dull;
+
+static const uint64_t P9N2_C_0_FIR_ERR_INJ = 0x20010A4Dull;
+
+static const uint64_t P9N2_C_1_FIR_ERR_INJ = 0x21010A4Dull;
+
+static const uint64_t P9N2_C_2_FIR_ERR_INJ = 0x22010A4Dull;
+
+static const uint64_t P9N2_C_3_FIR_ERR_INJ = 0x23010A4Dull;
+
+static const uint64_t P9N2_C_4_FIR_ERR_INJ = 0x24010A4Dull;
+
+static const uint64_t P9N2_C_5_FIR_ERR_INJ = 0x25010A4Dull;
+
+static const uint64_t P9N2_C_6_FIR_ERR_INJ = 0x26010A4Dull;
+
+static const uint64_t P9N2_C_7_FIR_ERR_INJ = 0x27010A4Dull;
+
+static const uint64_t P9N2_C_8_FIR_ERR_INJ = 0x28010A4Dull;
+
+static const uint64_t P9N2_C_9_FIR_ERR_INJ = 0x29010A4Dull;
+
+static const uint64_t P9N2_C_10_FIR_ERR_INJ = 0x2A010A4Dull;
+
+static const uint64_t P9N2_C_11_FIR_ERR_INJ = 0x2B010A4Dull;
+
+static const uint64_t P9N2_C_12_FIR_ERR_INJ = 0x2C010A4Dull;
+
+static const uint64_t P9N2_C_13_FIR_ERR_INJ = 0x2D010A4Dull;
+
+static const uint64_t P9N2_C_14_FIR_ERR_INJ = 0x2E010A4Dull;
+
+static const uint64_t P9N2_C_15_FIR_ERR_INJ = 0x2F010A4Dull;
+
+static const uint64_t P9N2_C_16_FIR_ERR_INJ = 0x30010A4Dull;
+
+static const uint64_t P9N2_C_17_FIR_ERR_INJ = 0x31010A4Dull;
+
+static const uint64_t P9N2_C_18_FIR_ERR_INJ = 0x32010A4Dull;
+
+static const uint64_t P9N2_C_19_FIR_ERR_INJ = 0x33010A4Dull;
+
+static const uint64_t P9N2_C_20_FIR_ERR_INJ = 0x34010A4Dull;
+
+static const uint64_t P9N2_C_21_FIR_ERR_INJ = 0x35010A4Dull;
+
+static const uint64_t P9N2_C_22_FIR_ERR_INJ = 0x36010A4Dull;
+
+static const uint64_t P9N2_C_23_FIR_ERR_INJ = 0x37010A4Dull;
+
+static const uint64_t P9N2_EX_0_L2_FIR_ERR_INJ = 0x20010A4Dull;
+//DUPS: 21010A4D,
+static const uint64_t P9N2_EX_10_L2_FIR_ERR_INJ = 0x34010A4Dull;
+//DUPS: 35010A4D,
+static const uint64_t P9N2_EX_11_L2_FIR_ERR_INJ = 0x36010A4Dull;
+//DUPS: 37010A4D,
+static const uint64_t P9N2_EX_1_L2_FIR_ERR_INJ = 0x22010A4Dull;
+//DUPS: 23010A4D,
+static const uint64_t P9N2_EX_2_L2_FIR_ERR_INJ = 0x24010A4Dull;
+//DUPS: 25010A4D,
+static const uint64_t P9N2_EX_3_L2_FIR_ERR_INJ = 0x26010A4Dull;
+//DUPS: 27010A4D,
+static const uint64_t P9N2_EX_4_L2_FIR_ERR_INJ = 0x28010A4Dull;
+//DUPS: 29010A4D,
+static const uint64_t P9N2_EX_5_L2_FIR_ERR_INJ = 0x2A010A4Dull;
+//DUPS: 2B010A4D,
+static const uint64_t P9N2_EX_6_L2_FIR_ERR_INJ = 0x2C010A4Dull;
+//DUPS: 2D010A4D,
+static const uint64_t P9N2_EX_7_L2_FIR_ERR_INJ = 0x2F010A4Dull;
+//DUPS: 2F010A4D,
+static const uint64_t P9N2_EX_8_L2_FIR_ERR_INJ = 0x30010A4Dull;
+//DUPS: 31010A4D,
+static const uint64_t P9N2_EX_9_L2_FIR_ERR_INJ = 0x32010A4Dull;
+//DUPS: 33010A4D,
+static const uint64_t P9N2_EX_L2_FIR_ERR_INJ = 0x20010A4Dull;
+//DUPS: 21010A4D,
+
+static const uint64_t P9N2_C_FIR_HOLD_OUT = 0x20010A51ull;
+
+static const uint64_t P9N2_C_0_FIR_HOLD_OUT = 0x20010A51ull;
+
+static const uint64_t P9N2_C_1_FIR_HOLD_OUT = 0x21010A51ull;
+
+static const uint64_t P9N2_C_2_FIR_HOLD_OUT = 0x22010A51ull;
+
+static const uint64_t P9N2_C_3_FIR_HOLD_OUT = 0x23010A51ull;
+
+static const uint64_t P9N2_C_4_FIR_HOLD_OUT = 0x24010A51ull;
+
+static const uint64_t P9N2_C_5_FIR_HOLD_OUT = 0x25010A51ull;
+
+static const uint64_t P9N2_C_6_FIR_HOLD_OUT = 0x26010A51ull;
+
+static const uint64_t P9N2_C_7_FIR_HOLD_OUT = 0x27010A51ull;
+
+static const uint64_t P9N2_C_8_FIR_HOLD_OUT = 0x28010A51ull;
+
+static const uint64_t P9N2_C_9_FIR_HOLD_OUT = 0x29010A51ull;
+
+static const uint64_t P9N2_C_10_FIR_HOLD_OUT = 0x2A010A51ull;
+
+static const uint64_t P9N2_C_11_FIR_HOLD_OUT = 0x2B010A51ull;
+
+static const uint64_t P9N2_C_12_FIR_HOLD_OUT = 0x2C010A51ull;
+
+static const uint64_t P9N2_C_13_FIR_HOLD_OUT = 0x2D010A51ull;
+
+static const uint64_t P9N2_C_14_FIR_HOLD_OUT = 0x2E010A51ull;
+
+static const uint64_t P9N2_C_15_FIR_HOLD_OUT = 0x2F010A51ull;
+
+static const uint64_t P9N2_C_16_FIR_HOLD_OUT = 0x30010A51ull;
+
+static const uint64_t P9N2_C_17_FIR_HOLD_OUT = 0x31010A51ull;
+
+static const uint64_t P9N2_C_18_FIR_HOLD_OUT = 0x32010A51ull;
+
+static const uint64_t P9N2_C_19_FIR_HOLD_OUT = 0x33010A51ull;
+
+static const uint64_t P9N2_C_20_FIR_HOLD_OUT = 0x34010A51ull;
+
+static const uint64_t P9N2_C_21_FIR_HOLD_OUT = 0x35010A51ull;
+
+static const uint64_t P9N2_C_22_FIR_HOLD_OUT = 0x36010A51ull;
+
+static const uint64_t P9N2_C_23_FIR_HOLD_OUT = 0x37010A51ull;
+
+static const uint64_t P9N2_EX_0_L2_FIR_HOLD_OUT = 0x20010A51ull;
+//DUPS: 21010A51,
+static const uint64_t P9N2_EX_10_L2_FIR_HOLD_OUT = 0x34010A51ull;
+//DUPS: 35010A51,
+static const uint64_t P9N2_EX_11_L2_FIR_HOLD_OUT = 0x36010A51ull;
+//DUPS: 37010A51,
+static const uint64_t P9N2_EX_1_L2_FIR_HOLD_OUT = 0x22010A51ull;
+//DUPS: 23010A51,
+static const uint64_t P9N2_EX_2_L2_FIR_HOLD_OUT = 0x24010A51ull;
+//DUPS: 25010A51,
+static const uint64_t P9N2_EX_3_L2_FIR_HOLD_OUT = 0x26010A51ull;
+//DUPS: 27010A51,
+static const uint64_t P9N2_EX_4_L2_FIR_HOLD_OUT = 0x28010A51ull;
+//DUPS: 29010A51,
+static const uint64_t P9N2_EX_5_L2_FIR_HOLD_OUT = 0x2A010A51ull;
+//DUPS: 2B010A51,
+static const uint64_t P9N2_EX_6_L2_FIR_HOLD_OUT = 0x2C010A51ull;
+//DUPS: 2D010A51,
+static const uint64_t P9N2_EX_7_L2_FIR_HOLD_OUT = 0x2F010A51ull;
+//DUPS: 2F010A51,
+static const uint64_t P9N2_EX_8_L2_FIR_HOLD_OUT = 0x30010A51ull;
+//DUPS: 31010A51,
+static const uint64_t P9N2_EX_9_L2_FIR_HOLD_OUT = 0x32010A51ull;
+//DUPS: 33010A51,
+static const uint64_t P9N2_EX_L2_FIR_HOLD_OUT = 0x20010A51ull;
+//DUPS: 21010A51,
+
+static const uint64_t P9N2_C_FIR_MASK = 0x20040002ull;
+
+static const uint64_t P9N2_C_0_FIR_MASK = 0x20040002ull;
+
+static const uint64_t P9N2_C_1_FIR_MASK = 0x21040002ull;
+
+static const uint64_t P9N2_C_2_FIR_MASK = 0x22040002ull;
+
+static const uint64_t P9N2_C_3_FIR_MASK = 0x23040002ull;
+
+static const uint64_t P9N2_C_4_FIR_MASK = 0x24040002ull;
+
+static const uint64_t P9N2_C_5_FIR_MASK = 0x25040002ull;
+
+static const uint64_t P9N2_C_6_FIR_MASK = 0x26040002ull;
+
+static const uint64_t P9N2_C_7_FIR_MASK = 0x27040002ull;
+
+static const uint64_t P9N2_C_8_FIR_MASK = 0x28040002ull;
+
+static const uint64_t P9N2_C_9_FIR_MASK = 0x29040002ull;
+
+static const uint64_t P9N2_C_10_FIR_MASK = 0x2A040002ull;
+
+static const uint64_t P9N2_C_11_FIR_MASK = 0x2B040002ull;
+
+static const uint64_t P9N2_C_12_FIR_MASK = 0x2C040002ull;
+
+static const uint64_t P9N2_C_13_FIR_MASK = 0x2D040002ull;
+
+static const uint64_t P9N2_C_14_FIR_MASK = 0x2E040002ull;
+
+static const uint64_t P9N2_C_15_FIR_MASK = 0x2F040002ull;
+
+static const uint64_t P9N2_C_16_FIR_MASK = 0x30040002ull;
+
+static const uint64_t P9N2_C_17_FIR_MASK = 0x31040002ull;
+
+static const uint64_t P9N2_C_18_FIR_MASK = 0x32040002ull;
+
+static const uint64_t P9N2_C_19_FIR_MASK = 0x33040002ull;
+
+static const uint64_t P9N2_C_20_FIR_MASK = 0x34040002ull;
+
+static const uint64_t P9N2_C_21_FIR_MASK = 0x35040002ull;
+
+static const uint64_t P9N2_C_22_FIR_MASK = 0x36040002ull;
+
+static const uint64_t P9N2_C_23_FIR_MASK = 0x37040002ull;
+
+static const uint64_t P9N2_EQ_FIR_MASK = 0x10040002ull;
+
+static const uint64_t P9N2_EQ_0_FIR_MASK = 0x10040002ull;
+
+static const uint64_t P9N2_EQ_1_FIR_MASK = 0x11040002ull;
+
+static const uint64_t P9N2_EQ_2_FIR_MASK = 0x12040002ull;
+
+static const uint64_t P9N2_EQ_3_FIR_MASK = 0x13040002ull;
+
+static const uint64_t P9N2_EQ_4_FIR_MASK = 0x14040002ull;
+
+static const uint64_t P9N2_EQ_5_FIR_MASK = 0x15040002ull;
+
+static const uint64_t P9N2_EX_FIR_MASK = 0x20040002ull;
+//DUPS: 21040002,
+static const uint64_t P9N2_EX_0_FIR_MASK = 0x20040002ull;
+//DUPS: 21040002,
+static const uint64_t P9N2_EX_1_FIR_MASK = 0x22040002ull;
+//DUPS: 23040002,
+static const uint64_t P9N2_EX_2_FIR_MASK = 0x24040002ull;
+//DUPS: 25040002,
+static const uint64_t P9N2_EX_3_FIR_MASK = 0x26040002ull;
+//DUPS: 27040002,
+static const uint64_t P9N2_EX_4_FIR_MASK = 0x28040002ull;
+//DUPS: 29040002,
+static const uint64_t P9N2_EX_5_FIR_MASK = 0x2A040002ull;
+//DUPS: 2B040002,
+static const uint64_t P9N2_EX_6_FIR_MASK = 0x2C040002ull;
+//DUPS: 2D040002,
+static const uint64_t P9N2_EX_7_FIR_MASK = 0x2F040002ull;
+//DUPS: 2F040002,
+static const uint64_t P9N2_EX_8_FIR_MASK = 0x30040002ull;
+//DUPS: 31040002,
+static const uint64_t P9N2_EX_9_FIR_MASK = 0x32040002ull;
+//DUPS: 33040002,
+static const uint64_t P9N2_EX_10_FIR_MASK = 0x34040002ull;
+//DUPS: 35040002,
+static const uint64_t P9N2_EX_11_FIR_MASK = 0x36040002ull;
+//DUPS: 37040002,
+
+static const uint64_t P9N2_EQ_FIR_MASK_REG = 0x10010C03ull;
+//DUPS: 10011803, 10011003, 10010C03, 10011C03, 10011403,
+static const uint64_t P9N2_EQ_FIR_MASK_REG_AND = 0x10010C04ull;
+//DUPS: 10011804, 10011004, 10010C04, 10011C04, 10011404,
+static const uint64_t P9N2_EQ_FIR_MASK_REG_OR = 0x10010C05ull;
+//DUPS: 10011805, 10011005, 10010C05, 10011C05, 10011405,
+static const uint64_t P9N2_EQ_0_FIR_MASK_REG = 0x10010C03ull;
+//DUPS: 10011803, 10011003, 10010C03, 10011C03, 10011403,
+static const uint64_t P9N2_EQ_0_FIR_MASK_REG_AND = 0x10010C04ull;
+//DUPS: 10011804, 10011004, 10010C04, 10011C04, 10011404,
+static const uint64_t P9N2_EQ_0_FIR_MASK_REG_OR = 0x10010C05ull;
+//DUPS: 10011805, 10011005, 10010C05, 10011C05, 10011405,
+static const uint64_t P9N2_EQ_1_FIR_MASK_REG = 0x11010C03ull;
+//DUPS: 11011803, 11011003, 11010C03, 11011C03, 11011403,
+static const uint64_t P9N2_EQ_1_FIR_MASK_REG_AND = 0x11010C04ull;
+//DUPS: 11011804, 11011004, 11010C04, 11011C04, 11011404,
+static const uint64_t P9N2_EQ_1_FIR_MASK_REG_OR = 0x11010C05ull;
+//DUPS: 11011805, 11011005, 11010C05, 11011C05, 11011405,
+static const uint64_t P9N2_EQ_2_FIR_MASK_REG = 0x12010C03ull;
+//DUPS: 12011803, 12011003, 12010C03, 12011C03, 12011403,
+static const uint64_t P9N2_EQ_2_FIR_MASK_REG_AND = 0x12010C04ull;
+//DUPS: 12011804, 12011004, 12010C04, 12011C04, 12011404,
+static const uint64_t P9N2_EQ_2_FIR_MASK_REG_OR = 0x12010C05ull;
+//DUPS: 12011805, 12011005, 12010C05, 12011C05, 12011405,
+static const uint64_t P9N2_EQ_3_FIR_MASK_REG = 0x13010C03ull;
+//DUPS: 13011803, 13011003, 13010C03, 13011C03, 13011403,
+static const uint64_t P9N2_EQ_3_FIR_MASK_REG_AND = 0x13010C04ull;
+//DUPS: 13011804, 13011004, 13010C04, 13011C04, 13011404,
+static const uint64_t P9N2_EQ_3_FIR_MASK_REG_OR = 0x13010C05ull;
+//DUPS: 13011805, 13011005, 13010C05, 13011C05, 13011405,
+static const uint64_t P9N2_EQ_4_FIR_MASK_REG = 0x14010C03ull;
+//DUPS: 14011803, 14011003, 14010C03, 14011C03, 14011403,
+static const uint64_t P9N2_EQ_4_FIR_MASK_REG_AND = 0x14010C04ull;
+//DUPS: 14011804, 14011004, 14010C04, 14011C04, 14011404,
+static const uint64_t P9N2_EQ_4_FIR_MASK_REG_OR = 0x14010C05ull;
+//DUPS: 14011805, 14011005, 14010C05, 14011C05, 14011405,
+static const uint64_t P9N2_EQ_5_FIR_MASK_REG = 0x15010C03ull;
+//DUPS: 15011803, 15011003, 15010C03, 15011C03, 15011403,
+static const uint64_t P9N2_EQ_5_FIR_MASK_REG_AND = 0x15010C04ull;
+//DUPS: 15011804, 15011004, 15010C04, 15011C04, 15011404,
+static const uint64_t P9N2_EQ_5_FIR_MASK_REG_OR = 0x15010C05ull;
+//DUPS: 15011805, 15011005, 15010C05, 15011C05, 15011405,
+static const uint64_t P9N2_EX_FIR_MASK_REG = 0x10011003ull;
+
+static const uint64_t P9N2_EX_FIR_MASK_REG_AND = 0x10011004ull;
+
+static const uint64_t P9N2_EX_FIR_MASK_REG_OR = 0x10011005ull;
+
+static const uint64_t P9N2_EX_0_FIR_MASK_REG = 0x10011003ull;
+
+static const uint64_t P9N2_EX_0_FIR_MASK_REG_AND = 0x10011004ull;
+
+static const uint64_t P9N2_EX_0_FIR_MASK_REG_OR = 0x10011005ull;
+
+static const uint64_t P9N2_EX_1_FIR_MASK_REG = 0x10011403ull;
+
+static const uint64_t P9N2_EX_1_FIR_MASK_REG_AND = 0x10011404ull;
+
+static const uint64_t P9N2_EX_1_FIR_MASK_REG_OR = 0x10011405ull;
+
+static const uint64_t P9N2_EX_2_FIR_MASK_REG = 0x11011003ull;
+
+static const uint64_t P9N2_EX_2_FIR_MASK_REG_AND = 0x11011004ull;
+
+static const uint64_t P9N2_EX_2_FIR_MASK_REG_OR = 0x11011005ull;
+
+static const uint64_t P9N2_EX_3_FIR_MASK_REG = 0x11011403ull;
+
+static const uint64_t P9N2_EX_3_FIR_MASK_REG_AND = 0x11011404ull;
+
+static const uint64_t P9N2_EX_3_FIR_MASK_REG_OR = 0x11011405ull;
+
+static const uint64_t P9N2_EX_4_FIR_MASK_REG = 0x12011003ull;
+
+static const uint64_t P9N2_EX_4_FIR_MASK_REG_AND = 0x12011004ull;
+
+static const uint64_t P9N2_EX_4_FIR_MASK_REG_OR = 0x12011005ull;
+
+static const uint64_t P9N2_EX_5_FIR_MASK_REG = 0x12011403ull;
+
+static const uint64_t P9N2_EX_5_FIR_MASK_REG_AND = 0x12011404ull;
+
+static const uint64_t P9N2_EX_5_FIR_MASK_REG_OR = 0x12011405ull;
+
+static const uint64_t P9N2_EX_6_FIR_MASK_REG = 0x13011003ull;
+
+static const uint64_t P9N2_EX_6_FIR_MASK_REG_AND = 0x13011004ull;
+
+static const uint64_t P9N2_EX_6_FIR_MASK_REG_OR = 0x13011005ull;
+
+static const uint64_t P9N2_EX_7_FIR_MASK_REG = 0x13011403ull;
+
+static const uint64_t P9N2_EX_7_FIR_MASK_REG_AND = 0x13011404ull;
+
+static const uint64_t P9N2_EX_7_FIR_MASK_REG_OR = 0x13011405ull;
+
+static const uint64_t P9N2_EX_8_FIR_MASK_REG = 0x14011003ull;
+
+static const uint64_t P9N2_EX_8_FIR_MASK_REG_AND = 0x14011004ull;
+
+static const uint64_t P9N2_EX_8_FIR_MASK_REG_OR = 0x14011005ull;
+
+static const uint64_t P9N2_EX_9_FIR_MASK_REG = 0x14011403ull;
+
+static const uint64_t P9N2_EX_9_FIR_MASK_REG_AND = 0x14011404ull;
+
+static const uint64_t P9N2_EX_9_FIR_MASK_REG_OR = 0x14011405ull;
+
+static const uint64_t P9N2_EX_0_L2_FIR_MASK_REG = 0x10010803ull;
+
+static const uint64_t P9N2_EX_0_L2_FIR_MASK_REG_AND = 0x10010804ull;
+
+static const uint64_t P9N2_EX_0_L2_FIR_MASK_REG_OR = 0x10010805ull;
+
+static const uint64_t P9N2_EX_0_L3_FIR_MASK_REG = 0x10011803ull;
+
+static const uint64_t P9N2_EX_0_L3_FIR_MASK_REG_AND = 0x10011804ull;
+
+static const uint64_t P9N2_EX_0_L3_FIR_MASK_REG_OR = 0x10011805ull;
+
+static const uint64_t P9N2_EX_10_FIR_MASK_REG = 0x15011003ull;
+
+static const uint64_t P9N2_EX_10_FIR_MASK_REG_AND = 0x15011004ull;
+
+static const uint64_t P9N2_EX_10_FIR_MASK_REG_OR = 0x15011005ull;
+
+static const uint64_t P9N2_EX_11_FIR_MASK_REG = 0x15011403ull;
+
+static const uint64_t P9N2_EX_11_FIR_MASK_REG_AND = 0x15011404ull;
+
+static const uint64_t P9N2_EX_11_FIR_MASK_REG_OR = 0x15011405ull;
+
+static const uint64_t P9N2_EX_10_L2_FIR_MASK_REG = 0x15010803ull;
+
+static const uint64_t P9N2_EX_10_L2_FIR_MASK_REG_AND = 0x15010804ull;
+
+static const uint64_t P9N2_EX_10_L2_FIR_MASK_REG_OR = 0x15010805ull;
+
+static const uint64_t P9N2_EX_10_L3_FIR_MASK_REG = 0x15011803ull;
+
+static const uint64_t P9N2_EX_10_L3_FIR_MASK_REG_AND = 0x15011804ull;
+
+static const uint64_t P9N2_EX_10_L3_FIR_MASK_REG_OR = 0x15011805ull;
+
+static const uint64_t P9N2_EX_11_L2_FIR_MASK_REG = 0x15010C03ull;
+
+static const uint64_t P9N2_EX_11_L2_FIR_MASK_REG_AND = 0x15010C04ull;
+
+static const uint64_t P9N2_EX_11_L2_FIR_MASK_REG_OR = 0x15010C05ull;
+
+static const uint64_t P9N2_EX_11_L3_FIR_MASK_REG = 0x15011C03ull;
+
+static const uint64_t P9N2_EX_11_L3_FIR_MASK_REG_AND = 0x15011C04ull;
+
+static const uint64_t P9N2_EX_11_L3_FIR_MASK_REG_OR = 0x15011C05ull;
+
+static const uint64_t P9N2_EX_1_L2_FIR_MASK_REG = 0x10010C03ull;
+
+static const uint64_t P9N2_EX_1_L2_FIR_MASK_REG_AND = 0x10010C04ull;
+
+static const uint64_t P9N2_EX_1_L2_FIR_MASK_REG_OR = 0x10010C05ull;
+
+static const uint64_t P9N2_EX_1_L3_FIR_MASK_REG = 0x10011C03ull;
+
+static const uint64_t P9N2_EX_1_L3_FIR_MASK_REG_AND = 0x10011C04ull;
+
+static const uint64_t P9N2_EX_1_L3_FIR_MASK_REG_OR = 0x10011C05ull;
+
+static const uint64_t P9N2_EX_2_L2_FIR_MASK_REG = 0x11010803ull;
+
+static const uint64_t P9N2_EX_2_L2_FIR_MASK_REG_AND = 0x11010804ull;
+
+static const uint64_t P9N2_EX_2_L2_FIR_MASK_REG_OR = 0x11010805ull;
+
+static const uint64_t P9N2_EX_2_L3_FIR_MASK_REG = 0x11011803ull;
+
+static const uint64_t P9N2_EX_2_L3_FIR_MASK_REG_AND = 0x11011804ull;
+
+static const uint64_t P9N2_EX_2_L3_FIR_MASK_REG_OR = 0x11011805ull;
+
+static const uint64_t P9N2_EX_3_L2_FIR_MASK_REG = 0x11010C03ull;
+
+static const uint64_t P9N2_EX_3_L2_FIR_MASK_REG_AND = 0x11010C04ull;
+
+static const uint64_t P9N2_EX_3_L2_FIR_MASK_REG_OR = 0x11010C05ull;
+
+static const uint64_t P9N2_EX_3_L3_FIR_MASK_REG = 0x11011C03ull;
+
+static const uint64_t P9N2_EX_3_L3_FIR_MASK_REG_AND = 0x11011C04ull;
+
+static const uint64_t P9N2_EX_3_L3_FIR_MASK_REG_OR = 0x11011C05ull;
+
+static const uint64_t P9N2_EX_4_L2_FIR_MASK_REG = 0x12010803ull;
+
+static const uint64_t P9N2_EX_4_L2_FIR_MASK_REG_AND = 0x12010804ull;
+
+static const uint64_t P9N2_EX_4_L2_FIR_MASK_REG_OR = 0x12010805ull;
+
+static const uint64_t P9N2_EX_4_L3_FIR_MASK_REG = 0x12011803ull;
+
+static const uint64_t P9N2_EX_4_L3_FIR_MASK_REG_AND = 0x12011804ull;
+
+static const uint64_t P9N2_EX_4_L3_FIR_MASK_REG_OR = 0x12011805ull;
+
+static const uint64_t P9N2_EX_5_L2_FIR_MASK_REG = 0x12010C03ull;
+
+static const uint64_t P9N2_EX_5_L2_FIR_MASK_REG_AND = 0x12010C04ull;
+
+static const uint64_t P9N2_EX_5_L2_FIR_MASK_REG_OR = 0x12010C05ull;
+
+static const uint64_t P9N2_EX_5_L3_FIR_MASK_REG = 0x12011C03ull;
+
+static const uint64_t P9N2_EX_5_L3_FIR_MASK_REG_AND = 0x12011C04ull;
+
+static const uint64_t P9N2_EX_5_L3_FIR_MASK_REG_OR = 0x12011C05ull;
+
+static const uint64_t P9N2_EX_6_L2_FIR_MASK_REG = 0x13010803ull;
+
+static const uint64_t P9N2_EX_6_L2_FIR_MASK_REG_AND = 0x13010804ull;
+
+static const uint64_t P9N2_EX_6_L2_FIR_MASK_REG_OR = 0x13010805ull;
+
+static const uint64_t P9N2_EX_6_L3_FIR_MASK_REG = 0x13011803ull;
+
+static const uint64_t P9N2_EX_6_L3_FIR_MASK_REG_AND = 0x13011804ull;
+
+static const uint64_t P9N2_EX_6_L3_FIR_MASK_REG_OR = 0x13011805ull;
+
+static const uint64_t P9N2_EX_7_L2_FIR_MASK_REG = 0x13010C03ull;
+
+static const uint64_t P9N2_EX_7_L2_FIR_MASK_REG_AND = 0x13010C04ull;
+
+static const uint64_t P9N2_EX_7_L2_FIR_MASK_REG_OR = 0x13010C05ull;
+
+static const uint64_t P9N2_EX_7_L3_FIR_MASK_REG = 0x13011C03ull;
+
+static const uint64_t P9N2_EX_7_L3_FIR_MASK_REG_AND = 0x13011C04ull;
+
+static const uint64_t P9N2_EX_7_L3_FIR_MASK_REG_OR = 0x13011C05ull;
+
+static const uint64_t P9N2_EX_8_L2_FIR_MASK_REG = 0x14010803ull;
+
+static const uint64_t P9N2_EX_8_L2_FIR_MASK_REG_AND = 0x14010804ull;
+
+static const uint64_t P9N2_EX_8_L2_FIR_MASK_REG_OR = 0x14010805ull;
+
+static const uint64_t P9N2_EX_8_L3_FIR_MASK_REG = 0x14011803ull;
+
+static const uint64_t P9N2_EX_8_L3_FIR_MASK_REG_AND = 0x14011804ull;
+
+static const uint64_t P9N2_EX_8_L3_FIR_MASK_REG_OR = 0x14011805ull;
+
+static const uint64_t P9N2_EX_9_L2_FIR_MASK_REG = 0x14010C03ull;
+
+static const uint64_t P9N2_EX_9_L2_FIR_MASK_REG_AND = 0x14010C04ull;
+
+static const uint64_t P9N2_EX_9_L2_FIR_MASK_REG_OR = 0x14010C05ull;
+
+static const uint64_t P9N2_EX_9_L3_FIR_MASK_REG = 0x14011C03ull;
+
+static const uint64_t P9N2_EX_9_L3_FIR_MASK_REG_AND = 0x14011C04ull;
+
+static const uint64_t P9N2_EX_9_L3_FIR_MASK_REG_OR = 0x14011C05ull;
+
+static const uint64_t P9N2_EX_L2_FIR_MASK_REG = 0x10010803ull;
+
+static const uint64_t P9N2_EX_L2_FIR_MASK_REG_AND = 0x10010804ull;
+
+static const uint64_t P9N2_EX_L2_FIR_MASK_REG_OR = 0x10010805ull;
+
+static const uint64_t P9N2_EX_L3_FIR_MASK_REG = 0x10011803ull;
+
+static const uint64_t P9N2_EX_L3_FIR_MASK_REG_AND = 0x10011804ull;
+
+static const uint64_t P9N2_EX_L3_FIR_MASK_REG_OR = 0x10011805ull;
+
+
+static const uint64_t P9N2_EQ_FIR_REG = 0x10010C00ull;
+//DUPS: 10011800, 10011000, 10010C00, 10011C00, 10011400,
+static const uint64_t P9N2_EQ_FIR_REG_AND = 0x10010C01ull;
+//DUPS: 10011801, 10011001, 10010C01, 10011C01, 10011401,
+static const uint64_t P9N2_EQ_FIR_REG_OR = 0x10010C02ull;
+//DUPS: 10011802, 10011002, 10010C02, 10011C02, 10011402,
+static const uint64_t P9N2_EQ_0_FIR_REG = 0x10010C00ull;
+//DUPS: 10011800, 10011000, 10010C00, 10011C00, 10011400,
+static const uint64_t P9N2_EQ_0_FIR_REG_AND = 0x10010C01ull;
+//DUPS: 10011801, 10011001, 10010C01, 10011C01, 10011401,
+static const uint64_t P9N2_EQ_0_FIR_REG_OR = 0x10010C02ull;
+//DUPS: 10011802, 10011002, 10010C02, 10011C02, 10011402,
+static const uint64_t P9N2_EQ_1_FIR_REG = 0x11010C00ull;
+//DUPS: 11011800, 11011000, 11010C00, 11011C00, 11011400,
+static const uint64_t P9N2_EQ_1_FIR_REG_AND = 0x11010C01ull;
+//DUPS: 11011801, 11011001, 11010C01, 11011C01, 11011401,
+static const uint64_t P9N2_EQ_1_FIR_REG_OR = 0x11010C02ull;
+//DUPS: 11011802, 11011002, 11010C02, 11011C02, 11011402,
+static const uint64_t P9N2_EQ_2_FIR_REG = 0x12010C00ull;
+//DUPS: 12011800, 12011000, 12010C00, 12011C00, 12011400,
+static const uint64_t P9N2_EQ_2_FIR_REG_AND = 0x12010C01ull;
+//DUPS: 12011801, 12011001, 12010C01, 12011C01, 12011401,
+static const uint64_t P9N2_EQ_2_FIR_REG_OR = 0x12010C02ull;
+//DUPS: 12011802, 12011002, 12010C02, 12011C02, 12011402,
+static const uint64_t P9N2_EQ_3_FIR_REG = 0x13010C00ull;
+//DUPS: 13011800, 13011000, 13010C00, 13011C00, 13011400,
+static const uint64_t P9N2_EQ_3_FIR_REG_AND = 0x13010C01ull;
+//DUPS: 13011801, 13011001, 13010C01, 13011C01, 13011401,
+static const uint64_t P9N2_EQ_3_FIR_REG_OR = 0x13010C02ull;
+//DUPS: 13011802, 13011002, 13010C02, 13011C02, 13011402,
+static const uint64_t P9N2_EQ_4_FIR_REG = 0x14010C00ull;
+//DUPS: 14011800, 14011000, 14010C00, 14011C00, 14011400,
+static const uint64_t P9N2_EQ_4_FIR_REG_AND = 0x14010C01ull;
+//DUPS: 14011801, 14011001, 14010C01, 14011C01, 14011401,
+static const uint64_t P9N2_EQ_4_FIR_REG_OR = 0x14010C02ull;
+//DUPS: 14011802, 14011002, 14010C02, 14011C02, 14011402,
+static const uint64_t P9N2_EQ_5_FIR_REG = 0x15010C00ull;
+//DUPS: 15011800, 15011000, 15010C00, 15011C00, 15011400,
+static const uint64_t P9N2_EQ_5_FIR_REG_AND = 0x15010C01ull;
+//DUPS: 15011801, 15011001, 15010C01, 15011C01, 15011401,
+static const uint64_t P9N2_EQ_5_FIR_REG_OR = 0x15010C02ull;
+//DUPS: 15011802, 15011002, 15010C02, 15011C02, 15011402,
+static const uint64_t P9N2_EX_FIR_REG = 0x10011000ull;
+
+static const uint64_t P9N2_EX_FIR_REG_AND = 0x10011001ull;
+
+static const uint64_t P9N2_EX_FIR_REG_OR = 0x10011002ull;
+
+static const uint64_t P9N2_EX_0_FIR_REG = 0x10011000ull;
+
+static const uint64_t P9N2_EX_0_FIR_REG_AND = 0x10011001ull;
+
+static const uint64_t P9N2_EX_0_FIR_REG_OR = 0x10011002ull;
+
+static const uint64_t P9N2_EX_1_FIR_REG = 0x10011400ull;
+
+static const uint64_t P9N2_EX_1_FIR_REG_AND = 0x10011401ull;
+
+static const uint64_t P9N2_EX_1_FIR_REG_OR = 0x10011402ull;
+
+static const uint64_t P9N2_EX_2_FIR_REG = 0x11011000ull;
+
+static const uint64_t P9N2_EX_2_FIR_REG_AND = 0x11011001ull;
+
+static const uint64_t P9N2_EX_2_FIR_REG_OR = 0x11011002ull;
+
+static const uint64_t P9N2_EX_3_FIR_REG = 0x11011400ull;
+
+static const uint64_t P9N2_EX_3_FIR_REG_AND = 0x11011401ull;
+
+static const uint64_t P9N2_EX_3_FIR_REG_OR = 0x11011402ull;
+
+static const uint64_t P9N2_EX_4_FIR_REG = 0x12011000ull;
+
+static const uint64_t P9N2_EX_4_FIR_REG_AND = 0x12011001ull;
+
+static const uint64_t P9N2_EX_4_FIR_REG_OR = 0x12011002ull;
+
+static const uint64_t P9N2_EX_5_FIR_REG = 0x12011400ull;
+
+static const uint64_t P9N2_EX_5_FIR_REG_AND = 0x12011401ull;
+
+static const uint64_t P9N2_EX_5_FIR_REG_OR = 0x12011402ull;
+
+static const uint64_t P9N2_EX_6_FIR_REG = 0x13011000ull;
+
+static const uint64_t P9N2_EX_6_FIR_REG_AND = 0x13011001ull;
+
+static const uint64_t P9N2_EX_6_FIR_REG_OR = 0x13011002ull;
+
+static const uint64_t P9N2_EX_7_FIR_REG = 0x13011400ull;
+
+static const uint64_t P9N2_EX_7_FIR_REG_AND = 0x13011401ull;
+
+static const uint64_t P9N2_EX_7_FIR_REG_OR = 0x13011402ull;
+
+static const uint64_t P9N2_EX_8_FIR_REG = 0x14011000ull;
+
+static const uint64_t P9N2_EX_8_FIR_REG_AND = 0x14011001ull;
+
+static const uint64_t P9N2_EX_8_FIR_REG_OR = 0x14011002ull;
+
+static const uint64_t P9N2_EX_9_FIR_REG = 0x14011400ull;
+
+static const uint64_t P9N2_EX_9_FIR_REG_AND = 0x14011401ull;
+
+static const uint64_t P9N2_EX_9_FIR_REG_OR = 0x14011402ull;
+
+static const uint64_t P9N2_EX_0_L2_FIR_REG = 0x10010800ull;
+
+static const uint64_t P9N2_EX_0_L2_FIR_REG_AND = 0x10010801ull;
+
+static const uint64_t P9N2_EX_0_L2_FIR_REG_OR = 0x10010802ull;
+
+static const uint64_t P9N2_EX_0_L3_FIR_REG = 0x10011800ull;
+
+static const uint64_t P9N2_EX_0_L3_FIR_REG_AND = 0x10011801ull;
+
+static const uint64_t P9N2_EX_0_L3_FIR_REG_OR = 0x10011802ull;
+
+static const uint64_t P9N2_EX_10_FIR_REG = 0x15011000ull;
+
+static const uint64_t P9N2_EX_10_FIR_REG_AND = 0x15011001ull;
+
+static const uint64_t P9N2_EX_10_FIR_REG_OR = 0x15011002ull;
+
+static const uint64_t P9N2_EX_11_FIR_REG = 0x15011400ull;
+
+static const uint64_t P9N2_EX_11_FIR_REG_AND = 0x15011401ull;
+
+static const uint64_t P9N2_EX_11_FIR_REG_OR = 0x15011402ull;
+
+static const uint64_t P9N2_EX_10_L2_FIR_REG = 0x15010800ull;
+
+static const uint64_t P9N2_EX_10_L2_FIR_REG_AND = 0x15010801ull;
+
+static const uint64_t P9N2_EX_10_L2_FIR_REG_OR = 0x15010802ull;
+
+static const uint64_t P9N2_EX_10_L3_FIR_REG = 0x15011800ull;
+
+static const uint64_t P9N2_EX_10_L3_FIR_REG_AND = 0x15011801ull;
+
+static const uint64_t P9N2_EX_10_L3_FIR_REG_OR = 0x15011802ull;
+
+static const uint64_t P9N2_EX_11_L2_FIR_REG = 0x15010C00ull;
+
+static const uint64_t P9N2_EX_11_L2_FIR_REG_AND = 0x15010C01ull;
+
+static const uint64_t P9N2_EX_11_L2_FIR_REG_OR = 0x15010C02ull;
+
+static const uint64_t P9N2_EX_11_L3_FIR_REG = 0x15011C00ull;
+
+static const uint64_t P9N2_EX_11_L3_FIR_REG_AND = 0x15011C01ull;
+
+static const uint64_t P9N2_EX_11_L3_FIR_REG_OR = 0x15011C02ull;
+
+static const uint64_t P9N2_EX_1_L2_FIR_REG = 0x10010C00ull;
+
+static const uint64_t P9N2_EX_1_L2_FIR_REG_AND = 0x10010C01ull;
+
+static const uint64_t P9N2_EX_1_L2_FIR_REG_OR = 0x10010C02ull;
+
+static const uint64_t P9N2_EX_1_L3_FIR_REG = 0x10011C00ull;
+
+static const uint64_t P9N2_EX_1_L3_FIR_REG_AND = 0x10011C01ull;
+
+static const uint64_t P9N2_EX_1_L3_FIR_REG_OR = 0x10011C02ull;
+
+static const uint64_t P9N2_EX_2_L2_FIR_REG = 0x11010800ull;
+
+static const uint64_t P9N2_EX_2_L2_FIR_REG_AND = 0x11010801ull;
+
+static const uint64_t P9N2_EX_2_L2_FIR_REG_OR = 0x11010802ull;
+
+static const uint64_t P9N2_EX_2_L3_FIR_REG = 0x11011800ull;
+
+static const uint64_t P9N2_EX_2_L3_FIR_REG_AND = 0x11011801ull;
+
+static const uint64_t P9N2_EX_2_L3_FIR_REG_OR = 0x11011802ull;
+
+static const uint64_t P9N2_EX_3_L2_FIR_REG = 0x11010C00ull;
+
+static const uint64_t P9N2_EX_3_L2_FIR_REG_AND = 0x11010C01ull;
+
+static const uint64_t P9N2_EX_3_L2_FIR_REG_OR = 0x11010C02ull;
+
+static const uint64_t P9N2_EX_3_L3_FIR_REG = 0x11011C00ull;
+
+static const uint64_t P9N2_EX_3_L3_FIR_REG_AND = 0x11011C01ull;
+
+static const uint64_t P9N2_EX_3_L3_FIR_REG_OR = 0x11011C02ull;
+
+static const uint64_t P9N2_EX_4_L2_FIR_REG = 0x12010800ull;
+
+static const uint64_t P9N2_EX_4_L2_FIR_REG_AND = 0x12010801ull;
+
+static const uint64_t P9N2_EX_4_L2_FIR_REG_OR = 0x12010802ull;
+
+static const uint64_t P9N2_EX_4_L3_FIR_REG = 0x12011800ull;
+
+static const uint64_t P9N2_EX_4_L3_FIR_REG_AND = 0x12011801ull;
+
+static const uint64_t P9N2_EX_4_L3_FIR_REG_OR = 0x12011802ull;
+
+static const uint64_t P9N2_EX_5_L2_FIR_REG = 0x12010C00ull;
+
+static const uint64_t P9N2_EX_5_L2_FIR_REG_AND = 0x12010C01ull;
+
+static const uint64_t P9N2_EX_5_L2_FIR_REG_OR = 0x12010C02ull;
+
+static const uint64_t P9N2_EX_5_L3_FIR_REG = 0x12011C00ull;
+
+static const uint64_t P9N2_EX_5_L3_FIR_REG_AND = 0x12011C01ull;
+
+static const uint64_t P9N2_EX_5_L3_FIR_REG_OR = 0x12011C02ull;
+
+static const uint64_t P9N2_EX_6_L2_FIR_REG = 0x13010800ull;
+
+static const uint64_t P9N2_EX_6_L2_FIR_REG_AND = 0x13010801ull;
+
+static const uint64_t P9N2_EX_6_L2_FIR_REG_OR = 0x13010802ull;
+
+static const uint64_t P9N2_EX_6_L3_FIR_REG = 0x13011800ull;
+
+static const uint64_t P9N2_EX_6_L3_FIR_REG_AND = 0x13011801ull;
+
+static const uint64_t P9N2_EX_6_L3_FIR_REG_OR = 0x13011802ull;
+
+static const uint64_t P9N2_EX_7_L2_FIR_REG = 0x13010C00ull;
+
+static const uint64_t P9N2_EX_7_L2_FIR_REG_AND = 0x13010C01ull;
+
+static const uint64_t P9N2_EX_7_L2_FIR_REG_OR = 0x13010C02ull;
+
+static const uint64_t P9N2_EX_7_L3_FIR_REG = 0x13011C00ull;
+
+static const uint64_t P9N2_EX_7_L3_FIR_REG_AND = 0x13011C01ull;
+
+static const uint64_t P9N2_EX_7_L3_FIR_REG_OR = 0x13011C02ull;
+
+static const uint64_t P9N2_EX_8_L2_FIR_REG = 0x14010800ull;
+
+static const uint64_t P9N2_EX_8_L2_FIR_REG_AND = 0x14010801ull;
+
+static const uint64_t P9N2_EX_8_L2_FIR_REG_OR = 0x14010802ull;
+
+static const uint64_t P9N2_EX_8_L3_FIR_REG = 0x14011800ull;
+
+static const uint64_t P9N2_EX_8_L3_FIR_REG_AND = 0x14011801ull;
+
+static const uint64_t P9N2_EX_8_L3_FIR_REG_OR = 0x14011802ull;
+
+static const uint64_t P9N2_EX_9_L2_FIR_REG = 0x14010C00ull;
+
+static const uint64_t P9N2_EX_9_L2_FIR_REG_AND = 0x14010C01ull;
+
+static const uint64_t P9N2_EX_9_L2_FIR_REG_OR = 0x14010C02ull;
+
+static const uint64_t P9N2_EX_9_L3_FIR_REG = 0x14011C00ull;
+
+static const uint64_t P9N2_EX_9_L3_FIR_REG_AND = 0x14011C01ull;
+
+static const uint64_t P9N2_EX_9_L3_FIR_REG_OR = 0x14011C02ull;
+
+static const uint64_t P9N2_EX_L2_FIR_REG = 0x10010800ull;
+
+static const uint64_t P9N2_EX_L2_FIR_REG_AND = 0x10010801ull;
+
+static const uint64_t P9N2_EX_L2_FIR_REG_OR = 0x10010802ull;
+
+static const uint64_t P9N2_EX_L3_FIR_REG = 0x10011800ull;
+
+static const uint64_t P9N2_EX_L3_FIR_REG_AND = 0x10011801ull;
+
+static const uint64_t P9N2_EX_L3_FIR_REG_OR = 0x10011802ull;
+
+
+static const uint64_t P9N2_C_GXSTOP0_MASK_REG = 0x20040014ull;
+
+static const uint64_t P9N2_C_0_GXSTOP0_MASK_REG = 0x20040014ull;
+
+static const uint64_t P9N2_C_1_GXSTOP0_MASK_REG = 0x21040014ull;
+
+static const uint64_t P9N2_C_2_GXSTOP0_MASK_REG = 0x22040014ull;
+
+static const uint64_t P9N2_C_3_GXSTOP0_MASK_REG = 0x23040014ull;
+
+static const uint64_t P9N2_C_4_GXSTOP0_MASK_REG = 0x24040014ull;
+
+static const uint64_t P9N2_C_5_GXSTOP0_MASK_REG = 0x25040014ull;
+
+static const uint64_t P9N2_C_6_GXSTOP0_MASK_REG = 0x26040014ull;
+
+static const uint64_t P9N2_C_7_GXSTOP0_MASK_REG = 0x27040014ull;
+
+static const uint64_t P9N2_C_8_GXSTOP0_MASK_REG = 0x28040014ull;
+
+static const uint64_t P9N2_C_9_GXSTOP0_MASK_REG = 0x29040014ull;
+
+static const uint64_t P9N2_C_10_GXSTOP0_MASK_REG = 0x2A040014ull;
+
+static const uint64_t P9N2_C_11_GXSTOP0_MASK_REG = 0x2B040014ull;
+
+static const uint64_t P9N2_C_12_GXSTOP0_MASK_REG = 0x2C040014ull;
+
+static const uint64_t P9N2_C_13_GXSTOP0_MASK_REG = 0x2D040014ull;
+
+static const uint64_t P9N2_C_14_GXSTOP0_MASK_REG = 0x2E040014ull;
+
+static const uint64_t P9N2_C_15_GXSTOP0_MASK_REG = 0x2F040014ull;
+
+static const uint64_t P9N2_C_16_GXSTOP0_MASK_REG = 0x30040014ull;
+
+static const uint64_t P9N2_C_17_GXSTOP0_MASK_REG = 0x31040014ull;
+
+static const uint64_t P9N2_C_18_GXSTOP0_MASK_REG = 0x32040014ull;
+
+static const uint64_t P9N2_C_19_GXSTOP0_MASK_REG = 0x33040014ull;
+
+static const uint64_t P9N2_C_20_GXSTOP0_MASK_REG = 0x34040014ull;
+
+static const uint64_t P9N2_C_21_GXSTOP0_MASK_REG = 0x35040014ull;
+
+static const uint64_t P9N2_C_22_GXSTOP0_MASK_REG = 0x36040014ull;
+
+static const uint64_t P9N2_C_23_GXSTOP0_MASK_REG = 0x37040014ull;
+
+static const uint64_t P9N2_EQ_GXSTOP0_MASK_REG = 0x10040014ull;
+
+static const uint64_t P9N2_EQ_0_GXSTOP0_MASK_REG = 0x10040014ull;
+
+static const uint64_t P9N2_EQ_1_GXSTOP0_MASK_REG = 0x11040014ull;
+
+static const uint64_t P9N2_EQ_2_GXSTOP0_MASK_REG = 0x12040014ull;
+
+static const uint64_t P9N2_EQ_3_GXSTOP0_MASK_REG = 0x13040014ull;
+
+static const uint64_t P9N2_EQ_4_GXSTOP0_MASK_REG = 0x14040014ull;
+
+static const uint64_t P9N2_EQ_5_GXSTOP0_MASK_REG = 0x15040014ull;
+
+static const uint64_t P9N2_EX_GXSTOP0_MASK_REG = 0x20040014ull;
+//DUPS: 21040014,
+static const uint64_t P9N2_EX_0_GXSTOP0_MASK_REG = 0x20040014ull;
+//DUPS: 21040014,
+static const uint64_t P9N2_EX_1_GXSTOP0_MASK_REG = 0x22040014ull;
+//DUPS: 23040014,
+static const uint64_t P9N2_EX_2_GXSTOP0_MASK_REG = 0x24040014ull;
+//DUPS: 25040014,
+static const uint64_t P9N2_EX_3_GXSTOP0_MASK_REG = 0x26040014ull;
+//DUPS: 27040014,
+static const uint64_t P9N2_EX_4_GXSTOP0_MASK_REG = 0x28040014ull;
+//DUPS: 29040014,
+static const uint64_t P9N2_EX_5_GXSTOP0_MASK_REG = 0x2A040014ull;
+//DUPS: 2B040014,
+static const uint64_t P9N2_EX_6_GXSTOP0_MASK_REG = 0x2C040014ull;
+//DUPS: 2D040014,
+static const uint64_t P9N2_EX_7_GXSTOP0_MASK_REG = 0x2F040014ull;
+//DUPS: 2F040014,
+static const uint64_t P9N2_EX_8_GXSTOP0_MASK_REG = 0x30040014ull;
+//DUPS: 31040014,
+static const uint64_t P9N2_EX_9_GXSTOP0_MASK_REG = 0x32040014ull;
+//DUPS: 33040014,
+static const uint64_t P9N2_EX_10_GXSTOP0_MASK_REG = 0x34040014ull;
+//DUPS: 35040014,
+static const uint64_t P9N2_EX_11_GXSTOP0_MASK_REG = 0x36040014ull;
+//DUPS: 37040014,
+
+static const uint64_t P9N2_C_GXSTOP1_MASK_REG = 0x20040015ull;
+
+static const uint64_t P9N2_C_0_GXSTOP1_MASK_REG = 0x20040015ull;
+
+static const uint64_t P9N2_C_1_GXSTOP1_MASK_REG = 0x21040015ull;
+
+static const uint64_t P9N2_C_2_GXSTOP1_MASK_REG = 0x22040015ull;
+
+static const uint64_t P9N2_C_3_GXSTOP1_MASK_REG = 0x23040015ull;
+
+static const uint64_t P9N2_C_4_GXSTOP1_MASK_REG = 0x24040015ull;
+
+static const uint64_t P9N2_C_5_GXSTOP1_MASK_REG = 0x25040015ull;
+
+static const uint64_t P9N2_C_6_GXSTOP1_MASK_REG = 0x26040015ull;
+
+static const uint64_t P9N2_C_7_GXSTOP1_MASK_REG = 0x27040015ull;
+
+static const uint64_t P9N2_C_8_GXSTOP1_MASK_REG = 0x28040015ull;
+
+static const uint64_t P9N2_C_9_GXSTOP1_MASK_REG = 0x29040015ull;
+
+static const uint64_t P9N2_C_10_GXSTOP1_MASK_REG = 0x2A040015ull;
+
+static const uint64_t P9N2_C_11_GXSTOP1_MASK_REG = 0x2B040015ull;
+
+static const uint64_t P9N2_C_12_GXSTOP1_MASK_REG = 0x2C040015ull;
+
+static const uint64_t P9N2_C_13_GXSTOP1_MASK_REG = 0x2D040015ull;
+
+static const uint64_t P9N2_C_14_GXSTOP1_MASK_REG = 0x2E040015ull;
+
+static const uint64_t P9N2_C_15_GXSTOP1_MASK_REG = 0x2F040015ull;
+
+static const uint64_t P9N2_C_16_GXSTOP1_MASK_REG = 0x30040015ull;
+
+static const uint64_t P9N2_C_17_GXSTOP1_MASK_REG = 0x31040015ull;
+
+static const uint64_t P9N2_C_18_GXSTOP1_MASK_REG = 0x32040015ull;
+
+static const uint64_t P9N2_C_19_GXSTOP1_MASK_REG = 0x33040015ull;
+
+static const uint64_t P9N2_C_20_GXSTOP1_MASK_REG = 0x34040015ull;
+
+static const uint64_t P9N2_C_21_GXSTOP1_MASK_REG = 0x35040015ull;
+
+static const uint64_t P9N2_C_22_GXSTOP1_MASK_REG = 0x36040015ull;
+
+static const uint64_t P9N2_C_23_GXSTOP1_MASK_REG = 0x37040015ull;
+
+static const uint64_t P9N2_EQ_GXSTOP1_MASK_REG = 0x10040015ull;
+
+static const uint64_t P9N2_EQ_0_GXSTOP1_MASK_REG = 0x10040015ull;
+
+static const uint64_t P9N2_EQ_1_GXSTOP1_MASK_REG = 0x11040015ull;
+
+static const uint64_t P9N2_EQ_2_GXSTOP1_MASK_REG = 0x12040015ull;
+
+static const uint64_t P9N2_EQ_3_GXSTOP1_MASK_REG = 0x13040015ull;
+
+static const uint64_t P9N2_EQ_4_GXSTOP1_MASK_REG = 0x14040015ull;
+
+static const uint64_t P9N2_EQ_5_GXSTOP1_MASK_REG = 0x15040015ull;
+
+static const uint64_t P9N2_EX_GXSTOP1_MASK_REG = 0x20040015ull;
+//DUPS: 21040015,
+static const uint64_t P9N2_EX_0_GXSTOP1_MASK_REG = 0x20040015ull;
+//DUPS: 21040015,
+static const uint64_t P9N2_EX_1_GXSTOP1_MASK_REG = 0x22040015ull;
+//DUPS: 23040015,
+static const uint64_t P9N2_EX_2_GXSTOP1_MASK_REG = 0x24040015ull;
+//DUPS: 25040015,
+static const uint64_t P9N2_EX_3_GXSTOP1_MASK_REG = 0x26040015ull;
+//DUPS: 27040015,
+static const uint64_t P9N2_EX_4_GXSTOP1_MASK_REG = 0x28040015ull;
+//DUPS: 29040015,
+static const uint64_t P9N2_EX_5_GXSTOP1_MASK_REG = 0x2A040015ull;
+//DUPS: 2B040015,
+static const uint64_t P9N2_EX_6_GXSTOP1_MASK_REG = 0x2C040015ull;
+//DUPS: 2D040015,
+static const uint64_t P9N2_EX_7_GXSTOP1_MASK_REG = 0x2F040015ull;
+//DUPS: 2F040015,
+static const uint64_t P9N2_EX_8_GXSTOP1_MASK_REG = 0x30040015ull;
+//DUPS: 31040015,
+static const uint64_t P9N2_EX_9_GXSTOP1_MASK_REG = 0x32040015ull;
+//DUPS: 33040015,
+static const uint64_t P9N2_EX_10_GXSTOP1_MASK_REG = 0x34040015ull;
+//DUPS: 35040015,
+static const uint64_t P9N2_EX_11_GXSTOP1_MASK_REG = 0x36040015ull;
+//DUPS: 37040015,
+
+static const uint64_t P9N2_C_GXSTOP2_MASK_REG = 0x20040016ull;
+
+static const uint64_t P9N2_C_0_GXSTOP2_MASK_REG = 0x20040016ull;
+
+static const uint64_t P9N2_C_1_GXSTOP2_MASK_REG = 0x21040016ull;
+
+static const uint64_t P9N2_C_2_GXSTOP2_MASK_REG = 0x22040016ull;
+
+static const uint64_t P9N2_C_3_GXSTOP2_MASK_REG = 0x23040016ull;
+
+static const uint64_t P9N2_C_4_GXSTOP2_MASK_REG = 0x24040016ull;
+
+static const uint64_t P9N2_C_5_GXSTOP2_MASK_REG = 0x25040016ull;
+
+static const uint64_t P9N2_C_6_GXSTOP2_MASK_REG = 0x26040016ull;
+
+static const uint64_t P9N2_C_7_GXSTOP2_MASK_REG = 0x27040016ull;
+
+static const uint64_t P9N2_C_8_GXSTOP2_MASK_REG = 0x28040016ull;
+
+static const uint64_t P9N2_C_9_GXSTOP2_MASK_REG = 0x29040016ull;
+
+static const uint64_t P9N2_C_10_GXSTOP2_MASK_REG = 0x2A040016ull;
+
+static const uint64_t P9N2_C_11_GXSTOP2_MASK_REG = 0x2B040016ull;
+
+static const uint64_t P9N2_C_12_GXSTOP2_MASK_REG = 0x2C040016ull;
+
+static const uint64_t P9N2_C_13_GXSTOP2_MASK_REG = 0x2D040016ull;
+
+static const uint64_t P9N2_C_14_GXSTOP2_MASK_REG = 0x2E040016ull;
+
+static const uint64_t P9N2_C_15_GXSTOP2_MASK_REG = 0x2F040016ull;
+
+static const uint64_t P9N2_C_16_GXSTOP2_MASK_REG = 0x30040016ull;
+
+static const uint64_t P9N2_C_17_GXSTOP2_MASK_REG = 0x31040016ull;
+
+static const uint64_t P9N2_C_18_GXSTOP2_MASK_REG = 0x32040016ull;
+
+static const uint64_t P9N2_C_19_GXSTOP2_MASK_REG = 0x33040016ull;
+
+static const uint64_t P9N2_C_20_GXSTOP2_MASK_REG = 0x34040016ull;
+
+static const uint64_t P9N2_C_21_GXSTOP2_MASK_REG = 0x35040016ull;
+
+static const uint64_t P9N2_C_22_GXSTOP2_MASK_REG = 0x36040016ull;
+
+static const uint64_t P9N2_C_23_GXSTOP2_MASK_REG = 0x37040016ull;
+
+static const uint64_t P9N2_EQ_GXSTOP2_MASK_REG = 0x10040016ull;
+
+static const uint64_t P9N2_EQ_0_GXSTOP2_MASK_REG = 0x10040016ull;
+
+static const uint64_t P9N2_EQ_1_GXSTOP2_MASK_REG = 0x11040016ull;
+
+static const uint64_t P9N2_EQ_2_GXSTOP2_MASK_REG = 0x12040016ull;
+
+static const uint64_t P9N2_EQ_3_GXSTOP2_MASK_REG = 0x13040016ull;
+
+static const uint64_t P9N2_EQ_4_GXSTOP2_MASK_REG = 0x14040016ull;
+
+static const uint64_t P9N2_EQ_5_GXSTOP2_MASK_REG = 0x15040016ull;
+
+static const uint64_t P9N2_EX_GXSTOP2_MASK_REG = 0x20040016ull;
+//DUPS: 21040016,
+static const uint64_t P9N2_EX_0_GXSTOP2_MASK_REG = 0x20040016ull;
+//DUPS: 21040016,
+static const uint64_t P9N2_EX_1_GXSTOP2_MASK_REG = 0x22040016ull;
+//DUPS: 23040016,
+static const uint64_t P9N2_EX_2_GXSTOP2_MASK_REG = 0x24040016ull;
+//DUPS: 25040016,
+static const uint64_t P9N2_EX_3_GXSTOP2_MASK_REG = 0x26040016ull;
+//DUPS: 27040016,
+static const uint64_t P9N2_EX_4_GXSTOP2_MASK_REG = 0x28040016ull;
+//DUPS: 29040016,
+static const uint64_t P9N2_EX_5_GXSTOP2_MASK_REG = 0x2A040016ull;
+//DUPS: 2B040016,
+static const uint64_t P9N2_EX_6_GXSTOP2_MASK_REG = 0x2C040016ull;
+//DUPS: 2D040016,
+static const uint64_t P9N2_EX_7_GXSTOP2_MASK_REG = 0x2F040016ull;
+//DUPS: 2F040016,
+static const uint64_t P9N2_EX_8_GXSTOP2_MASK_REG = 0x30040016ull;
+//DUPS: 31040016,
+static const uint64_t P9N2_EX_9_GXSTOP2_MASK_REG = 0x32040016ull;
+//DUPS: 33040016,
+static const uint64_t P9N2_EX_10_GXSTOP2_MASK_REG = 0x34040016ull;
+//DUPS: 35040016,
+static const uint64_t P9N2_EX_11_GXSTOP2_MASK_REG = 0x36040016ull;
+//DUPS: 37040016,
+
+static const uint64_t P9N2_C_GXSTOP_TRIG_REG = 0x20040013ull;
+
+static const uint64_t P9N2_C_0_GXSTOP_TRIG_REG = 0x20040013ull;
+
+static const uint64_t P9N2_C_1_GXSTOP_TRIG_REG = 0x21040013ull;
+
+static const uint64_t P9N2_C_2_GXSTOP_TRIG_REG = 0x22040013ull;
+
+static const uint64_t P9N2_C_3_GXSTOP_TRIG_REG = 0x23040013ull;
+
+static const uint64_t P9N2_C_4_GXSTOP_TRIG_REG = 0x24040013ull;
+
+static const uint64_t P9N2_C_5_GXSTOP_TRIG_REG = 0x25040013ull;
+
+static const uint64_t P9N2_C_6_GXSTOP_TRIG_REG = 0x26040013ull;
+
+static const uint64_t P9N2_C_7_GXSTOP_TRIG_REG = 0x27040013ull;
+
+static const uint64_t P9N2_C_8_GXSTOP_TRIG_REG = 0x28040013ull;
+
+static const uint64_t P9N2_C_9_GXSTOP_TRIG_REG = 0x29040013ull;
+
+static const uint64_t P9N2_C_10_GXSTOP_TRIG_REG = 0x2A040013ull;
+
+static const uint64_t P9N2_C_11_GXSTOP_TRIG_REG = 0x2B040013ull;
+
+static const uint64_t P9N2_C_12_GXSTOP_TRIG_REG = 0x2C040013ull;
+
+static const uint64_t P9N2_C_13_GXSTOP_TRIG_REG = 0x2D040013ull;
+
+static const uint64_t P9N2_C_14_GXSTOP_TRIG_REG = 0x2E040013ull;
+
+static const uint64_t P9N2_C_15_GXSTOP_TRIG_REG = 0x2F040013ull;
+
+static const uint64_t P9N2_C_16_GXSTOP_TRIG_REG = 0x30040013ull;
+
+static const uint64_t P9N2_C_17_GXSTOP_TRIG_REG = 0x31040013ull;
+
+static const uint64_t P9N2_C_18_GXSTOP_TRIG_REG = 0x32040013ull;
+
+static const uint64_t P9N2_C_19_GXSTOP_TRIG_REG = 0x33040013ull;
+
+static const uint64_t P9N2_C_20_GXSTOP_TRIG_REG = 0x34040013ull;
+
+static const uint64_t P9N2_C_21_GXSTOP_TRIG_REG = 0x35040013ull;
+
+static const uint64_t P9N2_C_22_GXSTOP_TRIG_REG = 0x36040013ull;
+
+static const uint64_t P9N2_C_23_GXSTOP_TRIG_REG = 0x37040013ull;
+
+static const uint64_t P9N2_EQ_GXSTOP_TRIG_REG = 0x10040013ull;
+
+static const uint64_t P9N2_EQ_0_GXSTOP_TRIG_REG = 0x10040013ull;
+
+static const uint64_t P9N2_EQ_1_GXSTOP_TRIG_REG = 0x11040013ull;
+
+static const uint64_t P9N2_EQ_2_GXSTOP_TRIG_REG = 0x12040013ull;
+
+static const uint64_t P9N2_EQ_3_GXSTOP_TRIG_REG = 0x13040013ull;
+
+static const uint64_t P9N2_EQ_4_GXSTOP_TRIG_REG = 0x14040013ull;
+
+static const uint64_t P9N2_EQ_5_GXSTOP_TRIG_REG = 0x15040013ull;
+
+static const uint64_t P9N2_EX_GXSTOP_TRIG_REG = 0x20040013ull;
+//DUPS: 21040013,
+static const uint64_t P9N2_EX_0_GXSTOP_TRIG_REG = 0x20040013ull;
+//DUPS: 21040013,
+static const uint64_t P9N2_EX_1_GXSTOP_TRIG_REG = 0x22040013ull;
+//DUPS: 23040013,
+static const uint64_t P9N2_EX_2_GXSTOP_TRIG_REG = 0x24040013ull;
+//DUPS: 25040013,
+static const uint64_t P9N2_EX_3_GXSTOP_TRIG_REG = 0x26040013ull;
+//DUPS: 27040013,
+static const uint64_t P9N2_EX_4_GXSTOP_TRIG_REG = 0x28040013ull;
+//DUPS: 29040013,
+static const uint64_t P9N2_EX_5_GXSTOP_TRIG_REG = 0x2A040013ull;
+//DUPS: 2B040013,
+static const uint64_t P9N2_EX_6_GXSTOP_TRIG_REG = 0x2C040013ull;
+//DUPS: 2D040013,
+static const uint64_t P9N2_EX_7_GXSTOP_TRIG_REG = 0x2F040013ull;
+//DUPS: 2F040013,
+static const uint64_t P9N2_EX_8_GXSTOP_TRIG_REG = 0x30040013ull;
+//DUPS: 31040013,
+static const uint64_t P9N2_EX_9_GXSTOP_TRIG_REG = 0x32040013ull;
+//DUPS: 33040013,
+static const uint64_t P9N2_EX_10_GXSTOP_TRIG_REG = 0x34040013ull;
+//DUPS: 35040013,
+static const uint64_t P9N2_EX_11_GXSTOP_TRIG_REG = 0x36040013ull;
+//DUPS: 37040013,
+
+static const uint64_t P9N2_C_HANG_CONTROL = 0x20010A00ull;
+
+static const uint64_t P9N2_C_0_HANG_CONTROL = 0x20010A00ull;
+
+static const uint64_t P9N2_C_1_HANG_CONTROL = 0x21010A00ull;
+
+static const uint64_t P9N2_C_2_HANG_CONTROL = 0x22010A00ull;
+
+static const uint64_t P9N2_C_3_HANG_CONTROL = 0x23010A00ull;
+
+static const uint64_t P9N2_C_4_HANG_CONTROL = 0x24010A00ull;
+
+static const uint64_t P9N2_C_5_HANG_CONTROL = 0x25010A00ull;
+
+static const uint64_t P9N2_C_6_HANG_CONTROL = 0x26010A00ull;
+
+static const uint64_t P9N2_C_7_HANG_CONTROL = 0x27010A00ull;
+
+static const uint64_t P9N2_C_8_HANG_CONTROL = 0x28010A00ull;
+
+static const uint64_t P9N2_C_9_HANG_CONTROL = 0x29010A00ull;
+
+static const uint64_t P9N2_C_10_HANG_CONTROL = 0x2A010A00ull;
+
+static const uint64_t P9N2_C_11_HANG_CONTROL = 0x2B010A00ull;
+
+static const uint64_t P9N2_C_12_HANG_CONTROL = 0x2C010A00ull;
+
+static const uint64_t P9N2_C_13_HANG_CONTROL = 0x2D010A00ull;
+
+static const uint64_t P9N2_C_14_HANG_CONTROL = 0x2E010A00ull;
+
+static const uint64_t P9N2_C_15_HANG_CONTROL = 0x2F010A00ull;
+
+static const uint64_t P9N2_C_16_HANG_CONTROL = 0x30010A00ull;
+
+static const uint64_t P9N2_C_17_HANG_CONTROL = 0x31010A00ull;
+
+static const uint64_t P9N2_C_18_HANG_CONTROL = 0x32010A00ull;
+
+static const uint64_t P9N2_C_19_HANG_CONTROL = 0x33010A00ull;
+
+static const uint64_t P9N2_C_20_HANG_CONTROL = 0x34010A00ull;
+
+static const uint64_t P9N2_C_21_HANG_CONTROL = 0x35010A00ull;
+
+static const uint64_t P9N2_C_22_HANG_CONTROL = 0x36010A00ull;
+
+static const uint64_t P9N2_C_23_HANG_CONTROL = 0x37010A00ull;
+
+static const uint64_t P9N2_EX_0_L2_HANG_CONTROL = 0x20010A00ull;
+//DUPS: 21010A00,
+static const uint64_t P9N2_EX_10_L2_HANG_CONTROL = 0x34010A00ull;
+//DUPS: 35010A00,
+static const uint64_t P9N2_EX_11_L2_HANG_CONTROL = 0x36010A00ull;
+//DUPS: 37010A00,
+static const uint64_t P9N2_EX_1_L2_HANG_CONTROL = 0x22010A00ull;
+//DUPS: 23010A00,
+static const uint64_t P9N2_EX_2_L2_HANG_CONTROL = 0x24010A00ull;
+//DUPS: 25010A00,
+static const uint64_t P9N2_EX_3_L2_HANG_CONTROL = 0x26010A00ull;
+//DUPS: 27010A00,
+static const uint64_t P9N2_EX_4_L2_HANG_CONTROL = 0x28010A00ull;
+//DUPS: 29010A00,
+static const uint64_t P9N2_EX_5_L2_HANG_CONTROL = 0x2A010A00ull;
+//DUPS: 2B010A00,
+static const uint64_t P9N2_EX_6_L2_HANG_CONTROL = 0x2C010A00ull;
+//DUPS: 2D010A00,
+static const uint64_t P9N2_EX_7_L2_HANG_CONTROL = 0x2F010A00ull;
+//DUPS: 2F010A00,
+static const uint64_t P9N2_EX_8_L2_HANG_CONTROL = 0x30010A00ull;
+//DUPS: 31010A00,
+static const uint64_t P9N2_EX_9_L2_HANG_CONTROL = 0x32010A00ull;
+//DUPS: 33010A00,
+static const uint64_t P9N2_EX_L2_HANG_CONTROL = 0x20010A00ull;
+//DUPS: 21010A00,
+
+static const uint64_t P9N2_C_HANG_PULSE_0_REG = 0x200F0020ull;
+
+static const uint64_t P9N2_C_0_HANG_PULSE_0_REG = 0x200F0020ull;
+
+static const uint64_t P9N2_C_1_HANG_PULSE_0_REG = 0x210F0020ull;
+
+static const uint64_t P9N2_C_2_HANG_PULSE_0_REG = 0x220F0020ull;
+
+static const uint64_t P9N2_C_3_HANG_PULSE_0_REG = 0x230F0020ull;
+
+static const uint64_t P9N2_C_4_HANG_PULSE_0_REG = 0x240F0020ull;
+
+static const uint64_t P9N2_C_5_HANG_PULSE_0_REG = 0x250F0020ull;
+
+static const uint64_t P9N2_C_6_HANG_PULSE_0_REG = 0x260F0020ull;
+
+static const uint64_t P9N2_C_7_HANG_PULSE_0_REG = 0x270F0020ull;
+
+static const uint64_t P9N2_C_8_HANG_PULSE_0_REG = 0x280F0020ull;
+
+static const uint64_t P9N2_C_9_HANG_PULSE_0_REG = 0x290F0020ull;
+
+static const uint64_t P9N2_C_10_HANG_PULSE_0_REG = 0x2A0F0020ull;
+
+static const uint64_t P9N2_C_11_HANG_PULSE_0_REG = 0x2B0F0020ull;
+
+static const uint64_t P9N2_C_12_HANG_PULSE_0_REG = 0x2C0F0020ull;
+
+static const uint64_t P9N2_C_13_HANG_PULSE_0_REG = 0x2D0F0020ull;
+
+static const uint64_t P9N2_C_14_HANG_PULSE_0_REG = 0x2E0F0020ull;
+
+static const uint64_t P9N2_C_15_HANG_PULSE_0_REG = 0x2F0F0020ull;
+
+static const uint64_t P9N2_C_16_HANG_PULSE_0_REG = 0x300F0020ull;
+
+static const uint64_t P9N2_C_17_HANG_PULSE_0_REG = 0x310F0020ull;
+
+static const uint64_t P9N2_C_18_HANG_PULSE_0_REG = 0x320F0020ull;
+
+static const uint64_t P9N2_C_19_HANG_PULSE_0_REG = 0x330F0020ull;
+
+static const uint64_t P9N2_C_20_HANG_PULSE_0_REG = 0x340F0020ull;
+
+static const uint64_t P9N2_C_21_HANG_PULSE_0_REG = 0x350F0020ull;
+
+static const uint64_t P9N2_C_22_HANG_PULSE_0_REG = 0x360F0020ull;
+
+static const uint64_t P9N2_C_23_HANG_PULSE_0_REG = 0x370F0020ull;
+
+static const uint64_t P9N2_EQ_HANG_PULSE_0_REG = 0x100F0020ull;
+
+static const uint64_t P9N2_EQ_0_HANG_PULSE_0_REG = 0x100F0020ull;
+
+static const uint64_t P9N2_EQ_1_HANG_PULSE_0_REG = 0x110F0020ull;
+
+static const uint64_t P9N2_EQ_2_HANG_PULSE_0_REG = 0x120F0020ull;
+
+static const uint64_t P9N2_EQ_3_HANG_PULSE_0_REG = 0x130F0020ull;
+
+static const uint64_t P9N2_EQ_4_HANG_PULSE_0_REG = 0x140F0020ull;
+
+static const uint64_t P9N2_EQ_5_HANG_PULSE_0_REG = 0x150F0020ull;
+
+static const uint64_t P9N2_EX_HANG_PULSE_0_REG = 0x200F0020ull;
+//DUPS: 210F0020,
+static const uint64_t P9N2_EX_0_HANG_PULSE_0_REG = 0x200F0020ull;
+//DUPS: 210F0020,
+static const uint64_t P9N2_EX_1_HANG_PULSE_0_REG = 0x220F0020ull;
+//DUPS: 220F0020,
+static const uint64_t P9N2_EX_2_HANG_PULSE_0_REG = 0x240F0020ull;
+//DUPS: 250F0020,
+static const uint64_t P9N2_EX_3_HANG_PULSE_0_REG = 0x260F0020ull;
+//DUPS: 270F0020,
+static const uint64_t P9N2_EX_4_HANG_PULSE_0_REG = 0x280F0020ull;
+//DUPS: 290F0020,
+static const uint64_t P9N2_EX_5_HANG_PULSE_0_REG = 0x2A0F0020ull;
+//DUPS: 2B0F0020,
+static const uint64_t P9N2_EX_6_HANG_PULSE_0_REG = 0x2C0F0020ull;
+//DUPS: 2D0F0020,
+static const uint64_t P9N2_EX_7_HANG_PULSE_0_REG = 0x2E0F0020ull;
+//DUPS: 2F0F0020,
+static const uint64_t P9N2_EX_8_HANG_PULSE_0_REG = 0x300F0020ull;
+//DUPS: 310F0020,
+static const uint64_t P9N2_EX_9_HANG_PULSE_0_REG = 0x320F0020ull;
+//DUPS: 330F0020,
+static const uint64_t P9N2_EX_10_HANG_PULSE_0_REG = 0x340F0020ull;
+//DUPS: 350F0020,
+static const uint64_t P9N2_EX_11_HANG_PULSE_0_REG = 0x360F0020ull;
+//DUPS: 370F0020,
+
+static const uint64_t P9N2_C_HANG_PULSE_1_REG = 0x200F0021ull;
+
+static const uint64_t P9N2_C_0_HANG_PULSE_1_REG = 0x200F0021ull;
+
+static const uint64_t P9N2_C_1_HANG_PULSE_1_REG = 0x210F0021ull;
+
+static const uint64_t P9N2_C_2_HANG_PULSE_1_REG = 0x220F0021ull;
+
+static const uint64_t P9N2_C_3_HANG_PULSE_1_REG = 0x230F0021ull;
+
+static const uint64_t P9N2_C_4_HANG_PULSE_1_REG = 0x240F0021ull;
+
+static const uint64_t P9N2_C_5_HANG_PULSE_1_REG = 0x250F0021ull;
+
+static const uint64_t P9N2_C_6_HANG_PULSE_1_REG = 0x260F0021ull;
+
+static const uint64_t P9N2_C_7_HANG_PULSE_1_REG = 0x270F0021ull;
+
+static const uint64_t P9N2_C_8_HANG_PULSE_1_REG = 0x280F0021ull;
+
+static const uint64_t P9N2_C_9_HANG_PULSE_1_REG = 0x290F0021ull;
+
+static const uint64_t P9N2_C_10_HANG_PULSE_1_REG = 0x2A0F0021ull;
+
+static const uint64_t P9N2_C_11_HANG_PULSE_1_REG = 0x2B0F0021ull;
+
+static const uint64_t P9N2_C_12_HANG_PULSE_1_REG = 0x2C0F0021ull;
+
+static const uint64_t P9N2_C_13_HANG_PULSE_1_REG = 0x2D0F0021ull;
+
+static const uint64_t P9N2_C_14_HANG_PULSE_1_REG = 0x2E0F0021ull;
+
+static const uint64_t P9N2_C_15_HANG_PULSE_1_REG = 0x2F0F0021ull;
+
+static const uint64_t P9N2_C_16_HANG_PULSE_1_REG = 0x300F0021ull;
+
+static const uint64_t P9N2_C_17_HANG_PULSE_1_REG = 0x310F0021ull;
+
+static const uint64_t P9N2_C_18_HANG_PULSE_1_REG = 0x320F0021ull;
+
+static const uint64_t P9N2_C_19_HANG_PULSE_1_REG = 0x330F0021ull;
+
+static const uint64_t P9N2_C_20_HANG_PULSE_1_REG = 0x340F0021ull;
+
+static const uint64_t P9N2_C_21_HANG_PULSE_1_REG = 0x350F0021ull;
+
+static const uint64_t P9N2_C_22_HANG_PULSE_1_REG = 0x360F0021ull;
+
+static const uint64_t P9N2_C_23_HANG_PULSE_1_REG = 0x370F0021ull;
+
+static const uint64_t P9N2_EQ_HANG_PULSE_1_REG = 0x100F0021ull;
+
+static const uint64_t P9N2_EQ_0_HANG_PULSE_1_REG = 0x100F0021ull;
+
+static const uint64_t P9N2_EQ_1_HANG_PULSE_1_REG = 0x110F0021ull;
+
+static const uint64_t P9N2_EQ_2_HANG_PULSE_1_REG = 0x120F0021ull;
+
+static const uint64_t P9N2_EQ_3_HANG_PULSE_1_REG = 0x130F0021ull;
+
+static const uint64_t P9N2_EQ_4_HANG_PULSE_1_REG = 0x140F0021ull;
+
+static const uint64_t P9N2_EQ_5_HANG_PULSE_1_REG = 0x150F0021ull;
+
+static const uint64_t P9N2_EX_HANG_PULSE_1_REG = 0x200F0021ull;
+//DUPS: 210F0021,
+static const uint64_t P9N2_EX_0_HANG_PULSE_1_REG = 0x200F0021ull;
+//DUPS: 210F0021,
+static const uint64_t P9N2_EX_1_HANG_PULSE_1_REG = 0x220F0021ull;
+//DUPS: 220F0021,
+static const uint64_t P9N2_EX_2_HANG_PULSE_1_REG = 0x240F0021ull;
+//DUPS: 250F0021,
+static const uint64_t P9N2_EX_3_HANG_PULSE_1_REG = 0x260F0021ull;
+//DUPS: 270F0021,
+static const uint64_t P9N2_EX_4_HANG_PULSE_1_REG = 0x280F0021ull;
+//DUPS: 290F0021,
+static const uint64_t P9N2_EX_5_HANG_PULSE_1_REG = 0x2A0F0021ull;
+//DUPS: 2B0F0021,
+static const uint64_t P9N2_EX_6_HANG_PULSE_1_REG = 0x2C0F0021ull;
+//DUPS: 2D0F0021,
+static const uint64_t P9N2_EX_7_HANG_PULSE_1_REG = 0x2E0F0021ull;
+//DUPS: 2F0F0021,
+static const uint64_t P9N2_EX_8_HANG_PULSE_1_REG = 0x300F0021ull;
+//DUPS: 310F0021,
+static const uint64_t P9N2_EX_9_HANG_PULSE_1_REG = 0x320F0021ull;
+//DUPS: 330F0021,
+static const uint64_t P9N2_EX_10_HANG_PULSE_1_REG = 0x340F0021ull;
+//DUPS: 350F0021,
+static const uint64_t P9N2_EX_11_HANG_PULSE_1_REG = 0x360F0021ull;
+//DUPS: 370F0021,
+
+static const uint64_t P9N2_C_HANG_PULSE_2_REG = 0x200F0022ull;
+
+static const uint64_t P9N2_C_0_HANG_PULSE_2_REG = 0x200F0022ull;
+
+static const uint64_t P9N2_C_1_HANG_PULSE_2_REG = 0x210F0022ull;
+
+static const uint64_t P9N2_C_2_HANG_PULSE_2_REG = 0x220F0022ull;
+
+static const uint64_t P9N2_C_3_HANG_PULSE_2_REG = 0x230F0022ull;
+
+static const uint64_t P9N2_C_4_HANG_PULSE_2_REG = 0x240F0022ull;
+
+static const uint64_t P9N2_C_5_HANG_PULSE_2_REG = 0x250F0022ull;
+
+static const uint64_t P9N2_C_6_HANG_PULSE_2_REG = 0x260F0022ull;
+
+static const uint64_t P9N2_C_7_HANG_PULSE_2_REG = 0x270F0022ull;
+
+static const uint64_t P9N2_C_8_HANG_PULSE_2_REG = 0x280F0022ull;
+
+static const uint64_t P9N2_C_9_HANG_PULSE_2_REG = 0x290F0022ull;
+
+static const uint64_t P9N2_C_10_HANG_PULSE_2_REG = 0x2A0F0022ull;
+
+static const uint64_t P9N2_C_11_HANG_PULSE_2_REG = 0x2B0F0022ull;
+
+static const uint64_t P9N2_C_12_HANG_PULSE_2_REG = 0x2C0F0022ull;
+
+static const uint64_t P9N2_C_13_HANG_PULSE_2_REG = 0x2D0F0022ull;
+
+static const uint64_t P9N2_C_14_HANG_PULSE_2_REG = 0x2E0F0022ull;
+
+static const uint64_t P9N2_C_15_HANG_PULSE_2_REG = 0x2F0F0022ull;
+
+static const uint64_t P9N2_C_16_HANG_PULSE_2_REG = 0x300F0022ull;
+
+static const uint64_t P9N2_C_17_HANG_PULSE_2_REG = 0x310F0022ull;
+
+static const uint64_t P9N2_C_18_HANG_PULSE_2_REG = 0x320F0022ull;
+
+static const uint64_t P9N2_C_19_HANG_PULSE_2_REG = 0x330F0022ull;
+
+static const uint64_t P9N2_C_20_HANG_PULSE_2_REG = 0x340F0022ull;
+
+static const uint64_t P9N2_C_21_HANG_PULSE_2_REG = 0x350F0022ull;
+
+static const uint64_t P9N2_C_22_HANG_PULSE_2_REG = 0x360F0022ull;
+
+static const uint64_t P9N2_C_23_HANG_PULSE_2_REG = 0x370F0022ull;
+
+static const uint64_t P9N2_EQ_HANG_PULSE_2_REG = 0x100F0022ull;
+
+static const uint64_t P9N2_EQ_0_HANG_PULSE_2_REG = 0x100F0022ull;
+
+static const uint64_t P9N2_EQ_1_HANG_PULSE_2_REG = 0x110F0022ull;
+
+static const uint64_t P9N2_EQ_2_HANG_PULSE_2_REG = 0x120F0022ull;
+
+static const uint64_t P9N2_EQ_3_HANG_PULSE_2_REG = 0x130F0022ull;
+
+static const uint64_t P9N2_EQ_4_HANG_PULSE_2_REG = 0x140F0022ull;
+
+static const uint64_t P9N2_EQ_5_HANG_PULSE_2_REG = 0x150F0022ull;
+
+static const uint64_t P9N2_EX_HANG_PULSE_2_REG = 0x200F0022ull;
+//DUPS: 210F0022,
+static const uint64_t P9N2_EX_0_HANG_PULSE_2_REG = 0x200F0022ull;
+//DUPS: 210F0022,
+static const uint64_t P9N2_EX_1_HANG_PULSE_2_REG = 0x220F0022ull;
+//DUPS: 220F0022,
+static const uint64_t P9N2_EX_2_HANG_PULSE_2_REG = 0x240F0022ull;
+//DUPS: 250F0022,
+static const uint64_t P9N2_EX_3_HANG_PULSE_2_REG = 0x260F0022ull;
+//DUPS: 270F0022,
+static const uint64_t P9N2_EX_4_HANG_PULSE_2_REG = 0x280F0022ull;
+//DUPS: 290F0022,
+static const uint64_t P9N2_EX_5_HANG_PULSE_2_REG = 0x2A0F0022ull;
+//DUPS: 2B0F0022,
+static const uint64_t P9N2_EX_6_HANG_PULSE_2_REG = 0x2C0F0022ull;
+//DUPS: 2D0F0022,
+static const uint64_t P9N2_EX_7_HANG_PULSE_2_REG = 0x2E0F0022ull;
+//DUPS: 2F0F0022,
+static const uint64_t P9N2_EX_8_HANG_PULSE_2_REG = 0x300F0022ull;
+//DUPS: 310F0022,
+static const uint64_t P9N2_EX_9_HANG_PULSE_2_REG = 0x320F0022ull;
+//DUPS: 330F0022,
+static const uint64_t P9N2_EX_10_HANG_PULSE_2_REG = 0x340F0022ull;
+//DUPS: 350F0022,
+static const uint64_t P9N2_EX_11_HANG_PULSE_2_REG = 0x360F0022ull;
+//DUPS: 370F0022,
+
+static const uint64_t P9N2_C_HANG_PULSE_3_REG = 0x200F0023ull;
+
+static const uint64_t P9N2_C_0_HANG_PULSE_3_REG = 0x200F0023ull;
+
+static const uint64_t P9N2_C_1_HANG_PULSE_3_REG = 0x210F0023ull;
+
+static const uint64_t P9N2_C_2_HANG_PULSE_3_REG = 0x220F0023ull;
+
+static const uint64_t P9N2_C_3_HANG_PULSE_3_REG = 0x230F0023ull;
+
+static const uint64_t P9N2_C_4_HANG_PULSE_3_REG = 0x240F0023ull;
+
+static const uint64_t P9N2_C_5_HANG_PULSE_3_REG = 0x250F0023ull;
+
+static const uint64_t P9N2_C_6_HANG_PULSE_3_REG = 0x260F0023ull;
+
+static const uint64_t P9N2_C_7_HANG_PULSE_3_REG = 0x270F0023ull;
+
+static const uint64_t P9N2_C_8_HANG_PULSE_3_REG = 0x280F0023ull;
+
+static const uint64_t P9N2_C_9_HANG_PULSE_3_REG = 0x290F0023ull;
+
+static const uint64_t P9N2_C_10_HANG_PULSE_3_REG = 0x2A0F0023ull;
+
+static const uint64_t P9N2_C_11_HANG_PULSE_3_REG = 0x2B0F0023ull;
+
+static const uint64_t P9N2_C_12_HANG_PULSE_3_REG = 0x2C0F0023ull;
+
+static const uint64_t P9N2_C_13_HANG_PULSE_3_REG = 0x2D0F0023ull;
+
+static const uint64_t P9N2_C_14_HANG_PULSE_3_REG = 0x2E0F0023ull;
+
+static const uint64_t P9N2_C_15_HANG_PULSE_3_REG = 0x2F0F0023ull;
+
+static const uint64_t P9N2_C_16_HANG_PULSE_3_REG = 0x300F0023ull;
+
+static const uint64_t P9N2_C_17_HANG_PULSE_3_REG = 0x310F0023ull;
+
+static const uint64_t P9N2_C_18_HANG_PULSE_3_REG = 0x320F0023ull;
+
+static const uint64_t P9N2_C_19_HANG_PULSE_3_REG = 0x330F0023ull;
+
+static const uint64_t P9N2_C_20_HANG_PULSE_3_REG = 0x340F0023ull;
+
+static const uint64_t P9N2_C_21_HANG_PULSE_3_REG = 0x350F0023ull;
+
+static const uint64_t P9N2_C_22_HANG_PULSE_3_REG = 0x360F0023ull;
+
+static const uint64_t P9N2_C_23_HANG_PULSE_3_REG = 0x370F0023ull;
+
+static const uint64_t P9N2_EQ_HANG_PULSE_3_REG = 0x100F0023ull;
+
+static const uint64_t P9N2_EQ_0_HANG_PULSE_3_REG = 0x100F0023ull;
+
+static const uint64_t P9N2_EQ_1_HANG_PULSE_3_REG = 0x110F0023ull;
+
+static const uint64_t P9N2_EQ_2_HANG_PULSE_3_REG = 0x120F0023ull;
+
+static const uint64_t P9N2_EQ_3_HANG_PULSE_3_REG = 0x130F0023ull;
+
+static const uint64_t P9N2_EQ_4_HANG_PULSE_3_REG = 0x140F0023ull;
+
+static const uint64_t P9N2_EQ_5_HANG_PULSE_3_REG = 0x150F0023ull;
+
+static const uint64_t P9N2_EX_HANG_PULSE_3_REG = 0x200F0023ull;
+//DUPS: 210F0023,
+static const uint64_t P9N2_EX_0_HANG_PULSE_3_REG = 0x200F0023ull;
+//DUPS: 210F0023,
+static const uint64_t P9N2_EX_1_HANG_PULSE_3_REG = 0x220F0023ull;
+//DUPS: 220F0023,
+static const uint64_t P9N2_EX_2_HANG_PULSE_3_REG = 0x240F0023ull;
+//DUPS: 250F0023,
+static const uint64_t P9N2_EX_3_HANG_PULSE_3_REG = 0x260F0023ull;
+//DUPS: 270F0023,
+static const uint64_t P9N2_EX_4_HANG_PULSE_3_REG = 0x280F0023ull;
+//DUPS: 290F0023,
+static const uint64_t P9N2_EX_5_HANG_PULSE_3_REG = 0x2A0F0023ull;
+//DUPS: 2B0F0023,
+static const uint64_t P9N2_EX_6_HANG_PULSE_3_REG = 0x2C0F0023ull;
+//DUPS: 2D0F0023,
+static const uint64_t P9N2_EX_7_HANG_PULSE_3_REG = 0x2E0F0023ull;
+//DUPS: 2F0F0023,
+static const uint64_t P9N2_EX_8_HANG_PULSE_3_REG = 0x300F0023ull;
+//DUPS: 310F0023,
+static const uint64_t P9N2_EX_9_HANG_PULSE_3_REG = 0x320F0023ull;
+//DUPS: 330F0023,
+static const uint64_t P9N2_EX_10_HANG_PULSE_3_REG = 0x340F0023ull;
+//DUPS: 350F0023,
+static const uint64_t P9N2_EX_11_HANG_PULSE_3_REG = 0x360F0023ull;
+//DUPS: 370F0023,
+
+static const uint64_t P9N2_C_HANG_PULSE_4_REG = 0x200F0024ull;
+
+static const uint64_t P9N2_C_0_HANG_PULSE_4_REG = 0x200F0024ull;
+
+static const uint64_t P9N2_C_1_HANG_PULSE_4_REG = 0x210F0024ull;
+
+static const uint64_t P9N2_C_2_HANG_PULSE_4_REG = 0x220F0024ull;
+
+static const uint64_t P9N2_C_3_HANG_PULSE_4_REG = 0x230F0024ull;
+
+static const uint64_t P9N2_C_4_HANG_PULSE_4_REG = 0x240F0024ull;
+
+static const uint64_t P9N2_C_5_HANG_PULSE_4_REG = 0x250F0024ull;
+
+static const uint64_t P9N2_C_6_HANG_PULSE_4_REG = 0x260F0024ull;
+
+static const uint64_t P9N2_C_7_HANG_PULSE_4_REG = 0x270F0024ull;
+
+static const uint64_t P9N2_C_8_HANG_PULSE_4_REG = 0x280F0024ull;
+
+static const uint64_t P9N2_C_9_HANG_PULSE_4_REG = 0x290F0024ull;
+
+static const uint64_t P9N2_C_10_HANG_PULSE_4_REG = 0x2A0F0024ull;
+
+static const uint64_t P9N2_C_11_HANG_PULSE_4_REG = 0x2B0F0024ull;
+
+static const uint64_t P9N2_C_12_HANG_PULSE_4_REG = 0x2C0F0024ull;
+
+static const uint64_t P9N2_C_13_HANG_PULSE_4_REG = 0x2D0F0024ull;
+
+static const uint64_t P9N2_C_14_HANG_PULSE_4_REG = 0x2E0F0024ull;
+
+static const uint64_t P9N2_C_15_HANG_PULSE_4_REG = 0x2F0F0024ull;
+
+static const uint64_t P9N2_C_16_HANG_PULSE_4_REG = 0x300F0024ull;
+
+static const uint64_t P9N2_C_17_HANG_PULSE_4_REG = 0x310F0024ull;
+
+static const uint64_t P9N2_C_18_HANG_PULSE_4_REG = 0x320F0024ull;
+
+static const uint64_t P9N2_C_19_HANG_PULSE_4_REG = 0x330F0024ull;
+
+static const uint64_t P9N2_C_20_HANG_PULSE_4_REG = 0x340F0024ull;
+
+static const uint64_t P9N2_C_21_HANG_PULSE_4_REG = 0x350F0024ull;
+
+static const uint64_t P9N2_C_22_HANG_PULSE_4_REG = 0x360F0024ull;
+
+static const uint64_t P9N2_C_23_HANG_PULSE_4_REG = 0x370F0024ull;
+
+static const uint64_t P9N2_EQ_HANG_PULSE_4_REG = 0x100F0024ull;
+
+static const uint64_t P9N2_EQ_0_HANG_PULSE_4_REG = 0x100F0024ull;
+
+static const uint64_t P9N2_EQ_1_HANG_PULSE_4_REG = 0x110F0024ull;
+
+static const uint64_t P9N2_EQ_2_HANG_PULSE_4_REG = 0x120F0024ull;
+
+static const uint64_t P9N2_EQ_3_HANG_PULSE_4_REG = 0x130F0024ull;
+
+static const uint64_t P9N2_EQ_4_HANG_PULSE_4_REG = 0x140F0024ull;
+
+static const uint64_t P9N2_EQ_5_HANG_PULSE_4_REG = 0x150F0024ull;
+
+static const uint64_t P9N2_EX_HANG_PULSE_4_REG = 0x200F0024ull;
+//DUPS: 210F0024,
+static const uint64_t P9N2_EX_0_HANG_PULSE_4_REG = 0x200F0024ull;
+//DUPS: 210F0024,
+static const uint64_t P9N2_EX_1_HANG_PULSE_4_REG = 0x220F0024ull;
+//DUPS: 220F0024,
+static const uint64_t P9N2_EX_2_HANG_PULSE_4_REG = 0x240F0024ull;
+//DUPS: 250F0024,
+static const uint64_t P9N2_EX_3_HANG_PULSE_4_REG = 0x260F0024ull;
+//DUPS: 270F0024,
+static const uint64_t P9N2_EX_4_HANG_PULSE_4_REG = 0x280F0024ull;
+//DUPS: 290F0024,
+static const uint64_t P9N2_EX_5_HANG_PULSE_4_REG = 0x2A0F0024ull;
+//DUPS: 2B0F0024,
+static const uint64_t P9N2_EX_6_HANG_PULSE_4_REG = 0x2C0F0024ull;
+//DUPS: 2D0F0024,
+static const uint64_t P9N2_EX_7_HANG_PULSE_4_REG = 0x2E0F0024ull;
+//DUPS: 2F0F0024,
+static const uint64_t P9N2_EX_8_HANG_PULSE_4_REG = 0x300F0024ull;
+//DUPS: 310F0024,
+static const uint64_t P9N2_EX_9_HANG_PULSE_4_REG = 0x320F0024ull;
+//DUPS: 330F0024,
+static const uint64_t P9N2_EX_10_HANG_PULSE_4_REG = 0x340F0024ull;
+//DUPS: 350F0024,
+static const uint64_t P9N2_EX_11_HANG_PULSE_4_REG = 0x360F0024ull;
+//DUPS: 370F0024,
+
+static const uint64_t P9N2_C_HANG_PULSE_5_REG = 0x200F0025ull;
+
+static const uint64_t P9N2_C_0_HANG_PULSE_5_REG = 0x200F0025ull;
+
+static const uint64_t P9N2_C_1_HANG_PULSE_5_REG = 0x210F0025ull;
+
+static const uint64_t P9N2_C_2_HANG_PULSE_5_REG = 0x220F0025ull;
+
+static const uint64_t P9N2_C_3_HANG_PULSE_5_REG = 0x230F0025ull;
+
+static const uint64_t P9N2_C_4_HANG_PULSE_5_REG = 0x240F0025ull;
+
+static const uint64_t P9N2_C_5_HANG_PULSE_5_REG = 0x250F0025ull;
+
+static const uint64_t P9N2_C_6_HANG_PULSE_5_REG = 0x260F0025ull;
+
+static const uint64_t P9N2_C_7_HANG_PULSE_5_REG = 0x270F0025ull;
+
+static const uint64_t P9N2_C_8_HANG_PULSE_5_REG = 0x280F0025ull;
+
+static const uint64_t P9N2_C_9_HANG_PULSE_5_REG = 0x290F0025ull;
+
+static const uint64_t P9N2_C_10_HANG_PULSE_5_REG = 0x2A0F0025ull;
+
+static const uint64_t P9N2_C_11_HANG_PULSE_5_REG = 0x2B0F0025ull;
+
+static const uint64_t P9N2_C_12_HANG_PULSE_5_REG = 0x2C0F0025ull;
+
+static const uint64_t P9N2_C_13_HANG_PULSE_5_REG = 0x2D0F0025ull;
+
+static const uint64_t P9N2_C_14_HANG_PULSE_5_REG = 0x2E0F0025ull;
+
+static const uint64_t P9N2_C_15_HANG_PULSE_5_REG = 0x2F0F0025ull;
+
+static const uint64_t P9N2_C_16_HANG_PULSE_5_REG = 0x300F0025ull;
+
+static const uint64_t P9N2_C_17_HANG_PULSE_5_REG = 0x310F0025ull;
+
+static const uint64_t P9N2_C_18_HANG_PULSE_5_REG = 0x320F0025ull;
+
+static const uint64_t P9N2_C_19_HANG_PULSE_5_REG = 0x330F0025ull;
+
+static const uint64_t P9N2_C_20_HANG_PULSE_5_REG = 0x340F0025ull;
+
+static const uint64_t P9N2_C_21_HANG_PULSE_5_REG = 0x350F0025ull;
+
+static const uint64_t P9N2_C_22_HANG_PULSE_5_REG = 0x360F0025ull;
+
+static const uint64_t P9N2_C_23_HANG_PULSE_5_REG = 0x370F0025ull;
+
+static const uint64_t P9N2_EQ_HANG_PULSE_5_REG = 0x100F0025ull;
+
+static const uint64_t P9N2_EQ_0_HANG_PULSE_5_REG = 0x100F0025ull;
+
+static const uint64_t P9N2_EQ_1_HANG_PULSE_5_REG = 0x110F0025ull;
+
+static const uint64_t P9N2_EQ_2_HANG_PULSE_5_REG = 0x120F0025ull;
+
+static const uint64_t P9N2_EQ_3_HANG_PULSE_5_REG = 0x130F0025ull;
+
+static const uint64_t P9N2_EQ_4_HANG_PULSE_5_REG = 0x140F0025ull;
+
+static const uint64_t P9N2_EQ_5_HANG_PULSE_5_REG = 0x150F0025ull;
+
+static const uint64_t P9N2_EX_HANG_PULSE_5_REG = 0x200F0025ull;
+//DUPS: 210F0025,
+static const uint64_t P9N2_EX_0_HANG_PULSE_5_REG = 0x200F0025ull;
+//DUPS: 210F0025,
+static const uint64_t P9N2_EX_1_HANG_PULSE_5_REG = 0x220F0025ull;
+//DUPS: 220F0025,
+static const uint64_t P9N2_EX_2_HANG_PULSE_5_REG = 0x240F0025ull;
+//DUPS: 250F0025,
+static const uint64_t P9N2_EX_3_HANG_PULSE_5_REG = 0x260F0025ull;
+//DUPS: 270F0025,
+static const uint64_t P9N2_EX_4_HANG_PULSE_5_REG = 0x280F0025ull;
+//DUPS: 290F0025,
+static const uint64_t P9N2_EX_5_HANG_PULSE_5_REG = 0x2A0F0025ull;
+//DUPS: 2B0F0025,
+static const uint64_t P9N2_EX_6_HANG_PULSE_5_REG = 0x2C0F0025ull;
+//DUPS: 2D0F0025,
+static const uint64_t P9N2_EX_7_HANG_PULSE_5_REG = 0x2E0F0025ull;
+//DUPS: 2F0F0025,
+static const uint64_t P9N2_EX_8_HANG_PULSE_5_REG = 0x300F0025ull;
+//DUPS: 310F0025,
+static const uint64_t P9N2_EX_9_HANG_PULSE_5_REG = 0x320F0025ull;
+//DUPS: 330F0025,
+static const uint64_t P9N2_EX_10_HANG_PULSE_5_REG = 0x340F0025ull;
+//DUPS: 350F0025,
+static const uint64_t P9N2_EX_11_HANG_PULSE_5_REG = 0x360F0025ull;
+//DUPS: 370F0025,
+
+static const uint64_t P9N2_C_HANG_PULSE_6_REG = 0x200F0026ull;
+
+static const uint64_t P9N2_C_0_HANG_PULSE_6_REG = 0x200F0026ull;
+
+static const uint64_t P9N2_C_1_HANG_PULSE_6_REG = 0x210F0026ull;
+
+static const uint64_t P9N2_C_2_HANG_PULSE_6_REG = 0x220F0026ull;
+
+static const uint64_t P9N2_C_3_HANG_PULSE_6_REG = 0x230F0026ull;
+
+static const uint64_t P9N2_C_4_HANG_PULSE_6_REG = 0x240F0026ull;
+
+static const uint64_t P9N2_C_5_HANG_PULSE_6_REG = 0x250F0026ull;
+
+static const uint64_t P9N2_C_6_HANG_PULSE_6_REG = 0x260F0026ull;
+
+static const uint64_t P9N2_C_7_HANG_PULSE_6_REG = 0x270F0026ull;
+
+static const uint64_t P9N2_C_8_HANG_PULSE_6_REG = 0x280F0026ull;
+
+static const uint64_t P9N2_C_9_HANG_PULSE_6_REG = 0x290F0026ull;
+
+static const uint64_t P9N2_C_10_HANG_PULSE_6_REG = 0x2A0F0026ull;
+
+static const uint64_t P9N2_C_11_HANG_PULSE_6_REG = 0x2B0F0026ull;
+
+static const uint64_t P9N2_C_12_HANG_PULSE_6_REG = 0x2C0F0026ull;
+
+static const uint64_t P9N2_C_13_HANG_PULSE_6_REG = 0x2D0F0026ull;
+
+static const uint64_t P9N2_C_14_HANG_PULSE_6_REG = 0x2E0F0026ull;
+
+static const uint64_t P9N2_C_15_HANG_PULSE_6_REG = 0x2F0F0026ull;
+
+static const uint64_t P9N2_C_16_HANG_PULSE_6_REG = 0x300F0026ull;
+
+static const uint64_t P9N2_C_17_HANG_PULSE_6_REG = 0x310F0026ull;
+
+static const uint64_t P9N2_C_18_HANG_PULSE_6_REG = 0x320F0026ull;
+
+static const uint64_t P9N2_C_19_HANG_PULSE_6_REG = 0x330F0026ull;
+
+static const uint64_t P9N2_C_20_HANG_PULSE_6_REG = 0x340F0026ull;
+
+static const uint64_t P9N2_C_21_HANG_PULSE_6_REG = 0x350F0026ull;
+
+static const uint64_t P9N2_C_22_HANG_PULSE_6_REG = 0x360F0026ull;
+
+static const uint64_t P9N2_C_23_HANG_PULSE_6_REG = 0x370F0026ull;
+
+static const uint64_t P9N2_EQ_HANG_PULSE_6_REG = 0x100F0026ull;
+
+static const uint64_t P9N2_EQ_0_HANG_PULSE_6_REG = 0x100F0026ull;
+
+static const uint64_t P9N2_EQ_1_HANG_PULSE_6_REG = 0x110F0026ull;
+
+static const uint64_t P9N2_EQ_2_HANG_PULSE_6_REG = 0x120F0026ull;
+
+static const uint64_t P9N2_EQ_3_HANG_PULSE_6_REG = 0x130F0026ull;
+
+static const uint64_t P9N2_EQ_4_HANG_PULSE_6_REG = 0x140F0026ull;
+
+static const uint64_t P9N2_EQ_5_HANG_PULSE_6_REG = 0x150F0026ull;
+
+static const uint64_t P9N2_EX_HANG_PULSE_6_REG = 0x200F0026ull;
+//DUPS: 210F0026,
+static const uint64_t P9N2_EX_0_HANG_PULSE_6_REG = 0x200F0026ull;
+//DUPS: 210F0026,
+static const uint64_t P9N2_EX_1_HANG_PULSE_6_REG = 0x220F0026ull;
+//DUPS: 220F0026,
+static const uint64_t P9N2_EX_2_HANG_PULSE_6_REG = 0x240F0026ull;
+//DUPS: 250F0026,
+static const uint64_t P9N2_EX_3_HANG_PULSE_6_REG = 0x260F0026ull;
+//DUPS: 270F0026,
+static const uint64_t P9N2_EX_4_HANG_PULSE_6_REG = 0x280F0026ull;
+//DUPS: 290F0026,
+static const uint64_t P9N2_EX_5_HANG_PULSE_6_REG = 0x2A0F0026ull;
+//DUPS: 2B0F0026,
+static const uint64_t P9N2_EX_6_HANG_PULSE_6_REG = 0x2C0F0026ull;
+//DUPS: 2D0F0026,
+static const uint64_t P9N2_EX_7_HANG_PULSE_6_REG = 0x2E0F0026ull;
+//DUPS: 2F0F0026,
+static const uint64_t P9N2_EX_8_HANG_PULSE_6_REG = 0x300F0026ull;
+//DUPS: 310F0026,
+static const uint64_t P9N2_EX_9_HANG_PULSE_6_REG = 0x320F0026ull;
+//DUPS: 330F0026,
+static const uint64_t P9N2_EX_10_HANG_PULSE_6_REG = 0x340F0026ull;
+//DUPS: 350F0026,
+static const uint64_t P9N2_EX_11_HANG_PULSE_6_REG = 0x360F0026ull;
+//DUPS: 370F0026,
+
+static const uint64_t P9N2_C_HEARTBEAT_REG = 0x200F0018ull;
+
+static const uint64_t P9N2_C_0_HEARTBEAT_REG = 0x200F0018ull;
+
+static const uint64_t P9N2_C_1_HEARTBEAT_REG = 0x210F0018ull;
+
+static const uint64_t P9N2_C_2_HEARTBEAT_REG = 0x220F0018ull;
+
+static const uint64_t P9N2_C_3_HEARTBEAT_REG = 0x230F0018ull;
+
+static const uint64_t P9N2_C_4_HEARTBEAT_REG = 0x240F0018ull;
+
+static const uint64_t P9N2_C_5_HEARTBEAT_REG = 0x250F0018ull;
+
+static const uint64_t P9N2_C_6_HEARTBEAT_REG = 0x260F0018ull;
+
+static const uint64_t P9N2_C_7_HEARTBEAT_REG = 0x270F0018ull;
+
+static const uint64_t P9N2_C_8_HEARTBEAT_REG = 0x280F0018ull;
+
+static const uint64_t P9N2_C_9_HEARTBEAT_REG = 0x290F0018ull;
+
+static const uint64_t P9N2_C_10_HEARTBEAT_REG = 0x2A0F0018ull;
+
+static const uint64_t P9N2_C_11_HEARTBEAT_REG = 0x2B0F0018ull;
+
+static const uint64_t P9N2_C_12_HEARTBEAT_REG = 0x2C0F0018ull;
+
+static const uint64_t P9N2_C_13_HEARTBEAT_REG = 0x2D0F0018ull;
+
+static const uint64_t P9N2_C_14_HEARTBEAT_REG = 0x2E0F0018ull;
+
+static const uint64_t P9N2_C_15_HEARTBEAT_REG = 0x2F0F0018ull;
+
+static const uint64_t P9N2_C_16_HEARTBEAT_REG = 0x300F0018ull;
+
+static const uint64_t P9N2_C_17_HEARTBEAT_REG = 0x310F0018ull;
+
+static const uint64_t P9N2_C_18_HEARTBEAT_REG = 0x320F0018ull;
+
+static const uint64_t P9N2_C_19_HEARTBEAT_REG = 0x330F0018ull;
+
+static const uint64_t P9N2_C_20_HEARTBEAT_REG = 0x340F0018ull;
+
+static const uint64_t P9N2_C_21_HEARTBEAT_REG = 0x350F0018ull;
+
+static const uint64_t P9N2_C_22_HEARTBEAT_REG = 0x360F0018ull;
+
+static const uint64_t P9N2_C_23_HEARTBEAT_REG = 0x370F0018ull;
+
+static const uint64_t P9N2_EQ_HEARTBEAT_REG = 0x100F0018ull;
+
+static const uint64_t P9N2_EQ_0_HEARTBEAT_REG = 0x100F0018ull;
+
+static const uint64_t P9N2_EQ_1_HEARTBEAT_REG = 0x110F0018ull;
+
+static const uint64_t P9N2_EQ_2_HEARTBEAT_REG = 0x120F0018ull;
+
+static const uint64_t P9N2_EQ_3_HEARTBEAT_REG = 0x130F0018ull;
+
+static const uint64_t P9N2_EQ_4_HEARTBEAT_REG = 0x140F0018ull;
+
+static const uint64_t P9N2_EQ_5_HEARTBEAT_REG = 0x150F0018ull;
+
+static const uint64_t P9N2_EX_HEARTBEAT_REG = 0x200F0018ull;
+//DUPS: 210F0018,
+static const uint64_t P9N2_EX_0_HEARTBEAT_REG = 0x200F0018ull;
+//DUPS: 210F0018,
+static const uint64_t P9N2_EX_1_HEARTBEAT_REG = 0x220F0018ull;
+//DUPS: 220F0018,
+static const uint64_t P9N2_EX_2_HEARTBEAT_REG = 0x240F0018ull;
+//DUPS: 250F0018,
+static const uint64_t P9N2_EX_3_HEARTBEAT_REG = 0x260F0018ull;
+//DUPS: 270F0018,
+static const uint64_t P9N2_EX_4_HEARTBEAT_REG = 0x280F0018ull;
+//DUPS: 290F0018,
+static const uint64_t P9N2_EX_5_HEARTBEAT_REG = 0x2A0F0018ull;
+//DUPS: 2B0F0018,
+static const uint64_t P9N2_EX_6_HEARTBEAT_REG = 0x2C0F0018ull;
+//DUPS: 2D0F0018,
+static const uint64_t P9N2_EX_7_HEARTBEAT_REG = 0x2E0F0018ull;
+//DUPS: 2F0F0018,
+static const uint64_t P9N2_EX_8_HEARTBEAT_REG = 0x300F0018ull;
+//DUPS: 310F0018,
+static const uint64_t P9N2_EX_9_HEARTBEAT_REG = 0x320F0018ull;
+//DUPS: 330F0018,
+static const uint64_t P9N2_EX_10_HEARTBEAT_REG = 0x340F0018ull;
+//DUPS: 350F0018,
+static const uint64_t P9N2_EX_11_HEARTBEAT_REG = 0x360F0018ull;
+//DUPS: 370F0018,
+
+static const uint64_t P9N2_C_HID = 0x20010A01ull;
+
+static const uint64_t P9N2_C_0_HID = 0x20010A01ull;
+
+static const uint64_t P9N2_C_1_HID = 0x21010A01ull;
+
+static const uint64_t P9N2_C_2_HID = 0x22010A01ull;
+
+static const uint64_t P9N2_C_3_HID = 0x23010A01ull;
+
+static const uint64_t P9N2_C_4_HID = 0x24010A01ull;
+
+static const uint64_t P9N2_C_5_HID = 0x25010A01ull;
+
+static const uint64_t P9N2_C_6_HID = 0x26010A01ull;
+
+static const uint64_t P9N2_C_7_HID = 0x27010A01ull;
+
+static const uint64_t P9N2_C_8_HID = 0x28010A01ull;
+
+static const uint64_t P9N2_C_9_HID = 0x29010A01ull;
+
+static const uint64_t P9N2_C_10_HID = 0x2A010A01ull;
+
+static const uint64_t P9N2_C_11_HID = 0x2B010A01ull;
+
+static const uint64_t P9N2_C_12_HID = 0x2C010A01ull;
+
+static const uint64_t P9N2_C_13_HID = 0x2D010A01ull;
+
+static const uint64_t P9N2_C_14_HID = 0x2E010A01ull;
+
+static const uint64_t P9N2_C_15_HID = 0x2F010A01ull;
+
+static const uint64_t P9N2_C_16_HID = 0x30010A01ull;
+
+static const uint64_t P9N2_C_17_HID = 0x31010A01ull;
+
+static const uint64_t P9N2_C_18_HID = 0x32010A01ull;
+
+static const uint64_t P9N2_C_19_HID = 0x33010A01ull;
+
+static const uint64_t P9N2_C_20_HID = 0x34010A01ull;
+
+static const uint64_t P9N2_C_21_HID = 0x35010A01ull;
+
+static const uint64_t P9N2_C_22_HID = 0x36010A01ull;
+
+static const uint64_t P9N2_C_23_HID = 0x37010A01ull;
+
+static const uint64_t P9N2_EX_0_L2_HID = 0x20010A01ull;
+//DUPS: 21010A01,
+static const uint64_t P9N2_EX_10_L2_HID = 0x34010A01ull;
+//DUPS: 35010A01,
+static const uint64_t P9N2_EX_11_L2_HID = 0x36010A01ull;
+//DUPS: 37010A01,
+static const uint64_t P9N2_EX_1_L2_HID = 0x22010A01ull;
+//DUPS: 23010A01,
+static const uint64_t P9N2_EX_2_L2_HID = 0x24010A01ull;
+//DUPS: 25010A01,
+static const uint64_t P9N2_EX_3_L2_HID = 0x26010A01ull;
+//DUPS: 27010A01,
+static const uint64_t P9N2_EX_4_L2_HID = 0x28010A01ull;
+//DUPS: 29010A01,
+static const uint64_t P9N2_EX_5_L2_HID = 0x2A010A01ull;
+//DUPS: 2B010A01,
+static const uint64_t P9N2_EX_6_L2_HID = 0x2C010A01ull;
+//DUPS: 2D010A01,
+static const uint64_t P9N2_EX_7_L2_HID = 0x2F010A01ull;
+//DUPS: 2F010A01,
+static const uint64_t P9N2_EX_8_L2_HID = 0x30010A01ull;
+//DUPS: 31010A01,
+static const uint64_t P9N2_EX_9_L2_HID = 0x32010A01ull;
+//DUPS: 33010A01,
+static const uint64_t P9N2_EX_L2_HID = 0x20010A01ull;
+//DUPS: 21010A01,
+
+static const uint64_t P9N2_C_HMEER = 0x20010A96ull;
+
+static const uint64_t P9N2_C_0_HMEER = 0x20010A96ull;
+
+static const uint64_t P9N2_C_1_HMEER = 0x21010A96ull;
+
+static const uint64_t P9N2_C_2_HMEER = 0x22010A96ull;
+
+static const uint64_t P9N2_C_3_HMEER = 0x23010A96ull;
+
+static const uint64_t P9N2_C_4_HMEER = 0x24010A96ull;
+
+static const uint64_t P9N2_C_5_HMEER = 0x25010A96ull;
+
+static const uint64_t P9N2_C_6_HMEER = 0x26010A96ull;
+
+static const uint64_t P9N2_C_7_HMEER = 0x27010A96ull;
+
+static const uint64_t P9N2_C_8_HMEER = 0x28010A96ull;
+
+static const uint64_t P9N2_C_9_HMEER = 0x29010A96ull;
+
+static const uint64_t P9N2_C_10_HMEER = 0x2A010A96ull;
+
+static const uint64_t P9N2_C_11_HMEER = 0x2B010A96ull;
+
+static const uint64_t P9N2_C_12_HMEER = 0x2C010A96ull;
+
+static const uint64_t P9N2_C_13_HMEER = 0x2D010A96ull;
+
+static const uint64_t P9N2_C_14_HMEER = 0x2E010A96ull;
+
+static const uint64_t P9N2_C_15_HMEER = 0x2F010A96ull;
+
+static const uint64_t P9N2_C_16_HMEER = 0x30010A96ull;
+
+static const uint64_t P9N2_C_17_HMEER = 0x31010A96ull;
+
+static const uint64_t P9N2_C_18_HMEER = 0x32010A96ull;
+
+static const uint64_t P9N2_C_19_HMEER = 0x33010A96ull;
+
+static const uint64_t P9N2_C_20_HMEER = 0x34010A96ull;
+
+static const uint64_t P9N2_C_21_HMEER = 0x35010A96ull;
+
+static const uint64_t P9N2_C_22_HMEER = 0x36010A96ull;
+
+static const uint64_t P9N2_C_23_HMEER = 0x37010A96ull;
+
+static const uint64_t P9N2_EX_0_L2_HMEER = 0x20010A96ull;
+//DUPS: 20010A96,
+static const uint64_t P9N2_EX_10_L2_HMEER = 0x34010A96ull;
+//DUPS: 34010A96,
+static const uint64_t P9N2_EX_11_L2_HMEER = 0x36010A96ull;
+//DUPS: 36010A96,
+static const uint64_t P9N2_EX_1_L2_HMEER = 0x22010A96ull;
+//DUPS: 22010A96,
+static const uint64_t P9N2_EX_2_L2_HMEER = 0x24010A96ull;
+//DUPS: 24010A96,
+static const uint64_t P9N2_EX_3_L2_HMEER = 0x26010A96ull;
+//DUPS: 26010A96,
+static const uint64_t P9N2_EX_4_L2_HMEER = 0x28010A96ull;
+//DUPS: 28010A96,
+static const uint64_t P9N2_EX_5_L2_HMEER = 0x2B010A96ull;
+//DUPS: 2A010A96,
+static const uint64_t P9N2_EX_6_L2_HMEER = 0x2D010A96ull;
+//DUPS: 2C010A96,
+static const uint64_t P9N2_EX_7_L2_HMEER = 0x2F010A96ull;
+//DUPS: 2E010A96,
+static const uint64_t P9N2_EX_8_L2_HMEER = 0x30010A96ull;
+//DUPS: 30010A96,
+static const uint64_t P9N2_EX_9_L2_HMEER = 0x32010A96ull;
+//DUPS: 32010A96,
+static const uint64_t P9N2_EX_L2_HMEER = 0x20010A96ull;
+//DUPS: 20010A96,
+
+static const uint64_t P9N2_C_HOSTATTN = 0x20040009ull;
+
+static const uint64_t P9N2_C_0_HOSTATTN = 0x20040009ull;
+
+static const uint64_t P9N2_C_1_HOSTATTN = 0x21040009ull;
+
+static const uint64_t P9N2_C_2_HOSTATTN = 0x22040009ull;
+
+static const uint64_t P9N2_C_3_HOSTATTN = 0x23040009ull;
+
+static const uint64_t P9N2_C_4_HOSTATTN = 0x24040009ull;
+
+static const uint64_t P9N2_C_5_HOSTATTN = 0x25040009ull;
+
+static const uint64_t P9N2_C_6_HOSTATTN = 0x26040009ull;
+
+static const uint64_t P9N2_C_7_HOSTATTN = 0x27040009ull;
+
+static const uint64_t P9N2_C_8_HOSTATTN = 0x28040009ull;
+
+static const uint64_t P9N2_C_9_HOSTATTN = 0x29040009ull;
+
+static const uint64_t P9N2_C_10_HOSTATTN = 0x2A040009ull;
+
+static const uint64_t P9N2_C_11_HOSTATTN = 0x2B040009ull;
+
+static const uint64_t P9N2_C_12_HOSTATTN = 0x2C040009ull;
+
+static const uint64_t P9N2_C_13_HOSTATTN = 0x2D040009ull;
+
+static const uint64_t P9N2_C_14_HOSTATTN = 0x2E040009ull;
+
+static const uint64_t P9N2_C_15_HOSTATTN = 0x2F040009ull;
+
+static const uint64_t P9N2_C_16_HOSTATTN = 0x30040009ull;
+
+static const uint64_t P9N2_C_17_HOSTATTN = 0x31040009ull;
+
+static const uint64_t P9N2_C_18_HOSTATTN = 0x32040009ull;
+
+static const uint64_t P9N2_C_19_HOSTATTN = 0x33040009ull;
+
+static const uint64_t P9N2_C_20_HOSTATTN = 0x34040009ull;
+
+static const uint64_t P9N2_C_21_HOSTATTN = 0x35040009ull;
+
+static const uint64_t P9N2_C_22_HOSTATTN = 0x36040009ull;
+
+static const uint64_t P9N2_C_23_HOSTATTN = 0x37040009ull;
+
+static const uint64_t P9N2_EQ_HOSTATTN = 0x10040009ull;
+
+static const uint64_t P9N2_EQ_0_HOSTATTN = 0x10040009ull;
+
+static const uint64_t P9N2_EQ_1_HOSTATTN = 0x11040009ull;
+
+static const uint64_t P9N2_EQ_2_HOSTATTN = 0x12040009ull;
+
+static const uint64_t P9N2_EQ_3_HOSTATTN = 0x13040009ull;
+
+static const uint64_t P9N2_EQ_4_HOSTATTN = 0x14040009ull;
+
+static const uint64_t P9N2_EQ_5_HOSTATTN = 0x15040009ull;
+
+static const uint64_t P9N2_EX_HOSTATTN = 0x20040009ull;
+//DUPS: 21040009,
+static const uint64_t P9N2_EX_0_HOSTATTN = 0x20040009ull;
+//DUPS: 21040009,
+static const uint64_t P9N2_EX_1_HOSTATTN = 0x22040009ull;
+//DUPS: 23040009,
+static const uint64_t P9N2_EX_2_HOSTATTN = 0x24040009ull;
+//DUPS: 25040009,
+static const uint64_t P9N2_EX_3_HOSTATTN = 0x26040009ull;
+//DUPS: 27040009,
+static const uint64_t P9N2_EX_4_HOSTATTN = 0x28040009ull;
+//DUPS: 29040009,
+static const uint64_t P9N2_EX_5_HOSTATTN = 0x2A040009ull;
+//DUPS: 2B040009,
+static const uint64_t P9N2_EX_6_HOSTATTN = 0x2C040009ull;
+//DUPS: 2D040009,
+static const uint64_t P9N2_EX_7_HOSTATTN = 0x2F040009ull;
+//DUPS: 2F040009,
+static const uint64_t P9N2_EX_8_HOSTATTN = 0x30040009ull;
+//DUPS: 31040009,
+static const uint64_t P9N2_EX_9_HOSTATTN = 0x32040009ull;
+//DUPS: 33040009,
+static const uint64_t P9N2_EX_10_HOSTATTN = 0x34040009ull;
+//DUPS: 35040009,
+static const uint64_t P9N2_EX_11_HOSTATTN = 0x36040009ull;
+//DUPS: 37040009,
+
+static const uint64_t P9N2_C_HOSTATTN_MASK = 0x2004001Aull;
+
+static const uint64_t P9N2_C_0_HOSTATTN_MASK = 0x2004001Aull;
+
+static const uint64_t P9N2_C_1_HOSTATTN_MASK = 0x2104001Aull;
+
+static const uint64_t P9N2_C_2_HOSTATTN_MASK = 0x2204001Aull;
+
+static const uint64_t P9N2_C_3_HOSTATTN_MASK = 0x2304001Aull;
+
+static const uint64_t P9N2_C_4_HOSTATTN_MASK = 0x2404001Aull;
+
+static const uint64_t P9N2_C_5_HOSTATTN_MASK = 0x2504001Aull;
+
+static const uint64_t P9N2_C_6_HOSTATTN_MASK = 0x2604001Aull;
+
+static const uint64_t P9N2_C_7_HOSTATTN_MASK = 0x2704001Aull;
+
+static const uint64_t P9N2_C_8_HOSTATTN_MASK = 0x2804001Aull;
+
+static const uint64_t P9N2_C_9_HOSTATTN_MASK = 0x2904001Aull;
+
+static const uint64_t P9N2_C_10_HOSTATTN_MASK = 0x2A04001Aull;
+
+static const uint64_t P9N2_C_11_HOSTATTN_MASK = 0x2B04001Aull;
+
+static const uint64_t P9N2_C_12_HOSTATTN_MASK = 0x2C04001Aull;
+
+static const uint64_t P9N2_C_13_HOSTATTN_MASK = 0x2D04001Aull;
+
+static const uint64_t P9N2_C_14_HOSTATTN_MASK = 0x2E04001Aull;
+
+static const uint64_t P9N2_C_15_HOSTATTN_MASK = 0x2F04001Aull;
+
+static const uint64_t P9N2_C_16_HOSTATTN_MASK = 0x3004001Aull;
+
+static const uint64_t P9N2_C_17_HOSTATTN_MASK = 0x3104001Aull;
+
+static const uint64_t P9N2_C_18_HOSTATTN_MASK = 0x3204001Aull;
+
+static const uint64_t P9N2_C_19_HOSTATTN_MASK = 0x3304001Aull;
+
+static const uint64_t P9N2_C_20_HOSTATTN_MASK = 0x3404001Aull;
+
+static const uint64_t P9N2_C_21_HOSTATTN_MASK = 0x3504001Aull;
+
+static const uint64_t P9N2_C_22_HOSTATTN_MASK = 0x3604001Aull;
+
+static const uint64_t P9N2_C_23_HOSTATTN_MASK = 0x3704001Aull;
+
+static const uint64_t P9N2_EQ_HOSTATTN_MASK = 0x1004001Aull;
+
+static const uint64_t P9N2_EQ_0_HOSTATTN_MASK = 0x1004001Aull;
+
+static const uint64_t P9N2_EQ_1_HOSTATTN_MASK = 0x1104001Aull;
+
+static const uint64_t P9N2_EQ_2_HOSTATTN_MASK = 0x1204001Aull;
+
+static const uint64_t P9N2_EQ_3_HOSTATTN_MASK = 0x1304001Aull;
+
+static const uint64_t P9N2_EQ_4_HOSTATTN_MASK = 0x1404001Aull;
+
+static const uint64_t P9N2_EQ_5_HOSTATTN_MASK = 0x1504001Aull;
+
+static const uint64_t P9N2_EX_HOSTATTN_MASK = 0x2004001Aull;
+//DUPS: 2104001A,
+static const uint64_t P9N2_EX_0_HOSTATTN_MASK = 0x2004001Aull;
+//DUPS: 2104001A,
+static const uint64_t P9N2_EX_1_HOSTATTN_MASK = 0x2204001Aull;
+//DUPS: 2304001A,
+static const uint64_t P9N2_EX_2_HOSTATTN_MASK = 0x2404001Aull;
+//DUPS: 2504001A,
+static const uint64_t P9N2_EX_3_HOSTATTN_MASK = 0x2604001Aull;
+//DUPS: 2704001A,
+static const uint64_t P9N2_EX_4_HOSTATTN_MASK = 0x2804001Aull;
+//DUPS: 2904001A,
+static const uint64_t P9N2_EX_5_HOSTATTN_MASK = 0x2A04001Aull;
+//DUPS: 2B04001A,
+static const uint64_t P9N2_EX_6_HOSTATTN_MASK = 0x2C04001Aull;
+//DUPS: 2D04001A,
+static const uint64_t P9N2_EX_7_HOSTATTN_MASK = 0x2F04001Aull;
+//DUPS: 2F04001A,
+static const uint64_t P9N2_EX_8_HOSTATTN_MASK = 0x3004001Aull;
+//DUPS: 3104001A,
+static const uint64_t P9N2_EX_9_HOSTATTN_MASK = 0x3204001Aull;
+//DUPS: 3304001A,
+static const uint64_t P9N2_EX_10_HOSTATTN_MASK = 0x3404001Aull;
+//DUPS: 3504001A,
+static const uint64_t P9N2_EX_11_HOSTATTN_MASK = 0x3604001Aull;
+//DUPS: 3704001A,
+
+static const uint64_t P9N2_C_HRMOR = 0x20010AB9ull;
+
+static const uint64_t P9N2_C_0_HRMOR = 0x20010AB9ull;
+
+static const uint64_t P9N2_C_1_HRMOR = 0x21010AB9ull;
+
+static const uint64_t P9N2_C_2_HRMOR = 0x22010AB9ull;
+
+static const uint64_t P9N2_C_3_HRMOR = 0x23010AB9ull;
+
+static const uint64_t P9N2_C_4_HRMOR = 0x24010AB9ull;
+
+static const uint64_t P9N2_C_5_HRMOR = 0x25010AB9ull;
+
+static const uint64_t P9N2_C_6_HRMOR = 0x26010AB9ull;
+
+static const uint64_t P9N2_C_7_HRMOR = 0x27010AB9ull;
+
+static const uint64_t P9N2_C_8_HRMOR = 0x28010AB9ull;
+
+static const uint64_t P9N2_C_9_HRMOR = 0x29010AB9ull;
+
+static const uint64_t P9N2_C_10_HRMOR = 0x2A010AB9ull;
+
+static const uint64_t P9N2_C_11_HRMOR = 0x2B010AB9ull;
+
+static const uint64_t P9N2_C_12_HRMOR = 0x2C010AB9ull;
+
+static const uint64_t P9N2_C_13_HRMOR = 0x2D010AB9ull;
+
+static const uint64_t P9N2_C_14_HRMOR = 0x2E010AB9ull;
+
+static const uint64_t P9N2_C_15_HRMOR = 0x2F010AB9ull;
+
+static const uint64_t P9N2_C_16_HRMOR = 0x30010AB9ull;
+
+static const uint64_t P9N2_C_17_HRMOR = 0x31010AB9ull;
+
+static const uint64_t P9N2_C_18_HRMOR = 0x32010AB9ull;
+
+static const uint64_t P9N2_C_19_HRMOR = 0x33010AB9ull;
+
+static const uint64_t P9N2_C_20_HRMOR = 0x34010AB9ull;
+
+static const uint64_t P9N2_C_21_HRMOR = 0x35010AB9ull;
+
+static const uint64_t P9N2_C_22_HRMOR = 0x36010AB9ull;
+
+static const uint64_t P9N2_C_23_HRMOR = 0x37010AB9ull;
+
+static const uint64_t P9N2_EX_HRMOR = 0x20010AB9ull;
+//DUPS: 21010AB9,
+static const uint64_t P9N2_EX_0_HRMOR = 0x20010AB9ull;
+//DUPS: 21010AB9,
+static const uint64_t P9N2_EX_1_HRMOR = 0x22010AB9ull;
+//DUPS: 23010AB9,
+static const uint64_t P9N2_EX_2_HRMOR = 0x24010AB9ull;
+//DUPS: 25010AB9,
+static const uint64_t P9N2_EX_3_HRMOR = 0x26010AB9ull;
+//DUPS: 27010AB9,
+static const uint64_t P9N2_EX_4_HRMOR = 0x28010AB9ull;
+//DUPS: 29010AB9,
+static const uint64_t P9N2_EX_5_HRMOR = 0x2A010AB9ull;
+//DUPS: 2B010AB9,
+static const uint64_t P9N2_EX_6_HRMOR = 0x2C010AB9ull;
+//DUPS: 2D010AB9,
+static const uint64_t P9N2_EX_7_HRMOR = 0x2F010AB9ull;
+//DUPS: 2F010AB9,
+static const uint64_t P9N2_EX_8_HRMOR = 0x30010AB9ull;
+//DUPS: 31010AB9,
+static const uint64_t P9N2_EX_9_HRMOR = 0x32010AB9ull;
+//DUPS: 33010AB9,
+static const uint64_t P9N2_EX_10_HRMOR = 0x34010AB9ull;
+//DUPS: 35010AB9,
+static const uint64_t P9N2_EX_11_HRMOR = 0x36010AB9ull;
+//DUPS: 37010AB9,
+
+static const uint64_t P9N2_EQ_HTM_CSEL = 0x10012207ull;
+//DUPS: 10012707, 10012207, 10012307,
+static const uint64_t P9N2_EQ_0_HTM_CSEL = 0x10012207ull;
+//DUPS: 10012707, 10012207, 10012307,
+static const uint64_t P9N2_EQ_1_HTM_CSEL = 0x11012207ull;
+//DUPS: 11012707, 11012207, 11012307,
+static const uint64_t P9N2_EQ_2_HTM_CSEL = 0x12012207ull;
+//DUPS: 12012707, 12012207, 12012307,
+static const uint64_t P9N2_EQ_3_HTM_CSEL = 0x13012207ull;
+//DUPS: 13012707, 13012207, 13012307,
+static const uint64_t P9N2_EQ_4_HTM_CSEL = 0x14012207ull;
+//DUPS: 14012707, 14012207, 14012307,
+static const uint64_t P9N2_EQ_5_HTM_CSEL = 0x15012207ull;
+//DUPS: 15012707, 15012207, 15012307,
+static const uint64_t P9N2_EX_HTM_CSEL = 0x10012207ull;
+//DUPS: 10012307,
+static const uint64_t P9N2_EX_0_HTM_CSEL = 0x10012207ull;
+//DUPS: 10012307,
+static const uint64_t P9N2_EX_2_HTM_CSEL = 0x11012207ull;
+//DUPS: 11012307,
+static const uint64_t P9N2_EX_4_HTM_CSEL = 0x12012207ull;
+//DUPS: 12012307,
+static const uint64_t P9N2_EX_6_HTM_CSEL = 0x13012207ull;
+//DUPS: 13012307,
+static const uint64_t P9N2_EX_8_HTM_CSEL = 0x14012207ull;
+//DUPS: 14012307,
+static const uint64_t P9N2_EX_10_HTM_CSEL = 0x15012207ull;
+//DUPS: 15012307,
+static const uint64_t P9N2_EX_11_CHTMLBS0_HTM_CSEL = 0x15012607ull;
+
+static const uint64_t P9N2_EX_11_CHTMLBS1_HTM_CSEL = 0x15012707ull;
+
+static const uint64_t P9N2_EX_1_CHTMLBS0_HTM_CSEL = 0x10012607ull;
+
+static const uint64_t P9N2_EX_1_CHTMLBS1_HTM_CSEL = 0x10012707ull;
+
+static const uint64_t P9N2_EX_3_CHTMLBS0_HTM_CSEL = 0x11012607ull;
+
+static const uint64_t P9N2_EX_3_CHTMLBS1_HTM_CSEL = 0x11012707ull;
+
+static const uint64_t P9N2_EX_5_CHTMLBS0_HTM_CSEL = 0x12012607ull;
+
+static const uint64_t P9N2_EX_5_CHTMLBS1_HTM_CSEL = 0x12012707ull;
+
+static const uint64_t P9N2_EX_7_CHTMLBS0_HTM_CSEL = 0x13012607ull;
+
+static const uint64_t P9N2_EX_7_CHTMLBS1_HTM_CSEL = 0x13012707ull;
+
+static const uint64_t P9N2_EX_9_CHTMLBS0_HTM_CSEL = 0x14012607ull;
+
+static const uint64_t P9N2_EX_9_CHTMLBS1_HTM_CSEL = 0x14012707ull;
+
+
+static const uint64_t P9N2_EQ_HTM_CTRL = 0x10012205ull;
+//DUPS: 10012705, 10012205, 10012305,
+static const uint64_t P9N2_EQ_0_HTM_CTRL = 0x10012205ull;
+//DUPS: 10012705, 10012205, 10012305,
+static const uint64_t P9N2_EQ_1_HTM_CTRL = 0x11012205ull;
+//DUPS: 11012705, 11012205, 11012305,
+static const uint64_t P9N2_EQ_2_HTM_CTRL = 0x12012205ull;
+//DUPS: 12012705, 12012205, 12012305,
+static const uint64_t P9N2_EQ_3_HTM_CTRL = 0x13012205ull;
+//DUPS: 13012705, 13012205, 13012305,
+static const uint64_t P9N2_EQ_4_HTM_CTRL = 0x14012205ull;
+//DUPS: 14012705, 14012205, 14012305,
+static const uint64_t P9N2_EQ_5_HTM_CTRL = 0x15012205ull;
+//DUPS: 15012705, 15012205, 15012305,
+static const uint64_t P9N2_EX_HTM_CTRL = 0x10012205ull;
+//DUPS: 10012305,
+static const uint64_t P9N2_EX_0_HTM_CTRL = 0x10012205ull;
+//DUPS: 10012305,
+static const uint64_t P9N2_EX_2_HTM_CTRL = 0x11012205ull;
+//DUPS: 11012305,
+static const uint64_t P9N2_EX_4_HTM_CTRL = 0x12012205ull;
+//DUPS: 12012305,
+static const uint64_t P9N2_EX_6_HTM_CTRL = 0x13012205ull;
+//DUPS: 13012305,
+static const uint64_t P9N2_EX_8_HTM_CTRL = 0x14012205ull;
+//DUPS: 14012305,
+static const uint64_t P9N2_EX_10_HTM_CTRL = 0x15012205ull;
+//DUPS: 15012305,
+static const uint64_t P9N2_EX_11_CHTMLBS0_HTM_CTRL = 0x15012605ull;
+
+static const uint64_t P9N2_EX_11_CHTMLBS1_HTM_CTRL = 0x15012705ull;
+
+static const uint64_t P9N2_EX_1_CHTMLBS0_HTM_CTRL = 0x10012605ull;
+
+static const uint64_t P9N2_EX_1_CHTMLBS1_HTM_CTRL = 0x10012705ull;
+
+static const uint64_t P9N2_EX_3_CHTMLBS0_HTM_CTRL = 0x11012605ull;
+
+static const uint64_t P9N2_EX_3_CHTMLBS1_HTM_CTRL = 0x11012705ull;
+
+static const uint64_t P9N2_EX_5_CHTMLBS0_HTM_CTRL = 0x12012605ull;
+
+static const uint64_t P9N2_EX_5_CHTMLBS1_HTM_CTRL = 0x12012705ull;
+
+static const uint64_t P9N2_EX_7_CHTMLBS0_HTM_CTRL = 0x13012605ull;
+
+static const uint64_t P9N2_EX_7_CHTMLBS1_HTM_CTRL = 0x13012705ull;
+
+static const uint64_t P9N2_EX_9_CHTMLBS0_HTM_CTRL = 0x14012605ull;
+
+static const uint64_t P9N2_EX_9_CHTMLBS1_HTM_CTRL = 0x14012705ull;
+
+
+static const uint64_t P9N2_EQ_HTM_IMA_PDBAR = 0x1001220Bull;
+//DUPS: 1001270B, 1001220B, 1001230B,
+static const uint64_t P9N2_EQ_0_HTM_IMA_PDBAR = 0x1001220Bull;
+//DUPS: 1001270B, 1001220B, 1001230B,
+static const uint64_t P9N2_EQ_1_HTM_IMA_PDBAR = 0x1101220Bull;
+//DUPS: 1101270B, 1101220B, 1101230B,
+static const uint64_t P9N2_EQ_2_HTM_IMA_PDBAR = 0x1201220Bull;
+//DUPS: 1201270B, 1201220B, 1201230B,
+static const uint64_t P9N2_EQ_3_HTM_IMA_PDBAR = 0x1301220Bull;
+//DUPS: 1301270B, 1301220B, 1301230B,
+static const uint64_t P9N2_EQ_4_HTM_IMA_PDBAR = 0x1401220Bull;
+//DUPS: 1401270B, 1401220B, 1401230B,
+static const uint64_t P9N2_EQ_5_HTM_IMA_PDBAR = 0x1501220Bull;
+//DUPS: 1501270B, 1501220B, 1501230B,
+static const uint64_t P9N2_EX_HTM_IMA_PDBAR = 0x1001220Bull;
+//DUPS: 1001230B,
+static const uint64_t P9N2_EX_0_HTM_IMA_PDBAR = 0x1001220Bull;
+//DUPS: 1001230B,
+static const uint64_t P9N2_EX_2_HTM_IMA_PDBAR = 0x1101220Bull;
+//DUPS: 1101230B,
+static const uint64_t P9N2_EX_4_HTM_IMA_PDBAR = 0x1201220Bull;
+//DUPS: 1201230B,
+static const uint64_t P9N2_EX_6_HTM_IMA_PDBAR = 0x1301220Bull;
+//DUPS: 1301230B,
+static const uint64_t P9N2_EX_8_HTM_IMA_PDBAR = 0x1401220Bull;
+//DUPS: 1401230B,
+static const uint64_t P9N2_EX_10_HTM_IMA_PDBAR = 0x1501220Bull;
+//DUPS: 1501230B,
+static const uint64_t P9N2_EX_11_CHTMLBS0_HTM_IMA_PDBAR = 0x1501260Bull;
+
+static const uint64_t P9N2_EX_11_CHTMLBS1_HTM_IMA_PDBAR = 0x1501270Bull;
+
+static const uint64_t P9N2_EX_1_CHTMLBS0_HTM_IMA_PDBAR = 0x1001260Bull;
+
+static const uint64_t P9N2_EX_1_CHTMLBS1_HTM_IMA_PDBAR = 0x1001270Bull;
+
+static const uint64_t P9N2_EX_3_CHTMLBS0_HTM_IMA_PDBAR = 0x1101260Bull;
+
+static const uint64_t P9N2_EX_3_CHTMLBS1_HTM_IMA_PDBAR = 0x1101270Bull;
+
+static const uint64_t P9N2_EX_5_CHTMLBS0_HTM_IMA_PDBAR = 0x1201260Bull;
+
+static const uint64_t P9N2_EX_5_CHTMLBS1_HTM_IMA_PDBAR = 0x1201270Bull;
+
+static const uint64_t P9N2_EX_7_CHTMLBS0_HTM_IMA_PDBAR = 0x1301260Bull;
+
+static const uint64_t P9N2_EX_7_CHTMLBS1_HTM_IMA_PDBAR = 0x1301270Bull;
+
+static const uint64_t P9N2_EX_9_CHTMLBS0_HTM_IMA_PDBAR = 0x1401260Bull;
+
+static const uint64_t P9N2_EX_9_CHTMLBS1_HTM_IMA_PDBAR = 0x1401270Bull;
+
+
+static const uint64_t P9N2_EQ_HTM_IMA_STATUS = 0x1001220Aull;
+//DUPS: 1001270A, 1001220A, 1001230A,
+static const uint64_t P9N2_EQ_0_HTM_IMA_STATUS = 0x1001220Aull;
+//DUPS: 1001270A, 1001220A, 1001230A,
+static const uint64_t P9N2_EQ_1_HTM_IMA_STATUS = 0x1101220Aull;
+//DUPS: 1101270A, 1101220A, 1101230A,
+static const uint64_t P9N2_EQ_2_HTM_IMA_STATUS = 0x1201220Aull;
+//DUPS: 1201270A, 1201220A, 1201230A,
+static const uint64_t P9N2_EQ_3_HTM_IMA_STATUS = 0x1301220Aull;
+//DUPS: 1301270A, 1301220A, 1301230A,
+static const uint64_t P9N2_EQ_4_HTM_IMA_STATUS = 0x1401220Aull;
+//DUPS: 1401270A, 1401220A, 1401230A,
+static const uint64_t P9N2_EQ_5_HTM_IMA_STATUS = 0x1501220Aull;
+//DUPS: 1501270A, 1501220A, 1501230A,
+static const uint64_t P9N2_EX_HTM_IMA_STATUS = 0x1001220Aull;
+//DUPS: 1001230A,
+static const uint64_t P9N2_EX_0_HTM_IMA_STATUS = 0x1001220Aull;
+//DUPS: 1001230A,
+static const uint64_t P9N2_EX_2_HTM_IMA_STATUS = 0x1101220Aull;
+//DUPS: 1101230A,
+static const uint64_t P9N2_EX_4_HTM_IMA_STATUS = 0x1201220Aull;
+//DUPS: 1201230A,
+static const uint64_t P9N2_EX_6_HTM_IMA_STATUS = 0x1301220Aull;
+//DUPS: 1301230A,
+static const uint64_t P9N2_EX_8_HTM_IMA_STATUS = 0x1401220Aull;
+//DUPS: 1401230A,
+static const uint64_t P9N2_EX_10_HTM_IMA_STATUS = 0x1501220Aull;
+//DUPS: 1501230A,
+static const uint64_t P9N2_EX_11_CHTMLBS0_HTM_IMA_STATUS = 0x1501260Aull;
+
+static const uint64_t P9N2_EX_11_CHTMLBS1_HTM_IMA_STATUS = 0x1501270Aull;
+
+static const uint64_t P9N2_EX_1_CHTMLBS0_HTM_IMA_STATUS = 0x1001260Aull;
+
+static const uint64_t P9N2_EX_1_CHTMLBS1_HTM_IMA_STATUS = 0x1001270Aull;
+
+static const uint64_t P9N2_EX_3_CHTMLBS0_HTM_IMA_STATUS = 0x1101260Aull;
+
+static const uint64_t P9N2_EX_3_CHTMLBS1_HTM_IMA_STATUS = 0x1101270Aull;
+
+static const uint64_t P9N2_EX_5_CHTMLBS0_HTM_IMA_STATUS = 0x1201260Aull;
+
+static const uint64_t P9N2_EX_5_CHTMLBS1_HTM_IMA_STATUS = 0x1201270Aull;
+
+static const uint64_t P9N2_EX_7_CHTMLBS0_HTM_IMA_STATUS = 0x1301260Aull;
+
+static const uint64_t P9N2_EX_7_CHTMLBS1_HTM_IMA_STATUS = 0x1301270Aull;
+
+static const uint64_t P9N2_EX_9_CHTMLBS0_HTM_IMA_STATUS = 0x1401260Aull;
+
+static const uint64_t P9N2_EX_9_CHTMLBS1_HTM_IMA_STATUS = 0x1401270Aull;
+
+
+static const uint64_t P9N2_EQ_HTM_LAST = 0x10012203ull;
+//DUPS: 10012703, 10012203, 10012303,
+static const uint64_t P9N2_EQ_0_HTM_LAST = 0x10012203ull;
+//DUPS: 10012703, 10012203, 10012303,
+static const uint64_t P9N2_EQ_1_HTM_LAST = 0x11012203ull;
+//DUPS: 11012703, 11012203, 11012303,
+static const uint64_t P9N2_EQ_2_HTM_LAST = 0x12012203ull;
+//DUPS: 12012703, 12012203, 12012303,
+static const uint64_t P9N2_EQ_3_HTM_LAST = 0x13012203ull;
+//DUPS: 13012703, 13012203, 13012303,
+static const uint64_t P9N2_EQ_4_HTM_LAST = 0x14012203ull;
+//DUPS: 14012703, 14012203, 14012303,
+static const uint64_t P9N2_EQ_5_HTM_LAST = 0x15012203ull;
+//DUPS: 15012703, 15012203, 15012303,
+static const uint64_t P9N2_EX_HTM_LAST = 0x10012203ull;
+//DUPS: 10012303,
+static const uint64_t P9N2_EX_0_HTM_LAST = 0x10012203ull;
+//DUPS: 10012303,
+static const uint64_t P9N2_EX_2_HTM_LAST = 0x11012203ull;
+//DUPS: 11012303,
+static const uint64_t P9N2_EX_4_HTM_LAST = 0x12012203ull;
+//DUPS: 12012303,
+static const uint64_t P9N2_EX_6_HTM_LAST = 0x13012203ull;
+//DUPS: 13012303,
+static const uint64_t P9N2_EX_8_HTM_LAST = 0x14012203ull;
+//DUPS: 14012303,
+static const uint64_t P9N2_EX_10_HTM_LAST = 0x15012203ull;
+//DUPS: 15012303,
+static const uint64_t P9N2_EX_11_CHTMLBS0_HTM_LAST = 0x15012603ull;
+
+static const uint64_t P9N2_EX_11_CHTMLBS1_HTM_LAST = 0x15012703ull;
+
+static const uint64_t P9N2_EX_1_CHTMLBS0_HTM_LAST = 0x10012603ull;
+
+static const uint64_t P9N2_EX_1_CHTMLBS1_HTM_LAST = 0x10012703ull;
+
+static const uint64_t P9N2_EX_3_CHTMLBS0_HTM_LAST = 0x11012603ull;
+
+static const uint64_t P9N2_EX_3_CHTMLBS1_HTM_LAST = 0x11012703ull;
+
+static const uint64_t P9N2_EX_5_CHTMLBS0_HTM_LAST = 0x12012603ull;
+
+static const uint64_t P9N2_EX_5_CHTMLBS1_HTM_LAST = 0x12012703ull;
+
+static const uint64_t P9N2_EX_7_CHTMLBS0_HTM_LAST = 0x13012603ull;
+
+static const uint64_t P9N2_EX_7_CHTMLBS1_HTM_LAST = 0x13012703ull;
+
+static const uint64_t P9N2_EX_9_CHTMLBS0_HTM_LAST = 0x14012603ull;
+
+static const uint64_t P9N2_EX_9_CHTMLBS1_HTM_LAST = 0x14012703ull;
+
+
+static const uint64_t P9N2_EQ_HTM_MEM = 0x10012201ull;
+//DUPS: 10012701, 10012201, 10012301,
+static const uint64_t P9N2_EQ_0_HTM_MEM = 0x10012201ull;
+//DUPS: 10012701, 10012201, 10012301,
+static const uint64_t P9N2_EQ_1_HTM_MEM = 0x11012201ull;
+//DUPS: 11012701, 11012201, 11012301,
+static const uint64_t P9N2_EQ_2_HTM_MEM = 0x12012201ull;
+//DUPS: 12012701, 12012201, 12012301,
+static const uint64_t P9N2_EQ_3_HTM_MEM = 0x13012201ull;
+//DUPS: 13012701, 13012201, 13012301,
+static const uint64_t P9N2_EQ_4_HTM_MEM = 0x14012201ull;
+//DUPS: 14012701, 14012201, 14012301,
+static const uint64_t P9N2_EQ_5_HTM_MEM = 0x15012201ull;
+//DUPS: 15012701, 15012201, 15012301,
+static const uint64_t P9N2_EX_HTM_MEM = 0x10012201ull;
+//DUPS: 10012301,
+static const uint64_t P9N2_EX_0_HTM_MEM = 0x10012201ull;
+//DUPS: 10012301,
+static const uint64_t P9N2_EX_2_HTM_MEM = 0x11012201ull;
+//DUPS: 11012301,
+static const uint64_t P9N2_EX_4_HTM_MEM = 0x12012201ull;
+//DUPS: 12012301,
+static const uint64_t P9N2_EX_6_HTM_MEM = 0x13012201ull;
+//DUPS: 13012301,
+static const uint64_t P9N2_EX_8_HTM_MEM = 0x14012201ull;
+//DUPS: 14012301,
+static const uint64_t P9N2_EX_10_HTM_MEM = 0x15012201ull;
+//DUPS: 15012301,
+static const uint64_t P9N2_EX_11_CHTMLBS0_HTM_MEM = 0x15012601ull;
+
+static const uint64_t P9N2_EX_11_CHTMLBS1_HTM_MEM = 0x15012701ull;
+
+static const uint64_t P9N2_EX_1_CHTMLBS0_HTM_MEM = 0x10012601ull;
+
+static const uint64_t P9N2_EX_1_CHTMLBS1_HTM_MEM = 0x10012701ull;
+
+static const uint64_t P9N2_EX_3_CHTMLBS0_HTM_MEM = 0x11012601ull;
+
+static const uint64_t P9N2_EX_3_CHTMLBS1_HTM_MEM = 0x11012701ull;
+
+static const uint64_t P9N2_EX_5_CHTMLBS0_HTM_MEM = 0x12012601ull;
+
+static const uint64_t P9N2_EX_5_CHTMLBS1_HTM_MEM = 0x12012701ull;
+
+static const uint64_t P9N2_EX_7_CHTMLBS0_HTM_MEM = 0x13012601ull;
+
+static const uint64_t P9N2_EX_7_CHTMLBS1_HTM_MEM = 0x13012701ull;
+
+static const uint64_t P9N2_EX_9_CHTMLBS0_HTM_MEM = 0x14012601ull;
+
+static const uint64_t P9N2_EX_9_CHTMLBS1_HTM_MEM = 0x14012701ull;
+
+
+static const uint64_t P9N2_EQ_HTM_MODE = 0x10012200ull;
+//DUPS: 10012700, 10012200, 10012300,
+static const uint64_t P9N2_EQ_0_HTM_MODE = 0x10012200ull;
+//DUPS: 10012700, 10012200, 10012300,
+static const uint64_t P9N2_EQ_1_HTM_MODE = 0x11012200ull;
+//DUPS: 11012700, 11012200, 11012300,
+static const uint64_t P9N2_EQ_2_HTM_MODE = 0x12012200ull;
+//DUPS: 12012700, 12012200, 12012300,
+static const uint64_t P9N2_EQ_3_HTM_MODE = 0x13012200ull;
+//DUPS: 13012700, 13012200, 13012300,
+static const uint64_t P9N2_EQ_4_HTM_MODE = 0x14012200ull;
+//DUPS: 14012700, 14012200, 14012300,
+static const uint64_t P9N2_EQ_5_HTM_MODE = 0x15012200ull;
+//DUPS: 15012700, 15012200, 15012300,
+static const uint64_t P9N2_EX_HTM_MODE = 0x10012200ull;
+//DUPS: 10012300,
+static const uint64_t P9N2_EX_0_HTM_MODE = 0x10012200ull;
+//DUPS: 10012300,
+static const uint64_t P9N2_EX_2_HTM_MODE = 0x11012200ull;
+//DUPS: 11012300,
+static const uint64_t P9N2_EX_4_HTM_MODE = 0x12012200ull;
+//DUPS: 12012300,
+static const uint64_t P9N2_EX_6_HTM_MODE = 0x13012200ull;
+//DUPS: 13012300,
+static const uint64_t P9N2_EX_8_HTM_MODE = 0x14012200ull;
+//DUPS: 14012300,
+static const uint64_t P9N2_EX_10_HTM_MODE = 0x15012200ull;
+//DUPS: 15012300,
+static const uint64_t P9N2_EX_11_CHTMLBS0_HTM_MODE = 0x15012600ull;
+
+static const uint64_t P9N2_EX_11_CHTMLBS1_HTM_MODE = 0x15012700ull;
+
+static const uint64_t P9N2_EX_1_CHTMLBS0_HTM_MODE = 0x10012600ull;
+
+static const uint64_t P9N2_EX_1_CHTMLBS1_HTM_MODE = 0x10012700ull;
+
+static const uint64_t P9N2_EX_3_CHTMLBS0_HTM_MODE = 0x11012600ull;
+
+static const uint64_t P9N2_EX_3_CHTMLBS1_HTM_MODE = 0x11012700ull;
+
+static const uint64_t P9N2_EX_5_CHTMLBS0_HTM_MODE = 0x12012600ull;
+
+static const uint64_t P9N2_EX_5_CHTMLBS1_HTM_MODE = 0x12012700ull;
+
+static const uint64_t P9N2_EX_7_CHTMLBS0_HTM_MODE = 0x13012600ull;
+
+static const uint64_t P9N2_EX_7_CHTMLBS1_HTM_MODE = 0x13012700ull;
+
+static const uint64_t P9N2_EX_9_CHTMLBS0_HTM_MODE = 0x14012600ull;
+
+static const uint64_t P9N2_EX_9_CHTMLBS1_HTM_MODE = 0x14012700ull;
+
+
+static const uint64_t P9N2_EQ_HTM_PTRC = 0x10012206ull;
+//DUPS: 10012706, 10012206, 10012306,
+static const uint64_t P9N2_EQ_0_HTM_PTRC = 0x10012206ull;
+//DUPS: 10012706, 10012206, 10012306,
+static const uint64_t P9N2_EQ_1_HTM_PTRC = 0x11012206ull;
+//DUPS: 11012706, 11012206, 11012306,
+static const uint64_t P9N2_EQ_2_HTM_PTRC = 0x12012206ull;
+//DUPS: 12012706, 12012206, 12012306,
+static const uint64_t P9N2_EQ_3_HTM_PTRC = 0x13012206ull;
+//DUPS: 13012706, 13012206, 13012306,
+static const uint64_t P9N2_EQ_4_HTM_PTRC = 0x14012206ull;
+//DUPS: 14012706, 14012206, 14012306,
+static const uint64_t P9N2_EQ_5_HTM_PTRC = 0x15012206ull;
+//DUPS: 15012706, 15012206, 15012306,
+static const uint64_t P9N2_EX_HTM_PTRC = 0x10012206ull;
+//DUPS: 10012306,
+static const uint64_t P9N2_EX_0_HTM_PTRC = 0x10012206ull;
+//DUPS: 10012306,
+static const uint64_t P9N2_EX_2_HTM_PTRC = 0x11012206ull;
+//DUPS: 11012306,
+static const uint64_t P9N2_EX_4_HTM_PTRC = 0x12012206ull;
+//DUPS: 12012306,
+static const uint64_t P9N2_EX_6_HTM_PTRC = 0x13012206ull;
+//DUPS: 13012306,
+static const uint64_t P9N2_EX_8_HTM_PTRC = 0x14012206ull;
+//DUPS: 14012306,
+static const uint64_t P9N2_EX_10_HTM_PTRC = 0x15012206ull;
+//DUPS: 15012306,
+static const uint64_t P9N2_EX_11_CHTMLBS0_HTM_PTRC = 0x15012606ull;
+
+static const uint64_t P9N2_EX_11_CHTMLBS1_HTM_PTRC = 0x15012706ull;
+
+static const uint64_t P9N2_EX_1_CHTMLBS0_HTM_PTRC = 0x10012606ull;
+
+static const uint64_t P9N2_EX_1_CHTMLBS1_HTM_PTRC = 0x10012706ull;
+
+static const uint64_t P9N2_EX_3_CHTMLBS0_HTM_PTRC = 0x11012606ull;
+
+static const uint64_t P9N2_EX_3_CHTMLBS1_HTM_PTRC = 0x11012706ull;
+
+static const uint64_t P9N2_EX_5_CHTMLBS0_HTM_PTRC = 0x12012606ull;
+
+static const uint64_t P9N2_EX_5_CHTMLBS1_HTM_PTRC = 0x12012706ull;
+
+static const uint64_t P9N2_EX_7_CHTMLBS0_HTM_PTRC = 0x13012606ull;
+
+static const uint64_t P9N2_EX_7_CHTMLBS1_HTM_PTRC = 0x13012706ull;
+
+static const uint64_t P9N2_EX_9_CHTMLBS0_HTM_PTRC = 0x14012606ull;
+
+static const uint64_t P9N2_EX_9_CHTMLBS1_HTM_PTRC = 0x14012706ull;
+
+
+static const uint64_t P9N2_EQ_HTM_STAT = 0x10012202ull;
+//DUPS: 10012702, 10012202, 10012302,
+static const uint64_t P9N2_EQ_0_HTM_STAT = 0x10012202ull;
+//DUPS: 10012702, 10012202, 10012302,
+static const uint64_t P9N2_EQ_1_HTM_STAT = 0x11012202ull;
+//DUPS: 11012702, 11012202, 11012302,
+static const uint64_t P9N2_EQ_2_HTM_STAT = 0x12012202ull;
+//DUPS: 12012702, 12012202, 12012302,
+static const uint64_t P9N2_EQ_3_HTM_STAT = 0x13012202ull;
+//DUPS: 13012702, 13012202, 13012302,
+static const uint64_t P9N2_EQ_4_HTM_STAT = 0x14012202ull;
+//DUPS: 14012702, 14012202, 14012302,
+static const uint64_t P9N2_EQ_5_HTM_STAT = 0x15012202ull;
+//DUPS: 15012702, 15012202, 15012302,
+static const uint64_t P9N2_EX_HTM_STAT = 0x10012202ull;
+//DUPS: 10012302,
+static const uint64_t P9N2_EX_0_HTM_STAT = 0x10012202ull;
+//DUPS: 10012302,
+static const uint64_t P9N2_EX_2_HTM_STAT = 0x11012202ull;
+//DUPS: 11012302,
+static const uint64_t P9N2_EX_4_HTM_STAT = 0x12012202ull;
+//DUPS: 12012302,
+static const uint64_t P9N2_EX_6_HTM_STAT = 0x13012202ull;
+//DUPS: 13012302,
+static const uint64_t P9N2_EX_8_HTM_STAT = 0x14012202ull;
+//DUPS: 14012302,
+static const uint64_t P9N2_EX_10_HTM_STAT = 0x15012202ull;
+//DUPS: 15012302,
+static const uint64_t P9N2_EX_11_CHTMLBS0_HTM_STAT = 0x15012602ull;
+
+static const uint64_t P9N2_EX_11_CHTMLBS1_HTM_STAT = 0x15012702ull;
+
+static const uint64_t P9N2_EX_1_CHTMLBS0_HTM_STAT = 0x10012602ull;
+
+static const uint64_t P9N2_EX_1_CHTMLBS1_HTM_STAT = 0x10012702ull;
+
+static const uint64_t P9N2_EX_3_CHTMLBS0_HTM_STAT = 0x11012602ull;
+
+static const uint64_t P9N2_EX_3_CHTMLBS1_HTM_STAT = 0x11012702ull;
+
+static const uint64_t P9N2_EX_5_CHTMLBS0_HTM_STAT = 0x12012602ull;
+
+static const uint64_t P9N2_EX_5_CHTMLBS1_HTM_STAT = 0x12012702ull;
+
+static const uint64_t P9N2_EX_7_CHTMLBS0_HTM_STAT = 0x13012602ull;
+
+static const uint64_t P9N2_EX_7_CHTMLBS1_HTM_STAT = 0x13012702ull;
+
+static const uint64_t P9N2_EX_9_CHTMLBS0_HTM_STAT = 0x14012602ull;
+
+static const uint64_t P9N2_EX_9_CHTMLBS1_HTM_STAT = 0x14012702ull;
+
+
+static const uint64_t P9N2_EQ_HTM_TRIG = 0x10012204ull;
+//DUPS: 10012704, 10012204, 10012304,
+static const uint64_t P9N2_EQ_0_HTM_TRIG = 0x10012204ull;
+//DUPS: 10012704, 10012204, 10012304,
+static const uint64_t P9N2_EQ_1_HTM_TRIG = 0x11012204ull;
+//DUPS: 11012704, 11012204, 11012304,
+static const uint64_t P9N2_EQ_2_HTM_TRIG = 0x12012204ull;
+//DUPS: 12012704, 12012204, 12012304,
+static const uint64_t P9N2_EQ_3_HTM_TRIG = 0x13012204ull;
+//DUPS: 13012704, 13012204, 13012304,
+static const uint64_t P9N2_EQ_4_HTM_TRIG = 0x14012204ull;
+//DUPS: 14012704, 14012204, 14012304,
+static const uint64_t P9N2_EQ_5_HTM_TRIG = 0x15012204ull;
+//DUPS: 15012704, 15012204, 15012304,
+static const uint64_t P9N2_EX_HTM_TRIG = 0x10012204ull;
+//DUPS: 10012304,
+static const uint64_t P9N2_EX_0_HTM_TRIG = 0x10012204ull;
+//DUPS: 10012304,
+static const uint64_t P9N2_EX_2_HTM_TRIG = 0x11012204ull;
+//DUPS: 11012304,
+static const uint64_t P9N2_EX_4_HTM_TRIG = 0x12012204ull;
+//DUPS: 12012304,
+static const uint64_t P9N2_EX_6_HTM_TRIG = 0x13012204ull;
+//DUPS: 13012304,
+static const uint64_t P9N2_EX_8_HTM_TRIG = 0x14012204ull;
+//DUPS: 14012304,
+static const uint64_t P9N2_EX_10_HTM_TRIG = 0x15012204ull;
+//DUPS: 15012304,
+static const uint64_t P9N2_EX_11_CHTMLBS0_HTM_TRIG = 0x15012604ull;
+
+static const uint64_t P9N2_EX_11_CHTMLBS1_HTM_TRIG = 0x15012704ull;
+
+static const uint64_t P9N2_EX_1_CHTMLBS0_HTM_TRIG = 0x10012604ull;
+
+static const uint64_t P9N2_EX_1_CHTMLBS1_HTM_TRIG = 0x10012704ull;
+
+static const uint64_t P9N2_EX_3_CHTMLBS0_HTM_TRIG = 0x11012604ull;
+
+static const uint64_t P9N2_EX_3_CHTMLBS1_HTM_TRIG = 0x11012704ull;
+
+static const uint64_t P9N2_EX_5_CHTMLBS0_HTM_TRIG = 0x12012604ull;
+
+static const uint64_t P9N2_EX_5_CHTMLBS1_HTM_TRIG = 0x12012704ull;
+
+static const uint64_t P9N2_EX_7_CHTMLBS0_HTM_TRIG = 0x13012604ull;
+
+static const uint64_t P9N2_EX_7_CHTMLBS1_HTM_TRIG = 0x13012704ull;
+
+static const uint64_t P9N2_EX_9_CHTMLBS0_HTM_TRIG = 0x14012604ull;
+
+static const uint64_t P9N2_EX_9_CHTMLBS1_HTM_TRIG = 0x14012704ull;
+
+
+static const uint64_t P9N2_C_HV_STATE = 0x20010AA6ull;
+
+static const uint64_t P9N2_C_0_HV_STATE = 0x20010AA6ull;
+
+static const uint64_t P9N2_C_1_HV_STATE = 0x21010AA6ull;
+
+static const uint64_t P9N2_C_2_HV_STATE = 0x22010AA6ull;
+
+static const uint64_t P9N2_C_3_HV_STATE = 0x23010AA6ull;
+
+static const uint64_t P9N2_C_4_HV_STATE = 0x24010AA6ull;
+
+static const uint64_t P9N2_C_5_HV_STATE = 0x25010AA6ull;
+
+static const uint64_t P9N2_C_6_HV_STATE = 0x26010AA6ull;
+
+static const uint64_t P9N2_C_7_HV_STATE = 0x27010AA6ull;
+
+static const uint64_t P9N2_C_8_HV_STATE = 0x28010AA6ull;
+
+static const uint64_t P9N2_C_9_HV_STATE = 0x29010AA6ull;
+
+static const uint64_t P9N2_C_10_HV_STATE = 0x2A010AA6ull;
+
+static const uint64_t P9N2_C_11_HV_STATE = 0x2B010AA6ull;
+
+static const uint64_t P9N2_C_12_HV_STATE = 0x2C010AA6ull;
+
+static const uint64_t P9N2_C_13_HV_STATE = 0x2D010AA6ull;
+
+static const uint64_t P9N2_C_14_HV_STATE = 0x2E010AA6ull;
+
+static const uint64_t P9N2_C_15_HV_STATE = 0x2F010AA6ull;
+
+static const uint64_t P9N2_C_16_HV_STATE = 0x30010AA6ull;
+
+static const uint64_t P9N2_C_17_HV_STATE = 0x31010AA6ull;
+
+static const uint64_t P9N2_C_18_HV_STATE = 0x32010AA6ull;
+
+static const uint64_t P9N2_C_19_HV_STATE = 0x33010AA6ull;
+
+static const uint64_t P9N2_C_20_HV_STATE = 0x34010AA6ull;
+
+static const uint64_t P9N2_C_21_HV_STATE = 0x35010AA6ull;
+
+static const uint64_t P9N2_C_22_HV_STATE = 0x36010AA6ull;
+
+static const uint64_t P9N2_C_23_HV_STATE = 0x37010AA6ull;
+
+static const uint64_t P9N2_EX_0_L2_HV_STATE = 0x20010AA6ull;
+//DUPS: 21010AA6,
+static const uint64_t P9N2_EX_10_L2_HV_STATE = 0x34010AA6ull;
+//DUPS: 35010AA6,
+static const uint64_t P9N2_EX_11_L2_HV_STATE = 0x36010AA6ull;
+//DUPS: 37010AA6,
+static const uint64_t P9N2_EX_1_L2_HV_STATE = 0x22010AA6ull;
+//DUPS: 23010AA6,
+static const uint64_t P9N2_EX_2_L2_HV_STATE = 0x24010AA6ull;
+//DUPS: 25010AA6,
+static const uint64_t P9N2_EX_3_L2_HV_STATE = 0x26010AA6ull;
+//DUPS: 27010AA6,
+static const uint64_t P9N2_EX_4_L2_HV_STATE = 0x28010AA6ull;
+//DUPS: 29010AA6,
+static const uint64_t P9N2_EX_5_L2_HV_STATE = 0x2A010AA6ull;
+//DUPS: 2B010AA6,
+static const uint64_t P9N2_EX_6_L2_HV_STATE = 0x2C010AA6ull;
+//DUPS: 2D010AA6,
+static const uint64_t P9N2_EX_7_L2_HV_STATE = 0x2F010AA6ull;
+//DUPS: 2F010AA6,
+static const uint64_t P9N2_EX_8_L2_HV_STATE = 0x30010AA6ull;
+//DUPS: 31010AA6,
+static const uint64_t P9N2_EX_9_L2_HV_STATE = 0x32010AA6ull;
+//DUPS: 33010AA6,
+static const uint64_t P9N2_EX_L2_HV_STATE = 0x20010AA6ull;
+//DUPS: 21010AA6,
+
+static const uint64_t P9N2_C_IFU_HOLD_OUT_0 = 0x20010C00ull;
+
+static const uint64_t P9N2_C_0_IFU_HOLD_OUT_0 = 0x20010C00ull;
+
+static const uint64_t P9N2_C_1_IFU_HOLD_OUT_0 = 0x21010C00ull;
+
+static const uint64_t P9N2_C_2_IFU_HOLD_OUT_0 = 0x22010C00ull;
+
+static const uint64_t P9N2_C_3_IFU_HOLD_OUT_0 = 0x23010C00ull;
+
+static const uint64_t P9N2_C_4_IFU_HOLD_OUT_0 = 0x24010C00ull;
+
+static const uint64_t P9N2_C_5_IFU_HOLD_OUT_0 = 0x25010C00ull;
+
+static const uint64_t P9N2_C_6_IFU_HOLD_OUT_0 = 0x26010C00ull;
+
+static const uint64_t P9N2_C_7_IFU_HOLD_OUT_0 = 0x27010C00ull;
+
+static const uint64_t P9N2_C_8_IFU_HOLD_OUT_0 = 0x28010C00ull;
+
+static const uint64_t P9N2_C_9_IFU_HOLD_OUT_0 = 0x29010C00ull;
+
+static const uint64_t P9N2_C_10_IFU_HOLD_OUT_0 = 0x2A010C00ull;
+
+static const uint64_t P9N2_C_11_IFU_HOLD_OUT_0 = 0x2B010C00ull;
+
+static const uint64_t P9N2_C_12_IFU_HOLD_OUT_0 = 0x2C010C00ull;
+
+static const uint64_t P9N2_C_13_IFU_HOLD_OUT_0 = 0x2D010C00ull;
+
+static const uint64_t P9N2_C_14_IFU_HOLD_OUT_0 = 0x2E010C00ull;
+
+static const uint64_t P9N2_C_15_IFU_HOLD_OUT_0 = 0x2F010C00ull;
+
+static const uint64_t P9N2_C_16_IFU_HOLD_OUT_0 = 0x30010C00ull;
+
+static const uint64_t P9N2_C_17_IFU_HOLD_OUT_0 = 0x31010C00ull;
+
+static const uint64_t P9N2_C_18_IFU_HOLD_OUT_0 = 0x32010C00ull;
+
+static const uint64_t P9N2_C_19_IFU_HOLD_OUT_0 = 0x33010C00ull;
+
+static const uint64_t P9N2_C_20_IFU_HOLD_OUT_0 = 0x34010C00ull;
+
+static const uint64_t P9N2_C_21_IFU_HOLD_OUT_0 = 0x35010C00ull;
+
+static const uint64_t P9N2_C_22_IFU_HOLD_OUT_0 = 0x36010C00ull;
+
+static const uint64_t P9N2_C_23_IFU_HOLD_OUT_0 = 0x37010C00ull;
+
+static const uint64_t P9N2_EX_0_L2_IFU_HOLD_OUT_0 = 0x20010C00ull;
+//DUPS: 21010C00,
+static const uint64_t P9N2_EX_10_L2_IFU_HOLD_OUT_0 = 0x34010C00ull;
+//DUPS: 35010C00,
+static const uint64_t P9N2_EX_11_L2_IFU_HOLD_OUT_0 = 0x36010C00ull;
+//DUPS: 37010C00,
+static const uint64_t P9N2_EX_1_L2_IFU_HOLD_OUT_0 = 0x22010C00ull;
+//DUPS: 23010C00,
+static const uint64_t P9N2_EX_2_L2_IFU_HOLD_OUT_0 = 0x24010C00ull;
+//DUPS: 25010C00,
+static const uint64_t P9N2_EX_3_L2_IFU_HOLD_OUT_0 = 0x26010C00ull;
+//DUPS: 27010C00,
+static const uint64_t P9N2_EX_4_L2_IFU_HOLD_OUT_0 = 0x28010C00ull;
+//DUPS: 29010C00,
+static const uint64_t P9N2_EX_5_L2_IFU_HOLD_OUT_0 = 0x2A010C00ull;
+//DUPS: 2B010C00,
+static const uint64_t P9N2_EX_6_L2_IFU_HOLD_OUT_0 = 0x2C010C00ull;
+//DUPS: 2D010C00,
+static const uint64_t P9N2_EX_7_L2_IFU_HOLD_OUT_0 = 0x2F010C00ull;
+//DUPS: 2F010C00,
+static const uint64_t P9N2_EX_8_L2_IFU_HOLD_OUT_0 = 0x30010C00ull;
+//DUPS: 31010C00,
+static const uint64_t P9N2_EX_9_L2_IFU_HOLD_OUT_0 = 0x32010C00ull;
+//DUPS: 33010C00,
+static const uint64_t P9N2_EX_L2_IFU_HOLD_OUT_0 = 0x20010C00ull;
+//DUPS: 21010C00,
+
+static const uint64_t P9N2_C_IFU_HOLD_OUT_1 = 0x20010C01ull;
+
+static const uint64_t P9N2_C_0_IFU_HOLD_OUT_1 = 0x20010C01ull;
+
+static const uint64_t P9N2_C_1_IFU_HOLD_OUT_1 = 0x21010C01ull;
+
+static const uint64_t P9N2_C_2_IFU_HOLD_OUT_1 = 0x22010C01ull;
+
+static const uint64_t P9N2_C_3_IFU_HOLD_OUT_1 = 0x23010C01ull;
+
+static const uint64_t P9N2_C_4_IFU_HOLD_OUT_1 = 0x24010C01ull;
+
+static const uint64_t P9N2_C_5_IFU_HOLD_OUT_1 = 0x25010C01ull;
+
+static const uint64_t P9N2_C_6_IFU_HOLD_OUT_1 = 0x26010C01ull;
+
+static const uint64_t P9N2_C_7_IFU_HOLD_OUT_1 = 0x27010C01ull;
+
+static const uint64_t P9N2_C_8_IFU_HOLD_OUT_1 = 0x28010C01ull;
+
+static const uint64_t P9N2_C_9_IFU_HOLD_OUT_1 = 0x29010C01ull;
+
+static const uint64_t P9N2_C_10_IFU_HOLD_OUT_1 = 0x2A010C01ull;
+
+static const uint64_t P9N2_C_11_IFU_HOLD_OUT_1 = 0x2B010C01ull;
+
+static const uint64_t P9N2_C_12_IFU_HOLD_OUT_1 = 0x2C010C01ull;
+
+static const uint64_t P9N2_C_13_IFU_HOLD_OUT_1 = 0x2D010C01ull;
+
+static const uint64_t P9N2_C_14_IFU_HOLD_OUT_1 = 0x2E010C01ull;
+
+static const uint64_t P9N2_C_15_IFU_HOLD_OUT_1 = 0x2F010C01ull;
+
+static const uint64_t P9N2_C_16_IFU_HOLD_OUT_1 = 0x30010C01ull;
+
+static const uint64_t P9N2_C_17_IFU_HOLD_OUT_1 = 0x31010C01ull;
+
+static const uint64_t P9N2_C_18_IFU_HOLD_OUT_1 = 0x32010C01ull;
+
+static const uint64_t P9N2_C_19_IFU_HOLD_OUT_1 = 0x33010C01ull;
+
+static const uint64_t P9N2_C_20_IFU_HOLD_OUT_1 = 0x34010C01ull;
+
+static const uint64_t P9N2_C_21_IFU_HOLD_OUT_1 = 0x35010C01ull;
+
+static const uint64_t P9N2_C_22_IFU_HOLD_OUT_1 = 0x36010C01ull;
+
+static const uint64_t P9N2_C_23_IFU_HOLD_OUT_1 = 0x37010C01ull;
+
+static const uint64_t P9N2_EX_0_L2_IFU_HOLD_OUT_1 = 0x20010C01ull;
+//DUPS: 21010C01,
+static const uint64_t P9N2_EX_10_L2_IFU_HOLD_OUT_1 = 0x34010C01ull;
+//DUPS: 35010C01,
+static const uint64_t P9N2_EX_11_L2_IFU_HOLD_OUT_1 = 0x36010C01ull;
+//DUPS: 37010C01,
+static const uint64_t P9N2_EX_1_L2_IFU_HOLD_OUT_1 = 0x22010C01ull;
+//DUPS: 23010C01,
+static const uint64_t P9N2_EX_2_L2_IFU_HOLD_OUT_1 = 0x24010C01ull;
+//DUPS: 25010C01,
+static const uint64_t P9N2_EX_3_L2_IFU_HOLD_OUT_1 = 0x26010C01ull;
+//DUPS: 27010C01,
+static const uint64_t P9N2_EX_4_L2_IFU_HOLD_OUT_1 = 0x28010C01ull;
+//DUPS: 29010C01,
+static const uint64_t P9N2_EX_5_L2_IFU_HOLD_OUT_1 = 0x2A010C01ull;
+//DUPS: 2B010C01,
+static const uint64_t P9N2_EX_6_L2_IFU_HOLD_OUT_1 = 0x2C010C01ull;
+//DUPS: 2D010C01,
+static const uint64_t P9N2_EX_7_L2_IFU_HOLD_OUT_1 = 0x2F010C01ull;
+//DUPS: 2F010C01,
+static const uint64_t P9N2_EX_8_L2_IFU_HOLD_OUT_1 = 0x30010C01ull;
+//DUPS: 31010C01,
+static const uint64_t P9N2_EX_9_L2_IFU_HOLD_OUT_1 = 0x32010C01ull;
+//DUPS: 33010C01,
+static const uint64_t P9N2_EX_L2_IFU_HOLD_OUT_1 = 0x20010C01ull;
+//DUPS: 21010C01,
+
+static const uint64_t P9N2_C_IFU_HOLD_OUT_2 = 0x20010C02ull;
+
+static const uint64_t P9N2_C_0_IFU_HOLD_OUT_2 = 0x20010C02ull;
+
+static const uint64_t P9N2_C_1_IFU_HOLD_OUT_2 = 0x21010C02ull;
+
+static const uint64_t P9N2_C_2_IFU_HOLD_OUT_2 = 0x22010C02ull;
+
+static const uint64_t P9N2_C_3_IFU_HOLD_OUT_2 = 0x23010C02ull;
+
+static const uint64_t P9N2_C_4_IFU_HOLD_OUT_2 = 0x24010C02ull;
+
+static const uint64_t P9N2_C_5_IFU_HOLD_OUT_2 = 0x25010C02ull;
+
+static const uint64_t P9N2_C_6_IFU_HOLD_OUT_2 = 0x26010C02ull;
+
+static const uint64_t P9N2_C_7_IFU_HOLD_OUT_2 = 0x27010C02ull;
+
+static const uint64_t P9N2_C_8_IFU_HOLD_OUT_2 = 0x28010C02ull;
+
+static const uint64_t P9N2_C_9_IFU_HOLD_OUT_2 = 0x29010C02ull;
+
+static const uint64_t P9N2_C_10_IFU_HOLD_OUT_2 = 0x2A010C02ull;
+
+static const uint64_t P9N2_C_11_IFU_HOLD_OUT_2 = 0x2B010C02ull;
+
+static const uint64_t P9N2_C_12_IFU_HOLD_OUT_2 = 0x2C010C02ull;
+
+static const uint64_t P9N2_C_13_IFU_HOLD_OUT_2 = 0x2D010C02ull;
+
+static const uint64_t P9N2_C_14_IFU_HOLD_OUT_2 = 0x2E010C02ull;
+
+static const uint64_t P9N2_C_15_IFU_HOLD_OUT_2 = 0x2F010C02ull;
+
+static const uint64_t P9N2_C_16_IFU_HOLD_OUT_2 = 0x30010C02ull;
+
+static const uint64_t P9N2_C_17_IFU_HOLD_OUT_2 = 0x31010C02ull;
+
+static const uint64_t P9N2_C_18_IFU_HOLD_OUT_2 = 0x32010C02ull;
+
+static const uint64_t P9N2_C_19_IFU_HOLD_OUT_2 = 0x33010C02ull;
+
+static const uint64_t P9N2_C_20_IFU_HOLD_OUT_2 = 0x34010C02ull;
+
+static const uint64_t P9N2_C_21_IFU_HOLD_OUT_2 = 0x35010C02ull;
+
+static const uint64_t P9N2_C_22_IFU_HOLD_OUT_2 = 0x36010C02ull;
+
+static const uint64_t P9N2_C_23_IFU_HOLD_OUT_2 = 0x37010C02ull;
+
+static const uint64_t P9N2_EX_0_L2_IFU_HOLD_OUT_2 = 0x20010C02ull;
+//DUPS: 21010C02,
+static const uint64_t P9N2_EX_10_L2_IFU_HOLD_OUT_2 = 0x34010C02ull;
+//DUPS: 35010C02,
+static const uint64_t P9N2_EX_11_L2_IFU_HOLD_OUT_2 = 0x36010C02ull;
+//DUPS: 37010C02,
+static const uint64_t P9N2_EX_1_L2_IFU_HOLD_OUT_2 = 0x22010C02ull;
+//DUPS: 23010C02,
+static const uint64_t P9N2_EX_2_L2_IFU_HOLD_OUT_2 = 0x24010C02ull;
+//DUPS: 25010C02,
+static const uint64_t P9N2_EX_3_L2_IFU_HOLD_OUT_2 = 0x26010C02ull;
+//DUPS: 27010C02,
+static const uint64_t P9N2_EX_4_L2_IFU_HOLD_OUT_2 = 0x28010C02ull;
+//DUPS: 29010C02,
+static const uint64_t P9N2_EX_5_L2_IFU_HOLD_OUT_2 = 0x2A010C02ull;
+//DUPS: 2B010C02,
+static const uint64_t P9N2_EX_6_L2_IFU_HOLD_OUT_2 = 0x2C010C02ull;
+//DUPS: 2D010C02,
+static const uint64_t P9N2_EX_7_L2_IFU_HOLD_OUT_2 = 0x2F010C02ull;
+//DUPS: 2F010C02,
+static const uint64_t P9N2_EX_8_L2_IFU_HOLD_OUT_2 = 0x30010C02ull;
+//DUPS: 31010C02,
+static const uint64_t P9N2_EX_9_L2_IFU_HOLD_OUT_2 = 0x32010C02ull;
+//DUPS: 33010C02,
+static const uint64_t P9N2_EX_L2_IFU_HOLD_OUT_2 = 0x20010C02ull;
+//DUPS: 21010C02,
+
+static const uint64_t P9N2_C_IFU_HOLD_OUT_3 = 0x20010C03ull;
+
+static const uint64_t P9N2_C_0_IFU_HOLD_OUT_3 = 0x20010C03ull;
+
+static const uint64_t P9N2_C_1_IFU_HOLD_OUT_3 = 0x21010C03ull;
+
+static const uint64_t P9N2_C_2_IFU_HOLD_OUT_3 = 0x22010C03ull;
+
+static const uint64_t P9N2_C_3_IFU_HOLD_OUT_3 = 0x23010C03ull;
+
+static const uint64_t P9N2_C_4_IFU_HOLD_OUT_3 = 0x24010C03ull;
+
+static const uint64_t P9N2_C_5_IFU_HOLD_OUT_3 = 0x25010C03ull;
+
+static const uint64_t P9N2_C_6_IFU_HOLD_OUT_3 = 0x26010C03ull;
+
+static const uint64_t P9N2_C_7_IFU_HOLD_OUT_3 = 0x27010C03ull;
+
+static const uint64_t P9N2_C_8_IFU_HOLD_OUT_3 = 0x28010C03ull;
+
+static const uint64_t P9N2_C_9_IFU_HOLD_OUT_3 = 0x29010C03ull;
+
+static const uint64_t P9N2_C_10_IFU_HOLD_OUT_3 = 0x2A010C03ull;
+
+static const uint64_t P9N2_C_11_IFU_HOLD_OUT_3 = 0x2B010C03ull;
+
+static const uint64_t P9N2_C_12_IFU_HOLD_OUT_3 = 0x2C010C03ull;
+
+static const uint64_t P9N2_C_13_IFU_HOLD_OUT_3 = 0x2D010C03ull;
+
+static const uint64_t P9N2_C_14_IFU_HOLD_OUT_3 = 0x2E010C03ull;
+
+static const uint64_t P9N2_C_15_IFU_HOLD_OUT_3 = 0x2F010C03ull;
+
+static const uint64_t P9N2_C_16_IFU_HOLD_OUT_3 = 0x30010C03ull;
+
+static const uint64_t P9N2_C_17_IFU_HOLD_OUT_3 = 0x31010C03ull;
+
+static const uint64_t P9N2_C_18_IFU_HOLD_OUT_3 = 0x32010C03ull;
+
+static const uint64_t P9N2_C_19_IFU_HOLD_OUT_3 = 0x33010C03ull;
+
+static const uint64_t P9N2_C_20_IFU_HOLD_OUT_3 = 0x34010C03ull;
+
+static const uint64_t P9N2_C_21_IFU_HOLD_OUT_3 = 0x35010C03ull;
+
+static const uint64_t P9N2_C_22_IFU_HOLD_OUT_3 = 0x36010C03ull;
+
+static const uint64_t P9N2_C_23_IFU_HOLD_OUT_3 = 0x37010C03ull;
+
+static const uint64_t P9N2_EX_0_L2_IFU_HOLD_OUT_3 = 0x20010C03ull;
+//DUPS: 21010C03,
+static const uint64_t P9N2_EX_10_L2_IFU_HOLD_OUT_3 = 0x34010C03ull;
+//DUPS: 35010C03,
+static const uint64_t P9N2_EX_11_L2_IFU_HOLD_OUT_3 = 0x36010C03ull;
+//DUPS: 37010C03,
+static const uint64_t P9N2_EX_1_L2_IFU_HOLD_OUT_3 = 0x22010C03ull;
+//DUPS: 23010C03,
+static const uint64_t P9N2_EX_2_L2_IFU_HOLD_OUT_3 = 0x24010C03ull;
+//DUPS: 25010C03,
+static const uint64_t P9N2_EX_3_L2_IFU_HOLD_OUT_3 = 0x26010C03ull;
+//DUPS: 27010C03,
+static const uint64_t P9N2_EX_4_L2_IFU_HOLD_OUT_3 = 0x28010C03ull;
+//DUPS: 29010C03,
+static const uint64_t P9N2_EX_5_L2_IFU_HOLD_OUT_3 = 0x2A010C03ull;
+//DUPS: 2B010C03,
+static const uint64_t P9N2_EX_6_L2_IFU_HOLD_OUT_3 = 0x2C010C03ull;
+//DUPS: 2D010C03,
+static const uint64_t P9N2_EX_7_L2_IFU_HOLD_OUT_3 = 0x2F010C03ull;
+//DUPS: 2F010C03,
+static const uint64_t P9N2_EX_8_L2_IFU_HOLD_OUT_3 = 0x30010C03ull;
+//DUPS: 31010C03,
+static const uint64_t P9N2_EX_9_L2_IFU_HOLD_OUT_3 = 0x32010C03ull;
+//DUPS: 33010C03,
+static const uint64_t P9N2_EX_L2_IFU_HOLD_OUT_3 = 0x20010C03ull;
+//DUPS: 21010C03,
+
+static const uint64_t P9N2_C_IMA_EVENT_MASK = 0x20010AA8ull;
+
+static const uint64_t P9N2_C_0_IMA_EVENT_MASK = 0x20010AA8ull;
+
+static const uint64_t P9N2_C_1_IMA_EVENT_MASK = 0x21010AA8ull;
+
+static const uint64_t P9N2_C_2_IMA_EVENT_MASK = 0x22010AA8ull;
+
+static const uint64_t P9N2_C_3_IMA_EVENT_MASK = 0x23010AA8ull;
+
+static const uint64_t P9N2_C_4_IMA_EVENT_MASK = 0x24010AA8ull;
+
+static const uint64_t P9N2_C_5_IMA_EVENT_MASK = 0x25010AA8ull;
+
+static const uint64_t P9N2_C_6_IMA_EVENT_MASK = 0x26010AA8ull;
+
+static const uint64_t P9N2_C_7_IMA_EVENT_MASK = 0x27010AA8ull;
+
+static const uint64_t P9N2_C_8_IMA_EVENT_MASK = 0x28010AA8ull;
+
+static const uint64_t P9N2_C_9_IMA_EVENT_MASK = 0x29010AA8ull;
+
+static const uint64_t P9N2_C_10_IMA_EVENT_MASK = 0x2A010AA8ull;
+
+static const uint64_t P9N2_C_11_IMA_EVENT_MASK = 0x2B010AA8ull;
+
+static const uint64_t P9N2_C_12_IMA_EVENT_MASK = 0x2C010AA8ull;
+
+static const uint64_t P9N2_C_13_IMA_EVENT_MASK = 0x2D010AA8ull;
+
+static const uint64_t P9N2_C_14_IMA_EVENT_MASK = 0x2E010AA8ull;
+
+static const uint64_t P9N2_C_15_IMA_EVENT_MASK = 0x2F010AA8ull;
+
+static const uint64_t P9N2_C_16_IMA_EVENT_MASK = 0x30010AA8ull;
+
+static const uint64_t P9N2_C_17_IMA_EVENT_MASK = 0x31010AA8ull;
+
+static const uint64_t P9N2_C_18_IMA_EVENT_MASK = 0x32010AA8ull;
+
+static const uint64_t P9N2_C_19_IMA_EVENT_MASK = 0x33010AA8ull;
+
+static const uint64_t P9N2_C_20_IMA_EVENT_MASK = 0x34010AA8ull;
+
+static const uint64_t P9N2_C_21_IMA_EVENT_MASK = 0x35010AA8ull;
+
+static const uint64_t P9N2_C_22_IMA_EVENT_MASK = 0x36010AA8ull;
+
+static const uint64_t P9N2_C_23_IMA_EVENT_MASK = 0x37010AA8ull;
+
+static const uint64_t P9N2_EX_IMA_EVENT_MASK = 0x20010AA8ull;
+//DUPS: 21010AA8,
+static const uint64_t P9N2_EX_0_IMA_EVENT_MASK = 0x20010AA8ull;
+//DUPS: 21010AA8,
+static const uint64_t P9N2_EX_1_IMA_EVENT_MASK = 0x22010AA8ull;
+//DUPS: 23010AA8,
+static const uint64_t P9N2_EX_2_IMA_EVENT_MASK = 0x24010AA8ull;
+//DUPS: 25010AA8,
+static const uint64_t P9N2_EX_3_IMA_EVENT_MASK = 0x26010AA8ull;
+//DUPS: 27010AA8,
+static const uint64_t P9N2_EX_4_IMA_EVENT_MASK = 0x28010AA8ull;
+//DUPS: 29010AA8,
+static const uint64_t P9N2_EX_5_IMA_EVENT_MASK = 0x2A010AA8ull;
+//DUPS: 2B010AA8,
+static const uint64_t P9N2_EX_6_IMA_EVENT_MASK = 0x2C010AA8ull;
+//DUPS: 2D010AA8,
+static const uint64_t P9N2_EX_7_IMA_EVENT_MASK = 0x2F010AA8ull;
+//DUPS: 2F010AA8,
+static const uint64_t P9N2_EX_8_IMA_EVENT_MASK = 0x30010AA8ull;
+//DUPS: 31010AA8,
+static const uint64_t P9N2_EX_9_IMA_EVENT_MASK = 0x32010AA8ull;
+//DUPS: 33010AA8,
+static const uint64_t P9N2_EX_10_IMA_EVENT_MASK = 0x34010AA8ull;
+//DUPS: 35010AA8,
+static const uint64_t P9N2_EX_11_IMA_EVENT_MASK = 0x36010AA8ull;
+//DUPS: 37010AA8,
+
+static const uint64_t P9N2_C_IMA_TRACE = 0x20010AA9ull;
+
+static const uint64_t P9N2_C_0_IMA_TRACE = 0x20010AA9ull;
+
+static const uint64_t P9N2_C_1_IMA_TRACE = 0x21010AA9ull;
+
+static const uint64_t P9N2_C_2_IMA_TRACE = 0x22010AA9ull;
+
+static const uint64_t P9N2_C_3_IMA_TRACE = 0x23010AA9ull;
+
+static const uint64_t P9N2_C_4_IMA_TRACE = 0x24010AA9ull;
+
+static const uint64_t P9N2_C_5_IMA_TRACE = 0x25010AA9ull;
+
+static const uint64_t P9N2_C_6_IMA_TRACE = 0x26010AA9ull;
+
+static const uint64_t P9N2_C_7_IMA_TRACE = 0x27010AA9ull;
+
+static const uint64_t P9N2_C_8_IMA_TRACE = 0x28010AA9ull;
+
+static const uint64_t P9N2_C_9_IMA_TRACE = 0x29010AA9ull;
+
+static const uint64_t P9N2_C_10_IMA_TRACE = 0x2A010AA9ull;
+
+static const uint64_t P9N2_C_11_IMA_TRACE = 0x2B010AA9ull;
+
+static const uint64_t P9N2_C_12_IMA_TRACE = 0x2C010AA9ull;
+
+static const uint64_t P9N2_C_13_IMA_TRACE = 0x2D010AA9ull;
+
+static const uint64_t P9N2_C_14_IMA_TRACE = 0x2E010AA9ull;
+
+static const uint64_t P9N2_C_15_IMA_TRACE = 0x2F010AA9ull;
+
+static const uint64_t P9N2_C_16_IMA_TRACE = 0x30010AA9ull;
+
+static const uint64_t P9N2_C_17_IMA_TRACE = 0x31010AA9ull;
+
+static const uint64_t P9N2_C_18_IMA_TRACE = 0x32010AA9ull;
+
+static const uint64_t P9N2_C_19_IMA_TRACE = 0x33010AA9ull;
+
+static const uint64_t P9N2_C_20_IMA_TRACE = 0x34010AA9ull;
+
+static const uint64_t P9N2_C_21_IMA_TRACE = 0x35010AA9ull;
+
+static const uint64_t P9N2_C_22_IMA_TRACE = 0x36010AA9ull;
+
+static const uint64_t P9N2_C_23_IMA_TRACE = 0x37010AA9ull;
+
+static const uint64_t P9N2_EX_IMA_TRACE = 0x20010AA9ull;
+//DUPS: 21010AA9,
+static const uint64_t P9N2_EX_0_IMA_TRACE = 0x20010AA9ull;
+//DUPS: 21010AA9,
+static const uint64_t P9N2_EX_1_IMA_TRACE = 0x22010AA9ull;
+//DUPS: 23010AA9,
+static const uint64_t P9N2_EX_2_IMA_TRACE = 0x24010AA9ull;
+//DUPS: 25010AA9,
+static const uint64_t P9N2_EX_3_IMA_TRACE = 0x26010AA9ull;
+//DUPS: 27010AA9,
+static const uint64_t P9N2_EX_4_IMA_TRACE = 0x28010AA9ull;
+//DUPS: 29010AA9,
+static const uint64_t P9N2_EX_5_IMA_TRACE = 0x2A010AA9ull;
+//DUPS: 2B010AA9,
+static const uint64_t P9N2_EX_6_IMA_TRACE = 0x2C010AA9ull;
+//DUPS: 2D010AA9,
+static const uint64_t P9N2_EX_7_IMA_TRACE = 0x2F010AA9ull;
+//DUPS: 2F010AA9,
+static const uint64_t P9N2_EX_8_IMA_TRACE = 0x30010AA9ull;
+//DUPS: 31010AA9,
+static const uint64_t P9N2_EX_9_IMA_TRACE = 0x32010AA9ull;
+//DUPS: 33010AA9,
+static const uint64_t P9N2_EX_10_IMA_TRACE = 0x34010AA9ull;
+//DUPS: 35010AA9,
+static const uint64_t P9N2_EX_11_IMA_TRACE = 0x36010AA9ull;
+//DUPS: 37010AA9,
+
+static const uint64_t P9N2_C_INJECT_REG = 0x20050011ull;
+
+static const uint64_t P9N2_C_0_INJECT_REG = 0x20050011ull;
+
+static const uint64_t P9N2_C_1_INJECT_REG = 0x21050011ull;
+
+static const uint64_t P9N2_C_2_INJECT_REG = 0x22050011ull;
+
+static const uint64_t P9N2_C_3_INJECT_REG = 0x23050011ull;
+
+static const uint64_t P9N2_C_4_INJECT_REG = 0x24050011ull;
+
+static const uint64_t P9N2_C_5_INJECT_REG = 0x25050011ull;
+
+static const uint64_t P9N2_C_6_INJECT_REG = 0x26050011ull;
+
+static const uint64_t P9N2_C_7_INJECT_REG = 0x27050011ull;
+
+static const uint64_t P9N2_C_8_INJECT_REG = 0x28050011ull;
+
+static const uint64_t P9N2_C_9_INJECT_REG = 0x29050011ull;
+
+static const uint64_t P9N2_C_10_INJECT_REG = 0x2A050011ull;
+
+static const uint64_t P9N2_C_11_INJECT_REG = 0x2B050011ull;
+
+static const uint64_t P9N2_C_12_INJECT_REG = 0x2C050011ull;
+
+static const uint64_t P9N2_C_13_INJECT_REG = 0x2D050011ull;
+
+static const uint64_t P9N2_C_14_INJECT_REG = 0x2E050011ull;
+
+static const uint64_t P9N2_C_15_INJECT_REG = 0x2F050011ull;
+
+static const uint64_t P9N2_C_16_INJECT_REG = 0x30050011ull;
+
+static const uint64_t P9N2_C_17_INJECT_REG = 0x31050011ull;
+
+static const uint64_t P9N2_C_18_INJECT_REG = 0x32050011ull;
+
+static const uint64_t P9N2_C_19_INJECT_REG = 0x33050011ull;
+
+static const uint64_t P9N2_C_20_INJECT_REG = 0x34050011ull;
+
+static const uint64_t P9N2_C_21_INJECT_REG = 0x35050011ull;
+
+static const uint64_t P9N2_C_22_INJECT_REG = 0x36050011ull;
+
+static const uint64_t P9N2_C_23_INJECT_REG = 0x37050011ull;
+
+static const uint64_t P9N2_EQ_INJECT_REG = 0x10050011ull;
+
+static const uint64_t P9N2_EQ_0_INJECT_REG = 0x10050011ull;
+
+static const uint64_t P9N2_EQ_1_INJECT_REG = 0x11050011ull;
+
+static const uint64_t P9N2_EQ_2_INJECT_REG = 0x12050011ull;
+
+static const uint64_t P9N2_EQ_3_INJECT_REG = 0x13050011ull;
+
+static const uint64_t P9N2_EQ_4_INJECT_REG = 0x14050011ull;
+
+static const uint64_t P9N2_EQ_5_INJECT_REG = 0x15050011ull;
+
+static const uint64_t P9N2_EX_INJECT_REG = 0x20050011ull;
+//DUPS: 21050011,
+static const uint64_t P9N2_EX_0_INJECT_REG = 0x20050011ull;
+//DUPS: 21050011,
+static const uint64_t P9N2_EX_1_INJECT_REG = 0x22050011ull;
+//DUPS: 23050011,
+static const uint64_t P9N2_EX_2_INJECT_REG = 0x24050011ull;
+//DUPS: 25050011,
+static const uint64_t P9N2_EX_3_INJECT_REG = 0x26050011ull;
+//DUPS: 27050011,
+static const uint64_t P9N2_EX_4_INJECT_REG = 0x28050011ull;
+//DUPS: 29050011,
+static const uint64_t P9N2_EX_5_INJECT_REG = 0x2A050011ull;
+//DUPS: 2B050011,
+static const uint64_t P9N2_EX_6_INJECT_REG = 0x2C050011ull;
+//DUPS: 2D050011,
+static const uint64_t P9N2_EX_7_INJECT_REG = 0x2F050011ull;
+//DUPS: 2F050011,
+static const uint64_t P9N2_EX_8_INJECT_REG = 0x30050011ull;
+//DUPS: 31050011,
+static const uint64_t P9N2_EX_9_INJECT_REG = 0x32050011ull;
+//DUPS: 33050011,
+static const uint64_t P9N2_EX_10_INJECT_REG = 0x34050011ull;
+//DUPS: 35050011,
+static const uint64_t P9N2_EX_11_INJECT_REG = 0x36050011ull;
+//DUPS: 37050011,
+
+static const uint64_t P9N2_EQ_INJ_REG = 0x1001100Dull;
+//DUPS: 1001140D,
+static const uint64_t P9N2_EQ_0_INJ_REG = 0x1001100Dull;
+//DUPS: 1001140D,
+static const uint64_t P9N2_EQ_1_INJ_REG = 0x1101100Dull;
+//DUPS: 1101140D,
+static const uint64_t P9N2_EQ_2_INJ_REG = 0x1201100Dull;
+//DUPS: 1201140D,
+static const uint64_t P9N2_EQ_3_INJ_REG = 0x1301100Dull;
+//DUPS: 1301140D,
+static const uint64_t P9N2_EQ_4_INJ_REG = 0x1401100Dull;
+//DUPS: 1401140D,
+static const uint64_t P9N2_EQ_5_INJ_REG = 0x1501100Dull;
+//DUPS: 1501140D,
+static const uint64_t P9N2_EX_INJ_REG = 0x1001100Dull;
+
+static const uint64_t P9N2_EX_0_INJ_REG = 0x1001100Dull;
+
+static const uint64_t P9N2_EX_1_INJ_REG = 0x1001140Dull;
+
+static const uint64_t P9N2_EX_2_INJ_REG = 0x1101100Dull;
+
+static const uint64_t P9N2_EX_3_INJ_REG = 0x1101140Dull;
+
+static const uint64_t P9N2_EX_4_INJ_REG = 0x1201100Dull;
+
+static const uint64_t P9N2_EX_5_INJ_REG = 0x1201140Dull;
+
+static const uint64_t P9N2_EX_6_INJ_REG = 0x1301100Dull;
+
+static const uint64_t P9N2_EX_7_INJ_REG = 0x1301140Dull;
+
+static const uint64_t P9N2_EX_8_INJ_REG = 0x1401100Dull;
+
+static const uint64_t P9N2_EX_9_INJ_REG = 0x1401140Dull;
+
+static const uint64_t P9N2_EX_10_INJ_REG = 0x1501100Dull;
+
+static const uint64_t P9N2_EX_11_INJ_REG = 0x1501140Dull;
+
+
+static const uint64_t P9N2_C_INV_ERATE = 0x20010AB4ull;
+
+static const uint64_t P9N2_C_0_INV_ERATE = 0x20010AB4ull;
+
+static const uint64_t P9N2_C_1_INV_ERATE = 0x21010AB4ull;
+
+static const uint64_t P9N2_C_2_INV_ERATE = 0x22010AB4ull;
+
+static const uint64_t P9N2_C_3_INV_ERATE = 0x23010AB4ull;
+
+static const uint64_t P9N2_C_4_INV_ERATE = 0x24010AB4ull;
+
+static const uint64_t P9N2_C_5_INV_ERATE = 0x25010AB4ull;
+
+static const uint64_t P9N2_C_6_INV_ERATE = 0x26010AB4ull;
+
+static const uint64_t P9N2_C_7_INV_ERATE = 0x27010AB4ull;
+
+static const uint64_t P9N2_C_8_INV_ERATE = 0x28010AB4ull;
+
+static const uint64_t P9N2_C_9_INV_ERATE = 0x29010AB4ull;
+
+static const uint64_t P9N2_C_10_INV_ERATE = 0x2A010AB4ull;
+
+static const uint64_t P9N2_C_11_INV_ERATE = 0x2B010AB4ull;
+
+static const uint64_t P9N2_C_12_INV_ERATE = 0x2C010AB4ull;
+
+static const uint64_t P9N2_C_13_INV_ERATE = 0x2D010AB4ull;
+
+static const uint64_t P9N2_C_14_INV_ERATE = 0x2E010AB4ull;
+
+static const uint64_t P9N2_C_15_INV_ERATE = 0x2F010AB4ull;
+
+static const uint64_t P9N2_C_16_INV_ERATE = 0x30010AB4ull;
+
+static const uint64_t P9N2_C_17_INV_ERATE = 0x31010AB4ull;
+
+static const uint64_t P9N2_C_18_INV_ERATE = 0x32010AB4ull;
+
+static const uint64_t P9N2_C_19_INV_ERATE = 0x33010AB4ull;
+
+static const uint64_t P9N2_C_20_INV_ERATE = 0x34010AB4ull;
+
+static const uint64_t P9N2_C_21_INV_ERATE = 0x35010AB4ull;
+
+static const uint64_t P9N2_C_22_INV_ERATE = 0x36010AB4ull;
+
+static const uint64_t P9N2_C_23_INV_ERATE = 0x37010AB4ull;
+
+static const uint64_t P9N2_EX_0_L2_INV_ERATE = 0x20010AB4ull;
+//DUPS: 21010AB4,
+static const uint64_t P9N2_EX_10_L2_INV_ERATE = 0x34010AB4ull;
+//DUPS: 35010AB4,
+static const uint64_t P9N2_EX_11_L2_INV_ERATE = 0x36010AB4ull;
+//DUPS: 37010AB4,
+static const uint64_t P9N2_EX_1_L2_INV_ERATE = 0x22010AB4ull;
+//DUPS: 23010AB4,
+static const uint64_t P9N2_EX_2_L2_INV_ERATE = 0x24010AB4ull;
+//DUPS: 25010AB4,
+static const uint64_t P9N2_EX_3_L2_INV_ERATE = 0x26010AB4ull;
+//DUPS: 27010AB4,
+static const uint64_t P9N2_EX_4_L2_INV_ERATE = 0x28010AB4ull;
+//DUPS: 29010AB4,
+static const uint64_t P9N2_EX_5_L2_INV_ERATE = 0x2A010AB4ull;
+//DUPS: 2B010AB4,
+static const uint64_t P9N2_EX_6_L2_INV_ERATE = 0x2C010AB4ull;
+//DUPS: 2D010AB4,
+static const uint64_t P9N2_EX_7_L2_INV_ERATE = 0x2F010AB4ull;
+//DUPS: 2F010AB4,
+static const uint64_t P9N2_EX_8_L2_INV_ERATE = 0x30010AB4ull;
+//DUPS: 31010AB4,
+static const uint64_t P9N2_EX_9_L2_INV_ERATE = 0x32010AB4ull;
+//DUPS: 33010AB4,
+static const uint64_t P9N2_EX_L2_INV_ERATE = 0x20010AB4ull;
+//DUPS: 21010AB4,
+
+static const uint64_t P9N2_C_ISU_DEBUG_CTRL = 0x20010C46ull;
+
+static const uint64_t P9N2_C_0_ISU_DEBUG_CTRL = 0x20010C46ull;
+
+static const uint64_t P9N2_C_1_ISU_DEBUG_CTRL = 0x21010C46ull;
+
+static const uint64_t P9N2_C_2_ISU_DEBUG_CTRL = 0x22010C46ull;
+
+static const uint64_t P9N2_C_3_ISU_DEBUG_CTRL = 0x23010C46ull;
+
+static const uint64_t P9N2_C_4_ISU_DEBUG_CTRL = 0x24010C46ull;
+
+static const uint64_t P9N2_C_5_ISU_DEBUG_CTRL = 0x25010C46ull;
+
+static const uint64_t P9N2_C_6_ISU_DEBUG_CTRL = 0x26010C46ull;
+
+static const uint64_t P9N2_C_7_ISU_DEBUG_CTRL = 0x27010C46ull;
+
+static const uint64_t P9N2_C_8_ISU_DEBUG_CTRL = 0x28010C46ull;
+
+static const uint64_t P9N2_C_9_ISU_DEBUG_CTRL = 0x29010C46ull;
+
+static const uint64_t P9N2_C_10_ISU_DEBUG_CTRL = 0x2A010C46ull;
+
+static const uint64_t P9N2_C_11_ISU_DEBUG_CTRL = 0x2B010C46ull;
+
+static const uint64_t P9N2_C_12_ISU_DEBUG_CTRL = 0x2C010C46ull;
+
+static const uint64_t P9N2_C_13_ISU_DEBUG_CTRL = 0x2D010C46ull;
+
+static const uint64_t P9N2_C_14_ISU_DEBUG_CTRL = 0x2E010C46ull;
+
+static const uint64_t P9N2_C_15_ISU_DEBUG_CTRL = 0x2F010C46ull;
+
+static const uint64_t P9N2_C_16_ISU_DEBUG_CTRL = 0x30010C46ull;
+
+static const uint64_t P9N2_C_17_ISU_DEBUG_CTRL = 0x31010C46ull;
+
+static const uint64_t P9N2_C_18_ISU_DEBUG_CTRL = 0x32010C46ull;
+
+static const uint64_t P9N2_C_19_ISU_DEBUG_CTRL = 0x33010C46ull;
+
+static const uint64_t P9N2_C_20_ISU_DEBUG_CTRL = 0x34010C46ull;
+
+static const uint64_t P9N2_C_21_ISU_DEBUG_CTRL = 0x35010C46ull;
+
+static const uint64_t P9N2_C_22_ISU_DEBUG_CTRL = 0x36010C46ull;
+
+static const uint64_t P9N2_C_23_ISU_DEBUG_CTRL = 0x37010C46ull;
+
+static const uint64_t P9N2_EX_0_L2_ISU_DEBUG_CTRL = 0x20010C46ull;
+//DUPS: 21010C46,
+static const uint64_t P9N2_EX_10_L2_ISU_DEBUG_CTRL = 0x34010C46ull;
+//DUPS: 35010C46,
+static const uint64_t P9N2_EX_11_L2_ISU_DEBUG_CTRL = 0x36010C46ull;
+//DUPS: 37010C46,
+static const uint64_t P9N2_EX_1_L2_ISU_DEBUG_CTRL = 0x22010C46ull;
+//DUPS: 23010C46,
+static const uint64_t P9N2_EX_2_L2_ISU_DEBUG_CTRL = 0x24010C46ull;
+//DUPS: 25010C46,
+static const uint64_t P9N2_EX_3_L2_ISU_DEBUG_CTRL = 0x26010C46ull;
+//DUPS: 27010C46,
+static const uint64_t P9N2_EX_4_L2_ISU_DEBUG_CTRL = 0x28010C46ull;
+//DUPS: 29010C46,
+static const uint64_t P9N2_EX_5_L2_ISU_DEBUG_CTRL = 0x2A010C46ull;
+//DUPS: 2B010C46,
+static const uint64_t P9N2_EX_6_L2_ISU_DEBUG_CTRL = 0x2C010C46ull;
+//DUPS: 2D010C46,
+static const uint64_t P9N2_EX_7_L2_ISU_DEBUG_CTRL = 0x2F010C46ull;
+//DUPS: 2F010C46,
+static const uint64_t P9N2_EX_8_L2_ISU_DEBUG_CTRL = 0x30010C46ull;
+//DUPS: 31010C46,
+static const uint64_t P9N2_EX_9_L2_ISU_DEBUG_CTRL = 0x32010C46ull;
+//DUPS: 33010C46,
+static const uint64_t P9N2_EX_L2_ISU_DEBUG_CTRL = 0x20010C46ull;
+//DUPS: 21010C46,
+
+static const uint64_t P9N2_C_ISU_REG0_HOLD_OUT = 0x20010C40ull;
+
+static const uint64_t P9N2_C_0_ISU_REG0_HOLD_OUT = 0x20010C40ull;
+
+static const uint64_t P9N2_C_1_ISU_REG0_HOLD_OUT = 0x21010C40ull;
+
+static const uint64_t P9N2_C_2_ISU_REG0_HOLD_OUT = 0x22010C40ull;
+
+static const uint64_t P9N2_C_3_ISU_REG0_HOLD_OUT = 0x23010C40ull;
+
+static const uint64_t P9N2_C_4_ISU_REG0_HOLD_OUT = 0x24010C40ull;
+
+static const uint64_t P9N2_C_5_ISU_REG0_HOLD_OUT = 0x25010C40ull;
+
+static const uint64_t P9N2_C_6_ISU_REG0_HOLD_OUT = 0x26010C40ull;
+
+static const uint64_t P9N2_C_7_ISU_REG0_HOLD_OUT = 0x27010C40ull;
+
+static const uint64_t P9N2_C_8_ISU_REG0_HOLD_OUT = 0x28010C40ull;
+
+static const uint64_t P9N2_C_9_ISU_REG0_HOLD_OUT = 0x29010C40ull;
+
+static const uint64_t P9N2_C_10_ISU_REG0_HOLD_OUT = 0x2A010C40ull;
+
+static const uint64_t P9N2_C_11_ISU_REG0_HOLD_OUT = 0x2B010C40ull;
+
+static const uint64_t P9N2_C_12_ISU_REG0_HOLD_OUT = 0x2C010C40ull;
+
+static const uint64_t P9N2_C_13_ISU_REG0_HOLD_OUT = 0x2D010C40ull;
+
+static const uint64_t P9N2_C_14_ISU_REG0_HOLD_OUT = 0x2E010C40ull;
+
+static const uint64_t P9N2_C_15_ISU_REG0_HOLD_OUT = 0x2F010C40ull;
+
+static const uint64_t P9N2_C_16_ISU_REG0_HOLD_OUT = 0x30010C40ull;
+
+static const uint64_t P9N2_C_17_ISU_REG0_HOLD_OUT = 0x31010C40ull;
+
+static const uint64_t P9N2_C_18_ISU_REG0_HOLD_OUT = 0x32010C40ull;
+
+static const uint64_t P9N2_C_19_ISU_REG0_HOLD_OUT = 0x33010C40ull;
+
+static const uint64_t P9N2_C_20_ISU_REG0_HOLD_OUT = 0x34010C40ull;
+
+static const uint64_t P9N2_C_21_ISU_REG0_HOLD_OUT = 0x35010C40ull;
+
+static const uint64_t P9N2_C_22_ISU_REG0_HOLD_OUT = 0x36010C40ull;
+
+static const uint64_t P9N2_C_23_ISU_REG0_HOLD_OUT = 0x37010C40ull;
+
+static const uint64_t P9N2_EX_0_L2_ISU_REG0_HOLD_OUT = 0x20010C40ull;
+//DUPS: 21010C40,
+static const uint64_t P9N2_EX_10_L2_ISU_REG0_HOLD_OUT = 0x34010C40ull;
+//DUPS: 35010C40,
+static const uint64_t P9N2_EX_11_L2_ISU_REG0_HOLD_OUT = 0x36010C40ull;
+//DUPS: 37010C40,
+static const uint64_t P9N2_EX_1_L2_ISU_REG0_HOLD_OUT = 0x22010C40ull;
+//DUPS: 23010C40,
+static const uint64_t P9N2_EX_2_L2_ISU_REG0_HOLD_OUT = 0x24010C40ull;
+//DUPS: 25010C40,
+static const uint64_t P9N2_EX_3_L2_ISU_REG0_HOLD_OUT = 0x26010C40ull;
+//DUPS: 27010C40,
+static const uint64_t P9N2_EX_4_L2_ISU_REG0_HOLD_OUT = 0x28010C40ull;
+//DUPS: 29010C40,
+static const uint64_t P9N2_EX_5_L2_ISU_REG0_HOLD_OUT = 0x2A010C40ull;
+//DUPS: 2B010C40,
+static const uint64_t P9N2_EX_6_L2_ISU_REG0_HOLD_OUT = 0x2C010C40ull;
+//DUPS: 2D010C40,
+static const uint64_t P9N2_EX_7_L2_ISU_REG0_HOLD_OUT = 0x2F010C40ull;
+//DUPS: 2F010C40,
+static const uint64_t P9N2_EX_8_L2_ISU_REG0_HOLD_OUT = 0x30010C40ull;
+//DUPS: 31010C40,
+static const uint64_t P9N2_EX_9_L2_ISU_REG0_HOLD_OUT = 0x32010C40ull;
+//DUPS: 33010C40,
+static const uint64_t P9N2_EX_L2_ISU_REG0_HOLD_OUT = 0x20010C40ull;
+//DUPS: 21010C40,
+
+static const uint64_t P9N2_C_ISU_REG1_HOLD_OUT = 0x20010C41ull;
+
+static const uint64_t P9N2_C_0_ISU_REG1_HOLD_OUT = 0x20010C41ull;
+
+static const uint64_t P9N2_C_1_ISU_REG1_HOLD_OUT = 0x21010C41ull;
+
+static const uint64_t P9N2_C_2_ISU_REG1_HOLD_OUT = 0x22010C41ull;
+
+static const uint64_t P9N2_C_3_ISU_REG1_HOLD_OUT = 0x23010C41ull;
+
+static const uint64_t P9N2_C_4_ISU_REG1_HOLD_OUT = 0x24010C41ull;
+
+static const uint64_t P9N2_C_5_ISU_REG1_HOLD_OUT = 0x25010C41ull;
+
+static const uint64_t P9N2_C_6_ISU_REG1_HOLD_OUT = 0x26010C41ull;
+
+static const uint64_t P9N2_C_7_ISU_REG1_HOLD_OUT = 0x27010C41ull;
+
+static const uint64_t P9N2_C_8_ISU_REG1_HOLD_OUT = 0x28010C41ull;
+
+static const uint64_t P9N2_C_9_ISU_REG1_HOLD_OUT = 0x29010C41ull;
+
+static const uint64_t P9N2_C_10_ISU_REG1_HOLD_OUT = 0x2A010C41ull;
+
+static const uint64_t P9N2_C_11_ISU_REG1_HOLD_OUT = 0x2B010C41ull;
+
+static const uint64_t P9N2_C_12_ISU_REG1_HOLD_OUT = 0x2C010C41ull;
+
+static const uint64_t P9N2_C_13_ISU_REG1_HOLD_OUT = 0x2D010C41ull;
+
+static const uint64_t P9N2_C_14_ISU_REG1_HOLD_OUT = 0x2E010C41ull;
+
+static const uint64_t P9N2_C_15_ISU_REG1_HOLD_OUT = 0x2F010C41ull;
+
+static const uint64_t P9N2_C_16_ISU_REG1_HOLD_OUT = 0x30010C41ull;
+
+static const uint64_t P9N2_C_17_ISU_REG1_HOLD_OUT = 0x31010C41ull;
+
+static const uint64_t P9N2_C_18_ISU_REG1_HOLD_OUT = 0x32010C41ull;
+
+static const uint64_t P9N2_C_19_ISU_REG1_HOLD_OUT = 0x33010C41ull;
+
+static const uint64_t P9N2_C_20_ISU_REG1_HOLD_OUT = 0x34010C41ull;
+
+static const uint64_t P9N2_C_21_ISU_REG1_HOLD_OUT = 0x35010C41ull;
+
+static const uint64_t P9N2_C_22_ISU_REG1_HOLD_OUT = 0x36010C41ull;
+
+static const uint64_t P9N2_C_23_ISU_REG1_HOLD_OUT = 0x37010C41ull;
+
+static const uint64_t P9N2_EX_0_L2_ISU_REG1_HOLD_OUT = 0x20010C41ull;
+//DUPS: 21010C41,
+static const uint64_t P9N2_EX_10_L2_ISU_REG1_HOLD_OUT = 0x34010C41ull;
+//DUPS: 35010C41,
+static const uint64_t P9N2_EX_11_L2_ISU_REG1_HOLD_OUT = 0x36010C41ull;
+//DUPS: 37010C41,
+static const uint64_t P9N2_EX_1_L2_ISU_REG1_HOLD_OUT = 0x22010C41ull;
+//DUPS: 23010C41,
+static const uint64_t P9N2_EX_2_L2_ISU_REG1_HOLD_OUT = 0x24010C41ull;
+//DUPS: 25010C41,
+static const uint64_t P9N2_EX_3_L2_ISU_REG1_HOLD_OUT = 0x26010C41ull;
+//DUPS: 27010C41,
+static const uint64_t P9N2_EX_4_L2_ISU_REG1_HOLD_OUT = 0x28010C41ull;
+//DUPS: 29010C41,
+static const uint64_t P9N2_EX_5_L2_ISU_REG1_HOLD_OUT = 0x2A010C41ull;
+//DUPS: 2B010C41,
+static const uint64_t P9N2_EX_6_L2_ISU_REG1_HOLD_OUT = 0x2C010C41ull;
+//DUPS: 2D010C41,
+static const uint64_t P9N2_EX_7_L2_ISU_REG1_HOLD_OUT = 0x2F010C41ull;
+//DUPS: 2F010C41,
+static const uint64_t P9N2_EX_8_L2_ISU_REG1_HOLD_OUT = 0x30010C41ull;
+//DUPS: 31010C41,
+static const uint64_t P9N2_EX_9_L2_ISU_REG1_HOLD_OUT = 0x32010C41ull;
+//DUPS: 33010C41,
+static const uint64_t P9N2_EX_L2_ISU_REG1_HOLD_OUT = 0x20010C41ull;
+//DUPS: 21010C41,
+
+static const uint64_t P9N2_C_ISU_REG2_HOLD_OUT = 0x20010C42ull;
+
+static const uint64_t P9N2_C_0_ISU_REG2_HOLD_OUT = 0x20010C42ull;
+
+static const uint64_t P9N2_C_1_ISU_REG2_HOLD_OUT = 0x21010C42ull;
+
+static const uint64_t P9N2_C_2_ISU_REG2_HOLD_OUT = 0x22010C42ull;
+
+static const uint64_t P9N2_C_3_ISU_REG2_HOLD_OUT = 0x23010C42ull;
+
+static const uint64_t P9N2_C_4_ISU_REG2_HOLD_OUT = 0x24010C42ull;
+
+static const uint64_t P9N2_C_5_ISU_REG2_HOLD_OUT = 0x25010C42ull;
+
+static const uint64_t P9N2_C_6_ISU_REG2_HOLD_OUT = 0x26010C42ull;
+
+static const uint64_t P9N2_C_7_ISU_REG2_HOLD_OUT = 0x27010C42ull;
+
+static const uint64_t P9N2_C_8_ISU_REG2_HOLD_OUT = 0x28010C42ull;
+
+static const uint64_t P9N2_C_9_ISU_REG2_HOLD_OUT = 0x29010C42ull;
+
+static const uint64_t P9N2_C_10_ISU_REG2_HOLD_OUT = 0x2A010C42ull;
+
+static const uint64_t P9N2_C_11_ISU_REG2_HOLD_OUT = 0x2B010C42ull;
+
+static const uint64_t P9N2_C_12_ISU_REG2_HOLD_OUT = 0x2C010C42ull;
+
+static const uint64_t P9N2_C_13_ISU_REG2_HOLD_OUT = 0x2D010C42ull;
+
+static const uint64_t P9N2_C_14_ISU_REG2_HOLD_OUT = 0x2E010C42ull;
+
+static const uint64_t P9N2_C_15_ISU_REG2_HOLD_OUT = 0x2F010C42ull;
+
+static const uint64_t P9N2_C_16_ISU_REG2_HOLD_OUT = 0x30010C42ull;
+
+static const uint64_t P9N2_C_17_ISU_REG2_HOLD_OUT = 0x31010C42ull;
+
+static const uint64_t P9N2_C_18_ISU_REG2_HOLD_OUT = 0x32010C42ull;
+
+static const uint64_t P9N2_C_19_ISU_REG2_HOLD_OUT = 0x33010C42ull;
+
+static const uint64_t P9N2_C_20_ISU_REG2_HOLD_OUT = 0x34010C42ull;
+
+static const uint64_t P9N2_C_21_ISU_REG2_HOLD_OUT = 0x35010C42ull;
+
+static const uint64_t P9N2_C_22_ISU_REG2_HOLD_OUT = 0x36010C42ull;
+
+static const uint64_t P9N2_C_23_ISU_REG2_HOLD_OUT = 0x37010C42ull;
+
+static const uint64_t P9N2_EX_0_L2_ISU_REG2_HOLD_OUT = 0x20010C42ull;
+//DUPS: 21010C42,
+static const uint64_t P9N2_EX_10_L2_ISU_REG2_HOLD_OUT = 0x34010C42ull;
+//DUPS: 35010C42,
+static const uint64_t P9N2_EX_11_L2_ISU_REG2_HOLD_OUT = 0x36010C42ull;
+//DUPS: 37010C42,
+static const uint64_t P9N2_EX_1_L2_ISU_REG2_HOLD_OUT = 0x22010C42ull;
+//DUPS: 23010C42,
+static const uint64_t P9N2_EX_2_L2_ISU_REG2_HOLD_OUT = 0x24010C42ull;
+//DUPS: 25010C42,
+static const uint64_t P9N2_EX_3_L2_ISU_REG2_HOLD_OUT = 0x26010C42ull;
+//DUPS: 27010C42,
+static const uint64_t P9N2_EX_4_L2_ISU_REG2_HOLD_OUT = 0x28010C42ull;
+//DUPS: 29010C42,
+static const uint64_t P9N2_EX_5_L2_ISU_REG2_HOLD_OUT = 0x2A010C42ull;
+//DUPS: 2B010C42,
+static const uint64_t P9N2_EX_6_L2_ISU_REG2_HOLD_OUT = 0x2C010C42ull;
+//DUPS: 2D010C42,
+static const uint64_t P9N2_EX_7_L2_ISU_REG2_HOLD_OUT = 0x2F010C42ull;
+//DUPS: 2F010C42,
+static const uint64_t P9N2_EX_8_L2_ISU_REG2_HOLD_OUT = 0x30010C42ull;
+//DUPS: 31010C42,
+static const uint64_t P9N2_EX_9_L2_ISU_REG2_HOLD_OUT = 0x32010C42ull;
+//DUPS: 33010C42,
+static const uint64_t P9N2_EX_L2_ISU_REG2_HOLD_OUT = 0x20010C42ull;
+//DUPS: 21010C42,
+
+static const uint64_t P9N2_C_ISU_REG3_HOLD_OUT = 0x20010C43ull;
+
+static const uint64_t P9N2_C_0_ISU_REG3_HOLD_OUT = 0x20010C43ull;
+
+static const uint64_t P9N2_C_1_ISU_REG3_HOLD_OUT = 0x21010C43ull;
+
+static const uint64_t P9N2_C_2_ISU_REG3_HOLD_OUT = 0x22010C43ull;
+
+static const uint64_t P9N2_C_3_ISU_REG3_HOLD_OUT = 0x23010C43ull;
+
+static const uint64_t P9N2_C_4_ISU_REG3_HOLD_OUT = 0x24010C43ull;
+
+static const uint64_t P9N2_C_5_ISU_REG3_HOLD_OUT = 0x25010C43ull;
+
+static const uint64_t P9N2_C_6_ISU_REG3_HOLD_OUT = 0x26010C43ull;
+
+static const uint64_t P9N2_C_7_ISU_REG3_HOLD_OUT = 0x27010C43ull;
+
+static const uint64_t P9N2_C_8_ISU_REG3_HOLD_OUT = 0x28010C43ull;
+
+static const uint64_t P9N2_C_9_ISU_REG3_HOLD_OUT = 0x29010C43ull;
+
+static const uint64_t P9N2_C_10_ISU_REG3_HOLD_OUT = 0x2A010C43ull;
+
+static const uint64_t P9N2_C_11_ISU_REG3_HOLD_OUT = 0x2B010C43ull;
+
+static const uint64_t P9N2_C_12_ISU_REG3_HOLD_OUT = 0x2C010C43ull;
+
+static const uint64_t P9N2_C_13_ISU_REG3_HOLD_OUT = 0x2D010C43ull;
+
+static const uint64_t P9N2_C_14_ISU_REG3_HOLD_OUT = 0x2E010C43ull;
+
+static const uint64_t P9N2_C_15_ISU_REG3_HOLD_OUT = 0x2F010C43ull;
+
+static const uint64_t P9N2_C_16_ISU_REG3_HOLD_OUT = 0x30010C43ull;
+
+static const uint64_t P9N2_C_17_ISU_REG3_HOLD_OUT = 0x31010C43ull;
+
+static const uint64_t P9N2_C_18_ISU_REG3_HOLD_OUT = 0x32010C43ull;
+
+static const uint64_t P9N2_C_19_ISU_REG3_HOLD_OUT = 0x33010C43ull;
+
+static const uint64_t P9N2_C_20_ISU_REG3_HOLD_OUT = 0x34010C43ull;
+
+static const uint64_t P9N2_C_21_ISU_REG3_HOLD_OUT = 0x35010C43ull;
+
+static const uint64_t P9N2_C_22_ISU_REG3_HOLD_OUT = 0x36010C43ull;
+
+static const uint64_t P9N2_C_23_ISU_REG3_HOLD_OUT = 0x37010C43ull;
+
+static const uint64_t P9N2_EX_0_L2_ISU_REG3_HOLD_OUT = 0x20010C43ull;
+//DUPS: 21010C43,
+static const uint64_t P9N2_EX_10_L2_ISU_REG3_HOLD_OUT = 0x34010C43ull;
+//DUPS: 35010C43,
+static const uint64_t P9N2_EX_11_L2_ISU_REG3_HOLD_OUT = 0x36010C43ull;
+//DUPS: 37010C43,
+static const uint64_t P9N2_EX_1_L2_ISU_REG3_HOLD_OUT = 0x22010C43ull;
+//DUPS: 23010C43,
+static const uint64_t P9N2_EX_2_L2_ISU_REG3_HOLD_OUT = 0x24010C43ull;
+//DUPS: 25010C43,
+static const uint64_t P9N2_EX_3_L2_ISU_REG3_HOLD_OUT = 0x26010C43ull;
+//DUPS: 27010C43,
+static const uint64_t P9N2_EX_4_L2_ISU_REG3_HOLD_OUT = 0x28010C43ull;
+//DUPS: 29010C43,
+static const uint64_t P9N2_EX_5_L2_ISU_REG3_HOLD_OUT = 0x2A010C43ull;
+//DUPS: 2B010C43,
+static const uint64_t P9N2_EX_6_L2_ISU_REG3_HOLD_OUT = 0x2C010C43ull;
+//DUPS: 2D010C43,
+static const uint64_t P9N2_EX_7_L2_ISU_REG3_HOLD_OUT = 0x2F010C43ull;
+//DUPS: 2F010C43,
+static const uint64_t P9N2_EX_8_L2_ISU_REG3_HOLD_OUT = 0x30010C43ull;
+//DUPS: 31010C43,
+static const uint64_t P9N2_EX_9_L2_ISU_REG3_HOLD_OUT = 0x32010C43ull;
+//DUPS: 33010C43,
+static const uint64_t P9N2_EX_L2_ISU_REG3_HOLD_OUT = 0x20010C43ull;
+//DUPS: 21010C43,
+
+static const uint64_t P9N2_C_ISU_REG4_HOLD_OUT = 0x20010C44ull;
+
+static const uint64_t P9N2_C_0_ISU_REG4_HOLD_OUT = 0x20010C44ull;
+
+static const uint64_t P9N2_C_1_ISU_REG4_HOLD_OUT = 0x21010C44ull;
+
+static const uint64_t P9N2_C_2_ISU_REG4_HOLD_OUT = 0x22010C44ull;
+
+static const uint64_t P9N2_C_3_ISU_REG4_HOLD_OUT = 0x23010C44ull;
+
+static const uint64_t P9N2_C_4_ISU_REG4_HOLD_OUT = 0x24010C44ull;
+
+static const uint64_t P9N2_C_5_ISU_REG4_HOLD_OUT = 0x25010C44ull;
+
+static const uint64_t P9N2_C_6_ISU_REG4_HOLD_OUT = 0x26010C44ull;
+
+static const uint64_t P9N2_C_7_ISU_REG4_HOLD_OUT = 0x27010C44ull;
+
+static const uint64_t P9N2_C_8_ISU_REG4_HOLD_OUT = 0x28010C44ull;
+
+static const uint64_t P9N2_C_9_ISU_REG4_HOLD_OUT = 0x29010C44ull;
+
+static const uint64_t P9N2_C_10_ISU_REG4_HOLD_OUT = 0x2A010C44ull;
+
+static const uint64_t P9N2_C_11_ISU_REG4_HOLD_OUT = 0x2B010C44ull;
+
+static const uint64_t P9N2_C_12_ISU_REG4_HOLD_OUT = 0x2C010C44ull;
+
+static const uint64_t P9N2_C_13_ISU_REG4_HOLD_OUT = 0x2D010C44ull;
+
+static const uint64_t P9N2_C_14_ISU_REG4_HOLD_OUT = 0x2E010C44ull;
+
+static const uint64_t P9N2_C_15_ISU_REG4_HOLD_OUT = 0x2F010C44ull;
+
+static const uint64_t P9N2_C_16_ISU_REG4_HOLD_OUT = 0x30010C44ull;
+
+static const uint64_t P9N2_C_17_ISU_REG4_HOLD_OUT = 0x31010C44ull;
+
+static const uint64_t P9N2_C_18_ISU_REG4_HOLD_OUT = 0x32010C44ull;
+
+static const uint64_t P9N2_C_19_ISU_REG4_HOLD_OUT = 0x33010C44ull;
+
+static const uint64_t P9N2_C_20_ISU_REG4_HOLD_OUT = 0x34010C44ull;
+
+static const uint64_t P9N2_C_21_ISU_REG4_HOLD_OUT = 0x35010C44ull;
+
+static const uint64_t P9N2_C_22_ISU_REG4_HOLD_OUT = 0x36010C44ull;
+
+static const uint64_t P9N2_C_23_ISU_REG4_HOLD_OUT = 0x37010C44ull;
+
+static const uint64_t P9N2_EX_0_L2_ISU_REG4_HOLD_OUT = 0x20010C44ull;
+//DUPS: 21010C44,
+static const uint64_t P9N2_EX_10_L2_ISU_REG4_HOLD_OUT = 0x34010C44ull;
+//DUPS: 35010C44,
+static const uint64_t P9N2_EX_11_L2_ISU_REG4_HOLD_OUT = 0x36010C44ull;
+//DUPS: 37010C44,
+static const uint64_t P9N2_EX_1_L2_ISU_REG4_HOLD_OUT = 0x22010C44ull;
+//DUPS: 23010C44,
+static const uint64_t P9N2_EX_2_L2_ISU_REG4_HOLD_OUT = 0x24010C44ull;
+//DUPS: 25010C44,
+static const uint64_t P9N2_EX_3_L2_ISU_REG4_HOLD_OUT = 0x26010C44ull;
+//DUPS: 27010C44,
+static const uint64_t P9N2_EX_4_L2_ISU_REG4_HOLD_OUT = 0x28010C44ull;
+//DUPS: 29010C44,
+static const uint64_t P9N2_EX_5_L2_ISU_REG4_HOLD_OUT = 0x2A010C44ull;
+//DUPS: 2B010C44,
+static const uint64_t P9N2_EX_6_L2_ISU_REG4_HOLD_OUT = 0x2C010C44ull;
+//DUPS: 2D010C44,
+static const uint64_t P9N2_EX_7_L2_ISU_REG4_HOLD_OUT = 0x2F010C44ull;
+//DUPS: 2F010C44,
+static const uint64_t P9N2_EX_8_L2_ISU_REG4_HOLD_OUT = 0x30010C44ull;
+//DUPS: 31010C44,
+static const uint64_t P9N2_EX_9_L2_ISU_REG4_HOLD_OUT = 0x32010C44ull;
+//DUPS: 33010C44,
+static const uint64_t P9N2_EX_L2_ISU_REG4_HOLD_OUT = 0x20010C44ull;
+//DUPS: 21010C44,
+
+static const uint64_t P9N2_C_ISU_REG5_HOLD_OUT = 0x20010C45ull;
+
+static const uint64_t P9N2_C_0_ISU_REG5_HOLD_OUT = 0x20010C45ull;
+
+static const uint64_t P9N2_C_1_ISU_REG5_HOLD_OUT = 0x21010C45ull;
+
+static const uint64_t P9N2_C_2_ISU_REG5_HOLD_OUT = 0x22010C45ull;
+
+static const uint64_t P9N2_C_3_ISU_REG5_HOLD_OUT = 0x23010C45ull;
+
+static const uint64_t P9N2_C_4_ISU_REG5_HOLD_OUT = 0x24010C45ull;
+
+static const uint64_t P9N2_C_5_ISU_REG5_HOLD_OUT = 0x25010C45ull;
+
+static const uint64_t P9N2_C_6_ISU_REG5_HOLD_OUT = 0x26010C45ull;
+
+static const uint64_t P9N2_C_7_ISU_REG5_HOLD_OUT = 0x27010C45ull;
+
+static const uint64_t P9N2_C_8_ISU_REG5_HOLD_OUT = 0x28010C45ull;
+
+static const uint64_t P9N2_C_9_ISU_REG5_HOLD_OUT = 0x29010C45ull;
+
+static const uint64_t P9N2_C_10_ISU_REG5_HOLD_OUT = 0x2A010C45ull;
+
+static const uint64_t P9N2_C_11_ISU_REG5_HOLD_OUT = 0x2B010C45ull;
+
+static const uint64_t P9N2_C_12_ISU_REG5_HOLD_OUT = 0x2C010C45ull;
+
+static const uint64_t P9N2_C_13_ISU_REG5_HOLD_OUT = 0x2D010C45ull;
+
+static const uint64_t P9N2_C_14_ISU_REG5_HOLD_OUT = 0x2E010C45ull;
+
+static const uint64_t P9N2_C_15_ISU_REG5_HOLD_OUT = 0x2F010C45ull;
+
+static const uint64_t P9N2_C_16_ISU_REG5_HOLD_OUT = 0x30010C45ull;
+
+static const uint64_t P9N2_C_17_ISU_REG5_HOLD_OUT = 0x31010C45ull;
+
+static const uint64_t P9N2_C_18_ISU_REG5_HOLD_OUT = 0x32010C45ull;
+
+static const uint64_t P9N2_C_19_ISU_REG5_HOLD_OUT = 0x33010C45ull;
+
+static const uint64_t P9N2_C_20_ISU_REG5_HOLD_OUT = 0x34010C45ull;
+
+static const uint64_t P9N2_C_21_ISU_REG5_HOLD_OUT = 0x35010C45ull;
+
+static const uint64_t P9N2_C_22_ISU_REG5_HOLD_OUT = 0x36010C45ull;
+
+static const uint64_t P9N2_C_23_ISU_REG5_HOLD_OUT = 0x37010C45ull;
+
+static const uint64_t P9N2_EX_0_L2_ISU_REG5_HOLD_OUT = 0x20010C45ull;
+//DUPS: 21010C45,
+static const uint64_t P9N2_EX_10_L2_ISU_REG5_HOLD_OUT = 0x34010C45ull;
+//DUPS: 35010C45,
+static const uint64_t P9N2_EX_11_L2_ISU_REG5_HOLD_OUT = 0x36010C45ull;
+//DUPS: 37010C45,
+static const uint64_t P9N2_EX_1_L2_ISU_REG5_HOLD_OUT = 0x22010C45ull;
+//DUPS: 23010C45,
+static const uint64_t P9N2_EX_2_L2_ISU_REG5_HOLD_OUT = 0x24010C45ull;
+//DUPS: 25010C45,
+static const uint64_t P9N2_EX_3_L2_ISU_REG5_HOLD_OUT = 0x26010C45ull;
+//DUPS: 27010C45,
+static const uint64_t P9N2_EX_4_L2_ISU_REG5_HOLD_OUT = 0x28010C45ull;
+//DUPS: 29010C45,
+static const uint64_t P9N2_EX_5_L2_ISU_REG5_HOLD_OUT = 0x2A010C45ull;
+//DUPS: 2B010C45,
+static const uint64_t P9N2_EX_6_L2_ISU_REG5_HOLD_OUT = 0x2C010C45ull;
+//DUPS: 2D010C45,
+static const uint64_t P9N2_EX_7_L2_ISU_REG5_HOLD_OUT = 0x2F010C45ull;
+//DUPS: 2F010C45,
+static const uint64_t P9N2_EX_8_L2_ISU_REG5_HOLD_OUT = 0x30010C45ull;
+//DUPS: 31010C45,
+static const uint64_t P9N2_EX_9_L2_ISU_REG5_HOLD_OUT = 0x32010C45ull;
+//DUPS: 33010C45,
+static const uint64_t P9N2_EX_L2_ISU_REG5_HOLD_OUT = 0x20010C45ull;
+//DUPS: 21010C45,
+
+static const uint64_t P9N2_EQ_L3_ERR_RPT0_REG = 0x10011C10ull;
+//DUPS: 10011C10,
+static const uint64_t P9N2_EQ_0_L3_ERR_RPT0_REG = 0x10011C10ull;
+//DUPS: 10011C10,
+static const uint64_t P9N2_EQ_1_L3_ERR_RPT0_REG = 0x11011C10ull;
+//DUPS: 11011C10,
+static const uint64_t P9N2_EQ_2_L3_ERR_RPT0_REG = 0x12011C10ull;
+//DUPS: 12011C10,
+static const uint64_t P9N2_EQ_3_L3_ERR_RPT0_REG = 0x13011C10ull;
+//DUPS: 13011C10,
+static const uint64_t P9N2_EQ_4_L3_ERR_RPT0_REG = 0x14011C10ull;
+//DUPS: 14011C10,
+static const uint64_t P9N2_EQ_5_L3_ERR_RPT0_REG = 0x15011C10ull;
+//DUPS: 15011C10,
+static const uint64_t P9N2_EX_0_L3_L3_ERR_RPT0_REG = 0x10011810ull;
+
+static const uint64_t P9N2_EX_10_L3_L3_ERR_RPT0_REG = 0x15011810ull;
+
+static const uint64_t P9N2_EX_11_L3_L3_ERR_RPT0_REG = 0x15011C10ull;
+
+static const uint64_t P9N2_EX_1_L3_L3_ERR_RPT0_REG = 0x10011C10ull;
+
+static const uint64_t P9N2_EX_2_L3_L3_ERR_RPT0_REG = 0x11011810ull;
+
+static const uint64_t P9N2_EX_3_L3_L3_ERR_RPT0_REG = 0x11011C10ull;
+
+static const uint64_t P9N2_EX_4_L3_L3_ERR_RPT0_REG = 0x12011810ull;
+
+static const uint64_t P9N2_EX_5_L3_L3_ERR_RPT0_REG = 0x12011C10ull;
+
+static const uint64_t P9N2_EX_6_L3_L3_ERR_RPT0_REG = 0x13011810ull;
+
+static const uint64_t P9N2_EX_7_L3_L3_ERR_RPT0_REG = 0x13011C10ull;
+
+static const uint64_t P9N2_EX_8_L3_L3_ERR_RPT0_REG = 0x14011810ull;
+
+static const uint64_t P9N2_EX_9_L3_L3_ERR_RPT0_REG = 0x14011C10ull;
+
+static const uint64_t P9N2_EX_L3_L3_ERR_RPT0_REG = 0x10011810ull;
+
+
+static const uint64_t P9N2_EQ_L3_ERR_RPT1_REG = 0x10011C17ull;
+//DUPS: 10011C17,
+static const uint64_t P9N2_EQ_0_L3_ERR_RPT1_REG = 0x10011C17ull;
+//DUPS: 10011C17,
+static const uint64_t P9N2_EQ_1_L3_ERR_RPT1_REG = 0x11011C17ull;
+//DUPS: 11011C17,
+static const uint64_t P9N2_EQ_2_L3_ERR_RPT1_REG = 0x12011C17ull;
+//DUPS: 12011C17,
+static const uint64_t P9N2_EQ_3_L3_ERR_RPT1_REG = 0x13011C17ull;
+//DUPS: 13011C17,
+static const uint64_t P9N2_EQ_4_L3_ERR_RPT1_REG = 0x14011C17ull;
+//DUPS: 14011C17,
+static const uint64_t P9N2_EQ_5_L3_ERR_RPT1_REG = 0x15011C17ull;
+//DUPS: 15011C17,
+static const uint64_t P9N2_EX_0_L3_L3_ERR_RPT1_REG = 0x10011817ull;
+
+static const uint64_t P9N2_EX_10_L3_L3_ERR_RPT1_REG = 0x15011817ull;
+
+static const uint64_t P9N2_EX_11_L3_L3_ERR_RPT1_REG = 0x15011C17ull;
+
+static const uint64_t P9N2_EX_1_L3_L3_ERR_RPT1_REG = 0x10011C17ull;
+
+static const uint64_t P9N2_EX_2_L3_L3_ERR_RPT1_REG = 0x11011817ull;
+
+static const uint64_t P9N2_EX_3_L3_L3_ERR_RPT1_REG = 0x11011C17ull;
+
+static const uint64_t P9N2_EX_4_L3_L3_ERR_RPT1_REG = 0x12011817ull;
+
+static const uint64_t P9N2_EX_5_L3_L3_ERR_RPT1_REG = 0x12011C17ull;
+
+static const uint64_t P9N2_EX_6_L3_L3_ERR_RPT1_REG = 0x13011817ull;
+
+static const uint64_t P9N2_EX_7_L3_L3_ERR_RPT1_REG = 0x13011C17ull;
+
+static const uint64_t P9N2_EX_8_L3_L3_ERR_RPT1_REG = 0x14011817ull;
+
+static const uint64_t P9N2_EX_9_L3_L3_ERR_RPT1_REG = 0x14011C17ull;
+
+static const uint64_t P9N2_EX_L3_L3_ERR_RPT1_REG = 0x10011817ull;
+
+
+static const uint64_t P9N2_EQ_L3_RD_EPSILON_CFG_REG = 0x10011C29ull;
+//DUPS: 10011C29,
+static const uint64_t P9N2_EQ_0_L3_RD_EPSILON_CFG_REG = 0x10011C29ull;
+//DUPS: 10011C29,
+static const uint64_t P9N2_EQ_1_L3_RD_EPSILON_CFG_REG = 0x11011C29ull;
+//DUPS: 11011C29,
+static const uint64_t P9N2_EQ_2_L3_RD_EPSILON_CFG_REG = 0x12011C29ull;
+//DUPS: 12011C29,
+static const uint64_t P9N2_EQ_3_L3_RD_EPSILON_CFG_REG = 0x13011C29ull;
+//DUPS: 13011C29,
+static const uint64_t P9N2_EQ_4_L3_RD_EPSILON_CFG_REG = 0x14011C29ull;
+//DUPS: 14011C29,
+static const uint64_t P9N2_EQ_5_L3_RD_EPSILON_CFG_REG = 0x15011C29ull;
+//DUPS: 15011C29,
+static const uint64_t P9N2_EX_L3_RD_EPSILON_CFG_REG = 0x10011829ull;
+
+static const uint64_t P9N2_EX_0_L3_RD_EPSILON_CFG_REG = 0x10011829ull;
+
+static const uint64_t P9N2_EX_1_L3_RD_EPSILON_CFG_REG = 0x10011C29ull;
+
+static const uint64_t P9N2_EX_2_L3_RD_EPSILON_CFG_REG = 0x11011829ull;
+
+static const uint64_t P9N2_EX_3_L3_RD_EPSILON_CFG_REG = 0x11011C29ull;
+
+static const uint64_t P9N2_EX_4_L3_RD_EPSILON_CFG_REG = 0x12011829ull;
+
+static const uint64_t P9N2_EX_5_L3_RD_EPSILON_CFG_REG = 0x12011C29ull;
+
+static const uint64_t P9N2_EX_6_L3_RD_EPSILON_CFG_REG = 0x13011829ull;
+
+static const uint64_t P9N2_EX_7_L3_RD_EPSILON_CFG_REG = 0x13011C29ull;
+
+static const uint64_t P9N2_EX_8_L3_RD_EPSILON_CFG_REG = 0x14011829ull;
+
+static const uint64_t P9N2_EX_9_L3_RD_EPSILON_CFG_REG = 0x14011C29ull;
+
+static const uint64_t P9N2_EX_10_L3_RD_EPSILON_CFG_REG = 0x15011829ull;
+
+static const uint64_t P9N2_EX_11_L3_RD_EPSILON_CFG_REG = 0x15011C29ull;
+
+
+static const uint64_t P9N2_EQ_L3_RTIM_PERIOD_MONITOR = 0x10011C12ull;
+//DUPS: 10011C12,
+static const uint64_t P9N2_EQ_0_L3_RTIM_PERIOD_MONITOR = 0x10011C12ull;
+//DUPS: 10011C12,
+static const uint64_t P9N2_EQ_1_L3_RTIM_PERIOD_MONITOR = 0x11011C12ull;
+//DUPS: 11011C12,
+static const uint64_t P9N2_EQ_2_L3_RTIM_PERIOD_MONITOR = 0x12011C12ull;
+//DUPS: 12011C12,
+static const uint64_t P9N2_EQ_3_L3_RTIM_PERIOD_MONITOR = 0x13011C12ull;
+//DUPS: 13011C12,
+static const uint64_t P9N2_EQ_4_L3_RTIM_PERIOD_MONITOR = 0x14011C12ull;
+//DUPS: 14011C12,
+static const uint64_t P9N2_EQ_5_L3_RTIM_PERIOD_MONITOR = 0x15011C12ull;
+//DUPS: 15011C12,
+static const uint64_t P9N2_EX_0_L3_L3_RTIM_PERIOD_MONITOR = 0x10011812ull;
+
+static const uint64_t P9N2_EX_10_L3_L3_RTIM_PERIOD_MONITOR = 0x15011812ull;
+
+static const uint64_t P9N2_EX_11_L3_L3_RTIM_PERIOD_MONITOR = 0x15011C12ull;
+
+static const uint64_t P9N2_EX_1_L3_L3_RTIM_PERIOD_MONITOR = 0x10011C12ull;
+
+static const uint64_t P9N2_EX_2_L3_L3_RTIM_PERIOD_MONITOR = 0x11011812ull;
+
+static const uint64_t P9N2_EX_3_L3_L3_RTIM_PERIOD_MONITOR = 0x11011C12ull;
+
+static const uint64_t P9N2_EX_4_L3_L3_RTIM_PERIOD_MONITOR = 0x12011812ull;
+
+static const uint64_t P9N2_EX_5_L3_L3_RTIM_PERIOD_MONITOR = 0x12011C12ull;
+
+static const uint64_t P9N2_EX_6_L3_L3_RTIM_PERIOD_MONITOR = 0x13011812ull;
+
+static const uint64_t P9N2_EX_7_L3_L3_RTIM_PERIOD_MONITOR = 0x13011C12ull;
+
+static const uint64_t P9N2_EX_8_L3_L3_RTIM_PERIOD_MONITOR = 0x14011812ull;
+
+static const uint64_t P9N2_EX_9_L3_L3_RTIM_PERIOD_MONITOR = 0x14011C12ull;
+
+static const uint64_t P9N2_EX_L3_L3_RTIM_PERIOD_MONITOR = 0x10011812ull;
+
+
+static const uint64_t P9N2_EQ_L3_WR_EPSILON_CFG_REG = 0x10011C2Aull;
+//DUPS: 10011C2A,
+static const uint64_t P9N2_EQ_0_L3_WR_EPSILON_CFG_REG = 0x10011C2Aull;
+//DUPS: 10011C2A,
+static const uint64_t P9N2_EQ_1_L3_WR_EPSILON_CFG_REG = 0x11011C2Aull;
+//DUPS: 11011C2A,
+static const uint64_t P9N2_EQ_2_L3_WR_EPSILON_CFG_REG = 0x12011C2Aull;
+//DUPS: 12011C2A,
+static const uint64_t P9N2_EQ_3_L3_WR_EPSILON_CFG_REG = 0x13011C2Aull;
+//DUPS: 13011C2A,
+static const uint64_t P9N2_EQ_4_L3_WR_EPSILON_CFG_REG = 0x14011C2Aull;
+//DUPS: 14011C2A,
+static const uint64_t P9N2_EQ_5_L3_WR_EPSILON_CFG_REG = 0x15011C2Aull;
+//DUPS: 15011C2A,
+static const uint64_t P9N2_EX_0_L3_L3_WR_EPSILON_CFG_REG = 0x1001182Aull;
+
+static const uint64_t P9N2_EX_10_L3_L3_WR_EPSILON_CFG_REG = 0x1501182Aull;
+
+static const uint64_t P9N2_EX_11_L3_L3_WR_EPSILON_CFG_REG = 0x15011C2Aull;
+
+static const uint64_t P9N2_EX_1_L3_L3_WR_EPSILON_CFG_REG = 0x10011C2Aull;
+
+static const uint64_t P9N2_EX_2_L3_L3_WR_EPSILON_CFG_REG = 0x1101182Aull;
+
+static const uint64_t P9N2_EX_3_L3_L3_WR_EPSILON_CFG_REG = 0x11011C2Aull;
+
+static const uint64_t P9N2_EX_4_L3_L3_WR_EPSILON_CFG_REG = 0x1201182Aull;
+
+static const uint64_t P9N2_EX_5_L3_L3_WR_EPSILON_CFG_REG = 0x12011C2Aull;
+
+static const uint64_t P9N2_EX_6_L3_L3_WR_EPSILON_CFG_REG = 0x1301182Aull;
+
+static const uint64_t P9N2_EX_7_L3_L3_WR_EPSILON_CFG_REG = 0x13011C2Aull;
+
+static const uint64_t P9N2_EX_8_L3_L3_WR_EPSILON_CFG_REG = 0x1401182Aull;
+
+static const uint64_t P9N2_EX_9_L3_L3_WR_EPSILON_CFG_REG = 0x14011C2Aull;
+
+static const uint64_t P9N2_EX_L3_L3_WR_EPSILON_CFG_REG = 0x1001182Aull;
+
+
+static const uint64_t P9N2_EQ_LINEDEL_TRIG_REG = 0x10010C0Dull;
+//DUPS: 10010C0D,
+static const uint64_t P9N2_EQ_0_LINEDEL_TRIG_REG = 0x10010C0Dull;
+//DUPS: 10010C0D,
+static const uint64_t P9N2_EQ_1_LINEDEL_TRIG_REG = 0x11010C0Dull;
+//DUPS: 11010C0D,
+static const uint64_t P9N2_EQ_2_LINEDEL_TRIG_REG = 0x12010C0Dull;
+//DUPS: 12010C0D,
+static const uint64_t P9N2_EQ_3_LINEDEL_TRIG_REG = 0x13010C0Dull;
+//DUPS: 13010C0D,
+static const uint64_t P9N2_EQ_4_LINEDEL_TRIG_REG = 0x14010C0Dull;
+//DUPS: 14010C0D,
+static const uint64_t P9N2_EQ_5_LINEDEL_TRIG_REG = 0x15010C0Dull;
+//DUPS: 15010C0D,
+static const uint64_t P9N2_EX_0_L2_LINEDEL_TRIG_REG = 0x1001080Dull;
+
+static const uint64_t P9N2_EX_10_L2_LINEDEL_TRIG_REG = 0x1501080Dull;
+
+static const uint64_t P9N2_EX_11_L2_LINEDEL_TRIG_REG = 0x15010C0Dull;
+
+static const uint64_t P9N2_EX_1_L2_LINEDEL_TRIG_REG = 0x10010C0Dull;
+
+static const uint64_t P9N2_EX_2_L2_LINEDEL_TRIG_REG = 0x1101080Dull;
+
+static const uint64_t P9N2_EX_3_L2_LINEDEL_TRIG_REG = 0x11010C0Dull;
+
+static const uint64_t P9N2_EX_4_L2_LINEDEL_TRIG_REG = 0x1201080Dull;
+
+static const uint64_t P9N2_EX_5_L2_LINEDEL_TRIG_REG = 0x12010C0Dull;
+
+static const uint64_t P9N2_EX_6_L2_LINEDEL_TRIG_REG = 0x1301080Dull;
+
+static const uint64_t P9N2_EX_7_L2_LINEDEL_TRIG_REG = 0x13010C0Dull;
+
+static const uint64_t P9N2_EX_8_L2_LINEDEL_TRIG_REG = 0x1401080Dull;
+
+static const uint64_t P9N2_EX_9_L2_LINEDEL_TRIG_REG = 0x14010C0Dull;
+
+static const uint64_t P9N2_EX_L2_LINEDEL_TRIG_REG = 0x1001080Dull;
+
+
+static const uint64_t P9N2_EQ_LINE_DELETED_MEMBERS_REG = 0x10011C15ull;
+//DUPS: 10011C15,
+static const uint64_t P9N2_EQ_0_LINE_DELETED_MEMBERS_REG = 0x10011C15ull;
+//DUPS: 10011C15,
+static const uint64_t P9N2_EQ_1_LINE_DELETED_MEMBERS_REG = 0x11011C15ull;
+//DUPS: 11011C15,
+static const uint64_t P9N2_EQ_2_LINE_DELETED_MEMBERS_REG = 0x12011C15ull;
+//DUPS: 12011C15,
+static const uint64_t P9N2_EQ_3_LINE_DELETED_MEMBERS_REG = 0x13011C15ull;
+//DUPS: 13011C15,
+static const uint64_t P9N2_EQ_4_LINE_DELETED_MEMBERS_REG = 0x14011C15ull;
+//DUPS: 14011C15,
+static const uint64_t P9N2_EQ_5_LINE_DELETED_MEMBERS_REG = 0x15011C15ull;
+//DUPS: 15011C15,
+static const uint64_t P9N2_EX_0_L3_LINE_DELETED_MEMBERS_REG = 0x10011815ull;
+
+static const uint64_t P9N2_EX_10_L3_LINE_DELETED_MEMBERS_REG = 0x15011815ull;
+
+static const uint64_t P9N2_EX_11_L3_LINE_DELETED_MEMBERS_REG = 0x15011C15ull;
+
+static const uint64_t P9N2_EX_1_L3_LINE_DELETED_MEMBERS_REG = 0x10011C15ull;
+
+static const uint64_t P9N2_EX_2_L3_LINE_DELETED_MEMBERS_REG = 0x11011815ull;
+
+static const uint64_t P9N2_EX_3_L3_LINE_DELETED_MEMBERS_REG = 0x11011C15ull;
+
+static const uint64_t P9N2_EX_4_L3_LINE_DELETED_MEMBERS_REG = 0x12011815ull;
+
+static const uint64_t P9N2_EX_5_L3_LINE_DELETED_MEMBERS_REG = 0x12011C15ull;
+
+static const uint64_t P9N2_EX_6_L3_LINE_DELETED_MEMBERS_REG = 0x13011815ull;
+
+static const uint64_t P9N2_EX_7_L3_LINE_DELETED_MEMBERS_REG = 0x13011C15ull;
+
+static const uint64_t P9N2_EX_8_L3_LINE_DELETED_MEMBERS_REG = 0x14011815ull;
+
+static const uint64_t P9N2_EX_9_L3_LINE_DELETED_MEMBERS_REG = 0x14011C15ull;
+
+static const uint64_t P9N2_EX_L3_LINE_DELETED_MEMBERS_REG = 0x10011815ull;
+
+
+static const uint64_t P9N2_C_LOCAL_FIR = 0x2004000Aull;
+
+static const uint64_t P9N2_C_LOCAL_FIR_AND = 0x2004000Bull;
+
+static const uint64_t P9N2_C_LOCAL_FIR_OR = 0x2004000Cull;
+
+static const uint64_t P9N2_C_0_LOCAL_FIR = 0x2004000Aull;
+
+static const uint64_t P9N2_C_0_LOCAL_FIR_AND = 0x2004000Bull;
+
+static const uint64_t P9N2_C_0_LOCAL_FIR_OR = 0x2004000Cull;
+
+static const uint64_t P9N2_C_1_LOCAL_FIR = 0x2104000Aull;
+
+static const uint64_t P9N2_C_1_LOCAL_FIR_AND = 0x2104000Bull;
+
+static const uint64_t P9N2_C_1_LOCAL_FIR_OR = 0x2104000Cull;
+
+static const uint64_t P9N2_C_2_LOCAL_FIR = 0x2204000Aull;
+
+static const uint64_t P9N2_C_2_LOCAL_FIR_AND = 0x2204000Bull;
+
+static const uint64_t P9N2_C_2_LOCAL_FIR_OR = 0x2204000Cull;
+
+static const uint64_t P9N2_C_3_LOCAL_FIR = 0x2304000Aull;
+
+static const uint64_t P9N2_C_3_LOCAL_FIR_AND = 0x2304000Bull;
+
+static const uint64_t P9N2_C_3_LOCAL_FIR_OR = 0x2304000Cull;
+
+static const uint64_t P9N2_C_4_LOCAL_FIR = 0x2404000Aull;
+
+static const uint64_t P9N2_C_4_LOCAL_FIR_AND = 0x2404000Bull;
+
+static const uint64_t P9N2_C_4_LOCAL_FIR_OR = 0x2404000Cull;
+
+static const uint64_t P9N2_C_5_LOCAL_FIR = 0x2504000Aull;
+
+static const uint64_t P9N2_C_5_LOCAL_FIR_AND = 0x2504000Bull;
+
+static const uint64_t P9N2_C_5_LOCAL_FIR_OR = 0x2504000Cull;
+
+static const uint64_t P9N2_C_6_LOCAL_FIR = 0x2604000Aull;
+
+static const uint64_t P9N2_C_6_LOCAL_FIR_AND = 0x2604000Bull;
+
+static const uint64_t P9N2_C_6_LOCAL_FIR_OR = 0x2604000Cull;
+
+static const uint64_t P9N2_C_7_LOCAL_FIR = 0x2704000Aull;
+
+static const uint64_t P9N2_C_7_LOCAL_FIR_AND = 0x2704000Bull;
+
+static const uint64_t P9N2_C_7_LOCAL_FIR_OR = 0x2704000Cull;
+
+static const uint64_t P9N2_C_8_LOCAL_FIR = 0x2804000Aull;
+
+static const uint64_t P9N2_C_8_LOCAL_FIR_AND = 0x2804000Bull;
+
+static const uint64_t P9N2_C_8_LOCAL_FIR_OR = 0x2804000Cull;
+
+static const uint64_t P9N2_C_9_LOCAL_FIR = 0x2904000Aull;
+
+static const uint64_t P9N2_C_9_LOCAL_FIR_AND = 0x2904000Bull;
+
+static const uint64_t P9N2_C_9_LOCAL_FIR_OR = 0x2904000Cull;
+
+static const uint64_t P9N2_C_10_LOCAL_FIR = 0x2A04000Aull;
+
+static const uint64_t P9N2_C_10_LOCAL_FIR_AND = 0x2A04000Bull;
+
+static const uint64_t P9N2_C_10_LOCAL_FIR_OR = 0x2A04000Cull;
+
+static const uint64_t P9N2_C_11_LOCAL_FIR = 0x2B04000Aull;
+
+static const uint64_t P9N2_C_11_LOCAL_FIR_AND = 0x2B04000Bull;
+
+static const uint64_t P9N2_C_11_LOCAL_FIR_OR = 0x2B04000Cull;
+
+static const uint64_t P9N2_C_12_LOCAL_FIR = 0x2C04000Aull;
+
+static const uint64_t P9N2_C_12_LOCAL_FIR_AND = 0x2C04000Bull;
+
+static const uint64_t P9N2_C_12_LOCAL_FIR_OR = 0x2C04000Cull;
+
+static const uint64_t P9N2_C_13_LOCAL_FIR = 0x2D04000Aull;
+
+static const uint64_t P9N2_C_13_LOCAL_FIR_AND = 0x2D04000Bull;
+
+static const uint64_t P9N2_C_13_LOCAL_FIR_OR = 0x2D04000Cull;
+
+static const uint64_t P9N2_C_14_LOCAL_FIR = 0x2E04000Aull;
+
+static const uint64_t P9N2_C_14_LOCAL_FIR_AND = 0x2E04000Bull;
+
+static const uint64_t P9N2_C_14_LOCAL_FIR_OR = 0x2E04000Cull;
+
+static const uint64_t P9N2_C_15_LOCAL_FIR = 0x2F04000Aull;
+
+static const uint64_t P9N2_C_15_LOCAL_FIR_AND = 0x2F04000Bull;
+
+static const uint64_t P9N2_C_15_LOCAL_FIR_OR = 0x2F04000Cull;
+
+static const uint64_t P9N2_C_16_LOCAL_FIR = 0x3004000Aull;
+
+static const uint64_t P9N2_C_16_LOCAL_FIR_AND = 0x3004000Bull;
+
+static const uint64_t P9N2_C_16_LOCAL_FIR_OR = 0x3004000Cull;
+
+static const uint64_t P9N2_C_17_LOCAL_FIR = 0x3104000Aull;
+
+static const uint64_t P9N2_C_17_LOCAL_FIR_AND = 0x3104000Bull;
+
+static const uint64_t P9N2_C_17_LOCAL_FIR_OR = 0x3104000Cull;
+
+static const uint64_t P9N2_C_18_LOCAL_FIR = 0x3204000Aull;
+
+static const uint64_t P9N2_C_18_LOCAL_FIR_AND = 0x3204000Bull;
+
+static const uint64_t P9N2_C_18_LOCAL_FIR_OR = 0x3204000Cull;
+
+static const uint64_t P9N2_C_19_LOCAL_FIR = 0x3304000Aull;
+
+static const uint64_t P9N2_C_19_LOCAL_FIR_AND = 0x3304000Bull;
+
+static const uint64_t P9N2_C_19_LOCAL_FIR_OR = 0x3304000Cull;
+
+static const uint64_t P9N2_C_20_LOCAL_FIR = 0x3404000Aull;
+
+static const uint64_t P9N2_C_20_LOCAL_FIR_AND = 0x3404000Bull;
+
+static const uint64_t P9N2_C_20_LOCAL_FIR_OR = 0x3404000Cull;
+
+static const uint64_t P9N2_C_21_LOCAL_FIR = 0x3504000Aull;
+
+static const uint64_t P9N2_C_21_LOCAL_FIR_AND = 0x3504000Bull;
+
+static const uint64_t P9N2_C_21_LOCAL_FIR_OR = 0x3504000Cull;
+
+static const uint64_t P9N2_C_22_LOCAL_FIR = 0x3604000Aull;
+
+static const uint64_t P9N2_C_22_LOCAL_FIR_AND = 0x3604000Bull;
+
+static const uint64_t P9N2_C_22_LOCAL_FIR_OR = 0x3604000Cull;
+
+static const uint64_t P9N2_C_23_LOCAL_FIR = 0x3704000Aull;
+
+static const uint64_t P9N2_C_23_LOCAL_FIR_AND = 0x3704000Bull;
+
+static const uint64_t P9N2_C_23_LOCAL_FIR_OR = 0x3704000Cull;
+
+static const uint64_t P9N2_EQ_LOCAL_FIR = 0x1004000Aull;
+
+static const uint64_t P9N2_EQ_LOCAL_FIR_AND = 0x1004000Bull;
+
+static const uint64_t P9N2_EQ_LOCAL_FIR_OR = 0x1004000Cull;
+
+static const uint64_t P9N2_EQ_0_LOCAL_FIR = 0x1004000Aull;
+
+static const uint64_t P9N2_EQ_0_LOCAL_FIR_AND = 0x1004000Bull;
+
+static const uint64_t P9N2_EQ_0_LOCAL_FIR_OR = 0x1004000Cull;
+
+static const uint64_t P9N2_EQ_1_LOCAL_FIR = 0x1104000Aull;
+
+static const uint64_t P9N2_EQ_1_LOCAL_FIR_AND = 0x1104000Bull;
+
+static const uint64_t P9N2_EQ_1_LOCAL_FIR_OR = 0x1104000Cull;
+
+static const uint64_t P9N2_EQ_2_LOCAL_FIR = 0x1204000Aull;
+
+static const uint64_t P9N2_EQ_2_LOCAL_FIR_AND = 0x1204000Bull;
+
+static const uint64_t P9N2_EQ_2_LOCAL_FIR_OR = 0x1204000Cull;
+
+static const uint64_t P9N2_EQ_3_LOCAL_FIR = 0x1304000Aull;
+
+static const uint64_t P9N2_EQ_3_LOCAL_FIR_AND = 0x1304000Bull;
+
+static const uint64_t P9N2_EQ_3_LOCAL_FIR_OR = 0x1304000Cull;
+
+static const uint64_t P9N2_EQ_4_LOCAL_FIR = 0x1404000Aull;
+
+static const uint64_t P9N2_EQ_4_LOCAL_FIR_AND = 0x1404000Bull;
+
+static const uint64_t P9N2_EQ_4_LOCAL_FIR_OR = 0x1404000Cull;
+
+static const uint64_t P9N2_EQ_5_LOCAL_FIR = 0x1504000Aull;
+
+static const uint64_t P9N2_EQ_5_LOCAL_FIR_AND = 0x1504000Bull;
+
+static const uint64_t P9N2_EQ_5_LOCAL_FIR_OR = 0x1504000Cull;
+
+static const uint64_t P9N2_EX_LOCAL_FIR = 0x2004000Aull;
+//DUPS: 2104000A,
+static const uint64_t P9N2_EX_LOCAL_FIR_AND = 0x2004000Bull;
+//DUPS: 2104000B,
+static const uint64_t P9N2_EX_LOCAL_FIR_OR = 0x2004000Cull;
+//DUPS: 2104000C,
+static const uint64_t P9N2_EX_0_LOCAL_FIR = 0x2004000Aull;
+//DUPS: 2104000A,
+static const uint64_t P9N2_EX_0_LOCAL_FIR_AND = 0x2004000Bull;
+//DUPS: 2104000B,
+static const uint64_t P9N2_EX_0_LOCAL_FIR_OR = 0x2004000Cull;
+//DUPS: 2104000C,
+static const uint64_t P9N2_EX_1_LOCAL_FIR = 0x2204000Aull;
+//DUPS: 2304000A,
+static const uint64_t P9N2_EX_1_LOCAL_FIR_AND = 0x2204000Bull;
+//DUPS: 2304000B,
+static const uint64_t P9N2_EX_1_LOCAL_FIR_OR = 0x2204000Cull;
+//DUPS: 2304000C,
+static const uint64_t P9N2_EX_2_LOCAL_FIR = 0x2404000Aull;
+//DUPS: 2504000A,
+static const uint64_t P9N2_EX_2_LOCAL_FIR_AND = 0x2404000Bull;
+//DUPS: 2504000B,
+static const uint64_t P9N2_EX_2_LOCAL_FIR_OR = 0x2404000Cull;
+//DUPS: 2504000C,
+static const uint64_t P9N2_EX_3_LOCAL_FIR = 0x2604000Aull;
+//DUPS: 2704000A,
+static const uint64_t P9N2_EX_3_LOCAL_FIR_AND = 0x2604000Bull;
+//DUPS: 2704000B,
+static const uint64_t P9N2_EX_3_LOCAL_FIR_OR = 0x2604000Cull;
+//DUPS: 2704000C,
+static const uint64_t P9N2_EX_4_LOCAL_FIR = 0x2804000Aull;
+//DUPS: 2904000A,
+static const uint64_t P9N2_EX_4_LOCAL_FIR_AND = 0x2804000Bull;
+//DUPS: 2904000B,
+static const uint64_t P9N2_EX_4_LOCAL_FIR_OR = 0x2804000Cull;
+//DUPS: 2904000C,
+static const uint64_t P9N2_EX_5_LOCAL_FIR = 0x2A04000Aull;
+//DUPS: 2B04000A,
+static const uint64_t P9N2_EX_5_LOCAL_FIR_AND = 0x2A04000Bull;
+//DUPS: 2B04000B,
+static const uint64_t P9N2_EX_5_LOCAL_FIR_OR = 0x2A04000Cull;
+//DUPS: 2B04000C,
+static const uint64_t P9N2_EX_6_LOCAL_FIR = 0x2C04000Aull;
+//DUPS: 2D04000A,
+static const uint64_t P9N2_EX_6_LOCAL_FIR_AND = 0x2C04000Bull;
+//DUPS: 2D04000B,
+static const uint64_t P9N2_EX_6_LOCAL_FIR_OR = 0x2C04000Cull;
+//DUPS: 2D04000C,
+static const uint64_t P9N2_EX_7_LOCAL_FIR = 0x2F04000Aull;
+//DUPS: 2F04000A,
+static const uint64_t P9N2_EX_7_LOCAL_FIR_AND = 0x2F04000Bull;
+//DUPS: 2F04000B,
+static const uint64_t P9N2_EX_7_LOCAL_FIR_OR = 0x2F04000Cull;
+//DUPS: 2F04000C,
+static const uint64_t P9N2_EX_8_LOCAL_FIR = 0x3004000Aull;
+//DUPS: 3104000A,
+static const uint64_t P9N2_EX_8_LOCAL_FIR_AND = 0x3004000Bull;
+//DUPS: 3104000B,
+static const uint64_t P9N2_EX_8_LOCAL_FIR_OR = 0x3004000Cull;
+//DUPS: 3104000C,
+static const uint64_t P9N2_EX_9_LOCAL_FIR = 0x3204000Aull;
+//DUPS: 3304000A,
+static const uint64_t P9N2_EX_9_LOCAL_FIR_AND = 0x3204000Bull;
+//DUPS: 3304000B,
+static const uint64_t P9N2_EX_9_LOCAL_FIR_OR = 0x3204000Cull;
+//DUPS: 3304000C,
+static const uint64_t P9N2_EX_10_LOCAL_FIR = 0x3404000Aull;
+//DUPS: 3504000A,
+static const uint64_t P9N2_EX_10_LOCAL_FIR_AND = 0x3404000Bull;
+//DUPS: 3504000B,
+static const uint64_t P9N2_EX_10_LOCAL_FIR_OR = 0x3404000Cull;
+//DUPS: 3504000C,
+static const uint64_t P9N2_EX_11_LOCAL_FIR = 0x3604000Aull;
+//DUPS: 3704000A,
+static const uint64_t P9N2_EX_11_LOCAL_FIR_AND = 0x3604000Bull;
+//DUPS: 3704000B,
+static const uint64_t P9N2_EX_11_LOCAL_FIR_OR = 0x3604000Cull;
+//DUPS: 3704000C,
+
+static const uint64_t P9N2_C_LOCAL_FIR_ACTION0 = 0x20040010ull;
+
+static const uint64_t P9N2_C_0_LOCAL_FIR_ACTION0 = 0x20040010ull;
+
+static const uint64_t P9N2_C_1_LOCAL_FIR_ACTION0 = 0x21040010ull;
+
+static const uint64_t P9N2_C_2_LOCAL_FIR_ACTION0 = 0x22040010ull;
+
+static const uint64_t P9N2_C_3_LOCAL_FIR_ACTION0 = 0x23040010ull;
+
+static const uint64_t P9N2_C_4_LOCAL_FIR_ACTION0 = 0x24040010ull;
+
+static const uint64_t P9N2_C_5_LOCAL_FIR_ACTION0 = 0x25040010ull;
+
+static const uint64_t P9N2_C_6_LOCAL_FIR_ACTION0 = 0x26040010ull;
+
+static const uint64_t P9N2_C_7_LOCAL_FIR_ACTION0 = 0x27040010ull;
+
+static const uint64_t P9N2_C_8_LOCAL_FIR_ACTION0 = 0x28040010ull;
+
+static const uint64_t P9N2_C_9_LOCAL_FIR_ACTION0 = 0x29040010ull;
+
+static const uint64_t P9N2_C_10_LOCAL_FIR_ACTION0 = 0x2A040010ull;
+
+static const uint64_t P9N2_C_11_LOCAL_FIR_ACTION0 = 0x2B040010ull;
+
+static const uint64_t P9N2_C_12_LOCAL_FIR_ACTION0 = 0x2C040010ull;
+
+static const uint64_t P9N2_C_13_LOCAL_FIR_ACTION0 = 0x2D040010ull;
+
+static const uint64_t P9N2_C_14_LOCAL_FIR_ACTION0 = 0x2E040010ull;
+
+static const uint64_t P9N2_C_15_LOCAL_FIR_ACTION0 = 0x2F040010ull;
+
+static const uint64_t P9N2_C_16_LOCAL_FIR_ACTION0 = 0x30040010ull;
+
+static const uint64_t P9N2_C_17_LOCAL_FIR_ACTION0 = 0x31040010ull;
+
+static const uint64_t P9N2_C_18_LOCAL_FIR_ACTION0 = 0x32040010ull;
+
+static const uint64_t P9N2_C_19_LOCAL_FIR_ACTION0 = 0x33040010ull;
+
+static const uint64_t P9N2_C_20_LOCAL_FIR_ACTION0 = 0x34040010ull;
+
+static const uint64_t P9N2_C_21_LOCAL_FIR_ACTION0 = 0x35040010ull;
+
+static const uint64_t P9N2_C_22_LOCAL_FIR_ACTION0 = 0x36040010ull;
+
+static const uint64_t P9N2_C_23_LOCAL_FIR_ACTION0 = 0x37040010ull;
+
+static const uint64_t P9N2_EQ_LOCAL_FIR_ACTION0 = 0x10040010ull;
+
+static const uint64_t P9N2_EQ_0_LOCAL_FIR_ACTION0 = 0x10040010ull;
+
+static const uint64_t P9N2_EQ_1_LOCAL_FIR_ACTION0 = 0x11040010ull;
+
+static const uint64_t P9N2_EQ_2_LOCAL_FIR_ACTION0 = 0x12040010ull;
+
+static const uint64_t P9N2_EQ_3_LOCAL_FIR_ACTION0 = 0x13040010ull;
+
+static const uint64_t P9N2_EQ_4_LOCAL_FIR_ACTION0 = 0x14040010ull;
+
+static const uint64_t P9N2_EQ_5_LOCAL_FIR_ACTION0 = 0x15040010ull;
+
+static const uint64_t P9N2_EX_LOCAL_FIR_ACTION0 = 0x20040010ull;
+//DUPS: 21040010,
+static const uint64_t P9N2_EX_0_LOCAL_FIR_ACTION0 = 0x20040010ull;
+//DUPS: 21040010,
+static const uint64_t P9N2_EX_1_LOCAL_FIR_ACTION0 = 0x22040010ull;
+//DUPS: 23040010,
+static const uint64_t P9N2_EX_2_LOCAL_FIR_ACTION0 = 0x24040010ull;
+//DUPS: 25040010,
+static const uint64_t P9N2_EX_3_LOCAL_FIR_ACTION0 = 0x26040010ull;
+//DUPS: 27040010,
+static const uint64_t P9N2_EX_4_LOCAL_FIR_ACTION0 = 0x28040010ull;
+//DUPS: 29040010,
+static const uint64_t P9N2_EX_5_LOCAL_FIR_ACTION0 = 0x2A040010ull;
+//DUPS: 2B040010,
+static const uint64_t P9N2_EX_6_LOCAL_FIR_ACTION0 = 0x2C040010ull;
+//DUPS: 2D040010,
+static const uint64_t P9N2_EX_7_LOCAL_FIR_ACTION0 = 0x2F040010ull;
+//DUPS: 2F040010,
+static const uint64_t P9N2_EX_8_LOCAL_FIR_ACTION0 = 0x30040010ull;
+//DUPS: 31040010,
+static const uint64_t P9N2_EX_9_LOCAL_FIR_ACTION0 = 0x32040010ull;
+//DUPS: 33040010,
+static const uint64_t P9N2_EX_10_LOCAL_FIR_ACTION0 = 0x34040010ull;
+//DUPS: 35040010,
+static const uint64_t P9N2_EX_11_LOCAL_FIR_ACTION0 = 0x36040010ull;
+//DUPS: 37040010,
+
+static const uint64_t P9N2_C_LOCAL_FIR_ACTION1 = 0x20040011ull;
+
+static const uint64_t P9N2_C_0_LOCAL_FIR_ACTION1 = 0x20040011ull;
+
+static const uint64_t P9N2_C_1_LOCAL_FIR_ACTION1 = 0x21040011ull;
+
+static const uint64_t P9N2_C_2_LOCAL_FIR_ACTION1 = 0x22040011ull;
+
+static const uint64_t P9N2_C_3_LOCAL_FIR_ACTION1 = 0x23040011ull;
+
+static const uint64_t P9N2_C_4_LOCAL_FIR_ACTION1 = 0x24040011ull;
+
+static const uint64_t P9N2_C_5_LOCAL_FIR_ACTION1 = 0x25040011ull;
+
+static const uint64_t P9N2_C_6_LOCAL_FIR_ACTION1 = 0x26040011ull;
+
+static const uint64_t P9N2_C_7_LOCAL_FIR_ACTION1 = 0x27040011ull;
+
+static const uint64_t P9N2_C_8_LOCAL_FIR_ACTION1 = 0x28040011ull;
+
+static const uint64_t P9N2_C_9_LOCAL_FIR_ACTION1 = 0x29040011ull;
+
+static const uint64_t P9N2_C_10_LOCAL_FIR_ACTION1 = 0x2A040011ull;
+
+static const uint64_t P9N2_C_11_LOCAL_FIR_ACTION1 = 0x2B040011ull;
+
+static const uint64_t P9N2_C_12_LOCAL_FIR_ACTION1 = 0x2C040011ull;
+
+static const uint64_t P9N2_C_13_LOCAL_FIR_ACTION1 = 0x2D040011ull;
+
+static const uint64_t P9N2_C_14_LOCAL_FIR_ACTION1 = 0x2E040011ull;
+
+static const uint64_t P9N2_C_15_LOCAL_FIR_ACTION1 = 0x2F040011ull;
+
+static const uint64_t P9N2_C_16_LOCAL_FIR_ACTION1 = 0x30040011ull;
+
+static const uint64_t P9N2_C_17_LOCAL_FIR_ACTION1 = 0x31040011ull;
+
+static const uint64_t P9N2_C_18_LOCAL_FIR_ACTION1 = 0x32040011ull;
+
+static const uint64_t P9N2_C_19_LOCAL_FIR_ACTION1 = 0x33040011ull;
+
+static const uint64_t P9N2_C_20_LOCAL_FIR_ACTION1 = 0x34040011ull;
+
+static const uint64_t P9N2_C_21_LOCAL_FIR_ACTION1 = 0x35040011ull;
+
+static const uint64_t P9N2_C_22_LOCAL_FIR_ACTION1 = 0x36040011ull;
+
+static const uint64_t P9N2_C_23_LOCAL_FIR_ACTION1 = 0x37040011ull;
+
+static const uint64_t P9N2_EQ_LOCAL_FIR_ACTION1 = 0x10040011ull;
+
+static const uint64_t P9N2_EQ_0_LOCAL_FIR_ACTION1 = 0x10040011ull;
+
+static const uint64_t P9N2_EQ_1_LOCAL_FIR_ACTION1 = 0x11040011ull;
+
+static const uint64_t P9N2_EQ_2_LOCAL_FIR_ACTION1 = 0x12040011ull;
+
+static const uint64_t P9N2_EQ_3_LOCAL_FIR_ACTION1 = 0x13040011ull;
+
+static const uint64_t P9N2_EQ_4_LOCAL_FIR_ACTION1 = 0x14040011ull;
+
+static const uint64_t P9N2_EQ_5_LOCAL_FIR_ACTION1 = 0x15040011ull;
+
+static const uint64_t P9N2_EX_LOCAL_FIR_ACTION1 = 0x20040011ull;
+//DUPS: 21040011,
+static const uint64_t P9N2_EX_0_LOCAL_FIR_ACTION1 = 0x20040011ull;
+//DUPS: 21040011,
+static const uint64_t P9N2_EX_1_LOCAL_FIR_ACTION1 = 0x22040011ull;
+//DUPS: 23040011,
+static const uint64_t P9N2_EX_2_LOCAL_FIR_ACTION1 = 0x24040011ull;
+//DUPS: 25040011,
+static const uint64_t P9N2_EX_3_LOCAL_FIR_ACTION1 = 0x26040011ull;
+//DUPS: 27040011,
+static const uint64_t P9N2_EX_4_LOCAL_FIR_ACTION1 = 0x28040011ull;
+//DUPS: 29040011,
+static const uint64_t P9N2_EX_5_LOCAL_FIR_ACTION1 = 0x2A040011ull;
+//DUPS: 2B040011,
+static const uint64_t P9N2_EX_6_LOCAL_FIR_ACTION1 = 0x2C040011ull;
+//DUPS: 2D040011,
+static const uint64_t P9N2_EX_7_LOCAL_FIR_ACTION1 = 0x2F040011ull;
+//DUPS: 2F040011,
+static const uint64_t P9N2_EX_8_LOCAL_FIR_ACTION1 = 0x30040011ull;
+//DUPS: 31040011,
+static const uint64_t P9N2_EX_9_LOCAL_FIR_ACTION1 = 0x32040011ull;
+//DUPS: 33040011,
+static const uint64_t P9N2_EX_10_LOCAL_FIR_ACTION1 = 0x34040011ull;
+//DUPS: 35040011,
+static const uint64_t P9N2_EX_11_LOCAL_FIR_ACTION1 = 0x36040011ull;
+//DUPS: 37040011,
+
+static const uint64_t P9N2_C_LOCAL_FIR_MASK = 0x2004000Dull;
+
+static const uint64_t P9N2_C_LOCAL_FIR_MASK_AND = 0x2004000Eull;
+
+static const uint64_t P9N2_C_LOCAL_FIR_MASK_OR = 0x2004000Full;
+
+static const uint64_t P9N2_C_0_LOCAL_FIR_MASK = 0x2004000Dull;
+
+static const uint64_t P9N2_C_0_LOCAL_FIR_MASK_AND = 0x2004000Eull;
+
+static const uint64_t P9N2_C_0_LOCAL_FIR_MASK_OR = 0x2004000Full;
+
+static const uint64_t P9N2_C_1_LOCAL_FIR_MASK = 0x2104000Dull;
+
+static const uint64_t P9N2_C_1_LOCAL_FIR_MASK_AND = 0x2104000Eull;
+
+static const uint64_t P9N2_C_1_LOCAL_FIR_MASK_OR = 0x2104000Full;
+
+static const uint64_t P9N2_C_2_LOCAL_FIR_MASK = 0x2204000Dull;
+
+static const uint64_t P9N2_C_2_LOCAL_FIR_MASK_AND = 0x2204000Eull;
+
+static const uint64_t P9N2_C_2_LOCAL_FIR_MASK_OR = 0x2204000Full;
+
+static const uint64_t P9N2_C_3_LOCAL_FIR_MASK = 0x2304000Dull;
+
+static const uint64_t P9N2_C_3_LOCAL_FIR_MASK_AND = 0x2304000Eull;
+
+static const uint64_t P9N2_C_3_LOCAL_FIR_MASK_OR = 0x2304000Full;
+
+static const uint64_t P9N2_C_4_LOCAL_FIR_MASK = 0x2404000Dull;
+
+static const uint64_t P9N2_C_4_LOCAL_FIR_MASK_AND = 0x2404000Eull;
+
+static const uint64_t P9N2_C_4_LOCAL_FIR_MASK_OR = 0x2404000Full;
+
+static const uint64_t P9N2_C_5_LOCAL_FIR_MASK = 0x2504000Dull;
+
+static const uint64_t P9N2_C_5_LOCAL_FIR_MASK_AND = 0x2504000Eull;
+
+static const uint64_t P9N2_C_5_LOCAL_FIR_MASK_OR = 0x2504000Full;
+
+static const uint64_t P9N2_C_6_LOCAL_FIR_MASK = 0x2604000Dull;
+
+static const uint64_t P9N2_C_6_LOCAL_FIR_MASK_AND = 0x2604000Eull;
+
+static const uint64_t P9N2_C_6_LOCAL_FIR_MASK_OR = 0x2604000Full;
+
+static const uint64_t P9N2_C_7_LOCAL_FIR_MASK = 0x2704000Dull;
+
+static const uint64_t P9N2_C_7_LOCAL_FIR_MASK_AND = 0x2704000Eull;
+
+static const uint64_t P9N2_C_7_LOCAL_FIR_MASK_OR = 0x2704000Full;
+
+static const uint64_t P9N2_C_8_LOCAL_FIR_MASK = 0x2804000Dull;
+
+static const uint64_t P9N2_C_8_LOCAL_FIR_MASK_AND = 0x2804000Eull;
+
+static const uint64_t P9N2_C_8_LOCAL_FIR_MASK_OR = 0x2804000Full;
+
+static const uint64_t P9N2_C_9_LOCAL_FIR_MASK = 0x2904000Dull;
+
+static const uint64_t P9N2_C_9_LOCAL_FIR_MASK_AND = 0x2904000Eull;
+
+static const uint64_t P9N2_C_9_LOCAL_FIR_MASK_OR = 0x2904000Full;
+
+static const uint64_t P9N2_C_10_LOCAL_FIR_MASK = 0x2A04000Dull;
+
+static const uint64_t P9N2_C_10_LOCAL_FIR_MASK_AND = 0x2A04000Eull;
+
+static const uint64_t P9N2_C_10_LOCAL_FIR_MASK_OR = 0x2A04000Full;
+
+static const uint64_t P9N2_C_11_LOCAL_FIR_MASK = 0x2B04000Dull;
+
+static const uint64_t P9N2_C_11_LOCAL_FIR_MASK_AND = 0x2B04000Eull;
+
+static const uint64_t P9N2_C_11_LOCAL_FIR_MASK_OR = 0x2B04000Full;
+
+static const uint64_t P9N2_C_12_LOCAL_FIR_MASK = 0x2C04000Dull;
+
+static const uint64_t P9N2_C_12_LOCAL_FIR_MASK_AND = 0x2C04000Eull;
+
+static const uint64_t P9N2_C_12_LOCAL_FIR_MASK_OR = 0x2C04000Full;
+
+static const uint64_t P9N2_C_13_LOCAL_FIR_MASK = 0x2D04000Dull;
+
+static const uint64_t P9N2_C_13_LOCAL_FIR_MASK_AND = 0x2D04000Eull;
+
+static const uint64_t P9N2_C_13_LOCAL_FIR_MASK_OR = 0x2D04000Full;
+
+static const uint64_t P9N2_C_14_LOCAL_FIR_MASK = 0x2E04000Dull;
+
+static const uint64_t P9N2_C_14_LOCAL_FIR_MASK_AND = 0x2E04000Eull;
+
+static const uint64_t P9N2_C_14_LOCAL_FIR_MASK_OR = 0x2E04000Full;
+
+static const uint64_t P9N2_C_15_LOCAL_FIR_MASK = 0x2F04000Dull;
+
+static const uint64_t P9N2_C_15_LOCAL_FIR_MASK_AND = 0x2F04000Eull;
+
+static const uint64_t P9N2_C_15_LOCAL_FIR_MASK_OR = 0x2F04000Full;
+
+static const uint64_t P9N2_C_16_LOCAL_FIR_MASK = 0x3004000Dull;
+
+static const uint64_t P9N2_C_16_LOCAL_FIR_MASK_AND = 0x3004000Eull;
+
+static const uint64_t P9N2_C_16_LOCAL_FIR_MASK_OR = 0x3004000Full;
+
+static const uint64_t P9N2_C_17_LOCAL_FIR_MASK = 0x3104000Dull;
+
+static const uint64_t P9N2_C_17_LOCAL_FIR_MASK_AND = 0x3104000Eull;
+
+static const uint64_t P9N2_C_17_LOCAL_FIR_MASK_OR = 0x3104000Full;
+
+static const uint64_t P9N2_C_18_LOCAL_FIR_MASK = 0x3204000Dull;
+
+static const uint64_t P9N2_C_18_LOCAL_FIR_MASK_AND = 0x3204000Eull;
+
+static const uint64_t P9N2_C_18_LOCAL_FIR_MASK_OR = 0x3204000Full;
+
+static const uint64_t P9N2_C_19_LOCAL_FIR_MASK = 0x3304000Dull;
+
+static const uint64_t P9N2_C_19_LOCAL_FIR_MASK_AND = 0x3304000Eull;
+
+static const uint64_t P9N2_C_19_LOCAL_FIR_MASK_OR = 0x3304000Full;
+
+static const uint64_t P9N2_C_20_LOCAL_FIR_MASK = 0x3404000Dull;
+
+static const uint64_t P9N2_C_20_LOCAL_FIR_MASK_AND = 0x3404000Eull;
+
+static const uint64_t P9N2_C_20_LOCAL_FIR_MASK_OR = 0x3404000Full;
+
+static const uint64_t P9N2_C_21_LOCAL_FIR_MASK = 0x3504000Dull;
+
+static const uint64_t P9N2_C_21_LOCAL_FIR_MASK_AND = 0x3504000Eull;
+
+static const uint64_t P9N2_C_21_LOCAL_FIR_MASK_OR = 0x3504000Full;
+
+static const uint64_t P9N2_C_22_LOCAL_FIR_MASK = 0x3604000Dull;
+
+static const uint64_t P9N2_C_22_LOCAL_FIR_MASK_AND = 0x3604000Eull;
+
+static const uint64_t P9N2_C_22_LOCAL_FIR_MASK_OR = 0x3604000Full;
+
+static const uint64_t P9N2_C_23_LOCAL_FIR_MASK = 0x3704000Dull;
+
+static const uint64_t P9N2_C_23_LOCAL_FIR_MASK_AND = 0x3704000Eull;
+
+static const uint64_t P9N2_C_23_LOCAL_FIR_MASK_OR = 0x3704000Full;
+
+static const uint64_t P9N2_EQ_LOCAL_FIR_MASK = 0x1004000Dull;
+
+static const uint64_t P9N2_EQ_LOCAL_FIR_MASK_AND = 0x1004000Eull;
+
+static const uint64_t P9N2_EQ_LOCAL_FIR_MASK_OR = 0x1004000Full;
+
+static const uint64_t P9N2_EQ_0_LOCAL_FIR_MASK = 0x1004000Dull;
+
+static const uint64_t P9N2_EQ_0_LOCAL_FIR_MASK_AND = 0x1004000Eull;
+
+static const uint64_t P9N2_EQ_0_LOCAL_FIR_MASK_OR = 0x1004000Full;
+
+static const uint64_t P9N2_EQ_1_LOCAL_FIR_MASK = 0x1104000Dull;
+
+static const uint64_t P9N2_EQ_1_LOCAL_FIR_MASK_AND = 0x1104000Eull;
+
+static const uint64_t P9N2_EQ_1_LOCAL_FIR_MASK_OR = 0x1104000Full;
+
+static const uint64_t P9N2_EQ_2_LOCAL_FIR_MASK = 0x1204000Dull;
+
+static const uint64_t P9N2_EQ_2_LOCAL_FIR_MASK_AND = 0x1204000Eull;
+
+static const uint64_t P9N2_EQ_2_LOCAL_FIR_MASK_OR = 0x1204000Full;
+
+static const uint64_t P9N2_EQ_3_LOCAL_FIR_MASK = 0x1304000Dull;
+
+static const uint64_t P9N2_EQ_3_LOCAL_FIR_MASK_AND = 0x1304000Eull;
+
+static const uint64_t P9N2_EQ_3_LOCAL_FIR_MASK_OR = 0x1304000Full;
+
+static const uint64_t P9N2_EQ_4_LOCAL_FIR_MASK = 0x1404000Dull;
+
+static const uint64_t P9N2_EQ_4_LOCAL_FIR_MASK_AND = 0x1404000Eull;
+
+static const uint64_t P9N2_EQ_4_LOCAL_FIR_MASK_OR = 0x1404000Full;
+
+static const uint64_t P9N2_EQ_5_LOCAL_FIR_MASK = 0x1504000Dull;
+
+static const uint64_t P9N2_EQ_5_LOCAL_FIR_MASK_AND = 0x1504000Eull;
+
+static const uint64_t P9N2_EQ_5_LOCAL_FIR_MASK_OR = 0x1504000Full;
+
+static const uint64_t P9N2_EX_LOCAL_FIR_MASK = 0x2004000Dull;
+//DUPS: 2104000D,
+static const uint64_t P9N2_EX_LOCAL_FIR_MASK_AND = 0x2004000Eull;
+//DUPS: 2104000E,
+static const uint64_t P9N2_EX_LOCAL_FIR_MASK_OR = 0x2004000Full;
+//DUPS: 2104000F,
+static const uint64_t P9N2_EX_0_LOCAL_FIR_MASK = 0x2004000Dull;
+//DUPS: 2104000D,
+static const uint64_t P9N2_EX_0_LOCAL_FIR_MASK_AND = 0x2004000Eull;
+//DUPS: 2104000E,
+static const uint64_t P9N2_EX_0_LOCAL_FIR_MASK_OR = 0x2004000Full;
+//DUPS: 2104000F,
+static const uint64_t P9N2_EX_1_LOCAL_FIR_MASK = 0x2204000Dull;
+//DUPS: 2304000D,
+static const uint64_t P9N2_EX_1_LOCAL_FIR_MASK_AND = 0x2204000Eull;
+//DUPS: 2304000E,
+static const uint64_t P9N2_EX_1_LOCAL_FIR_MASK_OR = 0x2204000Full;
+//DUPS: 2304000F,
+static const uint64_t P9N2_EX_2_LOCAL_FIR_MASK = 0x2404000Dull;
+//DUPS: 2504000D,
+static const uint64_t P9N2_EX_2_LOCAL_FIR_MASK_AND = 0x2404000Eull;
+//DUPS: 2504000E,
+static const uint64_t P9N2_EX_2_LOCAL_FIR_MASK_OR = 0x2404000Full;
+//DUPS: 2504000F,
+static const uint64_t P9N2_EX_3_LOCAL_FIR_MASK = 0x2604000Dull;
+//DUPS: 2704000D,
+static const uint64_t P9N2_EX_3_LOCAL_FIR_MASK_AND = 0x2604000Eull;
+//DUPS: 2704000E,
+static const uint64_t P9N2_EX_3_LOCAL_FIR_MASK_OR = 0x2604000Full;
+//DUPS: 2704000F,
+static const uint64_t P9N2_EX_4_LOCAL_FIR_MASK = 0x2804000Dull;
+//DUPS: 2904000D,
+static const uint64_t P9N2_EX_4_LOCAL_FIR_MASK_AND = 0x2804000Eull;
+//DUPS: 2904000E,
+static const uint64_t P9N2_EX_4_LOCAL_FIR_MASK_OR = 0x2804000Full;
+//DUPS: 2904000F,
+static const uint64_t P9N2_EX_5_LOCAL_FIR_MASK = 0x2A04000Dull;
+//DUPS: 2B04000D,
+static const uint64_t P9N2_EX_5_LOCAL_FIR_MASK_AND = 0x2A04000Eull;
+//DUPS: 2B04000E,
+static const uint64_t P9N2_EX_5_LOCAL_FIR_MASK_OR = 0x2A04000Full;
+//DUPS: 2B04000F,
+static const uint64_t P9N2_EX_6_LOCAL_FIR_MASK = 0x2C04000Dull;
+//DUPS: 2D04000D,
+static const uint64_t P9N2_EX_6_LOCAL_FIR_MASK_AND = 0x2C04000Eull;
+//DUPS: 2D04000E,
+static const uint64_t P9N2_EX_6_LOCAL_FIR_MASK_OR = 0x2C04000Full;
+//DUPS: 2D04000F,
+static const uint64_t P9N2_EX_7_LOCAL_FIR_MASK = 0x2F04000Dull;
+//DUPS: 2F04000D,
+static const uint64_t P9N2_EX_7_LOCAL_FIR_MASK_AND = 0x2F04000Eull;
+//DUPS: 2F04000E,
+static const uint64_t P9N2_EX_7_LOCAL_FIR_MASK_OR = 0x2F04000Full;
+//DUPS: 2F04000F,
+static const uint64_t P9N2_EX_8_LOCAL_FIR_MASK = 0x3004000Dull;
+//DUPS: 3104000D,
+static const uint64_t P9N2_EX_8_LOCAL_FIR_MASK_AND = 0x3004000Eull;
+//DUPS: 3104000E,
+static const uint64_t P9N2_EX_8_LOCAL_FIR_MASK_OR = 0x3004000Full;
+//DUPS: 3104000F,
+static const uint64_t P9N2_EX_9_LOCAL_FIR_MASK = 0x3204000Dull;
+//DUPS: 3304000D,
+static const uint64_t P9N2_EX_9_LOCAL_FIR_MASK_AND = 0x3204000Eull;
+//DUPS: 3304000E,
+static const uint64_t P9N2_EX_9_LOCAL_FIR_MASK_OR = 0x3204000Full;
+//DUPS: 3304000F,
+static const uint64_t P9N2_EX_10_LOCAL_FIR_MASK = 0x3404000Dull;
+//DUPS: 3504000D,
+static const uint64_t P9N2_EX_10_LOCAL_FIR_MASK_AND = 0x3404000Eull;
+//DUPS: 3504000E,
+static const uint64_t P9N2_EX_10_LOCAL_FIR_MASK_OR = 0x3404000Full;
+//DUPS: 3504000F,
+static const uint64_t P9N2_EX_11_LOCAL_FIR_MASK = 0x3604000Dull;
+//DUPS: 3704000D,
+static const uint64_t P9N2_EX_11_LOCAL_FIR_MASK_AND = 0x3604000Eull;
+//DUPS: 3704000E,
+static const uint64_t P9N2_EX_11_LOCAL_FIR_MASK_OR = 0x3604000Full;
+//DUPS: 3704000F,
+
+static const uint64_t P9N2_C_LOCAL_XSTOP_ERR = 0x20040018ull;
+
+static const uint64_t P9N2_C_0_LOCAL_XSTOP_ERR = 0x20040018ull;
+
+static const uint64_t P9N2_C_1_LOCAL_XSTOP_ERR = 0x21040018ull;
+
+static const uint64_t P9N2_C_2_LOCAL_XSTOP_ERR = 0x22040018ull;
+
+static const uint64_t P9N2_C_3_LOCAL_XSTOP_ERR = 0x23040018ull;
+
+static const uint64_t P9N2_C_4_LOCAL_XSTOP_ERR = 0x24040018ull;
+
+static const uint64_t P9N2_C_5_LOCAL_XSTOP_ERR = 0x25040018ull;
+
+static const uint64_t P9N2_C_6_LOCAL_XSTOP_ERR = 0x26040018ull;
+
+static const uint64_t P9N2_C_7_LOCAL_XSTOP_ERR = 0x27040018ull;
+
+static const uint64_t P9N2_C_8_LOCAL_XSTOP_ERR = 0x28040018ull;
+
+static const uint64_t P9N2_C_9_LOCAL_XSTOP_ERR = 0x29040018ull;
+
+static const uint64_t P9N2_C_10_LOCAL_XSTOP_ERR = 0x2A040018ull;
+
+static const uint64_t P9N2_C_11_LOCAL_XSTOP_ERR = 0x2B040018ull;
+
+static const uint64_t P9N2_C_12_LOCAL_XSTOP_ERR = 0x2C040018ull;
+
+static const uint64_t P9N2_C_13_LOCAL_XSTOP_ERR = 0x2D040018ull;
+
+static const uint64_t P9N2_C_14_LOCAL_XSTOP_ERR = 0x2E040018ull;
+
+static const uint64_t P9N2_C_15_LOCAL_XSTOP_ERR = 0x2F040018ull;
+
+static const uint64_t P9N2_C_16_LOCAL_XSTOP_ERR = 0x30040018ull;
+
+static const uint64_t P9N2_C_17_LOCAL_XSTOP_ERR = 0x31040018ull;
+
+static const uint64_t P9N2_C_18_LOCAL_XSTOP_ERR = 0x32040018ull;
+
+static const uint64_t P9N2_C_19_LOCAL_XSTOP_ERR = 0x33040018ull;
+
+static const uint64_t P9N2_C_20_LOCAL_XSTOP_ERR = 0x34040018ull;
+
+static const uint64_t P9N2_C_21_LOCAL_XSTOP_ERR = 0x35040018ull;
+
+static const uint64_t P9N2_C_22_LOCAL_XSTOP_ERR = 0x36040018ull;
+
+static const uint64_t P9N2_C_23_LOCAL_XSTOP_ERR = 0x37040018ull;
+
+static const uint64_t P9N2_EQ_LOCAL_XSTOP_ERR = 0x10040018ull;
+
+static const uint64_t P9N2_EQ_0_LOCAL_XSTOP_ERR = 0x10040018ull;
+
+static const uint64_t P9N2_EQ_1_LOCAL_XSTOP_ERR = 0x11040018ull;
+
+static const uint64_t P9N2_EQ_2_LOCAL_XSTOP_ERR = 0x12040018ull;
+
+static const uint64_t P9N2_EQ_3_LOCAL_XSTOP_ERR = 0x13040018ull;
+
+static const uint64_t P9N2_EQ_4_LOCAL_XSTOP_ERR = 0x14040018ull;
+
+static const uint64_t P9N2_EQ_5_LOCAL_XSTOP_ERR = 0x15040018ull;
+
+static const uint64_t P9N2_EX_LOCAL_XSTOP_ERR = 0x20040018ull;
+//DUPS: 21040018,
+static const uint64_t P9N2_EX_0_LOCAL_XSTOP_ERR = 0x20040018ull;
+//DUPS: 21040018,
+static const uint64_t P9N2_EX_1_LOCAL_XSTOP_ERR = 0x22040018ull;
+//DUPS: 23040018,
+static const uint64_t P9N2_EX_2_LOCAL_XSTOP_ERR = 0x24040018ull;
+//DUPS: 25040018,
+static const uint64_t P9N2_EX_3_LOCAL_XSTOP_ERR = 0x26040018ull;
+//DUPS: 27040018,
+static const uint64_t P9N2_EX_4_LOCAL_XSTOP_ERR = 0x28040018ull;
+//DUPS: 29040018,
+static const uint64_t P9N2_EX_5_LOCAL_XSTOP_ERR = 0x2A040018ull;
+//DUPS: 2B040018,
+static const uint64_t P9N2_EX_6_LOCAL_XSTOP_ERR = 0x2C040018ull;
+//DUPS: 2D040018,
+static const uint64_t P9N2_EX_7_LOCAL_XSTOP_ERR = 0x2F040018ull;
+//DUPS: 2F040018,
+static const uint64_t P9N2_EX_8_LOCAL_XSTOP_ERR = 0x30040018ull;
+//DUPS: 31040018,
+static const uint64_t P9N2_EX_9_LOCAL_XSTOP_ERR = 0x32040018ull;
+//DUPS: 33040018,
+static const uint64_t P9N2_EX_10_LOCAL_XSTOP_ERR = 0x34040018ull;
+//DUPS: 35040018,
+static const uint64_t P9N2_EX_11_LOCAL_XSTOP_ERR = 0x36040018ull;
+//DUPS: 37040018,
+
+static const uint64_t P9N2_C_LOCAL_XSTOP_MASK = 0x20040019ull;
+
+static const uint64_t P9N2_C_0_LOCAL_XSTOP_MASK = 0x20040019ull;
+
+static const uint64_t P9N2_C_1_LOCAL_XSTOP_MASK = 0x21040019ull;
+
+static const uint64_t P9N2_C_2_LOCAL_XSTOP_MASK = 0x22040019ull;
+
+static const uint64_t P9N2_C_3_LOCAL_XSTOP_MASK = 0x23040019ull;
+
+static const uint64_t P9N2_C_4_LOCAL_XSTOP_MASK = 0x24040019ull;
+
+static const uint64_t P9N2_C_5_LOCAL_XSTOP_MASK = 0x25040019ull;
+
+static const uint64_t P9N2_C_6_LOCAL_XSTOP_MASK = 0x26040019ull;
+
+static const uint64_t P9N2_C_7_LOCAL_XSTOP_MASK = 0x27040019ull;
+
+static const uint64_t P9N2_C_8_LOCAL_XSTOP_MASK = 0x28040019ull;
+
+static const uint64_t P9N2_C_9_LOCAL_XSTOP_MASK = 0x29040019ull;
+
+static const uint64_t P9N2_C_10_LOCAL_XSTOP_MASK = 0x2A040019ull;
+
+static const uint64_t P9N2_C_11_LOCAL_XSTOP_MASK = 0x2B040019ull;
+
+static const uint64_t P9N2_C_12_LOCAL_XSTOP_MASK = 0x2C040019ull;
+
+static const uint64_t P9N2_C_13_LOCAL_XSTOP_MASK = 0x2D040019ull;
+
+static const uint64_t P9N2_C_14_LOCAL_XSTOP_MASK = 0x2E040019ull;
+
+static const uint64_t P9N2_C_15_LOCAL_XSTOP_MASK = 0x2F040019ull;
+
+static const uint64_t P9N2_C_16_LOCAL_XSTOP_MASK = 0x30040019ull;
+
+static const uint64_t P9N2_C_17_LOCAL_XSTOP_MASK = 0x31040019ull;
+
+static const uint64_t P9N2_C_18_LOCAL_XSTOP_MASK = 0x32040019ull;
+
+static const uint64_t P9N2_C_19_LOCAL_XSTOP_MASK = 0x33040019ull;
+
+static const uint64_t P9N2_C_20_LOCAL_XSTOP_MASK = 0x34040019ull;
+
+static const uint64_t P9N2_C_21_LOCAL_XSTOP_MASK = 0x35040019ull;
+
+static const uint64_t P9N2_C_22_LOCAL_XSTOP_MASK = 0x36040019ull;
+
+static const uint64_t P9N2_C_23_LOCAL_XSTOP_MASK = 0x37040019ull;
+
+static const uint64_t P9N2_EQ_LOCAL_XSTOP_MASK = 0x10040019ull;
+
+static const uint64_t P9N2_EQ_0_LOCAL_XSTOP_MASK = 0x10040019ull;
+
+static const uint64_t P9N2_EQ_1_LOCAL_XSTOP_MASK = 0x11040019ull;
+
+static const uint64_t P9N2_EQ_2_LOCAL_XSTOP_MASK = 0x12040019ull;
+
+static const uint64_t P9N2_EQ_3_LOCAL_XSTOP_MASK = 0x13040019ull;
+
+static const uint64_t P9N2_EQ_4_LOCAL_XSTOP_MASK = 0x14040019ull;
+
+static const uint64_t P9N2_EQ_5_LOCAL_XSTOP_MASK = 0x15040019ull;
+
+static const uint64_t P9N2_EX_LOCAL_XSTOP_MASK = 0x20040019ull;
+//DUPS: 21040019,
+static const uint64_t P9N2_EX_0_LOCAL_XSTOP_MASK = 0x20040019ull;
+//DUPS: 21040019,
+static const uint64_t P9N2_EX_1_LOCAL_XSTOP_MASK = 0x22040019ull;
+//DUPS: 23040019,
+static const uint64_t P9N2_EX_2_LOCAL_XSTOP_MASK = 0x24040019ull;
+//DUPS: 25040019,
+static const uint64_t P9N2_EX_3_LOCAL_XSTOP_MASK = 0x26040019ull;
+//DUPS: 27040019,
+static const uint64_t P9N2_EX_4_LOCAL_XSTOP_MASK = 0x28040019ull;
+//DUPS: 29040019,
+static const uint64_t P9N2_EX_5_LOCAL_XSTOP_MASK = 0x2A040019ull;
+//DUPS: 2B040019,
+static const uint64_t P9N2_EX_6_LOCAL_XSTOP_MASK = 0x2C040019ull;
+//DUPS: 2D040019,
+static const uint64_t P9N2_EX_7_LOCAL_XSTOP_MASK = 0x2F040019ull;
+//DUPS: 2F040019,
+static const uint64_t P9N2_EX_8_LOCAL_XSTOP_MASK = 0x30040019ull;
+//DUPS: 31040019,
+static const uint64_t P9N2_EX_9_LOCAL_XSTOP_MASK = 0x32040019ull;
+//DUPS: 33040019,
+static const uint64_t P9N2_EX_10_LOCAL_XSTOP_MASK = 0x34040019ull;
+//DUPS: 35040019,
+static const uint64_t P9N2_EX_11_LOCAL_XSTOP_MASK = 0x36040019ull;
+//DUPS: 37040019,
+
+static const uint64_t P9N2_EQ_LRU_VIC_ALLOC_REG = 0x10011C11ull;
+//DUPS: 10011C11,
+static const uint64_t P9N2_EQ_0_LRU_VIC_ALLOC_REG = 0x10011C11ull;
+//DUPS: 10011C11,
+static const uint64_t P9N2_EQ_1_LRU_VIC_ALLOC_REG = 0x11011C11ull;
+//DUPS: 11011C11,
+static const uint64_t P9N2_EQ_2_LRU_VIC_ALLOC_REG = 0x12011C11ull;
+//DUPS: 12011C11,
+static const uint64_t P9N2_EQ_3_LRU_VIC_ALLOC_REG = 0x13011C11ull;
+//DUPS: 13011C11,
+static const uint64_t P9N2_EQ_4_LRU_VIC_ALLOC_REG = 0x14011C11ull;
+//DUPS: 14011C11,
+static const uint64_t P9N2_EQ_5_LRU_VIC_ALLOC_REG = 0x15011C11ull;
+//DUPS: 15011C11,
+static const uint64_t P9N2_EX_0_L3_LRU_VIC_ALLOC_REG = 0x10011811ull;
+
+static const uint64_t P9N2_EX_10_L3_LRU_VIC_ALLOC_REG = 0x15011811ull;
+
+static const uint64_t P9N2_EX_11_L3_LRU_VIC_ALLOC_REG = 0x15011C11ull;
+
+static const uint64_t P9N2_EX_1_L3_LRU_VIC_ALLOC_REG = 0x10011C11ull;
+
+static const uint64_t P9N2_EX_2_L3_LRU_VIC_ALLOC_REG = 0x11011811ull;
+
+static const uint64_t P9N2_EX_3_L3_LRU_VIC_ALLOC_REG = 0x11011C11ull;
+
+static const uint64_t P9N2_EX_4_L3_LRU_VIC_ALLOC_REG = 0x12011811ull;
+
+static const uint64_t P9N2_EX_5_L3_LRU_VIC_ALLOC_REG = 0x12011C11ull;
+
+static const uint64_t P9N2_EX_6_L3_LRU_VIC_ALLOC_REG = 0x13011811ull;
+
+static const uint64_t P9N2_EX_7_L3_LRU_VIC_ALLOC_REG = 0x13011C11ull;
+
+static const uint64_t P9N2_EX_8_L3_LRU_VIC_ALLOC_REG = 0x14011811ull;
+
+static const uint64_t P9N2_EX_9_L3_LRU_VIC_ALLOC_REG = 0x14011C11ull;
+
+static const uint64_t P9N2_EX_L3_LRU_VIC_ALLOC_REG = 0x10011811ull;
+
+
+static const uint64_t P9N2_C_LSU_HOLD_OUT_REG0 = 0x20010C80ull;
+
+static const uint64_t P9N2_C_0_LSU_HOLD_OUT_REG0 = 0x20010C80ull;
+
+static const uint64_t P9N2_C_1_LSU_HOLD_OUT_REG0 = 0x21010C80ull;
+
+static const uint64_t P9N2_C_2_LSU_HOLD_OUT_REG0 = 0x22010C80ull;
+
+static const uint64_t P9N2_C_3_LSU_HOLD_OUT_REG0 = 0x23010C80ull;
+
+static const uint64_t P9N2_C_4_LSU_HOLD_OUT_REG0 = 0x24010C80ull;
+
+static const uint64_t P9N2_C_5_LSU_HOLD_OUT_REG0 = 0x25010C80ull;
+
+static const uint64_t P9N2_C_6_LSU_HOLD_OUT_REG0 = 0x26010C80ull;
+
+static const uint64_t P9N2_C_7_LSU_HOLD_OUT_REG0 = 0x27010C80ull;
+
+static const uint64_t P9N2_C_8_LSU_HOLD_OUT_REG0 = 0x28010C80ull;
+
+static const uint64_t P9N2_C_9_LSU_HOLD_OUT_REG0 = 0x29010C80ull;
+
+static const uint64_t P9N2_C_10_LSU_HOLD_OUT_REG0 = 0x2A010C80ull;
+
+static const uint64_t P9N2_C_11_LSU_HOLD_OUT_REG0 = 0x2B010C80ull;
+
+static const uint64_t P9N2_C_12_LSU_HOLD_OUT_REG0 = 0x2C010C80ull;
+
+static const uint64_t P9N2_C_13_LSU_HOLD_OUT_REG0 = 0x2D010C80ull;
+
+static const uint64_t P9N2_C_14_LSU_HOLD_OUT_REG0 = 0x2E010C80ull;
+
+static const uint64_t P9N2_C_15_LSU_HOLD_OUT_REG0 = 0x2F010C80ull;
+
+static const uint64_t P9N2_C_16_LSU_HOLD_OUT_REG0 = 0x30010C80ull;
+
+static const uint64_t P9N2_C_17_LSU_HOLD_OUT_REG0 = 0x31010C80ull;
+
+static const uint64_t P9N2_C_18_LSU_HOLD_OUT_REG0 = 0x32010C80ull;
+
+static const uint64_t P9N2_C_19_LSU_HOLD_OUT_REG0 = 0x33010C80ull;
+
+static const uint64_t P9N2_C_20_LSU_HOLD_OUT_REG0 = 0x34010C80ull;
+
+static const uint64_t P9N2_C_21_LSU_HOLD_OUT_REG0 = 0x35010C80ull;
+
+static const uint64_t P9N2_C_22_LSU_HOLD_OUT_REG0 = 0x36010C80ull;
+
+static const uint64_t P9N2_C_23_LSU_HOLD_OUT_REG0 = 0x37010C80ull;
+
+static const uint64_t P9N2_EX_0_L2_LSU_HOLD_OUT_REG0 = 0x20010C80ull;
+//DUPS: 21010C80,
+static const uint64_t P9N2_EX_10_L2_LSU_HOLD_OUT_REG0 = 0x34010C80ull;
+//DUPS: 35010C80,
+static const uint64_t P9N2_EX_11_L2_LSU_HOLD_OUT_REG0 = 0x36010C80ull;
+//DUPS: 37010C80,
+static const uint64_t P9N2_EX_1_L2_LSU_HOLD_OUT_REG0 = 0x22010C80ull;
+//DUPS: 23010C80,
+static const uint64_t P9N2_EX_2_L2_LSU_HOLD_OUT_REG0 = 0x24010C80ull;
+//DUPS: 25010C80,
+static const uint64_t P9N2_EX_3_L2_LSU_HOLD_OUT_REG0 = 0x26010C80ull;
+//DUPS: 27010C80,
+static const uint64_t P9N2_EX_4_L2_LSU_HOLD_OUT_REG0 = 0x28010C80ull;
+//DUPS: 29010C80,
+static const uint64_t P9N2_EX_5_L2_LSU_HOLD_OUT_REG0 = 0x2A010C80ull;
+//DUPS: 2B010C80,
+static const uint64_t P9N2_EX_6_L2_LSU_HOLD_OUT_REG0 = 0x2C010C80ull;
+//DUPS: 2D010C80,
+static const uint64_t P9N2_EX_7_L2_LSU_HOLD_OUT_REG0 = 0x2F010C80ull;
+//DUPS: 2F010C80,
+static const uint64_t P9N2_EX_8_L2_LSU_HOLD_OUT_REG0 = 0x30010C80ull;
+//DUPS: 31010C80,
+static const uint64_t P9N2_EX_9_L2_LSU_HOLD_OUT_REG0 = 0x32010C80ull;
+//DUPS: 33010C80,
+static const uint64_t P9N2_EX_L2_LSU_HOLD_OUT_REG0 = 0x20010C80ull;
+//DUPS: 21010C80,
+
+static const uint64_t P9N2_C_LSU_HOLD_OUT_REG1 = 0x20010C81ull;
+
+static const uint64_t P9N2_C_0_LSU_HOLD_OUT_REG1 = 0x20010C81ull;
+
+static const uint64_t P9N2_C_1_LSU_HOLD_OUT_REG1 = 0x21010C81ull;
+
+static const uint64_t P9N2_C_2_LSU_HOLD_OUT_REG1 = 0x22010C81ull;
+
+static const uint64_t P9N2_C_3_LSU_HOLD_OUT_REG1 = 0x23010C81ull;
+
+static const uint64_t P9N2_C_4_LSU_HOLD_OUT_REG1 = 0x24010C81ull;
+
+static const uint64_t P9N2_C_5_LSU_HOLD_OUT_REG1 = 0x25010C81ull;
+
+static const uint64_t P9N2_C_6_LSU_HOLD_OUT_REG1 = 0x26010C81ull;
+
+static const uint64_t P9N2_C_7_LSU_HOLD_OUT_REG1 = 0x27010C81ull;
+
+static const uint64_t P9N2_C_8_LSU_HOLD_OUT_REG1 = 0x28010C81ull;
+
+static const uint64_t P9N2_C_9_LSU_HOLD_OUT_REG1 = 0x29010C81ull;
+
+static const uint64_t P9N2_C_10_LSU_HOLD_OUT_REG1 = 0x2A010C81ull;
+
+static const uint64_t P9N2_C_11_LSU_HOLD_OUT_REG1 = 0x2B010C81ull;
+
+static const uint64_t P9N2_C_12_LSU_HOLD_OUT_REG1 = 0x2C010C81ull;
+
+static const uint64_t P9N2_C_13_LSU_HOLD_OUT_REG1 = 0x2D010C81ull;
+
+static const uint64_t P9N2_C_14_LSU_HOLD_OUT_REG1 = 0x2E010C81ull;
+
+static const uint64_t P9N2_C_15_LSU_HOLD_OUT_REG1 = 0x2F010C81ull;
+
+static const uint64_t P9N2_C_16_LSU_HOLD_OUT_REG1 = 0x30010C81ull;
+
+static const uint64_t P9N2_C_17_LSU_HOLD_OUT_REG1 = 0x31010C81ull;
+
+static const uint64_t P9N2_C_18_LSU_HOLD_OUT_REG1 = 0x32010C81ull;
+
+static const uint64_t P9N2_C_19_LSU_HOLD_OUT_REG1 = 0x33010C81ull;
+
+static const uint64_t P9N2_C_20_LSU_HOLD_OUT_REG1 = 0x34010C81ull;
+
+static const uint64_t P9N2_C_21_LSU_HOLD_OUT_REG1 = 0x35010C81ull;
+
+static const uint64_t P9N2_C_22_LSU_HOLD_OUT_REG1 = 0x36010C81ull;
+
+static const uint64_t P9N2_C_23_LSU_HOLD_OUT_REG1 = 0x37010C81ull;
+
+static const uint64_t P9N2_EX_0_L2_LSU_HOLD_OUT_REG1 = 0x20010C81ull;
+//DUPS: 21010C81,
+static const uint64_t P9N2_EX_10_L2_LSU_HOLD_OUT_REG1 = 0x34010C81ull;
+//DUPS: 35010C81,
+static const uint64_t P9N2_EX_11_L2_LSU_HOLD_OUT_REG1 = 0x36010C81ull;
+//DUPS: 37010C81,
+static const uint64_t P9N2_EX_1_L2_LSU_HOLD_OUT_REG1 = 0x22010C81ull;
+//DUPS: 23010C81,
+static const uint64_t P9N2_EX_2_L2_LSU_HOLD_OUT_REG1 = 0x24010C81ull;
+//DUPS: 25010C81,
+static const uint64_t P9N2_EX_3_L2_LSU_HOLD_OUT_REG1 = 0x26010C81ull;
+//DUPS: 27010C81,
+static const uint64_t P9N2_EX_4_L2_LSU_HOLD_OUT_REG1 = 0x28010C81ull;
+//DUPS: 29010C81,
+static const uint64_t P9N2_EX_5_L2_LSU_HOLD_OUT_REG1 = 0x2A010C81ull;
+//DUPS: 2B010C81,
+static const uint64_t P9N2_EX_6_L2_LSU_HOLD_OUT_REG1 = 0x2C010C81ull;
+//DUPS: 2D010C81,
+static const uint64_t P9N2_EX_7_L2_LSU_HOLD_OUT_REG1 = 0x2F010C81ull;
+//DUPS: 2F010C81,
+static const uint64_t P9N2_EX_8_L2_LSU_HOLD_OUT_REG1 = 0x30010C81ull;
+//DUPS: 31010C81,
+static const uint64_t P9N2_EX_9_L2_LSU_HOLD_OUT_REG1 = 0x32010C81ull;
+//DUPS: 33010C81,
+static const uint64_t P9N2_EX_L2_LSU_HOLD_OUT_REG1 = 0x20010C81ull;
+//DUPS: 21010C81,
+
+static const uint64_t P9N2_C_LSU_HOLD_OUT_REG2 = 0x20010C82ull;
+
+static const uint64_t P9N2_C_0_LSU_HOLD_OUT_REG2 = 0x20010C82ull;
+
+static const uint64_t P9N2_C_1_LSU_HOLD_OUT_REG2 = 0x21010C82ull;
+
+static const uint64_t P9N2_C_2_LSU_HOLD_OUT_REG2 = 0x22010C82ull;
+
+static const uint64_t P9N2_C_3_LSU_HOLD_OUT_REG2 = 0x23010C82ull;
+
+static const uint64_t P9N2_C_4_LSU_HOLD_OUT_REG2 = 0x24010C82ull;
+
+static const uint64_t P9N2_C_5_LSU_HOLD_OUT_REG2 = 0x25010C82ull;
+
+static const uint64_t P9N2_C_6_LSU_HOLD_OUT_REG2 = 0x26010C82ull;
+
+static const uint64_t P9N2_C_7_LSU_HOLD_OUT_REG2 = 0x27010C82ull;
+
+static const uint64_t P9N2_C_8_LSU_HOLD_OUT_REG2 = 0x28010C82ull;
+
+static const uint64_t P9N2_C_9_LSU_HOLD_OUT_REG2 = 0x29010C82ull;
+
+static const uint64_t P9N2_C_10_LSU_HOLD_OUT_REG2 = 0x2A010C82ull;
+
+static const uint64_t P9N2_C_11_LSU_HOLD_OUT_REG2 = 0x2B010C82ull;
+
+static const uint64_t P9N2_C_12_LSU_HOLD_OUT_REG2 = 0x2C010C82ull;
+
+static const uint64_t P9N2_C_13_LSU_HOLD_OUT_REG2 = 0x2D010C82ull;
+
+static const uint64_t P9N2_C_14_LSU_HOLD_OUT_REG2 = 0x2E010C82ull;
+
+static const uint64_t P9N2_C_15_LSU_HOLD_OUT_REG2 = 0x2F010C82ull;
+
+static const uint64_t P9N2_C_16_LSU_HOLD_OUT_REG2 = 0x30010C82ull;
+
+static const uint64_t P9N2_C_17_LSU_HOLD_OUT_REG2 = 0x31010C82ull;
+
+static const uint64_t P9N2_C_18_LSU_HOLD_OUT_REG2 = 0x32010C82ull;
+
+static const uint64_t P9N2_C_19_LSU_HOLD_OUT_REG2 = 0x33010C82ull;
+
+static const uint64_t P9N2_C_20_LSU_HOLD_OUT_REG2 = 0x34010C82ull;
+
+static const uint64_t P9N2_C_21_LSU_HOLD_OUT_REG2 = 0x35010C82ull;
+
+static const uint64_t P9N2_C_22_LSU_HOLD_OUT_REG2 = 0x36010C82ull;
+
+static const uint64_t P9N2_C_23_LSU_HOLD_OUT_REG2 = 0x37010C82ull;
+
+static const uint64_t P9N2_EX_0_L2_LSU_HOLD_OUT_REG2 = 0x20010C82ull;
+//DUPS: 21010C82,
+static const uint64_t P9N2_EX_10_L2_LSU_HOLD_OUT_REG2 = 0x34010C82ull;
+//DUPS: 35010C82,
+static const uint64_t P9N2_EX_11_L2_LSU_HOLD_OUT_REG2 = 0x36010C82ull;
+//DUPS: 37010C82,
+static const uint64_t P9N2_EX_1_L2_LSU_HOLD_OUT_REG2 = 0x22010C82ull;
+//DUPS: 23010C82,
+static const uint64_t P9N2_EX_2_L2_LSU_HOLD_OUT_REG2 = 0x24010C82ull;
+//DUPS: 25010C82,
+static const uint64_t P9N2_EX_3_L2_LSU_HOLD_OUT_REG2 = 0x26010C82ull;
+//DUPS: 27010C82,
+static const uint64_t P9N2_EX_4_L2_LSU_HOLD_OUT_REG2 = 0x28010C82ull;
+//DUPS: 29010C82,
+static const uint64_t P9N2_EX_5_L2_LSU_HOLD_OUT_REG2 = 0x2A010C82ull;
+//DUPS: 2B010C82,
+static const uint64_t P9N2_EX_6_L2_LSU_HOLD_OUT_REG2 = 0x2C010C82ull;
+//DUPS: 2D010C82,
+static const uint64_t P9N2_EX_7_L2_LSU_HOLD_OUT_REG2 = 0x2F010C82ull;
+//DUPS: 2F010C82,
+static const uint64_t P9N2_EX_8_L2_LSU_HOLD_OUT_REG2 = 0x30010C82ull;
+//DUPS: 31010C82,
+static const uint64_t P9N2_EX_9_L2_LSU_HOLD_OUT_REG2 = 0x32010C82ull;
+//DUPS: 33010C82,
+static const uint64_t P9N2_EX_L2_LSU_HOLD_OUT_REG2 = 0x20010C82ull;
+//DUPS: 21010C82,
+
+static const uint64_t P9N2_C_LSU_HOLD_OUT_REG3 = 0x20010C83ull;
+
+static const uint64_t P9N2_C_0_LSU_HOLD_OUT_REG3 = 0x20010C83ull;
+
+static const uint64_t P9N2_C_1_LSU_HOLD_OUT_REG3 = 0x21010C83ull;
+
+static const uint64_t P9N2_C_2_LSU_HOLD_OUT_REG3 = 0x22010C83ull;
+
+static const uint64_t P9N2_C_3_LSU_HOLD_OUT_REG3 = 0x23010C83ull;
+
+static const uint64_t P9N2_C_4_LSU_HOLD_OUT_REG3 = 0x24010C83ull;
+
+static const uint64_t P9N2_C_5_LSU_HOLD_OUT_REG3 = 0x25010C83ull;
+
+static const uint64_t P9N2_C_6_LSU_HOLD_OUT_REG3 = 0x26010C83ull;
+
+static const uint64_t P9N2_C_7_LSU_HOLD_OUT_REG3 = 0x27010C83ull;
+
+static const uint64_t P9N2_C_8_LSU_HOLD_OUT_REG3 = 0x28010C83ull;
+
+static const uint64_t P9N2_C_9_LSU_HOLD_OUT_REG3 = 0x29010C83ull;
+
+static const uint64_t P9N2_C_10_LSU_HOLD_OUT_REG3 = 0x2A010C83ull;
+
+static const uint64_t P9N2_C_11_LSU_HOLD_OUT_REG3 = 0x2B010C83ull;
+
+static const uint64_t P9N2_C_12_LSU_HOLD_OUT_REG3 = 0x2C010C83ull;
+
+static const uint64_t P9N2_C_13_LSU_HOLD_OUT_REG3 = 0x2D010C83ull;
+
+static const uint64_t P9N2_C_14_LSU_HOLD_OUT_REG3 = 0x2E010C83ull;
+
+static const uint64_t P9N2_C_15_LSU_HOLD_OUT_REG3 = 0x2F010C83ull;
+
+static const uint64_t P9N2_C_16_LSU_HOLD_OUT_REG3 = 0x30010C83ull;
+
+static const uint64_t P9N2_C_17_LSU_HOLD_OUT_REG3 = 0x31010C83ull;
+
+static const uint64_t P9N2_C_18_LSU_HOLD_OUT_REG3 = 0x32010C83ull;
+
+static const uint64_t P9N2_C_19_LSU_HOLD_OUT_REG3 = 0x33010C83ull;
+
+static const uint64_t P9N2_C_20_LSU_HOLD_OUT_REG3 = 0x34010C83ull;
+
+static const uint64_t P9N2_C_21_LSU_HOLD_OUT_REG3 = 0x35010C83ull;
+
+static const uint64_t P9N2_C_22_LSU_HOLD_OUT_REG3 = 0x36010C83ull;
+
+static const uint64_t P9N2_C_23_LSU_HOLD_OUT_REG3 = 0x37010C83ull;
+
+static const uint64_t P9N2_EX_0_L2_LSU_HOLD_OUT_REG3 = 0x20010C83ull;
+//DUPS: 21010C83,
+static const uint64_t P9N2_EX_10_L2_LSU_HOLD_OUT_REG3 = 0x34010C83ull;
+//DUPS: 35010C83,
+static const uint64_t P9N2_EX_11_L2_LSU_HOLD_OUT_REG3 = 0x36010C83ull;
+//DUPS: 37010C83,
+static const uint64_t P9N2_EX_1_L2_LSU_HOLD_OUT_REG3 = 0x22010C83ull;
+//DUPS: 23010C83,
+static const uint64_t P9N2_EX_2_L2_LSU_HOLD_OUT_REG3 = 0x24010C83ull;
+//DUPS: 25010C83,
+static const uint64_t P9N2_EX_3_L2_LSU_HOLD_OUT_REG3 = 0x26010C83ull;
+//DUPS: 27010C83,
+static const uint64_t P9N2_EX_4_L2_LSU_HOLD_OUT_REG3 = 0x28010C83ull;
+//DUPS: 29010C83,
+static const uint64_t P9N2_EX_5_L2_LSU_HOLD_OUT_REG3 = 0x2A010C83ull;
+//DUPS: 2B010C83,
+static const uint64_t P9N2_EX_6_L2_LSU_HOLD_OUT_REG3 = 0x2C010C83ull;
+//DUPS: 2D010C83,
+static const uint64_t P9N2_EX_7_L2_LSU_HOLD_OUT_REG3 = 0x2F010C83ull;
+//DUPS: 2F010C83,
+static const uint64_t P9N2_EX_8_L2_LSU_HOLD_OUT_REG3 = 0x30010C83ull;
+//DUPS: 31010C83,
+static const uint64_t P9N2_EX_9_L2_LSU_HOLD_OUT_REG3 = 0x32010C83ull;
+//DUPS: 33010C83,
+static const uint64_t P9N2_EX_L2_LSU_HOLD_OUT_REG3 = 0x20010C83ull;
+//DUPS: 21010C83,
+
+static const uint64_t P9N2_EQ_MEM_OP_CTR = 0x10012208ull;
+//DUPS: 10012708, 10012208, 10012308,
+static const uint64_t P9N2_EQ_0_MEM_OP_CTR = 0x10012208ull;
+//DUPS: 10012708, 10012208, 10012308,
+static const uint64_t P9N2_EQ_1_MEM_OP_CTR = 0x11012208ull;
+//DUPS: 11012708, 11012208, 11012308,
+static const uint64_t P9N2_EQ_2_MEM_OP_CTR = 0x12012208ull;
+//DUPS: 12012708, 12012208, 12012308,
+static const uint64_t P9N2_EQ_3_MEM_OP_CTR = 0x13012208ull;
+//DUPS: 13012708, 13012208, 13012308,
+static const uint64_t P9N2_EQ_4_MEM_OP_CTR = 0x14012208ull;
+//DUPS: 14012708, 14012208, 14012308,
+static const uint64_t P9N2_EQ_5_MEM_OP_CTR = 0x15012208ull;
+//DUPS: 15012708, 15012208, 15012308,
+static const uint64_t P9N2_EX_MEM_OP_CTR = 0x10012208ull;
+//DUPS: 10012308,
+static const uint64_t P9N2_EX_0_MEM_OP_CTR = 0x10012208ull;
+//DUPS: 10012308,
+static const uint64_t P9N2_EX_2_MEM_OP_CTR = 0x11012208ull;
+//DUPS: 11012308,
+static const uint64_t P9N2_EX_4_MEM_OP_CTR = 0x12012208ull;
+//DUPS: 12012308,
+static const uint64_t P9N2_EX_6_MEM_OP_CTR = 0x13012208ull;
+//DUPS: 13012308,
+static const uint64_t P9N2_EX_8_MEM_OP_CTR = 0x14012208ull;
+//DUPS: 14012308,
+static const uint64_t P9N2_EX_10_MEM_OP_CTR = 0x15012208ull;
+//DUPS: 15012308,
+static const uint64_t P9N2_EX_11_CHTMLBS0_MEM_OP_CTR = 0x15012608ull;
+
+static const uint64_t P9N2_EX_11_CHTMLBS1_MEM_OP_CTR = 0x15012708ull;
+
+static const uint64_t P9N2_EX_1_CHTMLBS0_MEM_OP_CTR = 0x10012608ull;
+
+static const uint64_t P9N2_EX_1_CHTMLBS1_MEM_OP_CTR = 0x10012708ull;
+
+static const uint64_t P9N2_EX_3_CHTMLBS0_MEM_OP_CTR = 0x11012608ull;
+
+static const uint64_t P9N2_EX_3_CHTMLBS1_MEM_OP_CTR = 0x11012708ull;
+
+static const uint64_t P9N2_EX_5_CHTMLBS0_MEM_OP_CTR = 0x12012608ull;
+
+static const uint64_t P9N2_EX_5_CHTMLBS1_MEM_OP_CTR = 0x12012708ull;
+
+static const uint64_t P9N2_EX_7_CHTMLBS0_MEM_OP_CTR = 0x13012608ull;
+
+static const uint64_t P9N2_EX_7_CHTMLBS1_MEM_OP_CTR = 0x13012708ull;
+
+static const uint64_t P9N2_EX_9_CHTMLBS0_MEM_OP_CTR = 0x14012608ull;
+
+static const uint64_t P9N2_EX_9_CHTMLBS1_MEM_OP_CTR = 0x14012708ull;
+
+
+static const uint64_t P9N2_EQ_MIB_XIICAC = 0x10012019ull;
+//DUPS: 10012019,
+static const uint64_t P9N2_EQ_0_MIB_XIICAC = 0x10012019ull;
+//DUPS: 10012019,
+static const uint64_t P9N2_EQ_1_MIB_XIICAC = 0x11012019ull;
+//DUPS: 11012019,
+static const uint64_t P9N2_EQ_2_MIB_XIICAC = 0x12012019ull;
+//DUPS: 12012019,
+static const uint64_t P9N2_EQ_3_MIB_XIICAC = 0x13012019ull;
+//DUPS: 13012019,
+static const uint64_t P9N2_EQ_4_MIB_XIICAC = 0x14012019ull;
+//DUPS: 14012019,
+static const uint64_t P9N2_EQ_5_MIB_XIICAC = 0x15012019ull;
+//DUPS: 15012019,
+static const uint64_t P9N2_EX_MIB_XIICAC = 0x10012019ull;
+
+static const uint64_t P9N2_EX_0_MIB_XIICAC = 0x10012019ull;
+
+static const uint64_t P9N2_EX_1_MIB_XIICAC = 0x10012419ull;
+
+static const uint64_t P9N2_EX_2_MIB_XIICAC = 0x11012019ull;
+
+static const uint64_t P9N2_EX_3_MIB_XIICAC = 0x11012419ull;
+
+static const uint64_t P9N2_EX_4_MIB_XIICAC = 0x12012019ull;
+
+static const uint64_t P9N2_EX_5_MIB_XIICAC = 0x12012419ull;
+
+static const uint64_t P9N2_EX_6_MIB_XIICAC = 0x13012019ull;
+
+static const uint64_t P9N2_EX_7_MIB_XIICAC = 0x13012419ull;
+
+static const uint64_t P9N2_EX_8_MIB_XIICAC = 0x14012019ull;
+
+static const uint64_t P9N2_EX_9_MIB_XIICAC = 0x14012419ull;
+
+static const uint64_t P9N2_EX_10_MIB_XIICAC = 0x15012019ull;
+
+static const uint64_t P9N2_EX_11_MIB_XIICAC = 0x15012419ull;
+
+
+static const uint64_t P9N2_EQ_MIB_XIMEM = 0x10012017ull;
+//DUPS: 10012017,
+static const uint64_t P9N2_EQ_0_MIB_XIMEM = 0x10012017ull;
+//DUPS: 10012017,
+static const uint64_t P9N2_EQ_1_MIB_XIMEM = 0x11012017ull;
+//DUPS: 11012017,
+static const uint64_t P9N2_EQ_2_MIB_XIMEM = 0x12012017ull;
+//DUPS: 12012017,
+static const uint64_t P9N2_EQ_3_MIB_XIMEM = 0x13012017ull;
+//DUPS: 13012017,
+static const uint64_t P9N2_EQ_4_MIB_XIMEM = 0x14012017ull;
+//DUPS: 14012017,
+static const uint64_t P9N2_EQ_5_MIB_XIMEM = 0x15012017ull;
+//DUPS: 15012017,
+static const uint64_t P9N2_EX_MIB_XIMEM = 0x10012017ull;
+
+static const uint64_t P9N2_EX_0_MIB_XIMEM = 0x10012017ull;
+
+static const uint64_t P9N2_EX_1_MIB_XIMEM = 0x10012417ull;
+
+static const uint64_t P9N2_EX_2_MIB_XIMEM = 0x11012017ull;
+
+static const uint64_t P9N2_EX_3_MIB_XIMEM = 0x11012417ull;
+
+static const uint64_t P9N2_EX_4_MIB_XIMEM = 0x12012017ull;
+
+static const uint64_t P9N2_EX_5_MIB_XIMEM = 0x12012417ull;
+
+static const uint64_t P9N2_EX_6_MIB_XIMEM = 0x13012017ull;
+
+static const uint64_t P9N2_EX_7_MIB_XIMEM = 0x13012417ull;
+
+static const uint64_t P9N2_EX_8_MIB_XIMEM = 0x14012017ull;
+
+static const uint64_t P9N2_EX_9_MIB_XIMEM = 0x14012417ull;
+
+static const uint64_t P9N2_EX_10_MIB_XIMEM = 0x15012017ull;
+
+static const uint64_t P9N2_EX_11_MIB_XIMEM = 0x15012417ull;
+
+
+static const uint64_t P9N2_EQ_MIB_XISGB = 0x10012018ull;
+//DUPS: 10012018,
+static const uint64_t P9N2_EQ_0_MIB_XISGB = 0x10012018ull;
+//DUPS: 10012018,
+static const uint64_t P9N2_EQ_1_MIB_XISGB = 0x11012018ull;
+//DUPS: 11012018,
+static const uint64_t P9N2_EQ_2_MIB_XISGB = 0x12012018ull;
+//DUPS: 12012018,
+static const uint64_t P9N2_EQ_3_MIB_XISGB = 0x13012018ull;
+//DUPS: 13012018,
+static const uint64_t P9N2_EQ_4_MIB_XISGB = 0x14012018ull;
+//DUPS: 14012018,
+static const uint64_t P9N2_EQ_5_MIB_XISGB = 0x15012018ull;
+//DUPS: 15012018,
+static const uint64_t P9N2_EX_MIB_XISGB = 0x10012018ull;
+
+static const uint64_t P9N2_EX_0_MIB_XISGB = 0x10012018ull;
+
+static const uint64_t P9N2_EX_1_MIB_XISGB = 0x10012418ull;
+
+static const uint64_t P9N2_EX_2_MIB_XISGB = 0x11012018ull;
+
+static const uint64_t P9N2_EX_3_MIB_XISGB = 0x11012418ull;
+
+static const uint64_t P9N2_EX_4_MIB_XISGB = 0x12012018ull;
+
+static const uint64_t P9N2_EX_5_MIB_XISGB = 0x12012418ull;
+
+static const uint64_t P9N2_EX_6_MIB_XISGB = 0x13012018ull;
+
+static const uint64_t P9N2_EX_7_MIB_XISGB = 0x13012418ull;
+
+static const uint64_t P9N2_EX_8_MIB_XISGB = 0x14012018ull;
+
+static const uint64_t P9N2_EX_9_MIB_XISGB = 0x14012418ull;
+
+static const uint64_t P9N2_EX_10_MIB_XISGB = 0x15012018ull;
+
+static const uint64_t P9N2_EX_11_MIB_XISGB = 0x15012418ull;
+
+
+static const uint64_t P9N2_C_MODE_REG = 0x20040008ull;
+
+static const uint64_t P9N2_C_0_MODE_REG = 0x20040008ull;
+
+static const uint64_t P9N2_C_1_MODE_REG = 0x21040008ull;
+
+static const uint64_t P9N2_C_2_MODE_REG = 0x22040008ull;
+
+static const uint64_t P9N2_C_3_MODE_REG = 0x23040008ull;
+
+static const uint64_t P9N2_C_4_MODE_REG = 0x24040008ull;
+
+static const uint64_t P9N2_C_5_MODE_REG = 0x25040008ull;
+
+static const uint64_t P9N2_C_6_MODE_REG = 0x26040008ull;
+
+static const uint64_t P9N2_C_7_MODE_REG = 0x27040008ull;
+
+static const uint64_t P9N2_C_8_MODE_REG = 0x28040008ull;
+
+static const uint64_t P9N2_C_9_MODE_REG = 0x29040008ull;
+
+static const uint64_t P9N2_C_10_MODE_REG = 0x2A040008ull;
+
+static const uint64_t P9N2_C_11_MODE_REG = 0x2B040008ull;
+
+static const uint64_t P9N2_C_12_MODE_REG = 0x2C040008ull;
+
+static const uint64_t P9N2_C_13_MODE_REG = 0x2D040008ull;
+
+static const uint64_t P9N2_C_14_MODE_REG = 0x2E040008ull;
+
+static const uint64_t P9N2_C_15_MODE_REG = 0x2F040008ull;
+
+static const uint64_t P9N2_C_16_MODE_REG = 0x30040008ull;
+
+static const uint64_t P9N2_C_17_MODE_REG = 0x31040008ull;
+
+static const uint64_t P9N2_C_18_MODE_REG = 0x32040008ull;
+
+static const uint64_t P9N2_C_19_MODE_REG = 0x33040008ull;
+
+static const uint64_t P9N2_C_20_MODE_REG = 0x34040008ull;
+
+static const uint64_t P9N2_C_21_MODE_REG = 0x35040008ull;
+
+static const uint64_t P9N2_C_22_MODE_REG = 0x36040008ull;
+
+static const uint64_t P9N2_C_23_MODE_REG = 0x37040008ull;
+
+static const uint64_t P9N2_EQ_MODE_REG = 0x10040008ull;
+
+static const uint64_t P9N2_EQ_0_MODE_REG = 0x10040008ull;
+
+static const uint64_t P9N2_EQ_1_MODE_REG = 0x11040008ull;
+
+static const uint64_t P9N2_EQ_2_MODE_REG = 0x12040008ull;
+
+static const uint64_t P9N2_EQ_3_MODE_REG = 0x13040008ull;
+
+static const uint64_t P9N2_EQ_4_MODE_REG = 0x14040008ull;
+
+static const uint64_t P9N2_EQ_5_MODE_REG = 0x15040008ull;
+
+static const uint64_t P9N2_EX_MODE_REG = 0x20040008ull;
+//DUPS: 21040008,
+static const uint64_t P9N2_EX_0_MODE_REG = 0x20040008ull;
+//DUPS: 21040008,
+static const uint64_t P9N2_EX_1_MODE_REG = 0x22040008ull;
+//DUPS: 23040008,
+static const uint64_t P9N2_EX_2_MODE_REG = 0x24040008ull;
+//DUPS: 25040008,
+static const uint64_t P9N2_EX_3_MODE_REG = 0x26040008ull;
+//DUPS: 27040008,
+static const uint64_t P9N2_EX_4_MODE_REG = 0x28040008ull;
+//DUPS: 29040008,
+static const uint64_t P9N2_EX_5_MODE_REG = 0x2A040008ull;
+//DUPS: 2B040008,
+static const uint64_t P9N2_EX_6_MODE_REG = 0x2C040008ull;
+//DUPS: 2D040008,
+static const uint64_t P9N2_EX_7_MODE_REG = 0x2F040008ull;
+//DUPS: 2F040008,
+static const uint64_t P9N2_EX_8_MODE_REG = 0x30040008ull;
+//DUPS: 31040008,
+static const uint64_t P9N2_EX_9_MODE_REG = 0x32040008ull;
+//DUPS: 33040008,
+static const uint64_t P9N2_EX_10_MODE_REG = 0x34040008ull;
+//DUPS: 35040008,
+static const uint64_t P9N2_EX_11_MODE_REG = 0x36040008ull;
+//DUPS: 37040008,
+
+static const uint64_t P9N2_EQ_MODE_REG0 = 0x10010C0Aull;
+//DUPS: 1001182B, 10010C0A, 10011C2B,
+static const uint64_t P9N2_EQ_0_MODE_REG0 = 0x10010C0Aull;
+//DUPS: 1001182B, 10010C0A, 10011C2B,
+static const uint64_t P9N2_EQ_1_MODE_REG0 = 0x11010C0Aull;
+//DUPS: 1101182B, 11010C0A, 11011C2B,
+static const uint64_t P9N2_EQ_2_MODE_REG0 = 0x12010C0Aull;
+//DUPS: 1201182B, 12010C0A, 12011C2B,
+static const uint64_t P9N2_EQ_3_MODE_REG0 = 0x13010C0Aull;
+//DUPS: 1301182B, 13010C0A, 13011C2B,
+static const uint64_t P9N2_EQ_4_MODE_REG0 = 0x14010C0Aull;
+//DUPS: 1401182B, 14010C0A, 14011C2B,
+static const uint64_t P9N2_EQ_5_MODE_REG0 = 0x15010C0Aull;
+//DUPS: 1501182B, 15010C0A, 15011C2B,
+static const uint64_t P9N2_EX_0_L2_MODE_REG0 = 0x1001080Aull;
+
+static const uint64_t P9N2_EX_0_L3_MODE_REG0 = 0x1001182Bull;
+
+static const uint64_t P9N2_EX_10_L2_MODE_REG0 = 0x1501080Aull;
+
+static const uint64_t P9N2_EX_10_L3_MODE_REG0 = 0x1501182Bull;
+
+static const uint64_t P9N2_EX_11_L2_MODE_REG0 = 0x15010C0Aull;
+
+static const uint64_t P9N2_EX_11_L3_MODE_REG0 = 0x15011C2Bull;
+
+static const uint64_t P9N2_EX_1_L2_MODE_REG0 = 0x10010C0Aull;
+
+static const uint64_t P9N2_EX_1_L3_MODE_REG0 = 0x10011C2Bull;
+
+static const uint64_t P9N2_EX_2_L2_MODE_REG0 = 0x1101080Aull;
+
+static const uint64_t P9N2_EX_2_L3_MODE_REG0 = 0x1101182Bull;
+
+static const uint64_t P9N2_EX_3_L2_MODE_REG0 = 0x11010C0Aull;
+
+static const uint64_t P9N2_EX_3_L3_MODE_REG0 = 0x11011C2Bull;
+
+static const uint64_t P9N2_EX_4_L2_MODE_REG0 = 0x1201080Aull;
+
+static const uint64_t P9N2_EX_4_L3_MODE_REG0 = 0x1201182Bull;
+
+static const uint64_t P9N2_EX_5_L2_MODE_REG0 = 0x12010C0Aull;
+
+static const uint64_t P9N2_EX_5_L3_MODE_REG0 = 0x12011C2Bull;
+
+static const uint64_t P9N2_EX_6_L2_MODE_REG0 = 0x1301080Aull;
+
+static const uint64_t P9N2_EX_6_L3_MODE_REG0 = 0x1301182Bull;
+
+static const uint64_t P9N2_EX_7_L2_MODE_REG0 = 0x13010C0Aull;
+
+static const uint64_t P9N2_EX_7_L3_MODE_REG0 = 0x13011C2Bull;
+
+static const uint64_t P9N2_EX_8_L2_MODE_REG0 = 0x1401080Aull;
+
+static const uint64_t P9N2_EX_8_L3_MODE_REG0 = 0x1401182Bull;
+
+static const uint64_t P9N2_EX_9_L2_MODE_REG0 = 0x14010C0Aull;
+
+static const uint64_t P9N2_EX_9_L3_MODE_REG0 = 0x14011C2Bull;
+
+static const uint64_t P9N2_EX_L2_MODE_REG0 = 0x1001080Aull;
+
+static const uint64_t P9N2_EX_L3_MODE_REG0 = 0x1001182Bull;
+
+
+static const uint64_t P9N2_EQ_MODE_REG1 = 0x10010C0Bull;
+//DUPS: 1001180A, 10010C0B, 10011C0A,
+static const uint64_t P9N2_EQ_0_MODE_REG1 = 0x10010C0Bull;
+//DUPS: 1001180A, 10010C0B, 10011C0A,
+static const uint64_t P9N2_EQ_1_MODE_REG1 = 0x11010C0Bull;
+//DUPS: 1101180A, 11010C0B, 11011C0A,
+static const uint64_t P9N2_EQ_2_MODE_REG1 = 0x12010C0Bull;
+//DUPS: 1201180A, 12010C0B, 12011C0A,
+static const uint64_t P9N2_EQ_3_MODE_REG1 = 0x13010C0Bull;
+//DUPS: 1301180A, 13010C0B, 13011C0A,
+static const uint64_t P9N2_EQ_4_MODE_REG1 = 0x14010C0Bull;
+//DUPS: 1401180A, 14010C0B, 14011C0A,
+static const uint64_t P9N2_EQ_5_MODE_REG1 = 0x15010C0Bull;
+//DUPS: 1501180A, 15010C0B, 15011C0A,
+static const uint64_t P9N2_EX_0_L2_MODE_REG1 = 0x1001080Bull;
+
+static const uint64_t P9N2_EX_0_L3_MODE_REG1 = 0x1001180Aull;
+
+static const uint64_t P9N2_EX_10_L2_MODE_REG1 = 0x1501080Bull;
+
+static const uint64_t P9N2_EX_10_L3_MODE_REG1 = 0x1501180Aull;
+
+static const uint64_t P9N2_EX_11_L2_MODE_REG1 = 0x15010C0Bull;
+
+static const uint64_t P9N2_EX_11_L3_MODE_REG1 = 0x15011C0Aull;
+
+static const uint64_t P9N2_EX_1_L2_MODE_REG1 = 0x10010C0Bull;
+
+static const uint64_t P9N2_EX_1_L3_MODE_REG1 = 0x10011C0Aull;
+
+static const uint64_t P9N2_EX_2_L2_MODE_REG1 = 0x1101080Bull;
+
+static const uint64_t P9N2_EX_2_L3_MODE_REG1 = 0x1101180Aull;
+
+static const uint64_t P9N2_EX_3_L2_MODE_REG1 = 0x11010C0Bull;
+
+static const uint64_t P9N2_EX_3_L3_MODE_REG1 = 0x11011C0Aull;
+
+static const uint64_t P9N2_EX_4_L2_MODE_REG1 = 0x1201080Bull;
+
+static const uint64_t P9N2_EX_4_L3_MODE_REG1 = 0x1201180Aull;
+
+static const uint64_t P9N2_EX_5_L2_MODE_REG1 = 0x12010C0Bull;
+
+static const uint64_t P9N2_EX_5_L3_MODE_REG1 = 0x12011C0Aull;
+
+static const uint64_t P9N2_EX_6_L2_MODE_REG1 = 0x1301080Bull;
+
+static const uint64_t P9N2_EX_6_L3_MODE_REG1 = 0x1301180Aull;
+
+static const uint64_t P9N2_EX_7_L2_MODE_REG1 = 0x13010C0Bull;
+
+static const uint64_t P9N2_EX_7_L3_MODE_REG1 = 0x13011C0Aull;
+
+static const uint64_t P9N2_EX_8_L2_MODE_REG1 = 0x1401080Bull;
+
+static const uint64_t P9N2_EX_8_L3_MODE_REG1 = 0x1401180Aull;
+
+static const uint64_t P9N2_EX_9_L2_MODE_REG1 = 0x14010C0Bull;
+
+static const uint64_t P9N2_EX_9_L3_MODE_REG1 = 0x14011C0Aull;
+
+static const uint64_t P9N2_EX_L2_MODE_REG1 = 0x1001080Bull;
+
+static const uint64_t P9N2_EX_L3_MODE_REG1 = 0x1001180Aull;
+
+
+static const uint64_t P9N2_C_MULTICAST_GROUP_1 = 0x200F0001ull;
+
+static const uint64_t P9N2_C_0_MULTICAST_GROUP_1 = 0x200F0001ull;
+
+static const uint64_t P9N2_C_1_MULTICAST_GROUP_1 = 0x210F0001ull;
+
+static const uint64_t P9N2_C_2_MULTICAST_GROUP_1 = 0x220F0001ull;
+
+static const uint64_t P9N2_C_3_MULTICAST_GROUP_1 = 0x230F0001ull;
+
+static const uint64_t P9N2_C_4_MULTICAST_GROUP_1 = 0x240F0001ull;
+
+static const uint64_t P9N2_C_5_MULTICAST_GROUP_1 = 0x250F0001ull;
+
+static const uint64_t P9N2_C_6_MULTICAST_GROUP_1 = 0x260F0001ull;
+
+static const uint64_t P9N2_C_7_MULTICAST_GROUP_1 = 0x270F0001ull;
+
+static const uint64_t P9N2_C_8_MULTICAST_GROUP_1 = 0x280F0001ull;
+
+static const uint64_t P9N2_C_9_MULTICAST_GROUP_1 = 0x290F0001ull;
+
+static const uint64_t P9N2_C_10_MULTICAST_GROUP_1 = 0x2A0F0001ull;
+
+static const uint64_t P9N2_C_11_MULTICAST_GROUP_1 = 0x2B0F0001ull;
+
+static const uint64_t P9N2_C_12_MULTICAST_GROUP_1 = 0x2C0F0001ull;
+
+static const uint64_t P9N2_C_13_MULTICAST_GROUP_1 = 0x2D0F0001ull;
+
+static const uint64_t P9N2_C_14_MULTICAST_GROUP_1 = 0x2E0F0001ull;
+
+static const uint64_t P9N2_C_15_MULTICAST_GROUP_1 = 0x2F0F0001ull;
+
+static const uint64_t P9N2_C_16_MULTICAST_GROUP_1 = 0x300F0001ull;
+
+static const uint64_t P9N2_C_17_MULTICAST_GROUP_1 = 0x310F0001ull;
+
+static const uint64_t P9N2_C_18_MULTICAST_GROUP_1 = 0x320F0001ull;
+
+static const uint64_t P9N2_C_19_MULTICAST_GROUP_1 = 0x330F0001ull;
+
+static const uint64_t P9N2_C_20_MULTICAST_GROUP_1 = 0x340F0001ull;
+
+static const uint64_t P9N2_C_21_MULTICAST_GROUP_1 = 0x350F0001ull;
+
+static const uint64_t P9N2_C_22_MULTICAST_GROUP_1 = 0x360F0001ull;
+
+static const uint64_t P9N2_C_23_MULTICAST_GROUP_1 = 0x370F0001ull;
+
+static const uint64_t P9N2_EQ_MULTICAST_GROUP_1 = 0x100F0001ull;
+
+static const uint64_t P9N2_EQ_0_MULTICAST_GROUP_1 = 0x100F0001ull;
+
+static const uint64_t P9N2_EQ_1_MULTICAST_GROUP_1 = 0x110F0001ull;
+
+static const uint64_t P9N2_EQ_2_MULTICAST_GROUP_1 = 0x120F0001ull;
+
+static const uint64_t P9N2_EQ_3_MULTICAST_GROUP_1 = 0x130F0001ull;
+
+static const uint64_t P9N2_EQ_4_MULTICAST_GROUP_1 = 0x140F0001ull;
+
+static const uint64_t P9N2_EQ_5_MULTICAST_GROUP_1 = 0x150F0001ull;
+
+static const uint64_t P9N2_EX_MULTICAST_GROUP_1 = 0x200F0001ull;
+//DUPS: 210F0001,
+static const uint64_t P9N2_EX_0_MULTICAST_GROUP_1 = 0x200F0001ull;
+//DUPS: 210F0001,
+static const uint64_t P9N2_EX_1_MULTICAST_GROUP_1 = 0x220F0001ull;
+//DUPS: 220F0001,
+static const uint64_t P9N2_EX_2_MULTICAST_GROUP_1 = 0x240F0001ull;
+//DUPS: 250F0001,
+static const uint64_t P9N2_EX_3_MULTICAST_GROUP_1 = 0x260F0001ull;
+//DUPS: 270F0001,
+static const uint64_t P9N2_EX_4_MULTICAST_GROUP_1 = 0x280F0001ull;
+//DUPS: 290F0001,
+static const uint64_t P9N2_EX_5_MULTICAST_GROUP_1 = 0x2A0F0001ull;
+//DUPS: 2B0F0001,
+static const uint64_t P9N2_EX_6_MULTICAST_GROUP_1 = 0x2C0F0001ull;
+//DUPS: 2D0F0001,
+static const uint64_t P9N2_EX_7_MULTICAST_GROUP_1 = 0x2E0F0001ull;
+//DUPS: 2F0F0001,
+static const uint64_t P9N2_EX_8_MULTICAST_GROUP_1 = 0x300F0001ull;
+//DUPS: 310F0001,
+static const uint64_t P9N2_EX_9_MULTICAST_GROUP_1 = 0x320F0001ull;
+//DUPS: 330F0001,
+static const uint64_t P9N2_EX_10_MULTICAST_GROUP_1 = 0x340F0001ull;
+//DUPS: 350F0001,
+static const uint64_t P9N2_EX_11_MULTICAST_GROUP_1 = 0x360F0001ull;
+//DUPS: 370F0001,
+
+static const uint64_t P9N2_C_MULTICAST_GROUP_2 = 0x200F0002ull;
+
+static const uint64_t P9N2_C_0_MULTICAST_GROUP_2 = 0x200F0002ull;
+
+static const uint64_t P9N2_C_1_MULTICAST_GROUP_2 = 0x210F0002ull;
+
+static const uint64_t P9N2_C_2_MULTICAST_GROUP_2 = 0x220F0002ull;
+
+static const uint64_t P9N2_C_3_MULTICAST_GROUP_2 = 0x230F0002ull;
+
+static const uint64_t P9N2_C_4_MULTICAST_GROUP_2 = 0x240F0002ull;
+
+static const uint64_t P9N2_C_5_MULTICAST_GROUP_2 = 0x250F0002ull;
+
+static const uint64_t P9N2_C_6_MULTICAST_GROUP_2 = 0x260F0002ull;
+
+static const uint64_t P9N2_C_7_MULTICAST_GROUP_2 = 0x270F0002ull;
+
+static const uint64_t P9N2_C_8_MULTICAST_GROUP_2 = 0x280F0002ull;
+
+static const uint64_t P9N2_C_9_MULTICAST_GROUP_2 = 0x290F0002ull;
+
+static const uint64_t P9N2_C_10_MULTICAST_GROUP_2 = 0x2A0F0002ull;
+
+static const uint64_t P9N2_C_11_MULTICAST_GROUP_2 = 0x2B0F0002ull;
+
+static const uint64_t P9N2_C_12_MULTICAST_GROUP_2 = 0x2C0F0002ull;
+
+static const uint64_t P9N2_C_13_MULTICAST_GROUP_2 = 0x2D0F0002ull;
+
+static const uint64_t P9N2_C_14_MULTICAST_GROUP_2 = 0x2E0F0002ull;
+
+static const uint64_t P9N2_C_15_MULTICAST_GROUP_2 = 0x2F0F0002ull;
+
+static const uint64_t P9N2_C_16_MULTICAST_GROUP_2 = 0x300F0002ull;
+
+static const uint64_t P9N2_C_17_MULTICAST_GROUP_2 = 0x310F0002ull;
+
+static const uint64_t P9N2_C_18_MULTICAST_GROUP_2 = 0x320F0002ull;
+
+static const uint64_t P9N2_C_19_MULTICAST_GROUP_2 = 0x330F0002ull;
+
+static const uint64_t P9N2_C_20_MULTICAST_GROUP_2 = 0x340F0002ull;
+
+static const uint64_t P9N2_C_21_MULTICAST_GROUP_2 = 0x350F0002ull;
+
+static const uint64_t P9N2_C_22_MULTICAST_GROUP_2 = 0x360F0002ull;
+
+static const uint64_t P9N2_C_23_MULTICAST_GROUP_2 = 0x370F0002ull;
+
+static const uint64_t P9N2_EQ_MULTICAST_GROUP_2 = 0x100F0002ull;
+
+static const uint64_t P9N2_EQ_0_MULTICAST_GROUP_2 = 0x100F0002ull;
+
+static const uint64_t P9N2_EQ_1_MULTICAST_GROUP_2 = 0x110F0002ull;
+
+static const uint64_t P9N2_EQ_2_MULTICAST_GROUP_2 = 0x120F0002ull;
+
+static const uint64_t P9N2_EQ_3_MULTICAST_GROUP_2 = 0x130F0002ull;
+
+static const uint64_t P9N2_EQ_4_MULTICAST_GROUP_2 = 0x140F0002ull;
+
+static const uint64_t P9N2_EQ_5_MULTICAST_GROUP_2 = 0x150F0002ull;
+
+static const uint64_t P9N2_EX_MULTICAST_GROUP_2 = 0x200F0002ull;
+//DUPS: 210F0002,
+static const uint64_t P9N2_EX_0_MULTICAST_GROUP_2 = 0x200F0002ull;
+//DUPS: 210F0002,
+static const uint64_t P9N2_EX_1_MULTICAST_GROUP_2 = 0x220F0002ull;
+//DUPS: 220F0002,
+static const uint64_t P9N2_EX_2_MULTICAST_GROUP_2 = 0x240F0002ull;
+//DUPS: 250F0002,
+static const uint64_t P9N2_EX_3_MULTICAST_GROUP_2 = 0x260F0002ull;
+//DUPS: 270F0002,
+static const uint64_t P9N2_EX_4_MULTICAST_GROUP_2 = 0x280F0002ull;
+//DUPS: 290F0002,
+static const uint64_t P9N2_EX_5_MULTICAST_GROUP_2 = 0x2A0F0002ull;
+//DUPS: 2B0F0002,
+static const uint64_t P9N2_EX_6_MULTICAST_GROUP_2 = 0x2C0F0002ull;
+//DUPS: 2D0F0002,
+static const uint64_t P9N2_EX_7_MULTICAST_GROUP_2 = 0x2E0F0002ull;
+//DUPS: 2F0F0002,
+static const uint64_t P9N2_EX_8_MULTICAST_GROUP_2 = 0x300F0002ull;
+//DUPS: 310F0002,
+static const uint64_t P9N2_EX_9_MULTICAST_GROUP_2 = 0x320F0002ull;
+//DUPS: 330F0002,
+static const uint64_t P9N2_EX_10_MULTICAST_GROUP_2 = 0x340F0002ull;
+//DUPS: 350F0002,
+static const uint64_t P9N2_EX_11_MULTICAST_GROUP_2 = 0x360F0002ull;
+//DUPS: 370F0002,
+
+static const uint64_t P9N2_C_MULTICAST_GROUP_3 = 0x200F0003ull;
+
+static const uint64_t P9N2_C_0_MULTICAST_GROUP_3 = 0x200F0003ull;
+
+static const uint64_t P9N2_C_1_MULTICAST_GROUP_3 = 0x210F0003ull;
+
+static const uint64_t P9N2_C_2_MULTICAST_GROUP_3 = 0x220F0003ull;
+
+static const uint64_t P9N2_C_3_MULTICAST_GROUP_3 = 0x230F0003ull;
+
+static const uint64_t P9N2_C_4_MULTICAST_GROUP_3 = 0x240F0003ull;
+
+static const uint64_t P9N2_C_5_MULTICAST_GROUP_3 = 0x250F0003ull;
+
+static const uint64_t P9N2_C_6_MULTICAST_GROUP_3 = 0x260F0003ull;
+
+static const uint64_t P9N2_C_7_MULTICAST_GROUP_3 = 0x270F0003ull;
+
+static const uint64_t P9N2_C_8_MULTICAST_GROUP_3 = 0x280F0003ull;
+
+static const uint64_t P9N2_C_9_MULTICAST_GROUP_3 = 0x290F0003ull;
+
+static const uint64_t P9N2_C_10_MULTICAST_GROUP_3 = 0x2A0F0003ull;
+
+static const uint64_t P9N2_C_11_MULTICAST_GROUP_3 = 0x2B0F0003ull;
+
+static const uint64_t P9N2_C_12_MULTICAST_GROUP_3 = 0x2C0F0003ull;
+
+static const uint64_t P9N2_C_13_MULTICAST_GROUP_3 = 0x2D0F0003ull;
+
+static const uint64_t P9N2_C_14_MULTICAST_GROUP_3 = 0x2E0F0003ull;
+
+static const uint64_t P9N2_C_15_MULTICAST_GROUP_3 = 0x2F0F0003ull;
+
+static const uint64_t P9N2_C_16_MULTICAST_GROUP_3 = 0x300F0003ull;
+
+static const uint64_t P9N2_C_17_MULTICAST_GROUP_3 = 0x310F0003ull;
+
+static const uint64_t P9N2_C_18_MULTICAST_GROUP_3 = 0x320F0003ull;
+
+static const uint64_t P9N2_C_19_MULTICAST_GROUP_3 = 0x330F0003ull;
+
+static const uint64_t P9N2_C_20_MULTICAST_GROUP_3 = 0x340F0003ull;
+
+static const uint64_t P9N2_C_21_MULTICAST_GROUP_3 = 0x350F0003ull;
+
+static const uint64_t P9N2_C_22_MULTICAST_GROUP_3 = 0x360F0003ull;
+
+static const uint64_t P9N2_C_23_MULTICAST_GROUP_3 = 0x370F0003ull;
+
+static const uint64_t P9N2_EQ_MULTICAST_GROUP_3 = 0x100F0003ull;
+
+static const uint64_t P9N2_EQ_0_MULTICAST_GROUP_3 = 0x100F0003ull;
+
+static const uint64_t P9N2_EQ_1_MULTICAST_GROUP_3 = 0x110F0003ull;
+
+static const uint64_t P9N2_EQ_2_MULTICAST_GROUP_3 = 0x120F0003ull;
+
+static const uint64_t P9N2_EQ_3_MULTICAST_GROUP_3 = 0x130F0003ull;
+
+static const uint64_t P9N2_EQ_4_MULTICAST_GROUP_3 = 0x140F0003ull;
+
+static const uint64_t P9N2_EQ_5_MULTICAST_GROUP_3 = 0x150F0003ull;
+
+static const uint64_t P9N2_EX_MULTICAST_GROUP_3 = 0x200F0003ull;
+//DUPS: 210F0003,
+static const uint64_t P9N2_EX_0_MULTICAST_GROUP_3 = 0x200F0003ull;
+//DUPS: 210F0003,
+static const uint64_t P9N2_EX_1_MULTICAST_GROUP_3 = 0x220F0003ull;
+//DUPS: 220F0003,
+static const uint64_t P9N2_EX_2_MULTICAST_GROUP_3 = 0x240F0003ull;
+//DUPS: 250F0003,
+static const uint64_t P9N2_EX_3_MULTICAST_GROUP_3 = 0x260F0003ull;
+//DUPS: 270F0003,
+static const uint64_t P9N2_EX_4_MULTICAST_GROUP_3 = 0x280F0003ull;
+//DUPS: 290F0003,
+static const uint64_t P9N2_EX_5_MULTICAST_GROUP_3 = 0x2A0F0003ull;
+//DUPS: 2B0F0003,
+static const uint64_t P9N2_EX_6_MULTICAST_GROUP_3 = 0x2C0F0003ull;
+//DUPS: 2D0F0003,
+static const uint64_t P9N2_EX_7_MULTICAST_GROUP_3 = 0x2E0F0003ull;
+//DUPS: 2F0F0003,
+static const uint64_t P9N2_EX_8_MULTICAST_GROUP_3 = 0x300F0003ull;
+//DUPS: 310F0003,
+static const uint64_t P9N2_EX_9_MULTICAST_GROUP_3 = 0x320F0003ull;
+//DUPS: 330F0003,
+static const uint64_t P9N2_EX_10_MULTICAST_GROUP_3 = 0x340F0003ull;
+//DUPS: 350F0003,
+static const uint64_t P9N2_EX_11_MULTICAST_GROUP_3 = 0x360F0003ull;
+//DUPS: 370F0003,
+
+static const uint64_t P9N2_C_MULTICAST_GROUP_4 = 0x200F0004ull;
+
+static const uint64_t P9N2_C_0_MULTICAST_GROUP_4 = 0x200F0004ull;
+
+static const uint64_t P9N2_C_1_MULTICAST_GROUP_4 = 0x210F0004ull;
+
+static const uint64_t P9N2_C_2_MULTICAST_GROUP_4 = 0x220F0004ull;
+
+static const uint64_t P9N2_C_3_MULTICAST_GROUP_4 = 0x230F0004ull;
+
+static const uint64_t P9N2_C_4_MULTICAST_GROUP_4 = 0x240F0004ull;
+
+static const uint64_t P9N2_C_5_MULTICAST_GROUP_4 = 0x250F0004ull;
+
+static const uint64_t P9N2_C_6_MULTICAST_GROUP_4 = 0x260F0004ull;
+
+static const uint64_t P9N2_C_7_MULTICAST_GROUP_4 = 0x270F0004ull;
+
+static const uint64_t P9N2_C_8_MULTICAST_GROUP_4 = 0x280F0004ull;
+
+static const uint64_t P9N2_C_9_MULTICAST_GROUP_4 = 0x290F0004ull;
+
+static const uint64_t P9N2_C_10_MULTICAST_GROUP_4 = 0x2A0F0004ull;
+
+static const uint64_t P9N2_C_11_MULTICAST_GROUP_4 = 0x2B0F0004ull;
+
+static const uint64_t P9N2_C_12_MULTICAST_GROUP_4 = 0x2C0F0004ull;
+
+static const uint64_t P9N2_C_13_MULTICAST_GROUP_4 = 0x2D0F0004ull;
+
+static const uint64_t P9N2_C_14_MULTICAST_GROUP_4 = 0x2E0F0004ull;
+
+static const uint64_t P9N2_C_15_MULTICAST_GROUP_4 = 0x2F0F0004ull;
+
+static const uint64_t P9N2_C_16_MULTICAST_GROUP_4 = 0x300F0004ull;
+
+static const uint64_t P9N2_C_17_MULTICAST_GROUP_4 = 0x310F0004ull;
+
+static const uint64_t P9N2_C_18_MULTICAST_GROUP_4 = 0x320F0004ull;
+
+static const uint64_t P9N2_C_19_MULTICAST_GROUP_4 = 0x330F0004ull;
+
+static const uint64_t P9N2_C_20_MULTICAST_GROUP_4 = 0x340F0004ull;
+
+static const uint64_t P9N2_C_21_MULTICAST_GROUP_4 = 0x350F0004ull;
+
+static const uint64_t P9N2_C_22_MULTICAST_GROUP_4 = 0x360F0004ull;
+
+static const uint64_t P9N2_C_23_MULTICAST_GROUP_4 = 0x370F0004ull;
+
+static const uint64_t P9N2_EQ_MULTICAST_GROUP_4 = 0x100F0004ull;
+
+static const uint64_t P9N2_EQ_0_MULTICAST_GROUP_4 = 0x100F0004ull;
+
+static const uint64_t P9N2_EQ_1_MULTICAST_GROUP_4 = 0x110F0004ull;
+
+static const uint64_t P9N2_EQ_2_MULTICAST_GROUP_4 = 0x120F0004ull;
+
+static const uint64_t P9N2_EQ_3_MULTICAST_GROUP_4 = 0x130F0004ull;
+
+static const uint64_t P9N2_EQ_4_MULTICAST_GROUP_4 = 0x140F0004ull;
+
+static const uint64_t P9N2_EQ_5_MULTICAST_GROUP_4 = 0x150F0004ull;
+
+static const uint64_t P9N2_EX_MULTICAST_GROUP_4 = 0x200F0004ull;
+//DUPS: 210F0004,
+static const uint64_t P9N2_EX_0_MULTICAST_GROUP_4 = 0x200F0004ull;
+//DUPS: 210F0004,
+static const uint64_t P9N2_EX_1_MULTICAST_GROUP_4 = 0x220F0004ull;
+//DUPS: 220F0004,
+static const uint64_t P9N2_EX_2_MULTICAST_GROUP_4 = 0x240F0004ull;
+//DUPS: 250F0004,
+static const uint64_t P9N2_EX_3_MULTICAST_GROUP_4 = 0x260F0004ull;
+//DUPS: 270F0004,
+static const uint64_t P9N2_EX_4_MULTICAST_GROUP_4 = 0x280F0004ull;
+//DUPS: 290F0004,
+static const uint64_t P9N2_EX_5_MULTICAST_GROUP_4 = 0x2A0F0004ull;
+//DUPS: 2B0F0004,
+static const uint64_t P9N2_EX_6_MULTICAST_GROUP_4 = 0x2C0F0004ull;
+//DUPS: 2D0F0004,
+static const uint64_t P9N2_EX_7_MULTICAST_GROUP_4 = 0x2E0F0004ull;
+//DUPS: 2F0F0004,
+static const uint64_t P9N2_EX_8_MULTICAST_GROUP_4 = 0x300F0004ull;
+//DUPS: 310F0004,
+static const uint64_t P9N2_EX_9_MULTICAST_GROUP_4 = 0x320F0004ull;
+//DUPS: 330F0004,
+static const uint64_t P9N2_EX_10_MULTICAST_GROUP_4 = 0x340F0004ull;
+//DUPS: 350F0004,
+static const uint64_t P9N2_EX_11_MULTICAST_GROUP_4 = 0x360F0004ull;
+//DUPS: 370F0004,
+
+static const uint64_t P9N2_EQ_NCU_DARN_BAR_REG = 0x10011011ull;
+//DUPS: 10011411,
+static const uint64_t P9N2_EQ_0_NCU_DARN_BAR_REG = 0x10011011ull;
+//DUPS: 10011411,
+static const uint64_t P9N2_EQ_1_NCU_DARN_BAR_REG = 0x11011011ull;
+//DUPS: 11011411,
+static const uint64_t P9N2_EQ_2_NCU_DARN_BAR_REG = 0x12011011ull;
+//DUPS: 12011411,
+static const uint64_t P9N2_EQ_3_NCU_DARN_BAR_REG = 0x13011011ull;
+//DUPS: 13011411,
+static const uint64_t P9N2_EQ_4_NCU_DARN_BAR_REG = 0x14011011ull;
+//DUPS: 14011411,
+static const uint64_t P9N2_EQ_5_NCU_DARN_BAR_REG = 0x15011011ull;
+//DUPS: 15011411,
+static const uint64_t P9N2_EX_NCU_DARN_BAR_REG = 0x10011011ull;
+
+static const uint64_t P9N2_EX_0_NCU_DARN_BAR_REG = 0x10011011ull;
+
+static const uint64_t P9N2_EX_1_NCU_DARN_BAR_REG = 0x10011411ull;
+
+static const uint64_t P9N2_EX_2_NCU_DARN_BAR_REG = 0x11011011ull;
+
+static const uint64_t P9N2_EX_3_NCU_DARN_BAR_REG = 0x11011411ull;
+
+static const uint64_t P9N2_EX_4_NCU_DARN_BAR_REG = 0x12011011ull;
+
+static const uint64_t P9N2_EX_5_NCU_DARN_BAR_REG = 0x12011411ull;
+
+static const uint64_t P9N2_EX_6_NCU_DARN_BAR_REG = 0x13011011ull;
+
+static const uint64_t P9N2_EX_7_NCU_DARN_BAR_REG = 0x13011411ull;
+
+static const uint64_t P9N2_EX_8_NCU_DARN_BAR_REG = 0x14011011ull;
+
+static const uint64_t P9N2_EX_9_NCU_DARN_BAR_REG = 0x14011411ull;
+
+static const uint64_t P9N2_EX_10_NCU_DARN_BAR_REG = 0x15011011ull;
+
+static const uint64_t P9N2_EX_11_NCU_DARN_BAR_REG = 0x15011411ull;
+
+
+static const uint64_t P9N2_EQ_NCU_MODE_REG = 0x1001100Aull;
+//DUPS: 1001140A,
+static const uint64_t P9N2_EQ_0_NCU_MODE_REG = 0x1001100Aull;
+//DUPS: 1001140A,
+static const uint64_t P9N2_EQ_1_NCU_MODE_REG = 0x1101100Aull;
+//DUPS: 1101140A,
+static const uint64_t P9N2_EQ_2_NCU_MODE_REG = 0x1201100Aull;
+//DUPS: 1201140A,
+static const uint64_t P9N2_EQ_3_NCU_MODE_REG = 0x1301100Aull;
+//DUPS: 1301140A,
+static const uint64_t P9N2_EQ_4_NCU_MODE_REG = 0x1401100Aull;
+//DUPS: 1401140A,
+static const uint64_t P9N2_EQ_5_NCU_MODE_REG = 0x1501100Aull;
+//DUPS: 1501140A,
+static const uint64_t P9N2_EX_NCU_MODE_REG = 0x1001100Aull;
+
+static const uint64_t P9N2_EX_0_NCU_MODE_REG = 0x1001100Aull;
+
+static const uint64_t P9N2_EX_1_NCU_MODE_REG = 0x1001140Aull;
+
+static const uint64_t P9N2_EX_2_NCU_MODE_REG = 0x1101100Aull;
+
+static const uint64_t P9N2_EX_3_NCU_MODE_REG = 0x1101140Aull;
+
+static const uint64_t P9N2_EX_4_NCU_MODE_REG = 0x1201100Aull;
+
+static const uint64_t P9N2_EX_5_NCU_MODE_REG = 0x1201140Aull;
+
+static const uint64_t P9N2_EX_6_NCU_MODE_REG = 0x1301100Aull;
+
+static const uint64_t P9N2_EX_7_NCU_MODE_REG = 0x1301140Aull;
+
+static const uint64_t P9N2_EX_8_NCU_MODE_REG = 0x1401100Aull;
+
+static const uint64_t P9N2_EX_9_NCU_MODE_REG = 0x1401140Aull;
+
+static const uint64_t P9N2_EX_10_NCU_MODE_REG = 0x1501100Aull;
+
+static const uint64_t P9N2_EX_11_NCU_MODE_REG = 0x1501140Aull;
+
+
+static const uint64_t P9N2_EQ_NCU_MODE_REG2 = 0x1001100Bull;
+//DUPS: 1001140B,
+static const uint64_t P9N2_EQ_0_NCU_MODE_REG2 = 0x1001100Bull;
+//DUPS: 1001140B,
+static const uint64_t P9N2_EQ_1_NCU_MODE_REG2 = 0x1101100Bull;
+//DUPS: 1101140B,
+static const uint64_t P9N2_EQ_2_NCU_MODE_REG2 = 0x1201100Bull;
+//DUPS: 1201140B,
+static const uint64_t P9N2_EQ_3_NCU_MODE_REG2 = 0x1301100Bull;
+//DUPS: 1301140B,
+static const uint64_t P9N2_EQ_4_NCU_MODE_REG2 = 0x1401100Bull;
+//DUPS: 1401140B,
+static const uint64_t P9N2_EQ_5_NCU_MODE_REG2 = 0x1501100Bull;
+//DUPS: 1501140B,
+static const uint64_t P9N2_EX_NCU_MODE_REG2 = 0x1001100Bull;
+
+static const uint64_t P9N2_EX_0_NCU_MODE_REG2 = 0x1001100Bull;
+
+static const uint64_t P9N2_EX_1_NCU_MODE_REG2 = 0x1001140Bull;
+
+static const uint64_t P9N2_EX_2_NCU_MODE_REG2 = 0x1101100Bull;
+
+static const uint64_t P9N2_EX_3_NCU_MODE_REG2 = 0x1101140Bull;
+
+static const uint64_t P9N2_EX_4_NCU_MODE_REG2 = 0x1201100Bull;
+
+static const uint64_t P9N2_EX_5_NCU_MODE_REG2 = 0x1201140Bull;
+
+static const uint64_t P9N2_EX_6_NCU_MODE_REG2 = 0x1301100Bull;
+
+static const uint64_t P9N2_EX_7_NCU_MODE_REG2 = 0x1301140Bull;
+
+static const uint64_t P9N2_EX_8_NCU_MODE_REG2 = 0x1401100Bull;
+
+static const uint64_t P9N2_EX_9_NCU_MODE_REG2 = 0x1401140Bull;
+
+static const uint64_t P9N2_EX_10_NCU_MODE_REG2 = 0x1501100Bull;
+
+static const uint64_t P9N2_EX_11_NCU_MODE_REG2 = 0x1501140Bull;
+
+
+static const uint64_t P9N2_EQ_NCU_MODE_REG3 = 0x1001100Cull;
+//DUPS: 1001140C,
+static const uint64_t P9N2_EQ_0_NCU_MODE_REG3 = 0x1001100Cull;
+//DUPS: 1001140C,
+static const uint64_t P9N2_EQ_1_NCU_MODE_REG3 = 0x1101100Cull;
+//DUPS: 1101140C,
+static const uint64_t P9N2_EQ_2_NCU_MODE_REG3 = 0x1201100Cull;
+//DUPS: 1201140C,
+static const uint64_t P9N2_EQ_3_NCU_MODE_REG3 = 0x1301100Cull;
+//DUPS: 1301140C,
+static const uint64_t P9N2_EQ_4_NCU_MODE_REG3 = 0x1401100Cull;
+//DUPS: 1401140C,
+static const uint64_t P9N2_EQ_5_NCU_MODE_REG3 = 0x1501100Cull;
+//DUPS: 1501140C,
+static const uint64_t P9N2_EX_NCU_MODE_REG3 = 0x1001100Cull;
+
+static const uint64_t P9N2_EX_0_NCU_MODE_REG3 = 0x1001100Cull;
+
+static const uint64_t P9N2_EX_1_NCU_MODE_REG3 = 0x1001140Cull;
+
+static const uint64_t P9N2_EX_2_NCU_MODE_REG3 = 0x1101100Cull;
+
+static const uint64_t P9N2_EX_3_NCU_MODE_REG3 = 0x1101140Cull;
+
+static const uint64_t P9N2_EX_4_NCU_MODE_REG3 = 0x1201100Cull;
+
+static const uint64_t P9N2_EX_5_NCU_MODE_REG3 = 0x1201140Cull;
+
+static const uint64_t P9N2_EX_6_NCU_MODE_REG3 = 0x1301100Cull;
+
+static const uint64_t P9N2_EX_7_NCU_MODE_REG3 = 0x1301140Cull;
+
+static const uint64_t P9N2_EX_8_NCU_MODE_REG3 = 0x1401100Cull;
+
+static const uint64_t P9N2_EX_9_NCU_MODE_REG3 = 0x1401140Cull;
+
+static const uint64_t P9N2_EX_10_NCU_MODE_REG3 = 0x1501100Cull;
+
+static const uint64_t P9N2_EX_11_NCU_MODE_REG3 = 0x1501140Cull;
+
+
+static const uint64_t P9N2_EQ_NCU_SLOW_LPAR_REG0 = 0x10011012ull;
+//DUPS: 10011412,
+static const uint64_t P9N2_EQ_0_NCU_SLOW_LPAR_REG0 = 0x10011012ull;
+//DUPS: 10011412,
+static const uint64_t P9N2_EQ_1_NCU_SLOW_LPAR_REG0 = 0x11011012ull;
+//DUPS: 11011412,
+static const uint64_t P9N2_EQ_2_NCU_SLOW_LPAR_REG0 = 0x12011012ull;
+//DUPS: 12011412,
+static const uint64_t P9N2_EQ_3_NCU_SLOW_LPAR_REG0 = 0x13011012ull;
+//DUPS: 13011412,
+static const uint64_t P9N2_EQ_4_NCU_SLOW_LPAR_REG0 = 0x14011012ull;
+//DUPS: 14011412,
+static const uint64_t P9N2_EQ_5_NCU_SLOW_LPAR_REG0 = 0x15011012ull;
+//DUPS: 15011412,
+static const uint64_t P9N2_EX_NCU_SLOW_LPAR_REG0 = 0x10011012ull;
+
+static const uint64_t P9N2_EX_0_NCU_SLOW_LPAR_REG0 = 0x10011012ull;
+
+static const uint64_t P9N2_EX_1_NCU_SLOW_LPAR_REG0 = 0x10011412ull;
+
+static const uint64_t P9N2_EX_2_NCU_SLOW_LPAR_REG0 = 0x11011012ull;
+
+static const uint64_t P9N2_EX_3_NCU_SLOW_LPAR_REG0 = 0x11011412ull;
+
+static const uint64_t P9N2_EX_4_NCU_SLOW_LPAR_REG0 = 0x12011012ull;
+
+static const uint64_t P9N2_EX_5_NCU_SLOW_LPAR_REG0 = 0x12011412ull;
+
+static const uint64_t P9N2_EX_6_NCU_SLOW_LPAR_REG0 = 0x13011012ull;
+
+static const uint64_t P9N2_EX_7_NCU_SLOW_LPAR_REG0 = 0x13011412ull;
+
+static const uint64_t P9N2_EX_8_NCU_SLOW_LPAR_REG0 = 0x14011012ull;
+
+static const uint64_t P9N2_EX_9_NCU_SLOW_LPAR_REG0 = 0x14011412ull;
+
+static const uint64_t P9N2_EX_10_NCU_SLOW_LPAR_REG0 = 0x15011012ull;
+
+static const uint64_t P9N2_EX_11_NCU_SLOW_LPAR_REG0 = 0x15011412ull;
+
+
+static const uint64_t P9N2_EQ_NCU_SLOW_LPAR_REG1 = 0x10011013ull;
+//DUPS: 10011413,
+static const uint64_t P9N2_EQ_0_NCU_SLOW_LPAR_REG1 = 0x10011013ull;
+//DUPS: 10011413,
+static const uint64_t P9N2_EQ_1_NCU_SLOW_LPAR_REG1 = 0x11011013ull;
+//DUPS: 11011413,
+static const uint64_t P9N2_EQ_2_NCU_SLOW_LPAR_REG1 = 0x12011013ull;
+//DUPS: 12011413,
+static const uint64_t P9N2_EQ_3_NCU_SLOW_LPAR_REG1 = 0x13011013ull;
+//DUPS: 13011413,
+static const uint64_t P9N2_EQ_4_NCU_SLOW_LPAR_REG1 = 0x14011013ull;
+//DUPS: 14011413,
+static const uint64_t P9N2_EQ_5_NCU_SLOW_LPAR_REG1 = 0x15011013ull;
+//DUPS: 15011413,
+static const uint64_t P9N2_EX_NCU_SLOW_LPAR_REG1 = 0x10011013ull;
+
+static const uint64_t P9N2_EX_0_NCU_SLOW_LPAR_REG1 = 0x10011013ull;
+
+static const uint64_t P9N2_EX_1_NCU_SLOW_LPAR_REG1 = 0x10011413ull;
+
+static const uint64_t P9N2_EX_2_NCU_SLOW_LPAR_REG1 = 0x11011013ull;
+
+static const uint64_t P9N2_EX_3_NCU_SLOW_LPAR_REG1 = 0x11011413ull;
+
+static const uint64_t P9N2_EX_4_NCU_SLOW_LPAR_REG1 = 0x12011013ull;
+
+static const uint64_t P9N2_EX_5_NCU_SLOW_LPAR_REG1 = 0x12011413ull;
+
+static const uint64_t P9N2_EX_6_NCU_SLOW_LPAR_REG1 = 0x13011013ull;
+
+static const uint64_t P9N2_EX_7_NCU_SLOW_LPAR_REG1 = 0x13011413ull;
+
+static const uint64_t P9N2_EX_8_NCU_SLOW_LPAR_REG1 = 0x14011013ull;
+
+static const uint64_t P9N2_EX_9_NCU_SLOW_LPAR_REG1 = 0x14011413ull;
+
+static const uint64_t P9N2_EX_10_NCU_SLOW_LPAR_REG1 = 0x15011013ull;
+
+static const uint64_t P9N2_EX_11_NCU_SLOW_LPAR_REG1 = 0x15011413ull;
+
+
+static const uint64_t P9N2_EQ_NCU_SPEC_BAR_REG = 0x10011010ull;
+//DUPS: 10011410,
+static const uint64_t P9N2_EQ_0_NCU_SPEC_BAR_REG = 0x10011010ull;
+//DUPS: 10011410,
+static const uint64_t P9N2_EQ_1_NCU_SPEC_BAR_REG = 0x11011010ull;
+//DUPS: 11011410,
+static const uint64_t P9N2_EQ_2_NCU_SPEC_BAR_REG = 0x12011010ull;
+//DUPS: 12011410,
+static const uint64_t P9N2_EQ_3_NCU_SPEC_BAR_REG = 0x13011010ull;
+//DUPS: 13011410,
+static const uint64_t P9N2_EQ_4_NCU_SPEC_BAR_REG = 0x14011010ull;
+//DUPS: 14011410,
+static const uint64_t P9N2_EQ_5_NCU_SPEC_BAR_REG = 0x15011010ull;
+//DUPS: 15011410,
+static const uint64_t P9N2_EX_NCU_SPEC_BAR_REG = 0x10011010ull;
+
+static const uint64_t P9N2_EX_0_NCU_SPEC_BAR_REG = 0x10011010ull;
+
+static const uint64_t P9N2_EX_1_NCU_SPEC_BAR_REG = 0x10011410ull;
+
+static const uint64_t P9N2_EX_2_NCU_SPEC_BAR_REG = 0x11011010ull;
+
+static const uint64_t P9N2_EX_3_NCU_SPEC_BAR_REG = 0x11011410ull;
+
+static const uint64_t P9N2_EX_4_NCU_SPEC_BAR_REG = 0x12011010ull;
+
+static const uint64_t P9N2_EX_5_NCU_SPEC_BAR_REG = 0x12011410ull;
+
+static const uint64_t P9N2_EX_6_NCU_SPEC_BAR_REG = 0x13011010ull;
+
+static const uint64_t P9N2_EX_7_NCU_SPEC_BAR_REG = 0x13011410ull;
+
+static const uint64_t P9N2_EX_8_NCU_SPEC_BAR_REG = 0x14011010ull;
+
+static const uint64_t P9N2_EX_9_NCU_SPEC_BAR_REG = 0x14011410ull;
+
+static const uint64_t P9N2_EX_10_NCU_SPEC_BAR_REG = 0x15011010ull;
+
+static const uint64_t P9N2_EX_11_NCU_SPEC_BAR_REG = 0x15011410ull;
+
+
+static const uint64_t P9N2_EQ_NCU_STATUS_REG = 0x1001100Full;
+//DUPS: 1001140F,
+static const uint64_t P9N2_EQ_0_NCU_STATUS_REG = 0x1001100Full;
+//DUPS: 1001140F,
+static const uint64_t P9N2_EQ_1_NCU_STATUS_REG = 0x1101100Full;
+//DUPS: 1101140F,
+static const uint64_t P9N2_EQ_2_NCU_STATUS_REG = 0x1201100Full;
+//DUPS: 1201140F,
+static const uint64_t P9N2_EQ_3_NCU_STATUS_REG = 0x1301100Full;
+//DUPS: 1301140F,
+static const uint64_t P9N2_EQ_4_NCU_STATUS_REG = 0x1401100Full;
+//DUPS: 1401140F,
+static const uint64_t P9N2_EQ_5_NCU_STATUS_REG = 0x1501100Full;
+//DUPS: 1501140F,
+static const uint64_t P9N2_EX_NCU_STATUS_REG = 0x1001100Full;
+
+static const uint64_t P9N2_EX_0_NCU_STATUS_REG = 0x1001100Full;
+
+static const uint64_t P9N2_EX_1_NCU_STATUS_REG = 0x1001140Full;
+
+static const uint64_t P9N2_EX_2_NCU_STATUS_REG = 0x1101100Full;
+
+static const uint64_t P9N2_EX_3_NCU_STATUS_REG = 0x1101140Full;
+
+static const uint64_t P9N2_EX_4_NCU_STATUS_REG = 0x1201100Full;
+
+static const uint64_t P9N2_EX_5_NCU_STATUS_REG = 0x1201140Full;
+
+static const uint64_t P9N2_EX_6_NCU_STATUS_REG = 0x1301100Full;
+
+static const uint64_t P9N2_EX_7_NCU_STATUS_REG = 0x1301140Full;
+
+static const uint64_t P9N2_EX_8_NCU_STATUS_REG = 0x1401100Full;
+
+static const uint64_t P9N2_EX_9_NCU_STATUS_REG = 0x1401140Full;
+
+static const uint64_t P9N2_EX_10_NCU_STATUS_REG = 0x1501100Full;
+
+static const uint64_t P9N2_EX_11_NCU_STATUS_REG = 0x1501140Full;
+
+
+static const uint64_t P9N2_C_NET_CTRL0 = 0x200F0040ull;
+
+static const uint64_t P9N2_C_NET_CTRL0_WAND = 0x200F0041ull;
+
+static const uint64_t P9N2_C_NET_CTRL0_WOR = 0x200F0042ull;
+
+static const uint64_t P9N2_C_0_NET_CTRL0 = 0x200F0040ull;
+
+static const uint64_t P9N2_C_0_NET_CTRL0_WAND = 0x200F0041ull;
+
+static const uint64_t P9N2_C_0_NET_CTRL0_WOR = 0x200F0042ull;
+
+static const uint64_t P9N2_C_1_NET_CTRL0 = 0x210F0040ull;
+
+static const uint64_t P9N2_C_1_NET_CTRL0_WAND = 0x210F0041ull;
+
+static const uint64_t P9N2_C_1_NET_CTRL0_WOR = 0x210F0042ull;
+
+static const uint64_t P9N2_C_2_NET_CTRL0 = 0x220F0040ull;
+
+static const uint64_t P9N2_C_2_NET_CTRL0_WAND = 0x220F0041ull;
+
+static const uint64_t P9N2_C_2_NET_CTRL0_WOR = 0x220F0042ull;
+
+static const uint64_t P9N2_C_3_NET_CTRL0 = 0x230F0040ull;
+
+static const uint64_t P9N2_C_3_NET_CTRL0_WAND = 0x230F0041ull;
+
+static const uint64_t P9N2_C_3_NET_CTRL0_WOR = 0x230F0042ull;
+
+static const uint64_t P9N2_C_4_NET_CTRL0 = 0x240F0040ull;
+
+static const uint64_t P9N2_C_4_NET_CTRL0_WAND = 0x240F0041ull;
+
+static const uint64_t P9N2_C_4_NET_CTRL0_WOR = 0x240F0042ull;
+
+static const uint64_t P9N2_C_5_NET_CTRL0 = 0x250F0040ull;
+
+static const uint64_t P9N2_C_5_NET_CTRL0_WAND = 0x250F0041ull;
+
+static const uint64_t P9N2_C_5_NET_CTRL0_WOR = 0x250F0042ull;
+
+static const uint64_t P9N2_C_6_NET_CTRL0 = 0x260F0040ull;
+
+static const uint64_t P9N2_C_6_NET_CTRL0_WAND = 0x260F0041ull;
+
+static const uint64_t P9N2_C_6_NET_CTRL0_WOR = 0x260F0042ull;
+
+static const uint64_t P9N2_C_7_NET_CTRL0 = 0x270F0040ull;
+
+static const uint64_t P9N2_C_7_NET_CTRL0_WAND = 0x270F0041ull;
+
+static const uint64_t P9N2_C_7_NET_CTRL0_WOR = 0x270F0042ull;
+
+static const uint64_t P9N2_C_8_NET_CTRL0 = 0x280F0040ull;
+
+static const uint64_t P9N2_C_8_NET_CTRL0_WAND = 0x280F0041ull;
+
+static const uint64_t P9N2_C_8_NET_CTRL0_WOR = 0x280F0042ull;
+
+static const uint64_t P9N2_C_9_NET_CTRL0 = 0x290F0040ull;
+
+static const uint64_t P9N2_C_9_NET_CTRL0_WAND = 0x290F0041ull;
+
+static const uint64_t P9N2_C_9_NET_CTRL0_WOR = 0x290F0042ull;
+
+static const uint64_t P9N2_C_10_NET_CTRL0 = 0x2A0F0040ull;
+
+static const uint64_t P9N2_C_10_NET_CTRL0_WAND = 0x2A0F0041ull;
+
+static const uint64_t P9N2_C_10_NET_CTRL0_WOR = 0x2A0F0042ull;
+
+static const uint64_t P9N2_C_11_NET_CTRL0 = 0x2B0F0040ull;
+
+static const uint64_t P9N2_C_11_NET_CTRL0_WAND = 0x2B0F0041ull;
+
+static const uint64_t P9N2_C_11_NET_CTRL0_WOR = 0x2B0F0042ull;
+
+static const uint64_t P9N2_C_12_NET_CTRL0 = 0x2C0F0040ull;
+
+static const uint64_t P9N2_C_12_NET_CTRL0_WAND = 0x2C0F0041ull;
+
+static const uint64_t P9N2_C_12_NET_CTRL0_WOR = 0x2C0F0042ull;
+
+static const uint64_t P9N2_C_13_NET_CTRL0 = 0x2D0F0040ull;
+
+static const uint64_t P9N2_C_13_NET_CTRL0_WAND = 0x2D0F0041ull;
+
+static const uint64_t P9N2_C_13_NET_CTRL0_WOR = 0x2D0F0042ull;
+
+static const uint64_t P9N2_C_14_NET_CTRL0 = 0x2E0F0040ull;
+
+static const uint64_t P9N2_C_14_NET_CTRL0_WAND = 0x2E0F0041ull;
+
+static const uint64_t P9N2_C_14_NET_CTRL0_WOR = 0x2E0F0042ull;
+
+static const uint64_t P9N2_C_15_NET_CTRL0 = 0x2F0F0040ull;
+
+static const uint64_t P9N2_C_15_NET_CTRL0_WAND = 0x2F0F0041ull;
+
+static const uint64_t P9N2_C_15_NET_CTRL0_WOR = 0x2F0F0042ull;
+
+static const uint64_t P9N2_C_16_NET_CTRL0 = 0x300F0040ull;
+
+static const uint64_t P9N2_C_16_NET_CTRL0_WAND = 0x300F0041ull;
+
+static const uint64_t P9N2_C_16_NET_CTRL0_WOR = 0x300F0042ull;
+
+static const uint64_t P9N2_C_17_NET_CTRL0 = 0x310F0040ull;
+
+static const uint64_t P9N2_C_17_NET_CTRL0_WAND = 0x310F0041ull;
+
+static const uint64_t P9N2_C_17_NET_CTRL0_WOR = 0x310F0042ull;
+
+static const uint64_t P9N2_C_18_NET_CTRL0 = 0x320F0040ull;
+
+static const uint64_t P9N2_C_18_NET_CTRL0_WAND = 0x320F0041ull;
+
+static const uint64_t P9N2_C_18_NET_CTRL0_WOR = 0x320F0042ull;
+
+static const uint64_t P9N2_C_19_NET_CTRL0 = 0x330F0040ull;
+
+static const uint64_t P9N2_C_19_NET_CTRL0_WAND = 0x330F0041ull;
+
+static const uint64_t P9N2_C_19_NET_CTRL0_WOR = 0x330F0042ull;
+
+static const uint64_t P9N2_C_20_NET_CTRL0 = 0x340F0040ull;
+
+static const uint64_t P9N2_C_20_NET_CTRL0_WAND = 0x340F0041ull;
+
+static const uint64_t P9N2_C_20_NET_CTRL0_WOR = 0x340F0042ull;
+
+static const uint64_t P9N2_C_21_NET_CTRL0 = 0x350F0040ull;
+
+static const uint64_t P9N2_C_21_NET_CTRL0_WAND = 0x350F0041ull;
+
+static const uint64_t P9N2_C_21_NET_CTRL0_WOR = 0x350F0042ull;
+
+static const uint64_t P9N2_C_22_NET_CTRL0 = 0x360F0040ull;
+
+static const uint64_t P9N2_C_22_NET_CTRL0_WAND = 0x360F0041ull;
+
+static const uint64_t P9N2_C_22_NET_CTRL0_WOR = 0x360F0042ull;
+
+static const uint64_t P9N2_C_23_NET_CTRL0 = 0x370F0040ull;
+
+static const uint64_t P9N2_C_23_NET_CTRL0_WAND = 0x370F0041ull;
+
+static const uint64_t P9N2_C_23_NET_CTRL0_WOR = 0x370F0042ull;
+
+static const uint64_t P9N2_EQ_NET_CTRL0 = 0x100F0040ull;
+
+static const uint64_t P9N2_EQ_NET_CTRL0_WAND = 0x100F0041ull;
+
+static const uint64_t P9N2_EQ_NET_CTRL0_WOR = 0x100F0042ull;
+
+static const uint64_t P9N2_EQ_0_NET_CTRL0 = 0x100F0040ull;
+
+static const uint64_t P9N2_EQ_0_NET_CTRL0_WAND = 0x100F0041ull;
+
+static const uint64_t P9N2_EQ_0_NET_CTRL0_WOR = 0x100F0042ull;
+
+static const uint64_t P9N2_EQ_1_NET_CTRL0 = 0x110F0040ull;
+
+static const uint64_t P9N2_EQ_1_NET_CTRL0_WAND = 0x110F0041ull;
+
+static const uint64_t P9N2_EQ_1_NET_CTRL0_WOR = 0x110F0042ull;
+
+static const uint64_t P9N2_EQ_2_NET_CTRL0 = 0x120F0040ull;
+
+static const uint64_t P9N2_EQ_2_NET_CTRL0_WAND = 0x120F0041ull;
+
+static const uint64_t P9N2_EQ_2_NET_CTRL0_WOR = 0x120F0042ull;
+
+static const uint64_t P9N2_EQ_3_NET_CTRL0 = 0x130F0040ull;
+
+static const uint64_t P9N2_EQ_3_NET_CTRL0_WAND = 0x130F0041ull;
+
+static const uint64_t P9N2_EQ_3_NET_CTRL0_WOR = 0x130F0042ull;
+
+static const uint64_t P9N2_EQ_4_NET_CTRL0 = 0x140F0040ull;
+
+static const uint64_t P9N2_EQ_4_NET_CTRL0_WAND = 0x140F0041ull;
+
+static const uint64_t P9N2_EQ_4_NET_CTRL0_WOR = 0x140F0042ull;
+
+static const uint64_t P9N2_EQ_5_NET_CTRL0 = 0x150F0040ull;
+
+static const uint64_t P9N2_EQ_5_NET_CTRL0_WAND = 0x150F0041ull;
+
+static const uint64_t P9N2_EQ_5_NET_CTRL0_WOR = 0x150F0042ull;
+
+static const uint64_t P9N2_EX_NET_CTRL0 = 0x200F0040ull;
+//DUPS: 210F0040,
+static const uint64_t P9N2_EX_NET_CTRL0_WAND = 0x200F0041ull;
+//DUPS: 210F0041,
+static const uint64_t P9N2_EX_NET_CTRL0_WOR = 0x200F0042ull;
+//DUPS: 210F0042,
+static const uint64_t P9N2_EX_0_NET_CTRL0 = 0x200F0040ull;
+//DUPS: 210F0040,
+static const uint64_t P9N2_EX_0_NET_CTRL0_WAND = 0x200F0041ull;
+//DUPS: 210F0041,
+static const uint64_t P9N2_EX_0_NET_CTRL0_WOR = 0x200F0042ull;
+//DUPS: 210F0042,
+static const uint64_t P9N2_EX_1_NET_CTRL0 = 0x220F0040ull;
+//DUPS: 220F0040,
+static const uint64_t P9N2_EX_1_NET_CTRL0_WAND = 0x220F0041ull;
+//DUPS: 220F0041,
+static const uint64_t P9N2_EX_1_NET_CTRL0_WOR = 0x220F0042ull;
+//DUPS: 220F0042,
+static const uint64_t P9N2_EX_2_NET_CTRL0 = 0x240F0040ull;
+//DUPS: 250F0040,
+static const uint64_t P9N2_EX_2_NET_CTRL0_WAND = 0x240F0041ull;
+//DUPS: 250F0041,
+static const uint64_t P9N2_EX_2_NET_CTRL0_WOR = 0x240F0042ull;
+//DUPS: 250F0042,
+static const uint64_t P9N2_EX_3_NET_CTRL0 = 0x260F0040ull;
+//DUPS: 270F0040,
+static const uint64_t P9N2_EX_3_NET_CTRL0_WAND = 0x260F0041ull;
+//DUPS: 270F0041,
+static const uint64_t P9N2_EX_3_NET_CTRL0_WOR = 0x260F0042ull;
+//DUPS: 270F0042,
+static const uint64_t P9N2_EX_4_NET_CTRL0 = 0x280F0040ull;
+//DUPS: 290F0040,
+static const uint64_t P9N2_EX_4_NET_CTRL0_WAND = 0x280F0041ull;
+//DUPS: 290F0041,
+static const uint64_t P9N2_EX_4_NET_CTRL0_WOR = 0x280F0042ull;
+//DUPS: 290F0042,
+static const uint64_t P9N2_EX_5_NET_CTRL0 = 0x2A0F0040ull;
+//DUPS: 2B0F0040,
+static const uint64_t P9N2_EX_5_NET_CTRL0_WAND = 0x2A0F0041ull;
+//DUPS: 2B0F0041,
+static const uint64_t P9N2_EX_5_NET_CTRL0_WOR = 0x2A0F0042ull;
+//DUPS: 2B0F0042,
+static const uint64_t P9N2_EX_6_NET_CTRL0 = 0x2C0F0040ull;
+//DUPS: 2D0F0040,
+static const uint64_t P9N2_EX_6_NET_CTRL0_WAND = 0x2C0F0041ull;
+//DUPS: 2D0F0041,
+static const uint64_t P9N2_EX_6_NET_CTRL0_WOR = 0x2C0F0042ull;
+//DUPS: 2D0F0042,
+static const uint64_t P9N2_EX_7_NET_CTRL0 = 0x2E0F0040ull;
+//DUPS: 2F0F0040,
+static const uint64_t P9N2_EX_7_NET_CTRL0_WAND = 0x2E0F0041ull;
+//DUPS: 2F0F0041,
+static const uint64_t P9N2_EX_7_NET_CTRL0_WOR = 0x2E0F0042ull;
+//DUPS: 2F0F0042,
+static const uint64_t P9N2_EX_8_NET_CTRL0 = 0x300F0040ull;
+//DUPS: 310F0040,
+static const uint64_t P9N2_EX_8_NET_CTRL0_WAND = 0x300F0041ull;
+//DUPS: 310F0041,
+static const uint64_t P9N2_EX_8_NET_CTRL0_WOR = 0x300F0042ull;
+//DUPS: 310F0042,
+static const uint64_t P9N2_EX_9_NET_CTRL0 = 0x320F0040ull;
+//DUPS: 330F0040,
+static const uint64_t P9N2_EX_9_NET_CTRL0_WAND = 0x320F0041ull;
+//DUPS: 330F0041,
+static const uint64_t P9N2_EX_9_NET_CTRL0_WOR = 0x320F0042ull;
+//DUPS: 330F0042,
+static const uint64_t P9N2_EX_10_NET_CTRL0 = 0x340F0040ull;
+//DUPS: 350F0040,
+static const uint64_t P9N2_EX_10_NET_CTRL0_WAND = 0x340F0041ull;
+//DUPS: 350F0041,
+static const uint64_t P9N2_EX_10_NET_CTRL0_WOR = 0x340F0042ull;
+//DUPS: 350F0042,
+static const uint64_t P9N2_EX_11_NET_CTRL0 = 0x360F0040ull;
+//DUPS: 370F0040,
+static const uint64_t P9N2_EX_11_NET_CTRL0_WAND = 0x360F0041ull;
+//DUPS: 370F0041,
+static const uint64_t P9N2_EX_11_NET_CTRL0_WOR = 0x360F0042ull;
+//DUPS: 370F0042,
+
+static const uint64_t P9N2_C_NET_CTRL1 = 0x200F0044ull;
+
+static const uint64_t P9N2_C_NET_CTRL1_WAND = 0x200F0045ull;
+
+static const uint64_t P9N2_C_NET_CTRL1_WOR = 0x200F0046ull;
+
+static const uint64_t P9N2_C_0_NET_CTRL1 = 0x200F0044ull;
+
+static const uint64_t P9N2_C_0_NET_CTRL1_WAND = 0x200F0045ull;
+
+static const uint64_t P9N2_C_0_NET_CTRL1_WOR = 0x200F0046ull;
+
+static const uint64_t P9N2_C_1_NET_CTRL1 = 0x210F0044ull;
+
+static const uint64_t P9N2_C_1_NET_CTRL1_WAND = 0x210F0045ull;
+
+static const uint64_t P9N2_C_1_NET_CTRL1_WOR = 0x210F0046ull;
+
+static const uint64_t P9N2_C_2_NET_CTRL1 = 0x220F0044ull;
+
+static const uint64_t P9N2_C_2_NET_CTRL1_WAND = 0x220F0045ull;
+
+static const uint64_t P9N2_C_2_NET_CTRL1_WOR = 0x220F0046ull;
+
+static const uint64_t P9N2_C_3_NET_CTRL1 = 0x230F0044ull;
+
+static const uint64_t P9N2_C_3_NET_CTRL1_WAND = 0x230F0045ull;
+
+static const uint64_t P9N2_C_3_NET_CTRL1_WOR = 0x230F0046ull;
+
+static const uint64_t P9N2_C_4_NET_CTRL1 = 0x240F0044ull;
+
+static const uint64_t P9N2_C_4_NET_CTRL1_WAND = 0x240F0045ull;
+
+static const uint64_t P9N2_C_4_NET_CTRL1_WOR = 0x240F0046ull;
+
+static const uint64_t P9N2_C_5_NET_CTRL1 = 0x250F0044ull;
+
+static const uint64_t P9N2_C_5_NET_CTRL1_WAND = 0x250F0045ull;
+
+static const uint64_t P9N2_C_5_NET_CTRL1_WOR = 0x250F0046ull;
+
+static const uint64_t P9N2_C_6_NET_CTRL1 = 0x260F0044ull;
+
+static const uint64_t P9N2_C_6_NET_CTRL1_WAND = 0x260F0045ull;
+
+static const uint64_t P9N2_C_6_NET_CTRL1_WOR = 0x260F0046ull;
+
+static const uint64_t P9N2_C_7_NET_CTRL1 = 0x270F0044ull;
+
+static const uint64_t P9N2_C_7_NET_CTRL1_WAND = 0x270F0045ull;
+
+static const uint64_t P9N2_C_7_NET_CTRL1_WOR = 0x270F0046ull;
+
+static const uint64_t P9N2_C_8_NET_CTRL1 = 0x280F0044ull;
+
+static const uint64_t P9N2_C_8_NET_CTRL1_WAND = 0x280F0045ull;
+
+static const uint64_t P9N2_C_8_NET_CTRL1_WOR = 0x280F0046ull;
+
+static const uint64_t P9N2_C_9_NET_CTRL1 = 0x290F0044ull;
+
+static const uint64_t P9N2_C_9_NET_CTRL1_WAND = 0x290F0045ull;
+
+static const uint64_t P9N2_C_9_NET_CTRL1_WOR = 0x290F0046ull;
+
+static const uint64_t P9N2_C_10_NET_CTRL1 = 0x2A0F0044ull;
+
+static const uint64_t P9N2_C_10_NET_CTRL1_WAND = 0x2A0F0045ull;
+
+static const uint64_t P9N2_C_10_NET_CTRL1_WOR = 0x2A0F0046ull;
+
+static const uint64_t P9N2_C_11_NET_CTRL1 = 0x2B0F0044ull;
+
+static const uint64_t P9N2_C_11_NET_CTRL1_WAND = 0x2B0F0045ull;
+
+static const uint64_t P9N2_C_11_NET_CTRL1_WOR = 0x2B0F0046ull;
+
+static const uint64_t P9N2_C_12_NET_CTRL1 = 0x2C0F0044ull;
+
+static const uint64_t P9N2_C_12_NET_CTRL1_WAND = 0x2C0F0045ull;
+
+static const uint64_t P9N2_C_12_NET_CTRL1_WOR = 0x2C0F0046ull;
+
+static const uint64_t P9N2_C_13_NET_CTRL1 = 0x2D0F0044ull;
+
+static const uint64_t P9N2_C_13_NET_CTRL1_WAND = 0x2D0F0045ull;
+
+static const uint64_t P9N2_C_13_NET_CTRL1_WOR = 0x2D0F0046ull;
+
+static const uint64_t P9N2_C_14_NET_CTRL1 = 0x2E0F0044ull;
+
+static const uint64_t P9N2_C_14_NET_CTRL1_WAND = 0x2E0F0045ull;
+
+static const uint64_t P9N2_C_14_NET_CTRL1_WOR = 0x2E0F0046ull;
+
+static const uint64_t P9N2_C_15_NET_CTRL1 = 0x2F0F0044ull;
+
+static const uint64_t P9N2_C_15_NET_CTRL1_WAND = 0x2F0F0045ull;
+
+static const uint64_t P9N2_C_15_NET_CTRL1_WOR = 0x2F0F0046ull;
+
+static const uint64_t P9N2_C_16_NET_CTRL1 = 0x300F0044ull;
+
+static const uint64_t P9N2_C_16_NET_CTRL1_WAND = 0x300F0045ull;
+
+static const uint64_t P9N2_C_16_NET_CTRL1_WOR = 0x300F0046ull;
+
+static const uint64_t P9N2_C_17_NET_CTRL1 = 0x310F0044ull;
+
+static const uint64_t P9N2_C_17_NET_CTRL1_WAND = 0x310F0045ull;
+
+static const uint64_t P9N2_C_17_NET_CTRL1_WOR = 0x310F0046ull;
+
+static const uint64_t P9N2_C_18_NET_CTRL1 = 0x320F0044ull;
+
+static const uint64_t P9N2_C_18_NET_CTRL1_WAND = 0x320F0045ull;
+
+static const uint64_t P9N2_C_18_NET_CTRL1_WOR = 0x320F0046ull;
+
+static const uint64_t P9N2_C_19_NET_CTRL1 = 0x330F0044ull;
+
+static const uint64_t P9N2_C_19_NET_CTRL1_WAND = 0x330F0045ull;
+
+static const uint64_t P9N2_C_19_NET_CTRL1_WOR = 0x330F0046ull;
+
+static const uint64_t P9N2_C_20_NET_CTRL1 = 0x340F0044ull;
+
+static const uint64_t P9N2_C_20_NET_CTRL1_WAND = 0x340F0045ull;
+
+static const uint64_t P9N2_C_20_NET_CTRL1_WOR = 0x340F0046ull;
+
+static const uint64_t P9N2_C_21_NET_CTRL1 = 0x350F0044ull;
+
+static const uint64_t P9N2_C_21_NET_CTRL1_WAND = 0x350F0045ull;
+
+static const uint64_t P9N2_C_21_NET_CTRL1_WOR = 0x350F0046ull;
+
+static const uint64_t P9N2_C_22_NET_CTRL1 = 0x360F0044ull;
+
+static const uint64_t P9N2_C_22_NET_CTRL1_WAND = 0x360F0045ull;
+
+static const uint64_t P9N2_C_22_NET_CTRL1_WOR = 0x360F0046ull;
+
+static const uint64_t P9N2_C_23_NET_CTRL1 = 0x370F0044ull;
+
+static const uint64_t P9N2_C_23_NET_CTRL1_WAND = 0x370F0045ull;
+
+static const uint64_t P9N2_C_23_NET_CTRL1_WOR = 0x370F0046ull;
+
+static const uint64_t P9N2_EQ_NET_CTRL1 = 0x100F0044ull;
+
+static const uint64_t P9N2_EQ_NET_CTRL1_WAND = 0x100F0045ull;
+
+static const uint64_t P9N2_EQ_NET_CTRL1_WOR = 0x100F0046ull;
+
+static const uint64_t P9N2_EQ_0_NET_CTRL1 = 0x100F0044ull;
+
+static const uint64_t P9N2_EQ_0_NET_CTRL1_WAND = 0x100F0045ull;
+
+static const uint64_t P9N2_EQ_0_NET_CTRL1_WOR = 0x100F0046ull;
+
+static const uint64_t P9N2_EQ_1_NET_CTRL1 = 0x110F0044ull;
+
+static const uint64_t P9N2_EQ_1_NET_CTRL1_WAND = 0x110F0045ull;
+
+static const uint64_t P9N2_EQ_1_NET_CTRL1_WOR = 0x110F0046ull;
+
+static const uint64_t P9N2_EQ_2_NET_CTRL1 = 0x120F0044ull;
+
+static const uint64_t P9N2_EQ_2_NET_CTRL1_WAND = 0x120F0045ull;
+
+static const uint64_t P9N2_EQ_2_NET_CTRL1_WOR = 0x120F0046ull;
+
+static const uint64_t P9N2_EQ_3_NET_CTRL1 = 0x130F0044ull;
+
+static const uint64_t P9N2_EQ_3_NET_CTRL1_WAND = 0x130F0045ull;
+
+static const uint64_t P9N2_EQ_3_NET_CTRL1_WOR = 0x130F0046ull;
+
+static const uint64_t P9N2_EQ_4_NET_CTRL1 = 0x140F0044ull;
+
+static const uint64_t P9N2_EQ_4_NET_CTRL1_WAND = 0x140F0045ull;
+
+static const uint64_t P9N2_EQ_4_NET_CTRL1_WOR = 0x140F0046ull;
+
+static const uint64_t P9N2_EQ_5_NET_CTRL1 = 0x150F0044ull;
+
+static const uint64_t P9N2_EQ_5_NET_CTRL1_WAND = 0x150F0045ull;
+
+static const uint64_t P9N2_EQ_5_NET_CTRL1_WOR = 0x150F0046ull;
+
+static const uint64_t P9N2_EX_NET_CTRL1 = 0x200F0044ull;
+//DUPS: 210F0044,
+static const uint64_t P9N2_EX_NET_CTRL1_WAND = 0x200F0045ull;
+//DUPS: 210F0045,
+static const uint64_t P9N2_EX_NET_CTRL1_WOR = 0x200F0046ull;
+//DUPS: 210F0046,
+static const uint64_t P9N2_EX_0_NET_CTRL1 = 0x200F0044ull;
+//DUPS: 210F0044,
+static const uint64_t P9N2_EX_0_NET_CTRL1_WAND = 0x200F0045ull;
+//DUPS: 210F0045,
+static const uint64_t P9N2_EX_0_NET_CTRL1_WOR = 0x200F0046ull;
+//DUPS: 210F0046,
+static const uint64_t P9N2_EX_1_NET_CTRL1 = 0x220F0044ull;
+//DUPS: 220F0044,
+static const uint64_t P9N2_EX_1_NET_CTRL1_WAND = 0x220F0045ull;
+//DUPS: 220F0045,
+static const uint64_t P9N2_EX_1_NET_CTRL1_WOR = 0x220F0046ull;
+//DUPS: 220F0046,
+static const uint64_t P9N2_EX_2_NET_CTRL1 = 0x240F0044ull;
+//DUPS: 250F0044,
+static const uint64_t P9N2_EX_2_NET_CTRL1_WAND = 0x240F0045ull;
+//DUPS: 250F0045,
+static const uint64_t P9N2_EX_2_NET_CTRL1_WOR = 0x240F0046ull;
+//DUPS: 250F0046,
+static const uint64_t P9N2_EX_3_NET_CTRL1 = 0x260F0044ull;
+//DUPS: 270F0044,
+static const uint64_t P9N2_EX_3_NET_CTRL1_WAND = 0x260F0045ull;
+//DUPS: 270F0045,
+static const uint64_t P9N2_EX_3_NET_CTRL1_WOR = 0x260F0046ull;
+//DUPS: 270F0046,
+static const uint64_t P9N2_EX_4_NET_CTRL1 = 0x280F0044ull;
+//DUPS: 290F0044,
+static const uint64_t P9N2_EX_4_NET_CTRL1_WAND = 0x280F0045ull;
+//DUPS: 290F0045,
+static const uint64_t P9N2_EX_4_NET_CTRL1_WOR = 0x280F0046ull;
+//DUPS: 290F0046,
+static const uint64_t P9N2_EX_5_NET_CTRL1 = 0x2A0F0044ull;
+//DUPS: 2B0F0044,
+static const uint64_t P9N2_EX_5_NET_CTRL1_WAND = 0x2A0F0045ull;
+//DUPS: 2B0F0045,
+static const uint64_t P9N2_EX_5_NET_CTRL1_WOR = 0x2A0F0046ull;
+//DUPS: 2B0F0046,
+static const uint64_t P9N2_EX_6_NET_CTRL1 = 0x2C0F0044ull;
+//DUPS: 2D0F0044,
+static const uint64_t P9N2_EX_6_NET_CTRL1_WAND = 0x2C0F0045ull;
+//DUPS: 2D0F0045,
+static const uint64_t P9N2_EX_6_NET_CTRL1_WOR = 0x2C0F0046ull;
+//DUPS: 2D0F0046,
+static const uint64_t P9N2_EX_7_NET_CTRL1 = 0x2E0F0044ull;
+//DUPS: 2F0F0044,
+static const uint64_t P9N2_EX_7_NET_CTRL1_WAND = 0x2E0F0045ull;
+//DUPS: 2F0F0045,
+static const uint64_t P9N2_EX_7_NET_CTRL1_WOR = 0x2E0F0046ull;
+//DUPS: 2F0F0046,
+static const uint64_t P9N2_EX_8_NET_CTRL1 = 0x300F0044ull;
+//DUPS: 310F0044,
+static const uint64_t P9N2_EX_8_NET_CTRL1_WAND = 0x300F0045ull;
+//DUPS: 310F0045,
+static const uint64_t P9N2_EX_8_NET_CTRL1_WOR = 0x300F0046ull;
+//DUPS: 310F0046,
+static const uint64_t P9N2_EX_9_NET_CTRL1 = 0x320F0044ull;
+//DUPS: 330F0044,
+static const uint64_t P9N2_EX_9_NET_CTRL1_WAND = 0x320F0045ull;
+//DUPS: 330F0045,
+static const uint64_t P9N2_EX_9_NET_CTRL1_WOR = 0x320F0046ull;
+//DUPS: 330F0046,
+static const uint64_t P9N2_EX_10_NET_CTRL1 = 0x340F0044ull;
+//DUPS: 350F0044,
+static const uint64_t P9N2_EX_10_NET_CTRL1_WAND = 0x340F0045ull;
+//DUPS: 350F0045,
+static const uint64_t P9N2_EX_10_NET_CTRL1_WOR = 0x340F0046ull;
+//DUPS: 350F0046,
+static const uint64_t P9N2_EX_11_NET_CTRL1 = 0x360F0044ull;
+//DUPS: 370F0044,
+static const uint64_t P9N2_EX_11_NET_CTRL1_WAND = 0x360F0045ull;
+//DUPS: 370F0045,
+static const uint64_t P9N2_EX_11_NET_CTRL1_WOR = 0x360F0046ull;
+//DUPS: 370F0046,
+
+static const uint64_t P9N2_C_OCC_SCOMC = 0x20010A82ull;
+
+static const uint64_t P9N2_C_0_OCC_SCOMC = 0x20010A82ull;
+
+static const uint64_t P9N2_C_1_OCC_SCOMC = 0x21010A82ull;
+
+static const uint64_t P9N2_C_2_OCC_SCOMC = 0x22010A82ull;
+
+static const uint64_t P9N2_C_3_OCC_SCOMC = 0x23010A82ull;
+
+static const uint64_t P9N2_C_4_OCC_SCOMC = 0x24010A82ull;
+
+static const uint64_t P9N2_C_5_OCC_SCOMC = 0x25010A82ull;
+
+static const uint64_t P9N2_C_6_OCC_SCOMC = 0x26010A82ull;
+
+static const uint64_t P9N2_C_7_OCC_SCOMC = 0x27010A82ull;
+
+static const uint64_t P9N2_C_8_OCC_SCOMC = 0x28010A82ull;
+
+static const uint64_t P9N2_C_9_OCC_SCOMC = 0x29010A82ull;
+
+static const uint64_t P9N2_C_10_OCC_SCOMC = 0x2A010A82ull;
+
+static const uint64_t P9N2_C_11_OCC_SCOMC = 0x2B010A82ull;
+
+static const uint64_t P9N2_C_12_OCC_SCOMC = 0x2C010A82ull;
+
+static const uint64_t P9N2_C_13_OCC_SCOMC = 0x2D010A82ull;
+
+static const uint64_t P9N2_C_14_OCC_SCOMC = 0x2E010A82ull;
+
+static const uint64_t P9N2_C_15_OCC_SCOMC = 0x2F010A82ull;
+
+static const uint64_t P9N2_C_16_OCC_SCOMC = 0x30010A82ull;
+
+static const uint64_t P9N2_C_17_OCC_SCOMC = 0x31010A82ull;
+
+static const uint64_t P9N2_C_18_OCC_SCOMC = 0x32010A82ull;
+
+static const uint64_t P9N2_C_19_OCC_SCOMC = 0x33010A82ull;
+
+static const uint64_t P9N2_C_20_OCC_SCOMC = 0x34010A82ull;
+
+static const uint64_t P9N2_C_21_OCC_SCOMC = 0x35010A82ull;
+
+static const uint64_t P9N2_C_22_OCC_SCOMC = 0x36010A82ull;
+
+static const uint64_t P9N2_C_23_OCC_SCOMC = 0x37010A82ull;
+
+static const uint64_t P9N2_EX_0_L2_OCC_SCOMC = 0x20010A82ull;
+//DUPS: 20010A82,
+static const uint64_t P9N2_EX_10_L2_OCC_SCOMC = 0x34010A82ull;
+//DUPS: 34010A82,
+static const uint64_t P9N2_EX_11_L2_OCC_SCOMC = 0x36010A82ull;
+//DUPS: 36010A82,
+static const uint64_t P9N2_EX_1_L2_OCC_SCOMC = 0x22010A82ull;
+//DUPS: 22010A82,
+static const uint64_t P9N2_EX_2_L2_OCC_SCOMC = 0x24010A82ull;
+//DUPS: 24010A82,
+static const uint64_t P9N2_EX_3_L2_OCC_SCOMC = 0x26010A82ull;
+//DUPS: 26010A82,
+static const uint64_t P9N2_EX_4_L2_OCC_SCOMC = 0x28010A82ull;
+//DUPS: 28010A82,
+static const uint64_t P9N2_EX_5_L2_OCC_SCOMC = 0x2B010A82ull;
+//DUPS: 2A010A82,
+static const uint64_t P9N2_EX_6_L2_OCC_SCOMC = 0x2D010A82ull;
+//DUPS: 2C010A82,
+static const uint64_t P9N2_EX_7_L2_OCC_SCOMC = 0x2F010A82ull;
+//DUPS: 2E010A82,
+static const uint64_t P9N2_EX_8_L2_OCC_SCOMC = 0x30010A82ull;
+//DUPS: 30010A82,
+static const uint64_t P9N2_EX_9_L2_OCC_SCOMC = 0x32010A82ull;
+//DUPS: 32010A82,
+static const uint64_t P9N2_EX_L2_OCC_SCOMC = 0x20010A82ull;
+//DUPS: 20010A82,
+
+static const uint64_t P9N2_C_OCC_SCOMD = 0x20010A83ull;
+
+static const uint64_t P9N2_C_0_OCC_SCOMD = 0x20010A83ull;
+
+static const uint64_t P9N2_C_1_OCC_SCOMD = 0x21010A83ull;
+
+static const uint64_t P9N2_C_2_OCC_SCOMD = 0x22010A83ull;
+
+static const uint64_t P9N2_C_3_OCC_SCOMD = 0x23010A83ull;
+
+static const uint64_t P9N2_C_4_OCC_SCOMD = 0x24010A83ull;
+
+static const uint64_t P9N2_C_5_OCC_SCOMD = 0x25010A83ull;
+
+static const uint64_t P9N2_C_6_OCC_SCOMD = 0x26010A83ull;
+
+static const uint64_t P9N2_C_7_OCC_SCOMD = 0x27010A83ull;
+
+static const uint64_t P9N2_C_8_OCC_SCOMD = 0x28010A83ull;
+
+static const uint64_t P9N2_C_9_OCC_SCOMD = 0x29010A83ull;
+
+static const uint64_t P9N2_C_10_OCC_SCOMD = 0x2A010A83ull;
+
+static const uint64_t P9N2_C_11_OCC_SCOMD = 0x2B010A83ull;
+
+static const uint64_t P9N2_C_12_OCC_SCOMD = 0x2C010A83ull;
+
+static const uint64_t P9N2_C_13_OCC_SCOMD = 0x2D010A83ull;
+
+static const uint64_t P9N2_C_14_OCC_SCOMD = 0x2E010A83ull;
+
+static const uint64_t P9N2_C_15_OCC_SCOMD = 0x2F010A83ull;
+
+static const uint64_t P9N2_C_16_OCC_SCOMD = 0x30010A83ull;
+
+static const uint64_t P9N2_C_17_OCC_SCOMD = 0x31010A83ull;
+
+static const uint64_t P9N2_C_18_OCC_SCOMD = 0x32010A83ull;
+
+static const uint64_t P9N2_C_19_OCC_SCOMD = 0x33010A83ull;
+
+static const uint64_t P9N2_C_20_OCC_SCOMD = 0x34010A83ull;
+
+static const uint64_t P9N2_C_21_OCC_SCOMD = 0x35010A83ull;
+
+static const uint64_t P9N2_C_22_OCC_SCOMD = 0x36010A83ull;
+
+static const uint64_t P9N2_C_23_OCC_SCOMD = 0x37010A83ull;
+
+static const uint64_t P9N2_EX_0_L2_OCC_SCOMD = 0x20010A83ull;
+//DUPS: 20010A83,
+static const uint64_t P9N2_EX_10_L2_OCC_SCOMD = 0x34010A83ull;
+//DUPS: 34010A83,
+static const uint64_t P9N2_EX_11_L2_OCC_SCOMD = 0x36010A83ull;
+//DUPS: 36010A83,
+static const uint64_t P9N2_EX_1_L2_OCC_SCOMD = 0x22010A83ull;
+//DUPS: 22010A83,
+static const uint64_t P9N2_EX_2_L2_OCC_SCOMD = 0x24010A83ull;
+//DUPS: 24010A83,
+static const uint64_t P9N2_EX_3_L2_OCC_SCOMD = 0x26010A83ull;
+//DUPS: 26010A83,
+static const uint64_t P9N2_EX_4_L2_OCC_SCOMD = 0x28010A83ull;
+//DUPS: 28010A83,
+static const uint64_t P9N2_EX_5_L2_OCC_SCOMD = 0x2B010A83ull;
+//DUPS: 2A010A83,
+static const uint64_t P9N2_EX_6_L2_OCC_SCOMD = 0x2D010A83ull;
+//DUPS: 2C010A83,
+static const uint64_t P9N2_EX_7_L2_OCC_SCOMD = 0x2F010A83ull;
+//DUPS: 2E010A83,
+static const uint64_t P9N2_EX_8_L2_OCC_SCOMD = 0x30010A83ull;
+//DUPS: 30010A83,
+static const uint64_t P9N2_EX_9_L2_OCC_SCOMD = 0x32010A83ull;
+//DUPS: 32010A83,
+static const uint64_t P9N2_EX_L2_OCC_SCOMD = 0x20010A83ull;
+//DUPS: 20010A83,
+
+static const uint64_t P9N2_C_OPCG_ALIGN = 0x20030001ull;
+
+static const uint64_t P9N2_C_0_OPCG_ALIGN = 0x20030001ull;
+
+static const uint64_t P9N2_C_1_OPCG_ALIGN = 0x21030001ull;
+
+static const uint64_t P9N2_C_2_OPCG_ALIGN = 0x22030001ull;
+
+static const uint64_t P9N2_C_3_OPCG_ALIGN = 0x23030001ull;
+
+static const uint64_t P9N2_C_4_OPCG_ALIGN = 0x24030001ull;
+
+static const uint64_t P9N2_C_5_OPCG_ALIGN = 0x25030001ull;
+
+static const uint64_t P9N2_C_6_OPCG_ALIGN = 0x26030001ull;
+
+static const uint64_t P9N2_C_7_OPCG_ALIGN = 0x27030001ull;
+
+static const uint64_t P9N2_C_8_OPCG_ALIGN = 0x28030001ull;
+
+static const uint64_t P9N2_C_9_OPCG_ALIGN = 0x29030001ull;
+
+static const uint64_t P9N2_C_10_OPCG_ALIGN = 0x2A030001ull;
+
+static const uint64_t P9N2_C_11_OPCG_ALIGN = 0x2B030001ull;
+
+static const uint64_t P9N2_C_12_OPCG_ALIGN = 0x2C030001ull;
+
+static const uint64_t P9N2_C_13_OPCG_ALIGN = 0x2D030001ull;
+
+static const uint64_t P9N2_C_14_OPCG_ALIGN = 0x2E030001ull;
+
+static const uint64_t P9N2_C_15_OPCG_ALIGN = 0x2F030001ull;
+
+static const uint64_t P9N2_C_16_OPCG_ALIGN = 0x30030001ull;
+
+static const uint64_t P9N2_C_17_OPCG_ALIGN = 0x31030001ull;
+
+static const uint64_t P9N2_C_18_OPCG_ALIGN = 0x32030001ull;
+
+static const uint64_t P9N2_C_19_OPCG_ALIGN = 0x33030001ull;
+
+static const uint64_t P9N2_C_20_OPCG_ALIGN = 0x34030001ull;
+
+static const uint64_t P9N2_C_21_OPCG_ALIGN = 0x35030001ull;
+
+static const uint64_t P9N2_C_22_OPCG_ALIGN = 0x36030001ull;
+
+static const uint64_t P9N2_C_23_OPCG_ALIGN = 0x37030001ull;
+
+static const uint64_t P9N2_EQ_OPCG_ALIGN = 0x10030001ull;
+
+static const uint64_t P9N2_EQ_0_OPCG_ALIGN = 0x10030001ull;
+
+static const uint64_t P9N2_EQ_1_OPCG_ALIGN = 0x11030001ull;
+
+static const uint64_t P9N2_EQ_2_OPCG_ALIGN = 0x12030001ull;
+
+static const uint64_t P9N2_EQ_3_OPCG_ALIGN = 0x13030001ull;
+
+static const uint64_t P9N2_EQ_4_OPCG_ALIGN = 0x14030001ull;
+
+static const uint64_t P9N2_EQ_5_OPCG_ALIGN = 0x15030001ull;
+
+static const uint64_t P9N2_EX_OPCG_ALIGN = 0x20030001ull;
+//DUPS: 21030001,
+static const uint64_t P9N2_EX_0_OPCG_ALIGN = 0x20030001ull;
+//DUPS: 21030001,
+static const uint64_t P9N2_EX_1_OPCG_ALIGN = 0x22030001ull;
+//DUPS: 23030001,
+static const uint64_t P9N2_EX_2_OPCG_ALIGN = 0x24030001ull;
+//DUPS: 25030001,
+static const uint64_t P9N2_EX_3_OPCG_ALIGN = 0x26030001ull;
+//DUPS: 27030001,
+static const uint64_t P9N2_EX_4_OPCG_ALIGN = 0x28030001ull;
+//DUPS: 29030001,
+static const uint64_t P9N2_EX_5_OPCG_ALIGN = 0x2A030001ull;
+//DUPS: 2B030001,
+static const uint64_t P9N2_EX_6_OPCG_ALIGN = 0x2C030001ull;
+//DUPS: 2D030001,
+static const uint64_t P9N2_EX_7_OPCG_ALIGN = 0x2F030001ull;
+//DUPS: 2F030001,
+static const uint64_t P9N2_EX_8_OPCG_ALIGN = 0x30030001ull;
+//DUPS: 31030001,
+static const uint64_t P9N2_EX_9_OPCG_ALIGN = 0x32030001ull;
+//DUPS: 33030001,
+static const uint64_t P9N2_EX_10_OPCG_ALIGN = 0x34030001ull;
+//DUPS: 35030001,
+static const uint64_t P9N2_EX_11_OPCG_ALIGN = 0x36030001ull;
+//DUPS: 37030001,
+
+static const uint64_t P9N2_C_OPCG_CAPT1 = 0x20030010ull;
+
+static const uint64_t P9N2_C_0_OPCG_CAPT1 = 0x20030010ull;
+
+static const uint64_t P9N2_C_1_OPCG_CAPT1 = 0x21030010ull;
+
+static const uint64_t P9N2_C_2_OPCG_CAPT1 = 0x22030010ull;
+
+static const uint64_t P9N2_C_3_OPCG_CAPT1 = 0x23030010ull;
+
+static const uint64_t P9N2_C_4_OPCG_CAPT1 = 0x24030010ull;
+
+static const uint64_t P9N2_C_5_OPCG_CAPT1 = 0x25030010ull;
+
+static const uint64_t P9N2_C_6_OPCG_CAPT1 = 0x26030010ull;
+
+static const uint64_t P9N2_C_7_OPCG_CAPT1 = 0x27030010ull;
+
+static const uint64_t P9N2_C_8_OPCG_CAPT1 = 0x28030010ull;
+
+static const uint64_t P9N2_C_9_OPCG_CAPT1 = 0x29030010ull;
+
+static const uint64_t P9N2_C_10_OPCG_CAPT1 = 0x2A030010ull;
+
+static const uint64_t P9N2_C_11_OPCG_CAPT1 = 0x2B030010ull;
+
+static const uint64_t P9N2_C_12_OPCG_CAPT1 = 0x2C030010ull;
+
+static const uint64_t P9N2_C_13_OPCG_CAPT1 = 0x2D030010ull;
+
+static const uint64_t P9N2_C_14_OPCG_CAPT1 = 0x2E030010ull;
+
+static const uint64_t P9N2_C_15_OPCG_CAPT1 = 0x2F030010ull;
+
+static const uint64_t P9N2_C_16_OPCG_CAPT1 = 0x30030010ull;
+
+static const uint64_t P9N2_C_17_OPCG_CAPT1 = 0x31030010ull;
+
+static const uint64_t P9N2_C_18_OPCG_CAPT1 = 0x32030010ull;
+
+static const uint64_t P9N2_C_19_OPCG_CAPT1 = 0x33030010ull;
+
+static const uint64_t P9N2_C_20_OPCG_CAPT1 = 0x34030010ull;
+
+static const uint64_t P9N2_C_21_OPCG_CAPT1 = 0x35030010ull;
+
+static const uint64_t P9N2_C_22_OPCG_CAPT1 = 0x36030010ull;
+
+static const uint64_t P9N2_C_23_OPCG_CAPT1 = 0x37030010ull;
+
+static const uint64_t P9N2_EQ_OPCG_CAPT1 = 0x10030010ull;
+
+static const uint64_t P9N2_EQ_0_OPCG_CAPT1 = 0x10030010ull;
+
+static const uint64_t P9N2_EQ_1_OPCG_CAPT1 = 0x11030010ull;
+
+static const uint64_t P9N2_EQ_2_OPCG_CAPT1 = 0x12030010ull;
+
+static const uint64_t P9N2_EQ_3_OPCG_CAPT1 = 0x13030010ull;
+
+static const uint64_t P9N2_EQ_4_OPCG_CAPT1 = 0x14030010ull;
+
+static const uint64_t P9N2_EQ_5_OPCG_CAPT1 = 0x15030010ull;
+
+static const uint64_t P9N2_EX_OPCG_CAPT1 = 0x20030010ull;
+//DUPS: 21030010,
+static const uint64_t P9N2_EX_0_OPCG_CAPT1 = 0x20030010ull;
+//DUPS: 21030010,
+static const uint64_t P9N2_EX_1_OPCG_CAPT1 = 0x22030010ull;
+//DUPS: 23030010,
+static const uint64_t P9N2_EX_2_OPCG_CAPT1 = 0x24030010ull;
+//DUPS: 25030010,
+static const uint64_t P9N2_EX_3_OPCG_CAPT1 = 0x26030010ull;
+//DUPS: 27030010,
+static const uint64_t P9N2_EX_4_OPCG_CAPT1 = 0x28030010ull;
+//DUPS: 29030010,
+static const uint64_t P9N2_EX_5_OPCG_CAPT1 = 0x2A030010ull;
+//DUPS: 2B030010,
+static const uint64_t P9N2_EX_6_OPCG_CAPT1 = 0x2C030010ull;
+//DUPS: 2D030010,
+static const uint64_t P9N2_EX_7_OPCG_CAPT1 = 0x2F030010ull;
+//DUPS: 2F030010,
+static const uint64_t P9N2_EX_8_OPCG_CAPT1 = 0x30030010ull;
+//DUPS: 31030010,
+static const uint64_t P9N2_EX_9_OPCG_CAPT1 = 0x32030010ull;
+//DUPS: 33030010,
+static const uint64_t P9N2_EX_10_OPCG_CAPT1 = 0x34030010ull;
+//DUPS: 35030010,
+static const uint64_t P9N2_EX_11_OPCG_CAPT1 = 0x36030010ull;
+//DUPS: 37030010,
+
+static const uint64_t P9N2_C_OPCG_CAPT2 = 0x20030011ull;
+
+static const uint64_t P9N2_C_0_OPCG_CAPT2 = 0x20030011ull;
+
+static const uint64_t P9N2_C_1_OPCG_CAPT2 = 0x21030011ull;
+
+static const uint64_t P9N2_C_2_OPCG_CAPT2 = 0x22030011ull;
+
+static const uint64_t P9N2_C_3_OPCG_CAPT2 = 0x23030011ull;
+
+static const uint64_t P9N2_C_4_OPCG_CAPT2 = 0x24030011ull;
+
+static const uint64_t P9N2_C_5_OPCG_CAPT2 = 0x25030011ull;
+
+static const uint64_t P9N2_C_6_OPCG_CAPT2 = 0x26030011ull;
+
+static const uint64_t P9N2_C_7_OPCG_CAPT2 = 0x27030011ull;
+
+static const uint64_t P9N2_C_8_OPCG_CAPT2 = 0x28030011ull;
+
+static const uint64_t P9N2_C_9_OPCG_CAPT2 = 0x29030011ull;
+
+static const uint64_t P9N2_C_10_OPCG_CAPT2 = 0x2A030011ull;
+
+static const uint64_t P9N2_C_11_OPCG_CAPT2 = 0x2B030011ull;
+
+static const uint64_t P9N2_C_12_OPCG_CAPT2 = 0x2C030011ull;
+
+static const uint64_t P9N2_C_13_OPCG_CAPT2 = 0x2D030011ull;
+
+static const uint64_t P9N2_C_14_OPCG_CAPT2 = 0x2E030011ull;
+
+static const uint64_t P9N2_C_15_OPCG_CAPT2 = 0x2F030011ull;
+
+static const uint64_t P9N2_C_16_OPCG_CAPT2 = 0x30030011ull;
+
+static const uint64_t P9N2_C_17_OPCG_CAPT2 = 0x31030011ull;
+
+static const uint64_t P9N2_C_18_OPCG_CAPT2 = 0x32030011ull;
+
+static const uint64_t P9N2_C_19_OPCG_CAPT2 = 0x33030011ull;
+
+static const uint64_t P9N2_C_20_OPCG_CAPT2 = 0x34030011ull;
+
+static const uint64_t P9N2_C_21_OPCG_CAPT2 = 0x35030011ull;
+
+static const uint64_t P9N2_C_22_OPCG_CAPT2 = 0x36030011ull;
+
+static const uint64_t P9N2_C_23_OPCG_CAPT2 = 0x37030011ull;
+
+static const uint64_t P9N2_EQ_OPCG_CAPT2 = 0x10030011ull;
+
+static const uint64_t P9N2_EQ_0_OPCG_CAPT2 = 0x10030011ull;
+
+static const uint64_t P9N2_EQ_1_OPCG_CAPT2 = 0x11030011ull;
+
+static const uint64_t P9N2_EQ_2_OPCG_CAPT2 = 0x12030011ull;
+
+static const uint64_t P9N2_EQ_3_OPCG_CAPT2 = 0x13030011ull;
+
+static const uint64_t P9N2_EQ_4_OPCG_CAPT2 = 0x14030011ull;
+
+static const uint64_t P9N2_EQ_5_OPCG_CAPT2 = 0x15030011ull;
+
+static const uint64_t P9N2_EX_OPCG_CAPT2 = 0x20030011ull;
+//DUPS: 21030011,
+static const uint64_t P9N2_EX_0_OPCG_CAPT2 = 0x20030011ull;
+//DUPS: 21030011,
+static const uint64_t P9N2_EX_1_OPCG_CAPT2 = 0x22030011ull;
+//DUPS: 23030011,
+static const uint64_t P9N2_EX_2_OPCG_CAPT2 = 0x24030011ull;
+//DUPS: 25030011,
+static const uint64_t P9N2_EX_3_OPCG_CAPT2 = 0x26030011ull;
+//DUPS: 27030011,
+static const uint64_t P9N2_EX_4_OPCG_CAPT2 = 0x28030011ull;
+//DUPS: 29030011,
+static const uint64_t P9N2_EX_5_OPCG_CAPT2 = 0x2A030011ull;
+//DUPS: 2B030011,
+static const uint64_t P9N2_EX_6_OPCG_CAPT2 = 0x2C030011ull;
+//DUPS: 2D030011,
+static const uint64_t P9N2_EX_7_OPCG_CAPT2 = 0x2F030011ull;
+//DUPS: 2F030011,
+static const uint64_t P9N2_EX_8_OPCG_CAPT2 = 0x30030011ull;
+//DUPS: 31030011,
+static const uint64_t P9N2_EX_9_OPCG_CAPT2 = 0x32030011ull;
+//DUPS: 33030011,
+static const uint64_t P9N2_EX_10_OPCG_CAPT2 = 0x34030011ull;
+//DUPS: 35030011,
+static const uint64_t P9N2_EX_11_OPCG_CAPT2 = 0x36030011ull;
+//DUPS: 37030011,
+
+static const uint64_t P9N2_C_OPCG_CAPT3 = 0x20030012ull;
+
+static const uint64_t P9N2_C_0_OPCG_CAPT3 = 0x20030012ull;
+
+static const uint64_t P9N2_C_1_OPCG_CAPT3 = 0x21030012ull;
+
+static const uint64_t P9N2_C_2_OPCG_CAPT3 = 0x22030012ull;
+
+static const uint64_t P9N2_C_3_OPCG_CAPT3 = 0x23030012ull;
+
+static const uint64_t P9N2_C_4_OPCG_CAPT3 = 0x24030012ull;
+
+static const uint64_t P9N2_C_5_OPCG_CAPT3 = 0x25030012ull;
+
+static const uint64_t P9N2_C_6_OPCG_CAPT3 = 0x26030012ull;
+
+static const uint64_t P9N2_C_7_OPCG_CAPT3 = 0x27030012ull;
+
+static const uint64_t P9N2_C_8_OPCG_CAPT3 = 0x28030012ull;
+
+static const uint64_t P9N2_C_9_OPCG_CAPT3 = 0x29030012ull;
+
+static const uint64_t P9N2_C_10_OPCG_CAPT3 = 0x2A030012ull;
+
+static const uint64_t P9N2_C_11_OPCG_CAPT3 = 0x2B030012ull;
+
+static const uint64_t P9N2_C_12_OPCG_CAPT3 = 0x2C030012ull;
+
+static const uint64_t P9N2_C_13_OPCG_CAPT3 = 0x2D030012ull;
+
+static const uint64_t P9N2_C_14_OPCG_CAPT3 = 0x2E030012ull;
+
+static const uint64_t P9N2_C_15_OPCG_CAPT3 = 0x2F030012ull;
+
+static const uint64_t P9N2_C_16_OPCG_CAPT3 = 0x30030012ull;
+
+static const uint64_t P9N2_C_17_OPCG_CAPT3 = 0x31030012ull;
+
+static const uint64_t P9N2_C_18_OPCG_CAPT3 = 0x32030012ull;
+
+static const uint64_t P9N2_C_19_OPCG_CAPT3 = 0x33030012ull;
+
+static const uint64_t P9N2_C_20_OPCG_CAPT3 = 0x34030012ull;
+
+static const uint64_t P9N2_C_21_OPCG_CAPT3 = 0x35030012ull;
+
+static const uint64_t P9N2_C_22_OPCG_CAPT3 = 0x36030012ull;
+
+static const uint64_t P9N2_C_23_OPCG_CAPT3 = 0x37030012ull;
+
+static const uint64_t P9N2_EQ_OPCG_CAPT3 = 0x10030012ull;
+
+static const uint64_t P9N2_EQ_0_OPCG_CAPT3 = 0x10030012ull;
+
+static const uint64_t P9N2_EQ_1_OPCG_CAPT3 = 0x11030012ull;
+
+static const uint64_t P9N2_EQ_2_OPCG_CAPT3 = 0x12030012ull;
+
+static const uint64_t P9N2_EQ_3_OPCG_CAPT3 = 0x13030012ull;
+
+static const uint64_t P9N2_EQ_4_OPCG_CAPT3 = 0x14030012ull;
+
+static const uint64_t P9N2_EQ_5_OPCG_CAPT3 = 0x15030012ull;
+
+static const uint64_t P9N2_EX_OPCG_CAPT3 = 0x20030012ull;
+//DUPS: 21030012,
+static const uint64_t P9N2_EX_0_OPCG_CAPT3 = 0x20030012ull;
+//DUPS: 21030012,
+static const uint64_t P9N2_EX_1_OPCG_CAPT3 = 0x22030012ull;
+//DUPS: 23030012,
+static const uint64_t P9N2_EX_2_OPCG_CAPT3 = 0x24030012ull;
+//DUPS: 25030012,
+static const uint64_t P9N2_EX_3_OPCG_CAPT3 = 0x26030012ull;
+//DUPS: 27030012,
+static const uint64_t P9N2_EX_4_OPCG_CAPT3 = 0x28030012ull;
+//DUPS: 29030012,
+static const uint64_t P9N2_EX_5_OPCG_CAPT3 = 0x2A030012ull;
+//DUPS: 2B030012,
+static const uint64_t P9N2_EX_6_OPCG_CAPT3 = 0x2C030012ull;
+//DUPS: 2D030012,
+static const uint64_t P9N2_EX_7_OPCG_CAPT3 = 0x2F030012ull;
+//DUPS: 2F030012,
+static const uint64_t P9N2_EX_8_OPCG_CAPT3 = 0x30030012ull;
+//DUPS: 31030012,
+static const uint64_t P9N2_EX_9_OPCG_CAPT3 = 0x32030012ull;
+//DUPS: 33030012,
+static const uint64_t P9N2_EX_10_OPCG_CAPT3 = 0x34030012ull;
+//DUPS: 35030012,
+static const uint64_t P9N2_EX_11_OPCG_CAPT3 = 0x36030012ull;
+//DUPS: 37030012,
+
+static const uint64_t P9N2_C_OPCG_REG0 = 0x20030002ull;
+
+static const uint64_t P9N2_C_0_OPCG_REG0 = 0x20030002ull;
+
+static const uint64_t P9N2_C_1_OPCG_REG0 = 0x21030002ull;
+
+static const uint64_t P9N2_C_2_OPCG_REG0 = 0x22030002ull;
+
+static const uint64_t P9N2_C_3_OPCG_REG0 = 0x23030002ull;
+
+static const uint64_t P9N2_C_4_OPCG_REG0 = 0x24030002ull;
+
+static const uint64_t P9N2_C_5_OPCG_REG0 = 0x25030002ull;
+
+static const uint64_t P9N2_C_6_OPCG_REG0 = 0x26030002ull;
+
+static const uint64_t P9N2_C_7_OPCG_REG0 = 0x27030002ull;
+
+static const uint64_t P9N2_C_8_OPCG_REG0 = 0x28030002ull;
+
+static const uint64_t P9N2_C_9_OPCG_REG0 = 0x29030002ull;
+
+static const uint64_t P9N2_C_10_OPCG_REG0 = 0x2A030002ull;
+
+static const uint64_t P9N2_C_11_OPCG_REG0 = 0x2B030002ull;
+
+static const uint64_t P9N2_C_12_OPCG_REG0 = 0x2C030002ull;
+
+static const uint64_t P9N2_C_13_OPCG_REG0 = 0x2D030002ull;
+
+static const uint64_t P9N2_C_14_OPCG_REG0 = 0x2E030002ull;
+
+static const uint64_t P9N2_C_15_OPCG_REG0 = 0x2F030002ull;
+
+static const uint64_t P9N2_C_16_OPCG_REG0 = 0x30030002ull;
+
+static const uint64_t P9N2_C_17_OPCG_REG0 = 0x31030002ull;
+
+static const uint64_t P9N2_C_18_OPCG_REG0 = 0x32030002ull;
+
+static const uint64_t P9N2_C_19_OPCG_REG0 = 0x33030002ull;
+
+static const uint64_t P9N2_C_20_OPCG_REG0 = 0x34030002ull;
+
+static const uint64_t P9N2_C_21_OPCG_REG0 = 0x35030002ull;
+
+static const uint64_t P9N2_C_22_OPCG_REG0 = 0x36030002ull;
+
+static const uint64_t P9N2_C_23_OPCG_REG0 = 0x37030002ull;
+
+static const uint64_t P9N2_EQ_OPCG_REG0 = 0x10030002ull;
+
+static const uint64_t P9N2_EQ_0_OPCG_REG0 = 0x10030002ull;
+
+static const uint64_t P9N2_EQ_1_OPCG_REG0 = 0x11030002ull;
+
+static const uint64_t P9N2_EQ_2_OPCG_REG0 = 0x12030002ull;
+
+static const uint64_t P9N2_EQ_3_OPCG_REG0 = 0x13030002ull;
+
+static const uint64_t P9N2_EQ_4_OPCG_REG0 = 0x14030002ull;
+
+static const uint64_t P9N2_EQ_5_OPCG_REG0 = 0x15030002ull;
+
+static const uint64_t P9N2_EX_OPCG_REG0 = 0x20030002ull;
+//DUPS: 21030002,
+static const uint64_t P9N2_EX_0_OPCG_REG0 = 0x20030002ull;
+//DUPS: 21030002,
+static const uint64_t P9N2_EX_1_OPCG_REG0 = 0x22030002ull;
+//DUPS: 23030002,
+static const uint64_t P9N2_EX_2_OPCG_REG0 = 0x24030002ull;
+//DUPS: 25030002,
+static const uint64_t P9N2_EX_3_OPCG_REG0 = 0x26030002ull;
+//DUPS: 27030002,
+static const uint64_t P9N2_EX_4_OPCG_REG0 = 0x28030002ull;
+//DUPS: 29030002,
+static const uint64_t P9N2_EX_5_OPCG_REG0 = 0x2A030002ull;
+//DUPS: 2B030002,
+static const uint64_t P9N2_EX_6_OPCG_REG0 = 0x2C030002ull;
+//DUPS: 2D030002,
+static const uint64_t P9N2_EX_7_OPCG_REG0 = 0x2F030002ull;
+//DUPS: 2F030002,
+static const uint64_t P9N2_EX_8_OPCG_REG0 = 0x30030002ull;
+//DUPS: 31030002,
+static const uint64_t P9N2_EX_9_OPCG_REG0 = 0x32030002ull;
+//DUPS: 33030002,
+static const uint64_t P9N2_EX_10_OPCG_REG0 = 0x34030002ull;
+//DUPS: 35030002,
+static const uint64_t P9N2_EX_11_OPCG_REG0 = 0x36030002ull;
+//DUPS: 37030002,
+
+static const uint64_t P9N2_C_OPCG_REG1 = 0x20030003ull;
+
+static const uint64_t P9N2_C_0_OPCG_REG1 = 0x20030003ull;
+
+static const uint64_t P9N2_C_1_OPCG_REG1 = 0x21030003ull;
+
+static const uint64_t P9N2_C_2_OPCG_REG1 = 0x22030003ull;
+
+static const uint64_t P9N2_C_3_OPCG_REG1 = 0x23030003ull;
+
+static const uint64_t P9N2_C_4_OPCG_REG1 = 0x24030003ull;
+
+static const uint64_t P9N2_C_5_OPCG_REG1 = 0x25030003ull;
+
+static const uint64_t P9N2_C_6_OPCG_REG1 = 0x26030003ull;
+
+static const uint64_t P9N2_C_7_OPCG_REG1 = 0x27030003ull;
+
+static const uint64_t P9N2_C_8_OPCG_REG1 = 0x28030003ull;
+
+static const uint64_t P9N2_C_9_OPCG_REG1 = 0x29030003ull;
+
+static const uint64_t P9N2_C_10_OPCG_REG1 = 0x2A030003ull;
+
+static const uint64_t P9N2_C_11_OPCG_REG1 = 0x2B030003ull;
+
+static const uint64_t P9N2_C_12_OPCG_REG1 = 0x2C030003ull;
+
+static const uint64_t P9N2_C_13_OPCG_REG1 = 0x2D030003ull;
+
+static const uint64_t P9N2_C_14_OPCG_REG1 = 0x2E030003ull;
+
+static const uint64_t P9N2_C_15_OPCG_REG1 = 0x2F030003ull;
+
+static const uint64_t P9N2_C_16_OPCG_REG1 = 0x30030003ull;
+
+static const uint64_t P9N2_C_17_OPCG_REG1 = 0x31030003ull;
+
+static const uint64_t P9N2_C_18_OPCG_REG1 = 0x32030003ull;
+
+static const uint64_t P9N2_C_19_OPCG_REG1 = 0x33030003ull;
+
+static const uint64_t P9N2_C_20_OPCG_REG1 = 0x34030003ull;
+
+static const uint64_t P9N2_C_21_OPCG_REG1 = 0x35030003ull;
+
+static const uint64_t P9N2_C_22_OPCG_REG1 = 0x36030003ull;
+
+static const uint64_t P9N2_C_23_OPCG_REG1 = 0x37030003ull;
+
+static const uint64_t P9N2_EQ_OPCG_REG1 = 0x10030003ull;
+
+static const uint64_t P9N2_EQ_0_OPCG_REG1 = 0x10030003ull;
+
+static const uint64_t P9N2_EQ_1_OPCG_REG1 = 0x11030003ull;
+
+static const uint64_t P9N2_EQ_2_OPCG_REG1 = 0x12030003ull;
+
+static const uint64_t P9N2_EQ_3_OPCG_REG1 = 0x13030003ull;
+
+static const uint64_t P9N2_EQ_4_OPCG_REG1 = 0x14030003ull;
+
+static const uint64_t P9N2_EQ_5_OPCG_REG1 = 0x15030003ull;
+
+static const uint64_t P9N2_EX_OPCG_REG1 = 0x20030003ull;
+//DUPS: 21030003,
+static const uint64_t P9N2_EX_0_OPCG_REG1 = 0x20030003ull;
+//DUPS: 21030003,
+static const uint64_t P9N2_EX_1_OPCG_REG1 = 0x22030003ull;
+//DUPS: 23030003,
+static const uint64_t P9N2_EX_2_OPCG_REG1 = 0x24030003ull;
+//DUPS: 25030003,
+static const uint64_t P9N2_EX_3_OPCG_REG1 = 0x26030003ull;
+//DUPS: 27030003,
+static const uint64_t P9N2_EX_4_OPCG_REG1 = 0x28030003ull;
+//DUPS: 29030003,
+static const uint64_t P9N2_EX_5_OPCG_REG1 = 0x2A030003ull;
+//DUPS: 2B030003,
+static const uint64_t P9N2_EX_6_OPCG_REG1 = 0x2C030003ull;
+//DUPS: 2D030003,
+static const uint64_t P9N2_EX_7_OPCG_REG1 = 0x2F030003ull;
+//DUPS: 2F030003,
+static const uint64_t P9N2_EX_8_OPCG_REG1 = 0x30030003ull;
+//DUPS: 31030003,
+static const uint64_t P9N2_EX_9_OPCG_REG1 = 0x32030003ull;
+//DUPS: 33030003,
+static const uint64_t P9N2_EX_10_OPCG_REG1 = 0x34030003ull;
+//DUPS: 35030003,
+static const uint64_t P9N2_EX_11_OPCG_REG1 = 0x36030003ull;
+//DUPS: 37030003,
+
+static const uint64_t P9N2_C_OPCG_REG2 = 0x20030004ull;
+
+static const uint64_t P9N2_C_0_OPCG_REG2 = 0x20030004ull;
+
+static const uint64_t P9N2_C_1_OPCG_REG2 = 0x21030004ull;
+
+static const uint64_t P9N2_C_2_OPCG_REG2 = 0x22030004ull;
+
+static const uint64_t P9N2_C_3_OPCG_REG2 = 0x23030004ull;
+
+static const uint64_t P9N2_C_4_OPCG_REG2 = 0x24030004ull;
+
+static const uint64_t P9N2_C_5_OPCG_REG2 = 0x25030004ull;
+
+static const uint64_t P9N2_C_6_OPCG_REG2 = 0x26030004ull;
+
+static const uint64_t P9N2_C_7_OPCG_REG2 = 0x27030004ull;
+
+static const uint64_t P9N2_C_8_OPCG_REG2 = 0x28030004ull;
+
+static const uint64_t P9N2_C_9_OPCG_REG2 = 0x29030004ull;
+
+static const uint64_t P9N2_C_10_OPCG_REG2 = 0x2A030004ull;
+
+static const uint64_t P9N2_C_11_OPCG_REG2 = 0x2B030004ull;
+
+static const uint64_t P9N2_C_12_OPCG_REG2 = 0x2C030004ull;
+
+static const uint64_t P9N2_C_13_OPCG_REG2 = 0x2D030004ull;
+
+static const uint64_t P9N2_C_14_OPCG_REG2 = 0x2E030004ull;
+
+static const uint64_t P9N2_C_15_OPCG_REG2 = 0x2F030004ull;
+
+static const uint64_t P9N2_C_16_OPCG_REG2 = 0x30030004ull;
+
+static const uint64_t P9N2_C_17_OPCG_REG2 = 0x31030004ull;
+
+static const uint64_t P9N2_C_18_OPCG_REG2 = 0x32030004ull;
+
+static const uint64_t P9N2_C_19_OPCG_REG2 = 0x33030004ull;
+
+static const uint64_t P9N2_C_20_OPCG_REG2 = 0x34030004ull;
+
+static const uint64_t P9N2_C_21_OPCG_REG2 = 0x35030004ull;
+
+static const uint64_t P9N2_C_22_OPCG_REG2 = 0x36030004ull;
+
+static const uint64_t P9N2_C_23_OPCG_REG2 = 0x37030004ull;
+
+static const uint64_t P9N2_EQ_OPCG_REG2 = 0x10030004ull;
+
+static const uint64_t P9N2_EQ_0_OPCG_REG2 = 0x10030004ull;
+
+static const uint64_t P9N2_EQ_1_OPCG_REG2 = 0x11030004ull;
+
+static const uint64_t P9N2_EQ_2_OPCG_REG2 = 0x12030004ull;
+
+static const uint64_t P9N2_EQ_3_OPCG_REG2 = 0x13030004ull;
+
+static const uint64_t P9N2_EQ_4_OPCG_REG2 = 0x14030004ull;
+
+static const uint64_t P9N2_EQ_5_OPCG_REG2 = 0x15030004ull;
+
+static const uint64_t P9N2_EX_OPCG_REG2 = 0x20030004ull;
+//DUPS: 21030004,
+static const uint64_t P9N2_EX_0_OPCG_REG2 = 0x20030004ull;
+//DUPS: 21030004,
+static const uint64_t P9N2_EX_1_OPCG_REG2 = 0x22030004ull;
+//DUPS: 23030004,
+static const uint64_t P9N2_EX_2_OPCG_REG2 = 0x24030004ull;
+//DUPS: 25030004,
+static const uint64_t P9N2_EX_3_OPCG_REG2 = 0x26030004ull;
+//DUPS: 27030004,
+static const uint64_t P9N2_EX_4_OPCG_REG2 = 0x28030004ull;
+//DUPS: 29030004,
+static const uint64_t P9N2_EX_5_OPCG_REG2 = 0x2A030004ull;
+//DUPS: 2B030004,
+static const uint64_t P9N2_EX_6_OPCG_REG2 = 0x2C030004ull;
+//DUPS: 2D030004,
+static const uint64_t P9N2_EX_7_OPCG_REG2 = 0x2F030004ull;
+//DUPS: 2F030004,
+static const uint64_t P9N2_EX_8_OPCG_REG2 = 0x30030004ull;
+//DUPS: 31030004,
+static const uint64_t P9N2_EX_9_OPCG_REG2 = 0x32030004ull;
+//DUPS: 33030004,
+static const uint64_t P9N2_EX_10_OPCG_REG2 = 0x34030004ull;
+//DUPS: 35030004,
+static const uint64_t P9N2_EX_11_OPCG_REG2 = 0x36030004ull;
+//DUPS: 37030004,
+
+static const uint64_t P9N2_C_PCB_OPCG_GO = 0x20030020ull;
+
+static const uint64_t P9N2_C_0_PCB_OPCG_GO = 0x20030020ull;
+
+static const uint64_t P9N2_C_1_PCB_OPCG_GO = 0x21030020ull;
+
+static const uint64_t P9N2_C_2_PCB_OPCG_GO = 0x22030020ull;
+
+static const uint64_t P9N2_C_3_PCB_OPCG_GO = 0x23030020ull;
+
+static const uint64_t P9N2_C_4_PCB_OPCG_GO = 0x24030020ull;
+
+static const uint64_t P9N2_C_5_PCB_OPCG_GO = 0x25030020ull;
+
+static const uint64_t P9N2_C_6_PCB_OPCG_GO = 0x26030020ull;
+
+static const uint64_t P9N2_C_7_PCB_OPCG_GO = 0x27030020ull;
+
+static const uint64_t P9N2_C_8_PCB_OPCG_GO = 0x28030020ull;
+
+static const uint64_t P9N2_C_9_PCB_OPCG_GO = 0x29030020ull;
+
+static const uint64_t P9N2_C_10_PCB_OPCG_GO = 0x2A030020ull;
+
+static const uint64_t P9N2_C_11_PCB_OPCG_GO = 0x2B030020ull;
+
+static const uint64_t P9N2_C_12_PCB_OPCG_GO = 0x2C030020ull;
+
+static const uint64_t P9N2_C_13_PCB_OPCG_GO = 0x2D030020ull;
+
+static const uint64_t P9N2_C_14_PCB_OPCG_GO = 0x2E030020ull;
+
+static const uint64_t P9N2_C_15_PCB_OPCG_GO = 0x2F030020ull;
+
+static const uint64_t P9N2_C_16_PCB_OPCG_GO = 0x30030020ull;
+
+static const uint64_t P9N2_C_17_PCB_OPCG_GO = 0x31030020ull;
+
+static const uint64_t P9N2_C_18_PCB_OPCG_GO = 0x32030020ull;
+
+static const uint64_t P9N2_C_19_PCB_OPCG_GO = 0x33030020ull;
+
+static const uint64_t P9N2_C_20_PCB_OPCG_GO = 0x34030020ull;
+
+static const uint64_t P9N2_C_21_PCB_OPCG_GO = 0x35030020ull;
+
+static const uint64_t P9N2_C_22_PCB_OPCG_GO = 0x36030020ull;
+
+static const uint64_t P9N2_C_23_PCB_OPCG_GO = 0x37030020ull;
+
+static const uint64_t P9N2_EQ_PCB_OPCG_GO = 0x10030020ull;
+
+static const uint64_t P9N2_EQ_0_PCB_OPCG_GO = 0x10030020ull;
+
+static const uint64_t P9N2_EQ_1_PCB_OPCG_GO = 0x11030020ull;
+
+static const uint64_t P9N2_EQ_2_PCB_OPCG_GO = 0x12030020ull;
+
+static const uint64_t P9N2_EQ_3_PCB_OPCG_GO = 0x13030020ull;
+
+static const uint64_t P9N2_EQ_4_PCB_OPCG_GO = 0x14030020ull;
+
+static const uint64_t P9N2_EQ_5_PCB_OPCG_GO = 0x15030020ull;
+
+static const uint64_t P9N2_EX_PCB_OPCG_GO = 0x20030020ull;
+//DUPS: 21030020,
+static const uint64_t P9N2_EX_0_PCB_OPCG_GO = 0x20030020ull;
+//DUPS: 21030020,
+static const uint64_t P9N2_EX_1_PCB_OPCG_GO = 0x22030020ull;
+//DUPS: 23030020,
+static const uint64_t P9N2_EX_2_PCB_OPCG_GO = 0x24030020ull;
+//DUPS: 25030020,
+static const uint64_t P9N2_EX_3_PCB_OPCG_GO = 0x26030020ull;
+//DUPS: 27030020,
+static const uint64_t P9N2_EX_4_PCB_OPCG_GO = 0x28030020ull;
+//DUPS: 29030020,
+static const uint64_t P9N2_EX_5_PCB_OPCG_GO = 0x2A030020ull;
+//DUPS: 2B030020,
+static const uint64_t P9N2_EX_6_PCB_OPCG_GO = 0x2C030020ull;
+//DUPS: 2D030020,
+static const uint64_t P9N2_EX_7_PCB_OPCG_GO = 0x2F030020ull;
+//DUPS: 2F030020,
+static const uint64_t P9N2_EX_8_PCB_OPCG_GO = 0x30030020ull;
+//DUPS: 31030020,
+static const uint64_t P9N2_EX_9_PCB_OPCG_GO = 0x32030020ull;
+//DUPS: 33030020,
+static const uint64_t P9N2_EX_10_PCB_OPCG_GO = 0x34030020ull;
+//DUPS: 35030020,
+static const uint64_t P9N2_EX_11_PCB_OPCG_GO = 0x36030020ull;
+//DUPS: 37030020,
+
+static const uint64_t P9N2_C_PCB_OPCG_STOP = 0x20030030ull;
+
+static const uint64_t P9N2_C_0_PCB_OPCG_STOP = 0x20030030ull;
+
+static const uint64_t P9N2_C_1_PCB_OPCG_STOP = 0x21030030ull;
+
+static const uint64_t P9N2_C_2_PCB_OPCG_STOP = 0x22030030ull;
+
+static const uint64_t P9N2_C_3_PCB_OPCG_STOP = 0x23030030ull;
+
+static const uint64_t P9N2_C_4_PCB_OPCG_STOP = 0x24030030ull;
+
+static const uint64_t P9N2_C_5_PCB_OPCG_STOP = 0x25030030ull;
+
+static const uint64_t P9N2_C_6_PCB_OPCG_STOP = 0x26030030ull;
+
+static const uint64_t P9N2_C_7_PCB_OPCG_STOP = 0x27030030ull;
+
+static const uint64_t P9N2_C_8_PCB_OPCG_STOP = 0x28030030ull;
+
+static const uint64_t P9N2_C_9_PCB_OPCG_STOP = 0x29030030ull;
+
+static const uint64_t P9N2_C_10_PCB_OPCG_STOP = 0x2A030030ull;
+
+static const uint64_t P9N2_C_11_PCB_OPCG_STOP = 0x2B030030ull;
+
+static const uint64_t P9N2_C_12_PCB_OPCG_STOP = 0x2C030030ull;
+
+static const uint64_t P9N2_C_13_PCB_OPCG_STOP = 0x2D030030ull;
+
+static const uint64_t P9N2_C_14_PCB_OPCG_STOP = 0x2E030030ull;
+
+static const uint64_t P9N2_C_15_PCB_OPCG_STOP = 0x2F030030ull;
+
+static const uint64_t P9N2_C_16_PCB_OPCG_STOP = 0x30030030ull;
+
+static const uint64_t P9N2_C_17_PCB_OPCG_STOP = 0x31030030ull;
+
+static const uint64_t P9N2_C_18_PCB_OPCG_STOP = 0x32030030ull;
+
+static const uint64_t P9N2_C_19_PCB_OPCG_STOP = 0x33030030ull;
+
+static const uint64_t P9N2_C_20_PCB_OPCG_STOP = 0x34030030ull;
+
+static const uint64_t P9N2_C_21_PCB_OPCG_STOP = 0x35030030ull;
+
+static const uint64_t P9N2_C_22_PCB_OPCG_STOP = 0x36030030ull;
+
+static const uint64_t P9N2_C_23_PCB_OPCG_STOP = 0x37030030ull;
+
+static const uint64_t P9N2_EQ_PCB_OPCG_STOP = 0x10030030ull;
+
+static const uint64_t P9N2_EQ_0_PCB_OPCG_STOP = 0x10030030ull;
+
+static const uint64_t P9N2_EQ_1_PCB_OPCG_STOP = 0x11030030ull;
+
+static const uint64_t P9N2_EQ_2_PCB_OPCG_STOP = 0x12030030ull;
+
+static const uint64_t P9N2_EQ_3_PCB_OPCG_STOP = 0x13030030ull;
+
+static const uint64_t P9N2_EQ_4_PCB_OPCG_STOP = 0x14030030ull;
+
+static const uint64_t P9N2_EQ_5_PCB_OPCG_STOP = 0x15030030ull;
+
+static const uint64_t P9N2_EX_PCB_OPCG_STOP = 0x20030030ull;
+//DUPS: 21030030,
+static const uint64_t P9N2_EX_0_PCB_OPCG_STOP = 0x20030030ull;
+//DUPS: 21030030,
+static const uint64_t P9N2_EX_1_PCB_OPCG_STOP = 0x22030030ull;
+//DUPS: 23030030,
+static const uint64_t P9N2_EX_2_PCB_OPCG_STOP = 0x24030030ull;
+//DUPS: 25030030,
+static const uint64_t P9N2_EX_3_PCB_OPCG_STOP = 0x26030030ull;
+//DUPS: 27030030,
+static const uint64_t P9N2_EX_4_PCB_OPCG_STOP = 0x28030030ull;
+//DUPS: 29030030,
+static const uint64_t P9N2_EX_5_PCB_OPCG_STOP = 0x2A030030ull;
+//DUPS: 2B030030,
+static const uint64_t P9N2_EX_6_PCB_OPCG_STOP = 0x2C030030ull;
+//DUPS: 2D030030,
+static const uint64_t P9N2_EX_7_PCB_OPCG_STOP = 0x2F030030ull;
+//DUPS: 2F030030,
+static const uint64_t P9N2_EX_8_PCB_OPCG_STOP = 0x30030030ull;
+//DUPS: 31030030,
+static const uint64_t P9N2_EX_9_PCB_OPCG_STOP = 0x32030030ull;
+//DUPS: 33030030,
+static const uint64_t P9N2_EX_10_PCB_OPCG_STOP = 0x34030030ull;
+//DUPS: 35030030,
+static const uint64_t P9N2_EX_11_PCB_OPCG_STOP = 0x36030030ull;
+//DUPS: 37030030,
+
+static const uint64_t P9N2_EQ_PHYP_PURGE_CMD_REG = 0x10010C0Full;
+//DUPS: 10010C0F,
+static const uint64_t P9N2_EQ_0_PHYP_PURGE_CMD_REG = 0x10010C0Full;
+//DUPS: 10010C0F,
+static const uint64_t P9N2_EQ_1_PHYP_PURGE_CMD_REG = 0x11010C0Full;
+//DUPS: 11010C0F,
+static const uint64_t P9N2_EQ_2_PHYP_PURGE_CMD_REG = 0x12010C0Full;
+//DUPS: 12010C0F,
+static const uint64_t P9N2_EQ_3_PHYP_PURGE_CMD_REG = 0x13010C0Full;
+//DUPS: 13010C0F,
+static const uint64_t P9N2_EQ_4_PHYP_PURGE_CMD_REG = 0x14010C0Full;
+//DUPS: 14010C0F,
+static const uint64_t P9N2_EQ_5_PHYP_PURGE_CMD_REG = 0x15010C0Full;
+//DUPS: 15010C0F,
+static const uint64_t P9N2_EX_PHYP_PURGE_CMD_REG = 0x1001080Full;
+
+static const uint64_t P9N2_EX_0_PHYP_PURGE_CMD_REG = 0x1001080Full;
+
+static const uint64_t P9N2_EX_1_PHYP_PURGE_CMD_REG = 0x10010C0Full;
+
+static const uint64_t P9N2_EX_2_PHYP_PURGE_CMD_REG = 0x1101080Full;
+
+static const uint64_t P9N2_EX_3_PHYP_PURGE_CMD_REG = 0x11010C0Full;
+
+static const uint64_t P9N2_EX_4_PHYP_PURGE_CMD_REG = 0x1201080Full;
+
+static const uint64_t P9N2_EX_5_PHYP_PURGE_CMD_REG = 0x12010C0Full;
+
+static const uint64_t P9N2_EX_6_PHYP_PURGE_CMD_REG = 0x1301080Full;
+
+static const uint64_t P9N2_EX_7_PHYP_PURGE_CMD_REG = 0x13010C0Full;
+
+static const uint64_t P9N2_EX_8_PHYP_PURGE_CMD_REG = 0x1401080Full;
+
+static const uint64_t P9N2_EX_9_PHYP_PURGE_CMD_REG = 0x14010C0Full;
+
+static const uint64_t P9N2_EX_10_PHYP_PURGE_CMD_REG = 0x1501080Full;
+
+static const uint64_t P9N2_EX_11_PHYP_PURGE_CMD_REG = 0x15010C0Full;
+
+
+static const uint64_t P9N2_EQ_PHYP_PURGE_REG = 0x10011C14ull;
+//DUPS: 10011C14,
+static const uint64_t P9N2_EQ_0_PHYP_PURGE_REG = 0x10011C14ull;
+//DUPS: 10011C14,
+static const uint64_t P9N2_EQ_1_PHYP_PURGE_REG = 0x11011C14ull;
+//DUPS: 11011C14,
+static const uint64_t P9N2_EQ_2_PHYP_PURGE_REG = 0x12011C14ull;
+//DUPS: 12011C14,
+static const uint64_t P9N2_EQ_3_PHYP_PURGE_REG = 0x13011C14ull;
+//DUPS: 13011C14,
+static const uint64_t P9N2_EQ_4_PHYP_PURGE_REG = 0x14011C14ull;
+//DUPS: 14011C14,
+static const uint64_t P9N2_EQ_5_PHYP_PURGE_REG = 0x15011C14ull;
+//DUPS: 15011C14,
+static const uint64_t P9N2_EX_0_L3_PHYP_PURGE_REG = 0x10011814ull;
+
+static const uint64_t P9N2_EX_10_L3_PHYP_PURGE_REG = 0x15011814ull;
+
+static const uint64_t P9N2_EX_11_L3_PHYP_PURGE_REG = 0x15011C14ull;
+
+static const uint64_t P9N2_EX_1_L3_PHYP_PURGE_REG = 0x10011C14ull;
+
+static const uint64_t P9N2_EX_2_L3_PHYP_PURGE_REG = 0x11011814ull;
+
+static const uint64_t P9N2_EX_3_L3_PHYP_PURGE_REG = 0x11011C14ull;
+
+static const uint64_t P9N2_EX_4_L3_PHYP_PURGE_REG = 0x12011814ull;
+
+static const uint64_t P9N2_EX_5_L3_PHYP_PURGE_REG = 0x12011C14ull;
+
+static const uint64_t P9N2_EX_6_L3_PHYP_PURGE_REG = 0x13011814ull;
+
+static const uint64_t P9N2_EX_7_L3_PHYP_PURGE_REG = 0x13011C14ull;
+
+static const uint64_t P9N2_EX_8_L3_PHYP_PURGE_REG = 0x14011814ull;
+
+static const uint64_t P9N2_EX_9_L3_PHYP_PURGE_REG = 0x14011C14ull;
+
+static const uint64_t P9N2_EX_L3_PHYP_PURGE_REG = 0x10011814ull;
+
+
+static const uint64_t P9N2_C_PLL_LOCK_REG = 0x200F0019ull;
+
+static const uint64_t P9N2_C_0_PLL_LOCK_REG = 0x200F0019ull;
+
+static const uint64_t P9N2_C_1_PLL_LOCK_REG = 0x210F0019ull;
+
+static const uint64_t P9N2_C_2_PLL_LOCK_REG = 0x220F0019ull;
+
+static const uint64_t P9N2_C_3_PLL_LOCK_REG = 0x230F0019ull;
+
+static const uint64_t P9N2_C_4_PLL_LOCK_REG = 0x240F0019ull;
+
+static const uint64_t P9N2_C_5_PLL_LOCK_REG = 0x250F0019ull;
+
+static const uint64_t P9N2_C_6_PLL_LOCK_REG = 0x260F0019ull;
+
+static const uint64_t P9N2_C_7_PLL_LOCK_REG = 0x270F0019ull;
+
+static const uint64_t P9N2_C_8_PLL_LOCK_REG = 0x280F0019ull;
+
+static const uint64_t P9N2_C_9_PLL_LOCK_REG = 0x290F0019ull;
+
+static const uint64_t P9N2_C_10_PLL_LOCK_REG = 0x2A0F0019ull;
+
+static const uint64_t P9N2_C_11_PLL_LOCK_REG = 0x2B0F0019ull;
+
+static const uint64_t P9N2_C_12_PLL_LOCK_REG = 0x2C0F0019ull;
+
+static const uint64_t P9N2_C_13_PLL_LOCK_REG = 0x2D0F0019ull;
+
+static const uint64_t P9N2_C_14_PLL_LOCK_REG = 0x2E0F0019ull;
+
+static const uint64_t P9N2_C_15_PLL_LOCK_REG = 0x2F0F0019ull;
+
+static const uint64_t P9N2_C_16_PLL_LOCK_REG = 0x300F0019ull;
+
+static const uint64_t P9N2_C_17_PLL_LOCK_REG = 0x310F0019ull;
+
+static const uint64_t P9N2_C_18_PLL_LOCK_REG = 0x320F0019ull;
+
+static const uint64_t P9N2_C_19_PLL_LOCK_REG = 0x330F0019ull;
+
+static const uint64_t P9N2_C_20_PLL_LOCK_REG = 0x340F0019ull;
+
+static const uint64_t P9N2_C_21_PLL_LOCK_REG = 0x350F0019ull;
+
+static const uint64_t P9N2_C_22_PLL_LOCK_REG = 0x360F0019ull;
+
+static const uint64_t P9N2_C_23_PLL_LOCK_REG = 0x370F0019ull;
+
+static const uint64_t P9N2_EQ_PLL_LOCK_REG = 0x100F0019ull;
+
+static const uint64_t P9N2_EQ_0_PLL_LOCK_REG = 0x100F0019ull;
+
+static const uint64_t P9N2_EQ_1_PLL_LOCK_REG = 0x110F0019ull;
+
+static const uint64_t P9N2_EQ_2_PLL_LOCK_REG = 0x120F0019ull;
+
+static const uint64_t P9N2_EQ_3_PLL_LOCK_REG = 0x130F0019ull;
+
+static const uint64_t P9N2_EQ_4_PLL_LOCK_REG = 0x140F0019ull;
+
+static const uint64_t P9N2_EQ_5_PLL_LOCK_REG = 0x150F0019ull;
+
+static const uint64_t P9N2_EX_PLL_LOCK_REG = 0x200F0019ull;
+//DUPS: 210F0019,
+static const uint64_t P9N2_EX_0_PLL_LOCK_REG = 0x200F0019ull;
+//DUPS: 210F0019,
+static const uint64_t P9N2_EX_1_PLL_LOCK_REG = 0x220F0019ull;
+//DUPS: 220F0019,
+static const uint64_t P9N2_EX_2_PLL_LOCK_REG = 0x240F0019ull;
+//DUPS: 250F0019,
+static const uint64_t P9N2_EX_3_PLL_LOCK_REG = 0x260F0019ull;
+//DUPS: 270F0019,
+static const uint64_t P9N2_EX_4_PLL_LOCK_REG = 0x280F0019ull;
+//DUPS: 290F0019,
+static const uint64_t P9N2_EX_5_PLL_LOCK_REG = 0x2A0F0019ull;
+//DUPS: 2B0F0019,
+static const uint64_t P9N2_EX_6_PLL_LOCK_REG = 0x2C0F0019ull;
+//DUPS: 2D0F0019,
+static const uint64_t P9N2_EX_7_PLL_LOCK_REG = 0x2E0F0019ull;
+//DUPS: 2F0F0019,
+static const uint64_t P9N2_EX_8_PLL_LOCK_REG = 0x300F0019ull;
+//DUPS: 310F0019,
+static const uint64_t P9N2_EX_9_PLL_LOCK_REG = 0x320F0019ull;
+//DUPS: 330F0019,
+static const uint64_t P9N2_EX_10_PLL_LOCK_REG = 0x340F0019ull;
+//DUPS: 350F0019,
+static const uint64_t P9N2_EX_11_PLL_LOCK_REG = 0x360F0019ull;
+//DUPS: 370F0019,
+
+static const uint64_t P9N2_C_PMU_HOLD_OUT = 0x20010AB6ull;
+
+static const uint64_t P9N2_C_0_PMU_HOLD_OUT = 0x20010AB6ull;
+
+static const uint64_t P9N2_C_1_PMU_HOLD_OUT = 0x21010AB6ull;
+
+static const uint64_t P9N2_C_2_PMU_HOLD_OUT = 0x22010AB6ull;
+
+static const uint64_t P9N2_C_3_PMU_HOLD_OUT = 0x23010AB6ull;
+
+static const uint64_t P9N2_C_4_PMU_HOLD_OUT = 0x24010AB6ull;
+
+static const uint64_t P9N2_C_5_PMU_HOLD_OUT = 0x25010AB6ull;
+
+static const uint64_t P9N2_C_6_PMU_HOLD_OUT = 0x26010AB6ull;
+
+static const uint64_t P9N2_C_7_PMU_HOLD_OUT = 0x27010AB6ull;
+
+static const uint64_t P9N2_C_8_PMU_HOLD_OUT = 0x28010AB6ull;
+
+static const uint64_t P9N2_C_9_PMU_HOLD_OUT = 0x29010AB6ull;
+
+static const uint64_t P9N2_C_10_PMU_HOLD_OUT = 0x2A010AB6ull;
+
+static const uint64_t P9N2_C_11_PMU_HOLD_OUT = 0x2B010AB6ull;
+
+static const uint64_t P9N2_C_12_PMU_HOLD_OUT = 0x2C010AB6ull;
+
+static const uint64_t P9N2_C_13_PMU_HOLD_OUT = 0x2D010AB6ull;
+
+static const uint64_t P9N2_C_14_PMU_HOLD_OUT = 0x2E010AB6ull;
+
+static const uint64_t P9N2_C_15_PMU_HOLD_OUT = 0x2F010AB6ull;
+
+static const uint64_t P9N2_C_16_PMU_HOLD_OUT = 0x30010AB6ull;
+
+static const uint64_t P9N2_C_17_PMU_HOLD_OUT = 0x31010AB6ull;
+
+static const uint64_t P9N2_C_18_PMU_HOLD_OUT = 0x32010AB6ull;
+
+static const uint64_t P9N2_C_19_PMU_HOLD_OUT = 0x33010AB6ull;
+
+static const uint64_t P9N2_C_20_PMU_HOLD_OUT = 0x34010AB6ull;
+
+static const uint64_t P9N2_C_21_PMU_HOLD_OUT = 0x35010AB6ull;
+
+static const uint64_t P9N2_C_22_PMU_HOLD_OUT = 0x36010AB6ull;
+
+static const uint64_t P9N2_C_23_PMU_HOLD_OUT = 0x37010AB6ull;
+
+static const uint64_t P9N2_EX_0_L2_PMU_HOLD_OUT = 0x20010AB6ull;
+//DUPS: 21010AB6,
+static const uint64_t P9N2_EX_10_L2_PMU_HOLD_OUT = 0x34010AB6ull;
+//DUPS: 35010AB6,
+static const uint64_t P9N2_EX_11_L2_PMU_HOLD_OUT = 0x36010AB6ull;
+//DUPS: 37010AB6,
+static const uint64_t P9N2_EX_1_L2_PMU_HOLD_OUT = 0x22010AB6ull;
+//DUPS: 23010AB6,
+static const uint64_t P9N2_EX_2_L2_PMU_HOLD_OUT = 0x24010AB6ull;
+//DUPS: 25010AB6,
+static const uint64_t P9N2_EX_3_L2_PMU_HOLD_OUT = 0x26010AB6ull;
+//DUPS: 27010AB6,
+static const uint64_t P9N2_EX_4_L2_PMU_HOLD_OUT = 0x28010AB6ull;
+//DUPS: 29010AB6,
+static const uint64_t P9N2_EX_5_L2_PMU_HOLD_OUT = 0x2A010AB6ull;
+//DUPS: 2B010AB6,
+static const uint64_t P9N2_EX_6_L2_PMU_HOLD_OUT = 0x2C010AB6ull;
+//DUPS: 2D010AB6,
+static const uint64_t P9N2_EX_7_L2_PMU_HOLD_OUT = 0x2F010AB6ull;
+//DUPS: 2F010AB6,
+static const uint64_t P9N2_EX_8_L2_PMU_HOLD_OUT = 0x30010AB6ull;
+//DUPS: 31010AB6,
+static const uint64_t P9N2_EX_9_L2_PMU_HOLD_OUT = 0x32010AB6ull;
+//DUPS: 33010AB6,
+static const uint64_t P9N2_EX_L2_PMU_HOLD_OUT = 0x20010AB6ull;
+//DUPS: 21010AB6,
+
+static const uint64_t P9N2_C_PMU_SCOMC = 0x20010AB0ull;
+
+static const uint64_t P9N2_C_0_PMU_SCOMC = 0x20010AB0ull;
+
+static const uint64_t P9N2_C_1_PMU_SCOMC = 0x21010AB0ull;
+
+static const uint64_t P9N2_C_2_PMU_SCOMC = 0x22010AB0ull;
+
+static const uint64_t P9N2_C_3_PMU_SCOMC = 0x23010AB0ull;
+
+static const uint64_t P9N2_C_4_PMU_SCOMC = 0x24010AB0ull;
+
+static const uint64_t P9N2_C_5_PMU_SCOMC = 0x25010AB0ull;
+
+static const uint64_t P9N2_C_6_PMU_SCOMC = 0x26010AB0ull;
+
+static const uint64_t P9N2_C_7_PMU_SCOMC = 0x27010AB0ull;
+
+static const uint64_t P9N2_C_8_PMU_SCOMC = 0x28010AB0ull;
+
+static const uint64_t P9N2_C_9_PMU_SCOMC = 0x29010AB0ull;
+
+static const uint64_t P9N2_C_10_PMU_SCOMC = 0x2A010AB0ull;
+
+static const uint64_t P9N2_C_11_PMU_SCOMC = 0x2B010AB0ull;
+
+static const uint64_t P9N2_C_12_PMU_SCOMC = 0x2C010AB0ull;
+
+static const uint64_t P9N2_C_13_PMU_SCOMC = 0x2D010AB0ull;
+
+static const uint64_t P9N2_C_14_PMU_SCOMC = 0x2E010AB0ull;
+
+static const uint64_t P9N2_C_15_PMU_SCOMC = 0x2F010AB0ull;
+
+static const uint64_t P9N2_C_16_PMU_SCOMC = 0x30010AB0ull;
+
+static const uint64_t P9N2_C_17_PMU_SCOMC = 0x31010AB0ull;
+
+static const uint64_t P9N2_C_18_PMU_SCOMC = 0x32010AB0ull;
+
+static const uint64_t P9N2_C_19_PMU_SCOMC = 0x33010AB0ull;
+
+static const uint64_t P9N2_C_20_PMU_SCOMC = 0x34010AB0ull;
+
+static const uint64_t P9N2_C_21_PMU_SCOMC = 0x35010AB0ull;
+
+static const uint64_t P9N2_C_22_PMU_SCOMC = 0x36010AB0ull;
+
+static const uint64_t P9N2_C_23_PMU_SCOMC = 0x37010AB0ull;
+
+static const uint64_t P9N2_EX_0_L2_PMU_SCOMC = 0x20010AB0ull;
+//DUPS: 21010AB0,
+static const uint64_t P9N2_EX_10_L2_PMU_SCOMC = 0x34010AB0ull;
+//DUPS: 35010AB0,
+static const uint64_t P9N2_EX_11_L2_PMU_SCOMC = 0x36010AB0ull;
+//DUPS: 37010AB0,
+static const uint64_t P9N2_EX_1_L2_PMU_SCOMC = 0x22010AB0ull;
+//DUPS: 23010AB0,
+static const uint64_t P9N2_EX_2_L2_PMU_SCOMC = 0x24010AB0ull;
+//DUPS: 25010AB0,
+static const uint64_t P9N2_EX_3_L2_PMU_SCOMC = 0x26010AB0ull;
+//DUPS: 27010AB0,
+static const uint64_t P9N2_EX_4_L2_PMU_SCOMC = 0x28010AB0ull;
+//DUPS: 29010AB0,
+static const uint64_t P9N2_EX_5_L2_PMU_SCOMC = 0x2A010AB0ull;
+//DUPS: 2B010AB0,
+static const uint64_t P9N2_EX_6_L2_PMU_SCOMC = 0x2C010AB0ull;
+//DUPS: 2D010AB0,
+static const uint64_t P9N2_EX_7_L2_PMU_SCOMC = 0x2F010AB0ull;
+//DUPS: 2F010AB0,
+static const uint64_t P9N2_EX_8_L2_PMU_SCOMC = 0x30010AB0ull;
+//DUPS: 31010AB0,
+static const uint64_t P9N2_EX_9_L2_PMU_SCOMC = 0x32010AB0ull;
+//DUPS: 33010AB0,
+static const uint64_t P9N2_EX_L2_PMU_SCOMC = 0x20010AB0ull;
+//DUPS: 21010AB0,
+
+static const uint64_t P9N2_C_PMU_SCOMC_EN = 0x20010AB2ull;
+
+static const uint64_t P9N2_C_0_PMU_SCOMC_EN = 0x20010AB2ull;
+
+static const uint64_t P9N2_C_1_PMU_SCOMC_EN = 0x21010AB2ull;
+
+static const uint64_t P9N2_C_2_PMU_SCOMC_EN = 0x22010AB2ull;
+
+static const uint64_t P9N2_C_3_PMU_SCOMC_EN = 0x23010AB2ull;
+
+static const uint64_t P9N2_C_4_PMU_SCOMC_EN = 0x24010AB2ull;
+
+static const uint64_t P9N2_C_5_PMU_SCOMC_EN = 0x25010AB2ull;
+
+static const uint64_t P9N2_C_6_PMU_SCOMC_EN = 0x26010AB2ull;
+
+static const uint64_t P9N2_C_7_PMU_SCOMC_EN = 0x27010AB2ull;
+
+static const uint64_t P9N2_C_8_PMU_SCOMC_EN = 0x28010AB2ull;
+
+static const uint64_t P9N2_C_9_PMU_SCOMC_EN = 0x29010AB2ull;
+
+static const uint64_t P9N2_C_10_PMU_SCOMC_EN = 0x2A010AB2ull;
+
+static const uint64_t P9N2_C_11_PMU_SCOMC_EN = 0x2B010AB2ull;
+
+static const uint64_t P9N2_C_12_PMU_SCOMC_EN = 0x2C010AB2ull;
+
+static const uint64_t P9N2_C_13_PMU_SCOMC_EN = 0x2D010AB2ull;
+
+static const uint64_t P9N2_C_14_PMU_SCOMC_EN = 0x2E010AB2ull;
+
+static const uint64_t P9N2_C_15_PMU_SCOMC_EN = 0x2F010AB2ull;
+
+static const uint64_t P9N2_C_16_PMU_SCOMC_EN = 0x30010AB2ull;
+
+static const uint64_t P9N2_C_17_PMU_SCOMC_EN = 0x31010AB2ull;
+
+static const uint64_t P9N2_C_18_PMU_SCOMC_EN = 0x32010AB2ull;
+
+static const uint64_t P9N2_C_19_PMU_SCOMC_EN = 0x33010AB2ull;
+
+static const uint64_t P9N2_C_20_PMU_SCOMC_EN = 0x34010AB2ull;
+
+static const uint64_t P9N2_C_21_PMU_SCOMC_EN = 0x35010AB2ull;
+
+static const uint64_t P9N2_C_22_PMU_SCOMC_EN = 0x36010AB2ull;
+
+static const uint64_t P9N2_C_23_PMU_SCOMC_EN = 0x37010AB2ull;
+
+static const uint64_t P9N2_EX_0_L2_PMU_SCOMC_EN = 0x20010AB2ull;
+//DUPS: 21010AB2,
+static const uint64_t P9N2_EX_10_L2_PMU_SCOMC_EN = 0x34010AB2ull;
+//DUPS: 35010AB2,
+static const uint64_t P9N2_EX_11_L2_PMU_SCOMC_EN = 0x36010AB2ull;
+//DUPS: 37010AB2,
+static const uint64_t P9N2_EX_1_L2_PMU_SCOMC_EN = 0x22010AB2ull;
+//DUPS: 23010AB2,
+static const uint64_t P9N2_EX_2_L2_PMU_SCOMC_EN = 0x24010AB2ull;
+//DUPS: 25010AB2,
+static const uint64_t P9N2_EX_3_L2_PMU_SCOMC_EN = 0x26010AB2ull;
+//DUPS: 27010AB2,
+static const uint64_t P9N2_EX_4_L2_PMU_SCOMC_EN = 0x28010AB2ull;
+//DUPS: 29010AB2,
+static const uint64_t P9N2_EX_5_L2_PMU_SCOMC_EN = 0x2A010AB2ull;
+//DUPS: 2B010AB2,
+static const uint64_t P9N2_EX_6_L2_PMU_SCOMC_EN = 0x2C010AB2ull;
+//DUPS: 2D010AB2,
+static const uint64_t P9N2_EX_7_L2_PMU_SCOMC_EN = 0x2F010AB2ull;
+//DUPS: 2F010AB2,
+static const uint64_t P9N2_EX_8_L2_PMU_SCOMC_EN = 0x30010AB2ull;
+//DUPS: 31010AB2,
+static const uint64_t P9N2_EX_9_L2_PMU_SCOMC_EN = 0x32010AB2ull;
+//DUPS: 33010AB2,
+static const uint64_t P9N2_EX_L2_PMU_SCOMC_EN = 0x20010AB2ull;
+//DUPS: 21010AB2,
+
+static const uint64_t P9N2_EQ_PM_L2_RCMD_DIS_REG = 0x10011C18ull;
+//DUPS: 10011C18,
+static const uint64_t P9N2_EQ_0_PM_L2_RCMD_DIS_REG = 0x10011C18ull;
+//DUPS: 10011C18,
+static const uint64_t P9N2_EQ_1_PM_L2_RCMD_DIS_REG = 0x11011C18ull;
+//DUPS: 11011C18,
+static const uint64_t P9N2_EQ_2_PM_L2_RCMD_DIS_REG = 0x12011C18ull;
+//DUPS: 12011C18,
+static const uint64_t P9N2_EQ_3_PM_L2_RCMD_DIS_REG = 0x13011C18ull;
+//DUPS: 13011C18,
+static const uint64_t P9N2_EQ_4_PM_L2_RCMD_DIS_REG = 0x14011C18ull;
+//DUPS: 14011C18,
+static const uint64_t P9N2_EQ_5_PM_L2_RCMD_DIS_REG = 0x15011C18ull;
+//DUPS: 15011C18,
+static const uint64_t P9N2_EX_PM_L2_RCMD_DIS_REG = 0x10011818ull;
+
+static const uint64_t P9N2_EX_0_PM_L2_RCMD_DIS_REG = 0x10011818ull;
+
+static const uint64_t P9N2_EX_1_PM_L2_RCMD_DIS_REG = 0x10011C18ull;
+
+static const uint64_t P9N2_EX_2_PM_L2_RCMD_DIS_REG = 0x11011818ull;
+
+static const uint64_t P9N2_EX_3_PM_L2_RCMD_DIS_REG = 0x11011C18ull;
+
+static const uint64_t P9N2_EX_4_PM_L2_RCMD_DIS_REG = 0x12011818ull;
+
+static const uint64_t P9N2_EX_5_PM_L2_RCMD_DIS_REG = 0x12011C18ull;
+
+static const uint64_t P9N2_EX_6_PM_L2_RCMD_DIS_REG = 0x13011818ull;
+
+static const uint64_t P9N2_EX_7_PM_L2_RCMD_DIS_REG = 0x13011C18ull;
+
+static const uint64_t P9N2_EX_8_PM_L2_RCMD_DIS_REG = 0x14011818ull;
+
+static const uint64_t P9N2_EX_9_PM_L2_RCMD_DIS_REG = 0x14011C18ull;
+
+static const uint64_t P9N2_EX_10_PM_L2_RCMD_DIS_REG = 0x15011818ull;
+
+static const uint64_t P9N2_EX_11_PM_L2_RCMD_DIS_REG = 0x15011C18ull;
+
+
+static const uint64_t P9N2_EQ_PM_LCO_DIS_REG = 0x10011C16ull;
+//DUPS: 10011C16,
+static const uint64_t P9N2_EQ_0_PM_LCO_DIS_REG = 0x10011C16ull;
+//DUPS: 10011C16,
+static const uint64_t P9N2_EQ_1_PM_LCO_DIS_REG = 0x11011C16ull;
+//DUPS: 11011C16,
+static const uint64_t P9N2_EQ_2_PM_LCO_DIS_REG = 0x12011C16ull;
+//DUPS: 12011C16,
+static const uint64_t P9N2_EQ_3_PM_LCO_DIS_REG = 0x13011C16ull;
+//DUPS: 13011C16,
+static const uint64_t P9N2_EQ_4_PM_LCO_DIS_REG = 0x14011C16ull;
+//DUPS: 14011C16,
+static const uint64_t P9N2_EQ_5_PM_LCO_DIS_REG = 0x15011C16ull;
+//DUPS: 15011C16,
+static const uint64_t P9N2_EX_0_L3_PM_LCO_DIS_REG = 0x10011816ull;
+
+static const uint64_t P9N2_EX_10_L3_PM_LCO_DIS_REG = 0x15011816ull;
+
+static const uint64_t P9N2_EX_11_L3_PM_LCO_DIS_REG = 0x15011C16ull;
+
+static const uint64_t P9N2_EX_1_L3_PM_LCO_DIS_REG = 0x10011C16ull;
+
+static const uint64_t P9N2_EX_2_L3_PM_LCO_DIS_REG = 0x11011816ull;
+
+static const uint64_t P9N2_EX_3_L3_PM_LCO_DIS_REG = 0x11011C16ull;
+
+static const uint64_t P9N2_EX_4_L3_PM_LCO_DIS_REG = 0x12011816ull;
+
+static const uint64_t P9N2_EX_5_L3_PM_LCO_DIS_REG = 0x12011C16ull;
+
+static const uint64_t P9N2_EX_6_L3_PM_LCO_DIS_REG = 0x13011816ull;
+
+static const uint64_t P9N2_EX_7_L3_PM_LCO_DIS_REG = 0x13011C16ull;
+
+static const uint64_t P9N2_EX_8_L3_PM_LCO_DIS_REG = 0x14011816ull;
+
+static const uint64_t P9N2_EX_9_L3_PM_LCO_DIS_REG = 0x14011C16ull;
+
+static const uint64_t P9N2_EX_L3_PM_LCO_DIS_REG = 0x10011816ull;
+
+
+static const uint64_t P9N2_EQ_PM_PURGE_REG = 0x10011C13ull;
+//DUPS: 10011C13,
+static const uint64_t P9N2_EQ_0_PM_PURGE_REG = 0x10011C13ull;
+//DUPS: 10011C13,
+static const uint64_t P9N2_EQ_1_PM_PURGE_REG = 0x11011C13ull;
+//DUPS: 11011C13,
+static const uint64_t P9N2_EQ_2_PM_PURGE_REG = 0x12011C13ull;
+//DUPS: 12011C13,
+static const uint64_t P9N2_EQ_3_PM_PURGE_REG = 0x13011C13ull;
+//DUPS: 13011C13,
+static const uint64_t P9N2_EQ_4_PM_PURGE_REG = 0x14011C13ull;
+//DUPS: 14011C13,
+static const uint64_t P9N2_EQ_5_PM_PURGE_REG = 0x15011C13ull;
+//DUPS: 15011C13,
+static const uint64_t P9N2_EX_0_L3_PM_PURGE_REG = 0x10011813ull;
+
+static const uint64_t P9N2_EX_10_L3_PM_PURGE_REG = 0x15011813ull;
+
+static const uint64_t P9N2_EX_11_L3_PM_PURGE_REG = 0x15011C13ull;
+
+static const uint64_t P9N2_EX_1_L3_PM_PURGE_REG = 0x10011C13ull;
+
+static const uint64_t P9N2_EX_2_L3_PM_PURGE_REG = 0x11011813ull;
+
+static const uint64_t P9N2_EX_3_L3_PM_PURGE_REG = 0x11011C13ull;
+
+static const uint64_t P9N2_EX_4_L3_PM_PURGE_REG = 0x12011813ull;
+
+static const uint64_t P9N2_EX_5_L3_PM_PURGE_REG = 0x12011C13ull;
+
+static const uint64_t P9N2_EX_6_L3_PM_PURGE_REG = 0x13011813ull;
+
+static const uint64_t P9N2_EX_7_L3_PM_PURGE_REG = 0x13011C13ull;
+
+static const uint64_t P9N2_EX_8_L3_PM_PURGE_REG = 0x14011813ull;
+
+static const uint64_t P9N2_EX_9_L3_PM_PURGE_REG = 0x14011C13ull;
+
+static const uint64_t P9N2_EX_L3_PM_PURGE_REG = 0x10011813ull;
+
+
+static const uint64_t P9N2_EQ_PPE_XIDBGPRO = 0x10012015ull;
+//DUPS: 10012015,
+static const uint64_t P9N2_EQ_0_PPE_XIDBGPRO = 0x10012015ull;
+//DUPS: 10012015,
+static const uint64_t P9N2_EQ_1_PPE_XIDBGPRO = 0x11012015ull;
+//DUPS: 11012015,
+static const uint64_t P9N2_EQ_2_PPE_XIDBGPRO = 0x12012015ull;
+//DUPS: 12012015,
+static const uint64_t P9N2_EQ_3_PPE_XIDBGPRO = 0x13012015ull;
+//DUPS: 13012015,
+static const uint64_t P9N2_EQ_4_PPE_XIDBGPRO = 0x14012015ull;
+//DUPS: 14012015,
+static const uint64_t P9N2_EQ_5_PPE_XIDBGPRO = 0x15012015ull;
+//DUPS: 15012015,
+static const uint64_t P9N2_EX_PPE_XIDBGPRO = 0x10012015ull;
+
+static const uint64_t P9N2_EX_0_PPE_XIDBGPRO = 0x10012015ull;
+
+static const uint64_t P9N2_EX_1_PPE_XIDBGPRO = 0x10012415ull;
+
+static const uint64_t P9N2_EX_2_PPE_XIDBGPRO = 0x11012015ull;
+
+static const uint64_t P9N2_EX_3_PPE_XIDBGPRO = 0x11012415ull;
+
+static const uint64_t P9N2_EX_4_PPE_XIDBGPRO = 0x12012015ull;
+
+static const uint64_t P9N2_EX_5_PPE_XIDBGPRO = 0x12012415ull;
+
+static const uint64_t P9N2_EX_6_PPE_XIDBGPRO = 0x13012015ull;
+
+static const uint64_t P9N2_EX_7_PPE_XIDBGPRO = 0x13012415ull;
+
+static const uint64_t P9N2_EX_8_PPE_XIDBGPRO = 0x14012015ull;
+
+static const uint64_t P9N2_EX_9_PPE_XIDBGPRO = 0x14012415ull;
+
+static const uint64_t P9N2_EX_10_PPE_XIDBGPRO = 0x15012015ull;
+
+static const uint64_t P9N2_EX_11_PPE_XIDBGPRO = 0x15012415ull;
+
+
+static const uint64_t P9N2_EQ_PPE_XIRAMDBG = 0x10012013ull;
+//DUPS: 10012013,
+static const uint64_t P9N2_EQ_0_PPE_XIRAMDBG = 0x10012013ull;
+//DUPS: 10012013,
+static const uint64_t P9N2_EQ_1_PPE_XIRAMDBG = 0x11012013ull;
+//DUPS: 11012013,
+static const uint64_t P9N2_EQ_2_PPE_XIRAMDBG = 0x12012013ull;
+//DUPS: 12012013,
+static const uint64_t P9N2_EQ_3_PPE_XIRAMDBG = 0x13012013ull;
+//DUPS: 13012013,
+static const uint64_t P9N2_EQ_4_PPE_XIRAMDBG = 0x14012013ull;
+//DUPS: 14012013,
+static const uint64_t P9N2_EQ_5_PPE_XIRAMDBG = 0x15012013ull;
+//DUPS: 15012013,
+static const uint64_t P9N2_EX_PPE_XIRAMDBG = 0x10012013ull;
+
+static const uint64_t P9N2_EX_0_PPE_XIRAMDBG = 0x10012013ull;
+
+static const uint64_t P9N2_EX_1_PPE_XIRAMDBG = 0x10012413ull;
+
+static const uint64_t P9N2_EX_2_PPE_XIRAMDBG = 0x11012013ull;
+
+static const uint64_t P9N2_EX_3_PPE_XIRAMDBG = 0x11012413ull;
+
+static const uint64_t P9N2_EX_4_PPE_XIRAMDBG = 0x12012013ull;
+
+static const uint64_t P9N2_EX_5_PPE_XIRAMDBG = 0x12012413ull;
+
+static const uint64_t P9N2_EX_6_PPE_XIRAMDBG = 0x13012013ull;
+
+static const uint64_t P9N2_EX_7_PPE_XIRAMDBG = 0x13012413ull;
+
+static const uint64_t P9N2_EX_8_PPE_XIRAMDBG = 0x14012013ull;
+
+static const uint64_t P9N2_EX_9_PPE_XIRAMDBG = 0x14012413ull;
+
+static const uint64_t P9N2_EX_10_PPE_XIRAMDBG = 0x15012013ull;
+
+static const uint64_t P9N2_EX_11_PPE_XIRAMDBG = 0x15012413ull;
+
+
+static const uint64_t P9N2_EQ_PPE_XIRAMEDR = 0x10012014ull;
+//DUPS: 10012014,
+static const uint64_t P9N2_EQ_0_PPE_XIRAMEDR = 0x10012014ull;
+//DUPS: 10012014,
+static const uint64_t P9N2_EQ_1_PPE_XIRAMEDR = 0x11012014ull;
+//DUPS: 11012014,
+static const uint64_t P9N2_EQ_2_PPE_XIRAMEDR = 0x12012014ull;
+//DUPS: 12012014,
+static const uint64_t P9N2_EQ_3_PPE_XIRAMEDR = 0x13012014ull;
+//DUPS: 13012014,
+static const uint64_t P9N2_EQ_4_PPE_XIRAMEDR = 0x14012014ull;
+//DUPS: 14012014,
+static const uint64_t P9N2_EQ_5_PPE_XIRAMEDR = 0x15012014ull;
+//DUPS: 15012014,
+static const uint64_t P9N2_EX_PPE_XIRAMEDR = 0x10012014ull;
+
+static const uint64_t P9N2_EX_0_PPE_XIRAMEDR = 0x10012014ull;
+
+static const uint64_t P9N2_EX_1_PPE_XIRAMEDR = 0x10012414ull;
+
+static const uint64_t P9N2_EX_2_PPE_XIRAMEDR = 0x11012014ull;
+
+static const uint64_t P9N2_EX_3_PPE_XIRAMEDR = 0x11012414ull;
+
+static const uint64_t P9N2_EX_4_PPE_XIRAMEDR = 0x12012014ull;
+
+static const uint64_t P9N2_EX_5_PPE_XIRAMEDR = 0x12012414ull;
+
+static const uint64_t P9N2_EX_6_PPE_XIRAMEDR = 0x13012014ull;
+
+static const uint64_t P9N2_EX_7_PPE_XIRAMEDR = 0x13012414ull;
+
+static const uint64_t P9N2_EX_8_PPE_XIRAMEDR = 0x14012014ull;
+
+static const uint64_t P9N2_EX_9_PPE_XIRAMEDR = 0x14012414ull;
+
+static const uint64_t P9N2_EX_10_PPE_XIRAMEDR = 0x15012014ull;
+
+static const uint64_t P9N2_EX_11_PPE_XIRAMEDR = 0x15012414ull;
+
+
+static const uint64_t P9N2_EQ_PPE_XIRAMGA = 0x10012012ull;
+//DUPS: 10012012,
+static const uint64_t P9N2_EQ_0_PPE_XIRAMGA = 0x10012012ull;
+//DUPS: 10012012,
+static const uint64_t P9N2_EQ_1_PPE_XIRAMGA = 0x11012012ull;
+//DUPS: 11012012,
+static const uint64_t P9N2_EQ_2_PPE_XIRAMGA = 0x12012012ull;
+//DUPS: 12012012,
+static const uint64_t P9N2_EQ_3_PPE_XIRAMGA = 0x13012012ull;
+//DUPS: 13012012,
+static const uint64_t P9N2_EQ_4_PPE_XIRAMGA = 0x14012012ull;
+//DUPS: 14012012,
+static const uint64_t P9N2_EQ_5_PPE_XIRAMGA = 0x15012012ull;
+//DUPS: 15012012,
+static const uint64_t P9N2_EX_PPE_XIRAMGA = 0x10012012ull;
+
+static const uint64_t P9N2_EX_0_PPE_XIRAMGA = 0x10012012ull;
+
+static const uint64_t P9N2_EX_1_PPE_XIRAMGA = 0x10012412ull;
+
+static const uint64_t P9N2_EX_2_PPE_XIRAMGA = 0x11012012ull;
+
+static const uint64_t P9N2_EX_3_PPE_XIRAMGA = 0x11012412ull;
+
+static const uint64_t P9N2_EX_4_PPE_XIRAMGA = 0x12012012ull;
+
+static const uint64_t P9N2_EX_5_PPE_XIRAMGA = 0x12012412ull;
+
+static const uint64_t P9N2_EX_6_PPE_XIRAMGA = 0x13012012ull;
+
+static const uint64_t P9N2_EX_7_PPE_XIRAMGA = 0x13012412ull;
+
+static const uint64_t P9N2_EX_8_PPE_XIRAMGA = 0x14012012ull;
+
+static const uint64_t P9N2_EX_9_PPE_XIRAMGA = 0x14012412ull;
+
+static const uint64_t P9N2_EX_10_PPE_XIRAMGA = 0x15012012ull;
+
+static const uint64_t P9N2_EX_11_PPE_XIRAMGA = 0x15012412ull;
+
+
+static const uint64_t P9N2_EQ_PPE_XIRAMRA = 0x10012011ull;
+//DUPS: 10012011,
+static const uint64_t P9N2_EQ_0_PPE_XIRAMRA = 0x10012011ull;
+//DUPS: 10012011,
+static const uint64_t P9N2_EQ_1_PPE_XIRAMRA = 0x11012011ull;
+//DUPS: 11012011,
+static const uint64_t P9N2_EQ_2_PPE_XIRAMRA = 0x12012011ull;
+//DUPS: 12012011,
+static const uint64_t P9N2_EQ_3_PPE_XIRAMRA = 0x13012011ull;
+//DUPS: 13012011,
+static const uint64_t P9N2_EQ_4_PPE_XIRAMRA = 0x14012011ull;
+//DUPS: 14012011,
+static const uint64_t P9N2_EQ_5_PPE_XIRAMRA = 0x15012011ull;
+//DUPS: 15012011,
+static const uint64_t P9N2_EX_PPE_XIRAMRA = 0x10012011ull;
+
+static const uint64_t P9N2_EX_0_PPE_XIRAMRA = 0x10012011ull;
+
+static const uint64_t P9N2_EX_1_PPE_XIRAMRA = 0x10012411ull;
+
+static const uint64_t P9N2_EX_2_PPE_XIRAMRA = 0x11012011ull;
+
+static const uint64_t P9N2_EX_3_PPE_XIRAMRA = 0x11012411ull;
+
+static const uint64_t P9N2_EX_4_PPE_XIRAMRA = 0x12012011ull;
+
+static const uint64_t P9N2_EX_5_PPE_XIRAMRA = 0x12012411ull;
+
+static const uint64_t P9N2_EX_6_PPE_XIRAMRA = 0x13012011ull;
+
+static const uint64_t P9N2_EX_7_PPE_XIRAMRA = 0x13012411ull;
+
+static const uint64_t P9N2_EX_8_PPE_XIRAMRA = 0x14012011ull;
+
+static const uint64_t P9N2_EX_9_PPE_XIRAMRA = 0x14012411ull;
+
+static const uint64_t P9N2_EX_10_PPE_XIRAMRA = 0x15012011ull;
+
+static const uint64_t P9N2_EX_11_PPE_XIRAMRA = 0x15012411ull;
+
+
+static const uint64_t P9N2_EQ_PPE_XIXCR = 0x10012010ull;
+//DUPS: 10012010,
+static const uint64_t P9N2_EQ_0_PPE_XIXCR = 0x10012010ull;
+//DUPS: 10012010,
+static const uint64_t P9N2_EQ_1_PPE_XIXCR = 0x11012010ull;
+//DUPS: 11012010,
+static const uint64_t P9N2_EQ_2_PPE_XIXCR = 0x12012010ull;
+//DUPS: 12012010,
+static const uint64_t P9N2_EQ_3_PPE_XIXCR = 0x13012010ull;
+//DUPS: 13012010,
+static const uint64_t P9N2_EQ_4_PPE_XIXCR = 0x14012010ull;
+//DUPS: 14012010,
+static const uint64_t P9N2_EQ_5_PPE_XIXCR = 0x15012010ull;
+//DUPS: 15012010,
+static const uint64_t P9N2_EX_PPE_XIXCR = 0x10012010ull;
+
+static const uint64_t P9N2_EX_0_PPE_XIXCR = 0x10012010ull;
+
+static const uint64_t P9N2_EX_1_PPE_XIXCR = 0x10012410ull;
+
+static const uint64_t P9N2_EX_2_PPE_XIXCR = 0x11012010ull;
+
+static const uint64_t P9N2_EX_3_PPE_XIXCR = 0x11012410ull;
+
+static const uint64_t P9N2_EX_4_PPE_XIXCR = 0x12012010ull;
+
+static const uint64_t P9N2_EX_5_PPE_XIXCR = 0x12012410ull;
+
+static const uint64_t P9N2_EX_6_PPE_XIXCR = 0x13012010ull;
+
+static const uint64_t P9N2_EX_7_PPE_XIXCR = 0x13012410ull;
+
+static const uint64_t P9N2_EX_8_PPE_XIXCR = 0x14012010ull;
+
+static const uint64_t P9N2_EX_9_PPE_XIXCR = 0x14012410ull;
+
+static const uint64_t P9N2_EX_10_PPE_XIXCR = 0x15012010ull;
+
+static const uint64_t P9N2_EX_11_PPE_XIXCR = 0x15012410ull;
+
+
+static const uint64_t P9N2_C_PPM_CGCR = 0x200F0164ull;
+
+static const uint64_t P9N2_C_0_PPM_CGCR = 0x200F0164ull;
+
+static const uint64_t P9N2_C_1_PPM_CGCR = 0x210F0164ull;
+
+static const uint64_t P9N2_C_2_PPM_CGCR = 0x220F0164ull;
+
+static const uint64_t P9N2_C_3_PPM_CGCR = 0x230F0164ull;
+
+static const uint64_t P9N2_C_4_PPM_CGCR = 0x240F0164ull;
+
+static const uint64_t P9N2_C_5_PPM_CGCR = 0x250F0164ull;
+
+static const uint64_t P9N2_C_6_PPM_CGCR = 0x260F0164ull;
+
+static const uint64_t P9N2_C_7_PPM_CGCR = 0x270F0164ull;
+
+static const uint64_t P9N2_C_8_PPM_CGCR = 0x280F0164ull;
+
+static const uint64_t P9N2_C_9_PPM_CGCR = 0x290F0164ull;
+
+static const uint64_t P9N2_C_10_PPM_CGCR = 0x2A0F0164ull;
+
+static const uint64_t P9N2_C_11_PPM_CGCR = 0x2B0F0164ull;
+
+static const uint64_t P9N2_C_12_PPM_CGCR = 0x2C0F0164ull;
+
+static const uint64_t P9N2_C_13_PPM_CGCR = 0x2D0F0164ull;
+
+static const uint64_t P9N2_C_14_PPM_CGCR = 0x2E0F0164ull;
+
+static const uint64_t P9N2_C_15_PPM_CGCR = 0x2F0F0164ull;
+
+static const uint64_t P9N2_C_16_PPM_CGCR = 0x300F0164ull;
+
+static const uint64_t P9N2_C_17_PPM_CGCR = 0x310F0164ull;
+
+static const uint64_t P9N2_C_18_PPM_CGCR = 0x320F0164ull;
+
+static const uint64_t P9N2_C_19_PPM_CGCR = 0x330F0164ull;
+
+static const uint64_t P9N2_C_20_PPM_CGCR = 0x340F0164ull;
+
+static const uint64_t P9N2_C_21_PPM_CGCR = 0x350F0164ull;
+
+static const uint64_t P9N2_C_22_PPM_CGCR = 0x360F0164ull;
+
+static const uint64_t P9N2_C_23_PPM_CGCR = 0x370F0164ull;
+
+static const uint64_t P9N2_EQ_PPM_CGCR = 0x100F0164ull;
+
+static const uint64_t P9N2_EQ_0_PPM_CGCR = 0x100F0164ull;
+
+static const uint64_t P9N2_EQ_1_PPM_CGCR = 0x110F0164ull;
+
+static const uint64_t P9N2_EQ_2_PPM_CGCR = 0x120F0164ull;
+
+static const uint64_t P9N2_EQ_3_PPM_CGCR = 0x130F0164ull;
+
+static const uint64_t P9N2_EQ_4_PPM_CGCR = 0x140F0164ull;
+
+static const uint64_t P9N2_EQ_5_PPM_CGCR = 0x150F0164ull;
+
+static const uint64_t P9N2_EX_PPM_CGCR = 0x200F0164ull;
+//DUPS: 210F0164,
+static const uint64_t P9N2_EX_0_PPM_CGCR = 0x200F0164ull;
+//DUPS: 210F0164,
+static const uint64_t P9N2_EX_1_PPM_CGCR = 0x220F0164ull;
+//DUPS: 220F0164,
+static const uint64_t P9N2_EX_2_PPM_CGCR = 0x240F0164ull;
+//DUPS: 250F0164,
+static const uint64_t P9N2_EX_3_PPM_CGCR = 0x260F0164ull;
+//DUPS: 270F0164,
+static const uint64_t P9N2_EX_4_PPM_CGCR = 0x280F0164ull;
+//DUPS: 290F0164,
+static const uint64_t P9N2_EX_5_PPM_CGCR = 0x2A0F0164ull;
+//DUPS: 2B0F0164,
+static const uint64_t P9N2_EX_6_PPM_CGCR = 0x2C0F0164ull;
+//DUPS: 2D0F0164,
+static const uint64_t P9N2_EX_7_PPM_CGCR = 0x2E0F0164ull;
+//DUPS: 2F0F0164,
+static const uint64_t P9N2_EX_8_PPM_CGCR = 0x300F0164ull;
+//DUPS: 310F0164,
+static const uint64_t P9N2_EX_9_PPM_CGCR = 0x320F0164ull;
+//DUPS: 330F0164,
+static const uint64_t P9N2_EX_10_PPM_CGCR = 0x340F0164ull;
+//DUPS: 350F0164,
+static const uint64_t P9N2_EX_11_PPM_CGCR = 0x360F0164ull;
+//DUPS: 370F0164,
+
+static const uint64_t P9N2_C_PPM_GPMMR_SCOM = 0x200F0100ull;
+
+static const uint64_t P9N2_C_PPM_GPMMR_SCOM1 = 0x200F0101ull;
+
+static const uint64_t P9N2_C_PPM_GPMMR_SCOM2 = 0x200F0102ull;
+
+static const uint64_t P9N2_C_0_PPM_GPMMR_SCOM = 0x200F0100ull;
+
+static const uint64_t P9N2_C_0_PPM_GPMMR_SCOM1 = 0x200F0101ull;
+
+static const uint64_t P9N2_C_0_PPM_GPMMR_SCOM2 = 0x200F0102ull;
+
+static const uint64_t P9N2_C_1_PPM_GPMMR_SCOM = 0x210F0100ull;
+
+static const uint64_t P9N2_C_1_PPM_GPMMR_SCOM1 = 0x210F0101ull;
+
+static const uint64_t P9N2_C_1_PPM_GPMMR_SCOM2 = 0x210F0102ull;
+
+static const uint64_t P9N2_C_2_PPM_GPMMR_SCOM = 0x220F0100ull;
+
+static const uint64_t P9N2_C_2_PPM_GPMMR_SCOM1 = 0x220F0101ull;
+
+static const uint64_t P9N2_C_2_PPM_GPMMR_SCOM2 = 0x220F0102ull;
+
+static const uint64_t P9N2_C_3_PPM_GPMMR_SCOM = 0x230F0100ull;
+
+static const uint64_t P9N2_C_3_PPM_GPMMR_SCOM1 = 0x230F0101ull;
+
+static const uint64_t P9N2_C_3_PPM_GPMMR_SCOM2 = 0x230F0102ull;
+
+static const uint64_t P9N2_C_4_PPM_GPMMR_SCOM = 0x240F0100ull;
+
+static const uint64_t P9N2_C_4_PPM_GPMMR_SCOM1 = 0x240F0101ull;
+
+static const uint64_t P9N2_C_4_PPM_GPMMR_SCOM2 = 0x240F0102ull;
+
+static const uint64_t P9N2_C_5_PPM_GPMMR_SCOM = 0x250F0100ull;
+
+static const uint64_t P9N2_C_5_PPM_GPMMR_SCOM1 = 0x250F0101ull;
+
+static const uint64_t P9N2_C_5_PPM_GPMMR_SCOM2 = 0x250F0102ull;
+
+static const uint64_t P9N2_C_6_PPM_GPMMR_SCOM = 0x260F0100ull;
+
+static const uint64_t P9N2_C_6_PPM_GPMMR_SCOM1 = 0x260F0101ull;
+
+static const uint64_t P9N2_C_6_PPM_GPMMR_SCOM2 = 0x260F0102ull;
+
+static const uint64_t P9N2_C_7_PPM_GPMMR_SCOM = 0x270F0100ull;
+
+static const uint64_t P9N2_C_7_PPM_GPMMR_SCOM1 = 0x270F0101ull;
+
+static const uint64_t P9N2_C_7_PPM_GPMMR_SCOM2 = 0x270F0102ull;
+
+static const uint64_t P9N2_C_8_PPM_GPMMR_SCOM = 0x280F0100ull;
+
+static const uint64_t P9N2_C_8_PPM_GPMMR_SCOM1 = 0x280F0101ull;
+
+static const uint64_t P9N2_C_8_PPM_GPMMR_SCOM2 = 0x280F0102ull;
+
+static const uint64_t P9N2_C_9_PPM_GPMMR_SCOM = 0x290F0100ull;
+
+static const uint64_t P9N2_C_9_PPM_GPMMR_SCOM1 = 0x290F0101ull;
+
+static const uint64_t P9N2_C_9_PPM_GPMMR_SCOM2 = 0x290F0102ull;
+
+static const uint64_t P9N2_C_10_PPM_GPMMR_SCOM = 0x2A0F0100ull;
+
+static const uint64_t P9N2_C_10_PPM_GPMMR_SCOM1 = 0x2A0F0101ull;
+
+static const uint64_t P9N2_C_10_PPM_GPMMR_SCOM2 = 0x2A0F0102ull;
+
+static const uint64_t P9N2_C_11_PPM_GPMMR_SCOM = 0x2B0F0100ull;
+
+static const uint64_t P9N2_C_11_PPM_GPMMR_SCOM1 = 0x2B0F0101ull;
+
+static const uint64_t P9N2_C_11_PPM_GPMMR_SCOM2 = 0x2B0F0102ull;
+
+static const uint64_t P9N2_C_12_PPM_GPMMR_SCOM = 0x2C0F0100ull;
+
+static const uint64_t P9N2_C_12_PPM_GPMMR_SCOM1 = 0x2C0F0101ull;
+
+static const uint64_t P9N2_C_12_PPM_GPMMR_SCOM2 = 0x2C0F0102ull;
+
+static const uint64_t P9N2_C_13_PPM_GPMMR_SCOM = 0x2D0F0100ull;
+
+static const uint64_t P9N2_C_13_PPM_GPMMR_SCOM1 = 0x2D0F0101ull;
+
+static const uint64_t P9N2_C_13_PPM_GPMMR_SCOM2 = 0x2D0F0102ull;
+
+static const uint64_t P9N2_C_14_PPM_GPMMR_SCOM = 0x2E0F0100ull;
+
+static const uint64_t P9N2_C_14_PPM_GPMMR_SCOM1 = 0x2E0F0101ull;
+
+static const uint64_t P9N2_C_14_PPM_GPMMR_SCOM2 = 0x2E0F0102ull;
+
+static const uint64_t P9N2_C_15_PPM_GPMMR_SCOM = 0x2F0F0100ull;
+
+static const uint64_t P9N2_C_15_PPM_GPMMR_SCOM1 = 0x2F0F0101ull;
+
+static const uint64_t P9N2_C_15_PPM_GPMMR_SCOM2 = 0x2F0F0102ull;
+
+static const uint64_t P9N2_C_16_PPM_GPMMR_SCOM = 0x300F0100ull;
+
+static const uint64_t P9N2_C_16_PPM_GPMMR_SCOM1 = 0x300F0101ull;
+
+static const uint64_t P9N2_C_16_PPM_GPMMR_SCOM2 = 0x300F0102ull;
+
+static const uint64_t P9N2_C_17_PPM_GPMMR_SCOM = 0x310F0100ull;
+
+static const uint64_t P9N2_C_17_PPM_GPMMR_SCOM1 = 0x310F0101ull;
+
+static const uint64_t P9N2_C_17_PPM_GPMMR_SCOM2 = 0x310F0102ull;
+
+static const uint64_t P9N2_C_18_PPM_GPMMR_SCOM = 0x320F0100ull;
+
+static const uint64_t P9N2_C_18_PPM_GPMMR_SCOM1 = 0x320F0101ull;
+
+static const uint64_t P9N2_C_18_PPM_GPMMR_SCOM2 = 0x320F0102ull;
+
+static const uint64_t P9N2_C_19_PPM_GPMMR_SCOM = 0x330F0100ull;
+
+static const uint64_t P9N2_C_19_PPM_GPMMR_SCOM1 = 0x330F0101ull;
+
+static const uint64_t P9N2_C_19_PPM_GPMMR_SCOM2 = 0x330F0102ull;
+
+static const uint64_t P9N2_C_20_PPM_GPMMR_SCOM = 0x340F0100ull;
+
+static const uint64_t P9N2_C_20_PPM_GPMMR_SCOM1 = 0x340F0101ull;
+
+static const uint64_t P9N2_C_20_PPM_GPMMR_SCOM2 = 0x340F0102ull;
+
+static const uint64_t P9N2_C_21_PPM_GPMMR_SCOM = 0x350F0100ull;
+
+static const uint64_t P9N2_C_21_PPM_GPMMR_SCOM1 = 0x350F0101ull;
+
+static const uint64_t P9N2_C_21_PPM_GPMMR_SCOM2 = 0x350F0102ull;
+
+static const uint64_t P9N2_C_22_PPM_GPMMR_SCOM = 0x360F0100ull;
+
+static const uint64_t P9N2_C_22_PPM_GPMMR_SCOM1 = 0x360F0101ull;
+
+static const uint64_t P9N2_C_22_PPM_GPMMR_SCOM2 = 0x360F0102ull;
+
+static const uint64_t P9N2_C_23_PPM_GPMMR_SCOM = 0x370F0100ull;
+
+static const uint64_t P9N2_C_23_PPM_GPMMR_SCOM1 = 0x370F0101ull;
+
+static const uint64_t P9N2_C_23_PPM_GPMMR_SCOM2 = 0x370F0102ull;
+
+static const uint64_t P9N2_EQ_PPM_GPMMR_SCOM = 0x100F0100ull;
+
+static const uint64_t P9N2_EQ_PPM_GPMMR_SCOM1 = 0x100F0101ull;
+
+static const uint64_t P9N2_EQ_PPM_GPMMR_SCOM2 = 0x100F0102ull;
+
+static const uint64_t P9N2_EQ_0_PPM_GPMMR_SCOM = 0x100F0100ull;
+
+static const uint64_t P9N2_EQ_0_PPM_GPMMR_SCOM1 = 0x100F0101ull;
+
+static const uint64_t P9N2_EQ_0_PPM_GPMMR_SCOM2 = 0x100F0102ull;
+
+static const uint64_t P9N2_EQ_1_PPM_GPMMR_SCOM = 0x110F0100ull;
+
+static const uint64_t P9N2_EQ_1_PPM_GPMMR_SCOM1 = 0x110F0101ull;
+
+static const uint64_t P9N2_EQ_1_PPM_GPMMR_SCOM2 = 0x110F0102ull;
+
+static const uint64_t P9N2_EQ_2_PPM_GPMMR_SCOM = 0x120F0100ull;
+
+static const uint64_t P9N2_EQ_2_PPM_GPMMR_SCOM1 = 0x120F0101ull;
+
+static const uint64_t P9N2_EQ_2_PPM_GPMMR_SCOM2 = 0x120F0102ull;
+
+static const uint64_t P9N2_EQ_3_PPM_GPMMR_SCOM = 0x130F0100ull;
+
+static const uint64_t P9N2_EQ_3_PPM_GPMMR_SCOM1 = 0x130F0101ull;
+
+static const uint64_t P9N2_EQ_3_PPM_GPMMR_SCOM2 = 0x130F0102ull;
+
+static const uint64_t P9N2_EQ_4_PPM_GPMMR_SCOM = 0x140F0100ull;
+
+static const uint64_t P9N2_EQ_4_PPM_GPMMR_SCOM1 = 0x140F0101ull;
+
+static const uint64_t P9N2_EQ_4_PPM_GPMMR_SCOM2 = 0x140F0102ull;
+
+static const uint64_t P9N2_EQ_5_PPM_GPMMR_SCOM = 0x150F0100ull;
+
+static const uint64_t P9N2_EQ_5_PPM_GPMMR_SCOM1 = 0x150F0101ull;
+
+static const uint64_t P9N2_EQ_5_PPM_GPMMR_SCOM2 = 0x150F0102ull;
+
+static const uint64_t P9N2_EX_PPM_GPMMR_SCOM = 0x200F0100ull;
+//DUPS: 210F0100,
+static const uint64_t P9N2_EX_PPM_GPMMR_SCOM1 = 0x200F0101ull;
+//DUPS: 210F0101,
+static const uint64_t P9N2_EX_PPM_GPMMR_SCOM2 = 0x200F0102ull;
+//DUPS: 210F0102,
+static const uint64_t P9N2_EX_0_PPM_GPMMR_SCOM = 0x200F0100ull;
+//DUPS: 210F0100,
+static const uint64_t P9N2_EX_0_PPM_GPMMR_SCOM1 = 0x200F0101ull;
+//DUPS: 210F0101,
+static const uint64_t P9N2_EX_0_PPM_GPMMR_SCOM2 = 0x200F0102ull;
+//DUPS: 210F0102,
+static const uint64_t P9N2_EX_1_PPM_GPMMR_SCOM = 0x220F0100ull;
+//DUPS: 220F0100,
+static const uint64_t P9N2_EX_1_PPM_GPMMR_SCOM1 = 0x220F0101ull;
+//DUPS: 220F0101,
+static const uint64_t P9N2_EX_1_PPM_GPMMR_SCOM2 = 0x220F0102ull;
+//DUPS: 220F0102,
+static const uint64_t P9N2_EX_2_PPM_GPMMR_SCOM = 0x240F0100ull;
+//DUPS: 250F0100,
+static const uint64_t P9N2_EX_2_PPM_GPMMR_SCOM1 = 0x240F0101ull;
+//DUPS: 250F0101,
+static const uint64_t P9N2_EX_2_PPM_GPMMR_SCOM2 = 0x240F0102ull;
+//DUPS: 250F0102,
+static const uint64_t P9N2_EX_3_PPM_GPMMR_SCOM = 0x260F0100ull;
+//DUPS: 270F0100,
+static const uint64_t P9N2_EX_3_PPM_GPMMR_SCOM1 = 0x260F0101ull;
+//DUPS: 270F0101,
+static const uint64_t P9N2_EX_3_PPM_GPMMR_SCOM2 = 0x260F0102ull;
+//DUPS: 270F0102,
+static const uint64_t P9N2_EX_4_PPM_GPMMR_SCOM = 0x280F0100ull;
+//DUPS: 290F0100,
+static const uint64_t P9N2_EX_4_PPM_GPMMR_SCOM1 = 0x280F0101ull;
+//DUPS: 290F0101,
+static const uint64_t P9N2_EX_4_PPM_GPMMR_SCOM2 = 0x280F0102ull;
+//DUPS: 290F0102,
+static const uint64_t P9N2_EX_5_PPM_GPMMR_SCOM = 0x2A0F0100ull;
+//DUPS: 2B0F0100,
+static const uint64_t P9N2_EX_5_PPM_GPMMR_SCOM1 = 0x2A0F0101ull;
+//DUPS: 2B0F0101,
+static const uint64_t P9N2_EX_5_PPM_GPMMR_SCOM2 = 0x2A0F0102ull;
+//DUPS: 2B0F0102,
+static const uint64_t P9N2_EX_6_PPM_GPMMR_SCOM = 0x2C0F0100ull;
+//DUPS: 2D0F0100,
+static const uint64_t P9N2_EX_6_PPM_GPMMR_SCOM1 = 0x2C0F0101ull;
+//DUPS: 2D0F0101,
+static const uint64_t P9N2_EX_6_PPM_GPMMR_SCOM2 = 0x2C0F0102ull;
+//DUPS: 2D0F0102,
+static const uint64_t P9N2_EX_7_PPM_GPMMR_SCOM = 0x2E0F0100ull;
+//DUPS: 2F0F0100,
+static const uint64_t P9N2_EX_7_PPM_GPMMR_SCOM1 = 0x2E0F0101ull;
+//DUPS: 2F0F0101,
+static const uint64_t P9N2_EX_7_PPM_GPMMR_SCOM2 = 0x2E0F0102ull;
+//DUPS: 2F0F0102,
+static const uint64_t P9N2_EX_8_PPM_GPMMR_SCOM = 0x300F0100ull;
+//DUPS: 310F0100,
+static const uint64_t P9N2_EX_8_PPM_GPMMR_SCOM1 = 0x300F0101ull;
+//DUPS: 310F0101,
+static const uint64_t P9N2_EX_8_PPM_GPMMR_SCOM2 = 0x300F0102ull;
+//DUPS: 310F0102,
+static const uint64_t P9N2_EX_9_PPM_GPMMR_SCOM = 0x320F0100ull;
+//DUPS: 330F0100,
+static const uint64_t P9N2_EX_9_PPM_GPMMR_SCOM1 = 0x320F0101ull;
+//DUPS: 330F0101,
+static const uint64_t P9N2_EX_9_PPM_GPMMR_SCOM2 = 0x320F0102ull;
+//DUPS: 330F0102,
+static const uint64_t P9N2_EX_10_PPM_GPMMR_SCOM = 0x340F0100ull;
+//DUPS: 350F0100,
+static const uint64_t P9N2_EX_10_PPM_GPMMR_SCOM1 = 0x340F0101ull;
+//DUPS: 350F0101,
+static const uint64_t P9N2_EX_10_PPM_GPMMR_SCOM2 = 0x340F0102ull;
+//DUPS: 350F0102,
+static const uint64_t P9N2_EX_11_PPM_GPMMR_SCOM = 0x360F0100ull;
+//DUPS: 370F0100,
+static const uint64_t P9N2_EX_11_PPM_GPMMR_SCOM1 = 0x360F0101ull;
+//DUPS: 370F0101,
+static const uint64_t P9N2_EX_11_PPM_GPMMR_SCOM2 = 0x360F0102ull;
+//DUPS: 370F0102,
+
+static const uint64_t P9N2_C_PPM_IVRMAVR = 0x200F01B5ull;
+
+static const uint64_t P9N2_C_0_PPM_IVRMAVR = 0x200F01B5ull;
+
+static const uint64_t P9N2_C_1_PPM_IVRMAVR = 0x210F01B5ull;
+
+static const uint64_t P9N2_C_2_PPM_IVRMAVR = 0x220F01B5ull;
+
+static const uint64_t P9N2_C_3_PPM_IVRMAVR = 0x230F01B5ull;
+
+static const uint64_t P9N2_C_4_PPM_IVRMAVR = 0x240F01B5ull;
+
+static const uint64_t P9N2_C_5_PPM_IVRMAVR = 0x250F01B5ull;
+
+static const uint64_t P9N2_C_6_PPM_IVRMAVR = 0x260F01B5ull;
+
+static const uint64_t P9N2_C_7_PPM_IVRMAVR = 0x270F01B5ull;
+
+static const uint64_t P9N2_C_8_PPM_IVRMAVR = 0x280F01B5ull;
+
+static const uint64_t P9N2_C_9_PPM_IVRMAVR = 0x290F01B5ull;
+
+static const uint64_t P9N2_C_10_PPM_IVRMAVR = 0x2A0F01B5ull;
+
+static const uint64_t P9N2_C_11_PPM_IVRMAVR = 0x2B0F01B5ull;
+
+static const uint64_t P9N2_C_12_PPM_IVRMAVR = 0x2C0F01B5ull;
+
+static const uint64_t P9N2_C_13_PPM_IVRMAVR = 0x2D0F01B5ull;
+
+static const uint64_t P9N2_C_14_PPM_IVRMAVR = 0x2E0F01B5ull;
+
+static const uint64_t P9N2_C_15_PPM_IVRMAVR = 0x2F0F01B5ull;
+
+static const uint64_t P9N2_C_16_PPM_IVRMAVR = 0x300F01B5ull;
+
+static const uint64_t P9N2_C_17_PPM_IVRMAVR = 0x310F01B5ull;
+
+static const uint64_t P9N2_C_18_PPM_IVRMAVR = 0x320F01B5ull;
+
+static const uint64_t P9N2_C_19_PPM_IVRMAVR = 0x330F01B5ull;
+
+static const uint64_t P9N2_C_20_PPM_IVRMAVR = 0x340F01B5ull;
+
+static const uint64_t P9N2_C_21_PPM_IVRMAVR = 0x350F01B5ull;
+
+static const uint64_t P9N2_C_22_PPM_IVRMAVR = 0x360F01B5ull;
+
+static const uint64_t P9N2_C_23_PPM_IVRMAVR = 0x370F01B5ull;
+
+static const uint64_t P9N2_EQ_PPM_IVRMAVR = 0x100F01B5ull;
+
+static const uint64_t P9N2_EQ_0_PPM_IVRMAVR = 0x100F01B5ull;
+
+static const uint64_t P9N2_EQ_1_PPM_IVRMAVR = 0x110F01B5ull;
+
+static const uint64_t P9N2_EQ_2_PPM_IVRMAVR = 0x120F01B5ull;
+
+static const uint64_t P9N2_EQ_3_PPM_IVRMAVR = 0x130F01B5ull;
+
+static const uint64_t P9N2_EQ_4_PPM_IVRMAVR = 0x140F01B5ull;
+
+static const uint64_t P9N2_EQ_5_PPM_IVRMAVR = 0x150F01B5ull;
+
+static const uint64_t P9N2_EX_PPM_IVRMAVR = 0x200F01B5ull;
+//DUPS: 210F01B5,
+static const uint64_t P9N2_EX_0_PPM_IVRMAVR = 0x200F01B5ull;
+//DUPS: 210F01B5,
+static const uint64_t P9N2_EX_1_PPM_IVRMAVR = 0x220F01B5ull;
+//DUPS: 220F01B5,
+static const uint64_t P9N2_EX_2_PPM_IVRMAVR = 0x240F01B5ull;
+//DUPS: 250F01B5,
+static const uint64_t P9N2_EX_3_PPM_IVRMAVR = 0x260F01B5ull;
+//DUPS: 270F01B5,
+static const uint64_t P9N2_EX_4_PPM_IVRMAVR = 0x280F01B5ull;
+//DUPS: 290F01B5,
+static const uint64_t P9N2_EX_5_PPM_IVRMAVR = 0x2A0F01B5ull;
+//DUPS: 2B0F01B5,
+static const uint64_t P9N2_EX_6_PPM_IVRMAVR = 0x2C0F01B5ull;
+//DUPS: 2D0F01B5,
+static const uint64_t P9N2_EX_7_PPM_IVRMAVR = 0x2E0F01B5ull;
+//DUPS: 2F0F01B5,
+static const uint64_t P9N2_EX_8_PPM_IVRMAVR = 0x300F01B5ull;
+//DUPS: 310F01B5,
+static const uint64_t P9N2_EX_9_PPM_IVRMAVR = 0x320F01B5ull;
+//DUPS: 330F01B5,
+static const uint64_t P9N2_EX_10_PPM_IVRMAVR = 0x340F01B5ull;
+//DUPS: 350F01B5,
+static const uint64_t P9N2_EX_11_PPM_IVRMAVR = 0x360F01B5ull;
+//DUPS: 370F01B5,
+
+static const uint64_t P9N2_C_PPM_IVRMCR = 0x200F01B0ull;
+
+static const uint64_t P9N2_C_PPM_IVRMCR_CLEAR = 0x200F01B1ull;
+
+static const uint64_t P9N2_C_PPM_IVRMCR_OR = 0x200F01B2ull;
+
+static const uint64_t P9N2_C_0_PPM_IVRMCR = 0x200F01B0ull;
+
+static const uint64_t P9N2_C_0_PPM_IVRMCR_CLEAR = 0x200F01B1ull;
+
+static const uint64_t P9N2_C_0_PPM_IVRMCR_OR = 0x200F01B2ull;
+
+static const uint64_t P9N2_C_1_PPM_IVRMCR = 0x210F01B0ull;
+
+static const uint64_t P9N2_C_1_PPM_IVRMCR_CLEAR = 0x210F01B1ull;
+
+static const uint64_t P9N2_C_1_PPM_IVRMCR_OR = 0x210F01B2ull;
+
+static const uint64_t P9N2_C_2_PPM_IVRMCR = 0x220F01B0ull;
+
+static const uint64_t P9N2_C_2_PPM_IVRMCR_CLEAR = 0x220F01B1ull;
+
+static const uint64_t P9N2_C_2_PPM_IVRMCR_OR = 0x220F01B2ull;
+
+static const uint64_t P9N2_C_3_PPM_IVRMCR = 0x230F01B0ull;
+
+static const uint64_t P9N2_C_3_PPM_IVRMCR_CLEAR = 0x230F01B1ull;
+
+static const uint64_t P9N2_C_3_PPM_IVRMCR_OR = 0x230F01B2ull;
+
+static const uint64_t P9N2_C_4_PPM_IVRMCR = 0x240F01B0ull;
+
+static const uint64_t P9N2_C_4_PPM_IVRMCR_CLEAR = 0x240F01B1ull;
+
+static const uint64_t P9N2_C_4_PPM_IVRMCR_OR = 0x240F01B2ull;
+
+static const uint64_t P9N2_C_5_PPM_IVRMCR = 0x250F01B0ull;
+
+static const uint64_t P9N2_C_5_PPM_IVRMCR_CLEAR = 0x250F01B1ull;
+
+static const uint64_t P9N2_C_5_PPM_IVRMCR_OR = 0x250F01B2ull;
+
+static const uint64_t P9N2_C_6_PPM_IVRMCR = 0x260F01B0ull;
+
+static const uint64_t P9N2_C_6_PPM_IVRMCR_CLEAR = 0x260F01B1ull;
+
+static const uint64_t P9N2_C_6_PPM_IVRMCR_OR = 0x260F01B2ull;
+
+static const uint64_t P9N2_C_7_PPM_IVRMCR = 0x270F01B0ull;
+
+static const uint64_t P9N2_C_7_PPM_IVRMCR_CLEAR = 0x270F01B1ull;
+
+static const uint64_t P9N2_C_7_PPM_IVRMCR_OR = 0x270F01B2ull;
+
+static const uint64_t P9N2_C_8_PPM_IVRMCR = 0x280F01B0ull;
+
+static const uint64_t P9N2_C_8_PPM_IVRMCR_CLEAR = 0x280F01B1ull;
+
+static const uint64_t P9N2_C_8_PPM_IVRMCR_OR = 0x280F01B2ull;
+
+static const uint64_t P9N2_C_9_PPM_IVRMCR = 0x290F01B0ull;
+
+static const uint64_t P9N2_C_9_PPM_IVRMCR_CLEAR = 0x290F01B1ull;
+
+static const uint64_t P9N2_C_9_PPM_IVRMCR_OR = 0x290F01B2ull;
+
+static const uint64_t P9N2_C_10_PPM_IVRMCR = 0x2A0F01B0ull;
+
+static const uint64_t P9N2_C_10_PPM_IVRMCR_CLEAR = 0x2A0F01B1ull;
+
+static const uint64_t P9N2_C_10_PPM_IVRMCR_OR = 0x2A0F01B2ull;
+
+static const uint64_t P9N2_C_11_PPM_IVRMCR = 0x2B0F01B0ull;
+
+static const uint64_t P9N2_C_11_PPM_IVRMCR_CLEAR = 0x2B0F01B1ull;
+
+static const uint64_t P9N2_C_11_PPM_IVRMCR_OR = 0x2B0F01B2ull;
+
+static const uint64_t P9N2_C_12_PPM_IVRMCR = 0x2C0F01B0ull;
+
+static const uint64_t P9N2_C_12_PPM_IVRMCR_CLEAR = 0x2C0F01B1ull;
+
+static const uint64_t P9N2_C_12_PPM_IVRMCR_OR = 0x2C0F01B2ull;
+
+static const uint64_t P9N2_C_13_PPM_IVRMCR = 0x2D0F01B0ull;
+
+static const uint64_t P9N2_C_13_PPM_IVRMCR_CLEAR = 0x2D0F01B1ull;
+
+static const uint64_t P9N2_C_13_PPM_IVRMCR_OR = 0x2D0F01B2ull;
+
+static const uint64_t P9N2_C_14_PPM_IVRMCR = 0x2E0F01B0ull;
+
+static const uint64_t P9N2_C_14_PPM_IVRMCR_CLEAR = 0x2E0F01B1ull;
+
+static const uint64_t P9N2_C_14_PPM_IVRMCR_OR = 0x2E0F01B2ull;
+
+static const uint64_t P9N2_C_15_PPM_IVRMCR = 0x2F0F01B0ull;
+
+static const uint64_t P9N2_C_15_PPM_IVRMCR_CLEAR = 0x2F0F01B1ull;
+
+static const uint64_t P9N2_C_15_PPM_IVRMCR_OR = 0x2F0F01B2ull;
+
+static const uint64_t P9N2_C_16_PPM_IVRMCR = 0x300F01B0ull;
+
+static const uint64_t P9N2_C_16_PPM_IVRMCR_CLEAR = 0x300F01B1ull;
+
+static const uint64_t P9N2_C_16_PPM_IVRMCR_OR = 0x300F01B2ull;
+
+static const uint64_t P9N2_C_17_PPM_IVRMCR = 0x310F01B0ull;
+
+static const uint64_t P9N2_C_17_PPM_IVRMCR_CLEAR = 0x310F01B1ull;
+
+static const uint64_t P9N2_C_17_PPM_IVRMCR_OR = 0x310F01B2ull;
+
+static const uint64_t P9N2_C_18_PPM_IVRMCR = 0x320F01B0ull;
+
+static const uint64_t P9N2_C_18_PPM_IVRMCR_CLEAR = 0x320F01B1ull;
+
+static const uint64_t P9N2_C_18_PPM_IVRMCR_OR = 0x320F01B2ull;
+
+static const uint64_t P9N2_C_19_PPM_IVRMCR = 0x330F01B0ull;
+
+static const uint64_t P9N2_C_19_PPM_IVRMCR_CLEAR = 0x330F01B1ull;
+
+static const uint64_t P9N2_C_19_PPM_IVRMCR_OR = 0x330F01B2ull;
+
+static const uint64_t P9N2_C_20_PPM_IVRMCR = 0x340F01B0ull;
+
+static const uint64_t P9N2_C_20_PPM_IVRMCR_CLEAR = 0x340F01B1ull;
+
+static const uint64_t P9N2_C_20_PPM_IVRMCR_OR = 0x340F01B2ull;
+
+static const uint64_t P9N2_C_21_PPM_IVRMCR = 0x350F01B0ull;
+
+static const uint64_t P9N2_C_21_PPM_IVRMCR_CLEAR = 0x350F01B1ull;
+
+static const uint64_t P9N2_C_21_PPM_IVRMCR_OR = 0x350F01B2ull;
+
+static const uint64_t P9N2_C_22_PPM_IVRMCR = 0x360F01B0ull;
+
+static const uint64_t P9N2_C_22_PPM_IVRMCR_CLEAR = 0x360F01B1ull;
+
+static const uint64_t P9N2_C_22_PPM_IVRMCR_OR = 0x360F01B2ull;
+
+static const uint64_t P9N2_C_23_PPM_IVRMCR = 0x370F01B0ull;
+
+static const uint64_t P9N2_C_23_PPM_IVRMCR_CLEAR = 0x370F01B1ull;
+
+static const uint64_t P9N2_C_23_PPM_IVRMCR_OR = 0x370F01B2ull;
+
+static const uint64_t P9N2_EQ_PPM_IVRMCR = 0x100F01B0ull;
+
+static const uint64_t P9N2_EQ_PPM_IVRMCR_CLEAR = 0x100F01B1ull;
+
+static const uint64_t P9N2_EQ_PPM_IVRMCR_OR = 0x100F01B2ull;
+
+static const uint64_t P9N2_EQ_0_PPM_IVRMCR = 0x100F01B0ull;
+
+static const uint64_t P9N2_EQ_0_PPM_IVRMCR_CLEAR = 0x100F01B1ull;
+
+static const uint64_t P9N2_EQ_0_PPM_IVRMCR_OR = 0x100F01B2ull;
+
+static const uint64_t P9N2_EQ_1_PPM_IVRMCR = 0x110F01B0ull;
+
+static const uint64_t P9N2_EQ_1_PPM_IVRMCR_CLEAR = 0x110F01B1ull;
+
+static const uint64_t P9N2_EQ_1_PPM_IVRMCR_OR = 0x110F01B2ull;
+
+static const uint64_t P9N2_EQ_2_PPM_IVRMCR = 0x120F01B0ull;
+
+static const uint64_t P9N2_EQ_2_PPM_IVRMCR_CLEAR = 0x120F01B1ull;
+
+static const uint64_t P9N2_EQ_2_PPM_IVRMCR_OR = 0x120F01B2ull;
+
+static const uint64_t P9N2_EQ_3_PPM_IVRMCR = 0x130F01B0ull;
+
+static const uint64_t P9N2_EQ_3_PPM_IVRMCR_CLEAR = 0x130F01B1ull;
+
+static const uint64_t P9N2_EQ_3_PPM_IVRMCR_OR = 0x130F01B2ull;
+
+static const uint64_t P9N2_EQ_4_PPM_IVRMCR = 0x140F01B0ull;
+
+static const uint64_t P9N2_EQ_4_PPM_IVRMCR_CLEAR = 0x140F01B1ull;
+
+static const uint64_t P9N2_EQ_4_PPM_IVRMCR_OR = 0x140F01B2ull;
+
+static const uint64_t P9N2_EQ_5_PPM_IVRMCR = 0x150F01B0ull;
+
+static const uint64_t P9N2_EQ_5_PPM_IVRMCR_CLEAR = 0x150F01B1ull;
+
+static const uint64_t P9N2_EQ_5_PPM_IVRMCR_OR = 0x150F01B2ull;
+
+static const uint64_t P9N2_EX_PPM_IVRMCR = 0x200F01B0ull;
+//DUPS: 210F01B0,
+static const uint64_t P9N2_EX_PPM_IVRMCR_CLEAR = 0x200F01B1ull;
+//DUPS: 210F01B1,
+static const uint64_t P9N2_EX_PPM_IVRMCR_OR = 0x200F01B2ull;
+//DUPS: 210F01B2,
+static const uint64_t P9N2_EX_0_PPM_IVRMCR = 0x200F01B0ull;
+//DUPS: 210F01B0,
+static const uint64_t P9N2_EX_0_PPM_IVRMCR_CLEAR = 0x200F01B1ull;
+//DUPS: 210F01B1,
+static const uint64_t P9N2_EX_0_PPM_IVRMCR_OR = 0x200F01B2ull;
+//DUPS: 210F01B2,
+static const uint64_t P9N2_EX_1_PPM_IVRMCR = 0x220F01B0ull;
+//DUPS: 220F01B0,
+static const uint64_t P9N2_EX_1_PPM_IVRMCR_CLEAR = 0x220F01B1ull;
+//DUPS: 220F01B1,
+static const uint64_t P9N2_EX_1_PPM_IVRMCR_OR = 0x220F01B2ull;
+//DUPS: 220F01B2,
+static const uint64_t P9N2_EX_2_PPM_IVRMCR = 0x240F01B0ull;
+//DUPS: 250F01B0,
+static const uint64_t P9N2_EX_2_PPM_IVRMCR_CLEAR = 0x240F01B1ull;
+//DUPS: 250F01B1,
+static const uint64_t P9N2_EX_2_PPM_IVRMCR_OR = 0x240F01B2ull;
+//DUPS: 250F01B2,
+static const uint64_t P9N2_EX_3_PPM_IVRMCR = 0x260F01B0ull;
+//DUPS: 270F01B0,
+static const uint64_t P9N2_EX_3_PPM_IVRMCR_CLEAR = 0x260F01B1ull;
+//DUPS: 270F01B1,
+static const uint64_t P9N2_EX_3_PPM_IVRMCR_OR = 0x260F01B2ull;
+//DUPS: 270F01B2,
+static const uint64_t P9N2_EX_4_PPM_IVRMCR = 0x280F01B0ull;
+//DUPS: 290F01B0,
+static const uint64_t P9N2_EX_4_PPM_IVRMCR_CLEAR = 0x280F01B1ull;
+//DUPS: 290F01B1,
+static const uint64_t P9N2_EX_4_PPM_IVRMCR_OR = 0x280F01B2ull;
+//DUPS: 290F01B2,
+static const uint64_t P9N2_EX_5_PPM_IVRMCR = 0x2A0F01B0ull;
+//DUPS: 2B0F01B0,
+static const uint64_t P9N2_EX_5_PPM_IVRMCR_CLEAR = 0x2A0F01B1ull;
+//DUPS: 2B0F01B1,
+static const uint64_t P9N2_EX_5_PPM_IVRMCR_OR = 0x2A0F01B2ull;
+//DUPS: 2B0F01B2,
+static const uint64_t P9N2_EX_6_PPM_IVRMCR = 0x2C0F01B0ull;
+//DUPS: 2D0F01B0,
+static const uint64_t P9N2_EX_6_PPM_IVRMCR_CLEAR = 0x2C0F01B1ull;
+//DUPS: 2D0F01B1,
+static const uint64_t P9N2_EX_6_PPM_IVRMCR_OR = 0x2C0F01B2ull;
+//DUPS: 2D0F01B2,
+static const uint64_t P9N2_EX_7_PPM_IVRMCR = 0x2E0F01B0ull;
+//DUPS: 2F0F01B0,
+static const uint64_t P9N2_EX_7_PPM_IVRMCR_CLEAR = 0x2E0F01B1ull;
+//DUPS: 2F0F01B1,
+static const uint64_t P9N2_EX_7_PPM_IVRMCR_OR = 0x2E0F01B2ull;
+//DUPS: 2F0F01B2,
+static const uint64_t P9N2_EX_8_PPM_IVRMCR = 0x300F01B0ull;
+//DUPS: 310F01B0,
+static const uint64_t P9N2_EX_8_PPM_IVRMCR_CLEAR = 0x300F01B1ull;
+//DUPS: 310F01B1,
+static const uint64_t P9N2_EX_8_PPM_IVRMCR_OR = 0x300F01B2ull;
+//DUPS: 310F01B2,
+static const uint64_t P9N2_EX_9_PPM_IVRMCR = 0x320F01B0ull;
+//DUPS: 330F01B0,
+static const uint64_t P9N2_EX_9_PPM_IVRMCR_CLEAR = 0x320F01B1ull;
+//DUPS: 330F01B1,
+static const uint64_t P9N2_EX_9_PPM_IVRMCR_OR = 0x320F01B2ull;
+//DUPS: 330F01B2,
+static const uint64_t P9N2_EX_10_PPM_IVRMCR = 0x340F01B0ull;
+//DUPS: 350F01B0,
+static const uint64_t P9N2_EX_10_PPM_IVRMCR_CLEAR = 0x340F01B1ull;
+//DUPS: 350F01B1,
+static const uint64_t P9N2_EX_10_PPM_IVRMCR_OR = 0x340F01B2ull;
+//DUPS: 350F01B2,
+static const uint64_t P9N2_EX_11_PPM_IVRMCR = 0x360F01B0ull;
+//DUPS: 370F01B0,
+static const uint64_t P9N2_EX_11_PPM_IVRMCR_CLEAR = 0x360F01B1ull;
+//DUPS: 370F01B1,
+static const uint64_t P9N2_EX_11_PPM_IVRMCR_OR = 0x360F01B2ull;
+//DUPS: 370F01B2,
+
+static const uint64_t P9N2_C_PPM_IVRMDVR = 0x200F01B4ull;
+
+static const uint64_t P9N2_C_0_PPM_IVRMDVR = 0x200F01B4ull;
+
+static const uint64_t P9N2_C_1_PPM_IVRMDVR = 0x210F01B4ull;
+
+static const uint64_t P9N2_C_2_PPM_IVRMDVR = 0x220F01B4ull;
+
+static const uint64_t P9N2_C_3_PPM_IVRMDVR = 0x230F01B4ull;
+
+static const uint64_t P9N2_C_4_PPM_IVRMDVR = 0x240F01B4ull;
+
+static const uint64_t P9N2_C_5_PPM_IVRMDVR = 0x250F01B4ull;
+
+static const uint64_t P9N2_C_6_PPM_IVRMDVR = 0x260F01B4ull;
+
+static const uint64_t P9N2_C_7_PPM_IVRMDVR = 0x270F01B4ull;
+
+static const uint64_t P9N2_C_8_PPM_IVRMDVR = 0x280F01B4ull;
+
+static const uint64_t P9N2_C_9_PPM_IVRMDVR = 0x290F01B4ull;
+
+static const uint64_t P9N2_C_10_PPM_IVRMDVR = 0x2A0F01B4ull;
+
+static const uint64_t P9N2_C_11_PPM_IVRMDVR = 0x2B0F01B4ull;
+
+static const uint64_t P9N2_C_12_PPM_IVRMDVR = 0x2C0F01B4ull;
+
+static const uint64_t P9N2_C_13_PPM_IVRMDVR = 0x2D0F01B4ull;
+
+static const uint64_t P9N2_C_14_PPM_IVRMDVR = 0x2E0F01B4ull;
+
+static const uint64_t P9N2_C_15_PPM_IVRMDVR = 0x2F0F01B4ull;
+
+static const uint64_t P9N2_C_16_PPM_IVRMDVR = 0x300F01B4ull;
+
+static const uint64_t P9N2_C_17_PPM_IVRMDVR = 0x310F01B4ull;
+
+static const uint64_t P9N2_C_18_PPM_IVRMDVR = 0x320F01B4ull;
+
+static const uint64_t P9N2_C_19_PPM_IVRMDVR = 0x330F01B4ull;
+
+static const uint64_t P9N2_C_20_PPM_IVRMDVR = 0x340F01B4ull;
+
+static const uint64_t P9N2_C_21_PPM_IVRMDVR = 0x350F01B4ull;
+
+static const uint64_t P9N2_C_22_PPM_IVRMDVR = 0x360F01B4ull;
+
+static const uint64_t P9N2_C_23_PPM_IVRMDVR = 0x370F01B4ull;
+
+static const uint64_t P9N2_EQ_PPM_IVRMDVR = 0x100F01B4ull;
+
+static const uint64_t P9N2_EQ_0_PPM_IVRMDVR = 0x100F01B4ull;
+
+static const uint64_t P9N2_EQ_1_PPM_IVRMDVR = 0x110F01B4ull;
+
+static const uint64_t P9N2_EQ_2_PPM_IVRMDVR = 0x120F01B4ull;
+
+static const uint64_t P9N2_EQ_3_PPM_IVRMDVR = 0x130F01B4ull;
+
+static const uint64_t P9N2_EQ_4_PPM_IVRMDVR = 0x140F01B4ull;
+
+static const uint64_t P9N2_EQ_5_PPM_IVRMDVR = 0x150F01B4ull;
+
+static const uint64_t P9N2_EX_PPM_IVRMDVR = 0x200F01B4ull;
+//DUPS: 210F01B4,
+static const uint64_t P9N2_EX_0_PPM_IVRMDVR = 0x200F01B4ull;
+//DUPS: 210F01B4,
+static const uint64_t P9N2_EX_1_PPM_IVRMDVR = 0x220F01B4ull;
+//DUPS: 220F01B4,
+static const uint64_t P9N2_EX_2_PPM_IVRMDVR = 0x240F01B4ull;
+//DUPS: 250F01B4,
+static const uint64_t P9N2_EX_3_PPM_IVRMDVR = 0x260F01B4ull;
+//DUPS: 270F01B4,
+static const uint64_t P9N2_EX_4_PPM_IVRMDVR = 0x280F01B4ull;
+//DUPS: 290F01B4,
+static const uint64_t P9N2_EX_5_PPM_IVRMDVR = 0x2A0F01B4ull;
+//DUPS: 2B0F01B4,
+static const uint64_t P9N2_EX_6_PPM_IVRMDVR = 0x2C0F01B4ull;
+//DUPS: 2D0F01B4,
+static const uint64_t P9N2_EX_7_PPM_IVRMDVR = 0x2E0F01B4ull;
+//DUPS: 2F0F01B4,
+static const uint64_t P9N2_EX_8_PPM_IVRMDVR = 0x300F01B4ull;
+//DUPS: 310F01B4,
+static const uint64_t P9N2_EX_9_PPM_IVRMDVR = 0x320F01B4ull;
+//DUPS: 330F01B4,
+static const uint64_t P9N2_EX_10_PPM_IVRMDVR = 0x340F01B4ull;
+//DUPS: 350F01B4,
+static const uint64_t P9N2_EX_11_PPM_IVRMDVR = 0x360F01B4ull;
+//DUPS: 370F01B4,
+
+static const uint64_t P9N2_C_PPM_IVRMST = 0x200F01B3ull;
+
+static const uint64_t P9N2_C_0_PPM_IVRMST = 0x200F01B3ull;
+
+static const uint64_t P9N2_C_1_PPM_IVRMST = 0x210F01B3ull;
+
+static const uint64_t P9N2_C_2_PPM_IVRMST = 0x220F01B3ull;
+
+static const uint64_t P9N2_C_3_PPM_IVRMST = 0x230F01B3ull;
+
+static const uint64_t P9N2_C_4_PPM_IVRMST = 0x240F01B3ull;
+
+static const uint64_t P9N2_C_5_PPM_IVRMST = 0x250F01B3ull;
+
+static const uint64_t P9N2_C_6_PPM_IVRMST = 0x260F01B3ull;
+
+static const uint64_t P9N2_C_7_PPM_IVRMST = 0x270F01B3ull;
+
+static const uint64_t P9N2_C_8_PPM_IVRMST = 0x280F01B3ull;
+
+static const uint64_t P9N2_C_9_PPM_IVRMST = 0x290F01B3ull;
+
+static const uint64_t P9N2_C_10_PPM_IVRMST = 0x2A0F01B3ull;
+
+static const uint64_t P9N2_C_11_PPM_IVRMST = 0x2B0F01B3ull;
+
+static const uint64_t P9N2_C_12_PPM_IVRMST = 0x2C0F01B3ull;
+
+static const uint64_t P9N2_C_13_PPM_IVRMST = 0x2D0F01B3ull;
+
+static const uint64_t P9N2_C_14_PPM_IVRMST = 0x2E0F01B3ull;
+
+static const uint64_t P9N2_C_15_PPM_IVRMST = 0x2F0F01B3ull;
+
+static const uint64_t P9N2_C_16_PPM_IVRMST = 0x300F01B3ull;
+
+static const uint64_t P9N2_C_17_PPM_IVRMST = 0x310F01B3ull;
+
+static const uint64_t P9N2_C_18_PPM_IVRMST = 0x320F01B3ull;
+
+static const uint64_t P9N2_C_19_PPM_IVRMST = 0x330F01B3ull;
+
+static const uint64_t P9N2_C_20_PPM_IVRMST = 0x340F01B3ull;
+
+static const uint64_t P9N2_C_21_PPM_IVRMST = 0x350F01B3ull;
+
+static const uint64_t P9N2_C_22_PPM_IVRMST = 0x360F01B3ull;
+
+static const uint64_t P9N2_C_23_PPM_IVRMST = 0x370F01B3ull;
+
+static const uint64_t P9N2_EQ_PPM_IVRMST = 0x100F01B3ull;
+
+static const uint64_t P9N2_EQ_0_PPM_IVRMST = 0x100F01B3ull;
+
+static const uint64_t P9N2_EQ_1_PPM_IVRMST = 0x110F01B3ull;
+
+static const uint64_t P9N2_EQ_2_PPM_IVRMST = 0x120F01B3ull;
+
+static const uint64_t P9N2_EQ_3_PPM_IVRMST = 0x130F01B3ull;
+
+static const uint64_t P9N2_EQ_4_PPM_IVRMST = 0x140F01B3ull;
+
+static const uint64_t P9N2_EQ_5_PPM_IVRMST = 0x150F01B3ull;
+
+static const uint64_t P9N2_EX_PPM_IVRMST = 0x200F01B3ull;
+//DUPS: 210F01B3,
+static const uint64_t P9N2_EX_0_PPM_IVRMST = 0x200F01B3ull;
+//DUPS: 210F01B3,
+static const uint64_t P9N2_EX_1_PPM_IVRMST = 0x220F01B3ull;
+//DUPS: 220F01B3,
+static const uint64_t P9N2_EX_2_PPM_IVRMST = 0x240F01B3ull;
+//DUPS: 250F01B3,
+static const uint64_t P9N2_EX_3_PPM_IVRMST = 0x260F01B3ull;
+//DUPS: 270F01B3,
+static const uint64_t P9N2_EX_4_PPM_IVRMST = 0x280F01B3ull;
+//DUPS: 290F01B3,
+static const uint64_t P9N2_EX_5_PPM_IVRMST = 0x2A0F01B3ull;
+//DUPS: 2B0F01B3,
+static const uint64_t P9N2_EX_6_PPM_IVRMST = 0x2C0F01B3ull;
+//DUPS: 2D0F01B3,
+static const uint64_t P9N2_EX_7_PPM_IVRMST = 0x2E0F01B3ull;
+//DUPS: 2F0F01B3,
+static const uint64_t P9N2_EX_8_PPM_IVRMST = 0x300F01B3ull;
+//DUPS: 310F01B3,
+static const uint64_t P9N2_EX_9_PPM_IVRMST = 0x320F01B3ull;
+//DUPS: 330F01B3,
+static const uint64_t P9N2_EX_10_PPM_IVRMST = 0x340F01B3ull;
+//DUPS: 350F01B3,
+static const uint64_t P9N2_EX_11_PPM_IVRMST = 0x360F01B3ull;
+//DUPS: 370F01B3,
+
+static const uint64_t P9N2_C_PPM_PFCS_SCOM = 0x200F0118ull;
+
+static const uint64_t P9N2_C_PPM_PFCS_SCOM1 = 0x200F0119ull;
+
+static const uint64_t P9N2_C_PPM_PFCS_SCOM2 = 0x200F011Aull;
+
+static const uint64_t P9N2_C_0_PPM_PFCS_SCOM = 0x200F0118ull;
+
+static const uint64_t P9N2_C_0_PPM_PFCS_SCOM1 = 0x200F0119ull;
+
+static const uint64_t P9N2_C_0_PPM_PFCS_SCOM2 = 0x200F011Aull;
+
+static const uint64_t P9N2_C_1_PPM_PFCS_SCOM = 0x210F0118ull;
+
+static const uint64_t P9N2_C_1_PPM_PFCS_SCOM1 = 0x210F0119ull;
+
+static const uint64_t P9N2_C_1_PPM_PFCS_SCOM2 = 0x210F011Aull;
+
+static const uint64_t P9N2_C_2_PPM_PFCS_SCOM = 0x220F0118ull;
+
+static const uint64_t P9N2_C_2_PPM_PFCS_SCOM1 = 0x220F0119ull;
+
+static const uint64_t P9N2_C_2_PPM_PFCS_SCOM2 = 0x220F011Aull;
+
+static const uint64_t P9N2_C_3_PPM_PFCS_SCOM = 0x230F0118ull;
+
+static const uint64_t P9N2_C_3_PPM_PFCS_SCOM1 = 0x230F0119ull;
+
+static const uint64_t P9N2_C_3_PPM_PFCS_SCOM2 = 0x230F011Aull;
+
+static const uint64_t P9N2_C_4_PPM_PFCS_SCOM = 0x240F0118ull;
+
+static const uint64_t P9N2_C_4_PPM_PFCS_SCOM1 = 0x240F0119ull;
+
+static const uint64_t P9N2_C_4_PPM_PFCS_SCOM2 = 0x240F011Aull;
+
+static const uint64_t P9N2_C_5_PPM_PFCS_SCOM = 0x250F0118ull;
+
+static const uint64_t P9N2_C_5_PPM_PFCS_SCOM1 = 0x250F0119ull;
+
+static const uint64_t P9N2_C_5_PPM_PFCS_SCOM2 = 0x250F011Aull;
+
+static const uint64_t P9N2_C_6_PPM_PFCS_SCOM = 0x260F0118ull;
+
+static const uint64_t P9N2_C_6_PPM_PFCS_SCOM1 = 0x260F0119ull;
+
+static const uint64_t P9N2_C_6_PPM_PFCS_SCOM2 = 0x260F011Aull;
+
+static const uint64_t P9N2_C_7_PPM_PFCS_SCOM = 0x270F0118ull;
+
+static const uint64_t P9N2_C_7_PPM_PFCS_SCOM1 = 0x270F0119ull;
+
+static const uint64_t P9N2_C_7_PPM_PFCS_SCOM2 = 0x270F011Aull;
+
+static const uint64_t P9N2_C_8_PPM_PFCS_SCOM = 0x280F0118ull;
+
+static const uint64_t P9N2_C_8_PPM_PFCS_SCOM1 = 0x280F0119ull;
+
+static const uint64_t P9N2_C_8_PPM_PFCS_SCOM2 = 0x280F011Aull;
+
+static const uint64_t P9N2_C_9_PPM_PFCS_SCOM = 0x290F0118ull;
+
+static const uint64_t P9N2_C_9_PPM_PFCS_SCOM1 = 0x290F0119ull;
+
+static const uint64_t P9N2_C_9_PPM_PFCS_SCOM2 = 0x290F011Aull;
+
+static const uint64_t P9N2_C_10_PPM_PFCS_SCOM = 0x2A0F0118ull;
+
+static const uint64_t P9N2_C_10_PPM_PFCS_SCOM1 = 0x2A0F0119ull;
+
+static const uint64_t P9N2_C_10_PPM_PFCS_SCOM2 = 0x2A0F011Aull;
+
+static const uint64_t P9N2_C_11_PPM_PFCS_SCOM = 0x2B0F0118ull;
+
+static const uint64_t P9N2_C_11_PPM_PFCS_SCOM1 = 0x2B0F0119ull;
+
+static const uint64_t P9N2_C_11_PPM_PFCS_SCOM2 = 0x2B0F011Aull;
+
+static const uint64_t P9N2_C_12_PPM_PFCS_SCOM = 0x2C0F0118ull;
+
+static const uint64_t P9N2_C_12_PPM_PFCS_SCOM1 = 0x2C0F0119ull;
+
+static const uint64_t P9N2_C_12_PPM_PFCS_SCOM2 = 0x2C0F011Aull;
+
+static const uint64_t P9N2_C_13_PPM_PFCS_SCOM = 0x2D0F0118ull;
+
+static const uint64_t P9N2_C_13_PPM_PFCS_SCOM1 = 0x2D0F0119ull;
+
+static const uint64_t P9N2_C_13_PPM_PFCS_SCOM2 = 0x2D0F011Aull;
+
+static const uint64_t P9N2_C_14_PPM_PFCS_SCOM = 0x2E0F0118ull;
+
+static const uint64_t P9N2_C_14_PPM_PFCS_SCOM1 = 0x2E0F0119ull;
+
+static const uint64_t P9N2_C_14_PPM_PFCS_SCOM2 = 0x2E0F011Aull;
+
+static const uint64_t P9N2_C_15_PPM_PFCS_SCOM = 0x2F0F0118ull;
+
+static const uint64_t P9N2_C_15_PPM_PFCS_SCOM1 = 0x2F0F0119ull;
+
+static const uint64_t P9N2_C_15_PPM_PFCS_SCOM2 = 0x2F0F011Aull;
+
+static const uint64_t P9N2_C_16_PPM_PFCS_SCOM = 0x300F0118ull;
+
+static const uint64_t P9N2_C_16_PPM_PFCS_SCOM1 = 0x300F0119ull;
+
+static const uint64_t P9N2_C_16_PPM_PFCS_SCOM2 = 0x300F011Aull;
+
+static const uint64_t P9N2_C_17_PPM_PFCS_SCOM = 0x310F0118ull;
+
+static const uint64_t P9N2_C_17_PPM_PFCS_SCOM1 = 0x310F0119ull;
+
+static const uint64_t P9N2_C_17_PPM_PFCS_SCOM2 = 0x310F011Aull;
+
+static const uint64_t P9N2_C_18_PPM_PFCS_SCOM = 0x320F0118ull;
+
+static const uint64_t P9N2_C_18_PPM_PFCS_SCOM1 = 0x320F0119ull;
+
+static const uint64_t P9N2_C_18_PPM_PFCS_SCOM2 = 0x320F011Aull;
+
+static const uint64_t P9N2_C_19_PPM_PFCS_SCOM = 0x330F0118ull;
+
+static const uint64_t P9N2_C_19_PPM_PFCS_SCOM1 = 0x330F0119ull;
+
+static const uint64_t P9N2_C_19_PPM_PFCS_SCOM2 = 0x330F011Aull;
+
+static const uint64_t P9N2_C_20_PPM_PFCS_SCOM = 0x340F0118ull;
+
+static const uint64_t P9N2_C_20_PPM_PFCS_SCOM1 = 0x340F0119ull;
+
+static const uint64_t P9N2_C_20_PPM_PFCS_SCOM2 = 0x340F011Aull;
+
+static const uint64_t P9N2_C_21_PPM_PFCS_SCOM = 0x350F0118ull;
+
+static const uint64_t P9N2_C_21_PPM_PFCS_SCOM1 = 0x350F0119ull;
+
+static const uint64_t P9N2_C_21_PPM_PFCS_SCOM2 = 0x350F011Aull;
+
+static const uint64_t P9N2_C_22_PPM_PFCS_SCOM = 0x360F0118ull;
+
+static const uint64_t P9N2_C_22_PPM_PFCS_SCOM1 = 0x360F0119ull;
+
+static const uint64_t P9N2_C_22_PPM_PFCS_SCOM2 = 0x360F011Aull;
+
+static const uint64_t P9N2_C_23_PPM_PFCS_SCOM = 0x370F0118ull;
+
+static const uint64_t P9N2_C_23_PPM_PFCS_SCOM1 = 0x370F0119ull;
+
+static const uint64_t P9N2_C_23_PPM_PFCS_SCOM2 = 0x370F011Aull;
+
+static const uint64_t P9N2_EQ_PPM_PFCS_SCOM = 0x100F0118ull;
+
+static const uint64_t P9N2_EQ_PPM_PFCS_SCOM1 = 0x100F0119ull;
+
+static const uint64_t P9N2_EQ_PPM_PFCS_SCOM2 = 0x100F011Aull;
+
+static const uint64_t P9N2_EQ_0_PPM_PFCS_SCOM = 0x100F0118ull;
+
+static const uint64_t P9N2_EQ_0_PPM_PFCS_SCOM1 = 0x100F0119ull;
+
+static const uint64_t P9N2_EQ_0_PPM_PFCS_SCOM2 = 0x100F011Aull;
+
+static const uint64_t P9N2_EQ_1_PPM_PFCS_SCOM = 0x110F0118ull;
+
+static const uint64_t P9N2_EQ_1_PPM_PFCS_SCOM1 = 0x110F0119ull;
+
+static const uint64_t P9N2_EQ_1_PPM_PFCS_SCOM2 = 0x110F011Aull;
+
+static const uint64_t P9N2_EQ_2_PPM_PFCS_SCOM = 0x120F0118ull;
+
+static const uint64_t P9N2_EQ_2_PPM_PFCS_SCOM1 = 0x120F0119ull;
+
+static const uint64_t P9N2_EQ_2_PPM_PFCS_SCOM2 = 0x120F011Aull;
+
+static const uint64_t P9N2_EQ_3_PPM_PFCS_SCOM = 0x130F0118ull;
+
+static const uint64_t P9N2_EQ_3_PPM_PFCS_SCOM1 = 0x130F0119ull;
+
+static const uint64_t P9N2_EQ_3_PPM_PFCS_SCOM2 = 0x130F011Aull;
+
+static const uint64_t P9N2_EQ_4_PPM_PFCS_SCOM = 0x140F0118ull;
+
+static const uint64_t P9N2_EQ_4_PPM_PFCS_SCOM1 = 0x140F0119ull;
+
+static const uint64_t P9N2_EQ_4_PPM_PFCS_SCOM2 = 0x140F011Aull;
+
+static const uint64_t P9N2_EQ_5_PPM_PFCS_SCOM = 0x150F0118ull;
+
+static const uint64_t P9N2_EQ_5_PPM_PFCS_SCOM1 = 0x150F0119ull;
+
+static const uint64_t P9N2_EQ_5_PPM_PFCS_SCOM2 = 0x150F011Aull;
+
+static const uint64_t P9N2_EX_PPM_PFCS_SCOM = 0x200F0118ull;
+//DUPS: 210F0118,
+static const uint64_t P9N2_EX_PPM_PFCS_SCOM1 = 0x200F0119ull;
+//DUPS: 210F0119,
+static const uint64_t P9N2_EX_PPM_PFCS_SCOM2 = 0x200F011Aull;
+//DUPS: 210F011A,
+static const uint64_t P9N2_EX_0_PPM_PFCS_SCOM = 0x200F0118ull;
+//DUPS: 210F0118,
+static const uint64_t P9N2_EX_0_PPM_PFCS_SCOM1 = 0x200F0119ull;
+//DUPS: 210F0119,
+static const uint64_t P9N2_EX_0_PPM_PFCS_SCOM2 = 0x200F011Aull;
+//DUPS: 210F011A,
+static const uint64_t P9N2_EX_1_PPM_PFCS_SCOM = 0x220F0118ull;
+//DUPS: 220F0118,
+static const uint64_t P9N2_EX_1_PPM_PFCS_SCOM1 = 0x220F0119ull;
+//DUPS: 220F0119,
+static const uint64_t P9N2_EX_1_PPM_PFCS_SCOM2 = 0x220F011Aull;
+//DUPS: 220F011A,
+static const uint64_t P9N2_EX_2_PPM_PFCS_SCOM = 0x240F0118ull;
+//DUPS: 250F0118,
+static const uint64_t P9N2_EX_2_PPM_PFCS_SCOM1 = 0x240F0119ull;
+//DUPS: 250F0119,
+static const uint64_t P9N2_EX_2_PPM_PFCS_SCOM2 = 0x240F011Aull;
+//DUPS: 250F011A,
+static const uint64_t P9N2_EX_3_PPM_PFCS_SCOM = 0x260F0118ull;
+//DUPS: 270F0118,
+static const uint64_t P9N2_EX_3_PPM_PFCS_SCOM1 = 0x260F0119ull;
+//DUPS: 270F0119,
+static const uint64_t P9N2_EX_3_PPM_PFCS_SCOM2 = 0x260F011Aull;
+//DUPS: 270F011A,
+static const uint64_t P9N2_EX_4_PPM_PFCS_SCOM = 0x280F0118ull;
+//DUPS: 290F0118,
+static const uint64_t P9N2_EX_4_PPM_PFCS_SCOM1 = 0x280F0119ull;
+//DUPS: 290F0119,
+static const uint64_t P9N2_EX_4_PPM_PFCS_SCOM2 = 0x280F011Aull;
+//DUPS: 290F011A,
+static const uint64_t P9N2_EX_5_PPM_PFCS_SCOM = 0x2A0F0118ull;
+//DUPS: 2B0F0118,
+static const uint64_t P9N2_EX_5_PPM_PFCS_SCOM1 = 0x2A0F0119ull;
+//DUPS: 2B0F0119,
+static const uint64_t P9N2_EX_5_PPM_PFCS_SCOM2 = 0x2A0F011Aull;
+//DUPS: 2B0F011A,
+static const uint64_t P9N2_EX_6_PPM_PFCS_SCOM = 0x2C0F0118ull;
+//DUPS: 2D0F0118,
+static const uint64_t P9N2_EX_6_PPM_PFCS_SCOM1 = 0x2C0F0119ull;
+//DUPS: 2D0F0119,
+static const uint64_t P9N2_EX_6_PPM_PFCS_SCOM2 = 0x2C0F011Aull;
+//DUPS: 2D0F011A,
+static const uint64_t P9N2_EX_7_PPM_PFCS_SCOM = 0x2E0F0118ull;
+//DUPS: 2F0F0118,
+static const uint64_t P9N2_EX_7_PPM_PFCS_SCOM1 = 0x2E0F0119ull;
+//DUPS: 2F0F0119,
+static const uint64_t P9N2_EX_7_PPM_PFCS_SCOM2 = 0x2E0F011Aull;
+//DUPS: 2F0F011A,
+static const uint64_t P9N2_EX_8_PPM_PFCS_SCOM = 0x300F0118ull;
+//DUPS: 310F0118,
+static const uint64_t P9N2_EX_8_PPM_PFCS_SCOM1 = 0x300F0119ull;
+//DUPS: 310F0119,
+static const uint64_t P9N2_EX_8_PPM_PFCS_SCOM2 = 0x300F011Aull;
+//DUPS: 310F011A,
+static const uint64_t P9N2_EX_9_PPM_PFCS_SCOM = 0x320F0118ull;
+//DUPS: 330F0118,
+static const uint64_t P9N2_EX_9_PPM_PFCS_SCOM1 = 0x320F0119ull;
+//DUPS: 330F0119,
+static const uint64_t P9N2_EX_9_PPM_PFCS_SCOM2 = 0x320F011Aull;
+//DUPS: 330F011A,
+static const uint64_t P9N2_EX_10_PPM_PFCS_SCOM = 0x340F0118ull;
+//DUPS: 350F0118,
+static const uint64_t P9N2_EX_10_PPM_PFCS_SCOM1 = 0x340F0119ull;
+//DUPS: 350F0119,
+static const uint64_t P9N2_EX_10_PPM_PFCS_SCOM2 = 0x340F011Aull;
+//DUPS: 350F011A,
+static const uint64_t P9N2_EX_11_PPM_PFCS_SCOM = 0x360F0118ull;
+//DUPS: 370F0118,
+static const uint64_t P9N2_EX_11_PPM_PFCS_SCOM1 = 0x360F0119ull;
+//DUPS: 370F0119,
+static const uint64_t P9N2_EX_11_PPM_PFCS_SCOM2 = 0x360F011Aull;
+//DUPS: 370F011A,
+
+static const uint64_t P9N2_C_PPM_PFDLY = 0x200F011Bull;
+
+static const uint64_t P9N2_C_0_PPM_PFDLY = 0x200F011Bull;
+
+static const uint64_t P9N2_C_1_PPM_PFDLY = 0x210F011Bull;
+
+static const uint64_t P9N2_C_2_PPM_PFDLY = 0x220F011Bull;
+
+static const uint64_t P9N2_C_3_PPM_PFDLY = 0x230F011Bull;
+
+static const uint64_t P9N2_C_4_PPM_PFDLY = 0x240F011Bull;
+
+static const uint64_t P9N2_C_5_PPM_PFDLY = 0x250F011Bull;
+
+static const uint64_t P9N2_C_6_PPM_PFDLY = 0x260F011Bull;
+
+static const uint64_t P9N2_C_7_PPM_PFDLY = 0x270F011Bull;
+
+static const uint64_t P9N2_C_8_PPM_PFDLY = 0x280F011Bull;
+
+static const uint64_t P9N2_C_9_PPM_PFDLY = 0x290F011Bull;
+
+static const uint64_t P9N2_C_10_PPM_PFDLY = 0x2A0F011Bull;
+
+static const uint64_t P9N2_C_11_PPM_PFDLY = 0x2B0F011Bull;
+
+static const uint64_t P9N2_C_12_PPM_PFDLY = 0x2C0F011Bull;
+
+static const uint64_t P9N2_C_13_PPM_PFDLY = 0x2D0F011Bull;
+
+static const uint64_t P9N2_C_14_PPM_PFDLY = 0x2E0F011Bull;
+
+static const uint64_t P9N2_C_15_PPM_PFDLY = 0x2F0F011Bull;
+
+static const uint64_t P9N2_C_16_PPM_PFDLY = 0x300F011Bull;
+
+static const uint64_t P9N2_C_17_PPM_PFDLY = 0x310F011Bull;
+
+static const uint64_t P9N2_C_18_PPM_PFDLY = 0x320F011Bull;
+
+static const uint64_t P9N2_C_19_PPM_PFDLY = 0x330F011Bull;
+
+static const uint64_t P9N2_C_20_PPM_PFDLY = 0x340F011Bull;
+
+static const uint64_t P9N2_C_21_PPM_PFDLY = 0x350F011Bull;
+
+static const uint64_t P9N2_C_22_PPM_PFDLY = 0x360F011Bull;
+
+static const uint64_t P9N2_C_23_PPM_PFDLY = 0x370F011Bull;
+
+static const uint64_t P9N2_EQ_PPM_PFDLY = 0x100F011Bull;
+
+static const uint64_t P9N2_EQ_0_PPM_PFDLY = 0x100F011Bull;
+
+static const uint64_t P9N2_EQ_1_PPM_PFDLY = 0x110F011Bull;
+
+static const uint64_t P9N2_EQ_2_PPM_PFDLY = 0x120F011Bull;
+
+static const uint64_t P9N2_EQ_3_PPM_PFDLY = 0x130F011Bull;
+
+static const uint64_t P9N2_EQ_4_PPM_PFDLY = 0x140F011Bull;
+
+static const uint64_t P9N2_EQ_5_PPM_PFDLY = 0x150F011Bull;
+
+static const uint64_t P9N2_EX_PPM_PFDLY = 0x200F011Bull;
+//DUPS: 210F011B,
+static const uint64_t P9N2_EX_0_PPM_PFDLY = 0x200F011Bull;
+//DUPS: 210F011B,
+static const uint64_t P9N2_EX_1_PPM_PFDLY = 0x220F011Bull;
+//DUPS: 220F011B,
+static const uint64_t P9N2_EX_2_PPM_PFDLY = 0x240F011Bull;
+//DUPS: 250F011B,
+static const uint64_t P9N2_EX_3_PPM_PFDLY = 0x260F011Bull;
+//DUPS: 270F011B,
+static const uint64_t P9N2_EX_4_PPM_PFDLY = 0x280F011Bull;
+//DUPS: 290F011B,
+static const uint64_t P9N2_EX_5_PPM_PFDLY = 0x2A0F011Bull;
+//DUPS: 2B0F011B,
+static const uint64_t P9N2_EX_6_PPM_PFDLY = 0x2C0F011Bull;
+//DUPS: 2D0F011B,
+static const uint64_t P9N2_EX_7_PPM_PFDLY = 0x2E0F011Bull;
+//DUPS: 2F0F011B,
+static const uint64_t P9N2_EX_8_PPM_PFDLY = 0x300F011Bull;
+//DUPS: 310F011B,
+static const uint64_t P9N2_EX_9_PPM_PFDLY = 0x320F011Bull;
+//DUPS: 330F011B,
+static const uint64_t P9N2_EX_10_PPM_PFDLY = 0x340F011Bull;
+//DUPS: 350F011B,
+static const uint64_t P9N2_EX_11_PPM_PFDLY = 0x360F011Bull;
+//DUPS: 370F011B,
+
+static const uint64_t P9N2_C_PPM_PFOFF = 0x200F011Dull;
+
+static const uint64_t P9N2_C_0_PPM_PFOFF = 0x200F011Dull;
+
+static const uint64_t P9N2_C_1_PPM_PFOFF = 0x210F011Dull;
+
+static const uint64_t P9N2_C_2_PPM_PFOFF = 0x220F011Dull;
+
+static const uint64_t P9N2_C_3_PPM_PFOFF = 0x230F011Dull;
+
+static const uint64_t P9N2_C_4_PPM_PFOFF = 0x240F011Dull;
+
+static const uint64_t P9N2_C_5_PPM_PFOFF = 0x250F011Dull;
+
+static const uint64_t P9N2_C_6_PPM_PFOFF = 0x260F011Dull;
+
+static const uint64_t P9N2_C_7_PPM_PFOFF = 0x270F011Dull;
+
+static const uint64_t P9N2_C_8_PPM_PFOFF = 0x280F011Dull;
+
+static const uint64_t P9N2_C_9_PPM_PFOFF = 0x290F011Dull;
+
+static const uint64_t P9N2_C_10_PPM_PFOFF = 0x2A0F011Dull;
+
+static const uint64_t P9N2_C_11_PPM_PFOFF = 0x2B0F011Dull;
+
+static const uint64_t P9N2_C_12_PPM_PFOFF = 0x2C0F011Dull;
+
+static const uint64_t P9N2_C_13_PPM_PFOFF = 0x2D0F011Dull;
+
+static const uint64_t P9N2_C_14_PPM_PFOFF = 0x2E0F011Dull;
+
+static const uint64_t P9N2_C_15_PPM_PFOFF = 0x2F0F011Dull;
+
+static const uint64_t P9N2_C_16_PPM_PFOFF = 0x300F011Dull;
+
+static const uint64_t P9N2_C_17_PPM_PFOFF = 0x310F011Dull;
+
+static const uint64_t P9N2_C_18_PPM_PFOFF = 0x320F011Dull;
+
+static const uint64_t P9N2_C_19_PPM_PFOFF = 0x330F011Dull;
+
+static const uint64_t P9N2_C_20_PPM_PFOFF = 0x340F011Dull;
+
+static const uint64_t P9N2_C_21_PPM_PFOFF = 0x350F011Dull;
+
+static const uint64_t P9N2_C_22_PPM_PFOFF = 0x360F011Dull;
+
+static const uint64_t P9N2_C_23_PPM_PFOFF = 0x370F011Dull;
+
+static const uint64_t P9N2_EQ_PPM_PFOFF = 0x100F011Dull;
+
+static const uint64_t P9N2_EQ_0_PPM_PFOFF = 0x100F011Dull;
+
+static const uint64_t P9N2_EQ_1_PPM_PFOFF = 0x110F011Dull;
+
+static const uint64_t P9N2_EQ_2_PPM_PFOFF = 0x120F011Dull;
+
+static const uint64_t P9N2_EQ_3_PPM_PFOFF = 0x130F011Dull;
+
+static const uint64_t P9N2_EQ_4_PPM_PFOFF = 0x140F011Dull;
+
+static const uint64_t P9N2_EQ_5_PPM_PFOFF = 0x150F011Dull;
+
+static const uint64_t P9N2_EX_PPM_PFOFF = 0x200F011Dull;
+//DUPS: 210F011D,
+static const uint64_t P9N2_EX_0_PPM_PFOFF = 0x200F011Dull;
+//DUPS: 210F011D,
+static const uint64_t P9N2_EX_1_PPM_PFOFF = 0x220F011Dull;
+//DUPS: 220F011D,
+static const uint64_t P9N2_EX_2_PPM_PFOFF = 0x240F011Dull;
+//DUPS: 250F011D,
+static const uint64_t P9N2_EX_3_PPM_PFOFF = 0x260F011Dull;
+//DUPS: 270F011D,
+static const uint64_t P9N2_EX_4_PPM_PFOFF = 0x280F011Dull;
+//DUPS: 290F011D,
+static const uint64_t P9N2_EX_5_PPM_PFOFF = 0x2A0F011Dull;
+//DUPS: 2B0F011D,
+static const uint64_t P9N2_EX_6_PPM_PFOFF = 0x2C0F011Dull;
+//DUPS: 2D0F011D,
+static const uint64_t P9N2_EX_7_PPM_PFOFF = 0x2E0F011Dull;
+//DUPS: 2F0F011D,
+static const uint64_t P9N2_EX_8_PPM_PFOFF = 0x300F011Dull;
+//DUPS: 310F011D,
+static const uint64_t P9N2_EX_9_PPM_PFOFF = 0x320F011Dull;
+//DUPS: 330F011D,
+static const uint64_t P9N2_EX_10_PPM_PFOFF = 0x340F011Dull;
+//DUPS: 350F011D,
+static const uint64_t P9N2_EX_11_PPM_PFOFF = 0x360F011Dull;
+//DUPS: 370F011D,
+
+static const uint64_t P9N2_C_PPM_PFSNS = 0x200F011Cull;
+
+static const uint64_t P9N2_C_0_PPM_PFSNS = 0x200F011Cull;
+
+static const uint64_t P9N2_C_1_PPM_PFSNS = 0x210F011Cull;
+
+static const uint64_t P9N2_C_2_PPM_PFSNS = 0x220F011Cull;
+
+static const uint64_t P9N2_C_3_PPM_PFSNS = 0x230F011Cull;
+
+static const uint64_t P9N2_C_4_PPM_PFSNS = 0x240F011Cull;
+
+static const uint64_t P9N2_C_5_PPM_PFSNS = 0x250F011Cull;
+
+static const uint64_t P9N2_C_6_PPM_PFSNS = 0x260F011Cull;
+
+static const uint64_t P9N2_C_7_PPM_PFSNS = 0x270F011Cull;
+
+static const uint64_t P9N2_C_8_PPM_PFSNS = 0x280F011Cull;
+
+static const uint64_t P9N2_C_9_PPM_PFSNS = 0x290F011Cull;
+
+static const uint64_t P9N2_C_10_PPM_PFSNS = 0x2A0F011Cull;
+
+static const uint64_t P9N2_C_11_PPM_PFSNS = 0x2B0F011Cull;
+
+static const uint64_t P9N2_C_12_PPM_PFSNS = 0x2C0F011Cull;
+
+static const uint64_t P9N2_C_13_PPM_PFSNS = 0x2D0F011Cull;
+
+static const uint64_t P9N2_C_14_PPM_PFSNS = 0x2E0F011Cull;
+
+static const uint64_t P9N2_C_15_PPM_PFSNS = 0x2F0F011Cull;
+
+static const uint64_t P9N2_C_16_PPM_PFSNS = 0x300F011Cull;
+
+static const uint64_t P9N2_C_17_PPM_PFSNS = 0x310F011Cull;
+
+static const uint64_t P9N2_C_18_PPM_PFSNS = 0x320F011Cull;
+
+static const uint64_t P9N2_C_19_PPM_PFSNS = 0x330F011Cull;
+
+static const uint64_t P9N2_C_20_PPM_PFSNS = 0x340F011Cull;
+
+static const uint64_t P9N2_C_21_PPM_PFSNS = 0x350F011Cull;
+
+static const uint64_t P9N2_C_22_PPM_PFSNS = 0x360F011Cull;
+
+static const uint64_t P9N2_C_23_PPM_PFSNS = 0x370F011Cull;
+
+static const uint64_t P9N2_EQ_PPM_PFSNS = 0x100F011Cull;
+
+static const uint64_t P9N2_EQ_0_PPM_PFSNS = 0x100F011Cull;
+
+static const uint64_t P9N2_EQ_1_PPM_PFSNS = 0x110F011Cull;
+
+static const uint64_t P9N2_EQ_2_PPM_PFSNS = 0x120F011Cull;
+
+static const uint64_t P9N2_EQ_3_PPM_PFSNS = 0x130F011Cull;
+
+static const uint64_t P9N2_EQ_4_PPM_PFSNS = 0x140F011Cull;
+
+static const uint64_t P9N2_EQ_5_PPM_PFSNS = 0x150F011Cull;
+
+static const uint64_t P9N2_EX_PPM_PFSNS = 0x200F011Cull;
+//DUPS: 210F011C,
+static const uint64_t P9N2_EX_0_PPM_PFSNS = 0x200F011Cull;
+//DUPS: 210F011C,
+static const uint64_t P9N2_EX_1_PPM_PFSNS = 0x220F011Cull;
+//DUPS: 220F011C,
+static const uint64_t P9N2_EX_2_PPM_PFSNS = 0x240F011Cull;
+//DUPS: 250F011C,
+static const uint64_t P9N2_EX_3_PPM_PFSNS = 0x260F011Cull;
+//DUPS: 270F011C,
+static const uint64_t P9N2_EX_4_PPM_PFSNS = 0x280F011Cull;
+//DUPS: 290F011C,
+static const uint64_t P9N2_EX_5_PPM_PFSNS = 0x2A0F011Cull;
+//DUPS: 2B0F011C,
+static const uint64_t P9N2_EX_6_PPM_PFSNS = 0x2C0F011Cull;
+//DUPS: 2D0F011C,
+static const uint64_t P9N2_EX_7_PPM_PFSNS = 0x2E0F011Cull;
+//DUPS: 2F0F011C,
+static const uint64_t P9N2_EX_8_PPM_PFSNS = 0x300F011Cull;
+//DUPS: 310F011C,
+static const uint64_t P9N2_EX_9_PPM_PFSNS = 0x320F011Cull;
+//DUPS: 330F011C,
+static const uint64_t P9N2_EX_10_PPM_PFSNS = 0x340F011Cull;
+//DUPS: 350F011C,
+static const uint64_t P9N2_EX_11_PPM_PFSNS = 0x360F011Cull;
+//DUPS: 370F011C,
+
+static const uint64_t P9N2_C_PPM_PIG = 0x200F0180ull;
+
+static const uint64_t P9N2_C_0_PPM_PIG = 0x200F0180ull;
+
+static const uint64_t P9N2_C_1_PPM_PIG = 0x210F0180ull;
+
+static const uint64_t P9N2_C_2_PPM_PIG = 0x220F0180ull;
+
+static const uint64_t P9N2_C_3_PPM_PIG = 0x230F0180ull;
+
+static const uint64_t P9N2_C_4_PPM_PIG = 0x240F0180ull;
+
+static const uint64_t P9N2_C_5_PPM_PIG = 0x250F0180ull;
+
+static const uint64_t P9N2_C_6_PPM_PIG = 0x260F0180ull;
+
+static const uint64_t P9N2_C_7_PPM_PIG = 0x270F0180ull;
+
+static const uint64_t P9N2_C_8_PPM_PIG = 0x280F0180ull;
+
+static const uint64_t P9N2_C_9_PPM_PIG = 0x290F0180ull;
+
+static const uint64_t P9N2_C_10_PPM_PIG = 0x2A0F0180ull;
+
+static const uint64_t P9N2_C_11_PPM_PIG = 0x2B0F0180ull;
+
+static const uint64_t P9N2_C_12_PPM_PIG = 0x2C0F0180ull;
+
+static const uint64_t P9N2_C_13_PPM_PIG = 0x2D0F0180ull;
+
+static const uint64_t P9N2_C_14_PPM_PIG = 0x2E0F0180ull;
+
+static const uint64_t P9N2_C_15_PPM_PIG = 0x2F0F0180ull;
+
+static const uint64_t P9N2_C_16_PPM_PIG = 0x300F0180ull;
+
+static const uint64_t P9N2_C_17_PPM_PIG = 0x310F0180ull;
+
+static const uint64_t P9N2_C_18_PPM_PIG = 0x320F0180ull;
+
+static const uint64_t P9N2_C_19_PPM_PIG = 0x330F0180ull;
+
+static const uint64_t P9N2_C_20_PPM_PIG = 0x340F0180ull;
+
+static const uint64_t P9N2_C_21_PPM_PIG = 0x350F0180ull;
+
+static const uint64_t P9N2_C_22_PPM_PIG = 0x360F0180ull;
+
+static const uint64_t P9N2_C_23_PPM_PIG = 0x370F0180ull;
+
+static const uint64_t P9N2_EQ_PPM_PIG = 0x100F0180ull;
+
+static const uint64_t P9N2_EQ_0_PPM_PIG = 0x100F0180ull;
+
+static const uint64_t P9N2_EQ_1_PPM_PIG = 0x110F0180ull;
+
+static const uint64_t P9N2_EQ_2_PPM_PIG = 0x120F0180ull;
+
+static const uint64_t P9N2_EQ_3_PPM_PIG = 0x130F0180ull;
+
+static const uint64_t P9N2_EQ_4_PPM_PIG = 0x140F0180ull;
+
+static const uint64_t P9N2_EQ_5_PPM_PIG = 0x150F0180ull;
+
+static const uint64_t P9N2_EX_PPM_PIG = 0x200F0180ull;
+//DUPS: 210F0180,
+static const uint64_t P9N2_EX_0_PPM_PIG = 0x200F0180ull;
+//DUPS: 210F0180,
+static const uint64_t P9N2_EX_1_PPM_PIG = 0x220F0180ull;
+//DUPS: 220F0180,
+static const uint64_t P9N2_EX_2_PPM_PIG = 0x240F0180ull;
+//DUPS: 250F0180,
+static const uint64_t P9N2_EX_3_PPM_PIG = 0x260F0180ull;
+//DUPS: 270F0180,
+static const uint64_t P9N2_EX_4_PPM_PIG = 0x280F0180ull;
+//DUPS: 290F0180,
+static const uint64_t P9N2_EX_5_PPM_PIG = 0x2A0F0180ull;
+//DUPS: 2B0F0180,
+static const uint64_t P9N2_EX_6_PPM_PIG = 0x2C0F0180ull;
+//DUPS: 2D0F0180,
+static const uint64_t P9N2_EX_7_PPM_PIG = 0x2E0F0180ull;
+//DUPS: 2F0F0180,
+static const uint64_t P9N2_EX_8_PPM_PIG = 0x300F0180ull;
+//DUPS: 310F0180,
+static const uint64_t P9N2_EX_9_PPM_PIG = 0x320F0180ull;
+//DUPS: 330F0180,
+static const uint64_t P9N2_EX_10_PPM_PIG = 0x340F0180ull;
+//DUPS: 350F0180,
+static const uint64_t P9N2_EX_11_PPM_PIG = 0x360F0180ull;
+//DUPS: 370F0180,
+
+static const uint64_t P9N2_C_PPM_SCRATCH0 = 0x200F011Eull;
+
+static const uint64_t P9N2_C_0_PPM_SCRATCH0 = 0x200F011Eull;
+
+static const uint64_t P9N2_C_1_PPM_SCRATCH0 = 0x210F011Eull;
+
+static const uint64_t P9N2_C_2_PPM_SCRATCH0 = 0x220F011Eull;
+
+static const uint64_t P9N2_C_3_PPM_SCRATCH0 = 0x230F011Eull;
+
+static const uint64_t P9N2_C_4_PPM_SCRATCH0 = 0x240F011Eull;
+
+static const uint64_t P9N2_C_5_PPM_SCRATCH0 = 0x250F011Eull;
+
+static const uint64_t P9N2_C_6_PPM_SCRATCH0 = 0x260F011Eull;
+
+static const uint64_t P9N2_C_7_PPM_SCRATCH0 = 0x270F011Eull;
+
+static const uint64_t P9N2_C_8_PPM_SCRATCH0 = 0x280F011Eull;
+
+static const uint64_t P9N2_C_9_PPM_SCRATCH0 = 0x290F011Eull;
+
+static const uint64_t P9N2_C_10_PPM_SCRATCH0 = 0x2A0F011Eull;
+
+static const uint64_t P9N2_C_11_PPM_SCRATCH0 = 0x2B0F011Eull;
+
+static const uint64_t P9N2_C_12_PPM_SCRATCH0 = 0x2C0F011Eull;
+
+static const uint64_t P9N2_C_13_PPM_SCRATCH0 = 0x2D0F011Eull;
+
+static const uint64_t P9N2_C_14_PPM_SCRATCH0 = 0x2E0F011Eull;
+
+static const uint64_t P9N2_C_15_PPM_SCRATCH0 = 0x2F0F011Eull;
+
+static const uint64_t P9N2_C_16_PPM_SCRATCH0 = 0x300F011Eull;
+
+static const uint64_t P9N2_C_17_PPM_SCRATCH0 = 0x310F011Eull;
+
+static const uint64_t P9N2_C_18_PPM_SCRATCH0 = 0x320F011Eull;
+
+static const uint64_t P9N2_C_19_PPM_SCRATCH0 = 0x330F011Eull;
+
+static const uint64_t P9N2_C_20_PPM_SCRATCH0 = 0x340F011Eull;
+
+static const uint64_t P9N2_C_21_PPM_SCRATCH0 = 0x350F011Eull;
+
+static const uint64_t P9N2_C_22_PPM_SCRATCH0 = 0x360F011Eull;
+
+static const uint64_t P9N2_C_23_PPM_SCRATCH0 = 0x370F011Eull;
+
+static const uint64_t P9N2_EQ_PPM_SCRATCH0 = 0x100F011Eull;
+
+static const uint64_t P9N2_EQ_0_PPM_SCRATCH0 = 0x100F011Eull;
+
+static const uint64_t P9N2_EQ_1_PPM_SCRATCH0 = 0x110F011Eull;
+
+static const uint64_t P9N2_EQ_2_PPM_SCRATCH0 = 0x120F011Eull;
+
+static const uint64_t P9N2_EQ_3_PPM_SCRATCH0 = 0x130F011Eull;
+
+static const uint64_t P9N2_EQ_4_PPM_SCRATCH0 = 0x140F011Eull;
+
+static const uint64_t P9N2_EQ_5_PPM_SCRATCH0 = 0x150F011Eull;
+
+static const uint64_t P9N2_EX_PPM_SCRATCH0 = 0x200F011Eull;
+//DUPS: 210F011E,
+static const uint64_t P9N2_EX_0_PPM_SCRATCH0 = 0x200F011Eull;
+//DUPS: 210F011E,
+static const uint64_t P9N2_EX_1_PPM_SCRATCH0 = 0x220F011Eull;
+//DUPS: 220F011E,
+static const uint64_t P9N2_EX_2_PPM_SCRATCH0 = 0x240F011Eull;
+//DUPS: 250F011E,
+static const uint64_t P9N2_EX_3_PPM_SCRATCH0 = 0x260F011Eull;
+//DUPS: 270F011E,
+static const uint64_t P9N2_EX_4_PPM_SCRATCH0 = 0x280F011Eull;
+//DUPS: 290F011E,
+static const uint64_t P9N2_EX_5_PPM_SCRATCH0 = 0x2A0F011Eull;
+//DUPS: 2B0F011E,
+static const uint64_t P9N2_EX_6_PPM_SCRATCH0 = 0x2C0F011Eull;
+//DUPS: 2D0F011E,
+static const uint64_t P9N2_EX_7_PPM_SCRATCH0 = 0x2E0F011Eull;
+//DUPS: 2F0F011E,
+static const uint64_t P9N2_EX_8_PPM_SCRATCH0 = 0x300F011Eull;
+//DUPS: 310F011E,
+static const uint64_t P9N2_EX_9_PPM_SCRATCH0 = 0x320F011Eull;
+//DUPS: 330F011E,
+static const uint64_t P9N2_EX_10_PPM_SCRATCH0 = 0x340F011Eull;
+//DUPS: 350F011E,
+static const uint64_t P9N2_EX_11_PPM_SCRATCH0 = 0x360F011Eull;
+//DUPS: 370F011E,
+
+static const uint64_t P9N2_C_PPM_SCRATCH1 = 0x200F011Full;
+
+static const uint64_t P9N2_C_0_PPM_SCRATCH1 = 0x200F011Full;
+
+static const uint64_t P9N2_C_1_PPM_SCRATCH1 = 0x210F011Full;
+
+static const uint64_t P9N2_C_2_PPM_SCRATCH1 = 0x220F011Full;
+
+static const uint64_t P9N2_C_3_PPM_SCRATCH1 = 0x230F011Full;
+
+static const uint64_t P9N2_C_4_PPM_SCRATCH1 = 0x240F011Full;
+
+static const uint64_t P9N2_C_5_PPM_SCRATCH1 = 0x250F011Full;
+
+static const uint64_t P9N2_C_6_PPM_SCRATCH1 = 0x260F011Full;
+
+static const uint64_t P9N2_C_7_PPM_SCRATCH1 = 0x270F011Full;
+
+static const uint64_t P9N2_C_8_PPM_SCRATCH1 = 0x280F011Full;
+
+static const uint64_t P9N2_C_9_PPM_SCRATCH1 = 0x290F011Full;
+
+static const uint64_t P9N2_C_10_PPM_SCRATCH1 = 0x2A0F011Full;
+
+static const uint64_t P9N2_C_11_PPM_SCRATCH1 = 0x2B0F011Full;
+
+static const uint64_t P9N2_C_12_PPM_SCRATCH1 = 0x2C0F011Full;
+
+static const uint64_t P9N2_C_13_PPM_SCRATCH1 = 0x2D0F011Full;
+
+static const uint64_t P9N2_C_14_PPM_SCRATCH1 = 0x2E0F011Full;
+
+static const uint64_t P9N2_C_15_PPM_SCRATCH1 = 0x2F0F011Full;
+
+static const uint64_t P9N2_C_16_PPM_SCRATCH1 = 0x300F011Full;
+
+static const uint64_t P9N2_C_17_PPM_SCRATCH1 = 0x310F011Full;
+
+static const uint64_t P9N2_C_18_PPM_SCRATCH1 = 0x320F011Full;
+
+static const uint64_t P9N2_C_19_PPM_SCRATCH1 = 0x330F011Full;
+
+static const uint64_t P9N2_C_20_PPM_SCRATCH1 = 0x340F011Full;
+
+static const uint64_t P9N2_C_21_PPM_SCRATCH1 = 0x350F011Full;
+
+static const uint64_t P9N2_C_22_PPM_SCRATCH1 = 0x360F011Full;
+
+static const uint64_t P9N2_C_23_PPM_SCRATCH1 = 0x370F011Full;
+
+static const uint64_t P9N2_EQ_PPM_SCRATCH1 = 0x100F011Full;
+
+static const uint64_t P9N2_EQ_0_PPM_SCRATCH1 = 0x100F011Full;
+
+static const uint64_t P9N2_EQ_1_PPM_SCRATCH1 = 0x110F011Full;
+
+static const uint64_t P9N2_EQ_2_PPM_SCRATCH1 = 0x120F011Full;
+
+static const uint64_t P9N2_EQ_3_PPM_SCRATCH1 = 0x130F011Full;
+
+static const uint64_t P9N2_EQ_4_PPM_SCRATCH1 = 0x140F011Full;
+
+static const uint64_t P9N2_EQ_5_PPM_SCRATCH1 = 0x150F011Full;
+
+static const uint64_t P9N2_EX_PPM_SCRATCH1 = 0x200F011Full;
+//DUPS: 210F011F,
+static const uint64_t P9N2_EX_0_PPM_SCRATCH1 = 0x200F011Full;
+//DUPS: 210F011F,
+static const uint64_t P9N2_EX_1_PPM_SCRATCH1 = 0x220F011Full;
+//DUPS: 220F011F,
+static const uint64_t P9N2_EX_2_PPM_SCRATCH1 = 0x240F011Full;
+//DUPS: 250F011F,
+static const uint64_t P9N2_EX_3_PPM_SCRATCH1 = 0x260F011Full;
+//DUPS: 270F011F,
+static const uint64_t P9N2_EX_4_PPM_SCRATCH1 = 0x280F011Full;
+//DUPS: 290F011F,
+static const uint64_t P9N2_EX_5_PPM_SCRATCH1 = 0x2A0F011Full;
+//DUPS: 2B0F011F,
+static const uint64_t P9N2_EX_6_PPM_SCRATCH1 = 0x2C0F011Full;
+//DUPS: 2D0F011F,
+static const uint64_t P9N2_EX_7_PPM_SCRATCH1 = 0x2E0F011Full;
+//DUPS: 2F0F011F,
+static const uint64_t P9N2_EX_8_PPM_SCRATCH1 = 0x300F011Full;
+//DUPS: 310F011F,
+static const uint64_t P9N2_EX_9_PPM_SCRATCH1 = 0x320F011Full;
+//DUPS: 330F011F,
+static const uint64_t P9N2_EX_10_PPM_SCRATCH1 = 0x340F011Full;
+//DUPS: 350F011F,
+static const uint64_t P9N2_EX_11_PPM_SCRATCH1 = 0x360F011Full;
+//DUPS: 370F011F,
+
+static const uint64_t P9N2_C_PPM_SPWKUP_FSP = 0x200F010Bull;
+
+static const uint64_t P9N2_C_0_PPM_SPWKUP_FSP = 0x200F010Bull;
+
+static const uint64_t P9N2_C_1_PPM_SPWKUP_FSP = 0x210F010Bull;
+
+static const uint64_t P9N2_C_2_PPM_SPWKUP_FSP = 0x220F010Bull;
+
+static const uint64_t P9N2_C_3_PPM_SPWKUP_FSP = 0x230F010Bull;
+
+static const uint64_t P9N2_C_4_PPM_SPWKUP_FSP = 0x240F010Bull;
+
+static const uint64_t P9N2_C_5_PPM_SPWKUP_FSP = 0x250F010Bull;
+
+static const uint64_t P9N2_C_6_PPM_SPWKUP_FSP = 0x260F010Bull;
+
+static const uint64_t P9N2_C_7_PPM_SPWKUP_FSP = 0x270F010Bull;
+
+static const uint64_t P9N2_C_8_PPM_SPWKUP_FSP = 0x280F010Bull;
+
+static const uint64_t P9N2_C_9_PPM_SPWKUP_FSP = 0x290F010Bull;
+
+static const uint64_t P9N2_C_10_PPM_SPWKUP_FSP = 0x2A0F010Bull;
+
+static const uint64_t P9N2_C_11_PPM_SPWKUP_FSP = 0x2B0F010Bull;
+
+static const uint64_t P9N2_C_12_PPM_SPWKUP_FSP = 0x2C0F010Bull;
+
+static const uint64_t P9N2_C_13_PPM_SPWKUP_FSP = 0x2D0F010Bull;
+
+static const uint64_t P9N2_C_14_PPM_SPWKUP_FSP = 0x2E0F010Bull;
+
+static const uint64_t P9N2_C_15_PPM_SPWKUP_FSP = 0x2F0F010Bull;
+
+static const uint64_t P9N2_C_16_PPM_SPWKUP_FSP = 0x300F010Bull;
+
+static const uint64_t P9N2_C_17_PPM_SPWKUP_FSP = 0x310F010Bull;
+
+static const uint64_t P9N2_C_18_PPM_SPWKUP_FSP = 0x320F010Bull;
+
+static const uint64_t P9N2_C_19_PPM_SPWKUP_FSP = 0x330F010Bull;
+
+static const uint64_t P9N2_C_20_PPM_SPWKUP_FSP = 0x340F010Bull;
+
+static const uint64_t P9N2_C_21_PPM_SPWKUP_FSP = 0x350F010Bull;
+
+static const uint64_t P9N2_C_22_PPM_SPWKUP_FSP = 0x360F010Bull;
+
+static const uint64_t P9N2_C_23_PPM_SPWKUP_FSP = 0x370F010Bull;
+
+static const uint64_t P9N2_EQ_PPM_SPWKUP_FSP = 0x100F010Bull;
+
+static const uint64_t P9N2_EQ_0_PPM_SPWKUP_FSP = 0x100F010Bull;
+
+static const uint64_t P9N2_EQ_1_PPM_SPWKUP_FSP = 0x110F010Bull;
+
+static const uint64_t P9N2_EQ_2_PPM_SPWKUP_FSP = 0x120F010Bull;
+
+static const uint64_t P9N2_EQ_3_PPM_SPWKUP_FSP = 0x130F010Bull;
+
+static const uint64_t P9N2_EQ_4_PPM_SPWKUP_FSP = 0x140F010Bull;
+
+static const uint64_t P9N2_EQ_5_PPM_SPWKUP_FSP = 0x150F010Bull;
+
+static const uint64_t P9N2_EX_PPM_SPWKUP_FSP = 0x200F010Bull;
+//DUPS: 210F010B,
+static const uint64_t P9N2_EX_0_PPM_SPWKUP_FSP = 0x200F010Bull;
+//DUPS: 210F010B,
+static const uint64_t P9N2_EX_1_PPM_SPWKUP_FSP = 0x220F010Bull;
+//DUPS: 220F010B,
+static const uint64_t P9N2_EX_2_PPM_SPWKUP_FSP = 0x240F010Bull;
+//DUPS: 250F010B,
+static const uint64_t P9N2_EX_3_PPM_SPWKUP_FSP = 0x260F010Bull;
+//DUPS: 270F010B,
+static const uint64_t P9N2_EX_4_PPM_SPWKUP_FSP = 0x280F010Bull;
+//DUPS: 290F010B,
+static const uint64_t P9N2_EX_5_PPM_SPWKUP_FSP = 0x2A0F010Bull;
+//DUPS: 2B0F010B,
+static const uint64_t P9N2_EX_6_PPM_SPWKUP_FSP = 0x2C0F010Bull;
+//DUPS: 2D0F010B,
+static const uint64_t P9N2_EX_7_PPM_SPWKUP_FSP = 0x2E0F010Bull;
+//DUPS: 2F0F010B,
+static const uint64_t P9N2_EX_8_PPM_SPWKUP_FSP = 0x300F010Bull;
+//DUPS: 310F010B,
+static const uint64_t P9N2_EX_9_PPM_SPWKUP_FSP = 0x320F010Bull;
+//DUPS: 330F010B,
+static const uint64_t P9N2_EX_10_PPM_SPWKUP_FSP = 0x340F010Bull;
+//DUPS: 350F010B,
+static const uint64_t P9N2_EX_11_PPM_SPWKUP_FSP = 0x360F010Bull;
+//DUPS: 370F010B,
+
+static const uint64_t P9N2_C_PPM_SPWKUP_HYP = 0x200F010Dull;
+
+static const uint64_t P9N2_C_0_PPM_SPWKUP_HYP = 0x200F010Dull;
+
+static const uint64_t P9N2_C_1_PPM_SPWKUP_HYP = 0x210F010Dull;
+
+static const uint64_t P9N2_C_2_PPM_SPWKUP_HYP = 0x220F010Dull;
+
+static const uint64_t P9N2_C_3_PPM_SPWKUP_HYP = 0x230F010Dull;
+
+static const uint64_t P9N2_C_4_PPM_SPWKUP_HYP = 0x240F010Dull;
+
+static const uint64_t P9N2_C_5_PPM_SPWKUP_HYP = 0x250F010Dull;
+
+static const uint64_t P9N2_C_6_PPM_SPWKUP_HYP = 0x260F010Dull;
+
+static const uint64_t P9N2_C_7_PPM_SPWKUP_HYP = 0x270F010Dull;
+
+static const uint64_t P9N2_C_8_PPM_SPWKUP_HYP = 0x280F010Dull;
+
+static const uint64_t P9N2_C_9_PPM_SPWKUP_HYP = 0x290F010Dull;
+
+static const uint64_t P9N2_C_10_PPM_SPWKUP_HYP = 0x2A0F010Dull;
+
+static const uint64_t P9N2_C_11_PPM_SPWKUP_HYP = 0x2B0F010Dull;
+
+static const uint64_t P9N2_C_12_PPM_SPWKUP_HYP = 0x2C0F010Dull;
+
+static const uint64_t P9N2_C_13_PPM_SPWKUP_HYP = 0x2D0F010Dull;
+
+static const uint64_t P9N2_C_14_PPM_SPWKUP_HYP = 0x2E0F010Dull;
+
+static const uint64_t P9N2_C_15_PPM_SPWKUP_HYP = 0x2F0F010Dull;
+
+static const uint64_t P9N2_C_16_PPM_SPWKUP_HYP = 0x300F010Dull;
+
+static const uint64_t P9N2_C_17_PPM_SPWKUP_HYP = 0x310F010Dull;
+
+static const uint64_t P9N2_C_18_PPM_SPWKUP_HYP = 0x320F010Dull;
+
+static const uint64_t P9N2_C_19_PPM_SPWKUP_HYP = 0x330F010Dull;
+
+static const uint64_t P9N2_C_20_PPM_SPWKUP_HYP = 0x340F010Dull;
+
+static const uint64_t P9N2_C_21_PPM_SPWKUP_HYP = 0x350F010Dull;
+
+static const uint64_t P9N2_C_22_PPM_SPWKUP_HYP = 0x360F010Dull;
+
+static const uint64_t P9N2_C_23_PPM_SPWKUP_HYP = 0x370F010Dull;
+
+static const uint64_t P9N2_EQ_PPM_SPWKUP_HYP = 0x100F010Dull;
+
+static const uint64_t P9N2_EQ_0_PPM_SPWKUP_HYP = 0x100F010Dull;
+
+static const uint64_t P9N2_EQ_1_PPM_SPWKUP_HYP = 0x110F010Dull;
+
+static const uint64_t P9N2_EQ_2_PPM_SPWKUP_HYP = 0x120F010Dull;
+
+static const uint64_t P9N2_EQ_3_PPM_SPWKUP_HYP = 0x130F010Dull;
+
+static const uint64_t P9N2_EQ_4_PPM_SPWKUP_HYP = 0x140F010Dull;
+
+static const uint64_t P9N2_EQ_5_PPM_SPWKUP_HYP = 0x150F010Dull;
+
+static const uint64_t P9N2_EX_PPM_SPWKUP_HYP = 0x200F010Dull;
+//DUPS: 210F010D,
+static const uint64_t P9N2_EX_0_PPM_SPWKUP_HYP = 0x200F010Dull;
+//DUPS: 210F010D,
+static const uint64_t P9N2_EX_1_PPM_SPWKUP_HYP = 0x220F010Dull;
+//DUPS: 220F010D,
+static const uint64_t P9N2_EX_2_PPM_SPWKUP_HYP = 0x240F010Dull;
+//DUPS: 250F010D,
+static const uint64_t P9N2_EX_3_PPM_SPWKUP_HYP = 0x260F010Dull;
+//DUPS: 270F010D,
+static const uint64_t P9N2_EX_4_PPM_SPWKUP_HYP = 0x280F010Dull;
+//DUPS: 290F010D,
+static const uint64_t P9N2_EX_5_PPM_SPWKUP_HYP = 0x2A0F010Dull;
+//DUPS: 2B0F010D,
+static const uint64_t P9N2_EX_6_PPM_SPWKUP_HYP = 0x2C0F010Dull;
+//DUPS: 2D0F010D,
+static const uint64_t P9N2_EX_7_PPM_SPWKUP_HYP = 0x2E0F010Dull;
+//DUPS: 2F0F010D,
+static const uint64_t P9N2_EX_8_PPM_SPWKUP_HYP = 0x300F010Dull;
+//DUPS: 310F010D,
+static const uint64_t P9N2_EX_9_PPM_SPWKUP_HYP = 0x320F010Dull;
+//DUPS: 330F010D,
+static const uint64_t P9N2_EX_10_PPM_SPWKUP_HYP = 0x340F010Dull;
+//DUPS: 350F010D,
+static const uint64_t P9N2_EX_11_PPM_SPWKUP_HYP = 0x360F010Dull;
+//DUPS: 370F010D,
+
+static const uint64_t P9N2_C_PPM_SPWKUP_OCC = 0x200F010Cull;
+
+static const uint64_t P9N2_C_0_PPM_SPWKUP_OCC = 0x200F010Cull;
+
+static const uint64_t P9N2_C_1_PPM_SPWKUP_OCC = 0x210F010Cull;
+
+static const uint64_t P9N2_C_2_PPM_SPWKUP_OCC = 0x220F010Cull;
+
+static const uint64_t P9N2_C_3_PPM_SPWKUP_OCC = 0x230F010Cull;
+
+static const uint64_t P9N2_C_4_PPM_SPWKUP_OCC = 0x240F010Cull;
+
+static const uint64_t P9N2_C_5_PPM_SPWKUP_OCC = 0x250F010Cull;
+
+static const uint64_t P9N2_C_6_PPM_SPWKUP_OCC = 0x260F010Cull;
+
+static const uint64_t P9N2_C_7_PPM_SPWKUP_OCC = 0x270F010Cull;
+
+static const uint64_t P9N2_C_8_PPM_SPWKUP_OCC = 0x280F010Cull;
+
+static const uint64_t P9N2_C_9_PPM_SPWKUP_OCC = 0x290F010Cull;
+
+static const uint64_t P9N2_C_10_PPM_SPWKUP_OCC = 0x2A0F010Cull;
+
+static const uint64_t P9N2_C_11_PPM_SPWKUP_OCC = 0x2B0F010Cull;
+
+static const uint64_t P9N2_C_12_PPM_SPWKUP_OCC = 0x2C0F010Cull;
+
+static const uint64_t P9N2_C_13_PPM_SPWKUP_OCC = 0x2D0F010Cull;
+
+static const uint64_t P9N2_C_14_PPM_SPWKUP_OCC = 0x2E0F010Cull;
+
+static const uint64_t P9N2_C_15_PPM_SPWKUP_OCC = 0x2F0F010Cull;
+
+static const uint64_t P9N2_C_16_PPM_SPWKUP_OCC = 0x300F010Cull;
+
+static const uint64_t P9N2_C_17_PPM_SPWKUP_OCC = 0x310F010Cull;
+
+static const uint64_t P9N2_C_18_PPM_SPWKUP_OCC = 0x320F010Cull;
+
+static const uint64_t P9N2_C_19_PPM_SPWKUP_OCC = 0x330F010Cull;
+
+static const uint64_t P9N2_C_20_PPM_SPWKUP_OCC = 0x340F010Cull;
+
+static const uint64_t P9N2_C_21_PPM_SPWKUP_OCC = 0x350F010Cull;
+
+static const uint64_t P9N2_C_22_PPM_SPWKUP_OCC = 0x360F010Cull;
+
+static const uint64_t P9N2_C_23_PPM_SPWKUP_OCC = 0x370F010Cull;
+
+static const uint64_t P9N2_EQ_PPM_SPWKUP_OCC = 0x100F010Cull;
+
+static const uint64_t P9N2_EQ_0_PPM_SPWKUP_OCC = 0x100F010Cull;
+
+static const uint64_t P9N2_EQ_1_PPM_SPWKUP_OCC = 0x110F010Cull;
+
+static const uint64_t P9N2_EQ_2_PPM_SPWKUP_OCC = 0x120F010Cull;
+
+static const uint64_t P9N2_EQ_3_PPM_SPWKUP_OCC = 0x130F010Cull;
+
+static const uint64_t P9N2_EQ_4_PPM_SPWKUP_OCC = 0x140F010Cull;
+
+static const uint64_t P9N2_EQ_5_PPM_SPWKUP_OCC = 0x150F010Cull;
+
+static const uint64_t P9N2_EX_PPM_SPWKUP_OCC = 0x200F010Cull;
+//DUPS: 210F010C,
+static const uint64_t P9N2_EX_0_PPM_SPWKUP_OCC = 0x200F010Cull;
+//DUPS: 210F010C,
+static const uint64_t P9N2_EX_1_PPM_SPWKUP_OCC = 0x220F010Cull;
+//DUPS: 220F010C,
+static const uint64_t P9N2_EX_2_PPM_SPWKUP_OCC = 0x240F010Cull;
+//DUPS: 250F010C,
+static const uint64_t P9N2_EX_3_PPM_SPWKUP_OCC = 0x260F010Cull;
+//DUPS: 270F010C,
+static const uint64_t P9N2_EX_4_PPM_SPWKUP_OCC = 0x280F010Cull;
+//DUPS: 290F010C,
+static const uint64_t P9N2_EX_5_PPM_SPWKUP_OCC = 0x2A0F010Cull;
+//DUPS: 2B0F010C,
+static const uint64_t P9N2_EX_6_PPM_SPWKUP_OCC = 0x2C0F010Cull;
+//DUPS: 2D0F010C,
+static const uint64_t P9N2_EX_7_PPM_SPWKUP_OCC = 0x2E0F010Cull;
+//DUPS: 2F0F010C,
+static const uint64_t P9N2_EX_8_PPM_SPWKUP_OCC = 0x300F010Cull;
+//DUPS: 310F010C,
+static const uint64_t P9N2_EX_9_PPM_SPWKUP_OCC = 0x320F010Cull;
+//DUPS: 330F010C,
+static const uint64_t P9N2_EX_10_PPM_SPWKUP_OCC = 0x340F010Cull;
+//DUPS: 350F010C,
+static const uint64_t P9N2_EX_11_PPM_SPWKUP_OCC = 0x360F010Cull;
+//DUPS: 370F010C,
+
+static const uint64_t P9N2_C_PPM_SPWKUP_OTR = 0x200F010Aull;
+
+static const uint64_t P9N2_C_0_PPM_SPWKUP_OTR = 0x200F010Aull;
+
+static const uint64_t P9N2_C_1_PPM_SPWKUP_OTR = 0x210F010Aull;
+
+static const uint64_t P9N2_C_2_PPM_SPWKUP_OTR = 0x220F010Aull;
+
+static const uint64_t P9N2_C_3_PPM_SPWKUP_OTR = 0x230F010Aull;
+
+static const uint64_t P9N2_C_4_PPM_SPWKUP_OTR = 0x240F010Aull;
+
+static const uint64_t P9N2_C_5_PPM_SPWKUP_OTR = 0x250F010Aull;
+
+static const uint64_t P9N2_C_6_PPM_SPWKUP_OTR = 0x260F010Aull;
+
+static const uint64_t P9N2_C_7_PPM_SPWKUP_OTR = 0x270F010Aull;
+
+static const uint64_t P9N2_C_8_PPM_SPWKUP_OTR = 0x280F010Aull;
+
+static const uint64_t P9N2_C_9_PPM_SPWKUP_OTR = 0x290F010Aull;
+
+static const uint64_t P9N2_C_10_PPM_SPWKUP_OTR = 0x2A0F010Aull;
+
+static const uint64_t P9N2_C_11_PPM_SPWKUP_OTR = 0x2B0F010Aull;
+
+static const uint64_t P9N2_C_12_PPM_SPWKUP_OTR = 0x2C0F010Aull;
+
+static const uint64_t P9N2_C_13_PPM_SPWKUP_OTR = 0x2D0F010Aull;
+
+static const uint64_t P9N2_C_14_PPM_SPWKUP_OTR = 0x2E0F010Aull;
+
+static const uint64_t P9N2_C_15_PPM_SPWKUP_OTR = 0x2F0F010Aull;
+
+static const uint64_t P9N2_C_16_PPM_SPWKUP_OTR = 0x300F010Aull;
+
+static const uint64_t P9N2_C_17_PPM_SPWKUP_OTR = 0x310F010Aull;
+
+static const uint64_t P9N2_C_18_PPM_SPWKUP_OTR = 0x320F010Aull;
+
+static const uint64_t P9N2_C_19_PPM_SPWKUP_OTR = 0x330F010Aull;
+
+static const uint64_t P9N2_C_20_PPM_SPWKUP_OTR = 0x340F010Aull;
+
+static const uint64_t P9N2_C_21_PPM_SPWKUP_OTR = 0x350F010Aull;
+
+static const uint64_t P9N2_C_22_PPM_SPWKUP_OTR = 0x360F010Aull;
+
+static const uint64_t P9N2_C_23_PPM_SPWKUP_OTR = 0x370F010Aull;
+
+static const uint64_t P9N2_EQ_PPM_SPWKUP_OTR = 0x100F010Aull;
+
+static const uint64_t P9N2_EQ_0_PPM_SPWKUP_OTR = 0x100F010Aull;
+
+static const uint64_t P9N2_EQ_1_PPM_SPWKUP_OTR = 0x110F010Aull;
+
+static const uint64_t P9N2_EQ_2_PPM_SPWKUP_OTR = 0x120F010Aull;
+
+static const uint64_t P9N2_EQ_3_PPM_SPWKUP_OTR = 0x130F010Aull;
+
+static const uint64_t P9N2_EQ_4_PPM_SPWKUP_OTR = 0x140F010Aull;
+
+static const uint64_t P9N2_EQ_5_PPM_SPWKUP_OTR = 0x150F010Aull;
+
+static const uint64_t P9N2_EX_PPM_SPWKUP_OTR = 0x200F010Aull;
+//DUPS: 210F010A,
+static const uint64_t P9N2_EX_0_PPM_SPWKUP_OTR = 0x200F010Aull;
+//DUPS: 210F010A,
+static const uint64_t P9N2_EX_1_PPM_SPWKUP_OTR = 0x220F010Aull;
+//DUPS: 220F010A,
+static const uint64_t P9N2_EX_2_PPM_SPWKUP_OTR = 0x240F010Aull;
+//DUPS: 250F010A,
+static const uint64_t P9N2_EX_3_PPM_SPWKUP_OTR = 0x260F010Aull;
+//DUPS: 270F010A,
+static const uint64_t P9N2_EX_4_PPM_SPWKUP_OTR = 0x280F010Aull;
+//DUPS: 290F010A,
+static const uint64_t P9N2_EX_5_PPM_SPWKUP_OTR = 0x2A0F010Aull;
+//DUPS: 2B0F010A,
+static const uint64_t P9N2_EX_6_PPM_SPWKUP_OTR = 0x2C0F010Aull;
+//DUPS: 2D0F010A,
+static const uint64_t P9N2_EX_7_PPM_SPWKUP_OTR = 0x2E0F010Aull;
+//DUPS: 2F0F010A,
+static const uint64_t P9N2_EX_8_PPM_SPWKUP_OTR = 0x300F010Aull;
+//DUPS: 310F010A,
+static const uint64_t P9N2_EX_9_PPM_SPWKUP_OTR = 0x320F010Aull;
+//DUPS: 330F010A,
+static const uint64_t P9N2_EX_10_PPM_SPWKUP_OTR = 0x340F010Aull;
+//DUPS: 350F010A,
+static const uint64_t P9N2_EX_11_PPM_SPWKUP_OTR = 0x360F010Aull;
+//DUPS: 370F010A,
+
+static const uint64_t P9N2_C_PPM_SSHFSP = 0x200F0111ull;
+
+static const uint64_t P9N2_C_0_PPM_SSHFSP = 0x200F0111ull;
+
+static const uint64_t P9N2_C_1_PPM_SSHFSP = 0x210F0111ull;
+
+static const uint64_t P9N2_C_2_PPM_SSHFSP = 0x220F0111ull;
+
+static const uint64_t P9N2_C_3_PPM_SSHFSP = 0x230F0111ull;
+
+static const uint64_t P9N2_C_4_PPM_SSHFSP = 0x240F0111ull;
+
+static const uint64_t P9N2_C_5_PPM_SSHFSP = 0x250F0111ull;
+
+static const uint64_t P9N2_C_6_PPM_SSHFSP = 0x260F0111ull;
+
+static const uint64_t P9N2_C_7_PPM_SSHFSP = 0x270F0111ull;
+
+static const uint64_t P9N2_C_8_PPM_SSHFSP = 0x280F0111ull;
+
+static const uint64_t P9N2_C_9_PPM_SSHFSP = 0x290F0111ull;
+
+static const uint64_t P9N2_C_10_PPM_SSHFSP = 0x2A0F0111ull;
+
+static const uint64_t P9N2_C_11_PPM_SSHFSP = 0x2B0F0111ull;
+
+static const uint64_t P9N2_C_12_PPM_SSHFSP = 0x2C0F0111ull;
+
+static const uint64_t P9N2_C_13_PPM_SSHFSP = 0x2D0F0111ull;
+
+static const uint64_t P9N2_C_14_PPM_SSHFSP = 0x2E0F0111ull;
+
+static const uint64_t P9N2_C_15_PPM_SSHFSP = 0x2F0F0111ull;
+
+static const uint64_t P9N2_C_16_PPM_SSHFSP = 0x300F0111ull;
+
+static const uint64_t P9N2_C_17_PPM_SSHFSP = 0x310F0111ull;
+
+static const uint64_t P9N2_C_18_PPM_SSHFSP = 0x320F0111ull;
+
+static const uint64_t P9N2_C_19_PPM_SSHFSP = 0x330F0111ull;
+
+static const uint64_t P9N2_C_20_PPM_SSHFSP = 0x340F0111ull;
+
+static const uint64_t P9N2_C_21_PPM_SSHFSP = 0x350F0111ull;
+
+static const uint64_t P9N2_C_22_PPM_SSHFSP = 0x360F0111ull;
+
+static const uint64_t P9N2_C_23_PPM_SSHFSP = 0x370F0111ull;
+
+static const uint64_t P9N2_EQ_PPM_SSHFSP = 0x100F0111ull;
+
+static const uint64_t P9N2_EQ_0_PPM_SSHFSP = 0x100F0111ull;
+
+static const uint64_t P9N2_EQ_1_PPM_SSHFSP = 0x110F0111ull;
+
+static const uint64_t P9N2_EQ_2_PPM_SSHFSP = 0x120F0111ull;
+
+static const uint64_t P9N2_EQ_3_PPM_SSHFSP = 0x130F0111ull;
+
+static const uint64_t P9N2_EQ_4_PPM_SSHFSP = 0x140F0111ull;
+
+static const uint64_t P9N2_EQ_5_PPM_SSHFSP = 0x150F0111ull;
+
+static const uint64_t P9N2_EX_PPM_SSHFSP = 0x200F0111ull;
+//DUPS: 210F0111,
+static const uint64_t P9N2_EX_0_PPM_SSHFSP = 0x200F0111ull;
+//DUPS: 210F0111,
+static const uint64_t P9N2_EX_1_PPM_SSHFSP = 0x220F0111ull;
+//DUPS: 220F0111,
+static const uint64_t P9N2_EX_2_PPM_SSHFSP = 0x240F0111ull;
+//DUPS: 250F0111,
+static const uint64_t P9N2_EX_3_PPM_SSHFSP = 0x260F0111ull;
+//DUPS: 270F0111,
+static const uint64_t P9N2_EX_4_PPM_SSHFSP = 0x280F0111ull;
+//DUPS: 290F0111,
+static const uint64_t P9N2_EX_5_PPM_SSHFSP = 0x2A0F0111ull;
+//DUPS: 2B0F0111,
+static const uint64_t P9N2_EX_6_PPM_SSHFSP = 0x2C0F0111ull;
+//DUPS: 2D0F0111,
+static const uint64_t P9N2_EX_7_PPM_SSHFSP = 0x2E0F0111ull;
+//DUPS: 2F0F0111,
+static const uint64_t P9N2_EX_8_PPM_SSHFSP = 0x300F0111ull;
+//DUPS: 310F0111,
+static const uint64_t P9N2_EX_9_PPM_SSHFSP = 0x320F0111ull;
+//DUPS: 330F0111,
+static const uint64_t P9N2_EX_10_PPM_SSHFSP = 0x340F0111ull;
+//DUPS: 350F0111,
+static const uint64_t P9N2_EX_11_PPM_SSHFSP = 0x360F0111ull;
+//DUPS: 370F0111,
+
+static const uint64_t P9N2_C_PPM_SSHHYP = 0x200F0114ull;
+
+static const uint64_t P9N2_C_0_PPM_SSHHYP = 0x200F0114ull;
+
+static const uint64_t P9N2_C_1_PPM_SSHHYP = 0x210F0114ull;
+
+static const uint64_t P9N2_C_2_PPM_SSHHYP = 0x220F0114ull;
+
+static const uint64_t P9N2_C_3_PPM_SSHHYP = 0x230F0114ull;
+
+static const uint64_t P9N2_C_4_PPM_SSHHYP = 0x240F0114ull;
+
+static const uint64_t P9N2_C_5_PPM_SSHHYP = 0x250F0114ull;
+
+static const uint64_t P9N2_C_6_PPM_SSHHYP = 0x260F0114ull;
+
+static const uint64_t P9N2_C_7_PPM_SSHHYP = 0x270F0114ull;
+
+static const uint64_t P9N2_C_8_PPM_SSHHYP = 0x280F0114ull;
+
+static const uint64_t P9N2_C_9_PPM_SSHHYP = 0x290F0114ull;
+
+static const uint64_t P9N2_C_10_PPM_SSHHYP = 0x2A0F0114ull;
+
+static const uint64_t P9N2_C_11_PPM_SSHHYP = 0x2B0F0114ull;
+
+static const uint64_t P9N2_C_12_PPM_SSHHYP = 0x2C0F0114ull;
+
+static const uint64_t P9N2_C_13_PPM_SSHHYP = 0x2D0F0114ull;
+
+static const uint64_t P9N2_C_14_PPM_SSHHYP = 0x2E0F0114ull;
+
+static const uint64_t P9N2_C_15_PPM_SSHHYP = 0x2F0F0114ull;
+
+static const uint64_t P9N2_C_16_PPM_SSHHYP = 0x300F0114ull;
+
+static const uint64_t P9N2_C_17_PPM_SSHHYP = 0x310F0114ull;
+
+static const uint64_t P9N2_C_18_PPM_SSHHYP = 0x320F0114ull;
+
+static const uint64_t P9N2_C_19_PPM_SSHHYP = 0x330F0114ull;
+
+static const uint64_t P9N2_C_20_PPM_SSHHYP = 0x340F0114ull;
+
+static const uint64_t P9N2_C_21_PPM_SSHHYP = 0x350F0114ull;
+
+static const uint64_t P9N2_C_22_PPM_SSHHYP = 0x360F0114ull;
+
+static const uint64_t P9N2_C_23_PPM_SSHHYP = 0x370F0114ull;
+
+static const uint64_t P9N2_EQ_PPM_SSHHYP = 0x100F0114ull;
+
+static const uint64_t P9N2_EQ_0_PPM_SSHHYP = 0x100F0114ull;
+
+static const uint64_t P9N2_EQ_1_PPM_SSHHYP = 0x110F0114ull;
+
+static const uint64_t P9N2_EQ_2_PPM_SSHHYP = 0x120F0114ull;
+
+static const uint64_t P9N2_EQ_3_PPM_SSHHYP = 0x130F0114ull;
+
+static const uint64_t P9N2_EQ_4_PPM_SSHHYP = 0x140F0114ull;
+
+static const uint64_t P9N2_EQ_5_PPM_SSHHYP = 0x150F0114ull;
+
+static const uint64_t P9N2_EX_PPM_SSHHYP = 0x200F0114ull;
+//DUPS: 210F0114,
+static const uint64_t P9N2_EX_0_PPM_SSHHYP = 0x200F0114ull;
+//DUPS: 210F0114,
+static const uint64_t P9N2_EX_1_PPM_SSHHYP = 0x220F0114ull;
+//DUPS: 220F0114,
+static const uint64_t P9N2_EX_2_PPM_SSHHYP = 0x240F0114ull;
+//DUPS: 250F0114,
+static const uint64_t P9N2_EX_3_PPM_SSHHYP = 0x260F0114ull;
+//DUPS: 270F0114,
+static const uint64_t P9N2_EX_4_PPM_SSHHYP = 0x280F0114ull;
+//DUPS: 290F0114,
+static const uint64_t P9N2_EX_5_PPM_SSHHYP = 0x2A0F0114ull;
+//DUPS: 2B0F0114,
+static const uint64_t P9N2_EX_6_PPM_SSHHYP = 0x2C0F0114ull;
+//DUPS: 2D0F0114,
+static const uint64_t P9N2_EX_7_PPM_SSHHYP = 0x2E0F0114ull;
+//DUPS: 2F0F0114,
+static const uint64_t P9N2_EX_8_PPM_SSHHYP = 0x300F0114ull;
+//DUPS: 310F0114,
+static const uint64_t P9N2_EX_9_PPM_SSHHYP = 0x320F0114ull;
+//DUPS: 330F0114,
+static const uint64_t P9N2_EX_10_PPM_SSHHYP = 0x340F0114ull;
+//DUPS: 350F0114,
+static const uint64_t P9N2_EX_11_PPM_SSHHYP = 0x360F0114ull;
+//DUPS: 370F0114,
+
+static const uint64_t P9N2_C_PPM_SSHOCC = 0x200F0112ull;
+
+static const uint64_t P9N2_C_0_PPM_SSHOCC = 0x200F0112ull;
+
+static const uint64_t P9N2_C_1_PPM_SSHOCC = 0x210F0112ull;
+
+static const uint64_t P9N2_C_2_PPM_SSHOCC = 0x220F0112ull;
+
+static const uint64_t P9N2_C_3_PPM_SSHOCC = 0x230F0112ull;
+
+static const uint64_t P9N2_C_4_PPM_SSHOCC = 0x240F0112ull;
+
+static const uint64_t P9N2_C_5_PPM_SSHOCC = 0x250F0112ull;
+
+static const uint64_t P9N2_C_6_PPM_SSHOCC = 0x260F0112ull;
+
+static const uint64_t P9N2_C_7_PPM_SSHOCC = 0x270F0112ull;
+
+static const uint64_t P9N2_C_8_PPM_SSHOCC = 0x280F0112ull;
+
+static const uint64_t P9N2_C_9_PPM_SSHOCC = 0x290F0112ull;
+
+static const uint64_t P9N2_C_10_PPM_SSHOCC = 0x2A0F0112ull;
+
+static const uint64_t P9N2_C_11_PPM_SSHOCC = 0x2B0F0112ull;
+
+static const uint64_t P9N2_C_12_PPM_SSHOCC = 0x2C0F0112ull;
+
+static const uint64_t P9N2_C_13_PPM_SSHOCC = 0x2D0F0112ull;
+
+static const uint64_t P9N2_C_14_PPM_SSHOCC = 0x2E0F0112ull;
+
+static const uint64_t P9N2_C_15_PPM_SSHOCC = 0x2F0F0112ull;
+
+static const uint64_t P9N2_C_16_PPM_SSHOCC = 0x300F0112ull;
+
+static const uint64_t P9N2_C_17_PPM_SSHOCC = 0x310F0112ull;
+
+static const uint64_t P9N2_C_18_PPM_SSHOCC = 0x320F0112ull;
+
+static const uint64_t P9N2_C_19_PPM_SSHOCC = 0x330F0112ull;
+
+static const uint64_t P9N2_C_20_PPM_SSHOCC = 0x340F0112ull;
+
+static const uint64_t P9N2_C_21_PPM_SSHOCC = 0x350F0112ull;
+
+static const uint64_t P9N2_C_22_PPM_SSHOCC = 0x360F0112ull;
+
+static const uint64_t P9N2_C_23_PPM_SSHOCC = 0x370F0112ull;
+
+static const uint64_t P9N2_EQ_PPM_SSHOCC = 0x100F0112ull;
+
+static const uint64_t P9N2_EQ_0_PPM_SSHOCC = 0x100F0112ull;
+
+static const uint64_t P9N2_EQ_1_PPM_SSHOCC = 0x110F0112ull;
+
+static const uint64_t P9N2_EQ_2_PPM_SSHOCC = 0x120F0112ull;
+
+static const uint64_t P9N2_EQ_3_PPM_SSHOCC = 0x130F0112ull;
+
+static const uint64_t P9N2_EQ_4_PPM_SSHOCC = 0x140F0112ull;
+
+static const uint64_t P9N2_EQ_5_PPM_SSHOCC = 0x150F0112ull;
+
+static const uint64_t P9N2_EX_PPM_SSHOCC = 0x200F0112ull;
+//DUPS: 210F0112,
+static const uint64_t P9N2_EX_0_PPM_SSHOCC = 0x200F0112ull;
+//DUPS: 210F0112,
+static const uint64_t P9N2_EX_1_PPM_SSHOCC = 0x220F0112ull;
+//DUPS: 220F0112,
+static const uint64_t P9N2_EX_2_PPM_SSHOCC = 0x240F0112ull;
+//DUPS: 250F0112,
+static const uint64_t P9N2_EX_3_PPM_SSHOCC = 0x260F0112ull;
+//DUPS: 270F0112,
+static const uint64_t P9N2_EX_4_PPM_SSHOCC = 0x280F0112ull;
+//DUPS: 290F0112,
+static const uint64_t P9N2_EX_5_PPM_SSHOCC = 0x2A0F0112ull;
+//DUPS: 2B0F0112,
+static const uint64_t P9N2_EX_6_PPM_SSHOCC = 0x2C0F0112ull;
+//DUPS: 2D0F0112,
+static const uint64_t P9N2_EX_7_PPM_SSHOCC = 0x2E0F0112ull;
+//DUPS: 2F0F0112,
+static const uint64_t P9N2_EX_8_PPM_SSHOCC = 0x300F0112ull;
+//DUPS: 310F0112,
+static const uint64_t P9N2_EX_9_PPM_SSHOCC = 0x320F0112ull;
+//DUPS: 330F0112,
+static const uint64_t P9N2_EX_10_PPM_SSHOCC = 0x340F0112ull;
+//DUPS: 350F0112,
+static const uint64_t P9N2_EX_11_PPM_SSHOCC = 0x360F0112ull;
+//DUPS: 370F0112,
+
+static const uint64_t P9N2_C_PPM_SSHOTR = 0x200F0113ull;
+
+static const uint64_t P9N2_C_0_PPM_SSHOTR = 0x200F0113ull;
+
+static const uint64_t P9N2_C_1_PPM_SSHOTR = 0x210F0113ull;
+
+static const uint64_t P9N2_C_2_PPM_SSHOTR = 0x220F0113ull;
+
+static const uint64_t P9N2_C_3_PPM_SSHOTR = 0x230F0113ull;
+
+static const uint64_t P9N2_C_4_PPM_SSHOTR = 0x240F0113ull;
+
+static const uint64_t P9N2_C_5_PPM_SSHOTR = 0x250F0113ull;
+
+static const uint64_t P9N2_C_6_PPM_SSHOTR = 0x260F0113ull;
+
+static const uint64_t P9N2_C_7_PPM_SSHOTR = 0x270F0113ull;
+
+static const uint64_t P9N2_C_8_PPM_SSHOTR = 0x280F0113ull;
+
+static const uint64_t P9N2_C_9_PPM_SSHOTR = 0x290F0113ull;
+
+static const uint64_t P9N2_C_10_PPM_SSHOTR = 0x2A0F0113ull;
+
+static const uint64_t P9N2_C_11_PPM_SSHOTR = 0x2B0F0113ull;
+
+static const uint64_t P9N2_C_12_PPM_SSHOTR = 0x2C0F0113ull;
+
+static const uint64_t P9N2_C_13_PPM_SSHOTR = 0x2D0F0113ull;
+
+static const uint64_t P9N2_C_14_PPM_SSHOTR = 0x2E0F0113ull;
+
+static const uint64_t P9N2_C_15_PPM_SSHOTR = 0x2F0F0113ull;
+
+static const uint64_t P9N2_C_16_PPM_SSHOTR = 0x300F0113ull;
+
+static const uint64_t P9N2_C_17_PPM_SSHOTR = 0x310F0113ull;
+
+static const uint64_t P9N2_C_18_PPM_SSHOTR = 0x320F0113ull;
+
+static const uint64_t P9N2_C_19_PPM_SSHOTR = 0x330F0113ull;
+
+static const uint64_t P9N2_C_20_PPM_SSHOTR = 0x340F0113ull;
+
+static const uint64_t P9N2_C_21_PPM_SSHOTR = 0x350F0113ull;
+
+static const uint64_t P9N2_C_22_PPM_SSHOTR = 0x360F0113ull;
+
+static const uint64_t P9N2_C_23_PPM_SSHOTR = 0x370F0113ull;
+
+static const uint64_t P9N2_EQ_PPM_SSHOTR = 0x100F0113ull;
+
+static const uint64_t P9N2_EQ_0_PPM_SSHOTR = 0x100F0113ull;
+
+static const uint64_t P9N2_EQ_1_PPM_SSHOTR = 0x110F0113ull;
+
+static const uint64_t P9N2_EQ_2_PPM_SSHOTR = 0x120F0113ull;
+
+static const uint64_t P9N2_EQ_3_PPM_SSHOTR = 0x130F0113ull;
+
+static const uint64_t P9N2_EQ_4_PPM_SSHOTR = 0x140F0113ull;
+
+static const uint64_t P9N2_EQ_5_PPM_SSHOTR = 0x150F0113ull;
+
+static const uint64_t P9N2_EX_PPM_SSHOTR = 0x200F0113ull;
+//DUPS: 210F0113,
+static const uint64_t P9N2_EX_0_PPM_SSHOTR = 0x200F0113ull;
+//DUPS: 210F0113,
+static const uint64_t P9N2_EX_1_PPM_SSHOTR = 0x220F0113ull;
+//DUPS: 220F0113,
+static const uint64_t P9N2_EX_2_PPM_SSHOTR = 0x240F0113ull;
+//DUPS: 250F0113,
+static const uint64_t P9N2_EX_3_PPM_SSHOTR = 0x260F0113ull;
+//DUPS: 270F0113,
+static const uint64_t P9N2_EX_4_PPM_SSHOTR = 0x280F0113ull;
+//DUPS: 290F0113,
+static const uint64_t P9N2_EX_5_PPM_SSHOTR = 0x2A0F0113ull;
+//DUPS: 2B0F0113,
+static const uint64_t P9N2_EX_6_PPM_SSHOTR = 0x2C0F0113ull;
+//DUPS: 2D0F0113,
+static const uint64_t P9N2_EX_7_PPM_SSHOTR = 0x2E0F0113ull;
+//DUPS: 2F0F0113,
+static const uint64_t P9N2_EX_8_PPM_SSHOTR = 0x300F0113ull;
+//DUPS: 310F0113,
+static const uint64_t P9N2_EX_9_PPM_SSHOTR = 0x320F0113ull;
+//DUPS: 330F0113,
+static const uint64_t P9N2_EX_10_PPM_SSHOTR = 0x340F0113ull;
+//DUPS: 350F0113,
+static const uint64_t P9N2_EX_11_PPM_SSHOTR = 0x360F0113ull;
+//DUPS: 370F0113,
+
+static const uint64_t P9N2_C_PPM_SSHSRC = 0x200F0110ull;
+
+static const uint64_t P9N2_C_0_PPM_SSHSRC = 0x200F0110ull;
+
+static const uint64_t P9N2_C_1_PPM_SSHSRC = 0x210F0110ull;
+
+static const uint64_t P9N2_C_2_PPM_SSHSRC = 0x220F0110ull;
+
+static const uint64_t P9N2_C_3_PPM_SSHSRC = 0x230F0110ull;
+
+static const uint64_t P9N2_C_4_PPM_SSHSRC = 0x240F0110ull;
+
+static const uint64_t P9N2_C_5_PPM_SSHSRC = 0x250F0110ull;
+
+static const uint64_t P9N2_C_6_PPM_SSHSRC = 0x260F0110ull;
+
+static const uint64_t P9N2_C_7_PPM_SSHSRC = 0x270F0110ull;
+
+static const uint64_t P9N2_C_8_PPM_SSHSRC = 0x280F0110ull;
+
+static const uint64_t P9N2_C_9_PPM_SSHSRC = 0x290F0110ull;
+
+static const uint64_t P9N2_C_10_PPM_SSHSRC = 0x2A0F0110ull;
+
+static const uint64_t P9N2_C_11_PPM_SSHSRC = 0x2B0F0110ull;
+
+static const uint64_t P9N2_C_12_PPM_SSHSRC = 0x2C0F0110ull;
+
+static const uint64_t P9N2_C_13_PPM_SSHSRC = 0x2D0F0110ull;
+
+static const uint64_t P9N2_C_14_PPM_SSHSRC = 0x2E0F0110ull;
+
+static const uint64_t P9N2_C_15_PPM_SSHSRC = 0x2F0F0110ull;
+
+static const uint64_t P9N2_C_16_PPM_SSHSRC = 0x300F0110ull;
+
+static const uint64_t P9N2_C_17_PPM_SSHSRC = 0x310F0110ull;
+
+static const uint64_t P9N2_C_18_PPM_SSHSRC = 0x320F0110ull;
+
+static const uint64_t P9N2_C_19_PPM_SSHSRC = 0x330F0110ull;
+
+static const uint64_t P9N2_C_20_PPM_SSHSRC = 0x340F0110ull;
+
+static const uint64_t P9N2_C_21_PPM_SSHSRC = 0x350F0110ull;
+
+static const uint64_t P9N2_C_22_PPM_SSHSRC = 0x360F0110ull;
+
+static const uint64_t P9N2_C_23_PPM_SSHSRC = 0x370F0110ull;
+
+static const uint64_t P9N2_EQ_PPM_SSHSRC = 0x100F0110ull;
+
+static const uint64_t P9N2_EQ_0_PPM_SSHSRC = 0x100F0110ull;
+
+static const uint64_t P9N2_EQ_1_PPM_SSHSRC = 0x110F0110ull;
+
+static const uint64_t P9N2_EQ_2_PPM_SSHSRC = 0x120F0110ull;
+
+static const uint64_t P9N2_EQ_3_PPM_SSHSRC = 0x130F0110ull;
+
+static const uint64_t P9N2_EQ_4_PPM_SSHSRC = 0x140F0110ull;
+
+static const uint64_t P9N2_EQ_5_PPM_SSHSRC = 0x150F0110ull;
+
+static const uint64_t P9N2_EX_PPM_SSHSRC = 0x200F0110ull;
+//DUPS: 210F0110,
+static const uint64_t P9N2_EX_0_PPM_SSHSRC = 0x200F0110ull;
+//DUPS: 210F0110,
+static const uint64_t P9N2_EX_1_PPM_SSHSRC = 0x220F0110ull;
+//DUPS: 220F0110,
+static const uint64_t P9N2_EX_2_PPM_SSHSRC = 0x240F0110ull;
+//DUPS: 250F0110,
+static const uint64_t P9N2_EX_3_PPM_SSHSRC = 0x260F0110ull;
+//DUPS: 270F0110,
+static const uint64_t P9N2_EX_4_PPM_SSHSRC = 0x280F0110ull;
+//DUPS: 290F0110,
+static const uint64_t P9N2_EX_5_PPM_SSHSRC = 0x2A0F0110ull;
+//DUPS: 2B0F0110,
+static const uint64_t P9N2_EX_6_PPM_SSHSRC = 0x2C0F0110ull;
+//DUPS: 2D0F0110,
+static const uint64_t P9N2_EX_7_PPM_SSHSRC = 0x2E0F0110ull;
+//DUPS: 2F0F0110,
+static const uint64_t P9N2_EX_8_PPM_SSHSRC = 0x300F0110ull;
+//DUPS: 310F0110,
+static const uint64_t P9N2_EX_9_PPM_SSHSRC = 0x320F0110ull;
+//DUPS: 330F0110,
+static const uint64_t P9N2_EX_10_PPM_SSHSRC = 0x340F0110ull;
+//DUPS: 350F0110,
+static const uint64_t P9N2_EX_11_PPM_SSHSRC = 0x360F0110ull;
+//DUPS: 370F0110,
+
+static const uint64_t P9N2_C_PPM_VDMCR = 0x200F01B8ull;
+
+static const uint64_t P9N2_C_PPM_VDMCR_CLEAR = 0x200F01B9ull;
+
+static const uint64_t P9N2_C_PPM_VDMCR_OR = 0x200F01BAull;
+
+static const uint64_t P9N2_C_0_PPM_VDMCR = 0x200F01B8ull;
+
+static const uint64_t P9N2_C_0_PPM_VDMCR_CLEAR = 0x200F01B9ull;
+
+static const uint64_t P9N2_C_0_PPM_VDMCR_OR = 0x200F01BAull;
+
+static const uint64_t P9N2_C_1_PPM_VDMCR = 0x210F01B8ull;
+
+static const uint64_t P9N2_C_1_PPM_VDMCR_CLEAR = 0x210F01B9ull;
+
+static const uint64_t P9N2_C_1_PPM_VDMCR_OR = 0x210F01BAull;
+
+static const uint64_t P9N2_C_2_PPM_VDMCR = 0x220F01B8ull;
+
+static const uint64_t P9N2_C_2_PPM_VDMCR_CLEAR = 0x220F01B9ull;
+
+static const uint64_t P9N2_C_2_PPM_VDMCR_OR = 0x220F01BAull;
+
+static const uint64_t P9N2_C_3_PPM_VDMCR = 0x230F01B8ull;
+
+static const uint64_t P9N2_C_3_PPM_VDMCR_CLEAR = 0x230F01B9ull;
+
+static const uint64_t P9N2_C_3_PPM_VDMCR_OR = 0x230F01BAull;
+
+static const uint64_t P9N2_C_4_PPM_VDMCR = 0x240F01B8ull;
+
+static const uint64_t P9N2_C_4_PPM_VDMCR_CLEAR = 0x240F01B9ull;
+
+static const uint64_t P9N2_C_4_PPM_VDMCR_OR = 0x240F01BAull;
+
+static const uint64_t P9N2_C_5_PPM_VDMCR = 0x250F01B8ull;
+
+static const uint64_t P9N2_C_5_PPM_VDMCR_CLEAR = 0x250F01B9ull;
+
+static const uint64_t P9N2_C_5_PPM_VDMCR_OR = 0x250F01BAull;
+
+static const uint64_t P9N2_C_6_PPM_VDMCR = 0x260F01B8ull;
+
+static const uint64_t P9N2_C_6_PPM_VDMCR_CLEAR = 0x260F01B9ull;
+
+static const uint64_t P9N2_C_6_PPM_VDMCR_OR = 0x260F01BAull;
+
+static const uint64_t P9N2_C_7_PPM_VDMCR = 0x270F01B8ull;
+
+static const uint64_t P9N2_C_7_PPM_VDMCR_CLEAR = 0x270F01B9ull;
+
+static const uint64_t P9N2_C_7_PPM_VDMCR_OR = 0x270F01BAull;
+
+static const uint64_t P9N2_C_8_PPM_VDMCR = 0x280F01B8ull;
+
+static const uint64_t P9N2_C_8_PPM_VDMCR_CLEAR = 0x280F01B9ull;
+
+static const uint64_t P9N2_C_8_PPM_VDMCR_OR = 0x280F01BAull;
+
+static const uint64_t P9N2_C_9_PPM_VDMCR = 0x290F01B8ull;
+
+static const uint64_t P9N2_C_9_PPM_VDMCR_CLEAR = 0x290F01B9ull;
+
+static const uint64_t P9N2_C_9_PPM_VDMCR_OR = 0x290F01BAull;
+
+static const uint64_t P9N2_C_10_PPM_VDMCR = 0x2A0F01B8ull;
+
+static const uint64_t P9N2_C_10_PPM_VDMCR_CLEAR = 0x2A0F01B9ull;
+
+static const uint64_t P9N2_C_10_PPM_VDMCR_OR = 0x2A0F01BAull;
+
+static const uint64_t P9N2_C_11_PPM_VDMCR = 0x2B0F01B8ull;
+
+static const uint64_t P9N2_C_11_PPM_VDMCR_CLEAR = 0x2B0F01B9ull;
+
+static const uint64_t P9N2_C_11_PPM_VDMCR_OR = 0x2B0F01BAull;
+
+static const uint64_t P9N2_C_12_PPM_VDMCR = 0x2C0F01B8ull;
+
+static const uint64_t P9N2_C_12_PPM_VDMCR_CLEAR = 0x2C0F01B9ull;
+
+static const uint64_t P9N2_C_12_PPM_VDMCR_OR = 0x2C0F01BAull;
+
+static const uint64_t P9N2_C_13_PPM_VDMCR = 0x2D0F01B8ull;
+
+static const uint64_t P9N2_C_13_PPM_VDMCR_CLEAR = 0x2D0F01B9ull;
+
+static const uint64_t P9N2_C_13_PPM_VDMCR_OR = 0x2D0F01BAull;
+
+static const uint64_t P9N2_C_14_PPM_VDMCR = 0x2E0F01B8ull;
+
+static const uint64_t P9N2_C_14_PPM_VDMCR_CLEAR = 0x2E0F01B9ull;
+
+static const uint64_t P9N2_C_14_PPM_VDMCR_OR = 0x2E0F01BAull;
+
+static const uint64_t P9N2_C_15_PPM_VDMCR = 0x2F0F01B8ull;
+
+static const uint64_t P9N2_C_15_PPM_VDMCR_CLEAR = 0x2F0F01B9ull;
+
+static const uint64_t P9N2_C_15_PPM_VDMCR_OR = 0x2F0F01BAull;
+
+static const uint64_t P9N2_C_16_PPM_VDMCR = 0x300F01B8ull;
+
+static const uint64_t P9N2_C_16_PPM_VDMCR_CLEAR = 0x300F01B9ull;
+
+static const uint64_t P9N2_C_16_PPM_VDMCR_OR = 0x300F01BAull;
+
+static const uint64_t P9N2_C_17_PPM_VDMCR = 0x310F01B8ull;
+
+static const uint64_t P9N2_C_17_PPM_VDMCR_CLEAR = 0x310F01B9ull;
+
+static const uint64_t P9N2_C_17_PPM_VDMCR_OR = 0x310F01BAull;
+
+static const uint64_t P9N2_C_18_PPM_VDMCR = 0x320F01B8ull;
+
+static const uint64_t P9N2_C_18_PPM_VDMCR_CLEAR = 0x320F01B9ull;
+
+static const uint64_t P9N2_C_18_PPM_VDMCR_OR = 0x320F01BAull;
+
+static const uint64_t P9N2_C_19_PPM_VDMCR = 0x330F01B8ull;
+
+static const uint64_t P9N2_C_19_PPM_VDMCR_CLEAR = 0x330F01B9ull;
+
+static const uint64_t P9N2_C_19_PPM_VDMCR_OR = 0x330F01BAull;
+
+static const uint64_t P9N2_C_20_PPM_VDMCR = 0x340F01B8ull;
+
+static const uint64_t P9N2_C_20_PPM_VDMCR_CLEAR = 0x340F01B9ull;
+
+static const uint64_t P9N2_C_20_PPM_VDMCR_OR = 0x340F01BAull;
+
+static const uint64_t P9N2_C_21_PPM_VDMCR = 0x350F01B8ull;
+
+static const uint64_t P9N2_C_21_PPM_VDMCR_CLEAR = 0x350F01B9ull;
+
+static const uint64_t P9N2_C_21_PPM_VDMCR_OR = 0x350F01BAull;
+
+static const uint64_t P9N2_C_22_PPM_VDMCR = 0x360F01B8ull;
+
+static const uint64_t P9N2_C_22_PPM_VDMCR_CLEAR = 0x360F01B9ull;
+
+static const uint64_t P9N2_C_22_PPM_VDMCR_OR = 0x360F01BAull;
+
+static const uint64_t P9N2_C_23_PPM_VDMCR = 0x370F01B8ull;
+
+static const uint64_t P9N2_C_23_PPM_VDMCR_CLEAR = 0x370F01B9ull;
+
+static const uint64_t P9N2_C_23_PPM_VDMCR_OR = 0x370F01BAull;
+
+static const uint64_t P9N2_EQ_PPM_VDMCR = 0x100F01B8ull;
+
+static const uint64_t P9N2_EQ_PPM_VDMCR_CLEAR = 0x100F01B9ull;
+
+static const uint64_t P9N2_EQ_PPM_VDMCR_OR = 0x100F01BAull;
+
+static const uint64_t P9N2_EQ_0_PPM_VDMCR = 0x100F01B8ull;
+
+static const uint64_t P9N2_EQ_0_PPM_VDMCR_CLEAR = 0x100F01B9ull;
+
+static const uint64_t P9N2_EQ_0_PPM_VDMCR_OR = 0x100F01BAull;
+
+static const uint64_t P9N2_EQ_1_PPM_VDMCR = 0x110F01B8ull;
+
+static const uint64_t P9N2_EQ_1_PPM_VDMCR_CLEAR = 0x110F01B9ull;
+
+static const uint64_t P9N2_EQ_1_PPM_VDMCR_OR = 0x110F01BAull;
+
+static const uint64_t P9N2_EQ_2_PPM_VDMCR = 0x120F01B8ull;
+
+static const uint64_t P9N2_EQ_2_PPM_VDMCR_CLEAR = 0x120F01B9ull;
+
+static const uint64_t P9N2_EQ_2_PPM_VDMCR_OR = 0x120F01BAull;
+
+static const uint64_t P9N2_EQ_3_PPM_VDMCR = 0x130F01B8ull;
+
+static const uint64_t P9N2_EQ_3_PPM_VDMCR_CLEAR = 0x130F01B9ull;
+
+static const uint64_t P9N2_EQ_3_PPM_VDMCR_OR = 0x130F01BAull;
+
+static const uint64_t P9N2_EQ_4_PPM_VDMCR = 0x140F01B8ull;
+
+static const uint64_t P9N2_EQ_4_PPM_VDMCR_CLEAR = 0x140F01B9ull;
+
+static const uint64_t P9N2_EQ_4_PPM_VDMCR_OR = 0x140F01BAull;
+
+static const uint64_t P9N2_EQ_5_PPM_VDMCR = 0x150F01B8ull;
+
+static const uint64_t P9N2_EQ_5_PPM_VDMCR_CLEAR = 0x150F01B9ull;
+
+static const uint64_t P9N2_EQ_5_PPM_VDMCR_OR = 0x150F01BAull;
+
+static const uint64_t P9N2_EX_PPM_VDMCR = 0x200F01B8ull;
+//DUPS: 210F01B8,
+static const uint64_t P9N2_EX_PPM_VDMCR_CLEAR = 0x200F01B9ull;
+//DUPS: 210F01B9,
+static const uint64_t P9N2_EX_PPM_VDMCR_OR = 0x200F01BAull;
+//DUPS: 210F01BA,
+static const uint64_t P9N2_EX_0_PPM_VDMCR = 0x200F01B8ull;
+//DUPS: 210F01B8,
+static const uint64_t P9N2_EX_0_PPM_VDMCR_CLEAR = 0x200F01B9ull;
+//DUPS: 210F01B9,
+static const uint64_t P9N2_EX_0_PPM_VDMCR_OR = 0x200F01BAull;
+//DUPS: 210F01BA,
+static const uint64_t P9N2_EX_1_PPM_VDMCR = 0x220F01B8ull;
+//DUPS: 220F01B8,
+static const uint64_t P9N2_EX_1_PPM_VDMCR_CLEAR = 0x220F01B9ull;
+//DUPS: 220F01B9,
+static const uint64_t P9N2_EX_1_PPM_VDMCR_OR = 0x220F01BAull;
+//DUPS: 220F01BA,
+static const uint64_t P9N2_EX_2_PPM_VDMCR = 0x240F01B8ull;
+//DUPS: 250F01B8,
+static const uint64_t P9N2_EX_2_PPM_VDMCR_CLEAR = 0x240F01B9ull;
+//DUPS: 250F01B9,
+static const uint64_t P9N2_EX_2_PPM_VDMCR_OR = 0x240F01BAull;
+//DUPS: 250F01BA,
+static const uint64_t P9N2_EX_3_PPM_VDMCR = 0x260F01B8ull;
+//DUPS: 270F01B8,
+static const uint64_t P9N2_EX_3_PPM_VDMCR_CLEAR = 0x260F01B9ull;
+//DUPS: 270F01B9,
+static const uint64_t P9N2_EX_3_PPM_VDMCR_OR = 0x260F01BAull;
+//DUPS: 270F01BA,
+static const uint64_t P9N2_EX_4_PPM_VDMCR = 0x280F01B8ull;
+//DUPS: 290F01B8,
+static const uint64_t P9N2_EX_4_PPM_VDMCR_CLEAR = 0x280F01B9ull;
+//DUPS: 290F01B9,
+static const uint64_t P9N2_EX_4_PPM_VDMCR_OR = 0x280F01BAull;
+//DUPS: 290F01BA,
+static const uint64_t P9N2_EX_5_PPM_VDMCR = 0x2A0F01B8ull;
+//DUPS: 2B0F01B8,
+static const uint64_t P9N2_EX_5_PPM_VDMCR_CLEAR = 0x2A0F01B9ull;
+//DUPS: 2B0F01B9,
+static const uint64_t P9N2_EX_5_PPM_VDMCR_OR = 0x2A0F01BAull;
+//DUPS: 2B0F01BA,
+static const uint64_t P9N2_EX_6_PPM_VDMCR = 0x2C0F01B8ull;
+//DUPS: 2D0F01B8,
+static const uint64_t P9N2_EX_6_PPM_VDMCR_CLEAR = 0x2C0F01B9ull;
+//DUPS: 2D0F01B9,
+static const uint64_t P9N2_EX_6_PPM_VDMCR_OR = 0x2C0F01BAull;
+//DUPS: 2D0F01BA,
+static const uint64_t P9N2_EX_7_PPM_VDMCR = 0x2E0F01B8ull;
+//DUPS: 2F0F01B8,
+static const uint64_t P9N2_EX_7_PPM_VDMCR_CLEAR = 0x2E0F01B9ull;
+//DUPS: 2F0F01B9,
+static const uint64_t P9N2_EX_7_PPM_VDMCR_OR = 0x2E0F01BAull;
+//DUPS: 2F0F01BA,
+static const uint64_t P9N2_EX_8_PPM_VDMCR = 0x300F01B8ull;
+//DUPS: 310F01B8,
+static const uint64_t P9N2_EX_8_PPM_VDMCR_CLEAR = 0x300F01B9ull;
+//DUPS: 310F01B9,
+static const uint64_t P9N2_EX_8_PPM_VDMCR_OR = 0x300F01BAull;
+//DUPS: 310F01BA,
+static const uint64_t P9N2_EX_9_PPM_VDMCR = 0x320F01B8ull;
+//DUPS: 330F01B8,
+static const uint64_t P9N2_EX_9_PPM_VDMCR_CLEAR = 0x320F01B9ull;
+//DUPS: 330F01B9,
+static const uint64_t P9N2_EX_9_PPM_VDMCR_OR = 0x320F01BAull;
+//DUPS: 330F01BA,
+static const uint64_t P9N2_EX_10_PPM_VDMCR = 0x340F01B8ull;
+//DUPS: 350F01B8,
+static const uint64_t P9N2_EX_10_PPM_VDMCR_CLEAR = 0x340F01B9ull;
+//DUPS: 350F01B9,
+static const uint64_t P9N2_EX_10_PPM_VDMCR_OR = 0x340F01BAull;
+//DUPS: 350F01BA,
+static const uint64_t P9N2_EX_11_PPM_VDMCR = 0x360F01B8ull;
+//DUPS: 370F01B8,
+static const uint64_t P9N2_EX_11_PPM_VDMCR_CLEAR = 0x360F01B9ull;
+//DUPS: 370F01B9,
+static const uint64_t P9N2_EX_11_PPM_VDMCR_OR = 0x360F01BAull;
+//DUPS: 370F01BA,
+
+static const uint64_t P9N2_EQ_PRD_PURGE_CMD_REG = 0x10010C0Eull;
+//DUPS: 10010C0E,
+static const uint64_t P9N2_EQ_0_PRD_PURGE_CMD_REG = 0x10010C0Eull;
+//DUPS: 10010C0E,
+static const uint64_t P9N2_EQ_1_PRD_PURGE_CMD_REG = 0x11010C0Eull;
+//DUPS: 11010C0E,
+static const uint64_t P9N2_EQ_2_PRD_PURGE_CMD_REG = 0x12010C0Eull;
+//DUPS: 12010C0E,
+static const uint64_t P9N2_EQ_3_PRD_PURGE_CMD_REG = 0x13010C0Eull;
+//DUPS: 13010C0E,
+static const uint64_t P9N2_EQ_4_PRD_PURGE_CMD_REG = 0x14010C0Eull;
+//DUPS: 14010C0E,
+static const uint64_t P9N2_EQ_5_PRD_PURGE_CMD_REG = 0x15010C0Eull;
+//DUPS: 15010C0E,
+static const uint64_t P9N2_EX_PRD_PURGE_CMD_REG = 0x1001080Eull;
+
+static const uint64_t P9N2_EX_0_PRD_PURGE_CMD_REG = 0x1001080Eull;
+
+static const uint64_t P9N2_EX_1_PRD_PURGE_CMD_REG = 0x10010C0Eull;
+
+static const uint64_t P9N2_EX_2_PRD_PURGE_CMD_REG = 0x1101080Eull;
+
+static const uint64_t P9N2_EX_3_PRD_PURGE_CMD_REG = 0x11010C0Eull;
+
+static const uint64_t P9N2_EX_4_PRD_PURGE_CMD_REG = 0x1201080Eull;
+
+static const uint64_t P9N2_EX_5_PRD_PURGE_CMD_REG = 0x12010C0Eull;
+
+static const uint64_t P9N2_EX_6_PRD_PURGE_CMD_REG = 0x1301080Eull;
+
+static const uint64_t P9N2_EX_7_PRD_PURGE_CMD_REG = 0x13010C0Eull;
+
+static const uint64_t P9N2_EX_8_PRD_PURGE_CMD_REG = 0x1401080Eull;
+
+static const uint64_t P9N2_EX_9_PRD_PURGE_CMD_REG = 0x14010C0Eull;
+
+static const uint64_t P9N2_EX_10_PRD_PURGE_CMD_REG = 0x1501080Eull;
+
+static const uint64_t P9N2_EX_11_PRD_PURGE_CMD_REG = 0x15010C0Eull;
+
+
+static const uint64_t P9N2_EQ_PRD_PURGE_REG = 0x10011C0Eull;
+//DUPS: 10011C0E,
+static const uint64_t P9N2_EQ_0_PRD_PURGE_REG = 0x10011C0Eull;
+//DUPS: 10011C0E,
+static const uint64_t P9N2_EQ_1_PRD_PURGE_REG = 0x11011C0Eull;
+//DUPS: 11011C0E,
+static const uint64_t P9N2_EQ_2_PRD_PURGE_REG = 0x12011C0Eull;
+//DUPS: 12011C0E,
+static const uint64_t P9N2_EQ_3_PRD_PURGE_REG = 0x13011C0Eull;
+//DUPS: 13011C0E,
+static const uint64_t P9N2_EQ_4_PRD_PURGE_REG = 0x14011C0Eull;
+//DUPS: 14011C0E,
+static const uint64_t P9N2_EQ_5_PRD_PURGE_REG = 0x15011C0Eull;
+//DUPS: 15011C0E,
+static const uint64_t P9N2_EX_PRD_PURGE_REG = 0x1001180Eull;
+
+static const uint64_t P9N2_EX_0_PRD_PURGE_REG = 0x1001180Eull;
+
+static const uint64_t P9N2_EX_1_PRD_PURGE_REG = 0x10011C0Eull;
+
+static const uint64_t P9N2_EX_2_PRD_PURGE_REG = 0x1101180Eull;
+
+static const uint64_t P9N2_EX_3_PRD_PURGE_REG = 0x11011C0Eull;
+
+static const uint64_t P9N2_EX_4_PRD_PURGE_REG = 0x1201180Eull;
+
+static const uint64_t P9N2_EX_5_PRD_PURGE_REG = 0x12011C0Eull;
+
+static const uint64_t P9N2_EX_6_PRD_PURGE_REG = 0x1301180Eull;
+
+static const uint64_t P9N2_EX_7_PRD_PURGE_REG = 0x13011C0Eull;
+
+static const uint64_t P9N2_EX_8_PRD_PURGE_REG = 0x1401180Eull;
+
+static const uint64_t P9N2_EX_9_PRD_PURGE_REG = 0x14011C0Eull;
+
+static const uint64_t P9N2_EX_10_PRD_PURGE_REG = 0x1501180Eull;
+
+static const uint64_t P9N2_EX_11_PRD_PURGE_REG = 0x15011C0Eull;
+
+
+static const uint64_t P9N2_C_PRE_COUNTER_REG = 0x200F0028ull;
+
+static const uint64_t P9N2_C_0_PRE_COUNTER_REG = 0x200F0028ull;
+
+static const uint64_t P9N2_C_1_PRE_COUNTER_REG = 0x210F0028ull;
+
+static const uint64_t P9N2_C_2_PRE_COUNTER_REG = 0x220F0028ull;
+
+static const uint64_t P9N2_C_3_PRE_COUNTER_REG = 0x230F0028ull;
+
+static const uint64_t P9N2_C_4_PRE_COUNTER_REG = 0x240F0028ull;
+
+static const uint64_t P9N2_C_5_PRE_COUNTER_REG = 0x250F0028ull;
+
+static const uint64_t P9N2_C_6_PRE_COUNTER_REG = 0x260F0028ull;
+
+static const uint64_t P9N2_C_7_PRE_COUNTER_REG = 0x270F0028ull;
+
+static const uint64_t P9N2_C_8_PRE_COUNTER_REG = 0x280F0028ull;
+
+static const uint64_t P9N2_C_9_PRE_COUNTER_REG = 0x290F0028ull;
+
+static const uint64_t P9N2_C_10_PRE_COUNTER_REG = 0x2A0F0028ull;
+
+static const uint64_t P9N2_C_11_PRE_COUNTER_REG = 0x2B0F0028ull;
+
+static const uint64_t P9N2_C_12_PRE_COUNTER_REG = 0x2C0F0028ull;
+
+static const uint64_t P9N2_C_13_PRE_COUNTER_REG = 0x2D0F0028ull;
+
+static const uint64_t P9N2_C_14_PRE_COUNTER_REG = 0x2E0F0028ull;
+
+static const uint64_t P9N2_C_15_PRE_COUNTER_REG = 0x2F0F0028ull;
+
+static const uint64_t P9N2_C_16_PRE_COUNTER_REG = 0x300F0028ull;
+
+static const uint64_t P9N2_C_17_PRE_COUNTER_REG = 0x310F0028ull;
+
+static const uint64_t P9N2_C_18_PRE_COUNTER_REG = 0x320F0028ull;
+
+static const uint64_t P9N2_C_19_PRE_COUNTER_REG = 0x330F0028ull;
+
+static const uint64_t P9N2_C_20_PRE_COUNTER_REG = 0x340F0028ull;
+
+static const uint64_t P9N2_C_21_PRE_COUNTER_REG = 0x350F0028ull;
+
+static const uint64_t P9N2_C_22_PRE_COUNTER_REG = 0x360F0028ull;
+
+static const uint64_t P9N2_C_23_PRE_COUNTER_REG = 0x370F0028ull;
+
+static const uint64_t P9N2_EQ_PRE_COUNTER_REG = 0x100F0028ull;
+
+static const uint64_t P9N2_EQ_0_PRE_COUNTER_REG = 0x100F0028ull;
+
+static const uint64_t P9N2_EQ_1_PRE_COUNTER_REG = 0x110F0028ull;
+
+static const uint64_t P9N2_EQ_2_PRE_COUNTER_REG = 0x120F0028ull;
+
+static const uint64_t P9N2_EQ_3_PRE_COUNTER_REG = 0x130F0028ull;
+
+static const uint64_t P9N2_EQ_4_PRE_COUNTER_REG = 0x140F0028ull;
+
+static const uint64_t P9N2_EQ_5_PRE_COUNTER_REG = 0x150F0028ull;
+
+static const uint64_t P9N2_EX_PRE_COUNTER_REG = 0x200F0028ull;
+//DUPS: 210F0028,
+static const uint64_t P9N2_EX_0_PRE_COUNTER_REG = 0x200F0028ull;
+//DUPS: 210F0028,
+static const uint64_t P9N2_EX_1_PRE_COUNTER_REG = 0x220F0028ull;
+//DUPS: 220F0028,
+static const uint64_t P9N2_EX_2_PRE_COUNTER_REG = 0x240F0028ull;
+//DUPS: 250F0028,
+static const uint64_t P9N2_EX_3_PRE_COUNTER_REG = 0x260F0028ull;
+//DUPS: 270F0028,
+static const uint64_t P9N2_EX_4_PRE_COUNTER_REG = 0x280F0028ull;
+//DUPS: 290F0028,
+static const uint64_t P9N2_EX_5_PRE_COUNTER_REG = 0x2A0F0028ull;
+//DUPS: 2B0F0028,
+static const uint64_t P9N2_EX_6_PRE_COUNTER_REG = 0x2C0F0028ull;
+//DUPS: 2D0F0028,
+static const uint64_t P9N2_EX_7_PRE_COUNTER_REG = 0x2E0F0028ull;
+//DUPS: 2F0F0028,
+static const uint64_t P9N2_EX_8_PRE_COUNTER_REG = 0x300F0028ull;
+//DUPS: 310F0028,
+static const uint64_t P9N2_EX_9_PRE_COUNTER_REG = 0x320F0028ull;
+//DUPS: 330F0028,
+static const uint64_t P9N2_EX_10_PRE_COUNTER_REG = 0x340F0028ull;
+//DUPS: 350F0028,
+static const uint64_t P9N2_EX_11_PRE_COUNTER_REG = 0x360F0028ull;
+//DUPS: 370F0028,
+
+static const uint64_t P9N2_C_PRIMARY_ADDRESS_REG = 0x200F0000ull;
+
+static const uint64_t P9N2_C_0_PRIMARY_ADDRESS_REG = 0x200F0000ull;
+
+static const uint64_t P9N2_C_1_PRIMARY_ADDRESS_REG = 0x210F0000ull;
+
+static const uint64_t P9N2_C_2_PRIMARY_ADDRESS_REG = 0x220F0000ull;
+
+static const uint64_t P9N2_C_3_PRIMARY_ADDRESS_REG = 0x230F0000ull;
+
+static const uint64_t P9N2_C_4_PRIMARY_ADDRESS_REG = 0x240F0000ull;
+
+static const uint64_t P9N2_C_5_PRIMARY_ADDRESS_REG = 0x250F0000ull;
+
+static const uint64_t P9N2_C_6_PRIMARY_ADDRESS_REG = 0x260F0000ull;
+
+static const uint64_t P9N2_C_7_PRIMARY_ADDRESS_REG = 0x270F0000ull;
+
+static const uint64_t P9N2_C_8_PRIMARY_ADDRESS_REG = 0x280F0000ull;
+
+static const uint64_t P9N2_C_9_PRIMARY_ADDRESS_REG = 0x290F0000ull;
+
+static const uint64_t P9N2_C_10_PRIMARY_ADDRESS_REG = 0x2A0F0000ull;
+
+static const uint64_t P9N2_C_11_PRIMARY_ADDRESS_REG = 0x2B0F0000ull;
+
+static const uint64_t P9N2_C_12_PRIMARY_ADDRESS_REG = 0x2C0F0000ull;
+
+static const uint64_t P9N2_C_13_PRIMARY_ADDRESS_REG = 0x2D0F0000ull;
+
+static const uint64_t P9N2_C_14_PRIMARY_ADDRESS_REG = 0x2E0F0000ull;
+
+static const uint64_t P9N2_C_15_PRIMARY_ADDRESS_REG = 0x2F0F0000ull;
+
+static const uint64_t P9N2_C_16_PRIMARY_ADDRESS_REG = 0x300F0000ull;
+
+static const uint64_t P9N2_C_17_PRIMARY_ADDRESS_REG = 0x310F0000ull;
+
+static const uint64_t P9N2_C_18_PRIMARY_ADDRESS_REG = 0x320F0000ull;
+
+static const uint64_t P9N2_C_19_PRIMARY_ADDRESS_REG = 0x330F0000ull;
+
+static const uint64_t P9N2_C_20_PRIMARY_ADDRESS_REG = 0x340F0000ull;
+
+static const uint64_t P9N2_C_21_PRIMARY_ADDRESS_REG = 0x350F0000ull;
+
+static const uint64_t P9N2_C_22_PRIMARY_ADDRESS_REG = 0x360F0000ull;
+
+static const uint64_t P9N2_C_23_PRIMARY_ADDRESS_REG = 0x370F0000ull;
+
+static const uint64_t P9N2_EQ_PRIMARY_ADDRESS_REG = 0x100F0000ull;
+
+static const uint64_t P9N2_EQ_0_PRIMARY_ADDRESS_REG = 0x100F0000ull;
+
+static const uint64_t P9N2_EQ_1_PRIMARY_ADDRESS_REG = 0x110F0000ull;
+
+static const uint64_t P9N2_EQ_2_PRIMARY_ADDRESS_REG = 0x120F0000ull;
+
+static const uint64_t P9N2_EQ_3_PRIMARY_ADDRESS_REG = 0x130F0000ull;
+
+static const uint64_t P9N2_EQ_4_PRIMARY_ADDRESS_REG = 0x140F0000ull;
+
+static const uint64_t P9N2_EQ_5_PRIMARY_ADDRESS_REG = 0x150F0000ull;
+
+static const uint64_t P9N2_EX_PRIMARY_ADDRESS_REG = 0x200F0000ull;
+//DUPS: 210F0000,
+static const uint64_t P9N2_EX_0_PRIMARY_ADDRESS_REG = 0x200F0000ull;
+//DUPS: 210F0000,
+static const uint64_t P9N2_EX_1_PRIMARY_ADDRESS_REG = 0x220F0000ull;
+//DUPS: 220F0000,
+static const uint64_t P9N2_EX_2_PRIMARY_ADDRESS_REG = 0x240F0000ull;
+//DUPS: 250F0000,
+static const uint64_t P9N2_EX_3_PRIMARY_ADDRESS_REG = 0x260F0000ull;
+//DUPS: 270F0000,
+static const uint64_t P9N2_EX_4_PRIMARY_ADDRESS_REG = 0x280F0000ull;
+//DUPS: 290F0000,
+static const uint64_t P9N2_EX_5_PRIMARY_ADDRESS_REG = 0x2A0F0000ull;
+//DUPS: 2B0F0000,
+static const uint64_t P9N2_EX_6_PRIMARY_ADDRESS_REG = 0x2C0F0000ull;
+//DUPS: 2D0F0000,
+static const uint64_t P9N2_EX_7_PRIMARY_ADDRESS_REG = 0x2E0F0000ull;
+//DUPS: 2F0F0000,
+static const uint64_t P9N2_EX_8_PRIMARY_ADDRESS_REG = 0x300F0000ull;
+//DUPS: 310F0000,
+static const uint64_t P9N2_EX_9_PRIMARY_ADDRESS_REG = 0x320F0000ull;
+//DUPS: 330F0000,
+static const uint64_t P9N2_EX_10_PRIMARY_ADDRESS_REG = 0x340F0000ull;
+//DUPS: 350F0000,
+static const uint64_t P9N2_EX_11_PRIMARY_ADDRESS_REG = 0x360F0000ull;
+//DUPS: 370F0000,
+
+static const uint64_t P9N2_C_PROTECT_MODE_REG = 0x200F03FEull;
+
+static const uint64_t P9N2_C_0_PROTECT_MODE_REG = 0x200F03FEull;
+
+static const uint64_t P9N2_C_1_PROTECT_MODE_REG = 0x210F03FEull;
+
+static const uint64_t P9N2_C_2_PROTECT_MODE_REG = 0x220F03FEull;
+
+static const uint64_t P9N2_C_3_PROTECT_MODE_REG = 0x230F03FEull;
+
+static const uint64_t P9N2_C_4_PROTECT_MODE_REG = 0x240F03FEull;
+
+static const uint64_t P9N2_C_5_PROTECT_MODE_REG = 0x250F03FEull;
+
+static const uint64_t P9N2_C_6_PROTECT_MODE_REG = 0x260F03FEull;
+
+static const uint64_t P9N2_C_7_PROTECT_MODE_REG = 0x270F03FEull;
+
+static const uint64_t P9N2_C_8_PROTECT_MODE_REG = 0x280F03FEull;
+
+static const uint64_t P9N2_C_9_PROTECT_MODE_REG = 0x290F03FEull;
+
+static const uint64_t P9N2_C_10_PROTECT_MODE_REG = 0x2A0F03FEull;
+
+static const uint64_t P9N2_C_11_PROTECT_MODE_REG = 0x2B0F03FEull;
+
+static const uint64_t P9N2_C_12_PROTECT_MODE_REG = 0x2C0F03FEull;
+
+static const uint64_t P9N2_C_13_PROTECT_MODE_REG = 0x2D0F03FEull;
+
+static const uint64_t P9N2_C_14_PROTECT_MODE_REG = 0x2E0F03FEull;
+
+static const uint64_t P9N2_C_15_PROTECT_MODE_REG = 0x2F0F03FEull;
+
+static const uint64_t P9N2_C_16_PROTECT_MODE_REG = 0x300F03FEull;
+
+static const uint64_t P9N2_C_17_PROTECT_MODE_REG = 0x310F03FEull;
+
+static const uint64_t P9N2_C_18_PROTECT_MODE_REG = 0x320F03FEull;
+
+static const uint64_t P9N2_C_19_PROTECT_MODE_REG = 0x330F03FEull;
+
+static const uint64_t P9N2_C_20_PROTECT_MODE_REG = 0x340F03FEull;
+
+static const uint64_t P9N2_C_21_PROTECT_MODE_REG = 0x350F03FEull;
+
+static const uint64_t P9N2_C_22_PROTECT_MODE_REG = 0x360F03FEull;
+
+static const uint64_t P9N2_C_23_PROTECT_MODE_REG = 0x370F03FEull;
+
+static const uint64_t P9N2_EQ_PROTECT_MODE_REG = 0x100F03FEull;
+
+static const uint64_t P9N2_EQ_0_PROTECT_MODE_REG = 0x100F03FEull;
+
+static const uint64_t P9N2_EQ_1_PROTECT_MODE_REG = 0x110F03FEull;
+
+static const uint64_t P9N2_EQ_2_PROTECT_MODE_REG = 0x120F03FEull;
+
+static const uint64_t P9N2_EQ_3_PROTECT_MODE_REG = 0x130F03FEull;
+
+static const uint64_t P9N2_EQ_4_PROTECT_MODE_REG = 0x140F03FEull;
+
+static const uint64_t P9N2_EQ_5_PROTECT_MODE_REG = 0x150F03FEull;
+
+static const uint64_t P9N2_EX_PROTECT_MODE_REG = 0x200F03FEull;
+//DUPS: 210F03FE,
+static const uint64_t P9N2_EX_0_PROTECT_MODE_REG = 0x200F03FEull;
+//DUPS: 210F03FE,
+static const uint64_t P9N2_EX_1_PROTECT_MODE_REG = 0x220F03FEull;
+//DUPS: 220F03FE,
+static const uint64_t P9N2_EX_2_PROTECT_MODE_REG = 0x240F03FEull;
+//DUPS: 250F03FE,
+static const uint64_t P9N2_EX_3_PROTECT_MODE_REG = 0x260F03FEull;
+//DUPS: 270F03FE,
+static const uint64_t P9N2_EX_4_PROTECT_MODE_REG = 0x280F03FEull;
+//DUPS: 290F03FE,
+static const uint64_t P9N2_EX_5_PROTECT_MODE_REG = 0x2A0F03FEull;
+//DUPS: 2B0F03FE,
+static const uint64_t P9N2_EX_6_PROTECT_MODE_REG = 0x2C0F03FEull;
+//DUPS: 2D0F03FE,
+static const uint64_t P9N2_EX_7_PROTECT_MODE_REG = 0x2E0F03FEull;
+//DUPS: 2F0F03FE,
+static const uint64_t P9N2_EX_8_PROTECT_MODE_REG = 0x300F03FEull;
+//DUPS: 310F03FE,
+static const uint64_t P9N2_EX_9_PROTECT_MODE_REG = 0x320F03FEull;
+//DUPS: 330F03FE,
+static const uint64_t P9N2_EX_10_PROTECT_MODE_REG = 0x340F03FEull;
+//DUPS: 350F03FE,
+static const uint64_t P9N2_EX_11_PROTECT_MODE_REG = 0x360F03FEull;
+//DUPS: 370F03FE,
+
+static const uint64_t P9N2_C_PSCOM_ERROR_MASK = 0x20010002ull;
+
+static const uint64_t P9N2_C_0_PSCOM_ERROR_MASK = 0x20010002ull;
+
+static const uint64_t P9N2_C_1_PSCOM_ERROR_MASK = 0x21010002ull;
+
+static const uint64_t P9N2_C_2_PSCOM_ERROR_MASK = 0x22010002ull;
+
+static const uint64_t P9N2_C_3_PSCOM_ERROR_MASK = 0x23010002ull;
+
+static const uint64_t P9N2_C_4_PSCOM_ERROR_MASK = 0x24010002ull;
+
+static const uint64_t P9N2_C_5_PSCOM_ERROR_MASK = 0x25010002ull;
+
+static const uint64_t P9N2_C_6_PSCOM_ERROR_MASK = 0x26010002ull;
+
+static const uint64_t P9N2_C_7_PSCOM_ERROR_MASK = 0x27010002ull;
+
+static const uint64_t P9N2_C_8_PSCOM_ERROR_MASK = 0x28010002ull;
+
+static const uint64_t P9N2_C_9_PSCOM_ERROR_MASK = 0x29010002ull;
+
+static const uint64_t P9N2_C_10_PSCOM_ERROR_MASK = 0x2A010002ull;
+
+static const uint64_t P9N2_C_11_PSCOM_ERROR_MASK = 0x2B010002ull;
+
+static const uint64_t P9N2_C_12_PSCOM_ERROR_MASK = 0x2C010002ull;
+
+static const uint64_t P9N2_C_13_PSCOM_ERROR_MASK = 0x2D010002ull;
+
+static const uint64_t P9N2_C_14_PSCOM_ERROR_MASK = 0x2E010002ull;
+
+static const uint64_t P9N2_C_15_PSCOM_ERROR_MASK = 0x2F010002ull;
+
+static const uint64_t P9N2_C_16_PSCOM_ERROR_MASK = 0x30010002ull;
+
+static const uint64_t P9N2_C_17_PSCOM_ERROR_MASK = 0x31010002ull;
+
+static const uint64_t P9N2_C_18_PSCOM_ERROR_MASK = 0x32010002ull;
+
+static const uint64_t P9N2_C_19_PSCOM_ERROR_MASK = 0x33010002ull;
+
+static const uint64_t P9N2_C_20_PSCOM_ERROR_MASK = 0x34010002ull;
+
+static const uint64_t P9N2_C_21_PSCOM_ERROR_MASK = 0x35010002ull;
+
+static const uint64_t P9N2_C_22_PSCOM_ERROR_MASK = 0x36010002ull;
+
+static const uint64_t P9N2_C_23_PSCOM_ERROR_MASK = 0x37010002ull;
+
+static const uint64_t P9N2_EQ_PSCOM_ERROR_MASK = 0x10010002ull;
+
+static const uint64_t P9N2_EQ_0_PSCOM_ERROR_MASK = 0x10010002ull;
+
+static const uint64_t P9N2_EQ_1_PSCOM_ERROR_MASK = 0x11010002ull;
+
+static const uint64_t P9N2_EQ_2_PSCOM_ERROR_MASK = 0x12010002ull;
+
+static const uint64_t P9N2_EQ_3_PSCOM_ERROR_MASK = 0x13010002ull;
+
+static const uint64_t P9N2_EQ_4_PSCOM_ERROR_MASK = 0x14010002ull;
+
+static const uint64_t P9N2_EQ_5_PSCOM_ERROR_MASK = 0x15010002ull;
+
+static const uint64_t P9N2_EX_PSCOM_ERROR_MASK = 0x20010002ull;
+//DUPS: 21010002,
+static const uint64_t P9N2_EX_0_PSCOM_ERROR_MASK = 0x20010002ull;
+//DUPS: 21010002,
+static const uint64_t P9N2_EX_1_PSCOM_ERROR_MASK = 0x22010002ull;
+//DUPS: 23010002,
+static const uint64_t P9N2_EX_2_PSCOM_ERROR_MASK = 0x24010002ull;
+//DUPS: 25010002,
+static const uint64_t P9N2_EX_3_PSCOM_ERROR_MASK = 0x26010002ull;
+//DUPS: 27010002,
+static const uint64_t P9N2_EX_4_PSCOM_ERROR_MASK = 0x28010002ull;
+//DUPS: 29010002,
+static const uint64_t P9N2_EX_5_PSCOM_ERROR_MASK = 0x2A010002ull;
+//DUPS: 2B010002,
+static const uint64_t P9N2_EX_6_PSCOM_ERROR_MASK = 0x2C010002ull;
+//DUPS: 2D010002,
+static const uint64_t P9N2_EX_7_PSCOM_ERROR_MASK = 0x2F010002ull;
+//DUPS: 2F010002,
+static const uint64_t P9N2_EX_8_PSCOM_ERROR_MASK = 0x30010002ull;
+//DUPS: 31010002,
+static const uint64_t P9N2_EX_9_PSCOM_ERROR_MASK = 0x32010002ull;
+//DUPS: 33010002,
+static const uint64_t P9N2_EX_10_PSCOM_ERROR_MASK = 0x34010002ull;
+//DUPS: 35010002,
+static const uint64_t P9N2_EX_11_PSCOM_ERROR_MASK = 0x36010002ull;
+//DUPS: 37010002,
+
+static const uint64_t P9N2_C_PSCOM_MODE_REG = 0x20010000ull;
+
+static const uint64_t P9N2_C_0_PSCOM_MODE_REG = 0x20010000ull;
+
+static const uint64_t P9N2_C_1_PSCOM_MODE_REG = 0x21010000ull;
+
+static const uint64_t P9N2_C_2_PSCOM_MODE_REG = 0x22010000ull;
+
+static const uint64_t P9N2_C_3_PSCOM_MODE_REG = 0x23010000ull;
+
+static const uint64_t P9N2_C_4_PSCOM_MODE_REG = 0x24010000ull;
+
+static const uint64_t P9N2_C_5_PSCOM_MODE_REG = 0x25010000ull;
+
+static const uint64_t P9N2_C_6_PSCOM_MODE_REG = 0x26010000ull;
+
+static const uint64_t P9N2_C_7_PSCOM_MODE_REG = 0x27010000ull;
+
+static const uint64_t P9N2_C_8_PSCOM_MODE_REG = 0x28010000ull;
+
+static const uint64_t P9N2_C_9_PSCOM_MODE_REG = 0x29010000ull;
+
+static const uint64_t P9N2_C_10_PSCOM_MODE_REG = 0x2A010000ull;
+
+static const uint64_t P9N2_C_11_PSCOM_MODE_REG = 0x2B010000ull;
+
+static const uint64_t P9N2_C_12_PSCOM_MODE_REG = 0x2C010000ull;
+
+static const uint64_t P9N2_C_13_PSCOM_MODE_REG = 0x2D010000ull;
+
+static const uint64_t P9N2_C_14_PSCOM_MODE_REG = 0x2E010000ull;
+
+static const uint64_t P9N2_C_15_PSCOM_MODE_REG = 0x2F010000ull;
+
+static const uint64_t P9N2_C_16_PSCOM_MODE_REG = 0x30010000ull;
+
+static const uint64_t P9N2_C_17_PSCOM_MODE_REG = 0x31010000ull;
+
+static const uint64_t P9N2_C_18_PSCOM_MODE_REG = 0x32010000ull;
+
+static const uint64_t P9N2_C_19_PSCOM_MODE_REG = 0x33010000ull;
+
+static const uint64_t P9N2_C_20_PSCOM_MODE_REG = 0x34010000ull;
+
+static const uint64_t P9N2_C_21_PSCOM_MODE_REG = 0x35010000ull;
+
+static const uint64_t P9N2_C_22_PSCOM_MODE_REG = 0x36010000ull;
+
+static const uint64_t P9N2_C_23_PSCOM_MODE_REG = 0x37010000ull;
+
+static const uint64_t P9N2_EQ_PSCOM_MODE_REG = 0x10010000ull;
+
+static const uint64_t P9N2_EQ_0_PSCOM_MODE_REG = 0x10010000ull;
+
+static const uint64_t P9N2_EQ_1_PSCOM_MODE_REG = 0x11010000ull;
+
+static const uint64_t P9N2_EQ_2_PSCOM_MODE_REG = 0x12010000ull;
+
+static const uint64_t P9N2_EQ_3_PSCOM_MODE_REG = 0x13010000ull;
+
+static const uint64_t P9N2_EQ_4_PSCOM_MODE_REG = 0x14010000ull;
+
+static const uint64_t P9N2_EQ_5_PSCOM_MODE_REG = 0x15010000ull;
+
+static const uint64_t P9N2_EX_PSCOM_MODE_REG = 0x20010000ull;
+//DUPS: 21010000,
+static const uint64_t P9N2_EX_0_PSCOM_MODE_REG = 0x20010000ull;
+//DUPS: 21010000,
+static const uint64_t P9N2_EX_1_PSCOM_MODE_REG = 0x22010000ull;
+//DUPS: 23010000,
+static const uint64_t P9N2_EX_2_PSCOM_MODE_REG = 0x24010000ull;
+//DUPS: 25010000,
+static const uint64_t P9N2_EX_3_PSCOM_MODE_REG = 0x26010000ull;
+//DUPS: 27010000,
+static const uint64_t P9N2_EX_4_PSCOM_MODE_REG = 0x28010000ull;
+//DUPS: 29010000,
+static const uint64_t P9N2_EX_5_PSCOM_MODE_REG = 0x2A010000ull;
+//DUPS: 2B010000,
+static const uint64_t P9N2_EX_6_PSCOM_MODE_REG = 0x2C010000ull;
+//DUPS: 2D010000,
+static const uint64_t P9N2_EX_7_PSCOM_MODE_REG = 0x2F010000ull;
+//DUPS: 2F010000,
+static const uint64_t P9N2_EX_8_PSCOM_MODE_REG = 0x30010000ull;
+//DUPS: 31010000,
+static const uint64_t P9N2_EX_9_PSCOM_MODE_REG = 0x32010000ull;
+//DUPS: 33010000,
+static const uint64_t P9N2_EX_10_PSCOM_MODE_REG = 0x34010000ull;
+//DUPS: 35010000,
+static const uint64_t P9N2_EX_11_PSCOM_MODE_REG = 0x36010000ull;
+//DUPS: 37010000,
+
+static const uint64_t P9N2_C_PSCOM_STATUS_ERROR_REG = 0x20010001ull;
+
+static const uint64_t P9N2_C_0_PSCOM_STATUS_ERROR_REG = 0x20010001ull;
+
+static const uint64_t P9N2_C_1_PSCOM_STATUS_ERROR_REG = 0x21010001ull;
+
+static const uint64_t P9N2_C_2_PSCOM_STATUS_ERROR_REG = 0x22010001ull;
+
+static const uint64_t P9N2_C_3_PSCOM_STATUS_ERROR_REG = 0x23010001ull;
+
+static const uint64_t P9N2_C_4_PSCOM_STATUS_ERROR_REG = 0x24010001ull;
+
+static const uint64_t P9N2_C_5_PSCOM_STATUS_ERROR_REG = 0x25010001ull;
+
+static const uint64_t P9N2_C_6_PSCOM_STATUS_ERROR_REG = 0x26010001ull;
+
+static const uint64_t P9N2_C_7_PSCOM_STATUS_ERROR_REG = 0x27010001ull;
+
+static const uint64_t P9N2_C_8_PSCOM_STATUS_ERROR_REG = 0x28010001ull;
+
+static const uint64_t P9N2_C_9_PSCOM_STATUS_ERROR_REG = 0x29010001ull;
+
+static const uint64_t P9N2_C_10_PSCOM_STATUS_ERROR_REG = 0x2A010001ull;
+
+static const uint64_t P9N2_C_11_PSCOM_STATUS_ERROR_REG = 0x2B010001ull;
+
+static const uint64_t P9N2_C_12_PSCOM_STATUS_ERROR_REG = 0x2C010001ull;
+
+static const uint64_t P9N2_C_13_PSCOM_STATUS_ERROR_REG = 0x2D010001ull;
+
+static const uint64_t P9N2_C_14_PSCOM_STATUS_ERROR_REG = 0x2E010001ull;
+
+static const uint64_t P9N2_C_15_PSCOM_STATUS_ERROR_REG = 0x2F010001ull;
+
+static const uint64_t P9N2_C_16_PSCOM_STATUS_ERROR_REG = 0x30010001ull;
+
+static const uint64_t P9N2_C_17_PSCOM_STATUS_ERROR_REG = 0x31010001ull;
+
+static const uint64_t P9N2_C_18_PSCOM_STATUS_ERROR_REG = 0x32010001ull;
+
+static const uint64_t P9N2_C_19_PSCOM_STATUS_ERROR_REG = 0x33010001ull;
+
+static const uint64_t P9N2_C_20_PSCOM_STATUS_ERROR_REG = 0x34010001ull;
+
+static const uint64_t P9N2_C_21_PSCOM_STATUS_ERROR_REG = 0x35010001ull;
+
+static const uint64_t P9N2_C_22_PSCOM_STATUS_ERROR_REG = 0x36010001ull;
+
+static const uint64_t P9N2_C_23_PSCOM_STATUS_ERROR_REG = 0x37010001ull;
+
+static const uint64_t P9N2_EQ_PSCOM_STATUS_ERROR_REG = 0x10010001ull;
+
+static const uint64_t P9N2_EQ_0_PSCOM_STATUS_ERROR_REG = 0x10010001ull;
+
+static const uint64_t P9N2_EQ_1_PSCOM_STATUS_ERROR_REG = 0x11010001ull;
+
+static const uint64_t P9N2_EQ_2_PSCOM_STATUS_ERROR_REG = 0x12010001ull;
+
+static const uint64_t P9N2_EQ_3_PSCOM_STATUS_ERROR_REG = 0x13010001ull;
+
+static const uint64_t P9N2_EQ_4_PSCOM_STATUS_ERROR_REG = 0x14010001ull;
+
+static const uint64_t P9N2_EQ_5_PSCOM_STATUS_ERROR_REG = 0x15010001ull;
+
+static const uint64_t P9N2_EX_PSCOM_STATUS_ERROR_REG = 0x20010001ull;
+//DUPS: 21010001,
+static const uint64_t P9N2_EX_0_PSCOM_STATUS_ERROR_REG = 0x20010001ull;
+//DUPS: 21010001,
+static const uint64_t P9N2_EX_1_PSCOM_STATUS_ERROR_REG = 0x22010001ull;
+//DUPS: 23010001,
+static const uint64_t P9N2_EX_2_PSCOM_STATUS_ERROR_REG = 0x24010001ull;
+//DUPS: 25010001,
+static const uint64_t P9N2_EX_3_PSCOM_STATUS_ERROR_REG = 0x26010001ull;
+//DUPS: 27010001,
+static const uint64_t P9N2_EX_4_PSCOM_STATUS_ERROR_REG = 0x28010001ull;
+//DUPS: 29010001,
+static const uint64_t P9N2_EX_5_PSCOM_STATUS_ERROR_REG = 0x2A010001ull;
+//DUPS: 2B010001,
+static const uint64_t P9N2_EX_6_PSCOM_STATUS_ERROR_REG = 0x2C010001ull;
+//DUPS: 2D010001,
+static const uint64_t P9N2_EX_7_PSCOM_STATUS_ERROR_REG = 0x2F010001ull;
+//DUPS: 2F010001,
+static const uint64_t P9N2_EX_8_PSCOM_STATUS_ERROR_REG = 0x30010001ull;
+//DUPS: 31010001,
+static const uint64_t P9N2_EX_9_PSCOM_STATUS_ERROR_REG = 0x32010001ull;
+//DUPS: 33010001,
+static const uint64_t P9N2_EX_10_PSCOM_STATUS_ERROR_REG = 0x34010001ull;
+//DUPS: 35010001,
+static const uint64_t P9N2_EX_11_PSCOM_STATUS_ERROR_REG = 0x36010001ull;
+//DUPS: 37010001,
+
+static const uint64_t P9N2_C_PWM_EVENTS = 0x20010AA2ull;
+
+static const uint64_t P9N2_C_0_PWM_EVENTS = 0x20010AA2ull;
+
+static const uint64_t P9N2_C_1_PWM_EVENTS = 0x21010AA2ull;
+
+static const uint64_t P9N2_C_2_PWM_EVENTS = 0x22010AA2ull;
+
+static const uint64_t P9N2_C_3_PWM_EVENTS = 0x23010AA2ull;
+
+static const uint64_t P9N2_C_4_PWM_EVENTS = 0x24010AA2ull;
+
+static const uint64_t P9N2_C_5_PWM_EVENTS = 0x25010AA2ull;
+
+static const uint64_t P9N2_C_6_PWM_EVENTS = 0x26010AA2ull;
+
+static const uint64_t P9N2_C_7_PWM_EVENTS = 0x27010AA2ull;
+
+static const uint64_t P9N2_C_8_PWM_EVENTS = 0x28010AA2ull;
+
+static const uint64_t P9N2_C_9_PWM_EVENTS = 0x29010AA2ull;
+
+static const uint64_t P9N2_C_10_PWM_EVENTS = 0x2A010AA2ull;
+
+static const uint64_t P9N2_C_11_PWM_EVENTS = 0x2B010AA2ull;
+
+static const uint64_t P9N2_C_12_PWM_EVENTS = 0x2C010AA2ull;
+
+static const uint64_t P9N2_C_13_PWM_EVENTS = 0x2D010AA2ull;
+
+static const uint64_t P9N2_C_14_PWM_EVENTS = 0x2E010AA2ull;
+
+static const uint64_t P9N2_C_15_PWM_EVENTS = 0x2F010AA2ull;
+
+static const uint64_t P9N2_C_16_PWM_EVENTS = 0x30010AA2ull;
+
+static const uint64_t P9N2_C_17_PWM_EVENTS = 0x31010AA2ull;
+
+static const uint64_t P9N2_C_18_PWM_EVENTS = 0x32010AA2ull;
+
+static const uint64_t P9N2_C_19_PWM_EVENTS = 0x33010AA2ull;
+
+static const uint64_t P9N2_C_20_PWM_EVENTS = 0x34010AA2ull;
+
+static const uint64_t P9N2_C_21_PWM_EVENTS = 0x35010AA2ull;
+
+static const uint64_t P9N2_C_22_PWM_EVENTS = 0x36010AA2ull;
+
+static const uint64_t P9N2_C_23_PWM_EVENTS = 0x37010AA2ull;
+
+static const uint64_t P9N2_EX_0_L2_PWM_EVENTS = 0x20010AA2ull;
+//DUPS: 20010AA2,
+static const uint64_t P9N2_EX_10_L2_PWM_EVENTS = 0x34010AA2ull;
+//DUPS: 34010AA2,
+static const uint64_t P9N2_EX_11_L2_PWM_EVENTS = 0x36010AA2ull;
+//DUPS: 36010AA2,
+static const uint64_t P9N2_EX_1_L2_PWM_EVENTS = 0x22010AA2ull;
+//DUPS: 22010AA2,
+static const uint64_t P9N2_EX_2_L2_PWM_EVENTS = 0x24010AA2ull;
+//DUPS: 24010AA2,
+static const uint64_t P9N2_EX_3_L2_PWM_EVENTS = 0x26010AA2ull;
+//DUPS: 26010AA2,
+static const uint64_t P9N2_EX_4_L2_PWM_EVENTS = 0x28010AA2ull;
+//DUPS: 28010AA2,
+static const uint64_t P9N2_EX_5_L2_PWM_EVENTS = 0x2B010AA2ull;
+//DUPS: 2A010AA2,
+static const uint64_t P9N2_EX_6_L2_PWM_EVENTS = 0x2D010AA2ull;
+//DUPS: 2C010AA2,
+static const uint64_t P9N2_EX_7_L2_PWM_EVENTS = 0x2F010AA2ull;
+//DUPS: 2E010AA2,
+static const uint64_t P9N2_EX_8_L2_PWM_EVENTS = 0x30010AA2ull;
+//DUPS: 30010AA2,
+static const uint64_t P9N2_EX_9_L2_PWM_EVENTS = 0x32010AA2ull;
+//DUPS: 32010AA2,
+static const uint64_t P9N2_EX_L2_PWM_EVENTS = 0x20010AA2ull;
+//DUPS: 20010AA2,
+
+static const uint64_t P9N2_EQ_QPPM_DPLL_CTRL = 0x100F0152ull;
+
+static const uint64_t P9N2_EQ_QPPM_DPLL_CTRL_CLEAR = 0x100F0153ull;
+
+static const uint64_t P9N2_EQ_QPPM_DPLL_CTRL_OR = 0x100F0154ull;
+
+static const uint64_t P9N2_EQ_0_QPPM_DPLL_CTRL = 0x100F0152ull;
+
+static const uint64_t P9N2_EQ_0_QPPM_DPLL_CTRL_CLEAR = 0x100F0153ull;
+
+static const uint64_t P9N2_EQ_0_QPPM_DPLL_CTRL_OR = 0x100F0154ull;
+
+static const uint64_t P9N2_EQ_1_QPPM_DPLL_CTRL = 0x110F0152ull;
+
+static const uint64_t P9N2_EQ_1_QPPM_DPLL_CTRL_CLEAR = 0x110F0153ull;
+
+static const uint64_t P9N2_EQ_1_QPPM_DPLL_CTRL_OR = 0x110F0154ull;
+
+static const uint64_t P9N2_EQ_2_QPPM_DPLL_CTRL = 0x120F0152ull;
+
+static const uint64_t P9N2_EQ_2_QPPM_DPLL_CTRL_CLEAR = 0x120F0153ull;
+
+static const uint64_t P9N2_EQ_2_QPPM_DPLL_CTRL_OR = 0x120F0154ull;
+
+static const uint64_t P9N2_EQ_3_QPPM_DPLL_CTRL = 0x130F0152ull;
+
+static const uint64_t P9N2_EQ_3_QPPM_DPLL_CTRL_CLEAR = 0x130F0153ull;
+
+static const uint64_t P9N2_EQ_3_QPPM_DPLL_CTRL_OR = 0x130F0154ull;
+
+static const uint64_t P9N2_EQ_4_QPPM_DPLL_CTRL = 0x140F0152ull;
+
+static const uint64_t P9N2_EQ_4_QPPM_DPLL_CTRL_CLEAR = 0x140F0153ull;
+
+static const uint64_t P9N2_EQ_4_QPPM_DPLL_CTRL_OR = 0x140F0154ull;
+
+static const uint64_t P9N2_EQ_5_QPPM_DPLL_CTRL = 0x150F0152ull;
+
+static const uint64_t P9N2_EQ_5_QPPM_DPLL_CTRL_CLEAR = 0x150F0153ull;
+
+static const uint64_t P9N2_EQ_5_QPPM_DPLL_CTRL_OR = 0x150F0154ull;
+
+
+static const uint64_t P9N2_EQ_QPPM_DPLL_FREQ = 0x100F0151ull;
+
+static const uint64_t P9N2_EQ_0_QPPM_DPLL_FREQ = 0x100F0151ull;
+
+static const uint64_t P9N2_EQ_1_QPPM_DPLL_FREQ = 0x110F0151ull;
+
+static const uint64_t P9N2_EQ_2_QPPM_DPLL_FREQ = 0x120F0151ull;
+
+static const uint64_t P9N2_EQ_3_QPPM_DPLL_FREQ = 0x130F0151ull;
+
+static const uint64_t P9N2_EQ_4_QPPM_DPLL_FREQ = 0x140F0151ull;
+
+static const uint64_t P9N2_EQ_5_QPPM_DPLL_FREQ = 0x150F0151ull;
+
+
+static const uint64_t P9N2_EQ_QPPM_DPLL_ICHAR = 0x100F0157ull;
+
+static const uint64_t P9N2_EQ_0_QPPM_DPLL_ICHAR = 0x100F0157ull;
+
+static const uint64_t P9N2_EQ_1_QPPM_DPLL_ICHAR = 0x110F0157ull;
+
+static const uint64_t P9N2_EQ_2_QPPM_DPLL_ICHAR = 0x120F0157ull;
+
+static const uint64_t P9N2_EQ_3_QPPM_DPLL_ICHAR = 0x130F0157ull;
+
+static const uint64_t P9N2_EQ_4_QPPM_DPLL_ICHAR = 0x140F0157ull;
+
+static const uint64_t P9N2_EQ_5_QPPM_DPLL_ICHAR = 0x150F0157ull;
+
+
+static const uint64_t P9N2_EQ_QPPM_DPLL_OCHAR = 0x100F0156ull;
+
+static const uint64_t P9N2_EQ_0_QPPM_DPLL_OCHAR = 0x100F0156ull;
+
+static const uint64_t P9N2_EQ_1_QPPM_DPLL_OCHAR = 0x110F0156ull;
+
+static const uint64_t P9N2_EQ_2_QPPM_DPLL_OCHAR = 0x120F0156ull;
+
+static const uint64_t P9N2_EQ_3_QPPM_DPLL_OCHAR = 0x130F0156ull;
+
+static const uint64_t P9N2_EQ_4_QPPM_DPLL_OCHAR = 0x140F0156ull;
+
+static const uint64_t P9N2_EQ_5_QPPM_DPLL_OCHAR = 0x150F0156ull;
+
+
+static const uint64_t P9N2_EQ_QPPM_DPLL_STAT = 0x100F0155ull;
+
+static const uint64_t P9N2_EQ_0_QPPM_DPLL_STAT = 0x100F0155ull;
+
+static const uint64_t P9N2_EQ_1_QPPM_DPLL_STAT = 0x110F0155ull;
+
+static const uint64_t P9N2_EQ_2_QPPM_DPLL_STAT = 0x120F0155ull;
+
+static const uint64_t P9N2_EQ_3_QPPM_DPLL_STAT = 0x130F0155ull;
+
+static const uint64_t P9N2_EQ_4_QPPM_DPLL_STAT = 0x140F0155ull;
+
+static const uint64_t P9N2_EQ_5_QPPM_DPLL_STAT = 0x150F0155ull;
+
+
+static const uint64_t P9N2_EQ_QPPM_ERR = 0x100F0121ull;
+
+static const uint64_t P9N2_EQ_0_QPPM_ERR = 0x100F0121ull;
+
+static const uint64_t P9N2_EQ_1_QPPM_ERR = 0x110F0121ull;
+
+static const uint64_t P9N2_EQ_2_QPPM_ERR = 0x120F0121ull;
+
+static const uint64_t P9N2_EQ_3_QPPM_ERR = 0x130F0121ull;
+
+static const uint64_t P9N2_EQ_4_QPPM_ERR = 0x140F0121ull;
+
+static const uint64_t P9N2_EQ_5_QPPM_ERR = 0x150F0121ull;
+
+
+static const uint64_t P9N2_EQ_QPPM_ERRMSK = 0x100F0122ull;
+
+static const uint64_t P9N2_EQ_0_QPPM_ERRMSK = 0x100F0122ull;
+
+static const uint64_t P9N2_EQ_1_QPPM_ERRMSK = 0x110F0122ull;
+
+static const uint64_t P9N2_EQ_2_QPPM_ERRMSK = 0x120F0122ull;
+
+static const uint64_t P9N2_EQ_3_QPPM_ERRMSK = 0x130F0122ull;
+
+static const uint64_t P9N2_EQ_4_QPPM_ERRMSK = 0x140F0122ull;
+
+static const uint64_t P9N2_EQ_5_QPPM_ERRMSK = 0x150F0122ull;
+
+
+static const uint64_t P9N2_EQ_QPPM_ERRSUM = 0x100F0120ull;
+
+static const uint64_t P9N2_EQ_0_QPPM_ERRSUM = 0x100F0120ull;
+
+static const uint64_t P9N2_EQ_1_QPPM_ERRSUM = 0x110F0120ull;
+
+static const uint64_t P9N2_EQ_2_QPPM_ERRSUM = 0x120F0120ull;
+
+static const uint64_t P9N2_EQ_3_QPPM_ERRSUM = 0x130F0120ull;
+
+static const uint64_t P9N2_EQ_4_QPPM_ERRSUM = 0x140F0120ull;
+
+static const uint64_t P9N2_EQ_5_QPPM_ERRSUM = 0x150F0120ull;
+
+
+static const uint64_t P9N2_EQ_QPPM_EXCGCR = 0x100F0165ull;
+
+static const uint64_t P9N2_EQ_QPPM_EXCGCR_CLEAR = 0x100F0166ull;
+
+static const uint64_t P9N2_EQ_QPPM_EXCGCR_OR = 0x100F0167ull;
+
+static const uint64_t P9N2_EQ_0_QPPM_EXCGCR = 0x100F0165ull;
+
+static const uint64_t P9N2_EQ_0_QPPM_EXCGCR_CLEAR = 0x100F0166ull;
+
+static const uint64_t P9N2_EQ_0_QPPM_EXCGCR_OR = 0x100F0167ull;
+
+static const uint64_t P9N2_EQ_1_QPPM_EXCGCR = 0x110F0165ull;
+
+static const uint64_t P9N2_EQ_1_QPPM_EXCGCR_CLEAR = 0x110F0166ull;
+
+static const uint64_t P9N2_EQ_1_QPPM_EXCGCR_OR = 0x110F0167ull;
+
+static const uint64_t P9N2_EQ_2_QPPM_EXCGCR = 0x120F0165ull;
+
+static const uint64_t P9N2_EQ_2_QPPM_EXCGCR_CLEAR = 0x120F0166ull;
+
+static const uint64_t P9N2_EQ_2_QPPM_EXCGCR_OR = 0x120F0167ull;
+
+static const uint64_t P9N2_EQ_3_QPPM_EXCGCR = 0x130F0165ull;
+
+static const uint64_t P9N2_EQ_3_QPPM_EXCGCR_CLEAR = 0x130F0166ull;
+
+static const uint64_t P9N2_EQ_3_QPPM_EXCGCR_OR = 0x130F0167ull;
+
+static const uint64_t P9N2_EQ_4_QPPM_EXCGCR = 0x140F0165ull;
+
+static const uint64_t P9N2_EQ_4_QPPM_EXCGCR_CLEAR = 0x140F0166ull;
+
+static const uint64_t P9N2_EQ_4_QPPM_EXCGCR_OR = 0x140F0167ull;
+
+static const uint64_t P9N2_EQ_5_QPPM_EXCGCR = 0x150F0165ull;
+
+static const uint64_t P9N2_EQ_5_QPPM_EXCGCR_CLEAR = 0x150F0166ull;
+
+static const uint64_t P9N2_EQ_5_QPPM_EXCGCR_OR = 0x150F0167ull;
+
+
+static const uint64_t P9N2_EQ_QPPM_OCCHB = 0x100F015Full;
+
+static const uint64_t P9N2_EQ_0_QPPM_OCCHB = 0x100F015Full;
+
+static const uint64_t P9N2_EQ_1_QPPM_OCCHB = 0x110F015Full;
+
+static const uint64_t P9N2_EQ_2_QPPM_OCCHB = 0x120F015Full;
+
+static const uint64_t P9N2_EQ_3_QPPM_OCCHB = 0x130F015Full;
+
+static const uint64_t P9N2_EQ_4_QPPM_OCCHB = 0x140F015Full;
+
+static const uint64_t P9N2_EQ_5_QPPM_OCCHB = 0x150F015Full;
+
+
+static const uint64_t P9N2_EQ_QPPM_QACCR = 0x100F0160ull;
+
+static const uint64_t P9N2_EQ_QPPM_QACCR_CLEAR = 0x100F0161ull;
+
+static const uint64_t P9N2_EQ_QPPM_QACCR_OR = 0x100F0162ull;
+
+static const uint64_t P9N2_EQ_0_QPPM_QACCR = 0x100F0160ull;
+
+static const uint64_t P9N2_EQ_0_QPPM_QACCR_CLEAR = 0x100F0161ull;
+
+static const uint64_t P9N2_EQ_0_QPPM_QACCR_OR = 0x100F0162ull;
+
+static const uint64_t P9N2_EQ_1_QPPM_QACCR = 0x110F0160ull;
+
+static const uint64_t P9N2_EQ_1_QPPM_QACCR_CLEAR = 0x110F0161ull;
+
+static const uint64_t P9N2_EQ_1_QPPM_QACCR_OR = 0x110F0162ull;
+
+static const uint64_t P9N2_EQ_2_QPPM_QACCR = 0x120F0160ull;
+
+static const uint64_t P9N2_EQ_2_QPPM_QACCR_CLEAR = 0x120F0161ull;
+
+static const uint64_t P9N2_EQ_2_QPPM_QACCR_OR = 0x120F0162ull;
+
+static const uint64_t P9N2_EQ_3_QPPM_QACCR = 0x130F0160ull;
+
+static const uint64_t P9N2_EQ_3_QPPM_QACCR_CLEAR = 0x130F0161ull;
+
+static const uint64_t P9N2_EQ_3_QPPM_QACCR_OR = 0x130F0162ull;
+
+static const uint64_t P9N2_EQ_4_QPPM_QACCR = 0x140F0160ull;
+
+static const uint64_t P9N2_EQ_4_QPPM_QACCR_CLEAR = 0x140F0161ull;
+
+static const uint64_t P9N2_EQ_4_QPPM_QACCR_OR = 0x140F0162ull;
+
+static const uint64_t P9N2_EQ_5_QPPM_QACCR = 0x150F0160ull;
+
+static const uint64_t P9N2_EQ_5_QPPM_QACCR_CLEAR = 0x150F0161ull;
+
+static const uint64_t P9N2_EQ_5_QPPM_QACCR_OR = 0x150F0162ull;
+
+
+static const uint64_t P9N2_EQ_QPPM_QACSR = 0x100F0163ull;
+
+static const uint64_t P9N2_EQ_0_QPPM_QACSR = 0x100F0163ull;
+
+static const uint64_t P9N2_EQ_1_QPPM_QACSR = 0x110F0163ull;
+
+static const uint64_t P9N2_EQ_2_QPPM_QACSR = 0x120F0163ull;
+
+static const uint64_t P9N2_EQ_3_QPPM_QACSR = 0x130F0163ull;
+
+static const uint64_t P9N2_EQ_4_QPPM_QACSR = 0x140F0163ull;
+
+static const uint64_t P9N2_EQ_5_QPPM_QACSR = 0x150F0163ull;
+
+
+static const uint64_t P9N2_EQ_QPPM_QCCR_SCOM = 0x100F01BDull;
+
+static const uint64_t P9N2_EQ_QPPM_QCCR_SCOM1 = 0x100F01BEull;
+
+static const uint64_t P9N2_EQ_QPPM_QCCR_SCOM2 = 0x100F01BFull;
+
+static const uint64_t P9N2_EQ_0_QPPM_QCCR_SCOM = 0x100F01BDull;
+
+static const uint64_t P9N2_EQ_0_QPPM_QCCR_SCOM1 = 0x100F01BEull;
+
+static const uint64_t P9N2_EQ_0_QPPM_QCCR_SCOM2 = 0x100F01BFull;
+
+static const uint64_t P9N2_EQ_1_QPPM_QCCR_SCOM = 0x110F01BDull;
+
+static const uint64_t P9N2_EQ_1_QPPM_QCCR_SCOM1 = 0x110F01BEull;
+
+static const uint64_t P9N2_EQ_1_QPPM_QCCR_SCOM2 = 0x110F01BFull;
+
+static const uint64_t P9N2_EQ_2_QPPM_QCCR_SCOM = 0x120F01BDull;
+
+static const uint64_t P9N2_EQ_2_QPPM_QCCR_SCOM1 = 0x120F01BEull;
+
+static const uint64_t P9N2_EQ_2_QPPM_QCCR_SCOM2 = 0x120F01BFull;
+
+static const uint64_t P9N2_EQ_3_QPPM_QCCR_SCOM = 0x130F01BDull;
+
+static const uint64_t P9N2_EQ_3_QPPM_QCCR_SCOM1 = 0x130F01BEull;
+
+static const uint64_t P9N2_EQ_3_QPPM_QCCR_SCOM2 = 0x130F01BFull;
+
+static const uint64_t P9N2_EQ_4_QPPM_QCCR_SCOM = 0x140F01BDull;
+
+static const uint64_t P9N2_EQ_4_QPPM_QCCR_SCOM1 = 0x140F01BEull;
+
+static const uint64_t P9N2_EQ_4_QPPM_QCCR_SCOM2 = 0x140F01BFull;
+
+static const uint64_t P9N2_EQ_5_QPPM_QCCR_SCOM = 0x150F01BDull;
+
+static const uint64_t P9N2_EQ_5_QPPM_QCCR_SCOM1 = 0x150F01BEull;
+
+static const uint64_t P9N2_EQ_5_QPPM_QCCR_SCOM2 = 0x150F01BFull;
+
+
+static const uint64_t P9N2_EQ_QPPM_QPMMR = 0x100F0103ull;
+
+static const uint64_t P9N2_EQ_QPPM_QPMMR_CLEAR = 0x100F0104ull;
+
+static const uint64_t P9N2_EQ_QPPM_QPMMR_OR = 0x100F0105ull;
+
+static const uint64_t P9N2_EQ_0_QPPM_QPMMR = 0x100F0103ull;
+
+static const uint64_t P9N2_EQ_0_QPPM_QPMMR_CLEAR = 0x100F0104ull;
+
+static const uint64_t P9N2_EQ_0_QPPM_QPMMR_OR = 0x100F0105ull;
+
+static const uint64_t P9N2_EQ_1_QPPM_QPMMR = 0x110F0103ull;
+
+static const uint64_t P9N2_EQ_1_QPPM_QPMMR_CLEAR = 0x110F0104ull;
+
+static const uint64_t P9N2_EQ_1_QPPM_QPMMR_OR = 0x110F0105ull;
+
+static const uint64_t P9N2_EQ_2_QPPM_QPMMR = 0x120F0103ull;
+
+static const uint64_t P9N2_EQ_2_QPPM_QPMMR_CLEAR = 0x120F0104ull;
+
+static const uint64_t P9N2_EQ_2_QPPM_QPMMR_OR = 0x120F0105ull;
+
+static const uint64_t P9N2_EQ_3_QPPM_QPMMR = 0x130F0103ull;
+
+static const uint64_t P9N2_EQ_3_QPPM_QPMMR_CLEAR = 0x130F0104ull;
+
+static const uint64_t P9N2_EQ_3_QPPM_QPMMR_OR = 0x130F0105ull;
+
+static const uint64_t P9N2_EQ_4_QPPM_QPMMR = 0x140F0103ull;
+
+static const uint64_t P9N2_EQ_4_QPPM_QPMMR_CLEAR = 0x140F0104ull;
+
+static const uint64_t P9N2_EQ_4_QPPM_QPMMR_OR = 0x140F0105ull;
+
+static const uint64_t P9N2_EQ_5_QPPM_QPMMR = 0x150F0103ull;
+
+static const uint64_t P9N2_EQ_5_QPPM_QPMMR_CLEAR = 0x150F0104ull;
+
+static const uint64_t P9N2_EQ_5_QPPM_QPMMR_OR = 0x150F0105ull;
+
+
+static const uint64_t P9N2_EQ_QPPM_VDMCFGR = 0x100F01B6ull;
+
+static const uint64_t P9N2_EQ_0_QPPM_VDMCFGR = 0x100F01B6ull;
+
+static const uint64_t P9N2_EQ_1_QPPM_VDMCFGR = 0x110F01B6ull;
+
+static const uint64_t P9N2_EQ_2_QPPM_VDMCFGR = 0x120F01B6ull;
+
+static const uint64_t P9N2_EQ_3_QPPM_VDMCFGR = 0x130F01B6ull;
+
+static const uint64_t P9N2_EQ_4_QPPM_VDMCFGR = 0x140F01B6ull;
+
+static const uint64_t P9N2_EQ_5_QPPM_VDMCFGR = 0x150F01B6ull;
+
+
+static const uint64_t P9N2_EQ_QPPM_VOLT_CHAR = 0x100F01BBull;
+
+static const uint64_t P9N2_EQ_0_QPPM_VOLT_CHAR = 0x100F01BBull;
+
+static const uint64_t P9N2_EQ_1_QPPM_VOLT_CHAR = 0x110F01BBull;
+
+static const uint64_t P9N2_EQ_2_QPPM_VOLT_CHAR = 0x120F01BBull;
+
+static const uint64_t P9N2_EQ_3_QPPM_VOLT_CHAR = 0x130F01BBull;
+
+static const uint64_t P9N2_EQ_4_QPPM_VOLT_CHAR = 0x140F01BBull;
+
+static const uint64_t P9N2_EQ_5_QPPM_VOLT_CHAR = 0x150F01BBull;
+
+
+static const uint64_t P9N2_C_RAM_CTRL = 0x20010A4Full;
+
+static const uint64_t P9N2_C_0_RAM_CTRL = 0x20010A4Full;
+
+static const uint64_t P9N2_C_1_RAM_CTRL = 0x21010A4Full;
+
+static const uint64_t P9N2_C_2_RAM_CTRL = 0x22010A4Full;
+
+static const uint64_t P9N2_C_3_RAM_CTRL = 0x23010A4Full;
+
+static const uint64_t P9N2_C_4_RAM_CTRL = 0x24010A4Full;
+
+static const uint64_t P9N2_C_5_RAM_CTRL = 0x25010A4Full;
+
+static const uint64_t P9N2_C_6_RAM_CTRL = 0x26010A4Full;
+
+static const uint64_t P9N2_C_7_RAM_CTRL = 0x27010A4Full;
+
+static const uint64_t P9N2_C_8_RAM_CTRL = 0x28010A4Full;
+
+static const uint64_t P9N2_C_9_RAM_CTRL = 0x29010A4Full;
+
+static const uint64_t P9N2_C_10_RAM_CTRL = 0x2A010A4Full;
+
+static const uint64_t P9N2_C_11_RAM_CTRL = 0x2B010A4Full;
+
+static const uint64_t P9N2_C_12_RAM_CTRL = 0x2C010A4Full;
+
+static const uint64_t P9N2_C_13_RAM_CTRL = 0x2D010A4Full;
+
+static const uint64_t P9N2_C_14_RAM_CTRL = 0x2E010A4Full;
+
+static const uint64_t P9N2_C_15_RAM_CTRL = 0x2F010A4Full;
+
+static const uint64_t P9N2_C_16_RAM_CTRL = 0x30010A4Full;
+
+static const uint64_t P9N2_C_17_RAM_CTRL = 0x31010A4Full;
+
+static const uint64_t P9N2_C_18_RAM_CTRL = 0x32010A4Full;
+
+static const uint64_t P9N2_C_19_RAM_CTRL = 0x33010A4Full;
+
+static const uint64_t P9N2_C_20_RAM_CTRL = 0x34010A4Full;
+
+static const uint64_t P9N2_C_21_RAM_CTRL = 0x35010A4Full;
+
+static const uint64_t P9N2_C_22_RAM_CTRL = 0x36010A4Full;
+
+static const uint64_t P9N2_C_23_RAM_CTRL = 0x37010A4Full;
+
+static const uint64_t P9N2_EX_RAM_CTRL = 0x20010A4Full;
+//DUPS: 21010A4F,
+static const uint64_t P9N2_EX_0_RAM_CTRL = 0x20010A4Full;
+//DUPS: 21010A4F,
+static const uint64_t P9N2_EX_1_RAM_CTRL = 0x22010A4Full;
+//DUPS: 23010A4F,
+static const uint64_t P9N2_EX_2_RAM_CTRL = 0x24010A4Full;
+//DUPS: 25010A4F,
+static const uint64_t P9N2_EX_3_RAM_CTRL = 0x26010A4Full;
+//DUPS: 27010A4F,
+static const uint64_t P9N2_EX_4_RAM_CTRL = 0x28010A4Full;
+//DUPS: 29010A4F,
+static const uint64_t P9N2_EX_5_RAM_CTRL = 0x2A010A4Full;
+//DUPS: 2B010A4F,
+static const uint64_t P9N2_EX_6_RAM_CTRL = 0x2C010A4Full;
+//DUPS: 2D010A4F,
+static const uint64_t P9N2_EX_7_RAM_CTRL = 0x2F010A4Full;
+//DUPS: 2F010A4F,
+static const uint64_t P9N2_EX_8_RAM_CTRL = 0x30010A4Full;
+//DUPS: 31010A4F,
+static const uint64_t P9N2_EX_9_RAM_CTRL = 0x32010A4Full;
+//DUPS: 33010A4F,
+static const uint64_t P9N2_EX_10_RAM_CTRL = 0x34010A4Full;
+//DUPS: 35010A4F,
+static const uint64_t P9N2_EX_11_RAM_CTRL = 0x36010A4Full;
+//DUPS: 37010A4F,
+
+static const uint64_t P9N2_C_RAM_MODEREG = 0x20010A4Eull;
+
+static const uint64_t P9N2_C_0_RAM_MODEREG = 0x20010A4Eull;
+
+static const uint64_t P9N2_C_1_RAM_MODEREG = 0x21010A4Eull;
+
+static const uint64_t P9N2_C_2_RAM_MODEREG = 0x22010A4Eull;
+
+static const uint64_t P9N2_C_3_RAM_MODEREG = 0x23010A4Eull;
+
+static const uint64_t P9N2_C_4_RAM_MODEREG = 0x24010A4Eull;
+
+static const uint64_t P9N2_C_5_RAM_MODEREG = 0x25010A4Eull;
+
+static const uint64_t P9N2_C_6_RAM_MODEREG = 0x26010A4Eull;
+
+static const uint64_t P9N2_C_7_RAM_MODEREG = 0x27010A4Eull;
+
+static const uint64_t P9N2_C_8_RAM_MODEREG = 0x28010A4Eull;
+
+static const uint64_t P9N2_C_9_RAM_MODEREG = 0x29010A4Eull;
+
+static const uint64_t P9N2_C_10_RAM_MODEREG = 0x2A010A4Eull;
+
+static const uint64_t P9N2_C_11_RAM_MODEREG = 0x2B010A4Eull;
+
+static const uint64_t P9N2_C_12_RAM_MODEREG = 0x2C010A4Eull;
+
+static const uint64_t P9N2_C_13_RAM_MODEREG = 0x2D010A4Eull;
+
+static const uint64_t P9N2_C_14_RAM_MODEREG = 0x2E010A4Eull;
+
+static const uint64_t P9N2_C_15_RAM_MODEREG = 0x2F010A4Eull;
+
+static const uint64_t P9N2_C_16_RAM_MODEREG = 0x30010A4Eull;
+
+static const uint64_t P9N2_C_17_RAM_MODEREG = 0x31010A4Eull;
+
+static const uint64_t P9N2_C_18_RAM_MODEREG = 0x32010A4Eull;
+
+static const uint64_t P9N2_C_19_RAM_MODEREG = 0x33010A4Eull;
+
+static const uint64_t P9N2_C_20_RAM_MODEREG = 0x34010A4Eull;
+
+static const uint64_t P9N2_C_21_RAM_MODEREG = 0x35010A4Eull;
+
+static const uint64_t P9N2_C_22_RAM_MODEREG = 0x36010A4Eull;
+
+static const uint64_t P9N2_C_23_RAM_MODEREG = 0x37010A4Eull;
+
+static const uint64_t P9N2_EX_RAM_MODEREG = 0x20010A4Eull;
+//DUPS: 21010A4E,
+static const uint64_t P9N2_EX_0_RAM_MODEREG = 0x20010A4Eull;
+//DUPS: 21010A4E,
+static const uint64_t P9N2_EX_1_RAM_MODEREG = 0x22010A4Eull;
+//DUPS: 23010A4E,
+static const uint64_t P9N2_EX_2_RAM_MODEREG = 0x24010A4Eull;
+//DUPS: 25010A4E,
+static const uint64_t P9N2_EX_3_RAM_MODEREG = 0x26010A4Eull;
+//DUPS: 27010A4E,
+static const uint64_t P9N2_EX_4_RAM_MODEREG = 0x28010A4Eull;
+//DUPS: 29010A4E,
+static const uint64_t P9N2_EX_5_RAM_MODEREG = 0x2A010A4Eull;
+//DUPS: 2B010A4E,
+static const uint64_t P9N2_EX_6_RAM_MODEREG = 0x2C010A4Eull;
+//DUPS: 2D010A4E,
+static const uint64_t P9N2_EX_7_RAM_MODEREG = 0x2F010A4Eull;
+//DUPS: 2F010A4E,
+static const uint64_t P9N2_EX_8_RAM_MODEREG = 0x30010A4Eull;
+//DUPS: 31010A4E,
+static const uint64_t P9N2_EX_9_RAM_MODEREG = 0x32010A4Eull;
+//DUPS: 33010A4E,
+static const uint64_t P9N2_EX_10_RAM_MODEREG = 0x34010A4Eull;
+//DUPS: 35010A4E,
+static const uint64_t P9N2_EX_11_RAM_MODEREG = 0x36010A4Eull;
+//DUPS: 37010A4E,
+
+static const uint64_t P9N2_C_RAM_STATUS = 0x20010A50ull;
+
+static const uint64_t P9N2_C_0_RAM_STATUS = 0x20010A50ull;
+
+static const uint64_t P9N2_C_1_RAM_STATUS = 0x21010A50ull;
+
+static const uint64_t P9N2_C_2_RAM_STATUS = 0x22010A50ull;
+
+static const uint64_t P9N2_C_3_RAM_STATUS = 0x23010A50ull;
+
+static const uint64_t P9N2_C_4_RAM_STATUS = 0x24010A50ull;
+
+static const uint64_t P9N2_C_5_RAM_STATUS = 0x25010A50ull;
+
+static const uint64_t P9N2_C_6_RAM_STATUS = 0x26010A50ull;
+
+static const uint64_t P9N2_C_7_RAM_STATUS = 0x27010A50ull;
+
+static const uint64_t P9N2_C_8_RAM_STATUS = 0x28010A50ull;
+
+static const uint64_t P9N2_C_9_RAM_STATUS = 0x29010A50ull;
+
+static const uint64_t P9N2_C_10_RAM_STATUS = 0x2A010A50ull;
+
+static const uint64_t P9N2_C_11_RAM_STATUS = 0x2B010A50ull;
+
+static const uint64_t P9N2_C_12_RAM_STATUS = 0x2C010A50ull;
+
+static const uint64_t P9N2_C_13_RAM_STATUS = 0x2D010A50ull;
+
+static const uint64_t P9N2_C_14_RAM_STATUS = 0x2E010A50ull;
+
+static const uint64_t P9N2_C_15_RAM_STATUS = 0x2F010A50ull;
+
+static const uint64_t P9N2_C_16_RAM_STATUS = 0x30010A50ull;
+
+static const uint64_t P9N2_C_17_RAM_STATUS = 0x31010A50ull;
+
+static const uint64_t P9N2_C_18_RAM_STATUS = 0x32010A50ull;
+
+static const uint64_t P9N2_C_19_RAM_STATUS = 0x33010A50ull;
+
+static const uint64_t P9N2_C_20_RAM_STATUS = 0x34010A50ull;
+
+static const uint64_t P9N2_C_21_RAM_STATUS = 0x35010A50ull;
+
+static const uint64_t P9N2_C_22_RAM_STATUS = 0x36010A50ull;
+
+static const uint64_t P9N2_C_23_RAM_STATUS = 0x37010A50ull;
+
+static const uint64_t P9N2_EX_0_L2_RAM_STATUS = 0x20010A50ull;
+//DUPS: 21010A50,
+static const uint64_t P9N2_EX_10_L2_RAM_STATUS = 0x34010A50ull;
+//DUPS: 35010A50,
+static const uint64_t P9N2_EX_11_L2_RAM_STATUS = 0x36010A50ull;
+//DUPS: 37010A50,
+static const uint64_t P9N2_EX_1_L2_RAM_STATUS = 0x22010A50ull;
+//DUPS: 23010A50,
+static const uint64_t P9N2_EX_2_L2_RAM_STATUS = 0x24010A50ull;
+//DUPS: 25010A50,
+static const uint64_t P9N2_EX_3_L2_RAM_STATUS = 0x26010A50ull;
+//DUPS: 27010A50,
+static const uint64_t P9N2_EX_4_L2_RAM_STATUS = 0x28010A50ull;
+//DUPS: 29010A50,
+static const uint64_t P9N2_EX_5_L2_RAM_STATUS = 0x2A010A50ull;
+//DUPS: 2B010A50,
+static const uint64_t P9N2_EX_6_L2_RAM_STATUS = 0x2C010A50ull;
+//DUPS: 2D010A50,
+static const uint64_t P9N2_EX_7_L2_RAM_STATUS = 0x2F010A50ull;
+//DUPS: 2F010A50,
+static const uint64_t P9N2_EX_8_L2_RAM_STATUS = 0x30010A50ull;
+//DUPS: 31010A50,
+static const uint64_t P9N2_EX_9_L2_RAM_STATUS = 0x32010A50ull;
+//DUPS: 33010A50,
+static const uint64_t P9N2_EX_L2_RAM_STATUS = 0x20010A50ull;
+//DUPS: 21010A50,
+
+static const uint64_t P9N2_C_RAS_MODEREG = 0x20010A9Dull;
+
+static const uint64_t P9N2_C_0_RAS_MODEREG = 0x20010A9Dull;
+
+static const uint64_t P9N2_C_1_RAS_MODEREG = 0x21010A9Dull;
+
+static const uint64_t P9N2_C_2_RAS_MODEREG = 0x22010A9Dull;
+
+static const uint64_t P9N2_C_3_RAS_MODEREG = 0x23010A9Dull;
+
+static const uint64_t P9N2_C_4_RAS_MODEREG = 0x24010A9Dull;
+
+static const uint64_t P9N2_C_5_RAS_MODEREG = 0x25010A9Dull;
+
+static const uint64_t P9N2_C_6_RAS_MODEREG = 0x26010A9Dull;
+
+static const uint64_t P9N2_C_7_RAS_MODEREG = 0x27010A9Dull;
+
+static const uint64_t P9N2_C_8_RAS_MODEREG = 0x28010A9Dull;
+
+static const uint64_t P9N2_C_9_RAS_MODEREG = 0x29010A9Dull;
+
+static const uint64_t P9N2_C_10_RAS_MODEREG = 0x2A010A9Dull;
+
+static const uint64_t P9N2_C_11_RAS_MODEREG = 0x2B010A9Dull;
+
+static const uint64_t P9N2_C_12_RAS_MODEREG = 0x2C010A9Dull;
+
+static const uint64_t P9N2_C_13_RAS_MODEREG = 0x2D010A9Dull;
+
+static const uint64_t P9N2_C_14_RAS_MODEREG = 0x2E010A9Dull;
+
+static const uint64_t P9N2_C_15_RAS_MODEREG = 0x2F010A9Dull;
+
+static const uint64_t P9N2_C_16_RAS_MODEREG = 0x30010A9Dull;
+
+static const uint64_t P9N2_C_17_RAS_MODEREG = 0x31010A9Dull;
+
+static const uint64_t P9N2_C_18_RAS_MODEREG = 0x32010A9Dull;
+
+static const uint64_t P9N2_C_19_RAS_MODEREG = 0x33010A9Dull;
+
+static const uint64_t P9N2_C_20_RAS_MODEREG = 0x34010A9Dull;
+
+static const uint64_t P9N2_C_21_RAS_MODEREG = 0x35010A9Dull;
+
+static const uint64_t P9N2_C_22_RAS_MODEREG = 0x36010A9Dull;
+
+static const uint64_t P9N2_C_23_RAS_MODEREG = 0x37010A9Dull;
+
+static const uint64_t P9N2_EX_0_L2_RAS_MODEREG = 0x20010A9Dull;
+//DUPS: 21010A9D,
+static const uint64_t P9N2_EX_10_L2_RAS_MODEREG = 0x34010A9Dull;
+//DUPS: 35010A9D,
+static const uint64_t P9N2_EX_11_L2_RAS_MODEREG = 0x36010A9Dull;
+//DUPS: 37010A9D,
+static const uint64_t P9N2_EX_1_L2_RAS_MODEREG = 0x22010A9Dull;
+//DUPS: 23010A9D,
+static const uint64_t P9N2_EX_2_L2_RAS_MODEREG = 0x24010A9Dull;
+//DUPS: 25010A9D,
+static const uint64_t P9N2_EX_3_L2_RAS_MODEREG = 0x26010A9Dull;
+//DUPS: 27010A9D,
+static const uint64_t P9N2_EX_4_L2_RAS_MODEREG = 0x28010A9Dull;
+//DUPS: 29010A9D,
+static const uint64_t P9N2_EX_5_L2_RAS_MODEREG = 0x2A010A9Dull;
+//DUPS: 2B010A9D,
+static const uint64_t P9N2_EX_6_L2_RAS_MODEREG = 0x2C010A9Dull;
+//DUPS: 2D010A9D,
+static const uint64_t P9N2_EX_7_L2_RAS_MODEREG = 0x2F010A9Dull;
+//DUPS: 2F010A9D,
+static const uint64_t P9N2_EX_8_L2_RAS_MODEREG = 0x30010A9Dull;
+//DUPS: 31010A9D,
+static const uint64_t P9N2_EX_9_L2_RAS_MODEREG = 0x32010A9Dull;
+//DUPS: 33010A9D,
+static const uint64_t P9N2_EX_L2_RAS_MODEREG = 0x20010A9Dull;
+//DUPS: 21010A9D,
+
+static const uint64_t P9N2_C_RAS_STATUS = 0x20010A02ull;
+
+static const uint64_t P9N2_C_0_RAS_STATUS = 0x20010A02ull;
+
+static const uint64_t P9N2_C_1_RAS_STATUS = 0x21010A02ull;
+
+static const uint64_t P9N2_C_2_RAS_STATUS = 0x22010A02ull;
+
+static const uint64_t P9N2_C_3_RAS_STATUS = 0x23010A02ull;
+
+static const uint64_t P9N2_C_4_RAS_STATUS = 0x24010A02ull;
+
+static const uint64_t P9N2_C_5_RAS_STATUS = 0x25010A02ull;
+
+static const uint64_t P9N2_C_6_RAS_STATUS = 0x26010A02ull;
+
+static const uint64_t P9N2_C_7_RAS_STATUS = 0x27010A02ull;
+
+static const uint64_t P9N2_C_8_RAS_STATUS = 0x28010A02ull;
+
+static const uint64_t P9N2_C_9_RAS_STATUS = 0x29010A02ull;
+
+static const uint64_t P9N2_C_10_RAS_STATUS = 0x2A010A02ull;
+
+static const uint64_t P9N2_C_11_RAS_STATUS = 0x2B010A02ull;
+
+static const uint64_t P9N2_C_12_RAS_STATUS = 0x2C010A02ull;
+
+static const uint64_t P9N2_C_13_RAS_STATUS = 0x2D010A02ull;
+
+static const uint64_t P9N2_C_14_RAS_STATUS = 0x2E010A02ull;
+
+static const uint64_t P9N2_C_15_RAS_STATUS = 0x2F010A02ull;
+
+static const uint64_t P9N2_C_16_RAS_STATUS = 0x30010A02ull;
+
+static const uint64_t P9N2_C_17_RAS_STATUS = 0x31010A02ull;
+
+static const uint64_t P9N2_C_18_RAS_STATUS = 0x32010A02ull;
+
+static const uint64_t P9N2_C_19_RAS_STATUS = 0x33010A02ull;
+
+static const uint64_t P9N2_C_20_RAS_STATUS = 0x34010A02ull;
+
+static const uint64_t P9N2_C_21_RAS_STATUS = 0x35010A02ull;
+
+static const uint64_t P9N2_C_22_RAS_STATUS = 0x36010A02ull;
+
+static const uint64_t P9N2_C_23_RAS_STATUS = 0x37010A02ull;
+
+static const uint64_t P9N2_EX_0_L2_RAS_STATUS = 0x20010A02ull;
+//DUPS: 21010A02,
+static const uint64_t P9N2_EX_10_L2_RAS_STATUS = 0x34010A02ull;
+//DUPS: 35010A02,
+static const uint64_t P9N2_EX_11_L2_RAS_STATUS = 0x36010A02ull;
+//DUPS: 37010A02,
+static const uint64_t P9N2_EX_1_L2_RAS_STATUS = 0x22010A02ull;
+//DUPS: 23010A02,
+static const uint64_t P9N2_EX_2_L2_RAS_STATUS = 0x24010A02ull;
+//DUPS: 25010A02,
+static const uint64_t P9N2_EX_3_L2_RAS_STATUS = 0x26010A02ull;
+//DUPS: 27010A02,
+static const uint64_t P9N2_EX_4_L2_RAS_STATUS = 0x28010A02ull;
+//DUPS: 29010A02,
+static const uint64_t P9N2_EX_5_L2_RAS_STATUS = 0x2A010A02ull;
+//DUPS: 2B010A02,
+static const uint64_t P9N2_EX_6_L2_RAS_STATUS = 0x2C010A02ull;
+//DUPS: 2D010A02,
+static const uint64_t P9N2_EX_7_L2_RAS_STATUS = 0x2F010A02ull;
+//DUPS: 2F010A02,
+static const uint64_t P9N2_EX_8_L2_RAS_STATUS = 0x30010A02ull;
+//DUPS: 31010A02,
+static const uint64_t P9N2_EX_9_L2_RAS_STATUS = 0x32010A02ull;
+//DUPS: 33010A02,
+static const uint64_t P9N2_EX_L2_RAS_STATUS = 0x20010A02ull;
+//DUPS: 21010A02,
+
+static const uint64_t P9N2_EQ_RD_EPS_REG = 0x10010C10ull;
+//DUPS: 10010C10,
+static const uint64_t P9N2_EQ_0_RD_EPS_REG = 0x10010C10ull;
+//DUPS: 10010C10,
+static const uint64_t P9N2_EQ_1_RD_EPS_REG = 0x11010C10ull;
+//DUPS: 11010C10,
+static const uint64_t P9N2_EQ_2_RD_EPS_REG = 0x12010C10ull;
+//DUPS: 12010C10,
+static const uint64_t P9N2_EQ_3_RD_EPS_REG = 0x13010C10ull;
+//DUPS: 13010C10,
+static const uint64_t P9N2_EQ_4_RD_EPS_REG = 0x14010C10ull;
+//DUPS: 14010C10,
+static const uint64_t P9N2_EQ_5_RD_EPS_REG = 0x15010C10ull;
+//DUPS: 15010C10,
+static const uint64_t P9N2_EX_0_L2_RD_EPS_REG = 0x10010810ull;
+
+static const uint64_t P9N2_EX_10_L2_RD_EPS_REG = 0x15010810ull;
+
+static const uint64_t P9N2_EX_11_L2_RD_EPS_REG = 0x15010C10ull;
+
+static const uint64_t P9N2_EX_1_L2_RD_EPS_REG = 0x10010C10ull;
+
+static const uint64_t P9N2_EX_2_L2_RD_EPS_REG = 0x11010810ull;
+
+static const uint64_t P9N2_EX_3_L2_RD_EPS_REG = 0x11010C10ull;
+
+static const uint64_t P9N2_EX_4_L2_RD_EPS_REG = 0x12010810ull;
+
+static const uint64_t P9N2_EX_5_L2_RD_EPS_REG = 0x12010C10ull;
+
+static const uint64_t P9N2_EX_6_L2_RD_EPS_REG = 0x13010810ull;
+
+static const uint64_t P9N2_EX_7_L2_RD_EPS_REG = 0x13010C10ull;
+
+static const uint64_t P9N2_EX_8_L2_RD_EPS_REG = 0x14010810ull;
+
+static const uint64_t P9N2_EX_9_L2_RD_EPS_REG = 0x14010C10ull;
+
+static const uint64_t P9N2_EX_L2_RD_EPS_REG = 0x10010810ull;
+
+
+static const uint64_t P9N2_C_RECOV_FWD_PROG_CTRL = 0x20010A4Bull;
+
+static const uint64_t P9N2_C_0_RECOV_FWD_PROG_CTRL = 0x20010A4Bull;
+
+static const uint64_t P9N2_C_1_RECOV_FWD_PROG_CTRL = 0x21010A4Bull;
+
+static const uint64_t P9N2_C_2_RECOV_FWD_PROG_CTRL = 0x22010A4Bull;
+
+static const uint64_t P9N2_C_3_RECOV_FWD_PROG_CTRL = 0x23010A4Bull;
+
+static const uint64_t P9N2_C_4_RECOV_FWD_PROG_CTRL = 0x24010A4Bull;
+
+static const uint64_t P9N2_C_5_RECOV_FWD_PROG_CTRL = 0x25010A4Bull;
+
+static const uint64_t P9N2_C_6_RECOV_FWD_PROG_CTRL = 0x26010A4Bull;
+
+static const uint64_t P9N2_C_7_RECOV_FWD_PROG_CTRL = 0x27010A4Bull;
+
+static const uint64_t P9N2_C_8_RECOV_FWD_PROG_CTRL = 0x28010A4Bull;
+
+static const uint64_t P9N2_C_9_RECOV_FWD_PROG_CTRL = 0x29010A4Bull;
+
+static const uint64_t P9N2_C_10_RECOV_FWD_PROG_CTRL = 0x2A010A4Bull;
+
+static const uint64_t P9N2_C_11_RECOV_FWD_PROG_CTRL = 0x2B010A4Bull;
+
+static const uint64_t P9N2_C_12_RECOV_FWD_PROG_CTRL = 0x2C010A4Bull;
+
+static const uint64_t P9N2_C_13_RECOV_FWD_PROG_CTRL = 0x2D010A4Bull;
+
+static const uint64_t P9N2_C_14_RECOV_FWD_PROG_CTRL = 0x2E010A4Bull;
+
+static const uint64_t P9N2_C_15_RECOV_FWD_PROG_CTRL = 0x2F010A4Bull;
+
+static const uint64_t P9N2_C_16_RECOV_FWD_PROG_CTRL = 0x30010A4Bull;
+
+static const uint64_t P9N2_C_17_RECOV_FWD_PROG_CTRL = 0x31010A4Bull;
+
+static const uint64_t P9N2_C_18_RECOV_FWD_PROG_CTRL = 0x32010A4Bull;
+
+static const uint64_t P9N2_C_19_RECOV_FWD_PROG_CTRL = 0x33010A4Bull;
+
+static const uint64_t P9N2_C_20_RECOV_FWD_PROG_CTRL = 0x34010A4Bull;
+
+static const uint64_t P9N2_C_21_RECOV_FWD_PROG_CTRL = 0x35010A4Bull;
+
+static const uint64_t P9N2_C_22_RECOV_FWD_PROG_CTRL = 0x36010A4Bull;
+
+static const uint64_t P9N2_C_23_RECOV_FWD_PROG_CTRL = 0x37010A4Bull;
+
+static const uint64_t P9N2_EX_0_L2_RECOV_FWD_PROG_CTRL = 0x20010A4Bull;
+//DUPS: 21010A4B,
+static const uint64_t P9N2_EX_10_L2_RECOV_FWD_PROG_CTRL = 0x34010A4Bull;
+//DUPS: 35010A4B,
+static const uint64_t P9N2_EX_11_L2_RECOV_FWD_PROG_CTRL = 0x36010A4Bull;
+//DUPS: 37010A4B,
+static const uint64_t P9N2_EX_1_L2_RECOV_FWD_PROG_CTRL = 0x22010A4Bull;
+//DUPS: 23010A4B,
+static const uint64_t P9N2_EX_2_L2_RECOV_FWD_PROG_CTRL = 0x24010A4Bull;
+//DUPS: 25010A4B,
+static const uint64_t P9N2_EX_3_L2_RECOV_FWD_PROG_CTRL = 0x26010A4Bull;
+//DUPS: 27010A4B,
+static const uint64_t P9N2_EX_4_L2_RECOV_FWD_PROG_CTRL = 0x28010A4Bull;
+//DUPS: 29010A4B,
+static const uint64_t P9N2_EX_5_L2_RECOV_FWD_PROG_CTRL = 0x2A010A4Bull;
+//DUPS: 2B010A4B,
+static const uint64_t P9N2_EX_6_L2_RECOV_FWD_PROG_CTRL = 0x2C010A4Bull;
+//DUPS: 2D010A4B,
+static const uint64_t P9N2_EX_7_L2_RECOV_FWD_PROG_CTRL = 0x2F010A4Bull;
+//DUPS: 2F010A4B,
+static const uint64_t P9N2_EX_8_L2_RECOV_FWD_PROG_CTRL = 0x30010A4Bull;
+//DUPS: 31010A4B,
+static const uint64_t P9N2_EX_9_L2_RECOV_FWD_PROG_CTRL = 0x32010A4Bull;
+//DUPS: 33010A4B,
+static const uint64_t P9N2_EX_L2_RECOV_FWD_PROG_CTRL = 0x20010A4Bull;
+//DUPS: 21010A4B,
+
+static const uint64_t P9N2_C_RECOV_INTERRUPT_REG = 0x200F001Bull;
+
+static const uint64_t P9N2_C_0_RECOV_INTERRUPT_REG = 0x200F001Bull;
+
+static const uint64_t P9N2_C_1_RECOV_INTERRUPT_REG = 0x210F001Bull;
+
+static const uint64_t P9N2_C_2_RECOV_INTERRUPT_REG = 0x220F001Bull;
+
+static const uint64_t P9N2_C_3_RECOV_INTERRUPT_REG = 0x230F001Bull;
+
+static const uint64_t P9N2_C_4_RECOV_INTERRUPT_REG = 0x240F001Bull;
+
+static const uint64_t P9N2_C_5_RECOV_INTERRUPT_REG = 0x250F001Bull;
+
+static const uint64_t P9N2_C_6_RECOV_INTERRUPT_REG = 0x260F001Bull;
+
+static const uint64_t P9N2_C_7_RECOV_INTERRUPT_REG = 0x270F001Bull;
+
+static const uint64_t P9N2_C_8_RECOV_INTERRUPT_REG = 0x280F001Bull;
+
+static const uint64_t P9N2_C_9_RECOV_INTERRUPT_REG = 0x290F001Bull;
+
+static const uint64_t P9N2_C_10_RECOV_INTERRUPT_REG = 0x2A0F001Bull;
+
+static const uint64_t P9N2_C_11_RECOV_INTERRUPT_REG = 0x2B0F001Bull;
+
+static const uint64_t P9N2_C_12_RECOV_INTERRUPT_REG = 0x2C0F001Bull;
+
+static const uint64_t P9N2_C_13_RECOV_INTERRUPT_REG = 0x2D0F001Bull;
+
+static const uint64_t P9N2_C_14_RECOV_INTERRUPT_REG = 0x2E0F001Bull;
+
+static const uint64_t P9N2_C_15_RECOV_INTERRUPT_REG = 0x2F0F001Bull;
+
+static const uint64_t P9N2_C_16_RECOV_INTERRUPT_REG = 0x300F001Bull;
+
+static const uint64_t P9N2_C_17_RECOV_INTERRUPT_REG = 0x310F001Bull;
+
+static const uint64_t P9N2_C_18_RECOV_INTERRUPT_REG = 0x320F001Bull;
+
+static const uint64_t P9N2_C_19_RECOV_INTERRUPT_REG = 0x330F001Bull;
+
+static const uint64_t P9N2_C_20_RECOV_INTERRUPT_REG = 0x340F001Bull;
+
+static const uint64_t P9N2_C_21_RECOV_INTERRUPT_REG = 0x350F001Bull;
+
+static const uint64_t P9N2_C_22_RECOV_INTERRUPT_REG = 0x360F001Bull;
+
+static const uint64_t P9N2_C_23_RECOV_INTERRUPT_REG = 0x370F001Bull;
+
+static const uint64_t P9N2_EQ_RECOV_INTERRUPT_REG = 0x100F001Bull;
+
+static const uint64_t P9N2_EQ_0_RECOV_INTERRUPT_REG = 0x100F001Bull;
+
+static const uint64_t P9N2_EQ_1_RECOV_INTERRUPT_REG = 0x110F001Bull;
+
+static const uint64_t P9N2_EQ_2_RECOV_INTERRUPT_REG = 0x120F001Bull;
+
+static const uint64_t P9N2_EQ_3_RECOV_INTERRUPT_REG = 0x130F001Bull;
+
+static const uint64_t P9N2_EQ_4_RECOV_INTERRUPT_REG = 0x140F001Bull;
+
+static const uint64_t P9N2_EQ_5_RECOV_INTERRUPT_REG = 0x150F001Bull;
+
+static const uint64_t P9N2_EX_RECOV_INTERRUPT_REG = 0x200F001Bull;
+//DUPS: 210F001B,
+static const uint64_t P9N2_EX_0_RECOV_INTERRUPT_REG = 0x200F001Bull;
+//DUPS: 210F001B,
+static const uint64_t P9N2_EX_1_RECOV_INTERRUPT_REG = 0x220F001Bull;
+//DUPS: 220F001B,
+static const uint64_t P9N2_EX_2_RECOV_INTERRUPT_REG = 0x240F001Bull;
+//DUPS: 250F001B,
+static const uint64_t P9N2_EX_3_RECOV_INTERRUPT_REG = 0x260F001Bull;
+//DUPS: 270F001B,
+static const uint64_t P9N2_EX_4_RECOV_INTERRUPT_REG = 0x280F001Bull;
+//DUPS: 290F001B,
+static const uint64_t P9N2_EX_5_RECOV_INTERRUPT_REG = 0x2A0F001Bull;
+//DUPS: 2B0F001B,
+static const uint64_t P9N2_EX_6_RECOV_INTERRUPT_REG = 0x2C0F001Bull;
+//DUPS: 2D0F001B,
+static const uint64_t P9N2_EX_7_RECOV_INTERRUPT_REG = 0x2E0F001Bull;
+//DUPS: 2F0F001B,
+static const uint64_t P9N2_EX_8_RECOV_INTERRUPT_REG = 0x300F001Bull;
+//DUPS: 310F001B,
+static const uint64_t P9N2_EX_9_RECOV_INTERRUPT_REG = 0x320F001Bull;
+//DUPS: 330F001B,
+static const uint64_t P9N2_EX_10_RECOV_INTERRUPT_REG = 0x340F001Bull;
+//DUPS: 350F001B,
+static const uint64_t P9N2_EX_11_RECOV_INTERRUPT_REG = 0x360F001Bull;
+//DUPS: 370F001B,
+
+static const uint64_t P9N2_C_RECOV_THOLD = 0x20010A4Cull;
+
+static const uint64_t P9N2_C_0_RECOV_THOLD = 0x20010A4Cull;
+
+static const uint64_t P9N2_C_1_RECOV_THOLD = 0x21010A4Cull;
+
+static const uint64_t P9N2_C_2_RECOV_THOLD = 0x22010A4Cull;
+
+static const uint64_t P9N2_C_3_RECOV_THOLD = 0x23010A4Cull;
+
+static const uint64_t P9N2_C_4_RECOV_THOLD = 0x24010A4Cull;
+
+static const uint64_t P9N2_C_5_RECOV_THOLD = 0x25010A4Cull;
+
+static const uint64_t P9N2_C_6_RECOV_THOLD = 0x26010A4Cull;
+
+static const uint64_t P9N2_C_7_RECOV_THOLD = 0x27010A4Cull;
+
+static const uint64_t P9N2_C_8_RECOV_THOLD = 0x28010A4Cull;
+
+static const uint64_t P9N2_C_9_RECOV_THOLD = 0x29010A4Cull;
+
+static const uint64_t P9N2_C_10_RECOV_THOLD = 0x2A010A4Cull;
+
+static const uint64_t P9N2_C_11_RECOV_THOLD = 0x2B010A4Cull;
+
+static const uint64_t P9N2_C_12_RECOV_THOLD = 0x2C010A4Cull;
+
+static const uint64_t P9N2_C_13_RECOV_THOLD = 0x2D010A4Cull;
+
+static const uint64_t P9N2_C_14_RECOV_THOLD = 0x2E010A4Cull;
+
+static const uint64_t P9N2_C_15_RECOV_THOLD = 0x2F010A4Cull;
+
+static const uint64_t P9N2_C_16_RECOV_THOLD = 0x30010A4Cull;
+
+static const uint64_t P9N2_C_17_RECOV_THOLD = 0x31010A4Cull;
+
+static const uint64_t P9N2_C_18_RECOV_THOLD = 0x32010A4Cull;
+
+static const uint64_t P9N2_C_19_RECOV_THOLD = 0x33010A4Cull;
+
+static const uint64_t P9N2_C_20_RECOV_THOLD = 0x34010A4Cull;
+
+static const uint64_t P9N2_C_21_RECOV_THOLD = 0x35010A4Cull;
+
+static const uint64_t P9N2_C_22_RECOV_THOLD = 0x36010A4Cull;
+
+static const uint64_t P9N2_C_23_RECOV_THOLD = 0x37010A4Cull;
+
+static const uint64_t P9N2_EX_0_L2_RECOV_THOLD = 0x20010A4Cull;
+//DUPS: 21010A4C,
+static const uint64_t P9N2_EX_10_L2_RECOV_THOLD = 0x34010A4Cull;
+//DUPS: 35010A4C,
+static const uint64_t P9N2_EX_11_L2_RECOV_THOLD = 0x36010A4Cull;
+//DUPS: 37010A4C,
+static const uint64_t P9N2_EX_1_L2_RECOV_THOLD = 0x22010A4Cull;
+//DUPS: 23010A4C,
+static const uint64_t P9N2_EX_2_L2_RECOV_THOLD = 0x24010A4Cull;
+//DUPS: 25010A4C,
+static const uint64_t P9N2_EX_3_L2_RECOV_THOLD = 0x26010A4Cull;
+//DUPS: 27010A4C,
+static const uint64_t P9N2_EX_4_L2_RECOV_THOLD = 0x28010A4Cull;
+//DUPS: 29010A4C,
+static const uint64_t P9N2_EX_5_L2_RECOV_THOLD = 0x2A010A4Cull;
+//DUPS: 2B010A4C,
+static const uint64_t P9N2_EX_6_L2_RECOV_THOLD = 0x2C010A4Cull;
+//DUPS: 2D010A4C,
+static const uint64_t P9N2_EX_7_L2_RECOV_THOLD = 0x2F010A4Cull;
+//DUPS: 2F010A4C,
+static const uint64_t P9N2_EX_8_L2_RECOV_THOLD = 0x30010A4Cull;
+//DUPS: 31010A4C,
+static const uint64_t P9N2_EX_9_L2_RECOV_THOLD = 0x32010A4Cull;
+//DUPS: 33010A4C,
+static const uint64_t P9N2_EX_L2_RECOV_THOLD = 0x20010A4Cull;
+//DUPS: 21010A4C,
+
+static const uint64_t P9N2_C_RESET_KEEPER = 0x20010A4Aull;
+
+static const uint64_t P9N2_C_0_RESET_KEEPER = 0x20010A4Aull;
+
+static const uint64_t P9N2_C_1_RESET_KEEPER = 0x21010A4Aull;
+
+static const uint64_t P9N2_C_2_RESET_KEEPER = 0x22010A4Aull;
+
+static const uint64_t P9N2_C_3_RESET_KEEPER = 0x23010A4Aull;
+
+static const uint64_t P9N2_C_4_RESET_KEEPER = 0x24010A4Aull;
+
+static const uint64_t P9N2_C_5_RESET_KEEPER = 0x25010A4Aull;
+
+static const uint64_t P9N2_C_6_RESET_KEEPER = 0x26010A4Aull;
+
+static const uint64_t P9N2_C_7_RESET_KEEPER = 0x27010A4Aull;
+
+static const uint64_t P9N2_C_8_RESET_KEEPER = 0x28010A4Aull;
+
+static const uint64_t P9N2_C_9_RESET_KEEPER = 0x29010A4Aull;
+
+static const uint64_t P9N2_C_10_RESET_KEEPER = 0x2A010A4Aull;
+
+static const uint64_t P9N2_C_11_RESET_KEEPER = 0x2B010A4Aull;
+
+static const uint64_t P9N2_C_12_RESET_KEEPER = 0x2C010A4Aull;
+
+static const uint64_t P9N2_C_13_RESET_KEEPER = 0x2D010A4Aull;
+
+static const uint64_t P9N2_C_14_RESET_KEEPER = 0x2E010A4Aull;
+
+static const uint64_t P9N2_C_15_RESET_KEEPER = 0x2F010A4Aull;
+
+static const uint64_t P9N2_C_16_RESET_KEEPER = 0x30010A4Aull;
+
+static const uint64_t P9N2_C_17_RESET_KEEPER = 0x31010A4Aull;
+
+static const uint64_t P9N2_C_18_RESET_KEEPER = 0x32010A4Aull;
+
+static const uint64_t P9N2_C_19_RESET_KEEPER = 0x33010A4Aull;
+
+static const uint64_t P9N2_C_20_RESET_KEEPER = 0x34010A4Aull;
+
+static const uint64_t P9N2_C_21_RESET_KEEPER = 0x35010A4Aull;
+
+static const uint64_t P9N2_C_22_RESET_KEEPER = 0x36010A4Aull;
+
+static const uint64_t P9N2_C_23_RESET_KEEPER = 0x37010A4Aull;
+
+static const uint64_t P9N2_EX_0_L2_RESET_KEEPER = 0x20010A4Aull;
+//DUPS: 21010A4A,
+static const uint64_t P9N2_EX_10_L2_RESET_KEEPER = 0x34010A4Aull;
+//DUPS: 35010A4A,
+static const uint64_t P9N2_EX_11_L2_RESET_KEEPER = 0x36010A4Aull;
+//DUPS: 37010A4A,
+static const uint64_t P9N2_EX_1_L2_RESET_KEEPER = 0x22010A4Aull;
+//DUPS: 23010A4A,
+static const uint64_t P9N2_EX_2_L2_RESET_KEEPER = 0x24010A4Aull;
+//DUPS: 25010A4A,
+static const uint64_t P9N2_EX_3_L2_RESET_KEEPER = 0x26010A4Aull;
+//DUPS: 27010A4A,
+static const uint64_t P9N2_EX_4_L2_RESET_KEEPER = 0x28010A4Aull;
+//DUPS: 29010A4A,
+static const uint64_t P9N2_EX_5_L2_RESET_KEEPER = 0x2A010A4Aull;
+//DUPS: 2B010A4A,
+static const uint64_t P9N2_EX_6_L2_RESET_KEEPER = 0x2C010A4Aull;
+//DUPS: 2D010A4A,
+static const uint64_t P9N2_EX_7_L2_RESET_KEEPER = 0x2F010A4Aull;
+//DUPS: 2F010A4A,
+static const uint64_t P9N2_EX_8_L2_RESET_KEEPER = 0x30010A4Aull;
+//DUPS: 31010A4A,
+static const uint64_t P9N2_EX_9_L2_RESET_KEEPER = 0x32010A4Aull;
+//DUPS: 33010A4A,
+static const uint64_t P9N2_EX_L2_RESET_KEEPER = 0x20010A4Aull;
+//DUPS: 21010A4A,
+
+static const uint64_t P9N2_C_RFIR = 0x20040001ull;
+
+static const uint64_t P9N2_C_0_RFIR = 0x20040001ull;
+
+static const uint64_t P9N2_C_1_RFIR = 0x21040001ull;
+
+static const uint64_t P9N2_C_2_RFIR = 0x22040001ull;
+
+static const uint64_t P9N2_C_3_RFIR = 0x23040001ull;
+
+static const uint64_t P9N2_C_4_RFIR = 0x24040001ull;
+
+static const uint64_t P9N2_C_5_RFIR = 0x25040001ull;
+
+static const uint64_t P9N2_C_6_RFIR = 0x26040001ull;
+
+static const uint64_t P9N2_C_7_RFIR = 0x27040001ull;
+
+static const uint64_t P9N2_C_8_RFIR = 0x28040001ull;
+
+static const uint64_t P9N2_C_9_RFIR = 0x29040001ull;
+
+static const uint64_t P9N2_C_10_RFIR = 0x2A040001ull;
+
+static const uint64_t P9N2_C_11_RFIR = 0x2B040001ull;
+
+static const uint64_t P9N2_C_12_RFIR = 0x2C040001ull;
+
+static const uint64_t P9N2_C_13_RFIR = 0x2D040001ull;
+
+static const uint64_t P9N2_C_14_RFIR = 0x2E040001ull;
+
+static const uint64_t P9N2_C_15_RFIR = 0x2F040001ull;
+
+static const uint64_t P9N2_C_16_RFIR = 0x30040001ull;
+
+static const uint64_t P9N2_C_17_RFIR = 0x31040001ull;
+
+static const uint64_t P9N2_C_18_RFIR = 0x32040001ull;
+
+static const uint64_t P9N2_C_19_RFIR = 0x33040001ull;
+
+static const uint64_t P9N2_C_20_RFIR = 0x34040001ull;
+
+static const uint64_t P9N2_C_21_RFIR = 0x35040001ull;
+
+static const uint64_t P9N2_C_22_RFIR = 0x36040001ull;
+
+static const uint64_t P9N2_C_23_RFIR = 0x37040001ull;
+
+static const uint64_t P9N2_EQ_RFIR = 0x10040001ull;
+
+static const uint64_t P9N2_EQ_0_RFIR = 0x10040001ull;
+
+static const uint64_t P9N2_EQ_1_RFIR = 0x11040001ull;
+
+static const uint64_t P9N2_EQ_2_RFIR = 0x12040001ull;
+
+static const uint64_t P9N2_EQ_3_RFIR = 0x13040001ull;
+
+static const uint64_t P9N2_EQ_4_RFIR = 0x14040001ull;
+
+static const uint64_t P9N2_EQ_5_RFIR = 0x15040001ull;
+
+static const uint64_t P9N2_EX_RFIR = 0x20040001ull;
+//DUPS: 21040001,
+static const uint64_t P9N2_EX_0_RFIR = 0x20040001ull;
+//DUPS: 21040001,
+static const uint64_t P9N2_EX_1_RFIR = 0x22040001ull;
+//DUPS: 23040001,
+static const uint64_t P9N2_EX_2_RFIR = 0x24040001ull;
+//DUPS: 25040001,
+static const uint64_t P9N2_EX_3_RFIR = 0x26040001ull;
+//DUPS: 27040001,
+static const uint64_t P9N2_EX_4_RFIR = 0x28040001ull;
+//DUPS: 29040001,
+static const uint64_t P9N2_EX_5_RFIR = 0x2A040001ull;
+//DUPS: 2B040001,
+static const uint64_t P9N2_EX_6_RFIR = 0x2C040001ull;
+//DUPS: 2D040001,
+static const uint64_t P9N2_EX_7_RFIR = 0x2F040001ull;
+//DUPS: 2F040001,
+static const uint64_t P9N2_EX_8_RFIR = 0x30040001ull;
+//DUPS: 31040001,
+static const uint64_t P9N2_EX_9_RFIR = 0x32040001ull;
+//DUPS: 33040001,
+static const uint64_t P9N2_EX_10_RFIR = 0x34040001ull;
+//DUPS: 35040001,
+static const uint64_t P9N2_EX_11_RFIR = 0x36040001ull;
+//DUPS: 37040001,
+
+static const uint64_t P9N2_C_RING_FENCE_MASK_LATCH_REG = 0x20010008ull;
+
+static const uint64_t P9N2_C_0_RING_FENCE_MASK_LATCH_REG = 0x20010008ull;
+
+static const uint64_t P9N2_C_1_RING_FENCE_MASK_LATCH_REG = 0x21010008ull;
+
+static const uint64_t P9N2_C_2_RING_FENCE_MASK_LATCH_REG = 0x22010008ull;
+
+static const uint64_t P9N2_C_3_RING_FENCE_MASK_LATCH_REG = 0x23010008ull;
+
+static const uint64_t P9N2_C_4_RING_FENCE_MASK_LATCH_REG = 0x24010008ull;
+
+static const uint64_t P9N2_C_5_RING_FENCE_MASK_LATCH_REG = 0x25010008ull;
+
+static const uint64_t P9N2_C_6_RING_FENCE_MASK_LATCH_REG = 0x26010008ull;
+
+static const uint64_t P9N2_C_7_RING_FENCE_MASK_LATCH_REG = 0x27010008ull;
+
+static const uint64_t P9N2_C_8_RING_FENCE_MASK_LATCH_REG = 0x28010008ull;
+
+static const uint64_t P9N2_C_9_RING_FENCE_MASK_LATCH_REG = 0x29010008ull;
+
+static const uint64_t P9N2_C_10_RING_FENCE_MASK_LATCH_REG = 0x2A010008ull;
+
+static const uint64_t P9N2_C_11_RING_FENCE_MASK_LATCH_REG = 0x2B010008ull;
+
+static const uint64_t P9N2_C_12_RING_FENCE_MASK_LATCH_REG = 0x2C010008ull;
+
+static const uint64_t P9N2_C_13_RING_FENCE_MASK_LATCH_REG = 0x2D010008ull;
+
+static const uint64_t P9N2_C_14_RING_FENCE_MASK_LATCH_REG = 0x2E010008ull;
+
+static const uint64_t P9N2_C_15_RING_FENCE_MASK_LATCH_REG = 0x2F010008ull;
+
+static const uint64_t P9N2_C_16_RING_FENCE_MASK_LATCH_REG = 0x30010008ull;
+
+static const uint64_t P9N2_C_17_RING_FENCE_MASK_LATCH_REG = 0x31010008ull;
+
+static const uint64_t P9N2_C_18_RING_FENCE_MASK_LATCH_REG = 0x32010008ull;
+
+static const uint64_t P9N2_C_19_RING_FENCE_MASK_LATCH_REG = 0x33010008ull;
+
+static const uint64_t P9N2_C_20_RING_FENCE_MASK_LATCH_REG = 0x34010008ull;
+
+static const uint64_t P9N2_C_21_RING_FENCE_MASK_LATCH_REG = 0x35010008ull;
+
+static const uint64_t P9N2_C_22_RING_FENCE_MASK_LATCH_REG = 0x36010008ull;
+
+static const uint64_t P9N2_C_23_RING_FENCE_MASK_LATCH_REG = 0x37010008ull;
+
+static const uint64_t P9N2_EQ_RING_FENCE_MASK_LATCH_REG = 0x10010008ull;
+
+static const uint64_t P9N2_EQ_0_RING_FENCE_MASK_LATCH_REG = 0x10010008ull;
+
+static const uint64_t P9N2_EQ_1_RING_FENCE_MASK_LATCH_REG = 0x11010008ull;
+
+static const uint64_t P9N2_EQ_2_RING_FENCE_MASK_LATCH_REG = 0x12010008ull;
+
+static const uint64_t P9N2_EQ_3_RING_FENCE_MASK_LATCH_REG = 0x13010008ull;
+
+static const uint64_t P9N2_EQ_4_RING_FENCE_MASK_LATCH_REG = 0x14010008ull;
+
+static const uint64_t P9N2_EQ_5_RING_FENCE_MASK_LATCH_REG = 0x15010008ull;
+
+static const uint64_t P9N2_EX_RING_FENCE_MASK_LATCH_REG = 0x20010008ull;
+//DUPS: 21010008,
+static const uint64_t P9N2_EX_0_RING_FENCE_MASK_LATCH_REG = 0x20010008ull;
+//DUPS: 21010008,
+static const uint64_t P9N2_EX_1_RING_FENCE_MASK_LATCH_REG = 0x22010008ull;
+//DUPS: 23010008,
+static const uint64_t P9N2_EX_2_RING_FENCE_MASK_LATCH_REG = 0x24010008ull;
+//DUPS: 25010008,
+static const uint64_t P9N2_EX_3_RING_FENCE_MASK_LATCH_REG = 0x26010008ull;
+//DUPS: 27010008,
+static const uint64_t P9N2_EX_4_RING_FENCE_MASK_LATCH_REG = 0x28010008ull;
+//DUPS: 29010008,
+static const uint64_t P9N2_EX_5_RING_FENCE_MASK_LATCH_REG = 0x2A010008ull;
+//DUPS: 2B010008,
+static const uint64_t P9N2_EX_6_RING_FENCE_MASK_LATCH_REG = 0x2C010008ull;
+//DUPS: 2D010008,
+static const uint64_t P9N2_EX_7_RING_FENCE_MASK_LATCH_REG = 0x2F010008ull;
+//DUPS: 2F010008,
+static const uint64_t P9N2_EX_8_RING_FENCE_MASK_LATCH_REG = 0x30010008ull;
+//DUPS: 31010008,
+static const uint64_t P9N2_EX_9_RING_FENCE_MASK_LATCH_REG = 0x32010008ull;
+//DUPS: 33010008,
+static const uint64_t P9N2_EX_10_RING_FENCE_MASK_LATCH_REG = 0x34010008ull;
+//DUPS: 35010008,
+static const uint64_t P9N2_EX_11_RING_FENCE_MASK_LATCH_REG = 0x36010008ull;
+//DUPS: 37010008,
+
+static const uint64_t P9N2_C_SCAN32 = 0x20038000ull;
+
+static const uint64_t P9N2_C_0_SCAN32 = 0x20038000ull;
+
+static const uint64_t P9N2_C_1_SCAN32 = 0x21038000ull;
+
+static const uint64_t P9N2_C_2_SCAN32 = 0x22038000ull;
+
+static const uint64_t P9N2_C_3_SCAN32 = 0x23038000ull;
+
+static const uint64_t P9N2_C_4_SCAN32 = 0x24038000ull;
+
+static const uint64_t P9N2_C_5_SCAN32 = 0x25038000ull;
+
+static const uint64_t P9N2_C_6_SCAN32 = 0x26038000ull;
+
+static const uint64_t P9N2_C_7_SCAN32 = 0x27038000ull;
+
+static const uint64_t P9N2_C_8_SCAN32 = 0x28038000ull;
+
+static const uint64_t P9N2_C_9_SCAN32 = 0x29038000ull;
+
+static const uint64_t P9N2_C_10_SCAN32 = 0x2A038000ull;
+
+static const uint64_t P9N2_C_11_SCAN32 = 0x2B038000ull;
+
+static const uint64_t P9N2_C_12_SCAN32 = 0x2C038000ull;
+
+static const uint64_t P9N2_C_13_SCAN32 = 0x2D038000ull;
+
+static const uint64_t P9N2_C_14_SCAN32 = 0x2E038000ull;
+
+static const uint64_t P9N2_C_15_SCAN32 = 0x2F038000ull;
+
+static const uint64_t P9N2_C_16_SCAN32 = 0x30038000ull;
+
+static const uint64_t P9N2_C_17_SCAN32 = 0x31038000ull;
+
+static const uint64_t P9N2_C_18_SCAN32 = 0x32038000ull;
+
+static const uint64_t P9N2_C_19_SCAN32 = 0x33038000ull;
+
+static const uint64_t P9N2_C_20_SCAN32 = 0x34038000ull;
+
+static const uint64_t P9N2_C_21_SCAN32 = 0x35038000ull;
+
+static const uint64_t P9N2_C_22_SCAN32 = 0x36038000ull;
+
+static const uint64_t P9N2_C_23_SCAN32 = 0x37038000ull;
+
+static const uint64_t P9N2_EQ_SCAN32 = 0x10038000ull;
+
+static const uint64_t P9N2_EQ_0_SCAN32 = 0x10038000ull;
+
+static const uint64_t P9N2_EQ_1_SCAN32 = 0x11038000ull;
+
+static const uint64_t P9N2_EQ_2_SCAN32 = 0x12038000ull;
+
+static const uint64_t P9N2_EQ_3_SCAN32 = 0x13038000ull;
+
+static const uint64_t P9N2_EQ_4_SCAN32 = 0x14038000ull;
+
+static const uint64_t P9N2_EQ_5_SCAN32 = 0x15038000ull;
+
+static const uint64_t P9N2_EX_SCAN32 = 0x20038000ull;
+//DUPS: 21038000,
+static const uint64_t P9N2_EX_0_SCAN32 = 0x20038000ull;
+//DUPS: 21038000,
+static const uint64_t P9N2_EX_1_SCAN32 = 0x22038000ull;
+//DUPS: 23038000,
+static const uint64_t P9N2_EX_2_SCAN32 = 0x24038000ull;
+//DUPS: 25038000,
+static const uint64_t P9N2_EX_3_SCAN32 = 0x26038000ull;
+//DUPS: 27038000,
+static const uint64_t P9N2_EX_4_SCAN32 = 0x28038000ull;
+//DUPS: 29038000,
+static const uint64_t P9N2_EX_5_SCAN32 = 0x2A038000ull;
+//DUPS: 2B038000,
+static const uint64_t P9N2_EX_6_SCAN32 = 0x2C038000ull;
+//DUPS: 2D038000,
+static const uint64_t P9N2_EX_7_SCAN32 = 0x2F038000ull;
+//DUPS: 2F038000,
+static const uint64_t P9N2_EX_8_SCAN32 = 0x30038000ull;
+//DUPS: 31038000,
+static const uint64_t P9N2_EX_9_SCAN32 = 0x32038000ull;
+//DUPS: 33038000,
+static const uint64_t P9N2_EX_10_SCAN32 = 0x34038000ull;
+//DUPS: 35038000,
+static const uint64_t P9N2_EX_11_SCAN32 = 0x36038000ull;
+//DUPS: 37038000,
+
+static const uint64_t P9N2_C_SCAN64 = 0x2003E000ull;
+
+static const uint64_t P9N2_C_0_SCAN64 = 0x2003E000ull;
+
+static const uint64_t P9N2_C_1_SCAN64 = 0x2103E000ull;
+
+static const uint64_t P9N2_C_2_SCAN64 = 0x2203E000ull;
+
+static const uint64_t P9N2_C_3_SCAN64 = 0x2303E000ull;
+
+static const uint64_t P9N2_C_4_SCAN64 = 0x2403E000ull;
+
+static const uint64_t P9N2_C_5_SCAN64 = 0x2503E000ull;
+
+static const uint64_t P9N2_C_6_SCAN64 = 0x2603E000ull;
+
+static const uint64_t P9N2_C_7_SCAN64 = 0x2703E000ull;
+
+static const uint64_t P9N2_C_8_SCAN64 = 0x2803E000ull;
+
+static const uint64_t P9N2_C_9_SCAN64 = 0x2903E000ull;
+
+static const uint64_t P9N2_C_10_SCAN64 = 0x2A03E000ull;
+
+static const uint64_t P9N2_C_11_SCAN64 = 0x2B03E000ull;
+
+static const uint64_t P9N2_C_12_SCAN64 = 0x2C03E000ull;
+
+static const uint64_t P9N2_C_13_SCAN64 = 0x2D03E000ull;
+
+static const uint64_t P9N2_C_14_SCAN64 = 0x2E03E000ull;
+
+static const uint64_t P9N2_C_15_SCAN64 = 0x2F03E000ull;
+
+static const uint64_t P9N2_C_16_SCAN64 = 0x3003E000ull;
+
+static const uint64_t P9N2_C_17_SCAN64 = 0x3103E000ull;
+
+static const uint64_t P9N2_C_18_SCAN64 = 0x3203E000ull;
+
+static const uint64_t P9N2_C_19_SCAN64 = 0x3303E000ull;
+
+static const uint64_t P9N2_C_20_SCAN64 = 0x3403E000ull;
+
+static const uint64_t P9N2_C_21_SCAN64 = 0x3503E000ull;
+
+static const uint64_t P9N2_C_22_SCAN64 = 0x3603E000ull;
+
+static const uint64_t P9N2_C_23_SCAN64 = 0x3703E000ull;
+
+static const uint64_t P9N2_EQ_SCAN64 = 0x1003E000ull;
+
+static const uint64_t P9N2_EQ_0_SCAN64 = 0x1003E000ull;
+
+static const uint64_t P9N2_EQ_1_SCAN64 = 0x1103E000ull;
+
+static const uint64_t P9N2_EQ_2_SCAN64 = 0x1203E000ull;
+
+static const uint64_t P9N2_EQ_3_SCAN64 = 0x1303E000ull;
+
+static const uint64_t P9N2_EQ_4_SCAN64 = 0x1403E000ull;
+
+static const uint64_t P9N2_EQ_5_SCAN64 = 0x1503E000ull;
+
+static const uint64_t P9N2_EX_SCAN64 = 0x2003E000ull;
+//DUPS: 2103E000,
+static const uint64_t P9N2_EX_0_SCAN64 = 0x2003E000ull;
+//DUPS: 2103E000,
+static const uint64_t P9N2_EX_1_SCAN64 = 0x2203E000ull;
+//DUPS: 2303E000,
+static const uint64_t P9N2_EX_2_SCAN64 = 0x2403E000ull;
+//DUPS: 2503E000,
+static const uint64_t P9N2_EX_3_SCAN64 = 0x2603E000ull;
+//DUPS: 2703E000,
+static const uint64_t P9N2_EX_4_SCAN64 = 0x2803E000ull;
+//DUPS: 2903E000,
+static const uint64_t P9N2_EX_5_SCAN64 = 0x2A03E000ull;
+//DUPS: 2B03E000,
+static const uint64_t P9N2_EX_6_SCAN64 = 0x2C03E000ull;
+//DUPS: 2D03E000,
+static const uint64_t P9N2_EX_7_SCAN64 = 0x2F03E000ull;
+//DUPS: 2F03E000,
+static const uint64_t P9N2_EX_8_SCAN64 = 0x3003E000ull;
+//DUPS: 3103E000,
+static const uint64_t P9N2_EX_9_SCAN64 = 0x3203E000ull;
+//DUPS: 3303E000,
+static const uint64_t P9N2_EX_10_SCAN64 = 0x3403E000ull;
+//DUPS: 3503E000,
+static const uint64_t P9N2_EX_11_SCAN64 = 0x3603E000ull;
+//DUPS: 3703E000,
+
+static const uint64_t P9N2_C_SCAN_CAPTUREDR = 0x2003C000ull;
+
+static const uint64_t P9N2_C_0_SCAN_CAPTUREDR = 0x2003C000ull;
+
+static const uint64_t P9N2_C_1_SCAN_CAPTUREDR = 0x2103C000ull;
+
+static const uint64_t P9N2_C_2_SCAN_CAPTUREDR = 0x2203C000ull;
+
+static const uint64_t P9N2_C_3_SCAN_CAPTUREDR = 0x2303C000ull;
+
+static const uint64_t P9N2_C_4_SCAN_CAPTUREDR = 0x2403C000ull;
+
+static const uint64_t P9N2_C_5_SCAN_CAPTUREDR = 0x2503C000ull;
+
+static const uint64_t P9N2_C_6_SCAN_CAPTUREDR = 0x2603C000ull;
+
+static const uint64_t P9N2_C_7_SCAN_CAPTUREDR = 0x2703C000ull;
+
+static const uint64_t P9N2_C_8_SCAN_CAPTUREDR = 0x2803C000ull;
+
+static const uint64_t P9N2_C_9_SCAN_CAPTUREDR = 0x2903C000ull;
+
+static const uint64_t P9N2_C_10_SCAN_CAPTUREDR = 0x2A03C000ull;
+
+static const uint64_t P9N2_C_11_SCAN_CAPTUREDR = 0x2B03C000ull;
+
+static const uint64_t P9N2_C_12_SCAN_CAPTUREDR = 0x2C03C000ull;
+
+static const uint64_t P9N2_C_13_SCAN_CAPTUREDR = 0x2D03C000ull;
+
+static const uint64_t P9N2_C_14_SCAN_CAPTUREDR = 0x2E03C000ull;
+
+static const uint64_t P9N2_C_15_SCAN_CAPTUREDR = 0x2F03C000ull;
+
+static const uint64_t P9N2_C_16_SCAN_CAPTUREDR = 0x3003C000ull;
+
+static const uint64_t P9N2_C_17_SCAN_CAPTUREDR = 0x3103C000ull;
+
+static const uint64_t P9N2_C_18_SCAN_CAPTUREDR = 0x3203C000ull;
+
+static const uint64_t P9N2_C_19_SCAN_CAPTUREDR = 0x3303C000ull;
+
+static const uint64_t P9N2_C_20_SCAN_CAPTUREDR = 0x3403C000ull;
+
+static const uint64_t P9N2_C_21_SCAN_CAPTUREDR = 0x3503C000ull;
+
+static const uint64_t P9N2_C_22_SCAN_CAPTUREDR = 0x3603C000ull;
+
+static const uint64_t P9N2_C_23_SCAN_CAPTUREDR = 0x3703C000ull;
+
+static const uint64_t P9N2_EQ_SCAN_CAPTUREDR = 0x1003C000ull;
+
+static const uint64_t P9N2_EQ_0_SCAN_CAPTUREDR = 0x1003C000ull;
+
+static const uint64_t P9N2_EQ_1_SCAN_CAPTUREDR = 0x1103C000ull;
+
+static const uint64_t P9N2_EQ_2_SCAN_CAPTUREDR = 0x1203C000ull;
+
+static const uint64_t P9N2_EQ_3_SCAN_CAPTUREDR = 0x1303C000ull;
+
+static const uint64_t P9N2_EQ_4_SCAN_CAPTUREDR = 0x1403C000ull;
+
+static const uint64_t P9N2_EQ_5_SCAN_CAPTUREDR = 0x1503C000ull;
+
+static const uint64_t P9N2_EX_SCAN_CAPTUREDR = 0x2003C000ull;
+//DUPS: 2103C000,
+static const uint64_t P9N2_EX_0_SCAN_CAPTUREDR = 0x2003C000ull;
+//DUPS: 2103C000,
+static const uint64_t P9N2_EX_1_SCAN_CAPTUREDR = 0x2203C000ull;
+//DUPS: 2303C000,
+static const uint64_t P9N2_EX_2_SCAN_CAPTUREDR = 0x2403C000ull;
+//DUPS: 2503C000,
+static const uint64_t P9N2_EX_3_SCAN_CAPTUREDR = 0x2603C000ull;
+//DUPS: 2703C000,
+static const uint64_t P9N2_EX_4_SCAN_CAPTUREDR = 0x2803C000ull;
+//DUPS: 2903C000,
+static const uint64_t P9N2_EX_5_SCAN_CAPTUREDR = 0x2A03C000ull;
+//DUPS: 2B03C000,
+static const uint64_t P9N2_EX_6_SCAN_CAPTUREDR = 0x2C03C000ull;
+//DUPS: 2D03C000,
+static const uint64_t P9N2_EX_7_SCAN_CAPTUREDR = 0x2F03C000ull;
+//DUPS: 2F03C000,
+static const uint64_t P9N2_EX_8_SCAN_CAPTUREDR = 0x3003C000ull;
+//DUPS: 3103C000,
+static const uint64_t P9N2_EX_9_SCAN_CAPTUREDR = 0x3203C000ull;
+//DUPS: 3303C000,
+static const uint64_t P9N2_EX_10_SCAN_CAPTUREDR = 0x3403C000ull;
+//DUPS: 3503C000,
+static const uint64_t P9N2_EX_11_SCAN_CAPTUREDR = 0x3603C000ull;
+//DUPS: 3703C000,
+
+static const uint64_t P9N2_C_SCAN_CAPTUREDR_LONG = 0x2003D000ull;
+
+static const uint64_t P9N2_C_0_SCAN_CAPTUREDR_LONG = 0x2003D000ull;
+
+static const uint64_t P9N2_C_1_SCAN_CAPTUREDR_LONG = 0x2103D000ull;
+
+static const uint64_t P9N2_C_2_SCAN_CAPTUREDR_LONG = 0x2203D000ull;
+
+static const uint64_t P9N2_C_3_SCAN_CAPTUREDR_LONG = 0x2303D000ull;
+
+static const uint64_t P9N2_C_4_SCAN_CAPTUREDR_LONG = 0x2403D000ull;
+
+static const uint64_t P9N2_C_5_SCAN_CAPTUREDR_LONG = 0x2503D000ull;
+
+static const uint64_t P9N2_C_6_SCAN_CAPTUREDR_LONG = 0x2603D000ull;
+
+static const uint64_t P9N2_C_7_SCAN_CAPTUREDR_LONG = 0x2703D000ull;
+
+static const uint64_t P9N2_C_8_SCAN_CAPTUREDR_LONG = 0x2803D000ull;
+
+static const uint64_t P9N2_C_9_SCAN_CAPTUREDR_LONG = 0x2903D000ull;
+
+static const uint64_t P9N2_C_10_SCAN_CAPTUREDR_LONG = 0x2A03D000ull;
+
+static const uint64_t P9N2_C_11_SCAN_CAPTUREDR_LONG = 0x2B03D000ull;
+
+static const uint64_t P9N2_C_12_SCAN_CAPTUREDR_LONG = 0x2C03D000ull;
+
+static const uint64_t P9N2_C_13_SCAN_CAPTUREDR_LONG = 0x2D03D000ull;
+
+static const uint64_t P9N2_C_14_SCAN_CAPTUREDR_LONG = 0x2E03D000ull;
+
+static const uint64_t P9N2_C_15_SCAN_CAPTUREDR_LONG = 0x2F03D000ull;
+
+static const uint64_t P9N2_C_16_SCAN_CAPTUREDR_LONG = 0x3003D000ull;
+
+static const uint64_t P9N2_C_17_SCAN_CAPTUREDR_LONG = 0x3103D000ull;
+
+static const uint64_t P9N2_C_18_SCAN_CAPTUREDR_LONG = 0x3203D000ull;
+
+static const uint64_t P9N2_C_19_SCAN_CAPTUREDR_LONG = 0x3303D000ull;
+
+static const uint64_t P9N2_C_20_SCAN_CAPTUREDR_LONG = 0x3403D000ull;
+
+static const uint64_t P9N2_C_21_SCAN_CAPTUREDR_LONG = 0x3503D000ull;
+
+static const uint64_t P9N2_C_22_SCAN_CAPTUREDR_LONG = 0x3603D000ull;
+
+static const uint64_t P9N2_C_23_SCAN_CAPTUREDR_LONG = 0x3703D000ull;
+
+static const uint64_t P9N2_EQ_SCAN_CAPTUREDR_LONG = 0x1003D000ull;
+
+static const uint64_t P9N2_EQ_0_SCAN_CAPTUREDR_LONG = 0x1003D000ull;
+
+static const uint64_t P9N2_EQ_1_SCAN_CAPTUREDR_LONG = 0x1103D000ull;
+
+static const uint64_t P9N2_EQ_2_SCAN_CAPTUREDR_LONG = 0x1203D000ull;
+
+static const uint64_t P9N2_EQ_3_SCAN_CAPTUREDR_LONG = 0x1303D000ull;
+
+static const uint64_t P9N2_EQ_4_SCAN_CAPTUREDR_LONG = 0x1403D000ull;
+
+static const uint64_t P9N2_EQ_5_SCAN_CAPTUREDR_LONG = 0x1503D000ull;
+
+static const uint64_t P9N2_EX_SCAN_CAPTUREDR_LONG = 0x2003D000ull;
+//DUPS: 2103D000,
+static const uint64_t P9N2_EX_0_SCAN_CAPTUREDR_LONG = 0x2003D000ull;
+//DUPS: 2103D000,
+static const uint64_t P9N2_EX_1_SCAN_CAPTUREDR_LONG = 0x2203D000ull;
+//DUPS: 2303D000,
+static const uint64_t P9N2_EX_2_SCAN_CAPTUREDR_LONG = 0x2403D000ull;
+//DUPS: 2503D000,
+static const uint64_t P9N2_EX_3_SCAN_CAPTUREDR_LONG = 0x2603D000ull;
+//DUPS: 2703D000,
+static const uint64_t P9N2_EX_4_SCAN_CAPTUREDR_LONG = 0x2803D000ull;
+//DUPS: 2903D000,
+static const uint64_t P9N2_EX_5_SCAN_CAPTUREDR_LONG = 0x2A03D000ull;
+//DUPS: 2B03D000,
+static const uint64_t P9N2_EX_6_SCAN_CAPTUREDR_LONG = 0x2C03D000ull;
+//DUPS: 2D03D000,
+static const uint64_t P9N2_EX_7_SCAN_CAPTUREDR_LONG = 0x2F03D000ull;
+//DUPS: 2F03D000,
+static const uint64_t P9N2_EX_8_SCAN_CAPTUREDR_LONG = 0x3003D000ull;
+//DUPS: 3103D000,
+static const uint64_t P9N2_EX_9_SCAN_CAPTUREDR_LONG = 0x3203D000ull;
+//DUPS: 3303D000,
+static const uint64_t P9N2_EX_10_SCAN_CAPTUREDR_LONG = 0x3403D000ull;
+//DUPS: 3503D000,
+static const uint64_t P9N2_EX_11_SCAN_CAPTUREDR_LONG = 0x3603D000ull;
+//DUPS: 3703D000,
+
+static const uint64_t P9N2_C_SCAN_LONG_ROTATE = 0x20039000ull;
+
+static const uint64_t P9N2_C_0_SCAN_LONG_ROTATE = 0x20039000ull;
+
+static const uint64_t P9N2_C_1_SCAN_LONG_ROTATE = 0x21039000ull;
+
+static const uint64_t P9N2_C_2_SCAN_LONG_ROTATE = 0x22039000ull;
+
+static const uint64_t P9N2_C_3_SCAN_LONG_ROTATE = 0x23039000ull;
+
+static const uint64_t P9N2_C_4_SCAN_LONG_ROTATE = 0x24039000ull;
+
+static const uint64_t P9N2_C_5_SCAN_LONG_ROTATE = 0x25039000ull;
+
+static const uint64_t P9N2_C_6_SCAN_LONG_ROTATE = 0x26039000ull;
+
+static const uint64_t P9N2_C_7_SCAN_LONG_ROTATE = 0x27039000ull;
+
+static const uint64_t P9N2_C_8_SCAN_LONG_ROTATE = 0x28039000ull;
+
+static const uint64_t P9N2_C_9_SCAN_LONG_ROTATE = 0x29039000ull;
+
+static const uint64_t P9N2_C_10_SCAN_LONG_ROTATE = 0x2A039000ull;
+
+static const uint64_t P9N2_C_11_SCAN_LONG_ROTATE = 0x2B039000ull;
+
+static const uint64_t P9N2_C_12_SCAN_LONG_ROTATE = 0x2C039000ull;
+
+static const uint64_t P9N2_C_13_SCAN_LONG_ROTATE = 0x2D039000ull;
+
+static const uint64_t P9N2_C_14_SCAN_LONG_ROTATE = 0x2E039000ull;
+
+static const uint64_t P9N2_C_15_SCAN_LONG_ROTATE = 0x2F039000ull;
+
+static const uint64_t P9N2_C_16_SCAN_LONG_ROTATE = 0x30039000ull;
+
+static const uint64_t P9N2_C_17_SCAN_LONG_ROTATE = 0x31039000ull;
+
+static const uint64_t P9N2_C_18_SCAN_LONG_ROTATE = 0x32039000ull;
+
+static const uint64_t P9N2_C_19_SCAN_LONG_ROTATE = 0x33039000ull;
+
+static const uint64_t P9N2_C_20_SCAN_LONG_ROTATE = 0x34039000ull;
+
+static const uint64_t P9N2_C_21_SCAN_LONG_ROTATE = 0x35039000ull;
+
+static const uint64_t P9N2_C_22_SCAN_LONG_ROTATE = 0x36039000ull;
+
+static const uint64_t P9N2_C_23_SCAN_LONG_ROTATE = 0x37039000ull;
+
+static const uint64_t P9N2_EQ_SCAN_LONG_ROTATE = 0x10039000ull;
+
+static const uint64_t P9N2_EQ_0_SCAN_LONG_ROTATE = 0x10039000ull;
+
+static const uint64_t P9N2_EQ_1_SCAN_LONG_ROTATE = 0x11039000ull;
+
+static const uint64_t P9N2_EQ_2_SCAN_LONG_ROTATE = 0x12039000ull;
+
+static const uint64_t P9N2_EQ_3_SCAN_LONG_ROTATE = 0x13039000ull;
+
+static const uint64_t P9N2_EQ_4_SCAN_LONG_ROTATE = 0x14039000ull;
+
+static const uint64_t P9N2_EQ_5_SCAN_LONG_ROTATE = 0x15039000ull;
+
+static const uint64_t P9N2_EX_SCAN_LONG_ROTATE = 0x20039000ull;
+//DUPS: 21039000,
+static const uint64_t P9N2_EX_0_SCAN_LONG_ROTATE = 0x20039000ull;
+//DUPS: 21039000,
+static const uint64_t P9N2_EX_1_SCAN_LONG_ROTATE = 0x22039000ull;
+//DUPS: 23039000,
+static const uint64_t P9N2_EX_2_SCAN_LONG_ROTATE = 0x24039000ull;
+//DUPS: 25039000,
+static const uint64_t P9N2_EX_3_SCAN_LONG_ROTATE = 0x26039000ull;
+//DUPS: 27039000,
+static const uint64_t P9N2_EX_4_SCAN_LONG_ROTATE = 0x28039000ull;
+//DUPS: 29039000,
+static const uint64_t P9N2_EX_5_SCAN_LONG_ROTATE = 0x2A039000ull;
+//DUPS: 2B039000,
+static const uint64_t P9N2_EX_6_SCAN_LONG_ROTATE = 0x2C039000ull;
+//DUPS: 2D039000,
+static const uint64_t P9N2_EX_7_SCAN_LONG_ROTATE = 0x2F039000ull;
+//DUPS: 2F039000,
+static const uint64_t P9N2_EX_8_SCAN_LONG_ROTATE = 0x30039000ull;
+//DUPS: 31039000,
+static const uint64_t P9N2_EX_9_SCAN_LONG_ROTATE = 0x32039000ull;
+//DUPS: 33039000,
+static const uint64_t P9N2_EX_10_SCAN_LONG_ROTATE = 0x34039000ull;
+//DUPS: 35039000,
+static const uint64_t P9N2_EX_11_SCAN_LONG_ROTATE = 0x36039000ull;
+//DUPS: 37039000,
+
+static const uint64_t P9N2_C_SCAN_REGION_TYPE = 0x20030005ull;
+
+static const uint64_t P9N2_C_0_SCAN_REGION_TYPE = 0x20030005ull;
+
+static const uint64_t P9N2_C_1_SCAN_REGION_TYPE = 0x21030005ull;
+
+static const uint64_t P9N2_C_2_SCAN_REGION_TYPE = 0x22030005ull;
+
+static const uint64_t P9N2_C_3_SCAN_REGION_TYPE = 0x23030005ull;
+
+static const uint64_t P9N2_C_4_SCAN_REGION_TYPE = 0x24030005ull;
+
+static const uint64_t P9N2_C_5_SCAN_REGION_TYPE = 0x25030005ull;
+
+static const uint64_t P9N2_C_6_SCAN_REGION_TYPE = 0x26030005ull;
+
+static const uint64_t P9N2_C_7_SCAN_REGION_TYPE = 0x27030005ull;
+
+static const uint64_t P9N2_C_8_SCAN_REGION_TYPE = 0x28030005ull;
+
+static const uint64_t P9N2_C_9_SCAN_REGION_TYPE = 0x29030005ull;
+
+static const uint64_t P9N2_C_10_SCAN_REGION_TYPE = 0x2A030005ull;
+
+static const uint64_t P9N2_C_11_SCAN_REGION_TYPE = 0x2B030005ull;
+
+static const uint64_t P9N2_C_12_SCAN_REGION_TYPE = 0x2C030005ull;
+
+static const uint64_t P9N2_C_13_SCAN_REGION_TYPE = 0x2D030005ull;
+
+static const uint64_t P9N2_C_14_SCAN_REGION_TYPE = 0x2E030005ull;
+
+static const uint64_t P9N2_C_15_SCAN_REGION_TYPE = 0x2F030005ull;
+
+static const uint64_t P9N2_C_16_SCAN_REGION_TYPE = 0x30030005ull;
+
+static const uint64_t P9N2_C_17_SCAN_REGION_TYPE = 0x31030005ull;
+
+static const uint64_t P9N2_C_18_SCAN_REGION_TYPE = 0x32030005ull;
+
+static const uint64_t P9N2_C_19_SCAN_REGION_TYPE = 0x33030005ull;
+
+static const uint64_t P9N2_C_20_SCAN_REGION_TYPE = 0x34030005ull;
+
+static const uint64_t P9N2_C_21_SCAN_REGION_TYPE = 0x35030005ull;
+
+static const uint64_t P9N2_C_22_SCAN_REGION_TYPE = 0x36030005ull;
+
+static const uint64_t P9N2_C_23_SCAN_REGION_TYPE = 0x37030005ull;
+
+static const uint64_t P9N2_EQ_SCAN_REGION_TYPE = 0x10030005ull;
+
+static const uint64_t P9N2_EQ_0_SCAN_REGION_TYPE = 0x10030005ull;
+
+static const uint64_t P9N2_EQ_1_SCAN_REGION_TYPE = 0x11030005ull;
+
+static const uint64_t P9N2_EQ_2_SCAN_REGION_TYPE = 0x12030005ull;
+
+static const uint64_t P9N2_EQ_3_SCAN_REGION_TYPE = 0x13030005ull;
+
+static const uint64_t P9N2_EQ_4_SCAN_REGION_TYPE = 0x14030005ull;
+
+static const uint64_t P9N2_EQ_5_SCAN_REGION_TYPE = 0x15030005ull;
+
+static const uint64_t P9N2_EX_SCAN_REGION_TYPE = 0x20030005ull;
+//DUPS: 21030005,
+static const uint64_t P9N2_EX_0_SCAN_REGION_TYPE = 0x20030005ull;
+//DUPS: 21030005,
+static const uint64_t P9N2_EX_1_SCAN_REGION_TYPE = 0x22030005ull;
+//DUPS: 23030005,
+static const uint64_t P9N2_EX_2_SCAN_REGION_TYPE = 0x24030005ull;
+//DUPS: 25030005,
+static const uint64_t P9N2_EX_3_SCAN_REGION_TYPE = 0x26030005ull;
+//DUPS: 27030005,
+static const uint64_t P9N2_EX_4_SCAN_REGION_TYPE = 0x28030005ull;
+//DUPS: 29030005,
+static const uint64_t P9N2_EX_5_SCAN_REGION_TYPE = 0x2A030005ull;
+//DUPS: 2B030005,
+static const uint64_t P9N2_EX_6_SCAN_REGION_TYPE = 0x2C030005ull;
+//DUPS: 2D030005,
+static const uint64_t P9N2_EX_7_SCAN_REGION_TYPE = 0x2F030005ull;
+//DUPS: 2F030005,
+static const uint64_t P9N2_EX_8_SCAN_REGION_TYPE = 0x30030005ull;
+//DUPS: 31030005,
+static const uint64_t P9N2_EX_9_SCAN_REGION_TYPE = 0x32030005ull;
+//DUPS: 33030005,
+static const uint64_t P9N2_EX_10_SCAN_REGION_TYPE = 0x34030005ull;
+//DUPS: 35030005,
+static const uint64_t P9N2_EX_11_SCAN_REGION_TYPE = 0x36030005ull;
+//DUPS: 37030005,
+
+static const uint64_t P9N2_C_SCAN_UPDATEDR = 0x2003A000ull;
+
+static const uint64_t P9N2_C_0_SCAN_UPDATEDR = 0x2003A000ull;
+
+static const uint64_t P9N2_C_1_SCAN_UPDATEDR = 0x2103A000ull;
+
+static const uint64_t P9N2_C_2_SCAN_UPDATEDR = 0x2203A000ull;
+
+static const uint64_t P9N2_C_3_SCAN_UPDATEDR = 0x2303A000ull;
+
+static const uint64_t P9N2_C_4_SCAN_UPDATEDR = 0x2403A000ull;
+
+static const uint64_t P9N2_C_5_SCAN_UPDATEDR = 0x2503A000ull;
+
+static const uint64_t P9N2_C_6_SCAN_UPDATEDR = 0x2603A000ull;
+
+static const uint64_t P9N2_C_7_SCAN_UPDATEDR = 0x2703A000ull;
+
+static const uint64_t P9N2_C_8_SCAN_UPDATEDR = 0x2803A000ull;
+
+static const uint64_t P9N2_C_9_SCAN_UPDATEDR = 0x2903A000ull;
+
+static const uint64_t P9N2_C_10_SCAN_UPDATEDR = 0x2A03A000ull;
+
+static const uint64_t P9N2_C_11_SCAN_UPDATEDR = 0x2B03A000ull;
+
+static const uint64_t P9N2_C_12_SCAN_UPDATEDR = 0x2C03A000ull;
+
+static const uint64_t P9N2_C_13_SCAN_UPDATEDR = 0x2D03A000ull;
+
+static const uint64_t P9N2_C_14_SCAN_UPDATEDR = 0x2E03A000ull;
+
+static const uint64_t P9N2_C_15_SCAN_UPDATEDR = 0x2F03A000ull;
+
+static const uint64_t P9N2_C_16_SCAN_UPDATEDR = 0x3003A000ull;
+
+static const uint64_t P9N2_C_17_SCAN_UPDATEDR = 0x3103A000ull;
+
+static const uint64_t P9N2_C_18_SCAN_UPDATEDR = 0x3203A000ull;
+
+static const uint64_t P9N2_C_19_SCAN_UPDATEDR = 0x3303A000ull;
+
+static const uint64_t P9N2_C_20_SCAN_UPDATEDR = 0x3403A000ull;
+
+static const uint64_t P9N2_C_21_SCAN_UPDATEDR = 0x3503A000ull;
+
+static const uint64_t P9N2_C_22_SCAN_UPDATEDR = 0x3603A000ull;
+
+static const uint64_t P9N2_C_23_SCAN_UPDATEDR = 0x3703A000ull;
+
+static const uint64_t P9N2_EQ_SCAN_UPDATEDR = 0x1003A000ull;
+
+static const uint64_t P9N2_EQ_0_SCAN_UPDATEDR = 0x1003A000ull;
+
+static const uint64_t P9N2_EQ_1_SCAN_UPDATEDR = 0x1103A000ull;
+
+static const uint64_t P9N2_EQ_2_SCAN_UPDATEDR = 0x1203A000ull;
+
+static const uint64_t P9N2_EQ_3_SCAN_UPDATEDR = 0x1303A000ull;
+
+static const uint64_t P9N2_EQ_4_SCAN_UPDATEDR = 0x1403A000ull;
+
+static const uint64_t P9N2_EQ_5_SCAN_UPDATEDR = 0x1503A000ull;
+
+static const uint64_t P9N2_EX_SCAN_UPDATEDR = 0x2003A000ull;
+//DUPS: 2103A000,
+static const uint64_t P9N2_EX_0_SCAN_UPDATEDR = 0x2003A000ull;
+//DUPS: 2103A000,
+static const uint64_t P9N2_EX_1_SCAN_UPDATEDR = 0x2203A000ull;
+//DUPS: 2303A000,
+static const uint64_t P9N2_EX_2_SCAN_UPDATEDR = 0x2403A000ull;
+//DUPS: 2503A000,
+static const uint64_t P9N2_EX_3_SCAN_UPDATEDR = 0x2603A000ull;
+//DUPS: 2703A000,
+static const uint64_t P9N2_EX_4_SCAN_UPDATEDR = 0x2803A000ull;
+//DUPS: 2903A000,
+static const uint64_t P9N2_EX_5_SCAN_UPDATEDR = 0x2A03A000ull;
+//DUPS: 2B03A000,
+static const uint64_t P9N2_EX_6_SCAN_UPDATEDR = 0x2C03A000ull;
+//DUPS: 2D03A000,
+static const uint64_t P9N2_EX_7_SCAN_UPDATEDR = 0x2F03A000ull;
+//DUPS: 2F03A000,
+static const uint64_t P9N2_EX_8_SCAN_UPDATEDR = 0x3003A000ull;
+//DUPS: 3103A000,
+static const uint64_t P9N2_EX_9_SCAN_UPDATEDR = 0x3203A000ull;
+//DUPS: 3303A000,
+static const uint64_t P9N2_EX_10_SCAN_UPDATEDR = 0x3403A000ull;
+//DUPS: 3503A000,
+static const uint64_t P9N2_EX_11_SCAN_UPDATEDR = 0x3603A000ull;
+//DUPS: 3703A000,
+
+static const uint64_t P9N2_C_SCAN_UPDATEDR_LONG = 0x2003B000ull;
+
+static const uint64_t P9N2_C_0_SCAN_UPDATEDR_LONG = 0x2003B000ull;
+
+static const uint64_t P9N2_C_1_SCAN_UPDATEDR_LONG = 0x2103B000ull;
+
+static const uint64_t P9N2_C_2_SCAN_UPDATEDR_LONG = 0x2203B000ull;
+
+static const uint64_t P9N2_C_3_SCAN_UPDATEDR_LONG = 0x2303B000ull;
+
+static const uint64_t P9N2_C_4_SCAN_UPDATEDR_LONG = 0x2403B000ull;
+
+static const uint64_t P9N2_C_5_SCAN_UPDATEDR_LONG = 0x2503B000ull;
+
+static const uint64_t P9N2_C_6_SCAN_UPDATEDR_LONG = 0x2603B000ull;
+
+static const uint64_t P9N2_C_7_SCAN_UPDATEDR_LONG = 0x2703B000ull;
+
+static const uint64_t P9N2_C_8_SCAN_UPDATEDR_LONG = 0x2803B000ull;
+
+static const uint64_t P9N2_C_9_SCAN_UPDATEDR_LONG = 0x2903B000ull;
+
+static const uint64_t P9N2_C_10_SCAN_UPDATEDR_LONG = 0x2A03B000ull;
+
+static const uint64_t P9N2_C_11_SCAN_UPDATEDR_LONG = 0x2B03B000ull;
+
+static const uint64_t P9N2_C_12_SCAN_UPDATEDR_LONG = 0x2C03B000ull;
+
+static const uint64_t P9N2_C_13_SCAN_UPDATEDR_LONG = 0x2D03B000ull;
+
+static const uint64_t P9N2_C_14_SCAN_UPDATEDR_LONG = 0x2E03B000ull;
+
+static const uint64_t P9N2_C_15_SCAN_UPDATEDR_LONG = 0x2F03B000ull;
+
+static const uint64_t P9N2_C_16_SCAN_UPDATEDR_LONG = 0x3003B000ull;
+
+static const uint64_t P9N2_C_17_SCAN_UPDATEDR_LONG = 0x3103B000ull;
+
+static const uint64_t P9N2_C_18_SCAN_UPDATEDR_LONG = 0x3203B000ull;
+
+static const uint64_t P9N2_C_19_SCAN_UPDATEDR_LONG = 0x3303B000ull;
+
+static const uint64_t P9N2_C_20_SCAN_UPDATEDR_LONG = 0x3403B000ull;
+
+static const uint64_t P9N2_C_21_SCAN_UPDATEDR_LONG = 0x3503B000ull;
+
+static const uint64_t P9N2_C_22_SCAN_UPDATEDR_LONG = 0x3603B000ull;
+
+static const uint64_t P9N2_C_23_SCAN_UPDATEDR_LONG = 0x3703B000ull;
+
+static const uint64_t P9N2_EQ_SCAN_UPDATEDR_LONG = 0x1003B000ull;
+
+static const uint64_t P9N2_EQ_0_SCAN_UPDATEDR_LONG = 0x1003B000ull;
+
+static const uint64_t P9N2_EQ_1_SCAN_UPDATEDR_LONG = 0x1103B000ull;
+
+static const uint64_t P9N2_EQ_2_SCAN_UPDATEDR_LONG = 0x1203B000ull;
+
+static const uint64_t P9N2_EQ_3_SCAN_UPDATEDR_LONG = 0x1303B000ull;
+
+static const uint64_t P9N2_EQ_4_SCAN_UPDATEDR_LONG = 0x1403B000ull;
+
+static const uint64_t P9N2_EQ_5_SCAN_UPDATEDR_LONG = 0x1503B000ull;
+
+static const uint64_t P9N2_EX_SCAN_UPDATEDR_LONG = 0x2003B000ull;
+//DUPS: 2103B000,
+static const uint64_t P9N2_EX_0_SCAN_UPDATEDR_LONG = 0x2003B000ull;
+//DUPS: 2103B000,
+static const uint64_t P9N2_EX_1_SCAN_UPDATEDR_LONG = 0x2203B000ull;
+//DUPS: 2303B000,
+static const uint64_t P9N2_EX_2_SCAN_UPDATEDR_LONG = 0x2403B000ull;
+//DUPS: 2503B000,
+static const uint64_t P9N2_EX_3_SCAN_UPDATEDR_LONG = 0x2603B000ull;
+//DUPS: 2703B000,
+static const uint64_t P9N2_EX_4_SCAN_UPDATEDR_LONG = 0x2803B000ull;
+//DUPS: 2903B000,
+static const uint64_t P9N2_EX_5_SCAN_UPDATEDR_LONG = 0x2A03B000ull;
+//DUPS: 2B03B000,
+static const uint64_t P9N2_EX_6_SCAN_UPDATEDR_LONG = 0x2C03B000ull;
+//DUPS: 2D03B000,
+static const uint64_t P9N2_EX_7_SCAN_UPDATEDR_LONG = 0x2F03B000ull;
+//DUPS: 2F03B000,
+static const uint64_t P9N2_EX_8_SCAN_UPDATEDR_LONG = 0x3003B000ull;
+//DUPS: 3103B000,
+static const uint64_t P9N2_EX_9_SCAN_UPDATEDR_LONG = 0x3203B000ull;
+//DUPS: 3303B000,
+static const uint64_t P9N2_EX_10_SCAN_UPDATEDR_LONG = 0x3403B000ull;
+//DUPS: 3503B000,
+static const uint64_t P9N2_EX_11_SCAN_UPDATEDR_LONG = 0x3603B000ull;
+//DUPS: 3703B000,
+
+static const uint64_t P9N2_C_SCOMC = 0x20010A80ull;
+
+static const uint64_t P9N2_C_0_SCOMC = 0x20010A80ull;
+
+static const uint64_t P9N2_C_1_SCOMC = 0x21010A80ull;
+
+static const uint64_t P9N2_C_2_SCOMC = 0x22010A80ull;
+
+static const uint64_t P9N2_C_3_SCOMC = 0x23010A80ull;
+
+static const uint64_t P9N2_C_4_SCOMC = 0x24010A80ull;
+
+static const uint64_t P9N2_C_5_SCOMC = 0x25010A80ull;
+
+static const uint64_t P9N2_C_6_SCOMC = 0x26010A80ull;
+
+static const uint64_t P9N2_C_7_SCOMC = 0x27010A80ull;
+
+static const uint64_t P9N2_C_8_SCOMC = 0x28010A80ull;
+
+static const uint64_t P9N2_C_9_SCOMC = 0x29010A80ull;
+
+static const uint64_t P9N2_C_10_SCOMC = 0x2A010A80ull;
+
+static const uint64_t P9N2_C_11_SCOMC = 0x2B010A80ull;
+
+static const uint64_t P9N2_C_12_SCOMC = 0x2C010A80ull;
+
+static const uint64_t P9N2_C_13_SCOMC = 0x2D010A80ull;
+
+static const uint64_t P9N2_C_14_SCOMC = 0x2E010A80ull;
+
+static const uint64_t P9N2_C_15_SCOMC = 0x2F010A80ull;
+
+static const uint64_t P9N2_C_16_SCOMC = 0x30010A80ull;
+
+static const uint64_t P9N2_C_17_SCOMC = 0x31010A80ull;
+
+static const uint64_t P9N2_C_18_SCOMC = 0x32010A80ull;
+
+static const uint64_t P9N2_C_19_SCOMC = 0x33010A80ull;
+
+static const uint64_t P9N2_C_20_SCOMC = 0x34010A80ull;
+
+static const uint64_t P9N2_C_21_SCOMC = 0x35010A80ull;
+
+static const uint64_t P9N2_C_22_SCOMC = 0x36010A80ull;
+
+static const uint64_t P9N2_C_23_SCOMC = 0x37010A80ull;
+
+static const uint64_t P9N2_EX_0_L2_SCOMC = 0x20010A80ull;
+//DUPS: 20010A80,
+static const uint64_t P9N2_EX_10_L2_SCOMC = 0x34010A80ull;
+//DUPS: 34010A80,
+static const uint64_t P9N2_EX_11_L2_SCOMC = 0x36010A80ull;
+//DUPS: 36010A80,
+static const uint64_t P9N2_EX_1_L2_SCOMC = 0x22010A80ull;
+//DUPS: 22010A80,
+static const uint64_t P9N2_EX_2_L2_SCOMC = 0x24010A80ull;
+//DUPS: 24010A80,
+static const uint64_t P9N2_EX_3_L2_SCOMC = 0x26010A80ull;
+//DUPS: 26010A80,
+static const uint64_t P9N2_EX_4_L2_SCOMC = 0x28010A80ull;
+//DUPS: 28010A80,
+static const uint64_t P9N2_EX_5_L2_SCOMC = 0x2B010A80ull;
+//DUPS: 2A010A80,
+static const uint64_t P9N2_EX_6_L2_SCOMC = 0x2D010A80ull;
+//DUPS: 2C010A80,
+static const uint64_t P9N2_EX_7_L2_SCOMC = 0x2F010A80ull;
+//DUPS: 2E010A80,
+static const uint64_t P9N2_EX_8_L2_SCOMC = 0x30010A80ull;
+//DUPS: 30010A80,
+static const uint64_t P9N2_EX_9_L2_SCOMC = 0x32010A80ull;
+//DUPS: 32010A80,
+static const uint64_t P9N2_EX_L2_SCOMC = 0x20010A80ull;
+//DUPS: 20010A80,
+
+static const uint64_t P9N2_C_SCOMD = 0x20010A81ull;
+
+static const uint64_t P9N2_C_0_SCOMD = 0x20010A81ull;
+
+static const uint64_t P9N2_C_1_SCOMD = 0x21010A81ull;
+
+static const uint64_t P9N2_C_2_SCOMD = 0x22010A81ull;
+
+static const uint64_t P9N2_C_3_SCOMD = 0x23010A81ull;
+
+static const uint64_t P9N2_C_4_SCOMD = 0x24010A81ull;
+
+static const uint64_t P9N2_C_5_SCOMD = 0x25010A81ull;
+
+static const uint64_t P9N2_C_6_SCOMD = 0x26010A81ull;
+
+static const uint64_t P9N2_C_7_SCOMD = 0x27010A81ull;
+
+static const uint64_t P9N2_C_8_SCOMD = 0x28010A81ull;
+
+static const uint64_t P9N2_C_9_SCOMD = 0x29010A81ull;
+
+static const uint64_t P9N2_C_10_SCOMD = 0x2A010A81ull;
+
+static const uint64_t P9N2_C_11_SCOMD = 0x2B010A81ull;
+
+static const uint64_t P9N2_C_12_SCOMD = 0x2C010A81ull;
+
+static const uint64_t P9N2_C_13_SCOMD = 0x2D010A81ull;
+
+static const uint64_t P9N2_C_14_SCOMD = 0x2E010A81ull;
+
+static const uint64_t P9N2_C_15_SCOMD = 0x2F010A81ull;
+
+static const uint64_t P9N2_C_16_SCOMD = 0x30010A81ull;
+
+static const uint64_t P9N2_C_17_SCOMD = 0x31010A81ull;
+
+static const uint64_t P9N2_C_18_SCOMD = 0x32010A81ull;
+
+static const uint64_t P9N2_C_19_SCOMD = 0x33010A81ull;
+
+static const uint64_t P9N2_C_20_SCOMD = 0x34010A81ull;
+
+static const uint64_t P9N2_C_21_SCOMD = 0x35010A81ull;
+
+static const uint64_t P9N2_C_22_SCOMD = 0x36010A81ull;
+
+static const uint64_t P9N2_C_23_SCOMD = 0x37010A81ull;
+
+static const uint64_t P9N2_EX_0_L2_SCOMD = 0x20010A81ull;
+//DUPS: 20010A81,
+static const uint64_t P9N2_EX_10_L2_SCOMD = 0x34010A81ull;
+//DUPS: 34010A81,
+static const uint64_t P9N2_EX_11_L2_SCOMD = 0x36010A81ull;
+//DUPS: 36010A81,
+static const uint64_t P9N2_EX_1_L2_SCOMD = 0x22010A81ull;
+//DUPS: 22010A81,
+static const uint64_t P9N2_EX_2_L2_SCOMD = 0x24010A81ull;
+//DUPS: 24010A81,
+static const uint64_t P9N2_EX_3_L2_SCOMD = 0x26010A81ull;
+//DUPS: 26010A81,
+static const uint64_t P9N2_EX_4_L2_SCOMD = 0x28010A81ull;
+//DUPS: 28010A81,
+static const uint64_t P9N2_EX_5_L2_SCOMD = 0x2B010A81ull;
+//DUPS: 2A010A81,
+static const uint64_t P9N2_EX_6_L2_SCOMD = 0x2D010A81ull;
+//DUPS: 2C010A81,
+static const uint64_t P9N2_EX_7_L2_SCOMD = 0x2F010A81ull;
+//DUPS: 2E010A81,
+static const uint64_t P9N2_EX_8_L2_SCOMD = 0x30010A81ull;
+//DUPS: 30010A81,
+static const uint64_t P9N2_EX_9_L2_SCOMD = 0x32010A81ull;
+//DUPS: 32010A81,
+static const uint64_t P9N2_EX_L2_SCOMD = 0x20010A81ull;
+//DUPS: 20010A81,
+
+static const uint64_t P9N2_C_SCR0 = 0x20010A86ull;
+
+static const uint64_t P9N2_C_0_SCR0 = 0x20010A86ull;
+
+static const uint64_t P9N2_C_1_SCR0 = 0x21010A86ull;
+
+static const uint64_t P9N2_C_2_SCR0 = 0x22010A86ull;
+
+static const uint64_t P9N2_C_3_SCR0 = 0x23010A86ull;
+
+static const uint64_t P9N2_C_4_SCR0 = 0x24010A86ull;
+
+static const uint64_t P9N2_C_5_SCR0 = 0x25010A86ull;
+
+static const uint64_t P9N2_C_6_SCR0 = 0x26010A86ull;
+
+static const uint64_t P9N2_C_7_SCR0 = 0x27010A86ull;
+
+static const uint64_t P9N2_C_8_SCR0 = 0x28010A86ull;
+
+static const uint64_t P9N2_C_9_SCR0 = 0x29010A86ull;
+
+static const uint64_t P9N2_C_10_SCR0 = 0x2A010A86ull;
+
+static const uint64_t P9N2_C_11_SCR0 = 0x2B010A86ull;
+
+static const uint64_t P9N2_C_12_SCR0 = 0x2C010A86ull;
+
+static const uint64_t P9N2_C_13_SCR0 = 0x2D010A86ull;
+
+static const uint64_t P9N2_C_14_SCR0 = 0x2E010A86ull;
+
+static const uint64_t P9N2_C_15_SCR0 = 0x2F010A86ull;
+
+static const uint64_t P9N2_C_16_SCR0 = 0x30010A86ull;
+
+static const uint64_t P9N2_C_17_SCR0 = 0x31010A86ull;
+
+static const uint64_t P9N2_C_18_SCR0 = 0x32010A86ull;
+
+static const uint64_t P9N2_C_19_SCR0 = 0x33010A86ull;
+
+static const uint64_t P9N2_C_20_SCR0 = 0x34010A86ull;
+
+static const uint64_t P9N2_C_21_SCR0 = 0x35010A86ull;
+
+static const uint64_t P9N2_C_22_SCR0 = 0x36010A86ull;
+
+static const uint64_t P9N2_C_23_SCR0 = 0x37010A86ull;
+
+static const uint64_t P9N2_EX_0_L2_SCR0 = 0x20010A86ull;
+//DUPS: 20010A86,
+static const uint64_t P9N2_EX_10_L2_SCR0 = 0x34010A86ull;
+//DUPS: 34010A86,
+static const uint64_t P9N2_EX_11_L2_SCR0 = 0x36010A86ull;
+//DUPS: 36010A86,
+static const uint64_t P9N2_EX_1_L2_SCR0 = 0x22010A86ull;
+//DUPS: 22010A86,
+static const uint64_t P9N2_EX_2_L2_SCR0 = 0x24010A86ull;
+//DUPS: 24010A86,
+static const uint64_t P9N2_EX_3_L2_SCR0 = 0x26010A86ull;
+//DUPS: 26010A86,
+static const uint64_t P9N2_EX_4_L2_SCR0 = 0x28010A86ull;
+//DUPS: 28010A86,
+static const uint64_t P9N2_EX_5_L2_SCR0 = 0x2B010A86ull;
+//DUPS: 2A010A86,
+static const uint64_t P9N2_EX_6_L2_SCR0 = 0x2D010A86ull;
+//DUPS: 2C010A86,
+static const uint64_t P9N2_EX_7_L2_SCR0 = 0x2F010A86ull;
+//DUPS: 2E010A86,
+static const uint64_t P9N2_EX_8_L2_SCR0 = 0x30010A86ull;
+//DUPS: 30010A86,
+static const uint64_t P9N2_EX_9_L2_SCR0 = 0x32010A86ull;
+//DUPS: 32010A86,
+static const uint64_t P9N2_EX_L2_SCR0 = 0x20010A86ull;
+//DUPS: 20010A86,
+
+static const uint64_t P9N2_C_SCR1 = 0x20010A87ull;
+
+static const uint64_t P9N2_C_0_SCR1 = 0x20010A87ull;
+
+static const uint64_t P9N2_C_1_SCR1 = 0x21010A87ull;
+
+static const uint64_t P9N2_C_2_SCR1 = 0x22010A87ull;
+
+static const uint64_t P9N2_C_3_SCR1 = 0x23010A87ull;
+
+static const uint64_t P9N2_C_4_SCR1 = 0x24010A87ull;
+
+static const uint64_t P9N2_C_5_SCR1 = 0x25010A87ull;
+
+static const uint64_t P9N2_C_6_SCR1 = 0x26010A87ull;
+
+static const uint64_t P9N2_C_7_SCR1 = 0x27010A87ull;
+
+static const uint64_t P9N2_C_8_SCR1 = 0x28010A87ull;
+
+static const uint64_t P9N2_C_9_SCR1 = 0x29010A87ull;
+
+static const uint64_t P9N2_C_10_SCR1 = 0x2A010A87ull;
+
+static const uint64_t P9N2_C_11_SCR1 = 0x2B010A87ull;
+
+static const uint64_t P9N2_C_12_SCR1 = 0x2C010A87ull;
+
+static const uint64_t P9N2_C_13_SCR1 = 0x2D010A87ull;
+
+static const uint64_t P9N2_C_14_SCR1 = 0x2E010A87ull;
+
+static const uint64_t P9N2_C_15_SCR1 = 0x2F010A87ull;
+
+static const uint64_t P9N2_C_16_SCR1 = 0x30010A87ull;
+
+static const uint64_t P9N2_C_17_SCR1 = 0x31010A87ull;
+
+static const uint64_t P9N2_C_18_SCR1 = 0x32010A87ull;
+
+static const uint64_t P9N2_C_19_SCR1 = 0x33010A87ull;
+
+static const uint64_t P9N2_C_20_SCR1 = 0x34010A87ull;
+
+static const uint64_t P9N2_C_21_SCR1 = 0x35010A87ull;
+
+static const uint64_t P9N2_C_22_SCR1 = 0x36010A87ull;
+
+static const uint64_t P9N2_C_23_SCR1 = 0x37010A87ull;
+
+static const uint64_t P9N2_EX_0_L2_SCR1 = 0x20010A87ull;
+//DUPS: 20010A87,
+static const uint64_t P9N2_EX_10_L2_SCR1 = 0x34010A87ull;
+//DUPS: 34010A87,
+static const uint64_t P9N2_EX_11_L2_SCR1 = 0x36010A87ull;
+//DUPS: 36010A87,
+static const uint64_t P9N2_EX_1_L2_SCR1 = 0x22010A87ull;
+//DUPS: 22010A87,
+static const uint64_t P9N2_EX_2_L2_SCR1 = 0x24010A87ull;
+//DUPS: 24010A87,
+static const uint64_t P9N2_EX_3_L2_SCR1 = 0x26010A87ull;
+//DUPS: 26010A87,
+static const uint64_t P9N2_EX_4_L2_SCR1 = 0x28010A87ull;
+//DUPS: 28010A87,
+static const uint64_t P9N2_EX_5_L2_SCR1 = 0x2B010A87ull;
+//DUPS: 2A010A87,
+static const uint64_t P9N2_EX_6_L2_SCR1 = 0x2D010A87ull;
+//DUPS: 2C010A87,
+static const uint64_t P9N2_EX_7_L2_SCR1 = 0x2F010A87ull;
+//DUPS: 2E010A87,
+static const uint64_t P9N2_EX_8_L2_SCR1 = 0x30010A87ull;
+//DUPS: 30010A87,
+static const uint64_t P9N2_EX_9_L2_SCR1 = 0x32010A87ull;
+//DUPS: 32010A87,
+static const uint64_t P9N2_EX_L2_SCR1 = 0x20010A87ull;
+//DUPS: 20010A87,
+
+static const uint64_t P9N2_C_SCR2 = 0x20010A88ull;
+
+static const uint64_t P9N2_C_0_SCR2 = 0x20010A88ull;
+
+static const uint64_t P9N2_C_1_SCR2 = 0x21010A88ull;
+
+static const uint64_t P9N2_C_2_SCR2 = 0x22010A88ull;
+
+static const uint64_t P9N2_C_3_SCR2 = 0x23010A88ull;
+
+static const uint64_t P9N2_C_4_SCR2 = 0x24010A88ull;
+
+static const uint64_t P9N2_C_5_SCR2 = 0x25010A88ull;
+
+static const uint64_t P9N2_C_6_SCR2 = 0x26010A88ull;
+
+static const uint64_t P9N2_C_7_SCR2 = 0x27010A88ull;
+
+static const uint64_t P9N2_C_8_SCR2 = 0x28010A88ull;
+
+static const uint64_t P9N2_C_9_SCR2 = 0x29010A88ull;
+
+static const uint64_t P9N2_C_10_SCR2 = 0x2A010A88ull;
+
+static const uint64_t P9N2_C_11_SCR2 = 0x2B010A88ull;
+
+static const uint64_t P9N2_C_12_SCR2 = 0x2C010A88ull;
+
+static const uint64_t P9N2_C_13_SCR2 = 0x2D010A88ull;
+
+static const uint64_t P9N2_C_14_SCR2 = 0x2E010A88ull;
+
+static const uint64_t P9N2_C_15_SCR2 = 0x2F010A88ull;
+
+static const uint64_t P9N2_C_16_SCR2 = 0x30010A88ull;
+
+static const uint64_t P9N2_C_17_SCR2 = 0x31010A88ull;
+
+static const uint64_t P9N2_C_18_SCR2 = 0x32010A88ull;
+
+static const uint64_t P9N2_C_19_SCR2 = 0x33010A88ull;
+
+static const uint64_t P9N2_C_20_SCR2 = 0x34010A88ull;
+
+static const uint64_t P9N2_C_21_SCR2 = 0x35010A88ull;
+
+static const uint64_t P9N2_C_22_SCR2 = 0x36010A88ull;
+
+static const uint64_t P9N2_C_23_SCR2 = 0x37010A88ull;
+
+static const uint64_t P9N2_EX_SCR2 = 0x20010A88ull;
+//DUPS: 20010A88,
+static const uint64_t P9N2_EX_0_SCR2 = 0x20010A88ull;
+//DUPS: 20010A88,
+static const uint64_t P9N2_EX_1_SCR2 = 0x22010A88ull;
+//DUPS: 22010A88,
+static const uint64_t P9N2_EX_2_SCR2 = 0x24010A88ull;
+//DUPS: 24010A88,
+static const uint64_t P9N2_EX_3_SCR2 = 0x26010A88ull;
+//DUPS: 26010A88,
+static const uint64_t P9N2_EX_4_SCR2 = 0x28010A88ull;
+//DUPS: 28010A88,
+static const uint64_t P9N2_EX_5_SCR2 = 0x2B010A88ull;
+//DUPS: 2A010A88,
+static const uint64_t P9N2_EX_6_SCR2 = 0x2D010A88ull;
+//DUPS: 2C010A88,
+static const uint64_t P9N2_EX_7_SCR2 = 0x2F010A88ull;
+//DUPS: 2E010A88,
+static const uint64_t P9N2_EX_8_SCR2 = 0x30010A88ull;
+//DUPS: 30010A88,
+static const uint64_t P9N2_EX_9_SCR2 = 0x32010A88ull;
+//DUPS: 32010A88,
+static const uint64_t P9N2_EX_10_SCR2 = 0x34010A88ull;
+//DUPS: 34010A88,
+static const uint64_t P9N2_EX_11_SCR2 = 0x36010A88ull;
+//DUPS: 36010A88,
+
+static const uint64_t P9N2_C_SCR3 = 0x20010A89ull;
+
+static const uint64_t P9N2_C_0_SCR3 = 0x20010A89ull;
+
+static const uint64_t P9N2_C_1_SCR3 = 0x21010A89ull;
+
+static const uint64_t P9N2_C_2_SCR3 = 0x22010A89ull;
+
+static const uint64_t P9N2_C_3_SCR3 = 0x23010A89ull;
+
+static const uint64_t P9N2_C_4_SCR3 = 0x24010A89ull;
+
+static const uint64_t P9N2_C_5_SCR3 = 0x25010A89ull;
+
+static const uint64_t P9N2_C_6_SCR3 = 0x26010A89ull;
+
+static const uint64_t P9N2_C_7_SCR3 = 0x27010A89ull;
+
+static const uint64_t P9N2_C_8_SCR3 = 0x28010A89ull;
+
+static const uint64_t P9N2_C_9_SCR3 = 0x29010A89ull;
+
+static const uint64_t P9N2_C_10_SCR3 = 0x2A010A89ull;
+
+static const uint64_t P9N2_C_11_SCR3 = 0x2B010A89ull;
+
+static const uint64_t P9N2_C_12_SCR3 = 0x2C010A89ull;
+
+static const uint64_t P9N2_C_13_SCR3 = 0x2D010A89ull;
+
+static const uint64_t P9N2_C_14_SCR3 = 0x2E010A89ull;
+
+static const uint64_t P9N2_C_15_SCR3 = 0x2F010A89ull;
+
+static const uint64_t P9N2_C_16_SCR3 = 0x30010A89ull;
+
+static const uint64_t P9N2_C_17_SCR3 = 0x31010A89ull;
+
+static const uint64_t P9N2_C_18_SCR3 = 0x32010A89ull;
+
+static const uint64_t P9N2_C_19_SCR3 = 0x33010A89ull;
+
+static const uint64_t P9N2_C_20_SCR3 = 0x34010A89ull;
+
+static const uint64_t P9N2_C_21_SCR3 = 0x35010A89ull;
+
+static const uint64_t P9N2_C_22_SCR3 = 0x36010A89ull;
+
+static const uint64_t P9N2_C_23_SCR3 = 0x37010A89ull;
+
+static const uint64_t P9N2_EX_SCR3 = 0x20010A89ull;
+//DUPS: 20010A89,
+static const uint64_t P9N2_EX_0_SCR3 = 0x20010A89ull;
+//DUPS: 20010A89,
+static const uint64_t P9N2_EX_1_SCR3 = 0x22010A89ull;
+//DUPS: 22010A89,
+static const uint64_t P9N2_EX_2_SCR3 = 0x24010A89ull;
+//DUPS: 24010A89,
+static const uint64_t P9N2_EX_3_SCR3 = 0x26010A89ull;
+//DUPS: 26010A89,
+static const uint64_t P9N2_EX_4_SCR3 = 0x28010A89ull;
+//DUPS: 28010A89,
+static const uint64_t P9N2_EX_5_SCR3 = 0x2B010A89ull;
+//DUPS: 2A010A89,
+static const uint64_t P9N2_EX_6_SCR3 = 0x2D010A89ull;
+//DUPS: 2C010A89,
+static const uint64_t P9N2_EX_7_SCR3 = 0x2F010A89ull;
+//DUPS: 2E010A89,
+static const uint64_t P9N2_EX_8_SCR3 = 0x30010A89ull;
+//DUPS: 30010A89,
+static const uint64_t P9N2_EX_9_SCR3 = 0x32010A89ull;
+//DUPS: 32010A89,
+static const uint64_t P9N2_EX_10_SCR3 = 0x34010A89ull;
+//DUPS: 34010A89,
+static const uint64_t P9N2_EX_11_SCR3 = 0x36010A89ull;
+//DUPS: 36010A89,
+
+static const uint64_t P9N2_C_SHID0 = 0x20010AA5ull;
+
+static const uint64_t P9N2_C_0_SHID0 = 0x20010AA5ull;
+
+static const uint64_t P9N2_C_1_SHID0 = 0x21010AA5ull;
+
+static const uint64_t P9N2_C_2_SHID0 = 0x22010AA5ull;
+
+static const uint64_t P9N2_C_3_SHID0 = 0x23010AA5ull;
+
+static const uint64_t P9N2_C_4_SHID0 = 0x24010AA5ull;
+
+static const uint64_t P9N2_C_5_SHID0 = 0x25010AA5ull;
+
+static const uint64_t P9N2_C_6_SHID0 = 0x26010AA5ull;
+
+static const uint64_t P9N2_C_7_SHID0 = 0x27010AA5ull;
+
+static const uint64_t P9N2_C_8_SHID0 = 0x28010AA5ull;
+
+static const uint64_t P9N2_C_9_SHID0 = 0x29010AA5ull;
+
+static const uint64_t P9N2_C_10_SHID0 = 0x2A010AA5ull;
+
+static const uint64_t P9N2_C_11_SHID0 = 0x2B010AA5ull;
+
+static const uint64_t P9N2_C_12_SHID0 = 0x2C010AA5ull;
+
+static const uint64_t P9N2_C_13_SHID0 = 0x2D010AA5ull;
+
+static const uint64_t P9N2_C_14_SHID0 = 0x2E010AA5ull;
+
+static const uint64_t P9N2_C_15_SHID0 = 0x2F010AA5ull;
+
+static const uint64_t P9N2_C_16_SHID0 = 0x30010AA5ull;
+
+static const uint64_t P9N2_C_17_SHID0 = 0x31010AA5ull;
+
+static const uint64_t P9N2_C_18_SHID0 = 0x32010AA5ull;
+
+static const uint64_t P9N2_C_19_SHID0 = 0x33010AA5ull;
+
+static const uint64_t P9N2_C_20_SHID0 = 0x34010AA5ull;
+
+static const uint64_t P9N2_C_21_SHID0 = 0x35010AA5ull;
+
+static const uint64_t P9N2_C_22_SHID0 = 0x36010AA5ull;
+
+static const uint64_t P9N2_C_23_SHID0 = 0x37010AA5ull;
+
+static const uint64_t P9N2_EX_0_L2_SHID0 = 0x20010AA5ull;
+//DUPS: 21010AA5,
+static const uint64_t P9N2_EX_10_L2_SHID0 = 0x34010AA5ull;
+//DUPS: 35010AA5,
+static const uint64_t P9N2_EX_11_L2_SHID0 = 0x36010AA5ull;
+//DUPS: 37010AA5,
+static const uint64_t P9N2_EX_1_L2_SHID0 = 0x22010AA5ull;
+//DUPS: 23010AA5,
+static const uint64_t P9N2_EX_2_L2_SHID0 = 0x24010AA5ull;
+//DUPS: 25010AA5,
+static const uint64_t P9N2_EX_3_L2_SHID0 = 0x26010AA5ull;
+//DUPS: 27010AA5,
+static const uint64_t P9N2_EX_4_L2_SHID0 = 0x28010AA5ull;
+//DUPS: 29010AA5,
+static const uint64_t P9N2_EX_5_L2_SHID0 = 0x2A010AA5ull;
+//DUPS: 2B010AA5,
+static const uint64_t P9N2_EX_6_L2_SHID0 = 0x2C010AA5ull;
+//DUPS: 2D010AA5,
+static const uint64_t P9N2_EX_7_L2_SHID0 = 0x2F010AA5ull;
+//DUPS: 2F010AA5,
+static const uint64_t P9N2_EX_8_L2_SHID0 = 0x30010AA5ull;
+//DUPS: 31010AA5,
+static const uint64_t P9N2_EX_9_L2_SHID0 = 0x32010AA5ull;
+//DUPS: 33010AA5,
+static const uint64_t P9N2_EX_L2_SHID0 = 0x20010AA5ull;
+//DUPS: 21010AA5,
+
+static const uint64_t P9N2_C_SIER_MASK = 0x20010AAEull;
+
+static const uint64_t P9N2_C_0_SIER_MASK = 0x20010AAEull;
+
+static const uint64_t P9N2_C_1_SIER_MASK = 0x21010AAEull;
+
+static const uint64_t P9N2_C_2_SIER_MASK = 0x22010AAEull;
+
+static const uint64_t P9N2_C_3_SIER_MASK = 0x23010AAEull;
+
+static const uint64_t P9N2_C_4_SIER_MASK = 0x24010AAEull;
+
+static const uint64_t P9N2_C_5_SIER_MASK = 0x25010AAEull;
+
+static const uint64_t P9N2_C_6_SIER_MASK = 0x26010AAEull;
+
+static const uint64_t P9N2_C_7_SIER_MASK = 0x27010AAEull;
+
+static const uint64_t P9N2_C_8_SIER_MASK = 0x28010AAEull;
+
+static const uint64_t P9N2_C_9_SIER_MASK = 0x29010AAEull;
+
+static const uint64_t P9N2_C_10_SIER_MASK = 0x2A010AAEull;
+
+static const uint64_t P9N2_C_11_SIER_MASK = 0x2B010AAEull;
+
+static const uint64_t P9N2_C_12_SIER_MASK = 0x2C010AAEull;
+
+static const uint64_t P9N2_C_13_SIER_MASK = 0x2D010AAEull;
+
+static const uint64_t P9N2_C_14_SIER_MASK = 0x2E010AAEull;
+
+static const uint64_t P9N2_C_15_SIER_MASK = 0x2F010AAEull;
+
+static const uint64_t P9N2_C_16_SIER_MASK = 0x30010AAEull;
+
+static const uint64_t P9N2_C_17_SIER_MASK = 0x31010AAEull;
+
+static const uint64_t P9N2_C_18_SIER_MASK = 0x32010AAEull;
+
+static const uint64_t P9N2_C_19_SIER_MASK = 0x33010AAEull;
+
+static const uint64_t P9N2_C_20_SIER_MASK = 0x34010AAEull;
+
+static const uint64_t P9N2_C_21_SIER_MASK = 0x35010AAEull;
+
+static const uint64_t P9N2_C_22_SIER_MASK = 0x36010AAEull;
+
+static const uint64_t P9N2_C_23_SIER_MASK = 0x37010AAEull;
+
+static const uint64_t P9N2_EX_SIER_MASK = 0x20010AAEull;
+//DUPS: 21010AAE,
+static const uint64_t P9N2_EX_0_SIER_MASK = 0x20010AAEull;
+//DUPS: 21010AAE,
+static const uint64_t P9N2_EX_1_SIER_MASK = 0x22010AAEull;
+//DUPS: 23010AAE,
+static const uint64_t P9N2_EX_2_SIER_MASK = 0x24010AAEull;
+//DUPS: 25010AAE,
+static const uint64_t P9N2_EX_3_SIER_MASK = 0x26010AAEull;
+//DUPS: 27010AAE,
+static const uint64_t P9N2_EX_4_SIER_MASK = 0x28010AAEull;
+//DUPS: 29010AAE,
+static const uint64_t P9N2_EX_5_SIER_MASK = 0x2A010AAEull;
+//DUPS: 2B010AAE,
+static const uint64_t P9N2_EX_6_SIER_MASK = 0x2C010AAEull;
+//DUPS: 2D010AAE,
+static const uint64_t P9N2_EX_7_SIER_MASK = 0x2F010AAEull;
+//DUPS: 2F010AAE,
+static const uint64_t P9N2_EX_8_SIER_MASK = 0x30010AAEull;
+//DUPS: 31010AAE,
+static const uint64_t P9N2_EX_9_SIER_MASK = 0x32010AAEull;
+//DUPS: 33010AAE,
+static const uint64_t P9N2_EX_10_SIER_MASK = 0x34010AAEull;
+//DUPS: 35010AAE,
+static const uint64_t P9N2_EX_11_SIER_MASK = 0x36010AAEull;
+//DUPS: 37010AAE,
+
+static const uint64_t P9N2_C_SKITTER_CLKSRC_REG = 0x20050016ull;
+
+static const uint64_t P9N2_C_0_SKITTER_CLKSRC_REG = 0x20050016ull;
+
+static const uint64_t P9N2_C_1_SKITTER_CLKSRC_REG = 0x21050016ull;
+
+static const uint64_t P9N2_C_2_SKITTER_CLKSRC_REG = 0x22050016ull;
+
+static const uint64_t P9N2_C_3_SKITTER_CLKSRC_REG = 0x23050016ull;
+
+static const uint64_t P9N2_C_4_SKITTER_CLKSRC_REG = 0x24050016ull;
+
+static const uint64_t P9N2_C_5_SKITTER_CLKSRC_REG = 0x25050016ull;
+
+static const uint64_t P9N2_C_6_SKITTER_CLKSRC_REG = 0x26050016ull;
+
+static const uint64_t P9N2_C_7_SKITTER_CLKSRC_REG = 0x27050016ull;
+
+static const uint64_t P9N2_C_8_SKITTER_CLKSRC_REG = 0x28050016ull;
+
+static const uint64_t P9N2_C_9_SKITTER_CLKSRC_REG = 0x29050016ull;
+
+static const uint64_t P9N2_C_10_SKITTER_CLKSRC_REG = 0x2A050016ull;
+
+static const uint64_t P9N2_C_11_SKITTER_CLKSRC_REG = 0x2B050016ull;
+
+static const uint64_t P9N2_C_12_SKITTER_CLKSRC_REG = 0x2C050016ull;
+
+static const uint64_t P9N2_C_13_SKITTER_CLKSRC_REG = 0x2D050016ull;
+
+static const uint64_t P9N2_C_14_SKITTER_CLKSRC_REG = 0x2E050016ull;
+
+static const uint64_t P9N2_C_15_SKITTER_CLKSRC_REG = 0x2F050016ull;
+
+static const uint64_t P9N2_C_16_SKITTER_CLKSRC_REG = 0x30050016ull;
+
+static const uint64_t P9N2_C_17_SKITTER_CLKSRC_REG = 0x31050016ull;
+
+static const uint64_t P9N2_C_18_SKITTER_CLKSRC_REG = 0x32050016ull;
+
+static const uint64_t P9N2_C_19_SKITTER_CLKSRC_REG = 0x33050016ull;
+
+static const uint64_t P9N2_C_20_SKITTER_CLKSRC_REG = 0x34050016ull;
+
+static const uint64_t P9N2_C_21_SKITTER_CLKSRC_REG = 0x35050016ull;
+
+static const uint64_t P9N2_C_22_SKITTER_CLKSRC_REG = 0x36050016ull;
+
+static const uint64_t P9N2_C_23_SKITTER_CLKSRC_REG = 0x37050016ull;
+
+static const uint64_t P9N2_EQ_SKITTER_CLKSRC_REG = 0x10050016ull;
+
+static const uint64_t P9N2_EQ_0_SKITTER_CLKSRC_REG = 0x10050016ull;
+
+static const uint64_t P9N2_EQ_1_SKITTER_CLKSRC_REG = 0x11050016ull;
+
+static const uint64_t P9N2_EQ_2_SKITTER_CLKSRC_REG = 0x12050016ull;
+
+static const uint64_t P9N2_EQ_3_SKITTER_CLKSRC_REG = 0x13050016ull;
+
+static const uint64_t P9N2_EQ_4_SKITTER_CLKSRC_REG = 0x14050016ull;
+
+static const uint64_t P9N2_EQ_5_SKITTER_CLKSRC_REG = 0x15050016ull;
+
+static const uint64_t P9N2_EX_SKITTER_CLKSRC_REG = 0x20050016ull;
+//DUPS: 21050016,
+static const uint64_t P9N2_EX_0_SKITTER_CLKSRC_REG = 0x20050016ull;
+//DUPS: 21050016,
+static const uint64_t P9N2_EX_1_SKITTER_CLKSRC_REG = 0x22050016ull;
+//DUPS: 23050016,
+static const uint64_t P9N2_EX_2_SKITTER_CLKSRC_REG = 0x24050016ull;
+//DUPS: 25050016,
+static const uint64_t P9N2_EX_3_SKITTER_CLKSRC_REG = 0x26050016ull;
+//DUPS: 27050016,
+static const uint64_t P9N2_EX_4_SKITTER_CLKSRC_REG = 0x28050016ull;
+//DUPS: 29050016,
+static const uint64_t P9N2_EX_5_SKITTER_CLKSRC_REG = 0x2A050016ull;
+//DUPS: 2B050016,
+static const uint64_t P9N2_EX_6_SKITTER_CLKSRC_REG = 0x2C050016ull;
+//DUPS: 2D050016,
+static const uint64_t P9N2_EX_7_SKITTER_CLKSRC_REG = 0x2F050016ull;
+//DUPS: 2F050016,
+static const uint64_t P9N2_EX_8_SKITTER_CLKSRC_REG = 0x30050016ull;
+//DUPS: 31050016,
+static const uint64_t P9N2_EX_9_SKITTER_CLKSRC_REG = 0x32050016ull;
+//DUPS: 33050016,
+static const uint64_t P9N2_EX_10_SKITTER_CLKSRC_REG = 0x34050016ull;
+//DUPS: 35050016,
+static const uint64_t P9N2_EX_11_SKITTER_CLKSRC_REG = 0x36050016ull;
+//DUPS: 37050016,
+
+static const uint64_t P9N2_C_SKITTER_DATA0 = 0x20050019ull;
+
+static const uint64_t P9N2_C_0_SKITTER_DATA0 = 0x20050019ull;
+
+static const uint64_t P9N2_C_1_SKITTER_DATA0 = 0x21050019ull;
+
+static const uint64_t P9N2_C_2_SKITTER_DATA0 = 0x22050019ull;
+
+static const uint64_t P9N2_C_3_SKITTER_DATA0 = 0x23050019ull;
+
+static const uint64_t P9N2_C_4_SKITTER_DATA0 = 0x24050019ull;
+
+static const uint64_t P9N2_C_5_SKITTER_DATA0 = 0x25050019ull;
+
+static const uint64_t P9N2_C_6_SKITTER_DATA0 = 0x26050019ull;
+
+static const uint64_t P9N2_C_7_SKITTER_DATA0 = 0x27050019ull;
+
+static const uint64_t P9N2_C_8_SKITTER_DATA0 = 0x28050019ull;
+
+static const uint64_t P9N2_C_9_SKITTER_DATA0 = 0x29050019ull;
+
+static const uint64_t P9N2_C_10_SKITTER_DATA0 = 0x2A050019ull;
+
+static const uint64_t P9N2_C_11_SKITTER_DATA0 = 0x2B050019ull;
+
+static const uint64_t P9N2_C_12_SKITTER_DATA0 = 0x2C050019ull;
+
+static const uint64_t P9N2_C_13_SKITTER_DATA0 = 0x2D050019ull;
+
+static const uint64_t P9N2_C_14_SKITTER_DATA0 = 0x2E050019ull;
+
+static const uint64_t P9N2_C_15_SKITTER_DATA0 = 0x2F050019ull;
+
+static const uint64_t P9N2_C_16_SKITTER_DATA0 = 0x30050019ull;
+
+static const uint64_t P9N2_C_17_SKITTER_DATA0 = 0x31050019ull;
+
+static const uint64_t P9N2_C_18_SKITTER_DATA0 = 0x32050019ull;
+
+static const uint64_t P9N2_C_19_SKITTER_DATA0 = 0x33050019ull;
+
+static const uint64_t P9N2_C_20_SKITTER_DATA0 = 0x34050019ull;
+
+static const uint64_t P9N2_C_21_SKITTER_DATA0 = 0x35050019ull;
+
+static const uint64_t P9N2_C_22_SKITTER_DATA0 = 0x36050019ull;
+
+static const uint64_t P9N2_C_23_SKITTER_DATA0 = 0x37050019ull;
+
+static const uint64_t P9N2_EQ_SKITTER_DATA0 = 0x10050019ull;
+
+static const uint64_t P9N2_EQ_0_SKITTER_DATA0 = 0x10050019ull;
+
+static const uint64_t P9N2_EQ_1_SKITTER_DATA0 = 0x11050019ull;
+
+static const uint64_t P9N2_EQ_2_SKITTER_DATA0 = 0x12050019ull;
+
+static const uint64_t P9N2_EQ_3_SKITTER_DATA0 = 0x13050019ull;
+
+static const uint64_t P9N2_EQ_4_SKITTER_DATA0 = 0x14050019ull;
+
+static const uint64_t P9N2_EQ_5_SKITTER_DATA0 = 0x15050019ull;
+
+static const uint64_t P9N2_EX_SKITTER_DATA0 = 0x20050019ull;
+//DUPS: 21050019,
+static const uint64_t P9N2_EX_0_SKITTER_DATA0 = 0x20050019ull;
+//DUPS: 21050019,
+static const uint64_t P9N2_EX_1_SKITTER_DATA0 = 0x22050019ull;
+//DUPS: 23050019,
+static const uint64_t P9N2_EX_2_SKITTER_DATA0 = 0x24050019ull;
+//DUPS: 25050019,
+static const uint64_t P9N2_EX_3_SKITTER_DATA0 = 0x26050019ull;
+//DUPS: 27050019,
+static const uint64_t P9N2_EX_4_SKITTER_DATA0 = 0x28050019ull;
+//DUPS: 29050019,
+static const uint64_t P9N2_EX_5_SKITTER_DATA0 = 0x2A050019ull;
+//DUPS: 2B050019,
+static const uint64_t P9N2_EX_6_SKITTER_DATA0 = 0x2C050019ull;
+//DUPS: 2D050019,
+static const uint64_t P9N2_EX_7_SKITTER_DATA0 = 0x2F050019ull;
+//DUPS: 2F050019,
+static const uint64_t P9N2_EX_8_SKITTER_DATA0 = 0x30050019ull;
+//DUPS: 31050019,
+static const uint64_t P9N2_EX_9_SKITTER_DATA0 = 0x32050019ull;
+//DUPS: 33050019,
+static const uint64_t P9N2_EX_10_SKITTER_DATA0 = 0x34050019ull;
+//DUPS: 35050019,
+static const uint64_t P9N2_EX_11_SKITTER_DATA0 = 0x36050019ull;
+//DUPS: 37050019,
+
+static const uint64_t P9N2_C_SKITTER_DATA1 = 0x2005001Aull;
+
+static const uint64_t P9N2_C_0_SKITTER_DATA1 = 0x2005001Aull;
+
+static const uint64_t P9N2_C_1_SKITTER_DATA1 = 0x2105001Aull;
+
+static const uint64_t P9N2_C_2_SKITTER_DATA1 = 0x2205001Aull;
+
+static const uint64_t P9N2_C_3_SKITTER_DATA1 = 0x2305001Aull;
+
+static const uint64_t P9N2_C_4_SKITTER_DATA1 = 0x2405001Aull;
+
+static const uint64_t P9N2_C_5_SKITTER_DATA1 = 0x2505001Aull;
+
+static const uint64_t P9N2_C_6_SKITTER_DATA1 = 0x2605001Aull;
+
+static const uint64_t P9N2_C_7_SKITTER_DATA1 = 0x2705001Aull;
+
+static const uint64_t P9N2_C_8_SKITTER_DATA1 = 0x2805001Aull;
+
+static const uint64_t P9N2_C_9_SKITTER_DATA1 = 0x2905001Aull;
+
+static const uint64_t P9N2_C_10_SKITTER_DATA1 = 0x2A05001Aull;
+
+static const uint64_t P9N2_C_11_SKITTER_DATA1 = 0x2B05001Aull;
+
+static const uint64_t P9N2_C_12_SKITTER_DATA1 = 0x2C05001Aull;
+
+static const uint64_t P9N2_C_13_SKITTER_DATA1 = 0x2D05001Aull;
+
+static const uint64_t P9N2_C_14_SKITTER_DATA1 = 0x2E05001Aull;
+
+static const uint64_t P9N2_C_15_SKITTER_DATA1 = 0x2F05001Aull;
+
+static const uint64_t P9N2_C_16_SKITTER_DATA1 = 0x3005001Aull;
+
+static const uint64_t P9N2_C_17_SKITTER_DATA1 = 0x3105001Aull;
+
+static const uint64_t P9N2_C_18_SKITTER_DATA1 = 0x3205001Aull;
+
+static const uint64_t P9N2_C_19_SKITTER_DATA1 = 0x3305001Aull;
+
+static const uint64_t P9N2_C_20_SKITTER_DATA1 = 0x3405001Aull;
+
+static const uint64_t P9N2_C_21_SKITTER_DATA1 = 0x3505001Aull;
+
+static const uint64_t P9N2_C_22_SKITTER_DATA1 = 0x3605001Aull;
+
+static const uint64_t P9N2_C_23_SKITTER_DATA1 = 0x3705001Aull;
+
+static const uint64_t P9N2_EQ_SKITTER_DATA1 = 0x1005001Aull;
+
+static const uint64_t P9N2_EQ_0_SKITTER_DATA1 = 0x1005001Aull;
+
+static const uint64_t P9N2_EQ_1_SKITTER_DATA1 = 0x1105001Aull;
+
+static const uint64_t P9N2_EQ_2_SKITTER_DATA1 = 0x1205001Aull;
+
+static const uint64_t P9N2_EQ_3_SKITTER_DATA1 = 0x1305001Aull;
+
+static const uint64_t P9N2_EQ_4_SKITTER_DATA1 = 0x1405001Aull;
+
+static const uint64_t P9N2_EQ_5_SKITTER_DATA1 = 0x1505001Aull;
+
+static const uint64_t P9N2_EX_SKITTER_DATA1 = 0x2005001Aull;
+//DUPS: 2105001A,
+static const uint64_t P9N2_EX_0_SKITTER_DATA1 = 0x2005001Aull;
+//DUPS: 2105001A,
+static const uint64_t P9N2_EX_1_SKITTER_DATA1 = 0x2205001Aull;
+//DUPS: 2305001A,
+static const uint64_t P9N2_EX_2_SKITTER_DATA1 = 0x2405001Aull;
+//DUPS: 2505001A,
+static const uint64_t P9N2_EX_3_SKITTER_DATA1 = 0x2605001Aull;
+//DUPS: 2705001A,
+static const uint64_t P9N2_EX_4_SKITTER_DATA1 = 0x2805001Aull;
+//DUPS: 2905001A,
+static const uint64_t P9N2_EX_5_SKITTER_DATA1 = 0x2A05001Aull;
+//DUPS: 2B05001A,
+static const uint64_t P9N2_EX_6_SKITTER_DATA1 = 0x2C05001Aull;
+//DUPS: 2D05001A,
+static const uint64_t P9N2_EX_7_SKITTER_DATA1 = 0x2F05001Aull;
+//DUPS: 2F05001A,
+static const uint64_t P9N2_EX_8_SKITTER_DATA1 = 0x3005001Aull;
+//DUPS: 3105001A,
+static const uint64_t P9N2_EX_9_SKITTER_DATA1 = 0x3205001Aull;
+//DUPS: 3305001A,
+static const uint64_t P9N2_EX_10_SKITTER_DATA1 = 0x3405001Aull;
+//DUPS: 3505001A,
+static const uint64_t P9N2_EX_11_SKITTER_DATA1 = 0x3605001Aull;
+//DUPS: 3705001A,
+
+static const uint64_t P9N2_C_SKITTER_DATA2 = 0x2005001Bull;
+
+static const uint64_t P9N2_C_0_SKITTER_DATA2 = 0x2005001Bull;
+
+static const uint64_t P9N2_C_1_SKITTER_DATA2 = 0x2105001Bull;
+
+static const uint64_t P9N2_C_2_SKITTER_DATA2 = 0x2205001Bull;
+
+static const uint64_t P9N2_C_3_SKITTER_DATA2 = 0x2305001Bull;
+
+static const uint64_t P9N2_C_4_SKITTER_DATA2 = 0x2405001Bull;
+
+static const uint64_t P9N2_C_5_SKITTER_DATA2 = 0x2505001Bull;
+
+static const uint64_t P9N2_C_6_SKITTER_DATA2 = 0x2605001Bull;
+
+static const uint64_t P9N2_C_7_SKITTER_DATA2 = 0x2705001Bull;
+
+static const uint64_t P9N2_C_8_SKITTER_DATA2 = 0x2805001Bull;
+
+static const uint64_t P9N2_C_9_SKITTER_DATA2 = 0x2905001Bull;
+
+static const uint64_t P9N2_C_10_SKITTER_DATA2 = 0x2A05001Bull;
+
+static const uint64_t P9N2_C_11_SKITTER_DATA2 = 0x2B05001Bull;
+
+static const uint64_t P9N2_C_12_SKITTER_DATA2 = 0x2C05001Bull;
+
+static const uint64_t P9N2_C_13_SKITTER_DATA2 = 0x2D05001Bull;
+
+static const uint64_t P9N2_C_14_SKITTER_DATA2 = 0x2E05001Bull;
+
+static const uint64_t P9N2_C_15_SKITTER_DATA2 = 0x2F05001Bull;
+
+static const uint64_t P9N2_C_16_SKITTER_DATA2 = 0x3005001Bull;
+
+static const uint64_t P9N2_C_17_SKITTER_DATA2 = 0x3105001Bull;
+
+static const uint64_t P9N2_C_18_SKITTER_DATA2 = 0x3205001Bull;
+
+static const uint64_t P9N2_C_19_SKITTER_DATA2 = 0x3305001Bull;
+
+static const uint64_t P9N2_C_20_SKITTER_DATA2 = 0x3405001Bull;
+
+static const uint64_t P9N2_C_21_SKITTER_DATA2 = 0x3505001Bull;
+
+static const uint64_t P9N2_C_22_SKITTER_DATA2 = 0x3605001Bull;
+
+static const uint64_t P9N2_C_23_SKITTER_DATA2 = 0x3705001Bull;
+
+static const uint64_t P9N2_EQ_SKITTER_DATA2 = 0x1005001Bull;
+
+static const uint64_t P9N2_EQ_0_SKITTER_DATA2 = 0x1005001Bull;
+
+static const uint64_t P9N2_EQ_1_SKITTER_DATA2 = 0x1105001Bull;
+
+static const uint64_t P9N2_EQ_2_SKITTER_DATA2 = 0x1205001Bull;
+
+static const uint64_t P9N2_EQ_3_SKITTER_DATA2 = 0x1305001Bull;
+
+static const uint64_t P9N2_EQ_4_SKITTER_DATA2 = 0x1405001Bull;
+
+static const uint64_t P9N2_EQ_5_SKITTER_DATA2 = 0x1505001Bull;
+
+static const uint64_t P9N2_EX_SKITTER_DATA2 = 0x2005001Bull;
+//DUPS: 2105001B,
+static const uint64_t P9N2_EX_0_SKITTER_DATA2 = 0x2005001Bull;
+//DUPS: 2105001B,
+static const uint64_t P9N2_EX_1_SKITTER_DATA2 = 0x2205001Bull;
+//DUPS: 2305001B,
+static const uint64_t P9N2_EX_2_SKITTER_DATA2 = 0x2405001Bull;
+//DUPS: 2505001B,
+static const uint64_t P9N2_EX_3_SKITTER_DATA2 = 0x2605001Bull;
+//DUPS: 2705001B,
+static const uint64_t P9N2_EX_4_SKITTER_DATA2 = 0x2805001Bull;
+//DUPS: 2905001B,
+static const uint64_t P9N2_EX_5_SKITTER_DATA2 = 0x2A05001Bull;
+//DUPS: 2B05001B,
+static const uint64_t P9N2_EX_6_SKITTER_DATA2 = 0x2C05001Bull;
+//DUPS: 2D05001B,
+static const uint64_t P9N2_EX_7_SKITTER_DATA2 = 0x2F05001Bull;
+//DUPS: 2F05001B,
+static const uint64_t P9N2_EX_8_SKITTER_DATA2 = 0x3005001Bull;
+//DUPS: 3105001B,
+static const uint64_t P9N2_EX_9_SKITTER_DATA2 = 0x3205001Bull;
+//DUPS: 3305001B,
+static const uint64_t P9N2_EX_10_SKITTER_DATA2 = 0x3405001Bull;
+//DUPS: 3505001B,
+static const uint64_t P9N2_EX_11_SKITTER_DATA2 = 0x3605001Bull;
+//DUPS: 3705001B,
+
+static const uint64_t P9N2_C_SKITTER_FORCE_REG = 0x20050014ull;
+
+static const uint64_t P9N2_C_0_SKITTER_FORCE_REG = 0x20050014ull;
+
+static const uint64_t P9N2_C_1_SKITTER_FORCE_REG = 0x21050014ull;
+
+static const uint64_t P9N2_C_2_SKITTER_FORCE_REG = 0x22050014ull;
+
+static const uint64_t P9N2_C_3_SKITTER_FORCE_REG = 0x23050014ull;
+
+static const uint64_t P9N2_C_4_SKITTER_FORCE_REG = 0x24050014ull;
+
+static const uint64_t P9N2_C_5_SKITTER_FORCE_REG = 0x25050014ull;
+
+static const uint64_t P9N2_C_6_SKITTER_FORCE_REG = 0x26050014ull;
+
+static const uint64_t P9N2_C_7_SKITTER_FORCE_REG = 0x27050014ull;
+
+static const uint64_t P9N2_C_8_SKITTER_FORCE_REG = 0x28050014ull;
+
+static const uint64_t P9N2_C_9_SKITTER_FORCE_REG = 0x29050014ull;
+
+static const uint64_t P9N2_C_10_SKITTER_FORCE_REG = 0x2A050014ull;
+
+static const uint64_t P9N2_C_11_SKITTER_FORCE_REG = 0x2B050014ull;
+
+static const uint64_t P9N2_C_12_SKITTER_FORCE_REG = 0x2C050014ull;
+
+static const uint64_t P9N2_C_13_SKITTER_FORCE_REG = 0x2D050014ull;
+
+static const uint64_t P9N2_C_14_SKITTER_FORCE_REG = 0x2E050014ull;
+
+static const uint64_t P9N2_C_15_SKITTER_FORCE_REG = 0x2F050014ull;
+
+static const uint64_t P9N2_C_16_SKITTER_FORCE_REG = 0x30050014ull;
+
+static const uint64_t P9N2_C_17_SKITTER_FORCE_REG = 0x31050014ull;
+
+static const uint64_t P9N2_C_18_SKITTER_FORCE_REG = 0x32050014ull;
+
+static const uint64_t P9N2_C_19_SKITTER_FORCE_REG = 0x33050014ull;
+
+static const uint64_t P9N2_C_20_SKITTER_FORCE_REG = 0x34050014ull;
+
+static const uint64_t P9N2_C_21_SKITTER_FORCE_REG = 0x35050014ull;
+
+static const uint64_t P9N2_C_22_SKITTER_FORCE_REG = 0x36050014ull;
+
+static const uint64_t P9N2_C_23_SKITTER_FORCE_REG = 0x37050014ull;
+
+static const uint64_t P9N2_EQ_SKITTER_FORCE_REG = 0x10050014ull;
+
+static const uint64_t P9N2_EQ_0_SKITTER_FORCE_REG = 0x10050014ull;
+
+static const uint64_t P9N2_EQ_1_SKITTER_FORCE_REG = 0x11050014ull;
+
+static const uint64_t P9N2_EQ_2_SKITTER_FORCE_REG = 0x12050014ull;
+
+static const uint64_t P9N2_EQ_3_SKITTER_FORCE_REG = 0x13050014ull;
+
+static const uint64_t P9N2_EQ_4_SKITTER_FORCE_REG = 0x14050014ull;
+
+static const uint64_t P9N2_EQ_5_SKITTER_FORCE_REG = 0x15050014ull;
+
+static const uint64_t P9N2_EX_SKITTER_FORCE_REG = 0x20050014ull;
+//DUPS: 21050014,
+static const uint64_t P9N2_EX_0_SKITTER_FORCE_REG = 0x20050014ull;
+//DUPS: 21050014,
+static const uint64_t P9N2_EX_1_SKITTER_FORCE_REG = 0x22050014ull;
+//DUPS: 23050014,
+static const uint64_t P9N2_EX_2_SKITTER_FORCE_REG = 0x24050014ull;
+//DUPS: 25050014,
+static const uint64_t P9N2_EX_3_SKITTER_FORCE_REG = 0x26050014ull;
+//DUPS: 27050014,
+static const uint64_t P9N2_EX_4_SKITTER_FORCE_REG = 0x28050014ull;
+//DUPS: 29050014,
+static const uint64_t P9N2_EX_5_SKITTER_FORCE_REG = 0x2A050014ull;
+//DUPS: 2B050014,
+static const uint64_t P9N2_EX_6_SKITTER_FORCE_REG = 0x2C050014ull;
+//DUPS: 2D050014,
+static const uint64_t P9N2_EX_7_SKITTER_FORCE_REG = 0x2F050014ull;
+//DUPS: 2F050014,
+static const uint64_t P9N2_EX_8_SKITTER_FORCE_REG = 0x30050014ull;
+//DUPS: 31050014,
+static const uint64_t P9N2_EX_9_SKITTER_FORCE_REG = 0x32050014ull;
+//DUPS: 33050014,
+static const uint64_t P9N2_EX_10_SKITTER_FORCE_REG = 0x34050014ull;
+//DUPS: 35050014,
+static const uint64_t P9N2_EX_11_SKITTER_FORCE_REG = 0x36050014ull;
+//DUPS: 37050014,
+
+static const uint64_t P9N2_C_SKITTER_MODE_REG = 0x20050010ull;
+
+static const uint64_t P9N2_C_0_SKITTER_MODE_REG = 0x20050010ull;
+
+static const uint64_t P9N2_C_1_SKITTER_MODE_REG = 0x21050010ull;
+
+static const uint64_t P9N2_C_2_SKITTER_MODE_REG = 0x22050010ull;
+
+static const uint64_t P9N2_C_3_SKITTER_MODE_REG = 0x23050010ull;
+
+static const uint64_t P9N2_C_4_SKITTER_MODE_REG = 0x24050010ull;
+
+static const uint64_t P9N2_C_5_SKITTER_MODE_REG = 0x25050010ull;
+
+static const uint64_t P9N2_C_6_SKITTER_MODE_REG = 0x26050010ull;
+
+static const uint64_t P9N2_C_7_SKITTER_MODE_REG = 0x27050010ull;
+
+static const uint64_t P9N2_C_8_SKITTER_MODE_REG = 0x28050010ull;
+
+static const uint64_t P9N2_C_9_SKITTER_MODE_REG = 0x29050010ull;
+
+static const uint64_t P9N2_C_10_SKITTER_MODE_REG = 0x2A050010ull;
+
+static const uint64_t P9N2_C_11_SKITTER_MODE_REG = 0x2B050010ull;
+
+static const uint64_t P9N2_C_12_SKITTER_MODE_REG = 0x2C050010ull;
+
+static const uint64_t P9N2_C_13_SKITTER_MODE_REG = 0x2D050010ull;
+
+static const uint64_t P9N2_C_14_SKITTER_MODE_REG = 0x2E050010ull;
+
+static const uint64_t P9N2_C_15_SKITTER_MODE_REG = 0x2F050010ull;
+
+static const uint64_t P9N2_C_16_SKITTER_MODE_REG = 0x30050010ull;
+
+static const uint64_t P9N2_C_17_SKITTER_MODE_REG = 0x31050010ull;
+
+static const uint64_t P9N2_C_18_SKITTER_MODE_REG = 0x32050010ull;
+
+static const uint64_t P9N2_C_19_SKITTER_MODE_REG = 0x33050010ull;
+
+static const uint64_t P9N2_C_20_SKITTER_MODE_REG = 0x34050010ull;
+
+static const uint64_t P9N2_C_21_SKITTER_MODE_REG = 0x35050010ull;
+
+static const uint64_t P9N2_C_22_SKITTER_MODE_REG = 0x36050010ull;
+
+static const uint64_t P9N2_C_23_SKITTER_MODE_REG = 0x37050010ull;
+
+static const uint64_t P9N2_EQ_SKITTER_MODE_REG = 0x10050010ull;
+
+static const uint64_t P9N2_EQ_0_SKITTER_MODE_REG = 0x10050010ull;
+
+static const uint64_t P9N2_EQ_1_SKITTER_MODE_REG = 0x11050010ull;
+
+static const uint64_t P9N2_EQ_2_SKITTER_MODE_REG = 0x12050010ull;
+
+static const uint64_t P9N2_EQ_3_SKITTER_MODE_REG = 0x13050010ull;
+
+static const uint64_t P9N2_EQ_4_SKITTER_MODE_REG = 0x14050010ull;
+
+static const uint64_t P9N2_EQ_5_SKITTER_MODE_REG = 0x15050010ull;
+
+static const uint64_t P9N2_EX_SKITTER_MODE_REG = 0x20050010ull;
+//DUPS: 21050010,
+static const uint64_t P9N2_EX_0_SKITTER_MODE_REG = 0x20050010ull;
+//DUPS: 21050010,
+static const uint64_t P9N2_EX_1_SKITTER_MODE_REG = 0x22050010ull;
+//DUPS: 23050010,
+static const uint64_t P9N2_EX_2_SKITTER_MODE_REG = 0x24050010ull;
+//DUPS: 25050010,
+static const uint64_t P9N2_EX_3_SKITTER_MODE_REG = 0x26050010ull;
+//DUPS: 27050010,
+static const uint64_t P9N2_EX_4_SKITTER_MODE_REG = 0x28050010ull;
+//DUPS: 29050010,
+static const uint64_t P9N2_EX_5_SKITTER_MODE_REG = 0x2A050010ull;
+//DUPS: 2B050010,
+static const uint64_t P9N2_EX_6_SKITTER_MODE_REG = 0x2C050010ull;
+//DUPS: 2D050010,
+static const uint64_t P9N2_EX_7_SKITTER_MODE_REG = 0x2F050010ull;
+//DUPS: 2F050010,
+static const uint64_t P9N2_EX_8_SKITTER_MODE_REG = 0x30050010ull;
+//DUPS: 31050010,
+static const uint64_t P9N2_EX_9_SKITTER_MODE_REG = 0x32050010ull;
+//DUPS: 33050010,
+static const uint64_t P9N2_EX_10_SKITTER_MODE_REG = 0x34050010ull;
+//DUPS: 35050010,
+static const uint64_t P9N2_EX_11_SKITTER_MODE_REG = 0x36050010ull;
+//DUPS: 37050010,
+
+static const uint64_t P9N2_C_SLAVE_CONFIG_REG = 0x200F001Eull;
+
+static const uint64_t P9N2_C_0_SLAVE_CONFIG_REG = 0x200F001Eull;
+
+static const uint64_t P9N2_C_1_SLAVE_CONFIG_REG = 0x210F001Eull;
+
+static const uint64_t P9N2_C_2_SLAVE_CONFIG_REG = 0x220F001Eull;
+
+static const uint64_t P9N2_C_3_SLAVE_CONFIG_REG = 0x230F001Eull;
+
+static const uint64_t P9N2_C_4_SLAVE_CONFIG_REG = 0x240F001Eull;
+
+static const uint64_t P9N2_C_5_SLAVE_CONFIG_REG = 0x250F001Eull;
+
+static const uint64_t P9N2_C_6_SLAVE_CONFIG_REG = 0x260F001Eull;
+
+static const uint64_t P9N2_C_7_SLAVE_CONFIG_REG = 0x270F001Eull;
+
+static const uint64_t P9N2_C_8_SLAVE_CONFIG_REG = 0x280F001Eull;
+
+static const uint64_t P9N2_C_9_SLAVE_CONFIG_REG = 0x290F001Eull;
+
+static const uint64_t P9N2_C_10_SLAVE_CONFIG_REG = 0x2A0F001Eull;
+
+static const uint64_t P9N2_C_11_SLAVE_CONFIG_REG = 0x2B0F001Eull;
+
+static const uint64_t P9N2_C_12_SLAVE_CONFIG_REG = 0x2C0F001Eull;
+
+static const uint64_t P9N2_C_13_SLAVE_CONFIG_REG = 0x2D0F001Eull;
+
+static const uint64_t P9N2_C_14_SLAVE_CONFIG_REG = 0x2E0F001Eull;
+
+static const uint64_t P9N2_C_15_SLAVE_CONFIG_REG = 0x2F0F001Eull;
+
+static const uint64_t P9N2_C_16_SLAVE_CONFIG_REG = 0x300F001Eull;
+
+static const uint64_t P9N2_C_17_SLAVE_CONFIG_REG = 0x310F001Eull;
+
+static const uint64_t P9N2_C_18_SLAVE_CONFIG_REG = 0x320F001Eull;
+
+static const uint64_t P9N2_C_19_SLAVE_CONFIG_REG = 0x330F001Eull;
+
+static const uint64_t P9N2_C_20_SLAVE_CONFIG_REG = 0x340F001Eull;
+
+static const uint64_t P9N2_C_21_SLAVE_CONFIG_REG = 0x350F001Eull;
+
+static const uint64_t P9N2_C_22_SLAVE_CONFIG_REG = 0x360F001Eull;
+
+static const uint64_t P9N2_C_23_SLAVE_CONFIG_REG = 0x370F001Eull;
+
+static const uint64_t P9N2_EQ_SLAVE_CONFIG_REG = 0x100F001Eull;
+
+static const uint64_t P9N2_EQ_0_SLAVE_CONFIG_REG = 0x100F001Eull;
+
+static const uint64_t P9N2_EQ_1_SLAVE_CONFIG_REG = 0x110F001Eull;
+
+static const uint64_t P9N2_EQ_2_SLAVE_CONFIG_REG = 0x120F001Eull;
+
+static const uint64_t P9N2_EQ_3_SLAVE_CONFIG_REG = 0x130F001Eull;
+
+static const uint64_t P9N2_EQ_4_SLAVE_CONFIG_REG = 0x140F001Eull;
+
+static const uint64_t P9N2_EQ_5_SLAVE_CONFIG_REG = 0x150F001Eull;
+
+static const uint64_t P9N2_EX_SLAVE_CONFIG_REG = 0x200F001Eull;
+//DUPS: 210F001E,
+static const uint64_t P9N2_EX_0_SLAVE_CONFIG_REG = 0x200F001Eull;
+//DUPS: 210F001E,
+static const uint64_t P9N2_EX_1_SLAVE_CONFIG_REG = 0x220F001Eull;
+//DUPS: 220F001E,
+static const uint64_t P9N2_EX_2_SLAVE_CONFIG_REG = 0x240F001Eull;
+//DUPS: 250F001E,
+static const uint64_t P9N2_EX_3_SLAVE_CONFIG_REG = 0x260F001Eull;
+//DUPS: 270F001E,
+static const uint64_t P9N2_EX_4_SLAVE_CONFIG_REG = 0x280F001Eull;
+//DUPS: 290F001E,
+static const uint64_t P9N2_EX_5_SLAVE_CONFIG_REG = 0x2A0F001Eull;
+//DUPS: 2B0F001E,
+static const uint64_t P9N2_EX_6_SLAVE_CONFIG_REG = 0x2C0F001Eull;
+//DUPS: 2D0F001E,
+static const uint64_t P9N2_EX_7_SLAVE_CONFIG_REG = 0x2E0F001Eull;
+//DUPS: 2F0F001E,
+static const uint64_t P9N2_EX_8_SLAVE_CONFIG_REG = 0x300F001Eull;
+//DUPS: 310F001E,
+static const uint64_t P9N2_EX_9_SLAVE_CONFIG_REG = 0x320F001Eull;
+//DUPS: 330F001E,
+static const uint64_t P9N2_EX_10_SLAVE_CONFIG_REG = 0x340F001Eull;
+//DUPS: 350F001E,
+static const uint64_t P9N2_EX_11_SLAVE_CONFIG_REG = 0x360F001Eull;
+//DUPS: 370F001E,
+
+static const uint64_t P9N2_C_SPATTN_SCOM = 0x20010A99ull;
+//DUPS: 20010A99,
+static const uint64_t P9N2_C_SPATTN_SCOM1 = 0x20010A98ull;
+//DUPS: 20010A98,
+static const uint64_t P9N2_C_SPATTN_SCOM2 = 0x20010A97ull;
+//DUPS: 20010A97,
+static const uint64_t P9N2_C_0_SPATTN_SCOM = 0x20010A99ull;
+//DUPS: 20010A99,
+static const uint64_t P9N2_C_0_SPATTN_SCOM1 = 0x20010A98ull;
+//DUPS: 20010A98,
+static const uint64_t P9N2_C_0_SPATTN_SCOM2 = 0x20010A97ull;
+//DUPS: 20010A97,
+static const uint64_t P9N2_C_1_SPATTN_SCOM = 0x21010A99ull;
+//DUPS: 21010A99,
+static const uint64_t P9N2_C_1_SPATTN_SCOM1 = 0x21010A98ull;
+//DUPS: 21010A98,
+static const uint64_t P9N2_C_1_SPATTN_SCOM2 = 0x21010A97ull;
+//DUPS: 21010A97,
+static const uint64_t P9N2_C_2_SPATTN_SCOM = 0x22010A99ull;
+//DUPS: 22010A99,
+static const uint64_t P9N2_C_2_SPATTN_SCOM1 = 0x22010A98ull;
+//DUPS: 22010A98,
+static const uint64_t P9N2_C_2_SPATTN_SCOM2 = 0x22010A97ull;
+//DUPS: 22010A97,
+static const uint64_t P9N2_C_3_SPATTN_SCOM = 0x23010A99ull;
+//DUPS: 23010A99,
+static const uint64_t P9N2_C_3_SPATTN_SCOM1 = 0x23010A98ull;
+//DUPS: 23010A98,
+static const uint64_t P9N2_C_3_SPATTN_SCOM2 = 0x23010A97ull;
+//DUPS: 23010A97,
+static const uint64_t P9N2_C_4_SPATTN_SCOM = 0x24010A99ull;
+//DUPS: 24010A99,
+static const uint64_t P9N2_C_4_SPATTN_SCOM1 = 0x24010A98ull;
+//DUPS: 24010A98,
+static const uint64_t P9N2_C_4_SPATTN_SCOM2 = 0x24010A97ull;
+//DUPS: 24010A97,
+static const uint64_t P9N2_C_5_SPATTN_SCOM = 0x25010A99ull;
+//DUPS: 25010A99,
+static const uint64_t P9N2_C_5_SPATTN_SCOM1 = 0x25010A98ull;
+//DUPS: 25010A98,
+static const uint64_t P9N2_C_5_SPATTN_SCOM2 = 0x25010A97ull;
+//DUPS: 25010A97,
+static const uint64_t P9N2_C_6_SPATTN_SCOM = 0x26010A99ull;
+//DUPS: 26010A99,
+static const uint64_t P9N2_C_6_SPATTN_SCOM1 = 0x26010A98ull;
+//DUPS: 26010A98,
+static const uint64_t P9N2_C_6_SPATTN_SCOM2 = 0x26010A97ull;
+//DUPS: 26010A97,
+static const uint64_t P9N2_C_7_SPATTN_SCOM = 0x27010A99ull;
+//DUPS: 27010A99,
+static const uint64_t P9N2_C_7_SPATTN_SCOM1 = 0x27010A98ull;
+//DUPS: 27010A98,
+static const uint64_t P9N2_C_7_SPATTN_SCOM2 = 0x27010A97ull;
+//DUPS: 27010A97,
+static const uint64_t P9N2_C_8_SPATTN_SCOM = 0x28010A99ull;
+//DUPS: 28010A99,
+static const uint64_t P9N2_C_8_SPATTN_SCOM1 = 0x28010A98ull;
+//DUPS: 28010A98,
+static const uint64_t P9N2_C_8_SPATTN_SCOM2 = 0x28010A97ull;
+//DUPS: 28010A97,
+static const uint64_t P9N2_C_9_SPATTN_SCOM = 0x29010A99ull;
+//DUPS: 29010A99,
+static const uint64_t P9N2_C_9_SPATTN_SCOM1 = 0x29010A98ull;
+//DUPS: 29010A98,
+static const uint64_t P9N2_C_9_SPATTN_SCOM2 = 0x29010A97ull;
+//DUPS: 29010A97,
+static const uint64_t P9N2_C_10_SPATTN_SCOM = 0x2A040004ull;
+//DUPS: 2A010A99,
+static const uint64_t P9N2_C_10_SPATTN_SCOM1 = 0x2A040005ull;
+//DUPS: 2A010A98,
+static const uint64_t P9N2_C_10_SPATTN_SCOM2 = 0x2A040006ull;
+//DUPS: 2A010A97,
+static const uint64_t P9N2_C_11_SPATTN_SCOM = 0x2B040004ull;
+//DUPS: 2B010A99,
+static const uint64_t P9N2_C_11_SPATTN_SCOM1 = 0x2B040005ull;
+//DUPS: 2B010A98,
+static const uint64_t P9N2_C_11_SPATTN_SCOM2 = 0x2B040006ull;
+//DUPS: 2B010A97,
+static const uint64_t P9N2_C_12_SPATTN_SCOM = 0x2C040004ull;
+//DUPS: 2C010A99,
+static const uint64_t P9N2_C_12_SPATTN_SCOM1 = 0x2C040005ull;
+//DUPS: 2C010A98,
+static const uint64_t P9N2_C_12_SPATTN_SCOM2 = 0x2C040006ull;
+//DUPS: 2C010A97,
+static const uint64_t P9N2_C_13_SPATTN_SCOM = 0x2D040004ull;
+//DUPS: 2D010A99,
+static const uint64_t P9N2_C_13_SPATTN_SCOM1 = 0x2D040005ull;
+//DUPS: 2D010A98,
+static const uint64_t P9N2_C_13_SPATTN_SCOM2 = 0x2D040006ull;
+//DUPS: 2D010A97,
+static const uint64_t P9N2_C_14_SPATTN_SCOM = 0x2E010A99ull;
+//DUPS: 2E010A99,
+static const uint64_t P9N2_C_14_SPATTN_SCOM1 = 0x2E010A98ull;
+//DUPS: 2E010A98,
+static const uint64_t P9N2_C_14_SPATTN_SCOM2 = 0x2E010A97ull;
+//DUPS: 2E010A97,
+static const uint64_t P9N2_C_15_SPATTN_SCOM = 0x2F040004ull;
+//DUPS: 2F010A99,
+static const uint64_t P9N2_C_15_SPATTN_SCOM1 = 0x2F040005ull;
+//DUPS: 2F010A98,
+static const uint64_t P9N2_C_15_SPATTN_SCOM2 = 0x2F040006ull;
+//DUPS: 2F010A97,
+static const uint64_t P9N2_C_16_SPATTN_SCOM = 0x30010A99ull;
+//DUPS: 30010A99,
+static const uint64_t P9N2_C_16_SPATTN_SCOM1 = 0x30010A98ull;
+//DUPS: 30010A98,
+static const uint64_t P9N2_C_16_SPATTN_SCOM2 = 0x30010A97ull;
+//DUPS: 30010A97,
+static const uint64_t P9N2_C_17_SPATTN_SCOM = 0x31010A99ull;
+//DUPS: 31010A99,
+static const uint64_t P9N2_C_17_SPATTN_SCOM1 = 0x31010A98ull;
+//DUPS: 31010A98,
+static const uint64_t P9N2_C_17_SPATTN_SCOM2 = 0x31010A97ull;
+//DUPS: 31010A97,
+static const uint64_t P9N2_C_18_SPATTN_SCOM = 0x32010A99ull;
+//DUPS: 32010A99,
+static const uint64_t P9N2_C_18_SPATTN_SCOM1 = 0x32010A98ull;
+//DUPS: 32010A98,
+static const uint64_t P9N2_C_18_SPATTN_SCOM2 = 0x32010A97ull;
+//DUPS: 32010A97,
+static const uint64_t P9N2_C_19_SPATTN_SCOM = 0x33010A99ull;
+//DUPS: 33010A99,
+static const uint64_t P9N2_C_19_SPATTN_SCOM1 = 0x33010A98ull;
+//DUPS: 33010A98,
+static const uint64_t P9N2_C_19_SPATTN_SCOM2 = 0x33010A97ull;
+//DUPS: 33010A97,
+static const uint64_t P9N2_C_20_SPATTN_SCOM = 0x34010A99ull;
+//DUPS: 34010A99,
+static const uint64_t P9N2_C_20_SPATTN_SCOM1 = 0x34010A98ull;
+//DUPS: 34010A98,
+static const uint64_t P9N2_C_20_SPATTN_SCOM2 = 0x34010A97ull;
+//DUPS: 34010A97,
+static const uint64_t P9N2_C_21_SPATTN_SCOM = 0x35010A99ull;
+//DUPS: 35010A99,
+static const uint64_t P9N2_C_21_SPATTN_SCOM1 = 0x35010A98ull;
+//DUPS: 35010A98,
+static const uint64_t P9N2_C_21_SPATTN_SCOM2 = 0x35010A97ull;
+//DUPS: 35010A97,
+static const uint64_t P9N2_C_22_SPATTN_SCOM = 0x36010A99ull;
+//DUPS: 36010A99,
+static const uint64_t P9N2_C_22_SPATTN_SCOM1 = 0x36010A98ull;
+//DUPS: 36010A98,
+static const uint64_t P9N2_C_22_SPATTN_SCOM2 = 0x36010A97ull;
+//DUPS: 36010A97,
+static const uint64_t P9N2_C_23_SPATTN_SCOM = 0x37010A99ull;
+//DUPS: 37010A99,
+static const uint64_t P9N2_C_23_SPATTN_SCOM1 = 0x37010A98ull;
+//DUPS: 37010A98,
+static const uint64_t P9N2_C_23_SPATTN_SCOM2 = 0x37010A97ull;
+//DUPS: 37010A97,
+static const uint64_t P9N2_EQ_SPATTN_SCOM = 0x10040004ull;
+
+static const uint64_t P9N2_EQ_SPATTN_SCOM1 = 0x10040005ull;
+
+static const uint64_t P9N2_EQ_SPATTN_SCOM2 = 0x10040006ull;
+
+static const uint64_t P9N2_EQ_0_SPATTN_SCOM = 0x10040004ull;
+
+static const uint64_t P9N2_EQ_0_SPATTN_SCOM1 = 0x10040005ull;
+
+static const uint64_t P9N2_EQ_0_SPATTN_SCOM2 = 0x10040006ull;
+
+static const uint64_t P9N2_EQ_1_SPATTN_SCOM = 0x11040004ull;
+
+static const uint64_t P9N2_EQ_1_SPATTN_SCOM1 = 0x11040005ull;
+
+static const uint64_t P9N2_EQ_1_SPATTN_SCOM2 = 0x11040006ull;
+
+static const uint64_t P9N2_EQ_2_SPATTN_SCOM = 0x12040004ull;
+
+static const uint64_t P9N2_EQ_2_SPATTN_SCOM1 = 0x12040005ull;
+
+static const uint64_t P9N2_EQ_2_SPATTN_SCOM2 = 0x12040006ull;
+
+static const uint64_t P9N2_EQ_3_SPATTN_SCOM = 0x13040004ull;
+
+static const uint64_t P9N2_EQ_3_SPATTN_SCOM1 = 0x13040005ull;
+
+static const uint64_t P9N2_EQ_3_SPATTN_SCOM2 = 0x13040006ull;
+
+static const uint64_t P9N2_EQ_4_SPATTN_SCOM = 0x14040004ull;
+
+static const uint64_t P9N2_EQ_4_SPATTN_SCOM1 = 0x14040005ull;
+
+static const uint64_t P9N2_EQ_4_SPATTN_SCOM2 = 0x14040006ull;
+
+static const uint64_t P9N2_EQ_5_SPATTN_SCOM = 0x15040004ull;
+
+static const uint64_t P9N2_EQ_5_SPATTN_SCOM1 = 0x15040005ull;
+
+static const uint64_t P9N2_EQ_5_SPATTN_SCOM2 = 0x15040006ull;
+
+static const uint64_t P9N2_EX_SPATTN_SCOM = 0x20010A99ull;
+//DUPS: 21040004, 21010A99, 20010A99,
+static const uint64_t P9N2_EX_SPATTN_SCOM1 = 0x20010A98ull;
+//DUPS: 21040005, 21010A98, 20010A98,
+static const uint64_t P9N2_EX_SPATTN_SCOM2 = 0x20040006ull;
+//DUPS: 21040006,
+static const uint64_t P9N2_EX_0_SPATTN_SCOM = 0x20010A99ull;
+//DUPS: 21040004, 21010A99, 20010A99,
+static const uint64_t P9N2_EX_0_SPATTN_SCOM1 = 0x20010A98ull;
+//DUPS: 21040005, 21010A98, 20010A98,
+static const uint64_t P9N2_EX_0_SPATTN_SCOM2 = 0x20040006ull;
+//DUPS: 21040006,
+static const uint64_t P9N2_EX_1_SPATTN_SCOM = 0x22010A99ull;
+//DUPS: 23040004, 23010A99, 22010A99,
+static const uint64_t P9N2_EX_1_SPATTN_SCOM1 = 0x22010A98ull;
+//DUPS: 23040005, 23010A98, 22010A98,
+static const uint64_t P9N2_EX_1_SPATTN_SCOM2 = 0x22040006ull;
+//DUPS: 23040006,
+static const uint64_t P9N2_EX_2_SPATTN_SCOM = 0x24010A99ull;
+//DUPS: 25040004, 25010A99, 24010A99,
+static const uint64_t P9N2_EX_2_SPATTN_SCOM1 = 0x24010A98ull;
+//DUPS: 25040005, 25010A98, 24010A98,
+static const uint64_t P9N2_EX_2_SPATTN_SCOM2 = 0x24040006ull;
+//DUPS: 25040006,
+static const uint64_t P9N2_EX_3_SPATTN_SCOM = 0x26010A99ull;
+//DUPS: 27040004, 27010A99, 26010A99,
+static const uint64_t P9N2_EX_3_SPATTN_SCOM1 = 0x26010A98ull;
+//DUPS: 27040005, 27010A98, 26010A98,
+static const uint64_t P9N2_EX_3_SPATTN_SCOM2 = 0x26040006ull;
+//DUPS: 27040006,
+static const uint64_t P9N2_EX_4_SPATTN_SCOM = 0x28010A99ull;
+//DUPS: 29040004, 29010A99, 28010A99,
+static const uint64_t P9N2_EX_4_SPATTN_SCOM1 = 0x28010A98ull;
+//DUPS: 29040005, 29010A98, 28010A98,
+static const uint64_t P9N2_EX_4_SPATTN_SCOM2 = 0x28040006ull;
+//DUPS: 29040006,
+static const uint64_t P9N2_EX_5_SPATTN_SCOM = 0x2A040004ull;
+//DUPS: 2B040004, 2B010A99, 2A010A99,
+static const uint64_t P9N2_EX_5_SPATTN_SCOM1 = 0x2A040005ull;
+//DUPS: 2B040005, 2B010A98, 2A010A98,
+static const uint64_t P9N2_EX_5_SPATTN_SCOM2 = 0x2A040006ull;
+//DUPS: 2B040006,
+static const uint64_t P9N2_EX_6_SPATTN_SCOM = 0x2C040004ull;
+//DUPS: 2D040004, 2D010A99, 2C010A99,
+static const uint64_t P9N2_EX_6_SPATTN_SCOM1 = 0x2C040005ull;
+//DUPS: 2D040005, 2D010A98, 2C010A98,
+static const uint64_t P9N2_EX_6_SPATTN_SCOM2 = 0x2C040006ull;
+//DUPS: 2D040006,
+static const uint64_t P9N2_EX_7_SPATTN_SCOM = 0x2F040004ull;
+//DUPS: 2F040004, 2F010A99, 2E010A99,
+static const uint64_t P9N2_EX_7_SPATTN_SCOM1 = 0x2F040005ull;
+//DUPS: 2F040005, 2F010A98, 2E010A98,
+static const uint64_t P9N2_EX_7_SPATTN_SCOM2 = 0x2F040006ull;
+//DUPS: 2F040006,
+static const uint64_t P9N2_EX_8_SPATTN_SCOM = 0x30010A99ull;
+//DUPS: 31040004, 31010A99, 30010A99,
+static const uint64_t P9N2_EX_8_SPATTN_SCOM1 = 0x30010A98ull;
+//DUPS: 31040005, 31010A98, 30010A98,
+static const uint64_t P9N2_EX_8_SPATTN_SCOM2 = 0x30040006ull;
+//DUPS: 31040006,
+static const uint64_t P9N2_EX_9_SPATTN_SCOM = 0x32010A99ull;
+//DUPS: 33040004, 33010A99, 32010A99,
+static const uint64_t P9N2_EX_9_SPATTN_SCOM1 = 0x32010A98ull;
+//DUPS: 33040005, 33010A98, 32010A98,
+static const uint64_t P9N2_EX_9_SPATTN_SCOM2 = 0x32040006ull;
+//DUPS: 33040006,
+static const uint64_t P9N2_EX_0_L2_SPATTN = 0x20010A97ull;
+//DUPS: 20010A97,
+static const uint64_t P9N2_EX_10_SPATTN_SCOM = 0x34010A99ull;
+//DUPS: 35040004, 35010A99, 34010A99,
+static const uint64_t P9N2_EX_10_SPATTN_SCOM1 = 0x34010A98ull;
+//DUPS: 35040005, 35010A98, 34010A98,
+static const uint64_t P9N2_EX_10_SPATTN_SCOM2 = 0x34040006ull;
+//DUPS: 35040006,
+static const uint64_t P9N2_EX_11_SPATTN_SCOM = 0x36010A99ull;
+//DUPS: 37040004, 37010A99, 36010A99,
+static const uint64_t P9N2_EX_11_SPATTN_SCOM1 = 0x36010A98ull;
+//DUPS: 37040005, 37010A98, 36010A98,
+static const uint64_t P9N2_EX_11_SPATTN_SCOM2 = 0x36040006ull;
+//DUPS: 37040006,
+static const uint64_t P9N2_EX_10_L2_SPATTN = 0x34010A97ull;
+//DUPS: 34010A97,
+static const uint64_t P9N2_EX_11_L2_SPATTN = 0x36010A97ull;
+//DUPS: 36010A97,
+static const uint64_t P9N2_EX_1_L2_SPATTN = 0x22010A97ull;
+//DUPS: 22010A97,
+static const uint64_t P9N2_EX_2_L2_SPATTN = 0x24010A97ull;
+//DUPS: 24010A97,
+static const uint64_t P9N2_EX_3_L2_SPATTN = 0x26010A97ull;
+//DUPS: 26010A97,
+static const uint64_t P9N2_EX_4_L2_SPATTN = 0x28010A97ull;
+//DUPS: 28010A97,
+static const uint64_t P9N2_EX_5_L2_SPATTN = 0x2B010A97ull;
+//DUPS: 2A010A97,
+static const uint64_t P9N2_EX_6_L2_SPATTN = 0x2D010A97ull;
+//DUPS: 2C010A97,
+static const uint64_t P9N2_EX_7_L2_SPATTN = 0x2F010A97ull;
+//DUPS: 2E010A97,
+static const uint64_t P9N2_EX_8_L2_SPATTN = 0x30010A97ull;
+//DUPS: 30010A97,
+static const uint64_t P9N2_EX_9_L2_SPATTN = 0x32010A97ull;
+//DUPS: 32010A97,
+static const uint64_t P9N2_EX_L2_SPATTN = 0x20010A97ull;
+//DUPS: 20010A97,
+
+static const uint64_t P9N2_C_SPATTN_MASK = 0x20010A9Aull;
+
+static const uint64_t P9N2_C_0_SPATTN_MASK = 0x20010A9Aull;
+
+static const uint64_t P9N2_C_1_SPATTN_MASK = 0x21010A9Aull;
+
+static const uint64_t P9N2_C_2_SPATTN_MASK = 0x22010A9Aull;
+
+static const uint64_t P9N2_C_3_SPATTN_MASK = 0x23010A9Aull;
+
+static const uint64_t P9N2_C_4_SPATTN_MASK = 0x24010A9Aull;
+
+static const uint64_t P9N2_C_5_SPATTN_MASK = 0x25010A9Aull;
+
+static const uint64_t P9N2_C_6_SPATTN_MASK = 0x26010A9Aull;
+
+static const uint64_t P9N2_C_7_SPATTN_MASK = 0x27010A9Aull;
+
+static const uint64_t P9N2_C_8_SPATTN_MASK = 0x28010A9Aull;
+
+static const uint64_t P9N2_C_9_SPATTN_MASK = 0x29010A9Aull;
+
+static const uint64_t P9N2_C_10_SPATTN_MASK = 0x2A010A9Aull;
+
+static const uint64_t P9N2_C_11_SPATTN_MASK = 0x2B010A9Aull;
+
+static const uint64_t P9N2_C_12_SPATTN_MASK = 0x2C010A9Aull;
+
+static const uint64_t P9N2_C_13_SPATTN_MASK = 0x2D010A9Aull;
+
+static const uint64_t P9N2_C_14_SPATTN_MASK = 0x2E010A9Aull;
+
+static const uint64_t P9N2_C_15_SPATTN_MASK = 0x2F010A9Aull;
+
+static const uint64_t P9N2_C_16_SPATTN_MASK = 0x30010A9Aull;
+
+static const uint64_t P9N2_C_17_SPATTN_MASK = 0x31010A9Aull;
+
+static const uint64_t P9N2_C_18_SPATTN_MASK = 0x32010A9Aull;
+
+static const uint64_t P9N2_C_19_SPATTN_MASK = 0x33010A9Aull;
+
+static const uint64_t P9N2_C_20_SPATTN_MASK = 0x34010A9Aull;
+
+static const uint64_t P9N2_C_21_SPATTN_MASK = 0x35010A9Aull;
+
+static const uint64_t P9N2_C_22_SPATTN_MASK = 0x36010A9Aull;
+
+static const uint64_t P9N2_C_23_SPATTN_MASK = 0x37010A9Aull;
+
+static const uint64_t P9N2_EX_0_L2_SPATTN_MASK = 0x20010A9Aull;
+//DUPS: 20010A9A,
+static const uint64_t P9N2_EX_10_L2_SPATTN_MASK = 0x34010A9Aull;
+//DUPS: 34010A9A,
+static const uint64_t P9N2_EX_11_L2_SPATTN_MASK = 0x36010A9Aull;
+//DUPS: 36010A9A,
+static const uint64_t P9N2_EX_1_L2_SPATTN_MASK = 0x22010A9Aull;
+//DUPS: 22010A9A,
+static const uint64_t P9N2_EX_2_L2_SPATTN_MASK = 0x24010A9Aull;
+//DUPS: 24010A9A,
+static const uint64_t P9N2_EX_3_L2_SPATTN_MASK = 0x26010A9Aull;
+//DUPS: 26010A9A,
+static const uint64_t P9N2_EX_4_L2_SPATTN_MASK = 0x28010A9Aull;
+//DUPS: 28010A9A,
+static const uint64_t P9N2_EX_5_L2_SPATTN_MASK = 0x2B010A9Aull;
+//DUPS: 2A010A9A,
+static const uint64_t P9N2_EX_6_L2_SPATTN_MASK = 0x2D010A9Aull;
+//DUPS: 2C010A9A,
+static const uint64_t P9N2_EX_7_L2_SPATTN_MASK = 0x2F010A9Aull;
+//DUPS: 2E010A9A,
+static const uint64_t P9N2_EX_8_L2_SPATTN_MASK = 0x30010A9Aull;
+//DUPS: 30010A9A,
+static const uint64_t P9N2_EX_9_L2_SPATTN_MASK = 0x32010A9Aull;
+//DUPS: 32010A9A,
+static const uint64_t P9N2_EX_L2_SPATTN_MASK = 0x20010A9Aull;
+//DUPS: 20010A9A,
+
+static const uint64_t P9N2_C_SPA_MASK = 0x20040007ull;
+
+static const uint64_t P9N2_C_0_SPA_MASK = 0x20040007ull;
+
+static const uint64_t P9N2_C_1_SPA_MASK = 0x21040007ull;
+
+static const uint64_t P9N2_C_2_SPA_MASK = 0x22040007ull;
+
+static const uint64_t P9N2_C_3_SPA_MASK = 0x23040007ull;
+
+static const uint64_t P9N2_C_4_SPA_MASK = 0x24040007ull;
+
+static const uint64_t P9N2_C_5_SPA_MASK = 0x25040007ull;
+
+static const uint64_t P9N2_C_6_SPA_MASK = 0x26040007ull;
+
+static const uint64_t P9N2_C_7_SPA_MASK = 0x27040007ull;
+
+static const uint64_t P9N2_C_8_SPA_MASK = 0x28040007ull;
+
+static const uint64_t P9N2_C_9_SPA_MASK = 0x29040007ull;
+
+static const uint64_t P9N2_C_10_SPA_MASK = 0x2A040007ull;
+
+static const uint64_t P9N2_C_11_SPA_MASK = 0x2B040007ull;
+
+static const uint64_t P9N2_C_12_SPA_MASK = 0x2C040007ull;
+
+static const uint64_t P9N2_C_13_SPA_MASK = 0x2D040007ull;
+
+static const uint64_t P9N2_C_14_SPA_MASK = 0x2E040007ull;
+
+static const uint64_t P9N2_C_15_SPA_MASK = 0x2F040007ull;
+
+static const uint64_t P9N2_C_16_SPA_MASK = 0x30040007ull;
+
+static const uint64_t P9N2_C_17_SPA_MASK = 0x31040007ull;
+
+static const uint64_t P9N2_C_18_SPA_MASK = 0x32040007ull;
+
+static const uint64_t P9N2_C_19_SPA_MASK = 0x33040007ull;
+
+static const uint64_t P9N2_C_20_SPA_MASK = 0x34040007ull;
+
+static const uint64_t P9N2_C_21_SPA_MASK = 0x35040007ull;
+
+static const uint64_t P9N2_C_22_SPA_MASK = 0x36040007ull;
+
+static const uint64_t P9N2_C_23_SPA_MASK = 0x37040007ull;
+
+static const uint64_t P9N2_EQ_SPA_MASK = 0x10040007ull;
+
+static const uint64_t P9N2_EQ_0_SPA_MASK = 0x10040007ull;
+
+static const uint64_t P9N2_EQ_1_SPA_MASK = 0x11040007ull;
+
+static const uint64_t P9N2_EQ_2_SPA_MASK = 0x12040007ull;
+
+static const uint64_t P9N2_EQ_3_SPA_MASK = 0x13040007ull;
+
+static const uint64_t P9N2_EQ_4_SPA_MASK = 0x14040007ull;
+
+static const uint64_t P9N2_EQ_5_SPA_MASK = 0x15040007ull;
+
+static const uint64_t P9N2_EX_SPA_MASK = 0x20040007ull;
+//DUPS: 21040007,
+static const uint64_t P9N2_EX_0_SPA_MASK = 0x20040007ull;
+//DUPS: 21040007,
+static const uint64_t P9N2_EX_1_SPA_MASK = 0x22040007ull;
+//DUPS: 23040007,
+static const uint64_t P9N2_EX_2_SPA_MASK = 0x24040007ull;
+//DUPS: 25040007,
+static const uint64_t P9N2_EX_3_SPA_MASK = 0x26040007ull;
+//DUPS: 27040007,
+static const uint64_t P9N2_EX_4_SPA_MASK = 0x28040007ull;
+//DUPS: 29040007,
+static const uint64_t P9N2_EX_5_SPA_MASK = 0x2A040007ull;
+//DUPS: 2B040007,
+static const uint64_t P9N2_EX_6_SPA_MASK = 0x2C040007ull;
+//DUPS: 2D040007,
+static const uint64_t P9N2_EX_7_SPA_MASK = 0x2F040007ull;
+//DUPS: 2F040007,
+static const uint64_t P9N2_EX_8_SPA_MASK = 0x30040007ull;
+//DUPS: 31040007,
+static const uint64_t P9N2_EX_9_SPA_MASK = 0x32040007ull;
+//DUPS: 33040007,
+static const uint64_t P9N2_EX_10_SPA_MASK = 0x34040007ull;
+//DUPS: 35040007,
+static const uint64_t P9N2_EX_11_SPA_MASK = 0x36040007ull;
+//DUPS: 37040007,
+
+static const uint64_t P9N2_C_SPR_COMMON_HOLD_OUT = 0x20010AB8ull;
+
+static const uint64_t P9N2_C_0_SPR_COMMON_HOLD_OUT = 0x20010AB8ull;
+
+static const uint64_t P9N2_C_1_SPR_COMMON_HOLD_OUT = 0x21010AB8ull;
+
+static const uint64_t P9N2_C_2_SPR_COMMON_HOLD_OUT = 0x22010AB8ull;
+
+static const uint64_t P9N2_C_3_SPR_COMMON_HOLD_OUT = 0x23010AB8ull;
+
+static const uint64_t P9N2_C_4_SPR_COMMON_HOLD_OUT = 0x24010AB8ull;
+
+static const uint64_t P9N2_C_5_SPR_COMMON_HOLD_OUT = 0x25010AB8ull;
+
+static const uint64_t P9N2_C_6_SPR_COMMON_HOLD_OUT = 0x26010AB8ull;
+
+static const uint64_t P9N2_C_7_SPR_COMMON_HOLD_OUT = 0x27010AB8ull;
+
+static const uint64_t P9N2_C_8_SPR_COMMON_HOLD_OUT = 0x28010AB8ull;
+
+static const uint64_t P9N2_C_9_SPR_COMMON_HOLD_OUT = 0x29010AB8ull;
+
+static const uint64_t P9N2_C_10_SPR_COMMON_HOLD_OUT = 0x2A010AB8ull;
+
+static const uint64_t P9N2_C_11_SPR_COMMON_HOLD_OUT = 0x2B010AB8ull;
+
+static const uint64_t P9N2_C_12_SPR_COMMON_HOLD_OUT = 0x2C010AB8ull;
+
+static const uint64_t P9N2_C_13_SPR_COMMON_HOLD_OUT = 0x2D010AB8ull;
+
+static const uint64_t P9N2_C_14_SPR_COMMON_HOLD_OUT = 0x2E010AB8ull;
+
+static const uint64_t P9N2_C_15_SPR_COMMON_HOLD_OUT = 0x2F010AB8ull;
+
+static const uint64_t P9N2_C_16_SPR_COMMON_HOLD_OUT = 0x30010AB8ull;
+
+static const uint64_t P9N2_C_17_SPR_COMMON_HOLD_OUT = 0x31010AB8ull;
+
+static const uint64_t P9N2_C_18_SPR_COMMON_HOLD_OUT = 0x32010AB8ull;
+
+static const uint64_t P9N2_C_19_SPR_COMMON_HOLD_OUT = 0x33010AB8ull;
+
+static const uint64_t P9N2_C_20_SPR_COMMON_HOLD_OUT = 0x34010AB8ull;
+
+static const uint64_t P9N2_C_21_SPR_COMMON_HOLD_OUT = 0x35010AB8ull;
+
+static const uint64_t P9N2_C_22_SPR_COMMON_HOLD_OUT = 0x36010AB8ull;
+
+static const uint64_t P9N2_C_23_SPR_COMMON_HOLD_OUT = 0x37010AB8ull;
+
+static const uint64_t P9N2_EX_SPR_COMMON_HOLD_OUT = 0x20010AB8ull;
+//DUPS: 20010AB8,
+static const uint64_t P9N2_EX_0_SPR_COMMON_HOLD_OUT = 0x20010AB8ull;
+//DUPS: 20010AB8,
+static const uint64_t P9N2_EX_1_SPR_COMMON_HOLD_OUT = 0x22010AB8ull;
+//DUPS: 22010AB8,
+static const uint64_t P9N2_EX_2_SPR_COMMON_HOLD_OUT = 0x24010AB8ull;
+//DUPS: 24010AB8,
+static const uint64_t P9N2_EX_3_SPR_COMMON_HOLD_OUT = 0x26010AB8ull;
+//DUPS: 26010AB8,
+static const uint64_t P9N2_EX_4_SPR_COMMON_HOLD_OUT = 0x28010AB8ull;
+//DUPS: 28010AB8,
+static const uint64_t P9N2_EX_5_SPR_COMMON_HOLD_OUT = 0x2B010AB8ull;
+//DUPS: 2A010AB8,
+static const uint64_t P9N2_EX_6_SPR_COMMON_HOLD_OUT = 0x2D010AB8ull;
+//DUPS: 2C010AB8,
+static const uint64_t P9N2_EX_7_SPR_COMMON_HOLD_OUT = 0x2F010AB8ull;
+//DUPS: 2E010AB8,
+static const uint64_t P9N2_EX_8_SPR_COMMON_HOLD_OUT = 0x30010AB8ull;
+//DUPS: 30010AB8,
+static const uint64_t P9N2_EX_9_SPR_COMMON_HOLD_OUT = 0x32010AB8ull;
+//DUPS: 32010AB8,
+static const uint64_t P9N2_EX_10_SPR_COMMON_HOLD_OUT = 0x34010AB8ull;
+//DUPS: 34010AB8,
+static const uint64_t P9N2_EX_11_SPR_COMMON_HOLD_OUT = 0x36010AB8ull;
+//DUPS: 36010AB8,
+
+static const uint64_t P9N2_C_SPR_CORE_HOLD_OUT = 0x20010AB5ull;
+
+static const uint64_t P9N2_C_0_SPR_CORE_HOLD_OUT = 0x20010AB5ull;
+
+static const uint64_t P9N2_C_1_SPR_CORE_HOLD_OUT = 0x21010AB5ull;
+
+static const uint64_t P9N2_C_2_SPR_CORE_HOLD_OUT = 0x22010AB5ull;
+
+static const uint64_t P9N2_C_3_SPR_CORE_HOLD_OUT = 0x23010AB5ull;
+
+static const uint64_t P9N2_C_4_SPR_CORE_HOLD_OUT = 0x24010AB5ull;
+
+static const uint64_t P9N2_C_5_SPR_CORE_HOLD_OUT = 0x25010AB5ull;
+
+static const uint64_t P9N2_C_6_SPR_CORE_HOLD_OUT = 0x26010AB5ull;
+
+static const uint64_t P9N2_C_7_SPR_CORE_HOLD_OUT = 0x27010AB5ull;
+
+static const uint64_t P9N2_C_8_SPR_CORE_HOLD_OUT = 0x28010AB5ull;
+
+static const uint64_t P9N2_C_9_SPR_CORE_HOLD_OUT = 0x29010AB5ull;
+
+static const uint64_t P9N2_C_10_SPR_CORE_HOLD_OUT = 0x2A010AB5ull;
+
+static const uint64_t P9N2_C_11_SPR_CORE_HOLD_OUT = 0x2B010AB5ull;
+
+static const uint64_t P9N2_C_12_SPR_CORE_HOLD_OUT = 0x2C010AB5ull;
+
+static const uint64_t P9N2_C_13_SPR_CORE_HOLD_OUT = 0x2D010AB5ull;
+
+static const uint64_t P9N2_C_14_SPR_CORE_HOLD_OUT = 0x2E010AB5ull;
+
+static const uint64_t P9N2_C_15_SPR_CORE_HOLD_OUT = 0x2F010AB5ull;
+
+static const uint64_t P9N2_C_16_SPR_CORE_HOLD_OUT = 0x30010AB5ull;
+
+static const uint64_t P9N2_C_17_SPR_CORE_HOLD_OUT = 0x31010AB5ull;
+
+static const uint64_t P9N2_C_18_SPR_CORE_HOLD_OUT = 0x32010AB5ull;
+
+static const uint64_t P9N2_C_19_SPR_CORE_HOLD_OUT = 0x33010AB5ull;
+
+static const uint64_t P9N2_C_20_SPR_CORE_HOLD_OUT = 0x34010AB5ull;
+
+static const uint64_t P9N2_C_21_SPR_CORE_HOLD_OUT = 0x35010AB5ull;
+
+static const uint64_t P9N2_C_22_SPR_CORE_HOLD_OUT = 0x36010AB5ull;
+
+static const uint64_t P9N2_C_23_SPR_CORE_HOLD_OUT = 0x37010AB5ull;
+
+static const uint64_t P9N2_EX_0_L2_SPR_CORE_HOLD_OUT = 0x20010AB5ull;
+//DUPS: 21010AB5,
+static const uint64_t P9N2_EX_10_L2_SPR_CORE_HOLD_OUT = 0x34010AB5ull;
+//DUPS: 35010AB5,
+static const uint64_t P9N2_EX_11_L2_SPR_CORE_HOLD_OUT = 0x36010AB5ull;
+//DUPS: 37010AB5,
+static const uint64_t P9N2_EX_1_L2_SPR_CORE_HOLD_OUT = 0x22010AB5ull;
+//DUPS: 23010AB5,
+static const uint64_t P9N2_EX_2_L2_SPR_CORE_HOLD_OUT = 0x24010AB5ull;
+//DUPS: 25010AB5,
+static const uint64_t P9N2_EX_3_L2_SPR_CORE_HOLD_OUT = 0x26010AB5ull;
+//DUPS: 27010AB5,
+static const uint64_t P9N2_EX_4_L2_SPR_CORE_HOLD_OUT = 0x28010AB5ull;
+//DUPS: 29010AB5,
+static const uint64_t P9N2_EX_5_L2_SPR_CORE_HOLD_OUT = 0x2A010AB5ull;
+//DUPS: 2B010AB5,
+static const uint64_t P9N2_EX_6_L2_SPR_CORE_HOLD_OUT = 0x2C010AB5ull;
+//DUPS: 2D010AB5,
+static const uint64_t P9N2_EX_7_L2_SPR_CORE_HOLD_OUT = 0x2F010AB5ull;
+//DUPS: 2F010AB5,
+static const uint64_t P9N2_EX_8_L2_SPR_CORE_HOLD_OUT = 0x30010AB5ull;
+//DUPS: 31010AB5,
+static const uint64_t P9N2_EX_9_L2_SPR_CORE_HOLD_OUT = 0x32010AB5ull;
+//DUPS: 33010AB5,
+static const uint64_t P9N2_EX_L2_SPR_CORE_HOLD_OUT = 0x20010AB5ull;
+//DUPS: 21010AB5,
+
+static const uint64_t P9N2_C_SPR_MODE = 0x20010A84ull;
+
+static const uint64_t P9N2_C_0_SPR_MODE = 0x20010A84ull;
+
+static const uint64_t P9N2_C_1_SPR_MODE = 0x21010A84ull;
+
+static const uint64_t P9N2_C_2_SPR_MODE = 0x22010A84ull;
+
+static const uint64_t P9N2_C_3_SPR_MODE = 0x23010A84ull;
+
+static const uint64_t P9N2_C_4_SPR_MODE = 0x24010A84ull;
+
+static const uint64_t P9N2_C_5_SPR_MODE = 0x25010A84ull;
+
+static const uint64_t P9N2_C_6_SPR_MODE = 0x26010A84ull;
+
+static const uint64_t P9N2_C_7_SPR_MODE = 0x27010A84ull;
+
+static const uint64_t P9N2_C_8_SPR_MODE = 0x28010A84ull;
+
+static const uint64_t P9N2_C_9_SPR_MODE = 0x29010A84ull;
+
+static const uint64_t P9N2_C_10_SPR_MODE = 0x2A010A84ull;
+
+static const uint64_t P9N2_C_11_SPR_MODE = 0x2B010A84ull;
+
+static const uint64_t P9N2_C_12_SPR_MODE = 0x2C010A84ull;
+
+static const uint64_t P9N2_C_13_SPR_MODE = 0x2D010A84ull;
+
+static const uint64_t P9N2_C_14_SPR_MODE = 0x2E010A84ull;
+
+static const uint64_t P9N2_C_15_SPR_MODE = 0x2F010A84ull;
+
+static const uint64_t P9N2_C_16_SPR_MODE = 0x30010A84ull;
+
+static const uint64_t P9N2_C_17_SPR_MODE = 0x31010A84ull;
+
+static const uint64_t P9N2_C_18_SPR_MODE = 0x32010A84ull;
+
+static const uint64_t P9N2_C_19_SPR_MODE = 0x33010A84ull;
+
+static const uint64_t P9N2_C_20_SPR_MODE = 0x34010A84ull;
+
+static const uint64_t P9N2_C_21_SPR_MODE = 0x35010A84ull;
+
+static const uint64_t P9N2_C_22_SPR_MODE = 0x36010A84ull;
+
+static const uint64_t P9N2_C_23_SPR_MODE = 0x37010A84ull;
+
+static const uint64_t P9N2_EX_0_L2_SPR_MODE = 0x20010A84ull;
+//DUPS: 20010A84,
+static const uint64_t P9N2_EX_10_L2_SPR_MODE = 0x34010A84ull;
+//DUPS: 34010A84,
+static const uint64_t P9N2_EX_11_L2_SPR_MODE = 0x36010A84ull;
+//DUPS: 36010A84,
+static const uint64_t P9N2_EX_1_L2_SPR_MODE = 0x22010A84ull;
+//DUPS: 22010A84,
+static const uint64_t P9N2_EX_2_L2_SPR_MODE = 0x24010A84ull;
+//DUPS: 24010A84,
+static const uint64_t P9N2_EX_3_L2_SPR_MODE = 0x26010A84ull;
+//DUPS: 26010A84,
+static const uint64_t P9N2_EX_4_L2_SPR_MODE = 0x28010A84ull;
+//DUPS: 28010A84,
+static const uint64_t P9N2_EX_5_L2_SPR_MODE = 0x2B010A84ull;
+//DUPS: 2A010A84,
+static const uint64_t P9N2_EX_6_L2_SPR_MODE = 0x2D010A84ull;
+//DUPS: 2C010A84,
+static const uint64_t P9N2_EX_7_L2_SPR_MODE = 0x2F010A84ull;
+//DUPS: 2E010A84,
+static const uint64_t P9N2_EX_8_L2_SPR_MODE = 0x30010A84ull;
+//DUPS: 30010A84,
+static const uint64_t P9N2_EX_9_L2_SPR_MODE = 0x32010A84ull;
+//DUPS: 32010A84,
+static const uint64_t P9N2_EX_L2_SPR_MODE = 0x20010A84ull;
+//DUPS: 20010A84,
+
+static const uint64_t P9N2_C_SPURR_FREQ_DETECT_CYC_CNT = 0x20010A9Full;
+
+static const uint64_t P9N2_C_0_SPURR_FREQ_DETECT_CYC_CNT = 0x20010A9Full;
+
+static const uint64_t P9N2_C_1_SPURR_FREQ_DETECT_CYC_CNT = 0x21010A9Full;
+
+static const uint64_t P9N2_C_2_SPURR_FREQ_DETECT_CYC_CNT = 0x22010A9Full;
+
+static const uint64_t P9N2_C_3_SPURR_FREQ_DETECT_CYC_CNT = 0x23010A9Full;
+
+static const uint64_t P9N2_C_4_SPURR_FREQ_DETECT_CYC_CNT = 0x24010A9Full;
+
+static const uint64_t P9N2_C_5_SPURR_FREQ_DETECT_CYC_CNT = 0x25010A9Full;
+
+static const uint64_t P9N2_C_6_SPURR_FREQ_DETECT_CYC_CNT = 0x26010A9Full;
+
+static const uint64_t P9N2_C_7_SPURR_FREQ_DETECT_CYC_CNT = 0x27010A9Full;
+
+static const uint64_t P9N2_C_8_SPURR_FREQ_DETECT_CYC_CNT = 0x28010A9Full;
+
+static const uint64_t P9N2_C_9_SPURR_FREQ_DETECT_CYC_CNT = 0x29010A9Full;
+
+static const uint64_t P9N2_C_10_SPURR_FREQ_DETECT_CYC_CNT = 0x2A010A9Full;
+
+static const uint64_t P9N2_C_11_SPURR_FREQ_DETECT_CYC_CNT = 0x2B010A9Full;
+
+static const uint64_t P9N2_C_12_SPURR_FREQ_DETECT_CYC_CNT = 0x2C010A9Full;
+
+static const uint64_t P9N2_C_13_SPURR_FREQ_DETECT_CYC_CNT = 0x2D010A9Full;
+
+static const uint64_t P9N2_C_14_SPURR_FREQ_DETECT_CYC_CNT = 0x2E010A9Full;
+
+static const uint64_t P9N2_C_15_SPURR_FREQ_DETECT_CYC_CNT = 0x2F010A9Full;
+
+static const uint64_t P9N2_C_16_SPURR_FREQ_DETECT_CYC_CNT = 0x30010A9Full;
+
+static const uint64_t P9N2_C_17_SPURR_FREQ_DETECT_CYC_CNT = 0x31010A9Full;
+
+static const uint64_t P9N2_C_18_SPURR_FREQ_DETECT_CYC_CNT = 0x32010A9Full;
+
+static const uint64_t P9N2_C_19_SPURR_FREQ_DETECT_CYC_CNT = 0x33010A9Full;
+
+static const uint64_t P9N2_C_20_SPURR_FREQ_DETECT_CYC_CNT = 0x34010A9Full;
+
+static const uint64_t P9N2_C_21_SPURR_FREQ_DETECT_CYC_CNT = 0x35010A9Full;
+
+static const uint64_t P9N2_C_22_SPURR_FREQ_DETECT_CYC_CNT = 0x36010A9Full;
+
+static const uint64_t P9N2_C_23_SPURR_FREQ_DETECT_CYC_CNT = 0x37010A9Full;
+
+static const uint64_t P9N2_EX_SPURR_FREQ_DETECT_CYC_CNT = 0x20010A9Full;
+//DUPS: 20010A9F,
+static const uint64_t P9N2_EX_0_SPURR_FREQ_DETECT_CYC_CNT = 0x20010A9Full;
+//DUPS: 20010A9F,
+static const uint64_t P9N2_EX_1_SPURR_FREQ_DETECT_CYC_CNT = 0x22010A9Full;
+//DUPS: 22010A9F,
+static const uint64_t P9N2_EX_2_SPURR_FREQ_DETECT_CYC_CNT = 0x24010A9Full;
+//DUPS: 24010A9F,
+static const uint64_t P9N2_EX_3_SPURR_FREQ_DETECT_CYC_CNT = 0x26010A9Full;
+//DUPS: 26010A9F,
+static const uint64_t P9N2_EX_4_SPURR_FREQ_DETECT_CYC_CNT = 0x28010A9Full;
+//DUPS: 28010A9F,
+static const uint64_t P9N2_EX_5_SPURR_FREQ_DETECT_CYC_CNT = 0x2B010A9Full;
+//DUPS: 2A010A9F,
+static const uint64_t P9N2_EX_6_SPURR_FREQ_DETECT_CYC_CNT = 0x2D010A9Full;
+//DUPS: 2C010A9F,
+static const uint64_t P9N2_EX_7_SPURR_FREQ_DETECT_CYC_CNT = 0x2F010A9Full;
+//DUPS: 2E010A9F,
+static const uint64_t P9N2_EX_8_SPURR_FREQ_DETECT_CYC_CNT = 0x30010A9Full;
+//DUPS: 30010A9F,
+static const uint64_t P9N2_EX_9_SPURR_FREQ_DETECT_CYC_CNT = 0x32010A9Full;
+//DUPS: 32010A9F,
+static const uint64_t P9N2_EX_10_SPURR_FREQ_DETECT_CYC_CNT = 0x34010A9Full;
+//DUPS: 34010A9F,
+static const uint64_t P9N2_EX_11_SPURR_FREQ_DETECT_CYC_CNT = 0x36010A9Full;
+//DUPS: 36010A9F,
+
+static const uint64_t P9N2_C_SPURR_FREQ_REF = 0x20010AA1ull;
+
+static const uint64_t P9N2_C_0_SPURR_FREQ_REF = 0x20010AA1ull;
+
+static const uint64_t P9N2_C_1_SPURR_FREQ_REF = 0x21010AA1ull;
+
+static const uint64_t P9N2_C_2_SPURR_FREQ_REF = 0x22010AA1ull;
+
+static const uint64_t P9N2_C_3_SPURR_FREQ_REF = 0x23010AA1ull;
+
+static const uint64_t P9N2_C_4_SPURR_FREQ_REF = 0x24010AA1ull;
+
+static const uint64_t P9N2_C_5_SPURR_FREQ_REF = 0x25010AA1ull;
+
+static const uint64_t P9N2_C_6_SPURR_FREQ_REF = 0x26010AA1ull;
+
+static const uint64_t P9N2_C_7_SPURR_FREQ_REF = 0x27010AA1ull;
+
+static const uint64_t P9N2_C_8_SPURR_FREQ_REF = 0x28010AA1ull;
+
+static const uint64_t P9N2_C_9_SPURR_FREQ_REF = 0x29010AA1ull;
+
+static const uint64_t P9N2_C_10_SPURR_FREQ_REF = 0x2A010AA1ull;
+
+static const uint64_t P9N2_C_11_SPURR_FREQ_REF = 0x2B010AA1ull;
+
+static const uint64_t P9N2_C_12_SPURR_FREQ_REF = 0x2C010AA1ull;
+
+static const uint64_t P9N2_C_13_SPURR_FREQ_REF = 0x2D010AA1ull;
+
+static const uint64_t P9N2_C_14_SPURR_FREQ_REF = 0x2E010AA1ull;
+
+static const uint64_t P9N2_C_15_SPURR_FREQ_REF = 0x2F010AA1ull;
+
+static const uint64_t P9N2_C_16_SPURR_FREQ_REF = 0x30010AA1ull;
+
+static const uint64_t P9N2_C_17_SPURR_FREQ_REF = 0x31010AA1ull;
+
+static const uint64_t P9N2_C_18_SPURR_FREQ_REF = 0x32010AA1ull;
+
+static const uint64_t P9N2_C_19_SPURR_FREQ_REF = 0x33010AA1ull;
+
+static const uint64_t P9N2_C_20_SPURR_FREQ_REF = 0x34010AA1ull;
+
+static const uint64_t P9N2_C_21_SPURR_FREQ_REF = 0x35010AA1ull;
+
+static const uint64_t P9N2_C_22_SPURR_FREQ_REF = 0x36010AA1ull;
+
+static const uint64_t P9N2_C_23_SPURR_FREQ_REF = 0x37010AA1ull;
+
+static const uint64_t P9N2_EX_0_L2_SPURR_FREQ_REF = 0x20010AA1ull;
+//DUPS: 20010AA1,
+static const uint64_t P9N2_EX_10_L2_SPURR_FREQ_REF = 0x34010AA1ull;
+//DUPS: 34010AA1,
+static const uint64_t P9N2_EX_11_L2_SPURR_FREQ_REF = 0x36010AA1ull;
+//DUPS: 36010AA1,
+static const uint64_t P9N2_EX_1_L2_SPURR_FREQ_REF = 0x22010AA1ull;
+//DUPS: 22010AA1,
+static const uint64_t P9N2_EX_2_L2_SPURR_FREQ_REF = 0x24010AA1ull;
+//DUPS: 24010AA1,
+static const uint64_t P9N2_EX_3_L2_SPURR_FREQ_REF = 0x26010AA1ull;
+//DUPS: 26010AA1,
+static const uint64_t P9N2_EX_4_L2_SPURR_FREQ_REF = 0x28010AA1ull;
+//DUPS: 28010AA1,
+static const uint64_t P9N2_EX_5_L2_SPURR_FREQ_REF = 0x2B010AA1ull;
+//DUPS: 2A010AA1,
+static const uint64_t P9N2_EX_6_L2_SPURR_FREQ_REF = 0x2D010AA1ull;
+//DUPS: 2C010AA1,
+static const uint64_t P9N2_EX_7_L2_SPURR_FREQ_REF = 0x2F010AA1ull;
+//DUPS: 2E010AA1,
+static const uint64_t P9N2_EX_8_L2_SPURR_FREQ_REF = 0x30010AA1ull;
+//DUPS: 30010AA1,
+static const uint64_t P9N2_EX_9_L2_SPURR_FREQ_REF = 0x32010AA1ull;
+//DUPS: 32010AA1,
+static const uint64_t P9N2_EX_L2_SPURR_FREQ_REF = 0x20010AA1ull;
+//DUPS: 20010AA1,
+
+static const uint64_t P9N2_C_SPURR_FREQ_SCALE = 0x20010AA0ull;
+
+static const uint64_t P9N2_C_0_SPURR_FREQ_SCALE = 0x20010AA0ull;
+
+static const uint64_t P9N2_C_1_SPURR_FREQ_SCALE = 0x21010AA0ull;
+
+static const uint64_t P9N2_C_2_SPURR_FREQ_SCALE = 0x22010AA0ull;
+
+static const uint64_t P9N2_C_3_SPURR_FREQ_SCALE = 0x23010AA0ull;
+
+static const uint64_t P9N2_C_4_SPURR_FREQ_SCALE = 0x24010AA0ull;
+
+static const uint64_t P9N2_C_5_SPURR_FREQ_SCALE = 0x25010AA0ull;
+
+static const uint64_t P9N2_C_6_SPURR_FREQ_SCALE = 0x26010AA0ull;
+
+static const uint64_t P9N2_C_7_SPURR_FREQ_SCALE = 0x27010AA0ull;
+
+static const uint64_t P9N2_C_8_SPURR_FREQ_SCALE = 0x28010AA0ull;
+
+static const uint64_t P9N2_C_9_SPURR_FREQ_SCALE = 0x29010AA0ull;
+
+static const uint64_t P9N2_C_10_SPURR_FREQ_SCALE = 0x2A010AA0ull;
+
+static const uint64_t P9N2_C_11_SPURR_FREQ_SCALE = 0x2B010AA0ull;
+
+static const uint64_t P9N2_C_12_SPURR_FREQ_SCALE = 0x2C010AA0ull;
+
+static const uint64_t P9N2_C_13_SPURR_FREQ_SCALE = 0x2D010AA0ull;
+
+static const uint64_t P9N2_C_14_SPURR_FREQ_SCALE = 0x2E010AA0ull;
+
+static const uint64_t P9N2_C_15_SPURR_FREQ_SCALE = 0x2F010AA0ull;
+
+static const uint64_t P9N2_C_16_SPURR_FREQ_SCALE = 0x30010AA0ull;
+
+static const uint64_t P9N2_C_17_SPURR_FREQ_SCALE = 0x31010AA0ull;
+
+static const uint64_t P9N2_C_18_SPURR_FREQ_SCALE = 0x32010AA0ull;
+
+static const uint64_t P9N2_C_19_SPURR_FREQ_SCALE = 0x33010AA0ull;
+
+static const uint64_t P9N2_C_20_SPURR_FREQ_SCALE = 0x34010AA0ull;
+
+static const uint64_t P9N2_C_21_SPURR_FREQ_SCALE = 0x35010AA0ull;
+
+static const uint64_t P9N2_C_22_SPURR_FREQ_SCALE = 0x36010AA0ull;
+
+static const uint64_t P9N2_C_23_SPURR_FREQ_SCALE = 0x37010AA0ull;
+
+static const uint64_t P9N2_EX_0_L2_SPURR_FREQ_SCALE = 0x20010AA0ull;
+//DUPS: 20010AA0,
+static const uint64_t P9N2_EX_10_L2_SPURR_FREQ_SCALE = 0x34010AA0ull;
+//DUPS: 34010AA0,
+static const uint64_t P9N2_EX_11_L2_SPURR_FREQ_SCALE = 0x36010AA0ull;
+//DUPS: 36010AA0,
+static const uint64_t P9N2_EX_1_L2_SPURR_FREQ_SCALE = 0x22010AA0ull;
+//DUPS: 22010AA0,
+static const uint64_t P9N2_EX_2_L2_SPURR_FREQ_SCALE = 0x24010AA0ull;
+//DUPS: 24010AA0,
+static const uint64_t P9N2_EX_3_L2_SPURR_FREQ_SCALE = 0x26010AA0ull;
+//DUPS: 26010AA0,
+static const uint64_t P9N2_EX_4_L2_SPURR_FREQ_SCALE = 0x28010AA0ull;
+//DUPS: 28010AA0,
+static const uint64_t P9N2_EX_5_L2_SPURR_FREQ_SCALE = 0x2B010AA0ull;
+//DUPS: 2A010AA0,
+static const uint64_t P9N2_EX_6_L2_SPURR_FREQ_SCALE = 0x2D010AA0ull;
+//DUPS: 2C010AA0,
+static const uint64_t P9N2_EX_7_L2_SPURR_FREQ_SCALE = 0x2F010AA0ull;
+//DUPS: 2E010AA0,
+static const uint64_t P9N2_EX_8_L2_SPURR_FREQ_SCALE = 0x30010AA0ull;
+//DUPS: 30010AA0,
+static const uint64_t P9N2_EX_9_L2_SPURR_FREQ_SCALE = 0x32010AA0ull;
+//DUPS: 32010AA0,
+static const uint64_t P9N2_EX_L2_SPURR_FREQ_SCALE = 0x20010AA0ull;
+//DUPS: 20010AA0,
+
+static const uint64_t P9N2_C_SRC_MASK = 0x20010AAFull;
+
+static const uint64_t P9N2_C_0_SRC_MASK = 0x20010AAFull;
+
+static const uint64_t P9N2_C_1_SRC_MASK = 0x21010AAFull;
+
+static const uint64_t P9N2_C_2_SRC_MASK = 0x22010AAFull;
+
+static const uint64_t P9N2_C_3_SRC_MASK = 0x23010AAFull;
+
+static const uint64_t P9N2_C_4_SRC_MASK = 0x24010AAFull;
+
+static const uint64_t P9N2_C_5_SRC_MASK = 0x25010AAFull;
+
+static const uint64_t P9N2_C_6_SRC_MASK = 0x26010AAFull;
+
+static const uint64_t P9N2_C_7_SRC_MASK = 0x27010AAFull;
+
+static const uint64_t P9N2_C_8_SRC_MASK = 0x28010AAFull;
+
+static const uint64_t P9N2_C_9_SRC_MASK = 0x29010AAFull;
+
+static const uint64_t P9N2_C_10_SRC_MASK = 0x2A010AAFull;
+
+static const uint64_t P9N2_C_11_SRC_MASK = 0x2B010AAFull;
+
+static const uint64_t P9N2_C_12_SRC_MASK = 0x2C010AAFull;
+
+static const uint64_t P9N2_C_13_SRC_MASK = 0x2D010AAFull;
+
+static const uint64_t P9N2_C_14_SRC_MASK = 0x2E010AAFull;
+
+static const uint64_t P9N2_C_15_SRC_MASK = 0x2F010AAFull;
+
+static const uint64_t P9N2_C_16_SRC_MASK = 0x30010AAFull;
+
+static const uint64_t P9N2_C_17_SRC_MASK = 0x31010AAFull;
+
+static const uint64_t P9N2_C_18_SRC_MASK = 0x32010AAFull;
+
+static const uint64_t P9N2_C_19_SRC_MASK = 0x33010AAFull;
+
+static const uint64_t P9N2_C_20_SRC_MASK = 0x34010AAFull;
+
+static const uint64_t P9N2_C_21_SRC_MASK = 0x35010AAFull;
+
+static const uint64_t P9N2_C_22_SRC_MASK = 0x36010AAFull;
+
+static const uint64_t P9N2_C_23_SRC_MASK = 0x37010AAFull;
+
+static const uint64_t P9N2_EX_SRC_MASK = 0x20010AAFull;
+//DUPS: 21010AAF,
+static const uint64_t P9N2_EX_0_SRC_MASK = 0x20010AAFull;
+//DUPS: 21010AAF,
+static const uint64_t P9N2_EX_1_SRC_MASK = 0x22010AAFull;
+//DUPS: 23010AAF,
+static const uint64_t P9N2_EX_2_SRC_MASK = 0x24010AAFull;
+//DUPS: 25010AAF,
+static const uint64_t P9N2_EX_3_SRC_MASK = 0x26010AAFull;
+//DUPS: 27010AAF,
+static const uint64_t P9N2_EX_4_SRC_MASK = 0x28010AAFull;
+//DUPS: 29010AAF,
+static const uint64_t P9N2_EX_5_SRC_MASK = 0x2A010AAFull;
+//DUPS: 2B010AAF,
+static const uint64_t P9N2_EX_6_SRC_MASK = 0x2C010AAFull;
+//DUPS: 2D010AAF,
+static const uint64_t P9N2_EX_7_SRC_MASK = 0x2F010AAFull;
+//DUPS: 2F010AAF,
+static const uint64_t P9N2_EX_8_SRC_MASK = 0x30010AAFull;
+//DUPS: 31010AAF,
+static const uint64_t P9N2_EX_9_SRC_MASK = 0x32010AAFull;
+//DUPS: 33010AAF,
+static const uint64_t P9N2_EX_10_SRC_MASK = 0x34010AAFull;
+//DUPS: 35010AAF,
+static const uint64_t P9N2_EX_11_SRC_MASK = 0x36010AAFull;
+//DUPS: 37010AAF,
+
+static const uint64_t P9N2_C_SUM_MASK_REG = 0x20040017ull;
+
+static const uint64_t P9N2_C_0_SUM_MASK_REG = 0x20040017ull;
+
+static const uint64_t P9N2_C_1_SUM_MASK_REG = 0x21040017ull;
+
+static const uint64_t P9N2_C_2_SUM_MASK_REG = 0x22040017ull;
+
+static const uint64_t P9N2_C_3_SUM_MASK_REG = 0x23040017ull;
+
+static const uint64_t P9N2_C_4_SUM_MASK_REG = 0x24040017ull;
+
+static const uint64_t P9N2_C_5_SUM_MASK_REG = 0x25040017ull;
+
+static const uint64_t P9N2_C_6_SUM_MASK_REG = 0x26040017ull;
+
+static const uint64_t P9N2_C_7_SUM_MASK_REG = 0x27040017ull;
+
+static const uint64_t P9N2_C_8_SUM_MASK_REG = 0x28040017ull;
+
+static const uint64_t P9N2_C_9_SUM_MASK_REG = 0x29040017ull;
+
+static const uint64_t P9N2_C_10_SUM_MASK_REG = 0x2A040017ull;
+
+static const uint64_t P9N2_C_11_SUM_MASK_REG = 0x2B040017ull;
+
+static const uint64_t P9N2_C_12_SUM_MASK_REG = 0x2C040017ull;
+
+static const uint64_t P9N2_C_13_SUM_MASK_REG = 0x2D040017ull;
+
+static const uint64_t P9N2_C_14_SUM_MASK_REG = 0x2E040017ull;
+
+static const uint64_t P9N2_C_15_SUM_MASK_REG = 0x2F040017ull;
+
+static const uint64_t P9N2_C_16_SUM_MASK_REG = 0x30040017ull;
+
+static const uint64_t P9N2_C_17_SUM_MASK_REG = 0x31040017ull;
+
+static const uint64_t P9N2_C_18_SUM_MASK_REG = 0x32040017ull;
+
+static const uint64_t P9N2_C_19_SUM_MASK_REG = 0x33040017ull;
+
+static const uint64_t P9N2_C_20_SUM_MASK_REG = 0x34040017ull;
+
+static const uint64_t P9N2_C_21_SUM_MASK_REG = 0x35040017ull;
+
+static const uint64_t P9N2_C_22_SUM_MASK_REG = 0x36040017ull;
+
+static const uint64_t P9N2_C_23_SUM_MASK_REG = 0x37040017ull;
+
+static const uint64_t P9N2_EQ_SUM_MASK_REG = 0x10040017ull;
+
+static const uint64_t P9N2_EQ_0_SUM_MASK_REG = 0x10040017ull;
+
+static const uint64_t P9N2_EQ_1_SUM_MASK_REG = 0x11040017ull;
+
+static const uint64_t P9N2_EQ_2_SUM_MASK_REG = 0x12040017ull;
+
+static const uint64_t P9N2_EQ_3_SUM_MASK_REG = 0x13040017ull;
+
+static const uint64_t P9N2_EQ_4_SUM_MASK_REG = 0x14040017ull;
+
+static const uint64_t P9N2_EQ_5_SUM_MASK_REG = 0x15040017ull;
+
+static const uint64_t P9N2_EX_SUM_MASK_REG = 0x20040017ull;
+//DUPS: 21040017,
+static const uint64_t P9N2_EX_0_SUM_MASK_REG = 0x20040017ull;
+//DUPS: 21040017,
+static const uint64_t P9N2_EX_1_SUM_MASK_REG = 0x22040017ull;
+//DUPS: 23040017,
+static const uint64_t P9N2_EX_2_SUM_MASK_REG = 0x24040017ull;
+//DUPS: 25040017,
+static const uint64_t P9N2_EX_3_SUM_MASK_REG = 0x26040017ull;
+//DUPS: 27040017,
+static const uint64_t P9N2_EX_4_SUM_MASK_REG = 0x28040017ull;
+//DUPS: 29040017,
+static const uint64_t P9N2_EX_5_SUM_MASK_REG = 0x2A040017ull;
+//DUPS: 2B040017,
+static const uint64_t P9N2_EX_6_SUM_MASK_REG = 0x2C040017ull;
+//DUPS: 2D040017,
+static const uint64_t P9N2_EX_7_SUM_MASK_REG = 0x2F040017ull;
+//DUPS: 2F040017,
+static const uint64_t P9N2_EX_8_SUM_MASK_REG = 0x30040017ull;
+//DUPS: 31040017,
+static const uint64_t P9N2_EX_9_SUM_MASK_REG = 0x32040017ull;
+//DUPS: 33040017,
+static const uint64_t P9N2_EX_10_SUM_MASK_REG = 0x34040017ull;
+//DUPS: 35040017,
+static const uint64_t P9N2_EX_11_SUM_MASK_REG = 0x36040017ull;
+//DUPS: 37040017,
+
+static const uint64_t P9N2_C_SYNC_CONFIG = 0x20030000ull;
+
+static const uint64_t P9N2_C_0_SYNC_CONFIG = 0x20030000ull;
+
+static const uint64_t P9N2_C_1_SYNC_CONFIG = 0x21030000ull;
+
+static const uint64_t P9N2_C_2_SYNC_CONFIG = 0x22030000ull;
+
+static const uint64_t P9N2_C_3_SYNC_CONFIG = 0x23030000ull;
+
+static const uint64_t P9N2_C_4_SYNC_CONFIG = 0x24030000ull;
+
+static const uint64_t P9N2_C_5_SYNC_CONFIG = 0x25030000ull;
+
+static const uint64_t P9N2_C_6_SYNC_CONFIG = 0x26030000ull;
+
+static const uint64_t P9N2_C_7_SYNC_CONFIG = 0x27030000ull;
+
+static const uint64_t P9N2_C_8_SYNC_CONFIG = 0x28030000ull;
+
+static const uint64_t P9N2_C_9_SYNC_CONFIG = 0x29030000ull;
+
+static const uint64_t P9N2_C_10_SYNC_CONFIG = 0x2A030000ull;
+
+static const uint64_t P9N2_C_11_SYNC_CONFIG = 0x2B030000ull;
+
+static const uint64_t P9N2_C_12_SYNC_CONFIG = 0x2C030000ull;
+
+static const uint64_t P9N2_C_13_SYNC_CONFIG = 0x2D030000ull;
+
+static const uint64_t P9N2_C_14_SYNC_CONFIG = 0x2E030000ull;
+
+static const uint64_t P9N2_C_15_SYNC_CONFIG = 0x2F030000ull;
+
+static const uint64_t P9N2_C_16_SYNC_CONFIG = 0x30030000ull;
+
+static const uint64_t P9N2_C_17_SYNC_CONFIG = 0x31030000ull;
+
+static const uint64_t P9N2_C_18_SYNC_CONFIG = 0x32030000ull;
+
+static const uint64_t P9N2_C_19_SYNC_CONFIG = 0x33030000ull;
+
+static const uint64_t P9N2_C_20_SYNC_CONFIG = 0x34030000ull;
+
+static const uint64_t P9N2_C_21_SYNC_CONFIG = 0x35030000ull;
+
+static const uint64_t P9N2_C_22_SYNC_CONFIG = 0x36030000ull;
+
+static const uint64_t P9N2_C_23_SYNC_CONFIG = 0x37030000ull;
+
+static const uint64_t P9N2_EQ_SYNC_CONFIG = 0x10030000ull;
+
+static const uint64_t P9N2_EQ_0_SYNC_CONFIG = 0x10030000ull;
+
+static const uint64_t P9N2_EQ_1_SYNC_CONFIG = 0x11030000ull;
+
+static const uint64_t P9N2_EQ_2_SYNC_CONFIG = 0x12030000ull;
+
+static const uint64_t P9N2_EQ_3_SYNC_CONFIG = 0x13030000ull;
+
+static const uint64_t P9N2_EQ_4_SYNC_CONFIG = 0x14030000ull;
+
+static const uint64_t P9N2_EQ_5_SYNC_CONFIG = 0x15030000ull;
+
+static const uint64_t P9N2_EX_SYNC_CONFIG = 0x20030000ull;
+//DUPS: 21030000,
+static const uint64_t P9N2_EX_0_SYNC_CONFIG = 0x20030000ull;
+//DUPS: 21030000,
+static const uint64_t P9N2_EX_1_SYNC_CONFIG = 0x22030000ull;
+//DUPS: 23030000,
+static const uint64_t P9N2_EX_2_SYNC_CONFIG = 0x24030000ull;
+//DUPS: 25030000,
+static const uint64_t P9N2_EX_3_SYNC_CONFIG = 0x26030000ull;
+//DUPS: 27030000,
+static const uint64_t P9N2_EX_4_SYNC_CONFIG = 0x28030000ull;
+//DUPS: 29030000,
+static const uint64_t P9N2_EX_5_SYNC_CONFIG = 0x2A030000ull;
+//DUPS: 2B030000,
+static const uint64_t P9N2_EX_6_SYNC_CONFIG = 0x2C030000ull;
+//DUPS: 2D030000,
+static const uint64_t P9N2_EX_7_SYNC_CONFIG = 0x2F030000ull;
+//DUPS: 2F030000,
+static const uint64_t P9N2_EX_8_SYNC_CONFIG = 0x30030000ull;
+//DUPS: 31030000,
+static const uint64_t P9N2_EX_9_SYNC_CONFIG = 0x32030000ull;
+//DUPS: 33030000,
+static const uint64_t P9N2_EX_10_SYNC_CONFIG = 0x34030000ull;
+//DUPS: 35030000,
+static const uint64_t P9N2_EX_11_SYNC_CONFIG = 0x36030000ull;
+//DUPS: 37030000,
+
+static const uint64_t P9N2_C_T0_PMU_SCOM = 0x20010AAAull;
+
+static const uint64_t P9N2_C_0_T0_PMU_SCOM = 0x20010AAAull;
+
+static const uint64_t P9N2_C_1_T0_PMU_SCOM = 0x21010AAAull;
+
+static const uint64_t P9N2_C_2_T0_PMU_SCOM = 0x22010AAAull;
+
+static const uint64_t P9N2_C_3_T0_PMU_SCOM = 0x23010AAAull;
+
+static const uint64_t P9N2_C_4_T0_PMU_SCOM = 0x24010AAAull;
+
+static const uint64_t P9N2_C_5_T0_PMU_SCOM = 0x25010AAAull;
+
+static const uint64_t P9N2_C_6_T0_PMU_SCOM = 0x26010AAAull;
+
+static const uint64_t P9N2_C_7_T0_PMU_SCOM = 0x27010AAAull;
+
+static const uint64_t P9N2_C_8_T0_PMU_SCOM = 0x28010AAAull;
+
+static const uint64_t P9N2_C_9_T0_PMU_SCOM = 0x29010AAAull;
+
+static const uint64_t P9N2_C_10_T0_PMU_SCOM = 0x2A010AAAull;
+
+static const uint64_t P9N2_C_11_T0_PMU_SCOM = 0x2B010AAAull;
+
+static const uint64_t P9N2_C_12_T0_PMU_SCOM = 0x2C010AAAull;
+
+static const uint64_t P9N2_C_13_T0_PMU_SCOM = 0x2D010AAAull;
+
+static const uint64_t P9N2_C_14_T0_PMU_SCOM = 0x2E010AAAull;
+
+static const uint64_t P9N2_C_15_T0_PMU_SCOM = 0x2F010AAAull;
+
+static const uint64_t P9N2_C_16_T0_PMU_SCOM = 0x30010AAAull;
+
+static const uint64_t P9N2_C_17_T0_PMU_SCOM = 0x31010AAAull;
+
+static const uint64_t P9N2_C_18_T0_PMU_SCOM = 0x32010AAAull;
+
+static const uint64_t P9N2_C_19_T0_PMU_SCOM = 0x33010AAAull;
+
+static const uint64_t P9N2_C_20_T0_PMU_SCOM = 0x34010AAAull;
+
+static const uint64_t P9N2_C_21_T0_PMU_SCOM = 0x35010AAAull;
+
+static const uint64_t P9N2_C_22_T0_PMU_SCOM = 0x36010AAAull;
+
+static const uint64_t P9N2_C_23_T0_PMU_SCOM = 0x37010AAAull;
+
+static const uint64_t P9N2_EX_0_L2_T0_PMU_SCOM = 0x20010AAAull;
+//DUPS: 21010AAA,
+static const uint64_t P9N2_EX_10_L2_T0_PMU_SCOM = 0x34010AAAull;
+//DUPS: 35010AAA,
+static const uint64_t P9N2_EX_11_L2_T0_PMU_SCOM = 0x36010AAAull;
+//DUPS: 37010AAA,
+static const uint64_t P9N2_EX_1_L2_T0_PMU_SCOM = 0x22010AAAull;
+//DUPS: 23010AAA,
+static const uint64_t P9N2_EX_2_L2_T0_PMU_SCOM = 0x24010AAAull;
+//DUPS: 25010AAA,
+static const uint64_t P9N2_EX_3_L2_T0_PMU_SCOM = 0x26010AAAull;
+//DUPS: 27010AAA,
+static const uint64_t P9N2_EX_4_L2_T0_PMU_SCOM = 0x28010AAAull;
+//DUPS: 29010AAA,
+static const uint64_t P9N2_EX_5_L2_T0_PMU_SCOM = 0x2A010AAAull;
+//DUPS: 2B010AAA,
+static const uint64_t P9N2_EX_6_L2_T0_PMU_SCOM = 0x2C010AAAull;
+//DUPS: 2D010AAA,
+static const uint64_t P9N2_EX_7_L2_T0_PMU_SCOM = 0x2F010AAAull;
+//DUPS: 2F010AAA,
+static const uint64_t P9N2_EX_8_L2_T0_PMU_SCOM = 0x30010AAAull;
+//DUPS: 31010AAA,
+static const uint64_t P9N2_EX_9_L2_T0_PMU_SCOM = 0x32010AAAull;
+//DUPS: 33010AAA,
+static const uint64_t P9N2_EX_L2_T0_PMU_SCOM = 0x20010AAAull;
+//DUPS: 21010AAA,
+
+static const uint64_t P9N2_C_T1_PMU_SCOM = 0x20010AABull;
+
+static const uint64_t P9N2_C_0_T1_PMU_SCOM = 0x20010AABull;
+
+static const uint64_t P9N2_C_1_T1_PMU_SCOM = 0x21010AABull;
+
+static const uint64_t P9N2_C_2_T1_PMU_SCOM = 0x22010AABull;
+
+static const uint64_t P9N2_C_3_T1_PMU_SCOM = 0x23010AABull;
+
+static const uint64_t P9N2_C_4_T1_PMU_SCOM = 0x24010AABull;
+
+static const uint64_t P9N2_C_5_T1_PMU_SCOM = 0x25010AABull;
+
+static const uint64_t P9N2_C_6_T1_PMU_SCOM = 0x26010AABull;
+
+static const uint64_t P9N2_C_7_T1_PMU_SCOM = 0x27010AABull;
+
+static const uint64_t P9N2_C_8_T1_PMU_SCOM = 0x28010AABull;
+
+static const uint64_t P9N2_C_9_T1_PMU_SCOM = 0x29010AABull;
+
+static const uint64_t P9N2_C_10_T1_PMU_SCOM = 0x2A010AABull;
+
+static const uint64_t P9N2_C_11_T1_PMU_SCOM = 0x2B010AABull;
+
+static const uint64_t P9N2_C_12_T1_PMU_SCOM = 0x2C010AABull;
+
+static const uint64_t P9N2_C_13_T1_PMU_SCOM = 0x2D010AABull;
+
+static const uint64_t P9N2_C_14_T1_PMU_SCOM = 0x2E010AABull;
+
+static const uint64_t P9N2_C_15_T1_PMU_SCOM = 0x2F010AABull;
+
+static const uint64_t P9N2_C_16_T1_PMU_SCOM = 0x30010AABull;
+
+static const uint64_t P9N2_C_17_T1_PMU_SCOM = 0x31010AABull;
+
+static const uint64_t P9N2_C_18_T1_PMU_SCOM = 0x32010AABull;
+
+static const uint64_t P9N2_C_19_T1_PMU_SCOM = 0x33010AABull;
+
+static const uint64_t P9N2_C_20_T1_PMU_SCOM = 0x34010AABull;
+
+static const uint64_t P9N2_C_21_T1_PMU_SCOM = 0x35010AABull;
+
+static const uint64_t P9N2_C_22_T1_PMU_SCOM = 0x36010AABull;
+
+static const uint64_t P9N2_C_23_T1_PMU_SCOM = 0x37010AABull;
+
+static const uint64_t P9N2_EX_0_L2_T1_PMU_SCOM = 0x20010AABull;
+//DUPS: 21010AAB,
+static const uint64_t P9N2_EX_10_L2_T1_PMU_SCOM = 0x34010AABull;
+//DUPS: 35010AAB,
+static const uint64_t P9N2_EX_11_L2_T1_PMU_SCOM = 0x36010AABull;
+//DUPS: 37010AAB,
+static const uint64_t P9N2_EX_1_L2_T1_PMU_SCOM = 0x22010AABull;
+//DUPS: 23010AAB,
+static const uint64_t P9N2_EX_2_L2_T1_PMU_SCOM = 0x24010AABull;
+//DUPS: 25010AAB,
+static const uint64_t P9N2_EX_3_L2_T1_PMU_SCOM = 0x26010AABull;
+//DUPS: 27010AAB,
+static const uint64_t P9N2_EX_4_L2_T1_PMU_SCOM = 0x28010AABull;
+//DUPS: 29010AAB,
+static const uint64_t P9N2_EX_5_L2_T1_PMU_SCOM = 0x2A010AABull;
+//DUPS: 2B010AAB,
+static const uint64_t P9N2_EX_6_L2_T1_PMU_SCOM = 0x2C010AABull;
+//DUPS: 2D010AAB,
+static const uint64_t P9N2_EX_7_L2_T1_PMU_SCOM = 0x2F010AABull;
+//DUPS: 2F010AAB,
+static const uint64_t P9N2_EX_8_L2_T1_PMU_SCOM = 0x30010AABull;
+//DUPS: 31010AAB,
+static const uint64_t P9N2_EX_9_L2_T1_PMU_SCOM = 0x32010AABull;
+//DUPS: 33010AAB,
+static const uint64_t P9N2_EX_L2_T1_PMU_SCOM = 0x20010AABull;
+//DUPS: 21010AAB,
+
+static const uint64_t P9N2_C_T2_PMU_SCOM = 0x20010AACull;
+
+static const uint64_t P9N2_C_0_T2_PMU_SCOM = 0x20010AACull;
+
+static const uint64_t P9N2_C_1_T2_PMU_SCOM = 0x21010AACull;
+
+static const uint64_t P9N2_C_2_T2_PMU_SCOM = 0x22010AACull;
+
+static const uint64_t P9N2_C_3_T2_PMU_SCOM = 0x23010AACull;
+
+static const uint64_t P9N2_C_4_T2_PMU_SCOM = 0x24010AACull;
+
+static const uint64_t P9N2_C_5_T2_PMU_SCOM = 0x25010AACull;
+
+static const uint64_t P9N2_C_6_T2_PMU_SCOM = 0x26010AACull;
+
+static const uint64_t P9N2_C_7_T2_PMU_SCOM = 0x27010AACull;
+
+static const uint64_t P9N2_C_8_T2_PMU_SCOM = 0x28010AACull;
+
+static const uint64_t P9N2_C_9_T2_PMU_SCOM = 0x29010AACull;
+
+static const uint64_t P9N2_C_10_T2_PMU_SCOM = 0x2A010AACull;
+
+static const uint64_t P9N2_C_11_T2_PMU_SCOM = 0x2B010AACull;
+
+static const uint64_t P9N2_C_12_T2_PMU_SCOM = 0x2C010AACull;
+
+static const uint64_t P9N2_C_13_T2_PMU_SCOM = 0x2D010AACull;
+
+static const uint64_t P9N2_C_14_T2_PMU_SCOM = 0x2E010AACull;
+
+static const uint64_t P9N2_C_15_T2_PMU_SCOM = 0x2F010AACull;
+
+static const uint64_t P9N2_C_16_T2_PMU_SCOM = 0x30010AACull;
+
+static const uint64_t P9N2_C_17_T2_PMU_SCOM = 0x31010AACull;
+
+static const uint64_t P9N2_C_18_T2_PMU_SCOM = 0x32010AACull;
+
+static const uint64_t P9N2_C_19_T2_PMU_SCOM = 0x33010AACull;
+
+static const uint64_t P9N2_C_20_T2_PMU_SCOM = 0x34010AACull;
+
+static const uint64_t P9N2_C_21_T2_PMU_SCOM = 0x35010AACull;
+
+static const uint64_t P9N2_C_22_T2_PMU_SCOM = 0x36010AACull;
+
+static const uint64_t P9N2_C_23_T2_PMU_SCOM = 0x37010AACull;
+
+static const uint64_t P9N2_EX_0_L2_T2_PMU_SCOM = 0x20010AACull;
+//DUPS: 21010AAC,
+static const uint64_t P9N2_EX_10_L2_T2_PMU_SCOM = 0x34010AACull;
+//DUPS: 35010AAC,
+static const uint64_t P9N2_EX_11_L2_T2_PMU_SCOM = 0x36010AACull;
+//DUPS: 37010AAC,
+static const uint64_t P9N2_EX_1_L2_T2_PMU_SCOM = 0x22010AACull;
+//DUPS: 23010AAC,
+static const uint64_t P9N2_EX_2_L2_T2_PMU_SCOM = 0x24010AACull;
+//DUPS: 25010AAC,
+static const uint64_t P9N2_EX_3_L2_T2_PMU_SCOM = 0x26010AACull;
+//DUPS: 27010AAC,
+static const uint64_t P9N2_EX_4_L2_T2_PMU_SCOM = 0x28010AACull;
+//DUPS: 29010AAC,
+static const uint64_t P9N2_EX_5_L2_T2_PMU_SCOM = 0x2A010AACull;
+//DUPS: 2B010AAC,
+static const uint64_t P9N2_EX_6_L2_T2_PMU_SCOM = 0x2C010AACull;
+//DUPS: 2D010AAC,
+static const uint64_t P9N2_EX_7_L2_T2_PMU_SCOM = 0x2F010AACull;
+//DUPS: 2F010AAC,
+static const uint64_t P9N2_EX_8_L2_T2_PMU_SCOM = 0x30010AACull;
+//DUPS: 31010AAC,
+static const uint64_t P9N2_EX_9_L2_T2_PMU_SCOM = 0x32010AACull;
+//DUPS: 33010AAC,
+static const uint64_t P9N2_EX_L2_T2_PMU_SCOM = 0x20010AACull;
+//DUPS: 21010AAC,
+
+static const uint64_t P9N2_C_T3_PMU_SCOM = 0x20010AADull;
+
+static const uint64_t P9N2_C_0_T3_PMU_SCOM = 0x20010AADull;
+
+static const uint64_t P9N2_C_1_T3_PMU_SCOM = 0x21010AADull;
+
+static const uint64_t P9N2_C_2_T3_PMU_SCOM = 0x22010AADull;
+
+static const uint64_t P9N2_C_3_T3_PMU_SCOM = 0x23010AADull;
+
+static const uint64_t P9N2_C_4_T3_PMU_SCOM = 0x24010AADull;
+
+static const uint64_t P9N2_C_5_T3_PMU_SCOM = 0x25010AADull;
+
+static const uint64_t P9N2_C_6_T3_PMU_SCOM = 0x26010AADull;
+
+static const uint64_t P9N2_C_7_T3_PMU_SCOM = 0x27010AADull;
+
+static const uint64_t P9N2_C_8_T3_PMU_SCOM = 0x28010AADull;
+
+static const uint64_t P9N2_C_9_T3_PMU_SCOM = 0x29010AADull;
+
+static const uint64_t P9N2_C_10_T3_PMU_SCOM = 0x2A010AADull;
+
+static const uint64_t P9N2_C_11_T3_PMU_SCOM = 0x2B010AADull;
+
+static const uint64_t P9N2_C_12_T3_PMU_SCOM = 0x2C010AADull;
+
+static const uint64_t P9N2_C_13_T3_PMU_SCOM = 0x2D010AADull;
+
+static const uint64_t P9N2_C_14_T3_PMU_SCOM = 0x2E010AADull;
+
+static const uint64_t P9N2_C_15_T3_PMU_SCOM = 0x2F010AADull;
+
+static const uint64_t P9N2_C_16_T3_PMU_SCOM = 0x30010AADull;
+
+static const uint64_t P9N2_C_17_T3_PMU_SCOM = 0x31010AADull;
+
+static const uint64_t P9N2_C_18_T3_PMU_SCOM = 0x32010AADull;
+
+static const uint64_t P9N2_C_19_T3_PMU_SCOM = 0x33010AADull;
+
+static const uint64_t P9N2_C_20_T3_PMU_SCOM = 0x34010AADull;
+
+static const uint64_t P9N2_C_21_T3_PMU_SCOM = 0x35010AADull;
+
+static const uint64_t P9N2_C_22_T3_PMU_SCOM = 0x36010AADull;
+
+static const uint64_t P9N2_C_23_T3_PMU_SCOM = 0x37010AADull;
+
+static const uint64_t P9N2_EX_0_L2_T3_PMU_SCOM = 0x20010AADull;
+//DUPS: 21010AAD,
+static const uint64_t P9N2_EX_10_L2_T3_PMU_SCOM = 0x34010AADull;
+//DUPS: 35010AAD,
+static const uint64_t P9N2_EX_11_L2_T3_PMU_SCOM = 0x36010AADull;
+//DUPS: 37010AAD,
+static const uint64_t P9N2_EX_1_L2_T3_PMU_SCOM = 0x22010AADull;
+//DUPS: 23010AAD,
+static const uint64_t P9N2_EX_2_L2_T3_PMU_SCOM = 0x24010AADull;
+//DUPS: 25010AAD,
+static const uint64_t P9N2_EX_3_L2_T3_PMU_SCOM = 0x26010AADull;
+//DUPS: 27010AAD,
+static const uint64_t P9N2_EX_4_L2_T3_PMU_SCOM = 0x28010AADull;
+//DUPS: 29010AAD,
+static const uint64_t P9N2_EX_5_L2_T3_PMU_SCOM = 0x2A010AADull;
+//DUPS: 2B010AAD,
+static const uint64_t P9N2_EX_6_L2_T3_PMU_SCOM = 0x2C010AADull;
+//DUPS: 2D010AAD,
+static const uint64_t P9N2_EX_7_L2_T3_PMU_SCOM = 0x2F010AADull;
+//DUPS: 2F010AAD,
+static const uint64_t P9N2_EX_8_L2_T3_PMU_SCOM = 0x30010AADull;
+//DUPS: 31010AAD,
+static const uint64_t P9N2_EX_9_L2_T3_PMU_SCOM = 0x32010AADull;
+//DUPS: 33010AAD,
+static const uint64_t P9N2_EX_L2_T3_PMU_SCOM = 0x20010AADull;
+//DUPS: 21010AAD,
+
+static const uint64_t P9N2_C_TFAC_HOLD_OUT = 0x20010AB7ull;
+
+static const uint64_t P9N2_C_0_TFAC_HOLD_OUT = 0x20010AB7ull;
+
+static const uint64_t P9N2_C_1_TFAC_HOLD_OUT = 0x21010AB7ull;
+
+static const uint64_t P9N2_C_2_TFAC_HOLD_OUT = 0x22010AB7ull;
+
+static const uint64_t P9N2_C_3_TFAC_HOLD_OUT = 0x23010AB7ull;
+
+static const uint64_t P9N2_C_4_TFAC_HOLD_OUT = 0x24010AB7ull;
+
+static const uint64_t P9N2_C_5_TFAC_HOLD_OUT = 0x25010AB7ull;
+
+static const uint64_t P9N2_C_6_TFAC_HOLD_OUT = 0x26010AB7ull;
+
+static const uint64_t P9N2_C_7_TFAC_HOLD_OUT = 0x27010AB7ull;
+
+static const uint64_t P9N2_C_8_TFAC_HOLD_OUT = 0x28010AB7ull;
+
+static const uint64_t P9N2_C_9_TFAC_HOLD_OUT = 0x29010AB7ull;
+
+static const uint64_t P9N2_C_10_TFAC_HOLD_OUT = 0x2A010AB7ull;
+
+static const uint64_t P9N2_C_11_TFAC_HOLD_OUT = 0x2B010AB7ull;
+
+static const uint64_t P9N2_C_12_TFAC_HOLD_OUT = 0x2C010AB7ull;
+
+static const uint64_t P9N2_C_13_TFAC_HOLD_OUT = 0x2D010AB7ull;
+
+static const uint64_t P9N2_C_14_TFAC_HOLD_OUT = 0x2E010AB7ull;
+
+static const uint64_t P9N2_C_15_TFAC_HOLD_OUT = 0x2F010AB7ull;
+
+static const uint64_t P9N2_C_16_TFAC_HOLD_OUT = 0x30010AB7ull;
+
+static const uint64_t P9N2_C_17_TFAC_HOLD_OUT = 0x31010AB7ull;
+
+static const uint64_t P9N2_C_18_TFAC_HOLD_OUT = 0x32010AB7ull;
+
+static const uint64_t P9N2_C_19_TFAC_HOLD_OUT = 0x33010AB7ull;
+
+static const uint64_t P9N2_C_20_TFAC_HOLD_OUT = 0x34010AB7ull;
+
+static const uint64_t P9N2_C_21_TFAC_HOLD_OUT = 0x35010AB7ull;
+
+static const uint64_t P9N2_C_22_TFAC_HOLD_OUT = 0x36010AB7ull;
+
+static const uint64_t P9N2_C_23_TFAC_HOLD_OUT = 0x37010AB7ull;
+
+static const uint64_t P9N2_EX_0_L2_TFAC_HOLD_OUT = 0x20010AB7ull;
+//DUPS: 20010AB7,
+static const uint64_t P9N2_EX_10_L2_TFAC_HOLD_OUT = 0x34010AB7ull;
+//DUPS: 34010AB7,
+static const uint64_t P9N2_EX_11_L2_TFAC_HOLD_OUT = 0x36010AB7ull;
+//DUPS: 36010AB7,
+static const uint64_t P9N2_EX_1_L2_TFAC_HOLD_OUT = 0x22010AB7ull;
+//DUPS: 22010AB7,
+static const uint64_t P9N2_EX_2_L2_TFAC_HOLD_OUT = 0x24010AB7ull;
+//DUPS: 24010AB7,
+static const uint64_t P9N2_EX_3_L2_TFAC_HOLD_OUT = 0x26010AB7ull;
+//DUPS: 26010AB7,
+static const uint64_t P9N2_EX_4_L2_TFAC_HOLD_OUT = 0x28010AB7ull;
+//DUPS: 28010AB7,
+static const uint64_t P9N2_EX_5_L2_TFAC_HOLD_OUT = 0x2B010AB7ull;
+//DUPS: 2A010AB7,
+static const uint64_t P9N2_EX_6_L2_TFAC_HOLD_OUT = 0x2D010AB7ull;
+//DUPS: 2C010AB7,
+static const uint64_t P9N2_EX_7_L2_TFAC_HOLD_OUT = 0x2F010AB7ull;
+//DUPS: 2E010AB7,
+static const uint64_t P9N2_EX_8_L2_TFAC_HOLD_OUT = 0x30010AB7ull;
+//DUPS: 30010AB7,
+static const uint64_t P9N2_EX_9_L2_TFAC_HOLD_OUT = 0x32010AB7ull;
+//DUPS: 32010AB7,
+static const uint64_t P9N2_EX_L2_TFAC_HOLD_OUT = 0x20010AB7ull;
+//DUPS: 20010AB7,
+
+static const uint64_t P9N2_C_THERM_MODE_REG = 0x2005000Full;
+
+static const uint64_t P9N2_C_0_THERM_MODE_REG = 0x2005000Full;
+
+static const uint64_t P9N2_C_1_THERM_MODE_REG = 0x2105000Full;
+
+static const uint64_t P9N2_C_2_THERM_MODE_REG = 0x2205000Full;
+
+static const uint64_t P9N2_C_3_THERM_MODE_REG = 0x2305000Full;
+
+static const uint64_t P9N2_C_4_THERM_MODE_REG = 0x2405000Full;
+
+static const uint64_t P9N2_C_5_THERM_MODE_REG = 0x2505000Full;
+
+static const uint64_t P9N2_C_6_THERM_MODE_REG = 0x2605000Full;
+
+static const uint64_t P9N2_C_7_THERM_MODE_REG = 0x2705000Full;
+
+static const uint64_t P9N2_C_8_THERM_MODE_REG = 0x2805000Full;
+
+static const uint64_t P9N2_C_9_THERM_MODE_REG = 0x2905000Full;
+
+static const uint64_t P9N2_C_10_THERM_MODE_REG = 0x2A05000Full;
+
+static const uint64_t P9N2_C_11_THERM_MODE_REG = 0x2B05000Full;
+
+static const uint64_t P9N2_C_12_THERM_MODE_REG = 0x2C05000Full;
+
+static const uint64_t P9N2_C_13_THERM_MODE_REG = 0x2D05000Full;
+
+static const uint64_t P9N2_C_14_THERM_MODE_REG = 0x2E05000Full;
+
+static const uint64_t P9N2_C_15_THERM_MODE_REG = 0x2F05000Full;
+
+static const uint64_t P9N2_C_16_THERM_MODE_REG = 0x3005000Full;
+
+static const uint64_t P9N2_C_17_THERM_MODE_REG = 0x3105000Full;
+
+static const uint64_t P9N2_C_18_THERM_MODE_REG = 0x3205000Full;
+
+static const uint64_t P9N2_C_19_THERM_MODE_REG = 0x3305000Full;
+
+static const uint64_t P9N2_C_20_THERM_MODE_REG = 0x3405000Full;
+
+static const uint64_t P9N2_C_21_THERM_MODE_REG = 0x3505000Full;
+
+static const uint64_t P9N2_C_22_THERM_MODE_REG = 0x3605000Full;
+
+static const uint64_t P9N2_C_23_THERM_MODE_REG = 0x3705000Full;
+
+static const uint64_t P9N2_EQ_THERM_MODE_REG = 0x1005000Full;
+
+static const uint64_t P9N2_EQ_0_THERM_MODE_REG = 0x1005000Full;
+
+static const uint64_t P9N2_EQ_1_THERM_MODE_REG = 0x1105000Full;
+
+static const uint64_t P9N2_EQ_2_THERM_MODE_REG = 0x1205000Full;
+
+static const uint64_t P9N2_EQ_3_THERM_MODE_REG = 0x1305000Full;
+
+static const uint64_t P9N2_EQ_4_THERM_MODE_REG = 0x1405000Full;
+
+static const uint64_t P9N2_EQ_5_THERM_MODE_REG = 0x1505000Full;
+
+static const uint64_t P9N2_EX_THERM_MODE_REG = 0x2005000Full;
+//DUPS: 2105000F,
+static const uint64_t P9N2_EX_0_THERM_MODE_REG = 0x2005000Full;
+//DUPS: 2105000F,
+static const uint64_t P9N2_EX_1_THERM_MODE_REG = 0x2205000Full;
+//DUPS: 2305000F,
+static const uint64_t P9N2_EX_2_THERM_MODE_REG = 0x2405000Full;
+//DUPS: 2505000F,
+static const uint64_t P9N2_EX_3_THERM_MODE_REG = 0x2605000Full;
+//DUPS: 2705000F,
+static const uint64_t P9N2_EX_4_THERM_MODE_REG = 0x2805000Full;
+//DUPS: 2905000F,
+static const uint64_t P9N2_EX_5_THERM_MODE_REG = 0x2A05000Full;
+//DUPS: 2B05000F,
+static const uint64_t P9N2_EX_6_THERM_MODE_REG = 0x2C05000Full;
+//DUPS: 2D05000F,
+static const uint64_t P9N2_EX_7_THERM_MODE_REG = 0x2F05000Full;
+//DUPS: 2F05000F,
+static const uint64_t P9N2_EX_8_THERM_MODE_REG = 0x3005000Full;
+//DUPS: 3105000F,
+static const uint64_t P9N2_EX_9_THERM_MODE_REG = 0x3205000Full;
+//DUPS: 3305000F,
+static const uint64_t P9N2_EX_10_THERM_MODE_REG = 0x3405000Full;
+//DUPS: 3505000F,
+static const uint64_t P9N2_EX_11_THERM_MODE_REG = 0x3605000Full;
+//DUPS: 3705000F,
+
+static const uint64_t P9N2_C_THRCTL_HOLD_OUT = 0x20010A03ull;
+
+static const uint64_t P9N2_C_0_THRCTL_HOLD_OUT = 0x20010A03ull;
+
+static const uint64_t P9N2_C_1_THRCTL_HOLD_OUT = 0x21010A03ull;
+
+static const uint64_t P9N2_C_2_THRCTL_HOLD_OUT = 0x22010A03ull;
+
+static const uint64_t P9N2_C_3_THRCTL_HOLD_OUT = 0x23010A03ull;
+
+static const uint64_t P9N2_C_4_THRCTL_HOLD_OUT = 0x24010A03ull;
+
+static const uint64_t P9N2_C_5_THRCTL_HOLD_OUT = 0x25010A03ull;
+
+static const uint64_t P9N2_C_6_THRCTL_HOLD_OUT = 0x26010A03ull;
+
+static const uint64_t P9N2_C_7_THRCTL_HOLD_OUT = 0x27010A03ull;
+
+static const uint64_t P9N2_C_8_THRCTL_HOLD_OUT = 0x28010A03ull;
+
+static const uint64_t P9N2_C_9_THRCTL_HOLD_OUT = 0x29010A03ull;
+
+static const uint64_t P9N2_C_10_THRCTL_HOLD_OUT = 0x2A010A03ull;
+
+static const uint64_t P9N2_C_11_THRCTL_HOLD_OUT = 0x2B010A03ull;
+
+static const uint64_t P9N2_C_12_THRCTL_HOLD_OUT = 0x2C010A03ull;
+
+static const uint64_t P9N2_C_13_THRCTL_HOLD_OUT = 0x2D010A03ull;
+
+static const uint64_t P9N2_C_14_THRCTL_HOLD_OUT = 0x2E010A03ull;
+
+static const uint64_t P9N2_C_15_THRCTL_HOLD_OUT = 0x2F010A03ull;
+
+static const uint64_t P9N2_C_16_THRCTL_HOLD_OUT = 0x30010A03ull;
+
+static const uint64_t P9N2_C_17_THRCTL_HOLD_OUT = 0x31010A03ull;
+
+static const uint64_t P9N2_C_18_THRCTL_HOLD_OUT = 0x32010A03ull;
+
+static const uint64_t P9N2_C_19_THRCTL_HOLD_OUT = 0x33010A03ull;
+
+static const uint64_t P9N2_C_20_THRCTL_HOLD_OUT = 0x34010A03ull;
+
+static const uint64_t P9N2_C_21_THRCTL_HOLD_OUT = 0x35010A03ull;
+
+static const uint64_t P9N2_C_22_THRCTL_HOLD_OUT = 0x36010A03ull;
+
+static const uint64_t P9N2_C_23_THRCTL_HOLD_OUT = 0x37010A03ull;
+
+static const uint64_t P9N2_EX_0_L2_THRCTL_HOLD_OUT = 0x20010A03ull;
+//DUPS: 21010A03,
+static const uint64_t P9N2_EX_10_L2_THRCTL_HOLD_OUT = 0x34010A03ull;
+//DUPS: 35010A03,
+static const uint64_t P9N2_EX_11_L2_THRCTL_HOLD_OUT = 0x36010A03ull;
+//DUPS: 37010A03,
+static const uint64_t P9N2_EX_1_L2_THRCTL_HOLD_OUT = 0x22010A03ull;
+//DUPS: 23010A03,
+static const uint64_t P9N2_EX_2_L2_THRCTL_HOLD_OUT = 0x24010A03ull;
+//DUPS: 25010A03,
+static const uint64_t P9N2_EX_3_L2_THRCTL_HOLD_OUT = 0x26010A03ull;
+//DUPS: 27010A03,
+static const uint64_t P9N2_EX_4_L2_THRCTL_HOLD_OUT = 0x28010A03ull;
+//DUPS: 29010A03,
+static const uint64_t P9N2_EX_5_L2_THRCTL_HOLD_OUT = 0x2A010A03ull;
+//DUPS: 2B010A03,
+static const uint64_t P9N2_EX_6_L2_THRCTL_HOLD_OUT = 0x2C010A03ull;
+//DUPS: 2D010A03,
+static const uint64_t P9N2_EX_7_L2_THRCTL_HOLD_OUT = 0x2F010A03ull;
+//DUPS: 2F010A03,
+static const uint64_t P9N2_EX_8_L2_THRCTL_HOLD_OUT = 0x30010A03ull;
+//DUPS: 31010A03,
+static const uint64_t P9N2_EX_9_L2_THRCTL_HOLD_OUT = 0x32010A03ull;
+//DUPS: 33010A03,
+static const uint64_t P9N2_EX_L2_THRCTL_HOLD_OUT = 0x20010A03ull;
+//DUPS: 21010A03,
+
+static const uint64_t P9N2_C_THREAD_INFO = 0x20010A9Bull;
+
+static const uint64_t P9N2_C_0_THREAD_INFO = 0x20010A9Bull;
+
+static const uint64_t P9N2_C_1_THREAD_INFO = 0x21010A9Bull;
+
+static const uint64_t P9N2_C_2_THREAD_INFO = 0x22010A9Bull;
+
+static const uint64_t P9N2_C_3_THREAD_INFO = 0x23010A9Bull;
+
+static const uint64_t P9N2_C_4_THREAD_INFO = 0x24010A9Bull;
+
+static const uint64_t P9N2_C_5_THREAD_INFO = 0x25010A9Bull;
+
+static const uint64_t P9N2_C_6_THREAD_INFO = 0x26010A9Bull;
+
+static const uint64_t P9N2_C_7_THREAD_INFO = 0x27010A9Bull;
+
+static const uint64_t P9N2_C_8_THREAD_INFO = 0x28010A9Bull;
+
+static const uint64_t P9N2_C_9_THREAD_INFO = 0x29010A9Bull;
+
+static const uint64_t P9N2_C_10_THREAD_INFO = 0x2A010A9Bull;
+
+static const uint64_t P9N2_C_11_THREAD_INFO = 0x2B010A9Bull;
+
+static const uint64_t P9N2_C_12_THREAD_INFO = 0x2C010A9Bull;
+
+static const uint64_t P9N2_C_13_THREAD_INFO = 0x2D010A9Bull;
+
+static const uint64_t P9N2_C_14_THREAD_INFO = 0x2E010A9Bull;
+
+static const uint64_t P9N2_C_15_THREAD_INFO = 0x2F010A9Bull;
+
+static const uint64_t P9N2_C_16_THREAD_INFO = 0x30010A9Bull;
+
+static const uint64_t P9N2_C_17_THREAD_INFO = 0x31010A9Bull;
+
+static const uint64_t P9N2_C_18_THREAD_INFO = 0x32010A9Bull;
+
+static const uint64_t P9N2_C_19_THREAD_INFO = 0x33010A9Bull;
+
+static const uint64_t P9N2_C_20_THREAD_INFO = 0x34010A9Bull;
+
+static const uint64_t P9N2_C_21_THREAD_INFO = 0x35010A9Bull;
+
+static const uint64_t P9N2_C_22_THREAD_INFO = 0x36010A9Bull;
+
+static const uint64_t P9N2_C_23_THREAD_INFO = 0x37010A9Bull;
+
+static const uint64_t P9N2_EX_0_L2_THREAD_INFO = 0x20010A9Bull;
+//DUPS: 20010A9B,
+static const uint64_t P9N2_EX_10_L2_THREAD_INFO = 0x34010A9Bull;
+//DUPS: 34010A9B,
+static const uint64_t P9N2_EX_11_L2_THREAD_INFO = 0x36010A9Bull;
+//DUPS: 36010A9B,
+static const uint64_t P9N2_EX_1_L2_THREAD_INFO = 0x22010A9Bull;
+//DUPS: 22010A9B,
+static const uint64_t P9N2_EX_2_L2_THREAD_INFO = 0x24010A9Bull;
+//DUPS: 24010A9B,
+static const uint64_t P9N2_EX_3_L2_THREAD_INFO = 0x26010A9Bull;
+//DUPS: 26010A9B,
+static const uint64_t P9N2_EX_4_L2_THREAD_INFO = 0x28010A9Bull;
+//DUPS: 28010A9B,
+static const uint64_t P9N2_EX_5_L2_THREAD_INFO = 0x2B010A9Bull;
+//DUPS: 2A010A9B,
+static const uint64_t P9N2_EX_6_L2_THREAD_INFO = 0x2D010A9Bull;
+//DUPS: 2C010A9B,
+static const uint64_t P9N2_EX_7_L2_THREAD_INFO = 0x2F010A9Bull;
+//DUPS: 2E010A9B,
+static const uint64_t P9N2_EX_8_L2_THREAD_INFO = 0x30010A9Bull;
+//DUPS: 30010A9B,
+static const uint64_t P9N2_EX_9_L2_THREAD_INFO = 0x32010A9Bull;
+//DUPS: 32010A9B,
+static const uint64_t P9N2_EX_L2_THREAD_INFO = 0x20010A9Bull;
+//DUPS: 20010A9B,
+
+static const uint64_t P9N2_C_THROTTLE_CONTROL = 0x20010A9Eull;
+
+static const uint64_t P9N2_C_0_THROTTLE_CONTROL = 0x20010A9Eull;
+
+static const uint64_t P9N2_C_1_THROTTLE_CONTROL = 0x21010A9Eull;
+
+static const uint64_t P9N2_C_2_THROTTLE_CONTROL = 0x22010A9Eull;
+
+static const uint64_t P9N2_C_3_THROTTLE_CONTROL = 0x23010A9Eull;
+
+static const uint64_t P9N2_C_4_THROTTLE_CONTROL = 0x24010A9Eull;
+
+static const uint64_t P9N2_C_5_THROTTLE_CONTROL = 0x25010A9Eull;
+
+static const uint64_t P9N2_C_6_THROTTLE_CONTROL = 0x26010A9Eull;
+
+static const uint64_t P9N2_C_7_THROTTLE_CONTROL = 0x27010A9Eull;
+
+static const uint64_t P9N2_C_8_THROTTLE_CONTROL = 0x28010A9Eull;
+
+static const uint64_t P9N2_C_9_THROTTLE_CONTROL = 0x29010A9Eull;
+
+static const uint64_t P9N2_C_10_THROTTLE_CONTROL = 0x2A010A9Eull;
+
+static const uint64_t P9N2_C_11_THROTTLE_CONTROL = 0x2B010A9Eull;
+
+static const uint64_t P9N2_C_12_THROTTLE_CONTROL = 0x2C010A9Eull;
+
+static const uint64_t P9N2_C_13_THROTTLE_CONTROL = 0x2D010A9Eull;
+
+static const uint64_t P9N2_C_14_THROTTLE_CONTROL = 0x2E010A9Eull;
+
+static const uint64_t P9N2_C_15_THROTTLE_CONTROL = 0x2F010A9Eull;
+
+static const uint64_t P9N2_C_16_THROTTLE_CONTROL = 0x30010A9Eull;
+
+static const uint64_t P9N2_C_17_THROTTLE_CONTROL = 0x31010A9Eull;
+
+static const uint64_t P9N2_C_18_THROTTLE_CONTROL = 0x32010A9Eull;
+
+static const uint64_t P9N2_C_19_THROTTLE_CONTROL = 0x33010A9Eull;
+
+static const uint64_t P9N2_C_20_THROTTLE_CONTROL = 0x34010A9Eull;
+
+static const uint64_t P9N2_C_21_THROTTLE_CONTROL = 0x35010A9Eull;
+
+static const uint64_t P9N2_C_22_THROTTLE_CONTROL = 0x36010A9Eull;
+
+static const uint64_t P9N2_C_23_THROTTLE_CONTROL = 0x37010A9Eull;
+
+static const uint64_t P9N2_EX_THROTTLE_CONTROL = 0x20010A9Eull;
+//DUPS: 20010A9E,
+static const uint64_t P9N2_EX_0_THROTTLE_CONTROL = 0x20010A9Eull;
+//DUPS: 20010A9E,
+static const uint64_t P9N2_EX_1_THROTTLE_CONTROL = 0x22010A9Eull;
+//DUPS: 22010A9E,
+static const uint64_t P9N2_EX_2_THROTTLE_CONTROL = 0x24010A9Eull;
+//DUPS: 24010A9E,
+static const uint64_t P9N2_EX_3_THROTTLE_CONTROL = 0x26010A9Eull;
+//DUPS: 26010A9E,
+static const uint64_t P9N2_EX_4_THROTTLE_CONTROL = 0x28010A9Eull;
+//DUPS: 28010A9E,
+static const uint64_t P9N2_EX_5_THROTTLE_CONTROL = 0x2B010A9Eull;
+//DUPS: 2A010A9E,
+static const uint64_t P9N2_EX_6_THROTTLE_CONTROL = 0x2D010A9Eull;
+//DUPS: 2C010A9E,
+static const uint64_t P9N2_EX_7_THROTTLE_CONTROL = 0x2F010A9Eull;
+//DUPS: 2E010A9E,
+static const uint64_t P9N2_EX_8_THROTTLE_CONTROL = 0x30010A9Eull;
+//DUPS: 30010A9E,
+static const uint64_t P9N2_EX_9_THROTTLE_CONTROL = 0x32010A9Eull;
+//DUPS: 32010A9E,
+static const uint64_t P9N2_EX_10_THROTTLE_CONTROL = 0x34010A9Eull;
+//DUPS: 34010A9E,
+static const uint64_t P9N2_EX_11_THROTTLE_CONTROL = 0x36010A9Eull;
+//DUPS: 36010A9E,
+
+static const uint64_t P9N2_C_TIMEOUT_REG = 0x200F0010ull;
+
+static const uint64_t P9N2_C_0_TIMEOUT_REG = 0x200F0010ull;
+
+static const uint64_t P9N2_C_1_TIMEOUT_REG = 0x210F0010ull;
+
+static const uint64_t P9N2_C_2_TIMEOUT_REG = 0x220F0010ull;
+
+static const uint64_t P9N2_C_3_TIMEOUT_REG = 0x230F0010ull;
+
+static const uint64_t P9N2_C_4_TIMEOUT_REG = 0x240F0010ull;
+
+static const uint64_t P9N2_C_5_TIMEOUT_REG = 0x250F0010ull;
+
+static const uint64_t P9N2_C_6_TIMEOUT_REG = 0x260F0010ull;
+
+static const uint64_t P9N2_C_7_TIMEOUT_REG = 0x270F0010ull;
+
+static const uint64_t P9N2_C_8_TIMEOUT_REG = 0x280F0010ull;
+
+static const uint64_t P9N2_C_9_TIMEOUT_REG = 0x290F0010ull;
+
+static const uint64_t P9N2_C_10_TIMEOUT_REG = 0x2A0F0010ull;
+
+static const uint64_t P9N2_C_11_TIMEOUT_REG = 0x2B0F0010ull;
+
+static const uint64_t P9N2_C_12_TIMEOUT_REG = 0x2C0F0010ull;
+
+static const uint64_t P9N2_C_13_TIMEOUT_REG = 0x2D0F0010ull;
+
+static const uint64_t P9N2_C_14_TIMEOUT_REG = 0x2E0F0010ull;
+
+static const uint64_t P9N2_C_15_TIMEOUT_REG = 0x2F0F0010ull;
+
+static const uint64_t P9N2_C_16_TIMEOUT_REG = 0x300F0010ull;
+
+static const uint64_t P9N2_C_17_TIMEOUT_REG = 0x310F0010ull;
+
+static const uint64_t P9N2_C_18_TIMEOUT_REG = 0x320F0010ull;
+
+static const uint64_t P9N2_C_19_TIMEOUT_REG = 0x330F0010ull;
+
+static const uint64_t P9N2_C_20_TIMEOUT_REG = 0x340F0010ull;
+
+static const uint64_t P9N2_C_21_TIMEOUT_REG = 0x350F0010ull;
+
+static const uint64_t P9N2_C_22_TIMEOUT_REG = 0x360F0010ull;
+
+static const uint64_t P9N2_C_23_TIMEOUT_REG = 0x370F0010ull;
+
+static const uint64_t P9N2_EQ_TIMEOUT_REG = 0x100F0010ull;
+
+static const uint64_t P9N2_EQ_0_TIMEOUT_REG = 0x100F0010ull;
+
+static const uint64_t P9N2_EQ_1_TIMEOUT_REG = 0x110F0010ull;
+
+static const uint64_t P9N2_EQ_2_TIMEOUT_REG = 0x120F0010ull;
+
+static const uint64_t P9N2_EQ_3_TIMEOUT_REG = 0x130F0010ull;
+
+static const uint64_t P9N2_EQ_4_TIMEOUT_REG = 0x140F0010ull;
+
+static const uint64_t P9N2_EQ_5_TIMEOUT_REG = 0x150F0010ull;
+
+static const uint64_t P9N2_EX_TIMEOUT_REG = 0x200F0010ull;
+//DUPS: 210F0010,
+static const uint64_t P9N2_EX_0_TIMEOUT_REG = 0x200F0010ull;
+//DUPS: 210F0010,
+static const uint64_t P9N2_EX_1_TIMEOUT_REG = 0x220F0010ull;
+//DUPS: 220F0010,
+static const uint64_t P9N2_EX_2_TIMEOUT_REG = 0x240F0010ull;
+//DUPS: 250F0010,
+static const uint64_t P9N2_EX_3_TIMEOUT_REG = 0x260F0010ull;
+//DUPS: 270F0010,
+static const uint64_t P9N2_EX_4_TIMEOUT_REG = 0x280F0010ull;
+//DUPS: 290F0010,
+static const uint64_t P9N2_EX_5_TIMEOUT_REG = 0x2A0F0010ull;
+//DUPS: 2B0F0010,
+static const uint64_t P9N2_EX_6_TIMEOUT_REG = 0x2C0F0010ull;
+//DUPS: 2D0F0010,
+static const uint64_t P9N2_EX_7_TIMEOUT_REG = 0x2E0F0010ull;
+//DUPS: 2F0F0010,
+static const uint64_t P9N2_EX_8_TIMEOUT_REG = 0x300F0010ull;
+//DUPS: 310F0010,
+static const uint64_t P9N2_EX_9_TIMEOUT_REG = 0x320F0010ull;
+//DUPS: 330F0010,
+static const uint64_t P9N2_EX_10_TIMEOUT_REG = 0x340F0010ull;
+//DUPS: 350F0010,
+static const uint64_t P9N2_EX_11_TIMEOUT_REG = 0x360F0010ull;
+//DUPS: 370F0010,
+
+static const uint64_t P9N2_C_TIMESTAMP_COUNTER_READ = 0x2005001Cull;
+
+static const uint64_t P9N2_C_0_TIMESTAMP_COUNTER_READ = 0x2005001Cull;
+
+static const uint64_t P9N2_C_1_TIMESTAMP_COUNTER_READ = 0x2105001Cull;
+
+static const uint64_t P9N2_C_2_TIMESTAMP_COUNTER_READ = 0x2205001Cull;
+
+static const uint64_t P9N2_C_3_TIMESTAMP_COUNTER_READ = 0x2305001Cull;
+
+static const uint64_t P9N2_C_4_TIMESTAMP_COUNTER_READ = 0x2405001Cull;
+
+static const uint64_t P9N2_C_5_TIMESTAMP_COUNTER_READ = 0x2505001Cull;
+
+static const uint64_t P9N2_C_6_TIMESTAMP_COUNTER_READ = 0x2605001Cull;
+
+static const uint64_t P9N2_C_7_TIMESTAMP_COUNTER_READ = 0x2705001Cull;
+
+static const uint64_t P9N2_C_8_TIMESTAMP_COUNTER_READ = 0x2805001Cull;
+
+static const uint64_t P9N2_C_9_TIMESTAMP_COUNTER_READ = 0x2905001Cull;
+
+static const uint64_t P9N2_C_10_TIMESTAMP_COUNTER_READ = 0x2A05001Cull;
+
+static const uint64_t P9N2_C_11_TIMESTAMP_COUNTER_READ = 0x2B05001Cull;
+
+static const uint64_t P9N2_C_12_TIMESTAMP_COUNTER_READ = 0x2C05001Cull;
+
+static const uint64_t P9N2_C_13_TIMESTAMP_COUNTER_READ = 0x2D05001Cull;
+
+static const uint64_t P9N2_C_14_TIMESTAMP_COUNTER_READ = 0x2E05001Cull;
+
+static const uint64_t P9N2_C_15_TIMESTAMP_COUNTER_READ = 0x2F05001Cull;
+
+static const uint64_t P9N2_C_16_TIMESTAMP_COUNTER_READ = 0x3005001Cull;
+
+static const uint64_t P9N2_C_17_TIMESTAMP_COUNTER_READ = 0x3105001Cull;
+
+static const uint64_t P9N2_C_18_TIMESTAMP_COUNTER_READ = 0x3205001Cull;
+
+static const uint64_t P9N2_C_19_TIMESTAMP_COUNTER_READ = 0x3305001Cull;
+
+static const uint64_t P9N2_C_20_TIMESTAMP_COUNTER_READ = 0x3405001Cull;
+
+static const uint64_t P9N2_C_21_TIMESTAMP_COUNTER_READ = 0x3505001Cull;
+
+static const uint64_t P9N2_C_22_TIMESTAMP_COUNTER_READ = 0x3605001Cull;
+
+static const uint64_t P9N2_C_23_TIMESTAMP_COUNTER_READ = 0x3705001Cull;
+
+static const uint64_t P9N2_EQ_TIMESTAMP_COUNTER_READ = 0x1005001Cull;
+
+static const uint64_t P9N2_EQ_0_TIMESTAMP_COUNTER_READ = 0x1005001Cull;
+
+static const uint64_t P9N2_EQ_1_TIMESTAMP_COUNTER_READ = 0x1105001Cull;
+
+static const uint64_t P9N2_EQ_2_TIMESTAMP_COUNTER_READ = 0x1205001Cull;
+
+static const uint64_t P9N2_EQ_3_TIMESTAMP_COUNTER_READ = 0x1305001Cull;
+
+static const uint64_t P9N2_EQ_4_TIMESTAMP_COUNTER_READ = 0x1405001Cull;
+
+static const uint64_t P9N2_EQ_5_TIMESTAMP_COUNTER_READ = 0x1505001Cull;
+
+static const uint64_t P9N2_EX_TIMESTAMP_COUNTER_READ = 0x2005001Cull;
+//DUPS: 2105001C,
+static const uint64_t P9N2_EX_0_TIMESTAMP_COUNTER_READ = 0x2005001Cull;
+//DUPS: 2105001C,
+static const uint64_t P9N2_EX_1_TIMESTAMP_COUNTER_READ = 0x2205001Cull;
+//DUPS: 2305001C,
+static const uint64_t P9N2_EX_2_TIMESTAMP_COUNTER_READ = 0x2405001Cull;
+//DUPS: 2505001C,
+static const uint64_t P9N2_EX_3_TIMESTAMP_COUNTER_READ = 0x2605001Cull;
+//DUPS: 2705001C,
+static const uint64_t P9N2_EX_4_TIMESTAMP_COUNTER_READ = 0x2805001Cull;
+//DUPS: 2905001C,
+static const uint64_t P9N2_EX_5_TIMESTAMP_COUNTER_READ = 0x2A05001Cull;
+//DUPS: 2B05001C,
+static const uint64_t P9N2_EX_6_TIMESTAMP_COUNTER_READ = 0x2C05001Cull;
+//DUPS: 2D05001C,
+static const uint64_t P9N2_EX_7_TIMESTAMP_COUNTER_READ = 0x2F05001Cull;
+//DUPS: 2F05001C,
+static const uint64_t P9N2_EX_8_TIMESTAMP_COUNTER_READ = 0x3005001Cull;
+//DUPS: 3105001C,
+static const uint64_t P9N2_EX_9_TIMESTAMP_COUNTER_READ = 0x3205001Cull;
+//DUPS: 3305001C,
+static const uint64_t P9N2_EX_10_TIMESTAMP_COUNTER_READ = 0x3405001Cull;
+//DUPS: 3505001C,
+static const uint64_t P9N2_EX_11_TIMESTAMP_COUNTER_READ = 0x3605001Cull;
+//DUPS: 3705001C,
+
+static const uint64_t P9N2_C_TOD_READ = 0x20010AA3ull;
+
+static const uint64_t P9N2_C_0_TOD_READ = 0x20010AA3ull;
+
+static const uint64_t P9N2_C_1_TOD_READ = 0x21010AA3ull;
+
+static const uint64_t P9N2_C_2_TOD_READ = 0x22010AA3ull;
+
+static const uint64_t P9N2_C_3_TOD_READ = 0x23010AA3ull;
+
+static const uint64_t P9N2_C_4_TOD_READ = 0x24010AA3ull;
+
+static const uint64_t P9N2_C_5_TOD_READ = 0x25010AA3ull;
+
+static const uint64_t P9N2_C_6_TOD_READ = 0x26010AA3ull;
+
+static const uint64_t P9N2_C_7_TOD_READ = 0x27010AA3ull;
+
+static const uint64_t P9N2_C_8_TOD_READ = 0x28010AA3ull;
+
+static const uint64_t P9N2_C_9_TOD_READ = 0x29010AA3ull;
+
+static const uint64_t P9N2_C_10_TOD_READ = 0x2A010AA3ull;
+
+static const uint64_t P9N2_C_11_TOD_READ = 0x2B010AA3ull;
+
+static const uint64_t P9N2_C_12_TOD_READ = 0x2C010AA3ull;
+
+static const uint64_t P9N2_C_13_TOD_READ = 0x2D010AA3ull;
+
+static const uint64_t P9N2_C_14_TOD_READ = 0x2E010AA3ull;
+
+static const uint64_t P9N2_C_15_TOD_READ = 0x2F010AA3ull;
+
+static const uint64_t P9N2_C_16_TOD_READ = 0x30010AA3ull;
+
+static const uint64_t P9N2_C_17_TOD_READ = 0x31010AA3ull;
+
+static const uint64_t P9N2_C_18_TOD_READ = 0x32010AA3ull;
+
+static const uint64_t P9N2_C_19_TOD_READ = 0x33010AA3ull;
+
+static const uint64_t P9N2_C_20_TOD_READ = 0x34010AA3ull;
+
+static const uint64_t P9N2_C_21_TOD_READ = 0x35010AA3ull;
+
+static const uint64_t P9N2_C_22_TOD_READ = 0x36010AA3ull;
+
+static const uint64_t P9N2_C_23_TOD_READ = 0x37010AA3ull;
+
+static const uint64_t P9N2_EX_0_L2_TOD_READ = 0x20010AA3ull;
+//DUPS: 20010AA3,
+static const uint64_t P9N2_EX_10_L2_TOD_READ = 0x34010AA3ull;
+//DUPS: 34010AA3,
+static const uint64_t P9N2_EX_11_L2_TOD_READ = 0x36010AA3ull;
+//DUPS: 36010AA3,
+static const uint64_t P9N2_EX_1_L2_TOD_READ = 0x22010AA3ull;
+//DUPS: 22010AA3,
+static const uint64_t P9N2_EX_2_L2_TOD_READ = 0x24010AA3ull;
+//DUPS: 24010AA3,
+static const uint64_t P9N2_EX_3_L2_TOD_READ = 0x26010AA3ull;
+//DUPS: 26010AA3,
+static const uint64_t P9N2_EX_4_L2_TOD_READ = 0x28010AA3ull;
+//DUPS: 28010AA3,
+static const uint64_t P9N2_EX_5_L2_TOD_READ = 0x2B010AA3ull;
+//DUPS: 2A010AA3,
+static const uint64_t P9N2_EX_6_L2_TOD_READ = 0x2D010AA3ull;
+//DUPS: 2C010AA3,
+static const uint64_t P9N2_EX_7_L2_TOD_READ = 0x2F010AA3ull;
+//DUPS: 2E010AA3,
+static const uint64_t P9N2_EX_8_L2_TOD_READ = 0x30010AA3ull;
+//DUPS: 30010AA3,
+static const uint64_t P9N2_EX_9_L2_TOD_READ = 0x32010AA3ull;
+//DUPS: 32010AA3,
+static const uint64_t P9N2_EX_L2_TOD_READ = 0x20010AA3ull;
+//DUPS: 20010AA3,
+
+static const uint64_t P9N2_C_TOD_STEP_CHECK = 0x20010AA4ull;
+
+static const uint64_t P9N2_C_0_TOD_STEP_CHECK = 0x20010AA4ull;
+
+static const uint64_t P9N2_C_1_TOD_STEP_CHECK = 0x21010AA4ull;
+
+static const uint64_t P9N2_C_2_TOD_STEP_CHECK = 0x22010AA4ull;
+
+static const uint64_t P9N2_C_3_TOD_STEP_CHECK = 0x23010AA4ull;
+
+static const uint64_t P9N2_C_4_TOD_STEP_CHECK = 0x24010AA4ull;
+
+static const uint64_t P9N2_C_5_TOD_STEP_CHECK = 0x25010AA4ull;
+
+static const uint64_t P9N2_C_6_TOD_STEP_CHECK = 0x26010AA4ull;
+
+static const uint64_t P9N2_C_7_TOD_STEP_CHECK = 0x27010AA4ull;
+
+static const uint64_t P9N2_C_8_TOD_STEP_CHECK = 0x28010AA4ull;
+
+static const uint64_t P9N2_C_9_TOD_STEP_CHECK = 0x29010AA4ull;
+
+static const uint64_t P9N2_C_10_TOD_STEP_CHECK = 0x2A010AA4ull;
+
+static const uint64_t P9N2_C_11_TOD_STEP_CHECK = 0x2B010AA4ull;
+
+static const uint64_t P9N2_C_12_TOD_STEP_CHECK = 0x2C010AA4ull;
+
+static const uint64_t P9N2_C_13_TOD_STEP_CHECK = 0x2D010AA4ull;
+
+static const uint64_t P9N2_C_14_TOD_STEP_CHECK = 0x2E010AA4ull;
+
+static const uint64_t P9N2_C_15_TOD_STEP_CHECK = 0x2F010AA4ull;
+
+static const uint64_t P9N2_C_16_TOD_STEP_CHECK = 0x30010AA4ull;
+
+static const uint64_t P9N2_C_17_TOD_STEP_CHECK = 0x31010AA4ull;
+
+static const uint64_t P9N2_C_18_TOD_STEP_CHECK = 0x32010AA4ull;
+
+static const uint64_t P9N2_C_19_TOD_STEP_CHECK = 0x33010AA4ull;
+
+static const uint64_t P9N2_C_20_TOD_STEP_CHECK = 0x34010AA4ull;
+
+static const uint64_t P9N2_C_21_TOD_STEP_CHECK = 0x35010AA4ull;
+
+static const uint64_t P9N2_C_22_TOD_STEP_CHECK = 0x36010AA4ull;
+
+static const uint64_t P9N2_C_23_TOD_STEP_CHECK = 0x37010AA4ull;
+
+static const uint64_t P9N2_EX_0_L2_TOD_STEP_CHECK = 0x20010AA4ull;
+//DUPS: 20010AA4,
+static const uint64_t P9N2_EX_10_L2_TOD_STEP_CHECK = 0x34010AA4ull;
+//DUPS: 34010AA4,
+static const uint64_t P9N2_EX_11_L2_TOD_STEP_CHECK = 0x36010AA4ull;
+//DUPS: 36010AA4,
+static const uint64_t P9N2_EX_1_L2_TOD_STEP_CHECK = 0x22010AA4ull;
+//DUPS: 22010AA4,
+static const uint64_t P9N2_EX_2_L2_TOD_STEP_CHECK = 0x24010AA4ull;
+//DUPS: 24010AA4,
+static const uint64_t P9N2_EX_3_L2_TOD_STEP_CHECK = 0x26010AA4ull;
+//DUPS: 26010AA4,
+static const uint64_t P9N2_EX_4_L2_TOD_STEP_CHECK = 0x28010AA4ull;
+//DUPS: 28010AA4,
+static const uint64_t P9N2_EX_5_L2_TOD_STEP_CHECK = 0x2B010AA4ull;
+//DUPS: 2A010AA4,
+static const uint64_t P9N2_EX_6_L2_TOD_STEP_CHECK = 0x2D010AA4ull;
+//DUPS: 2C010AA4,
+static const uint64_t P9N2_EX_7_L2_TOD_STEP_CHECK = 0x2F010AA4ull;
+//DUPS: 2E010AA4,
+static const uint64_t P9N2_EX_8_L2_TOD_STEP_CHECK = 0x30010AA4ull;
+//DUPS: 30010AA4,
+static const uint64_t P9N2_EX_9_L2_TOD_STEP_CHECK = 0x32010AA4ull;
+//DUPS: 32010AA4,
+static const uint64_t P9N2_EX_L2_TOD_STEP_CHECK = 0x20010AA4ull;
+//DUPS: 20010AA4,
+
+static const uint64_t P9N2_C_TOD_SYNC000 = 0x20010AA3ull;
+
+
+static const uint64_t P9N2_C_0_TOD_SYNC000 = 0x20010AA3ull;
+
+static const uint64_t P9N2_C_1_TOD_SYNC000 = 0x21010AA3ull;
+
+static const uint64_t P9N2_C_2_TOD_SYNC000 = 0x22010AA3ull;
+
+static const uint64_t P9N2_C_3_TOD_SYNC000 = 0x23010AA3ull;
+
+static const uint64_t P9N2_C_4_TOD_SYNC000 = 0x24010AA3ull;
+
+static const uint64_t P9N2_C_5_TOD_SYNC000 = 0x25010AA3ull;
+
+static const uint64_t P9N2_C_6_TOD_SYNC000 = 0x26010AA3ull;
+
+static const uint64_t P9N2_C_7_TOD_SYNC000 = 0x27010AA3ull;
+
+static const uint64_t P9N2_C_8_TOD_SYNC000 = 0x28010AA3ull;
+
+static const uint64_t P9N2_C_9_TOD_SYNC000 = 0x29010AA3ull;
+
+static const uint64_t P9N2_C_10_TOD_SYNC000 = 0x2A010AA3ull;
+
+static const uint64_t P9N2_C_11_TOD_SYNC000 = 0x2B010AA3ull;
+
+static const uint64_t P9N2_C_12_TOD_SYNC000 = 0x2C010AA3ull;
+
+static const uint64_t P9N2_C_13_TOD_SYNC000 = 0x2D010AA3ull;
+
+static const uint64_t P9N2_C_14_TOD_SYNC000 = 0x2E010AA3ull;
+
+static const uint64_t P9N2_C_15_TOD_SYNC000 = 0x2F010AA3ull;
+
+static const uint64_t P9N2_C_16_TOD_SYNC000 = 0x30010AA3ull;
+
+static const uint64_t P9N2_C_17_TOD_SYNC000 = 0x31010AA3ull;
+
+static const uint64_t P9N2_C_18_TOD_SYNC000 = 0x32010AA3ull;
+
+static const uint64_t P9N2_C_19_TOD_SYNC000 = 0x33010AA3ull;
+
+static const uint64_t P9N2_C_20_TOD_SYNC000 = 0x34010AA3ull;
+
+static const uint64_t P9N2_C_21_TOD_SYNC000 = 0x35010AA3ull;
+
+static const uint64_t P9N2_C_22_TOD_SYNC000 = 0x36010AA3ull;
+
+static const uint64_t P9N2_C_23_TOD_SYNC000 = 0x37010AA3ull;
+
+static const uint64_t P9N2_EX_0_L2_TOD_SYNC000 = 0x20010AA3ull;
+//DUPS: 20010AA3,
+static const uint64_t P9N2_EX_10_L2_TOD_SYNC000 = 0x34010AA3ull;
+//DUPS: 34010AA3,
+static const uint64_t P9N2_EX_11_L2_TOD_SYNC000 = 0x36010AA3ull;
+//DUPS: 36010AA3,
+static const uint64_t P9N2_EX_1_L2_TOD_SYNC000 = 0x22010AA3ull;
+//DUPS: 22010AA3,
+static const uint64_t P9N2_EX_2_L2_TOD_SYNC000 = 0x24010AA3ull;
+//DUPS: 24010AA3,
+static const uint64_t P9N2_EX_3_L2_TOD_SYNC000 = 0x26010AA3ull;
+//DUPS: 26010AA3,
+static const uint64_t P9N2_EX_4_L2_TOD_SYNC000 = 0x28010AA3ull;
+//DUPS: 28010AA3,
+static const uint64_t P9N2_EX_5_L2_TOD_SYNC000 = 0x2B010AA3ull;
+//DUPS: 2A010AA3,
+static const uint64_t P9N2_EX_6_L2_TOD_SYNC000 = 0x2D010AA3ull;
+//DUPS: 2C010AA3,
+static const uint64_t P9N2_EX_7_L2_TOD_SYNC000 = 0x2F010AA3ull;
+//DUPS: 2E010AA3,
+static const uint64_t P9N2_EX_8_L2_TOD_SYNC000 = 0x30010AA3ull;
+//DUPS: 30010AA3,
+static const uint64_t P9N2_EX_9_L2_TOD_SYNC000 = 0x32010AA3ull;
+//DUPS: 32010AA3,
+static const uint64_t P9N2_EX_L2_TOD_SYNC000 = 0x20010AA3ull;
+//DUPS: 20010AA3,
+
+static const uint64_t P9N2_C_TOD_SYNC001 = 0x20010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_0_TOD_SYNC001 = 0x20010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_1_TOD_SYNC001 = 0x21010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_2_TOD_SYNC001 = 0x22010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_3_TOD_SYNC001 = 0x23010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_4_TOD_SYNC001 = 0x24010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_5_TOD_SYNC001 = 0x25010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_6_TOD_SYNC001 = 0x26010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_7_TOD_SYNC001 = 0x27010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_8_TOD_SYNC001 = 0x28010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_9_TOD_SYNC001 = 0x29010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_10_TOD_SYNC001 = 0x2A010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_11_TOD_SYNC001 = 0x2B010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_12_TOD_SYNC001 = 0x2C010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_13_TOD_SYNC001 = 0x2D010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_14_TOD_SYNC001 = 0x2E010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_15_TOD_SYNC001 = 0x2F010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_16_TOD_SYNC001 = 0x30010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_17_TOD_SYNC001 = 0x31010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_18_TOD_SYNC001 = 0x32010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_19_TOD_SYNC001 = 0x33010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_20_TOD_SYNC001 = 0x34010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_21_TOD_SYNC001 = 0x35010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_22_TOD_SYNC001 = 0x36010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_23_TOD_SYNC001 = 0x37010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_EX_0_L2_TOD_SYNC001 = 0x20010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 20010AA3,
+static const uint64_t P9N2_EX_10_L2_TOD_SYNC001 = 0x34010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 34010AA3,
+static const uint64_t P9N2_EX_11_L2_TOD_SYNC001 = 0x36010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 36010AA3,
+static const uint64_t P9N2_EX_1_L2_TOD_SYNC001 = 0x22010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 22010AA3,
+static const uint64_t P9N2_EX_2_L2_TOD_SYNC001 = 0x24010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 24010AA3,
+static const uint64_t P9N2_EX_3_L2_TOD_SYNC001 = 0x26010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 26010AA3,
+static const uint64_t P9N2_EX_4_L2_TOD_SYNC001 = 0x28010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 28010AA3,
+static const uint64_t P9N2_EX_5_L2_TOD_SYNC001 = 0x2B010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 2A010AA3,
+static const uint64_t P9N2_EX_6_L2_TOD_SYNC001 = 0x2D010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 2C010AA3,
+static const uint64_t P9N2_EX_7_L2_TOD_SYNC001 = 0x2F010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 2E010AA3,
+static const uint64_t P9N2_EX_8_L2_TOD_SYNC001 = 0x30010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 30010AA3,
+static const uint64_t P9N2_EX_9_L2_TOD_SYNC001 = 0x32010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 32010AA3,
+static const uint64_t P9N2_EX_L2_TOD_SYNC001 = 0x20010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 20010AA3,
+
+static const uint64_t P9N2_C_TOD_SYNC010 = 0x20010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_0_TOD_SYNC010 = 0x20010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_1_TOD_SYNC010 = 0x21010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_2_TOD_SYNC010 = 0x22010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_3_TOD_SYNC010 = 0x23010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_4_TOD_SYNC010 = 0x24010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_5_TOD_SYNC010 = 0x25010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_6_TOD_SYNC010 = 0x26010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_7_TOD_SYNC010 = 0x27010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_8_TOD_SYNC010 = 0x28010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_9_TOD_SYNC010 = 0x29010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_10_TOD_SYNC010 = 0x2A010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_11_TOD_SYNC010 = 0x2B010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_12_TOD_SYNC010 = 0x2C010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_13_TOD_SYNC010 = 0x2D010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_14_TOD_SYNC010 = 0x2E010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_15_TOD_SYNC010 = 0x2F010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_16_TOD_SYNC010 = 0x30010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_17_TOD_SYNC010 = 0x31010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_18_TOD_SYNC010 = 0x32010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_19_TOD_SYNC010 = 0x33010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_20_TOD_SYNC010 = 0x34010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_21_TOD_SYNC010 = 0x35010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_22_TOD_SYNC010 = 0x36010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_23_TOD_SYNC010 = 0x37010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_EX_0_L2_TOD_SYNC010 = 0x20010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 20010AA3,
+static const uint64_t P9N2_EX_10_L2_TOD_SYNC010 = 0x34010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 34010AA3,
+static const uint64_t P9N2_EX_11_L2_TOD_SYNC010 = 0x36010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 36010AA3,
+static const uint64_t P9N2_EX_1_L2_TOD_SYNC010 = 0x22010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 22010AA3,
+static const uint64_t P9N2_EX_2_L2_TOD_SYNC010 = 0x24010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 24010AA3,
+static const uint64_t P9N2_EX_3_L2_TOD_SYNC010 = 0x26010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 26010AA3,
+static const uint64_t P9N2_EX_4_L2_TOD_SYNC010 = 0x28010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 28010AA3,
+static const uint64_t P9N2_EX_5_L2_TOD_SYNC010 = 0x2B010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 2A010AA3,
+static const uint64_t P9N2_EX_6_L2_TOD_SYNC010 = 0x2D010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 2C010AA3,
+static const uint64_t P9N2_EX_7_L2_TOD_SYNC010 = 0x2F010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 2E010AA3,
+static const uint64_t P9N2_EX_8_L2_TOD_SYNC010 = 0x30010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 30010AA3,
+static const uint64_t P9N2_EX_9_L2_TOD_SYNC010 = 0x32010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 32010AA3,
+static const uint64_t P9N2_EX_L2_TOD_SYNC010 = 0x20010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 20010AA3,
+
+static const uint64_t P9N2_C_TOD_SYNC011 = 0x20010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_0_TOD_SYNC011 = 0x20010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_1_TOD_SYNC011 = 0x21010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_2_TOD_SYNC011 = 0x22010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_3_TOD_SYNC011 = 0x23010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_4_TOD_SYNC011 = 0x24010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_5_TOD_SYNC011 = 0x25010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_6_TOD_SYNC011 = 0x26010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_7_TOD_SYNC011 = 0x27010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_8_TOD_SYNC011 = 0x28010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_9_TOD_SYNC011 = 0x29010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_10_TOD_SYNC011 = 0x2A010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_11_TOD_SYNC011 = 0x2B010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_12_TOD_SYNC011 = 0x2C010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_13_TOD_SYNC011 = 0x2D010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_14_TOD_SYNC011 = 0x2E010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_15_TOD_SYNC011 = 0x2F010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_16_TOD_SYNC011 = 0x30010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_17_TOD_SYNC011 = 0x31010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_18_TOD_SYNC011 = 0x32010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_19_TOD_SYNC011 = 0x33010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_20_TOD_SYNC011 = 0x34010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_21_TOD_SYNC011 = 0x35010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_22_TOD_SYNC011 = 0x36010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_23_TOD_SYNC011 = 0x37010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_EX_0_L2_TOD_SYNC011 = 0x20010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 20010AA3,
+static const uint64_t P9N2_EX_10_L2_TOD_SYNC011 = 0x34010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 34010AA3,
+static const uint64_t P9N2_EX_11_L2_TOD_SYNC011 = 0x36010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 36010AA3,
+static const uint64_t P9N2_EX_1_L2_TOD_SYNC011 = 0x22010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 22010AA3,
+static const uint64_t P9N2_EX_2_L2_TOD_SYNC011 = 0x24010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 24010AA3,
+static const uint64_t P9N2_EX_3_L2_TOD_SYNC011 = 0x26010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 26010AA3,
+static const uint64_t P9N2_EX_4_L2_TOD_SYNC011 = 0x28010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 28010AA3,
+static const uint64_t P9N2_EX_5_L2_TOD_SYNC011 = 0x2B010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 2A010AA3,
+static const uint64_t P9N2_EX_6_L2_TOD_SYNC011 = 0x2D010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 2C010AA3,
+static const uint64_t P9N2_EX_7_L2_TOD_SYNC011 = 0x2F010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 2E010AA3,
+static const uint64_t P9N2_EX_8_L2_TOD_SYNC011 = 0x30010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 30010AA3,
+static const uint64_t P9N2_EX_9_L2_TOD_SYNC011 = 0x32010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 32010AA3,
+static const uint64_t P9N2_EX_L2_TOD_SYNC011 = 0x20010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 20010AA3,
+
+static const uint64_t P9N2_C_TOD_SYNC100 = 0x20010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_0_TOD_SYNC100 = 0x20010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_1_TOD_SYNC100 = 0x21010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_2_TOD_SYNC100 = 0x22010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_3_TOD_SYNC100 = 0x23010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_4_TOD_SYNC100 = 0x24010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_5_TOD_SYNC100 = 0x25010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_6_TOD_SYNC100 = 0x26010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_7_TOD_SYNC100 = 0x27010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_8_TOD_SYNC100 = 0x28010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_9_TOD_SYNC100 = 0x29010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_10_TOD_SYNC100 = 0x2A010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_11_TOD_SYNC100 = 0x2B010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_12_TOD_SYNC100 = 0x2C010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_13_TOD_SYNC100 = 0x2D010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_14_TOD_SYNC100 = 0x2E010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_15_TOD_SYNC100 = 0x2F010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_16_TOD_SYNC100 = 0x30010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_17_TOD_SYNC100 = 0x31010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_18_TOD_SYNC100 = 0x32010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_19_TOD_SYNC100 = 0x33010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_20_TOD_SYNC100 = 0x34010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_21_TOD_SYNC100 = 0x35010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_22_TOD_SYNC100 = 0x36010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_23_TOD_SYNC100 = 0x37010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_EX_0_L2_TOD_SYNC100 = 0x20010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 20010AA3,
+static const uint64_t P9N2_EX_10_L2_TOD_SYNC100 = 0x34010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 34010AA3,
+static const uint64_t P9N2_EX_11_L2_TOD_SYNC100 = 0x36010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 36010AA3,
+static const uint64_t P9N2_EX_1_L2_TOD_SYNC100 = 0x22010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 22010AA3,
+static const uint64_t P9N2_EX_2_L2_TOD_SYNC100 = 0x24010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 24010AA3,
+static const uint64_t P9N2_EX_3_L2_TOD_SYNC100 = 0x26010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 26010AA3,
+static const uint64_t P9N2_EX_4_L2_TOD_SYNC100 = 0x28010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 28010AA3,
+static const uint64_t P9N2_EX_5_L2_TOD_SYNC100 = 0x2B010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 2A010AA3,
+static const uint64_t P9N2_EX_6_L2_TOD_SYNC100 = 0x2D010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 2C010AA3,
+static const uint64_t P9N2_EX_7_L2_TOD_SYNC100 = 0x2F010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 2E010AA3,
+static const uint64_t P9N2_EX_8_L2_TOD_SYNC100 = 0x30010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 30010AA3,
+static const uint64_t P9N2_EX_9_L2_TOD_SYNC100 = 0x32010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 32010AA3,
+static const uint64_t P9N2_EX_L2_TOD_SYNC100 = 0x20010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 20010AA3,
+
+static const uint64_t P9N2_C_TOD_SYNC101 = 0x20010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_0_TOD_SYNC101 = 0x20010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_1_TOD_SYNC101 = 0x21010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_2_TOD_SYNC101 = 0x22010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_3_TOD_SYNC101 = 0x23010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_4_TOD_SYNC101 = 0x24010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_5_TOD_SYNC101 = 0x25010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_6_TOD_SYNC101 = 0x26010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_7_TOD_SYNC101 = 0x27010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_8_TOD_SYNC101 = 0x28010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_9_TOD_SYNC101 = 0x29010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_10_TOD_SYNC101 = 0x2A010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_11_TOD_SYNC101 = 0x2B010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_12_TOD_SYNC101 = 0x2C010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_13_TOD_SYNC101 = 0x2D010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_14_TOD_SYNC101 = 0x2E010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_15_TOD_SYNC101 = 0x2F010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_16_TOD_SYNC101 = 0x30010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_17_TOD_SYNC101 = 0x31010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_18_TOD_SYNC101 = 0x32010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_19_TOD_SYNC101 = 0x33010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_20_TOD_SYNC101 = 0x34010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_21_TOD_SYNC101 = 0x35010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_22_TOD_SYNC101 = 0x36010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_23_TOD_SYNC101 = 0x37010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_EX_0_L2_TOD_SYNC101 = 0x20010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 20010AA3,
+static const uint64_t P9N2_EX_10_L2_TOD_SYNC101 = 0x34010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 34010AA3,
+static const uint64_t P9N2_EX_11_L2_TOD_SYNC101 = 0x36010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 36010AA3,
+static const uint64_t P9N2_EX_1_L2_TOD_SYNC101 = 0x22010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 22010AA3,
+static const uint64_t P9N2_EX_2_L2_TOD_SYNC101 = 0x24010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 24010AA3,
+static const uint64_t P9N2_EX_3_L2_TOD_SYNC101 = 0x26010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 26010AA3,
+static const uint64_t P9N2_EX_4_L2_TOD_SYNC101 = 0x28010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 28010AA3,
+static const uint64_t P9N2_EX_5_L2_TOD_SYNC101 = 0x2B010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 2A010AA3,
+static const uint64_t P9N2_EX_6_L2_TOD_SYNC101 = 0x2D010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 2C010AA3,
+static const uint64_t P9N2_EX_7_L2_TOD_SYNC101 = 0x2F010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 2E010AA3,
+static const uint64_t P9N2_EX_8_L2_TOD_SYNC101 = 0x30010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 30010AA3,
+static const uint64_t P9N2_EX_9_L2_TOD_SYNC101 = 0x32010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 32010AA3,
+static const uint64_t P9N2_EX_L2_TOD_SYNC101 = 0x20010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 20010AA3,
+
+static const uint64_t P9N2_C_TOD_SYNC110 = 0x20010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_0_TOD_SYNC110 = 0x20010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_1_TOD_SYNC110 = 0x21010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_2_TOD_SYNC110 = 0x22010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_3_TOD_SYNC110 = 0x23010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_4_TOD_SYNC110 = 0x24010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_5_TOD_SYNC110 = 0x25010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_6_TOD_SYNC110 = 0x26010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_7_TOD_SYNC110 = 0x27010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_8_TOD_SYNC110 = 0x28010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_9_TOD_SYNC110 = 0x29010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_10_TOD_SYNC110 = 0x2A010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_11_TOD_SYNC110 = 0x2B010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_12_TOD_SYNC110 = 0x2C010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_13_TOD_SYNC110 = 0x2D010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_14_TOD_SYNC110 = 0x2E010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_15_TOD_SYNC110 = 0x2F010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_16_TOD_SYNC110 = 0x30010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_17_TOD_SYNC110 = 0x31010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_18_TOD_SYNC110 = 0x32010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_19_TOD_SYNC110 = 0x33010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_20_TOD_SYNC110 = 0x34010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_21_TOD_SYNC110 = 0x35010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_22_TOD_SYNC110 = 0x36010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_23_TOD_SYNC110 = 0x37010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_EX_0_L2_TOD_SYNC110 = 0x20010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 20010AA3,
+static const uint64_t P9N2_EX_10_L2_TOD_SYNC110 = 0x34010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 34010AA3,
+static const uint64_t P9N2_EX_11_L2_TOD_SYNC110 = 0x36010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 36010AA3,
+static const uint64_t P9N2_EX_1_L2_TOD_SYNC110 = 0x22010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 22010AA3,
+static const uint64_t P9N2_EX_2_L2_TOD_SYNC110 = 0x24010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 24010AA3,
+static const uint64_t P9N2_EX_3_L2_TOD_SYNC110 = 0x26010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 26010AA3,
+static const uint64_t P9N2_EX_4_L2_TOD_SYNC110 = 0x28010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 28010AA3,
+static const uint64_t P9N2_EX_5_L2_TOD_SYNC110 = 0x2B010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 2A010AA3,
+static const uint64_t P9N2_EX_6_L2_TOD_SYNC110 = 0x2D010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 2C010AA3,
+static const uint64_t P9N2_EX_7_L2_TOD_SYNC110 = 0x2F010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 2E010AA3,
+static const uint64_t P9N2_EX_8_L2_TOD_SYNC110 = 0x30010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 30010AA3,
+static const uint64_t P9N2_EX_9_L2_TOD_SYNC110 = 0x32010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 32010AA3,
+static const uint64_t P9N2_EX_L2_TOD_SYNC110 = 0x20010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 20010AA3,
+
+static const uint64_t P9N2_C_TOD_SYNC111 = 0x20010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_0_TOD_SYNC111 = 0x20010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_1_TOD_SYNC111 = 0x21010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_2_TOD_SYNC111 = 0x22010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_3_TOD_SYNC111 = 0x23010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_4_TOD_SYNC111 = 0x24010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_5_TOD_SYNC111 = 0x25010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_6_TOD_SYNC111 = 0x26010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_7_TOD_SYNC111 = 0x27010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_8_TOD_SYNC111 = 0x28010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_9_TOD_SYNC111 = 0x29010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_10_TOD_SYNC111 = 0x2A010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_11_TOD_SYNC111 = 0x2B010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_12_TOD_SYNC111 = 0x2C010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_13_TOD_SYNC111 = 0x2D010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_14_TOD_SYNC111 = 0x2E010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_15_TOD_SYNC111 = 0x2F010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_16_TOD_SYNC111 = 0x30010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_17_TOD_SYNC111 = 0x31010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_18_TOD_SYNC111 = 0x32010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_19_TOD_SYNC111 = 0x33010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_20_TOD_SYNC111 = 0x34010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_21_TOD_SYNC111 = 0x35010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_22_TOD_SYNC111 = 0x36010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_C_23_TOD_SYNC111 = 0x37010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_EX_0_L2_TOD_SYNC111 = 0x20010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 20010AA3,
+static const uint64_t P9N2_EX_10_L2_TOD_SYNC111 = 0x34010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 34010AA3,
+static const uint64_t P9N2_EX_11_L2_TOD_SYNC111 = 0x36010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 36010AA3,
+static const uint64_t P9N2_EX_1_L2_TOD_SYNC111 = 0x22010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 22010AA3,
+static const uint64_t P9N2_EX_2_L2_TOD_SYNC111 = 0x24010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 24010AA3,
+static const uint64_t P9N2_EX_3_L2_TOD_SYNC111 = 0x26010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 26010AA3,
+static const uint64_t P9N2_EX_4_L2_TOD_SYNC111 = 0x28010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 28010AA3,
+static const uint64_t P9N2_EX_5_L2_TOD_SYNC111 = 0x2B010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 2A010AA3,
+static const uint64_t P9N2_EX_6_L2_TOD_SYNC111 = 0x2D010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 2C010AA3,
+static const uint64_t P9N2_EX_7_L2_TOD_SYNC111 = 0x2F010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 2E010AA3,
+static const uint64_t P9N2_EX_8_L2_TOD_SYNC111 = 0x30010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 30010AA3,
+static const uint64_t P9N2_EX_9_L2_TOD_SYNC111 = 0x32010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 32010AA3,
+static const uint64_t P9N2_EX_L2_TOD_SYNC111 = 0x20010AA3ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 20010AA3,
+
+static const uint64_t P9N2_C_TRACE_HI_DATA_REG = 0x20011400ull;
+//DUPS: 20011440, 20011400,
+static const uint64_t P9N2_C_0_TRACE_HI_DATA_REG = 0x20011400ull;
+//DUPS: 20011440, 20011400,
+static const uint64_t P9N2_C_1_TRACE_HI_DATA_REG = 0x21011400ull;
+//DUPS: 21011440, 21011400,
+static const uint64_t P9N2_C_2_TRACE_HI_DATA_REG = 0x22011400ull;
+//DUPS: 22011440, 22011400,
+static const uint64_t P9N2_C_3_TRACE_HI_DATA_REG = 0x23011400ull;
+//DUPS: 23011440, 23011400,
+static const uint64_t P9N2_C_4_TRACE_HI_DATA_REG = 0x24011400ull;
+//DUPS: 24011440, 24011400,
+static const uint64_t P9N2_C_5_TRACE_HI_DATA_REG = 0x25011400ull;
+//DUPS: 25011440, 25011400,
+static const uint64_t P9N2_C_6_TRACE_HI_DATA_REG = 0x26011400ull;
+//DUPS: 26011440, 26011400,
+static const uint64_t P9N2_C_7_TRACE_HI_DATA_REG = 0x27011400ull;
+//DUPS: 27011440, 27011400,
+static const uint64_t P9N2_C_8_TRACE_HI_DATA_REG = 0x28011400ull;
+//DUPS: 28011440, 28011400,
+static const uint64_t P9N2_C_9_TRACE_HI_DATA_REG = 0x29011400ull;
+//DUPS: 29011440, 29011400,
+static const uint64_t P9N2_C_10_TRACE_HI_DATA_REG = 0x2A011480ull;
+//DUPS: 2A011440, 2A011400,
+static const uint64_t P9N2_C_11_TRACE_HI_DATA_REG = 0x2B011480ull;
+//DUPS: 2B011440, 2B011400,
+static const uint64_t P9N2_C_12_TRACE_HI_DATA_REG = 0x2C011480ull;
+//DUPS: 2C011440, 2C011400,
+static const uint64_t P9N2_C_13_TRACE_HI_DATA_REG = 0x2D011480ull;
+//DUPS: 2D011440, 2D011400,
+static const uint64_t P9N2_C_14_TRACE_HI_DATA_REG = 0x2E011480ull;
+//DUPS: 2E011440, 2E011400,
+static const uint64_t P9N2_C_15_TRACE_HI_DATA_REG = 0x2F011480ull;
+//DUPS: 2F011440, 2F011400,
+static const uint64_t P9N2_C_16_TRACE_HI_DATA_REG = 0x30011400ull;
+//DUPS: 30011440, 30011400,
+static const uint64_t P9N2_C_17_TRACE_HI_DATA_REG = 0x31011400ull;
+//DUPS: 31011440, 31011400,
+static const uint64_t P9N2_C_18_TRACE_HI_DATA_REG = 0x32011400ull;
+//DUPS: 32011440, 32011400,
+static const uint64_t P9N2_C_19_TRACE_HI_DATA_REG = 0x33011400ull;
+//DUPS: 33011440, 33011400,
+static const uint64_t P9N2_C_20_TRACE_HI_DATA_REG = 0x34011400ull;
+//DUPS: 34011440, 34011400,
+static const uint64_t P9N2_C_21_TRACE_HI_DATA_REG = 0x35011400ull;
+//DUPS: 35011440, 35011400,
+static const uint64_t P9N2_C_22_TRACE_HI_DATA_REG = 0x36011400ull;
+//DUPS: 36011440, 36011400,
+static const uint64_t P9N2_C_23_TRACE_HI_DATA_REG = 0x37011400ull;
+//DUPS: 37011440, 37011400,
+static const uint64_t P9N2_EQ_TRACE_HI_DATA_REG = 0x10012D40ull;
+//DUPS: 10010400, 100104C0, 10010480, 10012940, 10012900, 10012D40, 10012D00,
+static const uint64_t P9N2_EQ_0_TRACE_HI_DATA_REG = 0x10012D40ull;
+//DUPS: 10010400, 100104C0, 10010480, 10012940, 10012900, 10012D40, 10012D00,
+static const uint64_t P9N2_EQ_1_TRACE_HI_DATA_REG = 0x11012D40ull;
+//DUPS: 11010400, 110104C0, 11010480, 11012940, 11012900, 11012D40, 11012D00,
+static const uint64_t P9N2_EQ_2_TRACE_HI_DATA_REG = 0x12012D40ull;
+//DUPS: 12010400, 120104C0, 12010480, 12012940, 12012900, 12012D40, 12012D00,
+static const uint64_t P9N2_EQ_3_TRACE_HI_DATA_REG = 0x13012D40ull;
+//DUPS: 13010400, 130104C0, 13010480, 13012940, 13012900, 13012D40, 13012D00,
+static const uint64_t P9N2_EQ_4_TRACE_HI_DATA_REG = 0x14012D40ull;
+//DUPS: 14010400, 140104C0, 14010480, 14012940, 14012900, 14012D40, 14012D00,
+static const uint64_t P9N2_EQ_5_TRACE_HI_DATA_REG = 0x15012D40ull;
+//DUPS: 15010400, 150104C0, 15010480, 15012940, 15012900, 15012D40, 15012D00,
+static const uint64_t P9N2_EX_TRACE_HI_DATA_REG = 0x10012900ull;
+//DUPS: 10012900, 20011480, 20011440, 20011400, 21011480, 21011440, 21011400,
+static const uint64_t P9N2_EX_0_TRACE_HI_DATA_REG = 0x10012900ull;
+//DUPS: 10012900, 20011480, 20011440, 20011400, 21011480, 21011440, 21011400,
+static const uint64_t P9N2_EX_1_TRACE_HI_DATA_REG = 0x10012D40ull;
+//DUPS: 10012D00, 22011480, 22011440, 22011400, 23011480, 23011440, 23011400,
+static const uint64_t P9N2_EX_2_TRACE_HI_DATA_REG = 0x11012900ull;
+//DUPS: 11012900, 24011480, 24011440, 24011400, 25011480, 25011440, 25011400,
+static const uint64_t P9N2_EX_3_TRACE_HI_DATA_REG = 0x11012D40ull;
+//DUPS: 11012D00, 26011480, 26011440, 26011400, 27011480, 27011440, 27011400,
+static const uint64_t P9N2_EX_4_TRACE_HI_DATA_REG = 0x12012900ull;
+//DUPS: 12012900, 28011480, 28011440, 28011400, 29011480, 29011440, 29011400,
+static const uint64_t P9N2_EX_5_TRACE_HI_DATA_REG = 0x2A011480ull;
+//DUPS: 12012D00, 2A011480, 2A011440, 2A011400, 2B011480, 2B011440, 2B011400,
+static const uint64_t P9N2_EX_6_TRACE_HI_DATA_REG = 0x2C011480ull;
+//DUPS: 13012900, 2C011480, 2C011440, 2C011400, 2D011480, 2D011440, 2D011400,
+static const uint64_t P9N2_EX_7_TRACE_HI_DATA_REG = 0x2F011480ull;
+//DUPS: 13012D00, 2E011480, 2E011440, 2E011400, 2F011480, 2F011440, 2F011400,
+static const uint64_t P9N2_EX_8_TRACE_HI_DATA_REG = 0x14012900ull;
+//DUPS: 14012900, 30011480, 30011440, 30011400, 31011480, 31011440, 31011400,
+static const uint64_t P9N2_EX_9_TRACE_HI_DATA_REG = 0x14012D40ull;
+//DUPS: 14012D00, 32011480, 32011440, 32011400, 33011480, 33011440, 33011400,
+static const uint64_t P9N2_EX_10_TRACE_HI_DATA_REG = 0x15012900ull;
+//DUPS: 15012900, 34011480, 34011440, 34011400, 35011480, 35011440, 35011400,
+static const uint64_t P9N2_EX_11_TRACE_HI_DATA_REG = 0x15012D40ull;
+//DUPS: 15012D00, 36011480, 36011440, 36011400, 37011480, 37011440, 37011400,
+
+static const uint64_t P9N2_C_TRACE_LO_DATA_REG = 0x20011401ull;
+//DUPS: 20011441, 20011401,
+static const uint64_t P9N2_C_0_TRACE_LO_DATA_REG = 0x20011401ull;
+//DUPS: 20011441, 20011401,
+static const uint64_t P9N2_C_1_TRACE_LO_DATA_REG = 0x21011401ull;
+//DUPS: 21011441, 21011401,
+static const uint64_t P9N2_C_2_TRACE_LO_DATA_REG = 0x22011401ull;
+//DUPS: 22011441, 22011401,
+static const uint64_t P9N2_C_3_TRACE_LO_DATA_REG = 0x23011401ull;
+//DUPS: 23011441, 23011401,
+static const uint64_t P9N2_C_4_TRACE_LO_DATA_REG = 0x24011401ull;
+//DUPS: 24011441, 24011401,
+static const uint64_t P9N2_C_5_TRACE_LO_DATA_REG = 0x25011401ull;
+//DUPS: 25011441, 25011401,
+static const uint64_t P9N2_C_6_TRACE_LO_DATA_REG = 0x26011401ull;
+//DUPS: 26011441, 26011401,
+static const uint64_t P9N2_C_7_TRACE_LO_DATA_REG = 0x27011401ull;
+//DUPS: 27011441, 27011401,
+static const uint64_t P9N2_C_8_TRACE_LO_DATA_REG = 0x28011401ull;
+//DUPS: 28011441, 28011401,
+static const uint64_t P9N2_C_9_TRACE_LO_DATA_REG = 0x29011401ull;
+//DUPS: 29011441, 29011401,
+static const uint64_t P9N2_C_10_TRACE_LO_DATA_REG = 0x2A011481ull;
+//DUPS: 2A011441, 2A011401,
+static const uint64_t P9N2_C_11_TRACE_LO_DATA_REG = 0x2B011481ull;
+//DUPS: 2B011441, 2B011401,
+static const uint64_t P9N2_C_12_TRACE_LO_DATA_REG = 0x2C011481ull;
+//DUPS: 2C011441, 2C011401,
+static const uint64_t P9N2_C_13_TRACE_LO_DATA_REG = 0x2D011481ull;
+//DUPS: 2D011441, 2D011401,
+static const uint64_t P9N2_C_14_TRACE_LO_DATA_REG = 0x2E011481ull;
+//DUPS: 2E011441, 2E011401,
+static const uint64_t P9N2_C_15_TRACE_LO_DATA_REG = 0x2F011481ull;
+//DUPS: 2F011441, 2F011401,
+static const uint64_t P9N2_C_16_TRACE_LO_DATA_REG = 0x30011401ull;
+//DUPS: 30011441, 30011401,
+static const uint64_t P9N2_C_17_TRACE_LO_DATA_REG = 0x31011401ull;
+//DUPS: 31011441, 31011401,
+static const uint64_t P9N2_C_18_TRACE_LO_DATA_REG = 0x32011401ull;
+//DUPS: 32011441, 32011401,
+static const uint64_t P9N2_C_19_TRACE_LO_DATA_REG = 0x33011401ull;
+//DUPS: 33011441, 33011401,
+static const uint64_t P9N2_C_20_TRACE_LO_DATA_REG = 0x34011401ull;
+//DUPS: 34011441, 34011401,
+static const uint64_t P9N2_C_21_TRACE_LO_DATA_REG = 0x35011401ull;
+//DUPS: 35011441, 35011401,
+static const uint64_t P9N2_C_22_TRACE_LO_DATA_REG = 0x36011401ull;
+//DUPS: 36011441, 36011401,
+static const uint64_t P9N2_C_23_TRACE_LO_DATA_REG = 0x37011401ull;
+//DUPS: 37011441, 37011401,
+static const uint64_t P9N2_EQ_TRACE_LO_DATA_REG = 0x10012D41ull;
+//DUPS: 10010401, 100104C1, 10010481, 10012941, 10012901, 10012D41, 10012D01,
+static const uint64_t P9N2_EQ_0_TRACE_LO_DATA_REG = 0x10012D41ull;
+//DUPS: 10010401, 100104C1, 10010481, 10012941, 10012901, 10012D41, 10012D01,
+static const uint64_t P9N2_EQ_1_TRACE_LO_DATA_REG = 0x11012D41ull;
+//DUPS: 11010401, 110104C1, 11010481, 11012941, 11012901, 11012D41, 11012D01,
+static const uint64_t P9N2_EQ_2_TRACE_LO_DATA_REG = 0x12012D41ull;
+//DUPS: 12010401, 120104C1, 12010481, 12012941, 12012901, 12012D41, 12012D01,
+static const uint64_t P9N2_EQ_3_TRACE_LO_DATA_REG = 0x13012D41ull;
+//DUPS: 13010401, 130104C1, 13010481, 13012941, 13012901, 13012D41, 13012D01,
+static const uint64_t P9N2_EQ_4_TRACE_LO_DATA_REG = 0x14012D41ull;
+//DUPS: 14010401, 140104C1, 14010481, 14012941, 14012901, 14012D41, 14012D01,
+static const uint64_t P9N2_EQ_5_TRACE_LO_DATA_REG = 0x15012D41ull;
+//DUPS: 15010401, 150104C1, 15010481, 15012941, 15012901, 15012D41, 15012D01,
+static const uint64_t P9N2_EX_TRACE_LO_DATA_REG = 0x10012901ull;
+//DUPS: 10012901, 20011481, 20011441, 20011401, 21011481, 21011441, 21011401,
+static const uint64_t P9N2_EX_0_TRACE_LO_DATA_REG = 0x10012901ull;
+//DUPS: 10012901, 20011481, 20011441, 20011401, 21011481, 21011441, 21011401,
+static const uint64_t P9N2_EX_1_TRACE_LO_DATA_REG = 0x10012D41ull;
+//DUPS: 10012D01, 22011481, 22011441, 22011401, 23011481, 23011441, 23011401,
+static const uint64_t P9N2_EX_2_TRACE_LO_DATA_REG = 0x11012901ull;
+//DUPS: 11012901, 24011481, 24011441, 24011401, 25011481, 25011441, 25011401,
+static const uint64_t P9N2_EX_3_TRACE_LO_DATA_REG = 0x11012D41ull;
+//DUPS: 11012D01, 26011481, 26011441, 26011401, 27011481, 27011441, 27011401,
+static const uint64_t P9N2_EX_4_TRACE_LO_DATA_REG = 0x12012901ull;
+//DUPS: 12012901, 28011481, 28011441, 28011401, 29011481, 29011441, 29011401,
+static const uint64_t P9N2_EX_5_TRACE_LO_DATA_REG = 0x2A011481ull;
+//DUPS: 12012D01, 2A011481, 2A011441, 2A011401, 2B011481, 2B011441, 2B011401,
+static const uint64_t P9N2_EX_6_TRACE_LO_DATA_REG = 0x2C011481ull;
+//DUPS: 13012901, 2C011481, 2C011441, 2C011401, 2D011481, 2D011441, 2D011401,
+static const uint64_t P9N2_EX_7_TRACE_LO_DATA_REG = 0x2F011481ull;
+//DUPS: 13012D01, 2E011481, 2E011441, 2E011401, 2F011481, 2F011441, 2F011401,
+static const uint64_t P9N2_EX_8_TRACE_LO_DATA_REG = 0x14012901ull;
+//DUPS: 14012901, 30011481, 30011441, 30011401, 31011481, 31011441, 31011401,
+static const uint64_t P9N2_EX_9_TRACE_LO_DATA_REG = 0x14012D41ull;
+//DUPS: 14012D01, 32011481, 32011441, 32011401, 33011481, 33011441, 33011401,
+static const uint64_t P9N2_EX_10_TRACE_LO_DATA_REG = 0x15012901ull;
+//DUPS: 15012901, 34011481, 34011441, 34011401, 35011481, 35011441, 35011401,
+static const uint64_t P9N2_EX_11_TRACE_LO_DATA_REG = 0x15012D41ull;
+//DUPS: 15012D01, 36011481, 36011441, 36011401, 37011481, 37011441, 37011401,
+
+static const uint64_t P9N2_C_TRACE_TRCTRL_CONFIG = 0x20011402ull;
+//DUPS: 20011442, 20011402,
+static const uint64_t P9N2_C_0_TRACE_TRCTRL_CONFIG = 0x20011402ull;
+//DUPS: 20011442, 20011402,
+static const uint64_t P9N2_C_1_TRACE_TRCTRL_CONFIG = 0x21011402ull;
+//DUPS: 21011442, 21011402,
+static const uint64_t P9N2_C_2_TRACE_TRCTRL_CONFIG = 0x22011402ull;
+//DUPS: 22011442, 22011402,
+static const uint64_t P9N2_C_3_TRACE_TRCTRL_CONFIG = 0x23011402ull;
+//DUPS: 23011442, 23011402,
+static const uint64_t P9N2_C_4_TRACE_TRCTRL_CONFIG = 0x24011402ull;
+//DUPS: 24011442, 24011402,
+static const uint64_t P9N2_C_5_TRACE_TRCTRL_CONFIG = 0x25011402ull;
+//DUPS: 25011442, 25011402,
+static const uint64_t P9N2_C_6_TRACE_TRCTRL_CONFIG = 0x26011402ull;
+//DUPS: 26011442, 26011402,
+static const uint64_t P9N2_C_7_TRACE_TRCTRL_CONFIG = 0x27011402ull;
+//DUPS: 27011442, 27011402,
+static const uint64_t P9N2_C_8_TRACE_TRCTRL_CONFIG = 0x28011402ull;
+//DUPS: 28011442, 28011402,
+static const uint64_t P9N2_C_9_TRACE_TRCTRL_CONFIG = 0x29011402ull;
+//DUPS: 29011442, 29011402,
+static const uint64_t P9N2_C_10_TRACE_TRCTRL_CONFIG = 0x2A011482ull;
+//DUPS: 2A011442, 2A011402,
+static const uint64_t P9N2_C_11_TRACE_TRCTRL_CONFIG = 0x2B011482ull;
+//DUPS: 2B011442, 2B011402,
+static const uint64_t P9N2_C_12_TRACE_TRCTRL_CONFIG = 0x2C011482ull;
+//DUPS: 2C011442, 2C011402,
+static const uint64_t P9N2_C_13_TRACE_TRCTRL_CONFIG = 0x2D011482ull;
+//DUPS: 2D011442, 2D011402,
+static const uint64_t P9N2_C_14_TRACE_TRCTRL_CONFIG = 0x2E011482ull;
+//DUPS: 2E011442, 2E011402,
+static const uint64_t P9N2_C_15_TRACE_TRCTRL_CONFIG = 0x2F011482ull;
+//DUPS: 2F011442, 2F011402,
+static const uint64_t P9N2_C_16_TRACE_TRCTRL_CONFIG = 0x30011402ull;
+//DUPS: 30011442, 30011402,
+static const uint64_t P9N2_C_17_TRACE_TRCTRL_CONFIG = 0x31011402ull;
+//DUPS: 31011442, 31011402,
+static const uint64_t P9N2_C_18_TRACE_TRCTRL_CONFIG = 0x32011402ull;
+//DUPS: 32011442, 32011402,
+static const uint64_t P9N2_C_19_TRACE_TRCTRL_CONFIG = 0x33011402ull;
+//DUPS: 33011442, 33011402,
+static const uint64_t P9N2_C_20_TRACE_TRCTRL_CONFIG = 0x34011402ull;
+//DUPS: 34011442, 34011402,
+static const uint64_t P9N2_C_21_TRACE_TRCTRL_CONFIG = 0x35011402ull;
+//DUPS: 35011442, 35011402,
+static const uint64_t P9N2_C_22_TRACE_TRCTRL_CONFIG = 0x36011402ull;
+//DUPS: 36011442, 36011402,
+static const uint64_t P9N2_C_23_TRACE_TRCTRL_CONFIG = 0x37011402ull;
+//DUPS: 37011442, 37011402,
+static const uint64_t P9N2_EQ_TRACE_TRCTRL_CONFIG = 0x10012D42ull;
+//DUPS: 10010402, 100104C2, 10010482, 10012942, 10012902, 10012D42, 10012D02,
+static const uint64_t P9N2_EQ_0_TRACE_TRCTRL_CONFIG = 0x10012D42ull;
+//DUPS: 10010402, 100104C2, 10010482, 10012942, 10012902, 10012D42, 10012D02,
+static const uint64_t P9N2_EQ_1_TRACE_TRCTRL_CONFIG = 0x11012D42ull;
+//DUPS: 11010402, 110104C2, 11010482, 11012942, 11012902, 11012D42, 11012D02,
+static const uint64_t P9N2_EQ_2_TRACE_TRCTRL_CONFIG = 0x12012D42ull;
+//DUPS: 12010402, 120104C2, 12010482, 12012942, 12012902, 12012D42, 12012D02,
+static const uint64_t P9N2_EQ_3_TRACE_TRCTRL_CONFIG = 0x13012D42ull;
+//DUPS: 13010402, 130104C2, 13010482, 13012942, 13012902, 13012D42, 13012D02,
+static const uint64_t P9N2_EQ_4_TRACE_TRCTRL_CONFIG = 0x14012D42ull;
+//DUPS: 14010402, 140104C2, 14010482, 14012942, 14012902, 14012D42, 14012D02,
+static const uint64_t P9N2_EQ_5_TRACE_TRCTRL_CONFIG = 0x15012D42ull;
+//DUPS: 15010402, 150104C2, 15010482, 15012942, 15012902, 15012D42, 15012D02,
+static const uint64_t P9N2_EX_TRACE_TRCTRL_CONFIG = 0x10012902ull;
+//DUPS: 10012902, 20011482, 20011442, 20011402, 21011482, 21011442, 21011402,
+static const uint64_t P9N2_EX_0_TRACE_TRCTRL_CONFIG = 0x10012902ull;
+//DUPS: 10012902, 20011482, 20011442, 20011402, 21011482, 21011442, 21011402,
+static const uint64_t P9N2_EX_1_TRACE_TRCTRL_CONFIG = 0x10012D42ull;
+//DUPS: 10012D02, 22011482, 22011442, 22011402, 23011482, 23011442, 23011402,
+static const uint64_t P9N2_EX_2_TRACE_TRCTRL_CONFIG = 0x11012902ull;
+//DUPS: 11012902, 24011482, 24011442, 24011402, 25011482, 25011442, 25011402,
+static const uint64_t P9N2_EX_3_TRACE_TRCTRL_CONFIG = 0x11012D42ull;
+//DUPS: 11012D02, 26011482, 26011442, 26011402, 27011482, 27011442, 27011402,
+static const uint64_t P9N2_EX_4_TRACE_TRCTRL_CONFIG = 0x12012902ull;
+//DUPS: 12012902, 28011482, 28011442, 28011402, 29011482, 29011442, 29011402,
+static const uint64_t P9N2_EX_5_TRACE_TRCTRL_CONFIG = 0x2A011482ull;
+//DUPS: 12012D02, 2A011482, 2A011442, 2A011402, 2B011482, 2B011442, 2B011402,
+static const uint64_t P9N2_EX_6_TRACE_TRCTRL_CONFIG = 0x2C011482ull;
+//DUPS: 13012902, 2C011482, 2C011442, 2C011402, 2D011482, 2D011442, 2D011402,
+static const uint64_t P9N2_EX_7_TRACE_TRCTRL_CONFIG = 0x2F011482ull;
+//DUPS: 13012D02, 2E011482, 2E011442, 2E011402, 2F011482, 2F011442, 2F011402,
+static const uint64_t P9N2_EX_8_TRACE_TRCTRL_CONFIG = 0x14012902ull;
+//DUPS: 14012902, 30011482, 30011442, 30011402, 31011482, 31011442, 31011402,
+static const uint64_t P9N2_EX_9_TRACE_TRCTRL_CONFIG = 0x14012D42ull;
+//DUPS: 14012D02, 32011482, 32011442, 32011402, 33011482, 33011442, 33011402,
+static const uint64_t P9N2_EX_10_TRACE_TRCTRL_CONFIG = 0x15012902ull;
+//DUPS: 15012902, 34011482, 34011442, 34011402, 35011482, 35011442, 35011402,
+static const uint64_t P9N2_EX_11_TRACE_TRCTRL_CONFIG = 0x15012D42ull;
+//DUPS: 15012D02, 36011482, 36011442, 36011402, 37011482, 37011442, 37011402,
+
+static const uint64_t P9N2_C_TRACE_TRDATA_CONFIG_0 = 0x20011403ull;
+//DUPS: 20011443, 20011403,
+static const uint64_t P9N2_C_0_TRACE_TRDATA_CONFIG_0 = 0x20011403ull;
+//DUPS: 20011443, 20011403,
+static const uint64_t P9N2_C_1_TRACE_TRDATA_CONFIG_0 = 0x21011403ull;
+//DUPS: 21011443, 21011403,
+static const uint64_t P9N2_C_2_TRACE_TRDATA_CONFIG_0 = 0x22011403ull;
+//DUPS: 22011443, 22011403,
+static const uint64_t P9N2_C_3_TRACE_TRDATA_CONFIG_0 = 0x23011403ull;
+//DUPS: 23011443, 23011403,
+static const uint64_t P9N2_C_4_TRACE_TRDATA_CONFIG_0 = 0x24011403ull;
+//DUPS: 24011443, 24011403,
+static const uint64_t P9N2_C_5_TRACE_TRDATA_CONFIG_0 = 0x25011403ull;
+//DUPS: 25011443, 25011403,
+static const uint64_t P9N2_C_6_TRACE_TRDATA_CONFIG_0 = 0x26011403ull;
+//DUPS: 26011443, 26011403,
+static const uint64_t P9N2_C_7_TRACE_TRDATA_CONFIG_0 = 0x27011403ull;
+//DUPS: 27011443, 27011403,
+static const uint64_t P9N2_C_8_TRACE_TRDATA_CONFIG_0 = 0x28011403ull;
+//DUPS: 28011443, 28011403,
+static const uint64_t P9N2_C_9_TRACE_TRDATA_CONFIG_0 = 0x29011403ull;
+//DUPS: 29011443, 29011403,
+static const uint64_t P9N2_C_10_TRACE_TRDATA_CONFIG_0 = 0x2A011483ull;
+//DUPS: 2A011443, 2A011403,
+static const uint64_t P9N2_C_11_TRACE_TRDATA_CONFIG_0 = 0x2B011483ull;
+//DUPS: 2B011443, 2B011403,
+static const uint64_t P9N2_C_12_TRACE_TRDATA_CONFIG_0 = 0x2C011483ull;
+//DUPS: 2C011443, 2C011403,
+static const uint64_t P9N2_C_13_TRACE_TRDATA_CONFIG_0 = 0x2D011483ull;
+//DUPS: 2D011443, 2D011403,
+static const uint64_t P9N2_C_14_TRACE_TRDATA_CONFIG_0 = 0x2E011483ull;
+//DUPS: 2E011443, 2E011403,
+static const uint64_t P9N2_C_15_TRACE_TRDATA_CONFIG_0 = 0x2F011483ull;
+//DUPS: 2F011443, 2F011403,
+static const uint64_t P9N2_C_16_TRACE_TRDATA_CONFIG_0 = 0x30011403ull;
+//DUPS: 30011443, 30011403,
+static const uint64_t P9N2_C_17_TRACE_TRDATA_CONFIG_0 = 0x31011403ull;
+//DUPS: 31011443, 31011403,
+static const uint64_t P9N2_C_18_TRACE_TRDATA_CONFIG_0 = 0x32011403ull;
+//DUPS: 32011443, 32011403,
+static const uint64_t P9N2_C_19_TRACE_TRDATA_CONFIG_0 = 0x33011403ull;
+//DUPS: 33011443, 33011403,
+static const uint64_t P9N2_C_20_TRACE_TRDATA_CONFIG_0 = 0x34011403ull;
+//DUPS: 34011443, 34011403,
+static const uint64_t P9N2_C_21_TRACE_TRDATA_CONFIG_0 = 0x35011403ull;
+//DUPS: 35011443, 35011403,
+static const uint64_t P9N2_C_22_TRACE_TRDATA_CONFIG_0 = 0x36011403ull;
+//DUPS: 36011443, 36011403,
+static const uint64_t P9N2_C_23_TRACE_TRDATA_CONFIG_0 = 0x37011403ull;
+//DUPS: 37011443, 37011403,
+static const uint64_t P9N2_EQ_TRACE_TRDATA_CONFIG_0 = 0x10012D43ull;
+//DUPS: 10010403, 100104C3, 10010483, 10012943, 10012903, 10012D43, 10012D03,
+static const uint64_t P9N2_EQ_0_TRACE_TRDATA_CONFIG_0 = 0x10012D43ull;
+//DUPS: 10010403, 100104C3, 10010483, 10012943, 10012903, 10012D43, 10012D03,
+static const uint64_t P9N2_EQ_1_TRACE_TRDATA_CONFIG_0 = 0x11012D43ull;
+//DUPS: 11010403, 110104C3, 11010483, 11012943, 11012903, 11012D43, 11012D03,
+static const uint64_t P9N2_EQ_2_TRACE_TRDATA_CONFIG_0 = 0x12012D43ull;
+//DUPS: 12010403, 120104C3, 12010483, 12012943, 12012903, 12012D43, 12012D03,
+static const uint64_t P9N2_EQ_3_TRACE_TRDATA_CONFIG_0 = 0x13012D43ull;
+//DUPS: 13010403, 130104C3, 13010483, 13012943, 13012903, 13012D43, 13012D03,
+static const uint64_t P9N2_EQ_4_TRACE_TRDATA_CONFIG_0 = 0x14012D43ull;
+//DUPS: 14010403, 140104C3, 14010483, 14012943, 14012903, 14012D43, 14012D03,
+static const uint64_t P9N2_EQ_5_TRACE_TRDATA_CONFIG_0 = 0x15012D43ull;
+//DUPS: 15010403, 150104C3, 15010483, 15012943, 15012903, 15012D43, 15012D03,
+static const uint64_t P9N2_EX_TRACE_TRDATA_CONFIG_0 = 0x10012903ull;
+//DUPS: 10012903, 20011483, 20011443, 20011403, 21011483, 21011443, 21011403,
+static const uint64_t P9N2_EX_0_TRACE_TRDATA_CONFIG_0 = 0x10012903ull;
+//DUPS: 10012903, 20011483, 20011443, 20011403, 21011483, 21011443, 21011403,
+static const uint64_t P9N2_EX_1_TRACE_TRDATA_CONFIG_0 = 0x10012D43ull;
+//DUPS: 10012D03, 22011483, 22011443, 22011403, 23011483, 23011443, 23011403,
+static const uint64_t P9N2_EX_2_TRACE_TRDATA_CONFIG_0 = 0x11012903ull;
+//DUPS: 11012903, 24011483, 24011443, 24011403, 25011483, 25011443, 25011403,
+static const uint64_t P9N2_EX_3_TRACE_TRDATA_CONFIG_0 = 0x11012D43ull;
+//DUPS: 11012D03, 26011483, 26011443, 26011403, 27011483, 27011443, 27011403,
+static const uint64_t P9N2_EX_4_TRACE_TRDATA_CONFIG_0 = 0x12012903ull;
+//DUPS: 12012903, 28011483, 28011443, 28011403, 29011483, 29011443, 29011403,
+static const uint64_t P9N2_EX_5_TRACE_TRDATA_CONFIG_0 = 0x2A011483ull;
+//DUPS: 12012D03, 2A011483, 2A011443, 2A011403, 2B011483, 2B011443, 2B011403,
+static const uint64_t P9N2_EX_6_TRACE_TRDATA_CONFIG_0 = 0x2C011483ull;
+//DUPS: 13012903, 2C011483, 2C011443, 2C011403, 2D011483, 2D011443, 2D011403,
+static const uint64_t P9N2_EX_7_TRACE_TRDATA_CONFIG_0 = 0x2F011483ull;
+//DUPS: 13012D03, 2E011483, 2E011443, 2E011403, 2F011483, 2F011443, 2F011403,
+static const uint64_t P9N2_EX_8_TRACE_TRDATA_CONFIG_0 = 0x14012903ull;
+//DUPS: 14012903, 30011483, 30011443, 30011403, 31011483, 31011443, 31011403,
+static const uint64_t P9N2_EX_9_TRACE_TRDATA_CONFIG_0 = 0x14012D43ull;
+//DUPS: 14012D03, 32011483, 32011443, 32011403, 33011483, 33011443, 33011403,
+static const uint64_t P9N2_EX_10_TRACE_TRDATA_CONFIG_0 = 0x15012903ull;
+//DUPS: 15012903, 34011483, 34011443, 34011403, 35011483, 35011443, 35011403,
+static const uint64_t P9N2_EX_11_TRACE_TRDATA_CONFIG_0 = 0x15012D43ull;
+//DUPS: 15012D03, 36011483, 36011443, 36011403, 37011483, 37011443, 37011403,
+
+static const uint64_t P9N2_C_TRACE_TRDATA_CONFIG_1 = 0x20011404ull;
+//DUPS: 20011444, 20011404,
+static const uint64_t P9N2_C_0_TRACE_TRDATA_CONFIG_1 = 0x20011404ull;
+//DUPS: 20011444, 20011404,
+static const uint64_t P9N2_C_1_TRACE_TRDATA_CONFIG_1 = 0x21011404ull;
+//DUPS: 21011444, 21011404,
+static const uint64_t P9N2_C_2_TRACE_TRDATA_CONFIG_1 = 0x22011404ull;
+//DUPS: 22011444, 22011404,
+static const uint64_t P9N2_C_3_TRACE_TRDATA_CONFIG_1 = 0x23011404ull;
+//DUPS: 23011444, 23011404,
+static const uint64_t P9N2_C_4_TRACE_TRDATA_CONFIG_1 = 0x24011404ull;
+//DUPS: 24011444, 24011404,
+static const uint64_t P9N2_C_5_TRACE_TRDATA_CONFIG_1 = 0x25011404ull;
+//DUPS: 25011444, 25011404,
+static const uint64_t P9N2_C_6_TRACE_TRDATA_CONFIG_1 = 0x26011404ull;
+//DUPS: 26011444, 26011404,
+static const uint64_t P9N2_C_7_TRACE_TRDATA_CONFIG_1 = 0x27011404ull;
+//DUPS: 27011444, 27011404,
+static const uint64_t P9N2_C_8_TRACE_TRDATA_CONFIG_1 = 0x28011404ull;
+//DUPS: 28011444, 28011404,
+static const uint64_t P9N2_C_9_TRACE_TRDATA_CONFIG_1 = 0x29011404ull;
+//DUPS: 29011444, 29011404,
+static const uint64_t P9N2_C_10_TRACE_TRDATA_CONFIG_1 = 0x2A011484ull;
+//DUPS: 2A011444, 2A011404,
+static const uint64_t P9N2_C_11_TRACE_TRDATA_CONFIG_1 = 0x2B011484ull;
+//DUPS: 2B011444, 2B011404,
+static const uint64_t P9N2_C_12_TRACE_TRDATA_CONFIG_1 = 0x2C011484ull;
+//DUPS: 2C011444, 2C011404,
+static const uint64_t P9N2_C_13_TRACE_TRDATA_CONFIG_1 = 0x2D011484ull;
+//DUPS: 2D011444, 2D011404,
+static const uint64_t P9N2_C_14_TRACE_TRDATA_CONFIG_1 = 0x2E011484ull;
+//DUPS: 2E011444, 2E011404,
+static const uint64_t P9N2_C_15_TRACE_TRDATA_CONFIG_1 = 0x2F011484ull;
+//DUPS: 2F011444, 2F011404,
+static const uint64_t P9N2_C_16_TRACE_TRDATA_CONFIG_1 = 0x30011404ull;
+//DUPS: 30011444, 30011404,
+static const uint64_t P9N2_C_17_TRACE_TRDATA_CONFIG_1 = 0x31011404ull;
+//DUPS: 31011444, 31011404,
+static const uint64_t P9N2_C_18_TRACE_TRDATA_CONFIG_1 = 0x32011404ull;
+//DUPS: 32011444, 32011404,
+static const uint64_t P9N2_C_19_TRACE_TRDATA_CONFIG_1 = 0x33011404ull;
+//DUPS: 33011444, 33011404,
+static const uint64_t P9N2_C_20_TRACE_TRDATA_CONFIG_1 = 0x34011404ull;
+//DUPS: 34011444, 34011404,
+static const uint64_t P9N2_C_21_TRACE_TRDATA_CONFIG_1 = 0x35011404ull;
+//DUPS: 35011444, 35011404,
+static const uint64_t P9N2_C_22_TRACE_TRDATA_CONFIG_1 = 0x36011404ull;
+//DUPS: 36011444, 36011404,
+static const uint64_t P9N2_C_23_TRACE_TRDATA_CONFIG_1 = 0x37011404ull;
+//DUPS: 37011444, 37011404,
+static const uint64_t P9N2_EQ_TRACE_TRDATA_CONFIG_1 = 0x10012D44ull;
+//DUPS: 10010404, 100104C4, 10010484, 10012944, 10012904, 10012D44, 10012D04,
+static const uint64_t P9N2_EQ_0_TRACE_TRDATA_CONFIG_1 = 0x10012D44ull;
+//DUPS: 10010404, 100104C4, 10010484, 10012944, 10012904, 10012D44, 10012D04,
+static const uint64_t P9N2_EQ_1_TRACE_TRDATA_CONFIG_1 = 0x11012D44ull;
+//DUPS: 11010404, 110104C4, 11010484, 11012944, 11012904, 11012D44, 11012D04,
+static const uint64_t P9N2_EQ_2_TRACE_TRDATA_CONFIG_1 = 0x12012D44ull;
+//DUPS: 12010404, 120104C4, 12010484, 12012944, 12012904, 12012D44, 12012D04,
+static const uint64_t P9N2_EQ_3_TRACE_TRDATA_CONFIG_1 = 0x13012D44ull;
+//DUPS: 13010404, 130104C4, 13010484, 13012944, 13012904, 13012D44, 13012D04,
+static const uint64_t P9N2_EQ_4_TRACE_TRDATA_CONFIG_1 = 0x14012D44ull;
+//DUPS: 14010404, 140104C4, 14010484, 14012944, 14012904, 14012D44, 14012D04,
+static const uint64_t P9N2_EQ_5_TRACE_TRDATA_CONFIG_1 = 0x15012D44ull;
+//DUPS: 15010404, 150104C4, 15010484, 15012944, 15012904, 15012D44, 15012D04,
+static const uint64_t P9N2_EX_TRACE_TRDATA_CONFIG_1 = 0x10012904ull;
+//DUPS: 10012904, 20011484, 20011444, 20011404, 21011484, 21011444, 21011404,
+static const uint64_t P9N2_EX_0_TRACE_TRDATA_CONFIG_1 = 0x10012904ull;
+//DUPS: 10012904, 20011484, 20011444, 20011404, 21011484, 21011444, 21011404,
+static const uint64_t P9N2_EX_1_TRACE_TRDATA_CONFIG_1 = 0x10012D44ull;
+//DUPS: 10012D04, 22011484, 22011444, 22011404, 23011484, 23011444, 23011404,
+static const uint64_t P9N2_EX_2_TRACE_TRDATA_CONFIG_1 = 0x11012904ull;
+//DUPS: 11012904, 24011484, 24011444, 24011404, 25011484, 25011444, 25011404,
+static const uint64_t P9N2_EX_3_TRACE_TRDATA_CONFIG_1 = 0x11012D44ull;
+//DUPS: 11012D04, 26011484, 26011444, 26011404, 27011484, 27011444, 27011404,
+static const uint64_t P9N2_EX_4_TRACE_TRDATA_CONFIG_1 = 0x12012904ull;
+//DUPS: 12012904, 28011484, 28011444, 28011404, 29011484, 29011444, 29011404,
+static const uint64_t P9N2_EX_5_TRACE_TRDATA_CONFIG_1 = 0x2A011484ull;
+//DUPS: 12012D04, 2A011484, 2A011444, 2A011404, 2B011484, 2B011444, 2B011404,
+static const uint64_t P9N2_EX_6_TRACE_TRDATA_CONFIG_1 = 0x2C011484ull;
+//DUPS: 13012904, 2C011484, 2C011444, 2C011404, 2D011484, 2D011444, 2D011404,
+static const uint64_t P9N2_EX_7_TRACE_TRDATA_CONFIG_1 = 0x2F011484ull;
+//DUPS: 13012D04, 2E011484, 2E011444, 2E011404, 2F011484, 2F011444, 2F011404,
+static const uint64_t P9N2_EX_8_TRACE_TRDATA_CONFIG_1 = 0x14012904ull;
+//DUPS: 14012904, 30011484, 30011444, 30011404, 31011484, 31011444, 31011404,
+static const uint64_t P9N2_EX_9_TRACE_TRDATA_CONFIG_1 = 0x14012D44ull;
+//DUPS: 14012D04, 32011484, 32011444, 32011404, 33011484, 33011444, 33011404,
+static const uint64_t P9N2_EX_10_TRACE_TRDATA_CONFIG_1 = 0x15012904ull;
+//DUPS: 15012904, 34011484, 34011444, 34011404, 35011484, 35011444, 35011404,
+static const uint64_t P9N2_EX_11_TRACE_TRDATA_CONFIG_1 = 0x15012D44ull;
+//DUPS: 15012D04, 36011484, 36011444, 36011404, 37011484, 37011444, 37011404,
+
+static const uint64_t P9N2_C_TRACE_TRDATA_CONFIG_2 = 0x20011405ull;
+//DUPS: 20011445, 20011405,
+static const uint64_t P9N2_C_0_TRACE_TRDATA_CONFIG_2 = 0x20011405ull;
+//DUPS: 20011445, 20011405,
+static const uint64_t P9N2_C_1_TRACE_TRDATA_CONFIG_2 = 0x21011405ull;
+//DUPS: 21011445, 21011405,
+static const uint64_t P9N2_C_2_TRACE_TRDATA_CONFIG_2 = 0x22011405ull;
+//DUPS: 22011445, 22011405,
+static const uint64_t P9N2_C_3_TRACE_TRDATA_CONFIG_2 = 0x23011405ull;
+//DUPS: 23011445, 23011405,
+static const uint64_t P9N2_C_4_TRACE_TRDATA_CONFIG_2 = 0x24011405ull;
+//DUPS: 24011445, 24011405,
+static const uint64_t P9N2_C_5_TRACE_TRDATA_CONFIG_2 = 0x25011405ull;
+//DUPS: 25011445, 25011405,
+static const uint64_t P9N2_C_6_TRACE_TRDATA_CONFIG_2 = 0x26011405ull;
+//DUPS: 26011445, 26011405,
+static const uint64_t P9N2_C_7_TRACE_TRDATA_CONFIG_2 = 0x27011405ull;
+//DUPS: 27011445, 27011405,
+static const uint64_t P9N2_C_8_TRACE_TRDATA_CONFIG_2 = 0x28011405ull;
+//DUPS: 28011445, 28011405,
+static const uint64_t P9N2_C_9_TRACE_TRDATA_CONFIG_2 = 0x29011405ull;
+//DUPS: 29011445, 29011405,
+static const uint64_t P9N2_C_10_TRACE_TRDATA_CONFIG_2 = 0x2A011485ull;
+//DUPS: 2A011445, 2A011405,
+static const uint64_t P9N2_C_11_TRACE_TRDATA_CONFIG_2 = 0x2B011485ull;
+//DUPS: 2B011445, 2B011405,
+static const uint64_t P9N2_C_12_TRACE_TRDATA_CONFIG_2 = 0x2C011485ull;
+//DUPS: 2C011445, 2C011405,
+static const uint64_t P9N2_C_13_TRACE_TRDATA_CONFIG_2 = 0x2D011485ull;
+//DUPS: 2D011445, 2D011405,
+static const uint64_t P9N2_C_14_TRACE_TRDATA_CONFIG_2 = 0x2E011485ull;
+//DUPS: 2E011445, 2E011405,
+static const uint64_t P9N2_C_15_TRACE_TRDATA_CONFIG_2 = 0x2F011485ull;
+//DUPS: 2F011445, 2F011405,
+static const uint64_t P9N2_C_16_TRACE_TRDATA_CONFIG_2 = 0x30011405ull;
+//DUPS: 30011445, 30011405,
+static const uint64_t P9N2_C_17_TRACE_TRDATA_CONFIG_2 = 0x31011405ull;
+//DUPS: 31011445, 31011405,
+static const uint64_t P9N2_C_18_TRACE_TRDATA_CONFIG_2 = 0x32011405ull;
+//DUPS: 32011445, 32011405,
+static const uint64_t P9N2_C_19_TRACE_TRDATA_CONFIG_2 = 0x33011405ull;
+//DUPS: 33011445, 33011405,
+static const uint64_t P9N2_C_20_TRACE_TRDATA_CONFIG_2 = 0x34011405ull;
+//DUPS: 34011445, 34011405,
+static const uint64_t P9N2_C_21_TRACE_TRDATA_CONFIG_2 = 0x35011405ull;
+//DUPS: 35011445, 35011405,
+static const uint64_t P9N2_C_22_TRACE_TRDATA_CONFIG_2 = 0x36011405ull;
+//DUPS: 36011445, 36011405,
+static const uint64_t P9N2_C_23_TRACE_TRDATA_CONFIG_2 = 0x37011405ull;
+//DUPS: 37011445, 37011405,
+static const uint64_t P9N2_EQ_TRACE_TRDATA_CONFIG_2 = 0x10012D45ull;
+//DUPS: 10010405, 100104C5, 10010485, 10012945, 10012905, 10012D45, 10012D05,
+static const uint64_t P9N2_EQ_0_TRACE_TRDATA_CONFIG_2 = 0x10012D45ull;
+//DUPS: 10010405, 100104C5, 10010485, 10012945, 10012905, 10012D45, 10012D05,
+static const uint64_t P9N2_EQ_1_TRACE_TRDATA_CONFIG_2 = 0x11012D45ull;
+//DUPS: 11010405, 110104C5, 11010485, 11012945, 11012905, 11012D45, 11012D05,
+static const uint64_t P9N2_EQ_2_TRACE_TRDATA_CONFIG_2 = 0x12012D45ull;
+//DUPS: 12010405, 120104C5, 12010485, 12012945, 12012905, 12012D45, 12012D05,
+static const uint64_t P9N2_EQ_3_TRACE_TRDATA_CONFIG_2 = 0x13012D45ull;
+//DUPS: 13010405, 130104C5, 13010485, 13012945, 13012905, 13012D45, 13012D05,
+static const uint64_t P9N2_EQ_4_TRACE_TRDATA_CONFIG_2 = 0x14012D45ull;
+//DUPS: 14010405, 140104C5, 14010485, 14012945, 14012905, 14012D45, 14012D05,
+static const uint64_t P9N2_EQ_5_TRACE_TRDATA_CONFIG_2 = 0x15012D45ull;
+//DUPS: 15010405, 150104C5, 15010485, 15012945, 15012905, 15012D45, 15012D05,
+static const uint64_t P9N2_EX_TRACE_TRDATA_CONFIG_2 = 0x10012905ull;
+//DUPS: 10012905, 20011485, 20011445, 20011405, 21011485, 21011445, 21011405,
+static const uint64_t P9N2_EX_0_TRACE_TRDATA_CONFIG_2 = 0x10012905ull;
+//DUPS: 10012905, 20011485, 20011445, 20011405, 21011485, 21011445, 21011405,
+static const uint64_t P9N2_EX_1_TRACE_TRDATA_CONFIG_2 = 0x10012D45ull;
+//DUPS: 10012D05, 22011485, 22011445, 22011405, 23011485, 23011445, 23011405,
+static const uint64_t P9N2_EX_2_TRACE_TRDATA_CONFIG_2 = 0x11012905ull;
+//DUPS: 11012905, 24011485, 24011445, 24011405, 25011485, 25011445, 25011405,
+static const uint64_t P9N2_EX_3_TRACE_TRDATA_CONFIG_2 = 0x11012D45ull;
+//DUPS: 11012D05, 26011485, 26011445, 26011405, 27011485, 27011445, 27011405,
+static const uint64_t P9N2_EX_4_TRACE_TRDATA_CONFIG_2 = 0x12012905ull;
+//DUPS: 12012905, 28011485, 28011445, 28011405, 29011485, 29011445, 29011405,
+static const uint64_t P9N2_EX_5_TRACE_TRDATA_CONFIG_2 = 0x2A011485ull;
+//DUPS: 12012D05, 2A011485, 2A011445, 2A011405, 2B011485, 2B011445, 2B011405,
+static const uint64_t P9N2_EX_6_TRACE_TRDATA_CONFIG_2 = 0x2C011485ull;
+//DUPS: 13012905, 2C011485, 2C011445, 2C011405, 2D011485, 2D011445, 2D011405,
+static const uint64_t P9N2_EX_7_TRACE_TRDATA_CONFIG_2 = 0x2F011485ull;
+//DUPS: 13012D05, 2E011485, 2E011445, 2E011405, 2F011485, 2F011445, 2F011405,
+static const uint64_t P9N2_EX_8_TRACE_TRDATA_CONFIG_2 = 0x14012905ull;
+//DUPS: 14012905, 30011485, 30011445, 30011405, 31011485, 31011445, 31011405,
+static const uint64_t P9N2_EX_9_TRACE_TRDATA_CONFIG_2 = 0x14012D45ull;
+//DUPS: 14012D05, 32011485, 32011445, 32011405, 33011485, 33011445, 33011405,
+static const uint64_t P9N2_EX_10_TRACE_TRDATA_CONFIG_2 = 0x15012905ull;
+//DUPS: 15012905, 34011485, 34011445, 34011405, 35011485, 35011445, 35011405,
+static const uint64_t P9N2_EX_11_TRACE_TRDATA_CONFIG_2 = 0x15012D45ull;
+//DUPS: 15012D05, 36011485, 36011445, 36011405, 37011485, 37011445, 37011405,
+
+static const uint64_t P9N2_C_TRACE_TRDATA_CONFIG_3 = 0x20011406ull;
+//DUPS: 20011446, 20011406,
+static const uint64_t P9N2_C_0_TRACE_TRDATA_CONFIG_3 = 0x20011406ull;
+//DUPS: 20011446, 20011406,
+static const uint64_t P9N2_C_1_TRACE_TRDATA_CONFIG_3 = 0x21011406ull;
+//DUPS: 21011446, 21011406,
+static const uint64_t P9N2_C_2_TRACE_TRDATA_CONFIG_3 = 0x22011406ull;
+//DUPS: 22011446, 22011406,
+static const uint64_t P9N2_C_3_TRACE_TRDATA_CONFIG_3 = 0x23011406ull;
+//DUPS: 23011446, 23011406,
+static const uint64_t P9N2_C_4_TRACE_TRDATA_CONFIG_3 = 0x24011406ull;
+//DUPS: 24011446, 24011406,
+static const uint64_t P9N2_C_5_TRACE_TRDATA_CONFIG_3 = 0x25011406ull;
+//DUPS: 25011446, 25011406,
+static const uint64_t P9N2_C_6_TRACE_TRDATA_CONFIG_3 = 0x26011406ull;
+//DUPS: 26011446, 26011406,
+static const uint64_t P9N2_C_7_TRACE_TRDATA_CONFIG_3 = 0x27011406ull;
+//DUPS: 27011446, 27011406,
+static const uint64_t P9N2_C_8_TRACE_TRDATA_CONFIG_3 = 0x28011406ull;
+//DUPS: 28011446, 28011406,
+static const uint64_t P9N2_C_9_TRACE_TRDATA_CONFIG_3 = 0x29011406ull;
+//DUPS: 29011446, 29011406,
+static const uint64_t P9N2_C_10_TRACE_TRDATA_CONFIG_3 = 0x2A011486ull;
+//DUPS: 2A011446, 2A011406,
+static const uint64_t P9N2_C_11_TRACE_TRDATA_CONFIG_3 = 0x2B011486ull;
+//DUPS: 2B011446, 2B011406,
+static const uint64_t P9N2_C_12_TRACE_TRDATA_CONFIG_3 = 0x2C011486ull;
+//DUPS: 2C011446, 2C011406,
+static const uint64_t P9N2_C_13_TRACE_TRDATA_CONFIG_3 = 0x2D011486ull;
+//DUPS: 2D011446, 2D011406,
+static const uint64_t P9N2_C_14_TRACE_TRDATA_CONFIG_3 = 0x2E011486ull;
+//DUPS: 2E011446, 2E011406,
+static const uint64_t P9N2_C_15_TRACE_TRDATA_CONFIG_3 = 0x2F011486ull;
+//DUPS: 2F011446, 2F011406,
+static const uint64_t P9N2_C_16_TRACE_TRDATA_CONFIG_3 = 0x30011406ull;
+//DUPS: 30011446, 30011406,
+static const uint64_t P9N2_C_17_TRACE_TRDATA_CONFIG_3 = 0x31011406ull;
+//DUPS: 31011446, 31011406,
+static const uint64_t P9N2_C_18_TRACE_TRDATA_CONFIG_3 = 0x32011406ull;
+//DUPS: 32011446, 32011406,
+static const uint64_t P9N2_C_19_TRACE_TRDATA_CONFIG_3 = 0x33011406ull;
+//DUPS: 33011446, 33011406,
+static const uint64_t P9N2_C_20_TRACE_TRDATA_CONFIG_3 = 0x34011406ull;
+//DUPS: 34011446, 34011406,
+static const uint64_t P9N2_C_21_TRACE_TRDATA_CONFIG_3 = 0x35011406ull;
+//DUPS: 35011446, 35011406,
+static const uint64_t P9N2_C_22_TRACE_TRDATA_CONFIG_3 = 0x36011406ull;
+//DUPS: 36011446, 36011406,
+static const uint64_t P9N2_C_23_TRACE_TRDATA_CONFIG_3 = 0x37011406ull;
+//DUPS: 37011446, 37011406,
+static const uint64_t P9N2_EQ_TRACE_TRDATA_CONFIG_3 = 0x10012D46ull;
+//DUPS: 10010406, 100104C6, 10010486, 10012946, 10012906, 10012D46, 10012D06,
+static const uint64_t P9N2_EQ_0_TRACE_TRDATA_CONFIG_3 = 0x10012D46ull;
+//DUPS: 10010406, 100104C6, 10010486, 10012946, 10012906, 10012D46, 10012D06,
+static const uint64_t P9N2_EQ_1_TRACE_TRDATA_CONFIG_3 = 0x11012D46ull;
+//DUPS: 11010406, 110104C6, 11010486, 11012946, 11012906, 11012D46, 11012D06,
+static const uint64_t P9N2_EQ_2_TRACE_TRDATA_CONFIG_3 = 0x12012D46ull;
+//DUPS: 12010406, 120104C6, 12010486, 12012946, 12012906, 12012D46, 12012D06,
+static const uint64_t P9N2_EQ_3_TRACE_TRDATA_CONFIG_3 = 0x13012D46ull;
+//DUPS: 13010406, 130104C6, 13010486, 13012946, 13012906, 13012D46, 13012D06,
+static const uint64_t P9N2_EQ_4_TRACE_TRDATA_CONFIG_3 = 0x14012D46ull;
+//DUPS: 14010406, 140104C6, 14010486, 14012946, 14012906, 14012D46, 14012D06,
+static const uint64_t P9N2_EQ_5_TRACE_TRDATA_CONFIG_3 = 0x15012D46ull;
+//DUPS: 15010406, 150104C6, 15010486, 15012946, 15012906, 15012D46, 15012D06,
+static const uint64_t P9N2_EX_TRACE_TRDATA_CONFIG_3 = 0x10012906ull;
+//DUPS: 10012906, 20011486, 20011446, 20011406, 21011486, 21011446, 21011406,
+static const uint64_t P9N2_EX_0_TRACE_TRDATA_CONFIG_3 = 0x10012906ull;
+//DUPS: 10012906, 20011486, 20011446, 20011406, 21011486, 21011446, 21011406,
+static const uint64_t P9N2_EX_1_TRACE_TRDATA_CONFIG_3 = 0x10012D46ull;
+//DUPS: 10012D06, 22011486, 22011446, 22011406, 23011486, 23011446, 23011406,
+static const uint64_t P9N2_EX_2_TRACE_TRDATA_CONFIG_3 = 0x11012906ull;
+//DUPS: 11012906, 24011486, 24011446, 24011406, 25011486, 25011446, 25011406,
+static const uint64_t P9N2_EX_3_TRACE_TRDATA_CONFIG_3 = 0x11012D46ull;
+//DUPS: 11012D06, 26011486, 26011446, 26011406, 27011486, 27011446, 27011406,
+static const uint64_t P9N2_EX_4_TRACE_TRDATA_CONFIG_3 = 0x12012906ull;
+//DUPS: 12012906, 28011486, 28011446, 28011406, 29011486, 29011446, 29011406,
+static const uint64_t P9N2_EX_5_TRACE_TRDATA_CONFIG_3 = 0x2A011486ull;
+//DUPS: 12012D06, 2A011486, 2A011446, 2A011406, 2B011486, 2B011446, 2B011406,
+static const uint64_t P9N2_EX_6_TRACE_TRDATA_CONFIG_3 = 0x2C011486ull;
+//DUPS: 13012906, 2C011486, 2C011446, 2C011406, 2D011486, 2D011446, 2D011406,
+static const uint64_t P9N2_EX_7_TRACE_TRDATA_CONFIG_3 = 0x2F011486ull;
+//DUPS: 13012D06, 2E011486, 2E011446, 2E011406, 2F011486, 2F011446, 2F011406,
+static const uint64_t P9N2_EX_8_TRACE_TRDATA_CONFIG_3 = 0x14012906ull;
+//DUPS: 14012906, 30011486, 30011446, 30011406, 31011486, 31011446, 31011406,
+static const uint64_t P9N2_EX_9_TRACE_TRDATA_CONFIG_3 = 0x14012D46ull;
+//DUPS: 14012D06, 32011486, 32011446, 32011406, 33011486, 33011446, 33011406,
+static const uint64_t P9N2_EX_10_TRACE_TRDATA_CONFIG_3 = 0x15012906ull;
+//DUPS: 15012906, 34011486, 34011446, 34011406, 35011486, 35011446, 35011406,
+static const uint64_t P9N2_EX_11_TRACE_TRDATA_CONFIG_3 = 0x15012D46ull;
+//DUPS: 15012D06, 36011486, 36011446, 36011406, 37011486, 37011446, 37011406,
+
+static const uint64_t P9N2_C_TRACE_TRDATA_CONFIG_4 = 0x20011407ull;
+//DUPS: 20011447, 20011407,
+static const uint64_t P9N2_C_0_TRACE_TRDATA_CONFIG_4 = 0x20011407ull;
+//DUPS: 20011447, 20011407,
+static const uint64_t P9N2_C_1_TRACE_TRDATA_CONFIG_4 = 0x21011407ull;
+//DUPS: 21011447, 21011407,
+static const uint64_t P9N2_C_2_TRACE_TRDATA_CONFIG_4 = 0x22011407ull;
+//DUPS: 22011447, 22011407,
+static const uint64_t P9N2_C_3_TRACE_TRDATA_CONFIG_4 = 0x23011407ull;
+//DUPS: 23011447, 23011407,
+static const uint64_t P9N2_C_4_TRACE_TRDATA_CONFIG_4 = 0x24011407ull;
+//DUPS: 24011447, 24011407,
+static const uint64_t P9N2_C_5_TRACE_TRDATA_CONFIG_4 = 0x25011407ull;
+//DUPS: 25011447, 25011407,
+static const uint64_t P9N2_C_6_TRACE_TRDATA_CONFIG_4 = 0x26011407ull;
+//DUPS: 26011447, 26011407,
+static const uint64_t P9N2_C_7_TRACE_TRDATA_CONFIG_4 = 0x27011407ull;
+//DUPS: 27011447, 27011407,
+static const uint64_t P9N2_C_8_TRACE_TRDATA_CONFIG_4 = 0x28011407ull;
+//DUPS: 28011447, 28011407,
+static const uint64_t P9N2_C_9_TRACE_TRDATA_CONFIG_4 = 0x29011407ull;
+//DUPS: 29011447, 29011407,
+static const uint64_t P9N2_C_10_TRACE_TRDATA_CONFIG_4 = 0x2A011487ull;
+//DUPS: 2A011447, 2A011407,
+static const uint64_t P9N2_C_11_TRACE_TRDATA_CONFIG_4 = 0x2B011487ull;
+//DUPS: 2B011447, 2B011407,
+static const uint64_t P9N2_C_12_TRACE_TRDATA_CONFIG_4 = 0x2C011487ull;
+//DUPS: 2C011447, 2C011407,
+static const uint64_t P9N2_C_13_TRACE_TRDATA_CONFIG_4 = 0x2D011487ull;
+//DUPS: 2D011447, 2D011407,
+static const uint64_t P9N2_C_14_TRACE_TRDATA_CONFIG_4 = 0x2E011487ull;
+//DUPS: 2E011447, 2E011407,
+static const uint64_t P9N2_C_15_TRACE_TRDATA_CONFIG_4 = 0x2F011487ull;
+//DUPS: 2F011447, 2F011407,
+static const uint64_t P9N2_C_16_TRACE_TRDATA_CONFIG_4 = 0x30011407ull;
+//DUPS: 30011447, 30011407,
+static const uint64_t P9N2_C_17_TRACE_TRDATA_CONFIG_4 = 0x31011407ull;
+//DUPS: 31011447, 31011407,
+static const uint64_t P9N2_C_18_TRACE_TRDATA_CONFIG_4 = 0x32011407ull;
+//DUPS: 32011447, 32011407,
+static const uint64_t P9N2_C_19_TRACE_TRDATA_CONFIG_4 = 0x33011407ull;
+//DUPS: 33011447, 33011407,
+static const uint64_t P9N2_C_20_TRACE_TRDATA_CONFIG_4 = 0x34011407ull;
+//DUPS: 34011447, 34011407,
+static const uint64_t P9N2_C_21_TRACE_TRDATA_CONFIG_4 = 0x35011407ull;
+//DUPS: 35011447, 35011407,
+static const uint64_t P9N2_C_22_TRACE_TRDATA_CONFIG_4 = 0x36011407ull;
+//DUPS: 36011447, 36011407,
+static const uint64_t P9N2_C_23_TRACE_TRDATA_CONFIG_4 = 0x37011407ull;
+//DUPS: 37011447, 37011407,
+static const uint64_t P9N2_EQ_TRACE_TRDATA_CONFIG_4 = 0x10012D47ull;
+//DUPS: 10010407, 100104C7, 10010487, 10012947, 10012907, 10012D47, 10012D07,
+static const uint64_t P9N2_EQ_0_TRACE_TRDATA_CONFIG_4 = 0x10012D47ull;
+//DUPS: 10010407, 100104C7, 10010487, 10012947, 10012907, 10012D47, 10012D07,
+static const uint64_t P9N2_EQ_1_TRACE_TRDATA_CONFIG_4 = 0x11012D47ull;
+//DUPS: 11010407, 110104C7, 11010487, 11012947, 11012907, 11012D47, 11012D07,
+static const uint64_t P9N2_EQ_2_TRACE_TRDATA_CONFIG_4 = 0x12012D47ull;
+//DUPS: 12010407, 120104C7, 12010487, 12012947, 12012907, 12012D47, 12012D07,
+static const uint64_t P9N2_EQ_3_TRACE_TRDATA_CONFIG_4 = 0x13012D47ull;
+//DUPS: 13010407, 130104C7, 13010487, 13012947, 13012907, 13012D47, 13012D07,
+static const uint64_t P9N2_EQ_4_TRACE_TRDATA_CONFIG_4 = 0x14012D47ull;
+//DUPS: 14010407, 140104C7, 14010487, 14012947, 14012907, 14012D47, 14012D07,
+static const uint64_t P9N2_EQ_5_TRACE_TRDATA_CONFIG_4 = 0x15012D47ull;
+//DUPS: 15010407, 150104C7, 15010487, 15012947, 15012907, 15012D47, 15012D07,
+static const uint64_t P9N2_EX_TRACE_TRDATA_CONFIG_4 = 0x10012907ull;
+//DUPS: 10012907, 20011487, 20011447, 20011407, 21011487, 21011447, 21011407,
+static const uint64_t P9N2_EX_0_TRACE_TRDATA_CONFIG_4 = 0x10012907ull;
+//DUPS: 10012907, 20011487, 20011447, 20011407, 21011487, 21011447, 21011407,
+static const uint64_t P9N2_EX_1_TRACE_TRDATA_CONFIG_4 = 0x10012D47ull;
+//DUPS: 10012D07, 22011487, 22011447, 22011407, 23011487, 23011447, 23011407,
+static const uint64_t P9N2_EX_2_TRACE_TRDATA_CONFIG_4 = 0x11012907ull;
+//DUPS: 11012907, 24011487, 24011447, 24011407, 25011487, 25011447, 25011407,
+static const uint64_t P9N2_EX_3_TRACE_TRDATA_CONFIG_4 = 0x11012D47ull;
+//DUPS: 11012D07, 26011487, 26011447, 26011407, 27011487, 27011447, 27011407,
+static const uint64_t P9N2_EX_4_TRACE_TRDATA_CONFIG_4 = 0x12012907ull;
+//DUPS: 12012907, 28011487, 28011447, 28011407, 29011487, 29011447, 29011407,
+static const uint64_t P9N2_EX_5_TRACE_TRDATA_CONFIG_4 = 0x2A011487ull;
+//DUPS: 12012D07, 2A011487, 2A011447, 2A011407, 2B011487, 2B011447, 2B011407,
+static const uint64_t P9N2_EX_6_TRACE_TRDATA_CONFIG_4 = 0x2C011487ull;
+//DUPS: 13012907, 2C011487, 2C011447, 2C011407, 2D011487, 2D011447, 2D011407,
+static const uint64_t P9N2_EX_7_TRACE_TRDATA_CONFIG_4 = 0x2F011487ull;
+//DUPS: 13012D07, 2E011487, 2E011447, 2E011407, 2F011487, 2F011447, 2F011407,
+static const uint64_t P9N2_EX_8_TRACE_TRDATA_CONFIG_4 = 0x14012907ull;
+//DUPS: 14012907, 30011487, 30011447, 30011407, 31011487, 31011447, 31011407,
+static const uint64_t P9N2_EX_9_TRACE_TRDATA_CONFIG_4 = 0x14012D47ull;
+//DUPS: 14012D07, 32011487, 32011447, 32011407, 33011487, 33011447, 33011407,
+static const uint64_t P9N2_EX_10_TRACE_TRDATA_CONFIG_4 = 0x15012907ull;
+//DUPS: 15012907, 34011487, 34011447, 34011407, 35011487, 35011447, 35011407,
+static const uint64_t P9N2_EX_11_TRACE_TRDATA_CONFIG_4 = 0x15012D47ull;
+//DUPS: 15012D07, 36011487, 36011447, 36011407, 37011487, 37011447, 37011407,
+
+static const uint64_t P9N2_C_TRACE_TRDATA_CONFIG_5 = 0x20011408ull;
+//DUPS: 20011448, 20011408,
+static const uint64_t P9N2_C_0_TRACE_TRDATA_CONFIG_5 = 0x20011408ull;
+//DUPS: 20011448, 20011408,
+static const uint64_t P9N2_C_1_TRACE_TRDATA_CONFIG_5 = 0x21011408ull;
+//DUPS: 21011448, 21011408,
+static const uint64_t P9N2_C_2_TRACE_TRDATA_CONFIG_5 = 0x22011408ull;
+//DUPS: 22011448, 22011408,
+static const uint64_t P9N2_C_3_TRACE_TRDATA_CONFIG_5 = 0x23011408ull;
+//DUPS: 23011448, 23011408,
+static const uint64_t P9N2_C_4_TRACE_TRDATA_CONFIG_5 = 0x24011408ull;
+//DUPS: 24011448, 24011408,
+static const uint64_t P9N2_C_5_TRACE_TRDATA_CONFIG_5 = 0x25011408ull;
+//DUPS: 25011448, 25011408,
+static const uint64_t P9N2_C_6_TRACE_TRDATA_CONFIG_5 = 0x26011408ull;
+//DUPS: 26011448, 26011408,
+static const uint64_t P9N2_C_7_TRACE_TRDATA_CONFIG_5 = 0x27011408ull;
+//DUPS: 27011448, 27011408,
+static const uint64_t P9N2_C_8_TRACE_TRDATA_CONFIG_5 = 0x28011408ull;
+//DUPS: 28011448, 28011408,
+static const uint64_t P9N2_C_9_TRACE_TRDATA_CONFIG_5 = 0x29011408ull;
+//DUPS: 29011448, 29011408,
+static const uint64_t P9N2_C_10_TRACE_TRDATA_CONFIG_5 = 0x2A011488ull;
+//DUPS: 2A011448, 2A011408,
+static const uint64_t P9N2_C_11_TRACE_TRDATA_CONFIG_5 = 0x2B011488ull;
+//DUPS: 2B011448, 2B011408,
+static const uint64_t P9N2_C_12_TRACE_TRDATA_CONFIG_5 = 0x2C011488ull;
+//DUPS: 2C011448, 2C011408,
+static const uint64_t P9N2_C_13_TRACE_TRDATA_CONFIG_5 = 0x2D011488ull;
+//DUPS: 2D011448, 2D011408,
+static const uint64_t P9N2_C_14_TRACE_TRDATA_CONFIG_5 = 0x2E011488ull;
+//DUPS: 2E011448, 2E011408,
+static const uint64_t P9N2_C_15_TRACE_TRDATA_CONFIG_5 = 0x2F011488ull;
+//DUPS: 2F011448, 2F011408,
+static const uint64_t P9N2_C_16_TRACE_TRDATA_CONFIG_5 = 0x30011408ull;
+//DUPS: 30011448, 30011408,
+static const uint64_t P9N2_C_17_TRACE_TRDATA_CONFIG_5 = 0x31011408ull;
+//DUPS: 31011448, 31011408,
+static const uint64_t P9N2_C_18_TRACE_TRDATA_CONFIG_5 = 0x32011408ull;
+//DUPS: 32011448, 32011408,
+static const uint64_t P9N2_C_19_TRACE_TRDATA_CONFIG_5 = 0x33011408ull;
+//DUPS: 33011448, 33011408,
+static const uint64_t P9N2_C_20_TRACE_TRDATA_CONFIG_5 = 0x34011408ull;
+//DUPS: 34011448, 34011408,
+static const uint64_t P9N2_C_21_TRACE_TRDATA_CONFIG_5 = 0x35011408ull;
+//DUPS: 35011448, 35011408,
+static const uint64_t P9N2_C_22_TRACE_TRDATA_CONFIG_5 = 0x36011408ull;
+//DUPS: 36011448, 36011408,
+static const uint64_t P9N2_C_23_TRACE_TRDATA_CONFIG_5 = 0x37011408ull;
+//DUPS: 37011448, 37011408,
+static const uint64_t P9N2_EQ_TRACE_TRDATA_CONFIG_5 = 0x10012D48ull;
+//DUPS: 10010408, 100104C8, 10010488, 10012948, 10012908, 10012D48, 10012D08,
+static const uint64_t P9N2_EQ_0_TRACE_TRDATA_CONFIG_5 = 0x10012D48ull;
+//DUPS: 10010408, 100104C8, 10010488, 10012948, 10012908, 10012D48, 10012D08,
+static const uint64_t P9N2_EQ_1_TRACE_TRDATA_CONFIG_5 = 0x11012D48ull;
+//DUPS: 11010408, 110104C8, 11010488, 11012948, 11012908, 11012D48, 11012D08,
+static const uint64_t P9N2_EQ_2_TRACE_TRDATA_CONFIG_5 = 0x12012D48ull;
+//DUPS: 12010408, 120104C8, 12010488, 12012948, 12012908, 12012D48, 12012D08,
+static const uint64_t P9N2_EQ_3_TRACE_TRDATA_CONFIG_5 = 0x13012D48ull;
+//DUPS: 13010408, 130104C8, 13010488, 13012948, 13012908, 13012D48, 13012D08,
+static const uint64_t P9N2_EQ_4_TRACE_TRDATA_CONFIG_5 = 0x14012D48ull;
+//DUPS: 14010408, 140104C8, 14010488, 14012948, 14012908, 14012D48, 14012D08,
+static const uint64_t P9N2_EQ_5_TRACE_TRDATA_CONFIG_5 = 0x15012D48ull;
+//DUPS: 15010408, 150104C8, 15010488, 15012948, 15012908, 15012D48, 15012D08,
+static const uint64_t P9N2_EX_TRACE_TRDATA_CONFIG_5 = 0x10012908ull;
+//DUPS: 10012908, 20011488, 20011448, 20011408, 21011488, 21011448, 21011408,
+static const uint64_t P9N2_EX_0_TRACE_TRDATA_CONFIG_5 = 0x10012908ull;
+//DUPS: 10012908, 20011488, 20011448, 20011408, 21011488, 21011448, 21011408,
+static const uint64_t P9N2_EX_1_TRACE_TRDATA_CONFIG_5 = 0x10012D48ull;
+//DUPS: 10012D08, 22011488, 22011448, 22011408, 23011488, 23011448, 23011408,
+static const uint64_t P9N2_EX_2_TRACE_TRDATA_CONFIG_5 = 0x11012908ull;
+//DUPS: 11012908, 24011488, 24011448, 24011408, 25011488, 25011448, 25011408,
+static const uint64_t P9N2_EX_3_TRACE_TRDATA_CONFIG_5 = 0x11012D48ull;
+//DUPS: 11012D08, 26011488, 26011448, 26011408, 27011488, 27011448, 27011408,
+static const uint64_t P9N2_EX_4_TRACE_TRDATA_CONFIG_5 = 0x12012908ull;
+//DUPS: 12012908, 28011488, 28011448, 28011408, 29011488, 29011448, 29011408,
+static const uint64_t P9N2_EX_5_TRACE_TRDATA_CONFIG_5 = 0x2A011488ull;
+//DUPS: 12012D08, 2A011488, 2A011448, 2A011408, 2B011488, 2B011448, 2B011408,
+static const uint64_t P9N2_EX_6_TRACE_TRDATA_CONFIG_5 = 0x2C011488ull;
+//DUPS: 13012908, 2C011488, 2C011448, 2C011408, 2D011488, 2D011448, 2D011408,
+static const uint64_t P9N2_EX_7_TRACE_TRDATA_CONFIG_5 = 0x2F011488ull;
+//DUPS: 13012D08, 2E011488, 2E011448, 2E011408, 2F011488, 2F011448, 2F011408,
+static const uint64_t P9N2_EX_8_TRACE_TRDATA_CONFIG_5 = 0x14012908ull;
+//DUPS: 14012908, 30011488, 30011448, 30011408, 31011488, 31011448, 31011408,
+static const uint64_t P9N2_EX_9_TRACE_TRDATA_CONFIG_5 = 0x14012D48ull;
+//DUPS: 14012D08, 32011488, 32011448, 32011408, 33011488, 33011448, 33011408,
+static const uint64_t P9N2_EX_10_TRACE_TRDATA_CONFIG_5 = 0x15012908ull;
+//DUPS: 15012908, 34011488, 34011448, 34011408, 35011488, 35011448, 35011408,
+static const uint64_t P9N2_EX_11_TRACE_TRDATA_CONFIG_5 = 0x15012D48ull;
+//DUPS: 15012D08, 36011488, 36011448, 36011408, 37011488, 37011448, 37011408,
+
+static const uint64_t P9N2_C_TRACE_TRDATA_CONFIG_9 = 0x20011409ull;
+//DUPS: 20011449, 20011409,
+static const uint64_t P9N2_C_0_TRACE_TRDATA_CONFIG_9 = 0x20011409ull;
+//DUPS: 20011449, 20011409,
+static const uint64_t P9N2_C_1_TRACE_TRDATA_CONFIG_9 = 0x21011409ull;
+//DUPS: 21011449, 21011409,
+static const uint64_t P9N2_C_2_TRACE_TRDATA_CONFIG_9 = 0x22011409ull;
+//DUPS: 22011449, 22011409,
+static const uint64_t P9N2_C_3_TRACE_TRDATA_CONFIG_9 = 0x23011409ull;
+//DUPS: 23011449, 23011409,
+static const uint64_t P9N2_C_4_TRACE_TRDATA_CONFIG_9 = 0x24011409ull;
+//DUPS: 24011449, 24011409,
+static const uint64_t P9N2_C_5_TRACE_TRDATA_CONFIG_9 = 0x25011409ull;
+//DUPS: 25011449, 25011409,
+static const uint64_t P9N2_C_6_TRACE_TRDATA_CONFIG_9 = 0x26011409ull;
+//DUPS: 26011449, 26011409,
+static const uint64_t P9N2_C_7_TRACE_TRDATA_CONFIG_9 = 0x27011409ull;
+//DUPS: 27011449, 27011409,
+static const uint64_t P9N2_C_8_TRACE_TRDATA_CONFIG_9 = 0x28011409ull;
+//DUPS: 28011449, 28011409,
+static const uint64_t P9N2_C_9_TRACE_TRDATA_CONFIG_9 = 0x29011409ull;
+//DUPS: 29011449, 29011409,
+static const uint64_t P9N2_C_10_TRACE_TRDATA_CONFIG_9 = 0x2A011489ull;
+//DUPS: 2A011449, 2A011409,
+static const uint64_t P9N2_C_11_TRACE_TRDATA_CONFIG_9 = 0x2B011489ull;
+//DUPS: 2B011449, 2B011409,
+static const uint64_t P9N2_C_12_TRACE_TRDATA_CONFIG_9 = 0x2C011489ull;
+//DUPS: 2C011449, 2C011409,
+static const uint64_t P9N2_C_13_TRACE_TRDATA_CONFIG_9 = 0x2D011489ull;
+//DUPS: 2D011449, 2D011409,
+static const uint64_t P9N2_C_14_TRACE_TRDATA_CONFIG_9 = 0x2E011489ull;
+//DUPS: 2E011449, 2E011409,
+static const uint64_t P9N2_C_15_TRACE_TRDATA_CONFIG_9 = 0x2F011489ull;
+//DUPS: 2F011449, 2F011409,
+static const uint64_t P9N2_C_16_TRACE_TRDATA_CONFIG_9 = 0x30011409ull;
+//DUPS: 30011449, 30011409,
+static const uint64_t P9N2_C_17_TRACE_TRDATA_CONFIG_9 = 0x31011409ull;
+//DUPS: 31011449, 31011409,
+static const uint64_t P9N2_C_18_TRACE_TRDATA_CONFIG_9 = 0x32011409ull;
+//DUPS: 32011449, 32011409,
+static const uint64_t P9N2_C_19_TRACE_TRDATA_CONFIG_9 = 0x33011409ull;
+//DUPS: 33011449, 33011409,
+static const uint64_t P9N2_C_20_TRACE_TRDATA_CONFIG_9 = 0x34011409ull;
+//DUPS: 34011449, 34011409,
+static const uint64_t P9N2_C_21_TRACE_TRDATA_CONFIG_9 = 0x35011409ull;
+//DUPS: 35011449, 35011409,
+static const uint64_t P9N2_C_22_TRACE_TRDATA_CONFIG_9 = 0x36011409ull;
+//DUPS: 36011449, 36011409,
+static const uint64_t P9N2_C_23_TRACE_TRDATA_CONFIG_9 = 0x37011409ull;
+//DUPS: 37011449, 37011409,
+static const uint64_t P9N2_EQ_TRACE_TRDATA_CONFIG_9 = 0x10012D49ull;
+//DUPS: 10010409, 100104C9, 10010489, 10012949, 10012909, 10012D49, 10012D09,
+static const uint64_t P9N2_EQ_0_TRACE_TRDATA_CONFIG_9 = 0x10012D49ull;
+//DUPS: 10010409, 100104C9, 10010489, 10012949, 10012909, 10012D49, 10012D09,
+static const uint64_t P9N2_EQ_1_TRACE_TRDATA_CONFIG_9 = 0x11012D49ull;
+//DUPS: 11010409, 110104C9, 11010489, 11012949, 11012909, 11012D49, 11012D09,
+static const uint64_t P9N2_EQ_2_TRACE_TRDATA_CONFIG_9 = 0x12012D49ull;
+//DUPS: 12010409, 120104C9, 12010489, 12012949, 12012909, 12012D49, 12012D09,
+static const uint64_t P9N2_EQ_3_TRACE_TRDATA_CONFIG_9 = 0x13012D49ull;
+//DUPS: 13010409, 130104C9, 13010489, 13012949, 13012909, 13012D49, 13012D09,
+static const uint64_t P9N2_EQ_4_TRACE_TRDATA_CONFIG_9 = 0x14012D49ull;
+//DUPS: 14010409, 140104C9, 14010489, 14012949, 14012909, 14012D49, 14012D09,
+static const uint64_t P9N2_EQ_5_TRACE_TRDATA_CONFIG_9 = 0x15012D49ull;
+//DUPS: 15010409, 150104C9, 15010489, 15012949, 15012909, 15012D49, 15012D09,
+static const uint64_t P9N2_EX_TRACE_TRDATA_CONFIG_9 = 0x10012909ull;
+//DUPS: 10012909, 20011489, 20011449, 20011409, 21011489, 21011449, 21011409,
+static const uint64_t P9N2_EX_0_TRACE_TRDATA_CONFIG_9 = 0x10012909ull;
+//DUPS: 10012909, 20011489, 20011449, 20011409, 21011489, 21011449, 21011409,
+static const uint64_t P9N2_EX_1_TRACE_TRDATA_CONFIG_9 = 0x10012D49ull;
+//DUPS: 10012D09, 22011489, 22011449, 22011409, 23011489, 23011449, 23011409,
+static const uint64_t P9N2_EX_2_TRACE_TRDATA_CONFIG_9 = 0x11012909ull;
+//DUPS: 11012909, 24011489, 24011449, 24011409, 25011489, 25011449, 25011409,
+static const uint64_t P9N2_EX_3_TRACE_TRDATA_CONFIG_9 = 0x11012D49ull;
+//DUPS: 11012D09, 26011489, 26011449, 26011409, 27011489, 27011449, 27011409,
+static const uint64_t P9N2_EX_4_TRACE_TRDATA_CONFIG_9 = 0x12012909ull;
+//DUPS: 12012909, 28011489, 28011449, 28011409, 29011489, 29011449, 29011409,
+static const uint64_t P9N2_EX_5_TRACE_TRDATA_CONFIG_9 = 0x2A011489ull;
+//DUPS: 12012D09, 2A011489, 2A011449, 2A011409, 2B011489, 2B011449, 2B011409,
+static const uint64_t P9N2_EX_6_TRACE_TRDATA_CONFIG_9 = 0x2C011489ull;
+//DUPS: 13012909, 2C011489, 2C011449, 2C011409, 2D011489, 2D011449, 2D011409,
+static const uint64_t P9N2_EX_7_TRACE_TRDATA_CONFIG_9 = 0x2F011489ull;
+//DUPS: 13012D09, 2E011489, 2E011449, 2E011409, 2F011489, 2F011449, 2F011409,
+static const uint64_t P9N2_EX_8_TRACE_TRDATA_CONFIG_9 = 0x14012909ull;
+//DUPS: 14012909, 30011489, 30011449, 30011409, 31011489, 31011449, 31011409,
+static const uint64_t P9N2_EX_9_TRACE_TRDATA_CONFIG_9 = 0x14012D49ull;
+//DUPS: 14012D09, 32011489, 32011449, 32011409, 33011489, 33011449, 33011409,
+static const uint64_t P9N2_EX_10_TRACE_TRDATA_CONFIG_9 = 0x15012909ull;
+//DUPS: 15012909, 34011489, 34011449, 34011409, 35011489, 35011449, 35011409,
+static const uint64_t P9N2_EX_11_TRACE_TRDATA_CONFIG_9 = 0x15012D49ull;
+//DUPS: 15012D09, 36011489, 36011449, 36011409, 37011489, 37011449, 37011409,
+
+static const uint64_t P9N2_C_URMOR = 0x20010ABAull;
+
+static const uint64_t P9N2_C_0_URMOR = 0x20010ABAull;
+
+static const uint64_t P9N2_C_1_URMOR = 0x21010ABAull;
+
+static const uint64_t P9N2_C_2_URMOR = 0x22010ABAull;
+
+static const uint64_t P9N2_C_3_URMOR = 0x23010ABAull;
+
+static const uint64_t P9N2_C_4_URMOR = 0x24010ABAull;
+
+static const uint64_t P9N2_C_5_URMOR = 0x25010ABAull;
+
+static const uint64_t P9N2_C_6_URMOR = 0x26010ABAull;
+
+static const uint64_t P9N2_C_7_URMOR = 0x27010ABAull;
+
+static const uint64_t P9N2_C_8_URMOR = 0x28010ABAull;
+
+static const uint64_t P9N2_C_9_URMOR = 0x29010ABAull;
+
+static const uint64_t P9N2_C_10_URMOR = 0x2A010ABAull;
+
+static const uint64_t P9N2_C_11_URMOR = 0x2B010ABAull;
+
+static const uint64_t P9N2_C_12_URMOR = 0x2C010ABAull;
+
+static const uint64_t P9N2_C_13_URMOR = 0x2D010ABAull;
+
+static const uint64_t P9N2_C_14_URMOR = 0x2E010ABAull;
+
+static const uint64_t P9N2_C_15_URMOR = 0x2F010ABAull;
+
+static const uint64_t P9N2_C_16_URMOR = 0x30010ABAull;
+
+static const uint64_t P9N2_C_17_URMOR = 0x31010ABAull;
+
+static const uint64_t P9N2_C_18_URMOR = 0x32010ABAull;
+
+static const uint64_t P9N2_C_19_URMOR = 0x33010ABAull;
+
+static const uint64_t P9N2_C_20_URMOR = 0x34010ABAull;
+
+static const uint64_t P9N2_C_21_URMOR = 0x35010ABAull;
+
+static const uint64_t P9N2_C_22_URMOR = 0x36010ABAull;
+
+static const uint64_t P9N2_C_23_URMOR = 0x37010ABAull;
+
+static const uint64_t P9N2_EX_0_L2_URMOR = 0x20010ABAull;
+//DUPS: 21010ABA,
+static const uint64_t P9N2_EX_10_L2_URMOR = 0x34010ABAull;
+//DUPS: 35010ABA,
+static const uint64_t P9N2_EX_11_L2_URMOR = 0x36010ABAull;
+//DUPS: 37010ABA,
+static const uint64_t P9N2_EX_1_L2_URMOR = 0x22010ABAull;
+//DUPS: 23010ABA,
+static const uint64_t P9N2_EX_2_L2_URMOR = 0x24010ABAull;
+//DUPS: 25010ABA,
+static const uint64_t P9N2_EX_3_L2_URMOR = 0x26010ABAull;
+//DUPS: 27010ABA,
+static const uint64_t P9N2_EX_4_L2_URMOR = 0x28010ABAull;
+//DUPS: 29010ABA,
+static const uint64_t P9N2_EX_5_L2_URMOR = 0x2A010ABAull;
+//DUPS: 2B010ABA,
+static const uint64_t P9N2_EX_6_L2_URMOR = 0x2C010ABAull;
+//DUPS: 2D010ABA,
+static const uint64_t P9N2_EX_7_L2_URMOR = 0x2F010ABAull;
+//DUPS: 2F010ABA,
+static const uint64_t P9N2_EX_8_L2_URMOR = 0x30010ABAull;
+//DUPS: 31010ABA,
+static const uint64_t P9N2_EX_9_L2_URMOR = 0x32010ABAull;
+//DUPS: 33010ABA,
+static const uint64_t P9N2_EX_L2_URMOR = 0x20010ABAull;
+//DUPS: 21010ABA,
+
+static const uint64_t P9N2_C_V0_HMER_WAND = 0x20010A92ull;
+
+static const uint64_t P9N2_C_V0_HMER_OR = 0x20010A8Eull;
+
+static const uint64_t P9N2_C_0_V0_HMER_WAND = 0x20010A92ull;
+
+static const uint64_t P9N2_C_0_V0_HMER_OR = 0x20010A8Eull;
+
+static const uint64_t P9N2_C_1_V0_HMER_WAND = 0x21010A92ull;
+
+static const uint64_t P9N2_C_1_V0_HMER_OR = 0x21010A8Eull;
+
+static const uint64_t P9N2_C_2_V0_HMER_WAND = 0x22010A92ull;
+
+static const uint64_t P9N2_C_2_V0_HMER_OR = 0x22010A8Eull;
+
+static const uint64_t P9N2_C_3_V0_HMER_WAND = 0x23010A92ull;
+
+static const uint64_t P9N2_C_3_V0_HMER_OR = 0x23010A8Eull;
+
+static const uint64_t P9N2_C_4_V0_HMER_WAND = 0x24010A92ull;
+
+static const uint64_t P9N2_C_4_V0_HMER_OR = 0x24010A8Eull;
+
+static const uint64_t P9N2_C_5_V0_HMER_WAND = 0x25010A92ull;
+
+static const uint64_t P9N2_C_5_V0_HMER_OR = 0x25010A8Eull;
+
+static const uint64_t P9N2_C_6_V0_HMER_WAND = 0x26010A92ull;
+
+static const uint64_t P9N2_C_6_V0_HMER_OR = 0x26010A8Eull;
+
+static const uint64_t P9N2_C_7_V0_HMER_WAND = 0x27010A92ull;
+
+static const uint64_t P9N2_C_7_V0_HMER_OR = 0x27010A8Eull;
+
+static const uint64_t P9N2_C_8_V0_HMER_WAND = 0x28010A92ull;
+
+static const uint64_t P9N2_C_8_V0_HMER_OR = 0x28010A8Eull;
+
+static const uint64_t P9N2_C_9_V0_HMER_WAND = 0x29010A92ull;
+
+static const uint64_t P9N2_C_9_V0_HMER_OR = 0x29010A8Eull;
+
+static const uint64_t P9N2_C_10_V0_HMER_WAND = 0x2A010A92ull;
+
+static const uint64_t P9N2_C_10_V0_HMER_OR = 0x2A010A8Eull;
+
+static const uint64_t P9N2_C_11_V0_HMER_WAND = 0x2B010A92ull;
+
+static const uint64_t P9N2_C_11_V0_HMER_OR = 0x2B010A8Eull;
+
+static const uint64_t P9N2_C_12_V0_HMER_WAND = 0x2C010A92ull;
+
+static const uint64_t P9N2_C_12_V0_HMER_OR = 0x2C010A8Eull;
+
+static const uint64_t P9N2_C_13_V0_HMER_WAND = 0x2D010A92ull;
+
+static const uint64_t P9N2_C_13_V0_HMER_OR = 0x2D010A8Eull;
+
+static const uint64_t P9N2_C_14_V0_HMER_WAND = 0x2E010A92ull;
+
+static const uint64_t P9N2_C_14_V0_HMER_OR = 0x2E010A8Eull;
+
+static const uint64_t P9N2_C_15_V0_HMER_WAND = 0x2F010A92ull;
+
+static const uint64_t P9N2_C_15_V0_HMER_OR = 0x2F010A8Eull;
+
+static const uint64_t P9N2_C_16_V0_HMER_WAND = 0x30010A92ull;
+
+static const uint64_t P9N2_C_16_V0_HMER_OR = 0x30010A8Eull;
+
+static const uint64_t P9N2_C_17_V0_HMER_WAND = 0x31010A92ull;
+
+static const uint64_t P9N2_C_17_V0_HMER_OR = 0x31010A8Eull;
+
+static const uint64_t P9N2_C_18_V0_HMER_WAND = 0x32010A92ull;
+
+static const uint64_t P9N2_C_18_V0_HMER_OR = 0x32010A8Eull;
+
+static const uint64_t P9N2_C_19_V0_HMER_WAND = 0x33010A92ull;
+
+static const uint64_t P9N2_C_19_V0_HMER_OR = 0x33010A8Eull;
+
+static const uint64_t P9N2_C_20_V0_HMER_WAND = 0x34010A92ull;
+
+static const uint64_t P9N2_C_20_V0_HMER_OR = 0x34010A8Eull;
+
+static const uint64_t P9N2_C_21_V0_HMER_WAND = 0x35010A92ull;
+
+static const uint64_t P9N2_C_21_V0_HMER_OR = 0x35010A8Eull;
+
+static const uint64_t P9N2_C_22_V0_HMER_WAND = 0x36010A92ull;
+
+static const uint64_t P9N2_C_22_V0_HMER_OR = 0x36010A8Eull;
+
+static const uint64_t P9N2_C_23_V0_HMER_WAND = 0x37010A92ull;
+
+static const uint64_t P9N2_C_23_V0_HMER_OR = 0x37010A8Eull;
+
+static const uint64_t P9N2_EX_V0_HMER = 0x20010A8Eull;
+//DUPS: 20010A8E,
+static const uint64_t P9N2_EX_0_V0_HMER = 0x20010A8Eull;
+//DUPS: 20010A8E,
+static const uint64_t P9N2_EX_1_V0_HMER = 0x22010A8Eull;
+//DUPS: 22010A8E,
+static const uint64_t P9N2_EX_2_V0_HMER = 0x24010A8Eull;
+//DUPS: 24010A8E,
+static const uint64_t P9N2_EX_3_V0_HMER = 0x26010A8Eull;
+//DUPS: 26010A8E,
+static const uint64_t P9N2_EX_4_V0_HMER = 0x28010A8Eull;
+//DUPS: 28010A8E,
+static const uint64_t P9N2_EX_5_V0_HMER = 0x2B010A8Eull;
+//DUPS: 2A010A8E,
+static const uint64_t P9N2_EX_6_V0_HMER = 0x2D010A8Eull;
+//DUPS: 2C010A8E,
+static const uint64_t P9N2_EX_7_V0_HMER = 0x2F010A8Eull;
+//DUPS: 2E010A8E,
+static const uint64_t P9N2_EX_8_V0_HMER = 0x30010A8Eull;
+//DUPS: 30010A8E,
+static const uint64_t P9N2_EX_9_V0_HMER = 0x32010A8Eull;
+//DUPS: 32010A8E,
+static const uint64_t P9N2_EX_0_L2_V0_HMER = 0x20010A92ull;
+//DUPS: 20010A92,
+static const uint64_t P9N2_EX_10_V0_HMER = 0x34010A8Eull;
+//DUPS: 34010A8E,
+static const uint64_t P9N2_EX_11_V0_HMER = 0x36010A8Eull;
+//DUPS: 36010A8E,
+static const uint64_t P9N2_EX_10_L2_V0_HMER = 0x34010A92ull;
+//DUPS: 34010A92,
+static const uint64_t P9N2_EX_11_L2_V0_HMER = 0x36010A92ull;
+//DUPS: 36010A92,
+static const uint64_t P9N2_EX_1_L2_V0_HMER = 0x22010A92ull;
+//DUPS: 22010A92,
+static const uint64_t P9N2_EX_2_L2_V0_HMER = 0x24010A92ull;
+//DUPS: 24010A92,
+static const uint64_t P9N2_EX_3_L2_V0_HMER = 0x26010A92ull;
+//DUPS: 26010A92,
+static const uint64_t P9N2_EX_4_L2_V0_HMER = 0x28010A92ull;
+//DUPS: 28010A92,
+static const uint64_t P9N2_EX_5_L2_V0_HMER = 0x2B010A92ull;
+//DUPS: 2A010A92,
+static const uint64_t P9N2_EX_6_L2_V0_HMER = 0x2D010A92ull;
+//DUPS: 2C010A92,
+static const uint64_t P9N2_EX_7_L2_V0_HMER = 0x2F010A92ull;
+//DUPS: 2E010A92,
+static const uint64_t P9N2_EX_8_L2_V0_HMER = 0x30010A92ull;
+//DUPS: 30010A92,
+static const uint64_t P9N2_EX_9_L2_V0_HMER = 0x32010A92ull;
+//DUPS: 32010A92,
+static const uint64_t P9N2_EX_L2_V0_HMER = 0x20010A92ull;
+//DUPS: 20010A92,
+
+static const uint64_t P9N2_C_V1_HMER_WAND = 0x20010A93ull;
+
+static const uint64_t P9N2_C_V1_HMER_OR = 0x20010A8Full;
+
+static const uint64_t P9N2_C_0_V1_HMER_WAND = 0x20010A93ull;
+
+static const uint64_t P9N2_C_0_V1_HMER_OR = 0x20010A8Full;
+
+static const uint64_t P9N2_C_1_V1_HMER_WAND = 0x21010A93ull;
+
+static const uint64_t P9N2_C_1_V1_HMER_OR = 0x21010A8Full;
+
+static const uint64_t P9N2_C_2_V1_HMER_WAND = 0x22010A93ull;
+
+static const uint64_t P9N2_C_2_V1_HMER_OR = 0x22010A8Full;
+
+static const uint64_t P9N2_C_3_V1_HMER_WAND = 0x23010A93ull;
+
+static const uint64_t P9N2_C_3_V1_HMER_OR = 0x23010A8Full;
+
+static const uint64_t P9N2_C_4_V1_HMER_WAND = 0x24010A93ull;
+
+static const uint64_t P9N2_C_4_V1_HMER_OR = 0x24010A8Full;
+
+static const uint64_t P9N2_C_5_V1_HMER_WAND = 0x25010A93ull;
+
+static const uint64_t P9N2_C_5_V1_HMER_OR = 0x25010A8Full;
+
+static const uint64_t P9N2_C_6_V1_HMER_WAND = 0x26010A93ull;
+
+static const uint64_t P9N2_C_6_V1_HMER_OR = 0x26010A8Full;
+
+static const uint64_t P9N2_C_7_V1_HMER_WAND = 0x27010A93ull;
+
+static const uint64_t P9N2_C_7_V1_HMER_OR = 0x27010A8Full;
+
+static const uint64_t P9N2_C_8_V1_HMER_WAND = 0x28010A93ull;
+
+static const uint64_t P9N2_C_8_V1_HMER_OR = 0x28010A8Full;
+
+static const uint64_t P9N2_C_9_V1_HMER_WAND = 0x29010A93ull;
+
+static const uint64_t P9N2_C_9_V1_HMER_OR = 0x29010A8Full;
+
+static const uint64_t P9N2_C_10_V1_HMER_WAND = 0x2A010A93ull;
+
+static const uint64_t P9N2_C_10_V1_HMER_OR = 0x2A010A8Full;
+
+static const uint64_t P9N2_C_11_V1_HMER_WAND = 0x2B010A93ull;
+
+static const uint64_t P9N2_C_11_V1_HMER_OR = 0x2B010A8Full;
+
+static const uint64_t P9N2_C_12_V1_HMER_WAND = 0x2C010A93ull;
+
+static const uint64_t P9N2_C_12_V1_HMER_OR = 0x2C010A8Full;
+
+static const uint64_t P9N2_C_13_V1_HMER_WAND = 0x2D010A93ull;
+
+static const uint64_t P9N2_C_13_V1_HMER_OR = 0x2D010A8Full;
+
+static const uint64_t P9N2_C_14_V1_HMER_WAND = 0x2E010A93ull;
+
+static const uint64_t P9N2_C_14_V1_HMER_OR = 0x2E010A8Full;
+
+static const uint64_t P9N2_C_15_V1_HMER_WAND = 0x2F010A93ull;
+
+static const uint64_t P9N2_C_15_V1_HMER_OR = 0x2F010A8Full;
+
+static const uint64_t P9N2_C_16_V1_HMER_WAND = 0x30010A93ull;
+
+static const uint64_t P9N2_C_16_V1_HMER_OR = 0x30010A8Full;
+
+static const uint64_t P9N2_C_17_V1_HMER_WAND = 0x31010A93ull;
+
+static const uint64_t P9N2_C_17_V1_HMER_OR = 0x31010A8Full;
+
+static const uint64_t P9N2_C_18_V1_HMER_WAND = 0x32010A93ull;
+
+static const uint64_t P9N2_C_18_V1_HMER_OR = 0x32010A8Full;
+
+static const uint64_t P9N2_C_19_V1_HMER_WAND = 0x33010A93ull;
+
+static const uint64_t P9N2_C_19_V1_HMER_OR = 0x33010A8Full;
+
+static const uint64_t P9N2_C_20_V1_HMER_WAND = 0x34010A93ull;
+
+static const uint64_t P9N2_C_20_V1_HMER_OR = 0x34010A8Full;
+
+static const uint64_t P9N2_C_21_V1_HMER_WAND = 0x35010A93ull;
+
+static const uint64_t P9N2_C_21_V1_HMER_OR = 0x35010A8Full;
+
+static const uint64_t P9N2_C_22_V1_HMER_WAND = 0x36010A93ull;
+
+static const uint64_t P9N2_C_22_V1_HMER_OR = 0x36010A8Full;
+
+static const uint64_t P9N2_C_23_V1_HMER_WAND = 0x37010A93ull;
+
+static const uint64_t P9N2_C_23_V1_HMER_OR = 0x37010A8Full;
+
+static const uint64_t P9N2_EX_V1_HMER = 0x20010A8Full;
+//DUPS: 20010A8F,
+static const uint64_t P9N2_EX_0_V1_HMER = 0x20010A8Full;
+//DUPS: 20010A8F,
+static const uint64_t P9N2_EX_1_V1_HMER = 0x22010A8Full;
+//DUPS: 22010A8F,
+static const uint64_t P9N2_EX_2_V1_HMER = 0x24010A8Full;
+//DUPS: 24010A8F,
+static const uint64_t P9N2_EX_3_V1_HMER = 0x26010A8Full;
+//DUPS: 26010A8F,
+static const uint64_t P9N2_EX_4_V1_HMER = 0x28010A8Full;
+//DUPS: 28010A8F,
+static const uint64_t P9N2_EX_5_V1_HMER = 0x2B010A8Full;
+//DUPS: 2A010A8F,
+static const uint64_t P9N2_EX_6_V1_HMER = 0x2D010A8Full;
+//DUPS: 2C010A8F,
+static const uint64_t P9N2_EX_7_V1_HMER = 0x2F010A8Full;
+//DUPS: 2E010A8F,
+static const uint64_t P9N2_EX_8_V1_HMER = 0x30010A8Full;
+//DUPS: 30010A8F,
+static const uint64_t P9N2_EX_9_V1_HMER = 0x32010A8Full;
+//DUPS: 32010A8F,
+static const uint64_t P9N2_EX_0_L2_V1_HMER = 0x20010A93ull;
+//DUPS: 20010A93,
+static const uint64_t P9N2_EX_10_V1_HMER = 0x34010A8Full;
+//DUPS: 34010A8F,
+static const uint64_t P9N2_EX_11_V1_HMER = 0x36010A8Full;
+//DUPS: 36010A8F,
+static const uint64_t P9N2_EX_10_L2_V1_HMER = 0x34010A93ull;
+//DUPS: 34010A93,
+static const uint64_t P9N2_EX_11_L2_V1_HMER = 0x36010A93ull;
+//DUPS: 36010A93,
+static const uint64_t P9N2_EX_1_L2_V1_HMER = 0x22010A93ull;
+//DUPS: 22010A93,
+static const uint64_t P9N2_EX_2_L2_V1_HMER = 0x24010A93ull;
+//DUPS: 24010A93,
+static const uint64_t P9N2_EX_3_L2_V1_HMER = 0x26010A93ull;
+//DUPS: 26010A93,
+static const uint64_t P9N2_EX_4_L2_V1_HMER = 0x28010A93ull;
+//DUPS: 28010A93,
+static const uint64_t P9N2_EX_5_L2_V1_HMER = 0x2B010A93ull;
+//DUPS: 2A010A93,
+static const uint64_t P9N2_EX_6_L2_V1_HMER = 0x2D010A93ull;
+//DUPS: 2C010A93,
+static const uint64_t P9N2_EX_7_L2_V1_HMER = 0x2F010A93ull;
+//DUPS: 2E010A93,
+static const uint64_t P9N2_EX_8_L2_V1_HMER = 0x30010A93ull;
+//DUPS: 30010A93,
+static const uint64_t P9N2_EX_9_L2_V1_HMER = 0x32010A93ull;
+//DUPS: 32010A93,
+static const uint64_t P9N2_EX_L2_V1_HMER = 0x20010A93ull;
+//DUPS: 20010A93,
+
+static const uint64_t P9N2_C_V2_HMER_WAND = 0x20010A94ull;
+
+static const uint64_t P9N2_C_V2_HMER_OR = 0x20010A90ull;
+
+static const uint64_t P9N2_C_0_V2_HMER_WAND = 0x20010A94ull;
+
+static const uint64_t P9N2_C_0_V2_HMER_OR = 0x20010A90ull;
+
+static const uint64_t P9N2_C_1_V2_HMER_WAND = 0x21010A94ull;
+
+static const uint64_t P9N2_C_1_V2_HMER_OR = 0x21010A90ull;
+
+static const uint64_t P9N2_C_2_V2_HMER_WAND = 0x22010A94ull;
+
+static const uint64_t P9N2_C_2_V2_HMER_OR = 0x22010A90ull;
+
+static const uint64_t P9N2_C_3_V2_HMER_WAND = 0x23010A94ull;
+
+static const uint64_t P9N2_C_3_V2_HMER_OR = 0x23010A90ull;
+
+static const uint64_t P9N2_C_4_V2_HMER_WAND = 0x24010A94ull;
+
+static const uint64_t P9N2_C_4_V2_HMER_OR = 0x24010A90ull;
+
+static const uint64_t P9N2_C_5_V2_HMER_WAND = 0x25010A94ull;
+
+static const uint64_t P9N2_C_5_V2_HMER_OR = 0x25010A90ull;
+
+static const uint64_t P9N2_C_6_V2_HMER_WAND = 0x26010A94ull;
+
+static const uint64_t P9N2_C_6_V2_HMER_OR = 0x26010A90ull;
+
+static const uint64_t P9N2_C_7_V2_HMER_WAND = 0x27010A94ull;
+
+static const uint64_t P9N2_C_7_V2_HMER_OR = 0x27010A90ull;
+
+static const uint64_t P9N2_C_8_V2_HMER_WAND = 0x28010A94ull;
+
+static const uint64_t P9N2_C_8_V2_HMER_OR = 0x28010A90ull;
+
+static const uint64_t P9N2_C_9_V2_HMER_WAND = 0x29010A94ull;
+
+static const uint64_t P9N2_C_9_V2_HMER_OR = 0x29010A90ull;
+
+static const uint64_t P9N2_C_10_V2_HMER_WAND = 0x2A010A94ull;
+
+static const uint64_t P9N2_C_10_V2_HMER_OR = 0x2A010A90ull;
+
+static const uint64_t P9N2_C_11_V2_HMER_WAND = 0x2B010A94ull;
+
+static const uint64_t P9N2_C_11_V2_HMER_OR = 0x2B010A90ull;
+
+static const uint64_t P9N2_C_12_V2_HMER_WAND = 0x2C010A94ull;
+
+static const uint64_t P9N2_C_12_V2_HMER_OR = 0x2C010A90ull;
+
+static const uint64_t P9N2_C_13_V2_HMER_WAND = 0x2D010A94ull;
+
+static const uint64_t P9N2_C_13_V2_HMER_OR = 0x2D010A90ull;
+
+static const uint64_t P9N2_C_14_V2_HMER_WAND = 0x2E010A94ull;
+
+static const uint64_t P9N2_C_14_V2_HMER_OR = 0x2E010A90ull;
+
+static const uint64_t P9N2_C_15_V2_HMER_WAND = 0x2F010A94ull;
+
+static const uint64_t P9N2_C_15_V2_HMER_OR = 0x2F010A90ull;
+
+static const uint64_t P9N2_C_16_V2_HMER_WAND = 0x30010A94ull;
+
+static const uint64_t P9N2_C_16_V2_HMER_OR = 0x30010A90ull;
+
+static const uint64_t P9N2_C_17_V2_HMER_WAND = 0x31010A94ull;
+
+static const uint64_t P9N2_C_17_V2_HMER_OR = 0x31010A90ull;
+
+static const uint64_t P9N2_C_18_V2_HMER_WAND = 0x32010A94ull;
+
+static const uint64_t P9N2_C_18_V2_HMER_OR = 0x32010A90ull;
+
+static const uint64_t P9N2_C_19_V2_HMER_WAND = 0x33010A94ull;
+
+static const uint64_t P9N2_C_19_V2_HMER_OR = 0x33010A90ull;
+
+static const uint64_t P9N2_C_20_V2_HMER_WAND = 0x34010A94ull;
+
+static const uint64_t P9N2_C_20_V2_HMER_OR = 0x34010A90ull;
+
+static const uint64_t P9N2_C_21_V2_HMER_WAND = 0x35010A94ull;
+
+static const uint64_t P9N2_C_21_V2_HMER_OR = 0x35010A90ull;
+
+static const uint64_t P9N2_C_22_V2_HMER_WAND = 0x36010A94ull;
+
+static const uint64_t P9N2_C_22_V2_HMER_OR = 0x36010A90ull;
+
+static const uint64_t P9N2_C_23_V2_HMER_WAND = 0x37010A94ull;
+
+static const uint64_t P9N2_C_23_V2_HMER_OR = 0x37010A90ull;
+
+static const uint64_t P9N2_EX_0_L2_V2_HMER_WAND = 0x20010A94ull;
+//DUPS: 20010A94,
+static const uint64_t P9N2_EX_0_L2_V2_HMER_OR = 0x20010A90ull;
+//DUPS: 20010A90,
+static const uint64_t P9N2_EX_10_L2_V2_HMER_WAND = 0x34010A94ull;
+//DUPS: 34010A94,
+static const uint64_t P9N2_EX_10_L2_V2_HMER_OR = 0x34010A90ull;
+//DUPS: 34010A90,
+static const uint64_t P9N2_EX_11_L2_V2_HMER_WAND = 0x36010A94ull;
+//DUPS: 36010A94,
+static const uint64_t P9N2_EX_11_L2_V2_HMER_OR = 0x36010A90ull;
+//DUPS: 36010A90,
+static const uint64_t P9N2_EX_1_L2_V2_HMER_WAND = 0x22010A94ull;
+//DUPS: 22010A94,
+static const uint64_t P9N2_EX_1_L2_V2_HMER_OR = 0x22010A90ull;
+//DUPS: 22010A90,
+static const uint64_t P9N2_EX_2_L2_V2_HMER_WAND = 0x24010A94ull;
+//DUPS: 24010A94,
+static const uint64_t P9N2_EX_2_L2_V2_HMER_OR = 0x24010A90ull;
+//DUPS: 24010A90,
+static const uint64_t P9N2_EX_3_L2_V2_HMER_WAND = 0x26010A94ull;
+//DUPS: 26010A94,
+static const uint64_t P9N2_EX_3_L2_V2_HMER_OR = 0x26010A90ull;
+//DUPS: 26010A90,
+static const uint64_t P9N2_EX_4_L2_V2_HMER_WAND = 0x28010A94ull;
+//DUPS: 28010A94,
+static const uint64_t P9N2_EX_4_L2_V2_HMER_OR = 0x28010A90ull;
+//DUPS: 28010A90,
+static const uint64_t P9N2_EX_5_L2_V2_HMER_WAND = 0x2B010A94ull;
+//DUPS: 2A010A94,
+static const uint64_t P9N2_EX_5_L2_V2_HMER_OR = 0x2B010A90ull;
+//DUPS: 2A010A90,
+static const uint64_t P9N2_EX_6_L2_V2_HMER_WAND = 0x2D010A94ull;
+//DUPS: 2C010A94,
+static const uint64_t P9N2_EX_6_L2_V2_HMER_OR = 0x2D010A90ull;
+//DUPS: 2C010A90,
+static const uint64_t P9N2_EX_7_L2_V2_HMER_WAND = 0x2F010A94ull;
+//DUPS: 2E010A94,
+static const uint64_t P9N2_EX_7_L2_V2_HMER_OR = 0x2F010A90ull;
+//DUPS: 2E010A90,
+static const uint64_t P9N2_EX_8_L2_V2_HMER_WAND = 0x30010A94ull;
+//DUPS: 30010A94,
+static const uint64_t P9N2_EX_8_L2_V2_HMER_OR = 0x30010A90ull;
+//DUPS: 30010A90,
+static const uint64_t P9N2_EX_9_L2_V2_HMER_WAND = 0x32010A94ull;
+//DUPS: 32010A94,
+static const uint64_t P9N2_EX_9_L2_V2_HMER_OR = 0x32010A90ull;
+//DUPS: 32010A90,
+static const uint64_t P9N2_EX_L2_V2_HMER_WAND = 0x20010A94ull;
+//DUPS: 20010A94,
+static const uint64_t P9N2_EX_L2_V2_HMER_OR = 0x20010A90ull;
+//DUPS: 20010A90,
+
+static const uint64_t P9N2_C_V3_HMER_WAND = 0x20010A95ull;
+
+static const uint64_t P9N2_C_V3_HMER_OR = 0x20010A91ull;
+
+static const uint64_t P9N2_C_0_V3_HMER_WAND = 0x20010A95ull;
+
+static const uint64_t P9N2_C_0_V3_HMER_OR = 0x20010A91ull;
+
+static const uint64_t P9N2_C_1_V3_HMER_WAND = 0x21010A95ull;
+
+static const uint64_t P9N2_C_1_V3_HMER_OR = 0x21010A91ull;
+
+static const uint64_t P9N2_C_2_V3_HMER_WAND = 0x22010A95ull;
+
+static const uint64_t P9N2_C_2_V3_HMER_OR = 0x22010A91ull;
+
+static const uint64_t P9N2_C_3_V3_HMER_WAND = 0x23010A95ull;
+
+static const uint64_t P9N2_C_3_V3_HMER_OR = 0x23010A91ull;
+
+static const uint64_t P9N2_C_4_V3_HMER_WAND = 0x24010A95ull;
+
+static const uint64_t P9N2_C_4_V3_HMER_OR = 0x24010A91ull;
+
+static const uint64_t P9N2_C_5_V3_HMER_WAND = 0x25010A95ull;
+
+static const uint64_t P9N2_C_5_V3_HMER_OR = 0x25010A91ull;
+
+static const uint64_t P9N2_C_6_V3_HMER_WAND = 0x26010A95ull;
+
+static const uint64_t P9N2_C_6_V3_HMER_OR = 0x26010A91ull;
+
+static const uint64_t P9N2_C_7_V3_HMER_WAND = 0x27010A95ull;
+
+static const uint64_t P9N2_C_7_V3_HMER_OR = 0x27010A91ull;
+
+static const uint64_t P9N2_C_8_V3_HMER_WAND = 0x28010A95ull;
+
+static const uint64_t P9N2_C_8_V3_HMER_OR = 0x28010A91ull;
+
+static const uint64_t P9N2_C_9_V3_HMER_WAND = 0x29010A95ull;
+
+static const uint64_t P9N2_C_9_V3_HMER_OR = 0x29010A91ull;
+
+static const uint64_t P9N2_C_10_V3_HMER_WAND = 0x2A010A95ull;
+
+static const uint64_t P9N2_C_10_V3_HMER_OR = 0x2A010A91ull;
+
+static const uint64_t P9N2_C_11_V3_HMER_WAND = 0x2B010A95ull;
+
+static const uint64_t P9N2_C_11_V3_HMER_OR = 0x2B010A91ull;
+
+static const uint64_t P9N2_C_12_V3_HMER_WAND = 0x2C010A95ull;
+
+static const uint64_t P9N2_C_12_V3_HMER_OR = 0x2C010A91ull;
+
+static const uint64_t P9N2_C_13_V3_HMER_WAND = 0x2D010A95ull;
+
+static const uint64_t P9N2_C_13_V3_HMER_OR = 0x2D010A91ull;
+
+static const uint64_t P9N2_C_14_V3_HMER_WAND = 0x2E010A95ull;
+
+static const uint64_t P9N2_C_14_V3_HMER_OR = 0x2E010A91ull;
+
+static const uint64_t P9N2_C_15_V3_HMER_WAND = 0x2F010A95ull;
+
+static const uint64_t P9N2_C_15_V3_HMER_OR = 0x2F010A91ull;
+
+static const uint64_t P9N2_C_16_V3_HMER_WAND = 0x30010A95ull;
+
+static const uint64_t P9N2_C_16_V3_HMER_OR = 0x30010A91ull;
+
+static const uint64_t P9N2_C_17_V3_HMER_WAND = 0x31010A95ull;
+
+static const uint64_t P9N2_C_17_V3_HMER_OR = 0x31010A91ull;
+
+static const uint64_t P9N2_C_18_V3_HMER_WAND = 0x32010A95ull;
+
+static const uint64_t P9N2_C_18_V3_HMER_OR = 0x32010A91ull;
+
+static const uint64_t P9N2_C_19_V3_HMER_WAND = 0x33010A95ull;
+
+static const uint64_t P9N2_C_19_V3_HMER_OR = 0x33010A91ull;
+
+static const uint64_t P9N2_C_20_V3_HMER_WAND = 0x34010A95ull;
+
+static const uint64_t P9N2_C_20_V3_HMER_OR = 0x34010A91ull;
+
+static const uint64_t P9N2_C_21_V3_HMER_WAND = 0x35010A95ull;
+
+static const uint64_t P9N2_C_21_V3_HMER_OR = 0x35010A91ull;
+
+static const uint64_t P9N2_C_22_V3_HMER_WAND = 0x36010A95ull;
+
+static const uint64_t P9N2_C_22_V3_HMER_OR = 0x36010A91ull;
+
+static const uint64_t P9N2_C_23_V3_HMER_WAND = 0x37010A95ull;
+
+static const uint64_t P9N2_C_23_V3_HMER_OR = 0x37010A91ull;
+
+static const uint64_t P9N2_EX_0_L2_V3_HMER_WAND = 0x20010A95ull;
+//DUPS: 20010A95,
+static const uint64_t P9N2_EX_0_L2_V3_HMER_OR = 0x20010A91ull;
+//DUPS: 20010A91,
+static const uint64_t P9N2_EX_10_L2_V3_HMER_WAND = 0x34010A95ull;
+//DUPS: 34010A95,
+static const uint64_t P9N2_EX_10_L2_V3_HMER_OR = 0x34010A91ull;
+//DUPS: 34010A91,
+static const uint64_t P9N2_EX_11_L2_V3_HMER_WAND = 0x36010A95ull;
+//DUPS: 36010A95,
+static const uint64_t P9N2_EX_11_L2_V3_HMER_OR = 0x36010A91ull;
+//DUPS: 36010A91,
+static const uint64_t P9N2_EX_1_L2_V3_HMER_WAND = 0x22010A95ull;
+//DUPS: 22010A95,
+static const uint64_t P9N2_EX_1_L2_V3_HMER_OR = 0x22010A91ull;
+//DUPS: 22010A91,
+static const uint64_t P9N2_EX_2_L2_V3_HMER_WAND = 0x24010A95ull;
+//DUPS: 24010A95,
+static const uint64_t P9N2_EX_2_L2_V3_HMER_OR = 0x24010A91ull;
+//DUPS: 24010A91,
+static const uint64_t P9N2_EX_3_L2_V3_HMER_WAND = 0x26010A95ull;
+//DUPS: 26010A95,
+static const uint64_t P9N2_EX_3_L2_V3_HMER_OR = 0x26010A91ull;
+//DUPS: 26010A91,
+static const uint64_t P9N2_EX_4_L2_V3_HMER_WAND = 0x28010A95ull;
+//DUPS: 28010A95,
+static const uint64_t P9N2_EX_4_L2_V3_HMER_OR = 0x28010A91ull;
+//DUPS: 28010A91,
+static const uint64_t P9N2_EX_5_L2_V3_HMER_WAND = 0x2B010A95ull;
+//DUPS: 2A010A95,
+static const uint64_t P9N2_EX_5_L2_V3_HMER_OR = 0x2B010A91ull;
+//DUPS: 2A010A91,
+static const uint64_t P9N2_EX_6_L2_V3_HMER_WAND = 0x2D010A95ull;
+//DUPS: 2C010A95,
+static const uint64_t P9N2_EX_6_L2_V3_HMER_OR = 0x2D010A91ull;
+//DUPS: 2C010A91,
+static const uint64_t P9N2_EX_7_L2_V3_HMER_WAND = 0x2F010A95ull;
+//DUPS: 2E010A95,
+static const uint64_t P9N2_EX_7_L2_V3_HMER_OR = 0x2F010A91ull;
+//DUPS: 2E010A91,
+static const uint64_t P9N2_EX_8_L2_V3_HMER_WAND = 0x30010A95ull;
+//DUPS: 30010A95,
+static const uint64_t P9N2_EX_8_L2_V3_HMER_OR = 0x30010A91ull;
+//DUPS: 30010A91,
+static const uint64_t P9N2_EX_9_L2_V3_HMER_WAND = 0x32010A95ull;
+//DUPS: 32010A95,
+static const uint64_t P9N2_EX_9_L2_V3_HMER_OR = 0x32010A91ull;
+//DUPS: 32010A91,
+static const uint64_t P9N2_EX_L2_V3_HMER_WAND = 0x20010A95ull;
+//DUPS: 20010A95,
+static const uint64_t P9N2_EX_L2_V3_HMER_OR = 0x20010A91ull;
+//DUPS: 20010A91,
+
+static const uint64_t P9N2_C_VITAL_SCAN_OUT = 0x200F0017ull;
+
+static const uint64_t P9N2_C_0_VITAL_SCAN_OUT = 0x200F0017ull;
+
+static const uint64_t P9N2_C_1_VITAL_SCAN_OUT = 0x210F0017ull;
+
+static const uint64_t P9N2_C_2_VITAL_SCAN_OUT = 0x220F0017ull;
+
+static const uint64_t P9N2_C_3_VITAL_SCAN_OUT = 0x230F0017ull;
+
+static const uint64_t P9N2_C_4_VITAL_SCAN_OUT = 0x240F0017ull;
+
+static const uint64_t P9N2_C_5_VITAL_SCAN_OUT = 0x250F0017ull;
+
+static const uint64_t P9N2_C_6_VITAL_SCAN_OUT = 0x260F0017ull;
+
+static const uint64_t P9N2_C_7_VITAL_SCAN_OUT = 0x270F0017ull;
+
+static const uint64_t P9N2_C_8_VITAL_SCAN_OUT = 0x280F0017ull;
+
+static const uint64_t P9N2_C_9_VITAL_SCAN_OUT = 0x290F0017ull;
+
+static const uint64_t P9N2_C_10_VITAL_SCAN_OUT = 0x2A0F0017ull;
+
+static const uint64_t P9N2_C_11_VITAL_SCAN_OUT = 0x2B0F0017ull;
+
+static const uint64_t P9N2_C_12_VITAL_SCAN_OUT = 0x2C0F0017ull;
+
+static const uint64_t P9N2_C_13_VITAL_SCAN_OUT = 0x2D0F0017ull;
+
+static const uint64_t P9N2_C_14_VITAL_SCAN_OUT = 0x2E0F0017ull;
+
+static const uint64_t P9N2_C_15_VITAL_SCAN_OUT = 0x2F0F0017ull;
+
+static const uint64_t P9N2_C_16_VITAL_SCAN_OUT = 0x300F0017ull;
+
+static const uint64_t P9N2_C_17_VITAL_SCAN_OUT = 0x310F0017ull;
+
+static const uint64_t P9N2_C_18_VITAL_SCAN_OUT = 0x320F0017ull;
+
+static const uint64_t P9N2_C_19_VITAL_SCAN_OUT = 0x330F0017ull;
+
+static const uint64_t P9N2_C_20_VITAL_SCAN_OUT = 0x340F0017ull;
+
+static const uint64_t P9N2_C_21_VITAL_SCAN_OUT = 0x350F0017ull;
+
+static const uint64_t P9N2_C_22_VITAL_SCAN_OUT = 0x360F0017ull;
+
+static const uint64_t P9N2_C_23_VITAL_SCAN_OUT = 0x370F0017ull;
+
+static const uint64_t P9N2_EQ_VITAL_SCAN_OUT = 0x100F0017ull;
+
+static const uint64_t P9N2_EQ_0_VITAL_SCAN_OUT = 0x100F0017ull;
+
+static const uint64_t P9N2_EQ_1_VITAL_SCAN_OUT = 0x110F0017ull;
+
+static const uint64_t P9N2_EQ_2_VITAL_SCAN_OUT = 0x120F0017ull;
+
+static const uint64_t P9N2_EQ_3_VITAL_SCAN_OUT = 0x130F0017ull;
+
+static const uint64_t P9N2_EQ_4_VITAL_SCAN_OUT = 0x140F0017ull;
+
+static const uint64_t P9N2_EQ_5_VITAL_SCAN_OUT = 0x150F0017ull;
+
+static const uint64_t P9N2_EX_VITAL_SCAN_OUT = 0x200F0017ull;
+//DUPS: 210F0017,
+static const uint64_t P9N2_EX_0_VITAL_SCAN_OUT = 0x200F0017ull;
+//DUPS: 210F0017,
+static const uint64_t P9N2_EX_1_VITAL_SCAN_OUT = 0x220F0017ull;
+//DUPS: 220F0017,
+static const uint64_t P9N2_EX_2_VITAL_SCAN_OUT = 0x240F0017ull;
+//DUPS: 250F0017,
+static const uint64_t P9N2_EX_3_VITAL_SCAN_OUT = 0x260F0017ull;
+//DUPS: 270F0017,
+static const uint64_t P9N2_EX_4_VITAL_SCAN_OUT = 0x280F0017ull;
+//DUPS: 290F0017,
+static const uint64_t P9N2_EX_5_VITAL_SCAN_OUT = 0x2A0F0017ull;
+//DUPS: 2B0F0017,
+static const uint64_t P9N2_EX_6_VITAL_SCAN_OUT = 0x2C0F0017ull;
+//DUPS: 2D0F0017,
+static const uint64_t P9N2_EX_7_VITAL_SCAN_OUT = 0x2E0F0017ull;
+//DUPS: 2F0F0017,
+static const uint64_t P9N2_EX_8_VITAL_SCAN_OUT = 0x300F0017ull;
+//DUPS: 310F0017,
+static const uint64_t P9N2_EX_9_VITAL_SCAN_OUT = 0x320F0017ull;
+//DUPS: 330F0017,
+static const uint64_t P9N2_EX_10_VITAL_SCAN_OUT = 0x340F0017ull;
+//DUPS: 350F0017,
+static const uint64_t P9N2_EX_11_VITAL_SCAN_OUT = 0x360F0017ull;
+//DUPS: 370F0017,
+
+static const uint64_t P9N2_C_WRITE_PROTECT_ENABLE_REG = 0x20010005ull;
+
+static const uint64_t P9N2_C_0_WRITE_PROTECT_ENABLE_REG = 0x20010005ull;
+
+static const uint64_t P9N2_C_1_WRITE_PROTECT_ENABLE_REG = 0x21010005ull;
+
+static const uint64_t P9N2_C_2_WRITE_PROTECT_ENABLE_REG = 0x22010005ull;
+
+static const uint64_t P9N2_C_3_WRITE_PROTECT_ENABLE_REG = 0x23010005ull;
+
+static const uint64_t P9N2_C_4_WRITE_PROTECT_ENABLE_REG = 0x24010005ull;
+
+static const uint64_t P9N2_C_5_WRITE_PROTECT_ENABLE_REG = 0x25010005ull;
+
+static const uint64_t P9N2_C_6_WRITE_PROTECT_ENABLE_REG = 0x26010005ull;
+
+static const uint64_t P9N2_C_7_WRITE_PROTECT_ENABLE_REG = 0x27010005ull;
+
+static const uint64_t P9N2_C_8_WRITE_PROTECT_ENABLE_REG = 0x28010005ull;
+
+static const uint64_t P9N2_C_9_WRITE_PROTECT_ENABLE_REG = 0x29010005ull;
+
+static const uint64_t P9N2_C_10_WRITE_PROTECT_ENABLE_REG = 0x2A010005ull;
+
+static const uint64_t P9N2_C_11_WRITE_PROTECT_ENABLE_REG = 0x2B010005ull;
+
+static const uint64_t P9N2_C_12_WRITE_PROTECT_ENABLE_REG = 0x2C010005ull;
+
+static const uint64_t P9N2_C_13_WRITE_PROTECT_ENABLE_REG = 0x2D010005ull;
+
+static const uint64_t P9N2_C_14_WRITE_PROTECT_ENABLE_REG = 0x2E010005ull;
+
+static const uint64_t P9N2_C_15_WRITE_PROTECT_ENABLE_REG = 0x2F010005ull;
+
+static const uint64_t P9N2_C_16_WRITE_PROTECT_ENABLE_REG = 0x30010005ull;
+
+static const uint64_t P9N2_C_17_WRITE_PROTECT_ENABLE_REG = 0x31010005ull;
+
+static const uint64_t P9N2_C_18_WRITE_PROTECT_ENABLE_REG = 0x32010005ull;
+
+static const uint64_t P9N2_C_19_WRITE_PROTECT_ENABLE_REG = 0x33010005ull;
+
+static const uint64_t P9N2_C_20_WRITE_PROTECT_ENABLE_REG = 0x34010005ull;
+
+static const uint64_t P9N2_C_21_WRITE_PROTECT_ENABLE_REG = 0x35010005ull;
+
+static const uint64_t P9N2_C_22_WRITE_PROTECT_ENABLE_REG = 0x36010005ull;
+
+static const uint64_t P9N2_C_23_WRITE_PROTECT_ENABLE_REG = 0x37010005ull;
+
+static const uint64_t P9N2_EQ_WRITE_PROTECT_ENABLE_REG = 0x10010005ull;
+
+static const uint64_t P9N2_EQ_0_WRITE_PROTECT_ENABLE_REG = 0x10010005ull;
+
+static const uint64_t P9N2_EQ_1_WRITE_PROTECT_ENABLE_REG = 0x11010005ull;
+
+static const uint64_t P9N2_EQ_2_WRITE_PROTECT_ENABLE_REG = 0x12010005ull;
+
+static const uint64_t P9N2_EQ_3_WRITE_PROTECT_ENABLE_REG = 0x13010005ull;
+
+static const uint64_t P9N2_EQ_4_WRITE_PROTECT_ENABLE_REG = 0x14010005ull;
+
+static const uint64_t P9N2_EQ_5_WRITE_PROTECT_ENABLE_REG = 0x15010005ull;
+
+static const uint64_t P9N2_EX_WRITE_PROTECT_ENABLE_REG = 0x20010005ull;
+//DUPS: 21010005,
+static const uint64_t P9N2_EX_0_WRITE_PROTECT_ENABLE_REG = 0x20010005ull;
+//DUPS: 21010005,
+static const uint64_t P9N2_EX_1_WRITE_PROTECT_ENABLE_REG = 0x22010005ull;
+//DUPS: 23010005,
+static const uint64_t P9N2_EX_2_WRITE_PROTECT_ENABLE_REG = 0x24010005ull;
+//DUPS: 25010005,
+static const uint64_t P9N2_EX_3_WRITE_PROTECT_ENABLE_REG = 0x26010005ull;
+//DUPS: 27010005,
+static const uint64_t P9N2_EX_4_WRITE_PROTECT_ENABLE_REG = 0x28010005ull;
+//DUPS: 29010005,
+static const uint64_t P9N2_EX_5_WRITE_PROTECT_ENABLE_REG = 0x2A010005ull;
+//DUPS: 2B010005,
+static const uint64_t P9N2_EX_6_WRITE_PROTECT_ENABLE_REG = 0x2C010005ull;
+//DUPS: 2D010005,
+static const uint64_t P9N2_EX_7_WRITE_PROTECT_ENABLE_REG = 0x2F010005ull;
+//DUPS: 2F010005,
+static const uint64_t P9N2_EX_8_WRITE_PROTECT_ENABLE_REG = 0x30010005ull;
+//DUPS: 31010005,
+static const uint64_t P9N2_EX_9_WRITE_PROTECT_ENABLE_REG = 0x32010005ull;
+//DUPS: 33010005,
+static const uint64_t P9N2_EX_10_WRITE_PROTECT_ENABLE_REG = 0x34010005ull;
+//DUPS: 35010005,
+static const uint64_t P9N2_EX_11_WRITE_PROTECT_ENABLE_REG = 0x36010005ull;
+//DUPS: 37010005,
+
+static const uint64_t P9N2_C_WRITE_PROTECT_RINGS_REG = 0x20010006ull;
+
+static const uint64_t P9N2_C_0_WRITE_PROTECT_RINGS_REG = 0x20010006ull;
+
+static const uint64_t P9N2_C_1_WRITE_PROTECT_RINGS_REG = 0x21010006ull;
+
+static const uint64_t P9N2_C_2_WRITE_PROTECT_RINGS_REG = 0x22010006ull;
+
+static const uint64_t P9N2_C_3_WRITE_PROTECT_RINGS_REG = 0x23010006ull;
+
+static const uint64_t P9N2_C_4_WRITE_PROTECT_RINGS_REG = 0x24010006ull;
+
+static const uint64_t P9N2_C_5_WRITE_PROTECT_RINGS_REG = 0x25010006ull;
+
+static const uint64_t P9N2_C_6_WRITE_PROTECT_RINGS_REG = 0x26010006ull;
+
+static const uint64_t P9N2_C_7_WRITE_PROTECT_RINGS_REG = 0x27010006ull;
+
+static const uint64_t P9N2_C_8_WRITE_PROTECT_RINGS_REG = 0x28010006ull;
+
+static const uint64_t P9N2_C_9_WRITE_PROTECT_RINGS_REG = 0x29010006ull;
+
+static const uint64_t P9N2_C_10_WRITE_PROTECT_RINGS_REG = 0x2A010006ull;
+
+static const uint64_t P9N2_C_11_WRITE_PROTECT_RINGS_REG = 0x2B010006ull;
+
+static const uint64_t P9N2_C_12_WRITE_PROTECT_RINGS_REG = 0x2C010006ull;
+
+static const uint64_t P9N2_C_13_WRITE_PROTECT_RINGS_REG = 0x2D010006ull;
+
+static const uint64_t P9N2_C_14_WRITE_PROTECT_RINGS_REG = 0x2E010006ull;
+
+static const uint64_t P9N2_C_15_WRITE_PROTECT_RINGS_REG = 0x2F010006ull;
+
+static const uint64_t P9N2_C_16_WRITE_PROTECT_RINGS_REG = 0x30010006ull;
+
+static const uint64_t P9N2_C_17_WRITE_PROTECT_RINGS_REG = 0x31010006ull;
+
+static const uint64_t P9N2_C_18_WRITE_PROTECT_RINGS_REG = 0x32010006ull;
+
+static const uint64_t P9N2_C_19_WRITE_PROTECT_RINGS_REG = 0x33010006ull;
+
+static const uint64_t P9N2_C_20_WRITE_PROTECT_RINGS_REG = 0x34010006ull;
+
+static const uint64_t P9N2_C_21_WRITE_PROTECT_RINGS_REG = 0x35010006ull;
+
+static const uint64_t P9N2_C_22_WRITE_PROTECT_RINGS_REG = 0x36010006ull;
+
+static const uint64_t P9N2_C_23_WRITE_PROTECT_RINGS_REG = 0x37010006ull;
+
+static const uint64_t P9N2_EQ_WRITE_PROTECT_RINGS_REG = 0x10010006ull;
+
+static const uint64_t P9N2_EQ_0_WRITE_PROTECT_RINGS_REG = 0x10010006ull;
+
+static const uint64_t P9N2_EQ_1_WRITE_PROTECT_RINGS_REG = 0x11010006ull;
+
+static const uint64_t P9N2_EQ_2_WRITE_PROTECT_RINGS_REG = 0x12010006ull;
+
+static const uint64_t P9N2_EQ_3_WRITE_PROTECT_RINGS_REG = 0x13010006ull;
+
+static const uint64_t P9N2_EQ_4_WRITE_PROTECT_RINGS_REG = 0x14010006ull;
+
+static const uint64_t P9N2_EQ_5_WRITE_PROTECT_RINGS_REG = 0x15010006ull;
+
+static const uint64_t P9N2_EX_WRITE_PROTECT_RINGS_REG = 0x20010006ull;
+//DUPS: 21010006,
+static const uint64_t P9N2_EX_0_WRITE_PROTECT_RINGS_REG = 0x20010006ull;
+//DUPS: 21010006,
+static const uint64_t P9N2_EX_1_WRITE_PROTECT_RINGS_REG = 0x22010006ull;
+//DUPS: 23010006,
+static const uint64_t P9N2_EX_2_WRITE_PROTECT_RINGS_REG = 0x24010006ull;
+//DUPS: 25010006,
+static const uint64_t P9N2_EX_3_WRITE_PROTECT_RINGS_REG = 0x26010006ull;
+//DUPS: 27010006,
+static const uint64_t P9N2_EX_4_WRITE_PROTECT_RINGS_REG = 0x28010006ull;
+//DUPS: 29010006,
+static const uint64_t P9N2_EX_5_WRITE_PROTECT_RINGS_REG = 0x2A010006ull;
+//DUPS: 2B010006,
+static const uint64_t P9N2_EX_6_WRITE_PROTECT_RINGS_REG = 0x2C010006ull;
+//DUPS: 2D010006,
+static const uint64_t P9N2_EX_7_WRITE_PROTECT_RINGS_REG = 0x2F010006ull;
+//DUPS: 2F010006,
+static const uint64_t P9N2_EX_8_WRITE_PROTECT_RINGS_REG = 0x30010006ull;
+//DUPS: 31010006,
+static const uint64_t P9N2_EX_9_WRITE_PROTECT_RINGS_REG = 0x32010006ull;
+//DUPS: 33010006,
+static const uint64_t P9N2_EX_10_WRITE_PROTECT_RINGS_REG = 0x34010006ull;
+//DUPS: 35010006,
+static const uint64_t P9N2_EX_11_WRITE_PROTECT_RINGS_REG = 0x36010006ull;
+//DUPS: 37010006,
+
+static const uint64_t P9N2_EQ_WR_EPS_REG = 0x10010C11ull;
+//DUPS: 10010C11,
+static const uint64_t P9N2_EQ_0_WR_EPS_REG = 0x10010C11ull;
+//DUPS: 10010C11,
+static const uint64_t P9N2_EQ_1_WR_EPS_REG = 0x11010C11ull;
+//DUPS: 11010C11,
+static const uint64_t P9N2_EQ_2_WR_EPS_REG = 0x12010C11ull;
+//DUPS: 12010C11,
+static const uint64_t P9N2_EQ_3_WR_EPS_REG = 0x13010C11ull;
+//DUPS: 13010C11,
+static const uint64_t P9N2_EQ_4_WR_EPS_REG = 0x14010C11ull;
+//DUPS: 14010C11,
+static const uint64_t P9N2_EQ_5_WR_EPS_REG = 0x15010C11ull;
+//DUPS: 15010C11,
+static const uint64_t P9N2_EX_0_L2_WR_EPS_REG = 0x10010811ull;
+
+static const uint64_t P9N2_EX_10_L2_WR_EPS_REG = 0x15010811ull;
+
+static const uint64_t P9N2_EX_11_L2_WR_EPS_REG = 0x15010C11ull;
+
+static const uint64_t P9N2_EX_1_L2_WR_EPS_REG = 0x10010C11ull;
+
+static const uint64_t P9N2_EX_2_L2_WR_EPS_REG = 0x11010811ull;
+
+static const uint64_t P9N2_EX_3_L2_WR_EPS_REG = 0x11010C11ull;
+
+static const uint64_t P9N2_EX_4_L2_WR_EPS_REG = 0x12010811ull;
+
+static const uint64_t P9N2_EX_5_L2_WR_EPS_REG = 0x12010C11ull;
+
+static const uint64_t P9N2_EX_6_L2_WR_EPS_REG = 0x13010811ull;
+
+static const uint64_t P9N2_EX_7_L2_WR_EPS_REG = 0x13010C11ull;
+
+static const uint64_t P9N2_EX_8_L2_WR_EPS_REG = 0x14010811ull;
+
+static const uint64_t P9N2_EX_9_L2_WR_EPS_REG = 0x14010C11ull;
+
+static const uint64_t P9N2_EX_L2_WR_EPS_REG = 0x10010811ull;
+
+
+static const uint64_t P9N2_C_XFIR = 0x20040000ull;
+
+static const uint64_t P9N2_C_0_XFIR = 0x20040000ull;
+
+static const uint64_t P9N2_C_1_XFIR = 0x21040000ull;
+
+static const uint64_t P9N2_C_2_XFIR = 0x22040000ull;
+
+static const uint64_t P9N2_C_3_XFIR = 0x23040000ull;
+
+static const uint64_t P9N2_C_4_XFIR = 0x24040000ull;
+
+static const uint64_t P9N2_C_5_XFIR = 0x25040000ull;
+
+static const uint64_t P9N2_C_6_XFIR = 0x26040000ull;
+
+static const uint64_t P9N2_C_7_XFIR = 0x27040000ull;
+
+static const uint64_t P9N2_C_8_XFIR = 0x28040000ull;
+
+static const uint64_t P9N2_C_9_XFIR = 0x29040000ull;
+
+static const uint64_t P9N2_C_10_XFIR = 0x2A040000ull;
+
+static const uint64_t P9N2_C_11_XFIR = 0x2B040000ull;
+
+static const uint64_t P9N2_C_12_XFIR = 0x2C040000ull;
+
+static const uint64_t P9N2_C_13_XFIR = 0x2D040000ull;
+
+static const uint64_t P9N2_C_14_XFIR = 0x2E040000ull;
+
+static const uint64_t P9N2_C_15_XFIR = 0x2F040000ull;
+
+static const uint64_t P9N2_C_16_XFIR = 0x30040000ull;
+
+static const uint64_t P9N2_C_17_XFIR = 0x31040000ull;
+
+static const uint64_t P9N2_C_18_XFIR = 0x32040000ull;
+
+static const uint64_t P9N2_C_19_XFIR = 0x33040000ull;
+
+static const uint64_t P9N2_C_20_XFIR = 0x34040000ull;
+
+static const uint64_t P9N2_C_21_XFIR = 0x35040000ull;
+
+static const uint64_t P9N2_C_22_XFIR = 0x36040000ull;
+
+static const uint64_t P9N2_C_23_XFIR = 0x37040000ull;
+
+static const uint64_t P9N2_EQ_XFIR = 0x10040000ull;
+
+static const uint64_t P9N2_EQ_0_XFIR = 0x10040000ull;
+
+static const uint64_t P9N2_EQ_1_XFIR = 0x11040000ull;
+
+static const uint64_t P9N2_EQ_2_XFIR = 0x12040000ull;
+
+static const uint64_t P9N2_EQ_3_XFIR = 0x13040000ull;
+
+static const uint64_t P9N2_EQ_4_XFIR = 0x14040000ull;
+
+static const uint64_t P9N2_EQ_5_XFIR = 0x15040000ull;
+
+static const uint64_t P9N2_EX_XFIR = 0x20040000ull;
+//DUPS: 21040000,
+static const uint64_t P9N2_EX_0_XFIR = 0x20040000ull;
+//DUPS: 21040000,
+static const uint64_t P9N2_EX_1_XFIR = 0x22040000ull;
+//DUPS: 23040000,
+static const uint64_t P9N2_EX_2_XFIR = 0x24040000ull;
+//DUPS: 25040000,
+static const uint64_t P9N2_EX_3_XFIR = 0x26040000ull;
+//DUPS: 27040000,
+static const uint64_t P9N2_EX_4_XFIR = 0x28040000ull;
+//DUPS: 29040000,
+static const uint64_t P9N2_EX_5_XFIR = 0x2A040000ull;
+//DUPS: 2B040000,
+static const uint64_t P9N2_EX_6_XFIR = 0x2C040000ull;
+//DUPS: 2D040000,
+static const uint64_t P9N2_EX_7_XFIR = 0x2F040000ull;
+//DUPS: 2F040000,
+static const uint64_t P9N2_EX_8_XFIR = 0x30040000ull;
+//DUPS: 31040000,
+static const uint64_t P9N2_EX_9_XFIR = 0x32040000ull;
+//DUPS: 33040000,
+static const uint64_t P9N2_EX_10_XFIR = 0x34040000ull;
+//DUPS: 35040000,
+static const uint64_t P9N2_EX_11_XFIR = 0x36040000ull;
+//DUPS: 37040000,
+
+static const uint64_t P9N2_C_XSTOP1 = 0x2003000Cull;
+
+static const uint64_t P9N2_C_0_XSTOP1 = 0x2003000Cull;
+
+static const uint64_t P9N2_C_1_XSTOP1 = 0x2103000Cull;
+
+static const uint64_t P9N2_C_2_XSTOP1 = 0x2203000Cull;
+
+static const uint64_t P9N2_C_3_XSTOP1 = 0x2303000Cull;
+
+static const uint64_t P9N2_C_4_XSTOP1 = 0x2403000Cull;
+
+static const uint64_t P9N2_C_5_XSTOP1 = 0x2503000Cull;
+
+static const uint64_t P9N2_C_6_XSTOP1 = 0x2603000Cull;
+
+static const uint64_t P9N2_C_7_XSTOP1 = 0x2703000Cull;
+
+static const uint64_t P9N2_C_8_XSTOP1 = 0x2803000Cull;
+
+static const uint64_t P9N2_C_9_XSTOP1 = 0x2903000Cull;
+
+static const uint64_t P9N2_C_10_XSTOP1 = 0x2A03000Cull;
+
+static const uint64_t P9N2_C_11_XSTOP1 = 0x2B03000Cull;
+
+static const uint64_t P9N2_C_12_XSTOP1 = 0x2C03000Cull;
+
+static const uint64_t P9N2_C_13_XSTOP1 = 0x2D03000Cull;
+
+static const uint64_t P9N2_C_14_XSTOP1 = 0x2E03000Cull;
+
+static const uint64_t P9N2_C_15_XSTOP1 = 0x2F03000Cull;
+
+static const uint64_t P9N2_C_16_XSTOP1 = 0x3003000Cull;
+
+static const uint64_t P9N2_C_17_XSTOP1 = 0x3103000Cull;
+
+static const uint64_t P9N2_C_18_XSTOP1 = 0x3203000Cull;
+
+static const uint64_t P9N2_C_19_XSTOP1 = 0x3303000Cull;
+
+static const uint64_t P9N2_C_20_XSTOP1 = 0x3403000Cull;
+
+static const uint64_t P9N2_C_21_XSTOP1 = 0x3503000Cull;
+
+static const uint64_t P9N2_C_22_XSTOP1 = 0x3603000Cull;
+
+static const uint64_t P9N2_C_23_XSTOP1 = 0x3703000Cull;
+
+static const uint64_t P9N2_EQ_XSTOP1 = 0x1003000Cull;
+
+static const uint64_t P9N2_EQ_0_XSTOP1 = 0x1003000Cull;
+
+static const uint64_t P9N2_EQ_1_XSTOP1 = 0x1103000Cull;
+
+static const uint64_t P9N2_EQ_2_XSTOP1 = 0x1203000Cull;
+
+static const uint64_t P9N2_EQ_3_XSTOP1 = 0x1303000Cull;
+
+static const uint64_t P9N2_EQ_4_XSTOP1 = 0x1403000Cull;
+
+static const uint64_t P9N2_EQ_5_XSTOP1 = 0x1503000Cull;
+
+static const uint64_t P9N2_EX_XSTOP1 = 0x2003000Cull;
+//DUPS: 2103000C,
+static const uint64_t P9N2_EX_0_XSTOP1 = 0x2003000Cull;
+//DUPS: 2103000C,
+static const uint64_t P9N2_EX_1_XSTOP1 = 0x2203000Cull;
+//DUPS: 2303000C,
+static const uint64_t P9N2_EX_2_XSTOP1 = 0x2403000Cull;
+//DUPS: 2503000C,
+static const uint64_t P9N2_EX_3_XSTOP1 = 0x2603000Cull;
+//DUPS: 2703000C,
+static const uint64_t P9N2_EX_4_XSTOP1 = 0x2803000Cull;
+//DUPS: 2903000C,
+static const uint64_t P9N2_EX_5_XSTOP1 = 0x2A03000Cull;
+//DUPS: 2B03000C,
+static const uint64_t P9N2_EX_6_XSTOP1 = 0x2C03000Cull;
+//DUPS: 2D03000C,
+static const uint64_t P9N2_EX_7_XSTOP1 = 0x2F03000Cull;
+//DUPS: 2F03000C,
+static const uint64_t P9N2_EX_8_XSTOP1 = 0x3003000Cull;
+//DUPS: 3103000C,
+static const uint64_t P9N2_EX_9_XSTOP1 = 0x3203000Cull;
+//DUPS: 3303000C,
+static const uint64_t P9N2_EX_10_XSTOP1 = 0x3403000Cull;
+//DUPS: 3503000C,
+static const uint64_t P9N2_EX_11_XSTOP1 = 0x3603000Cull;
+//DUPS: 3703000C,
+
+static const uint64_t P9N2_C_XSTOP2 = 0x2003000Dull;
+
+static const uint64_t P9N2_C_0_XSTOP2 = 0x2003000Dull;
+
+static const uint64_t P9N2_C_1_XSTOP2 = 0x2103000Dull;
+
+static const uint64_t P9N2_C_2_XSTOP2 = 0x2203000Dull;
+
+static const uint64_t P9N2_C_3_XSTOP2 = 0x2303000Dull;
+
+static const uint64_t P9N2_C_4_XSTOP2 = 0x2403000Dull;
+
+static const uint64_t P9N2_C_5_XSTOP2 = 0x2503000Dull;
+
+static const uint64_t P9N2_C_6_XSTOP2 = 0x2603000Dull;
+
+static const uint64_t P9N2_C_7_XSTOP2 = 0x2703000Dull;
+
+static const uint64_t P9N2_C_8_XSTOP2 = 0x2803000Dull;
+
+static const uint64_t P9N2_C_9_XSTOP2 = 0x2903000Dull;
+
+static const uint64_t P9N2_C_10_XSTOP2 = 0x2A03000Dull;
+
+static const uint64_t P9N2_C_11_XSTOP2 = 0x2B03000Dull;
+
+static const uint64_t P9N2_C_12_XSTOP2 = 0x2C03000Dull;
+
+static const uint64_t P9N2_C_13_XSTOP2 = 0x2D03000Dull;
+
+static const uint64_t P9N2_C_14_XSTOP2 = 0x2E03000Dull;
+
+static const uint64_t P9N2_C_15_XSTOP2 = 0x2F03000Dull;
+
+static const uint64_t P9N2_C_16_XSTOP2 = 0x3003000Dull;
+
+static const uint64_t P9N2_C_17_XSTOP2 = 0x3103000Dull;
+
+static const uint64_t P9N2_C_18_XSTOP2 = 0x3203000Dull;
+
+static const uint64_t P9N2_C_19_XSTOP2 = 0x3303000Dull;
+
+static const uint64_t P9N2_C_20_XSTOP2 = 0x3403000Dull;
+
+static const uint64_t P9N2_C_21_XSTOP2 = 0x3503000Dull;
+
+static const uint64_t P9N2_C_22_XSTOP2 = 0x3603000Dull;
+
+static const uint64_t P9N2_C_23_XSTOP2 = 0x3703000Dull;
+
+static const uint64_t P9N2_EQ_XSTOP2 = 0x1003000Dull;
+
+static const uint64_t P9N2_EQ_0_XSTOP2 = 0x1003000Dull;
+
+static const uint64_t P9N2_EQ_1_XSTOP2 = 0x1103000Dull;
+
+static const uint64_t P9N2_EQ_2_XSTOP2 = 0x1203000Dull;
+
+static const uint64_t P9N2_EQ_3_XSTOP2 = 0x1303000Dull;
+
+static const uint64_t P9N2_EQ_4_XSTOP2 = 0x1403000Dull;
+
+static const uint64_t P9N2_EQ_5_XSTOP2 = 0x1503000Dull;
+
+static const uint64_t P9N2_EX_XSTOP2 = 0x2003000Dull;
+//DUPS: 2103000D,
+static const uint64_t P9N2_EX_0_XSTOP2 = 0x2003000Dull;
+//DUPS: 2103000D,
+static const uint64_t P9N2_EX_1_XSTOP2 = 0x2203000Dull;
+//DUPS: 2303000D,
+static const uint64_t P9N2_EX_2_XSTOP2 = 0x2403000Dull;
+//DUPS: 2503000D,
+static const uint64_t P9N2_EX_3_XSTOP2 = 0x2603000Dull;
+//DUPS: 2703000D,
+static const uint64_t P9N2_EX_4_XSTOP2 = 0x2803000Dull;
+//DUPS: 2903000D,
+static const uint64_t P9N2_EX_5_XSTOP2 = 0x2A03000Dull;
+//DUPS: 2B03000D,
+static const uint64_t P9N2_EX_6_XSTOP2 = 0x2C03000Dull;
+//DUPS: 2D03000D,
+static const uint64_t P9N2_EX_7_XSTOP2 = 0x2F03000Dull;
+//DUPS: 2F03000D,
+static const uint64_t P9N2_EX_8_XSTOP2 = 0x3003000Dull;
+//DUPS: 3103000D,
+static const uint64_t P9N2_EX_9_XSTOP2 = 0x3203000Dull;
+//DUPS: 3303000D,
+static const uint64_t P9N2_EX_10_XSTOP2 = 0x3403000Dull;
+//DUPS: 3503000D,
+static const uint64_t P9N2_EX_11_XSTOP2 = 0x3603000Dull;
+//DUPS: 3703000D,
+
+static const uint64_t P9N2_C_XSTOP3 = 0x2003000Eull;
+
+static const uint64_t P9N2_C_0_XSTOP3 = 0x2003000Eull;
+
+static const uint64_t P9N2_C_1_XSTOP3 = 0x2103000Eull;
+
+static const uint64_t P9N2_C_2_XSTOP3 = 0x2203000Eull;
+
+static const uint64_t P9N2_C_3_XSTOP3 = 0x2303000Eull;
+
+static const uint64_t P9N2_C_4_XSTOP3 = 0x2403000Eull;
+
+static const uint64_t P9N2_C_5_XSTOP3 = 0x2503000Eull;
+
+static const uint64_t P9N2_C_6_XSTOP3 = 0x2603000Eull;
+
+static const uint64_t P9N2_C_7_XSTOP3 = 0x2703000Eull;
+
+static const uint64_t P9N2_C_8_XSTOP3 = 0x2803000Eull;
+
+static const uint64_t P9N2_C_9_XSTOP3 = 0x2903000Eull;
+
+static const uint64_t P9N2_C_10_XSTOP3 = 0x2A03000Eull;
+
+static const uint64_t P9N2_C_11_XSTOP3 = 0x2B03000Eull;
+
+static const uint64_t P9N2_C_12_XSTOP3 = 0x2C03000Eull;
+
+static const uint64_t P9N2_C_13_XSTOP3 = 0x2D03000Eull;
+
+static const uint64_t P9N2_C_14_XSTOP3 = 0x2E03000Eull;
+
+static const uint64_t P9N2_C_15_XSTOP3 = 0x2F03000Eull;
+
+static const uint64_t P9N2_C_16_XSTOP3 = 0x3003000Eull;
+
+static const uint64_t P9N2_C_17_XSTOP3 = 0x3103000Eull;
+
+static const uint64_t P9N2_C_18_XSTOP3 = 0x3203000Eull;
+
+static const uint64_t P9N2_C_19_XSTOP3 = 0x3303000Eull;
+
+static const uint64_t P9N2_C_20_XSTOP3 = 0x3403000Eull;
+
+static const uint64_t P9N2_C_21_XSTOP3 = 0x3503000Eull;
+
+static const uint64_t P9N2_C_22_XSTOP3 = 0x3603000Eull;
+
+static const uint64_t P9N2_C_23_XSTOP3 = 0x3703000Eull;
+
+static const uint64_t P9N2_EQ_XSTOP3 = 0x1003000Eull;
+
+static const uint64_t P9N2_EQ_0_XSTOP3 = 0x1003000Eull;
+
+static const uint64_t P9N2_EQ_1_XSTOP3 = 0x1103000Eull;
+
+static const uint64_t P9N2_EQ_2_XSTOP3 = 0x1203000Eull;
+
+static const uint64_t P9N2_EQ_3_XSTOP3 = 0x1303000Eull;
+
+static const uint64_t P9N2_EQ_4_XSTOP3 = 0x1403000Eull;
+
+static const uint64_t P9N2_EQ_5_XSTOP3 = 0x1503000Eull;
+
+static const uint64_t P9N2_EX_XSTOP3 = 0x2003000Eull;
+//DUPS: 2103000E,
+static const uint64_t P9N2_EX_0_XSTOP3 = 0x2003000Eull;
+//DUPS: 2103000E,
+static const uint64_t P9N2_EX_1_XSTOP3 = 0x2203000Eull;
+//DUPS: 2303000E,
+static const uint64_t P9N2_EX_2_XSTOP3 = 0x2403000Eull;
+//DUPS: 2503000E,
+static const uint64_t P9N2_EX_3_XSTOP3 = 0x2603000Eull;
+//DUPS: 2703000E,
+static const uint64_t P9N2_EX_4_XSTOP3 = 0x2803000Eull;
+//DUPS: 2903000E,
+static const uint64_t P9N2_EX_5_XSTOP3 = 0x2A03000Eull;
+//DUPS: 2B03000E,
+static const uint64_t P9N2_EX_6_XSTOP3 = 0x2C03000Eull;
+//DUPS: 2D03000E,
+static const uint64_t P9N2_EX_7_XSTOP3 = 0x2F03000Eull;
+//DUPS: 2F03000E,
+static const uint64_t P9N2_EX_8_XSTOP3 = 0x3003000Eull;
+//DUPS: 3103000E,
+static const uint64_t P9N2_EX_9_XSTOP3 = 0x3203000Eull;
+//DUPS: 3303000E,
+static const uint64_t P9N2_EX_10_XSTOP3 = 0x3403000Eull;
+//DUPS: 3503000E,
+static const uint64_t P9N2_EX_11_XSTOP3 = 0x3603000Eull;
+//DUPS: 3703000E,
+
+static const uint64_t P9N2_C_XSTOP_INTERRUPT_REG = 0x200F001Cull;
+
+static const uint64_t P9N2_C_0_XSTOP_INTERRUPT_REG = 0x200F001Cull;
+
+static const uint64_t P9N2_C_1_XSTOP_INTERRUPT_REG = 0x210F001Cull;
+
+static const uint64_t P9N2_C_2_XSTOP_INTERRUPT_REG = 0x220F001Cull;
+
+static const uint64_t P9N2_C_3_XSTOP_INTERRUPT_REG = 0x230F001Cull;
+
+static const uint64_t P9N2_C_4_XSTOP_INTERRUPT_REG = 0x240F001Cull;
+
+static const uint64_t P9N2_C_5_XSTOP_INTERRUPT_REG = 0x250F001Cull;
+
+static const uint64_t P9N2_C_6_XSTOP_INTERRUPT_REG = 0x260F001Cull;
+
+static const uint64_t P9N2_C_7_XSTOP_INTERRUPT_REG = 0x270F001Cull;
+
+static const uint64_t P9N2_C_8_XSTOP_INTERRUPT_REG = 0x280F001Cull;
+
+static const uint64_t P9N2_C_9_XSTOP_INTERRUPT_REG = 0x290F001Cull;
+
+static const uint64_t P9N2_C_10_XSTOP_INTERRUPT_REG = 0x2A0F001Cull;
+
+static const uint64_t P9N2_C_11_XSTOP_INTERRUPT_REG = 0x2B0F001Cull;
+
+static const uint64_t P9N2_C_12_XSTOP_INTERRUPT_REG = 0x2C0F001Cull;
+
+static const uint64_t P9N2_C_13_XSTOP_INTERRUPT_REG = 0x2D0F001Cull;
+
+static const uint64_t P9N2_C_14_XSTOP_INTERRUPT_REG = 0x2E0F001Cull;
+
+static const uint64_t P9N2_C_15_XSTOP_INTERRUPT_REG = 0x2F0F001Cull;
+
+static const uint64_t P9N2_C_16_XSTOP_INTERRUPT_REG = 0x300F001Cull;
+
+static const uint64_t P9N2_C_17_XSTOP_INTERRUPT_REG = 0x310F001Cull;
+
+static const uint64_t P9N2_C_18_XSTOP_INTERRUPT_REG = 0x320F001Cull;
+
+static const uint64_t P9N2_C_19_XSTOP_INTERRUPT_REG = 0x330F001Cull;
+
+static const uint64_t P9N2_C_20_XSTOP_INTERRUPT_REG = 0x340F001Cull;
+
+static const uint64_t P9N2_C_21_XSTOP_INTERRUPT_REG = 0x350F001Cull;
+
+static const uint64_t P9N2_C_22_XSTOP_INTERRUPT_REG = 0x360F001Cull;
+
+static const uint64_t P9N2_C_23_XSTOP_INTERRUPT_REG = 0x370F001Cull;
+
+static const uint64_t P9N2_EQ_XSTOP_INTERRUPT_REG = 0x100F001Cull;
+
+static const uint64_t P9N2_EQ_0_XSTOP_INTERRUPT_REG = 0x100F001Cull;
+
+static const uint64_t P9N2_EQ_1_XSTOP_INTERRUPT_REG = 0x110F001Cull;
+
+static const uint64_t P9N2_EQ_2_XSTOP_INTERRUPT_REG = 0x120F001Cull;
+
+static const uint64_t P9N2_EQ_3_XSTOP_INTERRUPT_REG = 0x130F001Cull;
+
+static const uint64_t P9N2_EQ_4_XSTOP_INTERRUPT_REG = 0x140F001Cull;
+
+static const uint64_t P9N2_EQ_5_XSTOP_INTERRUPT_REG = 0x150F001Cull;
+
+static const uint64_t P9N2_EX_XSTOP_INTERRUPT_REG = 0x200F001Cull;
+//DUPS: 210F001C,
+static const uint64_t P9N2_EX_0_XSTOP_INTERRUPT_REG = 0x200F001Cull;
+//DUPS: 210F001C,
+static const uint64_t P9N2_EX_1_XSTOP_INTERRUPT_REG = 0x220F001Cull;
+//DUPS: 220F001C,
+static const uint64_t P9N2_EX_2_XSTOP_INTERRUPT_REG = 0x240F001Cull;
+//DUPS: 250F001C,
+static const uint64_t P9N2_EX_3_XSTOP_INTERRUPT_REG = 0x260F001Cull;
+//DUPS: 270F001C,
+static const uint64_t P9N2_EX_4_XSTOP_INTERRUPT_REG = 0x280F001Cull;
+//DUPS: 290F001C,
+static const uint64_t P9N2_EX_5_XSTOP_INTERRUPT_REG = 0x2A0F001Cull;
+//DUPS: 2B0F001C,
+static const uint64_t P9N2_EX_6_XSTOP_INTERRUPT_REG = 0x2C0F001Cull;
+//DUPS: 2D0F001C,
+static const uint64_t P9N2_EX_7_XSTOP_INTERRUPT_REG = 0x2E0F001Cull;
+//DUPS: 2F0F001C,
+static const uint64_t P9N2_EX_8_XSTOP_INTERRUPT_REG = 0x300F001Cull;
+//DUPS: 310F001C,
+static const uint64_t P9N2_EX_9_XSTOP_INTERRUPT_REG = 0x320F001Cull;
+//DUPS: 330F001C,
+static const uint64_t P9N2_EX_10_XSTOP_INTERRUPT_REG = 0x340F001Cull;
+//DUPS: 350F001C,
+static const uint64_t P9N2_EX_11_XSTOP_INTERRUPT_REG = 0x360F001Cull;
+//DUPS: 370F001C,
+
+static const uint64_t P9N2_C_XTRA_TRACE_MODE = 0x200107D1ull;
+
+static const uint64_t P9N2_C_0_XTRA_TRACE_MODE = 0x200107D1ull;
+
+static const uint64_t P9N2_C_1_XTRA_TRACE_MODE = 0x210107D1ull;
+
+static const uint64_t P9N2_C_2_XTRA_TRACE_MODE = 0x220107D1ull;
+
+static const uint64_t P9N2_C_3_XTRA_TRACE_MODE = 0x230107D1ull;
+
+static const uint64_t P9N2_C_4_XTRA_TRACE_MODE = 0x240107D1ull;
+
+static const uint64_t P9N2_C_5_XTRA_TRACE_MODE = 0x250107D1ull;
+
+static const uint64_t P9N2_C_6_XTRA_TRACE_MODE = 0x260107D1ull;
+
+static const uint64_t P9N2_C_7_XTRA_TRACE_MODE = 0x270107D1ull;
+
+static const uint64_t P9N2_C_8_XTRA_TRACE_MODE = 0x280107D1ull;
+
+static const uint64_t P9N2_C_9_XTRA_TRACE_MODE = 0x290107D1ull;
+
+static const uint64_t P9N2_C_10_XTRA_TRACE_MODE = 0x2A0107D1ull;
+
+static const uint64_t P9N2_C_11_XTRA_TRACE_MODE = 0x2B0107D1ull;
+
+static const uint64_t P9N2_C_12_XTRA_TRACE_MODE = 0x2C0107D1ull;
+
+static const uint64_t P9N2_C_13_XTRA_TRACE_MODE = 0x2D0107D1ull;
+
+static const uint64_t P9N2_C_14_XTRA_TRACE_MODE = 0x2E0107D1ull;
+
+static const uint64_t P9N2_C_15_XTRA_TRACE_MODE = 0x2F0107D1ull;
+
+static const uint64_t P9N2_C_16_XTRA_TRACE_MODE = 0x300107D1ull;
+
+static const uint64_t P9N2_C_17_XTRA_TRACE_MODE = 0x310107D1ull;
+
+static const uint64_t P9N2_C_18_XTRA_TRACE_MODE = 0x320107D1ull;
+
+static const uint64_t P9N2_C_19_XTRA_TRACE_MODE = 0x330107D1ull;
+
+static const uint64_t P9N2_C_20_XTRA_TRACE_MODE = 0x340107D1ull;
+
+static const uint64_t P9N2_C_21_XTRA_TRACE_MODE = 0x350107D1ull;
+
+static const uint64_t P9N2_C_22_XTRA_TRACE_MODE = 0x360107D1ull;
+
+static const uint64_t P9N2_C_23_XTRA_TRACE_MODE = 0x370107D1ull;
+
+static const uint64_t P9N2_EQ_XTRA_TRACE_MODE = 0x100107D1ull;
+
+static const uint64_t P9N2_EQ_0_XTRA_TRACE_MODE = 0x100107D1ull;
+
+static const uint64_t P9N2_EQ_1_XTRA_TRACE_MODE = 0x110107D1ull;
+
+static const uint64_t P9N2_EQ_2_XTRA_TRACE_MODE = 0x120107D1ull;
+
+static const uint64_t P9N2_EQ_3_XTRA_TRACE_MODE = 0x130107D1ull;
+
+static const uint64_t P9N2_EQ_4_XTRA_TRACE_MODE = 0x140107D1ull;
+
+static const uint64_t P9N2_EQ_5_XTRA_TRACE_MODE = 0x150107D1ull;
+
+static const uint64_t P9N2_EX_XTRA_TRACE_MODE = 0x200107D1ull;
+//DUPS: 210107D1,
+static const uint64_t P9N2_EX_0_XTRA_TRACE_MODE = 0x200107D1ull;
+//DUPS: 210107D1,
+static const uint64_t P9N2_EX_1_XTRA_TRACE_MODE = 0x220107D1ull;
+//DUPS: 230107D1,
+static const uint64_t P9N2_EX_2_XTRA_TRACE_MODE = 0x240107D1ull;
+//DUPS: 250107D1,
+static const uint64_t P9N2_EX_3_XTRA_TRACE_MODE = 0x260107D1ull;
+//DUPS: 270107D1,
+static const uint64_t P9N2_EX_4_XTRA_TRACE_MODE = 0x280107D1ull;
+//DUPS: 290107D1,
+static const uint64_t P9N2_EX_5_XTRA_TRACE_MODE = 0x2A0107D1ull;
+//DUPS: 2B0107D1,
+static const uint64_t P9N2_EX_6_XTRA_TRACE_MODE = 0x2C0107D1ull;
+//DUPS: 2D0107D1,
+static const uint64_t P9N2_EX_7_XTRA_TRACE_MODE = 0x2F0107D1ull;
+//DUPS: 2F0107D1,
+static const uint64_t P9N2_EX_8_XTRA_TRACE_MODE = 0x300107D1ull;
+//DUPS: 310107D1,
+static const uint64_t P9N2_EX_9_XTRA_TRACE_MODE = 0x320107D1ull;
+//DUPS: 330107D1,
+static const uint64_t P9N2_EX_10_XTRA_TRACE_MODE = 0x340107D1ull;
+//DUPS: 350107D1,
+static const uint64_t P9N2_EX_11_XTRA_TRACE_MODE = 0x360107D1ull;
+//DUPS: 370107D1,
+#endif
+
diff --git a/src/import/chips/p9/common/include/p9n2_quad_scom_addresses_fld.H b/src/import/chips/p9/common/include/p9n2_quad_scom_addresses_fld.H
new file mode 100644
index 000000000..fdc0d13e0
--- /dev/null
+++ b/src/import/chips/p9/common/include/p9n2_quad_scom_addresses_fld.H
@@ -0,0 +1,11158 @@
+/* IBM_PROLOG_BEGIN_TAG */
+/* This is an automatically generated prolog. */
+/* */
+/* $Source: src/import/chips/p9/common/include/p9n2_quad_scom_addresses_fld.H $ */
+/* */
+/* OpenPOWER HostBoot Project */
+/* */
+/* Contributors Listed Below - COPYRIGHT 2017 */
+/* [+] International Business Machines Corp. */
+/* */
+/* */
+/* Licensed under the Apache License, Version 2.0 (the "License"); */
+/* you may not use this file except in compliance with the License. */
+/* You may obtain a copy of the License at */
+/* */
+/* http://www.apache.org/licenses/LICENSE-2.0 */
+/* */
+/* Unless required by applicable law or agreed to in writing, software */
+/* distributed under the License is distributed on an "AS IS" BASIS, */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */
+/* implied. See the License for the specific language governing */
+/* permissions and limitations under the License. */
+/* */
+/* IBM_PROLOG_END_TAG */
+///
+/// @file p9_quad_scom_addresses_fld.H
+/// @brief Defines constants for scom addresses
+///
+// *HWP HWP Owner: Ben Gass <bgass@us.ibm.com>
+// *HWP FW Owner: Thi Tran <thi@us.ibm.com>
+// *HWP Team: SOA
+// *HWP Level: 1
+// *HWP Consumed by: FSP:HB:HS:OCC:SBE:CME:SGPE:PGPE:FPPE:IPPE
+
+
+#ifndef __P9N2_QUAD_SCOM_ADDRESSES_FLD_H
+#define __P9N2_QUAD_SCOM_ADDRESSES_FLD_H
+
+#include <stdint.h>
+
+static const uint8_t P9N2_EQ_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR = 0 ;
+static const uint8_t P9N2_EQ_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN = 16 ;
+static const uint8_t P9N2_EQ_ADDR_TRAP_REG_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR = 16 ;
+static const uint8_t P9N2_EQ_ADDR_TRAP_REG_RESERVED_LAST_LT = 17 ;
+static const uint8_t P9N2_EQ_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR = 18 ;
+static const uint8_t P9N2_EQ_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN = 13 ;
+static const uint8_t P9N2_EQ_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY = 31 ;
+static const uint8_t P9N2_EQ_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR = 32 ;
+static const uint8_t P9N2_EQ_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION = 33 ;
+static const uint8_t P9N2_EQ_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER = 34 ;
+
+static const uint8_t P9N2_EX_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR = 0 ;
+static const uint8_t P9N2_EX_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN = 16 ;
+static const uint8_t P9N2_EX_ADDR_TRAP_REG_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR = 16 ;
+static const uint8_t P9N2_EX_ADDR_TRAP_REG_RESERVED_LAST_LT = 17 ;
+static const uint8_t P9N2_EX_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR = 18 ;
+static const uint8_t P9N2_EX_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN = 13 ;
+static const uint8_t P9N2_EX_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY = 31 ;
+static const uint8_t P9N2_EX_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR = 32 ;
+static const uint8_t P9N2_EX_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION = 33 ;
+static const uint8_t P9N2_EX_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER = 34 ;
+
+static const uint8_t P9N2_C_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR = 0 ;
+static const uint8_t P9N2_C_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN = 16 ;
+static const uint8_t P9N2_C_ADDR_TRAP_REG_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR = 16 ;
+static const uint8_t P9N2_C_ADDR_TRAP_REG_RESERVED_LAST_LT = 17 ;
+static const uint8_t P9N2_C_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR = 18 ;
+static const uint8_t P9N2_C_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN = 13 ;
+static const uint8_t P9N2_C_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY = 31 ;
+static const uint8_t P9N2_C_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR = 32 ;
+static const uint8_t P9N2_C_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION = 33 ;
+static const uint8_t P9N2_C_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER = 34 ;
+
+static const uint8_t P9N2_EQ_ASSIST_INTERRUPT_REG_ATTN = 0 ;
+static const uint8_t P9N2_EQ_ASSIST_INTERRUPT_REG_RECOV = 1 ;
+static const uint8_t P9N2_EQ_ASSIST_INTERRUPT_REG_XSTOP = 2 ;
+
+static const uint8_t P9N2_EX_ASSIST_INTERRUPT_REG_ATTN = 0 ;
+static const uint8_t P9N2_EX_ASSIST_INTERRUPT_REG_RECOV = 1 ;
+static const uint8_t P9N2_EX_ASSIST_INTERRUPT_REG_XSTOP = 2 ;
+
+static const uint8_t P9N2_C_ASSIST_INTERRUPT_REG_ATTN = 0 ;
+static const uint8_t P9N2_C_ASSIST_INTERRUPT_REG_RECOV = 1 ;
+static const uint8_t P9N2_C_ASSIST_INTERRUPT_REG_XSTOP = 2 ;
+
+static const uint8_t P9N2_EQ_ATOMIC_LOCK_MASK_LATCH_REG_MASK = 0 ;
+static const uint8_t P9N2_EQ_ATOMIC_LOCK_MASK_LATCH_REG_MASK_LEN = 16 ;
+
+static const uint8_t P9N2_EX_ATOMIC_LOCK_MASK_LATCH_REG_MASK = 0 ;
+static const uint8_t P9N2_EX_ATOMIC_LOCK_MASK_LATCH_REG_MASK_LEN = 16 ;
+
+static const uint8_t P9N2_C_ATOMIC_LOCK_MASK_LATCH_REG_MASK = 0 ;
+static const uint8_t P9N2_C_ATOMIC_LOCK_MASK_LATCH_REG_MASK_LEN = 16 ;
+
+static const uint8_t P9N2_EQ_ATOMIC_LOCK_REG_ENABLE = 0 ;
+static const uint8_t P9N2_EQ_ATOMIC_LOCK_REG_ID = 1 ;
+static const uint8_t P9N2_EQ_ATOMIC_LOCK_REG_ID_LEN = 4 ;
+static const uint8_t P9N2_EQ_ATOMIC_LOCK_REG_ACTIVITY = 8 ;
+static const uint8_t P9N2_EQ_ATOMIC_LOCK_REG_ACTIVITY_LEN = 8 ;
+
+static const uint8_t P9N2_EX_ATOMIC_LOCK_REG_ENABLE = 0 ;
+static const uint8_t P9N2_EX_ATOMIC_LOCK_REG_ID = 1 ;
+static const uint8_t P9N2_EX_ATOMIC_LOCK_REG_ID_LEN = 4 ;
+static const uint8_t P9N2_EX_ATOMIC_LOCK_REG_ACTIVITY = 8 ;
+static const uint8_t P9N2_EX_ATOMIC_LOCK_REG_ACTIVITY_LEN = 8 ;
+
+static const uint8_t P9N2_C_ATOMIC_LOCK_REG_ENABLE = 0 ;
+static const uint8_t P9N2_C_ATOMIC_LOCK_REG_ID = 1 ;
+static const uint8_t P9N2_C_ATOMIC_LOCK_REG_ID_LEN = 4 ;
+static const uint8_t P9N2_C_ATOMIC_LOCK_REG_ACTIVITY = 8 ;
+static const uint8_t P9N2_C_ATOMIC_LOCK_REG_ACTIVITY_LEN = 8 ;
+
+static const uint8_t P9N2_EQ_ATTN_INTERRUPT_REG_ATTN = 0 ;
+
+static const uint8_t P9N2_EX_ATTN_INTERRUPT_REG_ATTN = 0 ;
+
+static const uint8_t P9N2_C_ATTN_INTERRUPT_REG_ATTN = 0 ;
+
+static const uint8_t P9N2_EQ_BIST_TC_START_TEST_DC = 0 ;
+static const uint8_t P9N2_EQ_BIST_TC_SRAM_ABIST_MODE_DC = 1 ;
+static const uint8_t P9N2_EQ_BIST_TC_EDRAM_ABIST_MODE_DC = 2 ;
+static const uint8_t P9N2_EQ_BIST_TC_IOBIST_MODE_DC = 3 ;
+static const uint8_t P9N2_EQ_BIST_PERV = 4 ;
+static const uint8_t P9N2_EQ_BIST_UNIT1 = 5 ;
+static const uint8_t P9N2_EQ_BIST_UNIT2 = 6 ;
+static const uint8_t P9N2_EQ_BIST_UNIT3 = 7 ;
+static const uint8_t P9N2_EQ_BIST_UNIT4 = 8 ;
+static const uint8_t P9N2_EQ_BIST_UNIT5 = 9 ;
+static const uint8_t P9N2_EQ_BIST_UNIT6 = 10 ;
+static const uint8_t P9N2_EQ_BIST_UNIT7 = 11 ;
+static const uint8_t P9N2_EQ_BIST_UNIT8 = 12 ;
+static const uint8_t P9N2_EQ_BIST_UNIT9 = 13 ;
+static const uint8_t P9N2_EQ_BIST_UNIT10 = 14 ;
+static const uint8_t P9N2_EQ_BIST_STROBE_WINDOW_EN = 48 ;
+
+static const uint8_t P9N2_EX_BIST_TC_START_TEST_DC = 0 ;
+static const uint8_t P9N2_EX_BIST_TC_SRAM_ABIST_MODE_DC = 1 ;
+static const uint8_t P9N2_EX_BIST_TC_EDRAM_ABIST_MODE_DC = 2 ;
+static const uint8_t P9N2_EX_BIST_TC_IOBIST_MODE_DC = 3 ;
+static const uint8_t P9N2_EX_BIST_PERV = 4 ;
+static const uint8_t P9N2_EX_BIST_UNIT1 = 5 ;
+static const uint8_t P9N2_EX_BIST_UNIT2 = 6 ;
+static const uint8_t P9N2_EX_BIST_UNIT3 = 7 ;
+static const uint8_t P9N2_EX_BIST_UNIT4 = 8 ;
+static const uint8_t P9N2_EX_BIST_UNIT5 = 9 ;
+static const uint8_t P9N2_EX_BIST_UNIT6 = 10 ;
+static const uint8_t P9N2_EX_BIST_UNIT7 = 11 ;
+static const uint8_t P9N2_EX_BIST_UNIT8 = 12 ;
+static const uint8_t P9N2_EX_BIST_UNIT9 = 13 ;
+static const uint8_t P9N2_EX_BIST_UNIT10 = 14 ;
+static const uint8_t P9N2_EX_BIST_STROBE_WINDOW_EN = 48 ;
+
+static const uint8_t P9N2_C_BIST_TC_START_TEST_DC = 0 ;
+static const uint8_t P9N2_C_BIST_TC_SRAM_ABIST_MODE_DC = 1 ;
+static const uint8_t P9N2_C_BIST_TC_EDRAM_ABIST_MODE_DC = 2 ;
+static const uint8_t P9N2_C_BIST_TC_IOBIST_MODE_DC = 3 ;
+static const uint8_t P9N2_C_BIST_PERV = 4 ;
+static const uint8_t P9N2_C_BIST_UNIT1 = 5 ;
+static const uint8_t P9N2_C_BIST_UNIT2 = 6 ;
+static const uint8_t P9N2_C_BIST_UNIT3 = 7 ;
+static const uint8_t P9N2_C_BIST_UNIT4 = 8 ;
+static const uint8_t P9N2_C_BIST_UNIT5 = 9 ;
+static const uint8_t P9N2_C_BIST_UNIT6 = 10 ;
+static const uint8_t P9N2_C_BIST_UNIT7 = 11 ;
+static const uint8_t P9N2_C_BIST_UNIT8 = 12 ;
+static const uint8_t P9N2_C_BIST_UNIT9 = 13 ;
+static const uint8_t P9N2_C_BIST_UNIT10 = 14 ;
+static const uint8_t P9N2_C_BIST_STROBE_WINDOW_EN = 48 ;
+
+static const uint8_t P9N2_EQ_CC_ATOMIC_LOCK_REG_ENABLE = 0 ;
+static const uint8_t P9N2_EQ_CC_ATOMIC_LOCK_REG_ID = 1 ;
+static const uint8_t P9N2_EQ_CC_ATOMIC_LOCK_REG_ID_LEN = 4 ;
+static const uint8_t P9N2_EQ_CC_ATOMIC_LOCK_REG_ACTIVITY = 8 ;
+static const uint8_t P9N2_EQ_CC_ATOMIC_LOCK_REG_ACTIVITY_LEN = 8 ;
+
+static const uint8_t P9N2_EX_CC_ATOMIC_LOCK_REG_ENABLE = 0 ;
+static const uint8_t P9N2_EX_CC_ATOMIC_LOCK_REG_ID = 1 ;
+static const uint8_t P9N2_EX_CC_ATOMIC_LOCK_REG_ID_LEN = 4 ;
+static const uint8_t P9N2_EX_CC_ATOMIC_LOCK_REG_ACTIVITY = 8 ;
+static const uint8_t P9N2_EX_CC_ATOMIC_LOCK_REG_ACTIVITY_LEN = 8 ;
+
+static const uint8_t P9N2_C_CC_ATOMIC_LOCK_REG_ENABLE = 0 ;
+static const uint8_t P9N2_C_CC_ATOMIC_LOCK_REG_ID = 1 ;
+static const uint8_t P9N2_C_CC_ATOMIC_LOCK_REG_ID_LEN = 4 ;
+static const uint8_t P9N2_C_CC_ATOMIC_LOCK_REG_ACTIVITY = 8 ;
+static const uint8_t P9N2_C_CC_ATOMIC_LOCK_REG_ACTIVITY_LEN = 8 ;
+
+static const uint8_t P9N2_EQ_CC_PROTECT_MODE_REG_READ_ENABLE = 0 ;
+static const uint8_t P9N2_EQ_CC_PROTECT_MODE_REG_WRITE_ENABLE = 1 ;
+
+static const uint8_t P9N2_EX_CC_PROTECT_MODE_REG_READ_ENABLE = 0 ;
+static const uint8_t P9N2_EX_CC_PROTECT_MODE_REG_WRITE_ENABLE = 1 ;
+
+static const uint8_t P9N2_C_CC_PROTECT_MODE_REG_READ_ENABLE = 0 ;
+static const uint8_t P9N2_C_CC_PROTECT_MODE_REG_WRITE_ENABLE = 1 ;
+
+static const uint8_t P9N2_EQ_CLK_REGION_CLOCK_CMD = 0 ;
+static const uint8_t P9N2_EQ_CLK_REGION_CLOCK_CMD_LEN = 2 ;
+static const uint8_t P9N2_EQ_CLK_REGION_SLAVE_MODE = 2 ;
+static const uint8_t P9N2_EQ_CLK_REGION_MASTER_MODE = 3 ;
+static const uint8_t P9N2_EQ_CLK_REGION_CLOCK_PERV = 4 ;
+static const uint8_t P9N2_EQ_CLK_REGION_CLOCK_UNIT1 = 5 ;
+static const uint8_t P9N2_EQ_CLK_REGION_CLOCK_UNIT2 = 6 ;
+static const uint8_t P9N2_EQ_CLK_REGION_CLOCK_UNIT3 = 7 ;
+static const uint8_t P9N2_EQ_CLK_REGION_CLOCK_UNIT4 = 8 ;
+static const uint8_t P9N2_EQ_CLK_REGION_CLOCK_UNIT5 = 9 ;
+static const uint8_t P9N2_EQ_CLK_REGION_CLOCK_UNIT6 = 10 ;
+static const uint8_t P9N2_EQ_CLK_REGION_CLOCK_UNIT7 = 11 ;
+static const uint8_t P9N2_EQ_CLK_REGION_CLOCK_UNIT8 = 12 ;
+static const uint8_t P9N2_EQ_CLK_REGION_CLOCK_UNIT9 = 13 ;
+static const uint8_t P9N2_EQ_CLK_REGION_CLOCK_UNIT10 = 14 ;
+static const uint8_t P9N2_EQ_CLK_REGION_SEL_THOLD_SL = 48 ;
+static const uint8_t P9N2_EQ_CLK_REGION_SEL_THOLD_NSL = 49 ;
+static const uint8_t P9N2_EQ_CLK_REGION_SEL_THOLD_ARY = 50 ;
+static const uint8_t P9N2_EQ_CLK_REGION_CLOCK_PULSE_USE_EVEN = 52 ;
+
+static const uint8_t P9N2_EX_CLK_REGION_CLOCK_CMD = 0 ;
+static const uint8_t P9N2_EX_CLK_REGION_CLOCK_CMD_LEN = 2 ;
+static const uint8_t P9N2_EX_CLK_REGION_SLAVE_MODE = 2 ;
+static const uint8_t P9N2_EX_CLK_REGION_MASTER_MODE = 3 ;
+static const uint8_t P9N2_EX_CLK_REGION_CLOCK_PERV = 4 ;
+static const uint8_t P9N2_EX_CLK_REGION_CLOCK_UNIT1 = 5 ;
+static const uint8_t P9N2_EX_CLK_REGION_CLOCK_UNIT2 = 6 ;
+static const uint8_t P9N2_EX_CLK_REGION_CLOCK_UNIT3 = 7 ;
+static const uint8_t P9N2_EX_CLK_REGION_CLOCK_UNIT4 = 8 ;
+static const uint8_t P9N2_EX_CLK_REGION_CLOCK_UNIT5 = 9 ;
+static const uint8_t P9N2_EX_CLK_REGION_CLOCK_UNIT6 = 10 ;
+static const uint8_t P9N2_EX_CLK_REGION_CLOCK_UNIT7 = 11 ;
+static const uint8_t P9N2_EX_CLK_REGION_CLOCK_UNIT8 = 12 ;
+static const uint8_t P9N2_EX_CLK_REGION_CLOCK_UNIT9 = 13 ;
+static const uint8_t P9N2_EX_CLK_REGION_CLOCK_UNIT10 = 14 ;
+static const uint8_t P9N2_EX_CLK_REGION_SEL_THOLD_SL = 48 ;
+static const uint8_t P9N2_EX_CLK_REGION_SEL_THOLD_NSL = 49 ;
+static const uint8_t P9N2_EX_CLK_REGION_SEL_THOLD_ARY = 50 ;
+static const uint8_t P9N2_EX_CLK_REGION_CLOCK_PULSE_USE_EVEN = 52 ;
+
+static const uint8_t P9N2_C_CLK_REGION_CLOCK_CMD = 0 ;
+static const uint8_t P9N2_C_CLK_REGION_CLOCK_CMD_LEN = 2 ;
+static const uint8_t P9N2_C_CLK_REGION_SLAVE_MODE = 2 ;
+static const uint8_t P9N2_C_CLK_REGION_MASTER_MODE = 3 ;
+static const uint8_t P9N2_C_CLK_REGION_CLOCK_PERV = 4 ;
+static const uint8_t P9N2_C_CLK_REGION_CLOCK_UNIT1 = 5 ;
+static const uint8_t P9N2_C_CLK_REGION_CLOCK_UNIT2 = 6 ;
+static const uint8_t P9N2_C_CLK_REGION_CLOCK_UNIT3 = 7 ;
+static const uint8_t P9N2_C_CLK_REGION_CLOCK_UNIT4 = 8 ;
+static const uint8_t P9N2_C_CLK_REGION_CLOCK_UNIT5 = 9 ;
+static const uint8_t P9N2_C_CLK_REGION_CLOCK_UNIT6 = 10 ;
+static const uint8_t P9N2_C_CLK_REGION_CLOCK_UNIT7 = 11 ;
+static const uint8_t P9N2_C_CLK_REGION_CLOCK_UNIT8 = 12 ;
+static const uint8_t P9N2_C_CLK_REGION_CLOCK_UNIT9 = 13 ;
+static const uint8_t P9N2_C_CLK_REGION_CLOCK_UNIT10 = 14 ;
+static const uint8_t P9N2_C_CLK_REGION_SEL_THOLD_SL = 48 ;
+static const uint8_t P9N2_C_CLK_REGION_SEL_THOLD_NSL = 49 ;
+static const uint8_t P9N2_C_CLK_REGION_SEL_THOLD_ARY = 50 ;
+static const uint8_t P9N2_C_CLK_REGION_CLOCK_PULSE_USE_EVEN = 52 ;
+
+static const uint8_t P9N2_EQ_CLOCK_STAT_ARY_STATUS_PERV = 4 ;
+static const uint8_t P9N2_EQ_CLOCK_STAT_ARY_STATUS_UNIT1 = 5 ;
+static const uint8_t P9N2_EQ_CLOCK_STAT_ARY_STATUS_UNIT2 = 6 ;
+static const uint8_t P9N2_EQ_CLOCK_STAT_ARY_STATUS_UNIT3 = 7 ;
+static const uint8_t P9N2_EQ_CLOCK_STAT_ARY_STATUS_UNIT4 = 8 ;
+static const uint8_t P9N2_EQ_CLOCK_STAT_ARY_STATUS_UNIT5 = 9 ;
+static const uint8_t P9N2_EQ_CLOCK_STAT_ARY_STATUS_UNIT6 = 10 ;
+static const uint8_t P9N2_EQ_CLOCK_STAT_ARY_STATUS_UNIT7 = 11 ;
+static const uint8_t P9N2_EQ_CLOCK_STAT_ARY_STATUS_UNIT8 = 12 ;
+static const uint8_t P9N2_EQ_CLOCK_STAT_ARY_STATUS_UNIT9 = 13 ;
+static const uint8_t P9N2_EQ_CLOCK_STAT_ARY_STATUS_UNIT10 = 14 ;
+
+static const uint8_t P9N2_EX_CLOCK_STAT_ARY_STATUS_PERV = 4 ;
+static const uint8_t P9N2_EX_CLOCK_STAT_ARY_STATUS_UNIT1 = 5 ;
+static const uint8_t P9N2_EX_CLOCK_STAT_ARY_STATUS_UNIT2 = 6 ;
+static const uint8_t P9N2_EX_CLOCK_STAT_ARY_STATUS_UNIT3 = 7 ;
+static const uint8_t P9N2_EX_CLOCK_STAT_ARY_STATUS_UNIT4 = 8 ;
+static const uint8_t P9N2_EX_CLOCK_STAT_ARY_STATUS_UNIT5 = 9 ;
+static const uint8_t P9N2_EX_CLOCK_STAT_ARY_STATUS_UNIT6 = 10 ;
+static const uint8_t P9N2_EX_CLOCK_STAT_ARY_STATUS_UNIT7 = 11 ;
+static const uint8_t P9N2_EX_CLOCK_STAT_ARY_STATUS_UNIT8 = 12 ;
+static const uint8_t P9N2_EX_CLOCK_STAT_ARY_STATUS_UNIT9 = 13 ;
+static const uint8_t P9N2_EX_CLOCK_STAT_ARY_STATUS_UNIT10 = 14 ;
+
+static const uint8_t P9N2_C_CLOCK_STAT_ARY_STATUS_PERV = 4 ;
+static const uint8_t P9N2_C_CLOCK_STAT_ARY_STATUS_UNIT1 = 5 ;
+static const uint8_t P9N2_C_CLOCK_STAT_ARY_STATUS_UNIT2 = 6 ;
+static const uint8_t P9N2_C_CLOCK_STAT_ARY_STATUS_UNIT3 = 7 ;
+static const uint8_t P9N2_C_CLOCK_STAT_ARY_STATUS_UNIT4 = 8 ;
+static const uint8_t P9N2_C_CLOCK_STAT_ARY_STATUS_UNIT5 = 9 ;
+static const uint8_t P9N2_C_CLOCK_STAT_ARY_STATUS_UNIT6 = 10 ;
+static const uint8_t P9N2_C_CLOCK_STAT_ARY_STATUS_UNIT7 = 11 ;
+static const uint8_t P9N2_C_CLOCK_STAT_ARY_STATUS_UNIT8 = 12 ;
+static const uint8_t P9N2_C_CLOCK_STAT_ARY_STATUS_UNIT9 = 13 ;
+static const uint8_t P9N2_C_CLOCK_STAT_ARY_STATUS_UNIT10 = 14 ;
+
+static const uint8_t P9N2_EQ_CLOCK_STAT_NSL_STATUS_PERV = 4 ;
+static const uint8_t P9N2_EQ_CLOCK_STAT_NSL_STATUS_UNIT1 = 5 ;
+static const uint8_t P9N2_EQ_CLOCK_STAT_NSL_STATUS_UNIT2 = 6 ;
+static const uint8_t P9N2_EQ_CLOCK_STAT_NSL_STATUS_UNIT3 = 7 ;
+static const uint8_t P9N2_EQ_CLOCK_STAT_NSL_STATUS_UNIT4 = 8 ;
+static const uint8_t P9N2_EQ_CLOCK_STAT_NSL_STATUS_UNIT5 = 9 ;
+static const uint8_t P9N2_EQ_CLOCK_STAT_NSL_STATUS_UNIT6 = 10 ;
+static const uint8_t P9N2_EQ_CLOCK_STAT_NSL_STATUS_UNIT7 = 11 ;
+static const uint8_t P9N2_EQ_CLOCK_STAT_NSL_STATUS_UNIT8 = 12 ;
+static const uint8_t P9N2_EQ_CLOCK_STAT_NSL_STATUS_UNIT9 = 13 ;
+static const uint8_t P9N2_EQ_CLOCK_STAT_NSL_STATUS_UNIT10 = 14 ;
+
+static const uint8_t P9N2_EX_CLOCK_STAT_NSL_STATUS_PERV = 4 ;
+static const uint8_t P9N2_EX_CLOCK_STAT_NSL_STATUS_UNIT1 = 5 ;
+static const uint8_t P9N2_EX_CLOCK_STAT_NSL_STATUS_UNIT2 = 6 ;
+static const uint8_t P9N2_EX_CLOCK_STAT_NSL_STATUS_UNIT3 = 7 ;
+static const uint8_t P9N2_EX_CLOCK_STAT_NSL_STATUS_UNIT4 = 8 ;
+static const uint8_t P9N2_EX_CLOCK_STAT_NSL_STATUS_UNIT5 = 9 ;
+static const uint8_t P9N2_EX_CLOCK_STAT_NSL_STATUS_UNIT6 = 10 ;
+static const uint8_t P9N2_EX_CLOCK_STAT_NSL_STATUS_UNIT7 = 11 ;
+static const uint8_t P9N2_EX_CLOCK_STAT_NSL_STATUS_UNIT8 = 12 ;
+static const uint8_t P9N2_EX_CLOCK_STAT_NSL_STATUS_UNIT9 = 13 ;
+static const uint8_t P9N2_EX_CLOCK_STAT_NSL_STATUS_UNIT10 = 14 ;
+
+static const uint8_t P9N2_C_CLOCK_STAT_NSL_STATUS_PERV = 4 ;
+static const uint8_t P9N2_C_CLOCK_STAT_NSL_STATUS_UNIT1 = 5 ;
+static const uint8_t P9N2_C_CLOCK_STAT_NSL_STATUS_UNIT2 = 6 ;
+static const uint8_t P9N2_C_CLOCK_STAT_NSL_STATUS_UNIT3 = 7 ;
+static const uint8_t P9N2_C_CLOCK_STAT_NSL_STATUS_UNIT4 = 8 ;
+static const uint8_t P9N2_C_CLOCK_STAT_NSL_STATUS_UNIT5 = 9 ;
+static const uint8_t P9N2_C_CLOCK_STAT_NSL_STATUS_UNIT6 = 10 ;
+static const uint8_t P9N2_C_CLOCK_STAT_NSL_STATUS_UNIT7 = 11 ;
+static const uint8_t P9N2_C_CLOCK_STAT_NSL_STATUS_UNIT8 = 12 ;
+static const uint8_t P9N2_C_CLOCK_STAT_NSL_STATUS_UNIT9 = 13 ;
+static const uint8_t P9N2_C_CLOCK_STAT_NSL_STATUS_UNIT10 = 14 ;
+
+static const uint8_t P9N2_EQ_CLOCK_STAT_SL_STATUS_PERV = 4 ;
+static const uint8_t P9N2_EQ_CLOCK_STAT_SL_STATUS_UNIT1 = 5 ;
+static const uint8_t P9N2_EQ_CLOCK_STAT_SL_STATUS_UNIT2 = 6 ;
+static const uint8_t P9N2_EQ_CLOCK_STAT_SL_STATUS_UNIT3 = 7 ;
+static const uint8_t P9N2_EQ_CLOCK_STAT_SL_STATUS_UNIT4 = 8 ;
+static const uint8_t P9N2_EQ_CLOCK_STAT_SL_STATUS_UNIT5 = 9 ;
+static const uint8_t P9N2_EQ_CLOCK_STAT_SL_STATUS_UNIT6 = 10 ;
+static const uint8_t P9N2_EQ_CLOCK_STAT_SL_STATUS_UNIT7 = 11 ;
+static const uint8_t P9N2_EQ_CLOCK_STAT_SL_STATUS_UNIT8 = 12 ;
+static const uint8_t P9N2_EQ_CLOCK_STAT_SL_STATUS_UNIT9 = 13 ;
+static const uint8_t P9N2_EQ_CLOCK_STAT_SL_STATUS_UNIT10 = 14 ;
+
+static const uint8_t P9N2_EX_CLOCK_STAT_SL_STATUS_PERV = 4 ;
+static const uint8_t P9N2_EX_CLOCK_STAT_SL_STATUS_UNIT1 = 5 ;
+static const uint8_t P9N2_EX_CLOCK_STAT_SL_STATUS_UNIT2 = 6 ;
+static const uint8_t P9N2_EX_CLOCK_STAT_SL_STATUS_UNIT3 = 7 ;
+static const uint8_t P9N2_EX_CLOCK_STAT_SL_STATUS_UNIT4 = 8 ;
+static const uint8_t P9N2_EX_CLOCK_STAT_SL_STATUS_UNIT5 = 9 ;
+static const uint8_t P9N2_EX_CLOCK_STAT_SL_STATUS_UNIT6 = 10 ;
+static const uint8_t P9N2_EX_CLOCK_STAT_SL_STATUS_UNIT7 = 11 ;
+static const uint8_t P9N2_EX_CLOCK_STAT_SL_STATUS_UNIT8 = 12 ;
+static const uint8_t P9N2_EX_CLOCK_STAT_SL_STATUS_UNIT9 = 13 ;
+static const uint8_t P9N2_EX_CLOCK_STAT_SL_STATUS_UNIT10 = 14 ;
+
+static const uint8_t P9N2_C_CLOCK_STAT_SL_STATUS_PERV = 4 ;
+static const uint8_t P9N2_C_CLOCK_STAT_SL_STATUS_UNIT1 = 5 ;
+static const uint8_t P9N2_C_CLOCK_STAT_SL_STATUS_UNIT2 = 6 ;
+static const uint8_t P9N2_C_CLOCK_STAT_SL_STATUS_UNIT3 = 7 ;
+static const uint8_t P9N2_C_CLOCK_STAT_SL_STATUS_UNIT4 = 8 ;
+static const uint8_t P9N2_C_CLOCK_STAT_SL_STATUS_UNIT5 = 9 ;
+static const uint8_t P9N2_C_CLOCK_STAT_SL_STATUS_UNIT6 = 10 ;
+static const uint8_t P9N2_C_CLOCK_STAT_SL_STATUS_UNIT7 = 11 ;
+static const uint8_t P9N2_C_CLOCK_STAT_SL_STATUS_UNIT8 = 12 ;
+static const uint8_t P9N2_C_CLOCK_STAT_SL_STATUS_UNIT9 = 13 ;
+static const uint8_t P9N2_C_CLOCK_STAT_SL_STATUS_UNIT10 = 14 ;
+
+static const uint8_t P9N2_EX_CME_LCL_DBG_EN = 0 ;
+static const uint8_t P9N2_EX_CME_LCL_DBG_HALT_ON_XSTOP = 1 ;
+static const uint8_t P9N2_EX_CME_LCL_DBG_HALT_ON_TRIG = 2 ;
+static const uint8_t P9N2_EX_CME_LCL_DBG_RESERVED3 = 3 ;
+static const uint8_t P9N2_EX_CME_LCL_DBG_EN_INTR_ADDR = 4 ;
+static const uint8_t P9N2_EX_CME_LCL_DBG_EN_TRACE_EXTRA = 5 ;
+static const uint8_t P9N2_EX_CME_LCL_DBG_EN_TRACE_STALL = 6 ;
+static const uint8_t P9N2_EX_CME_LCL_DBG_EN_WAIT_CYCLES = 7 ;
+static const uint8_t P9N2_EX_CME_LCL_DBG_EN_FULL_SPEED = 8 ;
+static const uint8_t P9N2_EX_CME_LCL_DBG_RESERVED9 = 9 ;
+static const uint8_t P9N2_EX_CME_LCL_DBG_TRACE_MODE_SEL = 10 ;
+static const uint8_t P9N2_EX_CME_LCL_DBG_TRACE_MODE_SEL_LEN = 2 ;
+static const uint8_t P9N2_EX_CME_LCL_DBG_RESERVED12_15 = 12 ;
+static const uint8_t P9N2_EX_CME_LCL_DBG_RESERVED12_15_LEN = 4 ;
+static const uint8_t P9N2_EX_CME_LCL_DBG_FIR_TRIGGER = 16 ;
+static const uint8_t P9N2_EX_CME_LCL_DBG_MIB_GPIO = 17 ;
+static const uint8_t P9N2_EX_CME_LCL_DBG_MIB_GPIO_LEN = 3 ;
+static const uint8_t P9N2_EX_CME_LCL_DBG_TRACE_DATA_SEL = 20 ;
+static const uint8_t P9N2_EX_CME_LCL_DBG_TRACE_DATA_SEL_LEN = 4 ;
+static const uint8_t P9N2_EX_CME_LCL_DBG_HALT_INPUT = 24 ;
+
+static const uint8_t P9N2_EQ_CME_LCL_EIMR_INTERRUPT_MASK = 0 ;
+static const uint8_t P9N2_EQ_CME_LCL_EIMR_INTERRUPT_MASK_LEN = 44 ;
+
+static const uint8_t P9N2_EX_CME_LCL_EIMR_INTERRUPT_MASK = 0 ;
+static const uint8_t P9N2_EX_CME_LCL_EIMR_INTERRUPT_MASK_LEN = 44 ;
+
+static const uint8_t P9N2_EQ_CME_LCL_EINR_INTERRUPT_INPUT = 0 ;
+static const uint8_t P9N2_EQ_CME_LCL_EINR_INTERRUPT_INPUT_LEN = 44 ;
+
+static const uint8_t P9N2_EX_CME_LCL_EINR_INTERRUPT_INPUT = 0 ;
+static const uint8_t P9N2_EX_CME_LCL_EINR_INTERRUPT_INPUT_LEN = 44 ;
+
+static const uint8_t P9N2_EQ_CME_LCL_EIPR_INTERRUPT_POLARITY = 0 ;
+static const uint8_t P9N2_EQ_CME_LCL_EIPR_INTERRUPT_POLARITY_LEN = 44 ;
+
+static const uint8_t P9N2_EX_CME_LCL_EIPR_INTERRUPT_POLARITY = 0 ;
+static const uint8_t P9N2_EX_CME_LCL_EIPR_INTERRUPT_POLARITY_LEN = 44 ;
+
+static const uint8_t P9N2_EQ_CME_LCL_EISR_DEBUGGER = 0 ;
+static const uint8_t P9N2_EQ_CME_LCL_EISR_DEBUG_TRIGGER = 1 ;
+static const uint8_t P9N2_EQ_CME_LCL_EISR_QUAD_CHECKSTOP = 2 ;
+static const uint8_t P9N2_EQ_CME_LCL_EISR_PVREF_FAIL = 3 ;
+static const uint8_t P9N2_EQ_CME_LCL_EISR_OCC_HEARTBEAT_LOST = 4 ;
+static const uint8_t P9N2_EQ_CME_LCL_EISR_CORE_CHECKSTOP = 5 ;
+static const uint8_t P9N2_EQ_CME_LCL_EISR_DROPOUT_DETECT = 6 ;
+static const uint8_t P9N2_EQ_CME_LCL_EISR_INTERCME_DIRECT_IN_0 = 7 ;
+static const uint8_t P9N2_EQ_CME_LCL_EISR_BCE_BUSY_HIGH = 8 ;
+static const uint8_t P9N2_EQ_CME_LCL_EISR_BCE_TIMEOUT = 9 ;
+static const uint8_t P9N2_EQ_CME_LCL_EISR_DOORBELL3_C0 = 10 ;
+static const uint8_t P9N2_EQ_CME_LCL_EISR_DOORBELL3_C1 = 11 ;
+static const uint8_t P9N2_EQ_CME_LCL_EISR_PC_INTR_PENDING_C0 = 12 ;
+static const uint8_t P9N2_EQ_CME_LCL_EISR_PC_INTR_PENDING_C1 = 13 ;
+static const uint8_t P9N2_EQ_CME_LCL_EISR_SPECIAL_WAKEUP_C0 = 14 ;
+static const uint8_t P9N2_EQ_CME_LCL_EISR_SPECIAL_WAKEUP_C1 = 15 ;
+static const uint8_t P9N2_EQ_CME_LCL_EISR_REG_WAKEUP_C0 = 16 ;
+static const uint8_t P9N2_EQ_CME_LCL_EISR_REG_WAKEUP_C1 = 17 ;
+static const uint8_t P9N2_EQ_CME_LCL_EISR_DOORBELL2_C0 = 18 ;
+static const uint8_t P9N2_EQ_CME_LCL_EISR_DOORBELL2_C1 = 19 ;
+static const uint8_t P9N2_EQ_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C0 = 20 ;
+static const uint8_t P9N2_EQ_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C1 = 21 ;
+static const uint8_t P9N2_EQ_CME_LCL_EISR_L2_PURGE_DONE = 22 ;
+static const uint8_t P9N2_EQ_CME_LCL_EISR_NCU_PURGE_DONE = 23 ;
+static const uint8_t P9N2_EQ_CME_LCL_EISR_CHTM_PURGE_DONE_C0 = 24 ;
+static const uint8_t P9N2_EQ_CME_LCL_EISR_CHTM_PURGE_DONE_C1 = 25 ;
+static const uint8_t P9N2_EQ_CME_LCL_EISR_BCE_BUSY_LOW = 26 ;
+static const uint8_t P9N2_EQ_CME_LCL_EISR_FINAL_VDM_DATA01 = 27 ;
+static const uint8_t P9N2_EQ_CME_LCL_EISR_FINAL_VDM_DATA01_LEN = 2 ;
+static const uint8_t P9N2_EQ_CME_LCL_EISR_COMM_RECVD = 29 ;
+static const uint8_t P9N2_EQ_CME_LCL_EISR_COMM_SEND_ACK = 30 ;
+static const uint8_t P9N2_EQ_CME_LCL_EISR_COMM_SEND_NACK = 31 ;
+static const uint8_t P9N2_EQ_CME_LCL_EISR_BLOCK_REG_WAKEUP_C0 = 32 ;
+static const uint8_t P9N2_EQ_CME_LCL_EISR_BLOCK_REG_WAKEUP_C1 = 33 ;
+static const uint8_t P9N2_EQ_CME_LCL_EISR_PMCR_UPDATE_C0 = 34 ;
+static const uint8_t P9N2_EQ_CME_LCL_EISR_PMCR_UPDATE_C1 = 35 ;
+static const uint8_t P9N2_EQ_CME_LCL_EISR_DOORBELL0_C0 = 36 ;
+static const uint8_t P9N2_EQ_CME_LCL_EISR_DOORBELL0_C1 = 37 ;
+static const uint8_t P9N2_EQ_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2 = 38 ;
+static const uint8_t P9N2_EQ_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2_LEN = 2 ;
+static const uint8_t P9N2_EQ_CME_LCL_EISR_DOORBELL1_C0 = 40 ;
+static const uint8_t P9N2_EQ_CME_LCL_EISR_DOORBELL1_C1 = 41 ;
+static const uint8_t P9N2_EQ_CME_LCL_EISR_RESERVED_42_43 = 42 ;
+static const uint8_t P9N2_EQ_CME_LCL_EISR_RESERVED_42_43_LEN = 2 ;
+
+static const uint8_t P9N2_EX_CME_LCL_EISR_DEBUGGER = 0 ;
+static const uint8_t P9N2_EX_CME_LCL_EISR_DEBUG_TRIGGER = 1 ;
+static const uint8_t P9N2_EX_CME_LCL_EISR_QUAD_CHECKSTOP = 2 ;
+static const uint8_t P9N2_EX_CME_LCL_EISR_PVREF_FAIL = 3 ;
+static const uint8_t P9N2_EX_CME_LCL_EISR_OCC_HEARTBEAT_LOST = 4 ;
+static const uint8_t P9N2_EX_CME_LCL_EISR_CORE_CHECKSTOP = 5 ;
+static const uint8_t P9N2_EX_CME_LCL_EISR_DROPOUT_DETECT = 6 ;
+static const uint8_t P9N2_EX_CME_LCL_EISR_INTERCME_DIRECT_IN_0 = 7 ;
+static const uint8_t P9N2_EX_CME_LCL_EISR_BCE_BUSY_HIGH = 8 ;
+static const uint8_t P9N2_EX_CME_LCL_EISR_BCE_TIMEOUT = 9 ;
+static const uint8_t P9N2_EX_CME_LCL_EISR_DOORBELL3_C0 = 10 ;
+static const uint8_t P9N2_EX_CME_LCL_EISR_DOORBELL3_C1 = 11 ;
+static const uint8_t P9N2_EX_CME_LCL_EISR_PC_INTR_PENDING_C0 = 12 ;
+static const uint8_t P9N2_EX_CME_LCL_EISR_PC_INTR_PENDING_C1 = 13 ;
+static const uint8_t P9N2_EX_CME_LCL_EISR_SPECIAL_WAKEUP_C0 = 14 ;
+static const uint8_t P9N2_EX_CME_LCL_EISR_SPECIAL_WAKEUP_C1 = 15 ;
+static const uint8_t P9N2_EX_CME_LCL_EISR_REG_WAKEUP_C0 = 16 ;
+static const uint8_t P9N2_EX_CME_LCL_EISR_REG_WAKEUP_C1 = 17 ;
+static const uint8_t P9N2_EX_CME_LCL_EISR_DOORBELL2_C0 = 18 ;
+static const uint8_t P9N2_EX_CME_LCL_EISR_DOORBELL2_C1 = 19 ;
+static const uint8_t P9N2_EX_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C0 = 20 ;
+static const uint8_t P9N2_EX_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C1 = 21 ;
+static const uint8_t P9N2_EX_CME_LCL_EISR_L2_PURGE_DONE = 22 ;
+static const uint8_t P9N2_EX_CME_LCL_EISR_NCU_PURGE_DONE = 23 ;
+static const uint8_t P9N2_EX_CME_LCL_EISR_CHTM_PURGE_DONE_C0 = 24 ;
+static const uint8_t P9N2_EX_CME_LCL_EISR_CHTM_PURGE_DONE_C1 = 25 ;
+static const uint8_t P9N2_EX_CME_LCL_EISR_BCE_BUSY_LOW = 26 ;
+static const uint8_t P9N2_EX_CME_LCL_EISR_FINAL_VDM_DATA01 = 27 ;
+static const uint8_t P9N2_EX_CME_LCL_EISR_FINAL_VDM_DATA01_LEN = 2 ;
+static const uint8_t P9N2_EX_CME_LCL_EISR_COMM_RECVD = 29 ;
+static const uint8_t P9N2_EX_CME_LCL_EISR_COMM_SEND_ACK = 30 ;
+static const uint8_t P9N2_EX_CME_LCL_EISR_COMM_SEND_NACK = 31 ;
+static const uint8_t P9N2_EX_CME_LCL_EISR_BLOCK_REG_WAKEUP_C0 = 32 ;
+static const uint8_t P9N2_EX_CME_LCL_EISR_BLOCK_REG_WAKEUP_C1 = 33 ;
+static const uint8_t P9N2_EX_CME_LCL_EISR_PMCR_UPDATE_C0 = 34 ;
+static const uint8_t P9N2_EX_CME_LCL_EISR_PMCR_UPDATE_C1 = 35 ;
+static const uint8_t P9N2_EX_CME_LCL_EISR_DOORBELL0_C0 = 36 ;
+static const uint8_t P9N2_EX_CME_LCL_EISR_DOORBELL0_C1 = 37 ;
+static const uint8_t P9N2_EX_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2 = 38 ;
+static const uint8_t P9N2_EX_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2_LEN = 2 ;
+static const uint8_t P9N2_EX_CME_LCL_EISR_DOORBELL1_C0 = 40 ;
+static const uint8_t P9N2_EX_CME_LCL_EISR_DOORBELL1_C1 = 41 ;
+static const uint8_t P9N2_EX_CME_LCL_EISR_RESERVED_42_43 = 42 ;
+static const uint8_t P9N2_EX_CME_LCL_EISR_RESERVED_42_43_LEN = 2 ;
+
+static const uint8_t P9N2_EQ_CME_LCL_EISTR_INTERRUPT_STATUS = 0 ;
+static const uint8_t P9N2_EQ_CME_LCL_EISTR_INTERRUPT_STATUS_LEN = 44 ;
+
+static const uint8_t P9N2_EX_CME_LCL_EISTR_INTERRUPT_STATUS = 0 ;
+static const uint8_t P9N2_EX_CME_LCL_EISTR_INTERRUPT_STATUS_LEN = 44 ;
+
+static const uint8_t P9N2_EQ_CME_LCL_EITR_INTERRUPT_TYPE = 0 ;
+static const uint8_t P9N2_EQ_CME_LCL_EITR_INTERRUPT_TYPE_LEN = 44 ;
+
+static const uint8_t P9N2_EX_CME_LCL_EITR_INTERRUPT_TYPE = 0 ;
+static const uint8_t P9N2_EX_CME_LCL_EITR_INTERRUPT_TYPE_LEN = 44 ;
+
+static const uint8_t P9N2_EX_CME_LCL_ICCR_COMM_ACK = 0 ;
+static const uint8_t P9N2_EX_CME_LCL_ICCR_COMM_NACK = 1 ;
+static const uint8_t P9N2_EX_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT = 5 ;
+static const uint8_t P9N2_EX_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT_LEN = 3 ;
+static const uint8_t P9N2_EX_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN = 9 ;
+static const uint8_t P9N2_EX_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN_LEN = 3 ;
+
+static const uint8_t P9N2_EQ_CME_LCL_ICRR_COMM_RECV = 0 ;
+static const uint8_t P9N2_EQ_CME_LCL_ICRR_COMM_RECV_LEN = 32 ;
+
+static const uint8_t P9N2_EX_CME_LCL_ICRR_COMM_RECV = 0 ;
+static const uint8_t P9N2_EX_CME_LCL_ICRR_COMM_RECV_LEN = 32 ;
+
+static const uint8_t P9N2_EX_CME_LCL_ICSR_COMM_SEND = 0 ;
+static const uint8_t P9N2_EX_CME_LCL_ICSR_COMM_SEND_LEN = 32 ;
+
+static const uint8_t P9N2_EX_CME_LCL_PECESR0_PECE_C_N_T0 = 0 ;
+static const uint8_t P9N2_EX_CME_LCL_PECESR0_PECE_C_N_T0_LEN = 6 ;
+static const uint8_t P9N2_EX_CME_LCL_PECESR0_PECE_C_N_T1 = 8 ;
+static const uint8_t P9N2_EX_CME_LCL_PECESR0_PECE_C_N_T1_LEN = 6 ;
+static const uint8_t P9N2_EX_CME_LCL_PECESR0_PECE_C_N_T2 = 16 ;
+static const uint8_t P9N2_EX_CME_LCL_PECESR0_PECE_C_N_T2_LEN = 6 ;
+static const uint8_t P9N2_EX_CME_LCL_PECESR0_PECE_C_N_T3 = 24 ;
+static const uint8_t P9N2_EX_CME_LCL_PECESR0_PECE_C_N_T3_LEN = 6 ;
+static const uint8_t P9N2_EX_CME_LCL_PECESR0_USE_PECE = 32 ;
+static const uint8_t P9N2_EX_CME_LCL_PECESR0_USE_PECE_LEN = 4 ;
+
+static const uint8_t P9N2_EX_CME_LCL_PECESR1_PECE_C_N_T0 = 0 ;
+static const uint8_t P9N2_EX_CME_LCL_PECESR1_PECE_C_N_T0_LEN = 6 ;
+static const uint8_t P9N2_EX_CME_LCL_PECESR1_PECE_C_N_T1 = 8 ;
+static const uint8_t P9N2_EX_CME_LCL_PECESR1_PECE_C_N_T1_LEN = 6 ;
+static const uint8_t P9N2_EX_CME_LCL_PECESR1_PECE_C_N_T2 = 16 ;
+static const uint8_t P9N2_EX_CME_LCL_PECESR1_PECE_C_N_T2_LEN = 6 ;
+static const uint8_t P9N2_EX_CME_LCL_PECESR1_PECE_C_N_T3 = 24 ;
+static const uint8_t P9N2_EX_CME_LCL_PECESR1_PECE_C_N_T3_LEN = 6 ;
+static const uint8_t P9N2_EX_CME_LCL_PECESR1_USE_PECE = 32 ;
+static const uint8_t P9N2_EX_CME_LCL_PECESR1_USE_PECE_LEN = 4 ;
+
+static const uint8_t P9N2_EQ_CME_LCL_SISR_PM_ENTRY_ACK_C0_ACTUAL = 0 ;
+static const uint8_t P9N2_EQ_CME_LCL_SISR_PM_ENTRY_ACK_C1_ACTUAL = 1 ;
+static const uint8_t P9N2_EQ_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C0_ACTUAL = 2 ;
+static const uint8_t P9N2_EQ_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C1_ACTUAL = 3 ;
+static const uint8_t P9N2_EQ_CME_LCL_SISR_PM_EXIT_C0_ACTUAL = 4 ;
+static const uint8_t P9N2_EQ_CME_LCL_SISR_PM_EXIT_C1_ACTUAL = 5 ;
+static const uint8_t P9N2_EQ_CME_LCL_SISR_RESERVED_6_8 = 6 ;
+static const uint8_t P9N2_EQ_CME_LCL_SISR_RESERVED_6_8_LEN = 3 ;
+static const uint8_t P9N2_EQ_CME_LCL_SISR_FUSED_CORE_MODE = 9 ;
+static const uint8_t P9N2_EQ_CME_LCL_SISR_PCBMUX_GRANT_C0 = 10 ;
+static const uint8_t P9N2_EQ_CME_LCL_SISR_PCBMUX_GRANT_C1 = 11 ;
+static const uint8_t P9N2_EQ_CME_LCL_SISR_PCB_RSP_OOB_0123_C0 = 12 ;
+static const uint8_t P9N2_EQ_CME_LCL_SISR_PCB_RSP_OOB_0123_C0_LEN = 4 ;
+static const uint8_t P9N2_EQ_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL = 16 ;
+static const uint8_t P9N2_EQ_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL = 17 ;
+static const uint8_t P9N2_EQ_CME_LCL_SISR_RESERVED_18_19 = 18 ;
+static const uint8_t P9N2_EQ_CME_LCL_SISR_RESERVED_18_19_LEN = 2 ;
+static const uint8_t P9N2_EQ_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C0 = 20 ;
+static const uint8_t P9N2_EQ_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C0_LEN = 4 ;
+static const uint8_t P9N2_EQ_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C1 = 24 ;
+static const uint8_t P9N2_EQ_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C1_LEN = 4 ;
+static const uint8_t P9N2_EQ_CME_LCL_SISR_RESERVED_28_29 = 28 ;
+static const uint8_t P9N2_EQ_CME_LCL_SISR_RESERVED_28_29_LEN = 2 ;
+static const uint8_t P9N2_EQ_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1 = 30 ;
+static const uint8_t P9N2_EQ_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN = 2 ;
+static const uint8_t P9N2_EQ_CME_LCL_SISR_PC_UNMASKED_ATTN_C0 = 32 ;
+static const uint8_t P9N2_EQ_CME_LCL_SISR_PC_UNMASKED_ATTN_C1 = 33 ;
+static const uint8_t P9N2_EQ_CME_LCL_SISR_PM_STATE_ACTIVE_C0 = 34 ;
+static const uint8_t P9N2_EQ_CME_LCL_SISR_PM_STATE_ACTIVE_C1 = 35 ;
+static const uint8_t P9N2_EQ_CME_LCL_SISR_PM_STATE_C0 = 36 ;
+static const uint8_t P9N2_EQ_CME_LCL_SISR_PM_STATE_C0_LEN = 4 ;
+static const uint8_t P9N2_EQ_CME_LCL_SISR_PM_STATE_C1 = 40 ;
+static const uint8_t P9N2_EQ_CME_LCL_SISR_PM_STATE_C1_LEN = 4 ;
+static const uint8_t P9N2_EQ_CME_LCL_SISR_PM_STATE_ALL_HV_C0 = 44 ;
+static const uint8_t P9N2_EQ_CME_LCL_SISR_PM_STATE_ALL_HV_C1 = 45 ;
+static const uint8_t P9N2_EQ_CME_LCL_SISR_PC_INSTR_RUNNING_C0 = 46 ;
+static const uint8_t P9N2_EQ_CME_LCL_SISR_PC_INSTR_RUNNING_C1 = 47 ;
+static const uint8_t P9N2_EQ_CME_LCL_SISR_PC_NON_HV_RUNNING_C0 = 48 ;
+static const uint8_t P9N2_EQ_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN = 4 ;
+static const uint8_t P9N2_EQ_CME_LCL_SISR_PC_NON_HV_RUNNING_C1 = 52 ;
+static const uint8_t P9N2_EQ_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN = 4 ;
+static const uint8_t P9N2_EQ_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0 = 56 ;
+static const uint8_t P9N2_EQ_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1 = 57 ;
+static const uint8_t P9N2_EQ_CME_LCL_SISR_PCB_RSP_OOB_9_C0 = 58 ;
+static const uint8_t P9N2_EQ_CME_LCL_SISR_PCB_RSP_OOB_9_C1 = 59 ;
+static const uint8_t P9N2_EQ_CME_LCL_SISR_PCB_RSP_OOB_0123_C1 = 60 ;
+static const uint8_t P9N2_EQ_CME_LCL_SISR_PCB_RSP_OOB_0123_C1_LEN = 4 ;
+
+static const uint8_t P9N2_EX_CME_LCL_SISR_PM_ENTRY_ACK_C0_ACTUAL = 0 ;
+static const uint8_t P9N2_EX_CME_LCL_SISR_PM_ENTRY_ACK_C1_ACTUAL = 1 ;
+static const uint8_t P9N2_EX_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C0_ACTUAL = 2 ;
+static const uint8_t P9N2_EX_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C1_ACTUAL = 3 ;
+static const uint8_t P9N2_EX_CME_LCL_SISR_PM_EXIT_C0_ACTUAL = 4 ;
+static const uint8_t P9N2_EX_CME_LCL_SISR_PM_EXIT_C1_ACTUAL = 5 ;
+static const uint8_t P9N2_EX_CME_LCL_SISR_RESERVED_6_8 = 6 ;
+static const uint8_t P9N2_EX_CME_LCL_SISR_RESERVED_6_8_LEN = 3 ;
+static const uint8_t P9N2_EX_CME_LCL_SISR_FUSED_CORE_MODE = 9 ;
+static const uint8_t P9N2_EX_CME_LCL_SISR_PCBMUX_GRANT_C0 = 10 ;
+static const uint8_t P9N2_EX_CME_LCL_SISR_PCBMUX_GRANT_C1 = 11 ;
+static const uint8_t P9N2_EX_CME_LCL_SISR_PCB_RSP_OOB_0123_C0 = 12 ;
+static const uint8_t P9N2_EX_CME_LCL_SISR_PCB_RSP_OOB_0123_C0_LEN = 4 ;
+static const uint8_t P9N2_EX_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL = 16 ;
+static const uint8_t P9N2_EX_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL = 17 ;
+static const uint8_t P9N2_EX_CME_LCL_SISR_RESERVED_18_19 = 18 ;
+static const uint8_t P9N2_EX_CME_LCL_SISR_RESERVED_18_19_LEN = 2 ;
+static const uint8_t P9N2_EX_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C0 = 20 ;
+static const uint8_t P9N2_EX_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C0_LEN = 4 ;
+static const uint8_t P9N2_EX_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C1 = 24 ;
+static const uint8_t P9N2_EX_CME_LCL_SISR_PC_THREAD_INSTR_RUNNING_C1_LEN = 4 ;
+static const uint8_t P9N2_EX_CME_LCL_SISR_RESERVED_28_29 = 28 ;
+static const uint8_t P9N2_EX_CME_LCL_SISR_RESERVED_28_29_LEN = 2 ;
+static const uint8_t P9N2_EX_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1 = 30 ;
+static const uint8_t P9N2_EX_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN = 2 ;
+static const uint8_t P9N2_EX_CME_LCL_SISR_PC_UNMASKED_ATTN_C0 = 32 ;
+static const uint8_t P9N2_EX_CME_LCL_SISR_PC_UNMASKED_ATTN_C1 = 33 ;
+static const uint8_t P9N2_EX_CME_LCL_SISR_PM_STATE_ACTIVE_C0 = 34 ;
+static const uint8_t P9N2_EX_CME_LCL_SISR_PM_STATE_ACTIVE_C1 = 35 ;
+static const uint8_t P9N2_EX_CME_LCL_SISR_PM_STATE_C0 = 36 ;
+static const uint8_t P9N2_EX_CME_LCL_SISR_PM_STATE_C0_LEN = 4 ;
+static const uint8_t P9N2_EX_CME_LCL_SISR_PM_STATE_C1 = 40 ;
+static const uint8_t P9N2_EX_CME_LCL_SISR_PM_STATE_C1_LEN = 4 ;
+static const uint8_t P9N2_EX_CME_LCL_SISR_PM_STATE_ALL_HV_C0 = 44 ;
+static const uint8_t P9N2_EX_CME_LCL_SISR_PM_STATE_ALL_HV_C1 = 45 ;
+static const uint8_t P9N2_EX_CME_LCL_SISR_PC_INSTR_RUNNING_C0 = 46 ;
+static const uint8_t P9N2_EX_CME_LCL_SISR_PC_INSTR_RUNNING_C1 = 47 ;
+static const uint8_t P9N2_EX_CME_LCL_SISR_PC_NON_HV_RUNNING_C0 = 48 ;
+static const uint8_t P9N2_EX_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN = 4 ;
+static const uint8_t P9N2_EX_CME_LCL_SISR_PC_NON_HV_RUNNING_C1 = 52 ;
+static const uint8_t P9N2_EX_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN = 4 ;
+static const uint8_t P9N2_EX_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0 = 56 ;
+static const uint8_t P9N2_EX_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1 = 57 ;
+static const uint8_t P9N2_EX_CME_LCL_SISR_PCB_RSP_OOB_9_C0 = 58 ;
+static const uint8_t P9N2_EX_CME_LCL_SISR_PCB_RSP_OOB_9_C1 = 59 ;
+static const uint8_t P9N2_EX_CME_LCL_SISR_PCB_RSP_OOB_0123_C1 = 60 ;
+static const uint8_t P9N2_EX_CME_LCL_SISR_PCB_RSP_OOB_0123_C1_LEN = 4 ;
+
+static const uint8_t P9N2_EX_CME_LCL_TSEL_FIT_SEL = 0 ;
+static const uint8_t P9N2_EX_CME_LCL_TSEL_FIT_SEL_LEN = 4 ;
+static const uint8_t P9N2_EX_CME_LCL_TSEL_WATCHDOG_SEL = 4 ;
+static const uint8_t P9N2_EX_CME_LCL_TSEL_WATCHDOG_SEL_LEN = 4 ;
+
+static const uint8_t P9N2_EQ_CME_SCOM_AFSR_INST_CYCLE_SAMPLE = 0 ;
+static const uint8_t P9N2_EQ_CME_SCOM_AFSR_INST_CYCLE_SAMPLE_LEN = 20 ;
+static const uint8_t P9N2_EQ_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE = 32 ;
+static const uint8_t P9N2_EQ_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE_LEN = 20 ;
+static const uint8_t P9N2_EQ_CME_SCOM_AFSR_SAMPLE_VALID = 63 ;
+
+static const uint8_t P9N2_EX_CME_SCOM_AFSR_INST_CYCLE_SAMPLE = 0 ;
+static const uint8_t P9N2_EX_CME_SCOM_AFSR_INST_CYCLE_SAMPLE_LEN = 20 ;
+static const uint8_t P9N2_EX_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE = 32 ;
+static const uint8_t P9N2_EX_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE_LEN = 20 ;
+static const uint8_t P9N2_EX_CME_SCOM_AFSR_SAMPLE_VALID = 63 ;
+
+static const uint8_t P9N2_EQ_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE = 0 ;
+static const uint8_t P9N2_EQ_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE_LEN = 20 ;
+static const uint8_t P9N2_EQ_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE = 32 ;
+static const uint8_t P9N2_EQ_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE_LEN = 20 ;
+
+static const uint8_t P9N2_EX_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE = 0 ;
+static const uint8_t P9N2_EX_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE_LEN = 20 ;
+static const uint8_t P9N2_EX_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE = 32 ;
+static const uint8_t P9N2_EX_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE_LEN = 20 ;
+
+static const uint8_t P9N2_EQ_CME_SCOM_BCEBAR0_BASE = 8 ;
+static const uint8_t P9N2_EQ_CME_SCOM_BCEBAR0_BASE_LEN = 36 ;
+static const uint8_t P9N2_EQ_CME_SCOM_BCEBAR0_RD_SCOPE = 57 ;
+static const uint8_t P9N2_EQ_CME_SCOM_BCEBAR0_RD_SCOPE_LEN = 2 ;
+static const uint8_t P9N2_EQ_CME_SCOM_BCEBAR0_WR_SCOPE = 59 ;
+static const uint8_t P9N2_EQ_CME_SCOM_BCEBAR0_VG_TARGET_SEL = 60 ;
+static const uint8_t P9N2_EQ_CME_SCOM_BCEBAR0_SIZE = 61 ;
+static const uint8_t P9N2_EQ_CME_SCOM_BCEBAR0_SIZE_LEN = 3 ;
+
+static const uint8_t P9N2_EX_CME_SCOM_BCEBAR0_BASE = 8 ;
+static const uint8_t P9N2_EX_CME_SCOM_BCEBAR0_BASE_LEN = 36 ;
+static const uint8_t P9N2_EX_CME_SCOM_BCEBAR0_RD_SCOPE = 57 ;
+static const uint8_t P9N2_EX_CME_SCOM_BCEBAR0_RD_SCOPE_LEN = 2 ;
+static const uint8_t P9N2_EX_CME_SCOM_BCEBAR0_WR_SCOPE = 59 ;
+static const uint8_t P9N2_EX_CME_SCOM_BCEBAR0_VG_TARGET_SEL = 60 ;
+static const uint8_t P9N2_EX_CME_SCOM_BCEBAR0_SIZE = 61 ;
+static const uint8_t P9N2_EX_CME_SCOM_BCEBAR0_SIZE_LEN = 3 ;
+
+static const uint8_t P9N2_EQ_CME_SCOM_BCEBAR1_BASE = 8 ;
+static const uint8_t P9N2_EQ_CME_SCOM_BCEBAR1_BASE_LEN = 36 ;
+static const uint8_t P9N2_EQ_CME_SCOM_BCEBAR1_RD_SCOPE = 57 ;
+static const uint8_t P9N2_EQ_CME_SCOM_BCEBAR1_RD_SCOPE_LEN = 2 ;
+static const uint8_t P9N2_EQ_CME_SCOM_BCEBAR1_WR_SCOPE = 59 ;
+static const uint8_t P9N2_EQ_CME_SCOM_BCEBAR1_VG_TARGET_SEL = 60 ;
+static const uint8_t P9N2_EQ_CME_SCOM_BCEBAR1_SIZE = 61 ;
+static const uint8_t P9N2_EQ_CME_SCOM_BCEBAR1_SIZE_LEN = 3 ;
+
+static const uint8_t P9N2_EX_CME_SCOM_BCEBAR1_BASE = 8 ;
+static const uint8_t P9N2_EX_CME_SCOM_BCEBAR1_BASE_LEN = 36 ;
+static const uint8_t P9N2_EX_CME_SCOM_BCEBAR1_RD_SCOPE = 57 ;
+static const uint8_t P9N2_EX_CME_SCOM_BCEBAR1_RD_SCOPE_LEN = 2 ;
+static const uint8_t P9N2_EX_CME_SCOM_BCEBAR1_WR_SCOPE = 59 ;
+static const uint8_t P9N2_EX_CME_SCOM_BCEBAR1_VG_TARGET_SEL = 60 ;
+static const uint8_t P9N2_EX_CME_SCOM_BCEBAR1_SIZE = 61 ;
+static const uint8_t P9N2_EX_CME_SCOM_BCEBAR1_SIZE_LEN = 3 ;
+
+static const uint8_t P9N2_EQ_CME_SCOM_BCECSR_BUSY = 0 ;
+static const uint8_t P9N2_EQ_CME_SCOM_BCECSR_ERROR = 1 ;
+static const uint8_t P9N2_EQ_CME_SCOM_BCECSR_RNW = 4 ;
+static const uint8_t P9N2_EQ_CME_SCOM_BCECSR_BARSEL = 5 ;
+static const uint8_t P9N2_EQ_CME_SCOM_BCECSR_PRIORITY = 6 ;
+static const uint8_t P9N2_EQ_CME_SCOM_BCECSR_INJECT_ERR = 7 ;
+static const uint8_t P9N2_EQ_CME_SCOM_BCECSR_TYPE = 13 ;
+static const uint8_t P9N2_EQ_CME_SCOM_BCECSR_TYPE_LEN = 3 ;
+static const uint8_t P9N2_EQ_CME_SCOM_BCECSR_NUM_BLOCKS = 17 ;
+static const uint8_t P9N2_EQ_CME_SCOM_BCECSR_NUM_BLOCKS_LEN = 11 ;
+static const uint8_t P9N2_EQ_CME_SCOM_BCECSR_SBASE = 28 ;
+static const uint8_t P9N2_EQ_CME_SCOM_BCECSR_SBASE_LEN = 12 ;
+static const uint8_t P9N2_EQ_CME_SCOM_BCECSR_MBASE = 42 ;
+static const uint8_t P9N2_EQ_CME_SCOM_BCECSR_MBASE_LEN = 22 ;
+
+static const uint8_t P9N2_EX_CME_SCOM_BCECSR_BUSY = 0 ;
+static const uint8_t P9N2_EX_CME_SCOM_BCECSR_ERROR = 1 ;
+static const uint8_t P9N2_EX_CME_SCOM_BCECSR_RNW = 4 ;
+static const uint8_t P9N2_EX_CME_SCOM_BCECSR_BARSEL = 5 ;
+static const uint8_t P9N2_EX_CME_SCOM_BCECSR_PRIORITY = 6 ;
+static const uint8_t P9N2_EX_CME_SCOM_BCECSR_INJECT_ERR = 7 ;
+static const uint8_t P9N2_EX_CME_SCOM_BCECSR_TYPE = 13 ;
+static const uint8_t P9N2_EX_CME_SCOM_BCECSR_TYPE_LEN = 3 ;
+static const uint8_t P9N2_EX_CME_SCOM_BCECSR_NUM_BLOCKS = 17 ;
+static const uint8_t P9N2_EX_CME_SCOM_BCECSR_NUM_BLOCKS_LEN = 11 ;
+static const uint8_t P9N2_EX_CME_SCOM_BCECSR_SBASE = 28 ;
+static const uint8_t P9N2_EX_CME_SCOM_BCECSR_SBASE_LEN = 12 ;
+static const uint8_t P9N2_EX_CME_SCOM_BCECSR_MBASE = 42 ;
+static const uint8_t P9N2_EX_CME_SCOM_BCECSR_MBASE_LEN = 22 ;
+
+static const uint8_t P9N2_EQ_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT = 0 ;
+static const uint8_t P9N2_EQ_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT_LEN = 24 ;
+static const uint8_t P9N2_EQ_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT = 24 ;
+static const uint8_t P9N2_EQ_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT_LEN = 8 ;
+static const uint8_t P9N2_EQ_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT = 32 ;
+static const uint8_t P9N2_EQ_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT_LEN = 24 ;
+static const uint8_t P9N2_EQ_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT = 56 ;
+static const uint8_t P9N2_EQ_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT_LEN = 8 ;
+
+static const uint8_t P9N2_EX_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT = 0 ;
+static const uint8_t P9N2_EX_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT_LEN = 24 ;
+static const uint8_t P9N2_EX_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT = 24 ;
+static const uint8_t P9N2_EX_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT_LEN = 8 ;
+static const uint8_t P9N2_EX_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT = 32 ;
+static const uint8_t P9N2_EX_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT_LEN = 24 ;
+static const uint8_t P9N2_EX_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT = 56 ;
+static const uint8_t P9N2_EX_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT_LEN = 8 ;
+
+static const uint8_t P9N2_EQ_CME_SCOM_EIIR_DEBUGGER = 0 ;
+static const uint8_t P9N2_EQ_CME_SCOM_EIIR_DEBUG_TRIGGER = 1 ;
+static const uint8_t P9N2_EQ_CME_SCOM_EIIR_BCE_TIMEOUT = 9 ;
+static const uint8_t P9N2_EQ_CME_SCOM_EIIR_PC_INTR_PENDING_C0 = 12 ;
+static const uint8_t P9N2_EQ_CME_SCOM_EIIR_PC_INTR_PENDING_C1 = 13 ;
+static const uint8_t P9N2_EQ_CME_SCOM_EIIR_SPECIAL_WAKEUP_C0 = 14 ;
+static const uint8_t P9N2_EQ_CME_SCOM_EIIR_SPECIAL_WAKEUP_C1 = 15 ;
+static const uint8_t P9N2_EQ_CME_SCOM_EIIR_REG_WAKEUP_C0 = 16 ;
+static const uint8_t P9N2_EQ_CME_SCOM_EIIR_REG_WAKEUP_C1 = 17 ;
+static const uint8_t P9N2_EQ_CME_SCOM_EIIR_PC_PM_STATE_ACTIVE_C0 = 20 ;
+static const uint8_t P9N2_EQ_CME_SCOM_EIIR_PC_PM_STATE_ACTIVE_C1 = 21 ;
+static const uint8_t P9N2_EQ_CME_SCOM_EIIR_L2_PURGE_DONE = 22 ;
+static const uint8_t P9N2_EQ_CME_SCOM_EIIR_NCU_PURGE_DONE = 23 ;
+static const uint8_t P9N2_EQ_CME_SCOM_EIIR_CHTM_PURGE_DONE_C0 = 24 ;
+static const uint8_t P9N2_EQ_CME_SCOM_EIIR_CHTM_PURGE_DONE_C1 = 25 ;
+
+static const uint8_t P9N2_EX_CME_SCOM_EIIR_DEBUGGER = 0 ;
+static const uint8_t P9N2_EX_CME_SCOM_EIIR_DEBUG_TRIGGER = 1 ;
+static const uint8_t P9N2_EX_CME_SCOM_EIIR_BCE_TIMEOUT = 9 ;
+static const uint8_t P9N2_EX_CME_SCOM_EIIR_PC_INTR_PENDING_C0 = 12 ;
+static const uint8_t P9N2_EX_CME_SCOM_EIIR_PC_INTR_PENDING_C1 = 13 ;
+static const uint8_t P9N2_EX_CME_SCOM_EIIR_SPECIAL_WAKEUP_C0 = 14 ;
+static const uint8_t P9N2_EX_CME_SCOM_EIIR_SPECIAL_WAKEUP_C1 = 15 ;
+static const uint8_t P9N2_EX_CME_SCOM_EIIR_REG_WAKEUP_C0 = 16 ;
+static const uint8_t P9N2_EX_CME_SCOM_EIIR_REG_WAKEUP_C1 = 17 ;
+static const uint8_t P9N2_EX_CME_SCOM_EIIR_PC_PM_STATE_ACTIVE_C0 = 20 ;
+static const uint8_t P9N2_EX_CME_SCOM_EIIR_PC_PM_STATE_ACTIVE_C1 = 21 ;
+static const uint8_t P9N2_EX_CME_SCOM_EIIR_L2_PURGE_DONE = 22 ;
+static const uint8_t P9N2_EX_CME_SCOM_EIIR_NCU_PURGE_DONE = 23 ;
+static const uint8_t P9N2_EX_CME_SCOM_EIIR_CHTM_PURGE_DONE_C0 = 24 ;
+static const uint8_t P9N2_EX_CME_SCOM_EIIR_CHTM_PURGE_DONE_C1 = 25 ;
+
+static const uint8_t P9N2_EQ_CME_SCOM_FLAGS_DATA = 0 ;
+static const uint8_t P9N2_EQ_CME_SCOM_FLAGS_DATA_LEN = 32 ;
+
+static const uint8_t P9N2_EX_CME_SCOM_FLAGS_DATA = 0 ;
+static const uint8_t P9N2_EX_CME_SCOM_FLAGS_DATA_LEN = 32 ;
+
+static const uint8_t P9N2_EQ_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD = 0 ;
+static const uint8_t P9N2_EQ_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD_LEN = 24 ;
+static const uint8_t P9N2_EQ_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD = 24 ;
+static const uint8_t P9N2_EQ_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD_LEN = 8 ;
+static const uint8_t P9N2_EQ_CME_SCOM_IDCR_DROPOUT_TIMER_MODE = 32 ;
+static const uint8_t P9N2_EQ_CME_SCOM_IDCR_DROPOUT_CHAR_MODE = 33 ;
+static const uint8_t P9N2_EQ_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE = 34 ;
+static const uint8_t P9N2_EQ_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE_LEN = 2 ;
+static const uint8_t P9N2_EQ_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE = 36 ;
+static const uint8_t P9N2_EQ_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE_LEN = 2 ;
+static const uint8_t P9N2_EQ_CME_SCOM_IDCR_CACHE_DROPOUT_ENABLE = 38 ;
+static const uint8_t P9N2_EQ_CME_SCOM_IDCR_SPARE = 39 ;
+static const uint8_t P9N2_EQ_CME_SCOM_IDCR_DROPOUT_NOTIFY_ENABLE = 40 ;
+static const uint8_t P9N2_EQ_CME_SCOM_IDCR_SPARE41_43 = 41 ;
+static const uint8_t P9N2_EQ_CME_SCOM_IDCR_SPARE41_43_LEN = 3 ;
+static const uint8_t P9N2_EQ_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE = 59 ;
+static const uint8_t P9N2_EQ_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE_LEN = 5 ;
+
+static const uint8_t P9N2_EX_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD = 0 ;
+static const uint8_t P9N2_EX_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD_LEN = 24 ;
+static const uint8_t P9N2_EX_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD = 24 ;
+static const uint8_t P9N2_EX_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD_LEN = 8 ;
+static const uint8_t P9N2_EX_CME_SCOM_IDCR_DROPOUT_TIMER_MODE = 32 ;
+static const uint8_t P9N2_EX_CME_SCOM_IDCR_DROPOUT_CHAR_MODE = 33 ;
+static const uint8_t P9N2_EX_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE = 34 ;
+static const uint8_t P9N2_EX_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE_LEN = 2 ;
+static const uint8_t P9N2_EX_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE = 36 ;
+static const uint8_t P9N2_EX_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE_LEN = 2 ;
+static const uint8_t P9N2_EX_CME_SCOM_IDCR_CACHE_DROPOUT_ENABLE = 38 ;
+static const uint8_t P9N2_EX_CME_SCOM_IDCR_SPARE = 39 ;
+static const uint8_t P9N2_EX_CME_SCOM_IDCR_DROPOUT_NOTIFY_ENABLE = 40 ;
+static const uint8_t P9N2_EX_CME_SCOM_IDCR_SPARE41_43 = 41 ;
+static const uint8_t P9N2_EX_CME_SCOM_IDCR_SPARE41_43_LEN = 3 ;
+static const uint8_t P9N2_EX_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE = 59 ;
+static const uint8_t P9N2_EX_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE_LEN = 5 ;
+
+static const uint8_t P9N2_EQ_CME_SCOM_LFIR_PPE_INTERNAL_ERROR = 0 ;
+static const uint8_t P9N2_EQ_CME_SCOM_LFIR_PPE_EXTERNAL_ERROR = 1 ;
+static const uint8_t P9N2_EQ_CME_SCOM_LFIR_PPE_PROGRESS_ERROR = 2 ;
+static const uint8_t P9N2_EQ_CME_SCOM_LFIR_PPE_BREAKPOINT_ERROR = 3 ;
+static const uint8_t P9N2_EQ_CME_SCOM_LFIR_PPE_WATCHDOG = 4 ;
+static const uint8_t P9N2_EQ_CME_SCOM_LFIR_PPE_HALTED = 5 ;
+static const uint8_t P9N2_EQ_CME_SCOM_LFIR_PPE_DEBUG_TRIGGER = 6 ;
+static const uint8_t P9N2_EQ_CME_SCOM_LFIR_SRAM_UE = 7 ;
+static const uint8_t P9N2_EQ_CME_SCOM_LFIR_SRAM_CE = 8 ;
+static const uint8_t P9N2_EQ_CME_SCOM_LFIR_SRAM_SCRUB_ERR = 9 ;
+static const uint8_t P9N2_EQ_CME_SCOM_LFIR_BCE_ERROR = 10 ;
+static const uint8_t P9N2_EQ_CME_SCOM_LFIR_SPARE11 = 11 ;
+static const uint8_t P9N2_EQ_CME_SCOM_LFIR_SPARE12 = 12 ;
+static const uint8_t P9N2_EQ_CME_SCOM_LFIR_C0_IVRM_DROPOUT = 13 ;
+static const uint8_t P9N2_EQ_CME_SCOM_LFIR_C1_IVRM_DROPOUT = 14 ;
+static const uint8_t P9N2_EQ_CME_SCOM_LFIR_CACHE_IVRM_DROPOUT = 15 ;
+static const uint8_t P9N2_EQ_CME_SCOM_LFIR_EXTREME_DROOP_ERR = 16 ;
+static const uint8_t P9N2_EQ_CME_SCOM_LFIR_LARGE_DROOP_ERR = 17 ;
+static const uint8_t P9N2_EQ_CME_SCOM_LFIR_SMALL_DROOP_ERR = 18 ;
+static const uint8_t P9N2_EQ_CME_SCOM_LFIR_UNEXPECTED_DROOP_ENCODE = 19 ;
+static const uint8_t P9N2_EQ_CME_SCOM_LFIR_FIR_PARITY_ERR_DUP = 20 ;
+static const uint8_t P9N2_EQ_CME_SCOM_LFIR_FIR_PARITY_ERR = 21 ;
+
+static const uint8_t P9N2_EX_CME_SCOM_LFIR_PPE_INTERNAL_ERROR = 0 ;
+static const uint8_t P9N2_EX_CME_SCOM_LFIR_PPE_EXTERNAL_ERROR = 1 ;
+static const uint8_t P9N2_EX_CME_SCOM_LFIR_PPE_PROGRESS_ERROR = 2 ;
+static const uint8_t P9N2_EX_CME_SCOM_LFIR_PPE_BREAKPOINT_ERROR = 3 ;
+static const uint8_t P9N2_EX_CME_SCOM_LFIR_PPE_WATCHDOG = 4 ;
+static const uint8_t P9N2_EX_CME_SCOM_LFIR_PPE_HALTED = 5 ;
+static const uint8_t P9N2_EX_CME_SCOM_LFIR_PPE_DEBUG_TRIGGER = 6 ;
+static const uint8_t P9N2_EX_CME_SCOM_LFIR_SRAM_UE = 7 ;
+static const uint8_t P9N2_EX_CME_SCOM_LFIR_SRAM_CE = 8 ;
+static const uint8_t P9N2_EX_CME_SCOM_LFIR_SRAM_SCRUB_ERR = 9 ;
+static const uint8_t P9N2_EX_CME_SCOM_LFIR_BCE_ERROR = 10 ;
+static const uint8_t P9N2_EX_CME_SCOM_LFIR_SPARE11 = 11 ;
+static const uint8_t P9N2_EX_CME_SCOM_LFIR_SPARE12 = 12 ;
+static const uint8_t P9N2_EX_CME_SCOM_LFIR_C0_IVRM_DROPOUT = 13 ;
+static const uint8_t P9N2_EX_CME_SCOM_LFIR_C1_IVRM_DROPOUT = 14 ;
+static const uint8_t P9N2_EX_CME_SCOM_LFIR_CACHE_IVRM_DROPOUT = 15 ;
+static const uint8_t P9N2_EX_CME_SCOM_LFIR_EXTREME_DROOP_ERR = 16 ;
+static const uint8_t P9N2_EX_CME_SCOM_LFIR_LARGE_DROOP_ERR = 17 ;
+static const uint8_t P9N2_EX_CME_SCOM_LFIR_SMALL_DROOP_ERR = 18 ;
+static const uint8_t P9N2_EX_CME_SCOM_LFIR_UNEXPECTED_DROOP_ENCODE = 19 ;
+static const uint8_t P9N2_EX_CME_SCOM_LFIR_FIR_PARITY_ERR_DUP = 20 ;
+static const uint8_t P9N2_EX_CME_SCOM_LFIR_FIR_PARITY_ERR = 21 ;
+
+static const uint8_t P9N2_EQ_CME_SCOM_LFIRACT0_FIR_ACTION0 = 0 ;
+static const uint8_t P9N2_EQ_CME_SCOM_LFIRACT0_FIR_ACTION0_LEN = 22 ;
+
+static const uint8_t P9N2_EX_CME_SCOM_LFIRACT0_FIR_ACTION0 = 0 ;
+static const uint8_t P9N2_EX_CME_SCOM_LFIRACT0_FIR_ACTION0_LEN = 22 ;
+
+static const uint8_t P9N2_EQ_CME_SCOM_LFIRACT1_FIR_ACTION1 = 0 ;
+static const uint8_t P9N2_EQ_CME_SCOM_LFIRACT1_FIR_ACTION1_LEN = 22 ;
+
+static const uint8_t P9N2_EX_CME_SCOM_LFIRACT1_FIR_ACTION1 = 0 ;
+static const uint8_t P9N2_EX_CME_SCOM_LFIRACT1_FIR_ACTION1_LEN = 22 ;
+
+static const uint8_t P9N2_EQ_CME_SCOM_LFIRMASK_FIR_MASK = 0 ;
+static const uint8_t P9N2_EQ_CME_SCOM_LFIRMASK_FIR_MASK_LEN = 22 ;
+
+static const uint8_t P9N2_EX_CME_SCOM_LFIRMASK_FIR_MASK = 0 ;
+static const uint8_t P9N2_EX_CME_SCOM_LFIRMASK_FIR_MASK_LEN = 22 ;
+
+static const uint8_t P9N2_EQ_CME_SCOM_LMCR_PMCR_OVERRIDE_EN = 0 ;
+static const uint8_t P9N2_EQ_CME_SCOM_LMCR_PSCR_OVERRIDE_EN = 1 ;
+static const uint8_t P9N2_EQ_CME_SCOM_LMCR_PMSR_OVERRIDE_EN = 2 ;
+static const uint8_t P9N2_EQ_CME_SCOM_LMCR_BCECSR_OVERRIDE_EN = 3 ;
+static const uint8_t P9N2_EQ_CME_SCOM_LMCR_IDR_LCL_SAMPLE_EN = 4 ;
+static const uint8_t P9N2_EQ_CME_SCOM_LMCR_VDM_LCL_SAMPLE_EN = 5 ;
+static const uint8_t P9N2_EQ_CME_SCOM_LMCR_FREQ_LCL_SAMPLE_EN = 6 ;
+static const uint8_t P9N2_EQ_CME_SCOM_LMCR_LOCK_PCB_ON_ERR = 7 ;
+static const uint8_t P9N2_EQ_CME_SCOM_LMCR_QUEUED_WR_EN = 8 ;
+static const uint8_t P9N2_EQ_CME_SCOM_LMCR_QUEUED_RD_EN = 9 ;
+static const uint8_t P9N2_EQ_CME_SCOM_LMCR_MASK_PURGE_INTERFACE = 10 ;
+static const uint8_t P9N2_EQ_CME_SCOM_LMCR_AUTO_BLOCK_REG_WAKEUP_DISABLE = 11 ;
+static const uint8_t P9N2_EQ_CME_SCOM_LMCR_C0_AUTO_SPECIAL_WAKEUP_DISABLE = 12 ;
+static const uint8_t P9N2_EQ_CME_SCOM_LMCR_C1_AUTO_SPECIAL_WAKEUP_DISABLE = 13 ;
+static const uint8_t P9N2_EQ_CME_SCOM_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE = 14 ;
+static const uint8_t P9N2_EQ_CME_SCOM_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE = 15 ;
+static const uint8_t P9N2_EQ_CME_SCOM_LMCR_STOP_OVERRIDE_MODE = 16 ;
+static const uint8_t P9N2_EQ_CME_SCOM_LMCR_STOP_ACTIVE_MASK = 17 ;
+static const uint8_t P9N2_EQ_CME_SCOM_LMCR_AUTO_STOP1_DISABLE = 18 ;
+static const uint8_t P9N2_EQ_CME_SCOM_LMCR_STOP1_ACTIVE_ENABLE = 19 ;
+static const uint8_t P9N2_EQ_CME_SCOM_LMCR_FENCE_EISR = 20 ;
+static const uint8_t P9N2_EQ_CME_SCOM_LMCR_PC_DISABLE_DROOP = 21 ;
+static const uint8_t P9N2_EQ_CME_SCOM_LMCR_BLOCK_PM_EXIT_DISABLE = 22 ;
+static const uint8_t P9N2_EQ_CME_SCOM_LMCR_SPARE_23 = 23 ;
+static const uint8_t P9N2_EQ_CME_SCOM_LMCR_AVG_FREQ_TSEL = 24 ;
+static const uint8_t P9N2_EQ_CME_SCOM_LMCR_AVG_FREQ_TSEL_LEN = 4 ;
+static const uint8_t P9N2_EQ_CME_SCOM_LMCR_SPARE_28_31 = 28 ;
+static const uint8_t P9N2_EQ_CME_SCOM_LMCR_SPARE_28_31_LEN = 4 ;
+static const uint8_t P9N2_EQ_CME_SCOM_LMCR_RESET_IMPRECISE_QERR = 32 ;
+static const uint8_t P9N2_EQ_CME_SCOM_LMCR_SET_ECC_INJECT_ERR = 33 ;
+static const uint8_t P9N2_EQ_CME_SCOM_LMCR_SPARE_34 = 34 ;
+static const uint8_t P9N2_EQ_CME_SCOM_LMCR_OOB_ERR_DISABLE = 35 ;
+static const uint8_t P9N2_EQ_CME_SCOM_LMCR_OOB_ERR_DISABLE_LEN = 5 ;
+
+static const uint8_t P9N2_EX_CME_SCOM_LMCR_PMCR_OVERRIDE_EN = 0 ;
+static const uint8_t P9N2_EX_CME_SCOM_LMCR_PSCR_OVERRIDE_EN = 1 ;
+static const uint8_t P9N2_EX_CME_SCOM_LMCR_PMSR_OVERRIDE_EN = 2 ;
+static const uint8_t P9N2_EX_CME_SCOM_LMCR_BCECSR_OVERRIDE_EN = 3 ;
+static const uint8_t P9N2_EX_CME_SCOM_LMCR_IDR_LCL_SAMPLE_EN = 4 ;
+static const uint8_t P9N2_EX_CME_SCOM_LMCR_VDM_LCL_SAMPLE_EN = 5 ;
+static const uint8_t P9N2_EX_CME_SCOM_LMCR_FREQ_LCL_SAMPLE_EN = 6 ;
+static const uint8_t P9N2_EX_CME_SCOM_LMCR_LOCK_PCB_ON_ERR = 7 ;
+static const uint8_t P9N2_EX_CME_SCOM_LMCR_QUEUED_WR_EN = 8 ;
+static const uint8_t P9N2_EX_CME_SCOM_LMCR_QUEUED_RD_EN = 9 ;
+static const uint8_t P9N2_EX_CME_SCOM_LMCR_MASK_PURGE_INTERFACE = 10 ;
+static const uint8_t P9N2_EX_CME_SCOM_LMCR_AUTO_BLOCK_REG_WAKEUP_DISABLE = 11 ;
+static const uint8_t P9N2_EX_CME_SCOM_LMCR_C0_AUTO_SPECIAL_WAKEUP_DISABLE = 12 ;
+static const uint8_t P9N2_EX_CME_SCOM_LMCR_C1_AUTO_SPECIAL_WAKEUP_DISABLE = 13 ;
+static const uint8_t P9N2_EX_CME_SCOM_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE = 14 ;
+static const uint8_t P9N2_EX_CME_SCOM_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE = 15 ;
+static const uint8_t P9N2_EX_CME_SCOM_LMCR_STOP_OVERRIDE_MODE = 16 ;
+static const uint8_t P9N2_EX_CME_SCOM_LMCR_STOP_ACTIVE_MASK = 17 ;
+static const uint8_t P9N2_EX_CME_SCOM_LMCR_AUTO_STOP1_DISABLE = 18 ;
+static const uint8_t P9N2_EX_CME_SCOM_LMCR_STOP1_ACTIVE_ENABLE = 19 ;
+static const uint8_t P9N2_EX_CME_SCOM_LMCR_FENCE_EISR = 20 ;
+static const uint8_t P9N2_EX_CME_SCOM_LMCR_PC_DISABLE_DROOP = 21 ;
+static const uint8_t P9N2_EX_CME_SCOM_LMCR_BLOCK_PM_EXIT_DISABLE = 22 ;
+static const uint8_t P9N2_EX_CME_SCOM_LMCR_SPARE_23 = 23 ;
+static const uint8_t P9N2_EX_CME_SCOM_LMCR_AVG_FREQ_TSEL = 24 ;
+static const uint8_t P9N2_EX_CME_SCOM_LMCR_AVG_FREQ_TSEL_LEN = 4 ;
+static const uint8_t P9N2_EX_CME_SCOM_LMCR_SPARE_28_31 = 28 ;
+static const uint8_t P9N2_EX_CME_SCOM_LMCR_SPARE_28_31_LEN = 4 ;
+static const uint8_t P9N2_EX_CME_SCOM_LMCR_RESET_IMPRECISE_QERR = 32 ;
+static const uint8_t P9N2_EX_CME_SCOM_LMCR_SET_ECC_INJECT_ERR = 33 ;
+static const uint8_t P9N2_EX_CME_SCOM_LMCR_SPARE_34 = 34 ;
+static const uint8_t P9N2_EX_CME_SCOM_LMCR_OOB_ERR_DISABLE = 35 ;
+static const uint8_t P9N2_EX_CME_SCOM_LMCR_OOB_ERR_DISABLE_LEN = 5 ;
+
+static const uint8_t P9N2_EQ_CME_SCOM_PMCRS0_DATA = 0 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PMCRS0_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_EX_CME_SCOM_PMCRS0_DATA = 0 ;
+static const uint8_t P9N2_EX_CME_SCOM_PMCRS0_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_EQ_CME_SCOM_PMCRS1_DATA = 0 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PMCRS1_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_EX_CME_SCOM_PMCRS1_DATA = 0 ;
+static const uint8_t P9N2_EX_CME_SCOM_PMCRS1_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_EQ_CME_SCOM_PMSRS0_DATA = 0 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PMSRS0_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_EX_CME_SCOM_PMSRS0_DATA = 0 ;
+static const uint8_t P9N2_EX_CME_SCOM_PMSRS0_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_EQ_CME_SCOM_PMSRS1_DATA = 0 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PMSRS1_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_EX_CME_SCOM_PMSRS1_DATA = 0 ;
+static const uint8_t P9N2_EX_CME_SCOM_PMSRS1_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS00_SPARE0 = 0 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS00_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS00_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS00_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS00_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS00_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS00_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS00_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS00_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS00_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS00_SPARE0 = 0 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS00_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS00_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS00_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS00_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS00_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS00_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS00_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS00_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS00_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS01_SPARE0 = 0 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS01_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS01_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS01_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS01_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS01_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS01_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS01_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS01_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS01_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS01_SPARE0 = 0 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS01_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS01_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS01_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS01_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS01_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS01_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS01_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS01_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS01_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS02_SPARE0 = 0 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS02_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS02_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS02_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS02_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS02_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS02_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS02_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS02_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS02_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS02_SPARE0 = 0 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS02_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS02_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS02_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS02_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS02_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS02_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS02_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS02_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS02_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS03_SPARE0 = 0 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS03_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS03_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS03_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS03_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS03_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS03_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS03_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS03_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS03_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS03_SPARE0 = 0 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS03_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS03_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS03_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS03_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS03_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS03_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS03_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS03_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS03_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS10_SPARE0 = 0 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS10_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS10_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS10_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS10_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS10_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS10_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS10_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS10_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS10_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS10_SPARE0 = 0 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS10_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS10_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS10_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS10_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS10_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS10_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS10_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS10_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS10_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS11_SPARE0 = 0 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS11_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS11_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS11_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS11_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS11_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS11_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS11_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS11_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS11_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS11_SPARE0 = 0 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS11_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS11_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS11_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS11_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS11_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS11_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS11_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS11_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS11_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS12_SPARE0 = 0 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS12_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS12_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS12_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS12_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS12_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS12_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS12_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS12_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS12_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS12_SPARE0 = 0 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS12_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS12_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS12_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS12_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS12_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS12_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS12_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS12_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS12_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS13_SPARE0 = 0 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS13_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS13_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS13_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS13_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS13_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS13_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS13_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS13_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS13_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_EQ_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS13_SPARE0 = 0 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS13_OS_STATUS_DISABLE_A_N = 1 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS13_STATE_LOSS_ENABLE_A_N = 2 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS13_EXIT_CRITERION_A_N = 3 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N = 4 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N_LEN = 4 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS13_HYP_VIRT_EXIT_ENABLE = 8 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS13_EXT_EBB_EXIT_ENABLE = 9 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS13_EXT_RESUME_EXIT_ENABLE = 10 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS13_EXT_EXIT_ENABLE = 11 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS13_DEC_EXIT_ENABLE = 12 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS13_HMI_EXIT_ENABLE = 13 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N = 14 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N_LEN = 2 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N = 16 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N_LEN = 4 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N = 20 ;
+static const uint8_t P9N2_EX_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N_LEN = 4 ;
+
+static const uint8_t P9N2_EQ_CME_SCOM_QFMR_TIMEBASE = 0 ;
+static const uint8_t P9N2_EQ_CME_SCOM_QFMR_TIMEBASE_LEN = 32 ;
+static const uint8_t P9N2_EQ_CME_SCOM_QFMR_CYCLES = 32 ;
+static const uint8_t P9N2_EQ_CME_SCOM_QFMR_CYCLES_LEN = 32 ;
+
+static const uint8_t P9N2_EX_CME_SCOM_QFMR_TIMEBASE = 0 ;
+static const uint8_t P9N2_EX_CME_SCOM_QFMR_TIMEBASE_LEN = 32 ;
+static const uint8_t P9N2_EX_CME_SCOM_QFMR_CYCLES = 32 ;
+static const uint8_t P9N2_EX_CME_SCOM_QFMR_CYCLES_LEN = 32 ;
+
+static const uint8_t P9N2_EQ_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT = 0 ;
+static const uint8_t P9N2_EQ_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT_LEN = 24 ;
+static const uint8_t P9N2_EQ_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT = 24 ;
+static const uint8_t P9N2_EQ_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT_LEN = 8 ;
+static const uint8_t P9N2_EQ_CME_SCOM_QIDSR_DROPOUT_SAMPLE = 32 ;
+static const uint8_t P9N2_EQ_CME_SCOM_QIDSR_DROPOUT_SAMPLE_LEN = 3 ;
+
+static const uint8_t P9N2_EX_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT = 0 ;
+static const uint8_t P9N2_EX_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT_LEN = 24 ;
+static const uint8_t P9N2_EX_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT = 24 ;
+static const uint8_t P9N2_EX_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT_LEN = 8 ;
+static const uint8_t P9N2_EX_CME_SCOM_QIDSR_DROPOUT_SAMPLE = 32 ;
+static const uint8_t P9N2_EX_CME_SCOM_QIDSR_DROPOUT_SAMPLE_LEN = 3 ;
+
+static const uint8_t P9N2_EQ_CME_SCOM_SICR_PM_ENTRY_ACK_C0 = 0 ;
+static const uint8_t P9N2_EQ_CME_SCOM_SICR_PM_ENTRY_ACK_C1 = 1 ;
+static const uint8_t P9N2_EQ_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C0 = 2 ;
+static const uint8_t P9N2_EQ_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C1 = 3 ;
+static const uint8_t P9N2_EQ_CME_SCOM_SICR_PM_EXIT_C0 = 4 ;
+static const uint8_t P9N2_EQ_CME_SCOM_SICR_PM_EXIT_C1 = 5 ;
+static const uint8_t P9N2_EQ_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0 = 6 ;
+static const uint8_t P9N2_EQ_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1 = 7 ;
+static const uint8_t P9N2_EQ_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0 = 8 ;
+static const uint8_t P9N2_EQ_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1 = 9 ;
+static const uint8_t P9N2_EQ_CME_SCOM_SICR_PCBMUX_REQ_C0 = 10 ;
+static const uint8_t P9N2_EQ_CME_SCOM_SICR_PCBMUX_REQ_C1 = 11 ;
+static const uint8_t P9N2_EQ_CME_SCOM_SICR_RESERVED_12_15 = 12 ;
+static const uint8_t P9N2_EQ_CME_SCOM_SICR_RESERVED_12_15_LEN = 4 ;
+static const uint8_t P9N2_EQ_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C0 = 16 ;
+static const uint8_t P9N2_EQ_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C1 = 17 ;
+static const uint8_t P9N2_EQ_CME_SCOM_SICR_L2_PURGE = 18 ;
+static const uint8_t P9N2_EQ_CME_SCOM_SICR_L2_PURGE_ABORT = 19 ;
+static const uint8_t P9N2_EQ_CME_SCOM_SICR_PC_THROTTLE_REQ = 20 ;
+static const uint8_t P9N2_EQ_CME_SCOM_SICR_NCU_TLBIE_QUIESCE = 21 ;
+static const uint8_t P9N2_EQ_CME_SCOM_SICR_NCU_PURGE = 22 ;
+static const uint8_t P9N2_EQ_CME_SCOM_SICR_NCU_PURGE_ABORT = 23 ;
+static const uint8_t P9N2_EQ_CME_SCOM_SICR_CHTM_PURGE_C0 = 24 ;
+static const uint8_t P9N2_EQ_CME_SCOM_SICR_CHTM_PURGE_C1 = 25 ;
+static const uint8_t P9N2_EQ_CME_SCOM_SICR_HMI_REQUEST_C0 = 26 ;
+static const uint8_t P9N2_EQ_CME_SCOM_SICR_HMI_REQUEST_C1 = 27 ;
+static const uint8_t P9N2_EQ_CME_SCOM_SICR_PPM_SPARE_OUT_C0 = 28 ;
+static const uint8_t P9N2_EQ_CME_SCOM_SICR_PPM_SPARE_OUT_C1 = 29 ;
+static const uint8_t P9N2_EQ_CME_SCOM_SICR_RESERVED_30_31 = 30 ;
+static const uint8_t P9N2_EQ_CME_SCOM_SICR_RESERVED_30_31_LEN = 2 ;
+
+static const uint8_t P9N2_EX_CME_SCOM_SICR_PM_ENTRY_ACK_C0 = 0 ;
+static const uint8_t P9N2_EX_CME_SCOM_SICR_PM_ENTRY_ACK_C1 = 1 ;
+static const uint8_t P9N2_EX_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C0 = 2 ;
+static const uint8_t P9N2_EX_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C1 = 3 ;
+static const uint8_t P9N2_EX_CME_SCOM_SICR_PM_EXIT_C0 = 4 ;
+static const uint8_t P9N2_EX_CME_SCOM_SICR_PM_EXIT_C1 = 5 ;
+static const uint8_t P9N2_EX_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0 = 6 ;
+static const uint8_t P9N2_EX_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1 = 7 ;
+static const uint8_t P9N2_EX_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0 = 8 ;
+static const uint8_t P9N2_EX_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1 = 9 ;
+static const uint8_t P9N2_EX_CME_SCOM_SICR_PCBMUX_REQ_C0 = 10 ;
+static const uint8_t P9N2_EX_CME_SCOM_SICR_PCBMUX_REQ_C1 = 11 ;
+static const uint8_t P9N2_EX_CME_SCOM_SICR_RESERVED_12_15 = 12 ;
+static const uint8_t P9N2_EX_CME_SCOM_SICR_RESERVED_12_15_LEN = 4 ;
+static const uint8_t P9N2_EX_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C0 = 16 ;
+static const uint8_t P9N2_EX_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C1 = 17 ;
+static const uint8_t P9N2_EX_CME_SCOM_SICR_L2_PURGE = 18 ;
+static const uint8_t P9N2_EX_CME_SCOM_SICR_L2_PURGE_ABORT = 19 ;
+static const uint8_t P9N2_EX_CME_SCOM_SICR_PC_THROTTLE_REQ = 20 ;
+static const uint8_t P9N2_EX_CME_SCOM_SICR_NCU_TLBIE_QUIESCE = 21 ;
+static const uint8_t P9N2_EX_CME_SCOM_SICR_NCU_PURGE = 22 ;
+static const uint8_t P9N2_EX_CME_SCOM_SICR_NCU_PURGE_ABORT = 23 ;
+static const uint8_t P9N2_EX_CME_SCOM_SICR_CHTM_PURGE_C0 = 24 ;
+static const uint8_t P9N2_EX_CME_SCOM_SICR_CHTM_PURGE_C1 = 25 ;
+static const uint8_t P9N2_EX_CME_SCOM_SICR_HMI_REQUEST_C0 = 26 ;
+static const uint8_t P9N2_EX_CME_SCOM_SICR_HMI_REQUEST_C1 = 27 ;
+static const uint8_t P9N2_EX_CME_SCOM_SICR_PPM_SPARE_OUT_C0 = 28 ;
+static const uint8_t P9N2_EX_CME_SCOM_SICR_PPM_SPARE_OUT_C1 = 29 ;
+static const uint8_t P9N2_EX_CME_SCOM_SICR_RESERVED_30_31 = 30 ;
+static const uint8_t P9N2_EX_CME_SCOM_SICR_RESERVED_30_31_LEN = 2 ;
+
+static const uint8_t P9N2_EQ_CME_SCOM_SRTCH0_DATA = 0 ;
+static const uint8_t P9N2_EQ_CME_SCOM_SRTCH0_DATA_LEN = 32 ;
+
+static const uint8_t P9N2_EX_CME_SCOM_SRTCH0_DATA = 0 ;
+static const uint8_t P9N2_EX_CME_SCOM_SRTCH0_DATA_LEN = 32 ;
+
+static const uint8_t P9N2_EQ_CME_SCOM_SRTCH1_DATA = 0 ;
+static const uint8_t P9N2_EQ_CME_SCOM_SRTCH1_DATA_LEN = 32 ;
+
+static const uint8_t P9N2_EX_CME_SCOM_SRTCH1_DATA = 0 ;
+static const uint8_t P9N2_EX_CME_SCOM_SRTCH1_DATA_LEN = 32 ;
+
+static const uint8_t P9N2_EQ_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD = 0 ;
+static const uint8_t P9N2_EQ_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD_LEN = 16 ;
+static const uint8_t P9N2_EQ_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD = 16 ;
+static const uint8_t P9N2_EQ_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD_LEN = 12 ;
+static const uint8_t P9N2_EQ_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD = 28 ;
+static const uint8_t P9N2_EQ_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD_LEN = 8 ;
+static const uint8_t P9N2_EQ_CME_SCOM_VCCR_DROOP_PROFILE_TYPE = 36 ;
+static const uint8_t P9N2_EQ_CME_SCOM_VCCR_DROOP_PROFILE_TYPE_LEN = 2 ;
+static const uint8_t P9N2_EQ_CME_SCOM_VCCR_DROOP_TIMER_MODE = 38 ;
+static const uint8_t P9N2_EQ_CME_SCOM_VCCR_DROOP_CHAR_MODE = 39 ;
+static const uint8_t P9N2_EQ_CME_SCOM_VCCR_DROOP_NOTIFY_ENABLE = 40 ;
+static const uint8_t P9N2_EQ_CME_SCOM_VCCR_SPARE41_43 = 41 ;
+static const uint8_t P9N2_EQ_CME_SCOM_VCCR_SPARE41_43_LEN = 3 ;
+static const uint8_t P9N2_EQ_CME_SCOM_VCCR_DROOP_SAMPLE_RATE = 59 ;
+static const uint8_t P9N2_EQ_CME_SCOM_VCCR_DROOP_SAMPLE_RATE_LEN = 5 ;
+
+static const uint8_t P9N2_EX_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD = 0 ;
+static const uint8_t P9N2_EX_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD_LEN = 16 ;
+static const uint8_t P9N2_EX_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD = 16 ;
+static const uint8_t P9N2_EX_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD_LEN = 12 ;
+static const uint8_t P9N2_EX_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD = 28 ;
+static const uint8_t P9N2_EX_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD_LEN = 8 ;
+static const uint8_t P9N2_EX_CME_SCOM_VCCR_DROOP_PROFILE_TYPE = 36 ;
+static const uint8_t P9N2_EX_CME_SCOM_VCCR_DROOP_PROFILE_TYPE_LEN = 2 ;
+static const uint8_t P9N2_EX_CME_SCOM_VCCR_DROOP_TIMER_MODE = 38 ;
+static const uint8_t P9N2_EX_CME_SCOM_VCCR_DROOP_CHAR_MODE = 39 ;
+static const uint8_t P9N2_EX_CME_SCOM_VCCR_DROOP_NOTIFY_ENABLE = 40 ;
+static const uint8_t P9N2_EX_CME_SCOM_VCCR_SPARE41_43 = 41 ;
+static const uint8_t P9N2_EX_CME_SCOM_VCCR_SPARE41_43_LEN = 3 ;
+static const uint8_t P9N2_EX_CME_SCOM_VCCR_DROOP_SAMPLE_RATE = 59 ;
+static const uint8_t P9N2_EX_CME_SCOM_VCCR_DROOP_SAMPLE_RATE_LEN = 5 ;
+
+static const uint8_t P9N2_EQ_CME_SCOM_VCTR_VDM_EXTREME_DROOP_THRESHOLD = 0 ;
+static const uint8_t P9N2_EQ_CME_SCOM_VCTR_VDM_EXTREME_DROOP_THRESHOLD_LEN = 16 ;
+static const uint8_t P9N2_EQ_CME_SCOM_VCTR_VDM_LARGE_DROOP_THRESHOLD = 16 ;
+static const uint8_t P9N2_EQ_CME_SCOM_VCTR_VDM_LARGE_DROOP_THRESHOLD_LEN = 24 ;
+static const uint8_t P9N2_EQ_CME_SCOM_VCTR_VDM_SMALL_DROOP_THRESHOLD = 40 ;
+static const uint8_t P9N2_EQ_CME_SCOM_VCTR_VDM_SMALL_DROOP_THRESHOLD_LEN = 24 ;
+
+static const uint8_t P9N2_EX_CME_SCOM_VCTR_VDM_EXTREME_DROOP_THRESHOLD = 0 ;
+static const uint8_t P9N2_EX_CME_SCOM_VCTR_VDM_EXTREME_DROOP_THRESHOLD_LEN = 16 ;
+static const uint8_t P9N2_EX_CME_SCOM_VCTR_VDM_LARGE_DROOP_THRESHOLD = 16 ;
+static const uint8_t P9N2_EX_CME_SCOM_VCTR_VDM_LARGE_DROOP_THRESHOLD_LEN = 24 ;
+static const uint8_t P9N2_EX_CME_SCOM_VCTR_VDM_SMALL_DROOP_THRESHOLD = 40 ;
+static const uint8_t P9N2_EX_CME_SCOM_VCTR_VDM_SMALL_DROOP_THRESHOLD_LEN = 24 ;
+
+static const uint8_t P9N2_EQ_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR = 0 ;
+static const uint8_t P9N2_EQ_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR_LEN = 16 ;
+static const uint8_t P9N2_EQ_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR = 16 ;
+static const uint8_t P9N2_EQ_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR_LEN = 24 ;
+static const uint8_t P9N2_EQ_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR = 40 ;
+static const uint8_t P9N2_EQ_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR_LEN = 24 ;
+
+static const uint8_t P9N2_EX_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR = 0 ;
+static const uint8_t P9N2_EX_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR_LEN = 16 ;
+static const uint8_t P9N2_EX_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR = 16 ;
+static const uint8_t P9N2_EX_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR_LEN = 24 ;
+static const uint8_t P9N2_EX_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR = 40 ;
+static const uint8_t P9N2_EX_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR_LEN = 24 ;
+
+static const uint8_t P9N2_EQ_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY = 0 ;
+static const uint8_t P9N2_EQ_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY_LEN = 4 ;
+static const uint8_t P9N2_EQ_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA = 4 ;
+static const uint8_t P9N2_EQ_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_EQ_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA = 8 ;
+static const uint8_t P9N2_EQ_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_EQ_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA = 12 ;
+static const uint8_t P9N2_EQ_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_EQ_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA = 16 ;
+static const uint8_t P9N2_EQ_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_EQ_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA = 20 ;
+static const uint8_t P9N2_EQ_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_EQ_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY = 32 ;
+static const uint8_t P9N2_EQ_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY_LEN = 4 ;
+static const uint8_t P9N2_EQ_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA = 36 ;
+static const uint8_t P9N2_EQ_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_EQ_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA = 40 ;
+static const uint8_t P9N2_EQ_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_EQ_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA = 44 ;
+static const uint8_t P9N2_EQ_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_EQ_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA = 48 ;
+static const uint8_t P9N2_EQ_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_EQ_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA = 52 ;
+static const uint8_t P9N2_EQ_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA_LEN = 4 ;
+
+static const uint8_t P9N2_EX_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY = 0 ;
+static const uint8_t P9N2_EX_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY_LEN = 4 ;
+static const uint8_t P9N2_EX_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA = 4 ;
+static const uint8_t P9N2_EX_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_EX_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA = 8 ;
+static const uint8_t P9N2_EX_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_EX_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA = 12 ;
+static const uint8_t P9N2_EX_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_EX_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA = 16 ;
+static const uint8_t P9N2_EX_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_EX_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA = 20 ;
+static const uint8_t P9N2_EX_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_EX_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY = 32 ;
+static const uint8_t P9N2_EX_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY_LEN = 4 ;
+static const uint8_t P9N2_EX_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA = 36 ;
+static const uint8_t P9N2_EX_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_EX_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA = 40 ;
+static const uint8_t P9N2_EX_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_EX_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA = 44 ;
+static const uint8_t P9N2_EX_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_EX_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA = 48 ;
+static const uint8_t P9N2_EX_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_EX_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA = 52 ;
+static const uint8_t P9N2_EX_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA_LEN = 4 ;
+
+static const uint8_t P9N2_EQ_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR = 0 ;
+static const uint8_t P9N2_EQ_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR_LEN = 16 ;
+static const uint8_t P9N2_EQ_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR = 16 ;
+static const uint8_t P9N2_EQ_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR_LEN = 16 ;
+static const uint8_t P9N2_EQ_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR = 32 ;
+static const uint8_t P9N2_EQ_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR_LEN = 12 ;
+static const uint8_t P9N2_EQ_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR = 44 ;
+static const uint8_t P9N2_EQ_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR_LEN = 12 ;
+static const uint8_t P9N2_EQ_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR = 56 ;
+static const uint8_t P9N2_EQ_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR_LEN = 8 ;
+
+static const uint8_t P9N2_EX_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR = 0 ;
+static const uint8_t P9N2_EX_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR_LEN = 16 ;
+static const uint8_t P9N2_EX_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR = 16 ;
+static const uint8_t P9N2_EX_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR_LEN = 16 ;
+static const uint8_t P9N2_EX_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR = 32 ;
+static const uint8_t P9N2_EX_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR_LEN = 12 ;
+static const uint8_t P9N2_EX_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR = 44 ;
+static const uint8_t P9N2_EX_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR_LEN = 12 ;
+static const uint8_t P9N2_EX_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR = 56 ;
+static const uint8_t P9N2_EX_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR_LEN = 8 ;
+
+static const uint8_t P9N2_EQ_CME_SCOM_VNCR_VDM_NO_DROOP_CTR = 16 ;
+static const uint8_t P9N2_EQ_CME_SCOM_VNCR_VDM_NO_DROOP_CTR_LEN = 24 ;
+static const uint8_t P9N2_EQ_CME_SCOM_VNCR_VDM_OVERVOLT_CTR = 40 ;
+static const uint8_t P9N2_EQ_CME_SCOM_VNCR_VDM_OVERVOLT_CTR_LEN = 24 ;
+
+static const uint8_t P9N2_EX_CME_SCOM_VNCR_VDM_NO_DROOP_CTR = 16 ;
+static const uint8_t P9N2_EX_CME_SCOM_VNCR_VDM_NO_DROOP_CTR_LEN = 24 ;
+static const uint8_t P9N2_EX_CME_SCOM_VNCR_VDM_OVERVOLT_CTR = 40 ;
+static const uint8_t P9N2_EX_CME_SCOM_VNCR_VDM_OVERVOLT_CTR_LEN = 24 ;
+
+static const uint8_t P9N2_EQ_CME_SCOM_XIPCBMD0_PCBM_DATA = 0 ;
+static const uint8_t P9N2_EQ_CME_SCOM_XIPCBMD0_PCBM_DATA_LEN = 27 ;
+
+static const uint8_t P9N2_EX_CME_SCOM_XIPCBMD0_PCBM_DATA = 0 ;
+static const uint8_t P9N2_EX_CME_SCOM_XIPCBMD0_PCBM_DATA_LEN = 27 ;
+
+static const uint8_t P9N2_EQ_CME_SCOM_XIPCBMD1_PCBM_DATA = 0 ;
+static const uint8_t P9N2_EQ_CME_SCOM_XIPCBMD1_PCBM_DATA_LEN = 27 ;
+
+static const uint8_t P9N2_EX_CME_SCOM_XIPCBMD1_PCBM_DATA = 0 ;
+static const uint8_t P9N2_EX_CME_SCOM_XIPCBMD1_PCBM_DATA_LEN = 27 ;
+
+static const uint8_t P9N2_EQ_CME_SCOM_XIPCBMI0_PCBM_INFO = 0 ;
+static const uint8_t P9N2_EQ_CME_SCOM_XIPCBMI0_PCBM_INFO_LEN = 7 ;
+
+static const uint8_t P9N2_EX_CME_SCOM_XIPCBMI0_PCBM_INFO = 0 ;
+static const uint8_t P9N2_EX_CME_SCOM_XIPCBMI0_PCBM_INFO_LEN = 7 ;
+
+static const uint8_t P9N2_EQ_CME_SCOM_XIPCBMI1_PCBM_INFO = 0 ;
+static const uint8_t P9N2_EQ_CME_SCOM_XIPCBMI1_PCBM_INFO_LEN = 7 ;
+
+static const uint8_t P9N2_EX_CME_SCOM_XIPCBMI1_PCBM_INFO = 0 ;
+static const uint8_t P9N2_EX_CME_SCOM_XIPCBMI1_PCBM_INFO_LEN = 7 ;
+
+static const uint8_t P9N2_EQ_CME_SCOM_XIPCBQ0_PCBQ_N_INFO = 0 ;
+static const uint8_t P9N2_EQ_CME_SCOM_XIPCBQ0_PCBQ_N_INFO_LEN = 26 ;
+
+static const uint8_t P9N2_EX_CME_SCOM_XIPCBQ0_PCBQ_N_INFO = 0 ;
+static const uint8_t P9N2_EX_CME_SCOM_XIPCBQ0_PCBQ_N_INFO_LEN = 26 ;
+
+static const uint8_t P9N2_EQ_CME_SCOM_XIPCBQ1_PCBQ_N_INFO = 0 ;
+static const uint8_t P9N2_EQ_CME_SCOM_XIPCBQ1_PCBQ_N_INFO_LEN = 26 ;
+
+static const uint8_t P9N2_EX_CME_SCOM_XIPCBQ1_PCBQ_N_INFO = 0 ;
+static const uint8_t P9N2_EX_CME_SCOM_XIPCBQ1_PCBQ_N_INFO_LEN = 26 ;
+
+static const uint8_t P9N2_EQ_CME_SCOM_XISIB_PIB_ADDR = 0 ;
+static const uint8_t P9N2_EQ_CME_SCOM_XISIB_PIB_ADDR_LEN = 32 ;
+static const uint8_t P9N2_EQ_CME_SCOM_XISIB_PIB_R_NW = 32 ;
+static const uint8_t P9N2_EQ_CME_SCOM_XISIB_PIB_BUSY = 33 ;
+static const uint8_t P9N2_EQ_CME_SCOM_XISIB_PIB_IMPRECISE_ERROR_PENDING = 34 ;
+static const uint8_t P9N2_EQ_CME_SCOM_XISIB_PIB_RSP_INFO = 49 ;
+static const uint8_t P9N2_EQ_CME_SCOM_XISIB_PIB_RSP_INFO_LEN = 3 ;
+static const uint8_t P9N2_EQ_CME_SCOM_XISIB_PIB_IFETCH_PENDING = 62 ;
+static const uint8_t P9N2_EQ_CME_SCOM_XISIB_PIB_DATAOP_PENDING = 63 ;
+
+static const uint8_t P9N2_EX_CME_SCOM_XISIB_PIB_ADDR = 0 ;
+static const uint8_t P9N2_EX_CME_SCOM_XISIB_PIB_ADDR_LEN = 32 ;
+static const uint8_t P9N2_EX_CME_SCOM_XISIB_PIB_R_NW = 32 ;
+static const uint8_t P9N2_EX_CME_SCOM_XISIB_PIB_BUSY = 33 ;
+static const uint8_t P9N2_EX_CME_SCOM_XISIB_PIB_IMPRECISE_ERROR_PENDING = 34 ;
+static const uint8_t P9N2_EX_CME_SCOM_XISIB_PIB_RSP_INFO = 49 ;
+static const uint8_t P9N2_EX_CME_SCOM_XISIB_PIB_RSP_INFO_LEN = 3 ;
+static const uint8_t P9N2_EX_CME_SCOM_XISIB_PIB_IFETCH_PENDING = 62 ;
+static const uint8_t P9N2_EX_CME_SCOM_XISIB_PIB_DATAOP_PENDING = 63 ;
+
+static const uint8_t P9N2_EQ_CONTROL_REG_RESET_TRIP_HISTORY = 0 ;
+static const uint8_t P9N2_EQ_CONTROL_REG_RESET_SAMPLE_PULSE_CNT = 1 ;
+static const uint8_t P9N2_EQ_CONTROL_REG_F_RESET_CPM_RD = 2 ;
+static const uint8_t P9N2_EQ_CONTROL_REG_F_RESET_CPM_WR = 3 ;
+static const uint8_t P9N2_EQ_CONTROL_REG_RESET_SAMPLE_DTS = 4 ;
+static const uint8_t P9N2_EQ_CONTROL_REG_FORCE_SAMPLE_DTS = 5 ;
+static const uint8_t P9N2_EQ_CONTROL_REG_FORCE_SAMPLE_DTS_INTERRUPTIBLE = 6 ;
+static const uint8_t P9N2_EQ_CONTROL_REG_FORCE_RESET_THRES_L1RESULTS = 7 ;
+static const uint8_t P9N2_EQ_CONTROL_REG_FORCE_RESET_THRES_L2RESULTS = 8 ;
+static const uint8_t P9N2_EQ_CONTROL_REG_FORCE_RESET_THRES_L3RESULTS = 9 ;
+static const uint8_t P9N2_EQ_CONTROL_REG_FORCE_MEASURE_VOLT_INTERRUPTIBLE = 10 ;
+static const uint8_t P9N2_EQ_CONTROL_REG_FORCE_RESET_MEASURE_VOLT = 11 ;
+static const uint8_t P9N2_EQ_CONTROL_REG_FORCE_SHIFT_SENSOR = 12 ;
+
+static const uint8_t P9N2_EX_CONTROL_REG_RESET_TRIP_HISTORY = 0 ;
+static const uint8_t P9N2_EX_CONTROL_REG_RESET_SAMPLE_PULSE_CNT = 1 ;
+static const uint8_t P9N2_EX_CONTROL_REG_F_RESET_CPM_RD = 2 ;
+static const uint8_t P9N2_EX_CONTROL_REG_F_RESET_CPM_WR = 3 ;
+static const uint8_t P9N2_EX_CONTROL_REG_RESET_SAMPLE_DTS = 4 ;
+static const uint8_t P9N2_EX_CONTROL_REG_FORCE_SAMPLE_DTS = 5 ;
+static const uint8_t P9N2_EX_CONTROL_REG_FORCE_SAMPLE_DTS_INTERRUPTIBLE = 6 ;
+static const uint8_t P9N2_EX_CONTROL_REG_FORCE_RESET_THRES_L1RESULTS = 7 ;
+static const uint8_t P9N2_EX_CONTROL_REG_FORCE_RESET_THRES_L2RESULTS = 8 ;
+static const uint8_t P9N2_EX_CONTROL_REG_FORCE_RESET_THRES_L3RESULTS = 9 ;
+static const uint8_t P9N2_EX_CONTROL_REG_FORCE_MEASURE_VOLT_INTERRUPTIBLE = 10 ;
+static const uint8_t P9N2_EX_CONTROL_REG_FORCE_RESET_MEASURE_VOLT = 11 ;
+static const uint8_t P9N2_EX_CONTROL_REG_FORCE_SHIFT_SENSOR = 12 ;
+
+static const uint8_t P9N2_C_CONTROL_REG_RESET_TRIP_HISTORY = 0 ;
+static const uint8_t P9N2_C_CONTROL_REG_RESET_SAMPLE_PULSE_CNT = 1 ;
+static const uint8_t P9N2_C_CONTROL_REG_F_RESET_CPM_RD = 2 ;
+static const uint8_t P9N2_C_CONTROL_REG_F_RESET_CPM_WR = 3 ;
+static const uint8_t P9N2_C_CONTROL_REG_RESET_SAMPLE_DTS = 4 ;
+static const uint8_t P9N2_C_CONTROL_REG_FORCE_SAMPLE_DTS = 5 ;
+static const uint8_t P9N2_C_CONTROL_REG_FORCE_SAMPLE_DTS_INTERRUPTIBLE = 6 ;
+static const uint8_t P9N2_C_CONTROL_REG_FORCE_RESET_THRES_L1RESULTS = 7 ;
+static const uint8_t P9N2_C_CONTROL_REG_FORCE_RESET_THRES_L2RESULTS = 8 ;
+static const uint8_t P9N2_C_CONTROL_REG_FORCE_RESET_THRES_L3RESULTS = 9 ;
+static const uint8_t P9N2_C_CONTROL_REG_FORCE_MEASURE_VOLT_INTERRUPTIBLE = 10 ;
+static const uint8_t P9N2_C_CONTROL_REG_FORCE_RESET_MEASURE_VOLT = 11 ;
+static const uint8_t P9N2_C_CONTROL_REG_FORCE_SHIFT_SENSOR = 12 ;
+
+static const uint8_t P9N2_EX_L2_CORE_ACTION0_ACTION_IF_SRAM_REC_ERROR = 0 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION0_ACTION_TC_FIR_XSTOP_ERROR = 1 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION0_ACTION_IF_RFILE_REC_ERROR = 2 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION0_ACTION_IF_RFILE_XSTOP_ERROR = 3 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION0_ACTION_IF_LOG_REC_ERROR = 4 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION0_ACTION_IF_LOG_XSTOP_ERROR = 5 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION0_ACTION_UNUSED_6 = 6 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION0_ACTION_UNUSED_7 = 7 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION0_ACTION_PC_RECOV_XSTOP_ERROR = 8 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION0_ACTION_SD_RFILE_REC_ERROR = 9 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION0_ACTION_SD_RFILE_XSTOP_ERROR = 10 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION0_ACTION_SD_LOG_REC_ERROR = 11 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION0_ACTION_SD_LOG_XSTOP_ERROR = 12 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION0_ACTION_SD_NOT_MT_CI_REC_ERROR = 13 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION0_ACTION_SD_MCHK_AND_ME_EQ_0_ERROR = 14 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION0_ACTION_SD_L2_UE_ERROR = 15 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION0_ACTION_SD_L2_UE_OVER_THRES_ERROR = 16 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION0_ACTION_SD_CI_UE_ERROR = 17 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION0_ACTION_UNUSED_18 = 18 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION0_ACTION_UNUSED_19 = 19 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION0_ACTION_SD_SYS_XSTOP_ERROR = 20 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION0_ACTION_UNUSED_21 = 21 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION0_ACTION_UNUSED_22 = 22 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION0_ACTION_UNUSED_23 = 23 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION0_ACTION_VS_LOG_REC_ERROR = 24 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION0_ACTION_VS_LOG_XSTOP_ERROR = 25 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION0_ACTION_PC_RECOV_IN_MAINT_ERROR = 26 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION0_ACTION_VS_DU_LOG_REC_ERROR = 27 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION0_ACTION_PC_SYS_XSTOP_ERROR = 28 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION0_ACTION_LS_SRAM_PARITY_ERROR = 29 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION0_ACTION_LS_SETDELETE_ERROR = 30 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION0_ACTION_LS_RFILE_REC_ERROR = 31 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION0_ACTION_LS_RFILE_XSTOP_ERROR = 32 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION0_ACTION_LS_TLB_MULTIHIT_ERROR = 33 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION0_ACTION_LS_SLB_MULTIHIT_ERROR = 34 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION0_ACTION_LS_DERAT_MULTIHIT_ERROR = 35 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION0_ACTION_PC_FWD_PROGRESS_ERROR = 36 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION0_ACTION_LS_LOG_REC_ERROR = 37 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION0_ACTION_LS_LOG_XSTOP_ERROR = 38 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION0_ACTION_UNUSED_39 = 39 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION0_ACTION_UNUSED_40 = 40 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION0_ACTION_LS_SYS_XSTOP_ERROR = 41 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION0_ACTION_UNUSED_42 = 42 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION0_ACTION_PC_THREAD_HANG_REC_ERROR = 43 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION0_ACTION_UNUSED_44 = 44 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION0_ACTION_PC_LOG_XSTOP_ERROR = 45 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION0_ACTION_UNUSED_46 = 46 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION0_ACTION_PC_TFAC_XSTOP_ERROR = 47 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION0_ACTION_PC_HYP_RES_ERROR = 48 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION0_ACTION_UNUSED_49 = 49 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION0_ACTION_UNUSED_50 = 50 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION0_ACTION_UNUSED_51 = 51 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION0_ACTION_PC_HANG_RECOVERY_FAILED = 52 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION0_ACTION_PC_HANG_DETECT_ERROR = 53 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION0_ACTION_UNUSED_54 = 54 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION0_ACTION_PC_NEST_HANG_DETECT_ERROR = 55 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION0_ACTION_PC_OTHER_CHIPLET_REC_ERROR = 56 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION0_ACTION_PC_OTHER_CHIPLET_XSTOP_ERROR = 57 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION0_ACTION_PC_OTHER_CHIPLET_SYS_XSTOP_ERROR = 58 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION0_ACTION_PC_SCOM_ERROR = 59 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION0_ACTION_PC_XSTOP_ON_DBG_TRIGGER_ERROR = 60 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION0_ACTION_PC_FW_INJ_REC_ERROR = 61 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION0_ACTION_PC_FW_INJ_XSTOP_ERROR = 62 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION0_ACTION_PC_PHYP_XSTOP_ERROR = 63 ;
+
+static const uint8_t P9N2_C_CORE_ACTION0_ACTION_IF_SRAM_REC_ERROR = 0 ;
+static const uint8_t P9N2_C_CORE_ACTION0_ACTION_TC_FIR_XSTOP_ERROR = 1 ;
+static const uint8_t P9N2_C_CORE_ACTION0_ACTION_IF_RFILE_REC_ERROR = 2 ;
+static const uint8_t P9N2_C_CORE_ACTION0_ACTION_IF_RFILE_XSTOP_ERROR = 3 ;
+static const uint8_t P9N2_C_CORE_ACTION0_ACTION_IF_LOG_REC_ERROR = 4 ;
+static const uint8_t P9N2_C_CORE_ACTION0_ACTION_IF_LOG_XSTOP_ERROR = 5 ;
+static const uint8_t P9N2_C_CORE_ACTION0_ACTION_UNUSED_6 = 6 ;
+static const uint8_t P9N2_C_CORE_ACTION0_ACTION_UNUSED_7 = 7 ;
+static const uint8_t P9N2_C_CORE_ACTION0_ACTION_PC_RECOV_XSTOP_ERROR = 8 ;
+static const uint8_t P9N2_C_CORE_ACTION0_ACTION_SD_RFILE_REC_ERROR = 9 ;
+static const uint8_t P9N2_C_CORE_ACTION0_ACTION_SD_RFILE_XSTOP_ERROR = 10 ;
+static const uint8_t P9N2_C_CORE_ACTION0_ACTION_SD_LOG_REC_ERROR = 11 ;
+static const uint8_t P9N2_C_CORE_ACTION0_ACTION_SD_LOG_XSTOP_ERROR = 12 ;
+static const uint8_t P9N2_C_CORE_ACTION0_ACTION_SD_NOT_MT_CI_REC_ERROR = 13 ;
+static const uint8_t P9N2_C_CORE_ACTION0_ACTION_SD_MCHK_AND_ME_EQ_0_ERROR = 14 ;
+static const uint8_t P9N2_C_CORE_ACTION0_ACTION_SD_L2_UE_ERROR = 15 ;
+static const uint8_t P9N2_C_CORE_ACTION0_ACTION_SD_L2_UE_OVER_THRES_ERROR = 16 ;
+static const uint8_t P9N2_C_CORE_ACTION0_ACTION_SD_CI_UE_ERROR = 17 ;
+static const uint8_t P9N2_C_CORE_ACTION0_ACTION_UNUSED_18 = 18 ;
+static const uint8_t P9N2_C_CORE_ACTION0_ACTION_UNUSED_19 = 19 ;
+static const uint8_t P9N2_C_CORE_ACTION0_ACTION_SD_SYS_XSTOP_ERROR = 20 ;
+static const uint8_t P9N2_C_CORE_ACTION0_ACTION_UNUSED_21 = 21 ;
+static const uint8_t P9N2_C_CORE_ACTION0_ACTION_UNUSED_22 = 22 ;
+static const uint8_t P9N2_C_CORE_ACTION0_ACTION_UNUSED_23 = 23 ;
+static const uint8_t P9N2_C_CORE_ACTION0_ACTION_VS_LOG_REC_ERROR = 24 ;
+static const uint8_t P9N2_C_CORE_ACTION0_ACTION_VS_LOG_XSTOP_ERROR = 25 ;
+static const uint8_t P9N2_C_CORE_ACTION0_ACTION_PC_RECOV_IN_MAINT_ERROR = 26 ;
+static const uint8_t P9N2_C_CORE_ACTION0_ACTION_VS_DU_LOG_REC_ERROR = 27 ;
+static const uint8_t P9N2_C_CORE_ACTION0_ACTION_PC_SYS_XSTOP_ERROR = 28 ;
+static const uint8_t P9N2_C_CORE_ACTION0_ACTION_LS_SRAM_PARITY_ERROR = 29 ;
+static const uint8_t P9N2_C_CORE_ACTION0_ACTION_LS_SETDELETE_ERROR = 30 ;
+static const uint8_t P9N2_C_CORE_ACTION0_ACTION_LS_RFILE_REC_ERROR = 31 ;
+static const uint8_t P9N2_C_CORE_ACTION0_ACTION_LS_RFILE_XSTOP_ERROR = 32 ;
+static const uint8_t P9N2_C_CORE_ACTION0_ACTION_LS_TLB_MULTIHIT_ERROR = 33 ;
+static const uint8_t P9N2_C_CORE_ACTION0_ACTION_LS_SLB_MULTIHIT_ERROR = 34 ;
+static const uint8_t P9N2_C_CORE_ACTION0_ACTION_LS_DERAT_MULTIHIT_ERROR = 35 ;
+static const uint8_t P9N2_C_CORE_ACTION0_ACTION_PC_FWD_PROGRESS_ERROR = 36 ;
+static const uint8_t P9N2_C_CORE_ACTION0_ACTION_LS_LOG_REC_ERROR = 37 ;
+static const uint8_t P9N2_C_CORE_ACTION0_ACTION_LS_LOG_XSTOP_ERROR = 38 ;
+static const uint8_t P9N2_C_CORE_ACTION0_ACTION_UNUSED_39 = 39 ;
+static const uint8_t P9N2_C_CORE_ACTION0_ACTION_UNUSED_40 = 40 ;
+static const uint8_t P9N2_C_CORE_ACTION0_ACTION_LS_SYS_XSTOP_ERROR = 41 ;
+static const uint8_t P9N2_C_CORE_ACTION0_ACTION_UNUSED_42 = 42 ;
+static const uint8_t P9N2_C_CORE_ACTION0_ACTION_PC_THREAD_HANG_REC_ERROR = 43 ;
+static const uint8_t P9N2_C_CORE_ACTION0_ACTION_UNUSED_44 = 44 ;
+static const uint8_t P9N2_C_CORE_ACTION0_ACTION_PC_LOG_XSTOP_ERROR = 45 ;
+static const uint8_t P9N2_C_CORE_ACTION0_ACTION_UNUSED_46 = 46 ;
+static const uint8_t P9N2_C_CORE_ACTION0_ACTION_PC_TFAC_XSTOP_ERROR = 47 ;
+static const uint8_t P9N2_C_CORE_ACTION0_ACTION_PC_HYP_RES_ERROR = 48 ;
+static const uint8_t P9N2_C_CORE_ACTION0_ACTION_UNUSED_49 = 49 ;
+static const uint8_t P9N2_C_CORE_ACTION0_ACTION_UNUSED_50 = 50 ;
+static const uint8_t P9N2_C_CORE_ACTION0_ACTION_UNUSED_51 = 51 ;
+static const uint8_t P9N2_C_CORE_ACTION0_ACTION_PC_HANG_RECOVERY_FAILED = 52 ;
+static const uint8_t P9N2_C_CORE_ACTION0_ACTION_PC_HANG_DETECT_ERROR = 53 ;
+static const uint8_t P9N2_C_CORE_ACTION0_ACTION_UNUSED_54 = 54 ;
+static const uint8_t P9N2_C_CORE_ACTION0_ACTION_PC_NEST_HANG_DETECT_ERROR = 55 ;
+static const uint8_t P9N2_C_CORE_ACTION0_ACTION_PC_OTHER_CHIPLET_REC_ERROR = 56 ;
+static const uint8_t P9N2_C_CORE_ACTION0_ACTION_PC_OTHER_CHIPLET_XSTOP_ERROR = 57 ;
+static const uint8_t P9N2_C_CORE_ACTION0_ACTION_PC_OTHER_CHIPLET_SYS_XSTOP_ERROR = 58 ;
+static const uint8_t P9N2_C_CORE_ACTION0_ACTION_PC_SCOM_ERROR = 59 ;
+static const uint8_t P9N2_C_CORE_ACTION0_ACTION_PC_XSTOP_ON_DBG_TRIGGER_ERROR = 60 ;
+static const uint8_t P9N2_C_CORE_ACTION0_ACTION_PC_FW_INJ_REC_ERROR = 61 ;
+static const uint8_t P9N2_C_CORE_ACTION0_ACTION_PC_FW_INJ_XSTOP_ERROR = 62 ;
+static const uint8_t P9N2_C_CORE_ACTION0_ACTION_PC_PHYP_XSTOP_ERROR = 63 ;
+
+static const uint8_t P9N2_EX_L2_CORE_ACTION1_ACTION_IF_SRAM_REC_ERROR = 0 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION1_ACTION_TC_FIR_XSTOP_ERROR = 1 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION1_ACTION_IF_RFILE_REC_ERROR = 2 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION1_ACTION_IF_RFILE_XSTOP_ERROR = 3 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION1_ACTION_IF_LOG_REC_ERROR = 4 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION1_ACTION_IF_LOG_XSTOP_ERROR = 5 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION1_ACTION_UNUSED_6 = 6 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION1_ACTION_UNUSED_7 = 7 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION1_ACTION_PC_RECOV_XSTOP_ERROR = 8 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION1_ACTION_SD_RFILE_REC_ERROR = 9 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION1_ACTION_SD_RFILE_XSTOP_ERROR = 10 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION1_ACTION_SD_LOG_REC_ERROR = 11 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION1_ACTION_SD_LOG_XSTOP_ERROR = 12 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION1_ACTION_SD_NOT_MT_CI_REC_ERROR = 13 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION1_ACTION_SD_MCHK_AND_ME_EQ_0_ERROR = 14 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION1_ACTION_SD_L2_UE_ERROR = 15 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION1_ACTION_SD_L2_UE_OVER_THRES_ERROR = 16 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION1_ACTION_SD_CI_UE_ERROR = 17 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION1_ACTION_UNUSED_18 = 18 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION1_ACTION_UNUSED_19 = 19 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION1_ACTION_SD_SYS_XSTOP_ERROR = 20 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION1_ACTION_UNUSED_21 = 21 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION1_ACTION_UNUSED_22 = 22 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION1_ACTION_UNUSED_23 = 23 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION1_ACTION_VS_LOG_REC_ERROR = 24 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION1_ACTION_VS_LOG_XSTOP_ERROR = 25 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION1_ACTION_PC_RECOV_IN_MAINT_ERROR = 26 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION1_ACTION_VS_DU_LOG_REC_ERROR = 27 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION1_ACTION_PC_SYS_XSTOP_ERROR = 28 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION1_ACTION_LS_SRAM_PARITY_ERROR = 29 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION1_ACTION_LS_SETDELETE_ERROR = 30 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION1_ACTION_LS_RFILE_REC_ERROR = 31 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION1_ACTION_LS_RFILE_XSTOP_ERROR = 32 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION1_ACTION_LS_TLB_MULTIHIT_ERROR = 33 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION1_ACTION_LS_SLB_MULTIHIT_ERROR = 34 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION1_ACTION_LS_DERAT_MULTIHIT_ERROR = 35 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION1_ACTION_PC_FWD_PROGRESS_ERROR = 36 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION1_ACTION_LS_LOG_REC_ERROR = 37 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION1_ACTION_LS_LOG_XSTOP_ERROR = 38 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION1_ACTION_UNUSED_39 = 39 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION1_ACTION_UNUSED_40 = 40 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION1_ACTION_LS_SYS_XSTOP_ERROR = 41 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION1_ACTION_UNUSED_42 = 42 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION1_ACTION_PC_THREAD_HANG_REC_ERROR = 43 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION1_ACTION_UNUSED_44 = 44 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION1_ACTION_PC_LOG_XSTOP_ERROR = 45 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION1_ACTION_UNUSED_46 = 46 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION1_ACTION_PC_TFAC_XSTOP_ERROR = 47 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION1_ACTION_PC_HYP_RES_ERROR = 48 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION1_ACTION_UNUSED_49 = 49 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION1_ACTION_UNUSED_50 = 50 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION1_ACTION_UNUSED_51 = 51 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION1_ACTION_PC_HANG_RECOVERY_FAILED = 52 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION1_ACTION_PC_HANG_DETECT_ERROR = 53 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION1_ACTION_UNUSED_54 = 54 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION1_ACTION_PC_NEST_HANG_DETECT_ERROR = 55 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION1_ACTION_PC_OTHER_CHIPLET_REC_ERROR = 56 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION1_ACTION_PC_OTHER_CHIPLET_XSTOP_ERROR = 57 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION1_ACTION_PC_OTHER_CHIPLET_SYS_XSTOP_ERROR = 58 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION1_ACTION_PC_SCOM_ERROR = 59 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION1_ACTION_PC_XSTOP_ON_DBG_TRIGGER_ERROR = 60 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION1_ACTION_PC_FW_INJ_REC_ERROR = 61 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION1_ACTION_PC_FW_INJ_XSTOP_ERROR = 62 ;
+static const uint8_t P9N2_EX_L2_CORE_ACTION1_ACTION_PC_PHYP_XSTOP_ERROR = 63 ;
+
+static const uint8_t P9N2_C_CORE_ACTION1_ACTION_IF_SRAM_REC_ERROR = 0 ;
+static const uint8_t P9N2_C_CORE_ACTION1_ACTION_TC_FIR_XSTOP_ERROR = 1 ;
+static const uint8_t P9N2_C_CORE_ACTION1_ACTION_IF_RFILE_REC_ERROR = 2 ;
+static const uint8_t P9N2_C_CORE_ACTION1_ACTION_IF_RFILE_XSTOP_ERROR = 3 ;
+static const uint8_t P9N2_C_CORE_ACTION1_ACTION_IF_LOG_REC_ERROR = 4 ;
+static const uint8_t P9N2_C_CORE_ACTION1_ACTION_IF_LOG_XSTOP_ERROR = 5 ;
+static const uint8_t P9N2_C_CORE_ACTION1_ACTION_UNUSED_6 = 6 ;
+static const uint8_t P9N2_C_CORE_ACTION1_ACTION_UNUSED_7 = 7 ;
+static const uint8_t P9N2_C_CORE_ACTION1_ACTION_PC_RECOV_XSTOP_ERROR = 8 ;
+static const uint8_t P9N2_C_CORE_ACTION1_ACTION_SD_RFILE_REC_ERROR = 9 ;
+static const uint8_t P9N2_C_CORE_ACTION1_ACTION_SD_RFILE_XSTOP_ERROR = 10 ;
+static const uint8_t P9N2_C_CORE_ACTION1_ACTION_SD_LOG_REC_ERROR = 11 ;
+static const uint8_t P9N2_C_CORE_ACTION1_ACTION_SD_LOG_XSTOP_ERROR = 12 ;
+static const uint8_t P9N2_C_CORE_ACTION1_ACTION_SD_NOT_MT_CI_REC_ERROR = 13 ;
+static const uint8_t P9N2_C_CORE_ACTION1_ACTION_SD_MCHK_AND_ME_EQ_0_ERROR = 14 ;
+static const uint8_t P9N2_C_CORE_ACTION1_ACTION_SD_L2_UE_ERROR = 15 ;
+static const uint8_t P9N2_C_CORE_ACTION1_ACTION_SD_L2_UE_OVER_THRES_ERROR = 16 ;
+static const uint8_t P9N2_C_CORE_ACTION1_ACTION_SD_CI_UE_ERROR = 17 ;
+static const uint8_t P9N2_C_CORE_ACTION1_ACTION_UNUSED_18 = 18 ;
+static const uint8_t P9N2_C_CORE_ACTION1_ACTION_UNUSED_19 = 19 ;
+static const uint8_t P9N2_C_CORE_ACTION1_ACTION_SD_SYS_XSTOP_ERROR = 20 ;
+static const uint8_t P9N2_C_CORE_ACTION1_ACTION_UNUSED_21 = 21 ;
+static const uint8_t P9N2_C_CORE_ACTION1_ACTION_UNUSED_22 = 22 ;
+static const uint8_t P9N2_C_CORE_ACTION1_ACTION_UNUSED_23 = 23 ;
+static const uint8_t P9N2_C_CORE_ACTION1_ACTION_VS_LOG_REC_ERROR = 24 ;
+static const uint8_t P9N2_C_CORE_ACTION1_ACTION_VS_LOG_XSTOP_ERROR = 25 ;
+static const uint8_t P9N2_C_CORE_ACTION1_ACTION_PC_RECOV_IN_MAINT_ERROR = 26 ;
+static const uint8_t P9N2_C_CORE_ACTION1_ACTION_VS_DU_LOG_REC_ERROR = 27 ;
+static const uint8_t P9N2_C_CORE_ACTION1_ACTION_PC_SYS_XSTOP_ERROR = 28 ;
+static const uint8_t P9N2_C_CORE_ACTION1_ACTION_LS_SRAM_PARITY_ERROR = 29 ;
+static const uint8_t P9N2_C_CORE_ACTION1_ACTION_LS_SETDELETE_ERROR = 30 ;
+static const uint8_t P9N2_C_CORE_ACTION1_ACTION_LS_RFILE_REC_ERROR = 31 ;
+static const uint8_t P9N2_C_CORE_ACTION1_ACTION_LS_RFILE_XSTOP_ERROR = 32 ;
+static const uint8_t P9N2_C_CORE_ACTION1_ACTION_LS_TLB_MULTIHIT_ERROR = 33 ;
+static const uint8_t P9N2_C_CORE_ACTION1_ACTION_LS_SLB_MULTIHIT_ERROR = 34 ;
+static const uint8_t P9N2_C_CORE_ACTION1_ACTION_LS_DERAT_MULTIHIT_ERROR = 35 ;
+static const uint8_t P9N2_C_CORE_ACTION1_ACTION_PC_FWD_PROGRESS_ERROR = 36 ;
+static const uint8_t P9N2_C_CORE_ACTION1_ACTION_LS_LOG_REC_ERROR = 37 ;
+static const uint8_t P9N2_C_CORE_ACTION1_ACTION_LS_LOG_XSTOP_ERROR = 38 ;
+static const uint8_t P9N2_C_CORE_ACTION1_ACTION_UNUSED_39 = 39 ;
+static const uint8_t P9N2_C_CORE_ACTION1_ACTION_UNUSED_40 = 40 ;
+static const uint8_t P9N2_C_CORE_ACTION1_ACTION_LS_SYS_XSTOP_ERROR = 41 ;
+static const uint8_t P9N2_C_CORE_ACTION1_ACTION_UNUSED_42 = 42 ;
+static const uint8_t P9N2_C_CORE_ACTION1_ACTION_PC_THREAD_HANG_REC_ERROR = 43 ;
+static const uint8_t P9N2_C_CORE_ACTION1_ACTION_UNUSED_44 = 44 ;
+static const uint8_t P9N2_C_CORE_ACTION1_ACTION_PC_LOG_XSTOP_ERROR = 45 ;
+static const uint8_t P9N2_C_CORE_ACTION1_ACTION_UNUSED_46 = 46 ;
+static const uint8_t P9N2_C_CORE_ACTION1_ACTION_PC_TFAC_XSTOP_ERROR = 47 ;
+static const uint8_t P9N2_C_CORE_ACTION1_ACTION_PC_HYP_RES_ERROR = 48 ;
+static const uint8_t P9N2_C_CORE_ACTION1_ACTION_UNUSED_49 = 49 ;
+static const uint8_t P9N2_C_CORE_ACTION1_ACTION_UNUSED_50 = 50 ;
+static const uint8_t P9N2_C_CORE_ACTION1_ACTION_UNUSED_51 = 51 ;
+static const uint8_t P9N2_C_CORE_ACTION1_ACTION_PC_HANG_RECOVERY_FAILED = 52 ;
+static const uint8_t P9N2_C_CORE_ACTION1_ACTION_PC_HANG_DETECT_ERROR = 53 ;
+static const uint8_t P9N2_C_CORE_ACTION1_ACTION_UNUSED_54 = 54 ;
+static const uint8_t P9N2_C_CORE_ACTION1_ACTION_PC_NEST_HANG_DETECT_ERROR = 55 ;
+static const uint8_t P9N2_C_CORE_ACTION1_ACTION_PC_OTHER_CHIPLET_REC_ERROR = 56 ;
+static const uint8_t P9N2_C_CORE_ACTION1_ACTION_PC_OTHER_CHIPLET_XSTOP_ERROR = 57 ;
+static const uint8_t P9N2_C_CORE_ACTION1_ACTION_PC_OTHER_CHIPLET_SYS_XSTOP_ERROR = 58 ;
+static const uint8_t P9N2_C_CORE_ACTION1_ACTION_PC_SCOM_ERROR = 59 ;
+static const uint8_t P9N2_C_CORE_ACTION1_ACTION_PC_XSTOP_ON_DBG_TRIGGER_ERROR = 60 ;
+static const uint8_t P9N2_C_CORE_ACTION1_ACTION_PC_FW_INJ_REC_ERROR = 61 ;
+static const uint8_t P9N2_C_CORE_ACTION1_ACTION_PC_FW_INJ_XSTOP_ERROR = 62 ;
+static const uint8_t P9N2_C_CORE_ACTION1_ACTION_PC_PHYP_XSTOP_ERROR = 63 ;
+
+static const uint8_t P9N2_EX_L2_CORE_FIR_IF_SRAM_REC_ERROR = 0 ;
+static const uint8_t P9N2_EX_L2_CORE_FIR_TC_XSTOP_ERROR = 1 ;
+static const uint8_t P9N2_EX_L2_CORE_FIR_IF_RFILE_REC_ERROR = 2 ;
+static const uint8_t P9N2_EX_L2_CORE_FIR_IF_RFILE_XSTOP_ERROR = 3 ;
+static const uint8_t P9N2_EX_L2_CORE_FIR_IF_LOG_REC_ERROR = 4 ;
+static const uint8_t P9N2_EX_L2_CORE_FIR_IF_LOG_XSTOP_ERROR = 5 ;
+static const uint8_t P9N2_EX_L2_CORE_FIR_UNUSED_6 = 6 ;
+static const uint8_t P9N2_EX_L2_CORE_FIR_UNUSED_7 = 7 ;
+static const uint8_t P9N2_EX_L2_CORE_FIR_PC_RECOV_XSTOP_ERROR = 8 ;
+static const uint8_t P9N2_EX_L2_CORE_FIR_SD_RFILE_REC_ERROR = 9 ;
+static const uint8_t P9N2_EX_L2_CORE_FIR_SD_RFILE_XSTOP_ERROR = 10 ;
+static const uint8_t P9N2_EX_L2_CORE_FIR_SD_LOG_REC_ERROR = 11 ;
+static const uint8_t P9N2_EX_L2_CORE_FIR_SD_LOG_XSTOP_ERROR = 12 ;
+static const uint8_t P9N2_EX_L2_CORE_FIR_SD_NOT_MT_CI_REC_ERROR = 13 ;
+static const uint8_t P9N2_EX_L2_CORE_FIR_SD_MCHK_AND_ME_EQ_0_ERROR = 14 ;
+static const uint8_t P9N2_EX_L2_CORE_FIR_SD_L2_UE_ERROR = 15 ;
+static const uint8_t P9N2_EX_L2_CORE_FIR_SD_L2_UE_OVER_THRES_ERROR = 16 ;
+static const uint8_t P9N2_EX_L2_CORE_FIR_SD_CI_UE_ERROR = 17 ;
+static const uint8_t P9N2_EX_L2_CORE_FIR_UNUSED_18 = 18 ;
+static const uint8_t P9N2_EX_L2_CORE_FIR_UNUSED_19 = 19 ;
+static const uint8_t P9N2_EX_L2_CORE_FIR_SD_SYS_XSTOP_ERROR = 20 ;
+static const uint8_t P9N2_EX_L2_CORE_FIR_UNUSED_21 = 21 ;
+static const uint8_t P9N2_EX_L2_CORE_FIR_UNUSED_22 = 22 ;
+static const uint8_t P9N2_EX_L2_CORE_FIR_UNUSED_23 = 23 ;
+static const uint8_t P9N2_EX_L2_CORE_FIR_VS_LOG_REC_ERROR = 24 ;
+static const uint8_t P9N2_EX_L2_CORE_FIR_VS_LOG_XSTOP_ERROR = 25 ;
+static const uint8_t P9N2_EX_L2_CORE_FIR_PC_RECOV_IN_MAINT_ERROR = 26 ;
+static const uint8_t P9N2_EX_L2_CORE_FIR_VS_DU_LOG_REC_ERROR = 27 ;
+static const uint8_t P9N2_EX_L2_CORE_FIR_PC_SYS_XSTOP_ERROR = 28 ;
+static const uint8_t P9N2_EX_L2_CORE_FIR_LS_SRAM_PARITY_ERROR = 29 ;
+static const uint8_t P9N2_EX_L2_CORE_FIR_LS_SETDELETE_ERROR = 30 ;
+static const uint8_t P9N2_EX_L2_CORE_FIR_LS_RFILE_REC_ERROR = 31 ;
+static const uint8_t P9N2_EX_L2_CORE_FIR_LS_RFILE_XSTOP_ERROR = 32 ;
+static const uint8_t P9N2_EX_L2_CORE_FIR_LS_TLB_MULTIHIT_ERROR = 33 ;
+static const uint8_t P9N2_EX_L2_CORE_FIR_LS_SLB_MULTIHIT_ERROR = 34 ;
+static const uint8_t P9N2_EX_L2_CORE_FIR_LS_DERAT_MULTIHIT_ERROR = 35 ;
+static const uint8_t P9N2_EX_L2_CORE_FIR_PC_FWD_PROGRESS_ERROR = 36 ;
+static const uint8_t P9N2_EX_L2_CORE_FIR_LS_LOG_REC_ERROR = 37 ;
+static const uint8_t P9N2_EX_L2_CORE_FIR_LS_LOG_XSTOP_ERROR = 38 ;
+static const uint8_t P9N2_EX_L2_CORE_FIR_UNUSED_39 = 39 ;
+static const uint8_t P9N2_EX_L2_CORE_FIR_UNUSED_40 = 40 ;
+static const uint8_t P9N2_EX_L2_CORE_FIR_LS_SYS_XSTOP_ERROR = 41 ;
+static const uint8_t P9N2_EX_L2_CORE_FIR_UNUSED_42 = 42 ;
+static const uint8_t P9N2_EX_L2_CORE_FIR_PC_THREAD_HANG_REC_ERROR = 43 ;
+static const uint8_t P9N2_EX_L2_CORE_FIR_UNUSED_44 = 44 ;
+static const uint8_t P9N2_EX_L2_CORE_FIR_PC_LOG_XSTOP_ERROR = 45 ;
+static const uint8_t P9N2_EX_L2_CORE_FIR_UNUSED_46 = 46 ;
+static const uint8_t P9N2_EX_L2_CORE_FIR_PC_TFAC_XSTOP_ERROR = 47 ;
+static const uint8_t P9N2_EX_L2_CORE_FIR_PC_HYP_RES_ERROR = 48 ;
+static const uint8_t P9N2_EX_L2_CORE_FIR_UNUSED_49 = 49 ;
+static const uint8_t P9N2_EX_L2_CORE_FIR_UNUSED_50 = 50 ;
+static const uint8_t P9N2_EX_L2_CORE_FIR_UNUSED_51 = 51 ;
+static const uint8_t P9N2_EX_L2_CORE_FIR_PC_HANG_RECOVERY_FAILED = 52 ;
+static const uint8_t P9N2_EX_L2_CORE_FIR_PC_HANG_DETECT_ERROR = 53 ;
+static const uint8_t P9N2_EX_L2_CORE_FIR_UNUSED_54 = 54 ;
+static const uint8_t P9N2_EX_L2_CORE_FIR_PC_NEST_HANG_DETECT_ERROR = 55 ;
+static const uint8_t P9N2_EX_L2_CORE_FIR_PC_OTHER_CHIPLET_REC_ERROR = 56 ;
+static const uint8_t P9N2_EX_L2_CORE_FIR_PC_OTHER_CHIPLET_XSTOP_ERROR = 57 ;
+static const uint8_t P9N2_EX_L2_CORE_FIR_PC_OTHER_CHIPLET_SYS_XSTOP_ERROR = 58 ;
+static const uint8_t P9N2_EX_L2_CORE_FIR_PC_SCOM_ERROR = 59 ;
+static const uint8_t P9N2_EX_L2_CORE_FIR_PC_XSTOP_ON_DBG_TRIGGER_ERROR = 60 ;
+static const uint8_t P9N2_EX_L2_CORE_FIR_PC_FW_INJ_REC_ERROR = 61 ;
+static const uint8_t P9N2_EX_L2_CORE_FIR_PC_FW_INJ_XSTOP_ERROR = 62 ;
+static const uint8_t P9N2_EX_L2_CORE_FIR_PC_PHYP_XSTOP_ERROR = 63 ;
+
+static const uint8_t P9N2_C_CORE_FIR_IF_SRAM_REC_ERROR = 0 ;
+static const uint8_t P9N2_C_CORE_FIR_TC_XSTOP_ERROR = 1 ;
+static const uint8_t P9N2_C_CORE_FIR_IF_RFILE_REC_ERROR = 2 ;
+static const uint8_t P9N2_C_CORE_FIR_IF_RFILE_XSTOP_ERROR = 3 ;
+static const uint8_t P9N2_C_CORE_FIR_IF_LOG_REC_ERROR = 4 ;
+static const uint8_t P9N2_C_CORE_FIR_IF_LOG_XSTOP_ERROR = 5 ;
+static const uint8_t P9N2_C_CORE_FIR_UNUSED_6 = 6 ;
+static const uint8_t P9N2_C_CORE_FIR_UNUSED_7 = 7 ;
+static const uint8_t P9N2_C_CORE_FIR_PC_RECOV_XSTOP_ERROR = 8 ;
+static const uint8_t P9N2_C_CORE_FIR_SD_RFILE_REC_ERROR = 9 ;
+static const uint8_t P9N2_C_CORE_FIR_SD_RFILE_XSTOP_ERROR = 10 ;
+static const uint8_t P9N2_C_CORE_FIR_SD_LOG_REC_ERROR = 11 ;
+static const uint8_t P9N2_C_CORE_FIR_SD_LOG_XSTOP_ERROR = 12 ;
+static const uint8_t P9N2_C_CORE_FIR_SD_NOT_MT_CI_REC_ERROR = 13 ;
+static const uint8_t P9N2_C_CORE_FIR_SD_MCHK_AND_ME_EQ_0_ERROR = 14 ;
+static const uint8_t P9N2_C_CORE_FIR_SD_L2_UE_ERROR = 15 ;
+static const uint8_t P9N2_C_CORE_FIR_SD_L2_UE_OVER_THRES_ERROR = 16 ;
+static const uint8_t P9N2_C_CORE_FIR_SD_CI_UE_ERROR = 17 ;
+static const uint8_t P9N2_C_CORE_FIR_UNUSED_18 = 18 ;
+static const uint8_t P9N2_C_CORE_FIR_UNUSED_19 = 19 ;
+static const uint8_t P9N2_C_CORE_FIR_SD_SYS_XSTOP_ERROR = 20 ;
+static const uint8_t P9N2_C_CORE_FIR_UNUSED_21 = 21 ;
+static const uint8_t P9N2_C_CORE_FIR_UNUSED_22 = 22 ;
+static const uint8_t P9N2_C_CORE_FIR_UNUSED_23 = 23 ;
+static const uint8_t P9N2_C_CORE_FIR_VS_LOG_REC_ERROR = 24 ;
+static const uint8_t P9N2_C_CORE_FIR_VS_LOG_XSTOP_ERROR = 25 ;
+static const uint8_t P9N2_C_CORE_FIR_PC_RECOV_IN_MAINT_ERROR = 26 ;
+static const uint8_t P9N2_C_CORE_FIR_VS_DU_LOG_REC_ERROR = 27 ;
+static const uint8_t P9N2_C_CORE_FIR_PC_SYS_XSTOP_ERROR = 28 ;
+static const uint8_t P9N2_C_CORE_FIR_LS_SRAM_PARITY_ERROR = 29 ;
+static const uint8_t P9N2_C_CORE_FIR_LS_SETDELETE_ERROR = 30 ;
+static const uint8_t P9N2_C_CORE_FIR_LS_RFILE_REC_ERROR = 31 ;
+static const uint8_t P9N2_C_CORE_FIR_LS_RFILE_XSTOP_ERROR = 32 ;
+static const uint8_t P9N2_C_CORE_FIR_LS_TLB_MULTIHIT_ERROR = 33 ;
+static const uint8_t P9N2_C_CORE_FIR_LS_SLB_MULTIHIT_ERROR = 34 ;
+static const uint8_t P9N2_C_CORE_FIR_LS_DERAT_MULTIHIT_ERROR = 35 ;
+static const uint8_t P9N2_C_CORE_FIR_PC_FWD_PROGRESS_ERROR = 36 ;
+static const uint8_t P9N2_C_CORE_FIR_LS_LOG_REC_ERROR = 37 ;
+static const uint8_t P9N2_C_CORE_FIR_LS_LOG_XSTOP_ERROR = 38 ;
+static const uint8_t P9N2_C_CORE_FIR_UNUSED_39 = 39 ;
+static const uint8_t P9N2_C_CORE_FIR_UNUSED_40 = 40 ;
+static const uint8_t P9N2_C_CORE_FIR_LS_SYS_XSTOP_ERROR = 41 ;
+static const uint8_t P9N2_C_CORE_FIR_UNUSED_42 = 42 ;
+static const uint8_t P9N2_C_CORE_FIR_PC_THREAD_HANG_REC_ERROR = 43 ;
+static const uint8_t P9N2_C_CORE_FIR_UNUSED_44 = 44 ;
+static const uint8_t P9N2_C_CORE_FIR_PC_LOG_XSTOP_ERROR = 45 ;
+static const uint8_t P9N2_C_CORE_FIR_UNUSED_46 = 46 ;
+static const uint8_t P9N2_C_CORE_FIR_PC_TFAC_XSTOP_ERROR = 47 ;
+static const uint8_t P9N2_C_CORE_FIR_PC_HYP_RES_ERROR = 48 ;
+static const uint8_t P9N2_C_CORE_FIR_UNUSED_49 = 49 ;
+static const uint8_t P9N2_C_CORE_FIR_UNUSED_50 = 50 ;
+static const uint8_t P9N2_C_CORE_FIR_UNUSED_51 = 51 ;
+static const uint8_t P9N2_C_CORE_FIR_PC_HANG_RECOVERY_FAILED = 52 ;
+static const uint8_t P9N2_C_CORE_FIR_PC_HANG_DETECT_ERROR = 53 ;
+static const uint8_t P9N2_C_CORE_FIR_UNUSED_54 = 54 ;
+static const uint8_t P9N2_C_CORE_FIR_PC_NEST_HANG_DETECT_ERROR = 55 ;
+static const uint8_t P9N2_C_CORE_FIR_PC_OTHER_CHIPLET_REC_ERROR = 56 ;
+static const uint8_t P9N2_C_CORE_FIR_PC_OTHER_CHIPLET_XSTOP_ERROR = 57 ;
+static const uint8_t P9N2_C_CORE_FIR_PC_OTHER_CHIPLET_SYS_XSTOP_ERROR = 58 ;
+static const uint8_t P9N2_C_CORE_FIR_PC_SCOM_ERROR = 59 ;
+static const uint8_t P9N2_C_CORE_FIR_PC_XSTOP_ON_DBG_TRIGGER_ERROR = 60 ;
+static const uint8_t P9N2_C_CORE_FIR_PC_FW_INJ_REC_ERROR = 61 ;
+static const uint8_t P9N2_C_CORE_FIR_PC_FW_INJ_XSTOP_ERROR = 62 ;
+static const uint8_t P9N2_C_CORE_FIR_PC_PHYP_XSTOP_ERROR = 63 ;
+
+static const uint8_t P9N2_EX_L2_CORE_FIRMASK_MASK_IF_SRAM_REC_ERROR = 0 ;
+static const uint8_t P9N2_EX_L2_CORE_FIRMASK_MASK_TC_FIR_XSTOP_ERROR = 1 ;
+static const uint8_t P9N2_EX_L2_CORE_FIRMASK_MASK_IF_RFILE_REC_ERROR = 2 ;
+static const uint8_t P9N2_EX_L2_CORE_FIRMASK_MASK_IF_RFILE_XSTOP_ERROR = 3 ;
+static const uint8_t P9N2_EX_L2_CORE_FIRMASK_MASK_IF_LOG_REC_ERROR = 4 ;
+static const uint8_t P9N2_EX_L2_CORE_FIRMASK_MASK_IF_LOG_XSTOP_ERROR = 5 ;
+static const uint8_t P9N2_EX_L2_CORE_FIRMASK_MASK_UNUSED_6 = 6 ;
+static const uint8_t P9N2_EX_L2_CORE_FIRMASK_MASK_UNUSED_7 = 7 ;
+static const uint8_t P9N2_EX_L2_CORE_FIRMASK_MASK_PC_RECOV_XSTOP_ERROR = 8 ;
+static const uint8_t P9N2_EX_L2_CORE_FIRMASK_MASK_SD_RFILE_REC_ERROR = 9 ;
+static const uint8_t P9N2_EX_L2_CORE_FIRMASK_MASK_SD_RFILE_XSTOP_ERROR = 10 ;
+static const uint8_t P9N2_EX_L2_CORE_FIRMASK_MASK_SD_LOG_REC_ERROR = 11 ;
+static const uint8_t P9N2_EX_L2_CORE_FIRMASK_MASK_SD_LOG_XSTOP_ERROR = 12 ;
+static const uint8_t P9N2_EX_L2_CORE_FIRMASK_MASK_SD_NOT_MT_CI_REC_ERROR = 13 ;
+static const uint8_t P9N2_EX_L2_CORE_FIRMASK_MASK_SD_MCHK_AND_ME_EQ_0_ERROR = 14 ;
+static const uint8_t P9N2_EX_L2_CORE_FIRMASK_MASK_SD_L2_UE_ERROR = 15 ;
+static const uint8_t P9N2_EX_L2_CORE_FIRMASK_MASK_SD_L2_UE_OVER_THRES_ERROR = 16 ;
+static const uint8_t P9N2_EX_L2_CORE_FIRMASK_MASK_SD_CI_UE_ERROR = 17 ;
+static const uint8_t P9N2_EX_L2_CORE_FIRMASK_MASK_UNUSED_18 = 18 ;
+static const uint8_t P9N2_EX_L2_CORE_FIRMASK_MASK_UNUSED_19 = 19 ;
+static const uint8_t P9N2_EX_L2_CORE_FIRMASK_MASK_SD_SYS_XSTOP_ERROR = 20 ;
+static const uint8_t P9N2_EX_L2_CORE_FIRMASK_MASK_UNUSED_21 = 21 ;
+static const uint8_t P9N2_EX_L2_CORE_FIRMASK_MASK_UNUSED_22 = 22 ;
+static const uint8_t P9N2_EX_L2_CORE_FIRMASK_MASK_UNUSED_23 = 23 ;
+static const uint8_t P9N2_EX_L2_CORE_FIRMASK_MASK_VS_LOG_REC_ERROR = 24 ;
+static const uint8_t P9N2_EX_L2_CORE_FIRMASK_MASK_VS_LOG_XSTOP_ERROR = 25 ;
+static const uint8_t P9N2_EX_L2_CORE_FIRMASK_MASK_PC_RECOV_IN_MAINT_ERROR = 26 ;
+static const uint8_t P9N2_EX_L2_CORE_FIRMASK_MASK_VS_DU_LOG_REC_ERROR = 27 ;
+static const uint8_t P9N2_EX_L2_CORE_FIRMASK_MASK_PC_SYS_XSTOP_ERROR = 28 ;
+static const uint8_t P9N2_EX_L2_CORE_FIRMASK_MASK_LS_SRAM_PARITY_ERROR = 29 ;
+static const uint8_t P9N2_EX_L2_CORE_FIRMASK_MASK_LS_SETDELETE_ERROR = 30 ;
+static const uint8_t P9N2_EX_L2_CORE_FIRMASK_MASK_LS_RFILE_REC_ERROR = 31 ;
+static const uint8_t P9N2_EX_L2_CORE_FIRMASK_MASK_LS_RFILE_XSTOP_ERROR = 32 ;
+static const uint8_t P9N2_EX_L2_CORE_FIRMASK_MASK_LS_TLB_MULTIHIT_ERROR = 33 ;
+static const uint8_t P9N2_EX_L2_CORE_FIRMASK_MASK_LS_SLB_MULTIHIT_ERROR = 34 ;
+static const uint8_t P9N2_EX_L2_CORE_FIRMASK_MASK_LS_DERAT_MULTIHIT_ERROR = 35 ;
+static const uint8_t P9N2_EX_L2_CORE_FIRMASK_MASK_PC_FWD_PROGRESS_ERROR = 36 ;
+static const uint8_t P9N2_EX_L2_CORE_FIRMASK_MASK_LS_LOG_REC_ERROR = 37 ;
+static const uint8_t P9N2_EX_L2_CORE_FIRMASK_MASK_LS_LOG_XSTOP_ERROR = 38 ;
+static const uint8_t P9N2_EX_L2_CORE_FIRMASK_MASK_UNUSED_39 = 39 ;
+static const uint8_t P9N2_EX_L2_CORE_FIRMASK_MASK_UNUSED_40 = 40 ;
+static const uint8_t P9N2_EX_L2_CORE_FIRMASK_MASK_LS_SYS_XSTOP_ERROR = 41 ;
+static const uint8_t P9N2_EX_L2_CORE_FIRMASK_MASK_UNUSED_42 = 42 ;
+static const uint8_t P9N2_EX_L2_CORE_FIRMASK_MASK_PC_THREAD_HANG_REC_ERROR = 43 ;
+static const uint8_t P9N2_EX_L2_CORE_FIRMASK_MASK_UNUSED_44 = 44 ;
+static const uint8_t P9N2_EX_L2_CORE_FIRMASK_MASK_PC_LOG_XSTOP_ERROR = 45 ;
+static const uint8_t P9N2_EX_L2_CORE_FIRMASK_MASK_UNUSED_46 = 46 ;
+static const uint8_t P9N2_EX_L2_CORE_FIRMASK_MASK_PC_TFAC_XSTOP_ERROR = 47 ;
+static const uint8_t P9N2_EX_L2_CORE_FIRMASK_MASK_PC_HYP_RES_ERROR = 48 ;
+static const uint8_t P9N2_EX_L2_CORE_FIRMASK_MASK_UNUSED_49 = 49 ;
+static const uint8_t P9N2_EX_L2_CORE_FIRMASK_MASK_UNUSED_50 = 50 ;
+static const uint8_t P9N2_EX_L2_CORE_FIRMASK_MASK_UNUSED_51 = 51 ;
+static const uint8_t P9N2_EX_L2_CORE_FIRMASK_MASK_PC_HANG_RECOVERY_FAILED = 52 ;
+static const uint8_t P9N2_EX_L2_CORE_FIRMASK_MASK_PC_HANG_DETECT_ERROR = 53 ;
+static const uint8_t P9N2_EX_L2_CORE_FIRMASK_MASK_UNUSED_54 = 54 ;
+static const uint8_t P9N2_EX_L2_CORE_FIRMASK_MASK_PC_NEST_HANG_DETECT_ERROR = 55 ;
+static const uint8_t P9N2_EX_L2_CORE_FIRMASK_MASK_PC_OTHER_CHIPLET_REC_ERROR = 56 ;
+static const uint8_t P9N2_EX_L2_CORE_FIRMASK_MASK_PC_OTHER_CHIPLET_XSTOP_ERROR = 57 ;
+static const uint8_t P9N2_EX_L2_CORE_FIRMASK_MASK_PC_OTHER_CHIPLET_SYS_XSTOP_ERROR = 58 ;
+static const uint8_t P9N2_EX_L2_CORE_FIRMASK_MASK_PC_SCOM_ERROR = 59 ;
+static const uint8_t P9N2_EX_L2_CORE_FIRMASK_MASK_PC_XSTOP_ON_DBG_TRIGGER_ERROR = 60 ;
+static const uint8_t P9N2_EX_L2_CORE_FIRMASK_MASK_PC_FW_INJ_REC_ERROR = 61 ;
+static const uint8_t P9N2_EX_L2_CORE_FIRMASK_MASK_PC_FW_INJ_XSTOP_ERROR = 62 ;
+static const uint8_t P9N2_EX_L2_CORE_FIRMASK_MASK_PC_PHYP_XSTOP_ERROR = 63 ;
+
+static const uint8_t P9N2_C_CORE_FIRMASK_MASK_IF_SRAM_REC_ERROR = 0 ;
+static const uint8_t P9N2_C_CORE_FIRMASK_MASK_TC_FIR_XSTOP_ERROR = 1 ;
+static const uint8_t P9N2_C_CORE_FIRMASK_MASK_IF_RFILE_REC_ERROR = 2 ;
+static const uint8_t P9N2_C_CORE_FIRMASK_MASK_IF_RFILE_XSTOP_ERROR = 3 ;
+static const uint8_t P9N2_C_CORE_FIRMASK_MASK_IF_LOG_REC_ERROR = 4 ;
+static const uint8_t P9N2_C_CORE_FIRMASK_MASK_IF_LOG_XSTOP_ERROR = 5 ;
+static const uint8_t P9N2_C_CORE_FIRMASK_MASK_UNUSED_6 = 6 ;
+static const uint8_t P9N2_C_CORE_FIRMASK_MASK_UNUSED_7 = 7 ;
+static const uint8_t P9N2_C_CORE_FIRMASK_MASK_PC_RECOV_XSTOP_ERROR = 8 ;
+static const uint8_t P9N2_C_CORE_FIRMASK_MASK_SD_RFILE_REC_ERROR = 9 ;
+static const uint8_t P9N2_C_CORE_FIRMASK_MASK_SD_RFILE_XSTOP_ERROR = 10 ;
+static const uint8_t P9N2_C_CORE_FIRMASK_MASK_SD_LOG_REC_ERROR = 11 ;
+static const uint8_t P9N2_C_CORE_FIRMASK_MASK_SD_LOG_XSTOP_ERROR = 12 ;
+static const uint8_t P9N2_C_CORE_FIRMASK_MASK_SD_NOT_MT_CI_REC_ERROR = 13 ;
+static const uint8_t P9N2_C_CORE_FIRMASK_MASK_SD_MCHK_AND_ME_EQ_0_ERROR = 14 ;
+static const uint8_t P9N2_C_CORE_FIRMASK_MASK_SD_L2_UE_ERROR = 15 ;
+static const uint8_t P9N2_C_CORE_FIRMASK_MASK_SD_L2_UE_OVER_THRES_ERROR = 16 ;
+static const uint8_t P9N2_C_CORE_FIRMASK_MASK_SD_CI_UE_ERROR = 17 ;
+static const uint8_t P9N2_C_CORE_FIRMASK_MASK_UNUSED_18 = 18 ;
+static const uint8_t P9N2_C_CORE_FIRMASK_MASK_UNUSED_19 = 19 ;
+static const uint8_t P9N2_C_CORE_FIRMASK_MASK_SD_SYS_XSTOP_ERROR = 20 ;
+static const uint8_t P9N2_C_CORE_FIRMASK_MASK_UNUSED_21 = 21 ;
+static const uint8_t P9N2_C_CORE_FIRMASK_MASK_UNUSED_22 = 22 ;
+static const uint8_t P9N2_C_CORE_FIRMASK_MASK_UNUSED_23 = 23 ;
+static const uint8_t P9N2_C_CORE_FIRMASK_MASK_VS_LOG_REC_ERROR = 24 ;
+static const uint8_t P9N2_C_CORE_FIRMASK_MASK_VS_LOG_XSTOP_ERROR = 25 ;
+static const uint8_t P9N2_C_CORE_FIRMASK_MASK_PC_RECOV_IN_MAINT_ERROR = 26 ;
+static const uint8_t P9N2_C_CORE_FIRMASK_MASK_VS_DU_LOG_REC_ERROR = 27 ;
+static const uint8_t P9N2_C_CORE_FIRMASK_MASK_PC_SYS_XSTOP_ERROR = 28 ;
+static const uint8_t P9N2_C_CORE_FIRMASK_MASK_LS_SRAM_PARITY_ERROR = 29 ;
+static const uint8_t P9N2_C_CORE_FIRMASK_MASK_LS_SETDELETE_ERROR = 30 ;
+static const uint8_t P9N2_C_CORE_FIRMASK_MASK_LS_RFILE_REC_ERROR = 31 ;
+static const uint8_t P9N2_C_CORE_FIRMASK_MASK_LS_RFILE_XSTOP_ERROR = 32 ;
+static const uint8_t P9N2_C_CORE_FIRMASK_MASK_LS_TLB_MULTIHIT_ERROR = 33 ;
+static const uint8_t P9N2_C_CORE_FIRMASK_MASK_LS_SLB_MULTIHIT_ERROR = 34 ;
+static const uint8_t P9N2_C_CORE_FIRMASK_MASK_LS_DERAT_MULTIHIT_ERROR = 35 ;
+static const uint8_t P9N2_C_CORE_FIRMASK_MASK_PC_FWD_PROGRESS_ERROR = 36 ;
+static const uint8_t P9N2_C_CORE_FIRMASK_MASK_LS_LOG_REC_ERROR = 37 ;
+static const uint8_t P9N2_C_CORE_FIRMASK_MASK_LS_LOG_XSTOP_ERROR = 38 ;
+static const uint8_t P9N2_C_CORE_FIRMASK_MASK_UNUSED_39 = 39 ;
+static const uint8_t P9N2_C_CORE_FIRMASK_MASK_UNUSED_40 = 40 ;
+static const uint8_t P9N2_C_CORE_FIRMASK_MASK_LS_SYS_XSTOP_ERROR = 41 ;
+static const uint8_t P9N2_C_CORE_FIRMASK_MASK_UNUSED_42 = 42 ;
+static const uint8_t P9N2_C_CORE_FIRMASK_MASK_PC_THREAD_HANG_REC_ERROR = 43 ;
+static const uint8_t P9N2_C_CORE_FIRMASK_MASK_UNUSED_44 = 44 ;
+static const uint8_t P9N2_C_CORE_FIRMASK_MASK_PC_LOG_XSTOP_ERROR = 45 ;
+static const uint8_t P9N2_C_CORE_FIRMASK_MASK_UNUSED_46 = 46 ;
+static const uint8_t P9N2_C_CORE_FIRMASK_MASK_PC_TFAC_XSTOP_ERROR = 47 ;
+static const uint8_t P9N2_C_CORE_FIRMASK_MASK_PC_HYP_RES_ERROR = 48 ;
+static const uint8_t P9N2_C_CORE_FIRMASK_MASK_UNUSED_49 = 49 ;
+static const uint8_t P9N2_C_CORE_FIRMASK_MASK_UNUSED_50 = 50 ;
+static const uint8_t P9N2_C_CORE_FIRMASK_MASK_UNUSED_51 = 51 ;
+static const uint8_t P9N2_C_CORE_FIRMASK_MASK_PC_HANG_RECOVERY_FAILED = 52 ;
+static const uint8_t P9N2_C_CORE_FIRMASK_MASK_PC_HANG_DETECT_ERROR = 53 ;
+static const uint8_t P9N2_C_CORE_FIRMASK_MASK_UNUSED_54 = 54 ;
+static const uint8_t P9N2_C_CORE_FIRMASK_MASK_PC_NEST_HANG_DETECT_ERROR = 55 ;
+static const uint8_t P9N2_C_CORE_FIRMASK_MASK_PC_OTHER_CHIPLET_REC_ERROR = 56 ;
+static const uint8_t P9N2_C_CORE_FIRMASK_MASK_PC_OTHER_CHIPLET_XSTOP_ERROR = 57 ;
+static const uint8_t P9N2_C_CORE_FIRMASK_MASK_PC_OTHER_CHIPLET_SYS_XSTOP_ERROR = 58 ;
+static const uint8_t P9N2_C_CORE_FIRMASK_MASK_PC_SCOM_ERROR = 59 ;
+static const uint8_t P9N2_C_CORE_FIRMASK_MASK_PC_XSTOP_ON_DBG_TRIGGER_ERROR = 60 ;
+static const uint8_t P9N2_C_CORE_FIRMASK_MASK_PC_FW_INJ_REC_ERROR = 61 ;
+static const uint8_t P9N2_C_CORE_FIRMASK_MASK_PC_FW_INJ_XSTOP_ERROR = 62 ;
+static const uint8_t P9N2_C_CORE_FIRMASK_MASK_PC_PHYP_XSTOP_ERROR = 63 ;
+
+static const uint8_t P9N2_EX_L2_CORE_FUSES_FP_THROTTLE_EN = 0 ;
+static const uint8_t P9N2_EX_L2_CORE_FUSES_VMX_CRYPTO_DIS = 1 ;
+
+static const uint8_t P9N2_C_CORE_FUSES_FP_THROTTLE_EN = 0 ;
+static const uint8_t P9N2_C_CORE_FUSES_VMX_CRYPTO_DIS = 1 ;
+
+static const uint8_t P9N2_EX_L2_CORE_THREAD_STATE_VT0_PSSCR_RL = 32 ;
+static const uint8_t P9N2_EX_L2_CORE_THREAD_STATE_VT0_PSSCR_RL_LEN = 4 ;
+static const uint8_t P9N2_EX_L2_CORE_THREAD_STATE_VT1_PSSCR_RL = 36 ;
+static const uint8_t P9N2_EX_L2_CORE_THREAD_STATE_VT1_PSSCR_RL_LEN = 4 ;
+static const uint8_t P9N2_EX_L2_CORE_THREAD_STATE_VT2_PSSCR_RL = 40 ;
+static const uint8_t P9N2_EX_L2_CORE_THREAD_STATE_VT2_PSSCR_RL_LEN = 4 ;
+static const uint8_t P9N2_EX_L2_CORE_THREAD_STATE_VT3_PSSCR_RL = 44 ;
+static const uint8_t P9N2_EX_L2_CORE_THREAD_STATE_VT3_PSSCR_RL_LEN = 4 ;
+static const uint8_t P9N2_EX_L2_CORE_THREAD_STATE_VT0_STOP_STATE = 56 ;
+static const uint8_t P9N2_EX_L2_CORE_THREAD_STATE_VT1_STOP_STATE = 57 ;
+static const uint8_t P9N2_EX_L2_CORE_THREAD_STATE_VT2_STOP_STATE = 58 ;
+static const uint8_t P9N2_EX_L2_CORE_THREAD_STATE_VT3_STOP_STATE = 59 ;
+static const uint8_t P9N2_EX_L2_CORE_THREAD_STATE_LPAR_MODE = 62 ;
+static const uint8_t P9N2_EX_L2_CORE_THREAD_STATE_FUSED_CORE_MODE = 63 ;
+
+static const uint8_t P9N2_C_CORE_THREAD_STATE_VT0_PSSCR_RL = 32 ;
+static const uint8_t P9N2_C_CORE_THREAD_STATE_VT0_PSSCR_RL_LEN = 4 ;
+static const uint8_t P9N2_C_CORE_THREAD_STATE_VT1_PSSCR_RL = 36 ;
+static const uint8_t P9N2_C_CORE_THREAD_STATE_VT1_PSSCR_RL_LEN = 4 ;
+static const uint8_t P9N2_C_CORE_THREAD_STATE_VT2_PSSCR_RL = 40 ;
+static const uint8_t P9N2_C_CORE_THREAD_STATE_VT2_PSSCR_RL_LEN = 4 ;
+static const uint8_t P9N2_C_CORE_THREAD_STATE_VT3_PSSCR_RL = 44 ;
+static const uint8_t P9N2_C_CORE_THREAD_STATE_VT3_PSSCR_RL_LEN = 4 ;
+static const uint8_t P9N2_C_CORE_THREAD_STATE_VT0_STOP_STATE = 56 ;
+static const uint8_t P9N2_C_CORE_THREAD_STATE_VT1_STOP_STATE = 57 ;
+static const uint8_t P9N2_C_CORE_THREAD_STATE_VT2_STOP_STATE = 58 ;
+static const uint8_t P9N2_C_CORE_THREAD_STATE_VT3_STOP_STATE = 59 ;
+static const uint8_t P9N2_C_CORE_THREAD_STATE_LPAR_MODE = 62 ;
+static const uint8_t P9N2_C_CORE_THREAD_STATE_FUSED_CORE_MODE = 63 ;
+
+static const uint8_t P9N2_EX_CORE_WOF_WOF_IF_SRAM_REC_ERROR = 0 ;
+static const uint8_t P9N2_EX_CORE_WOF_WOF_TC_FIR_XSTOP_ERROR = 1 ;
+static const uint8_t P9N2_EX_CORE_WOF_WOF_IF_RFILE_REC_ERROR = 2 ;
+static const uint8_t P9N2_EX_CORE_WOF_WOF_IF_RFILE_XSTOP_ERROR = 3 ;
+static const uint8_t P9N2_EX_CORE_WOF_WOF_IF_LOG_REC_ERROR = 4 ;
+static const uint8_t P9N2_EX_CORE_WOF_WOF_IF_LOG_XSTOP_ERROR = 5 ;
+static const uint8_t P9N2_EX_CORE_WOF_WOF_UNUSED_6 = 6 ;
+static const uint8_t P9N2_EX_CORE_WOF_WOF_UNUSED_7 = 7 ;
+static const uint8_t P9N2_EX_CORE_WOF_WOF_PC_RECOV_XSTOP_ERROR = 8 ;
+static const uint8_t P9N2_EX_CORE_WOF_WOF_SD_RFILE_REC_ERROR = 9 ;
+static const uint8_t P9N2_EX_CORE_WOF_WOF_SD_RFILE_XSTOP_ERROR = 10 ;
+static const uint8_t P9N2_EX_CORE_WOF_WOF_SD_LOG_REC_ERROR = 11 ;
+static const uint8_t P9N2_EX_CORE_WOF_WOF_SD_LOG_XSTOP_ERROR = 12 ;
+static const uint8_t P9N2_EX_CORE_WOF_WOF_SD_NOT_MT_CI_REC_ERROR = 13 ;
+static const uint8_t P9N2_EX_CORE_WOF_WOF_SD_MCHK_AND_ME_EQ_0_ERROR = 14 ;
+static const uint8_t P9N2_EX_CORE_WOF_WOF_SD_L2_UE_ERROR = 15 ;
+static const uint8_t P9N2_EX_CORE_WOF_WOF_SD_L2_UE_OVER_THRES_ERROR = 16 ;
+static const uint8_t P9N2_EX_CORE_WOF_WOF_SD_CI_UE_ERROR = 17 ;
+static const uint8_t P9N2_EX_CORE_WOF_WOF_UNUSED_18 = 18 ;
+static const uint8_t P9N2_EX_CORE_WOF_WOF_UNUSED_19 = 19 ;
+static const uint8_t P9N2_EX_CORE_WOF_WOF_SD_SYS_XSTOP_ERROR = 20 ;
+static const uint8_t P9N2_EX_CORE_WOF_WOF_UNUSED_21 = 21 ;
+static const uint8_t P9N2_EX_CORE_WOF_WOF_UNUSED_22 = 22 ;
+static const uint8_t P9N2_EX_CORE_WOF_WOF_UNUSED_23 = 23 ;
+static const uint8_t P9N2_EX_CORE_WOF_WOF_VS_LOG_REC_ERROR = 24 ;
+static const uint8_t P9N2_EX_CORE_WOF_WOF_VS_LOG_XSTOP_ERROR = 25 ;
+static const uint8_t P9N2_EX_CORE_WOF_WOF_PC_RECOV_IN_MAINT_ERROR = 26 ;
+static const uint8_t P9N2_EX_CORE_WOF_WOF_VS_DU_LOG_REC_ERROR = 27 ;
+static const uint8_t P9N2_EX_CORE_WOF_WOF_PC_SYS_XSTOP_ERROR = 28 ;
+static const uint8_t P9N2_EX_CORE_WOF_WOF_LS_SRAM_PARITY_ERROR = 29 ;
+static const uint8_t P9N2_EX_CORE_WOF_WOF_LS_SETDELETE_ERROR = 30 ;
+static const uint8_t P9N2_EX_CORE_WOF_WOF_LS_RFILE_REC_ERROR = 31 ;
+static const uint8_t P9N2_EX_CORE_WOF_WOF_LS_RFILE_XSTOP_ERROR = 32 ;
+static const uint8_t P9N2_EX_CORE_WOF_WOF_LS_TLB_MULTIHIT_ERROR = 33 ;
+static const uint8_t P9N2_EX_CORE_WOF_WOF_LS_SLB_MULTIHIT_ERROR = 34 ;
+static const uint8_t P9N2_EX_CORE_WOF_WOF_LS_DERAT_MULTIHIT_ERROR = 35 ;
+static const uint8_t P9N2_EX_CORE_WOF_WOF_PC_FWD_PROGRESS_ERROR = 36 ;
+static const uint8_t P9N2_EX_CORE_WOF_WOF_LS_LOG_REC_ERROR = 37 ;
+static const uint8_t P9N2_EX_CORE_WOF_WOF_LS_LOG_XSTOP_ERROR = 38 ;
+static const uint8_t P9N2_EX_CORE_WOF_WOF_UNUSED_39 = 39 ;
+static const uint8_t P9N2_EX_CORE_WOF_WOF_UNUSED_40 = 40 ;
+static const uint8_t P9N2_EX_CORE_WOF_WOF_LS_SYS_XSTOP_ERROR = 41 ;
+static const uint8_t P9N2_EX_CORE_WOF_WOF_UNUSED_42 = 42 ;
+static const uint8_t P9N2_EX_CORE_WOF_WOF_PC_THREAD_HANG_REC_ERROR = 43 ;
+static const uint8_t P9N2_EX_CORE_WOF_WOF_UNUSED_44 = 44 ;
+static const uint8_t P9N2_EX_CORE_WOF_WOF_PC_LOG_XSTOP_ERROR = 45 ;
+static const uint8_t P9N2_EX_CORE_WOF_WOF_UNUSED_46 = 46 ;
+static const uint8_t P9N2_EX_CORE_WOF_WOF_PC_TFAC_XSTOP_ERROR = 47 ;
+static const uint8_t P9N2_EX_CORE_WOF_WOF_PC_HYP_RES_ERROR = 48 ;
+static const uint8_t P9N2_EX_CORE_WOF_WOF_UNUSED_49 = 49 ;
+static const uint8_t P9N2_EX_CORE_WOF_WOF_UNUSED_50 = 50 ;
+static const uint8_t P9N2_EX_CORE_WOF_WOF_UNUSED_51 = 51 ;
+static const uint8_t P9N2_EX_CORE_WOF_WOF_PC_HANG_RECOVERY_FAILED = 52 ;
+static const uint8_t P9N2_EX_CORE_WOF_WOF_PC_CORE_HANG_DETECT_ERROR = 53 ;
+static const uint8_t P9N2_EX_CORE_WOF_WOF_UNUSED_54 = 54 ;
+static const uint8_t P9N2_EX_CORE_WOF_WOF_PC_NEST_HANG_DETECT_ERROR = 55 ;
+static const uint8_t P9N2_EX_CORE_WOF_WOF_PC_OTHER_CORE_CHIPLET_REC_ERROR = 56 ;
+static const uint8_t P9N2_EX_CORE_WOF_WOF_PC_OTHER_CORE_CHIPLET_XSTOP_ERROR = 57 ;
+static const uint8_t P9N2_EX_CORE_WOF_WOF_PC_OTHER_CORE_CHIPLET_SYS_XSTOP_ERROR = 58 ;
+static const uint8_t P9N2_EX_CORE_WOF_WOF_PC_SCOM_ERROR = 59 ;
+static const uint8_t P9N2_EX_CORE_WOF_WOF_PC_XSTOP_ON_DBG_TRIGGER_ERROR = 60 ;
+static const uint8_t P9N2_EX_CORE_WOF_WOF_PC_FW_INJ_REC_ERROR = 61 ;
+static const uint8_t P9N2_EX_CORE_WOF_WOF_PC_FW_INJ_XSTOP_ERROR = 62 ;
+static const uint8_t P9N2_EX_CORE_WOF_WOF_PC_PHYP_XSTOP_ERROR = 63 ;
+
+static const uint8_t P9N2_C_CORE_WOF_WOF_IF_SRAM_REC_ERROR = 0 ;
+static const uint8_t P9N2_C_CORE_WOF_WOF_TC_FIR_XSTOP_ERROR = 1 ;
+static const uint8_t P9N2_C_CORE_WOF_WOF_IF_RFILE_REC_ERROR = 2 ;
+static const uint8_t P9N2_C_CORE_WOF_WOF_IF_RFILE_XSTOP_ERROR = 3 ;
+static const uint8_t P9N2_C_CORE_WOF_WOF_IF_LOG_REC_ERROR = 4 ;
+static const uint8_t P9N2_C_CORE_WOF_WOF_IF_LOG_XSTOP_ERROR = 5 ;
+static const uint8_t P9N2_C_CORE_WOF_WOF_UNUSED_6 = 6 ;
+static const uint8_t P9N2_C_CORE_WOF_WOF_UNUSED_7 = 7 ;
+static const uint8_t P9N2_C_CORE_WOF_WOF_PC_RECOV_XSTOP_ERROR = 8 ;
+static const uint8_t P9N2_C_CORE_WOF_WOF_SD_RFILE_REC_ERROR = 9 ;
+static const uint8_t P9N2_C_CORE_WOF_WOF_SD_RFILE_XSTOP_ERROR = 10 ;
+static const uint8_t P9N2_C_CORE_WOF_WOF_SD_LOG_REC_ERROR = 11 ;
+static const uint8_t P9N2_C_CORE_WOF_WOF_SD_LOG_XSTOP_ERROR = 12 ;
+static const uint8_t P9N2_C_CORE_WOF_WOF_SD_NOT_MT_CI_REC_ERROR = 13 ;
+static const uint8_t P9N2_C_CORE_WOF_WOF_SD_MCHK_AND_ME_EQ_0_ERROR = 14 ;
+static const uint8_t P9N2_C_CORE_WOF_WOF_SD_L2_UE_ERROR = 15 ;
+static const uint8_t P9N2_C_CORE_WOF_WOF_SD_L2_UE_OVER_THRES_ERROR = 16 ;
+static const uint8_t P9N2_C_CORE_WOF_WOF_SD_CI_UE_ERROR = 17 ;
+static const uint8_t P9N2_C_CORE_WOF_WOF_UNUSED_18 = 18 ;
+static const uint8_t P9N2_C_CORE_WOF_WOF_UNUSED_19 = 19 ;
+static const uint8_t P9N2_C_CORE_WOF_WOF_SD_SYS_XSTOP_ERROR = 20 ;
+static const uint8_t P9N2_C_CORE_WOF_WOF_UNUSED_21 = 21 ;
+static const uint8_t P9N2_C_CORE_WOF_WOF_UNUSED_22 = 22 ;
+static const uint8_t P9N2_C_CORE_WOF_WOF_UNUSED_23 = 23 ;
+static const uint8_t P9N2_C_CORE_WOF_WOF_VS_LOG_REC_ERROR = 24 ;
+static const uint8_t P9N2_C_CORE_WOF_WOF_VS_LOG_XSTOP_ERROR = 25 ;
+static const uint8_t P9N2_C_CORE_WOF_WOF_PC_RECOV_IN_MAINT_ERROR = 26 ;
+static const uint8_t P9N2_C_CORE_WOF_WOF_VS_DU_LOG_REC_ERROR = 27 ;
+static const uint8_t P9N2_C_CORE_WOF_WOF_PC_SYS_XSTOP_ERROR = 28 ;
+static const uint8_t P9N2_C_CORE_WOF_WOF_LS_SRAM_PARITY_ERROR = 29 ;
+static const uint8_t P9N2_C_CORE_WOF_WOF_LS_SETDELETE_ERROR = 30 ;
+static const uint8_t P9N2_C_CORE_WOF_WOF_LS_RFILE_REC_ERROR = 31 ;
+static const uint8_t P9N2_C_CORE_WOF_WOF_LS_RFILE_XSTOP_ERROR = 32 ;
+static const uint8_t P9N2_C_CORE_WOF_WOF_LS_TLB_MULTIHIT_ERROR = 33 ;
+static const uint8_t P9N2_C_CORE_WOF_WOF_LS_SLB_MULTIHIT_ERROR = 34 ;
+static const uint8_t P9N2_C_CORE_WOF_WOF_LS_DERAT_MULTIHIT_ERROR = 35 ;
+static const uint8_t P9N2_C_CORE_WOF_WOF_PC_FWD_PROGRESS_ERROR = 36 ;
+static const uint8_t P9N2_C_CORE_WOF_WOF_LS_LOG_REC_ERROR = 37 ;
+static const uint8_t P9N2_C_CORE_WOF_WOF_LS_LOG_XSTOP_ERROR = 38 ;
+static const uint8_t P9N2_C_CORE_WOF_WOF_UNUSED_39 = 39 ;
+static const uint8_t P9N2_C_CORE_WOF_WOF_UNUSED_40 = 40 ;
+static const uint8_t P9N2_C_CORE_WOF_WOF_LS_SYS_XSTOP_ERROR = 41 ;
+static const uint8_t P9N2_C_CORE_WOF_WOF_UNUSED_42 = 42 ;
+static const uint8_t P9N2_C_CORE_WOF_WOF_PC_THREAD_HANG_REC_ERROR = 43 ;
+static const uint8_t P9N2_C_CORE_WOF_WOF_UNUSED_44 = 44 ;
+static const uint8_t P9N2_C_CORE_WOF_WOF_PC_LOG_XSTOP_ERROR = 45 ;
+static const uint8_t P9N2_C_CORE_WOF_WOF_UNUSED_46 = 46 ;
+static const uint8_t P9N2_C_CORE_WOF_WOF_PC_TFAC_XSTOP_ERROR = 47 ;
+static const uint8_t P9N2_C_CORE_WOF_WOF_PC_HYP_RES_ERROR = 48 ;
+static const uint8_t P9N2_C_CORE_WOF_WOF_UNUSED_49 = 49 ;
+static const uint8_t P9N2_C_CORE_WOF_WOF_UNUSED_50 = 50 ;
+static const uint8_t P9N2_C_CORE_WOF_WOF_UNUSED_51 = 51 ;
+static const uint8_t P9N2_C_CORE_WOF_WOF_PC_HANG_RECOVERY_FAILED = 52 ;
+static const uint8_t P9N2_C_CORE_WOF_WOF_PC_CORE_HANG_DETECT_ERROR = 53 ;
+static const uint8_t P9N2_C_CORE_WOF_WOF_UNUSED_54 = 54 ;
+static const uint8_t P9N2_C_CORE_WOF_WOF_PC_NEST_HANG_DETECT_ERROR = 55 ;
+static const uint8_t P9N2_C_CORE_WOF_WOF_PC_OTHER_CORE_CHIPLET_REC_ERROR = 56 ;
+static const uint8_t P9N2_C_CORE_WOF_WOF_PC_OTHER_CORE_CHIPLET_XSTOP_ERROR = 57 ;
+static const uint8_t P9N2_C_CORE_WOF_WOF_PC_OTHER_CORE_CHIPLET_SYS_XSTOP_ERROR = 58 ;
+static const uint8_t P9N2_C_CORE_WOF_WOF_PC_SCOM_ERROR = 59 ;
+static const uint8_t P9N2_C_CORE_WOF_WOF_PC_XSTOP_ON_DBG_TRIGGER_ERROR = 60 ;
+static const uint8_t P9N2_C_CORE_WOF_WOF_PC_FW_INJ_REC_ERROR = 61 ;
+static const uint8_t P9N2_C_CORE_WOF_WOF_PC_FW_INJ_XSTOP_ERROR = 62 ;
+static const uint8_t P9N2_C_CORE_WOF_WOF_PC_PHYP_XSTOP_ERROR = 63 ;
+
+static const uint8_t P9N2_EQ_CPLT_CONF0_CTRL_MISC_PROBE0_SEL_DC = 0 ;
+static const uint8_t P9N2_EQ_CPLT_CONF0_CTRL_MISC_PROBE0_SEL_DC_LEN = 6 ;
+static const uint8_t P9N2_EQ_CPLT_CONF0_RESERVED_6C = 6 ;
+static const uint8_t P9N2_EQ_CPLT_CONF0_RESERVED_7C = 7 ;
+static const uint8_t P9N2_EQ_CPLT_CONF0_CTRL_MISC_PROBE1_SEL_DC = 8 ;
+static const uint8_t P9N2_EQ_CPLT_CONF0_CTRL_MISC_PROBE1_SEL_DC_LEN = 6 ;
+static const uint8_t P9N2_EQ_CPLT_CONF0_RESERVED_14C = 14 ;
+static const uint8_t P9N2_EQ_CPLT_CONF0_RESERVED_15C = 15 ;
+static const uint8_t P9N2_EQ_CPLT_CONF0_CTRL_MISC_PROBE2_SEL_DC = 16 ;
+static const uint8_t P9N2_EQ_CPLT_CONF0_CTRL_MISC_PROBE2_SEL_DC_LEN = 6 ;
+static const uint8_t P9N2_EQ_CPLT_CONF0_RESERVED_22C = 22 ;
+static const uint8_t P9N2_EQ_CPLT_CONF0_RESERVED_23C = 23 ;
+static const uint8_t P9N2_EQ_CPLT_CONF0_CTRL_MISC_PROBE3_SEL_DC = 24 ;
+static const uint8_t P9N2_EQ_CPLT_CONF0_CTRL_MISC_PROBE3_SEL_DC_LEN = 6 ;
+static const uint8_t P9N2_EQ_CPLT_CONF0_RESERVED_30C = 30 ;
+static const uint8_t P9N2_EQ_CPLT_CONF0_RESERVED_31C = 31 ;
+static const uint8_t P9N2_EQ_CPLT_CONF0_CTRL_CC_OFLOW_FEH_SEL_DC = 32 ;
+static const uint8_t P9N2_EQ_CPLT_CONF0_CTRL_CC_SCAN_PROTECT_DC = 33 ;
+static const uint8_t P9N2_EQ_CPLT_CONF0_CTRL_CC_SDIS_DC_N = 34 ;
+static const uint8_t P9N2_EQ_CPLT_CONF0_CTRL_CC_SCAN_DIAG = 35 ;
+static const uint8_t P9N2_EQ_CPLT_CONF0_RESERVED_TEST_CONTROL_36C = 36 ;
+static const uint8_t P9N2_EQ_CPLT_CONF0_RESERVED_TEST_CONTROL_37C = 37 ;
+static const uint8_t P9N2_EQ_CPLT_CONF0_RESERVED_TEST_CONTROL_38C = 38 ;
+static const uint8_t P9N2_EQ_CPLT_CONF0_RESERVED_TEST_CONTROL_39C = 39 ;
+static const uint8_t P9N2_EQ_CPLT_CONF0_CTRL_EPS_MASK_VITL_PCB_ERR_DC = 40 ;
+static const uint8_t P9N2_EQ_CPLT_CONF0_CTRL_CC_MASK_VITL_SCAN_OPCG_ERR_DC = 41 ;
+static const uint8_t P9N2_EQ_CPLT_CONF0_RESERVED_42C = 42 ;
+static const uint8_t P9N2_EQ_CPLT_CONF0_RESERVED_43C = 43 ;
+static const uint8_t P9N2_EQ_CPLT_CONF0_TC_PCB_DBG_GLB_BRCST_EN = 44 ;
+static const uint8_t P9N2_EQ_CPLT_CONF0_FREE_USAGE_45C = 45 ;
+static const uint8_t P9N2_EQ_CPLT_CONF0_FREE_USAGE_46C = 46 ;
+static const uint8_t P9N2_EQ_CPLT_CONF0_FREE_USAGE_47C = 47 ;
+static const uint8_t P9N2_EQ_CPLT_CONF0_TC_UNIT_GROUP_ID_DC = 48 ;
+static const uint8_t P9N2_EQ_CPLT_CONF0_TC_UNIT_GROUP_ID_DC_LEN = 4 ;
+static const uint8_t P9N2_EQ_CPLT_CONF0_TC_UNIT_CHIP_ID_DC = 52 ;
+static const uint8_t P9N2_EQ_CPLT_CONF0_TC_UNIT_CHIP_ID_DC_LEN = 3 ;
+static const uint8_t P9N2_EQ_CPLT_CONF0_RESERVED_ID_55C = 55 ;
+static const uint8_t P9N2_EQ_CPLT_CONF0_TC_UNIT_SYS_ID_DC = 56 ;
+static const uint8_t P9N2_EQ_CPLT_CONF0_TC_UNIT_SYS_ID_DC_LEN = 5 ;
+static const uint8_t P9N2_EQ_CPLT_CONF0_RESERVED_ID_61C = 61 ;
+static const uint8_t P9N2_EQ_CPLT_CONF0_RESERVED_ID_62C = 62 ;
+static const uint8_t P9N2_EQ_CPLT_CONF0_RESERVED_ID_63C = 63 ;
+
+static const uint8_t P9N2_EX_CPLT_CONF0_CTRL_MISC_PROBE0_SEL_DC = 0 ;
+static const uint8_t P9N2_EX_CPLT_CONF0_CTRL_MISC_PROBE0_SEL_DC_LEN = 6 ;
+static const uint8_t P9N2_EX_CPLT_CONF0_RESERVED_6C = 6 ;
+static const uint8_t P9N2_EX_CPLT_CONF0_RESERVED_7C = 7 ;
+static const uint8_t P9N2_EX_CPLT_CONF0_CTRL_MISC_PROBE1_SEL_DC = 8 ;
+static const uint8_t P9N2_EX_CPLT_CONF0_CTRL_MISC_PROBE1_SEL_DC_LEN = 6 ;
+static const uint8_t P9N2_EX_CPLT_CONF0_RESERVED_14C = 14 ;
+static const uint8_t P9N2_EX_CPLT_CONF0_RESERVED_15C = 15 ;
+static const uint8_t P9N2_EX_CPLT_CONF0_CTRL_MISC_PROBE2_SEL_DC = 16 ;
+static const uint8_t P9N2_EX_CPLT_CONF0_CTRL_MISC_PROBE2_SEL_DC_LEN = 6 ;
+static const uint8_t P9N2_EX_CPLT_CONF0_RESERVED_22C = 22 ;
+static const uint8_t P9N2_EX_CPLT_CONF0_RESERVED_23C = 23 ;
+static const uint8_t P9N2_EX_CPLT_CONF0_CTRL_MISC_PROBE3_SEL_DC = 24 ;
+static const uint8_t P9N2_EX_CPLT_CONF0_CTRL_MISC_PROBE3_SEL_DC_LEN = 6 ;
+static const uint8_t P9N2_EX_CPLT_CONF0_RESERVED_30C = 30 ;
+static const uint8_t P9N2_EX_CPLT_CONF0_RESERVED_31C = 31 ;
+static const uint8_t P9N2_EX_CPLT_CONF0_CTRL_CC_OFLOW_FEH_SEL_DC = 32 ;
+static const uint8_t P9N2_EX_CPLT_CONF0_CTRL_CC_SCAN_PROTECT_DC = 33 ;
+static const uint8_t P9N2_EX_CPLT_CONF0_CTRL_CC_SDIS_DC_N = 34 ;
+static const uint8_t P9N2_EX_CPLT_CONF0_CTRL_CC_SCAN_DIAG = 35 ;
+static const uint8_t P9N2_EX_CPLT_CONF0_RESERVED_TEST_CONTROL_36C = 36 ;
+static const uint8_t P9N2_EX_CPLT_CONF0_RESERVED_TEST_CONTROL_37C = 37 ;
+static const uint8_t P9N2_EX_CPLT_CONF0_RESERVED_TEST_CONTROL_38C = 38 ;
+static const uint8_t P9N2_EX_CPLT_CONF0_RESERVED_TEST_CONTROL_39C = 39 ;
+static const uint8_t P9N2_EX_CPLT_CONF0_CTRL_EPS_MASK_VITL_PCB_ERR_DC = 40 ;
+static const uint8_t P9N2_EX_CPLT_CONF0_CTRL_CC_MASK_VITL_SCAN_OPCG_ERR_DC = 41 ;
+static const uint8_t P9N2_EX_CPLT_CONF0_RESERVED_42C = 42 ;
+static const uint8_t P9N2_EX_CPLT_CONF0_RESERVED_43C = 43 ;
+static const uint8_t P9N2_EX_CPLT_CONF0_TC_PCB_DBG_GLB_BRCST_EN = 44 ;
+static const uint8_t P9N2_EX_CPLT_CONF0_FREE_USAGE_45C = 45 ;
+static const uint8_t P9N2_EX_CPLT_CONF0_FREE_USAGE_46C = 46 ;
+static const uint8_t P9N2_EX_CPLT_CONF0_FREE_USAGE_47C = 47 ;
+static const uint8_t P9N2_EX_CPLT_CONF0_TC_UNIT_GROUP_ID_DC = 48 ;
+static const uint8_t P9N2_EX_CPLT_CONF0_TC_UNIT_GROUP_ID_DC_LEN = 4 ;
+static const uint8_t P9N2_EX_CPLT_CONF0_TC_UNIT_CHIP_ID_DC = 52 ;
+static const uint8_t P9N2_EX_CPLT_CONF0_TC_UNIT_CHIP_ID_DC_LEN = 3 ;
+static const uint8_t P9N2_EX_CPLT_CONF0_RESERVED_ID_55C = 55 ;
+static const uint8_t P9N2_EX_CPLT_CONF0_UNUSED_56C = 56 ;
+static const uint8_t P9N2_EX_CPLT_CONF0_UNUSED_57C = 57 ;
+static const uint8_t P9N2_EX_CPLT_CONF0_UNUSED_58C = 58 ;
+static const uint8_t P9N2_EX_CPLT_CONF0_UNUSED_59C = 59 ;
+static const uint8_t P9N2_EX_CPLT_CONF0_UNUSED_60C = 60 ;
+static const uint8_t P9N2_EX_CPLT_CONF0_RESERVED_ID_61C = 61 ;
+static const uint8_t P9N2_EX_CPLT_CONF0_RESERVED_ID_62C = 62 ;
+static const uint8_t P9N2_EX_CPLT_CONF0_RESERVED_ID_63C = 63 ;
+
+static const uint8_t P9N2_C_CPLT_CONF0_CTRL_MISC_PROBE0_SEL_DC = 0 ;
+static const uint8_t P9N2_C_CPLT_CONF0_CTRL_MISC_PROBE0_SEL_DC_LEN = 6 ;
+static const uint8_t P9N2_C_CPLT_CONF0_RESERVED_6C = 6 ;
+static const uint8_t P9N2_C_CPLT_CONF0_RESERVED_7C = 7 ;
+static const uint8_t P9N2_C_CPLT_CONF0_CTRL_MISC_PROBE1_SEL_DC = 8 ;
+static const uint8_t P9N2_C_CPLT_CONF0_CTRL_MISC_PROBE1_SEL_DC_LEN = 6 ;
+static const uint8_t P9N2_C_CPLT_CONF0_RESERVED_14C = 14 ;
+static const uint8_t P9N2_C_CPLT_CONF0_RESERVED_15C = 15 ;
+static const uint8_t P9N2_C_CPLT_CONF0_CTRL_MISC_PROBE2_SEL_DC = 16 ;
+static const uint8_t P9N2_C_CPLT_CONF0_CTRL_MISC_PROBE2_SEL_DC_LEN = 6 ;
+static const uint8_t P9N2_C_CPLT_CONF0_RESERVED_22C = 22 ;
+static const uint8_t P9N2_C_CPLT_CONF0_RESERVED_23C = 23 ;
+static const uint8_t P9N2_C_CPLT_CONF0_CTRL_MISC_PROBE3_SEL_DC = 24 ;
+static const uint8_t P9N2_C_CPLT_CONF0_CTRL_MISC_PROBE3_SEL_DC_LEN = 6 ;
+static const uint8_t P9N2_C_CPLT_CONF0_RESERVED_30C = 30 ;
+static const uint8_t P9N2_C_CPLT_CONF0_RESERVED_31C = 31 ;
+static const uint8_t P9N2_C_CPLT_CONF0_CTRL_CC_OFLOW_FEH_SEL_DC = 32 ;
+static const uint8_t P9N2_C_CPLT_CONF0_CTRL_CC_SCAN_PROTECT_DC = 33 ;
+static const uint8_t P9N2_C_CPLT_CONF0_CTRL_CC_SDIS_DC_N = 34 ;
+static const uint8_t P9N2_C_CPLT_CONF0_CTRL_CC_SCAN_DIAG = 35 ;
+static const uint8_t P9N2_C_CPLT_CONF0_RESERVED_TEST_CONTROL_36C = 36 ;
+static const uint8_t P9N2_C_CPLT_CONF0_RESERVED_TEST_CONTROL_37C = 37 ;
+static const uint8_t P9N2_C_CPLT_CONF0_RESERVED_TEST_CONTROL_38C = 38 ;
+static const uint8_t P9N2_C_CPLT_CONF0_RESERVED_TEST_CONTROL_39C = 39 ;
+static const uint8_t P9N2_C_CPLT_CONF0_CTRL_EPS_MASK_VITL_PCB_ERR_DC = 40 ;
+static const uint8_t P9N2_C_CPLT_CONF0_CTRL_CC_MASK_VITL_SCAN_OPCG_ERR_DC = 41 ;
+static const uint8_t P9N2_C_CPLT_CONF0_RESERVED_42C = 42 ;
+static const uint8_t P9N2_C_CPLT_CONF0_RESERVED_43C = 43 ;
+static const uint8_t P9N2_C_CPLT_CONF0_TC_PCB_DBG_GLB_BRCST_EN = 44 ;
+static const uint8_t P9N2_C_CPLT_CONF0_FREE_USAGE_45C = 45 ;
+static const uint8_t P9N2_C_CPLT_CONF0_FREE_USAGE_46C = 46 ;
+static const uint8_t P9N2_C_CPLT_CONF0_FREE_USAGE_47C = 47 ;
+static const uint8_t P9N2_C_CPLT_CONF0_TC_UNIT_GROUP_ID_DC = 48 ;
+static const uint8_t P9N2_C_CPLT_CONF0_TC_UNIT_GROUP_ID_DC_LEN = 4 ;
+static const uint8_t P9N2_C_CPLT_CONF0_TC_UNIT_CHIP_ID_DC = 52 ;
+static const uint8_t P9N2_C_CPLT_CONF0_TC_UNIT_CHIP_ID_DC_LEN = 3 ;
+static const uint8_t P9N2_C_CPLT_CONF0_RESERVED_ID_55C = 55 ;
+static const uint8_t P9N2_C_CPLT_CONF0_UNUSED_56C = 56 ;
+static const uint8_t P9N2_C_CPLT_CONF0_UNUSED_57C = 57 ;
+static const uint8_t P9N2_C_CPLT_CONF0_UNUSED_58C = 58 ;
+static const uint8_t P9N2_C_CPLT_CONF0_UNUSED_59C = 59 ;
+static const uint8_t P9N2_C_CPLT_CONF0_UNUSED_60C = 60 ;
+static const uint8_t P9N2_C_CPLT_CONF0_RESERVED_ID_61C = 61 ;
+static const uint8_t P9N2_C_CPLT_CONF0_RESERVED_ID_62C = 62 ;
+static const uint8_t P9N2_C_CPLT_CONF0_RESERVED_ID_63C = 63 ;
+
+static const uint8_t P9N2_EQ_CPLT_CONF1_TCEP_AMUX_VSELECT_EQ = 0 ;
+static const uint8_t P9N2_EQ_CPLT_CONF1_TCEP_AMUX_VSELECT_EQ_LEN = 3 ;
+static const uint8_t P9N2_EQ_CPLT_CONF1_TCEP_AMUX_VSELECT_PWR_UP = 3 ;
+static const uint8_t P9N2_EQ_CPLT_CONF1_TCEP_AMUX_VSELECT_PWR_UP_LEN = 2 ;
+static const uint8_t P9N2_EQ_CPLT_CONF1_TCEP_AMUX_VSELECT_PWR_DN = 5 ;
+static const uint8_t P9N2_EQ_CPLT_CONF1_TCEP_AMUX_VSELECT_PWR_DN_LEN = 2 ;
+static const uint8_t P9N2_EQ_CPLT_CONF1_TCEP_AMUX_VSELECT_L3_UP = 7 ;
+static const uint8_t P9N2_EQ_CPLT_CONF1_TCEP_AMUX_VSELECT_L3_UP_LEN = 3 ;
+static const uint8_t P9N2_EQ_CPLT_CONF1_TCEP_AMUX_VSELECT_L3_DN = 10 ;
+static const uint8_t P9N2_EQ_CPLT_CONF1_TCEP_AMUX_VSELECT_L3_DN_LEN = 3 ;
+static const uint8_t P9N2_EQ_CPLT_CONF1_UNUSED_13D = 13 ;
+static const uint8_t P9N2_EQ_CPLT_CONF1_UNUSED_14D = 14 ;
+static const uint8_t P9N2_EQ_CPLT_CONF1_UNUSED_15D = 15 ;
+static const uint8_t P9N2_EQ_CPLT_CONF1_UNUSED_16D = 16 ;
+static const uint8_t P9N2_EQ_CPLT_CONF1_UNUSED_17D = 17 ;
+static const uint8_t P9N2_EQ_CPLT_CONF1_UNUSED_18D = 18 ;
+static const uint8_t P9N2_EQ_CPLT_CONF1_UNUSED_19D = 19 ;
+static const uint8_t P9N2_EQ_CPLT_CONF1_UNUSED_20D = 20 ;
+static const uint8_t P9N2_EQ_CPLT_CONF1_UNUSED_21D = 21 ;
+static const uint8_t P9N2_EQ_CPLT_CONF1_UNUSED_22D = 22 ;
+static const uint8_t P9N2_EQ_CPLT_CONF1_UNUSED_23D = 23 ;
+static const uint8_t P9N2_EQ_CPLT_CONF1_UNUSED_24D = 24 ;
+static const uint8_t P9N2_EQ_CPLT_CONF1_UNUSED_25D = 25 ;
+static const uint8_t P9N2_EQ_CPLT_CONF1_UNUSED_26D = 26 ;
+static const uint8_t P9N2_EQ_CPLT_CONF1_UNUSED_27D = 27 ;
+static const uint8_t P9N2_EQ_CPLT_CONF1_UNUSED_28D = 28 ;
+static const uint8_t P9N2_EQ_CPLT_CONF1_UNUSED_29D = 29 ;
+static const uint8_t P9N2_EQ_CPLT_CONF1_UNUSED_30D = 30 ;
+static const uint8_t P9N2_EQ_CPLT_CONF1_UNUSED_31D = 31 ;
+
+static const uint8_t P9N2_EX_CPLT_CONF1_UNUSED_0D = 0 ;
+static const uint8_t P9N2_EX_CPLT_CONF1_UNUSED_1D = 1 ;
+static const uint8_t P9N2_EX_CPLT_CONF1_UNUSED_2D = 2 ;
+static const uint8_t P9N2_EX_CPLT_CONF1_UNUSED_3D = 3 ;
+static const uint8_t P9N2_EX_CPLT_CONF1_UNUSED_4D = 4 ;
+static const uint8_t P9N2_EX_CPLT_CONF1_UNUSED_5D = 5 ;
+static const uint8_t P9N2_EX_CPLT_CONF1_UNUSED_6D = 6 ;
+static const uint8_t P9N2_EX_CPLT_CONF1_UNUSED_7D = 7 ;
+static const uint8_t P9N2_EX_CPLT_CONF1_UNUSED_8D = 8 ;
+static const uint8_t P9N2_EX_CPLT_CONF1_UNUSED_9D = 9 ;
+static const uint8_t P9N2_EX_CPLT_CONF1_UNUSED_10D = 10 ;
+static const uint8_t P9N2_EX_CPLT_CONF1_UNUSED_11D = 11 ;
+static const uint8_t P9N2_EX_CPLT_CONF1_UNUSED_12D = 12 ;
+static const uint8_t P9N2_EX_CPLT_CONF1_UNUSED_13D = 13 ;
+static const uint8_t P9N2_EX_CPLT_CONF1_UNUSED_14D = 14 ;
+static const uint8_t P9N2_EX_CPLT_CONF1_UNUSED_15D = 15 ;
+static const uint8_t P9N2_EX_CPLT_CONF1_UNUSED_16D = 16 ;
+static const uint8_t P9N2_EX_CPLT_CONF1_UNUSED_17D = 17 ;
+static const uint8_t P9N2_EX_CPLT_CONF1_UNUSED_18D = 18 ;
+static const uint8_t P9N2_EX_CPLT_CONF1_UNUSED_19D = 19 ;
+static const uint8_t P9N2_EX_CPLT_CONF1_UNUSED_20D = 20 ;
+static const uint8_t P9N2_EX_CPLT_CONF1_UNUSED_21D = 21 ;
+static const uint8_t P9N2_EX_CPLT_CONF1_UNUSED_22D = 22 ;
+static const uint8_t P9N2_EX_CPLT_CONF1_UNUSED_23D = 23 ;
+static const uint8_t P9N2_EX_CPLT_CONF1_UNUSED_24D = 24 ;
+static const uint8_t P9N2_EX_CPLT_CONF1_UNUSED_25D = 25 ;
+static const uint8_t P9N2_EX_CPLT_CONF1_UNUSED_26D = 26 ;
+static const uint8_t P9N2_EX_CPLT_CONF1_UNUSED_27D = 27 ;
+static const uint8_t P9N2_EX_CPLT_CONF1_UNUSED_28D = 28 ;
+static const uint8_t P9N2_EX_CPLT_CONF1_UNUSED_29D = 29 ;
+static const uint8_t P9N2_EX_CPLT_CONF1_UNUSED_30D = 30 ;
+static const uint8_t P9N2_EX_CPLT_CONF1_UNUSED_31D = 31 ;
+
+static const uint8_t P9N2_C_CPLT_CONF1_UNUSED_0D = 0 ;
+static const uint8_t P9N2_C_CPLT_CONF1_UNUSED_1D = 1 ;
+static const uint8_t P9N2_C_CPLT_CONF1_UNUSED_2D = 2 ;
+static const uint8_t P9N2_C_CPLT_CONF1_UNUSED_3D = 3 ;
+static const uint8_t P9N2_C_CPLT_CONF1_UNUSED_4D = 4 ;
+static const uint8_t P9N2_C_CPLT_CONF1_UNUSED_5D = 5 ;
+static const uint8_t P9N2_C_CPLT_CONF1_UNUSED_6D = 6 ;
+static const uint8_t P9N2_C_CPLT_CONF1_UNUSED_7D = 7 ;
+static const uint8_t P9N2_C_CPLT_CONF1_UNUSED_8D = 8 ;
+static const uint8_t P9N2_C_CPLT_CONF1_UNUSED_9D = 9 ;
+static const uint8_t P9N2_C_CPLT_CONF1_UNUSED_10D = 10 ;
+static const uint8_t P9N2_C_CPLT_CONF1_UNUSED_11D = 11 ;
+static const uint8_t P9N2_C_CPLT_CONF1_UNUSED_12D = 12 ;
+static const uint8_t P9N2_C_CPLT_CONF1_UNUSED_13D = 13 ;
+static const uint8_t P9N2_C_CPLT_CONF1_UNUSED_14D = 14 ;
+static const uint8_t P9N2_C_CPLT_CONF1_UNUSED_15D = 15 ;
+static const uint8_t P9N2_C_CPLT_CONF1_UNUSED_16D = 16 ;
+static const uint8_t P9N2_C_CPLT_CONF1_UNUSED_17D = 17 ;
+static const uint8_t P9N2_C_CPLT_CONF1_UNUSED_18D = 18 ;
+static const uint8_t P9N2_C_CPLT_CONF1_UNUSED_19D = 19 ;
+static const uint8_t P9N2_C_CPLT_CONF1_UNUSED_20D = 20 ;
+static const uint8_t P9N2_C_CPLT_CONF1_UNUSED_21D = 21 ;
+static const uint8_t P9N2_C_CPLT_CONF1_UNUSED_22D = 22 ;
+static const uint8_t P9N2_C_CPLT_CONF1_UNUSED_23D = 23 ;
+static const uint8_t P9N2_C_CPLT_CONF1_UNUSED_24D = 24 ;
+static const uint8_t P9N2_C_CPLT_CONF1_UNUSED_25D = 25 ;
+static const uint8_t P9N2_C_CPLT_CONF1_UNUSED_26D = 26 ;
+static const uint8_t P9N2_C_CPLT_CONF1_UNUSED_27D = 27 ;
+static const uint8_t P9N2_C_CPLT_CONF1_UNUSED_28D = 28 ;
+static const uint8_t P9N2_C_CPLT_CONF1_UNUSED_29D = 29 ;
+static const uint8_t P9N2_C_CPLT_CONF1_UNUSED_30D = 30 ;
+static const uint8_t P9N2_C_CPLT_CONF1_UNUSED_31D = 31 ;
+
+static const uint8_t P9N2_EQ_CPLT_CTRL0_CTRL_CC_ABSTCLK_MUXSEL_DC = 0 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL0_UNUSED_1A = 1 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL0_CTRL_CC_FLUSHMODE_INH_DC = 2 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL0_CTRL_CC_FORCE_ALIGN_DC = 3 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL0_TC_UNIT_ARY_WRT_THRU_DC = 4 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL0_TC_UNIT_AVP_MODE = 5 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL0_TC_BIT6_CHIPLET_ID_DC = 6 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL0_UNUSED_7A = 7 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL0_CTRL_CC_ABIST_RECOV_DISABLE_DC = 8 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL0_UNUSED_9A = 9 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL0_UNUSED_10A = 10 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL0_RESERVED_11A = 11 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL0_UNUSED_12A = 12 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL0_TC_UNIT_DETERMINISTIC_TEST_ENABLE_DC = 13 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL0_TC_UNIT_CONSTRAIN_SAFESCAN_DC = 14 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL0_UNUSED_15A = 15 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL0_UNUSED_16A = 16 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL0_UNUSED_17A = 17 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL0_RESERVED_18A = 18 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL0_RESERVED_19A = 19 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL0_UNUSED_20A = 20 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL0_UNUSED_21A = 21 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL0_UNUSED_22A = 22 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL0_UNUSED_23A = 23 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL0_UNUSED_24A = 24 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL0_UNUSED_25A = 25 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL0_UNUSED_26A = 26 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL0_UNUSED_27A = 27 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL0_UNUSED_28A = 28 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL0_UNUSED_29A = 29 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL0_UNUSED_30A = 30 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL0_UNUSED_31A = 31 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL0_UNUSED_32A = 32 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL0_RESERVED_33A = 33 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL0_RESERVED_34A = 34 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL0_RESERVED_35A = 35 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL0_TC_OELCC_EDGE_DELAYED_DC = 36 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL0_TC_OELCC_ALIGN_FLUSH_DC = 37 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL0_RESERVED_38A = 38 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL0_RESERVED_39A = 39 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL0_CTRL_MISC_CLKDIV_SEL_DC = 40 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL0_CTRL_MISC_CLKDIV_SEL_DC_LEN = 2 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL0_RESERVED_42A = 42 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL0_RESERVED_43A = 43 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL0_UNUSED_44A = 44 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL0_UNUSED_45A = 45 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL0_CTRL_CC_SSS_CALIBRATE_DC = 46 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL0_CTRL_CC_PIN_LBIST_DC = 47 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL0_FREE_USAGE_48A = 48 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL0_FREE_USAGE_49A = 49 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL0_FREE_USAGE_50A = 50 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL0_FREE_USAGE_51A = 51 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL0_FREE_USAGE_52A = 52 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL0_FREE_USAGE_53A = 53 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL0_FREE_USAGE_54A = 54 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL0_FREE_USAGE_55A = 55 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL0_FREE_USAGE_56A = 56 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL0_FREE_USAGE_57A = 57 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL0_FREE_USAGE_58A = 58 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL0_FREE_USAGE_59A = 59 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL0_FREE_USAGE_60A = 60 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL0_FREE_USAGE_61A = 61 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL0_FREE_USAGE_62A = 62 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL0_FREE_USAGE_63A = 63 ;
+
+static const uint8_t P9N2_EX_CPLT_CTRL0_UNUSED_0A = 0 ;
+static const uint8_t P9N2_EX_CPLT_CTRL0_UNUSED_1A = 1 ;
+static const uint8_t P9N2_EX_CPLT_CTRL0_CTRL_CC_FLUSHMODE_INH_DC = 2 ;
+static const uint8_t P9N2_EX_CPLT_CTRL0_CTRL_CC_FORCE_ALIGN_DC = 3 ;
+static const uint8_t P9N2_EX_CPLT_CTRL0_TC_UNIT_ARY_WRT_THRU_DC = 4 ;
+static const uint8_t P9N2_EX_CPLT_CTRL0_UNUSED_5A = 5 ;
+static const uint8_t P9N2_EX_CPLT_CTRL0_UNUSED_6A = 6 ;
+static const uint8_t P9N2_EX_CPLT_CTRL0_UNUSED_7A = 7 ;
+static const uint8_t P9N2_EX_CPLT_CTRL0_CTRL_CC_ABIST_RECOV_DISABLE_DC = 8 ;
+static const uint8_t P9N2_EX_CPLT_CTRL0_UNUSED_9A = 9 ;
+static const uint8_t P9N2_EX_CPLT_CTRL0_UNUSED_10A = 10 ;
+static const uint8_t P9N2_EX_CPLT_CTRL0_RESERVED_11A = 11 ;
+static const uint8_t P9N2_EX_CPLT_CTRL0_TC_SKIT_MODE_BIST_DC = 12 ;
+static const uint8_t P9N2_EX_CPLT_CTRL0_TC_UNIT_DETERMINISTIC_TEST_ENABLE_DC = 13 ;
+static const uint8_t P9N2_EX_CPLT_CTRL0_TC_UNIT_CONSTRAIN_SAFESCAN_DC = 14 ;
+static const uint8_t P9N2_EX_CPLT_CTRL0_TC_UNIT_RRFA_TEST_ENABLE_DC = 15 ;
+static const uint8_t P9N2_EX_CPLT_CTRL0_UNUSED_16A = 16 ;
+static const uint8_t P9N2_EX_CPLT_CTRL0_UNUSED_17A = 17 ;
+static const uint8_t P9N2_EX_CPLT_CTRL0_RESERVED_18A = 18 ;
+static const uint8_t P9N2_EX_CPLT_CTRL0_RESERVED_19A = 19 ;
+static const uint8_t P9N2_EX_CPLT_CTRL0_TC_PSRO_SEL_DC = 20 ;
+static const uint8_t P9N2_EX_CPLT_CTRL0_TC_PSRO_SEL_DC_LEN = 8 ;
+static const uint8_t P9N2_EX_CPLT_CTRL0_UNUSED_28A = 28 ;
+static const uint8_t P9N2_EX_CPLT_CTRL0_UNUSED_29A = 29 ;
+static const uint8_t P9N2_EX_CPLT_CTRL0_UNUSED_30A = 30 ;
+static const uint8_t P9N2_EX_CPLT_CTRL0_UNUSED_31A = 31 ;
+static const uint8_t P9N2_EX_CPLT_CTRL0_UNUSED_32A = 32 ;
+static const uint8_t P9N2_EX_CPLT_CTRL0_RESERVED_33A = 33 ;
+static const uint8_t P9N2_EX_CPLT_CTRL0_RESERVED_34A = 34 ;
+static const uint8_t P9N2_EX_CPLT_CTRL0_RESERVED_35A = 35 ;
+static const uint8_t P9N2_EX_CPLT_CTRL0_UNUSED_36A = 36 ;
+static const uint8_t P9N2_EX_CPLT_CTRL0_UNUSED_37A = 37 ;
+static const uint8_t P9N2_EX_CPLT_CTRL0_RESERVED_38A = 38 ;
+static const uint8_t P9N2_EX_CPLT_CTRL0_RESERVED_39A = 39 ;
+static const uint8_t P9N2_EX_CPLT_CTRL0_CTRL_MISC_CLKDIV_SEL_DC = 40 ;
+static const uint8_t P9N2_EX_CPLT_CTRL0_CTRL_MISC_CLKDIV_SEL_DC_LEN = 2 ;
+static const uint8_t P9N2_EX_CPLT_CTRL0_RESERVED_42A = 42 ;
+static const uint8_t P9N2_EX_CPLT_CTRL0_RESERVED_43A = 43 ;
+static const uint8_t P9N2_EX_CPLT_CTRL0_UNUSED_44A = 44 ;
+static const uint8_t P9N2_EX_CPLT_CTRL0_UNUSED_45A = 45 ;
+static const uint8_t P9N2_EX_CPLT_CTRL0_CTRL_CC_SSS_CALIBRATE_DC = 46 ;
+static const uint8_t P9N2_EX_CPLT_CTRL0_CTRL_CC_PIN_LBIST_DC = 47 ;
+static const uint8_t P9N2_EX_CPLT_CTRL0_FREE_USAGE_48A = 48 ;
+static const uint8_t P9N2_EX_CPLT_CTRL0_FREE_USAGE_49A = 49 ;
+static const uint8_t P9N2_EX_CPLT_CTRL0_FREE_USAGE_50A = 50 ;
+static const uint8_t P9N2_EX_CPLT_CTRL0_FREE_USAGE_51A = 51 ;
+static const uint8_t P9N2_EX_CPLT_CTRL0_FREE_USAGE_52A = 52 ;
+static const uint8_t P9N2_EX_CPLT_CTRL0_FREE_USAGE_53A = 53 ;
+static const uint8_t P9N2_EX_CPLT_CTRL0_FREE_USAGE_54A = 54 ;
+static const uint8_t P9N2_EX_CPLT_CTRL0_FREE_USAGE_55A = 55 ;
+static const uint8_t P9N2_EX_CPLT_CTRL0_FREE_USAGE_56A = 56 ;
+static const uint8_t P9N2_EX_CPLT_CTRL0_FREE_USAGE_57A = 57 ;
+static const uint8_t P9N2_EX_CPLT_CTRL0_FREE_USAGE_58A = 58 ;
+static const uint8_t P9N2_EX_CPLT_CTRL0_FREE_USAGE_59A = 59 ;
+static const uint8_t P9N2_EX_CPLT_CTRL0_FREE_USAGE_60A = 60 ;
+static const uint8_t P9N2_EX_CPLT_CTRL0_FREE_USAGE_61A = 61 ;
+static const uint8_t P9N2_EX_CPLT_CTRL0_FREE_USAGE_62A = 62 ;
+static const uint8_t P9N2_EX_CPLT_CTRL0_FREE_USAGE_63A = 63 ;
+
+static const uint8_t P9N2_C_CPLT_CTRL0_UNUSED_0A = 0 ;
+static const uint8_t P9N2_C_CPLT_CTRL0_UNUSED_1A = 1 ;
+static const uint8_t P9N2_C_CPLT_CTRL0_CTRL_CC_FLUSHMODE_INH_DC = 2 ;
+static const uint8_t P9N2_C_CPLT_CTRL0_CTRL_CC_FORCE_ALIGN_DC = 3 ;
+static const uint8_t P9N2_C_CPLT_CTRL0_TC_UNIT_ARY_WRT_THRU_DC = 4 ;
+static const uint8_t P9N2_C_CPLT_CTRL0_UNUSED_5A = 5 ;
+static const uint8_t P9N2_C_CPLT_CTRL0_UNUSED_6A = 6 ;
+static const uint8_t P9N2_C_CPLT_CTRL0_UNUSED_7A = 7 ;
+static const uint8_t P9N2_C_CPLT_CTRL0_CTRL_CC_ABIST_RECOV_DISABLE_DC = 8 ;
+static const uint8_t P9N2_C_CPLT_CTRL0_UNUSED_9A = 9 ;
+static const uint8_t P9N2_C_CPLT_CTRL0_UNUSED_10A = 10 ;
+static const uint8_t P9N2_C_CPLT_CTRL0_RESERVED_11A = 11 ;
+static const uint8_t P9N2_C_CPLT_CTRL0_TC_SKIT_MODE_BIST_DC = 12 ;
+static const uint8_t P9N2_C_CPLT_CTRL0_TC_UNIT_DETERMINISTIC_TEST_ENABLE_DC = 13 ;
+static const uint8_t P9N2_C_CPLT_CTRL0_TC_UNIT_CONSTRAIN_SAFESCAN_DC = 14 ;
+static const uint8_t P9N2_C_CPLT_CTRL0_TC_UNIT_RRFA_TEST_ENABLE_DC = 15 ;
+static const uint8_t P9N2_C_CPLT_CTRL0_UNUSED_16A = 16 ;
+static const uint8_t P9N2_C_CPLT_CTRL0_UNUSED_17A = 17 ;
+static const uint8_t P9N2_C_CPLT_CTRL0_RESERVED_18A = 18 ;
+static const uint8_t P9N2_C_CPLT_CTRL0_RESERVED_19A = 19 ;
+static const uint8_t P9N2_C_CPLT_CTRL0_TC_PSRO_SEL_DC = 20 ;
+static const uint8_t P9N2_C_CPLT_CTRL0_TC_PSRO_SEL_DC_LEN = 8 ;
+static const uint8_t P9N2_C_CPLT_CTRL0_UNUSED_28A = 28 ;
+static const uint8_t P9N2_C_CPLT_CTRL0_UNUSED_29A = 29 ;
+static const uint8_t P9N2_C_CPLT_CTRL0_UNUSED_30A = 30 ;
+static const uint8_t P9N2_C_CPLT_CTRL0_UNUSED_31A = 31 ;
+static const uint8_t P9N2_C_CPLT_CTRL0_UNUSED_32A = 32 ;
+static const uint8_t P9N2_C_CPLT_CTRL0_RESERVED_33A = 33 ;
+static const uint8_t P9N2_C_CPLT_CTRL0_RESERVED_34A = 34 ;
+static const uint8_t P9N2_C_CPLT_CTRL0_RESERVED_35A = 35 ;
+static const uint8_t P9N2_C_CPLT_CTRL0_UNUSED_36A = 36 ;
+static const uint8_t P9N2_C_CPLT_CTRL0_UNUSED_37A = 37 ;
+static const uint8_t P9N2_C_CPLT_CTRL0_RESERVED_38A = 38 ;
+static const uint8_t P9N2_C_CPLT_CTRL0_RESERVED_39A = 39 ;
+static const uint8_t P9N2_C_CPLT_CTRL0_CTRL_MISC_CLKDIV_SEL_DC = 40 ;
+static const uint8_t P9N2_C_CPLT_CTRL0_CTRL_MISC_CLKDIV_SEL_DC_LEN = 2 ;
+static const uint8_t P9N2_C_CPLT_CTRL0_RESERVED_42A = 42 ;
+static const uint8_t P9N2_C_CPLT_CTRL0_RESERVED_43A = 43 ;
+static const uint8_t P9N2_C_CPLT_CTRL0_UNUSED_44A = 44 ;
+static const uint8_t P9N2_C_CPLT_CTRL0_UNUSED_45A = 45 ;
+static const uint8_t P9N2_C_CPLT_CTRL0_CTRL_CC_SSS_CALIBRATE_DC = 46 ;
+static const uint8_t P9N2_C_CPLT_CTRL0_CTRL_CC_PIN_LBIST_DC = 47 ;
+static const uint8_t P9N2_C_CPLT_CTRL0_FREE_USAGE_48A = 48 ;
+static const uint8_t P9N2_C_CPLT_CTRL0_FREE_USAGE_49A = 49 ;
+static const uint8_t P9N2_C_CPLT_CTRL0_FREE_USAGE_50A = 50 ;
+static const uint8_t P9N2_C_CPLT_CTRL0_FREE_USAGE_51A = 51 ;
+static const uint8_t P9N2_C_CPLT_CTRL0_FREE_USAGE_52A = 52 ;
+static const uint8_t P9N2_C_CPLT_CTRL0_FREE_USAGE_53A = 53 ;
+static const uint8_t P9N2_C_CPLT_CTRL0_FREE_USAGE_54A = 54 ;
+static const uint8_t P9N2_C_CPLT_CTRL0_FREE_USAGE_55A = 55 ;
+static const uint8_t P9N2_C_CPLT_CTRL0_FREE_USAGE_56A = 56 ;
+static const uint8_t P9N2_C_CPLT_CTRL0_FREE_USAGE_57A = 57 ;
+static const uint8_t P9N2_C_CPLT_CTRL0_FREE_USAGE_58A = 58 ;
+static const uint8_t P9N2_C_CPLT_CTRL0_FREE_USAGE_59A = 59 ;
+static const uint8_t P9N2_C_CPLT_CTRL0_FREE_USAGE_60A = 60 ;
+static const uint8_t P9N2_C_CPLT_CTRL0_FREE_USAGE_61A = 61 ;
+static const uint8_t P9N2_C_CPLT_CTRL0_FREE_USAGE_62A = 62 ;
+static const uint8_t P9N2_C_CPLT_CTRL0_FREE_USAGE_63A = 63 ;
+
+static const uint8_t P9N2_EQ_CPLT_CTRL1_UNUSED_0B = 0 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL1_UNUSED_1B = 1 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL1_UNUSED_2B = 2 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL1_TC_VITL_REGION_FENCE = 3 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL1_TC_PERV_REGION_FENCE = 4 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL1_TC_REGION1_FENCE = 5 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL1_TC_REGION2_FENCE = 6 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL1_TC_REGION3_FENCE = 7 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL1_TC_REGION4_FENCE = 8 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL1_TC_REGION5_FENCE = 9 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL1_TC_REGION6_FENCE = 10 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL1_TC_REGION7_FENCE = 11 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL1_TC_REGION8_FENCE = 12 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL1_TC_REGION9_FENCE = 13 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL1_TC_REGION10_FENCE = 14 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL1_RESERVED = 15 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL1_TC_UNIT_MULTICYCLE_TEST_FENCE = 16 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL1_UNUSED_17B = 17 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL1_UNUSED_18B = 18 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL1_UNUSED_19B = 19 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL1_UNUSED_20B = 20 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL1_UNUSED_21B = 21 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL1_UNUSED_22B = 22 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL1_UNUSED_23B = 23 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL1_UNUSED_24B = 24 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL1_UNUSED_25B = 25 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL1_UNUSED_26B = 26 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL1_UNUSED_27B = 27 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL1_UNUSED_28B = 28 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL1_UNUSED_29B = 29 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL1_UNUSED_30B = 30 ;
+static const uint8_t P9N2_EQ_CPLT_CTRL1_UNUSED_31B = 31 ;
+
+static const uint8_t P9N2_EX_CPLT_CTRL1_UNUSED_0B = 0 ;
+static const uint8_t P9N2_EX_CPLT_CTRL1_UNUSED_1B = 1 ;
+static const uint8_t P9N2_EX_CPLT_CTRL1_UNUSED_2B = 2 ;
+static const uint8_t P9N2_EX_CPLT_CTRL1_TC_VITL_REGION_FENCE = 3 ;
+static const uint8_t P9N2_EX_CPLT_CTRL1_TC_PERV_REGION_FENCE = 4 ;
+static const uint8_t P9N2_EX_CPLT_CTRL1_TC_REGION1_FENCE = 5 ;
+static const uint8_t P9N2_EX_CPLT_CTRL1_TC_REGION2_FENCE = 6 ;
+static const uint8_t P9N2_EX_CPLT_CTRL1_UNUSED_7B = 7 ;
+static const uint8_t P9N2_EX_CPLT_CTRL1_UNUSED_8B = 8 ;
+static const uint8_t P9N2_EX_CPLT_CTRL1_UNUSED_9B = 9 ;
+static const uint8_t P9N2_EX_CPLT_CTRL1_UNUSED_10B = 10 ;
+static const uint8_t P9N2_EX_CPLT_CTRL1_UNUSED_11B = 11 ;
+static const uint8_t P9N2_EX_CPLT_CTRL1_UNUSED_12B = 12 ;
+static const uint8_t P9N2_EX_CPLT_CTRL1_UNUSED_13B = 13 ;
+static const uint8_t P9N2_EX_CPLT_CTRL1_UNUSED_14B = 14 ;
+static const uint8_t P9N2_EX_CPLT_CTRL1_RESERVED = 15 ;
+static const uint8_t P9N2_EX_CPLT_CTRL1_TC_UNIT_MULTICYCLE_TEST_FENCE = 16 ;
+static const uint8_t P9N2_EX_CPLT_CTRL1_UNUSED_17B = 17 ;
+static const uint8_t P9N2_EX_CPLT_CTRL1_UNUSED_18B = 18 ;
+static const uint8_t P9N2_EX_CPLT_CTRL1_UNUSED_19B = 19 ;
+static const uint8_t P9N2_EX_CPLT_CTRL1_UNUSED_20B = 20 ;
+static const uint8_t P9N2_EX_CPLT_CTRL1_UNUSED_21B = 21 ;
+static const uint8_t P9N2_EX_CPLT_CTRL1_UNUSED_22B = 22 ;
+static const uint8_t P9N2_EX_CPLT_CTRL1_UNUSED_23B = 23 ;
+static const uint8_t P9N2_EX_CPLT_CTRL1_UNUSED_24B = 24 ;
+static const uint8_t P9N2_EX_CPLT_CTRL1_UNUSED_25B = 25 ;
+static const uint8_t P9N2_EX_CPLT_CTRL1_UNUSED_26B = 26 ;
+static const uint8_t P9N2_EX_CPLT_CTRL1_UNUSED_27B = 27 ;
+static const uint8_t P9N2_EX_CPLT_CTRL1_UNUSED_28B = 28 ;
+static const uint8_t P9N2_EX_CPLT_CTRL1_UNUSED_29B = 29 ;
+static const uint8_t P9N2_EX_CPLT_CTRL1_UNUSED_30B = 30 ;
+static const uint8_t P9N2_EX_CPLT_CTRL1_UNUSED_31B = 31 ;
+
+static const uint8_t P9N2_C_CPLT_CTRL1_UNUSED_0B = 0 ;
+static const uint8_t P9N2_C_CPLT_CTRL1_UNUSED_1B = 1 ;
+static const uint8_t P9N2_C_CPLT_CTRL1_UNUSED_2B = 2 ;
+static const uint8_t P9N2_C_CPLT_CTRL1_TC_VITL_REGION_FENCE = 3 ;
+static const uint8_t P9N2_C_CPLT_CTRL1_TC_PERV_REGION_FENCE = 4 ;
+static const uint8_t P9N2_C_CPLT_CTRL1_TC_REGION1_FENCE = 5 ;
+static const uint8_t P9N2_C_CPLT_CTRL1_TC_REGION2_FENCE = 6 ;
+static const uint8_t P9N2_C_CPLT_CTRL1_UNUSED_7B = 7 ;
+static const uint8_t P9N2_C_CPLT_CTRL1_UNUSED_8B = 8 ;
+static const uint8_t P9N2_C_CPLT_CTRL1_UNUSED_9B = 9 ;
+static const uint8_t P9N2_C_CPLT_CTRL1_UNUSED_10B = 10 ;
+static const uint8_t P9N2_C_CPLT_CTRL1_UNUSED_11B = 11 ;
+static const uint8_t P9N2_C_CPLT_CTRL1_UNUSED_12B = 12 ;
+static const uint8_t P9N2_C_CPLT_CTRL1_UNUSED_13B = 13 ;
+static const uint8_t P9N2_C_CPLT_CTRL1_UNUSED_14B = 14 ;
+static const uint8_t P9N2_C_CPLT_CTRL1_RESERVED = 15 ;
+static const uint8_t P9N2_C_CPLT_CTRL1_TC_UNIT_MULTICYCLE_TEST_FENCE = 16 ;
+static const uint8_t P9N2_C_CPLT_CTRL1_UNUSED_17B = 17 ;
+static const uint8_t P9N2_C_CPLT_CTRL1_UNUSED_18B = 18 ;
+static const uint8_t P9N2_C_CPLT_CTRL1_UNUSED_19B = 19 ;
+static const uint8_t P9N2_C_CPLT_CTRL1_UNUSED_20B = 20 ;
+static const uint8_t P9N2_C_CPLT_CTRL1_UNUSED_21B = 21 ;
+static const uint8_t P9N2_C_CPLT_CTRL1_UNUSED_22B = 22 ;
+static const uint8_t P9N2_C_CPLT_CTRL1_UNUSED_23B = 23 ;
+static const uint8_t P9N2_C_CPLT_CTRL1_UNUSED_24B = 24 ;
+static const uint8_t P9N2_C_CPLT_CTRL1_UNUSED_25B = 25 ;
+static const uint8_t P9N2_C_CPLT_CTRL1_UNUSED_26B = 26 ;
+static const uint8_t P9N2_C_CPLT_CTRL1_UNUSED_27B = 27 ;
+static const uint8_t P9N2_C_CPLT_CTRL1_UNUSED_28B = 28 ;
+static const uint8_t P9N2_C_CPLT_CTRL1_UNUSED_29B = 29 ;
+static const uint8_t P9N2_C_CPLT_CTRL1_UNUSED_30B = 30 ;
+static const uint8_t P9N2_C_CPLT_CTRL1_UNUSED_31B = 31 ;
+
+static const uint8_t P9N2_EQ_CPLT_MASK0_CPLTMASK0 = 0 ;
+static const uint8_t P9N2_EQ_CPLT_MASK0_CPLTMASK0_LEN = 24 ;
+
+static const uint8_t P9N2_EX_CPLT_MASK0_CPLTMASK0 = 0 ;
+static const uint8_t P9N2_EX_CPLT_MASK0_CPLTMASK0_LEN = 24 ;
+
+static const uint8_t P9N2_C_CPLT_MASK0_CPLTMASK0 = 0 ;
+static const uint8_t P9N2_C_CPLT_MASK0_CPLTMASK0_LEN = 24 ;
+
+static const uint8_t P9N2_EQ_CPLT_STAT0_ABIST_DONE_DC = 0 ;
+static const uint8_t P9N2_EQ_CPLT_STAT0_EBIST_DONE_DC = 1 ;
+static const uint8_t P9N2_EQ_CPLT_STAT0_RESERVED_2E = 2 ;
+static const uint8_t P9N2_EQ_CPLT_STAT0_RESERVED_3E = 3 ;
+static const uint8_t P9N2_EQ_CPLT_STAT0_TC_DIAG_PORT0_OUT = 4 ;
+static const uint8_t P9N2_EQ_CPLT_STAT0_TC_DIAG_PORT1_OUT = 5 ;
+static const uint8_t P9N2_EQ_CPLT_STAT0_RESERVED_6E = 6 ;
+static const uint8_t P9N2_EQ_CPLT_STAT0_UNUSED = 7 ;
+static const uint8_t P9N2_EQ_CPLT_STAT0_CC_CTRL_OPCG_DONE_DC = 8 ;
+static const uint8_t P9N2_EQ_CPLT_STAT0_CC_CTRL_CHIPLET_IS_ALIGNED_DC = 9 ;
+static const uint8_t P9N2_EQ_CPLT_STAT0_FREE_USAGE_10E = 10 ;
+static const uint8_t P9N2_EQ_CPLT_STAT0_FREE_USAGE_11E = 11 ;
+static const uint8_t P9N2_EQ_CPLT_STAT0_FREE_USAGE_12E = 12 ;
+static const uint8_t P9N2_EQ_CPLT_STAT0_FREE_USAGE_13E = 13 ;
+static const uint8_t P9N2_EQ_CPLT_STAT0_FREE_USAGE_14E = 14 ;
+static const uint8_t P9N2_EQ_CPLT_STAT0_FREE_USAGE_15E = 15 ;
+static const uint8_t P9N2_EQ_CPLT_STAT0_FREE_USAGE_16E = 16 ;
+static const uint8_t P9N2_EQ_CPLT_STAT0_FREE_USAGE_17E = 17 ;
+static const uint8_t P9N2_EQ_CPLT_STAT0_FREE_USAGE_18E = 18 ;
+static const uint8_t P9N2_EQ_CPLT_STAT0_FREE_USAGE_19E = 19 ;
+static const uint8_t P9N2_EQ_CPLT_STAT0_FREE_USAGE_20E = 20 ;
+static const uint8_t P9N2_EQ_CPLT_STAT0_FREE_USAGE_21E = 21 ;
+static const uint8_t P9N2_EQ_CPLT_STAT0_FREE_USAGE_22E = 22 ;
+static const uint8_t P9N2_EQ_CPLT_STAT0_FREE_USAGE_23E = 23 ;
+
+static const uint8_t P9N2_EX_CPLT_STAT0_ABIST_DONE_DC = 0 ;
+static const uint8_t P9N2_EX_CPLT_STAT0_UNUSED_1E = 1 ;
+static const uint8_t P9N2_EX_CPLT_STAT0_RESERVED_2E = 2 ;
+static const uint8_t P9N2_EX_CPLT_STAT0_RESERVED_3E = 3 ;
+static const uint8_t P9N2_EX_CPLT_STAT0_TC_DIAG_PORT0_OUT = 4 ;
+static const uint8_t P9N2_EX_CPLT_STAT0_TC_DIAG_PORT1_OUT = 5 ;
+static const uint8_t P9N2_EX_CPLT_STAT0_RESERVED_6E = 6 ;
+static const uint8_t P9N2_EX_CPLT_STAT0_UNUSED_7E = 7 ;
+static const uint8_t P9N2_EX_CPLT_STAT0_CC_CTRL_OPCG_DONE_DC = 8 ;
+static const uint8_t P9N2_EX_CPLT_STAT0_CC_CTRL_CHIPLET_IS_ALIGNED_DC = 9 ;
+static const uint8_t P9N2_EX_CPLT_STAT0_PC_TC_VALID_NOT_HV_MODE = 10 ;
+static const uint8_t P9N2_EX_CPLT_STAT0_PC_TC_AVP_OUT = 11 ;
+static const uint8_t P9N2_EX_CPLT_STAT0_FREE_USAGE_12E = 12 ;
+static const uint8_t P9N2_EX_CPLT_STAT0_FREE_USAGE_13E = 13 ;
+static const uint8_t P9N2_EX_CPLT_STAT0_FREE_USAGE_14E = 14 ;
+static const uint8_t P9N2_EX_CPLT_STAT0_FREE_USAGE_15E = 15 ;
+static const uint8_t P9N2_EX_CPLT_STAT0_FREE_USAGE_16E = 16 ;
+static const uint8_t P9N2_EX_CPLT_STAT0_FREE_USAGE_17E = 17 ;
+static const uint8_t P9N2_EX_CPLT_STAT0_FREE_USAGE_18E = 18 ;
+static const uint8_t P9N2_EX_CPLT_STAT0_FREE_USAGE_19E = 19 ;
+static const uint8_t P9N2_EX_CPLT_STAT0_FREE_USAGE_20E = 20 ;
+static const uint8_t P9N2_EX_CPLT_STAT0_FREE_USAGE_21E = 21 ;
+static const uint8_t P9N2_EX_CPLT_STAT0_FREE_USAGE_22E = 22 ;
+static const uint8_t P9N2_EX_CPLT_STAT0_FREE_USAGE_23E = 23 ;
+
+static const uint8_t P9N2_C_CPLT_STAT0_ABIST_DONE_DC = 0 ;
+static const uint8_t P9N2_C_CPLT_STAT0_UNUSED_1E = 1 ;
+static const uint8_t P9N2_C_CPLT_STAT0_RESERVED_2E = 2 ;
+static const uint8_t P9N2_C_CPLT_STAT0_RESERVED_3E = 3 ;
+static const uint8_t P9N2_C_CPLT_STAT0_TC_DIAG_PORT0_OUT = 4 ;
+static const uint8_t P9N2_C_CPLT_STAT0_TC_DIAG_PORT1_OUT = 5 ;
+static const uint8_t P9N2_C_CPLT_STAT0_RESERVED_6E = 6 ;
+static const uint8_t P9N2_C_CPLT_STAT0_UNUSED_7E = 7 ;
+static const uint8_t P9N2_C_CPLT_STAT0_CC_CTRL_OPCG_DONE_DC = 8 ;
+static const uint8_t P9N2_C_CPLT_STAT0_CC_CTRL_CHIPLET_IS_ALIGNED_DC = 9 ;
+static const uint8_t P9N2_C_CPLT_STAT0_PC_TC_VALID_NOT_HV_MODE = 10 ;
+static const uint8_t P9N2_C_CPLT_STAT0_PC_TC_AVP_OUT = 11 ;
+static const uint8_t P9N2_C_CPLT_STAT0_FREE_USAGE_12E = 12 ;
+static const uint8_t P9N2_C_CPLT_STAT0_FREE_USAGE_13E = 13 ;
+static const uint8_t P9N2_C_CPLT_STAT0_FREE_USAGE_14E = 14 ;
+static const uint8_t P9N2_C_CPLT_STAT0_FREE_USAGE_15E = 15 ;
+static const uint8_t P9N2_C_CPLT_STAT0_FREE_USAGE_16E = 16 ;
+static const uint8_t P9N2_C_CPLT_STAT0_FREE_USAGE_17E = 17 ;
+static const uint8_t P9N2_C_CPLT_STAT0_FREE_USAGE_18E = 18 ;
+static const uint8_t P9N2_C_CPLT_STAT0_FREE_USAGE_19E = 19 ;
+static const uint8_t P9N2_C_CPLT_STAT0_FREE_USAGE_20E = 20 ;
+static const uint8_t P9N2_C_CPLT_STAT0_FREE_USAGE_21E = 21 ;
+static const uint8_t P9N2_C_CPLT_STAT0_FREE_USAGE_22E = 22 ;
+static const uint8_t P9N2_C_CPLT_STAT0_FREE_USAGE_23E = 23 ;
+
+static const uint8_t P9N2_EX_CPPM_CACCR_CLK_SB_STRENGTH = 0 ;
+static const uint8_t P9N2_EX_CPPM_CACCR_CLK_SB_STRENGTH_LEN = 4 ;
+static const uint8_t P9N2_EX_CPPM_CACCR_CLK_SB_SPARE = 4 ;
+static const uint8_t P9N2_EX_CPPM_CACCR_CLK_SB_PULSE_MODE_EN = 5 ;
+static const uint8_t P9N2_EX_CPPM_CACCR_CLK_SB_PULSE_MODE = 6 ;
+static const uint8_t P9N2_EX_CPPM_CACCR_CLK_SB_PULSE_MODE_LEN = 2 ;
+static const uint8_t P9N2_EX_CPPM_CACCR_CLK_SW_RESCLK = 8 ;
+static const uint8_t P9N2_EX_CPPM_CACCR_CLK_SW_RESCLK_LEN = 4 ;
+static const uint8_t P9N2_EX_CPPM_CACCR_CLK_SW_SPARE = 12 ;
+static const uint8_t P9N2_EX_CPPM_CACCR_QUAD_CLK_SB_OVERRIDE = 13 ;
+static const uint8_t P9N2_EX_CPPM_CACCR_QUAD_CLK_SW_OVERRIDE = 14 ;
+static const uint8_t P9N2_EX_CPPM_CACCR_CLK_SYNC_ENABLE = 15 ;
+
+static const uint8_t P9N2_C_CPPM_CACCR_CLK_SB_STRENGTH = 0 ;
+static const uint8_t P9N2_C_CPPM_CACCR_CLK_SB_STRENGTH_LEN = 4 ;
+static const uint8_t P9N2_C_CPPM_CACCR_CLK_SB_SPARE = 4 ;
+static const uint8_t P9N2_C_CPPM_CACCR_CLK_SB_PULSE_MODE_EN = 5 ;
+static const uint8_t P9N2_C_CPPM_CACCR_CLK_SB_PULSE_MODE = 6 ;
+static const uint8_t P9N2_C_CPPM_CACCR_CLK_SB_PULSE_MODE_LEN = 2 ;
+static const uint8_t P9N2_C_CPPM_CACCR_CLK_SW_RESCLK = 8 ;
+static const uint8_t P9N2_C_CPPM_CACCR_CLK_SW_RESCLK_LEN = 4 ;
+static const uint8_t P9N2_C_CPPM_CACCR_CLK_SW_SPARE = 12 ;
+static const uint8_t P9N2_C_CPPM_CACCR_QUAD_CLK_SB_OVERRIDE = 13 ;
+static const uint8_t P9N2_C_CPPM_CACCR_QUAD_CLK_SW_OVERRIDE = 14 ;
+static const uint8_t P9N2_C_CPPM_CACCR_CLK_SYNC_ENABLE = 15 ;
+
+static const uint8_t P9N2_EX_CPPM_CACSR_ACTUAL_CLK_SB_STRENGTH = 0 ;
+static const uint8_t P9N2_EX_CPPM_CACSR_ACTUAL_CLK_SB_STRENGTH_LEN = 4 ;
+static const uint8_t P9N2_EX_CPPM_CACSR_ACTUAL_CLK_SB_SPARE = 4 ;
+static const uint8_t P9N2_EX_CPPM_CACSR_ACTUAL_CLK_SB_PULSE_MODE_EN = 5 ;
+static const uint8_t P9N2_EX_CPPM_CACSR_ACTUAL_CLK_SB_PULSE_MODE = 6 ;
+static const uint8_t P9N2_EX_CPPM_CACSR_ACTUAL_CLK_SB_PULSE_MODE_LEN = 2 ;
+static const uint8_t P9N2_EX_CPPM_CACSR_ACTUAL_CLK_SW_RESCLK = 8 ;
+static const uint8_t P9N2_EX_CPPM_CACSR_ACTUAL_CLK_SW_RESCLK_LEN = 4 ;
+static const uint8_t P9N2_EX_CPPM_CACSR_ACTUAL_CLK_SW_SPARE = 12 ;
+static const uint8_t P9N2_EX_CPPM_CACSR_CLK_SYNC_DONE = 13 ;
+
+static const uint8_t P9N2_C_CPPM_CACSR_ACTUAL_CLK_SB_STRENGTH = 0 ;
+static const uint8_t P9N2_C_CPPM_CACSR_ACTUAL_CLK_SB_STRENGTH_LEN = 4 ;
+static const uint8_t P9N2_C_CPPM_CACSR_ACTUAL_CLK_SB_SPARE = 4 ;
+static const uint8_t P9N2_C_CPPM_CACSR_ACTUAL_CLK_SB_PULSE_MODE_EN = 5 ;
+static const uint8_t P9N2_C_CPPM_CACSR_ACTUAL_CLK_SB_PULSE_MODE = 6 ;
+static const uint8_t P9N2_C_CPPM_CACSR_ACTUAL_CLK_SB_PULSE_MODE_LEN = 2 ;
+static const uint8_t P9N2_C_CPPM_CACSR_ACTUAL_CLK_SW_RESCLK = 8 ;
+static const uint8_t P9N2_C_CPPM_CACSR_ACTUAL_CLK_SW_RESCLK_LEN = 4 ;
+static const uint8_t P9N2_C_CPPM_CACSR_ACTUAL_CLK_SW_SPARE = 12 ;
+static const uint8_t P9N2_C_CPPM_CACSR_CLK_SYNC_DONE = 13 ;
+
+static const uint8_t P9N2_EX_CPPM_CIIR_MSGSND_INTR_INJECT = 28 ;
+static const uint8_t P9N2_EX_CPPM_CIIR_MSGSND_INTR_INJECT_LEN = 4 ;
+static const uint8_t P9N2_EX_CPPM_CIIR_DD2_MSGSNDU_INTR_INJECT = 60 ;
+static const uint8_t P9N2_EX_CPPM_CIIR_DD2_MSGSNDU_INTR_INJECT_LEN = 4 ;
+
+static const uint8_t P9N2_C_CPPM_CIIR_MSGSND_INTR_INJECT = 28 ;
+static const uint8_t P9N2_C_CPPM_CIIR_MSGSND_INTR_INJECT_LEN = 4 ;
+static const uint8_t P9N2_C_CPPM_CIIR_DD2_MSGSNDU_INTR_INJECT = 60 ;
+static const uint8_t P9N2_C_CPPM_CIIR_DD2_MSGSNDU_INTR_INJECT_LEN = 4 ;
+
+static const uint8_t P9N2_EX_CPPM_CISR_HYP_INTR_PRESENT = 0 ;
+static const uint8_t P9N2_EX_CPPM_CISR_HYP_INTR_PRESENT_LEN = 4 ;
+static const uint8_t P9N2_EX_CPPM_CISR_OS_INTR_PRESENT = 4 ;
+static const uint8_t P9N2_EX_CPPM_CISR_OS_INTR_PRESENT_LEN = 4 ;
+static const uint8_t P9N2_EX_CPPM_CISR_MSGSND_INTR_PRESENT = 8 ;
+static const uint8_t P9N2_EX_CPPM_CISR_MSGSND_INTR_PRESENT_LEN = 4 ;
+static const uint8_t P9N2_EX_CPPM_CISR_EBB_INTR_PRESENT = 12 ;
+static const uint8_t P9N2_EX_CPPM_CISR_EBB_INTR_PRESENT_LEN = 4 ;
+static const uint8_t P9N2_EX_CPPM_CISR_HYP_INTR_REQUESTED = 16 ;
+static const uint8_t P9N2_EX_CPPM_CISR_HYP_INTR_REQUESTED_LEN = 4 ;
+static const uint8_t P9N2_EX_CPPM_CISR_OS_INTR_REQUESTED = 20 ;
+static const uint8_t P9N2_EX_CPPM_CISR_OS_INTR_REQUESTED_LEN = 4 ;
+static const uint8_t P9N2_EX_CPPM_CISR_MSGSND_INTR_REQUESTED = 24 ;
+static const uint8_t P9N2_EX_CPPM_CISR_MSGSND_INTR_REQUESTED_LEN = 4 ;
+static const uint8_t P9N2_EX_CPPM_CISR_MSGSND_INTR_SAMPLE = 28 ;
+static const uint8_t P9N2_EX_CPPM_CISR_MSGSND_INTR_SAMPLE_LEN = 4 ;
+static const uint8_t P9N2_EX_CPPM_CISR_MSGSND_ACK = 32 ;
+static const uint8_t P9N2_EX_CPPM_CISR_MALF_ALERT_PRESENT = 33 ;
+static const uint8_t P9N2_EX_CPPM_CISR_MALF_ALERT_REQUESTED = 34 ;
+static const uint8_t P9N2_EX_CPPM_CISR_CME_SPECIAL_WKUP_DONE = 35 ;
+static const uint8_t P9N2_EX_CPPM_CISR_DD2_MSGSNDU_INTR_PRESENT = 36 ;
+static const uint8_t P9N2_EX_CPPM_CISR_DD2_MSGSNDU_INTR_PRESENT_LEN = 4 ;
+static const uint8_t P9N2_EX_CPPM_CISR_DD2_MSGSNDU_INTR_REQUESTED = 40 ;
+static const uint8_t P9N2_EX_CPPM_CISR_DD2_MSGSNDU_INTR_REQUESTED_LEN = 4 ;
+static const uint8_t P9N2_EX_CPPM_CISR_DD2_MSGSNDU_INTR_SAMPLE = 44 ;
+static const uint8_t P9N2_EX_CPPM_CISR_DD2_MSGSNDU_INTR_SAMPLE_LEN = 4 ;
+
+static const uint8_t P9N2_C_CPPM_CISR_HYP_INTR_PRESENT = 0 ;
+static const uint8_t P9N2_C_CPPM_CISR_HYP_INTR_PRESENT_LEN = 4 ;
+static const uint8_t P9N2_C_CPPM_CISR_OS_INTR_PRESENT = 4 ;
+static const uint8_t P9N2_C_CPPM_CISR_OS_INTR_PRESENT_LEN = 4 ;
+static const uint8_t P9N2_C_CPPM_CISR_MSGSND_INTR_PRESENT = 8 ;
+static const uint8_t P9N2_C_CPPM_CISR_MSGSND_INTR_PRESENT_LEN = 4 ;
+static const uint8_t P9N2_C_CPPM_CISR_EBB_INTR_PRESENT = 12 ;
+static const uint8_t P9N2_C_CPPM_CISR_EBB_INTR_PRESENT_LEN = 4 ;
+static const uint8_t P9N2_C_CPPM_CISR_HYP_INTR_REQUESTED = 16 ;
+static const uint8_t P9N2_C_CPPM_CISR_HYP_INTR_REQUESTED_LEN = 4 ;
+static const uint8_t P9N2_C_CPPM_CISR_OS_INTR_REQUESTED = 20 ;
+static const uint8_t P9N2_C_CPPM_CISR_OS_INTR_REQUESTED_LEN = 4 ;
+static const uint8_t P9N2_C_CPPM_CISR_MSGSND_INTR_REQUESTED = 24 ;
+static const uint8_t P9N2_C_CPPM_CISR_MSGSND_INTR_REQUESTED_LEN = 4 ;
+static const uint8_t P9N2_C_CPPM_CISR_MSGSND_INTR_SAMPLE = 28 ;
+static const uint8_t P9N2_C_CPPM_CISR_MSGSND_INTR_SAMPLE_LEN = 4 ;
+static const uint8_t P9N2_C_CPPM_CISR_MSGSND_ACK = 32 ;
+static const uint8_t P9N2_C_CPPM_CISR_MALF_ALERT_PRESENT = 33 ;
+static const uint8_t P9N2_C_CPPM_CISR_MALF_ALERT_REQUESTED = 34 ;
+static const uint8_t P9N2_C_CPPM_CISR_CME_SPECIAL_WKUP_DONE = 35 ;
+static const uint8_t P9N2_C_CPPM_CISR_DD2_MSGSNDU_INTR_PRESENT = 36 ;
+static const uint8_t P9N2_C_CPPM_CISR_DD2_MSGSNDU_INTR_PRESENT_LEN = 4 ;
+static const uint8_t P9N2_C_CPPM_CISR_DD2_MSGSNDU_INTR_REQUESTED = 40 ;
+static const uint8_t P9N2_C_CPPM_CISR_DD2_MSGSNDU_INTR_REQUESTED_LEN = 4 ;
+static const uint8_t P9N2_C_CPPM_CISR_DD2_MSGSNDU_INTR_SAMPLE = 44 ;
+static const uint8_t P9N2_C_CPPM_CISR_DD2_MSGSNDU_INTR_SAMPLE_LEN = 4 ;
+
+static const uint8_t P9N2_EX_CPPM_CIVRMLCR_IVRM_LOCAL_CONTROL = 0 ;
+static const uint8_t P9N2_EX_CPPM_CIVRMLCR_RESERVED_1_2 = 1 ;
+static const uint8_t P9N2_EX_CPPM_CIVRMLCR_RESERVED_1_2_LEN = 2 ;
+static const uint8_t P9N2_EX_CPPM_CIVRMLCR_IVRM_UREG_TEST_EN = 3 ;
+static const uint8_t P9N2_EX_CPPM_CIVRMLCR_IVRM_UREG_TEST_ID = 4 ;
+static const uint8_t P9N2_EX_CPPM_CIVRMLCR_IVRM_UREG_TEST_ID_LEN = 4 ;
+
+static const uint8_t P9N2_C_CPPM_CIVRMLCR_IVRM_LOCAL_CONTROL = 0 ;
+static const uint8_t P9N2_C_CPPM_CIVRMLCR_RESERVED_1_2 = 1 ;
+static const uint8_t P9N2_C_CPPM_CIVRMLCR_RESERVED_1_2_LEN = 2 ;
+static const uint8_t P9N2_C_CPPM_CIVRMLCR_IVRM_UREG_TEST_EN = 3 ;
+static const uint8_t P9N2_C_CPPM_CIVRMLCR_IVRM_UREG_TEST_ID = 4 ;
+static const uint8_t P9N2_C_CPPM_CIVRMLCR_IVRM_UREG_TEST_ID_LEN = 4 ;
+
+static const uint8_t P9N2_EX_CPPM_CMEDATA_DATA = 0 ;
+static const uint8_t P9N2_EX_CPPM_CMEDATA_DATA_LEN = 32 ;
+
+static const uint8_t P9N2_C_CPPM_CMEDATA_DATA = 0 ;
+static const uint8_t P9N2_C_CPPM_CMEDATA_DATA_LEN = 32 ;
+
+static const uint8_t P9N2_EX_CPPM_CMEDB0_CME_MESSAGE_NUMBER0 = 0 ;
+static const uint8_t P9N2_EX_CPPM_CMEDB0_CME_MESSAGE_NUMBER0_LEN = 8 ;
+static const uint8_t P9N2_EX_CPPM_CMEDB0_CME_MESSAGE_HI = 8 ;
+static const uint8_t P9N2_EX_CPPM_CMEDB0_CME_MESSAGE_HI_LEN = 56 ;
+
+static const uint8_t P9N2_C_CPPM_CMEDB0_CME_MESSAGE_NUMBER0 = 0 ;
+static const uint8_t P9N2_C_CPPM_CMEDB0_CME_MESSAGE_NUMBER0_LEN = 8 ;
+static const uint8_t P9N2_C_CPPM_CMEDB0_CME_MESSAGE_HI = 8 ;
+static const uint8_t P9N2_C_CPPM_CMEDB0_CME_MESSAGE_HI_LEN = 56 ;
+
+static const uint8_t P9N2_EX_CPPM_CMEDB1_CME_MESSAGE_NUMBER_N = 0 ;
+static const uint8_t P9N2_EX_CPPM_CMEDB1_CME_MESSAGE_NUMBER_N_LEN = 8 ;
+
+static const uint8_t P9N2_C_CPPM_CMEDB1_CME_MESSAGE_NUMBER_N = 0 ;
+static const uint8_t P9N2_C_CPPM_CMEDB1_CME_MESSAGE_NUMBER_N_LEN = 8 ;
+
+static const uint8_t P9N2_EX_CPPM_CMEDB2_CME_MESSAGE_NUMBER_N = 0 ;
+static const uint8_t P9N2_EX_CPPM_CMEDB2_CME_MESSAGE_NUMBER_N_LEN = 8 ;
+
+static const uint8_t P9N2_C_CPPM_CMEDB2_CME_MESSAGE_NUMBER_N = 0 ;
+static const uint8_t P9N2_C_CPPM_CMEDB2_CME_MESSAGE_NUMBER_N_LEN = 8 ;
+
+static const uint8_t P9N2_EX_CPPM_CMEDB3_CME_MESSAGE_NUMBER_N = 0 ;
+static const uint8_t P9N2_EX_CPPM_CMEDB3_CME_MESSAGE_NUMBER_N_LEN = 8 ;
+static const uint8_t P9N2_EX_CPPM_CMEDB3_CME_MESSAGE_HI = 8 ;
+static const uint8_t P9N2_EX_CPPM_CMEDB3_CME_MESSAGE_HI_LEN = 56 ;
+
+static const uint8_t P9N2_C_CPPM_CMEDB3_CME_MESSAGE_NUMBER_N = 0 ;
+static const uint8_t P9N2_C_CPPM_CMEDB3_CME_MESSAGE_NUMBER_N_LEN = 8 ;
+static const uint8_t P9N2_C_CPPM_CMEDB3_CME_MESSAGE_HI = 8 ;
+static const uint8_t P9N2_C_CPPM_CMEDB3_CME_MESSAGE_HI_LEN = 56 ;
+
+static const uint8_t P9N2_EX_CPPM_CMEMSG_CME_MESSAGE = 0 ;
+static const uint8_t P9N2_EX_CPPM_CMEMSG_CME_MESSAGE_LEN = 64 ;
+
+static const uint8_t P9N2_C_CPPM_CMEMSG_CME_MESSAGE = 0 ;
+static const uint8_t P9N2_C_CPPM_CMEMSG_CME_MESSAGE_LEN = 64 ;
+
+static const uint8_t P9N2_EX_CPPM_CPMMR_PPM_WRITE_DISABLE = 0 ;
+static const uint8_t P9N2_EX_CPPM_CPMMR_PPM_WRITE_OVERRIDE = 1 ;
+static const uint8_t P9N2_EX_CPPM_CPMMR_RESERVED_2_8 = 2 ;
+static const uint8_t P9N2_EX_CPPM_CPMMR_RESERVED_2_8_LEN = 7 ;
+static const uint8_t P9N2_EX_CPPM_CPMMR_FUSED_CORE_MODE = 9 ;
+static const uint8_t P9N2_EX_CPPM_CPMMR_STOP_EXIT_TYPE_SEL = 10 ;
+static const uint8_t P9N2_EX_CPPM_CPMMR_BLOCK_INTR_INPUTS = 11 ;
+static const uint8_t P9N2_EX_CPPM_CPMMR_CME_ERR_NOTIFY_DIS = 12 ;
+static const uint8_t P9N2_EX_CPPM_CPMMR_WKUP_NOTIFY_SELECT = 13 ;
+static const uint8_t P9N2_EX_CPPM_CPMMR_ENABLE_PECE = 14 ;
+static const uint8_t P9N2_EX_CPPM_CPMMR_CME_SPECIAL_WKUP_DONE_DIS = 15 ;
+
+static const uint8_t P9N2_C_CPPM_CPMMR_PPM_WRITE_DISABLE = 0 ;
+static const uint8_t P9N2_C_CPPM_CPMMR_PPM_WRITE_OVERRIDE = 1 ;
+static const uint8_t P9N2_C_CPPM_CPMMR_RESERVED_2_8 = 2 ;
+static const uint8_t P9N2_C_CPPM_CPMMR_RESERVED_2_8_LEN = 7 ;
+static const uint8_t P9N2_C_CPPM_CPMMR_FUSED_CORE_MODE = 9 ;
+static const uint8_t P9N2_C_CPPM_CPMMR_STOP_EXIT_TYPE_SEL = 10 ;
+static const uint8_t P9N2_C_CPPM_CPMMR_BLOCK_INTR_INPUTS = 11 ;
+static const uint8_t P9N2_C_CPPM_CPMMR_CME_ERR_NOTIFY_DIS = 12 ;
+static const uint8_t P9N2_C_CPPM_CPMMR_WKUP_NOTIFY_SELECT = 13 ;
+static const uint8_t P9N2_C_CPPM_CPMMR_ENABLE_PECE = 14 ;
+static const uint8_t P9N2_C_CPPM_CPMMR_CME_SPECIAL_WKUP_DONE_DIS = 15 ;
+
+static const uint8_t P9N2_EX_CPPM_CSAR_SCRATCH_ATOMIC_DATA = 0 ;
+static const uint8_t P9N2_EX_CPPM_CSAR_SCRATCH_ATOMIC_DATA_LEN = 32 ;
+
+static const uint8_t P9N2_C_CPPM_CSAR_SCRATCH_ATOMIC_DATA = 0 ;
+static const uint8_t P9N2_C_CPPM_CSAR_SCRATCH_ATOMIC_DATA_LEN = 32 ;
+
+static const uint8_t P9N2_EX_CPPM_ERR_PCB_INTERRUPT_PROTOCOL = 0 ;
+static const uint8_t P9N2_EX_CPPM_ERR_SPECIAL_WKUP_PROTOCOL = 1 ;
+static const uint8_t P9N2_EX_CPPM_ERR_SPECIAL_WKUP_DONE_PROTOCOL = 2 ;
+static const uint8_t P9N2_EX_CPPM_ERR_PFET_SEQ_PROGRAM = 3 ;
+static const uint8_t P9N2_EX_CPPM_ERR_CLK_SYNC = 4 ;
+static const uint8_t P9N2_EX_CPPM_ERR_PECE_INTR_DISABLED = 5 ;
+static const uint8_t P9N2_EX_CPPM_ERR_DECONFIGURED_INTR = 6 ;
+static const uint8_t P9N2_EX_CPPM_ERR_RESERVED_7 = 7 ;
+static const uint8_t P9N2_EX_CPPM_ERR_RESERVED_8_11 = 8 ;
+static const uint8_t P9N2_EX_CPPM_ERR_RESERVED_8_11_LEN = 4 ;
+
+static const uint8_t P9N2_C_CPPM_ERR_PCB_INTERRUPT_PROTOCOL = 0 ;
+static const uint8_t P9N2_C_CPPM_ERR_SPECIAL_WKUP_PROTOCOL = 1 ;
+static const uint8_t P9N2_C_CPPM_ERR_SPECIAL_WKUP_DONE_PROTOCOL = 2 ;
+static const uint8_t P9N2_C_CPPM_ERR_PFET_SEQ_PROGRAM = 3 ;
+static const uint8_t P9N2_C_CPPM_ERR_CLK_SYNC = 4 ;
+static const uint8_t P9N2_C_CPPM_ERR_PECE_INTR_DISABLED = 5 ;
+static const uint8_t P9N2_C_CPPM_ERR_DECONFIGURED_INTR = 6 ;
+static const uint8_t P9N2_C_CPPM_ERR_RESERVED_7 = 7 ;
+static const uint8_t P9N2_C_CPPM_ERR_RESERVED_8_11 = 8 ;
+static const uint8_t P9N2_C_CPPM_ERR_RESERVED_8_11_LEN = 4 ;
+
+static const uint8_t P9N2_EX_CPPM_ERRMSK_RESERVED_0_11 = 0 ;
+static const uint8_t P9N2_EX_CPPM_ERRMSK_RESERVED_0_11_LEN = 12 ;
+
+static const uint8_t P9N2_C_CPPM_ERRMSK_RESERVED_0_11 = 0 ;
+static const uint8_t P9N2_C_CPPM_ERRMSK_RESERVED_0_11_LEN = 12 ;
+
+static const uint8_t P9N2_EX_CPPM_IPPMCMD_QPPM_REG = 0 ;
+static const uint8_t P9N2_EX_CPPM_IPPMCMD_QPPM_REG_LEN = 8 ;
+static const uint8_t P9N2_EX_CPPM_IPPMCMD_QPPM_RNW = 8 ;
+static const uint8_t P9N2_EX_CPPM_IPPMCMD_RESERVED_9 = 9 ;
+
+static const uint8_t P9N2_C_CPPM_IPPMCMD_QPPM_REG = 0 ;
+static const uint8_t P9N2_C_CPPM_IPPMCMD_QPPM_REG_LEN = 8 ;
+static const uint8_t P9N2_C_CPPM_IPPMCMD_QPPM_RNW = 8 ;
+static const uint8_t P9N2_C_CPPM_IPPMCMD_RESERVED_9 = 9 ;
+
+static const uint8_t P9N2_EX_CPPM_IPPMRDATA_QPPM_RDATA = 0 ;
+static const uint8_t P9N2_EX_CPPM_IPPMRDATA_QPPM_RDATA_LEN = 64 ;
+
+static const uint8_t P9N2_C_CPPM_IPPMRDATA_QPPM_RDATA = 0 ;
+static const uint8_t P9N2_C_CPPM_IPPMRDATA_QPPM_RDATA_LEN = 64 ;
+
+static const uint8_t P9N2_EX_CPPM_IPPMSTAT_QPPM_ONGOING = 0 ;
+static const uint8_t P9N2_EX_CPPM_IPPMSTAT_QPPM_STATUS = 1 ;
+static const uint8_t P9N2_EX_CPPM_IPPMSTAT_QPPM_STATUS_LEN = 2 ;
+
+static const uint8_t P9N2_C_CPPM_IPPMSTAT_QPPM_ONGOING = 0 ;
+static const uint8_t P9N2_C_CPPM_IPPMSTAT_QPPM_STATUS = 1 ;
+static const uint8_t P9N2_C_CPPM_IPPMSTAT_QPPM_STATUS_LEN = 2 ;
+
+static const uint8_t P9N2_EX_CPPM_IPPMWDATA_QPPM_WDATA = 0 ;
+static const uint8_t P9N2_EX_CPPM_IPPMWDATA_QPPM_WDATA_LEN = 64 ;
+
+static const uint8_t P9N2_C_CPPM_IPPMWDATA_QPPM_WDATA = 0 ;
+static const uint8_t P9N2_C_CPPM_IPPMWDATA_QPPM_WDATA_LEN = 64 ;
+
+static const uint8_t P9N2_EX_CPPM_NC0INDIR_NC_N_INDIRECT = 0 ;
+static const uint8_t P9N2_EX_CPPM_NC0INDIR_NC_N_INDIRECT_LEN = 32 ;
+
+static const uint8_t P9N2_C_CPPM_NC0INDIR_NC_N_INDIRECT = 0 ;
+static const uint8_t P9N2_C_CPPM_NC0INDIR_NC_N_INDIRECT_LEN = 32 ;
+
+static const uint8_t P9N2_EX_CPPM_NC1INDIR_NC_N_INDIRECT = 0 ;
+static const uint8_t P9N2_EX_CPPM_NC1INDIR_NC_N_INDIRECT_LEN = 32 ;
+
+static const uint8_t P9N2_C_CPPM_NC1INDIR_NC_N_INDIRECT = 0 ;
+static const uint8_t P9N2_C_CPPM_NC1INDIR_NC_N_INDIRECT_LEN = 32 ;
+
+static const uint8_t P9N2_EX_CPPM_PECES_PECE_T0 = 0 ;
+static const uint8_t P9N2_EX_CPPM_PECES_PECE_T0_LEN = 6 ;
+static const uint8_t P9N2_EX_CPPM_PECES_PECE_T1 = 8 ;
+static const uint8_t P9N2_EX_CPPM_PECES_PECE_T1_LEN = 6 ;
+static const uint8_t P9N2_EX_CPPM_PECES_PECE_T2 = 16 ;
+static const uint8_t P9N2_EX_CPPM_PECES_PECE_T2_LEN = 6 ;
+static const uint8_t P9N2_EX_CPPM_PECES_PECE_T3 = 24 ;
+static const uint8_t P9N2_EX_CPPM_PECES_PECE_T3_LEN = 6 ;
+static const uint8_t P9N2_EX_CPPM_PECES_USE_PECE = 32 ;
+static const uint8_t P9N2_EX_CPPM_PECES_USE_PECE_LEN = 4 ;
+
+static const uint8_t P9N2_C_CPPM_PECES_PECE_T0 = 0 ;
+static const uint8_t P9N2_C_CPPM_PECES_PECE_T0_LEN = 6 ;
+static const uint8_t P9N2_C_CPPM_PECES_PECE_T1 = 8 ;
+static const uint8_t P9N2_C_CPPM_PECES_PECE_T1_LEN = 6 ;
+static const uint8_t P9N2_C_CPPM_PECES_PECE_T2 = 16 ;
+static const uint8_t P9N2_C_CPPM_PECES_PECE_T2_LEN = 6 ;
+static const uint8_t P9N2_C_CPPM_PECES_PECE_T3 = 24 ;
+static const uint8_t P9N2_C_CPPM_PECES_PECE_T3_LEN = 6 ;
+static const uint8_t P9N2_C_CPPM_PECES_USE_PECE = 32 ;
+static const uint8_t P9N2_C_CPPM_PECES_USE_PECE_LEN = 4 ;
+
+static const uint8_t P9N2_EX_CPPM_PERRSUM_ERROR = 0 ;
+
+static const uint8_t P9N2_C_CPPM_PERRSUM_ERROR = 0 ;
+
+static const uint8_t P9N2_EQ_CSAR_SRAM_ADDRESS = 16 ;
+static const uint8_t P9N2_EQ_CSAR_SRAM_ADDRESS_LEN = 13 ;
+
+static const uint8_t P9N2_EX_CSAR_SRAM_ADDRESS = 16 ;
+static const uint8_t P9N2_EX_CSAR_SRAM_ADDRESS_LEN = 13 ;
+
+static const uint8_t P9N2_EQ_CSCR_SRAM_ACCESS_MODE = 0 ;
+static const uint8_t P9N2_EQ_CSCR_SRAM_SCRUB_ENABLE = 1 ;
+static const uint8_t P9N2_EQ_CSCR_ECC_CORRECT_DIS = 2 ;
+static const uint8_t P9N2_EQ_CSCR_ECC_DETECT_DIS = 3 ;
+static const uint8_t P9N2_EQ_CSCR_ECC_INJECT_TYPE = 4 ;
+static const uint8_t P9N2_EQ_CSCR_ECC_INJECT_ERR = 5 ;
+static const uint8_t P9N2_EQ_CSCR_SPARE_6_7 = 6 ;
+static const uint8_t P9N2_EQ_CSCR_SPARE_6_7_LEN = 2 ;
+static const uint8_t P9N2_EQ_CSCR_SRAM_SCRUB_INDEX = 47 ;
+static const uint8_t P9N2_EQ_CSCR_SRAM_SCRUB_INDEX_LEN = 13 ;
+
+static const uint8_t P9N2_EX_CSCR_SRAM_ACCESS_MODE = 0 ;
+static const uint8_t P9N2_EX_CSCR_SRAM_SCRUB_ENABLE = 1 ;
+static const uint8_t P9N2_EX_CSCR_ECC_CORRECT_DIS = 2 ;
+static const uint8_t P9N2_EX_CSCR_ECC_DETECT_DIS = 3 ;
+static const uint8_t P9N2_EX_CSCR_ECC_INJECT_TYPE = 4 ;
+static const uint8_t P9N2_EX_CSCR_ECC_INJECT_ERR = 5 ;
+static const uint8_t P9N2_EX_CSCR_SPARE_6_7 = 6 ;
+static const uint8_t P9N2_EX_CSCR_SPARE_6_7_LEN = 2 ;
+static const uint8_t P9N2_EX_CSCR_SRAM_SCRUB_INDEX = 47 ;
+static const uint8_t P9N2_EX_CSCR_SRAM_SCRUB_INDEX_LEN = 13 ;
+
+static const uint8_t P9N2_EQ_CSDR_SRAM_DATA = 0 ;
+static const uint8_t P9N2_EQ_CSDR_SRAM_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_EX_CSDR_SRAM_DATA = 0 ;
+static const uint8_t P9N2_EX_CSDR_SRAM_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_EX_L2_CTRL_T0_RUN_Q = 48 ;
+static const uint8_t P9N2_EX_L2_CTRL_T1_RUN_Q = 49 ;
+static const uint8_t P9N2_EX_L2_CTRL_T2_RUN_Q = 50 ;
+static const uint8_t P9N2_EX_L2_CTRL_T3_RUN_Q = 51 ;
+static const uint8_t P9N2_EX_L2_CTRL_T4_RUN_Q = 52 ;
+static const uint8_t P9N2_EX_L2_CTRL_T5_RUN_Q = 53 ;
+static const uint8_t P9N2_EX_L2_CTRL_T6_RUN_Q = 54 ;
+static const uint8_t P9N2_EX_L2_CTRL_T7_RUN_Q = 55 ;
+static const uint8_t P9N2_EX_L2_CTRL_RUN_LATCH = 63 ;
+
+static const uint8_t P9N2_C_CTRL_T0_RUN_Q = 48 ;
+static const uint8_t P9N2_C_CTRL_T1_RUN_Q = 49 ;
+static const uint8_t P9N2_C_CTRL_T2_RUN_Q = 50 ;
+static const uint8_t P9N2_C_CTRL_T3_RUN_Q = 51 ;
+static const uint8_t P9N2_C_CTRL_T4_RUN_Q = 52 ;
+static const uint8_t P9N2_C_CTRL_T5_RUN_Q = 53 ;
+static const uint8_t P9N2_C_CTRL_T6_RUN_Q = 54 ;
+static const uint8_t P9N2_C_CTRL_T7_RUN_Q = 55 ;
+static const uint8_t P9N2_C_CTRL_RUN_LATCH = 63 ;
+
+static const uint8_t P9N2_EQ_CTRL_ATOMIC_LOCK_REG_ENABLE = 0 ;
+static const uint8_t P9N2_EQ_CTRL_ATOMIC_LOCK_REG_ID = 1 ;
+static const uint8_t P9N2_EQ_CTRL_ATOMIC_LOCK_REG_ID_LEN = 4 ;
+static const uint8_t P9N2_EQ_CTRL_ATOMIC_LOCK_REG_ACTIVITY = 8 ;
+static const uint8_t P9N2_EQ_CTRL_ATOMIC_LOCK_REG_ACTIVITY_LEN = 8 ;
+
+static const uint8_t P9N2_EX_CTRL_ATOMIC_LOCK_REG_ENABLE = 0 ;
+static const uint8_t P9N2_EX_CTRL_ATOMIC_LOCK_REG_ID = 1 ;
+static const uint8_t P9N2_EX_CTRL_ATOMIC_LOCK_REG_ID_LEN = 4 ;
+static const uint8_t P9N2_EX_CTRL_ATOMIC_LOCK_REG_ACTIVITY = 8 ;
+static const uint8_t P9N2_EX_CTRL_ATOMIC_LOCK_REG_ACTIVITY_LEN = 8 ;
+
+static const uint8_t P9N2_C_CTRL_ATOMIC_LOCK_REG_ENABLE = 0 ;
+static const uint8_t P9N2_C_CTRL_ATOMIC_LOCK_REG_ID = 1 ;
+static const uint8_t P9N2_C_CTRL_ATOMIC_LOCK_REG_ID_LEN = 4 ;
+static const uint8_t P9N2_C_CTRL_ATOMIC_LOCK_REG_ACTIVITY = 8 ;
+static const uint8_t P9N2_C_CTRL_ATOMIC_LOCK_REG_ACTIVITY_LEN = 8 ;
+
+static const uint8_t P9N2_EQ_CTRL_PROTECT_MODE_REG_READ_ENABLE = 0 ;
+static const uint8_t P9N2_EQ_CTRL_PROTECT_MODE_REG_WRITE_ENABLE = 1 ;
+
+static const uint8_t P9N2_EX_CTRL_PROTECT_MODE_REG_READ_ENABLE = 0 ;
+static const uint8_t P9N2_EX_CTRL_PROTECT_MODE_REG_WRITE_ENABLE = 1 ;
+
+static const uint8_t P9N2_C_CTRL_PROTECT_MODE_REG_READ_ENABLE = 0 ;
+static const uint8_t P9N2_C_CTRL_PROTECT_MODE_REG_WRITE_ENABLE = 1 ;
+
+static const uint8_t P9N2_EQ_DBG_CBS_CC_RESET_EP = 0 ;
+static const uint8_t P9N2_EQ_DBG_CBS_CC_OPCG_IP = 1 ;
+static const uint8_t P9N2_EQ_DBG_CBS_CC_VITL_CLKOFF = 2 ;
+static const uint8_t P9N2_EQ_DBG_CBS_CC_TEST_ENABLE = 3 ;
+static const uint8_t P9N2_EQ_DBG_CBS_CC_REQ = 4 ;
+static const uint8_t P9N2_EQ_DBG_CBS_CC_CMD = 5 ;
+static const uint8_t P9N2_EQ_DBG_CBS_CC_CMD_LEN = 3 ;
+static const uint8_t P9N2_EQ_DBG_CBS_CC_STATE = 8 ;
+static const uint8_t P9N2_EQ_DBG_CBS_CC_STATE_LEN = 5 ;
+static const uint8_t P9N2_EQ_DBG_CBS_CC_SECURITY_DEBUG_MODE = 13 ;
+static const uint8_t P9N2_EQ_DBG_CBS_CC_PROTOCOL_ERROR = 14 ;
+static const uint8_t P9N2_EQ_DBG_CBS_CC_PCB_IDLE = 15 ;
+static const uint8_t P9N2_EQ_DBG_CBS_CC_CURRENT_OPCG_MODE = 16 ;
+static const uint8_t P9N2_EQ_DBG_CBS_CC_CURRENT_OPCG_MODE_LEN = 4 ;
+static const uint8_t P9N2_EQ_DBG_CBS_CC_LAST_OPCG_MODE = 20 ;
+static const uint8_t P9N2_EQ_DBG_CBS_CC_LAST_OPCG_MODE_LEN = 4 ;
+static const uint8_t P9N2_EQ_DBG_CBS_CC_PCB_ERROR = 24 ;
+static const uint8_t P9N2_EQ_DBG_CBS_CC_PARITY_ERROR = 25 ;
+static const uint8_t P9N2_EQ_DBG_CBS_CC_ERROR = 26 ;
+static const uint8_t P9N2_EQ_DBG_CBS_CC_CHIPLET_IS_ALIGNED = 27 ;
+static const uint8_t P9N2_EQ_DBG_CBS_CC_PCB_REQUEST_SINCE_RESET = 28 ;
+static const uint8_t P9N2_EQ_DBG_CBS_CC_PARANOIA_TEST_ENABLE_CHANGE = 29 ;
+static const uint8_t P9N2_EQ_DBG_CBS_CC_PARANOIA_VITL_CLKOFF_CHANGE = 30 ;
+static const uint8_t P9N2_EQ_DBG_CBS_CC_TP_TPFSI_ACK = 31 ;
+
+static const uint8_t P9N2_EX_DBG_CBS_CC_RESET_EP = 0 ;
+static const uint8_t P9N2_EX_DBG_CBS_CC_OPCG_IP = 1 ;
+static const uint8_t P9N2_EX_DBG_CBS_CC_VITL_CLKOFF = 2 ;
+static const uint8_t P9N2_EX_DBG_CBS_CC_TEST_ENABLE = 3 ;
+static const uint8_t P9N2_EX_DBG_CBS_CC_REQ = 4 ;
+static const uint8_t P9N2_EX_DBG_CBS_CC_CMD = 5 ;
+static const uint8_t P9N2_EX_DBG_CBS_CC_CMD_LEN = 3 ;
+static const uint8_t P9N2_EX_DBG_CBS_CC_STATE = 8 ;
+static const uint8_t P9N2_EX_DBG_CBS_CC_STATE_LEN = 5 ;
+static const uint8_t P9N2_EX_DBG_CBS_CC_SECURITY_DEBUG_MODE = 13 ;
+static const uint8_t P9N2_EX_DBG_CBS_CC_PROTOCOL_ERROR = 14 ;
+static const uint8_t P9N2_EX_DBG_CBS_CC_PCB_IDLE = 15 ;
+static const uint8_t P9N2_EX_DBG_CBS_CC_CURRENT_OPCG_MODE = 16 ;
+static const uint8_t P9N2_EX_DBG_CBS_CC_CURRENT_OPCG_MODE_LEN = 4 ;
+static const uint8_t P9N2_EX_DBG_CBS_CC_LAST_OPCG_MODE = 20 ;
+static const uint8_t P9N2_EX_DBG_CBS_CC_LAST_OPCG_MODE_LEN = 4 ;
+static const uint8_t P9N2_EX_DBG_CBS_CC_PCB_ERROR = 24 ;
+static const uint8_t P9N2_EX_DBG_CBS_CC_PARITY_ERROR = 25 ;
+static const uint8_t P9N2_EX_DBG_CBS_CC_ERROR = 26 ;
+static const uint8_t P9N2_EX_DBG_CBS_CC_CHIPLET_IS_ALIGNED = 27 ;
+static const uint8_t P9N2_EX_DBG_CBS_CC_PCB_REQUEST_SINCE_RESET = 28 ;
+static const uint8_t P9N2_EX_DBG_CBS_CC_PARANOIA_TEST_ENABLE_CHANGE = 29 ;
+static const uint8_t P9N2_EX_DBG_CBS_CC_PARANOIA_VITL_CLKOFF_CHANGE = 30 ;
+static const uint8_t P9N2_EX_DBG_CBS_CC_TP_TPFSI_ACK = 31 ;
+
+static const uint8_t P9N2_C_DBG_CBS_CC_RESET_EP = 0 ;
+static const uint8_t P9N2_C_DBG_CBS_CC_OPCG_IP = 1 ;
+static const uint8_t P9N2_C_DBG_CBS_CC_VITL_CLKOFF = 2 ;
+static const uint8_t P9N2_C_DBG_CBS_CC_TEST_ENABLE = 3 ;
+static const uint8_t P9N2_C_DBG_CBS_CC_REQ = 4 ;
+static const uint8_t P9N2_C_DBG_CBS_CC_CMD = 5 ;
+static const uint8_t P9N2_C_DBG_CBS_CC_CMD_LEN = 3 ;
+static const uint8_t P9N2_C_DBG_CBS_CC_STATE = 8 ;
+static const uint8_t P9N2_C_DBG_CBS_CC_STATE_LEN = 5 ;
+static const uint8_t P9N2_C_DBG_CBS_CC_SECURITY_DEBUG_MODE = 13 ;
+static const uint8_t P9N2_C_DBG_CBS_CC_PROTOCOL_ERROR = 14 ;
+static const uint8_t P9N2_C_DBG_CBS_CC_PCB_IDLE = 15 ;
+static const uint8_t P9N2_C_DBG_CBS_CC_CURRENT_OPCG_MODE = 16 ;
+static const uint8_t P9N2_C_DBG_CBS_CC_CURRENT_OPCG_MODE_LEN = 4 ;
+static const uint8_t P9N2_C_DBG_CBS_CC_LAST_OPCG_MODE = 20 ;
+static const uint8_t P9N2_C_DBG_CBS_CC_LAST_OPCG_MODE_LEN = 4 ;
+static const uint8_t P9N2_C_DBG_CBS_CC_PCB_ERROR = 24 ;
+static const uint8_t P9N2_C_DBG_CBS_CC_PARITY_ERROR = 25 ;
+static const uint8_t P9N2_C_DBG_CBS_CC_ERROR = 26 ;
+static const uint8_t P9N2_C_DBG_CBS_CC_CHIPLET_IS_ALIGNED = 27 ;
+static const uint8_t P9N2_C_DBG_CBS_CC_PCB_REQUEST_SINCE_RESET = 28 ;
+static const uint8_t P9N2_C_DBG_CBS_CC_PARANOIA_TEST_ENABLE_CHANGE = 29 ;
+static const uint8_t P9N2_C_DBG_CBS_CC_PARANOIA_VITL_CLKOFF_CHANGE = 30 ;
+static const uint8_t P9N2_C_DBG_CBS_CC_TP_TPFSI_ACK = 31 ;
+
+static const uint8_t P9N2_EQ_DBG_INST1_COND_REG_1_COND1_SEL_A = 0 ;
+static const uint8_t P9N2_EQ_DBG_INST1_COND_REG_1_COND1_SEL_A_LEN = 8 ;
+static const uint8_t P9N2_EQ_DBG_INST1_COND_REG_1_COND1_SEL_B = 8 ;
+static const uint8_t P9N2_EQ_DBG_INST1_COND_REG_1_COND1_SEL_B_LEN = 8 ;
+static const uint8_t P9N2_EQ_DBG_INST1_COND_REG_1_COND2_SEL_A = 16 ;
+static const uint8_t P9N2_EQ_DBG_INST1_COND_REG_1_COND2_SEL_A_LEN = 8 ;
+static const uint8_t P9N2_EQ_DBG_INST1_COND_REG_1_COND2_SEL_B = 24 ;
+static const uint8_t P9N2_EQ_DBG_INST1_COND_REG_1_COND2_SEL_B_LEN = 8 ;
+static const uint8_t P9N2_EQ_DBG_INST1_COND_REG_1_C1_INAROW_MODE = 32 ;
+static const uint8_t P9N2_EQ_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE1 = 33 ;
+static const uint8_t P9N2_EQ_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE1 = 34 ;
+static const uint8_t P9N2_EQ_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE1 = 35 ;
+static const uint8_t P9N2_EQ_DBG_INST1_COND_REG_1_UNUSED = 36 ;
+static const uint8_t P9N2_EQ_DBG_INST1_COND_REG_1_UNUSED_LEN = 3 ;
+static const uint8_t P9N2_EQ_DBG_INST1_COND_REG_1_C2_INAROW_MODE = 39 ;
+static const uint8_t P9N2_EQ_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE2 = 40 ;
+static const uint8_t P9N2_EQ_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE2 = 41 ;
+static const uint8_t P9N2_EQ_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE2 = 42 ;
+static const uint8_t P9N2_EQ_DBG_INST1_COND_REG_1_UNUSED_2 = 43 ;
+static const uint8_t P9N2_EQ_DBG_INST1_COND_REG_1_UNUSED_2_LEN = 3 ;
+static const uint8_t P9N2_EQ_DBG_INST1_COND_REG_1_COND3_ENABLE_RESET = 46 ;
+static const uint8_t P9N2_EQ_DBG_INST1_COND_REG_1_EXACT_TO_MODE = 47 ;
+static const uint8_t P9N2_EQ_DBG_INST1_COND_REG_1_RESET_C2TIMER_ON_C1 = 48 ;
+static const uint8_t P9N2_EQ_DBG_INST1_COND_REG_1_RESET_C3_ON_C0 = 49 ;
+static const uint8_t P9N2_EQ_DBG_INST1_COND_REG_1_SLOW_TO_MODE = 50 ;
+static const uint8_t P9N2_EQ_DBG_INST1_COND_REG_1_EXACT_RESET_C3_ON_TO = 51 ;
+static const uint8_t P9N2_EQ_DBG_INST1_COND_REG_1_C1_COUNT_LT = 52 ;
+static const uint8_t P9N2_EQ_DBG_INST1_COND_REG_1_C1_COUNT_LT_LEN = 4 ;
+static const uint8_t P9N2_EQ_DBG_INST1_COND_REG_1_C2_COUNT_LT = 56 ;
+static const uint8_t P9N2_EQ_DBG_INST1_COND_REG_1_C2_COUNT_LT_LEN = 4 ;
+static const uint8_t P9N2_EQ_DBG_INST1_COND_REG_1_RESET_C3_SELECT = 60 ;
+static const uint8_t P9N2_EQ_DBG_INST1_COND_REG_1_RESET_C3_SELECT_LEN = 3 ;
+
+static const uint8_t P9N2_EX_DBG_INST1_COND_REG_1_COND1_SEL_A = 0 ;
+static const uint8_t P9N2_EX_DBG_INST1_COND_REG_1_COND1_SEL_A_LEN = 8 ;
+static const uint8_t P9N2_EX_DBG_INST1_COND_REG_1_COND1_SEL_B = 8 ;
+static const uint8_t P9N2_EX_DBG_INST1_COND_REG_1_COND1_SEL_B_LEN = 8 ;
+static const uint8_t P9N2_EX_DBG_INST1_COND_REG_1_COND2_SEL_A = 16 ;
+static const uint8_t P9N2_EX_DBG_INST1_COND_REG_1_COND2_SEL_A_LEN = 8 ;
+static const uint8_t P9N2_EX_DBG_INST1_COND_REG_1_COND2_SEL_B = 24 ;
+static const uint8_t P9N2_EX_DBG_INST1_COND_REG_1_COND2_SEL_B_LEN = 8 ;
+static const uint8_t P9N2_EX_DBG_INST1_COND_REG_1_C1_INAROW_MODE = 32 ;
+static const uint8_t P9N2_EX_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE1 = 33 ;
+static const uint8_t P9N2_EX_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE1 = 34 ;
+static const uint8_t P9N2_EX_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE1 = 35 ;
+static const uint8_t P9N2_EX_DBG_INST1_COND_REG_1_UNUSED = 36 ;
+static const uint8_t P9N2_EX_DBG_INST1_COND_REG_1_UNUSED_LEN = 3 ;
+static const uint8_t P9N2_EX_DBG_INST1_COND_REG_1_C2_INAROW_MODE = 39 ;
+static const uint8_t P9N2_EX_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE2 = 40 ;
+static const uint8_t P9N2_EX_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE2 = 41 ;
+static const uint8_t P9N2_EX_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE2 = 42 ;
+static const uint8_t P9N2_EX_DBG_INST1_COND_REG_1_UNUSED_2 = 43 ;
+static const uint8_t P9N2_EX_DBG_INST1_COND_REG_1_UNUSED_2_LEN = 3 ;
+static const uint8_t P9N2_EX_DBG_INST1_COND_REG_1_COND3_ENABLE_RESET = 46 ;
+static const uint8_t P9N2_EX_DBG_INST1_COND_REG_1_EXACT_TO_MODE = 47 ;
+static const uint8_t P9N2_EX_DBG_INST1_COND_REG_1_RESET_C2TIMER_ON_C1 = 48 ;
+static const uint8_t P9N2_EX_DBG_INST1_COND_REG_1_RESET_C3_ON_C0 = 49 ;
+static const uint8_t P9N2_EX_DBG_INST1_COND_REG_1_SLOW_TO_MODE = 50 ;
+static const uint8_t P9N2_EX_DBG_INST1_COND_REG_1_EXACT_RESET_C3_ON_TO = 51 ;
+static const uint8_t P9N2_EX_DBG_INST1_COND_REG_1_C1_COUNT_LT = 52 ;
+static const uint8_t P9N2_EX_DBG_INST1_COND_REG_1_C1_COUNT_LT_LEN = 4 ;
+static const uint8_t P9N2_EX_DBG_INST1_COND_REG_1_C2_COUNT_LT = 56 ;
+static const uint8_t P9N2_EX_DBG_INST1_COND_REG_1_C2_COUNT_LT_LEN = 4 ;
+static const uint8_t P9N2_EX_DBG_INST1_COND_REG_1_RESET_C3_SELECT = 60 ;
+static const uint8_t P9N2_EX_DBG_INST1_COND_REG_1_RESET_C3_SELECT_LEN = 3 ;
+
+static const uint8_t P9N2_C_DBG_INST1_COND_REG_1_COND1_SEL_A = 0 ;
+static const uint8_t P9N2_C_DBG_INST1_COND_REG_1_COND1_SEL_A_LEN = 8 ;
+static const uint8_t P9N2_C_DBG_INST1_COND_REG_1_COND1_SEL_B = 8 ;
+static const uint8_t P9N2_C_DBG_INST1_COND_REG_1_COND1_SEL_B_LEN = 8 ;
+static const uint8_t P9N2_C_DBG_INST1_COND_REG_1_COND2_SEL_A = 16 ;
+static const uint8_t P9N2_C_DBG_INST1_COND_REG_1_COND2_SEL_A_LEN = 8 ;
+static const uint8_t P9N2_C_DBG_INST1_COND_REG_1_COND2_SEL_B = 24 ;
+static const uint8_t P9N2_C_DBG_INST1_COND_REG_1_COND2_SEL_B_LEN = 8 ;
+static const uint8_t P9N2_C_DBG_INST1_COND_REG_1_C1_INAROW_MODE = 32 ;
+static const uint8_t P9N2_C_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE1 = 33 ;
+static const uint8_t P9N2_C_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE1 = 34 ;
+static const uint8_t P9N2_C_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE1 = 35 ;
+static const uint8_t P9N2_C_DBG_INST1_COND_REG_1_UNUSED = 36 ;
+static const uint8_t P9N2_C_DBG_INST1_COND_REG_1_UNUSED_LEN = 3 ;
+static const uint8_t P9N2_C_DBG_INST1_COND_REG_1_C2_INAROW_MODE = 39 ;
+static const uint8_t P9N2_C_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE2 = 40 ;
+static const uint8_t P9N2_C_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE2 = 41 ;
+static const uint8_t P9N2_C_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE2 = 42 ;
+static const uint8_t P9N2_C_DBG_INST1_COND_REG_1_UNUSED_2 = 43 ;
+static const uint8_t P9N2_C_DBG_INST1_COND_REG_1_UNUSED_2_LEN = 3 ;
+static const uint8_t P9N2_C_DBG_INST1_COND_REG_1_COND3_ENABLE_RESET = 46 ;
+static const uint8_t P9N2_C_DBG_INST1_COND_REG_1_EXACT_TO_MODE = 47 ;
+static const uint8_t P9N2_C_DBG_INST1_COND_REG_1_RESET_C2TIMER_ON_C1 = 48 ;
+static const uint8_t P9N2_C_DBG_INST1_COND_REG_1_RESET_C3_ON_C0 = 49 ;
+static const uint8_t P9N2_C_DBG_INST1_COND_REG_1_SLOW_TO_MODE = 50 ;
+static const uint8_t P9N2_C_DBG_INST1_COND_REG_1_EXACT_RESET_C3_ON_TO = 51 ;
+static const uint8_t P9N2_C_DBG_INST1_COND_REG_1_C1_COUNT_LT = 52 ;
+static const uint8_t P9N2_C_DBG_INST1_COND_REG_1_C1_COUNT_LT_LEN = 4 ;
+static const uint8_t P9N2_C_DBG_INST1_COND_REG_1_C2_COUNT_LT = 56 ;
+static const uint8_t P9N2_C_DBG_INST1_COND_REG_1_C2_COUNT_LT_LEN = 4 ;
+static const uint8_t P9N2_C_DBG_INST1_COND_REG_1_RESET_C3_SELECT = 60 ;
+static const uint8_t P9N2_C_DBG_INST1_COND_REG_1_RESET_C3_SELECT_LEN = 3 ;
+
+static const uint8_t P9N2_EQ_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A = 0 ;
+static const uint8_t P9N2_EQ_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN = 5 ;
+static const uint8_t P9N2_EQ_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B = 5 ;
+static const uint8_t P9N2_EQ_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN = 5 ;
+static const uint8_t P9N2_EQ_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A = 10 ;
+static const uint8_t P9N2_EQ_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN = 5 ;
+static const uint8_t P9N2_EQ_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B = 15 ;
+static const uint8_t P9N2_EQ_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN = 5 ;
+static const uint8_t P9N2_EQ_DBG_INST1_COND_REG_2_TO_CMP_LT = 20 ;
+static const uint8_t P9N2_EQ_DBG_INST1_COND_REG_2_TO_CMP_LT_LEN = 24 ;
+
+static const uint8_t P9N2_EX_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A = 0 ;
+static const uint8_t P9N2_EX_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN = 5 ;
+static const uint8_t P9N2_EX_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B = 5 ;
+static const uint8_t P9N2_EX_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN = 5 ;
+static const uint8_t P9N2_EX_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A = 10 ;
+static const uint8_t P9N2_EX_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN = 5 ;
+static const uint8_t P9N2_EX_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B = 15 ;
+static const uint8_t P9N2_EX_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN = 5 ;
+static const uint8_t P9N2_EX_DBG_INST1_COND_REG_2_TO_CMP_LT = 20 ;
+static const uint8_t P9N2_EX_DBG_INST1_COND_REG_2_TO_CMP_LT_LEN = 24 ;
+
+static const uint8_t P9N2_C_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A = 0 ;
+static const uint8_t P9N2_C_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN = 5 ;
+static const uint8_t P9N2_C_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B = 5 ;
+static const uint8_t P9N2_C_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN = 5 ;
+static const uint8_t P9N2_C_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A = 10 ;
+static const uint8_t P9N2_C_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN = 5 ;
+static const uint8_t P9N2_C_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B = 15 ;
+static const uint8_t P9N2_C_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN = 5 ;
+static const uint8_t P9N2_C_DBG_INST1_COND_REG_2_TO_CMP_LT = 20 ;
+static const uint8_t P9N2_C_DBG_INST1_COND_REG_2_TO_CMP_LT_LEN = 24 ;
+
+static const uint8_t P9N2_EQ_DBG_INST2_COND_REG_1_COND1_SEL_A = 0 ;
+static const uint8_t P9N2_EQ_DBG_INST2_COND_REG_1_COND1_SEL_A_LEN = 8 ;
+static const uint8_t P9N2_EQ_DBG_INST2_COND_REG_1_COND1_SEL_B = 8 ;
+static const uint8_t P9N2_EQ_DBG_INST2_COND_REG_1_COND1_SEL_B_LEN = 8 ;
+static const uint8_t P9N2_EQ_DBG_INST2_COND_REG_1_COND2_SEL_A = 16 ;
+static const uint8_t P9N2_EQ_DBG_INST2_COND_REG_1_COND2_SEL_A_LEN = 8 ;
+static const uint8_t P9N2_EQ_DBG_INST2_COND_REG_1_COND2_SEL_B = 24 ;
+static const uint8_t P9N2_EQ_DBG_INST2_COND_REG_1_COND2_SEL_B_LEN = 8 ;
+static const uint8_t P9N2_EQ_DBG_INST2_COND_REG_1_C1_INAROW_MODE = 32 ;
+static const uint8_t P9N2_EQ_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE1 = 33 ;
+static const uint8_t P9N2_EQ_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE1 = 34 ;
+static const uint8_t P9N2_EQ_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE1 = 35 ;
+static const uint8_t P9N2_EQ_DBG_INST2_COND_REG_1_UNUSED = 36 ;
+static const uint8_t P9N2_EQ_DBG_INST2_COND_REG_1_UNUSED_LEN = 3 ;
+static const uint8_t P9N2_EQ_DBG_INST2_COND_REG_1_C2_INAROW_MODE = 39 ;
+static const uint8_t P9N2_EQ_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE2 = 40 ;
+static const uint8_t P9N2_EQ_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE2 = 41 ;
+static const uint8_t P9N2_EQ_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE2 = 42 ;
+static const uint8_t P9N2_EQ_DBG_INST2_COND_REG_1_UNUSED_2 = 43 ;
+static const uint8_t P9N2_EQ_DBG_INST2_COND_REG_1_UNUSED_2_LEN = 3 ;
+static const uint8_t P9N2_EQ_DBG_INST2_COND_REG_1_COND3_ENABLE_RESET = 46 ;
+static const uint8_t P9N2_EQ_DBG_INST2_COND_REG_1_EXACT_TO_MODE = 47 ;
+static const uint8_t P9N2_EQ_DBG_INST2_COND_REG_1_RESET_C2TIMER_ON_C1 = 48 ;
+static const uint8_t P9N2_EQ_DBG_INST2_COND_REG_1_RESET_C3_ON_C0 = 49 ;
+static const uint8_t P9N2_EQ_DBG_INST2_COND_REG_1_SLOW_TO_MODE = 50 ;
+static const uint8_t P9N2_EQ_DBG_INST2_COND_REG_1_EXACT_RESET_C3_ON_TO = 51 ;
+static const uint8_t P9N2_EQ_DBG_INST2_COND_REG_1_C1_COUNT_LT = 52 ;
+static const uint8_t P9N2_EQ_DBG_INST2_COND_REG_1_C1_COUNT_LT_LEN = 4 ;
+static const uint8_t P9N2_EQ_DBG_INST2_COND_REG_1_C2_COUNT_LT = 56 ;
+static const uint8_t P9N2_EQ_DBG_INST2_COND_REG_1_C2_COUNT_LT_LEN = 4 ;
+static const uint8_t P9N2_EQ_DBG_INST2_COND_REG_1_RESET_C3_SELECT = 60 ;
+static const uint8_t P9N2_EQ_DBG_INST2_COND_REG_1_RESET_C3_SELECT_LEN = 3 ;
+
+static const uint8_t P9N2_EX_DBG_INST2_COND_REG_1_COND1_SEL_A = 0 ;
+static const uint8_t P9N2_EX_DBG_INST2_COND_REG_1_COND1_SEL_A_LEN = 8 ;
+static const uint8_t P9N2_EX_DBG_INST2_COND_REG_1_COND1_SEL_B = 8 ;
+static const uint8_t P9N2_EX_DBG_INST2_COND_REG_1_COND1_SEL_B_LEN = 8 ;
+static const uint8_t P9N2_EX_DBG_INST2_COND_REG_1_COND2_SEL_A = 16 ;
+static const uint8_t P9N2_EX_DBG_INST2_COND_REG_1_COND2_SEL_A_LEN = 8 ;
+static const uint8_t P9N2_EX_DBG_INST2_COND_REG_1_COND2_SEL_B = 24 ;
+static const uint8_t P9N2_EX_DBG_INST2_COND_REG_1_COND2_SEL_B_LEN = 8 ;
+static const uint8_t P9N2_EX_DBG_INST2_COND_REG_1_C1_INAROW_MODE = 32 ;
+static const uint8_t P9N2_EX_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE1 = 33 ;
+static const uint8_t P9N2_EX_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE1 = 34 ;
+static const uint8_t P9N2_EX_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE1 = 35 ;
+static const uint8_t P9N2_EX_DBG_INST2_COND_REG_1_UNUSED = 36 ;
+static const uint8_t P9N2_EX_DBG_INST2_COND_REG_1_UNUSED_LEN = 3 ;
+static const uint8_t P9N2_EX_DBG_INST2_COND_REG_1_C2_INAROW_MODE = 39 ;
+static const uint8_t P9N2_EX_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE2 = 40 ;
+static const uint8_t P9N2_EX_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE2 = 41 ;
+static const uint8_t P9N2_EX_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE2 = 42 ;
+static const uint8_t P9N2_EX_DBG_INST2_COND_REG_1_UNUSED_2 = 43 ;
+static const uint8_t P9N2_EX_DBG_INST2_COND_REG_1_UNUSED_2_LEN = 3 ;
+static const uint8_t P9N2_EX_DBG_INST2_COND_REG_1_COND3_ENABLE_RESET = 46 ;
+static const uint8_t P9N2_EX_DBG_INST2_COND_REG_1_EXACT_TO_MODE = 47 ;
+static const uint8_t P9N2_EX_DBG_INST2_COND_REG_1_RESET_C2TIMER_ON_C1 = 48 ;
+static const uint8_t P9N2_EX_DBG_INST2_COND_REG_1_RESET_C3_ON_C0 = 49 ;
+static const uint8_t P9N2_EX_DBG_INST2_COND_REG_1_SLOW_TO_MODE = 50 ;
+static const uint8_t P9N2_EX_DBG_INST2_COND_REG_1_EXACT_RESET_C3_ON_TO = 51 ;
+static const uint8_t P9N2_EX_DBG_INST2_COND_REG_1_C1_COUNT_LT = 52 ;
+static const uint8_t P9N2_EX_DBG_INST2_COND_REG_1_C1_COUNT_LT_LEN = 4 ;
+static const uint8_t P9N2_EX_DBG_INST2_COND_REG_1_C2_COUNT_LT = 56 ;
+static const uint8_t P9N2_EX_DBG_INST2_COND_REG_1_C2_COUNT_LT_LEN = 4 ;
+static const uint8_t P9N2_EX_DBG_INST2_COND_REG_1_RESET_C3_SELECT = 60 ;
+static const uint8_t P9N2_EX_DBG_INST2_COND_REG_1_RESET_C3_SELECT_LEN = 3 ;
+
+static const uint8_t P9N2_C_DBG_INST2_COND_REG_1_COND1_SEL_A = 0 ;
+static const uint8_t P9N2_C_DBG_INST2_COND_REG_1_COND1_SEL_A_LEN = 8 ;
+static const uint8_t P9N2_C_DBG_INST2_COND_REG_1_COND1_SEL_B = 8 ;
+static const uint8_t P9N2_C_DBG_INST2_COND_REG_1_COND1_SEL_B_LEN = 8 ;
+static const uint8_t P9N2_C_DBG_INST2_COND_REG_1_COND2_SEL_A = 16 ;
+static const uint8_t P9N2_C_DBG_INST2_COND_REG_1_COND2_SEL_A_LEN = 8 ;
+static const uint8_t P9N2_C_DBG_INST2_COND_REG_1_COND2_SEL_B = 24 ;
+static const uint8_t P9N2_C_DBG_INST2_COND_REG_1_COND2_SEL_B_LEN = 8 ;
+static const uint8_t P9N2_C_DBG_INST2_COND_REG_1_C1_INAROW_MODE = 32 ;
+static const uint8_t P9N2_C_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE1 = 33 ;
+static const uint8_t P9N2_C_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE1 = 34 ;
+static const uint8_t P9N2_C_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE1 = 35 ;
+static const uint8_t P9N2_C_DBG_INST2_COND_REG_1_UNUSED = 36 ;
+static const uint8_t P9N2_C_DBG_INST2_COND_REG_1_UNUSED_LEN = 3 ;
+static const uint8_t P9N2_C_DBG_INST2_COND_REG_1_C2_INAROW_MODE = 39 ;
+static const uint8_t P9N2_C_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE2 = 40 ;
+static const uint8_t P9N2_C_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE2 = 41 ;
+static const uint8_t P9N2_C_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE2 = 42 ;
+static const uint8_t P9N2_C_DBG_INST2_COND_REG_1_UNUSED_2 = 43 ;
+static const uint8_t P9N2_C_DBG_INST2_COND_REG_1_UNUSED_2_LEN = 3 ;
+static const uint8_t P9N2_C_DBG_INST2_COND_REG_1_COND3_ENABLE_RESET = 46 ;
+static const uint8_t P9N2_C_DBG_INST2_COND_REG_1_EXACT_TO_MODE = 47 ;
+static const uint8_t P9N2_C_DBG_INST2_COND_REG_1_RESET_C2TIMER_ON_C1 = 48 ;
+static const uint8_t P9N2_C_DBG_INST2_COND_REG_1_RESET_C3_ON_C0 = 49 ;
+static const uint8_t P9N2_C_DBG_INST2_COND_REG_1_SLOW_TO_MODE = 50 ;
+static const uint8_t P9N2_C_DBG_INST2_COND_REG_1_EXACT_RESET_C3_ON_TO = 51 ;
+static const uint8_t P9N2_C_DBG_INST2_COND_REG_1_C1_COUNT_LT = 52 ;
+static const uint8_t P9N2_C_DBG_INST2_COND_REG_1_C1_COUNT_LT_LEN = 4 ;
+static const uint8_t P9N2_C_DBG_INST2_COND_REG_1_C2_COUNT_LT = 56 ;
+static const uint8_t P9N2_C_DBG_INST2_COND_REG_1_C2_COUNT_LT_LEN = 4 ;
+static const uint8_t P9N2_C_DBG_INST2_COND_REG_1_RESET_C3_SELECT = 60 ;
+static const uint8_t P9N2_C_DBG_INST2_COND_REG_1_RESET_C3_SELECT_LEN = 3 ;
+
+static const uint8_t P9N2_EQ_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A = 0 ;
+static const uint8_t P9N2_EQ_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN = 5 ;
+static const uint8_t P9N2_EQ_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B = 5 ;
+static const uint8_t P9N2_EQ_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN = 5 ;
+static const uint8_t P9N2_EQ_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A = 10 ;
+static const uint8_t P9N2_EQ_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN = 5 ;
+static const uint8_t P9N2_EQ_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B = 15 ;
+static const uint8_t P9N2_EQ_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN = 5 ;
+static const uint8_t P9N2_EQ_DBG_INST2_COND_REG_2_TO_CMP_LT = 20 ;
+static const uint8_t P9N2_EQ_DBG_INST2_COND_REG_2_TO_CMP_LT_LEN = 24 ;
+
+static const uint8_t P9N2_EX_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A = 0 ;
+static const uint8_t P9N2_EX_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN = 5 ;
+static const uint8_t P9N2_EX_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B = 5 ;
+static const uint8_t P9N2_EX_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN = 5 ;
+static const uint8_t P9N2_EX_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A = 10 ;
+static const uint8_t P9N2_EX_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN = 5 ;
+static const uint8_t P9N2_EX_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B = 15 ;
+static const uint8_t P9N2_EX_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN = 5 ;
+static const uint8_t P9N2_EX_DBG_INST2_COND_REG_2_TO_CMP_LT = 20 ;
+static const uint8_t P9N2_EX_DBG_INST2_COND_REG_2_TO_CMP_LT_LEN = 24 ;
+
+static const uint8_t P9N2_C_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A = 0 ;
+static const uint8_t P9N2_C_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN = 5 ;
+static const uint8_t P9N2_C_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B = 5 ;
+static const uint8_t P9N2_C_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN = 5 ;
+static const uint8_t P9N2_C_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A = 10 ;
+static const uint8_t P9N2_C_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN = 5 ;
+static const uint8_t P9N2_C_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B = 15 ;
+static const uint8_t P9N2_C_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN = 5 ;
+static const uint8_t P9N2_C_DBG_INST2_COND_REG_2_TO_CMP_LT = 20 ;
+static const uint8_t P9N2_C_DBG_INST2_COND_REG_2_TO_CMP_LT_LEN = 24 ;
+
+static const uint8_t P9N2_EQ_DBG_MODE_REG_GLB_BRCST = 0 ;
+static const uint8_t P9N2_EQ_DBG_MODE_REG_GLB_BRCST_LEN = 3 ;
+static const uint8_t P9N2_EQ_DBG_MODE_REG_TRACE_SEL = 3 ;
+static const uint8_t P9N2_EQ_DBG_MODE_REG_TRACE_SEL_LEN = 3 ;
+static const uint8_t P9N2_EQ_DBG_MODE_REG_TRIG_SEL = 6 ;
+static const uint8_t P9N2_EQ_DBG_MODE_REG_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_EQ_DBG_MODE_REG_STOP_ON_XSTOP_SELECTION = 8 ;
+static const uint8_t P9N2_EQ_DBG_MODE_REG_STOP_ON_RECOV_ERR_SELECTION = 9 ;
+static const uint8_t P9N2_EQ_DBG_MODE_REG_STOP_ON_SPATTN_SELECTION = 10 ;
+static const uint8_t P9N2_EQ_DBG_MODE_REG_FREEZE_SEL = 11 ;
+static const uint8_t P9N2_EQ_DBG_MODE_REG_SYNC_BRCST = 12 ;
+static const uint8_t P9N2_EQ_DBG_MODE_REG_SYNC_BRCST_LEN = 2 ;
+
+static const uint8_t P9N2_EX_DBG_MODE_REG_GLB_BRCST = 0 ;
+static const uint8_t P9N2_EX_DBG_MODE_REG_GLB_BRCST_LEN = 3 ;
+static const uint8_t P9N2_EX_DBG_MODE_REG_TRACE_SEL = 3 ;
+static const uint8_t P9N2_EX_DBG_MODE_REG_TRACE_SEL_LEN = 3 ;
+static const uint8_t P9N2_EX_DBG_MODE_REG_TRIG_SEL = 6 ;
+static const uint8_t P9N2_EX_DBG_MODE_REG_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_EX_DBG_MODE_REG_STOP_ON_XSTOP_SELECTION = 8 ;
+static const uint8_t P9N2_EX_DBG_MODE_REG_STOP_ON_RECOV_ERR_SELECTION = 9 ;
+static const uint8_t P9N2_EX_DBG_MODE_REG_STOP_ON_SPATTN_SELECTION = 10 ;
+static const uint8_t P9N2_EX_DBG_MODE_REG_FREEZE_SEL = 11 ;
+static const uint8_t P9N2_EX_DBG_MODE_REG_SYNC_BRCST = 12 ;
+static const uint8_t P9N2_EX_DBG_MODE_REG_SYNC_BRCST_LEN = 2 ;
+
+static const uint8_t P9N2_C_DBG_MODE_REG_GLB_BRCST = 0 ;
+static const uint8_t P9N2_C_DBG_MODE_REG_GLB_BRCST_LEN = 3 ;
+static const uint8_t P9N2_C_DBG_MODE_REG_TRACE_SEL = 3 ;
+static const uint8_t P9N2_C_DBG_MODE_REG_TRACE_SEL_LEN = 3 ;
+static const uint8_t P9N2_C_DBG_MODE_REG_TRIG_SEL = 6 ;
+static const uint8_t P9N2_C_DBG_MODE_REG_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_C_DBG_MODE_REG_STOP_ON_XSTOP_SELECTION = 8 ;
+static const uint8_t P9N2_C_DBG_MODE_REG_STOP_ON_RECOV_ERR_SELECTION = 9 ;
+static const uint8_t P9N2_C_DBG_MODE_REG_STOP_ON_SPATTN_SELECTION = 10 ;
+static const uint8_t P9N2_C_DBG_MODE_REG_FREEZE_SEL = 11 ;
+static const uint8_t P9N2_C_DBG_MODE_REG_SYNC_BRCST = 12 ;
+static const uint8_t P9N2_C_DBG_MODE_REG_SYNC_BRCST_LEN = 2 ;
+
+static const uint8_t P9N2_EQ_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE = 0 ;
+static const uint8_t P9N2_EQ_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE_LEN = 16 ;
+static const uint8_t P9N2_EQ_DBG_TRACE_MODE_REG_2_IMM_FREEZE = 16 ;
+static const uint8_t P9N2_EQ_DBG_TRACE_MODE_REG_2_STOP_ON_ERR = 17 ;
+static const uint8_t P9N2_EQ_DBG_TRACE_MODE_REG_2_BANK_ON_RUNN_MATCH = 18 ;
+static const uint8_t P9N2_EQ_DBG_TRACE_MODE_REG_2_FORCE_TEST = 19 ;
+static const uint8_t P9N2_EQ_DBG_TRACE_MODE_REG_2_ACCUM_HIST = 20 ;
+static const uint8_t P9N2_EQ_DBG_TRACE_MODE_REG_2_FRZ_COUNT_ON_FRZ = 21 ;
+
+static const uint8_t P9N2_EX_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE = 0 ;
+static const uint8_t P9N2_EX_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE_LEN = 16 ;
+static const uint8_t P9N2_EX_DBG_TRACE_MODE_REG_2_IMM_FREEZE = 16 ;
+static const uint8_t P9N2_EX_DBG_TRACE_MODE_REG_2_STOP_ON_ERR = 17 ;
+static const uint8_t P9N2_EX_DBG_TRACE_MODE_REG_2_BANK_ON_RUNN_MATCH = 18 ;
+static const uint8_t P9N2_EX_DBG_TRACE_MODE_REG_2_FORCE_TEST = 19 ;
+static const uint8_t P9N2_EX_DBG_TRACE_MODE_REG_2_ACCUM_HIST = 20 ;
+static const uint8_t P9N2_EX_DBG_TRACE_MODE_REG_2_FRZ_COUNT_ON_FRZ = 21 ;
+
+static const uint8_t P9N2_C_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE = 0 ;
+static const uint8_t P9N2_C_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE_LEN = 16 ;
+static const uint8_t P9N2_C_DBG_TRACE_MODE_REG_2_IMM_FREEZE = 16 ;
+static const uint8_t P9N2_C_DBG_TRACE_MODE_REG_2_STOP_ON_ERR = 17 ;
+static const uint8_t P9N2_C_DBG_TRACE_MODE_REG_2_BANK_ON_RUNN_MATCH = 18 ;
+static const uint8_t P9N2_C_DBG_TRACE_MODE_REG_2_FORCE_TEST = 19 ;
+static const uint8_t P9N2_C_DBG_TRACE_MODE_REG_2_ACCUM_HIST = 20 ;
+static const uint8_t P9N2_C_DBG_TRACE_MODE_REG_2_FRZ_COUNT_ON_FRZ = 21 ;
+
+static const uint8_t P9N2_EQ_DBG_TRACE_REG_0_INST1_COND3_ENABLE = 0 ;
+static const uint8_t P9N2_EQ_DBG_TRACE_REG_0_INST2_COND3_ENABLE = 1 ;
+static const uint8_t P9N2_EQ_DBG_TRACE_REG_0_INST3_COND3_ENABLE = 2 ;
+static const uint8_t P9N2_EQ_DBG_TRACE_REG_0_INST4_COND3_ENABLE = 3 ;
+static const uint8_t P9N2_EQ_DBG_TRACE_REG_0_INST1_SLOW_LFSR_MODE = 4 ;
+static const uint8_t P9N2_EQ_DBG_TRACE_REG_0_INST2_SLOW_LFSR_MODE = 5 ;
+static const uint8_t P9N2_EQ_DBG_TRACE_REG_0_INST3_SLOW_LFSR_MODE = 6 ;
+static const uint8_t P9N2_EQ_DBG_TRACE_REG_0_INST4_SLOW_LFSR_MODE = 7 ;
+static const uint8_t P9N2_EQ_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL = 8 ;
+static const uint8_t P9N2_EQ_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_EQ_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL = 10 ;
+static const uint8_t P9N2_EQ_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_EQ_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL = 12 ;
+static const uint8_t P9N2_EQ_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_EQ_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL = 14 ;
+static const uint8_t P9N2_EQ_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_EQ_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL = 16 ;
+static const uint8_t P9N2_EQ_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_EQ_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL = 18 ;
+static const uint8_t P9N2_EQ_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_EQ_DBG_TRACE_REG_0_EXT_TRIG_ON_STOP = 32 ;
+static const uint8_t P9N2_EQ_DBG_TRACE_REG_0_EXT_TRIG_ON_FREEZE = 33 ;
+static const uint8_t P9N2_EQ_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL = 34 ;
+static const uint8_t P9N2_EQ_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL_LEN = 5 ;
+static const uint8_t P9N2_EQ_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL = 39 ;
+static const uint8_t P9N2_EQ_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL_LEN = 5 ;
+static const uint8_t P9N2_EQ_DBG_TRACE_REG_0_PC_TP_TRIG_SEL = 44 ;
+static const uint8_t P9N2_EQ_DBG_TRACE_REG_0_PC_TP_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_EQ_DBG_TRACE_REG_0_ARM_SEL = 46 ;
+static const uint8_t P9N2_EQ_DBG_TRACE_REG_0_ARM_SEL_LEN = 4 ;
+static const uint8_t P9N2_EQ_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL = 50 ;
+static const uint8_t P9N2_EQ_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL_LEN = 4 ;
+static const uint8_t P9N2_EQ_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL = 54 ;
+static const uint8_t P9N2_EQ_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL_LEN = 4 ;
+
+static const uint8_t P9N2_EX_DBG_TRACE_REG_0_INST1_COND3_ENABLE = 0 ;
+static const uint8_t P9N2_EX_DBG_TRACE_REG_0_INST2_COND3_ENABLE = 1 ;
+static const uint8_t P9N2_EX_DBG_TRACE_REG_0_INST3_COND3_ENABLE = 2 ;
+static const uint8_t P9N2_EX_DBG_TRACE_REG_0_INST4_COND3_ENABLE = 3 ;
+static const uint8_t P9N2_EX_DBG_TRACE_REG_0_INST1_SLOW_LFSR_MODE = 4 ;
+static const uint8_t P9N2_EX_DBG_TRACE_REG_0_INST2_SLOW_LFSR_MODE = 5 ;
+static const uint8_t P9N2_EX_DBG_TRACE_REG_0_INST3_SLOW_LFSR_MODE = 6 ;
+static const uint8_t P9N2_EX_DBG_TRACE_REG_0_INST4_SLOW_LFSR_MODE = 7 ;
+static const uint8_t P9N2_EX_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL = 8 ;
+static const uint8_t P9N2_EX_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_EX_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL = 10 ;
+static const uint8_t P9N2_EX_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_EX_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL = 12 ;
+static const uint8_t P9N2_EX_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_EX_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL = 14 ;
+static const uint8_t P9N2_EX_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_EX_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL = 16 ;
+static const uint8_t P9N2_EX_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_EX_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL = 18 ;
+static const uint8_t P9N2_EX_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_EX_DBG_TRACE_REG_0_EXT_TRIG_ON_STOP = 32 ;
+static const uint8_t P9N2_EX_DBG_TRACE_REG_0_EXT_TRIG_ON_FREEZE = 33 ;
+static const uint8_t P9N2_EX_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL = 34 ;
+static const uint8_t P9N2_EX_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL_LEN = 5 ;
+static const uint8_t P9N2_EX_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL = 39 ;
+static const uint8_t P9N2_EX_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL_LEN = 5 ;
+static const uint8_t P9N2_EX_DBG_TRACE_REG_0_PC_TP_TRIG_SEL = 44 ;
+static const uint8_t P9N2_EX_DBG_TRACE_REG_0_PC_TP_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_EX_DBG_TRACE_REG_0_ARM_SEL = 46 ;
+static const uint8_t P9N2_EX_DBG_TRACE_REG_0_ARM_SEL_LEN = 4 ;
+static const uint8_t P9N2_EX_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL = 50 ;
+static const uint8_t P9N2_EX_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL_LEN = 4 ;
+static const uint8_t P9N2_EX_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL = 54 ;
+static const uint8_t P9N2_EX_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL_LEN = 4 ;
+
+static const uint8_t P9N2_C_DBG_TRACE_REG_0_INST1_COND3_ENABLE = 0 ;
+static const uint8_t P9N2_C_DBG_TRACE_REG_0_INST2_COND3_ENABLE = 1 ;
+static const uint8_t P9N2_C_DBG_TRACE_REG_0_INST3_COND3_ENABLE = 2 ;
+static const uint8_t P9N2_C_DBG_TRACE_REG_0_INST4_COND3_ENABLE = 3 ;
+static const uint8_t P9N2_C_DBG_TRACE_REG_0_INST1_SLOW_LFSR_MODE = 4 ;
+static const uint8_t P9N2_C_DBG_TRACE_REG_0_INST2_SLOW_LFSR_MODE = 5 ;
+static const uint8_t P9N2_C_DBG_TRACE_REG_0_INST3_SLOW_LFSR_MODE = 6 ;
+static const uint8_t P9N2_C_DBG_TRACE_REG_0_INST4_SLOW_LFSR_MODE = 7 ;
+static const uint8_t P9N2_C_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL = 8 ;
+static const uint8_t P9N2_C_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_C_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL = 10 ;
+static const uint8_t P9N2_C_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_C_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL = 12 ;
+static const uint8_t P9N2_C_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_C_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL = 14 ;
+static const uint8_t P9N2_C_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_C_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL = 16 ;
+static const uint8_t P9N2_C_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_C_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL = 18 ;
+static const uint8_t P9N2_C_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_C_DBG_TRACE_REG_0_EXT_TRIG_ON_STOP = 32 ;
+static const uint8_t P9N2_C_DBG_TRACE_REG_0_EXT_TRIG_ON_FREEZE = 33 ;
+static const uint8_t P9N2_C_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL = 34 ;
+static const uint8_t P9N2_C_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL_LEN = 5 ;
+static const uint8_t P9N2_C_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL = 39 ;
+static const uint8_t P9N2_C_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL_LEN = 5 ;
+static const uint8_t P9N2_C_DBG_TRACE_REG_0_PC_TP_TRIG_SEL = 44 ;
+static const uint8_t P9N2_C_DBG_TRACE_REG_0_PC_TP_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_C_DBG_TRACE_REG_0_ARM_SEL = 46 ;
+static const uint8_t P9N2_C_DBG_TRACE_REG_0_ARM_SEL_LEN = 4 ;
+static const uint8_t P9N2_C_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL = 50 ;
+static const uint8_t P9N2_C_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL_LEN = 4 ;
+static const uint8_t P9N2_C_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL = 54 ;
+static const uint8_t P9N2_C_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL_LEN = 4 ;
+
+static const uint8_t P9N2_EQ_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO = 0 ;
+static const uint8_t P9N2_EQ_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO_LEN = 2 ;
+static const uint8_t P9N2_EQ_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO = 2 ;
+static const uint8_t P9N2_EQ_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO_LEN = 2 ;
+static const uint8_t P9N2_EQ_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO = 4 ;
+static const uint8_t P9N2_EQ_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO_LEN = 2 ;
+static const uint8_t P9N2_EQ_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO = 6 ;
+static const uint8_t P9N2_EQ_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO_LEN = 2 ;
+static const uint8_t P9N2_EQ_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO = 8 ;
+static const uint8_t P9N2_EQ_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO_LEN = 2 ;
+static const uint8_t P9N2_EQ_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO = 10 ;
+static const uint8_t P9N2_EQ_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO_LEN = 2 ;
+static const uint8_t P9N2_EQ_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_WAITN = 24 ;
+static const uint8_t P9N2_EQ_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_WAITN = 25 ;
+static const uint8_t P9N2_EQ_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_WAITN = 26 ;
+static const uint8_t P9N2_EQ_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_WAITN = 27 ;
+static const uint8_t P9N2_EQ_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_WAITN = 28 ;
+static const uint8_t P9N2_EQ_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_WAITN = 29 ;
+static const uint8_t P9N2_EQ_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_BANK = 36 ;
+static const uint8_t P9N2_EQ_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_BANK = 37 ;
+static const uint8_t P9N2_EQ_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_BANK = 38 ;
+static const uint8_t P9N2_EQ_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_BANK = 39 ;
+static const uint8_t P9N2_EQ_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_BANK = 40 ;
+static const uint8_t P9N2_EQ_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_BANK = 41 ;
+static const uint8_t P9N2_EQ_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT = 48 ;
+static const uint8_t P9N2_EQ_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT_LEN = 3 ;
+static const uint8_t P9N2_EQ_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_SELECTOR = 51 ;
+static const uint8_t P9N2_EQ_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT = 52 ;
+static const uint8_t P9N2_EQ_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT_LEN = 3 ;
+static const uint8_t P9N2_EQ_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_SELECTOR = 55 ;
+
+static const uint8_t P9N2_EX_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO = 0 ;
+static const uint8_t P9N2_EX_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO_LEN = 2 ;
+static const uint8_t P9N2_EX_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO = 2 ;
+static const uint8_t P9N2_EX_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO_LEN = 2 ;
+static const uint8_t P9N2_EX_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO = 4 ;
+static const uint8_t P9N2_EX_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO_LEN = 2 ;
+static const uint8_t P9N2_EX_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO = 6 ;
+static const uint8_t P9N2_EX_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO_LEN = 2 ;
+static const uint8_t P9N2_EX_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO = 8 ;
+static const uint8_t P9N2_EX_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO_LEN = 2 ;
+static const uint8_t P9N2_EX_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO = 10 ;
+static const uint8_t P9N2_EX_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO_LEN = 2 ;
+static const uint8_t P9N2_EX_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_WAITN = 24 ;
+static const uint8_t P9N2_EX_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_WAITN = 25 ;
+static const uint8_t P9N2_EX_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_WAITN = 26 ;
+static const uint8_t P9N2_EX_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_WAITN = 27 ;
+static const uint8_t P9N2_EX_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_WAITN = 28 ;
+static const uint8_t P9N2_EX_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_WAITN = 29 ;
+static const uint8_t P9N2_EX_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_BANK = 36 ;
+static const uint8_t P9N2_EX_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_BANK = 37 ;
+static const uint8_t P9N2_EX_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_BANK = 38 ;
+static const uint8_t P9N2_EX_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_BANK = 39 ;
+static const uint8_t P9N2_EX_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_BANK = 40 ;
+static const uint8_t P9N2_EX_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_BANK = 41 ;
+static const uint8_t P9N2_EX_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT = 48 ;
+static const uint8_t P9N2_EX_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT_LEN = 3 ;
+static const uint8_t P9N2_EX_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_SELECTOR = 51 ;
+static const uint8_t P9N2_EX_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT = 52 ;
+static const uint8_t P9N2_EX_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT_LEN = 3 ;
+static const uint8_t P9N2_EX_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_SELECTOR = 55 ;
+
+static const uint8_t P9N2_C_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO = 0 ;
+static const uint8_t P9N2_C_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO_LEN = 2 ;
+static const uint8_t P9N2_C_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO = 2 ;
+static const uint8_t P9N2_C_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO_LEN = 2 ;
+static const uint8_t P9N2_C_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO = 4 ;
+static const uint8_t P9N2_C_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO_LEN = 2 ;
+static const uint8_t P9N2_C_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO = 6 ;
+static const uint8_t P9N2_C_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO_LEN = 2 ;
+static const uint8_t P9N2_C_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO = 8 ;
+static const uint8_t P9N2_C_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO_LEN = 2 ;
+static const uint8_t P9N2_C_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO = 10 ;
+static const uint8_t P9N2_C_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO_LEN = 2 ;
+static const uint8_t P9N2_C_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_WAITN = 24 ;
+static const uint8_t P9N2_C_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_WAITN = 25 ;
+static const uint8_t P9N2_C_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_WAITN = 26 ;
+static const uint8_t P9N2_C_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_WAITN = 27 ;
+static const uint8_t P9N2_C_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_WAITN = 28 ;
+static const uint8_t P9N2_C_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_WAITN = 29 ;
+static const uint8_t P9N2_C_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_BANK = 36 ;
+static const uint8_t P9N2_C_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_BANK = 37 ;
+static const uint8_t P9N2_C_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_BANK = 38 ;
+static const uint8_t P9N2_C_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_BANK = 39 ;
+static const uint8_t P9N2_C_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_BANK = 40 ;
+static const uint8_t P9N2_C_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_BANK = 41 ;
+static const uint8_t P9N2_C_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT = 48 ;
+static const uint8_t P9N2_C_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT_LEN = 3 ;
+static const uint8_t P9N2_C_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_SELECTOR = 51 ;
+static const uint8_t P9N2_C_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT = 52 ;
+static const uint8_t P9N2_C_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT_LEN = 3 ;
+static const uint8_t P9N2_C_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_SELECTOR = 55 ;
+
+static const uint8_t P9N2_EQ_DEBUG_TRACE_CONTROL_SCOM_TRACE_START = 0 ;
+static const uint8_t P9N2_EQ_DEBUG_TRACE_CONTROL_SCOM_TRACE_STOP = 1 ;
+static const uint8_t P9N2_EQ_DEBUG_TRACE_CONTROL_SCOM_TRACE_RESET = 2 ;
+
+static const uint8_t P9N2_EX_DEBUG_TRACE_CONTROL_SCOM_TRACE_START = 0 ;
+static const uint8_t P9N2_EX_DEBUG_TRACE_CONTROL_SCOM_TRACE_STOP = 1 ;
+static const uint8_t P9N2_EX_DEBUG_TRACE_CONTROL_SCOM_TRACE_RESET = 2 ;
+
+static const uint8_t P9N2_C_DEBUG_TRACE_CONTROL_SCOM_TRACE_START = 0 ;
+static const uint8_t P9N2_C_DEBUG_TRACE_CONTROL_SCOM_TRACE_STOP = 1 ;
+static const uint8_t P9N2_C_DEBUG_TRACE_CONTROL_SCOM_TRACE_RESET = 2 ;
+
+static const uint8_t P9N2_EX_L2_DIRECT_CONTROLS_DC_T0_CLEAR_MAINT = 3 ;
+static const uint8_t P9N2_EX_L2_DIRECT_CONTROLS_DC_T0_SRESET_REQUEST = 4 ;
+static const uint8_t P9N2_EX_L2_DIRECT_CONTROLS_DC_T0_CORE_STEP = 5 ;
+static const uint8_t P9N2_EX_L2_DIRECT_CONTROLS_DC_T0_CORE_START = 6 ;
+static const uint8_t P9N2_EX_L2_DIRECT_CONTROLS_DC_T0_CORE_STOP = 7 ;
+static const uint8_t P9N2_EX_L2_DIRECT_CONTROLS_DC_T1_CLEAR_MAINT = 11 ;
+static const uint8_t P9N2_EX_L2_DIRECT_CONTROLS_DC_T1_SRESET_REQUEST = 12 ;
+static const uint8_t P9N2_EX_L2_DIRECT_CONTROLS_DC_T1_CORE_STEP = 13 ;
+static const uint8_t P9N2_EX_L2_DIRECT_CONTROLS_DC_T1_CORE_START = 14 ;
+static const uint8_t P9N2_EX_L2_DIRECT_CONTROLS_DC_T1_CORE_STOP = 15 ;
+static const uint8_t P9N2_EX_L2_DIRECT_CONTROLS_DC_T2_CLEAR_MAINT = 19 ;
+static const uint8_t P9N2_EX_L2_DIRECT_CONTROLS_DC_T2_SRESET_REQUEST = 20 ;
+static const uint8_t P9N2_EX_L2_DIRECT_CONTROLS_DC_T2_CORE_STEP = 21 ;
+static const uint8_t P9N2_EX_L2_DIRECT_CONTROLS_DC_T2_CORE_START = 22 ;
+static const uint8_t P9N2_EX_L2_DIRECT_CONTROLS_DC_T2_CORE_STOP = 23 ;
+static const uint8_t P9N2_EX_L2_DIRECT_CONTROLS_DC_T3_CLEAR_MAINT = 27 ;
+static const uint8_t P9N2_EX_L2_DIRECT_CONTROLS_DC_T3_SRESET_REQUEST = 28 ;
+static const uint8_t P9N2_EX_L2_DIRECT_CONTROLS_DC_T3_CORE_STEP = 29 ;
+static const uint8_t P9N2_EX_L2_DIRECT_CONTROLS_DC_T3_CORE_START = 30 ;
+static const uint8_t P9N2_EX_L2_DIRECT_CONTROLS_DC_T3_CORE_STOP = 31 ;
+static const uint8_t P9N2_EX_L2_DIRECT_CONTROLS_WRITE_T0_PM_STATE = 32 ;
+static const uint8_t P9N2_EX_L2_DIRECT_CONTROLS_PSSCR_T0_PLS = 33 ;
+static const uint8_t P9N2_EX_L2_DIRECT_CONTROLS_PSSCR_T0_PLS_LEN = 4 ;
+static const uint8_t P9N2_EX_L2_DIRECT_CONTROLS_PSSCR_T0_SRR1 = 37 ;
+static const uint8_t P9N2_EX_L2_DIRECT_CONTROLS_PSSCR_T0_SRR1_LEN = 3 ;
+static const uint8_t P9N2_EX_L2_DIRECT_CONTROLS_WRITE_T1_PM_STATE = 40 ;
+static const uint8_t P9N2_EX_L2_DIRECT_CONTROLS_PSSCR_T1_PLS = 41 ;
+static const uint8_t P9N2_EX_L2_DIRECT_CONTROLS_PSSCR_T1_PLS_LEN = 4 ;
+static const uint8_t P9N2_EX_L2_DIRECT_CONTROLS_PSSCR_T1_SRR1 = 45 ;
+static const uint8_t P9N2_EX_L2_DIRECT_CONTROLS_PSSCR_T1_SRR1_LEN = 3 ;
+static const uint8_t P9N2_EX_L2_DIRECT_CONTROLS_WRITE_T2_PM_STATE = 48 ;
+static const uint8_t P9N2_EX_L2_DIRECT_CONTROLS_PSSCR_T2_PLS = 49 ;
+static const uint8_t P9N2_EX_L2_DIRECT_CONTROLS_PSSCR_T2_PLS_LEN = 4 ;
+static const uint8_t P9N2_EX_L2_DIRECT_CONTROLS_PSSCR_T2_SRR1 = 53 ;
+static const uint8_t P9N2_EX_L2_DIRECT_CONTROLS_PSSCR_T2_SRR1_LEN = 3 ;
+static const uint8_t P9N2_EX_L2_DIRECT_CONTROLS_WRITE_T3_PM_STATE = 56 ;
+static const uint8_t P9N2_EX_L2_DIRECT_CONTROLS_PSSCR_T3_PLS = 57 ;
+static const uint8_t P9N2_EX_L2_DIRECT_CONTROLS_PSSCR_T3_PLS_LEN = 4 ;
+static const uint8_t P9N2_EX_L2_DIRECT_CONTROLS_PSSCR_T3_SRR1 = 61 ;
+static const uint8_t P9N2_EX_L2_DIRECT_CONTROLS_PSSCR_T3_SRR1_LEN = 3 ;
+
+static const uint8_t P9N2_C_DIRECT_CONTROLS_DC_T0_CLEAR_MAINT = 3 ;
+static const uint8_t P9N2_C_DIRECT_CONTROLS_DC_T0_SRESET_REQUEST = 4 ;
+static const uint8_t P9N2_C_DIRECT_CONTROLS_DC_T0_CORE_STEP = 5 ;
+static const uint8_t P9N2_C_DIRECT_CONTROLS_DC_T0_CORE_START = 6 ;
+static const uint8_t P9N2_C_DIRECT_CONTROLS_DC_T0_CORE_STOP = 7 ;
+static const uint8_t P9N2_C_DIRECT_CONTROLS_DC_T1_CLEAR_MAINT = 11 ;
+static const uint8_t P9N2_C_DIRECT_CONTROLS_DC_T1_SRESET_REQUEST = 12 ;
+static const uint8_t P9N2_C_DIRECT_CONTROLS_DC_T1_CORE_STEP = 13 ;
+static const uint8_t P9N2_C_DIRECT_CONTROLS_DC_T1_CORE_START = 14 ;
+static const uint8_t P9N2_C_DIRECT_CONTROLS_DC_T1_CORE_STOP = 15 ;
+static const uint8_t P9N2_C_DIRECT_CONTROLS_DC_T2_CLEAR_MAINT = 19 ;
+static const uint8_t P9N2_C_DIRECT_CONTROLS_DC_T2_SRESET_REQUEST = 20 ;
+static const uint8_t P9N2_C_DIRECT_CONTROLS_DC_T2_CORE_STEP = 21 ;
+static const uint8_t P9N2_C_DIRECT_CONTROLS_DC_T2_CORE_START = 22 ;
+static const uint8_t P9N2_C_DIRECT_CONTROLS_DC_T2_CORE_STOP = 23 ;
+static const uint8_t P9N2_C_DIRECT_CONTROLS_DC_T3_CLEAR_MAINT = 27 ;
+static const uint8_t P9N2_C_DIRECT_CONTROLS_DC_T3_SRESET_REQUEST = 28 ;
+static const uint8_t P9N2_C_DIRECT_CONTROLS_DC_T3_CORE_STEP = 29 ;
+static const uint8_t P9N2_C_DIRECT_CONTROLS_DC_T3_CORE_START = 30 ;
+static const uint8_t P9N2_C_DIRECT_CONTROLS_DC_T3_CORE_STOP = 31 ;
+static const uint8_t P9N2_C_DIRECT_CONTROLS_WRITE_T0_PM_STATE = 32 ;
+static const uint8_t P9N2_C_DIRECT_CONTROLS_PSSCR_T0_PLS = 33 ;
+static const uint8_t P9N2_C_DIRECT_CONTROLS_PSSCR_T0_PLS_LEN = 4 ;
+static const uint8_t P9N2_C_DIRECT_CONTROLS_PSSCR_T0_SRR1 = 37 ;
+static const uint8_t P9N2_C_DIRECT_CONTROLS_PSSCR_T0_SRR1_LEN = 3 ;
+static const uint8_t P9N2_C_DIRECT_CONTROLS_WRITE_T1_PM_STATE = 40 ;
+static const uint8_t P9N2_C_DIRECT_CONTROLS_PSSCR_T1_PLS = 41 ;
+static const uint8_t P9N2_C_DIRECT_CONTROLS_PSSCR_T1_PLS_LEN = 4 ;
+static const uint8_t P9N2_C_DIRECT_CONTROLS_PSSCR_T1_SRR1 = 45 ;
+static const uint8_t P9N2_C_DIRECT_CONTROLS_PSSCR_T1_SRR1_LEN = 3 ;
+static const uint8_t P9N2_C_DIRECT_CONTROLS_WRITE_T2_PM_STATE = 48 ;
+static const uint8_t P9N2_C_DIRECT_CONTROLS_PSSCR_T2_PLS = 49 ;
+static const uint8_t P9N2_C_DIRECT_CONTROLS_PSSCR_T2_PLS_LEN = 4 ;
+static const uint8_t P9N2_C_DIRECT_CONTROLS_PSSCR_T2_SRR1 = 53 ;
+static const uint8_t P9N2_C_DIRECT_CONTROLS_PSSCR_T2_SRR1_LEN = 3 ;
+static const uint8_t P9N2_C_DIRECT_CONTROLS_WRITE_T3_PM_STATE = 56 ;
+static const uint8_t P9N2_C_DIRECT_CONTROLS_PSSCR_T3_PLS = 57 ;
+static const uint8_t P9N2_C_DIRECT_CONTROLS_PSSCR_T3_PLS_LEN = 4 ;
+static const uint8_t P9N2_C_DIRECT_CONTROLS_PSSCR_T3_SRR1 = 61 ;
+static const uint8_t P9N2_C_DIRECT_CONTROLS_PSSCR_T3_SRR1_LEN = 3 ;
+
+static const uint8_t P9N2_EQ_DRAM_REF_REG_L3_TIMER_DIVIDE_MAJOR = 0 ;
+static const uint8_t P9N2_EQ_DRAM_REF_REG_L3_TIMER_DIVIDE_MAJOR_LEN = 4 ;
+static const uint8_t P9N2_EQ_DRAM_REF_REG_L3_SCOM_INIT = 4 ;
+static const uint8_t P9N2_EQ_DRAM_REF_REG_L3_SCOM_QUIESCE_CACHE = 5 ;
+static const uint8_t P9N2_EQ_DRAM_REF_REG_L3_SCOM_QUIESCE_CACHE_LFSR = 6 ;
+static const uint8_t P9N2_EQ_DRAM_REF_REG_L3_SCOM_QUIESCE_REFRESH = 7 ;
+static const uint8_t P9N2_EQ_DRAM_REF_REG_L3_TIMER_DIVIDE_MINOR = 8 ;
+static const uint8_t P9N2_EQ_DRAM_REF_REG_L3_TIMER_DIVIDE_MINOR_LEN = 4 ;
+
+static const uint8_t P9N2_EX_DRAM_REF_REG_L3_TIMER_DIVIDE_MAJOR = 0 ;
+static const uint8_t P9N2_EX_DRAM_REF_REG_L3_TIMER_DIVIDE_MAJOR_LEN = 4 ;
+static const uint8_t P9N2_EX_DRAM_REF_REG_L3_SCOM_INIT = 4 ;
+static const uint8_t P9N2_EX_DRAM_REF_REG_L3_SCOM_QUIESCE_CACHE = 5 ;
+static const uint8_t P9N2_EX_DRAM_REF_REG_L3_SCOM_QUIESCE_CACHE_LFSR = 6 ;
+static const uint8_t P9N2_EX_DRAM_REF_REG_L3_SCOM_QUIESCE_REFRESH = 7 ;
+static const uint8_t P9N2_EX_DRAM_REF_REG_L3_TIMER_DIVIDE_MINOR = 8 ;
+static const uint8_t P9N2_EX_DRAM_REF_REG_L3_TIMER_DIVIDE_MINOR_LEN = 4 ;
+
+static const uint8_t P9N2_EQ_DTS_RESULT0_0_RESULT = 0 ;
+static const uint8_t P9N2_EQ_DTS_RESULT0_0_RESULT_LEN = 16 ;
+static const uint8_t P9N2_EQ_DTS_RESULT0_1_RESULT = 16 ;
+static const uint8_t P9N2_EQ_DTS_RESULT0_1_RESULT_LEN = 16 ;
+
+static const uint8_t P9N2_EX_DTS_RESULT0_0_RESULT = 0 ;
+static const uint8_t P9N2_EX_DTS_RESULT0_0_RESULT_LEN = 16 ;
+static const uint8_t P9N2_EX_DTS_RESULT0_1_RESULT = 16 ;
+static const uint8_t P9N2_EX_DTS_RESULT0_1_RESULT_LEN = 16 ;
+
+static const uint8_t P9N2_C_DTS_RESULT0_0_RESULT = 0 ;
+static const uint8_t P9N2_C_DTS_RESULT0_0_RESULT_LEN = 16 ;
+static const uint8_t P9N2_C_DTS_RESULT0_1_RESULT = 16 ;
+static const uint8_t P9N2_C_DTS_RESULT0_1_RESULT_LEN = 16 ;
+
+static const uint8_t P9N2_EQ_DTS_TRC_RESULT_TIMESTAMP_COUNTER_VALUE = 0 ;
+static const uint8_t P9N2_EQ_DTS_TRC_RESULT_TIMESTAMP_COUNTER_VALUE_LEN = 44 ;
+static const uint8_t P9N2_EQ_DTS_TRC_RESULT_TIMESTAMP_COUNTER_OVERFLOW_ERR = 44 ;
+static const uint8_t P9N2_EQ_DTS_TRC_RESULT_1 = 48 ;
+static const uint8_t P9N2_EQ_DTS_TRC_RESULT_1_LEN = 16 ;
+
+static const uint8_t P9N2_EX_DTS_TRC_RESULT_TIMESTAMP_COUNTER_VALUE = 0 ;
+static const uint8_t P9N2_EX_DTS_TRC_RESULT_TIMESTAMP_COUNTER_VALUE_LEN = 44 ;
+static const uint8_t P9N2_EX_DTS_TRC_RESULT_TIMESTAMP_COUNTER_OVERFLOW_ERR = 44 ;
+static const uint8_t P9N2_EX_DTS_TRC_RESULT_1 = 48 ;
+static const uint8_t P9N2_EX_DTS_TRC_RESULT_1_LEN = 16 ;
+
+static const uint8_t P9N2_C_DTS_TRC_RESULT_TIMESTAMP_COUNTER_VALUE = 0 ;
+static const uint8_t P9N2_C_DTS_TRC_RESULT_TIMESTAMP_COUNTER_VALUE_LEN = 44 ;
+static const uint8_t P9N2_C_DTS_TRC_RESULT_TIMESTAMP_COUNTER_OVERFLOW_ERR = 44 ;
+static const uint8_t P9N2_C_DTS_TRC_RESULT_1 = 48 ;
+static const uint8_t P9N2_C_DTS_TRC_RESULT_1_LEN = 16 ;
+
+static const uint8_t P9N2_EQ_EDRAM_BANK_FAIL_SCOM_RD_L3 = 0 ;
+static const uint8_t P9N2_EQ_EDRAM_BANK_FAIL_SCOM_RD_L3_LEN = 3 ;
+
+static const uint8_t P9N2_EX_L3_EDRAM_BANK_FAIL_SCOM_RD_L3 = 0 ;
+static const uint8_t P9N2_EX_L3_EDRAM_BANK_FAIL_SCOM_RD_L3_LEN = 3 ;
+
+static const uint8_t P9N2_EQ_EDRAM_BANK_SOFT_DIS_L3_CFG = 0 ;
+static const uint8_t P9N2_EQ_EDRAM_BANK_SOFT_DIS_L3_CFG_LEN = 10 ;
+
+static const uint8_t P9N2_EX_L3_EDRAM_BANK_SOFT_DIS_L3_CFG = 0 ;
+static const uint8_t P9N2_EX_L3_EDRAM_BANK_SOFT_DIS_L3_CFG_LEN = 10 ;
+
+static const uint8_t P9N2_EQ_EDRAM_REG_L3_CP_UTIL_EN_DC = 0 ;
+static const uint8_t P9N2_EQ_EDRAM_REG_L3_CP_UTIL_SEL_DC = 1 ;
+static const uint8_t P9N2_EQ_EDRAM_REG_L3_CP_UTIL_SEL_DC_LEN = 2 ;
+static const uint8_t P9N2_EQ_EDRAM_REG_L3_SPARE3 = 3 ;
+static const uint8_t P9N2_EQ_EDRAM_REG_L3_CP_UTIL_EXT_SEL = 4 ;
+static const uint8_t P9N2_EQ_EDRAM_REG_L3_CP_UTIL_EXT_SEL_LEN = 3 ;
+static const uint8_t P9N2_EQ_EDRAM_REG_L3_UTIL_MON_BITS = 7 ;
+static const uint8_t P9N2_EQ_EDRAM_REG_L3_UTIL_MON_BITS_LEN = 6 ;
+
+static const uint8_t P9N2_EX_L3_EDRAM_REG_L3_CP_UTIL_EN_DC = 0 ;
+static const uint8_t P9N2_EX_L3_EDRAM_REG_L3_CP_UTIL_SEL_DC = 1 ;
+static const uint8_t P9N2_EX_L3_EDRAM_REG_L3_CP_UTIL_SEL_DC_LEN = 2 ;
+static const uint8_t P9N2_EX_L3_EDRAM_REG_L3_SPARE3 = 3 ;
+static const uint8_t P9N2_EX_L3_EDRAM_REG_L3_CP_UTIL_EXT_SEL = 4 ;
+static const uint8_t P9N2_EX_L3_EDRAM_REG_L3_CP_UTIL_EXT_SEL_LEN = 3 ;
+static const uint8_t P9N2_EX_L3_EDRAM_REG_L3_UTIL_MON_BITS = 7 ;
+static const uint8_t P9N2_EX_L3_EDRAM_REG_L3_UTIL_MON_BITS_LEN = 6 ;
+
+static const uint8_t P9N2_EQ_EDRAM_STATUS_STAT = 0 ;
+static const uint8_t P9N2_EQ_EDRAM_STATUS_STAT_LEN = 4 ;
+
+static const uint8_t P9N2_EX_EDRAM_STATUS_STAT = 0 ;
+static const uint8_t P9N2_EX_EDRAM_STATUS_STAT_LEN = 4 ;
+
+static const uint8_t P9N2_C_EDRAM_STATUS_STAT = 0 ;
+static const uint8_t P9N2_C_EDRAM_STATUS_STAT_LEN = 4 ;
+
+static const uint8_t P9N2_EQ_ED_RD_ERR_STAT_REG0_L3_VAL = 0 ;
+static const uint8_t P9N2_EQ_ED_RD_ERR_STAT_REG0_L3_1ST_BEAT_UE = 1 ;
+static const uint8_t P9N2_EQ_ED_RD_ERR_STAT_REG0_L3_2ND_BEAT_UE = 2 ;
+static const uint8_t P9N2_EQ_ED_RD_ERR_STAT_REG0_L3_SPARE3 = 3 ;
+static const uint8_t P9N2_EQ_ED_RD_ERR_STAT_REG0_L3_1ST_BEAT_SYNDROME = 4 ;
+static const uint8_t P9N2_EQ_ED_RD_ERR_STAT_REG0_L3_1ST_BEAT_SYNDROME_LEN = 8 ;
+static const uint8_t P9N2_EQ_ED_RD_ERR_STAT_REG0_L3_2ND_BEAT_SYNDROME = 12 ;
+static const uint8_t P9N2_EQ_ED_RD_ERR_STAT_REG0_L3_2ND_BEAT_SYNDROME_LEN = 8 ;
+static const uint8_t P9N2_EQ_ED_RD_ERR_STAT_REG0_L3_DW = 20 ;
+static const uint8_t P9N2_EQ_ED_RD_ERR_STAT_REG0_L3_DW_LEN = 3 ;
+
+static const uint8_t P9N2_EX_ED_RD_ERR_STAT_REG0_L3_VAL = 0 ;
+static const uint8_t P9N2_EX_ED_RD_ERR_STAT_REG0_L3_1ST_BEAT_UE = 1 ;
+static const uint8_t P9N2_EX_ED_RD_ERR_STAT_REG0_L3_2ND_BEAT_UE = 2 ;
+static const uint8_t P9N2_EX_ED_RD_ERR_STAT_REG0_L3_SPARE3 = 3 ;
+static const uint8_t P9N2_EX_ED_RD_ERR_STAT_REG0_L3_1ST_BEAT_SYNDROME = 4 ;
+static const uint8_t P9N2_EX_ED_RD_ERR_STAT_REG0_L3_1ST_BEAT_SYNDROME_LEN = 8 ;
+static const uint8_t P9N2_EX_ED_RD_ERR_STAT_REG0_L3_2ND_BEAT_SYNDROME = 12 ;
+static const uint8_t P9N2_EX_ED_RD_ERR_STAT_REG0_L3_2ND_BEAT_SYNDROME_LEN = 8 ;
+static const uint8_t P9N2_EX_ED_RD_ERR_STAT_REG0_L3_DW = 20 ;
+static const uint8_t P9N2_EX_ED_RD_ERR_STAT_REG0_L3_DW_LEN = 3 ;
+
+static const uint8_t P9N2_EQ_ED_RD_ERR_STAT_REG1_L3_RA = 0 ;
+static const uint8_t P9N2_EQ_ED_RD_ERR_STAT_REG1_L3_RA_LEN = 14 ;
+static const uint8_t P9N2_EQ_ED_RD_ERR_STAT_REG1_L3_BANK = 14 ;
+static const uint8_t P9N2_EQ_ED_RD_ERR_STAT_REG1_L3_BANK_LEN = 4 ;
+
+static const uint8_t P9N2_EX_L3_ED_RD_ERR_STAT_REG1_L3_RA = 0 ;
+static const uint8_t P9N2_EX_L3_ED_RD_ERR_STAT_REG1_L3_RA_LEN = 14 ;
+static const uint8_t P9N2_EX_L3_ED_RD_ERR_STAT_REG1_L3_BANK = 14 ;
+static const uint8_t P9N2_EX_L3_ED_RD_ERR_STAT_REG1_L3_BANK_LEN = 4 ;
+
+static const uint8_t P9N2_EQ_ERROR_REG_CE = 0 ;
+static const uint8_t P9N2_EQ_ERROR_REG_CHIPLET_ERRORS = 1 ;
+static const uint8_t P9N2_EQ_ERROR_REG_CHIPLET_ERRORS_LEN = 3 ;
+static const uint8_t P9N2_EQ_ERROR_REG_PARITY = 4 ;
+static const uint8_t P9N2_EQ_ERROR_REG_DATA_BUFFER = 5 ;
+static const uint8_t P9N2_EQ_ERROR_REG_ADDR_BUFFER = 6 ;
+static const uint8_t P9N2_EQ_ERROR_REG_PCB_FSM = 7 ;
+static const uint8_t P9N2_EQ_ERROR_REG_CL_FSM = 8 ;
+static const uint8_t P9N2_EQ_ERROR_REG_INT_RX_FSM = 9 ;
+static const uint8_t P9N2_EQ_ERROR_REG_INT_TX_FSM = 10 ;
+static const uint8_t P9N2_EQ_ERROR_REG_INT_TYPE = 11 ;
+static const uint8_t P9N2_EQ_ERROR_REG_CL_DATA = 12 ;
+static const uint8_t P9N2_EQ_ERROR_REG_INFO = 13 ;
+static const uint8_t P9N2_EQ_ERROR_REG_UNUSED_0 = 14 ;
+static const uint8_t P9N2_EQ_ERROR_REG_CHIPLET_ATOMIC_LOCK = 15 ;
+static const uint8_t P9N2_EQ_ERROR_REG_PCB_INTERFACE = 16 ;
+static const uint8_t P9N2_EQ_ERROR_REG_CHIPLET_OFFLINE = 17 ;
+static const uint8_t P9N2_EQ_ERROR_REG_EDRAM_SEQUENCE_ERR = 18 ;
+static const uint8_t P9N2_EQ_ERROR_REG_CTRL_PARITY = 19 ;
+static const uint8_t P9N2_EQ_ERROR_REG_ADDRESS_PARITY = 20 ;
+static const uint8_t P9N2_EQ_ERROR_REG_TIMEOUT_PARITY = 21 ;
+static const uint8_t P9N2_EQ_ERROR_REG_CONFIG_PARITY = 22 ;
+static const uint8_t P9N2_EQ_ERROR_REG_UNUSED_1 = 23 ;
+static const uint8_t P9N2_EQ_ERROR_REG_DIV_PARITY = 24 ;
+static const uint8_t P9N2_EQ_ERROR_REG_PLL_UNLOCK = 25 ;
+static const uint8_t P9N2_EQ_ERROR_REG_PLL_UNLOCK_LEN = 4 ;
+
+static const uint8_t P9N2_EX_ERROR_REG_CE = 0 ;
+static const uint8_t P9N2_EX_ERROR_REG_CHIPLET_ERRORS = 1 ;
+static const uint8_t P9N2_EX_ERROR_REG_CHIPLET_ERRORS_LEN = 3 ;
+static const uint8_t P9N2_EX_ERROR_REG_PARITY = 4 ;
+static const uint8_t P9N2_EX_ERROR_REG_DATA_BUFFER = 5 ;
+static const uint8_t P9N2_EX_ERROR_REG_ADDR_BUFFER = 6 ;
+static const uint8_t P9N2_EX_ERROR_REG_PCB_FSM = 7 ;
+static const uint8_t P9N2_EX_ERROR_REG_CL_FSM = 8 ;
+static const uint8_t P9N2_EX_ERROR_REG_INT_RX_FSM = 9 ;
+static const uint8_t P9N2_EX_ERROR_REG_INT_TX_FSM = 10 ;
+static const uint8_t P9N2_EX_ERROR_REG_INT_TYPE = 11 ;
+static const uint8_t P9N2_EX_ERROR_REG_CL_DATA = 12 ;
+static const uint8_t P9N2_EX_ERROR_REG_INFO = 13 ;
+static const uint8_t P9N2_EX_ERROR_REG_UNUSED_0 = 14 ;
+static const uint8_t P9N2_EX_ERROR_REG_CHIPLET_ATOMIC_LOCK = 15 ;
+static const uint8_t P9N2_EX_ERROR_REG_PCB_INTERFACE = 16 ;
+static const uint8_t P9N2_EX_ERROR_REG_CHIPLET_OFFLINE = 17 ;
+static const uint8_t P9N2_EX_ERROR_REG_EDRAM_SEQUENCE_ERR = 18 ;
+static const uint8_t P9N2_EX_ERROR_REG_CTRL_PARITY = 19 ;
+static const uint8_t P9N2_EX_ERROR_REG_ADDRESS_PARITY = 20 ;
+static const uint8_t P9N2_EX_ERROR_REG_TIMEOUT_PARITY = 21 ;
+static const uint8_t P9N2_EX_ERROR_REG_CONFIG_PARITY = 22 ;
+static const uint8_t P9N2_EX_ERROR_REG_UNUSED_1 = 23 ;
+static const uint8_t P9N2_EX_ERROR_REG_DIV_PARITY = 24 ;
+static const uint8_t P9N2_EX_ERROR_REG_PLL_UNLOCK = 25 ;
+static const uint8_t P9N2_EX_ERROR_REG_PLL_UNLOCK_LEN = 4 ;
+
+static const uint8_t P9N2_C_ERROR_REG_CE = 0 ;
+static const uint8_t P9N2_C_ERROR_REG_CHIPLET_ERRORS = 1 ;
+static const uint8_t P9N2_C_ERROR_REG_CHIPLET_ERRORS_LEN = 3 ;
+static const uint8_t P9N2_C_ERROR_REG_PARITY = 4 ;
+static const uint8_t P9N2_C_ERROR_REG_DATA_BUFFER = 5 ;
+static const uint8_t P9N2_C_ERROR_REG_ADDR_BUFFER = 6 ;
+static const uint8_t P9N2_C_ERROR_REG_PCB_FSM = 7 ;
+static const uint8_t P9N2_C_ERROR_REG_CL_FSM = 8 ;
+static const uint8_t P9N2_C_ERROR_REG_INT_RX_FSM = 9 ;
+static const uint8_t P9N2_C_ERROR_REG_INT_TX_FSM = 10 ;
+static const uint8_t P9N2_C_ERROR_REG_INT_TYPE = 11 ;
+static const uint8_t P9N2_C_ERROR_REG_CL_DATA = 12 ;
+static const uint8_t P9N2_C_ERROR_REG_INFO = 13 ;
+static const uint8_t P9N2_C_ERROR_REG_UNUSED_0 = 14 ;
+static const uint8_t P9N2_C_ERROR_REG_CHIPLET_ATOMIC_LOCK = 15 ;
+static const uint8_t P9N2_C_ERROR_REG_PCB_INTERFACE = 16 ;
+static const uint8_t P9N2_C_ERROR_REG_CHIPLET_OFFLINE = 17 ;
+static const uint8_t P9N2_C_ERROR_REG_EDRAM_SEQUENCE_ERR = 18 ;
+static const uint8_t P9N2_C_ERROR_REG_CTRL_PARITY = 19 ;
+static const uint8_t P9N2_C_ERROR_REG_ADDRESS_PARITY = 20 ;
+static const uint8_t P9N2_C_ERROR_REG_TIMEOUT_PARITY = 21 ;
+static const uint8_t P9N2_C_ERROR_REG_CONFIG_PARITY = 22 ;
+static const uint8_t P9N2_C_ERROR_REG_UNUSED_1 = 23 ;
+static const uint8_t P9N2_C_ERROR_REG_DIV_PARITY = 24 ;
+static const uint8_t P9N2_C_ERROR_REG_PLL_UNLOCK = 25 ;
+static const uint8_t P9N2_C_ERROR_REG_PLL_UNLOCK_LEN = 4 ;
+
+static const uint8_t P9N2_EQ_ERROR_STATUS_PCB_WRITE_NOT_ALLOWED_ERR = 0 ;
+static const uint8_t P9N2_EQ_ERROR_STATUS_PCB_READ_NOT_ALLOWED_ERR = 1 ;
+static const uint8_t P9N2_EQ_ERROR_STATUS_PCB_PARITY_ON_CMD_ERR = 2 ;
+static const uint8_t P9N2_EQ_ERROR_STATUS_PCB_ADDRESS_NOT_VALID_ERR = 3 ;
+static const uint8_t P9N2_EQ_ERROR_STATUS_PCB_PARITY_ON_ADDR_ERR = 4 ;
+static const uint8_t P9N2_EQ_ERROR_STATUS_PCB_PARITY_ON_DATA_ERR = 5 ;
+static const uint8_t P9N2_EQ_ERROR_STATUS_PCB_PROTECTED_ACCESS_INVALID_ERR = 6 ;
+static const uint8_t P9N2_EQ_ERROR_STATUS_PCB_PARITY_ON_SPCIF_ERR = 7 ;
+static const uint8_t P9N2_EQ_ERROR_STATUS_PCB_WRITE_AND_OPCG_IP_ERR = 8 ;
+static const uint8_t P9N2_EQ_ERROR_STATUS_SCAN_READ_AND_OPCG_IP_ERR = 9 ;
+static const uint8_t P9N2_EQ_ERROR_STATUS_CLOCK_CMD_CONFLICT_ERR = 10 ;
+static const uint8_t P9N2_EQ_ERROR_STATUS_SCAN_COLLISION_ERR = 11 ;
+static const uint8_t P9N2_EQ_ERROR_STATUS_PREVENTED_SCAN_COLLISION_ERR = 12 ;
+static const uint8_t P9N2_EQ_ERROR_STATUS_OPCG_TRIGGER_ERR = 13 ;
+static const uint8_t P9N2_EQ_ERROR_STATUS_PHASE_CNT_CORRUPTION_ERR = 14 ;
+static const uint8_t P9N2_EQ_ERROR_STATUS_CLOCK_CMD_PREVENTED_ERR = 15 ;
+static const uint8_t P9N2_EQ_ERROR_STATUS_PARITY_ON_OPCG_SM_ERR = 16 ;
+static const uint8_t P9N2_EQ_ERROR_STATUS_PARITY_ON_CLOCK_MUX_REG_ERR = 17 ;
+static const uint8_t P9N2_EQ_ERROR_STATUS_PARITY_ON_OPCG_REG_ERR = 18 ;
+static const uint8_t P9N2_EQ_ERROR_STATUS_PARITY_ON_SYNC_CONFIG_REG_ERR = 19 ;
+static const uint8_t P9N2_EQ_ERROR_STATUS_PARITY_ON_XSTOP_REG_ERR = 20 ;
+static const uint8_t P9N2_EQ_ERROR_STATUS_PARITY_ON_GPIO_REG_ERR = 21 ;
+static const uint8_t P9N2_EQ_ERROR_STATUS_CLKCMD_REQUEST_ERR = 22 ;
+static const uint8_t P9N2_EQ_ERROR_STATUS_CBS_PROTOCOL_ERR = 23 ;
+static const uint8_t P9N2_EQ_ERROR_STATUS_VITL_ALIGN_ERR = 24 ;
+static const uint8_t P9N2_EQ_ERROR_STATUS_UNIT_SYNC_LVL_ERR = 25 ;
+static const uint8_t P9N2_EQ_ERROR_STATUS_PARITY_ON_SELFBOOT_CMD_STATE_ERR = 26 ;
+static const uint8_t P9N2_EQ_ERROR_STATUS_OPCG_STOPPED_BY_PCB_ERR = 27 ;
+static const uint8_t P9N2_EQ_ERROR_STATUS_EDRAM_SCAN_PREVENTED_ERR = 28 ;
+static const uint8_t P9N2_EQ_ERROR_STATUS_UNUSED_ERROR29 = 29 ;
+static const uint8_t P9N2_EQ_ERROR_STATUS_UNUSED_ERROR30 = 30 ;
+static const uint8_t P9N2_EQ_ERROR_STATUS_UNUSED_ERROR31 = 31 ;
+
+static const uint8_t P9N2_EX_ERROR_STATUS_PCB_WRITE_NOT_ALLOWED_ERR = 0 ;
+static const uint8_t P9N2_EX_ERROR_STATUS_PCB_READ_NOT_ALLOWED_ERR = 1 ;
+static const uint8_t P9N2_EX_ERROR_STATUS_PCB_PARITY_ON_CMD_ERR = 2 ;
+static const uint8_t P9N2_EX_ERROR_STATUS_PCB_ADDRESS_NOT_VALID_ERR = 3 ;
+static const uint8_t P9N2_EX_ERROR_STATUS_PCB_PARITY_ON_ADDR_ERR = 4 ;
+static const uint8_t P9N2_EX_ERROR_STATUS_PCB_PARITY_ON_DATA_ERR = 5 ;
+static const uint8_t P9N2_EX_ERROR_STATUS_PCB_PROTECTED_ACCESS_INVALID_ERR = 6 ;
+static const uint8_t P9N2_EX_ERROR_STATUS_PCB_PARITY_ON_SPCIF_ERR = 7 ;
+static const uint8_t P9N2_EX_ERROR_STATUS_PCB_WRITE_AND_OPCG_IP_ERR = 8 ;
+static const uint8_t P9N2_EX_ERROR_STATUS_SCAN_READ_AND_OPCG_IP_ERR = 9 ;
+static const uint8_t P9N2_EX_ERROR_STATUS_CLOCK_CMD_CONFLICT_ERR = 10 ;
+static const uint8_t P9N2_EX_ERROR_STATUS_SCAN_COLLISION_ERR = 11 ;
+static const uint8_t P9N2_EX_ERROR_STATUS_PREVENTED_SCAN_COLLISION_ERR = 12 ;
+static const uint8_t P9N2_EX_ERROR_STATUS_OPCG_TRIGGER_ERR = 13 ;
+static const uint8_t P9N2_EX_ERROR_STATUS_PHASE_CNT_CORRUPTION_ERR = 14 ;
+static const uint8_t P9N2_EX_ERROR_STATUS_CLOCK_CMD_PREVENTED_ERR = 15 ;
+static const uint8_t P9N2_EX_ERROR_STATUS_PARITY_ON_OPCG_SM_ERR = 16 ;
+static const uint8_t P9N2_EX_ERROR_STATUS_PARITY_ON_CLOCK_MUX_REG_ERR = 17 ;
+static const uint8_t P9N2_EX_ERROR_STATUS_PARITY_ON_OPCG_REG_ERR = 18 ;
+static const uint8_t P9N2_EX_ERROR_STATUS_PARITY_ON_SYNC_CONFIG_REG_ERR = 19 ;
+static const uint8_t P9N2_EX_ERROR_STATUS_PARITY_ON_XSTOP_REG_ERR = 20 ;
+static const uint8_t P9N2_EX_ERROR_STATUS_PARITY_ON_GPIO_REG_ERR = 21 ;
+static const uint8_t P9N2_EX_ERROR_STATUS_CLKCMD_REQUEST_ERR = 22 ;
+static const uint8_t P9N2_EX_ERROR_STATUS_CBS_PROTOCOL_ERR = 23 ;
+static const uint8_t P9N2_EX_ERROR_STATUS_VITL_ALIGN_ERR = 24 ;
+static const uint8_t P9N2_EX_ERROR_STATUS_UNIT_SYNC_LVL_ERR = 25 ;
+static const uint8_t P9N2_EX_ERROR_STATUS_PARITY_ON_SELFBOOT_CMD_STATE_ERR = 26 ;
+static const uint8_t P9N2_EX_ERROR_STATUS_OPCG_STOPPED_BY_PCB_ERR = 27 ;
+static const uint8_t P9N2_EX_ERROR_STATUS_EDRAM_SCAN_PREVENTED_ERR = 28 ;
+static const uint8_t P9N2_EX_ERROR_STATUS_UNUSED_ERROR29 = 29 ;
+static const uint8_t P9N2_EX_ERROR_STATUS_UNUSED_ERROR30 = 30 ;
+static const uint8_t P9N2_EX_ERROR_STATUS_UNUSED_ERROR31 = 31 ;
+
+static const uint8_t P9N2_C_ERROR_STATUS_PCB_WRITE_NOT_ALLOWED_ERR = 0 ;
+static const uint8_t P9N2_C_ERROR_STATUS_PCB_READ_NOT_ALLOWED_ERR = 1 ;
+static const uint8_t P9N2_C_ERROR_STATUS_PCB_PARITY_ON_CMD_ERR = 2 ;
+static const uint8_t P9N2_C_ERROR_STATUS_PCB_ADDRESS_NOT_VALID_ERR = 3 ;
+static const uint8_t P9N2_C_ERROR_STATUS_PCB_PARITY_ON_ADDR_ERR = 4 ;
+static const uint8_t P9N2_C_ERROR_STATUS_PCB_PARITY_ON_DATA_ERR = 5 ;
+static const uint8_t P9N2_C_ERROR_STATUS_PCB_PROTECTED_ACCESS_INVALID_ERR = 6 ;
+static const uint8_t P9N2_C_ERROR_STATUS_PCB_PARITY_ON_SPCIF_ERR = 7 ;
+static const uint8_t P9N2_C_ERROR_STATUS_PCB_WRITE_AND_OPCG_IP_ERR = 8 ;
+static const uint8_t P9N2_C_ERROR_STATUS_SCAN_READ_AND_OPCG_IP_ERR = 9 ;
+static const uint8_t P9N2_C_ERROR_STATUS_CLOCK_CMD_CONFLICT_ERR = 10 ;
+static const uint8_t P9N2_C_ERROR_STATUS_SCAN_COLLISION_ERR = 11 ;
+static const uint8_t P9N2_C_ERROR_STATUS_PREVENTED_SCAN_COLLISION_ERR = 12 ;
+static const uint8_t P9N2_C_ERROR_STATUS_OPCG_TRIGGER_ERR = 13 ;
+static const uint8_t P9N2_C_ERROR_STATUS_PHASE_CNT_CORRUPTION_ERR = 14 ;
+static const uint8_t P9N2_C_ERROR_STATUS_CLOCK_CMD_PREVENTED_ERR = 15 ;
+static const uint8_t P9N2_C_ERROR_STATUS_PARITY_ON_OPCG_SM_ERR = 16 ;
+static const uint8_t P9N2_C_ERROR_STATUS_PARITY_ON_CLOCK_MUX_REG_ERR = 17 ;
+static const uint8_t P9N2_C_ERROR_STATUS_PARITY_ON_OPCG_REG_ERR = 18 ;
+static const uint8_t P9N2_C_ERROR_STATUS_PARITY_ON_SYNC_CONFIG_REG_ERR = 19 ;
+static const uint8_t P9N2_C_ERROR_STATUS_PARITY_ON_XSTOP_REG_ERR = 20 ;
+static const uint8_t P9N2_C_ERROR_STATUS_PARITY_ON_GPIO_REG_ERR = 21 ;
+static const uint8_t P9N2_C_ERROR_STATUS_CLKCMD_REQUEST_ERR = 22 ;
+static const uint8_t P9N2_C_ERROR_STATUS_CBS_PROTOCOL_ERR = 23 ;
+static const uint8_t P9N2_C_ERROR_STATUS_VITL_ALIGN_ERR = 24 ;
+static const uint8_t P9N2_C_ERROR_STATUS_UNIT_SYNC_LVL_ERR = 25 ;
+static const uint8_t P9N2_C_ERROR_STATUS_PARITY_ON_SELFBOOT_CMD_STATE_ERR = 26 ;
+static const uint8_t P9N2_C_ERROR_STATUS_OPCG_STOPPED_BY_PCB_ERR = 27 ;
+static const uint8_t P9N2_C_ERROR_STATUS_EDRAM_SCAN_PREVENTED_ERR = 28 ;
+static const uint8_t P9N2_C_ERROR_STATUS_UNUSED_ERROR29 = 29 ;
+static const uint8_t P9N2_C_ERROR_STATUS_UNUSED_ERROR30 = 30 ;
+static const uint8_t P9N2_C_ERROR_STATUS_UNUSED_ERROR31 = 31 ;
+
+static const uint8_t P9N2_EQ_ERR_INJ_REG_L3_SINGLE_CAC = 0 ;
+static const uint8_t P9N2_EQ_ERR_INJ_REG_L3_SOLID_CAC = 1 ;
+static const uint8_t P9N2_EQ_ERR_INJ_REG_L3_CAC_TYPE = 2 ;
+static const uint8_t P9N2_EQ_ERR_INJ_REG_L3_CAC_TYPE_LEN = 2 ;
+static const uint8_t P9N2_EQ_ERR_INJ_REG_L3_SINGLE_DIR = 4 ;
+static const uint8_t P9N2_EQ_ERR_INJ_REG_L3_SOLID_DIR = 5 ;
+static const uint8_t P9N2_EQ_ERR_INJ_REG_L3_DIR_TYPE = 6 ;
+static const uint8_t P9N2_EQ_ERR_INJ_REG_L3_SINGLE_LRU = 7 ;
+static const uint8_t P9N2_EQ_ERR_INJ_REG_L3_SOLID_LRU = 8 ;
+
+static const uint8_t P9N2_EX_ERR_INJ_REG_ERROR_INJ_DCSET0 = 0 ;
+static const uint8_t P9N2_EX_ERR_INJ_REG_ERROR_INJ_DCSET1 = 1 ;
+static const uint8_t P9N2_EX_ERR_INJ_REG_ERROR_INJ_DCSET2 = 2 ;
+static const uint8_t P9N2_EX_ERR_INJ_REG_ERROR_INJ_SLICE_DCD0 = 3 ;
+static const uint8_t P9N2_EX_ERR_INJ_REG_ERROR_INJ_SLICE_DCD1 = 4 ;
+static const uint8_t P9N2_EX_ERR_INJ_REG_ERROR_INJ_SLICE_DCD2 = 5 ;
+static const uint8_t P9N2_EX_ERR_INJ_REG_ERROR_INJ_DCACHE = 6 ;
+static const uint8_t P9N2_EX_ERR_INJ_REG_ERROR_INJ_DDIR = 7 ;
+static const uint8_t P9N2_EX_ERR_INJ_REG_ERROR_INJ_SETP = 8 ;
+static const uint8_t P9N2_EX_ERR_INJ_REG_ERROR_INJ_DERAT = 9 ;
+static const uint8_t P9N2_EX_ERR_INJ_REG_ERROR_INJ_DERAT_MULTIHIT = 10 ;
+static const uint8_t P9N2_EX_ERR_INJ_REG_ERROR_INJ_SLB = 11 ;
+static const uint8_t P9N2_EX_ERR_INJ_REG_ERROR_INJ_SLB_MULTIHIT = 12 ;
+static const uint8_t P9N2_EX_ERR_INJ_REG_ERROR_INJ_ITLB = 13 ;
+static const uint8_t P9N2_EX_ERR_INJ_REG_ERROR_INJ_DTLB = 14 ;
+static const uint8_t P9N2_EX_ERR_INJ_REG_ERROR_INJ_DTLB_MULTIHIT = 15 ;
+
+static const uint8_t P9N2_EX_L2_ERR_INJ_REG_DW_TYPE = 0 ;
+static const uint8_t P9N2_EX_L2_ERR_INJ_REG_DW_TYPE_LEN = 3 ;
+static const uint8_t P9N2_EX_L2_ERR_INJ_REG_CW_TYPE = 4 ;
+static const uint8_t P9N2_EX_L2_ERR_INJ_REG_CW_TYPE_LEN = 4 ;
+static const uint8_t P9N2_EX_L2_ERR_INJ_REG_STQ_TYPE = 8 ;
+static const uint8_t P9N2_EX_L2_ERR_INJ_REG_STQ_TYPE_LEN = 2 ;
+static const uint8_t P9N2_EX_L2_ERR_INJ_REG_CPI_TYPE = 10 ;
+static const uint8_t P9N2_EX_L2_ERR_INJ_REG_CPI_TYPE_LEN = 3 ;
+static const uint8_t P9N2_EX_L2_ERR_INJ_REG_LVDIR_EN = 13 ;
+static const uint8_t P9N2_EX_L2_ERR_INJ_REG_LRU_EN = 14 ;
+
+static const uint8_t P9N2_C_ERR_INJ_REG_ERROR_INJ_DCSET0 = 0 ;
+static const uint8_t P9N2_C_ERR_INJ_REG_ERROR_INJ_DCSET1 = 1 ;
+static const uint8_t P9N2_C_ERR_INJ_REG_ERROR_INJ_DCSET2 = 2 ;
+static const uint8_t P9N2_C_ERR_INJ_REG_ERROR_INJ_SLICE_DCD0 = 3 ;
+static const uint8_t P9N2_C_ERR_INJ_REG_ERROR_INJ_SLICE_DCD1 = 4 ;
+static const uint8_t P9N2_C_ERR_INJ_REG_ERROR_INJ_SLICE_DCD2 = 5 ;
+static const uint8_t P9N2_C_ERR_INJ_REG_ERROR_INJ_DCACHE = 6 ;
+static const uint8_t P9N2_C_ERR_INJ_REG_ERROR_INJ_DDIR = 7 ;
+static const uint8_t P9N2_C_ERR_INJ_REG_ERROR_INJ_SETP = 8 ;
+static const uint8_t P9N2_C_ERR_INJ_REG_ERROR_INJ_DERAT = 9 ;
+static const uint8_t P9N2_C_ERR_INJ_REG_ERROR_INJ_DERAT_MULTIHIT = 10 ;
+static const uint8_t P9N2_C_ERR_INJ_REG_ERROR_INJ_SLB = 11 ;
+static const uint8_t P9N2_C_ERR_INJ_REG_ERROR_INJ_SLB_MULTIHIT = 12 ;
+static const uint8_t P9N2_C_ERR_INJ_REG_ERROR_INJ_ITLB = 13 ;
+static const uint8_t P9N2_C_ERR_INJ_REG_ERROR_INJ_DTLB = 14 ;
+static const uint8_t P9N2_C_ERR_INJ_REG_ERROR_INJ_DTLB_MULTIHIT = 15 ;
+
+static const uint8_t P9N2_EX_L3_ERR_INJ_REG_L3_SINGLE_CAC = 0 ;
+static const uint8_t P9N2_EX_L3_ERR_INJ_REG_L3_SOLID_CAC = 1 ;
+static const uint8_t P9N2_EX_L3_ERR_INJ_REG_L3_CAC_TYPE = 2 ;
+static const uint8_t P9N2_EX_L3_ERR_INJ_REG_L3_CAC_TYPE_LEN = 2 ;
+static const uint8_t P9N2_EX_L3_ERR_INJ_REG_L3_SINGLE_DIR = 4 ;
+static const uint8_t P9N2_EX_L3_ERR_INJ_REG_L3_SOLID_DIR = 5 ;
+static const uint8_t P9N2_EX_L3_ERR_INJ_REG_L3_DIR_TYPE = 6 ;
+static const uint8_t P9N2_EX_L3_ERR_INJ_REG_L3_SINGLE_LRU = 7 ;
+static const uint8_t P9N2_EX_L3_ERR_INJ_REG_L3_SOLID_LRU = 8 ;
+
+static const uint8_t P9N2_EQ_ERR_RPT0_RSV = 0 ;
+static const uint8_t P9N2_EQ_ERR_RPT0_FIR14_NCCTL_RLD_BARRIER = 1 ;
+static const uint8_t P9N2_EQ_ERR_RPT0_FIR14_NCCTL_SNP = 2 ;
+static const uint8_t P9N2_EQ_ERR_RPT0_FIR14_NCCTL_TLBIE_ACK = 3 ;
+static const uint8_t P9N2_EQ_ERR_RPT0_FIR14_NCCTL_SYNC = 4 ;
+static const uint8_t P9N2_EQ_ERR_RPT0_FIR14_NCCTL_VSYNC = 5 ;
+static const uint8_t P9N2_EQ_ERR_RPT0_FIR14_TMCTL_TIDX_TEND_LDST_SEQ = 6 ;
+static const uint8_t P9N2_EQ_ERR_RPT0_FIR14_RVCTL = 7 ;
+static const uint8_t P9N2_EQ_ERR_RPT0_FIR14_SRCTL0_BAD_HPC = 8 ;
+static const uint8_t P9N2_EQ_ERR_RPT0_FIR14_SRCTL1_BAD_HPC = 9 ;
+static const uint8_t P9N2_EQ_ERR_RPT0_FIR14_SRCTL2_BAD_HPC = 10 ;
+static const uint8_t P9N2_EQ_ERR_RPT0_FIR14_SRCTL3_BAD_HPC = 11 ;
+static const uint8_t P9N2_EQ_ERR_RPT0_FIR14_PBARB_FSM_REQ_OVERFLOW = 12 ;
+static const uint8_t P9N2_EQ_ERR_RPT0_FIR14_PBARB_TRASHMODE_PB_REQ = 13 ;
+static const uint8_t P9N2_EQ_ERR_RPT0_FIR14_L3PF_MACH_DONE = 14 ;
+static const uint8_t P9N2_EQ_ERR_RPT0_FIR14_RCMD0_TTAG_PERR = 15 ;
+static const uint8_t P9N2_EQ_ERR_RPT0_FIR14_RCMD1_TTAG_PERR = 16 ;
+static const uint8_t P9N2_EQ_ERR_RPT0_FIR14_RCMD2_TTAG_PERR = 17 ;
+static const uint8_t P9N2_EQ_ERR_RPT0_FIR14_RCMD3_TTAG_PERR = 18 ;
+static const uint8_t P9N2_EQ_ERR_RPT0_FIR14_CR0_TTAG_PERR = 19 ;
+static const uint8_t P9N2_EQ_ERR_RPT0_FIR14_CR0_ATAG_PERR = 20 ;
+static const uint8_t P9N2_EQ_ERR_RPT0_FIR14_CR1_TTAG_PERR = 21 ;
+static const uint8_t P9N2_EQ_ERR_RPT0_FIR14_CR1_ATAG_PERR = 22 ;
+static const uint8_t P9N2_EQ_ERR_RPT0_FIR14_CR2_TTAG_PERR = 23 ;
+static const uint8_t P9N2_EQ_ERR_RPT0_FIR14_CR2_ATAG_PERR = 24 ;
+static const uint8_t P9N2_EQ_ERR_RPT0_FIR14_CR3_TTAG_PERR = 25 ;
+static const uint8_t P9N2_EQ_ERR_RPT0_FIR14_CR3_ATAG_PERR = 26 ;
+static const uint8_t P9N2_EQ_ERR_RPT0_FIR14_RCMD0_ADDR_PERR = 27 ;
+static const uint8_t P9N2_EQ_ERR_RPT0_FIR14_RCMD1_ADDR_PERR = 28 ;
+static const uint8_t P9N2_EQ_ERR_RPT0_FIR14_RCMD2_ADDR_PERR = 29 ;
+static const uint8_t P9N2_EQ_ERR_RPT0_FIR14_RCMD3_ADDR_PERR = 30 ;
+static const uint8_t P9N2_EQ_ERR_RPT0_FIR9_PEC_PHASE3_TIMEOUT = 31 ;
+static const uint8_t P9N2_EQ_ERR_RPT0_FIR9_PEC_PHASE4_SAME = 32 ;
+static const uint8_t P9N2_EQ_ERR_RPT0_FIR9_PEC_PHASE4_RCCO_DISP_FAIL = 33 ;
+static const uint8_t P9N2_EQ_ERR_RPT0_FIR9_PEC_PHASE5_TIMEOUT = 34 ;
+static const uint8_t P9N2_EQ_ERR_RPT0_FIR14_B01_BOTH_ACTIVE = 35 ;
+static const uint8_t P9N2_EQ_ERR_RPT0_FIR14_PHANTOM_B01_REQ = 36 ;
+static const uint8_t P9N2_EQ_ERR_RPT0_FIR14_RC_UNEXP_F2_DATA = 37 ;
+static const uint8_t P9N2_EQ_ERR_RPT0_FIR14_RC_UNEXP_PURG_HIT = 38 ;
+static const uint8_t P9N2_EQ_ERR_RPT0_FIR14_RCX_UNEXP_IDLE_PBL3_DATA = 39 ;
+static const uint8_t P9N2_EQ_ERR_RPT0_FIR14_RCX_UNEXP_IDLE_PB_CRESP = 40 ;
+static const uint8_t P9N2_EQ_ERR_RPT0_FIR14_COX_UNEXP_IDLE_PB_CRESP = 41 ;
+
+static const uint8_t P9N2_EX_L2_ERR_RPT0_RSV = 0 ;
+static const uint8_t P9N2_EX_L2_ERR_RPT0_FIR14_NCCTL_RLD_BARRIER = 1 ;
+static const uint8_t P9N2_EX_L2_ERR_RPT0_FIR14_NCCTL_SNP = 2 ;
+static const uint8_t P9N2_EX_L2_ERR_RPT0_FIR14_NCCTL_TLBIE_ACK = 3 ;
+static const uint8_t P9N2_EX_L2_ERR_RPT0_FIR14_NCCTL_SYNC = 4 ;
+static const uint8_t P9N2_EX_L2_ERR_RPT0_FIR14_NCCTL_VSYNC = 5 ;
+static const uint8_t P9N2_EX_L2_ERR_RPT0_FIR14_TMCTL_TIDX_TEND_LDST_SEQ = 6 ;
+static const uint8_t P9N2_EX_L2_ERR_RPT0_FIR14_RVCTL = 7 ;
+static const uint8_t P9N2_EX_L2_ERR_RPT0_FIR14_SRCTL0_BAD_HPC = 8 ;
+static const uint8_t P9N2_EX_L2_ERR_RPT0_FIR14_SRCTL1_BAD_HPC = 9 ;
+static const uint8_t P9N2_EX_L2_ERR_RPT0_FIR14_SRCTL2_BAD_HPC = 10 ;
+static const uint8_t P9N2_EX_L2_ERR_RPT0_FIR14_SRCTL3_BAD_HPC = 11 ;
+static const uint8_t P9N2_EX_L2_ERR_RPT0_FIR14_PBARB_FSM_REQ_OVERFLOW = 12 ;
+static const uint8_t P9N2_EX_L2_ERR_RPT0_FIR14_PBARB_TRASHMODE_PB_REQ = 13 ;
+static const uint8_t P9N2_EX_L2_ERR_RPT0_FIR14_L3PF_MACH_DONE = 14 ;
+static const uint8_t P9N2_EX_L2_ERR_RPT0_FIR14_RCMD0_TTAG_PERR = 15 ;
+static const uint8_t P9N2_EX_L2_ERR_RPT0_FIR14_RCMD1_TTAG_PERR = 16 ;
+static const uint8_t P9N2_EX_L2_ERR_RPT0_FIR14_RCMD2_TTAG_PERR = 17 ;
+static const uint8_t P9N2_EX_L2_ERR_RPT0_FIR14_RCMD3_TTAG_PERR = 18 ;
+static const uint8_t P9N2_EX_L2_ERR_RPT0_FIR14_CR0_TTAG_PERR = 19 ;
+static const uint8_t P9N2_EX_L2_ERR_RPT0_FIR14_CR0_ATAG_PERR = 20 ;
+static const uint8_t P9N2_EX_L2_ERR_RPT0_FIR14_CR1_TTAG_PERR = 21 ;
+static const uint8_t P9N2_EX_L2_ERR_RPT0_FIR14_CR1_ATAG_PERR = 22 ;
+static const uint8_t P9N2_EX_L2_ERR_RPT0_FIR14_CR2_TTAG_PERR = 23 ;
+static const uint8_t P9N2_EX_L2_ERR_RPT0_FIR14_CR2_ATAG_PERR = 24 ;
+static const uint8_t P9N2_EX_L2_ERR_RPT0_FIR14_CR3_TTAG_PERR = 25 ;
+static const uint8_t P9N2_EX_L2_ERR_RPT0_FIR14_CR3_ATAG_PERR = 26 ;
+static const uint8_t P9N2_EX_L2_ERR_RPT0_FIR14_RCMD0_ADDR_PERR = 27 ;
+static const uint8_t P9N2_EX_L2_ERR_RPT0_FIR14_RCMD1_ADDR_PERR = 28 ;
+static const uint8_t P9N2_EX_L2_ERR_RPT0_FIR14_RCMD2_ADDR_PERR = 29 ;
+static const uint8_t P9N2_EX_L2_ERR_RPT0_FIR14_RCMD3_ADDR_PERR = 30 ;
+static const uint8_t P9N2_EX_L2_ERR_RPT0_FIR9_PEC_PHASE3_TIMEOUT = 31 ;
+static const uint8_t P9N2_EX_L2_ERR_RPT0_FIR9_PEC_PHASE4_SAME = 32 ;
+static const uint8_t P9N2_EX_L2_ERR_RPT0_FIR9_PEC_PHASE4_RCCO_DISP_FAIL = 33 ;
+static const uint8_t P9N2_EX_L2_ERR_RPT0_FIR9_PEC_PHASE5_TIMEOUT = 34 ;
+static const uint8_t P9N2_EX_L2_ERR_RPT0_FIR14_B01_BOTH_ACTIVE = 35 ;
+static const uint8_t P9N2_EX_L2_ERR_RPT0_FIR14_PHANTOM_B01_REQ = 36 ;
+static const uint8_t P9N2_EX_L2_ERR_RPT0_FIR14_RC_UNEXP_F2_DATA = 37 ;
+static const uint8_t P9N2_EX_L2_ERR_RPT0_FIR14_RC_UNEXP_PURG_HIT = 38 ;
+static const uint8_t P9N2_EX_L2_ERR_RPT0_FIR14_RCX_UNEXP_IDLE_PBL3_DATA = 39 ;
+static const uint8_t P9N2_EX_L2_ERR_RPT0_FIR14_RCX_UNEXP_IDLE_PB_CRESP = 40 ;
+static const uint8_t P9N2_EX_L2_ERR_RPT0_FIR14_COX_UNEXP_IDLE_PB_CRESP = 41 ;
+
+static const uint8_t P9N2_EQ_ERR_RPT1_FIR14_RCX_UNEXP_IDLE_L3_CRESP = 0 ;
+static const uint8_t P9N2_EQ_ERR_RPT1_FIR14_RCX_UNEXP_IDLE_L3_DWDONE = 1 ;
+static const uint8_t P9N2_EQ_ERR_RPT1_FIR14_RCX_UNEXP_PB_RC_DTAG_PCHK = 2 ;
+static const uint8_t P9N2_EQ_ERR_RPT1_FIR14_DW_SET_REF_WITH_FLAG_IDLE = 3 ;
+static const uint8_t P9N2_EQ_ERR_RPT1_FIR14_KILL_REF_WITH_FLAG_IDLE = 4 ;
+static const uint8_t P9N2_EQ_ERR_RPT1_FIR14_DW_SET_SI_BY_MACH = 5 ;
+static const uint8_t P9N2_EQ_ERR_RPT1_FIR14_PD_DIR_MULT_HIT = 6 ;
+static const uint8_t P9N2_EQ_ERR_RPT1_FIR14_B0_SD_DIR_MULT_HIT = 7 ;
+static const uint8_t P9N2_EQ_ERR_RPT1_FIR14_B1_SD_DIR_MULT_HIT = 8 ;
+static const uint8_t P9N2_EQ_ERR_RPT1_FIR14_B2_SD_DIR_MULT_HIT = 9 ;
+static const uint8_t P9N2_EQ_ERR_RPT1_FIR14_B3_SD_DIR_MULT_HIT = 10 ;
+static const uint8_t P9N2_EQ_ERR_RPT1_FIR14_INVALID_SNP_CPS_STATU_RTN = 11 ;
+static const uint8_t P9N2_EQ_ERR_RPT1_FIR14_HANG_WAITING_FOR_FP_MATE = 12 ;
+static const uint8_t P9N2_EQ_ERR_RPT1_FIR14_BAD_FP_MATE = 13 ;
+static const uint8_t P9N2_EQ_ERR_RPT1_FIR14_LSU_TAG_REUSE = 14 ;
+static const uint8_t P9N2_EQ_ERR_RPT1_FIR14_IFU_MULT_REQ = 15 ;
+static const uint8_t P9N2_EQ_ERR_RPT1_FIR14_XPF_MULT_REQ = 16 ;
+static const uint8_t P9N2_EQ_ERR_RPT1_FIR14_XLT_QUEUE_OVRFLW = 17 ;
+static const uint8_t P9N2_EQ_ERR_RPT1_FIR14_L3PF_REQ = 18 ;
+static const uint8_t P9N2_EQ_ERR_RPT1_FIR14_NCU_TID_DONE = 19 ;
+static const uint8_t P9N2_EQ_ERR_RPT1_FIR11_LRU_MEM_INVALID_ABCD = 20 ;
+static const uint8_t P9N2_EQ_ERR_RPT1_FIR11_LRU_MEM_INVALID_EFGH = 21 ;
+static const uint8_t P9N2_EQ_ERR_RPT1_FIR14_STQ_COMING = 22 ;
+static const uint8_t P9N2_EQ_ERR_RPT1_FIR14_STQ_OVERFLOW = 23 ;
+static const uint8_t P9N2_EQ_ERR_RPT1_FIR14_RC_PBBUS_SFSTAT = 24 ;
+static const uint8_t P9N2_EQ_ERR_RPT1_FIR14_TMA_LARXA_VS_FRCMISS_SV = 25 ;
+static const uint8_t P9N2_EQ_ERR_RPT1_FIR37_RC_TGT_NODAL_REQ_CRESP_DINC = 26 ;
+static const uint8_t P9N2_EQ_ERR_RPT1_FIR37_SN_TGT_NODAL_REQ_CRESP_DINC = 27 ;
+static const uint8_t P9N2_EQ_ERR_RPT1_FIR14_RC_UNEXP_DIRSTAT_VS_DSECT_CHK = 28 ;
+static const uint8_t P9N2_EQ_ERR_RPT1_RSV = 29 ;
+
+static const uint8_t P9N2_EX_L2_ERR_RPT1_FIR14_RCX_UNEXP_IDLE_L3_CRESP = 0 ;
+static const uint8_t P9N2_EX_L2_ERR_RPT1_FIR14_RCX_UNEXP_IDLE_L3_DWDONE = 1 ;
+static const uint8_t P9N2_EX_L2_ERR_RPT1_FIR14_RCX_UNEXP_PB_RC_DTAG_PCHK = 2 ;
+static const uint8_t P9N2_EX_L2_ERR_RPT1_FIR14_DW_SET_REF_WITH_FLAG_IDLE = 3 ;
+static const uint8_t P9N2_EX_L2_ERR_RPT1_FIR14_KILL_REF_WITH_FLAG_IDLE = 4 ;
+static const uint8_t P9N2_EX_L2_ERR_RPT1_FIR14_DW_SET_SI_BY_MACH = 5 ;
+static const uint8_t P9N2_EX_L2_ERR_RPT1_FIR14_PD_DIR_MULT_HIT = 6 ;
+static const uint8_t P9N2_EX_L2_ERR_RPT1_FIR14_B0_SD_DIR_MULT_HIT = 7 ;
+static const uint8_t P9N2_EX_L2_ERR_RPT1_FIR14_B1_SD_DIR_MULT_HIT = 8 ;
+static const uint8_t P9N2_EX_L2_ERR_RPT1_FIR14_B2_SD_DIR_MULT_HIT = 9 ;
+static const uint8_t P9N2_EX_L2_ERR_RPT1_FIR14_B3_SD_DIR_MULT_HIT = 10 ;
+static const uint8_t P9N2_EX_L2_ERR_RPT1_FIR14_INVALID_SNP_CPS_STATU_RTN = 11 ;
+static const uint8_t P9N2_EX_L2_ERR_RPT1_FIR14_HANG_WAITING_FOR_FP_MATE = 12 ;
+static const uint8_t P9N2_EX_L2_ERR_RPT1_FIR14_BAD_FP_MATE = 13 ;
+static const uint8_t P9N2_EX_L2_ERR_RPT1_FIR14_LSU_TAG_REUSE = 14 ;
+static const uint8_t P9N2_EX_L2_ERR_RPT1_FIR14_IFU_MULT_REQ = 15 ;
+static const uint8_t P9N2_EX_L2_ERR_RPT1_FIR14_XPF_MULT_REQ = 16 ;
+static const uint8_t P9N2_EX_L2_ERR_RPT1_FIR14_XLT_QUEUE_OVRFLW = 17 ;
+static const uint8_t P9N2_EX_L2_ERR_RPT1_FIR14_L3PF_REQ = 18 ;
+static const uint8_t P9N2_EX_L2_ERR_RPT1_FIR14_NCU_TID_DONE = 19 ;
+static const uint8_t P9N2_EX_L2_ERR_RPT1_FIR11_LRU_MEM_INVALID_ABCD = 20 ;
+static const uint8_t P9N2_EX_L2_ERR_RPT1_FIR11_LRU_MEM_INVALID_EFGH = 21 ;
+static const uint8_t P9N2_EX_L2_ERR_RPT1_FIR14_STQ_COMING = 22 ;
+static const uint8_t P9N2_EX_L2_ERR_RPT1_FIR14_STQ_OVERFLOW = 23 ;
+static const uint8_t P9N2_EX_L2_ERR_RPT1_FIR14_RC_PBBUS_SFSTAT = 24 ;
+static const uint8_t P9N2_EX_L2_ERR_RPT1_FIR14_TMA_LARXA_VS_FRCMISS_SV = 25 ;
+static const uint8_t P9N2_EX_L2_ERR_RPT1_FIR37_RC_TGT_NODAL_REQ_CRESP_DINC = 26 ;
+static const uint8_t P9N2_EX_L2_ERR_RPT1_FIR37_SN_TGT_NODAL_REQ_CRESP_DINC = 27 ;
+static const uint8_t P9N2_EX_L2_ERR_RPT1_FIR14_RC_UNEXP_DIRSTAT_VS_DSECT_CHK = 28 ;
+static const uint8_t P9N2_EX_L2_ERR_RPT1_RSV = 29 ;
+
+static const uint8_t P9N2_EQ_ERR_RPT_REG_FIR0_OVERFLOW = 0 ;
+static const uint8_t P9N2_EQ_ERR_RPT_REG_FIR0_ILLEGAL_STORE_SIZE = 1 ;
+static const uint8_t P9N2_EQ_ERR_RPT_REG_FIR0_LD_AMO_SEQ = 2 ;
+static const uint8_t P9N2_EQ_ERR_RPT_REG_FIR0_CR0_TTAG_PERR = 3 ;
+static const uint8_t P9N2_EQ_ERR_RPT_REG_FIR0_CR0_ATAG_PERR = 4 ;
+static const uint8_t P9N2_EQ_ERR_RPT_REG_FIR0_CR1_TTAG_PERR = 5 ;
+static const uint8_t P9N2_EQ_ERR_RPT_REG_FIR0_CR1_ATAG_PERR = 6 ;
+static const uint8_t P9N2_EQ_ERR_RPT_REG_FIR0_CR2_TTAG_PERR = 7 ;
+static const uint8_t P9N2_EQ_ERR_RPT_REG_FIR0_CR2_ATAG_PERR = 8 ;
+static const uint8_t P9N2_EQ_ERR_RPT_REG_FIR0_CR3_TTAG_PERR = 9 ;
+static const uint8_t P9N2_EQ_ERR_RPT_REG_FIR0_CR3_ATAG_PERR = 10 ;
+static const uint8_t P9N2_EQ_ERR_RPT_REG_FIR0_SNP0_ADDR_PERR = 11 ;
+static const uint8_t P9N2_EQ_ERR_RPT_REG_FIR0_SNP0_TTAG_PERR = 12 ;
+static const uint8_t P9N2_EQ_ERR_RPT_REG_FIR0_SNP1_ADDR_PERR = 13 ;
+static const uint8_t P9N2_EQ_ERR_RPT_REG_FIR0_SNP1_TTAG_PERR = 14 ;
+static const uint8_t P9N2_EQ_ERR_RPT_REG_FIR0_PBARB_TRASHMODE = 15 ;
+static const uint8_t P9N2_EQ_ERR_RPT_REG_FIR1_TLBIE_BAD_OP = 16 ;
+static const uint8_t P9N2_EQ_ERR_RPT_REG_FIR1_MASTER_SEQ_ID_PAR = 17 ;
+static const uint8_t P9N2_EQ_ERR_RPT_REG_FIR1_SNOOP_TLBIE_SEQ_PARITY = 18 ;
+static const uint8_t P9N2_EQ_ERR_RPT_REG_FIR0_PURGE_LVL_ERR1 = 19 ;
+static const uint8_t P9N2_EQ_ERR_RPT_REG_FIR0_PURGE_LVL_ERR2 = 20 ;
+static const uint8_t P9N2_EQ_ERR_RPT_REG_FIR0_PURGE_ABORT_LVL_ERR1 = 21 ;
+static const uint8_t P9N2_EQ_ERR_RPT_REG_FIR0_PURGE_ABORT_LVL_ERR2 = 22 ;
+static const uint8_t P9N2_EQ_ERR_RPT_REG_FIR0_PURGE_DONE_LVL_ERR1 = 23 ;
+static const uint8_t P9N2_EQ_ERR_RPT_REG_FIR0_IMA_FSM_TIMEOUT = 24 ;
+static const uint8_t P9N2_EQ_ERR_RPT_REG_FIR0_PPE_WR_FSM_TIMEOUT = 25 ;
+static const uint8_t P9N2_EQ_ERR_RPT_REG_FIR0_PPE_RD_FSM_TIMEOUT = 26 ;
+static const uint8_t P9N2_EQ_ERR_RPT_REG_FIR0_TLB_DATA_PAR = 27 ;
+static const uint8_t P9N2_EQ_ERR_RPT_REG_FIR19_LD_TGT_NODAL_DINC = 28 ;
+static const uint8_t P9N2_EQ_ERR_RPT_REG_FIR19_ST_TGT_NODAL_DINC = 29 ;
+
+static const uint8_t P9N2_EX_ERR_RPT_REG_FIR0_OVERFLOW = 0 ;
+static const uint8_t P9N2_EX_ERR_RPT_REG_FIR0_ILLEGAL_STORE_SIZE = 1 ;
+static const uint8_t P9N2_EX_ERR_RPT_REG_FIR0_LD_AMO_SEQ = 2 ;
+static const uint8_t P9N2_EX_ERR_RPT_REG_FIR0_CR0_TTAG_PERR = 3 ;
+static const uint8_t P9N2_EX_ERR_RPT_REG_FIR0_CR0_ATAG_PERR = 4 ;
+static const uint8_t P9N2_EX_ERR_RPT_REG_FIR0_CR1_TTAG_PERR = 5 ;
+static const uint8_t P9N2_EX_ERR_RPT_REG_FIR0_CR1_ATAG_PERR = 6 ;
+static const uint8_t P9N2_EX_ERR_RPT_REG_FIR0_CR2_TTAG_PERR = 7 ;
+static const uint8_t P9N2_EX_ERR_RPT_REG_FIR0_CR2_ATAG_PERR = 8 ;
+static const uint8_t P9N2_EX_ERR_RPT_REG_FIR0_CR3_TTAG_PERR = 9 ;
+static const uint8_t P9N2_EX_ERR_RPT_REG_FIR0_CR3_ATAG_PERR = 10 ;
+static const uint8_t P9N2_EX_ERR_RPT_REG_FIR0_SNP0_ADDR_PERR = 11 ;
+static const uint8_t P9N2_EX_ERR_RPT_REG_FIR0_SNP0_TTAG_PERR = 12 ;
+static const uint8_t P9N2_EX_ERR_RPT_REG_FIR0_SNP1_ADDR_PERR = 13 ;
+static const uint8_t P9N2_EX_ERR_RPT_REG_FIR0_SNP1_TTAG_PERR = 14 ;
+static const uint8_t P9N2_EX_ERR_RPT_REG_FIR0_PBARB_TRASHMODE = 15 ;
+static const uint8_t P9N2_EX_ERR_RPT_REG_FIR1_TLBIE_BAD_OP = 16 ;
+static const uint8_t P9N2_EX_ERR_RPT_REG_FIR1_MASTER_SEQ_ID_PAR = 17 ;
+static const uint8_t P9N2_EX_ERR_RPT_REG_FIR1_SNOOP_TLBIE_SEQ_PARITY = 18 ;
+static const uint8_t P9N2_EX_ERR_RPT_REG_FIR0_PURGE_LVL_ERR1 = 19 ;
+static const uint8_t P9N2_EX_ERR_RPT_REG_FIR0_PURGE_LVL_ERR2 = 20 ;
+static const uint8_t P9N2_EX_ERR_RPT_REG_FIR0_PURGE_ABORT_LVL_ERR1 = 21 ;
+static const uint8_t P9N2_EX_ERR_RPT_REG_FIR0_PURGE_ABORT_LVL_ERR2 = 22 ;
+static const uint8_t P9N2_EX_ERR_RPT_REG_FIR0_PURGE_DONE_LVL_ERR1 = 23 ;
+static const uint8_t P9N2_EX_ERR_RPT_REG_FIR0_IMA_FSM_TIMEOUT = 24 ;
+static const uint8_t P9N2_EX_ERR_RPT_REG_FIR0_PPE_WR_FSM_TIMEOUT = 25 ;
+static const uint8_t P9N2_EX_ERR_RPT_REG_FIR0_PPE_RD_FSM_TIMEOUT = 26 ;
+static const uint8_t P9N2_EX_ERR_RPT_REG_FIR0_TLB_DATA_PAR = 27 ;
+static const uint8_t P9N2_EX_ERR_RPT_REG_FIR19_LD_TGT_NODAL_DINC = 28 ;
+static const uint8_t P9N2_EX_ERR_RPT_REG_FIR19_ST_TGT_NODAL_DINC = 29 ;
+
+static const uint8_t P9N2_EQ_ERR_STATUS_REG_SERIAL_SHIFTCNT_MODEREG_PARITY_ERR_HOLD = 0 ;
+static const uint8_t P9N2_EQ_ERR_STATUS_REG_THERM_MODEREG_PARITY_ERR_HOLD = 1 ;
+static const uint8_t P9N2_EQ_ERR_STATUS_REG_SKITTER_MODEREG_PARITY_ERR_HOLD = 2 ;
+static const uint8_t P9N2_EQ_ERR_STATUS_REG_SKITTER_FORCEREG_PARITY_ERR_HOLD = 3 ;
+static const uint8_t P9N2_EQ_ERR_STATUS_REG_SCAN_INIT_VERSION_REG_PARITY_ERR_HOLD = 4 ;
+static const uint8_t P9N2_EQ_ERR_STATUS_REG_VOLT_MODEREG_PARITY_ERR_HOLD = 5 ;
+static const uint8_t P9N2_EQ_ERR_STATUS_REG_SKITTER_CLKSRCREG_PARITY_ERR_HOLD = 6 ;
+static const uint8_t P9N2_EQ_ERR_STATUS_REG_COUNT_STATE_ERR_HOLD = 7 ;
+static const uint8_t P9N2_EQ_ERR_STATUS_REG_RUN_STATE_ERR_HOLD = 8 ;
+static const uint8_t P9N2_EQ_ERR_STATUS_REG_THRES_THERM_STATE_ERR_HOLD = 9 ;
+static const uint8_t P9N2_EQ_ERR_STATUS_REG_THRES_THERM_OVERFLOW_ERR_HOLD = 10 ;
+static const uint8_t P9N2_EQ_ERR_STATUS_REG_SHIFTER_PARITY_ERR_HOLD = 11 ;
+static const uint8_t P9N2_EQ_ERR_STATUS_REG_SHIFTER_VALID_ERR_HOLD = 12 ;
+static const uint8_t P9N2_EQ_ERR_STATUS_REG_TIMEOUT_ERR_HOLD = 13 ;
+static const uint8_t P9N2_EQ_ERR_STATUS_REG_F_SKITTER_ERR_HOLD = 14 ;
+static const uint8_t P9N2_EQ_ERR_STATUS_REG_PCB_ERR_HOLD_OUT = 15 ;
+static const uint8_t P9N2_EQ_ERR_STATUS_REG_SERIAL_SHIFTCNT_MODEREG_PARITY_MASK = 16 ;
+static const uint8_t P9N2_EQ_ERR_STATUS_REG_THERM_MODEREG_PARITY_MASK = 17 ;
+static const uint8_t P9N2_EQ_ERR_STATUS_REG_SKITTER_MODEREG_PARITY_MASK = 18 ;
+static const uint8_t P9N2_EQ_ERR_STATUS_REG_SKITTER_FORCEREG_PARITY_MASK = 19 ;
+static const uint8_t P9N2_EQ_ERR_STATUS_REG_SCAN_INIT_VERSION_PARITY_MASK = 20 ;
+static const uint8_t P9N2_EQ_ERR_STATUS_REG_VOLT_MODEREG_PARITY_MASK = 21 ;
+static const uint8_t P9N2_EQ_ERR_STATUS_REG_COUNT_STATE_MASK = 23 ;
+static const uint8_t P9N2_EQ_ERR_STATUS_REG_RUN_STATE_MASK = 24 ;
+static const uint8_t P9N2_EQ_ERR_STATUS_REG_THRES_STATE_MASK = 25 ;
+static const uint8_t P9N2_EQ_ERR_STATUS_REG_OVERFLOW_MASK = 26 ;
+static const uint8_t P9N2_EQ_ERR_STATUS_REG_SHIFTER_PARITY_MASK = 27 ;
+static const uint8_t P9N2_EQ_ERR_STATUS_REG_SHIFTER_VALID_MASK = 28 ;
+static const uint8_t P9N2_EQ_ERR_STATUS_REG_TIMEOUT_MASK = 29 ;
+static const uint8_t P9N2_EQ_ERR_STATUS_REG_F_SKITTER_READ_MASK = 30 ;
+static const uint8_t P9N2_EQ_ERR_STATUS_REG_PCB_MASK = 31 ;
+static const uint8_t P9N2_EQ_ERR_STATUS_REG_COUNT_STATE_LT = 40 ;
+static const uint8_t P9N2_EQ_ERR_STATUS_REG_COUNT_STATE_LT_LEN = 4 ;
+static const uint8_t P9N2_EQ_ERR_STATUS_REG_RUN_STATE_LT = 44 ;
+static const uint8_t P9N2_EQ_ERR_STATUS_REG_RUN_STATE_LT_LEN = 3 ;
+static const uint8_t P9N2_EQ_ERR_STATUS_REG_SHIFT_DTS_LT = 47 ;
+static const uint8_t P9N2_EQ_ERR_STATUS_REG_SHIFT_VOLT_LT = 48 ;
+static const uint8_t P9N2_EQ_ERR_STATUS_REG_READ_STATE_LT = 49 ;
+static const uint8_t P9N2_EQ_ERR_STATUS_REG_READ_STATE_LT_LEN = 2 ;
+static const uint8_t P9N2_EQ_ERR_STATUS_REG_WRITE_STATE_LT = 51 ;
+static const uint8_t P9N2_EQ_ERR_STATUS_REG_WRITE_STATE_LT_LEN = 4 ;
+static const uint8_t P9N2_EQ_ERR_STATUS_REG_SAMPLE_DTS_LT = 55 ;
+static const uint8_t P9N2_EQ_ERR_STATUS_REG_MEASURE_VOLT_LT = 56 ;
+static const uint8_t P9N2_EQ_ERR_STATUS_REG_READ_CPM_LT = 57 ;
+static const uint8_t P9N2_EQ_ERR_STATUS_REG_WRITE_CPM_LT = 58 ;
+static const uint8_t P9N2_EQ_ERR_STATUS_REG_UNUSED = 59 ;
+
+static const uint8_t P9N2_EX_ERR_STATUS_REG_SERIAL_SHIFTCNT_MODEREG_PARITY_ERR_HOLD = 0 ;
+static const uint8_t P9N2_EX_ERR_STATUS_REG_THERM_MODEREG_PARITY_ERR_HOLD = 1 ;
+static const uint8_t P9N2_EX_ERR_STATUS_REG_SKITTER_MODEREG_PARITY_ERR_HOLD = 2 ;
+static const uint8_t P9N2_EX_ERR_STATUS_REG_SKITTER_FORCEREG_PARITY_ERR_HOLD = 3 ;
+static const uint8_t P9N2_EX_ERR_STATUS_REG_SCAN_INIT_VERSION_REG_PARITY_ERR_HOLD = 4 ;
+static const uint8_t P9N2_EX_ERR_STATUS_REG_VOLT_MODEREG_PARITY_ERR_HOLD = 5 ;
+static const uint8_t P9N2_EX_ERR_STATUS_REG_SKITTER_CLKSRCREG_PARITY_ERR_HOLD = 6 ;
+static const uint8_t P9N2_EX_ERR_STATUS_REG_COUNT_STATE_ERR_HOLD = 7 ;
+static const uint8_t P9N2_EX_ERR_STATUS_REG_RUN_STATE_ERR_HOLD = 8 ;
+static const uint8_t P9N2_EX_ERR_STATUS_REG_THRES_THERM_STATE_ERR_HOLD = 9 ;
+static const uint8_t P9N2_EX_ERR_STATUS_REG_THRES_THERM_OVERFLOW_ERR_HOLD = 10 ;
+static const uint8_t P9N2_EX_ERR_STATUS_REG_SHIFTER_PARITY_ERR_HOLD = 11 ;
+static const uint8_t P9N2_EX_ERR_STATUS_REG_SHIFTER_VALID_ERR_HOLD = 12 ;
+static const uint8_t P9N2_EX_ERR_STATUS_REG_TIMEOUT_ERR_HOLD = 13 ;
+static const uint8_t P9N2_EX_ERR_STATUS_REG_F_SKITTER_ERR_HOLD = 14 ;
+static const uint8_t P9N2_EX_ERR_STATUS_REG_PCB_ERR_HOLD_OUT = 15 ;
+static const uint8_t P9N2_EX_ERR_STATUS_REG_SERIAL_SHIFTCNT_MODEREG_PARITY_MASK = 16 ;
+static const uint8_t P9N2_EX_ERR_STATUS_REG_THERM_MODEREG_PARITY_MASK = 17 ;
+static const uint8_t P9N2_EX_ERR_STATUS_REG_SKITTER_MODEREG_PARITY_MASK = 18 ;
+static const uint8_t P9N2_EX_ERR_STATUS_REG_SKITTER_FORCEREG_PARITY_MASK = 19 ;
+static const uint8_t P9N2_EX_ERR_STATUS_REG_SCAN_INIT_VERSION_PARITY_MASK = 20 ;
+static const uint8_t P9N2_EX_ERR_STATUS_REG_VOLT_MODEREG_PARITY_MASK = 21 ;
+static const uint8_t P9N2_EX_ERR_STATUS_REG_COUNT_STATE_MASK = 23 ;
+static const uint8_t P9N2_EX_ERR_STATUS_REG_RUN_STATE_MASK = 24 ;
+static const uint8_t P9N2_EX_ERR_STATUS_REG_THRES_STATE_MASK = 25 ;
+static const uint8_t P9N2_EX_ERR_STATUS_REG_OVERFLOW_MASK = 26 ;
+static const uint8_t P9N2_EX_ERR_STATUS_REG_SHIFTER_PARITY_MASK = 27 ;
+static const uint8_t P9N2_EX_ERR_STATUS_REG_SHIFTER_VALID_MASK = 28 ;
+static const uint8_t P9N2_EX_ERR_STATUS_REG_TIMEOUT_MASK = 29 ;
+static const uint8_t P9N2_EX_ERR_STATUS_REG_F_SKITTER_READ_MASK = 30 ;
+static const uint8_t P9N2_EX_ERR_STATUS_REG_PCB_MASK = 31 ;
+static const uint8_t P9N2_EX_ERR_STATUS_REG_COUNT_STATE_LT = 40 ;
+static const uint8_t P9N2_EX_ERR_STATUS_REG_COUNT_STATE_LT_LEN = 4 ;
+static const uint8_t P9N2_EX_ERR_STATUS_REG_RUN_STATE_LT = 44 ;
+static const uint8_t P9N2_EX_ERR_STATUS_REG_RUN_STATE_LT_LEN = 3 ;
+static const uint8_t P9N2_EX_ERR_STATUS_REG_SHIFT_DTS_LT = 47 ;
+static const uint8_t P9N2_EX_ERR_STATUS_REG_SHIFT_VOLT_LT = 48 ;
+static const uint8_t P9N2_EX_ERR_STATUS_REG_READ_STATE_LT = 49 ;
+static const uint8_t P9N2_EX_ERR_STATUS_REG_READ_STATE_LT_LEN = 2 ;
+static const uint8_t P9N2_EX_ERR_STATUS_REG_WRITE_STATE_LT = 51 ;
+static const uint8_t P9N2_EX_ERR_STATUS_REG_WRITE_STATE_LT_LEN = 4 ;
+static const uint8_t P9N2_EX_ERR_STATUS_REG_SAMPLE_DTS_LT = 55 ;
+static const uint8_t P9N2_EX_ERR_STATUS_REG_MEASURE_VOLT_LT = 56 ;
+static const uint8_t P9N2_EX_ERR_STATUS_REG_READ_CPM_LT = 57 ;
+static const uint8_t P9N2_EX_ERR_STATUS_REG_WRITE_CPM_LT = 58 ;
+static const uint8_t P9N2_EX_ERR_STATUS_REG_UNUSED = 59 ;
+
+static const uint8_t P9N2_C_ERR_STATUS_REG_SERIAL_SHIFTCNT_MODEREG_PARITY_ERR_HOLD = 0 ;
+static const uint8_t P9N2_C_ERR_STATUS_REG_THERM_MODEREG_PARITY_ERR_HOLD = 1 ;
+static const uint8_t P9N2_C_ERR_STATUS_REG_SKITTER_MODEREG_PARITY_ERR_HOLD = 2 ;
+static const uint8_t P9N2_C_ERR_STATUS_REG_SKITTER_FORCEREG_PARITY_ERR_HOLD = 3 ;
+static const uint8_t P9N2_C_ERR_STATUS_REG_SCAN_INIT_VERSION_REG_PARITY_ERR_HOLD = 4 ;
+static const uint8_t P9N2_C_ERR_STATUS_REG_VOLT_MODEREG_PARITY_ERR_HOLD = 5 ;
+static const uint8_t P9N2_C_ERR_STATUS_REG_SKITTER_CLKSRCREG_PARITY_ERR_HOLD = 6 ;
+static const uint8_t P9N2_C_ERR_STATUS_REG_COUNT_STATE_ERR_HOLD = 7 ;
+static const uint8_t P9N2_C_ERR_STATUS_REG_RUN_STATE_ERR_HOLD = 8 ;
+static const uint8_t P9N2_C_ERR_STATUS_REG_THRES_THERM_STATE_ERR_HOLD = 9 ;
+static const uint8_t P9N2_C_ERR_STATUS_REG_THRES_THERM_OVERFLOW_ERR_HOLD = 10 ;
+static const uint8_t P9N2_C_ERR_STATUS_REG_SHIFTER_PARITY_ERR_HOLD = 11 ;
+static const uint8_t P9N2_C_ERR_STATUS_REG_SHIFTER_VALID_ERR_HOLD = 12 ;
+static const uint8_t P9N2_C_ERR_STATUS_REG_TIMEOUT_ERR_HOLD = 13 ;
+static const uint8_t P9N2_C_ERR_STATUS_REG_F_SKITTER_ERR_HOLD = 14 ;
+static const uint8_t P9N2_C_ERR_STATUS_REG_PCB_ERR_HOLD_OUT = 15 ;
+static const uint8_t P9N2_C_ERR_STATUS_REG_SERIAL_SHIFTCNT_MODEREG_PARITY_MASK = 16 ;
+static const uint8_t P9N2_C_ERR_STATUS_REG_THERM_MODEREG_PARITY_MASK = 17 ;
+static const uint8_t P9N2_C_ERR_STATUS_REG_SKITTER_MODEREG_PARITY_MASK = 18 ;
+static const uint8_t P9N2_C_ERR_STATUS_REG_SKITTER_FORCEREG_PARITY_MASK = 19 ;
+static const uint8_t P9N2_C_ERR_STATUS_REG_SCAN_INIT_VERSION_PARITY_MASK = 20 ;
+static const uint8_t P9N2_C_ERR_STATUS_REG_VOLT_MODEREG_PARITY_MASK = 21 ;
+static const uint8_t P9N2_C_ERR_STATUS_REG_COUNT_STATE_MASK = 23 ;
+static const uint8_t P9N2_C_ERR_STATUS_REG_RUN_STATE_MASK = 24 ;
+static const uint8_t P9N2_C_ERR_STATUS_REG_THRES_STATE_MASK = 25 ;
+static const uint8_t P9N2_C_ERR_STATUS_REG_OVERFLOW_MASK = 26 ;
+static const uint8_t P9N2_C_ERR_STATUS_REG_SHIFTER_PARITY_MASK = 27 ;
+static const uint8_t P9N2_C_ERR_STATUS_REG_SHIFTER_VALID_MASK = 28 ;
+static const uint8_t P9N2_C_ERR_STATUS_REG_TIMEOUT_MASK = 29 ;
+static const uint8_t P9N2_C_ERR_STATUS_REG_F_SKITTER_READ_MASK = 30 ;
+static const uint8_t P9N2_C_ERR_STATUS_REG_PCB_MASK = 31 ;
+static const uint8_t P9N2_C_ERR_STATUS_REG_COUNT_STATE_LT = 40 ;
+static const uint8_t P9N2_C_ERR_STATUS_REG_COUNT_STATE_LT_LEN = 4 ;
+static const uint8_t P9N2_C_ERR_STATUS_REG_RUN_STATE_LT = 44 ;
+static const uint8_t P9N2_C_ERR_STATUS_REG_RUN_STATE_LT_LEN = 3 ;
+static const uint8_t P9N2_C_ERR_STATUS_REG_SHIFT_DTS_LT = 47 ;
+static const uint8_t P9N2_C_ERR_STATUS_REG_SHIFT_VOLT_LT = 48 ;
+static const uint8_t P9N2_C_ERR_STATUS_REG_READ_STATE_LT = 49 ;
+static const uint8_t P9N2_C_ERR_STATUS_REG_READ_STATE_LT_LEN = 2 ;
+static const uint8_t P9N2_C_ERR_STATUS_REG_WRITE_STATE_LT = 51 ;
+static const uint8_t P9N2_C_ERR_STATUS_REG_WRITE_STATE_LT_LEN = 4 ;
+static const uint8_t P9N2_C_ERR_STATUS_REG_SAMPLE_DTS_LT = 55 ;
+static const uint8_t P9N2_C_ERR_STATUS_REG_MEASURE_VOLT_LT = 56 ;
+static const uint8_t P9N2_C_ERR_STATUS_REG_READ_CPM_LT = 57 ;
+static const uint8_t P9N2_C_ERR_STATUS_REG_WRITE_CPM_LT = 58 ;
+static const uint8_t P9N2_C_ERR_STATUS_REG_UNUSED = 59 ;
+
+static const uint8_t P9N2_EQ_FIR_ACTION0_REG_ACTION0 = 0 ;
+static const uint8_t P9N2_EQ_FIR_ACTION0_REG_ACTION0_LEN = 31 ;
+
+static const uint8_t P9N2_EX_FIR_ACTION0_REG_ACTION0 = 0 ;
+static const uint8_t P9N2_EX_FIR_ACTION0_REG_ACTION0_LEN = 31 ;
+
+static const uint8_t P9N2_EX_L2_FIR_ACTION0_REG_ACTION0 = 0 ;
+static const uint8_t P9N2_EX_L2_FIR_ACTION0_REG_ACTION0_LEN = 42 ;
+
+static const uint8_t P9N2_EX_L3_FIR_ACTION0_REG_ACTION0 = 0 ;
+static const uint8_t P9N2_EX_L3_FIR_ACTION0_REG_ACTION0_LEN = 35 ;
+
+static const uint8_t P9N2_EQ_FIR_ACTION1_REG_ACTION1 = 0 ;
+static const uint8_t P9N2_EQ_FIR_ACTION1_REG_ACTION1_LEN = 31 ;
+
+static const uint8_t P9N2_EX_FIR_ACTION1_REG_ACTION1 = 0 ;
+static const uint8_t P9N2_EX_FIR_ACTION1_REG_ACTION1_LEN = 31 ;
+
+static const uint8_t P9N2_EX_L2_FIR_ACTION1_REG_ACTION1 = 0 ;
+static const uint8_t P9N2_EX_L2_FIR_ACTION1_REG_ACTION1_LEN = 42 ;
+
+static const uint8_t P9N2_EX_L3_FIR_ACTION1_REG_ACTION1 = 0 ;
+static const uint8_t P9N2_EX_L3_FIR_ACTION1_REG_ACTION1_LEN = 35 ;
+
+static const uint8_t P9N2_EX_L2_FIR_ERR_INJ_TO_LSU = 0 ;
+static const uint8_t P9N2_EX_L2_FIR_ERR_INJ_TO_IFU = 1 ;
+static const uint8_t P9N2_EX_L2_FIR_ERR_INJ_TO_ISU = 2 ;
+static const uint8_t P9N2_EX_L2_FIR_ERR_INJ_TO_VSU = 3 ;
+static const uint8_t P9N2_EX_L2_FIR_ERR_INJ_TO_PC = 4 ;
+static const uint8_t P9N2_EX_L2_FIR_ERR_INJ_RESERVED = 5 ;
+static const uint8_t P9N2_EX_L2_FIR_ERR_INJ_ERROR_PULSE_OR_LEVEL = 6 ;
+static const uint8_t P9N2_EX_L2_FIR_ERR_INJ_CLEAR_STICKY_LEVEL = 7 ;
+static const uint8_t P9N2_EX_L2_FIR_ERR_INJ_SCOM_WRITE = 8 ;
+static const uint8_t P9N2_EX_L2_FIR_ERR_INJ_TRIGGER = 9 ;
+static const uint8_t P9N2_EX_L2_FIR_ERR_INJ_TRIGGER1 = 10 ;
+static const uint8_t P9N2_EX_L2_FIR_ERR_INJ_TOD_TAP = 11 ;
+static const uint8_t P9N2_EX_L2_FIR_ERR_INJ_BLOCK = 12 ;
+static const uint8_t P9N2_EX_L2_FIR_ERR_INJ_BLOCK_LEN = 2 ;
+static const uint8_t P9N2_EX_L2_FIR_ERR_INJ_DELAY_AFTER_BLOCK = 14 ;
+static const uint8_t P9N2_EX_L2_FIR_ERR_INJ_RECOVERY_BLK = 15 ;
+static const uint8_t P9N2_EX_L2_FIR_ERR_INJ_RECOVERY_BLK_EXTEND = 16 ;
+static const uint8_t P9N2_EX_L2_FIR_ERR_INJ_TAP_SEL = 17 ;
+static const uint8_t P9N2_EX_L2_FIR_ERR_INJ_TAP_SEL_LEN = 4 ;
+static const uint8_t P9N2_EX_L2_FIR_ERR_INJ_HYP_BLOCK = 21 ;
+static const uint8_t P9N2_EX_L2_FIR_ERR_INJ_HYP_BLOCK_LEN = 3 ;
+
+static const uint8_t P9N2_C_FIR_ERR_INJ_TO_LSU = 0 ;
+static const uint8_t P9N2_C_FIR_ERR_INJ_TO_IFU = 1 ;
+static const uint8_t P9N2_C_FIR_ERR_INJ_TO_ISU = 2 ;
+static const uint8_t P9N2_C_FIR_ERR_INJ_TO_VSU = 3 ;
+static const uint8_t P9N2_C_FIR_ERR_INJ_TO_PC = 4 ;
+static const uint8_t P9N2_C_FIR_ERR_INJ_RESERVED = 5 ;
+static const uint8_t P9N2_C_FIR_ERR_INJ_ERROR_PULSE_OR_LEVEL = 6 ;
+static const uint8_t P9N2_C_FIR_ERR_INJ_CLEAR_STICKY_LEVEL = 7 ;
+static const uint8_t P9N2_C_FIR_ERR_INJ_SCOM_WRITE = 8 ;
+static const uint8_t P9N2_C_FIR_ERR_INJ_TRIGGER = 9 ;
+static const uint8_t P9N2_C_FIR_ERR_INJ_TRIGGER1 = 10 ;
+static const uint8_t P9N2_C_FIR_ERR_INJ_TOD_TAP = 11 ;
+static const uint8_t P9N2_C_FIR_ERR_INJ_BLOCK = 12 ;
+static const uint8_t P9N2_C_FIR_ERR_INJ_BLOCK_LEN = 2 ;
+static const uint8_t P9N2_C_FIR_ERR_INJ_DELAY_AFTER_BLOCK = 14 ;
+static const uint8_t P9N2_C_FIR_ERR_INJ_RECOVERY_BLK = 15 ;
+static const uint8_t P9N2_C_FIR_ERR_INJ_RECOVERY_BLK_EXTEND = 16 ;
+static const uint8_t P9N2_C_FIR_ERR_INJ_TAP_SEL = 17 ;
+static const uint8_t P9N2_C_FIR_ERR_INJ_TAP_SEL_LEN = 4 ;
+static const uint8_t P9N2_C_FIR_ERR_INJ_HYP_BLOCK = 21 ;
+static const uint8_t P9N2_C_FIR_ERR_INJ_HYP_BLOCK_LEN = 3 ;
+
+static const uint8_t P9N2_EX_L2_FIR_HOLD_OUT_CY_FIR_LOCAL_XSTOP_HOLD_OUT = 0 ;
+static const uint8_t P9N2_EX_L2_FIR_HOLD_OUT_CY_FIR_RECOV_HOLD_OUT = 1 ;
+static const uint8_t P9N2_EX_L2_FIR_HOLD_OUT_CY_FIR_SYS_XSTOP_HOLD_OUT = 2 ;
+static const uint8_t P9N2_EX_L2_FIR_HOLD_OUT_FIR_ERR_INJ_REC_HOLD_OUT = 3 ;
+static const uint8_t P9N2_EX_L2_FIR_HOLD_OUT_FIR_ERR_INJ_XSTP_HOLD_OUT = 4 ;
+static const uint8_t P9N2_EX_L2_FIR_HOLD_OUT_FIR_PARITY_HOLD_OUT = 5 ;
+static const uint8_t P9N2_EX_L2_FIR_HOLD_OUT_FIR_SCOM_HOLD_OUT = 6 ;
+static const uint8_t P9N2_EX_L2_FIR_HOLD_OUT_L2_UE_OVER_THRES_HOLD_OUT = 7 ;
+static const uint8_t P9N2_EX_L2_FIR_HOLD_OUT_PHYP_ERR_INJ_HOLD_OUT = 8 ;
+static const uint8_t P9N2_EX_L2_FIR_HOLD_OUT_RAM_EXCEPTION_XSTOP_HOLD_OUT = 9 ;
+static const uint8_t P9N2_EX_L2_FIR_HOLD_OUT_RAM_INSTR_REG_ACCESS_HOLD_OUT = 10 ;
+static const uint8_t P9N2_EX_L2_FIR_HOLD_OUT_RECOV_ERR_DURING_RAM_MODE_HOLD_OUT = 11 ;
+static const uint8_t P9N2_EX_L2_FIR_HOLD_OUT_RECOV_ERR_DURING_SMT_MODE_CHANGE_HOLD_OUT = 12 ;
+static const uint8_t P9N2_EX_L2_FIR_HOLD_OUT_ECC_REF_STATE_HOLD_OUT = 13 ;
+static const uint8_t P9N2_EX_L2_FIR_HOLD_OUT_FWD_PROG_HOLD_OUT = 14 ;
+static const uint8_t P9N2_EX_L2_FIR_HOLD_OUT_RECONFIG_STATE_HOLD_OUT = 15 ;
+static const uint8_t P9N2_EX_L2_FIR_HOLD_OUT_RECOV_ABIST_TIMEOUT_HOLD_OUT = 16 ;
+static const uint8_t P9N2_EX_L2_FIR_HOLD_OUT_RECOV_DISABLED_HOLD_OUT = 17 ;
+static const uint8_t P9N2_EX_L2_FIR_HOLD_OUT_RCVY_STATE_HOLD_OUT = 18 ;
+static const uint8_t P9N2_EX_L2_FIR_HOLD_OUT_SD_LOG_XSTOP_HOLD_OUT = 19 ;
+static const uint8_t P9N2_EX_L2_FIR_HOLD_OUT_XSTOP_ON_DBG_TRIGGER_HOLD_OUT = 20 ;
+
+static const uint8_t P9N2_C_FIR_HOLD_OUT_CY_FIR_LOCAL_XSTOP_HOLD_OUT = 0 ;
+static const uint8_t P9N2_C_FIR_HOLD_OUT_CY_FIR_RECOV_HOLD_OUT = 1 ;
+static const uint8_t P9N2_C_FIR_HOLD_OUT_CY_FIR_SYS_XSTOP_HOLD_OUT = 2 ;
+static const uint8_t P9N2_C_FIR_HOLD_OUT_FIR_ERR_INJ_REC_HOLD_OUT = 3 ;
+static const uint8_t P9N2_C_FIR_HOLD_OUT_FIR_ERR_INJ_XSTP_HOLD_OUT = 4 ;
+static const uint8_t P9N2_C_FIR_HOLD_OUT_FIR_PARITY_HOLD_OUT = 5 ;
+static const uint8_t P9N2_C_FIR_HOLD_OUT_FIR_SCOM_HOLD_OUT = 6 ;
+static const uint8_t P9N2_C_FIR_HOLD_OUT_L2_UE_OVER_THRES_HOLD_OUT = 7 ;
+static const uint8_t P9N2_C_FIR_HOLD_OUT_PHYP_ERR_INJ_HOLD_OUT = 8 ;
+static const uint8_t P9N2_C_FIR_HOLD_OUT_RAM_EXCEPTION_XSTOP_HOLD_OUT = 9 ;
+static const uint8_t P9N2_C_FIR_HOLD_OUT_RAM_INSTR_REG_ACCESS_HOLD_OUT = 10 ;
+static const uint8_t P9N2_C_FIR_HOLD_OUT_RECOV_ERR_DURING_RAM_MODE_HOLD_OUT = 11 ;
+static const uint8_t P9N2_C_FIR_HOLD_OUT_RECOV_ERR_DURING_SMT_MODE_CHANGE_HOLD_OUT = 12 ;
+static const uint8_t P9N2_C_FIR_HOLD_OUT_ECC_REF_STATE_HOLD_OUT = 13 ;
+static const uint8_t P9N2_C_FIR_HOLD_OUT_FWD_PROG_HOLD_OUT = 14 ;
+static const uint8_t P9N2_C_FIR_HOLD_OUT_RECONFIG_STATE_HOLD_OUT = 15 ;
+static const uint8_t P9N2_C_FIR_HOLD_OUT_RECOV_ABIST_TIMEOUT_HOLD_OUT = 16 ;
+static const uint8_t P9N2_C_FIR_HOLD_OUT_RECOV_DISABLED_HOLD_OUT = 17 ;
+static const uint8_t P9N2_C_FIR_HOLD_OUT_RCVY_STATE_HOLD_OUT = 18 ;
+static const uint8_t P9N2_C_FIR_HOLD_OUT_SD_LOG_XSTOP_HOLD_OUT = 19 ;
+static const uint8_t P9N2_C_FIR_HOLD_OUT_XSTOP_ON_DBG_TRIGGER_HOLD_OUT = 20 ;
+
+static const uint8_t P9N2_EQ_FIR_MASK_IN0 = 0 ;
+static const uint8_t P9N2_EQ_FIR_MASK_IN1 = 1 ;
+static const uint8_t P9N2_EQ_FIR_MASK_IN2 = 2 ;
+static const uint8_t P9N2_EQ_FIR_MASK_IN3 = 3 ;
+static const uint8_t P9N2_EQ_FIR_MASK_IN4 = 4 ;
+static const uint8_t P9N2_EQ_FIR_MASK_IN5 = 5 ;
+static const uint8_t P9N2_EQ_FIR_MASK_IN6 = 6 ;
+static const uint8_t P9N2_EQ_FIR_MASK_IN7 = 7 ;
+static const uint8_t P9N2_EQ_FIR_MASK_IN8 = 8 ;
+static const uint8_t P9N2_EQ_FIR_MASK_IN9 = 9 ;
+static const uint8_t P9N2_EQ_FIR_MASK_IN10 = 10 ;
+static const uint8_t P9N2_EQ_FIR_MASK_IN11 = 11 ;
+static const uint8_t P9N2_EQ_FIR_MASK_IN12 = 12 ;
+static const uint8_t P9N2_EQ_FIR_MASK_IN13 = 13 ;
+static const uint8_t P9N2_EQ_FIR_MASK_IN13_LEN = 13 ;
+static const uint8_t P9N2_EQ_FIR_MASK_IN26 = 26 ;
+
+static const uint8_t P9N2_EX_FIR_MASK_IN0 = 0 ;
+static const uint8_t P9N2_EX_FIR_MASK_IN1 = 1 ;
+static const uint8_t P9N2_EX_FIR_MASK_IN2 = 2 ;
+static const uint8_t P9N2_EX_FIR_MASK_IN3 = 3 ;
+static const uint8_t P9N2_EX_FIR_MASK_IN4 = 4 ;
+static const uint8_t P9N2_EX_FIR_MASK_IN5 = 5 ;
+static const uint8_t P9N2_EX_FIR_MASK_IN5_LEN = 21 ;
+static const uint8_t P9N2_EX_FIR_MASK_IN26 = 26 ;
+
+static const uint8_t P9N2_C_FIR_MASK_IN0 = 0 ;
+static const uint8_t P9N2_C_FIR_MASK_IN1 = 1 ;
+static const uint8_t P9N2_C_FIR_MASK_IN2 = 2 ;
+static const uint8_t P9N2_C_FIR_MASK_IN3 = 3 ;
+static const uint8_t P9N2_C_FIR_MASK_IN4 = 4 ;
+static const uint8_t P9N2_C_FIR_MASK_IN5 = 5 ;
+static const uint8_t P9N2_C_FIR_MASK_IN5_LEN = 21 ;
+static const uint8_t P9N2_C_FIR_MASK_IN26 = 26 ;
+
+static const uint8_t P9N2_EQ_FIR_MASK_REG_MASK = 0 ;
+static const uint8_t P9N2_EQ_FIR_MASK_REG_MASK_LEN = 31 ;
+
+static const uint8_t P9N2_EX_FIR_MASK_REG_MASK = 0 ;
+static const uint8_t P9N2_EX_FIR_MASK_REG_MASK_LEN = 31 ;
+
+static const uint8_t P9N2_EX_L2_FIR_MASK_REG_L2 = 0 ;
+static const uint8_t P9N2_EX_L2_FIR_MASK_REG_L2_LEN = 42 ;
+
+static const uint8_t P9N2_EX_L3_FIR_MASK_REG_L3_RDDSP_SEGR_LCO_ALL_MEM_UNAVAIL_ERR_MASK = 0 ;
+static const uint8_t P9N2_EX_L3_FIR_MASK_REG_L3_FIR_SPARE1_MASK = 1 ;
+static const uint8_t P9N2_EX_L3_FIR_MASK_REG_L3_FIR_SPARE2_MASK = 2 ;
+static const uint8_t P9N2_EX_L3_FIR_MASK_REG_L3_DRAM_POS_WORDLINE_FAIL_MASK = 3 ;
+static const uint8_t P9N2_EX_L3_FIR_MASK_REG_L3_CAC_RD_CE_DET_NOT_LINDEL_REQ_MASK = 4 ;
+static const uint8_t P9N2_EX_L3_FIR_MASK_REG_L3_CAC_RD_UE_DET_MASK = 5 ;
+static const uint8_t P9N2_EX_L3_FIR_MASK_REG_L3_CAC_RD_SUE_DET_MASK = 6 ;
+static const uint8_t P9N2_EX_L3_FIR_MASK_REG_L3_CAC_WR_DATA_CE_FROM_PB_MASK = 7 ;
+static const uint8_t P9N2_EX_L3_FIR_MASK_REG_L3_CAC_WR_DATA_UE_FROM_PB_MASK = 8 ;
+static const uint8_t P9N2_EX_L3_FIR_MASK_REG_L3_CAC_WR_DATA_SUE_FROM_PB_MASK = 9 ;
+static const uint8_t P9N2_EX_L3_FIR_MASK_REG_L3_CAC_WR_DATA_CE_FROM_L2_MASK = 10 ;
+static const uint8_t P9N2_EX_L3_FIR_MASK_REG_L3_CAC_WR_DATA_UE_FROM_L2_MASK = 11 ;
+static const uint8_t P9N2_EX_L3_FIR_MASK_REG_L3_CAC_WR_DATA_SUE_FROM_L2_OR_WIHPC_MASK = 12 ;
+static const uint8_t P9N2_EX_L3_FIR_MASK_REG_L3_DIR_RD_CE_DET_MASK = 13 ;
+static const uint8_t P9N2_EX_L3_FIR_MASK_REG_L3_DIR_RD_UE_DET_MASK = 14 ;
+static const uint8_t P9N2_EX_L3_FIR_MASK_REG_L3_DIR_RD_PHANTOM_ERROR_MASK = 15 ;
+static const uint8_t P9N2_EX_L3_FIR_MASK_REG_L3_PB_MAST_WR_ADDR_ERR_MASK = 16 ;
+static const uint8_t P9N2_EX_L3_FIR_MASK_REG_L3_PB_MAST_RD_ADDR_ERR_MASK = 17 ;
+static const uint8_t P9N2_EX_L3_FIR_MASK_REG_L3_ADDR_HANG_DETECTED_MASK = 18 ;
+static const uint8_t P9N2_EX_L3_FIR_MASK_REG_L3_LRU_INVAL_CNT_MASK = 19 ;
+static const uint8_t P9N2_EX_L3_FIR_MASK_REG_L3_PPE_RD_CE_DET_MASK = 20 ;
+static const uint8_t P9N2_EX_L3_FIR_MASK_REG_L3_PPE_RD_UE_DET_MASK = 21 ;
+static const uint8_t P9N2_EX_L3_FIR_MASK_REG_L3_PPE_RD_SUE_DET_MASK = 22 ;
+static const uint8_t P9N2_EX_L3_FIR_MASK_REG_L3_MACH_HANG_DETECTED_MASK = 23 ;
+static const uint8_t P9N2_EX_L3_FIR_MASK_REG_L3_HW_CONTROL_ERR_MASK = 24 ;
+static const uint8_t P9N2_EX_L3_FIR_MASK_REG_L3_SNP_CACHE_INHIBIT_ERR_MASK = 25 ;
+static const uint8_t P9N2_EX_L3_FIR_MASK_REG_L3_LINE_DEL_CE_DONE_MASK = 26 ;
+static const uint8_t P9N2_EX_L3_FIR_MASK_REG_L3_DRAM_ERROR_MASK = 27 ;
+static const uint8_t P9N2_EX_L3_FIR_MASK_REG_L3_LRU_ERROR_MASK = 28 ;
+static const uint8_t P9N2_EX_L3_FIR_MASK_REG_L3_ALL_MEMBERS_DELETED_ERROR_MASK = 29 ;
+static const uint8_t P9N2_EX_L3_FIR_MASK_REG_L3_REFRESH_TIMER_ERROR_MASK = 30 ;
+static const uint8_t P9N2_EX_L3_FIR_MASK_REG_L3_PB_MAST_WR_ACK_DEAD_MASK = 31 ;
+static const uint8_t P9N2_EX_L3_FIR_MASK_REG_L3_PB_MAST_RD_ACK_DEAD_MASK = 32 ;
+static const uint8_t P9N2_EX_L3_FIR_MASK_REG_SCOM_ERR_MASK1 = 33 ;
+static const uint8_t P9N2_EX_L3_FIR_MASK_REG_SCOM_ERR_MASK2 = 34 ;
+
+static const uint8_t P9N2_EQ_FIR_REG_CONTROL_ERR = 0 ;
+static const uint8_t P9N2_EQ_FIR_REG_TLBIE_CONTROL_ERR = 1 ;
+static const uint8_t P9N2_EQ_FIR_REG_TLBIE_SLBIEG_SW_ERR = 2 ;
+static const uint8_t P9N2_EQ_FIR_REG_ST_ADDR_ERR = 3 ;
+static const uint8_t P9N2_EQ_FIR_REG_LD_ADDR_ERR = 4 ;
+static const uint8_t P9N2_EQ_FIR_REG_ST_ACK_DEAD = 5 ;
+static const uint8_t P9N2_EQ_FIR_REG_LD_ACK_DEAD = 6 ;
+static const uint8_t P9N2_EQ_FIR_REG_MSG_ADDR_ERR = 7 ;
+static const uint8_t P9N2_EQ_FIR_REG_STQ_DATA_PARITY_ERR = 8 ;
+static const uint8_t P9N2_EQ_FIR_REG_STORE_TIMEOUT = 9 ;
+static const uint8_t P9N2_EQ_FIR_REG_TLBIE_MASTER_TIMEOUT = 10 ;
+static const uint8_t P9N2_EQ_FIR_REG_TLBIE_SNOOP_TIMEOUT = 11 ;
+static const uint8_t P9N2_EQ_FIR_REG_IMA_CRESP_ADDR_ERR = 12 ;
+static const uint8_t P9N2_EQ_FIR_REG_IMA_ACK_DEAD = 13 ;
+static const uint8_t P9N2_EQ_FIR_REG_PMISC_CRESP_ADDR_ERR = 14 ;
+static const uint8_t P9N2_EQ_FIR_REG_PPE_RD_CRESP_ADDR_ERR = 15 ;
+static const uint8_t P9N2_EQ_FIR_REG_PPE_WR_CRESP_ADDR_ERR = 16 ;
+static const uint8_t P9N2_EQ_FIR_REG_PPE_RD_ACK_DEAD = 17 ;
+static const uint8_t P9N2_EQ_FIR_REG_PPE_WR_ACK_DEAD = 18 ;
+static const uint8_t P9N2_EQ_FIR_REG_TGT_NODAL_DINC_ERR = 19 ;
+static const uint8_t P9N2_EQ_FIR_REG_DARN_EN_ERR = 20 ;
+static const uint8_t P9N2_EQ_FIR_REG_DARN_ADDR_ERR = 21 ;
+static const uint8_t P9N2_EQ_FIR_REG_PRATS_ACK_DEAD = 22 ;
+static const uint8_t P9N2_EQ_FIR_REG_SPARE = 23 ;
+static const uint8_t P9N2_EQ_FIR_REG_SPARE_LEN = 6 ;
+static const uint8_t P9N2_EQ_FIR_REG_SCOM_ERR1 = 29 ;
+static const uint8_t P9N2_EQ_FIR_REG_SCOM_ERR2 = 30 ;
+
+static const uint8_t P9N2_EX_FIR_REG_CONTROL_ERR = 0 ;
+static const uint8_t P9N2_EX_FIR_REG_TLBIE_CONTROL_ERR = 1 ;
+static const uint8_t P9N2_EX_FIR_REG_TLBIE_SLBIEG_SW_ERR = 2 ;
+static const uint8_t P9N2_EX_FIR_REG_ST_ADDR_ERR = 3 ;
+static const uint8_t P9N2_EX_FIR_REG_LD_ADDR_ERR = 4 ;
+static const uint8_t P9N2_EX_FIR_REG_ST_ACK_DEAD = 5 ;
+static const uint8_t P9N2_EX_FIR_REG_LD_ACK_DEAD = 6 ;
+static const uint8_t P9N2_EX_FIR_REG_MSG_ADDR_ERR = 7 ;
+static const uint8_t P9N2_EX_FIR_REG_STQ_DATA_PARITY_ERR = 8 ;
+static const uint8_t P9N2_EX_FIR_REG_STORE_TIMEOUT = 9 ;
+static const uint8_t P9N2_EX_FIR_REG_TLBIE_MASTER_TIMEOUT = 10 ;
+static const uint8_t P9N2_EX_FIR_REG_TLBIE_SNOOP_TIMEOUT = 11 ;
+static const uint8_t P9N2_EX_FIR_REG_IMA_CRESP_ADDR_ERR = 12 ;
+static const uint8_t P9N2_EX_FIR_REG_IMA_ACK_DEAD = 13 ;
+static const uint8_t P9N2_EX_FIR_REG_PMISC_CRESP_ADDR_ERR = 14 ;
+static const uint8_t P9N2_EX_FIR_REG_PPE_RD_CRESP_ADDR_ERR = 15 ;
+static const uint8_t P9N2_EX_FIR_REG_PPE_WR_CRESP_ADDR_ERR = 16 ;
+static const uint8_t P9N2_EX_FIR_REG_PPE_RD_ACK_DEAD = 17 ;
+static const uint8_t P9N2_EX_FIR_REG_PPE_WR_ACK_DEAD = 18 ;
+static const uint8_t P9N2_EX_FIR_REG_TGT_NODAL_DINC_ERR = 19 ;
+static const uint8_t P9N2_EX_FIR_REG_DARN_EN_ERR = 20 ;
+static const uint8_t P9N2_EX_FIR_REG_DARN_ADDR_ERR = 21 ;
+static const uint8_t P9N2_EX_FIR_REG_PRATS_ACK_DEAD = 22 ;
+static const uint8_t P9N2_EX_FIR_REG_SPARE = 23 ;
+static const uint8_t P9N2_EX_FIR_REG_SPARE_LEN = 6 ;
+static const uint8_t P9N2_EX_FIR_REG_SCOM_ERR1 = 29 ;
+static const uint8_t P9N2_EX_FIR_REG_SCOM_ERR2 = 30 ;
+
+static const uint8_t P9N2_EX_L2_FIR_REG_CACHE_RD_CE = 0 ;
+static const uint8_t P9N2_EX_L2_FIR_REG_CACHE_RD_UE = 1 ;
+static const uint8_t P9N2_EX_L2_FIR_REG_CACHE_RD_SUE = 2 ;
+static const uint8_t P9N2_EX_L2_FIR_REG_HW_DIR_INTIATED_LINE_DELETE_OCCURRED = 3 ;
+static const uint8_t P9N2_EX_L2_FIR_REG_CACHE_UE_SUE_DETECTED_ON_MODIFIED_LINE_BY_CO = 4 ;
+static const uint8_t P9N2_EX_L2_FIR_REG_CACHE_UE_SUE_DETECTED_ON_NON_MODIFIED_LINE_BY_CO = 5 ;
+static const uint8_t P9N2_EX_L2_FIR_REG_DIR_CE_DETECTED = 6 ;
+static const uint8_t P9N2_EX_L2_FIR_REG_DIR_UE_DETECTED = 7 ;
+static const uint8_t P9N2_EX_L2_FIR_REG_DIR_STUCK_BIT_CE = 8 ;
+static const uint8_t P9N2_EX_L2_FIR_REG_DIR_SBCE_REPAIR_FAILED = 9 ;
+static const uint8_t P9N2_EX_L2_FIR_REG_MULTIPLE_DIR_ERRORS_DETECTED = 10 ;
+static const uint8_t P9N2_EX_L2_FIR_REG_LRU_READ_ERROR_DETECTED = 11 ;
+static const uint8_t P9N2_EX_L2_FIR_REG_RC_POWERBUS_DATA_TIMEOUT = 12 ;
+static const uint8_t P9N2_EX_L2_FIR_REG_NCU_POWERBUS_DATA_TIMEOUT = 13 ;
+static const uint8_t P9N2_EX_L2_FIR_REG_HW_CONTROL_ERROR = 14 ;
+static const uint8_t P9N2_EX_L2_FIR_REG_LRU_ALL_MEMBERS_IN_CGC_ARE_LINE_DELETED = 15 ;
+static const uint8_t P9N2_EX_L2_FIR_REG_CACHE_INHIBITED_HIT_CACHEABLE_ERROR = 16 ;
+static const uint8_t P9N2_EX_L2_FIR_REG_RC_LOAD_RECEIVED_PB_CRESP_ADR_ERR = 17 ;
+static const uint8_t P9N2_EX_L2_FIR_REG_RC_STORE_RECEIVED_PB_CRESP_ADR_ERR = 18 ;
+static const uint8_t P9N2_EX_L2_FIR_REG_RC_POWBUS_DATA_CE_ERR_FROM_F2CHK = 19 ;
+static const uint8_t P9N2_EX_L2_FIR_REG_RC_POWBUS_DATA_UE_ERR_FROM_F2CHK = 20 ;
+static const uint8_t P9N2_EX_L2_FIR_REG_RC_POWBUS_DATA_SUE_ERR_FROM_F2CHK = 21 ;
+static const uint8_t P9N2_EX_L2_FIR_REG_TGT_NODAL_REQ_DINC_ERR = 22 ;
+static const uint8_t P9N2_EX_L2_FIR_REG_RC_LOAD_RECEIVED_PB_CRESP_ADR_ERR_FOR_HYP = 23 ;
+static const uint8_t P9N2_EX_L2_FIR_REG_RCDAT_RD_PARITY_ERR = 24 ;
+static const uint8_t P9N2_EX_L2_FIR_REG_CO_PSH_RECEIVED_PB_CRESP_ADR_ERR = 25 ;
+static const uint8_t P9N2_EX_L2_FIR_REG_LVDIR_PERR = 26 ;
+static const uint8_t P9N2_EX_L2_FIR_REG_RC_LOAD_RECEIVED_PB_ACK_DEAD_FROM_ALINKRECOV = 27 ;
+static const uint8_t P9N2_EX_L2_FIR_REG_DARN_DATA_TIMEOUT = 28 ;
+static const uint8_t P9N2_EX_L2_FIR_REG_RC_STORE_RECEIVED_PB_ACK_DEAD_FROM_ALINKRECOV = 29 ;
+static const uint8_t P9N2_EX_L2_FIR_REG_RC_XLATE_LOAD_RECEIVED_PB_ACK_DEAD_FROM_ALINKRECOV = 30 ;
+static const uint8_t P9N2_EX_L2_FIR_REG_RC_XLATE_STORE_RECEIVED_PB_ACK_DEAD_FROM_ALINKRECOV = 31 ;
+static const uint8_t P9N2_EX_L2_FIR_REG_PEC_PH3_TIMEOUT = 32 ;
+static const uint8_t P9N2_EX_L2_FIR_REG_SPARE2TO1 = 33 ;
+static const uint8_t P9N2_EX_L2_FIR_REG_SPARE2TO1_LEN = 3 ;
+static const uint8_t P9N2_EX_L2_FIR_REG_CACHE_RD_CE_AND_UE = 36 ;
+static const uint8_t P9N2_EX_L2_FIR_REG_SPARE1TO1 = 37 ;
+static const uint8_t P9N2_EX_L2_FIR_REG_SPARE1TO1_LEN = 3 ;
+static const uint8_t P9N2_EX_L2_FIR_REG_SCOM_ERR1 = 40 ;
+static const uint8_t P9N2_EX_L2_FIR_REG_SCOM_ERR2 = 41 ;
+
+static const uint8_t P9N2_EX_L3_FIR_REG_L3_RDDSP_SEGR_LCO_ALL_MEM_UNAVAIL_ERR = 0 ;
+static const uint8_t P9N2_EX_L3_FIR_REG_L3_SPARE1 = 1 ;
+static const uint8_t P9N2_EX_L3_FIR_REG_L3_SPARE2 = 2 ;
+static const uint8_t P9N2_EX_L3_FIR_REG_L3_DRAM_POS_WORDLINE_FAIL = 3 ;
+static const uint8_t P9N2_EX_L3_FIR_REG_L3_CAC_RD_CE_DET_NOT_LINDEL_REQ = 4 ;
+static const uint8_t P9N2_EX_L3_FIR_REG_L3_CAC_RD_UE_DET = 5 ;
+static const uint8_t P9N2_EX_L3_FIR_REG_L3_CAC_RD_SUE_DET = 6 ;
+static const uint8_t P9N2_EX_L3_FIR_REG_L3_CAC_WR_DATA_CE_FROM_PB = 7 ;
+static const uint8_t P9N2_EX_L3_FIR_REG_L3_CAC_WR_DATA_UE_FROM_PB = 8 ;
+static const uint8_t P9N2_EX_L3_FIR_REG_L3_CAC_WR_DATA_SUE_FROM_PB = 9 ;
+static const uint8_t P9N2_EX_L3_FIR_REG_L3_CAC_WR_DATA_CE_FROM_L2 = 10 ;
+static const uint8_t P9N2_EX_L3_FIR_REG_L3_CAC_WR_DATA_UE_FROM_L2 = 11 ;
+static const uint8_t P9N2_EX_L3_FIR_REG_L3_CAC_WR_DATA_SUE_FROM_L2_OR_WIHPC = 12 ;
+static const uint8_t P9N2_EX_L3_FIR_REG_L3_DIR_RD_CE_DET = 13 ;
+static const uint8_t P9N2_EX_L3_FIR_REG_L3_DIR_RD_UE_DET = 14 ;
+static const uint8_t P9N2_EX_L3_FIR_REG_L3_DIR_RD_PHANTOM_ERROR = 15 ;
+static const uint8_t P9N2_EX_L3_FIR_REG_L3_PB_MAST_WR_ADDR_ERR = 16 ;
+static const uint8_t P9N2_EX_L3_FIR_REG_L3_PB_MAST_RD_ADDR_ERR = 17 ;
+static const uint8_t P9N2_EX_L3_FIR_REG_L3_ADDR_HANG_DETECTED = 18 ;
+static const uint8_t P9N2_EX_L3_FIR_REG_L3_LRU_INVAL_CNT = 19 ;
+static const uint8_t P9N2_EX_L3_FIR_REG_L3_PPE_RD_CE_DET = 20 ;
+static const uint8_t P9N2_EX_L3_FIR_REG_L3_PPE_RD_UE_DET = 21 ;
+static const uint8_t P9N2_EX_L3_FIR_REG_L3_PPE_RD_SUE_DET = 22 ;
+static const uint8_t P9N2_EX_L3_FIR_REG_L3_MACH_HANG_DETECTED = 23 ;
+static const uint8_t P9N2_EX_L3_FIR_REG_L3_HW_CONTROL_ERR = 24 ;
+static const uint8_t P9N2_EX_L3_FIR_REG_L3_SNP_CACHE_INHIBIT_ERR = 25 ;
+static const uint8_t P9N2_EX_L3_FIR_REG_L3_LINE_DEL_CE_DONE = 26 ;
+static const uint8_t P9N2_EX_L3_FIR_REG_L3_DRAM_ERROR = 27 ;
+static const uint8_t P9N2_EX_L3_FIR_REG_L3_LRU_ERROR = 28 ;
+static const uint8_t P9N2_EX_L3_FIR_REG_L3_ALL_MEMBERS_DELETED_ERROR = 29 ;
+static const uint8_t P9N2_EX_L3_FIR_REG_L3_REFRESH_TIMER_ERROR = 30 ;
+static const uint8_t P9N2_EX_L3_FIR_REG_L3_PB_MAST_WR_ACK_DEAD = 31 ;
+static const uint8_t P9N2_EX_L3_FIR_REG_L3_PB_MAST_RD_ACK_DEAD = 32 ;
+static const uint8_t P9N2_EX_L3_FIR_REG_SCOM_ERR1 = 33 ;
+static const uint8_t P9N2_EX_L3_FIR_REG_SCOM_ERR2 = 34 ;
+
+static const uint8_t P9N2_EQ_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN0 = 0 ;
+static const uint8_t P9N2_EQ_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN1 = 1 ;
+static const uint8_t P9N2_EQ_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN2 = 2 ;
+static const uint8_t P9N2_EQ_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN3 = 3 ;
+static const uint8_t P9N2_EQ_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN4 = 4 ;
+static const uint8_t P9N2_EQ_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN5 = 5 ;
+static const uint8_t P9N2_EQ_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN6 = 6 ;
+static const uint8_t P9N2_EQ_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN7 = 7 ;
+static const uint8_t P9N2_EQ_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN8 = 8 ;
+static const uint8_t P9N2_EQ_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN9 = 9 ;
+static const uint8_t P9N2_EQ_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN10 = 10 ;
+static const uint8_t P9N2_EQ_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN11 = 11 ;
+
+static const uint8_t P9N2_EX_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN0 = 0 ;
+static const uint8_t P9N2_EX_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN1 = 1 ;
+static const uint8_t P9N2_EX_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN2 = 2 ;
+static const uint8_t P9N2_EX_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN3 = 3 ;
+static const uint8_t P9N2_EX_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN4 = 4 ;
+static const uint8_t P9N2_EX_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN5 = 5 ;
+static const uint8_t P9N2_EX_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN6 = 6 ;
+static const uint8_t P9N2_EX_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN7 = 7 ;
+static const uint8_t P9N2_EX_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN8 = 8 ;
+static const uint8_t P9N2_EX_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN9 = 9 ;
+static const uint8_t P9N2_EX_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN10 = 10 ;
+static const uint8_t P9N2_EX_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN11 = 11 ;
+
+static const uint8_t P9N2_C_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN0 = 0 ;
+static const uint8_t P9N2_C_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN1 = 1 ;
+static const uint8_t P9N2_C_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN2 = 2 ;
+static const uint8_t P9N2_C_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN3 = 3 ;
+static const uint8_t P9N2_C_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN4 = 4 ;
+static const uint8_t P9N2_C_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN5 = 5 ;
+static const uint8_t P9N2_C_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN6 = 6 ;
+static const uint8_t P9N2_C_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN7 = 7 ;
+static const uint8_t P9N2_C_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN8 = 8 ;
+static const uint8_t P9N2_C_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN9 = 9 ;
+static const uint8_t P9N2_C_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN10 = 10 ;
+static const uint8_t P9N2_C_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN11 = 11 ;
+
+static const uint8_t P9N2_EQ_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN0 = 0 ;
+static const uint8_t P9N2_EQ_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN1 = 1 ;
+static const uint8_t P9N2_EQ_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN2 = 2 ;
+static const uint8_t P9N2_EQ_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN3 = 3 ;
+static const uint8_t P9N2_EQ_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN4 = 4 ;
+static const uint8_t P9N2_EQ_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN5 = 5 ;
+static const uint8_t P9N2_EQ_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN6 = 6 ;
+static const uint8_t P9N2_EQ_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN7 = 7 ;
+static const uint8_t P9N2_EQ_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN8 = 8 ;
+static const uint8_t P9N2_EQ_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN9 = 9 ;
+static const uint8_t P9N2_EQ_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN10 = 10 ;
+static const uint8_t P9N2_EQ_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN11 = 11 ;
+
+static const uint8_t P9N2_EX_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN0 = 0 ;
+static const uint8_t P9N2_EX_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN1 = 1 ;
+static const uint8_t P9N2_EX_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN2 = 2 ;
+static const uint8_t P9N2_EX_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN3 = 3 ;
+static const uint8_t P9N2_EX_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN4 = 4 ;
+static const uint8_t P9N2_EX_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN5 = 5 ;
+static const uint8_t P9N2_EX_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN6 = 6 ;
+static const uint8_t P9N2_EX_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN7 = 7 ;
+static const uint8_t P9N2_EX_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN8 = 8 ;
+static const uint8_t P9N2_EX_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN9 = 9 ;
+static const uint8_t P9N2_EX_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN10 = 10 ;
+static const uint8_t P9N2_EX_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN11 = 11 ;
+
+static const uint8_t P9N2_C_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN0 = 0 ;
+static const uint8_t P9N2_C_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN1 = 1 ;
+static const uint8_t P9N2_C_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN2 = 2 ;
+static const uint8_t P9N2_C_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN3 = 3 ;
+static const uint8_t P9N2_C_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN4 = 4 ;
+static const uint8_t P9N2_C_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN5 = 5 ;
+static const uint8_t P9N2_C_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN6 = 6 ;
+static const uint8_t P9N2_C_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN7 = 7 ;
+static const uint8_t P9N2_C_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN8 = 8 ;
+static const uint8_t P9N2_C_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN9 = 9 ;
+static const uint8_t P9N2_C_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN10 = 10 ;
+static const uint8_t P9N2_C_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN11 = 11 ;
+
+static const uint8_t P9N2_EQ_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN0 = 0 ;
+static const uint8_t P9N2_EQ_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN1 = 1 ;
+static const uint8_t P9N2_EQ_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN2 = 2 ;
+static const uint8_t P9N2_EQ_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN3 = 3 ;
+static const uint8_t P9N2_EQ_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN4 = 4 ;
+static const uint8_t P9N2_EQ_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN5 = 5 ;
+static const uint8_t P9N2_EQ_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN6 = 6 ;
+static const uint8_t P9N2_EQ_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN7 = 7 ;
+static const uint8_t P9N2_EQ_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN8 = 8 ;
+static const uint8_t P9N2_EQ_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN9 = 9 ;
+static const uint8_t P9N2_EQ_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN10 = 10 ;
+static const uint8_t P9N2_EQ_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN11 = 11 ;
+
+static const uint8_t P9N2_EX_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN0 = 0 ;
+static const uint8_t P9N2_EX_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN1 = 1 ;
+static const uint8_t P9N2_EX_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN2 = 2 ;
+static const uint8_t P9N2_EX_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN3 = 3 ;
+static const uint8_t P9N2_EX_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN4 = 4 ;
+static const uint8_t P9N2_EX_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN5 = 5 ;
+static const uint8_t P9N2_EX_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN6 = 6 ;
+static const uint8_t P9N2_EX_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN7 = 7 ;
+static const uint8_t P9N2_EX_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN8 = 8 ;
+static const uint8_t P9N2_EX_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN9 = 9 ;
+static const uint8_t P9N2_EX_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN10 = 10 ;
+static const uint8_t P9N2_EX_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN11 = 11 ;
+
+static const uint8_t P9N2_C_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN0 = 0 ;
+static const uint8_t P9N2_C_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN1 = 1 ;
+static const uint8_t P9N2_C_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN2 = 2 ;
+static const uint8_t P9N2_C_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN3 = 3 ;
+static const uint8_t P9N2_C_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN4 = 4 ;
+static const uint8_t P9N2_C_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN5 = 5 ;
+static const uint8_t P9N2_C_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN6 = 6 ;
+static const uint8_t P9N2_C_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN7 = 7 ;
+static const uint8_t P9N2_C_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN8 = 8 ;
+static const uint8_t P9N2_C_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN9 = 9 ;
+static const uint8_t P9N2_C_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN10 = 10 ;
+static const uint8_t P9N2_C_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN11 = 11 ;
+
+static const uint8_t P9N2_EQ_GXSTOP_TRIG_REG_GXSTP_IN0 = 0 ;
+static const uint8_t P9N2_EQ_GXSTOP_TRIG_REG_GXSTP_IN1 = 1 ;
+static const uint8_t P9N2_EQ_GXSTOP_TRIG_REG_GXSTP_IN2 = 2 ;
+static const uint8_t P9N2_EQ_GXSTOP_TRIG_REG_GXSTP_IN3 = 3 ;
+static const uint8_t P9N2_EQ_GXSTOP_TRIG_REG_GXSTP_IN4 = 4 ;
+static const uint8_t P9N2_EQ_GXSTOP_TRIG_REG_GXSTP_IN5 = 5 ;
+static const uint8_t P9N2_EQ_GXSTOP_TRIG_REG_GXSTP_IN6 = 6 ;
+static const uint8_t P9N2_EQ_GXSTOP_TRIG_REG_GXSTP_IN7 = 7 ;
+static const uint8_t P9N2_EQ_GXSTOP_TRIG_REG_GXSTP_IN8 = 8 ;
+static const uint8_t P9N2_EQ_GXSTOP_TRIG_REG_GXSTP_IN9 = 9 ;
+static const uint8_t P9N2_EQ_GXSTOP_TRIG_REG_GXSTP_IN10 = 10 ;
+static const uint8_t P9N2_EQ_GXSTOP_TRIG_REG_GXSTP_IN11 = 11 ;
+
+static const uint8_t P9N2_EX_GXSTOP_TRIG_REG_GXSTP_IN0 = 0 ;
+static const uint8_t P9N2_EX_GXSTOP_TRIG_REG_GXSTP_IN1 = 1 ;
+static const uint8_t P9N2_EX_GXSTOP_TRIG_REG_GXSTP_IN2 = 2 ;
+static const uint8_t P9N2_EX_GXSTOP_TRIG_REG_GXSTP_IN3 = 3 ;
+static const uint8_t P9N2_EX_GXSTOP_TRIG_REG_GXSTP_IN4 = 4 ;
+static const uint8_t P9N2_EX_GXSTOP_TRIG_REG_GXSTP_IN5 = 5 ;
+static const uint8_t P9N2_EX_GXSTOP_TRIG_REG_GXSTP_IN6 = 6 ;
+static const uint8_t P9N2_EX_GXSTOP_TRIG_REG_GXSTP_IN7 = 7 ;
+static const uint8_t P9N2_EX_GXSTOP_TRIG_REG_GXSTP_IN8 = 8 ;
+static const uint8_t P9N2_EX_GXSTOP_TRIG_REG_GXSTP_IN9 = 9 ;
+static const uint8_t P9N2_EX_GXSTOP_TRIG_REG_GXSTP_IN10 = 10 ;
+static const uint8_t P9N2_EX_GXSTOP_TRIG_REG_GXSTP_IN11 = 11 ;
+
+static const uint8_t P9N2_C_GXSTOP_TRIG_REG_GXSTP_IN0 = 0 ;
+static const uint8_t P9N2_C_GXSTOP_TRIG_REG_GXSTP_IN1 = 1 ;
+static const uint8_t P9N2_C_GXSTOP_TRIG_REG_GXSTP_IN2 = 2 ;
+static const uint8_t P9N2_C_GXSTOP_TRIG_REG_GXSTP_IN3 = 3 ;
+static const uint8_t P9N2_C_GXSTOP_TRIG_REG_GXSTP_IN4 = 4 ;
+static const uint8_t P9N2_C_GXSTOP_TRIG_REG_GXSTP_IN5 = 5 ;
+static const uint8_t P9N2_C_GXSTOP_TRIG_REG_GXSTP_IN6 = 6 ;
+static const uint8_t P9N2_C_GXSTOP_TRIG_REG_GXSTP_IN7 = 7 ;
+static const uint8_t P9N2_C_GXSTOP_TRIG_REG_GXSTP_IN8 = 8 ;
+static const uint8_t P9N2_C_GXSTOP_TRIG_REG_GXSTP_IN9 = 9 ;
+static const uint8_t P9N2_C_GXSTOP_TRIG_REG_GXSTP_IN10 = 10 ;
+static const uint8_t P9N2_C_GXSTOP_TRIG_REG_GXSTP_IN11 = 11 ;
+
+static const uint8_t P9N2_EX_L2_HANG_CONTROL_CORE_LIMIT = 0 ;
+static const uint8_t P9N2_EX_L2_HANG_CONTROL_CORE_LIMIT_LEN = 8 ;
+static const uint8_t P9N2_EX_L2_HANG_CONTROL_NEST_LIMIT = 8 ;
+static const uint8_t P9N2_EX_L2_HANG_CONTROL_NEST_LIMIT_LEN = 8 ;
+static const uint8_t P9N2_EX_L2_HANG_CONTROL_RETURN_GOOD_ON_COMP = 16 ;
+static const uint8_t P9N2_EX_L2_HANG_CONTROL_COMP_CNT_LIMIT = 17 ;
+static const uint8_t P9N2_EX_L2_HANG_CONTROL_COMP_CNT_LIMIT_LEN = 8 ;
+static const uint8_t P9N2_EX_L2_HANG_CONTROL_REC_LIMIT = 25 ;
+static const uint8_t P9N2_EX_L2_HANG_CONTROL_REC_LIMIT_LEN = 3 ;
+static const uint8_t P9N2_EX_L2_HANG_CONTROL_USE_REC_LIMIT = 28 ;
+static const uint8_t P9N2_EX_L2_HANG_CONTROL_ACTIVE_MASK = 29 ;
+static const uint8_t P9N2_EX_L2_HANG_CONTROL_ACTIVE_MASK_LEN = 5 ;
+static const uint8_t P9N2_EX_L2_HANG_CONTROL_TLBIE_STALL_LIMIT = 34 ;
+static const uint8_t P9N2_EX_L2_HANG_CONTROL_TLBIE_STALL_LIMIT_LEN = 8 ;
+
+static const uint8_t P9N2_C_HANG_CONTROL_CORE_LIMIT = 0 ;
+static const uint8_t P9N2_C_HANG_CONTROL_CORE_LIMIT_LEN = 8 ;
+static const uint8_t P9N2_C_HANG_CONTROL_NEST_LIMIT = 8 ;
+static const uint8_t P9N2_C_HANG_CONTROL_NEST_LIMIT_LEN = 8 ;
+static const uint8_t P9N2_C_HANG_CONTROL_RETURN_GOOD_ON_COMP = 16 ;
+static const uint8_t P9N2_C_HANG_CONTROL_COMP_CNT_LIMIT = 17 ;
+static const uint8_t P9N2_C_HANG_CONTROL_COMP_CNT_LIMIT_LEN = 8 ;
+static const uint8_t P9N2_C_HANG_CONTROL_REC_LIMIT = 25 ;
+static const uint8_t P9N2_C_HANG_CONTROL_REC_LIMIT_LEN = 3 ;
+static const uint8_t P9N2_C_HANG_CONTROL_USE_REC_LIMIT = 28 ;
+static const uint8_t P9N2_C_HANG_CONTROL_ACTIVE_MASK = 29 ;
+static const uint8_t P9N2_C_HANG_CONTROL_ACTIVE_MASK_LEN = 5 ;
+static const uint8_t P9N2_C_HANG_CONTROL_TLBIE_STALL_LIMIT = 34 ;
+static const uint8_t P9N2_C_HANG_CONTROL_TLBIE_STALL_LIMIT_LEN = 8 ;
+
+static const uint8_t P9N2_EQ_HANG_PULSE_0_REG_0 = 0 ;
+static const uint8_t P9N2_EQ_HANG_PULSE_0_REG_0_LEN = 6 ;
+static const uint8_t P9N2_EQ_HANG_PULSE_0_REG_SUPPRESS = 6 ;
+
+static const uint8_t P9N2_EX_HANG_PULSE_0_REG_0 = 0 ;
+static const uint8_t P9N2_EX_HANG_PULSE_0_REG_0_LEN = 6 ;
+static const uint8_t P9N2_EX_HANG_PULSE_0_REG_SUPPRESS = 6 ;
+
+static const uint8_t P9N2_C_HANG_PULSE_0_REG_0 = 0 ;
+static const uint8_t P9N2_C_HANG_PULSE_0_REG_0_LEN = 6 ;
+static const uint8_t P9N2_C_HANG_PULSE_0_REG_SUPPRESS = 6 ;
+
+static const uint8_t P9N2_EQ_HANG_PULSE_1_REG_1 = 0 ;
+static const uint8_t P9N2_EQ_HANG_PULSE_1_REG_1_LEN = 6 ;
+static const uint8_t P9N2_EQ_HANG_PULSE_1_REG_SUPPRESS = 6 ;
+
+static const uint8_t P9N2_EX_HANG_PULSE_1_REG_1 = 0 ;
+static const uint8_t P9N2_EX_HANG_PULSE_1_REG_1_LEN = 6 ;
+static const uint8_t P9N2_EX_HANG_PULSE_1_REG_SUPPRESS = 6 ;
+
+static const uint8_t P9N2_C_HANG_PULSE_1_REG_1 = 0 ;
+static const uint8_t P9N2_C_HANG_PULSE_1_REG_1_LEN = 6 ;
+static const uint8_t P9N2_C_HANG_PULSE_1_REG_SUPPRESS = 6 ;
+
+static const uint8_t P9N2_EQ_HANG_PULSE_2_REG_2 = 0 ;
+static const uint8_t P9N2_EQ_HANG_PULSE_2_REG_2_LEN = 6 ;
+static const uint8_t P9N2_EQ_HANG_PULSE_2_REG_SUPPRESS = 6 ;
+
+static const uint8_t P9N2_EX_HANG_PULSE_2_REG_2 = 0 ;
+static const uint8_t P9N2_EX_HANG_PULSE_2_REG_2_LEN = 6 ;
+static const uint8_t P9N2_EX_HANG_PULSE_2_REG_SUPPRESS = 6 ;
+
+static const uint8_t P9N2_C_HANG_PULSE_2_REG_2 = 0 ;
+static const uint8_t P9N2_C_HANG_PULSE_2_REG_2_LEN = 6 ;
+static const uint8_t P9N2_C_HANG_PULSE_2_REG_SUPPRESS = 6 ;
+
+static const uint8_t P9N2_EQ_HANG_PULSE_3_REG_3 = 0 ;
+static const uint8_t P9N2_EQ_HANG_PULSE_3_REG_3_LEN = 6 ;
+static const uint8_t P9N2_EQ_HANG_PULSE_3_REG_SUPPRESS = 6 ;
+
+static const uint8_t P9N2_EX_HANG_PULSE_3_REG_3 = 0 ;
+static const uint8_t P9N2_EX_HANG_PULSE_3_REG_3_LEN = 6 ;
+static const uint8_t P9N2_EX_HANG_PULSE_3_REG_SUPPRESS = 6 ;
+
+static const uint8_t P9N2_C_HANG_PULSE_3_REG_3 = 0 ;
+static const uint8_t P9N2_C_HANG_PULSE_3_REG_3_LEN = 6 ;
+static const uint8_t P9N2_C_HANG_PULSE_3_REG_SUPPRESS = 6 ;
+
+static const uint8_t P9N2_EQ_HANG_PULSE_4_REG_4 = 0 ;
+static const uint8_t P9N2_EQ_HANG_PULSE_4_REG_4_LEN = 6 ;
+static const uint8_t P9N2_EQ_HANG_PULSE_4_REG_SUPPRESS = 6 ;
+
+static const uint8_t P9N2_EX_HANG_PULSE_4_REG_4 = 0 ;
+static const uint8_t P9N2_EX_HANG_PULSE_4_REG_4_LEN = 6 ;
+static const uint8_t P9N2_EX_HANG_PULSE_4_REG_SUPPRESS = 6 ;
+
+static const uint8_t P9N2_C_HANG_PULSE_4_REG_4 = 0 ;
+static const uint8_t P9N2_C_HANG_PULSE_4_REG_4_LEN = 6 ;
+static const uint8_t P9N2_C_HANG_PULSE_4_REG_SUPPRESS = 6 ;
+
+static const uint8_t P9N2_EQ_HANG_PULSE_5_REG_5 = 0 ;
+static const uint8_t P9N2_EQ_HANG_PULSE_5_REG_5_LEN = 6 ;
+static const uint8_t P9N2_EQ_HANG_PULSE_5_REG_SUPPRESS = 6 ;
+
+static const uint8_t P9N2_EX_HANG_PULSE_5_REG_5 = 0 ;
+static const uint8_t P9N2_EX_HANG_PULSE_5_REG_5_LEN = 6 ;
+static const uint8_t P9N2_EX_HANG_PULSE_5_REG_SUPPRESS = 6 ;
+
+static const uint8_t P9N2_C_HANG_PULSE_5_REG_5 = 0 ;
+static const uint8_t P9N2_C_HANG_PULSE_5_REG_5_LEN = 6 ;
+static const uint8_t P9N2_C_HANG_PULSE_5_REG_SUPPRESS = 6 ;
+
+static const uint8_t P9N2_EQ_HANG_PULSE_6_REG_6 = 0 ;
+static const uint8_t P9N2_EQ_HANG_PULSE_6_REG_6_LEN = 6 ;
+static const uint8_t P9N2_EQ_HANG_PULSE_6_REG_SUPPRESS = 6 ;
+
+static const uint8_t P9N2_EX_HANG_PULSE_6_REG_6 = 0 ;
+static const uint8_t P9N2_EX_HANG_PULSE_6_REG_6_LEN = 6 ;
+static const uint8_t P9N2_EX_HANG_PULSE_6_REG_SUPPRESS = 6 ;
+
+static const uint8_t P9N2_C_HANG_PULSE_6_REG_6 = 0 ;
+static const uint8_t P9N2_C_HANG_PULSE_6_REG_6_LEN = 6 ;
+static const uint8_t P9N2_C_HANG_PULSE_6_REG_SUPPRESS = 6 ;
+
+static const uint8_t P9N2_EQ_HEARTBEAT_REG_DEAD = 0 ;
+
+static const uint8_t P9N2_EX_HEARTBEAT_REG_DEAD = 0 ;
+
+static const uint8_t P9N2_C_HEARTBEAT_REG_DEAD = 0 ;
+
+static const uint8_t P9N2_EX_L2_HID_ONE_PPC = 0 ;
+static const uint8_t P9N2_EX_L2_HID_EN_INSTRUC_TRACE = 1 ;
+static const uint8_t P9N2_EX_L2_HID_FLUSH_IC = 2 ;
+static const uint8_t P9N2_EX_L2_HID_EN_ATTN = 3 ;
+static const uint8_t P9N2_EX_L2_HID_HILE = 4 ;
+static const uint8_t P9N2_EX_L2_HID_DIS_RECOVERY = 5 ;
+static const uint8_t P9N2_EX_L2_HID_MEGAMOUTH = 6 ;
+static const uint8_t P9N2_EX_L2_HID_PREFETCH_RESET = 7 ;
+static const uint8_t P9N2_EX_L2_HID_RADIX_MODE = 8 ;
+static const uint8_t P9N2_EX_L2_HID_DCACHE_PARTITIONED = 9 ;
+static const uint8_t P9N2_EX_L2_HID_ICACHE_PARTITIONED = 10 ;
+static const uint8_t P9N2_EX_L2_HID_SPARE_11 = 11 ;
+static const uint8_t P9N2_EX_L2_HID_SPARE_12 = 12 ;
+
+static const uint8_t P9N2_C_HID_ONE_PPC = 0 ;
+static const uint8_t P9N2_C_HID_EN_INSTRUC_TRACE = 1 ;
+static const uint8_t P9N2_C_HID_FLUSH_IC = 2 ;
+static const uint8_t P9N2_C_HID_EN_ATTN = 3 ;
+static const uint8_t P9N2_C_HID_HILE = 4 ;
+static const uint8_t P9N2_C_HID_DIS_RECOVERY = 5 ;
+static const uint8_t P9N2_C_HID_MEGAMOUTH = 6 ;
+static const uint8_t P9N2_C_HID_PREFETCH_RESET = 7 ;
+static const uint8_t P9N2_C_HID_RADIX_MODE = 8 ;
+static const uint8_t P9N2_C_HID_DCACHE_PARTITIONED = 9 ;
+static const uint8_t P9N2_C_HID_ICACHE_PARTITIONED = 10 ;
+static const uint8_t P9N2_C_HID_SPARE_11 = 11 ;
+static const uint8_t P9N2_C_HID_SPARE_12 = 12 ;
+
+static const uint8_t P9N2_EX_L2_HMEER_ENABLE = 0 ;
+static const uint8_t P9N2_EX_L2_HMEER_ENABLE_LEN = 24 ;
+
+static const uint8_t P9N2_C_HMEER_ENABLE = 0 ;
+static const uint8_t P9N2_C_HMEER_ENABLE_LEN = 24 ;
+
+static const uint8_t P9N2_EQ_HOSTATTN_IN0 = 0 ;
+static const uint8_t P9N2_EQ_HOSTATTN_IN1 = 1 ;
+static const uint8_t P9N2_EQ_HOSTATTN_IN2 = 2 ;
+static const uint8_t P9N2_EQ_HOSTATTN_IN3 = 3 ;
+static const uint8_t P9N2_EQ_HOSTATTN_IN4 = 4 ;
+static const uint8_t P9N2_EQ_HOSTATTN_IN5 = 5 ;
+static const uint8_t P9N2_EQ_HOSTATTN_IN6 = 6 ;
+static const uint8_t P9N2_EQ_HOSTATTN_IN7 = 7 ;
+static const uint8_t P9N2_EQ_HOSTATTN_IN8 = 8 ;
+static const uint8_t P9N2_EQ_HOSTATTN_IN9 = 9 ;
+static const uint8_t P9N2_EQ_HOSTATTN_IN10 = 10 ;
+static const uint8_t P9N2_EQ_HOSTATTN_IN11 = 11 ;
+static const uint8_t P9N2_EQ_HOSTATTN_IN12 = 12 ;
+static const uint8_t P9N2_EQ_HOSTATTN_IN13 = 13 ;
+static const uint8_t P9N2_EQ_HOSTATTN_IN14 = 14 ;
+static const uint8_t P9N2_EQ_HOSTATTN_IN15 = 15 ;
+static const uint8_t P9N2_EQ_HOSTATTN_IN16 = 16 ;
+static const uint8_t P9N2_EQ_HOSTATTN_IN17 = 17 ;
+static const uint8_t P9N2_EQ_HOSTATTN_IN18 = 18 ;
+static const uint8_t P9N2_EQ_HOSTATTN_IN19 = 19 ;
+static const uint8_t P9N2_EQ_HOSTATTN_IN20 = 20 ;
+static const uint8_t P9N2_EQ_HOSTATTN_IN21 = 21 ;
+static const uint8_t P9N2_EQ_HOSTATTN_IN22 = 22 ;
+
+static const uint8_t P9N2_EX_HOSTATTN_IN0 = 0 ;
+static const uint8_t P9N2_EX_HOSTATTN_IN1 = 1 ;
+static const uint8_t P9N2_EX_HOSTATTN_IN2 = 2 ;
+static const uint8_t P9N2_EX_HOSTATTN_IN3 = 3 ;
+static const uint8_t P9N2_EX_HOSTATTN_IN4 = 4 ;
+static const uint8_t P9N2_EX_HOSTATTN_IN5 = 5 ;
+static const uint8_t P9N2_EX_HOSTATTN_IN6 = 6 ;
+static const uint8_t P9N2_EX_HOSTATTN_IN7 = 7 ;
+static const uint8_t P9N2_EX_HOSTATTN_IN8 = 8 ;
+static const uint8_t P9N2_EX_HOSTATTN_IN9 = 9 ;
+static const uint8_t P9N2_EX_HOSTATTN_IN10 = 10 ;
+static const uint8_t P9N2_EX_HOSTATTN_IN11 = 11 ;
+static const uint8_t P9N2_EX_HOSTATTN_IN12 = 12 ;
+static const uint8_t P9N2_EX_HOSTATTN_IN13 = 13 ;
+static const uint8_t P9N2_EX_HOSTATTN_IN14 = 14 ;
+static const uint8_t P9N2_EX_HOSTATTN_IN15 = 15 ;
+static const uint8_t P9N2_EX_HOSTATTN_IN16 = 16 ;
+static const uint8_t P9N2_EX_HOSTATTN_IN17 = 17 ;
+static const uint8_t P9N2_EX_HOSTATTN_IN18 = 18 ;
+static const uint8_t P9N2_EX_HOSTATTN_IN19 = 19 ;
+static const uint8_t P9N2_EX_HOSTATTN_IN20 = 20 ;
+static const uint8_t P9N2_EX_HOSTATTN_IN21 = 21 ;
+static const uint8_t P9N2_EX_HOSTATTN_IN22 = 22 ;
+
+static const uint8_t P9N2_C_HOSTATTN_IN0 = 0 ;
+static const uint8_t P9N2_C_HOSTATTN_IN1 = 1 ;
+static const uint8_t P9N2_C_HOSTATTN_IN2 = 2 ;
+static const uint8_t P9N2_C_HOSTATTN_IN3 = 3 ;
+static const uint8_t P9N2_C_HOSTATTN_IN4 = 4 ;
+static const uint8_t P9N2_C_HOSTATTN_IN5 = 5 ;
+static const uint8_t P9N2_C_HOSTATTN_IN6 = 6 ;
+static const uint8_t P9N2_C_HOSTATTN_IN7 = 7 ;
+static const uint8_t P9N2_C_HOSTATTN_IN8 = 8 ;
+static const uint8_t P9N2_C_HOSTATTN_IN9 = 9 ;
+static const uint8_t P9N2_C_HOSTATTN_IN10 = 10 ;
+static const uint8_t P9N2_C_HOSTATTN_IN11 = 11 ;
+static const uint8_t P9N2_C_HOSTATTN_IN12 = 12 ;
+static const uint8_t P9N2_C_HOSTATTN_IN13 = 13 ;
+static const uint8_t P9N2_C_HOSTATTN_IN14 = 14 ;
+static const uint8_t P9N2_C_HOSTATTN_IN15 = 15 ;
+static const uint8_t P9N2_C_HOSTATTN_IN16 = 16 ;
+static const uint8_t P9N2_C_HOSTATTN_IN17 = 17 ;
+static const uint8_t P9N2_C_HOSTATTN_IN18 = 18 ;
+static const uint8_t P9N2_C_HOSTATTN_IN19 = 19 ;
+static const uint8_t P9N2_C_HOSTATTN_IN20 = 20 ;
+static const uint8_t P9N2_C_HOSTATTN_IN21 = 21 ;
+static const uint8_t P9N2_C_HOSTATTN_IN22 = 22 ;
+
+static const uint8_t P9N2_EQ_HOSTATTN_MASK_IN = 0 ;
+static const uint8_t P9N2_EQ_HOSTATTN_MASK_IN_LEN = 22 ;
+
+static const uint8_t P9N2_EX_HOSTATTN_MASK_IN = 0 ;
+static const uint8_t P9N2_EX_HOSTATTN_MASK_IN_LEN = 22 ;
+
+static const uint8_t P9N2_C_HOSTATTN_MASK_IN = 0 ;
+static const uint8_t P9N2_C_HOSTATTN_MASK_IN_LEN = 22 ;
+
+static const uint8_t P9N2_EQ_HTM_CTRL_HTMSC_TRIG = 0 ;
+static const uint8_t P9N2_EQ_HTM_CTRL_HTMSC_TRIG_LEN = 2 ;
+static const uint8_t P9N2_EQ_HTM_CTRL_HTMSC_MTSPR_TRIG = 2 ;
+static const uint8_t P9N2_EQ_HTM_CTRL_HTMSC_MTSPR_MARK = 3 ;
+static const uint8_t P9N2_EQ_HTM_CTRL_HTMSC_MARK = 4 ;
+static const uint8_t P9N2_EQ_HTM_CTRL_HTMSC_MARK_LEN = 2 ;
+static const uint8_t P9N2_EQ_HTM_CTRL_HTMSC_DBG0_STOP = 6 ;
+static const uint8_t P9N2_EQ_HTM_CTRL_HTMSC_DBG1_STOP = 7 ;
+static const uint8_t P9N2_EQ_HTM_CTRL_HTMSC_RUN_STOP = 8 ;
+static const uint8_t P9N2_EQ_HTM_CTRL_HTMSC_CHIP0_STOP = 9 ;
+static const uint8_t P9N2_EQ_HTM_CTRL_HTMSC_CHIP1_STOP = 10 ;
+static const uint8_t P9N2_EQ_HTM_CTRL_HTMSC_SPARE1112 = 11 ;
+static const uint8_t P9N2_EQ_HTM_CTRL_HTMSC_SPARE1112_LEN = 2 ;
+static const uint8_t P9N2_EQ_HTM_CTRL_HTMSC_XSTOP_STOP = 13 ;
+static const uint8_t P9N2_EQ_HTM_CTRL_HTMSC_SPARE1415 = 14 ;
+static const uint8_t P9N2_EQ_HTM_CTRL_HTMSC_SPARE1415_LEN = 2 ;
+
+static const uint8_t P9N2_EX_HTM_CTRL_HTMSC_TRIG = 0 ;
+static const uint8_t P9N2_EX_HTM_CTRL_HTMSC_TRIG_LEN = 2 ;
+static const uint8_t P9N2_EX_HTM_CTRL_HTMSC_MTSPR_TRIG = 2 ;
+static const uint8_t P9N2_EX_HTM_CTRL_HTMSC_MTSPR_MARK = 3 ;
+static const uint8_t P9N2_EX_HTM_CTRL_HTMSC_MARK = 4 ;
+static const uint8_t P9N2_EX_HTM_CTRL_HTMSC_MARK_LEN = 2 ;
+static const uint8_t P9N2_EX_HTM_CTRL_HTMSC_DBG0_STOP = 6 ;
+static const uint8_t P9N2_EX_HTM_CTRL_HTMSC_DBG1_STOP = 7 ;
+static const uint8_t P9N2_EX_HTM_CTRL_HTMSC_RUN_STOP = 8 ;
+static const uint8_t P9N2_EX_HTM_CTRL_HTMSC_CHIP0_STOP = 9 ;
+static const uint8_t P9N2_EX_HTM_CTRL_HTMSC_CHIP1_STOP = 10 ;
+static const uint8_t P9N2_EX_HTM_CTRL_HTMSC_SPARE1112 = 11 ;
+static const uint8_t P9N2_EX_HTM_CTRL_HTMSC_SPARE1112_LEN = 2 ;
+static const uint8_t P9N2_EX_HTM_CTRL_HTMSC_XSTOP_STOP = 13 ;
+static const uint8_t P9N2_EX_HTM_CTRL_HTMSC_SPARE1415 = 14 ;
+static const uint8_t P9N2_EX_HTM_CTRL_HTMSC_SPARE1415_LEN = 2 ;
+
+static const uint8_t P9N2_EQ_HTM_IMA_PDBAR_HTMSC_ENABLE_SPLIT_CORE = 1 ;
+static const uint8_t P9N2_EQ_HTM_IMA_PDBAR_HTMSC_SPARE2TO4 = 2 ;
+static const uint8_t P9N2_EQ_HTM_IMA_PDBAR_HTMSC_SPARE2TO4_LEN = 3 ;
+static const uint8_t P9N2_EQ_HTM_IMA_PDBAR_HTMSC_SCOPE = 5 ;
+static const uint8_t P9N2_EQ_HTM_IMA_PDBAR_HTMSC_SCOPE_LEN = 3 ;
+static const uint8_t P9N2_EQ_HTM_IMA_PDBAR_HTMSC = 8 ;
+static const uint8_t P9N2_EQ_HTM_IMA_PDBAR_HTMSC_LEN = 43 ;
+
+static const uint8_t P9N2_EX_HTM_IMA_PDBAR_HTMSC_ENABLE_SPLIT_CORE = 1 ;
+static const uint8_t P9N2_EX_HTM_IMA_PDBAR_HTMSC_SPARE2TO4 = 2 ;
+static const uint8_t P9N2_EX_HTM_IMA_PDBAR_HTMSC_SPARE2TO4_LEN = 3 ;
+static const uint8_t P9N2_EX_HTM_IMA_PDBAR_HTMSC_SCOPE = 5 ;
+static const uint8_t P9N2_EX_HTM_IMA_PDBAR_HTMSC_SCOPE_LEN = 3 ;
+static const uint8_t P9N2_EX_HTM_IMA_PDBAR_HTMSC = 8 ;
+static const uint8_t P9N2_EX_HTM_IMA_PDBAR_HTMSC_LEN = 43 ;
+
+static const uint8_t P9N2_EQ_HTM_IMA_STATUS_HTMSC_ERROR = 0 ;
+static const uint8_t P9N2_EQ_HTM_IMA_STATUS_HTMSC_TRACE_ACTIVE = 1 ;
+static const uint8_t P9N2_EQ_HTM_IMA_STATUS_HTMSC_PDBAR_ERROR = 2 ;
+static const uint8_t P9N2_EQ_HTM_IMA_STATUS_HTMSC_RESERVED = 3 ;
+static const uint8_t P9N2_EQ_HTM_IMA_STATUS_HTMSC_RESERVED_LEN = 2 ;
+static const uint8_t P9N2_EQ_HTM_IMA_STATUS_HTMSC_FSM = 5 ;
+static const uint8_t P9N2_EQ_HTM_IMA_STATUS_HTMSC_FSM_LEN = 7 ;
+static const uint8_t P9N2_EQ_HTM_IMA_STATUS_HTMSC_COUNT = 12 ;
+static const uint8_t P9N2_EQ_HTM_IMA_STATUS_HTMSC_COUNT_LEN = 4 ;
+
+static const uint8_t P9N2_EX_HTM_IMA_STATUS_HTMSC_ERROR = 0 ;
+static const uint8_t P9N2_EX_HTM_IMA_STATUS_HTMSC_TRACE_ACTIVE = 1 ;
+static const uint8_t P9N2_EX_HTM_IMA_STATUS_HTMSC_PDBAR_ERROR = 2 ;
+static const uint8_t P9N2_EX_HTM_IMA_STATUS_HTMSC_RESERVED = 3 ;
+static const uint8_t P9N2_EX_HTM_IMA_STATUS_HTMSC_RESERVED_LEN = 2 ;
+static const uint8_t P9N2_EX_HTM_IMA_STATUS_HTMSC_FSM = 5 ;
+static const uint8_t P9N2_EX_HTM_IMA_STATUS_HTMSC_FSM_LEN = 7 ;
+static const uint8_t P9N2_EX_HTM_IMA_STATUS_HTMSC_COUNT = 12 ;
+static const uint8_t P9N2_EX_HTM_IMA_STATUS_HTMSC_COUNT_LEN = 4 ;
+
+static const uint8_t P9N2_EQ_HTM_LAST_ADDRESS = 8 ;
+static const uint8_t P9N2_EQ_HTM_LAST_ADDRESS_LEN = 49 ;
+
+static const uint8_t P9N2_EX_HTM_LAST_ADDRESS = 8 ;
+static const uint8_t P9N2_EX_HTM_LAST_ADDRESS_LEN = 49 ;
+
+static const uint8_t P9N2_EQ_HTM_MEM_HTMSC_ALLOC = 0 ;
+static const uint8_t P9N2_EQ_HTM_MEM_HTMSC_SCOPE = 1 ;
+static const uint8_t P9N2_EQ_HTM_MEM_HTMSC_SCOPE_LEN = 3 ;
+static const uint8_t P9N2_EQ_HTM_MEM_HTMSC_PRIORITY = 4 ;
+static const uint8_t P9N2_EQ_HTM_MEM_HTMSC_SIZE_SMALL = 5 ;
+static const uint8_t P9N2_EQ_HTM_MEM_HTMSC_SPARE = 6 ;
+static const uint8_t P9N2_EQ_HTM_MEM_HTMSC_SPARE_LEN = 2 ;
+static const uint8_t P9N2_EQ_HTM_MEM_HTMSC_BASE = 8 ;
+static const uint8_t P9N2_EQ_HTM_MEM_HTMSC_BASE_LEN = 32 ;
+static const uint8_t P9N2_EQ_HTM_MEM_HTMSC_SIZE = 40 ;
+static const uint8_t P9N2_EQ_HTM_MEM_HTMSC_SIZE_LEN = 9 ;
+
+static const uint8_t P9N2_EX_HTM_MEM_HTMSC_ALLOC = 0 ;
+static const uint8_t P9N2_EX_HTM_MEM_HTMSC_SCOPE = 1 ;
+static const uint8_t P9N2_EX_HTM_MEM_HTMSC_SCOPE_LEN = 3 ;
+static const uint8_t P9N2_EX_HTM_MEM_HTMSC_PRIORITY = 4 ;
+static const uint8_t P9N2_EX_HTM_MEM_HTMSC_SIZE_SMALL = 5 ;
+static const uint8_t P9N2_EX_HTM_MEM_HTMSC_SPARE = 6 ;
+static const uint8_t P9N2_EX_HTM_MEM_HTMSC_SPARE_LEN = 2 ;
+static const uint8_t P9N2_EX_HTM_MEM_HTMSC_BASE = 8 ;
+static const uint8_t P9N2_EX_HTM_MEM_HTMSC_BASE_LEN = 32 ;
+static const uint8_t P9N2_EX_HTM_MEM_HTMSC_SIZE = 40 ;
+static const uint8_t P9N2_EX_HTM_MEM_HTMSC_SIZE_LEN = 9 ;
+
+static const uint8_t P9N2_EQ_HTM_MODE_HTMSC_ENABLE = 0 ;
+static const uint8_t P9N2_EQ_HTM_MODE_HTMSC_CONTENT_SEL = 1 ;
+static const uint8_t P9N2_EQ_HTM_MODE_HTMSC_CONTENT_SEL_LEN = 2 ;
+static const uint8_t P9N2_EQ_HTM_MODE_HTMSC_SPARE0 = 3 ;
+static const uint8_t P9N2_EQ_HTM_MODE_HTMSC_CAPTURE = 4 ;
+static const uint8_t P9N2_EQ_HTM_MODE_HTMSC_CAPTURE_LEN = 6 ;
+static const uint8_t P9N2_EQ_HTM_MODE_HTMSC_DD1EQUIV = 10 ;
+static const uint8_t P9N2_EQ_HTM_MODE_HTMSC_SPARE_1TO2 = 11 ;
+static const uint8_t P9N2_EQ_HTM_MODE_HTMSC_SPARE_1TO2_LEN = 2 ;
+static const uint8_t P9N2_EQ_HTM_MODE_HTMSC_WRAP = 13 ;
+static const uint8_t P9N2_EQ_HTM_MODE_HTMSC_DIS_TSTAMP = 14 ;
+static const uint8_t P9N2_EQ_HTM_MODE_HTMSC_SINGLE_TSTAMP = 15 ;
+static const uint8_t P9N2_EQ_HTM_MODE_HTMSC_DIS_STALL = 16 ;
+static const uint8_t P9N2_EQ_HTM_MODE_HTMSC_MARKERS_ONLY = 17 ;
+static const uint8_t P9N2_EQ_HTM_MODE_HTMSC_DIS_GROUP = 18 ;
+static const uint8_t P9N2_EQ_HTM_MODE_HTMSC_SPARES = 19 ;
+static const uint8_t P9N2_EQ_HTM_MODE_HTMSC_SPARES_LEN = 5 ;
+static const uint8_t P9N2_EQ_HTM_MODE_HTMSC_VGTARGET = 24 ;
+static const uint8_t P9N2_EQ_HTM_MODE_HTMSC_VGTARGET_LEN = 16 ;
+
+static const uint8_t P9N2_EX_HTM_MODE_HTMSC_ENABLE = 0 ;
+static const uint8_t P9N2_EX_HTM_MODE_HTMSC_CONTENT_SEL = 1 ;
+static const uint8_t P9N2_EX_HTM_MODE_HTMSC_CONTENT_SEL_LEN = 2 ;
+static const uint8_t P9N2_EX_HTM_MODE_HTMSC_SPARE0 = 3 ;
+static const uint8_t P9N2_EX_HTM_MODE_HTMSC_CAPTURE = 4 ;
+static const uint8_t P9N2_EX_HTM_MODE_HTMSC_CAPTURE_LEN = 6 ;
+static const uint8_t P9N2_EX_HTM_MODE_HTMSC_DD1EQUIV = 10 ;
+static const uint8_t P9N2_EX_HTM_MODE_HTMSC_SPARE_1TO2 = 11 ;
+static const uint8_t P9N2_EX_HTM_MODE_HTMSC_SPARE_1TO2_LEN = 2 ;
+static const uint8_t P9N2_EX_HTM_MODE_HTMSC_WRAP = 13 ;
+static const uint8_t P9N2_EX_HTM_MODE_HTMSC_DIS_TSTAMP = 14 ;
+static const uint8_t P9N2_EX_HTM_MODE_HTMSC_SINGLE_TSTAMP = 15 ;
+static const uint8_t P9N2_EX_HTM_MODE_HTMSC_DIS_STALL = 16 ;
+static const uint8_t P9N2_EX_HTM_MODE_HTMSC_MARKERS_ONLY = 17 ;
+static const uint8_t P9N2_EX_HTM_MODE_HTMSC_DIS_GROUP = 18 ;
+static const uint8_t P9N2_EX_HTM_MODE_HTMSC_SPARES = 19 ;
+static const uint8_t P9N2_EX_HTM_MODE_HTMSC_SPARES_LEN = 5 ;
+static const uint8_t P9N2_EX_HTM_MODE_HTMSC_VGTARGET = 24 ;
+static const uint8_t P9N2_EX_HTM_MODE_HTMSC_VGTARGET_LEN = 16 ;
+
+static const uint8_t P9N2_EQ_HTM_STAT_HTMCO_STATUS_PURGE_IN_PROG = 0 ;
+static const uint8_t P9N2_EQ_HTM_STAT_HTMCO_STATUS_PURGE_DONE = 1 ;
+static const uint8_t P9N2_EQ_HTM_STAT_HTMCO_STATUS_CRESP_OV = 2 ;
+static const uint8_t P9N2_EQ_HTM_STAT_HTMCO_STATUS_REPAIR = 3 ;
+static const uint8_t P9N2_EQ_HTM_STAT_HTMCO_STATUS_BUF_WAIT = 4 ;
+static const uint8_t P9N2_EQ_HTM_STAT_STATUS_TRIG_DROPPED_Q = 5 ;
+static const uint8_t P9N2_EQ_HTM_STAT_HTMCO_STATUS_ADDR_ERROR = 6 ;
+static const uint8_t P9N2_EQ_HTM_STAT_STATUS_REC_DROPPED_Q = 7 ;
+static const uint8_t P9N2_EQ_HTM_STAT_HTMCO_STATUS_INIT = 8 ;
+static const uint8_t P9N2_EQ_HTM_STAT_HTMCO_STATUS_PREREQ = 9 ;
+static const uint8_t P9N2_EQ_HTM_STAT_HTMCO_STATUS_READY = 10 ;
+static const uint8_t P9N2_EQ_HTM_STAT_HTMCO_STATUS_TRACING = 11 ;
+static const uint8_t P9N2_EQ_HTM_STAT_HTMCO_STATUS_PAUSED = 12 ;
+static const uint8_t P9N2_EQ_HTM_STAT_HTMCO_STATUS_FLUSH = 13 ;
+static const uint8_t P9N2_EQ_HTM_STAT_HTMCO_STATUS_COMPLETE = 14 ;
+static const uint8_t P9N2_EQ_HTM_STAT_HTMCO_STATUS_ENABLE = 15 ;
+static const uint8_t P9N2_EQ_HTM_STAT_HTMCO_STATUS_STAMP = 16 ;
+static const uint8_t P9N2_EQ_HTM_STAT_STATUS_SCOM_ERROR = 17 ;
+static const uint8_t P9N2_EQ_HTM_STAT_STATUS_UNUSED = 18 ;
+static const uint8_t P9N2_EQ_HTM_STAT_STATUS_UNUSED_LEN = 2 ;
+
+static const uint8_t P9N2_EX_HTM_STAT_HTMCO_STATUS_PURGE_IN_PROG = 0 ;
+static const uint8_t P9N2_EX_HTM_STAT_HTMCO_STATUS_PURGE_DONE = 1 ;
+static const uint8_t P9N2_EX_HTM_STAT_HTMCO_STATUS_CRESP_OV = 2 ;
+static const uint8_t P9N2_EX_HTM_STAT_HTMCO_STATUS_REPAIR = 3 ;
+static const uint8_t P9N2_EX_HTM_STAT_HTMCO_STATUS_BUF_WAIT = 4 ;
+static const uint8_t P9N2_EX_HTM_STAT_STATUS_TRIG_DROPPED_Q = 5 ;
+static const uint8_t P9N2_EX_HTM_STAT_HTMCO_STATUS_ADDR_ERROR = 6 ;
+static const uint8_t P9N2_EX_HTM_STAT_STATUS_REC_DROPPED_Q = 7 ;
+static const uint8_t P9N2_EX_HTM_STAT_HTMCO_STATUS_INIT = 8 ;
+static const uint8_t P9N2_EX_HTM_STAT_HTMCO_STATUS_PREREQ = 9 ;
+static const uint8_t P9N2_EX_HTM_STAT_HTMCO_STATUS_READY = 10 ;
+static const uint8_t P9N2_EX_HTM_STAT_HTMCO_STATUS_TRACING = 11 ;
+static const uint8_t P9N2_EX_HTM_STAT_HTMCO_STATUS_PAUSED = 12 ;
+static const uint8_t P9N2_EX_HTM_STAT_HTMCO_STATUS_FLUSH = 13 ;
+static const uint8_t P9N2_EX_HTM_STAT_HTMCO_STATUS_COMPLETE = 14 ;
+static const uint8_t P9N2_EX_HTM_STAT_HTMCO_STATUS_ENABLE = 15 ;
+static const uint8_t P9N2_EX_HTM_STAT_HTMCO_STATUS_STAMP = 16 ;
+static const uint8_t P9N2_EX_HTM_STAT_STATUS_SCOM_ERROR = 17 ;
+static const uint8_t P9N2_EX_HTM_STAT_STATUS_UNUSED = 18 ;
+static const uint8_t P9N2_EX_HTM_STAT_STATUS_UNUSED_LEN = 2 ;
+
+static const uint8_t P9N2_EQ_HTM_TRIG_HTMSC_START = 0 ;
+static const uint8_t P9N2_EQ_HTM_TRIG_HTMSC_STOP = 1 ;
+static const uint8_t P9N2_EQ_HTM_TRIG_HTMSC_PAUSE = 2 ;
+static const uint8_t P9N2_EQ_HTM_TRIG_HTMSC_STOP_ALT = 3 ;
+static const uint8_t P9N2_EQ_HTM_TRIG_HTMSC_RESET = 4 ;
+static const uint8_t P9N2_EQ_HTM_TRIG_HTMSC_MARK_VALID = 5 ;
+static const uint8_t P9N2_EQ_HTM_TRIG_HTMSC_MARK_TYPE = 6 ;
+static const uint8_t P9N2_EQ_HTM_TRIG_HTMSC_MARK_TYPE_LEN = 10 ;
+
+static const uint8_t P9N2_EX_HTM_TRIG_HTMSC_START = 0 ;
+static const uint8_t P9N2_EX_HTM_TRIG_HTMSC_STOP = 1 ;
+static const uint8_t P9N2_EX_HTM_TRIG_HTMSC_PAUSE = 2 ;
+static const uint8_t P9N2_EX_HTM_TRIG_HTMSC_STOP_ALT = 3 ;
+static const uint8_t P9N2_EX_HTM_TRIG_HTMSC_RESET = 4 ;
+static const uint8_t P9N2_EX_HTM_TRIG_HTMSC_MARK_VALID = 5 ;
+static const uint8_t P9N2_EX_HTM_TRIG_HTMSC_MARK_TYPE = 6 ;
+static const uint8_t P9N2_EX_HTM_TRIG_HTMSC_MARK_TYPE_LEN = 10 ;
+
+static const uint8_t P9N2_EX_L2_HV_STATE_VT0_MSR_HV = 56 ;
+static const uint8_t P9N2_EX_L2_HV_STATE_VT1_MSR_HV = 57 ;
+static const uint8_t P9N2_EX_L2_HV_STATE_VT2_MSR_HV = 58 ;
+static const uint8_t P9N2_EX_L2_HV_STATE_VT3_MSR_HV = 59 ;
+static const uint8_t P9N2_EX_L2_HV_STATE_VT0_MSR_PR = 60 ;
+static const uint8_t P9N2_EX_L2_HV_STATE_VT1_MSR_PR = 61 ;
+static const uint8_t P9N2_EX_L2_HV_STATE_VT2_MSR_PR = 62 ;
+static const uint8_t P9N2_EX_L2_HV_STATE_VT3_MSR_PR = 63 ;
+
+static const uint8_t P9N2_C_HV_STATE_VT0_MSR_HV = 56 ;
+static const uint8_t P9N2_C_HV_STATE_VT1_MSR_HV = 57 ;
+static const uint8_t P9N2_C_HV_STATE_VT2_MSR_HV = 58 ;
+static const uint8_t P9N2_C_HV_STATE_VT3_MSR_HV = 59 ;
+static const uint8_t P9N2_C_HV_STATE_VT0_MSR_PR = 60 ;
+static const uint8_t P9N2_C_HV_STATE_VT1_MSR_PR = 61 ;
+static const uint8_t P9N2_C_HV_STATE_VT2_MSR_PR = 62 ;
+static const uint8_t P9N2_C_HV_STATE_VT3_MSR_PR = 63 ;
+
+static const uint8_t P9N2_EX_L2_IFU_HOLD_OUT_0_UNUSED = 0 ;
+static const uint8_t P9N2_EX_L2_IFU_HOLD_OUT_0_UNUSED_LEN = 4 ;
+static const uint8_t P9N2_EX_L2_IFU_HOLD_OUT_0_IFFBC_EAT_OVERFLOW_HOLD_OUT_2 = 4 ;
+static const uint8_t P9N2_EX_L2_IFU_HOLD_OUT_0_IFFBC_EATAG_MISMATCHES_IFAR_HOLD_OUT_2 = 5 ;
+static const uint8_t P9N2_EX_L2_IFU_HOLD_OUT_0_IFFBC_IFAR_PARITY_HOLD_OUT_2 = 6 ;
+static const uint8_t P9N2_EX_L2_IFU_HOLD_OUT_0_IFFBC_LNK_STK_OR_CC_PTY_HOLD_OUT_2 = 7 ;
+static const uint8_t P9N2_EX_L2_IFU_HOLD_OUT_0_IFFBC_MULTI_THREAD_HOLD_OUT_2 = 8 ;
+static const uint8_t P9N2_EX_L2_IFU_HOLD_OUT_0_IFFBC_EAT_UNDERFLOW_HOLD_OUT_2 = 9 ;
+static const uint8_t P9N2_EX_L2_IFU_HOLD_OUT_0_IFFSE_SPR_PARITY_HOLD_OUT_2 = 10 ;
+static const uint8_t P9N2_EX_L2_IFU_HOLD_OUT_0_IFFAC_EAT_WRITE_CONFLICT_HOLD_OUT_2 = 11 ;
+static const uint8_t P9N2_EX_L2_IFU_HOLD_OUT_0_IFFEC_DYNAMIC_IC_DELETE_HOLD_OUT = 12 ;
+static const uint8_t P9N2_EX_L2_IFU_HOLD_OUT_0_IFFEC_EADIR_ILLEGAL_HOLD_OUT = 13 ;
+static const uint8_t P9N2_EX_L2_IFU_HOLD_OUT_0_IFFEC_ERAT_PTY_HOLD_OUT = 14 ;
+static const uint8_t P9N2_EX_L2_IFU_HOLD_OUT_0_IFFEC_ICACHE_MISSING_EADIR_WRT_HOLD_OUT = 15 ;
+
+static const uint8_t P9N2_C_IFU_HOLD_OUT_0_UNUSED = 0 ;
+static const uint8_t P9N2_C_IFU_HOLD_OUT_0_UNUSED_LEN = 4 ;
+static const uint8_t P9N2_C_IFU_HOLD_OUT_0_IFFBC_EAT_OVERFLOW_HOLD_OUT_2 = 4 ;
+static const uint8_t P9N2_C_IFU_HOLD_OUT_0_IFFBC_EATAG_MISMATCHES_IFAR_HOLD_OUT_2 = 5 ;
+static const uint8_t P9N2_C_IFU_HOLD_OUT_0_IFFBC_IFAR_PARITY_HOLD_OUT_2 = 6 ;
+static const uint8_t P9N2_C_IFU_HOLD_OUT_0_IFFBC_LNK_STK_OR_CC_PTY_HOLD_OUT_2 = 7 ;
+static const uint8_t P9N2_C_IFU_HOLD_OUT_0_IFFBC_MULTI_THREAD_HOLD_OUT_2 = 8 ;
+static const uint8_t P9N2_C_IFU_HOLD_OUT_0_IFFBC_EAT_UNDERFLOW_HOLD_OUT_2 = 9 ;
+static const uint8_t P9N2_C_IFU_HOLD_OUT_0_IFFSE_SPR_PARITY_HOLD_OUT_2 = 10 ;
+static const uint8_t P9N2_C_IFU_HOLD_OUT_0_IFFAC_EAT_WRITE_CONFLICT_HOLD_OUT_2 = 11 ;
+static const uint8_t P9N2_C_IFU_HOLD_OUT_0_IFFEC_DYNAMIC_IC_DELETE_HOLD_OUT = 12 ;
+static const uint8_t P9N2_C_IFU_HOLD_OUT_0_IFFEC_EADIR_ILLEGAL_HOLD_OUT = 13 ;
+static const uint8_t P9N2_C_IFU_HOLD_OUT_0_IFFEC_ERAT_PTY_HOLD_OUT = 14 ;
+static const uint8_t P9N2_C_IFU_HOLD_OUT_0_IFFEC_ICACHE_MISSING_EADIR_WRT_HOLD_OUT = 15 ;
+
+static const uint8_t P9N2_EX_L2_IFU_HOLD_OUT_1_IFFEC_ICACHE_PE_HOLD_OUT = 0 ;
+static const uint8_t P9N2_EX_L2_IFU_HOLD_OUT_1_IFFEC_IDIR_EA_PTY_HOLD_OUT = 1 ;
+static const uint8_t P9N2_EX_L2_IFU_HOLD_OUT_1_IFFEC_IDIR_PTY_HOLD_OUT = 2 ;
+static const uint8_t P9N2_EX_L2_IFU_HOLD_OUT_1_IFFEC_IERAT_WRT_EA_HOLD_OUT = 3 ;
+static const uint8_t P9N2_EX_L2_IFU_HOLD_OUT_1_IFFEC_IFAR_CHECK1_HOLD_OUT = 4 ;
+static const uint8_t P9N2_EX_L2_IFU_HOLD_OUT_1_IFFEC_IFAR_CHECK2_HOLD_OUT = 5 ;
+static const uint8_t P9N2_EX_L2_IFU_HOLD_OUT_1_IFFEC_IFFIW_IDIR_HOLD_OUT = 6 ;
+static const uint8_t P9N2_EX_L2_IFU_HOLD_OUT_1_IFDPOP_IBUF_PERR_HOLD_OUT_2_0 = 7 ;
+static const uint8_t P9N2_EX_L2_IFU_HOLD_OUT_1_IFDPOP_IBUF_PERR_HOLD_OUT_2 = 8 ;
+static const uint8_t P9N2_EX_L2_IFU_HOLD_OUT_1_IFDPOP_IBUF_PERR_HOLD_OUT_2_2 = 9 ;
+static const uint8_t P9N2_EX_L2_IFU_HOLD_OUT_1_IFDPOP_IBUF_PERR_HOLD_OUT_2_3 = 10 ;
+static const uint8_t P9N2_EX_L2_IFU_HOLD_OUT_1_IFDPOP_IBUF_PERR_HOLD_OUT_2_4 = 11 ;
+static const uint8_t P9N2_EX_L2_IFU_HOLD_OUT_1_IFDPOP_IBUF_PERR_HOLD_OUT_2_5 = 12 ;
+static const uint8_t P9N2_EX_L2_IFU_HOLD_OUT_1_IFFLC_WRITE_COLL_HOLD_OUT_2 = 13 ;
+static const uint8_t P9N2_EX_L2_IFU_HOLD_OUT_1_IFDFE_IDU_FETCH_LENGTH_ERROR_HOLD_OUT_2 = 14 ;
+static const uint8_t P9N2_EX_L2_IFU_HOLD_OUT_1_IFDFE_IBUF_OVERRUN_ERROR_HOLD_OUT_2 = 15 ;
+
+static const uint8_t P9N2_C_IFU_HOLD_OUT_1_IFFEC_ICACHE_PE_HOLD_OUT = 0 ;
+static const uint8_t P9N2_C_IFU_HOLD_OUT_1_IFFEC_IDIR_EA_PTY_HOLD_OUT = 1 ;
+static const uint8_t P9N2_C_IFU_HOLD_OUT_1_IFFEC_IDIR_PTY_HOLD_OUT = 2 ;
+static const uint8_t P9N2_C_IFU_HOLD_OUT_1_IFFEC_IERAT_WRT_EA_HOLD_OUT = 3 ;
+static const uint8_t P9N2_C_IFU_HOLD_OUT_1_IFFEC_IFAR_CHECK1_HOLD_OUT = 4 ;
+static const uint8_t P9N2_C_IFU_HOLD_OUT_1_IFFEC_IFAR_CHECK2_HOLD_OUT = 5 ;
+static const uint8_t P9N2_C_IFU_HOLD_OUT_1_IFFEC_IFFIW_IDIR_HOLD_OUT = 6 ;
+static const uint8_t P9N2_C_IFU_HOLD_OUT_1_IFDPOP_IBUF_PERR_HOLD_OUT_2_0 = 7 ;
+static const uint8_t P9N2_C_IFU_HOLD_OUT_1_IFDPOP_IBUF_PERR_HOLD_OUT_2 = 8 ;
+static const uint8_t P9N2_C_IFU_HOLD_OUT_1_IFDPOP_IBUF_PERR_HOLD_OUT_2_2 = 9 ;
+static const uint8_t P9N2_C_IFU_HOLD_OUT_1_IFDPOP_IBUF_PERR_HOLD_OUT_2_3 = 10 ;
+static const uint8_t P9N2_C_IFU_HOLD_OUT_1_IFDPOP_IBUF_PERR_HOLD_OUT_2_4 = 11 ;
+static const uint8_t P9N2_C_IFU_HOLD_OUT_1_IFDPOP_IBUF_PERR_HOLD_OUT_2_5 = 12 ;
+static const uint8_t P9N2_C_IFU_HOLD_OUT_1_IFFLC_WRITE_COLL_HOLD_OUT_2 = 13 ;
+static const uint8_t P9N2_C_IFU_HOLD_OUT_1_IFDFE_IDU_FETCH_LENGTH_ERROR_HOLD_OUT_2 = 14 ;
+static const uint8_t P9N2_C_IFU_HOLD_OUT_1_IFDFE_IBUF_OVERRUN_ERROR_HOLD_OUT_2 = 15 ;
+
+static const uint8_t P9N2_EX_L2_IFU_HOLD_OUT_2_IFFSE_MFSPR_COLLISION_ERR_HOLD_OUT = 0 ;
+static const uint8_t P9N2_EX_L2_IFU_HOLD_OUT_2_IFFPF_IFAR_VLD_IN_QERR_HOLD_OUT = 1 ;
+static const uint8_t P9N2_EX_L2_IFU_HOLD_OUT_2_IFFPF_L2_RELOAD_COMING_QERR_HOLD_OUT = 2 ;
+static const uint8_t P9N2_EX_L2_IFU_HOLD_OUT_2_IFFPF_L2_RELOAD_INTERF_QERR_HOLD_OUT = 3 ;
+static const uint8_t P9N2_EX_L2_IFU_HOLD_OUT_2_IFFPF_MULTI_RLDM_HAS_SAME_EA_QERR_HOLD_OUT = 4 ;
+static const uint8_t P9N2_EX_L2_IFU_HOLD_OUT_2_IFFCP_CIABR_PERR_HOLD_OUT = 5 ;
+static const uint8_t P9N2_EX_L2_IFU_HOLD_OUT_2_UNUSED_1 = 6 ;
+static const uint8_t P9N2_EX_L2_IFU_HOLD_OUT_2_IFFMSR_MSR_DATA_PERR_HOLD_OUT_3 = 7 ;
+static const uint8_t P9N2_EX_L2_IFU_HOLD_OUT_2_IFBBC_BREX_PRED_CHECKER_HOLD_OUT = 8 ;
+static const uint8_t P9N2_EX_L2_IFU_HOLD_OUT_2_IFBBX_RFILE_EAT_BR_ERR_HOLD_OUT_3 = 9 ;
+static const uint8_t P9N2_EX_L2_IFU_HOLD_OUT_2_IFBBX_RFILE_EAT_BRP1_ERR_HOLD_OUT_3 = 10 ;
+static const uint8_t P9N2_EX_L2_IFU_HOLD_OUT_2_IFBBX_RFILE_LKCT0_ARF_ERR_HOLD_OUT_3 = 11 ;
+static const uint8_t P9N2_EX_L2_IFU_HOLD_OUT_2_IFBBX_RFILE_LKCT0_ROB_ERR_HOLD_OUT_3 = 12 ;
+static const uint8_t P9N2_EX_L2_IFU_HOLD_OUT_2_IFBBX_RFILE_LKCT1_ARF_ERR_HOLD_OUT_3 = 13 ;
+static const uint8_t P9N2_EX_L2_IFU_HOLD_OUT_2_IFBBX_RFILE_LKCT1_ROB_ERR_HOLD_OUT_3 = 14 ;
+static const uint8_t P9N2_EX_L2_IFU_HOLD_OUT_2_IFBBC_BREX_ROB_WR_COLLISION_HOLD_OUT = 15 ;
+
+static const uint8_t P9N2_C_IFU_HOLD_OUT_2_IFFSE_MFSPR_COLLISION_ERR_HOLD_OUT = 0 ;
+static const uint8_t P9N2_C_IFU_HOLD_OUT_2_IFFPF_IFAR_VLD_IN_QERR_HOLD_OUT = 1 ;
+static const uint8_t P9N2_C_IFU_HOLD_OUT_2_IFFPF_L2_RELOAD_COMING_QERR_HOLD_OUT = 2 ;
+static const uint8_t P9N2_C_IFU_HOLD_OUT_2_IFFPF_L2_RELOAD_INTERF_QERR_HOLD_OUT = 3 ;
+static const uint8_t P9N2_C_IFU_HOLD_OUT_2_IFFPF_MULTI_RLDM_HAS_SAME_EA_QERR_HOLD_OUT = 4 ;
+static const uint8_t P9N2_C_IFU_HOLD_OUT_2_IFFCP_CIABR_PERR_HOLD_OUT = 5 ;
+static const uint8_t P9N2_C_IFU_HOLD_OUT_2_UNUSED_1 = 6 ;
+static const uint8_t P9N2_C_IFU_HOLD_OUT_2_IFFMSR_MSR_DATA_PERR_HOLD_OUT_3 = 7 ;
+static const uint8_t P9N2_C_IFU_HOLD_OUT_2_IFBBC_BREX_PRED_CHECKER_HOLD_OUT = 8 ;
+static const uint8_t P9N2_C_IFU_HOLD_OUT_2_IFBBX_RFILE_EAT_BR_ERR_HOLD_OUT_3 = 9 ;
+static const uint8_t P9N2_C_IFU_HOLD_OUT_2_IFBBX_RFILE_EAT_BRP1_ERR_HOLD_OUT_3 = 10 ;
+static const uint8_t P9N2_C_IFU_HOLD_OUT_2_IFBBX_RFILE_LKCT0_ARF_ERR_HOLD_OUT_3 = 11 ;
+static const uint8_t P9N2_C_IFU_HOLD_OUT_2_IFBBX_RFILE_LKCT0_ROB_ERR_HOLD_OUT_3 = 12 ;
+static const uint8_t P9N2_C_IFU_HOLD_OUT_2_IFBBX_RFILE_LKCT1_ARF_ERR_HOLD_OUT_3 = 13 ;
+static const uint8_t P9N2_C_IFU_HOLD_OUT_2_IFBBX_RFILE_LKCT1_ROB_ERR_HOLD_OUT_3 = 14 ;
+static const uint8_t P9N2_C_IFU_HOLD_OUT_2_IFBBC_BREX_ROB_WR_COLLISION_HOLD_OUT = 15 ;
+
+static const uint8_t P9N2_EX_L2_IFU_HOLD_OUT_3_IFBSC_MFSPR_LOG_CRIT_P_HOLD_OUT = 0 ;
+static const uint8_t P9N2_EX_L2_IFU_HOLD_OUT_3_IFBSC_MFSPR_LOG_NONCRIT_P_HOLD_OUT = 1 ;
+static const uint8_t P9N2_EX_L2_IFU_HOLD_OUT_3_IFBSC_MFSPR_RFILE_CRIT_P_HOLD_OUT = 2 ;
+static const uint8_t P9N2_EX_L2_IFU_HOLD_OUT_3_IFBSC_MFSPR_RFILE_NONCRIT_P_HOLD_OUT = 3 ;
+static const uint8_t P9N2_EX_L2_IFU_HOLD_OUT_3_IFBBC_BREX_EATAG_OUTOFRANGE_HOLD_OUT_2 = 4 ;
+static const uint8_t P9N2_EX_L2_IFU_HOLD_OUT_3_IFBBC_BREX_FLUSH_CHECKER_HOLD_OUT_2 = 5 ;
+static const uint8_t P9N2_EX_L2_IFU_HOLD_OUT_3_IFFAC_S0_NIA_P_HOLD_OUT = 6 ;
+static const uint8_t P9N2_EX_L2_IFU_HOLD_OUT_3_IFFAC_S0_TAIL_P_HOLD_OUT = 7 ;
+static const uint8_t P9N2_EX_L2_IFU_HOLD_OUT_3_IFFAC_REFETCH_OUTOFRANGE_HOLD_OUT = 8 ;
+static const uint8_t P9N2_EX_L2_IFU_HOLD_OUT_3_IFFAC_S0_COMP_EATAG_OUTOFRANGE_HOLD_OUT = 9 ;
+static const uint8_t P9N2_EX_L2_IFU_HOLD_OUT_3_IFFAC_S0_NIA_EATAG_OUTOFRANGE_HOLD_OUT = 10 ;
+static const uint8_t P9N2_EX_L2_IFU_HOLD_OUT_3_UNUSED_2 = 11 ;
+static const uint8_t P9N2_EX_L2_IFU_HOLD_OUT_3_IFFRC_REFETCH_EAT_P_HOLD_OUT = 12 ;
+static const uint8_t P9N2_EX_L2_IFU_HOLD_OUT_3_IFFRC_REFETCH_SPR_P_HOLD_OUT = 13 ;
+static const uint8_t P9N2_EX_L2_IFU_HOLD_OUT_3_TCC_TC_FIR_SCOM_HOLD_OUT = 14 ;
+static const uint8_t P9N2_EX_L2_IFU_HOLD_OUT_3_UNUSED = 15 ;
+
+static const uint8_t P9N2_C_IFU_HOLD_OUT_3_IFBSC_MFSPR_LOG_CRIT_P_HOLD_OUT = 0 ;
+static const uint8_t P9N2_C_IFU_HOLD_OUT_3_IFBSC_MFSPR_LOG_NONCRIT_P_HOLD_OUT = 1 ;
+static const uint8_t P9N2_C_IFU_HOLD_OUT_3_IFBSC_MFSPR_RFILE_CRIT_P_HOLD_OUT = 2 ;
+static const uint8_t P9N2_C_IFU_HOLD_OUT_3_IFBSC_MFSPR_RFILE_NONCRIT_P_HOLD_OUT = 3 ;
+static const uint8_t P9N2_C_IFU_HOLD_OUT_3_IFBBC_BREX_EATAG_OUTOFRANGE_HOLD_OUT_2 = 4 ;
+static const uint8_t P9N2_C_IFU_HOLD_OUT_3_IFBBC_BREX_FLUSH_CHECKER_HOLD_OUT_2 = 5 ;
+static const uint8_t P9N2_C_IFU_HOLD_OUT_3_IFFAC_S0_NIA_P_HOLD_OUT = 6 ;
+static const uint8_t P9N2_C_IFU_HOLD_OUT_3_IFFAC_S0_TAIL_P_HOLD_OUT = 7 ;
+static const uint8_t P9N2_C_IFU_HOLD_OUT_3_IFFAC_REFETCH_OUTOFRANGE_HOLD_OUT = 8 ;
+static const uint8_t P9N2_C_IFU_HOLD_OUT_3_IFFAC_S0_COMP_EATAG_OUTOFRANGE_HOLD_OUT = 9 ;
+static const uint8_t P9N2_C_IFU_HOLD_OUT_3_IFFAC_S0_NIA_EATAG_OUTOFRANGE_HOLD_OUT = 10 ;
+static const uint8_t P9N2_C_IFU_HOLD_OUT_3_UNUSED_2 = 11 ;
+static const uint8_t P9N2_C_IFU_HOLD_OUT_3_IFFRC_REFETCH_EAT_P_HOLD_OUT = 12 ;
+static const uint8_t P9N2_C_IFU_HOLD_OUT_3_IFFRC_REFETCH_SPR_P_HOLD_OUT = 13 ;
+static const uint8_t P9N2_C_IFU_HOLD_OUT_3_TCC_TC_FIR_SCOM_HOLD_OUT = 14 ;
+static const uint8_t P9N2_C_IFU_HOLD_OUT_3_UNUSED = 15 ;
+
+static const uint8_t P9N2_EX_IMA_EVENT_MASK_ECONL_0 = 0 ;
+static const uint8_t P9N2_EX_IMA_EVENT_MASK_ECRL_0 = 1 ;
+static const uint8_t P9N2_EX_IMA_EVENT_MASK_ECH_0 = 2 ;
+static const uint8_t P9N2_EX_IMA_EVENT_MASK_ECP_0 = 3 ;
+static const uint8_t P9N2_EX_IMA_EVENT_MASK_ECS_0 = 4 ;
+static const uint8_t P9N2_EX_IMA_EVENT_MASK_ECA_0 = 5 ;
+static const uint8_t P9N2_EX_IMA_EVENT_MASK_ECTA0_0 = 6 ;
+static const uint8_t P9N2_EX_IMA_EVENT_MASK_ECTA1_0 = 7 ;
+static const uint8_t P9N2_EX_IMA_EVENT_MASK_ECUS0_0 = 8 ;
+static const uint8_t P9N2_EX_IMA_EVENT_MASK_ECUS1_0 = 9 ;
+static const uint8_t P9N2_EX_IMA_EVENT_MASK_ECONL_1 = 10 ;
+static const uint8_t P9N2_EX_IMA_EVENT_MASK_ECRL_1 = 11 ;
+static const uint8_t P9N2_EX_IMA_EVENT_MASK_ECH_1 = 12 ;
+static const uint8_t P9N2_EX_IMA_EVENT_MASK_ECP_1 = 13 ;
+static const uint8_t P9N2_EX_IMA_EVENT_MASK_ECS_1 = 14 ;
+static const uint8_t P9N2_EX_IMA_EVENT_MASK_ECA_1 = 15 ;
+static const uint8_t P9N2_EX_IMA_EVENT_MASK_ECTA0_1 = 16 ;
+static const uint8_t P9N2_EX_IMA_EVENT_MASK_ECTA1_1 = 17 ;
+static const uint8_t P9N2_EX_IMA_EVENT_MASK_ECUS0_1 = 18 ;
+static const uint8_t P9N2_EX_IMA_EVENT_MASK_ECUS1_1 = 19 ;
+static const uint8_t P9N2_EX_IMA_EVENT_MASK_ECONL_2 = 20 ;
+static const uint8_t P9N2_EX_IMA_EVENT_MASK_ECRL_2 = 21 ;
+static const uint8_t P9N2_EX_IMA_EVENT_MASK_ECH_2 = 22 ;
+static const uint8_t P9N2_EX_IMA_EVENT_MASK_ECP_2 = 23 ;
+static const uint8_t P9N2_EX_IMA_EVENT_MASK_ECS_2 = 24 ;
+static const uint8_t P9N2_EX_IMA_EVENT_MASK_ECA_2 = 25 ;
+static const uint8_t P9N2_EX_IMA_EVENT_MASK_ECTA0_2 = 26 ;
+static const uint8_t P9N2_EX_IMA_EVENT_MASK_ECTA1_2 = 27 ;
+static const uint8_t P9N2_EX_IMA_EVENT_MASK_ECUS0_2 = 28 ;
+static const uint8_t P9N2_EX_IMA_EVENT_MASK_ECUS1_2 = 29 ;
+static const uint8_t P9N2_EX_IMA_EVENT_MASK_IC_TAP = 30 ;
+static const uint8_t P9N2_EX_IMA_EVENT_MASK_IC_TAP_LEN = 3 ;
+static const uint8_t P9N2_EX_IMA_EVENT_MASK_DISABLE_WRAP = 33 ;
+static const uint8_t P9N2_EX_IMA_EVENT_MASK_CME_POWSAV = 34 ;
+static const uint8_t P9N2_EX_IMA_EVENT_MASK_ONL_OVR = 35 ;
+static const uint8_t P9N2_EX_IMA_EVENT_MASK_DIS_D_PRE = 36 ;
+static const uint8_t P9N2_EX_IMA_EVENT_MASK_DIS_I_PRE = 37 ;
+
+static const uint8_t P9N2_C_IMA_EVENT_MASK_ECONL_0 = 0 ;
+static const uint8_t P9N2_C_IMA_EVENT_MASK_ECRL_0 = 1 ;
+static const uint8_t P9N2_C_IMA_EVENT_MASK_ECH_0 = 2 ;
+static const uint8_t P9N2_C_IMA_EVENT_MASK_ECP_0 = 3 ;
+static const uint8_t P9N2_C_IMA_EVENT_MASK_ECS_0 = 4 ;
+static const uint8_t P9N2_C_IMA_EVENT_MASK_ECA_0 = 5 ;
+static const uint8_t P9N2_C_IMA_EVENT_MASK_ECTA0_0 = 6 ;
+static const uint8_t P9N2_C_IMA_EVENT_MASK_ECTA1_0 = 7 ;
+static const uint8_t P9N2_C_IMA_EVENT_MASK_ECUS0_0 = 8 ;
+static const uint8_t P9N2_C_IMA_EVENT_MASK_ECUS1_0 = 9 ;
+static const uint8_t P9N2_C_IMA_EVENT_MASK_ECONL_1 = 10 ;
+static const uint8_t P9N2_C_IMA_EVENT_MASK_ECRL_1 = 11 ;
+static const uint8_t P9N2_C_IMA_EVENT_MASK_ECH_1 = 12 ;
+static const uint8_t P9N2_C_IMA_EVENT_MASK_ECP_1 = 13 ;
+static const uint8_t P9N2_C_IMA_EVENT_MASK_ECS_1 = 14 ;
+static const uint8_t P9N2_C_IMA_EVENT_MASK_ECA_1 = 15 ;
+static const uint8_t P9N2_C_IMA_EVENT_MASK_ECTA0_1 = 16 ;
+static const uint8_t P9N2_C_IMA_EVENT_MASK_ECTA1_1 = 17 ;
+static const uint8_t P9N2_C_IMA_EVENT_MASK_ECUS0_1 = 18 ;
+static const uint8_t P9N2_C_IMA_EVENT_MASK_ECUS1_1 = 19 ;
+static const uint8_t P9N2_C_IMA_EVENT_MASK_ECONL_2 = 20 ;
+static const uint8_t P9N2_C_IMA_EVENT_MASK_ECRL_2 = 21 ;
+static const uint8_t P9N2_C_IMA_EVENT_MASK_ECH_2 = 22 ;
+static const uint8_t P9N2_C_IMA_EVENT_MASK_ECP_2 = 23 ;
+static const uint8_t P9N2_C_IMA_EVENT_MASK_ECS_2 = 24 ;
+static const uint8_t P9N2_C_IMA_EVENT_MASK_ECA_2 = 25 ;
+static const uint8_t P9N2_C_IMA_EVENT_MASK_ECTA0_2 = 26 ;
+static const uint8_t P9N2_C_IMA_EVENT_MASK_ECTA1_2 = 27 ;
+static const uint8_t P9N2_C_IMA_EVENT_MASK_ECUS0_2 = 28 ;
+static const uint8_t P9N2_C_IMA_EVENT_MASK_ECUS1_2 = 29 ;
+static const uint8_t P9N2_C_IMA_EVENT_MASK_IC_TAP = 30 ;
+static const uint8_t P9N2_C_IMA_EVENT_MASK_IC_TAP_LEN = 3 ;
+static const uint8_t P9N2_C_IMA_EVENT_MASK_DISABLE_WRAP = 33 ;
+static const uint8_t P9N2_C_IMA_EVENT_MASK_CME_POWSAV = 34 ;
+static const uint8_t P9N2_C_IMA_EVENT_MASK_ONL_OVR = 35 ;
+static const uint8_t P9N2_C_IMA_EVENT_MASK_DIS_D_PRE = 36 ;
+static const uint8_t P9N2_C_IMA_EVENT_MASK_DIS_I_PRE = 37 ;
+
+static const uint8_t P9N2_EX_IMA_TRACE_SAMPSEL = 0 ;
+static const uint8_t P9N2_EX_IMA_TRACE_SAMPSEL_LEN = 2 ;
+static const uint8_t P9N2_EX_IMA_TRACE_CPMC_LOAD = 2 ;
+static const uint8_t P9N2_EX_IMA_TRACE_CPMC_LOAD_LEN = 32 ;
+static const uint8_t P9N2_EX_IMA_TRACE_CPMC1SEL = 34 ;
+static const uint8_t P9N2_EX_IMA_TRACE_CPMC1SEL_LEN = 7 ;
+static const uint8_t P9N2_EX_IMA_TRACE_CPMC2SEL = 41 ;
+static const uint8_t P9N2_EX_IMA_TRACE_CPMC2SEL_LEN = 7 ;
+static const uint8_t P9N2_EX_IMA_TRACE_BUFFERSIZE = 48 ;
+static const uint8_t P9N2_EX_IMA_TRACE_BUFFERSIZE_LEN = 3 ;
+
+static const uint8_t P9N2_C_IMA_TRACE_SAMPSEL = 0 ;
+static const uint8_t P9N2_C_IMA_TRACE_SAMPSEL_LEN = 2 ;
+static const uint8_t P9N2_C_IMA_TRACE_CPMC_LOAD = 2 ;
+static const uint8_t P9N2_C_IMA_TRACE_CPMC_LOAD_LEN = 32 ;
+static const uint8_t P9N2_C_IMA_TRACE_CPMC1SEL = 34 ;
+static const uint8_t P9N2_C_IMA_TRACE_CPMC1SEL_LEN = 7 ;
+static const uint8_t P9N2_C_IMA_TRACE_CPMC2SEL = 41 ;
+static const uint8_t P9N2_C_IMA_TRACE_CPMC2SEL_LEN = 7 ;
+static const uint8_t P9N2_C_IMA_TRACE_BUFFERSIZE = 48 ;
+static const uint8_t P9N2_C_IMA_TRACE_BUFFERSIZE_LEN = 3 ;
+
+static const uint8_t P9N2_EQ_INJECT_REG_THERM_TRIP = 0 ;
+static const uint8_t P9N2_EQ_INJECT_REG_THERM_TRIP_LEN = 2 ;
+static const uint8_t P9N2_EQ_INJECT_REG_THERM_MODE = 2 ;
+static const uint8_t P9N2_EQ_INJECT_REG_THERM_MODE_LEN = 2 ;
+
+static const uint8_t P9N2_EX_INJECT_REG_THERM_TRIP = 0 ;
+static const uint8_t P9N2_EX_INJECT_REG_THERM_TRIP_LEN = 2 ;
+static const uint8_t P9N2_EX_INJECT_REG_THERM_MODE = 2 ;
+static const uint8_t P9N2_EX_INJECT_REG_THERM_MODE_LEN = 2 ;
+
+static const uint8_t P9N2_C_INJECT_REG_THERM_TRIP = 0 ;
+static const uint8_t P9N2_C_INJECT_REG_THERM_TRIP_LEN = 2 ;
+static const uint8_t P9N2_C_INJECT_REG_THERM_MODE = 2 ;
+static const uint8_t P9N2_C_INJECT_REG_THERM_MODE_LEN = 2 ;
+
+static const uint8_t P9N2_EQ_INJ_REG_STQ_ERR = 0 ;
+static const uint8_t P9N2_EQ_INJ_REG_STQ_ERR_LEN = 2 ;
+
+static const uint8_t P9N2_EX_INJ_REG_STQ_ERR = 0 ;
+static const uint8_t P9N2_EX_INJ_REG_STQ_ERR_LEN = 2 ;
+
+static const uint8_t P9N2_EX_L2_INV_ERATE_INVALIDATE_ERAT = 63 ;
+
+static const uint8_t P9N2_C_INV_ERATE_INVALIDATE_ERAT = 63 ;
+
+static const uint8_t P9N2_EX_L2_ISU_DEBUG_CTRL_ISU_HLD_OUT_REG6 = 0 ;
+static const uint8_t P9N2_EX_L2_ISU_DEBUG_CTRL_ISU_HLD_OUT_REG6_LEN = 18 ;
+
+static const uint8_t P9N2_C_ISU_DEBUG_CTRL_ISU_HLD_OUT_REG6 = 0 ;
+static const uint8_t P9N2_C_ISU_DEBUG_CTRL_ISU_HLD_OUT_REG6_LEN = 18 ;
+
+static const uint8_t P9N2_EX_L2_ISU_REG0_HOLD_OUT_SDCX_SDCO_T0_HEIR_CHKSTOP_HOLD_OUT = 0 ;
+static const uint8_t P9N2_EX_L2_ISU_REG0_HOLD_OUT_SDCX_SDCO_T0_HSRR1_CHKSTOP_HOLD_OUT = 1 ;
+static const uint8_t P9N2_EX_L2_ISU_REG0_HOLD_OUT_SDCX_SDCO_T0_MSR_CHKSTOP_HOLD_OUT = 2 ;
+static const uint8_t P9N2_EX_L2_ISU_REG0_HOLD_OUT_SDCX_SDCO_T0_SRR1_CHKSTOP_HOLD_OUT = 3 ;
+static const uint8_t P9N2_EX_L2_ISU_REG0_HOLD_OUT_SDCX_SDCO_T0_VRSAVE_BKUP_CHKSTOP_HOLD_OUT = 4 ;
+static const uint8_t P9N2_EX_L2_ISU_REG0_HOLD_OUT_SDCX_SDCO_T0_VRSAVE_CHKSTOP_HOLD_OUT = 5 ;
+static const uint8_t P9N2_EX_L2_ISU_REG0_HOLD_OUT_SDCX_SDCO_T0_FSCR_CHKSTOP_HOLD_OUT = 6 ;
+static const uint8_t P9N2_EX_L2_ISU_REG0_HOLD_OUT_SDCX_SDCO_T0_HFSCR_CHKSTOP_HOLD_OUT = 7 ;
+static const uint8_t P9N2_EX_L2_ISU_REG0_HOLD_OUT_SDCX_SDCO_T0_TEXASR_CHKSTOP_HOLD_OUT = 8 ;
+static const uint8_t P9N2_EX_L2_ISU_REG0_HOLD_OUT_SDCX_SDCO_T0_BESCR_CHKSTOP_HOLD_OUT = 9 ;
+static const uint8_t P9N2_EX_L2_ISU_REG0_HOLD_OUT_SDCX_SDCU_T0_MCHK_AND_ME_EQ_0_HOLD_OUT = 12 ;
+static const uint8_t P9N2_EX_L2_ISU_REG0_HOLD_OUT_SDCR_ERR_INJ = 13 ;
+static const uint8_t P9N2_EX_L2_ISU_REG0_HOLD_OUT_SDCC_T0_HEAD_TAIL_XSTOP = 14 ;
+static const uint8_t P9N2_EX_L2_ISU_REG0_HOLD_OUT_SDCC_T1_HEAD_TAIL_XSTOP = 15 ;
+static const uint8_t P9N2_EX_L2_ISU_REG0_HOLD_OUT_SDCC_T2_HEAD_TAIL_XSTOP = 16 ;
+static const uint8_t P9N2_EX_L2_ISU_REG0_HOLD_OUT_SDCC_T3_HEAD_TAIL_XSTOP = 17 ;
+
+static const uint8_t P9N2_C_ISU_REG0_HOLD_OUT_SDCX_SDCO_T0_HEIR_CHKSTOP_HOLD_OUT = 0 ;
+static const uint8_t P9N2_C_ISU_REG0_HOLD_OUT_SDCX_SDCO_T0_HSRR1_CHKSTOP_HOLD_OUT = 1 ;
+static const uint8_t P9N2_C_ISU_REG0_HOLD_OUT_SDCX_SDCO_T0_MSR_CHKSTOP_HOLD_OUT = 2 ;
+static const uint8_t P9N2_C_ISU_REG0_HOLD_OUT_SDCX_SDCO_T0_SRR1_CHKSTOP_HOLD_OUT = 3 ;
+static const uint8_t P9N2_C_ISU_REG0_HOLD_OUT_SDCX_SDCO_T0_VRSAVE_BKUP_CHKSTOP_HOLD_OUT = 4 ;
+static const uint8_t P9N2_C_ISU_REG0_HOLD_OUT_SDCX_SDCO_T0_VRSAVE_CHKSTOP_HOLD_OUT = 5 ;
+static const uint8_t P9N2_C_ISU_REG0_HOLD_OUT_SDCX_SDCO_T0_FSCR_CHKSTOP_HOLD_OUT = 6 ;
+static const uint8_t P9N2_C_ISU_REG0_HOLD_OUT_SDCX_SDCO_T0_HFSCR_CHKSTOP_HOLD_OUT = 7 ;
+static const uint8_t P9N2_C_ISU_REG0_HOLD_OUT_SDCX_SDCO_T0_TEXASR_CHKSTOP_HOLD_OUT = 8 ;
+static const uint8_t P9N2_C_ISU_REG0_HOLD_OUT_SDCX_SDCO_T0_BESCR_CHKSTOP_HOLD_OUT = 9 ;
+static const uint8_t P9N2_C_ISU_REG0_HOLD_OUT_SDCX_SDCU_T0_MCHK_AND_ME_EQ_0_HOLD_OUT = 12 ;
+static const uint8_t P9N2_C_ISU_REG0_HOLD_OUT_SDCR_ERR_INJ = 13 ;
+static const uint8_t P9N2_C_ISU_REG0_HOLD_OUT_SDCC_T0_HEAD_TAIL_XSTOP = 14 ;
+static const uint8_t P9N2_C_ISU_REG0_HOLD_OUT_SDCC_T1_HEAD_TAIL_XSTOP = 15 ;
+static const uint8_t P9N2_C_ISU_REG0_HOLD_OUT_SDCC_T2_HEAD_TAIL_XSTOP = 16 ;
+static const uint8_t P9N2_C_ISU_REG0_HOLD_OUT_SDCC_T3_HEAD_TAIL_XSTOP = 17 ;
+
+static const uint8_t P9N2_EX_L2_ISU_REG1_HOLD_OUT_SDCX_SDCO_T1_HEIR_CHKSTOP_HOLD_OUT = 0 ;
+static const uint8_t P9N2_EX_L2_ISU_REG1_HOLD_OUT_SDCX_SDCO_T1_HSRR1_CHKSTOP_HOLD_OUT = 1 ;
+static const uint8_t P9N2_EX_L2_ISU_REG1_HOLD_OUT_SDCX_SDCO_T1_MSR_CHKSTOP_HOLD_OUT = 2 ;
+static const uint8_t P9N2_EX_L2_ISU_REG1_HOLD_OUT_SDCX_SDCO_T1_SRR1_CHKSTOP_HOLD_OUT = 3 ;
+static const uint8_t P9N2_EX_L2_ISU_REG1_HOLD_OUT_SDCX_SDCO_T1_VRSAVE_BKUP_CHKSTOP_HOLD_OUT = 4 ;
+static const uint8_t P9N2_EX_L2_ISU_REG1_HOLD_OUT_SDCX_SDCO_T1_VRSAVE_CHKSTOP_HOLD_OUT = 5 ;
+static const uint8_t P9N2_EX_L2_ISU_REG1_HOLD_OUT_SDCX_SDCO_T1_FSCR_CHKSTOP_HOLD_OUT = 6 ;
+static const uint8_t P9N2_EX_L2_ISU_REG1_HOLD_OUT_SDCX_SDCO_T1_HFSCR_CHKSTOP_HOLD_OUT = 7 ;
+static const uint8_t P9N2_EX_L2_ISU_REG1_HOLD_OUT_SDCX_SDCO_T1_TEXASR_CHKSTOP_HOLD_OUT = 8 ;
+static const uint8_t P9N2_EX_L2_ISU_REG1_HOLD_OUT_SDCX_SDCO_T1_BESCR_CHKSTOP_HOLD_OUT = 9 ;
+static const uint8_t P9N2_EX_L2_ISU_REG1_HOLD_OUT_SDCX_SDCU_T1_MCHK_AND_ME_EQ_0_HOLD_OUT = 12 ;
+static const uint8_t P9N2_EX_L2_ISU_REG1_HOLD_OUT_ERR_INJ_RECOV = 13 ;
+static const uint8_t P9N2_EX_L2_ISU_REG1_HOLD_OUT_SDCCC_T0_COMP_RCOV = 14 ;
+static const uint8_t P9N2_EX_L2_ISU_REG1_HOLD_OUT_SDCCC_T1_COMP_RCOV = 15 ;
+static const uint8_t P9N2_EX_L2_ISU_REG1_HOLD_OUT_SDCCC_T2_COMP_RCOV = 16 ;
+static const uint8_t P9N2_EX_L2_ISU_REG1_HOLD_OUT_SDCCC_T3_COMP_RCOV = 17 ;
+
+static const uint8_t P9N2_C_ISU_REG1_HOLD_OUT_SDCX_SDCO_T1_HEIR_CHKSTOP_HOLD_OUT = 0 ;
+static const uint8_t P9N2_C_ISU_REG1_HOLD_OUT_SDCX_SDCO_T1_HSRR1_CHKSTOP_HOLD_OUT = 1 ;
+static const uint8_t P9N2_C_ISU_REG1_HOLD_OUT_SDCX_SDCO_T1_MSR_CHKSTOP_HOLD_OUT = 2 ;
+static const uint8_t P9N2_C_ISU_REG1_HOLD_OUT_SDCX_SDCO_T1_SRR1_CHKSTOP_HOLD_OUT = 3 ;
+static const uint8_t P9N2_C_ISU_REG1_HOLD_OUT_SDCX_SDCO_T1_VRSAVE_BKUP_CHKSTOP_HOLD_OUT = 4 ;
+static const uint8_t P9N2_C_ISU_REG1_HOLD_OUT_SDCX_SDCO_T1_VRSAVE_CHKSTOP_HOLD_OUT = 5 ;
+static const uint8_t P9N2_C_ISU_REG1_HOLD_OUT_SDCX_SDCO_T1_FSCR_CHKSTOP_HOLD_OUT = 6 ;
+static const uint8_t P9N2_C_ISU_REG1_HOLD_OUT_SDCX_SDCO_T1_HFSCR_CHKSTOP_HOLD_OUT = 7 ;
+static const uint8_t P9N2_C_ISU_REG1_HOLD_OUT_SDCX_SDCO_T1_TEXASR_CHKSTOP_HOLD_OUT = 8 ;
+static const uint8_t P9N2_C_ISU_REG1_HOLD_OUT_SDCX_SDCO_T1_BESCR_CHKSTOP_HOLD_OUT = 9 ;
+static const uint8_t P9N2_C_ISU_REG1_HOLD_OUT_SDCX_SDCU_T1_MCHK_AND_ME_EQ_0_HOLD_OUT = 12 ;
+static const uint8_t P9N2_C_ISU_REG1_HOLD_OUT_ERR_INJ_RECOV = 13 ;
+static const uint8_t P9N2_C_ISU_REG1_HOLD_OUT_SDCCC_T0_COMP_RCOV = 14 ;
+static const uint8_t P9N2_C_ISU_REG1_HOLD_OUT_SDCCC_T1_COMP_RCOV = 15 ;
+static const uint8_t P9N2_C_ISU_REG1_HOLD_OUT_SDCCC_T2_COMP_RCOV = 16 ;
+static const uint8_t P9N2_C_ISU_REG1_HOLD_OUT_SDCCC_T3_COMP_RCOV = 17 ;
+
+static const uint8_t P9N2_EX_L2_ISU_REG2_HOLD_OUT_SDCX_SDCO_T2_HEIR_CHKSTOP_HOLD_OUT = 0 ;
+static const uint8_t P9N2_EX_L2_ISU_REG2_HOLD_OUT_SDCX_SDCO_T2_HSRR1_CHKSTOP_HOLD_OUT = 1 ;
+static const uint8_t P9N2_EX_L2_ISU_REG2_HOLD_OUT_SDCX_SDCO_T2_MSR_CHKSTOP_HOLD_OUT = 2 ;
+static const uint8_t P9N2_EX_L2_ISU_REG2_HOLD_OUT_SDCX_SDCO_T2_SRR1_CHKSTOP_HOLD_OUT = 3 ;
+static const uint8_t P9N2_EX_L2_ISU_REG2_HOLD_OUT_SDCX_SDCO_T2_VRSAVE_BKUP_CHKSTOP_HOLD_OUT = 4 ;
+static const uint8_t P9N2_EX_L2_ISU_REG2_HOLD_OUT_SDCX_SDCO_T2_VRSAVE_CHKSTOP_HOLD_OUT = 5 ;
+static const uint8_t P9N2_EX_L2_ISU_REG2_HOLD_OUT_SDCX_SDCO_T2_FSCR_CHKSTOP_HOLD_OUT = 6 ;
+static const uint8_t P9N2_EX_L2_ISU_REG2_HOLD_OUT_SDCX_SDCO_T2_HFSCR_CHKSTOP_HOLD_OUT = 7 ;
+static const uint8_t P9N2_EX_L2_ISU_REG2_HOLD_OUT_SDCX_SDCO_T2_TEXASR_CHKSTOP_HOLD_OUT = 8 ;
+static const uint8_t P9N2_EX_L2_ISU_REG2_HOLD_OUT_SDCX_SDCO_T2_BESCR_CHKSTOP_HOLD_OUT = 9 ;
+static const uint8_t P9N2_EX_L2_ISU_REG2_HOLD_OUT_SDCX_SDCU_T2_MCHK_AND_ME_EQ_0_HOLD_OUT = 12 ;
+static const uint8_t P9N2_EX_L2_ISU_REG2_HOLD_OUT_WAT_INJECT_INT = 13 ;
+static const uint8_t P9N2_EX_L2_ISU_REG2_HOLD_OUT_SDCA_RCOV = 14 ;
+static const uint8_t P9N2_EX_L2_ISU_REG2_HOLD_OUT_SDCU_RAM_XSTOP = 15 ;
+static const uint8_t P9N2_EX_L2_ISU_REG2_HOLD_OUT_SDCU_XSTOP = 16 ;
+static const uint8_t P9N2_EX_L2_ISU_REG2_HOLD_OUT_WAT_INJECT_INT_RECOV = 17 ;
+
+static const uint8_t P9N2_C_ISU_REG2_HOLD_OUT_SDCX_SDCO_T2_HEIR_CHKSTOP_HOLD_OUT = 0 ;
+static const uint8_t P9N2_C_ISU_REG2_HOLD_OUT_SDCX_SDCO_T2_HSRR1_CHKSTOP_HOLD_OUT = 1 ;
+static const uint8_t P9N2_C_ISU_REG2_HOLD_OUT_SDCX_SDCO_T2_MSR_CHKSTOP_HOLD_OUT = 2 ;
+static const uint8_t P9N2_C_ISU_REG2_HOLD_OUT_SDCX_SDCO_T2_SRR1_CHKSTOP_HOLD_OUT = 3 ;
+static const uint8_t P9N2_C_ISU_REG2_HOLD_OUT_SDCX_SDCO_T2_VRSAVE_BKUP_CHKSTOP_HOLD_OUT = 4 ;
+static const uint8_t P9N2_C_ISU_REG2_HOLD_OUT_SDCX_SDCO_T2_VRSAVE_CHKSTOP_HOLD_OUT = 5 ;
+static const uint8_t P9N2_C_ISU_REG2_HOLD_OUT_SDCX_SDCO_T2_FSCR_CHKSTOP_HOLD_OUT = 6 ;
+static const uint8_t P9N2_C_ISU_REG2_HOLD_OUT_SDCX_SDCO_T2_HFSCR_CHKSTOP_HOLD_OUT = 7 ;
+static const uint8_t P9N2_C_ISU_REG2_HOLD_OUT_SDCX_SDCO_T2_TEXASR_CHKSTOP_HOLD_OUT = 8 ;
+static const uint8_t P9N2_C_ISU_REG2_HOLD_OUT_SDCX_SDCO_T2_BESCR_CHKSTOP_HOLD_OUT = 9 ;
+static const uint8_t P9N2_C_ISU_REG2_HOLD_OUT_SDCX_SDCU_T2_MCHK_AND_ME_EQ_0_HOLD_OUT = 12 ;
+static const uint8_t P9N2_C_ISU_REG2_HOLD_OUT_WAT_INJECT_INT = 13 ;
+static const uint8_t P9N2_C_ISU_REG2_HOLD_OUT_SDCA_RCOV = 14 ;
+static const uint8_t P9N2_C_ISU_REG2_HOLD_OUT_SDCU_RAM_XSTOP = 15 ;
+static const uint8_t P9N2_C_ISU_REG2_HOLD_OUT_SDCU_XSTOP = 16 ;
+static const uint8_t P9N2_C_ISU_REG2_HOLD_OUT_WAT_INJECT_INT_RECOV = 17 ;
+
+static const uint8_t P9N2_EX_L2_ISU_REG3_HOLD_OUT_SDCX_SDCO_T3_HEIR_CHKSTOP_HOLD_OUT = 0 ;
+static const uint8_t P9N2_EX_L2_ISU_REG3_HOLD_OUT_SDCX_SDCO_T3_HSRR1_CHKSTOP_HOLD_OUT = 1 ;
+static const uint8_t P9N2_EX_L2_ISU_REG3_HOLD_OUT_SDCX_SDCO_T3_MSR_CHKSTOP_HOLD_OUT = 2 ;
+static const uint8_t P9N2_EX_L2_ISU_REG3_HOLD_OUT_SDCX_SDCO_T3_SRR1_CHKSTOP_HOLD_OUT = 3 ;
+static const uint8_t P9N2_EX_L2_ISU_REG3_HOLD_OUT_SDCX_SDCO_T3_VRSAVE_BKUP_CHKSTOP_HOLD_OUT = 4 ;
+static const uint8_t P9N2_EX_L2_ISU_REG3_HOLD_OUT_SDCX_SDCO_T3_VRSAVE_CHKSTOP_HOLD_OUT = 5 ;
+static const uint8_t P9N2_EX_L2_ISU_REG3_HOLD_OUT_SDCX_SDCO_T3_FSCR_CHKSTOP_HOLD_OUT = 6 ;
+static const uint8_t P9N2_EX_L2_ISU_REG3_HOLD_OUT_SDCX_SDCO_T3_HFSCR_CHKSTOP_HOLD_OUT = 7 ;
+static const uint8_t P9N2_EX_L2_ISU_REG3_HOLD_OUT_SDCX_SDCO_T3_TEXASR_CHKSTOP_HOLD_OUT = 8 ;
+static const uint8_t P9N2_EX_L2_ISU_REG3_HOLD_OUT_SDCX_SDCO_T3_BESCR_CHKSTOP_HOLD_OUT = 9 ;
+static const uint8_t P9N2_EX_L2_ISU_REG3_HOLD_OUT_SDCX_SDCU_T3_MCHK_AND_ME_EQ_0_HOLD_OUT = 12 ;
+static const uint8_t P9N2_EX_L2_ISU_REG3_HOLD_OUT_SDCV_T0_FLUSH_XSTOP = 13 ;
+static const uint8_t P9N2_EX_L2_ISU_REG3_HOLD_OUT_SDCV_T1_FLUSH_XSTOP = 14 ;
+static const uint8_t P9N2_EX_L2_ISU_REG3_HOLD_OUT_SDCV_T2_FLUSH_XSTOP = 15 ;
+static const uint8_t P9N2_EX_L2_ISU_REG3_HOLD_OUT_SDCV_T3_FLUSH_XSTOP = 16 ;
+static const uint8_t P9N2_EX_L2_ISU_REG3_HOLD_OUT_SDKSMRF_SS0_1B = 17 ;
+
+static const uint8_t P9N2_C_ISU_REG3_HOLD_OUT_SDCX_SDCO_T3_HEIR_CHKSTOP_HOLD_OUT = 0 ;
+static const uint8_t P9N2_C_ISU_REG3_HOLD_OUT_SDCX_SDCO_T3_HSRR1_CHKSTOP_HOLD_OUT = 1 ;
+static const uint8_t P9N2_C_ISU_REG3_HOLD_OUT_SDCX_SDCO_T3_MSR_CHKSTOP_HOLD_OUT = 2 ;
+static const uint8_t P9N2_C_ISU_REG3_HOLD_OUT_SDCX_SDCO_T3_SRR1_CHKSTOP_HOLD_OUT = 3 ;
+static const uint8_t P9N2_C_ISU_REG3_HOLD_OUT_SDCX_SDCO_T3_VRSAVE_BKUP_CHKSTOP_HOLD_OUT = 4 ;
+static const uint8_t P9N2_C_ISU_REG3_HOLD_OUT_SDCX_SDCO_T3_VRSAVE_CHKSTOP_HOLD_OUT = 5 ;
+static const uint8_t P9N2_C_ISU_REG3_HOLD_OUT_SDCX_SDCO_T3_FSCR_CHKSTOP_HOLD_OUT = 6 ;
+static const uint8_t P9N2_C_ISU_REG3_HOLD_OUT_SDCX_SDCO_T3_HFSCR_CHKSTOP_HOLD_OUT = 7 ;
+static const uint8_t P9N2_C_ISU_REG3_HOLD_OUT_SDCX_SDCO_T3_TEXASR_CHKSTOP_HOLD_OUT = 8 ;
+static const uint8_t P9N2_C_ISU_REG3_HOLD_OUT_SDCX_SDCO_T3_BESCR_CHKSTOP_HOLD_OUT = 9 ;
+static const uint8_t P9N2_C_ISU_REG3_HOLD_OUT_SDCX_SDCU_T3_MCHK_AND_ME_EQ_0_HOLD_OUT = 12 ;
+static const uint8_t P9N2_C_ISU_REG3_HOLD_OUT_SDCV_T0_FLUSH_XSTOP = 13 ;
+static const uint8_t P9N2_C_ISU_REG3_HOLD_OUT_SDCV_T1_FLUSH_XSTOP = 14 ;
+static const uint8_t P9N2_C_ISU_REG3_HOLD_OUT_SDCV_T2_FLUSH_XSTOP = 15 ;
+static const uint8_t P9N2_C_ISU_REG3_HOLD_OUT_SDCV_T3_FLUSH_XSTOP = 16 ;
+static const uint8_t P9N2_C_ISU_REG3_HOLD_OUT_SDKSMRF_SS0_1B = 17 ;
+
+static const uint8_t P9N2_EX_L2_ISU_REG4_HOLD_OUT_SDKSMRF_SS1_1B = 0 ;
+static const uint8_t P9N2_EX_L2_ISU_REG4_HOLD_OUT_SDKSMRF_SS0_2B_XSTOP = 1 ;
+static const uint8_t P9N2_EX_L2_ISU_REG4_HOLD_OUT_SDKSMRF_SS1_2B_XSTOP = 2 ;
+static const uint8_t P9N2_EX_L2_ISU_REG4_HOLD_OUT_SDCXC_ERR_RPT = 3 ;
+static const uint8_t P9N2_EX_L2_ISU_REG4_HOLD_OUT_SDCC_T0_CRITICAL_IS_XSTOP = 4 ;
+static const uint8_t P9N2_EX_L2_ISU_REG4_HOLD_OUT_SDCC_T1_CRITICAL_IS_XSTOP = 5 ;
+static const uint8_t P9N2_EX_L2_ISU_REG4_HOLD_OUT_SDCC_T2_CRITICAL_IS_XSTOP = 6 ;
+static const uint8_t P9N2_EX_L2_ISU_REG4_HOLD_OUT_SDCC_T3_CRITICAL_IS_XSTOP = 7 ;
+static const uint8_t P9N2_EX_L2_ISU_REG4_HOLD_OUT_GND = 8 ;
+static const uint8_t P9N2_EX_L2_ISU_REG4_HOLD_OUT_GND_LEN = 10 ;
+
+static const uint8_t P9N2_C_ISU_REG4_HOLD_OUT_SDKSMRF_SS1_1B = 0 ;
+static const uint8_t P9N2_C_ISU_REG4_HOLD_OUT_SDKSMRF_SS0_2B_XSTOP = 1 ;
+static const uint8_t P9N2_C_ISU_REG4_HOLD_OUT_SDKSMRF_SS1_2B_XSTOP = 2 ;
+static const uint8_t P9N2_C_ISU_REG4_HOLD_OUT_SDCXC_ERR_RPT = 3 ;
+static const uint8_t P9N2_C_ISU_REG4_HOLD_OUT_SDCC_T0_CRITICAL_IS_XSTOP = 4 ;
+static const uint8_t P9N2_C_ISU_REG4_HOLD_OUT_SDCC_T1_CRITICAL_IS_XSTOP = 5 ;
+static const uint8_t P9N2_C_ISU_REG4_HOLD_OUT_SDCC_T2_CRITICAL_IS_XSTOP = 6 ;
+static const uint8_t P9N2_C_ISU_REG4_HOLD_OUT_SDCC_T3_CRITICAL_IS_XSTOP = 7 ;
+static const uint8_t P9N2_C_ISU_REG4_HOLD_OUT_GND = 8 ;
+static const uint8_t P9N2_C_ISU_REG4_HOLD_OUT_GND_LEN = 10 ;
+
+static const uint8_t P9N2_EX_L2_ISU_REG5_HOLD_OUT_GND = 0 ;
+static const uint8_t P9N2_EX_L2_ISU_REG5_HOLD_OUT_GND_LEN = 18 ;
+
+static const uint8_t P9N2_C_ISU_REG5_HOLD_OUT_GND = 0 ;
+static const uint8_t P9N2_C_ISU_REG5_HOLD_OUT_GND_LEN = 18 ;
+
+static const uint8_t P9N2_EQ_L3_ERR_RPT0_REG_L3SDRTL0_BAD_HPC = 0 ;
+static const uint8_t P9N2_EQ_L3_ERR_RPT0_REG_L3SDRTL1_BAD_HPC = 1 ;
+static const uint8_t P9N2_EQ_L3_ERR_RPT0_REG_L3CORTR_NO_LCO_TGTS = 2 ;
+static const uint8_t P9N2_EQ_L3_ERR_RPT0_REG_SN0_RCMD_TTAG_P = 3 ;
+static const uint8_t P9N2_EQ_L3_ERR_RPT0_REG_SN1_RCMD_TTAG_P = 4 ;
+static const uint8_t P9N2_EQ_L3_ERR_RPT0_REG_SN0_RCMD_ADDR_P = 5 ;
+static const uint8_t P9N2_EQ_L3_ERR_RPT0_REG_SN1_RCMD_ADDR_P = 6 ;
+static const uint8_t P9N2_EQ_L3_ERR_RPT0_REG_SN0_CRESP_TTAG_P = 7 ;
+static const uint8_t P9N2_EQ_L3_ERR_RPT0_REG_SN1_CRESP_TTAG_P = 8 ;
+static const uint8_t P9N2_EQ_L3_ERR_RPT0_REG_SN0_CRESP_ATAG_P = 9 ;
+static const uint8_t P9N2_EQ_L3_ERR_RPT0_REG_SN1_CRESP_ATAG_P = 10 ;
+static const uint8_t P9N2_EQ_L3_ERR_RPT0_REG_DATA_RTAG_P = 11 ;
+static const uint8_t P9N2_EQ_L3_ERR_RPT0_REG_PF_UNSOLICITED_CRESP = 12 ;
+static const uint8_t P9N2_EQ_L3_ERR_RPT0_REG_SN_UNSOLICITED_CRESP = 13 ;
+static const uint8_t P9N2_EQ_L3_ERR_RPT0_REG_CO_UNSOLICITED_CRESP = 14 ;
+static const uint8_t P9N2_EQ_L3_ERR_RPT0_REG_MC_FP_MATE_CMD_ERR2 = 15 ;
+static const uint8_t P9N2_EQ_L3_ERR_RPT0_REG_MC_FP_MATE_CMD_ERR3 = 16 ;
+static const uint8_t P9N2_EQ_L3_ERR_RPT0_REG_SPARE_17 = 17 ;
+static const uint8_t P9N2_EQ_L3_ERR_RPT0_REG_WI_UNSOLICITED_DATA = 18 ;
+static const uint8_t P9N2_EQ_L3_ERR_RPT0_REG_PF_UNSOLICITED_DATA = 19 ;
+static const uint8_t P9N2_EQ_L3_ERR_RPT0_REG_TM_CAM = 20 ;
+static const uint8_t P9N2_EQ_L3_ERR_RPT0_REG_TM_CAM_LEN = 4 ;
+static const uint8_t P9N2_EQ_L3_ERR_RPT0_REG_COFSM_ADDR = 24 ;
+static const uint8_t P9N2_EQ_L3_ERR_RPT0_REG_SNFSM_ADDR = 25 ;
+static const uint8_t P9N2_EQ_L3_ERR_RPT0_REG_L3SDRTL0_CACHE_INHIBIT = 26 ;
+static const uint8_t P9N2_EQ_L3_ERR_RPT0_REG_L3SDRTL1_CACHE_INHIBIT = 27 ;
+static const uint8_t P9N2_EQ_L3_ERR_RPT0_REG_L3SDRTL2_CACHE_INHIBIT = 28 ;
+static const uint8_t P9N2_EQ_L3_ERR_RPT0_REG_L3SDRTL3_CACHE_INHIBIT = 29 ;
+static const uint8_t P9N2_EQ_L3_ERR_RPT0_REG_L3SDRTL2_BAD_HPC = 30 ;
+static const uint8_t P9N2_EQ_L3_ERR_RPT0_REG_L3SDRTL3_BAD_HPC = 31 ;
+static const uint8_t P9N2_EQ_L3_ERR_RPT0_REG_SN_MACHINE_HANG = 32 ;
+static const uint8_t P9N2_EQ_L3_ERR_RPT0_REG_RD_MACHINE_HANG = 33 ;
+static const uint8_t P9N2_EQ_L3_ERR_RPT0_REG_CI_MACHINE_HANG = 34 ;
+static const uint8_t P9N2_EQ_L3_ERR_RPT0_REG_CO_MACHINE_HANG = 35 ;
+
+static const uint8_t P9N2_EX_L3_L3_ERR_RPT0_REG_L3SDRTL0_BAD_HPC = 0 ;
+static const uint8_t P9N2_EX_L3_L3_ERR_RPT0_REG_L3SDRTL1_BAD_HPC = 1 ;
+static const uint8_t P9N2_EX_L3_L3_ERR_RPT0_REG_L3CORTR_NO_LCO_TGTS = 2 ;
+static const uint8_t P9N2_EX_L3_L3_ERR_RPT0_REG_SN0_RCMD_TTAG_P = 3 ;
+static const uint8_t P9N2_EX_L3_L3_ERR_RPT0_REG_SN1_RCMD_TTAG_P = 4 ;
+static const uint8_t P9N2_EX_L3_L3_ERR_RPT0_REG_SN0_RCMD_ADDR_P = 5 ;
+static const uint8_t P9N2_EX_L3_L3_ERR_RPT0_REG_SN1_RCMD_ADDR_P = 6 ;
+static const uint8_t P9N2_EX_L3_L3_ERR_RPT0_REG_SN0_CRESP_TTAG_P = 7 ;
+static const uint8_t P9N2_EX_L3_L3_ERR_RPT0_REG_SN1_CRESP_TTAG_P = 8 ;
+static const uint8_t P9N2_EX_L3_L3_ERR_RPT0_REG_SN0_CRESP_ATAG_P = 9 ;
+static const uint8_t P9N2_EX_L3_L3_ERR_RPT0_REG_SN1_CRESP_ATAG_P = 10 ;
+static const uint8_t P9N2_EX_L3_L3_ERR_RPT0_REG_DATA_RTAG_P = 11 ;
+static const uint8_t P9N2_EX_L3_L3_ERR_RPT0_REG_PF_UNSOLICITED_CRESP = 12 ;
+static const uint8_t P9N2_EX_L3_L3_ERR_RPT0_REG_SN_UNSOLICITED_CRESP = 13 ;
+static const uint8_t P9N2_EX_L3_L3_ERR_RPT0_REG_CO_UNSOLICITED_CRESP = 14 ;
+static const uint8_t P9N2_EX_L3_L3_ERR_RPT0_REG_MC_FP_MATE_CMD_ERR2 = 15 ;
+static const uint8_t P9N2_EX_L3_L3_ERR_RPT0_REG_MC_FP_MATE_CMD_ERR3 = 16 ;
+static const uint8_t P9N2_EX_L3_L3_ERR_RPT0_REG_SPARE_17 = 17 ;
+static const uint8_t P9N2_EX_L3_L3_ERR_RPT0_REG_WI_UNSOLICITED_DATA = 18 ;
+static const uint8_t P9N2_EX_L3_L3_ERR_RPT0_REG_PF_UNSOLICITED_DATA = 19 ;
+static const uint8_t P9N2_EX_L3_L3_ERR_RPT0_REG_TM_CAM = 20 ;
+static const uint8_t P9N2_EX_L3_L3_ERR_RPT0_REG_TM_CAM_LEN = 4 ;
+static const uint8_t P9N2_EX_L3_L3_ERR_RPT0_REG_COFSM_ADDR = 24 ;
+static const uint8_t P9N2_EX_L3_L3_ERR_RPT0_REG_SNFSM_ADDR = 25 ;
+static const uint8_t P9N2_EX_L3_L3_ERR_RPT0_REG_L3SDRTL0_CACHE_INHIBIT = 26 ;
+static const uint8_t P9N2_EX_L3_L3_ERR_RPT0_REG_L3SDRTL1_CACHE_INHIBIT = 27 ;
+static const uint8_t P9N2_EX_L3_L3_ERR_RPT0_REG_L3SDRTL2_CACHE_INHIBIT = 28 ;
+static const uint8_t P9N2_EX_L3_L3_ERR_RPT0_REG_L3SDRTL3_CACHE_INHIBIT = 29 ;
+static const uint8_t P9N2_EX_L3_L3_ERR_RPT0_REG_L3SDRTL2_BAD_HPC = 30 ;
+static const uint8_t P9N2_EX_L3_L3_ERR_RPT0_REG_L3SDRTL3_BAD_HPC = 31 ;
+static const uint8_t P9N2_EX_L3_L3_ERR_RPT0_REG_SN_MACHINE_HANG = 32 ;
+static const uint8_t P9N2_EX_L3_L3_ERR_RPT0_REG_RD_MACHINE_HANG = 33 ;
+static const uint8_t P9N2_EX_L3_L3_ERR_RPT0_REG_CI_MACHINE_HANG = 34 ;
+static const uint8_t P9N2_EX_L3_L3_ERR_RPT0_REG_CO_MACHINE_HANG = 35 ;
+
+static const uint8_t P9N2_EQ_L3_ERR_RPT1_REG_PF_MACHINE_HANG = 0 ;
+static const uint8_t P9N2_EQ_L3_ERR_RPT1_REG_WI_MACHINE_HANG = 1 ;
+static const uint8_t P9N2_EQ_L3_ERR_RPT1_REG_L3L2CTL_RD_OVERRUN_CK = 2 ;
+static const uint8_t P9N2_EQ_L3_ERR_RPT1_REG_L3L2CTL_PF_OVERRUN_CK = 3 ;
+static const uint8_t P9N2_EQ_L3_ERR_RPT1_REG_L3CICTL_CI_OVERRUN_CK = 4 ;
+static const uint8_t P9N2_EQ_L3_ERR_RPT1_REG_L3XMEMA0_DW_DIR_HIT = 5 ;
+static const uint8_t P9N2_EQ_L3_ERR_RPT1_REG_L3XMEMA1_DW_DIR_HIT = 6 ;
+static const uint8_t P9N2_EQ_L3_ERR_RPT1_REG_L3XMEMA0_CRW_DIR_HIT = 7 ;
+static const uint8_t P9N2_EQ_L3_ERR_RPT1_REG_L3XMEMA1_CRW_DIR_HIT = 8 ;
+static const uint8_t P9N2_EQ_L3_ERR_RPT1_REG_PBEXCA0_CMD_REQ_ERR0 = 9 ;
+static const uint8_t P9N2_EQ_L3_ERR_RPT1_REG_PBEXCA0_CMD_REQ_ERR1 = 10 ;
+static const uint8_t P9N2_EQ_L3_ERR_RPT1_REG_PBEXCA0_CMD_REQ_ERR2 = 11 ;
+static const uint8_t P9N2_EQ_L3_ERR_RPT1_REG_PBEXCA1_CMD_REQ_ERR0 = 12 ;
+static const uint8_t P9N2_EQ_L3_ERR_RPT1_REG_PBEXCA1_CMD_REQ_ERR1 = 13 ;
+static const uint8_t P9N2_EQ_L3_ERR_RPT1_REG_PBEXCA1_CMD_REQ_ERR2 = 14 ;
+static const uint8_t P9N2_EQ_L3_ERR_RPT1_REG_MC_FP_MATE_CMD_ERR0 = 15 ;
+static const uint8_t P9N2_EQ_L3_ERR_RPT1_REG_MC_FP_MATE_CMD_ERR1 = 16 ;
+static const uint8_t P9N2_EQ_L3_ERR_RPT1_REG_L3PBEXCA0_OVERFLOW = 17 ;
+static const uint8_t P9N2_EQ_L3_ERR_RPT1_REG_L3PBEXCA1_OVERFLOW = 18 ;
+static const uint8_t P9N2_EQ_L3_ERR_RPT1_REG_L3PBEXCA0_UNDERFLOW = 19 ;
+static const uint8_t P9N2_EQ_L3_ERR_RPT1_REG_L3PBEXCA1_UNDERFLOW = 20 ;
+static const uint8_t P9N2_EQ_L3_ERR_RPT1_REG_PF_MACHINE_W4DT_HANG = 21 ;
+static const uint8_t P9N2_EQ_L3_ERR_RPT1_REG_WI_MACHINE_W4DT_HANG = 22 ;
+static const uint8_t P9N2_EQ_L3_ERR_RPT1_REG_CO_CRESP_ACK_DEAD = 23 ;
+static const uint8_t P9N2_EQ_L3_ERR_RPT1_REG_SN_CRESP_ACK_DEAD = 24 ;
+static const uint8_t P9N2_EQ_L3_ERR_RPT1_REG_SN2_RCMD_TTAG_P = 25 ;
+static const uint8_t P9N2_EQ_L3_ERR_RPT1_REG_SN3_RCMD_TTAG_P = 26 ;
+static const uint8_t P9N2_EQ_L3_ERR_RPT1_REG_SN2_RCMD_ADDR_P = 27 ;
+static const uint8_t P9N2_EQ_L3_ERR_RPT1_REG_SN3_RCMD_ADDR_P = 28 ;
+static const uint8_t P9N2_EQ_L3_ERR_RPT1_REG_SN2_CRESP_TTAG_P = 29 ;
+static const uint8_t P9N2_EQ_L3_ERR_RPT1_REG_SN3_CRESP_TTAG_P = 30 ;
+static const uint8_t P9N2_EQ_L3_ERR_RPT1_REG_SN2_CRESP_ATAG_P = 31 ;
+static const uint8_t P9N2_EQ_L3_ERR_RPT1_REG_SN3_CRESP_ATAG_P = 32 ;
+
+static const uint8_t P9N2_EX_L3_L3_ERR_RPT1_REG_PF_MACHINE_HANG = 0 ;
+static const uint8_t P9N2_EX_L3_L3_ERR_RPT1_REG_WI_MACHINE_HANG = 1 ;
+static const uint8_t P9N2_EX_L3_L3_ERR_RPT1_REG_L3L2CTL_RD_OVERRUN_CK = 2 ;
+static const uint8_t P9N2_EX_L3_L3_ERR_RPT1_REG_L3L2CTL_PF_OVERRUN_CK = 3 ;
+static const uint8_t P9N2_EX_L3_L3_ERR_RPT1_REG_L3CICTL_CI_OVERRUN_CK = 4 ;
+static const uint8_t P9N2_EX_L3_L3_ERR_RPT1_REG_L3XMEMA0_DW_DIR_HIT = 5 ;
+static const uint8_t P9N2_EX_L3_L3_ERR_RPT1_REG_L3XMEMA1_DW_DIR_HIT = 6 ;
+static const uint8_t P9N2_EX_L3_L3_ERR_RPT1_REG_L3XMEMA0_CRW_DIR_HIT = 7 ;
+static const uint8_t P9N2_EX_L3_L3_ERR_RPT1_REG_L3XMEMA1_CRW_DIR_HIT = 8 ;
+static const uint8_t P9N2_EX_L3_L3_ERR_RPT1_REG_PBEXCA0_CMD_REQ_ERR0 = 9 ;
+static const uint8_t P9N2_EX_L3_L3_ERR_RPT1_REG_PBEXCA0_CMD_REQ_ERR1 = 10 ;
+static const uint8_t P9N2_EX_L3_L3_ERR_RPT1_REG_PBEXCA0_CMD_REQ_ERR2 = 11 ;
+static const uint8_t P9N2_EX_L3_L3_ERR_RPT1_REG_PBEXCA1_CMD_REQ_ERR0 = 12 ;
+static const uint8_t P9N2_EX_L3_L3_ERR_RPT1_REG_PBEXCA1_CMD_REQ_ERR1 = 13 ;
+static const uint8_t P9N2_EX_L3_L3_ERR_RPT1_REG_PBEXCA1_CMD_REQ_ERR2 = 14 ;
+static const uint8_t P9N2_EX_L3_L3_ERR_RPT1_REG_MC_FP_MATE_CMD_ERR0 = 15 ;
+static const uint8_t P9N2_EX_L3_L3_ERR_RPT1_REG_MC_FP_MATE_CMD_ERR1 = 16 ;
+static const uint8_t P9N2_EX_L3_L3_ERR_RPT1_REG_L3PBEXCA0_OVERFLOW = 17 ;
+static const uint8_t P9N2_EX_L3_L3_ERR_RPT1_REG_L3PBEXCA1_OVERFLOW = 18 ;
+static const uint8_t P9N2_EX_L3_L3_ERR_RPT1_REG_L3PBEXCA0_UNDERFLOW = 19 ;
+static const uint8_t P9N2_EX_L3_L3_ERR_RPT1_REG_L3PBEXCA1_UNDERFLOW = 20 ;
+static const uint8_t P9N2_EX_L3_L3_ERR_RPT1_REG_PF_MACHINE_W4DT_HANG = 21 ;
+static const uint8_t P9N2_EX_L3_L3_ERR_RPT1_REG_WI_MACHINE_W4DT_HANG = 22 ;
+static const uint8_t P9N2_EX_L3_L3_ERR_RPT1_REG_CO_CRESP_ACK_DEAD = 23 ;
+static const uint8_t P9N2_EX_L3_L3_ERR_RPT1_REG_SN_CRESP_ACK_DEAD = 24 ;
+static const uint8_t P9N2_EX_L3_L3_ERR_RPT1_REG_SN2_RCMD_TTAG_P = 25 ;
+static const uint8_t P9N2_EX_L3_L3_ERR_RPT1_REG_SN3_RCMD_TTAG_P = 26 ;
+static const uint8_t P9N2_EX_L3_L3_ERR_RPT1_REG_SN2_RCMD_ADDR_P = 27 ;
+static const uint8_t P9N2_EX_L3_L3_ERR_RPT1_REG_SN3_RCMD_ADDR_P = 28 ;
+static const uint8_t P9N2_EX_L3_L3_ERR_RPT1_REG_SN2_CRESP_TTAG_P = 29 ;
+static const uint8_t P9N2_EX_L3_L3_ERR_RPT1_REG_SN3_CRESP_TTAG_P = 30 ;
+static const uint8_t P9N2_EX_L3_L3_ERR_RPT1_REG_SN2_CRESP_ATAG_P = 31 ;
+static const uint8_t P9N2_EX_L3_L3_ERR_RPT1_REG_SN3_CRESP_ATAG_P = 32 ;
+
+static const uint8_t P9N2_EQ_L3_RD_EPSILON_CFG_REG_WT4CR_TIER0_EPS_VAL = 0 ;
+static const uint8_t P9N2_EQ_L3_RD_EPSILON_CFG_REG_WT4CR_TIER0_EPS_VAL_LEN = 12 ;
+static const uint8_t P9N2_EQ_L3_RD_EPSILON_CFG_REG_WT4CR_TIER1_EPS_VAL = 12 ;
+static const uint8_t P9N2_EQ_L3_RD_EPSILON_CFG_REG_WT4CR_TIER1_EPS_VAL_LEN = 12 ;
+static const uint8_t P9N2_EQ_L3_RD_EPSILON_CFG_REG_WT4CR_TIER2_EPS_VAL = 24 ;
+static const uint8_t P9N2_EQ_L3_RD_EPSILON_CFG_REG_WT4CR_TIER2_EPS_VAL_LEN = 12 ;
+static const uint8_t P9N2_EQ_L3_RD_EPSILON_CFG_REG_EPS_MODE_SEL = 36 ;
+
+static const uint8_t P9N2_EX_L3_RD_EPSILON_CFG_REG_WT4CR_TIER0_EPS_VAL = 0 ;
+static const uint8_t P9N2_EX_L3_RD_EPSILON_CFG_REG_WT4CR_TIER0_EPS_VAL_LEN = 12 ;
+static const uint8_t P9N2_EX_L3_RD_EPSILON_CFG_REG_WT4CR_TIER1_EPS_VAL = 12 ;
+static const uint8_t P9N2_EX_L3_RD_EPSILON_CFG_REG_WT4CR_TIER1_EPS_VAL_LEN = 12 ;
+static const uint8_t P9N2_EX_L3_RD_EPSILON_CFG_REG_WT4CR_TIER2_EPS_VAL = 24 ;
+static const uint8_t P9N2_EX_L3_RD_EPSILON_CFG_REG_WT4CR_TIER2_EPS_VAL_LEN = 12 ;
+static const uint8_t P9N2_EX_L3_RD_EPSILON_CFG_REG_EPS_MODE_SEL = 36 ;
+
+static const uint8_t P9N2_EQ_L3_RTIM_PERIOD_MONITOR_MON = 0 ;
+static const uint8_t P9N2_EQ_L3_RTIM_PERIOD_MONITOR_MON_LEN = 8 ;
+
+static const uint8_t P9N2_EX_L3_L3_RTIM_PERIOD_MONITOR_MON = 0 ;
+static const uint8_t P9N2_EX_L3_L3_RTIM_PERIOD_MONITOR_MON_LEN = 8 ;
+
+static const uint8_t P9N2_EQ_L3_WR_EPSILON_CFG_REG_WT4CR_TIER1_EPS_VAL = 0 ;
+static const uint8_t P9N2_EQ_L3_WR_EPSILON_CFG_REG_WT4CR_TIER1_EPS_VAL_LEN = 12 ;
+static const uint8_t P9N2_EQ_L3_WR_EPSILON_CFG_REG_WT4CR_TIER2_EPS_VAL = 12 ;
+static const uint8_t P9N2_EQ_L3_WR_EPSILON_CFG_REG_WT4CR_TIER2_EPS_VAL_LEN = 12 ;
+static const uint8_t P9N2_EQ_L3_WR_EPSILON_CFG_REG_EN_WT4CR_EPS_ON_LCO = 24 ;
+static const uint8_t P9N2_EQ_L3_WR_EPSILON_CFG_REG_EN_WT4CR_EXTENDED_MODE = 25 ;
+static const uint8_t P9N2_EQ_L3_WR_EPSILON_CFG_REG_EPS_STEP_MODE = 26 ;
+static const uint8_t P9N2_EQ_L3_WR_EPSILON_CFG_REG_EPS_STEP_MODE_LEN = 4 ;
+static const uint8_t P9N2_EQ_L3_WR_EPSILON_CFG_REG_EPS_DIVIDER_MODE = 30 ;
+static const uint8_t P9N2_EQ_L3_WR_EPSILON_CFG_REG_EPS_DIVIDER_MODE_LEN = 4 ;
+static const uint8_t P9N2_EQ_L3_WR_EPSILON_CFG_REG_EPS_CNT_USE_DIVIDER_EN = 34 ;
+
+static const uint8_t P9N2_EX_L3_L3_WR_EPSILON_CFG_REG_WT4CR_TIER1_EPS_VAL = 0 ;
+static const uint8_t P9N2_EX_L3_L3_WR_EPSILON_CFG_REG_WT4CR_TIER1_EPS_VAL_LEN = 12 ;
+static const uint8_t P9N2_EX_L3_L3_WR_EPSILON_CFG_REG_WT4CR_TIER2_EPS_VAL = 12 ;
+static const uint8_t P9N2_EX_L3_L3_WR_EPSILON_CFG_REG_WT4CR_TIER2_EPS_VAL_LEN = 12 ;
+static const uint8_t P9N2_EX_L3_L3_WR_EPSILON_CFG_REG_EN_WT4CR_EPS_ON_LCO = 24 ;
+static const uint8_t P9N2_EX_L3_L3_WR_EPSILON_CFG_REG_EN_WT4CR_EXTENDED_MODE = 25 ;
+static const uint8_t P9N2_EX_L3_L3_WR_EPSILON_CFG_REG_EPS_STEP_MODE = 26 ;
+static const uint8_t P9N2_EX_L3_L3_WR_EPSILON_CFG_REG_EPS_STEP_MODE_LEN = 4 ;
+static const uint8_t P9N2_EX_L3_L3_WR_EPSILON_CFG_REG_EPS_DIVIDER_MODE = 30 ;
+static const uint8_t P9N2_EX_L3_L3_WR_EPSILON_CFG_REG_EPS_DIVIDER_MODE_LEN = 4 ;
+static const uint8_t P9N2_EX_L3_L3_WR_EPSILON_CFG_REG_EPS_CNT_USE_DIVIDER_EN = 34 ;
+
+static const uint8_t P9N2_EQ_LINEDEL_TRIG_REG_TRIG = 0 ;
+static const uint8_t P9N2_EQ_LINEDEL_TRIG_REG_DONE = 1 ;
+static const uint8_t P9N2_EQ_LINEDEL_TRIG_REG_SPARE = 2 ;
+static const uint8_t P9N2_EQ_LINEDEL_TRIG_REG_SPARE_LEN = 2 ;
+
+static const uint8_t P9N2_EX_L2_LINEDEL_TRIG_REG_TRIG = 0 ;
+static const uint8_t P9N2_EX_L2_LINEDEL_TRIG_REG_DONE = 1 ;
+static const uint8_t P9N2_EX_L2_LINEDEL_TRIG_REG_SPARE = 2 ;
+static const uint8_t P9N2_EX_L2_LINEDEL_TRIG_REG_SPARE_LEN = 2 ;
+
+static const uint8_t P9N2_EQ_LINE_DELETED_MEMBERS_REG_L3 = 0 ;
+static const uint8_t P9N2_EQ_LINE_DELETED_MEMBERS_REG_L3_LEN = 5 ;
+
+static const uint8_t P9N2_EX_L3_LINE_DELETED_MEMBERS_REG_L3 = 0 ;
+static const uint8_t P9N2_EX_L3_LINE_DELETED_MEMBERS_REG_L3_LEN = 5 ;
+
+static const uint8_t P9N2_EQ_LOCAL_FIR_IN0 = 0 ;
+static const uint8_t P9N2_EQ_LOCAL_FIR_IN1 = 1 ;
+static const uint8_t P9N2_EQ_LOCAL_FIR_IN2 = 2 ;
+static const uint8_t P9N2_EQ_LOCAL_FIR_IN3 = 3 ;
+static const uint8_t P9N2_EQ_LOCAL_FIR_IN4 = 4 ;
+static const uint8_t P9N2_EQ_LOCAL_FIR_IN5 = 5 ;
+static const uint8_t P9N2_EQ_LOCAL_FIR_IN6 = 6 ;
+static const uint8_t P9N2_EQ_LOCAL_FIR_IN7 = 7 ;
+static const uint8_t P9N2_EQ_LOCAL_FIR_IN8 = 8 ;
+static const uint8_t P9N2_EQ_LOCAL_FIR_IN9 = 9 ;
+static const uint8_t P9N2_EQ_LOCAL_FIR_IN10 = 10 ;
+static const uint8_t P9N2_EQ_LOCAL_FIR_IN11 = 11 ;
+static const uint8_t P9N2_EQ_LOCAL_FIR_IN12 = 12 ;
+static const uint8_t P9N2_EQ_LOCAL_FIR_IN13 = 13 ;
+static const uint8_t P9N2_EQ_LOCAL_FIR_IN14 = 14 ;
+static const uint8_t P9N2_EQ_LOCAL_FIR_IN15 = 15 ;
+static const uint8_t P9N2_EQ_LOCAL_FIR_IN16 = 16 ;
+static const uint8_t P9N2_EQ_LOCAL_FIR_IN17 = 17 ;
+static const uint8_t P9N2_EQ_LOCAL_FIR_IN18 = 18 ;
+static const uint8_t P9N2_EQ_LOCAL_FIR_IN19 = 19 ;
+static const uint8_t P9N2_EQ_LOCAL_FIR_IN20 = 20 ;
+static const uint8_t P9N2_EQ_LOCAL_FIR_IN21 = 21 ;
+static const uint8_t P9N2_EQ_LOCAL_FIR_IN22 = 22 ;
+static const uint8_t P9N2_EQ_LOCAL_FIR_IN23 = 23 ;
+static const uint8_t P9N2_EQ_LOCAL_FIR_IN24 = 24 ;
+static const uint8_t P9N2_EQ_LOCAL_FIR_IN25 = 25 ;
+static const uint8_t P9N2_EQ_LOCAL_FIR_IN26 = 26 ;
+static const uint8_t P9N2_EQ_LOCAL_FIR_IN27 = 27 ;
+static const uint8_t P9N2_EQ_LOCAL_FIR_IN28 = 28 ;
+static const uint8_t P9N2_EQ_LOCAL_FIR_IN29 = 29 ;
+static const uint8_t P9N2_EQ_LOCAL_FIR_IN30 = 30 ;
+static const uint8_t P9N2_EQ_LOCAL_FIR_IN31 = 31 ;
+static const uint8_t P9N2_EQ_LOCAL_FIR_IN32 = 32 ;
+static const uint8_t P9N2_EQ_LOCAL_FIR_IN33 = 33 ;
+static const uint8_t P9N2_EQ_LOCAL_FIR_IN34 = 34 ;
+static const uint8_t P9N2_EQ_LOCAL_FIR_IN35 = 35 ;
+static const uint8_t P9N2_EQ_LOCAL_FIR_IN36 = 36 ;
+static const uint8_t P9N2_EQ_LOCAL_FIR_IN37 = 37 ;
+static const uint8_t P9N2_EQ_LOCAL_FIR_IN38 = 38 ;
+static const uint8_t P9N2_EQ_LOCAL_FIR_IN39 = 39 ;
+static const uint8_t P9N2_EQ_LOCAL_FIR_IN40 = 40 ;
+static const uint8_t P9N2_EQ_LOCAL_FIR_IN41 = 41 ;
+
+static const uint8_t P9N2_EX_LOCAL_FIR_IN0 = 0 ;
+static const uint8_t P9N2_EX_LOCAL_FIR_IN1 = 1 ;
+static const uint8_t P9N2_EX_LOCAL_FIR_IN2 = 2 ;
+static const uint8_t P9N2_EX_LOCAL_FIR_IN3 = 3 ;
+static const uint8_t P9N2_EX_LOCAL_FIR_IN4 = 4 ;
+static const uint8_t P9N2_EX_LOCAL_FIR_IN5 = 5 ;
+static const uint8_t P9N2_EX_LOCAL_FIR_IN6 = 6 ;
+static const uint8_t P9N2_EX_LOCAL_FIR_IN7 = 7 ;
+static const uint8_t P9N2_EX_LOCAL_FIR_IN8 = 8 ;
+static const uint8_t P9N2_EX_LOCAL_FIR_IN9 = 9 ;
+static const uint8_t P9N2_EX_LOCAL_FIR_IN10 = 10 ;
+static const uint8_t P9N2_EX_LOCAL_FIR_IN11 = 11 ;
+static const uint8_t P9N2_EX_LOCAL_FIR_IN12 = 12 ;
+static const uint8_t P9N2_EX_LOCAL_FIR_IN13 = 13 ;
+static const uint8_t P9N2_EX_LOCAL_FIR_IN14 = 14 ;
+static const uint8_t P9N2_EX_LOCAL_FIR_IN15 = 15 ;
+static const uint8_t P9N2_EX_LOCAL_FIR_IN16 = 16 ;
+static const uint8_t P9N2_EX_LOCAL_FIR_IN17 = 17 ;
+static const uint8_t P9N2_EX_LOCAL_FIR_IN18 = 18 ;
+static const uint8_t P9N2_EX_LOCAL_FIR_IN19 = 19 ;
+static const uint8_t P9N2_EX_LOCAL_FIR_IN20 = 20 ;
+static const uint8_t P9N2_EX_LOCAL_FIR_IN21 = 21 ;
+static const uint8_t P9N2_EX_LOCAL_FIR_IN22 = 22 ;
+static const uint8_t P9N2_EX_LOCAL_FIR_IN23 = 23 ;
+static const uint8_t P9N2_EX_LOCAL_FIR_IN24 = 24 ;
+static const uint8_t P9N2_EX_LOCAL_FIR_IN25 = 25 ;
+static const uint8_t P9N2_EX_LOCAL_FIR_IN26 = 26 ;
+static const uint8_t P9N2_EX_LOCAL_FIR_IN27 = 27 ;
+static const uint8_t P9N2_EX_LOCAL_FIR_IN28 = 28 ;
+static const uint8_t P9N2_EX_LOCAL_FIR_IN29 = 29 ;
+static const uint8_t P9N2_EX_LOCAL_FIR_IN30 = 30 ;
+static const uint8_t P9N2_EX_LOCAL_FIR_IN31 = 31 ;
+static const uint8_t P9N2_EX_LOCAL_FIR_IN32 = 32 ;
+static const uint8_t P9N2_EX_LOCAL_FIR_IN33 = 33 ;
+static const uint8_t P9N2_EX_LOCAL_FIR_IN34 = 34 ;
+static const uint8_t P9N2_EX_LOCAL_FIR_IN35 = 35 ;
+static const uint8_t P9N2_EX_LOCAL_FIR_IN36 = 36 ;
+static const uint8_t P9N2_EX_LOCAL_FIR_IN37 = 37 ;
+static const uint8_t P9N2_EX_LOCAL_FIR_IN38 = 38 ;
+static const uint8_t P9N2_EX_LOCAL_FIR_IN39 = 39 ;
+static const uint8_t P9N2_EX_LOCAL_FIR_IN40 = 40 ;
+static const uint8_t P9N2_EX_LOCAL_FIR_IN41 = 41 ;
+
+static const uint8_t P9N2_C_LOCAL_FIR_IN0 = 0 ;
+static const uint8_t P9N2_C_LOCAL_FIR_IN1 = 1 ;
+static const uint8_t P9N2_C_LOCAL_FIR_IN2 = 2 ;
+static const uint8_t P9N2_C_LOCAL_FIR_IN3 = 3 ;
+static const uint8_t P9N2_C_LOCAL_FIR_IN4 = 4 ;
+static const uint8_t P9N2_C_LOCAL_FIR_IN5 = 5 ;
+static const uint8_t P9N2_C_LOCAL_FIR_IN6 = 6 ;
+static const uint8_t P9N2_C_LOCAL_FIR_IN7 = 7 ;
+static const uint8_t P9N2_C_LOCAL_FIR_IN8 = 8 ;
+static const uint8_t P9N2_C_LOCAL_FIR_IN9 = 9 ;
+static const uint8_t P9N2_C_LOCAL_FIR_IN10 = 10 ;
+static const uint8_t P9N2_C_LOCAL_FIR_IN11 = 11 ;
+static const uint8_t P9N2_C_LOCAL_FIR_IN12 = 12 ;
+static const uint8_t P9N2_C_LOCAL_FIR_IN13 = 13 ;
+static const uint8_t P9N2_C_LOCAL_FIR_IN14 = 14 ;
+static const uint8_t P9N2_C_LOCAL_FIR_IN15 = 15 ;
+static const uint8_t P9N2_C_LOCAL_FIR_IN16 = 16 ;
+static const uint8_t P9N2_C_LOCAL_FIR_IN17 = 17 ;
+static const uint8_t P9N2_C_LOCAL_FIR_IN18 = 18 ;
+static const uint8_t P9N2_C_LOCAL_FIR_IN19 = 19 ;
+static const uint8_t P9N2_C_LOCAL_FIR_IN20 = 20 ;
+static const uint8_t P9N2_C_LOCAL_FIR_IN21 = 21 ;
+static const uint8_t P9N2_C_LOCAL_FIR_IN22 = 22 ;
+static const uint8_t P9N2_C_LOCAL_FIR_IN23 = 23 ;
+static const uint8_t P9N2_C_LOCAL_FIR_IN24 = 24 ;
+static const uint8_t P9N2_C_LOCAL_FIR_IN25 = 25 ;
+static const uint8_t P9N2_C_LOCAL_FIR_IN26 = 26 ;
+static const uint8_t P9N2_C_LOCAL_FIR_IN27 = 27 ;
+static const uint8_t P9N2_C_LOCAL_FIR_IN28 = 28 ;
+static const uint8_t P9N2_C_LOCAL_FIR_IN29 = 29 ;
+static const uint8_t P9N2_C_LOCAL_FIR_IN30 = 30 ;
+static const uint8_t P9N2_C_LOCAL_FIR_IN31 = 31 ;
+static const uint8_t P9N2_C_LOCAL_FIR_IN32 = 32 ;
+static const uint8_t P9N2_C_LOCAL_FIR_IN33 = 33 ;
+static const uint8_t P9N2_C_LOCAL_FIR_IN34 = 34 ;
+static const uint8_t P9N2_C_LOCAL_FIR_IN35 = 35 ;
+static const uint8_t P9N2_C_LOCAL_FIR_IN36 = 36 ;
+static const uint8_t P9N2_C_LOCAL_FIR_IN37 = 37 ;
+static const uint8_t P9N2_C_LOCAL_FIR_IN38 = 38 ;
+static const uint8_t P9N2_C_LOCAL_FIR_IN39 = 39 ;
+static const uint8_t P9N2_C_LOCAL_FIR_IN40 = 40 ;
+static const uint8_t P9N2_C_LOCAL_FIR_IN41 = 41 ;
+
+static const uint8_t P9N2_EQ_LOCAL_FIR_ACTION0_IN = 0 ;
+static const uint8_t P9N2_EQ_LOCAL_FIR_ACTION0_IN_LEN = 42 ;
+
+static const uint8_t P9N2_EX_LOCAL_FIR_ACTION0_IN = 0 ;
+static const uint8_t P9N2_EX_LOCAL_FIR_ACTION0_IN_LEN = 42 ;
+
+static const uint8_t P9N2_C_LOCAL_FIR_ACTION0_IN = 0 ;
+static const uint8_t P9N2_C_LOCAL_FIR_ACTION0_IN_LEN = 42 ;
+
+static const uint8_t P9N2_EQ_LOCAL_FIR_ACTION1_IN = 0 ;
+static const uint8_t P9N2_EQ_LOCAL_FIR_ACTION1_IN_LEN = 42 ;
+
+static const uint8_t P9N2_EX_LOCAL_FIR_ACTION1_IN = 0 ;
+static const uint8_t P9N2_EX_LOCAL_FIR_ACTION1_IN_LEN = 42 ;
+
+static const uint8_t P9N2_C_LOCAL_FIR_ACTION1_IN = 0 ;
+static const uint8_t P9N2_C_LOCAL_FIR_ACTION1_IN_LEN = 42 ;
+
+static const uint8_t P9N2_EQ_LOCAL_FIR_MASK_LFIR_IN = 0 ;
+static const uint8_t P9N2_EQ_LOCAL_FIR_MASK_LFIR_IN_LEN = 42 ;
+
+static const uint8_t P9N2_EX_LOCAL_FIR_MASK_LFIR_IN = 0 ;
+static const uint8_t P9N2_EX_LOCAL_FIR_MASK_LFIR_IN_LEN = 42 ;
+
+static const uint8_t P9N2_C_LOCAL_FIR_MASK_LFIR_IN = 0 ;
+static const uint8_t P9N2_C_LOCAL_FIR_MASK_LFIR_IN_LEN = 42 ;
+
+static const uint8_t P9N2_EQ_LOCAL_XSTOP_ERR_IN0 = 0 ;
+static const uint8_t P9N2_EQ_LOCAL_XSTOP_ERR_IN1 = 1 ;
+static const uint8_t P9N2_EQ_LOCAL_XSTOP_ERR_IN2 = 2 ;
+static const uint8_t P9N2_EQ_LOCAL_XSTOP_ERR_IN3 = 3 ;
+static const uint8_t P9N2_EQ_LOCAL_XSTOP_ERR_IN4 = 4 ;
+static const uint8_t P9N2_EQ_LOCAL_XSTOP_ERR_IN5 = 5 ;
+static const uint8_t P9N2_EQ_LOCAL_XSTOP_ERR_IN6 = 6 ;
+static const uint8_t P9N2_EQ_LOCAL_XSTOP_ERR_IN7 = 7 ;
+static const uint8_t P9N2_EQ_LOCAL_XSTOP_ERR_IN8 = 8 ;
+static const uint8_t P9N2_EQ_LOCAL_XSTOP_ERR_IN9 = 9 ;
+static const uint8_t P9N2_EQ_LOCAL_XSTOP_ERR_IN10 = 10 ;
+static const uint8_t P9N2_EQ_LOCAL_XSTOP_ERR_IN11 = 11 ;
+static const uint8_t P9N2_EQ_LOCAL_XSTOP_ERR_IN12 = 12 ;
+static const uint8_t P9N2_EQ_LOCAL_XSTOP_ERR_IN13 = 13 ;
+static const uint8_t P9N2_EQ_LOCAL_XSTOP_ERR_IN14 = 14 ;
+static const uint8_t P9N2_EQ_LOCAL_XSTOP_ERR_IN15 = 15 ;
+static const uint8_t P9N2_EQ_LOCAL_XSTOP_ERR_IN16 = 16 ;
+static const uint8_t P9N2_EQ_LOCAL_XSTOP_ERR_IN17 = 17 ;
+static const uint8_t P9N2_EQ_LOCAL_XSTOP_ERR_IN18 = 18 ;
+static const uint8_t P9N2_EQ_LOCAL_XSTOP_ERR_IN19 = 19 ;
+static const uint8_t P9N2_EQ_LOCAL_XSTOP_ERR_IN20 = 20 ;
+static const uint8_t P9N2_EQ_LOCAL_XSTOP_ERR_IN21 = 21 ;
+static const uint8_t P9N2_EQ_LOCAL_XSTOP_ERR_IN22 = 22 ;
+
+static const uint8_t P9N2_EX_LOCAL_XSTOP_ERR_IN0 = 0 ;
+static const uint8_t P9N2_EX_LOCAL_XSTOP_ERR_IN1 = 1 ;
+static const uint8_t P9N2_EX_LOCAL_XSTOP_ERR_IN2 = 2 ;
+static const uint8_t P9N2_EX_LOCAL_XSTOP_ERR_IN3 = 3 ;
+static const uint8_t P9N2_EX_LOCAL_XSTOP_ERR_IN4 = 4 ;
+static const uint8_t P9N2_EX_LOCAL_XSTOP_ERR_IN5 = 5 ;
+static const uint8_t P9N2_EX_LOCAL_XSTOP_ERR_IN6 = 6 ;
+static const uint8_t P9N2_EX_LOCAL_XSTOP_ERR_IN7 = 7 ;
+static const uint8_t P9N2_EX_LOCAL_XSTOP_ERR_IN8 = 8 ;
+static const uint8_t P9N2_EX_LOCAL_XSTOP_ERR_IN9 = 9 ;
+static const uint8_t P9N2_EX_LOCAL_XSTOP_ERR_IN10 = 10 ;
+static const uint8_t P9N2_EX_LOCAL_XSTOP_ERR_IN11 = 11 ;
+static const uint8_t P9N2_EX_LOCAL_XSTOP_ERR_IN12 = 12 ;
+static const uint8_t P9N2_EX_LOCAL_XSTOP_ERR_IN13 = 13 ;
+static const uint8_t P9N2_EX_LOCAL_XSTOP_ERR_IN14 = 14 ;
+static const uint8_t P9N2_EX_LOCAL_XSTOP_ERR_IN15 = 15 ;
+static const uint8_t P9N2_EX_LOCAL_XSTOP_ERR_IN16 = 16 ;
+static const uint8_t P9N2_EX_LOCAL_XSTOP_ERR_IN17 = 17 ;
+static const uint8_t P9N2_EX_LOCAL_XSTOP_ERR_IN18 = 18 ;
+static const uint8_t P9N2_EX_LOCAL_XSTOP_ERR_IN19 = 19 ;
+static const uint8_t P9N2_EX_LOCAL_XSTOP_ERR_IN20 = 20 ;
+static const uint8_t P9N2_EX_LOCAL_XSTOP_ERR_IN21 = 21 ;
+static const uint8_t P9N2_EX_LOCAL_XSTOP_ERR_IN22 = 22 ;
+
+static const uint8_t P9N2_C_LOCAL_XSTOP_ERR_IN0 = 0 ;
+static const uint8_t P9N2_C_LOCAL_XSTOP_ERR_IN1 = 1 ;
+static const uint8_t P9N2_C_LOCAL_XSTOP_ERR_IN2 = 2 ;
+static const uint8_t P9N2_C_LOCAL_XSTOP_ERR_IN3 = 3 ;
+static const uint8_t P9N2_C_LOCAL_XSTOP_ERR_IN4 = 4 ;
+static const uint8_t P9N2_C_LOCAL_XSTOP_ERR_IN5 = 5 ;
+static const uint8_t P9N2_C_LOCAL_XSTOP_ERR_IN6 = 6 ;
+static const uint8_t P9N2_C_LOCAL_XSTOP_ERR_IN7 = 7 ;
+static const uint8_t P9N2_C_LOCAL_XSTOP_ERR_IN8 = 8 ;
+static const uint8_t P9N2_C_LOCAL_XSTOP_ERR_IN9 = 9 ;
+static const uint8_t P9N2_C_LOCAL_XSTOP_ERR_IN10 = 10 ;
+static const uint8_t P9N2_C_LOCAL_XSTOP_ERR_IN11 = 11 ;
+static const uint8_t P9N2_C_LOCAL_XSTOP_ERR_IN12 = 12 ;
+static const uint8_t P9N2_C_LOCAL_XSTOP_ERR_IN13 = 13 ;
+static const uint8_t P9N2_C_LOCAL_XSTOP_ERR_IN14 = 14 ;
+static const uint8_t P9N2_C_LOCAL_XSTOP_ERR_IN15 = 15 ;
+static const uint8_t P9N2_C_LOCAL_XSTOP_ERR_IN16 = 16 ;
+static const uint8_t P9N2_C_LOCAL_XSTOP_ERR_IN17 = 17 ;
+static const uint8_t P9N2_C_LOCAL_XSTOP_ERR_IN18 = 18 ;
+static const uint8_t P9N2_C_LOCAL_XSTOP_ERR_IN19 = 19 ;
+static const uint8_t P9N2_C_LOCAL_XSTOP_ERR_IN20 = 20 ;
+static const uint8_t P9N2_C_LOCAL_XSTOP_ERR_IN21 = 21 ;
+static const uint8_t P9N2_C_LOCAL_XSTOP_ERR_IN22 = 22 ;
+
+static const uint8_t P9N2_EQ_LOCAL_XSTOP_MASK_IN = 0 ;
+static const uint8_t P9N2_EQ_LOCAL_XSTOP_MASK_IN_LEN = 22 ;
+
+static const uint8_t P9N2_EX_LOCAL_XSTOP_MASK_IN = 0 ;
+static const uint8_t P9N2_EX_LOCAL_XSTOP_MASK_IN_LEN = 22 ;
+
+static const uint8_t P9N2_C_LOCAL_XSTOP_MASK_IN = 0 ;
+static const uint8_t P9N2_C_LOCAL_XSTOP_MASK_IN_LEN = 22 ;
+
+static const uint8_t P9N2_EQ_LRU_VIC_ALLOC_REG_L3_COLUMN_SEGR_COLUMN_CFG = 0 ;
+static const uint8_t P9N2_EQ_LRU_VIC_ALLOC_REG_L3_COLUMN_SEGR_COLUMN_CFG_LEN = 20 ;
+static const uint8_t P9N2_EQ_LRU_VIC_ALLOC_REG_L3_COLUMN_MD_CFG = 20 ;
+static const uint8_t P9N2_EQ_LRU_VIC_ALLOC_REG_L3_COLUMN_MD_CFG_LEN = 2 ;
+
+static const uint8_t P9N2_EX_L3_LRU_VIC_ALLOC_REG_L3_COLUMN_SEGR_COLUMN_CFG = 0 ;
+static const uint8_t P9N2_EX_L3_LRU_VIC_ALLOC_REG_L3_COLUMN_SEGR_COLUMN_CFG_LEN = 20 ;
+static const uint8_t P9N2_EX_L3_LRU_VIC_ALLOC_REG_L3_COLUMN_MD_CFG = 20 ;
+static const uint8_t P9N2_EX_L3_LRU_VIC_ALLOC_REG_L3_COLUMN_MD_CFG_LEN = 2 ;
+
+static const uint8_t P9N2_EX_L2_LSU_HOLD_OUT_REG0_LSEXEC_HYPERV_TRAP_CHECKSTOP_HOLD_OUT = 0 ;
+static const uint8_t P9N2_EX_L2_LSU_HOLD_OUT_REG0_LSEXEC_BAD_DVAL_FINISH_CHECKSTOP_HOLD_OUT = 1 ;
+static const uint8_t P9N2_EX_L2_LSU_HOLD_OUT_REG0_LSEXEC_REJECT_FINISH_CHECKSTOP_HOLD_OUT = 2 ;
+static const uint8_t P9N2_EX_L2_LSU_HOLD_OUT_REG0_FLSH_FFN_AND_NOT_UC_HOLD_OUT = 3 ;
+static const uint8_t P9N2_EX_L2_LSU_HOLD_OUT_REG0_FLSH_FLUSH_NEXT_UCODE_HOLD_OUT = 4 ;
+static const uint8_t P9N2_EX_L2_LSU_HOLD_OUT_REG0_FLSH_INVALID_FLUSH_CASE_HOLD_OUT = 5 ;
+static const uint8_t P9N2_EX_L2_LSU_HOLD_OUT_REG0_FLSH_FLUSH_CRITICAL_OP_HOLD_OUT = 6 ;
+static const uint8_t P9N2_EX_L2_LSU_HOLD_OUT_REG0_FLSH_FLUSH_NEXT_NON_CRIT_ATOMIC_HOLD_OUT = 7 ;
+static const uint8_t P9N2_EX_L2_LSU_HOLD_OUT_REG0_LSLRQE_CI_CDF_STUCK_HOLD_OUT = 8 ;
+static const uint8_t P9N2_EX_L2_LSU_HOLD_OUT_REG0_LSLRQE_OVERFLOW_HOLD_OUT = 9 ;
+static const uint8_t P9N2_EX_L2_LSU_HOLD_OUT_REG0_LSLRQF_OVERFLOW_HOLD_OUT = 10 ;
+static const uint8_t P9N2_EX_L2_LSU_HOLD_OUT_REG0_LSLSAQ_OVERFLOW_HOLD_OUT = 11 ;
+static const uint8_t P9N2_EX_L2_LSU_HOLD_OUT_REG0_LSLMQE_BAD_MC_RLD_DTYPE_ERR_HOLD_OUT = 12 ;
+static const uint8_t P9N2_EX_L2_LSU_HOLD_OUT_REG0_LSLMQE_GOT_SV_TWICE_ERR_HOLD_OUT = 13 ;
+static const uint8_t P9N2_EX_L2_LSU_HOLD_OUT_REG0_LSLMQE_INV_RD_ERR_HOLD_OUT = 14 ;
+static const uint8_t P9N2_EX_L2_LSU_HOLD_OUT_REG0_SCOM_PARITY_HOLD_OUT = 15 ;
+
+static const uint8_t P9N2_C_LSU_HOLD_OUT_REG0_LSEXEC_HYPERV_TRAP_CHECKSTOP_HOLD_OUT = 0 ;
+static const uint8_t P9N2_C_LSU_HOLD_OUT_REG0_LSEXEC_BAD_DVAL_FINISH_CHECKSTOP_HOLD_OUT = 1 ;
+static const uint8_t P9N2_C_LSU_HOLD_OUT_REG0_LSEXEC_REJECT_FINISH_CHECKSTOP_HOLD_OUT = 2 ;
+static const uint8_t P9N2_C_LSU_HOLD_OUT_REG0_FLSH_FFN_AND_NOT_UC_HOLD_OUT = 3 ;
+static const uint8_t P9N2_C_LSU_HOLD_OUT_REG0_FLSH_FLUSH_NEXT_UCODE_HOLD_OUT = 4 ;
+static const uint8_t P9N2_C_LSU_HOLD_OUT_REG0_FLSH_INVALID_FLUSH_CASE_HOLD_OUT = 5 ;
+static const uint8_t P9N2_C_LSU_HOLD_OUT_REG0_FLSH_FLUSH_CRITICAL_OP_HOLD_OUT = 6 ;
+static const uint8_t P9N2_C_LSU_HOLD_OUT_REG0_FLSH_FLUSH_NEXT_NON_CRIT_ATOMIC_HOLD_OUT = 7 ;
+static const uint8_t P9N2_C_LSU_HOLD_OUT_REG0_LSLRQE_CI_CDF_STUCK_HOLD_OUT = 8 ;
+static const uint8_t P9N2_C_LSU_HOLD_OUT_REG0_LSLRQE_OVERFLOW_HOLD_OUT = 9 ;
+static const uint8_t P9N2_C_LSU_HOLD_OUT_REG0_LSLRQF_OVERFLOW_HOLD_OUT = 10 ;
+static const uint8_t P9N2_C_LSU_HOLD_OUT_REG0_LSLSAQ_OVERFLOW_HOLD_OUT = 11 ;
+static const uint8_t P9N2_C_LSU_HOLD_OUT_REG0_LSLMQE_BAD_MC_RLD_DTYPE_ERR_HOLD_OUT = 12 ;
+static const uint8_t P9N2_C_LSU_HOLD_OUT_REG0_LSLMQE_GOT_SV_TWICE_ERR_HOLD_OUT = 13 ;
+static const uint8_t P9N2_C_LSU_HOLD_OUT_REG0_LSLMQE_INV_RD_ERR_HOLD_OUT = 14 ;
+static const uint8_t P9N2_C_LSU_HOLD_OUT_REG0_SCOM_PARITY_HOLD_OUT = 15 ;
+
+static const uint8_t P9N2_EX_L2_LSU_HOLD_OUT_REG1_LSSLBC_MULTI_BUSY_CHECKSTOP_HOLD_OUT = 0 ;
+static const uint8_t P9N2_EX_L2_LSU_HOLD_OUT_REG1_LSSLBC_MULTI_ERAT_WRITE_CHECKSTOP_HOLD_OUT = 1 ;
+static const uint8_t P9N2_EX_L2_LSU_HOLD_OUT_REG1_LSSLBC_MULTI_GRANT_CHECKSTOP_HOLD_OUT = 2 ;
+static const uint8_t P9N2_EX_L2_LSU_HOLD_OUT_REG1_LSSLBC_MULTI_PGSEL_CHECKSTOP_HOLD_OUT = 3 ;
+static const uint8_t P9N2_EX_L2_LSU_HOLD_OUT_REG1_LSPRQ_CONTROL_ERROR_CORE_XSTOP_HOLD_OUT = 4 ;
+static const uint8_t P9N2_EX_L2_LSU_HOLD_OUT_REG1_LSPRQ_CONTROL_ERROR_SYS_XSTOP_HOLD_OUT = 5 ;
+static const uint8_t P9N2_EX_L2_LSU_HOLD_OUT_REG1_LS_S2QR_PERR_P2_HOLD_OUT = 6 ;
+static const uint8_t P9N2_EX_L2_LSU_HOLD_OUT_REG1_LSPRQ_SPR_PERR_HOLD_OUT = 7 ;
+static const uint8_t P9N2_EX_L2_LSU_HOLD_OUT_REG1_LSAMRD_SPR_PERR_HOLD_OUT = 8 ;
+static const uint8_t P9N2_EX_L2_LSU_HOLD_OUT_REG1_LSAMRS_SPR_PERR_HOLD_OUT = 9 ;
+static const uint8_t P9N2_EX_L2_LSU_HOLD_OUT_REG1_LSINTR_SPR_PERR_HOLD_OUT = 10 ;
+static const uint8_t P9N2_EX_L2_LSU_HOLD_OUT_REG1_LSXREG_SPR_PERR_HOLD_OUT = 11 ;
+static const uint8_t P9N2_EX_L2_LSU_HOLD_OUT_REG1_GRBC_SPR_PARITY_ERROR_CORE_XSTOP_HOLD_OUT = 12 ;
+static const uint8_t P9N2_EX_L2_LSU_HOLD_OUT_REG1_WPPM_SPR_PARITY_ERROR_CORE_XSTOP_HOLD_OUT = 13 ;
+static const uint8_t P9N2_EX_L2_LSU_HOLD_OUT_REG1_LSPRQ_CONTROL_ERROR_RECOV_HOLD_OUT = 14 ;
+static const uint8_t P9N2_EX_L2_LSU_HOLD_OUT_REG1_LSS2Q_ERRC_RTYPE_CHECKSTOP_HOLD_OUT = 15 ;
+
+static const uint8_t P9N2_C_LSU_HOLD_OUT_REG1_LSSLBC_MULTI_BUSY_CHECKSTOP_HOLD_OUT = 0 ;
+static const uint8_t P9N2_C_LSU_HOLD_OUT_REG1_LSSLBC_MULTI_ERAT_WRITE_CHECKSTOP_HOLD_OUT = 1 ;
+static const uint8_t P9N2_C_LSU_HOLD_OUT_REG1_LSSLBC_MULTI_GRANT_CHECKSTOP_HOLD_OUT = 2 ;
+static const uint8_t P9N2_C_LSU_HOLD_OUT_REG1_LSSLBC_MULTI_PGSEL_CHECKSTOP_HOLD_OUT = 3 ;
+static const uint8_t P9N2_C_LSU_HOLD_OUT_REG1_LSPRQ_CONTROL_ERROR_CORE_XSTOP_HOLD_OUT = 4 ;
+static const uint8_t P9N2_C_LSU_HOLD_OUT_REG1_LSPRQ_CONTROL_ERROR_SYS_XSTOP_HOLD_OUT = 5 ;
+static const uint8_t P9N2_C_LSU_HOLD_OUT_REG1_LS_S2QR_PERR_P2_HOLD_OUT = 6 ;
+static const uint8_t P9N2_C_LSU_HOLD_OUT_REG1_LSPRQ_SPR_PERR_HOLD_OUT = 7 ;
+static const uint8_t P9N2_C_LSU_HOLD_OUT_REG1_LSAMRD_SPR_PERR_HOLD_OUT = 8 ;
+static const uint8_t P9N2_C_LSU_HOLD_OUT_REG1_LSAMRS_SPR_PERR_HOLD_OUT = 9 ;
+static const uint8_t P9N2_C_LSU_HOLD_OUT_REG1_LSINTR_SPR_PERR_HOLD_OUT = 10 ;
+static const uint8_t P9N2_C_LSU_HOLD_OUT_REG1_LSXREG_SPR_PERR_HOLD_OUT = 11 ;
+static const uint8_t P9N2_C_LSU_HOLD_OUT_REG1_GRBC_SPR_PARITY_ERROR_CORE_XSTOP_HOLD_OUT = 12 ;
+static const uint8_t P9N2_C_LSU_HOLD_OUT_REG1_WPPM_SPR_PARITY_ERROR_CORE_XSTOP_HOLD_OUT = 13 ;
+static const uint8_t P9N2_C_LSU_HOLD_OUT_REG1_LSPRQ_CONTROL_ERROR_RECOV_HOLD_OUT = 14 ;
+static const uint8_t P9N2_C_LSU_HOLD_OUT_REG1_LSS2Q_ERRC_RTYPE_CHECKSTOP_HOLD_OUT = 15 ;
+
+static const uint8_t P9N2_EX_L2_LSU_HOLD_OUT_REG2_LS0_DCAC_FIN_PERR_HOLD_OUT = 0 ;
+static const uint8_t P9N2_EX_L2_LSU_HOLD_OUT_REG2_LS1_DCAC_FIN_PERR_HOLD_OUT = 1 ;
+static const uint8_t P9N2_EX_L2_LSU_HOLD_OUT_REG2_LS2_DCAC_FIN_PERR_HOLD_OUT = 2 ;
+static const uint8_t P9N2_EX_L2_LSU_HOLD_OUT_REG2_LS3_DCAC_FIN_PERR_HOLD_OUT = 3 ;
+static const uint8_t P9N2_EX_L2_LSU_HOLD_OUT_REG2_SETC_RC6_RD23_PARITY_ERROR_TOTAL_HOLD_OUT = 4 ;
+static const uint8_t P9N2_EX_L2_LSU_HOLD_OUT_REG2_WDRD0_RC9_DDIR_ANY_ERROR_ANY_SET_HOLD_OUT = 5 ;
+static const uint8_t P9N2_EX_L2_LSU_HOLD_OUT_REG2_WDRD1_RC8_DDIR_ANY_ERROR_ANY_SET_HOLD_OUT = 6 ;
+static const uint8_t P9N2_EX_L2_LSU_HOLD_OUT_REG2_DYNAM_SET_DELETED_HOLD_OUT = 7 ;
+static const uint8_t P9N2_EX_L2_LSU_HOLD_OUT_REG2_LS_SLB_MULTIHIT_HOLD_OUT = 8 ;
+static const uint8_t P9N2_EX_L2_LSU_HOLD_OUT_REG2_LS_SLB_P_HOLD_OUT = 9 ;
+static const uint8_t P9N2_EX_L2_LSU_HOLD_OUT_REG2_LS_TLB_MULTIHIT_HOLD_OUT = 10 ;
+static const uint8_t P9N2_EX_L2_LSU_HOLD_OUT_REG2_LS_TLB_P_HOLD_OUT = 11 ;
+static const uint8_t P9N2_EX_L2_LSU_HOLD_OUT_REG2_STPM0_RP2_SETP_PERR_HOLD_OUT = 12 ;
+static const uint8_t P9N2_EX_L2_LSU_HOLD_OUT_REG2_STPM1_RP2_SETP_PERR_HOLD_OUT = 13 ;
+static const uint8_t P9N2_EX_L2_LSU_HOLD_OUT_REG2_STPM2_RP1_SETP_PERR_HOLD_OUT = 14 ;
+static const uint8_t P9N2_EX_L2_LSU_HOLD_OUT_REG2_STPM3_RP1_SETP_PERR_HOLD_OUT = 15 ;
+
+static const uint8_t P9N2_C_LSU_HOLD_OUT_REG2_LS0_DCAC_FIN_PERR_HOLD_OUT = 0 ;
+static const uint8_t P9N2_C_LSU_HOLD_OUT_REG2_LS1_DCAC_FIN_PERR_HOLD_OUT = 1 ;
+static const uint8_t P9N2_C_LSU_HOLD_OUT_REG2_LS2_DCAC_FIN_PERR_HOLD_OUT = 2 ;
+static const uint8_t P9N2_C_LSU_HOLD_OUT_REG2_LS3_DCAC_FIN_PERR_HOLD_OUT = 3 ;
+static const uint8_t P9N2_C_LSU_HOLD_OUT_REG2_SETC_RC6_RD23_PARITY_ERROR_TOTAL_HOLD_OUT = 4 ;
+static const uint8_t P9N2_C_LSU_HOLD_OUT_REG2_WDRD0_RC9_DDIR_ANY_ERROR_ANY_SET_HOLD_OUT = 5 ;
+static const uint8_t P9N2_C_LSU_HOLD_OUT_REG2_WDRD1_RC8_DDIR_ANY_ERROR_ANY_SET_HOLD_OUT = 6 ;
+static const uint8_t P9N2_C_LSU_HOLD_OUT_REG2_DYNAM_SET_DELETED_HOLD_OUT = 7 ;
+static const uint8_t P9N2_C_LSU_HOLD_OUT_REG2_LS_SLB_MULTIHIT_HOLD_OUT = 8 ;
+static const uint8_t P9N2_C_LSU_HOLD_OUT_REG2_LS_SLB_P_HOLD_OUT = 9 ;
+static const uint8_t P9N2_C_LSU_HOLD_OUT_REG2_LS_TLB_MULTIHIT_HOLD_OUT = 10 ;
+static const uint8_t P9N2_C_LSU_HOLD_OUT_REG2_LS_TLB_P_HOLD_OUT = 11 ;
+static const uint8_t P9N2_C_LSU_HOLD_OUT_REG2_STPM0_RP2_SETP_PERR_HOLD_OUT = 12 ;
+static const uint8_t P9N2_C_LSU_HOLD_OUT_REG2_STPM1_RP2_SETP_PERR_HOLD_OUT = 13 ;
+static const uint8_t P9N2_C_LSU_HOLD_OUT_REG2_STPM2_RP1_SETP_PERR_HOLD_OUT = 14 ;
+static const uint8_t P9N2_C_LSU_HOLD_OUT_REG2_STPM3_RP1_SETP_PERR_HOLD_OUT = 15 ;
+
+static const uint8_t P9N2_EX_L2_LSU_HOLD_OUT_REG3_DMAG0_FIN_RF_PARITY_HOLD_OUT = 0 ;
+static const uint8_t P9N2_EX_L2_LSU_HOLD_OUT_REG3_DMAG1_FIN_RF_PARITY_HOLD_OUT = 1 ;
+static const uint8_t P9N2_EX_L2_LSU_HOLD_OUT_REG3_DMAG2_RP2_RF_PARITY_HOLD_OUT = 2 ;
+static const uint8_t P9N2_EX_L2_LSU_HOLD_OUT_REG3_DMAG3_RP2_RF_PARITY_HOLD_OUT = 3 ;
+static const uint8_t P9N2_EX_L2_LSU_HOLD_OUT_REG3_LS0_RP2_RSVT_MULTILMQ_HOLD_OUT = 4 ;
+static const uint8_t P9N2_EX_L2_LSU_HOLD_OUT_REG3_LS1_RP2_RSVT_MULTILMQ_HOLD_OUT = 5 ;
+static const uint8_t P9N2_EX_L2_LSU_HOLD_OUT_REG3_LS2_RP1_RSVT_MULTILMQ_HOLD_OUT = 6 ;
+static const uint8_t P9N2_EX_L2_LSU_HOLD_OUT_REG3_LS3_RP1_RSVT_MULTILMQ_HOLD_OUT = 7 ;
+static const uint8_t P9N2_EX_L2_LSU_HOLD_OUT_REG3_LSERTD_FIN_P_HOLD_OUT = 8 ;
+static const uint8_t P9N2_EX_L2_LSU_HOLD_OUT_REG3_LSERTD_FIN_ERATMHE_HOLD_OUT = 9 ;
+static const uint8_t P9N2_EX_L2_LSU_HOLD_OUT_REG3_LSS2Q_PC_S2Q_QUEUE_OVERFLOW_HOLD_OUT = 10 ;
+static const uint8_t P9N2_EX_L2_LSU_HOLD_OUT_REG3_LSSRQ_RES_OVERFLOW_HOLD_OUT = 11 ;
+static const uint8_t P9N2_EX_L2_LSU_HOLD_OUT_REG3_HID_PARITY_ERROR_CORE_XSTOP_HOLD_OUT = 12 ;
+static const uint8_t P9N2_EX_L2_LSU_HOLD_OUT_REG3_LSTBLW_CHECKSTOP_HOLD_OUT = 13 ;
+static const uint8_t P9N2_EX_L2_LSU_HOLD_OUT_REG3_LSLRQE_NTC_HANGBUSTER_HOLD_OUT = 14 ;
+static const uint8_t P9N2_EX_L2_LSU_HOLD_OUT_REG3_RESERVED1 = 15 ;
+
+static const uint8_t P9N2_C_LSU_HOLD_OUT_REG3_DMAG0_FIN_RF_PARITY_HOLD_OUT = 0 ;
+static const uint8_t P9N2_C_LSU_HOLD_OUT_REG3_DMAG1_FIN_RF_PARITY_HOLD_OUT = 1 ;
+static const uint8_t P9N2_C_LSU_HOLD_OUT_REG3_DMAG2_RP2_RF_PARITY_HOLD_OUT = 2 ;
+static const uint8_t P9N2_C_LSU_HOLD_OUT_REG3_DMAG3_RP2_RF_PARITY_HOLD_OUT = 3 ;
+static const uint8_t P9N2_C_LSU_HOLD_OUT_REG3_LS0_RP2_RSVT_MULTILMQ_HOLD_OUT = 4 ;
+static const uint8_t P9N2_C_LSU_HOLD_OUT_REG3_LS1_RP2_RSVT_MULTILMQ_HOLD_OUT = 5 ;
+static const uint8_t P9N2_C_LSU_HOLD_OUT_REG3_LS2_RP1_RSVT_MULTILMQ_HOLD_OUT = 6 ;
+static const uint8_t P9N2_C_LSU_HOLD_OUT_REG3_LS3_RP1_RSVT_MULTILMQ_HOLD_OUT = 7 ;
+static const uint8_t P9N2_C_LSU_HOLD_OUT_REG3_LSERTD_FIN_P_HOLD_OUT = 8 ;
+static const uint8_t P9N2_C_LSU_HOLD_OUT_REG3_LSERTD_FIN_ERATMHE_HOLD_OUT = 9 ;
+static const uint8_t P9N2_C_LSU_HOLD_OUT_REG3_LSS2Q_PC_S2Q_QUEUE_OVERFLOW_HOLD_OUT = 10 ;
+static const uint8_t P9N2_C_LSU_HOLD_OUT_REG3_LSSRQ_RES_OVERFLOW_HOLD_OUT = 11 ;
+static const uint8_t P9N2_C_LSU_HOLD_OUT_REG3_HID_PARITY_ERROR_CORE_XSTOP_HOLD_OUT = 12 ;
+static const uint8_t P9N2_C_LSU_HOLD_OUT_REG3_LSTBLW_CHECKSTOP_HOLD_OUT = 13 ;
+static const uint8_t P9N2_C_LSU_HOLD_OUT_REG3_LSLRQE_NTC_HANGBUSTER_HOLD_OUT = 14 ;
+static const uint8_t P9N2_C_LSU_HOLD_OUT_REG3_RESERVED1 = 15 ;
+
+static const uint8_t P9N2_EQ_MIB_XIICAC_ICACHE_TAG_ADDR = 0 ;
+static const uint8_t P9N2_EQ_MIB_XIICAC_ICACHE_TAG_ADDR_LEN = 27 ;
+static const uint8_t P9N2_EQ_MIB_XIICAC_ICACHE_ERR = 32 ;
+static const uint8_t P9N2_EQ_MIB_XIICAC_CME_SCOM_XISIB_PIB_IFETCH_PENDING = 34 ;
+static const uint8_t P9N2_EQ_MIB_XIICAC_XIMEM_MEM_IFETCH_PENDING = 35 ;
+static const uint8_t P9N2_EQ_MIB_XIICAC_ICACHE_VALID = 36 ;
+static const uint8_t P9N2_EQ_MIB_XIICAC_ICACHE_VALID_LEN = 4 ;
+static const uint8_t P9N2_EQ_MIB_XIICAC_ICACHE_LINE2_VALID = 40 ;
+static const uint8_t P9N2_EQ_MIB_XIICAC_ICACHE_LINE2_VALID_LEN = 4 ;
+static const uint8_t P9N2_EQ_MIB_XIICAC_ICACHE_LINE_PTR = 45 ;
+static const uint8_t P9N2_EQ_MIB_XIICAC_ICACHE_LINE2_ERR = 46 ;
+static const uint8_t P9N2_EQ_MIB_XIICAC_ICACHE_PREFETCH_PENDING = 47 ;
+
+static const uint8_t P9N2_EX_MIB_XIICAC_ICACHE_TAG_ADDR = 0 ;
+static const uint8_t P9N2_EX_MIB_XIICAC_ICACHE_TAG_ADDR_LEN = 27 ;
+static const uint8_t P9N2_EX_MIB_XIICAC_ICACHE_ERR = 32 ;
+static const uint8_t P9N2_EX_MIB_XIICAC_CME_SCOM_XISIB_PIB_IFETCH_PENDING = 34 ;
+static const uint8_t P9N2_EX_MIB_XIICAC_XIMEM_MEM_IFETCH_PENDING = 35 ;
+static const uint8_t P9N2_EX_MIB_XIICAC_ICACHE_VALID = 36 ;
+static const uint8_t P9N2_EX_MIB_XIICAC_ICACHE_VALID_LEN = 4 ;
+static const uint8_t P9N2_EX_MIB_XIICAC_ICACHE_LINE2_VALID = 40 ;
+static const uint8_t P9N2_EX_MIB_XIICAC_ICACHE_LINE2_VALID_LEN = 4 ;
+static const uint8_t P9N2_EX_MIB_XIICAC_ICACHE_LINE_PTR = 45 ;
+static const uint8_t P9N2_EX_MIB_XIICAC_ICACHE_LINE2_ERR = 46 ;
+static const uint8_t P9N2_EX_MIB_XIICAC_ICACHE_PREFETCH_PENDING = 47 ;
+
+static const uint8_t P9N2_EQ_MIB_XIMEM_MEM_ADDR = 0 ;
+static const uint8_t P9N2_EQ_MIB_XIMEM_MEM_ADDR_LEN = 32 ;
+static const uint8_t P9N2_EQ_MIB_XIMEM_MEM_R_NW = 32 ;
+static const uint8_t P9N2_EQ_MIB_XIMEM_MEM_BUSY = 33 ;
+static const uint8_t P9N2_EQ_MIB_XIMEM_MEM_IMPRECISE_ERROR_PENDING = 34 ;
+static const uint8_t P9N2_EQ_MIB_XIMEM_MEM_BYTE_ENABLE = 35 ;
+static const uint8_t P9N2_EQ_MIB_XIMEM_MEM_BYTE_ENABLE_LEN = 8 ;
+static const uint8_t P9N2_EQ_MIB_XIMEM_MEM_LINE_MODE = 43 ;
+static const uint8_t P9N2_EQ_MIB_XIMEM_MEM_ERROR = 49 ;
+static const uint8_t P9N2_EQ_MIB_XIMEM_MEM_ERROR_LEN = 3 ;
+static const uint8_t P9N2_EQ_MIB_XIMEM_MEM_IFETCH_PENDING = 62 ;
+static const uint8_t P9N2_EQ_MIB_XIMEM_MEM_DATAOP_PENDING = 63 ;
+
+static const uint8_t P9N2_EX_MIB_XIMEM_MEM_ADDR = 0 ;
+static const uint8_t P9N2_EX_MIB_XIMEM_MEM_ADDR_LEN = 32 ;
+static const uint8_t P9N2_EX_MIB_XIMEM_MEM_R_NW = 32 ;
+static const uint8_t P9N2_EX_MIB_XIMEM_MEM_BUSY = 33 ;
+static const uint8_t P9N2_EX_MIB_XIMEM_MEM_IMPRECISE_ERROR_PENDING = 34 ;
+static const uint8_t P9N2_EX_MIB_XIMEM_MEM_BYTE_ENABLE = 35 ;
+static const uint8_t P9N2_EX_MIB_XIMEM_MEM_BYTE_ENABLE_LEN = 8 ;
+static const uint8_t P9N2_EX_MIB_XIMEM_MEM_LINE_MODE = 43 ;
+static const uint8_t P9N2_EX_MIB_XIMEM_MEM_ERROR = 49 ;
+static const uint8_t P9N2_EX_MIB_XIMEM_MEM_ERROR_LEN = 3 ;
+static const uint8_t P9N2_EX_MIB_XIMEM_MEM_IFETCH_PENDING = 62 ;
+static const uint8_t P9N2_EX_MIB_XIMEM_MEM_DATAOP_PENDING = 63 ;
+
+static const uint8_t P9N2_EQ_MIB_XISGB_STORE_ADDRESS = 0 ;
+static const uint8_t P9N2_EQ_MIB_XISGB_STORE_ADDRESS_LEN = 32 ;
+static const uint8_t P9N2_EQ_MIB_XISGB_XIMEM_MEM_IMPRECISE_ERROR_PENDING = 35 ;
+static const uint8_t P9N2_EQ_MIB_XISGB_SGB_BYTE_VALID = 36 ;
+static const uint8_t P9N2_EQ_MIB_XISGB_SGB_BYTE_VALID_LEN = 4 ;
+static const uint8_t P9N2_EQ_MIB_XISGB_SGB_FLUSH_PENDING = 63 ;
+
+static const uint8_t P9N2_EX_MIB_XISGB_STORE_ADDRESS = 0 ;
+static const uint8_t P9N2_EX_MIB_XISGB_STORE_ADDRESS_LEN = 32 ;
+static const uint8_t P9N2_EX_MIB_XISGB_XIMEM_MEM_IMPRECISE_ERROR_PENDING = 35 ;
+static const uint8_t P9N2_EX_MIB_XISGB_SGB_BYTE_VALID = 36 ;
+static const uint8_t P9N2_EX_MIB_XISGB_SGB_BYTE_VALID_LEN = 4 ;
+static const uint8_t P9N2_EX_MIB_XISGB_SGB_FLUSH_PENDING = 63 ;
+
+static const uint8_t P9N2_EQ_MODE_REG_IN0 = 0 ;
+static const uint8_t P9N2_EQ_MODE_REG_IN1 = 1 ;
+static const uint8_t P9N2_EQ_MODE_REG_IN2 = 2 ;
+static const uint8_t P9N2_EQ_MODE_REG_IN3 = 3 ;
+static const uint8_t P9N2_EQ_MODE_REG_IN4 = 4 ;
+static const uint8_t P9N2_EQ_MODE_REG_IN5 = 5 ;
+static const uint8_t P9N2_EQ_MODE_REG_IN6 = 6 ;
+static const uint8_t P9N2_EQ_MODE_REG_IN7 = 7 ;
+static const uint8_t P9N2_EQ_MODE_REG_IN8 = 8 ;
+static const uint8_t P9N2_EQ_MODE_REG_IN9 = 9 ;
+static const uint8_t P9N2_EQ_MODE_REG_IN10 = 10 ;
+static const uint8_t P9N2_EQ_MODE_REG_IN11 = 11 ;
+static const uint8_t P9N2_EQ_MODE_REG_IN = 12 ;
+static const uint8_t P9N2_EQ_MODE_REG_IN_LEN = 4 ;
+
+static const uint8_t P9N2_EX_MODE_REG_IN0 = 0 ;
+static const uint8_t P9N2_EX_MODE_REG_IN1 = 1 ;
+static const uint8_t P9N2_EX_MODE_REG_IN2 = 2 ;
+static const uint8_t P9N2_EX_MODE_REG_IN3 = 3 ;
+static const uint8_t P9N2_EX_MODE_REG_IN4 = 4 ;
+static const uint8_t P9N2_EX_MODE_REG_IN5 = 5 ;
+static const uint8_t P9N2_EX_MODE_REG_IN6 = 6 ;
+static const uint8_t P9N2_EX_MODE_REG_IN7 = 7 ;
+static const uint8_t P9N2_EX_MODE_REG_IN8 = 8 ;
+static const uint8_t P9N2_EX_MODE_REG_IN9 = 9 ;
+static const uint8_t P9N2_EX_MODE_REG_IN10 = 10 ;
+static const uint8_t P9N2_EX_MODE_REG_IN11 = 11 ;
+static const uint8_t P9N2_EX_MODE_REG_IN = 12 ;
+static const uint8_t P9N2_EX_MODE_REG_IN_LEN = 4 ;
+
+static const uint8_t P9N2_C_MODE_REG_IN0 = 0 ;
+static const uint8_t P9N2_C_MODE_REG_IN1 = 1 ;
+static const uint8_t P9N2_C_MODE_REG_IN2 = 2 ;
+static const uint8_t P9N2_C_MODE_REG_IN3 = 3 ;
+static const uint8_t P9N2_C_MODE_REG_IN4 = 4 ;
+static const uint8_t P9N2_C_MODE_REG_IN5 = 5 ;
+static const uint8_t P9N2_C_MODE_REG_IN6 = 6 ;
+static const uint8_t P9N2_C_MODE_REG_IN7 = 7 ;
+static const uint8_t P9N2_C_MODE_REG_IN8 = 8 ;
+static const uint8_t P9N2_C_MODE_REG_IN9 = 9 ;
+static const uint8_t P9N2_C_MODE_REG_IN10 = 10 ;
+static const uint8_t P9N2_C_MODE_REG_IN11 = 11 ;
+static const uint8_t P9N2_C_MODE_REG_IN = 12 ;
+static const uint8_t P9N2_C_MODE_REG_IN_LEN = 4 ;
+
+static const uint8_t P9N2_EQ_MODE_REG0_L3_DISABLED_CFG = 0 ;
+static const uint8_t P9N2_EQ_MODE_REG0_L3_DMAP_CI_EN_CFG = 1 ;
+static const uint8_t P9N2_EQ_MODE_REG0_L3_RDSN_LINEDEL_UE_EN = 2 ;
+static const uint8_t P9N2_EQ_MODE_REG0_L3_NO_ALLOCATE_EN = 3 ;
+static const uint8_t P9N2_EQ_MODE_REG0_L3_NO_ALLOCATE_ACTIVE = 4 ;
+static const uint8_t P9N2_EQ_MODE_REG0_L3_CERRS_PF_CFG_SKIP_GRP_SCOPE_EN = 5 ;
+static const uint8_t P9N2_EQ_MODE_REG0_L3_SPARE6 = 6 ;
+static const uint8_t P9N2_EQ_MODE_REG0_L3_SPARE7 = 7 ;
+static const uint8_t P9N2_EQ_MODE_REG0_L3_LCO_RTY_LIMIT_DISABLE = 8 ;
+static const uint8_t P9N2_EQ_MODE_REG0_L3_DYN_LCO_BLK_DIS_CFG = 9 ;
+static const uint8_t P9N2_EQ_MODE_REG0_L3_LCO_ADDR_TGT_ENABLE = 10 ;
+static const uint8_t P9N2_EQ_MODE_REG0_L3_ADDR_HASH_EN_CFG = 11 ;
+static const uint8_t P9N2_EQ_MODE_REG0_L3_SPARE12 = 12 ;
+static const uint8_t P9N2_EQ_MODE_REG0_L3CERRS_LCO_RETRY_THROTL_DIS = 13 ;
+static const uint8_t P9N2_EQ_MODE_REG0_L3_HANG_POLL_PULSE_DIV = 14 ;
+static const uint8_t P9N2_EQ_MODE_REG0_L3_HANG_POLL_PULSE_DIV_LEN = 4 ;
+static const uint8_t P9N2_EQ_MODE_REG0_L3_DATA_POLL_PULSE_DIV = 18 ;
+static const uint8_t P9N2_EQ_MODE_REG0_L3_DATA_POLL_PULSE_DIV_LEN = 4 ;
+static const uint8_t P9N2_EQ_MODE_REG0_L3_SYSMAP_SM_NOT_LG_SEL = 22 ;
+static const uint8_t P9N2_EQ_MODE_REG0_L3_CFG_CHIP_ADDR_EXT_MASK_EN = 23 ;
+static const uint8_t P9N2_EQ_MODE_REG0_L3_CFG_CHIP_ADDR_EXT_MASK_EN_LEN = 7 ;
+static const uint8_t P9N2_EQ_MODE_REG0_L3_CERRS_LRU_DECR_EN_CFG = 30 ;
+static const uint8_t P9N2_EQ_MODE_REG0_L3_CERRS_LRU_DECR_PROB_SEL_CFG = 31 ;
+static const uint8_t P9N2_EQ_MODE_REG0_L3_CERRS_LRU_DECR_PROB_SEL_CFG_LEN = 2 ;
+static const uint8_t P9N2_EQ_MODE_REG0_L3_CERRS_LRU_DECR_SUB_SEL_CFG = 33 ;
+static const uint8_t P9N2_EQ_MODE_REG0_L3_CERRS_LRU_DECR_SUB_SEL_CFG_LEN = 3 ;
+
+static const uint8_t P9N2_EX_L2_MODE_REG0_CFG_LRU_DIRECT_MAP = 0 ;
+static const uint8_t P9N2_EX_L2_MODE_REG0_CFG_RANDOM_EN = 1 ;
+static const uint8_t P9N2_EX_L2_MODE_REG0_CFG_SINGLE_MEM_EN = 2 ;
+static const uint8_t P9N2_EX_L2_MODE_REG0_CFG_SINGLE_MEM = 3 ;
+static const uint8_t P9N2_EX_L2_MODE_REG0_CFG_SINGLE_MEM_LEN = 8 ;
+static const uint8_t P9N2_EX_L2_MODE_REG0_CFG_L3_DIS = 11 ;
+static const uint8_t P9N2_EX_L2_MODE_REG0_CFG_CO_SOFT_PURGE_ME_SX_EN = 12 ;
+static const uint8_t P9N2_EX_L2_MODE_REG0_CFG_CO_SOFT_PURGE_ALL_LINES_EN = 13 ;
+static const uint8_t P9N2_EX_L2_MODE_REG0_CFG_DCBZ_TRASHMODE_EN = 14 ;
+static const uint8_t P9N2_EX_L2_MODE_REG0_CFG_CAC_ERR_REPAIR_EN = 15 ;
+static const uint8_t P9N2_EX_L2_MODE_REG0_CFG_LINEDEL_ON_CAC_UE_EN = 16 ;
+static const uint8_t P9N2_EX_L2_MODE_REG0_CFG_HW_TRIG_LINEDEL_LDDISP_CE_EN = 17 ;
+static const uint8_t P9N2_EX_L2_MODE_REG0_CFG_C0_L2_PB_ARB_RATE_SEL = 18 ;
+static const uint8_t P9N2_EX_L2_MODE_REG0_CFG_C0_L2_PB_ARB_RATE_SEL_LEN = 3 ;
+static const uint8_t P9N2_EX_L2_MODE_REG0_CFG_HASH_L3_ADDR_EN = 21 ;
+static const uint8_t P9N2_EX_L2_MODE_REG0_CFG_RC_FRC_DISP_EQ_NTM_INIG_SI_TO_RCR_EN = 22 ;
+static const uint8_t P9N2_EX_L2_MODE_REG0_CFG_SYSMAP_SM_NOT_LG_SEL = 23 ;
+static const uint8_t P9N2_EX_L2_MODE_REG0_CFG_Q_BIT_TID_MASK = 24 ;
+static const uint8_t P9N2_EX_L2_MODE_REG0_CFG_Q_BIT_TID_MASK_LEN = 8 ;
+static const uint8_t P9N2_EX_L2_MODE_REG0_CFG_STQ_PF_EN = 32 ;
+static const uint8_t P9N2_EX_L2_MODE_REG0_CFG_DCACHE_CAPP_LPC_EN = 33 ;
+static const uint8_t P9N2_EX_L2_MODE_REG0_CFG_PERFMON_INFO_SRC_ED_SEL = 34 ;
+static const uint8_t P9N2_EX_L2_MODE_REG0_CFG_C1_L2_PB_ARB_RATE_SEL = 35 ;
+static const uint8_t P9N2_EX_L2_MODE_REG0_CFG_C1_L2_PB_ARB_RATE_SEL_LEN = 3 ;
+static const uint8_t P9N2_EX_L2_MODE_REG0_CFG_SKIP_GRP_SCOPE_EN = 38 ;
+static const uint8_t P9N2_EX_L2_MODE_REG0_CFG_TM_DTT_EN = 39 ;
+static const uint8_t P9N2_EX_L2_MODE_REG0_MODE_REG0_SPARE = 40 ;
+static const uint8_t P9N2_EX_L2_MODE_REG0_MODE_REG0_SPARE_LEN = 2 ;
+
+static const uint8_t P9N2_EX_L3_MODE_REG0_L3_DISABLED_CFG = 0 ;
+static const uint8_t P9N2_EX_L3_MODE_REG0_L3_DMAP_CI_EN_CFG = 1 ;
+static const uint8_t P9N2_EX_L3_MODE_REG0_L3_RDSN_LINEDEL_UE_EN = 2 ;
+static const uint8_t P9N2_EX_L3_MODE_REG0_L3_NO_ALLOCATE_EN = 3 ;
+static const uint8_t P9N2_EX_L3_MODE_REG0_L3_NO_ALLOCATE_ACTIVE = 4 ;
+static const uint8_t P9N2_EX_L3_MODE_REG0_L3_CERRS_PF_CFG_SKIP_GRP_SCOPE_EN = 5 ;
+static const uint8_t P9N2_EX_L3_MODE_REG0_L3_SPARE6 = 6 ;
+static const uint8_t P9N2_EX_L3_MODE_REG0_L3_SPARE7 = 7 ;
+static const uint8_t P9N2_EX_L3_MODE_REG0_L3_LCO_RTY_LIMIT_DISABLE = 8 ;
+static const uint8_t P9N2_EX_L3_MODE_REG0_L3_DYN_LCO_BLK_DIS_CFG = 9 ;
+static const uint8_t P9N2_EX_L3_MODE_REG0_L3_LCO_ADDR_TGT_ENABLE = 10 ;
+static const uint8_t P9N2_EX_L3_MODE_REG0_L3_ADDR_HASH_EN_CFG = 11 ;
+static const uint8_t P9N2_EX_L3_MODE_REG0_L3_SPARE12 = 12 ;
+static const uint8_t P9N2_EX_L3_MODE_REG0_L3CERRS_LCO_RETRY_THROTL_DIS = 13 ;
+static const uint8_t P9N2_EX_L3_MODE_REG0_L3_HANG_POLL_PULSE_DIV = 14 ;
+static const uint8_t P9N2_EX_L3_MODE_REG0_L3_HANG_POLL_PULSE_DIV_LEN = 4 ;
+static const uint8_t P9N2_EX_L3_MODE_REG0_L3_DATA_POLL_PULSE_DIV = 18 ;
+static const uint8_t P9N2_EX_L3_MODE_REG0_L3_DATA_POLL_PULSE_DIV_LEN = 4 ;
+static const uint8_t P9N2_EX_L3_MODE_REG0_L3_SYSMAP_SM_NOT_LG_SEL = 22 ;
+static const uint8_t P9N2_EX_L3_MODE_REG0_L3_CFG_CHIP_ADDR_EXT_MASK_EN = 23 ;
+static const uint8_t P9N2_EX_L3_MODE_REG0_L3_CFG_CHIP_ADDR_EXT_MASK_EN_LEN = 7 ;
+static const uint8_t P9N2_EX_L3_MODE_REG0_L3_CERRS_LRU_DECR_EN_CFG = 30 ;
+static const uint8_t P9N2_EX_L3_MODE_REG0_L3_CERRS_LRU_DECR_PROB_SEL_CFG = 31 ;
+static const uint8_t P9N2_EX_L3_MODE_REG0_L3_CERRS_LRU_DECR_PROB_SEL_CFG_LEN = 2 ;
+static const uint8_t P9N2_EX_L3_MODE_REG0_L3_CERRS_LRU_DECR_SUB_SEL_CFG = 33 ;
+static const uint8_t P9N2_EX_L3_MODE_REG0_L3_CERRS_LRU_DECR_SUB_SEL_CFG_LEN = 3 ;
+
+static const uint8_t P9N2_EQ_MODE_REG1_L3_LCO_ENABLE_CFG = 0 ;
+static const uint8_t P9N2_EQ_MODE_REG1_L3_LCO_TARGET_GROUP = 1 ;
+static const uint8_t P9N2_EQ_MODE_REG1_L3_LCO_TARGET_ID = 2 ;
+static const uint8_t P9N2_EQ_MODE_REG1_L3_LCO_TARGET_ID_LEN = 4 ;
+static const uint8_t P9N2_EQ_MODE_REG1_L3_LCO_TARGET_VICTIMS = 6 ;
+static const uint8_t P9N2_EQ_MODE_REG1_L3_LCO_TARGET_VICTIMS_LEN = 16 ;
+static const uint8_t P9N2_EQ_MODE_REG1_L3_SCOM_CINJ_LCO_DIS = 22 ;
+
+static const uint8_t P9N2_EX_L2_MODE_REG1_CFG_ECCCK_CE_UE_SUE_ERR_DET_DIS = 0 ;
+static const uint8_t P9N2_EX_L2_MODE_REG1_CFG_ECCCK_UE_SUE_DET_DIS = 1 ;
+static const uint8_t P9N2_EX_L2_MODE_REG1_MODE_REG1_SPARE0 = 2 ;
+static const uint8_t P9N2_EX_L2_MODE_REG1_MODE_REG1_SPARE0_LEN = 2 ;
+static const uint8_t P9N2_EX_L2_MODE_REG1_HANG_POLL_PULSE_DIV = 4 ;
+static const uint8_t P9N2_EX_L2_MODE_REG1_HANG_POLL_PULSE_DIV_LEN = 4 ;
+static const uint8_t P9N2_EX_L2_MODE_REG1_DATA_POLL_PULSE_DIV = 8 ;
+static const uint8_t P9N2_EX_L2_MODE_REG1_DATA_POLL_PULSE_DIV_LEN = 4 ;
+static const uint8_t P9N2_EX_L2_MODE_REG1_MODE_REG1_SPARE1 = 12 ;
+static const uint8_t P9N2_EX_L2_MODE_REG1_MODE_REG1_SPARE1_LEN = 4 ;
+static const uint8_t P9N2_EX_L2_MODE_REG1_PM03_SMT_ROTATION_DIS = 16 ;
+static const uint8_t P9N2_EX_L2_MODE_REG1_PM47_SMT_ROTATION_DIS = 17 ;
+static const uint8_t P9N2_EX_L2_MODE_REG1_MODE_REG1_SPARE2 = 18 ;
+static const uint8_t P9N2_EX_L2_MODE_REG1_MODE_REG1_SPARE2_LEN = 2 ;
+static const uint8_t P9N2_EX_L2_MODE_REG1_PM07_TID_ROTATE_PLSS_RATE = 20 ;
+static const uint8_t P9N2_EX_L2_MODE_REG1_PM07_TID_ROTATE_PLSS_RATE_LEN = 3 ;
+static const uint8_t P9N2_EX_L2_MODE_REG1_MODE_REG1_SPARE3 = 23 ;
+static const uint8_t P9N2_EX_L2_MODE_REG1_MODE_REG1_SPARE3_LEN = 2 ;
+static const uint8_t P9N2_EX_L2_MODE_REG1_PM03_L23_EVENT_TID_SEL_EN = 25 ;
+static const uint8_t P9N2_EX_L2_MODE_REG1_PM03_L23_EVENT_TID_SEL_NUM = 26 ;
+static const uint8_t P9N2_EX_L2_MODE_REG1_PM03_L23_EVENT_TID_SEL_NUM_LEN = 2 ;
+static const uint8_t P9N2_EX_L2_MODE_REG1_PM47_L23_EVENT_TID_SEL_EN = 29 ;
+static const uint8_t P9N2_EX_L2_MODE_REG1_PM47_L23_EVENT_TID_SEL_NUM = 30 ;
+static const uint8_t P9N2_EX_L2_MODE_REG1_PM47_L23_EVENT_TID_SEL_NUM_LEN = 2 ;
+static const uint8_t P9N2_EX_L2_MODE_REG1_SYSMAP_PB_CHIP_ADDR_EXT_MASK_EN = 32 ;
+static const uint8_t P9N2_EX_L2_MODE_REG1_SYSMAP_PB_CHIP_ADDR_EXT_MASK_EN_LEN = 7 ;
+
+static const uint8_t P9N2_EX_L3_MODE_REG1_L3_LCO_ENABLE_CFG = 0 ;
+static const uint8_t P9N2_EX_L3_MODE_REG1_L3_LCO_TARGET_GROUP = 1 ;
+static const uint8_t P9N2_EX_L3_MODE_REG1_L3_LCO_TARGET_ID = 2 ;
+static const uint8_t P9N2_EX_L3_MODE_REG1_L3_LCO_TARGET_ID_LEN = 4 ;
+static const uint8_t P9N2_EX_L3_MODE_REG1_L3_LCO_TARGET_VICTIMS = 6 ;
+static const uint8_t P9N2_EX_L3_MODE_REG1_L3_LCO_TARGET_VICTIMS_LEN = 16 ;
+static const uint8_t P9N2_EX_L3_MODE_REG1_L3_SCOM_CINJ_LCO_DIS = 22 ;
+
+static const uint8_t P9N2_EQ_MULTICAST_GROUP_1_MULTICAST1 = 3 ;
+static const uint8_t P9N2_EQ_MULTICAST_GROUP_1_MULTICAST1_LEN = 3 ;
+
+static const uint8_t P9N2_EX_MULTICAST_GROUP_1_MULTICAST1 = 3 ;
+static const uint8_t P9N2_EX_MULTICAST_GROUP_1_MULTICAST1_LEN = 3 ;
+
+static const uint8_t P9N2_C_MULTICAST_GROUP_1_MULTICAST1 = 3 ;
+static const uint8_t P9N2_C_MULTICAST_GROUP_1_MULTICAST1_LEN = 3 ;
+
+static const uint8_t P9N2_EQ_MULTICAST_GROUP_2_MULTICAST2 = 3 ;
+static const uint8_t P9N2_EQ_MULTICAST_GROUP_2_MULTICAST2_LEN = 3 ;
+
+static const uint8_t P9N2_EX_MULTICAST_GROUP_2_MULTICAST2 = 3 ;
+static const uint8_t P9N2_EX_MULTICAST_GROUP_2_MULTICAST2_LEN = 3 ;
+
+static const uint8_t P9N2_C_MULTICAST_GROUP_2_MULTICAST2 = 3 ;
+static const uint8_t P9N2_C_MULTICAST_GROUP_2_MULTICAST2_LEN = 3 ;
+
+static const uint8_t P9N2_EQ_MULTICAST_GROUP_3_MULTICAST3 = 3 ;
+static const uint8_t P9N2_EQ_MULTICAST_GROUP_3_MULTICAST3_LEN = 3 ;
+
+static const uint8_t P9N2_EX_MULTICAST_GROUP_3_MULTICAST3 = 3 ;
+static const uint8_t P9N2_EX_MULTICAST_GROUP_3_MULTICAST3_LEN = 3 ;
+
+static const uint8_t P9N2_C_MULTICAST_GROUP_3_MULTICAST3 = 3 ;
+static const uint8_t P9N2_C_MULTICAST_GROUP_3_MULTICAST3_LEN = 3 ;
+
+static const uint8_t P9N2_EQ_MULTICAST_GROUP_4_MULTICAST4 = 3 ;
+static const uint8_t P9N2_EQ_MULTICAST_GROUP_4_MULTICAST4_LEN = 3 ;
+
+static const uint8_t P9N2_EX_MULTICAST_GROUP_4_MULTICAST4 = 3 ;
+static const uint8_t P9N2_EX_MULTICAST_GROUP_4_MULTICAST4_LEN = 3 ;
+
+static const uint8_t P9N2_C_MULTICAST_GROUP_4_MULTICAST4 = 3 ;
+static const uint8_t P9N2_C_MULTICAST_GROUP_4_MULTICAST4_LEN = 3 ;
+
+static const uint8_t P9N2_EQ_NCU_DARN_BAR_REG_EN = 0 ;
+static const uint8_t P9N2_EQ_NCU_DARN_BAR_REG_ADDR = 8 ;
+static const uint8_t P9N2_EQ_NCU_DARN_BAR_REG_ADDR_LEN = 44 ;
+
+static const uint8_t P9N2_EX_NCU_DARN_BAR_REG_EN = 0 ;
+static const uint8_t P9N2_EX_NCU_DARN_BAR_REG_ADDR = 8 ;
+static const uint8_t P9N2_EX_NCU_DARN_BAR_REG_ADDR_LEN = 44 ;
+
+static const uint8_t P9N2_EQ_NCU_MODE_REG_HTM_QUEUE_LIMIT = 0 ;
+static const uint8_t P9N2_EQ_NCU_MODE_REG_HTM_QUEUE_LIMIT_LEN = 2 ;
+static const uint8_t P9N2_EQ_NCU_MODE_REG_TRASH_EN = 2 ;
+static const uint8_t P9N2_EQ_NCU_MODE_REG_FENCE_TLBIE = 3 ;
+static const uint8_t P9N2_EQ_NCU_MODE_REG_DROP_PRIORITY_MASK = 4 ;
+static const uint8_t P9N2_EQ_NCU_MODE_REG_DROP_PRIORITY_MASK_LEN = 3 ;
+static const uint8_t P9N2_EQ_NCU_MODE_REG_TLBI_GROUP_PUMP_EN = 7 ;
+static const uint8_t P9N2_EQ_NCU_MODE_REG_SLBI_GROUP_PUMP_EN = 8 ;
+static const uint8_t P9N2_EQ_NCU_MODE_REG_SYSMAP_SM_NOT_LG_SEL = 9 ;
+static const uint8_t P9N2_EQ_NCU_MODE_REG_TLBIE_PACING_CNT_EN = 10 ;
+static const uint8_t P9N2_EQ_NCU_MODE_REG_TLBIE_DEC_RATE = 11 ;
+static const uint8_t P9N2_EQ_NCU_MODE_REG_TLBIE_DEC_RATE_LEN = 8 ;
+static const uint8_t P9N2_EQ_NCU_MODE_REG_TLBIE_INC_RATE = 19 ;
+static const uint8_t P9N2_EQ_NCU_MODE_REG_TLBIE_INC_RATE_LEN = 8 ;
+static const uint8_t P9N2_EQ_NCU_MODE_REG_TLBIE_CNT_THRESH = 27 ;
+static const uint8_t P9N2_EQ_NCU_MODE_REG_TLBIE_CNT_THRESH_LEN = 8 ;
+static const uint8_t P9N2_EQ_NCU_MODE_REG_TLBIE_CNT_WT4TX_CORE_EN = 35 ;
+static const uint8_t P9N2_EQ_NCU_MODE_REG_TLB_CHK_WAIT_DEC = 36 ;
+static const uint8_t P9N2_EQ_NCU_MODE_REG_TLB_CHK_WAIT_DEC_LEN = 8 ;
+static const uint8_t P9N2_EQ_NCU_MODE_REG_SYSMAP_PB_CHIP_ADDR_EXT_MASK_EN = 44 ;
+static const uint8_t P9N2_EQ_NCU_MODE_REG_SYSMAP_PB_CHIP_ADDR_EXT_MASK_EN_LEN = 7 ;
+static const uint8_t P9N2_EQ_NCU_MODE_REG_SKIP_GRP_SCOPE_EN = 51 ;
+
+static const uint8_t P9N2_EX_NCU_MODE_REG_HTM_QUEUE_LIMIT = 0 ;
+static const uint8_t P9N2_EX_NCU_MODE_REG_HTM_QUEUE_LIMIT_LEN = 2 ;
+static const uint8_t P9N2_EX_NCU_MODE_REG_TRASH_EN = 2 ;
+static const uint8_t P9N2_EX_NCU_MODE_REG_FENCE_TLBIE = 3 ;
+static const uint8_t P9N2_EX_NCU_MODE_REG_DROP_PRIORITY_MASK = 4 ;
+static const uint8_t P9N2_EX_NCU_MODE_REG_DROP_PRIORITY_MASK_LEN = 3 ;
+static const uint8_t P9N2_EX_NCU_MODE_REG_TLBI_GROUP_PUMP_EN = 7 ;
+static const uint8_t P9N2_EX_NCU_MODE_REG_SLBI_GROUP_PUMP_EN = 8 ;
+static const uint8_t P9N2_EX_NCU_MODE_REG_SYSMAP_SM_NOT_LG_SEL = 9 ;
+static const uint8_t P9N2_EX_NCU_MODE_REG_TLBIE_PACING_CNT_EN = 10 ;
+static const uint8_t P9N2_EX_NCU_MODE_REG_TLBIE_DEC_RATE = 11 ;
+static const uint8_t P9N2_EX_NCU_MODE_REG_TLBIE_DEC_RATE_LEN = 8 ;
+static const uint8_t P9N2_EX_NCU_MODE_REG_TLBIE_INC_RATE = 19 ;
+static const uint8_t P9N2_EX_NCU_MODE_REG_TLBIE_INC_RATE_LEN = 8 ;
+static const uint8_t P9N2_EX_NCU_MODE_REG_TLBIE_CNT_THRESH = 27 ;
+static const uint8_t P9N2_EX_NCU_MODE_REG_TLBIE_CNT_THRESH_LEN = 8 ;
+static const uint8_t P9N2_EX_NCU_MODE_REG_TLBIE_CNT_WT4TX_CORE_EN = 35 ;
+static const uint8_t P9N2_EX_NCU_MODE_REG_TLB_CHK_WAIT_DEC = 36 ;
+static const uint8_t P9N2_EX_NCU_MODE_REG_TLB_CHK_WAIT_DEC_LEN = 8 ;
+static const uint8_t P9N2_EX_NCU_MODE_REG_SYSMAP_PB_CHIP_ADDR_EXT_MASK_EN = 44 ;
+static const uint8_t P9N2_EX_NCU_MODE_REG_SYSMAP_PB_CHIP_ADDR_EXT_MASK_EN_LEN = 7 ;
+static const uint8_t P9N2_EX_NCU_MODE_REG_SKIP_GRP_SCOPE_EN = 51 ;
+
+static const uint8_t P9N2_EQ_NCU_MODE_REG2_HANG_POLL_PULSE_DIV = 0 ;
+static const uint8_t P9N2_EQ_NCU_MODE_REG2_HANG_POLL_PULSE_DIV_LEN = 4 ;
+static const uint8_t P9N2_EQ_NCU_MODE_REG2_MASTER_CP_DATA_POLL_PULSE_DIV = 4 ;
+static const uint8_t P9N2_EQ_NCU_MODE_REG2_MASTER_CP_DATA_POLL_PULSE_DIV_LEN = 4 ;
+static const uint8_t P9N2_EQ_NCU_MODE_REG2_TLB_SNOOP_DATA_POLL_PULSE_DIV = 8 ;
+static const uint8_t P9N2_EQ_NCU_MODE_REG2_TLB_SNOOP_DATA_POLL_PULSE_DIV_LEN = 10 ;
+static const uint8_t P9N2_EQ_NCU_MODE_REG2_TLB_STG1_HANG_POLL_PULSE_DIV = 18 ;
+static const uint8_t P9N2_EQ_NCU_MODE_REG2_TLB_STG1_HANG_POLL_PULSE_DIV_LEN = 4 ;
+static const uint8_t P9N2_EQ_NCU_MODE_REG2_TLB_STG2_HANG_POLL_PULSE_DIV = 22 ;
+static const uint8_t P9N2_EQ_NCU_MODE_REG2_TLB_STG2_HANG_POLL_PULSE_DIV_LEN = 4 ;
+static const uint8_t P9N2_EQ_NCU_MODE_REG2_MASTER_TLB_DATA_POLL_PULSE_DIV = 26 ;
+static const uint8_t P9N2_EQ_NCU_MODE_REG2_MASTER_TLB_DATA_POLL_PULSE_DIV_LEN = 10 ;
+
+static const uint8_t P9N2_EX_NCU_MODE_REG2_HANG_POLL_PULSE_DIV = 0 ;
+static const uint8_t P9N2_EX_NCU_MODE_REG2_HANG_POLL_PULSE_DIV_LEN = 4 ;
+static const uint8_t P9N2_EX_NCU_MODE_REG2_MASTER_CP_DATA_POLL_PULSE_DIV = 4 ;
+static const uint8_t P9N2_EX_NCU_MODE_REG2_MASTER_CP_DATA_POLL_PULSE_DIV_LEN = 4 ;
+static const uint8_t P9N2_EX_NCU_MODE_REG2_TLB_SNOOP_DATA_POLL_PULSE_DIV = 8 ;
+static const uint8_t P9N2_EX_NCU_MODE_REG2_TLB_SNOOP_DATA_POLL_PULSE_DIV_LEN = 10 ;
+static const uint8_t P9N2_EX_NCU_MODE_REG2_TLB_STG1_HANG_POLL_PULSE_DIV = 18 ;
+static const uint8_t P9N2_EX_NCU_MODE_REG2_TLB_STG1_HANG_POLL_PULSE_DIV_LEN = 4 ;
+static const uint8_t P9N2_EX_NCU_MODE_REG2_TLB_STG2_HANG_POLL_PULSE_DIV = 22 ;
+static const uint8_t P9N2_EX_NCU_MODE_REG2_TLB_STG2_HANG_POLL_PULSE_DIV_LEN = 4 ;
+static const uint8_t P9N2_EX_NCU_MODE_REG2_MASTER_TLB_DATA_POLL_PULSE_DIV = 26 ;
+static const uint8_t P9N2_EX_NCU_MODE_REG2_MASTER_TLB_DATA_POLL_PULSE_DIV_LEN = 10 ;
+
+static const uint8_t P9N2_EQ_NCU_MODE_REG3_TLBIE_STALL_EN = 0 ;
+static const uint8_t P9N2_EQ_NCU_MODE_REG3_TLBIE_STALL_THRESHOLD = 1 ;
+static const uint8_t P9N2_EQ_NCU_MODE_REG3_TLBIE_STALL_THRESHOLD_LEN = 3 ;
+static const uint8_t P9N2_EQ_NCU_MODE_REG3_TLBIE_STALL_CMPLT_CNT = 4 ;
+static const uint8_t P9N2_EQ_NCU_MODE_REG3_TLBIE_STALL_CMPLT_CNT_LEN = 4 ;
+static const uint8_t P9N2_EQ_NCU_MODE_REG3_TLBIE_STALL_DELAY_CNT = 8 ;
+static const uint8_t P9N2_EQ_NCU_MODE_REG3_TLBIE_STALL_DELAY_CNT_LEN = 8 ;
+static const uint8_t P9N2_EQ_NCU_MODE_REG3_TLBIE_PACING_MST_DLY_EN = 16 ;
+static const uint8_t P9N2_EQ_NCU_MODE_REG3_TLBIE_PACING_PMU_THRESH = 17 ;
+static const uint8_t P9N2_EQ_NCU_MODE_REG3_TLBIE_PACING_PMU_THRESH_LEN = 3 ;
+static const uint8_t P9N2_EQ_NCU_MODE_REG3_SMF_CONFIG = 20 ;
+static const uint8_t P9N2_EQ_NCU_MODE_REG3_SMF_CONFIG_LEN = 2 ;
+static const uint8_t P9N2_EQ_NCU_MODE_REG3_SPARE = 22 ;
+static const uint8_t P9N2_EQ_NCU_MODE_REG3_SPARE_LEN = 10 ;
+
+static const uint8_t P9N2_EX_NCU_MODE_REG3_TLBIE_STALL_EN = 0 ;
+static const uint8_t P9N2_EX_NCU_MODE_REG3_TLBIE_STALL_THRESHOLD = 1 ;
+static const uint8_t P9N2_EX_NCU_MODE_REG3_TLBIE_STALL_THRESHOLD_LEN = 3 ;
+static const uint8_t P9N2_EX_NCU_MODE_REG3_TLBIE_STALL_CMPLT_CNT = 4 ;
+static const uint8_t P9N2_EX_NCU_MODE_REG3_TLBIE_STALL_CMPLT_CNT_LEN = 4 ;
+static const uint8_t P9N2_EX_NCU_MODE_REG3_TLBIE_STALL_DELAY_CNT = 8 ;
+static const uint8_t P9N2_EX_NCU_MODE_REG3_TLBIE_STALL_DELAY_CNT_LEN = 8 ;
+static const uint8_t P9N2_EX_NCU_MODE_REG3_TLBIE_PACING_MST_DLY_EN = 16 ;
+static const uint8_t P9N2_EX_NCU_MODE_REG3_TLBIE_PACING_PMU_THRESH = 17 ;
+static const uint8_t P9N2_EX_NCU_MODE_REG3_TLBIE_PACING_PMU_THRESH_LEN = 3 ;
+static const uint8_t P9N2_EX_NCU_MODE_REG3_SMF_CONFIG = 20 ;
+static const uint8_t P9N2_EX_NCU_MODE_REG3_SMF_CONFIG_LEN = 2 ;
+static const uint8_t P9N2_EX_NCU_MODE_REG3_SPARE = 22 ;
+static const uint8_t P9N2_EX_NCU_MODE_REG3_SPARE_LEN = 10 ;
+
+static const uint8_t P9N2_EQ_NCU_SLOW_LPAR_REG0_DELAY8_VALID = 0 ;
+static const uint8_t P9N2_EQ_NCU_SLOW_LPAR_REG0_DELAY8_ID = 1 ;
+static const uint8_t P9N2_EQ_NCU_SLOW_LPAR_REG0_DELAY8_ID_LEN = 12 ;
+static const uint8_t P9N2_EQ_NCU_SLOW_LPAR_REG0_DELAY7_VALID = 13 ;
+static const uint8_t P9N2_EQ_NCU_SLOW_LPAR_REG0_DELAY7_ID = 14 ;
+static const uint8_t P9N2_EQ_NCU_SLOW_LPAR_REG0_DELAY7_ID_LEN = 12 ;
+static const uint8_t P9N2_EQ_NCU_SLOW_LPAR_REG0_DELAY6_VALID = 26 ;
+static const uint8_t P9N2_EQ_NCU_SLOW_LPAR_REG0_DELAY6_ID = 27 ;
+static const uint8_t P9N2_EQ_NCU_SLOW_LPAR_REG0_DELAY6_ID_LEN = 12 ;
+static const uint8_t P9N2_EQ_NCU_SLOW_LPAR_REG0_DELAY5_VALID = 39 ;
+static const uint8_t P9N2_EQ_NCU_SLOW_LPAR_REG0_DELAY5_ID = 40 ;
+static const uint8_t P9N2_EQ_NCU_SLOW_LPAR_REG0_DELAY5_ID_LEN = 12 ;
+
+static const uint8_t P9N2_EX_NCU_SLOW_LPAR_REG0_DELAY8_VALID = 0 ;
+static const uint8_t P9N2_EX_NCU_SLOW_LPAR_REG0_DELAY8_ID = 1 ;
+static const uint8_t P9N2_EX_NCU_SLOW_LPAR_REG0_DELAY8_ID_LEN = 12 ;
+static const uint8_t P9N2_EX_NCU_SLOW_LPAR_REG0_DELAY7_VALID = 13 ;
+static const uint8_t P9N2_EX_NCU_SLOW_LPAR_REG0_DELAY7_ID = 14 ;
+static const uint8_t P9N2_EX_NCU_SLOW_LPAR_REG0_DELAY7_ID_LEN = 12 ;
+static const uint8_t P9N2_EX_NCU_SLOW_LPAR_REG0_DELAY6_VALID = 26 ;
+static const uint8_t P9N2_EX_NCU_SLOW_LPAR_REG0_DELAY6_ID = 27 ;
+static const uint8_t P9N2_EX_NCU_SLOW_LPAR_REG0_DELAY6_ID_LEN = 12 ;
+static const uint8_t P9N2_EX_NCU_SLOW_LPAR_REG0_DELAY5_VALID = 39 ;
+static const uint8_t P9N2_EX_NCU_SLOW_LPAR_REG0_DELAY5_ID = 40 ;
+static const uint8_t P9N2_EX_NCU_SLOW_LPAR_REG0_DELAY5_ID_LEN = 12 ;
+
+static const uint8_t P9N2_EQ_NCU_SLOW_LPAR_REG1_DELAY4_VALID = 0 ;
+static const uint8_t P9N2_EQ_NCU_SLOW_LPAR_REG1_DELAY4_ID = 1 ;
+static const uint8_t P9N2_EQ_NCU_SLOW_LPAR_REG1_DELAY4_ID_LEN = 12 ;
+static const uint8_t P9N2_EQ_NCU_SLOW_LPAR_REG1_DELAY3_VALID = 13 ;
+static const uint8_t P9N2_EQ_NCU_SLOW_LPAR_REG1_DELAY3_ID = 14 ;
+static const uint8_t P9N2_EQ_NCU_SLOW_LPAR_REG1_DELAY3_ID_LEN = 12 ;
+static const uint8_t P9N2_EQ_NCU_SLOW_LPAR_REG1_DELAY2_VALID = 26 ;
+static const uint8_t P9N2_EQ_NCU_SLOW_LPAR_REG1_DELAY2_ID = 27 ;
+static const uint8_t P9N2_EQ_NCU_SLOW_LPAR_REG1_DELAY2_ID_LEN = 12 ;
+static const uint8_t P9N2_EQ_NCU_SLOW_LPAR_REG1_DELAY1_VALID = 39 ;
+static const uint8_t P9N2_EQ_NCU_SLOW_LPAR_REG1_DELAY1_ID = 40 ;
+static const uint8_t P9N2_EQ_NCU_SLOW_LPAR_REG1_DELAY1_ID_LEN = 12 ;
+
+static const uint8_t P9N2_EX_NCU_SLOW_LPAR_REG1_DELAY4_VALID = 0 ;
+static const uint8_t P9N2_EX_NCU_SLOW_LPAR_REG1_DELAY4_ID = 1 ;
+static const uint8_t P9N2_EX_NCU_SLOW_LPAR_REG1_DELAY4_ID_LEN = 12 ;
+static const uint8_t P9N2_EX_NCU_SLOW_LPAR_REG1_DELAY3_VALID = 13 ;
+static const uint8_t P9N2_EX_NCU_SLOW_LPAR_REG1_DELAY3_ID = 14 ;
+static const uint8_t P9N2_EX_NCU_SLOW_LPAR_REG1_DELAY3_ID_LEN = 12 ;
+static const uint8_t P9N2_EX_NCU_SLOW_LPAR_REG1_DELAY2_VALID = 26 ;
+static const uint8_t P9N2_EX_NCU_SLOW_LPAR_REG1_DELAY2_ID = 27 ;
+static const uint8_t P9N2_EX_NCU_SLOW_LPAR_REG1_DELAY2_ID_LEN = 12 ;
+static const uint8_t P9N2_EX_NCU_SLOW_LPAR_REG1_DELAY1_VALID = 39 ;
+static const uint8_t P9N2_EX_NCU_SLOW_LPAR_REG1_DELAY1_ID = 40 ;
+static const uint8_t P9N2_EX_NCU_SLOW_LPAR_REG1_DELAY1_ID_LEN = 12 ;
+
+static const uint8_t P9N2_EQ_NCU_SPEC_BAR_REG_EN = 0 ;
+static const uint8_t P9N2_EQ_NCU_SPEC_BAR_REG_256K = 1 ;
+static const uint8_t P9N2_EQ_NCU_SPEC_BAR_REG_ADDR = 8 ;
+static const uint8_t P9N2_EQ_NCU_SPEC_BAR_REG_ADDR_LEN = 42 ;
+
+static const uint8_t P9N2_EX_NCU_SPEC_BAR_REG_EN = 0 ;
+static const uint8_t P9N2_EX_NCU_SPEC_BAR_REG_256K = 1 ;
+static const uint8_t P9N2_EX_NCU_SPEC_BAR_REG_ADDR = 8 ;
+static const uint8_t P9N2_EX_NCU_SPEC_BAR_REG_ADDR_LEN = 42 ;
+
+static const uint8_t P9N2_EQ_NCU_STATUS_REG_CORE0_REQ_ACTIVE = 0 ;
+static const uint8_t P9N2_EQ_NCU_STATUS_REG_CORE1_REQ_ACTIVE = 1 ;
+static const uint8_t P9N2_EQ_NCU_STATUS_REG_CORE_OR_SNP_REQ_ACTIVE = 2 ;
+static const uint8_t P9N2_EQ_NCU_STATUS_REG_ANY_REQ_ACTIVE = 3 ;
+
+static const uint8_t P9N2_EX_NCU_STATUS_REG_CORE0_REQ_ACTIVE = 0 ;
+static const uint8_t P9N2_EX_NCU_STATUS_REG_CORE1_REQ_ACTIVE = 1 ;
+static const uint8_t P9N2_EX_NCU_STATUS_REG_CORE_OR_SNP_REQ_ACTIVE = 2 ;
+static const uint8_t P9N2_EX_NCU_STATUS_REG_ANY_REQ_ACTIVE = 3 ;
+
+static const uint8_t P9N2_EQ_NET_CTRL0_CHIPLET_ENABLE = 0 ;
+static const uint8_t P9N2_EQ_NET_CTRL0_PCB_EP_RESET = 1 ;
+static const uint8_t P9N2_EQ_NET_CTRL0_CLK_ASYNC_RESET = 2 ;
+static const uint8_t P9N2_EQ_NET_CTRL0_PLL_TEST_EN = 3 ;
+static const uint8_t P9N2_EQ_NET_CTRL0_PLL_RESET = 4 ;
+static const uint8_t P9N2_EQ_NET_CTRL0_PLL_BYPASS = 5 ;
+static const uint8_t P9N2_EQ_NET_CTRL0_VITAL_SCAN = 6 ;
+static const uint8_t P9N2_EQ_NET_CTRL0_VITAL_SCAN_IN = 7 ;
+static const uint8_t P9N2_EQ_NET_CTRL0_VITAL_PHASE = 8 ;
+static const uint8_t P9N2_EQ_NET_CTRL0_FLUSH_ALIGN_OVR = 9 ;
+static const uint8_t P9N2_EQ_NET_CTRL0_VITAL_AL = 10 ;
+static const uint8_t P9N2_EQ_NET_CTRL0_ACT_DIS = 11 ;
+static const uint8_t P9N2_EQ_NET_CTRL0_MPW1 = 12 ;
+static const uint8_t P9N2_EQ_NET_CTRL0_MPW2 = 13 ;
+static const uint8_t P9N2_EQ_NET_CTRL0_MPW3 = 14 ;
+static const uint8_t P9N2_EQ_NET_CTRL0_DELAY_LCLKR = 15 ;
+static const uint8_t P9N2_EQ_NET_CTRL0_VITAL_THOLD = 16 ;
+static const uint8_t P9N2_EQ_NET_CTRL0_FLUSH_SCAN_N = 17 ;
+static const uint8_t P9N2_EQ_NET_CTRL0_FENCE_EN = 18 ;
+static const uint8_t P9N2_EQ_NET_CTRL0_CPLT_RCTRL = 19 ;
+static const uint8_t P9N2_EQ_NET_CTRL0_CPLT_DCTRL = 20 ;
+static const uint8_t P9N2_EQ_NET_CTRL0_ADJ_FUNC_CLKSEL = 22 ;
+static const uint8_t P9N2_EQ_NET_CTRL0_TP_FENCE_PCB = 25 ;
+static const uint8_t P9N2_EQ_NET_CTRL0_LVLTRANS_FENCE = 26 ;
+static const uint8_t P9N2_EQ_NET_CTRL0_ARRAY_WRITE_ASSIST_EN = 27 ;
+static const uint8_t P9N2_EQ_NET_CTRL0_HTB_INTEST = 28 ;
+static const uint8_t P9N2_EQ_NET_CTRL0_HTB_EXTEST = 29 ;
+static const uint8_t P9N2_EQ_NET_CTRL0_PM_ACCESS = 30 ;
+static const uint8_t P9N2_EQ_NET_CTRL0_PLLFORCE_OUT_EN = 31 ;
+
+static const uint8_t P9N2_EX_NET_CTRL0_CHIPLET_ENABLE = 0 ;
+static const uint8_t P9N2_EX_NET_CTRL0_PCB_EP_RESET = 1 ;
+static const uint8_t P9N2_EX_NET_CTRL0_CLK_ASYNC_RESET = 2 ;
+static const uint8_t P9N2_EX_NET_CTRL0_PLL_TEST_EN = 3 ;
+static const uint8_t P9N2_EX_NET_CTRL0_PLL_RESET = 4 ;
+static const uint8_t P9N2_EX_NET_CTRL0_PLL_BYPASS = 5 ;
+static const uint8_t P9N2_EX_NET_CTRL0_VITAL_SCAN = 6 ;
+static const uint8_t P9N2_EX_NET_CTRL0_VITAL_SCAN_IN = 7 ;
+static const uint8_t P9N2_EX_NET_CTRL0_VITAL_PHASE = 8 ;
+static const uint8_t P9N2_EX_NET_CTRL0_FLUSH_ALIGN_OVR = 9 ;
+static const uint8_t P9N2_EX_NET_CTRL0_VITAL_AL = 10 ;
+static const uint8_t P9N2_EX_NET_CTRL0_ACT_DIS = 11 ;
+static const uint8_t P9N2_EX_NET_CTRL0_MPW1 = 12 ;
+static const uint8_t P9N2_EX_NET_CTRL0_MPW2 = 13 ;
+static const uint8_t P9N2_EX_NET_CTRL0_MPW3 = 14 ;
+static const uint8_t P9N2_EX_NET_CTRL0_DELAY_LCLKR = 15 ;
+static const uint8_t P9N2_EX_NET_CTRL0_VITAL_THOLD = 16 ;
+static const uint8_t P9N2_EX_NET_CTRL0_FLUSH_SCAN_N = 17 ;
+static const uint8_t P9N2_EX_NET_CTRL0_FENCE_EN = 18 ;
+static const uint8_t P9N2_EX_NET_CTRL0_CPLT_RCTRL = 19 ;
+static const uint8_t P9N2_EX_NET_CTRL0_CPLT_DCTRL = 20 ;
+static const uint8_t P9N2_EX_NET_CTRL0_ADJ_FUNC_CLKSEL = 22 ;
+static const uint8_t P9N2_EX_NET_CTRL0_TP_FENCE_PCB = 25 ;
+static const uint8_t P9N2_EX_NET_CTRL0_LVLTRANS_FENCE = 26 ;
+static const uint8_t P9N2_EX_NET_CTRL0_ARRAY_WRITE_ASSIST_EN = 27 ;
+static const uint8_t P9N2_EX_NET_CTRL0_HTB_INTEST = 28 ;
+static const uint8_t P9N2_EX_NET_CTRL0_HTB_EXTEST = 29 ;
+static const uint8_t P9N2_EX_NET_CTRL0_PM_ACCESS = 30 ;
+static const uint8_t P9N2_EX_NET_CTRL0_PLLFORCE_OUT_EN = 31 ;
+
+static const uint8_t P9N2_C_NET_CTRL0_CHIPLET_ENABLE = 0 ;
+static const uint8_t P9N2_C_NET_CTRL0_PCB_EP_RESET = 1 ;
+static const uint8_t P9N2_C_NET_CTRL0_CLK_ASYNC_RESET = 2 ;
+static const uint8_t P9N2_C_NET_CTRL0_PLL_TEST_EN = 3 ;
+static const uint8_t P9N2_C_NET_CTRL0_PLL_RESET = 4 ;
+static const uint8_t P9N2_C_NET_CTRL0_PLL_BYPASS = 5 ;
+static const uint8_t P9N2_C_NET_CTRL0_VITAL_SCAN = 6 ;
+static const uint8_t P9N2_C_NET_CTRL0_VITAL_SCAN_IN = 7 ;
+static const uint8_t P9N2_C_NET_CTRL0_VITAL_PHASE = 8 ;
+static const uint8_t P9N2_C_NET_CTRL0_FLUSH_ALIGN_OVR = 9 ;
+static const uint8_t P9N2_C_NET_CTRL0_VITAL_AL = 10 ;
+static const uint8_t P9N2_C_NET_CTRL0_ACT_DIS = 11 ;
+static const uint8_t P9N2_C_NET_CTRL0_MPW1 = 12 ;
+static const uint8_t P9N2_C_NET_CTRL0_MPW2 = 13 ;
+static const uint8_t P9N2_C_NET_CTRL0_MPW3 = 14 ;
+static const uint8_t P9N2_C_NET_CTRL0_DELAY_LCLKR = 15 ;
+static const uint8_t P9N2_C_NET_CTRL0_VITAL_THOLD = 16 ;
+static const uint8_t P9N2_C_NET_CTRL0_FLUSH_SCAN_N = 17 ;
+static const uint8_t P9N2_C_NET_CTRL0_FENCE_EN = 18 ;
+static const uint8_t P9N2_C_NET_CTRL0_CPLT_RCTRL = 19 ;
+static const uint8_t P9N2_C_NET_CTRL0_CPLT_DCTRL = 20 ;
+static const uint8_t P9N2_C_NET_CTRL0_ADJ_FUNC_CLKSEL = 22 ;
+static const uint8_t P9N2_C_NET_CTRL0_TP_FENCE_PCB = 25 ;
+static const uint8_t P9N2_C_NET_CTRL0_LVLTRANS_FENCE = 26 ;
+static const uint8_t P9N2_C_NET_CTRL0_ARRAY_WRITE_ASSIST_EN = 27 ;
+static const uint8_t P9N2_C_NET_CTRL0_HTB_INTEST = 28 ;
+static const uint8_t P9N2_C_NET_CTRL0_HTB_EXTEST = 29 ;
+static const uint8_t P9N2_C_NET_CTRL0_PM_ACCESS = 30 ;
+static const uint8_t P9N2_C_NET_CTRL0_PLLFORCE_OUT_EN = 31 ;
+
+static const uint8_t P9N2_EQ_NET_CTRL1_PLL_CLKIN_SEL = 0 ;
+static const uint8_t P9N2_EQ_NET_CTRL1_CLK_DCC_BYPASS_EN = 1 ;
+static const uint8_t P9N2_EQ_NET_CTRL1_CLK_PDLY_BYPASS_EN = 2 ;
+static const uint8_t P9N2_EQ_NET_CTRL1_CLK_DIV_BYPASS_EN = 3 ;
+static const uint8_t P9N2_EQ_NET_CTRL1_REFCLK_CLKMUX0_SEL = 4 ;
+static const uint8_t P9N2_EQ_NET_CTRL1_REFCLK_CLKMUX1_SEL = 5 ;
+static const uint8_t P9N2_EQ_NET_CTRL1_PLL_BNDY_BYPASS_EN = 6 ;
+static const uint8_t P9N2_EQ_NET_CTRL1_DPLL_TEST_SEL = 8 ;
+static const uint8_t P9N2_EQ_NET_CTRL1_DPLL_TEST_SEL_LEN = 8 ;
+static const uint8_t P9N2_EQ_NET_CTRL1_SB_STRENGTH = 16 ;
+static const uint8_t P9N2_EQ_NET_CTRL1_SB_STRENGTH_LEN = 4 ;
+static const uint8_t P9N2_EQ_NET_CTRL1_ASYNC_TYPE = 20 ;
+static const uint8_t P9N2_EQ_NET_CTRL1_ASYNC_OBS = 21 ;
+static const uint8_t P9N2_EQ_NET_CTRL1_CPM_CAL_SET = 22 ;
+static const uint8_t P9N2_EQ_NET_CTRL1_SENSEADJ_RESET0 = 23 ;
+static const uint8_t P9N2_EQ_NET_CTRL1_SENSEADJ_RESET1 = 24 ;
+static const uint8_t P9N2_EQ_NET_CTRL1_CLK_PULSE_EN = 25 ;
+static const uint8_t P9N2_EQ_NET_CTRL1_CLK_PULSE_MODE = 26 ;
+static const uint8_t P9N2_EQ_NET_CTRL1_CLK_PULSE_MODE_LEN = 2 ;
+static const uint8_t P9N2_EQ_NET_CTRL1_PCB_ACCESS = 28 ;
+static const uint8_t P9N2_EQ_NET_CTRL1_PCB_ACCESS_LEN = 4 ;
+
+static const uint8_t P9N2_EX_NET_CTRL1_PLL_CLKIN_SEL = 0 ;
+static const uint8_t P9N2_EX_NET_CTRL1_CLK_DCC_BYPASS_EN = 1 ;
+static const uint8_t P9N2_EX_NET_CTRL1_CLK_PDLY_BYPASS_EN = 2 ;
+static const uint8_t P9N2_EX_NET_CTRL1_CLK_DIV_BYPASS_EN = 3 ;
+static const uint8_t P9N2_EX_NET_CTRL1_REFCLK_CLKMUX0_SEL = 4 ;
+static const uint8_t P9N2_EX_NET_CTRL1_REFCLK_CLKMUX1_SEL = 5 ;
+static const uint8_t P9N2_EX_NET_CTRL1_PLL_BNDY_BYPASS_EN = 6 ;
+static const uint8_t P9N2_EX_NET_CTRL1_DPLL_TEST_SEL = 8 ;
+static const uint8_t P9N2_EX_NET_CTRL1_DPLL_TEST_SEL_LEN = 8 ;
+static const uint8_t P9N2_EX_NET_CTRL1_SB_STRENGTH = 16 ;
+static const uint8_t P9N2_EX_NET_CTRL1_SB_STRENGTH_LEN = 4 ;
+static const uint8_t P9N2_EX_NET_CTRL1_ASYNC_TYPE = 20 ;
+static const uint8_t P9N2_EX_NET_CTRL1_ASYNC_OBS = 21 ;
+static const uint8_t P9N2_EX_NET_CTRL1_CPM_CAL_SET = 22 ;
+static const uint8_t P9N2_EX_NET_CTRL1_SENSEADJ_RESET0 = 23 ;
+static const uint8_t P9N2_EX_NET_CTRL1_SENSEADJ_RESET1 = 24 ;
+static const uint8_t P9N2_EX_NET_CTRL1_CLK_PULSE_EN = 25 ;
+static const uint8_t P9N2_EX_NET_CTRL1_CLK_PULSE_MODE = 26 ;
+static const uint8_t P9N2_EX_NET_CTRL1_CLK_PULSE_MODE_LEN = 2 ;
+static const uint8_t P9N2_EX_NET_CTRL1_PCB_ACCESS = 28 ;
+static const uint8_t P9N2_EX_NET_CTRL1_PCB_ACCESS_LEN = 4 ;
+
+static const uint8_t P9N2_C_NET_CTRL1_PLL_CLKIN_SEL = 0 ;
+static const uint8_t P9N2_C_NET_CTRL1_CLK_DCC_BYPASS_EN = 1 ;
+static const uint8_t P9N2_C_NET_CTRL1_CLK_PDLY_BYPASS_EN = 2 ;
+static const uint8_t P9N2_C_NET_CTRL1_CLK_DIV_BYPASS_EN = 3 ;
+static const uint8_t P9N2_C_NET_CTRL1_REFCLK_CLKMUX0_SEL = 4 ;
+static const uint8_t P9N2_C_NET_CTRL1_REFCLK_CLKMUX1_SEL = 5 ;
+static const uint8_t P9N2_C_NET_CTRL1_PLL_BNDY_BYPASS_EN = 6 ;
+static const uint8_t P9N2_C_NET_CTRL1_DPLL_TEST_SEL = 8 ;
+static const uint8_t P9N2_C_NET_CTRL1_DPLL_TEST_SEL_LEN = 8 ;
+static const uint8_t P9N2_C_NET_CTRL1_SB_STRENGTH = 16 ;
+static const uint8_t P9N2_C_NET_CTRL1_SB_STRENGTH_LEN = 4 ;
+static const uint8_t P9N2_C_NET_CTRL1_ASYNC_TYPE = 20 ;
+static const uint8_t P9N2_C_NET_CTRL1_ASYNC_OBS = 21 ;
+static const uint8_t P9N2_C_NET_CTRL1_CPM_CAL_SET = 22 ;
+static const uint8_t P9N2_C_NET_CTRL1_SENSEADJ_RESET0 = 23 ;
+static const uint8_t P9N2_C_NET_CTRL1_SENSEADJ_RESET1 = 24 ;
+static const uint8_t P9N2_C_NET_CTRL1_CLK_PULSE_EN = 25 ;
+static const uint8_t P9N2_C_NET_CTRL1_CLK_PULSE_MODE = 26 ;
+static const uint8_t P9N2_C_NET_CTRL1_CLK_PULSE_MODE_LEN = 2 ;
+static const uint8_t P9N2_C_NET_CTRL1_PCB_ACCESS = 28 ;
+static const uint8_t P9N2_C_NET_CTRL1_PCB_ACCESS_LEN = 4 ;
+
+static const uint8_t P9N2_EX_L2_OCC_SCOMC_MODE_CX = 54 ;
+static const uint8_t P9N2_EX_L2_OCC_SCOMC_MODE_CX_LEN = 7 ;
+
+static const uint8_t P9N2_C_OCC_SCOMC_MODE_CX = 54 ;
+static const uint8_t P9N2_C_OCC_SCOMC_MODE_CX_LEN = 7 ;
+
+static const uint8_t P9N2_EQ_OPCG_ALIGN_INOP = 0 ;
+static const uint8_t P9N2_EQ_OPCG_ALIGN_INOP_LEN = 4 ;
+static const uint8_t P9N2_EQ_OPCG_ALIGN_SNOP = 4 ;
+static const uint8_t P9N2_EQ_OPCG_ALIGN_SNOP_LEN = 4 ;
+static const uint8_t P9N2_EQ_OPCG_ALIGN_ENOP = 8 ;
+static const uint8_t P9N2_EQ_OPCG_ALIGN_ENOP_LEN = 4 ;
+static const uint8_t P9N2_EQ_OPCG_ALIGN_INOP_WAIT = 12 ;
+static const uint8_t P9N2_EQ_OPCG_ALIGN_INOP_WAIT_LEN = 8 ;
+static const uint8_t P9N2_EQ_OPCG_ALIGN_SNOP_WAIT = 20 ;
+static const uint8_t P9N2_EQ_OPCG_ALIGN_SNOP_WAIT_LEN = 12 ;
+static const uint8_t P9N2_EQ_OPCG_ALIGN_ENOP_WAIT = 32 ;
+static const uint8_t P9N2_EQ_OPCG_ALIGN_ENOP_WAIT_LEN = 8 ;
+static const uint8_t P9N2_EQ_OPCG_ALIGN_INOP_FORCE_SG = 40 ;
+static const uint8_t P9N2_EQ_OPCG_ALIGN_SNOP_FORCE_SG = 41 ;
+static const uint8_t P9N2_EQ_OPCG_ALIGN_ENOP_FORCE_SG = 42 ;
+static const uint8_t P9N2_EQ_OPCG_ALIGN_NO_WAIT_ON_CLK_CMD = 43 ;
+static const uint8_t P9N2_EQ_OPCG_ALIGN_SOURCE_SELECT = 44 ;
+static const uint8_t P9N2_EQ_OPCG_ALIGN_SOURCE_SELECT_LEN = 2 ;
+static const uint8_t P9N2_EQ_OPCG_ALIGN_UNUSED46 = 46 ;
+static const uint8_t P9N2_EQ_OPCG_ALIGN_SCAN_RATIO = 47 ;
+static const uint8_t P9N2_EQ_OPCG_ALIGN_SCAN_RATIO_LEN = 5 ;
+static const uint8_t P9N2_EQ_OPCG_ALIGN_WAIT_CYCLES = 52 ;
+static const uint8_t P9N2_EQ_OPCG_ALIGN_WAIT_CYCLES_LEN = 12 ;
+
+static const uint8_t P9N2_EX_OPCG_ALIGN_INOP = 0 ;
+static const uint8_t P9N2_EX_OPCG_ALIGN_INOP_LEN = 4 ;
+static const uint8_t P9N2_EX_OPCG_ALIGN_SNOP = 4 ;
+static const uint8_t P9N2_EX_OPCG_ALIGN_SNOP_LEN = 4 ;
+static const uint8_t P9N2_EX_OPCG_ALIGN_ENOP = 8 ;
+static const uint8_t P9N2_EX_OPCG_ALIGN_ENOP_LEN = 4 ;
+static const uint8_t P9N2_EX_OPCG_ALIGN_INOP_WAIT = 12 ;
+static const uint8_t P9N2_EX_OPCG_ALIGN_INOP_WAIT_LEN = 8 ;
+static const uint8_t P9N2_EX_OPCG_ALIGN_SNOP_WAIT = 20 ;
+static const uint8_t P9N2_EX_OPCG_ALIGN_SNOP_WAIT_LEN = 12 ;
+static const uint8_t P9N2_EX_OPCG_ALIGN_ENOP_WAIT = 32 ;
+static const uint8_t P9N2_EX_OPCG_ALIGN_ENOP_WAIT_LEN = 8 ;
+static const uint8_t P9N2_EX_OPCG_ALIGN_INOP_FORCE_SG = 40 ;
+static const uint8_t P9N2_EX_OPCG_ALIGN_SNOP_FORCE_SG = 41 ;
+static const uint8_t P9N2_EX_OPCG_ALIGN_ENOP_FORCE_SG = 42 ;
+static const uint8_t P9N2_EX_OPCG_ALIGN_NO_WAIT_ON_CLK_CMD = 43 ;
+static const uint8_t P9N2_EX_OPCG_ALIGN_SOURCE_SELECT = 44 ;
+static const uint8_t P9N2_EX_OPCG_ALIGN_SOURCE_SELECT_LEN = 2 ;
+static const uint8_t P9N2_EX_OPCG_ALIGN_UNUSED46 = 46 ;
+static const uint8_t P9N2_EX_OPCG_ALIGN_SCAN_RATIO = 47 ;
+static const uint8_t P9N2_EX_OPCG_ALIGN_SCAN_RATIO_LEN = 5 ;
+static const uint8_t P9N2_EX_OPCG_ALIGN_WAIT_CYCLES = 52 ;
+static const uint8_t P9N2_EX_OPCG_ALIGN_WAIT_CYCLES_LEN = 12 ;
+
+static const uint8_t P9N2_C_OPCG_ALIGN_INOP = 0 ;
+static const uint8_t P9N2_C_OPCG_ALIGN_INOP_LEN = 4 ;
+static const uint8_t P9N2_C_OPCG_ALIGN_SNOP = 4 ;
+static const uint8_t P9N2_C_OPCG_ALIGN_SNOP_LEN = 4 ;
+static const uint8_t P9N2_C_OPCG_ALIGN_ENOP = 8 ;
+static const uint8_t P9N2_C_OPCG_ALIGN_ENOP_LEN = 4 ;
+static const uint8_t P9N2_C_OPCG_ALIGN_INOP_WAIT = 12 ;
+static const uint8_t P9N2_C_OPCG_ALIGN_INOP_WAIT_LEN = 8 ;
+static const uint8_t P9N2_C_OPCG_ALIGN_SNOP_WAIT = 20 ;
+static const uint8_t P9N2_C_OPCG_ALIGN_SNOP_WAIT_LEN = 12 ;
+static const uint8_t P9N2_C_OPCG_ALIGN_ENOP_WAIT = 32 ;
+static const uint8_t P9N2_C_OPCG_ALIGN_ENOP_WAIT_LEN = 8 ;
+static const uint8_t P9N2_C_OPCG_ALIGN_INOP_FORCE_SG = 40 ;
+static const uint8_t P9N2_C_OPCG_ALIGN_SNOP_FORCE_SG = 41 ;
+static const uint8_t P9N2_C_OPCG_ALIGN_ENOP_FORCE_SG = 42 ;
+static const uint8_t P9N2_C_OPCG_ALIGN_NO_WAIT_ON_CLK_CMD = 43 ;
+static const uint8_t P9N2_C_OPCG_ALIGN_SOURCE_SELECT = 44 ;
+static const uint8_t P9N2_C_OPCG_ALIGN_SOURCE_SELECT_LEN = 2 ;
+static const uint8_t P9N2_C_OPCG_ALIGN_UNUSED46 = 46 ;
+static const uint8_t P9N2_C_OPCG_ALIGN_SCAN_RATIO = 47 ;
+static const uint8_t P9N2_C_OPCG_ALIGN_SCAN_RATIO_LEN = 5 ;
+static const uint8_t P9N2_C_OPCG_ALIGN_WAIT_CYCLES = 52 ;
+static const uint8_t P9N2_C_OPCG_ALIGN_WAIT_CYCLES_LEN = 12 ;
+
+static const uint8_t P9N2_EQ_OPCG_CAPT1_COUNT = 0 ;
+static const uint8_t P9N2_EQ_OPCG_CAPT1_COUNT_LEN = 4 ;
+static const uint8_t P9N2_EQ_OPCG_CAPT1_SEQ_01 = 4 ;
+static const uint8_t P9N2_EQ_OPCG_CAPT1_SEQ_01_LEN = 5 ;
+static const uint8_t P9N2_EQ_OPCG_CAPT1_SEQ_02 = 9 ;
+static const uint8_t P9N2_EQ_OPCG_CAPT1_SEQ_02_LEN = 5 ;
+static const uint8_t P9N2_EQ_OPCG_CAPT1_SEQ_03 = 14 ;
+static const uint8_t P9N2_EQ_OPCG_CAPT1_SEQ_03_LEN = 5 ;
+static const uint8_t P9N2_EQ_OPCG_CAPT1_SEQ_04 = 19 ;
+static const uint8_t P9N2_EQ_OPCG_CAPT1_SEQ_04_LEN = 5 ;
+static const uint8_t P9N2_EQ_OPCG_CAPT1_SEQ_05 = 24 ;
+static const uint8_t P9N2_EQ_OPCG_CAPT1_SEQ_05_LEN = 5 ;
+static const uint8_t P9N2_EQ_OPCG_CAPT1_SEQ_06 = 29 ;
+static const uint8_t P9N2_EQ_OPCG_CAPT1_SEQ_06_LEN = 5 ;
+static const uint8_t P9N2_EQ_OPCG_CAPT1_SEQ_07 = 34 ;
+static const uint8_t P9N2_EQ_OPCG_CAPT1_SEQ_07_LEN = 5 ;
+static const uint8_t P9N2_EQ_OPCG_CAPT1_SEQ_08 = 39 ;
+static const uint8_t P9N2_EQ_OPCG_CAPT1_SEQ_08_LEN = 5 ;
+static const uint8_t P9N2_EQ_OPCG_CAPT1_SEQ_09 = 44 ;
+static const uint8_t P9N2_EQ_OPCG_CAPT1_SEQ_09_LEN = 5 ;
+static const uint8_t P9N2_EQ_OPCG_CAPT1_SEQ_10 = 49 ;
+static const uint8_t P9N2_EQ_OPCG_CAPT1_SEQ_10_LEN = 5 ;
+static const uint8_t P9N2_EQ_OPCG_CAPT1_SEQ_11 = 54 ;
+static const uint8_t P9N2_EQ_OPCG_CAPT1_SEQ_11_LEN = 5 ;
+static const uint8_t P9N2_EQ_OPCG_CAPT1_SEQ_12 = 59 ;
+static const uint8_t P9N2_EQ_OPCG_CAPT1_SEQ_12_LEN = 5 ;
+
+static const uint8_t P9N2_EX_OPCG_CAPT1_COUNT = 0 ;
+static const uint8_t P9N2_EX_OPCG_CAPT1_COUNT_LEN = 4 ;
+static const uint8_t P9N2_EX_OPCG_CAPT1_SEQ_01 = 4 ;
+static const uint8_t P9N2_EX_OPCG_CAPT1_SEQ_01_LEN = 5 ;
+static const uint8_t P9N2_EX_OPCG_CAPT1_SEQ_02 = 9 ;
+static const uint8_t P9N2_EX_OPCG_CAPT1_SEQ_02_LEN = 5 ;
+static const uint8_t P9N2_EX_OPCG_CAPT1_SEQ_03 = 14 ;
+static const uint8_t P9N2_EX_OPCG_CAPT1_SEQ_03_LEN = 5 ;
+static const uint8_t P9N2_EX_OPCG_CAPT1_SEQ_04 = 19 ;
+static const uint8_t P9N2_EX_OPCG_CAPT1_SEQ_04_LEN = 5 ;
+static const uint8_t P9N2_EX_OPCG_CAPT1_SEQ_05 = 24 ;
+static const uint8_t P9N2_EX_OPCG_CAPT1_SEQ_05_LEN = 5 ;
+static const uint8_t P9N2_EX_OPCG_CAPT1_SEQ_06 = 29 ;
+static const uint8_t P9N2_EX_OPCG_CAPT1_SEQ_06_LEN = 5 ;
+static const uint8_t P9N2_EX_OPCG_CAPT1_SEQ_07 = 34 ;
+static const uint8_t P9N2_EX_OPCG_CAPT1_SEQ_07_LEN = 5 ;
+static const uint8_t P9N2_EX_OPCG_CAPT1_SEQ_08 = 39 ;
+static const uint8_t P9N2_EX_OPCG_CAPT1_SEQ_08_LEN = 5 ;
+static const uint8_t P9N2_EX_OPCG_CAPT1_SEQ_09 = 44 ;
+static const uint8_t P9N2_EX_OPCG_CAPT1_SEQ_09_LEN = 5 ;
+static const uint8_t P9N2_EX_OPCG_CAPT1_SEQ_10 = 49 ;
+static const uint8_t P9N2_EX_OPCG_CAPT1_SEQ_10_LEN = 5 ;
+static const uint8_t P9N2_EX_OPCG_CAPT1_SEQ_11 = 54 ;
+static const uint8_t P9N2_EX_OPCG_CAPT1_SEQ_11_LEN = 5 ;
+static const uint8_t P9N2_EX_OPCG_CAPT1_SEQ_12 = 59 ;
+static const uint8_t P9N2_EX_OPCG_CAPT1_SEQ_12_LEN = 5 ;
+
+static const uint8_t P9N2_C_OPCG_CAPT1_COUNT = 0 ;
+static const uint8_t P9N2_C_OPCG_CAPT1_COUNT_LEN = 4 ;
+static const uint8_t P9N2_C_OPCG_CAPT1_SEQ_01 = 4 ;
+static const uint8_t P9N2_C_OPCG_CAPT1_SEQ_01_LEN = 5 ;
+static const uint8_t P9N2_C_OPCG_CAPT1_SEQ_02 = 9 ;
+static const uint8_t P9N2_C_OPCG_CAPT1_SEQ_02_LEN = 5 ;
+static const uint8_t P9N2_C_OPCG_CAPT1_SEQ_03 = 14 ;
+static const uint8_t P9N2_C_OPCG_CAPT1_SEQ_03_LEN = 5 ;
+static const uint8_t P9N2_C_OPCG_CAPT1_SEQ_04 = 19 ;
+static const uint8_t P9N2_C_OPCG_CAPT1_SEQ_04_LEN = 5 ;
+static const uint8_t P9N2_C_OPCG_CAPT1_SEQ_05 = 24 ;
+static const uint8_t P9N2_C_OPCG_CAPT1_SEQ_05_LEN = 5 ;
+static const uint8_t P9N2_C_OPCG_CAPT1_SEQ_06 = 29 ;
+static const uint8_t P9N2_C_OPCG_CAPT1_SEQ_06_LEN = 5 ;
+static const uint8_t P9N2_C_OPCG_CAPT1_SEQ_07 = 34 ;
+static const uint8_t P9N2_C_OPCG_CAPT1_SEQ_07_LEN = 5 ;
+static const uint8_t P9N2_C_OPCG_CAPT1_SEQ_08 = 39 ;
+static const uint8_t P9N2_C_OPCG_CAPT1_SEQ_08_LEN = 5 ;
+static const uint8_t P9N2_C_OPCG_CAPT1_SEQ_09 = 44 ;
+static const uint8_t P9N2_C_OPCG_CAPT1_SEQ_09_LEN = 5 ;
+static const uint8_t P9N2_C_OPCG_CAPT1_SEQ_10 = 49 ;
+static const uint8_t P9N2_C_OPCG_CAPT1_SEQ_10_LEN = 5 ;
+static const uint8_t P9N2_C_OPCG_CAPT1_SEQ_11 = 54 ;
+static const uint8_t P9N2_C_OPCG_CAPT1_SEQ_11_LEN = 5 ;
+static const uint8_t P9N2_C_OPCG_CAPT1_SEQ_12 = 59 ;
+static const uint8_t P9N2_C_OPCG_CAPT1_SEQ_12_LEN = 5 ;
+
+static const uint8_t P9N2_EQ_OPCG_CAPT2_UNUSED = 0 ;
+static const uint8_t P9N2_EQ_OPCG_CAPT2_UNUSED_LEN = 4 ;
+static const uint8_t P9N2_EQ_OPCG_CAPT2_SEQ_13_01EVEN = 4 ;
+static const uint8_t P9N2_EQ_OPCG_CAPT2_SEQ_13_01EVEN_LEN = 5 ;
+static const uint8_t P9N2_EQ_OPCG_CAPT2_SEQ_14_01ODD = 9 ;
+static const uint8_t P9N2_EQ_OPCG_CAPT2_SEQ_14_01ODD_LEN = 5 ;
+static const uint8_t P9N2_EQ_OPCG_CAPT2_SEQ_15_02EVEN = 14 ;
+static const uint8_t P9N2_EQ_OPCG_CAPT2_SEQ_15_02EVEN_LEN = 5 ;
+static const uint8_t P9N2_EQ_OPCG_CAPT2_SEQ_16_02ODD = 19 ;
+static const uint8_t P9N2_EQ_OPCG_CAPT2_SEQ_16_02ODD_LEN = 5 ;
+static const uint8_t P9N2_EQ_OPCG_CAPT2_SEQ_17_03EVEN = 24 ;
+static const uint8_t P9N2_EQ_OPCG_CAPT2_SEQ_17_03EVEN_LEN = 5 ;
+static const uint8_t P9N2_EQ_OPCG_CAPT2_SEQ_18_03ODD = 29 ;
+static const uint8_t P9N2_EQ_OPCG_CAPT2_SEQ_18_03ODD_LEN = 5 ;
+static const uint8_t P9N2_EQ_OPCG_CAPT2_SEQ_19_04EVEN = 34 ;
+static const uint8_t P9N2_EQ_OPCG_CAPT2_SEQ_19_04EVEN_LEN = 5 ;
+static const uint8_t P9N2_EQ_OPCG_CAPT2_SEQ_20_04ODD = 39 ;
+static const uint8_t P9N2_EQ_OPCG_CAPT2_SEQ_20_04ODD_LEN = 5 ;
+static const uint8_t P9N2_EQ_OPCG_CAPT2_SEQ_21_05EVEN = 44 ;
+static const uint8_t P9N2_EQ_OPCG_CAPT2_SEQ_21_05EVEN_LEN = 5 ;
+static const uint8_t P9N2_EQ_OPCG_CAPT2_SEQ_22_05ODD = 49 ;
+static const uint8_t P9N2_EQ_OPCG_CAPT2_SEQ_22_05ODD_LEN = 5 ;
+static const uint8_t P9N2_EQ_OPCG_CAPT2_SEQ_23_06EVEN = 54 ;
+static const uint8_t P9N2_EQ_OPCG_CAPT2_SEQ_23_06EVEN_LEN = 5 ;
+static const uint8_t P9N2_EQ_OPCG_CAPT2_SEQ_24_06ODD = 59 ;
+static const uint8_t P9N2_EQ_OPCG_CAPT2_SEQ_24_06ODD_LEN = 5 ;
+
+static const uint8_t P9N2_EX_OPCG_CAPT2_UNUSED = 0 ;
+static const uint8_t P9N2_EX_OPCG_CAPT2_UNUSED_LEN = 4 ;
+static const uint8_t P9N2_EX_OPCG_CAPT2_SEQ_13_01EVEN = 4 ;
+static const uint8_t P9N2_EX_OPCG_CAPT2_SEQ_13_01EVEN_LEN = 5 ;
+static const uint8_t P9N2_EX_OPCG_CAPT2_SEQ_14_01ODD = 9 ;
+static const uint8_t P9N2_EX_OPCG_CAPT2_SEQ_14_01ODD_LEN = 5 ;
+static const uint8_t P9N2_EX_OPCG_CAPT2_SEQ_15_02EVEN = 14 ;
+static const uint8_t P9N2_EX_OPCG_CAPT2_SEQ_15_02EVEN_LEN = 5 ;
+static const uint8_t P9N2_EX_OPCG_CAPT2_SEQ_16_02ODD = 19 ;
+static const uint8_t P9N2_EX_OPCG_CAPT2_SEQ_16_02ODD_LEN = 5 ;
+static const uint8_t P9N2_EX_OPCG_CAPT2_SEQ_17_03EVEN = 24 ;
+static const uint8_t P9N2_EX_OPCG_CAPT2_SEQ_17_03EVEN_LEN = 5 ;
+static const uint8_t P9N2_EX_OPCG_CAPT2_SEQ_18_03ODD = 29 ;
+static const uint8_t P9N2_EX_OPCG_CAPT2_SEQ_18_03ODD_LEN = 5 ;
+static const uint8_t P9N2_EX_OPCG_CAPT2_SEQ_19_04EVEN = 34 ;
+static const uint8_t P9N2_EX_OPCG_CAPT2_SEQ_19_04EVEN_LEN = 5 ;
+static const uint8_t P9N2_EX_OPCG_CAPT2_SEQ_20_04ODD = 39 ;
+static const uint8_t P9N2_EX_OPCG_CAPT2_SEQ_20_04ODD_LEN = 5 ;
+static const uint8_t P9N2_EX_OPCG_CAPT2_SEQ_21_05EVEN = 44 ;
+static const uint8_t P9N2_EX_OPCG_CAPT2_SEQ_21_05EVEN_LEN = 5 ;
+static const uint8_t P9N2_EX_OPCG_CAPT2_SEQ_22_05ODD = 49 ;
+static const uint8_t P9N2_EX_OPCG_CAPT2_SEQ_22_05ODD_LEN = 5 ;
+static const uint8_t P9N2_EX_OPCG_CAPT2_SEQ_23_06EVEN = 54 ;
+static const uint8_t P9N2_EX_OPCG_CAPT2_SEQ_23_06EVEN_LEN = 5 ;
+static const uint8_t P9N2_EX_OPCG_CAPT2_SEQ_24_06ODD = 59 ;
+static const uint8_t P9N2_EX_OPCG_CAPT2_SEQ_24_06ODD_LEN = 5 ;
+
+static const uint8_t P9N2_C_OPCG_CAPT2_UNUSED = 0 ;
+static const uint8_t P9N2_C_OPCG_CAPT2_UNUSED_LEN = 4 ;
+static const uint8_t P9N2_C_OPCG_CAPT2_SEQ_13_01EVEN = 4 ;
+static const uint8_t P9N2_C_OPCG_CAPT2_SEQ_13_01EVEN_LEN = 5 ;
+static const uint8_t P9N2_C_OPCG_CAPT2_SEQ_14_01ODD = 9 ;
+static const uint8_t P9N2_C_OPCG_CAPT2_SEQ_14_01ODD_LEN = 5 ;
+static const uint8_t P9N2_C_OPCG_CAPT2_SEQ_15_02EVEN = 14 ;
+static const uint8_t P9N2_C_OPCG_CAPT2_SEQ_15_02EVEN_LEN = 5 ;
+static const uint8_t P9N2_C_OPCG_CAPT2_SEQ_16_02ODD = 19 ;
+static const uint8_t P9N2_C_OPCG_CAPT2_SEQ_16_02ODD_LEN = 5 ;
+static const uint8_t P9N2_C_OPCG_CAPT2_SEQ_17_03EVEN = 24 ;
+static const uint8_t P9N2_C_OPCG_CAPT2_SEQ_17_03EVEN_LEN = 5 ;
+static const uint8_t P9N2_C_OPCG_CAPT2_SEQ_18_03ODD = 29 ;
+static const uint8_t P9N2_C_OPCG_CAPT2_SEQ_18_03ODD_LEN = 5 ;
+static const uint8_t P9N2_C_OPCG_CAPT2_SEQ_19_04EVEN = 34 ;
+static const uint8_t P9N2_C_OPCG_CAPT2_SEQ_19_04EVEN_LEN = 5 ;
+static const uint8_t P9N2_C_OPCG_CAPT2_SEQ_20_04ODD = 39 ;
+static const uint8_t P9N2_C_OPCG_CAPT2_SEQ_20_04ODD_LEN = 5 ;
+static const uint8_t P9N2_C_OPCG_CAPT2_SEQ_21_05EVEN = 44 ;
+static const uint8_t P9N2_C_OPCG_CAPT2_SEQ_21_05EVEN_LEN = 5 ;
+static const uint8_t P9N2_C_OPCG_CAPT2_SEQ_22_05ODD = 49 ;
+static const uint8_t P9N2_C_OPCG_CAPT2_SEQ_22_05ODD_LEN = 5 ;
+static const uint8_t P9N2_C_OPCG_CAPT2_SEQ_23_06EVEN = 54 ;
+static const uint8_t P9N2_C_OPCG_CAPT2_SEQ_23_06EVEN_LEN = 5 ;
+static const uint8_t P9N2_C_OPCG_CAPT2_SEQ_24_06ODD = 59 ;
+static const uint8_t P9N2_C_OPCG_CAPT2_SEQ_24_06ODD_LEN = 5 ;
+
+static const uint8_t P9N2_EQ_OPCG_CAPT3_UNUSED = 0 ;
+static const uint8_t P9N2_EQ_OPCG_CAPT3_UNUSED_LEN = 4 ;
+static const uint8_t P9N2_EQ_OPCG_CAPT3_SEQ_07EVEN = 4 ;
+static const uint8_t P9N2_EQ_OPCG_CAPT3_SEQ_07EVEN_LEN = 5 ;
+static const uint8_t P9N2_EQ_OPCG_CAPT3_SEQ_07ODD = 9 ;
+static const uint8_t P9N2_EQ_OPCG_CAPT3_SEQ_07ODD_LEN = 5 ;
+static const uint8_t P9N2_EQ_OPCG_CAPT3_SEQ_08EVEN = 14 ;
+static const uint8_t P9N2_EQ_OPCG_CAPT3_SEQ_08EVEN_LEN = 5 ;
+static const uint8_t P9N2_EQ_OPCG_CAPT3_SEQ_08ODD = 19 ;
+static const uint8_t P9N2_EQ_OPCG_CAPT3_SEQ_08ODD_LEN = 5 ;
+static const uint8_t P9N2_EQ_OPCG_CAPT3_SEQ_09EVEN = 24 ;
+static const uint8_t P9N2_EQ_OPCG_CAPT3_SEQ_09EVEN_LEN = 5 ;
+static const uint8_t P9N2_EQ_OPCG_CAPT3_SEQ_09ODD = 29 ;
+static const uint8_t P9N2_EQ_OPCG_CAPT3_SEQ_09ODD_LEN = 5 ;
+static const uint8_t P9N2_EQ_OPCG_CAPT3_SEQ_10EVEN = 34 ;
+static const uint8_t P9N2_EQ_OPCG_CAPT3_SEQ_10EVEN_LEN = 5 ;
+static const uint8_t P9N2_EQ_OPCG_CAPT3_SEQ_10ODD = 39 ;
+static const uint8_t P9N2_EQ_OPCG_CAPT3_SEQ_10ODD_LEN = 5 ;
+static const uint8_t P9N2_EQ_OPCG_CAPT3_SEQ_11EVEN = 44 ;
+static const uint8_t P9N2_EQ_OPCG_CAPT3_SEQ_11EVEN_LEN = 5 ;
+static const uint8_t P9N2_EQ_OPCG_CAPT3_SEQ_11ODD = 49 ;
+static const uint8_t P9N2_EQ_OPCG_CAPT3_SEQ_11ODD_LEN = 5 ;
+static const uint8_t P9N2_EQ_OPCG_CAPT3_SEQ_12EVEN = 54 ;
+static const uint8_t P9N2_EQ_OPCG_CAPT3_SEQ_12EVEN_LEN = 5 ;
+static const uint8_t P9N2_EQ_OPCG_CAPT3_SEQ_12ODD = 59 ;
+static const uint8_t P9N2_EQ_OPCG_CAPT3_SEQ_12ODD_LEN = 5 ;
+
+static const uint8_t P9N2_EX_OPCG_CAPT3_UNUSED = 0 ;
+static const uint8_t P9N2_EX_OPCG_CAPT3_UNUSED_LEN = 4 ;
+static const uint8_t P9N2_EX_OPCG_CAPT3_SEQ_07EVEN = 4 ;
+static const uint8_t P9N2_EX_OPCG_CAPT3_SEQ_07EVEN_LEN = 5 ;
+static const uint8_t P9N2_EX_OPCG_CAPT3_SEQ_07ODD = 9 ;
+static const uint8_t P9N2_EX_OPCG_CAPT3_SEQ_07ODD_LEN = 5 ;
+static const uint8_t P9N2_EX_OPCG_CAPT3_SEQ_08EVEN = 14 ;
+static const uint8_t P9N2_EX_OPCG_CAPT3_SEQ_08EVEN_LEN = 5 ;
+static const uint8_t P9N2_EX_OPCG_CAPT3_SEQ_08ODD = 19 ;
+static const uint8_t P9N2_EX_OPCG_CAPT3_SEQ_08ODD_LEN = 5 ;
+static const uint8_t P9N2_EX_OPCG_CAPT3_SEQ_09EVEN = 24 ;
+static const uint8_t P9N2_EX_OPCG_CAPT3_SEQ_09EVEN_LEN = 5 ;
+static const uint8_t P9N2_EX_OPCG_CAPT3_SEQ_09ODD = 29 ;
+static const uint8_t P9N2_EX_OPCG_CAPT3_SEQ_09ODD_LEN = 5 ;
+static const uint8_t P9N2_EX_OPCG_CAPT3_SEQ_10EVEN = 34 ;
+static const uint8_t P9N2_EX_OPCG_CAPT3_SEQ_10EVEN_LEN = 5 ;
+static const uint8_t P9N2_EX_OPCG_CAPT3_SEQ_10ODD = 39 ;
+static const uint8_t P9N2_EX_OPCG_CAPT3_SEQ_10ODD_LEN = 5 ;
+static const uint8_t P9N2_EX_OPCG_CAPT3_SEQ_11EVEN = 44 ;
+static const uint8_t P9N2_EX_OPCG_CAPT3_SEQ_11EVEN_LEN = 5 ;
+static const uint8_t P9N2_EX_OPCG_CAPT3_SEQ_11ODD = 49 ;
+static const uint8_t P9N2_EX_OPCG_CAPT3_SEQ_11ODD_LEN = 5 ;
+static const uint8_t P9N2_EX_OPCG_CAPT3_SEQ_12EVEN = 54 ;
+static const uint8_t P9N2_EX_OPCG_CAPT3_SEQ_12EVEN_LEN = 5 ;
+static const uint8_t P9N2_EX_OPCG_CAPT3_SEQ_12ODD = 59 ;
+static const uint8_t P9N2_EX_OPCG_CAPT3_SEQ_12ODD_LEN = 5 ;
+
+static const uint8_t P9N2_C_OPCG_CAPT3_UNUSED = 0 ;
+static const uint8_t P9N2_C_OPCG_CAPT3_UNUSED_LEN = 4 ;
+static const uint8_t P9N2_C_OPCG_CAPT3_SEQ_07EVEN = 4 ;
+static const uint8_t P9N2_C_OPCG_CAPT3_SEQ_07EVEN_LEN = 5 ;
+static const uint8_t P9N2_C_OPCG_CAPT3_SEQ_07ODD = 9 ;
+static const uint8_t P9N2_C_OPCG_CAPT3_SEQ_07ODD_LEN = 5 ;
+static const uint8_t P9N2_C_OPCG_CAPT3_SEQ_08EVEN = 14 ;
+static const uint8_t P9N2_C_OPCG_CAPT3_SEQ_08EVEN_LEN = 5 ;
+static const uint8_t P9N2_C_OPCG_CAPT3_SEQ_08ODD = 19 ;
+static const uint8_t P9N2_C_OPCG_CAPT3_SEQ_08ODD_LEN = 5 ;
+static const uint8_t P9N2_C_OPCG_CAPT3_SEQ_09EVEN = 24 ;
+static const uint8_t P9N2_C_OPCG_CAPT3_SEQ_09EVEN_LEN = 5 ;
+static const uint8_t P9N2_C_OPCG_CAPT3_SEQ_09ODD = 29 ;
+static const uint8_t P9N2_C_OPCG_CAPT3_SEQ_09ODD_LEN = 5 ;
+static const uint8_t P9N2_C_OPCG_CAPT3_SEQ_10EVEN = 34 ;
+static const uint8_t P9N2_C_OPCG_CAPT3_SEQ_10EVEN_LEN = 5 ;
+static const uint8_t P9N2_C_OPCG_CAPT3_SEQ_10ODD = 39 ;
+static const uint8_t P9N2_C_OPCG_CAPT3_SEQ_10ODD_LEN = 5 ;
+static const uint8_t P9N2_C_OPCG_CAPT3_SEQ_11EVEN = 44 ;
+static const uint8_t P9N2_C_OPCG_CAPT3_SEQ_11EVEN_LEN = 5 ;
+static const uint8_t P9N2_C_OPCG_CAPT3_SEQ_11ODD = 49 ;
+static const uint8_t P9N2_C_OPCG_CAPT3_SEQ_11ODD_LEN = 5 ;
+static const uint8_t P9N2_C_OPCG_CAPT3_SEQ_12EVEN = 54 ;
+static const uint8_t P9N2_C_OPCG_CAPT3_SEQ_12EVEN_LEN = 5 ;
+static const uint8_t P9N2_C_OPCG_CAPT3_SEQ_12ODD = 59 ;
+static const uint8_t P9N2_C_OPCG_CAPT3_SEQ_12ODD_LEN = 5 ;
+
+static const uint8_t P9N2_EQ_OPCG_REG0_RUNN_MODE = 0 ;
+static const uint8_t P9N2_EQ_OPCG_REG0_GO = 1 ;
+static const uint8_t P9N2_EQ_OPCG_REG0_RUN_SCAN0 = 2 ;
+static const uint8_t P9N2_EQ_OPCG_REG0_SCAN0_MODE = 3 ;
+static const uint8_t P9N2_EQ_OPCG_REG0_IN_SLAVE_MODE = 4 ;
+static const uint8_t P9N2_EQ_OPCG_REG0_IN_MASTER_MODE = 5 ;
+static const uint8_t P9N2_EQ_OPCG_REG0_KEEP_MS_MODE = 6 ;
+static const uint8_t P9N2_EQ_OPCG_REG0_TRIGGER_ON_UNIT0_SYNC_LVL = 7 ;
+static const uint8_t P9N2_EQ_OPCG_REG0_TRIGGER_ON_UNIT1_SYNC_LVL = 8 ;
+static const uint8_t P9N2_EQ_OPCG_REG0_RUN_CHIPLET_SCAN0 = 9 ;
+static const uint8_t P9N2_EQ_OPCG_REG0_RUN_CHIPLET_SCAN0_NO_PLL = 10 ;
+static const uint8_t P9N2_EQ_OPCG_REG0_RUN_ON_UPDATE_DR = 11 ;
+static const uint8_t P9N2_EQ_OPCG_REG0_RUN_ON_CAPTURE_DR = 12 ;
+static const uint8_t P9N2_EQ_OPCG_REG0_STOP_RUNN_ON_XSTOP = 13 ;
+static const uint8_t P9N2_EQ_OPCG_REG0_STARTS_BIST = 14 ;
+static const uint8_t P9N2_EQ_OPCG_REG0_UNUSED1520 = 15 ;
+static const uint8_t P9N2_EQ_OPCG_REG0_UNUSED1520_LEN = 6 ;
+static const uint8_t P9N2_EQ_OPCG_REG0_LOOP_COUNT = 21 ;
+static const uint8_t P9N2_EQ_OPCG_REG0_LOOP_COUNT_LEN = 43 ;
+
+static const uint8_t P9N2_EX_OPCG_REG0_RUNN_MODE = 0 ;
+static const uint8_t P9N2_EX_OPCG_REG0_GO = 1 ;
+static const uint8_t P9N2_EX_OPCG_REG0_RUN_SCAN0 = 2 ;
+static const uint8_t P9N2_EX_OPCG_REG0_SCAN0_MODE = 3 ;
+static const uint8_t P9N2_EX_OPCG_REG0_IN_SLAVE_MODE = 4 ;
+static const uint8_t P9N2_EX_OPCG_REG0_IN_MASTER_MODE = 5 ;
+static const uint8_t P9N2_EX_OPCG_REG0_KEEP_MS_MODE = 6 ;
+static const uint8_t P9N2_EX_OPCG_REG0_TRIGGER_ON_UNIT0_SYNC_LVL = 7 ;
+static const uint8_t P9N2_EX_OPCG_REG0_TRIGGER_ON_UNIT1_SYNC_LVL = 8 ;
+static const uint8_t P9N2_EX_OPCG_REG0_RUN_CHIPLET_SCAN0 = 9 ;
+static const uint8_t P9N2_EX_OPCG_REG0_RUN_CHIPLET_SCAN0_NO_PLL = 10 ;
+static const uint8_t P9N2_EX_OPCG_REG0_RUN_ON_UPDATE_DR = 11 ;
+static const uint8_t P9N2_EX_OPCG_REG0_RUN_ON_CAPTURE_DR = 12 ;
+static const uint8_t P9N2_EX_OPCG_REG0_STOP_RUNN_ON_XSTOP = 13 ;
+static const uint8_t P9N2_EX_OPCG_REG0_STARTS_BIST = 14 ;
+static const uint8_t P9N2_EX_OPCG_REG0_UNUSED1520 = 15 ;
+static const uint8_t P9N2_EX_OPCG_REG0_UNUSED1520_LEN = 6 ;
+static const uint8_t P9N2_EX_OPCG_REG0_LOOP_COUNT = 21 ;
+static const uint8_t P9N2_EX_OPCG_REG0_LOOP_COUNT_LEN = 43 ;
+
+static const uint8_t P9N2_C_OPCG_REG0_RUNN_MODE = 0 ;
+static const uint8_t P9N2_C_OPCG_REG0_GO = 1 ;
+static const uint8_t P9N2_C_OPCG_REG0_RUN_SCAN0 = 2 ;
+static const uint8_t P9N2_C_OPCG_REG0_SCAN0_MODE = 3 ;
+static const uint8_t P9N2_C_OPCG_REG0_IN_SLAVE_MODE = 4 ;
+static const uint8_t P9N2_C_OPCG_REG0_IN_MASTER_MODE = 5 ;
+static const uint8_t P9N2_C_OPCG_REG0_KEEP_MS_MODE = 6 ;
+static const uint8_t P9N2_C_OPCG_REG0_TRIGGER_ON_UNIT0_SYNC_LVL = 7 ;
+static const uint8_t P9N2_C_OPCG_REG0_TRIGGER_ON_UNIT1_SYNC_LVL = 8 ;
+static const uint8_t P9N2_C_OPCG_REG0_RUN_CHIPLET_SCAN0 = 9 ;
+static const uint8_t P9N2_C_OPCG_REG0_RUN_CHIPLET_SCAN0_NO_PLL = 10 ;
+static const uint8_t P9N2_C_OPCG_REG0_RUN_ON_UPDATE_DR = 11 ;
+static const uint8_t P9N2_C_OPCG_REG0_RUN_ON_CAPTURE_DR = 12 ;
+static const uint8_t P9N2_C_OPCG_REG0_STOP_RUNN_ON_XSTOP = 13 ;
+static const uint8_t P9N2_C_OPCG_REG0_STARTS_BIST = 14 ;
+static const uint8_t P9N2_C_OPCG_REG0_UNUSED1520 = 15 ;
+static const uint8_t P9N2_C_OPCG_REG0_UNUSED1520_LEN = 6 ;
+static const uint8_t P9N2_C_OPCG_REG0_LOOP_COUNT = 21 ;
+static const uint8_t P9N2_C_OPCG_REG0_LOOP_COUNT_LEN = 43 ;
+
+static const uint8_t P9N2_EQ_OPCG_REG1_SCAN_COUNT = 0 ;
+static const uint8_t P9N2_EQ_OPCG_REG1_SCAN_COUNT_LEN = 12 ;
+static const uint8_t P9N2_EQ_OPCG_REG1_MISR_A_VAL = 12 ;
+static const uint8_t P9N2_EQ_OPCG_REG1_MISR_A_VAL_LEN = 12 ;
+static const uint8_t P9N2_EQ_OPCG_REG1_MISR_B_VAL = 24 ;
+static const uint8_t P9N2_EQ_OPCG_REG1_MISR_B_VAL_LEN = 12 ;
+static const uint8_t P9N2_EQ_OPCG_REG1_MISR_INIT_WAIT = 36 ;
+static const uint8_t P9N2_EQ_OPCG_REG1_MISR_INIT_WAIT_LEN = 12 ;
+static const uint8_t P9N2_EQ_OPCG_REG1_SUPPRESS_LAST_RUNN_CLK = 48 ;
+static const uint8_t P9N2_EQ_OPCG_REG1_SCAN_CLK_USE_EVEN = 49 ;
+static const uint8_t P9N2_EQ_OPCG_REG1_UNUSED2 = 50 ;
+static const uint8_t P9N2_EQ_OPCG_REG1_UNUSED2_LEN = 2 ;
+static const uint8_t P9N2_EQ_OPCG_REG1_RTIM_THOLD_FORCE = 52 ;
+static const uint8_t P9N2_EQ_OPCG_REG1_DISABLE_ARY_CLK_DURING_FILL = 53 ;
+static const uint8_t P9N2_EQ_OPCG_REG1_SG_HIGH_DURING_FILL = 54 ;
+static const uint8_t P9N2_EQ_OPCG_REG1_LBIST_SKITTER_CTL = 55 ;
+static const uint8_t P9N2_EQ_OPCG_REG1_LBIST_SKITTER_CTL_LEN = 2 ;
+static const uint8_t P9N2_EQ_OPCG_REG1_MISR_MODE = 57 ;
+static const uint8_t P9N2_EQ_OPCG_REG1_INFINITE_MODE = 58 ;
+static const uint8_t P9N2_EQ_OPCG_REG1_NSL_FILL_COUNT = 59 ;
+static const uint8_t P9N2_EQ_OPCG_REG1_NSL_FILL_COUNT_LEN = 5 ;
+
+static const uint8_t P9N2_EX_OPCG_REG1_SCAN_COUNT = 0 ;
+static const uint8_t P9N2_EX_OPCG_REG1_SCAN_COUNT_LEN = 12 ;
+static const uint8_t P9N2_EX_OPCG_REG1_MISR_A_VAL = 12 ;
+static const uint8_t P9N2_EX_OPCG_REG1_MISR_A_VAL_LEN = 12 ;
+static const uint8_t P9N2_EX_OPCG_REG1_MISR_B_VAL = 24 ;
+static const uint8_t P9N2_EX_OPCG_REG1_MISR_B_VAL_LEN = 12 ;
+static const uint8_t P9N2_EX_OPCG_REG1_MISR_INIT_WAIT = 36 ;
+static const uint8_t P9N2_EX_OPCG_REG1_MISR_INIT_WAIT_LEN = 12 ;
+static const uint8_t P9N2_EX_OPCG_REG1_SUPPRESS_LAST_RUNN_CLK = 48 ;
+static const uint8_t P9N2_EX_OPCG_REG1_SCAN_CLK_USE_EVEN = 49 ;
+static const uint8_t P9N2_EX_OPCG_REG1_UNUSED2 = 50 ;
+static const uint8_t P9N2_EX_OPCG_REG1_UNUSED2_LEN = 2 ;
+static const uint8_t P9N2_EX_OPCG_REG1_RTIM_THOLD_FORCE = 52 ;
+static const uint8_t P9N2_EX_OPCG_REG1_DISABLE_ARY_CLK_DURING_FILL = 53 ;
+static const uint8_t P9N2_EX_OPCG_REG1_SG_HIGH_DURING_FILL = 54 ;
+static const uint8_t P9N2_EX_OPCG_REG1_LBIST_SKITTER_CTL = 55 ;
+static const uint8_t P9N2_EX_OPCG_REG1_LBIST_SKITTER_CTL_LEN = 2 ;
+static const uint8_t P9N2_EX_OPCG_REG1_MISR_MODE = 57 ;
+static const uint8_t P9N2_EX_OPCG_REG1_INFINITE_MODE = 58 ;
+static const uint8_t P9N2_EX_OPCG_REG1_NSL_FILL_COUNT = 59 ;
+static const uint8_t P9N2_EX_OPCG_REG1_NSL_FILL_COUNT_LEN = 5 ;
+
+static const uint8_t P9N2_C_OPCG_REG1_SCAN_COUNT = 0 ;
+static const uint8_t P9N2_C_OPCG_REG1_SCAN_COUNT_LEN = 12 ;
+static const uint8_t P9N2_C_OPCG_REG1_MISR_A_VAL = 12 ;
+static const uint8_t P9N2_C_OPCG_REG1_MISR_A_VAL_LEN = 12 ;
+static const uint8_t P9N2_C_OPCG_REG1_MISR_B_VAL = 24 ;
+static const uint8_t P9N2_C_OPCG_REG1_MISR_B_VAL_LEN = 12 ;
+static const uint8_t P9N2_C_OPCG_REG1_MISR_INIT_WAIT = 36 ;
+static const uint8_t P9N2_C_OPCG_REG1_MISR_INIT_WAIT_LEN = 12 ;
+static const uint8_t P9N2_C_OPCG_REG1_SUPPRESS_LAST_RUNN_CLK = 48 ;
+static const uint8_t P9N2_C_OPCG_REG1_SCAN_CLK_USE_EVEN = 49 ;
+static const uint8_t P9N2_C_OPCG_REG1_UNUSED2 = 50 ;
+static const uint8_t P9N2_C_OPCG_REG1_UNUSED2_LEN = 2 ;
+static const uint8_t P9N2_C_OPCG_REG1_RTIM_THOLD_FORCE = 52 ;
+static const uint8_t P9N2_C_OPCG_REG1_DISABLE_ARY_CLK_DURING_FILL = 53 ;
+static const uint8_t P9N2_C_OPCG_REG1_SG_HIGH_DURING_FILL = 54 ;
+static const uint8_t P9N2_C_OPCG_REG1_LBIST_SKITTER_CTL = 55 ;
+static const uint8_t P9N2_C_OPCG_REG1_LBIST_SKITTER_CTL_LEN = 2 ;
+static const uint8_t P9N2_C_OPCG_REG1_MISR_MODE = 57 ;
+static const uint8_t P9N2_C_OPCG_REG1_INFINITE_MODE = 58 ;
+static const uint8_t P9N2_C_OPCG_REG1_NSL_FILL_COUNT = 59 ;
+static const uint8_t P9N2_C_OPCG_REG1_NSL_FILL_COUNT_LEN = 5 ;
+
+static const uint8_t P9N2_EQ_OPCG_REG2_GO2 = 0 ;
+static const uint8_t P9N2_EQ_OPCG_REG2_PRPG_WEIGHTING = 1 ;
+static const uint8_t P9N2_EQ_OPCG_REG2_PRPG_WEIGHTING_LEN = 3 ;
+static const uint8_t P9N2_EQ_OPCG_REG2_PRPG_VALUE = 4 ;
+static const uint8_t P9N2_EQ_OPCG_REG2_PRPG_VALUE_LEN = 12 ;
+static const uint8_t P9N2_EQ_OPCG_REG2_PRPG_A_VAL = 16 ;
+static const uint8_t P9N2_EQ_OPCG_REG2_PRPG_A_VAL_LEN = 12 ;
+static const uint8_t P9N2_EQ_OPCG_REG2_PRPG_B_VAL = 28 ;
+static const uint8_t P9N2_EQ_OPCG_REG2_PRPG_B_VAL_LEN = 12 ;
+static const uint8_t P9N2_EQ_OPCG_REG2_PRPG_MODE = 40 ;
+static const uint8_t P9N2_EQ_OPCG_REG2_UNUSED41_63 = 41 ;
+static const uint8_t P9N2_EQ_OPCG_REG2_UNUSED41_63_LEN = 23 ;
+
+static const uint8_t P9N2_EX_OPCG_REG2_GO2 = 0 ;
+static const uint8_t P9N2_EX_OPCG_REG2_PRPG_WEIGHTING = 1 ;
+static const uint8_t P9N2_EX_OPCG_REG2_PRPG_WEIGHTING_LEN = 3 ;
+static const uint8_t P9N2_EX_OPCG_REG2_PRPG_VALUE = 4 ;
+static const uint8_t P9N2_EX_OPCG_REG2_PRPG_VALUE_LEN = 12 ;
+static const uint8_t P9N2_EX_OPCG_REG2_PRPG_A_VAL = 16 ;
+static const uint8_t P9N2_EX_OPCG_REG2_PRPG_A_VAL_LEN = 12 ;
+static const uint8_t P9N2_EX_OPCG_REG2_PRPG_B_VAL = 28 ;
+static const uint8_t P9N2_EX_OPCG_REG2_PRPG_B_VAL_LEN = 12 ;
+static const uint8_t P9N2_EX_OPCG_REG2_PRPG_MODE = 40 ;
+static const uint8_t P9N2_EX_OPCG_REG2_UNUSED41_63 = 41 ;
+static const uint8_t P9N2_EX_OPCG_REG2_UNUSED41_63_LEN = 23 ;
+
+static const uint8_t P9N2_C_OPCG_REG2_GO2 = 0 ;
+static const uint8_t P9N2_C_OPCG_REG2_PRPG_WEIGHTING = 1 ;
+static const uint8_t P9N2_C_OPCG_REG2_PRPG_WEIGHTING_LEN = 3 ;
+static const uint8_t P9N2_C_OPCG_REG2_PRPG_VALUE = 4 ;
+static const uint8_t P9N2_C_OPCG_REG2_PRPG_VALUE_LEN = 12 ;
+static const uint8_t P9N2_C_OPCG_REG2_PRPG_A_VAL = 16 ;
+static const uint8_t P9N2_C_OPCG_REG2_PRPG_A_VAL_LEN = 12 ;
+static const uint8_t P9N2_C_OPCG_REG2_PRPG_B_VAL = 28 ;
+static const uint8_t P9N2_C_OPCG_REG2_PRPG_B_VAL_LEN = 12 ;
+static const uint8_t P9N2_C_OPCG_REG2_PRPG_MODE = 40 ;
+static const uint8_t P9N2_C_OPCG_REG2_UNUSED41_63 = 41 ;
+static const uint8_t P9N2_C_OPCG_REG2_UNUSED41_63_LEN = 23 ;
+
+static const uint8_t P9N2_EQ_PCB_OPCG_GO_OPCGGO = 0 ;
+
+static const uint8_t P9N2_EX_PCB_OPCG_GO_OPCGGO = 0 ;
+
+static const uint8_t P9N2_C_PCB_OPCG_GO_OPCGGO = 0 ;
+
+static const uint8_t P9N2_EQ_PCB_OPCG_STOP_OPCGSTOP = 0 ;
+
+static const uint8_t P9N2_EX_PCB_OPCG_STOP_OPCGSTOP = 0 ;
+
+static const uint8_t P9N2_C_PCB_OPCG_STOP_OPCGSTOP = 0 ;
+
+static const uint8_t P9N2_EQ_PHYP_PURGE_CMD_REG_TRIGGER = 0 ;
+static const uint8_t P9N2_EQ_PHYP_PURGE_CMD_REG_TYPE = 1 ;
+static const uint8_t P9N2_EQ_PHYP_PURGE_CMD_REG_TYPE_LEN = 4 ;
+static const uint8_t P9N2_EQ_PHYP_PURGE_CMD_REG_BUSY = 9 ;
+static const uint8_t P9N2_EQ_PHYP_PURGE_CMD_REG_PRGSM_BUSY_ON_THIS = 10 ;
+static const uint8_t P9N2_EQ_PHYP_PURGE_CMD_REG_PRGSM_BUSY = 11 ;
+static const uint8_t P9N2_EQ_PHYP_PURGE_CMD_REG_MEM = 17 ;
+static const uint8_t P9N2_EQ_PHYP_PURGE_CMD_REG_MEM_LEN = 3 ;
+static const uint8_t P9N2_EQ_PHYP_PURGE_CMD_REG_CGC = 20 ;
+static const uint8_t P9N2_EQ_PHYP_PURGE_CMD_REG_CGC_LEN = 8 ;
+static const uint8_t P9N2_EQ_PHYP_PURGE_CMD_REG_BANK = 28 ;
+static const uint8_t P9N2_EQ_PHYP_PURGE_CMD_REG_ERR = 29 ;
+
+static const uint8_t P9N2_EX_PHYP_PURGE_CMD_REG_TRIGGER = 0 ;
+static const uint8_t P9N2_EX_PHYP_PURGE_CMD_REG_TYPE = 1 ;
+static const uint8_t P9N2_EX_PHYP_PURGE_CMD_REG_TYPE_LEN = 4 ;
+static const uint8_t P9N2_EX_PHYP_PURGE_CMD_REG_BUSY = 9 ;
+static const uint8_t P9N2_EX_PHYP_PURGE_CMD_REG_PRGSM_BUSY_ON_THIS = 10 ;
+static const uint8_t P9N2_EX_PHYP_PURGE_CMD_REG_PRGSM_BUSY = 11 ;
+static const uint8_t P9N2_EX_PHYP_PURGE_CMD_REG_MEM = 17 ;
+static const uint8_t P9N2_EX_PHYP_PURGE_CMD_REG_MEM_LEN = 3 ;
+static const uint8_t P9N2_EX_PHYP_PURGE_CMD_REG_CGC = 20 ;
+static const uint8_t P9N2_EX_PHYP_PURGE_CMD_REG_CGC_LEN = 8 ;
+static const uint8_t P9N2_EX_PHYP_PURGE_CMD_REG_BANK = 28 ;
+static const uint8_t P9N2_EX_PHYP_PURGE_CMD_REG_ERR = 29 ;
+
+static const uint8_t P9N2_EQ_PHYP_PURGE_REG_L3_REQ = 0 ;
+static const uint8_t P9N2_EQ_PHYP_PURGE_REG_L3_TTYPE = 1 ;
+static const uint8_t P9N2_EQ_PHYP_PURGE_REG_L3_TTYPE_LEN = 4 ;
+static const uint8_t P9N2_EQ_PHYP_PURGE_REG_L3_LINE_DEL_ON_NEXT_CE = 5 ;
+static const uint8_t P9N2_EQ_PHYP_PURGE_REG_L3_LINE_DEL_ON_ALL_CE = 6 ;
+static const uint8_t P9N2_EQ_PHYP_PURGE_REG_L3_PHYP_PURGE_RESERVED_1 = 7 ;
+static const uint8_t P9N2_EQ_PHYP_PURGE_REG_L3_PHYP_PURGE_RESERVED_1_LEN = 2 ;
+static const uint8_t P9N2_EQ_PHYP_PURGE_REG_L3_BUSY_ERR = 9 ;
+static const uint8_t P9N2_EQ_PHYP_PURGE_REG_L3_PHYP_PURGE_RESERVED_2 = 10 ;
+static const uint8_t P9N2_EQ_PHYP_PURGE_REG_L3_PHYP_PURGE_RESERVED_2_LEN = 2 ;
+static const uint8_t P9N2_EQ_PHYP_PURGE_REG_L3_MEMBER = 12 ;
+static const uint8_t P9N2_EQ_PHYP_PURGE_REG_L3_MEMBER_LEN = 5 ;
+static const uint8_t P9N2_EQ_PHYP_PURGE_REG_L3_DIR_ADDR = 17 ;
+static const uint8_t P9N2_EQ_PHYP_PURGE_REG_L3_DIR_ADDR_LEN = 12 ;
+
+static const uint8_t P9N2_EX_L3_PHYP_PURGE_REG_L3_REQ = 0 ;
+static const uint8_t P9N2_EX_L3_PHYP_PURGE_REG_L3_TTYPE = 1 ;
+static const uint8_t P9N2_EX_L3_PHYP_PURGE_REG_L3_TTYPE_LEN = 4 ;
+static const uint8_t P9N2_EX_L3_PHYP_PURGE_REG_L3_LINE_DEL_ON_NEXT_CE = 5 ;
+static const uint8_t P9N2_EX_L3_PHYP_PURGE_REG_L3_LINE_DEL_ON_ALL_CE = 6 ;
+static const uint8_t P9N2_EX_L3_PHYP_PURGE_REG_L3_PHYP_PURGE_RESERVED_1 = 7 ;
+static const uint8_t P9N2_EX_L3_PHYP_PURGE_REG_L3_PHYP_PURGE_RESERVED_1_LEN = 2 ;
+static const uint8_t P9N2_EX_L3_PHYP_PURGE_REG_L3_BUSY_ERR = 9 ;
+static const uint8_t P9N2_EX_L3_PHYP_PURGE_REG_L3_PHYP_PURGE_RESERVED_2 = 10 ;
+static const uint8_t P9N2_EX_L3_PHYP_PURGE_REG_L3_PHYP_PURGE_RESERVED_2_LEN = 2 ;
+static const uint8_t P9N2_EX_L3_PHYP_PURGE_REG_L3_MEMBER = 12 ;
+static const uint8_t P9N2_EX_L3_PHYP_PURGE_REG_L3_MEMBER_LEN = 5 ;
+static const uint8_t P9N2_EX_L3_PHYP_PURGE_REG_L3_DIR_ADDR = 17 ;
+static const uint8_t P9N2_EX_L3_PHYP_PURGE_REG_L3_DIR_ADDR_LEN = 12 ;
+
+static const uint8_t P9N2_EQ_PLL_LOCK_REG_LOCK = 0 ;
+static const uint8_t P9N2_EQ_PLL_LOCK_REG_LOCK_LEN = 4 ;
+
+static const uint8_t P9N2_EX_PLL_LOCK_REG_LOCK = 0 ;
+static const uint8_t P9N2_EX_PLL_LOCK_REG_LOCK_LEN = 4 ;
+
+static const uint8_t P9N2_C_PLL_LOCK_REG_LOCK = 0 ;
+static const uint8_t P9N2_C_PLL_LOCK_REG_LOCK_LEN = 4 ;
+
+static const uint8_t P9N2_EX_L2_PMU_HOLD_OUT_PMUT0_SPR_HOLD_OUT = 0 ;
+static const uint8_t P9N2_EX_L2_PMU_HOLD_OUT_PMUT0_SPR_HOLD_OUT_LEN = 4 ;
+static const uint8_t P9N2_EX_L2_PMU_HOLD_OUT_PMUT1_SPR_HOLD_OUT = 4 ;
+static const uint8_t P9N2_EX_L2_PMU_HOLD_OUT_PMUT1_SPR_HOLD_OUT_LEN = 4 ;
+static const uint8_t P9N2_EX_L2_PMU_HOLD_OUT_PMUT2_SPR_HOLD_OUT = 8 ;
+static const uint8_t P9N2_EX_L2_PMU_HOLD_OUT_PMUT2_SPR_HOLD_OUT_LEN = 4 ;
+static const uint8_t P9N2_EX_L2_PMU_HOLD_OUT_PMUT3_SPR_HOLD_OUT = 12 ;
+static const uint8_t P9N2_EX_L2_PMU_HOLD_OUT_PMUT3_SPR_HOLD_OUT_LEN = 4 ;
+
+static const uint8_t P9N2_C_PMU_HOLD_OUT_PMUT0_SPR_HOLD_OUT = 0 ;
+static const uint8_t P9N2_C_PMU_HOLD_OUT_PMUT0_SPR_HOLD_OUT_LEN = 4 ;
+static const uint8_t P9N2_C_PMU_HOLD_OUT_PMUT1_SPR_HOLD_OUT = 4 ;
+static const uint8_t P9N2_C_PMU_HOLD_OUT_PMUT1_SPR_HOLD_OUT_LEN = 4 ;
+static const uint8_t P9N2_C_PMU_HOLD_OUT_PMUT2_SPR_HOLD_OUT = 8 ;
+static const uint8_t P9N2_C_PMU_HOLD_OUT_PMUT2_SPR_HOLD_OUT_LEN = 4 ;
+static const uint8_t P9N2_C_PMU_HOLD_OUT_PMUT3_SPR_HOLD_OUT = 12 ;
+static const uint8_t P9N2_C_PMU_HOLD_OUT_PMUT3_SPR_HOLD_OUT_LEN = 4 ;
+
+static const uint8_t P9N2_EX_L2_PMU_SCOMC_PMC1 = 0 ;
+static const uint8_t P9N2_EX_L2_PMU_SCOMC_PMC2 = 1 ;
+static const uint8_t P9N2_EX_L2_PMU_SCOMC_PMC3 = 2 ;
+static const uint8_t P9N2_EX_L2_PMU_SCOMC_PMC4 = 3 ;
+static const uint8_t P9N2_EX_L2_PMU_SCOMC_PMC5 = 4 ;
+static const uint8_t P9N2_EX_L2_PMU_SCOMC_PMC6 = 5 ;
+static const uint8_t P9N2_EX_L2_PMU_SCOMC_MMCRC = 6 ;
+static const uint8_t P9N2_EX_L2_PMU_SCOMC_MMCR0 = 7 ;
+static const uint8_t P9N2_EX_L2_PMU_SCOMC_MMCR1 = 8 ;
+static const uint8_t P9N2_EX_L2_PMU_SCOMC_MMCR2 = 9 ;
+static const uint8_t P9N2_EX_L2_PMU_SCOMC_MMCRA = 10 ;
+static const uint8_t P9N2_EX_L2_PMU_SCOMC_SIER = 11 ;
+static const uint8_t P9N2_EX_L2_PMU_SCOMC_THREAD_ID = 12 ;
+static const uint8_t P9N2_EX_L2_PMU_SCOMC_THREAD_ID_LEN = 2 ;
+
+static const uint8_t P9N2_C_PMU_SCOMC_PMC1 = 0 ;
+static const uint8_t P9N2_C_PMU_SCOMC_PMC2 = 1 ;
+static const uint8_t P9N2_C_PMU_SCOMC_PMC3 = 2 ;
+static const uint8_t P9N2_C_PMU_SCOMC_PMC4 = 3 ;
+static const uint8_t P9N2_C_PMU_SCOMC_PMC5 = 4 ;
+static const uint8_t P9N2_C_PMU_SCOMC_PMC6 = 5 ;
+static const uint8_t P9N2_C_PMU_SCOMC_MMCRC = 6 ;
+static const uint8_t P9N2_C_PMU_SCOMC_MMCR0 = 7 ;
+static const uint8_t P9N2_C_PMU_SCOMC_MMCR1 = 8 ;
+static const uint8_t P9N2_C_PMU_SCOMC_MMCR2 = 9 ;
+static const uint8_t P9N2_C_PMU_SCOMC_MMCRA = 10 ;
+static const uint8_t P9N2_C_PMU_SCOMC_SIER = 11 ;
+static const uint8_t P9N2_C_PMU_SCOMC_THREAD_ID = 12 ;
+static const uint8_t P9N2_C_PMU_SCOMC_THREAD_ID_LEN = 2 ;
+
+static const uint8_t P9N2_EX_L2_PMU_SCOMC_EN_ENABLE_INDIRECT_PMU_SCOM = 0 ;
+
+static const uint8_t P9N2_C_PMU_SCOMC_EN_ENABLE_INDIRECT_PMU_SCOM = 0 ;
+
+static const uint8_t P9N2_EQ_PM_L2_RCMD_DIS_REG_L3_CFG = 0 ;
+
+static const uint8_t P9N2_EX_PM_L2_RCMD_DIS_REG_L3_CFG = 0 ;
+
+static const uint8_t P9N2_EQ_PM_LCO_DIS_REG_L3_CFG = 0 ;
+
+static const uint8_t P9N2_EX_L3_PM_LCO_DIS_REG_L3_CFG = 0 ;
+
+static const uint8_t P9N2_EQ_PM_PURGE_REG_L3_REQ = 0 ;
+static const uint8_t P9N2_EQ_PM_PURGE_REG_L3_BUSY_ERR = 1 ;
+static const uint8_t P9N2_EQ_PM_PURGE_REG_L3_ABORT = 2 ;
+
+static const uint8_t P9N2_EX_L3_PM_PURGE_REG_L3_REQ = 0 ;
+static const uint8_t P9N2_EX_L3_PM_PURGE_REG_L3_BUSY_ERR = 1 ;
+static const uint8_t P9N2_EX_L3_PM_PURGE_REG_L3_ABORT = 2 ;
+
+static const uint8_t P9N2_EQ_PPE_XIDBGPRO_XSR_HS = 0 ;
+static const uint8_t P9N2_EQ_PPE_XIDBGPRO_XSR_HC = 1 ;
+static const uint8_t P9N2_EQ_PPE_XIDBGPRO_XSR_HC_LEN = 3 ;
+static const uint8_t P9N2_EQ_PPE_XIDBGPRO_XSR_HCP = 4 ;
+static const uint8_t P9N2_EQ_PPE_XIDBGPRO_XSR_RIP = 5 ;
+static const uint8_t P9N2_EQ_PPE_XIDBGPRO_XSR_SIP = 6 ;
+static const uint8_t P9N2_EQ_PPE_XIDBGPRO_XSR_TRAP = 7 ;
+static const uint8_t P9N2_EQ_PPE_XIDBGPRO_XSR_IAC = 8 ;
+static const uint8_t P9N2_EQ_PPE_XIDBGPRO_NULL_MSR_SIBRC = 9 ;
+static const uint8_t P9N2_EQ_PPE_XIDBGPRO_NULL_MSR_SIBRC_LEN = 3 ;
+static const uint8_t P9N2_EQ_PPE_XIDBGPRO_XSR_DACR = 12 ;
+static const uint8_t P9N2_EQ_PPE_XIDBGPRO_XSR_DACW = 13 ;
+static const uint8_t P9N2_EQ_PPE_XIDBGPRO_NULL_MSR_WE = 14 ;
+static const uint8_t P9N2_EQ_PPE_XIDBGPRO_XSR_TRH = 15 ;
+static const uint8_t P9N2_EQ_PPE_XIDBGPRO_XSR_SMS = 16 ;
+static const uint8_t P9N2_EQ_PPE_XIDBGPRO_XSR_SMS_LEN = 4 ;
+static const uint8_t P9N2_EQ_PPE_XIDBGPRO_NULL_MSR_LP = 20 ;
+static const uint8_t P9N2_EQ_PPE_XIDBGPRO_XSR_EP = 21 ;
+static const uint8_t P9N2_EQ_PPE_XIDBGPRO_XSR_PTR = 24 ;
+static const uint8_t P9N2_EQ_PPE_XIDBGPRO_XSR_ST = 25 ;
+static const uint8_t P9N2_EQ_PPE_XIDBGPRO_XSR_MFE = 28 ;
+static const uint8_t P9N2_EQ_PPE_XIDBGPRO_XSR_MCS = 29 ;
+static const uint8_t P9N2_EQ_PPE_XIDBGPRO_XSR_MCS_LEN = 3 ;
+static const uint8_t P9N2_EQ_PPE_XIDBGPRO_IAR = 32 ;
+static const uint8_t P9N2_EQ_PPE_XIDBGPRO_IAR_LEN = 30 ;
+
+static const uint8_t P9N2_EX_PPE_XIDBGPRO_XSR_HS = 0 ;
+static const uint8_t P9N2_EX_PPE_XIDBGPRO_XSR_HC = 1 ;
+static const uint8_t P9N2_EX_PPE_XIDBGPRO_XSR_HC_LEN = 3 ;
+static const uint8_t P9N2_EX_PPE_XIDBGPRO_XSR_HCP = 4 ;
+static const uint8_t P9N2_EX_PPE_XIDBGPRO_XSR_RIP = 5 ;
+static const uint8_t P9N2_EX_PPE_XIDBGPRO_XSR_SIP = 6 ;
+static const uint8_t P9N2_EX_PPE_XIDBGPRO_XSR_TRAP = 7 ;
+static const uint8_t P9N2_EX_PPE_XIDBGPRO_XSR_IAC = 8 ;
+static const uint8_t P9N2_EX_PPE_XIDBGPRO_NULL_MSR_SIBRC = 9 ;
+static const uint8_t P9N2_EX_PPE_XIDBGPRO_NULL_MSR_SIBRC_LEN = 3 ;
+static const uint8_t P9N2_EX_PPE_XIDBGPRO_XSR_DACR = 12 ;
+static const uint8_t P9N2_EX_PPE_XIDBGPRO_XSR_DACW = 13 ;
+static const uint8_t P9N2_EX_PPE_XIDBGPRO_NULL_MSR_WE = 14 ;
+static const uint8_t P9N2_EX_PPE_XIDBGPRO_XSR_TRH = 15 ;
+static const uint8_t P9N2_EX_PPE_XIDBGPRO_XSR_SMS = 16 ;
+static const uint8_t P9N2_EX_PPE_XIDBGPRO_XSR_SMS_LEN = 4 ;
+static const uint8_t P9N2_EX_PPE_XIDBGPRO_NULL_MSR_LP = 20 ;
+static const uint8_t P9N2_EX_PPE_XIDBGPRO_XSR_EP = 21 ;
+static const uint8_t P9N2_EX_PPE_XIDBGPRO_XSR_PTR = 24 ;
+static const uint8_t P9N2_EX_PPE_XIDBGPRO_XSR_ST = 25 ;
+static const uint8_t P9N2_EX_PPE_XIDBGPRO_XSR_MFE = 28 ;
+static const uint8_t P9N2_EX_PPE_XIDBGPRO_XSR_MCS = 29 ;
+static const uint8_t P9N2_EX_PPE_XIDBGPRO_XSR_MCS_LEN = 3 ;
+static const uint8_t P9N2_EX_PPE_XIDBGPRO_IAR = 32 ;
+static const uint8_t P9N2_EX_PPE_XIDBGPRO_IAR_LEN = 30 ;
+
+static const uint8_t P9N2_EQ_PPE_XIRAMDBG_XSR_HS = 0 ;
+static const uint8_t P9N2_EQ_PPE_XIRAMDBG_XSR_HC = 1 ;
+static const uint8_t P9N2_EQ_PPE_XIRAMDBG_XSR_HC_LEN = 3 ;
+static const uint8_t P9N2_EQ_PPE_XIRAMDBG_XSR_HCP = 4 ;
+static const uint8_t P9N2_EQ_PPE_XIRAMDBG_XSR_RIP = 5 ;
+static const uint8_t P9N2_EQ_PPE_XIRAMDBG_XSR_SIP = 6 ;
+static const uint8_t P9N2_EQ_PPE_XIRAMDBG_XSR_TRAP = 7 ;
+static const uint8_t P9N2_EQ_PPE_XIRAMDBG_XSR_IAC = 8 ;
+static const uint8_t P9N2_EQ_PPE_XIRAMDBG_NULL_MSR_SIBRC = 9 ;
+static const uint8_t P9N2_EQ_PPE_XIRAMDBG_NULL_MSR_SIBRC_LEN = 3 ;
+static const uint8_t P9N2_EQ_PPE_XIRAMDBG_XSR_DACR = 12 ;
+static const uint8_t P9N2_EQ_PPE_XIRAMDBG_XSR_DACW = 13 ;
+static const uint8_t P9N2_EQ_PPE_XIRAMDBG_NULL_MSR_WE = 14 ;
+static const uint8_t P9N2_EQ_PPE_XIRAMDBG_XSR_TRH = 15 ;
+static const uint8_t P9N2_EQ_PPE_XIRAMDBG_XSR_SMS = 16 ;
+static const uint8_t P9N2_EQ_PPE_XIRAMDBG_XSR_SMS_LEN = 4 ;
+static const uint8_t P9N2_EQ_PPE_XIRAMDBG_NULL_MSR_LP = 20 ;
+static const uint8_t P9N2_EQ_PPE_XIRAMDBG_XSR_EP = 21 ;
+static const uint8_t P9N2_EQ_PPE_XIRAMDBG_XSR_PTR = 24 ;
+static const uint8_t P9N2_EQ_PPE_XIRAMDBG_XSR_ST = 25 ;
+static const uint8_t P9N2_EQ_PPE_XIRAMDBG_XSR_MFE = 28 ;
+static const uint8_t P9N2_EQ_PPE_XIRAMDBG_XSR_MCS = 29 ;
+static const uint8_t P9N2_EQ_PPE_XIRAMDBG_XSR_MCS_LEN = 3 ;
+static const uint8_t P9N2_EQ_PPE_XIRAMDBG_XIRAMRA_SPRG0 = 32 ;
+static const uint8_t P9N2_EQ_PPE_XIRAMDBG_XIRAMRA_SPRG0_LEN = 32 ;
+
+static const uint8_t P9N2_EX_PPE_XIRAMDBG_XSR_HS = 0 ;
+static const uint8_t P9N2_EX_PPE_XIRAMDBG_XSR_HC = 1 ;
+static const uint8_t P9N2_EX_PPE_XIRAMDBG_XSR_HC_LEN = 3 ;
+static const uint8_t P9N2_EX_PPE_XIRAMDBG_XSR_HCP = 4 ;
+static const uint8_t P9N2_EX_PPE_XIRAMDBG_XSR_RIP = 5 ;
+static const uint8_t P9N2_EX_PPE_XIRAMDBG_XSR_SIP = 6 ;
+static const uint8_t P9N2_EX_PPE_XIRAMDBG_XSR_TRAP = 7 ;
+static const uint8_t P9N2_EX_PPE_XIRAMDBG_XSR_IAC = 8 ;
+static const uint8_t P9N2_EX_PPE_XIRAMDBG_NULL_MSR_SIBRC = 9 ;
+static const uint8_t P9N2_EX_PPE_XIRAMDBG_NULL_MSR_SIBRC_LEN = 3 ;
+static const uint8_t P9N2_EX_PPE_XIRAMDBG_XSR_DACR = 12 ;
+static const uint8_t P9N2_EX_PPE_XIRAMDBG_XSR_DACW = 13 ;
+static const uint8_t P9N2_EX_PPE_XIRAMDBG_NULL_MSR_WE = 14 ;
+static const uint8_t P9N2_EX_PPE_XIRAMDBG_XSR_TRH = 15 ;
+static const uint8_t P9N2_EX_PPE_XIRAMDBG_XSR_SMS = 16 ;
+static const uint8_t P9N2_EX_PPE_XIRAMDBG_XSR_SMS_LEN = 4 ;
+static const uint8_t P9N2_EX_PPE_XIRAMDBG_NULL_MSR_LP = 20 ;
+static const uint8_t P9N2_EX_PPE_XIRAMDBG_XSR_EP = 21 ;
+static const uint8_t P9N2_EX_PPE_XIRAMDBG_XSR_PTR = 24 ;
+static const uint8_t P9N2_EX_PPE_XIRAMDBG_XSR_ST = 25 ;
+static const uint8_t P9N2_EX_PPE_XIRAMDBG_XSR_MFE = 28 ;
+static const uint8_t P9N2_EX_PPE_XIRAMDBG_XSR_MCS = 29 ;
+static const uint8_t P9N2_EX_PPE_XIRAMDBG_XSR_MCS_LEN = 3 ;
+static const uint8_t P9N2_EX_PPE_XIRAMDBG_XIRAMRA_SPRG0 = 32 ;
+static const uint8_t P9N2_EX_PPE_XIRAMDBG_XIRAMRA_SPRG0_LEN = 32 ;
+
+static const uint8_t P9N2_EQ_PPE_XIRAMEDR_XIRAMGA_IR = 0 ;
+static const uint8_t P9N2_EQ_PPE_XIRAMEDR_XIRAMGA_IR_LEN = 32 ;
+static const uint8_t P9N2_EQ_PPE_XIRAMEDR_EDR = 32 ;
+static const uint8_t P9N2_EQ_PPE_XIRAMEDR_EDR_LEN = 32 ;
+
+static const uint8_t P9N2_EX_PPE_XIRAMEDR_XIRAMGA_IR = 0 ;
+static const uint8_t P9N2_EX_PPE_XIRAMEDR_XIRAMGA_IR_LEN = 32 ;
+static const uint8_t P9N2_EX_PPE_XIRAMEDR_EDR = 32 ;
+static const uint8_t P9N2_EX_PPE_XIRAMEDR_EDR_LEN = 32 ;
+
+static const uint8_t P9N2_EQ_PPE_XIRAMGA_IR = 0 ;
+static const uint8_t P9N2_EQ_PPE_XIRAMGA_IR_LEN = 32 ;
+static const uint8_t P9N2_EQ_PPE_XIRAMGA_XIRAMRA_SPRG0 = 32 ;
+static const uint8_t P9N2_EQ_PPE_XIRAMGA_XIRAMRA_SPRG0_LEN = 32 ;
+
+static const uint8_t P9N2_EX_PPE_XIRAMGA_IR = 0 ;
+static const uint8_t P9N2_EX_PPE_XIRAMGA_IR_LEN = 32 ;
+static const uint8_t P9N2_EX_PPE_XIRAMGA_XIRAMRA_SPRG0 = 32 ;
+static const uint8_t P9N2_EX_PPE_XIRAMGA_XIRAMRA_SPRG0_LEN = 32 ;
+
+static const uint8_t P9N2_EQ_PPE_XIRAMRA_XIXCR_XCR = 1 ;
+static const uint8_t P9N2_EQ_PPE_XIRAMRA_XIXCR_XCR_LEN = 3 ;
+static const uint8_t P9N2_EQ_PPE_XIRAMRA_SPRG0 = 32 ;
+static const uint8_t P9N2_EQ_PPE_XIRAMRA_SPRG0_LEN = 32 ;
+
+static const uint8_t P9N2_EX_PPE_XIRAMRA_XIXCR_XCR = 1 ;
+static const uint8_t P9N2_EX_PPE_XIRAMRA_XIXCR_XCR_LEN = 3 ;
+static const uint8_t P9N2_EX_PPE_XIRAMRA_SPRG0 = 32 ;
+static const uint8_t P9N2_EX_PPE_XIRAMRA_SPRG0_LEN = 32 ;
+
+static const uint8_t P9N2_EQ_PPE_XIXCR_XCR = 1 ;
+static const uint8_t P9N2_EQ_PPE_XIXCR_XCR_LEN = 3 ;
+
+static const uint8_t P9N2_EX_PPE_XIXCR_XCR = 1 ;
+static const uint8_t P9N2_EX_PPE_XIXCR_XCR_LEN = 3 ;
+
+static const uint8_t P9N2_EQ_PPM_CGCR_CLKGLM_ASYNC_RESET = 0 ;
+static const uint8_t P9N2_EQ_PPM_CGCR_RESERVED_1_2 = 1 ;
+static const uint8_t P9N2_EQ_PPM_CGCR_RESERVED_1_2_LEN = 2 ;
+static const uint8_t P9N2_EQ_PPM_CGCR_CLKGLM_SEL = 3 ;
+
+static const uint8_t P9N2_EX_PPM_CGCR_CLKGLM_ASYNC_RESET = 0 ;
+static const uint8_t P9N2_EX_PPM_CGCR_RESERVED_1_2 = 1 ;
+static const uint8_t P9N2_EX_PPM_CGCR_RESERVED_1_2_LEN = 2 ;
+static const uint8_t P9N2_EX_PPM_CGCR_CLKGLM_SEL = 3 ;
+
+static const uint8_t P9N2_C_PPM_CGCR_CLKGLM_ASYNC_RESET = 0 ;
+static const uint8_t P9N2_C_PPM_CGCR_RESERVED_1_2 = 1 ;
+static const uint8_t P9N2_C_PPM_CGCR_RESERVED_1_2_LEN = 2 ;
+static const uint8_t P9N2_C_PPM_CGCR_CLKGLM_SEL = 3 ;
+
+static const uint8_t P9N2_EQ_PPM_GPMMR_SPECIAL_WKUP_DONE = 0 ;
+static const uint8_t P9N2_EQ_PPM_GPMMR_SPECIAL_WKUP_ACTIVE = 1 ;
+static const uint8_t P9N2_EQ_PPM_GPMMR_REGULAR_WKUP_ACTIVE = 2 ;
+static const uint8_t P9N2_EQ_PPM_GPMMR_SPECIAL_WKUP_REQUESTED = 3 ;
+static const uint8_t P9N2_EQ_PPM_GPMMR_REGULAR_WKUP_REQUESTED = 4 ;
+static const uint8_t P9N2_EQ_PPM_GPMMR_REGULAR_WKUP_PRESENT = 5 ;
+static const uint8_t P9N2_EQ_PPM_GPMMR_BLOCK_REG_WKUP_EVENTS = 6 ;
+static const uint8_t P9N2_EQ_PPM_GPMMR_BLOCK_ALL_WKUP_EVENTS = 7 ;
+static const uint8_t P9N2_EQ_PPM_GPMMR_WKUP_OVERRIDE_EN = 8 ;
+static const uint8_t P9N2_EQ_PPM_GPMMR_SPC_WKUP_OVERRIDE = 9 ;
+static const uint8_t P9N2_EQ_PPM_GPMMR_REG_WKUP_OVERRIDE = 10 ;
+static const uint8_t P9N2_EQ_PPM_GPMMR_CHIPLET_ENABLE = 11 ;
+static const uint8_t P9N2_EQ_PPM_GPMMR_RESERVED_12_14 = 12 ;
+static const uint8_t P9N2_EQ_PPM_GPMMR_RESERVED_12_14_LEN = 3 ;
+static const uint8_t P9N2_EQ_PPM_GPMMR_RESET_STATE_INDICATOR = 15 ;
+
+static const uint8_t P9N2_EX_PPM_GPMMR_SPECIAL_WKUP_DONE = 0 ;
+static const uint8_t P9N2_EX_PPM_GPMMR_SPECIAL_WKUP_ACTIVE = 1 ;
+static const uint8_t P9N2_EX_PPM_GPMMR_REGULAR_WKUP_ACTIVE = 2 ;
+static const uint8_t P9N2_EX_PPM_GPMMR_SPECIAL_WKUP_REQUESTED = 3 ;
+static const uint8_t P9N2_EX_PPM_GPMMR_REGULAR_WKUP_REQUESTED = 4 ;
+static const uint8_t P9N2_EX_PPM_GPMMR_REGULAR_WKUP_PRESENT = 5 ;
+static const uint8_t P9N2_EX_PPM_GPMMR_BLOCK_REG_WKUP_EVENTS = 6 ;
+static const uint8_t P9N2_EX_PPM_GPMMR_BLOCK_ALL_WKUP_EVENTS = 7 ;
+static const uint8_t P9N2_EX_PPM_GPMMR_WKUP_OVERRIDE_EN = 8 ;
+static const uint8_t P9N2_EX_PPM_GPMMR_SPC_WKUP_OVERRIDE = 9 ;
+static const uint8_t P9N2_EX_PPM_GPMMR_REG_WKUP_OVERRIDE = 10 ;
+static const uint8_t P9N2_EX_PPM_GPMMR_CHIPLET_ENABLE = 11 ;
+static const uint8_t P9N2_EX_PPM_GPMMR_RESERVED_12_14 = 12 ;
+static const uint8_t P9N2_EX_PPM_GPMMR_RESERVED_12_14_LEN = 3 ;
+static const uint8_t P9N2_EX_PPM_GPMMR_RESET_STATE_INDICATOR = 15 ;
+
+static const uint8_t P9N2_C_PPM_GPMMR_SPECIAL_WKUP_DONE = 0 ;
+static const uint8_t P9N2_C_PPM_GPMMR_SPECIAL_WKUP_ACTIVE = 1 ;
+static const uint8_t P9N2_C_PPM_GPMMR_REGULAR_WKUP_ACTIVE = 2 ;
+static const uint8_t P9N2_C_PPM_GPMMR_SPECIAL_WKUP_REQUESTED = 3 ;
+static const uint8_t P9N2_C_PPM_GPMMR_REGULAR_WKUP_REQUESTED = 4 ;
+static const uint8_t P9N2_C_PPM_GPMMR_REGULAR_WKUP_PRESENT = 5 ;
+static const uint8_t P9N2_C_PPM_GPMMR_BLOCK_REG_WKUP_EVENTS = 6 ;
+static const uint8_t P9N2_C_PPM_GPMMR_BLOCK_ALL_WKUP_EVENTS = 7 ;
+static const uint8_t P9N2_C_PPM_GPMMR_WKUP_OVERRIDE_EN = 8 ;
+static const uint8_t P9N2_C_PPM_GPMMR_SPC_WKUP_OVERRIDE = 9 ;
+static const uint8_t P9N2_C_PPM_GPMMR_REG_WKUP_OVERRIDE = 10 ;
+static const uint8_t P9N2_C_PPM_GPMMR_CHIPLET_ENABLE = 11 ;
+static const uint8_t P9N2_C_PPM_GPMMR_RESERVED_12_14 = 12 ;
+static const uint8_t P9N2_C_PPM_GPMMR_RESERVED_12_14_LEN = 3 ;
+static const uint8_t P9N2_C_PPM_GPMMR_RESET_STATE_INDICATOR = 15 ;
+
+static const uint8_t P9N2_EQ_PPM_IVRMAVR_IVRM_IVID = 0 ;
+static const uint8_t P9N2_EQ_PPM_IVRMAVR_IVRM_IVID_LEN = 8 ;
+static const uint8_t P9N2_EQ_PPM_IVRMAVR_IVRM_PROTECT_ACTIVE = 8 ;
+static const uint8_t P9N2_EQ_PPM_IVRMAVR_IVRM_PFET_STRENGTH = 11 ;
+static const uint8_t P9N2_EQ_PPM_IVRMAVR_IVRM_PFET_STRENGTH_LEN = 5 ;
+static const uint8_t P9N2_EQ_PPM_IVRMAVR_IVRM_VID_VALID = 24 ;
+static const uint8_t P9N2_EQ_PPM_IVRMAVR_IVRM_BYPASS_B = 25 ;
+static const uint8_t P9N2_EQ_PPM_IVRMAVR_IVRM_POWERON = 26 ;
+static const uint8_t P9N2_EQ_PPM_IVRMAVR_IVRM_VREG_SLOW_DC = 27 ;
+
+static const uint8_t P9N2_EX_PPM_IVRMAVR_IVRM_IVID = 0 ;
+static const uint8_t P9N2_EX_PPM_IVRMAVR_IVRM_IVID_LEN = 8 ;
+static const uint8_t P9N2_EX_PPM_IVRMAVR_IVRM_PROTECT_ACTIVE = 8 ;
+static const uint8_t P9N2_EX_PPM_IVRMAVR_IVRM_PFET_STRENGTH = 11 ;
+static const uint8_t P9N2_EX_PPM_IVRMAVR_IVRM_PFET_STRENGTH_LEN = 5 ;
+static const uint8_t P9N2_EX_PPM_IVRMAVR_IVRM_VID_VALID = 24 ;
+static const uint8_t P9N2_EX_PPM_IVRMAVR_IVRM_BYPASS_B = 25 ;
+static const uint8_t P9N2_EX_PPM_IVRMAVR_IVRM_POWERON = 26 ;
+static const uint8_t P9N2_EX_PPM_IVRMAVR_IVRM_VREG_SLOW_DC = 27 ;
+
+static const uint8_t P9N2_C_PPM_IVRMAVR_IVRM_IVID = 0 ;
+static const uint8_t P9N2_C_PPM_IVRMAVR_IVRM_IVID_LEN = 8 ;
+static const uint8_t P9N2_C_PPM_IVRMAVR_IVRM_PROTECT_ACTIVE = 8 ;
+static const uint8_t P9N2_C_PPM_IVRMAVR_IVRM_PFET_STRENGTH = 11 ;
+static const uint8_t P9N2_C_PPM_IVRMAVR_IVRM_PFET_STRENGTH_LEN = 5 ;
+static const uint8_t P9N2_C_PPM_IVRMAVR_IVRM_VID_VALID = 24 ;
+static const uint8_t P9N2_C_PPM_IVRMAVR_IVRM_BYPASS_B = 25 ;
+static const uint8_t P9N2_C_PPM_IVRMAVR_IVRM_POWERON = 26 ;
+static const uint8_t P9N2_C_PPM_IVRMAVR_IVRM_VREG_SLOW_DC = 27 ;
+
+static const uint8_t P9N2_EQ_PPM_IVRMCR_IVRM_VID_VALID = 0 ;
+static const uint8_t P9N2_EQ_PPM_IVRMCR_IVRM_BYPASS_B = 1 ;
+static const uint8_t P9N2_EQ_PPM_IVRMCR_IVRM_POWERON = 2 ;
+static const uint8_t P9N2_EQ_PPM_IVRMCR_IVRM_VREG_SLOW_DC = 3 ;
+static const uint8_t P9N2_EQ_PPM_IVRMCR_RESERVED_4_7 = 4 ;
+static const uint8_t P9N2_EQ_PPM_IVRMCR_RESERVED_4_7_LEN = 4 ;
+
+static const uint8_t P9N2_EX_PPM_IVRMCR_IVRM_VID_VALID = 0 ;
+static const uint8_t P9N2_EX_PPM_IVRMCR_IVRM_BYPASS_B = 1 ;
+static const uint8_t P9N2_EX_PPM_IVRMCR_IVRM_POWERON = 2 ;
+static const uint8_t P9N2_EX_PPM_IVRMCR_IVRM_VREG_SLOW_DC = 3 ;
+static const uint8_t P9N2_EX_PPM_IVRMCR_RESERVED_4_7 = 4 ;
+static const uint8_t P9N2_EX_PPM_IVRMCR_RESERVED_4_7_LEN = 4 ;
+
+static const uint8_t P9N2_C_PPM_IVRMCR_IVRM_VID_VALID = 0 ;
+static const uint8_t P9N2_C_PPM_IVRMCR_IVRM_BYPASS_B = 1 ;
+static const uint8_t P9N2_C_PPM_IVRMCR_IVRM_POWERON = 2 ;
+static const uint8_t P9N2_C_PPM_IVRMCR_IVRM_VREG_SLOW_DC = 3 ;
+static const uint8_t P9N2_C_PPM_IVRMCR_RESERVED_4_7 = 4 ;
+static const uint8_t P9N2_C_PPM_IVRMCR_RESERVED_4_7_LEN = 4 ;
+
+static const uint8_t P9N2_EQ_PPM_IVRMDVR_IVRM_IVID = 0 ;
+static const uint8_t P9N2_EQ_PPM_IVRMDVR_IVRM_IVID_LEN = 8 ;
+static const uint8_t P9N2_EQ_PPM_IVRMDVR_RESERVED_8_10 = 8 ;
+static const uint8_t P9N2_EQ_PPM_IVRMDVR_RESERVED_8_10_LEN = 3 ;
+static const uint8_t P9N2_EQ_PPM_IVRMDVR_IVRM_PFET_STRENGTH_CORE = 11 ;
+static const uint8_t P9N2_EQ_PPM_IVRMDVR_IVRM_PFET_STRENGTH_CORE_LEN = 5 ;
+static const uint8_t P9N2_EQ_PPM_IVRMDVR_RESERVED_16_18 = 16 ;
+static const uint8_t P9N2_EQ_PPM_IVRMDVR_RESERVED_16_18_LEN = 3 ;
+static const uint8_t P9N2_EQ_PPM_IVRMDVR_IVRM_PFET_STRENGTH_CACHE = 19 ;
+static const uint8_t P9N2_EQ_PPM_IVRMDVR_IVRM_PFET_STRENGTH_CACHE_LEN = 5 ;
+
+static const uint8_t P9N2_EX_PPM_IVRMDVR_IVRM_IVID = 0 ;
+static const uint8_t P9N2_EX_PPM_IVRMDVR_IVRM_IVID_LEN = 8 ;
+static const uint8_t P9N2_EX_PPM_IVRMDVR_RESERVED_8_10 = 8 ;
+static const uint8_t P9N2_EX_PPM_IVRMDVR_RESERVED_8_10_LEN = 3 ;
+static const uint8_t P9N2_EX_PPM_IVRMDVR_IVRM_PFET_STRENGTH_CORE = 11 ;
+static const uint8_t P9N2_EX_PPM_IVRMDVR_IVRM_PFET_STRENGTH_CORE_LEN = 5 ;
+static const uint8_t P9N2_EX_PPM_IVRMDVR_RESERVED_16_18 = 16 ;
+static const uint8_t P9N2_EX_PPM_IVRMDVR_RESERVED_16_18_LEN = 3 ;
+static const uint8_t P9N2_EX_PPM_IVRMDVR_IVRM_PFET_STRENGTH_CACHE = 19 ;
+static const uint8_t P9N2_EX_PPM_IVRMDVR_IVRM_PFET_STRENGTH_CACHE_LEN = 5 ;
+
+static const uint8_t P9N2_C_PPM_IVRMDVR_IVRM_IVID = 0 ;
+static const uint8_t P9N2_C_PPM_IVRMDVR_IVRM_IVID_LEN = 8 ;
+static const uint8_t P9N2_C_PPM_IVRMDVR_RESERVED_8_10 = 8 ;
+static const uint8_t P9N2_C_PPM_IVRMDVR_RESERVED_8_10_LEN = 3 ;
+static const uint8_t P9N2_C_PPM_IVRMDVR_IVRM_PFET_STRENGTH_CORE = 11 ;
+static const uint8_t P9N2_C_PPM_IVRMDVR_IVRM_PFET_STRENGTH_CORE_LEN = 5 ;
+static const uint8_t P9N2_C_PPM_IVRMDVR_RESERVED_16_18 = 16 ;
+static const uint8_t P9N2_C_PPM_IVRMDVR_RESERVED_16_18_LEN = 3 ;
+static const uint8_t P9N2_C_PPM_IVRMDVR_IVRM_PFET_STRENGTH_CACHE = 19 ;
+static const uint8_t P9N2_C_PPM_IVRMDVR_IVRM_PFET_STRENGTH_CACHE_LEN = 5 ;
+
+static const uint8_t P9N2_EQ_PPM_IVRMST_IVRM_VID_DONE = 0 ;
+
+static const uint8_t P9N2_EX_PPM_IVRMST_IVRM_VID_DONE = 0 ;
+
+static const uint8_t P9N2_C_PPM_IVRMST_IVRM_VID_DONE = 0 ;
+
+static const uint8_t P9N2_EQ_PPM_PFCS_VDD_PFET_FORCE_STATE = 0 ;
+static const uint8_t P9N2_EQ_PPM_PFCS_VDD_PFET_FORCE_STATE_LEN = 2 ;
+static const uint8_t P9N2_EQ_PPM_PFCS_VCS_PFET_FORCE_STATE = 2 ;
+static const uint8_t P9N2_EQ_PPM_PFCS_VCS_PFET_FORCE_STATE_LEN = 2 ;
+static const uint8_t P9N2_EQ_PPM_PFCS_VDD_PFET_VAL_OVERRIDE = 4 ;
+static const uint8_t P9N2_EQ_PPM_PFCS_VDD_PFET_SEL_OVERRIDE = 5 ;
+static const uint8_t P9N2_EQ_PPM_PFCS_VCS_PFET_VAL_OVERRIDE = 6 ;
+static const uint8_t P9N2_EQ_PPM_PFCS_VCS_PFET_SEL_OVERRIDE = 7 ;
+static const uint8_t P9N2_EQ_PPM_PFCS_VDD_PFET_REGULATION_FINGER_EN = 8 ;
+static const uint8_t P9N2_EQ_PPM_PFCS_VDD_PFET_REGULATION_FINGER_VALUE = 9 ;
+static const uint8_t P9N2_EQ_PPM_PFCS_RESERVED_10_11 = 10 ;
+static const uint8_t P9N2_EQ_PPM_PFCS_RESERVED_10_11_LEN = 2 ;
+static const uint8_t P9N2_EQ_PPM_PFCS_VDD_PFET_ENABLE_VALUE = 12 ;
+static const uint8_t P9N2_EQ_PPM_PFCS_VDD_PFET_ENABLE_VALUE_LEN = 8 ;
+static const uint8_t P9N2_EQ_PPM_PFCS_VDD_PFET_SEL_VALUE = 20 ;
+static const uint8_t P9N2_EQ_PPM_PFCS_VDD_PFET_SEL_VALUE_LEN = 4 ;
+static const uint8_t P9N2_EQ_PPM_PFCS_VCS_PFET_ENABLE_VALUE = 24 ;
+static const uint8_t P9N2_EQ_PPM_PFCS_VCS_PFET_ENABLE_VALUE_LEN = 8 ;
+static const uint8_t P9N2_EQ_PPM_PFCS_VCS_PFET_SEL_VALUE = 32 ;
+static const uint8_t P9N2_EQ_PPM_PFCS_VCS_PFET_SEL_VALUE_LEN = 4 ;
+static const uint8_t P9N2_EQ_PPM_PFCS_VDD_PG_STATE = 42 ;
+static const uint8_t P9N2_EQ_PPM_PFCS_VDD_PG_STATE_LEN = 4 ;
+static const uint8_t P9N2_EQ_PPM_PFCS_VDD_PG_SEL = 46 ;
+static const uint8_t P9N2_EQ_PPM_PFCS_VDD_PG_SEL_LEN = 4 ;
+static const uint8_t P9N2_EQ_PPM_PFCS_VCS_PG_STATE = 50 ;
+static const uint8_t P9N2_EQ_PPM_PFCS_VCS_PG_STATE_LEN = 4 ;
+static const uint8_t P9N2_EQ_PPM_PFCS_VCS_PG_SEL = 54 ;
+static const uint8_t P9N2_EQ_PPM_PFCS_VCS_PG_SEL_LEN = 4 ;
+
+static const uint8_t P9N2_EX_PPM_PFCS_VDD_PFET_FORCE_STATE = 0 ;
+static const uint8_t P9N2_EX_PPM_PFCS_VDD_PFET_FORCE_STATE_LEN = 2 ;
+static const uint8_t P9N2_EX_PPM_PFCS_VCS_PFET_FORCE_STATE = 2 ;
+static const uint8_t P9N2_EX_PPM_PFCS_VCS_PFET_FORCE_STATE_LEN = 2 ;
+static const uint8_t P9N2_EX_PPM_PFCS_VDD_PFET_VAL_OVERRIDE = 4 ;
+static const uint8_t P9N2_EX_PPM_PFCS_VDD_PFET_SEL_OVERRIDE = 5 ;
+static const uint8_t P9N2_EX_PPM_PFCS_VCS_PFET_VAL_OVERRIDE = 6 ;
+static const uint8_t P9N2_EX_PPM_PFCS_VCS_PFET_SEL_OVERRIDE = 7 ;
+static const uint8_t P9N2_EX_PPM_PFCS_VDD_PFET_REGULATION_FINGER_EN = 8 ;
+static const uint8_t P9N2_EX_PPM_PFCS_VDD_PFET_REGULATION_FINGER_VALUE = 9 ;
+static const uint8_t P9N2_EX_PPM_PFCS_RESERVED_10_11 = 10 ;
+static const uint8_t P9N2_EX_PPM_PFCS_RESERVED_10_11_LEN = 2 ;
+static const uint8_t P9N2_EX_PPM_PFCS_VDD_PFET_ENABLE_VALUE = 12 ;
+static const uint8_t P9N2_EX_PPM_PFCS_VDD_PFET_ENABLE_VALUE_LEN = 8 ;
+static const uint8_t P9N2_EX_PPM_PFCS_VDD_PFET_SEL_VALUE = 20 ;
+static const uint8_t P9N2_EX_PPM_PFCS_VDD_PFET_SEL_VALUE_LEN = 4 ;
+static const uint8_t P9N2_EX_PPM_PFCS_VCS_PFET_ENABLE_VALUE = 24 ;
+static const uint8_t P9N2_EX_PPM_PFCS_VCS_PFET_ENABLE_VALUE_LEN = 8 ;
+static const uint8_t P9N2_EX_PPM_PFCS_VCS_PFET_SEL_VALUE = 32 ;
+static const uint8_t P9N2_EX_PPM_PFCS_VCS_PFET_SEL_VALUE_LEN = 4 ;
+static const uint8_t P9N2_EX_PPM_PFCS_VDD_PG_STATE = 42 ;
+static const uint8_t P9N2_EX_PPM_PFCS_VDD_PG_STATE_LEN = 4 ;
+static const uint8_t P9N2_EX_PPM_PFCS_VDD_PG_SEL = 46 ;
+static const uint8_t P9N2_EX_PPM_PFCS_VDD_PG_SEL_LEN = 4 ;
+static const uint8_t P9N2_EX_PPM_PFCS_VCS_PG_STATE = 50 ;
+static const uint8_t P9N2_EX_PPM_PFCS_VCS_PG_STATE_LEN = 4 ;
+static const uint8_t P9N2_EX_PPM_PFCS_VCS_PG_SEL = 54 ;
+static const uint8_t P9N2_EX_PPM_PFCS_VCS_PG_SEL_LEN = 4 ;
+
+static const uint8_t P9N2_C_PPM_PFCS_VDD_PFET_FORCE_STATE = 0 ;
+static const uint8_t P9N2_C_PPM_PFCS_VDD_PFET_FORCE_STATE_LEN = 2 ;
+static const uint8_t P9N2_C_PPM_PFCS_VCS_PFET_FORCE_STATE = 2 ;
+static const uint8_t P9N2_C_PPM_PFCS_VCS_PFET_FORCE_STATE_LEN = 2 ;
+static const uint8_t P9N2_C_PPM_PFCS_VDD_PFET_VAL_OVERRIDE = 4 ;
+static const uint8_t P9N2_C_PPM_PFCS_VDD_PFET_SEL_OVERRIDE = 5 ;
+static const uint8_t P9N2_C_PPM_PFCS_VCS_PFET_VAL_OVERRIDE = 6 ;
+static const uint8_t P9N2_C_PPM_PFCS_VCS_PFET_SEL_OVERRIDE = 7 ;
+static const uint8_t P9N2_C_PPM_PFCS_VDD_PFET_REGULATION_FINGER_EN = 8 ;
+static const uint8_t P9N2_C_PPM_PFCS_VDD_PFET_REGULATION_FINGER_VALUE = 9 ;
+static const uint8_t P9N2_C_PPM_PFCS_RESERVED_10_11 = 10 ;
+static const uint8_t P9N2_C_PPM_PFCS_RESERVED_10_11_LEN = 2 ;
+static const uint8_t P9N2_C_PPM_PFCS_VDD_PFET_ENABLE_VALUE = 12 ;
+static const uint8_t P9N2_C_PPM_PFCS_VDD_PFET_ENABLE_VALUE_LEN = 8 ;
+static const uint8_t P9N2_C_PPM_PFCS_VDD_PFET_SEL_VALUE = 20 ;
+static const uint8_t P9N2_C_PPM_PFCS_VDD_PFET_SEL_VALUE_LEN = 4 ;
+static const uint8_t P9N2_C_PPM_PFCS_VCS_PFET_ENABLE_VALUE = 24 ;
+static const uint8_t P9N2_C_PPM_PFCS_VCS_PFET_ENABLE_VALUE_LEN = 8 ;
+static const uint8_t P9N2_C_PPM_PFCS_VCS_PFET_SEL_VALUE = 32 ;
+static const uint8_t P9N2_C_PPM_PFCS_VCS_PFET_SEL_VALUE_LEN = 4 ;
+static const uint8_t P9N2_C_PPM_PFCS_VDD_PG_STATE = 42 ;
+static const uint8_t P9N2_C_PPM_PFCS_VDD_PG_STATE_LEN = 4 ;
+static const uint8_t P9N2_C_PPM_PFCS_VDD_PG_SEL = 46 ;
+static const uint8_t P9N2_C_PPM_PFCS_VDD_PG_SEL_LEN = 4 ;
+static const uint8_t P9N2_C_PPM_PFCS_VCS_PG_STATE = 50 ;
+static const uint8_t P9N2_C_PPM_PFCS_VCS_PG_STATE_LEN = 4 ;
+static const uint8_t P9N2_C_PPM_PFCS_VCS_PG_SEL = 54 ;
+static const uint8_t P9N2_C_PPM_PFCS_VCS_PG_SEL_LEN = 4 ;
+
+static const uint8_t P9N2_EQ_PPM_PFDLY_POWDN_DLY = 0 ;
+static const uint8_t P9N2_EQ_PPM_PFDLY_POWDN_DLY_LEN = 4 ;
+static const uint8_t P9N2_EQ_PPM_PFDLY_POWUP_DLY = 4 ;
+static const uint8_t P9N2_EQ_PPM_PFDLY_POWUP_DLY_LEN = 4 ;
+
+static const uint8_t P9N2_EX_PPM_PFDLY_POWDN_DLY = 0 ;
+static const uint8_t P9N2_EX_PPM_PFDLY_POWDN_DLY_LEN = 4 ;
+static const uint8_t P9N2_EX_PPM_PFDLY_POWUP_DLY = 4 ;
+static const uint8_t P9N2_EX_PPM_PFDLY_POWUP_DLY_LEN = 4 ;
+
+static const uint8_t P9N2_C_PPM_PFDLY_POWDN_DLY = 0 ;
+static const uint8_t P9N2_C_PPM_PFDLY_POWDN_DLY_LEN = 4 ;
+static const uint8_t P9N2_C_PPM_PFDLY_POWUP_DLY = 4 ;
+static const uint8_t P9N2_C_PPM_PFDLY_POWUP_DLY_LEN = 4 ;
+
+static const uint8_t P9N2_EQ_PPM_PFOFF_VDD_VOFF_SEL = 0 ;
+static const uint8_t P9N2_EQ_PPM_PFOFF_VDD_VOFF_SEL_LEN = 4 ;
+static const uint8_t P9N2_EQ_PPM_PFOFF_VCS_VOFF_SEL = 4 ;
+static const uint8_t P9N2_EQ_PPM_PFOFF_VCS_VOFF_SEL_LEN = 4 ;
+
+static const uint8_t P9N2_EX_PPM_PFOFF_VDD_VOFF_SEL = 0 ;
+static const uint8_t P9N2_EX_PPM_PFOFF_VDD_VOFF_SEL_LEN = 4 ;
+static const uint8_t P9N2_EX_PPM_PFOFF_VCS_VOFF_SEL = 4 ;
+static const uint8_t P9N2_EX_PPM_PFOFF_VCS_VOFF_SEL_LEN = 4 ;
+
+static const uint8_t P9N2_C_PPM_PFOFF_VDD_VOFF_SEL = 0 ;
+static const uint8_t P9N2_C_PPM_PFOFF_VDD_VOFF_SEL_LEN = 4 ;
+static const uint8_t P9N2_C_PPM_PFOFF_VCS_VOFF_SEL = 4 ;
+static const uint8_t P9N2_C_PPM_PFOFF_VCS_VOFF_SEL_LEN = 4 ;
+
+static const uint8_t P9N2_EQ_PPM_PFSNS_VDD_PFETS_ENABLED_SENSE = 0 ;
+static const uint8_t P9N2_EQ_PPM_PFSNS_VDD_PFETS_DISABLED_SENSE = 1 ;
+static const uint8_t P9N2_EQ_PPM_PFSNS_VCS_PFETS_ENABLED_SENSE = 2 ;
+static const uint8_t P9N2_EQ_PPM_PFSNS_VCS_PFETS_DISABLED_SENSE = 3 ;
+static const uint8_t P9N2_EQ_PPM_PFSNS_RESERVED_4_15 = 4 ;
+static const uint8_t P9N2_EQ_PPM_PFSNS_RESERVED_4_15_LEN = 12 ;
+static const uint8_t P9N2_EQ_PPM_PFSNS_TP_VDD_PFET_ENABLE_ACTUAL = 16 ;
+static const uint8_t P9N2_EQ_PPM_PFSNS_TP_VDD_PFET_ENABLE_ACTUAL_LEN = 8 ;
+static const uint8_t P9N2_EQ_PPM_PFSNS_TP_VCS_PFET_ENABLE_ACTUAL = 24 ;
+static const uint8_t P9N2_EQ_PPM_PFSNS_TP_VCS_PFET_ENABLE_ACTUAL_LEN = 8 ;
+static const uint8_t P9N2_EQ_PPM_PFSNS_VDD_PG_STATE = 42 ;
+static const uint8_t P9N2_EQ_PPM_PFSNS_VDD_PG_STATE_LEN = 4 ;
+static const uint8_t P9N2_EQ_PPM_PFSNS_VDD_PG_SEL = 46 ;
+static const uint8_t P9N2_EQ_PPM_PFSNS_VDD_PG_SEL_LEN = 4 ;
+static const uint8_t P9N2_EQ_PPM_PFSNS_VCS_PG_STATE = 50 ;
+static const uint8_t P9N2_EQ_PPM_PFSNS_VCS_PG_STATE_LEN = 4 ;
+static const uint8_t P9N2_EQ_PPM_PFSNS_VCS_PG_SEL = 54 ;
+static const uint8_t P9N2_EQ_PPM_PFSNS_VCS_PG_SEL_LEN = 4 ;
+
+static const uint8_t P9N2_EX_PPM_PFSNS_VDD_PFETS_ENABLED_SENSE = 0 ;
+static const uint8_t P9N2_EX_PPM_PFSNS_VDD_PFETS_DISABLED_SENSE = 1 ;
+static const uint8_t P9N2_EX_PPM_PFSNS_VCS_PFETS_ENABLED_SENSE = 2 ;
+static const uint8_t P9N2_EX_PPM_PFSNS_VCS_PFETS_DISABLED_SENSE = 3 ;
+static const uint8_t P9N2_EX_PPM_PFSNS_RESERVED_4_15 = 4 ;
+static const uint8_t P9N2_EX_PPM_PFSNS_RESERVED_4_15_LEN = 12 ;
+static const uint8_t P9N2_EX_PPM_PFSNS_TP_VDD_PFET_ENABLE_ACTUAL = 16 ;
+static const uint8_t P9N2_EX_PPM_PFSNS_TP_VDD_PFET_ENABLE_ACTUAL_LEN = 8 ;
+static const uint8_t P9N2_EX_PPM_PFSNS_TP_VCS_PFET_ENABLE_ACTUAL = 24 ;
+static const uint8_t P9N2_EX_PPM_PFSNS_TP_VCS_PFET_ENABLE_ACTUAL_LEN = 8 ;
+static const uint8_t P9N2_EX_PPM_PFSNS_VDD_PG_STATE = 42 ;
+static const uint8_t P9N2_EX_PPM_PFSNS_VDD_PG_STATE_LEN = 4 ;
+static const uint8_t P9N2_EX_PPM_PFSNS_VDD_PG_SEL = 46 ;
+static const uint8_t P9N2_EX_PPM_PFSNS_VDD_PG_SEL_LEN = 4 ;
+static const uint8_t P9N2_EX_PPM_PFSNS_VCS_PG_STATE = 50 ;
+static const uint8_t P9N2_EX_PPM_PFSNS_VCS_PG_STATE_LEN = 4 ;
+static const uint8_t P9N2_EX_PPM_PFSNS_VCS_PG_SEL = 54 ;
+static const uint8_t P9N2_EX_PPM_PFSNS_VCS_PG_SEL_LEN = 4 ;
+
+static const uint8_t P9N2_C_PPM_PFSNS_VDD_PFETS_ENABLED_SENSE = 0 ;
+static const uint8_t P9N2_C_PPM_PFSNS_VDD_PFETS_DISABLED_SENSE = 1 ;
+static const uint8_t P9N2_C_PPM_PFSNS_VCS_PFETS_ENABLED_SENSE = 2 ;
+static const uint8_t P9N2_C_PPM_PFSNS_VCS_PFETS_DISABLED_SENSE = 3 ;
+static const uint8_t P9N2_C_PPM_PFSNS_RESERVED_4_15 = 4 ;
+static const uint8_t P9N2_C_PPM_PFSNS_RESERVED_4_15_LEN = 12 ;
+static const uint8_t P9N2_C_PPM_PFSNS_TP_VDD_PFET_ENABLE_ACTUAL = 16 ;
+static const uint8_t P9N2_C_PPM_PFSNS_TP_VDD_PFET_ENABLE_ACTUAL_LEN = 8 ;
+static const uint8_t P9N2_C_PPM_PFSNS_TP_VCS_PFET_ENABLE_ACTUAL = 24 ;
+static const uint8_t P9N2_C_PPM_PFSNS_TP_VCS_PFET_ENABLE_ACTUAL_LEN = 8 ;
+static const uint8_t P9N2_C_PPM_PFSNS_VDD_PG_STATE = 42 ;
+static const uint8_t P9N2_C_PPM_PFSNS_VDD_PG_STATE_LEN = 4 ;
+static const uint8_t P9N2_C_PPM_PFSNS_VDD_PG_SEL = 46 ;
+static const uint8_t P9N2_C_PPM_PFSNS_VDD_PG_SEL_LEN = 4 ;
+static const uint8_t P9N2_C_PPM_PFSNS_VCS_PG_STATE = 50 ;
+static const uint8_t P9N2_C_PPM_PFSNS_VCS_PG_STATE_LEN = 4 ;
+static const uint8_t P9N2_C_PPM_PFSNS_VCS_PG_SEL = 54 ;
+static const uint8_t P9N2_C_PPM_PFSNS_VCS_PG_SEL_LEN = 4 ;
+
+static const uint8_t P9N2_EQ_PPM_PIG_REQ_INTR_TYPE = 1 ;
+static const uint8_t P9N2_EQ_PPM_PIG_REQ_INTR_TYPE_LEN = 3 ;
+static const uint8_t P9N2_EQ_PPM_PIG_REQ_INTR_PAYLOAD = 4 ;
+static const uint8_t P9N2_EQ_PPM_PIG_REQ_INTR_PAYLOAD_LEN = 12 ;
+static const uint8_t P9N2_EQ_PPM_PIG_GRANTED_PACKET = 16 ;
+static const uint8_t P9N2_EQ_PPM_PIG_GRANTED_PACKET_LEN = 16 ;
+static const uint8_t P9N2_EQ_PPM_PIG_INTR_GRANTED = 32 ;
+static const uint8_t P9N2_EQ_PPM_PIG_GRANTED_SOURCE = 34 ;
+static const uint8_t P9N2_EQ_PPM_PIG_GRANTED_SOURCE_LEN = 2 ;
+static const uint8_t P9N2_EQ_PPM_PIG_PENDING_SOURCE = 37 ;
+static const uint8_t P9N2_EQ_PPM_PIG_PENDING_SOURCE_LEN = 3 ;
+static const uint8_t P9N2_EQ_PPM_PIG_NETWORK_RESET_OCCURRED = 40 ;
+
+static const uint8_t P9N2_EX_PPM_PIG_REQ_INTR_TYPE = 1 ;
+static const uint8_t P9N2_EX_PPM_PIG_REQ_INTR_TYPE_LEN = 3 ;
+static const uint8_t P9N2_EX_PPM_PIG_REQ_INTR_PAYLOAD = 4 ;
+static const uint8_t P9N2_EX_PPM_PIG_REQ_INTR_PAYLOAD_LEN = 12 ;
+static const uint8_t P9N2_EX_PPM_PIG_GRANTED_PACKET = 16 ;
+static const uint8_t P9N2_EX_PPM_PIG_GRANTED_PACKET_LEN = 16 ;
+static const uint8_t P9N2_EX_PPM_PIG_INTR_GRANTED = 32 ;
+static const uint8_t P9N2_EX_PPM_PIG_GRANTED_SOURCE = 34 ;
+static const uint8_t P9N2_EX_PPM_PIG_GRANTED_SOURCE_LEN = 2 ;
+static const uint8_t P9N2_EX_PPM_PIG_PENDING_SOURCE = 37 ;
+static const uint8_t P9N2_EX_PPM_PIG_PENDING_SOURCE_LEN = 3 ;
+static const uint8_t P9N2_EX_PPM_PIG_NETWORK_RESET_OCCURRED = 40 ;
+
+static const uint8_t P9N2_C_PPM_PIG_REQ_INTR_TYPE = 1 ;
+static const uint8_t P9N2_C_PPM_PIG_REQ_INTR_TYPE_LEN = 3 ;
+static const uint8_t P9N2_C_PPM_PIG_REQ_INTR_PAYLOAD = 4 ;
+static const uint8_t P9N2_C_PPM_PIG_REQ_INTR_PAYLOAD_LEN = 12 ;
+static const uint8_t P9N2_C_PPM_PIG_GRANTED_PACKET = 16 ;
+static const uint8_t P9N2_C_PPM_PIG_GRANTED_PACKET_LEN = 16 ;
+static const uint8_t P9N2_C_PPM_PIG_INTR_GRANTED = 32 ;
+static const uint8_t P9N2_C_PPM_PIG_GRANTED_SOURCE = 34 ;
+static const uint8_t P9N2_C_PPM_PIG_GRANTED_SOURCE_LEN = 2 ;
+static const uint8_t P9N2_C_PPM_PIG_PENDING_SOURCE = 37 ;
+static const uint8_t P9N2_C_PPM_PIG_PENDING_SOURCE_LEN = 3 ;
+static const uint8_t P9N2_C_PPM_PIG_NETWORK_RESET_OCCURRED = 40 ;
+
+static const uint8_t P9N2_EQ_PPM_SCRATCH0_DATA = 0 ;
+static const uint8_t P9N2_EQ_PPM_SCRATCH0_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_EX_PPM_SCRATCH0_DATA = 0 ;
+static const uint8_t P9N2_EX_PPM_SCRATCH0_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_C_PPM_SCRATCH0_DATA = 0 ;
+static const uint8_t P9N2_C_PPM_SCRATCH0_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_EQ_PPM_SCRATCH1_DATA = 0 ;
+static const uint8_t P9N2_EQ_PPM_SCRATCH1_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_EX_PPM_SCRATCH1_DATA = 0 ;
+static const uint8_t P9N2_EX_PPM_SCRATCH1_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_C_PPM_SCRATCH1_DATA = 0 ;
+static const uint8_t P9N2_C_PPM_SCRATCH1_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_EQ_PPM_SPWKUP_FSP_FSP_SPECIAL_WKUP = 0 ;
+
+static const uint8_t P9N2_EX_PPM_SPWKUP_FSP_FSP_SPECIAL_WKUP = 0 ;
+
+static const uint8_t P9N2_C_PPM_SPWKUP_FSP_FSP_SPECIAL_WKUP = 0 ;
+
+static const uint8_t P9N2_EQ_PPM_SPWKUP_HYP_HYP_SPECIAL_WKUP = 0 ;
+
+static const uint8_t P9N2_EX_PPM_SPWKUP_HYP_HYP_SPECIAL_WKUP = 0 ;
+
+static const uint8_t P9N2_C_PPM_SPWKUP_HYP_HYP_SPECIAL_WKUP = 0 ;
+
+static const uint8_t P9N2_EQ_PPM_SPWKUP_OCC_OCC_SPECIAL_WKUP = 0 ;
+
+static const uint8_t P9N2_EX_PPM_SPWKUP_OCC_OCC_SPECIAL_WKUP = 0 ;
+
+static const uint8_t P9N2_C_PPM_SPWKUP_OCC_OCC_SPECIAL_WKUP = 0 ;
+
+static const uint8_t P9N2_EQ_PPM_SPWKUP_OTR_OTR_SPECIAL_WKUP = 0 ;
+
+static const uint8_t P9N2_EX_PPM_SPWKUP_OTR_OTR_SPECIAL_WKUP = 0 ;
+
+static const uint8_t P9N2_C_PPM_SPWKUP_OTR_OTR_SPECIAL_WKUP = 0 ;
+
+static const uint8_t P9N2_EQ_PPM_SSHFSP_STOP_GATED = 0 ;
+static const uint8_t P9N2_EQ_PPM_SSHFSP_SPECIAL_WKUP_DONE = 1 ;
+static const uint8_t P9N2_EQ_PPM_SSHFSP_STOP_TRANSITION = 2 ;
+static const uint8_t P9N2_EQ_PPM_SSHFSP_STOP_TRANSITION_LEN = 2 ;
+static const uint8_t P9N2_EQ_PPM_SSHFSP_REQ_STOP_LEVEL = 4 ;
+static const uint8_t P9N2_EQ_PPM_SSHFSP_REQ_STOP_LEVEL_LEN = 4 ;
+static const uint8_t P9N2_EQ_PPM_SSHFSP_ACT_STOP_LEVEL = 8 ;
+static const uint8_t P9N2_EQ_PPM_SSHFSP_ACT_STOP_LEVEL_LEN = 4 ;
+static const uint8_t P9N2_EQ_PPM_SSHFSP_DEEPEST_REQ_STOP_LEVEL_FSP = 12 ;
+static const uint8_t P9N2_EQ_PPM_SSHFSP_DEEPEST_REQ_STOP_LEVEL_FSP_LEN = 4 ;
+static const uint8_t P9N2_EQ_PPM_SSHFSP_DEEPEST_ACT_STOP_LEVEL_FSP = 16 ;
+static const uint8_t P9N2_EQ_PPM_SSHFSP_DEEPEST_ACT_STOP_LEVEL_FSP_LEN = 4 ;
+static const uint8_t P9N2_EQ_PPM_SSHFSP_IVRM_ENABLED_HISTORY_FSP = 20 ;
+
+static const uint8_t P9N2_EX_PPM_SSHFSP_STOP_GATED = 0 ;
+static const uint8_t P9N2_EX_PPM_SSHFSP_SPECIAL_WKUP_DONE = 1 ;
+static const uint8_t P9N2_EX_PPM_SSHFSP_STOP_TRANSITION = 2 ;
+static const uint8_t P9N2_EX_PPM_SSHFSP_STOP_TRANSITION_LEN = 2 ;
+static const uint8_t P9N2_EX_PPM_SSHFSP_REQ_STOP_LEVEL = 4 ;
+static const uint8_t P9N2_EX_PPM_SSHFSP_REQ_STOP_LEVEL_LEN = 4 ;
+static const uint8_t P9N2_EX_PPM_SSHFSP_ACT_STOP_LEVEL = 8 ;
+static const uint8_t P9N2_EX_PPM_SSHFSP_ACT_STOP_LEVEL_LEN = 4 ;
+static const uint8_t P9N2_EX_PPM_SSHFSP_DEEPEST_REQ_STOP_LEVEL_FSP = 12 ;
+static const uint8_t P9N2_EX_PPM_SSHFSP_DEEPEST_REQ_STOP_LEVEL_FSP_LEN = 4 ;
+static const uint8_t P9N2_EX_PPM_SSHFSP_DEEPEST_ACT_STOP_LEVEL_FSP = 16 ;
+static const uint8_t P9N2_EX_PPM_SSHFSP_DEEPEST_ACT_STOP_LEVEL_FSP_LEN = 4 ;
+static const uint8_t P9N2_EX_PPM_SSHFSP_IVRM_ENABLED_HISTORY_FSP = 20 ;
+
+static const uint8_t P9N2_C_PPM_SSHFSP_STOP_GATED = 0 ;
+static const uint8_t P9N2_C_PPM_SSHFSP_SPECIAL_WKUP_DONE = 1 ;
+static const uint8_t P9N2_C_PPM_SSHFSP_STOP_TRANSITION = 2 ;
+static const uint8_t P9N2_C_PPM_SSHFSP_STOP_TRANSITION_LEN = 2 ;
+static const uint8_t P9N2_C_PPM_SSHFSP_REQ_STOP_LEVEL = 4 ;
+static const uint8_t P9N2_C_PPM_SSHFSP_REQ_STOP_LEVEL_LEN = 4 ;
+static const uint8_t P9N2_C_PPM_SSHFSP_ACT_STOP_LEVEL = 8 ;
+static const uint8_t P9N2_C_PPM_SSHFSP_ACT_STOP_LEVEL_LEN = 4 ;
+static const uint8_t P9N2_C_PPM_SSHFSP_DEEPEST_REQ_STOP_LEVEL_FSP = 12 ;
+static const uint8_t P9N2_C_PPM_SSHFSP_DEEPEST_REQ_STOP_LEVEL_FSP_LEN = 4 ;
+static const uint8_t P9N2_C_PPM_SSHFSP_DEEPEST_ACT_STOP_LEVEL_FSP = 16 ;
+static const uint8_t P9N2_C_PPM_SSHFSP_DEEPEST_ACT_STOP_LEVEL_FSP_LEN = 4 ;
+static const uint8_t P9N2_C_PPM_SSHFSP_IVRM_ENABLED_HISTORY_FSP = 20 ;
+
+static const uint8_t P9N2_EQ_PPM_SSHHYP_STOP_GATED = 0 ;
+static const uint8_t P9N2_EQ_PPM_SSHHYP_SPECIAL_WKUP_DONE = 1 ;
+static const uint8_t P9N2_EQ_PPM_SSHHYP_STOP_TRANSITION = 2 ;
+static const uint8_t P9N2_EQ_PPM_SSHHYP_STOP_TRANSITION_LEN = 2 ;
+static const uint8_t P9N2_EQ_PPM_SSHHYP_REQ_STOP_LEVEL = 4 ;
+static const uint8_t P9N2_EQ_PPM_SSHHYP_REQ_STOP_LEVEL_LEN = 4 ;
+static const uint8_t P9N2_EQ_PPM_SSHHYP_ACT_STOP_LEVEL = 8 ;
+static const uint8_t P9N2_EQ_PPM_SSHHYP_ACT_STOP_LEVEL_LEN = 4 ;
+static const uint8_t P9N2_EQ_PPM_SSHHYP_DEEPEST_REQ_STOP_LEVEL_HYP = 12 ;
+static const uint8_t P9N2_EQ_PPM_SSHHYP_DEEPEST_REQ_STOP_LEVEL_HYP_LEN = 4 ;
+static const uint8_t P9N2_EQ_PPM_SSHHYP_DEEPEST_ACT_STOP_LEVEL_HYP = 16 ;
+static const uint8_t P9N2_EQ_PPM_SSHHYP_DEEPEST_ACT_STOP_LEVEL_HYP_LEN = 4 ;
+static const uint8_t P9N2_EQ_PPM_SSHHYP_IVRM_ENABLED_HISTORY_HYP = 20 ;
+
+static const uint8_t P9N2_EX_PPM_SSHHYP_STOP_GATED = 0 ;
+static const uint8_t P9N2_EX_PPM_SSHHYP_SPECIAL_WKUP_DONE = 1 ;
+static const uint8_t P9N2_EX_PPM_SSHHYP_STOP_TRANSITION = 2 ;
+static const uint8_t P9N2_EX_PPM_SSHHYP_STOP_TRANSITION_LEN = 2 ;
+static const uint8_t P9N2_EX_PPM_SSHHYP_REQ_STOP_LEVEL = 4 ;
+static const uint8_t P9N2_EX_PPM_SSHHYP_REQ_STOP_LEVEL_LEN = 4 ;
+static const uint8_t P9N2_EX_PPM_SSHHYP_ACT_STOP_LEVEL = 8 ;
+static const uint8_t P9N2_EX_PPM_SSHHYP_ACT_STOP_LEVEL_LEN = 4 ;
+static const uint8_t P9N2_EX_PPM_SSHHYP_DEEPEST_REQ_STOP_LEVEL_HYP = 12 ;
+static const uint8_t P9N2_EX_PPM_SSHHYP_DEEPEST_REQ_STOP_LEVEL_HYP_LEN = 4 ;
+static const uint8_t P9N2_EX_PPM_SSHHYP_DEEPEST_ACT_STOP_LEVEL_HYP = 16 ;
+static const uint8_t P9N2_EX_PPM_SSHHYP_DEEPEST_ACT_STOP_LEVEL_HYP_LEN = 4 ;
+static const uint8_t P9N2_EX_PPM_SSHHYP_IVRM_ENABLED_HISTORY_HYP = 20 ;
+
+static const uint8_t P9N2_C_PPM_SSHHYP_STOP_GATED = 0 ;
+static const uint8_t P9N2_C_PPM_SSHHYP_SPECIAL_WKUP_DONE = 1 ;
+static const uint8_t P9N2_C_PPM_SSHHYP_STOP_TRANSITION = 2 ;
+static const uint8_t P9N2_C_PPM_SSHHYP_STOP_TRANSITION_LEN = 2 ;
+static const uint8_t P9N2_C_PPM_SSHHYP_REQ_STOP_LEVEL = 4 ;
+static const uint8_t P9N2_C_PPM_SSHHYP_REQ_STOP_LEVEL_LEN = 4 ;
+static const uint8_t P9N2_C_PPM_SSHHYP_ACT_STOP_LEVEL = 8 ;
+static const uint8_t P9N2_C_PPM_SSHHYP_ACT_STOP_LEVEL_LEN = 4 ;
+static const uint8_t P9N2_C_PPM_SSHHYP_DEEPEST_REQ_STOP_LEVEL_HYP = 12 ;
+static const uint8_t P9N2_C_PPM_SSHHYP_DEEPEST_REQ_STOP_LEVEL_HYP_LEN = 4 ;
+static const uint8_t P9N2_C_PPM_SSHHYP_DEEPEST_ACT_STOP_LEVEL_HYP = 16 ;
+static const uint8_t P9N2_C_PPM_SSHHYP_DEEPEST_ACT_STOP_LEVEL_HYP_LEN = 4 ;
+static const uint8_t P9N2_C_PPM_SSHHYP_IVRM_ENABLED_HISTORY_HYP = 20 ;
+
+static const uint8_t P9N2_EQ_PPM_SSHOCC_STOP_GATED = 0 ;
+static const uint8_t P9N2_EQ_PPM_SSHOCC_SPECIAL_WKUP_DONE = 1 ;
+static const uint8_t P9N2_EQ_PPM_SSHOCC_STOP_TRANSITION = 2 ;
+static const uint8_t P9N2_EQ_PPM_SSHOCC_STOP_TRANSITION_LEN = 2 ;
+static const uint8_t P9N2_EQ_PPM_SSHOCC_REQ_STOP_LEVEL = 4 ;
+static const uint8_t P9N2_EQ_PPM_SSHOCC_REQ_STOP_LEVEL_LEN = 4 ;
+static const uint8_t P9N2_EQ_PPM_SSHOCC_ACT_STOP_LEVEL = 8 ;
+static const uint8_t P9N2_EQ_PPM_SSHOCC_ACT_STOP_LEVEL_LEN = 4 ;
+static const uint8_t P9N2_EQ_PPM_SSHOCC_DEEPEST_REQ_STOP_LEVEL_OCC = 12 ;
+static const uint8_t P9N2_EQ_PPM_SSHOCC_DEEPEST_REQ_STOP_LEVEL_OCC_LEN = 4 ;
+static const uint8_t P9N2_EQ_PPM_SSHOCC_DEEPEST_ACT_STOP_LEVEL_OCC = 16 ;
+static const uint8_t P9N2_EQ_PPM_SSHOCC_DEEPEST_ACT_STOP_LEVEL_OCC_LEN = 4 ;
+static const uint8_t P9N2_EQ_PPM_SSHOCC_IVRM_ENABLED_HISTORY_OCC = 20 ;
+
+static const uint8_t P9N2_EX_PPM_SSHOCC_STOP_GATED = 0 ;
+static const uint8_t P9N2_EX_PPM_SSHOCC_SPECIAL_WKUP_DONE = 1 ;
+static const uint8_t P9N2_EX_PPM_SSHOCC_STOP_TRANSITION = 2 ;
+static const uint8_t P9N2_EX_PPM_SSHOCC_STOP_TRANSITION_LEN = 2 ;
+static const uint8_t P9N2_EX_PPM_SSHOCC_REQ_STOP_LEVEL = 4 ;
+static const uint8_t P9N2_EX_PPM_SSHOCC_REQ_STOP_LEVEL_LEN = 4 ;
+static const uint8_t P9N2_EX_PPM_SSHOCC_ACT_STOP_LEVEL = 8 ;
+static const uint8_t P9N2_EX_PPM_SSHOCC_ACT_STOP_LEVEL_LEN = 4 ;
+static const uint8_t P9N2_EX_PPM_SSHOCC_DEEPEST_REQ_STOP_LEVEL_OCC = 12 ;
+static const uint8_t P9N2_EX_PPM_SSHOCC_DEEPEST_REQ_STOP_LEVEL_OCC_LEN = 4 ;
+static const uint8_t P9N2_EX_PPM_SSHOCC_DEEPEST_ACT_STOP_LEVEL_OCC = 16 ;
+static const uint8_t P9N2_EX_PPM_SSHOCC_DEEPEST_ACT_STOP_LEVEL_OCC_LEN = 4 ;
+static const uint8_t P9N2_EX_PPM_SSHOCC_IVRM_ENABLED_HISTORY_OCC = 20 ;
+
+static const uint8_t P9N2_C_PPM_SSHOCC_STOP_GATED = 0 ;
+static const uint8_t P9N2_C_PPM_SSHOCC_SPECIAL_WKUP_DONE = 1 ;
+static const uint8_t P9N2_C_PPM_SSHOCC_STOP_TRANSITION = 2 ;
+static const uint8_t P9N2_C_PPM_SSHOCC_STOP_TRANSITION_LEN = 2 ;
+static const uint8_t P9N2_C_PPM_SSHOCC_REQ_STOP_LEVEL = 4 ;
+static const uint8_t P9N2_C_PPM_SSHOCC_REQ_STOP_LEVEL_LEN = 4 ;
+static const uint8_t P9N2_C_PPM_SSHOCC_ACT_STOP_LEVEL = 8 ;
+static const uint8_t P9N2_C_PPM_SSHOCC_ACT_STOP_LEVEL_LEN = 4 ;
+static const uint8_t P9N2_C_PPM_SSHOCC_DEEPEST_REQ_STOP_LEVEL_OCC = 12 ;
+static const uint8_t P9N2_C_PPM_SSHOCC_DEEPEST_REQ_STOP_LEVEL_OCC_LEN = 4 ;
+static const uint8_t P9N2_C_PPM_SSHOCC_DEEPEST_ACT_STOP_LEVEL_OCC = 16 ;
+static const uint8_t P9N2_C_PPM_SSHOCC_DEEPEST_ACT_STOP_LEVEL_OCC_LEN = 4 ;
+static const uint8_t P9N2_C_PPM_SSHOCC_IVRM_ENABLED_HISTORY_OCC = 20 ;
+
+static const uint8_t P9N2_EQ_PPM_SSHOTR_STOP_GATED = 0 ;
+static const uint8_t P9N2_EQ_PPM_SSHOTR_SPECIAL_WKUP_DONE = 1 ;
+static const uint8_t P9N2_EQ_PPM_SSHOTR_STOP_TRANSITION = 2 ;
+static const uint8_t P9N2_EQ_PPM_SSHOTR_STOP_TRANSITION_LEN = 2 ;
+static const uint8_t P9N2_EQ_PPM_SSHOTR_REQ_STOP_LEVEL = 4 ;
+static const uint8_t P9N2_EQ_PPM_SSHOTR_REQ_STOP_LEVEL_LEN = 4 ;
+static const uint8_t P9N2_EQ_PPM_SSHOTR_ACT_STOP_LEVEL = 8 ;
+static const uint8_t P9N2_EQ_PPM_SSHOTR_ACT_STOP_LEVEL_LEN = 4 ;
+static const uint8_t P9N2_EQ_PPM_SSHOTR_DEEPEST_REQ_STOP_LEVEL_OTR = 12 ;
+static const uint8_t P9N2_EQ_PPM_SSHOTR_DEEPEST_REQ_STOP_LEVEL_OTR_LEN = 4 ;
+static const uint8_t P9N2_EQ_PPM_SSHOTR_DEEPEST_ACT_STOP_LEVEL_OTR = 16 ;
+static const uint8_t P9N2_EQ_PPM_SSHOTR_DEEPEST_ACT_STOP_LEVEL_OTR_LEN = 4 ;
+static const uint8_t P9N2_EQ_PPM_SSHOTR_IVRM_ENABLED_HISTORY_OTR = 20 ;
+
+static const uint8_t P9N2_EX_PPM_SSHOTR_STOP_GATED = 0 ;
+static const uint8_t P9N2_EX_PPM_SSHOTR_SPECIAL_WKUP_DONE = 1 ;
+static const uint8_t P9N2_EX_PPM_SSHOTR_STOP_TRANSITION = 2 ;
+static const uint8_t P9N2_EX_PPM_SSHOTR_STOP_TRANSITION_LEN = 2 ;
+static const uint8_t P9N2_EX_PPM_SSHOTR_REQ_STOP_LEVEL = 4 ;
+static const uint8_t P9N2_EX_PPM_SSHOTR_REQ_STOP_LEVEL_LEN = 4 ;
+static const uint8_t P9N2_EX_PPM_SSHOTR_ACT_STOP_LEVEL = 8 ;
+static const uint8_t P9N2_EX_PPM_SSHOTR_ACT_STOP_LEVEL_LEN = 4 ;
+static const uint8_t P9N2_EX_PPM_SSHOTR_DEEPEST_REQ_STOP_LEVEL_OTR = 12 ;
+static const uint8_t P9N2_EX_PPM_SSHOTR_DEEPEST_REQ_STOP_LEVEL_OTR_LEN = 4 ;
+static const uint8_t P9N2_EX_PPM_SSHOTR_DEEPEST_ACT_STOP_LEVEL_OTR = 16 ;
+static const uint8_t P9N2_EX_PPM_SSHOTR_DEEPEST_ACT_STOP_LEVEL_OTR_LEN = 4 ;
+static const uint8_t P9N2_EX_PPM_SSHOTR_IVRM_ENABLED_HISTORY_OTR = 20 ;
+
+static const uint8_t P9N2_C_PPM_SSHOTR_STOP_GATED = 0 ;
+static const uint8_t P9N2_C_PPM_SSHOTR_SPECIAL_WKUP_DONE = 1 ;
+static const uint8_t P9N2_C_PPM_SSHOTR_STOP_TRANSITION = 2 ;
+static const uint8_t P9N2_C_PPM_SSHOTR_STOP_TRANSITION_LEN = 2 ;
+static const uint8_t P9N2_C_PPM_SSHOTR_REQ_STOP_LEVEL = 4 ;
+static const uint8_t P9N2_C_PPM_SSHOTR_REQ_STOP_LEVEL_LEN = 4 ;
+static const uint8_t P9N2_C_PPM_SSHOTR_ACT_STOP_LEVEL = 8 ;
+static const uint8_t P9N2_C_PPM_SSHOTR_ACT_STOP_LEVEL_LEN = 4 ;
+static const uint8_t P9N2_C_PPM_SSHOTR_DEEPEST_REQ_STOP_LEVEL_OTR = 12 ;
+static const uint8_t P9N2_C_PPM_SSHOTR_DEEPEST_REQ_STOP_LEVEL_OTR_LEN = 4 ;
+static const uint8_t P9N2_C_PPM_SSHOTR_DEEPEST_ACT_STOP_LEVEL_OTR = 16 ;
+static const uint8_t P9N2_C_PPM_SSHOTR_DEEPEST_ACT_STOP_LEVEL_OTR_LEN = 4 ;
+static const uint8_t P9N2_C_PPM_SSHOTR_IVRM_ENABLED_HISTORY_OTR = 20 ;
+
+static const uint8_t P9N2_EQ_PPM_SSHSRC_STOP_GATED = 0 ;
+static const uint8_t P9N2_EQ_PPM_SSHSRC_SPECIAL_WKUP_DONE = 1 ;
+static const uint8_t P9N2_EQ_PPM_SSHSRC_STOP_TRANSITION = 2 ;
+static const uint8_t P9N2_EQ_PPM_SSHSRC_STOP_TRANSITION_LEN = 2 ;
+static const uint8_t P9N2_EQ_PPM_SSHSRC_REQ_STOP_LEVEL = 4 ;
+static const uint8_t P9N2_EQ_PPM_SSHSRC_REQ_STOP_LEVEL_LEN = 4 ;
+static const uint8_t P9N2_EQ_PPM_SSHSRC_ACT_STOP_LEVEL = 8 ;
+static const uint8_t P9N2_EQ_PPM_SSHSRC_ACT_STOP_LEVEL_LEN = 4 ;
+static const uint8_t P9N2_EQ_PPM_SSHSRC_REQ_WRITE_ENABLE = 12 ;
+static const uint8_t P9N2_EQ_PPM_SSHSRC_ACT_WRITE_ENABLE = 13 ;
+
+static const uint8_t P9N2_EX_PPM_SSHSRC_STOP_GATED = 0 ;
+static const uint8_t P9N2_EX_PPM_SSHSRC_SPECIAL_WKUP_DONE = 1 ;
+static const uint8_t P9N2_EX_PPM_SSHSRC_STOP_TRANSITION = 2 ;
+static const uint8_t P9N2_EX_PPM_SSHSRC_STOP_TRANSITION_LEN = 2 ;
+static const uint8_t P9N2_EX_PPM_SSHSRC_REQ_STOP_LEVEL = 4 ;
+static const uint8_t P9N2_EX_PPM_SSHSRC_REQ_STOP_LEVEL_LEN = 4 ;
+static const uint8_t P9N2_EX_PPM_SSHSRC_ACT_STOP_LEVEL = 8 ;
+static const uint8_t P9N2_EX_PPM_SSHSRC_ACT_STOP_LEVEL_LEN = 4 ;
+static const uint8_t P9N2_EX_PPM_SSHSRC_REQ_WRITE_ENABLE = 12 ;
+static const uint8_t P9N2_EX_PPM_SSHSRC_ACT_WRITE_ENABLE = 13 ;
+
+static const uint8_t P9N2_C_PPM_SSHSRC_STOP_GATED = 0 ;
+static const uint8_t P9N2_C_PPM_SSHSRC_SPECIAL_WKUP_DONE = 1 ;
+static const uint8_t P9N2_C_PPM_SSHSRC_STOP_TRANSITION = 2 ;
+static const uint8_t P9N2_C_PPM_SSHSRC_STOP_TRANSITION_LEN = 2 ;
+static const uint8_t P9N2_C_PPM_SSHSRC_REQ_STOP_LEVEL = 4 ;
+static const uint8_t P9N2_C_PPM_SSHSRC_REQ_STOP_LEVEL_LEN = 4 ;
+static const uint8_t P9N2_C_PPM_SSHSRC_ACT_STOP_LEVEL = 8 ;
+static const uint8_t P9N2_C_PPM_SSHSRC_ACT_STOP_LEVEL_LEN = 4 ;
+static const uint8_t P9N2_C_PPM_SSHSRC_REQ_WRITE_ENABLE = 12 ;
+static const uint8_t P9N2_C_PPM_SSHSRC_ACT_WRITE_ENABLE = 13 ;
+
+static const uint8_t P9N2_EQ_PPM_VDMCR_VDM_POWERON = 0 ;
+static const uint8_t P9N2_EQ_PPM_VDMCR_VDM_DISABLE = 1 ;
+
+static const uint8_t P9N2_EX_PPM_VDMCR_VDM_POWERON = 0 ;
+static const uint8_t P9N2_EX_PPM_VDMCR_VDM_DISABLE = 1 ;
+
+static const uint8_t P9N2_C_PPM_VDMCR_VDM_POWERON = 0 ;
+static const uint8_t P9N2_C_PPM_VDMCR_VDM_DISABLE = 1 ;
+
+static const uint8_t P9N2_EQ_PRD_PURGE_CMD_REG_TRIGGER = 0 ;
+static const uint8_t P9N2_EQ_PRD_PURGE_CMD_REG_TYPE = 1 ;
+static const uint8_t P9N2_EQ_PRD_PURGE_CMD_REG_TYPE_LEN = 4 ;
+static const uint8_t P9N2_EQ_PRD_PURGE_CMD_REG_BUSY = 9 ;
+static const uint8_t P9N2_EQ_PRD_PURGE_CMD_REG_PRGSM_BUSY_ON_THIS = 10 ;
+static const uint8_t P9N2_EQ_PRD_PURGE_CMD_REG_PRGSM_BUSY = 11 ;
+static const uint8_t P9N2_EQ_PRD_PURGE_CMD_REG_MEM = 17 ;
+static const uint8_t P9N2_EQ_PRD_PURGE_CMD_REG_MEM_LEN = 3 ;
+static const uint8_t P9N2_EQ_PRD_PURGE_CMD_REG_CGC = 20 ;
+static const uint8_t P9N2_EQ_PRD_PURGE_CMD_REG_CGC_LEN = 8 ;
+static const uint8_t P9N2_EQ_PRD_PURGE_CMD_REG_BANK = 28 ;
+static const uint8_t P9N2_EQ_PRD_PURGE_CMD_REG_ERR = 29 ;
+
+static const uint8_t P9N2_EX_PRD_PURGE_CMD_REG_TRIGGER = 0 ;
+static const uint8_t P9N2_EX_PRD_PURGE_CMD_REG_TYPE = 1 ;
+static const uint8_t P9N2_EX_PRD_PURGE_CMD_REG_TYPE_LEN = 4 ;
+static const uint8_t P9N2_EX_PRD_PURGE_CMD_REG_BUSY = 9 ;
+static const uint8_t P9N2_EX_PRD_PURGE_CMD_REG_PRGSM_BUSY_ON_THIS = 10 ;
+static const uint8_t P9N2_EX_PRD_PURGE_CMD_REG_PRGSM_BUSY = 11 ;
+static const uint8_t P9N2_EX_PRD_PURGE_CMD_REG_MEM = 17 ;
+static const uint8_t P9N2_EX_PRD_PURGE_CMD_REG_MEM_LEN = 3 ;
+static const uint8_t P9N2_EX_PRD_PURGE_CMD_REG_CGC = 20 ;
+static const uint8_t P9N2_EX_PRD_PURGE_CMD_REG_CGC_LEN = 8 ;
+static const uint8_t P9N2_EX_PRD_PURGE_CMD_REG_BANK = 28 ;
+static const uint8_t P9N2_EX_PRD_PURGE_CMD_REG_ERR = 29 ;
+
+static const uint8_t P9N2_EQ_PRD_PURGE_REG_L3_REQ = 0 ;
+static const uint8_t P9N2_EQ_PRD_PURGE_REG_L3_TTYPE = 1 ;
+static const uint8_t P9N2_EQ_PRD_PURGE_REG_L3_TTYPE_LEN = 4 ;
+static const uint8_t P9N2_EQ_PRD_PURGE_REG_L3_LINE_DEL_ON_NEXT_CE = 5 ;
+static const uint8_t P9N2_EQ_PRD_PURGE_REG_L3_LINE_DEL_ON_ALL_CE = 6 ;
+static const uint8_t P9N2_EQ_PRD_PURGE_REG_L3_PRD_PURGE_RESERVED_1 = 7 ;
+static const uint8_t P9N2_EQ_PRD_PURGE_REG_L3_PRD_PURGE_RESERVED_1_LEN = 2 ;
+static const uint8_t P9N2_EQ_PRD_PURGE_REG_L3_BUSY_ERR = 9 ;
+static const uint8_t P9N2_EQ_PRD_PURGE_REG_L3_PRD_PURGE_RESERVED_2 = 10 ;
+static const uint8_t P9N2_EQ_PRD_PURGE_REG_L3_PRD_PURGE_RESERVED_2_LEN = 2 ;
+static const uint8_t P9N2_EQ_PRD_PURGE_REG_L3_MEMBER = 12 ;
+static const uint8_t P9N2_EQ_PRD_PURGE_REG_L3_MEMBER_LEN = 5 ;
+static const uint8_t P9N2_EQ_PRD_PURGE_REG_L3_DIR_ADDR = 17 ;
+static const uint8_t P9N2_EQ_PRD_PURGE_REG_L3_DIR_ADDR_LEN = 12 ;
+
+static const uint8_t P9N2_EX_PRD_PURGE_REG_L3_REQ = 0 ;
+static const uint8_t P9N2_EX_PRD_PURGE_REG_L3_TTYPE = 1 ;
+static const uint8_t P9N2_EX_PRD_PURGE_REG_L3_TTYPE_LEN = 4 ;
+static const uint8_t P9N2_EX_PRD_PURGE_REG_L3_LINE_DEL_ON_NEXT_CE = 5 ;
+static const uint8_t P9N2_EX_PRD_PURGE_REG_L3_LINE_DEL_ON_ALL_CE = 6 ;
+static const uint8_t P9N2_EX_PRD_PURGE_REG_L3_PRD_PURGE_RESERVED_1 = 7 ;
+static const uint8_t P9N2_EX_PRD_PURGE_REG_L3_PRD_PURGE_RESERVED_1_LEN = 2 ;
+static const uint8_t P9N2_EX_PRD_PURGE_REG_L3_BUSY_ERR = 9 ;
+static const uint8_t P9N2_EX_PRD_PURGE_REG_L3_PRD_PURGE_RESERVED_2 = 10 ;
+static const uint8_t P9N2_EX_PRD_PURGE_REG_L3_PRD_PURGE_RESERVED_2_LEN = 2 ;
+static const uint8_t P9N2_EX_PRD_PURGE_REG_L3_MEMBER = 12 ;
+static const uint8_t P9N2_EX_PRD_PURGE_REG_L3_MEMBER_LEN = 5 ;
+static const uint8_t P9N2_EX_PRD_PURGE_REG_L3_DIR_ADDR = 17 ;
+static const uint8_t P9N2_EX_PRD_PURGE_REG_L3_DIR_ADDR_LEN = 12 ;
+
+static const uint8_t P9N2_EQ_PRE_COUNTER_REG_COUNTER = 0 ;
+static const uint8_t P9N2_EQ_PRE_COUNTER_REG_COUNTER_LEN = 8 ;
+
+static const uint8_t P9N2_EX_PRE_COUNTER_REG_COUNTER = 0 ;
+static const uint8_t P9N2_EX_PRE_COUNTER_REG_COUNTER_LEN = 8 ;
+
+static const uint8_t P9N2_C_PRE_COUNTER_REG_COUNTER = 0 ;
+static const uint8_t P9N2_C_PRE_COUNTER_REG_COUNTER_LEN = 8 ;
+
+static const uint8_t P9N2_EQ_PRIMARY_ADDRESS_REG_PRIMARY_ADDRESS = 0 ;
+static const uint8_t P9N2_EQ_PRIMARY_ADDRESS_REG_PRIMARY_ADDRESS_LEN = 6 ;
+
+static const uint8_t P9N2_EX_PRIMARY_ADDRESS_REG_PRIMARY_ADDRESS = 0 ;
+static const uint8_t P9N2_EX_PRIMARY_ADDRESS_REG_PRIMARY_ADDRESS_LEN = 6 ;
+
+static const uint8_t P9N2_C_PRIMARY_ADDRESS_REG_PRIMARY_ADDRESS = 0 ;
+static const uint8_t P9N2_C_PRIMARY_ADDRESS_REG_PRIMARY_ADDRESS_LEN = 6 ;
+
+static const uint8_t P9N2_EQ_PROTECT_MODE_REG_READ_ENABLE = 0 ;
+static const uint8_t P9N2_EQ_PROTECT_MODE_REG_WRITE_ENABLE = 1 ;
+
+static const uint8_t P9N2_EX_PROTECT_MODE_REG_READ_ENABLE = 0 ;
+static const uint8_t P9N2_EX_PROTECT_MODE_REG_WRITE_ENABLE = 1 ;
+
+static const uint8_t P9N2_C_PROTECT_MODE_REG_READ_ENABLE = 0 ;
+static const uint8_t P9N2_C_PROTECT_MODE_REG_WRITE_ENABLE = 1 ;
+
+static const uint8_t P9N2_EQ_PSCOM_ERROR_MASK_PCB_WDATA_PARITY = 0 ;
+static const uint8_t P9N2_EQ_PSCOM_ERROR_MASK_PCB_ADDRESS_PARITY = 1 ;
+static const uint8_t P9N2_EQ_PSCOM_ERROR_MASK_DL_RETURN_WDATA_PARITY = 2 ;
+static const uint8_t P9N2_EQ_PSCOM_ERROR_MASK_DL_RETURN_P0 = 3 ;
+static const uint8_t P9N2_EQ_PSCOM_ERROR_MASK_UL_RDATA_PARITY = 4 ;
+static const uint8_t P9N2_EQ_PSCOM_ERROR_MASK_UL_P0 = 5 ;
+static const uint8_t P9N2_EQ_PSCOM_ERROR_MASK_PARITY_ON_INTERFACE_MACHINE = 6 ;
+static const uint8_t P9N2_EQ_PSCOM_ERROR_MASK_PARITY_ON_P2S_MACHINE = 7 ;
+static const uint8_t P9N2_EQ_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 8 ;
+static const uint8_t P9N2_EQ_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 9 ;
+static const uint8_t P9N2_EQ_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 10 ;
+static const uint8_t P9N2_EQ_PSCOM_ERROR_MASK_PARALLEL_WRITE_NVLD = 11 ;
+static const uint8_t P9N2_EQ_PSCOM_ERROR_MASK_PARALLEL_READ_NVLD = 12 ;
+static const uint8_t P9N2_EQ_PSCOM_ERROR_MASK_PARALLEL_ADDR_INVALID = 13 ;
+static const uint8_t P9N2_EQ_PSCOM_ERROR_MASK_PCB_COMMAND_PARITY = 14 ;
+static const uint8_t P9N2_EQ_PSCOM_ERROR_MASK_GENERAL_TIMEOUT = 15 ;
+static const uint8_t P9N2_EQ_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 16 ;
+static const uint8_t P9N2_EQ_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 17 ;
+
+static const uint8_t P9N2_EX_PSCOM_ERROR_MASK_PCB_WDATA_PARITY = 0 ;
+static const uint8_t P9N2_EX_PSCOM_ERROR_MASK_PCB_ADDRESS_PARITY = 1 ;
+static const uint8_t P9N2_EX_PSCOM_ERROR_MASK_DL_RETURN_WDATA_PARITY = 2 ;
+static const uint8_t P9N2_EX_PSCOM_ERROR_MASK_DL_RETURN_P0 = 3 ;
+static const uint8_t P9N2_EX_PSCOM_ERROR_MASK_UL_RDATA_PARITY = 4 ;
+static const uint8_t P9N2_EX_PSCOM_ERROR_MASK_UL_P0 = 5 ;
+static const uint8_t P9N2_EX_PSCOM_ERROR_MASK_PARITY_ON_INTERFACE_MACHINE = 6 ;
+static const uint8_t P9N2_EX_PSCOM_ERROR_MASK_PARITY_ON_P2S_MACHINE = 7 ;
+static const uint8_t P9N2_EX_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 8 ;
+static const uint8_t P9N2_EX_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 9 ;
+static const uint8_t P9N2_EX_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 10 ;
+static const uint8_t P9N2_EX_PSCOM_ERROR_MASK_PARALLEL_WRITE_NVLD = 11 ;
+static const uint8_t P9N2_EX_PSCOM_ERROR_MASK_PARALLEL_READ_NVLD = 12 ;
+static const uint8_t P9N2_EX_PSCOM_ERROR_MASK_PARALLEL_ADDR_INVALID = 13 ;
+static const uint8_t P9N2_EX_PSCOM_ERROR_MASK_PCB_COMMAND_PARITY = 14 ;
+static const uint8_t P9N2_EX_PSCOM_ERROR_MASK_GENERAL_TIMEOUT = 15 ;
+static const uint8_t P9N2_EX_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 16 ;
+static const uint8_t P9N2_EX_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 17 ;
+
+static const uint8_t P9N2_C_PSCOM_ERROR_MASK_PCB_WDATA_PARITY = 0 ;
+static const uint8_t P9N2_C_PSCOM_ERROR_MASK_PCB_ADDRESS_PARITY = 1 ;
+static const uint8_t P9N2_C_PSCOM_ERROR_MASK_DL_RETURN_WDATA_PARITY = 2 ;
+static const uint8_t P9N2_C_PSCOM_ERROR_MASK_DL_RETURN_P0 = 3 ;
+static const uint8_t P9N2_C_PSCOM_ERROR_MASK_UL_RDATA_PARITY = 4 ;
+static const uint8_t P9N2_C_PSCOM_ERROR_MASK_UL_P0 = 5 ;
+static const uint8_t P9N2_C_PSCOM_ERROR_MASK_PARITY_ON_INTERFACE_MACHINE = 6 ;
+static const uint8_t P9N2_C_PSCOM_ERROR_MASK_PARITY_ON_P2S_MACHINE = 7 ;
+static const uint8_t P9N2_C_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 8 ;
+static const uint8_t P9N2_C_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 9 ;
+static const uint8_t P9N2_C_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 10 ;
+static const uint8_t P9N2_C_PSCOM_ERROR_MASK_PARALLEL_WRITE_NVLD = 11 ;
+static const uint8_t P9N2_C_PSCOM_ERROR_MASK_PARALLEL_READ_NVLD = 12 ;
+static const uint8_t P9N2_C_PSCOM_ERROR_MASK_PARALLEL_ADDR_INVALID = 13 ;
+static const uint8_t P9N2_C_PSCOM_ERROR_MASK_PCB_COMMAND_PARITY = 14 ;
+static const uint8_t P9N2_C_PSCOM_ERROR_MASK_GENERAL_TIMEOUT = 15 ;
+static const uint8_t P9N2_C_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 16 ;
+static const uint8_t P9N2_C_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 17 ;
+
+static const uint8_t P9N2_EQ_PSCOM_MODE_REG_ABORT_ON_PCB_ADDR_PARITY_ERROR = 0 ;
+static const uint8_t P9N2_EQ_PSCOM_MODE_REG_ABORT_ON_PCB_WDATA_PARITY_ERROR = 1 ;
+static const uint8_t P9N2_EQ_PSCOM_MODE_REG_UNUSED_BIT_2 = 2 ;
+static const uint8_t P9N2_EQ_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR = 3 ;
+static const uint8_t P9N2_EQ_PSCOM_MODE_REG_WATCHDOG_ENABLE = 4 ;
+static const uint8_t P9N2_EQ_PSCOM_MODE_REG_SCOM_HANG_LIMIT = 5 ;
+static const uint8_t P9N2_EQ_PSCOM_MODE_REG_SCOM_HANG_LIMIT_LEN = 2 ;
+static const uint8_t P9N2_EQ_PSCOM_MODE_REG_FORCE_ALL_RINGS = 7 ;
+static const uint8_t P9N2_EQ_PSCOM_MODE_REG_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE = 8 ;
+static const uint8_t P9N2_EQ_PSCOM_MODE_REG_RESERVED_LT = 9 ;
+static const uint8_t P9N2_EQ_PSCOM_MODE_REG_RESERVED_LT_LEN = 3 ;
+
+static const uint8_t P9N2_EX_PSCOM_MODE_REG_ABORT_ON_PCB_ADDR_PARITY_ERROR = 0 ;
+static const uint8_t P9N2_EX_PSCOM_MODE_REG_ABORT_ON_PCB_WDATA_PARITY_ERROR = 1 ;
+static const uint8_t P9N2_EX_PSCOM_MODE_REG_UNUSED_BIT_2 = 2 ;
+static const uint8_t P9N2_EX_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR = 3 ;
+static const uint8_t P9N2_EX_PSCOM_MODE_REG_WATCHDOG_ENABLE = 4 ;
+static const uint8_t P9N2_EX_PSCOM_MODE_REG_SCOM_HANG_LIMIT = 5 ;
+static const uint8_t P9N2_EX_PSCOM_MODE_REG_SCOM_HANG_LIMIT_LEN = 2 ;
+static const uint8_t P9N2_EX_PSCOM_MODE_REG_FORCE_ALL_RINGS = 7 ;
+static const uint8_t P9N2_EX_PSCOM_MODE_REG_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE = 8 ;
+static const uint8_t P9N2_EX_PSCOM_MODE_REG_RESERVED_LT = 9 ;
+static const uint8_t P9N2_EX_PSCOM_MODE_REG_RESERVED_LT_LEN = 3 ;
+
+static const uint8_t P9N2_C_PSCOM_MODE_REG_ABORT_ON_PCB_ADDR_PARITY_ERROR = 0 ;
+static const uint8_t P9N2_C_PSCOM_MODE_REG_ABORT_ON_PCB_WDATA_PARITY_ERROR = 1 ;
+static const uint8_t P9N2_C_PSCOM_MODE_REG_UNUSED_BIT_2 = 2 ;
+static const uint8_t P9N2_C_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR = 3 ;
+static const uint8_t P9N2_C_PSCOM_MODE_REG_WATCHDOG_ENABLE = 4 ;
+static const uint8_t P9N2_C_PSCOM_MODE_REG_SCOM_HANG_LIMIT = 5 ;
+static const uint8_t P9N2_C_PSCOM_MODE_REG_SCOM_HANG_LIMIT_LEN = 2 ;
+static const uint8_t P9N2_C_PSCOM_MODE_REG_FORCE_ALL_RINGS = 7 ;
+static const uint8_t P9N2_C_PSCOM_MODE_REG_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE = 8 ;
+static const uint8_t P9N2_C_PSCOM_MODE_REG_RESERVED_LT = 9 ;
+static const uint8_t P9N2_C_PSCOM_MODE_REG_RESERVED_LT_LEN = 3 ;
+
+static const uint8_t P9N2_EQ_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_WDATA_PARITY = 0 ;
+static const uint8_t P9N2_EQ_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_ADDRESS_PARITY = 1 ;
+static const uint8_t P9N2_EQ_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_WDATA_PARITY = 2 ;
+static const uint8_t P9N2_EQ_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_P0 = 3 ;
+static const uint8_t P9N2_EQ_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_RDATA_PARITY = 4 ;
+static const uint8_t P9N2_EQ_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_P0 = 5 ;
+static const uint8_t P9N2_EQ_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE = 6 ;
+static const uint8_t P9N2_EQ_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_P2S_MACHINE = 7 ;
+static const uint8_t P9N2_EQ_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 8 ;
+static const uint8_t P9N2_EQ_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 9 ;
+static const uint8_t P9N2_EQ_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 10 ;
+static const uint8_t P9N2_EQ_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_WRITE_NVLD = 11 ;
+static const uint8_t P9N2_EQ_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_READ_NVLD = 12 ;
+static const uint8_t P9N2_EQ_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_ADDR_INVALID = 13 ;
+static const uint8_t P9N2_EQ_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_COMMAND_PARITY = 14 ;
+static const uint8_t P9N2_EQ_PSCOM_STATUS_ERROR_REG_ACCUMULATED_GENERAL_TIMEOUT = 15 ;
+static const uint8_t P9N2_EQ_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 16 ;
+static const uint8_t P9N2_EQ_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 17 ;
+static const uint8_t P9N2_EQ_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_WDATA_PARITY = 18 ;
+static const uint8_t P9N2_EQ_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_ADDRESS_PARITY = 19 ;
+static const uint8_t P9N2_EQ_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_WDATA_PARITY = 20 ;
+static const uint8_t P9N2_EQ_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_P0 = 21 ;
+static const uint8_t P9N2_EQ_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_RDATA_PARITY = 22 ;
+static const uint8_t P9N2_EQ_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_P0 = 23 ;
+static const uint8_t P9N2_EQ_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_INTERFACE_MACHINE = 24 ;
+static const uint8_t P9N2_EQ_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_P2S_MACHINE = 25 ;
+static const uint8_t P9N2_EQ_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 26 ;
+static const uint8_t P9N2_EQ_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 27 ;
+static const uint8_t P9N2_EQ_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 28 ;
+static const uint8_t P9N2_EQ_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_WRITE_NVLD = 29 ;
+static const uint8_t P9N2_EQ_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_READ_NVLD = 30 ;
+static const uint8_t P9N2_EQ_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_ADDR_INVALID = 31 ;
+static const uint8_t P9N2_EQ_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_COMMAND_PARITY = 32 ;
+static const uint8_t P9N2_EQ_PSCOM_STATUS_ERROR_REG_TRAPPED_GENERAL_TIMEOUT = 33 ;
+static const uint8_t P9N2_EQ_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 34 ;
+static const uint8_t P9N2_EQ_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 35 ;
+
+static const uint8_t P9N2_EX_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_WDATA_PARITY = 0 ;
+static const uint8_t P9N2_EX_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_ADDRESS_PARITY = 1 ;
+static const uint8_t P9N2_EX_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_WDATA_PARITY = 2 ;
+static const uint8_t P9N2_EX_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_P0 = 3 ;
+static const uint8_t P9N2_EX_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_RDATA_PARITY = 4 ;
+static const uint8_t P9N2_EX_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_P0 = 5 ;
+static const uint8_t P9N2_EX_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE = 6 ;
+static const uint8_t P9N2_EX_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_P2S_MACHINE = 7 ;
+static const uint8_t P9N2_EX_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 8 ;
+static const uint8_t P9N2_EX_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 9 ;
+static const uint8_t P9N2_EX_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 10 ;
+static const uint8_t P9N2_EX_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_WRITE_NVLD = 11 ;
+static const uint8_t P9N2_EX_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_READ_NVLD = 12 ;
+static const uint8_t P9N2_EX_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_ADDR_INVALID = 13 ;
+static const uint8_t P9N2_EX_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_COMMAND_PARITY = 14 ;
+static const uint8_t P9N2_EX_PSCOM_STATUS_ERROR_REG_ACCUMULATED_GENERAL_TIMEOUT = 15 ;
+static const uint8_t P9N2_EX_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 16 ;
+static const uint8_t P9N2_EX_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 17 ;
+static const uint8_t P9N2_EX_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_WDATA_PARITY = 18 ;
+static const uint8_t P9N2_EX_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_ADDRESS_PARITY = 19 ;
+static const uint8_t P9N2_EX_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_WDATA_PARITY = 20 ;
+static const uint8_t P9N2_EX_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_P0 = 21 ;
+static const uint8_t P9N2_EX_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_RDATA_PARITY = 22 ;
+static const uint8_t P9N2_EX_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_P0 = 23 ;
+static const uint8_t P9N2_EX_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_INTERFACE_MACHINE = 24 ;
+static const uint8_t P9N2_EX_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_P2S_MACHINE = 25 ;
+static const uint8_t P9N2_EX_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 26 ;
+static const uint8_t P9N2_EX_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 27 ;
+static const uint8_t P9N2_EX_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 28 ;
+static const uint8_t P9N2_EX_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_WRITE_NVLD = 29 ;
+static const uint8_t P9N2_EX_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_READ_NVLD = 30 ;
+static const uint8_t P9N2_EX_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_ADDR_INVALID = 31 ;
+static const uint8_t P9N2_EX_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_COMMAND_PARITY = 32 ;
+static const uint8_t P9N2_EX_PSCOM_STATUS_ERROR_REG_TRAPPED_GENERAL_TIMEOUT = 33 ;
+static const uint8_t P9N2_EX_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 34 ;
+static const uint8_t P9N2_EX_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 35 ;
+
+static const uint8_t P9N2_C_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_WDATA_PARITY = 0 ;
+static const uint8_t P9N2_C_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_ADDRESS_PARITY = 1 ;
+static const uint8_t P9N2_C_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_WDATA_PARITY = 2 ;
+static const uint8_t P9N2_C_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_P0 = 3 ;
+static const uint8_t P9N2_C_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_RDATA_PARITY = 4 ;
+static const uint8_t P9N2_C_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_P0 = 5 ;
+static const uint8_t P9N2_C_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE = 6 ;
+static const uint8_t P9N2_C_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_P2S_MACHINE = 7 ;
+static const uint8_t P9N2_C_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 8 ;
+static const uint8_t P9N2_C_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 9 ;
+static const uint8_t P9N2_C_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 10 ;
+static const uint8_t P9N2_C_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_WRITE_NVLD = 11 ;
+static const uint8_t P9N2_C_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_READ_NVLD = 12 ;
+static const uint8_t P9N2_C_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_ADDR_INVALID = 13 ;
+static const uint8_t P9N2_C_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_COMMAND_PARITY = 14 ;
+static const uint8_t P9N2_C_PSCOM_STATUS_ERROR_REG_ACCUMULATED_GENERAL_TIMEOUT = 15 ;
+static const uint8_t P9N2_C_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 16 ;
+static const uint8_t P9N2_C_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 17 ;
+static const uint8_t P9N2_C_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_WDATA_PARITY = 18 ;
+static const uint8_t P9N2_C_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_ADDRESS_PARITY = 19 ;
+static const uint8_t P9N2_C_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_WDATA_PARITY = 20 ;
+static const uint8_t P9N2_C_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_P0 = 21 ;
+static const uint8_t P9N2_C_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_RDATA_PARITY = 22 ;
+static const uint8_t P9N2_C_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_P0 = 23 ;
+static const uint8_t P9N2_C_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_INTERFACE_MACHINE = 24 ;
+static const uint8_t P9N2_C_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_P2S_MACHINE = 25 ;
+static const uint8_t P9N2_C_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 26 ;
+static const uint8_t P9N2_C_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 27 ;
+static const uint8_t P9N2_C_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 28 ;
+static const uint8_t P9N2_C_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_WRITE_NVLD = 29 ;
+static const uint8_t P9N2_C_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_READ_NVLD = 30 ;
+static const uint8_t P9N2_C_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_ADDR_INVALID = 31 ;
+static const uint8_t P9N2_C_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_COMMAND_PARITY = 32 ;
+static const uint8_t P9N2_C_PSCOM_STATUS_ERROR_REG_TRAPPED_GENERAL_TIMEOUT = 33 ;
+static const uint8_t P9N2_C_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 34 ;
+static const uint8_t P9N2_C_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 35 ;
+
+static const uint8_t P9N2_EX_L2_PWM_EVENTS_RESERVED_32 = 32 ;
+static const uint8_t P9N2_EX_L2_PWM_EVENTS_FREQ_SCALE_A_THRESHOLD = 33 ;
+static const uint8_t P9N2_EX_L2_PWM_EVENTS_FREQ_SCALE_A_THRESHOLD_LEN = 7 ;
+static const uint8_t P9N2_EX_L2_PWM_EVENTS_RESERVED_40 = 40 ;
+static const uint8_t P9N2_EX_L2_PWM_EVENTS_FREQ_SCALE_B_THRESHOLD = 41 ;
+static const uint8_t P9N2_EX_L2_PWM_EVENTS_FREQ_SCALE_B_THRESHOLD_LEN = 7 ;
+static const uint8_t P9N2_EX_L2_PWM_EVENTS_RESERVED_48 = 48 ;
+static const uint8_t P9N2_EX_L2_PWM_EVENTS_PSTATE_A_THRESHOLD = 49 ;
+static const uint8_t P9N2_EX_L2_PWM_EVENTS_PSTATE_A_THRESHOLD_LEN = 3 ;
+static const uint8_t P9N2_EX_L2_PWM_EVENTS_RESERVED_52 = 52 ;
+static const uint8_t P9N2_EX_L2_PWM_EVENTS_PSTATE_B_THRESHOLD = 53 ;
+static const uint8_t P9N2_EX_L2_PWM_EVENTS_PSTATE_B_THRESHOLD_LEN = 3 ;
+static const uint8_t P9N2_EX_L2_PWM_EVENTS_RESERVED_56 = 56 ;
+static const uint8_t P9N2_EX_L2_PWM_EVENTS_RESERVED_57 = 57 ;
+static const uint8_t P9N2_EX_L2_PWM_EVENTS_EVENT_MUX_SELECTS = 58 ;
+static const uint8_t P9N2_EX_L2_PWM_EVENTS_EVENT_MUX_SELECTS_LEN = 2 ;
+static const uint8_t P9N2_EX_L2_PWM_EVENTS_RESERVED_60 = 60 ;
+static const uint8_t P9N2_EX_L2_PWM_EVENTS_RESERVED_61 = 61 ;
+static const uint8_t P9N2_EX_L2_PWM_EVENTS_PMCM_THRESHOLD = 62 ;
+static const uint8_t P9N2_EX_L2_PWM_EVENTS_PMCM_THRESHOLD_LEN = 2 ;
+
+static const uint8_t P9N2_C_PWM_EVENTS_RESERVED_32 = 32 ;
+static const uint8_t P9N2_C_PWM_EVENTS_FREQ_SCALE_A_THRESHOLD = 33 ;
+static const uint8_t P9N2_C_PWM_EVENTS_FREQ_SCALE_A_THRESHOLD_LEN = 7 ;
+static const uint8_t P9N2_C_PWM_EVENTS_RESERVED_40 = 40 ;
+static const uint8_t P9N2_C_PWM_EVENTS_FREQ_SCALE_B_THRESHOLD = 41 ;
+static const uint8_t P9N2_C_PWM_EVENTS_FREQ_SCALE_B_THRESHOLD_LEN = 7 ;
+static const uint8_t P9N2_C_PWM_EVENTS_RESERVED_48 = 48 ;
+static const uint8_t P9N2_C_PWM_EVENTS_PSTATE_A_THRESHOLD = 49 ;
+static const uint8_t P9N2_C_PWM_EVENTS_PSTATE_A_THRESHOLD_LEN = 3 ;
+static const uint8_t P9N2_C_PWM_EVENTS_RESERVED_52 = 52 ;
+static const uint8_t P9N2_C_PWM_EVENTS_PSTATE_B_THRESHOLD = 53 ;
+static const uint8_t P9N2_C_PWM_EVENTS_PSTATE_B_THRESHOLD_LEN = 3 ;
+static const uint8_t P9N2_C_PWM_EVENTS_RESERVED_56 = 56 ;
+static const uint8_t P9N2_C_PWM_EVENTS_RESERVED_57 = 57 ;
+static const uint8_t P9N2_C_PWM_EVENTS_EVENT_MUX_SELECTS = 58 ;
+static const uint8_t P9N2_C_PWM_EVENTS_EVENT_MUX_SELECTS_LEN = 2 ;
+static const uint8_t P9N2_C_PWM_EVENTS_RESERVED_60 = 60 ;
+static const uint8_t P9N2_C_PWM_EVENTS_RESERVED_61 = 61 ;
+static const uint8_t P9N2_C_PWM_EVENTS_PMCM_THRESHOLD = 62 ;
+static const uint8_t P9N2_C_PWM_EVENTS_PMCM_THRESHOLD_LEN = 2 ;
+
+static const uint8_t P9N2_EQ_QPPM_DPLL_CTRL_LOCK_SEL = 0 ;
+static const uint8_t P9N2_EQ_QPPM_DPLL_CTRL_ENABLE_JUMP_PROTECT = 1 ;
+static const uint8_t P9N2_EQ_QPPM_DPLL_CTRL_FF_BYPASS = 2 ;
+static const uint8_t P9N2_EQ_QPPM_DPLL_CTRL_DCO_OVERRIDE = 3 ;
+static const uint8_t P9N2_EQ_QPPM_DPLL_CTRL_DCO_INCR = 4 ;
+static const uint8_t P9N2_EQ_QPPM_DPLL_CTRL_DCO_DECR = 5 ;
+static const uint8_t P9N2_EQ_QPPM_DPLL_CTRL_FF_SLEWRATE = 6 ;
+static const uint8_t P9N2_EQ_QPPM_DPLL_CTRL_FF_SLEWRATE_LEN = 10 ;
+static const uint8_t P9N2_EQ_QPPM_DPLL_CTRL_SS_ENABLE = 16 ;
+static const uint8_t P9N2_EQ_QPPM_DPLL_CTRL_RESERVED_17_19 = 17 ;
+static const uint8_t P9N2_EQ_QPPM_DPLL_CTRL_RESERVED_17_19_LEN = 3 ;
+static const uint8_t P9N2_EQ_QPPM_DPLL_CTRL_SLEW_DN_SEL = 20 ;
+static const uint8_t P9N2_EQ_QPPM_DPLL_CTRL_ENABLE_JUMP_TARGET_UPDATE = 21 ;
+static const uint8_t P9N2_EQ_QPPM_DPLL_CTRL_ENABLE_FMIN_TARGET = 22 ;
+static const uint8_t P9N2_EQ_QPPM_DPLL_CTRL_ENABLE_FMAX_TARGET = 23 ;
+static const uint8_t P9N2_EQ_QPPM_DPLL_CTRL_JUMP_VALUE_N_L = 33 ;
+static const uint8_t P9N2_EQ_QPPM_DPLL_CTRL_JUMP_VALUE_N_L_LEN = 3 ;
+static const uint8_t P9N2_EQ_QPPM_DPLL_CTRL_JUMP_VALUE_N_S = 37 ;
+static const uint8_t P9N2_EQ_QPPM_DPLL_CTRL_JUMP_VALUE_N_S_LEN = 3 ;
+static const uint8_t P9N2_EQ_QPPM_DPLL_CTRL_JUMP_VALUE_L_S = 41 ;
+static const uint8_t P9N2_EQ_QPPM_DPLL_CTRL_JUMP_VALUE_L_S_LEN = 3 ;
+static const uint8_t P9N2_EQ_QPPM_DPLL_CTRL_JUMP_VALUE_S_N = 45 ;
+static const uint8_t P9N2_EQ_QPPM_DPLL_CTRL_JUMP_VALUE_S_N_LEN = 3 ;
+
+static const uint8_t P9N2_EQ_QPPM_DPLL_FREQ_FMAX = 1 ;
+static const uint8_t P9N2_EQ_QPPM_DPLL_FREQ_FMAX_LEN = 11 ;
+static const uint8_t P9N2_EQ_QPPM_DPLL_FREQ_HIRES_FMAX = 12 ;
+static const uint8_t P9N2_EQ_QPPM_DPLL_FREQ_HIRES_FMAX_LEN = 4 ;
+static const uint8_t P9N2_EQ_QPPM_DPLL_FREQ_FMULT = 17 ;
+static const uint8_t P9N2_EQ_QPPM_DPLL_FREQ_FMULT_LEN = 11 ;
+static const uint8_t P9N2_EQ_QPPM_DPLL_FREQ_HIRES_FMULT = 28 ;
+static const uint8_t P9N2_EQ_QPPM_DPLL_FREQ_HIRES_FMULT_LEN = 4 ;
+static const uint8_t P9N2_EQ_QPPM_DPLL_FREQ_FMIN = 33 ;
+static const uint8_t P9N2_EQ_QPPM_DPLL_FREQ_FMIN_LEN = 11 ;
+static const uint8_t P9N2_EQ_QPPM_DPLL_FREQ_HIRES_FMIN = 44 ;
+static const uint8_t P9N2_EQ_QPPM_DPLL_FREQ_HIRES_FMIN_LEN = 4 ;
+
+static const uint8_t P9N2_EQ_QPPM_DPLL_ICHAR_FREQIN_AVG = 1 ;
+static const uint8_t P9N2_EQ_QPPM_DPLL_ICHAR_FREQIN_AVG_LEN = 11 ;
+static const uint8_t P9N2_EQ_QPPM_DPLL_ICHAR_HIRES_FREQIN_AVG = 12 ;
+static const uint8_t P9N2_EQ_QPPM_DPLL_ICHAR_HIRES_FREQIN_AVG_LEN = 5 ;
+static const uint8_t P9N2_EQ_QPPM_DPLL_ICHAR_FREQIN_MAX = 21 ;
+static const uint8_t P9N2_EQ_QPPM_DPLL_ICHAR_FREQIN_MAX_LEN = 11 ;
+static const uint8_t P9N2_EQ_QPPM_DPLL_ICHAR_HIRES_FREQIN_MAX = 32 ;
+static const uint8_t P9N2_EQ_QPPM_DPLL_ICHAR_HIRES_FREQIN_MAX_LEN = 5 ;
+static const uint8_t P9N2_EQ_QPPM_DPLL_ICHAR_FREQIN_MIN = 41 ;
+static const uint8_t P9N2_EQ_QPPM_DPLL_ICHAR_FREQIN_MIN_LEN = 11 ;
+static const uint8_t P9N2_EQ_QPPM_DPLL_ICHAR_HIRES_FREQIN_MIN = 52 ;
+static const uint8_t P9N2_EQ_QPPM_DPLL_ICHAR_HIRES_FREQIN_MIN_LEN = 5 ;
+
+static const uint8_t P9N2_EQ_QPPM_DPLL_OCHAR_FREQOUT_MAX = 1 ;
+static const uint8_t P9N2_EQ_QPPM_DPLL_OCHAR_FREQOUT_MAX_LEN = 11 ;
+static const uint8_t P9N2_EQ_QPPM_DPLL_OCHAR_HIRES_FREQOUT_MAX = 12 ;
+static const uint8_t P9N2_EQ_QPPM_DPLL_OCHAR_HIRES_FREQOUT_MAX_LEN = 5 ;
+static const uint8_t P9N2_EQ_QPPM_DPLL_OCHAR_FREQOUT_AVG = 21 ;
+static const uint8_t P9N2_EQ_QPPM_DPLL_OCHAR_FREQOUT_AVG_LEN = 11 ;
+static const uint8_t P9N2_EQ_QPPM_DPLL_OCHAR_HIRES_FREQOUT_AVG = 32 ;
+static const uint8_t P9N2_EQ_QPPM_DPLL_OCHAR_HIRES_FREQOUT_AVG_LEN = 5 ;
+static const uint8_t P9N2_EQ_QPPM_DPLL_OCHAR_FREQOUT_MIN = 41 ;
+static const uint8_t P9N2_EQ_QPPM_DPLL_OCHAR_FREQOUT_MIN_LEN = 11 ;
+static const uint8_t P9N2_EQ_QPPM_DPLL_OCHAR_HIRES_FREQOUT_MIN = 52 ;
+static const uint8_t P9N2_EQ_QPPM_DPLL_OCHAR_HIRES_FREQOUT_MIN_LEN = 5 ;
+
+static const uint8_t P9N2_EQ_QPPM_DPLL_STAT_FREQOUT = 1 ;
+static const uint8_t P9N2_EQ_QPPM_DPLL_STAT_FREQOUT_LEN = 11 ;
+static const uint8_t P9N2_EQ_QPPM_DPLL_STAT_HIRES_FREQOUT = 12 ;
+static const uint8_t P9N2_EQ_QPPM_DPLL_STAT_HIRES_FREQOUT_LEN = 5 ;
+static const uint8_t P9N2_EQ_QPPM_DPLL_STAT_RESERVED_57_59 = 57 ;
+static const uint8_t P9N2_EQ_QPPM_DPLL_STAT_RESERVED_57_59_LEN = 2 ;
+static const uint8_t P9N2_EQ_QPPM_DPLL_STAT_FSAFE_ACTIVE = 59 ;
+static const uint8_t P9N2_EQ_QPPM_DPLL_STAT_UPDATE_COMPLETE = 60 ;
+static const uint8_t P9N2_EQ_QPPM_DPLL_STAT_FREQ_CHANGE = 61 ;
+static const uint8_t P9N2_EQ_QPPM_DPLL_STAT_BLOCK_ACTIVE = 62 ;
+static const uint8_t P9N2_EQ_QPPM_DPLL_STAT_LOCK = 63 ;
+
+static const uint8_t P9N2_EQ_QPPM_ERR_PCB_INTERRUPT_PROTOCOL = 0 ;
+static const uint8_t P9N2_EQ_QPPM_ERR_SPECIAL_WKUP_PROTOCOL = 1 ;
+static const uint8_t P9N2_EQ_QPPM_ERR_SPECIAL_WKUP_DONE_PROTOCOL = 2 ;
+static const uint8_t P9N2_EQ_QPPM_ERR_PFET_SEQ_PROGRAM = 3 ;
+static const uint8_t P9N2_EQ_QPPM_ERR_OCC_HEARTBEAT_LOSS = 4 ;
+static const uint8_t P9N2_EQ_QPPM_ERR_L2_EX0_CLK_SYNC = 5 ;
+static const uint8_t P9N2_EQ_QPPM_ERR_L2_EX1_CLK_SYNC = 6 ;
+static const uint8_t P9N2_EQ_QPPM_ERR_EDRAM_SEQUENCE = 7 ;
+static const uint8_t P9N2_EQ_QPPM_ERR_EDRAM_PGATE = 8 ;
+static const uint8_t P9N2_EQ_QPPM_ERR_DPLL_INT = 9 ;
+static const uint8_t P9N2_EQ_QPPM_ERR_DPLL_DYN_FMIN = 10 ;
+static const uint8_t P9N2_EQ_QPPM_ERR_DPLL_DCO_FULL = 11 ;
+static const uint8_t P9N2_EQ_QPPM_ERR_DPLL_DCO_EMPTY = 12 ;
+static const uint8_t P9N2_EQ_QPPM_ERR_INVERTED_VDM_DATA = 13 ;
+static const uint8_t P9N2_EQ_QPPM_ERR_INVERTED_VDM_DATA_LEN = 4 ;
+static const uint8_t P9N2_EQ_QPPM_ERR_CME0_IVRM_DROPOUT = 17 ;
+static const uint8_t P9N2_EQ_QPPM_ERR_CME1_IVRM_DROPOUT = 18 ;
+static const uint8_t P9N2_EQ_QPPM_ERR_SPARE_19 = 19 ;
+static const uint8_t P9N2_EQ_QPPM_ERR_SPARE_20_23 = 20 ;
+static const uint8_t P9N2_EQ_QPPM_ERR_SPARE_20_23_LEN = 4 ;
+
+static const uint8_t P9N2_EQ_QPPM_ERRMSK_RESERVED_0_23 = 0 ;
+static const uint8_t P9N2_EQ_QPPM_ERRMSK_RESERVED_0_23_LEN = 24 ;
+
+static const uint8_t P9N2_EQ_QPPM_ERRSUM_PM_ERROR = 0 ;
+
+static const uint8_t P9N2_EQ_QPPM_EXCGCR_L2_EX0_CLK_SB_STRENGTH = 0 ;
+static const uint8_t P9N2_EQ_QPPM_EXCGCR_L2_EX0_CLK_SB_STRENGTH_LEN = 4 ;
+static const uint8_t P9N2_EQ_QPPM_EXCGCR_L2_EX0_CLK_SB_SPARE0 = 4 ;
+static const uint8_t P9N2_EQ_QPPM_EXCGCR_L2_EX0_CLK_SB_PULSE_MODE_EN = 5 ;
+static const uint8_t P9N2_EQ_QPPM_EXCGCR_L2_EX0_CLK_SB_PULSE_MODE = 6 ;
+static const uint8_t P9N2_EQ_QPPM_EXCGCR_L2_EX0_CLK_SB_PULSE_MODE_LEN = 2 ;
+static const uint8_t P9N2_EQ_QPPM_EXCGCR_L2_EX0_CLK_SW_RESCLK = 8 ;
+static const uint8_t P9N2_EQ_QPPM_EXCGCR_L2_EX0_CLK_SW_RESCLK_LEN = 4 ;
+static const uint8_t P9N2_EQ_QPPM_EXCGCR_L2_EX0_CLK_SW_SPARE1 = 12 ;
+static const uint8_t P9N2_EQ_QPPM_EXCGCR_RESERVED_13_15 = 13 ;
+static const uint8_t P9N2_EQ_QPPM_EXCGCR_RESERVED_13_15_LEN = 3 ;
+static const uint8_t P9N2_EQ_QPPM_EXCGCR_L2_EX1_CLK_SB_STRENGTH = 16 ;
+static const uint8_t P9N2_EQ_QPPM_EXCGCR_L2_EX1_CLK_SB_STRENGTH_LEN = 4 ;
+static const uint8_t P9N2_EQ_QPPM_EXCGCR_L2_EX1_CLK_SB_SPARE0 = 20 ;
+static const uint8_t P9N2_EQ_QPPM_EXCGCR_L2_EX1_CLK_SB_PULSE_MODE_EN = 21 ;
+static const uint8_t P9N2_EQ_QPPM_EXCGCR_L2_EX1_CLK_SB_PULSE_MODE = 22 ;
+static const uint8_t P9N2_EQ_QPPM_EXCGCR_L2_EX1_CLK_SB_PULSE_MODE_LEN = 2 ;
+static const uint8_t P9N2_EQ_QPPM_EXCGCR_L2_EX1_CLK_SW_RESCLK = 24 ;
+static const uint8_t P9N2_EQ_QPPM_EXCGCR_L2_EX1_CLK_SW_RESCLK_LEN = 4 ;
+static const uint8_t P9N2_EQ_QPPM_EXCGCR_L2_EX1_CLK_SW_SPARE1 = 28 ;
+static const uint8_t P9N2_EQ_QPPM_EXCGCR_RESERVED_29_31 = 29 ;
+static const uint8_t P9N2_EQ_QPPM_EXCGCR_RESERVED_29_31_LEN = 3 ;
+static const uint8_t P9N2_EQ_QPPM_EXCGCR_L2_EX0_CLKGLM_ASYNC_RESET = 32 ;
+static const uint8_t P9N2_EQ_QPPM_EXCGCR_L2_EX1_CLKGLM_ASYNC_RESET = 33 ;
+static const uint8_t P9N2_EQ_QPPM_EXCGCR_L2_EX0_CLKGLM_SEL = 34 ;
+static const uint8_t P9N2_EQ_QPPM_EXCGCR_L2_EX1_CLKGLM_SEL = 35 ;
+static const uint8_t P9N2_EQ_QPPM_EXCGCR_L2_EX0_CLK_SYNC_ENABLE = 36 ;
+static const uint8_t P9N2_EQ_QPPM_EXCGCR_L2_EX1_CLK_SYNC_ENABLE = 37 ;
+static const uint8_t P9N2_EQ_QPPM_EXCGCR_L2_EX0_CLK_SB_OVERRIDE = 38 ;
+static const uint8_t P9N2_EQ_QPPM_EXCGCR_L2_EX1_CLK_SB_OVERRIDE = 39 ;
+static const uint8_t P9N2_EQ_QPPM_EXCGCR_L2_EX0_CLK_SW_OVERRIDE = 40 ;
+static const uint8_t P9N2_EQ_QPPM_EXCGCR_L2_EX1_CLK_SW_OVERRIDE = 41 ;
+
+static const uint8_t P9N2_EQ_QPPM_OCCHB_OCC_HEARTBEAT_COUNT = 0 ;
+static const uint8_t P9N2_EQ_QPPM_OCCHB_OCC_HEARTBEAT_COUNT_LEN = 16 ;
+static const uint8_t P9N2_EQ_QPPM_OCCHB_OCC_HEARTBEAT_ENABLE = 16 ;
+
+static const uint8_t P9N2_EQ_QPPM_QACCR_COMMON_CLK_SB_STRENGTH = 0 ;
+static const uint8_t P9N2_EQ_QPPM_QACCR_COMMON_CLK_SB_STRENGTH_LEN = 4 ;
+static const uint8_t P9N2_EQ_QPPM_QACCR_COMMON_CLK_SB_SPARE = 4 ;
+static const uint8_t P9N2_EQ_QPPM_QACCR_COMMON_CLK_SB_PULSE_MODE_EN = 5 ;
+static const uint8_t P9N2_EQ_QPPM_QACCR_COMMON_CLK_SB_PULSE_MODE = 6 ;
+static const uint8_t P9N2_EQ_QPPM_QACCR_COMMON_CLK_SB_PULSE_MODE_LEN = 2 ;
+static const uint8_t P9N2_EQ_QPPM_QACCR_COMMON_CLK_SW_RESCLK = 8 ;
+static const uint8_t P9N2_EQ_QPPM_QACCR_COMMON_CLK_SW_RESCLK_LEN = 4 ;
+static const uint8_t P9N2_EQ_QPPM_QACCR_COMMON_CLK_SW_SPARE = 12 ;
+static const uint8_t P9N2_EQ_QPPM_QACCR_RESERVED_13_15 = 13 ;
+static const uint8_t P9N2_EQ_QPPM_QACCR_RESERVED_13_15_LEN = 3 ;
+static const uint8_t P9N2_EQ_QPPM_QACCR_L3_CLK_SB_STRENGTH = 16 ;
+static const uint8_t P9N2_EQ_QPPM_QACCR_L3_CLK_SB_STRENGTH_LEN = 4 ;
+static const uint8_t P9N2_EQ_QPPM_QACCR_L3_CLK_SB_SPARE0 = 20 ;
+static const uint8_t P9N2_EQ_QPPM_QACCR_L3_CLK_SB_PULSE_MODE_EN = 21 ;
+static const uint8_t P9N2_EQ_QPPM_QACCR_L3_CLK_SB_PULSE_MODE = 22 ;
+static const uint8_t P9N2_EQ_QPPM_QACCR_L3_CLK_SB_PULSE_MODE_LEN = 2 ;
+
+static const uint8_t P9N2_EQ_QPPM_QACSR_ACTUAL_L2_EX0_CLK_SB_STRENGTH = 0 ;
+static const uint8_t P9N2_EQ_QPPM_QACSR_ACTUAL_L2_EX0_CLK_SB_STRENGTH_LEN = 4 ;
+static const uint8_t P9N2_EQ_QPPM_QACSR_ACTUAL_L2_EX0_CLK_SB_SPARE0 = 4 ;
+static const uint8_t P9N2_EQ_QPPM_QACSR_ACTUAL_L2_EX0_CLK_SB_PULSE_MODE_EN = 5 ;
+static const uint8_t P9N2_EQ_QPPM_QACSR_ACTUAL_L2_EX0_CLK_SB_PULSE_MODE = 6 ;
+static const uint8_t P9N2_EQ_QPPM_QACSR_ACTUAL_L2_EX0_CLK_SB_PULSE_MODE_LEN = 2 ;
+static const uint8_t P9N2_EQ_QPPM_QACSR_ACTUAL_L2_EX0_CLK_SW_RESCLK = 8 ;
+static const uint8_t P9N2_EQ_QPPM_QACSR_ACTUAL_L2_EX0_CLK_SW_RESCLK_LEN = 4 ;
+static const uint8_t P9N2_EQ_QPPM_QACSR_ACTUAL_L2_EX0_CLK_SW_SPARE1 = 12 ;
+static const uint8_t P9N2_EQ_QPPM_QACSR_ACTUAL_L2_EX1_CLK_SB_STRENGTH = 16 ;
+static const uint8_t P9N2_EQ_QPPM_QACSR_ACTUAL_L2_EX1_CLK_SB_STRENGTH_LEN = 4 ;
+static const uint8_t P9N2_EQ_QPPM_QACSR_ACTUAL_L2_EX1_CLK_SB_SPARE0 = 20 ;
+static const uint8_t P9N2_EQ_QPPM_QACSR_ACTUAL_L2_EX1_CLK_SB_PULSE_MODE_EN = 21 ;
+static const uint8_t P9N2_EQ_QPPM_QACSR_ACTUAL_L2_EX1_CLK_SB_PULSE_MODE = 22 ;
+static const uint8_t P9N2_EQ_QPPM_QACSR_ACTUAL_L2_EX1_CLK_SB_PULSE_MODE_LEN = 2 ;
+static const uint8_t P9N2_EQ_QPPM_QACSR_ACTUAL_L2_EX1_CLK_SW_RESCLK = 24 ;
+static const uint8_t P9N2_EQ_QPPM_QACSR_ACTUAL_L2_EX1_CLK_SW_RESCLK_LEN = 4 ;
+static const uint8_t P9N2_EQ_QPPM_QACSR_ACTUAL_L2_EX1_CLK_SW_SPARE1 = 28 ;
+static const uint8_t P9N2_EQ_QPPM_QACSR_L2_EX0_CLK_SYNC_DONE = 36 ;
+static const uint8_t P9N2_EQ_QPPM_QACSR_L2_EX1_CLK_SYNC_DONE = 37 ;
+
+static const uint8_t P9N2_EQ_QPPM_QCCR_L3_EX0_EDRAM_ENABLE_ENCODE = 0 ;
+static const uint8_t P9N2_EQ_QPPM_QCCR_L3_EX0_EDRAM_ENABLE_ENCODE_LEN = 4 ;
+static const uint8_t P9N2_EQ_QPPM_QCCR_L3_EX1_EDRAM_ENABLE_ENCODE = 4 ;
+static const uint8_t P9N2_EQ_QPPM_QCCR_L3_EX1_EDRAM_ENABLE_ENCODE_LEN = 4 ;
+static const uint8_t P9N2_EQ_QPPM_QCCR_SPARE_8_11 = 8 ;
+static const uint8_t P9N2_EQ_QPPM_QCCR_SPARE_8_11_LEN = 4 ;
+static const uint8_t P9N2_EQ_QPPM_QCCR_DROOP_PROTECT_DATA = 12 ;
+static const uint8_t P9N2_EQ_QPPM_QCCR_DROOP_PROTECT_DATA_LEN = 4 ;
+static const uint8_t P9N2_EQ_QPPM_QCCR_FORCE_DROOP_DATA = 16 ;
+static const uint8_t P9N2_EQ_QPPM_QCCR_FORCE_DROOP_DATA_LEN = 4 ;
+static const uint8_t P9N2_EQ_QPPM_QCCR_PULSE_DROOP_DATA = 20 ;
+static const uint8_t P9N2_EQ_QPPM_QCCR_PULSE_DROOP_DATA_LEN = 4 ;
+static const uint8_t P9N2_EQ_QPPM_QCCR_PULSE_DROOP_ENABLE = 24 ;
+static const uint8_t P9N2_EQ_QPPM_QCCR_PB_PURGE_REQ = 30 ;
+static const uint8_t P9N2_EQ_QPPM_QCCR_PB_PURGE_DONE_LVL = 31 ;
+static const uint8_t P9N2_EQ_QPPM_QCCR_L3_EX0_EDRAM_ENABLE_ACTUAL = 32 ;
+static const uint8_t P9N2_EQ_QPPM_QCCR_L3_EX0_EDRAM_ENABLE_ACTUAL_LEN = 4 ;
+static const uint8_t P9N2_EQ_QPPM_QCCR_L3_EX1_EDRAM_ENABLE_ACTUAL = 36 ;
+static const uint8_t P9N2_EQ_QPPM_QCCR_L3_EX1_EDRAM_ENABLE_ACTUAL_LEN = 4 ;
+static const uint8_t P9N2_EQ_QPPM_QCCR_L3_EDRAM_SEQ_ERR = 40 ;
+static const uint8_t P9N2_EQ_QPPM_QCCR_L3_EDRAM_PGATE_ERR = 41 ;
+static const uint8_t P9N2_EQ_QPPM_QCCR_L3_EX0_EDRAM_UNLOCKED = 42 ;
+static const uint8_t P9N2_EQ_QPPM_QCCR_L3_EX1_EDRAM_UNLOCKED = 43 ;
+static const uint8_t P9N2_EQ_QPPM_QCCR_PCB_RSP_OOB_9 = 59 ;
+static const uint8_t P9N2_EQ_QPPM_QCCR_PCB_RSP_OOB_0123 = 60 ;
+static const uint8_t P9N2_EQ_QPPM_QCCR_PCB_RSP_OOB_0123_LEN = 4 ;
+
+static const uint8_t P9N2_EQ_QPPM_QPMMR_FORCE_FSAFE = 0 ;
+static const uint8_t P9N2_EQ_QPPM_QPMMR_FSAFE = 1 ;
+static const uint8_t P9N2_EQ_QPPM_QPMMR_FSAFE_LEN = 11 ;
+static const uint8_t P9N2_EQ_QPPM_QPMMR_ENABLE_FSAFE_UPON_HEARTBEAT_LOSS = 12 ;
+static const uint8_t P9N2_EQ_QPPM_QPMMR_ENABLE_DROOP_PROTECT_UPON_HEARTBEAT_LOSS = 13 ;
+static const uint8_t P9N2_EQ_QPPM_QPMMR_ENABLE_PFETS_UPON_IVRM_DROPOUT = 14 ;
+static const uint8_t P9N2_EQ_QPPM_QPMMR_ENABLE_PCB_INTR_UPON_HEARTBEAT_LOSS = 16 ;
+static const uint8_t P9N2_EQ_QPPM_QPMMR_ENABLE_PCB_INTR_UPON_IVRM_DROPOUT = 17 ;
+static const uint8_t P9N2_EQ_QPPM_QPMMR_ENABLE_PCB_INTR_UPON_LARGE_DROOP = 18 ;
+static const uint8_t P9N2_EQ_QPPM_QPMMR_ENABLE_PCB_INTR_UPON_EXTREME_DROOP = 19 ;
+static const uint8_t P9N2_EQ_QPPM_QPMMR_CME_INTERPPM_IVRM_ENABLE = 20 ;
+static const uint8_t P9N2_EQ_QPPM_QPMMR_CME_INTERPPM_IVRM_SEL = 21 ;
+static const uint8_t P9N2_EQ_QPPM_QPMMR_CME_INTERPPM_ACLK_ENABLE = 22 ;
+static const uint8_t P9N2_EQ_QPPM_QPMMR_CME_INTERPPM_ACLK_SEL = 23 ;
+static const uint8_t P9N2_EQ_QPPM_QPMMR_CME_INTERPPM_VDATA_ENABLE = 24 ;
+static const uint8_t P9N2_EQ_QPPM_QPMMR_CME_INTERPPM_VDATA_SEL = 25 ;
+static const uint8_t P9N2_EQ_QPPM_QPMMR_CME_INTERPPM_DPLL_ENABLE = 26 ;
+static const uint8_t P9N2_EQ_QPPM_QPMMR_CME_INTERPPM_DPLL_SEL = 27 ;
+static const uint8_t P9N2_EQ_QPPM_QPMMR_RESERVED28_31 = 28 ;
+static const uint8_t P9N2_EQ_QPPM_QPMMR_RESERVED28_31_LEN = 4 ;
+
+static const uint8_t P9N2_EQ_QPPM_VDMCFGR_VDM_VID_COMPARE = 0 ;
+static const uint8_t P9N2_EQ_QPPM_VDMCFGR_VDM_VID_COMPARE_LEN = 8 ;
+static const uint8_t P9N2_EQ_QPPM_VDMCFGR_VDM_OVERVOLT = 8 ;
+static const uint8_t P9N2_EQ_QPPM_VDMCFGR_VDM_OVERVOLT_LEN = 4 ;
+static const uint8_t P9N2_EQ_QPPM_VDMCFGR_VDM_DROOP_SMALL = 12 ;
+static const uint8_t P9N2_EQ_QPPM_VDMCFGR_VDM_DROOP_SMALL_LEN = 4 ;
+static const uint8_t P9N2_EQ_QPPM_VDMCFGR_VDM_DROOP_LARGE = 16 ;
+static const uint8_t P9N2_EQ_QPPM_VDMCFGR_VDM_DROOP_LARGE_LEN = 4 ;
+static const uint8_t P9N2_EQ_QPPM_VDMCFGR_VDM_DROOP_XTREME = 20 ;
+static const uint8_t P9N2_EQ_QPPM_VDMCFGR_VDM_DROOP_XTREME_LEN = 4 ;
+
+static const uint8_t P9N2_EQ_QPPM_VOLT_CHAR_VID_COMPARE_MAX = 0 ;
+static const uint8_t P9N2_EQ_QPPM_VOLT_CHAR_VID_COMPARE_MAX_LEN = 8 ;
+static const uint8_t P9N2_EQ_QPPM_VOLT_CHAR_VID_COMPARE_MIN = 8 ;
+static const uint8_t P9N2_EQ_QPPM_VOLT_CHAR_VID_COMPARE_MIN_LEN = 8 ;
+static const uint8_t P9N2_EQ_QPPM_VOLT_CHAR_IVRM_ENABLED_HISTORY = 16 ;
+
+static const uint8_t P9N2_EX_RAM_CTRL_RAM_VTID = 0 ;
+static const uint8_t P9N2_EX_RAM_CTRL_RAM_VTID_LEN = 2 ;
+static const uint8_t P9N2_EX_RAM_CTRL_PPC_PREDCD = 2 ;
+static const uint8_t P9N2_EX_RAM_CTRL_PPC_PREDCD_LEN = 4 ;
+static const uint8_t P9N2_EX_RAM_CTRL_SPARE = 6 ;
+static const uint8_t P9N2_EX_RAM_CTRL_SPARE_LEN = 2 ;
+static const uint8_t P9N2_EX_RAM_CTRL_PPC_INSTR = 8 ;
+static const uint8_t P9N2_EX_RAM_CTRL_PPC_INSTR_LEN = 32 ;
+
+static const uint8_t P9N2_C_RAM_CTRL_RAM_VTID = 0 ;
+static const uint8_t P9N2_C_RAM_CTRL_RAM_VTID_LEN = 2 ;
+static const uint8_t P9N2_C_RAM_CTRL_PPC_PREDCD = 2 ;
+static const uint8_t P9N2_C_RAM_CTRL_PPC_PREDCD_LEN = 4 ;
+static const uint8_t P9N2_C_RAM_CTRL_SPARE = 6 ;
+static const uint8_t P9N2_C_RAM_CTRL_SPARE_LEN = 2 ;
+static const uint8_t P9N2_C_RAM_CTRL_PPC_INSTR = 8 ;
+static const uint8_t P9N2_C_RAM_CTRL_PPC_INSTR_LEN = 32 ;
+
+static const uint8_t P9N2_EX_RAM_MODEREG_MODE_ENABLE = 0 ;
+
+static const uint8_t P9N2_C_RAM_MODEREG_MODE_ENABLE = 0 ;
+
+static const uint8_t P9N2_EX_L2_RAM_STATUS_RAM_CONTROL_ACCESS_DURING_RECOV = 0 ;
+static const uint8_t P9N2_EX_L2_RAM_STATUS_RAM_COMPLETION = 1 ;
+static const uint8_t P9N2_EX_L2_RAM_STATUS_RAM_EXCEPTION = 2 ;
+static const uint8_t P9N2_EX_L2_RAM_STATUS_LSU_EMPTY = 3 ;
+
+static const uint8_t P9N2_C_RAM_STATUS_RAM_CONTROL_ACCESS_DURING_RECOV = 0 ;
+static const uint8_t P9N2_C_RAM_STATUS_RAM_COMPLETION = 1 ;
+static const uint8_t P9N2_C_RAM_STATUS_RAM_EXCEPTION = 2 ;
+static const uint8_t P9N2_C_RAM_STATUS_LSU_EMPTY = 3 ;
+
+static const uint8_t P9N2_EX_L2_RAS_MODEREG_MR_DIS_PMON_INTR = 56 ;
+static const uint8_t P9N2_EX_L2_RAS_MODEREG_MR_FENCE_INTERRUPTS = 57 ;
+static const uint8_t P9N2_EX_L2_RAS_MODEREG_MR_BLOCK_HMI_IN_MAINT = 62 ;
+static const uint8_t P9N2_EX_L2_RAS_MODEREG_MR_FENCE_INTR_ON_CHECKSTOP = 63 ;
+
+static const uint8_t P9N2_C_RAS_MODEREG_MR_DIS_PMON_INTR = 56 ;
+static const uint8_t P9N2_C_RAS_MODEREG_MR_FENCE_INTERRUPTS = 57 ;
+static const uint8_t P9N2_C_RAS_MODEREG_MR_BLOCK_HMI_IN_MAINT = 62 ;
+static const uint8_t P9N2_C_RAS_MODEREG_MR_FENCE_INTR_ON_CHECKSTOP = 63 ;
+
+static const uint8_t P9N2_EX_L2_RAS_STATUS_VT0_CORE_MAINT = 0 ;
+static const uint8_t P9N2_EX_L2_RAS_STATUS_VT0_THREAD_QUIESCED = 1 ;
+static const uint8_t P9N2_EX_L2_RAS_STATUS_VT0_ICT_EMPTY = 2 ;
+static const uint8_t P9N2_EX_L2_RAS_STATUS_VT0_LSU_QUIESCED = 3 ;
+static const uint8_t P9N2_EX_L2_RAS_STATUS_VT0_STEP_SUCCESS = 4 ;
+static const uint8_t P9N2_EX_L2_RAS_STATUS_VT1_CORE_MAINT = 8 ;
+static const uint8_t P9N2_EX_L2_RAS_STATUS_VT1_THREAD_QUIESCED = 9 ;
+static const uint8_t P9N2_EX_L2_RAS_STATUS_VT1_ICT_EMPTY = 10 ;
+static const uint8_t P9N2_EX_L2_RAS_STATUS_VT1_LSU_QUIESCED = 11 ;
+static const uint8_t P9N2_EX_L2_RAS_STATUS_VT1_STEP_SUCCESS = 12 ;
+static const uint8_t P9N2_EX_L2_RAS_STATUS_VT2_CORE_MAINT = 16 ;
+static const uint8_t P9N2_EX_L2_RAS_STATUS_VT2_THREAD_QUIESCED = 17 ;
+static const uint8_t P9N2_EX_L2_RAS_STATUS_VT2_ICT_EMPTY = 18 ;
+static const uint8_t P9N2_EX_L2_RAS_STATUS_VT2_LSU_QUIESCED = 19 ;
+static const uint8_t P9N2_EX_L2_RAS_STATUS_VT2_STEP_SUCCESS = 20 ;
+static const uint8_t P9N2_EX_L2_RAS_STATUS_VT3_CORE_MAINT = 24 ;
+static const uint8_t P9N2_EX_L2_RAS_STATUS_VT3_THREAD_QUIESCED = 25 ;
+static const uint8_t P9N2_EX_L2_RAS_STATUS_VT3_ICT_EMPTY = 26 ;
+static const uint8_t P9N2_EX_L2_RAS_STATUS_VT3_LSU_QUIESCED = 27 ;
+static const uint8_t P9N2_EX_L2_RAS_STATUS_VT3_STEP_SUCCESS = 28 ;
+static const uint8_t P9N2_EX_L2_RAS_STATUS_NEST_ACTIVE = 32 ;
+
+static const uint8_t P9N2_C_RAS_STATUS_VT0_CORE_MAINT = 0 ;
+static const uint8_t P9N2_C_RAS_STATUS_VT0_THREAD_QUIESCED = 1 ;
+static const uint8_t P9N2_C_RAS_STATUS_VT0_ICT_EMPTY = 2 ;
+static const uint8_t P9N2_C_RAS_STATUS_VT0_LSU_QUIESCED = 3 ;
+static const uint8_t P9N2_C_RAS_STATUS_VT0_STEP_SUCCESS = 4 ;
+static const uint8_t P9N2_C_RAS_STATUS_VT1_CORE_MAINT = 8 ;
+static const uint8_t P9N2_C_RAS_STATUS_VT1_THREAD_QUIESCED = 9 ;
+static const uint8_t P9N2_C_RAS_STATUS_VT1_ICT_EMPTY = 10 ;
+static const uint8_t P9N2_C_RAS_STATUS_VT1_LSU_QUIESCED = 11 ;
+static const uint8_t P9N2_C_RAS_STATUS_VT1_STEP_SUCCESS = 12 ;
+static const uint8_t P9N2_C_RAS_STATUS_VT2_CORE_MAINT = 16 ;
+static const uint8_t P9N2_C_RAS_STATUS_VT2_THREAD_QUIESCED = 17 ;
+static const uint8_t P9N2_C_RAS_STATUS_VT2_ICT_EMPTY = 18 ;
+static const uint8_t P9N2_C_RAS_STATUS_VT2_LSU_QUIESCED = 19 ;
+static const uint8_t P9N2_C_RAS_STATUS_VT2_STEP_SUCCESS = 20 ;
+static const uint8_t P9N2_C_RAS_STATUS_VT3_CORE_MAINT = 24 ;
+static const uint8_t P9N2_C_RAS_STATUS_VT3_THREAD_QUIESCED = 25 ;
+static const uint8_t P9N2_C_RAS_STATUS_VT3_ICT_EMPTY = 26 ;
+static const uint8_t P9N2_C_RAS_STATUS_VT3_LSU_QUIESCED = 27 ;
+static const uint8_t P9N2_C_RAS_STATUS_VT3_STEP_SUCCESS = 28 ;
+static const uint8_t P9N2_C_RAS_STATUS_NEST_ACTIVE = 32 ;
+
+static const uint8_t P9N2_EQ_RD_EPS_REG_TIER0_VALUE = 0 ;
+static const uint8_t P9N2_EQ_RD_EPS_REG_TIER0_VALUE_LEN = 12 ;
+static const uint8_t P9N2_EQ_RD_EPS_REG_TIER1_VALUE = 12 ;
+static const uint8_t P9N2_EQ_RD_EPS_REG_TIER1_VALUE_LEN = 12 ;
+static const uint8_t P9N2_EQ_RD_EPS_REG_TIER2_VALUE = 24 ;
+static const uint8_t P9N2_EQ_RD_EPS_REG_TIER2_VALUE_LEN = 12 ;
+
+static const uint8_t P9N2_EX_L2_RD_EPS_REG_TIER0_VALUE = 0 ;
+static const uint8_t P9N2_EX_L2_RD_EPS_REG_TIER0_VALUE_LEN = 12 ;
+static const uint8_t P9N2_EX_L2_RD_EPS_REG_TIER1_VALUE = 12 ;
+static const uint8_t P9N2_EX_L2_RD_EPS_REG_TIER1_VALUE_LEN = 12 ;
+static const uint8_t P9N2_EX_L2_RD_EPS_REG_TIER2_VALUE = 24 ;
+static const uint8_t P9N2_EX_L2_RD_EPS_REG_TIER2_VALUE_LEN = 12 ;
+
+static const uint8_t P9N2_EX_L2_RECOV_FWD_PROG_CTRL_RESET_FWD_PROG = 0 ;
+static const uint8_t P9N2_EX_L2_RECOV_FWD_PROG_CTRL_FWD_PROG_THOLD = 1 ;
+static const uint8_t P9N2_EX_L2_RECOV_FWD_PROG_CTRL_FWD_PROG_THOLD_LEN = 3 ;
+
+static const uint8_t P9N2_C_RECOV_FWD_PROG_CTRL_RESET_FWD_PROG = 0 ;
+static const uint8_t P9N2_C_RECOV_FWD_PROG_CTRL_FWD_PROG_THOLD = 1 ;
+static const uint8_t P9N2_C_RECOV_FWD_PROG_CTRL_FWD_PROG_THOLD_LEN = 3 ;
+
+static const uint8_t P9N2_EQ_RECOV_INTERRUPT_REG_RECOV = 0 ;
+
+static const uint8_t P9N2_EX_RECOV_INTERRUPT_REG_RECOV = 0 ;
+
+static const uint8_t P9N2_C_RECOV_INTERRUPT_REG_RECOV = 0 ;
+
+static const uint8_t P9N2_EX_L2_RECOV_THOLD_THRESHOLD_LIMIT = 0 ;
+static const uint8_t P9N2_EX_L2_RECOV_THOLD_THRESHOLD_LIMIT_LEN = 8 ;
+static const uint8_t P9N2_EX_L2_RECOV_THOLD_THRESHOLD_RESET = 8 ;
+static const uint8_t P9N2_EX_L2_RECOV_THOLD_THRESHOLD_RESET_LEN = 2 ;
+
+static const uint8_t P9N2_C_RECOV_THOLD_THRESHOLD_LIMIT = 0 ;
+static const uint8_t P9N2_C_RECOV_THOLD_THRESHOLD_LIMIT_LEN = 8 ;
+static const uint8_t P9N2_C_RECOV_THOLD_THRESHOLD_RESET = 8 ;
+static const uint8_t P9N2_C_RECOV_THOLD_THRESHOLD_RESET_LEN = 2 ;
+
+static const uint8_t P9N2_EX_L2_RESET_KEEPER_RESET_KEEPER = 0 ;
+static const uint8_t P9N2_EX_L2_RESET_KEEPER_CORE_SYS_ENABLE = 1 ;
+
+static const uint8_t P9N2_C_RESET_KEEPER_RESET_KEEPER = 0 ;
+static const uint8_t P9N2_C_RESET_KEEPER_CORE_SYS_ENABLE = 1 ;
+
+static const uint8_t P9N2_EQ_RFIR_IN0 = 0 ;
+static const uint8_t P9N2_EQ_RFIR_LFIR_RECOV_ERR = 1 ;
+static const uint8_t P9N2_EQ_RFIR_IN4 = 2 ;
+static const uint8_t P9N2_EQ_RFIR_IN5 = 3 ;
+static const uint8_t P9N2_EQ_RFIR_IN6 = 4 ;
+static const uint8_t P9N2_EQ_RFIR_IN7 = 5 ;
+static const uint8_t P9N2_EQ_RFIR_IN8 = 6 ;
+static const uint8_t P9N2_EQ_RFIR_IN9 = 7 ;
+static const uint8_t P9N2_EQ_RFIR_IN10 = 8 ;
+static const uint8_t P9N2_EQ_RFIR_IN11 = 9 ;
+static const uint8_t P9N2_EQ_RFIR_IN12 = 10 ;
+static const uint8_t P9N2_EQ_RFIR_IN13 = 11 ;
+static const uint8_t P9N2_EQ_RFIR_IN13_LEN = 13 ;
+
+static const uint8_t P9N2_EX_RFIR_IN0 = 0 ;
+static const uint8_t P9N2_EX_RFIR_LFIR_RECOV_ERR = 1 ;
+static const uint8_t P9N2_EX_RFIR_IN4 = 2 ;
+static const uint8_t P9N2_EX_RFIR_IN5 = 3 ;
+static const uint8_t P9N2_EX_RFIR_IN5_LEN = 21 ;
+
+static const uint8_t P9N2_C_RFIR_IN0 = 0 ;
+static const uint8_t P9N2_C_RFIR_LFIR_RECOV_ERR = 1 ;
+static const uint8_t P9N2_C_RFIR_IN4 = 2 ;
+static const uint8_t P9N2_C_RFIR_IN5 = 3 ;
+static const uint8_t P9N2_C_RFIR_IN5_LEN = 21 ;
+
+static const uint8_t P9N2_EQ_RING_FENCE_MASK_LATCH_REG_ENABLE = 1 ;
+static const uint8_t P9N2_EQ_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN = 15 ;
+
+static const uint8_t P9N2_EX_RING_FENCE_MASK_LATCH_REG_ENABLE = 1 ;
+static const uint8_t P9N2_EX_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN = 15 ;
+
+static const uint8_t P9N2_C_RING_FENCE_MASK_LATCH_REG_ENABLE = 1 ;
+static const uint8_t P9N2_C_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN = 15 ;
+
+static const uint8_t P9N2_EQ_SCAN32_SCAN32_REG = 0 ;
+static const uint8_t P9N2_EQ_SCAN32_SCAN32_REG_LEN = 32 ;
+
+static const uint8_t P9N2_EX_SCAN32_SCAN32_REG = 0 ;
+static const uint8_t P9N2_EX_SCAN32_SCAN32_REG_LEN = 32 ;
+
+static const uint8_t P9N2_C_SCAN32_SCAN32_REG = 0 ;
+static const uint8_t P9N2_C_SCAN32_SCAN32_REG_LEN = 32 ;
+
+static const uint8_t P9N2_EQ_SCAN64_SCAN64_REG = 0 ;
+static const uint8_t P9N2_EQ_SCAN64_SCAN64_REG_LEN = 64 ;
+
+static const uint8_t P9N2_EX_SCAN64_SCAN64_REG = 0 ;
+static const uint8_t P9N2_EX_SCAN64_SCAN64_REG_LEN = 64 ;
+
+static const uint8_t P9N2_C_SCAN64_SCAN64_REG = 0 ;
+static const uint8_t P9N2_C_SCAN64_SCAN64_REG_LEN = 64 ;
+
+static const uint8_t P9N2_EQ_SCAN_CAPTUREDR_SCAN_CAPTUREDR_REG = 0 ;
+static const uint8_t P9N2_EQ_SCAN_CAPTUREDR_SCAN_CAPTUREDR_REG_LEN = 32 ;
+
+static const uint8_t P9N2_EX_SCAN_CAPTUREDR_SCAN_CAPTUREDR_REG = 0 ;
+static const uint8_t P9N2_EX_SCAN_CAPTUREDR_SCAN_CAPTUREDR_REG_LEN = 32 ;
+
+static const uint8_t P9N2_C_SCAN_CAPTUREDR_SCAN_CAPTUREDR_REG = 0 ;
+static const uint8_t P9N2_C_SCAN_CAPTUREDR_SCAN_CAPTUREDR_REG_LEN = 32 ;
+
+static const uint8_t P9N2_EQ_SCAN_CAPTUREDR_LONG_SCAN_CAPTUREDR_LONG_REG = 0 ;
+static const uint8_t P9N2_EQ_SCAN_CAPTUREDR_LONG_SCAN_CAPTUREDR_LONG_REG_LEN = 32 ;
+
+static const uint8_t P9N2_EX_SCAN_CAPTUREDR_LONG_SCAN_CAPTUREDR_LONG_REG = 0 ;
+static const uint8_t P9N2_EX_SCAN_CAPTUREDR_LONG_SCAN_CAPTUREDR_LONG_REG_LEN = 32 ;
+
+static const uint8_t P9N2_C_SCAN_CAPTUREDR_LONG_SCAN_CAPTUREDR_LONG_REG = 0 ;
+static const uint8_t P9N2_C_SCAN_CAPTUREDR_LONG_SCAN_CAPTUREDR_LONG_REG_LEN = 32 ;
+
+static const uint8_t P9N2_EQ_SCAN_REGION_TYPE_SYSTEM_FAST_INIT = 0 ;
+static const uint8_t P9N2_EQ_SCAN_REGION_TYPE_VITL = 3 ;
+static const uint8_t P9N2_EQ_SCAN_REGION_TYPE_PERV = 4 ;
+static const uint8_t P9N2_EQ_SCAN_REGION_TYPE_UNIT1 = 5 ;
+static const uint8_t P9N2_EQ_SCAN_REGION_TYPE_UNIT2 = 6 ;
+static const uint8_t P9N2_EQ_SCAN_REGION_TYPE_UNIT3 = 7 ;
+static const uint8_t P9N2_EQ_SCAN_REGION_TYPE_UNIT4 = 8 ;
+static const uint8_t P9N2_EQ_SCAN_REGION_TYPE_UNIT5 = 9 ;
+static const uint8_t P9N2_EQ_SCAN_REGION_TYPE_UNIT6 = 10 ;
+static const uint8_t P9N2_EQ_SCAN_REGION_TYPE_UNIT7 = 11 ;
+static const uint8_t P9N2_EQ_SCAN_REGION_TYPE_UNIT8 = 12 ;
+static const uint8_t P9N2_EQ_SCAN_REGION_TYPE_UNIT9 = 13 ;
+static const uint8_t P9N2_EQ_SCAN_REGION_TYPE_UNIT10 = 14 ;
+static const uint8_t P9N2_EQ_SCAN_REGION_TYPE_FUNC = 48 ;
+static const uint8_t P9N2_EQ_SCAN_REGION_TYPE_CFG = 49 ;
+static const uint8_t P9N2_EQ_SCAN_REGION_TYPE_CCFG_GPTR = 50 ;
+static const uint8_t P9N2_EQ_SCAN_REGION_TYPE_REGF = 51 ;
+static const uint8_t P9N2_EQ_SCAN_REGION_TYPE_LBIST = 52 ;
+static const uint8_t P9N2_EQ_SCAN_REGION_TYPE_ABIST = 53 ;
+static const uint8_t P9N2_EQ_SCAN_REGION_TYPE_REPR = 54 ;
+static const uint8_t P9N2_EQ_SCAN_REGION_TYPE_TIME = 55 ;
+static const uint8_t P9N2_EQ_SCAN_REGION_TYPE_BNDY = 56 ;
+static const uint8_t P9N2_EQ_SCAN_REGION_TYPE_FARR = 57 ;
+static const uint8_t P9N2_EQ_SCAN_REGION_TYPE_CMSK = 58 ;
+static const uint8_t P9N2_EQ_SCAN_REGION_TYPE_INEX = 59 ;
+
+static const uint8_t P9N2_EX_SCAN_REGION_TYPE_SYSTEM_FAST_INIT = 0 ;
+static const uint8_t P9N2_EX_SCAN_REGION_TYPE_VITL = 3 ;
+static const uint8_t P9N2_EX_SCAN_REGION_TYPE_PERV = 4 ;
+static const uint8_t P9N2_EX_SCAN_REGION_TYPE_UNIT1 = 5 ;
+static const uint8_t P9N2_EX_SCAN_REGION_TYPE_UNIT2 = 6 ;
+static const uint8_t P9N2_EX_SCAN_REGION_TYPE_UNIT3 = 7 ;
+static const uint8_t P9N2_EX_SCAN_REGION_TYPE_UNIT4 = 8 ;
+static const uint8_t P9N2_EX_SCAN_REGION_TYPE_UNIT5 = 9 ;
+static const uint8_t P9N2_EX_SCAN_REGION_TYPE_UNIT6 = 10 ;
+static const uint8_t P9N2_EX_SCAN_REGION_TYPE_UNIT7 = 11 ;
+static const uint8_t P9N2_EX_SCAN_REGION_TYPE_UNIT8 = 12 ;
+static const uint8_t P9N2_EX_SCAN_REGION_TYPE_UNIT9 = 13 ;
+static const uint8_t P9N2_EX_SCAN_REGION_TYPE_UNIT10 = 14 ;
+static const uint8_t P9N2_EX_SCAN_REGION_TYPE_FUNC = 48 ;
+static const uint8_t P9N2_EX_SCAN_REGION_TYPE_CFG = 49 ;
+static const uint8_t P9N2_EX_SCAN_REGION_TYPE_CCFG_GPTR = 50 ;
+static const uint8_t P9N2_EX_SCAN_REGION_TYPE_REGF = 51 ;
+static const uint8_t P9N2_EX_SCAN_REGION_TYPE_LBIST = 52 ;
+static const uint8_t P9N2_EX_SCAN_REGION_TYPE_ABIST = 53 ;
+static const uint8_t P9N2_EX_SCAN_REGION_TYPE_REPR = 54 ;
+static const uint8_t P9N2_EX_SCAN_REGION_TYPE_TIME = 55 ;
+static const uint8_t P9N2_EX_SCAN_REGION_TYPE_BNDY = 56 ;
+static const uint8_t P9N2_EX_SCAN_REGION_TYPE_FARR = 57 ;
+static const uint8_t P9N2_EX_SCAN_REGION_TYPE_CMSK = 58 ;
+static const uint8_t P9N2_EX_SCAN_REGION_TYPE_INEX = 59 ;
+
+static const uint8_t P9N2_C_SCAN_REGION_TYPE_SYSTEM_FAST_INIT = 0 ;
+static const uint8_t P9N2_C_SCAN_REGION_TYPE_VITL = 3 ;
+static const uint8_t P9N2_C_SCAN_REGION_TYPE_PERV = 4 ;
+static const uint8_t P9N2_C_SCAN_REGION_TYPE_UNIT1 = 5 ;
+static const uint8_t P9N2_C_SCAN_REGION_TYPE_UNIT2 = 6 ;
+static const uint8_t P9N2_C_SCAN_REGION_TYPE_UNIT3 = 7 ;
+static const uint8_t P9N2_C_SCAN_REGION_TYPE_UNIT4 = 8 ;
+static const uint8_t P9N2_C_SCAN_REGION_TYPE_UNIT5 = 9 ;
+static const uint8_t P9N2_C_SCAN_REGION_TYPE_UNIT6 = 10 ;
+static const uint8_t P9N2_C_SCAN_REGION_TYPE_UNIT7 = 11 ;
+static const uint8_t P9N2_C_SCAN_REGION_TYPE_UNIT8 = 12 ;
+static const uint8_t P9N2_C_SCAN_REGION_TYPE_UNIT9 = 13 ;
+static const uint8_t P9N2_C_SCAN_REGION_TYPE_UNIT10 = 14 ;
+static const uint8_t P9N2_C_SCAN_REGION_TYPE_FUNC = 48 ;
+static const uint8_t P9N2_C_SCAN_REGION_TYPE_CFG = 49 ;
+static const uint8_t P9N2_C_SCAN_REGION_TYPE_CCFG_GPTR = 50 ;
+static const uint8_t P9N2_C_SCAN_REGION_TYPE_REGF = 51 ;
+static const uint8_t P9N2_C_SCAN_REGION_TYPE_LBIST = 52 ;
+static const uint8_t P9N2_C_SCAN_REGION_TYPE_ABIST = 53 ;
+static const uint8_t P9N2_C_SCAN_REGION_TYPE_REPR = 54 ;
+static const uint8_t P9N2_C_SCAN_REGION_TYPE_TIME = 55 ;
+static const uint8_t P9N2_C_SCAN_REGION_TYPE_BNDY = 56 ;
+static const uint8_t P9N2_C_SCAN_REGION_TYPE_FARR = 57 ;
+static const uint8_t P9N2_C_SCAN_REGION_TYPE_CMSK = 58 ;
+static const uint8_t P9N2_C_SCAN_REGION_TYPE_INEX = 59 ;
+
+static const uint8_t P9N2_EQ_SCAN_UPDATEDR_SCAN_UPDATEDR_REG = 0 ;
+static const uint8_t P9N2_EQ_SCAN_UPDATEDR_SCAN_UPDATEDR_REG_LEN = 32 ;
+
+static const uint8_t P9N2_EX_SCAN_UPDATEDR_SCAN_UPDATEDR_REG = 0 ;
+static const uint8_t P9N2_EX_SCAN_UPDATEDR_SCAN_UPDATEDR_REG_LEN = 32 ;
+
+static const uint8_t P9N2_C_SCAN_UPDATEDR_SCAN_UPDATEDR_REG = 0 ;
+static const uint8_t P9N2_C_SCAN_UPDATEDR_SCAN_UPDATEDR_REG_LEN = 32 ;
+
+static const uint8_t P9N2_EQ_SCAN_UPDATEDR_LONG_SCAN_UPDATEDR_LONG_REG = 0 ;
+static const uint8_t P9N2_EQ_SCAN_UPDATEDR_LONG_SCAN_UPDATEDR_LONG_REG_LEN = 32 ;
+
+static const uint8_t P9N2_EX_SCAN_UPDATEDR_LONG_SCAN_UPDATEDR_LONG_REG = 0 ;
+static const uint8_t P9N2_EX_SCAN_UPDATEDR_LONG_SCAN_UPDATEDR_LONG_REG_LEN = 32 ;
+
+static const uint8_t P9N2_C_SCAN_UPDATEDR_LONG_SCAN_UPDATEDR_LONG_REG = 0 ;
+static const uint8_t P9N2_C_SCAN_UPDATEDR_LONG_SCAN_UPDATEDR_LONG_REG_LEN = 32 ;
+
+static const uint8_t P9N2_EX_L2_SCOMC_MODE_CX = 54 ;
+static const uint8_t P9N2_EX_L2_SCOMC_MODE_CX_LEN = 7 ;
+
+static const uint8_t P9N2_C_SCOMC_MODE_CX = 54 ;
+static const uint8_t P9N2_C_SCOMC_MODE_CX_LEN = 7 ;
+
+static const uint8_t P9N2_EX_L2_SHID0_TRIG2_TRACE_EN = 0 ;
+static const uint8_t P9N2_EX_L2_SHID0_DIS_TRACE_SPR = 1 ;
+
+static const uint8_t P9N2_C_SHID0_TRIG2_TRACE_EN = 0 ;
+static const uint8_t P9N2_C_SHID0_DIS_TRACE_SPR = 1 ;
+
+static const uint8_t P9N2_EX_SIER_MASK_SIER_MASK_TBD = 0 ;
+static const uint8_t P9N2_EX_SIER_MASK_SIER_MASK_TBD_LEN = 64 ;
+
+static const uint8_t P9N2_C_SIER_MASK_SIER_MASK_TBD = 0 ;
+static const uint8_t P9N2_C_SIER_MASK_SIER_MASK_TBD_LEN = 64 ;
+
+static const uint8_t P9N2_EQ_SKITTER_CLKSRC_REG_SKITTER0 = 0 ;
+static const uint8_t P9N2_EQ_SKITTER_CLKSRC_REG_SKITTER0_LEN = 3 ;
+static const uint8_t P9N2_EQ_SKITTER_CLKSRC_REG_SKITTER0_DELAY_SELECT = 36 ;
+static const uint8_t P9N2_EQ_SKITTER_CLKSRC_REG_SKITTER0_DELAY_SELECT_LEN = 2 ;
+
+static const uint8_t P9N2_EX_SKITTER_CLKSRC_REG_SKITTER0 = 0 ;
+static const uint8_t P9N2_EX_SKITTER_CLKSRC_REG_SKITTER0_LEN = 3 ;
+static const uint8_t P9N2_EX_SKITTER_CLKSRC_REG_SKITTER0_DELAY_SELECT = 36 ;
+static const uint8_t P9N2_EX_SKITTER_CLKSRC_REG_SKITTER0_DELAY_SELECT_LEN = 2 ;
+
+static const uint8_t P9N2_C_SKITTER_CLKSRC_REG_SKITTER0 = 0 ;
+static const uint8_t P9N2_C_SKITTER_CLKSRC_REG_SKITTER0_LEN = 3 ;
+static const uint8_t P9N2_C_SKITTER_CLKSRC_REG_SKITTER0_DELAY_SELECT = 36 ;
+static const uint8_t P9N2_C_SKITTER_CLKSRC_REG_SKITTER0_DELAY_SELECT_LEN = 2 ;
+
+static const uint8_t P9N2_EQ_SKITTER_FORCE_REG_F_READ = 0 ;
+
+static const uint8_t P9N2_EX_SKITTER_FORCE_REG_F_READ = 0 ;
+
+static const uint8_t P9N2_C_SKITTER_FORCE_REG_F_READ = 0 ;
+
+static const uint8_t P9N2_EQ_SKITTER_MODE_REG_HOLD_SAMPLE = 0 ;
+static const uint8_t P9N2_EQ_SKITTER_MODE_REG_DISABLE_STICKINESS = 1 ;
+static const uint8_t P9N2_EQ_SKITTER_MODE_REG_UNUSED1 = 2 ;
+static const uint8_t P9N2_EQ_SKITTER_MODE_REG_UNUSED1_LEN = 2 ;
+static const uint8_t P9N2_EQ_SKITTER_MODE_REG_HOLD_DBGTRIG_SEL = 4 ;
+static const uint8_t P9N2_EQ_SKITTER_MODE_REG_HOLD_DBGTRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_EQ_SKITTER_MODE_REG_RESET_TRIG_SEL = 6 ;
+static const uint8_t P9N2_EQ_SKITTER_MODE_REG_RESET_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_EQ_SKITTER_MODE_REG_SAMPLE_GUTS = 8 ;
+static const uint8_t P9N2_EQ_SKITTER_MODE_REG_SAMPLE_GUTS_LEN = 2 ;
+static const uint8_t P9N2_EQ_SKITTER_MODE_REG_HOLD_SAMPLE_WITH_TRIGGER = 44 ;
+static const uint8_t P9N2_EQ_SKITTER_MODE_REG_DATA_V_LT = 45 ;
+
+static const uint8_t P9N2_EX_SKITTER_MODE_REG_HOLD_SAMPLE = 0 ;
+static const uint8_t P9N2_EX_SKITTER_MODE_REG_DISABLE_STICKINESS = 1 ;
+static const uint8_t P9N2_EX_SKITTER_MODE_REG_UNUSED1 = 2 ;
+static const uint8_t P9N2_EX_SKITTER_MODE_REG_UNUSED1_LEN = 2 ;
+static const uint8_t P9N2_EX_SKITTER_MODE_REG_HOLD_DBGTRIG_SEL = 4 ;
+static const uint8_t P9N2_EX_SKITTER_MODE_REG_HOLD_DBGTRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_EX_SKITTER_MODE_REG_RESET_TRIG_SEL = 6 ;
+static const uint8_t P9N2_EX_SKITTER_MODE_REG_RESET_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_EX_SKITTER_MODE_REG_SAMPLE_GUTS = 8 ;
+static const uint8_t P9N2_EX_SKITTER_MODE_REG_SAMPLE_GUTS_LEN = 2 ;
+static const uint8_t P9N2_EX_SKITTER_MODE_REG_HOLD_SAMPLE_WITH_TRIGGER = 44 ;
+static const uint8_t P9N2_EX_SKITTER_MODE_REG_DATA_V_LT = 45 ;
+
+static const uint8_t P9N2_C_SKITTER_MODE_REG_HOLD_SAMPLE = 0 ;
+static const uint8_t P9N2_C_SKITTER_MODE_REG_DISABLE_STICKINESS = 1 ;
+static const uint8_t P9N2_C_SKITTER_MODE_REG_UNUSED1 = 2 ;
+static const uint8_t P9N2_C_SKITTER_MODE_REG_UNUSED1_LEN = 2 ;
+static const uint8_t P9N2_C_SKITTER_MODE_REG_HOLD_DBGTRIG_SEL = 4 ;
+static const uint8_t P9N2_C_SKITTER_MODE_REG_HOLD_DBGTRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_C_SKITTER_MODE_REG_RESET_TRIG_SEL = 6 ;
+static const uint8_t P9N2_C_SKITTER_MODE_REG_RESET_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_C_SKITTER_MODE_REG_SAMPLE_GUTS = 8 ;
+static const uint8_t P9N2_C_SKITTER_MODE_REG_SAMPLE_GUTS_LEN = 2 ;
+static const uint8_t P9N2_C_SKITTER_MODE_REG_HOLD_SAMPLE_WITH_TRIGGER = 44 ;
+static const uint8_t P9N2_C_SKITTER_MODE_REG_DATA_V_LT = 45 ;
+
+static const uint8_t P9N2_EQ_SLAVE_CONFIG_REG_CFG_DISABLE_PERV_THOLD_CHECK = 0 ;
+static const uint8_t P9N2_EQ_SLAVE_CONFIG_REG_CFG_DISABLE_MALF_PULSE_GEN = 1 ;
+static const uint8_t P9N2_EQ_SLAVE_CONFIG_REG_CFG_STOP_HANG_CNT_SYS_XSTP = 2 ;
+static const uint8_t P9N2_EQ_SLAVE_CONFIG_REG_CFG_DISABLE_CL_ATOMIC_LOCK = 3 ;
+static const uint8_t P9N2_EQ_SLAVE_CONFIG_REG_CFG_DISABLE_HEARTBEAT = 4 ;
+static const uint8_t P9N2_EQ_SLAVE_CONFIG_REG_CFG_DISABLE_FORCE_TO_ZERO = 5 ;
+static const uint8_t P9N2_EQ_SLAVE_CONFIG_REG_CFG_PM_DISABLE = 6 ;
+static const uint8_t P9N2_EQ_SLAVE_CONFIG_REG_CFG_PM_MUX_DISABLE = 7 ;
+static const uint8_t P9N2_EQ_SLAVE_CONFIG_REG_ERROR_MASK = 8 ;
+static const uint8_t P9N2_EQ_SLAVE_CONFIG_REG_ERROR_MASK_LEN = 6 ;
+
+static const uint8_t P9N2_EX_SLAVE_CONFIG_REG_CFG_DISABLE_PERV_THOLD_CHECK = 0 ;
+static const uint8_t P9N2_EX_SLAVE_CONFIG_REG_CFG_DISABLE_MALF_PULSE_GEN = 1 ;
+static const uint8_t P9N2_EX_SLAVE_CONFIG_REG_CFG_STOP_HANG_CNT_SYS_XSTP = 2 ;
+static const uint8_t P9N2_EX_SLAVE_CONFIG_REG_CFG_DISABLE_CL_ATOMIC_LOCK = 3 ;
+static const uint8_t P9N2_EX_SLAVE_CONFIG_REG_CFG_DISABLE_HEARTBEAT = 4 ;
+static const uint8_t P9N2_EX_SLAVE_CONFIG_REG_CFG_DISABLE_FORCE_TO_ZERO = 5 ;
+static const uint8_t P9N2_EX_SLAVE_CONFIG_REG_CFG_PM_DISABLE = 6 ;
+static const uint8_t P9N2_EX_SLAVE_CONFIG_REG_CFG_PM_MUX_DISABLE = 7 ;
+static const uint8_t P9N2_EX_SLAVE_CONFIG_REG_ERROR_MASK = 8 ;
+static const uint8_t P9N2_EX_SLAVE_CONFIG_REG_ERROR_MASK_LEN = 6 ;
+
+static const uint8_t P9N2_C_SLAVE_CONFIG_REG_CFG_DISABLE_PERV_THOLD_CHECK = 0 ;
+static const uint8_t P9N2_C_SLAVE_CONFIG_REG_CFG_DISABLE_MALF_PULSE_GEN = 1 ;
+static const uint8_t P9N2_C_SLAVE_CONFIG_REG_CFG_STOP_HANG_CNT_SYS_XSTP = 2 ;
+static const uint8_t P9N2_C_SLAVE_CONFIG_REG_CFG_DISABLE_CL_ATOMIC_LOCK = 3 ;
+static const uint8_t P9N2_C_SLAVE_CONFIG_REG_CFG_DISABLE_HEARTBEAT = 4 ;
+static const uint8_t P9N2_C_SLAVE_CONFIG_REG_CFG_DISABLE_FORCE_TO_ZERO = 5 ;
+static const uint8_t P9N2_C_SLAVE_CONFIG_REG_CFG_PM_DISABLE = 6 ;
+static const uint8_t P9N2_C_SLAVE_CONFIG_REG_CFG_PM_MUX_DISABLE = 7 ;
+static const uint8_t P9N2_C_SLAVE_CONFIG_REG_ERROR_MASK = 8 ;
+static const uint8_t P9N2_C_SLAVE_CONFIG_REG_ERROR_MASK_LEN = 6 ;
+
+static const uint8_t P9N2_EQ_SPATTN_IN0 = 0 ;
+static const uint8_t P9N2_EQ_SPATTN_IN1 = 1 ;
+static const uint8_t P9N2_EQ_SPATTN_IN2 = 2 ;
+static const uint8_t P9N2_EQ_SPATTN_IN3 = 3 ;
+static const uint8_t P9N2_EQ_SPATTN_IN4 = 4 ;
+static const uint8_t P9N2_EQ_SPATTN_IN5 = 5 ;
+static const uint8_t P9N2_EQ_SPATTN_IN6 = 6 ;
+static const uint8_t P9N2_EQ_SPATTN_IN7 = 7 ;
+static const uint8_t P9N2_EQ_SPATTN_IN8 = 8 ;
+static const uint8_t P9N2_EQ_SPATTN_IN9 = 9 ;
+
+static const uint8_t P9N2_EX_SPATTN_LT0_SPR_INSTR_STOP = 0 ;
+static const uint8_t P9N2_EX_SPATTN_LT0_ATTN_COMPLETE = 1 ;
+static const uint8_t P9N2_EX_SPATTN_LT0_CORE_CHECKSTOP_RECOVERY_HANDSHAKE = 2 ;
+static const uint8_t P9N2_EX_SPATTN_LT0_CORE_CODE_TO_SP = 3 ;
+static const uint8_t P9N2_EX_SPATTN_LT1_SPR_INSTR_STOP = 4 ;
+static const uint8_t P9N2_EX_SPATTN_LT1_ATTN_COMPLETE = 5 ;
+static const uint8_t P9N2_EX_SPATTN_LT1_CORE_CHECKSTOP_RECOVERY_HANDSHAKE = 6 ;
+static const uint8_t P9N2_EX_SPATTN_LT1_CORE_CODE_TO_SP = 7 ;
+static const uint8_t P9N2_EX_SPATTN_LT2_SPR_INSTR_STOP = 8 ;
+static const uint8_t P9N2_EX_SPATTN_LT2_ATTN_COMPLETE = 9 ;
+static const uint8_t P9N2_EX_SPATTN_LT2_CORE_CHECKSTOP_RECOVERY_HANDSHAKE = 10 ;
+static const uint8_t P9N2_EX_SPATTN_LT2_CORE_CODE_TO_SP = 11 ;
+static const uint8_t P9N2_EX_SPATTN_LT3_SPR_INSTR_STOP = 12 ;
+static const uint8_t P9N2_EX_SPATTN_LT3_ATTN_COMPLETE = 13 ;
+static const uint8_t P9N2_EX_SPATTN_LT3_CORE_CHECKSTOP_RECOVERY_HANDSHAKE = 14 ;
+static const uint8_t P9N2_EX_SPATTN_LT3_CORE_CODE_TO_SP = 15 ;
+static const uint8_t P9N2_EX_SPATTN_LT4_SPR_INSTR_STOP = 16 ;
+static const uint8_t P9N2_EX_SPATTN_LT4_ATTN_COMPLETE = 17 ;
+static const uint8_t P9N2_EX_SPATTN_LT4_CORE_CHECKSTOP_RECOVERY_HANDSHAKE = 18 ;
+static const uint8_t P9N2_EX_SPATTN_LT4_CORE_CODE_TO_SP = 19 ;
+static const uint8_t P9N2_EX_SPATTN_LT5_SPR_INSTR_STOP = 20 ;
+static const uint8_t P9N2_EX_SPATTN_LT5_ATTN_COMPLETE = 21 ;
+static const uint8_t P9N2_EX_SPATTN_LT5_CORE_CHECKSTOP_RECOVERY_HANDSHAKE = 22 ;
+static const uint8_t P9N2_EX_SPATTN_LT5_CORE_CODE_TO_SP = 23 ;
+static const uint8_t P9N2_EX_SPATTN_LT6_SPR_INSTR_STOP = 24 ;
+static const uint8_t P9N2_EX_SPATTN_LT6_ATTN_COMPLETE = 25 ;
+static const uint8_t P9N2_EX_SPATTN_LT6_CORE_CHECKSTOP_RECOVERY_HANDSHAKE = 26 ;
+static const uint8_t P9N2_EX_SPATTN_LT6_CORE_CODE_TO_SP = 27 ;
+static const uint8_t P9N2_EX_SPATTN_LT7_SPR_INSTR_STOP = 28 ;
+static const uint8_t P9N2_EX_SPATTN_LT7_ATTN_COMPLETE = 29 ;
+static const uint8_t P9N2_EX_SPATTN_LT7_CORE_CHECKSTOP_RECOVERY_HANDSHAKE = 30 ;
+static const uint8_t P9N2_EX_SPATTN_LT7_CORE_CODE_TO_SP = 31 ;
+
+static const uint8_t P9N2_EX_L2_SPATTN_LT0_SPR_INSTR_STOP = 0 ;
+static const uint8_t P9N2_EX_L2_SPATTN_LT0_ATTN_COMPLETE = 1 ;
+static const uint8_t P9N2_EX_L2_SPATTN_LT0_CORE_CHECKSTOP_RECOVERY_HANDSHAKE = 2 ;
+static const uint8_t P9N2_EX_L2_SPATTN_LT0_CORE_CODE_TO_SP = 3 ;
+static const uint8_t P9N2_EX_L2_SPATTN_LT1_SPR_INSTR_STOP = 4 ;
+static const uint8_t P9N2_EX_L2_SPATTN_LT1_ATTN_COMPLETE = 5 ;
+static const uint8_t P9N2_EX_L2_SPATTN_LT1_CORE_CHECKSTOP_RECOVERY_HANDSHAKE = 6 ;
+static const uint8_t P9N2_EX_L2_SPATTN_LT1_CORE_CODE_TO_SP = 7 ;
+static const uint8_t P9N2_EX_L2_SPATTN_LT2_SPR_INSTR_STOP = 8 ;
+static const uint8_t P9N2_EX_L2_SPATTN_LT2_ATTN_COMPLETE = 9 ;
+static const uint8_t P9N2_EX_L2_SPATTN_LT2_CORE_CHECKSTOP_RECOVERY_HANDSHAKE = 10 ;
+static const uint8_t P9N2_EX_L2_SPATTN_LT2_CORE_CODE_TO_SP = 11 ;
+static const uint8_t P9N2_EX_L2_SPATTN_LT3_SPR_INSTR_STOP = 12 ;
+static const uint8_t P9N2_EX_L2_SPATTN_LT3_ATTN_COMPLETE = 13 ;
+static const uint8_t P9N2_EX_L2_SPATTN_LT3_CORE_CHECKSTOP_RECOVERY_HANDSHAKE = 14 ;
+static const uint8_t P9N2_EX_L2_SPATTN_LT3_CORE_CODE_TO_SP = 15 ;
+static const uint8_t P9N2_EX_L2_SPATTN_LT4_SPR_INSTR_STOP = 16 ;
+static const uint8_t P9N2_EX_L2_SPATTN_LT4_ATTN_COMPLETE = 17 ;
+static const uint8_t P9N2_EX_L2_SPATTN_LT4_CORE_CHECKSTOP_RECOVERY_HANDSHAKE = 18 ;
+static const uint8_t P9N2_EX_L2_SPATTN_LT4_CORE_CODE_TO_SP = 19 ;
+static const uint8_t P9N2_EX_L2_SPATTN_LT5_SPR_INSTR_STOP = 20 ;
+static const uint8_t P9N2_EX_L2_SPATTN_LT5_ATTN_COMPLETE = 21 ;
+static const uint8_t P9N2_EX_L2_SPATTN_LT5_CORE_CHECKSTOP_RECOVERY_HANDSHAKE = 22 ;
+static const uint8_t P9N2_EX_L2_SPATTN_LT5_CORE_CODE_TO_SP = 23 ;
+static const uint8_t P9N2_EX_L2_SPATTN_LT6_SPR_INSTR_STOP = 24 ;
+static const uint8_t P9N2_EX_L2_SPATTN_LT6_ATTN_COMPLETE = 25 ;
+static const uint8_t P9N2_EX_L2_SPATTN_LT6_CORE_CHECKSTOP_RECOVERY_HANDSHAKE = 26 ;
+static const uint8_t P9N2_EX_L2_SPATTN_LT6_CORE_CODE_TO_SP = 27 ;
+static const uint8_t P9N2_EX_L2_SPATTN_LT7_SPR_INSTR_STOP = 28 ;
+static const uint8_t P9N2_EX_L2_SPATTN_LT7_ATTN_COMPLETE = 29 ;
+static const uint8_t P9N2_EX_L2_SPATTN_LT7_CORE_CHECKSTOP_RECOVERY_HANDSHAKE = 30 ;
+static const uint8_t P9N2_EX_L2_SPATTN_LT7_CORE_CODE_TO_SP = 31 ;
+
+static const uint8_t P9N2_C_SPATTN_LT0_SPR_INSTR_STOP = 0 ;
+static const uint8_t P9N2_C_SPATTN_LT0_ATTN_COMPLETE = 1 ;
+static const uint8_t P9N2_C_SPATTN_LT0_CORE_CHECKSTOP_RECOVERY_HANDSHAKE = 2 ;
+static const uint8_t P9N2_C_SPATTN_LT0_CORE_CODE_TO_SP = 3 ;
+static const uint8_t P9N2_C_SPATTN_LT1_SPR_INSTR_STOP = 4 ;
+static const uint8_t P9N2_C_SPATTN_LT1_ATTN_COMPLETE = 5 ;
+static const uint8_t P9N2_C_SPATTN_LT1_CORE_CHECKSTOP_RECOVERY_HANDSHAKE = 6 ;
+static const uint8_t P9N2_C_SPATTN_LT1_CORE_CODE_TO_SP = 7 ;
+static const uint8_t P9N2_C_SPATTN_LT2_SPR_INSTR_STOP = 8 ;
+static const uint8_t P9N2_C_SPATTN_LT2_ATTN_COMPLETE = 9 ;
+static const uint8_t P9N2_C_SPATTN_LT2_CORE_CHECKSTOP_RECOVERY_HANDSHAKE = 10 ;
+static const uint8_t P9N2_C_SPATTN_LT2_CORE_CODE_TO_SP = 11 ;
+static const uint8_t P9N2_C_SPATTN_LT3_SPR_INSTR_STOP = 12 ;
+static const uint8_t P9N2_C_SPATTN_LT3_ATTN_COMPLETE = 13 ;
+static const uint8_t P9N2_C_SPATTN_LT3_CORE_CHECKSTOP_RECOVERY_HANDSHAKE = 14 ;
+static const uint8_t P9N2_C_SPATTN_LT3_CORE_CODE_TO_SP = 15 ;
+static const uint8_t P9N2_C_SPATTN_LT4_SPR_INSTR_STOP = 16 ;
+static const uint8_t P9N2_C_SPATTN_LT4_ATTN_COMPLETE = 17 ;
+static const uint8_t P9N2_C_SPATTN_LT4_CORE_CHECKSTOP_RECOVERY_HANDSHAKE = 18 ;
+static const uint8_t P9N2_C_SPATTN_LT4_CORE_CODE_TO_SP = 19 ;
+static const uint8_t P9N2_C_SPATTN_LT5_SPR_INSTR_STOP = 20 ;
+static const uint8_t P9N2_C_SPATTN_LT5_ATTN_COMPLETE = 21 ;
+static const uint8_t P9N2_C_SPATTN_LT5_CORE_CHECKSTOP_RECOVERY_HANDSHAKE = 22 ;
+static const uint8_t P9N2_C_SPATTN_LT5_CORE_CODE_TO_SP = 23 ;
+static const uint8_t P9N2_C_SPATTN_LT6_SPR_INSTR_STOP = 24 ;
+static const uint8_t P9N2_C_SPATTN_LT6_ATTN_COMPLETE = 25 ;
+static const uint8_t P9N2_C_SPATTN_LT6_CORE_CHECKSTOP_RECOVERY_HANDSHAKE = 26 ;
+static const uint8_t P9N2_C_SPATTN_LT6_CORE_CODE_TO_SP = 27 ;
+static const uint8_t P9N2_C_SPATTN_LT7_SPR_INSTR_STOP = 28 ;
+static const uint8_t P9N2_C_SPATTN_LT7_ATTN_COMPLETE = 29 ;
+static const uint8_t P9N2_C_SPATTN_LT7_CORE_CHECKSTOP_RECOVERY_HANDSHAKE = 30 ;
+static const uint8_t P9N2_C_SPATTN_LT7_CORE_CODE_TO_SP = 31 ;
+
+static const uint8_t P9N2_EX_L2_SPATTN_MASK_LT0_SPATTN_MASK = 0 ;
+static const uint8_t P9N2_EX_L2_SPATTN_MASK_LT0_SPATTN_MASK_LEN = 4 ;
+static const uint8_t P9N2_EX_L2_SPATTN_MASK_LT1_SPATTN_MASK = 4 ;
+static const uint8_t P9N2_EX_L2_SPATTN_MASK_LT1_SPATTN_MASK_LEN = 4 ;
+static const uint8_t P9N2_EX_L2_SPATTN_MASK_LT2_SPATTN_MASK = 8 ;
+static const uint8_t P9N2_EX_L2_SPATTN_MASK_LT2_SPATTN_MASK_LEN = 4 ;
+static const uint8_t P9N2_EX_L2_SPATTN_MASK_LT3_SPATTN_MASK = 12 ;
+static const uint8_t P9N2_EX_L2_SPATTN_MASK_LT3_SPATTN_MASK_LEN = 4 ;
+static const uint8_t P9N2_EX_L2_SPATTN_MASK_LT4_SPATTN_MASK = 16 ;
+static const uint8_t P9N2_EX_L2_SPATTN_MASK_LT4_SPATTN_MASK_LEN = 4 ;
+static const uint8_t P9N2_EX_L2_SPATTN_MASK_LT5_SPATTN_MASK = 20 ;
+static const uint8_t P9N2_EX_L2_SPATTN_MASK_LT5_SPATTN_MASK_LEN = 4 ;
+static const uint8_t P9N2_EX_L2_SPATTN_MASK_LT6_SPATTN_MASK = 24 ;
+static const uint8_t P9N2_EX_L2_SPATTN_MASK_LT6_SPATTN_MASK_LEN = 4 ;
+static const uint8_t P9N2_EX_L2_SPATTN_MASK_LT7_SPATTN_MASK = 28 ;
+static const uint8_t P9N2_EX_L2_SPATTN_MASK_LT7_SPATTN_MASK_LEN = 4 ;
+
+static const uint8_t P9N2_C_SPATTN_MASK_LT0_SPATTN_MASK = 0 ;
+static const uint8_t P9N2_C_SPATTN_MASK_LT0_SPATTN_MASK_LEN = 4 ;
+static const uint8_t P9N2_C_SPATTN_MASK_LT1_SPATTN_MASK = 4 ;
+static const uint8_t P9N2_C_SPATTN_MASK_LT1_SPATTN_MASK_LEN = 4 ;
+static const uint8_t P9N2_C_SPATTN_MASK_LT2_SPATTN_MASK = 8 ;
+static const uint8_t P9N2_C_SPATTN_MASK_LT2_SPATTN_MASK_LEN = 4 ;
+static const uint8_t P9N2_C_SPATTN_MASK_LT3_SPATTN_MASK = 12 ;
+static const uint8_t P9N2_C_SPATTN_MASK_LT3_SPATTN_MASK_LEN = 4 ;
+static const uint8_t P9N2_C_SPATTN_MASK_LT4_SPATTN_MASK = 16 ;
+static const uint8_t P9N2_C_SPATTN_MASK_LT4_SPATTN_MASK_LEN = 4 ;
+static const uint8_t P9N2_C_SPATTN_MASK_LT5_SPATTN_MASK = 20 ;
+static const uint8_t P9N2_C_SPATTN_MASK_LT5_SPATTN_MASK_LEN = 4 ;
+static const uint8_t P9N2_C_SPATTN_MASK_LT6_SPATTN_MASK = 24 ;
+static const uint8_t P9N2_C_SPATTN_MASK_LT6_SPATTN_MASK_LEN = 4 ;
+static const uint8_t P9N2_C_SPATTN_MASK_LT7_SPATTN_MASK = 28 ;
+static const uint8_t P9N2_C_SPATTN_MASK_LT7_SPATTN_MASK_LEN = 4 ;
+
+static const uint8_t P9N2_EQ_SPA_MASK_IN = 0 ;
+static const uint8_t P9N2_EQ_SPA_MASK_IN_LEN = 10 ;
+
+static const uint8_t P9N2_EX_SPA_MASK_IN = 0 ;
+static const uint8_t P9N2_EX_SPA_MASK_IN_LEN = 10 ;
+
+static const uint8_t P9N2_C_SPA_MASK_IN = 0 ;
+static const uint8_t P9N2_C_SPA_MASK_IN_LEN = 10 ;
+
+static const uint8_t P9N2_EX_SPR_COMMON_HOLD_OUT_ATTNREG_PAR_HOLD_OUT = 0 ;
+static const uint8_t P9N2_EX_SPR_COMMON_HOLD_OUT_CTRL_PAR_HOLD_OUT = 1 ;
+static const uint8_t P9N2_EX_SPR_COMMON_HOLD_OUT_HMEER_PAR_HOLD_OUT = 2 ;
+static const uint8_t P9N2_EX_SPR_COMMON_HOLD_OUT_L2_CHECKSTOP_HOLD_OUT = 3 ;
+static const uint8_t P9N2_EX_SPR_COMMON_HOLD_OUT_MODEREG_PAR_HOLD_OUT = 4 ;
+static const uint8_t P9N2_EX_SPR_COMMON_HOLD_OUT_CORE_POWSAV_STATE_HOLD_OUT = 5 ;
+static const uint8_t P9N2_EX_SPR_COMMON_HOLD_OUT_CORE_RECVY_THD_CHANGE_HOLD_OUT = 6 ;
+static const uint8_t P9N2_EX_SPR_COMMON_HOLD_OUT_FENCE_EN_PM_EXIT_HOLD_OUT = 7 ;
+static const uint8_t P9N2_EX_SPR_COMMON_HOLD_OUT_FENCE_EN_THD_SM_NONIDLE_HOLD_OUT = 8 ;
+static const uint8_t P9N2_EX_SPR_COMMON_HOLD_OUT_L2_MCHK_PB_ADDR_HOLD_OUT = 9 ;
+static const uint8_t P9N2_EX_SPR_COMMON_HOLD_OUT_L2_MCHK_PB_ALINK_HOLD_OUT = 10 ;
+static const uint8_t P9N2_EX_SPR_COMMON_HOLD_OUT_THD_POWSAV_STATE_HOLD_OUT = 11 ;
+static const uint8_t P9N2_EX_SPR_COMMON_HOLD_OUT_VT0_LPCR_PAR_HOLD_OUT = 12 ;
+static const uint8_t P9N2_EX_SPR_COMMON_HOLD_OUT_VT1_LPCR_PAR_HOLD_OUT = 13 ;
+static const uint8_t P9N2_EX_SPR_COMMON_HOLD_OUT_VT2_LPCR_PAR_HOLD_OUT = 14 ;
+static const uint8_t P9N2_EX_SPR_COMMON_HOLD_OUT_VT3_LPCR_PAR_HOLD_OUT = 15 ;
+static const uint8_t P9N2_EX_SPR_COMMON_HOLD_OUT_VT0_PSSCR_PAR_HOLD_OUT = 16 ;
+static const uint8_t P9N2_EX_SPR_COMMON_HOLD_OUT_VT1_PSSCR_PAR_HOLD_OUT = 17 ;
+static const uint8_t P9N2_EX_SPR_COMMON_HOLD_OUT_VT2_PSSCR_PAR_HOLD_OUT = 18 ;
+static const uint8_t P9N2_EX_SPR_COMMON_HOLD_OUT_VT3_PSSCR_PAR_HOLD_OUT = 19 ;
+static const uint8_t P9N2_EX_SPR_COMMON_HOLD_OUT_VT0_SMFCTRL_PAR_HOLD_OUT = 20 ;
+static const uint8_t P9N2_EX_SPR_COMMON_HOLD_OUT_VT1_SMFCTRL_PAR_HOLD_OUT = 21 ;
+static const uint8_t P9N2_EX_SPR_COMMON_HOLD_OUT_VT2_SMFCTRL_PAR_HOLD_OUT = 22 ;
+static const uint8_t P9N2_EX_SPR_COMMON_HOLD_OUT_VT3_SMFCTRL_PAR_HOLD_OUT = 23 ;
+
+static const uint8_t P9N2_C_SPR_COMMON_HOLD_OUT_ATTNREG_PAR_HOLD_OUT = 0 ;
+static const uint8_t P9N2_C_SPR_COMMON_HOLD_OUT_CTRL_PAR_HOLD_OUT = 1 ;
+static const uint8_t P9N2_C_SPR_COMMON_HOLD_OUT_HMEER_PAR_HOLD_OUT = 2 ;
+static const uint8_t P9N2_C_SPR_COMMON_HOLD_OUT_L2_CHECKSTOP_HOLD_OUT = 3 ;
+static const uint8_t P9N2_C_SPR_COMMON_HOLD_OUT_MODEREG_PAR_HOLD_OUT = 4 ;
+static const uint8_t P9N2_C_SPR_COMMON_HOLD_OUT_CORE_POWSAV_STATE_HOLD_OUT = 5 ;
+static const uint8_t P9N2_C_SPR_COMMON_HOLD_OUT_CORE_RECVY_THD_CHANGE_HOLD_OUT = 6 ;
+static const uint8_t P9N2_C_SPR_COMMON_HOLD_OUT_FENCE_EN_PM_EXIT_HOLD_OUT = 7 ;
+static const uint8_t P9N2_C_SPR_COMMON_HOLD_OUT_FENCE_EN_THD_SM_NONIDLE_HOLD_OUT = 8 ;
+static const uint8_t P9N2_C_SPR_COMMON_HOLD_OUT_L2_MCHK_PB_ADDR_HOLD_OUT = 9 ;
+static const uint8_t P9N2_C_SPR_COMMON_HOLD_OUT_L2_MCHK_PB_ALINK_HOLD_OUT = 10 ;
+static const uint8_t P9N2_C_SPR_COMMON_HOLD_OUT_THD_POWSAV_STATE_HOLD_OUT = 11 ;
+static const uint8_t P9N2_C_SPR_COMMON_HOLD_OUT_VT0_LPCR_PAR_HOLD_OUT = 12 ;
+static const uint8_t P9N2_C_SPR_COMMON_HOLD_OUT_VT1_LPCR_PAR_HOLD_OUT = 13 ;
+static const uint8_t P9N2_C_SPR_COMMON_HOLD_OUT_VT2_LPCR_PAR_HOLD_OUT = 14 ;
+static const uint8_t P9N2_C_SPR_COMMON_HOLD_OUT_VT3_LPCR_PAR_HOLD_OUT = 15 ;
+static const uint8_t P9N2_C_SPR_COMMON_HOLD_OUT_VT0_PSSCR_PAR_HOLD_OUT = 16 ;
+static const uint8_t P9N2_C_SPR_COMMON_HOLD_OUT_VT1_PSSCR_PAR_HOLD_OUT = 17 ;
+static const uint8_t P9N2_C_SPR_COMMON_HOLD_OUT_VT2_PSSCR_PAR_HOLD_OUT = 18 ;
+static const uint8_t P9N2_C_SPR_COMMON_HOLD_OUT_VT3_PSSCR_PAR_HOLD_OUT = 19 ;
+static const uint8_t P9N2_C_SPR_COMMON_HOLD_OUT_VT0_SMFCTRL_PAR_HOLD_OUT = 20 ;
+static const uint8_t P9N2_C_SPR_COMMON_HOLD_OUT_VT1_SMFCTRL_PAR_HOLD_OUT = 21 ;
+static const uint8_t P9N2_C_SPR_COMMON_HOLD_OUT_VT2_SMFCTRL_PAR_HOLD_OUT = 22 ;
+static const uint8_t P9N2_C_SPR_COMMON_HOLD_OUT_VT3_SMFCTRL_PAR_HOLD_OUT = 23 ;
+
+static const uint8_t P9N2_EX_L2_SPR_CORE_HOLD_OUT_IMA_HOLD_OUT = 0 ;
+static const uint8_t P9N2_EX_L2_SPR_CORE_HOLD_OUT_ITRACE_HOLD_OUT = 1 ;
+static const uint8_t P9N2_EX_L2_SPR_CORE_HOLD_OUT_PTID_SWAP_SM_HOLD_OUT = 2 ;
+static const uint8_t P9N2_EX_L2_SPR_CORE_HOLD_OUT_VS_ERR_HOLD_OUT = 3 ;
+static const uint8_t P9N2_EX_L2_SPR_CORE_HOLD_OUT_VS_ERR_HOLD_OUT_LEN = 6 ;
+static const uint8_t P9N2_EX_L2_SPR_CORE_HOLD_OUT_VT0_LPCR_ONL_PAR_HOLD_OUT = 9 ;
+static const uint8_t P9N2_EX_L2_SPR_CORE_HOLD_OUT_VT1_LPCR_ONL_PAR_HOLD_OUT = 10 ;
+static const uint8_t P9N2_EX_L2_SPR_CORE_HOLD_OUT_VT2_LPCR_ONL_PAR_HOLD_OUT = 11 ;
+static const uint8_t P9N2_EX_L2_SPR_CORE_HOLD_OUT_VT3_LPCR_ONL_PAR_HOLD_OUT = 12 ;
+
+static const uint8_t P9N2_C_SPR_CORE_HOLD_OUT_IMA_HOLD_OUT = 0 ;
+static const uint8_t P9N2_C_SPR_CORE_HOLD_OUT_ITRACE_HOLD_OUT = 1 ;
+static const uint8_t P9N2_C_SPR_CORE_HOLD_OUT_PTID_SWAP_SM_HOLD_OUT = 2 ;
+static const uint8_t P9N2_C_SPR_CORE_HOLD_OUT_VS_ERR_HOLD_OUT = 3 ;
+static const uint8_t P9N2_C_SPR_CORE_HOLD_OUT_VS_ERR_HOLD_OUT_LEN = 6 ;
+static const uint8_t P9N2_C_SPR_CORE_HOLD_OUT_VT0_LPCR_ONL_PAR_HOLD_OUT = 9 ;
+static const uint8_t P9N2_C_SPR_CORE_HOLD_OUT_VT1_LPCR_ONL_PAR_HOLD_OUT = 10 ;
+static const uint8_t P9N2_C_SPR_CORE_HOLD_OUT_VT2_LPCR_ONL_PAR_HOLD_OUT = 11 ;
+static const uint8_t P9N2_C_SPR_CORE_HOLD_OUT_VT3_LPCR_ONL_PAR_HOLD_OUT = 12 ;
+
+static const uint8_t P9N2_EX_L2_SPR_MODE_MODEREG_TFAC_ERR_INJ = 10 ;
+static const uint8_t P9N2_EX_L2_SPR_MODE_MODEREG_TFAC_ERR_INJ_LEN = 6 ;
+static const uint8_t P9N2_EX_L2_SPR_MODE_MODEREG_SPRC_LT0_SEL = 20 ;
+static const uint8_t P9N2_EX_L2_SPR_MODE_MODEREG_SPRC_LT1_SEL = 21 ;
+static const uint8_t P9N2_EX_L2_SPR_MODE_MODEREG_SPRC_LT2_SEL = 22 ;
+static const uint8_t P9N2_EX_L2_SPR_MODE_MODEREG_SPRC_LT3_SEL = 23 ;
+static const uint8_t P9N2_EX_L2_SPR_MODE_MODEREG_SPRC_LT4_SEL = 24 ;
+static const uint8_t P9N2_EX_L2_SPR_MODE_MODEREG_SPRC_LT5_SEL = 25 ;
+static const uint8_t P9N2_EX_L2_SPR_MODE_MODEREG_SPRC_LT6_SEL = 26 ;
+static const uint8_t P9N2_EX_L2_SPR_MODE_MODEREG_SPRC_LT7_SEL = 27 ;
+static const uint8_t P9N2_EX_L2_SPR_MODE_MODEREG_SPRC_CY_DISABLE = 28 ;
+
+static const uint8_t P9N2_C_SPR_MODE_MODEREG_TFAC_ERR_INJ = 10 ;
+static const uint8_t P9N2_C_SPR_MODE_MODEREG_TFAC_ERR_INJ_LEN = 6 ;
+static const uint8_t P9N2_C_SPR_MODE_MODEREG_SPRC_LT0_SEL = 20 ;
+static const uint8_t P9N2_C_SPR_MODE_MODEREG_SPRC_LT1_SEL = 21 ;
+static const uint8_t P9N2_C_SPR_MODE_MODEREG_SPRC_LT2_SEL = 22 ;
+static const uint8_t P9N2_C_SPR_MODE_MODEREG_SPRC_LT3_SEL = 23 ;
+static const uint8_t P9N2_C_SPR_MODE_MODEREG_SPRC_LT4_SEL = 24 ;
+static const uint8_t P9N2_C_SPR_MODE_MODEREG_SPRC_LT5_SEL = 25 ;
+static const uint8_t P9N2_C_SPR_MODE_MODEREG_SPRC_LT6_SEL = 26 ;
+static const uint8_t P9N2_C_SPR_MODE_MODEREG_SPRC_LT7_SEL = 27 ;
+static const uint8_t P9N2_C_SPR_MODE_MODEREG_SPRC_CY_DISABLE = 28 ;
+
+static const uint8_t P9N2_EX_SPURR_FREQ_DETECT_CYC_CNT_CYCLE_COUNT = 0 ;
+static const uint8_t P9N2_EX_SPURR_FREQ_DETECT_CYC_CNT_CYCLE_COUNT_LEN = 8 ;
+
+static const uint8_t P9N2_C_SPURR_FREQ_DETECT_CYC_CNT_CYCLE_COUNT = 0 ;
+static const uint8_t P9N2_C_SPURR_FREQ_DETECT_CYC_CNT_CYCLE_COUNT_LEN = 8 ;
+
+static const uint8_t P9N2_EX_L2_SPURR_FREQ_REF_FREQUENCY_REFERENCE = 0 ;
+static const uint8_t P9N2_EX_L2_SPURR_FREQ_REF_FREQUENCY_REFERENCE_LEN = 8 ;
+
+static const uint8_t P9N2_C_SPURR_FREQ_REF_FREQUENCY_REFERENCE = 0 ;
+static const uint8_t P9N2_C_SPURR_FREQ_REF_FREQUENCY_REFERENCE_LEN = 8 ;
+
+static const uint8_t P9N2_EX_L2_SPURR_FREQ_SCALE_OVERRIDE_EN = 0 ;
+static const uint8_t P9N2_EX_L2_SPURR_FREQ_SCALE_FACTOR = 1 ;
+static const uint8_t P9N2_EX_L2_SPURR_FREQ_SCALE_FACTOR_LEN = 7 ;
+
+static const uint8_t P9N2_C_SPURR_FREQ_SCALE_OVERRIDE_EN = 0 ;
+static const uint8_t P9N2_C_SPURR_FREQ_SCALE_FACTOR = 1 ;
+static const uint8_t P9N2_C_SPURR_FREQ_SCALE_FACTOR_LEN = 7 ;
+
+static const uint8_t P9N2_EX_SRC_MASK_SRC_MASK_TBD = 0 ;
+static const uint8_t P9N2_EX_SRC_MASK_SRC_MASK_TBD_LEN = 64 ;
+
+static const uint8_t P9N2_C_SRC_MASK_SRC_MASK_TBD = 0 ;
+static const uint8_t P9N2_C_SRC_MASK_SRC_MASK_TBD_LEN = 64 ;
+
+static const uint8_t P9N2_EQ_SUM_MASK_REG_SMASK_IN0 = 0 ;
+static const uint8_t P9N2_EQ_SUM_MASK_REG_SMASK_IN1 = 1 ;
+static const uint8_t P9N2_EQ_SUM_MASK_REG_SMASK_IN2 = 2 ;
+static const uint8_t P9N2_EQ_SUM_MASK_REG_SMASK_IN3 = 3 ;
+static const uint8_t P9N2_EQ_SUM_MASK_REG_SMASK_IN4 = 4 ;
+
+static const uint8_t P9N2_EX_SUM_MASK_REG_SMASK_IN0 = 0 ;
+static const uint8_t P9N2_EX_SUM_MASK_REG_SMASK_IN1 = 1 ;
+static const uint8_t P9N2_EX_SUM_MASK_REG_SMASK_IN2 = 2 ;
+static const uint8_t P9N2_EX_SUM_MASK_REG_SMASK_IN3 = 3 ;
+static const uint8_t P9N2_EX_SUM_MASK_REG_SMASK_IN4 = 4 ;
+
+static const uint8_t P9N2_C_SUM_MASK_REG_SMASK_IN0 = 0 ;
+static const uint8_t P9N2_C_SUM_MASK_REG_SMASK_IN1 = 1 ;
+static const uint8_t P9N2_C_SUM_MASK_REG_SMASK_IN2 = 2 ;
+static const uint8_t P9N2_C_SUM_MASK_REG_SMASK_IN3 = 3 ;
+static const uint8_t P9N2_C_SUM_MASK_REG_SMASK_IN4 = 4 ;
+
+static const uint8_t P9N2_EQ_SYNC_CONFIG_PULSE_DELAY = 0 ;
+static const uint8_t P9N2_EQ_SYNC_CONFIG_PULSE_DELAY_LEN = 4 ;
+static const uint8_t P9N2_EQ_SYNC_CONFIG_LISTEN_TO_PULSE_DIS = 4 ;
+static const uint8_t P9N2_EQ_SYNC_CONFIG_PULSE_INPUT_SEL = 5 ;
+static const uint8_t P9N2_EQ_SYNC_CONFIG_USE_FOR_SCAN = 6 ;
+static const uint8_t P9N2_EQ_SYNC_CONFIG_CLEAR_CHIPLET_IS_ALIGNED = 7 ;
+static const uint8_t P9N2_EQ_SYNC_CONFIG_UNIT_REGION_CLKCMD_ENABLE = 8 ;
+static const uint8_t P9N2_EQ_SYNC_CONFIG_DISABLE_PCB_ITR = 9 ;
+static const uint8_t P9N2_EQ_SYNC_CONFIG_ENABLE_VITL_ALIGN_CHECK = 10 ;
+static const uint8_t P9N2_EQ_SYNC_CONFIG_PULSE_OUT_DIS = 11 ;
+static const uint8_t P9N2_EQ_SYNC_CONFIG_CHKSW_DD1_MODE = 12 ;
+static const uint8_t P9N2_EQ_SYNC_CONFIG_CHKSW_DD1_E1 = 13 ;
+static const uint8_t P9N2_EQ_SYNC_CONFIG_CHKSW_DD1_E2 = 14 ;
+static const uint8_t P9N2_EQ_SYNC_CONFIG_CHKSW_DD1_E3 = 15 ;
+static const uint8_t P9N2_EQ_SYNC_CONFIG_PHASE_COUNTER_ON_CLKCHANGE = 16 ;
+static const uint8_t P9N2_EQ_SYNC_CONFIG_PHASE_COUNTER_ON_CLKCHANGE_LEN = 8 ;
+
+static const uint8_t P9N2_EX_SYNC_CONFIG_PULSE_DELAY = 0 ;
+static const uint8_t P9N2_EX_SYNC_CONFIG_PULSE_DELAY_LEN = 4 ;
+static const uint8_t P9N2_EX_SYNC_CONFIG_LISTEN_TO_PULSE_DIS = 4 ;
+static const uint8_t P9N2_EX_SYNC_CONFIG_PULSE_INPUT_SEL = 5 ;
+static const uint8_t P9N2_EX_SYNC_CONFIG_USE_FOR_SCAN = 6 ;
+static const uint8_t P9N2_EX_SYNC_CONFIG_CLEAR_CHIPLET_IS_ALIGNED = 7 ;
+static const uint8_t P9N2_EX_SYNC_CONFIG_UNIT_REGION_CLKCMD_ENABLE = 8 ;
+static const uint8_t P9N2_EX_SYNC_CONFIG_DISABLE_PCB_ITR = 9 ;
+static const uint8_t P9N2_EX_SYNC_CONFIG_ENABLE_VITL_ALIGN_CHECK = 10 ;
+static const uint8_t P9N2_EX_SYNC_CONFIG_PULSE_OUT_DIS = 11 ;
+static const uint8_t P9N2_EX_SYNC_CONFIG_CHKSW_DD1_MODE = 12 ;
+static const uint8_t P9N2_EX_SYNC_CONFIG_CHKSW_DD1_E1 = 13 ;
+static const uint8_t P9N2_EX_SYNC_CONFIG_CHKSW_DD1_E2 = 14 ;
+static const uint8_t P9N2_EX_SYNC_CONFIG_CHKSW_DD1_E3 = 15 ;
+static const uint8_t P9N2_EX_SYNC_CONFIG_PHASE_COUNTER_ON_CLKCHANGE = 16 ;
+static const uint8_t P9N2_EX_SYNC_CONFIG_PHASE_COUNTER_ON_CLKCHANGE_LEN = 8 ;
+
+static const uint8_t P9N2_C_SYNC_CONFIG_PULSE_DELAY = 0 ;
+static const uint8_t P9N2_C_SYNC_CONFIG_PULSE_DELAY_LEN = 4 ;
+static const uint8_t P9N2_C_SYNC_CONFIG_LISTEN_TO_PULSE_DIS = 4 ;
+static const uint8_t P9N2_C_SYNC_CONFIG_PULSE_INPUT_SEL = 5 ;
+static const uint8_t P9N2_C_SYNC_CONFIG_USE_FOR_SCAN = 6 ;
+static const uint8_t P9N2_C_SYNC_CONFIG_CLEAR_CHIPLET_IS_ALIGNED = 7 ;
+static const uint8_t P9N2_C_SYNC_CONFIG_UNIT_REGION_CLKCMD_ENABLE = 8 ;
+static const uint8_t P9N2_C_SYNC_CONFIG_DISABLE_PCB_ITR = 9 ;
+static const uint8_t P9N2_C_SYNC_CONFIG_ENABLE_VITL_ALIGN_CHECK = 10 ;
+static const uint8_t P9N2_C_SYNC_CONFIG_PULSE_OUT_DIS = 11 ;
+static const uint8_t P9N2_C_SYNC_CONFIG_CHKSW_DD1_MODE = 12 ;
+static const uint8_t P9N2_C_SYNC_CONFIG_CHKSW_DD1_E1 = 13 ;
+static const uint8_t P9N2_C_SYNC_CONFIG_CHKSW_DD1_E2 = 14 ;
+static const uint8_t P9N2_C_SYNC_CONFIG_CHKSW_DD1_E3 = 15 ;
+static const uint8_t P9N2_C_SYNC_CONFIG_PHASE_COUNTER_ON_CLKCHANGE = 16 ;
+static const uint8_t P9N2_C_SYNC_CONFIG_PHASE_COUNTER_ON_CLKCHANGE_LEN = 8 ;
+
+static const uint8_t P9N2_EX_L2_T0_PMU_SCOM_IDLE_DELAY = 0 ;
+static const uint8_t P9N2_EX_L2_T0_PMU_SCOM_IDLE_DELAY_LEN = 9 ;
+static const uint8_t P9N2_EX_L2_T0_PMU_SCOM_COMPLETION_DELAY = 9 ;
+static const uint8_t P9N2_EX_L2_T0_PMU_SCOM_COMPLETION_DELAY_LEN = 9 ;
+static const uint8_t P9N2_EX_L2_T0_PMU_SCOM_SAMPLE_OVERRIDE = 18 ;
+static const uint8_t P9N2_EX_L2_T0_PMU_SCOM_SPARE_CTRL = 19 ;
+static const uint8_t P9N2_EX_L2_T0_PMU_SCOM_SPARE_CTRL_LEN = 5 ;
+
+static const uint8_t P9N2_C_T0_PMU_SCOM_IDLE_DELAY = 0 ;
+static const uint8_t P9N2_C_T0_PMU_SCOM_IDLE_DELAY_LEN = 9 ;
+static const uint8_t P9N2_C_T0_PMU_SCOM_COMPLETION_DELAY = 9 ;
+static const uint8_t P9N2_C_T0_PMU_SCOM_COMPLETION_DELAY_LEN = 9 ;
+static const uint8_t P9N2_C_T0_PMU_SCOM_SAMPLE_OVERRIDE = 18 ;
+static const uint8_t P9N2_C_T0_PMU_SCOM_SPARE_CTRL = 19 ;
+static const uint8_t P9N2_C_T0_PMU_SCOM_SPARE_CTRL_LEN = 5 ;
+
+static const uint8_t P9N2_EX_L2_T1_PMU_SCOM_IDLE_DELAY = 0 ;
+static const uint8_t P9N2_EX_L2_T1_PMU_SCOM_IDLE_DELAY_LEN = 9 ;
+static const uint8_t P9N2_EX_L2_T1_PMU_SCOM_COMPLETION_DELAY = 9 ;
+static const uint8_t P9N2_EX_L2_T1_PMU_SCOM_COMPLETION_DELAY_LEN = 9 ;
+static const uint8_t P9N2_EX_L2_T1_PMU_SCOM_SAMPLE_OVERRIDE = 18 ;
+static const uint8_t P9N2_EX_L2_T1_PMU_SCOM_SPARE_CTRL = 19 ;
+static const uint8_t P9N2_EX_L2_T1_PMU_SCOM_SPARE_CTRL_LEN = 5 ;
+
+static const uint8_t P9N2_C_T1_PMU_SCOM_IDLE_DELAY = 0 ;
+static const uint8_t P9N2_C_T1_PMU_SCOM_IDLE_DELAY_LEN = 9 ;
+static const uint8_t P9N2_C_T1_PMU_SCOM_COMPLETION_DELAY = 9 ;
+static const uint8_t P9N2_C_T1_PMU_SCOM_COMPLETION_DELAY_LEN = 9 ;
+static const uint8_t P9N2_C_T1_PMU_SCOM_SAMPLE_OVERRIDE = 18 ;
+static const uint8_t P9N2_C_T1_PMU_SCOM_SPARE_CTRL = 19 ;
+static const uint8_t P9N2_C_T1_PMU_SCOM_SPARE_CTRL_LEN = 5 ;
+
+static const uint8_t P9N2_EX_L2_T2_PMU_SCOM_IDLE_DELAY = 0 ;
+static const uint8_t P9N2_EX_L2_T2_PMU_SCOM_IDLE_DELAY_LEN = 9 ;
+static const uint8_t P9N2_EX_L2_T2_PMU_SCOM_COMPLETION_DELAY = 9 ;
+static const uint8_t P9N2_EX_L2_T2_PMU_SCOM_COMPLETION_DELAY_LEN = 9 ;
+static const uint8_t P9N2_EX_L2_T2_PMU_SCOM_SAMPLE_OVERRIDE = 18 ;
+static const uint8_t P9N2_EX_L2_T2_PMU_SCOM_SPARE_CTRL = 19 ;
+static const uint8_t P9N2_EX_L2_T2_PMU_SCOM_SPARE_CTRL_LEN = 5 ;
+
+static const uint8_t P9N2_C_T2_PMU_SCOM_IDLE_DELAY = 0 ;
+static const uint8_t P9N2_C_T2_PMU_SCOM_IDLE_DELAY_LEN = 9 ;
+static const uint8_t P9N2_C_T2_PMU_SCOM_COMPLETION_DELAY = 9 ;
+static const uint8_t P9N2_C_T2_PMU_SCOM_COMPLETION_DELAY_LEN = 9 ;
+static const uint8_t P9N2_C_T2_PMU_SCOM_SAMPLE_OVERRIDE = 18 ;
+static const uint8_t P9N2_C_T2_PMU_SCOM_SPARE_CTRL = 19 ;
+static const uint8_t P9N2_C_T2_PMU_SCOM_SPARE_CTRL_LEN = 5 ;
+
+static const uint8_t P9N2_EX_L2_T3_PMU_SCOM_IDLE_DELAY = 0 ;
+static const uint8_t P9N2_EX_L2_T3_PMU_SCOM_IDLE_DELAY_LEN = 9 ;
+static const uint8_t P9N2_EX_L2_T3_PMU_SCOM_COMPLETION_DELAY = 9 ;
+static const uint8_t P9N2_EX_L2_T3_PMU_SCOM_COMPLETION_DELAY_LEN = 9 ;
+static const uint8_t P9N2_EX_L2_T3_PMU_SCOM_SAMPLE_OVERRIDE = 18 ;
+static const uint8_t P9N2_EX_L2_T3_PMU_SCOM_SPARE_CTRL = 19 ;
+static const uint8_t P9N2_EX_L2_T3_PMU_SCOM_SPARE_CTRL_LEN = 5 ;
+
+static const uint8_t P9N2_C_T3_PMU_SCOM_IDLE_DELAY = 0 ;
+static const uint8_t P9N2_C_T3_PMU_SCOM_IDLE_DELAY_LEN = 9 ;
+static const uint8_t P9N2_C_T3_PMU_SCOM_COMPLETION_DELAY = 9 ;
+static const uint8_t P9N2_C_T3_PMU_SCOM_COMPLETION_DELAY_LEN = 9 ;
+static const uint8_t P9N2_C_T3_PMU_SCOM_SAMPLE_OVERRIDE = 18 ;
+static const uint8_t P9N2_C_T3_PMU_SCOM_SPARE_CTRL = 19 ;
+static const uint8_t P9N2_C_T3_PMU_SCOM_SPARE_CTRL_LEN = 5 ;
+
+static const uint8_t P9N2_EX_L2_TFAC_HOLD_OUT_TFC_CONTROL_TB41_HOLD_OUT = 0 ;
+static const uint8_t P9N2_EX_L2_TFAC_HOLD_OUT_TFC_CONTROL_TB41_HOLD_OUT_LEN = 2 ;
+static const uint8_t P9N2_EX_L2_TFAC_HOLD_OUT_TFC_FIRMWARE_CONTROL_TB41_HOLD_OUT = 2 ;
+static const uint8_t P9N2_EX_L2_TFAC_HOLD_OUT_TFC_FIRMWARE_CONTROL_TB41_HOLD_OUT_LEN = 7 ;
+static const uint8_t P9N2_EX_L2_TFAC_HOLD_OUT_TFC_PARITY_TB41_HOLD_OUT = 9 ;
+static const uint8_t P9N2_EX_L2_TFAC_HOLD_OUT_TFC_PARITY_TB41_HOLD_OUT_LEN = 6 ;
+static const uint8_t P9N2_EX_L2_TFAC_HOLD_OUT_TFC_SPR_TOD_STEP_CHECK_HOLD_OUT = 15 ;
+static const uint8_t P9N2_EX_L2_TFAC_HOLD_OUT_TFC_SPR_TOD_STEP_CHECK_HOLD_OUT_LEN = 3 ;
+static const uint8_t P9N2_EX_L2_TFAC_HOLD_OUT_TFD_DEC_RESIDUE_NOPSAV_HOLD_OUT = 18 ;
+static const uint8_t P9N2_EX_L2_TFAC_HOLD_OUT_TFD_DEC_RESIDUE_NOPSAV_HOLD_OUT_LEN = 4 ;
+static const uint8_t P9N2_EX_L2_TFAC_HOLD_OUT_TFD_HDEC_RESIDUE_NOPSAV_HOLD_OUT = 22 ;
+static const uint8_t P9N2_EX_L2_TFAC_HOLD_OUT_TFP_PARITY_NOPSAV_HOLD_OUT = 23 ;
+static const uint8_t P9N2_EX_L2_TFAC_HOLD_OUT_TFP_PARITY_NOPSAV_HOLD_OUT_LEN = 3 ;
+static const uint8_t P9N2_EX_L2_TFAC_HOLD_OUT_TFP_PUR_ACCUM_OFLOW_HOLD_OUT = 26 ;
+static const uint8_t P9N2_EX_L2_TFAC_HOLD_OUT_TFP_PUR_ACCUM_OFLOW_HOLD_OUT_LEN = 4 ;
+static const uint8_t P9N2_EX_L2_TFAC_HOLD_OUT_TFP_SPURR_SCALE_LIMIT_SCALE_HOLD_OUT = 30 ;
+static const uint8_t P9N2_EX_L2_TFAC_HOLD_OUT_TFR_PARITY_NOPSAV_HOLD_OUT = 31 ;
+static const uint8_t P9N2_EX_L2_TFAC_HOLD_OUT_TFR_PARITY_NOPSAV_HOLD_OUT_LEN = 8 ;
+static const uint8_t P9N2_EX_L2_TFAC_HOLD_OUT_TFR_TX_PUR_OVERFLOW_OFLOW_HOLD_OUT = 39 ;
+static const uint8_t P9N2_EX_L2_TFAC_HOLD_OUT_TFR_TX_PUR_OVERFLOW_OFLOW_HOLD_OUT_LEN = 4 ;
+static const uint8_t P9N2_EX_L2_TFAC_HOLD_OUT_TFR_TX_SPUR_OVERFLOW_OFLOW_HOLD_OUT = 43 ;
+static const uint8_t P9N2_EX_L2_TFAC_HOLD_OUT_TFR_TX_SPUR_OVERFLOW_OFLOW_HOLD_OUT_LEN = 4 ;
+
+static const uint8_t P9N2_C_TFAC_HOLD_OUT_TFC_CONTROL_TB41_HOLD_OUT = 0 ;
+static const uint8_t P9N2_C_TFAC_HOLD_OUT_TFC_CONTROL_TB41_HOLD_OUT_LEN = 2 ;
+static const uint8_t P9N2_C_TFAC_HOLD_OUT_TFC_FIRMWARE_CONTROL_TB41_HOLD_OUT = 2 ;
+static const uint8_t P9N2_C_TFAC_HOLD_OUT_TFC_FIRMWARE_CONTROL_TB41_HOLD_OUT_LEN = 7 ;
+static const uint8_t P9N2_C_TFAC_HOLD_OUT_TFC_PARITY_TB41_HOLD_OUT = 9 ;
+static const uint8_t P9N2_C_TFAC_HOLD_OUT_TFC_PARITY_TB41_HOLD_OUT_LEN = 6 ;
+static const uint8_t P9N2_C_TFAC_HOLD_OUT_TFC_SPR_TOD_STEP_CHECK_HOLD_OUT = 15 ;
+static const uint8_t P9N2_C_TFAC_HOLD_OUT_TFC_SPR_TOD_STEP_CHECK_HOLD_OUT_LEN = 3 ;
+static const uint8_t P9N2_C_TFAC_HOLD_OUT_TFD_DEC_RESIDUE_NOPSAV_HOLD_OUT = 18 ;
+static const uint8_t P9N2_C_TFAC_HOLD_OUT_TFD_DEC_RESIDUE_NOPSAV_HOLD_OUT_LEN = 4 ;
+static const uint8_t P9N2_C_TFAC_HOLD_OUT_TFD_HDEC_RESIDUE_NOPSAV_HOLD_OUT = 22 ;
+static const uint8_t P9N2_C_TFAC_HOLD_OUT_TFP_PARITY_NOPSAV_HOLD_OUT = 23 ;
+static const uint8_t P9N2_C_TFAC_HOLD_OUT_TFP_PARITY_NOPSAV_HOLD_OUT_LEN = 3 ;
+static const uint8_t P9N2_C_TFAC_HOLD_OUT_TFP_PUR_ACCUM_OFLOW_HOLD_OUT = 26 ;
+static const uint8_t P9N2_C_TFAC_HOLD_OUT_TFP_PUR_ACCUM_OFLOW_HOLD_OUT_LEN = 4 ;
+static const uint8_t P9N2_C_TFAC_HOLD_OUT_TFP_SPURR_SCALE_LIMIT_SCALE_HOLD_OUT = 30 ;
+static const uint8_t P9N2_C_TFAC_HOLD_OUT_TFR_PARITY_NOPSAV_HOLD_OUT = 31 ;
+static const uint8_t P9N2_C_TFAC_HOLD_OUT_TFR_PARITY_NOPSAV_HOLD_OUT_LEN = 8 ;
+static const uint8_t P9N2_C_TFAC_HOLD_OUT_TFR_TX_PUR_OVERFLOW_OFLOW_HOLD_OUT = 39 ;
+static const uint8_t P9N2_C_TFAC_HOLD_OUT_TFR_TX_PUR_OVERFLOW_OFLOW_HOLD_OUT_LEN = 4 ;
+static const uint8_t P9N2_C_TFAC_HOLD_OUT_TFR_TX_SPUR_OVERFLOW_OFLOW_HOLD_OUT = 43 ;
+static const uint8_t P9N2_C_TFAC_HOLD_OUT_TFR_TX_SPUR_OVERFLOW_OFLOW_HOLD_OUT_LEN = 4 ;
+
+static const uint8_t P9N2_EQ_THERM_MODE_REG_DIS_CPM_BUBBLE_CORR = 0 ;
+static const uint8_t P9N2_EQ_THERM_MODE_REG_FORCE_THRES_ACT = 1 ;
+static const uint8_t P9N2_EQ_THERM_MODE_REG_THRES_TRIP_ENA = 2 ;
+static const uint8_t P9N2_EQ_THERM_MODE_REG_THRES_TRIP_ENA_LEN = 3 ;
+static const uint8_t P9N2_EQ_THERM_MODE_REG_DTS_SAMPLE_ENA = 5 ;
+static const uint8_t P9N2_EQ_THERM_MODE_REG_SAMPLE_PULSE_CNT = 6 ;
+static const uint8_t P9N2_EQ_THERM_MODE_REG_SAMPLE_PULSE_CNT_LEN = 4 ;
+static const uint8_t P9N2_EQ_THERM_MODE_REG_THRES_ENA = 10 ;
+static const uint8_t P9N2_EQ_THERM_MODE_REG_THRES_ENA_LEN = 2 ;
+static const uint8_t P9N2_EQ_THERM_MODE_REG_DTS_TRIGGER = 12 ;
+static const uint8_t P9N2_EQ_THERM_MODE_REG_DTS_TRIGGER_SEL = 13 ;
+static const uint8_t P9N2_EQ_THERM_MODE_REG_THRES_OVERFLOW_MASK = 14 ;
+static const uint8_t P9N2_EQ_THERM_MODE_REG_UNUSED = 15 ;
+static const uint8_t P9N2_EQ_THERM_MODE_REG_DTS_READ_SEL = 16 ;
+static const uint8_t P9N2_EQ_THERM_MODE_REG_DTS_READ_SEL_LEN = 4 ;
+static const uint8_t P9N2_EQ_THERM_MODE_REG_DTS_ENABLE_L1 = 20 ;
+static const uint8_t P9N2_EQ_THERM_MODE_REG_DTS_ENABLE_L1_LEN = 2 ;
+static const uint8_t P9N2_EQ_THERM_MODE_REG_THERM_CPM_ENABLE_L1 = 35 ;
+static const uint8_t P9N2_EQ_THERM_MODE_REG_THERM_CPM_ENABLE_L1_LEN = 2 ;
+
+static const uint8_t P9N2_EX_THERM_MODE_REG_DIS_CPM_BUBBLE_CORR = 0 ;
+static const uint8_t P9N2_EX_THERM_MODE_REG_FORCE_THRES_ACT = 1 ;
+static const uint8_t P9N2_EX_THERM_MODE_REG_THRES_TRIP_ENA = 2 ;
+static const uint8_t P9N2_EX_THERM_MODE_REG_THRES_TRIP_ENA_LEN = 3 ;
+static const uint8_t P9N2_EX_THERM_MODE_REG_DTS_SAMPLE_ENA = 5 ;
+static const uint8_t P9N2_EX_THERM_MODE_REG_SAMPLE_PULSE_CNT = 6 ;
+static const uint8_t P9N2_EX_THERM_MODE_REG_SAMPLE_PULSE_CNT_LEN = 4 ;
+static const uint8_t P9N2_EX_THERM_MODE_REG_THRES_ENA = 10 ;
+static const uint8_t P9N2_EX_THERM_MODE_REG_THRES_ENA_LEN = 2 ;
+static const uint8_t P9N2_EX_THERM_MODE_REG_DTS_TRIGGER = 12 ;
+static const uint8_t P9N2_EX_THERM_MODE_REG_DTS_TRIGGER_SEL = 13 ;
+static const uint8_t P9N2_EX_THERM_MODE_REG_THRES_OVERFLOW_MASK = 14 ;
+static const uint8_t P9N2_EX_THERM_MODE_REG_UNUSED = 15 ;
+static const uint8_t P9N2_EX_THERM_MODE_REG_DTS_READ_SEL = 16 ;
+static const uint8_t P9N2_EX_THERM_MODE_REG_DTS_READ_SEL_LEN = 4 ;
+static const uint8_t P9N2_EX_THERM_MODE_REG_DTS_ENABLE_L1 = 20 ;
+static const uint8_t P9N2_EX_THERM_MODE_REG_DTS_ENABLE_L1_LEN = 2 ;
+static const uint8_t P9N2_EX_THERM_MODE_REG_THERM_CPM_ENABLE_L1 = 35 ;
+static const uint8_t P9N2_EX_THERM_MODE_REG_THERM_CPM_ENABLE_L1_LEN = 2 ;
+
+static const uint8_t P9N2_C_THERM_MODE_REG_DIS_CPM_BUBBLE_CORR = 0 ;
+static const uint8_t P9N2_C_THERM_MODE_REG_FORCE_THRES_ACT = 1 ;
+static const uint8_t P9N2_C_THERM_MODE_REG_THRES_TRIP_ENA = 2 ;
+static const uint8_t P9N2_C_THERM_MODE_REG_THRES_TRIP_ENA_LEN = 3 ;
+static const uint8_t P9N2_C_THERM_MODE_REG_DTS_SAMPLE_ENA = 5 ;
+static const uint8_t P9N2_C_THERM_MODE_REG_SAMPLE_PULSE_CNT = 6 ;
+static const uint8_t P9N2_C_THERM_MODE_REG_SAMPLE_PULSE_CNT_LEN = 4 ;
+static const uint8_t P9N2_C_THERM_MODE_REG_THRES_ENA = 10 ;
+static const uint8_t P9N2_C_THERM_MODE_REG_THRES_ENA_LEN = 2 ;
+static const uint8_t P9N2_C_THERM_MODE_REG_DTS_TRIGGER = 12 ;
+static const uint8_t P9N2_C_THERM_MODE_REG_DTS_TRIGGER_SEL = 13 ;
+static const uint8_t P9N2_C_THERM_MODE_REG_THRES_OVERFLOW_MASK = 14 ;
+static const uint8_t P9N2_C_THERM_MODE_REG_UNUSED = 15 ;
+static const uint8_t P9N2_C_THERM_MODE_REG_DTS_READ_SEL = 16 ;
+static const uint8_t P9N2_C_THERM_MODE_REG_DTS_READ_SEL_LEN = 4 ;
+static const uint8_t P9N2_C_THERM_MODE_REG_DTS_ENABLE_L1 = 20 ;
+static const uint8_t P9N2_C_THERM_MODE_REG_DTS_ENABLE_L1_LEN = 2 ;
+static const uint8_t P9N2_C_THERM_MODE_REG_THERM_CPM_ENABLE_L1 = 35 ;
+static const uint8_t P9N2_C_THERM_MODE_REG_THERM_CPM_ENABLE_L1_LEN = 2 ;
+
+static const uint8_t P9N2_EX_L2_THRCTL_HOLD_OUT_T0_CORE_HANG_DETECT_HOLD_OUT = 0 ;
+static const uint8_t P9N2_EX_L2_THRCTL_HOLD_OUT_T0_CORE_HUNG_HOLD_OUT = 1 ;
+static const uint8_t P9N2_EX_L2_THRCTL_HOLD_OUT_T0_CORE_STEP_HOLD_OUT = 2 ;
+static const uint8_t P9N2_EX_L2_THRCTL_HOLD_OUT_T0_HANG_DETECT_STATE_HOLD_OUT = 3 ;
+static const uint8_t P9N2_EX_L2_THRCTL_HOLD_OUT_T0_HANG_RECOV_HOLD_OUT = 4 ;
+static const uint8_t P9N2_EX_L2_THRCTL_HOLD_OUT_T0_NEST_HANG_DETECT_HOLD_OUT = 5 ;
+static const uint8_t P9N2_EX_L2_THRCTL_HOLD_OUT_T0_PPC_COMPLETE_HOLD_OUT = 6 ;
+static const uint8_t P9N2_EX_L2_THRCTL_HOLD_OUT_T0_QUIESCE_ARB_STATE_HOLD_OUT = 7 ;
+static const uint8_t P9N2_EX_L2_THRCTL_HOLD_OUT_T0_RECOV_IN_MAINT_HOLD_OUT = 8 ;
+static const uint8_t P9N2_EX_L2_THRCTL_HOLD_OUT_T0_STOP_COMPLETE_IN_SUSPEND_HOLD_OUT = 9 ;
+static const uint8_t P9N2_EX_L2_THRCTL_HOLD_OUT_T0_THREAD_CTL_STATE_HOLD_OUT = 10 ;
+static const uint8_t P9N2_EX_L2_THRCTL_HOLD_OUT_T1_CORE_HANG_DETECT_HOLD_OUT = 11 ;
+static const uint8_t P9N2_EX_L2_THRCTL_HOLD_OUT_T1_CORE_HUNG_HOLD_OUT = 12 ;
+static const uint8_t P9N2_EX_L2_THRCTL_HOLD_OUT_T1_CORE_STEP_HOLD_OUT = 13 ;
+static const uint8_t P9N2_EX_L2_THRCTL_HOLD_OUT_T1_HANG_DETECT_STATE_HOLD_OUT = 14 ;
+static const uint8_t P9N2_EX_L2_THRCTL_HOLD_OUT_T1_HANG_RECOV_HOLD_OUT = 15 ;
+static const uint8_t P9N2_EX_L2_THRCTL_HOLD_OUT_T1_NEST_HANG_DETECT_HOLD_OUT = 16 ;
+static const uint8_t P9N2_EX_L2_THRCTL_HOLD_OUT_T1_PPC_COMPLETE_HOLD_OUT = 17 ;
+static const uint8_t P9N2_EX_L2_THRCTL_HOLD_OUT_T1_QUIESCE_ARB_STATE_HOLD_OUT = 18 ;
+static const uint8_t P9N2_EX_L2_THRCTL_HOLD_OUT_T1_RECOV_IN_MAINT_HOLD_OUT = 19 ;
+static const uint8_t P9N2_EX_L2_THRCTL_HOLD_OUT_T1_STOP_COMPLETE_IN_SUSPEND_HOLD_OUT = 20 ;
+static const uint8_t P9N2_EX_L2_THRCTL_HOLD_OUT_T1_THREAD_CTL_STATE_HOLD_OUT = 21 ;
+static const uint8_t P9N2_EX_L2_THRCTL_HOLD_OUT_T2_CORE_HANG_DETECT_HOLD_OUT = 22 ;
+static const uint8_t P9N2_EX_L2_THRCTL_HOLD_OUT_T2_CORE_HUNG_HOLD_OUT = 23 ;
+static const uint8_t P9N2_EX_L2_THRCTL_HOLD_OUT_T2_CORE_STEP_HOLD_OUT = 24 ;
+static const uint8_t P9N2_EX_L2_THRCTL_HOLD_OUT_T2_HANG_DETECT_STATE_HOLD_OUT = 25 ;
+static const uint8_t P9N2_EX_L2_THRCTL_HOLD_OUT_T2_HANG_RECOV_HOLD_OUT = 26 ;
+static const uint8_t P9N2_EX_L2_THRCTL_HOLD_OUT_T2_NEST_HANG_DETECT_HOLD_OUT = 27 ;
+static const uint8_t P9N2_EX_L2_THRCTL_HOLD_OUT_T2_PPC_COMPLETE_HOLD_OUT = 28 ;
+static const uint8_t P9N2_EX_L2_THRCTL_HOLD_OUT_T2_QUIESCE_ARB_STATE_HOLD_OUT = 29 ;
+static const uint8_t P9N2_EX_L2_THRCTL_HOLD_OUT_T2_RECOV_IN_MAINT_HOLD_OUT = 30 ;
+static const uint8_t P9N2_EX_L2_THRCTL_HOLD_OUT_T2_STOP_COMPLETE_IN_SUSPEND_HOLD_OUT = 31 ;
+static const uint8_t P9N2_EX_L2_THRCTL_HOLD_OUT_T2_THREAD_CTL_STATE_HOLD_OUT = 32 ;
+static const uint8_t P9N2_EX_L2_THRCTL_HOLD_OUT_T3_CORE_HANG_DETECT_HOLD_OUT = 33 ;
+static const uint8_t P9N2_EX_L2_THRCTL_HOLD_OUT_T3_CORE_HUNG_HOLD_OUT = 34 ;
+static const uint8_t P9N2_EX_L2_THRCTL_HOLD_OUT_T3_CORE_STEP_HOLD_OUT = 35 ;
+static const uint8_t P9N2_EX_L2_THRCTL_HOLD_OUT_T3_HANG_DETECT_STATE_HOLD_OUT = 36 ;
+static const uint8_t P9N2_EX_L2_THRCTL_HOLD_OUT_T3_HANG_RECOV_HOLD_OUT = 37 ;
+static const uint8_t P9N2_EX_L2_THRCTL_HOLD_OUT_T3_NEST_HANG_DETECT_HOLD_OUT = 38 ;
+static const uint8_t P9N2_EX_L2_THRCTL_HOLD_OUT_T3_PPC_COMPLETE_HOLD_OUT = 39 ;
+static const uint8_t P9N2_EX_L2_THRCTL_HOLD_OUT_T3_QUIESCE_ARB_STATE_HOLD_OUT = 40 ;
+static const uint8_t P9N2_EX_L2_THRCTL_HOLD_OUT_T3_RECOV_IN_MAINT_HOLD_OUT = 41 ;
+static const uint8_t P9N2_EX_L2_THRCTL_HOLD_OUT_T3_STOP_COMPLETE_IN_SUSPEND_HOLD_OUT = 42 ;
+static const uint8_t P9N2_EX_L2_THRCTL_HOLD_OUT_T3_THREAD_CTL_STATE_HOLD_OUT = 43 ;
+static const uint8_t P9N2_EX_L2_THRCTL_HOLD_OUT_HID_PAR_HOLD_OUT = 44 ;
+static const uint8_t P9N2_EX_L2_THRCTL_HOLD_OUT_THRCTL_SCOM_HOLD_OUT = 45 ;
+static const uint8_t P9N2_EX_L2_THRCTL_HOLD_OUT_VT0_PSSCR_ESL_PAR_HOLD_OUT = 46 ;
+static const uint8_t P9N2_EX_L2_THRCTL_HOLD_OUT_VT1_PSSCR_ESL_PAR_HOLD_OUT = 47 ;
+static const uint8_t P9N2_EX_L2_THRCTL_HOLD_OUT_VT2_PSSCR_ESL_PAR_HOLD_OUT = 48 ;
+static const uint8_t P9N2_EX_L2_THRCTL_HOLD_OUT_VT3_PSSCR_ESL_PAR_HOLD_OUT = 49 ;
+
+static const uint8_t P9N2_C_THRCTL_HOLD_OUT_T0_CORE_HANG_DETECT_HOLD_OUT = 0 ;
+static const uint8_t P9N2_C_THRCTL_HOLD_OUT_T0_CORE_HUNG_HOLD_OUT = 1 ;
+static const uint8_t P9N2_C_THRCTL_HOLD_OUT_T0_CORE_STEP_HOLD_OUT = 2 ;
+static const uint8_t P9N2_C_THRCTL_HOLD_OUT_T0_HANG_DETECT_STATE_HOLD_OUT = 3 ;
+static const uint8_t P9N2_C_THRCTL_HOLD_OUT_T0_HANG_RECOV_HOLD_OUT = 4 ;
+static const uint8_t P9N2_C_THRCTL_HOLD_OUT_T0_NEST_HANG_DETECT_HOLD_OUT = 5 ;
+static const uint8_t P9N2_C_THRCTL_HOLD_OUT_T0_PPC_COMPLETE_HOLD_OUT = 6 ;
+static const uint8_t P9N2_C_THRCTL_HOLD_OUT_T0_QUIESCE_ARB_STATE_HOLD_OUT = 7 ;
+static const uint8_t P9N2_C_THRCTL_HOLD_OUT_T0_RECOV_IN_MAINT_HOLD_OUT = 8 ;
+static const uint8_t P9N2_C_THRCTL_HOLD_OUT_T0_STOP_COMPLETE_IN_SUSPEND_HOLD_OUT = 9 ;
+static const uint8_t P9N2_C_THRCTL_HOLD_OUT_T0_THREAD_CTL_STATE_HOLD_OUT = 10 ;
+static const uint8_t P9N2_C_THRCTL_HOLD_OUT_T1_CORE_HANG_DETECT_HOLD_OUT = 11 ;
+static const uint8_t P9N2_C_THRCTL_HOLD_OUT_T1_CORE_HUNG_HOLD_OUT = 12 ;
+static const uint8_t P9N2_C_THRCTL_HOLD_OUT_T1_CORE_STEP_HOLD_OUT = 13 ;
+static const uint8_t P9N2_C_THRCTL_HOLD_OUT_T1_HANG_DETECT_STATE_HOLD_OUT = 14 ;
+static const uint8_t P9N2_C_THRCTL_HOLD_OUT_T1_HANG_RECOV_HOLD_OUT = 15 ;
+static const uint8_t P9N2_C_THRCTL_HOLD_OUT_T1_NEST_HANG_DETECT_HOLD_OUT = 16 ;
+static const uint8_t P9N2_C_THRCTL_HOLD_OUT_T1_PPC_COMPLETE_HOLD_OUT = 17 ;
+static const uint8_t P9N2_C_THRCTL_HOLD_OUT_T1_QUIESCE_ARB_STATE_HOLD_OUT = 18 ;
+static const uint8_t P9N2_C_THRCTL_HOLD_OUT_T1_RECOV_IN_MAINT_HOLD_OUT = 19 ;
+static const uint8_t P9N2_C_THRCTL_HOLD_OUT_T1_STOP_COMPLETE_IN_SUSPEND_HOLD_OUT = 20 ;
+static const uint8_t P9N2_C_THRCTL_HOLD_OUT_T1_THREAD_CTL_STATE_HOLD_OUT = 21 ;
+static const uint8_t P9N2_C_THRCTL_HOLD_OUT_T2_CORE_HANG_DETECT_HOLD_OUT = 22 ;
+static const uint8_t P9N2_C_THRCTL_HOLD_OUT_T2_CORE_HUNG_HOLD_OUT = 23 ;
+static const uint8_t P9N2_C_THRCTL_HOLD_OUT_T2_CORE_STEP_HOLD_OUT = 24 ;
+static const uint8_t P9N2_C_THRCTL_HOLD_OUT_T2_HANG_DETECT_STATE_HOLD_OUT = 25 ;
+static const uint8_t P9N2_C_THRCTL_HOLD_OUT_T2_HANG_RECOV_HOLD_OUT = 26 ;
+static const uint8_t P9N2_C_THRCTL_HOLD_OUT_T2_NEST_HANG_DETECT_HOLD_OUT = 27 ;
+static const uint8_t P9N2_C_THRCTL_HOLD_OUT_T2_PPC_COMPLETE_HOLD_OUT = 28 ;
+static const uint8_t P9N2_C_THRCTL_HOLD_OUT_T2_QUIESCE_ARB_STATE_HOLD_OUT = 29 ;
+static const uint8_t P9N2_C_THRCTL_HOLD_OUT_T2_RECOV_IN_MAINT_HOLD_OUT = 30 ;
+static const uint8_t P9N2_C_THRCTL_HOLD_OUT_T2_STOP_COMPLETE_IN_SUSPEND_HOLD_OUT = 31 ;
+static const uint8_t P9N2_C_THRCTL_HOLD_OUT_T2_THREAD_CTL_STATE_HOLD_OUT = 32 ;
+static const uint8_t P9N2_C_THRCTL_HOLD_OUT_T3_CORE_HANG_DETECT_HOLD_OUT = 33 ;
+static const uint8_t P9N2_C_THRCTL_HOLD_OUT_T3_CORE_HUNG_HOLD_OUT = 34 ;
+static const uint8_t P9N2_C_THRCTL_HOLD_OUT_T3_CORE_STEP_HOLD_OUT = 35 ;
+static const uint8_t P9N2_C_THRCTL_HOLD_OUT_T3_HANG_DETECT_STATE_HOLD_OUT = 36 ;
+static const uint8_t P9N2_C_THRCTL_HOLD_OUT_T3_HANG_RECOV_HOLD_OUT = 37 ;
+static const uint8_t P9N2_C_THRCTL_HOLD_OUT_T3_NEST_HANG_DETECT_HOLD_OUT = 38 ;
+static const uint8_t P9N2_C_THRCTL_HOLD_OUT_T3_PPC_COMPLETE_HOLD_OUT = 39 ;
+static const uint8_t P9N2_C_THRCTL_HOLD_OUT_T3_QUIESCE_ARB_STATE_HOLD_OUT = 40 ;
+static const uint8_t P9N2_C_THRCTL_HOLD_OUT_T3_RECOV_IN_MAINT_HOLD_OUT = 41 ;
+static const uint8_t P9N2_C_THRCTL_HOLD_OUT_T3_STOP_COMPLETE_IN_SUSPEND_HOLD_OUT = 42 ;
+static const uint8_t P9N2_C_THRCTL_HOLD_OUT_T3_THREAD_CTL_STATE_HOLD_OUT = 43 ;
+static const uint8_t P9N2_C_THRCTL_HOLD_OUT_HID_PAR_HOLD_OUT = 44 ;
+static const uint8_t P9N2_C_THRCTL_HOLD_OUT_THRCTL_SCOM_HOLD_OUT = 45 ;
+static const uint8_t P9N2_C_THRCTL_HOLD_OUT_VT0_PSSCR_ESL_PAR_HOLD_OUT = 46 ;
+static const uint8_t P9N2_C_THRCTL_HOLD_OUT_VT1_PSSCR_ESL_PAR_HOLD_OUT = 47 ;
+static const uint8_t P9N2_C_THRCTL_HOLD_OUT_VT2_PSSCR_ESL_PAR_HOLD_OUT = 48 ;
+static const uint8_t P9N2_C_THRCTL_HOLD_OUT_VT3_PSSCR_ESL_PAR_HOLD_OUT = 49 ;
+
+static const uint8_t P9N2_EX_L2_THREAD_INFO_VTID0_V = 0 ;
+static const uint8_t P9N2_EX_L2_THREAD_INFO_VTID1_V = 1 ;
+static const uint8_t P9N2_EX_L2_THREAD_INFO_VTID2_V = 2 ;
+static const uint8_t P9N2_EX_L2_THREAD_INFO_VTID3_V = 3 ;
+static const uint8_t P9N2_EX_L2_THREAD_INFO_PTID0_V = 4 ;
+static const uint8_t P9N2_EX_L2_THREAD_INFO_PTID1_V = 5 ;
+static const uint8_t P9N2_EX_L2_THREAD_INFO_PTID2_V = 6 ;
+static const uint8_t P9N2_EX_L2_THREAD_INFO_PTID3_V = 7 ;
+static const uint8_t P9N2_EX_L2_THREAD_INFO_SMT_MODE = 8 ;
+static const uint8_t P9N2_EX_L2_THREAD_INFO_SMT_MODE_LEN = 2 ;
+static const uint8_t P9N2_EX_L2_THREAD_INFO_VTID0_TO_PTID_MAP = 10 ;
+static const uint8_t P9N2_EX_L2_THREAD_INFO_VTID0_TO_PTID_MAP_LEN = 2 ;
+static const uint8_t P9N2_EX_L2_THREAD_INFO_VTID1_TO_PTID_MAP = 12 ;
+static const uint8_t P9N2_EX_L2_THREAD_INFO_VTID1_TO_PTID_MAP_LEN = 2 ;
+static const uint8_t P9N2_EX_L2_THREAD_INFO_VTID2_TO_PTID_MAP = 14 ;
+static const uint8_t P9N2_EX_L2_THREAD_INFO_VTID2_TO_PTID_MAP_LEN = 2 ;
+static const uint8_t P9N2_EX_L2_THREAD_INFO_VTID3_TO_PTID_MAP = 16 ;
+static const uint8_t P9N2_EX_L2_THREAD_INFO_VTID3_TO_PTID_MAP_LEN = 2 ;
+static const uint8_t P9N2_EX_L2_THREAD_INFO_RAM_THREAD_ACTIVE = 18 ;
+static const uint8_t P9N2_EX_L2_THREAD_INFO_RAM_THREAD_ACTIVE_LEN = 4 ;
+static const uint8_t P9N2_EX_L2_THREAD_INFO_PSCOM_PURGE = 22 ;
+static const uint8_t P9N2_EX_L2_THREAD_INFO_THREAD_ACTION_IN_PROGRESS = 23 ;
+
+static const uint8_t P9N2_C_THREAD_INFO_VTID0_V = 0 ;
+static const uint8_t P9N2_C_THREAD_INFO_VTID1_V = 1 ;
+static const uint8_t P9N2_C_THREAD_INFO_VTID2_V = 2 ;
+static const uint8_t P9N2_C_THREAD_INFO_VTID3_V = 3 ;
+static const uint8_t P9N2_C_THREAD_INFO_PTID0_V = 4 ;
+static const uint8_t P9N2_C_THREAD_INFO_PTID1_V = 5 ;
+static const uint8_t P9N2_C_THREAD_INFO_PTID2_V = 6 ;
+static const uint8_t P9N2_C_THREAD_INFO_PTID3_V = 7 ;
+static const uint8_t P9N2_C_THREAD_INFO_SMT_MODE = 8 ;
+static const uint8_t P9N2_C_THREAD_INFO_SMT_MODE_LEN = 2 ;
+static const uint8_t P9N2_C_THREAD_INFO_VTID0_TO_PTID_MAP = 10 ;
+static const uint8_t P9N2_C_THREAD_INFO_VTID0_TO_PTID_MAP_LEN = 2 ;
+static const uint8_t P9N2_C_THREAD_INFO_VTID1_TO_PTID_MAP = 12 ;
+static const uint8_t P9N2_C_THREAD_INFO_VTID1_TO_PTID_MAP_LEN = 2 ;
+static const uint8_t P9N2_C_THREAD_INFO_VTID2_TO_PTID_MAP = 14 ;
+static const uint8_t P9N2_C_THREAD_INFO_VTID2_TO_PTID_MAP_LEN = 2 ;
+static const uint8_t P9N2_C_THREAD_INFO_VTID3_TO_PTID_MAP = 16 ;
+static const uint8_t P9N2_C_THREAD_INFO_VTID3_TO_PTID_MAP_LEN = 2 ;
+static const uint8_t P9N2_C_THREAD_INFO_RAM_THREAD_ACTIVE = 18 ;
+static const uint8_t P9N2_C_THREAD_INFO_RAM_THREAD_ACTIVE_LEN = 4 ;
+static const uint8_t P9N2_C_THREAD_INFO_PSCOM_PURGE = 22 ;
+static const uint8_t P9N2_C_THREAD_INFO_THREAD_ACTION_IN_PROGRESS = 23 ;
+
+static const uint8_t P9N2_EX_THROTTLE_CONTROL_SCOM_DIDT_THROTTLE = 0 ;
+static const uint8_t P9N2_EX_THROTTLE_CONTROL_SCOM_DIDT_THROTTLE_LEN = 2 ;
+static const uint8_t P9N2_EX_THROTTLE_CONTROL_SCOM_DIDT_TRIGGER_ENABLE = 2 ;
+static const uint8_t P9N2_EX_THROTTLE_CONTROL_SCOM_CORE_SLOWDOWN = 3 ;
+static const uint8_t P9N2_EX_THROTTLE_CONTROL_SCOM_FORCE_DYN_SUPPRESS = 4 ;
+static const uint8_t P9N2_EX_THROTTLE_CONTROL_SCOM_DYN_SUPPRESS_ON_THROTTLE = 5 ;
+static const uint8_t P9N2_EX_THROTTLE_CONTROL_SCOM_DISABLE_DROOP = 6 ;
+static const uint8_t P9N2_EX_THROTTLE_CONTROL_SCOM_DISABLE_DROOP_LEN = 3 ;
+static const uint8_t P9N2_EX_THROTTLE_CONTROL_SCOM_DROOP_MODE_DISABLE = 9 ;
+static const uint8_t P9N2_EX_THROTTLE_CONTROL_SCOM_DROOP_MODE_DISABLE_LEN = 2 ;
+
+static const uint8_t P9N2_C_THROTTLE_CONTROL_SCOM_DIDT_THROTTLE = 0 ;
+static const uint8_t P9N2_C_THROTTLE_CONTROL_SCOM_DIDT_THROTTLE_LEN = 2 ;
+static const uint8_t P9N2_C_THROTTLE_CONTROL_SCOM_DIDT_TRIGGER_ENABLE = 2 ;
+static const uint8_t P9N2_C_THROTTLE_CONTROL_SCOM_CORE_SLOWDOWN = 3 ;
+static const uint8_t P9N2_C_THROTTLE_CONTROL_SCOM_FORCE_DYN_SUPPRESS = 4 ;
+static const uint8_t P9N2_C_THROTTLE_CONTROL_SCOM_DYN_SUPPRESS_ON_THROTTLE = 5 ;
+static const uint8_t P9N2_C_THROTTLE_CONTROL_SCOM_DISABLE_DROOP = 6 ;
+static const uint8_t P9N2_C_THROTTLE_CONTROL_SCOM_DISABLE_DROOP_LEN = 3 ;
+static const uint8_t P9N2_C_THROTTLE_CONTROL_SCOM_DROOP_MODE_DISABLE = 9 ;
+static const uint8_t P9N2_C_THROTTLE_CONTROL_SCOM_DROOP_MODE_DISABLE_LEN = 2 ;
+
+static const uint8_t P9N2_EQ_TIMEOUT_REG_INT_TIMEOUT = 0 ;
+static const uint8_t P9N2_EQ_TIMEOUT_REG_INT_TIMEOUT_LEN = 2 ;
+
+static const uint8_t P9N2_EX_TIMEOUT_REG_INT_TIMEOUT = 0 ;
+static const uint8_t P9N2_EX_TIMEOUT_REG_INT_TIMEOUT_LEN = 2 ;
+
+static const uint8_t P9N2_C_TIMEOUT_REG_INT_TIMEOUT = 0 ;
+static const uint8_t P9N2_C_TIMEOUT_REG_INT_TIMEOUT_LEN = 2 ;
+
+static const uint8_t P9N2_EQ_TIMESTAMP_COUNTER_READ_VALUE = 0 ;
+static const uint8_t P9N2_EQ_TIMESTAMP_COUNTER_READ_VALUE_LEN = 44 ;
+static const uint8_t P9N2_EQ_TIMESTAMP_COUNTER_READ_OVERFLOW_ERR = 44 ;
+
+static const uint8_t P9N2_EX_TIMESTAMP_COUNTER_READ_VALUE = 0 ;
+static const uint8_t P9N2_EX_TIMESTAMP_COUNTER_READ_VALUE_LEN = 44 ;
+static const uint8_t P9N2_EX_TIMESTAMP_COUNTER_READ_OVERFLOW_ERR = 44 ;
+
+static const uint8_t P9N2_C_TIMESTAMP_COUNTER_READ_VALUE = 0 ;
+static const uint8_t P9N2_C_TIMESTAMP_COUNTER_READ_VALUE_LEN = 44 ;
+static const uint8_t P9N2_C_TIMESTAMP_COUNTER_READ_OVERFLOW_ERR = 44 ;
+
+static const uint8_t P9N2_EX_L2_TOD_READ_TIMEBASE = 0 ;
+static const uint8_t P9N2_EX_L2_TOD_READ_TIMEBASE_LEN = 60 ;
+
+static const uint8_t P9N2_C_TOD_READ_TIMEBASE = 0 ;
+static const uint8_t P9N2_C_TOD_READ_TIMEBASE_LEN = 60 ;
+
+static const uint8_t P9N2_EX_L2_TOD_SYNC000_TIMEBASE = 0 ;
+static const uint8_t P9N2_EX_L2_TOD_SYNC000_TIMEBASE_LEN = 55 ;
+static const uint8_t P9N2_EX_L2_TOD_SYNC000_CHIP_STATUS = 60 ;
+static const uint8_t P9N2_EX_L2_TOD_SYNC000_CHIP_STATUS_LEN = 4 ;
+
+static const uint8_t P9N2_C_TOD_SYNC000_TIMEBASE = 0 ;
+static const uint8_t P9N2_C_TOD_SYNC000_TIMEBASE_LEN = 55 ;
+static const uint8_t P9N2_C_TOD_SYNC000_CHIP_STATUS = 60 ;
+static const uint8_t P9N2_C_TOD_SYNC000_CHIP_STATUS_LEN = 4 ;
+
+static const uint8_t P9N2_EX_L2_TOD_SYNC001_TIMEBASE = 0 ;
+static const uint8_t P9N2_EX_L2_TOD_SYNC001_TIMEBASE_LEN = 54 ;
+static const uint8_t P9N2_EX_L2_TOD_SYNC001_CHIP_STATUS = 60 ;
+static const uint8_t P9N2_EX_L2_TOD_SYNC001_CHIP_STATUS_LEN = 4 ;
+
+static const uint8_t P9N2_C_TOD_SYNC001_TIMEBASE = 0 ;
+static const uint8_t P9N2_C_TOD_SYNC001_TIMEBASE_LEN = 54 ;
+static const uint8_t P9N2_C_TOD_SYNC001_CHIP_STATUS = 60 ;
+static const uint8_t P9N2_C_TOD_SYNC001_CHIP_STATUS_LEN = 4 ;
+
+static const uint8_t P9N2_EX_L2_TOD_SYNC010_TIMEBASE = 0 ;
+static const uint8_t P9N2_EX_L2_TOD_SYNC010_TIMEBASE_LEN = 53 ;
+static const uint8_t P9N2_EX_L2_TOD_SYNC010_CHIP_STATUS = 60 ;
+static const uint8_t P9N2_EX_L2_TOD_SYNC010_CHIP_STATUS_LEN = 4 ;
+
+static const uint8_t P9N2_C_TOD_SYNC010_TIMEBASE = 0 ;
+static const uint8_t P9N2_C_TOD_SYNC010_TIMEBASE_LEN = 53 ;
+static const uint8_t P9N2_C_TOD_SYNC010_CHIP_STATUS = 60 ;
+static const uint8_t P9N2_C_TOD_SYNC010_CHIP_STATUS_LEN = 4 ;
+
+static const uint8_t P9N2_EX_L2_TOD_SYNC011_TIMEBASE = 0 ;
+static const uint8_t P9N2_EX_L2_TOD_SYNC011_TIMEBASE_LEN = 52 ;
+static const uint8_t P9N2_EX_L2_TOD_SYNC011_CHIP_STATUS = 60 ;
+static const uint8_t P9N2_EX_L2_TOD_SYNC011_CHIP_STATUS_LEN = 4 ;
+
+static const uint8_t P9N2_C_TOD_SYNC011_TIMEBASE = 0 ;
+static const uint8_t P9N2_C_TOD_SYNC011_TIMEBASE_LEN = 52 ;
+static const uint8_t P9N2_C_TOD_SYNC011_CHIP_STATUS = 60 ;
+static const uint8_t P9N2_C_TOD_SYNC011_CHIP_STATUS_LEN = 4 ;
+
+static const uint8_t P9N2_EX_L2_TOD_SYNC100_TIMEBASE = 0 ;
+static const uint8_t P9N2_EX_L2_TOD_SYNC100_TIMEBASE_LEN = 51 ;
+static const uint8_t P9N2_EX_L2_TOD_SYNC100_CHIP_STATUS = 60 ;
+static const uint8_t P9N2_EX_L2_TOD_SYNC100_CHIP_STATUS_LEN = 4 ;
+
+static const uint8_t P9N2_C_TOD_SYNC100_TIMEBASE = 0 ;
+static const uint8_t P9N2_C_TOD_SYNC100_TIMEBASE_LEN = 51 ;
+static const uint8_t P9N2_C_TOD_SYNC100_CHIP_STATUS = 60 ;
+static const uint8_t P9N2_C_TOD_SYNC100_CHIP_STATUS_LEN = 4 ;
+
+static const uint8_t P9N2_EX_L2_TOD_SYNC101_TIMEBASE = 0 ;
+static const uint8_t P9N2_EX_L2_TOD_SYNC101_TIMEBASE_LEN = 50 ;
+static const uint8_t P9N2_EX_L2_TOD_SYNC101_CHIP_STATUS = 60 ;
+static const uint8_t P9N2_EX_L2_TOD_SYNC101_CHIP_STATUS_LEN = 4 ;
+
+static const uint8_t P9N2_C_TOD_SYNC101_TIMEBASE = 0 ;
+static const uint8_t P9N2_C_TOD_SYNC101_TIMEBASE_LEN = 50 ;
+static const uint8_t P9N2_C_TOD_SYNC101_CHIP_STATUS = 60 ;
+static const uint8_t P9N2_C_TOD_SYNC101_CHIP_STATUS_LEN = 4 ;
+
+static const uint8_t P9N2_EX_L2_TOD_SYNC110_TIMEBASE = 0 ;
+static const uint8_t P9N2_EX_L2_TOD_SYNC110_TIMEBASE_LEN = 49 ;
+static const uint8_t P9N2_EX_L2_TOD_SYNC110_CHIP_STATUS = 60 ;
+static const uint8_t P9N2_EX_L2_TOD_SYNC110_CHIP_STATUS_LEN = 4 ;
+
+static const uint8_t P9N2_C_TOD_SYNC110_TIMEBASE = 0 ;
+static const uint8_t P9N2_C_TOD_SYNC110_TIMEBASE_LEN = 49 ;
+static const uint8_t P9N2_C_TOD_SYNC110_CHIP_STATUS = 60 ;
+static const uint8_t P9N2_C_TOD_SYNC110_CHIP_STATUS_LEN = 4 ;
+
+static const uint8_t P9N2_EX_L2_TOD_SYNC111_TIMEBASE = 0 ;
+static const uint8_t P9N2_EX_L2_TOD_SYNC111_TIMEBASE_LEN = 48 ;
+static const uint8_t P9N2_EX_L2_TOD_SYNC111_CHIP_STATUS = 60 ;
+static const uint8_t P9N2_EX_L2_TOD_SYNC111_CHIP_STATUS_LEN = 4 ;
+
+static const uint8_t P9N2_C_TOD_SYNC111_TIMEBASE = 0 ;
+static const uint8_t P9N2_C_TOD_SYNC111_TIMEBASE_LEN = 48 ;
+static const uint8_t P9N2_C_TOD_SYNC111_CHIP_STATUS = 60 ;
+static const uint8_t P9N2_C_TOD_SYNC111_CHIP_STATUS_LEN = 4 ;
+
+static const uint8_t P9N2_EQ_TRACE_HI_DATA_REG_DATA = 0 ;
+static const uint8_t P9N2_EQ_TRACE_HI_DATA_REG_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_EX_TRACE_HI_DATA_REG_DATA = 0 ;
+static const uint8_t P9N2_EX_TRACE_HI_DATA_REG_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_C_TRACE_HI_DATA_REG_DATA = 0 ;
+static const uint8_t P9N2_C_TRACE_HI_DATA_REG_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_EQ_TRACE_LO_DATA_REG_DATA = 0 ;
+static const uint8_t P9N2_EQ_TRACE_LO_DATA_REG_DATA_LEN = 32 ;
+static const uint8_t P9N2_EQ_TRACE_LO_DATA_REG_ADDRESS = 32 ;
+static const uint8_t P9N2_EQ_TRACE_LO_DATA_REG_ADDRESS_LEN = 10 ;
+static const uint8_t P9N2_EQ_TRACE_LO_DATA_REG_LAST_BANK = 42 ;
+static const uint8_t P9N2_EQ_TRACE_LO_DATA_REG_LAST_BANK_LEN = 9 ;
+static const uint8_t P9N2_EQ_TRACE_LO_DATA_REG_LAST_BANK_VALID = 51 ;
+static const uint8_t P9N2_EQ_TRACE_LO_DATA_REG_WRITE_ON_RUN = 52 ;
+static const uint8_t P9N2_EQ_TRACE_LO_DATA_REG_RUNNING = 53 ;
+static const uint8_t P9N2_EQ_TRACE_LO_DATA_REG_HOLD_ADDRESS = 54 ;
+static const uint8_t P9N2_EQ_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN = 10 ;
+
+static const uint8_t P9N2_EX_TRACE_LO_DATA_REG_DATA = 0 ;
+static const uint8_t P9N2_EX_TRACE_LO_DATA_REG_DATA_LEN = 32 ;
+static const uint8_t P9N2_EX_TRACE_LO_DATA_REG_ADDRESS = 32 ;
+static const uint8_t P9N2_EX_TRACE_LO_DATA_REG_ADDRESS_LEN = 10 ;
+static const uint8_t P9N2_EX_TRACE_LO_DATA_REG_LAST_BANK = 42 ;
+static const uint8_t P9N2_EX_TRACE_LO_DATA_REG_LAST_BANK_LEN = 9 ;
+static const uint8_t P9N2_EX_TRACE_LO_DATA_REG_LAST_BANK_VALID = 51 ;
+static const uint8_t P9N2_EX_TRACE_LO_DATA_REG_WRITE_ON_RUN = 52 ;
+static const uint8_t P9N2_EX_TRACE_LO_DATA_REG_RUNNING = 53 ;
+static const uint8_t P9N2_EX_TRACE_LO_DATA_REG_HOLD_ADDRESS = 54 ;
+static const uint8_t P9N2_EX_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN = 10 ;
+
+static const uint8_t P9N2_C_TRACE_LO_DATA_REG_DATA = 0 ;
+static const uint8_t P9N2_C_TRACE_LO_DATA_REG_DATA_LEN = 32 ;
+static const uint8_t P9N2_C_TRACE_LO_DATA_REG_ADDRESS = 32 ;
+static const uint8_t P9N2_C_TRACE_LO_DATA_REG_ADDRESS_LEN = 10 ;
+static const uint8_t P9N2_C_TRACE_LO_DATA_REG_LAST_BANK = 42 ;
+static const uint8_t P9N2_C_TRACE_LO_DATA_REG_LAST_BANK_LEN = 9 ;
+static const uint8_t P9N2_C_TRACE_LO_DATA_REG_LAST_BANK_VALID = 51 ;
+static const uint8_t P9N2_C_TRACE_LO_DATA_REG_WRITE_ON_RUN = 52 ;
+static const uint8_t P9N2_C_TRACE_LO_DATA_REG_RUNNING = 53 ;
+static const uint8_t P9N2_C_TRACE_LO_DATA_REG_HOLD_ADDRESS = 54 ;
+static const uint8_t P9N2_C_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN = 10 ;
+
+static const uint8_t P9N2_EQ_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE = 0 ;
+static const uint8_t P9N2_EQ_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE = 1 ;
+static const uint8_t P9N2_EQ_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE = 2 ;
+static const uint8_t P9N2_EQ_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN = 8 ;
+static const uint8_t P9N2_EQ_TRACE_TRCTRL_CONFIG_BANK_MODE = 10 ;
+static const uint8_t P9N2_EQ_TRACE_TRCTRL_CONFIG_ENH_MODE = 11 ;
+static const uint8_t P9N2_EQ_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL = 12 ;
+static const uint8_t P9N2_EQ_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN = 2 ;
+static const uint8_t P9N2_EQ_TRACE_TRCTRL_CONFIG_SELECT_CONTROL = 14 ;
+static const uint8_t P9N2_EQ_TRACE_TRCTRL_CONFIG_SELECT_CONTROL_LEN = 4 ;
+static const uint8_t P9N2_EQ_TRACE_TRCTRL_CONFIG_RUN_HOLD_OFF = 18 ;
+static const uint8_t P9N2_EQ_TRACE_TRCTRL_CONFIG_RUN_STATUS = 19 ;
+static const uint8_t P9N2_EQ_TRACE_TRCTRL_CONFIG_RUN_STICKY = 20 ;
+static const uint8_t P9N2_EQ_TRACE_TRCTRL_CONFIG_DISABLE_BANK_EDGE_DETECT = 21 ;
+static const uint8_t P9N2_EQ_TRACE_TRCTRL_CONFIG_CONTROL_UNUSED = 22 ;
+static const uint8_t P9N2_EQ_TRACE_TRCTRL_CONFIG_CONTROL_UNUSED_LEN = 6 ;
+
+static const uint8_t P9N2_EX_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE = 0 ;
+static const uint8_t P9N2_EX_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE = 1 ;
+static const uint8_t P9N2_EX_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE = 2 ;
+static const uint8_t P9N2_EX_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN = 8 ;
+static const uint8_t P9N2_EX_TRACE_TRCTRL_CONFIG_BANK_MODE = 10 ;
+static const uint8_t P9N2_EX_TRACE_TRCTRL_CONFIG_ENH_MODE = 11 ;
+static const uint8_t P9N2_EX_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL = 12 ;
+static const uint8_t P9N2_EX_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN = 2 ;
+static const uint8_t P9N2_EX_TRACE_TRCTRL_CONFIG_SELECT_CONTROL = 14 ;
+static const uint8_t P9N2_EX_TRACE_TRCTRL_CONFIG_SELECT_CONTROL_LEN = 4 ;
+static const uint8_t P9N2_EX_TRACE_TRCTRL_CONFIG_RUN_HOLD_OFF = 18 ;
+static const uint8_t P9N2_EX_TRACE_TRCTRL_CONFIG_RUN_STATUS = 19 ;
+static const uint8_t P9N2_EX_TRACE_TRCTRL_CONFIG_RUN_STICKY = 20 ;
+static const uint8_t P9N2_EX_TRACE_TRCTRL_CONFIG_DISABLE_BANK_EDGE_DETECT = 21 ;
+static const uint8_t P9N2_EX_TRACE_TRCTRL_CONFIG_CONTROL_UNUSED = 22 ;
+static const uint8_t P9N2_EX_TRACE_TRCTRL_CONFIG_CONTROL_UNUSED_LEN = 6 ;
+
+static const uint8_t P9N2_C_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE = 0 ;
+static const uint8_t P9N2_C_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE = 1 ;
+static const uint8_t P9N2_C_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE = 2 ;
+static const uint8_t P9N2_C_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN = 8 ;
+static const uint8_t P9N2_C_TRACE_TRCTRL_CONFIG_BANK_MODE = 10 ;
+static const uint8_t P9N2_C_TRACE_TRCTRL_CONFIG_ENH_MODE = 11 ;
+static const uint8_t P9N2_C_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL = 12 ;
+static const uint8_t P9N2_C_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN = 2 ;
+static const uint8_t P9N2_C_TRACE_TRCTRL_CONFIG_SELECT_CONTROL = 14 ;
+static const uint8_t P9N2_C_TRACE_TRCTRL_CONFIG_SELECT_CONTROL_LEN = 4 ;
+static const uint8_t P9N2_C_TRACE_TRCTRL_CONFIG_RUN_HOLD_OFF = 18 ;
+static const uint8_t P9N2_C_TRACE_TRCTRL_CONFIG_RUN_STATUS = 19 ;
+static const uint8_t P9N2_C_TRACE_TRCTRL_CONFIG_RUN_STICKY = 20 ;
+static const uint8_t P9N2_C_TRACE_TRCTRL_CONFIG_DISABLE_BANK_EDGE_DETECT = 21 ;
+static const uint8_t P9N2_C_TRACE_TRCTRL_CONFIG_CONTROL_UNUSED = 22 ;
+static const uint8_t P9N2_C_TRACE_TRCTRL_CONFIG_CONTROL_UNUSED_LEN = 6 ;
+
+static const uint8_t P9N2_EQ_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 = 0 ;
+static const uint8_t P9N2_EQ_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN = 64 ;
+
+static const uint8_t P9N2_EX_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 = 0 ;
+static const uint8_t P9N2_EX_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN = 64 ;
+
+static const uint8_t P9N2_C_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 = 0 ;
+static const uint8_t P9N2_C_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN = 64 ;
+
+static const uint8_t P9N2_EQ_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 = 0 ;
+static const uint8_t P9N2_EQ_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN = 24 ;
+
+static const uint8_t P9N2_EX_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 = 0 ;
+static const uint8_t P9N2_EX_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN = 24 ;
+
+static const uint8_t P9N2_C_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 = 0 ;
+static const uint8_t P9N2_C_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN = 24 ;
+
+static const uint8_t P9N2_EQ_TRACE_TRDATA_CONFIG_2_PATTERNA = 0 ;
+static const uint8_t P9N2_EQ_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN = 24 ;
+static const uint8_t P9N2_EQ_TRACE_TRDATA_CONFIG_2_PATTERNB = 24 ;
+static const uint8_t P9N2_EQ_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN = 24 ;
+
+static const uint8_t P9N2_EX_TRACE_TRDATA_CONFIG_2_PATTERNA = 0 ;
+static const uint8_t P9N2_EX_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN = 24 ;
+static const uint8_t P9N2_EX_TRACE_TRDATA_CONFIG_2_PATTERNB = 24 ;
+static const uint8_t P9N2_EX_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN = 24 ;
+
+static const uint8_t P9N2_C_TRACE_TRDATA_CONFIG_2_PATTERNA = 0 ;
+static const uint8_t P9N2_C_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN = 24 ;
+static const uint8_t P9N2_C_TRACE_TRDATA_CONFIG_2_PATTERNB = 24 ;
+static const uint8_t P9N2_C_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN = 24 ;
+
+static const uint8_t P9N2_EQ_TRACE_TRDATA_CONFIG_3_PATTERNC = 0 ;
+static const uint8_t P9N2_EQ_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN = 24 ;
+static const uint8_t P9N2_EQ_TRACE_TRDATA_CONFIG_3_PATTERND = 24 ;
+static const uint8_t P9N2_EQ_TRACE_TRDATA_CONFIG_3_PATTERND_LEN = 24 ;
+
+static const uint8_t P9N2_EX_TRACE_TRDATA_CONFIG_3_PATTERNC = 0 ;
+static const uint8_t P9N2_EX_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN = 24 ;
+static const uint8_t P9N2_EX_TRACE_TRDATA_CONFIG_3_PATTERND = 24 ;
+static const uint8_t P9N2_EX_TRACE_TRDATA_CONFIG_3_PATTERND_LEN = 24 ;
+
+static const uint8_t P9N2_C_TRACE_TRDATA_CONFIG_3_PATTERNC = 0 ;
+static const uint8_t P9N2_C_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN = 24 ;
+static const uint8_t P9N2_C_TRACE_TRDATA_CONFIG_3_PATTERND = 24 ;
+static const uint8_t P9N2_C_TRACE_TRDATA_CONFIG_3_PATTERND_LEN = 24 ;
+
+static const uint8_t P9N2_EQ_TRACE_TRDATA_CONFIG_4_MASKA = 0 ;
+static const uint8_t P9N2_EQ_TRACE_TRDATA_CONFIG_4_MASKA_LEN = 24 ;
+static const uint8_t P9N2_EQ_TRACE_TRDATA_CONFIG_4_MASKB = 24 ;
+static const uint8_t P9N2_EQ_TRACE_TRDATA_CONFIG_4_MASKB_LEN = 24 ;
+
+static const uint8_t P9N2_EX_TRACE_TRDATA_CONFIG_4_MASKA = 0 ;
+static const uint8_t P9N2_EX_TRACE_TRDATA_CONFIG_4_MASKA_LEN = 24 ;
+static const uint8_t P9N2_EX_TRACE_TRDATA_CONFIG_4_MASKB = 24 ;
+static const uint8_t P9N2_EX_TRACE_TRDATA_CONFIG_4_MASKB_LEN = 24 ;
+
+static const uint8_t P9N2_C_TRACE_TRDATA_CONFIG_4_MASKA = 0 ;
+static const uint8_t P9N2_C_TRACE_TRDATA_CONFIG_4_MASKA_LEN = 24 ;
+static const uint8_t P9N2_C_TRACE_TRDATA_CONFIG_4_MASKB = 24 ;
+static const uint8_t P9N2_C_TRACE_TRDATA_CONFIG_4_MASKB_LEN = 24 ;
+
+static const uint8_t P9N2_EQ_TRACE_TRDATA_CONFIG_5_MASKC = 0 ;
+static const uint8_t P9N2_EQ_TRACE_TRDATA_CONFIG_5_MASKC_LEN = 24 ;
+static const uint8_t P9N2_EQ_TRACE_TRDATA_CONFIG_5_MASKD = 24 ;
+static const uint8_t P9N2_EQ_TRACE_TRDATA_CONFIG_5_MASKD_LEN = 24 ;
+
+static const uint8_t P9N2_EX_TRACE_TRDATA_CONFIG_5_MASKC = 0 ;
+static const uint8_t P9N2_EX_TRACE_TRDATA_CONFIG_5_MASKC_LEN = 24 ;
+static const uint8_t P9N2_EX_TRACE_TRDATA_CONFIG_5_MASKD = 24 ;
+static const uint8_t P9N2_EX_TRACE_TRDATA_CONFIG_5_MASKD_LEN = 24 ;
+
+static const uint8_t P9N2_C_TRACE_TRDATA_CONFIG_5_MASKC = 0 ;
+static const uint8_t P9N2_C_TRACE_TRDATA_CONFIG_5_MASKC_LEN = 24 ;
+static const uint8_t P9N2_C_TRACE_TRDATA_CONFIG_5_MASKD = 24 ;
+static const uint8_t P9N2_C_TRACE_TRDATA_CONFIG_5_MASKD_LEN = 24 ;
+
+static const uint8_t P9N2_EQ_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION = 0 ;
+static const uint8_t P9N2_EQ_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK = 1 ;
+static const uint8_t P9N2_EQ_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL = 2 ;
+static const uint8_t P9N2_EQ_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN = 2 ;
+static const uint8_t P9N2_EQ_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL = 4 ;
+static const uint8_t P9N2_EQ_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN = 2 ;
+static const uint8_t P9N2_EQ_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL = 6 ;
+static const uint8_t P9N2_EQ_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN = 2 ;
+static const uint8_t P9N2_EQ_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL = 8 ;
+static const uint8_t P9N2_EQ_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN = 2 ;
+static const uint8_t P9N2_EQ_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK = 10 ;
+static const uint8_t P9N2_EQ_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN = 4 ;
+static const uint8_t P9N2_EQ_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK = 14 ;
+static const uint8_t P9N2_EQ_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN = 4 ;
+static const uint8_t P9N2_EQ_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK = 18 ;
+static const uint8_t P9N2_EQ_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN = 4 ;
+static const uint8_t P9N2_EQ_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK = 22 ;
+static const uint8_t P9N2_EQ_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN = 4 ;
+static const uint8_t P9N2_EQ_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE = 26 ;
+static const uint8_t P9N2_EQ_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE = 27 ;
+static const uint8_t P9N2_EQ_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE = 28 ;
+static const uint8_t P9N2_EQ_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN = 4 ;
+static const uint8_t P9N2_EQ_TRACE_TRDATA_CONFIG_9_ERROR_CMP_MASK = 32 ;
+static const uint8_t P9N2_EQ_TRACE_TRDATA_CONFIG_9_ERROR_CMP_PATTERN = 33 ;
+static const uint8_t P9N2_EQ_TRACE_TRDATA_CONFIG_9_TRIG0_ERR_CMP = 34 ;
+static const uint8_t P9N2_EQ_TRACE_TRDATA_CONFIG_9_TRIG1_ERR_CMP = 35 ;
+static const uint8_t P9N2_EQ_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES = 36 ;
+static const uint8_t P9N2_EQ_TRACE_TRDATA_CONFIG_9_SPARE_LT = 37 ;
+
+static const uint8_t P9N2_EX_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION = 0 ;
+static const uint8_t P9N2_EX_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK = 1 ;
+static const uint8_t P9N2_EX_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL = 2 ;
+static const uint8_t P9N2_EX_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN = 2 ;
+static const uint8_t P9N2_EX_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL = 4 ;
+static const uint8_t P9N2_EX_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN = 2 ;
+static const uint8_t P9N2_EX_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL = 6 ;
+static const uint8_t P9N2_EX_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN = 2 ;
+static const uint8_t P9N2_EX_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL = 8 ;
+static const uint8_t P9N2_EX_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN = 2 ;
+static const uint8_t P9N2_EX_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK = 10 ;
+static const uint8_t P9N2_EX_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN = 4 ;
+static const uint8_t P9N2_EX_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK = 14 ;
+static const uint8_t P9N2_EX_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN = 4 ;
+static const uint8_t P9N2_EX_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK = 18 ;
+static const uint8_t P9N2_EX_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN = 4 ;
+static const uint8_t P9N2_EX_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK = 22 ;
+static const uint8_t P9N2_EX_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN = 4 ;
+static const uint8_t P9N2_EX_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE = 26 ;
+static const uint8_t P9N2_EX_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE = 27 ;
+static const uint8_t P9N2_EX_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE = 28 ;
+static const uint8_t P9N2_EX_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN = 4 ;
+static const uint8_t P9N2_EX_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT = 32 ;
+static const uint8_t P9N2_EX_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN = 4 ;
+static const uint8_t P9N2_EX_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES = 36 ;
+static const uint8_t P9N2_EX_TRACE_TRDATA_CONFIG_9_SPARE_LT = 37 ;
+
+static const uint8_t P9N2_C_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION = 0 ;
+static const uint8_t P9N2_C_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK = 1 ;
+static const uint8_t P9N2_C_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL = 2 ;
+static const uint8_t P9N2_C_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN = 2 ;
+static const uint8_t P9N2_C_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL = 4 ;
+static const uint8_t P9N2_C_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN = 2 ;
+static const uint8_t P9N2_C_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL = 6 ;
+static const uint8_t P9N2_C_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN = 2 ;
+static const uint8_t P9N2_C_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL = 8 ;
+static const uint8_t P9N2_C_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN = 2 ;
+static const uint8_t P9N2_C_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK = 10 ;
+static const uint8_t P9N2_C_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN = 4 ;
+static const uint8_t P9N2_C_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK = 14 ;
+static const uint8_t P9N2_C_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN = 4 ;
+static const uint8_t P9N2_C_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK = 18 ;
+static const uint8_t P9N2_C_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN = 4 ;
+static const uint8_t P9N2_C_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK = 22 ;
+static const uint8_t P9N2_C_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN = 4 ;
+static const uint8_t P9N2_C_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE = 26 ;
+static const uint8_t P9N2_C_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE = 27 ;
+static const uint8_t P9N2_C_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE = 28 ;
+static const uint8_t P9N2_C_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN = 4 ;
+static const uint8_t P9N2_C_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT = 32 ;
+static const uint8_t P9N2_C_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN = 4 ;
+static const uint8_t P9N2_C_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES = 36 ;
+static const uint8_t P9N2_C_TRACE_TRDATA_CONFIG_9_SPARE_LT = 37 ;
+
+static const uint8_t P9N2_EX_V0_HMER_MALFUNCTION_ALERT = 0 ;
+static const uint8_t P9N2_EX_V0_HMER_CME_REQUEST = 1 ;
+static const uint8_t P9N2_EX_V0_HMER_PROC_RCVY_DONE = 2 ;
+static const uint8_t P9N2_EX_V0_HMER_SPARE_3 = 3 ;
+static const uint8_t P9N2_EX_V0_HMER_TFAC_ERR = 4 ;
+static const uint8_t P9N2_EX_V0_HMER_TFMR_PARITY_ERR = 5 ;
+static const uint8_t P9N2_EX_V0_HMER_SPARE_6 = 6 ;
+static const uint8_t P9N2_EX_V0_HMER_SPARE_7 = 7 ;
+static const uint8_t P9N2_EX_V0_HMER_XSCOM_FAIL = 8 ;
+static const uint8_t P9N2_EX_V0_HMER_XSCOM_DONE = 9 ;
+static const uint8_t P9N2_EX_V0_HMER_SPARE_10 = 10 ;
+static const uint8_t P9N2_EX_V0_HMER_PROC_RCVY_AGAIN = 11 ;
+static const uint8_t P9N2_EX_V0_HMER_SPARE_12 = 12 ;
+static const uint8_t P9N2_EX_V0_HMER_SPARE_13 = 13 ;
+static const uint8_t P9N2_EX_V0_HMER_SPARE_14 = 14 ;
+static const uint8_t P9N2_EX_V0_HMER_SPARE_15 = 15 ;
+static const uint8_t P9N2_EX_V0_HMER_SCOM_FIR_HMI = 16 ;
+static const uint8_t P9N2_EX_V0_HMER_TRIG_FIR_HMI = 17 ;
+static const uint8_t P9N2_EX_V0_HMER_SPARE_18 = 18 ;
+static const uint8_t P9N2_EX_V0_HMER_SPARE_19 = 19 ;
+static const uint8_t P9N2_EX_V0_HMER_HYP_RECOURCE_ERR = 20 ;
+static const uint8_t P9N2_EX_V0_HMER_XSCOM_STATUS = 21 ;
+static const uint8_t P9N2_EX_V0_HMER_XSCOM_STATUS_LEN = 3 ;
+
+static const uint8_t P9N2_EX_L2_V0_HMER_MALFUNCTION_ALERT = 0 ;
+static const uint8_t P9N2_EX_L2_V0_HMER_CME_REQUEST = 1 ;
+static const uint8_t P9N2_EX_L2_V0_HMER_PROC_RCVY_DONE = 2 ;
+static const uint8_t P9N2_EX_L2_V0_HMER_SPARE_3 = 3 ;
+static const uint8_t P9N2_EX_L2_V0_HMER_TFAC_ERR = 4 ;
+static const uint8_t P9N2_EX_L2_V0_HMER_TFMR_PARITY_ERR = 5 ;
+static const uint8_t P9N2_EX_L2_V0_HMER_SPARE_6 = 6 ;
+static const uint8_t P9N2_EX_L2_V0_HMER_SPARE_7 = 7 ;
+static const uint8_t P9N2_EX_L2_V0_HMER_XSCOM_FAIL = 8 ;
+static const uint8_t P9N2_EX_L2_V0_HMER_XSCOM_DONE = 9 ;
+static const uint8_t P9N2_EX_L2_V0_HMER_SPARE_10 = 10 ;
+static const uint8_t P9N2_EX_L2_V0_HMER_PROC_RCVY_AGAIN = 11 ;
+static const uint8_t P9N2_EX_L2_V0_HMER_SPARE_12 = 12 ;
+static const uint8_t P9N2_EX_L2_V0_HMER_SPARE_13 = 13 ;
+static const uint8_t P9N2_EX_L2_V0_HMER_SPARE_14 = 14 ;
+static const uint8_t P9N2_EX_L2_V0_HMER_SPARE_15 = 15 ;
+static const uint8_t P9N2_EX_L2_V0_HMER_SCOM_FIR_HMI = 16 ;
+static const uint8_t P9N2_EX_L2_V0_HMER_TRIG_FIR_HMI = 17 ;
+static const uint8_t P9N2_EX_L2_V0_HMER_SPARE_18 = 18 ;
+static const uint8_t P9N2_EX_L2_V0_HMER_SPARE_19 = 19 ;
+static const uint8_t P9N2_EX_L2_V0_HMER_HYP_RECOURCE_ERR = 20 ;
+static const uint8_t P9N2_EX_L2_V0_HMER_XSCOM_STATUS = 21 ;
+static const uint8_t P9N2_EX_L2_V0_HMER_XSCOM_STATUS_LEN = 3 ;
+
+static const uint8_t P9N2_C_V0_HMER_MALFUNCTION_ALERT = 0 ;
+static const uint8_t P9N2_C_V0_HMER_CME_REQUEST = 1 ;
+static const uint8_t P9N2_C_V0_HMER_PROC_RCVY_DONE = 2 ;
+static const uint8_t P9N2_C_V0_HMER_SPARE_3 = 3 ;
+static const uint8_t P9N2_C_V0_HMER_TFAC_ERR = 4 ;
+static const uint8_t P9N2_C_V0_HMER_TFMR_PARITY_ERR = 5 ;
+static const uint8_t P9N2_C_V0_HMER_SPARE_6 = 6 ;
+static const uint8_t P9N2_C_V0_HMER_SPARE_7 = 7 ;
+static const uint8_t P9N2_C_V0_HMER_XSCOM_FAIL = 8 ;
+static const uint8_t P9N2_C_V0_HMER_XSCOM_DONE = 9 ;
+static const uint8_t P9N2_C_V0_HMER_SPARE_10 = 10 ;
+static const uint8_t P9N2_C_V0_HMER_PROC_RCVY_AGAIN = 11 ;
+static const uint8_t P9N2_C_V0_HMER_SPARE_12 = 12 ;
+static const uint8_t P9N2_C_V0_HMER_SPARE_13 = 13 ;
+static const uint8_t P9N2_C_V0_HMER_SPARE_14 = 14 ;
+static const uint8_t P9N2_C_V0_HMER_SPARE_15 = 15 ;
+static const uint8_t P9N2_C_V0_HMER_SCOM_FIR_HMI = 16 ;
+static const uint8_t P9N2_C_V0_HMER_TRIG_FIR_HMI = 17 ;
+static const uint8_t P9N2_C_V0_HMER_SPARE_18 = 18 ;
+static const uint8_t P9N2_C_V0_HMER_SPARE_19 = 19 ;
+static const uint8_t P9N2_C_V0_HMER_HYP_RECOURCE_ERR = 20 ;
+static const uint8_t P9N2_C_V0_HMER_XSCOM_STATUS = 21 ;
+static const uint8_t P9N2_C_V0_HMER_XSCOM_STATUS_LEN = 3 ;
+
+static const uint8_t P9N2_EX_V1_HMER_MALFUNCTION_ALERT = 0 ;
+static const uint8_t P9N2_EX_V1_HMER_CME_REQUEST = 1 ;
+static const uint8_t P9N2_EX_V1_HMER_PROC_RCVY_DONE = 2 ;
+static const uint8_t P9N2_EX_V1_HMER_SPARE_3 = 3 ;
+static const uint8_t P9N2_EX_V1_HMER_TFAC_ERR = 4 ;
+static const uint8_t P9N2_EX_V1_HMER_TFMR_PARITY_ERR = 5 ;
+static const uint8_t P9N2_EX_V1_HMER_SPARE_6 = 6 ;
+static const uint8_t P9N2_EX_V1_HMER_SPARE_7 = 7 ;
+static const uint8_t P9N2_EX_V1_HMER_XSCOM_FAIL = 8 ;
+static const uint8_t P9N2_EX_V1_HMER_XSCOM_DONE = 9 ;
+static const uint8_t P9N2_EX_V1_HMER_SPARE_10 = 10 ;
+static const uint8_t P9N2_EX_V1_HMER_PROC_RCVY_AGAIN = 11 ;
+static const uint8_t P9N2_EX_V1_HMER_SPARE_12 = 12 ;
+static const uint8_t P9N2_EX_V1_HMER_SPARE_13 = 13 ;
+static const uint8_t P9N2_EX_V1_HMER_SPARE_14 = 14 ;
+static const uint8_t P9N2_EX_V1_HMER_SPARE_15 = 15 ;
+static const uint8_t P9N2_EX_V1_HMER_SCOM_FIR_HMI = 16 ;
+static const uint8_t P9N2_EX_V1_HMER_TRIG_FIR_HMI = 17 ;
+static const uint8_t P9N2_EX_V1_HMER_SPARE_18 = 18 ;
+static const uint8_t P9N2_EX_V1_HMER_SPARE_19 = 19 ;
+static const uint8_t P9N2_EX_V1_HMER_HYP_RECOURCE_ERR = 20 ;
+static const uint8_t P9N2_EX_V1_HMER_XSCOM_STATUS = 21 ;
+static const uint8_t P9N2_EX_V1_HMER_XSCOM_STATUS_LEN = 3 ;
+
+static const uint8_t P9N2_EX_L2_V1_HMER_MALFUNCTION_ALERT = 0 ;
+static const uint8_t P9N2_EX_L2_V1_HMER_CME_REQUEST = 1 ;
+static const uint8_t P9N2_EX_L2_V1_HMER_PROC_RCVY_DONE = 2 ;
+static const uint8_t P9N2_EX_L2_V1_HMER_SPARE_3 = 3 ;
+static const uint8_t P9N2_EX_L2_V1_HMER_TFAC_ERR = 4 ;
+static const uint8_t P9N2_EX_L2_V1_HMER_TFMR_PARITY_ERR = 5 ;
+static const uint8_t P9N2_EX_L2_V1_HMER_SPARE_6 = 6 ;
+static const uint8_t P9N2_EX_L2_V1_HMER_SPARE_7 = 7 ;
+static const uint8_t P9N2_EX_L2_V1_HMER_XSCOM_FAIL = 8 ;
+static const uint8_t P9N2_EX_L2_V1_HMER_XSCOM_DONE = 9 ;
+static const uint8_t P9N2_EX_L2_V1_HMER_SPARE_10 = 10 ;
+static const uint8_t P9N2_EX_L2_V1_HMER_PROC_RCVY_AGAIN = 11 ;
+static const uint8_t P9N2_EX_L2_V1_HMER_SPARE_12 = 12 ;
+static const uint8_t P9N2_EX_L2_V1_HMER_SPARE_13 = 13 ;
+static const uint8_t P9N2_EX_L2_V1_HMER_SPARE_14 = 14 ;
+static const uint8_t P9N2_EX_L2_V1_HMER_SPARE_15 = 15 ;
+static const uint8_t P9N2_EX_L2_V1_HMER_SCOM_FIR_HMI = 16 ;
+static const uint8_t P9N2_EX_L2_V1_HMER_TRIG_FIR_HMI = 17 ;
+static const uint8_t P9N2_EX_L2_V1_HMER_SPARE_18 = 18 ;
+static const uint8_t P9N2_EX_L2_V1_HMER_SPARE_19 = 19 ;
+static const uint8_t P9N2_EX_L2_V1_HMER_HYP_RECOURCE_ERR = 20 ;
+static const uint8_t P9N2_EX_L2_V1_HMER_XSCOM_STATUS = 21 ;
+static const uint8_t P9N2_EX_L2_V1_HMER_XSCOM_STATUS_LEN = 3 ;
+
+static const uint8_t P9N2_C_V1_HMER_MALFUNCTION_ALERT = 0 ;
+static const uint8_t P9N2_C_V1_HMER_CME_REQUEST = 1 ;
+static const uint8_t P9N2_C_V1_HMER_PROC_RCVY_DONE = 2 ;
+static const uint8_t P9N2_C_V1_HMER_SPARE_3 = 3 ;
+static const uint8_t P9N2_C_V1_HMER_TFAC_ERR = 4 ;
+static const uint8_t P9N2_C_V1_HMER_TFMR_PARITY_ERR = 5 ;
+static const uint8_t P9N2_C_V1_HMER_SPARE_6 = 6 ;
+static const uint8_t P9N2_C_V1_HMER_SPARE_7 = 7 ;
+static const uint8_t P9N2_C_V1_HMER_XSCOM_FAIL = 8 ;
+static const uint8_t P9N2_C_V1_HMER_XSCOM_DONE = 9 ;
+static const uint8_t P9N2_C_V1_HMER_SPARE_10 = 10 ;
+static const uint8_t P9N2_C_V1_HMER_PROC_RCVY_AGAIN = 11 ;
+static const uint8_t P9N2_C_V1_HMER_SPARE_12 = 12 ;
+static const uint8_t P9N2_C_V1_HMER_SPARE_13 = 13 ;
+static const uint8_t P9N2_C_V1_HMER_SPARE_14 = 14 ;
+static const uint8_t P9N2_C_V1_HMER_SPARE_15 = 15 ;
+static const uint8_t P9N2_C_V1_HMER_SCOM_FIR_HMI = 16 ;
+static const uint8_t P9N2_C_V1_HMER_TRIG_FIR_HMI = 17 ;
+static const uint8_t P9N2_C_V1_HMER_SPARE_18 = 18 ;
+static const uint8_t P9N2_C_V1_HMER_SPARE_19 = 19 ;
+static const uint8_t P9N2_C_V1_HMER_HYP_RECOURCE_ERR = 20 ;
+static const uint8_t P9N2_C_V1_HMER_XSCOM_STATUS = 21 ;
+static const uint8_t P9N2_C_V1_HMER_XSCOM_STATUS_LEN = 3 ;
+
+static const uint8_t P9N2_EX_L2_V2_HMER_MALFUNCTION_ALERT = 0 ;
+static const uint8_t P9N2_EX_L2_V2_HMER_CME_REQUEST = 1 ;
+static const uint8_t P9N2_EX_L2_V2_HMER_PROC_RCVY_DONE = 2 ;
+static const uint8_t P9N2_EX_L2_V2_HMER_SPARE_3 = 3 ;
+static const uint8_t P9N2_EX_L2_V2_HMER_TFAC_ERR = 4 ;
+static const uint8_t P9N2_EX_L2_V2_HMER_TFMR_PARITY_ERR = 5 ;
+static const uint8_t P9N2_EX_L2_V2_HMER_SPARE_6 = 6 ;
+static const uint8_t P9N2_EX_L2_V2_HMER_SPARE_7 = 7 ;
+static const uint8_t P9N2_EX_L2_V2_HMER_XSCOM_FAIL = 8 ;
+static const uint8_t P9N2_EX_L2_V2_HMER_XSCOM_DONE = 9 ;
+static const uint8_t P9N2_EX_L2_V2_HMER_SPARE_10 = 10 ;
+static const uint8_t P9N2_EX_L2_V2_HMER_PROC_RCVY_AGAIN = 11 ;
+static const uint8_t P9N2_EX_L2_V2_HMER_SPARE_12 = 12 ;
+static const uint8_t P9N2_EX_L2_V2_HMER_SPARE_13 = 13 ;
+static const uint8_t P9N2_EX_L2_V2_HMER_SPARE_14 = 14 ;
+static const uint8_t P9N2_EX_L2_V2_HMER_SPARE_15 = 15 ;
+static const uint8_t P9N2_EX_L2_V2_HMER_SCOM_FIR_HMI = 16 ;
+static const uint8_t P9N2_EX_L2_V2_HMER_TRIG_FIR_HMI = 17 ;
+static const uint8_t P9N2_EX_L2_V2_HMER_SPARE_18 = 18 ;
+static const uint8_t P9N2_EX_L2_V2_HMER_SPARE_19 = 19 ;
+static const uint8_t P9N2_EX_L2_V2_HMER_HYP_RECOURCE_ERR = 20 ;
+static const uint8_t P9N2_EX_L2_V2_HMER_XSCOM_STATUS = 21 ;
+static const uint8_t P9N2_EX_L2_V2_HMER_XSCOM_STATUS_LEN = 3 ;
+
+static const uint8_t P9N2_C_V2_HMER_MALFUNCTION_ALERT = 0 ;
+static const uint8_t P9N2_C_V2_HMER_CME_REQUEST = 1 ;
+static const uint8_t P9N2_C_V2_HMER_PROC_RCVY_DONE = 2 ;
+static const uint8_t P9N2_C_V2_HMER_SPARE_3 = 3 ;
+static const uint8_t P9N2_C_V2_HMER_TFAC_ERR = 4 ;
+static const uint8_t P9N2_C_V2_HMER_TFMR_PARITY_ERR = 5 ;
+static const uint8_t P9N2_C_V2_HMER_SPARE_6 = 6 ;
+static const uint8_t P9N2_C_V2_HMER_SPARE_7 = 7 ;
+static const uint8_t P9N2_C_V2_HMER_XSCOM_FAIL = 8 ;
+static const uint8_t P9N2_C_V2_HMER_XSCOM_DONE = 9 ;
+static const uint8_t P9N2_C_V2_HMER_SPARE_10 = 10 ;
+static const uint8_t P9N2_C_V2_HMER_PROC_RCVY_AGAIN = 11 ;
+static const uint8_t P9N2_C_V2_HMER_SPARE_12 = 12 ;
+static const uint8_t P9N2_C_V2_HMER_SPARE_13 = 13 ;
+static const uint8_t P9N2_C_V2_HMER_SPARE_14 = 14 ;
+static const uint8_t P9N2_C_V2_HMER_SPARE_15 = 15 ;
+static const uint8_t P9N2_C_V2_HMER_SCOM_FIR_HMI = 16 ;
+static const uint8_t P9N2_C_V2_HMER_TRIG_FIR_HMI = 17 ;
+static const uint8_t P9N2_C_V2_HMER_SPARE_18 = 18 ;
+static const uint8_t P9N2_C_V2_HMER_SPARE_19 = 19 ;
+static const uint8_t P9N2_C_V2_HMER_HYP_RECOURCE_ERR = 20 ;
+static const uint8_t P9N2_C_V2_HMER_XSCOM_STATUS = 21 ;
+static const uint8_t P9N2_C_V2_HMER_XSCOM_STATUS_LEN = 3 ;
+
+static const uint8_t P9N2_EX_L2_V3_HMER_MALFUNCTION_ALERT = 0 ;
+static const uint8_t P9N2_EX_L2_V3_HMER_CME_REQUEST = 1 ;
+static const uint8_t P9N2_EX_L2_V3_HMER_PROC_RCVY_DONE = 2 ;
+static const uint8_t P9N2_EX_L2_V3_HMER_SPARE_3 = 3 ;
+static const uint8_t P9N2_EX_L2_V3_HMER_TFAC_ERR = 4 ;
+static const uint8_t P9N2_EX_L2_V3_HMER_TFMR_PARITY_ERR = 5 ;
+static const uint8_t P9N2_EX_L2_V3_HMER_SPARE_6 = 6 ;
+static const uint8_t P9N2_EX_L2_V3_HMER_SPARE_7 = 7 ;
+static const uint8_t P9N2_EX_L2_V3_HMER_XSCOM_FAIL = 8 ;
+static const uint8_t P9N2_EX_L2_V3_HMER_XSCOM_DONE = 9 ;
+static const uint8_t P9N2_EX_L2_V3_HMER_SPARE_10 = 10 ;
+static const uint8_t P9N2_EX_L2_V3_HMER_PROC_RCVY_AGAIN = 11 ;
+static const uint8_t P9N2_EX_L2_V3_HMER_SPARE_12 = 12 ;
+static const uint8_t P9N2_EX_L2_V3_HMER_SPARE_13 = 13 ;
+static const uint8_t P9N2_EX_L2_V3_HMER_SPARE_14 = 14 ;
+static const uint8_t P9N2_EX_L2_V3_HMER_SPARE_15 = 15 ;
+static const uint8_t P9N2_EX_L2_V3_HMER_SCOM_FIR_HMI = 16 ;
+static const uint8_t P9N2_EX_L2_V3_HMER_TRIG_FIR_HMI = 17 ;
+static const uint8_t P9N2_EX_L2_V3_HMER_SPARE_18 = 18 ;
+static const uint8_t P9N2_EX_L2_V3_HMER_SPARE_19 = 19 ;
+static const uint8_t P9N2_EX_L2_V3_HMER_HYP_RECOURCE_ERR = 20 ;
+static const uint8_t P9N2_EX_L2_V3_HMER_XSCOM_STATUS = 21 ;
+static const uint8_t P9N2_EX_L2_V3_HMER_XSCOM_STATUS_LEN = 3 ;
+
+static const uint8_t P9N2_C_V3_HMER_MALFUNCTION_ALERT = 0 ;
+static const uint8_t P9N2_C_V3_HMER_CME_REQUEST = 1 ;
+static const uint8_t P9N2_C_V3_HMER_PROC_RCVY_DONE = 2 ;
+static const uint8_t P9N2_C_V3_HMER_SPARE_3 = 3 ;
+static const uint8_t P9N2_C_V3_HMER_TFAC_ERR = 4 ;
+static const uint8_t P9N2_C_V3_HMER_TFMR_PARITY_ERR = 5 ;
+static const uint8_t P9N2_C_V3_HMER_SPARE_6 = 6 ;
+static const uint8_t P9N2_C_V3_HMER_SPARE_7 = 7 ;
+static const uint8_t P9N2_C_V3_HMER_XSCOM_FAIL = 8 ;
+static const uint8_t P9N2_C_V3_HMER_XSCOM_DONE = 9 ;
+static const uint8_t P9N2_C_V3_HMER_SPARE_10 = 10 ;
+static const uint8_t P9N2_C_V3_HMER_PROC_RCVY_AGAIN = 11 ;
+static const uint8_t P9N2_C_V3_HMER_SPARE_12 = 12 ;
+static const uint8_t P9N2_C_V3_HMER_SPARE_13 = 13 ;
+static const uint8_t P9N2_C_V3_HMER_SPARE_14 = 14 ;
+static const uint8_t P9N2_C_V3_HMER_SPARE_15 = 15 ;
+static const uint8_t P9N2_C_V3_HMER_SCOM_FIR_HMI = 16 ;
+static const uint8_t P9N2_C_V3_HMER_TRIG_FIR_HMI = 17 ;
+static const uint8_t P9N2_C_V3_HMER_SPARE_18 = 18 ;
+static const uint8_t P9N2_C_V3_HMER_SPARE_19 = 19 ;
+static const uint8_t P9N2_C_V3_HMER_HYP_RECOURCE_ERR = 20 ;
+static const uint8_t P9N2_C_V3_HMER_XSCOM_STATUS = 21 ;
+static const uint8_t P9N2_C_V3_HMER_XSCOM_STATUS_LEN = 3 ;
+
+static const uint8_t P9N2_EQ_WRITE_PROTECT_ENABLE_REG_RING_LOCKING = 0 ;
+static const uint8_t P9N2_EQ_WRITE_PROTECT_ENABLE_REG_RESERVED_RING_LOCKING = 1 ;
+
+static const uint8_t P9N2_EX_WRITE_PROTECT_ENABLE_REG_RING_LOCKING = 0 ;
+static const uint8_t P9N2_EX_WRITE_PROTECT_ENABLE_REG_RESERVED_RING_LOCKING = 1 ;
+
+static const uint8_t P9N2_C_WRITE_PROTECT_ENABLE_REG_RING_LOCKING = 0 ;
+static const uint8_t P9N2_C_WRITE_PROTECT_ENABLE_REG_RESERVED_RING_LOCKING = 1 ;
+
+static const uint8_t P9N2_EQ_WRITE_PROTECT_RINGS_REG_RINGS = 0 ;
+static const uint8_t P9N2_EQ_WRITE_PROTECT_RINGS_REG_RINGS_LEN = 16 ;
+
+static const uint8_t P9N2_EX_WRITE_PROTECT_RINGS_REG_RINGS = 0 ;
+static const uint8_t P9N2_EX_WRITE_PROTECT_RINGS_REG_RINGS_LEN = 16 ;
+
+static const uint8_t P9N2_C_WRITE_PROTECT_RINGS_REG_RINGS = 0 ;
+static const uint8_t P9N2_C_WRITE_PROTECT_RINGS_REG_RINGS_LEN = 16 ;
+
+static const uint8_t P9N2_EQ_WR_EPS_REG_TIER1_VALUE = 0 ;
+static const uint8_t P9N2_EQ_WR_EPS_REG_TIER1_VALUE_LEN = 12 ;
+static const uint8_t P9N2_EQ_WR_EPS_REG_TIER2_VALUE = 12 ;
+static const uint8_t P9N2_EQ_WR_EPS_REG_TIER2_VALUE_LEN = 12 ;
+static const uint8_t P9N2_EQ_WR_EPS_REG_DIVIDER_MODE = 24 ;
+static const uint8_t P9N2_EQ_WR_EPS_REG_DIVIDER_MODE_LEN = 4 ;
+static const uint8_t P9N2_EQ_WR_EPS_REG_MODE_SEL = 28 ;
+static const uint8_t P9N2_EQ_WR_EPS_REG_CNT_USE_L2_DIVIDER_EN = 29 ;
+static const uint8_t P9N2_EQ_WR_EPS_REG_L2_STEP_MODE = 30 ;
+static const uint8_t P9N2_EQ_WR_EPS_REG_L2_STEP_MODE_LEN = 4 ;
+
+static const uint8_t P9N2_EX_L2_WR_EPS_REG_TIER1_VALUE = 0 ;
+static const uint8_t P9N2_EX_L2_WR_EPS_REG_TIER1_VALUE_LEN = 12 ;
+static const uint8_t P9N2_EX_L2_WR_EPS_REG_TIER2_VALUE = 12 ;
+static const uint8_t P9N2_EX_L2_WR_EPS_REG_TIER2_VALUE_LEN = 12 ;
+static const uint8_t P9N2_EX_L2_WR_EPS_REG_DIVIDER_MODE = 24 ;
+static const uint8_t P9N2_EX_L2_WR_EPS_REG_DIVIDER_MODE_LEN = 4 ;
+static const uint8_t P9N2_EX_L2_WR_EPS_REG_MODE_SEL = 28 ;
+static const uint8_t P9N2_EX_L2_WR_EPS_REG_CNT_USE_L2_DIVIDER_EN = 29 ;
+static const uint8_t P9N2_EX_L2_WR_EPS_REG_L2_STEP_MODE = 30 ;
+static const uint8_t P9N2_EX_L2_WR_EPS_REG_L2_STEP_MODE_LEN = 4 ;
+
+static const uint8_t P9N2_EQ_XFIR_IN0 = 0 ;
+static const uint8_t P9N2_EQ_XFIR_IN1 = 1 ;
+static const uint8_t P9N2_EQ_XFIR_IN2 = 2 ;
+static const uint8_t P9N2_EQ_XFIR_IN3 = 3 ;
+static const uint8_t P9N2_EQ_XFIR_IN4 = 4 ;
+static const uint8_t P9N2_EQ_XFIR_IN5 = 5 ;
+static const uint8_t P9N2_EQ_XFIR_IN6 = 6 ;
+static const uint8_t P9N2_EQ_XFIR_IN7 = 7 ;
+static const uint8_t P9N2_EQ_XFIR_IN8 = 8 ;
+static const uint8_t P9N2_EQ_XFIR_IN9 = 9 ;
+static const uint8_t P9N2_EQ_XFIR_IN10 = 10 ;
+static const uint8_t P9N2_EQ_XFIR_IN11 = 11 ;
+static const uint8_t P9N2_EQ_XFIR_IN12 = 12 ;
+static const uint8_t P9N2_EQ_XFIR_IN13 = 13 ;
+static const uint8_t P9N2_EQ_XFIR_IN13_LEN = 13 ;
+static const uint8_t P9N2_EQ_XFIR_IN26 = 26 ;
+
+static const uint8_t P9N2_EX_XFIR_IN0 = 0 ;
+static const uint8_t P9N2_EX_XFIR_IN1 = 1 ;
+static const uint8_t P9N2_EX_XFIR_IN2 = 2 ;
+static const uint8_t P9N2_EX_XFIR_IN3 = 3 ;
+static const uint8_t P9N2_EX_XFIR_IN4 = 4 ;
+static const uint8_t P9N2_EX_XFIR_IN5 = 5 ;
+static const uint8_t P9N2_EX_XFIR_IN5_LEN = 21 ;
+static const uint8_t P9N2_EX_XFIR_IN26 = 26 ;
+
+static const uint8_t P9N2_C_XFIR_IN0 = 0 ;
+static const uint8_t P9N2_C_XFIR_IN1 = 1 ;
+static const uint8_t P9N2_C_XFIR_IN2 = 2 ;
+static const uint8_t P9N2_C_XFIR_IN3 = 3 ;
+static const uint8_t P9N2_C_XFIR_IN4 = 4 ;
+static const uint8_t P9N2_C_XFIR_IN5 = 5 ;
+static const uint8_t P9N2_C_XFIR_IN5_LEN = 21 ;
+static const uint8_t P9N2_C_XFIR_IN26 = 26 ;
+
+static const uint8_t P9N2_EQ_XSTOP1_MASK_B = 0 ;
+static const uint8_t P9N2_EQ_XSTOP1_ALIGNED = 1 ;
+static const uint8_t P9N2_EQ_XSTOP1_TRIGGER_OPCG_ON = 2 ;
+static const uint8_t P9N2_EQ_XSTOP1_WAIT_ALLWAYS = 3 ;
+static const uint8_t P9N2_EQ_XSTOP1_PERV = 4 ;
+static const uint8_t P9N2_EQ_XSTOP1_UNIT1 = 5 ;
+static const uint8_t P9N2_EQ_XSTOP1_UNIT2 = 6 ;
+static const uint8_t P9N2_EQ_XSTOP1_UNIT3 = 7 ;
+static const uint8_t P9N2_EQ_XSTOP1_UNIT4 = 8 ;
+static const uint8_t P9N2_EQ_XSTOP1_UNIT5 = 9 ;
+static const uint8_t P9N2_EQ_XSTOP1_UNIT6 = 10 ;
+static const uint8_t P9N2_EQ_XSTOP1_UNIT7 = 11 ;
+static const uint8_t P9N2_EQ_XSTOP1_UNIT8 = 12 ;
+static const uint8_t P9N2_EQ_XSTOP1_UNIT9 = 13 ;
+static const uint8_t P9N2_EQ_XSTOP1_UNIT10 = 14 ;
+static const uint8_t P9N2_EQ_XSTOP1_WAIT_CYCLES = 48 ;
+static const uint8_t P9N2_EQ_XSTOP1_WAIT_CYCLES_LEN = 12 ;
+
+static const uint8_t P9N2_EX_XSTOP1_MASK_B = 0 ;
+static const uint8_t P9N2_EX_XSTOP1_ALIGNED = 1 ;
+static const uint8_t P9N2_EX_XSTOP1_TRIGGER_OPCG_ON = 2 ;
+static const uint8_t P9N2_EX_XSTOP1_WAIT_ALLWAYS = 3 ;
+static const uint8_t P9N2_EX_XSTOP1_PERV = 4 ;
+static const uint8_t P9N2_EX_XSTOP1_UNIT1 = 5 ;
+static const uint8_t P9N2_EX_XSTOP1_UNIT2 = 6 ;
+static const uint8_t P9N2_EX_XSTOP1_UNIT3 = 7 ;
+static const uint8_t P9N2_EX_XSTOP1_UNIT4 = 8 ;
+static const uint8_t P9N2_EX_XSTOP1_UNIT5 = 9 ;
+static const uint8_t P9N2_EX_XSTOP1_UNIT6 = 10 ;
+static const uint8_t P9N2_EX_XSTOP1_UNIT7 = 11 ;
+static const uint8_t P9N2_EX_XSTOP1_UNIT8 = 12 ;
+static const uint8_t P9N2_EX_XSTOP1_UNIT9 = 13 ;
+static const uint8_t P9N2_EX_XSTOP1_UNIT10 = 14 ;
+static const uint8_t P9N2_EX_XSTOP1_WAIT_CYCLES = 48 ;
+static const uint8_t P9N2_EX_XSTOP1_WAIT_CYCLES_LEN = 12 ;
+
+static const uint8_t P9N2_C_XSTOP1_MASK_B = 0 ;
+static const uint8_t P9N2_C_XSTOP1_ALIGNED = 1 ;
+static const uint8_t P9N2_C_XSTOP1_TRIGGER_OPCG_ON = 2 ;
+static const uint8_t P9N2_C_XSTOP1_WAIT_ALLWAYS = 3 ;
+static const uint8_t P9N2_C_XSTOP1_PERV = 4 ;
+static const uint8_t P9N2_C_XSTOP1_UNIT1 = 5 ;
+static const uint8_t P9N2_C_XSTOP1_UNIT2 = 6 ;
+static const uint8_t P9N2_C_XSTOP1_UNIT3 = 7 ;
+static const uint8_t P9N2_C_XSTOP1_UNIT4 = 8 ;
+static const uint8_t P9N2_C_XSTOP1_UNIT5 = 9 ;
+static const uint8_t P9N2_C_XSTOP1_UNIT6 = 10 ;
+static const uint8_t P9N2_C_XSTOP1_UNIT7 = 11 ;
+static const uint8_t P9N2_C_XSTOP1_UNIT8 = 12 ;
+static const uint8_t P9N2_C_XSTOP1_UNIT9 = 13 ;
+static const uint8_t P9N2_C_XSTOP1_UNIT10 = 14 ;
+static const uint8_t P9N2_C_XSTOP1_WAIT_CYCLES = 48 ;
+static const uint8_t P9N2_C_XSTOP1_WAIT_CYCLES_LEN = 12 ;
+
+static const uint8_t P9N2_EQ_XSTOP2_MASK_B = 0 ;
+static const uint8_t P9N2_EQ_XSTOP2_ALIGNED = 1 ;
+static const uint8_t P9N2_EQ_XSTOP2_TRIGGER_OPCG_ON = 2 ;
+static const uint8_t P9N2_EQ_XSTOP2_WAIT_ALLWAYS = 3 ;
+static const uint8_t P9N2_EQ_XSTOP2_PERV = 4 ;
+static const uint8_t P9N2_EQ_XSTOP2_UNIT1 = 5 ;
+static const uint8_t P9N2_EQ_XSTOP2_UNIT2 = 6 ;
+static const uint8_t P9N2_EQ_XSTOP2_UNIT3 = 7 ;
+static const uint8_t P9N2_EQ_XSTOP2_UNIT4 = 8 ;
+static const uint8_t P9N2_EQ_XSTOP2_UNIT5 = 9 ;
+static const uint8_t P9N2_EQ_XSTOP2_UNIT6 = 10 ;
+static const uint8_t P9N2_EQ_XSTOP2_UNIT7 = 11 ;
+static const uint8_t P9N2_EQ_XSTOP2_UNIT8 = 12 ;
+static const uint8_t P9N2_EQ_XSTOP2_UNIT9 = 13 ;
+static const uint8_t P9N2_EQ_XSTOP2_UNIT10 = 14 ;
+static const uint8_t P9N2_EQ_XSTOP2_WAIT_CYCLES = 48 ;
+static const uint8_t P9N2_EQ_XSTOP2_WAIT_CYCLES_LEN = 12 ;
+
+static const uint8_t P9N2_EX_XSTOP2_MASK_B = 0 ;
+static const uint8_t P9N2_EX_XSTOP2_ALIGNED = 1 ;
+static const uint8_t P9N2_EX_XSTOP2_TRIGGER_OPCG_ON = 2 ;
+static const uint8_t P9N2_EX_XSTOP2_WAIT_ALLWAYS = 3 ;
+static const uint8_t P9N2_EX_XSTOP2_PERV = 4 ;
+static const uint8_t P9N2_EX_XSTOP2_UNIT1 = 5 ;
+static const uint8_t P9N2_EX_XSTOP2_UNIT2 = 6 ;
+static const uint8_t P9N2_EX_XSTOP2_UNIT3 = 7 ;
+static const uint8_t P9N2_EX_XSTOP2_UNIT4 = 8 ;
+static const uint8_t P9N2_EX_XSTOP2_UNIT5 = 9 ;
+static const uint8_t P9N2_EX_XSTOP2_UNIT6 = 10 ;
+static const uint8_t P9N2_EX_XSTOP2_UNIT7 = 11 ;
+static const uint8_t P9N2_EX_XSTOP2_UNIT8 = 12 ;
+static const uint8_t P9N2_EX_XSTOP2_UNIT9 = 13 ;
+static const uint8_t P9N2_EX_XSTOP2_UNIT10 = 14 ;
+static const uint8_t P9N2_EX_XSTOP2_WAIT_CYCLES = 48 ;
+static const uint8_t P9N2_EX_XSTOP2_WAIT_CYCLES_LEN = 12 ;
+
+static const uint8_t P9N2_C_XSTOP2_MASK_B = 0 ;
+static const uint8_t P9N2_C_XSTOP2_ALIGNED = 1 ;
+static const uint8_t P9N2_C_XSTOP2_TRIGGER_OPCG_ON = 2 ;
+static const uint8_t P9N2_C_XSTOP2_WAIT_ALLWAYS = 3 ;
+static const uint8_t P9N2_C_XSTOP2_PERV = 4 ;
+static const uint8_t P9N2_C_XSTOP2_UNIT1 = 5 ;
+static const uint8_t P9N2_C_XSTOP2_UNIT2 = 6 ;
+static const uint8_t P9N2_C_XSTOP2_UNIT3 = 7 ;
+static const uint8_t P9N2_C_XSTOP2_UNIT4 = 8 ;
+static const uint8_t P9N2_C_XSTOP2_UNIT5 = 9 ;
+static const uint8_t P9N2_C_XSTOP2_UNIT6 = 10 ;
+static const uint8_t P9N2_C_XSTOP2_UNIT7 = 11 ;
+static const uint8_t P9N2_C_XSTOP2_UNIT8 = 12 ;
+static const uint8_t P9N2_C_XSTOP2_UNIT9 = 13 ;
+static const uint8_t P9N2_C_XSTOP2_UNIT10 = 14 ;
+static const uint8_t P9N2_C_XSTOP2_WAIT_CYCLES = 48 ;
+static const uint8_t P9N2_C_XSTOP2_WAIT_CYCLES_LEN = 12 ;
+
+static const uint8_t P9N2_EQ_XSTOP3_MASK_B = 0 ;
+static const uint8_t P9N2_EQ_XSTOP3_ALIGNED = 1 ;
+static const uint8_t P9N2_EQ_XSTOP3_TRIGGER_OPCG_ON = 2 ;
+static const uint8_t P9N2_EQ_XSTOP3_WAIT_ALLWAYS = 3 ;
+static const uint8_t P9N2_EQ_XSTOP3_PERV = 4 ;
+static const uint8_t P9N2_EQ_XSTOP3_UNIT1 = 5 ;
+static const uint8_t P9N2_EQ_XSTOP3_UNIT2 = 6 ;
+static const uint8_t P9N2_EQ_XSTOP3_UNIT3 = 7 ;
+static const uint8_t P9N2_EQ_XSTOP3_UNIT4 = 8 ;
+static const uint8_t P9N2_EQ_XSTOP3_UNIT5 = 9 ;
+static const uint8_t P9N2_EQ_XSTOP3_UNIT6 = 10 ;
+static const uint8_t P9N2_EQ_XSTOP3_UNIT7 = 11 ;
+static const uint8_t P9N2_EQ_XSTOP3_UNIT8 = 12 ;
+static const uint8_t P9N2_EQ_XSTOP3_UNIT9 = 13 ;
+static const uint8_t P9N2_EQ_XSTOP3_UNIT10 = 14 ;
+static const uint8_t P9N2_EQ_XSTOP3_WAIT_CYCLES = 48 ;
+static const uint8_t P9N2_EQ_XSTOP3_WAIT_CYCLES_LEN = 12 ;
+
+static const uint8_t P9N2_EX_XSTOP3_MASK_B = 0 ;
+static const uint8_t P9N2_EX_XSTOP3_ALIGNED = 1 ;
+static const uint8_t P9N2_EX_XSTOP3_TRIGGER_OPCG_ON = 2 ;
+static const uint8_t P9N2_EX_XSTOP3_WAIT_ALLWAYS = 3 ;
+static const uint8_t P9N2_EX_XSTOP3_PERV = 4 ;
+static const uint8_t P9N2_EX_XSTOP3_UNIT1 = 5 ;
+static const uint8_t P9N2_EX_XSTOP3_UNIT2 = 6 ;
+static const uint8_t P9N2_EX_XSTOP3_UNIT3 = 7 ;
+static const uint8_t P9N2_EX_XSTOP3_UNIT4 = 8 ;
+static const uint8_t P9N2_EX_XSTOP3_UNIT5 = 9 ;
+static const uint8_t P9N2_EX_XSTOP3_UNIT6 = 10 ;
+static const uint8_t P9N2_EX_XSTOP3_UNIT7 = 11 ;
+static const uint8_t P9N2_EX_XSTOP3_UNIT8 = 12 ;
+static const uint8_t P9N2_EX_XSTOP3_UNIT9 = 13 ;
+static const uint8_t P9N2_EX_XSTOP3_UNIT10 = 14 ;
+static const uint8_t P9N2_EX_XSTOP3_WAIT_CYCLES = 48 ;
+static const uint8_t P9N2_EX_XSTOP3_WAIT_CYCLES_LEN = 12 ;
+
+static const uint8_t P9N2_C_XSTOP3_MASK_B = 0 ;
+static const uint8_t P9N2_C_XSTOP3_ALIGNED = 1 ;
+static const uint8_t P9N2_C_XSTOP3_TRIGGER_OPCG_ON = 2 ;
+static const uint8_t P9N2_C_XSTOP3_WAIT_ALLWAYS = 3 ;
+static const uint8_t P9N2_C_XSTOP3_PERV = 4 ;
+static const uint8_t P9N2_C_XSTOP3_UNIT1 = 5 ;
+static const uint8_t P9N2_C_XSTOP3_UNIT2 = 6 ;
+static const uint8_t P9N2_C_XSTOP3_UNIT3 = 7 ;
+static const uint8_t P9N2_C_XSTOP3_UNIT4 = 8 ;
+static const uint8_t P9N2_C_XSTOP3_UNIT5 = 9 ;
+static const uint8_t P9N2_C_XSTOP3_UNIT6 = 10 ;
+static const uint8_t P9N2_C_XSTOP3_UNIT7 = 11 ;
+static const uint8_t P9N2_C_XSTOP3_UNIT8 = 12 ;
+static const uint8_t P9N2_C_XSTOP3_UNIT9 = 13 ;
+static const uint8_t P9N2_C_XSTOP3_UNIT10 = 14 ;
+static const uint8_t P9N2_C_XSTOP3_WAIT_CYCLES = 48 ;
+static const uint8_t P9N2_C_XSTOP3_WAIT_CYCLES_LEN = 12 ;
+
+static const uint8_t P9N2_EQ_XSTOP_INTERRUPT_REG_XSTOP = 0 ;
+
+static const uint8_t P9N2_EX_XSTOP_INTERRUPT_REG_XSTOP = 0 ;
+
+static const uint8_t P9N2_C_XSTOP_INTERRUPT_REG_XSTOP = 0 ;
+
+static const uint8_t P9N2_EQ_XTRA_TRACE_MODE_DATA = 0 ;
+static const uint8_t P9N2_EQ_XTRA_TRACE_MODE_DATA_LEN = 42 ;
+
+static const uint8_t P9N2_EX_XTRA_TRACE_MODE_DATA = 0 ;
+static const uint8_t P9N2_EX_XTRA_TRACE_MODE_DATA_LEN = 42 ;
+
+static const uint8_t P9N2_C_XTRA_TRACE_MODE_DATA = 0 ;
+static const uint8_t P9N2_C_XTRA_TRACE_MODE_DATA_LEN = 42 ;
+
+#endif
+
diff --git a/src/import/chips/p9/common/include/p9n2_xbus_scom_addresses.H b/src/import/chips/p9/common/include/p9n2_xbus_scom_addresses.H
new file mode 100644
index 000000000..89d66f70c
--- /dev/null
+++ b/src/import/chips/p9/common/include/p9n2_xbus_scom_addresses.H
@@ -0,0 +1,18542 @@
+/* IBM_PROLOG_BEGIN_TAG */
+/* This is an automatically generated prolog. */
+/* */
+/* $Source: src/import/chips/p9/common/include/p9n2_xbus_scom_addresses.H $ */
+/* */
+/* OpenPOWER HostBoot Project */
+/* */
+/* Contributors Listed Below - COPYRIGHT 2017 */
+/* [+] International Business Machines Corp. */
+/* */
+/* */
+/* Licensed under the Apache License, Version 2.0 (the "License"); */
+/* you may not use this file except in compliance with the License. */
+/* You may obtain a copy of the License at */
+/* */
+/* http://www.apache.org/licenses/LICENSE-2.0 */
+/* */
+/* Unless required by applicable law or agreed to in writing, software */
+/* distributed under the License is distributed on an "AS IS" BASIS, */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */
+/* implied. See the License for the specific language governing */
+/* permissions and limitations under the License. */
+/* */
+/* IBM_PROLOG_END_TAG */
+///
+/// @file p9_xbus_scom_addresses.H
+/// @brief Defines constants for scom addresses
+///
+// *HWP HWP Owner: Ben Gass <bgass@us.ibm.com>
+// *HWP FW Owner: Thi Tran <thi@us.ibm.com>
+// *HWP Team: SOA
+// *HWP Level: 1
+// *HWP Consumed by: FSP:HB:HS:OCC:SBE:CME:SGPE:PGPE:FPPE:IPPE
+
+/*---------------------------------------------------------------
+ *
+ *---------------------------------------------------------------
+ *
+ *
+ *---------------------------------------------------------------
+ */
+
+#ifndef __P9N2_XBUS_SCOM_ADDRESSES_H
+#define __P9N2_XBUS_SCOM_ADDRESSES_H
+
+#include <stdint.h>
+
+
+static const uint64_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_CSCR = 0x0601084Aull;
+
+static const uint64_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_CSCR_CLEAR = 0x0601084Bull;
+
+static const uint64_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_CSCR_OR = 0x0601084Cull;
+
+
+static const uint64_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_PPE_FIR_MASK_REG = 0x06010843ull;
+
+static const uint64_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_PPE_FIR_MASK_REG_AND = 0x06010844ull;
+
+static const uint64_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_PPE_FIR_MASK_REG_OR = 0x06010845ull;
+
+
+static const uint64_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_PPE_FIR_REG = 0x06010840ull;
+
+static const uint64_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_PPE_FIR_REG_AND = 0x06010841ull;
+
+static const uint64_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_PPE_FIR_REG_OR = 0x06010842ull;
+
+
+static const uint64_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_SCOM_PPE_FLAGS = 0x06010863ull;
+
+static const uint64_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_SCOM_PPE_FLAGS_OR = 0x06010864ull;
+
+static const uint64_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_SCOM_PPE_FLAGS_CLEAR = 0x06010865ull;
+
+
+static const uint64_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_CSAR = 0x0601084Dull;
+
+
+static const uint64_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_CSDR = 0x0601084Eull;
+
+
+static const uint64_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_1 = 0x060107C1ull;
+
+
+static const uint64_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_2 = 0x060107C2ull;
+
+
+static const uint64_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_3 = 0x060107C3ull;
+
+
+static const uint64_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_1 = 0x060107C4ull;
+
+
+static const uint64_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_2 = 0x060107C5ull;
+
+
+static const uint64_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_3 = 0x060107C6ull;
+
+
+static const uint64_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_MODE_REG = 0x060107C0ull;
+
+
+static const uint64_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_MODE_REG_2 = 0x060107CFull;
+
+
+static const uint64_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_0 = 0x060107CDull;
+
+
+static const uint64_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_1 = 0x060107CEull;
+
+
+static const uint64_t P9N2_XBUS_PERV_C0_S0_P0_E9_DEBUG_TRACE_CONTROL = 0x060107D0ull;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG = 0x06010C03ull;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG = 0x06011003ull;
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_AND = 0x06010C04ull;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_AND = 0x06011004ull;
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_OR = 0x06010C05ull;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_OR = 0x06011005ull;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG = 0x06010C00ull;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG = 0x06011000ull;
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_AND = 0x06010C01ull;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_AND = 0x06011001ull;
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_OR = 0x06010C02ull;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_OR = 0x06011002ull;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_FIR_ACTION0_REG = 0x06010C06ull;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_FIR_ACTION0_REG = 0x06011006ull;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_FIR_ACTION1_REG = 0x06010C07ull;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_FIR_ACTION1_REG = 0x06011007ull;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_FIR_WOF_REG = 0x06010C08ull;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_FIR_WOF_REG = 0x06011008ull;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL = 0x8003000D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL = 0x8003000D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL = 0x8002480D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL = 0x8002480D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_E_PL = 0x8003080D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_E_PL = 0x8003080D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL = 0x8002500D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL = 0x8002500D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_E_PL = 0x8003100D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_E_PL = 0x8003100D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL = 0x8002580D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL = 0x8002580D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL5_EO_PL = 0x8002600D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL5_EO_PL = 0x8002600D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL = 0x8002400D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL = 0x8002400D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL = 0x8002200D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL = 0x8002200D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_E_PL = 0x8002C00D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_E_PL = 0x8002C00D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE2_EO_PL = 0x8002280D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE2_EO_PL = 0x8002280D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE2_E_PL = 0x8002C80D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE2_E_PL = 0x8002C80D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL = 0x8002300D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL = 0x8002300D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT1_EO_PL = 0x8002680D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT1_EO_PL = 0x8002680D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL = 0x8002700D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL = 0x8002700D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL = 0x8002780D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL = 0x8002780D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL = 0x8000080D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL = 0x8000080D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_E_PL = 0x8000800D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_E_PL = 0x8000800D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL = 0x8000100D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL = 0x8000100D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_E_PL = 0x8000880D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_E_PL = 0x8000880D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_EO_PL = 0x8000180D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_EO_PL = 0x8000180D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_E_PL = 0x8000900D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_E_PL = 0x8000900D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_EO_PL = 0x8000200D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_EO_PL = 0x8000200D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_E_PL = 0x8000980D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_E_PL = 0x8000980D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL = 0x8000280D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL = 0x8000280D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_E_PL = 0x8000A00D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_E_PL = 0x8000A00D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_EO_PL = 0x8000300D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_EO_PL = 0x8000300D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_E_PL = 0x8000A80D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_E_PL = 0x8000A80D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL7_EO_PL = 0x8000380D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL7_EO_PL = 0x8000380D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL7_E_PL = 0x8000B00D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL7_E_PL = 0x8000B00D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL8_EO_PL = 0x8000400D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL8_EO_PL = 0x8000400D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL8_E_PL = 0x8000B80D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL8_E_PL = 0x8000B80D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL9_E_PL = 0x8000C00D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL9_E_PL = 0x8000C00D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL = 0x8000000D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x8000000D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_FIR_ERROR_INJECT_PL = 0x8002180D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_FIR_ERROR_INJECT_PL = 0x8002180D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_FIR_MASK_PL = 0x8002100D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_FIR_MASK_PL = 0x8002100D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_FIR_PL = 0x8002080D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_FIR_PL = 0x8002080D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_SPARE_MODE_PL = 0x8002000D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_SPARE_MODE_PL = 0x8002000D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL = 0x8003000F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL = 0x8003000F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL = 0x8002480F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL = 0x8002480F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_E_PL = 0x8003080F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_E_PL = 0x8003080F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL = 0x8002500F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL = 0x8002500F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_E_PL = 0x8003100F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_E_PL = 0x8003100F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL = 0x8002580F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL = 0x8002580F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL5_EO_PL = 0x8002600F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL5_EO_PL = 0x8002600F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL = 0x8002400F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL = 0x8002400F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL = 0x8002200F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL = 0x8002200F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_E_PL = 0x8002C00F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_E_PL = 0x8002C00F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE2_EO_PL = 0x8002280F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE2_EO_PL = 0x8002280F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE2_E_PL = 0x8002C80F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE2_E_PL = 0x8002C80F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL = 0x8002300F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL = 0x8002300F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT1_EO_PL = 0x8002680F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT1_EO_PL = 0x8002680F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL = 0x8002700F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL = 0x8002700F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL = 0x8002780F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL = 0x8002780F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL = 0x8000080F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL = 0x8000080F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_E_PL = 0x8000800F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_E_PL = 0x8000800F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL = 0x8000100F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL = 0x8000100F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_E_PL = 0x8000880F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_E_PL = 0x8000880F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_EO_PL = 0x8000180F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_EO_PL = 0x8000180F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_E_PL = 0x8000900F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_E_PL = 0x8000900F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_EO_PL = 0x8000200F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_EO_PL = 0x8000200F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_E_PL = 0x8000980F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_E_PL = 0x8000980F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL = 0x8000280F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL = 0x8000280F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_E_PL = 0x8000A00F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_E_PL = 0x8000A00F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_EO_PL = 0x8000300F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_EO_PL = 0x8000300F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_E_PL = 0x8000A80F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_E_PL = 0x8000A80F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL7_EO_PL = 0x8000380F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL7_EO_PL = 0x8000380F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL7_E_PL = 0x8000B00F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL7_E_PL = 0x8000B00F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL8_EO_PL = 0x8000400F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL8_EO_PL = 0x8000400F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL8_E_PL = 0x8000B80F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL8_E_PL = 0x8000B80F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL9_E_PL = 0x8000C00F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL9_E_PL = 0x8000C00F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL = 0x8000000F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x8000000F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_FIR_ERROR_INJECT_PL = 0x8002180F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_FIR_ERROR_INJECT_PL = 0x8002180F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_FIR_MASK_PL = 0x8002100F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_FIR_MASK_PL = 0x8002100F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_FIR_PL = 0x8002080F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_FIR_PL = 0x8002080F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_SPARE_MODE_PL = 0x8002000F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_SPARE_MODE_PL = 0x8002000F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL = 0x8003000E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL = 0x8003000E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL = 0x8002480E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL = 0x8002480E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_E_PL = 0x8003080E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_E_PL = 0x8003080E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL = 0x8002500E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL = 0x8002500E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_E_PL = 0x8003100E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_E_PL = 0x8003100E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL = 0x8002580E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL = 0x8002580E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL5_EO_PL = 0x8002600E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL5_EO_PL = 0x8002600E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL = 0x8002400E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL = 0x8002400E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL = 0x8002200E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL = 0x8002200E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_E_PL = 0x8002C00E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_E_PL = 0x8002C00E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE2_EO_PL = 0x8002280E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE2_EO_PL = 0x8002280E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE2_E_PL = 0x8002C80E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE2_E_PL = 0x8002C80E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL = 0x8002300E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL = 0x8002300E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT1_EO_PL = 0x8002680E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT1_EO_PL = 0x8002680E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL = 0x8002700E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL = 0x8002700E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL = 0x8002780E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL = 0x8002780E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL = 0x8000080E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL = 0x8000080E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_E_PL = 0x8000800E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_E_PL = 0x8000800E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL = 0x8000100E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL = 0x8000100E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_E_PL = 0x8000880E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_E_PL = 0x8000880E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_EO_PL = 0x8000180E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_EO_PL = 0x8000180E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_E_PL = 0x8000900E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_E_PL = 0x8000900E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_EO_PL = 0x8000200E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_EO_PL = 0x8000200E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_E_PL = 0x8000980E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_E_PL = 0x8000980E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL = 0x8000280E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL = 0x8000280E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_E_PL = 0x8000A00E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_E_PL = 0x8000A00E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_EO_PL = 0x8000300E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_EO_PL = 0x8000300E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_E_PL = 0x8000A80E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_E_PL = 0x8000A80E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL7_EO_PL = 0x8000380E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL7_EO_PL = 0x8000380E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL7_E_PL = 0x8000B00E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL7_E_PL = 0x8000B00E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL8_EO_PL = 0x8000400E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL8_EO_PL = 0x8000400E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL8_E_PL = 0x8000B80E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL8_E_PL = 0x8000B80E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL9_E_PL = 0x8000C00E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL9_E_PL = 0x8000C00E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL = 0x8000000E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x8000000E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_FIR_ERROR_INJECT_PL = 0x8002180E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_FIR_ERROR_INJECT_PL = 0x8002180E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_FIR_MASK_PL = 0x8002100E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_FIR_MASK_PL = 0x8002100E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_FIR_PL = 0x8002080E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_FIR_PL = 0x8002080E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_SPARE_MODE_PL = 0x8002000E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_SPARE_MODE_PL = 0x8002000E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL = 0x8003001006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL = 0x800300100601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL = 0x8002481006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL = 0x800248100601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_E_PL = 0x8003081006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_E_PL = 0x800308100601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL = 0x8002501006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL = 0x800250100601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_E_PL = 0x8003101006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_E_PL = 0x800310100601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL = 0x8002581006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL = 0x800258100601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL5_EO_PL = 0x8002601006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL5_EO_PL = 0x800260100601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL = 0x8002401006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL = 0x800240100601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL = 0x8002201006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL = 0x800220100601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_E_PL = 0x8002C01006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_E_PL = 0x8002C0100601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE2_EO_PL = 0x8002281006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE2_EO_PL = 0x800228100601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE2_E_PL = 0x8002C81006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE2_E_PL = 0x8002C8100601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL = 0x8002301006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL = 0x800230100601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT1_EO_PL = 0x8002681006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT1_EO_PL = 0x800268100601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL = 0x8002701006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL = 0x800270100601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL = 0x8002781006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL = 0x800278100601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL = 0x8000081006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL = 0x800008100601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_E_PL = 0x8000801006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_E_PL = 0x800080100601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL = 0x8000101006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL = 0x800010100601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_E_PL = 0x8000881006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_E_PL = 0x800088100601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL3_EO_PL = 0x8000181006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL3_EO_PL = 0x800018100601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL3_E_PL = 0x8000901006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL3_E_PL = 0x800090100601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_EO_PL = 0x8000201006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_EO_PL = 0x800020100601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_E_PL = 0x8000981006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_E_PL = 0x800098100601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL = 0x8000281006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL = 0x800028100601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_E_PL = 0x8000A01006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_E_PL = 0x8000A0100601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL6_EO_PL = 0x8000301006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL6_EO_PL = 0x800030100601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL6_E_PL = 0x8000A81006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL6_E_PL = 0x8000A8100601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL7_EO_PL = 0x8000381006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL7_EO_PL = 0x800038100601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL7_E_PL = 0x8000B01006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL7_E_PL = 0x8000B0100601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL8_EO_PL = 0x8000401006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL8_EO_PL = 0x800040100601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL8_E_PL = 0x8000B81006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL8_E_PL = 0x8000B8100601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL9_E_PL = 0x8000C01006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL9_E_PL = 0x8000C0100601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL = 0x8000001006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x800000100601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_FIR_ERROR_INJECT_PL = 0x8002181006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_FIR_ERROR_INJECT_PL = 0x800218100601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_FIR_MASK_PL = 0x8002101006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_FIR_MASK_PL = 0x800210100601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_FIR_PL = 0x8002081006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_FIR_PL = 0x800208100601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_SPARE_MODE_PL = 0x8002001006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_SPARE_MODE_PL = 0x800200100601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL = 0x8003000B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL = 0x8003000B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL = 0x8002480B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL = 0x8002480B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_E_PL = 0x8003080B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_E_PL = 0x8003080B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL = 0x8002500B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL = 0x8002500B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_E_PL = 0x8003100B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_E_PL = 0x8003100B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL = 0x8002580B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL = 0x8002580B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL5_EO_PL = 0x8002600B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL5_EO_PL = 0x8002600B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL = 0x8002400B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL = 0x8002400B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL = 0x8002200B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL = 0x8002200B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE1_E_PL = 0x8002C00B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE1_E_PL = 0x8002C00B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE2_EO_PL = 0x8002280B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE2_EO_PL = 0x8002280B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE2_E_PL = 0x8002C80B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE2_E_PL = 0x8002C80B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL = 0x8002300B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL = 0x8002300B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT1_EO_PL = 0x8002680B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT1_EO_PL = 0x8002680B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL = 0x8002700B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL = 0x8002700B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL = 0x8002780B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL = 0x8002780B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL = 0x8000080B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL = 0x8000080B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_E_PL = 0x8000800B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_E_PL = 0x8000800B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_EO_PL = 0x8000100B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_EO_PL = 0x8000100B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_E_PL = 0x8000880B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_E_PL = 0x8000880B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL3_EO_PL = 0x8000180B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL3_EO_PL = 0x8000180B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL3_E_PL = 0x8000900B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL3_E_PL = 0x8000900B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_EO_PL = 0x8000200B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_EO_PL = 0x8000200B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_E_PL = 0x8000980B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_E_PL = 0x8000980B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL = 0x8000280B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL = 0x8000280B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_E_PL = 0x8000A00B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_E_PL = 0x8000A00B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL6_EO_PL = 0x8000300B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL6_EO_PL = 0x8000300B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL6_E_PL = 0x8000A80B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL6_E_PL = 0x8000A80B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL7_EO_PL = 0x8000380B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL7_EO_PL = 0x8000380B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL7_E_PL = 0x8000B00B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL7_E_PL = 0x8000B00B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL8_EO_PL = 0x8000400B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL8_EO_PL = 0x8000400B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL8_E_PL = 0x8000B80B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL8_E_PL = 0x8000B80B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL9_E_PL = 0x8000C00B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL9_E_PL = 0x8000C00B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL = 0x8000000B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x8000000B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_FIR_ERROR_INJECT_PL = 0x8002180B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_FIR_ERROR_INJECT_PL = 0x8002180B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_FIR_MASK_PL = 0x8002100B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_FIR_MASK_PL = 0x8002100B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_FIR_PL = 0x8002080B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_FIR_PL = 0x8002080B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_SPARE_MODE_PL = 0x8002000B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_SPARE_MODE_PL = 0x8002000B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL = 0x8003000906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL = 0x800300090601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL = 0x8002480906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL = 0x800248090601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_E_PL = 0x8003080906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_E_PL = 0x800308090601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL = 0x8002500906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL = 0x800250090601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_E_PL = 0x8003100906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_E_PL = 0x800310090601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL = 0x8002580906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL = 0x800258090601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL5_EO_PL = 0x8002600906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL5_EO_PL = 0x800260090601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL = 0x8002400906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL = 0x800240090601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL = 0x8002200906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL = 0x800220090601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE1_E_PL = 0x8002C00906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE1_E_PL = 0x8002C0090601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE2_EO_PL = 0x8002280906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE2_EO_PL = 0x800228090601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE2_E_PL = 0x8002C80906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE2_E_PL = 0x8002C8090601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL = 0x8002300906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL = 0x800230090601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT1_EO_PL = 0x8002680906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT1_EO_PL = 0x800268090601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL = 0x8002700906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL = 0x800270090601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL = 0x8002780906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL = 0x800278090601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL = 0x8000080906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL = 0x800008090601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_E_PL = 0x8000800906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_E_PL = 0x800080090601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_EO_PL = 0x8000100906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_EO_PL = 0x800010090601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_E_PL = 0x8000880906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_E_PL = 0x800088090601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL3_EO_PL = 0x8000180906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL3_EO_PL = 0x800018090601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL3_E_PL = 0x8000900906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL3_E_PL = 0x800090090601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_EO_PL = 0x8000200906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_EO_PL = 0x800020090601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_E_PL = 0x8000980906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_E_PL = 0x800098090601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL = 0x8000280906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL = 0x800028090601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_E_PL = 0x8000A00906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_E_PL = 0x8000A0090601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL6_EO_PL = 0x8000300906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL6_EO_PL = 0x800030090601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL6_E_PL = 0x8000A80906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL6_E_PL = 0x8000A8090601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL7_EO_PL = 0x8000380906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL7_EO_PL = 0x800038090601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL7_E_PL = 0x8000B00906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL7_E_PL = 0x8000B0090601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL8_EO_PL = 0x8000400906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL8_EO_PL = 0x800040090601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL8_E_PL = 0x8000B80906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL8_E_PL = 0x8000B8090601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL9_E_PL = 0x8000C00906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL9_E_PL = 0x8000C0090601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL = 0x8000000906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x800000090601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_FIR_ERROR_INJECT_PL = 0x8002180906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_FIR_ERROR_INJECT_PL = 0x800218090601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_FIR_MASK_PL = 0x8002100906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_FIR_MASK_PL = 0x800210090601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_FIR_PL = 0x8002080906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_FIR_PL = 0x800208090601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_SPARE_MODE_PL = 0x8002000906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_SPARE_MODE_PL = 0x800200090601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL = 0x8003000C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL = 0x8003000C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL = 0x8002480C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL = 0x8002480C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_E_PL = 0x8003080C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_E_PL = 0x8003080C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL = 0x8002500C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL = 0x8002500C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_E_PL = 0x8003100C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_E_PL = 0x8003100C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL = 0x8002580C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL = 0x8002580C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL5_EO_PL = 0x8002600C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL5_EO_PL = 0x8002600C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL = 0x8002400C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL = 0x8002400C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL = 0x8002200C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL = 0x8002200C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE1_E_PL = 0x8002C00C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE1_E_PL = 0x8002C00C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE2_EO_PL = 0x8002280C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE2_EO_PL = 0x8002280C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE2_E_PL = 0x8002C80C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE2_E_PL = 0x8002C80C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL = 0x8002300C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL = 0x8002300C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT1_EO_PL = 0x8002680C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT1_EO_PL = 0x8002680C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL = 0x8002700C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL = 0x8002700C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL = 0x8002780C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL = 0x8002780C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL = 0x8000080C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL = 0x8000080C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_E_PL = 0x8000800C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_E_PL = 0x8000800C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_EO_PL = 0x8000100C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_EO_PL = 0x8000100C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_E_PL = 0x8000880C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_E_PL = 0x8000880C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL3_EO_PL = 0x8000180C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL3_EO_PL = 0x8000180C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL3_E_PL = 0x8000900C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL3_E_PL = 0x8000900C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_EO_PL = 0x8000200C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_EO_PL = 0x8000200C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_E_PL = 0x8000980C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_E_PL = 0x8000980C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL = 0x8000280C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL = 0x8000280C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_E_PL = 0x8000A00C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_E_PL = 0x8000A00C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL6_EO_PL = 0x8000300C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL6_EO_PL = 0x8000300C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL6_E_PL = 0x8000A80C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL6_E_PL = 0x8000A80C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL7_EO_PL = 0x8000380C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL7_EO_PL = 0x8000380C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL7_E_PL = 0x8000B00C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL7_E_PL = 0x8000B00C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL8_EO_PL = 0x8000400C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL8_EO_PL = 0x8000400C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL8_E_PL = 0x8000B80C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL8_E_PL = 0x8000B80C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL9_E_PL = 0x8000C00C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL9_E_PL = 0x8000C00C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL = 0x8000000C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x8000000C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_FIR_ERROR_INJECT_PL = 0x8002180C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_FIR_ERROR_INJECT_PL = 0x8002180C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_FIR_MASK_PL = 0x8002100C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_FIR_MASK_PL = 0x8002100C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_FIR_PL = 0x8002080C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_FIR_PL = 0x8002080C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_SPARE_MODE_PL = 0x8002000C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_SPARE_MODE_PL = 0x8002000C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL = 0x8003000A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL = 0x8003000A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL = 0x8002480A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL = 0x8002480A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_E_PL = 0x8003080A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_E_PL = 0x8003080A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL = 0x8002500A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL = 0x8002500A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_E_PL = 0x8003100A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_E_PL = 0x8003100A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL = 0x8002580A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL = 0x8002580A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL5_EO_PL = 0x8002600A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL5_EO_PL = 0x8002600A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL = 0x8002400A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL = 0x8002400A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL = 0x8002200A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL = 0x8002200A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE1_E_PL = 0x8002C00A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE1_E_PL = 0x8002C00A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE2_EO_PL = 0x8002280A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE2_EO_PL = 0x8002280A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE2_E_PL = 0x8002C80A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE2_E_PL = 0x8002C80A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL = 0x8002300A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL = 0x8002300A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT1_EO_PL = 0x8002680A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT1_EO_PL = 0x8002680A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL = 0x8002700A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL = 0x8002700A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL = 0x8002780A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL = 0x8002780A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL = 0x8000080A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL = 0x8000080A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_E_PL = 0x8000800A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_E_PL = 0x8000800A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_EO_PL = 0x8000100A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_EO_PL = 0x8000100A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_E_PL = 0x8000880A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_E_PL = 0x8000880A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL3_EO_PL = 0x8000180A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL3_EO_PL = 0x8000180A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL3_E_PL = 0x8000900A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL3_E_PL = 0x8000900A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_EO_PL = 0x8000200A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_EO_PL = 0x8000200A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_E_PL = 0x8000980A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_E_PL = 0x8000980A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL = 0x8000280A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL = 0x8000280A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_E_PL = 0x8000A00A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_E_PL = 0x8000A00A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL6_EO_PL = 0x8000300A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL6_EO_PL = 0x8000300A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL6_E_PL = 0x8000A80A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL6_E_PL = 0x8000A80A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL7_EO_PL = 0x8000380A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL7_EO_PL = 0x8000380A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL7_E_PL = 0x8000B00A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL7_E_PL = 0x8000B00A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL8_EO_PL = 0x8000400A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL8_EO_PL = 0x8000400A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL8_E_PL = 0x8000B80A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL8_E_PL = 0x8000B80A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL9_E_PL = 0x8000C00A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL9_E_PL = 0x8000C00A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL = 0x8000000A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x8000000A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_FIR_ERROR_INJECT_PL = 0x8002180A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_FIR_ERROR_INJECT_PL = 0x8002180A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_FIR_MASK_PL = 0x8002100A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_FIR_MASK_PL = 0x8002100A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_FIR_PL = 0x8002080A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_FIR_PL = 0x8002080A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_SPARE_MODE_PL = 0x8002000A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_SPARE_MODE_PL = 0x8002000A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL = 0x8003000706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL = 0x800300070601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL = 0x8002480706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL = 0x800248070601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_E_PL = 0x8003080706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_E_PL = 0x800308070601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL = 0x8002500706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL = 0x800250070601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_E_PL = 0x8003100706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_E_PL = 0x800310070601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL = 0x8002580706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL = 0x800258070601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL5_EO_PL = 0x8002600706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL5_EO_PL = 0x800260070601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL = 0x8002400706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL = 0x800240070601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL = 0x8002200706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL = 0x800220070601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE1_E_PL = 0x8002C00706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE1_E_PL = 0x8002C0070601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE2_EO_PL = 0x8002280706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE2_EO_PL = 0x800228070601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE2_E_PL = 0x8002C80706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE2_E_PL = 0x8002C8070601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL = 0x8002300706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL = 0x800230070601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT1_EO_PL = 0x8002680706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT1_EO_PL = 0x800268070601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL = 0x8002700706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL = 0x800270070601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL = 0x8002780706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL = 0x800278070601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL = 0x8000080706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL = 0x800008070601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_E_PL = 0x8000800706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_E_PL = 0x800080070601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_EO_PL = 0x8000100706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_EO_PL = 0x800010070601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_E_PL = 0x8000880706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_E_PL = 0x800088070601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL3_EO_PL = 0x8000180706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL3_EO_PL = 0x800018070601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL3_E_PL = 0x8000900706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL3_E_PL = 0x800090070601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_EO_PL = 0x8000200706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_EO_PL = 0x800020070601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_E_PL = 0x8000980706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_E_PL = 0x800098070601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL = 0x8000280706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL = 0x800028070601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_E_PL = 0x8000A00706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_E_PL = 0x8000A0070601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL6_EO_PL = 0x8000300706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL6_EO_PL = 0x800030070601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL6_E_PL = 0x8000A80706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL6_E_PL = 0x8000A8070601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL7_EO_PL = 0x8000380706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL7_EO_PL = 0x800038070601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL7_E_PL = 0x8000B00706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL7_E_PL = 0x8000B0070601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL8_EO_PL = 0x8000400706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL8_EO_PL = 0x800040070601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL8_E_PL = 0x8000B80706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL8_E_PL = 0x8000B8070601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL9_E_PL = 0x8000C00706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL9_E_PL = 0x8000C0070601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL = 0x8000000706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x800000070601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_FIR_ERROR_INJECT_PL = 0x8002180706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_FIR_ERROR_INJECT_PL = 0x800218070601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_FIR_MASK_PL = 0x8002100706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_FIR_MASK_PL = 0x800210070601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_FIR_PL = 0x8002080706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_FIR_PL = 0x800208070601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_SPARE_MODE_PL = 0x8002000706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_SPARE_MODE_PL = 0x800200070601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL = 0x8003001106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL = 0x800300110601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL = 0x8002481106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL = 0x800248110601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_E_PL = 0x8003081106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_E_PL = 0x800308110601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL = 0x8002501106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL = 0x800250110601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_E_PL = 0x8003101106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_E_PL = 0x800310110601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL = 0x8002581106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL = 0x800258110601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL5_EO_PL = 0x8002601106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL5_EO_PL = 0x800260110601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL = 0x8002401106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL = 0x800240110601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL = 0x8002201106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL = 0x800220110601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE1_E_PL = 0x8002C01106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE1_E_PL = 0x8002C0110601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE2_EO_PL = 0x8002281106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE2_EO_PL = 0x800228110601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE2_E_PL = 0x8002C81106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE2_E_PL = 0x8002C8110601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL = 0x8002301106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL = 0x800230110601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT1_EO_PL = 0x8002681106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT1_EO_PL = 0x800268110601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL = 0x8002701106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL = 0x800270110601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL = 0x8002781106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL = 0x800278110601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL = 0x8000081106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL = 0x800008110601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_E_PL = 0x8000801106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_E_PL = 0x800080110601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_EO_PL = 0x8000101106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_EO_PL = 0x800010110601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_E_PL = 0x8000881106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_E_PL = 0x800088110601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL3_EO_PL = 0x8000181106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL3_EO_PL = 0x800018110601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL3_E_PL = 0x8000901106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL3_E_PL = 0x800090110601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_EO_PL = 0x8000201106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_EO_PL = 0x800020110601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_E_PL = 0x8000981106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_E_PL = 0x800098110601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL = 0x8000281106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL = 0x800028110601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_E_PL = 0x8000A01106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_E_PL = 0x8000A0110601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL6_EO_PL = 0x8000301106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL6_EO_PL = 0x800030110601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL6_E_PL = 0x8000A81106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL6_E_PL = 0x8000A8110601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL7_EO_PL = 0x8000381106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL7_EO_PL = 0x800038110601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL7_E_PL = 0x8000B01106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL7_E_PL = 0x8000B0110601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL8_EO_PL = 0x8000401106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL8_EO_PL = 0x800040110601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL8_E_PL = 0x8000B81106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL8_E_PL = 0x8000B8110601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL9_E_PL = 0x8000C01106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL9_E_PL = 0x8000C0110601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL = 0x8000001106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x800000110601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_FIR_ERROR_INJECT_PL = 0x8002181106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_FIR_ERROR_INJECT_PL = 0x800218110601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_FIR_MASK_PL = 0x8002101106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_FIR_MASK_PL = 0x800210110601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_FIR_PL = 0x8002081106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_FIR_PL = 0x800208110601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_SPARE_MODE_PL = 0x8002001106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_SPARE_MODE_PL = 0x800200110601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL = 0x8003000606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL = 0x800300060601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL = 0x8002480606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL = 0x800248060601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_E_PL = 0x8003080606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_E_PL = 0x800308060601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL = 0x8002500606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL = 0x800250060601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_E_PL = 0x8003100606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_E_PL = 0x800310060601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL = 0x8002580606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL = 0x800258060601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL5_EO_PL = 0x8002600606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL5_EO_PL = 0x800260060601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL = 0x8002400606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL = 0x800240060601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL = 0x8002200606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL = 0x800220060601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE1_E_PL = 0x8002C00606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE1_E_PL = 0x8002C0060601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE2_EO_PL = 0x8002280606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE2_EO_PL = 0x800228060601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE2_E_PL = 0x8002C80606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE2_E_PL = 0x8002C8060601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL = 0x8002300606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL = 0x800230060601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT1_EO_PL = 0x8002680606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT1_EO_PL = 0x800268060601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL = 0x8002700606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL = 0x800270060601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL = 0x8002780606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL = 0x800278060601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL = 0x8000080606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL = 0x800008060601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_E_PL = 0x8000800606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_E_PL = 0x800080060601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_EO_PL = 0x8000100606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_EO_PL = 0x800010060601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_E_PL = 0x8000880606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_E_PL = 0x800088060601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL3_EO_PL = 0x8000180606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL3_EO_PL = 0x800018060601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL3_E_PL = 0x8000900606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL3_E_PL = 0x800090060601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_EO_PL = 0x8000200606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_EO_PL = 0x800020060601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_E_PL = 0x8000980606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_E_PL = 0x800098060601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL = 0x8000280606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL = 0x800028060601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_E_PL = 0x8000A00606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_E_PL = 0x8000A0060601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL6_EO_PL = 0x8000300606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL6_EO_PL = 0x800030060601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL6_E_PL = 0x8000A80606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL6_E_PL = 0x8000A8060601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL7_EO_PL = 0x8000380606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL7_EO_PL = 0x800038060601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL7_E_PL = 0x8000B00606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL7_E_PL = 0x8000B0060601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL8_EO_PL = 0x8000400606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL8_EO_PL = 0x800040060601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL8_E_PL = 0x8000B80606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL8_E_PL = 0x8000B8060601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL9_E_PL = 0x8000C00606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL9_E_PL = 0x8000C0060601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL = 0x8000000606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x800000060601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_FIR_ERROR_INJECT_PL = 0x8002180606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_FIR_ERROR_INJECT_PL = 0x800218060601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_FIR_MASK_PL = 0x8002100606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_FIR_MASK_PL = 0x800210060601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_FIR_PL = 0x8002080606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_FIR_PL = 0x800208060601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_SPARE_MODE_PL = 0x8002000606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_SPARE_MODE_PL = 0x800200060601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL = 0x8003000806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL = 0x800300080601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL = 0x8002480806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL = 0x800248080601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_E_PL = 0x8003080806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_E_PL = 0x800308080601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL = 0x8002500806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL = 0x800250080601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_E_PL = 0x8003100806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_E_PL = 0x800310080601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL = 0x8002580806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL = 0x800258080601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL5_EO_PL = 0x8002600806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL5_EO_PL = 0x800260080601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL = 0x8002400806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL = 0x800240080601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL = 0x8002200806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL = 0x800220080601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE1_E_PL = 0x8002C00806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE1_E_PL = 0x8002C0080601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE2_EO_PL = 0x8002280806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE2_EO_PL = 0x800228080601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE2_E_PL = 0x8002C80806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE2_E_PL = 0x8002C8080601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL = 0x8002300806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL = 0x800230080601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT1_EO_PL = 0x8002680806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT1_EO_PL = 0x800268080601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL = 0x8002700806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL = 0x800270080601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL = 0x8002780806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL = 0x800278080601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL = 0x8000080806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL = 0x800008080601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_E_PL = 0x8000800806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_E_PL = 0x800080080601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_EO_PL = 0x8000100806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_EO_PL = 0x800010080601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_E_PL = 0x8000880806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_E_PL = 0x800088080601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL3_EO_PL = 0x8000180806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL3_EO_PL = 0x800018080601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL3_E_PL = 0x8000900806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL3_E_PL = 0x800090080601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_EO_PL = 0x8000200806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_EO_PL = 0x800020080601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_E_PL = 0x8000980806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_E_PL = 0x800098080601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL = 0x8000280806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL = 0x800028080601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_E_PL = 0x8000A00806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_E_PL = 0x8000A0080601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL6_EO_PL = 0x8000300806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL6_EO_PL = 0x800030080601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL6_E_PL = 0x8000A80806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL6_E_PL = 0x8000A8080601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL7_EO_PL = 0x8000380806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL7_EO_PL = 0x800038080601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL7_E_PL = 0x8000B00806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL7_E_PL = 0x8000B0080601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL8_EO_PL = 0x8000400806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL8_EO_PL = 0x800040080601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL8_E_PL = 0x8000B80806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL8_E_PL = 0x8000B8080601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL9_E_PL = 0x8000C00806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL9_E_PL = 0x8000C0080601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL = 0x8000000806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x800000080601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_FIR_ERROR_INJECT_PL = 0x8002180806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_FIR_ERROR_INJECT_PL = 0x800218080601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_FIR_MASK_PL = 0x8002100806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_FIR_MASK_PL = 0x800210080601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_FIR_PL = 0x8002080806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_FIR_PL = 0x800208080601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_SPARE_MODE_PL = 0x8002000806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_SPARE_MODE_PL = 0x800200080601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL = 0x8003000406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL = 0x800300040601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL = 0x8002480406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL = 0x800248040601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_E_PL = 0x8003080406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_E_PL = 0x800308040601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL = 0x8002500406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL = 0x800250040601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_E_PL = 0x8003100406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_E_PL = 0x800310040601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL = 0x8002580406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL = 0x800258040601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL5_EO_PL = 0x8002600406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL5_EO_PL = 0x800260040601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL = 0x8002400406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL = 0x800240040601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL = 0x8002200406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL = 0x800220040601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE1_E_PL = 0x8002C00406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE1_E_PL = 0x8002C0040601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE2_EO_PL = 0x8002280406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE2_EO_PL = 0x800228040601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE2_E_PL = 0x8002C80406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE2_E_PL = 0x8002C8040601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL = 0x8002300406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL = 0x800230040601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT1_EO_PL = 0x8002680406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT1_EO_PL = 0x800268040601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL = 0x8002700406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL = 0x800270040601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL = 0x8002780406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL = 0x800278040601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL = 0x8000080406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL = 0x800008040601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_E_PL = 0x8000800406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_E_PL = 0x800080040601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_EO_PL = 0x8000100406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_EO_PL = 0x800010040601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_E_PL = 0x8000880406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_E_PL = 0x800088040601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL3_EO_PL = 0x8000180406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL3_EO_PL = 0x800018040601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL3_E_PL = 0x8000900406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL3_E_PL = 0x800090040601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_EO_PL = 0x8000200406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_EO_PL = 0x800020040601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_E_PL = 0x8000980406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_E_PL = 0x800098040601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL = 0x8000280406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL = 0x800028040601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_E_PL = 0x8000A00406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_E_PL = 0x8000A0040601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL6_EO_PL = 0x8000300406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL6_EO_PL = 0x800030040601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL6_E_PL = 0x8000A80406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL6_E_PL = 0x8000A8040601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL7_EO_PL = 0x8000380406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL7_EO_PL = 0x800038040601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL7_E_PL = 0x8000B00406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL7_E_PL = 0x8000B0040601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL8_EO_PL = 0x8000400406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL8_EO_PL = 0x800040040601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL8_E_PL = 0x8000B80406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL8_E_PL = 0x8000B8040601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL9_E_PL = 0x8000C00406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL9_E_PL = 0x8000C0040601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL = 0x8000000406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x800000040601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_FIR_ERROR_INJECT_PL = 0x8002180406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_FIR_ERROR_INJECT_PL = 0x800218040601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_FIR_MASK_PL = 0x8002100406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_FIR_MASK_PL = 0x800210040601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_FIR_PL = 0x8002080406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_FIR_PL = 0x800208040601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_SPARE_MODE_PL = 0x8002000406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_SPARE_MODE_PL = 0x800200040601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL = 0x8003000206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL = 0x800300020601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL = 0x8002480206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL = 0x800248020601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_E_PL = 0x8003080206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_E_PL = 0x800308020601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL = 0x8002500206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL = 0x800250020601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_E_PL = 0x8003100206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_E_PL = 0x800310020601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL = 0x8002580206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL = 0x800258020601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL5_EO_PL = 0x8002600206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL5_EO_PL = 0x800260020601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL = 0x8002400206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL = 0x800240020601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL = 0x8002200206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL = 0x800220020601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE1_E_PL = 0x8002C00206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE1_E_PL = 0x8002C0020601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE2_EO_PL = 0x8002280206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE2_EO_PL = 0x800228020601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE2_E_PL = 0x8002C80206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE2_E_PL = 0x8002C8020601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL = 0x8002300206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL = 0x800230020601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT1_EO_PL = 0x8002680206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT1_EO_PL = 0x800268020601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL = 0x8002700206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL = 0x800270020601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL = 0x8002780206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL = 0x800278020601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL = 0x8000080206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL = 0x800008020601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_E_PL = 0x8000800206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_E_PL = 0x800080020601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_EO_PL = 0x8000100206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_EO_PL = 0x800010020601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_E_PL = 0x8000880206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_E_PL = 0x800088020601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL3_EO_PL = 0x8000180206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL3_EO_PL = 0x800018020601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL3_E_PL = 0x8000900206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL3_E_PL = 0x800090020601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_EO_PL = 0x8000200206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_EO_PL = 0x800020020601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_E_PL = 0x8000980206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_E_PL = 0x800098020601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL = 0x8000280206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL = 0x800028020601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_E_PL = 0x8000A00206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_E_PL = 0x8000A0020601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL6_EO_PL = 0x8000300206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL6_EO_PL = 0x800030020601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL6_E_PL = 0x8000A80206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL6_E_PL = 0x8000A8020601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL7_EO_PL = 0x8000380206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL7_EO_PL = 0x800038020601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL7_E_PL = 0x8000B00206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL7_E_PL = 0x8000B0020601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL8_EO_PL = 0x8000400206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL8_EO_PL = 0x800040020601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL8_E_PL = 0x8000B80206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL8_E_PL = 0x8000B8020601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL9_E_PL = 0x8000C00206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL9_E_PL = 0x8000C0020601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL = 0x8000000206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x800000020601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_FIR_ERROR_INJECT_PL = 0x8002180206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_FIR_ERROR_INJECT_PL = 0x800218020601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_FIR_MASK_PL = 0x8002100206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_FIR_MASK_PL = 0x800210020601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_FIR_PL = 0x8002080206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_FIR_PL = 0x800208020601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_SPARE_MODE_PL = 0x8002000206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_SPARE_MODE_PL = 0x800200020601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL = 0x8003000506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL = 0x800300050601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL = 0x8002480506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL = 0x800248050601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_E_PL = 0x8003080506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_E_PL = 0x800308050601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL = 0x8002500506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL = 0x800250050601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_E_PL = 0x8003100506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_E_PL = 0x800310050601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL = 0x8002580506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL = 0x800258050601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL5_EO_PL = 0x8002600506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL5_EO_PL = 0x800260050601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL = 0x8002400506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL = 0x800240050601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL = 0x8002200506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL = 0x800220050601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE1_E_PL = 0x8002C00506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE1_E_PL = 0x8002C0050601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE2_EO_PL = 0x8002280506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE2_EO_PL = 0x800228050601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE2_E_PL = 0x8002C80506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE2_E_PL = 0x8002C8050601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL = 0x8002300506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL = 0x800230050601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT1_EO_PL = 0x8002680506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT1_EO_PL = 0x800268050601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL = 0x8002700506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL = 0x800270050601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL = 0x8002780506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL = 0x800278050601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL = 0x8000080506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL = 0x800008050601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_E_PL = 0x8000800506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_E_PL = 0x800080050601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_EO_PL = 0x8000100506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_EO_PL = 0x800010050601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_E_PL = 0x8000880506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_E_PL = 0x800088050601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL3_EO_PL = 0x8000180506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL3_EO_PL = 0x800018050601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL3_E_PL = 0x8000900506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL3_E_PL = 0x800090050601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_EO_PL = 0x8000200506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_EO_PL = 0x800020050601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_E_PL = 0x8000980506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_E_PL = 0x800098050601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL = 0x8000280506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL = 0x800028050601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_E_PL = 0x8000A00506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_E_PL = 0x8000A0050601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL6_EO_PL = 0x8000300506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL6_EO_PL = 0x800030050601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL6_E_PL = 0x8000A80506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL6_E_PL = 0x8000A8050601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL7_EO_PL = 0x8000380506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL7_EO_PL = 0x800038050601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL7_E_PL = 0x8000B00506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL7_E_PL = 0x8000B0050601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL8_EO_PL = 0x8000400506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL8_EO_PL = 0x800040050601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL8_E_PL = 0x8000B80506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL8_E_PL = 0x8000B8050601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL9_E_PL = 0x8000C00506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL9_E_PL = 0x8000C0050601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL = 0x8000000506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x800000050601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_FIR_ERROR_INJECT_PL = 0x8002180506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_FIR_ERROR_INJECT_PL = 0x800218050601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_FIR_MASK_PL = 0x8002100506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_FIR_MASK_PL = 0x800210050601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_FIR_PL = 0x8002080506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_FIR_PL = 0x800208050601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_SPARE_MODE_PL = 0x8002000506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_SPARE_MODE_PL = 0x800200050601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL = 0x8003000306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL = 0x800300030601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL = 0x8002480306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL = 0x800248030601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_E_PL = 0x8003080306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_E_PL = 0x800308030601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL = 0x8002500306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL = 0x800250030601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_E_PL = 0x8003100306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_E_PL = 0x800310030601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL = 0x8002580306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL = 0x800258030601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL5_EO_PL = 0x8002600306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL5_EO_PL = 0x800260030601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL = 0x8002400306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL = 0x800240030601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL = 0x8002200306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL = 0x800220030601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE1_E_PL = 0x8002C00306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE1_E_PL = 0x8002C0030601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE2_EO_PL = 0x8002280306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE2_EO_PL = 0x800228030601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE2_E_PL = 0x8002C80306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE2_E_PL = 0x8002C8030601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL = 0x8002300306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL = 0x800230030601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT1_EO_PL = 0x8002680306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT1_EO_PL = 0x800268030601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL = 0x8002700306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL = 0x800270030601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL = 0x8002780306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL = 0x800278030601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL = 0x8000080306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL = 0x800008030601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_E_PL = 0x8000800306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_E_PL = 0x800080030601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_EO_PL = 0x8000100306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_EO_PL = 0x800010030601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_E_PL = 0x8000880306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_E_PL = 0x800088030601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL3_EO_PL = 0x8000180306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL3_EO_PL = 0x800018030601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL3_E_PL = 0x8000900306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL3_E_PL = 0x800090030601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_EO_PL = 0x8000200306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_EO_PL = 0x800020030601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_E_PL = 0x8000980306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_E_PL = 0x800098030601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL = 0x8000280306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL = 0x800028030601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_E_PL = 0x8000A00306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_E_PL = 0x8000A0030601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL6_EO_PL = 0x8000300306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL6_EO_PL = 0x800030030601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL6_E_PL = 0x8000A80306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL6_E_PL = 0x8000A8030601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL7_EO_PL = 0x8000380306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL7_EO_PL = 0x800038030601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL7_E_PL = 0x8000B00306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL7_E_PL = 0x8000B0030601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL8_EO_PL = 0x8000400306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL8_EO_PL = 0x800040030601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL8_E_PL = 0x8000B80306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL8_E_PL = 0x8000B8030601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL9_E_PL = 0x8000C00306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL9_E_PL = 0x8000C0030601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL = 0x8000000306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x800000030601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_FIR_ERROR_INJECT_PL = 0x8002180306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_FIR_ERROR_INJECT_PL = 0x800218030601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_FIR_MASK_PL = 0x8002100306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_FIR_MASK_PL = 0x800210030601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_FIR_PL = 0x8002080306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_FIR_PL = 0x800208030601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_SPARE_MODE_PL = 0x8002000306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_SPARE_MODE_PL = 0x800200030601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL = 0x8003000006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL = 0x800300000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL2_EO_PL = 0x8002480006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL2_EO_PL = 0x800248000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL2_E_PL = 0x8003080006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL2_E_PL = 0x800308000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL3_EO_PL = 0x8002500006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL3_EO_PL = 0x800250000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL3_E_PL = 0x8003100006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL3_E_PL = 0x800310000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL4_EO_PL = 0x8002580006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL4_EO_PL = 0x800258000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL5_EO_PL = 0x8002600006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL5_EO_PL = 0x800260000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL = 0x8002400006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL = 0x800240000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE1_EO_PL = 0x8002200006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE1_EO_PL = 0x800220000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE1_E_PL = 0x8002C00006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE1_E_PL = 0x8002C0000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE2_EO_PL = 0x8002280006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE2_EO_PL = 0x800228000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE2_E_PL = 0x8002C80006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE2_E_PL = 0x8002C8000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE3_EO_PL = 0x8002300006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE3_EO_PL = 0x800230000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT1_EO_PL = 0x8002680006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT1_EO_PL = 0x800268000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT2_EO_PL = 0x8002700006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT2_EO_PL = 0x800270000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT3_EO_PL = 0x8002780006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT3_EO_PL = 0x800278000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL1_EO_PL = 0x8000080006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL1_EO_PL = 0x800008000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL1_E_PL = 0x8000800006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL1_E_PL = 0x800080000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL2_EO_PL = 0x8000100006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL2_EO_PL = 0x800010000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL2_E_PL = 0x8000880006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL2_E_PL = 0x800088000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL3_EO_PL = 0x8000180006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL3_EO_PL = 0x800018000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL3_E_PL = 0x8000900006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL3_E_PL = 0x800090000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL4_EO_PL = 0x8000200006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL4_EO_PL = 0x800020000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL4_E_PL = 0x8000980006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL4_E_PL = 0x800098000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL5_EO_PL = 0x8000280006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL5_EO_PL = 0x800028000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL5_E_PL = 0x8000A00006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL5_E_PL = 0x8000A0000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL6_EO_PL = 0x8000300006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL6_EO_PL = 0x800030000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL6_E_PL = 0x8000A80006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL6_E_PL = 0x8000A8000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL7_EO_PL = 0x8000380006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL7_EO_PL = 0x800038000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL7_E_PL = 0x8000B00006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL7_E_PL = 0x8000B0000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL8_EO_PL = 0x8000400006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL8_EO_PL = 0x800040000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL8_E_PL = 0x8000B80006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL8_E_PL = 0x8000B8000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL9_E_PL = 0x8000C00006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL9_E_PL = 0x8000C0000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DATA_DAC_SPARE_MODE_PL = 0x8000000006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x800000000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_FIR_ERROR_INJECT_PL = 0x8002180006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_FIR_ERROR_INJECT_PL = 0x800218000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_FIR_MASK_PL = 0x8002100006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_FIR_MASK_PL = 0x800210000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_FIR_PL = 0x8002080006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_FIR_PL = 0x800208000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_SPARE_MODE_PL = 0x8002000006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_SPARE_MODE_PL = 0x800200000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL = 0x8003000106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL = 0x800300010601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL2_EO_PL = 0x8002480106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL2_EO_PL = 0x800248010601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL2_E_PL = 0x8003080106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL2_E_PL = 0x800308010601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL3_EO_PL = 0x8002500106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL3_EO_PL = 0x800250010601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL3_E_PL = 0x8003100106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL3_E_PL = 0x800310010601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL4_EO_PL = 0x8002580106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL4_EO_PL = 0x800258010601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL5_EO_PL = 0x8002600106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL5_EO_PL = 0x800260010601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL = 0x8002400106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL = 0x800240010601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE1_EO_PL = 0x8002200106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE1_EO_PL = 0x800220010601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE1_E_PL = 0x8002C00106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE1_E_PL = 0x8002C0010601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE2_EO_PL = 0x8002280106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE2_EO_PL = 0x800228010601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE2_E_PL = 0x8002C80106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE2_E_PL = 0x8002C8010601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE3_EO_PL = 0x8002300106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE3_EO_PL = 0x800230010601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT1_EO_PL = 0x8002680106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT1_EO_PL = 0x800268010601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT2_EO_PL = 0x8002700106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT2_EO_PL = 0x800270010601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT3_EO_PL = 0x8002780106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT3_EO_PL = 0x800278010601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL1_EO_PL = 0x8000080106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL1_EO_PL = 0x800008010601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL1_E_PL = 0x8000800106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL1_E_PL = 0x800080010601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL2_EO_PL = 0x8000100106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL2_EO_PL = 0x800010010601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL2_E_PL = 0x8000880106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL2_E_PL = 0x800088010601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL3_EO_PL = 0x8000180106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL3_EO_PL = 0x800018010601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL3_E_PL = 0x8000900106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL3_E_PL = 0x800090010601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL4_EO_PL = 0x8000200106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL4_EO_PL = 0x800020010601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL4_E_PL = 0x8000980106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL4_E_PL = 0x800098010601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL5_EO_PL = 0x8000280106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL5_EO_PL = 0x800028010601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL5_E_PL = 0x8000A00106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL5_E_PL = 0x8000A0010601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL6_EO_PL = 0x8000300106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL6_EO_PL = 0x800030010601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL6_E_PL = 0x8000A80106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL6_E_PL = 0x8000A8010601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL7_EO_PL = 0x8000380106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL7_EO_PL = 0x800038010601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL7_E_PL = 0x8000B00106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL7_E_PL = 0x8000B0010601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL8_EO_PL = 0x8000400106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL8_EO_PL = 0x800040010601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL8_E_PL = 0x8000B80106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL8_E_PL = 0x8000B8010601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL9_E_PL = 0x8000C00106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL9_E_PL = 0x8000C0010601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DATA_DAC_SPARE_MODE_PL = 0x8000000106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x800000010601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_FIR_ERROR_INJECT_PL = 0x8002180106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_FIR_ERROR_INJECT_PL = 0x800218010601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_FIR_MASK_PL = 0x8002100106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_FIR_MASK_PL = 0x800210010601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_FIR_PL = 0x8002080106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_FIR_PL = 0x800208010601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_SPARE_MODE_PL = 0x8002000106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_SPARE_MODE_PL = 0x800200010601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL10_EO_PG = 0x8009200006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL10_EO_PG = 0x800920000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL11_EO_PG = 0x8009280006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL11_EO_PG = 0x800928000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL12_EO_PG = 0x8009300006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL12_EO_PG = 0x800930000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL13_EO_PG = 0x8009380006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL13_EO_PG = 0x800938000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL14_EO_PG = 0x8009400006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL14_EO_PG = 0x800940000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL15_EO_PG = 0x8009480006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL15_EO_PG = 0x800948000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL1_EO_PG = 0x8008D80006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL1_EO_PG = 0x8008D8000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL1_E_PG = 0x8009F00006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL1_E_PG = 0x8009F0000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL2_EO_PG = 0x8008E00006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL2_EO_PG = 0x8008E0000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL3_EO_PG = 0x8008E80006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL3_EO_PG = 0x8008E8000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL4_EO_PG = 0x8008F00006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL4_EO_PG = 0x8008F0000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL4_E_PG = 0x8009F80006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL4_E_PG = 0x8009F8000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL5_EO_PG = 0x8008F80006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL5_EO_PG = 0x8008F8000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL6_EO_PG = 0x8009000006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL6_EO_PG = 0x800900000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL8_EO_PG = 0x8009100006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL8_EO_PG = 0x800910000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL9_EO_PG = 0x8009180006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL9_EO_PG = 0x800918000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTLX11_E_PG = 0x800A300006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTLX11_E_PG = 0x800A30000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTLX7_EO_PG = 0x8009080006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTLX7_EO_PG = 0x800908000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE10_EO_PG = 0x8008580006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE10_EO_PG = 0x800858000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE10_E_PG = 0x8009D80006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE10_E_PG = 0x8009D8000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE11_EO_PG = 0x8008600006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE11_EO_PG = 0x800860000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE11_E_PG = 0x8009E00006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE11_E_PG = 0x8009E0000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE12_EO_PG = 0x8008680006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE12_EO_PG = 0x800868000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE12_E_PG = 0x8009E80006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE12_E_PG = 0x8009E8000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE13_EO_PG = 0x8008700006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE13_EO_PG = 0x800870000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE14_EO_PG = 0x8008780006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE14_EO_PG = 0x800878000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE15_EO_PG = 0x8008800006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE15_EO_PG = 0x800880000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE16_EO_PG = 0x8008880006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE16_EO_PG = 0x800888000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE17_EO_PG = 0x8008900006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE17_EO_PG = 0x800890000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE18_EO_PG = 0x8008980006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE18_EO_PG = 0x800898000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE19_EO_PG = 0x8008A00006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE19_EO_PG = 0x8008A0000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE1_EO_PG = 0x8008100006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE1_EO_PG = 0x800810000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE1_E_PG = 0x8009900006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE1_E_PG = 0x800990000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE20_EO_PG = 0x8008A80006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE20_EO_PG = 0x8008A8000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE21_EO_PG = 0x8008B00006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE21_EO_PG = 0x8008B0000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE22_EO_PG = 0x8008B80006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE22_EO_PG = 0x8008B8000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE23_EO_PG = 0x8008C00006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE23_EO_PG = 0x8008C0000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE24_EO_PG = 0x8008C80006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE24_EO_PG = 0x8008C8000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE26_EO_PG = 0x8009680006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE26_EO_PG = 0x800968000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE27_EO_PG = 0x8009700006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE27_EO_PG = 0x800970000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE28_EO_PG = 0x8009780006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE28_EO_PG = 0x800978000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE29_EO_PG = 0x8008D00006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE29_EO_PG = 0x8008D0000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE2_EO_PG = 0x8008180006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE2_EO_PG = 0x800818000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE2_E_PG = 0x8009980006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE2_E_PG = 0x800998000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE3_EO_PG = 0x8008200006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE3_EO_PG = 0x800820000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE3_E_PG = 0x8009A00006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE3_E_PG = 0x8009A0000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE4_EO_PG = 0x8008280006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE4_EO_PG = 0x800828000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE4_E_PG = 0x8009A80006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE4_E_PG = 0x8009A8000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE5_EO_PG = 0x8008300006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE5_EO_PG = 0x800830000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE5_E_PG = 0x8009B00006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE5_E_PG = 0x8009B0000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE6_EO_PG = 0x8008380006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE6_EO_PG = 0x800838000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE6_E_PG = 0x8009B80006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE6_E_PG = 0x8009B8000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE7_EO_PG = 0x8008400006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE7_EO_PG = 0x800840000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE7_E_PG = 0x8009C00006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE7_E_PG = 0x8009C0000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE8_EO_PG = 0x8008480006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE8_EO_PG = 0x800848000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE8_E_PG = 0x8009C80006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE8_E_PG = 0x8009C8000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE9_EO_PG = 0x8008500006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE9_EO_PG = 0x800850000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE9_E_PG = 0x8009D00006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE9_E_PG = 0x8009D0000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT1_EO_PG = 0x8009500006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT1_EO_PG = 0x800950000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT1_E_PG = 0x800A380006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT1_E_PG = 0x800A38000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT2_EO_PG = 0x8009580006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT2_EO_PG = 0x800958000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT2_E_PG = 0x800A400006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT2_E_PG = 0x800A40000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT3_EO_PG = 0x8009600006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT3_EO_PG = 0x800960000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT4_E_PG = 0x800A500006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT4_E_PG = 0x800A50000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT5_E_PG = 0x800A580006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT5_E_PG = 0x800A58000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT6_E_PG = 0x800A600006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT6_E_PG = 0x800A60000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STATX8_E_PG = 0x800A680006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STATX8_E_PG = 0x800A68000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_CNTL1_E_PG = 0x800BE80006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_CNTL1_E_PG = 0x800BE8000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_CNTL2_EO_PG = 0x800B780006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_CNTL2_EO_PG = 0x800B78000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_CNTLX1_EO_PG = 0x800B880006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_CNTLX1_EO_PG = 0x800B88000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_SPARE_MODE_PG = 0x800B800006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_SPARE_MODE_PG = 0x800B80000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT10_EO_PG = 0x800BD80006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT10_EO_PG = 0x800BD8000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT11_EO_PG = 0x800BE00006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT11_EO_PG = 0x800BE0000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT12_EO_PG = 0x800BF00006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT12_EO_PG = 0x800BF0000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT13_E_PG = 0x800BF80006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT13_E_PG = 0x800BF8000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT1_EO_PG = 0x800B900006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT1_EO_PG = 0x800B90000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT2_EO_PG = 0x800B980006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT2_EO_PG = 0x800B98000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT3_EO_PG = 0x800BA00006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT3_EO_PG = 0x800BA0000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT4_EO_PG = 0x800BA80006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT4_EO_PG = 0x800BA8000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT5_EO_PG = 0x800BB00006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT5_EO_PG = 0x800BB0000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT6_EO_PG = 0x800BB80006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT6_EO_PG = 0x800BB8000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT7_EO_PG = 0x800BC00006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT7_EO_PG = 0x800BC0000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT8_EO_PG = 0x800BC80006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT8_EO_PG = 0x800BC8000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT9_EO_PG = 0x800BD00006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT9_EO_PG = 0x800BD0000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_FIR1_ERROR_INJECT_PG = 0x800A980006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR1_ERROR_INJECT_PG = 0x800A98000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_FIR1_MASK_PG = 0x800A900006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR1_MASK_PG = 0x800A90000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_FIR1_PG = 0x800A880006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR1_PG = 0x800A88000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_FIR2_ERROR_INJECT_PG = 0x800B100006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR2_ERROR_INJECT_PG = 0x800B10000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_FIR2_MASK_PG = 0x800B080006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR2_MASK_PG = 0x800B08000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_FIR2_PG = 0x800B000006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR2_PG = 0x800B00000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_FIR_TRAINING_MASK_PG = 0x800AA80006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR_TRAINING_MASK_PG = 0x800AA8000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_FIR_TRAINING_PG = 0x800AA00006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR_TRAINING_PG = 0x800AA0000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_CNTL2_EO_PG = 0x800AE00006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_CNTL2_EO_PG = 0x800AE0000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_CNTL3_EO_PG = 0x800AE80006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_CNTL3_EO_PG = 0x800AE8000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_CNTL4_EO_PG = 0x800AF00006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_CNTL4_EO_PG = 0x800AF0000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_CNTLX1_EO_PG = 0x800AB00006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_CNTLX1_EO_PG = 0x800AB0000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_MODE1_EO_PG = 0x800AF80006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_MODE1_EO_PG = 0x800AF8000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_SPARE_MODE_PG = 0x800A800006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_SPARE_MODE_PG = 0x800A80000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT10_E_PG = 0x800B600006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT10_E_PG = 0x800B60000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT11_E_PG = 0x800B680006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT11_E_PG = 0x800B68000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT1_EO_PG = 0x800AB80006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT1_EO_PG = 0x800AB8000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT1_E_PG = 0x800B180006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT1_E_PG = 0x800B18000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT2_EO_PG = 0x800AC00006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT2_EO_PG = 0x800AC0000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT2_E_PG = 0x800B200006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT2_E_PG = 0x800B20000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT3_EO_PG = 0x800AC80006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT3_EO_PG = 0x800AC8000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT3_E_PG = 0x800B280006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT3_E_PG = 0x800B28000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT4_EO_PG = 0x800AD00006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT4_EO_PG = 0x800AD0000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT4_E_PG = 0x800B300006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT4_E_PG = 0x800B30000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT5_EO_PG = 0x800AD80006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT5_EO_PG = 0x800AD8000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT7_E_PG = 0x800B480006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT7_E_PG = 0x800B48000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT8_E_PG = 0x800B500006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT8_E_PG = 0x800B50000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT9_E_PG = 0x800B580006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT9_E_PG = 0x800B58000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_ID1_PG = 0x8008080006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_ID1_PG = 0x800808000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_ID2_PG = 0x8009800006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_ID2_PG = 0x800980000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_RX_SPARE_MODE_PG = 0x8008000006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_SPARE_MODE_PG = 0x800800000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE0_RX_DATA_WORK_SPARE_MODE_PL = 0x8003800D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE0_RX_DATA_WORK_SPARE_MODE_PL = 0x8003800D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE0_RX_WORK_STAT1_EO_PL = 0x8003880D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE0_RX_WORK_STAT1_EO_PL = 0x8003880D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE0_RX_WORK_STAT2_EO_PL = 0x8003900D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE0_RX_WORK_STAT2_EO_PL = 0x8003900D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE0_RX_WORK_STAT3_EO_PL = 0x8003980D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE0_RX_WORK_STAT3_EO_PL = 0x8003980D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE10_RX_DATA_WORK_SPARE_MODE_PL = 0x8003800606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE10_RX_DATA_WORK_SPARE_MODE_PL = 0x800380060601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE10_RX_WORK_STAT1_EO_PL = 0x8003880606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE10_RX_WORK_STAT1_EO_PL = 0x800388060601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE10_RX_WORK_STAT2_EO_PL = 0x8003900606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE10_RX_WORK_STAT2_EO_PL = 0x800390060601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE10_RX_WORK_STAT3_EO_PL = 0x8003980606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE10_RX_WORK_STAT3_EO_PL = 0x800398060601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE11_RX_DATA_WORK_SPARE_MODE_PL = 0x8003800806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE11_RX_DATA_WORK_SPARE_MODE_PL = 0x800380080601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE11_RX_WORK_STAT1_EO_PL = 0x8003880806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE11_RX_WORK_STAT1_EO_PL = 0x800388080601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE11_RX_WORK_STAT2_EO_PL = 0x8003900806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE11_RX_WORK_STAT2_EO_PL = 0x800390080601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE11_RX_WORK_STAT3_EO_PL = 0x8003980806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE11_RX_WORK_STAT3_EO_PL = 0x800398080601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE12_RX_DATA_WORK_SPARE_MODE_PL = 0x8003800406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE12_RX_DATA_WORK_SPARE_MODE_PL = 0x800380040601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE12_RX_WORK_STAT1_EO_PL = 0x8003880406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE12_RX_WORK_STAT1_EO_PL = 0x800388040601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE12_RX_WORK_STAT2_EO_PL = 0x8003900406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE12_RX_WORK_STAT2_EO_PL = 0x800390040601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE12_RX_WORK_STAT3_EO_PL = 0x8003980406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE12_RX_WORK_STAT3_EO_PL = 0x800398040601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE13_RX_DATA_WORK_SPARE_MODE_PL = 0x8003800206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE13_RX_DATA_WORK_SPARE_MODE_PL = 0x800380020601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE13_RX_WORK_STAT1_EO_PL = 0x8003880206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE13_RX_WORK_STAT1_EO_PL = 0x800388020601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE13_RX_WORK_STAT2_EO_PL = 0x8003900206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE13_RX_WORK_STAT2_EO_PL = 0x800390020601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE13_RX_WORK_STAT3_EO_PL = 0x8003980206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE13_RX_WORK_STAT3_EO_PL = 0x800398020601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE14_RX_DATA_WORK_SPARE_MODE_PL = 0x8003800506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE14_RX_DATA_WORK_SPARE_MODE_PL = 0x800380050601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE14_RX_WORK_STAT1_EO_PL = 0x8003880506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE14_RX_WORK_STAT1_EO_PL = 0x800388050601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE14_RX_WORK_STAT2_EO_PL = 0x8003900506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE14_RX_WORK_STAT2_EO_PL = 0x800390050601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE14_RX_WORK_STAT3_EO_PL = 0x8003980506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE14_RX_WORK_STAT3_EO_PL = 0x800398050601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE15_RX_DATA_WORK_SPARE_MODE_PL = 0x8003800306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE15_RX_DATA_WORK_SPARE_MODE_PL = 0x800380030601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE15_RX_WORK_STAT1_EO_PL = 0x8003880306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE15_RX_WORK_STAT1_EO_PL = 0x800388030601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE15_RX_WORK_STAT2_EO_PL = 0x8003900306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE15_RX_WORK_STAT2_EO_PL = 0x800390030601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE15_RX_WORK_STAT3_EO_PL = 0x8003980306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE15_RX_WORK_STAT3_EO_PL = 0x800398030601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE16_RX_DATA_WORK_SPARE_MODE_PL = 0x8003800006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE16_RX_DATA_WORK_SPARE_MODE_PL = 0x800380000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE16_RX_WORK_STAT1_EO_PL = 0x8003880006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE16_RX_WORK_STAT1_EO_PL = 0x800388000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE16_RX_WORK_STAT2_EO_PL = 0x8003900006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE16_RX_WORK_STAT2_EO_PL = 0x800390000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE16_RX_WORK_STAT3_EO_PL = 0x8003980006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE16_RX_WORK_STAT3_EO_PL = 0x800398000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE17_RX_DATA_WORK_SPARE_MODE_PL = 0x8003800106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE17_RX_DATA_WORK_SPARE_MODE_PL = 0x800380010601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE17_RX_WORK_STAT1_EO_PL = 0x8003880106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE17_RX_WORK_STAT1_EO_PL = 0x800388010601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE17_RX_WORK_STAT2_EO_PL = 0x8003900106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE17_RX_WORK_STAT2_EO_PL = 0x800390010601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE17_RX_WORK_STAT3_EO_PL = 0x8003980106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE17_RX_WORK_STAT3_EO_PL = 0x800398010601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE18_RX_DATA_WORK_SPARE_MODE_PL = 0x8003801206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE18_RX_DATA_WORK_SPARE_MODE_PL = 0x800380120601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE18_RX_WORK_STAT1_EO_PL = 0x8003881206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE18_RX_WORK_STAT1_EO_PL = 0x800388120601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE18_RX_WORK_STAT2_EO_PL = 0x8003901206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE18_RX_WORK_STAT2_EO_PL = 0x800390120601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE18_RX_WORK_STAT3_EO_PL = 0x8003981206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE18_RX_WORK_STAT3_EO_PL = 0x800398120601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE19_RX_DATA_WORK_SPARE_MODE_PL = 0x8003801306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE19_RX_DATA_WORK_SPARE_MODE_PL = 0x800380130601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE19_RX_WORK_STAT1_EO_PL = 0x8003881306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE19_RX_WORK_STAT1_EO_PL = 0x800388130601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE19_RX_WORK_STAT2_EO_PL = 0x8003901306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE19_RX_WORK_STAT2_EO_PL = 0x800390130601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE19_RX_WORK_STAT3_EO_PL = 0x8003981306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE19_RX_WORK_STAT3_EO_PL = 0x800398130601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE1_RX_DATA_WORK_SPARE_MODE_PL = 0x8003800F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE1_RX_DATA_WORK_SPARE_MODE_PL = 0x8003800F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE1_RX_WORK_STAT1_EO_PL = 0x8003880F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE1_RX_WORK_STAT1_EO_PL = 0x8003880F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE1_RX_WORK_STAT2_EO_PL = 0x8003900F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE1_RX_WORK_STAT2_EO_PL = 0x8003900F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE1_RX_WORK_STAT3_EO_PL = 0x8003980F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE1_RX_WORK_STAT3_EO_PL = 0x8003980F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE20_RX_DATA_WORK_SPARE_MODE_PL = 0x8003801406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE20_RX_DATA_WORK_SPARE_MODE_PL = 0x800380140601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE20_RX_WORK_STAT1_EO_PL = 0x8003881406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE20_RX_WORK_STAT1_EO_PL = 0x800388140601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE20_RX_WORK_STAT2_EO_PL = 0x8003901406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE20_RX_WORK_STAT2_EO_PL = 0x800390140601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE20_RX_WORK_STAT3_EO_PL = 0x8003981406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE20_RX_WORK_STAT3_EO_PL = 0x800398140601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE21_RX_DATA_WORK_SPARE_MODE_PL = 0x8003801506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE21_RX_DATA_WORK_SPARE_MODE_PL = 0x800380150601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE21_RX_WORK_STAT1_EO_PL = 0x8003881506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE21_RX_WORK_STAT1_EO_PL = 0x800388150601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE21_RX_WORK_STAT2_EO_PL = 0x8003901506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE21_RX_WORK_STAT2_EO_PL = 0x800390150601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE21_RX_WORK_STAT3_EO_PL = 0x8003981506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE21_RX_WORK_STAT3_EO_PL = 0x800398150601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE22_RX_DATA_WORK_SPARE_MODE_PL = 0x8003801606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE22_RX_DATA_WORK_SPARE_MODE_PL = 0x800380160601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE22_RX_WORK_STAT1_EO_PL = 0x8003881606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE22_RX_WORK_STAT1_EO_PL = 0x800388160601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE22_RX_WORK_STAT2_EO_PL = 0x8003901606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE22_RX_WORK_STAT2_EO_PL = 0x800390160601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE22_RX_WORK_STAT3_EO_PL = 0x8003981606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE22_RX_WORK_STAT3_EO_PL = 0x800398160601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE23_RX_DATA_WORK_SPARE_MODE_PL = 0x8003801706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE23_RX_DATA_WORK_SPARE_MODE_PL = 0x800380170601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE23_RX_WORK_STAT1_EO_PL = 0x8003881706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE23_RX_WORK_STAT1_EO_PL = 0x800388170601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE23_RX_WORK_STAT2_EO_PL = 0x8003901706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE23_RX_WORK_STAT2_EO_PL = 0x800390170601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE23_RX_WORK_STAT3_EO_PL = 0x8003981706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE23_RX_WORK_STAT3_EO_PL = 0x800398170601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE2_RX_DATA_WORK_SPARE_MODE_PL = 0x8003800E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE2_RX_DATA_WORK_SPARE_MODE_PL = 0x8003800E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE2_RX_WORK_STAT1_EO_PL = 0x8003880E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE2_RX_WORK_STAT1_EO_PL = 0x8003880E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE2_RX_WORK_STAT2_EO_PL = 0x8003900E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE2_RX_WORK_STAT2_EO_PL = 0x8003900E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE2_RX_WORK_STAT3_EO_PL = 0x8003980E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE2_RX_WORK_STAT3_EO_PL = 0x8003980E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE3_RX_DATA_WORK_SPARE_MODE_PL = 0x8003801006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE3_RX_DATA_WORK_SPARE_MODE_PL = 0x800380100601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE3_RX_WORK_STAT1_EO_PL = 0x8003881006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE3_RX_WORK_STAT1_EO_PL = 0x800388100601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE3_RX_WORK_STAT2_EO_PL = 0x8003901006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE3_RX_WORK_STAT2_EO_PL = 0x800390100601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE3_RX_WORK_STAT3_EO_PL = 0x8003981006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE3_RX_WORK_STAT3_EO_PL = 0x800398100601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE4_RX_DATA_WORK_SPARE_MODE_PL = 0x8003800B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE4_RX_DATA_WORK_SPARE_MODE_PL = 0x8003800B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE4_RX_WORK_STAT1_EO_PL = 0x8003880B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE4_RX_WORK_STAT1_EO_PL = 0x8003880B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE4_RX_WORK_STAT2_EO_PL = 0x8003900B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE4_RX_WORK_STAT2_EO_PL = 0x8003900B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE4_RX_WORK_STAT3_EO_PL = 0x8003980B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE4_RX_WORK_STAT3_EO_PL = 0x8003980B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE5_RX_DATA_WORK_SPARE_MODE_PL = 0x8003800906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE5_RX_DATA_WORK_SPARE_MODE_PL = 0x800380090601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE5_RX_WORK_STAT1_EO_PL = 0x8003880906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE5_RX_WORK_STAT1_EO_PL = 0x800388090601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE5_RX_WORK_STAT2_EO_PL = 0x8003900906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE5_RX_WORK_STAT2_EO_PL = 0x800390090601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE5_RX_WORK_STAT3_EO_PL = 0x8003980906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE5_RX_WORK_STAT3_EO_PL = 0x800398090601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE6_RX_DATA_WORK_SPARE_MODE_PL = 0x8003800C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE6_RX_DATA_WORK_SPARE_MODE_PL = 0x8003800C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE6_RX_WORK_STAT1_EO_PL = 0x8003880C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE6_RX_WORK_STAT1_EO_PL = 0x8003880C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE6_RX_WORK_STAT2_EO_PL = 0x8003900C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE6_RX_WORK_STAT2_EO_PL = 0x8003900C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE6_RX_WORK_STAT3_EO_PL = 0x8003980C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE6_RX_WORK_STAT3_EO_PL = 0x8003980C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE7_RX_DATA_WORK_SPARE_MODE_PL = 0x8003800A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE7_RX_DATA_WORK_SPARE_MODE_PL = 0x8003800A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE7_RX_WORK_STAT1_EO_PL = 0x8003880A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE7_RX_WORK_STAT1_EO_PL = 0x8003880A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE7_RX_WORK_STAT2_EO_PL = 0x8003900A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE7_RX_WORK_STAT2_EO_PL = 0x8003900A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE7_RX_WORK_STAT3_EO_PL = 0x8003980A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE7_RX_WORK_STAT3_EO_PL = 0x8003980A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE8_RX_DATA_WORK_SPARE_MODE_PL = 0x8003800706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE8_RX_DATA_WORK_SPARE_MODE_PL = 0x800380070601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE8_RX_WORK_STAT1_EO_PL = 0x8003880706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE8_RX_WORK_STAT1_EO_PL = 0x800388070601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE8_RX_WORK_STAT2_EO_PL = 0x8003900706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE8_RX_WORK_STAT2_EO_PL = 0x800390070601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE8_RX_WORK_STAT3_EO_PL = 0x8003980706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE8_RX_WORK_STAT3_EO_PL = 0x800398070601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE9_RX_DATA_WORK_SPARE_MODE_PL = 0x8003801106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE9_RX_DATA_WORK_SPARE_MODE_PL = 0x800380110601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE9_RX_WORK_STAT1_EO_PL = 0x8003881106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE9_RX_WORK_STAT1_EO_PL = 0x800388110601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE9_RX_WORK_STAT2_EO_PL = 0x8003901106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE9_RX_WORK_STAT2_EO_PL = 0x800390110601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX0_SLICE9_RX_WORK_STAT3_EO_PL = 0x8003981106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE9_RX_WORK_STAT3_EO_PL = 0x800398110601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL = 0x8003002106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL = 0x800300210601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL = 0x8002482106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL = 0x800248210601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL2_E_PL = 0x8003082106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL2_E_PL = 0x800308210601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL = 0x8002502106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL = 0x800250210601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL3_E_PL = 0x8003102106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL3_E_PL = 0x800310210601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL = 0x8002582106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL = 0x800258210601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL5_EO_PL = 0x8002602106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL5_EO_PL = 0x800260210601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL = 0x8002402106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL = 0x800240210601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL = 0x8002202106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL = 0x800220210601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE1_E_PL = 0x8002C02106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE1_E_PL = 0x8002C0210601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE2_EO_PL = 0x8002282106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE2_EO_PL = 0x800228210601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE2_E_PL = 0x8002C82106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE2_E_PL = 0x8002C8210601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL = 0x8002302106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL = 0x800230210601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT1_EO_PL = 0x8002682106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT1_EO_PL = 0x800268210601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL = 0x8002702106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL = 0x800270210601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL = 0x8002782106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL = 0x800278210601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL = 0x8000082106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL = 0x800008210601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL1_E_PL = 0x8000802106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL1_E_PL = 0x800080210601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL = 0x8000102106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL = 0x800010210601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL2_E_PL = 0x8000882106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL2_E_PL = 0x800088210601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL3_EO_PL = 0x8000182106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL3_EO_PL = 0x800018210601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL3_E_PL = 0x8000902106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL3_E_PL = 0x800090210601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL4_EO_PL = 0x8000202106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL4_EO_PL = 0x800020210601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL4_E_PL = 0x8000982106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL4_E_PL = 0x800098210601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL = 0x8000282106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL = 0x800028210601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL5_E_PL = 0x8000A02106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL5_E_PL = 0x8000A0210601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL6_EO_PL = 0x8000302106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL6_EO_PL = 0x800030210601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL6_E_PL = 0x8000A82106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL6_E_PL = 0x8000A8210601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL7_EO_PL = 0x8000382106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL7_EO_PL = 0x800038210601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL7_E_PL = 0x8000B02106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL7_E_PL = 0x8000B0210601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL8_EO_PL = 0x8000402106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL8_EO_PL = 0x800040210601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL8_E_PL = 0x8000B82106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL8_E_PL = 0x8000B8210601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL9_E_PL = 0x8000C02106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL9_E_PL = 0x8000C0210601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL = 0x8000002106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x800000210601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_FIR_ERROR_INJECT_PL = 0x8002182106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_FIR_ERROR_INJECT_PL = 0x800218210601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_FIR_MASK_PL = 0x8002102106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_FIR_MASK_PL = 0x800210210601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_FIR_PL = 0x8002082106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_FIR_PL = 0x800208210601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_SPARE_MODE_PL = 0x8002002106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_SPARE_MODE_PL = 0x800200210601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL = 0x8003002306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL = 0x800300230601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL = 0x8002482306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL = 0x800248230601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL2_E_PL = 0x8003082306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL2_E_PL = 0x800308230601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL = 0x8002502306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL = 0x800250230601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL3_E_PL = 0x8003102306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL3_E_PL = 0x800310230601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL = 0x8002582306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL = 0x800258230601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL5_EO_PL = 0x8002602306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL5_EO_PL = 0x800260230601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL = 0x8002402306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL = 0x800240230601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL = 0x8002202306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL = 0x800220230601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE1_E_PL = 0x8002C02306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE1_E_PL = 0x8002C0230601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE2_EO_PL = 0x8002282306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE2_EO_PL = 0x800228230601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE2_E_PL = 0x8002C82306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE2_E_PL = 0x8002C8230601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL = 0x8002302306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL = 0x800230230601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT1_EO_PL = 0x8002682306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT1_EO_PL = 0x800268230601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL = 0x8002702306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL = 0x800270230601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL = 0x8002782306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL = 0x800278230601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL = 0x8000082306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL = 0x800008230601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL1_E_PL = 0x8000802306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL1_E_PL = 0x800080230601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL = 0x8000102306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL = 0x800010230601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL2_E_PL = 0x8000882306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL2_E_PL = 0x800088230601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL3_EO_PL = 0x8000182306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL3_EO_PL = 0x800018230601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL3_E_PL = 0x8000902306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL3_E_PL = 0x800090230601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL4_EO_PL = 0x8000202306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL4_EO_PL = 0x800020230601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL4_E_PL = 0x8000982306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL4_E_PL = 0x800098230601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL = 0x8000282306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL = 0x800028230601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL5_E_PL = 0x8000A02306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL5_E_PL = 0x8000A0230601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL6_EO_PL = 0x8000302306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL6_EO_PL = 0x800030230601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL6_E_PL = 0x8000A82306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL6_E_PL = 0x8000A8230601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL7_EO_PL = 0x8000382306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL7_EO_PL = 0x800038230601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL7_E_PL = 0x8000B02306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL7_E_PL = 0x8000B0230601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL8_EO_PL = 0x8000402306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL8_EO_PL = 0x800040230601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL8_E_PL = 0x8000B82306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL8_E_PL = 0x8000B8230601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL9_E_PL = 0x8000C02306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL9_E_PL = 0x8000C0230601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL = 0x8000002306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x800000230601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_FIR_ERROR_INJECT_PL = 0x8002182306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_FIR_ERROR_INJECT_PL = 0x800218230601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_FIR_MASK_PL = 0x8002102306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_FIR_MASK_PL = 0x800210230601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_FIR_PL = 0x8002082306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_FIR_PL = 0x800208230601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_SPARE_MODE_PL = 0x8002002306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_SPARE_MODE_PL = 0x800200230601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL = 0x8003002006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL = 0x800300200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL = 0x8002482006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL = 0x800248200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL2_E_PL = 0x8003082006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL2_E_PL = 0x800308200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL = 0x8002502006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL = 0x800250200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL3_E_PL = 0x8003102006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL3_E_PL = 0x800310200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL = 0x8002582006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL = 0x800258200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL5_EO_PL = 0x8002602006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL5_EO_PL = 0x800260200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL = 0x8002402006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL = 0x800240200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL = 0x8002202006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL = 0x800220200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE1_E_PL = 0x8002C02006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE1_E_PL = 0x8002C0200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE2_EO_PL = 0x8002282006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE2_EO_PL = 0x800228200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE2_E_PL = 0x8002C82006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE2_E_PL = 0x8002C8200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL = 0x8002302006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL = 0x800230200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT1_EO_PL = 0x8002682006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT1_EO_PL = 0x800268200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL = 0x8002702006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL = 0x800270200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL = 0x8002782006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL = 0x800278200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL = 0x8000082006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL = 0x800008200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL1_E_PL = 0x8000802006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL1_E_PL = 0x800080200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL = 0x8000102006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL = 0x800010200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL2_E_PL = 0x8000882006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL2_E_PL = 0x800088200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL3_EO_PL = 0x8000182006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL3_EO_PL = 0x800018200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL3_E_PL = 0x8000902006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL3_E_PL = 0x800090200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL4_EO_PL = 0x8000202006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL4_EO_PL = 0x800020200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL4_E_PL = 0x8000982006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL4_E_PL = 0x800098200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL = 0x8000282006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL = 0x800028200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL5_E_PL = 0x8000A02006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL5_E_PL = 0x8000A0200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL6_EO_PL = 0x8000302006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL6_EO_PL = 0x800030200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL6_E_PL = 0x8000A82006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL6_E_PL = 0x8000A8200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL7_EO_PL = 0x8000382006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL7_EO_PL = 0x800038200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL7_E_PL = 0x8000B02006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL7_E_PL = 0x8000B0200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL8_EO_PL = 0x8000402006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL8_EO_PL = 0x800040200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL8_E_PL = 0x8000B82006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL8_E_PL = 0x8000B8200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL9_E_PL = 0x8000C02006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL9_E_PL = 0x8000C0200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL = 0x8000002006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x800000200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_FIR_ERROR_INJECT_PL = 0x8002182006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_FIR_ERROR_INJECT_PL = 0x800218200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_FIR_MASK_PL = 0x8002102006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_FIR_MASK_PL = 0x800210200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_FIR_PL = 0x8002082006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_FIR_PL = 0x800208200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_SPARE_MODE_PL = 0x8002002006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_SPARE_MODE_PL = 0x800200200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL = 0x8003002206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL = 0x800300220601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL = 0x8002482206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL = 0x800248220601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL2_E_PL = 0x8003082206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL2_E_PL = 0x800308220601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL = 0x8002502206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL = 0x800250220601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL3_E_PL = 0x8003102206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL3_E_PL = 0x800310220601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL = 0x8002582206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL = 0x800258220601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL5_EO_PL = 0x8002602206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL5_EO_PL = 0x800260220601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL = 0x8002402206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL = 0x800240220601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL = 0x8002202206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL = 0x800220220601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE1_E_PL = 0x8002C02206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE1_E_PL = 0x8002C0220601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE2_EO_PL = 0x8002282206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE2_EO_PL = 0x800228220601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE2_E_PL = 0x8002C82206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE2_E_PL = 0x8002C8220601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL = 0x8002302206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL = 0x800230220601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT1_EO_PL = 0x8002682206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT1_EO_PL = 0x800268220601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL = 0x8002702206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL = 0x800270220601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL = 0x8002782206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL = 0x800278220601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL = 0x8000082206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL = 0x800008220601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL1_E_PL = 0x8000802206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL1_E_PL = 0x800080220601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL = 0x8000102206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL = 0x800010220601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL2_E_PL = 0x8000882206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL2_E_PL = 0x800088220601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL3_EO_PL = 0x8000182206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL3_EO_PL = 0x800018220601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL3_E_PL = 0x8000902206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL3_E_PL = 0x800090220601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL4_EO_PL = 0x8000202206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL4_EO_PL = 0x800020220601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL4_E_PL = 0x8000982206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL4_E_PL = 0x800098220601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL = 0x8000282206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL = 0x800028220601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL5_E_PL = 0x8000A02206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL5_E_PL = 0x8000A0220601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL6_EO_PL = 0x8000302206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL6_EO_PL = 0x800030220601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL6_E_PL = 0x8000A82206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL6_E_PL = 0x8000A8220601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL7_EO_PL = 0x8000382206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL7_EO_PL = 0x800038220601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL7_E_PL = 0x8000B02206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL7_E_PL = 0x8000B0220601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL8_EO_PL = 0x8000402206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL8_EO_PL = 0x800040220601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL8_E_PL = 0x8000B82206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL8_E_PL = 0x8000B8220601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL9_E_PL = 0x8000C02206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL9_E_PL = 0x8000C0220601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL = 0x8000002206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x800000220601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_FIR_ERROR_INJECT_PL = 0x8002182206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_FIR_ERROR_INJECT_PL = 0x800218220601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_FIR_MASK_PL = 0x8002102206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_FIR_MASK_PL = 0x800210220601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_FIR_PL = 0x8002082206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_FIR_PL = 0x800208220601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_SPARE_MODE_PL = 0x8002002206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_SPARE_MODE_PL = 0x800200220601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL = 0x8003002706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL = 0x800300270601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL = 0x8002482706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL = 0x800248270601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL2_E_PL = 0x8003082706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL2_E_PL = 0x800308270601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL = 0x8002502706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL = 0x800250270601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL3_E_PL = 0x8003102706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL3_E_PL = 0x800310270601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL = 0x8002582706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL = 0x800258270601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL5_EO_PL = 0x8002602706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL5_EO_PL = 0x800260270601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL = 0x8002402706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL = 0x800240270601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL = 0x8002202706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL = 0x800220270601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE1_E_PL = 0x8002C02706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE1_E_PL = 0x8002C0270601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE2_EO_PL = 0x8002282706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE2_EO_PL = 0x800228270601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE2_E_PL = 0x8002C82706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE2_E_PL = 0x8002C8270601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL = 0x8002302706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL = 0x800230270601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT1_EO_PL = 0x8002682706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT1_EO_PL = 0x800268270601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL = 0x8002702706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL = 0x800270270601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL = 0x8002782706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL = 0x800278270601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL = 0x8000082706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL = 0x800008270601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL1_E_PL = 0x8000802706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL1_E_PL = 0x800080270601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL2_EO_PL = 0x8000102706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL2_EO_PL = 0x800010270601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL2_E_PL = 0x8000882706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL2_E_PL = 0x800088270601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL3_EO_PL = 0x8000182706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL3_EO_PL = 0x800018270601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL3_E_PL = 0x8000902706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL3_E_PL = 0x800090270601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL4_EO_PL = 0x8000202706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL4_EO_PL = 0x800020270601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL4_E_PL = 0x8000982706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL4_E_PL = 0x800098270601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL = 0x8000282706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL = 0x800028270601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL5_E_PL = 0x8000A02706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL5_E_PL = 0x8000A0270601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL6_EO_PL = 0x8000302706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL6_EO_PL = 0x800030270601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL6_E_PL = 0x8000A82706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL6_E_PL = 0x8000A8270601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL7_EO_PL = 0x8000382706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL7_EO_PL = 0x800038270601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL7_E_PL = 0x8000B02706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL7_E_PL = 0x8000B0270601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL8_EO_PL = 0x8000402706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL8_EO_PL = 0x800040270601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL8_E_PL = 0x8000B82706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL8_E_PL = 0x8000B8270601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL9_E_PL = 0x8000C02706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL9_E_PL = 0x8000C0270601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL = 0x8000002706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x800000270601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_FIR_ERROR_INJECT_PL = 0x8002182706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_FIR_ERROR_INJECT_PL = 0x800218270601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_FIR_MASK_PL = 0x8002102706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_FIR_MASK_PL = 0x800210270601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_FIR_PL = 0x8002082706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_FIR_PL = 0x800208270601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_SPARE_MODE_PL = 0x8002002706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_SPARE_MODE_PL = 0x800200270601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL = 0x8003002506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL = 0x800300250601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL = 0x8002482506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL = 0x800248250601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL2_E_PL = 0x8003082506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL2_E_PL = 0x800308250601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL = 0x8002502506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL = 0x800250250601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL3_E_PL = 0x8003102506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL3_E_PL = 0x800310250601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL = 0x8002582506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL = 0x800258250601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL5_EO_PL = 0x8002602506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL5_EO_PL = 0x800260250601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL = 0x8002402506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL = 0x800240250601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL = 0x8002202506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL = 0x800220250601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE1_E_PL = 0x8002C02506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE1_E_PL = 0x8002C0250601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE2_EO_PL = 0x8002282506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE2_EO_PL = 0x800228250601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE2_E_PL = 0x8002C82506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE2_E_PL = 0x8002C8250601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL = 0x8002302506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL = 0x800230250601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT1_EO_PL = 0x8002682506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT1_EO_PL = 0x800268250601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL = 0x8002702506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL = 0x800270250601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL = 0x8002782506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL = 0x800278250601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL = 0x8000082506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL = 0x800008250601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL1_E_PL = 0x8000802506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL1_E_PL = 0x800080250601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL2_EO_PL = 0x8000102506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL2_EO_PL = 0x800010250601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL2_E_PL = 0x8000882506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL2_E_PL = 0x800088250601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL3_EO_PL = 0x8000182506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL3_EO_PL = 0x800018250601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL3_E_PL = 0x8000902506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL3_E_PL = 0x800090250601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL4_EO_PL = 0x8000202506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL4_EO_PL = 0x800020250601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL4_E_PL = 0x8000982506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL4_E_PL = 0x800098250601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL = 0x8000282506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL = 0x800028250601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL5_E_PL = 0x8000A02506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL5_E_PL = 0x8000A0250601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL6_EO_PL = 0x8000302506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL6_EO_PL = 0x800030250601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL6_E_PL = 0x8000A82506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL6_E_PL = 0x8000A8250601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL7_EO_PL = 0x8000382506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL7_EO_PL = 0x800038250601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL7_E_PL = 0x8000B02506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL7_E_PL = 0x8000B0250601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL8_EO_PL = 0x8000402506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL8_EO_PL = 0x800040250601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL8_E_PL = 0x8000B82506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL8_E_PL = 0x8000B8250601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL9_E_PL = 0x8000C02506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL9_E_PL = 0x8000C0250601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL = 0x8000002506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x800000250601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_FIR_ERROR_INJECT_PL = 0x8002182506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_FIR_ERROR_INJECT_PL = 0x800218250601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_FIR_MASK_PL = 0x8002102506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_FIR_MASK_PL = 0x800210250601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_FIR_PL = 0x8002082506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_FIR_PL = 0x800208250601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_SPARE_MODE_PL = 0x8002002506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_SPARE_MODE_PL = 0x800200250601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL = 0x8003002606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL = 0x800300260601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL = 0x8002482606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL = 0x800248260601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL2_E_PL = 0x8003082606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL2_E_PL = 0x800308260601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL = 0x8002502606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL = 0x800250260601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL3_E_PL = 0x8003102606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL3_E_PL = 0x800310260601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL = 0x8002582606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL = 0x800258260601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL5_EO_PL = 0x8002602606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL5_EO_PL = 0x800260260601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL = 0x8002402606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL = 0x800240260601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL = 0x8002202606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL = 0x800220260601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE1_E_PL = 0x8002C02606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE1_E_PL = 0x8002C0260601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE2_EO_PL = 0x8002282606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE2_EO_PL = 0x800228260601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE2_E_PL = 0x8002C82606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE2_E_PL = 0x8002C8260601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL = 0x8002302606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL = 0x800230260601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT1_EO_PL = 0x8002682606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT1_EO_PL = 0x800268260601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL = 0x8002702606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL = 0x800270260601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL = 0x8002782606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL = 0x800278260601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL = 0x8000082606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL = 0x800008260601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL1_E_PL = 0x8000802606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL1_E_PL = 0x800080260601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL2_EO_PL = 0x8000102606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL2_EO_PL = 0x800010260601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL2_E_PL = 0x8000882606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL2_E_PL = 0x800088260601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL3_EO_PL = 0x8000182606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL3_EO_PL = 0x800018260601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL3_E_PL = 0x8000902606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL3_E_PL = 0x800090260601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL4_EO_PL = 0x8000202606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL4_EO_PL = 0x800020260601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL4_E_PL = 0x8000982606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL4_E_PL = 0x800098260601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL = 0x8000282606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL = 0x800028260601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL5_E_PL = 0x8000A02606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL5_E_PL = 0x8000A0260601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL6_EO_PL = 0x8000302606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL6_EO_PL = 0x800030260601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL6_E_PL = 0x8000A82606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL6_E_PL = 0x8000A8260601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL7_EO_PL = 0x8000382606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL7_EO_PL = 0x800038260601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL7_E_PL = 0x8000B02606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL7_E_PL = 0x8000B0260601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL8_EO_PL = 0x8000402606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL8_EO_PL = 0x800040260601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL8_E_PL = 0x8000B82606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL8_E_PL = 0x8000B8260601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL9_E_PL = 0x8000C02606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL9_E_PL = 0x8000C0260601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL = 0x8000002606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x800000260601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_FIR_ERROR_INJECT_PL = 0x8002182606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_FIR_ERROR_INJECT_PL = 0x800218260601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_FIR_MASK_PL = 0x8002102606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_FIR_MASK_PL = 0x800210260601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_FIR_PL = 0x8002082606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_FIR_PL = 0x800208260601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_SPARE_MODE_PL = 0x8002002606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_SPARE_MODE_PL = 0x800200260601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL = 0x8003002406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL = 0x800300240601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL = 0x8002482406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL = 0x800248240601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL2_E_PL = 0x8003082406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL2_E_PL = 0x800308240601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL = 0x8002502406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL = 0x800250240601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL3_E_PL = 0x8003102406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL3_E_PL = 0x800310240601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL = 0x8002582406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL = 0x800258240601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL5_EO_PL = 0x8002602406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL5_EO_PL = 0x800260240601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL = 0x8002402406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL = 0x800240240601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL = 0x8002202406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL = 0x800220240601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE1_E_PL = 0x8002C02406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE1_E_PL = 0x8002C0240601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE2_EO_PL = 0x8002282406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE2_EO_PL = 0x800228240601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE2_E_PL = 0x8002C82406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE2_E_PL = 0x8002C8240601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL = 0x8002302406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL = 0x800230240601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT1_EO_PL = 0x8002682406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT1_EO_PL = 0x800268240601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL = 0x8002702406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL = 0x800270240601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL = 0x8002782406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL = 0x800278240601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL = 0x8000082406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL = 0x800008240601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL1_E_PL = 0x8000802406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL1_E_PL = 0x800080240601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL2_EO_PL = 0x8000102406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL2_EO_PL = 0x800010240601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL2_E_PL = 0x8000882406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL2_E_PL = 0x800088240601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL3_EO_PL = 0x8000182406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL3_EO_PL = 0x800018240601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL3_E_PL = 0x8000902406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL3_E_PL = 0x800090240601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL4_EO_PL = 0x8000202406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL4_EO_PL = 0x800020240601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL4_E_PL = 0x8000982406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL4_E_PL = 0x800098240601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL = 0x8000282406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL = 0x800028240601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL5_E_PL = 0x8000A02406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL5_E_PL = 0x8000A0240601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL6_EO_PL = 0x8000302406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL6_EO_PL = 0x800030240601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL6_E_PL = 0x8000A82406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL6_E_PL = 0x8000A8240601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL7_EO_PL = 0x8000382406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL7_EO_PL = 0x800038240601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL7_E_PL = 0x8000B02406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL7_E_PL = 0x8000B0240601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL8_EO_PL = 0x8000402406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL8_EO_PL = 0x800040240601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL8_E_PL = 0x8000B82406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL8_E_PL = 0x8000B8240601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL9_E_PL = 0x8000C02406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL9_E_PL = 0x8000C0240601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL = 0x8000002406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x800000240601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_FIR_ERROR_INJECT_PL = 0x8002182406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_FIR_ERROR_INJECT_PL = 0x800218240601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_FIR_MASK_PL = 0x8002102406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_FIR_MASK_PL = 0x800210240601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_FIR_PL = 0x8002082406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_FIR_PL = 0x800208240601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_SPARE_MODE_PL = 0x8002002406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_SPARE_MODE_PL = 0x800200240601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL = 0x8003002806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL = 0x800300280601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL = 0x8002482806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL = 0x800248280601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL2_E_PL = 0x8003082806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL2_E_PL = 0x800308280601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL = 0x8002502806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL = 0x800250280601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL3_E_PL = 0x8003102806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL3_E_PL = 0x800310280601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL = 0x8002582806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL = 0x800258280601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL5_EO_PL = 0x8002602806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL5_EO_PL = 0x800260280601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL = 0x8002402806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL = 0x800240280601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL = 0x8002202806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL = 0x800220280601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE1_E_PL = 0x8002C02806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE1_E_PL = 0x8002C0280601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE2_EO_PL = 0x8002282806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE2_EO_PL = 0x800228280601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE2_E_PL = 0x8002C82806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE2_E_PL = 0x8002C8280601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL = 0x8002302806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL = 0x800230280601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT1_EO_PL = 0x8002682806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT1_EO_PL = 0x800268280601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL = 0x8002702806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL = 0x800270280601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL = 0x8002782806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL = 0x800278280601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL = 0x8000082806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL = 0x800008280601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL1_E_PL = 0x8000802806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL1_E_PL = 0x800080280601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL2_EO_PL = 0x8000102806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL2_EO_PL = 0x800010280601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL2_E_PL = 0x8000882806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL2_E_PL = 0x800088280601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL3_EO_PL = 0x8000182806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL3_EO_PL = 0x800018280601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL3_E_PL = 0x8000902806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL3_E_PL = 0x800090280601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL4_EO_PL = 0x8000202806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL4_EO_PL = 0x800020280601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL4_E_PL = 0x8000982806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL4_E_PL = 0x800098280601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL = 0x8000282806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL = 0x800028280601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL5_E_PL = 0x8000A02806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL5_E_PL = 0x8000A0280601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL6_EO_PL = 0x8000302806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL6_EO_PL = 0x800030280601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL6_E_PL = 0x8000A82806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL6_E_PL = 0x8000A8280601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL7_EO_PL = 0x8000382806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL7_EO_PL = 0x800038280601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL7_E_PL = 0x8000B02806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL7_E_PL = 0x8000B0280601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL8_EO_PL = 0x8000402806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL8_EO_PL = 0x800040280601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL8_E_PL = 0x8000B82806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL8_E_PL = 0x8000B8280601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL9_E_PL = 0x8000C02806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL9_E_PL = 0x8000C0280601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL = 0x8000002806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x800000280601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_FIR_ERROR_INJECT_PL = 0x8002182806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_FIR_ERROR_INJECT_PL = 0x800218280601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_FIR_MASK_PL = 0x8002102806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_FIR_MASK_PL = 0x800210280601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_FIR_PL = 0x8002082806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_FIR_PL = 0x800208280601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_SPARE_MODE_PL = 0x8002002806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_SPARE_MODE_PL = 0x800200280601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL = 0x8003002A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL = 0x8003002A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL = 0x8002482A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL = 0x8002482A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL2_E_PL = 0x8003082A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL2_E_PL = 0x8003082A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL = 0x8002502A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL = 0x8002502A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL3_E_PL = 0x8003102A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL3_E_PL = 0x8003102A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL = 0x8002582A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL = 0x8002582A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL5_EO_PL = 0x8002602A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL5_EO_PL = 0x8002602A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL = 0x8002402A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL = 0x8002402A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL = 0x8002202A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL = 0x8002202A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE1_E_PL = 0x8002C02A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE1_E_PL = 0x8002C02A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE2_EO_PL = 0x8002282A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE2_EO_PL = 0x8002282A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE2_E_PL = 0x8002C82A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE2_E_PL = 0x8002C82A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL = 0x8002302A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL = 0x8002302A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT1_EO_PL = 0x8002682A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT1_EO_PL = 0x8002682A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL = 0x8002702A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL = 0x8002702A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL = 0x8002782A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL = 0x8002782A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL = 0x8000082A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL = 0x8000082A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL1_E_PL = 0x8000802A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL1_E_PL = 0x8000802A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL2_EO_PL = 0x8000102A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL2_EO_PL = 0x8000102A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL2_E_PL = 0x8000882A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL2_E_PL = 0x8000882A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL3_EO_PL = 0x8000182A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL3_EO_PL = 0x8000182A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL3_E_PL = 0x8000902A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL3_E_PL = 0x8000902A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL4_EO_PL = 0x8000202A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL4_EO_PL = 0x8000202A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL4_E_PL = 0x8000982A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL4_E_PL = 0x8000982A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL = 0x8000282A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL = 0x8000282A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL5_E_PL = 0x8000A02A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL5_E_PL = 0x8000A02A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL6_EO_PL = 0x8000302A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL6_EO_PL = 0x8000302A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL6_E_PL = 0x8000A82A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL6_E_PL = 0x8000A82A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL7_EO_PL = 0x8000382A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL7_EO_PL = 0x8000382A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL7_E_PL = 0x8000B02A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL7_E_PL = 0x8000B02A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL8_EO_PL = 0x8000402A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL8_EO_PL = 0x8000402A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL8_E_PL = 0x8000B82A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL8_E_PL = 0x8000B82A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL9_E_PL = 0x8000C02A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL9_E_PL = 0x8000C02A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL = 0x8000002A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x8000002A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_FIR_ERROR_INJECT_PL = 0x8002182A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_FIR_ERROR_INJECT_PL = 0x8002182A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_FIR_MASK_PL = 0x8002102A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_FIR_MASK_PL = 0x8002102A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_FIR_PL = 0x8002082A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_FIR_PL = 0x8002082A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_SPARE_MODE_PL = 0x8002002A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_SPARE_MODE_PL = 0x8002002A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL = 0x8003002906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL = 0x800300290601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL = 0x8002482906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL = 0x800248290601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL2_E_PL = 0x8003082906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL2_E_PL = 0x800308290601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL = 0x8002502906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL = 0x800250290601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL3_E_PL = 0x8003102906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL3_E_PL = 0x800310290601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL = 0x8002582906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL = 0x800258290601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL5_EO_PL = 0x8002602906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL5_EO_PL = 0x800260290601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL = 0x8002402906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL = 0x800240290601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL = 0x8002202906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL = 0x800220290601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE1_E_PL = 0x8002C02906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE1_E_PL = 0x8002C0290601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE2_EO_PL = 0x8002282906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE2_EO_PL = 0x800228290601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE2_E_PL = 0x8002C82906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE2_E_PL = 0x8002C8290601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL = 0x8002302906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL = 0x800230290601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT1_EO_PL = 0x8002682906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT1_EO_PL = 0x800268290601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL = 0x8002702906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL = 0x800270290601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL = 0x8002782906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL = 0x800278290601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL = 0x8000082906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL = 0x800008290601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL1_E_PL = 0x8000802906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL1_E_PL = 0x800080290601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL2_EO_PL = 0x8000102906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL2_EO_PL = 0x800010290601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL2_E_PL = 0x8000882906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL2_E_PL = 0x800088290601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL3_EO_PL = 0x8000182906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL3_EO_PL = 0x800018290601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL3_E_PL = 0x8000902906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL3_E_PL = 0x800090290601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL4_EO_PL = 0x8000202906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL4_EO_PL = 0x800020290601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL4_E_PL = 0x8000982906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL4_E_PL = 0x800098290601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL = 0x8000282906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL = 0x800028290601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL5_E_PL = 0x8000A02906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL5_E_PL = 0x8000A0290601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL6_EO_PL = 0x8000302906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL6_EO_PL = 0x800030290601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL6_E_PL = 0x8000A82906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL6_E_PL = 0x8000A8290601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL7_EO_PL = 0x8000382906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL7_EO_PL = 0x800038290601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL7_E_PL = 0x8000B02906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL7_E_PL = 0x8000B0290601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL8_EO_PL = 0x8000402906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL8_EO_PL = 0x800040290601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL8_E_PL = 0x8000B82906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL8_E_PL = 0x8000B8290601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL9_E_PL = 0x8000C02906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL9_E_PL = 0x8000C0290601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL = 0x8000002906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x800000290601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_FIR_ERROR_INJECT_PL = 0x8002182906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_FIR_ERROR_INJECT_PL = 0x800218290601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_FIR_MASK_PL = 0x8002102906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_FIR_MASK_PL = 0x800210290601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_FIR_PL = 0x8002082906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_FIR_PL = 0x800208290601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_SPARE_MODE_PL = 0x8002002906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_SPARE_MODE_PL = 0x800200290601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL = 0x8003003106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL = 0x800300310601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL = 0x8002483106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL = 0x800248310601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL2_E_PL = 0x8003083106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL2_E_PL = 0x800308310601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL = 0x8002503106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL = 0x800250310601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL3_E_PL = 0x8003103106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL3_E_PL = 0x800310310601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL = 0x8002583106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL = 0x800258310601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL5_EO_PL = 0x8002603106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL5_EO_PL = 0x800260310601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL = 0x8002403106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL = 0x800240310601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL = 0x8002203106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL = 0x800220310601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE1_E_PL = 0x8002C03106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE1_E_PL = 0x8002C0310601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE2_EO_PL = 0x8002283106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE2_EO_PL = 0x800228310601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE2_E_PL = 0x8002C83106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE2_E_PL = 0x8002C8310601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL = 0x8002303106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL = 0x800230310601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT1_EO_PL = 0x8002683106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT1_EO_PL = 0x800268310601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL = 0x8002703106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL = 0x800270310601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL = 0x8002783106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL = 0x800278310601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL = 0x8000083106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL = 0x800008310601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL1_E_PL = 0x8000803106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL1_E_PL = 0x800080310601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL2_EO_PL = 0x8000103106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL2_EO_PL = 0x800010310601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL2_E_PL = 0x8000883106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL2_E_PL = 0x800088310601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL3_EO_PL = 0x8000183106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL3_EO_PL = 0x800018310601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL3_E_PL = 0x8000903106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL3_E_PL = 0x800090310601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL4_EO_PL = 0x8000203106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL4_EO_PL = 0x800020310601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL4_E_PL = 0x8000983106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL4_E_PL = 0x800098310601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL = 0x8000283106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL = 0x800028310601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL5_E_PL = 0x8000A03106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL5_E_PL = 0x8000A0310601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL6_EO_PL = 0x8000303106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL6_EO_PL = 0x800030310601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL6_E_PL = 0x8000A83106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL6_E_PL = 0x8000A8310601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL7_EO_PL = 0x8000383106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL7_EO_PL = 0x800038310601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL7_E_PL = 0x8000B03106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL7_E_PL = 0x8000B0310601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL8_EO_PL = 0x8000403106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL8_EO_PL = 0x800040310601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL8_E_PL = 0x8000B83106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL8_E_PL = 0x8000B8310601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL9_E_PL = 0x8000C03106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL9_E_PL = 0x8000C0310601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL = 0x8000003106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x800000310601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_FIR_ERROR_INJECT_PL = 0x8002183106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_FIR_ERROR_INJECT_PL = 0x800218310601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_FIR_MASK_PL = 0x8002103106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_FIR_MASK_PL = 0x800210310601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_FIR_PL = 0x8002083106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_FIR_PL = 0x800208310601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_SPARE_MODE_PL = 0x8002003106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_SPARE_MODE_PL = 0x800200310601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL = 0x8003002E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL = 0x8003002E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL = 0x8002482E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL = 0x8002482E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL2_E_PL = 0x8003082E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL2_E_PL = 0x8003082E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL = 0x8002502E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL = 0x8002502E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL3_E_PL = 0x8003102E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL3_E_PL = 0x8003102E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL = 0x8002582E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL = 0x8002582E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL5_EO_PL = 0x8002602E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL5_EO_PL = 0x8002602E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL = 0x8002402E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL = 0x8002402E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL = 0x8002202E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL = 0x8002202E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE1_E_PL = 0x8002C02E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE1_E_PL = 0x8002C02E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE2_EO_PL = 0x8002282E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE2_EO_PL = 0x8002282E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE2_E_PL = 0x8002C82E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE2_E_PL = 0x8002C82E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL = 0x8002302E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL = 0x8002302E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT1_EO_PL = 0x8002682E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT1_EO_PL = 0x8002682E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL = 0x8002702E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL = 0x8002702E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL = 0x8002782E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL = 0x8002782E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL = 0x8000082E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL = 0x8000082E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL1_E_PL = 0x8000802E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL1_E_PL = 0x8000802E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL2_EO_PL = 0x8000102E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL2_EO_PL = 0x8000102E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL2_E_PL = 0x8000882E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL2_E_PL = 0x8000882E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL3_EO_PL = 0x8000182E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL3_EO_PL = 0x8000182E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL3_E_PL = 0x8000902E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL3_E_PL = 0x8000902E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL4_EO_PL = 0x8000202E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL4_EO_PL = 0x8000202E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL4_E_PL = 0x8000982E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL4_E_PL = 0x8000982E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL = 0x8000282E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL = 0x8000282E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL5_E_PL = 0x8000A02E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL5_E_PL = 0x8000A02E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL6_EO_PL = 0x8000302E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL6_EO_PL = 0x8000302E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL6_E_PL = 0x8000A82E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL6_E_PL = 0x8000A82E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL7_EO_PL = 0x8000382E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL7_EO_PL = 0x8000382E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL7_E_PL = 0x8000B02E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL7_E_PL = 0x8000B02E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL8_EO_PL = 0x8000402E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL8_EO_PL = 0x8000402E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL8_E_PL = 0x8000B82E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL8_E_PL = 0x8000B82E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL9_E_PL = 0x8000C02E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL9_E_PL = 0x8000C02E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL = 0x8000002E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x8000002E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_FIR_ERROR_INJECT_PL = 0x8002182E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_FIR_ERROR_INJECT_PL = 0x8002182E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_FIR_MASK_PL = 0x8002102E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_FIR_MASK_PL = 0x8002102E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_FIR_PL = 0x8002082E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_FIR_PL = 0x8002082E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_SPARE_MODE_PL = 0x8002002E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_SPARE_MODE_PL = 0x8002002E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL = 0x8003002C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL = 0x8003002C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL = 0x8002482C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL = 0x8002482C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL2_E_PL = 0x8003082C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL2_E_PL = 0x8003082C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL = 0x8002502C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL = 0x8002502C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL3_E_PL = 0x8003102C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL3_E_PL = 0x8003102C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL = 0x8002582C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL = 0x8002582C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL5_EO_PL = 0x8002602C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL5_EO_PL = 0x8002602C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL = 0x8002402C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL = 0x8002402C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL = 0x8002202C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL = 0x8002202C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE1_E_PL = 0x8002C02C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE1_E_PL = 0x8002C02C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE2_EO_PL = 0x8002282C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE2_EO_PL = 0x8002282C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE2_E_PL = 0x8002C82C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE2_E_PL = 0x8002C82C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL = 0x8002302C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL = 0x8002302C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT1_EO_PL = 0x8002682C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT1_EO_PL = 0x8002682C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL = 0x8002702C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL = 0x8002702C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL = 0x8002782C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL = 0x8002782C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL = 0x8000082C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL = 0x8000082C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL1_E_PL = 0x8000802C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL1_E_PL = 0x8000802C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL2_EO_PL = 0x8000102C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL2_EO_PL = 0x8000102C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL2_E_PL = 0x8000882C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL2_E_PL = 0x8000882C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL3_EO_PL = 0x8000182C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL3_EO_PL = 0x8000182C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL3_E_PL = 0x8000902C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL3_E_PL = 0x8000902C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL4_EO_PL = 0x8000202C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL4_EO_PL = 0x8000202C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL4_E_PL = 0x8000982C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL4_E_PL = 0x8000982C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL = 0x8000282C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL = 0x8000282C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL5_E_PL = 0x8000A02C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL5_E_PL = 0x8000A02C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL6_EO_PL = 0x8000302C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL6_EO_PL = 0x8000302C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL6_E_PL = 0x8000A82C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL6_E_PL = 0x8000A82C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL7_EO_PL = 0x8000382C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL7_EO_PL = 0x8000382C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL7_E_PL = 0x8000B02C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL7_E_PL = 0x8000B02C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL8_EO_PL = 0x8000402C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL8_EO_PL = 0x8000402C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL8_E_PL = 0x8000B82C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL8_E_PL = 0x8000B82C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL9_E_PL = 0x8000C02C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL9_E_PL = 0x8000C02C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL = 0x8000002C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x8000002C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_FIR_ERROR_INJECT_PL = 0x8002182C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_FIR_ERROR_INJECT_PL = 0x8002182C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_FIR_MASK_PL = 0x8002102C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_FIR_MASK_PL = 0x8002102C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_FIR_PL = 0x8002082C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_FIR_PL = 0x8002082C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_SPARE_MODE_PL = 0x8002002C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_SPARE_MODE_PL = 0x8002002C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL = 0x8003002D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL = 0x8003002D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL = 0x8002482D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL = 0x8002482D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL2_E_PL = 0x8003082D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL2_E_PL = 0x8003082D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL = 0x8002502D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL = 0x8002502D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL3_E_PL = 0x8003102D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL3_E_PL = 0x8003102D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL = 0x8002582D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL = 0x8002582D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL5_EO_PL = 0x8002602D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL5_EO_PL = 0x8002602D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL = 0x8002402D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL = 0x8002402D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL = 0x8002202D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL = 0x8002202D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE1_E_PL = 0x8002C02D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE1_E_PL = 0x8002C02D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE2_EO_PL = 0x8002282D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE2_EO_PL = 0x8002282D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE2_E_PL = 0x8002C82D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE2_E_PL = 0x8002C82D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL = 0x8002302D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL = 0x8002302D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT1_EO_PL = 0x8002682D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT1_EO_PL = 0x8002682D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL = 0x8002702D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL = 0x8002702D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL = 0x8002782D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL = 0x8002782D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL = 0x8000082D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL = 0x8000082D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL1_E_PL = 0x8000802D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL1_E_PL = 0x8000802D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL2_EO_PL = 0x8000102D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL2_EO_PL = 0x8000102D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL2_E_PL = 0x8000882D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL2_E_PL = 0x8000882D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL3_EO_PL = 0x8000182D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL3_EO_PL = 0x8000182D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL3_E_PL = 0x8000902D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL3_E_PL = 0x8000902D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL4_EO_PL = 0x8000202D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL4_EO_PL = 0x8000202D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL4_E_PL = 0x8000982D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL4_E_PL = 0x8000982D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL = 0x8000282D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL = 0x8000282D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL5_E_PL = 0x8000A02D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL5_E_PL = 0x8000A02D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL6_EO_PL = 0x8000302D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL6_EO_PL = 0x8000302D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL6_E_PL = 0x8000A82D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL6_E_PL = 0x8000A82D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL7_EO_PL = 0x8000382D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL7_EO_PL = 0x8000382D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL7_E_PL = 0x8000B02D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL7_E_PL = 0x8000B02D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL8_EO_PL = 0x8000402D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL8_EO_PL = 0x8000402D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL8_E_PL = 0x8000B82D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL8_E_PL = 0x8000B82D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL9_E_PL = 0x8000C02D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL9_E_PL = 0x8000C02D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL = 0x8000002D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x8000002D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_FIR_ERROR_INJECT_PL = 0x8002182D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_FIR_ERROR_INJECT_PL = 0x8002182D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_FIR_MASK_PL = 0x8002102D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_FIR_MASK_PL = 0x8002102D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_FIR_PL = 0x8002082D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_FIR_PL = 0x8002082D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_SPARE_MODE_PL = 0x8002002D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_SPARE_MODE_PL = 0x8002002D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL = 0x8003002B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL = 0x8003002B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL = 0x8002482B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL = 0x8002482B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL2_E_PL = 0x8003082B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL2_E_PL = 0x8003082B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL = 0x8002502B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL = 0x8002502B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL3_E_PL = 0x8003102B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL3_E_PL = 0x8003102B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL = 0x8002582B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL = 0x8002582B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL5_EO_PL = 0x8002602B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL5_EO_PL = 0x8002602B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL = 0x8002402B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL = 0x8002402B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL = 0x8002202B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL = 0x8002202B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE1_E_PL = 0x8002C02B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE1_E_PL = 0x8002C02B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE2_EO_PL = 0x8002282B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE2_EO_PL = 0x8002282B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE2_E_PL = 0x8002C82B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE2_E_PL = 0x8002C82B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL = 0x8002302B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL = 0x8002302B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT1_EO_PL = 0x8002682B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT1_EO_PL = 0x8002682B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL = 0x8002702B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL = 0x8002702B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL = 0x8002782B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL = 0x8002782B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL = 0x8000082B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL = 0x8000082B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL1_E_PL = 0x8000802B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL1_E_PL = 0x8000802B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL2_EO_PL = 0x8000102B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL2_EO_PL = 0x8000102B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL2_E_PL = 0x8000882B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL2_E_PL = 0x8000882B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL3_EO_PL = 0x8000182B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL3_EO_PL = 0x8000182B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL3_E_PL = 0x8000902B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL3_E_PL = 0x8000902B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL4_EO_PL = 0x8000202B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL4_EO_PL = 0x8000202B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL4_E_PL = 0x8000982B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL4_E_PL = 0x8000982B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL = 0x8000282B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL = 0x8000282B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL5_E_PL = 0x8000A02B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL5_E_PL = 0x8000A02B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL6_EO_PL = 0x8000302B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL6_EO_PL = 0x8000302B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL6_E_PL = 0x8000A82B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL6_E_PL = 0x8000A82B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL7_EO_PL = 0x8000382B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL7_EO_PL = 0x8000382B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL7_E_PL = 0x8000B02B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL7_E_PL = 0x8000B02B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL8_EO_PL = 0x8000402B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL8_EO_PL = 0x8000402B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL8_E_PL = 0x8000B82B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL8_E_PL = 0x8000B82B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL9_E_PL = 0x8000C02B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL9_E_PL = 0x8000C02B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL = 0x8000002B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x8000002B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_FIR_ERROR_INJECT_PL = 0x8002182B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_FIR_ERROR_INJECT_PL = 0x8002182B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_FIR_MASK_PL = 0x8002102B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_FIR_MASK_PL = 0x8002102B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_FIR_PL = 0x8002082B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_FIR_PL = 0x8002082B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_SPARE_MODE_PL = 0x8002002B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_SPARE_MODE_PL = 0x8002002B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL = 0x8003002F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL = 0x8003002F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL2_EO_PL = 0x8002482F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL2_EO_PL = 0x8002482F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL2_E_PL = 0x8003082F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL2_E_PL = 0x8003082F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL3_EO_PL = 0x8002502F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL3_EO_PL = 0x8002502F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL3_E_PL = 0x8003102F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL3_E_PL = 0x8003102F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL4_EO_PL = 0x8002582F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL4_EO_PL = 0x8002582F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL5_EO_PL = 0x8002602F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL5_EO_PL = 0x8002602F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL = 0x8002402F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL = 0x8002402F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE1_EO_PL = 0x8002202F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE1_EO_PL = 0x8002202F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE1_E_PL = 0x8002C02F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE1_E_PL = 0x8002C02F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE2_EO_PL = 0x8002282F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE2_EO_PL = 0x8002282F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE2_E_PL = 0x8002C82F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE2_E_PL = 0x8002C82F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE3_EO_PL = 0x8002302F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE3_EO_PL = 0x8002302F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT1_EO_PL = 0x8002682F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT1_EO_PL = 0x8002682F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT2_EO_PL = 0x8002702F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT2_EO_PL = 0x8002702F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT3_EO_PL = 0x8002782F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT3_EO_PL = 0x8002782F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL1_EO_PL = 0x8000082F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL1_EO_PL = 0x8000082F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL1_E_PL = 0x8000802F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL1_E_PL = 0x8000802F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL2_EO_PL = 0x8000102F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL2_EO_PL = 0x8000102F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL2_E_PL = 0x8000882F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL2_E_PL = 0x8000882F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL3_EO_PL = 0x8000182F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL3_EO_PL = 0x8000182F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL3_E_PL = 0x8000902F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL3_E_PL = 0x8000902F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL4_EO_PL = 0x8000202F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL4_EO_PL = 0x8000202F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL4_E_PL = 0x8000982F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL4_E_PL = 0x8000982F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL5_EO_PL = 0x8000282F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL5_EO_PL = 0x8000282F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL5_E_PL = 0x8000A02F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL5_E_PL = 0x8000A02F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL6_EO_PL = 0x8000302F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL6_EO_PL = 0x8000302F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL6_E_PL = 0x8000A82F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL6_E_PL = 0x8000A82F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL7_EO_PL = 0x8000382F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL7_EO_PL = 0x8000382F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL7_E_PL = 0x8000B02F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL7_E_PL = 0x8000B02F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL8_EO_PL = 0x8000402F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL8_EO_PL = 0x8000402F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL8_E_PL = 0x8000B82F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL8_E_PL = 0x8000B82F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL9_E_PL = 0x8000C02F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL9_E_PL = 0x8000C02F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DATA_DAC_SPARE_MODE_PL = 0x8000002F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x8000002F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_FIR_ERROR_INJECT_PL = 0x8002182F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_FIR_ERROR_INJECT_PL = 0x8002182F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_FIR_MASK_PL = 0x8002102F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_FIR_MASK_PL = 0x8002102F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_FIR_PL = 0x8002082F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_FIR_PL = 0x8002082F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_SPARE_MODE_PL = 0x8002002F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_SPARE_MODE_PL = 0x8002002F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL = 0x8003003006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL = 0x800300300601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL2_EO_PL = 0x8002483006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL2_EO_PL = 0x800248300601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL2_E_PL = 0x8003083006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL2_E_PL = 0x800308300601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL3_EO_PL = 0x8002503006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL3_EO_PL = 0x800250300601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL3_E_PL = 0x8003103006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL3_E_PL = 0x800310300601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL4_EO_PL = 0x8002583006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL4_EO_PL = 0x800258300601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL5_EO_PL = 0x8002603006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL5_EO_PL = 0x800260300601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL = 0x8002403006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL = 0x800240300601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE1_EO_PL = 0x8002203006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE1_EO_PL = 0x800220300601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE1_E_PL = 0x8002C03006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE1_E_PL = 0x8002C0300601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE2_EO_PL = 0x8002283006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE2_EO_PL = 0x800228300601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE2_E_PL = 0x8002C83006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE2_E_PL = 0x8002C8300601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE3_EO_PL = 0x8002303006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE3_EO_PL = 0x800230300601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT1_EO_PL = 0x8002683006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT1_EO_PL = 0x800268300601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT2_EO_PL = 0x8002703006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT2_EO_PL = 0x800270300601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT3_EO_PL = 0x8002783006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT3_EO_PL = 0x800278300601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL1_EO_PL = 0x8000083006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL1_EO_PL = 0x800008300601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL1_E_PL = 0x8000803006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL1_E_PL = 0x800080300601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL2_EO_PL = 0x8000103006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL2_EO_PL = 0x800010300601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL2_E_PL = 0x8000883006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL2_E_PL = 0x800088300601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL3_EO_PL = 0x8000183006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL3_EO_PL = 0x800018300601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL3_E_PL = 0x8000903006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL3_E_PL = 0x800090300601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL4_EO_PL = 0x8000203006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL4_EO_PL = 0x800020300601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL4_E_PL = 0x8000983006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL4_E_PL = 0x800098300601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL5_EO_PL = 0x8000283006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL5_EO_PL = 0x800028300601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL5_E_PL = 0x8000A03006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL5_E_PL = 0x8000A0300601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL6_EO_PL = 0x8000303006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL6_EO_PL = 0x800030300601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL6_E_PL = 0x8000A83006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL6_E_PL = 0x8000A8300601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL7_EO_PL = 0x8000383006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL7_EO_PL = 0x800038300601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL7_E_PL = 0x8000B03006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL7_E_PL = 0x8000B0300601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL8_EO_PL = 0x8000403006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL8_EO_PL = 0x800040300601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL8_E_PL = 0x8000B83006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL8_E_PL = 0x8000B8300601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL9_E_PL = 0x8000C03006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL9_E_PL = 0x8000C0300601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DATA_DAC_SPARE_MODE_PL = 0x8000003006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x800000300601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_FIR_ERROR_INJECT_PL = 0x8002183006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_FIR_ERROR_INJECT_PL = 0x800218300601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_FIR_MASK_PL = 0x8002103006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_FIR_MASK_PL = 0x800210300601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_FIR_PL = 0x8002083006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_FIR_PL = 0x800208300601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_SPARE_MODE_PL = 0x8002003006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_SPARE_MODE_PL = 0x800200300601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL10_EO_PG = 0x8009202006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL10_EO_PG = 0x800920200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL11_EO_PG = 0x8009282006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL11_EO_PG = 0x800928200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL12_EO_PG = 0x8009302006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL12_EO_PG = 0x800930200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL13_EO_PG = 0x8009382006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL13_EO_PG = 0x800938200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL14_EO_PG = 0x8009402006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL14_EO_PG = 0x800940200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL15_EO_PG = 0x8009482006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL15_EO_PG = 0x800948200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL1_EO_PG = 0x8008D82006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL1_EO_PG = 0x8008D8200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL1_E_PG = 0x8009F02006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL1_E_PG = 0x8009F0200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL2_EO_PG = 0x8008E02006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL2_EO_PG = 0x8008E0200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL3_EO_PG = 0x8008E82006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL3_EO_PG = 0x8008E8200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL4_EO_PG = 0x8008F02006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL4_EO_PG = 0x8008F0200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL4_E_PG = 0x8009F82006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL4_E_PG = 0x8009F8200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL5_EO_PG = 0x8008F82006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL5_EO_PG = 0x8008F8200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL6_EO_PG = 0x8009002006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL6_EO_PG = 0x800900200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL8_EO_PG = 0x8009102006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL8_EO_PG = 0x800910200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL9_EO_PG = 0x8009182006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL9_EO_PG = 0x800918200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTLX11_E_PG = 0x800A302006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTLX11_E_PG = 0x800A30200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTLX7_EO_PG = 0x8009082006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTLX7_EO_PG = 0x800908200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE10_EO_PG = 0x8008582006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE10_EO_PG = 0x800858200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE10_E_PG = 0x8009D82006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE10_E_PG = 0x8009D8200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE11_EO_PG = 0x8008602006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE11_EO_PG = 0x800860200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE11_E_PG = 0x8009E02006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE11_E_PG = 0x8009E0200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE12_EO_PG = 0x8008682006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE12_EO_PG = 0x800868200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE12_E_PG = 0x8009E82006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE12_E_PG = 0x8009E8200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE13_EO_PG = 0x8008702006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE13_EO_PG = 0x800870200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE14_EO_PG = 0x8008782006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE14_EO_PG = 0x800878200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE15_EO_PG = 0x8008802006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE15_EO_PG = 0x800880200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE16_EO_PG = 0x8008882006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE16_EO_PG = 0x800888200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE17_EO_PG = 0x8008902006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE17_EO_PG = 0x800890200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE18_EO_PG = 0x8008982006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE18_EO_PG = 0x800898200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE19_EO_PG = 0x8008A02006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE19_EO_PG = 0x8008A0200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE1_EO_PG = 0x8008102006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE1_EO_PG = 0x800810200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE1_E_PG = 0x8009902006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE1_E_PG = 0x800990200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE20_EO_PG = 0x8008A82006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE20_EO_PG = 0x8008A8200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE21_EO_PG = 0x8008B02006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE21_EO_PG = 0x8008B0200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE22_EO_PG = 0x8008B82006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE22_EO_PG = 0x8008B8200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE23_EO_PG = 0x8008C02006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE23_EO_PG = 0x8008C0200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE24_EO_PG = 0x8008C82006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE24_EO_PG = 0x8008C8200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE26_EO_PG = 0x8009682006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE26_EO_PG = 0x800968200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE27_EO_PG = 0x8009702006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE27_EO_PG = 0x800970200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE28_EO_PG = 0x8009782006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE28_EO_PG = 0x800978200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE29_EO_PG = 0x8008D02006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE29_EO_PG = 0x8008D0200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE2_EO_PG = 0x8008182006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE2_EO_PG = 0x800818200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE2_E_PG = 0x8009982006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE2_E_PG = 0x800998200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE3_EO_PG = 0x8008202006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE3_EO_PG = 0x800820200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE3_E_PG = 0x8009A02006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE3_E_PG = 0x8009A0200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE4_EO_PG = 0x8008282006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE4_EO_PG = 0x800828200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE4_E_PG = 0x8009A82006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE4_E_PG = 0x8009A8200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE5_EO_PG = 0x8008302006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE5_EO_PG = 0x800830200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE5_E_PG = 0x8009B02006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE5_E_PG = 0x8009B0200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE6_EO_PG = 0x8008382006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE6_EO_PG = 0x800838200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE6_E_PG = 0x8009B82006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE6_E_PG = 0x8009B8200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE7_EO_PG = 0x8008402006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE7_EO_PG = 0x800840200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE7_E_PG = 0x8009C02006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE7_E_PG = 0x8009C0200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE8_EO_PG = 0x8008482006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE8_EO_PG = 0x800848200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE8_E_PG = 0x8009C82006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE8_E_PG = 0x8009C8200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE9_EO_PG = 0x8008502006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE9_EO_PG = 0x800850200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE9_E_PG = 0x8009D02006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE9_E_PG = 0x8009D0200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT1_EO_PG = 0x8009502006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT1_EO_PG = 0x800950200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT1_E_PG = 0x800A382006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT1_E_PG = 0x800A38200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT2_EO_PG = 0x8009582006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT2_EO_PG = 0x800958200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT2_E_PG = 0x800A402006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT2_E_PG = 0x800A40200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT3_EO_PG = 0x8009602006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT3_EO_PG = 0x800960200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT4_E_PG = 0x800A502006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT4_E_PG = 0x800A50200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT5_E_PG = 0x800A582006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT5_E_PG = 0x800A58200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT6_E_PG = 0x800A602006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT6_E_PG = 0x800A60200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STATX8_E_PG = 0x800A682006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STATX8_E_PG = 0x800A68200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_CNTL1_E_PG = 0x800BE82006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_CNTL1_E_PG = 0x800BE8200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_CNTL2_EO_PG = 0x800B782006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_CNTL2_EO_PG = 0x800B78200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_CNTLX1_EO_PG = 0x800B882006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_CNTLX1_EO_PG = 0x800B88200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_SPARE_MODE_PG = 0x800B802006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_SPARE_MODE_PG = 0x800B80200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT10_EO_PG = 0x800BD82006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT10_EO_PG = 0x800BD8200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT11_EO_PG = 0x800BE02006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT11_EO_PG = 0x800BE0200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT12_EO_PG = 0x800BF02006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT12_EO_PG = 0x800BF0200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT13_E_PG = 0x800BF82006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT13_E_PG = 0x800BF8200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT1_EO_PG = 0x800B902006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT1_EO_PG = 0x800B90200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT2_EO_PG = 0x800B982006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT2_EO_PG = 0x800B98200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT3_EO_PG = 0x800BA02006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT3_EO_PG = 0x800BA0200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT4_EO_PG = 0x800BA82006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT4_EO_PG = 0x800BA8200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT5_EO_PG = 0x800BB02006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT5_EO_PG = 0x800BB0200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT6_EO_PG = 0x800BB82006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT6_EO_PG = 0x800BB8200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT7_EO_PG = 0x800BC02006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT7_EO_PG = 0x800BC0200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT8_EO_PG = 0x800BC82006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT8_EO_PG = 0x800BC8200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT9_EO_PG = 0x800BD02006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT9_EO_PG = 0x800BD0200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_FIR1_ERROR_INJECT_PG = 0x800A982006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR1_ERROR_INJECT_PG = 0x800A98200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_FIR1_MASK_PG = 0x800A902006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR1_MASK_PG = 0x800A90200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_FIR1_PG = 0x800A882006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR1_PG = 0x800A88200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_FIR2_ERROR_INJECT_PG = 0x800B102006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR2_ERROR_INJECT_PG = 0x800B10200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_FIR2_MASK_PG = 0x800B082006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR2_MASK_PG = 0x800B08200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_FIR2_PG = 0x800B002006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR2_PG = 0x800B00200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_FIR_TRAINING_MASK_PG = 0x800AA82006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR_TRAINING_MASK_PG = 0x800AA8200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_FIR_TRAINING_PG = 0x800AA02006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR_TRAINING_PG = 0x800AA0200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_CNTL2_EO_PG = 0x800AE02006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_CNTL2_EO_PG = 0x800AE0200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_CNTL3_EO_PG = 0x800AE82006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_CNTL3_EO_PG = 0x800AE8200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_CNTL4_EO_PG = 0x800AF02006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_CNTL4_EO_PG = 0x800AF0200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_CNTLX1_EO_PG = 0x800AB02006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_CNTLX1_EO_PG = 0x800AB0200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_MODE1_EO_PG = 0x800AF82006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_MODE1_EO_PG = 0x800AF8200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_SPARE_MODE_PG = 0x800A802006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_SPARE_MODE_PG = 0x800A80200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT10_E_PG = 0x800B602006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT10_E_PG = 0x800B60200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT11_E_PG = 0x800B682006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT11_E_PG = 0x800B68200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT1_EO_PG = 0x800AB82006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT1_EO_PG = 0x800AB8200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT1_E_PG = 0x800B182006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT1_E_PG = 0x800B18200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT2_EO_PG = 0x800AC02006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT2_EO_PG = 0x800AC0200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT2_E_PG = 0x800B202006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT2_E_PG = 0x800B20200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT3_EO_PG = 0x800AC82006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT3_EO_PG = 0x800AC8200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT3_E_PG = 0x800B282006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT3_E_PG = 0x800B28200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT4_EO_PG = 0x800AD02006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT4_EO_PG = 0x800AD0200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT4_E_PG = 0x800B302006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT4_E_PG = 0x800B30200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT5_EO_PG = 0x800AD82006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT5_EO_PG = 0x800AD8200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT7_E_PG = 0x800B482006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT7_E_PG = 0x800B48200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT8_E_PG = 0x800B502006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT8_E_PG = 0x800B50200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT9_E_PG = 0x800B582006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT9_E_PG = 0x800B58200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_ID1_PG = 0x8008082006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_ID1_PG = 0x800808200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_ID2_PG = 0x8009802006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_ID2_PG = 0x800980200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_RX_SPARE_MODE_PG = 0x8008002006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_SPARE_MODE_PG = 0x800800200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE0_RX_DATA_WORK_SPARE_MODE_PL = 0x8003802106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE0_RX_DATA_WORK_SPARE_MODE_PL = 0x800380210601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE0_RX_WORK_STAT1_EO_PL = 0x8003882106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE0_RX_WORK_STAT1_EO_PL = 0x800388210601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE0_RX_WORK_STAT2_EO_PL = 0x8003902106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE0_RX_WORK_STAT2_EO_PL = 0x800390210601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE0_RX_WORK_STAT3_EO_PL = 0x8003982106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE0_RX_WORK_STAT3_EO_PL = 0x800398210601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE10_RX_DATA_WORK_SPARE_MODE_PL = 0x8003802906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE10_RX_DATA_WORK_SPARE_MODE_PL = 0x800380290601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE10_RX_WORK_STAT1_EO_PL = 0x8003882906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE10_RX_WORK_STAT1_EO_PL = 0x800388290601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE10_RX_WORK_STAT2_EO_PL = 0x8003902906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE10_RX_WORK_STAT2_EO_PL = 0x800390290601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE10_RX_WORK_STAT3_EO_PL = 0x8003982906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE10_RX_WORK_STAT3_EO_PL = 0x800398290601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE11_RX_DATA_WORK_SPARE_MODE_PL = 0x8003803106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE11_RX_DATA_WORK_SPARE_MODE_PL = 0x800380310601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE11_RX_WORK_STAT1_EO_PL = 0x8003883106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE11_RX_WORK_STAT1_EO_PL = 0x800388310601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE11_RX_WORK_STAT2_EO_PL = 0x8003903106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE11_RX_WORK_STAT2_EO_PL = 0x800390310601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE11_RX_WORK_STAT3_EO_PL = 0x8003983106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE11_RX_WORK_STAT3_EO_PL = 0x800398310601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE12_RX_DATA_WORK_SPARE_MODE_PL = 0x8003802E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE12_RX_DATA_WORK_SPARE_MODE_PL = 0x8003802E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE12_RX_WORK_STAT1_EO_PL = 0x8003882E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE12_RX_WORK_STAT1_EO_PL = 0x8003882E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE12_RX_WORK_STAT2_EO_PL = 0x8003902E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE12_RX_WORK_STAT2_EO_PL = 0x8003902E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE12_RX_WORK_STAT3_EO_PL = 0x8003982E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE12_RX_WORK_STAT3_EO_PL = 0x8003982E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE13_RX_DATA_WORK_SPARE_MODE_PL = 0x8003802C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE13_RX_DATA_WORK_SPARE_MODE_PL = 0x8003802C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE13_RX_WORK_STAT1_EO_PL = 0x8003882C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE13_RX_WORK_STAT1_EO_PL = 0x8003882C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE13_RX_WORK_STAT2_EO_PL = 0x8003902C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE13_RX_WORK_STAT2_EO_PL = 0x8003902C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE13_RX_WORK_STAT3_EO_PL = 0x8003982C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE13_RX_WORK_STAT3_EO_PL = 0x8003982C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE14_RX_DATA_WORK_SPARE_MODE_PL = 0x8003802D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE14_RX_DATA_WORK_SPARE_MODE_PL = 0x8003802D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE14_RX_WORK_STAT1_EO_PL = 0x8003882D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE14_RX_WORK_STAT1_EO_PL = 0x8003882D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE14_RX_WORK_STAT2_EO_PL = 0x8003902D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE14_RX_WORK_STAT2_EO_PL = 0x8003902D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE14_RX_WORK_STAT3_EO_PL = 0x8003982D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE14_RX_WORK_STAT3_EO_PL = 0x8003982D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE15_RX_DATA_WORK_SPARE_MODE_PL = 0x8003802B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE15_RX_DATA_WORK_SPARE_MODE_PL = 0x8003802B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE15_RX_WORK_STAT1_EO_PL = 0x8003882B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE15_RX_WORK_STAT1_EO_PL = 0x8003882B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE15_RX_WORK_STAT2_EO_PL = 0x8003902B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE15_RX_WORK_STAT2_EO_PL = 0x8003902B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE15_RX_WORK_STAT3_EO_PL = 0x8003982B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE15_RX_WORK_STAT3_EO_PL = 0x8003982B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE16_RX_DATA_WORK_SPARE_MODE_PL = 0x8003802F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE16_RX_DATA_WORK_SPARE_MODE_PL = 0x8003802F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE16_RX_WORK_STAT1_EO_PL = 0x8003882F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE16_RX_WORK_STAT1_EO_PL = 0x8003882F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE16_RX_WORK_STAT2_EO_PL = 0x8003902F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE16_RX_WORK_STAT2_EO_PL = 0x8003902F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE16_RX_WORK_STAT3_EO_PL = 0x8003982F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE16_RX_WORK_STAT3_EO_PL = 0x8003982F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE17_RX_DATA_WORK_SPARE_MODE_PL = 0x8003803006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE17_RX_DATA_WORK_SPARE_MODE_PL = 0x800380300601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE17_RX_WORK_STAT1_EO_PL = 0x8003883006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE17_RX_WORK_STAT1_EO_PL = 0x800388300601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE17_RX_WORK_STAT2_EO_PL = 0x8003903006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE17_RX_WORK_STAT2_EO_PL = 0x800390300601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE17_RX_WORK_STAT3_EO_PL = 0x8003983006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE17_RX_WORK_STAT3_EO_PL = 0x800398300601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE18_RX_DATA_WORK_SPARE_MODE_PL = 0x8003803206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE18_RX_DATA_WORK_SPARE_MODE_PL = 0x800380320601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE18_RX_WORK_STAT1_EO_PL = 0x8003883206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE18_RX_WORK_STAT1_EO_PL = 0x800388320601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE18_RX_WORK_STAT2_EO_PL = 0x8003903206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE18_RX_WORK_STAT2_EO_PL = 0x800390320601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE18_RX_WORK_STAT3_EO_PL = 0x8003983206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE18_RX_WORK_STAT3_EO_PL = 0x800398320601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE19_RX_DATA_WORK_SPARE_MODE_PL = 0x8003803306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE19_RX_DATA_WORK_SPARE_MODE_PL = 0x800380330601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE19_RX_WORK_STAT1_EO_PL = 0x8003883306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE19_RX_WORK_STAT1_EO_PL = 0x800388330601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE19_RX_WORK_STAT2_EO_PL = 0x8003903306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE19_RX_WORK_STAT2_EO_PL = 0x800390330601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE19_RX_WORK_STAT3_EO_PL = 0x8003983306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE19_RX_WORK_STAT3_EO_PL = 0x800398330601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE1_RX_DATA_WORK_SPARE_MODE_PL = 0x8003802306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE1_RX_DATA_WORK_SPARE_MODE_PL = 0x800380230601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE1_RX_WORK_STAT1_EO_PL = 0x8003882306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE1_RX_WORK_STAT1_EO_PL = 0x800388230601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE1_RX_WORK_STAT2_EO_PL = 0x8003902306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE1_RX_WORK_STAT2_EO_PL = 0x800390230601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE1_RX_WORK_STAT3_EO_PL = 0x8003982306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE1_RX_WORK_STAT3_EO_PL = 0x800398230601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE20_RX_DATA_WORK_SPARE_MODE_PL = 0x8003803406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE20_RX_DATA_WORK_SPARE_MODE_PL = 0x800380340601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE20_RX_WORK_STAT1_EO_PL = 0x8003883406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE20_RX_WORK_STAT1_EO_PL = 0x800388340601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE20_RX_WORK_STAT2_EO_PL = 0x8003903406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE20_RX_WORK_STAT2_EO_PL = 0x800390340601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE20_RX_WORK_STAT3_EO_PL = 0x8003983406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE20_RX_WORK_STAT3_EO_PL = 0x800398340601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE21_RX_DATA_WORK_SPARE_MODE_PL = 0x8003803506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE21_RX_DATA_WORK_SPARE_MODE_PL = 0x800380350601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE21_RX_WORK_STAT1_EO_PL = 0x8003883506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE21_RX_WORK_STAT1_EO_PL = 0x800388350601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE21_RX_WORK_STAT2_EO_PL = 0x8003903506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE21_RX_WORK_STAT2_EO_PL = 0x800390350601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE21_RX_WORK_STAT3_EO_PL = 0x8003983506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE21_RX_WORK_STAT3_EO_PL = 0x800398350601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE22_RX_DATA_WORK_SPARE_MODE_PL = 0x8003803606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE22_RX_DATA_WORK_SPARE_MODE_PL = 0x800380360601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE22_RX_WORK_STAT1_EO_PL = 0x8003883606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE22_RX_WORK_STAT1_EO_PL = 0x800388360601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE22_RX_WORK_STAT2_EO_PL = 0x8003903606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE22_RX_WORK_STAT2_EO_PL = 0x800390360601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE22_RX_WORK_STAT3_EO_PL = 0x8003983606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE22_RX_WORK_STAT3_EO_PL = 0x800398360601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE23_RX_DATA_WORK_SPARE_MODE_PL = 0x8003803706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE23_RX_DATA_WORK_SPARE_MODE_PL = 0x800380370601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE23_RX_WORK_STAT1_EO_PL = 0x8003883706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE23_RX_WORK_STAT1_EO_PL = 0x800388370601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE23_RX_WORK_STAT2_EO_PL = 0x8003903706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE23_RX_WORK_STAT2_EO_PL = 0x800390370601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE23_RX_WORK_STAT3_EO_PL = 0x8003983706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE23_RX_WORK_STAT3_EO_PL = 0x800398370601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE2_RX_DATA_WORK_SPARE_MODE_PL = 0x8003802006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE2_RX_DATA_WORK_SPARE_MODE_PL = 0x800380200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE2_RX_WORK_STAT1_EO_PL = 0x8003882006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE2_RX_WORK_STAT1_EO_PL = 0x800388200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE2_RX_WORK_STAT2_EO_PL = 0x8003902006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE2_RX_WORK_STAT2_EO_PL = 0x800390200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE2_RX_WORK_STAT3_EO_PL = 0x8003982006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE2_RX_WORK_STAT3_EO_PL = 0x800398200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE3_RX_DATA_WORK_SPARE_MODE_PL = 0x8003802206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE3_RX_DATA_WORK_SPARE_MODE_PL = 0x800380220601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE3_RX_WORK_STAT1_EO_PL = 0x8003882206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE3_RX_WORK_STAT1_EO_PL = 0x800388220601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE3_RX_WORK_STAT2_EO_PL = 0x8003902206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE3_RX_WORK_STAT2_EO_PL = 0x800390220601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE3_RX_WORK_STAT3_EO_PL = 0x8003982206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE3_RX_WORK_STAT3_EO_PL = 0x800398220601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE4_RX_DATA_WORK_SPARE_MODE_PL = 0x8003802706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE4_RX_DATA_WORK_SPARE_MODE_PL = 0x800380270601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE4_RX_WORK_STAT1_EO_PL = 0x8003882706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE4_RX_WORK_STAT1_EO_PL = 0x800388270601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE4_RX_WORK_STAT2_EO_PL = 0x8003902706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE4_RX_WORK_STAT2_EO_PL = 0x800390270601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE4_RX_WORK_STAT3_EO_PL = 0x8003982706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE4_RX_WORK_STAT3_EO_PL = 0x800398270601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE5_RX_DATA_WORK_SPARE_MODE_PL = 0x8003802506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE5_RX_DATA_WORK_SPARE_MODE_PL = 0x800380250601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE5_RX_WORK_STAT1_EO_PL = 0x8003882506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE5_RX_WORK_STAT1_EO_PL = 0x800388250601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE5_RX_WORK_STAT2_EO_PL = 0x8003902506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE5_RX_WORK_STAT2_EO_PL = 0x800390250601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE5_RX_WORK_STAT3_EO_PL = 0x8003982506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE5_RX_WORK_STAT3_EO_PL = 0x800398250601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE6_RX_DATA_WORK_SPARE_MODE_PL = 0x8003802606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE6_RX_DATA_WORK_SPARE_MODE_PL = 0x800380260601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE6_RX_WORK_STAT1_EO_PL = 0x8003882606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE6_RX_WORK_STAT1_EO_PL = 0x800388260601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE6_RX_WORK_STAT2_EO_PL = 0x8003902606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE6_RX_WORK_STAT2_EO_PL = 0x800390260601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE6_RX_WORK_STAT3_EO_PL = 0x8003982606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE6_RX_WORK_STAT3_EO_PL = 0x800398260601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE7_RX_DATA_WORK_SPARE_MODE_PL = 0x8003802406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE7_RX_DATA_WORK_SPARE_MODE_PL = 0x800380240601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE7_RX_WORK_STAT1_EO_PL = 0x8003882406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE7_RX_WORK_STAT1_EO_PL = 0x800388240601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE7_RX_WORK_STAT2_EO_PL = 0x8003902406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE7_RX_WORK_STAT2_EO_PL = 0x800390240601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE7_RX_WORK_STAT3_EO_PL = 0x8003982406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE7_RX_WORK_STAT3_EO_PL = 0x800398240601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE8_RX_DATA_WORK_SPARE_MODE_PL = 0x8003802806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE8_RX_DATA_WORK_SPARE_MODE_PL = 0x800380280601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE8_RX_WORK_STAT1_EO_PL = 0x8003882806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE8_RX_WORK_STAT1_EO_PL = 0x800388280601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE8_RX_WORK_STAT2_EO_PL = 0x8003902806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE8_RX_WORK_STAT2_EO_PL = 0x800390280601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE8_RX_WORK_STAT3_EO_PL = 0x8003982806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE8_RX_WORK_STAT3_EO_PL = 0x800398280601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE9_RX_DATA_WORK_SPARE_MODE_PL = 0x8003802A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE9_RX_DATA_WORK_SPARE_MODE_PL = 0x8003802A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE9_RX_WORK_STAT1_EO_PL = 0x8003882A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE9_RX_WORK_STAT1_EO_PL = 0x8003882A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE9_RX_WORK_STAT2_EO_PL = 0x8003902A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE9_RX_WORK_STAT2_EO_PL = 0x8003902A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX1_SLICE9_RX_WORK_STAT3_EO_PL = 0x8003982A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE9_RX_WORK_STAT3_EO_PL = 0x8003982A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX_FIR_ERROR_INJECT_PB = 0x800F980006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX_FIR_ERROR_INJECT_PB = 0x800F98000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX_FIR_MASK_PB = 0x800F900006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX_FIR_MASK_PB = 0x800F90000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX_FIR_PB = 0x800F880006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX_FIR_PB = 0x800F88000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_RX_FIR_RESET_PB = 0x800F800006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX_FIR_RESET_PB = 0x800F80000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_SCOM_MODE_PB = 0x06010C20ull;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_SCOM_MODE_PB = 0x06011020ull;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_SPARE_MODE_PB = 0x800F340006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_SPARE_MODE_PB = 0x800F34000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_BIT_MODE1_E_PL = 0x80043C0006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_BIT_MODE1_E_PL = 0x80043C000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_BIT_MODE2_E_PL = 0x8004440006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_BIT_MODE2_E_PL = 0x800444000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_CNTL1G_PL = 0x8004140006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_CNTL1G_PL = 0x800414000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_CNTL3_EO_PL = 0x8004540006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_CNTL3_EO_PL = 0x800454000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_FIR_ERROR_INJECT_PL = 0x8004340006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_FIR_ERROR_INJECT_PL = 0x800434000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_FIR_MASK_PL = 0x80042C0006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_FIR_MASK_PL = 0x80042C000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_FIR_PL = 0x8004240006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_FIR_PL = 0x800424000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_MODE1_PL = 0x8004040006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_MODE1_PL = 0x800404000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_MODE2_PL = 0x80040C0006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_MODE2_PL = 0x80040C000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_STAT1_PL = 0x80041C0006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_STAT1_PL = 0x80041C000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_BIT_MODE1_E_PL = 0x80043C0106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_BIT_MODE1_E_PL = 0x80043C010601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_BIT_MODE2_E_PL = 0x8004440106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_BIT_MODE2_E_PL = 0x800444010601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_CNTL1G_PL = 0x8004140106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_CNTL1G_PL = 0x800414010601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_CNTL3_EO_PL = 0x8004540106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_CNTL3_EO_PL = 0x800454010601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_FIR_ERROR_INJECT_PL = 0x8004340106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_FIR_ERROR_INJECT_PL = 0x800434010601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_FIR_MASK_PL = 0x80042C0106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_FIR_MASK_PL = 0x80042C010601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_FIR_PL = 0x8004240106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_FIR_PL = 0x800424010601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_MODE1_PL = 0x8004040106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_MODE1_PL = 0x800404010601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_MODE2_PL = 0x80040C0106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_MODE2_PL = 0x80040C010601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_STAT1_PL = 0x80041C0106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_STAT1_PL = 0x80041C010601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_BIT_MODE1_E_PL = 0x80043C0206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_BIT_MODE1_E_PL = 0x80043C020601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_BIT_MODE2_E_PL = 0x8004440206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_BIT_MODE2_E_PL = 0x800444020601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_CNTL1G_PL = 0x8004140206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_CNTL1G_PL = 0x800414020601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_CNTL3_EO_PL = 0x8004540206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_CNTL3_EO_PL = 0x800454020601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_FIR_ERROR_INJECT_PL = 0x8004340206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_FIR_ERROR_INJECT_PL = 0x800434020601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_FIR_MASK_PL = 0x80042C0206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_FIR_MASK_PL = 0x80042C020601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_FIR_PL = 0x8004240206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_FIR_PL = 0x800424020601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_MODE1_PL = 0x8004040206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_MODE1_PL = 0x800404020601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_MODE2_PL = 0x80040C0206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_MODE2_PL = 0x80040C020601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_STAT1_PL = 0x80041C0206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_STAT1_PL = 0x80041C020601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_BIT_MODE1_E_PL = 0x80043C0306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_BIT_MODE1_E_PL = 0x80043C030601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_BIT_MODE2_E_PL = 0x8004440306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_BIT_MODE2_E_PL = 0x800444030601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_CNTL1G_PL = 0x8004140306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_CNTL1G_PL = 0x800414030601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_CNTL3_EO_PL = 0x8004540306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_CNTL3_EO_PL = 0x800454030601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_FIR_ERROR_INJECT_PL = 0x8004340306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_FIR_ERROR_INJECT_PL = 0x800434030601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_FIR_MASK_PL = 0x80042C0306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_FIR_MASK_PL = 0x80042C030601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_FIR_PL = 0x8004240306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_FIR_PL = 0x800424030601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_MODE1_PL = 0x8004040306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_MODE1_PL = 0x800404030601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_MODE2_PL = 0x80040C0306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_MODE2_PL = 0x80040C030601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_STAT1_PL = 0x80041C0306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_STAT1_PL = 0x80041C030601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_BIT_MODE1_E_PL = 0x80043C0406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_BIT_MODE1_E_PL = 0x80043C040601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_BIT_MODE2_E_PL = 0x8004440406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_BIT_MODE2_E_PL = 0x800444040601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_CNTL1G_PL = 0x8004140406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_CNTL1G_PL = 0x800414040601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_CNTL3_EO_PL = 0x8004540406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_CNTL3_EO_PL = 0x800454040601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_FIR_ERROR_INJECT_PL = 0x8004340406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_FIR_ERROR_INJECT_PL = 0x800434040601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_FIR_MASK_PL = 0x80042C0406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_FIR_MASK_PL = 0x80042C040601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_FIR_PL = 0x8004240406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_FIR_PL = 0x800424040601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_MODE1_PL = 0x8004040406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_MODE1_PL = 0x800404040601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_MODE2_PL = 0x80040C0406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_MODE2_PL = 0x80040C040601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_STAT1_PL = 0x80041C0406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_STAT1_PL = 0x80041C040601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_BIT_MODE1_E_PL = 0x80043C0506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_BIT_MODE1_E_PL = 0x80043C050601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_BIT_MODE2_E_PL = 0x8004440506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_BIT_MODE2_E_PL = 0x800444050601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_CNTL1G_PL = 0x8004140506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_CNTL1G_PL = 0x800414050601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_CNTL3_EO_PL = 0x8004540506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_CNTL3_EO_PL = 0x800454050601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_FIR_ERROR_INJECT_PL = 0x8004340506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_FIR_ERROR_INJECT_PL = 0x800434050601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_FIR_MASK_PL = 0x80042C0506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_FIR_MASK_PL = 0x80042C050601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_FIR_PL = 0x8004240506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_FIR_PL = 0x800424050601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_MODE1_PL = 0x8004040506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_MODE1_PL = 0x800404050601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_MODE2_PL = 0x80040C0506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_MODE2_PL = 0x80040C050601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_STAT1_PL = 0x80041C0506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_STAT1_PL = 0x80041C050601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_BIT_MODE1_E_PL = 0x80043C0606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_BIT_MODE1_E_PL = 0x80043C060601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_BIT_MODE2_E_PL = 0x8004440606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_BIT_MODE2_E_PL = 0x800444060601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_CNTL1G_PL = 0x8004140606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_CNTL1G_PL = 0x800414060601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_CNTL3_EO_PL = 0x8004540606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_CNTL3_EO_PL = 0x800454060601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_FIR_ERROR_INJECT_PL = 0x8004340606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_FIR_ERROR_INJECT_PL = 0x800434060601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_FIR_MASK_PL = 0x80042C0606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_FIR_MASK_PL = 0x80042C060601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_FIR_PL = 0x8004240606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_FIR_PL = 0x800424060601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_MODE1_PL = 0x8004040606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_MODE1_PL = 0x800404060601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_MODE2_PL = 0x80040C0606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_MODE2_PL = 0x80040C060601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_STAT1_PL = 0x80041C0606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_STAT1_PL = 0x80041C060601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_BIT_MODE1_E_PL = 0x80043C0706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_BIT_MODE1_E_PL = 0x80043C070601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_BIT_MODE2_E_PL = 0x8004440706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_BIT_MODE2_E_PL = 0x800444070601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_CNTL1G_PL = 0x8004140706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_CNTL1G_PL = 0x800414070601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_CNTL3_EO_PL = 0x8004540706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_CNTL3_EO_PL = 0x800454070601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_FIR_ERROR_INJECT_PL = 0x8004340706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_FIR_ERROR_INJECT_PL = 0x800434070601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_FIR_MASK_PL = 0x80042C0706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_FIR_MASK_PL = 0x80042C070601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_FIR_PL = 0x8004240706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_FIR_PL = 0x800424070601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_MODE1_PL = 0x8004040706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_MODE1_PL = 0x800404070601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_MODE2_PL = 0x80040C0706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_MODE2_PL = 0x80040C070601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_STAT1_PL = 0x80041C0706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_STAT1_PL = 0x80041C070601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_BIT_MODE1_E_PL = 0x80043C0806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_BIT_MODE1_E_PL = 0x80043C080601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_BIT_MODE2_E_PL = 0x8004440806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_BIT_MODE2_E_PL = 0x800444080601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_CNTL1G_PL = 0x8004140806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_CNTL1G_PL = 0x800414080601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_CNTL3_EO_PL = 0x8004540806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_CNTL3_EO_PL = 0x800454080601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_FIR_ERROR_INJECT_PL = 0x8004340806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_FIR_ERROR_INJECT_PL = 0x800434080601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_FIR_MASK_PL = 0x80042C0806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_FIR_MASK_PL = 0x80042C080601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_FIR_PL = 0x8004240806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_FIR_PL = 0x800424080601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_MODE1_PL = 0x8004040806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_MODE1_PL = 0x800404080601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_MODE2_PL = 0x80040C0806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_MODE2_PL = 0x80040C080601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_STAT1_PL = 0x80041C0806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_STAT1_PL = 0x80041C080601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_BIT_MODE1_E_PL = 0x80043C0906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_BIT_MODE1_E_PL = 0x80043C090601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_BIT_MODE2_E_PL = 0x8004440906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_BIT_MODE2_E_PL = 0x800444090601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_CNTL1G_PL = 0x8004140906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_CNTL1G_PL = 0x800414090601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_CNTL3_EO_PL = 0x8004540906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_CNTL3_EO_PL = 0x800454090601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_FIR_ERROR_INJECT_PL = 0x8004340906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_FIR_ERROR_INJECT_PL = 0x800434090601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_FIR_MASK_PL = 0x80042C0906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_FIR_MASK_PL = 0x80042C090601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_FIR_PL = 0x8004240906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_FIR_PL = 0x800424090601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_MODE1_PL = 0x8004040906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_MODE1_PL = 0x800404090601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_MODE2_PL = 0x80040C0906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_MODE2_PL = 0x80040C090601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_STAT1_PL = 0x80041C0906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_STAT1_PL = 0x80041C090601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_BIT_MODE1_E_PL = 0x80043C0A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_BIT_MODE1_E_PL = 0x80043C0A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_BIT_MODE2_E_PL = 0x8004440A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_BIT_MODE2_E_PL = 0x8004440A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_CNTL1G_PL = 0x8004140A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_CNTL1G_PL = 0x8004140A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_CNTL3_EO_PL = 0x8004540A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_CNTL3_EO_PL = 0x8004540A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_FIR_ERROR_INJECT_PL = 0x8004340A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_FIR_ERROR_INJECT_PL = 0x8004340A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_FIR_MASK_PL = 0x80042C0A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_FIR_MASK_PL = 0x80042C0A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_FIR_PL = 0x8004240A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_FIR_PL = 0x8004240A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_MODE1_PL = 0x8004040A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_MODE1_PL = 0x8004040A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_MODE2_PL = 0x80040C0A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_MODE2_PL = 0x80040C0A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_STAT1_PL = 0x80041C0A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_STAT1_PL = 0x80041C0A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_BIT_MODE1_E_PL = 0x80043C0B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_BIT_MODE1_E_PL = 0x80043C0B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_BIT_MODE2_E_PL = 0x8004440B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_BIT_MODE2_E_PL = 0x8004440B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_CNTL1G_PL = 0x8004140B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_CNTL1G_PL = 0x8004140B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_CNTL3_EO_PL = 0x8004540B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_CNTL3_EO_PL = 0x8004540B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_FIR_ERROR_INJECT_PL = 0x8004340B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_FIR_ERROR_INJECT_PL = 0x8004340B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_FIR_MASK_PL = 0x80042C0B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_FIR_MASK_PL = 0x80042C0B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_FIR_PL = 0x8004240B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_FIR_PL = 0x8004240B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_MODE1_PL = 0x8004040B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_MODE1_PL = 0x8004040B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_MODE2_PL = 0x80040C0B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_MODE2_PL = 0x80040C0B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_STAT1_PL = 0x80041C0B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_STAT1_PL = 0x80041C0B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_BIT_MODE1_E_PL = 0x80043C0C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_BIT_MODE1_E_PL = 0x80043C0C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_BIT_MODE2_E_PL = 0x8004440C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_BIT_MODE2_E_PL = 0x8004440C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_CNTL1G_PL = 0x8004140C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_CNTL1G_PL = 0x8004140C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_CNTL3_EO_PL = 0x8004540C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_CNTL3_EO_PL = 0x8004540C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_FIR_ERROR_INJECT_PL = 0x8004340C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_FIR_ERROR_INJECT_PL = 0x8004340C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_FIR_MASK_PL = 0x80042C0C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_FIR_MASK_PL = 0x80042C0C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_FIR_PL = 0x8004240C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_FIR_PL = 0x8004240C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_MODE1_PL = 0x8004040C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_MODE1_PL = 0x8004040C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_MODE2_PL = 0x80040C0C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_MODE2_PL = 0x80040C0C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_STAT1_PL = 0x80041C0C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_STAT1_PL = 0x80041C0C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_BIT_MODE1_E_PL = 0x80043C0D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_BIT_MODE1_E_PL = 0x80043C0D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_BIT_MODE2_E_PL = 0x8004440D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_BIT_MODE2_E_PL = 0x8004440D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_CNTL1G_PL = 0x8004140D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_CNTL1G_PL = 0x8004140D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_CNTL3_EO_PL = 0x8004540D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_CNTL3_EO_PL = 0x8004540D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_FIR_ERROR_INJECT_PL = 0x8004340D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_FIR_ERROR_INJECT_PL = 0x8004340D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_FIR_MASK_PL = 0x80042C0D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_FIR_MASK_PL = 0x80042C0D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_FIR_PL = 0x8004240D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_FIR_PL = 0x8004240D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_MODE1_PL = 0x8004040D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_MODE1_PL = 0x8004040D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_MODE2_PL = 0x80040C0D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_MODE2_PL = 0x80040C0D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_STAT1_PL = 0x80041C0D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_STAT1_PL = 0x80041C0D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_BIT_MODE1_E_PL = 0x80043C0E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_BIT_MODE1_E_PL = 0x80043C0E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_BIT_MODE2_E_PL = 0x8004440E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_BIT_MODE2_E_PL = 0x8004440E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_CNTL1G_PL = 0x8004140E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_CNTL1G_PL = 0x8004140E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_CNTL3_EO_PL = 0x8004540E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_CNTL3_EO_PL = 0x8004540E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_FIR_ERROR_INJECT_PL = 0x8004340E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_FIR_ERROR_INJECT_PL = 0x8004340E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_FIR_MASK_PL = 0x80042C0E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_FIR_MASK_PL = 0x80042C0E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_FIR_PL = 0x8004240E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_FIR_PL = 0x8004240E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_MODE1_PL = 0x8004040E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_MODE1_PL = 0x8004040E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_MODE2_PL = 0x80040C0E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_MODE2_PL = 0x80040C0E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_STAT1_PL = 0x80041C0E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_STAT1_PL = 0x80041C0E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_BIT_MODE1_E_PL = 0x80043C0F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_BIT_MODE1_E_PL = 0x80043C0F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_BIT_MODE2_E_PL = 0x8004440F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_BIT_MODE2_E_PL = 0x8004440F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_CNTL1G_PL = 0x8004140F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_CNTL1G_PL = 0x8004140F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_CNTL3_EO_PL = 0x8004540F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_CNTL3_EO_PL = 0x8004540F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_FIR_ERROR_INJECT_PL = 0x8004340F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_FIR_ERROR_INJECT_PL = 0x8004340F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_FIR_MASK_PL = 0x80042C0F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_FIR_MASK_PL = 0x80042C0F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_FIR_PL = 0x8004240F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_FIR_PL = 0x8004240F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_MODE1_PL = 0x8004040F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_MODE1_PL = 0x8004040F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_MODE2_PL = 0x80040C0F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_MODE2_PL = 0x80040C0F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_STAT1_PL = 0x80041C0F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_STAT1_PL = 0x80041C0F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_BIT_MODE1_E_PL = 0x80043C1006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_BIT_MODE1_E_PL = 0x80043C100601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_BIT_MODE2_E_PL = 0x8004441006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_BIT_MODE2_E_PL = 0x800444100601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_CNTL1G_PL = 0x8004141006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_CNTL1G_PL = 0x800414100601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_CNTL3_EO_PL = 0x8004541006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_CNTL3_EO_PL = 0x800454100601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_FIR_ERROR_INJECT_PL = 0x8004341006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_FIR_ERROR_INJECT_PL = 0x800434100601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_FIR_MASK_PL = 0x80042C1006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_FIR_MASK_PL = 0x80042C100601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_FIR_PL = 0x8004241006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_FIR_PL = 0x800424100601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_MODE1_PL = 0x8004041006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_MODE1_PL = 0x800404100601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_MODE2_PL = 0x80040C1006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_MODE2_PL = 0x80040C100601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_STAT1_PL = 0x80041C1006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_STAT1_PL = 0x80041C100601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_CNTL1_EO_PG = 0x800D340006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_CNTL1_EO_PG = 0x800D34000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_CNTL2_EO_PG = 0x800D3C0006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_CNTL2_EO_PG = 0x800D3C000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_CNTL3_EO_PG = 0x800D440006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_CNTL3_EO_PG = 0x800D44000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_CNTL4_EO_PG = 0x800D4C0006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_CNTL4_EO_PG = 0x800D4C000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_CNTL5_EO_PG = 0x800D540006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_CNTL5_EO_PG = 0x800D54000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_CNTL6_EO_PG = 0x800D5C0006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_CNTL6_EO_PG = 0x800D5C000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_CNTL7_EO_PG = 0x800D640006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_CNTL7_EO_PG = 0x800D64000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_CNTLG1_E_PG = 0x800D840006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_CNTLG1_E_PG = 0x800D84000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_MODE1_EO_PG = 0x800D2C0006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_MODE1_EO_PG = 0x800D2C000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_SPARE_MODE_PG = 0x800D240006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_SPARE_MODE_PG = 0x800D24000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_STAT1_EO_PG = 0x800D6C0006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_STAT1_EO_PG = 0x800D6C000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_STAT1_E_PG = 0x800D8C0006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_STAT1_E_PG = 0x800D8C000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTL10_EO_PG = 0x800CDC0006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTL10_EO_PG = 0x800CDC000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTL2_EO_PG = 0x800C2C0006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTL2_EO_PG = 0x800C2C000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTL2_E_PG = 0x800C9C0006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTL2_E_PG = 0x800C9C000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTL3_EO_PG = 0x800C340006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTL3_EO_PG = 0x800C34000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTL8_EO_PG = 0x800CCC0006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTL8_EO_PG = 0x800CCC000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTL9_EO_PG = 0x800CD40006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTL9_EO_PG = 0x800CD4000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTLG1_EO_PG = 0x800C240006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTLG1_EO_PG = 0x800C24000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTLG3_E_PG = 0x800CA40006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTLG3_E_PG = 0x800CA4000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTLG4_E_PG = 0x800CAC0006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTLG4_E_PG = 0x800CAC000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTLG5_E_PG = 0x800CB40006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTLG5_E_PG = 0x800CB4000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTLG6_E_PG = 0x800CBC0006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTLG6_E_PG = 0x800CBC000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTLG7_E_PG = 0x800CC40006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTLG7_E_PG = 0x800CC4000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TX_CTL_MODE1_EO_PG = 0x800C140006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_MODE1_EO_PG = 0x800C14000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TX_CTL_MODE1_E_PG = 0x800C8C0006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_MODE1_E_PG = 0x800C8C000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TX_CTL_MODE2_EO_PG = 0x800C1C0006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_MODE2_EO_PG = 0x800C1C000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TX_CTL_MODE2_E_PG = 0x800CEC0006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_MODE2_E_PG = 0x800CEC000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TX_CTL_MODE3_E_PG = 0x800CF40006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_MODE3_E_PG = 0x800CF4000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TX_CTL_STATG1_E_PG = 0x800CE40006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_STATG1_E_PG = 0x800CE4000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TX_FIR_ERROR_INJECT_PG = 0x800D1C0006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_FIR_ERROR_INJECT_PG = 0x800D1C000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TX_FIR_MASK_PG = 0x800D0C0006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_FIR_MASK_PG = 0x800D0C000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TX_FIR_PG = 0x800D040006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_FIR_PG = 0x800D04000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TX_FIR_RESET_PG = 0x800D140006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_FIR_RESET_PG = 0x800D14000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TX_ID1_PG = 0x800C0C0006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_ID1_PG = 0x800C0C000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TX_ID2_PG = 0x800C840006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_ID2_PG = 0x800C84000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX0_TX_SPARE_MODE_PG = 0x800C040006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_SPARE_MODE_PG = 0x800C04000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_BIT_MODE1_E_PL = 0x80043C2006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_BIT_MODE1_E_PL = 0x80043C200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_BIT_MODE2_E_PL = 0x8004442006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_BIT_MODE2_E_PL = 0x800444200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_CNTL1G_PL = 0x8004142006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_CNTL1G_PL = 0x800414200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_CNTL3_EO_PL = 0x8004542006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_CNTL3_EO_PL = 0x800454200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_FIR_ERROR_INJECT_PL = 0x8004342006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_FIR_ERROR_INJECT_PL = 0x800434200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_FIR_MASK_PL = 0x80042C2006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_FIR_MASK_PL = 0x80042C200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_FIR_PL = 0x8004242006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_FIR_PL = 0x800424200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_MODE1_PL = 0x8004042006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_MODE1_PL = 0x800404200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_MODE2_PL = 0x80040C2006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_MODE2_PL = 0x80040C200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_STAT1_PL = 0x80041C2006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_STAT1_PL = 0x80041C200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_BIT_MODE1_E_PL = 0x80043C2106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_BIT_MODE1_E_PL = 0x80043C210601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_BIT_MODE2_E_PL = 0x8004442106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_BIT_MODE2_E_PL = 0x800444210601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_CNTL1G_PL = 0x8004142106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_CNTL1G_PL = 0x800414210601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_CNTL3_EO_PL = 0x8004542106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_CNTL3_EO_PL = 0x800454210601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_FIR_ERROR_INJECT_PL = 0x8004342106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_FIR_ERROR_INJECT_PL = 0x800434210601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_FIR_MASK_PL = 0x80042C2106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_FIR_MASK_PL = 0x80042C210601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_FIR_PL = 0x8004242106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_FIR_PL = 0x800424210601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_MODE1_PL = 0x8004042106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_MODE1_PL = 0x800404210601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_MODE2_PL = 0x80040C2106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_MODE2_PL = 0x80040C210601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_STAT1_PL = 0x80041C2106010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_STAT1_PL = 0x80041C210601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_BIT_MODE1_E_PL = 0x80043C2206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_BIT_MODE1_E_PL = 0x80043C220601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_BIT_MODE2_E_PL = 0x8004442206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_BIT_MODE2_E_PL = 0x800444220601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_CNTL1G_PL = 0x8004142206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_CNTL1G_PL = 0x800414220601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_CNTL3_EO_PL = 0x8004542206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_CNTL3_EO_PL = 0x800454220601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_FIR_ERROR_INJECT_PL = 0x8004342206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_FIR_ERROR_INJECT_PL = 0x800434220601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_FIR_MASK_PL = 0x80042C2206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_FIR_MASK_PL = 0x80042C220601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_FIR_PL = 0x8004242206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_FIR_PL = 0x800424220601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_MODE1_PL = 0x8004042206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_MODE1_PL = 0x800404220601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_MODE2_PL = 0x80040C2206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_MODE2_PL = 0x80040C220601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_STAT1_PL = 0x80041C2206010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_STAT1_PL = 0x80041C220601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_BIT_MODE1_E_PL = 0x80043C2306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_BIT_MODE1_E_PL = 0x80043C230601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_BIT_MODE2_E_PL = 0x8004442306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_BIT_MODE2_E_PL = 0x800444230601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_CNTL1G_PL = 0x8004142306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_CNTL1G_PL = 0x800414230601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_CNTL3_EO_PL = 0x8004542306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_CNTL3_EO_PL = 0x800454230601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_FIR_ERROR_INJECT_PL = 0x8004342306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_FIR_ERROR_INJECT_PL = 0x800434230601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_FIR_MASK_PL = 0x80042C2306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_FIR_MASK_PL = 0x80042C230601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_FIR_PL = 0x8004242306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_FIR_PL = 0x800424230601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_MODE1_PL = 0x8004042306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_MODE1_PL = 0x800404230601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_MODE2_PL = 0x80040C2306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_MODE2_PL = 0x80040C230601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_STAT1_PL = 0x80041C2306010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_STAT1_PL = 0x80041C230601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_BIT_MODE1_E_PL = 0x80043C2406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_BIT_MODE1_E_PL = 0x80043C240601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_BIT_MODE2_E_PL = 0x8004442406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_BIT_MODE2_E_PL = 0x800444240601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_CNTL1G_PL = 0x8004142406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_CNTL1G_PL = 0x800414240601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_CNTL3_EO_PL = 0x8004542406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_CNTL3_EO_PL = 0x800454240601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_FIR_ERROR_INJECT_PL = 0x8004342406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_FIR_ERROR_INJECT_PL = 0x800434240601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_FIR_MASK_PL = 0x80042C2406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_FIR_MASK_PL = 0x80042C240601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_FIR_PL = 0x8004242406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_FIR_PL = 0x800424240601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_MODE1_PL = 0x8004042406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_MODE1_PL = 0x800404240601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_MODE2_PL = 0x80040C2406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_MODE2_PL = 0x80040C240601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_STAT1_PL = 0x80041C2406010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_STAT1_PL = 0x80041C240601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_BIT_MODE1_E_PL = 0x80043C2506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_BIT_MODE1_E_PL = 0x80043C250601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_BIT_MODE2_E_PL = 0x8004442506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_BIT_MODE2_E_PL = 0x800444250601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_CNTL1G_PL = 0x8004142506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_CNTL1G_PL = 0x800414250601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_CNTL3_EO_PL = 0x8004542506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_CNTL3_EO_PL = 0x800454250601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_FIR_ERROR_INJECT_PL = 0x8004342506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_FIR_ERROR_INJECT_PL = 0x800434250601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_FIR_MASK_PL = 0x80042C2506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_FIR_MASK_PL = 0x80042C250601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_FIR_PL = 0x8004242506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_FIR_PL = 0x800424250601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_MODE1_PL = 0x8004042506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_MODE1_PL = 0x800404250601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_MODE2_PL = 0x80040C2506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_MODE2_PL = 0x80040C250601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_STAT1_PL = 0x80041C2506010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_STAT1_PL = 0x80041C250601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_BIT_MODE1_E_PL = 0x80043C2606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_BIT_MODE1_E_PL = 0x80043C260601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_BIT_MODE2_E_PL = 0x8004442606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_BIT_MODE2_E_PL = 0x800444260601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_CNTL1G_PL = 0x8004142606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_CNTL1G_PL = 0x800414260601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_CNTL3_EO_PL = 0x8004542606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_CNTL3_EO_PL = 0x800454260601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_FIR_ERROR_INJECT_PL = 0x8004342606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_FIR_ERROR_INJECT_PL = 0x800434260601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_FIR_MASK_PL = 0x80042C2606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_FIR_MASK_PL = 0x80042C260601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_FIR_PL = 0x8004242606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_FIR_PL = 0x800424260601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_MODE1_PL = 0x8004042606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_MODE1_PL = 0x800404260601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_MODE2_PL = 0x80040C2606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_MODE2_PL = 0x80040C260601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_STAT1_PL = 0x80041C2606010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_STAT1_PL = 0x80041C260601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_BIT_MODE1_E_PL = 0x80043C2706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_BIT_MODE1_E_PL = 0x80043C270601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_BIT_MODE2_E_PL = 0x8004442706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_BIT_MODE2_E_PL = 0x800444270601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_CNTL1G_PL = 0x8004142706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_CNTL1G_PL = 0x800414270601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_CNTL3_EO_PL = 0x8004542706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_CNTL3_EO_PL = 0x800454270601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_FIR_ERROR_INJECT_PL = 0x8004342706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_FIR_ERROR_INJECT_PL = 0x800434270601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_FIR_MASK_PL = 0x80042C2706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_FIR_MASK_PL = 0x80042C270601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_FIR_PL = 0x8004242706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_FIR_PL = 0x800424270601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_MODE1_PL = 0x8004042706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_MODE1_PL = 0x800404270601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_MODE2_PL = 0x80040C2706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_MODE2_PL = 0x80040C270601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_STAT1_PL = 0x80041C2706010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_STAT1_PL = 0x80041C270601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_BIT_MODE1_E_PL = 0x80043C2806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_BIT_MODE1_E_PL = 0x80043C280601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_BIT_MODE2_E_PL = 0x8004442806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_BIT_MODE2_E_PL = 0x800444280601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_CNTL1G_PL = 0x8004142806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_CNTL1G_PL = 0x800414280601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_CNTL3_EO_PL = 0x8004542806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_CNTL3_EO_PL = 0x800454280601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_FIR_ERROR_INJECT_PL = 0x8004342806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_FIR_ERROR_INJECT_PL = 0x800434280601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_FIR_MASK_PL = 0x80042C2806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_FIR_MASK_PL = 0x80042C280601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_FIR_PL = 0x8004242806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_FIR_PL = 0x800424280601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_MODE1_PL = 0x8004042806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_MODE1_PL = 0x800404280601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_MODE2_PL = 0x80040C2806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_MODE2_PL = 0x80040C280601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_STAT1_PL = 0x80041C2806010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_STAT1_PL = 0x80041C280601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_BIT_MODE1_E_PL = 0x80043C2906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_BIT_MODE1_E_PL = 0x80043C290601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_BIT_MODE2_E_PL = 0x8004442906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_BIT_MODE2_E_PL = 0x800444290601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_CNTL1G_PL = 0x8004142906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_CNTL1G_PL = 0x800414290601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_CNTL3_EO_PL = 0x8004542906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_CNTL3_EO_PL = 0x800454290601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_FIR_ERROR_INJECT_PL = 0x8004342906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_FIR_ERROR_INJECT_PL = 0x800434290601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_FIR_MASK_PL = 0x80042C2906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_FIR_MASK_PL = 0x80042C290601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_FIR_PL = 0x8004242906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_FIR_PL = 0x800424290601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_MODE1_PL = 0x8004042906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_MODE1_PL = 0x800404290601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_MODE2_PL = 0x80040C2906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_MODE2_PL = 0x80040C290601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_STAT1_PL = 0x80041C2906010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_STAT1_PL = 0x80041C290601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_BIT_MODE1_E_PL = 0x80043C2A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_BIT_MODE1_E_PL = 0x80043C2A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_BIT_MODE2_E_PL = 0x8004442A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_BIT_MODE2_E_PL = 0x8004442A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_CNTL1G_PL = 0x8004142A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_CNTL1G_PL = 0x8004142A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_CNTL3_EO_PL = 0x8004542A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_CNTL3_EO_PL = 0x8004542A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_FIR_ERROR_INJECT_PL = 0x8004342A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_FIR_ERROR_INJECT_PL = 0x8004342A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_FIR_MASK_PL = 0x80042C2A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_FIR_MASK_PL = 0x80042C2A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_FIR_PL = 0x8004242A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_FIR_PL = 0x8004242A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_MODE1_PL = 0x8004042A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_MODE1_PL = 0x8004042A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_MODE2_PL = 0x80040C2A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_MODE2_PL = 0x80040C2A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_STAT1_PL = 0x80041C2A06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_STAT1_PL = 0x80041C2A0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_BIT_MODE1_E_PL = 0x80043C2B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_BIT_MODE1_E_PL = 0x80043C2B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_BIT_MODE2_E_PL = 0x8004442B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_BIT_MODE2_E_PL = 0x8004442B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_CNTL1G_PL = 0x8004142B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_CNTL1G_PL = 0x8004142B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_CNTL3_EO_PL = 0x8004542B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_CNTL3_EO_PL = 0x8004542B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_FIR_ERROR_INJECT_PL = 0x8004342B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_FIR_ERROR_INJECT_PL = 0x8004342B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_FIR_MASK_PL = 0x80042C2B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_FIR_MASK_PL = 0x80042C2B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_FIR_PL = 0x8004242B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_FIR_PL = 0x8004242B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_MODE1_PL = 0x8004042B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_MODE1_PL = 0x8004042B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_MODE2_PL = 0x80040C2B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_MODE2_PL = 0x80040C2B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_STAT1_PL = 0x80041C2B06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_STAT1_PL = 0x80041C2B0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_BIT_MODE1_E_PL = 0x80043C2C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_BIT_MODE1_E_PL = 0x80043C2C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_BIT_MODE2_E_PL = 0x8004442C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_BIT_MODE2_E_PL = 0x8004442C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_CNTL1G_PL = 0x8004142C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_CNTL1G_PL = 0x8004142C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_CNTL3_EO_PL = 0x8004542C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_CNTL3_EO_PL = 0x8004542C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_FIR_ERROR_INJECT_PL = 0x8004342C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_FIR_ERROR_INJECT_PL = 0x8004342C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_FIR_MASK_PL = 0x80042C2C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_FIR_MASK_PL = 0x80042C2C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_FIR_PL = 0x8004242C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_FIR_PL = 0x8004242C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_MODE1_PL = 0x8004042C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_MODE1_PL = 0x8004042C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_MODE2_PL = 0x80040C2C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_MODE2_PL = 0x80040C2C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_STAT1_PL = 0x80041C2C06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_STAT1_PL = 0x80041C2C0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_BIT_MODE1_E_PL = 0x80043C2D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_BIT_MODE1_E_PL = 0x80043C2D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_BIT_MODE2_E_PL = 0x8004442D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_BIT_MODE2_E_PL = 0x8004442D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_CNTL1G_PL = 0x8004142D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_CNTL1G_PL = 0x8004142D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_CNTL3_EO_PL = 0x8004542D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_CNTL3_EO_PL = 0x8004542D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_FIR_ERROR_INJECT_PL = 0x8004342D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_FIR_ERROR_INJECT_PL = 0x8004342D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_FIR_MASK_PL = 0x80042C2D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_FIR_MASK_PL = 0x80042C2D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_FIR_PL = 0x8004242D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_FIR_PL = 0x8004242D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_MODE1_PL = 0x8004042D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_MODE1_PL = 0x8004042D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_MODE2_PL = 0x80040C2D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_MODE2_PL = 0x80040C2D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_STAT1_PL = 0x80041C2D06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_STAT1_PL = 0x80041C2D0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_BIT_MODE1_E_PL = 0x80043C2E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_BIT_MODE1_E_PL = 0x80043C2E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_BIT_MODE2_E_PL = 0x8004442E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_BIT_MODE2_E_PL = 0x8004442E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_CNTL1G_PL = 0x8004142E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_CNTL1G_PL = 0x8004142E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_CNTL3_EO_PL = 0x8004542E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_CNTL3_EO_PL = 0x8004542E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_FIR_ERROR_INJECT_PL = 0x8004342E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_FIR_ERROR_INJECT_PL = 0x8004342E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_FIR_MASK_PL = 0x80042C2E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_FIR_MASK_PL = 0x80042C2E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_FIR_PL = 0x8004242E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_FIR_PL = 0x8004242E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_MODE1_PL = 0x8004042E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_MODE1_PL = 0x8004042E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_MODE2_PL = 0x80040C2E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_MODE2_PL = 0x80040C2E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_STAT1_PL = 0x80041C2E06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_STAT1_PL = 0x80041C2E0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_BIT_MODE1_E_PL = 0x80043C2F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_BIT_MODE1_E_PL = 0x80043C2F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_BIT_MODE2_E_PL = 0x8004442F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_BIT_MODE2_E_PL = 0x8004442F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_CNTL1G_PL = 0x8004142F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_CNTL1G_PL = 0x8004142F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_CNTL3_EO_PL = 0x8004542F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_CNTL3_EO_PL = 0x8004542F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_FIR_ERROR_INJECT_PL = 0x8004342F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_FIR_ERROR_INJECT_PL = 0x8004342F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_FIR_MASK_PL = 0x80042C2F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_FIR_MASK_PL = 0x80042C2F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_FIR_PL = 0x8004242F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_FIR_PL = 0x8004242F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_MODE1_PL = 0x8004042F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_MODE1_PL = 0x8004042F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_MODE2_PL = 0x80040C2F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_MODE2_PL = 0x80040C2F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_STAT1_PL = 0x80041C2F06010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_STAT1_PL = 0x80041C2F0601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_BIT_MODE1_E_PL = 0x80043C3006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_BIT_MODE1_E_PL = 0x80043C300601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_BIT_MODE2_E_PL = 0x8004443006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_BIT_MODE2_E_PL = 0x800444300601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_CNTL1G_PL = 0x8004143006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_CNTL1G_PL = 0x800414300601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_CNTL3_EO_PL = 0x8004543006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_CNTL3_EO_PL = 0x800454300601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_FIR_ERROR_INJECT_PL = 0x8004343006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_FIR_ERROR_INJECT_PL = 0x800434300601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_FIR_MASK_PL = 0x80042C3006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_FIR_MASK_PL = 0x80042C300601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_FIR_PL = 0x8004243006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_FIR_PL = 0x800424300601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_MODE1_PL = 0x8004043006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_MODE1_PL = 0x800404300601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_MODE2_PL = 0x80040C3006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_MODE2_PL = 0x80040C300601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_STAT1_PL = 0x80041C3006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_STAT1_PL = 0x80041C300601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_CNTL1_EO_PG = 0x800D342006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_CNTL1_EO_PG = 0x800D34200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_CNTL2_EO_PG = 0x800D3C2006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_CNTL2_EO_PG = 0x800D3C200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_CNTL3_EO_PG = 0x800D442006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_CNTL3_EO_PG = 0x800D44200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_CNTL4_EO_PG = 0x800D4C2006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_CNTL4_EO_PG = 0x800D4C200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_CNTL5_EO_PG = 0x800D542006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_CNTL5_EO_PG = 0x800D54200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_CNTL6_EO_PG = 0x800D5C2006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_CNTL6_EO_PG = 0x800D5C200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_CNTL7_EO_PG = 0x800D642006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_CNTL7_EO_PG = 0x800D64200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_CNTLG1_E_PG = 0x800D842006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_CNTLG1_E_PG = 0x800D84200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_MODE1_EO_PG = 0x800D2C2006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_MODE1_EO_PG = 0x800D2C200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_SPARE_MODE_PG = 0x800D242006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_SPARE_MODE_PG = 0x800D24200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_STAT1_EO_PG = 0x800D6C2006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_STAT1_EO_PG = 0x800D6C200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_STAT1_E_PG = 0x800D8C2006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_STAT1_E_PG = 0x800D8C200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTL10_EO_PG = 0x800CDC2006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTL10_EO_PG = 0x800CDC200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTL2_EO_PG = 0x800C2C2006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTL2_EO_PG = 0x800C2C200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTL2_E_PG = 0x800C9C2006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTL2_E_PG = 0x800C9C200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTL3_EO_PG = 0x800C342006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTL3_EO_PG = 0x800C34200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTL8_EO_PG = 0x800CCC2006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTL8_EO_PG = 0x800CCC200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTL9_EO_PG = 0x800CD42006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTL9_EO_PG = 0x800CD4200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTLG1_EO_PG = 0x800C242006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTLG1_EO_PG = 0x800C24200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTLG3_E_PG = 0x800CA42006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTLG3_E_PG = 0x800CA4200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTLG4_E_PG = 0x800CAC2006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTLG4_E_PG = 0x800CAC200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTLG5_E_PG = 0x800CB42006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTLG5_E_PG = 0x800CB4200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTLG6_E_PG = 0x800CBC2006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTLG6_E_PG = 0x800CBC200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTLG7_E_PG = 0x800CC42006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTLG7_E_PG = 0x800CC4200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TX_CTL_MODE1_EO_PG = 0x800C142006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_MODE1_EO_PG = 0x800C14200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TX_CTL_MODE1_E_PG = 0x800C8C2006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_MODE1_E_PG = 0x800C8C200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TX_CTL_MODE2_EO_PG = 0x800C1C2006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_MODE2_EO_PG = 0x800C1C200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TX_CTL_MODE2_E_PG = 0x800CEC2006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_MODE2_E_PG = 0x800CEC200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TX_CTL_MODE3_E_PG = 0x800CF42006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_MODE3_E_PG = 0x800CF4200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TX_CTL_STATG1_E_PG = 0x800CE42006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_STATG1_E_PG = 0x800CE4200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TX_FIR_ERROR_INJECT_PG = 0x800D1C2006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_FIR_ERROR_INJECT_PG = 0x800D1C200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TX_FIR_MASK_PG = 0x800D0C2006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_FIR_MASK_PG = 0x800D0C200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TX_FIR_PG = 0x800D042006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_FIR_PG = 0x800D04200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TX_FIR_RESET_PG = 0x800D142006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_FIR_RESET_PG = 0x800D14200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TX_ID1_PG = 0x800C0C2006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_ID1_PG = 0x800C0C200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TX_ID2_PG = 0x800C842006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_ID2_PG = 0x800C84200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX1_TX_SPARE_MODE_PG = 0x800C042006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_SPARE_MODE_PG = 0x800C04200601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX_IMPCAL2_PB = 0x800F3C0006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL2_PB = 0x800F3C000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX_IMPCAL_NVAL_PB = 0x800F0C0006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL_NVAL_PB = 0x800F0C000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX_IMPCAL_PB = 0x800F040006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL_PB = 0x800F04000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX_IMPCAL_PVAL_PB = 0x800F140006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL_PVAL_PB = 0x800F14000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX_IMPCAL_P_4X_PB = 0x800F1C0006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL_P_4X_PB = 0x800F1C000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX_IMPCAL_SWO1_PB = 0x800F240006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL_SWO1_PB = 0x800F24000601103Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_IOF1_TX_IMPCAL_SWO2_PB = 0x800F2C0006010C3Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL_SWO2_PB = 0x800F2C000601103Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_C0_S0_P0_E9_IOF2_C0_S0_P0_E9_IOF2_FIR_MASK_REG = 0x06011403ull;
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_C0_S0_P0_E9_IOF2_C0_S0_P0_E9_IOF2_FIR_MASK_REG_AND = 0x06011404ull;
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_C0_S0_P0_E9_IOF2_C0_S0_P0_E9_IOF2_FIR_MASK_REG_OR = 0x06011405ull;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_C0_S0_P0_E9_IOF2_C0_S0_P0_E9_IOF2_FIR_REG = 0x06011400ull;
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_C0_S0_P0_E9_IOF2_C0_S0_P0_E9_IOF2_FIR_REG_AND = 0x06011401ull;
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_C0_S0_P0_E9_IOF2_C0_S0_P0_E9_IOF2_FIR_REG_OR = 0x06011402ull;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_FIR_ACTION0_REG = 0x06011406ull;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_FIR_ACTION1_REG = 0x06011407ull;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_FIR_WOF_REG = 0x06011408ull;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL = 0x8003000D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL = 0x8002480D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_E_PL = 0x8003080D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL = 0x8002500D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_E_PL = 0x8003100D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL = 0x8002580D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL5_EO_PL = 0x8002600D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL = 0x8002400D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL = 0x8002200D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_E_PL = 0x8002C00D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE0_RX_BIT_MODE2_EO_PL = 0x8002280D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE0_RX_BIT_MODE2_E_PL = 0x8002C80D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL = 0x8002300D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE0_RX_BIT_STAT1_EO_PL = 0x8002680D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL = 0x8002700D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL = 0x8002780D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL = 0x8000080D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_E_PL = 0x8000800D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL = 0x8000100D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_E_PL = 0x8000880D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_EO_PL = 0x8000180D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_E_PL = 0x8000900D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_EO_PL = 0x8000200D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_E_PL = 0x8000980D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL = 0x8000280D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_E_PL = 0x8000A00D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_EO_PL = 0x8000300D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_E_PL = 0x8000A80D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL7_EO_PL = 0x8000380D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL7_E_PL = 0x8000B00D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL8_EO_PL = 0x8000400D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL8_E_PL = 0x8000B80D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL9_E_PL = 0x8000C00D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x8000000D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE0_RX_FIR_ERROR_INJECT_PL = 0x8002180D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE0_RX_FIR_MASK_PL = 0x8002100D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE0_RX_FIR_PL = 0x8002080D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE0_RX_SPARE_MODE_PL = 0x8002000D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL = 0x8003000F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL = 0x8002480F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_E_PL = 0x8003080F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL = 0x8002500F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_E_PL = 0x8003100F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL = 0x8002580F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL5_EO_PL = 0x8002600F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL = 0x8002400F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL = 0x8002200F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_E_PL = 0x8002C00F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE1_RX_BIT_MODE2_EO_PL = 0x8002280F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE1_RX_BIT_MODE2_E_PL = 0x8002C80F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL = 0x8002300F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE1_RX_BIT_STAT1_EO_PL = 0x8002680F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL = 0x8002700F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL = 0x8002780F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL = 0x8000080F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_E_PL = 0x8000800F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL = 0x8000100F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_E_PL = 0x8000880F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_EO_PL = 0x8000180F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_E_PL = 0x8000900F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_EO_PL = 0x8000200F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_E_PL = 0x8000980F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL = 0x8000280F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_E_PL = 0x8000A00F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_EO_PL = 0x8000300F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_E_PL = 0x8000A80F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL7_EO_PL = 0x8000380F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL7_E_PL = 0x8000B00F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL8_EO_PL = 0x8000400F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL8_E_PL = 0x8000B80F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL9_E_PL = 0x8000C00F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x8000000F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE1_RX_FIR_ERROR_INJECT_PL = 0x8002180F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE1_RX_FIR_MASK_PL = 0x8002100F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE1_RX_FIR_PL = 0x8002080F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE1_RX_SPARE_MODE_PL = 0x8002000F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL = 0x8003000E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL = 0x8002480E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_E_PL = 0x8003080E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL = 0x8002500E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_E_PL = 0x8003100E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL = 0x8002580E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL5_EO_PL = 0x8002600E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL = 0x8002400E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL = 0x8002200E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_E_PL = 0x8002C00E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE2_RX_BIT_MODE2_EO_PL = 0x8002280E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE2_RX_BIT_MODE2_E_PL = 0x8002C80E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL = 0x8002300E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE2_RX_BIT_STAT1_EO_PL = 0x8002680E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL = 0x8002700E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL = 0x8002780E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL = 0x8000080E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_E_PL = 0x8000800E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL = 0x8000100E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_E_PL = 0x8000880E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_EO_PL = 0x8000180E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_E_PL = 0x8000900E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_EO_PL = 0x8000200E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_E_PL = 0x8000980E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL = 0x8000280E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_E_PL = 0x8000A00E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_EO_PL = 0x8000300E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_E_PL = 0x8000A80E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL7_EO_PL = 0x8000380E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL7_E_PL = 0x8000B00E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL8_EO_PL = 0x8000400E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL8_E_PL = 0x8000B80E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL9_E_PL = 0x8000C00E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x8000000E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE2_RX_FIR_ERROR_INJECT_PL = 0x8002180E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE2_RX_FIR_MASK_PL = 0x8002100E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE2_RX_FIR_PL = 0x8002080E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE2_RX_SPARE_MODE_PL = 0x8002000E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL = 0x800300100601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL = 0x800248100601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_E_PL = 0x800308100601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL = 0x800250100601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_E_PL = 0x800310100601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL = 0x800258100601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL5_EO_PL = 0x800260100601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL = 0x800240100601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL = 0x800220100601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_E_PL = 0x8002C0100601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE3_RX_BIT_MODE2_EO_PL = 0x800228100601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE3_RX_BIT_MODE2_E_PL = 0x8002C8100601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL = 0x800230100601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE3_RX_BIT_STAT1_EO_PL = 0x800268100601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL = 0x800270100601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL = 0x800278100601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL = 0x800008100601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_E_PL = 0x800080100601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL = 0x800010100601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_E_PL = 0x800088100601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL3_EO_PL = 0x800018100601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL3_E_PL = 0x800090100601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_EO_PL = 0x800020100601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_E_PL = 0x800098100601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL = 0x800028100601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_E_PL = 0x8000A0100601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL6_EO_PL = 0x800030100601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL6_E_PL = 0x8000A8100601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL7_EO_PL = 0x800038100601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL7_E_PL = 0x8000B0100601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL8_EO_PL = 0x800040100601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL8_E_PL = 0x8000B8100601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL9_E_PL = 0x8000C0100601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x800000100601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE3_RX_FIR_ERROR_INJECT_PL = 0x800218100601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE3_RX_FIR_MASK_PL = 0x800210100601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE3_RX_FIR_PL = 0x800208100601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS0_SLICE3_RX_SPARE_MODE_PL = 0x800200100601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL = 0x8003000B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL = 0x8002480B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_E_PL = 0x8003080B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL = 0x8002500B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_E_PL = 0x8003100B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL = 0x8002580B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL5_EO_PL = 0x8002600B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL = 0x8002400B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL = 0x8002200B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE0_RX_BIT_MODE1_E_PL = 0x8002C00B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE0_RX_BIT_MODE2_EO_PL = 0x8002280B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE0_RX_BIT_MODE2_E_PL = 0x8002C80B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL = 0x8002300B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE0_RX_BIT_STAT1_EO_PL = 0x8002680B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL = 0x8002700B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL = 0x8002780B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL = 0x8000080B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_E_PL = 0x8000800B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_EO_PL = 0x8000100B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_E_PL = 0x8000880B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL3_EO_PL = 0x8000180B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL3_E_PL = 0x8000900B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_EO_PL = 0x8000200B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_E_PL = 0x8000980B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL = 0x8000280B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_E_PL = 0x8000A00B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL6_EO_PL = 0x8000300B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL6_E_PL = 0x8000A80B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL7_EO_PL = 0x8000380B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL7_E_PL = 0x8000B00B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL8_EO_PL = 0x8000400B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL8_E_PL = 0x8000B80B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL9_E_PL = 0x8000C00B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x8000000B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE0_RX_FIR_ERROR_INJECT_PL = 0x8002180B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE0_RX_FIR_MASK_PL = 0x8002100B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE0_RX_FIR_PL = 0x8002080B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE0_RX_SPARE_MODE_PL = 0x8002000B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL = 0x800300090601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL = 0x800248090601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_E_PL = 0x800308090601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL = 0x800250090601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_E_PL = 0x800310090601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL = 0x800258090601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL5_EO_PL = 0x800260090601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL = 0x800240090601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL = 0x800220090601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE1_RX_BIT_MODE1_E_PL = 0x8002C0090601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE1_RX_BIT_MODE2_EO_PL = 0x800228090601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE1_RX_BIT_MODE2_E_PL = 0x8002C8090601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL = 0x800230090601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE1_RX_BIT_STAT1_EO_PL = 0x800268090601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL = 0x800270090601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL = 0x800278090601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL = 0x800008090601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_E_PL = 0x800080090601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_EO_PL = 0x800010090601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_E_PL = 0x800088090601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL3_EO_PL = 0x800018090601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL3_E_PL = 0x800090090601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_EO_PL = 0x800020090601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_E_PL = 0x800098090601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL = 0x800028090601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_E_PL = 0x8000A0090601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL6_EO_PL = 0x800030090601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL6_E_PL = 0x8000A8090601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL7_EO_PL = 0x800038090601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL7_E_PL = 0x8000B0090601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL8_EO_PL = 0x800040090601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL8_E_PL = 0x8000B8090601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL9_E_PL = 0x8000C0090601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x800000090601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE1_RX_FIR_ERROR_INJECT_PL = 0x800218090601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE1_RX_FIR_MASK_PL = 0x800210090601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE1_RX_FIR_PL = 0x800208090601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE1_RX_SPARE_MODE_PL = 0x800200090601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL = 0x8003000C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL = 0x8002480C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_E_PL = 0x8003080C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL = 0x8002500C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_E_PL = 0x8003100C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL = 0x8002580C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL5_EO_PL = 0x8002600C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL = 0x8002400C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL = 0x8002200C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE2_RX_BIT_MODE1_E_PL = 0x8002C00C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE2_RX_BIT_MODE2_EO_PL = 0x8002280C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE2_RX_BIT_MODE2_E_PL = 0x8002C80C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL = 0x8002300C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE2_RX_BIT_STAT1_EO_PL = 0x8002680C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL = 0x8002700C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL = 0x8002780C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL = 0x8000080C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_E_PL = 0x8000800C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_EO_PL = 0x8000100C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_E_PL = 0x8000880C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL3_EO_PL = 0x8000180C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL3_E_PL = 0x8000900C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_EO_PL = 0x8000200C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_E_PL = 0x8000980C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL = 0x8000280C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_E_PL = 0x8000A00C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL6_EO_PL = 0x8000300C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL6_E_PL = 0x8000A80C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL7_EO_PL = 0x8000380C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL7_E_PL = 0x8000B00C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL8_EO_PL = 0x8000400C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL8_E_PL = 0x8000B80C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL9_E_PL = 0x8000C00C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x8000000C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE2_RX_FIR_ERROR_INJECT_PL = 0x8002180C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE2_RX_FIR_MASK_PL = 0x8002100C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE2_RX_FIR_PL = 0x8002080C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE2_RX_SPARE_MODE_PL = 0x8002000C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL = 0x8003000A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL = 0x8002480A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_E_PL = 0x8003080A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL = 0x8002500A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_E_PL = 0x8003100A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL = 0x8002580A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL5_EO_PL = 0x8002600A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL = 0x8002400A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL = 0x8002200A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE3_RX_BIT_MODE1_E_PL = 0x8002C00A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE3_RX_BIT_MODE2_EO_PL = 0x8002280A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE3_RX_BIT_MODE2_E_PL = 0x8002C80A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL = 0x8002300A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE3_RX_BIT_STAT1_EO_PL = 0x8002680A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL = 0x8002700A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL = 0x8002780A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL = 0x8000080A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_E_PL = 0x8000800A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_EO_PL = 0x8000100A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_E_PL = 0x8000880A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL3_EO_PL = 0x8000180A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL3_E_PL = 0x8000900A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_EO_PL = 0x8000200A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_E_PL = 0x8000980A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL = 0x8000280A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_E_PL = 0x8000A00A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL6_EO_PL = 0x8000300A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL6_E_PL = 0x8000A80A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL7_EO_PL = 0x8000380A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL7_E_PL = 0x8000B00A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL8_EO_PL = 0x8000400A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL8_E_PL = 0x8000B80A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL9_E_PL = 0x8000C00A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x8000000A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE3_RX_FIR_ERROR_INJECT_PL = 0x8002180A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE3_RX_FIR_MASK_PL = 0x8002100A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE3_RX_FIR_PL = 0x8002080A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS1_SLICE3_RX_SPARE_MODE_PL = 0x8002000A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL = 0x800300070601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL = 0x800248070601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_E_PL = 0x800308070601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL = 0x800250070601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_E_PL = 0x800310070601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL = 0x800258070601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL5_EO_PL = 0x800260070601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL = 0x800240070601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL = 0x800220070601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE0_RX_BIT_MODE1_E_PL = 0x8002C0070601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE0_RX_BIT_MODE2_EO_PL = 0x800228070601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE0_RX_BIT_MODE2_E_PL = 0x8002C8070601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL = 0x800230070601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE0_RX_BIT_STAT1_EO_PL = 0x800268070601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL = 0x800270070601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL = 0x800278070601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL = 0x800008070601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_E_PL = 0x800080070601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_EO_PL = 0x800010070601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_E_PL = 0x800088070601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL3_EO_PL = 0x800018070601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL3_E_PL = 0x800090070601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_EO_PL = 0x800020070601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_E_PL = 0x800098070601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL = 0x800028070601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_E_PL = 0x8000A0070601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL6_EO_PL = 0x800030070601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL6_E_PL = 0x8000A8070601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL7_EO_PL = 0x800038070601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL7_E_PL = 0x8000B0070601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL8_EO_PL = 0x800040070601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL8_E_PL = 0x8000B8070601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL9_E_PL = 0x8000C0070601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x800000070601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE0_RX_FIR_ERROR_INJECT_PL = 0x800218070601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE0_RX_FIR_MASK_PL = 0x800210070601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE0_RX_FIR_PL = 0x800208070601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE0_RX_SPARE_MODE_PL = 0x800200070601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL = 0x800300110601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL = 0x800248110601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_E_PL = 0x800308110601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL = 0x800250110601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_E_PL = 0x800310110601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL = 0x800258110601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL5_EO_PL = 0x800260110601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL = 0x800240110601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL = 0x800220110601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE1_RX_BIT_MODE1_E_PL = 0x8002C0110601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE1_RX_BIT_MODE2_EO_PL = 0x800228110601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE1_RX_BIT_MODE2_E_PL = 0x8002C8110601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL = 0x800230110601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE1_RX_BIT_STAT1_EO_PL = 0x800268110601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL = 0x800270110601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL = 0x800278110601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL = 0x800008110601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_E_PL = 0x800080110601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_EO_PL = 0x800010110601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_E_PL = 0x800088110601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL3_EO_PL = 0x800018110601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL3_E_PL = 0x800090110601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_EO_PL = 0x800020110601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_E_PL = 0x800098110601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL = 0x800028110601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_E_PL = 0x8000A0110601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL6_EO_PL = 0x800030110601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL6_E_PL = 0x8000A8110601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL7_EO_PL = 0x800038110601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL7_E_PL = 0x8000B0110601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL8_EO_PL = 0x800040110601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL8_E_PL = 0x8000B8110601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL9_E_PL = 0x8000C0110601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x800000110601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE1_RX_FIR_ERROR_INJECT_PL = 0x800218110601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE1_RX_FIR_MASK_PL = 0x800210110601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE1_RX_FIR_PL = 0x800208110601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE1_RX_SPARE_MODE_PL = 0x800200110601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL = 0x800300060601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL = 0x800248060601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_E_PL = 0x800308060601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL = 0x800250060601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_E_PL = 0x800310060601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL = 0x800258060601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL5_EO_PL = 0x800260060601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL = 0x800240060601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL = 0x800220060601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE2_RX_BIT_MODE1_E_PL = 0x8002C0060601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE2_RX_BIT_MODE2_EO_PL = 0x800228060601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE2_RX_BIT_MODE2_E_PL = 0x8002C8060601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL = 0x800230060601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE2_RX_BIT_STAT1_EO_PL = 0x800268060601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL = 0x800270060601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL = 0x800278060601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL = 0x800008060601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_E_PL = 0x800080060601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_EO_PL = 0x800010060601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_E_PL = 0x800088060601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL3_EO_PL = 0x800018060601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL3_E_PL = 0x800090060601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_EO_PL = 0x800020060601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_E_PL = 0x800098060601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL = 0x800028060601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_E_PL = 0x8000A0060601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL6_EO_PL = 0x800030060601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL6_E_PL = 0x8000A8060601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL7_EO_PL = 0x800038060601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL7_E_PL = 0x8000B0060601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL8_EO_PL = 0x800040060601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL8_E_PL = 0x8000B8060601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL9_E_PL = 0x8000C0060601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x800000060601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE2_RX_FIR_ERROR_INJECT_PL = 0x800218060601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE2_RX_FIR_MASK_PL = 0x800210060601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE2_RX_FIR_PL = 0x800208060601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE2_RX_SPARE_MODE_PL = 0x800200060601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL = 0x800300080601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL = 0x800248080601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_E_PL = 0x800308080601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL = 0x800250080601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_E_PL = 0x800310080601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL = 0x800258080601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL5_EO_PL = 0x800260080601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL = 0x800240080601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL = 0x800220080601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE3_RX_BIT_MODE1_E_PL = 0x8002C0080601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE3_RX_BIT_MODE2_EO_PL = 0x800228080601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE3_RX_BIT_MODE2_E_PL = 0x8002C8080601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL = 0x800230080601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE3_RX_BIT_STAT1_EO_PL = 0x800268080601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL = 0x800270080601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL = 0x800278080601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL = 0x800008080601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_E_PL = 0x800080080601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_EO_PL = 0x800010080601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_E_PL = 0x800088080601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL3_EO_PL = 0x800018080601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL3_E_PL = 0x800090080601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_EO_PL = 0x800020080601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_E_PL = 0x800098080601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL = 0x800028080601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_E_PL = 0x8000A0080601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL6_EO_PL = 0x800030080601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL6_E_PL = 0x8000A8080601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL7_EO_PL = 0x800038080601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL7_E_PL = 0x8000B0080601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL8_EO_PL = 0x800040080601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL8_E_PL = 0x8000B8080601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL9_E_PL = 0x8000C0080601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x800000080601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE3_RX_FIR_ERROR_INJECT_PL = 0x800218080601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE3_RX_FIR_MASK_PL = 0x800210080601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE3_RX_FIR_PL = 0x800208080601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS2_SLICE3_RX_SPARE_MODE_PL = 0x800200080601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL = 0x800300040601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL = 0x800248040601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_E_PL = 0x800308040601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL = 0x800250040601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_E_PL = 0x800310040601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL = 0x800258040601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL5_EO_PL = 0x800260040601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL = 0x800240040601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL = 0x800220040601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE0_RX_BIT_MODE1_E_PL = 0x8002C0040601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE0_RX_BIT_MODE2_EO_PL = 0x800228040601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE0_RX_BIT_MODE2_E_PL = 0x8002C8040601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL = 0x800230040601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE0_RX_BIT_STAT1_EO_PL = 0x800268040601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL = 0x800270040601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL = 0x800278040601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL = 0x800008040601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_E_PL = 0x800080040601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_EO_PL = 0x800010040601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_E_PL = 0x800088040601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL3_EO_PL = 0x800018040601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL3_E_PL = 0x800090040601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_EO_PL = 0x800020040601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_E_PL = 0x800098040601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL = 0x800028040601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_E_PL = 0x8000A0040601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL6_EO_PL = 0x800030040601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL6_E_PL = 0x8000A8040601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL7_EO_PL = 0x800038040601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL7_E_PL = 0x8000B0040601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL8_EO_PL = 0x800040040601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL8_E_PL = 0x8000B8040601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL9_E_PL = 0x8000C0040601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x800000040601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE0_RX_FIR_ERROR_INJECT_PL = 0x800218040601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE0_RX_FIR_MASK_PL = 0x800210040601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE0_RX_FIR_PL = 0x800208040601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE0_RX_SPARE_MODE_PL = 0x800200040601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL = 0x800300020601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL = 0x800248020601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_E_PL = 0x800308020601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL = 0x800250020601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_E_PL = 0x800310020601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL = 0x800258020601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL5_EO_PL = 0x800260020601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL = 0x800240020601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL = 0x800220020601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE1_RX_BIT_MODE1_E_PL = 0x8002C0020601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE1_RX_BIT_MODE2_EO_PL = 0x800228020601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE1_RX_BIT_MODE2_E_PL = 0x8002C8020601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL = 0x800230020601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE1_RX_BIT_STAT1_EO_PL = 0x800268020601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL = 0x800270020601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL = 0x800278020601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL = 0x800008020601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_E_PL = 0x800080020601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_EO_PL = 0x800010020601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_E_PL = 0x800088020601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL3_EO_PL = 0x800018020601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL3_E_PL = 0x800090020601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_EO_PL = 0x800020020601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_E_PL = 0x800098020601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL = 0x800028020601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_E_PL = 0x8000A0020601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL6_EO_PL = 0x800030020601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL6_E_PL = 0x8000A8020601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL7_EO_PL = 0x800038020601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL7_E_PL = 0x8000B0020601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL8_EO_PL = 0x800040020601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL8_E_PL = 0x8000B8020601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL9_E_PL = 0x8000C0020601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x800000020601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE1_RX_FIR_ERROR_INJECT_PL = 0x800218020601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE1_RX_FIR_MASK_PL = 0x800210020601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE1_RX_FIR_PL = 0x800208020601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE1_RX_SPARE_MODE_PL = 0x800200020601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL = 0x800300050601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL = 0x800248050601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_E_PL = 0x800308050601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL = 0x800250050601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_E_PL = 0x800310050601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL = 0x800258050601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL5_EO_PL = 0x800260050601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL = 0x800240050601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL = 0x800220050601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE2_RX_BIT_MODE1_E_PL = 0x8002C0050601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE2_RX_BIT_MODE2_EO_PL = 0x800228050601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE2_RX_BIT_MODE2_E_PL = 0x8002C8050601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL = 0x800230050601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE2_RX_BIT_STAT1_EO_PL = 0x800268050601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL = 0x800270050601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL = 0x800278050601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL = 0x800008050601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_E_PL = 0x800080050601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_EO_PL = 0x800010050601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_E_PL = 0x800088050601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL3_EO_PL = 0x800018050601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL3_E_PL = 0x800090050601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_EO_PL = 0x800020050601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_E_PL = 0x800098050601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL = 0x800028050601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_E_PL = 0x8000A0050601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL6_EO_PL = 0x800030050601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL6_E_PL = 0x8000A8050601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL7_EO_PL = 0x800038050601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL7_E_PL = 0x8000B0050601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL8_EO_PL = 0x800040050601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL8_E_PL = 0x8000B8050601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL9_E_PL = 0x8000C0050601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x800000050601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE2_RX_FIR_ERROR_INJECT_PL = 0x800218050601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE2_RX_FIR_MASK_PL = 0x800210050601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE2_RX_FIR_PL = 0x800208050601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE2_RX_SPARE_MODE_PL = 0x800200050601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL = 0x800300030601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL = 0x800248030601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_E_PL = 0x800308030601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL = 0x800250030601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_E_PL = 0x800310030601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL = 0x800258030601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL5_EO_PL = 0x800260030601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL = 0x800240030601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL = 0x800220030601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE3_RX_BIT_MODE1_E_PL = 0x8002C0030601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE3_RX_BIT_MODE2_EO_PL = 0x800228030601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE3_RX_BIT_MODE2_E_PL = 0x8002C8030601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL = 0x800230030601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE3_RX_BIT_STAT1_EO_PL = 0x800268030601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL = 0x800270030601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL = 0x800278030601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL = 0x800008030601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_E_PL = 0x800080030601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_EO_PL = 0x800010030601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_E_PL = 0x800088030601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL3_EO_PL = 0x800018030601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL3_E_PL = 0x800090030601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_EO_PL = 0x800020030601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_E_PL = 0x800098030601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL = 0x800028030601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_E_PL = 0x8000A0030601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL6_EO_PL = 0x800030030601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL6_E_PL = 0x8000A8030601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL7_EO_PL = 0x800038030601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL7_E_PL = 0x8000B0030601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL8_EO_PL = 0x800040030601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL8_E_PL = 0x8000B8030601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL9_E_PL = 0x8000C0030601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x800000030601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE3_RX_FIR_ERROR_INJECT_PL = 0x800218030601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE3_RX_FIR_MASK_PL = 0x800210030601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE3_RX_FIR_PL = 0x800208030601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE3_RX_SPARE_MODE_PL = 0x800200030601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL = 0x800300000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL2_EO_PL = 0x800248000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL2_E_PL = 0x800308000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL3_EO_PL = 0x800250000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL3_E_PL = 0x800310000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL4_EO_PL = 0x800258000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL5_EO_PL = 0x800260000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL = 0x800240000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE4_RX_BIT_MODE1_EO_PL = 0x800220000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE4_RX_BIT_MODE1_E_PL = 0x8002C0000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE4_RX_BIT_MODE2_EO_PL = 0x800228000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE4_RX_BIT_MODE2_E_PL = 0x8002C8000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE4_RX_BIT_MODE3_EO_PL = 0x800230000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE4_RX_BIT_STAT1_EO_PL = 0x800268000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE4_RX_BIT_STAT2_EO_PL = 0x800270000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE4_RX_BIT_STAT3_EO_PL = 0x800278000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL1_EO_PL = 0x800008000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL1_E_PL = 0x800080000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL2_EO_PL = 0x800010000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL2_E_PL = 0x800088000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL3_EO_PL = 0x800018000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL3_E_PL = 0x800090000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL4_EO_PL = 0x800020000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL4_E_PL = 0x800098000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL5_EO_PL = 0x800028000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL5_E_PL = 0x8000A0000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL6_EO_PL = 0x800030000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL6_E_PL = 0x8000A8000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL7_EO_PL = 0x800038000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL7_E_PL = 0x8000B0000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL8_EO_PL = 0x800040000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL8_E_PL = 0x8000B8000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL9_E_PL = 0x8000C0000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE4_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x800000000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE4_RX_FIR_ERROR_INJECT_PL = 0x800218000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE4_RX_FIR_MASK_PL = 0x800210000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE4_RX_FIR_PL = 0x800208000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE4_RX_SPARE_MODE_PL = 0x800200000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL = 0x800300010601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL2_EO_PL = 0x800248010601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL2_E_PL = 0x800308010601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL3_EO_PL = 0x800250010601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL3_E_PL = 0x800310010601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL4_EO_PL = 0x800258010601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL5_EO_PL = 0x800260010601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL = 0x800240010601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE5_RX_BIT_MODE1_EO_PL = 0x800220010601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE5_RX_BIT_MODE1_E_PL = 0x8002C0010601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE5_RX_BIT_MODE2_EO_PL = 0x800228010601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE5_RX_BIT_MODE2_E_PL = 0x8002C8010601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE5_RX_BIT_MODE3_EO_PL = 0x800230010601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE5_RX_BIT_STAT1_EO_PL = 0x800268010601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE5_RX_BIT_STAT2_EO_PL = 0x800270010601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE5_RX_BIT_STAT3_EO_PL = 0x800278010601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL1_EO_PL = 0x800008010601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL1_E_PL = 0x800080010601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL2_EO_PL = 0x800010010601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL2_E_PL = 0x800088010601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL3_EO_PL = 0x800018010601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL3_E_PL = 0x800090010601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL4_EO_PL = 0x800020010601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL4_E_PL = 0x800098010601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL5_EO_PL = 0x800028010601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL5_E_PL = 0x8000A0010601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL6_EO_PL = 0x800030010601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL6_E_PL = 0x8000A8010601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL7_EO_PL = 0x800038010601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL7_E_PL = 0x8000B0010601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL8_EO_PL = 0x800040010601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL8_E_PL = 0x8000B8010601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL9_E_PL = 0x8000C0010601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE5_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x800000010601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE5_RX_FIR_ERROR_INJECT_PL = 0x800218010601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE5_RX_FIR_MASK_PL = 0x800210010601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE5_RX_FIR_PL = 0x800208010601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RXPACKS3_SLICE5_RX_SPARE_MODE_PL = 0x800200010601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_CTL_CNTL10_EO_PG = 0x800920000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_CTL_CNTL11_EO_PG = 0x800928000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_CTL_CNTL12_EO_PG = 0x800930000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_CTL_CNTL13_EO_PG = 0x800938000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_CTL_CNTL14_EO_PG = 0x800940000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_CTL_CNTL15_EO_PG = 0x800948000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_CTL_CNTL1_EO_PG = 0x8008D8000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_CTL_CNTL1_E_PG = 0x8009F0000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_CTL_CNTL2_EO_PG = 0x8008E0000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_CTL_CNTL3_EO_PG = 0x8008E8000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_CTL_CNTL4_EO_PG = 0x8008F0000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_CTL_CNTL4_E_PG = 0x8009F8000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_CTL_CNTL5_EO_PG = 0x8008F8000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_CTL_CNTL6_EO_PG = 0x800900000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_CTL_CNTL8_EO_PG = 0x800910000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_CTL_CNTL9_EO_PG = 0x800918000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_CTL_CNTLX11_E_PG = 0x800A30000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_CTL_CNTLX7_EO_PG = 0x800908000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_CTL_MODE10_EO_PG = 0x800858000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_CTL_MODE10_E_PG = 0x8009D8000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_CTL_MODE11_EO_PG = 0x800860000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_CTL_MODE11_E_PG = 0x8009E0000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_CTL_MODE12_EO_PG = 0x800868000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_CTL_MODE12_E_PG = 0x8009E8000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_CTL_MODE13_EO_PG = 0x800870000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_CTL_MODE14_EO_PG = 0x800878000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_CTL_MODE15_EO_PG = 0x800880000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_CTL_MODE16_EO_PG = 0x800888000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_CTL_MODE17_EO_PG = 0x800890000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_CTL_MODE18_EO_PG = 0x800898000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_CTL_MODE19_EO_PG = 0x8008A0000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_CTL_MODE1_EO_PG = 0x800810000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_CTL_MODE1_E_PG = 0x800990000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_CTL_MODE20_EO_PG = 0x8008A8000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_CTL_MODE21_EO_PG = 0x8008B0000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_CTL_MODE22_EO_PG = 0x8008B8000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_CTL_MODE23_EO_PG = 0x8008C0000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_CTL_MODE24_EO_PG = 0x8008C8000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_CTL_MODE26_EO_PG = 0x800968000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_CTL_MODE27_EO_PG = 0x800970000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_CTL_MODE28_EO_PG = 0x800978000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_CTL_MODE29_EO_PG = 0x8008D0000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_CTL_MODE2_EO_PG = 0x800818000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_CTL_MODE2_E_PG = 0x800998000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_CTL_MODE3_EO_PG = 0x800820000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_CTL_MODE3_E_PG = 0x8009A0000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_CTL_MODE4_EO_PG = 0x800828000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_CTL_MODE4_E_PG = 0x8009A8000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_CTL_MODE5_EO_PG = 0x800830000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_CTL_MODE5_E_PG = 0x8009B0000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_CTL_MODE6_EO_PG = 0x800838000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_CTL_MODE6_E_PG = 0x8009B8000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_CTL_MODE7_EO_PG = 0x800840000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_CTL_MODE7_E_PG = 0x8009C0000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_CTL_MODE8_EO_PG = 0x800848000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_CTL_MODE8_E_PG = 0x8009C8000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_CTL_MODE9_EO_PG = 0x800850000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_CTL_MODE9_E_PG = 0x8009D0000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_CTL_STAT1_EO_PG = 0x800950000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_CTL_STAT1_E_PG = 0x800A38000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_CTL_STAT2_EO_PG = 0x800958000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_CTL_STAT2_E_PG = 0x800A40000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_CTL_STAT3_EO_PG = 0x800960000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_CTL_STAT4_E_PG = 0x800A50000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_CTL_STAT5_E_PG = 0x800A58000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_CTL_STAT6_E_PG = 0x800A60000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_CTL_STATX8_E_PG = 0x800A68000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_DATASM_CNTL1_E_PG = 0x800BE8000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_DATASM_CNTL2_EO_PG = 0x800B78000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_DATASM_CNTLX1_EO_PG = 0x800B88000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_DATASM_SPARE_MODE_PG = 0x800B80000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_DATASM_STAT10_EO_PG = 0x800BD8000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_DATASM_STAT11_EO_PG = 0x800BE0000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_DATASM_STAT12_EO_PG = 0x800BF0000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_DATASM_STAT13_E_PG = 0x800BF8000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_DATASM_STAT1_EO_PG = 0x800B90000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_DATASM_STAT2_EO_PG = 0x800B98000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_DATASM_STAT3_EO_PG = 0x800BA0000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_DATASM_STAT4_EO_PG = 0x800BA8000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_DATASM_STAT5_EO_PG = 0x800BB0000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_DATASM_STAT6_EO_PG = 0x800BB8000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_DATASM_STAT7_EO_PG = 0x800BC0000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_DATASM_STAT8_EO_PG = 0x800BC8000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_DATASM_STAT9_EO_PG = 0x800BD0000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_FIR1_ERROR_INJECT_PG = 0x800A98000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_FIR1_MASK_PG = 0x800A90000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_FIR1_PG = 0x800A88000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_FIR2_ERROR_INJECT_PG = 0x800B10000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_FIR2_MASK_PG = 0x800B08000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_FIR2_PG = 0x800B00000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_FIR_TRAINING_MASK_PG = 0x800AA8000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_FIR_TRAINING_PG = 0x800AA0000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_GLBSM_CNTL2_EO_PG = 0x800AE0000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_GLBSM_CNTL3_EO_PG = 0x800AE8000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_GLBSM_CNTL4_EO_PG = 0x800AF0000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_GLBSM_CNTLX1_EO_PG = 0x800AB0000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_GLBSM_MODE1_EO_PG = 0x800AF8000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_GLBSM_SPARE_MODE_PG = 0x800A80000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_GLBSM_STAT10_E_PG = 0x800B60000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_GLBSM_STAT11_E_PG = 0x800B68000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_GLBSM_STAT1_EO_PG = 0x800AB8000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_GLBSM_STAT1_E_PG = 0x800B18000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_GLBSM_STAT2_EO_PG = 0x800AC0000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_GLBSM_STAT2_E_PG = 0x800B20000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_GLBSM_STAT3_EO_PG = 0x800AC8000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_GLBSM_STAT3_E_PG = 0x800B28000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_GLBSM_STAT4_EO_PG = 0x800AD0000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_GLBSM_STAT4_E_PG = 0x800B30000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_GLBSM_STAT5_EO_PG = 0x800AD8000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_GLBSM_STAT7_E_PG = 0x800B48000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_GLBSM_STAT8_E_PG = 0x800B50000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_GLBSM_STAT9_E_PG = 0x800B58000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_ID1_PG = 0x800808000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_ID2_PG = 0x800980000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_RX_SPARE_MODE_PG = 0x800800000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE0_RX_DATA_WORK_SPARE_MODE_PL = 0x8003800D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE0_RX_WORK_STAT1_EO_PL = 0x8003880D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE0_RX_WORK_STAT2_EO_PL = 0x8003900D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE0_RX_WORK_STAT3_EO_PL = 0x8003980D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE10_RX_DATA_WORK_SPARE_MODE_PL = 0x800380060601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE10_RX_WORK_STAT1_EO_PL = 0x800388060601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE10_RX_WORK_STAT2_EO_PL = 0x800390060601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE10_RX_WORK_STAT3_EO_PL = 0x800398060601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE11_RX_DATA_WORK_SPARE_MODE_PL = 0x800380080601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE11_RX_WORK_STAT1_EO_PL = 0x800388080601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE11_RX_WORK_STAT2_EO_PL = 0x800390080601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE11_RX_WORK_STAT3_EO_PL = 0x800398080601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE12_RX_DATA_WORK_SPARE_MODE_PL = 0x800380040601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE12_RX_WORK_STAT1_EO_PL = 0x800388040601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE12_RX_WORK_STAT2_EO_PL = 0x800390040601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE12_RX_WORK_STAT3_EO_PL = 0x800398040601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE13_RX_DATA_WORK_SPARE_MODE_PL = 0x800380020601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE13_RX_WORK_STAT1_EO_PL = 0x800388020601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE13_RX_WORK_STAT2_EO_PL = 0x800390020601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE13_RX_WORK_STAT3_EO_PL = 0x800398020601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE14_RX_DATA_WORK_SPARE_MODE_PL = 0x800380050601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE14_RX_WORK_STAT1_EO_PL = 0x800388050601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE14_RX_WORK_STAT2_EO_PL = 0x800390050601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE14_RX_WORK_STAT3_EO_PL = 0x800398050601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE15_RX_DATA_WORK_SPARE_MODE_PL = 0x800380030601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE15_RX_WORK_STAT1_EO_PL = 0x800388030601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE15_RX_WORK_STAT2_EO_PL = 0x800390030601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE15_RX_WORK_STAT3_EO_PL = 0x800398030601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE16_RX_DATA_WORK_SPARE_MODE_PL = 0x800380000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE16_RX_WORK_STAT1_EO_PL = 0x800388000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE16_RX_WORK_STAT2_EO_PL = 0x800390000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE16_RX_WORK_STAT3_EO_PL = 0x800398000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE17_RX_DATA_WORK_SPARE_MODE_PL = 0x800380010601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE17_RX_WORK_STAT1_EO_PL = 0x800388010601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE17_RX_WORK_STAT2_EO_PL = 0x800390010601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE17_RX_WORK_STAT3_EO_PL = 0x800398010601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE18_RX_DATA_WORK_SPARE_MODE_PL = 0x800380120601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE18_RX_WORK_STAT1_EO_PL = 0x800388120601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE18_RX_WORK_STAT2_EO_PL = 0x800390120601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE18_RX_WORK_STAT3_EO_PL = 0x800398120601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE19_RX_DATA_WORK_SPARE_MODE_PL = 0x800380130601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE19_RX_WORK_STAT1_EO_PL = 0x800388130601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE19_RX_WORK_STAT2_EO_PL = 0x800390130601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE19_RX_WORK_STAT3_EO_PL = 0x800398130601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE1_RX_DATA_WORK_SPARE_MODE_PL = 0x8003800F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE1_RX_WORK_STAT1_EO_PL = 0x8003880F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE1_RX_WORK_STAT2_EO_PL = 0x8003900F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE1_RX_WORK_STAT3_EO_PL = 0x8003980F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE20_RX_DATA_WORK_SPARE_MODE_PL = 0x800380140601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE20_RX_WORK_STAT1_EO_PL = 0x800388140601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE20_RX_WORK_STAT2_EO_PL = 0x800390140601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE20_RX_WORK_STAT3_EO_PL = 0x800398140601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE21_RX_DATA_WORK_SPARE_MODE_PL = 0x800380150601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE21_RX_WORK_STAT1_EO_PL = 0x800388150601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE21_RX_WORK_STAT2_EO_PL = 0x800390150601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE21_RX_WORK_STAT3_EO_PL = 0x800398150601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE22_RX_DATA_WORK_SPARE_MODE_PL = 0x800380160601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE22_RX_WORK_STAT1_EO_PL = 0x800388160601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE22_RX_WORK_STAT2_EO_PL = 0x800390160601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE22_RX_WORK_STAT3_EO_PL = 0x800398160601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE23_RX_DATA_WORK_SPARE_MODE_PL = 0x800380170601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE23_RX_WORK_STAT1_EO_PL = 0x800388170601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE23_RX_WORK_STAT2_EO_PL = 0x800390170601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE23_RX_WORK_STAT3_EO_PL = 0x800398170601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE2_RX_DATA_WORK_SPARE_MODE_PL = 0x8003800E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE2_RX_WORK_STAT1_EO_PL = 0x8003880E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE2_RX_WORK_STAT2_EO_PL = 0x8003900E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE2_RX_WORK_STAT3_EO_PL = 0x8003980E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE3_RX_DATA_WORK_SPARE_MODE_PL = 0x800380100601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE3_RX_WORK_STAT1_EO_PL = 0x800388100601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE3_RX_WORK_STAT2_EO_PL = 0x800390100601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE3_RX_WORK_STAT3_EO_PL = 0x800398100601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE4_RX_DATA_WORK_SPARE_MODE_PL = 0x8003800B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE4_RX_WORK_STAT1_EO_PL = 0x8003880B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE4_RX_WORK_STAT2_EO_PL = 0x8003900B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE4_RX_WORK_STAT3_EO_PL = 0x8003980B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE5_RX_DATA_WORK_SPARE_MODE_PL = 0x800380090601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE5_RX_WORK_STAT1_EO_PL = 0x800388090601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE5_RX_WORK_STAT2_EO_PL = 0x800390090601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE5_RX_WORK_STAT3_EO_PL = 0x800398090601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE6_RX_DATA_WORK_SPARE_MODE_PL = 0x8003800C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE6_RX_WORK_STAT1_EO_PL = 0x8003880C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE6_RX_WORK_STAT2_EO_PL = 0x8003900C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE6_RX_WORK_STAT3_EO_PL = 0x8003980C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE7_RX_DATA_WORK_SPARE_MODE_PL = 0x8003800A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE7_RX_WORK_STAT1_EO_PL = 0x8003880A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE7_RX_WORK_STAT2_EO_PL = 0x8003900A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE7_RX_WORK_STAT3_EO_PL = 0x8003980A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE8_RX_DATA_WORK_SPARE_MODE_PL = 0x800380070601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE8_RX_WORK_STAT1_EO_PL = 0x800388070601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE8_RX_WORK_STAT2_EO_PL = 0x800390070601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE8_RX_WORK_STAT3_EO_PL = 0x800398070601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE9_RX_DATA_WORK_SPARE_MODE_PL = 0x800380110601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE9_RX_WORK_STAT1_EO_PL = 0x800388110601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE9_RX_WORK_STAT2_EO_PL = 0x800390110601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX0_SLICE9_RX_WORK_STAT3_EO_PL = 0x800398110601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL = 0x800300210601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL = 0x800248210601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL2_E_PL = 0x800308210601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL = 0x800250210601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL3_E_PL = 0x800310210601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL = 0x800258210601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL5_EO_PL = 0x800260210601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL = 0x800240210601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL = 0x800220210601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE0_RX_BIT_MODE1_E_PL = 0x8002C0210601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE0_RX_BIT_MODE2_EO_PL = 0x800228210601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE0_RX_BIT_MODE2_E_PL = 0x8002C8210601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL = 0x800230210601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE0_RX_BIT_STAT1_EO_PL = 0x800268210601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL = 0x800270210601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL = 0x800278210601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL = 0x800008210601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL1_E_PL = 0x800080210601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL = 0x800010210601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL2_E_PL = 0x800088210601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL3_EO_PL = 0x800018210601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL3_E_PL = 0x800090210601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL4_EO_PL = 0x800020210601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL4_E_PL = 0x800098210601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL = 0x800028210601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL5_E_PL = 0x8000A0210601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL6_EO_PL = 0x800030210601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL6_E_PL = 0x8000A8210601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL7_EO_PL = 0x800038210601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL7_E_PL = 0x8000B0210601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL8_EO_PL = 0x800040210601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL8_E_PL = 0x8000B8210601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL9_E_PL = 0x8000C0210601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x800000210601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE0_RX_FIR_ERROR_INJECT_PL = 0x800218210601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE0_RX_FIR_MASK_PL = 0x800210210601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE0_RX_FIR_PL = 0x800208210601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE0_RX_SPARE_MODE_PL = 0x800200210601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL = 0x800300230601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL = 0x800248230601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL2_E_PL = 0x800308230601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL = 0x800250230601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL3_E_PL = 0x800310230601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL = 0x800258230601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL5_EO_PL = 0x800260230601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL = 0x800240230601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL = 0x800220230601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE1_RX_BIT_MODE1_E_PL = 0x8002C0230601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE1_RX_BIT_MODE2_EO_PL = 0x800228230601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE1_RX_BIT_MODE2_E_PL = 0x8002C8230601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL = 0x800230230601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE1_RX_BIT_STAT1_EO_PL = 0x800268230601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL = 0x800270230601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL = 0x800278230601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL = 0x800008230601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL1_E_PL = 0x800080230601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL = 0x800010230601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL2_E_PL = 0x800088230601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL3_EO_PL = 0x800018230601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL3_E_PL = 0x800090230601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL4_EO_PL = 0x800020230601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL4_E_PL = 0x800098230601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL = 0x800028230601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL5_E_PL = 0x8000A0230601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL6_EO_PL = 0x800030230601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL6_E_PL = 0x8000A8230601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL7_EO_PL = 0x800038230601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL7_E_PL = 0x8000B0230601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL8_EO_PL = 0x800040230601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL8_E_PL = 0x8000B8230601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL9_E_PL = 0x8000C0230601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x800000230601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE1_RX_FIR_ERROR_INJECT_PL = 0x800218230601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE1_RX_FIR_MASK_PL = 0x800210230601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE1_RX_FIR_PL = 0x800208230601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE1_RX_SPARE_MODE_PL = 0x800200230601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL = 0x800300200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL = 0x800248200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL2_E_PL = 0x800308200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL = 0x800250200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL3_E_PL = 0x800310200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL = 0x800258200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL5_EO_PL = 0x800260200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL = 0x800240200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL = 0x800220200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE2_RX_BIT_MODE1_E_PL = 0x8002C0200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE2_RX_BIT_MODE2_EO_PL = 0x800228200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE2_RX_BIT_MODE2_E_PL = 0x8002C8200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL = 0x800230200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE2_RX_BIT_STAT1_EO_PL = 0x800268200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL = 0x800270200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL = 0x800278200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL = 0x800008200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL1_E_PL = 0x800080200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL = 0x800010200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL2_E_PL = 0x800088200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL3_EO_PL = 0x800018200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL3_E_PL = 0x800090200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL4_EO_PL = 0x800020200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL4_E_PL = 0x800098200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL = 0x800028200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL5_E_PL = 0x8000A0200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL6_EO_PL = 0x800030200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL6_E_PL = 0x8000A8200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL7_EO_PL = 0x800038200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL7_E_PL = 0x8000B0200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL8_EO_PL = 0x800040200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL8_E_PL = 0x8000B8200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL9_E_PL = 0x8000C0200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x800000200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE2_RX_FIR_ERROR_INJECT_PL = 0x800218200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE2_RX_FIR_MASK_PL = 0x800210200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE2_RX_FIR_PL = 0x800208200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE2_RX_SPARE_MODE_PL = 0x800200200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL = 0x800300220601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL = 0x800248220601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL2_E_PL = 0x800308220601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL = 0x800250220601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL3_E_PL = 0x800310220601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL = 0x800258220601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL5_EO_PL = 0x800260220601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL = 0x800240220601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL = 0x800220220601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE3_RX_BIT_MODE1_E_PL = 0x8002C0220601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE3_RX_BIT_MODE2_EO_PL = 0x800228220601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE3_RX_BIT_MODE2_E_PL = 0x8002C8220601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL = 0x800230220601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE3_RX_BIT_STAT1_EO_PL = 0x800268220601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL = 0x800270220601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL = 0x800278220601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL = 0x800008220601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL1_E_PL = 0x800080220601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL = 0x800010220601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL2_E_PL = 0x800088220601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL3_EO_PL = 0x800018220601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL3_E_PL = 0x800090220601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL4_EO_PL = 0x800020220601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL4_E_PL = 0x800098220601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL = 0x800028220601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL5_E_PL = 0x8000A0220601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL6_EO_PL = 0x800030220601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL6_E_PL = 0x8000A8220601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL7_EO_PL = 0x800038220601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL7_E_PL = 0x8000B0220601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL8_EO_PL = 0x800040220601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL8_E_PL = 0x8000B8220601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL9_E_PL = 0x8000C0220601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x800000220601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE3_RX_FIR_ERROR_INJECT_PL = 0x800218220601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE3_RX_FIR_MASK_PL = 0x800210220601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE3_RX_FIR_PL = 0x800208220601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS0_SLICE3_RX_SPARE_MODE_PL = 0x800200220601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL = 0x800300270601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL = 0x800248270601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL2_E_PL = 0x800308270601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL = 0x800250270601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL3_E_PL = 0x800310270601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL = 0x800258270601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL5_EO_PL = 0x800260270601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL = 0x800240270601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL = 0x800220270601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE0_RX_BIT_MODE1_E_PL = 0x8002C0270601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE0_RX_BIT_MODE2_EO_PL = 0x800228270601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE0_RX_BIT_MODE2_E_PL = 0x8002C8270601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL = 0x800230270601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE0_RX_BIT_STAT1_EO_PL = 0x800268270601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL = 0x800270270601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL = 0x800278270601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL = 0x800008270601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL1_E_PL = 0x800080270601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL2_EO_PL = 0x800010270601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL2_E_PL = 0x800088270601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL3_EO_PL = 0x800018270601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL3_E_PL = 0x800090270601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL4_EO_PL = 0x800020270601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL4_E_PL = 0x800098270601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL = 0x800028270601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL5_E_PL = 0x8000A0270601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL6_EO_PL = 0x800030270601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL6_E_PL = 0x8000A8270601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL7_EO_PL = 0x800038270601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL7_E_PL = 0x8000B0270601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL8_EO_PL = 0x800040270601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL8_E_PL = 0x8000B8270601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL9_E_PL = 0x8000C0270601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x800000270601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE0_RX_FIR_ERROR_INJECT_PL = 0x800218270601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE0_RX_FIR_MASK_PL = 0x800210270601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE0_RX_FIR_PL = 0x800208270601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE0_RX_SPARE_MODE_PL = 0x800200270601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL = 0x800300250601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL = 0x800248250601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL2_E_PL = 0x800308250601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL = 0x800250250601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL3_E_PL = 0x800310250601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL = 0x800258250601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL5_EO_PL = 0x800260250601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL = 0x800240250601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL = 0x800220250601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE1_RX_BIT_MODE1_E_PL = 0x8002C0250601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE1_RX_BIT_MODE2_EO_PL = 0x800228250601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE1_RX_BIT_MODE2_E_PL = 0x8002C8250601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL = 0x800230250601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE1_RX_BIT_STAT1_EO_PL = 0x800268250601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL = 0x800270250601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL = 0x800278250601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL = 0x800008250601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL1_E_PL = 0x800080250601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL2_EO_PL = 0x800010250601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL2_E_PL = 0x800088250601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL3_EO_PL = 0x800018250601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL3_E_PL = 0x800090250601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL4_EO_PL = 0x800020250601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL4_E_PL = 0x800098250601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL = 0x800028250601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL5_E_PL = 0x8000A0250601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL6_EO_PL = 0x800030250601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL6_E_PL = 0x8000A8250601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL7_EO_PL = 0x800038250601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL7_E_PL = 0x8000B0250601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL8_EO_PL = 0x800040250601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL8_E_PL = 0x8000B8250601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL9_E_PL = 0x8000C0250601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x800000250601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE1_RX_FIR_ERROR_INJECT_PL = 0x800218250601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE1_RX_FIR_MASK_PL = 0x800210250601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE1_RX_FIR_PL = 0x800208250601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE1_RX_SPARE_MODE_PL = 0x800200250601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL = 0x800300260601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL = 0x800248260601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL2_E_PL = 0x800308260601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL = 0x800250260601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL3_E_PL = 0x800310260601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL = 0x800258260601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL5_EO_PL = 0x800260260601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL = 0x800240260601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL = 0x800220260601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE2_RX_BIT_MODE1_E_PL = 0x8002C0260601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE2_RX_BIT_MODE2_EO_PL = 0x800228260601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE2_RX_BIT_MODE2_E_PL = 0x8002C8260601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL = 0x800230260601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE2_RX_BIT_STAT1_EO_PL = 0x800268260601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL = 0x800270260601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL = 0x800278260601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL = 0x800008260601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL1_E_PL = 0x800080260601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL2_EO_PL = 0x800010260601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL2_E_PL = 0x800088260601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL3_EO_PL = 0x800018260601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL3_E_PL = 0x800090260601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL4_EO_PL = 0x800020260601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL4_E_PL = 0x800098260601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL = 0x800028260601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL5_E_PL = 0x8000A0260601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL6_EO_PL = 0x800030260601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL6_E_PL = 0x8000A8260601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL7_EO_PL = 0x800038260601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL7_E_PL = 0x8000B0260601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL8_EO_PL = 0x800040260601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL8_E_PL = 0x8000B8260601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL9_E_PL = 0x8000C0260601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x800000260601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE2_RX_FIR_ERROR_INJECT_PL = 0x800218260601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE2_RX_FIR_MASK_PL = 0x800210260601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE2_RX_FIR_PL = 0x800208260601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE2_RX_SPARE_MODE_PL = 0x800200260601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL = 0x800300240601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL = 0x800248240601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL2_E_PL = 0x800308240601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL = 0x800250240601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL3_E_PL = 0x800310240601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL = 0x800258240601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL5_EO_PL = 0x800260240601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL = 0x800240240601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL = 0x800220240601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE3_RX_BIT_MODE1_E_PL = 0x8002C0240601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE3_RX_BIT_MODE2_EO_PL = 0x800228240601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE3_RX_BIT_MODE2_E_PL = 0x8002C8240601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL = 0x800230240601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE3_RX_BIT_STAT1_EO_PL = 0x800268240601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL = 0x800270240601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL = 0x800278240601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL = 0x800008240601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL1_E_PL = 0x800080240601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL2_EO_PL = 0x800010240601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL2_E_PL = 0x800088240601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL3_EO_PL = 0x800018240601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL3_E_PL = 0x800090240601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL4_EO_PL = 0x800020240601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL4_E_PL = 0x800098240601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL = 0x800028240601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL5_E_PL = 0x8000A0240601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL6_EO_PL = 0x800030240601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL6_E_PL = 0x8000A8240601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL7_EO_PL = 0x800038240601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL7_E_PL = 0x8000B0240601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL8_EO_PL = 0x800040240601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL8_E_PL = 0x8000B8240601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL9_E_PL = 0x8000C0240601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x800000240601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE3_RX_FIR_ERROR_INJECT_PL = 0x800218240601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE3_RX_FIR_MASK_PL = 0x800210240601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE3_RX_FIR_PL = 0x800208240601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS1_SLICE3_RX_SPARE_MODE_PL = 0x800200240601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL = 0x800300280601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL = 0x800248280601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL2_E_PL = 0x800308280601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL = 0x800250280601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL3_E_PL = 0x800310280601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL = 0x800258280601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL5_EO_PL = 0x800260280601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL = 0x800240280601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL = 0x800220280601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE0_RX_BIT_MODE1_E_PL = 0x8002C0280601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE0_RX_BIT_MODE2_EO_PL = 0x800228280601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE0_RX_BIT_MODE2_E_PL = 0x8002C8280601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL = 0x800230280601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE0_RX_BIT_STAT1_EO_PL = 0x800268280601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL = 0x800270280601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL = 0x800278280601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL = 0x800008280601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL1_E_PL = 0x800080280601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL2_EO_PL = 0x800010280601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL2_E_PL = 0x800088280601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL3_EO_PL = 0x800018280601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL3_E_PL = 0x800090280601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL4_EO_PL = 0x800020280601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL4_E_PL = 0x800098280601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL = 0x800028280601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL5_E_PL = 0x8000A0280601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL6_EO_PL = 0x800030280601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL6_E_PL = 0x8000A8280601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL7_EO_PL = 0x800038280601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL7_E_PL = 0x8000B0280601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL8_EO_PL = 0x800040280601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL8_E_PL = 0x8000B8280601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL9_E_PL = 0x8000C0280601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x800000280601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE0_RX_FIR_ERROR_INJECT_PL = 0x800218280601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE0_RX_FIR_MASK_PL = 0x800210280601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE0_RX_FIR_PL = 0x800208280601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE0_RX_SPARE_MODE_PL = 0x800200280601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL = 0x8003002A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL = 0x8002482A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL2_E_PL = 0x8003082A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL = 0x8002502A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL3_E_PL = 0x8003102A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL = 0x8002582A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL5_EO_PL = 0x8002602A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL = 0x8002402A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL = 0x8002202A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE1_RX_BIT_MODE1_E_PL = 0x8002C02A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE1_RX_BIT_MODE2_EO_PL = 0x8002282A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE1_RX_BIT_MODE2_E_PL = 0x8002C82A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL = 0x8002302A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE1_RX_BIT_STAT1_EO_PL = 0x8002682A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL = 0x8002702A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL = 0x8002782A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL = 0x8000082A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL1_E_PL = 0x8000802A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL2_EO_PL = 0x8000102A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL2_E_PL = 0x8000882A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL3_EO_PL = 0x8000182A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL3_E_PL = 0x8000902A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL4_EO_PL = 0x8000202A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL4_E_PL = 0x8000982A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL = 0x8000282A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL5_E_PL = 0x8000A02A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL6_EO_PL = 0x8000302A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL6_E_PL = 0x8000A82A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL7_EO_PL = 0x8000382A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL7_E_PL = 0x8000B02A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL8_EO_PL = 0x8000402A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL8_E_PL = 0x8000B82A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL9_E_PL = 0x8000C02A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x8000002A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE1_RX_FIR_ERROR_INJECT_PL = 0x8002182A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE1_RX_FIR_MASK_PL = 0x8002102A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE1_RX_FIR_PL = 0x8002082A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE1_RX_SPARE_MODE_PL = 0x8002002A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL = 0x800300290601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL = 0x800248290601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL2_E_PL = 0x800308290601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL = 0x800250290601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL3_E_PL = 0x800310290601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL = 0x800258290601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL5_EO_PL = 0x800260290601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL = 0x800240290601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL = 0x800220290601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE2_RX_BIT_MODE1_E_PL = 0x8002C0290601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE2_RX_BIT_MODE2_EO_PL = 0x800228290601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE2_RX_BIT_MODE2_E_PL = 0x8002C8290601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL = 0x800230290601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE2_RX_BIT_STAT1_EO_PL = 0x800268290601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL = 0x800270290601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL = 0x800278290601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL = 0x800008290601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL1_E_PL = 0x800080290601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL2_EO_PL = 0x800010290601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL2_E_PL = 0x800088290601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL3_EO_PL = 0x800018290601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL3_E_PL = 0x800090290601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL4_EO_PL = 0x800020290601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL4_E_PL = 0x800098290601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL = 0x800028290601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL5_E_PL = 0x8000A0290601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL6_EO_PL = 0x800030290601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL6_E_PL = 0x8000A8290601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL7_EO_PL = 0x800038290601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL7_E_PL = 0x8000B0290601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL8_EO_PL = 0x800040290601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL8_E_PL = 0x8000B8290601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL9_E_PL = 0x8000C0290601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x800000290601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE2_RX_FIR_ERROR_INJECT_PL = 0x800218290601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE2_RX_FIR_MASK_PL = 0x800210290601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE2_RX_FIR_PL = 0x800208290601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE2_RX_SPARE_MODE_PL = 0x800200290601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL = 0x800300310601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL = 0x800248310601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL2_E_PL = 0x800308310601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL = 0x800250310601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL3_E_PL = 0x800310310601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL = 0x800258310601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL5_EO_PL = 0x800260310601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL = 0x800240310601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL = 0x800220310601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE3_RX_BIT_MODE1_E_PL = 0x8002C0310601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE3_RX_BIT_MODE2_EO_PL = 0x800228310601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE3_RX_BIT_MODE2_E_PL = 0x8002C8310601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL = 0x800230310601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE3_RX_BIT_STAT1_EO_PL = 0x800268310601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL = 0x800270310601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL = 0x800278310601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL = 0x800008310601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL1_E_PL = 0x800080310601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL2_EO_PL = 0x800010310601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL2_E_PL = 0x800088310601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL3_EO_PL = 0x800018310601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL3_E_PL = 0x800090310601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL4_EO_PL = 0x800020310601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL4_E_PL = 0x800098310601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL = 0x800028310601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL5_E_PL = 0x8000A0310601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL6_EO_PL = 0x800030310601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL6_E_PL = 0x8000A8310601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL7_EO_PL = 0x800038310601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL7_E_PL = 0x8000B0310601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL8_EO_PL = 0x800040310601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL8_E_PL = 0x8000B8310601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL9_E_PL = 0x8000C0310601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x800000310601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE3_RX_FIR_ERROR_INJECT_PL = 0x800218310601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE3_RX_FIR_MASK_PL = 0x800210310601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE3_RX_FIR_PL = 0x800208310601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS2_SLICE3_RX_SPARE_MODE_PL = 0x800200310601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL = 0x8003002E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL = 0x8002482E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL2_E_PL = 0x8003082E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL = 0x8002502E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL3_E_PL = 0x8003102E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL = 0x8002582E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL5_EO_PL = 0x8002602E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL = 0x8002402E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL = 0x8002202E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE0_RX_BIT_MODE1_E_PL = 0x8002C02E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE0_RX_BIT_MODE2_EO_PL = 0x8002282E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE0_RX_BIT_MODE2_E_PL = 0x8002C82E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL = 0x8002302E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE0_RX_BIT_STAT1_EO_PL = 0x8002682E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL = 0x8002702E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL = 0x8002782E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL = 0x8000082E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL1_E_PL = 0x8000802E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL2_EO_PL = 0x8000102E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL2_E_PL = 0x8000882E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL3_EO_PL = 0x8000182E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL3_E_PL = 0x8000902E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL4_EO_PL = 0x8000202E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL4_E_PL = 0x8000982E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL = 0x8000282E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL5_E_PL = 0x8000A02E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL6_EO_PL = 0x8000302E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL6_E_PL = 0x8000A82E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL7_EO_PL = 0x8000382E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL7_E_PL = 0x8000B02E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL8_EO_PL = 0x8000402E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL8_E_PL = 0x8000B82E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL9_E_PL = 0x8000C02E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x8000002E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE0_RX_FIR_ERROR_INJECT_PL = 0x8002182E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE0_RX_FIR_MASK_PL = 0x8002102E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE0_RX_FIR_PL = 0x8002082E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE0_RX_SPARE_MODE_PL = 0x8002002E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL = 0x8003002C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL = 0x8002482C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL2_E_PL = 0x8003082C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL = 0x8002502C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL3_E_PL = 0x8003102C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL = 0x8002582C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL5_EO_PL = 0x8002602C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL = 0x8002402C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL = 0x8002202C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE1_RX_BIT_MODE1_E_PL = 0x8002C02C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE1_RX_BIT_MODE2_EO_PL = 0x8002282C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE1_RX_BIT_MODE2_E_PL = 0x8002C82C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL = 0x8002302C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE1_RX_BIT_STAT1_EO_PL = 0x8002682C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL = 0x8002702C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL = 0x8002782C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL = 0x8000082C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL1_E_PL = 0x8000802C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL2_EO_PL = 0x8000102C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL2_E_PL = 0x8000882C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL3_EO_PL = 0x8000182C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL3_E_PL = 0x8000902C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL4_EO_PL = 0x8000202C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL4_E_PL = 0x8000982C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL = 0x8000282C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL5_E_PL = 0x8000A02C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL6_EO_PL = 0x8000302C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL6_E_PL = 0x8000A82C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL7_EO_PL = 0x8000382C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL7_E_PL = 0x8000B02C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL8_EO_PL = 0x8000402C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL8_E_PL = 0x8000B82C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL9_E_PL = 0x8000C02C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x8000002C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE1_RX_FIR_ERROR_INJECT_PL = 0x8002182C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE1_RX_FIR_MASK_PL = 0x8002102C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE1_RX_FIR_PL = 0x8002082C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE1_RX_SPARE_MODE_PL = 0x8002002C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL = 0x8003002D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL = 0x8002482D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL2_E_PL = 0x8003082D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL = 0x8002502D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL3_E_PL = 0x8003102D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL = 0x8002582D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL5_EO_PL = 0x8002602D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL = 0x8002402D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL = 0x8002202D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE2_RX_BIT_MODE1_E_PL = 0x8002C02D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE2_RX_BIT_MODE2_EO_PL = 0x8002282D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE2_RX_BIT_MODE2_E_PL = 0x8002C82D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL = 0x8002302D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE2_RX_BIT_STAT1_EO_PL = 0x8002682D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL = 0x8002702D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL = 0x8002782D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL = 0x8000082D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL1_E_PL = 0x8000802D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL2_EO_PL = 0x8000102D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL2_E_PL = 0x8000882D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL3_EO_PL = 0x8000182D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL3_E_PL = 0x8000902D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL4_EO_PL = 0x8000202D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL4_E_PL = 0x8000982D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL = 0x8000282D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL5_E_PL = 0x8000A02D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL6_EO_PL = 0x8000302D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL6_E_PL = 0x8000A82D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL7_EO_PL = 0x8000382D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL7_E_PL = 0x8000B02D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL8_EO_PL = 0x8000402D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL8_E_PL = 0x8000B82D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL9_E_PL = 0x8000C02D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x8000002D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE2_RX_FIR_ERROR_INJECT_PL = 0x8002182D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE2_RX_FIR_MASK_PL = 0x8002102D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE2_RX_FIR_PL = 0x8002082D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE2_RX_SPARE_MODE_PL = 0x8002002D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL = 0x8003002B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL = 0x8002482B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL2_E_PL = 0x8003082B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL = 0x8002502B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL3_E_PL = 0x8003102B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL = 0x8002582B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL5_EO_PL = 0x8002602B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL = 0x8002402B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL = 0x8002202B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE3_RX_BIT_MODE1_E_PL = 0x8002C02B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE3_RX_BIT_MODE2_EO_PL = 0x8002282B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE3_RX_BIT_MODE2_E_PL = 0x8002C82B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL = 0x8002302B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE3_RX_BIT_STAT1_EO_PL = 0x8002682B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL = 0x8002702B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL = 0x8002782B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL = 0x8000082B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL1_E_PL = 0x8000802B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL2_EO_PL = 0x8000102B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL2_E_PL = 0x8000882B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL3_EO_PL = 0x8000182B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL3_E_PL = 0x8000902B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL4_EO_PL = 0x8000202B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL4_E_PL = 0x8000982B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL = 0x8000282B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL5_E_PL = 0x8000A02B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL6_EO_PL = 0x8000302B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL6_E_PL = 0x8000A82B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL7_EO_PL = 0x8000382B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL7_E_PL = 0x8000B02B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL8_EO_PL = 0x8000402B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL8_E_PL = 0x8000B82B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL9_E_PL = 0x8000C02B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x8000002B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE3_RX_FIR_ERROR_INJECT_PL = 0x8002182B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE3_RX_FIR_MASK_PL = 0x8002102B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE3_RX_FIR_PL = 0x8002082B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE3_RX_SPARE_MODE_PL = 0x8002002B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL = 0x8003002F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL2_EO_PL = 0x8002482F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL2_E_PL = 0x8003082F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL3_EO_PL = 0x8002502F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL3_E_PL = 0x8003102F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL4_EO_PL = 0x8002582F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL5_EO_PL = 0x8002602F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL = 0x8002402F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE4_RX_BIT_MODE1_EO_PL = 0x8002202F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE4_RX_BIT_MODE1_E_PL = 0x8002C02F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE4_RX_BIT_MODE2_EO_PL = 0x8002282F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE4_RX_BIT_MODE2_E_PL = 0x8002C82F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE4_RX_BIT_MODE3_EO_PL = 0x8002302F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE4_RX_BIT_STAT1_EO_PL = 0x8002682F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE4_RX_BIT_STAT2_EO_PL = 0x8002702F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE4_RX_BIT_STAT3_EO_PL = 0x8002782F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL1_EO_PL = 0x8000082F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL1_E_PL = 0x8000802F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL2_EO_PL = 0x8000102F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL2_E_PL = 0x8000882F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL3_EO_PL = 0x8000182F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL3_E_PL = 0x8000902F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL4_EO_PL = 0x8000202F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL4_E_PL = 0x8000982F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL5_EO_PL = 0x8000282F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL5_E_PL = 0x8000A02F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL6_EO_PL = 0x8000302F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL6_E_PL = 0x8000A82F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL7_EO_PL = 0x8000382F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL7_E_PL = 0x8000B02F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL8_EO_PL = 0x8000402F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL8_E_PL = 0x8000B82F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL9_E_PL = 0x8000C02F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE4_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x8000002F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE4_RX_FIR_ERROR_INJECT_PL = 0x8002182F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE4_RX_FIR_MASK_PL = 0x8002102F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE4_RX_FIR_PL = 0x8002082F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE4_RX_SPARE_MODE_PL = 0x8002002F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL = 0x800300300601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL2_EO_PL = 0x800248300601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL2_E_PL = 0x800308300601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL3_EO_PL = 0x800250300601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL3_E_PL = 0x800310300601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL4_EO_PL = 0x800258300601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL5_EO_PL = 0x800260300601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL = 0x800240300601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE5_RX_BIT_MODE1_EO_PL = 0x800220300601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE5_RX_BIT_MODE1_E_PL = 0x8002C0300601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE5_RX_BIT_MODE2_EO_PL = 0x800228300601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE5_RX_BIT_MODE2_E_PL = 0x8002C8300601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE5_RX_BIT_MODE3_EO_PL = 0x800230300601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE5_RX_BIT_STAT1_EO_PL = 0x800268300601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE5_RX_BIT_STAT2_EO_PL = 0x800270300601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE5_RX_BIT_STAT3_EO_PL = 0x800278300601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL1_EO_PL = 0x800008300601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL1_E_PL = 0x800080300601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL2_EO_PL = 0x800010300601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL2_E_PL = 0x800088300601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL3_EO_PL = 0x800018300601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL3_E_PL = 0x800090300601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL4_EO_PL = 0x800020300601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL4_E_PL = 0x800098300601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL5_EO_PL = 0x800028300601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL5_E_PL = 0x8000A0300601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL6_EO_PL = 0x800030300601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL6_E_PL = 0x8000A8300601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL7_EO_PL = 0x800038300601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL7_E_PL = 0x8000B0300601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL8_EO_PL = 0x800040300601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL8_E_PL = 0x8000B8300601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL9_E_PL = 0x8000C0300601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE5_RX_DATA_DAC_SPARE_MODE_PL =
+ 0x800000300601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE5_RX_FIR_ERROR_INJECT_PL = 0x800218300601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE5_RX_FIR_MASK_PL = 0x800210300601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE5_RX_FIR_PL = 0x800208300601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RXPACKS3_SLICE5_RX_SPARE_MODE_PL = 0x800200300601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_CTL_CNTL10_EO_PG = 0x800920200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_CTL_CNTL11_EO_PG = 0x800928200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_CTL_CNTL12_EO_PG = 0x800930200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_CTL_CNTL13_EO_PG = 0x800938200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_CTL_CNTL14_EO_PG = 0x800940200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_CTL_CNTL15_EO_PG = 0x800948200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_CTL_CNTL1_EO_PG = 0x8008D8200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_CTL_CNTL1_E_PG = 0x8009F0200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_CTL_CNTL2_EO_PG = 0x8008E0200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_CTL_CNTL3_EO_PG = 0x8008E8200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_CTL_CNTL4_EO_PG = 0x8008F0200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_CTL_CNTL4_E_PG = 0x8009F8200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_CTL_CNTL5_EO_PG = 0x8008F8200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_CTL_CNTL6_EO_PG = 0x800900200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_CTL_CNTL8_EO_PG = 0x800910200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_CTL_CNTL9_EO_PG = 0x800918200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_CTL_CNTLX11_E_PG = 0x800A30200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_CTL_CNTLX7_EO_PG = 0x800908200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_CTL_MODE10_EO_PG = 0x800858200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_CTL_MODE10_E_PG = 0x8009D8200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_CTL_MODE11_EO_PG = 0x800860200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_CTL_MODE11_E_PG = 0x8009E0200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_CTL_MODE12_EO_PG = 0x800868200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_CTL_MODE12_E_PG = 0x8009E8200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_CTL_MODE13_EO_PG = 0x800870200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_CTL_MODE14_EO_PG = 0x800878200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_CTL_MODE15_EO_PG = 0x800880200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_CTL_MODE16_EO_PG = 0x800888200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_CTL_MODE17_EO_PG = 0x800890200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_CTL_MODE18_EO_PG = 0x800898200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_CTL_MODE19_EO_PG = 0x8008A0200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_CTL_MODE1_EO_PG = 0x800810200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_CTL_MODE1_E_PG = 0x800990200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_CTL_MODE20_EO_PG = 0x8008A8200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_CTL_MODE21_EO_PG = 0x8008B0200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_CTL_MODE22_EO_PG = 0x8008B8200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_CTL_MODE23_EO_PG = 0x8008C0200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_CTL_MODE24_EO_PG = 0x8008C8200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_CTL_MODE26_EO_PG = 0x800968200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_CTL_MODE27_EO_PG = 0x800970200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_CTL_MODE28_EO_PG = 0x800978200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_CTL_MODE29_EO_PG = 0x8008D0200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_CTL_MODE2_EO_PG = 0x800818200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_CTL_MODE2_E_PG = 0x800998200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_CTL_MODE3_EO_PG = 0x800820200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_CTL_MODE3_E_PG = 0x8009A0200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_CTL_MODE4_EO_PG = 0x800828200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_CTL_MODE4_E_PG = 0x8009A8200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_CTL_MODE5_EO_PG = 0x800830200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_CTL_MODE5_E_PG = 0x8009B0200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_CTL_MODE6_EO_PG = 0x800838200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_CTL_MODE6_E_PG = 0x8009B8200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_CTL_MODE7_EO_PG = 0x800840200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_CTL_MODE7_E_PG = 0x8009C0200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_CTL_MODE8_EO_PG = 0x800848200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_CTL_MODE8_E_PG = 0x8009C8200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_CTL_MODE9_EO_PG = 0x800850200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_CTL_MODE9_E_PG = 0x8009D0200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_CTL_STAT1_EO_PG = 0x800950200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_CTL_STAT1_E_PG = 0x800A38200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_CTL_STAT2_EO_PG = 0x800958200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_CTL_STAT2_E_PG = 0x800A40200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_CTL_STAT3_EO_PG = 0x800960200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_CTL_STAT4_E_PG = 0x800A50200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_CTL_STAT5_E_PG = 0x800A58200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_CTL_STAT6_E_PG = 0x800A60200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_CTL_STATX8_E_PG = 0x800A68200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_DATASM_CNTL1_E_PG = 0x800BE8200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_DATASM_CNTL2_EO_PG = 0x800B78200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_DATASM_CNTLX1_EO_PG = 0x800B88200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_DATASM_SPARE_MODE_PG = 0x800B80200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_DATASM_STAT10_EO_PG = 0x800BD8200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_DATASM_STAT11_EO_PG = 0x800BE0200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_DATASM_STAT12_EO_PG = 0x800BF0200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_DATASM_STAT13_E_PG = 0x800BF8200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_DATASM_STAT1_EO_PG = 0x800B90200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_DATASM_STAT2_EO_PG = 0x800B98200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_DATASM_STAT3_EO_PG = 0x800BA0200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_DATASM_STAT4_EO_PG = 0x800BA8200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_DATASM_STAT5_EO_PG = 0x800BB0200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_DATASM_STAT6_EO_PG = 0x800BB8200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_DATASM_STAT7_EO_PG = 0x800BC0200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_DATASM_STAT8_EO_PG = 0x800BC8200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_DATASM_STAT9_EO_PG = 0x800BD0200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_FIR1_ERROR_INJECT_PG = 0x800A98200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_FIR1_MASK_PG = 0x800A90200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_FIR1_PG = 0x800A88200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_FIR2_ERROR_INJECT_PG = 0x800B10200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_FIR2_MASK_PG = 0x800B08200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_FIR2_PG = 0x800B00200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_FIR_TRAINING_MASK_PG = 0x800AA8200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_FIR_TRAINING_PG = 0x800AA0200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_GLBSM_CNTL2_EO_PG = 0x800AE0200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_GLBSM_CNTL3_EO_PG = 0x800AE8200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_GLBSM_CNTL4_EO_PG = 0x800AF0200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_GLBSM_CNTLX1_EO_PG = 0x800AB0200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_GLBSM_MODE1_EO_PG = 0x800AF8200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_GLBSM_SPARE_MODE_PG = 0x800A80200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_GLBSM_STAT10_E_PG = 0x800B60200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_GLBSM_STAT11_E_PG = 0x800B68200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_GLBSM_STAT1_EO_PG = 0x800AB8200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_GLBSM_STAT1_E_PG = 0x800B18200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_GLBSM_STAT2_EO_PG = 0x800AC0200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_GLBSM_STAT2_E_PG = 0x800B20200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_GLBSM_STAT3_EO_PG = 0x800AC8200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_GLBSM_STAT3_E_PG = 0x800B28200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_GLBSM_STAT4_EO_PG = 0x800AD0200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_GLBSM_STAT4_E_PG = 0x800B30200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_GLBSM_STAT5_EO_PG = 0x800AD8200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_GLBSM_STAT7_E_PG = 0x800B48200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_GLBSM_STAT8_E_PG = 0x800B50200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_GLBSM_STAT9_E_PG = 0x800B58200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_ID1_PG = 0x800808200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_ID2_PG = 0x800980200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_RX_SPARE_MODE_PG = 0x800800200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE0_RX_DATA_WORK_SPARE_MODE_PL = 0x800380210601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE0_RX_WORK_STAT1_EO_PL = 0x800388210601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE0_RX_WORK_STAT2_EO_PL = 0x800390210601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE0_RX_WORK_STAT3_EO_PL = 0x800398210601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE10_RX_DATA_WORK_SPARE_MODE_PL = 0x800380290601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE10_RX_WORK_STAT1_EO_PL = 0x800388290601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE10_RX_WORK_STAT2_EO_PL = 0x800390290601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE10_RX_WORK_STAT3_EO_PL = 0x800398290601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE11_RX_DATA_WORK_SPARE_MODE_PL = 0x800380310601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE11_RX_WORK_STAT1_EO_PL = 0x800388310601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE11_RX_WORK_STAT2_EO_PL = 0x800390310601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE11_RX_WORK_STAT3_EO_PL = 0x800398310601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE12_RX_DATA_WORK_SPARE_MODE_PL = 0x8003802E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE12_RX_WORK_STAT1_EO_PL = 0x8003882E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE12_RX_WORK_STAT2_EO_PL = 0x8003902E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE12_RX_WORK_STAT3_EO_PL = 0x8003982E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE13_RX_DATA_WORK_SPARE_MODE_PL = 0x8003802C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE13_RX_WORK_STAT1_EO_PL = 0x8003882C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE13_RX_WORK_STAT2_EO_PL = 0x8003902C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE13_RX_WORK_STAT3_EO_PL = 0x8003982C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE14_RX_DATA_WORK_SPARE_MODE_PL = 0x8003802D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE14_RX_WORK_STAT1_EO_PL = 0x8003882D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE14_RX_WORK_STAT2_EO_PL = 0x8003902D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE14_RX_WORK_STAT3_EO_PL = 0x8003982D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE15_RX_DATA_WORK_SPARE_MODE_PL = 0x8003802B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE15_RX_WORK_STAT1_EO_PL = 0x8003882B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE15_RX_WORK_STAT2_EO_PL = 0x8003902B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE15_RX_WORK_STAT3_EO_PL = 0x8003982B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE16_RX_DATA_WORK_SPARE_MODE_PL = 0x8003802F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE16_RX_WORK_STAT1_EO_PL = 0x8003882F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE16_RX_WORK_STAT2_EO_PL = 0x8003902F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE16_RX_WORK_STAT3_EO_PL = 0x8003982F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE17_RX_DATA_WORK_SPARE_MODE_PL = 0x800380300601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE17_RX_WORK_STAT1_EO_PL = 0x800388300601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE17_RX_WORK_STAT2_EO_PL = 0x800390300601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE17_RX_WORK_STAT3_EO_PL = 0x800398300601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE18_RX_DATA_WORK_SPARE_MODE_PL = 0x800380320601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE18_RX_WORK_STAT1_EO_PL = 0x800388320601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE18_RX_WORK_STAT2_EO_PL = 0x800390320601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE18_RX_WORK_STAT3_EO_PL = 0x800398320601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE19_RX_DATA_WORK_SPARE_MODE_PL = 0x800380330601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE19_RX_WORK_STAT1_EO_PL = 0x800388330601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE19_RX_WORK_STAT2_EO_PL = 0x800390330601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE19_RX_WORK_STAT3_EO_PL = 0x800398330601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE1_RX_DATA_WORK_SPARE_MODE_PL = 0x800380230601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE1_RX_WORK_STAT1_EO_PL = 0x800388230601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE1_RX_WORK_STAT2_EO_PL = 0x800390230601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE1_RX_WORK_STAT3_EO_PL = 0x800398230601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE20_RX_DATA_WORK_SPARE_MODE_PL = 0x800380340601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE20_RX_WORK_STAT1_EO_PL = 0x800388340601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE20_RX_WORK_STAT2_EO_PL = 0x800390340601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE20_RX_WORK_STAT3_EO_PL = 0x800398340601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE21_RX_DATA_WORK_SPARE_MODE_PL = 0x800380350601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE21_RX_WORK_STAT1_EO_PL = 0x800388350601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE21_RX_WORK_STAT2_EO_PL = 0x800390350601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE21_RX_WORK_STAT3_EO_PL = 0x800398350601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE22_RX_DATA_WORK_SPARE_MODE_PL = 0x800380360601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE22_RX_WORK_STAT1_EO_PL = 0x800388360601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE22_RX_WORK_STAT2_EO_PL = 0x800390360601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE22_RX_WORK_STAT3_EO_PL = 0x800398360601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE23_RX_DATA_WORK_SPARE_MODE_PL = 0x800380370601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE23_RX_WORK_STAT1_EO_PL = 0x800388370601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE23_RX_WORK_STAT2_EO_PL = 0x800390370601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE23_RX_WORK_STAT3_EO_PL = 0x800398370601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE2_RX_DATA_WORK_SPARE_MODE_PL = 0x800380200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE2_RX_WORK_STAT1_EO_PL = 0x800388200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE2_RX_WORK_STAT2_EO_PL = 0x800390200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE2_RX_WORK_STAT3_EO_PL = 0x800398200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE3_RX_DATA_WORK_SPARE_MODE_PL = 0x800380220601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE3_RX_WORK_STAT1_EO_PL = 0x800388220601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE3_RX_WORK_STAT2_EO_PL = 0x800390220601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE3_RX_WORK_STAT3_EO_PL = 0x800398220601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE4_RX_DATA_WORK_SPARE_MODE_PL = 0x800380270601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE4_RX_WORK_STAT1_EO_PL = 0x800388270601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE4_RX_WORK_STAT2_EO_PL = 0x800390270601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE4_RX_WORK_STAT3_EO_PL = 0x800398270601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE5_RX_DATA_WORK_SPARE_MODE_PL = 0x800380250601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE5_RX_WORK_STAT1_EO_PL = 0x800388250601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE5_RX_WORK_STAT2_EO_PL = 0x800390250601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE5_RX_WORK_STAT3_EO_PL = 0x800398250601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE6_RX_DATA_WORK_SPARE_MODE_PL = 0x800380260601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE6_RX_WORK_STAT1_EO_PL = 0x800388260601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE6_RX_WORK_STAT2_EO_PL = 0x800390260601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE6_RX_WORK_STAT3_EO_PL = 0x800398260601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE7_RX_DATA_WORK_SPARE_MODE_PL = 0x800380240601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE7_RX_WORK_STAT1_EO_PL = 0x800388240601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE7_RX_WORK_STAT2_EO_PL = 0x800390240601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE7_RX_WORK_STAT3_EO_PL = 0x800398240601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE8_RX_DATA_WORK_SPARE_MODE_PL = 0x800380280601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE8_RX_WORK_STAT1_EO_PL = 0x800388280601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE8_RX_WORK_STAT2_EO_PL = 0x800390280601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE8_RX_WORK_STAT3_EO_PL = 0x800398280601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE9_RX_DATA_WORK_SPARE_MODE_PL = 0x8003802A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE9_RX_WORK_STAT1_EO_PL = 0x8003882A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE9_RX_WORK_STAT2_EO_PL = 0x8003902A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX1_SLICE9_RX_WORK_STAT3_EO_PL = 0x8003982A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX_FIR_ERROR_INJECT_PB = 0x800F98000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX_FIR_MASK_PB = 0x800F90000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX_FIR_PB = 0x800F88000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_RX_FIR_RESET_PB = 0x800F80000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_SCOM_MODE_PB = 0x06011420ull;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_SPARE_MODE_PB = 0x800F34000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS0_SLICE0_TX_BIT_MODE1_E_PL = 0x80043C000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS0_SLICE0_TX_BIT_MODE2_E_PL = 0x800444000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS0_SLICE0_TX_CNTL1G_PL = 0x800414000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS0_SLICE0_TX_CNTL3_EO_PL = 0x800454000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS0_SLICE0_TX_FIR_ERROR_INJECT_PL = 0x800434000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS0_SLICE0_TX_FIR_MASK_PL = 0x80042C000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS0_SLICE0_TX_FIR_PL = 0x800424000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS0_SLICE0_TX_MODE1_PL = 0x800404000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS0_SLICE0_TX_MODE2_PL = 0x80040C000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS0_SLICE0_TX_STAT1_PL = 0x80041C000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS0_SLICE1_TX_BIT_MODE1_E_PL = 0x80043C010601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS0_SLICE1_TX_BIT_MODE2_E_PL = 0x800444010601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS0_SLICE1_TX_CNTL1G_PL = 0x800414010601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS0_SLICE1_TX_CNTL3_EO_PL = 0x800454010601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS0_SLICE1_TX_FIR_ERROR_INJECT_PL = 0x800434010601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS0_SLICE1_TX_FIR_MASK_PL = 0x80042C010601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS0_SLICE1_TX_FIR_PL = 0x800424010601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS0_SLICE1_TX_MODE1_PL = 0x800404010601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS0_SLICE1_TX_MODE2_PL = 0x80040C010601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS0_SLICE1_TX_STAT1_PL = 0x80041C010601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS0_SLICE2_TX_BIT_MODE1_E_PL = 0x80043C020601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS0_SLICE2_TX_BIT_MODE2_E_PL = 0x800444020601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS0_SLICE2_TX_CNTL1G_PL = 0x800414020601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS0_SLICE2_TX_CNTL3_EO_PL = 0x800454020601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS0_SLICE2_TX_FIR_ERROR_INJECT_PL = 0x800434020601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS0_SLICE2_TX_FIR_MASK_PL = 0x80042C020601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS0_SLICE2_TX_FIR_PL = 0x800424020601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS0_SLICE2_TX_MODE1_PL = 0x800404020601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS0_SLICE2_TX_MODE2_PL = 0x80040C020601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS0_SLICE2_TX_STAT1_PL = 0x80041C020601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS0_SLICE3_TX_BIT_MODE1_E_PL = 0x80043C030601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS0_SLICE3_TX_BIT_MODE2_E_PL = 0x800444030601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS0_SLICE3_TX_CNTL1G_PL = 0x800414030601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS0_SLICE3_TX_CNTL3_EO_PL = 0x800454030601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS0_SLICE3_TX_FIR_ERROR_INJECT_PL = 0x800434030601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS0_SLICE3_TX_FIR_MASK_PL = 0x80042C030601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS0_SLICE3_TX_FIR_PL = 0x800424030601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS0_SLICE3_TX_MODE1_PL = 0x800404030601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS0_SLICE3_TX_MODE2_PL = 0x80040C030601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS0_SLICE3_TX_STAT1_PL = 0x80041C030601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS1_SLICE0_TX_BIT_MODE1_E_PL = 0x80043C040601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS1_SLICE0_TX_BIT_MODE2_E_PL = 0x800444040601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS1_SLICE0_TX_CNTL1G_PL = 0x800414040601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS1_SLICE0_TX_CNTL3_EO_PL = 0x800454040601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS1_SLICE0_TX_FIR_ERROR_INJECT_PL = 0x800434040601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS1_SLICE0_TX_FIR_MASK_PL = 0x80042C040601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS1_SLICE0_TX_FIR_PL = 0x800424040601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS1_SLICE0_TX_MODE1_PL = 0x800404040601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS1_SLICE0_TX_MODE2_PL = 0x80040C040601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS1_SLICE0_TX_STAT1_PL = 0x80041C040601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS1_SLICE1_TX_BIT_MODE1_E_PL = 0x80043C050601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS1_SLICE1_TX_BIT_MODE2_E_PL = 0x800444050601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS1_SLICE1_TX_CNTL1G_PL = 0x800414050601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS1_SLICE1_TX_CNTL3_EO_PL = 0x800454050601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS1_SLICE1_TX_FIR_ERROR_INJECT_PL = 0x800434050601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS1_SLICE1_TX_FIR_MASK_PL = 0x80042C050601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS1_SLICE1_TX_FIR_PL = 0x800424050601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS1_SLICE1_TX_MODE1_PL = 0x800404050601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS1_SLICE1_TX_MODE2_PL = 0x80040C050601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS1_SLICE1_TX_STAT1_PL = 0x80041C050601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS1_SLICE2_TX_BIT_MODE1_E_PL = 0x80043C060601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS1_SLICE2_TX_BIT_MODE2_E_PL = 0x800444060601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS1_SLICE2_TX_CNTL1G_PL = 0x800414060601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS1_SLICE2_TX_CNTL3_EO_PL = 0x800454060601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS1_SLICE2_TX_FIR_ERROR_INJECT_PL = 0x800434060601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS1_SLICE2_TX_FIR_MASK_PL = 0x80042C060601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS1_SLICE2_TX_FIR_PL = 0x800424060601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS1_SLICE2_TX_MODE1_PL = 0x800404060601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS1_SLICE2_TX_MODE2_PL = 0x80040C060601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS1_SLICE2_TX_STAT1_PL = 0x80041C060601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS1_SLICE3_TX_BIT_MODE1_E_PL = 0x80043C070601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS1_SLICE3_TX_BIT_MODE2_E_PL = 0x800444070601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS1_SLICE3_TX_CNTL1G_PL = 0x800414070601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS1_SLICE3_TX_CNTL3_EO_PL = 0x800454070601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS1_SLICE3_TX_FIR_ERROR_INJECT_PL = 0x800434070601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS1_SLICE3_TX_FIR_MASK_PL = 0x80042C070601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS1_SLICE3_TX_FIR_PL = 0x800424070601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS1_SLICE3_TX_MODE1_PL = 0x800404070601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS1_SLICE3_TX_MODE2_PL = 0x80040C070601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS1_SLICE3_TX_STAT1_PL = 0x80041C070601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS2_SLICE0_TX_BIT_MODE1_E_PL = 0x80043C080601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS2_SLICE0_TX_BIT_MODE2_E_PL = 0x800444080601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS2_SLICE0_TX_CNTL1G_PL = 0x800414080601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS2_SLICE0_TX_CNTL3_EO_PL = 0x800454080601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS2_SLICE0_TX_FIR_ERROR_INJECT_PL = 0x800434080601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS2_SLICE0_TX_FIR_MASK_PL = 0x80042C080601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS2_SLICE0_TX_FIR_PL = 0x800424080601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS2_SLICE0_TX_MODE1_PL = 0x800404080601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS2_SLICE0_TX_MODE2_PL = 0x80040C080601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS2_SLICE0_TX_STAT1_PL = 0x80041C080601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS2_SLICE1_TX_BIT_MODE1_E_PL = 0x80043C090601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS2_SLICE1_TX_BIT_MODE2_E_PL = 0x800444090601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS2_SLICE1_TX_CNTL1G_PL = 0x800414090601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS2_SLICE1_TX_CNTL3_EO_PL = 0x800454090601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS2_SLICE1_TX_FIR_ERROR_INJECT_PL = 0x800434090601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS2_SLICE1_TX_FIR_MASK_PL = 0x80042C090601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS2_SLICE1_TX_FIR_PL = 0x800424090601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS2_SLICE1_TX_MODE1_PL = 0x800404090601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS2_SLICE1_TX_MODE2_PL = 0x80040C090601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS2_SLICE1_TX_STAT1_PL = 0x80041C090601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS2_SLICE2_TX_BIT_MODE1_E_PL = 0x80043C0A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS2_SLICE2_TX_BIT_MODE2_E_PL = 0x8004440A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS2_SLICE2_TX_CNTL1G_PL = 0x8004140A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS2_SLICE2_TX_CNTL3_EO_PL = 0x8004540A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS2_SLICE2_TX_FIR_ERROR_INJECT_PL = 0x8004340A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS2_SLICE2_TX_FIR_MASK_PL = 0x80042C0A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS2_SLICE2_TX_FIR_PL = 0x8004240A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS2_SLICE2_TX_MODE1_PL = 0x8004040A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS2_SLICE2_TX_MODE2_PL = 0x80040C0A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS2_SLICE2_TX_STAT1_PL = 0x80041C0A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS2_SLICE3_TX_BIT_MODE1_E_PL = 0x80043C0B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS2_SLICE3_TX_BIT_MODE2_E_PL = 0x8004440B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS2_SLICE3_TX_CNTL1G_PL = 0x8004140B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS2_SLICE3_TX_CNTL3_EO_PL = 0x8004540B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS2_SLICE3_TX_FIR_ERROR_INJECT_PL = 0x8004340B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS2_SLICE3_TX_FIR_MASK_PL = 0x80042C0B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS2_SLICE3_TX_FIR_PL = 0x8004240B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS2_SLICE3_TX_MODE1_PL = 0x8004040B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS2_SLICE3_TX_MODE2_PL = 0x80040C0B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS2_SLICE3_TX_STAT1_PL = 0x80041C0B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS3_SLICE0_TX_BIT_MODE1_E_PL = 0x80043C0C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS3_SLICE0_TX_BIT_MODE2_E_PL = 0x8004440C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS3_SLICE0_TX_CNTL1G_PL = 0x8004140C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS3_SLICE0_TX_CNTL3_EO_PL = 0x8004540C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS3_SLICE0_TX_FIR_ERROR_INJECT_PL = 0x8004340C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS3_SLICE0_TX_FIR_MASK_PL = 0x80042C0C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS3_SLICE0_TX_FIR_PL = 0x8004240C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS3_SLICE0_TX_MODE1_PL = 0x8004040C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS3_SLICE0_TX_MODE2_PL = 0x80040C0C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS3_SLICE0_TX_STAT1_PL = 0x80041C0C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS3_SLICE1_TX_BIT_MODE1_E_PL = 0x80043C0D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS3_SLICE1_TX_BIT_MODE2_E_PL = 0x8004440D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS3_SLICE1_TX_CNTL1G_PL = 0x8004140D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS3_SLICE1_TX_CNTL3_EO_PL = 0x8004540D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS3_SLICE1_TX_FIR_ERROR_INJECT_PL = 0x8004340D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS3_SLICE1_TX_FIR_MASK_PL = 0x80042C0D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS3_SLICE1_TX_FIR_PL = 0x8004240D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS3_SLICE1_TX_MODE1_PL = 0x8004040D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS3_SLICE1_TX_MODE2_PL = 0x80040C0D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS3_SLICE1_TX_STAT1_PL = 0x80041C0D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS3_SLICE2_TX_BIT_MODE1_E_PL = 0x80043C0E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS3_SLICE2_TX_BIT_MODE2_E_PL = 0x8004440E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS3_SLICE2_TX_CNTL1G_PL = 0x8004140E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS3_SLICE2_TX_CNTL3_EO_PL = 0x8004540E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS3_SLICE2_TX_FIR_ERROR_INJECT_PL = 0x8004340E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS3_SLICE2_TX_FIR_MASK_PL = 0x80042C0E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS3_SLICE2_TX_FIR_PL = 0x8004240E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS3_SLICE2_TX_MODE1_PL = 0x8004040E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS3_SLICE2_TX_MODE2_PL = 0x80040C0E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS3_SLICE2_TX_STAT1_PL = 0x80041C0E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS3_SLICE3_TX_BIT_MODE1_E_PL = 0x80043C0F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS3_SLICE3_TX_BIT_MODE2_E_PL = 0x8004440F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS3_SLICE3_TX_CNTL1G_PL = 0x8004140F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS3_SLICE3_TX_CNTL3_EO_PL = 0x8004540F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS3_SLICE3_TX_FIR_ERROR_INJECT_PL = 0x8004340F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS3_SLICE3_TX_FIR_MASK_PL = 0x80042C0F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS3_SLICE3_TX_FIR_PL = 0x8004240F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS3_SLICE3_TX_MODE1_PL = 0x8004040F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS3_SLICE3_TX_MODE2_PL = 0x80040C0F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS3_SLICE3_TX_STAT1_PL = 0x80041C0F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS3_SLICE4_TX_BIT_MODE1_E_PL = 0x80043C100601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS3_SLICE4_TX_BIT_MODE2_E_PL = 0x800444100601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS3_SLICE4_TX_CNTL1G_PL = 0x800414100601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS3_SLICE4_TX_CNTL3_EO_PL = 0x800454100601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS3_SLICE4_TX_FIR_ERROR_INJECT_PL = 0x800434100601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS3_SLICE4_TX_FIR_MASK_PL = 0x80042C100601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS3_SLICE4_TX_FIR_PL = 0x800424100601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS3_SLICE4_TX_MODE1_PL = 0x800404100601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS3_SLICE4_TX_MODE2_PL = 0x80040C100601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TXPACKS3_SLICE4_TX_STAT1_PL = 0x80041C100601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TX_CTLSM_CNTL1_EO_PG = 0x800D34000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TX_CTLSM_CNTL2_EO_PG = 0x800D3C000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TX_CTLSM_CNTL3_EO_PG = 0x800D44000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TX_CTLSM_CNTL4_EO_PG = 0x800D4C000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TX_CTLSM_CNTL5_EO_PG = 0x800D54000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TX_CTLSM_CNTL6_EO_PG = 0x800D5C000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TX_CTLSM_CNTL7_EO_PG = 0x800D64000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TX_CTLSM_CNTLG1_E_PG = 0x800D84000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TX_CTLSM_MODE1_EO_PG = 0x800D2C000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TX_CTLSM_SPARE_MODE_PG = 0x800D24000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TX_CTLSM_STAT1_EO_PG = 0x800D6C000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TX_CTLSM_STAT1_E_PG = 0x800D8C000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TX_CTL_CNTL10_EO_PG = 0x800CDC000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TX_CTL_CNTL2_EO_PG = 0x800C2C000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TX_CTL_CNTL2_E_PG = 0x800C9C000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TX_CTL_CNTL3_EO_PG = 0x800C34000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TX_CTL_CNTL8_EO_PG = 0x800CCC000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TX_CTL_CNTL9_EO_PG = 0x800CD4000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TX_CTL_CNTLG1_EO_PG = 0x800C24000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TX_CTL_CNTLG3_E_PG = 0x800CA4000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TX_CTL_CNTLG4_E_PG = 0x800CAC000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TX_CTL_CNTLG5_E_PG = 0x800CB4000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TX_CTL_CNTLG6_E_PG = 0x800CBC000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TX_CTL_CNTLG7_E_PG = 0x800CC4000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TX_CTL_MODE1_EO_PG = 0x800C14000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TX_CTL_MODE1_E_PG = 0x800C8C000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TX_CTL_MODE2_EO_PG = 0x800C1C000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TX_CTL_MODE2_E_PG = 0x800CEC000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TX_CTL_MODE3_E_PG = 0x800CF4000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TX_CTL_STATG1_E_PG = 0x800CE4000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TX_FIR_ERROR_INJECT_PG = 0x800D1C000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TX_FIR_MASK_PG = 0x800D0C000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TX_FIR_PG = 0x800D04000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TX_FIR_RESET_PG = 0x800D14000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TX_ID1_PG = 0x800C0C000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TX_ID2_PG = 0x800C84000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX0_TX_SPARE_MODE_PG = 0x800C04000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS0_SLICE0_TX_BIT_MODE1_E_PL = 0x80043C200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS0_SLICE0_TX_BIT_MODE2_E_PL = 0x800444200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS0_SLICE0_TX_CNTL1G_PL = 0x800414200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS0_SLICE0_TX_CNTL3_EO_PL = 0x800454200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS0_SLICE0_TX_FIR_ERROR_INJECT_PL = 0x800434200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS0_SLICE0_TX_FIR_MASK_PL = 0x80042C200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS0_SLICE0_TX_FIR_PL = 0x800424200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS0_SLICE0_TX_MODE1_PL = 0x800404200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS0_SLICE0_TX_MODE2_PL = 0x80040C200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS0_SLICE0_TX_STAT1_PL = 0x80041C200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS0_SLICE1_TX_BIT_MODE1_E_PL = 0x80043C210601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS0_SLICE1_TX_BIT_MODE2_E_PL = 0x800444210601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS0_SLICE1_TX_CNTL1G_PL = 0x800414210601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS0_SLICE1_TX_CNTL3_EO_PL = 0x800454210601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS0_SLICE1_TX_FIR_ERROR_INJECT_PL = 0x800434210601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS0_SLICE1_TX_FIR_MASK_PL = 0x80042C210601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS0_SLICE1_TX_FIR_PL = 0x800424210601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS0_SLICE1_TX_MODE1_PL = 0x800404210601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS0_SLICE1_TX_MODE2_PL = 0x80040C210601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS0_SLICE1_TX_STAT1_PL = 0x80041C210601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS0_SLICE2_TX_BIT_MODE1_E_PL = 0x80043C220601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS0_SLICE2_TX_BIT_MODE2_E_PL = 0x800444220601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS0_SLICE2_TX_CNTL1G_PL = 0x800414220601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS0_SLICE2_TX_CNTL3_EO_PL = 0x800454220601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS0_SLICE2_TX_FIR_ERROR_INJECT_PL = 0x800434220601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS0_SLICE2_TX_FIR_MASK_PL = 0x80042C220601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS0_SLICE2_TX_FIR_PL = 0x800424220601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS0_SLICE2_TX_MODE1_PL = 0x800404220601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS0_SLICE2_TX_MODE2_PL = 0x80040C220601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS0_SLICE2_TX_STAT1_PL = 0x80041C220601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS0_SLICE3_TX_BIT_MODE1_E_PL = 0x80043C230601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS0_SLICE3_TX_BIT_MODE2_E_PL = 0x800444230601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS0_SLICE3_TX_CNTL1G_PL = 0x800414230601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS0_SLICE3_TX_CNTL3_EO_PL = 0x800454230601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS0_SLICE3_TX_FIR_ERROR_INJECT_PL = 0x800434230601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS0_SLICE3_TX_FIR_MASK_PL = 0x80042C230601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS0_SLICE3_TX_FIR_PL = 0x800424230601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS0_SLICE3_TX_MODE1_PL = 0x800404230601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS0_SLICE3_TX_MODE2_PL = 0x80040C230601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS0_SLICE3_TX_STAT1_PL = 0x80041C230601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS1_SLICE0_TX_BIT_MODE1_E_PL = 0x80043C240601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS1_SLICE0_TX_BIT_MODE2_E_PL = 0x800444240601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS1_SLICE0_TX_CNTL1G_PL = 0x800414240601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS1_SLICE0_TX_CNTL3_EO_PL = 0x800454240601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS1_SLICE0_TX_FIR_ERROR_INJECT_PL = 0x800434240601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS1_SLICE0_TX_FIR_MASK_PL = 0x80042C240601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS1_SLICE0_TX_FIR_PL = 0x800424240601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS1_SLICE0_TX_MODE1_PL = 0x800404240601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS1_SLICE0_TX_MODE2_PL = 0x80040C240601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS1_SLICE0_TX_STAT1_PL = 0x80041C240601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS1_SLICE1_TX_BIT_MODE1_E_PL = 0x80043C250601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS1_SLICE1_TX_BIT_MODE2_E_PL = 0x800444250601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS1_SLICE1_TX_CNTL1G_PL = 0x800414250601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS1_SLICE1_TX_CNTL3_EO_PL = 0x800454250601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS1_SLICE1_TX_FIR_ERROR_INJECT_PL = 0x800434250601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS1_SLICE1_TX_FIR_MASK_PL = 0x80042C250601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS1_SLICE1_TX_FIR_PL = 0x800424250601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS1_SLICE1_TX_MODE1_PL = 0x800404250601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS1_SLICE1_TX_MODE2_PL = 0x80040C250601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS1_SLICE1_TX_STAT1_PL = 0x80041C250601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS1_SLICE2_TX_BIT_MODE1_E_PL = 0x80043C260601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS1_SLICE2_TX_BIT_MODE2_E_PL = 0x800444260601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS1_SLICE2_TX_CNTL1G_PL = 0x800414260601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS1_SLICE2_TX_CNTL3_EO_PL = 0x800454260601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS1_SLICE2_TX_FIR_ERROR_INJECT_PL = 0x800434260601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS1_SLICE2_TX_FIR_MASK_PL = 0x80042C260601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS1_SLICE2_TX_FIR_PL = 0x800424260601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS1_SLICE2_TX_MODE1_PL = 0x800404260601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS1_SLICE2_TX_MODE2_PL = 0x80040C260601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS1_SLICE2_TX_STAT1_PL = 0x80041C260601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS1_SLICE3_TX_BIT_MODE1_E_PL = 0x80043C270601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS1_SLICE3_TX_BIT_MODE2_E_PL = 0x800444270601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS1_SLICE3_TX_CNTL1G_PL = 0x800414270601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS1_SLICE3_TX_CNTL3_EO_PL = 0x800454270601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS1_SLICE3_TX_FIR_ERROR_INJECT_PL = 0x800434270601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS1_SLICE3_TX_FIR_MASK_PL = 0x80042C270601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS1_SLICE3_TX_FIR_PL = 0x800424270601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS1_SLICE3_TX_MODE1_PL = 0x800404270601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS1_SLICE3_TX_MODE2_PL = 0x80040C270601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS1_SLICE3_TX_STAT1_PL = 0x80041C270601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS2_SLICE0_TX_BIT_MODE1_E_PL = 0x80043C280601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS2_SLICE0_TX_BIT_MODE2_E_PL = 0x800444280601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS2_SLICE0_TX_CNTL1G_PL = 0x800414280601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS2_SLICE0_TX_CNTL3_EO_PL = 0x800454280601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS2_SLICE0_TX_FIR_ERROR_INJECT_PL = 0x800434280601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS2_SLICE0_TX_FIR_MASK_PL = 0x80042C280601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS2_SLICE0_TX_FIR_PL = 0x800424280601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS2_SLICE0_TX_MODE1_PL = 0x800404280601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS2_SLICE0_TX_MODE2_PL = 0x80040C280601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS2_SLICE0_TX_STAT1_PL = 0x80041C280601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS2_SLICE1_TX_BIT_MODE1_E_PL = 0x80043C290601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS2_SLICE1_TX_BIT_MODE2_E_PL = 0x800444290601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS2_SLICE1_TX_CNTL1G_PL = 0x800414290601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS2_SLICE1_TX_CNTL3_EO_PL = 0x800454290601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS2_SLICE1_TX_FIR_ERROR_INJECT_PL = 0x800434290601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS2_SLICE1_TX_FIR_MASK_PL = 0x80042C290601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS2_SLICE1_TX_FIR_PL = 0x800424290601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS2_SLICE1_TX_MODE1_PL = 0x800404290601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS2_SLICE1_TX_MODE2_PL = 0x80040C290601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS2_SLICE1_TX_STAT1_PL = 0x80041C290601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS2_SLICE2_TX_BIT_MODE1_E_PL = 0x80043C2A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS2_SLICE2_TX_BIT_MODE2_E_PL = 0x8004442A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS2_SLICE2_TX_CNTL1G_PL = 0x8004142A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS2_SLICE2_TX_CNTL3_EO_PL = 0x8004542A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS2_SLICE2_TX_FIR_ERROR_INJECT_PL = 0x8004342A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS2_SLICE2_TX_FIR_MASK_PL = 0x80042C2A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS2_SLICE2_TX_FIR_PL = 0x8004242A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS2_SLICE2_TX_MODE1_PL = 0x8004042A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS2_SLICE2_TX_MODE2_PL = 0x80040C2A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS2_SLICE2_TX_STAT1_PL = 0x80041C2A0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS2_SLICE3_TX_BIT_MODE1_E_PL = 0x80043C2B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS2_SLICE3_TX_BIT_MODE2_E_PL = 0x8004442B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS2_SLICE3_TX_CNTL1G_PL = 0x8004142B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS2_SLICE3_TX_CNTL3_EO_PL = 0x8004542B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS2_SLICE3_TX_FIR_ERROR_INJECT_PL = 0x8004342B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS2_SLICE3_TX_FIR_MASK_PL = 0x80042C2B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS2_SLICE3_TX_FIR_PL = 0x8004242B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS2_SLICE3_TX_MODE1_PL = 0x8004042B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS2_SLICE3_TX_MODE2_PL = 0x80040C2B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS2_SLICE3_TX_STAT1_PL = 0x80041C2B0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS3_SLICE0_TX_BIT_MODE1_E_PL = 0x80043C2C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS3_SLICE0_TX_BIT_MODE2_E_PL = 0x8004442C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS3_SLICE0_TX_CNTL1G_PL = 0x8004142C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS3_SLICE0_TX_CNTL3_EO_PL = 0x8004542C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS3_SLICE0_TX_FIR_ERROR_INJECT_PL = 0x8004342C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS3_SLICE0_TX_FIR_MASK_PL = 0x80042C2C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS3_SLICE0_TX_FIR_PL = 0x8004242C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS3_SLICE0_TX_MODE1_PL = 0x8004042C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS3_SLICE0_TX_MODE2_PL = 0x80040C2C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS3_SLICE0_TX_STAT1_PL = 0x80041C2C0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS3_SLICE1_TX_BIT_MODE1_E_PL = 0x80043C2D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS3_SLICE1_TX_BIT_MODE2_E_PL = 0x8004442D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS3_SLICE1_TX_CNTL1G_PL = 0x8004142D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS3_SLICE1_TX_CNTL3_EO_PL = 0x8004542D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS3_SLICE1_TX_FIR_ERROR_INJECT_PL = 0x8004342D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS3_SLICE1_TX_FIR_MASK_PL = 0x80042C2D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS3_SLICE1_TX_FIR_PL = 0x8004242D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS3_SLICE1_TX_MODE1_PL = 0x8004042D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS3_SLICE1_TX_MODE2_PL = 0x80040C2D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS3_SLICE1_TX_STAT1_PL = 0x80041C2D0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS3_SLICE2_TX_BIT_MODE1_E_PL = 0x80043C2E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS3_SLICE2_TX_BIT_MODE2_E_PL = 0x8004442E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS3_SLICE2_TX_CNTL1G_PL = 0x8004142E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS3_SLICE2_TX_CNTL3_EO_PL = 0x8004542E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS3_SLICE2_TX_FIR_ERROR_INJECT_PL = 0x8004342E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS3_SLICE2_TX_FIR_MASK_PL = 0x80042C2E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS3_SLICE2_TX_FIR_PL = 0x8004242E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS3_SLICE2_TX_MODE1_PL = 0x8004042E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS3_SLICE2_TX_MODE2_PL = 0x80040C2E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS3_SLICE2_TX_STAT1_PL = 0x80041C2E0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS3_SLICE3_TX_BIT_MODE1_E_PL = 0x80043C2F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS3_SLICE3_TX_BIT_MODE2_E_PL = 0x8004442F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS3_SLICE3_TX_CNTL1G_PL = 0x8004142F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS3_SLICE3_TX_CNTL3_EO_PL = 0x8004542F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS3_SLICE3_TX_FIR_ERROR_INJECT_PL = 0x8004342F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS3_SLICE3_TX_FIR_MASK_PL = 0x80042C2F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS3_SLICE3_TX_FIR_PL = 0x8004242F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS3_SLICE3_TX_MODE1_PL = 0x8004042F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS3_SLICE3_TX_MODE2_PL = 0x80040C2F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS3_SLICE3_TX_STAT1_PL = 0x80041C2F0601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS3_SLICE4_TX_BIT_MODE1_E_PL = 0x80043C300601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS3_SLICE4_TX_BIT_MODE2_E_PL = 0x800444300601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS3_SLICE4_TX_CNTL1G_PL = 0x800414300601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS3_SLICE4_TX_CNTL3_EO_PL = 0x800454300601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS3_SLICE4_TX_FIR_ERROR_INJECT_PL = 0x800434300601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS3_SLICE4_TX_FIR_MASK_PL = 0x80042C300601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS3_SLICE4_TX_FIR_PL = 0x800424300601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS3_SLICE4_TX_MODE1_PL = 0x800404300601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS3_SLICE4_TX_MODE2_PL = 0x80040C300601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TXPACKS3_SLICE4_TX_STAT1_PL = 0x80041C300601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TX_CTLSM_CNTL1_EO_PG = 0x800D34200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TX_CTLSM_CNTL2_EO_PG = 0x800D3C200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TX_CTLSM_CNTL3_EO_PG = 0x800D44200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TX_CTLSM_CNTL4_EO_PG = 0x800D4C200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TX_CTLSM_CNTL5_EO_PG = 0x800D54200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TX_CTLSM_CNTL6_EO_PG = 0x800D5C200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TX_CTLSM_CNTL7_EO_PG = 0x800D64200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TX_CTLSM_CNTLG1_E_PG = 0x800D84200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TX_CTLSM_MODE1_EO_PG = 0x800D2C200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TX_CTLSM_SPARE_MODE_PG = 0x800D24200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TX_CTLSM_STAT1_EO_PG = 0x800D6C200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TX_CTLSM_STAT1_E_PG = 0x800D8C200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TX_CTL_CNTL10_EO_PG = 0x800CDC200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TX_CTL_CNTL2_EO_PG = 0x800C2C200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TX_CTL_CNTL2_E_PG = 0x800C9C200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TX_CTL_CNTL3_EO_PG = 0x800C34200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TX_CTL_CNTL8_EO_PG = 0x800CCC200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TX_CTL_CNTL9_EO_PG = 0x800CD4200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TX_CTL_CNTLG1_EO_PG = 0x800C24200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TX_CTL_CNTLG3_E_PG = 0x800CA4200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TX_CTL_CNTLG4_E_PG = 0x800CAC200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TX_CTL_CNTLG5_E_PG = 0x800CB4200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TX_CTL_CNTLG6_E_PG = 0x800CBC200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TX_CTL_CNTLG7_E_PG = 0x800CC4200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TX_CTL_MODE1_EO_PG = 0x800C14200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TX_CTL_MODE1_E_PG = 0x800C8C200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TX_CTL_MODE2_EO_PG = 0x800C1C200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TX_CTL_MODE2_E_PG = 0x800CEC200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TX_CTL_MODE3_E_PG = 0x800CF4200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TX_CTL_STATG1_E_PG = 0x800CE4200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TX_FIR_ERROR_INJECT_PG = 0x800D1C200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TX_FIR_MASK_PG = 0x800D0C200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TX_FIR_PG = 0x800D04200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TX_FIR_RESET_PG = 0x800D14200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TX_ID1_PG = 0x800C0C200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TX_ID2_PG = 0x800C84200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX1_TX_SPARE_MODE_PG = 0x800C04200601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX_IMPCAL2_PB = 0x800F3C000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX_IMPCAL_NVAL_PB = 0x800F0C000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX_IMPCAL_PB = 0x800F04000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX_IMPCAL_PVAL_PB = 0x800F14000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX_IMPCAL_P_4X_PB = 0x800F1C000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX_IMPCAL_SWO1_PB = 0x800F24000601143Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_IOF2_TX_IMPCAL_SWO2_PB = 0x800F2C000601143Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_MASK_REG = 0x06011803ull;
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_MASK_REG_AND = 0x06011804ull;
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_MASK_REG_OR = 0x06011805ull;
+
+static const uint64_t P9N2_XBUS_0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_MASK_REG = 0x06011803ull;
+
+static const uint64_t P9N2_XBUS_0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_MASK_REG_AND = 0x06011804ull;
+
+static const uint64_t P9N2_XBUS_0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_MASK_REG_OR = 0x06011805ull;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_REG = 0x06011800ull;
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_REG_AND = 0x06011801ull;
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_REG_OR = 0x06011802ull;
+
+static const uint64_t P9N2_XBUS_0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_REG = 0x06011800ull;
+
+static const uint64_t P9N2_XBUS_0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_REG_AND = 0x06011801ull;
+
+static const uint64_t P9N2_XBUS_0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_REG_OR = 0x06011802ull;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONFIG = 0x0601180Aull;
+
+static const uint64_t P9N2_XBUS_0_C0_S0_P0_E9_LL0_IOEL_CONFIG = 0x0601180Aull;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONTROL = 0x0601180Bull;
+
+static const uint64_t P9N2_XBUS_0_C0_S0_P0_E9_LL0_IOEL_CONTROL = 0x0601180Bull;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_DLL_STATUS = 0x06011828ull;
+
+static const uint64_t P9N2_XBUS_0_C0_S0_P0_E9_LL0_IOEL_DLL_STATUS = 0x06011828ull;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_ERR_INJ_LFSR = 0x0601181Bull;
+
+static const uint64_t P9N2_XBUS_0_C0_S0_P0_E9_LL0_IOEL_ERR_INJ_LFSR = 0x0601181Bull;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_FIR_ACTION0_REG = 0x06011806ull;
+
+static const uint64_t P9N2_XBUS_0_C0_S0_P0_E9_LL0_IOEL_FIR_ACTION0_REG = 0x06011806ull;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_FIR_ACTION1_REG = 0x06011807ull;
+
+static const uint64_t P9N2_XBUS_0_C0_S0_P0_E9_LL0_IOEL_FIR_ACTION1_REG = 0x06011807ull;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_FIR_WOF_REG = 0x06011808ull;
+
+static const uint64_t P9N2_XBUS_0_C0_S0_P0_E9_LL0_IOEL_FIR_WOF_REG = 0x06011808ull;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LAT_MEASURE = 0x0601180Eull;
+
+static const uint64_t P9N2_XBUS_0_C0_S0_P0_E9_LL0_IOEL_LAT_MEASURE = 0x0601180Eull;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_EDPL_STATUS = 0x06011824ull;
+
+static const uint64_t P9N2_XBUS_0_C0_S0_P0_E9_LL0_IOEL_LINK0_EDPL_STATUS = 0x06011824ull;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_ERROR_STATUS = 0x06011816ull;
+
+static const uint64_t P9N2_XBUS_0_C0_S0_P0_E9_LL0_IOEL_LINK0_ERROR_STATUS = 0x06011816ull;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_INFO = 0x06011814ull;
+
+static const uint64_t P9N2_XBUS_0_C0_S0_P0_E9_LL0_IOEL_LINK0_INFO = 0x06011814ull;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_QUALITY = 0x06011826ull;
+
+static const uint64_t P9N2_XBUS_0_C0_S0_P0_E9_LL0_IOEL_LINK0_QUALITY = 0x06011826ull;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_SYN_CAPTURE = 0x06011822ull;
+
+static const uint64_t P9N2_XBUS_0_C0_S0_P0_E9_LL0_IOEL_LINK0_SYN_CAPTURE = 0x06011822ull;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_EDPL_STATUS = 0x06011825ull;
+
+static const uint64_t P9N2_XBUS_0_C0_S0_P0_E9_LL0_IOEL_LINK1_EDPL_STATUS = 0x06011825ull;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_ERROR_STATUS = 0x06011817ull;
+
+static const uint64_t P9N2_XBUS_0_C0_S0_P0_E9_LL0_IOEL_LINK1_ERROR_STATUS = 0x06011817ull;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_INFO = 0x06011815ull;
+
+static const uint64_t P9N2_XBUS_0_C0_S0_P0_E9_LL0_IOEL_LINK1_INFO = 0x06011815ull;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_QUALITY = 0x06011827ull;
+
+static const uint64_t P9N2_XBUS_0_C0_S0_P0_E9_LL0_IOEL_LINK1_QUALITY = 0x06011827ull;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_SYN_CAPTURE = 0x06011823ull;
+
+static const uint64_t P9N2_XBUS_0_C0_S0_P0_E9_LL0_IOEL_LINK1_SYN_CAPTURE = 0x06011823ull;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_COUNTERS_0 = 0x0601181Eull;
+
+static const uint64_t P9N2_XBUS_0_C0_S0_P0_E9_LL0_IOEL_PERF_COUNTERS_0 = 0x0601181Eull;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_COUNTERS_1 = 0x0601181Full;
+
+static const uint64_t P9N2_XBUS_0_C0_S0_P0_E9_LL0_IOEL_PERF_COUNTERS_1 = 0x0601181Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_COUNT_LSB_0 = 0x06011820ull;
+
+static const uint64_t P9N2_XBUS_0_C0_S0_P0_E9_LL0_IOEL_PERF_COUNT_LSB_0 = 0x06011820ull;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_COUNT_LSB_1 = 0x06011821ull;
+
+static const uint64_t P9N2_XBUS_0_C0_S0_P0_E9_LL0_IOEL_PERF_COUNT_LSB_1 = 0x06011821ull;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_SEL_CONFIG = 0x0601181Dull;
+
+static const uint64_t P9N2_XBUS_0_C0_S0_P0_E9_LL0_IOEL_PERF_SEL_CONFIG = 0x0601181Dull;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG = 0x0601181Cull;
+
+static const uint64_t P9N2_XBUS_0_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG = 0x0601181Cull;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_REPLAY_THRESHOLD = 0x06011818ull;
+
+static const uint64_t P9N2_XBUS_0_C0_S0_P0_E9_LL0_IOEL_REPLAY_THRESHOLD = 0x06011818ull;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_SEC_CONFIG = 0x0601180Dull;
+
+static const uint64_t P9N2_XBUS_0_C0_S0_P0_E9_LL0_IOEL_SEC_CONFIG = 0x0601180Dull;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_SL_ECC_THRESHOLD = 0x06011819ull;
+
+static const uint64_t P9N2_XBUS_0_C0_S0_P0_E9_LL0_IOEL_SL_ECC_THRESHOLD = 0x06011819ull;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_MASK_REG = 0x06010C03ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_MASK_REG = 0x06011C03ull;
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_MASK_REG_AND = 0x06010C04ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_MASK_REG_AND = 0x06011C04ull;
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_MASK_REG_OR = 0x06010C05ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_MASK_REG_OR = 0x06011C05ull;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_REG = 0x06010C00ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_REG = 0x06011C00ull;
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_REG_AND = 0x06010C01ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_REG_AND = 0x06011C01ull;
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_REG_OR = 0x06010C02ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_REG_OR = 0x06011C02ull;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_LL1_IOEL_CONFIG = 0x06010C0Aull;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONFIG = 0x06011C0Aull;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_LL1_IOEL_CONTROL = 0x06010C0Bull;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONTROL = 0x06011C0Bull;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_LL1_IOEL_DLL_STATUS = 0x06010C28ull;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_DLL_STATUS = 0x06011C28ull;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_LL1_IOEL_ERR_INJ_LFSR = 0x06010C1Bull;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_ERR_INJ_LFSR = 0x06011C1Bull;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_LL1_IOEL_FIR_ACTION0_REG = 0x06010C06ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_FIR_ACTION0_REG = 0x06011C06ull;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_LL1_IOEL_FIR_ACTION1_REG = 0x06010C07ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_FIR_ACTION1_REG = 0x06011C07ull;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_LL1_IOEL_FIR_WOF_REG = 0x06010C08ull;
+//WARNING - VALUE SET SAME AS ANOTHER REG
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_FIR_WOF_REG = 0x06011C08ull;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_LL1_IOEL_LAT_MEASURE = 0x06010C0Eull;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LAT_MEASURE = 0x06011C0Eull;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_LL1_IOEL_LINK0_EDPL_STATUS = 0x06010C24ull;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_EDPL_STATUS = 0x06011C24ull;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_LL1_IOEL_LINK0_ERROR_STATUS = 0x06010C16ull;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_ERROR_STATUS = 0x06011C16ull;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_LL1_IOEL_LINK0_INFO = 0x06010C14ull;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_INFO = 0x06011C14ull;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_LL1_IOEL_LINK0_QUALITY = 0x06010C26ull;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_QUALITY = 0x06011C26ull;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_LL1_IOEL_LINK0_SYN_CAPTURE = 0x06010C22ull;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_SYN_CAPTURE = 0x06011C22ull;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_LL1_IOEL_LINK1_EDPL_STATUS = 0x06010C25ull;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_EDPL_STATUS = 0x06011C25ull;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_LL1_IOEL_LINK1_ERROR_STATUS = 0x06010C17ull;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_ERROR_STATUS = 0x06011C17ull;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_LL1_IOEL_LINK1_INFO = 0x06010C15ull;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_INFO = 0x06011C15ull;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_LL1_IOEL_LINK1_QUALITY = 0x06010C27ull;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_QUALITY = 0x06011C27ull;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_LL1_IOEL_LINK1_SYN_CAPTURE = 0x06010C23ull;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_SYN_CAPTURE = 0x06011C23ull;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_LL1_IOEL_PERF_COUNTERS_0 = 0x06010C1Eull;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_COUNTERS_0 = 0x06011C1Eull;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_LL1_IOEL_PERF_COUNTERS_1 = 0x06010C1Full;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_COUNTERS_1 = 0x06011C1Full;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_LL1_IOEL_PERF_COUNT_LSB_0 = 0x06010C20ull;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_COUNT_LSB_0 = 0x06011C20ull;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_LL1_IOEL_PERF_COUNT_LSB_1 = 0x06010C21ull;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_COUNT_LSB_1 = 0x06011C21ull;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_LL1_IOEL_PERF_SEL_CONFIG = 0x06010C1Dull;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_SEL_CONFIG = 0x06011C1Dull;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG = 0x06010C1Cull;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG = 0x06011C1Cull;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_LL1_IOEL_REPLAY_THRESHOLD = 0x06010C18ull;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_REPLAY_THRESHOLD = 0x06011C18ull;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_LL1_IOEL_SEC_CONFIG = 0x06010C0Dull;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_SEC_CONFIG = 0x06011C0Dull;
+
+
+static const uint64_t P9N2_XBUS_C0_S0_P0_E9_LL1_IOEL_SL_ECC_THRESHOLD = 0x06010C19ull;
+
+static const uint64_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_SL_ECC_THRESHOLD = 0x06011C19ull;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_LL2_C0_S0_P0_E9_LL2_C0_S0_P0_E9_LL2_IOEL_FIR_MASK_REG = 0x06012003ull;
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_LL2_C0_S0_P0_E9_LL2_C0_S0_P0_E9_LL2_IOEL_FIR_MASK_REG_AND = 0x06012004ull;
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_LL2_C0_S0_P0_E9_LL2_C0_S0_P0_E9_LL2_IOEL_FIR_MASK_REG_OR = 0x06012005ull;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_LL2_C0_S0_P0_E9_LL2_C0_S0_P0_E9_LL2_IOEL_FIR_REG = 0x06012000ull;
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_LL2_C0_S0_P0_E9_LL2_C0_S0_P0_E9_LL2_IOEL_FIR_REG_AND = 0x06012001ull;
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_LL2_C0_S0_P0_E9_LL2_C0_S0_P0_E9_LL2_IOEL_FIR_REG_OR = 0x06012002ull;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_LL2_IOEL_CONFIG = 0x0601200Aull;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_LL2_IOEL_CONTROL = 0x0601200Bull;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_LL2_IOEL_DLL_STATUS = 0x06012028ull;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_LL2_IOEL_ERR_INJ_LFSR = 0x0601201Bull;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_LL2_IOEL_FIR_ACTION0_REG = 0x06012006ull;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_LL2_IOEL_FIR_ACTION1_REG = 0x06012007ull;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_LL2_IOEL_FIR_WOF_REG = 0x06012008ull;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_LL2_IOEL_LAT_MEASURE = 0x0601200Eull;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_LL2_IOEL_LINK0_EDPL_STATUS = 0x06012024ull;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_LL2_IOEL_LINK0_ERROR_STATUS = 0x06012016ull;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_LL2_IOEL_LINK0_INFO = 0x06012014ull;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_LL2_IOEL_LINK0_QUALITY = 0x06012026ull;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_LL2_IOEL_LINK0_SYN_CAPTURE = 0x06012022ull;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_LL2_IOEL_LINK1_EDPL_STATUS = 0x06012025ull;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_LL2_IOEL_LINK1_ERROR_STATUS = 0x06012017ull;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_LL2_IOEL_LINK1_INFO = 0x06012015ull;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_LL2_IOEL_LINK1_QUALITY = 0x06012027ull;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_LL2_IOEL_LINK1_SYN_CAPTURE = 0x06012023ull;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_LL2_IOEL_PERF_COUNTERS_0 = 0x0601201Eull;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_LL2_IOEL_PERF_COUNTERS_1 = 0x0601201Full;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_LL2_IOEL_PERF_COUNT_LSB_0 = 0x06012020ull;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_LL2_IOEL_PERF_COUNT_LSB_1 = 0x06012021ull;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_LL2_IOEL_PERF_SEL_CONFIG = 0x0601201Dull;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_LL2_IOEL_PERF_TRACE_CONFIG = 0x0601201Cull;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_LL2_IOEL_REPLAY_THRESHOLD = 0x06012018ull;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_LL2_IOEL_SEC_CONFIG = 0x0601200Dull;
+
+
+static const uint64_t P9N2_XBUS_2_C0_S0_P0_E9_LL2_IOEL_SL_ECC_THRESHOLD = 0x06012019ull;
+
+
+static const uint64_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_MIB_XIICAC = 0x06010859ull;
+
+
+static const uint64_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_MIB_XIMEM = 0x06010857ull;
+
+
+static const uint64_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_MIB_XISGB = 0x06010858ull;
+
+
+static const uint64_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_FIR_ACTION0_REG = 0x06010846ull;
+
+
+static const uint64_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_FIR_ACTION1_REG = 0x06010847ull;
+
+
+static const uint64_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_FIR_WOF_REG = 0x06010848ull;
+
+
+static const uint64_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIDBGPRO = 0x06010855ull;
+
+
+static const uint64_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMDBG = 0x06010853ull;
+
+
+static const uint64_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMEDR = 0x06010854ull;
+
+
+static const uint64_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMGA = 0x06010852ull;
+
+
+static const uint64_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMRA = 0x06010851ull;
+
+
+static const uint64_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIXCR = 0x06010850ull;
+
+
+static const uint64_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_SCOM_PPE_CNTL = 0x06010860ull;
+
+
+static const uint64_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_SCOM_PPE_WORK_REG1 = 0x06010861ull;
+
+
+static const uint64_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_SCOM_PPE_WORK_REG2 = 0x06010862ull;
+
+
+static const uint64_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_HI_DATA_REG = 0x06010400ull;
+
+
+static const uint64_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_LO_DATA_REG = 0x06010401ull;
+
+
+static const uint64_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRCTRL_CONFIG = 0x06010402ull;
+
+
+static const uint64_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_0 = 0x06010403ull;
+
+
+static const uint64_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_1 = 0x06010404ull;
+
+
+static const uint64_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_2 = 0x06010405ull;
+
+
+static const uint64_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_3 = 0x06010406ull;
+
+
+static const uint64_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_4 = 0x06010407ull;
+
+
+static const uint64_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_5 = 0x06010408ull;
+
+
+static const uint64_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_9 = 0x06010409ull;
+
+
+static const uint64_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_HI_DATA_REG = 0x06010440ull;
+
+
+static const uint64_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_LO_DATA_REG = 0x06010441ull;
+
+
+static const uint64_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRCTRL_CONFIG = 0x06010442ull;
+
+
+static const uint64_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_0 = 0x06010443ull;
+
+
+static const uint64_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_1 = 0x06010444ull;
+
+
+static const uint64_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_2 = 0x06010445ull;
+
+
+static const uint64_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_3 = 0x06010446ull;
+
+
+static const uint64_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_4 = 0x06010447ull;
+
+
+static const uint64_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_5 = 0x06010448ull;
+
+
+static const uint64_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_9 = 0x06010449ull;
+
+
+static const uint64_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_HI_DATA_REG = 0x06010480ull;
+
+
+static const uint64_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_LO_DATA_REG = 0x06010481ull;
+
+
+static const uint64_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRCTRL_CONFIG = 0x06010482ull;
+
+
+static const uint64_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_0 = 0x06010483ull;
+
+
+static const uint64_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_1 = 0x06010484ull;
+
+
+static const uint64_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_2 = 0x06010485ull;
+
+
+static const uint64_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_3 = 0x06010486ull;
+
+
+static const uint64_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_4 = 0x06010487ull;
+
+
+static const uint64_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_5 = 0x06010488ull;
+
+
+static const uint64_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_9 = 0x06010489ull;
+
+
+static const uint64_t P9N2_XBUS_PERV_C0_S0_P0_E9_XTRA_TRACE_MODE = 0x060107D1ull;
+
+#endif
diff --git a/src/import/chips/p9/common/include/p9n2_xbus_scom_addresses_fld.H b/src/import/chips/p9/common/include/p9n2_xbus_scom_addresses_fld.H
new file mode 100644
index 000000000..7f577c0ef
--- /dev/null
+++ b/src/import/chips/p9/common/include/p9n2_xbus_scom_addresses_fld.H
@@ -0,0 +1,18456 @@
+/* IBM_PROLOG_BEGIN_TAG */
+/* This is an automatically generated prolog. */
+/* */
+/* $Source: src/import/chips/p9/common/include/p9n2_xbus_scom_addresses_fld.H $ */
+/* */
+/* OpenPOWER HostBoot Project */
+/* */
+/* Contributors Listed Below - COPYRIGHT 2017 */
+/* [+] International Business Machines Corp. */
+/* */
+/* */
+/* Licensed under the Apache License, Version 2.0 (the "License"); */
+/* you may not use this file except in compliance with the License. */
+/* You may obtain a copy of the License at */
+/* */
+/* http://www.apache.org/licenses/LICENSE-2.0 */
+/* */
+/* Unless required by applicable law or agreed to in writing, software */
+/* distributed under the License is distributed on an "AS IS" BASIS, */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */
+/* implied. See the License for the specific language governing */
+/* permissions and limitations under the License. */
+/* */
+/* IBM_PROLOG_END_TAG */
+///
+/// @file p9_xbus_scom_addresses_fld.H
+/// @brief Defines constants for scom addresses
+///
+// *HWP HWP Owner: Ben Gass <bgass@us.ibm.com>
+// *HWP FW Owner: Thi Tran <thi@us.ibm.com>
+// *HWP Team: SOA
+// *HWP Level: 1
+// *HWP Consumed by: FSP:HB:HS:OCC:SBE:CME:SGPE:PGPE:FPPE:IPPE
+
+#ifndef __P9N2_XBUS_SCOM_ADDRESSES_FLD_H
+#define __P9N2_XBUS_SCOM_ADDRESSES_FLD_H
+
+#include <stdint.h>
+
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_CSCR_SRAM_ACCESS_MODE = 0 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_CSCR_SRAM_SCRUB_ENABLE = 1 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_CSCR_ECC_CORRECT_DIS = 2 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_CSCR_ECC_DETECT_DIS = 3 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_CSCR_ECC_INJECT_TYPE = 4 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_CSCR_ECC_INJECT_ERR = 5 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_CSCR_SPARE_6_7 = 6 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_CSCR_SPARE_6_7_LEN = 2 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_CSCR_SRAM_SCRUB_INDEX = 47 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_CSCR_SRAM_SCRUB_INDEX_LEN = 13 ;
+
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_PPE_FIR_MASK_REG_ERROR = 0 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_PPE_FIR_MASK_REG_ERROR_LEN = 4 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_PPE_FIR_MASK_REG_HALTED = 4 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_PPE_FIR_MASK_REG_WATCHDOG_TIMEOUT = 5 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_PPE_FIR_MASK_REG_MMIO_DATA_IN = 6 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_PPE_FIR_MASK_REG_ARB_MISSED_SCRUB_TICK = 7 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_PPE_FIR_MASK_REG_ARB_ARY_UE = 8 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_PPE_FIR_MASK_REG_ARB_ARY_CE = 9 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_PPE_FIR_MASK_REG_RESERVED = 10 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_PPE_FIR_MASK_REG_INTERNAL_SCOM_ERROR = 11 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_PPE_FIR_MASK_REG_INTERNAL_SCOM_ERROR_CLONE = 12
+ ;
+
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_PPE_FIR_REG_ERROR = 0 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_PPE_FIR_REG_ERROR_LEN = 4 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_PPE_FIR_REG_HALTED = 4 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_PPE_FIR_REG_WATCHDOG_TIMEOUT = 5 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_PPE_FIR_REG_MMIO_DATA_IN = 6 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_PPE_FIR_REG_ARB_MISSED_SCRUB_TICK = 7 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_PPE_FIR_REG_ARB_ARY_UE = 8 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_PPE_FIR_REG_ARB_ARY_CE = 9 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_PPE_FIR_REG_RESERVED = 10 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_PPE_FIR_REG_SCOMFIR_ERROR = 11 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_PPE_FIR_REG_SCOMFIR_ERROR_CLONE = 12 ;
+
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_SCOM_PPE_FLAGS_FIELD = 0 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_C0_S0_P0_E9_C0_S0_P0_E9_SCOM_PPE_FLAGS_FIELD_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_CSAR_SRAM_ADDRESS = 16 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_CSAR_SRAM_ADDRESS_LEN = 13 ;
+
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_CSDR_SRAM_DATA = 0 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_CSDR_SRAM_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_1_COND1_SEL_A = 0 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_1_COND1_SEL_A_LEN = 8 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_1_COND1_SEL_B = 8 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_1_COND1_SEL_B_LEN = 8 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_1_COND2_SEL_A = 16 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_1_COND2_SEL_A_LEN = 8 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_1_COND2_SEL_B = 24 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_1_COND2_SEL_B_LEN = 8 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_1_C1_INAROW_MODE = 32 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE1 = 33 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE1 = 34 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE1 = 35 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_1_UNUSED = 36 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_1_UNUSED_LEN = 3 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_1_C2_INAROW_MODE = 39 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE2 = 40 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE2 = 41 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE2 = 42 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_1_UNUSED_2 = 43 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_1_UNUSED_2_LEN = 3 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_1_COND3_ENABLE_RESET = 46 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_1_EXACT_TO_MODE = 47 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_1_RESET_C2TIMER_ON_C1 = 48 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_1_RESET_C3_ON_C0 = 49 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_1_SLOW_TO_MODE = 50 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_1_EXACT_RESET_C3_ON_TO = 51 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_1_C1_COUNT_LT = 52 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_1_C1_COUNT_LT_LEN = 4 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_1_C2_COUNT_LT = 56 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_1_C2_COUNT_LT_LEN = 4 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_1_RESET_C3_SELECT = 60 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_1_RESET_C3_SELECT_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A = 0 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN = 5 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B = 5 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN = 5 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A = 10 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN = 5 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B = 15 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN = 5 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_2_TO_CMP_LT = 20 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST1_COND_REG_2_TO_CMP_LT_LEN = 24 ;
+
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_1_COND1_SEL_A = 0 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_1_COND1_SEL_A_LEN = 8 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_1_COND1_SEL_B = 8 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_1_COND1_SEL_B_LEN = 8 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_1_COND2_SEL_A = 16 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_1_COND2_SEL_A_LEN = 8 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_1_COND2_SEL_B = 24 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_1_COND2_SEL_B_LEN = 8 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_1_C1_INAROW_MODE = 32 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE1 = 33 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE1 = 34 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE1 = 35 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_1_UNUSED = 36 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_1_UNUSED_LEN = 3 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_1_C2_INAROW_MODE = 39 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE2 = 40 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE2 = 41 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE2 = 42 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_1_UNUSED_2 = 43 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_1_UNUSED_2_LEN = 3 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_1_COND3_ENABLE_RESET = 46 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_1_EXACT_TO_MODE = 47 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_1_RESET_C2TIMER_ON_C1 = 48 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_1_RESET_C3_ON_C0 = 49 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_1_SLOW_TO_MODE = 50 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_1_EXACT_RESET_C3_ON_TO = 51 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_1_C1_COUNT_LT = 52 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_1_C1_COUNT_LT_LEN = 4 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_1_C2_COUNT_LT = 56 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_1_C2_COUNT_LT_LEN = 4 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_1_RESET_C3_SELECT = 60 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_1_RESET_C3_SELECT_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A = 0 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN = 5 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B = 5 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN = 5 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A = 10 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN = 5 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B = 15 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN = 5 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_2_TO_CMP_LT = 20 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_INST2_COND_REG_2_TO_CMP_LT_LEN = 24 ;
+
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_MODE_REG_GLB_BRCST = 0 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_MODE_REG_GLB_BRCST_LEN = 3 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_MODE_REG_TRACE_SEL = 3 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_MODE_REG_TRACE_SEL_LEN = 3 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_MODE_REG_TRIG_SEL = 6 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_MODE_REG_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_MODE_REG_STOP_ON_XSTOP_SELECTION = 8 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_MODE_REG_STOP_ON_RECOV_ERR_SELECTION = 9 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_MODE_REG_STOP_ON_SPATTN_SELECTION = 10 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_MODE_REG_FREEZE_SEL = 11 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_MODE_REG_SYNC_BRCST = 12 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_MODE_REG_SYNC_BRCST_LEN = 2 ;
+
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE = 0 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE_LEN = 16 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_MODE_REG_2_IMM_FREEZE = 16 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_MODE_REG_2_STOP_ON_ERR = 17 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_MODE_REG_2_BANK_ON_RUNN_MATCH = 18 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_MODE_REG_2_FORCE_TEST = 19 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_MODE_REG_2_ACCUM_HIST = 20 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_MODE_REG_2_FRZ_COUNT_ON_FRZ = 21 ;
+
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_0_INST1_COND3_ENABLE = 0 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_0_INST2_COND3_ENABLE = 1 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_0_INST3_COND3_ENABLE = 2 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_0_INST4_COND3_ENABLE = 3 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_0_INST1_SLOW_LFSR_MODE = 4 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_0_INST2_SLOW_LFSR_MODE = 5 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_0_INST3_SLOW_LFSR_MODE = 6 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_0_INST4_SLOW_LFSR_MODE = 7 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL = 8 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL = 10 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL = 12 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL = 14 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL = 16 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL = 18 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_0_EXT_TRIG_ON_STOP = 32 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_0_EXT_TRIG_ON_FREEZE = 33 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL = 34 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL = 39 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_0_PC_TP_TRIG_SEL = 44 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_0_PC_TP_TRIG_SEL_LEN = 2 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_0_ARM_SEL = 46 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_0_ARM_SEL_LEN = 4 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL = 50 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL_LEN = 4 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL = 54 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO = 0 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO_LEN = 2 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO = 2 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO_LEN = 2 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO = 4 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO_LEN = 2 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO = 6 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO_LEN = 2 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO = 8 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO_LEN = 2 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO = 10 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO_LEN = 2 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_WAITN = 24 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_WAITN = 25 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_WAITN = 26 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_WAITN = 27 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_WAITN = 28 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_WAITN = 29 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_BANK = 36 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_BANK = 37 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_BANK = 38 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_BANK = 39 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_BANK = 40 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_BANK = 41 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT = 48 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT_LEN = 3 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_SELECTOR = 51 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT = 52 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT_LEN = 3 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_SELECTOR = 55 ;
+
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DEBUG_TRACE_CONTROL_SCOM_TRACE_START = 0 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DEBUG_TRACE_CONTROL_SCOM_TRACE_STOP = 1 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_DEBUG_TRACE_CONTROL_SCOM_TRACE_RESET = 2 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_RX_INVALID_STATE_OR_PARITY_ERROR = 0 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_TX_INVALID_STATE_OR_PARITY_ERROR = 1 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_GCR_HANG_ERROR = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_RESERVED3_7 = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_RESERVED3_7_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_RX_BUS0_TRAINING_ERROR
+ = 8 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_RX_BUS0_SPARE_DEPLOYED
+ = 9 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_RX_BUS0_MAX_SPARES_EXCEEDED = 10 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_RX_BUS0_RECAL_OR_DYN_REPAIR_ERROR = 11 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_RX_BUS0_TOO_MANY_BUS_ERRORS = 12 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_RESERVED13_15 = 13 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_RESERVED13_15_LEN = 3
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_RX_BUS1_TRAINING_ERROR
+ = 16 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_RX_BUS1_SPARE_DEPLOYED
+ = 17 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_RX_BUS1_MAX_SPARES_EXCEEDED = 18 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_RX_BUS1_RECAL_OR_DYN_REPAIR_ERROR = 19 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_RX_BUS1_TOO_MANY_BUS_ERRORS = 20 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_RESERVED21_23 = 21 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_RESERVED21_23_LEN = 3
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_RX_BUS2_TRAINING_ERROR
+ = 24 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_RX_BUS2_SPARE_DEPLOYED
+ = 25 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_RX_BUS2_MAX_SPARES_EXCEEDED = 26 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_RX_BUS2_RECAL_OR_DYN_REPAIR_ERROR = 27 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_RX_BUS2_TOO_MANY_BUS_ERRORS = 28 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_RESERVED29_31 = 29 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_RESERVED29_31_LEN = 3
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_RX_BUS3_TRAINING_ERROR
+ = 32 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_RX_BUS3_SPARE_DEPLOYED
+ = 33 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_RX_BUS3_MAX_SPARES_EXCEEDED = 34 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_RX_BUS3_RECAL_OR_DYN_REPAIR_ERROR = 35 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_RX_BUS3_TOO_MANY_BUS_ERRORS = 36 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_RESERVED37_39 = 37 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_RESERVED37_39_LEN = 3
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_RX_BUS4_TRAINING_ERROR
+ = 40 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_RX_BUS4_SPARE_DEPLOYED
+ = 41 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_RX_BUS4_MAX_SPARES_EXCEEDED = 42 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_RX_BUS4_RECAL_OR_DYN_REPAIR_ERROR = 43 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_RX_BUS4_TOO_MANY_BUS_ERRORS = 44 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_RESERVED45_47 = 45 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_RESERVED45_47_LEN = 3
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_INTERNAL_SCOM_ERROR =
+ 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_MASK_REG_INTERNAL_SCOM_ERROR_CLONE = 49 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_RX_INVALID_STATE_OR_PARITY_ERROR = 0 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_TX_INVALID_STATE_OR_PARITY_ERROR = 1 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_GCR_HANG_ERROR = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_RESERVED3_7 = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_RESERVED3_7_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_RX_BUS0_TRAINING_ERROR = 8
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_RX_BUS0_SPARE_DEPLOYED = 9
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_RX_BUS0_MAX_SPARES_EXCEEDED
+ = 10 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_RX_BUS0_RECAL_OR_DYN_REPAIR_ERROR = 11 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_RX_BUS0_TOO_MANY_BUS_ERRORS
+ = 12 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_RESERVED13_15 = 13 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_RESERVED13_15_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_RX_BUS1_TRAINING_ERROR = 16
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_RX_BUS1_SPARE_DEPLOYED = 17
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_RX_BUS1_MAX_SPARES_EXCEEDED
+ = 18 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_RX_BUS1_RECAL_OR_DYN_REPAIR_ERROR = 19 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_RX_BUS1_TOO_MANY_BUS_ERRORS
+ = 20 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_RESERVED21_23 = 21 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_RESERVED21_23_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_RX_BUS2_TRAINING_ERROR = 24
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_RX_BUS2_SPARE_DEPLOYED = 25
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_RX_BUS2_MAX_SPARES_EXCEEDED
+ = 26 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_RX_BUS2_RECAL_OR_DYN_REPAIR_ERROR = 27 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_RX_BUS2_TOO_MANY_BUS_ERRORS
+ = 28 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_RESERVED29_31 = 29 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_RESERVED29_31_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_RX_BUS3_TRAINING_ERROR = 32
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_RX_BUS3_SPARE_DEPLOYED = 33
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_RX_BUS3_MAX_SPARES_EXCEEDED
+ = 34 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_RX_BUS3_RECAL_OR_DYN_REPAIR_ERROR = 35 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_RX_BUS3_TOO_MANY_BUS_ERRORS
+ = 36 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_RESERVED37_39 = 37 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_RESERVED37_39_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_RX_BUS4_TRAINING_ERROR = 40
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_RX_BUS4_SPARE_DEPLOYED = 41
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_RX_BUS4_MAX_SPARES_EXCEEDED
+ = 42 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_RX_BUS4_RECAL_OR_DYN_REPAIR_ERROR = 43 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_RX_BUS4_TOO_MANY_BUS_ERRORS
+ = 44 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_RESERVED45_47 = 45 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_RESERVED45_47_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_SCOMFIR_ERROR = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_C0_S0_P0_E9_IOF1_FIR_REG_SCOMFIR_ERROR_CLONE = 49 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_FIR_ACTION0_REG_ACTION0 = 0 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_FIR_ACTION0_REG_ACTION0_LEN = 50 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_FIR_ACTION1_REG_ACTION1 = 0 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_FIR_ACTION1_REG_ACTION1_LEN = 50 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_FIR_WOF_REG_WOF = 0 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_FIR_WOF_REG_WOF_LEN = 50 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL
+ = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL
+ = 52 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 53 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 57 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 59 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 61 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 62 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN =
+ 2 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 51 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 52
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 53
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL = 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN = 2 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP = 58
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM = 59
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN =
+ 3 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_LANE_INVALID = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_PDWN_LITE = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL =
+ 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL =
+ 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL
+ = 50 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL =
+ 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL =
+ 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL
+ = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL
+ = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL =
+ 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
+ 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL = 59 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL =
+ 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN
+ = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL =
+ 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_E_PL_A_H2E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_E_PL_A_H2O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_E_PL_A_H3E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_E_PL_A_H3O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_E_PL_A_H4E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_E_PL_A_H4O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_E_PL_A_H5E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_E_PL_A_H5O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_E_PL_A_H6_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_E_PL_A_H7_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_E_PL_A_H8_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_E_PL_A_H9_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL7_E_PL_A_H10_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL7_E_PL_A_H11_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL8_E_PL_A_H12_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL9_E_PL_A_H1CAL_EN = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_FIR_MASK_PL_ERRS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_FIR_MASK_PL_ERRS_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL
+ = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL
+ = 52 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 53 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 57 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 59 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 61 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 62 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN =
+ 2 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 51 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 52
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 53
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL = 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN = 2 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP = 58
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM = 59
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN =
+ 3 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_LANE_INVALID = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_PDWN_LITE = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL =
+ 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL =
+ 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL
+ = 50 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL =
+ 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL =
+ 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL
+ = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL
+ = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL =
+ 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
+ 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL = 59 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL =
+ 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN
+ = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL =
+ 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_E_PL_A_H2E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_E_PL_A_H2O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_E_PL_A_H3E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_E_PL_A_H3O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_E_PL_A_H4E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_E_PL_A_H4O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_E_PL_A_H5E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_E_PL_A_H5O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_E_PL_A_H6_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_E_PL_A_H7_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_E_PL_A_H8_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_E_PL_A_H9_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL7_E_PL_A_H10_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL7_E_PL_A_H11_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL8_E_PL_A_H12_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL9_E_PL_A_H1CAL_EN = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_FIR_MASK_PL_ERRS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_FIR_MASK_PL_ERRS_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL
+ = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL
+ = 52 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 53 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 57 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 59 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 61 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 62 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN =
+ 2 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 51 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 52
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 53
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL = 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN = 2 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP = 58
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM = 59
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN =
+ 3 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_LANE_INVALID = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_PDWN_LITE = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL =
+ 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL =
+ 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL
+ = 50 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL =
+ 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL =
+ 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL
+ = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL
+ = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL =
+ 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
+ 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL = 59 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL =
+ 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN
+ = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL =
+ 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_E_PL_A_H2E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_E_PL_A_H2O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_E_PL_A_H3E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_E_PL_A_H3O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_E_PL_A_H4E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_E_PL_A_H4O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_E_PL_A_H5E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_E_PL_A_H5O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_E_PL_A_H6_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_E_PL_A_H7_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_E_PL_A_H8_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_E_PL_A_H9_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL7_E_PL_A_H10_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL7_E_PL_A_H11_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL8_E_PL_A_H12_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL9_E_PL_A_H1CAL_EN = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_FIR_MASK_PL_ERRS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_FIR_MASK_PL_ERRS_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL
+ = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL
+ = 52 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 53 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 57 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 59 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 61 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 62 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN =
+ 2 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 51 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 52
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 53
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL = 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN = 2 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP = 58
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM = 59
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN =
+ 3 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_LANE_INVALID = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_PDWN_LITE = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL =
+ 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL =
+ 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL
+ = 50 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL =
+ 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL =
+ 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL
+ = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL
+ = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL =
+ 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
+ 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL = 59 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL =
+ 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN
+ = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL =
+ 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_E_PL_A_H2E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_E_PL_A_H2O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_E_PL_A_H3E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_E_PL_A_H3O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL3_E_PL_A_H4E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL3_E_PL_A_H4O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_E_PL_A_H5E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_E_PL_A_H5O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_E_PL_A_H6_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_E_PL_A_H7_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL6_E_PL_A_H8_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL6_E_PL_A_H9_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL7_E_PL_A_H10_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL7_E_PL_A_H11_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL8_E_PL_A_H12_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL9_E_PL_A_H1CAL_EN = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_FIR_MASK_PL_ERRS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_FIR_MASK_PL_ERRS_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL
+ = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL
+ = 52 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 53 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 57 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 59 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 61 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 62 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN =
+ 2 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 51 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 52
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 53
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL = 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN = 2 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP = 58
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM = 59
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN =
+ 3 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_LANE_INVALID = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_PDWN_LITE = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL =
+ 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL =
+ 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL
+ = 50 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL =
+ 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL =
+ 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL
+ = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL
+ = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL =
+ 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
+ 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL = 59 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL =
+ 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN
+ = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL =
+ 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_E_PL_A_H2E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_E_PL_A_H2O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_E_PL_A_H3E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_E_PL_A_H3O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL3_E_PL_A_H4E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL3_E_PL_A_H4O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_E_PL_A_H5E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_E_PL_A_H5O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_E_PL_A_H6_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_E_PL_A_H7_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL6_E_PL_A_H8_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL6_E_PL_A_H9_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL7_E_PL_A_H10_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL7_E_PL_A_H11_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL8_E_PL_A_H12_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL9_E_PL_A_H1CAL_EN = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_FIR_MASK_PL_ERRS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_FIR_MASK_PL_ERRS_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL
+ = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL
+ = 52 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 53 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 57 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 59 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 61 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 62 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN =
+ 2 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 51 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 52
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 53
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL = 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN = 2 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP = 58
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM = 59
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN =
+ 3 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_LANE_INVALID = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_PDWN_LITE = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL =
+ 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL =
+ 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL
+ = 50 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL =
+ 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL =
+ 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL
+ = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL
+ = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL =
+ 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
+ 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL = 59 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL =
+ 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN
+ = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL =
+ 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_E_PL_A_H2E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_E_PL_A_H2O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_E_PL_A_H3E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_E_PL_A_H3O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL3_E_PL_A_H4E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL3_E_PL_A_H4O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_E_PL_A_H5E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_E_PL_A_H5O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_E_PL_A_H6_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_E_PL_A_H7_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL6_E_PL_A_H8_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL6_E_PL_A_H9_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL7_E_PL_A_H10_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL7_E_PL_A_H11_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL8_E_PL_A_H12_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL9_E_PL_A_H1CAL_EN = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_FIR_MASK_PL_ERRS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_FIR_MASK_PL_ERRS_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL
+ = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL
+ = 52 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 53 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 57 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 59 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 61 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 62 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN =
+ 2 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 51 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 52
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 53
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL = 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN = 2 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP = 58
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM = 59
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN =
+ 3 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_LANE_INVALID = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_PDWN_LITE = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL =
+ 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL =
+ 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL
+ = 50 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL =
+ 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL =
+ 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL
+ = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL
+ = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL =
+ 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
+ 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL = 59 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL =
+ 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN
+ = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL =
+ 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_E_PL_A_H2E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_E_PL_A_H2O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_E_PL_A_H3E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_E_PL_A_H3O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL3_E_PL_A_H4E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL3_E_PL_A_H4O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_E_PL_A_H5E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_E_PL_A_H5O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_E_PL_A_H6_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_E_PL_A_H7_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL6_E_PL_A_H8_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL6_E_PL_A_H9_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL7_E_PL_A_H10_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL7_E_PL_A_H11_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL8_E_PL_A_H12_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL9_E_PL_A_H1CAL_EN = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_FIR_MASK_PL_ERRS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_FIR_MASK_PL_ERRS_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL
+ = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL
+ = 52 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 53 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 57 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 59 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 61 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 62 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN =
+ 2 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 51 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 52
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 53
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL = 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN = 2 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP = 58
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM = 59
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN =
+ 3 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_LANE_INVALID = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_PDWN_LITE = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL =
+ 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL =
+ 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL
+ = 50 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL =
+ 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL =
+ 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL
+ = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL
+ = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL =
+ 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
+ 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL = 59 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL =
+ 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN
+ = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL =
+ 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_E_PL_A_H2E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_E_PL_A_H2O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_E_PL_A_H3E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_E_PL_A_H3O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL3_E_PL_A_H4E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL3_E_PL_A_H4O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_E_PL_A_H5E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_E_PL_A_H5O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_E_PL_A_H6_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_E_PL_A_H7_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL6_E_PL_A_H8_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL6_E_PL_A_H9_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL7_E_PL_A_H10_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL7_E_PL_A_H11_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL8_E_PL_A_H12_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL9_E_PL_A_H1CAL_EN = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_FIR_MASK_PL_ERRS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_FIR_MASK_PL_ERRS_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL
+ = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL
+ = 52 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 53 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 57 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 59 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 61 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 62 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN =
+ 2 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 51 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 52
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 53
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL = 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN = 2 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP = 58
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM = 59
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN =
+ 3 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_LANE_INVALID = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_PDWN_LITE = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL =
+ 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL =
+ 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL
+ = 50 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL =
+ 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL =
+ 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL
+ = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL
+ = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL =
+ 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
+ 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL = 59 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL =
+ 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN
+ = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL =
+ 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_E_PL_A_H2E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_E_PL_A_H2O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_E_PL_A_H3E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_E_PL_A_H3O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL3_E_PL_A_H4E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL3_E_PL_A_H4O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_E_PL_A_H5E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_E_PL_A_H5O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_E_PL_A_H6_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_E_PL_A_H7_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL6_E_PL_A_H8_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL6_E_PL_A_H9_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL7_E_PL_A_H10_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL7_E_PL_A_H11_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL8_E_PL_A_H12_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL9_E_PL_A_H1CAL_EN = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_FIR_MASK_PL_ERRS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_FIR_MASK_PL_ERRS_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL
+ = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL
+ = 52 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 53 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 57 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 59 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 61 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 62 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN =
+ 2 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 51 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 52
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 53
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL = 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN = 2 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP = 58
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM = 59
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN =
+ 3 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_LANE_INVALID = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_PDWN_LITE = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL =
+ 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL =
+ 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL
+ = 50 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL =
+ 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL =
+ 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL
+ = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL
+ = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL =
+ 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
+ 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL = 59 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL =
+ 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN
+ = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL =
+ 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_E_PL_A_H2E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_E_PL_A_H2O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_E_PL_A_H3E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_E_PL_A_H3O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL3_E_PL_A_H4E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL3_E_PL_A_H4O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_E_PL_A_H5E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_E_PL_A_H5O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_E_PL_A_H6_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_E_PL_A_H7_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL6_E_PL_A_H8_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL6_E_PL_A_H9_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL7_E_PL_A_H10_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL7_E_PL_A_H11_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL8_E_PL_A_H12_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL9_E_PL_A_H1CAL_EN = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_FIR_MASK_PL_ERRS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_FIR_MASK_PL_ERRS_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL
+ = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL
+ = 52 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 53 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 57 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 59 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 61 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 62 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN =
+ 2 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 51 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 52
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 53
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL = 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN = 2 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP = 58
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM = 59
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN =
+ 3 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_LANE_INVALID = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_PDWN_LITE = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL =
+ 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL =
+ 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL
+ = 50 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL =
+ 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL =
+ 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL
+ = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL
+ = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL =
+ 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
+ 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL = 59 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL =
+ 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN
+ = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL =
+ 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_E_PL_A_H2E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_E_PL_A_H2O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_E_PL_A_H3E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_E_PL_A_H3O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL3_E_PL_A_H4E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL3_E_PL_A_H4O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_E_PL_A_H5E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_E_PL_A_H5O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_E_PL_A_H6_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_E_PL_A_H7_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL6_E_PL_A_H8_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL6_E_PL_A_H9_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL7_E_PL_A_H10_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL7_E_PL_A_H11_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL8_E_PL_A_H12_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL9_E_PL_A_H1CAL_EN = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_FIR_MASK_PL_ERRS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_FIR_MASK_PL_ERRS_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL
+ = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL
+ = 52 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 53 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 57 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 59 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 61 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 62 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN =
+ 2 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 51 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 52
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 53
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL = 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN = 2 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP = 58
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM = 59
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN =
+ 3 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_LANE_INVALID = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_PDWN_LITE = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL =
+ 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL =
+ 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL
+ = 50 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL =
+ 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL =
+ 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL
+ = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL
+ = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL =
+ 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
+ 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL = 59 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL =
+ 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN
+ = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL =
+ 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_E_PL_A_H2E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_E_PL_A_H2O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_E_PL_A_H3E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_E_PL_A_H3O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL3_E_PL_A_H4E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL3_E_PL_A_H4O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_E_PL_A_H5E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_E_PL_A_H5O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_E_PL_A_H6_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_E_PL_A_H7_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL6_E_PL_A_H8_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL6_E_PL_A_H9_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL7_E_PL_A_H10_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL7_E_PL_A_H11_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL8_E_PL_A_H12_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL9_E_PL_A_H1CAL_EN = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_FIR_MASK_PL_ERRS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_FIR_MASK_PL_ERRS_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL
+ = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL
+ = 52 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 53 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 57 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 59 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 61 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 62 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN =
+ 2 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 51 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 52
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 53
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL = 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN = 2 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP = 58
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM = 59
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN =
+ 3 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_LANE_INVALID = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_PDWN_LITE = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL =
+ 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL =
+ 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL
+ = 50 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL =
+ 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL =
+ 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL
+ = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL
+ = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL =
+ 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
+ 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL = 59 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL =
+ 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN
+ = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL =
+ 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_E_PL_A_H2E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_E_PL_A_H2O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_E_PL_A_H3E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_E_PL_A_H3O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL3_E_PL_A_H4E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL3_E_PL_A_H4O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_E_PL_A_H5E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_E_PL_A_H5O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_E_PL_A_H6_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_E_PL_A_H7_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL6_E_PL_A_H8_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL6_E_PL_A_H9_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL7_E_PL_A_H10_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL7_E_PL_A_H11_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL8_E_PL_A_H12_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL9_E_PL_A_H1CAL_EN = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_FIR_MASK_PL_ERRS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_FIR_MASK_PL_ERRS_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL
+ = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL
+ = 52 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 53 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 57 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 59 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 61 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 62 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN =
+ 2 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 51 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 52
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 53
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL = 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN = 2 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP = 58
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM = 59
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN =
+ 3 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_LANE_INVALID = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_PDWN_LITE = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL =
+ 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL =
+ 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL
+ = 50 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL =
+ 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL =
+ 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL
+ = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL
+ = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL =
+ 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
+ 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL = 59 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL =
+ 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN
+ = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL =
+ 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_E_PL_A_H2E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_E_PL_A_H2O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_E_PL_A_H3E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_E_PL_A_H3O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL3_E_PL_A_H4E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL3_E_PL_A_H4O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_E_PL_A_H5E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_E_PL_A_H5O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_E_PL_A_H6_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_E_PL_A_H7_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL6_E_PL_A_H8_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL6_E_PL_A_H9_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL7_E_PL_A_H10_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL7_E_PL_A_H11_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL8_E_PL_A_H12_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL9_E_PL_A_H1CAL_EN = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_FIR_MASK_PL_ERRS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_FIR_MASK_PL_ERRS_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL
+ = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL
+ = 52 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 53 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 57 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 59 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 61 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 62 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN =
+ 2 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 51 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 52
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 53
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL = 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN = 2 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP = 58
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM = 59
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN =
+ 3 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_LANE_INVALID = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_PDWN_LITE = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL =
+ 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL =
+ 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL
+ = 50 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL =
+ 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL =
+ 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL
+ = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL
+ = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL =
+ 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
+ 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL = 59 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL =
+ 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN
+ = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL =
+ 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_E_PL_A_H2E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_E_PL_A_H2O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_E_PL_A_H3E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_E_PL_A_H3O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL3_E_PL_A_H4E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL3_E_PL_A_H4O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_E_PL_A_H5E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_E_PL_A_H5O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_E_PL_A_H6_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_E_PL_A_H7_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL6_E_PL_A_H8_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL6_E_PL_A_H9_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL7_E_PL_A_H10_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL7_E_PL_A_H11_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL8_E_PL_A_H12_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL9_E_PL_A_H1CAL_EN = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_FIR_MASK_PL_ERRS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_FIR_MASK_PL_ERRS_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL
+ = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL
+ = 52 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 53 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 57 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 59 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 61 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 62 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN =
+ 2 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 51 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 52
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 53
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL = 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN = 2 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP = 58
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM = 59
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN =
+ 3 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_LANE_INVALID = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_PDWN_LITE = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL =
+ 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL =
+ 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL
+ = 50 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL =
+ 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL =
+ 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL
+ = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL
+ = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL =
+ 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
+ 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL = 59 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL =
+ 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN
+ = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL =
+ 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_E_PL_A_H2E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_E_PL_A_H2O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_E_PL_A_H3E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_E_PL_A_H3O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL3_E_PL_A_H4E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL3_E_PL_A_H4O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_E_PL_A_H5E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_E_PL_A_H5O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_E_PL_A_H6_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_E_PL_A_H7_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL6_E_PL_A_H8_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL6_E_PL_A_H9_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL7_E_PL_A_H10_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL7_E_PL_A_H11_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL8_E_PL_A_H12_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL9_E_PL_A_H1CAL_EN = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_FIR_MASK_PL_ERRS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_FIR_MASK_PL_ERRS_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL
+ = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL
+ = 52 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 53 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 57 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 59 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 61 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 62 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN =
+ 2 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 51 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 52
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 53
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL = 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN = 2 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP = 58
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM = 59
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN =
+ 3 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_LANE_INVALID = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_PDWN_LITE = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE3_EO_PL_BER_CFG = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE3_EO_PL_DDC_CFG = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL =
+ 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL =
+ 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL
+ = 50 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL =
+ 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL =
+ 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL
+ = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL
+ = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL =
+ 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
+ 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL = 59 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL =
+ 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN
+ = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL =
+ 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL1_E_PL_A_H2E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL1_E_PL_A_H2O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL2_E_PL_A_H3E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL2_E_PL_A_H3O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL3_E_PL_A_H4E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL3_E_PL_A_H4O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL4_E_PL_A_H5E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL4_E_PL_A_H5O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL5_E_PL_A_H6_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL5_E_PL_A_H7_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL6_E_PL_A_H8_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL6_E_PL_A_H9_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL7_E_PL_A_H10_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL7_E_PL_A_H11_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL8_E_PL_A_H12_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL9_E_PL_A_H1CAL_EN = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DATA_DAC_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DATA_DAC_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DATA_DAC_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DATA_DAC_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DATA_DAC_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DATA_DAC_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DATA_DAC_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_DATA_DAC_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_FIR_MASK_PL_ERRS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_FIR_MASK_PL_ERRS_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE4_RX_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL
+ = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL
+ = 52 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 53 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 57 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 59 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 61 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 62 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN =
+ 2 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 51 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 52
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 53
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL = 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN = 2 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP = 58
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM = 59
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN =
+ 3 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_LANE_INVALID = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_PDWN_LITE = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE3_EO_PL_BER_CFG = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE3_EO_PL_DDC_CFG = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL =
+ 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL =
+ 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL
+ = 50 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL =
+ 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL =
+ 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL
+ = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL
+ = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL =
+ 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
+ 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL = 59 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL =
+ 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN
+ = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL =
+ 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL1_E_PL_A_H2E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL1_E_PL_A_H2O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL2_E_PL_A_H3E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL2_E_PL_A_H3O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL3_E_PL_A_H4E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL3_E_PL_A_H4O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL4_E_PL_A_H5E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL4_E_PL_A_H5O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL5_E_PL_A_H6_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL5_E_PL_A_H7_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL6_E_PL_A_H8_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL6_E_PL_A_H9_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL7_E_PL_A_H10_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL7_E_PL_A_H11_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL8_E_PL_A_H12_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL9_E_PL_A_H1CAL_EN = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DATA_DAC_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DATA_DAC_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DATA_DAC_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DATA_DAC_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DATA_DAC_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DATA_DAC_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DATA_DAC_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_DATA_DAC_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_FIR_MASK_PL_ERRS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_FIR_MASK_PL_ERRS_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RXPACKS3_SLICE5_RX_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL10_EO_PG_BIST_PRBS_TEST_TIME = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL10_EO_PG_BIST_PRBS_TEST_TIME_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL10_EO_PG_BIST_BUS_DATA_MODE = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL10_EO_PG_BIST_PRBS_PROP_TIME = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL10_EO_PG_BIST_PRBS_PROP_TIME_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL10_EO_PG_BIST_PLL_LOCK_TIMEOUT = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL10_EO_PG_BIST_PLL_LOCK_TIMEOUT_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL11_EO_PG_DACTEST_LLMT = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL11_EO_PG_DACTEST_LLMT_LEN = 9 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL11_EO_PG_DACTEST_RESET = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL11_EO_PG_DACTEST_START = 58 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL12_EO_PG_DACTEST_HLMT = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL12_EO_PG_DACTEST_HLMT_LEN = 9 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL13_EO_PG_HIST_MIN_EYE_WIDTH_VALID = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL13_EO_PG_HIST_MIN_EYE_WIDTH_LANE = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL13_EO_PG_HIST_MIN_EYE_WIDTH_LANE_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL13_EO_PG_HIST_MIN_EYE_WIDTH = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL13_EO_PG_HIST_MIN_EYE_WIDTH_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL14_EO_PG_HIST_MIN_EYE_HEIGHT_VALID = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL14_EO_PG_HIST_MIN_EYE_HEIGHT_LANE = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL14_EO_PG_HIST_MIN_EYE_HEIGHT_LANE_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL14_EO_PG_HIST_MIN_EYE_HEIGHT = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL14_EO_PG_HIST_MIN_EYE_HEIGHT_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL15_EO_PG_WTL_TEST_CLOCK = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL15_EO_PG_WTL_TEST_DATA = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL15_EO_PG_WT_BS_CLOCK_EN_BYP = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL15_EO_PG_WT_BS_DATA_EN_BYP = 51 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL1_EO_PG_BER_EN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL1_EO_PG_BER_TIMER_FREEZE_EN = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL1_EO_PG_BER_COUNT_FREEZE_EN = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL1_EO_PG_BER_COUNT_SEL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL1_EO_PG_BER_COUNT_SEL_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL1_EO_PG_BER_TIMER_SEL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL1_EO_PG_BER_TIMER_SEL_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL1_EO_PG_BER_CLR_COUNT_ON_READ_EN = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL1_EO_PG_BER_CLR_TIMER_ON_READ_EN = 60 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL1_E_PG_START_WIRETEST = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL1_E_PG_START_DESKEW = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL1_E_PG_START_EYE_OPT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL1_E_PG_START_REPAIR = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL1_E_PG_START_FUNC_MODE = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL1_E_PG_START_DC_CALIBRATE = 53 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL2_EO_PG_TRC_MODE = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL2_EO_PG_TRC_MODE_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL3_EO_PG_INT_MODE = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL3_EO_PG_INT_MODE_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL3_EO_PG_INT_CURRENT_STATE = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL3_EO_PG_INT_CURRENT_STATE_LEN = 12 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL4_EO_PG_INT_ENABLE_ENC = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL4_EO_PG_INT_ENABLE_ENC_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL4_EO_PG_INT_NEXT_STATE = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL4_EO_PG_INT_NEXT_STATE_LEN = 12 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL4_E_PG_WT_CU_PLL_PGOOD = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL4_E_PG_WT_CU_BYP_PLL_LOCK = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL4_E_PG_WT_PLL_REFCLKSEL = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL4_E_PG_PLL_REFCLKSEL_SCOM_EN = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL4_E_PG_IORESET = 52 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL5_EO_PG_INT_GOTO_STATE = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL5_EO_PG_INT_GOTO_STATE_LEN = 12 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL6_EO_PG_INT_RETURN_STATE = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL6_EO_PG_INT_RETURN_STATE_LEN = 12 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL8_EO_PG_SERVO_OP = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL8_EO_PG_SERVO_OP_LEN = 15 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL8_EO_PG_SERVO_DONE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL9_EO_PG_BIST_EN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL9_EO_PG_BIST_EXT_START_MODE = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL9_EO_PG_BIST_INIT_DISABLE = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL9_EO_PG_BIST_INIT_DISABLE_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL9_EO_PG_BIST_CUPLL_LOCK_CHECK_EN = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL9_EO_PG_BIST_STORE_EYES_LANE_SEL = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL9_EO_PG_BIST_STORE_EYES_LANE_SEL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL9_EO_PG_BIST_STORE_EYES_BANK_SEL = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL9_EO_PG_BIST_STORE_EYES_BANK_SEL_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTL9_EO_PG_PERVASIVE_CAPT = 62 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTLX11_E_PG_DESKEW_SEQ_GCRMSG = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTLX11_E_PG_DESKEW_SEQ_GCRMSG_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTLX11_E_PG_DESKEW_SKMIN_GCRMSG = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTLX11_E_PG_DESKEW_SKMIN_GCRMSG_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTLX11_E_PG_DESKEW_SKMAX_GCRMSG = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTLX11_E_PG_DESKEW_SKMAX_GCRMSG_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTLX7_EO_PG_CAL_LANE_GCRMSG = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTLX7_EO_PG_CAL_LANE_GCRMSG_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTLX7_EO_PG_CAL_LANE_VAL_GCRMSG = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTLX7_EO_PG_CAL_LANE_PHY_GCRMSG = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_CNTLX7_EO_PG_CAL_LANE_PHY_GCRMSG_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE10_EO_PG_AMP_INIT_CFG = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE10_EO_PG_AMP_INIT_CFG_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE10_EO_PG_AMP_RECAL_CFG = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE10_EO_PG_AMP_RECAL_CFG_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE10_EO_PG_PEAK_INIT_CFG = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE10_EO_PG_PEAK_INIT_CFG_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE10_EO_PG_PEAK_RECAL_CFG = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE10_EO_PG_PEAK_RECAL_CFG_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE10_EO_PG_AMP_CFG = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE10_EO_PG_AMP_CFG_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE10_E_PG_DESKEW_MAX_LIMIT = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE10_E_PG_DESKEW_MAX_LIMIT_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE11_EO_PG_OFF_INIT_CFG = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE11_EO_PG_OFF_INIT_CFG_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE11_EO_PG_OFF_RECAL_CFG = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE11_EO_PG_OFF_RECAL_CFG_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE11_EO_PG_CM_CFG = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE11_EO_PG_CM_CFG_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE11_EO_PG_AMIN_CFG = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE11_EO_PG_AMIN_CFG_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE11_EO_PG_USERDEF_CFG = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE11_EO_PG_USERDEF_CFG_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE11_E_PG_LANE_DISABLED_VEC_0_15 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE11_E_PG_LANE_DISABLED_VEC_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE12_EO_PG_SERVO_CHG_CFG = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE12_EO_PG_SERVO_CHG_CFG_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE12_EO_PG_DAC_BO_CFG = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE12_EO_PG_DAC_BO_CFG_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE12_EO_PG_FILTER_MODE = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE12_EO_PG_FILTER_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE12_EO_PG_MISC_CFG = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE12_EO_PG_MISC_CFG_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE12_EO_PG_DISABLE_H1_CLEAR = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE12_EO_PG_VOFF_CFG = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE12_EO_PG_VOFF_CFG_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE12_EO_PG_LOFF_AMP_EN = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE12_E_PG_LANE_DISABLED_VEC_16_23 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE12_E_PG_LANE_DISABLED_VEC_16_23_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE13_EO_PG_CM_OFFSET_VAL = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE13_EO_PG_CM_OFFSET_VAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE13_EO_PG_SERVO_THRESH1 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE13_EO_PG_SERVO_THRESH1_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE13_EO_PG_SERVO_THRESH2 = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE13_EO_PG_SERVO_THRESH2_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE14_EO_PG_AMP_INIT_TIMEOUT = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE14_EO_PG_AMP_INIT_TIMEOUT_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE14_EO_PG_AMP_RECAL_TIMEOUT = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE14_EO_PG_AMP_RECAL_TIMEOUT_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE14_EO_PG_PEAK_INIT_TIMEOUT = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE14_EO_PG_PEAK_INIT_TIMEOUT_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE14_EO_PG_PEAK_RECAL_TIMEOUT = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE14_EO_PG_PEAK_RECAL_TIMEOUT_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE15_EO_PG_OFF_INIT_TIMEOUT = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE15_EO_PG_OFF_INIT_TIMEOUT_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE15_EO_PG_OFF_RECAL_TIMEOUT = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE15_EO_PG_OFF_RECAL_TIMEOUT_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE15_EO_PG_CM_TIMEOUT = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE15_EO_PG_CM_TIMEOUT_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE15_EO_PG_AMIN_TIMEOUT = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE15_EO_PG_AMIN_TIMEOUT_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE16_EO_PG_AMP_TIMEOUT = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE16_EO_PG_AMP_TIMEOUT_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE16_EO_PG_USERDEF_TIMEOUT = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE16_EO_PG_USERDEF_TIMEOUT_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE16_EO_PG_BER_TIMEOUT = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE16_EO_PG_BER_TIMEOUT_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE16_EO_PG_SPARE4_TIMEOUT = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE16_EO_PG_SPARE4_TIMEOUT_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE17_EO_PG_AMAX_HIGH = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE17_EO_PG_AMAX_HIGH_LEN = 8 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE17_EO_PG_AMAX_LOW = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE17_EO_PG_AMAX_LOW_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE18_EO_PG_AMP0_FILTER_MASK = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE18_EO_PG_AMP0_FILTER_MASK_LEN = 8 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE18_EO_PG_AMP1_FILTER_MASK = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE18_EO_PG_AMP1_FILTER_MASK_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE19_EO_PG_CTLE_GAIN_MAX = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE19_EO_PG_CTLE_GAIN_MAX_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE19_EO_PG_AMP_START_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE19_EO_PG_AMP_START_VAL_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE1_EO_PG_CLKDIST_PDWN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE1_EO_PG_BIST_MIN_EYE_WIDTH = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE1_EO_PG_BIST_MIN_EYE_WIDTH_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE1_EO_PG_A_BIST_EN = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE1_E_PG_MASTER_MODE = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE1_E_PG_DISABLE_FENCE_RESET = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE1_E_PG_FENCE = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE1_E_PG_PDWN_LITE_DISABLE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE1_E_PG_USE_SLS_AS_SPR = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE1_E_PG_DYN_RECAL_SUSPEND = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE1_E_PG_WT_PATTERN_LENGTH = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE1_E_PG_WT_PATTERN_LENGTH_LEN = 2 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE20_EO_PG_DFE_CONVERGED_CNT_MAX = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE20_EO_PG_DFE_CONVERGED_CNT_MAX_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE20_EO_PG_AP110_AP010_DELTA_MAX = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE20_EO_PG_AP110_AP010_DELTA_MAX_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE21_EO_PG_ENABLE_INTEG_LATCH_OFFSET_CAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE21_EO_PG_ENABLE_CTLE_COARSE_CAL = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE21_EO_PG_ENABLE_DAC_H1_CAL = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE21_EO_PG_ENABLE_VGA_CAL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE21_EO_PG_ENABLE_DFE_H1_CAL = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE21_EO_PG_ENABLE_H1AP_TWEAK = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE21_EO_PG_ENABLE_DDC = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE21_EO_PG_ENABLE_CM_COARSE_CAL = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE21_EO_PG_ENABLE_CM_FINE_CAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE21_EO_PG_ENABLE_BER_TEST = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE21_EO_PG_ENABLE_RESULT_CHECK = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE21_EO_PG_ENABLE_CTLE_EDGE_TRACK_ONLY = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE21_EO_PG_ENABLE_DFE_H2_H12_CAL = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE21_EO_PG_ENABLE_DAC_H1_TO_A_CAL = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE21_EO_PG_ENABLE_FINAL_L2U_ADJ = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE21_EO_PG_ENABLE_DONE_SIGNALING = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_INTEG_LATCH_OFFSET_CAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_CTLE_COARSE_CAL = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_DAC_H1_CAL = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_VGA_CAL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_DFE_H1_CAL = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_H1AP_TWEAK = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_DDC = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_CM_COARSE_CAL = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_CM_FINE_CAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_BER_TEST = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_RESULT_CHECK = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_CTLE_EDGE_TRACK_ONLY = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_DFE_H2_H12_CAL = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_DAC_H1_TO_A_CAL = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE23_EO_PG_QUAD_SEL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE23_EO_PG_QUAD_SEL_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE23_EO_PG_PEAK_TUNE = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE23_EO_PG_LTE_EN = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE23_EO_PG_IQSPD_CFG = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE23_EO_PG_IQSPD_CFG_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE23_EO_PG_DFEHISPD_EN = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE23_EO_PG_DFE12_EN = 60 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE24_EO_PG_H1AP_CFG = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE24_EO_PG_H1AP_CFG_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE24_EO_PG_CTLE_UPDATE_MODE = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE24_EO_PG_USER_FILTER_MASK = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE24_EO_PG_USER_FILTER_MASK_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE26_EO_PG_ENABLE_CTLE_1ST_LATCH_OFFSET_CAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE26_EO_PG_ENABLE_CTLE_2ND_LATCH_OFFSET_CAL = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE26_EO_PG_ENABLE_VGA_AMAX_MODE = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE26_EO_PG_ENABLE_DFE_H2_H12_SUBSTEP = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE26_EO_PG_ENABLE_DFE_H2_H12_SUBSTEP_LEN = 11 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE26_EO_PG_ENABLE_DFE_VOLTAGE_MODE = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE26_EO_PG_ENABLE_DFE_H6_H12_FAST_MODE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE27_EO_PG_RC_ENABLE_CTLE_1ST_LATCH_OFFSET_CAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE27_EO_PG_RC_ENABLE_CTLE_2ND_LATCH_OFFSET_CAL = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE27_EO_PG_RC_ENABLE_VGA_AMAX_MODE = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE27_EO_PG_RC_ENABLE_DFE_H2_H12_SUBSTEP = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE27_EO_PG_RC_ENABLE_DFE_H2_H12_SUBSTEP_LEN = 11 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE27_EO_PG_RC_ENABLE_DFE_VOLTAGE_MODE = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE27_EO_PG_RC_ENABLE_DFE_H6_H12_FAST_MODE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE28_EO_PG_DC_ENABLE_CM_COARSE_CAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE28_EO_PG_DC_ENABLE_CM_FINE_CAL = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE28_EO_PG_DC_ENABLE_CTLE_1ST_LATCH_OFFSET_CAL = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE28_EO_PG_DC_ENABLE_CTLE_2ND_LATCH_OFFSET_CAL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE28_EO_PG_DC_ENABLE_INTEG_LATCH_OFFSET_CAL = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE28_EO_PG_DC_ENABLE_DAC_H1_CAL = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE28_EO_PG_DC_ENABLE_DAC_H1_TO_A_CAL = 54 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE29_EO_PG_APX111_HIGH = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE29_EO_PG_APX111_HIGH_LEN = 8 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE29_EO_PG_APX111_LOW = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE29_EO_PG_APX111_LOW_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE2_EO_PG_DFE_CA_CFG = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE2_EO_PG_DFE_CA_CFG_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE2_EO_PG_SCOPE_CONTROL = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE2_EO_PG_SCOPE_CONTROL_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE2_EO_PG_DATA_PIPE_CLR_ON_READ_MODE = 59 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE2_E_PG_WTR_MAX_BAD_LANES = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE2_E_PG_WTR_MAX_BAD_LANES_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE2_E_PG_SLS_EXTEND_SEL = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE2_E_PG_SLS_EXTEND_SEL_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE2_E_PG_DYN_RPR_ENC_BAD_DATA_LANE_SHFT_AMT = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE2_E_PG_DYN_RPR_ENC_BAD_DATA_LANE_SHFT_AMT_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE3_EO_PG_SERVO_THRESH3 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE3_EO_PG_SERVO_THRESH3_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE3_EO_PG_DFE_HTAP_CFG = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE3_EO_PG_DFE_HTAP_CFG_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE3_EO_PG_DFE_INIT_TIMEOUT = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE3_EO_PG_DFE_INIT_TIMEOUT_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE3_EO_PG_DFE_RECAL_TIMEOUT = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE3_EO_PG_DFE_RECAL_TIMEOUT_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE3_E_PG_SLS_TIMEOUT_SEL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE3_E_PG_SLS_TIMEOUT_SEL_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE3_E_PG_CL_TIMEOUT_SEL = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE3_E_PG_CL_TIMEOUT_SEL_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE3_E_PG_DS_SKEW_TIMEOUT_SEL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE3_E_PG_DS_SKEW_TIMEOUT_SEL_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE3_E_PG_DS_TIMEOUT_SEL = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE3_E_PG_DS_TIMEOUT_SEL_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE4_EO_PG_DISABLE_2TO12_CLEAR = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE4_EO_PG_PEAK_ENABLE_DAC_CFG = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE4_EO_PG_AMIN_ENABLE_HDAC = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE4_EO_PG_USE_PREV_COARSE_VAL = 51 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE4_E_PG_WT_CHECK_COUNT = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE4_E_PG_WT_CHECK_COUNT_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE4_E_PG_PGOOD_TIMEOUT_SEL = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE4_E_PG_PGOOD_TIMEOUT_SEL_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE4_E_PG_PLL_LOCK_TIMEOUT_SEL = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE4_E_PG_PLL_LOCK_TIMEOUT_SEL_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE4_E_PG_PSAVE_TIMER_WAKEUP_MODE = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE4_E_PG_PSAVE_WAKEUP_LANE0_ENABLE = 62 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE5_EO_PG_DYN_RECAL_INTERVAL_TIMEOUT_SEL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE5_EO_PG_DYN_RECAL_INTERVAL_TIMEOUT_SEL_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE5_EO_PG_DYN_RECAL_STATUS_RPT_TIMEOUT_SEL = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE5_EO_PG_DYN_RECAL_STATUS_RPT_TIMEOUT_SEL_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE5_EO_PG_TRACKING_TIMEOUT_SEL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE5_EO_PG_TRACKING_TIMEOUT_SEL_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE5_EO_PG_PUP_LITE_WAIT_SEL = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE5_EO_PG_PUP_LITE_WAIT_SEL_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE5_E_PG_FIFO_INITIAL_L2U_DLY = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE5_E_PG_FIFO_INITIAL_L2U_DLY_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE5_E_PG_FIFO_FINAL_L2U_DLY = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE5_E_PG_FIFO_FINAL_L2U_DLY_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE5_E_PG_WT_TIMEOUT_SEL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE5_E_PG_WT_TIMEOUT_SEL_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE6_EO_PG_CONVERGED_END_COUNT = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE6_EO_PG_CONVERGED_END_COUNT_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE6_EO_PG_HIST_MIN_EYE_WIDTH_MODE = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE6_EO_PG_HIST_MIN_EYE_WIDTH_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE6_EO_PG_HIST_MIN_EYE_HEIGHT_MODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE6_EO_PG_HIST_MIN_EYE_HEIGHT_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE6_EO_PG_AMP_GAIN_CNT_MAX = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE6_EO_PG_AMP_GAIN_CNT_MAX_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE6_E_PG_TX_BUS_WIDTH = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE6_E_PG_TX_BUS_WIDTH_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE6_E_PG_RX_BUS_WIDTH = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE6_E_PG_RX_BUS_WIDTH_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE7_EO_PG_ABORT_CHECK_TIMEOUT_SEL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE7_EO_PG_ABORT_CHECK_TIMEOUT_SEL_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE7_EO_PG_POLLING_TIMEOUT_SEL = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE7_EO_PG_POLLING_TIMEOUT_SEL_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE7_EO_PG_PSAVE_MODE_TIMEOUT_SEL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE7_EO_PG_PSAVE_MODE_TIMEOUT_SEL_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE7_EO_PG_DYN_RECAL_OVERALL_TIMEOUT_SEL = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE7_EO_PG_DYN_RECAL_OVERALL_TIMEOUT_SEL_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE7_E_PG_SLS_DISABLE = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE7_E_PG_TX_SLS_DISABLE = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE7_E_PG_SLS_CNTR_TAP_PTS = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE7_E_PG_SLS_CNTR_TAP_PTS_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE7_E_PG_NONSLS_CNTR_TAP_PTS = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE7_E_PG_NONSLS_CNTR_TAP_PTS_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE7_E_PG_SLS_EXCEPTION2_CS = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE7_E_PG_DYN_RPR_ERR_CNTR1_FILTER_MODE = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE7_E_PG_DYN_RPR_ERR_CNTR1_FILTER_MODE_LEN = 2 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE8_EO_PG_MAX_BER_CHECK_COUNT = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE8_EO_PG_MAX_BER_CHECK_COUNT_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE8_E_PG_DYN_RPR_BAD_LANE_MAX = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE8_E_PG_DYN_RPR_BAD_LANE_MAX_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE8_E_PG_DYN_RPR_ERR_CNTR1_DURATION = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE8_E_PG_DYN_RPR_ERR_CNTR1_DURATION_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE8_E_PG_DYN_RPR_CLR_ERR_CNTR1 = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE8_E_PG_DYN_RPR_DISABLE = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE8_E_PG_DYN_RPR_ENC_BAD_DATA_LANE_WIDTH = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE8_E_PG_DYN_RPR_ENC_BAD_DATA_LANE_WIDTH_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE9_EO_PG_MIN_EYE_WIDTH = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE9_EO_PG_MIN_EYE_WIDTH_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE9_EO_PG_MIN_EYE_HEIGHT = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE9_EO_PG_MIN_EYE_HEIGHT_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE9_E_PG_DYN_RPR_BAD_BUS_MAX = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE9_E_PG_DYN_RPR_BAD_BUS_MAX_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE9_E_PG_DYN_RPR_ERR_CNTR2_DURATION = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE9_E_PG_DYN_RPR_ERR_CNTR2_DURATION_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE9_E_PG_DYN_RPR_CLR_ERR_CNTR2 = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_MODE9_E_PG_DYN_RPR_DISABLE2 = 60 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT1_EO_PG_SERVO_RESULT = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT1_EO_PG_SERVO_RESULT_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT1_E_PG_WIRETEST_DONE = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT1_E_PG_DESKEW_DONE = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT1_E_PG_EYE_OPT_DONE = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT1_E_PG_REPAIR_DONE = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT1_E_PG_FUNC_MODE_DONE = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT1_E_PG_DC_CALIBRATE_DONE = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT1_E_PG_WIRETEST_FAILED = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT1_E_PG_DESKEW_FAILED = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT1_E_PG_EYE_OPT_FAILED = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT1_E_PG_REPAIR_FAILED = 59 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT2_EO_PG_BIST_INIT_DONE = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT2_EO_PG_BIST_DONE = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT2_EO_PG_BIST_CU_PLL_ERR = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT2_EO_PG_BIST_NO_EDGE_DET = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT2_EO_PG_BIST_EYE_A_WIDTH = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT2_EO_PG_BIST_EYE_A_WIDTH_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT2_EO_PG_BIST_EYE_B_WIDTH = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT2_EO_PG_BIST_EYE_B_WIDTH_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT2_E_PG_LANE_BAD_VEC_0_15 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT2_E_PG_LANE_BAD_VEC_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT3_EO_PG_WTL_SM_STATUS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT3_EO_PG_WTL_SM_STATUS_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT4_E_PG_LANE_BAD_VEC_16_23 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT4_E_PG_LANE_BAD_VEC_16_23_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT5_E_PG_WT_CLK_LANE_INVERTED = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT5_E_PG_WT_CLK_LANE_BAD_CODE = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT5_E_PG_WT_CLK_LANE_BAD_CODE_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT6_E_PG_DESKEW_MINSKEW_GRP = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT6_E_PG_DESKEW_MINSKEW_GRP_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT6_E_PG_DESKEW_MAXSKEW_GRP = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STAT6_E_PG_DESKEW_MAXSKEW_GRP_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STATX8_E_PG_WT_PREV_DONE_GCRMSG = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STATX8_E_PG_WT_ALL_DONE_GCRMSG = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_CTL_STATX8_E_PG_CNTLS_PREV_LDED_GCRMSG = 52 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_CNTL1_E_PG_PRBS_SCRAMBLE_MODE = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_CNTL1_E_PG_PRBS_SCRAMBLE_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_CNTL1_E_PG_PRBS_SEED_MODE = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_CNTL1_E_PG_DESKEW_RATE = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_CNTL1_E_PG_RUN_DYN_RECAL_TIMER = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_CNTL1_E_PG_DESKEW_PATTCHK_TIMEOUT_SEL = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_CNTL1_E_PG_DESKEW_PATTCHK_TIMEOUT_SEL_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_CNTL1_E_PG_PRBS_SLS_EXPECT = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_CNTL1_E_PG_PRBS_SLS_EXPECT_LEN = 8 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_CNTL1_E_PG_HALF_RATE_MODE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_CNTL2_EO_PG_POFF_EOFF_TIMEOUT = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_CNTL2_EO_PG_POFF_EOFF_TIMEOUT_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_CNTL2_EO_PG_POFF_EOFF_CFG = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_CNTL2_EO_PG_POFF_EOFF_CFG_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_CNTL2_EO_PG_POFF_EOFF_BLOCK_ERROR = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_CNTL2_EO_PG_FILTER_OPTIONS = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_CNTL2_EO_PG_FILTER_OPTIONS_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_CNTLX1_EO_PG_RX_BER_COUNT_CLR_WO_PULSE_SLOW_SIGNAL = 49
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_CNTLX1_EO_PG_RX_BER_TIMER_CLR_WO_PULSE_SLOW_SIGNAL = 50
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_CNTLX1_EO_PG_RX_SCOPE_CAPTURE_WO_PULSE_SLOW_SIGNAL = 51
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_CNTLX1_EO_PG_RX_DATA_PIPE_CAPTURE_WO_PULSE_SLOW_SIGNAL =
+ 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_CNTLX1_EO_PG_RX_RESET_SERVO_STATUS_WO_PULSE_SLOW_SIGNAL
+ = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_CNTLX1_EO_PG_RX_BER_RESET_WO_PULSE_SLOW_SIGNAL = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_CNTLX1_EO_PG_RX_REPAIR_COMP_WO_PULSE_SLOW_SIGNAL = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_SPARE_MODE_PG_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_SPARE_MODE_PG_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_SPARE_MODE_PG_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_SPARE_MODE_PG_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_SPARE_MODE_PG_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_SPARE_MODE_PG_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_SPARE_MODE_PG_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_SPARE_MODE_PG_7 = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_SPARE_MODE_PG_SERVO_CONFIG = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_SPARE_MODE_PG_SERVO_CONFIG_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_SPARE_MODE_PG_CTL_CLKDIST_PDWN = 60 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT10_EO_PG_RX_SCAN_N_16_23_RO_SIGNAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT10_EO_PG_RX_SCAN_N_16_23_RO_SIGNAL_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT11_EO_PG_RX_SCAN_N_0_15_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT11_EO_PG_RX_SCAN_N_0_15_RO_SIGNAL_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT12_EO_PG_RX_SERVO_STATUS2_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT12_EO_PG_RX_SERVO_STATUS2_RO_SIGNAL_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT13_E_PG_BAD_BUS_LANE_ERR_CNTR_DIS_CLR = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT13_E_PG_RX_BAD_BUS_LANE_ERR_CNTR_RO_SIGNAL = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT13_E_PG_RX_BAD_BUS_LANE_ERR_CNTR_RO_SIGNAL_LEN = 7
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT13_E_PG_RX_LAST_BAD_BUS_LANE_RO_SIGNAL = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT13_E_PG_RX_LAST_BAD_BUS_LANE_RO_SIGNAL_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT1_EO_PG_RX_BER_COUNT_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT1_EO_PG_RX_BER_COUNT_RO_SIGNAL_LEN = 11 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT1_EO_PG_RX_BER_COUNT_SATURATED_RO_SIGNAL = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT1_EO_PG_RX_BER_COUNT_FROZEN_BY_ERR_CNT_RO_SIGNAL =
+ 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT1_EO_PG_RX_BER_COUNT_FROZEN_BY_TIMER_RO_SIGNAL = 61
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT1_EO_PG_RX_BER_TIMER_SATURATED_RO_SIGNAL = 62 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT2_EO_PG_RX_BER_TIMER_VALUE_0_15_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT2_EO_PG_RX_BER_TIMER_VALUE_0_15_RO_SIGNAL_LEN = 16
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT3_EO_PG_RX_BER_TIMER_VALUE_16_31_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT3_EO_PG_RX_BER_TIMER_VALUE_16_31_RO_SIGNAL_LEN = 16
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT4_EO_PG_RX_DATA_PIPE_0_15_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT4_EO_PG_RX_DATA_PIPE_0_15_RO_SIGNAL_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT5_EO_PG_RX_DATA_PIPE_16_31_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT5_EO_PG_RX_DATA_PIPE_16_31_RO_SIGNAL_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT6_EO_PG_RX_SERVO_STATUS_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT6_EO_PG_RX_SERVO_STATUS_RO_SIGNAL_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT7_EO_PG_RX_SERVO_CHG_CNT_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT7_EO_PG_RX_SERVO_CHG_CNT_RO_SIGNAL_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT7_EO_PG_RX_PRBS_DATA_RCV_RO_SIGNAL = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT7_EO_PG_RX_PG_PRBS_SEED_DONE_RO_SIGNAL = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT7_EO_PG_RX_DYN_RECAL_TIMER_RUNNING_RO_SIGNAL = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT7_EO_PG_RX_PRVCPT_CHANGE_DET_RO_SIGNAL = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT8_EO_PG_RX_SCAN_P_0_15_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT8_EO_PG_RX_SCAN_P_0_15_RO_SIGNAL_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT9_EO_PG_RX_SCAN_P_16_23_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_DATASM_STAT9_EO_PG_RX_SCAN_P_16_23_RO_SIGNAL_LEN = 9 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR1_ERROR_INJECT_PG_ERR_INJ = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR1_ERROR_INJECT_PG_ERR_INJ_LEN = 15 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR1_MASK_PG_ERRS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR1_MASK_PG_ERRS_LEN = 15 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_PG_REGS_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_GCR_BUFF_RO_SIGNAL = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_GCRS_LD_SM_RO_SIGNAL = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_GCRS_UNLD_SM_RO_SIGNAL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_GLBSM_REGS_RO_SIGNAL = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_GLBSM_REGRW_RO_SIGNAL = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_DATASM_REGS_RO_SIGNAL = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_DATASM_REGRW_RO_SIGNAL = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_EYEOPT_SM_RO_SIGNAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_BIST_MAIN_STATE_RO_SIGNAL = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_BIST_INIT_STATE_RO_SIGNAL = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_RX_SERVO_SM_RO_SIGNAL = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_WORK_REGS_RO_SIGNAL = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR1_PG_RX_PG_FIR_ERR_SET_SLS_LN_STATE_RO_SIGNAL = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR1_PG_RX_PL_FIR_ERR_RO_SIGNAL = 62 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR2_ERROR_INJECT_PG_ERR_INJ = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR2_ERROR_INJECT_PG_ERR_INJ_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR2_MASK_PG_ERRS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR2_MASK_PG_ERRS_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR2_PG_RX_PG_FIR_ERR_DYN_RPR_SM_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR2_PG_RX_PG_FIR_ERR_DYN_RPR_SND_MSG_SM_RO_SIGNAL = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR2_PG_RX_PG_FIR_ERR_SLS_ENC_SND_MSG_SM_RO_SIGNAL = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR2_PG_RX_PG_FIR_ERR_SLS_HNDSHK_SM_RO_SIGNAL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR2_PG_RX_PG_FIR_ERR_SLS_RCVY_SM_RO_SIGNAL = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR2_PG_RX_PG_FIR_ERR_RECAL_SM_RO_SIGNAL = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR2_PG_RX_PG_FIR_ERR_DYN_RECAL_HNDSHK_SM_RO_SIGNAL = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR2_PG_RX_PG_FIR_ERR_GLB_CAL_SND_MSG_SM_RO_SIGNAL = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR2_PG_RX_PG_FIR_ERR_STAT_RPR_SND_MSG_SM_RO_SIGNAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR2_PG_RX_PG_FIR_ERR_MAIN_INIT_SM_RO_SIGNAL = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR2_PG_RX_PG_FIR_ERR_WTM_SM_RO_SIGNAL = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR2_PG_RX_PG_FIR_ERR_WTR_SM_RO_SIGNAL = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR2_PG_RX_PG_FIR_ERR_WTL_SM_RO_SIGNAL = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR2_PG_RX_PG_FIR_ERR_RPR_SM_RO_SIGNAL = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR2_PG_RX_PG_FIR_ERR_DSM_SM_RO_SIGNAL = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR2_PG_RX_PG_FIR_ERR_RXDSM_SM_RO_SIGNAL = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR_TRAINING_MASK_PG_ERROR = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR_TRAINING_MASK_PG_STATIC_SPARE_DEPLOYED = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR_TRAINING_MASK_PG_STATIC_MAX_SPARES_EXCEEDED = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR_TRAINING_MASK_PG_DYNAMIC_REPAIR_ERROR = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR_TRAINING_MASK_PG_DYNAMIC_SPARE_DEPLOYED = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR_TRAINING_MASK_PG_DYNAMIC_MAX_SPARES_EXCEEDED = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR_TRAINING_MASK_PG_RECAL_ERROR = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR_TRAINING_MASK_PG_RECAL_SPARE_DEPLOYED = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR_TRAINING_MASK_PG_RECAL_MAX_SPARES_EXCEEDED = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR_TRAINING_MASK_PG_TOO_MANY_BUS_ERRORS = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR_TRAINING_PG_ERROR = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR_TRAINING_PG_STATIC_SPARE_DEPLOYED = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR_TRAINING_PG_STATIC_MAX_SPARES_EXCEEDED = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR_TRAINING_PG_DYNAMIC_REPAIR_ERROR = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR_TRAINING_PG_DYNAMIC_SPARE_DEPLOYED = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR_TRAINING_PG_DYNAMIC_MAX_SPARES_EXCEEDED = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR_TRAINING_PG_RECAL_ERROR = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR_TRAINING_PG_RECAL_SPARE_DEPLOYED = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR_TRAINING_PG_RECAL_MAX_SPARES_EXCEEDED = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_FIR_TRAINING_PG_TOO_MANY_BUS_ERRORS = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_CNTL2_EO_PG_DYN_RPR_REQ_MANUAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_CNTL2_EO_PG_CNT_SINGLE_LANE_RECAL = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_CNTL2_EO_PG_RECAL_LANE_TO_MONITOR = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_CNTL2_EO_PG_RECAL_LANE_TO_MONITOR_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_CNTL2_EO_PG_DYN_RPR_SM_MANUAL = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_CNTL2_EO_PG_DIS_SYND_TALLYING = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_CNTL2_EO_PG_ENC_BUS_LANE2RPR_MANUAL = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_CNTL2_EO_PG_ENC_BUS_LANE2RPR_MANUAL_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_CNTL3_EO_PG_MANUAL_RECAL_REQUEST = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_CNTL3_EO_PG_MANUAL_RECAL_LANE = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_CNTL3_EO_PG_MANUAL_RECAL_LANE_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_CNTL3_EO_PG_SLS_TIMEOUT_EXT_SEL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_CNTL3_EO_PG_SLS_TIMEOUT_EXT_SEL_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_CNTL3_EO_PG_HALF_RATE_MODE = 58 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_CNTL4_EO_PG_RX_CLR_RECAL_CNT_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_CNTL4_EO_PG_RX_INT_RETURN_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_CNTL4_EO_PG_RX_MANUAL_RECAL_ABORT_WO_PULSE_SLOW_SIGNAL =
+ 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_CNTL4_EO_PG_RX_MANUAL_RECAL_CONTINUE_WO_PULSE_SLOW_SIGNAL
+ = 51 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_CNTLX1_EO_PG_CLR_PAR_ERRS = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_CNTLX1_EO_PG_FIR_RESET = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_MODE1_EO_PG_RPR_TX_LD_CNTLS_TIMEOUT_SEL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_MODE1_EO_PG_RPR_TX_LD_CNTLS_TIMEOUT_SEL_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_MODE1_EO_PG_TX_SLS_LN_MV_TIMEOUT_SEL = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_MODE1_EO_PG_TX_SLS_LN_MV_TIMEOUT_SEL_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_MODE1_EO_PG_DESKEW_SKIP_OFFSET = 56 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_SPARE_MODE_PG_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_SPARE_MODE_PG_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_SPARE_MODE_PG_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_SPARE_MODE_PG_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_SPARE_MODE_PG_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_SPARE_MODE_PG_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_SPARE_MODE_PG_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_SPARE_MODE_PG_7 = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_SPARE_MODE_PG_DESKEW_BUMP_AFTER = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_SPARE_MODE_PG_SLS_RCVY_DISABLE = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_SPARE_MODE_PG_SLS_HNDSHK_DISABLE = 58 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT10_E_PG_SERVO_RECAL_IP = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT10_E_PG_RX_DYN_RECAL_MAIN_STATE_RO_SIGNAL = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT10_E_PG_RX_DYN_RECAL_MAIN_STATE_RO_SIGNAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT10_E_PG_RX_DYN_RECAL_HNDSHK_STATE_RO_SIGNAL = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT10_E_PG_RX_DYN_RECAL_HNDSHK_STATE_RO_SIGNAL_LEN = 7
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT11_E_PG_SLS_CMD_VAL_HLD = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT11_E_PG_SLS_CMD_ENCODE_HLD = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT11_E_PG_SLS_CMD_ENCODE_HLD_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT1_EO_PG_RX_EYE_OPT_STATE_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT1_EO_PG_RX_EYE_OPT_STATE_RO_SIGNAL_LEN = 12 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT1_E_PG_RX_MAIN_INIT_STATE_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT1_E_PG_RX_MAIN_INIT_STATE_RO_SIGNAL_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT1_E_PG_RX_WTM_STATE_RO_SIGNAL = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT1_E_PG_RX_WTM_STATE_RO_SIGNAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT1_E_PG_RX_WTR_STATE_RO_SIGNAL = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT1_E_PG_RX_WTR_STATE_RO_SIGNAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT1_E_PG_RX_WT_CU_PLL_LOCK_RO_SIGNAL = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT2_EO_PG_RX_RECAL_CNT_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT2_EO_PG_RX_RECAL_CNT_RO_SIGNAL_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT2_E_PG_RX_WTR_CUR_LANE_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT2_E_PG_RX_WTR_CUR_LANE_RO_SIGNAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT2_E_PG_RX_WTR_BAD_LANE_COUNT_RO_SIGNAL = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT2_E_PG_RX_WTR_BAD_LANE_COUNT_RO_SIGNAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT3_EO_PG_RX_DACTEST_ISGT_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT3_EO_PG_RX_DACTEST_ISLT_RO_SIGNAL = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT3_EO_PG_RX_DACTEST_ISEQ_RO_SIGNAL = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT3_EO_PG_RX_DACTEST_DIFF_RO_SIGNAL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT3_EO_PG_RX_DACTEST_DIFF_RO_SIGNAL_LEN = 9 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT3_E_PG_RX_DSM_STATE_RO_SIGNAL = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT3_E_PG_RX_DSM_STATE_RO_SIGNAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT3_E_PG_RX_RXDSM_STATE_RO_SIGNAL = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT3_E_PG_RX_RXDSM_STATE_RO_SIGNAL_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT4_EO_PG_RX_INT_REQ_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT4_EO_PG_RX_INT_REQ_RO_SIGNAL_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT4_E_PG_RX_RPR_STATE_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT4_E_PG_RX_RPR_STATE_RO_SIGNAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT4_E_PG_RX_SLS_RCVY_STATE_RO_SIGNAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT4_E_PG_RX_SLS_RCVY_STATE_RO_SIGNAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT5_EO_PG_RX_LANE_CURRENTLY_INITIALIZING_RO_SIGNAL = 48
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT5_EO_PG_RX_LANE_CURRENTLY_RECALIBRATING_RO_SIGNAL =
+ 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT5_EO_PG_RX_CURRENT_RECAL_INIT_LANE_RO_SIGNAL = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT5_EO_PG_RX_CURRENT_RECAL_INIT_LANE_RO_SIGNAL_LEN = 5
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT5_EO_PG_RX_MANUAL_RECAL_DONE_RO_SIGNAL = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT7_E_PG_RX_SLS_CMD_VAL_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT7_E_PG_RX_NONSLS_CMD_RO_SIGNAL = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT7_E_PG_RX_SLS_CMD_ENCODE_RO_SIGNAL = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT7_E_PG_RX_SLS_CMD_ENCODE_RO_SIGNAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT7_E_PG_RX_ENC_BUS_LANE2RPR_RO_SIGNAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT7_E_PG_RX_ENC_BUS_LANE2RPR_RO_SIGNAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT7_E_PG_RX_REPAIR_REQ_RO_SIGNAL = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT8_E_PG_RX_SLS_USED_AS_SPR_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT8_E_PG_RX_DYN_RPR_STATE_RO_SIGNAL = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT8_E_PG_RX_DYN_RPR_STATE_RO_SIGNAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT8_E_PG_RX_SLS_HNDSHK_STATE_RO_SIGNAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT8_E_PG_RX_SLS_HNDSHK_STATE_RO_SIGNAL_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT9_E_PG_BAD_LANE1 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT9_E_PG_BAD_LANE1_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT9_E_PG_BAD_LANE2 = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT9_E_PG_BAD_LANE2_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT9_E_PG_BAD_LANE_CODE = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_GLBSM_STAT9_E_PG_BAD_LANE_CODE_LEN = 2 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_ID1_PG_BUS_ID = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_ID1_PG_BUS_ID_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_ID2_PG_START_LANE_ID = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_ID2_PG_START_LANE_ID_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_ID2_PG_END_LANE_ID = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_ID2_PG_END_LANE_ID_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_SPARE_MODE_PG_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_SPARE_MODE_PG_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_SPARE_MODE_PG_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_SPARE_MODE_PG_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_RX_SPARE_MODE_PG_4 = 52 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE0_RX_DATA_WORK_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE0_RX_DATA_WORK_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE0_RX_DATA_WORK_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE0_RX_DATA_WORK_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE0_RX_DATA_WORK_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE0_RX_DATA_WORK_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE0_RX_DATA_WORK_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE0_RX_DATA_WORK_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE0_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE0_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE0_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE0_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE0_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE0_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE0_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE0_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE0_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE0_RX_WORK_STAT1_EO_PL_BIST_ERR = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE0_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE0_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE0_RX_WORK_STAT2_EO_PL_A_AP = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE0_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE0_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE0_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE0_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE0_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE10_RX_DATA_WORK_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE10_RX_DATA_WORK_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE10_RX_DATA_WORK_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE10_RX_DATA_WORK_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE10_RX_DATA_WORK_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE10_RX_DATA_WORK_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE10_RX_DATA_WORK_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE10_RX_DATA_WORK_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE10_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE10_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE10_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE10_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE10_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE10_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE10_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE10_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE10_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE10_RX_WORK_STAT1_EO_PL_BIST_ERR = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE10_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE10_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE10_RX_WORK_STAT2_EO_PL_A_AP = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE10_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE10_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE10_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE10_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE10_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE11_RX_DATA_WORK_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE11_RX_DATA_WORK_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE11_RX_DATA_WORK_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE11_RX_DATA_WORK_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE11_RX_DATA_WORK_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE11_RX_DATA_WORK_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE11_RX_DATA_WORK_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE11_RX_DATA_WORK_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE11_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE11_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE11_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE11_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE11_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE11_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE11_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE11_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE11_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE11_RX_WORK_STAT1_EO_PL_BIST_ERR = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE11_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE11_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE11_RX_WORK_STAT2_EO_PL_A_AP = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE11_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE11_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE11_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE11_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE11_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE12_RX_DATA_WORK_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE12_RX_DATA_WORK_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE12_RX_DATA_WORK_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE12_RX_DATA_WORK_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE12_RX_DATA_WORK_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE12_RX_DATA_WORK_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE12_RX_DATA_WORK_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE12_RX_DATA_WORK_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE12_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE12_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE12_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE12_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE12_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE12_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE12_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE12_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE12_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE12_RX_WORK_STAT1_EO_PL_BIST_ERR = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE12_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE12_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE12_RX_WORK_STAT2_EO_PL_A_AP = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE12_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE12_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE12_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE12_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE12_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE13_RX_DATA_WORK_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE13_RX_DATA_WORK_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE13_RX_DATA_WORK_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE13_RX_DATA_WORK_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE13_RX_DATA_WORK_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE13_RX_DATA_WORK_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE13_RX_DATA_WORK_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE13_RX_DATA_WORK_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE13_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE13_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE13_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE13_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE13_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE13_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE13_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE13_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE13_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE13_RX_WORK_STAT1_EO_PL_BIST_ERR = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE13_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE13_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE13_RX_WORK_STAT2_EO_PL_A_AP = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE13_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE13_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE13_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE13_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE13_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE14_RX_DATA_WORK_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE14_RX_DATA_WORK_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE14_RX_DATA_WORK_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE14_RX_DATA_WORK_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE14_RX_DATA_WORK_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE14_RX_DATA_WORK_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE14_RX_DATA_WORK_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE14_RX_DATA_WORK_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE14_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE14_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE14_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE14_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE14_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE14_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE14_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE14_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE14_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE14_RX_WORK_STAT1_EO_PL_BIST_ERR = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE14_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE14_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE14_RX_WORK_STAT2_EO_PL_A_AP = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE14_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE14_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE14_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE14_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE14_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE15_RX_DATA_WORK_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE15_RX_DATA_WORK_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE15_RX_DATA_WORK_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE15_RX_DATA_WORK_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE15_RX_DATA_WORK_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE15_RX_DATA_WORK_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE15_RX_DATA_WORK_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE15_RX_DATA_WORK_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE15_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE15_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE15_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE15_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE15_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE15_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE15_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE15_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE15_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE15_RX_WORK_STAT1_EO_PL_BIST_ERR = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE15_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE15_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE15_RX_WORK_STAT2_EO_PL_A_AP = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE15_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE15_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE15_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE15_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE15_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE16_RX_DATA_WORK_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE16_RX_DATA_WORK_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE16_RX_DATA_WORK_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE16_RX_DATA_WORK_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE16_RX_DATA_WORK_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE16_RX_DATA_WORK_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE16_RX_DATA_WORK_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE16_RX_DATA_WORK_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE16_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE16_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE16_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE16_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE16_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE16_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE16_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE16_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE16_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE16_RX_WORK_STAT1_EO_PL_BIST_ERR = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE16_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE16_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE16_RX_WORK_STAT2_EO_PL_A_AP = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE16_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE16_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE16_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE16_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE16_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE17_RX_DATA_WORK_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE17_RX_DATA_WORK_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE17_RX_DATA_WORK_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE17_RX_DATA_WORK_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE17_RX_DATA_WORK_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE17_RX_DATA_WORK_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE17_RX_DATA_WORK_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE17_RX_DATA_WORK_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE17_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE17_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE17_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE17_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE17_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE17_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE17_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE17_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE17_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE17_RX_WORK_STAT1_EO_PL_BIST_ERR = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE17_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE17_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE17_RX_WORK_STAT2_EO_PL_A_AP = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE17_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE17_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE17_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE17_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE17_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE18_RX_DATA_WORK_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE18_RX_DATA_WORK_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE18_RX_DATA_WORK_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE18_RX_DATA_WORK_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE18_RX_DATA_WORK_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE18_RX_DATA_WORK_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE18_RX_DATA_WORK_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE18_RX_DATA_WORK_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE18_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE18_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE18_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE18_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE18_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE18_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE18_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE18_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE18_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE18_RX_WORK_STAT1_EO_PL_BIST_ERR = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE18_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE18_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE18_RX_WORK_STAT2_EO_PL_A_AP = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE18_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE18_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE18_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE18_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE18_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE19_RX_DATA_WORK_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE19_RX_DATA_WORK_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE19_RX_DATA_WORK_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE19_RX_DATA_WORK_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE19_RX_DATA_WORK_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE19_RX_DATA_WORK_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE19_RX_DATA_WORK_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE19_RX_DATA_WORK_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE19_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE19_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE19_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE19_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE19_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE19_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE19_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE19_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE19_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE19_RX_WORK_STAT1_EO_PL_BIST_ERR = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE19_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE19_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE19_RX_WORK_STAT2_EO_PL_A_AP = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE19_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE19_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE19_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE19_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE19_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE1_RX_DATA_WORK_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE1_RX_DATA_WORK_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE1_RX_DATA_WORK_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE1_RX_DATA_WORK_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE1_RX_DATA_WORK_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE1_RX_DATA_WORK_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE1_RX_DATA_WORK_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE1_RX_DATA_WORK_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE1_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE1_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE1_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE1_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE1_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE1_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE1_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE1_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE1_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE1_RX_WORK_STAT1_EO_PL_BIST_ERR = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE1_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE1_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE1_RX_WORK_STAT2_EO_PL_A_AP = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE1_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE1_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE1_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE1_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE1_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE20_RX_DATA_WORK_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE20_RX_DATA_WORK_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE20_RX_DATA_WORK_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE20_RX_DATA_WORK_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE20_RX_DATA_WORK_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE20_RX_DATA_WORK_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE20_RX_DATA_WORK_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE20_RX_DATA_WORK_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE20_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE20_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE20_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE20_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE20_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE20_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE20_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE20_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE20_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE20_RX_WORK_STAT1_EO_PL_BIST_ERR = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE20_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE20_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE20_RX_WORK_STAT2_EO_PL_A_AP = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE20_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE20_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE20_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE20_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE20_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE21_RX_DATA_WORK_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE21_RX_DATA_WORK_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE21_RX_DATA_WORK_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE21_RX_DATA_WORK_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE21_RX_DATA_WORK_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE21_RX_DATA_WORK_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE21_RX_DATA_WORK_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE21_RX_DATA_WORK_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE21_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE21_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE21_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE21_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE21_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE21_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE21_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE21_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE21_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE21_RX_WORK_STAT1_EO_PL_BIST_ERR = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE21_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE21_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE21_RX_WORK_STAT2_EO_PL_A_AP = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE21_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE21_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE21_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE21_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE21_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE22_RX_DATA_WORK_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE22_RX_DATA_WORK_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE22_RX_DATA_WORK_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE22_RX_DATA_WORK_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE22_RX_DATA_WORK_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE22_RX_DATA_WORK_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE22_RX_DATA_WORK_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE22_RX_DATA_WORK_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE22_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE22_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE22_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE22_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE22_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE22_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE22_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE22_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE22_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE22_RX_WORK_STAT1_EO_PL_BIST_ERR = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE22_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE22_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE22_RX_WORK_STAT2_EO_PL_A_AP = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE22_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE22_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE22_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE22_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE22_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE23_RX_DATA_WORK_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE23_RX_DATA_WORK_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE23_RX_DATA_WORK_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE23_RX_DATA_WORK_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE23_RX_DATA_WORK_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE23_RX_DATA_WORK_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE23_RX_DATA_WORK_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE23_RX_DATA_WORK_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE23_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE23_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE23_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE23_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE23_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE23_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE23_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE23_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE23_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE23_RX_WORK_STAT1_EO_PL_BIST_ERR = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE23_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE23_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE23_RX_WORK_STAT2_EO_PL_A_AP = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE23_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE23_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE23_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE23_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE23_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE2_RX_DATA_WORK_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE2_RX_DATA_WORK_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE2_RX_DATA_WORK_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE2_RX_DATA_WORK_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE2_RX_DATA_WORK_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE2_RX_DATA_WORK_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE2_RX_DATA_WORK_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE2_RX_DATA_WORK_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE2_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE2_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE2_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE2_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE2_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE2_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE2_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE2_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE2_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE2_RX_WORK_STAT1_EO_PL_BIST_ERR = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE2_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE2_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE2_RX_WORK_STAT2_EO_PL_A_AP = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE2_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE2_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE2_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE2_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE2_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE3_RX_DATA_WORK_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE3_RX_DATA_WORK_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE3_RX_DATA_WORK_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE3_RX_DATA_WORK_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE3_RX_DATA_WORK_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE3_RX_DATA_WORK_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE3_RX_DATA_WORK_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE3_RX_DATA_WORK_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE3_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE3_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE3_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE3_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE3_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE3_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE3_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE3_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE3_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE3_RX_WORK_STAT1_EO_PL_BIST_ERR = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE3_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE3_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE3_RX_WORK_STAT2_EO_PL_A_AP = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE3_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE3_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE3_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE3_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE3_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE4_RX_DATA_WORK_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE4_RX_DATA_WORK_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE4_RX_DATA_WORK_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE4_RX_DATA_WORK_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE4_RX_DATA_WORK_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE4_RX_DATA_WORK_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE4_RX_DATA_WORK_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE4_RX_DATA_WORK_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE4_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE4_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE4_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE4_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE4_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE4_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE4_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE4_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE4_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE4_RX_WORK_STAT1_EO_PL_BIST_ERR = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE4_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE4_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE4_RX_WORK_STAT2_EO_PL_A_AP = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE4_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE4_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE4_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE4_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE4_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE5_RX_DATA_WORK_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE5_RX_DATA_WORK_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE5_RX_DATA_WORK_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE5_RX_DATA_WORK_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE5_RX_DATA_WORK_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE5_RX_DATA_WORK_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE5_RX_DATA_WORK_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE5_RX_DATA_WORK_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE5_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE5_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE5_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE5_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE5_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE5_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE5_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE5_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE5_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE5_RX_WORK_STAT1_EO_PL_BIST_ERR = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE5_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE5_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE5_RX_WORK_STAT2_EO_PL_A_AP = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE5_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE5_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE5_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE5_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE5_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE6_RX_DATA_WORK_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE6_RX_DATA_WORK_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE6_RX_DATA_WORK_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE6_RX_DATA_WORK_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE6_RX_DATA_WORK_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE6_RX_DATA_WORK_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE6_RX_DATA_WORK_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE6_RX_DATA_WORK_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE6_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE6_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE6_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE6_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE6_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE6_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE6_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE6_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE6_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE6_RX_WORK_STAT1_EO_PL_BIST_ERR = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE6_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE6_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE6_RX_WORK_STAT2_EO_PL_A_AP = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE6_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE6_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE6_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE6_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE6_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE7_RX_DATA_WORK_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE7_RX_DATA_WORK_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE7_RX_DATA_WORK_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE7_RX_DATA_WORK_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE7_RX_DATA_WORK_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE7_RX_DATA_WORK_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE7_RX_DATA_WORK_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE7_RX_DATA_WORK_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE7_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE7_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE7_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE7_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE7_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE7_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE7_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE7_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE7_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE7_RX_WORK_STAT1_EO_PL_BIST_ERR = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE7_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE7_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE7_RX_WORK_STAT2_EO_PL_A_AP = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE7_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE7_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE7_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE7_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE7_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE8_RX_DATA_WORK_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE8_RX_DATA_WORK_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE8_RX_DATA_WORK_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE8_RX_DATA_WORK_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE8_RX_DATA_WORK_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE8_RX_DATA_WORK_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE8_RX_DATA_WORK_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE8_RX_DATA_WORK_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE8_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE8_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE8_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE8_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE8_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE8_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE8_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE8_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE8_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE8_RX_WORK_STAT1_EO_PL_BIST_ERR = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE8_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE8_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE8_RX_WORK_STAT2_EO_PL_A_AP = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE8_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE8_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE8_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE8_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE8_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE9_RX_DATA_WORK_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE9_RX_DATA_WORK_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE9_RX_DATA_WORK_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE9_RX_DATA_WORK_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE9_RX_DATA_WORK_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE9_RX_DATA_WORK_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE9_RX_DATA_WORK_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE9_RX_DATA_WORK_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE9_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE9_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE9_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE9_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE9_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE9_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE9_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE9_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE9_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE9_RX_WORK_STAT1_EO_PL_BIST_ERR = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE9_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE9_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE9_RX_WORK_STAT2_EO_PL_A_AP = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE9_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE9_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE9_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE9_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX0_SLICE9_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL
+ = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL
+ = 52 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 53 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 57 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 59 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 61 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 62 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN =
+ 2 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 51 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 52
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 53
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL = 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN = 2 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP = 58
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM = 59
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN =
+ 3 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_LANE_INVALID = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_PDWN_LITE = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL =
+ 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL =
+ 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL
+ = 50 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL =
+ 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL =
+ 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL
+ = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL
+ = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL =
+ 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
+ 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL = 59 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL =
+ 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN
+ = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL =
+ 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL1_E_PL_A_H2E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL1_E_PL_A_H2O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL2_E_PL_A_H3E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL2_E_PL_A_H3O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL3_E_PL_A_H4E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL3_E_PL_A_H4O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL4_E_PL_A_H5E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL4_E_PL_A_H5O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL5_E_PL_A_H6_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL5_E_PL_A_H7_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL6_E_PL_A_H8_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL6_E_PL_A_H9_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL7_E_PL_A_H10_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL7_E_PL_A_H11_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL8_E_PL_A_H12_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL9_E_PL_A_H1CAL_EN = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_FIR_MASK_PL_ERRS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_FIR_MASK_PL_ERRS_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL
+ = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL
+ = 52 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 53 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 57 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 59 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 61 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 62 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN =
+ 2 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 51 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 52
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 53
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL = 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN = 2 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP = 58
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM = 59
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN =
+ 3 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_LANE_INVALID = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_PDWN_LITE = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL =
+ 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL =
+ 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL
+ = 50 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL =
+ 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL =
+ 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL
+ = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL
+ = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL =
+ 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
+ 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL = 59 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL =
+ 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN
+ = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL =
+ 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL1_E_PL_A_H2E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL1_E_PL_A_H2O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL2_E_PL_A_H3E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL2_E_PL_A_H3O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL3_E_PL_A_H4E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL3_E_PL_A_H4O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL4_E_PL_A_H5E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL4_E_PL_A_H5O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL5_E_PL_A_H6_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL5_E_PL_A_H7_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL6_E_PL_A_H8_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL6_E_PL_A_H9_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL7_E_PL_A_H10_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL7_E_PL_A_H11_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL8_E_PL_A_H12_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL9_E_PL_A_H1CAL_EN = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_FIR_MASK_PL_ERRS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_FIR_MASK_PL_ERRS_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL
+ = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL
+ = 52 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 53 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 57 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 59 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 61 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 62 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN =
+ 2 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 51 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 52
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 53
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL = 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN = 2 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP = 58
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM = 59
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN =
+ 3 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_LANE_INVALID = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_PDWN_LITE = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL =
+ 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL =
+ 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL
+ = 50 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL =
+ 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL =
+ 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL
+ = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL
+ = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL =
+ 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
+ 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL = 59 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL =
+ 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN
+ = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL =
+ 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL1_E_PL_A_H2E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL1_E_PL_A_H2O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL2_E_PL_A_H3E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL2_E_PL_A_H3O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL3_E_PL_A_H4E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL3_E_PL_A_H4O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL4_E_PL_A_H5E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL4_E_PL_A_H5O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL5_E_PL_A_H6_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL5_E_PL_A_H7_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL6_E_PL_A_H8_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL6_E_PL_A_H9_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL7_E_PL_A_H10_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL7_E_PL_A_H11_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL8_E_PL_A_H12_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL9_E_PL_A_H1CAL_EN = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_FIR_MASK_PL_ERRS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_FIR_MASK_PL_ERRS_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL
+ = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL
+ = 52 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 53 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 57 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 59 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 61 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 62 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN =
+ 2 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 51 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 52
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 53
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL = 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN = 2 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP = 58
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM = 59
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN =
+ 3 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_LANE_INVALID = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_PDWN_LITE = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL =
+ 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL =
+ 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL
+ = 50 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL =
+ 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL =
+ 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL
+ = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL
+ = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL =
+ 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
+ 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL = 59 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL =
+ 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN
+ = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL =
+ 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL1_E_PL_A_H2E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL1_E_PL_A_H2O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL2_E_PL_A_H3E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL2_E_PL_A_H3O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL3_E_PL_A_H4E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL3_E_PL_A_H4O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL4_E_PL_A_H5E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL4_E_PL_A_H5O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL5_E_PL_A_H6_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL5_E_PL_A_H7_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL6_E_PL_A_H8_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL6_E_PL_A_H9_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL7_E_PL_A_H10_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL7_E_PL_A_H11_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL8_E_PL_A_H12_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL9_E_PL_A_H1CAL_EN = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_FIR_MASK_PL_ERRS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_FIR_MASK_PL_ERRS_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL
+ = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL
+ = 52 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 53 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 57 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 59 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 61 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 62 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN =
+ 2 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 51 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 52
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 53
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL = 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN = 2 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP = 58
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM = 59
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN =
+ 3 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_LANE_INVALID = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_PDWN_LITE = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL =
+ 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL =
+ 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL
+ = 50 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL =
+ 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL =
+ 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL
+ = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL
+ = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL =
+ 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
+ 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL = 59 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL =
+ 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN
+ = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL =
+ 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL1_E_PL_A_H2E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL1_E_PL_A_H2O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL2_E_PL_A_H3E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL2_E_PL_A_H3O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL3_E_PL_A_H4E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL3_E_PL_A_H4O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL4_E_PL_A_H5E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL4_E_PL_A_H5O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL5_E_PL_A_H6_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL5_E_PL_A_H7_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL6_E_PL_A_H8_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL6_E_PL_A_H9_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL7_E_PL_A_H10_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL7_E_PL_A_H11_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL8_E_PL_A_H12_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL9_E_PL_A_H1CAL_EN = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_FIR_MASK_PL_ERRS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_FIR_MASK_PL_ERRS_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL
+ = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL
+ = 52 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 53 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 57 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 59 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 61 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 62 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN =
+ 2 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 51 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 52
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 53
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL = 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN = 2 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP = 58
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM = 59
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN =
+ 3 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_LANE_INVALID = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_PDWN_LITE = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL =
+ 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL =
+ 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL
+ = 50 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL =
+ 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL =
+ 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL
+ = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL
+ = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL =
+ 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
+ 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL = 59 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL =
+ 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN
+ = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL =
+ 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL1_E_PL_A_H2E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL1_E_PL_A_H2O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL2_E_PL_A_H3E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL2_E_PL_A_H3O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL3_E_PL_A_H4E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL3_E_PL_A_H4O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL4_E_PL_A_H5E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL4_E_PL_A_H5O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL5_E_PL_A_H6_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL5_E_PL_A_H7_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL6_E_PL_A_H8_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL6_E_PL_A_H9_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL7_E_PL_A_H10_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL7_E_PL_A_H11_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL8_E_PL_A_H12_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL9_E_PL_A_H1CAL_EN = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_FIR_MASK_PL_ERRS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_FIR_MASK_PL_ERRS_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL
+ = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL
+ = 52 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 53 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 57 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 59 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 61 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 62 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN =
+ 2 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 51 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 52
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 53
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL = 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN = 2 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP = 58
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM = 59
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN =
+ 3 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_LANE_INVALID = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_PDWN_LITE = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL =
+ 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL =
+ 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL
+ = 50 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL =
+ 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL =
+ 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL
+ = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL
+ = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL =
+ 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
+ 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL = 59 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL =
+ 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN
+ = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL =
+ 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL1_E_PL_A_H2E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL1_E_PL_A_H2O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL2_E_PL_A_H3E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL2_E_PL_A_H3O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL3_E_PL_A_H4E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL3_E_PL_A_H4O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL4_E_PL_A_H5E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL4_E_PL_A_H5O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL5_E_PL_A_H6_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL5_E_PL_A_H7_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL6_E_PL_A_H8_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL6_E_PL_A_H9_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL7_E_PL_A_H10_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL7_E_PL_A_H11_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL8_E_PL_A_H12_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL9_E_PL_A_H1CAL_EN = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_FIR_MASK_PL_ERRS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_FIR_MASK_PL_ERRS_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL
+ = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL
+ = 52 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 53 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 57 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 59 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 61 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 62 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN =
+ 2 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 51 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 52
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 53
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL = 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN = 2 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP = 58
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM = 59
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN =
+ 3 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_LANE_INVALID = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_PDWN_LITE = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL =
+ 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL =
+ 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL
+ = 50 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL =
+ 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL =
+ 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL
+ = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL
+ = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL =
+ 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
+ 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL = 59 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL =
+ 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN
+ = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL =
+ 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL1_E_PL_A_H2E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL1_E_PL_A_H2O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL2_E_PL_A_H3E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL2_E_PL_A_H3O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL3_E_PL_A_H4E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL3_E_PL_A_H4O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL4_E_PL_A_H5E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL4_E_PL_A_H5O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL5_E_PL_A_H6_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL5_E_PL_A_H7_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL6_E_PL_A_H8_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL6_E_PL_A_H9_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL7_E_PL_A_H10_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL7_E_PL_A_H11_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL8_E_PL_A_H12_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL9_E_PL_A_H1CAL_EN = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_FIR_MASK_PL_ERRS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_FIR_MASK_PL_ERRS_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL
+ = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL
+ = 52 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 53 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 57 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 59 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 61 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 62 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN =
+ 2 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 51 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 52
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 53
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL = 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN = 2 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP = 58
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM = 59
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN =
+ 3 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_LANE_INVALID = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_PDWN_LITE = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL =
+ 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL =
+ 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL
+ = 50 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL =
+ 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL =
+ 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL
+ = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL
+ = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL =
+ 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
+ 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL = 59 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL =
+ 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN
+ = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL =
+ 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL1_E_PL_A_H2E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL1_E_PL_A_H2O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL2_E_PL_A_H3E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL2_E_PL_A_H3O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL3_E_PL_A_H4E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL3_E_PL_A_H4O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL4_E_PL_A_H5E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL4_E_PL_A_H5O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL5_E_PL_A_H6_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL5_E_PL_A_H7_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL6_E_PL_A_H8_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL6_E_PL_A_H9_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL7_E_PL_A_H10_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL7_E_PL_A_H11_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL8_E_PL_A_H12_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL9_E_PL_A_H1CAL_EN = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_FIR_MASK_PL_ERRS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_FIR_MASK_PL_ERRS_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL
+ = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL
+ = 52 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 53 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 57 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 59 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 61 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 62 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN =
+ 2 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 51 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 52
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 53
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL = 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN = 2 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP = 58
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM = 59
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN =
+ 3 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_LANE_INVALID = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_PDWN_LITE = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL =
+ 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL =
+ 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL
+ = 50 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL =
+ 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL =
+ 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL
+ = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL
+ = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL =
+ 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
+ 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL = 59 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL =
+ 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN
+ = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL =
+ 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL1_E_PL_A_H2E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL1_E_PL_A_H2O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL2_E_PL_A_H3E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL2_E_PL_A_H3O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL3_E_PL_A_H4E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL3_E_PL_A_H4O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL4_E_PL_A_H5E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL4_E_PL_A_H5O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL5_E_PL_A_H6_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL5_E_PL_A_H7_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL6_E_PL_A_H8_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL6_E_PL_A_H9_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL7_E_PL_A_H10_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL7_E_PL_A_H11_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL8_E_PL_A_H12_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL9_E_PL_A_H1CAL_EN = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_FIR_MASK_PL_ERRS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_FIR_MASK_PL_ERRS_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL
+ = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL
+ = 52 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 53 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 57 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 59 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 61 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 62 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN =
+ 2 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 51 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 52
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 53
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL = 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN = 2 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP = 58
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM = 59
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN =
+ 3 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_LANE_INVALID = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_PDWN_LITE = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL =
+ 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL =
+ 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL
+ = 50 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL =
+ 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL =
+ 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL
+ = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL
+ = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL =
+ 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
+ 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL = 59 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL =
+ 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN
+ = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL =
+ 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL1_E_PL_A_H2E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL1_E_PL_A_H2O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL2_E_PL_A_H3E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL2_E_PL_A_H3O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL3_E_PL_A_H4E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL3_E_PL_A_H4O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL4_E_PL_A_H5E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL4_E_PL_A_H5O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL5_E_PL_A_H6_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL5_E_PL_A_H7_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL6_E_PL_A_H8_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL6_E_PL_A_H9_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL7_E_PL_A_H10_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL7_E_PL_A_H11_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL8_E_PL_A_H12_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL9_E_PL_A_H1CAL_EN = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_FIR_MASK_PL_ERRS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_FIR_MASK_PL_ERRS_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL
+ = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL
+ = 52 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 53 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 57 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 59 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 61 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 62 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN =
+ 2 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 51 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 52
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 53
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL = 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN = 2 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP = 58
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM = 59
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN =
+ 3 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_LANE_INVALID = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_PDWN_LITE = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL =
+ 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL =
+ 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL
+ = 50 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL =
+ 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL =
+ 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL
+ = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL
+ = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL =
+ 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
+ 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL = 59 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL =
+ 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN
+ = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL =
+ 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL1_E_PL_A_H2E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL1_E_PL_A_H2O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL2_E_PL_A_H3E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL2_E_PL_A_H3O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL3_E_PL_A_H4E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL3_E_PL_A_H4O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL4_E_PL_A_H5E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL4_E_PL_A_H5O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL5_E_PL_A_H6_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL5_E_PL_A_H7_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL6_E_PL_A_H8_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL6_E_PL_A_H9_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL7_E_PL_A_H10_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL7_E_PL_A_H11_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL8_E_PL_A_H12_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL9_E_PL_A_H1CAL_EN = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_FIR_MASK_PL_ERRS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_FIR_MASK_PL_ERRS_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL
+ = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL
+ = 52 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 53 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 57 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 59 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 61 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 62 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN =
+ 2 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 51 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 52
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 53
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL = 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN = 2 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP = 58
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM = 59
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN =
+ 3 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_LANE_INVALID = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_PDWN_LITE = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL =
+ 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL =
+ 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL
+ = 50 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL =
+ 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL =
+ 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL
+ = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL
+ = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL =
+ 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
+ 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL = 59 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL =
+ 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN
+ = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL =
+ 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL1_E_PL_A_H2E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL1_E_PL_A_H2O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL2_E_PL_A_H3E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL2_E_PL_A_H3O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL3_E_PL_A_H4E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL3_E_PL_A_H4O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL4_E_PL_A_H5E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL4_E_PL_A_H5O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL5_E_PL_A_H6_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL5_E_PL_A_H7_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL6_E_PL_A_H8_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL6_E_PL_A_H9_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL7_E_PL_A_H10_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL7_E_PL_A_H11_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL8_E_PL_A_H12_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL9_E_PL_A_H1CAL_EN = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_FIR_MASK_PL_ERRS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_FIR_MASK_PL_ERRS_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL
+ = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL
+ = 52 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 53 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 57 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 59 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 61 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 62 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN =
+ 2 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 51 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 52
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 53
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL = 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN = 2 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP = 58
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM = 59
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN =
+ 3 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_LANE_INVALID = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_PDWN_LITE = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL =
+ 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL =
+ 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL
+ = 50 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL =
+ 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL =
+ 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL
+ = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL
+ = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL =
+ 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
+ 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL = 59 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL =
+ 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN
+ = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL =
+ 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL1_E_PL_A_H2E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL1_E_PL_A_H2O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL2_E_PL_A_H3E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL2_E_PL_A_H3O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL3_E_PL_A_H4E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL3_E_PL_A_H4O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL4_E_PL_A_H5E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL4_E_PL_A_H5O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL5_E_PL_A_H6_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL5_E_PL_A_H7_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL6_E_PL_A_H8_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL6_E_PL_A_H9_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL7_E_PL_A_H10_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL7_E_PL_A_H11_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL8_E_PL_A_H12_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL9_E_PL_A_H1CAL_EN = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_FIR_MASK_PL_ERRS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_FIR_MASK_PL_ERRS_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL
+ = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL
+ = 52 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 53 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 57 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 59 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 61 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 62 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN =
+ 2 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 51 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 52
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 53
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL = 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN = 2 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP = 58
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM = 59
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN =
+ 3 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_LANE_INVALID = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_PDWN_LITE = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL =
+ 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL =
+ 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL
+ = 50 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL =
+ 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL =
+ 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL
+ = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL
+ = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL =
+ 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
+ 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL = 59 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL =
+ 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN
+ = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL =
+ 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL1_E_PL_A_H2E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL1_E_PL_A_H2O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL2_E_PL_A_H3E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL2_E_PL_A_H3O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL3_E_PL_A_H4E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL3_E_PL_A_H4O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL4_E_PL_A_H5E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL4_E_PL_A_H5O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL5_E_PL_A_H6_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL5_E_PL_A_H7_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL6_E_PL_A_H8_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL6_E_PL_A_H9_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL7_E_PL_A_H10_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL7_E_PL_A_H11_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL8_E_PL_A_H12_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL9_E_PL_A_H1CAL_EN = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_FIR_MASK_PL_ERRS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_FIR_MASK_PL_ERRS_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL
+ = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL
+ = 52 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 53 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 57 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 59 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 61 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 62 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN =
+ 2 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 51 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 52
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 53
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL = 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN = 2 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP = 58
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM = 59
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN =
+ 3 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_LANE_INVALID = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_PDWN_LITE = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL =
+ 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL =
+ 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL
+ = 50 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL =
+ 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL =
+ 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL
+ = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL
+ = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL =
+ 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
+ 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL = 59 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL =
+ 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN
+ = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL =
+ 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL1_E_PL_A_H2E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL1_E_PL_A_H2O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL2_E_PL_A_H3E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL2_E_PL_A_H3O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL3_E_PL_A_H4E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL3_E_PL_A_H4O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL4_E_PL_A_H5E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL4_E_PL_A_H5O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL5_E_PL_A_H6_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL5_E_PL_A_H7_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL6_E_PL_A_H8_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL6_E_PL_A_H9_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL7_E_PL_A_H10_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL7_E_PL_A_H11_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL8_E_PL_A_H12_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL9_E_PL_A_H1CAL_EN = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_FIR_MASK_PL_ERRS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_FIR_MASK_PL_ERRS_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL
+ = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL
+ = 52 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 53 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 57 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 59 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 61 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 62 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN =
+ 2 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 51 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 52
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 53
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL = 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN = 2 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP = 58
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM = 59
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN =
+ 3 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_LANE_INVALID = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_PDWN_LITE = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE3_EO_PL_BER_CFG = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE3_EO_PL_DDC_CFG = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL =
+ 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL =
+ 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL
+ = 50 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL =
+ 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL =
+ 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL
+ = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL
+ = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL =
+ 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
+ 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL = 59 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL =
+ 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN
+ = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL =
+ 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL1_E_PL_A_H2E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL1_E_PL_A_H2O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL2_E_PL_A_H3E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL2_E_PL_A_H3O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL3_E_PL_A_H4E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL3_E_PL_A_H4O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL4_E_PL_A_H5E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL4_E_PL_A_H5O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL5_E_PL_A_H6_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL5_E_PL_A_H7_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL6_E_PL_A_H8_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL6_E_PL_A_H9_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL7_E_PL_A_H10_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL7_E_PL_A_H11_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL8_E_PL_A_H12_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL9_E_PL_A_H1CAL_EN = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DATA_DAC_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DATA_DAC_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DATA_DAC_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DATA_DAC_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DATA_DAC_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DATA_DAC_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DATA_DAC_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_DATA_DAC_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_FIR_MASK_PL_ERRS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_FIR_MASK_PL_ERRS_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE4_RX_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_FIFO_INC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_FIFO_DEC_L2U_DLY_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_PRBS_INC_WO_PULSE_SLOW_SIGNAL
+ = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_PRBS_DEC_WO_PULSE_SLOW_SIGNAL
+ = 52 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 53 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_CHECK_SYNC_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_SET_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 57 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_CLR_EDGE_TRACK_CNTL_WO_PULSE_SLOW_SIGNAL = 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_SET_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 59 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_CLR_PRBS_SEED_DDC_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_SET_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 61 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL_RX_CLR_BER_DPIPE_MUX_SEL_WO_PULSE_SLOW_SIGNAL = 62 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN =
+ 2 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL3_E_PL_RX_SET_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL3_E_PL_RX_CLR_PIPE_SEL_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL3_E_PL_RX_SET_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 50 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL3_E_PL_RX_CLR_PRBS_SEED_DFE_WO_PULSE_SLOW_SIGNAL = 51 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL3_E_PL_RX_SET_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 52
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL3_E_PL_RX_CLR_DFE_FORCE_LOAD_SEED_WO_PULSE_SLOW_SIGNAL = 53
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL = 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL3_E_PL_RX_FIFO_L2U_DEC_WO_PULSE_SLOW_SIGNAL_LEN = 2 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL3_E_PL_RX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL3_E_PL_RX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP = 58
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM = 59
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN =
+ 3 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_LANE_INVALID = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_PDWN_LITE = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE3_EO_PL_BER_CFG = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE3_EO_PL_DDC_CFG = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_RO_SIGNAL =
+ 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT1_EO_PL_RX_PRBS_SYNC_DONE_B_RO_SIGNAL =
+ 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_RO_SIGNAL
+ = 50 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT1_EO_PL_RX_PRBS_SEED_DDC_DONE_B_RO_SIGNAL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT1_EO_PL_RX_PR_NIBBLE_FOUND_RO_SIGNAL =
+ 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_RO_SIGNAL = 54
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT1_EO_PL_RX_DFE_SYNC_DONE_B_RO_SIGNAL =
+ 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL
+ = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT1_EO_PL_RX_PSAVE_RESYNC_BUSY_RO_SIGNAL
+ = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL =
+ 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_TO_FROM_EDGE_A_DONE_RO_SIGNAL = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
+ 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT2_EO_PL_RX_DDC_DFE_OFFSET_SWITCH_IP_RO_SIGNAL = 59 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL =
+ 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN
+ = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL =
+ 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL1_E_PL_A_H2E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL1_E_PL_A_H2O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL2_E_PL_A_H3E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL2_E_PL_A_H3O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL3_E_PL_A_H4E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL3_E_PL_A_H4O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL4_E_PL_A_H5E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL4_E_PL_A_H5O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL5_E_PL_A_H6_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL5_E_PL_A_H7_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL6_E_PL_A_H8_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL6_E_PL_A_H9_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL7_E_PL_A_H10_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL7_E_PL_A_H11_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL8_E_PL_A_H12_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL9_E_PL_A_H1CAL_EN = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DATA_DAC_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DATA_DAC_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DATA_DAC_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DATA_DAC_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DATA_DAC_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DATA_DAC_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DATA_DAC_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_DATA_DAC_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_FIR_MASK_PL_ERRS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_FIR_MASK_PL_ERRS_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RXPACKS3_SLICE5_RX_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL10_EO_PG_BIST_PRBS_TEST_TIME = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL10_EO_PG_BIST_PRBS_TEST_TIME_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL10_EO_PG_BIST_BUS_DATA_MODE = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL10_EO_PG_BIST_PRBS_PROP_TIME = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL10_EO_PG_BIST_PRBS_PROP_TIME_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL10_EO_PG_BIST_PLL_LOCK_TIMEOUT = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL10_EO_PG_BIST_PLL_LOCK_TIMEOUT_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL11_EO_PG_DACTEST_LLMT = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL11_EO_PG_DACTEST_LLMT_LEN = 9 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL11_EO_PG_DACTEST_RESET = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL11_EO_PG_DACTEST_START = 58 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL12_EO_PG_DACTEST_HLMT = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL12_EO_PG_DACTEST_HLMT_LEN = 9 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL13_EO_PG_HIST_MIN_EYE_WIDTH_VALID = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL13_EO_PG_HIST_MIN_EYE_WIDTH_LANE = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL13_EO_PG_HIST_MIN_EYE_WIDTH_LANE_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL13_EO_PG_HIST_MIN_EYE_WIDTH = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL13_EO_PG_HIST_MIN_EYE_WIDTH_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL14_EO_PG_HIST_MIN_EYE_HEIGHT_VALID = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL14_EO_PG_HIST_MIN_EYE_HEIGHT_LANE = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL14_EO_PG_HIST_MIN_EYE_HEIGHT_LANE_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL14_EO_PG_HIST_MIN_EYE_HEIGHT = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL14_EO_PG_HIST_MIN_EYE_HEIGHT_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL15_EO_PG_WTL_TEST_CLOCK = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL15_EO_PG_WTL_TEST_DATA = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL15_EO_PG_WT_BS_CLOCK_EN_BYP = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL15_EO_PG_WT_BS_DATA_EN_BYP = 51 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL1_EO_PG_BER_EN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL1_EO_PG_BER_TIMER_FREEZE_EN = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL1_EO_PG_BER_COUNT_FREEZE_EN = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL1_EO_PG_BER_COUNT_SEL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL1_EO_PG_BER_COUNT_SEL_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL1_EO_PG_BER_TIMER_SEL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL1_EO_PG_BER_TIMER_SEL_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL1_EO_PG_BER_CLR_COUNT_ON_READ_EN = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL1_EO_PG_BER_CLR_TIMER_ON_READ_EN = 60 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL1_E_PG_START_WIRETEST = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL1_E_PG_START_DESKEW = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL1_E_PG_START_EYE_OPT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL1_E_PG_START_REPAIR = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL1_E_PG_START_FUNC_MODE = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL1_E_PG_START_DC_CALIBRATE = 53 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL2_EO_PG_TRC_MODE = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL2_EO_PG_TRC_MODE_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL3_EO_PG_INT_MODE = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL3_EO_PG_INT_MODE_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL3_EO_PG_INT_CURRENT_STATE = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL3_EO_PG_INT_CURRENT_STATE_LEN = 12 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL4_EO_PG_INT_ENABLE_ENC = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL4_EO_PG_INT_ENABLE_ENC_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL4_EO_PG_INT_NEXT_STATE = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL4_EO_PG_INT_NEXT_STATE_LEN = 12 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL4_E_PG_WT_CU_PLL_PGOOD = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL4_E_PG_WT_CU_BYP_PLL_LOCK = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL4_E_PG_WT_PLL_REFCLKSEL = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL4_E_PG_PLL_REFCLKSEL_SCOM_EN = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL4_E_PG_IORESET = 52 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL5_EO_PG_INT_GOTO_STATE = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL5_EO_PG_INT_GOTO_STATE_LEN = 12 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL6_EO_PG_INT_RETURN_STATE = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL6_EO_PG_INT_RETURN_STATE_LEN = 12 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL8_EO_PG_SERVO_OP = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL8_EO_PG_SERVO_OP_LEN = 15 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL8_EO_PG_SERVO_DONE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL9_EO_PG_BIST_EN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL9_EO_PG_BIST_EXT_START_MODE = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL9_EO_PG_BIST_INIT_DISABLE = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL9_EO_PG_BIST_INIT_DISABLE_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL9_EO_PG_BIST_CUPLL_LOCK_CHECK_EN = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL9_EO_PG_BIST_STORE_EYES_LANE_SEL = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL9_EO_PG_BIST_STORE_EYES_LANE_SEL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL9_EO_PG_BIST_STORE_EYES_BANK_SEL = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL9_EO_PG_BIST_STORE_EYES_BANK_SEL_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTL9_EO_PG_PERVASIVE_CAPT = 62 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTLX11_E_PG_DESKEW_SEQ_GCRMSG = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTLX11_E_PG_DESKEW_SEQ_GCRMSG_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTLX11_E_PG_DESKEW_SKMIN_GCRMSG = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTLX11_E_PG_DESKEW_SKMIN_GCRMSG_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTLX11_E_PG_DESKEW_SKMAX_GCRMSG = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTLX11_E_PG_DESKEW_SKMAX_GCRMSG_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTLX7_EO_PG_CAL_LANE_GCRMSG = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTLX7_EO_PG_CAL_LANE_GCRMSG_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTLX7_EO_PG_CAL_LANE_VAL_GCRMSG = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTLX7_EO_PG_CAL_LANE_PHY_GCRMSG = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_CNTLX7_EO_PG_CAL_LANE_PHY_GCRMSG_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE10_EO_PG_AMP_INIT_CFG = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE10_EO_PG_AMP_INIT_CFG_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE10_EO_PG_AMP_RECAL_CFG = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE10_EO_PG_AMP_RECAL_CFG_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE10_EO_PG_PEAK_INIT_CFG = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE10_EO_PG_PEAK_INIT_CFG_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE10_EO_PG_PEAK_RECAL_CFG = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE10_EO_PG_PEAK_RECAL_CFG_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE10_EO_PG_AMP_CFG = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE10_EO_PG_AMP_CFG_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE10_E_PG_DESKEW_MAX_LIMIT = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE10_E_PG_DESKEW_MAX_LIMIT_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE11_EO_PG_OFF_INIT_CFG = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE11_EO_PG_OFF_INIT_CFG_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE11_EO_PG_OFF_RECAL_CFG = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE11_EO_PG_OFF_RECAL_CFG_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE11_EO_PG_CM_CFG = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE11_EO_PG_CM_CFG_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE11_EO_PG_AMIN_CFG = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE11_EO_PG_AMIN_CFG_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE11_EO_PG_USERDEF_CFG = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE11_EO_PG_USERDEF_CFG_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE11_E_PG_LANE_DISABLED_VEC_0_15 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE11_E_PG_LANE_DISABLED_VEC_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE12_EO_PG_SERVO_CHG_CFG = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE12_EO_PG_SERVO_CHG_CFG_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE12_EO_PG_DAC_BO_CFG = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE12_EO_PG_DAC_BO_CFG_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE12_EO_PG_FILTER_MODE = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE12_EO_PG_FILTER_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE12_EO_PG_MISC_CFG = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE12_EO_PG_MISC_CFG_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE12_EO_PG_DISABLE_H1_CLEAR = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE12_EO_PG_VOFF_CFG = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE12_EO_PG_VOFF_CFG_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE12_EO_PG_LOFF_AMP_EN = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE12_E_PG_LANE_DISABLED_VEC_16_23 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE12_E_PG_LANE_DISABLED_VEC_16_23_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE13_EO_PG_CM_OFFSET_VAL = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE13_EO_PG_CM_OFFSET_VAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE13_EO_PG_SERVO_THRESH1 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE13_EO_PG_SERVO_THRESH1_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE13_EO_PG_SERVO_THRESH2 = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE13_EO_PG_SERVO_THRESH2_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE14_EO_PG_AMP_INIT_TIMEOUT = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE14_EO_PG_AMP_INIT_TIMEOUT_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE14_EO_PG_AMP_RECAL_TIMEOUT = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE14_EO_PG_AMP_RECAL_TIMEOUT_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE14_EO_PG_PEAK_INIT_TIMEOUT = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE14_EO_PG_PEAK_INIT_TIMEOUT_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE14_EO_PG_PEAK_RECAL_TIMEOUT = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE14_EO_PG_PEAK_RECAL_TIMEOUT_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE15_EO_PG_OFF_INIT_TIMEOUT = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE15_EO_PG_OFF_INIT_TIMEOUT_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE15_EO_PG_OFF_RECAL_TIMEOUT = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE15_EO_PG_OFF_RECAL_TIMEOUT_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE15_EO_PG_CM_TIMEOUT = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE15_EO_PG_CM_TIMEOUT_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE15_EO_PG_AMIN_TIMEOUT = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE15_EO_PG_AMIN_TIMEOUT_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE16_EO_PG_AMP_TIMEOUT = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE16_EO_PG_AMP_TIMEOUT_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE16_EO_PG_USERDEF_TIMEOUT = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE16_EO_PG_USERDEF_TIMEOUT_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE16_EO_PG_BER_TIMEOUT = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE16_EO_PG_BER_TIMEOUT_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE16_EO_PG_SPARE4_TIMEOUT = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE16_EO_PG_SPARE4_TIMEOUT_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE17_EO_PG_AMAX_HIGH = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE17_EO_PG_AMAX_HIGH_LEN = 8 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE17_EO_PG_AMAX_LOW = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE17_EO_PG_AMAX_LOW_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE18_EO_PG_AMP0_FILTER_MASK = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE18_EO_PG_AMP0_FILTER_MASK_LEN = 8 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE18_EO_PG_AMP1_FILTER_MASK = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE18_EO_PG_AMP1_FILTER_MASK_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE19_EO_PG_CTLE_GAIN_MAX = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE19_EO_PG_CTLE_GAIN_MAX_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE19_EO_PG_AMP_START_VAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE19_EO_PG_AMP_START_VAL_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE1_EO_PG_CLKDIST_PDWN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE1_EO_PG_BIST_MIN_EYE_WIDTH = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE1_EO_PG_BIST_MIN_EYE_WIDTH_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE1_EO_PG_A_BIST_EN = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE1_E_PG_MASTER_MODE = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE1_E_PG_DISABLE_FENCE_RESET = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE1_E_PG_FENCE = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE1_E_PG_PDWN_LITE_DISABLE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE1_E_PG_USE_SLS_AS_SPR = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE1_E_PG_DYN_RECAL_SUSPEND = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE1_E_PG_WT_PATTERN_LENGTH = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE1_E_PG_WT_PATTERN_LENGTH_LEN = 2 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE20_EO_PG_DFE_CONVERGED_CNT_MAX = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE20_EO_PG_DFE_CONVERGED_CNT_MAX_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE20_EO_PG_AP110_AP010_DELTA_MAX = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE20_EO_PG_AP110_AP010_DELTA_MAX_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE21_EO_PG_ENABLE_INTEG_LATCH_OFFSET_CAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE21_EO_PG_ENABLE_CTLE_COARSE_CAL = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE21_EO_PG_ENABLE_DAC_H1_CAL = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE21_EO_PG_ENABLE_VGA_CAL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE21_EO_PG_ENABLE_DFE_H1_CAL = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE21_EO_PG_ENABLE_H1AP_TWEAK = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE21_EO_PG_ENABLE_DDC = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE21_EO_PG_ENABLE_CM_COARSE_CAL = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE21_EO_PG_ENABLE_CM_FINE_CAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE21_EO_PG_ENABLE_BER_TEST = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE21_EO_PG_ENABLE_RESULT_CHECK = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE21_EO_PG_ENABLE_CTLE_EDGE_TRACK_ONLY = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE21_EO_PG_ENABLE_DFE_H2_H12_CAL = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE21_EO_PG_ENABLE_DAC_H1_TO_A_CAL = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE21_EO_PG_ENABLE_FINAL_L2U_ADJ = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE21_EO_PG_ENABLE_DONE_SIGNALING = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE22_EO_PG_RC_ENABLE_INTEG_LATCH_OFFSET_CAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE22_EO_PG_RC_ENABLE_CTLE_COARSE_CAL = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE22_EO_PG_RC_ENABLE_DAC_H1_CAL = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE22_EO_PG_RC_ENABLE_VGA_CAL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE22_EO_PG_RC_ENABLE_DFE_H1_CAL = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE22_EO_PG_RC_ENABLE_H1AP_TWEAK = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE22_EO_PG_RC_ENABLE_DDC = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE22_EO_PG_RC_ENABLE_CM_COARSE_CAL = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE22_EO_PG_RC_ENABLE_CM_FINE_CAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE22_EO_PG_RC_ENABLE_BER_TEST = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE22_EO_PG_RC_ENABLE_RESULT_CHECK = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE22_EO_PG_RC_ENABLE_CTLE_EDGE_TRACK_ONLY = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE22_EO_PG_RC_ENABLE_DFE_H2_H12_CAL = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE22_EO_PG_RC_ENABLE_DAC_H1_TO_A_CAL = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE23_EO_PG_QUAD_SEL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE23_EO_PG_QUAD_SEL_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE23_EO_PG_PEAK_TUNE = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE23_EO_PG_LTE_EN = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE23_EO_PG_IQSPD_CFG = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE23_EO_PG_IQSPD_CFG_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE23_EO_PG_DFEHISPD_EN = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE23_EO_PG_DFE12_EN = 60 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE24_EO_PG_H1AP_CFG = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE24_EO_PG_H1AP_CFG_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE24_EO_PG_CTLE_UPDATE_MODE = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE24_EO_PG_USER_FILTER_MASK = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE24_EO_PG_USER_FILTER_MASK_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE26_EO_PG_ENABLE_CTLE_1ST_LATCH_OFFSET_CAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE26_EO_PG_ENABLE_CTLE_2ND_LATCH_OFFSET_CAL = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE26_EO_PG_ENABLE_VGA_AMAX_MODE = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE26_EO_PG_ENABLE_DFE_H2_H12_SUBSTEP = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE26_EO_PG_ENABLE_DFE_H2_H12_SUBSTEP_LEN = 11 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE26_EO_PG_ENABLE_DFE_VOLTAGE_MODE = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE26_EO_PG_ENABLE_DFE_H6_H12_FAST_MODE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE27_EO_PG_RC_ENABLE_CTLE_1ST_LATCH_OFFSET_CAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE27_EO_PG_RC_ENABLE_CTLE_2ND_LATCH_OFFSET_CAL = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE27_EO_PG_RC_ENABLE_VGA_AMAX_MODE = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE27_EO_PG_RC_ENABLE_DFE_H2_H12_SUBSTEP = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE27_EO_PG_RC_ENABLE_DFE_H2_H12_SUBSTEP_LEN = 11 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE27_EO_PG_RC_ENABLE_DFE_VOLTAGE_MODE = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE27_EO_PG_RC_ENABLE_DFE_H6_H12_FAST_MODE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE28_EO_PG_DC_ENABLE_CM_COARSE_CAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE28_EO_PG_DC_ENABLE_CM_FINE_CAL = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE28_EO_PG_DC_ENABLE_CTLE_1ST_LATCH_OFFSET_CAL = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE28_EO_PG_DC_ENABLE_CTLE_2ND_LATCH_OFFSET_CAL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE28_EO_PG_DC_ENABLE_INTEG_LATCH_OFFSET_CAL = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE28_EO_PG_DC_ENABLE_DAC_H1_CAL = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE28_EO_PG_DC_ENABLE_DAC_H1_TO_A_CAL = 54 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE29_EO_PG_APX111_HIGH = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE29_EO_PG_APX111_HIGH_LEN = 8 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE29_EO_PG_APX111_LOW = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE29_EO_PG_APX111_LOW_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE2_EO_PG_DFE_CA_CFG = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE2_EO_PG_DFE_CA_CFG_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE2_EO_PG_SCOPE_CONTROL = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE2_EO_PG_SCOPE_CONTROL_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE2_EO_PG_DATA_PIPE_CLR_ON_READ_MODE = 59 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE2_E_PG_WTR_MAX_BAD_LANES = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE2_E_PG_WTR_MAX_BAD_LANES_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE2_E_PG_SLS_EXTEND_SEL = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE2_E_PG_SLS_EXTEND_SEL_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE2_E_PG_DYN_RPR_ENC_BAD_DATA_LANE_SHFT_AMT = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE2_E_PG_DYN_RPR_ENC_BAD_DATA_LANE_SHFT_AMT_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE3_EO_PG_SERVO_THRESH3 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE3_EO_PG_SERVO_THRESH3_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE3_EO_PG_DFE_HTAP_CFG = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE3_EO_PG_DFE_HTAP_CFG_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE3_EO_PG_DFE_INIT_TIMEOUT = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE3_EO_PG_DFE_INIT_TIMEOUT_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE3_EO_PG_DFE_RECAL_TIMEOUT = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE3_EO_PG_DFE_RECAL_TIMEOUT_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE3_E_PG_SLS_TIMEOUT_SEL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE3_E_PG_SLS_TIMEOUT_SEL_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE3_E_PG_CL_TIMEOUT_SEL = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE3_E_PG_CL_TIMEOUT_SEL_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE3_E_PG_DS_SKEW_TIMEOUT_SEL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE3_E_PG_DS_SKEW_TIMEOUT_SEL_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE3_E_PG_DS_TIMEOUT_SEL = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE3_E_PG_DS_TIMEOUT_SEL_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE4_EO_PG_DISABLE_2TO12_CLEAR = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE4_EO_PG_PEAK_ENABLE_DAC_CFG = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE4_EO_PG_AMIN_ENABLE_HDAC = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE4_EO_PG_USE_PREV_COARSE_VAL = 51 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE4_E_PG_WT_CHECK_COUNT = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE4_E_PG_WT_CHECK_COUNT_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE4_E_PG_PGOOD_TIMEOUT_SEL = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE4_E_PG_PGOOD_TIMEOUT_SEL_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE4_E_PG_PLL_LOCK_TIMEOUT_SEL = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE4_E_PG_PLL_LOCK_TIMEOUT_SEL_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE4_E_PG_PSAVE_TIMER_WAKEUP_MODE = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE4_E_PG_PSAVE_WAKEUP_LANE0_ENABLE = 62 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE5_EO_PG_DYN_RECAL_INTERVAL_TIMEOUT_SEL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE5_EO_PG_DYN_RECAL_INTERVAL_TIMEOUT_SEL_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE5_EO_PG_DYN_RECAL_STATUS_RPT_TIMEOUT_SEL = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE5_EO_PG_DYN_RECAL_STATUS_RPT_TIMEOUT_SEL_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE5_EO_PG_TRACKING_TIMEOUT_SEL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE5_EO_PG_TRACKING_TIMEOUT_SEL_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE5_EO_PG_PUP_LITE_WAIT_SEL = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE5_EO_PG_PUP_LITE_WAIT_SEL_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE5_E_PG_FIFO_INITIAL_L2U_DLY = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE5_E_PG_FIFO_INITIAL_L2U_DLY_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE5_E_PG_FIFO_FINAL_L2U_DLY = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE5_E_PG_FIFO_FINAL_L2U_DLY_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE5_E_PG_WT_TIMEOUT_SEL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE5_E_PG_WT_TIMEOUT_SEL_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE6_EO_PG_CONVERGED_END_COUNT = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE6_EO_PG_CONVERGED_END_COUNT_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE6_EO_PG_HIST_MIN_EYE_WIDTH_MODE = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE6_EO_PG_HIST_MIN_EYE_WIDTH_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE6_EO_PG_HIST_MIN_EYE_HEIGHT_MODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE6_EO_PG_HIST_MIN_EYE_HEIGHT_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE6_EO_PG_AMP_GAIN_CNT_MAX = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE6_EO_PG_AMP_GAIN_CNT_MAX_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE6_E_PG_TX_BUS_WIDTH = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE6_E_PG_TX_BUS_WIDTH_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE6_E_PG_RX_BUS_WIDTH = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE6_E_PG_RX_BUS_WIDTH_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE7_EO_PG_ABORT_CHECK_TIMEOUT_SEL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE7_EO_PG_ABORT_CHECK_TIMEOUT_SEL_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE7_EO_PG_POLLING_TIMEOUT_SEL = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE7_EO_PG_POLLING_TIMEOUT_SEL_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE7_EO_PG_PSAVE_MODE_TIMEOUT_SEL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE7_EO_PG_PSAVE_MODE_TIMEOUT_SEL_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE7_EO_PG_DYN_RECAL_OVERALL_TIMEOUT_SEL = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE7_EO_PG_DYN_RECAL_OVERALL_TIMEOUT_SEL_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE7_E_PG_SLS_DISABLE = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE7_E_PG_TX_SLS_DISABLE = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE7_E_PG_SLS_CNTR_TAP_PTS = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE7_E_PG_SLS_CNTR_TAP_PTS_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE7_E_PG_NONSLS_CNTR_TAP_PTS = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE7_E_PG_NONSLS_CNTR_TAP_PTS_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE7_E_PG_SLS_EXCEPTION2_CS = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE7_E_PG_DYN_RPR_ERR_CNTR1_FILTER_MODE = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE7_E_PG_DYN_RPR_ERR_CNTR1_FILTER_MODE_LEN = 2 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE8_EO_PG_MAX_BER_CHECK_COUNT = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE8_EO_PG_MAX_BER_CHECK_COUNT_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE8_E_PG_DYN_RPR_BAD_LANE_MAX = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE8_E_PG_DYN_RPR_BAD_LANE_MAX_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE8_E_PG_DYN_RPR_ERR_CNTR1_DURATION = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE8_E_PG_DYN_RPR_ERR_CNTR1_DURATION_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE8_E_PG_DYN_RPR_CLR_ERR_CNTR1 = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE8_E_PG_DYN_RPR_DISABLE = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE8_E_PG_DYN_RPR_ENC_BAD_DATA_LANE_WIDTH = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE8_E_PG_DYN_RPR_ENC_BAD_DATA_LANE_WIDTH_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE9_EO_PG_MIN_EYE_WIDTH = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE9_EO_PG_MIN_EYE_WIDTH_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE9_EO_PG_MIN_EYE_HEIGHT = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE9_EO_PG_MIN_EYE_HEIGHT_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE9_E_PG_DYN_RPR_BAD_BUS_MAX = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE9_E_PG_DYN_RPR_BAD_BUS_MAX_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE9_E_PG_DYN_RPR_ERR_CNTR2_DURATION = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE9_E_PG_DYN_RPR_ERR_CNTR2_DURATION_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE9_E_PG_DYN_RPR_CLR_ERR_CNTR2 = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_MODE9_E_PG_DYN_RPR_DISABLE2 = 60 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT1_EO_PG_SERVO_RESULT = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT1_EO_PG_SERVO_RESULT_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT1_E_PG_WIRETEST_DONE = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT1_E_PG_DESKEW_DONE = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT1_E_PG_EYE_OPT_DONE = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT1_E_PG_REPAIR_DONE = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT1_E_PG_FUNC_MODE_DONE = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT1_E_PG_DC_CALIBRATE_DONE = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT1_E_PG_WIRETEST_FAILED = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT1_E_PG_DESKEW_FAILED = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT1_E_PG_EYE_OPT_FAILED = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT1_E_PG_REPAIR_FAILED = 59 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT2_EO_PG_BIST_INIT_DONE = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT2_EO_PG_BIST_DONE = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT2_EO_PG_BIST_CU_PLL_ERR = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT2_EO_PG_BIST_NO_EDGE_DET = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT2_EO_PG_BIST_EYE_A_WIDTH = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT2_EO_PG_BIST_EYE_A_WIDTH_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT2_EO_PG_BIST_EYE_B_WIDTH = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT2_EO_PG_BIST_EYE_B_WIDTH_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT2_E_PG_LANE_BAD_VEC_0_15 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT2_E_PG_LANE_BAD_VEC_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT3_EO_PG_WTL_SM_STATUS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT3_EO_PG_WTL_SM_STATUS_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT4_E_PG_LANE_BAD_VEC_16_23 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT4_E_PG_LANE_BAD_VEC_16_23_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT5_E_PG_WT_CLK_LANE_INVERTED = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT5_E_PG_WT_CLK_LANE_BAD_CODE = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT5_E_PG_WT_CLK_LANE_BAD_CODE_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT6_E_PG_DESKEW_MINSKEW_GRP = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT6_E_PG_DESKEW_MINSKEW_GRP_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT6_E_PG_DESKEW_MAXSKEW_GRP = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STAT6_E_PG_DESKEW_MAXSKEW_GRP_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STATX8_E_PG_WT_PREV_DONE_GCRMSG = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STATX8_E_PG_WT_ALL_DONE_GCRMSG = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_CTL_STATX8_E_PG_CNTLS_PREV_LDED_GCRMSG = 52 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_CNTL1_E_PG_PRBS_SCRAMBLE_MODE = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_CNTL1_E_PG_PRBS_SCRAMBLE_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_CNTL1_E_PG_PRBS_SEED_MODE = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_CNTL1_E_PG_DESKEW_RATE = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_CNTL1_E_PG_RUN_DYN_RECAL_TIMER = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_CNTL1_E_PG_DESKEW_PATTCHK_TIMEOUT_SEL = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_CNTL1_E_PG_DESKEW_PATTCHK_TIMEOUT_SEL_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_CNTL1_E_PG_PRBS_SLS_EXPECT = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_CNTL1_E_PG_PRBS_SLS_EXPECT_LEN = 8 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_CNTL1_E_PG_HALF_RATE_MODE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_CNTL2_EO_PG_POFF_EOFF_TIMEOUT = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_CNTL2_EO_PG_POFF_EOFF_TIMEOUT_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_CNTL2_EO_PG_POFF_EOFF_CFG = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_CNTL2_EO_PG_POFF_EOFF_CFG_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_CNTL2_EO_PG_POFF_EOFF_BLOCK_ERROR = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_CNTL2_EO_PG_FILTER_OPTIONS = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_CNTL2_EO_PG_FILTER_OPTIONS_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_CNTLX1_EO_PG_RX_BER_COUNT_CLR_WO_PULSE_SLOW_SIGNAL = 49
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_CNTLX1_EO_PG_RX_BER_TIMER_CLR_WO_PULSE_SLOW_SIGNAL = 50
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_CNTLX1_EO_PG_RX_SCOPE_CAPTURE_WO_PULSE_SLOW_SIGNAL = 51
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_CNTLX1_EO_PG_RX_DATA_PIPE_CAPTURE_WO_PULSE_SLOW_SIGNAL =
+ 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_CNTLX1_EO_PG_RX_RESET_SERVO_STATUS_WO_PULSE_SLOW_SIGNAL
+ = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_CNTLX1_EO_PG_RX_BER_RESET_WO_PULSE_SLOW_SIGNAL = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_CNTLX1_EO_PG_RX_REPAIR_COMP_WO_PULSE_SLOW_SIGNAL = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_SPARE_MODE_PG_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_SPARE_MODE_PG_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_SPARE_MODE_PG_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_SPARE_MODE_PG_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_SPARE_MODE_PG_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_SPARE_MODE_PG_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_SPARE_MODE_PG_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_SPARE_MODE_PG_7 = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_SPARE_MODE_PG_SERVO_CONFIG = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_SPARE_MODE_PG_SERVO_CONFIG_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_SPARE_MODE_PG_CTL_CLKDIST_PDWN = 60 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT10_EO_PG_RX_SCAN_N_16_23_RO_SIGNAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT10_EO_PG_RX_SCAN_N_16_23_RO_SIGNAL_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT11_EO_PG_RX_SCAN_N_0_15_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT11_EO_PG_RX_SCAN_N_0_15_RO_SIGNAL_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT12_EO_PG_RX_SERVO_STATUS2_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT12_EO_PG_RX_SERVO_STATUS2_RO_SIGNAL_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT13_E_PG_BAD_BUS_LANE_ERR_CNTR_DIS_CLR = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT13_E_PG_RX_BAD_BUS_LANE_ERR_CNTR_RO_SIGNAL = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT13_E_PG_RX_BAD_BUS_LANE_ERR_CNTR_RO_SIGNAL_LEN = 7
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT13_E_PG_RX_LAST_BAD_BUS_LANE_RO_SIGNAL = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT13_E_PG_RX_LAST_BAD_BUS_LANE_RO_SIGNAL_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT1_EO_PG_RX_BER_COUNT_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT1_EO_PG_RX_BER_COUNT_RO_SIGNAL_LEN = 11 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT1_EO_PG_RX_BER_COUNT_SATURATED_RO_SIGNAL = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT1_EO_PG_RX_BER_COUNT_FROZEN_BY_ERR_CNT_RO_SIGNAL =
+ 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT1_EO_PG_RX_BER_COUNT_FROZEN_BY_TIMER_RO_SIGNAL = 61
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT1_EO_PG_RX_BER_TIMER_SATURATED_RO_SIGNAL = 62 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT2_EO_PG_RX_BER_TIMER_VALUE_0_15_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT2_EO_PG_RX_BER_TIMER_VALUE_0_15_RO_SIGNAL_LEN = 16
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT3_EO_PG_RX_BER_TIMER_VALUE_16_31_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT3_EO_PG_RX_BER_TIMER_VALUE_16_31_RO_SIGNAL_LEN = 16
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT4_EO_PG_RX_DATA_PIPE_0_15_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT4_EO_PG_RX_DATA_PIPE_0_15_RO_SIGNAL_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT5_EO_PG_RX_DATA_PIPE_16_31_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT5_EO_PG_RX_DATA_PIPE_16_31_RO_SIGNAL_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT6_EO_PG_RX_SERVO_STATUS_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT6_EO_PG_RX_SERVO_STATUS_RO_SIGNAL_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT7_EO_PG_RX_SERVO_CHG_CNT_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT7_EO_PG_RX_SERVO_CHG_CNT_RO_SIGNAL_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT7_EO_PG_RX_PRBS_DATA_RCV_RO_SIGNAL = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT7_EO_PG_RX_PG_PRBS_SEED_DONE_RO_SIGNAL = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT7_EO_PG_RX_DYN_RECAL_TIMER_RUNNING_RO_SIGNAL = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT7_EO_PG_RX_PRVCPT_CHANGE_DET_RO_SIGNAL = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT8_EO_PG_RX_SCAN_P_0_15_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT8_EO_PG_RX_SCAN_P_0_15_RO_SIGNAL_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT9_EO_PG_RX_SCAN_P_16_23_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_DATASM_STAT9_EO_PG_RX_SCAN_P_16_23_RO_SIGNAL_LEN = 9 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR1_ERROR_INJECT_PG_ERR_INJ = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR1_ERROR_INJECT_PG_ERR_INJ_LEN = 15 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR1_MASK_PG_ERRS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR1_MASK_PG_ERRS_LEN = 15 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR1_PG_RX_PG_FIR_ERR_PG_REGS_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR1_PG_RX_PG_FIR_ERR_GCR_BUFF_RO_SIGNAL = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR1_PG_RX_PG_FIR_ERR_GCRS_LD_SM_RO_SIGNAL = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR1_PG_RX_PG_FIR_ERR_GCRS_UNLD_SM_RO_SIGNAL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR1_PG_RX_PG_FIR_ERR_GLBSM_REGS_RO_SIGNAL = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR1_PG_RX_PG_FIR_ERR_GLBSM_REGRW_RO_SIGNAL = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR1_PG_RX_PG_FIR_ERR_DATASM_REGS_RO_SIGNAL = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR1_PG_RX_PG_FIR_ERR_DATASM_REGRW_RO_SIGNAL = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR1_PG_RX_PG_FIR_ERR_EYEOPT_SM_RO_SIGNAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR1_PG_RX_PG_FIR_ERR_BIST_MAIN_STATE_RO_SIGNAL = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR1_PG_RX_PG_FIR_ERR_BIST_INIT_STATE_RO_SIGNAL = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR1_PG_RX_PG_FIR_ERR_RX_SERVO_SM_RO_SIGNAL = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR1_PG_RX_PG_FIR_ERR_WORK_REGS_RO_SIGNAL = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR1_PG_RX_PG_FIR_ERR_SET_SLS_LN_STATE_RO_SIGNAL = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR1_PG_RX_PL_FIR_ERR_RO_SIGNAL = 62 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR2_ERROR_INJECT_PG_ERR_INJ = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR2_ERROR_INJECT_PG_ERR_INJ_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR2_MASK_PG_ERRS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR2_MASK_PG_ERRS_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR2_PG_RX_PG_FIR_ERR_DYN_RPR_SM_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR2_PG_RX_PG_FIR_ERR_DYN_RPR_SND_MSG_SM_RO_SIGNAL = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR2_PG_RX_PG_FIR_ERR_SLS_ENC_SND_MSG_SM_RO_SIGNAL = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR2_PG_RX_PG_FIR_ERR_SLS_HNDSHK_SM_RO_SIGNAL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR2_PG_RX_PG_FIR_ERR_SLS_RCVY_SM_RO_SIGNAL = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR2_PG_RX_PG_FIR_ERR_RECAL_SM_RO_SIGNAL = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR2_PG_RX_PG_FIR_ERR_DYN_RECAL_HNDSHK_SM_RO_SIGNAL = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR2_PG_RX_PG_FIR_ERR_GLB_CAL_SND_MSG_SM_RO_SIGNAL = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR2_PG_RX_PG_FIR_ERR_STAT_RPR_SND_MSG_SM_RO_SIGNAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR2_PG_RX_PG_FIR_ERR_MAIN_INIT_SM_RO_SIGNAL = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR2_PG_RX_PG_FIR_ERR_WTM_SM_RO_SIGNAL = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR2_PG_RX_PG_FIR_ERR_WTR_SM_RO_SIGNAL = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR2_PG_RX_PG_FIR_ERR_WTL_SM_RO_SIGNAL = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR2_PG_RX_PG_FIR_ERR_RPR_SM_RO_SIGNAL = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR2_PG_RX_PG_FIR_ERR_DSM_SM_RO_SIGNAL = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR2_PG_RX_PG_FIR_ERR_RXDSM_SM_RO_SIGNAL = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR_TRAINING_MASK_PG_ERROR = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR_TRAINING_MASK_PG_STATIC_SPARE_DEPLOYED = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR_TRAINING_MASK_PG_STATIC_MAX_SPARES_EXCEEDED = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR_TRAINING_MASK_PG_DYNAMIC_REPAIR_ERROR = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR_TRAINING_MASK_PG_DYNAMIC_SPARE_DEPLOYED = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR_TRAINING_MASK_PG_DYNAMIC_MAX_SPARES_EXCEEDED = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR_TRAINING_MASK_PG_RECAL_ERROR = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR_TRAINING_MASK_PG_RECAL_SPARE_DEPLOYED = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR_TRAINING_MASK_PG_RECAL_MAX_SPARES_EXCEEDED = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR_TRAINING_MASK_PG_TOO_MANY_BUS_ERRORS = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR_TRAINING_PG_ERROR = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR_TRAINING_PG_STATIC_SPARE_DEPLOYED = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR_TRAINING_PG_STATIC_MAX_SPARES_EXCEEDED = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR_TRAINING_PG_DYNAMIC_REPAIR_ERROR = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR_TRAINING_PG_DYNAMIC_SPARE_DEPLOYED = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR_TRAINING_PG_DYNAMIC_MAX_SPARES_EXCEEDED = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR_TRAINING_PG_RECAL_ERROR = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR_TRAINING_PG_RECAL_SPARE_DEPLOYED = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR_TRAINING_PG_RECAL_MAX_SPARES_EXCEEDED = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_FIR_TRAINING_PG_TOO_MANY_BUS_ERRORS = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_CNTL2_EO_PG_DYN_RPR_REQ_MANUAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_CNTL2_EO_PG_CNT_SINGLE_LANE_RECAL = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_CNTL2_EO_PG_RECAL_LANE_TO_MONITOR = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_CNTL2_EO_PG_RECAL_LANE_TO_MONITOR_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_CNTL2_EO_PG_DYN_RPR_SM_MANUAL = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_CNTL2_EO_PG_DIS_SYND_TALLYING = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_CNTL2_EO_PG_ENC_BUS_LANE2RPR_MANUAL = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_CNTL2_EO_PG_ENC_BUS_LANE2RPR_MANUAL_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_CNTL3_EO_PG_MANUAL_RECAL_REQUEST = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_CNTL3_EO_PG_MANUAL_RECAL_LANE = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_CNTL3_EO_PG_MANUAL_RECAL_LANE_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_CNTL3_EO_PG_SLS_TIMEOUT_EXT_SEL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_CNTL3_EO_PG_SLS_TIMEOUT_EXT_SEL_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_CNTL3_EO_PG_HALF_RATE_MODE = 58 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_CNTL4_EO_PG_RX_CLR_RECAL_CNT_WO_PULSE_SLOW_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_CNTL4_EO_PG_RX_INT_RETURN_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_CNTL4_EO_PG_RX_MANUAL_RECAL_ABORT_WO_PULSE_SLOW_SIGNAL =
+ 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_CNTL4_EO_PG_RX_MANUAL_RECAL_CONTINUE_WO_PULSE_SLOW_SIGNAL
+ = 51 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_CNTLX1_EO_PG_CLR_PAR_ERRS = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_CNTLX1_EO_PG_FIR_RESET = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_MODE1_EO_PG_RPR_TX_LD_CNTLS_TIMEOUT_SEL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_MODE1_EO_PG_RPR_TX_LD_CNTLS_TIMEOUT_SEL_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_MODE1_EO_PG_TX_SLS_LN_MV_TIMEOUT_SEL = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_MODE1_EO_PG_TX_SLS_LN_MV_TIMEOUT_SEL_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_MODE1_EO_PG_DESKEW_SKIP_OFFSET = 56 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_SPARE_MODE_PG_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_SPARE_MODE_PG_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_SPARE_MODE_PG_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_SPARE_MODE_PG_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_SPARE_MODE_PG_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_SPARE_MODE_PG_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_SPARE_MODE_PG_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_SPARE_MODE_PG_7 = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_SPARE_MODE_PG_DESKEW_BUMP_AFTER = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_SPARE_MODE_PG_SLS_RCVY_DISABLE = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_SPARE_MODE_PG_SLS_HNDSHK_DISABLE = 58 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT10_E_PG_SERVO_RECAL_IP = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT10_E_PG_RX_DYN_RECAL_MAIN_STATE_RO_SIGNAL = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT10_E_PG_RX_DYN_RECAL_MAIN_STATE_RO_SIGNAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT10_E_PG_RX_DYN_RECAL_HNDSHK_STATE_RO_SIGNAL = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT10_E_PG_RX_DYN_RECAL_HNDSHK_STATE_RO_SIGNAL_LEN = 7
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT11_E_PG_SLS_CMD_VAL_HLD = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT11_E_PG_SLS_CMD_ENCODE_HLD = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT11_E_PG_SLS_CMD_ENCODE_HLD_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT1_EO_PG_RX_EYE_OPT_STATE_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT1_EO_PG_RX_EYE_OPT_STATE_RO_SIGNAL_LEN = 12 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT1_E_PG_RX_MAIN_INIT_STATE_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT1_E_PG_RX_MAIN_INIT_STATE_RO_SIGNAL_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT1_E_PG_RX_WTM_STATE_RO_SIGNAL = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT1_E_PG_RX_WTM_STATE_RO_SIGNAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT1_E_PG_RX_WTR_STATE_RO_SIGNAL = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT1_E_PG_RX_WTR_STATE_RO_SIGNAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT1_E_PG_RX_WT_CU_PLL_LOCK_RO_SIGNAL = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT2_EO_PG_RX_RECAL_CNT_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT2_EO_PG_RX_RECAL_CNT_RO_SIGNAL_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT2_E_PG_RX_WTR_CUR_LANE_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT2_E_PG_RX_WTR_CUR_LANE_RO_SIGNAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT2_E_PG_RX_WTR_BAD_LANE_COUNT_RO_SIGNAL = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT2_E_PG_RX_WTR_BAD_LANE_COUNT_RO_SIGNAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT3_EO_PG_RX_DACTEST_ISGT_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT3_EO_PG_RX_DACTEST_ISLT_RO_SIGNAL = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT3_EO_PG_RX_DACTEST_ISEQ_RO_SIGNAL = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT3_EO_PG_RX_DACTEST_DIFF_RO_SIGNAL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT3_EO_PG_RX_DACTEST_DIFF_RO_SIGNAL_LEN = 9 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT3_E_PG_RX_DSM_STATE_RO_SIGNAL = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT3_E_PG_RX_DSM_STATE_RO_SIGNAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT3_E_PG_RX_RXDSM_STATE_RO_SIGNAL = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT3_E_PG_RX_RXDSM_STATE_RO_SIGNAL_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT4_EO_PG_RX_INT_REQ_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT4_EO_PG_RX_INT_REQ_RO_SIGNAL_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT4_E_PG_RX_RPR_STATE_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT4_E_PG_RX_RPR_STATE_RO_SIGNAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT4_E_PG_RX_SLS_RCVY_STATE_RO_SIGNAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT4_E_PG_RX_SLS_RCVY_STATE_RO_SIGNAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT5_EO_PG_RX_LANE_CURRENTLY_INITIALIZING_RO_SIGNAL = 48
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT5_EO_PG_RX_LANE_CURRENTLY_RECALIBRATING_RO_SIGNAL =
+ 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT5_EO_PG_RX_CURRENT_RECAL_INIT_LANE_RO_SIGNAL = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT5_EO_PG_RX_CURRENT_RECAL_INIT_LANE_RO_SIGNAL_LEN = 5
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT5_EO_PG_RX_MANUAL_RECAL_DONE_RO_SIGNAL = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT7_E_PG_RX_SLS_CMD_VAL_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT7_E_PG_RX_NONSLS_CMD_RO_SIGNAL = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT7_E_PG_RX_SLS_CMD_ENCODE_RO_SIGNAL = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT7_E_PG_RX_SLS_CMD_ENCODE_RO_SIGNAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT7_E_PG_RX_ENC_BUS_LANE2RPR_RO_SIGNAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT7_E_PG_RX_ENC_BUS_LANE2RPR_RO_SIGNAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT7_E_PG_RX_REPAIR_REQ_RO_SIGNAL = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT8_E_PG_RX_SLS_USED_AS_SPR_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT8_E_PG_RX_DYN_RPR_STATE_RO_SIGNAL = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT8_E_PG_RX_DYN_RPR_STATE_RO_SIGNAL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT8_E_PG_RX_SLS_HNDSHK_STATE_RO_SIGNAL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT8_E_PG_RX_SLS_HNDSHK_STATE_RO_SIGNAL_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT9_E_PG_BAD_LANE1 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT9_E_PG_BAD_LANE1_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT9_E_PG_BAD_LANE2 = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT9_E_PG_BAD_LANE2_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT9_E_PG_BAD_LANE_CODE = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_GLBSM_STAT9_E_PG_BAD_LANE_CODE_LEN = 2 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_ID1_PG_BUS_ID = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_ID1_PG_BUS_ID_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_ID2_PG_START_LANE_ID = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_ID2_PG_START_LANE_ID_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_ID2_PG_END_LANE_ID = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_ID2_PG_END_LANE_ID_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_SPARE_MODE_PG_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_SPARE_MODE_PG_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_SPARE_MODE_PG_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_SPARE_MODE_PG_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_RX_SPARE_MODE_PG_4 = 52 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE0_RX_DATA_WORK_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE0_RX_DATA_WORK_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE0_RX_DATA_WORK_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE0_RX_DATA_WORK_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE0_RX_DATA_WORK_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE0_RX_DATA_WORK_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE0_RX_DATA_WORK_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE0_RX_DATA_WORK_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE0_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE0_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE0_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE0_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE0_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE0_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE0_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE0_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE0_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE0_RX_WORK_STAT1_EO_PL_BIST_ERR = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE0_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE0_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE0_RX_WORK_STAT2_EO_PL_A_AP = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE0_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE0_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE0_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE0_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE0_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE10_RX_DATA_WORK_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE10_RX_DATA_WORK_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE10_RX_DATA_WORK_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE10_RX_DATA_WORK_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE10_RX_DATA_WORK_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE10_RX_DATA_WORK_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE10_RX_DATA_WORK_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE10_RX_DATA_WORK_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE10_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE10_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE10_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE10_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE10_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE10_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE10_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE10_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE10_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE10_RX_WORK_STAT1_EO_PL_BIST_ERR = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE10_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE10_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE10_RX_WORK_STAT2_EO_PL_A_AP = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE10_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE10_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE10_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE10_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE10_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE11_RX_DATA_WORK_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE11_RX_DATA_WORK_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE11_RX_DATA_WORK_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE11_RX_DATA_WORK_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE11_RX_DATA_WORK_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE11_RX_DATA_WORK_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE11_RX_DATA_WORK_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE11_RX_DATA_WORK_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE11_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE11_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE11_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE11_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE11_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE11_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE11_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE11_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE11_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE11_RX_WORK_STAT1_EO_PL_BIST_ERR = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE11_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE11_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE11_RX_WORK_STAT2_EO_PL_A_AP = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE11_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE11_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE11_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE11_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE11_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE12_RX_DATA_WORK_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE12_RX_DATA_WORK_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE12_RX_DATA_WORK_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE12_RX_DATA_WORK_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE12_RX_DATA_WORK_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE12_RX_DATA_WORK_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE12_RX_DATA_WORK_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE12_RX_DATA_WORK_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE12_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE12_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE12_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE12_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE12_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE12_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE12_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE12_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE12_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE12_RX_WORK_STAT1_EO_PL_BIST_ERR = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE12_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE12_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE12_RX_WORK_STAT2_EO_PL_A_AP = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE12_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE12_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE12_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE12_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE12_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE13_RX_DATA_WORK_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE13_RX_DATA_WORK_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE13_RX_DATA_WORK_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE13_RX_DATA_WORK_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE13_RX_DATA_WORK_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE13_RX_DATA_WORK_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE13_RX_DATA_WORK_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE13_RX_DATA_WORK_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE13_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE13_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE13_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE13_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE13_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE13_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE13_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE13_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE13_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE13_RX_WORK_STAT1_EO_PL_BIST_ERR = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE13_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE13_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE13_RX_WORK_STAT2_EO_PL_A_AP = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE13_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE13_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE13_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE13_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE13_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE14_RX_DATA_WORK_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE14_RX_DATA_WORK_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE14_RX_DATA_WORK_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE14_RX_DATA_WORK_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE14_RX_DATA_WORK_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE14_RX_DATA_WORK_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE14_RX_DATA_WORK_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE14_RX_DATA_WORK_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE14_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE14_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE14_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE14_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE14_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE14_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE14_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE14_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE14_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE14_RX_WORK_STAT1_EO_PL_BIST_ERR = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE14_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE14_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE14_RX_WORK_STAT2_EO_PL_A_AP = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE14_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE14_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE14_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE14_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE14_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE15_RX_DATA_WORK_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE15_RX_DATA_WORK_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE15_RX_DATA_WORK_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE15_RX_DATA_WORK_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE15_RX_DATA_WORK_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE15_RX_DATA_WORK_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE15_RX_DATA_WORK_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE15_RX_DATA_WORK_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE15_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE15_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE15_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE15_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE15_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE15_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE15_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE15_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE15_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE15_RX_WORK_STAT1_EO_PL_BIST_ERR = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE15_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE15_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE15_RX_WORK_STAT2_EO_PL_A_AP = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE15_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE15_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE15_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE15_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE15_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE16_RX_DATA_WORK_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE16_RX_DATA_WORK_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE16_RX_DATA_WORK_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE16_RX_DATA_WORK_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE16_RX_DATA_WORK_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE16_RX_DATA_WORK_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE16_RX_DATA_WORK_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE16_RX_DATA_WORK_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE16_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE16_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE16_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE16_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE16_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE16_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE16_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE16_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE16_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE16_RX_WORK_STAT1_EO_PL_BIST_ERR = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE16_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE16_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE16_RX_WORK_STAT2_EO_PL_A_AP = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE16_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE16_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE16_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE16_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE16_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE17_RX_DATA_WORK_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE17_RX_DATA_WORK_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE17_RX_DATA_WORK_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE17_RX_DATA_WORK_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE17_RX_DATA_WORK_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE17_RX_DATA_WORK_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE17_RX_DATA_WORK_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE17_RX_DATA_WORK_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE17_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE17_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE17_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE17_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE17_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE17_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE17_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE17_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE17_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE17_RX_WORK_STAT1_EO_PL_BIST_ERR = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE17_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE17_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE17_RX_WORK_STAT2_EO_PL_A_AP = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE17_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE17_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE17_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE17_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE17_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE18_RX_DATA_WORK_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE18_RX_DATA_WORK_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE18_RX_DATA_WORK_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE18_RX_DATA_WORK_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE18_RX_DATA_WORK_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE18_RX_DATA_WORK_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE18_RX_DATA_WORK_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE18_RX_DATA_WORK_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE18_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE18_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE18_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE18_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE18_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE18_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE18_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE18_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE18_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE18_RX_WORK_STAT1_EO_PL_BIST_ERR = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE18_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE18_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE18_RX_WORK_STAT2_EO_PL_A_AP = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE18_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE18_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE18_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE18_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE18_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE19_RX_DATA_WORK_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE19_RX_DATA_WORK_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE19_RX_DATA_WORK_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE19_RX_DATA_WORK_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE19_RX_DATA_WORK_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE19_RX_DATA_WORK_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE19_RX_DATA_WORK_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE19_RX_DATA_WORK_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE19_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE19_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE19_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE19_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE19_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE19_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE19_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE19_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE19_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE19_RX_WORK_STAT1_EO_PL_BIST_ERR = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE19_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE19_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE19_RX_WORK_STAT2_EO_PL_A_AP = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE19_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE19_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE19_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE19_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE19_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE1_RX_DATA_WORK_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE1_RX_DATA_WORK_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE1_RX_DATA_WORK_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE1_RX_DATA_WORK_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE1_RX_DATA_WORK_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE1_RX_DATA_WORK_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE1_RX_DATA_WORK_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE1_RX_DATA_WORK_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE1_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE1_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE1_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE1_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE1_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE1_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE1_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE1_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE1_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE1_RX_WORK_STAT1_EO_PL_BIST_ERR = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE1_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE1_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE1_RX_WORK_STAT2_EO_PL_A_AP = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE1_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE1_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE1_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE1_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE1_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE20_RX_DATA_WORK_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE20_RX_DATA_WORK_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE20_RX_DATA_WORK_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE20_RX_DATA_WORK_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE20_RX_DATA_WORK_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE20_RX_DATA_WORK_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE20_RX_DATA_WORK_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE20_RX_DATA_WORK_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE20_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE20_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE20_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE20_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE20_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE20_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE20_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE20_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE20_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE20_RX_WORK_STAT1_EO_PL_BIST_ERR = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE20_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE20_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE20_RX_WORK_STAT2_EO_PL_A_AP = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE20_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE20_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE20_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE20_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE20_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE21_RX_DATA_WORK_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE21_RX_DATA_WORK_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE21_RX_DATA_WORK_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE21_RX_DATA_WORK_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE21_RX_DATA_WORK_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE21_RX_DATA_WORK_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE21_RX_DATA_WORK_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE21_RX_DATA_WORK_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE21_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE21_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE21_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE21_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE21_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE21_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE21_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE21_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE21_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE21_RX_WORK_STAT1_EO_PL_BIST_ERR = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE21_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE21_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE21_RX_WORK_STAT2_EO_PL_A_AP = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE21_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE21_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE21_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE21_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE21_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE22_RX_DATA_WORK_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE22_RX_DATA_WORK_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE22_RX_DATA_WORK_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE22_RX_DATA_WORK_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE22_RX_DATA_WORK_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE22_RX_DATA_WORK_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE22_RX_DATA_WORK_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE22_RX_DATA_WORK_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE22_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE22_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE22_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE22_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE22_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE22_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE22_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE22_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE22_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE22_RX_WORK_STAT1_EO_PL_BIST_ERR = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE22_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE22_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE22_RX_WORK_STAT2_EO_PL_A_AP = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE22_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE22_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE22_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE22_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE22_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE23_RX_DATA_WORK_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE23_RX_DATA_WORK_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE23_RX_DATA_WORK_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE23_RX_DATA_WORK_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE23_RX_DATA_WORK_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE23_RX_DATA_WORK_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE23_RX_DATA_WORK_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE23_RX_DATA_WORK_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE23_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE23_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE23_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE23_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE23_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE23_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE23_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE23_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE23_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE23_RX_WORK_STAT1_EO_PL_BIST_ERR = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE23_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE23_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE23_RX_WORK_STAT2_EO_PL_A_AP = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE23_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE23_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE23_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE23_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE23_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE2_RX_DATA_WORK_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE2_RX_DATA_WORK_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE2_RX_DATA_WORK_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE2_RX_DATA_WORK_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE2_RX_DATA_WORK_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE2_RX_DATA_WORK_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE2_RX_DATA_WORK_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE2_RX_DATA_WORK_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE2_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE2_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE2_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE2_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE2_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE2_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE2_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE2_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE2_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE2_RX_WORK_STAT1_EO_PL_BIST_ERR = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE2_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE2_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE2_RX_WORK_STAT2_EO_PL_A_AP = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE2_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE2_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE2_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE2_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE2_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE3_RX_DATA_WORK_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE3_RX_DATA_WORK_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE3_RX_DATA_WORK_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE3_RX_DATA_WORK_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE3_RX_DATA_WORK_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE3_RX_DATA_WORK_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE3_RX_DATA_WORK_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE3_RX_DATA_WORK_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE3_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE3_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE3_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE3_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE3_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE3_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE3_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE3_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE3_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE3_RX_WORK_STAT1_EO_PL_BIST_ERR = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE3_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE3_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE3_RX_WORK_STAT2_EO_PL_A_AP = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE3_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE3_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE3_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE3_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE3_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE4_RX_DATA_WORK_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE4_RX_DATA_WORK_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE4_RX_DATA_WORK_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE4_RX_DATA_WORK_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE4_RX_DATA_WORK_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE4_RX_DATA_WORK_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE4_RX_DATA_WORK_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE4_RX_DATA_WORK_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE4_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE4_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE4_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE4_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE4_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE4_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE4_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE4_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE4_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE4_RX_WORK_STAT1_EO_PL_BIST_ERR = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE4_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE4_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE4_RX_WORK_STAT2_EO_PL_A_AP = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE4_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE4_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE4_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE4_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE4_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE5_RX_DATA_WORK_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE5_RX_DATA_WORK_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE5_RX_DATA_WORK_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE5_RX_DATA_WORK_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE5_RX_DATA_WORK_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE5_RX_DATA_WORK_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE5_RX_DATA_WORK_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE5_RX_DATA_WORK_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE5_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE5_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE5_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE5_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE5_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE5_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE5_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE5_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE5_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE5_RX_WORK_STAT1_EO_PL_BIST_ERR = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE5_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE5_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE5_RX_WORK_STAT2_EO_PL_A_AP = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE5_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE5_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE5_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE5_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE5_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE6_RX_DATA_WORK_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE6_RX_DATA_WORK_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE6_RX_DATA_WORK_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE6_RX_DATA_WORK_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE6_RX_DATA_WORK_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE6_RX_DATA_WORK_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE6_RX_DATA_WORK_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE6_RX_DATA_WORK_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE6_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE6_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE6_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE6_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE6_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE6_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE6_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE6_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE6_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE6_RX_WORK_STAT1_EO_PL_BIST_ERR = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE6_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE6_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE6_RX_WORK_STAT2_EO_PL_A_AP = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE6_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE6_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE6_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE6_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE6_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE7_RX_DATA_WORK_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE7_RX_DATA_WORK_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE7_RX_DATA_WORK_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE7_RX_DATA_WORK_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE7_RX_DATA_WORK_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE7_RX_DATA_WORK_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE7_RX_DATA_WORK_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE7_RX_DATA_WORK_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE7_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE7_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE7_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE7_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE7_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE7_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE7_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE7_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE7_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE7_RX_WORK_STAT1_EO_PL_BIST_ERR = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE7_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE7_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE7_RX_WORK_STAT2_EO_PL_A_AP = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE7_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE7_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE7_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE7_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE7_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE8_RX_DATA_WORK_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE8_RX_DATA_WORK_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE8_RX_DATA_WORK_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE8_RX_DATA_WORK_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE8_RX_DATA_WORK_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE8_RX_DATA_WORK_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE8_RX_DATA_WORK_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE8_RX_DATA_WORK_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE8_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE8_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE8_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE8_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE8_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE8_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE8_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE8_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE8_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE8_RX_WORK_STAT1_EO_PL_BIST_ERR = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE8_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE8_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE8_RX_WORK_STAT2_EO_PL_A_AP = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE8_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE8_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE8_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE8_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE8_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE9_RX_DATA_WORK_SPARE_MODE_PL_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE9_RX_DATA_WORK_SPARE_MODE_PL_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE9_RX_DATA_WORK_SPARE_MODE_PL_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE9_RX_DATA_WORK_SPARE_MODE_PL_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE9_RX_DATA_WORK_SPARE_MODE_PL_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE9_RX_DATA_WORK_SPARE_MODE_PL_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE9_RX_DATA_WORK_SPARE_MODE_PL_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE9_RX_DATA_WORK_SPARE_MODE_PL_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE9_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE9_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE9_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE9_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE9_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE9_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE9_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE9_RX_WORK_STAT1_EO_PL_BAD_SKEW = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE9_RX_WORK_STAT1_EO_PL_BAD_DESKEW = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE9_RX_WORK_STAT1_EO_PL_BIST_ERR = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE9_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE9_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE9_RX_WORK_STAT2_EO_PL_A_AP = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE9_RX_WORK_STAT2_EO_PL_A_AP_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE9_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE9_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE9_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX1_SLICE9_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX_FIR_ERROR_INJECT_PB_ERRS_INJ = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX_FIR_ERROR_INJECT_PB_ERRS_INJ_LEN = 10 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX_FIR_MASK_PB_ERRS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX_FIR_MASK_PB_ERRS_LEN = 10 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX_FIR_PB_RX_PB_FIR_ERRS_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX_FIR_PB_RX_PB_FIR_ERRS_RO_SIGNAL_LEN = 10 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX_FIR_RESET_PB_CLR_PAR_ERRS = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_RX_FIR_RESET_PB_RESET = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_SCOM_MODE_PB_GCR_TEST = 0 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_SCOM_MODE_PB_ENABLE_GCR_OFL_BUFF = 1 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_SCOM_MODE_PB_IORESET_HARD_BUS0 = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_SCOM_MODE_PB_MMIO_PG_REG_ACCESS = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_SCOM_MODE_PB_SPARES1 = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_SCOM_MODE_PB_SPARES1_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_SCOM_MODE_PB_GCR_HANG_DET_SEL = 8 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_SCOM_MODE_PB_GCR_HANG_DET_SEL_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_SCOM_MODE_PB_GCR_BUFFER_ENABLED_RO_SIGNAL = 11 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_SCOM_MODE_PB_GCR_HANG_ERROR_MASK = 12 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_SCOM_MODE_PB_GCR_HANG_ERROR_INJ = 13 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_SCOM_MODE_PB_PPE_GCR = 14 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_SCOM_MODE_PB_CHAN_FAIL_MASK = 15 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_SCOM_MODE_PB_CHAN_FAIL_MASK_LEN = 8 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_SCOM_MODE_PB_SPARES2 = 23 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_SCOM_MODE_PB_SPARES2_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_SPARE_MODE_PB_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_SPARE_MODE_PB_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_SPARE_MODE_PB_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_SPARE_MODE_PB_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_SPARE_MODE_PB_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_SPARE_MODE_PB_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_SPARE_MODE_PB_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_SPARE_MODE_PB_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL =
+ 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL =
+ 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
+ = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
+ = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 57 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 59 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_CNTL3_EO_PL_TDR_ENABLE = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_FIR_MASK_PL_ERRS = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_MODE1_PL_LANE_PDWN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_MODE1_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_MODE1_PL_LANE_QUIESCE = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_MODE1_PL_LANE_QUIESCE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_MODE1_PL_PSAVE_MODE_DISABLE = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_MODE1_PL_ERR_INJ_A_SLS_ENABLE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_MODE1_PL_SPARE_MODE_0 = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_MODE1_PL_SPARE_MODE_1 = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_MODE1_PL_SPARE_MODE_2 = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_MODE1_PL_SPARE_MODE_3 = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_MODE2_PL_NEXT_CAL_LANE_SEL = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_MODE2_PL_PRBS_SCRAMBLE_MODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_MODE2_PL_UNLOAD_SEL = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_MODE2_PL_UNLOAD_SEL_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_MODE2_PL_PDWN_LITE = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_MODE2_PL_CAL_LANE_SEL = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_STAT1_PL_LANE_BIST_ERR = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE0_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL =
+ 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL =
+ 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
+ = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
+ = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 57 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 59 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_CNTL3_EO_PL_TDR_ENABLE = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_FIR_MASK_PL_ERRS = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_MODE1_PL_LANE_PDWN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_MODE1_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_MODE1_PL_LANE_QUIESCE = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_MODE1_PL_LANE_QUIESCE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_MODE1_PL_PSAVE_MODE_DISABLE = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_MODE1_PL_ERR_INJ_A_SLS_ENABLE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_MODE1_PL_SPARE_MODE_0 = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_MODE1_PL_SPARE_MODE_1 = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_MODE1_PL_SPARE_MODE_2 = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_MODE1_PL_SPARE_MODE_3 = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_MODE2_PL_NEXT_CAL_LANE_SEL = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_MODE2_PL_PRBS_SCRAMBLE_MODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_MODE2_PL_UNLOAD_SEL = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_MODE2_PL_UNLOAD_SEL_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_MODE2_PL_PDWN_LITE = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_MODE2_PL_CAL_LANE_SEL = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_STAT1_PL_LANE_BIST_ERR = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE1_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL =
+ 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL =
+ 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
+ = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
+ = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 57 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 59 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_CNTL3_EO_PL_TDR_ENABLE = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_FIR_MASK_PL_ERRS = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_MODE1_PL_LANE_PDWN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_MODE1_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_MODE1_PL_LANE_QUIESCE = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_MODE1_PL_LANE_QUIESCE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_MODE1_PL_PSAVE_MODE_DISABLE = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_MODE1_PL_ERR_INJ_A_SLS_ENABLE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_MODE1_PL_SPARE_MODE_0 = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_MODE1_PL_SPARE_MODE_1 = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_MODE1_PL_SPARE_MODE_2 = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_MODE1_PL_SPARE_MODE_3 = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_MODE2_PL_NEXT_CAL_LANE_SEL = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_MODE2_PL_PRBS_SCRAMBLE_MODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_MODE2_PL_UNLOAD_SEL = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_MODE2_PL_UNLOAD_SEL_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_MODE2_PL_PDWN_LITE = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_MODE2_PL_CAL_LANE_SEL = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_STAT1_PL_LANE_BIST_ERR = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE2_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL =
+ 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL =
+ 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
+ = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
+ = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 57 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 59 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_CNTL3_EO_PL_TDR_ENABLE = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_FIR_MASK_PL_ERRS = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_MODE1_PL_LANE_PDWN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_MODE1_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_MODE1_PL_LANE_QUIESCE = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_MODE1_PL_LANE_QUIESCE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_MODE1_PL_PSAVE_MODE_DISABLE = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_MODE1_PL_ERR_INJ_A_SLS_ENABLE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_MODE1_PL_SPARE_MODE_0 = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_MODE1_PL_SPARE_MODE_1 = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_MODE1_PL_SPARE_MODE_2 = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_MODE1_PL_SPARE_MODE_3 = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_MODE2_PL_NEXT_CAL_LANE_SEL = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_MODE2_PL_PRBS_SCRAMBLE_MODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_MODE2_PL_UNLOAD_SEL = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_MODE2_PL_UNLOAD_SEL_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_MODE2_PL_PDWN_LITE = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_MODE2_PL_CAL_LANE_SEL = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_STAT1_PL_LANE_BIST_ERR = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS0_SLICE3_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL =
+ 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL =
+ 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
+ = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
+ = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 57 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 59 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_CNTL3_EO_PL_TDR_ENABLE = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_FIR_MASK_PL_ERRS = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_MODE1_PL_LANE_PDWN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_MODE1_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_MODE1_PL_LANE_QUIESCE = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_MODE1_PL_LANE_QUIESCE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_MODE1_PL_PSAVE_MODE_DISABLE = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_MODE1_PL_ERR_INJ_A_SLS_ENABLE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_MODE1_PL_SPARE_MODE_0 = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_MODE1_PL_SPARE_MODE_1 = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_MODE1_PL_SPARE_MODE_2 = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_MODE1_PL_SPARE_MODE_3 = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_MODE2_PL_NEXT_CAL_LANE_SEL = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_MODE2_PL_PRBS_SCRAMBLE_MODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_MODE2_PL_UNLOAD_SEL = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_MODE2_PL_UNLOAD_SEL_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_MODE2_PL_PDWN_LITE = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_MODE2_PL_CAL_LANE_SEL = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_STAT1_PL_LANE_BIST_ERR = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE0_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL =
+ 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL =
+ 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
+ = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
+ = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 57 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 59 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_CNTL3_EO_PL_TDR_ENABLE = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_FIR_MASK_PL_ERRS = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_MODE1_PL_LANE_PDWN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_MODE1_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_MODE1_PL_LANE_QUIESCE = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_MODE1_PL_LANE_QUIESCE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_MODE1_PL_PSAVE_MODE_DISABLE = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_MODE1_PL_ERR_INJ_A_SLS_ENABLE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_MODE1_PL_SPARE_MODE_0 = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_MODE1_PL_SPARE_MODE_1 = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_MODE1_PL_SPARE_MODE_2 = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_MODE1_PL_SPARE_MODE_3 = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_MODE2_PL_NEXT_CAL_LANE_SEL = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_MODE2_PL_PRBS_SCRAMBLE_MODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_MODE2_PL_UNLOAD_SEL = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_MODE2_PL_UNLOAD_SEL_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_MODE2_PL_PDWN_LITE = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_MODE2_PL_CAL_LANE_SEL = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_STAT1_PL_LANE_BIST_ERR = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE1_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL =
+ 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL =
+ 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
+ = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
+ = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 57 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 59 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_CNTL3_EO_PL_TDR_ENABLE = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_FIR_MASK_PL_ERRS = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_MODE1_PL_LANE_PDWN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_MODE1_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_MODE1_PL_LANE_QUIESCE = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_MODE1_PL_LANE_QUIESCE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_MODE1_PL_PSAVE_MODE_DISABLE = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_MODE1_PL_ERR_INJ_A_SLS_ENABLE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_MODE1_PL_SPARE_MODE_0 = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_MODE1_PL_SPARE_MODE_1 = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_MODE1_PL_SPARE_MODE_2 = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_MODE1_PL_SPARE_MODE_3 = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_MODE2_PL_NEXT_CAL_LANE_SEL = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_MODE2_PL_PRBS_SCRAMBLE_MODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_MODE2_PL_UNLOAD_SEL = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_MODE2_PL_UNLOAD_SEL_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_MODE2_PL_PDWN_LITE = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_MODE2_PL_CAL_LANE_SEL = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_STAT1_PL_LANE_BIST_ERR = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE2_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL =
+ 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL =
+ 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
+ = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
+ = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 57 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 59 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_CNTL3_EO_PL_TDR_ENABLE = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_FIR_MASK_PL_ERRS = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_MODE1_PL_LANE_PDWN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_MODE1_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_MODE1_PL_LANE_QUIESCE = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_MODE1_PL_LANE_QUIESCE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_MODE1_PL_PSAVE_MODE_DISABLE = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_MODE1_PL_ERR_INJ_A_SLS_ENABLE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_MODE1_PL_SPARE_MODE_0 = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_MODE1_PL_SPARE_MODE_1 = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_MODE1_PL_SPARE_MODE_2 = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_MODE1_PL_SPARE_MODE_3 = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_MODE2_PL_NEXT_CAL_LANE_SEL = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_MODE2_PL_PRBS_SCRAMBLE_MODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_MODE2_PL_UNLOAD_SEL = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_MODE2_PL_UNLOAD_SEL_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_MODE2_PL_PDWN_LITE = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_MODE2_PL_CAL_LANE_SEL = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_STAT1_PL_LANE_BIST_ERR = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS1_SLICE3_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL =
+ 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL =
+ 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
+ = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
+ = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 57 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 59 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_CNTL3_EO_PL_TDR_ENABLE = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_FIR_MASK_PL_ERRS = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_MODE1_PL_LANE_PDWN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_MODE1_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_MODE1_PL_LANE_QUIESCE = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_MODE1_PL_LANE_QUIESCE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_MODE1_PL_PSAVE_MODE_DISABLE = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_MODE1_PL_ERR_INJ_A_SLS_ENABLE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_MODE1_PL_SPARE_MODE_0 = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_MODE1_PL_SPARE_MODE_1 = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_MODE1_PL_SPARE_MODE_2 = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_MODE1_PL_SPARE_MODE_3 = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_MODE2_PL_NEXT_CAL_LANE_SEL = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_MODE2_PL_PRBS_SCRAMBLE_MODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_MODE2_PL_UNLOAD_SEL = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_MODE2_PL_UNLOAD_SEL_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_MODE2_PL_PDWN_LITE = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_MODE2_PL_CAL_LANE_SEL = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_STAT1_PL_LANE_BIST_ERR = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE0_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL =
+ 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL =
+ 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
+ = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
+ = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 57 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 59 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_CNTL3_EO_PL_TDR_ENABLE = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_FIR_MASK_PL_ERRS = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_MODE1_PL_LANE_PDWN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_MODE1_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_MODE1_PL_LANE_QUIESCE = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_MODE1_PL_LANE_QUIESCE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_MODE1_PL_PSAVE_MODE_DISABLE = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_MODE1_PL_ERR_INJ_A_SLS_ENABLE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_MODE1_PL_SPARE_MODE_0 = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_MODE1_PL_SPARE_MODE_1 = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_MODE1_PL_SPARE_MODE_2 = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_MODE1_PL_SPARE_MODE_3 = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_MODE2_PL_NEXT_CAL_LANE_SEL = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_MODE2_PL_PRBS_SCRAMBLE_MODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_MODE2_PL_UNLOAD_SEL = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_MODE2_PL_UNLOAD_SEL_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_MODE2_PL_PDWN_LITE = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_MODE2_PL_CAL_LANE_SEL = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_STAT1_PL_LANE_BIST_ERR = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE1_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL =
+ 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL =
+ 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
+ = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
+ = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 57 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 59 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_CNTL3_EO_PL_TDR_ENABLE = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_FIR_MASK_PL_ERRS = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_MODE1_PL_LANE_PDWN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_MODE1_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_MODE1_PL_LANE_QUIESCE = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_MODE1_PL_LANE_QUIESCE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_MODE1_PL_PSAVE_MODE_DISABLE = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_MODE1_PL_ERR_INJ_A_SLS_ENABLE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_MODE1_PL_SPARE_MODE_0 = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_MODE1_PL_SPARE_MODE_1 = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_MODE1_PL_SPARE_MODE_2 = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_MODE1_PL_SPARE_MODE_3 = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_MODE2_PL_NEXT_CAL_LANE_SEL = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_MODE2_PL_PRBS_SCRAMBLE_MODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_MODE2_PL_UNLOAD_SEL = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_MODE2_PL_UNLOAD_SEL_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_MODE2_PL_PDWN_LITE = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_MODE2_PL_CAL_LANE_SEL = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_STAT1_PL_LANE_BIST_ERR = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE2_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL =
+ 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL =
+ 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
+ = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
+ = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 57 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 59 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_CNTL3_EO_PL_TDR_ENABLE = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_FIR_MASK_PL_ERRS = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_MODE1_PL_LANE_PDWN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_MODE1_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_MODE1_PL_LANE_QUIESCE = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_MODE1_PL_LANE_QUIESCE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_MODE1_PL_PSAVE_MODE_DISABLE = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_MODE1_PL_ERR_INJ_A_SLS_ENABLE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_MODE1_PL_SPARE_MODE_0 = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_MODE1_PL_SPARE_MODE_1 = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_MODE1_PL_SPARE_MODE_2 = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_MODE1_PL_SPARE_MODE_3 = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_MODE2_PL_NEXT_CAL_LANE_SEL = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_MODE2_PL_PRBS_SCRAMBLE_MODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_MODE2_PL_UNLOAD_SEL = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_MODE2_PL_UNLOAD_SEL_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_MODE2_PL_PDWN_LITE = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_MODE2_PL_CAL_LANE_SEL = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_STAT1_PL_LANE_BIST_ERR = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS2_SLICE3_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL =
+ 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL =
+ 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
+ = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
+ = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 57 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 59 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_CNTL3_EO_PL_TDR_ENABLE = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_FIR_MASK_PL_ERRS = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_MODE1_PL_LANE_PDWN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_MODE1_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_MODE1_PL_LANE_QUIESCE = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_MODE1_PL_LANE_QUIESCE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_MODE1_PL_PSAVE_MODE_DISABLE = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_MODE1_PL_ERR_INJ_A_SLS_ENABLE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_MODE1_PL_SPARE_MODE_0 = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_MODE1_PL_SPARE_MODE_1 = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_MODE1_PL_SPARE_MODE_2 = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_MODE1_PL_SPARE_MODE_3 = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_MODE2_PL_NEXT_CAL_LANE_SEL = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_MODE2_PL_PRBS_SCRAMBLE_MODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_MODE2_PL_UNLOAD_SEL = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_MODE2_PL_UNLOAD_SEL_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_MODE2_PL_PDWN_LITE = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_MODE2_PL_CAL_LANE_SEL = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_STAT1_PL_LANE_BIST_ERR = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE0_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL =
+ 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL =
+ 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
+ = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
+ = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 57 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 59 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_CNTL3_EO_PL_TDR_ENABLE = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_FIR_MASK_PL_ERRS = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_MODE1_PL_LANE_PDWN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_MODE1_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_MODE1_PL_LANE_QUIESCE = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_MODE1_PL_LANE_QUIESCE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_MODE1_PL_PSAVE_MODE_DISABLE = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_MODE1_PL_ERR_INJ_A_SLS_ENABLE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_MODE1_PL_SPARE_MODE_0 = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_MODE1_PL_SPARE_MODE_1 = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_MODE1_PL_SPARE_MODE_2 = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_MODE1_PL_SPARE_MODE_3 = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_MODE2_PL_NEXT_CAL_LANE_SEL = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_MODE2_PL_PRBS_SCRAMBLE_MODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_MODE2_PL_UNLOAD_SEL = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_MODE2_PL_UNLOAD_SEL_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_MODE2_PL_PDWN_LITE = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_MODE2_PL_CAL_LANE_SEL = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_STAT1_PL_LANE_BIST_ERR = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE1_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL =
+ 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL =
+ 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
+ = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
+ = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 57 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 59 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_CNTL3_EO_PL_TDR_ENABLE = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_FIR_MASK_PL_ERRS = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_MODE1_PL_LANE_PDWN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_MODE1_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_MODE1_PL_LANE_QUIESCE = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_MODE1_PL_LANE_QUIESCE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_MODE1_PL_PSAVE_MODE_DISABLE = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_MODE1_PL_ERR_INJ_A_SLS_ENABLE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_MODE1_PL_SPARE_MODE_0 = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_MODE1_PL_SPARE_MODE_1 = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_MODE1_PL_SPARE_MODE_2 = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_MODE1_PL_SPARE_MODE_3 = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_MODE2_PL_NEXT_CAL_LANE_SEL = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_MODE2_PL_PRBS_SCRAMBLE_MODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_MODE2_PL_UNLOAD_SEL = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_MODE2_PL_UNLOAD_SEL_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_MODE2_PL_PDWN_LITE = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_MODE2_PL_CAL_LANE_SEL = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_STAT1_PL_LANE_BIST_ERR = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE2_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL =
+ 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL =
+ 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
+ = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
+ = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 57 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 59 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_CNTL3_EO_PL_TDR_ENABLE = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_FIR_MASK_PL_ERRS = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_MODE1_PL_LANE_PDWN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_MODE1_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_MODE1_PL_LANE_QUIESCE = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_MODE1_PL_LANE_QUIESCE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_MODE1_PL_PSAVE_MODE_DISABLE = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_MODE1_PL_ERR_INJ_A_SLS_ENABLE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_MODE1_PL_SPARE_MODE_0 = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_MODE1_PL_SPARE_MODE_1 = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_MODE1_PL_SPARE_MODE_2 = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_MODE1_PL_SPARE_MODE_3 = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_MODE2_PL_NEXT_CAL_LANE_SEL = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_MODE2_PL_PRBS_SCRAMBLE_MODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_MODE2_PL_UNLOAD_SEL = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_MODE2_PL_UNLOAD_SEL_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_MODE2_PL_PDWN_LITE = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_MODE2_PL_CAL_LANE_SEL = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_STAT1_PL_LANE_BIST_ERR = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE3_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL =
+ 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL =
+ 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
+ = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
+ = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 57 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 59 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_CNTL3_EO_PL_TDR_ENABLE = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_FIR_MASK_PL_ERRS = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_MODE1_PL_LANE_PDWN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_MODE1_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_MODE1_PL_LANE_QUIESCE = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_MODE1_PL_LANE_QUIESCE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_MODE1_PL_PSAVE_MODE_DISABLE = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_MODE1_PL_ERR_INJ_A_SLS_ENABLE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_MODE1_PL_SPARE_MODE_0 = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_MODE1_PL_SPARE_MODE_1 = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_MODE1_PL_SPARE_MODE_2 = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_MODE1_PL_SPARE_MODE_3 = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_MODE2_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_MODE2_PL_NEXT_CAL_LANE_SEL = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_MODE2_PL_PRBS_SCRAMBLE_MODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_MODE2_PL_UNLOAD_SEL = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_MODE2_PL_UNLOAD_SEL_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_MODE2_PL_PDWN_LITE = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_MODE2_PL_CAL_LANE_SEL = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_STAT1_PL_LANE_BIST_ERR = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_STAT1_PL_SEG_TEST_STATUS = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TXPACKS3_SLICE4_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_CNTL1_EO_PG_PSEG_PRE_EN = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_CNTL1_EO_PG_PSEG_PRE_EN_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_CNTL1_EO_PG_PSEG_PRE_SEL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_CNTL1_EO_PG_PSEG_PRE_SEL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_CNTL2_EO_PG_NSEG_PRE_EN = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_CNTL2_EO_PG_NSEG_PRE_EN_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_CNTL2_EO_PG_NSEG_PRE_SEL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_CNTL2_EO_PG_NSEG_PRE_SEL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_CNTL3_EO_PG_PSEG_MARGINPU_EN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_CNTL3_EO_PG_PSEG_MARGINPU_EN_LEN = 8 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_CNTL3_EO_PG_PSEG_MARGINPD_EN = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_CNTL3_EO_PG_PSEG_MARGINPD_EN_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_CNTL4_EO_PG_NSEG_MARGINPU_EN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_CNTL4_EO_PG_NSEG_MARGINPU_EN_LEN = 8 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_CNTL4_EO_PG_NSEG_MARGINPD_EN = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_CNTL4_EO_PG_NSEG_MARGINPD_EN_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_CNTL5_EO_PG_MARGINPU_SEL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_CNTL5_EO_PG_MARGINPU_SEL_LEN = 8 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_CNTL5_EO_PG_MARGINPD_SEL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_CNTL5_EO_PG_MARGINPD_SEL_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_CNTL6_EO_PG_PSEG_MAIN_EN = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_CNTL6_EO_PG_PSEG_MAIN_EN_LEN = 13 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_CNTL7_EO_PG_NSEG_MAIN_EN = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_CNTL7_EO_PG_NSEG_MAIN_EN_LEN = 13 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_CNTLG1_E_PG_TX_DRV_SYNC_PATTERN_GCRMSG_WO_PULSE_SLOW_SIGNAL = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_MODE1_EO_PG_PSAVE_WAKEUP_LANE0_ENABLE = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_MODE1_EO_PG_PSAVE_FENCE_ENABLE = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_MODE1_EO_PG_SEG_TEST_MODE = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_MODE1_EO_PG_SEG_TEST_MODE_LEN = 8 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_MODE1_EO_PG_FFE_BOOST_EN = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_MODE1_EO_PG_SEG_TEST_LEAKAGE_CTRL = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_MODE1_EO_PG_HALF_RATE_MODE = 62 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_SPARE_MODE_PG_CTL_SM_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_SPARE_MODE_PG_CTL_SM_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_SPARE_MODE_PG_CTL_SM_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_SPARE_MODE_PG_CTL_SM_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_SPARE_MODE_PG_CTL_SM_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_SPARE_MODE_PG_CTL_SM_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_SPARE_MODE_PG_CTL_SM_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_SPARE_MODE_PG_CTL_SM_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_STAT1_EO_PG_CLK_BIST_ERR = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_STAT1_EO_PG_CLK_BIST_ACTIVITY_DET = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_STAT1_EO_PG_TX_BIST_DONE_RO_SIGNAL = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_STAT1_EO_PG_TX_SLS_HNDSHK_STATE_RO_SIGNAL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_STAT1_EO_PG_TX_SLS_HNDSHK_STATE_RO_SIGNAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_STAT1_E_PG_SEG_TEST_CLK_STATUS = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTLSM_STAT1_E_PG_SEG_TEST_CLK_STATUS_LEN = 2 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTL10_EO_PG_TDR_PULSE_WIDTH = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTL10_EO_PG_TDR_PULSE_WIDTH_LEN = 9 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTL2_EO_PG_ERR_INJ_A_FINE_SEL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTL2_EO_PG_ERR_INJ_A_FINE_SEL_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTL2_EO_PG_ERR_INJ_A_COARSE_SEL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTL2_EO_PG_ERR_INJ_A_COARSE_SEL_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTL2_EO_PG_ERR_INJ_A_BER_SEL = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTL2_EO_PG_ERR_INJ_A_BER_SEL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTL2_EO_PG_ERR_INJ_ENABLE = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTL2_EO_PG_ERR_INJ_CLOCK_ENABLE = 62 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTL2_E_PG_IORESET = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTL2_E_PG_ERR_INJ_SLS_MODE = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTL2_E_PG_ERR_INJ_SLS_ALL_CMD = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTL2_E_PG_ERR_INJ_SLS_RECAL = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTL2_E_PG_ERR_INJ_SLS_CMD = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTL2_E_PG_ERR_INJ_SLS_CMD_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTL3_EO_PG_ERR_INJ_B_FINE_SEL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTL3_EO_PG_ERR_INJ_B_FINE_SEL_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTL3_EO_PG_ERR_INJ_B_COARSE_SEL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTL3_EO_PG_ERR_INJ_B_COARSE_SEL_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTL3_EO_PG_ERR_INJ_B_BER_SEL = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTL3_EO_PG_ERR_INJ_B_BER_SEL_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTL8_EO_PG_TDR_DAC_CNTL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTL8_EO_PG_TDR_DAC_CNTL_LEN = 8 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTL8_EO_PG_TDR_PHASE_SEL = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTL9_EO_PG_TDR_PULSE_OFFSET = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTL9_EO_PG_TDR_PULSE_OFFSET_LEN = 14 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTLG1_EO_PG_DRV_CLK_PATTERN_GCRMSG = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTLG1_EO_PG_DRV_CLK_PATTERN_GCRMSG_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTLG1_EO_PG_DRV_DATA_PATTERN_GCRMSG = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTLG1_EO_PG_DRV_DATA_PATTERN_GCRMSG_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTLG3_E_PG_SND_SLS_CMD_GCRMSG = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTLG3_E_PG_DYN_RECAL_TSR_IGNORE_GCRMSG = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTLG3_E_PG_SLS_CMD_GCRMSG = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTLG3_E_PG_SLS_CMD_GCRMSG_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTLG3_E_PG_SND_SLS_CMD_PREV_GCRMSG = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTLG3_E_PG_SND_SLS_USING_REG_SCRAMBLE = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTLG4_E_PG_SLS_LANE_GCRMSG = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTLG4_E_PG_SLS_LANE_GCRMSG_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTLG4_E_PG_SLS_LANE_VAL_GCRMSG = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTLG4_E_PG_SLS_LANE_ENC_SPR1_GCRMSG = 56 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTLG5_E_PG_SLS_LANE_SHDW_GCRMSG = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTLG5_E_PG_SLS_LANE_SHDW_RPR_GCRMSG = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTLG5_E_PG_SLS_LANE_MUX_SPR1_GCRMSG = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTLG5_E_PG_SLS_LANE_MUX_SPR2_GCRMSG = 51 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTLG6_E_PG_SLV_MV_SLS_SHDW_REQ_GCRMSG = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTLG6_E_PG_SLV_MV_SLS_SHDW_RPR_REQ_GCRMSG = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTLG6_E_PG_SLV_MV_SLS_UNSHDW_REQ_GCRMSG = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTLG6_E_PG_SLV_MV_SLS_UNSHDW_RPR_REQ_GCRMSG = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTLG6_E_PG_SLV_MV_SLS_SPR1_GCRMSG = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTLG6_E_PG_SLV_MV_SLS_SPR2_GCRMSG = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTLG6_E_PG_SLV_MV_SLS_RPR_REQ_GCRMSG = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTLG6_E_PG_SLS_LANE_SEL_LG_GCRMSG = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTLG6_E_PG_SLS_LANE_UNSEL_LG_GCRMSG = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTLG6_E_PG_SPR_LNS_PDWN_LITE_GCRMSG = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTLG6_E_PG_SLV_LGL_RPR_REQ_GCRMSG = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTLG7_E_PG_WT_EN_ALL_CLK_SEGS_GCRMSG = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_CNTLG7_E_PG_WT_EN_ALL_DATA_SEGS_GCRMSG = 49 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_MODE1_EO_PG_CLKDIST_PDWN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_MODE1_EO_PG_BIST_EN = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_MODE1_EO_PG_EXBIST_MODE = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_MODE1_EO_PG_MAX_BAD_LANES = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_MODE1_EO_PG_MAX_BAD_LANES_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_MODE1_EO_PG_MSBSWAP = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_MODE1_EO_PG_PDWN_LITE_DISABLE = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_MODE1_EO_PG_WT_PATTERN_LENGTH = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_MODE1_EO_PG_WT_PATTERN_LENGTH_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_MODE1_EO_PG_DESKEW_RATE = 62 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_MODE1_E_PG_CLK_INVERT = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_MODE1_E_PG_CLK_QUIESCE = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_MODE1_E_PG_CLK_QUIESCE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_MODE1_E_PG_CLK_RATE = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_MODE1_E_PG_CLK_RATE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_MODE1_E_PG_DYN_RECAL_INTERVAL_TIMEOUT_SEL = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_MODE1_E_PG_DYN_RECAL_INTERVAL_TIMEOUT_SEL_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_MODE1_E_PG_DYN_RECAL_STATUS_RPT_TIMEOUT_SEL = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_MODE1_E_PG_DYN_RECAL_STATUS_RPT_TIMEOUT_SEL_LEN = 2 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_MODE2_EO_PG_SLS_SCRAMBLE_MODE = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_MODE2_EO_PG_SLS_SCRAMBLE_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_MODE2_EO_PG_CLK_UNLOAD_CLK_DISABLE = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_MODE2_EO_PG_CLK_RUN_COUNT = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_MODE2_EO_PG_CLK_UNLOAD_SEL = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_MODE2_EO_PG_CLK_UNLOAD_SEL_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_MODE2_EO_PG_CLK_HALF_WIDTH_MODE = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_MODE2_EO_PG_BUS_WIDTH = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_MODE2_EO_PG_BUS_WIDTH_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_MODE2_E_PG_LANE_DISABLED_VEC_0_15 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_MODE2_E_PG_LANE_DISABLED_VEC_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_MODE3_E_PG_LANE_DISABLED_VEC_16_23 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_MODE3_E_PG_LANE_DISABLED_VEC_16_23_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_STATG1_E_PG_BAD_LANE1_GCRMSG = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_STATG1_E_PG_BAD_LANE1_GCRMSG_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_STATG1_E_PG_BAD_LANE2_GCRMSG = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_STATG1_E_PG_BAD_LANE2_GCRMSG_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_STATG1_E_PG_BAD_LANE_CODE_GCRMSG = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_CTL_STATG1_E_PG_BAD_LANE_CODE_GCRMSG_LEN = 2 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_FIR_ERROR_INJECT_PG_ERR_INJ = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_FIR_ERROR_INJECT_PG_ERR_INJ_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_FIR_MASK_PG_ERRS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_FIR_MASK_PG_ERRS_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_FIR_MASK_PG_PL_ERR = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_FIR_PG_TX_PG_FIR_ERR_TX_SM_REGS_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_FIR_PG_TX_PG_FIR_ERR_GCR_BUFF_RO_SIGNAL = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_FIR_PG_TX_PG_FIR_ERR_GCRS_LD_SM_RO_SIGNAL = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_FIR_PG_TX_PG_FIR_ERR_GCRS_UNLD_SM_RO_SIGNAL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_FIR_PG_TX_PG_FIR_ERR_CTL_REGS_RO_SIGNAL = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_FIR_PG_TX_PL_FIR_ERR_RO_SIGNAL = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_FIR_RESET_PG_CLR_PAR_ERRS = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_FIR_RESET_PG_RESET = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_ID1_PG_BUS_ID = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_ID1_PG_BUS_ID_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_ID2_PG_START_LANE_ID = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_ID2_PG_START_LANE_ID_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_ID2_PG_END_LANE_ID = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_ID2_PG_END_LANE_ID_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_SPARE_MODE_PG_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_SPARE_MODE_PG_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_SPARE_MODE_PG_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_SPARE_MODE_PG_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_SPARE_MODE_PG_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_SPARE_MODE_PG_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_SPARE_MODE_PG_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_SPARE_MODE_PG_7 = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_SPARE_MODE_PG_8_9 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX0_TX_SPARE_MODE_PG_8_9_LEN = 2 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL =
+ 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL =
+ 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
+ = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
+ = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 57 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 59 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_CNTL3_EO_PL_TDR_ENABLE = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_FIR_MASK_PL_ERRS = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_MODE1_PL_LANE_PDWN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_MODE1_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_MODE1_PL_LANE_QUIESCE = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_MODE1_PL_LANE_QUIESCE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_MODE1_PL_PSAVE_MODE_DISABLE = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_MODE1_PL_ERR_INJ_A_SLS_ENABLE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_MODE1_PL_SPARE_MODE_0 = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_MODE1_PL_SPARE_MODE_1 = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_MODE1_PL_SPARE_MODE_2 = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_MODE1_PL_SPARE_MODE_3 = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_MODE2_PL_NEXT_CAL_LANE_SEL = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_MODE2_PL_PRBS_SCRAMBLE_MODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_MODE2_PL_UNLOAD_SEL = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_MODE2_PL_UNLOAD_SEL_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_MODE2_PL_PDWN_LITE = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_MODE2_PL_CAL_LANE_SEL = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_STAT1_PL_LANE_BIST_ERR = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE0_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL =
+ 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL =
+ 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
+ = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
+ = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 57 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 59 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_CNTL3_EO_PL_TDR_ENABLE = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_FIR_MASK_PL_ERRS = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_MODE1_PL_LANE_PDWN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_MODE1_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_MODE1_PL_LANE_QUIESCE = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_MODE1_PL_LANE_QUIESCE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_MODE1_PL_PSAVE_MODE_DISABLE = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_MODE1_PL_ERR_INJ_A_SLS_ENABLE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_MODE1_PL_SPARE_MODE_0 = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_MODE1_PL_SPARE_MODE_1 = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_MODE1_PL_SPARE_MODE_2 = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_MODE1_PL_SPARE_MODE_3 = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_MODE2_PL_NEXT_CAL_LANE_SEL = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_MODE2_PL_PRBS_SCRAMBLE_MODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_MODE2_PL_UNLOAD_SEL = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_MODE2_PL_UNLOAD_SEL_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_MODE2_PL_PDWN_LITE = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_MODE2_PL_CAL_LANE_SEL = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_STAT1_PL_LANE_BIST_ERR = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE1_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL =
+ 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL =
+ 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
+ = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
+ = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 57 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 59 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_CNTL3_EO_PL_TDR_ENABLE = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_FIR_MASK_PL_ERRS = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_MODE1_PL_LANE_PDWN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_MODE1_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_MODE1_PL_LANE_QUIESCE = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_MODE1_PL_LANE_QUIESCE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_MODE1_PL_PSAVE_MODE_DISABLE = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_MODE1_PL_ERR_INJ_A_SLS_ENABLE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_MODE1_PL_SPARE_MODE_0 = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_MODE1_PL_SPARE_MODE_1 = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_MODE1_PL_SPARE_MODE_2 = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_MODE1_PL_SPARE_MODE_3 = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_MODE2_PL_NEXT_CAL_LANE_SEL = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_MODE2_PL_PRBS_SCRAMBLE_MODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_MODE2_PL_UNLOAD_SEL = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_MODE2_PL_UNLOAD_SEL_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_MODE2_PL_PDWN_LITE = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_MODE2_PL_CAL_LANE_SEL = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_STAT1_PL_LANE_BIST_ERR = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE2_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL =
+ 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL =
+ 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
+ = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
+ = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 57 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 59 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_CNTL3_EO_PL_TDR_ENABLE = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_FIR_MASK_PL_ERRS = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_MODE1_PL_LANE_PDWN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_MODE1_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_MODE1_PL_LANE_QUIESCE = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_MODE1_PL_LANE_QUIESCE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_MODE1_PL_PSAVE_MODE_DISABLE = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_MODE1_PL_ERR_INJ_A_SLS_ENABLE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_MODE1_PL_SPARE_MODE_0 = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_MODE1_PL_SPARE_MODE_1 = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_MODE1_PL_SPARE_MODE_2 = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_MODE1_PL_SPARE_MODE_3 = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_MODE2_PL_NEXT_CAL_LANE_SEL = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_MODE2_PL_PRBS_SCRAMBLE_MODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_MODE2_PL_UNLOAD_SEL = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_MODE2_PL_UNLOAD_SEL_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_MODE2_PL_PDWN_LITE = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_MODE2_PL_CAL_LANE_SEL = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_STAT1_PL_LANE_BIST_ERR = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS0_SLICE3_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL =
+ 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL =
+ 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
+ = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
+ = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 57 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 59 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_CNTL3_EO_PL_TDR_ENABLE = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_FIR_MASK_PL_ERRS = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_MODE1_PL_LANE_PDWN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_MODE1_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_MODE1_PL_LANE_QUIESCE = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_MODE1_PL_LANE_QUIESCE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_MODE1_PL_PSAVE_MODE_DISABLE = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_MODE1_PL_ERR_INJ_A_SLS_ENABLE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_MODE1_PL_SPARE_MODE_0 = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_MODE1_PL_SPARE_MODE_1 = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_MODE1_PL_SPARE_MODE_2 = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_MODE1_PL_SPARE_MODE_3 = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_MODE2_PL_NEXT_CAL_LANE_SEL = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_MODE2_PL_PRBS_SCRAMBLE_MODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_MODE2_PL_UNLOAD_SEL = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_MODE2_PL_UNLOAD_SEL_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_MODE2_PL_PDWN_LITE = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_MODE2_PL_CAL_LANE_SEL = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_STAT1_PL_LANE_BIST_ERR = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE0_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL =
+ 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL =
+ 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
+ = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
+ = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 57 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 59 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_CNTL3_EO_PL_TDR_ENABLE = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_FIR_MASK_PL_ERRS = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_MODE1_PL_LANE_PDWN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_MODE1_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_MODE1_PL_LANE_QUIESCE = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_MODE1_PL_LANE_QUIESCE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_MODE1_PL_PSAVE_MODE_DISABLE = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_MODE1_PL_ERR_INJ_A_SLS_ENABLE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_MODE1_PL_SPARE_MODE_0 = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_MODE1_PL_SPARE_MODE_1 = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_MODE1_PL_SPARE_MODE_2 = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_MODE1_PL_SPARE_MODE_3 = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_MODE2_PL_NEXT_CAL_LANE_SEL = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_MODE2_PL_PRBS_SCRAMBLE_MODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_MODE2_PL_UNLOAD_SEL = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_MODE2_PL_UNLOAD_SEL_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_MODE2_PL_PDWN_LITE = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_MODE2_PL_CAL_LANE_SEL = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_STAT1_PL_LANE_BIST_ERR = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE1_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL =
+ 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL =
+ 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
+ = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
+ = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 57 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 59 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_CNTL3_EO_PL_TDR_ENABLE = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_FIR_MASK_PL_ERRS = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_MODE1_PL_LANE_PDWN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_MODE1_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_MODE1_PL_LANE_QUIESCE = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_MODE1_PL_LANE_QUIESCE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_MODE1_PL_PSAVE_MODE_DISABLE = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_MODE1_PL_ERR_INJ_A_SLS_ENABLE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_MODE1_PL_SPARE_MODE_0 = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_MODE1_PL_SPARE_MODE_1 = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_MODE1_PL_SPARE_MODE_2 = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_MODE1_PL_SPARE_MODE_3 = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_MODE2_PL_NEXT_CAL_LANE_SEL = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_MODE2_PL_PRBS_SCRAMBLE_MODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_MODE2_PL_UNLOAD_SEL = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_MODE2_PL_UNLOAD_SEL_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_MODE2_PL_PDWN_LITE = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_MODE2_PL_CAL_LANE_SEL = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_STAT1_PL_LANE_BIST_ERR = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE2_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL =
+ 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL =
+ 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
+ = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
+ = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 57 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 59 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_CNTL3_EO_PL_TDR_ENABLE = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_FIR_MASK_PL_ERRS = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_MODE1_PL_LANE_PDWN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_MODE1_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_MODE1_PL_LANE_QUIESCE = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_MODE1_PL_LANE_QUIESCE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_MODE1_PL_PSAVE_MODE_DISABLE = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_MODE1_PL_ERR_INJ_A_SLS_ENABLE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_MODE1_PL_SPARE_MODE_0 = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_MODE1_PL_SPARE_MODE_1 = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_MODE1_PL_SPARE_MODE_2 = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_MODE1_PL_SPARE_MODE_3 = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_MODE2_PL_NEXT_CAL_LANE_SEL = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_MODE2_PL_PRBS_SCRAMBLE_MODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_MODE2_PL_UNLOAD_SEL = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_MODE2_PL_UNLOAD_SEL_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_MODE2_PL_PDWN_LITE = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_MODE2_PL_CAL_LANE_SEL = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_STAT1_PL_LANE_BIST_ERR = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS1_SLICE3_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL =
+ 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL =
+ 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
+ = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
+ = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 57 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 59 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_CNTL3_EO_PL_TDR_ENABLE = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_FIR_MASK_PL_ERRS = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_MODE1_PL_LANE_PDWN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_MODE1_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_MODE1_PL_LANE_QUIESCE = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_MODE1_PL_LANE_QUIESCE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_MODE1_PL_PSAVE_MODE_DISABLE = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_MODE1_PL_ERR_INJ_A_SLS_ENABLE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_MODE1_PL_SPARE_MODE_0 = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_MODE1_PL_SPARE_MODE_1 = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_MODE1_PL_SPARE_MODE_2 = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_MODE1_PL_SPARE_MODE_3 = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_MODE2_PL_NEXT_CAL_LANE_SEL = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_MODE2_PL_PRBS_SCRAMBLE_MODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_MODE2_PL_UNLOAD_SEL = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_MODE2_PL_UNLOAD_SEL_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_MODE2_PL_PDWN_LITE = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_MODE2_PL_CAL_LANE_SEL = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_STAT1_PL_LANE_BIST_ERR = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE0_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL =
+ 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL =
+ 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
+ = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
+ = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 57 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 59 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_CNTL3_EO_PL_TDR_ENABLE = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_FIR_MASK_PL_ERRS = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_MODE1_PL_LANE_PDWN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_MODE1_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_MODE1_PL_LANE_QUIESCE = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_MODE1_PL_LANE_QUIESCE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_MODE1_PL_PSAVE_MODE_DISABLE = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_MODE1_PL_ERR_INJ_A_SLS_ENABLE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_MODE1_PL_SPARE_MODE_0 = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_MODE1_PL_SPARE_MODE_1 = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_MODE1_PL_SPARE_MODE_2 = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_MODE1_PL_SPARE_MODE_3 = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_MODE2_PL_NEXT_CAL_LANE_SEL = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_MODE2_PL_PRBS_SCRAMBLE_MODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_MODE2_PL_UNLOAD_SEL = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_MODE2_PL_UNLOAD_SEL_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_MODE2_PL_PDWN_LITE = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_MODE2_PL_CAL_LANE_SEL = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_STAT1_PL_LANE_BIST_ERR = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE1_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL =
+ 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL =
+ 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
+ = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
+ = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 57 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 59 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_CNTL3_EO_PL_TDR_ENABLE = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_FIR_MASK_PL_ERRS = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_MODE1_PL_LANE_PDWN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_MODE1_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_MODE1_PL_LANE_QUIESCE = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_MODE1_PL_LANE_QUIESCE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_MODE1_PL_PSAVE_MODE_DISABLE = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_MODE1_PL_ERR_INJ_A_SLS_ENABLE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_MODE1_PL_SPARE_MODE_0 = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_MODE1_PL_SPARE_MODE_1 = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_MODE1_PL_SPARE_MODE_2 = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_MODE1_PL_SPARE_MODE_3 = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_MODE2_PL_NEXT_CAL_LANE_SEL = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_MODE2_PL_PRBS_SCRAMBLE_MODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_MODE2_PL_UNLOAD_SEL = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_MODE2_PL_UNLOAD_SEL_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_MODE2_PL_PDWN_LITE = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_MODE2_PL_CAL_LANE_SEL = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_STAT1_PL_LANE_BIST_ERR = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE2_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL =
+ 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL =
+ 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
+ = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
+ = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 57 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 59 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_CNTL3_EO_PL_TDR_ENABLE = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_FIR_MASK_PL_ERRS = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_MODE1_PL_LANE_PDWN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_MODE1_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_MODE1_PL_LANE_QUIESCE = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_MODE1_PL_LANE_QUIESCE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_MODE1_PL_PSAVE_MODE_DISABLE = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_MODE1_PL_ERR_INJ_A_SLS_ENABLE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_MODE1_PL_SPARE_MODE_0 = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_MODE1_PL_SPARE_MODE_1 = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_MODE1_PL_SPARE_MODE_2 = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_MODE1_PL_SPARE_MODE_3 = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_MODE2_PL_NEXT_CAL_LANE_SEL = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_MODE2_PL_PRBS_SCRAMBLE_MODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_MODE2_PL_UNLOAD_SEL = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_MODE2_PL_UNLOAD_SEL_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_MODE2_PL_PDWN_LITE = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_MODE2_PL_CAL_LANE_SEL = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_STAT1_PL_LANE_BIST_ERR = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS2_SLICE3_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL =
+ 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL =
+ 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
+ = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
+ = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 57 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 59 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_CNTL3_EO_PL_TDR_ENABLE = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_FIR_MASK_PL_ERRS = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_MODE1_PL_LANE_PDWN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_MODE1_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_MODE1_PL_LANE_QUIESCE = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_MODE1_PL_LANE_QUIESCE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_MODE1_PL_PSAVE_MODE_DISABLE = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_MODE1_PL_ERR_INJ_A_SLS_ENABLE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_MODE1_PL_SPARE_MODE_0 = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_MODE1_PL_SPARE_MODE_1 = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_MODE1_PL_SPARE_MODE_2 = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_MODE1_PL_SPARE_MODE_3 = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_MODE2_PL_NEXT_CAL_LANE_SEL = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_MODE2_PL_PRBS_SCRAMBLE_MODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_MODE2_PL_UNLOAD_SEL = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_MODE2_PL_UNLOAD_SEL_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_MODE2_PL_PDWN_LITE = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_MODE2_PL_CAL_LANE_SEL = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_STAT1_PL_LANE_BIST_ERR = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE0_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL =
+ 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL =
+ 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
+ = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
+ = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 57 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 59 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_CNTL3_EO_PL_TDR_ENABLE = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_FIR_MASK_PL_ERRS = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_MODE1_PL_LANE_PDWN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_MODE1_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_MODE1_PL_LANE_QUIESCE = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_MODE1_PL_LANE_QUIESCE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_MODE1_PL_PSAVE_MODE_DISABLE = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_MODE1_PL_ERR_INJ_A_SLS_ENABLE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_MODE1_PL_SPARE_MODE_0 = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_MODE1_PL_SPARE_MODE_1 = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_MODE1_PL_SPARE_MODE_2 = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_MODE1_PL_SPARE_MODE_3 = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_MODE2_PL_NEXT_CAL_LANE_SEL = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_MODE2_PL_PRBS_SCRAMBLE_MODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_MODE2_PL_UNLOAD_SEL = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_MODE2_PL_UNLOAD_SEL_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_MODE2_PL_PDWN_LITE = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_MODE2_PL_CAL_LANE_SEL = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_STAT1_PL_LANE_BIST_ERR = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE1_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL =
+ 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL =
+ 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
+ = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
+ = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 57 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 59 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_CNTL3_EO_PL_TDR_ENABLE = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_FIR_MASK_PL_ERRS = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_MODE1_PL_LANE_PDWN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_MODE1_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_MODE1_PL_LANE_QUIESCE = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_MODE1_PL_LANE_QUIESCE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_MODE1_PL_PSAVE_MODE_DISABLE = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_MODE1_PL_ERR_INJ_A_SLS_ENABLE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_MODE1_PL_SPARE_MODE_0 = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_MODE1_PL_SPARE_MODE_1 = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_MODE1_PL_SPARE_MODE_2 = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_MODE1_PL_SPARE_MODE_3 = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_MODE2_PL_NEXT_CAL_LANE_SEL = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_MODE2_PL_PRBS_SCRAMBLE_MODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_MODE2_PL_UNLOAD_SEL = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_MODE2_PL_UNLOAD_SEL_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_MODE2_PL_PDWN_LITE = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_MODE2_PL_CAL_LANE_SEL = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_STAT1_PL_LANE_BIST_ERR = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE2_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL =
+ 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL =
+ 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
+ = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
+ = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 57 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 59 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_CNTL3_EO_PL_TDR_ENABLE = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_FIR_MASK_PL_ERRS = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_MODE1_PL_LANE_PDWN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_MODE1_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_MODE1_PL_LANE_QUIESCE = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_MODE1_PL_LANE_QUIESCE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_MODE1_PL_PSAVE_MODE_DISABLE = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_MODE1_PL_ERR_INJ_A_SLS_ENABLE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_MODE1_PL_SPARE_MODE_0 = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_MODE1_PL_SPARE_MODE_1 = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_MODE1_PL_SPARE_MODE_2 = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_MODE1_PL_SPARE_MODE_3 = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_MODE2_PL_NEXT_CAL_LANE_SEL = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_MODE2_PL_PRBS_SCRAMBLE_MODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_MODE2_PL_UNLOAD_SEL = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_MODE2_PL_UNLOAD_SEL_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_MODE2_PL_PDWN_LITE = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_MODE2_PL_CAL_LANE_SEL = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_STAT1_PL_LANE_BIST_ERR = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE3_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN = 7
+ ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL =
+ 48 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_CNTL1G_PL_TX_ERR_INJECT_WO_PULSE_SLOW_SIGNAL_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_CNTL1G_PL_TX_FIFO_INIT_WO_PULSE_SLOW_SIGNAL =
+ 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_CNTL1G_PL_TX_SET_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
+ = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_CNTL1G_PL_TX_CLR_PDWN_LITE_WO_PULSE_SLOW_SIGNAL
+ = 55 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_CNTL1G_PL_TX_SET_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 56 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_CNTL1G_PL_TX_CLR_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 57 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_CNTL1G_PL_TX_SET_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_CNTL1G_PL_TX_CLR_NEXT_CAL_LANE_SEL_WO_PULSE_SLOW_SIGNAL = 59 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_CNTL1G_PL_TX_SET_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 60 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_CNTL1G_PL_TX_CLR_UNLOAD_CLK_DISABLE_WO_PULSE_SLOW_SIGNAL = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_CNTL3_EO_PL_TDR_ENABLE = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_FIR_MASK_PL_ERRS = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_FIR_PL_TX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_MODE1_PL_LANE_PDWN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_MODE1_PL_LANE_INVERT = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_MODE1_PL_LANE_QUIESCE = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_MODE1_PL_LANE_QUIESCE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_MODE1_PL_ERR_INJ_A_ENABLE = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_MODE1_PL_ERR_INJ_B_ENABLE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_MODE1_PL_PSAVE_MODE_DISABLE = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_MODE1_PL_ERR_INJ_A_SLS_ENABLE = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_MODE1_PL_SPARE_MODE_0 = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_MODE1_PL_SPARE_MODE_1 = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_MODE1_PL_SPARE_MODE_2 = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_MODE1_PL_SPARE_MODE_3 = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_MODE2_PL_FIFO_L2U_DLY = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_MODE2_PL_FIFO_L2U_DLY_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_MODE2_PL_NEXT_CAL_LANE_SEL = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_MODE2_PL_PRBS_SCRAMBLE_MODE = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_MODE2_PL_UNLOAD_CLK_DISABLE = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_MODE2_PL_UNLOAD_SEL = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_MODE2_PL_UNLOAD_SEL_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_MODE2_PL_PDWN_LITE = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_MODE2_PL_CAL_LANE_SEL = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_STAT1_PL_LANE_BIST_ERR = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_STAT1_PL_LANE_BIST_ACTVITY_DET = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_STAT1_PL_SEG_TEST_STATUS = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_STAT1_PL_SEG_TEST_STATUS_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TXPACKS3_SLICE4_TX_STAT1_PL_TX_TDR_CAPT_VAL_RO_SIGNAL = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_CNTL1_EO_PG_PSEG_PRE_EN = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_CNTL1_EO_PG_PSEG_PRE_EN_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_CNTL1_EO_PG_PSEG_PRE_SEL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_CNTL1_EO_PG_PSEG_PRE_SEL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_CNTL2_EO_PG_NSEG_PRE_EN = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_CNTL2_EO_PG_NSEG_PRE_EN_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_CNTL2_EO_PG_NSEG_PRE_SEL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_CNTL2_EO_PG_NSEG_PRE_SEL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_CNTL3_EO_PG_PSEG_MARGINPU_EN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_CNTL3_EO_PG_PSEG_MARGINPU_EN_LEN = 8 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_CNTL3_EO_PG_PSEG_MARGINPD_EN = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_CNTL3_EO_PG_PSEG_MARGINPD_EN_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_CNTL4_EO_PG_NSEG_MARGINPU_EN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_CNTL4_EO_PG_NSEG_MARGINPU_EN_LEN = 8 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_CNTL4_EO_PG_NSEG_MARGINPD_EN = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_CNTL4_EO_PG_NSEG_MARGINPD_EN_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_CNTL5_EO_PG_MARGINPU_SEL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_CNTL5_EO_PG_MARGINPU_SEL_LEN = 8 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_CNTL5_EO_PG_MARGINPD_SEL = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_CNTL5_EO_PG_MARGINPD_SEL_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_CNTL6_EO_PG_PSEG_MAIN_EN = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_CNTL6_EO_PG_PSEG_MAIN_EN_LEN = 13 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_CNTL7_EO_PG_NSEG_MAIN_EN = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_CNTL7_EO_PG_NSEG_MAIN_EN_LEN = 13 ;
+
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_CNTLG1_E_PG_TX_DRV_SYNC_PATTERN_GCRMSG_WO_PULSE_SLOW_SIGNAL = 48 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_MODE1_EO_PG_PSAVE_WAKEUP_LANE0_ENABLE = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_MODE1_EO_PG_PSAVE_FENCE_ENABLE = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_MODE1_EO_PG_SEG_TEST_MODE = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_MODE1_EO_PG_SEG_TEST_MODE_LEN = 8 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_MODE1_EO_PG_FFE_BOOST_EN = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_MODE1_EO_PG_SEG_TEST_LEAKAGE_CTRL = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_MODE1_EO_PG_HALF_RATE_MODE = 62 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_SPARE_MODE_PG_CTL_SM_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_SPARE_MODE_PG_CTL_SM_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_SPARE_MODE_PG_CTL_SM_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_SPARE_MODE_PG_CTL_SM_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_SPARE_MODE_PG_CTL_SM_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_SPARE_MODE_PG_CTL_SM_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_SPARE_MODE_PG_CTL_SM_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_SPARE_MODE_PG_CTL_SM_7 = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_STAT1_EO_PG_CLK_BIST_ERR = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_STAT1_EO_PG_CLK_BIST_ACTIVITY_DET = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_STAT1_EO_PG_TX_BIST_DONE_RO_SIGNAL = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_STAT1_EO_PG_TX_SLS_HNDSHK_STATE_RO_SIGNAL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_STAT1_EO_PG_TX_SLS_HNDSHK_STATE_RO_SIGNAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_STAT1_E_PG_SEG_TEST_CLK_STATUS = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTLSM_STAT1_E_PG_SEG_TEST_CLK_STATUS_LEN = 2 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTL10_EO_PG_TDR_PULSE_WIDTH = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTL10_EO_PG_TDR_PULSE_WIDTH_LEN = 9 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTL2_EO_PG_ERR_INJ_A_FINE_SEL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTL2_EO_PG_ERR_INJ_A_FINE_SEL_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTL2_EO_PG_ERR_INJ_A_COARSE_SEL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTL2_EO_PG_ERR_INJ_A_COARSE_SEL_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTL2_EO_PG_ERR_INJ_A_BER_SEL = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTL2_EO_PG_ERR_INJ_A_BER_SEL_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTL2_EO_PG_ERR_INJ_ENABLE = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTL2_EO_PG_ERR_INJ_CLOCK_ENABLE = 62 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTL2_E_PG_IORESET = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTL2_E_PG_ERR_INJ_SLS_MODE = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTL2_E_PG_ERR_INJ_SLS_ALL_CMD = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTL2_E_PG_ERR_INJ_SLS_RECAL = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTL2_E_PG_ERR_INJ_SLS_CMD = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTL2_E_PG_ERR_INJ_SLS_CMD_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTL3_EO_PG_ERR_INJ_B_FINE_SEL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTL3_EO_PG_ERR_INJ_B_FINE_SEL_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTL3_EO_PG_ERR_INJ_B_COARSE_SEL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTL3_EO_PG_ERR_INJ_B_COARSE_SEL_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTL3_EO_PG_ERR_INJ_B_BER_SEL = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTL3_EO_PG_ERR_INJ_B_BER_SEL_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTL8_EO_PG_TDR_DAC_CNTL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTL8_EO_PG_TDR_DAC_CNTL_LEN = 8 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTL8_EO_PG_TDR_PHASE_SEL = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTL9_EO_PG_TDR_PULSE_OFFSET = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTL9_EO_PG_TDR_PULSE_OFFSET_LEN = 14 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTLG1_EO_PG_DRV_CLK_PATTERN_GCRMSG = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTLG1_EO_PG_DRV_CLK_PATTERN_GCRMSG_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTLG1_EO_PG_DRV_DATA_PATTERN_GCRMSG = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTLG1_EO_PG_DRV_DATA_PATTERN_GCRMSG_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTLG3_E_PG_SND_SLS_CMD_GCRMSG = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTLG3_E_PG_DYN_RECAL_TSR_IGNORE_GCRMSG = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTLG3_E_PG_SLS_CMD_GCRMSG = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTLG3_E_PG_SLS_CMD_GCRMSG_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTLG3_E_PG_SND_SLS_CMD_PREV_GCRMSG = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTLG3_E_PG_SND_SLS_USING_REG_SCRAMBLE = 57 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTLG4_E_PG_SLS_LANE_GCRMSG = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTLG4_E_PG_SLS_LANE_GCRMSG_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTLG4_E_PG_SLS_LANE_VAL_GCRMSG = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTLG4_E_PG_SLS_LANE_ENC_SPR1_GCRMSG = 56 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTLG5_E_PG_SLS_LANE_SHDW_GCRMSG = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTLG5_E_PG_SLS_LANE_SHDW_RPR_GCRMSG = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTLG5_E_PG_SLS_LANE_MUX_SPR1_GCRMSG = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTLG5_E_PG_SLS_LANE_MUX_SPR2_GCRMSG = 51 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTLG6_E_PG_SLV_MV_SLS_SHDW_REQ_GCRMSG = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTLG6_E_PG_SLV_MV_SLS_SHDW_RPR_REQ_GCRMSG = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTLG6_E_PG_SLV_MV_SLS_UNSHDW_REQ_GCRMSG = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTLG6_E_PG_SLV_MV_SLS_UNSHDW_RPR_REQ_GCRMSG = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTLG6_E_PG_SLV_MV_SLS_SPR1_GCRMSG = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTLG6_E_PG_SLV_MV_SLS_SPR2_GCRMSG = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTLG6_E_PG_SLV_MV_SLS_RPR_REQ_GCRMSG = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTLG6_E_PG_SLS_LANE_SEL_LG_GCRMSG = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTLG6_E_PG_SLS_LANE_UNSEL_LG_GCRMSG = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTLG6_E_PG_SPR_LNS_PDWN_LITE_GCRMSG = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTLG6_E_PG_SLV_LGL_RPR_REQ_GCRMSG = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTLG7_E_PG_WT_EN_ALL_CLK_SEGS_GCRMSG = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_CNTLG7_E_PG_WT_EN_ALL_DATA_SEGS_GCRMSG = 49 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_MODE1_EO_PG_CLKDIST_PDWN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_MODE1_EO_PG_BIST_EN = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_MODE1_EO_PG_EXBIST_MODE = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_MODE1_EO_PG_MAX_BAD_LANES = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_MODE1_EO_PG_MAX_BAD_LANES_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_MODE1_EO_PG_MSBSWAP = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_MODE1_EO_PG_PDWN_LITE_DISABLE = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_MODE1_EO_PG_WT_PATTERN_LENGTH = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_MODE1_EO_PG_WT_PATTERN_LENGTH_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_MODE1_EO_PG_DESKEW_RATE = 62 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_MODE1_E_PG_CLK_INVERT = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_MODE1_E_PG_CLK_QUIESCE = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_MODE1_E_PG_CLK_QUIESCE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_MODE1_E_PG_CLK_RATE = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_MODE1_E_PG_CLK_RATE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_MODE1_E_PG_DYN_RECAL_INTERVAL_TIMEOUT_SEL = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_MODE1_E_PG_DYN_RECAL_INTERVAL_TIMEOUT_SEL_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_MODE1_E_PG_DYN_RECAL_STATUS_RPT_TIMEOUT_SEL = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_MODE1_E_PG_DYN_RECAL_STATUS_RPT_TIMEOUT_SEL_LEN = 2 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_MODE2_EO_PG_SLS_SCRAMBLE_MODE = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_MODE2_EO_PG_SLS_SCRAMBLE_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_MODE2_EO_PG_CLK_UNLOAD_CLK_DISABLE = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_MODE2_EO_PG_CLK_RUN_COUNT = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_MODE2_EO_PG_CLK_UNLOAD_SEL = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_MODE2_EO_PG_CLK_UNLOAD_SEL_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_MODE2_EO_PG_CLK_HALF_WIDTH_MODE = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_MODE2_EO_PG_BUS_WIDTH = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_MODE2_EO_PG_BUS_WIDTH_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_MODE2_E_PG_LANE_DISABLED_VEC_0_15 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_MODE2_E_PG_LANE_DISABLED_VEC_0_15_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_MODE3_E_PG_LANE_DISABLED_VEC_16_23 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_MODE3_E_PG_LANE_DISABLED_VEC_16_23_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_STATG1_E_PG_BAD_LANE1_GCRMSG = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_STATG1_E_PG_BAD_LANE1_GCRMSG_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_STATG1_E_PG_BAD_LANE2_GCRMSG = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_STATG1_E_PG_BAD_LANE2_GCRMSG_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_STATG1_E_PG_BAD_LANE_CODE_GCRMSG = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_CTL_STATG1_E_PG_BAD_LANE_CODE_GCRMSG_LEN = 2 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_FIR_ERROR_INJECT_PG_ERR_INJ = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_FIR_ERROR_INJECT_PG_ERR_INJ_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_FIR_MASK_PG_ERRS = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_FIR_MASK_PG_ERRS_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_FIR_MASK_PG_PL_ERR = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_FIR_PG_TX_PG_FIR_ERR_TX_SM_REGS_RO_SIGNAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_FIR_PG_TX_PG_FIR_ERR_GCR_BUFF_RO_SIGNAL = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_FIR_PG_TX_PG_FIR_ERR_GCRS_LD_SM_RO_SIGNAL = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_FIR_PG_TX_PG_FIR_ERR_GCRS_UNLD_SM_RO_SIGNAL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_FIR_PG_TX_PG_FIR_ERR_CTL_REGS_RO_SIGNAL = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_FIR_PG_TX_PL_FIR_ERR_RO_SIGNAL = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_FIR_RESET_PG_CLR_PAR_ERRS = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_FIR_RESET_PG_RESET = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_ID1_PG_BUS_ID = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_ID1_PG_BUS_ID_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_ID2_PG_START_LANE_ID = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_ID2_PG_START_LANE_ID_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_ID2_PG_END_LANE_ID = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_ID2_PG_END_LANE_ID_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_SPARE_MODE_PG_0 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_SPARE_MODE_PG_1 = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_SPARE_MODE_PG_2 = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_SPARE_MODE_PG_3 = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_SPARE_MODE_PG_4 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_SPARE_MODE_PG_5 = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_SPARE_MODE_PG_6 = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_SPARE_MODE_PG_7 = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_SPARE_MODE_PG_8_9 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX1_TX_SPARE_MODE_PG_8_9_LEN = 2 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL2_PB_TX_ZCAL_ANS_NOT_FOUND_ERROR_RO_SIGNAL = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL2_PB_TX_ZCAL_ANS_RANGE_ERROR_RO_SIGNAL = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL2_PB_TX_ZCAL_TEST_ENABLE_WO_PULSE_SLOW_SIGNAL = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL2_PB_TX_ZCAL_TEST_STATUS_RO_SIGNAL = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL2_PB_TX_ZCAL_TEST_DONE_RO_SIGNAL = 55 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL_NVAL_PB_ZCAL_N = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL_NVAL_PB_ZCAL_N_LEN = 9 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL_PB_TX_ZCAL_REQ_WO_PULSE_SLOW_SIGNAL = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL_PB_TX_ZCAL_DONE_RO_SIGNAL = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL_PB_TX_ZCAL_ERROR_RO_SIGNAL = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL_PB_TX_ZCAL_BUSY_RO_SIGNAL = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL_PB_TX_ZCAL_FORCE_SAMPLE_WO_PULSE_SLOW_SIGNAL = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL_PB_TX_ZCAL_CMP_OUT_RO_SIGNAL = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL_PB_TX_ZCAL_SAMPLE_CNT_RO_SIGNAL = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL_PB_TX_ZCAL_SAMPLE_CNT_RO_SIGNAL_LEN = 9 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL_PVAL_PB_ZCAL_P = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL_PVAL_PB_ZCAL_P_LEN = 9 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL_P_4X_PB_ZCAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL_P_4X_PB_ZCAL_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL_SWO1_PB_ZCAL_SWO_EN = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL_SWO1_PB_ZCAL_SWO_CAL_SEGS = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL_SWO1_PB_ZCAL_SWO_CMP_INV = 50 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL_SWO1_PB_ZCAL_SWO_CMP_OFFSET = 51 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL_SWO1_PB_ZCAL_SWO_CMP_RESET = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL_SWO1_PB_ZCAL_SWO_POWERDOWN = 53 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL_SWO1_PB_ZCAL_SWO_TCOIL = 54 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL_SWO1_PB_ZCAL_RANGE_CHECK = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL_SWO1_PB_ZCAL_CYA_DATA_INV = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL_SWO1_PB_ZCAL_TEST_OVR_2R = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL_SWO1_PB_ZCAL_TEST_OVR_1R = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL_SWO1_PB_ZCAL_TEST_OVR_4X_SEG = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL_SWO1_PB_ZCAL_TEST_CLK_DIV = 60 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL_SWO2_PB_ZCAL_SM_MIN_VAL = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL_SWO2_PB_ZCAL_SM_MIN_VAL_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL_SWO2_PB_ZCAL_SM_MAX_VAL = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_IOF1_TX_IMPCAL_SWO2_PB_ZCAL_SM_MAX_VAL_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_MASK_REG_LINK0_TRAINED = 0 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_MASK_REG_LINK1_TRAINED = 1 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_MASK_REG_LINK0_REPLAY_THRESHOLD
+ = 4 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_MASK_REG_LINK1_REPLAY_THRESHOLD
+ = 5 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_MASK_REG_LINK0_CRC_ERROR = 6 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_MASK_REG_LINK1_CRC_ERROR = 7 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_MASK_REG_LINK0_NAK_RECEIVED = 8
+ ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_MASK_REG_LINK1_NAK_RECEIVED = 9
+ ;
+static const uint8_t
+P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_MASK_REG_LINK0_REPLAY_BUFFER_FULL = 10 ;
+static const uint8_t
+P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_MASK_REG_LINK1_REPLAY_BUFFER_FULL = 11 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_MASK_REG_LINK0_SL_ECC_THRESHOLD
+ = 12 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_MASK_REG_LINK1_SL_ECC_THRESHOLD
+ = 13 ;
+static const uint8_t
+P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_MASK_REG_LINK0_SL_ECC_CORRECTABLE = 14 ;
+static const uint8_t
+P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_MASK_REG_LINK1_SL_ECC_CORRECTABLE = 15 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_MASK_REG_LINK0_SL_ECC_UE = 16 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_MASK_REG_LINK1_SL_ECC_UE = 17 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_MASK_REG_LINK0_TOD_ECC_ERROR =
+ 18 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_MASK_REG_LINK1_TOD_ECC_ERROR =
+ 19 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_MASK_REG_LINK0_TCOMPLETE_BAD =
+ 40 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_MASK_REG_LINK1_TCOMPLETE_BAD =
+ 41 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_MASK_REG_LINK0_SPARE_DONE = 44
+ ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_MASK_REG_LINK1_SPARE_DONE = 45
+ ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_MASK_REG_PSAVE_INVALID_STATE =
+ 51 ;
+static const uint8_t
+P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_MASK_REG_LINK0_CORRECTABLE_ARRAY_ERROR = 52 ;
+static const uint8_t
+P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_MASK_REG_LINK1_CORRECTABLE_ARRAY_ERROR = 53 ;
+static const uint8_t
+P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_MASK_REG_LINK0_UNCORRECTABLE_ARRAY_ERROR = 54 ;
+static const uint8_t
+P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_MASK_REG_LINK1_UNCORRECTABLE_ARRAY_ERROR = 55 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_MASK_REG_LINK0_TRAINING_FAILED =
+ 56 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_MASK_REG_LINK1_TRAINING_FAILED =
+ 57 ;
+static const uint8_t
+P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_MASK_REG_LINK0_UNRECOVERABLE_ERROR = 58 ;
+static const uint8_t
+P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_MASK_REG_LINK1_UNRECOVERABLE_ERROR = 59 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_MASK_REG_LINK0_INTERNAL_ERROR =
+ 60 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_MASK_REG_LINK1_INTERNAL_ERROR =
+ 61 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_MASK_REG_SCOM_ERR_DUP = 62 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_MASK_REG_SCOM_ERR = 63 ;
+
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_REG_LINK0_TRAINED = 0 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_REG_LINK1_TRAINED = 1 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_REG_LINK0_REPLAY_THRESHOLD = 4
+ ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_REG_LINK1_REPLAY_THRESHOLD = 5
+ ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_REG_LINK0_CRC_ERROR = 6 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_REG_LINK1_CRC_ERROR = 7 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_REG_LINK0_NAK_RECEIVED = 8 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_REG_LINK1_NAK_RECEIVED = 9 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_REG_LINK0_REPLAY_BUFFER_FULL =
+ 10 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_REG_LINK1_REPLAY_BUFFER_FULL =
+ 11 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_REG_LINK0_SL_ECC_THRESHOLD = 12
+ ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_REG_LINK1_SL_ECC_THRESHOLD = 13
+ ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_REG_LINK0_SL_ECC_CORRECTABLE =
+ 14 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_REG_LINK1_SL_ECC_CORRECTABLE =
+ 15 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_REG_LINK0_SL_ECC_UE = 16 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_REG_LINK1_SL_ECC_UE = 17 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_REG_LINK0_TOD_ECC_ERROR = 18 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_REG_LINK1_TOD_ECC_ERROR = 19 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_REG_LINK0_TCOMPLETE_BAD = 40 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_REG_LINK1_TCOMPLETE_BAD = 41 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_REG_LINK0_SPARE_DONE = 44 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_REG_LINK1_SPARE_DONE = 45 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_REG_PSAVE_INVALID_STATE = 51 ;
+static const uint8_t
+P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_REG_LINK0_CORRECTABLE_ARRAY_ERROR = 52 ;
+static const uint8_t
+P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_REG_LINK1_CORRECTABLE_ARRAY_ERROR = 53 ;
+static const uint8_t
+P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_REG_LINK0_UNCORRECTABLE_ARRAY_ERROR = 54 ;
+static const uint8_t
+P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_REG_LINK1_UNCORRECTABLE_ARRAY_ERROR = 55 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_REG_LINK0_TRAINING_FAILED = 56
+ ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_REG_LINK1_TRAINING_FAILED = 57
+ ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_REG_LINK0_UNRECOVERABLE_ERROR =
+ 58 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_REG_LINK1_UNRECOVERABLE_ERROR =
+ 59 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_REG_LINK0_INTERNAL_ERROR = 60 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_REG_LINK1_INTERNAL_ERROR = 61 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_REG_SCOM_ERR_DUP = 62 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_C0_S0_P0_E9_LL0_IOEL_FIR_REG_SCOM_ERR = 63 ;
+
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONFIG_LINK_PAIR = 0 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONFIG_DISABLE_SL_ECC = 1 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONFIG_CRC_LANE_ID = 2 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONFIG_EDPL_LANE_ID = 3 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONFIG_SL_UE_CRC_ERR = 4 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONFIG_REPORT_SL_CHKBIT_ERR = 5 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONFIG_BW_SAMPLE_SIZE = 6 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONFIG_BW_WINDOW_SIZE = 7 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONFIG_UNUSED1 = 8 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONFIG_UNUSED1_LEN = 3 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONFIG_PACKET_DELAY_LIMIT = 11 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONFIG_PACKET_DELAY_LIMIT_LEN = 5 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONFIG_TDM_DELAY = 16 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONFIG_TDM_DELAY_LEN = 4 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONFIG_AUTO_TDM_TX = 20 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONFIG_AUTO_TDM_RX = 21 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONFIG_AUTO_TDM_AND_NOT_OR = 22 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONFIG_UNUSED2 = 23 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONFIG_AUTO_TDM_BW_DIFF = 24 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONFIG_AUTO_TDM_BW_DIFF_LEN = 4 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONFIG_AUTO_TDM_ERROR_RATE = 28 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONFIG_AUTO_TDM_ERROR_RATE_LEN = 4 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONFIG_AUTO_TDM_EXIT_RATE = 32 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONFIG_AUTO_TDM_EXIT_RATE_LEN = 4 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONFIG_UNUSED3 = 36 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONFIG_UNUSED3_LEN = 8 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONFIG_PSAVE_TIMEOUT = 44 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONFIG_PSAVE_TIMEOUT_LEN = 4 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONFIG_TIMEOUT = 48 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONFIG_TIMEOUT_LEN = 4 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONFIG_TIMER_1US = 52 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONFIG_TIMER_1US_LEN = 12 ;
+
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONTROL_UNUSED0A = 0 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONTROL_LINK0_STARTUP = 1 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONTROL_UNUSED0B = 2 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONTROL_UNUSED0B_LEN = 6 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONTROL_LINK0_ERR_INJ_COMMAND = 8 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONTROL_LINK0_ERR_INJ_COMMAND_LEN = 4 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONTROL_LINK0_ERR_INJ_COMMAND_LANES = 12 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONTROL_LINK0_ERR_INJ_COMMAND_LANES_LEN = 16 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONTROL_LINK0_COMMAND = 28 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONTROL_LINK0_COMMAND_LEN = 4 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONTROL_UNUSED1A = 32 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONTROL_LINK1_STARTUP = 33 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONTROL_UNUSED1B = 34 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONTROL_UNUSED1B_LEN = 6 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONTROL_LINK1_ERR_INJ_COMMAND = 40 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONTROL_LINK1_ERR_INJ_COMMAND_LEN = 4 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONTROL_LINK1_ERR_INJ_COMMAND_LANES = 44 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONTROL_LINK1_ERR_INJ_COMMAND_LANES_LEN = 16 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONTROL_LINK1_COMMAND = 60 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_CONTROL_LINK1_COMMAND_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_DLL_STATUS_LINK0_CURRENT_STATE = 4 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_DLL_STATUS_LINK0_CURRENT_STATE_LEN = 4 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_DLL_STATUS_LINK0_PRIOR_STATE = 12 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_DLL_STATUS_LINK0_PRIOR_STATE_LEN = 4 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_DLL_STATUS_LINK0_MAX_PKT_TIMER = 19 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_DLL_STATUS_LINK0_MAX_PKT_TIMER_LEN = 5 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_DLL_STATUS_LINK1_CURRENT_STATE = 28 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_DLL_STATUS_LINK1_CURRENT_STATE_LEN = 4 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_DLL_STATUS_LINK1_PRIOR_STATE = 36 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_DLL_STATUS_LINK1_PRIOR_STATE_LEN = 4 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_DLL_STATUS_LINK1_MAX_PKT_TIMER = 43 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_DLL_STATUS_LINK1_MAX_PKT_TIMER_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_ERR_INJ_LFSR_LFSR = 0 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_ERR_INJ_LFSR_LFSR_LEN = 61 ;
+
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_FIR_ACTION0_REG_ACTION0 = 0 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_FIR_ACTION0_REG_ACTION0_LEN = 64 ;
+
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_FIR_ACTION1_REG_ACTION1 = 0 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_FIR_ACTION1_REG_ACTION1_LEN = 64 ;
+
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_FIR_WOF_REG_WOF = 0 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_FIR_WOF_REG_WOF_LEN = 64 ;
+
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LAT_MEASURE_LINK0_ROUND_TRIP_VALID = 0 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LAT_MEASURE_LINK0_ROUND_TRIP = 2 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LAT_MEASURE_LINK0_ROUND_TRIP_LEN = 10 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LAT_MEASURE_LINK1_ROUND_TRIP_VALID = 12 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LAT_MEASURE_LINK1_ROUND_TRIP = 14 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LAT_MEASURE_LINK1_ROUND_TRIP_LEN = 10 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LAT_MEASURE_LOCAL_LATENCY_DIFFERENCE_VALID = 24 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LAT_MEASURE_LOCAL_LATENCY_LONGER_LINK = 25 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LAT_MEASURE_LOCAL_LATENCY_DIFFERENCE = 29 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LAT_MEASURE_LOCAL_LATENCY_DIFFERENCE_LEN = 7 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LAT_MEASURE_REMOTE_LATENCY_DIFFERENCE_VALID = 36 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LAT_MEASURE_REMOTE_LATENCY_LONGER_LINK = 37 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LAT_MEASURE_REMOTE_LATENCY_DIFFERENCE = 41 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LAT_MEASURE_REMOTE_LATENCY_DIFFERENCE_LEN = 7 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LAT_MEASURE_LINK0_TOD_LATENCY = 49 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LAT_MEASURE_LINK0_TOD_LATENCY_LEN = 7 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LAT_MEASURE_LINK1_TOD_LATENCY = 57 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LAT_MEASURE_LINK1_TOD_LATENCY_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_0 = 0 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_0_LEN = 4 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_1 = 4 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_1_LEN = 4 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_2 = 8 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_2_LEN = 4 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_3 = 12 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_3_LEN = 4 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_4 = 16 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_4_LEN = 4 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_5 = 20 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_5_LEN = 4 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_6 = 24 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_6_LEN = 4 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_7 = 28 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_7_LEN = 4 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_8 = 32 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_8_LEN = 4 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_9 = 36 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_9_LEN = 4 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_10 = 40 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_10_LEN = 4 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_11 = 44 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_11_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_ERROR_STATUS_RESET_KEEPER = 0 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_ERROR_STATUS_CE = 1 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_ERROR_STATUS_CE_LEN = 3 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_ERROR_STATUS_UE = 8 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_ERROR_STATUS_UE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_ERROR_STATUS_TRAIN = 16 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_ERROR_STATUS_TRAIN_LEN = 2 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_ERROR_STATUS_UNRECOV = 24 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_ERROR_STATUS_UNRECOV_LEN = 11 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_ERROR_STATUS_INTERNAL = 44 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_ERROR_STATUS_INTERNAL_LEN = 18 ;
+
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_INFO_MAX_TIMEOUT = 0 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_INFO_MAX_TIMEOUT_LEN = 16 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_INFO_FRAME_CAP_VALID = 16 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_INFO_FRAME_CAP_INST = 17 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_INFO_FRAME_CAP_ADDR = 19 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_INFO_FRAME_CAP_ADDR_LEN = 5 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_INFO_FRAME_CAP_SYN = 24 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_INFO_FRAME_CAP_SYN_LEN = 8 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_INFO_REPLAY_CAP_VALID = 32 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_INFO_REPLAY_CAP_INST = 34 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_INFO_REPLAY_CAP_ADDR = 37 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_INFO_REPLAY_CAP_ADDR_LEN = 7 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_INFO_REPLAY_CAP_SYN = 44 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_INFO_REPLAY_CAP_SYN_LEN = 8 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_INFO_ACK_FIFO_CAP_VALID = 52 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_INFO_ACK_FIFO_CAP_ADDR = 57 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_INFO_ACK_FIFO_CAP_ADDR_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_QUALITY_TX_BW = 1 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_QUALITY_TX_BW_LEN = 11 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_QUALITY_RX_BW = 13 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_QUALITY_RX_BW_LEN = 11 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_QUALITY_ERROR_RATE = 25 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_QUALITY_ERROR_RATE_LEN = 23 ;
+
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_CRC = 0 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_CRC_LEN = 28 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_CRC_UNUSED1 = 28 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_CRC_UNUSED1_LEN = 8 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_SLECC_SYN0 = 36 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_SLECC_SYN0_LEN = 8 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_SLECC_SYN1 = 44 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_SLECC_SYN1_LEN = 8 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_CRC_UNUSED2 = 52 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_CRC_UNUSED2_LEN = 3 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_VALID = 55 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_CRC_UNUSED3 = 56 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_CRC_UNUSED3_LEN = 3 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_CRC_LANE = 59 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_CRC_LANE_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_0 = 0 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_0_LEN = 4 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_1 = 4 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_1_LEN = 4 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_2 = 8 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_2_LEN = 4 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_3 = 12 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_3_LEN = 4 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_4 = 16 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_4_LEN = 4 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_5 = 20 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_5_LEN = 4 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_6 = 24 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_6_LEN = 4 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_7 = 28 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_7_LEN = 4 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_8 = 32 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_8_LEN = 4 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_9 = 36 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_9_LEN = 4 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_10 = 40 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_10_LEN = 4 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_11 = 44 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_11_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_ERROR_STATUS_RESET_KEEPER = 0 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_ERROR_STATUS_CE = 1 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_ERROR_STATUS_CE_LEN = 3 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_ERROR_STATUS_UE = 8 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_ERROR_STATUS_UE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_ERROR_STATUS_TRAIN = 16 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_ERROR_STATUS_TRAIN_LEN = 2 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_ERROR_STATUS_UNRECOV = 24 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_ERROR_STATUS_UNRECOV_LEN = 11 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_ERROR_STATUS_INTERNAL = 44 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_ERROR_STATUS_INTERNAL_LEN = 18 ;
+
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_INFO_MAX_TIMEOUT = 0 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_INFO_MAX_TIMEOUT_LEN = 16 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_INFO_FRAME_CAP_VALID = 16 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_INFO_FRAME_CAP_INST = 17 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_INFO_FRAME_CAP_ADDR = 19 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_INFO_FRAME_CAP_ADDR_LEN = 5 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_INFO_FRAME_CAP_SYN = 24 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_INFO_FRAME_CAP_SYN_LEN = 8 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_INFO_REPLAY_CAP_VALID = 32 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_INFO_REPLAY_CAP_INST = 34 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_INFO_REPLAY_CAP_ADDR = 37 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_INFO_REPLAY_CAP_ADDR_LEN = 7 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_INFO_REPLAY_CAP_SYN = 44 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_INFO_REPLAY_CAP_SYN_LEN = 8 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_INFO_ACK_FIFO_CAP_VALID = 52 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_INFO_ACK_FIFO_CAP_ADDR = 57 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_INFO_ACK_FIFO_CAP_ADDR_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_QUALITY_TX_BW = 1 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_QUALITY_TX_BW_LEN = 11 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_QUALITY_RX_BW = 13 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_QUALITY_RX_BW_LEN = 11 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_QUALITY_ERROR_RATE = 25 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_QUALITY_ERROR_RATE_LEN = 23 ;
+
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_CRC = 0 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_CRC_LEN = 28 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_CRC_UNUSED1 = 28 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_CRC_UNUSED1_LEN = 8 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_SLECC_SYN0 = 36 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_SLECC_SYN0_LEN = 8 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_SLECC_SYN1 = 44 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_SLECC_SYN1_LEN = 8 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_CRC_UNUSED2 = 52 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_CRC_UNUSED2_LEN = 3 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_VALID = 55 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_CRC_UNUSED3 = 56 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_CRC_UNUSED3_LEN = 3 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_CRC_LANE = 59 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_CRC_LANE_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_COUNTERS_0_PERFMON_COUNTER = 0 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_COUNTERS_0_PERFMON_COUNTER_LEN = 16 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_COUNTERS_0_PERFMON_COUNTER_1 = 16 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_COUNTERS_0_PERFMON_COUNTER_1_LEN = 16 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_COUNTERS_0_PERFMON_COUNTER_2 = 32 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_COUNTERS_0_PERFMON_COUNTER_2_LEN = 16 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_COUNTERS_0_PERFMON_COUNTER_3 = 48 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_COUNTERS_0_PERFMON_COUNTER_3_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_COUNTERS_1_PERFMON_COUNTER_4 = 0 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_COUNTERS_1_PERFMON_COUNTER_4_LEN = 16 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_COUNTERS_1_PERFMON_COUNTER_5 = 16 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_COUNTERS_1_PERFMON_COUNTER_5_LEN = 16 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_COUNTERS_1_PERFMON_COUNTER_6 = 32 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_COUNTERS_1_PERFMON_COUNTER_6_LEN = 16 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_COUNTERS_1_PERFMON_COUNTER_7 = 48 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_COUNTERS_1_PERFMON_COUNTER_7_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_SEL_CONFIG_SELECT_0 = 0 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_SEL_CONFIG_SELECT_0_LEN = 8 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_SEL_CONFIG_SELECT_1 = 8 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_SEL_CONFIG_SELECT_1_LEN = 8 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_SEL_CONFIG_SELECT_2 = 16 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_SEL_CONFIG_SELECT_2_LEN = 8 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_SEL_CONFIG_SELECT_3 = 24 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_SEL_CONFIG_SELECT_3_LEN = 8 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_SEL_CONFIG_SELECT_4 = 32 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_SEL_CONFIG_SELECT_4_LEN = 8 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_SEL_CONFIG_SELECT_5 = 40 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_SEL_CONFIG_SELECT_5_LEN = 8 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_SEL_CONFIG_SELECT_6 = 48 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_SEL_CONFIG_SELECT_6_LEN = 8 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_SEL_CONFIG_SELECT_7 = 56 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_SEL_CONFIG_SELECT_7_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_ENABLE_0 = 0 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_ENABLE_0_LEN = 2 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_ENABLE_1 = 2 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_ENABLE_1_LEN = 2 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_ENABLE_2 = 4 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_ENABLE_2_LEN = 2 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_ENABLE_3 = 6 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_ENABLE_3_LEN = 2 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_ENABLE_4 = 8 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_ENABLE_4_LEN = 2 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_ENABLE_5 = 10 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_ENABLE_5_LEN = 2 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_ENABLE_6 = 12 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_ENABLE_6_LEN = 2 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_ENABLE_7 = 14 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_ENABLE_7_LEN = 2 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_SIZE_0 = 16 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_SIZE_0_LEN = 2 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_SIZE_1 = 18 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_SIZE_1_LEN = 2 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_SIZE_2 = 20 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_SIZE_2_LEN = 2 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_SIZE_3 = 22 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_SIZE_3_LEN = 2 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_SIZE_4 = 24 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_SIZE_4_LEN = 2 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_SIZE_5 = 26 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_SIZE_5_LEN = 2 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_SIZE_6 = 28 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_SIZE_6_LEN = 2 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_SIZE_7 = 30 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_SIZE_7_LEN = 2 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_PMULET_FREEZE_MODE = 32 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_COMMON_FREEZE_MODE = 33 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_RESET_MODE = 34 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_PERFTRACE_ENABLE = 35 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_PERFTRACE_FIXED_WINDOW = 36 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_PERFTRACE_PRESCALE = 37 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_PERFTRACE_MODE = 38 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_PERFTRACE_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_CONFIG_0 = 40 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_CONFIG_0_LEN = 12 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_CONFIG_1 = 52 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_PERF_TRACE_CONFIG_CONFIG_1_LEN = 12 ;
+
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_REPLAY_THRESHOLD_THRESH_TB_SEL = 0 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_REPLAY_THRESHOLD_THRESH_TB_SEL_LEN = 4 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_REPLAY_THRESHOLD_THRESH_TAP_SEL = 4 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_REPLAY_THRESHOLD_THRESH_TAP_SEL_LEN = 4 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_REPLAY_THRESHOLD_THRESH_ENABLE = 8 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_REPLAY_THRESHOLD_THRESH_ENABLE_LEN = 3 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_REPLAY_THRESHOLD_THRESH_UNUSED1 = 11 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_REPLAY_THRESHOLD_THRESH_UNUSED1_LEN = 15 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_REPLAY_THRESHOLD_THRESH_LINK0_CLEAR = 26 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_REPLAY_THRESHOLD_THRESH_LINK1_CLEAR = 27 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_REPLAY_THRESHOLD_THRESH_DIS_TB_CLEAR = 28 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_REPLAY_THRESHOLD_THRESH_DIS_TAP_CLEAR = 29 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_REPLAY_THRESHOLD_THRESH_DIS_TAP_STOP = 30 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_REPLAY_THRESHOLD_THRESH_UNUSED2 = 31 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_REPLAY_THRESHOLD_THRESH_LINK0_COUNT = 32 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_REPLAY_THRESHOLD_THRESH_LINK0_COUNT_LEN = 16 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_REPLAY_THRESHOLD_THRESH_LINK1_COUNT = 48 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_REPLAY_THRESHOLD_THRESH_LINK1_COUNT_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_SEC_CONFIG_ENABLE_ERR_INJ = 0 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_SEC_CONFIG_ENABLE_TRACE = 1 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_SEC_CONFIG_UNUSED4 = 2 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_SEC_CONFIG_UNUSED4_LEN = 14 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_SEC_CONFIG_SBE_ERROR_RATE = 16 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_SEC_CONFIG_SBE_ERROR_RATE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_SEC_CONFIG_RAND_ERROR_RATE = 18 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_SEC_CONFIG_RAND_ERROR_RATE_LEN = 6 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_SEC_CONFIG_UNUSED5 = 24 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_SEC_CONFIG_UNUSED5_LEN = 24 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_SEC_CONFIG_EDPL_RATE = 48 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_SEC_CONFIG_EDPL_RATE_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_SL_ECC_THRESHOLD_THRESH_TB_SEL = 0 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_SL_ECC_THRESHOLD_THRESH_TB_SEL_LEN = 4 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_SL_ECC_THRESHOLD_THRESH_TAP_SEL = 4 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_SL_ECC_THRESHOLD_THRESH_TAP_SEL_LEN = 4 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_SL_ECC_THRESHOLD_THRESH_ENABLE = 8 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_SL_ECC_THRESHOLD_THRESH_ENABLE_LEN = 3 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_SL_ECC_THRESHOLD_THRESH_UNUSED1 = 11 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_SL_ECC_THRESHOLD_THRESH_UNUSED1_LEN = 15 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_SL_ECC_THRESHOLD_THRESH_LINK0_CLEAR = 26 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_SL_ECC_THRESHOLD_THRESH_LINK1_CLEAR = 27 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_SL_ECC_THRESHOLD_THRESH_DIS_TB_CLEAR = 28 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_SL_ECC_THRESHOLD_THRESH_DIS_TAP_CLEAR = 29 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_SL_ECC_THRESHOLD_THRESH_DIS_TAP_STOP = 30 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_SL_ECC_THRESHOLD_THRESH_UNUSED2 = 31 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_SL_ECC_THRESHOLD_THRESH_LINK0_COUNT = 32 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_SL_ECC_THRESHOLD_THRESH_LINK0_COUNT_LEN = 16 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_SL_ECC_THRESHOLD_THRESH_LINK1_COUNT = 48 ;
+static const uint8_t P9N2_XBUS_C0_S0_P0_E9_LL0_IOEL_SL_ECC_THRESHOLD_THRESH_LINK1_COUNT_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_MASK_REG_LINK0_TRAINED = 0 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_MASK_REG_LINK1_TRAINED = 1 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_MASK_REG_LINK0_REPLAY_THRESHOLD = 4 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_MASK_REG_LINK1_REPLAY_THRESHOLD = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_MASK_REG_LINK0_CRC_ERROR = 6
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_MASK_REG_LINK1_CRC_ERROR = 7
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_MASK_REG_LINK0_NAK_RECEIVED =
+ 8 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_MASK_REG_LINK1_NAK_RECEIVED =
+ 9 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_MASK_REG_LINK0_REPLAY_BUFFER_FULL = 10 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_MASK_REG_LINK1_REPLAY_BUFFER_FULL = 11 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_MASK_REG_LINK0_SL_ECC_THRESHOLD = 12 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_MASK_REG_LINK1_SL_ECC_THRESHOLD = 13 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_MASK_REG_LINK0_SL_ECC_CORRECTABLE = 14 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_MASK_REG_LINK1_SL_ECC_CORRECTABLE = 15 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_MASK_REG_LINK0_SL_ECC_UE = 16
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_MASK_REG_LINK1_SL_ECC_UE = 17
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_MASK_REG_LINK0_TOD_ECC_ERROR =
+ 18 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_MASK_REG_LINK1_TOD_ECC_ERROR =
+ 19 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_MASK_REG_LINK0_TCOMPLETE_BAD =
+ 40 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_MASK_REG_LINK1_TCOMPLETE_BAD =
+ 41 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_MASK_REG_LINK0_SPARE_DONE = 44
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_MASK_REG_LINK1_SPARE_DONE = 45
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_MASK_REG_PSAVE_INVALID_STATE =
+ 51 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_MASK_REG_LINK0_CORRECTABLE_ARRAY_ERROR = 52 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_MASK_REG_LINK1_CORRECTABLE_ARRAY_ERROR = 53 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_MASK_REG_LINK0_UNCORRECTABLE_ARRAY_ERROR = 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_MASK_REG_LINK1_UNCORRECTABLE_ARRAY_ERROR = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_MASK_REG_LINK0_TRAINING_FAILED
+ = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_MASK_REG_LINK1_TRAINING_FAILED
+ = 57 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_MASK_REG_LINK0_UNRECOVERABLE_ERROR = 58 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_MASK_REG_LINK1_UNRECOVERABLE_ERROR = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_MASK_REG_LINK0_INTERNAL_ERROR
+ = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_MASK_REG_LINK1_INTERNAL_ERROR
+ = 61 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_MASK_REG_SCOM_ERR_DUP = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_MASK_REG_SCOM_ERR = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_REG_LINK0_TRAINED = 0 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_REG_LINK1_TRAINED = 1 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_REG_LINK0_REPLAY_THRESHOLD = 4
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_REG_LINK1_REPLAY_THRESHOLD = 5
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_REG_LINK0_CRC_ERROR = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_REG_LINK1_CRC_ERROR = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_REG_LINK0_NAK_RECEIVED = 8 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_REG_LINK1_NAK_RECEIVED = 9 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_REG_LINK0_REPLAY_BUFFER_FULL =
+ 10 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_REG_LINK1_REPLAY_BUFFER_FULL =
+ 11 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_REG_LINK0_SL_ECC_THRESHOLD =
+ 12 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_REG_LINK1_SL_ECC_THRESHOLD =
+ 13 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_REG_LINK0_SL_ECC_CORRECTABLE =
+ 14 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_REG_LINK1_SL_ECC_CORRECTABLE =
+ 15 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_REG_LINK0_SL_ECC_UE = 16 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_REG_LINK1_SL_ECC_UE = 17 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_REG_LINK0_TOD_ECC_ERROR = 18
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_REG_LINK1_TOD_ECC_ERROR = 19
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_REG_LINK0_TCOMPLETE_BAD = 40
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_REG_LINK1_TCOMPLETE_BAD = 41
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_REG_LINK0_SPARE_DONE = 44 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_REG_LINK1_SPARE_DONE = 45 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_REG_PSAVE_INVALID_STATE = 51
+ ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_REG_LINK0_CORRECTABLE_ARRAY_ERROR = 52 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_REG_LINK1_CORRECTABLE_ARRAY_ERROR = 53 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_REG_LINK0_UNCORRECTABLE_ARRAY_ERROR = 54 ;
+static const uint8_t
+P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_REG_LINK1_UNCORRECTABLE_ARRAY_ERROR = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_REG_LINK0_TRAINING_FAILED = 56
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_REG_LINK1_TRAINING_FAILED = 57
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_REG_LINK0_UNRECOVERABLE_ERROR
+ = 58 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_REG_LINK1_UNRECOVERABLE_ERROR
+ = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_REG_LINK0_INTERNAL_ERROR = 60
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_REG_LINK1_INTERNAL_ERROR = 61
+ ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_REG_SCOM_ERR_DUP = 62 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_C0_S0_P0_E9_LL1_IOEL_FIR_REG_SCOM_ERR = 63 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONFIG_LINK_PAIR = 0 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONFIG_DISABLE_SL_ECC = 1 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONFIG_CRC_LANE_ID = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONFIG_EDPL_LANE_ID = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONFIG_SL_UE_CRC_ERR = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONFIG_REPORT_SL_CHKBIT_ERR = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONFIG_BW_SAMPLE_SIZE = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONFIG_BW_WINDOW_SIZE = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONFIG_UNUSED1 = 8 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONFIG_UNUSED1_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONFIG_PACKET_DELAY_LIMIT = 11 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONFIG_PACKET_DELAY_LIMIT_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONFIG_TDM_DELAY = 16 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONFIG_TDM_DELAY_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONFIG_AUTO_TDM_TX = 20 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONFIG_AUTO_TDM_RX = 21 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONFIG_AUTO_TDM_AND_NOT_OR = 22 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONFIG_UNUSED2 = 23 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONFIG_AUTO_TDM_BW_DIFF = 24 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONFIG_AUTO_TDM_BW_DIFF_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONFIG_AUTO_TDM_ERROR_RATE = 28 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONFIG_AUTO_TDM_ERROR_RATE_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONFIG_AUTO_TDM_EXIT_RATE = 32 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONFIG_AUTO_TDM_EXIT_RATE_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONFIG_UNUSED3 = 36 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONFIG_UNUSED3_LEN = 8 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONFIG_PSAVE_TIMEOUT = 44 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONFIG_PSAVE_TIMEOUT_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONFIG_TIMEOUT = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONFIG_TIMEOUT_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONFIG_TIMER_1US = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONFIG_TIMER_1US_LEN = 12 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONTROL_UNUSED0A = 0 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONTROL_LINK0_STARTUP = 1 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONTROL_UNUSED0B = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONTROL_UNUSED0B_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONTROL_LINK0_ERR_INJ_COMMAND = 8 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONTROL_LINK0_ERR_INJ_COMMAND_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONTROL_LINK0_ERR_INJ_COMMAND_LANES = 12 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONTROL_LINK0_ERR_INJ_COMMAND_LANES_LEN = 16 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONTROL_LINK0_COMMAND = 28 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONTROL_LINK0_COMMAND_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONTROL_UNUSED1A = 32 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONTROL_LINK1_STARTUP = 33 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONTROL_UNUSED1B = 34 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONTROL_UNUSED1B_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONTROL_LINK1_ERR_INJ_COMMAND = 40 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONTROL_LINK1_ERR_INJ_COMMAND_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONTROL_LINK1_ERR_INJ_COMMAND_LANES = 44 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONTROL_LINK1_ERR_INJ_COMMAND_LANES_LEN = 16 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONTROL_LINK1_COMMAND = 60 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_CONTROL_LINK1_COMMAND_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_DLL_STATUS_LINK0_CURRENT_STATE = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_DLL_STATUS_LINK0_CURRENT_STATE_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_DLL_STATUS_LINK0_PRIOR_STATE = 12 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_DLL_STATUS_LINK0_PRIOR_STATE_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_DLL_STATUS_LINK0_MAX_PKT_TIMER = 19 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_DLL_STATUS_LINK0_MAX_PKT_TIMER_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_DLL_STATUS_LINK1_CURRENT_STATE = 28 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_DLL_STATUS_LINK1_CURRENT_STATE_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_DLL_STATUS_LINK1_PRIOR_STATE = 36 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_DLL_STATUS_LINK1_PRIOR_STATE_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_DLL_STATUS_LINK1_MAX_PKT_TIMER = 43 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_DLL_STATUS_LINK1_MAX_PKT_TIMER_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_ERR_INJ_LFSR_LFSR = 0 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_ERR_INJ_LFSR_LFSR_LEN = 61 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_FIR_ACTION0_REG_ACTION0 = 0 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_FIR_ACTION0_REG_ACTION0_LEN = 64 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_FIR_ACTION1_REG_ACTION1 = 0 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_FIR_ACTION1_REG_ACTION1_LEN = 64 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_FIR_WOF_REG_WOF = 0 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_FIR_WOF_REG_WOF_LEN = 64 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LAT_MEASURE_LINK0_ROUND_TRIP_VALID = 0 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LAT_MEASURE_LINK0_ROUND_TRIP = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LAT_MEASURE_LINK0_ROUND_TRIP_LEN = 10 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LAT_MEASURE_LINK1_ROUND_TRIP_VALID = 12 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LAT_MEASURE_LINK1_ROUND_TRIP = 14 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LAT_MEASURE_LINK1_ROUND_TRIP_LEN = 10 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LAT_MEASURE_LOCAL_LATENCY_DIFFERENCE_VALID = 24 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LAT_MEASURE_LOCAL_LATENCY_LONGER_LINK = 25 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LAT_MEASURE_LOCAL_LATENCY_DIFFERENCE = 29 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LAT_MEASURE_LOCAL_LATENCY_DIFFERENCE_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LAT_MEASURE_REMOTE_LATENCY_DIFFERENCE_VALID = 36 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LAT_MEASURE_REMOTE_LATENCY_LONGER_LINK = 37 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LAT_MEASURE_REMOTE_LATENCY_DIFFERENCE = 41 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LAT_MEASURE_REMOTE_LATENCY_DIFFERENCE_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LAT_MEASURE_LINK0_TOD_LATENCY = 49 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LAT_MEASURE_LINK0_TOD_LATENCY_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LAT_MEASURE_LINK1_TOD_LATENCY = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LAT_MEASURE_LINK1_TOD_LATENCY_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_0 = 0 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_0_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_1 = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_1_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_2 = 8 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_2_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_3 = 12 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_3_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_4 = 16 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_4_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_5 = 20 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_5_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_6 = 24 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_6_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_7 = 28 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_7_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_8 = 32 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_8_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_9 = 36 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_9_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_10 = 40 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_10_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_11 = 44 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_11_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_ERROR_STATUS_RESET_KEEPER = 0 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_ERROR_STATUS_CE = 1 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_ERROR_STATUS_CE_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_ERROR_STATUS_UE = 8 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_ERROR_STATUS_UE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_ERROR_STATUS_TRAIN = 16 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_ERROR_STATUS_TRAIN_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_ERROR_STATUS_UNRECOV = 24 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_ERROR_STATUS_UNRECOV_LEN = 11 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_ERROR_STATUS_INTERNAL = 44 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_ERROR_STATUS_INTERNAL_LEN = 18 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_INFO_MAX_TIMEOUT = 0 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_INFO_MAX_TIMEOUT_LEN = 16 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_INFO_FRAME_CAP_VALID = 16 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_INFO_FRAME_CAP_INST = 17 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_INFO_FRAME_CAP_ADDR = 19 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_INFO_FRAME_CAP_ADDR_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_INFO_FRAME_CAP_SYN = 24 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_INFO_FRAME_CAP_SYN_LEN = 8 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_INFO_REPLAY_CAP_VALID = 32 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_INFO_REPLAY_CAP_INST = 34 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_INFO_REPLAY_CAP_ADDR = 37 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_INFO_REPLAY_CAP_ADDR_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_INFO_REPLAY_CAP_SYN = 44 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_INFO_REPLAY_CAP_SYN_LEN = 8 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_INFO_ACK_FIFO_CAP_VALID = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_INFO_ACK_FIFO_CAP_ADDR = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_INFO_ACK_FIFO_CAP_ADDR_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_QUALITY_TX_BW = 1 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_QUALITY_TX_BW_LEN = 11 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_QUALITY_RX_BW = 13 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_QUALITY_RX_BW_LEN = 11 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_QUALITY_ERROR_RATE = 25 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_QUALITY_ERROR_RATE_LEN = 23 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_CRC = 0 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_CRC_LEN = 28 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_CRC_UNUSED1 = 28 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_CRC_UNUSED1_LEN = 8 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_SLECC_SYN0 = 36 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_SLECC_SYN0_LEN = 8 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_SLECC_SYN1 = 44 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_SLECC_SYN1_LEN = 8 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_CRC_UNUSED2 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_CRC_UNUSED2_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_VALID = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_CRC_UNUSED3 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_CRC_UNUSED3_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_CRC_LANE = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_CRC_LANE_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_0 = 0 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_0_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_1 = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_1_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_2 = 8 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_2_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_3 = 12 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_3_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_4 = 16 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_4_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_5 = 20 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_5_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_6 = 24 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_6_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_7 = 28 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_7_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_8 = 32 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_8_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_9 = 36 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_9_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_10 = 40 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_10_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_11 = 44 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_11_LEN = 4 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_ERROR_STATUS_RESET_KEEPER = 0 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_ERROR_STATUS_CE = 1 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_ERROR_STATUS_CE_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_ERROR_STATUS_UE = 8 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_ERROR_STATUS_UE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_ERROR_STATUS_TRAIN = 16 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_ERROR_STATUS_TRAIN_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_ERROR_STATUS_UNRECOV = 24 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_ERROR_STATUS_UNRECOV_LEN = 11 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_ERROR_STATUS_INTERNAL = 44 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_ERROR_STATUS_INTERNAL_LEN = 18 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_INFO_MAX_TIMEOUT = 0 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_INFO_MAX_TIMEOUT_LEN = 16 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_INFO_FRAME_CAP_VALID = 16 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_INFO_FRAME_CAP_INST = 17 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_INFO_FRAME_CAP_ADDR = 19 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_INFO_FRAME_CAP_ADDR_LEN = 5 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_INFO_FRAME_CAP_SYN = 24 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_INFO_FRAME_CAP_SYN_LEN = 8 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_INFO_REPLAY_CAP_VALID = 32 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_INFO_REPLAY_CAP_INST = 34 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_INFO_REPLAY_CAP_ADDR = 37 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_INFO_REPLAY_CAP_ADDR_LEN = 7 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_INFO_REPLAY_CAP_SYN = 44 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_INFO_REPLAY_CAP_SYN_LEN = 8 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_INFO_ACK_FIFO_CAP_VALID = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_INFO_ACK_FIFO_CAP_ADDR = 57 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_INFO_ACK_FIFO_CAP_ADDR_LEN = 7 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_QUALITY_TX_BW = 1 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_QUALITY_TX_BW_LEN = 11 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_QUALITY_RX_BW = 13 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_QUALITY_RX_BW_LEN = 11 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_QUALITY_ERROR_RATE = 25 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_QUALITY_ERROR_RATE_LEN = 23 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_CRC = 0 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_CRC_LEN = 28 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_CRC_UNUSED1 = 28 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_CRC_UNUSED1_LEN = 8 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_SLECC_SYN0 = 36 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_SLECC_SYN0_LEN = 8 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_SLECC_SYN1 = 44 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_SLECC_SYN1_LEN = 8 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_CRC_UNUSED2 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_CRC_UNUSED2_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_VALID = 55 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_CRC_UNUSED3 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_CRC_UNUSED3_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_CRC_LANE = 59 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_CRC_LANE_LEN = 5 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_COUNTERS_0_PERFMON_COUNTER = 0 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_COUNTERS_0_PERFMON_COUNTER_LEN = 16 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_COUNTERS_0_PERFMON_COUNTER_1 = 16 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_COUNTERS_0_PERFMON_COUNTER_1_LEN = 16 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_COUNTERS_0_PERFMON_COUNTER_2 = 32 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_COUNTERS_0_PERFMON_COUNTER_2_LEN = 16 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_COUNTERS_0_PERFMON_COUNTER_3 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_COUNTERS_0_PERFMON_COUNTER_3_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_COUNTERS_1_PERFMON_COUNTER_4 = 0 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_COUNTERS_1_PERFMON_COUNTER_4_LEN = 16 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_COUNTERS_1_PERFMON_COUNTER_5 = 16 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_COUNTERS_1_PERFMON_COUNTER_5_LEN = 16 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_COUNTERS_1_PERFMON_COUNTER_6 = 32 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_COUNTERS_1_PERFMON_COUNTER_6_LEN = 16 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_COUNTERS_1_PERFMON_COUNTER_7 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_COUNTERS_1_PERFMON_COUNTER_7_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_SEL_CONFIG_SELECT_0 = 0 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_SEL_CONFIG_SELECT_0_LEN = 8 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_SEL_CONFIG_SELECT_1 = 8 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_SEL_CONFIG_SELECT_1_LEN = 8 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_SEL_CONFIG_SELECT_2 = 16 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_SEL_CONFIG_SELECT_2_LEN = 8 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_SEL_CONFIG_SELECT_3 = 24 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_SEL_CONFIG_SELECT_3_LEN = 8 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_SEL_CONFIG_SELECT_4 = 32 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_SEL_CONFIG_SELECT_4_LEN = 8 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_SEL_CONFIG_SELECT_5 = 40 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_SEL_CONFIG_SELECT_5_LEN = 8 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_SEL_CONFIG_SELECT_6 = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_SEL_CONFIG_SELECT_6_LEN = 8 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_SEL_CONFIG_SELECT_7 = 56 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_SEL_CONFIG_SELECT_7_LEN = 8 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_ENABLE_0 = 0 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_ENABLE_0_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_ENABLE_1 = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_ENABLE_1_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_ENABLE_2 = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_ENABLE_2_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_ENABLE_3 = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_ENABLE_3_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_ENABLE_4 = 8 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_ENABLE_4_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_ENABLE_5 = 10 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_ENABLE_5_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_ENABLE_6 = 12 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_ENABLE_6_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_ENABLE_7 = 14 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_ENABLE_7_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_SIZE_0 = 16 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_SIZE_0_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_SIZE_1 = 18 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_SIZE_1_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_SIZE_2 = 20 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_SIZE_2_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_SIZE_3 = 22 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_SIZE_3_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_SIZE_4 = 24 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_SIZE_4_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_SIZE_5 = 26 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_SIZE_5_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_SIZE_6 = 28 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_SIZE_6_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_SIZE_7 = 30 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_SIZE_7_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_PMULET_FREEZE_MODE = 32 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_COMMON_FREEZE_MODE = 33 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_RESET_MODE = 34 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_PERFTRACE_ENABLE = 35 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_PERFTRACE_FIXED_WINDOW = 36 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_PERFTRACE_PRESCALE = 37 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_PERFTRACE_MODE = 38 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_PERFTRACE_MODE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_CONFIG_0 = 40 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_CONFIG_0_LEN = 12 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_CONFIG_1 = 52 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_PERF_TRACE_CONFIG_CONFIG_1_LEN = 12 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_REPLAY_THRESHOLD_THRESH_TB_SEL = 0 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_REPLAY_THRESHOLD_THRESH_TB_SEL_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_REPLAY_THRESHOLD_THRESH_TAP_SEL = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_REPLAY_THRESHOLD_THRESH_TAP_SEL_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_REPLAY_THRESHOLD_THRESH_ENABLE = 8 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_REPLAY_THRESHOLD_THRESH_ENABLE_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_REPLAY_THRESHOLD_THRESH_UNUSED1 = 11 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_REPLAY_THRESHOLD_THRESH_UNUSED1_LEN = 15 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_REPLAY_THRESHOLD_THRESH_LINK0_CLEAR = 26 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_REPLAY_THRESHOLD_THRESH_LINK1_CLEAR = 27 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_REPLAY_THRESHOLD_THRESH_DIS_TB_CLEAR = 28 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_REPLAY_THRESHOLD_THRESH_DIS_TAP_CLEAR = 29 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_REPLAY_THRESHOLD_THRESH_DIS_TAP_STOP = 30 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_REPLAY_THRESHOLD_THRESH_UNUSED2 = 31 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_REPLAY_THRESHOLD_THRESH_LINK0_COUNT = 32 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_REPLAY_THRESHOLD_THRESH_LINK0_COUNT_LEN = 16 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_REPLAY_THRESHOLD_THRESH_LINK1_COUNT = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_REPLAY_THRESHOLD_THRESH_LINK1_COUNT_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_SEC_CONFIG_ENABLE_ERR_INJ = 0 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_SEC_CONFIG_ENABLE_TRACE = 1 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_SEC_CONFIG_UNUSED4 = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_SEC_CONFIG_UNUSED4_LEN = 14 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_SEC_CONFIG_SBE_ERROR_RATE = 16 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_SEC_CONFIG_SBE_ERROR_RATE_LEN = 2 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_SEC_CONFIG_RAND_ERROR_RATE = 18 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_SEC_CONFIG_RAND_ERROR_RATE_LEN = 6 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_SEC_CONFIG_UNUSED5 = 24 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_SEC_CONFIG_UNUSED5_LEN = 24 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_SEC_CONFIG_EDPL_RATE = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_SEC_CONFIG_EDPL_RATE_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_SL_ECC_THRESHOLD_THRESH_TB_SEL = 0 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_SL_ECC_THRESHOLD_THRESH_TB_SEL_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_SL_ECC_THRESHOLD_THRESH_TAP_SEL = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_SL_ECC_THRESHOLD_THRESH_TAP_SEL_LEN = 4 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_SL_ECC_THRESHOLD_THRESH_ENABLE = 8 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_SL_ECC_THRESHOLD_THRESH_ENABLE_LEN = 3 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_SL_ECC_THRESHOLD_THRESH_UNUSED1 = 11 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_SL_ECC_THRESHOLD_THRESH_UNUSED1_LEN = 15 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_SL_ECC_THRESHOLD_THRESH_LINK0_CLEAR = 26 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_SL_ECC_THRESHOLD_THRESH_LINK1_CLEAR = 27 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_SL_ECC_THRESHOLD_THRESH_DIS_TB_CLEAR = 28 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_SL_ECC_THRESHOLD_THRESH_DIS_TAP_CLEAR = 29 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_SL_ECC_THRESHOLD_THRESH_DIS_TAP_STOP = 30 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_SL_ECC_THRESHOLD_THRESH_UNUSED2 = 31 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_SL_ECC_THRESHOLD_THRESH_LINK0_COUNT = 32 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_SL_ECC_THRESHOLD_THRESH_LINK0_COUNT_LEN = 16 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_SL_ECC_THRESHOLD_THRESH_LINK1_COUNT = 48 ;
+static const uint8_t P9N2_XBUS_1_C0_S0_P0_E9_LL1_IOEL_SL_ECC_THRESHOLD_THRESH_LINK1_COUNT_LEN = 16 ;
+
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_MIB_XIICAC_ICACHE_TAG_ADDR = 0 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_MIB_XIICAC_ICACHE_TAG_ADDR_LEN = 27 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_MIB_XIICAC_ICACHE_ERR = 32 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_MIB_XIICAC_PIB_IFETCH_PENDING = 34 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_MIB_XIICAC_XIMEM_MEM_IFETCH_PENDING = 35 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_MIB_XIICAC_ICACHE_VALID = 36 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_MIB_XIICAC_ICACHE_VALID_LEN = 4 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_MIB_XIICAC_ICACHE_LINE2_VALID = 40 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_MIB_XIICAC_ICACHE_LINE2_VALID_LEN = 4 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_MIB_XIICAC_ICACHE_LINE_PTR = 45 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_MIB_XIICAC_ICACHE_LINE2_ERR = 46 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_MIB_XIICAC_ICACHE_PREFETCH_PENDING = 47 ;
+
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_MIB_XIMEM_MEM_ADDR = 0 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_MIB_XIMEM_MEM_ADDR_LEN = 32 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_MIB_XIMEM_MEM_R_NW = 32 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_MIB_XIMEM_MEM_BUSY = 33 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_MIB_XIMEM_MEM_IMPRECISE_ERROR_PENDING = 34 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_MIB_XIMEM_MEM_BYTE_ENABLE = 35 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_MIB_XIMEM_MEM_BYTE_ENABLE_LEN = 8 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_MIB_XIMEM_MEM_LINE_MODE = 43 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_MIB_XIMEM_MEM_ERROR = 49 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_MIB_XIMEM_MEM_ERROR_LEN = 3 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_MIB_XIMEM_MEM_IFETCH_PENDING = 62 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_MIB_XIMEM_MEM_DATAOP_PENDING = 63 ;
+
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_MIB_XISGB_STORE_ADDRESS = 0 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_MIB_XISGB_STORE_ADDRESS_LEN = 32 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_MIB_XISGB_XIMEM_MEM_IMPRECISE_ERROR_PENDING = 35 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_MIB_XISGB_SGB_BYTE_VALID = 36 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_MIB_XISGB_SGB_BYTE_VALID_LEN = 4 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_MIB_XISGB_SGB_FLUSH_PENDING = 63 ;
+
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_FIR_ACTION0_REG_ACTION0 = 0 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_FIR_ACTION0_REG_ACTION0_LEN = 13 ;
+
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_FIR_ACTION1_REG_ACTION1 = 0 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_FIR_ACTION1_REG_ACTION1_LEN = 13 ;
+
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_FIR_WOF_REG_WOF = 0 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_FIR_WOF_REG_WOF_LEN = 13 ;
+
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIDBGPRO_XSR_HS = 0 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIDBGPRO_XSR_HC = 1 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIDBGPRO_XSR_HC_LEN = 3 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIDBGPRO_XSR_HCP = 4 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIDBGPRO_XSR_RIP = 5 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIDBGPRO_XSR_SIP = 6 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIDBGPRO_XSR_TRAP = 7 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIDBGPRO_XSR_IAC = 8 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIDBGPRO_NULL_MSR_SIBRC = 9 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIDBGPRO_NULL_MSR_SIBRC_LEN = 3 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIDBGPRO_XSR_DACR = 12 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIDBGPRO_XSR_DACW = 13 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIDBGPRO_NULL_MSR_WE = 14 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIDBGPRO_XSR_TRH = 15 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIDBGPRO_XSR_SMS = 16 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIDBGPRO_XSR_SMS_LEN = 4 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIDBGPRO_NULL_MSR_LP = 20 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIDBGPRO_XSR_EP = 21 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIDBGPRO_XSR_PTR = 24 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIDBGPRO_XSR_ST = 25 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIDBGPRO_XSR_MFE = 28 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIDBGPRO_XSR_MCS = 29 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIDBGPRO_XSR_MCS_LEN = 3 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIDBGPRO_IAR = 32 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIDBGPRO_IAR_LEN = 30 ;
+
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMDBG_XSR_HS = 0 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMDBG_XSR_HC = 1 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMDBG_XSR_HC_LEN = 3 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMDBG_XSR_HCP = 4 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMDBG_XSR_RIP = 5 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMDBG_XSR_SIP = 6 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMDBG_XSR_TRAP = 7 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMDBG_XSR_IAC = 8 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMDBG_NULL_MSR_SIBRC = 9 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMDBG_NULL_MSR_SIBRC_LEN = 3 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMDBG_XSR_DACR = 12 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMDBG_XSR_DACW = 13 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMDBG_NULL_MSR_WE = 14 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMDBG_XSR_TRH = 15 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMDBG_XSR_SMS = 16 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMDBG_XSR_SMS_LEN = 4 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMDBG_NULL_MSR_LP = 20 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMDBG_XSR_EP = 21 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMDBG_XSR_PTR = 24 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMDBG_XSR_ST = 25 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMDBG_XSR_MFE = 28 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMDBG_XSR_MCS = 29 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMDBG_XSR_MCS_LEN = 3 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMDBG_XIRAMRA_SPRG0 = 32 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMDBG_XIRAMRA_SPRG0_LEN = 32 ;
+
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMEDR_XIRAMGA_IR = 0 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMEDR_XIRAMGA_IR_LEN = 32 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMEDR_EDR = 32 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMEDR_EDR_LEN = 32 ;
+
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMGA_IR = 0 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMGA_IR_LEN = 32 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMGA_XIRAMRA_SPRG0 = 32 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMGA_XIRAMRA_SPRG0_LEN = 32 ;
+
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMRA_XIXCR_XCR = 1 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMRA_XIXCR_XCR_LEN = 3 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMRA_SPRG0 = 32 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIRAMRA_SPRG0_LEN = 32 ;
+
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIXCR_XCR = 1 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_PPE_XIXCR_XCR_LEN = 3 ;
+
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_SCOM_PPE_CNTL_IORESET = 0 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_SCOM_PPE_CNTL_PDWN = 1 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_SCOM_PPE_CNTL_INTERRUPT = 2 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_SCOM_PPE_CNTL_ARB_ECC_INJECT_ERR = 3 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_SCOM_PPE_CNTL_SPARES = 4 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_SCOM_PPE_CNTL_SPARES_LEN = 12 ;
+
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_SCOM_PPE_WORK_REG1_WORK1 = 0 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_SCOM_PPE_WORK_REG1_WORK1_LEN = 32 ;
+
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_SCOM_PPE_WORK_REG2_WORK2 = 0 ;
+static const uint8_t P9N2_XBUS_IOPPE_C0_S0_P0_E9_SCOM_PPE_WORK_REG2_WORK2_LEN = 32 ;
+
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_HI_DATA_REG_DATA = 0 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_HI_DATA_REG_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_LO_DATA_REG_DATA = 0 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_LO_DATA_REG_DATA_LEN = 32 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_LO_DATA_REG_ADDRESS = 32 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN = 10 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK = 42 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN = 9 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID = 51 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN = 52 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_LO_DATA_REG_RUNNING = 53 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS = 54 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN = 10 ;
+
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE = 0 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE = 1 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE = 2 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN = 8 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRCTRL_CONFIG_BANK_MODE = 10 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRCTRL_CONFIG_ENH_MODE = 11 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL = 12 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN = 2 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRCTRL_CONFIG_SELECT_CONTROL = 14 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRCTRL_CONFIG_SELECT_CONTROL_LEN = 4 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRCTRL_CONFIG_RUN_HOLD_OFF = 18 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRCTRL_CONFIG_RUN_STATUS = 19 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRCTRL_CONFIG_RUN_STICKY = 20 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRCTRL_CONFIG_DISABLE_BANK_EDGE_DETECT = 21 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRCTRL_CONFIG_CONTROL_UNUSED = 22 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRCTRL_CONFIG_CONTROL_UNUSED_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 = 0 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN = 64 ;
+
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 = 0 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN = 24 ;
+
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA = 0 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN = 24 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB = 24 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN = 24 ;
+
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC = 0 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN = 24 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERND = 24 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN = 24 ;
+
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKA = 0 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN = 24 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKB = 24 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN = 24 ;
+
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKC = 0 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN = 24 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKD = 24 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN = 24 ;
+
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION = 0 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK = 1 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL = 2 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN = 2 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL = 4 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN = 2 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL = 6 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN = 2 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL = 8 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN = 2 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK = 10 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN = 4 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK = 14 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN = 4 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK = 18 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN = 4 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK = 22 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN = 4 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE = 26 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE = 27 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE = 28 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN = 4 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_9_ERROR_CMP_MASK = 32 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_9_ERROR_CMP_PATTERN = 33 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_ERR_CMP = 34 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_ERR_CMP = 35 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES = 36 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR0_TRACE_TRDATA_CONFIG_9_SPARE_LT = 37 ;
+
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_HI_DATA_REG_DATA = 0 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_HI_DATA_REG_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_LO_DATA_REG_DATA = 0 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_LO_DATA_REG_DATA_LEN = 32 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_LO_DATA_REG_ADDRESS = 32 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_LO_DATA_REG_ADDRESS_LEN = 10 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_LO_DATA_REG_LAST_BANK = 42 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_LO_DATA_REG_LAST_BANK_LEN = 9 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_LO_DATA_REG_LAST_BANK_VALID = 51 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_LO_DATA_REG_WRITE_ON_RUN = 52 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_LO_DATA_REG_RUNNING = 53 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS = 54 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN = 10 ;
+
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE = 0 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE = 1 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE = 2 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN = 8 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRCTRL_CONFIG_BANK_MODE = 10 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRCTRL_CONFIG_ENH_MODE = 11 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL = 12 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN = 2 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRCTRL_CONFIG_SELECT_CONTROL = 14 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRCTRL_CONFIG_SELECT_CONTROL_LEN = 4 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRCTRL_CONFIG_RUN_HOLD_OFF = 18 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRCTRL_CONFIG_RUN_STATUS = 19 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRCTRL_CONFIG_RUN_STICKY = 20 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRCTRL_CONFIG_DISABLE_BANK_EDGE_DETECT = 21 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRCTRL_CONFIG_CONTROL_UNUSED = 22 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRCTRL_CONFIG_CONTROL_UNUSED_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 = 0 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN = 64 ;
+
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 = 0 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN = 24 ;
+
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA = 0 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN = 24 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB = 24 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN = 24 ;
+
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC = 0 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN = 24 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERND = 24 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERND_LEN = 24 ;
+
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKA = 0 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKA_LEN = 24 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKB = 24 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKB_LEN = 24 ;
+
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKC = 0 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKC_LEN = 24 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKD = 24 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKD_LEN = 24 ;
+
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION = 0 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK = 1 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL = 2 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN = 2 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL = 4 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN = 2 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL = 6 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN = 2 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL = 8 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN = 2 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK = 10 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN = 4 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK = 14 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN = 4 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK = 18 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN = 4 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK = 22 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN = 4 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE = 26 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE = 27 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE = 28 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN = 4 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_9_ERROR_CMP_MASK = 32 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_9_ERROR_CMP_PATTERN = 33 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_ERR_CMP = 34 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_ERR_CMP = 35 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES = 36 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA0_TR1_TRACE_TRDATA_CONFIG_9_SPARE_LT = 37 ;
+
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_HI_DATA_REG_DATA = 0 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_HI_DATA_REG_DATA_LEN = 64 ;
+
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_LO_DATA_REG_DATA = 0 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_LO_DATA_REG_DATA_LEN = 32 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_LO_DATA_REG_ADDRESS = 32 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN = 10 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_LO_DATA_REG_LAST_BANK = 42 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN = 9 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID = 51 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN = 52 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_LO_DATA_REG_RUNNING = 53 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS = 54 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN = 10 ;
+
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE = 0 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE = 1 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE = 2 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN = 8 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRCTRL_CONFIG_BANK_MODE = 10 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRCTRL_CONFIG_ENH_MODE = 11 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL = 12 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN = 2 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRCTRL_CONFIG_SELECT_CONTROL = 14 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRCTRL_CONFIG_SELECT_CONTROL_LEN = 4 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRCTRL_CONFIG_RUN_HOLD_OFF = 18 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRCTRL_CONFIG_RUN_STATUS = 19 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRCTRL_CONFIG_RUN_STICKY = 20 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRCTRL_CONFIG_DISABLE_BANK_EDGE_DETECT = 21 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRCTRL_CONFIG_CONTROL_UNUSED = 22 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRCTRL_CONFIG_CONTROL_UNUSED_LEN = 6 ;
+
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 = 0 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN = 64 ;
+
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 = 0 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN = 24 ;
+
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA = 0 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN = 24 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB = 24 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN = 24 ;
+
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC = 0 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN = 24 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_3_PATTERND = 24 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN = 24 ;
+
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_4_MASKA = 0 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN = 24 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_4_MASKB = 24 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN = 24 ;
+
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_5_MASKC = 0 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN = 24 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_5_MASKD = 24 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN = 24 ;
+
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION = 0 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK = 1 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL = 2 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN = 2 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL = 4 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN = 2 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL = 6 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN = 2 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL = 8 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN = 2 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK = 10 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN = 4 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK = 14 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN = 4 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK = 18 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN = 4 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK = 22 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN = 4 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE = 26 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE = 27 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE = 28 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN = 4 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_9_ERROR_CMP_MASK = 32 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_9_ERROR_CMP_PATTERN = 33 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_ERR_CMP = 34 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_ERR_CMP = 35 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES = 36 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_TRA1_TR0_TRACE_TRDATA_CONFIG_9_SPARE_LT = 37 ;
+
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_XTRA_TRACE_MODE_DATA = 0 ;
+static const uint8_t P9N2_XBUS_PERV_C0_S0_P0_E9_XTRA_TRACE_MODE_DATA_LEN = 42 ;
+
+#endif
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